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tinygrad_repo/tinygrad/runtime/autogen/ib.py delete mode 100644 tinygrad_repo/tinygrad/runtime/support/ib.py delete mode 100644 tinygrad_repo/tinygrad/schedule/rangeify.py rename tinygrad_repo/tinygrad/uop/{decompositions.py => transcendental.py} (59%) delete mode 100644 tinygrad_repo/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/x86asm.min.js mode change 100644 => 100755 tinygrad_repo/tinygrad/viz/fetch_assets.sh rename tinygrad_repo/{extra/perfetto => tinygrad/viz}/perfetto.html (100%) mode change 100644 => 100755 tinygrad_repo/tinygrad/viz/serve.py diff --git a/tinygrad_repo/README.md b/tinygrad_repo/README.md index 274f5000e..2968535ab 100644 --- a/tinygrad_repo/README.md +++ b/tinygrad_repo/README.md @@ -39,8 +39,9 @@ Try a matmul. See how, despite the style, it is fused into one kernel with the p ```sh DEBUG=3 python3 -c "from tinygrad import Tensor; -N = 1024; a, b = Tensor.empty(N, N), Tensor.empty(N, N); -(a.reshape(N, 1, N) * b.T.reshape(1, N, N)).sum(axis=2).realize()" +N = 1024; a, b = Tensor.rand(N, N), Tensor.rand(N, N); +c = (a.reshape(N, 1, N) * b.T.reshape(1, N, N)).sum(axis=2); +print((c.numpy() - (a.numpy() @ b.numpy())).mean())" ``` And we can change `DEBUG` to `4` to see the generated code. diff --git a/tinygrad_repo/autogen_stubs.sh b/tinygrad_repo/autogen_stubs.sh old mode 100644 new mode 100755 index b60ced508..a60fc0311 --- a/tinygrad_repo/autogen_stubs.sh +++ b/tinygrad_repo/autogen_stubs.sh @@ -149,7 +149,6 @@ generate_nv() { $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h \ $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h \ $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrla06c.h \ - $NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl/ctrl90f1.h \ --clang-args="-include $NVKERN_SRC/src/common/sdk/nvidia/inc/nvtypes.h -I$NVKERN_SRC/src/common/inc -I$NVKERN_SRC/kernel-open/nvidia-uvm -I$NVKERN_SRC/kernel-open/common/inc -I$NVKERN_SRC/src/common/sdk/nvidia/inc -I$NVKERN_SRC/src/nvidia/arch/nvalloc/unix/include -I$NVKERN_SRC/src/common/sdk/nvidia/inc/ctrl" \ -o $BASE/nv_gpu.py fixup $BASE/nv_gpu.py @@ -167,7 +166,6 @@ generate_nv() { sed -n '1i\ nv_status_codes = {} /^NV_STATUS_CODE/ { s/^NV_STATUS_CODE(\([^,]*\), *\([^,]*\), *"\([^"]*\)") *.*$/\1 = \2\nnv_status_codes[\1] = "\3"/; p }' $NVKERN_SRC/src/common/sdk/nvidia/inc/nvstatuscodes.h >> $BASE/nv_gpu.py - python3 -c "import tinygrad.runtime.autogen.nv_gpu" clang2py -k cdefstum \ $NVKERN_SRC/src/nvidia/inc/kernel/gpu/fsp/kern_fsp_cot_payload.h \ @@ -182,7 +180,6 @@ nv_status_codes = {} $NVKERN_SRC/src/nvidia/inc/kernel/vgpu/rpc_headers.h \ $NVKERN_SRC/src/nvidia/inc/kernel/vgpu/rpc_global_enums.h \ $NVKERN_SRC/src/nvidia/generated/g_rpc-structures.h \ - $NVKERN_SRC/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h \ extra/nv_gpu_driver/g_rpc-message-header.h \ extra/nv_gpu_driver/gsp_static_config.h \ extra/nv_gpu_driver/vbios.h \ @@ -190,7 +187,7 @@ nv_status_codes = {} -o $BASE/nv/nv.py fixup $BASE/nv/nv.py - python3 -c "import tinygrad.runtime.autogen.nv.nv" + python3 -c "import tinygrad.runtime.autogen.nv_gpu" } generate_amd() { @@ -198,7 +195,11 @@ generate_amd() { clang2py -k cdefstum \ extra/hip_gpu_driver/sdma_registers.h \ extra/hip_gpu_driver/nvd.h \ + extra/hip_gpu_driver/kfd_pm4_headers_ai.h \ + extra/hip_gpu_driver/soc21_enum.h \ + extra/hip_gpu_driver/sdma_v6_0_0_pkt_open.h \ extra/hip_gpu_driver/gc_11_0_0_offset.h \ + extra/hip_gpu_driver/gc_10_3_0_offset.h \ extra/hip_gpu_driver/sienna_cichlid_ip_offset.h \ --clang-args="-I/opt/rocm/include -x c++" \ -o $BASE/amd_gpu.py @@ -236,21 +237,6 @@ generate_io_uring() { fixup $BASE/io_uring.py } -generate_ib() { - clang2py -k cdefstum \ - /usr/include/infiniband/verbs.h \ - /usr/include/infiniband/verbs_api.h \ - /usr/include/infiniband/ib_user_ioctl_verbs.h \ - /usr/include/rdma/ib_user_verbs.h \ - -o $BASE/ib.py - - sed -i "s\import ctypes\import ctypes, ctypes.util\g" "$BASE/ib.py" - sed -i "s\FIXME_STUB\libibverbs\g" "$BASE/ib.py" - sed -i "s\FunctionFactoryStub()\ctypes.CDLL(ctypes.util.find_library('ibverbs'), use_errno=True)\g" "$BASE/ib.py" - - fixup $BASE/ib.py -} - generate_libc() { clang2py -k cdefstum \ $(dpkg -L libc6-dev | grep sys/mman.h) \ @@ -372,6 +358,26 @@ generate_am() { -o $BASE/am/pm4_nv.py fixup $BASE/am/pm4_nv.py + clang2py -k cdefstum \ + $AMKERN_INC/vega10_enum.h \ + -o $BASE/am/vega10.py + fixup $BASE/am/vega10.py + + clang2py -k cdefstum \ + $AMKERN_INC/navi10_enum.h \ + -o $BASE/am/navi10.py + fixup $BASE/am/navi10.py + + clang2py -k cdefstum \ + $AMKERN_INC/soc21_enum.h \ + -o $BASE/am/soc21.py + fixup $BASE/am/soc21.py + + clang2py -k cdefstum \ + $AMKERN_INC/soc24_enum.h \ + -o $BASE/am/soc24.py + fixup $BASE/am/soc24.py + clang2py -k cdefstum \ extra/hip_gpu_driver/sdma_registers.h \ $AMKERN_AMD/amdgpu/vega10_sdma_pkt_open.h \ @@ -435,7 +441,7 @@ generate_libusb() { -o $BASE/libusb.py fixup $BASE/libusb.py - sed -i "s\import ctypes\import ctypes, ctypes.util, os\g" $BASE/libusb.py + sed -i "s\import ctypes\import ctypes, os\g" $BASE/libusb.py sed -i "s/FIXME_STUB/libusb/g" "$BASE/libusb.py" sed -i "s/libusb_le16_to_cpu = libusb_cpu_to_le16//g" "$BASE/libusb.py" sed -i "s/FunctionFactoryStub()/None if (lib_path:=os.getenv('LIBUSB_PATH', ctypes.util.find_library('usb-1.0'))) is None else ctypes.CDLL(lib_path)/g" "$BASE/libusb.py" @@ -456,7 +462,6 @@ elif [ "$1" == "nvdrv" ]; then generate_nvdrv elif [ "$1" == "sqtt" ]; then generate_sqtt elif [ "$1" == "qcom" ]; then generate_qcom elif [ "$1" == "io_uring" ]; then generate_io_uring -elif [ "$1" == "ib" ]; then generate_ib elif [ "$1" == "libc" ]; then generate_libc elif [ "$1" == "llvm" ]; then generate_llvm elif [ "$1" == "kgsl" ]; then generate_kgsl diff --git a/tinygrad_repo/docs/abstractions2.py b/tinygrad_repo/docs/abstractions2.py index e28037a76..c9f6a9211 100644 --- a/tinygrad_repo/docs/abstractions2.py +++ b/tinygrad_repo/docs/abstractions2.py @@ -7,30 +7,28 @@ print("******** first, the runtime ***********") -from tinygrad.runtime.ops_cpu import ClangJITCompiler, CPUDevice, CPUProgram - -cpu = CPUDevice() +from tinygrad.runtime.ops_cpu import ClangJITCompiler, MallocAllocator, CPUProgram # allocate some buffers -out = cpu.allocator.alloc(4) -a = cpu.allocator.alloc(4) -b = cpu.allocator.alloc(4) +out = MallocAllocator.alloc(4) +a = MallocAllocator.alloc(4) +b = MallocAllocator.alloc(4) # load in some values (little endian) -cpu.allocator._copyin(a, memoryview(bytearray([2,0,0,0]))) -cpu.allocator._copyin(b, memoryview(bytearray([3,0,0,0]))) +MallocAllocator._copyin(a, memoryview(bytearray([2,0,0,0]))) +MallocAllocator._copyin(b, memoryview(bytearray([3,0,0,0]))) # compile a program to a binary lib = ClangJITCompiler().compile("void add(int *out, int *a, int *b) { out[0] = a[0] + b[0]; }") # create a runtime for the program -fxn = cpu.runtime("add", lib) +fxn = CPUProgram("add", lib) # run the program fxn(out, a, b) # check the data out -print(val := cpu.allocator._as_buffer(out).cast("I").tolist()[0]) +print(val := MallocAllocator._as_buffer(out).cast("I").tolist()[0]) assert val == 5 @@ -48,7 +46,7 @@ from tinygrad.shape.shapetracker import ShapeTracker out = Buffer(DEVICE, 1, dtypes.int32).allocate() a = Buffer(DEVICE, 1, dtypes.int32).allocate().copyin(memoryview(bytearray(struct.pack("I", 2)))) b = Buffer(DEVICE, 1, dtypes.int32).allocate().copyin(memoryview(bytearray(struct.pack("I", 3)))) -# NOTE: a._buf is the same as the return from cpu.allocator.alloc +# NOTE: a._buf is the same as the return from MallocAllocator.alloc # describe the computation buf_1 = UOp(Ops.DEFINE_GLOBAL, dtypes.int32.ptr(), (), 1) @@ -80,7 +78,7 @@ print("******** third, the UOp ***********") from tinygrad.engine.realize import run_schedule from tinygrad.engine.schedule import create_schedule_with_vars -from tinygrad.schedule.kernelize import get_kernelize_map +from tinygrad.kernelize.kernelize import get_kernelize_map # allocate some values + load in values a = UOp.new_buffer(DEVICE, 1, dtypes.int32) diff --git a/tinygrad_repo/docs/developer/hcq.md b/tinygrad_repo/docs/developer/hcq.md index 783e7a75b..33655ab78 100644 --- a/tinygrad_repo/docs/developer/hcq.md +++ b/tinygrad_repo/docs/developer/hcq.md @@ -52,7 +52,7 @@ Signals are device-dependent structures used for synchronization and timing in H The following Python code demonstrates the usage of signals: ```python -signal = your_device.new_signal(value=0) +signal = your_device.signal_t() HWQueue().timestamp(signal) \ .signal(signal, value_to_fire) \ diff --git a/tinygrad_repo/docs/developer/layout.md b/tinygrad_repo/docs/developer/layout.md index 2f9a53a4b..11be1984c 100644 --- a/tinygrad_repo/docs/developer/layout.md +++ b/tinygrad_repo/docs/developer/layout.md @@ -6,11 +6,11 @@ Directories are listed in order of how they are processed. --- -## tinygrad/schedule +## tinygrad/kernelize Group UOps into kernels. -::: tinygrad.schedule.kernelize.get_kernelize_map +::: tinygrad.kernelize.kernelize.get_kernelize_map options: members: false show_labels: false @@ -18,11 +18,11 @@ Group UOps into kernels. --- -## tinygrad/codegen/opt +## tinygrad/opt Transforms the ast into an optimized ast. This is where BEAM search and heuristics live. -::: tinygrad.codegen.opt.get_optimized_ast +::: tinygrad.opt.get_optimized_ast options: members: false show_labels: false diff --git a/tinygrad_repo/docs/ramp.py b/tinygrad_repo/docs/ramp.py index 6e0fc2d4d..46499852c 100644 --- a/tinygrad_repo/docs/ramp.py +++ b/tinygrad_repo/docs/ramp.py @@ -126,7 +126,7 @@ print(t_log_grad.uop) """ void E_(float* restrict data0, float* restrict data1) { float val0 = *(data1+0); - *(data0+0) = (1/val0); + *(data0+0) = (0.6931471805599453f*(1/(val0*0.6931471805599453f))); } """ # the derivative is close to 1/3 diff --git a/tinygrad_repo/docs/runtime.md b/tinygrad_repo/docs/runtime.md index bc85d9bed..045ca91ce 100644 --- a/tinygrad_repo/docs/runtime.md +++ b/tinygrad_repo/docs/runtime.md @@ -12,7 +12,7 @@ tinygrad supports various runtimes, enabling your code to scale across a wide ra | [GPU (OpenCL)](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_gpu.py) | Accelerates computations using OpenCL on GPUs | OpenCL 2.0 compatible device | | [CPU (C Code)](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_cpu.py) | Runs on CPU using the clang compiler | `clang` compiler in system `PATH` | | [LLVM (LLVM IR)](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_llvm.py) | Runs on CPU using the LLVM compiler infrastructure | llvm libraries installed and findable | -| [WEBGPU](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_webgpu.py) | Runs on GPU using the Dawn WebGPU engine (used in Google Chrome) | Dawn library installed and findable. Download binaries [here](https://github.com/wpmed92/pydawn/releases/tag/v0.3.0). | +| [WEBGPU](https://github.com/tinygrad/tinygrad/tree/master/tinygrad/runtime/ops_webgpu.py) | Runs on GPU using the Dawn WebGPU engine (used in Google Chrome) | Dawn library installed and findable. Download binaries [here](https://github.com/wpmed92/pydawn/releases/tag/v0.1.6). | ## Interoperability diff --git a/tinygrad_repo/docs/tensor/elementwise.md b/tinygrad_repo/docs/tensor/elementwise.md index d776feef2..0bf376747 100644 --- a/tinygrad_repo/docs/tensor/elementwise.md +++ b/tinygrad_repo/docs/tensor/elementwise.md @@ -78,7 +78,6 @@ Elementwise ops operate on a per element basis. They don't change the shape of t ::: tinygrad.Tensor.minimum ::: tinygrad.Tensor.where ::: tinygrad.Tensor.copysign -::: tinygrad.Tensor.logaddexp ## Casting Ops diff --git a/tinygrad_repo/docs/tensor/movement.md b/tinygrad_repo/docs/tensor/movement.md index fa0461028..7c40bdc94 100644 --- a/tinygrad_repo/docs/tensor/movement.md +++ b/tinygrad_repo/docs/tensor/movement.md @@ -26,6 +26,5 @@ ::: tinygrad.Tensor.transpose ::: tinygrad.Tensor.flatten ::: tinygrad.Tensor.unflatten -::: tinygrad.Tensor.diag ::: tinygrad.Tensor.roll ::: tinygrad.Tensor.rearrange \ No newline at end of file diff --git a/tinygrad_repo/docs/tinybox.md b/tinygrad_repo/docs/tinybox.md index 237fe88e2..49a258a9a 100644 --- a/tinygrad_repo/docs/tinybox.md +++ b/tinygrad_repo/docs/tinybox.md @@ -6,7 +6,7 @@ If you don't have a tinybox and you want one, see [tinygrad.org](https://tinygra ## Welcome -Welcome to your tinybox! The tinybox is the universal system purpose-built for all AI infrastructure and workloads, from training to inference. The red box includes six 7900XTX GPUs, the green box includes six 4090 GPUs, and the green v2 box includes four 5090 GPUs. Whether you bought a red one or a green one, we want you to love it. +Welcome to your tinybox! The tinybox is the universal system purpose-built for all AI infrastructure and workloads, from training to inference. The red box includes six 7900XTX GPUs, and the green box includes six 4090 GPUs. Whether you bought a red one or a green one, we want you to love it. We don't have a stupid cloud service, you don't have to create a tiny account to set it up, and we aren't tracking how you use the box. We're just happy you bought one. This petaflop is your petaflop. @@ -47,8 +47,8 @@ Reboot after making these changes or restart the `displayservice.service` servic The [default tinybox image](https://github.com/tinygrad/tinyos) ships with tinygrad and PyTorch. While we develop tinygrad, the box is universal hardware. Use whatever framework you desire, run notebooks, download demos, install more things, train, inference, live, laugh, love, you aren't paying per hour for this box so the only limit is your imagination. -## Building the OS image +## tinychat -The OS image is built using `ubuntu-image` from . +Since LLMs are so popular, we ship with a built in tinygrad based chatbot using a LLaMA-3 finetune. Visit the IP (not the BMC IP) of your tinybox in a web browser on your computer or phone, and you'll find a friendly looking chat interface. This chatbot also provides an OpenAI compatible LLM API on that port, so you can script it. -After cloning, run `make green` or `make red` to build a tinybox green or tinybox red image respectively. +The conversations you have with this chatbot are between you and your tinybox. Also, the history in the web app is saved on the client, not the tinybox. diff --git a/tinygrad_repo/examples/beautiful_cifar.py b/tinygrad_repo/examples/beautiful_cifar.py index cea8262f1..66f693d9c 100644 --- a/tinygrad_repo/examples/beautiful_cifar.py +++ b/tinygrad_repo/examples/beautiful_cifar.py @@ -2,6 +2,7 @@ import time start_tm = time.perf_counter() import math from typing import Tuple, cast +import numpy as np from tinygrad import Tensor, nn, GlobalCounters, TinyJit, dtypes, Device from tinygrad.helpers import partition, trange, getenv, Context from extra.lr_scheduler import OneCycleLR @@ -149,12 +150,13 @@ if __name__ == "__main__": acc.append((out.argmax(-1) == Y).sum() / eval_batchsize) return Tensor.stack(*loss).mean() / (batchsize*loss_batchsize_scaler), Tensor.stack(*acc).mean() - Tensor.manual_seed(1337) - num_train_samples = X_train.shape[0] - + np.random.seed(1337) for epoch in range(math.ceil(hyp['misc']['train_epochs'])): + # TODO: move to tinygrad gst = time.perf_counter() - tidxs = Tensor.randperm(num_train_samples, dtype='int')[:num_steps_per_epoch*batchsize].reshape(num_steps_per_epoch, batchsize) + idxs = np.arange(X_train.shape[0]) + np.random.shuffle(idxs) + tidxs = Tensor(idxs, dtype='int')[:num_steps_per_epoch*batchsize].reshape(num_steps_per_epoch, batchsize) # NOTE: long doesn't fold train_loss:float = 0 for epoch_step in (t:=trange(num_steps_per_epoch)): st = time.perf_counter() diff --git a/tinygrad_repo/examples/beautiful_mnist.py b/tinygrad_repo/examples/beautiful_mnist.py index 0a73f5101..685a41311 100644 --- a/tinygrad_repo/examples/beautiful_mnist.py +++ b/tinygrad_repo/examples/beautiful_mnist.py @@ -1,12 +1,12 @@ # model based off https://medium.com/data-science/going-beyond-99-mnist-handwritten-digits-recognition-cfff96337392 -from typing import Callable +from typing import List, Callable from tinygrad import Tensor, TinyJit, nn, GlobalCounters from tinygrad.helpers import getenv, colored, trange from tinygrad.nn.datasets import mnist class Model: def __init__(self): - self.layers: list[Callable[[Tensor], Tensor]] = [ + self.layers: List[Callable[[Tensor], Tensor]] = [ nn.Conv2d(1, 32, 5), Tensor.relu, nn.Conv2d(32, 32, 5), Tensor.relu, nn.BatchNorm(32), Tensor.max_pool2d, @@ -21,15 +21,17 @@ if __name__ == "__main__": X_train, Y_train, X_test, Y_test = mnist(fashion=getenv("FASHION")) model = Model() - opt = (nn.optim.Adam if not getenv("MUON") else nn.optim.Muon)(nn.state.get_parameters(model)) + opt = nn.optim.Adam(nn.state.get_parameters(model)) @TinyJit @Tensor.train() def train_step() -> Tensor: opt.zero_grad() samples = Tensor.randint(getenv("BS", 512), high=X_train.shape[0]) + # TODO: this "gather" of samples is very slow. will be under 5s when this is fixed loss = model(X_train[samples]).sparse_categorical_crossentropy(Y_train[samples]).backward() - return loss.realize(*opt.schedule_step()) + opt.step() + return loss @TinyJit def get_test_acc() -> Tensor: return (model(X_test).argmax(axis=1) == Y_test).mean()*100 diff --git a/tinygrad_repo/examples/benchmark_onnx.py b/tinygrad_repo/examples/benchmark_onnx.py index ad7c1ebb1..2670ef057 100644 --- a/tinygrad_repo/examples/benchmark_onnx.py +++ b/tinygrad_repo/examples/benchmark_onnx.py @@ -1,10 +1,11 @@ -import sys, time +import sys, time, pickle from tinygrad import TinyJit, GlobalCounters, fetch, getenv -from tinygrad.frontend.onnx import OnnxRunner +from tinygrad.frontend.onnx import OnnxRunner, onnx_load from extra.onnx_helpers import get_example_inputs, validate def load_onnx_model(onnx_file): - run_onnx = OnnxRunner(onnx_file) + onnx_model = onnx_load(onnx_file) + run_onnx = OnnxRunner(onnx_model) run_onnx_jit = TinyJit(lambda **kwargs: next(iter(run_onnx({k:v.to(None) for k,v in kwargs.items()}).values())), prune=True, optimize=True) return run_onnx_jit, run_onnx.graph_inputs diff --git a/tinygrad_repo/examples/coder.py b/tinygrad_repo/examples/coder.py index 8a8d3c5b7..e6b9a5f83 100644 --- a/tinygrad_repo/examples/coder.py +++ b/tinygrad_repo/examples/coder.py @@ -4,7 +4,7 @@ sys.path.append(os.getcwd()) from io import StringIO from contextlib import redirect_stdout -from tinygrad import Tensor, nn +from tinygrad import Tensor, nn, Device, dtypes from tinygrad.helpers import Timing, colored, getenv, fetch from extra.models.llama import Transformer, convert_from_huggingface, fix_bf16 from sentencepiece import SentencePieceProcessor diff --git a/tinygrad_repo/examples/compile_tensorflow.py b/tinygrad_repo/examples/compile_tensorflow.py index 33434c831..3ad6f3119 100644 --- a/tinygrad_repo/examples/compile_tensorflow.py +++ b/tinygrad_repo/examples/compile_tensorflow.py @@ -10,7 +10,6 @@ import tensorflow as tf import tf2onnx from tinygrad.frontend.onnx import OnnxRunner from tinygrad.tensor import Tensor -from tinygrad.helpers import to_mv from extra.export_model import export_model_clang, compile_net, jit_model def get_uncompiled_model2(dataset_size=32, output_size=4): @@ -26,7 +25,7 @@ class TinyOnnx: def __init__(self, keras_model): input_signature = [tf.TensorSpec([1,32], tf.float32, name='x')] onnx_model, _ = tf2onnx.convert.from_keras(keras_model, input_signature, opset=13) - self.run_onnx = OnnxRunner(Tensor(onnx_model.SerializeToString(), device="PYTHON")) + self.run_onnx = OnnxRunner(onnx_model) def forward(self, x): return self.run_onnx({"x": x}, debug=False)['predictions'] @@ -48,8 +47,8 @@ def compile_onnx_model(onnx_model): cprog.append("void initialize(float *weights) {") weights = bytes() for name,cl in bufs_to_save.items(): - cprog.append(f"memcpy({name}, weights + {len(weights)//4}, {cl._buf.size});") - weights += bytes(to_mv(cl._buf.va_addr, cl._buf.size)) + cprog.append(f"memcpy({name}, weights + {len(weights)//4}, {len(cl._buf)*4});") + weights += bytes(cl._buf) cprog.append("}") # write the weights to disk diff --git a/tinygrad_repo/examples/handcode_opt.py b/tinygrad_repo/examples/handcode_opt.py new file mode 100644 index 000000000..f48d8a381 --- /dev/null +++ b/tinygrad_repo/examples/handcode_opt.py @@ -0,0 +1,133 @@ +from extra.models.resnet import ResNet50 +from extra.mcts_search import mcts_search +from examples.mlperf.helpers import get_mlperf_bert_model +from tinygrad import Tensor, Device, dtypes, nn +from tinygrad.opt.kernel import Kernel +from tinygrad.opt.heuristic import hand_coded_optimizations +from tinygrad.uop.ops import Ops, sym_infer +from tinygrad.device import Compiled +from tinygrad.opt.search import beam_search, bufs_from_lin +from tinygrad.helpers import DEBUG, ansilen, getenv, colored, TRACEMETA +from extra.optimization.helpers import time_linearizer + +def get_sched_resnet(): + mdl = ResNet50() + optim = (nn.optim.LARS if getenv("LARS") else nn.optim.SGD)(nn.state.get_parameters(mdl)) + BS = getenv("BS", 64) + + # run model twice to get only what changes, these are the kernels of the model + for _ in range(2): + out = mdl(Tensor.empty(BS, 3, 224, 224)) + targets = [out] + if getenv("BACKWARD"): + optim.zero_grad() + out.sparse_categorical_crossentropy(Tensor.empty(BS, dtype=dtypes.int)).backward() + targets += [x for x in optim.schedule_step()] + sched = Tensor.schedule(*targets) + print(f"schedule length {len(sched)}") + return sched + +def get_sched_bert(): + mdl = get_mlperf_bert_model() + optim = nn.optim.LAMB(nn.state.get_parameters(mdl)) + + # fake data + BS = getenv("BS", 9) + input_ids = Tensor.empty((BS, 512), dtype=dtypes.float32) + segment_ids = Tensor.empty((BS, 512), dtype=dtypes.float32) + attention_mask = Tensor.empty((BS, 512), dtype=dtypes.default_float) + masked_positions = Tensor.empty((BS, 76), dtype=dtypes.float32) + masked_lm_ids = Tensor.empty((BS, 76), dtype=dtypes.float32) + masked_lm_weights = Tensor.empty((BS, 76), dtype=dtypes.float32) + next_sentence_labels = Tensor.empty((BS, 1), dtype=dtypes.float32) + + # run model twice to get only what changes, these are the kernels of the model + for _ in range(2): + lm_logits, seq_relationship_logits = mdl(input_ids, attention_mask, masked_positions, segment_ids) + targets = [lm_logits, seq_relationship_logits] + if getenv("BACKWARD"): + optim.zero_grad() + loss = mdl.loss(lm_logits, seq_relationship_logits, masked_lm_ids, masked_lm_weights, next_sentence_labels) + # ignore grad norm and loss scaler for now + loss.backward() + targets += [x for x in optim.schedule_step()] + sched = Tensor.schedule(*targets) + print(f"schedule length {len(sched)}") + return sched + +if __name__ == "__main__": + if getenv("HALF", 1): + dtypes.default_float = dtypes.half + + # the device we are optimizing for + device: Compiled = Device[Device.DEFAULT] + if getenv("BACKWARD"): Tensor.training = True + print(f"optimizing for {Device.DEFAULT}") + + sched = globals()[f"get_sched_{getenv('MODEL', 'resnet')}"]() + sched = [x for x in sched if x.ast.op is Ops.SINK] + + # focus on one kernel + if getenv("KERNEL", -1) >= 0: sched = sched[getenv("KERNEL", -1):getenv("KERNEL", -1)+1] + + # work with the schedule + total_tm = 0 + running_gflops = 0 + usage = {} + for i,si in enumerate(sched): + if DEBUG >= 3: print(si.ast) + + rawbufs = bufs_from_lin(Kernel(si.ast)) + + # "linearize" the op into uops in different ways + lins: list[tuple[Kernel, str]] = [] + + # always try hand coded opt + lin = Kernel(si.ast, opts=device.renderer) + lin.apply_opts(hand_coded_optimizations(lin)) + lins.append((lin, "HC")) + + # maybe try tensor cores + lin = Kernel(si.ast, opts=device.renderer) + if lin.apply_tensor_cores(): + lins.append((lin, "TC")) + + # try a beam search + if beam:=getenv("BEAM"): + lin = Kernel(si.ast, opts=device.renderer) + lin = beam_search(lin, rawbufs, beam, bool(getenv("BEAM_ESTIMATE", 1))) + lins.append((lin, "BEAM")) + + # try MCTS + if mcts:=getenv("MCTS"): + lin = Kernel(si.ast, opts=device.renderer) + lin = mcts_search(lin, rawbufs, mcts) + lins.append((lin, "MCTS")) + + # benchmark the programs + choices = [] + for lin, nm in lins: + tm = time_linearizer(lin, rawbufs, allow_test_size=False, cnt=10, disable_cache=True) + ops = (prg:=lin.to_program()).estimates.ops + gflops = sym_infer(ops, {k:k.min for k in lin.ast.variables()})*1e-9/tm + choices.append((tm, gflops, lin, prg, nm)) + + sorted_choices = sorted(choices, key=lambda x: x[0]) + if DEBUG >= 1: # print all kernels + for tm, gflops, lin, prg, nm in choices: + print(f" kernel {i:2d} {lin.name+' '*(37-ansilen(lin.name))} {str(prg.global_size):18s} {str(prg.local_size):12s} takes {tm*1000:7.2f} ms, {gflops:6.0f} GFLOPS -- {colored(nm, 'green') if lin is sorted_choices[0][2] else nm}") + + tm, gflops, lin, prg, nm = sorted_choices[0] + if getenv("SRC"): + print(si.ast) + print(lin.applied_opts) + print(lin.to_program().src) + total_tm += tm + running_gflops += gflops * tm + if (key := str([str(m) for m in si.metadata])) not in usage: usage[key] = (0, 0) + usage[key] = (usage[key][0] + tm, usage[key][1] + 1) + print(f"*** {total_tm*1000:7.2f} ms : kernel {i:2d} {lin.name+' '*(37-ansilen(lin.name))} {str(prg.global_size):18s} {str(prg.local_size):12s} takes {tm*1000:7.2f} ms, {gflops:6.0f} GFLOPS {[repr(m) if TRACEMETA >= 2 else str(m) for m in si.metadata]}") + print(f"******* total {total_tm*1000:.2f} ms, {running_gflops/total_tm:6.0f} GFLOPS") + print("usage:") + for k in sorted(usage, key=lambda x: -usage[x][0])[:10]: + print(f"{usage[k][0]*1000:.2f} ms: {k} ({usage[k][1]} times)") diff --git a/tinygrad_repo/examples/hlb_cifar10.py b/tinygrad_repo/examples/hlb_cifar10.py index 8f19c8f73..378700de7 100644 --- a/tinygrad_repo/examples/hlb_cifar10.py +++ b/tinygrad_repo/examples/hlb_cifar10.py @@ -8,7 +8,7 @@ import numpy as np from typing import Optional from extra.lr_scheduler import OneCycleLR from tinygrad import nn, dtypes, Tensor, Device, GlobalCounters, TinyJit, Variable -from tinygrad.nn.state import get_state_dict +from tinygrad.nn.state import get_state_dict, get_parameters from tinygrad.nn import optim from tinygrad.helpers import Context, BEAM, WINO, getenv, colored, prod from extra.bench_log import BenchEvent, WallTimeEvent @@ -118,7 +118,7 @@ class SpeedyResNet: # hyper-parameters were exactly the same as the original repo bias_scaler = 58 hyp = { - 'seed' : 201, + 'seed' : 200, 'opt': { 'bias_lr': 1.76 * bias_scaler/512, 'non_bias_lr': 1.76 / 512, diff --git a/tinygrad_repo/examples/llama.py b/tinygrad_repo/examples/llama.py old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/llm.c/export.py b/tinygrad_repo/examples/llm.c/export.py old mode 100644 new mode 100755 index 4ab0a4fb2..9612f7e96 --- a/tinygrad_repo/examples/llm.c/export.py +++ b/tinygrad_repo/examples/llm.c/export.py @@ -1,11 +1,11 @@ #!/usr/bin/env python3 import os if "NOOPT" not in os.environ: os.environ["NOOPT"] = "1" -from tinygrad import Device, nn, Tensor, dtypes +from tinygrad import Device, nn, Tensor, dtypes, Variable Device.DEFAULT = "CPU" from train_gpt2 import GPT, GPTConfig -from tinygrad.helpers import dedup, flatten, getenv, GlobalCounters, to_function_name -from tinygrad.engine.realize import get_kernel +from tinygrad.helpers import dedup, to_function_name, flatten, getenv, GlobalCounters, ansilen, to_function_name +from tinygrad.engine.realize import get_kernel, run_schedule from tinygrad.engine.memory import memory_planner from tinygrad.uop.ops import Ops diff --git a/tinygrad_repo/examples/llm.c/train_gpt2.py b/tinygrad_repo/examples/llm.c/train_gpt2.py old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/dataloader.py b/tinygrad_repo/examples/mlperf/dataloader.py index 09fb19153..c01ab48a5 100644 --- a/tinygrad_repo/examples/mlperf/dataloader.py +++ b/tinygrad_repo/examples/mlperf/dataloader.py @@ -1,4 +1,4 @@ -import os, random, pickle, queue, struct, math, functools, hashlib, time +import os, random, pickle, queue from typing import List from pathlib import Path from multiprocessing import Queue, Process, shared_memory, connection, Lock, cpu_count @@ -6,7 +6,6 @@ from multiprocessing import Queue, Process, shared_memory, connection, Lock, cpu import numpy as np from tinygrad import dtypes, Tensor from tinygrad.helpers import getenv, prod, Context, round_up, tqdm, OSX -from tinygrad.nn.state import TensorIO ### ResNet @@ -511,274 +510,6 @@ def batch_load_retinanet(dataset, val:bool, base_dir:Path, batch_size:int=32, sh # happens with BENCHMARK set pass -# llama3 - -class BinIdxDataset: - def __init__(self, base_path:Path): - self.idx_t = Tensor(base_path.with_name(f"{base_path.name}.idx")) - self.idx = TensorIO(self.idx_t) - - # parse idx file - magic = self.idx.read(9) - assert magic == b"MMIDIDX\x00\x00", "invalid index file format" - version, = struct.unpack(" tuple[int, int]: - return int(self.pointers[idx]), int(self.sizes[idx]) - - def get(self, idx, offset:int=0, length:int|None=None): - ptr, size = self._index(idx) - if length is None: length = size - offset - ptr += offset * self.dtype.itemsize - return self.bin_t[ptr:ptr+length*self.dtype.itemsize].bitcast(self.dtype).to(None) - -# https://docs.nvidia.com/megatron-core/developer-guide/latest/api-guide/datasets.html -class GPTDataset: - def __init__(self, base_path:Path, samples:int, seqlen:int, seed:int, shuffle:bool): - self.samples, self.seqlen = samples, seqlen - self.shuffle = shuffle - self.rng = np.random.RandomState(seed) - - self.indexed_dataset = BinIdxDataset(base_path) - - # check for cache - cache_hash = hashlib.sha256(f"{samples}:{seqlen}:{seed}:{shuffle}".encode()).hexdigest() - cache_path = base_path.with_name(f"{base_path.name}.{cache_hash}.index_cache") - print(f"try loading GPTDataset from {cache_path}...") - if cache_path.exists(): - print("cache found, loading...") - with open(cache_path, "rb") as f: - self.doc_idx, self.sample_idx, self.shuffle_idx = pickle.load(f) - else: - print("cache not found, building index...") - self.doc_idx = self._build_doc_idx() - self.sample_idx = self._build_sample_idx() - self.shuffle_idx = self._build_shuffle_idx() - # save cache - with open(cache_path, "wb") as f: - pickle.dump((self.doc_idx, self.sample_idx, self.shuffle_idx), f) - - def __getitem__(self, idx): - if idx is None: - text = self._get(0) - else: - text = self._get(idx) - - return text - - def _get(self, idx): - idx = self.shuffle_idx[idx] - - doc_idx_beg, doc_idx_beg_offset = self.sample_idx[idx] - doc_idx_end, doc_idx_end_offset = self.sample_idx[idx + 1] - - doc_ids, sample_parts = [], [] - - if doc_idx_beg == doc_idx_end: - doc_ids.append(self.doc_idx[doc_idx_beg]) - - sample_parts.append( - self.indexed_dataset.get( - int(self.doc_idx[doc_idx_beg]), offset=int(doc_idx_beg_offset), length=int(doc_idx_end_offset - doc_idx_beg_offset + 1))) - else: - for i in range(doc_idx_beg, doc_idx_end + 1): - doc_ids.append(self.doc_idx[i]) - - offset = 0 if i > doc_idx_beg else doc_idx_beg_offset - length = None if i < doc_idx_end else int(doc_idx_end_offset + 1) - sample_parts.append(self.indexed_dataset.get(int(self.doc_idx[i]), offset=int(offset), length=length)) - - # concat all parts - text = Tensor.cat(*sample_parts) - - return text - - @functools.cached_property - def tokens_per_epoch(self) -> int: - return sum(self.indexed_dataset.sizes.tolist()) - - @functools.cached_property - def num_epochs(self) -> int: - # we need enough epochs to cover the requested amount of tokens - num_epochs = 1 - num_tokens = self.tokens_per_epoch - while num_tokens < self.samples * self.seqlen: - num_epochs += 1 - num_tokens += self.tokens_per_epoch - return num_epochs - - # https://github.com/NVIDIA/Megatron-LM/blob/94bd476bd840c2fd4c3ebfc7448c2af220f4832b/megatron/core/datasets/gpt_dataset.py#L558 - def _build_doc_idx(self): - print(f"building doc_idx for {self.num_epochs=}, {self.indexed_dataset.count=}") - st = time.perf_counter() - # doc_idx = np.mgrid[:self.num_epochs, :self.indexed_dataset.count][1] - doc_idx = np.arange(self.indexed_dataset.count).reshape(1, -1).repeat(self.num_epochs, axis=0).flatten() - doc_idx = doc_idx.astype(np.int32) - at = time.perf_counter() - if self.shuffle: self.rng.shuffle(doc_idx) - print(f"doc_idx built in {at - st:.3f}s, shuffled in {time.perf_counter() - at:.3f}s") - return doc_idx - - def _build_sample_idx(self): - print(f"building sample_idx for {self.samples=}, {self.seqlen=}, {self.doc_idx.shape[0]=}") - sample_idx_max = max(self.doc_idx.shape[0], self.indexed_dataset.sizes.max()) - sample_idx = np.empty((self.samples + 1, 2), dtype=np.int64 if sample_idx_max > dtypes.int32.max else np.int32) - - sample_idx_idx, doc_idx_idx, doc_offset = 0, 0, 0 - sample_idx[sample_idx_idx, 0], sample_idx[sample_idx_idx, 1] = doc_idx_idx, doc_offset - sample_idx_idx += 1 - - for _ in tqdm(range(1, self.samples + 1)): - remaining_seqlen = self.seqlen + 1 - while remaining_seqlen > 0: - doc_idx = int(self.doc_idx[doc_idx_idx]) - doc_len = int(self.indexed_dataset.sizes[doc_idx]) - doc_offset - remaining_seqlen -= doc_len - if remaining_seqlen <= 0: - doc_offset += remaining_seqlen + doc_len - 1 - remaining_seqlen = 0 - else: - if doc_idx_idx == len(self.doc_idx) - 1: - assert sample_idx_idx == self.samples - doc_idx = int(self.doc_idx[doc_idx_idx]) - doc_offset = int(self.indexed_dataset.sizes[doc_idx]) - 1 - break - doc_idx_idx += 1 - doc_offset = 0 - - sample_idx[sample_idx_idx, 0], sample_idx[sample_idx_idx, 1] = doc_idx_idx, doc_offset - sample_idx_idx += 1 - - return sample_idx - - def _build_shuffle_idx(self): - print(f"building shuffle_idx for {self.samples=}") - st = time.perf_counter() - shuffle_idx = np.arange(self.samples, dtype=np.int32) - at = time.perf_counter() - if self.shuffle: self.rng.shuffle(shuffle_idx) - print(f"shuffle_idx built in {at - st:.3f}s, shuffled in {time.perf_counter() - at:.3f}s") - return shuffle_idx - -class BlendedGPTDataset: - def __init__(self, paths:list[Path], weights:list[float], samples:int, seqlen:int, seed:int, shuffle:bool): - self.shuffle = shuffle - self.rng = np.random.RandomState(seed) - - # normalize weights - total_weight = sum(weights) - self.weights = [w / total_weight for w in weights] - - self.samples = samples - surplus = 0.005 - samples_per_blend = [math.ceil(math.ceil(self.samples * w) * (1 + surplus)) for w in self.weights] - - self.datasets = [GPTDataset(path, samples_per_blend[i], seqlen, seed + i, shuffle) for i,path in enumerate(paths)] - - # check for cache - cache_hash = hashlib.sha256(f"{samples}:{seqlen}:{seed}:{shuffle}".encode()).hexdigest() - cache_path = paths[0].with_name(f"{paths[0].name}.{cache_hash}.blend_cache") - print(f"try loading BlendedGPTDataset from {cache_path}...") - if cache_path.exists(): - print("cache found, loading...") - with open(cache_path, "rb") as f: - self.dataset_idx, self.dataset_sample_idx = pickle.load(f) - else: - print("cache not found, building index...") - self.dataset_idx, self.dataset_sample_idx = self._build_blend_idx() - # save cache - with open(cache_path, "wb") as f: - pickle.dump((self.dataset_idx, self.dataset_sample_idx), f) - - def get(self, idx:int): - tokens = self.datasets[self.dataset_idx[idx]][self.dataset_sample_idx[idx]] - return tokens - - def _build_blend_idx(self): - dataset_idx = np.zeros(self.samples, dtype=np.int16) - dataset_sample_idx = np.zeros(self.samples, dtype=np.int64) - - unspent_datasets = set(range(len(self.datasets))) - dataset_sample_counts = [0] * len(self.datasets) - - for i in tqdm(range(self.samples)): - error_argmax, error_max = 0, 0.0 - for di in unspent_datasets: - error = self.weights[di] * max(i, 1) - dataset_sample_counts[di] - if error > error_max: - error_max = error - error_argmax = di - - dataset_idx[i] = error_argmax - dataset_sample_idx[i] = dataset_sample_counts[error_argmax] - - dataset_sample_counts[error_argmax] += 1 - - return dataset_idx, dataset_sample_idx - -def batch_load_llama3(bs:int, samples:int, seqlen:int, base_dir:Path, seed:int=0, val:bool=True): - if val: - dataset = BlendedGPTDataset([ - base_dir / "validation" / "c4-validationn-91205-samples.en_text_document", - ], [ - 1.0 - ], samples, seqlen, seed, False) - else: - dataset = BlendedGPTDataset([ - base_dir / "c4-train.en_6_text_document", - base_dir / "c4-train.en_7_text_document", - ], [ - 1.0, 1.0 - ], samples, seqlen, seed, True) - - for b in range(math.ceil(samples / bs)): - batch = [] - for i in range(bs): - tokens = dataset.get(b * bs + i) - batch.append(tokens) - yield Tensor.stack(batch, dim=0) - -def batch_load_llama3_small(bs:int, samples:int, seqlen:int, base_dir:Path, seed:int=0, val:bool=True): - if val: - dataset = BlendedGPTDataset([ - base_dir / "c4-validation-91205-samples.en_text_document", - ], [ - 1.0 - ], samples, seqlen, seed, False) - else: - dataset = BlendedGPTDataset([ - base_dir / "c4-train.en_6_text_document", - ], [ - 1.0 - ], samples, seqlen, seed, True) - - for b in range(math.ceil(samples / bs)): - batch = [] - for i in range(bs): - tokens = dataset.get(b * bs + i) - batch.append(tokens) - yield Tensor.stack(batch, dim=0) - if __name__ == "__main__": def load_unet3d(val): assert not val, "validation set is not supported due to different sizes on inputs" @@ -807,18 +538,6 @@ if __name__ == "__main__": for x in batch_load_retinanet(dataset, val, base_dir): pbar.update(x[0].shape[0]) - def load_llama3(val): - bs = 24 - samples = 5760 if val else 1_200_000 * 1152 - seqlen = 8192 - - max_, min_ = 0, math.inf - for tokens in tqdm(batch_load_llama3(bs, samples, seqlen, Path(getenv("BASEDIR", "/raid/datasets/c4/")), seed=5760, val=bool(val)), total=samples//bs): - max_ = max(max_, tokens.shape[1]) - min_ = min(min_, tokens.shape[1]) - print(f"max seq length: {max_}") - print(f"min seq length: {min_}") - load_fn_name = f"load_{getenv('MODEL', 'resnet')}" if load_fn_name in globals(): globals()[load_fn_name](getenv("VAL", 1)) diff --git a/tinygrad_repo/examples/mlperf/model_eval.py b/tinygrad_repo/examples/mlperf/model_eval.py index b71c290a0..fa3ca9d7f 100644 --- a/tinygrad_repo/examples/mlperf/model_eval.py +++ b/tinygrad_repo/examples/mlperf/model_eval.py @@ -1,4 +1,4 @@ -import time, math +import time start = time.perf_counter() from pathlib import Path import numpy as np @@ -241,52 +241,6 @@ def eval_mrcnn(): evaluate_predictions_on_coco(bbox_output, iou_type='bbox') evaluate_predictions_on_coco(mask_output, iou_type='segm') -def eval_llama3(): - from extra.models.llama import Transformer - from examples.llama3 import MODEL_PARAMS, load, convert_from_huggingface - from tinygrad.helpers import tqdm - - BASEDIR = Path(getenv("BASEDIR", "/raid/datasets/c4/")) - BS = getenv("BS", 4) - SMALL = getenv("SMALL", 0) - SEQLEN = getenv("SEQLEN", 8192) - MODEL_PATH = Path(getenv("MODEL_PATH", "/raid/weights/llama31_8b/")) - - params = MODEL_PARAMS[getenv("LLAMA3_SIZE", "8B")]["args"] - params = params | {"vocab_size": 32000} if not SMALL else params - if (llama_layers:=getenv("LLAMA_LAYERS")) != 0: params['n_layers'] = llama_layers - model = Transformer(**params, max_context=SEQLEN, jit=False, disable_kv_cache=True) - - # load weights - weights = load(str(MODEL_PATH / "model.safetensors.index.json")) - if "model.embed_tokens.weight" in weights: - print("converting from huggingface format") - weights = convert_from_huggingface(weights, params["n_layers"], params["n_heads"], params["n_kv_heads"]) - - load_state_dict(model, weights, strict=False, consume=True) - - @TinyJit - def eval_step(model, tokens): - logits:Tensor = model(tokens[:, :-1], start_pos=0, temperature=math.nan) - loss = logits.sparse_categorical_crossentropy(tokens[:, 1:]) - return loss.flatten().float() - - if SMALL: - from examples.mlperf.dataloader import batch_load_llama3_small - iter = batch_load_llama3_small(BS, 5760, SEQLEN, BASEDIR, val=True) - else: - from examples.mlperf.dataloader import batch_load_llama3 - iter = batch_load_llama3(BS, 5760, SEQLEN, BASEDIR, val=True) - - losses = [] - for tokens in tqdm(iter, total=5760//BS): - GlobalCounters.reset() - losses += eval_step(model, tokens).tolist() - tqdm.write(f"loss: {np.mean(losses)}") - - log_perplexity = np.mean(losses) - print(f"Log Perplexity: {log_perplexity}") - if __name__ == "__main__": # inference only Tensor.training = False diff --git a/tinygrad_repo/examples/mlperf/model_train.py b/tinygrad_repo/examples/mlperf/model_train.py index 586e93e82..cb0d08230 100644 --- a/tinygrad_repo/examples/mlperf/model_train.py +++ b/tinygrad_repo/examples/mlperf/model_train.py @@ -5,7 +5,7 @@ import multiprocessing from tinygrad import Device, GlobalCounters, Tensor, TinyJit, dtypes from tinygrad.helpers import getenv, BEAM, WINO, round_up, diskcache_clear, FUSE_CONV_BW, Profiling from tinygrad.nn.state import get_parameters, get_state_dict, safe_load, safe_save -from tinygrad.nn.optim import LAMB, LARS, SGD, OptimizerGroup, Adam, AdamW +from tinygrad.nn.optim import LAMB, LARS, SGD, OptimizerGroup, Adam from extra.lr_scheduler import LRSchedulerGroup from examples.mlperf.helpers import get_training_state, load_training_state @@ -933,7 +933,7 @@ def train_step_bert(model, optimizer, scheduler, loss_scaler:float, GPUS, grad_a # TODO: OOM without this realize with large grad_acc Tensor.realize(*[p.grad for p in optimizer.params]) - global_norm = Tensor(0.0, dtype=dtypes.float32, device=optimizer[0].device) + global_norm = Tensor([0.0], dtype=dtypes.float32, device=optimizer[0].device) for p in optimizer.params: p.grad = p.grad / loss_scaler global_norm += p.grad.float().square().sum() @@ -1284,196 +1284,6 @@ def train_bert(): MLLOGGER.start(key=mllog_constants.BLOCK_START, value=None, metadata={"first_epoch_num": 1, "epoch_num": 1, "epoch_count": 1, "samples_count": i * GBS, "step_num": i, "first_step_num": i+1}) previous_step = i -def train_llama3(): - from extra.models.llama import Transformer - from examples.llama3 import MODEL_PARAMS - from examples.mlperf.lr_schedulers import CosineAnnealingLRWithWarmup - - config = {} - BASEDIR = config["BASEDIR"] = Path(getenv("BASEDIR", "/raid/datasets/c4/")) - BS = config["BS"] = getenv("BS", 16) - grad_acc = config["GRADIENT_ACC_STEPS"] = getenv("GRADIENT_ACC_STEPS", 1) - GBS = config["GLOBAL_BATCH_SIZE"] = BS * grad_acc - SEED = config["SEED"] = getenv("SEED", 5760) - SEQLEN = config["SEQLEN"] = getenv("SEQLEN", 8192) - TRAIN_ON_VAL = config["TRAIN_ON_VAL"] = getenv("TRAIN_ON_VAL", 0) - SMALL = config["SMALL"] = getenv("SMALL", 0) - SAMPLES = config["SAMPLES"] = getenv("SAMPLES", 5_760 if TRAIN_ON_VAL else 1_200_000 * 1152) - EVAL_FREQ = config["EVAL_FREQ"] = getenv("EVAL_FREQ", 46080) - EVAL_BS = config["EVAL_BS"] = getenv("EVAL_BS", 16) - EVAL_TARGET = config["EVAL_TARGET"] = getenv("EVAL_TARGET", 5.6) - - # LR=1e-4 TRAIN_ON_VAL=1 DEFAULT_FLOAT=bfloat16 FUSE_ARANGE=1 JITBEAM=2 OPTIM_DTYPE=bfloat16 LLAMA3_SIZE=1B WARMUP_STEPS=36 DECAY_STEPS=360 SEQLEN=512 PYTHONPATH=. AMD=1 AMD_LLVM=0 MODEL=llama3 python3 examples/mlperf/model_train.py - # trains to 7 - - opt_adamw_beta_1 = 0.9 - opt_adamw_beta_2 = 0.95 - opt_adamw_epsilon = 1e-5 - opt_adamw_weight_decay = 0.1 - - opt_gradient_clip_norm = 1.0 - opt_learning_rate_warmup_steps = getenv("WARMUP_STEPS", math.ceil(8000 * 1152 / GBS)) - opt_learning_rate_decay_steps = getenv("DECAY_STEPS", math.ceil(1_200_000 * 1152 / GBS) - opt_learning_rate_warmup_steps) - opt_base_learning_rate = getenv("LR", 8e-5 * GBS / 1152) # NOTE: cannot change for benchmark - opt_end_learning_rate = 8e-7 - - # TODO: confirm weights are in bf16 - # vocab_size from the mixtral tokenizer - params = MODEL_PARAMS[getenv("LLAMA3_SIZE", "8B")]["args"] - params = params | {"vocab_size": 32000} if not SMALL else params - if (llama_layers:=getenv("LLAMA_LAYERS")) != 0: params['n_layers'] = llama_layers - model = Transformer(**params, max_context=SEQLEN, jit=False, disable_kv_cache=True) - - if getenv("FAKEDATA"): - for v in get_parameters(model): - v = v.assign(Tensor.empty(v.shape)) - - if (DP := getenv("DP", 1)) > 1: - device = tuple(f"{Device.DEFAULT}:{i}" for i in range(DP)) - for v in get_parameters(model): - v.shard_(device, axis=None) - - if (MP := getenv("MP", 1)) > 1: - device = tuple(f"{Device.DEFAULT}:{i}" for i in range(MP)) - for k,v in get_state_dict(model).items(): - if 'scale' in k: v.shard_(device, axis=None) # from quantized - elif '.attention.wq' in k: v.shard_(device, axis=0) - elif '.attention.wk' in k: v.shard_(device, axis=0) - elif '.attention.wv' in k: v.shard_(device, axis=0) - elif '.attention.wo' in k: v.shard_(device, axis=1) - elif '.feed_forward.w1.' in k: v.shard_(device, axis=0) - elif '.feed_forward.w2.' in k: v.shard_(device, axis=1) - elif '.feed_forward.w3.' in k: v.shard_(device, axis=0) - elif 'tok_embeddings.weight' in k: v.shard_(device, axis=0) - elif 'output.weight' in k: v.shard_(device, axis=0) - else: - # attention_norm, ffn_norm, norm - v.shard_(device, axis=None) - # prevents memory spike on device 0 - v.realize() - - optim = AdamW(get_parameters(model), lr=0.0, - b1=opt_adamw_beta_1, b2=opt_adamw_beta_2, eps=opt_adamw_epsilon, weight_decay=opt_adamw_weight_decay) - scheduler = CosineAnnealingLRWithWarmup(optim, opt_base_learning_rate, opt_end_learning_rate, opt_learning_rate_warmup_steps, opt_learning_rate_decay_steps) - - @TinyJit - @Tensor.train() - def train_step(model, tokens:Tensor, grad_acc:int): - optim.zero_grad() - # grad acc - for batch in tokens.split(tokens.shape[0]//grad_acc): - if (DP := getenv("DP", 1)) > 1: - device = tuple(f"{Device.DEFAULT}:{i}" for i in range(DP)) - batch = batch.shard(device, 0) - if (MP := getenv("MP", 1)) > 1: - device = tuple(f"{Device.DEFAULT}:{i}" for i in range(MP)) - batch = batch.shard(device) - logits:Tensor = model(batch[:, :-1], start_pos=0, temperature=math.nan) - loss = logits.sparse_categorical_crossentropy(batch[:, 1:]) - loss.backward() - Tensor.realize(*[p.grad for p in optim.params]) - # L2 norm grad clip - # https://github.com/NVIDIA/NeMo/blob/3368c3fc0b4a186ab33a1d68a504315100c0b2a6/nemo/collections/nlp/modules/common/megatron/clip_grads.py#L57 - # https://docs.pytorch.org/docs/stable/generated/torch.nn.utils.clip_grad_norm_.html - if not getenv("DISABLE_GRAD_CLIP_NORM"): - total_norm = Tensor(0.0, dtype=dtypes.float32, device=optim.params[0].device) - for p in optim.params: - total_norm += p.grad.float().square().sum() - total_norm = total_norm.sqrt().contiguous() - for p in optim.params: - p.grad = p.grad * (opt_gradient_clip_norm / (total_norm + 1e-6)).clamp(max_=1.0) - - optim.step() - scheduler.step() - - lr = optim.lr - loss.realize(lr) - return loss, lr - - @TinyJit - @Tensor.train(False) - def eval_step(model, tokens:Tensor): - if (DP := getenv("DP", 1)) > 1: - device = tuple(f"{Device.DEFAULT}:{i}" for i in range(DP)) - tokens = tokens.shard(device, 0) - if (MP := getenv("MP", 1)) > 1: - device = tuple(f"{Device.DEFAULT}:{i}" for i in range(MP)) - tokens = tokens.shard(device) - logits:Tensor = model(tokens[:, :-1], start_pos=0, temperature=math.nan) - loss = logits.sparse_categorical_crossentropy(tokens[:, 1:]) - return loss.flatten().float() - - # ** data iters ** - def fake_data(bs, samples): - for _ in range(samples // bs): - yield Tensor.randint(bs, SEQLEN + 1, low=0, high=params["vocab_size"], dtype=dtypes.int32, device=Device.DEFAULT) - - def get_train_iter(): - if getenv("FAKEDATA", 0): - return fake_data(GBS, SAMPLES) - else: - if SMALL: - from examples.mlperf.dataloader import batch_load_llama3_small - return batch_load_llama3_small(GBS, SAMPLES, SEQLEN, BASEDIR, seed=SEED, val=bool(TRAIN_ON_VAL)) - else: - from examples.mlperf.dataloader import batch_load_llama3 - return batch_load_llama3(GBS, SAMPLES, SEQLEN, BASEDIR, seed=SEED, val=bool(TRAIN_ON_VAL)) - - def get_eval_iter(): - if getenv("FAKEDATA", 0): - return fake_data(EVAL_BS, 5760) - else: - if SMALL: - from examples.mlperf.dataloader import batch_load_llama3_small - return batch_load_llama3_small(EVAL_BS, 5760, SEQLEN, BASEDIR, val=True) - else: - from examples.mlperf.dataloader import batch_load_llama3 - return batch_load_llama3(EVAL_BS, 5760, SEQLEN, BASEDIR, val=True) - - iter = get_train_iter() - i, sequences_seen = 0, 0 - for tokens in tqdm(iter, total=SAMPLES//GBS): - t = time.perf_counter() - GlobalCounters.reset() - loss, lr = train_step(model, tokens, grad_acc) - loss = loss.float().item() - - tqdm.write(f"{loss:.4f} loss, {lr.item():.12f} LR, {GlobalCounters.mem_used / 1e9:.2f} GB used, {time.perf_counter()-t:.2f} s") - if (fname:=getenv("LOSS_FILE", "")): - with open(fname, "a") as f: - f.write(f"{i} {loss:.4f} {lr.item():.12f} {GlobalCounters.mem_used / 1e9:.2f}\n") - - if getenv("CKPT") and (i % 200 == 0 or i == 10): - tqdm.write("saving checkpoint") - if not os.path.exists(ckpt_dir := "./ckpts"): os.mkdir(ckpt_dir) - fn = f"{ckpt_dir}/llama3_{i}.safe" - safe_save(get_state_dict(model), fn) - - i += 1 - sequences_seen += tokens.shape[0] - - if sequences_seen % EVAL_FREQ == 0 and (i != 1 or EVAL_FREQ == 1): - tqdm.write(f"evaluating after {sequences_seen} sequences") - - # run eval - eval_losses = [] - eval_iter = get_eval_iter() - tqdm.write(f"evaluating {5760//EVAL_BS} batches of {EVAL_BS} sequences") - - for tokens in tqdm(eval_iter, total=5760//EVAL_BS): - eval_losses += eval_step(model, tokens).tolist() - log_perplexity = Tensor(eval_losses).mean().float().item() - - tqdm.write(f"eval log perplexity: {log_perplexity:.4f}") - - if log_perplexity < EVAL_TARGET: - tqdm.write(f"target achieved after {sequences_seen} sequences") - if getenv("CKPT"): - if not os.path.exists(ckpt_dir := "./ckpts"): os.mkdir(ckpt_dir) - fn = f"{ckpt_dir}/llama3.safe" - safe_save(get_state_dict(model), fn) - break - if __name__ == "__main__": multiprocessing.set_start_method('spawn') diff --git a/tinygrad_repo/examples/mlperf/scripts/setup_kits19_dataset.sh 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a/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_beam.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_beam.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_run.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_run.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_beam.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_beam.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_run.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.0/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_run.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_1xMI300X/dev_beam.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_1xMI300X/dev_beam.sh old mode 100644 new mode 100755 index 68e5fdfcd..35080c34b --- a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_1xMI300X/dev_beam.sh +++ b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_1xMI300X/dev_beam.sh @@ -4,8 +4,6 @@ export PYTHONPATH="." AMD=1 export MODEL="bert" export DEFAULT_FLOAT="HALF" GPUS=1 BS=128 EVAL_BS=128 -export IGNORE_OOB=1 - export BEAM=3 BEAM_UOPS_MAX=4000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 export IGNORE_JIT_FIRST_BEAM=1 # export BEAM_LOG_SURPASS_MAX=1 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_beam.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_beam.sh old mode 100644 new mode 100755 index cfaad1e59..6ea36f8b4 --- a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_beam.sh +++ b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_beam.sh @@ -5,8 +5,6 @@ export MODEL="bert" export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024 export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1 -export IGNORE_OOB=1 - export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0 export BASEDIR="/raid/datasets/wiki" diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_run.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_run.sh old mode 100644 new mode 100755 index 6ef7c1b99..ee43e95de --- a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_run.sh +++ b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/dev_run.sh @@ -8,8 +8,6 @@ export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024 export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1 export TRAIN_STEPS=3900 -export IGNORE_OOB=1 - export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0 export BASEDIR="/raid/datasets/wiki" diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh old mode 100644 new mode 100755 index cd2f30579..cef9f6e89 --- a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh +++ b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_8xMI300X/run_and_time.sh @@ -11,8 +11,6 @@ export DEFAULT_FLOAT="HALF" GPUS=8 BS=1024 EVAL_BS=1024 export OPT_BASE_LEARNING_RATE=0.0011 OPT_LAMB_BETA_1=0.60466 OPT_LAMB_BETA_2=0.85437 DECAY=0.1 export TRAIN_STEPS=3900 -export IGNORE_OOB=1 - export BEAM=3 BEAM_UOPS_MAX=6000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 export IGNORE_JIT_FIRST_BEAM=1 FREE_INTERMEDIATE=0 export BASEDIR="/raid/datasets/wiki" diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh old mode 100644 new mode 100755 index a2d477312..1205c210d --- a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh +++ b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_beam.sh @@ -2,9 +2,9 @@ export PYTHONPATH="." NV=1 export MODEL="bert" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=90 EVAL_BS=90 +export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 -export IGNORE_OOB=1 +export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 export IGNORE_JIT_FIRST_BEAM=1 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh old mode 100644 new mode 100755 index 436546621..f71688abf --- a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh +++ b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/dev_run.sh @@ -2,9 +2,9 @@ export PYTHONPATH="." NV=1 export MODEL="bert" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=90 EVAL_BS=90 +export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 -export IGNORE_OOB=1 +export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 export IGNORE_JIT_FIRST_BEAM=1 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh old mode 100644 new mode 100755 index 4b3b91193..52d85eeb5 --- a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh +++ b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_green/run_and_time.sh @@ -5,9 +5,9 @@ set -o pipefail # Make pipeline fail if any command fails export PYTHONPATH="." NV=1 export MODEL="bert" export SUBMISSION_PLATFORM="tinybox_green" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=90 EVAL_BS=90 +export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 -export IGNORE_OOB=1 +export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 export BEAM=8 BEAM_UOPS_MAX=10000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 export IGNORE_JIT_FIRST_BEAM=1 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh old mode 100644 new mode 100755 index 881dd247b..f99bf3020 --- a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh +++ b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_beam.sh @@ -2,9 +2,9 @@ export PYTHONPATH="." AMD=1 export MODEL="bert" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=90 EVAL_BS=90 +export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 -export IGNORE_OOB=1 +export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 export IGNORE_JIT_FIRST_BEAM=1 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh old mode 100644 new mode 100755 index 719ecd5bf..7f577c9cd --- a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh +++ b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/dev_run.sh @@ -2,9 +2,9 @@ export PYTHONPATH="." AMD=1 export MODEL="bert" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=90 EVAL_BS=90 +export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 -export IGNORE_OOB=1 +export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 export IGNORE_JIT_FIRST_BEAM=1 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh old mode 100644 new mode 100755 index 4b3030594..77c229e00 --- a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh +++ b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/bert/implementations/tinybox_red/run_and_time.sh @@ -5,9 +5,9 @@ set -o pipefail # Make pipeline fail if any command fails export PYTHONPATH="." AMD=1 export MODEL="bert" export SUBMISSION_PLATFORM="tinybox_red" -export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=90 EVAL_BS=90 +export DEFAULT_FLOAT="HALF" SUM_DTYPE="HALF" GPUS=6 BS=96 EVAL_BS=96 -export IGNORE_OOB=1 +export FUSE_ARANGE=1 FUSE_ARANGE_UINT=0 export BEAM=5 BEAM_UOPS_MAX=8000 BEAM_UPCAST_MAX=256 BEAM_LOCAL_MAX=1024 BEAM_MIN_PROGRESS=5 export IGNORE_JIT_FIRST_BEAM=1 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_beam.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/dev_run.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_green/run_and_time.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_beam.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/dev_run.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/run_and_time.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/resnet/implementations/tinybox_red/setup.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_beam.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_beam.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_run.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/dev_run.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_green/run_and_time.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_beam.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_beam.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_run.sh b/tinygrad_repo/examples/mlperf/training_submission_v5.1/tinycorp/benchmarks/retinanet/implementations/tinybox_red/dev_run.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/olmoe.py b/tinygrad_repo/examples/olmoe.py index 3f216ab8d..9789cb1ce 100644 --- a/tinygrad_repo/examples/olmoe.py +++ b/tinygrad_repo/examples/olmoe.py @@ -1,7 +1,8 @@ # https://arxiv.org/pdf/2409.02060 -import time, functools +import time import numpy as np np.set_printoptions(suppress=True, linewidth=1000) +import functools from tinygrad import Tensor, nn, Device, GlobalCounters from tinygrad.helpers import Timing, getenv from extra.models.llama import Transformer, convert_from_huggingface @@ -16,7 +17,7 @@ class MixtureFeedForward: def __call__(self, x:Tensor) -> Tensor: assert x.shape[0] == 1, "only BS=1" assert x.shape[1] == 1, "only length=1" - g = self.gate(x).softmax(-1) + g = self.gate(x).float().softmax(-1) g = g.squeeze() # (BS, length, num_experts) -> (num_experts,) probs, sel = g.topk(self.activated_experts) @@ -24,7 +25,7 @@ class MixtureFeedForward: # run MoE x_up_gate = x.dot(self.gate_proj[sel].permute(0,2,1)).silu() * x.dot(self.up_proj[sel].permute(0,2,1)) x_down = x_up_gate.dot(self.down_proj[sel].permute(0,2,1)) - return (x_down * probs.reshape(self.activated_experts, 1, 1)).sum(axis=0) + return (x_down.float() * probs.reshape(self.activated_experts, 1, 1)).sum(axis=0) # model is bf16, 1.3B active, 6.9B total # M3 Max is 400 GB/s, so 400/2.6 = ~154 tok/s diff --git a/tinygrad_repo/examples/openpilot/compile3.py b/tinygrad_repo/examples/openpilot/compile3.py index 6159bca5d..9f284ed6f 100644 --- a/tinygrad_repo/examples/openpilot/compile3.py +++ b/tinygrad_repo/examples/openpilot/compile3.py @@ -5,26 +5,29 @@ if "IMAGE" not in os.environ: os.environ["IMAGE"] = "2" if "NOLOCALS" not in os.environ: os.environ["NOLOCALS"] = "1" if "JIT_BATCH_SIZE" not in os.environ: os.environ["JIT_BATCH_SIZE"] = "0" -from tinygrad import fetch, Tensor, TinyJit, Context, GlobalCounters, Device, dtypes +from tinygrad import fetch, Tensor, TinyJit, Context, GlobalCounters, Device from tinygrad.helpers import DEBUG, getenv +from tinygrad.tensor import _from_np_dtype from tinygrad.engine.realize import CompiledRunner import onnx -from tinygrad.frontend.onnx import OnnxRunner +from onnx.helper import tensor_dtype_to_np_dtype +from tinygrad.frontend.onnx import OnnxRunner, onnx_load OPENPILOT_MODEL = sys.argv[1] if len(sys.argv) > 1 else "https://github.com/commaai/openpilot/raw/v0.9.7/selfdrive/modeld/models/supercombo.onnx" OUTPUT = sys.argv[2] if len(sys.argv) > 2 else "/tmp/openpilot.pkl" def compile(onnx_file): - run_onnx = OnnxRunner(onnx_file) + onnx_model = onnx_load(onnx_file) + run_onnx = OnnxRunner(onnx_model) print("loaded model") - input_shapes = {name: spec.shape for name, spec in run_onnx.graph_inputs.items()} - input_types = {name: spec.dtype for name, spec in run_onnx.graph_inputs.items()} + input_shapes = {inp.name:tuple(x.dim_value for x in inp.type.tensor_type.shape.dim) for inp in onnx_model.graph.input} + input_types = {inp.name: tensor_dtype_to_np_dtype(inp.type.tensor_type.elem_type) for inp in onnx_model.graph.input} # Float inputs and outputs to tinyjits for openpilot are always float32 - input_types = {k:(dtypes.float32 if v is dtypes.float16 else v) for k,v in input_types.items()} + input_types = {k:(np.float32 if v==np.float16 else v) for k,v in input_types.items()} Tensor.manual_seed(100) - new_inputs = {k:Tensor.randn(*shp, dtype=input_types[k]).mul(8).realize() for k,shp in sorted(input_shapes.items())} + new_inputs = {k:Tensor.randn(*shp, dtype=_from_np_dtype(input_types[k])).mul(8).realize() for k,shp in sorted(input_shapes.items())} new_inputs_numpy = {k:v.numpy() for k,v in new_inputs.items()} print("created tensors") @@ -54,11 +57,11 @@ def compile(onnx_file): gated_read_image_count += ei.prg.p.src.count("?read_image") print(f"{kernel_count=}, {read_image_count=}, {gated_read_image_count=}") if (allowed_kernel_count:=getenv("ALLOWED_KERNEL_COUNT", -1)) != -1: - assert kernel_count == allowed_kernel_count, f"different kernels! {kernel_count=}, {allowed_kernel_count=}" + assert kernel_count <= allowed_kernel_count, f"too many kernels! {kernel_count=}, {allowed_kernel_count=}" if (allowed_read_image:=getenv("ALLOWED_READ_IMAGE", -1)) != -1: assert read_image_count == allowed_read_image, f"different read_image! {read_image_count=}, {allowed_read_image=}" if (allowed_gated_read_image:=getenv("ALLOWED_GATED_READ_IMAGE", -1)) != -1: - assert gated_read_image_count == allowed_gated_read_image, f"different gated read_image! {gated_read_image_count=}, {allowed_gated_read_image=}" + assert gated_read_image_count <= allowed_gated_read_image, f"too many gated read_image! {gated_read_image_count=}, {allowed_gated_read_image=}" with open(OUTPUT, "wb") as f: pickle.dump(run_onnx_jit, f) diff --git a/tinygrad_repo/examples/openpilot/compile4.py b/tinygrad_repo/examples/openpilot/compile4.py index c57bd3eb7..be537f3cd 100644 --- a/tinygrad_repo/examples/openpilot/compile4.py +++ b/tinygrad_repo/examples/openpilot/compile4.py @@ -1,8 +1,8 @@ -import sys -from tinygrad import Tensor, fetch, GlobalCounters, dtypes +import sys, onnx +from tinygrad import Tensor, fetch, GlobalCounters from tinygrad.uop.ops import UOp from tinygrad.frontend.onnx import OnnxRunner -from tinygrad.schedule.kernelize import get_kernelize_map +from tinygrad.kernelize.kernelize import get_kernelize_map from tinygrad.engine.schedule import create_schedule_with_vars from tinygrad.engine.realize import run_schedule @@ -12,10 +12,12 @@ OPENPILOT_MODEL = sys.argv[1] if len(sys.argv) > 1 else "https://github.com/comm OUTPUT = sys.argv[2] if len(sys.argv) > 2 else "/tmp/openpilot.pkl" if __name__ == "__main__": + fn = fetch(OPENPILOT_MODEL) onnx_file = fetch(OPENPILOT_MODEL) - run_onnx = OnnxRunner(onnx_file) + onnx_model = onnx.load(onnx_file) + run_onnx = OnnxRunner(onnx_model) - inputs = run_onnx.get_empty_input_data("npy", dtypes.float32) + inputs = run_onnx.get_empty_input_data("npy") out: Tensor = next(iter(run_onnx({k:v.to(None) for k,v in inputs.items()}).values())).to('cpu') root = out.uop targets = [x.uop for x in inputs.values()] diff --git a/tinygrad_repo/examples/other_mnist/beautiful_mnist_torch.py b/tinygrad_repo/examples/other_mnist/beautiful_mnist_torch.py index 9fa597bae..fb3c547aa 100644 --- a/tinygrad_repo/examples/other_mnist/beautiful_mnist_torch.py +++ b/tinygrad_repo/examples/other_mnist/beautiful_mnist_torch.py @@ -27,7 +27,7 @@ class Model(nn.Module): if __name__ == "__main__": if getenv("TINY_BACKEND"): - import tinygrad.frontend.torch # noqa: F401 + import tinygrad.frontend.torch device = torch.device("tiny") else: device = torch.device({"METAL":"mps","NV":"cuda"}.get(Device.DEFAULT, "cpu")) diff --git a/tinygrad_repo/examples/sdxl.py b/tinygrad_repo/examples/sdxl.py index 24a5a6bb9..d449eb5e6 100644 --- a/tinygrad_repo/examples/sdxl.py +++ b/tinygrad_repo/examples/sdxl.py @@ -5,7 +5,7 @@ from tinygrad import Tensor, TinyJit, dtypes, GlobalCounters from tinygrad.nn import Conv2d, GroupNorm -from tinygrad.nn.state import safe_load, load_state_dict +from tinygrad.nn.state import safe_load, load_state_dict, get_state_dict from tinygrad.helpers import fetch, trange, colored, Timing from extra.models.clip import Embedder, FrozenClosedClipEmbedder, FrozenOpenClipEmbedder from extra.models.unet import UNetModel, Upsample, Downsample, timestep_embedding diff --git a/tinygrad_repo/examples/stunning_mnist.py b/tinygrad_repo/examples/stunning_mnist.py index 9f308c0cb..66c5aa82d 100644 --- a/tinygrad_repo/examples/stunning_mnist.py +++ b/tinygrad_repo/examples/stunning_mnist.py @@ -7,7 +7,7 @@ from examples.beautiful_mnist import Model from tinygrad import Tensor, nn, getenv, GlobalCounters, Variable from tinygrad.nn.datasets import mnist -from tinygrad.helpers import trange +from tinygrad.helpers import trange, DEBUG # STEPS=70 python3 examples/stunning_mnist.py # NOTE: it's broken with STACK=1, why? diff --git a/tinygrad_repo/examples/tinychat/assets/cdn.jsdelivr.net/npm/purecss@3.0.0/build/base-min.css b/tinygrad_repo/examples/tinychat/assets/cdn.jsdelivr.net/npm/purecss@3.0.0/build/base-min.css deleted file mode 100644 index df4fbc055..000000000 --- a/tinygrad_repo/examples/tinychat/assets/cdn.jsdelivr.net/npm/purecss@3.0.0/build/base-min.css +++ /dev/null @@ -1,11 +0,0 @@ -/*! -Pure v3.0.0 -Copyright 2013 Yahoo! -Licensed under the BSD License. -https://github.com/pure-css/pure/blob/master/LICENSE -*/ -/*! -normalize.css v | MIT License | https://necolas.github.io/normalize.css/ -Copyright (c) Nicolas Gallagher and Jonathan Neal -*/ -/*! normalize.css v8.0.1 | MIT License | github.com/necolas/normalize.css */html{line-height:1.15;-webkit-text-size-adjust:100%}body{margin:0}main{display:block}h1{font-size:2em;margin:.67em 0}hr{box-sizing:content-box;height:0;overflow:visible}pre{font-family:monospace,monospace;font-size:1em}a{background-color:transparent}abbr[title]{border-bottom:none;text-decoration:underline;-webkit-text-decoration:underline dotted;text-decoration:underline dotted}b,strong{font-weight:bolder}code,kbd,samp{font-family:monospace,monospace;font-size:1em}small{font-size:80%}sub,sup{font-size:75%;line-height:0;position:relative;vertical-align:baseline}sub{bottom:-.25em}sup{top:-.5em}img{border-style:none}button,input,optgroup,select,textarea{font-family:inherit;font-size:100%;line-height:1.15;margin:0}button,input{overflow:visible}button,select{text-transform:none}[type=button],[type=reset],[type=submit],button{-webkit-appearance:button}[type=button]::-moz-focus-inner,[type=reset]::-moz-focus-inner,[type=submit]::-moz-focus-inner,button::-moz-focus-inner{border-style:none;padding:0}[type=button]:-moz-focusring,[type=reset]:-moz-focusring,[type=submit]:-moz-focusring,button:-moz-focusring{outline:1px dotted ButtonText}fieldset{padding:.35em .75em .625em}legend{box-sizing:border-box;color:inherit;display:table;max-width:100%;padding:0;white-space:normal}progress{vertical-align:baseline}textarea{overflow:auto}[type=checkbox],[type=radio]{box-sizing:border-box;padding:0}[type=number]::-webkit-inner-spin-button,[type=number]::-webkit-outer-spin-button{height:auto}[type=search]{-webkit-appearance:textfield;outline-offset:-2px}[type=search]::-webkit-search-decoration{-webkit-appearance:none}::-webkit-file-upload-button{-webkit-appearance:button;font:inherit}details{display:block}summary{display:list-item}template{display:none}[hidden]{display:none}html{font-family:sans-serif}.hidden,[hidden]{display:none!important}.pure-img{max-width:100%;height:auto;display:block} \ No newline at end of file diff --git a/tinygrad_repo/examples/tinychat/fetch_assets.sh b/tinygrad_repo/examples/tinychat/fetch_assets.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/tinychat/tinychat-browser/compile_wasm.sh b/tinygrad_repo/examples/tinychat/tinychat-browser/compile_wasm.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/tinychat/tinychat-browser/make_tiktoken_js.sh b/tinygrad_repo/examples/tinychat/tinychat-browser/make_tiktoken_js.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/torch_cuda_kernel.py b/tinygrad_repo/examples/torch_cuda_kernel.py index 9786872fd..5d1706efe 100644 --- a/tinygrad_repo/examples/torch_cuda_kernel.py +++ b/tinygrad_repo/examples/torch_cuda_kernel.py @@ -2,9 +2,10 @@ #!POPCORN gpu A100 # not a stable API, but works -import torch +import torch, functools from tinygrad import Tensor, TinyJit, Device -from tinygrad.helpers import Context, OSX +from tinygrad.engine.realize import CompiledRunner +from tinygrad.helpers import get_single_element, Context, OSX from tinygrad.dtype import _from_torch_dtype @TinyJit diff --git a/tinygrad_repo/examples/train_resnet.py b/tinygrad_repo/examples/train_resnet.py old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/transformer.py b/tinygrad_repo/examples/transformer.py old mode 100644 new mode 100755 diff --git a/tinygrad_repo/examples/vgg7.py b/tinygrad_repo/examples/vgg7.py index 1b01fd1aa..a4a5835e5 100644 --- a/tinygrad_repo/examples/vgg7.py +++ b/tinygrad_repo/examples/vgg7.py @@ -2,6 +2,8 @@ import sys import random import json import numpy +from pathlib import Path +from PIL import Image from tinygrad.tensor import Tensor from tinygrad.nn.optim import SGD from tinygrad.nn.state import safe_save, safe_load, get_state_dict, load_state_dict diff --git a/tinygrad_repo/examples/whisper.py b/tinygrad_repo/examples/whisper.py index 5cce861a0..dc2832a4a 100644 --- a/tinygrad_repo/examples/whisper.py +++ b/tinygrad_repo/examples/whisper.py @@ -5,7 +5,7 @@ from typing import Optional, Union, Literal, List from tinygrad import Tensor, TinyJit, Variable, nn from tinygrad.nn.state import torch_load, load_state_dict -from tinygrad.helpers import getenv, fetch +from tinygrad.helpers import getenv, DEBUG, fetch import numpy as np import librosa @@ -321,7 +321,7 @@ if __name__ == "__main__": log_spec = prep_audio(total.reshape(1, -1), model.batch_size, truncate=True) encoded_audio = model.encoder.encode(Tensor(log_spec)) # pass the previously inferred tokens as 'prefix' - https://github.com/openai/whisper/discussions/117#discussioncomment-3727051 - out = model.decoder(Tensor([lst]), 0, encoded_audio).realize() + out = model.decoder(Tensor([lst]), 0, encoded_audio, streaming=True).realize() idx = int(out[0,-1].argmax().numpy().item()) lst.append(idx) dec = enc.decode(lst) diff --git a/tinygrad_repo/examples/yolov3.py b/tinygrad_repo/examples/yolov3.py old mode 100644 new mode 100755 index f6d688263..49a2adb0f --- a/tinygrad_repo/examples/yolov3.py +++ b/tinygrad_repo/examples/yolov3.py @@ -71,8 +71,8 @@ def bbox_iou(box1, box2): # get the coordinates of the intersection rectangle inter_rect_x1 = np.maximum(b1_x1, b2_x1) inter_rect_y1 = np.maximum(b1_y1, b2_y1) - inter_rect_x2 = np.minimum(b1_x2, b2_x2) - inter_rect_y2 = np.minimum(b1_y2, b2_y2) + inter_rect_x2 = np.maximum(b1_x2, b2_x2) + inter_rect_y2 = np.maximum(b1_y2, b2_y2) #Intersection area inter_area = np.clip(inter_rect_x2 - inter_rect_x1 + 1, 0, 99999) * np.clip(inter_rect_y2 - inter_rect_y1 + 1, 0, 99999) #Union Area @@ -297,13 +297,13 @@ class Darknet: # Get the number of weights of batchnorm num_bn_biases = math.prod(bn.bias.shape) # Load weights - bn_biases = Tensor(weights[ptr:ptr + num_bn_biases].astype(np.float32)) + bn_biases = Tensor(weights[ptr:ptr + num_bn_biases]) ptr += num_bn_biases - bn_weights = Tensor(weights[ptr:ptr+num_bn_biases].astype(np.float32)) + bn_weights = Tensor(weights[ptr:ptr+num_bn_biases]) ptr += num_bn_biases - bn_running_mean = Tensor(weights[ptr:ptr+num_bn_biases].astype(np.float32)) + bn_running_mean = Tensor(weights[ptr:ptr+num_bn_biases]) ptr += num_bn_biases - bn_running_var = Tensor(weights[ptr:ptr+num_bn_biases].astype(np.float32)) + bn_running_var = Tensor(weights[ptr:ptr+num_bn_biases]) ptr += num_bn_biases # Cast the loaded weights into dims of model weights bn_biases = bn_biases.reshape(shape=tuple(bn.bias.shape)) @@ -319,7 +319,7 @@ class Darknet: # load biases of the conv layer num_biases = math.prod(conv.bias.shape) # Load weights - conv_biases = Tensor(weights[ptr: ptr+num_biases].astype(np.float32)) + conv_biases = Tensor(weights[ptr: ptr+num_biases]) ptr += num_biases # Reshape conv_biases = conv_biases.reshape(shape=tuple(conv.bias.shape)) @@ -327,7 +327,7 @@ class Darknet: conv.bias = conv_biases # Load weighys for conv layers num_weights = math.prod(conv.weight.shape) - conv_weights = Tensor(weights[ptr:ptr+num_weights].astype(np.float32)) + conv_weights = Tensor(weights[ptr:ptr+num_weights]) ptr += num_weights conv_weights = conv_weights.reshape(shape=tuple(conv.weight.shape)) conv.weight = conv_weights @@ -371,7 +371,7 @@ class Darknet: if __name__ == "__main__": model = Darknet(fetch('https://raw.githubusercontent.com/pjreddie/darknet/master/cfg/yolov3.cfg').read_bytes()) print("Loading weights file (237MB). This might take a while…") - model.load_weights('https://github.com/shadiakiki1986/yolov3.weights/releases/download/3.0.1/yolov3.weights') + model.load_weights('https://pjreddie.com/media/files/yolov3.weights') if len(sys.argv) > 1: url = sys.argv[1] else: diff --git a/tinygrad_repo/examples/yolov8-onnx.py b/tinygrad_repo/examples/yolov8-onnx.py index bc3d50ab9..5f76ab7e4 100644 --- a/tinygrad_repo/examples/yolov8-onnx.py +++ b/tinygrad_repo/examples/yolov8-onnx.py @@ -2,12 +2,14 @@ import os from ultralytics import YOLO from pathlib import Path -from tinygrad.frontend.onnx import OnnxRunner +from tinygrad.frontend.onnx import OnnxRunner, onnx_load from extra.onnx_helpers import get_example_inputs +from tinygrad.tensor import Tensor os.chdir("/tmp") if not Path("yolov8n-seg.onnx").is_file(): model = YOLO("yolov8n-seg.pt") model.export(format="onnx", imgsz=[480,640]) -run_onnx = OnnxRunner("yolov8n-seg.onnx") +onnx_model = onnx_load(open("yolov8n-seg.onnx", "rb")) +run_onnx = OnnxRunner(onnx_model) run_onnx(get_example_inputs(run_onnx.graph_inputs), debug=True) diff --git a/tinygrad_repo/examples/yolov8.py b/tinygrad_repo/examples/yolov8.py index 4888ea0fb..1a9035a21 100644 --- a/tinygrad_repo/examples/yolov8.py +++ b/tinygrad_repo/examples/yolov8.py @@ -1,5 +1,7 @@ from tinygrad.nn import Conv2d, BatchNorm2d from tinygrad.tensor import Tensor +from tinygrad.device import is_dtype_supported +from tinygrad import dtypes import numpy as np from itertools import chain from pathlib import Path diff --git a/tinygrad_repo/extra/amdpci/am_smi.py b/tinygrad_repo/extra/amdpci/am_smi.py old mode 100644 new mode 100755 index a6f5bb89c..31f29f267 --- a/tinygrad_repo/extra/amdpci/am_smi.py +++ b/tinygrad_repo/extra/amdpci/am_smi.py @@ -8,6 +8,8 @@ from tinygrad.runtime.support.hcq import MMIOInterface from tinygrad.runtime.support.am.amdev import AMDev, AMMemoryManager, AMPageTableEntry from tinygrad.runtime.support.am.ip import AM_SOC, AM_GMC, AM_IH, AM_PSP, AM_SMU, AM_GFX, AM_SDMA +AM_VERSION = 0xA0000005 + def bold(s): return f"\033[1m{s}\033[0m" def trim(s:str, length:int) -> str: @@ -71,12 +73,21 @@ class AMSMI(AMDev): self._run_discovery() self._build_regs() - if self.reg("regSCRATCH_REG7").read() != AMDev.Version: + if self.reg("regSCRATCH_REG7").read() != AM_VERSION: raise Exception(f"Unsupported AM version: {self.reg('regSCRATCH_REG7').read():x}") - self.is_booting = True - self.init_sw(smi_dev=True) + self.is_booting, self.smi_dev = True, True self.partial_boot = True # do not init anything + self.mm = AMMemoryManager(self, self.vram_size) + + # Initialize IP blocks + self.soc:AM_SOC = AM_SOC(self) + self.gmc:AM_GMC = AM_GMC(self) + self.ih:AM_IH = AM_IH(self) + self.psp:AM_PSP = AM_PSP(self) + self.smu:AM_SMU = AM_SMU(self) + + for ip in [self.soc, self.gmc, self.ih, self.psp, self.smu]: ip.init_sw() def read_pci_state(self): with open(f"/sys/bus/pci/devices/{self.pcibus}/power_state", "r") as f: return f.read().strip().rstrip() @@ -125,7 +136,7 @@ class SMICtx: if d.pci_state == "D0": d._init_from_d0() os.system('clear') - if d.pci_state == "D0" and d.reg("regSCRATCH_REG7").read() != AMDev.Version: + if d.pci_state == "D0" and d.reg("regSCRATCH_REG7").read() != AM_VERSION: self.devs.remove(d) self.opened_pcidevs.remove(d.pcibus) os.system('clear') @@ -284,8 +295,8 @@ if __name__ == "__main__": while True: try: pid = subprocess.check_output(['sudo', 'lsof', '-t', dev]).decode('utf-8').split('\n')[0] except subprocess.CalledProcessError: break - if stopped_pids[pid] > 0: time.sleep(0.1) - if stopped_pids[pid] == 64: + if stopped_pids[pid] > 0: time.sleep(0.5) + if stopped_pids[pid] == 10: print(f"{dev[8:-5]}: can't stop process {pid}, exitting") exit(1) diff --git a/tinygrad_repo/extra/amdpci/proclogs.py b/tinygrad_repo/extra/amdpci/proclogs.py index 18c616d2b..6019366ec 100644 --- a/tinygrad_repo/extra/amdpci/proclogs.py +++ b/tinygrad_repo/extra/amdpci/proclogs.py @@ -1,16 +1,6 @@ -import re, ctypes, sys, importlib +import re, ctypes, sys -from tinygrad.runtime.support.am.amdev import AMDev, AMRegister -class AMDFake(AMDev): - def __init__(self, devfmt, vram, doorbell, mmio, dma_regions=None): - self.devfmt, self.vram, self.doorbell64, self.mmio, self.dma_regions = devfmt, vram, doorbell, mmio, dma_regions - self._run_discovery() - self._build_regs() - -amdev = importlib.import_module("tinygrad.runtime.support.am.amdev") -amdev.AMDev = AMDFake - -from tinygrad.runtime.ops_amd import PCIIface +from tinygrad.runtime.autogen.am import am, mp_11_0, mp_13_0_0, nbio_4_3_0, mmhub_3_0_0, gc_11_0_0, osssys_6_0_0 def parse_amdgpu_logs(log_content, register_names=None): register_map = register_names @@ -33,11 +23,16 @@ def parse_amdgpu_logs(log_content, register_names=None): return processed_log def main(): + regs_offset = {13: {0: [3072, 37784576]}, 28: {0: [93184, 37754880], 1: [201327616, 201461760], 2: [209716224, 209850368], 3: [218104832, 218238976], 4: [226493440, 226627584], 5: [234882048, 235016192], 6: [243270656, 243404800]}, 21: {0: [28672, 12582912, 37795840, 130023424, 306184192], 1: [201326592, 201463808, 201465856, 204210176, 204472320], 2: [209715200, 209852416, 209854464, 212598784, 212860928], 3: [218103808, 218241024, 218243072, 220987392, 221249536], 4: [226492416, 226629632, 226631680, 229376000, 229638144], 5: [234881024, 235018240, 235020288, 237764608, 238026752], 6: [243269632, 243406848, 243408896, 246153216, 246415360]}, 22: {0: [18, 192, 13504, 36864, 37764096]}, 1: {0: [4704, 40960, 114688, 37760000]}, 2: {0: [3872, 37790720]}, 11: {0: [70656, 38103040]}, 12: {0: [106496, 37783552]}, 15: {0: [90112, 14417920, 14680064, 14942208, 38009856]}, 16: {0: [90112, 14417920, 14680064, 14942208, 38009856]}, 14: {0: [0, 20, 3360, 66560, 37859328, 67371008]}, 26: {0: [0, 20, 3360, 66560, 37859328, 67371008]}, 23: {0: [4256, 37789696]}, 33: {0: [0, 20, 3360, 66560, 37859328, 67371008]}, 25: {0: []}, 3: {0: [4704, 40960, 114688, 37760000]}, 4: {0: [4704, 40960, 114688, 37760000]}, 24: {0: [92160, 92672, 37752832, 54788096]}, 27: {0: [91648, 37751808], 1: [201339904, 201458176], 2: [209728512, 209846784], 3: [218117120, 218235392], 4: [226505728, 226624000], 5: [234894336, 235012608], 6: [243282944, 243401216]}, 29: {0: [201342976, 201344000, 205520896, 205537280], 1: [209731584, 209732608, 213909504, 213925888], 2: [218120192, 218121216, 222298112, 222314496], 3: [226508800, 226509824, 230686720, 230703104], 4: [234897408, 234898432, 239075328, 239091712], 5: [243286016, 243287040, 247463936, 247480320]}, 17: {0: [30720, 32256], 1: [31488, 73728]}} + reg_names = {} - dev = PCIIface(None, 0) - for x, y in dev.dev_impl.__dict__.items(): - if isinstance(y, AMRegister): - for inst, addr in y.addr.items(): reg_names[addr] = f"{x}, xcc={inst}" + def _prepare_registers(modules): + for base, m in modules: + for k, regval in m.__dict__.items(): + if k.startswith("reg") and not k.endswith("_BASE_IDX") and (base_idx:=getattr(m, f"{k}_BASE_IDX", None)) is not None: + reg_names[regs_offset[am.__dict__.get(f"{base}_HWIP")][0][base_idx] + regval] = k + + _prepare_registers([("MP0", mp_13_0_0), ("NBIO", nbio_4_3_0), ("MMHUB", mmhub_3_0_0), ("GC", gc_11_0_0), ("OSSSYS", osssys_6_0_0)]) with open(sys.argv[1], 'r') as f: log_content = log_content_them = f.read() diff --git a/tinygrad_repo/extra/amdpci/setup_python_cap.sh b/tinygrad_repo/extra/amdpci/setup_python_cap.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/extra/amdpci/setup_vfio.sh b/tinygrad_repo/extra/amdpci/setup_vfio.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/extra/assembly/assembly.py b/tinygrad_repo/extra/assembly/assembly.py index ca19c4ff2..688f2b9aa 100644 --- a/tinygrad_repo/extra/assembly/assembly.py +++ b/tinygrad_repo/extra/assembly/assembly.py @@ -1,5 +1,5 @@ from typing import Tuple, List, NamedTuple, Any, Dict, Optional, Union, DefaultDict, cast -from tinygrad.codegen.opt.kernel import Ops, MemOp, UOp +from tinygrad.opt.kernel import Ops, MemOp, UOp from tinygrad.uop.ops import BinaryOps, UnaryOps from tinygrad.dtype import DType, dtypes from tinygrad.helpers import DEBUG @@ -156,7 +156,7 @@ def uops_to_asmstyle(lang, function_name:str, uops:List[UOp]): lang.ins.append(AssemblyInstruction(Ops.ALU, out, [tmp], args)) else: lang.ins.append(AssemblyInstruction(Ops.ALU, out, [lang.tor[x] for x in vin], args)) - elif uop == Ops.DEFINE_REG: + elif uop == Ops.DEFINE_ACC: reg = lang.newreg(u, dtype=dtype) lang.ins.append(AssemblyInstruction(Ops.LOAD, reg, [], args)) elif uop == Ops.SPECIAL: diff --git a/tinygrad_repo/extra/assembly/assembly_arm64.py b/tinygrad_repo/extra/assembly/assembly_arm64.py index c5a3ad49b..1b61b8e5a 100644 --- a/tinygrad_repo/extra/assembly/assembly_arm64.py +++ b/tinygrad_repo/extra/assembly/assembly_arm64.py @@ -3,7 +3,7 @@ from platform import system from typing import Tuple, Dict, List, Optional from tinygrad import dtypes from tinygrad.uop.ops import BinaryOps, UnaryOps, TernaryOps -from tinygrad.codegen.opt.kernel import Ops, UOp +from tinygrad.opt.kernel import Ops, UOp from tinygrad.helpers import CI from tinygrad.codegen.assembly import uops_to_asmstyle, AssemblyLanguage diff --git a/tinygrad_repo/extra/assembly/assembly_ptx.py b/tinygrad_repo/extra/assembly/assembly_ptx.py index 9a9593eb2..5535d4ccf 100644 --- a/tinygrad_repo/extra/assembly/assembly_ptx.py +++ b/tinygrad_repo/extra/assembly/assembly_ptx.py @@ -1,7 +1,7 @@ from typing import List import struct from tinygrad.codegen.assembly import uops_to_asmstyle, AssemblyLanguage -from tinygrad.codegen.opt.kernel import Ops, UOp +from tinygrad.opt.kernel import Ops, UOp from tinygrad import dtypes from tinygrad.uop.ops import BinaryOps, UnaryOps, TernaryOps from tinygrad.runtime.ops_cuda import arch diff --git a/tinygrad_repo/extra/assembly/assembly_rdna.py b/tinygrad_repo/extra/assembly/assembly_rdna.py index 0f5ab01ec..d57ba5245 100644 --- a/tinygrad_repo/extra/assembly/assembly_rdna.py +++ b/tinygrad_repo/extra/assembly/assembly_rdna.py @@ -2,7 +2,7 @@ import yaml from typing import Tuple, Set, Dict from tinygrad import dtypes from tinygrad.codegen.assembly import AssemblyCodegen, Register -from tinygrad.codegen.opt.kernel import Ops +from tinygrad.opt.kernel import Ops from tinygrad.uop.ops import BinaryOps, UnaryOps, TernaryOps from tinygrad.runtime.ops_gpu import ROCM_LLVM_PATH diff --git a/tinygrad_repo/extra/assembly/rocm/rocm_clone.sh b/tinygrad_repo/extra/assembly/rocm/rocm_clone.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/extra/assembly/rocm/rocm_from_scratch.sh b/tinygrad_repo/extra/assembly/rocm/rocm_from_scratch.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/extra/assembly/rocm/rocm_setup.sh b/tinygrad_repo/extra/assembly/rocm/rocm_setup.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/extra/assembly/rocm/sniffer/build.sh b/tinygrad_repo/extra/assembly/rocm/sniffer/build.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/extra/backends/rdna.py b/tinygrad_repo/extra/backends/rdna.py index 32e9b8d9e..1e26e9778 100644 --- a/tinygrad_repo/extra/backends/rdna.py +++ b/tinygrad_repo/extra/backends/rdna.py @@ -15,8 +15,8 @@ def uops_to_rdna(function_name:str, uops:UOpGraph) -> str: u.vin = tuple(n if x == o else x for x in u.vin) # pointer indexing if u.uop in {UOps.LOAD, UOps.STORE} and u.vin[0].dtype.itemsize > 1: - val = UOp(UOps.CONST, dtypes.int, tuple(), arg=u.vin[0].dtype.itemsize, insert_at=uops.uops.index(u)) - ptr = UOp(UOps.ALU, dtypes.int, (u.vin[1], val), arg=BinaryOps.MUL, insert_at=uops.uops.index(u)) + val = UOp(UOps.CONST, dtypes.int, tuple(), arg=u.vin[0].dtype.itemsize, insert_before=uops.uops.index(u)) + ptr = UOp(UOps.ALU, dtypes.int, (u.vin[1], val), arg=BinaryOps.MUL, insert_before=uops.uops.index(u)) u.vin = (u.vin[0], ptr) + u.vin[2:] #uops.print() diff --git a/tinygrad_repo/extra/backends/triton.py b/tinygrad_repo/extra/backends/triton.py index 646c19d60..f65334162 100644 --- a/tinygrad_repo/extra/backends/triton.py +++ b/tinygrad_repo/extra/backends/triton.py @@ -2,7 +2,7 @@ from typing import Dict, List, Final, Callable, DefaultDict from collections import defaultdict from tinygrad.uop.ops import UnaryOps, BinaryOps, TernaryOps, Op from tinygrad.helpers import DType, PtrDType, dtypes, ImageDType, DEBUG, getenv -from tinygrad.codegen.opt.kernel import UOp, Ops +from tinygrad.opt.kernel import UOp, Ops from triton.compiler import compile as triton_compile import linecache import math @@ -88,7 +88,7 @@ def uops_to_triton(function_name:str, uops:List[UOp]): assert dtype is not None if len(vin) == 2: kk(f"{ssa(u, 'val')} = {render_cast(f'tl.load({r[vin[0]]} + { fill_dims_for_idx(r[vin[1]], dims)}, mask = {render_valid(valid)})', dtype)}") else: kk(f"{ssa(u, 'val')} = {render_cast(f'tl.where({r[vin[2]]}, tl.load({r[vin[0]]}+{fill_dims_for_idx(r[vin[1]],dims)} , mask={render_valid(valid+[r[vin[2]]])}), 0.0)', dtype)}") - elif uop == Ops.DEFINE_REG: kk(f"{ssa(u, 'acc')} = {define_scalar(local_size, dtype, args).replace('//', '/')}") + elif uop == Ops.DEFINE_ACC: kk(f"{ssa(u, 'acc')} = {define_scalar(local_size, dtype, args).replace('//', '/')}") elif uop == Ops.CONST: r[u] = define_scalar([], dtype, args) elif uop == Ops.ASSIGN: kk(f"{r[vin[0]]} = {r[vin[1]].replace('//', '/')}") diff --git a/tinygrad_repo/extra/datasets/fake_imagenet_from_mnist.py b/tinygrad_repo/extra/datasets/fake_imagenet_from_mnist.py old mode 100644 new mode 100755 diff --git a/tinygrad_repo/extra/datasets/sops.gz b/tinygrad_repo/extra/datasets/sops.gz index 9b61b87ad23ea7a4c57b2ed46c2d25efd045614d..1362cbe16d2df001ba49b7380167eb9c76ba9f06 100644 GIT binary patch literal 1182286 zcmV)VK(D_aiwFogkU3}o19NY1a{%nUTazTWu_pMwe`K0wQEj*fux5JbrCJhgc{@Bh z63^2ZM?;CS;Spt|I8*!YH-N~D01&u10zgD$RW-?CS5;)D!{KoF_4EJu>Ywkv`sXk2 z|NXNs|KH(%{_Fqy=l8$7|KC6T{eKSM{rtDzeEHKqz8`-1`7ghD_aFDi{`l259|6z( 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zA>-Ftj^f(KZESnXF(*f}+VhB}gf1ueD(@8>;{Fz4n z*%_1&j3?Q0e{{Z{)!WD~k5bZUjTM6Y*0X?|?oic$A+@_(JI8HkAW?CK6+!svDne93FZz4E;DP8tW}|96osNO0pK! zDn=A?NbNIYd2Rcpo?4WdfPO4eHL9Wktf4qa+N~S5lH8LI#IcJ&qD6=C28BT>3=`F%=hD$%#u^n5tv bDfYREIl local store +# * why is TC=3 broken for 4096x4096? +# * write syntactic sugar for these local additions + use it in tensor core kernel.py N = 4096 +LN = 16 run_count = 5 -if __name__ == "__main__": - ast = (Tensor.empty(N, N)@Tensor.empty(N, N)).schedule()[-1].ast - prg = get_program(ast, Device.default.renderer) - - if getenv("ASM") == 1: - src = (pathlib.Path(__file__).parent / "amd_seb" / "kernel8_batched_gmem.s").read_text() - prgfast = replace(prg, name="kernel", src=src, global_size=[N//128, N//128, 1], local_size=[128, 1, 1]) - elif getenv("ASM") == -1: - src = (pathlib.Path(__file__).parent / "amd_seb" / "kernel3_registers.cpp").read_text() - prgfast = replace(prg, name="kernel3_registers", src=src, global_size=[N//128, N//128, 1], local_size=[256, 1, 1]) - elif getenv("ASM") == -2: - src = (pathlib.Path(__file__).parent / "amd_seb" / "kernel4_gmem_df.cpp").read_text() - prgfast = replace(prg, name="kernel4_gmem_db", src=src, global_size=[N//128, N//128, 1], local_size=[256, 1, 1]) +from tinygrad.shape.shapetracker import ShapeTracker, View +def transform_load(ctx:tuple[Kernel, set[UOp]], x:UOp): + if x.src[0].op is not Ops.DEFINE_GLOBAL: return None + if x in ctx[1]: return None + print(ctx[0].colored_shape()) + ctx[1].add(x) + input_st: ShapeTracker = x.src[1].arg + #strides = input_st.real_strides() + #strides = (0,0)+strides[2:] + if input_st.real_strides()[2] == 0: + perm = (0,1,5,3,4,2) + strides = (0,0,LN*4,4,0,0,1,0) + elif input_st.real_strides()[3] == 0: + perm = (0,1,2,5,4,3) + strides = (0,0,LN*4,4,0,0,0,1) else: - src = (pathlib.Path(__file__).parent / "amd_seb" / "kernel5_lds_optim.cpp").read_text() - prgfast = replace(prg, name="kernel5_lds_optim", src=src, global_size=[N//128, N//128, 1], local_size=[128, 1, 1]) - runner = CompiledRunner(prgfast) + return None + if len(input_st.shape) == 8: + local_st = ShapeTracker(views=(View.create((1,1,LN,LN,1,1,4,4), strides),)) + perm = perm + (6,7) + else: + local_st = ShapeTracker(views=(View.create((1,1,LN,LN,1,1)),)) + #local_st = ShapeTracker(views=(View.create((1,1,LN,LN,1,1)),)) + load_st = local_st.permute(perm) + input_st = input_st.permute(perm) + lcl = UOp(Ops.DEFINE_LOCAL, x.dtype.ptr(local_st.real_size(), local=True), (), f"temp{x.src[0].arg}") + global_load = x.replace(src=(x.src[0], input_st.to_uop())) + ret = UOp(Ops.STORE, src=(lcl, local_st.to_uop(), global_load)) + return UOp(Ops.LOAD, x.dtype, src=(lcl, load_st.to_uop(), ret)) - a = Tensor.randn(N, N).realize() - b = Tensor.randn(N, N).realize() - c = Tensor.zeros(N, N).contiguous().realize() +local_loads_pm = PatternMatcher([ + (UPat(Ops.LOAD, name="x"), transform_load), +]) - GlobalCounters.reset() - with Context(DEBUG=2): - for _ in range(run_count): tc = (a@b).realize() +def ast_transform(k, ast): + #return ast + ast = graph_rewrite(ast, local_loads_pm, ctx=(k, set())) + #ast = ast.replace(arg=replace(ast.arg, upcasted=0)) + print(ast) + return ast - GlobalCounters.reset() - ei = ExecItem(runner, [a.uop.buffer, b.uop.buffer, c.uop.buffer]) +if __name__ == "__main__": + rng = np.random.default_rng() + a = Tensor(na:=rng.random((4096, 4096), dtype=np.float32)).realize() + b = Tensor(nb:=rng.random((4096, 4096), dtype=np.float32)).realize() + c = a @ b + si = c.schedule()[-1] + k = Kernel(si.ast, opts=Device[Device.DEFAULT].renderer) + #opts = [Opt(op=OptOps.LOCAL, axis=1, arg=16), + # Opt(op=OptOps.LOCAL, axis=0, arg=8), + # Opt(op=OptOps.UPCAST, axis=2, arg=4), + # Opt(op=OptOps.UPCAST, axis=1, arg=4), + # Opt(op=OptOps.UPCAST, axis=0, arg=2)] + #opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), + # Opt(op=OptOps.UPCAST, axis=0, arg=4), + # Opt(op=OptOps.LOCAL, axis=1, arg=8), + # Opt(op=OptOps.LOCAL, axis=0, arg=4)] + opts = [Opt(op=OptOps.UNROLL, axis=0, arg=LN), + #Opt(op=OptOps.UPCAST, axis=0, arg=4), + #Opt(op=OptOps.UPCAST, axis=1, arg=4), + Opt(op=OptOps.LOCAL, axis=1, arg=LN), + Opt(op=OptOps.LOCAL, axis=0, arg=LN)] + k.apply_opts(opts) + prg = k.to_program(ast_transform=ast_transform) + if getenv("FAST", 1) and Device.DEFAULT == "AMD": + #src = (pathlib.Path(__file__).parent / "fp32_sgemm_amd" / "src" / "kernel8_batched_gmem.s").read_text() + src = (pathlib.Path(__file__).parent / "kernel8_batched_gmem.s").read_text() + prg = replace(prg, src=src, global_size=[N//128, N//128, 1], local_size=[128, 1, 1]) + print(prg.global_size, prg.local_size) + ei = ExecItem(CompiledRunner(prg), [x.ensure_allocated() for x in si.bufs], si.metadata) with Context(DEBUG=2): for _ in range(run_count): ei.run(wait=True) - print(f"custom {(c-tc).square().mean().item()}") + nc = c.numpy() + np.testing.assert_allclose(na@nb, nc, rtol=1e-5) diff --git a/tinygrad_repo/extra/gemm/amd_seb/kernel3_registers.cpp b/tinygrad_repo/extra/gemm/amd_seb/kernel3_registers.cpp deleted file mode 100644 index f4cdf21e2..000000000 --- a/tinygrad_repo/extra/gemm/amd_seb/kernel3_registers.cpp +++ /dev/null @@ -1,143 +0,0 @@ -typedef long unsigned int size_t; -extern "C" __attribute__((device, const)) size_t __ockl_get_local_id(unsigned int); -extern "C" __attribute__((device, const)) size_t __ockl_get_group_id(unsigned int); -struct Dim3 { size_t x, y, z; }; -#define __shared__ __attribute__((shared, aligned(16))) -__attribute__((device)) inline void __syncthreads() { - __builtin_amdgcn_fence(__ATOMIC_RELEASE, "workgroup"); - __builtin_amdgcn_s_barrier(); - __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "workgroup"); -} - -#define BLOCK_SIZE 256 -extern "C" __attribute__((global)) void __attribute__((amdgpu_flat_work_group_size(1, BLOCK_SIZE))) -kernel3_registers(float *a, float *b, float *c) -{ - constexpr int N = 4096; - constexpr float alpha = 1.0; - constexpr float beta = 0.0; - - const Dim3 blockIdx{ __ockl_get_group_id(0), __ockl_get_group_id(1), __ockl_get_group_id(2) }; - const Dim3 threadIdx{ __ockl_get_local_id(0), __ockl_get_local_id(1), __ockl_get_local_id(2) }; - - // Block Tile size - constexpr int BN = 128; - constexpr int BM = 128; - // Number of Row or column we read per batch - constexpr int BK = 8; - - // Thread Tile size - constexpr int TN = 4; - constexpr int TM = 4; - - constexpr int nbWaves = BLOCK_SIZE / 32; - // Wave Tile size - constexpr int WN = 64; - constexpr int WM = BN * BM / nbWaves / WN; - - // Number of wave on X & Y axis in the Block tile - constexpr int nbWaveX = BN / WN; - constexpr int nbWaveY = BM / WM; - - const int waveIndex = threadIdx.x / 32; - const int waveIdx = waveIndex % nbWaveX; - const int waveIdy = waveIndex / nbWaveX; - const int indexInWave = threadIdx.x % 32; - - // A wave is a block of 8x4 of the output matrix - constexpr int nbThreadXPerWave = 8; - constexpr int nbThreadYPerWave = 4; - - // Thread coordinates in Wave - const int idxInWave = indexInWave % nbThreadXPerWave; - const int idyInWave = indexInWave / nbThreadXPerWave; - - constexpr int nbIterWaveN = WN / (nbThreadXPerWave * TN); - constexpr int nbIterWaveM = WM / (nbThreadYPerWave * TM); - - // Wave Sub-tile size - constexpr int SUBWN = WN / nbIterWaveN; - constexpr int SUBWM = WM / nbIterWaveM; - - // Thread mapping to read BKxBN block from A - int rAIdx = threadIdx.x % BK; - int rAIdy = threadIdx.x / BK; - // Thread mapping to read BNxBK block from B - int rBIdx = threadIdx.x % BN; - int rBIdy = threadIdx.x / BN; - - constexpr int strideReadB = BLOCK_SIZE / BN; - constexpr int strideReadA = BLOCK_SIZE / BK; - constexpr int nbReadsB = BN * BK / BLOCK_SIZE; - constexpr int nbReadsA = BM * BK / BLOCK_SIZE; - - float A_col[nbIterWaveM * TM]; - float B_row[nbIterWaveN * TN]; - - __shared__ float As[BK][BM]; - __shared__ float Bs[BK][BN]; - - float c_regs[TM * nbIterWaveM * TN * nbIterWaveN] = {0.0f}; - - // Iteration over BK blocks. - for (int kId = 0; kId < N; kId += BK) { - __syncthreads(); - - // We populate the Shared Memory with Ks row and columns - for (int i = 0; i < nbReadsB; i++) { - int index_x = BN * blockIdx.x + rBIdx; - int index_y = rBIdy + i * strideReadB + kId; - Bs[index_y % BK][index_x % BN] = b[N * index_y + index_x]; - } - - for (int i = 0; i < nbReadsA; i++) { - int index_x = rAIdx + kId; - int index_y = BM * blockIdx.y + rAIdy + i * strideReadA; - As[(index_x % BK)][(index_y % BM)] = a[N * index_y + index_x]; - } - - __syncthreads(); - for (int k = 0; k < BK; k++) { - // we cache A & B for the entire Wave tile - for (int iterWave = 0; iterWave < nbIterWaveN; iterWave++) { - for (int i = 0; i < TN; i++) { - int index = waveIdx * WN + iterWave * SUBWN + TN * idxInWave + i; - B_row[iterWave * TN + i] = Bs[k][index]; - } - } - - for (int iterWave = 0; iterWave < nbIterWaveM; iterWave++) { - for (int i = 0; i < TM; i++) { - int index = waveIdy * WM + iterWave * SUBWM + TM * idyInWave + i; - A_col[iterWave * TM + i] = As[k][index]; - } - } - - // we accumulate to C_regs - for (int iterWaveM = 0; iterWaveM < nbIterWaveM; iterWaveM++) { - for (int iterWaveN = 0; iterWaveN < nbIterWaveN; iterWaveN++) { - for (int yt = 0; yt < TM; yt++) { - for (int xt = 0; xt < TN; xt++) { - const int x = iterWaveN * TN + xt; - const int y = iterWaveM * TM + yt; - c_regs[y * TN * nbIterWaveN + x] += A_col[y] * B_row[x]; - } - } - } - } - } - } - - for (int iterWaveM = 0; iterWaveM < nbIterWaveM; iterWaveM++) { - for (int iterWaveN = 0; iterWaveN < nbIterWaveN; iterWaveN++) { - int xOut = blockIdx.x * BN + waveIdx * WN + iterWaveN * SUBWN + TN * idxInWave; - int yOut = blockIdx.y * BM + waveIdy * WM + iterWaveM * SUBWM + TM * idyInWave; - for (int yt = 0; yt < TM; yt++) { - for (int xt = 0; xt < TN; xt++) { - int indexC = N * (yOut + yt) + xOut + xt; - c[indexC] = beta * c[indexC] + alpha * c_regs[TN * nbIterWaveN * (iterWaveM * TM + yt) + (iterWaveN * TN + xt)]; - } - } - } - } -} diff --git a/tinygrad_repo/extra/gemm/amd_seb/kernel4_gmem_df.cpp b/tinygrad_repo/extra/gemm/amd_seb/kernel4_gmem_df.cpp deleted file mode 100644 index 1d1265431..000000000 --- a/tinygrad_repo/extra/gemm/amd_seb/kernel4_gmem_df.cpp +++ /dev/null @@ -1,172 +0,0 @@ -typedef long unsigned int size_t; -extern "C" __attribute__((device, const)) size_t __ockl_get_local_id(unsigned int); -extern "C" __attribute__((device, const)) size_t __ockl_get_group_id(unsigned int); -struct Dim3 { size_t x, y, z; }; -#define __shared__ __attribute__((shared, aligned(16))) -__attribute__((device)) inline void __syncthreads() { - __builtin_amdgcn_fence(__ATOMIC_RELEASE, "workgroup"); - __builtin_amdgcn_s_barrier(); - __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "workgroup"); -} - -#define BLOCK_SIZE 256 -extern "C" __attribute__((global)) void __attribute__((amdgpu_flat_work_group_size(1, BLOCK_SIZE))) -kernel4_gmem_db(float *a, float *b, float *c) -{ - constexpr int N = 4096; - constexpr float alpha = 1.0; - constexpr float beta = 0.0; - - const Dim3 blockIdx{ __ockl_get_group_id(0), __ockl_get_group_id(1), __ockl_get_group_id(2) }; - const Dim3 threadIdx{ __ockl_get_local_id(0), __ockl_get_local_id(1), __ockl_get_local_id(2) }; - - // Block Tile size - constexpr int BN = 128; - constexpr int BM = 128; - // Number of Row or column we read per batch - constexpr int BK = 8; - - // Thread Tile size - constexpr int TN = 4; - constexpr int TM = 4; - - constexpr int nbWaves = BLOCK_SIZE / 32; - // Wave Tile size - constexpr int WN = 64; - constexpr int WM = BN * BM / nbWaves / WN; - - // Number of wave on X & Y axis in the Block tile - constexpr int nbWaveX = BN / WN; - constexpr int nbWaveY = BM / WM; - - const int waveIndex = threadIdx.x / 32; - const int waveIdx = waveIndex % nbWaveX; - const int waveIdy = waveIndex / nbWaveX; - const int indexInWave = threadIdx.x % 32; - - // A wave is a block of 8x4 of the output matrix - constexpr int nbThreadXPerWave = 8; - constexpr int nbThreadYPerWave = 4; - - // Thread coordinates in Wave - const int idxInWave = indexInWave % nbThreadXPerWave; - const int idyInWave = indexInWave / nbThreadXPerWave; - - constexpr int nbIterWaveN = WN / (nbThreadXPerWave * TN); - constexpr int nbIterWaveM = WM / (nbThreadYPerWave * TM); - - // Wave Sub-tile size - constexpr int SUBWN = WN / nbIterWaveN; - constexpr int SUBWM = WM / nbIterWaveM; - - // Thread mapping to read BKxBN block from A - int rAIdx = threadIdx.x % BK; - int rAIdy = threadIdx.x / BK; - // Thread mapping to read BNxBK block from B - int rBIdx = threadIdx.x % BN; - int rBIdy = threadIdx.x / BN; - - constexpr int strideReadB = BLOCK_SIZE / BN; - constexpr int strideReadA = BLOCK_SIZE / BK; - constexpr int nbReadsB = BN * BK / BLOCK_SIZE; - constexpr int nbReadsA = BM * BK / BLOCK_SIZE; - - float A_col[nbIterWaveM * TM]; - float B_row[nbIterWaveN * TN]; - - __shared__ float As[BK][BM]; - __shared__ float Bs[BK][BN]; - - float c_regs[TM * nbIterWaveM * TN * nbIterWaveN] = {0.0f}; - - for (int i = 0; i < nbReadsB; i++) { - int index_x = BN * blockIdx.x + rBIdx; - int index_y = rBIdy + i * strideReadB; - Bs[index_y % BK][index_x % BN] = b[N * index_y + index_x]; - } - - for (int i = 0; i < nbReadsA; i++) { - int index_x = rAIdx; - int index_y = BM * blockIdx.y + rAIdy + i * strideReadA; - As[(index_x % BK)][(index_y % BM)] = a[N * index_y + index_x]; - } - - __syncthreads(); - // Iteration over BK blocks. - for (int kId = 0; kId < N; kId += BK) { - float regA[nbReadsA]; - float regB[nbReadsB]; - if (kId < N - BK) { - // We populate the Shared Memory with Ks row and columns - for (int i = 0; i < nbReadsB; i++) { - int index_x = BN * blockIdx.x + rBIdx; - int index_y = rBIdy + i * strideReadB + kId + BK; - regB[i] = b[N * index_y + index_x]; - } - - for (int i = 0; i < nbReadsA; i++) { - int index_x = rAIdx + kId + BK; - int index_y = BM * blockIdx.y + rAIdy + i * strideReadA; - regA[i] = a[N * index_y + index_x]; - } - } - - for (int k = 0; k < BK; k++) { - // we cache A & B for the entire Wave tile - for (int iterWave = 0; iterWave < nbIterWaveN; iterWave++) { - for (int i = 0; i < TN; i++) { - int index = waveIdx * WN + iterWave * SUBWN + TN * idxInWave + i; - B_row[iterWave * TN + i] = Bs[k][index]; - } - } - - for (int iterWave = 0; iterWave < nbIterWaveM; iterWave++) { - for (int i = 0; i < TM; i++) { - int index = waveIdy * WM + iterWave * SUBWM + TM * idyInWave + i; - A_col[iterWave * TM + i] = As[k][index]; - } - } - - // we accumulate to C_regs - for (int iterWaveM = 0; iterWaveM < nbIterWaveM; iterWaveM++) { - for (int iterWaveN = 0; iterWaveN < nbIterWaveN; iterWaveN++) { - for (int yt = 0; yt < TM; yt++) { - for (int xt = 0; xt < TN; xt++) { - const int x = iterWaveN * TN + xt; - const int y = iterWaveM * TM + yt; - c_regs[y * TN * nbIterWaveN + x] += A_col[y] * B_row[x]; - } - } - } - } - } - __syncthreads(); - if (kId < N - BK) { - for (int i = 0; i < nbReadsB; i++) { - int index_x = BN * blockIdx.x + rBIdx; - int index_y = rBIdy + i * strideReadB + kId + BK; - Bs[index_y % BK][index_x % BN] = regB[i]; // row - } - - for (int i = 0; i < nbReadsA; i++) { - int index_x = rAIdx + kId + BK; - int index_y = BM * blockIdx.y + rAIdy + i * strideReadA; - As[(index_x % BK)][(index_y % BM)] = regA[i]; - } - __syncthreads(); - } - } - - for (int iterWaveM = 0; iterWaveM < nbIterWaveM; iterWaveM++) { - for (int iterWaveN = 0; iterWaveN < nbIterWaveN; iterWaveN++) { - int xOut = blockIdx.x * BN + waveIdx * WN + iterWaveN * SUBWN + TN * idxInWave; - int yOut = blockIdx.y * BM + waveIdy * WM + iterWaveM * SUBWM + TM * idyInWave; - for (int yt = 0; yt < TM; yt++) { - for (int xt = 0; xt < TN; xt++) { - int indexC = N * (yOut + yt) + xOut + xt; - c[indexC] = beta * c[indexC] + alpha * c_regs[TN * nbIterWaveN * (iterWaveM * TM + yt) + (iterWaveN * TN + xt)]; - } - } - } - } -} \ No newline at end of file diff --git a/tinygrad_repo/extra/gemm/amd_seb/kernel5_lds_optim.cpp b/tinygrad_repo/extra/gemm/amd_seb/kernel5_lds_optim.cpp deleted file mode 100644 index bf5b34e9c..000000000 --- a/tinygrad_repo/extra/gemm/amd_seb/kernel5_lds_optim.cpp +++ /dev/null @@ -1,172 +0,0 @@ -typedef long unsigned int size_t; -extern "C" __attribute__((device, const)) size_t __ockl_get_local_id(unsigned int); -extern "C" __attribute__((device, const)) size_t __ockl_get_group_id(unsigned int); -struct Dim3 { size_t x, y, z; }; -#define __shared__ __attribute__((shared, aligned(16))) -__attribute__((device)) inline void __syncthreads() { - __builtin_amdgcn_fence(__ATOMIC_RELEASE, "workgroup"); - __builtin_amdgcn_s_barrier(); - __builtin_amdgcn_fence(__ATOMIC_ACQUIRE, "workgroup"); -} - -#define BLOCK_SIZE 128 -extern "C" __attribute__((global)) void __attribute__((amdgpu_flat_work_group_size(1, BLOCK_SIZE))) -kernel5_lds_optim(float *a, float *b, float *c) -{ - constexpr int N = 4096; - constexpr float alpha = 1.0; - constexpr float beta = 0.0; - - const Dim3 blockIdx{ __ockl_get_group_id(0), __ockl_get_group_id(1), __ockl_get_group_id(2) }; - const Dim3 threadIdx{ __ockl_get_local_id(0), __ockl_get_local_id(1), __ockl_get_local_id(2) }; - - // Block Tile size - constexpr int BN = 128; - constexpr int BM = 128; - // Number of Row or column we read per batch - constexpr int BK = 8; - - // Thread Tile size - constexpr int TN = 4; - constexpr int TM = 4; - - constexpr int nbWaves = BLOCK_SIZE / 32; - // Wave Tile size - constexpr int WN = 128; - constexpr int WM = BN * BM / nbWaves / WN; - - // Number of wave on X & Y axis in the Block tile - constexpr int nbWaveX = BN / WN; - constexpr int nbWaveY = BM / WM; - - const int waveIndex = threadIdx.x / 32; - const int waveIdx = waveIndex % nbWaveX; - const int waveIdy = waveIndex / nbWaveX; - const int indexInWave = threadIdx.x % 32; - - // A wave is a block of 8x4 of the output matrix - constexpr int nbThreadXPerWave = 8; - constexpr int nbThreadYPerWave = 4; - - // Thread coordinates in Wave - const int idxInWave = indexInWave % nbThreadXPerWave; - const int idyInWave = indexInWave / nbThreadXPerWave; - - constexpr int nbIterWaveN = WN / (nbThreadXPerWave * TN); - constexpr int nbIterWaveM = WM / (nbThreadYPerWave * TM); - - // Wave Sub-tile size - constexpr int SUBWN = WN / nbIterWaveN; - constexpr int SUBWM = WM / nbIterWaveM; - - // Thread mapping to read BKxBN block from A - int rAIdx = threadIdx.x % BK; - int rAIdy = threadIdx.x / BK; - // Thread mapping to read BNxBK block from B - int rBIdx = threadIdx.x % BN; - int rBIdy = threadIdx.x / BN; - - constexpr int strideReadB = BLOCK_SIZE / BN; - constexpr int strideReadA = BLOCK_SIZE / BK; - constexpr int nbReadsB = BN * BK / BLOCK_SIZE; - constexpr int nbReadsA = BM * BK / BLOCK_SIZE; - - float A_col[nbIterWaveM * TM]; - float B_row[nbIterWaveN * TN]; - - __shared__ float As[BK][BM+4]; // 4 padding to avoid bank conflicts - __shared__ float Bs[BK][BN]; - - float c_regs[TM * nbIterWaveM * TN * nbIterWaveN] = {0.0f}; - - // initial copy into shared memory - for (int i = 0; i < nbReadsB; i++) { - int index_x = BN * blockIdx.x + rBIdx; - int index_y = rBIdy + i * strideReadB; - Bs[index_y % BK][index_x % BN] = b[N * index_y + index_x]; - } - for (int i = 0; i < nbReadsA; i++) { - int index_x = rAIdx; - int index_y = BM * blockIdx.y + rAIdy + i * strideReadA; - As[(index_x % BK)][(index_y % BM)] = a[N * index_y + index_x]; - } - - __syncthreads(); - // Iteration over BK blocks. - for (int kId = 0; kId < N; kId += BK) { - float regA[nbReadsA]; - float regB[nbReadsB]; - if (kId < N - BK) { - // We populate the Shared Memory with Ks row and columns - for (int i = 0; i < nbReadsB; i++) { - int index_x = BN * blockIdx.x + rBIdx; - int index_y = rBIdy + i * strideReadB + kId + BK; - regB[i] = b[N * index_y + index_x]; - } - - for (int i = 0; i < nbReadsA; i++) { - int index_x = rAIdx + kId + BK; - int index_y = BM * blockIdx.y + rAIdy + i * strideReadA; - regA[i] = a[N * index_y + index_x]; - } - } - - for (int k = 0; k < BK; k++) { - // we cache A & B for the entire Wave tile - for (int iterWave = 0; iterWave < nbIterWaveN; iterWave++) { - for (int i = 0; i < TN; i++) { - int index = waveIdx * WN + iterWave * SUBWN + TN * idxInWave + i; - B_row[iterWave * TN + i] = Bs[k][index]; - } - } - - for (int iterWave = 0; iterWave < nbIterWaveM; iterWave++) { - for (int i = 0; i < TM; i++) { - int index = waveIdy * WM + iterWave * SUBWM + TM * idyInWave + i; - A_col[iterWave * TM + i] = As[k][index]; - } - } - - // we accumulate to C_regs - for (int iterWaveM = 0; iterWaveM < nbIterWaveM; iterWaveM++) { - for (int iterWaveN = 0; iterWaveN < nbIterWaveN; iterWaveN++) { - for (int yt = 0; yt < TM; yt++) { - for (int xt = 0; xt < TN; xt++) { - const int x = iterWaveN * TN + xt; - const int y = iterWaveM * TM + yt; - c_regs[y * TN * nbIterWaveN + x] += A_col[y] * B_row[x]; - } - } - } - } - } - __syncthreads(); - if (kId < N - BK) { - for (int i = 0; i < nbReadsB; i++) { - int index_x = BN * blockIdx.x + rBIdx; - int index_y = rBIdy + i * strideReadB + kId + BK; - Bs[index_y % BK][index_x % BN] = regB[i]; // row - } - - for (int i = 0; i < nbReadsA; i++) { - int index_x = rAIdx + kId + BK; - int index_y = BM * blockIdx.y + rAIdy + i * strideReadA; - As[(index_x % BK)][(index_y % BM)] = regA[i]; - } - __syncthreads(); - } - } - - for (int iterWaveM = 0; iterWaveM < nbIterWaveM; iterWaveM++) { - for (int iterWaveN = 0; iterWaveN < nbIterWaveN; iterWaveN++) { - int xOut = blockIdx.x * BN + waveIdx * WN + iterWaveN * SUBWN + TN * idxInWave; - int yOut = blockIdx.y * BM + waveIdy * WM + iterWaveM * SUBWM + TM * idyInWave; - for (int yt = 0; yt < TM; yt++) { - for (int xt = 0; xt < TN; xt++) { - int indexC = N * (yOut + yt) + xOut + xt; - c[indexC] = beta * c[indexC] + alpha * c_regs[TN * nbIterWaveN * (iterWaveM * TM + yt) + (iterWaveN * TN + xt)]; - } - } - } - } -} diff --git a/tinygrad_repo/extra/gemm/amd_uop_matmul.py b/tinygrad_repo/extra/gemm/amd_uop_matmul.py deleted file mode 100644 index 78dbf81a1..000000000 --- a/tinygrad_repo/extra/gemm/amd_uop_matmul.py +++ /dev/null @@ -1,355 +0,0 @@ -from tinygrad import Tensor, Device, Context, GlobalCounters, dtypes -from tinygrad.uop.ops import UOp, Ops, KernelInfo, graph_rewrite, AxisType, PatternMatcher, UPat -from tinygrad.engine.realize import CompiledRunner, ExecItem, get_program -from tinygrad.dtype import AddrSpace -from tinygrad.helpers import getenv, colored, prod, unwrap -from tinygrad.shape.shapetracker import ShapeTracker, View -from tinygrad.shape.view import strides_for_shape -from tinygrad.codegen.opt.kernel import axis_colors, Opt, OptOps -from tinygrad.codegen.opt.swizzler import merge_views, view_left - -def to_colored(full_shape, axis_types): return '_'.join([colored(str(s), axis_colors[at]) for s,at in zip(full_shape, axis_types)]) - -N = 4096 -run_count = 5 - -BN = 128 -BM = 128 -BK = 8 - -TN = 4 -TM = 4 - -# NOTE: this is from testgrad -# change reduceop axes and input ShapeTrackers, view gets replaced with a reshape. -# src->r->view --> src->view->r -def swizzle_reduceop(src:UOp, r:UOp, view:UOp): - if r.tag is not None: return None - # confirm the input is in order - # TODO: replace this with a UOp that allows for nothing else then remove this - permute = tuple(i for i in range(len(src.shape)) if i not in r.axis_arg)+r.axis_arg - assert permute == tuple(range(len(permute))), f"reduce axis must already be in order, {permute} isn't" - - # append the reduce shape to each of the views - prshape = prod(rshape:=src.shape[-len(r.axis_arg):]) - rstrides = strides_for_shape(rshape) - nv = [View.create(v.shape+rshape, tuple(x*prshape for x in v.strides)+rstrides, v.offset*prshape, - v.mask+tuple((0,s) for s in rshape) if v.mask is not None else None) for v in unwrap(view.st).views] - - # no reshape required with shrinking REDUCE_AXIS - return UOp(Ops.REDUCE_AXIS, r.dtype, (src.view(ShapeTracker(tuple(nv))),), - (r.arg[0], tuple(range(len(view.shape), len(view.shape) + len(r.axis_arg))))) - -pm = PatternMatcher([ - (UPat(Ops.VIEW, src=(UPat(Ops.REDUCE_AXIS, src=(UPat.var("src"),), name="r"),), name="view"), swizzle_reduceop), -]) - -def rangeify_kernel3(): - a = Tensor.empty(N,N) - b = Tensor.empty(N,N) - c = a@b - #c = c.reshape((32,2,16,4,32,2,16,4)).contiguous() - with Context(RANGEIFY=1): - sink = c.schedule()[-1].ast - #print(sink) - - opts = [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.LOCAL, 0, 16), Opt(OptOps.UPCAST, 0, 2)] - opts += [Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.LOCAL, 1, 16), Opt(OptOps.UPCAST, 1, 2)] - opts += [Opt(OptOps.UNROLL, 0, 8)] - - return sink.replace(arg=KernelInfo(opts_to_apply=tuple(opts))) - -def top_spec_kernel3(): - a = Tensor.empty(N,N) - b = Tensor.empty(N,N) - c = a@b - sink = c.schedule()[-1].ast - L = 16 - sink = sink.reshape((N//L, L, N//L, L)) #.lift({0:UOp.range(N//BM, 0), 2:UOp.range(N//BN, 1)}) - sink = graph_rewrite(sink, view_left+pm) - axis_types = (AxisType.GLOBAL, AxisType.LOCAL, AxisType.GLOBAL, AxisType.LOCAL, AxisType.REDUCE) - return sink.replace(arg=KernelInfo(name="top_"+to_colored(sink.full_shape, axis_types), axis_types=axis_types)) - -def hl_spec_kernel3(): - nbIterWaveM = 2 - nbIterWaveN = 2 - - # define buffers - # TODO: remove these views once the defines have a shape - a = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(N*N), arg=1).view(ShapeTracker.from_shape((N,N))) - b = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(N*N), arg=2).view(ShapeTracker.from_shape((N,N))).permute((1,0)) - c = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(N*N), arg=0).view(ShapeTracker.from_shape((N,N))) - As = UOp(Ops.DEFINE_LOCAL, dtypes.float.ptr(BK*BM, AddrSpace.LOCAL), arg=0).view(ShapeTracker.from_shape((BK, BM))).permute((1,0)) - Bs = UOp(Ops.DEFINE_LOCAL, dtypes.float.ptr(BK*BN, AddrSpace.LOCAL), arg=1).view(ShapeTracker.from_shape((BK, BN))).permute((1,0)) - A_col = UOp(Ops.DEFINE_REG, dtypes.float.ptr(nbIterWaveM * TM, AddrSpace.REG), arg=0).view(ShapeTracker.from_shape((nbIterWaveM * TM,))) - B_row = UOp(Ops.DEFINE_REG, dtypes.float.ptr(nbIterWaveN * TN, AddrSpace.REG), arg=1).view(ShapeTracker.from_shape((nbIterWaveN * TN,))) - - # shape buffers. TODO: permutes - full_shape = (N//BM, nbIterWaveM, BM//(nbIterWaveM * TM), TM, N//BN, nbIterWaveN, BN//(nbIterWaveN * TN), TN, N//BK, BK) - a = a.reshape((N//BM, nbIterWaveM, BM//(nbIterWaveM * TM), TM, 1, 1, 1, 1, N//BK, BK)).expand(full_shape) - b = b.reshape((1, 1, 1, 1, N//BN, nbIterWaveN, BN//(nbIterWaveN * TN), TN, N//BK, BK)).expand(full_shape) - c = c.reshape((N//BM, nbIterWaveM, BM//(nbIterWaveM * TM), TM, N//BN, nbIterWaveN, BN//(nbIterWaveN * TN), TN, 1, 1)) - As = As.reshape((1, nbIterWaveM, BM//(nbIterWaveM * TM), TM, 1, 1, 1, 1, 1, BK)).expand(full_shape) - Bs = Bs.reshape((1, 1, 1, 1, 1, nbIterWaveN, BN//(nbIterWaveN * TN), TN, 1, BK)).expand(full_shape) - A_col = A_col.reshape((1, nbIterWaveM, 1, TM, 1, 1, 1, 1, 1, 1)).expand(full_shape) - B_row = B_row.reshape((1, 1, 1, 1, 1, nbIterWaveN, 1, TN, 1, 1)).expand(full_shape) - - # U1 L2 L3 L4 L5 U6 U7 U9 L10 L11 L12 L13 U14 U15 U17 U18 U19 - expanded_shape = (32, 2, 2, 2, 2, 2, 2, 2, 32, 2, 2, 2, 2, 2, 2, 2, 512, 2, 2, 2) - assert len(expanded_shape) == 20 - permute_a = list(range(len(expanded_shape))) - permute_b = permute_a[:] - - # this makes all the global loads match - # this can also be more simply done by rebinding the RANGEs - # but sadly, rebinding the RANGEs doesn't work to change the order of the local axes - permute_a[17:20] = [11,12,13] - permute_a[11:14] = [17,18,19] - permute_a[7], permute_a[10] = permute_a[10], permute_a[7] - permute_a[2:7] = [3,4,5,6,2] - - permute_b[2:16] = [19,9,10,11,17,18,8,2,12,13,14,15,3,4] - permute_b[17:20] = [5,6,7] - - a_permute = a.reshape(expanded_shape).permute(tuple(permute_a)).reshape(full_shape) - As_permute = As.reshape(expanded_shape).permute(tuple(permute_a)).reshape(full_shape) - - b_permute = b.reshape(expanded_shape).permute(tuple(permute_b)).reshape(full_shape) - Bs_permute = Bs.reshape(expanded_shape).permute(tuple(permute_b)).reshape(full_shape) - - #out = (a.load() * b.load()).r(Ops.ADD, (8, 9)) - out = (As.load(As_permute.store(a_permute.load())) * Bs.load(Bs_permute.store(b_permute.load()))).r(Ops.ADD, (8, 9)) - #out = (A_col.load(A_col.store(As.load(As.store(a.load())))) * B_row.load(B_row.store(Bs.load(Bs.store(b.load()))))).r(Ops.ADD, (8, 9)) - - axis_types = ( - AxisType.GLOBAL, AxisType.UPCAST, AxisType.LOCAL, AxisType.UPCAST, - AxisType.GLOBAL, AxisType.UPCAST, AxisType.LOCAL, AxisType.UPCAST, - AxisType.REDUCE, AxisType.REDUCE) - - sink = c.store(out).sink(arg=KernelInfo(name="tg_"+to_colored(full_shape, axis_types), axis_types=axis_types)) - sink = graph_rewrite(sink, merge_views) - return sink - -def hand_spec_kernel3(kernel4=getenv("K4", 0), kernel5=getenv("K5", 0)): - BLOCK_SIZE = 128 if kernel5 else 256 - - nbWaves = BLOCK_SIZE // 32 - WN = 128 if kernel5 else 64 - WM = BN * BM // nbWaves // WN - - nbWaveX = BN // WN - nbWaveY = BM // WM - - threadIdx_x = UOp(Ops.SPECIAL, dtypes.int, arg=("lidx0", BLOCK_SIZE)) - waveIndex = threadIdx_x // 32 - waveIdx = waveIndex % nbWaveX - waveIdy = waveIndex // nbWaveX - indexInWave = threadIdx_x % 32 - - nbThreadXPerWave = 8 - nbThreadYPerWave = 4 - - idxInWave = indexInWave % nbThreadXPerWave - idyInWave = indexInWave // nbThreadXPerWave - - nbIterWaveN = WN // (nbThreadXPerWave * TN) - nbIterWaveM = WM // (nbThreadYPerWave * TM) - - SUBWN = WN // nbIterWaveN - SUBWM = WM // nbIterWaveM - - # Thread mapping to read BKxBN block from A - rAIdx = threadIdx_x % BK - rAIdy = threadIdx_x // BK - # Thread mapping to read BNxBK block from B - rBIdx = threadIdx_x % BN - rBIdy = threadIdx_x // BN - - strideReadB = BLOCK_SIZE // BN - strideReadA = BLOCK_SIZE // BK - nbReadsB = BN * BK // BLOCK_SIZE - nbReadsA = BM * BK // BLOCK_SIZE - - blockIdx_x = UOp(Ops.SPECIAL, dtypes.int, arg=("gidx0", N//BN)) - blockIdx_y = UOp(Ops.SPECIAL, dtypes.int, arg=("gidx1", N//BM)) - - a = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(N*N), arg=1) - b = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(N*N), arg=2) - c = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(N*N), arg=0) - - A_col = UOp(Ops.DEFINE_REG, dtypes.float.ptr(nbIterWaveM * TM, AddrSpace.REG), arg=0) - B_row = UOp(Ops.DEFINE_REG, dtypes.float.ptr(nbIterWaveN * TN, AddrSpace.REG), arg=1) - - BM_As_stride = (BM+4) if kernel5 else BM - As = UOp(Ops.DEFINE_LOCAL, dtypes.float.ptr(BK*BM_As_stride, AddrSpace.LOCAL), arg=0) - Bs = UOp(Ops.DEFINE_LOCAL, dtypes.float.ptr(BK*BN, AddrSpace.LOCAL), arg=1) - - c_regs = UOp(Ops.DEFINE_REG, dtypes.float.ptr(TM * nbIterWaveM * TN * nbIterWaveN), arg=2) - - i = UOp.range(c_regs.dtype.size, 16) - init_store = c_regs[i].store(UOp.const(dtypes.float, 0.0), i) - - if kernel4: - regA = UOp(Ops.DEFINE_REG, dtypes.float.ptr(nbReadsA, AddrSpace.REG), arg=3) - regB = UOp(Ops.DEFINE_REG, dtypes.float.ptr(nbReadsB, AddrSpace.REG), arg=4) - - # initial load from globals into locals (0) - kId = 0 - - # load from globals into locals - i = UOp.range(nbReadsB, 0) - index_x = BN * blockIdx_x + rBIdx - index_y = rBIdy + i * strideReadB + kId - Bs_store = Bs[(index_y % BK) * BN + index_x % BN].store(b[N * index_y + index_x].load(), i) - - i = UOp.range(nbReadsA, 1) - index_x = rAIdx + kId - index_y = BM * blockIdx_y + rAIdy + i * strideReadA - As_store = As[(index_x % BK) * BM_As_stride + index_y % BM].store(a[N * index_y + index_x].load(), i) - - # iterate over the middle chunk - kId_range = UOp.range(N//BK-1, 2) - kId = kId_range*BK - - barrier = UOp.barrier(As_store, Bs_store) - - # load from globals into registers (next round) - i = UOp.range(nbReadsB, 3) - index_x = BN * blockIdx_x + rBIdx - index_y = rBIdy + i * strideReadB + kId + BK - regB_store = regB[i].store(b[N * index_y + index_x].load(), i) - - i = UOp.range(nbReadsA, 4) - index_x = rAIdx + kId + BK - index_y = BM * blockIdx_y + rAIdy + i * strideReadA - regA_store = regA[i].store(a[N * index_y + index_x].load(), i) - - def inner_loop(first_range, inp_dep=()): - # inner unroll - k = UOp.range(BK, first_range+0) - - # load from locals into registers - iterWave = UOp.range(nbIterWaveN, first_range+1) - i = UOp.range(TN, first_range+2) - index = waveIdx * WN + iterWave * SUBWN + TN * idxInWave + i - B_row_store = B_row[iterWave*TN + i].store(Bs[k*BN + index].load(*inp_dep), iterWave, i) - - iterWave = UOp.range(nbIterWaveM, first_range+3) - i = UOp.range(TM, first_range+4) - index = waveIdy * WM + iterWave * SUBWM + TM * idyInWave + i - A_col_store = A_col[iterWave*TM + i].store(As[k*BM_As_stride + index].load(*inp_dep), iterWave, i) - - # do the GEMM math - iterWaveM = UOp.range(nbIterWaveM, first_range+5) - yt = UOp.range(TM, first_range+6) - iterWaveN = UOp.range(nbIterWaveN, first_range+7) - xt = UOp.range(TN, first_range+8) - x = iterWaveN * TN + xt - y = iterWaveM * TM + yt - c_regs_idx = c_regs[y * TN * nbIterWaveN + x] - # sketchy, this should end the kId_range but it doesn't - sink = c_regs_idx.store(c_regs_idx.load(init_store) + A_col[y].load(A_col_store) * B_row[x].load(B_row_store), - iterWaveM, iterWaveN, yt, xt, k) - return sink - - # TODO: kId_range should endrange after a barrier - sink = inner_loop(5, (barrier, regB_store, regA_store)).barrier() - - # load from registers into locals - i = UOp.range(nbReadsB, 14) - index_x = BN * blockIdx_x + rBIdx - index_y = rBIdy + i * strideReadB + kId + BK - Bs_store = Bs[(index_y % BK) * BN + index_x % BN].store(regB[i].load(sink), i, kId_range) - - i = UOp.range(nbReadsA, 15) - index_x = rAIdx + kId + BK - index_y = BM * blockIdx_y + rAIdy + i * strideReadA - As_store = As[(index_x % BK) * BM_As_stride + index_y % BM].store(regA[i].load(sink), i, kId_range) - - # final iteration without the copy - sink = inner_loop(16, (UOp.barrier(Bs_store, As_store),)) - else: - kId_range = UOp.range(N//BK, 0) - kId = kId_range*BK - - # load from globals into locals - i = UOp.range(nbReadsB, 1) - index_x = BN * blockIdx_x + rBIdx - index_y = rBIdy + i * strideReadB + kId - Bs_store = Bs[(index_y % BK) * BN + index_x % BN].store(b[N * index_y + index_x].load(), i) - - i = UOp.range(nbReadsA, 2) - index_x = rAIdx + kId - index_y = BM * blockIdx_y + rAIdy + i * strideReadA - As_store = As[(index_x % BK) * BM_As_stride + index_y % BM].store(a[N * index_y + index_x].load(), i) - - barrier = UOp.barrier(As_store, Bs_store) - - k = UOp.range(BK, 3) - - # load from locals into registers - iterWave = UOp.range(nbIterWaveN, 4) - i = UOp.range(TN, 5) - index = waveIdx * WN + iterWave * SUBWN + TN * idxInWave + i - B_row_store = B_row[iterWave*TN + i].store(Bs[k*BN + index].load(barrier), iterWave, i) - - iterWave = UOp.range(nbIterWaveM, 6) - i = UOp.range(TM, 7) - index = waveIdy * WM + iterWave * SUBWM + TM * idyInWave + i - A_col_store = A_col[iterWave*TM + i].store(As[k*BM_As_stride + index].load(barrier), iterWave, i) - - # do the GEMM math - iterWaveM = UOp.range(nbIterWaveM, 8) - yt = UOp.range(TM, 9) - iterWaveN = UOp.range(nbIterWaveN, 10) - xt = UOp.range(TN, 12) - x = iterWaveN * TN + xt - y = iterWaveM * TM + yt - c_regs_idx = c_regs[y * TN * nbIterWaveN + x] - sink = c_regs_idx.store(c_regs_idx.load(init_store) + A_col[y].load(A_col_store) * B_row[x].load(B_row_store), - iterWaveM, iterWaveN, yt, xt, k, kId_range) - - # store c_regs into c - iterWaveM = UOp.range(nbIterWaveM, 1000) - yt = UOp.range(TM, 1001) - iterWaveN = UOp.range(nbIterWaveN, 1002) - xt = UOp.range(TN, 1003) - xOut = blockIdx_x * BN + waveIdx * WN + iterWaveN * SUBWN + TN * idxInWave - yOut = blockIdx_y * BM + waveIdy * WM + iterWaveM * SUBWM + TM * idyInWave - indexC = N * (yOut + yt) + xOut + xt - sink = c[indexC].store(c_regs[TN * nbIterWaveN * (iterWaveM * TM + yt) + (iterWaveN * TN + xt)].load(sink), - iterWaveM, iterWaveN, yt, xt) - - return sink.sink(arg=KernelInfo(name="tinygemm")) - -if __name__ == "__main__": - HL = getenv("HL") - if HL == 3: hprg = rangeify_kernel3() - elif HL == 2: hprg = top_spec_kernel3() - elif HL == 1: hprg = hl_spec_kernel3() - else: hprg = hand_spec_kernel3() - if HL == 3: - with Context(RANGEIFY=1, BLOCK_REORDER=0): - prg = get_program(hprg, Device.default.renderer) - else: - prg = get_program(hprg, Device.default.renderer) - print(prg.src) - if getenv("SRC"): exit(0) - hrunner = CompiledRunner(prg) - - a = Tensor.randn(N, N).realize() - b = Tensor.randn(N, N).realize() - hc = Tensor.zeros(N, N).contiguous().realize() - - GlobalCounters.reset() - with Context(DEBUG=2): - for _ in range(run_count): tc = (a@b).realize() - - GlobalCounters.reset() - buffers = [hc.uop.buffer, a.uop.buffer, b.uop.buffer] - ei = ExecItem(hrunner, buffers) - with Context(DEBUG=2): - for _ in range(run_count): ei.run(wait=True) - err = (hc-tc).square().mean().item() - print(f"hrunner {err}") - if err > 1e-06: raise RuntimeError("matmul is wrong!") diff --git a/tinygrad_repo/extra/gemm/amx.py b/tinygrad_repo/extra/gemm/amx.py old mode 100644 new mode 100755 diff --git a/tinygrad_repo/extra/gemm/gemm.py b/tinygrad_repo/extra/gemm/gemm.py old mode 100644 new mode 100755 diff --git a/tinygrad_repo/extra/gemm/halide_gemm.py b/tinygrad_repo/extra/gemm/halide_gemm.py deleted file mode 100644 index acfd83d14..000000000 --- a/tinygrad_repo/extra/gemm/halide_gemm.py +++ /dev/null @@ -1,90 +0,0 @@ -import numpy as np -import halide as hl -from tinygrad.helpers import Timing, getenv - -# HL_DEBUG_CODEGEN=1 -N = getenv("N", 1024) - -def gemm_pipeline(gpu=False): - # ---------------- Vars & Parameters ---------------- - i, j = hl.Var("i"), hl.Var("j") # output tile coordinates - - A = hl.InputBuffer(hl.Float(32), 2) # [M, K] - B = hl.InputBuffer(hl.Float(32), 2) # [K, N] - - A.dim(0).set_bounds(0, N) - A.dim(1).set_bounds(0, N) - B.dim(0).set_bounds(0, N) - B.dim(1).set_bounds(0, N) - - # ---------------- Definition ---------------- - - k = hl.RDom([(0, N)]) - - partial = hl.Func("partial") - partial[i, j] = 0.0 - partial[i, j] += A[i, k] * B[k, j] - - C = hl.Func("C") - C[i, j] = partial[i, j] - - if not gpu: - # ---------------- Schedule ---------------- - VEC = 16 - TILE_I = 64 - TILE_J = 64 - - io, jo, ii, ji = hl.Var("io"), hl.Var("jo"), hl.Var("ii"), hl.Var("ji") - C.update().tile(i, j, io, jo, ii, ji, TILE_I, TILE_J).fuse(io, jo, io).parallel(io).vectorize(ji, VEC) - else: - # ---------------- Schedule ---------------- - GRP_I = 8 # output tile size - GRP_J = 16 - - #partial.store_in(hl.MemoryType.Register) - #partial.update().unroll(k, 4) - - io, jo, ii, ji = hl.Var(), hl.Var(), hl.Var(), hl.Var() - C.gpu_tile(i, j, io, jo, ii, ji, GRP_I, GRP_J, hl.TailStrategy.RoundUp) - - return C, A, B - -if __name__ == "__main__": - pipe, A, B = gemm_pipeline(gpu=True) - - # NOTE: meteal does nothing - target = hl.get_host_target().with_feature(hl.TargetFeature.Metal) - - a_np = np.random.randn(N, N).astype(np.float32) - b_np = np.random.randn(N, N).astype(np.float32) - - # reverse order is correct! - a_hal = hl.Buffer(b_np) - b_hal = hl.Buffer(a_np) - A.set(a_hal) - B.set(b_hal) - - pipe.compile_to_lowered_stmt("/tmp/my_function.html", [A, B], hl.StmtOutputFormat.HTML, target=target) - #exit(0) - - c_hal = hl.Buffer(hl.Float(32), [N,N]) - with Timing("halide gemm "): - pipe.realize(c_hal, target) - c_hal.copy_to_host() - c_out = np.array(c_hal) - print(c_out) - - # tinygrad gets 60 ms with no BEAM, 20 ms with BEAM on CPU - with Timing("halide gemm "): - pipe.realize(c_hal, target) - c_hal.copy_to_host() - - # Check correctness - with Timing("numpy gemm "): - ref = a_np @ b_np - max_err = np.abs(ref - c_out).max() - print("Max absolute error:", max_err) - assert max_err < 1e-4, "GEMM result incorrect!" - - print("Pipeline ran on", target) - print("Success - GEMM Halide-Python output matches NumPy.") diff --git a/tinygrad_repo/extra/gemm/jax_pmatmul.py b/tinygrad_repo/extra/gemm/jax_pmatmul.py old mode 100644 new mode 100755 diff --git a/tinygrad_repo/extra/gemm/max_matmul.py b/tinygrad_repo/extra/gemm/max_matmul.py index 6937b7d15..9d093c2fb 100644 --- a/tinygrad_repo/extra/gemm/max_matmul.py +++ b/tinygrad_repo/extra/gemm/max_matmul.py @@ -2,12 +2,11 @@ import numpy as np, os from tinygrad.helpers import getenv, flat_mv from tinygrad import dtypes from typing import Optional, List, Tuple, cast, Dict, Final, DefaultDict, Self -from tinygrad.engine.realize import get_program # for copied uops -from tinygrad.codegen.opt.kernel import Kernel, KernelOptError +from tinygrad.opt.kernel import Kernel, KernelOptError from tinygrad.uop.ops import UOp, Ops, BinaryOps, UnaryOps, TernaryOps, KernelInfo -from tinygrad.codegen.opt.search import Opt, OptOps +from tinygrad.opt.search import Opt, OptOps from tinygrad import Device, dtypes, Tensor from tinygrad.dtype import PtrDType, DType, DTYPES_DICT from tinygrad.shape.shapetracker import ShapeTracker @@ -56,7 +55,7 @@ def randoms(): def ast_to_cuda_prog(compiler, ast, opts): k = Kernel(ast) k.apply_opts(opts) - p = get_program(k.ast, k.opts, k.applied_opts) + p = k.to_program() return CUDAProgram(device, p.function_name, compiler.compile(p.src)) if __name__ == "__main__": diff --git a/tinygrad_repo/extra/gemm/simple_matmul.py b/tinygrad_repo/extra/gemm/simple_matmul.py index 7b9c07278..8b857a882 100644 --- a/tinygrad_repo/extra/gemm/simple_matmul.py +++ b/tinygrad_repo/extra/gemm/simple_matmul.py @@ -2,7 +2,7 @@ import numpy as np from tinygrad import dtypes, Tensor from tinygrad.helpers import getenv, get_single_element from tinygrad.dtype import _to_np_dtype -from tinygrad.codegen.opt.kernel import OptOps +from tinygrad.opt.kernel import OptOps from tinygrad.engine.realize import lower_schedule dtype_in = dtypes.half if getenv("HALF") else dtypes.bfloat16 if getenv("BFLOAT16") else dtypes.float diff --git a/tinygrad_repo/extra/gemm/tinygrad_nv_matmul.py b/tinygrad_repo/extra/gemm/tinygrad_nv_matmul.py index 1ee3e72e1..f81877a41 100644 --- a/tinygrad_repo/extra/gemm/tinygrad_nv_matmul.py +++ b/tinygrad_repo/extra/gemm/tinygrad_nv_matmul.py @@ -1,7 +1,7 @@ from tinygrad import Tensor, dtypes, Device from tinygrad.helpers import getenv, DEBUG -from tinygrad.codegen.opt.kernel import Kernel, Opt, OptOps -from tinygrad.engine.realize import CompiledRunner, ExecItem, get_program +from tinygrad.opt.kernel import Kernel, Opt, OptOps +from tinygrad.engine.realize import CompiledRunner, ExecItem from dataclasses import replace N = 4096 @@ -29,7 +29,7 @@ if __name__ == "__main__": Opt(op=OptOps.LOCAL, axis=0, amt=2), ] k.apply_opts(opts) - prg = get_program(k.ast, k.opts, k.applied_opts) + prg = k.to_program() new_src = prg.src # can mod source here prg = replace(prg, src=new_src) diff --git a/tinygrad_repo/extra/gemm/tvm_gemm.py b/tinygrad_repo/extra/gemm/tvm_gemm.py index da58df243..47796023f 100644 --- a/tinygrad_repo/extra/gemm/tvm_gemm.py +++ b/tinygrad_repo/extra/gemm/tvm_gemm.py @@ -37,10 +37,10 @@ B = Tensor.rand(K, N, device="CPU") C = (A.reshape(M, 1, K) * B.permute(1,0).reshape(1, N, K)).sum(axis=2) sched = C.schedule() -from tinygrad.codegen.opt.kernel import Kernel +from tinygrad.opt.kernel import Kernel from tinygrad.device import CompilerOptions lin = Kernel(sched[-1].ast, CompilerOptions(has_local=False, supports_float4=False)) -lin.to_program() +lin.linearize() from tinygrad.runtime.ops_cpu import renderer src = renderer("mmult", lin.uops) print(src) diff --git a/tinygrad_repo/extra/hcq/hcq_smi.py b/tinygrad_repo/extra/hcq/hcq_smi.py deleted file mode 100644 index b5cd627d0..000000000 --- a/tinygrad_repo/extra/hcq/hcq_smi.py +++ /dev/null @@ -1,122 +0,0 @@ -#!/usr/bin/env python3 - -from tinygrad.runtime.support.system import System -import argparse, glob, os, re, time, subprocess, sys - -def scan_devs_based_on_lock(prefix:str, args) -> list[str]: - target_dev = args.pci_bus if 'pci_bus' in args.__dir__() else "" - - devs = [] - for dev in glob.glob(f'/tmp/{prefix}_*.lock'): - dev_id = dev[8:-5] - if os.path.exists(f"/sys/bus/pci/devices/{dev_id}") and dev_id.startswith(target_dev): devs.append(dev_id) - return devs - -def _do_reset_device(pci_bus): System.pci_reset(pci_bus) -def _is_module_loaded(name: str) -> bool: return os.path.isdir(f"/sys/module/{name}") - -def cmd_remove_module(args): - modules = ["nvidia_drm", "nvidia_modeset", "nvidia_uvm", "nvidia", "ast"] if args.backend == "nv" else ["amdgpu"] - to_unload = [m for m in modules if _is_module_loaded(m)] - if not to_unload: print("Kernel modules are not loaded") - else: - print("Removing kernel modules:", ", ".join(to_unload)) - try: subprocess.run(["sudo", "modprobe", "-r", *to_unload], check=True) - except subprocess.CalledProcessError as e: - print("Failed to unload all modules — they may be in use.", file=sys.stderr) - sys.exit(e.returncode) - -def cmd_insert_module(args): - cmd_remove_module(args) - cmd_reset_devices(args) - - module = "nvidia" if args.backend == "nv" else "amdgpu" - if _is_module_loaded(module): - print(f"{module} kernel module already loaded") - return - - print(f"Inserting kernel module: {module}") - if args.backend == "nv": - subprocess.run(["nvidia-smi"], check=True) - elif args.backend == "amd": - subprocess.run(["sudo", "modprobe", "amdgpu"], check=True) - -def cmd_reset_devices(args): - devs = scan_devs_based_on_lock({"amd":"am", "nv":"nv"}[args.backend], args) - - for dev in devs: - print(f"Resetting device {dev}") - if args.backend != "amd": _do_reset_device(dev) - time.sleep(0.2) - -def cmd_show_pids(args): - devs = scan_devs_based_on_lock(prefix:={"amd":"am", "nv":"nv"}[args.backend], args) - - for dev in devs: - try: - pid = subprocess.check_output(['sudo', 'lsof', f'/tmp/{prefix}_{dev}.lock']).decode('utf-8').strip().split('\n')[1].split()[1] - print(f"{dev}: {pid}") - except subprocess.CalledProcessError: print(f"{dev}: No processes found using this device") - -def cmd_kill_pids(args): - devs = scan_devs_based_on_lock(prefix:={"amd":"am", "nv":"nv"}[args.backend], args) - - for dev in devs: - try: - pid = subprocess.check_output(['sudo', 'lsof', f'/tmp/{prefix}_{dev}.lock']).decode('utf-8').strip().split('\n')[1].split()[1] - print(f"{dev}: {pid}") - except subprocess.CalledProcessError: print(f"{dev}: No processes found using this device") - -def cmd_kill_pids(args): - devs = scan_devs_based_on_lock(prefix:={"amd":"am", "nv":"nv"}[args.backend], args) - - for dev in devs: - for i in range(128): - if i > 0: time.sleep(0.2) - - try: - try: pid = subprocess.check_output(['sudo', 'lsof', f'/tmp/{prefix}_{dev}.lock']).decode('utf-8').strip().split('\n')[1].split()[1] - except subprocess.CalledProcessError: break - - print(f"Killing process {pid} (which uses {dev})") - subprocess.run(['sudo', 'kill', '-9', pid], check=True) - except subprocess.CalledProcessError as e: - print(f"Failed to kill process for device {dev}: {e}", file=sys.stderr) - -def add_common_commands(parent_subparsers): - p_insmod = parent_subparsers.add_parser("insmod", help="Insert a kernel module") - p_insmod.set_defaults(func=cmd_insert_module) - - p_rmmod = parent_subparsers.add_parser("rmmod", help="Remove a kernel module") - p_rmmod.set_defaults(func=cmd_remove_module) - - p_reset = parent_subparsers.add_parser("reset", help="Reset a device") - p_reset.add_argument("--pci_bus", default="", help="PCI bus ID of the device to reset") - p_reset.set_defaults(func=cmd_reset_devices) - - p_reset = parent_subparsers.add_parser("pids", help="Show pids of processes using the device") - p_reset.add_argument("--pci_bus", default="", help="PCI bus ID of the device") - p_reset.set_defaults(func=cmd_show_pids) - - p_reset = parent_subparsers.add_parser("kill_pids", help="Kill pids of processes using the device") - p_reset.add_argument("--pci_bus", default="", help="PCI bus ID of the device") - p_reset.set_defaults(func=cmd_kill_pids) - -if __name__ == "__main__": - parser = argparse.ArgumentParser() - backend_subparsers = parser.add_subparsers(dest="backend", required=True, metavar="{nv,amd}", help="Hardware backend to target") - - nv_parser = backend_subparsers.add_parser("nv", help="NVIDIA GPUs") - nv_commands = nv_parser.add_subparsers(dest="command", required=True) - add_common_commands(nv_commands) - - amd_parser = backend_subparsers.add_parser("amd", help="AMD GPUs") - amd_commands = amd_parser.add_subparsers(dest="command", required=True) - add_common_commands(amd_commands) - - args = parser.parse_args() - if args.command is None: - parser.print_help(sys.stderr) - sys.exit(1) - - args.func(args) diff --git a/tinygrad_repo/extra/hcqfuzz/tests/allocator.py b/tinygrad_repo/extra/hcqfuzz/tests/allocator.py new file mode 100644 index 000000000..dd1706491 --- /dev/null +++ b/tinygrad_repo/extra/hcqfuzz/tests/allocator.py @@ -0,0 +1,16 @@ +from extra.hcqfuzz.spec import TestSpec +import random + +class TLSFAllocator(TestSpec): + def prepare(self, dev, seed): + random.seed(seed) + + self.env = { + "SEED": seed, + "ITERS": random.randint(10000, 1000000), + } + + self.cmd = "python3 test/external/external_fuzz_tlsf.py" + self.timeout = 60 * 60 # 60 minutes + + def get_exec_state(self): return self.env, self.cmd, self.timeout diff --git a/tinygrad_repo/extra/hcqfuzz/tests/allreduce.py b/tinygrad_repo/extra/hcqfuzz/tests/allreduce.py new file mode 100644 index 000000000..b741d82aa --- /dev/null +++ b/tinygrad_repo/extra/hcqfuzz/tests/allreduce.py @@ -0,0 +1,17 @@ +from extra.hcqfuzz.spec import TestSpec +import random + +class RingAllreduce(TestSpec): + def prepare(self, dev, seed): + random.seed(seed) + + self.env = { + "GPUS": random.choice([2, 3, 4, 5, 6]), + "ITERS": random.randint(10, 1000), + "DEBUG": 2, + } + + self.cmd = "python3 test/external/external_benchmark_multitensor_allreduce.py" + self.timeout = 10 * 60 # 10 minutes + + def get_exec_state(self): return self.env, self.cmd, self.timeout diff --git a/tinygrad_repo/extra/hcqfuzz/tests/bert.py b/tinygrad_repo/extra/hcqfuzz/tests/bert.py new file mode 100644 index 000000000..331d908cf --- /dev/null +++ b/tinygrad_repo/extra/hcqfuzz/tests/bert.py @@ -0,0 +1,83 @@ +from extra.hcqfuzz.spec import TestSpec +import random + +bert_train_params = { + "DEFAULT_FLOAT": "HALF", + "SUM_DTYPE": "HALF", + "GPUS": 6, + "BS": 96, + "EVAL_BS": 96, + "FUSE_ARANGE": 1, + "FUSE_ARANGE_UINT": 0, + "BASEDIR": "/raid/datasets/wiki", +} + +class TrainBert(TestSpec): + def prepare(self, dev, seed): + random.seed(seed) + + self.env = { + **bert_train_params, + "IGNORE_BEAM_CACHE": 1, + "BEAM": 5, + "BEAM_UOPS_MAX": 10000, + "BEAM_UPCAST_MAX": 256, + "BEAM_LOCAL_MAX": 1024, + "BEAM_MIN_PROGRESS": 5, + "IGNORE_JIT_FIRST_BEAM": 1, + "LOGMLPERF": 0, + "SEED": seed, + } + + self.cmd = "python3 examples/mlperf/model_train.py" + self.timeout = 7 * 60 * 60 # 7 hours + + def get_exec_state(self): return self.env, self.cmd, self.timeout + +class TrainBertShort(TestSpec): + def prepare(self, dev, seed): + random.seed(seed) + + self.env = { + **bert_train_params, + "IGNORE_BEAM_CACHE": 1, + "BEAM": 5, + "BEAM_UOPS_MAX": 10000, + "BEAM_UPCAST_MAX": 256, + "BEAM_LOCAL_MAX": 1024, + "BEAM_MIN_PROGRESS": 5, + "IGNORE_JIT_FIRST_BEAM": 1, + "SEED": seed, + "BENCHMARK": 4096, + "JIT": 2 + } + + self.cmd = "python3 examples/mlperf/model_train.py" + self.timeout = 2 * 60 * 60 # 2 hours + + def get_exec_state(self): return self.env, self.cmd, self.timeout + +class BertBeam(TestSpec): + def prepare(self, dev, seed): + random.seed(seed) + + self.env = { + **bert_train_params, + "IGNORE_BEAM_CACHE": 1, + "BEAM": random.choice([1, 2, 3, 4, 5]), + "BEAM_UOPS_MAX": 10000, + "BEAM_UPCAST_MAX": 256, + "BEAM_LOCAL_MAX": 1024, + "BEAM_MIN_PROGRESS": 5, + "IGNORE_JIT_FIRST_BEAM": 1, + "SEED": seed, + "RESET_STEP": 1, + "BENCHMARK": 10, + "BERT_LAYERS": 2, + "SEED": seed, + } + + self.cmd = "python3 examples/mlperf/model_train.py" + self.timeout = 1 * 60 * 60 # 1 hour + + def get_exec_state(self): return self.env, self.cmd, self.timeout diff --git a/tinygrad_repo/extra/hcqfuzz/tests/hcq.py b/tinygrad_repo/extra/hcqfuzz/tests/hcq.py new file mode 100644 index 000000000..77eaef660 --- /dev/null +++ b/tinygrad_repo/extra/hcqfuzz/tests/hcq.py @@ -0,0 +1,35 @@ +from extra.hcqfuzz.spec import TestSpec +import random + +class HCQSignalFuzzer(TestSpec): + def prepare(self, dev, seed): + random.seed(seed) + + self.env = { + "GPUS": random.choice([2, 3, 4, 5, 6]), + "ITERS": random.randint(1000000, 10000000), + "SEED": seed, + } + + self.cmd = "python3 test/external/external_fuzz_hcq_signals.py" + self.timeout = 30 * 60 # 30 minutes + + def get_exec_state(self): return self.env, self.cmd, self.timeout + +class HCQGraphFuzzer(TestSpec): + def prepare(self, dev, seed): + random.seed(seed) + + self.env = { + "FUZZ_GRAPH_SPLIT_RUNS": random.randint(48, 64), + "FUZZ_GRAPH_MAX_SPLITS": random.randint(4, 16), + "FUZZ_GRAPH_SPLIT_RETRY_RUNS": random.randint(4, 8), + "MAX_KERNELS": random.randint(32, 512), + "MAX_DEVICES": random.choice([2, 3, 4, 5, 6]), + "ITERS": random.randint(100, 1000), + } + + self.cmd = "python3 test/external/fuzz_graph.py" + self.timeout = 60 * 60 # 60 minutes + + def get_exec_state(self): return self.env, self.cmd, self.timeout diff --git a/tinygrad_repo/extra/hcqfuzz/tests/resnet.py b/tinygrad_repo/extra/hcqfuzz/tests/resnet.py new file mode 100644 index 000000000..0009219db --- /dev/null +++ b/tinygrad_repo/extra/hcqfuzz/tests/resnet.py @@ -0,0 +1,66 @@ +from extra.hcqfuzz.spec import TestSpec +import random + +resnet_train_params = { + "DEFAULT_FLOAT": "HALF", + "SUM_DTYPE": "HALF", + "GPUS": 6, + "BS": 1536, + "EVAL_BS": 192, + "TRAIN_BEAM": 4, + "IGNORE_JIT_FIRST_BEAM": 1, + "BEAM_UOPS_MAX": 2000, + "BEAM_UPCAST_MAX": 96, + "BEAM_LOCAL_MAX": 1024, + "BEAM_MIN_PROGRESS": 5, + "BEAM_PADTO": 0, + "EVAL_START_EPOCH": 3, + "EVAL_FREQ": 4 +} + +class TrainResnet(TestSpec): + def prepare(self, dev, seed): + random.seed(seed) + + self.env = { + **resnet_train_params, + "IGNORE_BEAM_CACHE": 1, + "SEED": seed, + } + + self.cmd = "python3 examples/mlperf/model_train.py" + self.timeout = 4 * 60 * 60 # 7 hours + + def get_exec_state(self): return self.env, self.cmd, self.timeout + +class TrainResnetShort(TestSpec): + def prepare(self, dev, seed): + random.seed(seed) + + self.env = { + **resnet_train_params, + "SEED": seed, + "BENCHMARK": 4096, + "JIT": 2, + } + + self.cmd = "python3 examples/mlperf/model_train.py" + self.timeout = 2 * 60 * 60 # 2 hours + + def get_exec_state(self): return self.env, self.cmd, self.timeout + +class ResnetBeam(TestSpec): + def prepare(self, dev, seed): + random.seed(seed) + + self.env = { + **resnet_train_params, + "IGNORE_BEAM_CACHE": 1, + "BENCHMARK": 10, + "SEED": seed, + } + + self.cmd = "python3 examples/mlperf/model_train.py" + self.timeout = 1 * 60 * 60 # 1 hour + + def get_exec_state(self): return self.env, self.cmd, self.timeout diff --git a/tinygrad_repo/extra/hip_gpu_driver/hip_ioctl.py b/tinygrad_repo/extra/hip_gpu_driver/hip_ioctl.py index 20c4f3248..cd31694e9 100644 --- a/tinygrad_repo/extra/hip_gpu_driver/hip_ioctl.py +++ b/tinygrad_repo/extra/hip_gpu_driver/hip_ioctl.py @@ -5,7 +5,7 @@ start = time.perf_counter() # *** ioctl lib *** libc = ctypes.CDLL(ctypes.util.find_library("c")) # platform.processor calls `uname -p` which can return `unknown` on some systems -processor = os.getenv("IOCTL_PROCESSOR") or platform.processor() or platform.machine() +processor = os.getenv("IOCTL_PROCESSOR") or platform.processor() IOCTL_SYSCALL = {"aarch64": 0x1d, "x86_64":16}[processor] def get_struct(argp, stype): diff --git a/tinygrad_repo/extra/huggingface_onnx/README.md b/tinygrad_repo/extra/huggingface_onnx/README.md deleted file mode 100644 index d275ab57a..000000000 --- a/tinygrad_repo/extra/huggingface_onnx/README.md +++ /dev/null @@ -1,61 +0,0 @@ -# HuggingFace ONNX - -Tool for discovering, downloading, and validating ONNX models from HuggingFace. - -## Extra Dependencies - -```bash -pip install huggingface_hub pyyaml requests onnx onnxruntime numpy -``` - -## Huggingface Manager (discovering and downloading) - -The `huggingface_manager.py` script discovers top ONNX models from HuggingFace, collects metadata, and optionally downloads them. - -```bash -# Download top 50 models sorted by downloads -python huggingface_manager.py --limit 50 --download - -# Just collect metadata (no download) -python huggingface_manager.py --limit 100 - -# Sort by likes instead of downloads -python huggingface_manager.py --limit 20 --sort likes --download - -# Custom output file -python huggingface_manager.py --limit 10 --output my_models.yaml -``` - -### Output Format - -The tool generates a YAML file with the following structure: - -```yaml -repositories: - "model-name": - url: "https://huggingface.co/model-name" - download_path: "/path/to/models/..." # when --download used - files: - - file: "model.onnx" - size: "90.91MB" -total_size: "2.45GB" -created_at: "2024-01-15T10:30:00Z" -``` - -## Run Models (validation) - -The `run_models.py` script validates ONNX models against ONNX Runtime for correctness. - -```bash -# Validate models from a YAML configuration file -python run_models.py --validate huggingface_repos.yaml - -# Debug specific repository (downloads and validates all ONNX models) -python run_models.py --debug sentence-transformers/all-MiniLM-L6-v2 - -# Debug specific model file -python run_models.py --debug sentence-transformers/all-MiniLM-L6-v2/onnx/model.onnx - -# Debug with model truncation for debugging and validating intermediate results -DEBUGONNX=1 python run_models.py --debug sentence-transformers/all-MiniLM-L6-v2/onnx/model.onnx --truncate 10 -``` diff --git a/tinygrad_repo/extra/huggingface_onnx/collect_metadata.py b/tinygrad_repo/extra/huggingface_onnx/collect_metadata.py new file mode 100644 index 000000000..0a3d1eda2 --- /dev/null +++ b/tinygrad_repo/extra/huggingface_onnx/collect_metadata.py @@ -0,0 +1,85 @@ +import yaml, time, requests, argparse +from pathlib import Path +from huggingface_hub import list_models, HfApi +from tinygrad.helpers import tqdm + +HUGGINGFACE_URL = "https://huggingface.co" +SKIPPED_FILES = [ + "fp16", "int8", "uint8", "quantized", # numerical accuracy issues + "avx2", "arm64", "avx512", "avx512_vnni", # numerical accuracy issues + "q4", "q4f16", "bnb4", # unimplemented quantization + "model_O4", # requires non cpu ort runner and MemcpyFromHost op + "merged", # TODO implement attribute with graph type and Loop op +] +SKIPPED_REPO_PATHS = [ + # Invalid model-index + "AdamCodd/vit-base-nsfw-detector", + # TODO: implement attribute with graph type and Loop op + "minishlab/potion-base-8M", "minishlab/M2V_base_output", "minishlab/potion-retrieval-32M", + # TODO: implement SimplifiedLayerNormalization, SkipSimplifiedLayerNormalization, GroupQueryAttention + "HuggingFaceTB/SmolLM2-360M-Instruct", + # TODO: implement SimplifiedLayerNormalization, SkipSimplifiedLayerNormalization, RotaryEmbedding, MultiHeadAttention + "HuggingFaceTB/SmolLM2-1.7B-Instruct", + # TODO: implmement RandomNormalLike + "stabilityai/stable-diffusion-xl-base-1.0", "stabilityai/sdxl-turbo", 'SimianLuo/LCM_Dreamshaper_v7', + # TODO: implement NonZero + "mangoapps/fb_zeroshot_mnli_onnx", + # TODO huge Concat in here with 1024 (1, 3, 32, 32) Tensors, and maybe a MOD bug with const folding + "briaai/RMBG-2.0", +] + +def get_top_repos(n: int, sort: str) -> list[str]: # list["FacebookAI/xlm-roberta-large", ...] + print(f"** Getting top {n} models sorted by {sort} **") + repos = [] + i = 0 + for model in list_models(filter="onnx", sort=sort): + if model.id in SKIPPED_REPO_PATHS: continue + print(f"{i+1}/{n}: {model.id} ({getattr(model, sort)})") + repos.append(model.id) + i += 1 + if i == n: break + return repos + +def get_metadata(repos:list[str]) -> dict: + api = HfApi() + repos_metadata = {"repositories": {}} + total_size = 0 + + # TODO: speed head requests up with async? + for repo in tqdm(repos, desc="Getting metadata"): + files_metadata = [] + model_info = api.model_info(repo) + + for file in model_info.siblings: + filename = file.rfilename + if not (filename.endswith('.onnx') or filename.endswith('.onnx_data')): continue + if any(skip_str in filename for skip_str in SKIPPED_FILES): continue + head = requests.head(f"{HUGGINGFACE_URL}/{repo}/resolve/main/{filename}", allow_redirects=True) + file_size = file.size or int(head.headers.get('Content-Length', 0)) + files_metadata.append({"file": filename, "size": f"{file_size/1e6:.2f}MB"}) + total_size += file_size + + repos_metadata["repositories"][repo] = { + "url": f"{HUGGINGFACE_URL}/{repo}", + "download_path": None, + "files": files_metadata, + } + repos_metadata['total_size'] = f"{total_size/1e9:.2f}GB" + repos_metadata['created_at'] = time.strftime("%Y-%m-%dT%H:%M:%SZ", time.gmtime()) + return repos_metadata + +if __name__ == "__main__": + sort = "downloads" # recent 30 days downloads + huggingface_onnx_dir = Path(__file__).parent + + parser = argparse.ArgumentParser(description="Produces a YAML file with metadata of top huggingface onnx models") + parser.add_argument("--limit", type=int, required=True, help="Number of top repositories to process (e.g., 100)") + parser.add_argument("--output", type=str, default="huggingface_repos.yaml", help="Output YAML file name to save the report") + args = parser.parse_args() + + top_repos = get_top_repos(args.limit, sort) + metadata = get_metadata(top_repos) + yaml_path = huggingface_onnx_dir / args.output + with open(yaml_path, 'w') as f: + yaml.dump(metadata, f, sort_keys=False) + print(f"YAML saved to: {str(yaml_path)}") diff --git a/tinygrad_repo/extra/huggingface_onnx/download_models.py b/tinygrad_repo/extra/huggingface_onnx/download_models.py new file mode 100644 index 000000000..e79e0e85f --- /dev/null +++ b/tinygrad_repo/extra/huggingface_onnx/download_models.py @@ -0,0 +1,29 @@ +import yaml, argparse +from pathlib import Path +from huggingface_hub import snapshot_download + +def download_models(yaml_file: str, download_dir: str) -> None: + with open(yaml_file, 'r') as f: metadata = yaml.safe_load(f) + n = len(metadata["repositories"]) + + for i, (model_id, model_data) in enumerate(metadata["repositories"].items()): + print(f"Downloading {i+1}/{n}: {model_id}...") + allow_patterns = [file_info["file"] for file_info in model_data["files"]] + root_path = Path(snapshot_download(repo_id=model_id, allow_patterns=allow_patterns, cache_dir=download_dir)) + # download configs too (the sizes are small) + snapshot_download(repo_id=model_id, allow_patterns=["*config.json"], cache_dir=download_dir) + print(f"Downloaded model files to: {root_path}") + model_data["download_path"] = str(root_path) + + # Save the updated metadata back to the YAML file + with open(yaml_file, 'w') as f: yaml.dump(metadata, f, sort_keys=False) + print("Download completed according to YAML file.") + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description="Download models from Huggingface Hub based on a YAML configuration file.") + parser.add_argument("input", type=str, help="Path to the input YAML configuration file containing model information.") + args = parser.parse_args() + + models_folder = Path(__file__).parent / "models" + models_folder.mkdir(parents=True, exist_ok=True) + download_models(args.input, str(models_folder)) \ No newline at end of file diff --git a/tinygrad_repo/extra/huggingface_onnx/huggingface_manager.py b/tinygrad_repo/extra/huggingface_onnx/huggingface_manager.py deleted file mode 100644 index 7fe67f105..000000000 --- a/tinygrad_repo/extra/huggingface_onnx/huggingface_manager.py +++ /dev/null @@ -1,230 +0,0 @@ -import yaml -import time -import requests -import argparse -from pathlib import Path -from huggingface_hub import list_models, HfApi, snapshot_download -from tinygrad.helpers import _ensure_downloads_dir -DOWNLOADS_DIR = _ensure_downloads_dir() / "models" -from tinygrad.helpers import tqdm - -def snapshot_download_with_retry(*, repo_id: str, allow_patterns: list[str]|tuple[str, ...]|None=None, cache_dir: str|Path|None=None, - tries: int=2, **kwargs) -> Path: - for attempt in range(tries): - try: - return Path(snapshot_download( - repo_id=repo_id, - allow_patterns=allow_patterns, - cache_dir=str(cache_dir) if cache_dir is not None else None, - **kwargs - )) - except Exception as e: - if attempt == tries-1: raise - time.sleep(1) - -# Constants for filtering models -HUGGINGFACE_URL = "https://huggingface.co" -SKIPPED_FILES = [ - "fp16", "int8", "uint8", "quantized", # numerical accuracy issues - "avx2", "arm64", "avx512", "avx512_vnni", # numerical accuracy issues - "q4", "q4f16", "bnb4", # unimplemented quantization - "model_O4", # requires non cpu ort runner and MemcpyFromHost op - "merged", # TODO implement attribute with graph type and Loop op -] - -SKIPPED_REPO_PATHS = [ - # Invalid model-index - "AdamCodd/vit-base-nsfw-detector", - # TODO: implement attribute with graph type and Loop op - "minishlab/potion-base-8M", "minishlab/M2V_base_output", "minishlab/potion-retrieval-32M", - # TODO: implement SimplifiedLayerNormalization, SkipSimplifiedLayerNormalization, GroupQueryAttention - "HuggingFaceTB/SmolLM2-360M-Instruct", - # TODO: implement SimplifiedLayerNormalization, SkipSimplifiedLayerNormalization, RotaryEmbedding, MultiHeadAttention - "HuggingFaceTB/SmolLM2-1.7B-Instruct", - # TODO: implement RandomNormalLike - "stabilityai/stable-diffusion-xl-base-1.0", "stabilityai/sdxl-turbo", 'SimianLuo/LCM_Dreamshaper_v7', - # TODO: implement NonZero - "mangoapps/fb_zeroshot_mnli_onnx", - # TODO huge Concat in here with 1024 (1, 3, 32, 32) Tensors, and maybe a MOD bug with const folding - "briaai/RMBG-2.0", -] - - -class HuggingFaceONNXManager: - def __init__(self): - self.base_dir = Path(__file__).parent - self.models_dir = DOWNLOADS_DIR - self.api = HfApi() - - def discover_models(self, limit: int, sort: str = "downloads") -> list[str]: - print(f"Discovering top {limit} ONNX models sorted by {sort}...") - repos = [] - i = 0 - - for model in list_models(filter="onnx", sort=sort): - if model.id in SKIPPED_REPO_PATHS: - continue - - print(f" {i+1}/{limit}: {model.id} ({getattr(model, sort)})") - repos.append(model.id) - i += 1 - if i == limit: - break - - print(f"Found {len(repos)} suitable ONNX models") - return repos - - def collect_metadata(self, repos: list[str]) -> dict: - print(f"Collecting metadata for {len(repos)} repositories...") - metadata = {"repositories": {}} - total_size = 0 - - for repo in tqdm(repos, desc="Collecting metadata"): - try: - files_metadata = [] - model_info = self.api.model_info(repo) - - for file in model_info.siblings: - filename = file.rfilename - if not (filename.endswith('.onnx') or filename.endswith('.onnx_data')): - continue - if any(skip_str in filename for skip_str in SKIPPED_FILES): - continue - - # Get file size from API or HEAD request - try: - head = requests.head( - f"{HUGGINGFACE_URL}/{repo}/resolve/main/{filename}", - allow_redirects=True, - timeout=10 - ) - file_size = file.size or int(head.headers.get('Content-Length', 0)) - except requests.RequestException: - file_size = file.size or 0 - - files_metadata.append({ - "file": filename, - "size": f"{file_size/1e6:.2f}MB" - }) - total_size += file_size - - if files_metadata: # Only add repos with valid ONNX files - metadata["repositories"][repo] = { - "url": f"{HUGGINGFACE_URL}/{repo}", - "download_path": None, - "files": files_metadata, - } - - except Exception as e: - print(f"WARNING: Failed to collect metadata for {repo}: {e}") - continue - - metadata['total_size'] = f"{total_size/1e9:.2f}GB" - metadata['created_at'] = time.strftime("%Y-%m-%dT%H:%M:%SZ", time.gmtime()) - - print(f"Collected metadata for {len(metadata['repositories'])} repositories") - print(f"Total estimated download size: {metadata['total_size']}") - - return metadata - - def download_models(self, metadata: dict) -> dict: - self.models_dir.mkdir(parents=True, exist_ok=True) - - repos = metadata["repositories"] - n = len(repos) - - print(f"Downloading {n} repositories to {self.models_dir}...") - - for i, (model_id, model_data) in enumerate(repos.items()): - print(f" Downloading {i+1}/{n}: {model_id}...") - - try: - # Download ONNX model files - allow_patterns = [file_info["file"] for file_info in model_data["files"]] - root_path = snapshot_download_with_retry( - repo_id=model_id, - allow_patterns=allow_patterns, - cache_dir=str(self.models_dir) - ) - - # Download config files (usually small) - snapshot_download_with_retry( - repo_id=model_id, - allow_patterns=["*config.json"], - cache_dir=str(self.models_dir) - ) - - model_data["download_path"] = str(root_path) - print(f" Downloaded to: {root_path}") - - except Exception as e: - print(f" ERROR: Failed to download {model_id}: {e}") - model_data["download_path"] = None - continue - - successful_downloads = sum(1 for repo in repos.values() if repo["download_path"] is not None) - print(f"Successfully downloaded {successful_downloads}/{n} repositories") - print(f"All models saved to: {self.models_dir}") - - return metadata - - def save_metadata(self, metadata: dict, output_file: str): - yaml_path = self.base_dir / output_file - with open(yaml_path, 'w') as f: - yaml.dump(metadata, f, sort_keys=False) - print(f"Metadata saved to: {yaml_path}") - - def discover_and_download(self, limit: int, output_file: str = "huggingface_repos.yaml", - sort: str = "downloads", download: bool = True): - print(f"Starting HuggingFace ONNX workflow...") - print(f" Limit: {limit} models") - print(f" Sort by: {sort}") - print(f" Download: {'Yes' if download else 'No'}") - print(f" Output: {output_file}") - print("-" * 50) - - repos = self.discover_models(limit, sort) - - metadata = self.collect_metadata(repos) - - if download: - metadata = self.download_models(metadata) - - self.save_metadata(metadata, output_file) - - print("-" * 50) - print("Workflow completed successfully!") - if download: - successful = sum(1 for repo in metadata["repositories"].values() - if repo["download_path"] is not None) - print(f"{successful}/{len(metadata['repositories'])} models downloaded") - - return metadata - - -if __name__ == "__main__": - parser = argparse.ArgumentParser( - description="HuggingFace ONNX Model Manager - Discover, collect metadata, and download ONNX models", - ) - - parser.add_argument("--limit", type=int, help="Number of top repositories to process") - parser.add_argument("--output", type=str, default="huggingface_repos.yaml", - help="Output YAML file name (default: huggingface_repos.yaml)") - parser.add_argument("--sort", type=str, default="downloads", - choices=["downloads", "likes", "created", "modified"], - help="Sort criteria for model discovery (default: downloads)") - - parser.add_argument("--download", action="store_true", default=False, - help="Download models after collecting metadata") - - args = parser.parse_args() - - if not args.limit: parser.error("--limit is required") - - manager = HuggingFaceONNXManager() - manager.discover_and_download( - limit=args.limit, - output_file=args.output, - sort=args.sort, - download=args.download - ) \ No newline at end of file diff --git a/tinygrad_repo/extra/huggingface_onnx/run_models.py b/tinygrad_repo/extra/huggingface_onnx/run_models.py index fa8771a11..af920f8cf 100644 --- a/tinygrad_repo/extra/huggingface_onnx/run_models.py +++ b/tinygrad_repo/extra/huggingface_onnx/run_models.py @@ -1,11 +1,10 @@ -import onnx, yaml, tempfile, time, argparse, json +import onnx, yaml, tempfile, time, collections, pprint, argparse, json from pathlib import Path -from typing import Any -from tinygrad.frontend.onnx import OnnxRunner +from tinygrad.frontend.onnx import OnnxRunner, onnx_load +from extra.onnx import get_onnx_ops from extra.onnx_helpers import validate, get_example_inputs -from extra.huggingface_onnx.huggingface_manager import DOWNLOADS_DIR, snapshot_download_with_retry -def get_config(root_path: Path) -> dict[str, Any]: +def get_config(root_path: Path): ret = {} for path in root_path.rglob("*config.json"): config = json.load(path.open()) @@ -13,19 +12,20 @@ def get_config(root_path: Path) -> dict[str, Any]: ret.update(config) return ret -def get_tolerances(file_name: str) -> tuple[float, float]: +def run_huggingface_validate(onnx_model_path, config, rtol, atol): + onnx_model = onnx_load(onnx_model_path) + onnx_runner = OnnxRunner(onnx_model) + inputs = get_example_inputs(onnx_runner.graph_inputs, config) + validate(onnx_model_path, inputs, rtol=rtol, atol=atol) + +def get_tolerances(file_name): # -> rtol, atol # TODO very high rtol atol if "fp16" in file_name: return 9e-2, 9e-2 if any(q in file_name for q in ["int8", "uint8", "quantized"]): return 4, 4 return 4e-3, 3e-2 -def run_huggingface_validate(onnx_model_path: str | Path, config: dict[str, Any], rtol: float, atol: float): - onnx_runner = OnnxRunner(onnx_model_path) - inputs = get_example_inputs(onnx_runner.graph_inputs, config) - validate(onnx_model_path, inputs, rtol=rtol, atol=atol) - def validate_repos(models:dict[str, tuple[Path, Path]]): - print(f"** Validating {len(models)} models **") + print(f"** Validating {len(model_paths)} models **") for model_id, (root_path, relative_path) in models.items(): print(f"validating model {model_id}") model_path = root_path / relative_path @@ -37,6 +37,25 @@ def validate_repos(models:dict[str, tuple[Path, Path]]): et = time.time() - st print(f"passed, took {et:.2f}s") +def retrieve_op_stats(models:dict[str, tuple[Path, Path]]) -> dict: + ret = {} + op_counter = collections.Counter() + unsupported_ops = collections.defaultdict(set) + supported_ops = get_onnx_ops() + print(f"** Retrieving stats from {len(model_paths)} models **") + for model_id, (root_path, relative_path) in models.items(): + print(f"examining {model_id}") + model_path = root_path / relative_path + onnx_runner = OnnxRunner(onnx.load(model_path)) + for node in onnx_runner.graph_nodes: + op_counter[node.op] += 1 + if node.op not in supported_ops: + unsupported_ops[node.op].add(model_id) + del onnx_runner + ret["unsupported_ops"] = {k:list(v) for k, v in unsupported_ops.items()} + ret["op_counter"] = op_counter.most_common() + return ret + def debug_run(model_path, truncate, config, rtol, atol): if truncate != -1: model = onnx.load(model_path) @@ -53,9 +72,12 @@ def debug_run(model_path, truncate, config, rtol, atol): run_huggingface_validate(model_path, config, rtol, atol) if __name__ == "__main__": - parser = argparse.ArgumentParser(description="Huggingface ONNX Model Validator") - parser.add_argument("--validate", type=str, default="", - help="Validate correctness of models from the specified YAML configuration file") + parser = argparse.ArgumentParser(description="Huggingface ONNX Model Validator and Ops Checker") + parser.add_argument("input", type=str, help="Path to the input YAML configuration file containing model information.") + parser.add_argument("--check_ops", action="store_true", default=False, + help="Check support for ONNX operations in models from the YAML file") + parser.add_argument("--validate", action="store_true", default=False, + help="Validate correctness of models from the YAML file") parser.add_argument("--debug", type=str, default="", help="""Validates without explicitly needing a YAML or models pre-installed. provide repo id (e.g. "minishlab/potion-base-8M") to validate all onnx models inside the repo @@ -64,13 +86,13 @@ if __name__ == "__main__": parser.add_argument("--truncate", type=int, default=-1, help="Truncate the ONNX model so intermediate results can be validated") args = parser.parse_args() - if not (args.validate or args.debug): - parser.error("Please provide either --validate or --debug .") + if not (args.check_ops or args.validate or args.debug): + parser.error("Please provide either --validate, --check_ops, or --debug.") if args.truncate != -1 and not args.debug: parser.error("--truncate and --debug should be used together for debugging") - if args.validate: - with open(args.validate, 'r') as f: + if args.check_ops or args.validate: + with open(args.input, 'r') as f: data = yaml.safe_load(f) assert all(repo["download_path"] is not None for repo in data["repositories"].values()), "please run `download_models.py` for this yaml" model_paths = { @@ -80,16 +102,22 @@ if __name__ == "__main__": if model["file"].endswith(".onnx") } - validate_repos(model_paths) + if args.check_ops: + pprint.pprint(retrieve_op_stats(model_paths)) + + if args.validate: + validate_repos(model_paths) if args.debug: + from huggingface_hub import snapshot_download + download_dir = Path(__file__).parent / "models" path:list[str] = args.debug.split("/") if len(path) == 2: # repo id # validates all onnx models inside repo repo_id = "/".join(path) - root_path = snapshot_download_with_retry(repo_id=repo_id, allow_patterns=["*.onnx", "*.onnx_data"], cache_dir=DOWNLOADS_DIR) - snapshot_download_with_retry(repo_id=repo_id, allow_patterns=["*config.json"], cache_dir=DOWNLOADS_DIR) + root_path = Path(snapshot_download(repo_id=repo_id, allow_patterns=["*.onnx", "*.onnx_data"], cache_dir=download_dir)) + snapshot_download(repo_id=repo_id, allow_patterns=["*config.json"], cache_dir=download_dir) config = get_config(root_path) for onnx_model in root_path.rglob("*.onnx"): rtol, atol = get_tolerances(onnx_model.name) @@ -101,8 +129,8 @@ if __name__ == "__main__": onnx_model = path[-1] assert path[-1].endswith(".onnx") repo_id, relative_path = "/".join(path[:2]), "/".join(path[2:]) - root_path = snapshot_download_with_retry(repo_id=repo_id, allow_patterns=[relative_path], cache_dir=DOWNLOADS_DIR) - snapshot_download_with_retry(repo_id=repo_id, allow_patterns=["*config.json"], cache_dir=DOWNLOADS_DIR) + root_path = Path(snapshot_download(repo_id=repo_id, allow_patterns=[relative_path], cache_dir=download_dir)) + snapshot_download(repo_id=repo_id, allow_patterns=["*config.json"], cache_dir=download_dir) config = get_config(root_path) rtol, atol = get_tolerances(onnx_model) print(f"validating {relative_path} with truncate={args.truncate}, {rtol=}, {atol=}") diff --git a/tinygrad_repo/extra/mcts_search.py b/tinygrad_repo/extra/mcts_search.py index 731fab11f..562d11bc1 100644 --- a/tinygrad_repo/extra/mcts_search.py +++ b/tinygrad_repo/extra/mcts_search.py @@ -4,10 +4,9 @@ import numpy as np np.set_printoptions(suppress=True) import math, functools, time, random, statistics from tinygrad.helpers import DEBUG, getenv, CACHELEVEL, diskcache_get, diskcache_put, colored, Profiling -from tinygrad.codegen.opt.kernel import Kernel +from tinygrad.opt.kernel import Kernel from tinygrad.device import Buffer, Device, CompileError -from tinygrad.codegen.opt.search import _ensure_buffer_alloc, get_kernel_actions, _time_program -from tinygrad.engine.realize import get_program +from tinygrad.opt.search import _ensure_buffer_alloc, get_kernel_actions, _time_program class MCTSNode: def __init__(self, kernel:Kernel, parent=None): @@ -111,7 +110,7 @@ def mcts_search(lin:Kernel, rawbufs:List[Buffer], amt:int) -> Kernel: seen_asts[opt_ast.key] = node # lowering (50% of the time) - p = get_program(node.kernel.get_optimized_ast(name_override="test"), node.kernel.opts) + p = node.kernel.to_program(name_override="test") # rollout tm1 = time.perf_counter() diff --git a/tinygrad_repo/extra/models/llama.py b/tinygrad_repo/extra/models/llama.py index 6d2d584d8..16e1aea0b 100644 --- a/tinygrad_repo/extra/models/llama.py +++ b/tinygrad_repo/extra/models/llama.py @@ -99,9 +99,7 @@ class FeedForward: self.w3 = linear(dim, hidden_dim, bias=False) # the gate in Gated Linear Unit def __call__(self, x:Tensor) -> Tensor: - w1 = self.w1(x).silu() - w3 = self.w3(x.contiguous_backward()) # this fixes a strange fusion that makes tensor cores miss - return self.w2(w1 * w3) + return self.w2(self.w1(x).silu() * self.w3(x)) # SwiGLU [arxiv/2002.05202, eq (5)] class TransformerBlock: def __init__(self, dim:int, hidden_dim:int, n_heads:int, n_kv_heads:int, norm_eps:float, max_context:int, linear=nn.Linear, @@ -113,7 +111,7 @@ class TransformerBlock: def __call__(self, x:Tensor, start_pos:Union[Variable,int], freqs_cis:Tensor, mask:Optional[Tensor]): h = x + self.attention(self.attention_norm(x), start_pos, freqs_cis, mask) - return (h + self.feed_forward(self.ffn_norm(h))).contiguous().contiguous_backward() + return (h + self.feed_forward(self.ffn_norm(h))).contiguous() # standard openai sampling def sample(logits: Tensor, temp: float, k: int, p: float, af: float, ap: float): @@ -181,14 +179,16 @@ class Transformer: def forward(self, tokens:Tensor, start_pos:Union[Variable,int], temperature:float, top_k:int, top_p:float, alpha_f:float, alpha_p:float): _bsz, seqlen = tokens.shape h = self.tok_embeddings(tokens) - freqs_cis = self.freqs_cis.cast(h.dtype)[:, start_pos:start_pos+seqlen, :, :, :] + + self.freqs_cis = self.freqs_cis.cast(h.dtype).contiguous() + freqs_cis = self.freqs_cis[:, start_pos:start_pos+seqlen, :, :, :] mask = Tensor.full((1, 1, seqlen, start_pos+seqlen), float("-inf"), dtype=h.dtype, device=h.device).triu(start_pos+1) if seqlen > 1 else None for layer in self.layers: h = layer(h, start_pos, freqs_cis, mask) - logits = self.output(self.norm(h)) + logits = self.output(self.norm(h)).float()[:, -1, :] if math.isnan(temperature): return logits - return sample(logits[:, -1, :].flatten(), temperature, top_k, top_p, alpha_f, alpha_p) + return sample(logits.flatten(), temperature, top_k, top_p, alpha_f, alpha_p) def __call__(self, tokens:Tensor, start_pos:int, temperature:float=0.0, top_k:int=0, top_p:float=0.8, alpha_f:float=0.0, alpha_p:float=0.0): # TODO: better way to handle the first call v.s. the rest? diff --git a/tinygrad_repo/extra/nv_gpu_driver/vbios.h b/tinygrad_repo/extra/nv_gpu_driver/vbios.h index 18dfec63d..6721caf7e 100644 --- a/tinygrad_repo/extra/nv_gpu_driver/vbios.h +++ b/tinygrad_repo/extra/nv_gpu_driver/vbios.h @@ -27,20 +27,6 @@ #include "gpu/vbios/bios_types.h" #define FALCON_APPLICATION_INTERFACE_ENTRY_ID_DMEMMAPPER (0x4) -typedef struct -{ - NvU8 version; - NvU8 headerSize; - NvU8 entrySize; - NvU8 entryCount; -} __attribute__((packed)) FALCON_APPLICATION_INTERFACE_HEADER_V1; - -typedef struct -{ - NvU32 id; - NvU32 dmemOffset; -} __attribute__((packed)) FALCON_APPLICATION_INTERFACE_ENTRY_V1; - typedef struct { NvU32 signature; diff --git a/tinygrad_repo/extra/nvpci/gpu_reset.sh b/tinygrad_repo/extra/nvpci/gpu_reset.sh new file mode 100755 index 000000000..a76103675 --- /dev/null +++ b/tinygrad_repo/extra/nvpci/gpu_reset.sh @@ -0,0 +1,2 @@ +GPU="$1" +echo 1 | sudo tee /sys/bus/pci/devices/$GPU/reset 2>/dev/null diff --git a/tinygrad_repo/extra/onnx.py b/tinygrad_repo/extra/onnx.py new file mode 100644 index 000000000..483a5ae71 --- /dev/null +++ b/tinygrad_repo/extra/onnx.py @@ -0,0 +1,845 @@ +from types import SimpleNamespace +from typing import Any, Sequence, cast, Literal, Callable +import dataclasses, functools, io, math, types, warnings +from tinygrad.tensor import Tensor, _broadcast_shape, ReductionStr +from tinygrad.helpers import getenv, DEBUG, all_same, prod, flatten, make_tuple, argsort +from tinygrad.dtype import DType, ConstType, dtypes, ImageDType +from tinygrad.device import is_dtype_supported, Device + +# https://github.com/onnx/onnx/blob/rel-1.17.0/onnx/onnx.proto3#L500-L544 +data_types: dict[int, DType] = { + 1:dtypes.float32, 2:dtypes.uint8, 3:dtypes.int8, 4:dtypes.uint16, 5:dtypes.int16, 6:dtypes.int32, 7:dtypes.int64, + 9:dtypes.bool, 10:dtypes.float32, 11:dtypes.double, 12:dtypes.uint32, 13:dtypes.uint64, 16:dtypes.bfloat16, +} + +# https://github.com/onnx/onnx/blob/rel-1.17.0/onnx/onnx.proto3#L128-L145 +attribute_types: dict[int, Callable] = { + 1: lambda a: float(a.f), + 2: lambda a: int(a.i), + 3: lambda a: a.s.data().tobytes().decode("utf8") if isinstance(a.s, Tensor) else a.s.decode("utf8"), + 4: lambda a: buffer_parse(a.t), + 6: lambda a: tuple(float(x) for x in a.floats), + 7: lambda a: tuple(int(x) for x in a.ints), + 8: lambda a: tuple(x.data().tobytes().decode("utf8") for x in a.strings) +} + +# ***** protobuf parsing ****** +from onnx import AttributeProto, ModelProto, TensorProto, TypeProto, helper +import numpy as np + +def has_field(onnx_type: TypeProto|SimpleNamespace, field): + if isinstance(onnx_type, TypeProto): return onnx_type.HasField(field) + return hasattr(onnx_type, field) + +def dtype_parse(onnx_dtype: int, fallback_context: str | None = None) -> DType: + if onnx_dtype not in data_types: raise NotImplementedError(f"onnx dtype id {onnx_dtype} is not supported") + if is_dtype_supported(dtype := data_types[onnx_dtype]): return dtype + # if fallback_context is provided, we can fall back to a default dtype + if fallback_context is not None: + default_dtype = dtypes.default_int if dtypes.is_int(dtype) else dtypes.default_float + warnings.warn(f"dtype {dtype} on {Device.DEFAULT} from {fallback_context} is not supported, falling back to {default_dtype}") + assert is_dtype_supported(default_dtype), f"dtype {default_dtype} must be supported on {Device.DEFAULT}" + return default_dtype + raise RuntimeError(f"dtype {dtype} on device {Device.DEFAULT} is not supported") + +def attribute_parse(onnx_attribute: AttributeProto): + if onnx_attribute.type not in attribute_types: raise NotImplementedError(f"attribute type {onnx_attribute.type} is not supported") + return attribute_types[onnx_attribute.type](onnx_attribute) + +def buffer_parse(onnx_tensor: TensorProto) -> Tensor: + if onnx_tensor.string_data: raise NotImplementedError("Parsing for buffer with string data is not implemented.") + dtype, shape = dtype_parse(onnx_tensor.data_type, "buffer parse"), tuple(onnx_tensor.dims) + data = None + if len(onnx_tensor.float_data): data = onnx_tensor.float_data + elif len(onnx_tensor.int32_data): data = onnx_tensor.int32_data + elif len(onnx_tensor.int64_data): data = onnx_tensor.int64_data + elif len(onnx_tensor.double_data): data = onnx_tensor.double_data + elif len(onnx_tensor.uint64_data): data = onnx_tensor.uint64_data + if isinstance(data, Tensor): + if len(data) == 1: return Tensor(data.tolist()[0], dtype=dtype).reshape(shape) + return data.cast(dtype).reshape(shape).to(Device.DEFAULT) + if has_field(onnx_tensor, "raw_data"): + raw_data = onnx_tensor.raw_data + if not isinstance(raw_data, Tensor): raw_data = Tensor(raw_data) + if onnx_tensor.data_type == TensorProto.FLOAT16 or not is_dtype_supported(data_types[onnx_tensor.data_type]): + np_buffer = np.frombuffer(raw_data.data().tobytes(), + dtype=helper.tensor_dtype_to_np_dtype(onnx_tensor.data_type)).copy().reshape(shape) + if np_buffer.size == 1: return Tensor(np_buffer.item(), dtype=dtype).reshape(shape) + return Tensor(np_buffer, dtype=dtype) + ret = raw_data.bitcast(dtype).reshape(shape).to(Device.DEFAULT) + if shape == (): ret = Tensor(ret.item(), dtype=dtype).reshape(shape) + return ret + return Tensor(None) + +def type_parse(onnx_type: TypeProto): + elem_type = onnx_type + if has_field(elem_type, "map_type") or has_field(elem_type, "sparse_tensor_type") or has_field(elem_type, "opaque_type"): + raise NotImplementedError("parsing for map_type, sparse_tensor_type and opaque_type are not implemented") + if is_optional := has_field(elem_type, "optional_type"): elem_type = elem_type.optional_type.elem_type + if is_sequence := has_field(elem_type, "sequence_type"): elem_type = elem_type.sequence_type.elem_type + if has_field(elem_type, "tensor_type"): + shape = tuple(getattr(d, "dim_param", None) or getattr(d, "dim_value") for d in elem_type.tensor_type.shape.dim) \ + if has_field(elem_type.tensor_type, "shape") else None # test_identity_sequence_cpu + dtype = dtype_parse(elem_type.tensor_type.elem_type, "input type spec parse") + return OnnxValue(shape, dtype, is_optional, is_sequence) + raise RuntimeError(f"TypeProto was not parsed properly: {onnx_type=}") + +# ***** onnx spec ***** +@dataclasses.dataclass(frozen=True) +class OnnxValue: + shape: tuple[str|int, ...] + dtype: DType + is_optional: bool + is_sequence: bool + +@dataclasses.dataclass(frozen=True) +class OnnxNode: + num: int + op: str + inputs: tuple[str, ...] + outputs: tuple[str, ...] + opts: dict[str, Any] + +# ***** python const ***** +required_input_python_consts: dict[str, tuple[int, ...]] = { + "Tile": (1,), "Range": (0,1,2), "Expand": (1,), "Reshape": (1,), "Squeeze": (1,), "Unsqueeze": (1,), "Trilu": (1,), "ConstantOfShape": (0,), + "CumSum": (1,), "TopK": (1,), "Pad": (1,2,3), "MaxUnpool": (2,), "Dropout": (1,2), "CenterCropPad": (1,), "OneHot": (1,), "Compress": (1,), + "ImageDecoder": (0,), "AffineGrid": (1,), "Resize": (1,2,3), "Upsample": (1,), "Split": (1,), "Slice": (1,2,3,4), + **{"Reduce"+r: (1,) for r in ("Max", "Min", "Sum", "Mean", "SumSquare", "Prod", "L1", "L2", "LogSum", "LogSumExp")}, + **{optim: (1,) for optim in ("Adam", "Adagrad", "Momentum")} +} + +cache_misses = 0 +@functools.cache +def _cached_to_python_const(t:Tensor): + if t.dtype is dtypes.uint8: return t.data().tobytes() + if 0 in t.shape: return [] + return t.tolist() + +# Tensor -> python value cache for parameters +def to_python_const(t:Any, op:str, idx:int) -> list[ConstType]|ConstType|bytes: + if idx not in required_input_python_consts.get(op, ()) or not isinstance(t, Tensor): return t + global cache_misses + ret = _cached_to_python_const(t) + if (info := _cached_to_python_const.cache_info()).misses > cache_misses and DEBUG >= 3: + print(f"Cache miss for {t}") + cache_misses = info.misses + return ret + +# ***** runner ****** +debug = int(getenv("DEBUGONNX", "0")) +limit = int(getenv("ONNXLIMIT", "-1")) +class OnnxRunner: + def __init__(self, model: ModelProto|SimpleNamespace): + # parse model protobuf + self.is_training = any(n.domain in {"ai.onnx.training", "ai.onnx.preview.training"} for n in model.graph.node) + self.old_training = Tensor.training + Tensor.training = True if self.is_training else False + self.graph_values = {"": None, **{x.name:buffer_parse(x) for x in model.graph.initializer}} + self.graph_inputs = {x.name:type_parse(x.type) for x in model.graph.input if x.name not in self.graph_values} + self.graph_outputs = tuple(x.name for x in model.graph.output) + self.graph_nodes = tuple(OnnxNode(num, n.op_type, tuple(n.input), tuple(n.output), {x.name:attribute_parse(x) for x in n.attribute}) + for num,n in enumerate(model.graph.node)) + self.opset_version = model.opset_import[0].version + self.variable_dims: dict[str, int] = {} + + self.onnx_ops = onnx_ops + + def _parse_input(self, name: str, value: Any, spec: OnnxValue): + if spec.is_optional and value is None: return None + # TODO: need true float16 for dtype checking + if spec.is_sequence: + if not isinstance(value, Sequence): raise RuntimeError(f"input {name} received {value}, expected a sequence type") + sequence = [Tensor(v, dtype=spec.dtype, requires_grad=self.is_training) if not isinstance(v, Tensor) else v for v in value] + if not all_same(tuple(t.shape for t in sequence)): raise RuntimeError(f"Shapes for input {name} sequence must be homogeneous") + return sequence + tensor = Tensor(value, dtype=spec.dtype, requires_grad=self.is_training) if not isinstance(value, Tensor) else value + for dim, (onnx_dim, user_dim_input) in enumerate(zip(spec.shape, tensor.shape, strict=True)): + if isinstance(onnx_dim, str): + onnx_dim = self.variable_dims[onnx_dim] if onnx_dim in self.variable_dims else self.variable_dims.setdefault(onnx_dim, int(user_dim_input)) + if user_dim_input != onnx_dim: raise RuntimeError(f"input {name} has mismatch on {dim=}. Expected {onnx_dim}, received {user_dim_input}.") + return tensor + + def _dispatch_op(self, op, inps, opts): + if op in self.onnx_ops: + fxn = self.onnx_ops[op] + if isinstance(fxn, dict): + for k in sorted(fxn.keys()): + if k <= self.opset_version: + real_fxn = fxn[k] + else: real_fxn = fxn + return real_fxn(*inps, **opts) + raise NotImplementedError(f"{op=} not supported") + + def get_empty_input_data(self, device:str|None=None) -> dict[str, Tensor]: + return {name:Tensor.empty(*spec.shape, device=device, dtype=spec.dtype) for name, spec in self.graph_inputs.items()} + + def __call__(self, inputs:dict[str, Any], debug=debug): + for name, input_spec in self.graph_inputs.items(): + if name not in inputs: raise RuntimeError(f"Please provide input data for {name}") + self.graph_values[name] = self._parse_input(name, inputs[name], input_spec) + + for node in self.graph_nodes: + inps = [to_python_const(self.graph_values[name], node.op, i) for i,name in enumerate(node.inputs)] + opts = node.opts + + # provide additional opts + if node.op == "Split" and 'num_outputs' not in opts: opts['num_outputs'] = len(node.outputs) + if node.op == "Gradient": opts['intermediate_tensors'] = self.graph_values + + if debug >= 1: print(f"{node.num}: op '{node.op}' opt {opts}") + if debug >= 2 and node.inputs: print("\tinputs:\n" + "\n".join(f"\t\t{x} - {i!r}" for x,i in zip(node.inputs, inps))) + ret = self._dispatch_op(node.op, inps, opts) + ret = ret if isinstance(ret, tuple) else (ret,) + if debug >= 2: print("\toutputs:\n" + "\n".join(f"\t\t{x} - {o!r}" for x,o in zip(node.outputs, ret))) + + self.graph_values.update(dict(zip(node.outputs, ret[:len(node.outputs)], strict=True))) + + if node.num == limit: + Tensor.training = self.old_training + return {name:self.graph_values[name] for name in node.outputs} + Tensor.training = self.old_training + return {name:self.graph_values[name] for name in self.graph_outputs} + +#################### +##### ONNX OPS ##### +#################### +def get_onnx_ops(): + # ***** helper functions ***** + def _axes(axes, noop_with_empty_axes): return axes or ([] if noop_with_empty_axes else None) + + # (padding_top, padding_left, ..., padding_bottom, padding_right, ...) -> (padding_left, padding_right, padding_top, padding_bottom, ...) + def _onnx_pads_to_tiny_pads(pads): return tuple(flatten(reversed(list(zip(pads, pads[len(pads)//2:]))))) + + AUTO_PAD_OPTIONS = Literal["NOTSET", "SAME_UPPER", "SAME_LOWER", "VALID"] + # (padding_height, padding_width) -> (padding_top, padding_left, padding_bottom, padding_right) + def _auto_pad(pads, auto_pad: AUTO_PAD_OPTIONS): + if auto_pad == "SAME_UPPER": return [pads[i]//2 for i in range(len(pads))] + [pads[i]-pads[i]//2 for i in range(len(pads))] + return [pads[i]-pads[i]//2 for i in range(len(pads))] + [pads[i]//2 for i in range(len(pads))] + + def _resolve_pool_pads(x:Tensor, p_, k_, d_, s_, auto_pad:AUTO_PAD_OPTIONS): + if auto_pad == "VALID": return [0]*(len(k_)*2) + i_, (s_,d_,p_) = x.shape[-len(k_):], (make_tuple(x, len(k_)*2) for x in (s_, d_, p_)) + if auto_pad == "NOTSET": return _onnx_pads_to_tiny_pads(p_ if len(p_)==len(k_)*2 else p_*2) + o_ = [((i - (1 if auto_pad in ("SAME_UPPER", "SAME_LOWER") else k)) // s + 1) for i,k,s in zip(i_, k_, s_)] + return _onnx_pads_to_tiny_pads(_auto_pad([(o-1)*s+k-i for o,i,k,s in zip(o_, i_, k_, s_)], auto_pad)) + + def _clamp_cast(x:Tensor, dtype:DType): return x.clamp(dtypes.min(dtype), dtypes.max(dtype)).cast(dtype) + + def _prepare_quantize(x:Tensor, scale:Tensor, zero_point:Tensor|int, axis=1, block_size=0): + if axis < 0: axis += x.ndim + # https://github.com/onnx/onnx/blob/main/onnx/reference/ops/op_quantize_linear.py#L31 + def reshape(val:Tensor): + if val.numel() == 1: return val + if block_size == 0: return val.reshape([val.shape[0] if dim == axis else 1 for dim in range(x.ndim)]) + return val.repeat_interleave(block_size, axis) + return (reshape(scale), reshape(zero_point) if isinstance(zero_point, Tensor) else zero_point) + + def _op_integer(op, inputs:list[Tensor], zero_points:list[Tensor], **opts): + adjusted_inputs = [inp.int() - zp for inp, zp in zip(inputs, zero_points)] + return op(*adjusted_inputs, **opts) + + def _qlinearop_quantized(op, inputs:list[Tensor], zero_points:list[Tensor], scales:list[Tensor], out_scale:Tensor, out_zero_point:Tensor, **opts): + # op execution is done in quantized int + out = _op_integer(op, inputs, zero_points, **opts) + assert dtypes.is_int(out.dtype), "quantized op should've done math in int" + out_quantized = (out * prod(scales) / out_scale).round() + out_zero_point + return _clamp_cast(out_quantized, out_zero_point.dtype) + + def _qlinearop_float(op, inputs:list[Tensor], zero_points:list[Tensor], scales:list[Tensor], out_scale:Tensor, out_zero_point:Tensor, **opts): + # op execution is done in float32 + dequantized_inputs = [(inp.int() - zp) * scale for inp, zp, scale in zip(inputs, zero_points, scales)] + out = op(*dequantized_inputs, **opts) + assert dtypes.is_float(out.dtype), "op should've done math in float" + out_quantized = (out / out_scale).round() + out_zero_point + return _clamp_cast(out_quantized, out_zero_point.dtype) + + def _onnx_training(input_group_size): + def __decorator(func): + def ___wrapper(R:Tensor, T:int, *inputs:Tensor, **kwargs): + R = R.detach() + groups = len(inputs) // input_group_size + ret = [func(R, T, *inps, **kwargs) for inps in (inputs[i::groups] for i in range(groups))] + return tuple(flatten(zip(*ret))) + return ___wrapper + return __decorator + + # ***** Property/Graph Ops ***** + def Identity(x:Tensor): return x + def Constant(sparse_value:Tensor|None=None, value:Tensor|None=None, value_float:float|None=None, value_floats:list[float]|None=None, + value_int:int|None=None, value_ints:list[int]|None=None, value_string:str|None=None, value_strings:list[str]|None=None): + if value is not None: return value + if value_float is not None: return Tensor(value_float, dtype=dtypes.float32, requires_grad=False) + if value_floats is not None: return Tensor(list(value_floats), dtype=dtypes.float32, requires_grad=False) + if value_int is not None: return Tensor(value_int, dtype=dtypes.int64, requires_grad=False) + if value_ints is not None: return Tensor(list(value_ints), dtype=dtypes.int64, requires_grad=False) + if value_string is not None or value_strings is not None and sparse_value is not None: + raise NotImplementedError('Constant OP not implemented for value_string, value_strings and sparse_value') + + def Range(start:float|int, limit:float|int, delta:float|int): return Tensor.arange(start=start, stop=limit, step=delta) + + def ImageDecoder(encoded_stream:bytes, pixel_format="RGB"): + try: import PIL.Image + except ImportError as e: raise ImportError("Pillow must be installed for the ImageDecoder operator") from e + img = PIL.Image.open(io.BytesIO(encoded_stream)) + if pixel_format == "BGR": return Tensor(img.tobytes(), dtype=dtypes.uint8).reshape(*img.size, 3).flip(-1) + if pixel_format == "RGB": return Tensor(img.tobytes(), dtype=dtypes.uint8).reshape(*img.size, 3) + if pixel_format == "Grayscale": return Tensor(img.convert("L").tobytes(), dtype=dtypes.uint8).reshape(*img.size, 1) + raise ValueError(f"pixel_format={pixel_format!r} is not supported.") + + def EyeLike(x:Tensor, dtype:int|None=None, k:int=0): + ret = Tensor.eye(cast(int, min(x.shape)), dtype=dtype_parse(dtype, "EyeLike op") if dtype is not None else x.dtype) + return ret if x.size(0) == x.size(1) else ret.pad(tuple(None if d == ret.size(0) else (k, d-ret.shape[0]-k) for d in x.shape)) + + def OptionalHasElement(x:Tensor|None=None): return Tensor(x is not None and x.numel() > 0) + def OptionalGetElement(x:Tensor|None=None): return x if x is not None else Tensor([]) + def ConstantOfShape(shape:list[int], value:Tensor|None=None): + if value is None: value = Tensor(0, dtype=dtypes.float32) + if shape == [0]: return Tensor([], dtype=value.dtype) + return value.expand(shape) + + def Size(data:Tensor): return data.numel() + def Shape(data:Tensor, end:int|None=None, start:int=0): return Tensor(data.shape[start:end], dtype=dtypes.int64) + + # ***** Unary Ops (math) ***** + def Not(x:Tensor): return x.logical_not() + def Clip(x: Tensor, min:Tensor|None=None, max:Tensor|None=None): return x if min is None and max is None else x.clip(min, max) + def IsInf(x:Tensor, detect_negative:int=1, detect_positive:int=1): return x.isinf(bool(detect_positive), bool(detect_negative)) + + # ***** Unary Ops (activation) ***** + def Softmax_1(x:Tensor, axis:int=1): return x.softmax(axis) + def Softmax_13(x:Tensor, axis:int=-1): return x.softmax(axis) + Softmax = {1:Softmax_1, 13:Softmax_13} + def HardSigmoid(x:Tensor, alpha:float=0.2, beta:float=0.5): return (alpha*x + beta).clip(0, 1) + def Gelu(x:Tensor, approximate:str|None=None): return x.gelu() if approximate == "tanh" else 0.5 * x * (1 + (x/math.sqrt(2)).erf()) + def BiasGelu(x: Tensor, bias: Tensor, approximate: str | None = None) -> Tensor: return Gelu(x + bias, approximate) + def FastGelu(x:Tensor, bias:Tensor|None=None): return (x + bias).gelu() if bias is not None else x.gelu() # this is tanh approximated + def PRelu(X:Tensor, slope:Tensor): return (X > 0).where(X, X * slope) + def LeakyRelu(X:Tensor, alpha:float=0.01): return X.leaky_relu(alpha) + def ThresholdedRelu(X:Tensor, alpha:float=1.0): return (X > alpha).where(X, 0) + def LogSoftmax(x: Tensor, axis:int=-1): return x.log_softmax(axis) + def Binarizer(x:Tensor, threshold:float=0.0): return (x > threshold).float() + + # ***** Unary Ops (broadcasted) ***** + def Add(x:Tensor,y:Tensor, broadcast=None, axis=None): return x + y if x.dtype == dtypes.float or isinstance(x.dtype, ImageDType) else (x + y).cast(x.dtype) + def Sub(x:Tensor|int,y:Tensor): return x - y # some test has input as int + def Div(x:Tensor,y:Tensor): return x.div(y, rounding_mode='trunc' if dtypes.is_int(x.dtype) else None) + def Less(x:Tensor,y:Tensor): return x < y + def LessOrEqual(x:Tensor,y:Tensor): return x <= y + def Greater(x:Tensor,y:Tensor): return x > y + def GreaterOrEqual(x:Tensor,y:Tensor): return x >= y + def Equal(x:Tensor,y:Tensor): return x == y + def And(x:Tensor,y:Tensor): return (x==y).where(x, False) + def Or(x:Tensor,y:Tensor): return (x==y).where(x, True) + def Xor(x:Tensor,y:Tensor): return x.bool().bitwise_xor(y.bool()) + def BitwiseAnd(x:Tensor,y:Tensor): return x & y + def BitwiseOr(x:Tensor,y:Tensor): return x | y + def BitwiseXor(x:Tensor,y:Tensor): return x ^ y + def BitwiseNot(x:Tensor): return ~x + def Mod(x:Tensor,y:Tensor,fmod=0): + if fmod: return x - x.div(y, rounding_mode="trunc") * y + return x % y + + # ***** Casting Ops ***** + # TODO: saturate + def Cast(x:Tensor, to:int, saturate:int=1): return x.cast(dtype_parse(to, "Cast op")) + def CastLike(x:Tensor, target_type:Tensor, saturate:int=1): return x.cast(target_type.dtype) + + # ***** Reduce Ops ***** + def Max(*data_0:Tensor): return functools.reduce(Tensor.maximum, data_0) + def Min(*data_0:Tensor): return functools.reduce(Tensor.minimum, data_0) + def Sum(*data_0:Tensor): return functools.reduce(Tensor.add, data_0) + def Mean(*data_0:Tensor): return Sum(*data_0) / len(data_0) + def ReduceMax(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): + return data.max(_axes(axes, noop_with_empty_axes), keepdim=keepdims) + def ReduceMin(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): + return data.min(_axes(axes, noop_with_empty_axes), keepdim=keepdims) + def ReduceSum(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): + return data.sum(_axes(axes, noop_with_empty_axes), keepdim=keepdims) + def ReduceMean(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): + return data.mean(_axes(axes, noop_with_empty_axes), keepdim=keepdims) + def ReduceSumSquare(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): + return ReduceSum(data.square(), axes, keepdims, noop_with_empty_axes) + def ReduceProd(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): + return data.prod(_axes(axes, noop_with_empty_axes), keepdim=keepdims) + def ReduceL1(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): + return ReduceSum(data.abs(), axes, keepdims, noop_with_empty_axes) + def ReduceL2(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): + return ReduceSumSquare(data, axes, keepdims, noop_with_empty_axes).sqrt() + def ReduceLogSum(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): + return ReduceSum(data, axes, keepdims, noop_with_empty_axes).log() + def ReduceLogSumExp(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): + return ReduceSum(data.exp(), axes, keepdims, noop_with_empty_axes).log() + def ArgMax(x:Tensor, axis:int=0, keepdims:int=1, select_last_index:int=0): + if select_last_index: return ((x.shape[axis]-1) - x.flip(axis).argmax(axis, keepdim=keepdims)).cast(dtypes.int64) + return x.argmax(axis, keepdim=keepdims).cast(dtypes.int64) + def ArgMin(x, axis:int=0, keepdims:int=1, select_last_index:int=0): + return ArgMax(-x, axis=axis, keepdims=keepdims, select_last_index=select_last_index) + + # ***** Movement Ops ***** + def Reshape(data:Tensor, shape:list[int], allowzero:int=0): + return data.reshape([x if x != 0 else (0 if allowzero else data.shape[i]) for i,x in enumerate(shape)]) + def Flatten(x:Tensor, axis:int=1): return x.reshape(prod(x.shape[0:axis]), -1) + def Expand(x:Tensor, shape:list[int]): return x.expand(_broadcast_shape(x.shape, tuple(shape))) + def Shrink(x:Tensor, bias:float=0.0, lambd:float=0.5): return (x < -lambd)*(x+bias) + (x > lambd)*(x-bias) + def Transpose(x:Tensor, perm:list[int]|None=None): return x.permute(order=perm or list(range(x.ndim)[::-1])) + + def Squeeze(data:Tensor, axes:list[int]|None=None): + return data.squeeze() if axes is None else functools.reduce(lambda d, dim: d.squeeze(dim), sorted(axes, reverse=True), data) + def Unsqueeze(data:Tensor, axes:list[int]): return functools.reduce(lambda d, dim: d.unsqueeze(dim), sorted(axes), data) + + def Tile(x:Tensor, repeats:list[int]): return x.repeat(repeats) + def Concat(*xs:Tensor, axis:int): return Tensor.cat(*xs, dim=axis) + def Slice(data:Tensor, starts:list[int], ends:list[int], axes:list[int]|None=None, steps:list[int]|None=None): + axes = axes or list(range(data.ndim)) + steps = steps or [1]*data.ndim + slices = [slice(0,x,1) for x in data.shape] + for i, axis in enumerate(axes): slices[axis] = slice(starts[i], ends[i], steps[i]) + return data[tuple(slices)] + + def Split(data:Tensor, split:list[int]|None=None, num_outputs:int=0, axis:int=0): + sz = data.shape[axis] + if split is None: split = [sz // num_outputs + (1 if i < sz % num_outputs else 0) for i in range(num_outputs)] + return data.split(split, axis) + + def Pad(x:Tensor, pads:list[int], constant_value:ConstType|None=None, axes:list[int]|None=None, + mode:Literal["constant", "reflect", "edge", "wrap"]="constant", value=0): + value = constant_value or value + axes = axes or list(range(x.ndim)) + real_pads = [0] * (x.ndim*2) + for i,axis in enumerate(axes): real_pads[axis%x.ndim], real_pads[axis%x.ndim+x.ndim] = pads[i], pads[i+len(axes)] + return x.pad(padding=_onnx_pads_to_tiny_pads(real_pads), mode={"edge":"replicate", "wrap":"circular"}.get(mode, mode), value=value) + + def CenterCropPad(t:Tensor, shape:list[int], axes:list[int]|None=None): + shrink_arg:list[None|tuple[int,int]] = [None] * t.ndim + pad_arg:list[None|tuple[int,int]] = [None] * t.ndim + for s, x in zip(shape, axes or range(t.ndim)): + tx = t.shape[x] + if s < tx: shrink_arg[x] = (tx//2 - (s+1)//2, tx//2 + s//2) + elif s > tx: pad_arg[x] = ((s-tx)//2, (s-tx+1)//2) + return t.shrink(tuple(shrink_arg)).pad(tuple(pad_arg)) + + # ***** Processing Ops ***** + def AveragePool(X: Tensor, kernel_shape:list[int], auto_pad:AUTO_PAD_OPTIONS="NOTSET", ceil_mode:int=0, count_include_pad:int=0, + dilations:list[int]|int=1, pads:list[int]|int=0, strides:list[int]|int=1): + return X.avg_pool2d(kernel_shape, strides, dilations, _resolve_pool_pads(X, pads, kernel_shape, dilations, strides, auto_pad), + ceil_mode=ceil_mode, count_include_pad=count_include_pad) + + def MaxPool(X: Tensor, kernel_shape:list[int], auto_pad:AUTO_PAD_OPTIONS="NOTSET", ceil_mode:int=0, dilations:list[int]|int=1, pads:list[int]|int=0, + storage_order:int=0, strides:list[int]|int=1): + pads = _resolve_pool_pads(X, pads, kernel_shape, dilations, strides, auto_pad) + ret, idx = X.max_pool2d(kernel_shape, strides, dilations, pads, ceil_mode=ceil_mode, return_indices=True) + return ret, idx.transpose(-2, -1).cast(dtypes.int64) if storage_order else idx.cast(dtypes.int64) + + def Conv(X: Tensor, W: Tensor, B:Tensor|None=None, auto_pad:AUTO_PAD_OPTIONS="NOTSET", dilations:list[int]|int=1, group:int=1, + kernel_shape:list[int]|None=None, pads:list[int]|int=0, strides:list[int]|int=1): + return X.conv2d(W, B, stride=strides, groups=group, dilation=dilations, + padding=_resolve_pool_pads(X, pads, kernel_shape or W.shape[2:], dilations, strides, auto_pad)) + + def ConvTranspose(X: Tensor, W: Tensor, B:Tensor|None=None, auto_pad:AUTO_PAD_OPTIONS="NOTSET", dilations:list[int]|int=1, group:int=1, + kernel_shape:list[int]|None=None, pads:list[int]|None=None, output_shape:list[int]|None=None, output_padding:list[int]|int=0, + strides:list[int]|int=1): + input_shape, kernel_shape = X.shape[2:], (kernel_shape or W.shape[2:]) + strides, dilations, output_padding = (make_tuple(x, len(input_shape)) for x in (strides, dilations, output_padding)) + if output_shape is not None: # we pad according to output_shape + pads = _auto_pad([s*(i-1) + op + ((k-1)*d+1) - os for s,i,op,k,d,os in + zip(strides, input_shape, output_padding, kernel_shape, dilations, output_shape)], auto_pad) + if pads is None: # we generate pads + output_shape = output_shape or [X.shape[i+2] * strides[i] for i in range(len(strides))] + pads = [strides[i]*(input_shape[i]-1) + output_padding[i] + ((kernel_shape[i]-1)*dilations[i]+1)-output_shape[i] for i in range(len(input_shape))] + pads = _auto_pad(pads, auto_pad) if auto_pad != "NOTSET" else [0] * len(input_shape) * 2 + pads = _onnx_pads_to_tiny_pads(pads) + return X.conv_transpose2d(W, B, stride=strides, groups=group, dilation=dilations, padding=pads, output_padding=output_padding) + + def MaxUnpool(xT: Tensor, xI: Tensor, outshape: list[int]|None=None, kernel_shape:list[int]=None, pads:list[int]|int=0, strides:list[int]|int=1): + return Tensor.max_unpool2d(xT, xI, kernel_shape, strides, 1, pads, outshape if outshape is None else tuple(outshape)) + + def GlobalAveragePool(X:Tensor): return X.mean(axis=tuple(range(2, X.ndim)), keepdim=True) + def GlobalMaxPool(X:Tensor): return X.max(axis=tuple(range(2, X.ndim)), keepdim=True) + + def Gemm(A:Tensor, B:Tensor, C:Tensor|None=None, alpha:float=1.0, beta:float=1.0, transA:int=0, transB:int=0, broadcast=0): + ret = alpha * (A.transpose(transA) @ B.transpose(transB)) + if C is not None: ret = ret + beta * (C if broadcast == 0 else C.reshape([-1 if i < len(C.shape) else 1 for i in range(ret.ndim)][::-1])) + return ret + + def Einsum(*Inputs:list[Tensor], equation:str): return Tensor.einsum(equation, *Inputs) + + def CumSum(X:Tensor, axis:int|list, exclusive:int=0, reverse:int=0): + axis = X._resolve_dim(axis[0] if isinstance(axis, list) else axis) + if reverse: X = X.flip(axis) + if exclusive: X = X.pad(tuple((1,0) if i == axis else None for i in range(X.ndim)))\ + .shrink(tuple((0,X.shape[axis]) if i == axis else None for i in range(X.ndim))) + return X.cumsum(axis).flip(axis) if reverse else X.cumsum(axis) + + def Trilu(x:Tensor, k:int=0, upper:int=1): return x.triu(k) if upper else x.tril(k) + + def Resize(X:Tensor, roi:list[float]|None=None, scales:list[float]|None=None, sizes:list[int]|None=None, antialias:int=0, + axes:list[int]|None=None, coordinate_transformation_mode:str='half_pixel', cubic_coeff_a:float=-0.75, exclude_outside:int=0, + extrapolation_value:float=0.0, keep_aspect_ratio_policy:str='stretch', mode:str='nearest', nearest_mode:str='round_prefer_floor'): + def _apply_nearest_mode(index: Tensor, input_dim, mode: str): + if mode == "round_prefer_floor": index = (index - 0.5).ceil() + elif mode == "round_prefer_ceil": index = (index + 0.5).floor() + elif mode in ["floor", "ceil"]: index = getattr(index, mode)() + else: raise ValueError(f"invalid {nearest_mode=}") + return index.cast(dtypes.int32).clip(0, input_dim-1) + def _apply_transformation(index: Tensor, input_dim, scale_dim, mode): + # TODO: needs more testing, not confident in this + # NOTE: their reference implementation differ from the implementation in their reference docs + # https://github.com/onnx/onnx/blob/main/onnx/reference/ops/op_resize.py + # https://github.com/onnx/onnx/blob/main/docs/Operators.md#Resize + output_dim = scale_dim * input_dim + if mode == "half_pixel": index = (index + 0.5) / scale_dim - 0.5 + elif mode == "align_corners": index = index * (input_dim - 1) / (output_dim - 1) if output_dim != 1 else Tensor([0]) + elif mode == "asymmetric": index = index / scale_dim + elif mode == "pytorch_half_pixel": index = (index + 0.5) / scale_dim - 0.5 if output_dim != 1 else Tensor([-0.5]) + elif mode == "half_pixel_symmetric": index = input_dim / 2 * (1 - int(output_dim) / output_dim) + (index + 0.5) / scale_dim - 0.5 + else: raise NotImplementedError(f"invalid {coordinate_transformation_mode=}") + return index.clip(0, input_dim-1) + + scales, sizes = (None if scales is None else scales[2-(X.ndim-len(scales)):]), (None if sizes is None else sizes[2-(X.ndim-len(sizes)):]) + # we pre permute the axes and permute back after resize + axes, input_shape, = (axes or list(range(X.ndim))), cast(tuple[int, ...], X.shape[2:]), + perm = [a for a in range(len(X.shape)) if a not in axes] + list(axes) + X = X.permute(*perm) + + if sizes is not None: + if keep_aspect_ratio_policy in ["not_larger", "not_smaller"]: + scale_fxn = min if keep_aspect_ratio_policy == "not_larger" else max + scales = [scale_fxn([sizes[i] / input_shape[i] for i in range(len(input_shape)) if i+2 in axes])] * 2 + sizes = [int((scales[0] * input_shape[i]) + 0.5) if i+2 in axes else input_shape[i] for i in range(X.ndim-2)] + else: + scales = [size / input_shape for size, input_shape in zip(sizes, input_shape)] + else: + sizes = [int(sc*sh) for sc, sh in zip(scales, input_shape)] + + # NOTE: this transformation makes it so that we can't just call Tensor.interpolate + # in Tensor.interpolate, we use indexes without any transformation + indexes = [] + for shape, size, scale in zip(input_shape, sizes, scales): + indexes.append(_apply_transformation(Tensor.arange(size), shape, scale, coordinate_transformation_mode)) + + if mode == "nearest": + indexes = [_apply_nearest_mode(index, shape, nearest_mode) for (index, shape) in zip(indexes, input_shape)] + X = X[(..., *Tensor.meshgrid(*indexes))] + if mode == "linear": + expand = list(X.shape) + for i in range(-len(sizes), 0): + reshape, index = [1] * X.ndim, indexes[i] + reshape[i] = expand[i] = sizes[i] + low, high, perc = [y.reshape(reshape).expand(expand) for y in (index.floor().int(), index.ceil().int(), index - index.floor())] + X = X.gather(i, low).lerp(X.gather(i, high), perc) + if mode == "cubic": raise NotImplementedError("cubic interpolation is not implemented") + return X.permute(*argsort(perm)) if perm else X + def Upsample(X, scales, mode): return Resize(X=X, scales=scales, mode=mode) # deprecated + + def TopK(X:Tensor, K:int|list[int], axis:int=-1, largest:int=1, sorted:int=1): + val, idx = X.topk(K if isinstance(K, int) else K[0], axis, largest, sorted) + return val, idx.cast(dtypes.int64) + + # ***** Neural Network Ops ***** + def BatchNormalization(X:Tensor, scale:Tensor, B:Tensor, input_mean:Tensor, input_var:Tensor, epsilon:float=1e-05, momentum:float=0.9, + training_mode:int=0, spatial=1, is_test=0): + if training_mode: + x_detached = X.detach() + current_mean = x_detached.mean(axis=(0,2,3)) + y = (x_detached - current_mean.reshape(shape=[1, -1, 1, 1])) + current_var = (y*y).mean(axis=(0,2,3)) + current_invstd = current_var.add(epsilon).rsqrt() + + running_mean = input_mean * momentum + current_mean * (1 - momentum) + running_var = input_var * momentum + current_var * (1 - momentum) + + return X.batchnorm(scale, B, current_mean, current_invstd), running_mean, running_var + return X.batchnorm(scale, B, input_mean, (input_var + epsilon).rsqrt()) + def GroupNormalization(x:Tensor, scale:Tensor, bias:Tensor, num_groups:int, epsilon:float=1e-05): + x = x.reshape(x.shape[0], num_groups, -1).layernorm(eps=epsilon).reshape(x.shape) + return x * scale.reshape(1, -1, *[1] * (x.ndim-2)) + bias.reshape(1, -1, *[1] * (x.ndim-2)) + def InstanceNormalization(x:Tensor, scale:Tensor, bias:Tensor, epsilon:float=1e-05): + return GroupNormalization(x, scale, bias, num_groups=x.shape[1], epsilon=epsilon) + def LayerNormalization(x:Tensor, scale:Tensor, bias:Tensor, axis:int=-1, epsilon:float=1e-05, stash_type:int=1): + assert stash_type == 1, "only float32 is supported" + axes = tuple(i for i in range(axis if axis >= 0 else x.ndim + axis, x.ndim)) + mean = x.mean(axis=axes, keepdim=True) + return x.layernorm(axes, epsilon).mul(scale).add(bias), mean, (x.sub(mean)).square().mean(axis=axes, keepdim=True).add(epsilon).rsqrt() + def SkipLayerNormalization(x:Tensor, skip:Tensor, gamma:Tensor, beta:Tensor|None=None, bias:Tensor|None=None, epsilon:float=1e-12): + x = x + skip + if bias is not None: x = x + bias + ret = x.layernorm(eps=epsilon) * gamma + if beta is not None: ret = ret + beta + return ret, None, None, x + def EmbedLayerNormalization(input_ids: Tensor, segment_ids:Tensor, word_embedding:Tensor, position_embedding:Tensor, + segment_embedding:Tensor, gamma=None, beta=None, mask:Tensor|None=None, + position_ids:Tensor|None=None, epsilon=1e-12, mask_index_type=0): + # https://github.com/microsoft/onnxruntime/blob/main/docs/ContribOperators.md#com.microsoft.EmbedLayerNormalization + assert (segment_ids is None) is (segment_embedding is None) + assert mask is None and not mask_index_type, "functionality not supported yet" # TODO + input_shape = input_ids.shape + seq_length = input_shape[1] + compute_seg_emb = (segment_embedding is not None and segment_ids is not None) + vocab_size, max_position_embeddings = word_embedding.shape[0], position_embedding.shape[0] + type_vocab_size = (segment_embedding.shape[0] if compute_seg_emb else None) + + def embedding(x:Tensor, vocab_size, weight:Tensor) -> Tensor: + return x.unsqueeze(-1).expand(*x.shape, vocab_size)._one_hot_along_dim(vocab_size) @ weight + + # bert embedding layer + if position_ids is None: position_ids = Tensor.arange(seq_length, requires_grad=False).unsqueeze(0).expand(*input_shape) + wrd_embedding_res = embedding(input_ids, vocab_size, word_embedding) + pos_embedding_res = embedding(position_ids, max_position_embeddings, position_embedding) + seg_embedding_res = embedding(segment_ids, type_vocab_size, segment_embedding) if compute_seg_emb else None + + embedding_sum = wrd_embedding_res + pos_embedding_res + if seg_embedding_res is not None: embedding_sum = embedding_sum + seg_embedding_res + out = embedding_sum.layernorm(eps=epsilon) * gamma + beta + return out, None, embedding_sum + def MeanVarianceNormalization(x:Tensor, axis:list[int]=[0,2,3]): + return (x - x.mean(axis, keepdim=True)) / (x.std(axis, keepdim=True, correction=0) + 1e-9) + + def OneHot(indices:Tensor, depth:float|int|list, values:Tensor, axis:int=-1): + # Scalar or Rank 1 tensor containing exactly one element + depth = int(depth[0] if isinstance(depth, list) else depth) + indices = indices.int() + indices = (indices < 0).where(indices+depth, indices) + return indices.unsqueeze(axis)._one_hot_along_dim(depth, dim=axis).where(values[1], values[0]) + + def DepthToSpace(X:Tensor, blocksize:int, mode:str="DCR"): + return X.rearrange("b (c h1 w1) h w -> b c (h h1) (w w1)" if mode=="CRD" else "b (h1 w1 c) h w -> b c (h h1) (w w1)", h1=blocksize, w1=blocksize) + def SpaceToDepth(X:Tensor, blocksize:int): + return X.rearrange("b c (h h1) (w w1) -> b (h1 w1 c) h w", h1=blocksize, w1=blocksize) + + # Reimplemented here because you need legacy RNG for passing ONNX tests. + def Dropout_7(data:Tensor, ratio:float=0.5, training_mode:bool=False, seed:int|None=None): + if not training_mode: return data, data.full_like(True, dtype=dtypes.bool) + if seed is not None: + rand = Tensor(np.random.RandomState(seed).random(cast(tuple[int,...], data.shape)), requires_grad=False, dtype=data.dtype, device=data.device) + else: + rand = data.rand_like(requires_grad=False) + mask = rand >= ratio + return data * mask / (1.0 - ratio), mask + # 6 with 'is_test' needed for https://github.com/MTlab/onnx2caffe/raw/refs/heads/master/model/MobileNetV2.onnx + def Dropout_6(data:Tensor, ratio:float=0.5, is_test=0): return Dropout_7(data, ratio, training_mode=not is_test) + Dropout = {6:Dropout_6, 7:Dropout_7} + + def LRN(x:Tensor, size:int, alpha:float=1e-4, beta:float=0.75, bias:float=1.0): + pooled_x = (x**2).rearrange('b c h w -> b 1 c (h w)').pad((0,0,(size-1)//2, size//2)).avg_pool2d((size, 1), 1) + return x / (pooled_x.reshape(x.shape) * alpha + bias).pow(beta) + + def NegativeLogLikelihoodLoss(x:Tensor, target:Tensor, weight:Tensor|None=None, ignore_index:int|None=None, reduction:ReductionStr="mean"): + return x.nll_loss(target, weight, ignore_index, reduction) + def SoftmaxCrossEntropyLoss(scores:Tensor, labels:Tensor, weights:Tensor|None=None, ignore_index:int|None=None, reduction:ReductionStr="mean"): + log_probs = scores.log_softmax(1) + return log_probs.nll_loss(labels, weights, ignore_index, reduction), log_probs + + def AffineGrid(theta:Tensor, size:list[int], align_corners:int=0): + N, _, *spatial_dims = size + def generate_grid(steps): + return Tensor.linspace(-1, 1, steps, device=theta.device) if align_corners else Tensor.linspace(-1+1/steps, 1-1/steps, steps, device=theta.device) + grids = Tensor.meshgrid(*(generate_grid(d) for d in spatial_dims)) + base_grid = Tensor.stack(*reversed(grids), Tensor.ones_like(grids[0], device=theta.device), dim=-1) + base_grid = base_grid.reshape(1, prod(spatial_dims), len(grids)+1).expand(N, -1, -1) + return (base_grid @ theta.transpose(1, 2)).reshape(N, *spatial_dims, -1) + + def Attention(x:Tensor, weights:Tensor, bias:Tensor|None=None, mask_index:Tensor|None=None, past:Tensor|None=None, attention_bias:Tensor|None=None, + past_sequence_length:Tensor|None=None, do_rotary:int=0, mask_filter_value:float=-10000.0, num_heads:int|None=None, + past_present_share_buffer:int|None=None, qkv_hidden_sizes:list[int]|None=None, rotary_embedding_dim:int|None=None, + scale:float|None=None, unidirectional:int=0): + assert not do_rotary and not attention_bias, "TODO" + if qkv_hidden_sizes is None: qkv_hidden_sizes = [weights.shape[1] // 3] * 3 + qkv = x.linear(weights, bias) + q, k, v = qkv.split(qkv_hidden_sizes, dim=2) + + batch_size, seq_len, _ = x.shape + q_head_size, k_head_size, v_head_size = (sz // num_heads for sz in qkv_hidden_sizes) + q, k, v = (x.reshape(batch_size, seq_len, num_heads, hsz).transpose(1, 2) for x, hsz in zip((q, k, v), (q_head_size, k_head_size, v_head_size))) + + present = None + if past is not None: + k, v = past[0].cat(k, dim=2), past[1].cat(v, dim=2) + present = k.stack(v) + + if scale is None: scale = 1.0 / math.sqrt(q_head_size) + attn_scores = q @ k.transpose(-1, -2) * scale + + if mask_index is not None: + assert 4 >= mask_index.ndim >= 1, f"{mask_index.ndim=}" + if mask_index.ndim != 1: mask = mask_index.bool() + else: + if mask_index.shape[0] == batch_size: + mask = Tensor.arange(attn_scores.shape[-1], requires_grad=False, device=mask_index.device).unsqueeze(0) < mask_index.unsqueeze(1) + elif mask_index.shape[0] == 2*batch_size: + end_positions = mask_index[:batch_size] + start_positions = mask_index[batch_size:] + arange = Tensor.arange(seq_len).unsqueeze(0) + mask = (arange < end_positions.unsqueeze(1)) & (arange >= start_positions.unsqueeze(1)) + else: raise NotImplementedError("mask_index with shape (3 * batch_size + 2) is not implemented") + while mask.ndim < 4: mask = mask.unsqueeze(1) + attn_scores = mask.where(attn_scores, mask_filter_value) + + if unidirectional: + causal_mask = Tensor.ones((seq_len, seq_len), dtype=dtypes.bool).tril() + attn_scores = causal_mask.where(attn_scores, mask_filter_value) + + output = attn_scores.softmax(-1) @ v + output = output.transpose(1, 2).reshape(batch_size, seq_len, -1) + return output, present + + # ***** Indexing Ops ***** + def ArrayFeatureExtractor(x:Tensor, indices:Tensor): return x[..., indices] + + def Gather(x:Tensor, indices:Tensor, axis:int=0): + if indices.numel() < 9: # NOTE lessor kernels for smaller indices but kernel number increases depending on size of indices + x_sh = list(x.shape) + ret_shape = x_sh[:axis] + list(indices.shape) + x_sh[axis+1:] + if indices.ndim > 1: indices = indices.flatten() + indices = [_cached_to_python_const(indices)] if indices.shape == () else _cached_to_python_const(indices) + indices = [x_sh[axis]+x if x<0 else x for x in indices] + args = [[(0,x) if j != axis else (i,i+1) for j, x in enumerate(x_sh)] for i in indices] # type: ignore + return x.shrink(arg=tuple(args[0])).cat(*[x.shrink(arg=tuple(arg)) for arg in args[1:]], dim=axis).reshape(ret_shape) + # NOTE faster gather, fixed number of kernels, but exceeds limited kernels for openpilot + return x[tuple([slice(None) if i != axis else indices for i in range(x.ndim)])] + def Scatter(*args, **kwargs): return ScatterElements(*args, **kwargs) # deprecated + + def GatherND(x:Tensor, indices:Tensor, batch_dims:int=0): + if batch_dims == 0: return x[tuple(i.squeeze(-1) for i in indices.split(1, -1))] + x_shape, i_shape = x.shape, indices.shape + b = math.prod(x.shape[dim] for dim in range(batch_dims)) + # NOTE: each batched dim of both input and indices are equal + x = x.reshape(b, *x.shape[batch_dims:]) + indices = indices.reshape(b, *indices.shape[batch_dims:]) + b_idx = Tensor.arange(b, device=x.device).reshape(b, *(1,)*(indices.ndim - 2)).expand(*indices.shape[:-1]) + ret = x[(b_idx,) + tuple(i.squeeze(-1) for i in indices.split(1, -1))] + return ret.reshape(*x_shape[:batch_dims], *i_shape[batch_dims:-1], *ret.shape[indices.ndim-1:]) + def ScatterND(x:Tensor, indices:Tensor, updates:Tensor, reduction:Literal["none", "add", "mul"]='none'): + assert updates.shape == indices.shape[:-1] + x.shape[cast(int, indices.shape[-1]):] + x = x.contiguous() + for index, u in zip(indices.split(1, 0), updates.split(1, 0)): + i = tuple(idx.squeeze(-1) for idx in index.squeeze(0).split(1, -1)) + u = u.squeeze(0) + if reduction == "none": x[i] = u + elif reduction == "add": x[i] += u + elif reduction == "mul": x[i] *= u + else: raise NotImplementedError("reduction doesn't support max or min") + return x + + def ScatterElements(x: Tensor, indices: Tensor, updates: Tensor, axis=0, reduction:Literal["none", "add", "mul", "min", "max"]="none"): + indices = (indices < 0).where(x.shape[axis], 0) + indices + if reduction == "none": return x.scatter(axis, indices, updates) + return x.scatter_reduce(axis, indices, updates, {"add": "sum", "mul": "prod", "min": "amin", "max": "amax"}.get(reduction)) + def GatherElements(x:Tensor, indices:Tensor, axis:int): + indices = (indices < 0).where(x.shape[axis], 0) + indices + return x.gather(axis, indices) + + def Compress(inp:Tensor, condition:list[bool], axis:int|None=None): + if axis is None: + inp = inp.flatten() + axis = 0 + if axis < 0: axis += inp.ndim + con = Tensor([i for i,cond in enumerate(condition) if cond]) # compress in python + return inp[tuple(con if i == axis else slice(None) for i in range(inp.ndim))] + + # ***** Quantization Ops ***** + def QuantizeLinear(x:Tensor, y_scale:Tensor, y_zero_point:Tensor|int=0, axis:int=1, block_size:int=0, output_dtype:int=0, saturate=1): + if isinstance(y_zero_point, Tensor): out_dtype = y_zero_point.dtype + elif output_dtype != 0: out_dtype = dtype_parse(output_dtype, "QuantizeLinear op") + else: out_dtype = dtypes.uint8 + y_scale, y_zero_point = _prepare_quantize(x, y_scale, y_zero_point, axis, block_size) + if out_dtype == dtypes.uchar: + # this appears to work in practice, at least for uchar out_dtype. it folds with the quantize stuff + ret = _clamp_cast((x / y_scale + 0.4999999 + y_zero_point).int(), out_dtype) + else: + ret = _clamp_cast(((x / y_scale).round() + y_zero_point), out_dtype) + return ret.contiguous() + + def DynamicQuantizeLinear(x: Tensor): + # only support uint8 + qmin, qmax = dtypes.min(dtypes.uint8), dtypes.max(dtypes.uint8) + scale = (x.max().maximum(0) + ((-x).max()).maximum(0)) / (qmax - qmin) + zero_point = _clamp_cast((qmin - x.min() / scale).round(), dtypes.uint8) + y = _clamp_cast((x / scale).round() + zero_point, dtypes.uint8) + return y, scale, zero_point + + def DequantizeLinear(x:Tensor, x_scale:Tensor, x_zero_point:Tensor|int=0, axis:int=1, block_size:int=0): + x_scale, x_zero_point = _prepare_quantize(x, x_scale, x_zero_point, axis, block_size) + return ((x.int() - x_zero_point) * x_scale).cast(x_scale.dtype) + + def QLinearConv(x:Tensor, x_scale:Tensor, x_zero_point:Tensor|int, w:Tensor, w_scale:Tensor, w_zero_point:Tensor|int, y_scale:Tensor, + y_zero_point: Tensor|int, B:Tensor|None=None, **opts): + return _qlinearop_quantized(Conv, [x,w], [x_zero_point,w_zero_point], [x_scale,w_scale], y_scale, y_zero_point, **{"B":B, **opts}) + + def QLinearMatMul(a:Tensor, a_scale:Tensor, a_zero_point:Tensor|int, b:Tensor, b_scale:Tensor, b_zero_point:Tensor|int, y_scale:Tensor, + y_zero_point:Tensor|int) -> Tensor: + return _qlinearop_quantized(Tensor.matmul, [a,b], [a_zero_point,b_zero_point], [a_scale,b_scale], y_scale, y_zero_point) + + def QLinearAdd(a:Tensor, a_scale:Tensor, a_zero_point:Tensor, b:Tensor, b_scale:Tensor, b_zero_point:Tensor, c_scale:Tensor, c_zero_point:Tensor): + return _qlinearop_float(Tensor.add, [a,b], [a_zero_point,b_zero_point], [a_scale,b_scale], c_scale, c_zero_point) + + def QLinearMul(a:Tensor, a_scale:Tensor, a_zero_point:Tensor, b:Tensor, b_scale:Tensor, b_zero_point:Tensor, c_scale:Tensor, c_zero_point:Tensor): + return _qlinearop_quantized(Tensor.mul, [a,b], [a_zero_point,b_zero_point], [a_scale,b_scale], c_scale, c_zero_point) + + def QLinearGlobalAveragePool(X:Tensor, x_scale:Tensor, x_zero_point:Tensor, y_scale:Tensor, y_zero_point:Tensor, channels_last:int): + assert channels_last == 0, "TODO NHWC" + return _qlinearop_float(GlobalAveragePool, [X], [x_zero_point], [x_scale], y_scale, y_zero_point) + + def ConvInteger(x: Tensor, w: Tensor, x_zero_point: Tensor | int = 0, w_zero_point: Tensor | int = 0, B: Tensor | None = None, **opts) -> Tensor: + return _op_integer(Conv, [x,w], [x_zero_point,w_zero_point], **{"B":B, **opts}) + + def MatMulInteger(A: Tensor, B: Tensor, a_zero_point: Tensor | int = 0, b_zero_point: Tensor | int = 0) -> Tensor: + return _op_integer(Tensor.matmul, [A,B], [a_zero_point,b_zero_point]) + + # ***** Training Ops ***** + # NOTE: onnx training ops actually don't need the state for optim, all the ops work in a functional way, but we still can reuse optim.py code + @_onnx_training(3) + def Adagrad(R:Tensor, T:int, *inputs:Tensor, decay_factor:float=0.0, epsilon:float=0.0, norm_coefficient:float=0.0): + X, G, H = (i.detach() for i in inputs) + grad = norm_coefficient * X + G + H.assign(H + grad.square()) + up = grad / (H.sqrt() + epsilon) + r = R / (1 + T * decay_factor) + X.assign(X.detach() - r * up) + return [X, H] + + @_onnx_training(4) + def Adam(R:Tensor, T:int, *inputs:Tensor, alpha:float=0.9, beta:float=0.999, epsilon:float=0.0, norm_coefficient:float=0.0, + norm_coefficient_post:float=0.0): + from tinygrad.nn.optim import Adam as TinyAdam + X, G, V, H = inputs + G, V, H = G.detach(), V.detach(), H.detach() + X.grad = norm_coefficient * X.detach() + G + opt = TinyAdam([X], b1=alpha, b2=beta, eps=epsilon) + opt.m, opt.v, opt.lr = [V], [H], R + # need no-op for m_hat and v_hat if T == 0 + if T == 0: opt.b1_t, opt.b2_t = opt.b1_t.zeros_like(), opt.b2_t.zeros_like() + else: + # `T-1` since it's applied again at the start of `_step` + opt.b1_t = Tensor([alpha**(T-1)], dtype=dtypes.float32, device=X.device, requires_grad=False) + opt.b2_t = Tensor([beta**(T-1)], dtype=dtypes.float32, device=X.device, requires_grad=False) + opt.step() + X = (1 - norm_coefficient_post) * X + return [X, V, H] + + @_onnx_training(3) + def Momentum(R:Tensor, T:int, *inputs:Tensor, alpha:float, beta:float, mode:str, norm_coefficient:float): + X, G, V = (i.detach() for i in inputs) + grad = norm_coefficient * X + G + # NOTE: this beta_adjusted term makes it so we can't use SGD for nesterov + beta_adjusted = beta if T > 0 else 1 + V.assign(alpha * V + grad * beta_adjusted) + X.assign(X - R * (V if mode == "standard" else (grad + alpha * V))) + return [X, V] + + def Gradient(*inputs:Tensor, y:str, intermediate_tensors:dict[str, Tensor], **_): + intermediate_tensors[y].backward() + return tuple([t.grad for t in inputs]) + + return { + # Tensor ops + **{op: getattr(Tensor, op.lower()) for op in ("Neg", "Reciprocal", "Pow", "Sqrt", "Sign", "Abs", "Exp", "Log", "Mish", "Sin", "Cos", "Tan", + "Asin", "Acos", "Atan", "Relu", "Sigmoid", "MatMul", "Floor", "Ceil", "IsNaN", "Softplus", "HardSwish", "Where", "Mul", "Sinh", "Cosh", + "Tanh", "Softsign", "Asinh", "Acosh", "Atanh", "Elu", "Celu", "Selu", "Round", "Erf")}, + # Implemented ops + **{name:obj for name,obj in locals().items() if isinstance(obj, types.FunctionType) and not name.startswith("_") and name[0].isupper()}, + # Version ops + **{name:obj for name,obj in locals().items() if isinstance(obj, dict)}, + } + +onnx_ops = get_onnx_ops() diff --git a/tinygrad_repo/extra/onnx_helpers.py b/tinygrad_repo/extra/onnx_helpers.py index 632d5df8d..d2a8bb961 100644 --- a/tinygrad_repo/extra/onnx_helpers.py +++ b/tinygrad_repo/extra/onnx_helpers.py @@ -1,6 +1,7 @@ from tinygrad import Tensor from tinygrad.tensor import _to_np_dtype -from tinygrad.frontend.onnx import OnnxRunner, OnnxValue +from tinygrad.frontend.onnx import OnnxRunner, onnx_load +from extra.onnx import OnnxValue import numpy as np import onnxruntime as ort @@ -45,7 +46,7 @@ def get_example_inputs(graph_inputs:dict[str, OnnxValue], config={}): return ret def validate(onnx_file, inputs, rtol=1e-5, atol=1e-5): - run_onnx = OnnxRunner(onnx_file) + run_onnx = OnnxRunner(onnx_load(onnx_file)) ort_options = ort.SessionOptions() ort_options.log_severity_level = 3 diff --git a/tinygrad_repo/extra/onnx_parser.py b/tinygrad_repo/extra/onnx_parser.py new file mode 100644 index 000000000..dd8b8946d --- /dev/null +++ b/tinygrad_repo/extra/onnx_parser.py @@ -0,0 +1,205 @@ +# https://github.com/onnx/onnx/blob/main/onnx/onnx.proto3 + +import os, pathlib, struct +from io import BufferedReader +from typing import Tuple, Union +from types import SimpleNamespace +from tinygrad.nn.state import TensorIO +from tinygrad.tensor import Tensor, dtypes + +# Protobuf Wire Types +WIRETYPE_VARINT = 0; WIRETYPE_FIXED64 = 1; WIRETYPE_LENGTH_DELIMITED = 2; WIRETYPE_START_GROUP = 3; WIRETYPE_END_GROUP = 4; WIRETYPE_FIXED32 = 5 # noqa: E702 + +# TensorProto.DataType +class TensorDataType: + UNDEFINED = 0; FLOAT = 1; UINT8 = 2; INT8 = 3; UINT16 = 4; INT16 = 5; INT32 = 6; INT64 = 7 # noqa: E702 + STRING = 8; BOOL = 9; FLOAT16 = 10; DOUBLE = 11; UINT32 = 12; UINT64 = 13; COMPLEX64 = 14; COMPLEX128 = 15; BFLOAT16 = 16 # noqa: E702 + +# AttributeProto.AttributeType +class AttributeType: + UNDEFINED = 0; FLOAT = 1; INT = 2; STRING = 3; TENSOR = 4; GRAPH = 5; SPARSE_TENSOR = 11; TYPE_PROTO = 13; FLOATS = 6; INTS = 7 # noqa: E702 + STRINGS = 8; TENSORS = 9; GRAPHS = 10; SPARSE_TENSORS = 12; TYPE_PROTOS = 14 # noqa: E702 + +class PBType: FLOAT = 1; INT = 2; STRING = 3; FLOATS = 4; INTS = 5; STRINGS = 6; BYTES = 7; SUB = 8 # noqa: E702 + +PB_INFOS = { + "OperatorSetIdProto": {1: ("domain", PBType.STRING), 2: ("version", PBType.INT)}, + "StringStringEntryProto": {1: ("key", PBType.STRING), 2: ("value", PBType.STRING)}, + # TODO: support uint64 parsing (11: "uint64_data") and double parsing (10: "double_data") + "TensorProto": {1: ("dims", PBType.INT, True), 2: ("data_type", PBType.INT), 4: ("float_data", PBType.FLOATS), + 13: ("external_data", PBType.SUB, True, "StringStringEntryProto"), 14: ("data_location", PBType.INT), + 5: ("int32_data", PBType.INTS), 7: ("int64_data", PBType.INTS), 8: ("name", PBType.STRING), 9: ("raw_data", PBType.BYTES)}, + "TensorShapeProtoDimension": {1: ("dim_value", PBType.INT), 2: ("dim_param", PBType.STRING)}, + "TensorShapeProto": {1: ("dim", PBType.SUB, True, "TensorShapeProtoDimension")}, + "ModelProto": {1: ("ir_version", PBType.INT), 5: ("model_version", PBType.INT), + 2: ("producer_name", PBType.STRING), 3: ("producer_version", PBType.STRING), 4: ("domain", PBType.STRING), 6: ("doc_string", PBType.STRING), + 7: ("graph", PBType.SUB, False, ("GraphProto", lambda: {"node": [], "initializer": [], "input": [], "output": [], "value_info": []})), + 8: ("opset_import",PBType.SUB, True, "OperatorSetIdProto")}, + "GraphProto": {2: ("name", PBType.STRING), 10: ("doc_string", PBType.STRING), + 1: ("node", PBType.SUB, True, ("NodeProto", lambda: {"input": [], "output": [], "attribute": [], "domain": None})), + 5: ("initializer", PBType.SUB, True, ("TensorProto", lambda: {"dims": [], "float_data": [], "int32_data": [], "string_data": [], + "int64_data": [], "double_data": [], "uint64_data": []})), + 11: ("input", PBType.SUB, True, "ValueInfoProto"), 12: ("output", PBType.SUB, True, "ValueInfoProto")}, + "NodeProto": { 1: ("input", PBType.STRING, True), 2: ("output", PBType.STRING, True), 3: ("name", PBType.STRING), + 4: ("op_type", PBType.STRING), 6: ("doc_string", PBType.STRING), 7: ("domain", PBType.STRING), + 5: ("attribute", PBType.SUB, True, ("AttributeProto", lambda: {"floats": [], "ints": [], "strings": []}))}, + "AttributeProto": {1: ("name", PBType.STRING), 20: ("type", PBType.INT), 3: ("i", PBType.INT), 8: ("ints", PBType.INT, True), + 2: ("f", PBType.FLOAT), 7: ("floats", PBType.FLOAT, True), 4: ("s", PBType.BYTES), 9: ("strings", PBType.BYTES, True), + 5:("t", PBType.SUB, False, ("TensorProto", lambda: {"dims": [], "float_data": [], "int32_data": [], "string_data": [], "int64_data": [], + "double_data": [], "uint64_data": []}))}, + "ValueInfoProto": {1: ("name", PBType.STRING), 2: ("type", PBType.SUB, False, "TypeProto"), 3: ("doc_string", PBType.STRING)}, + "TypeProto": {1: ("tensor_type", PBType.SUB, False, "TypeProtoTensor"), 4: ("sequence_type", PBType.SUB, False, "TypeProtoSequence"), + 9: ("optional_type", PBType.SUB, False, "TypeProtoOptional"), 6: ("denotation", PBType.STRING)}, + "TypeProtoSequence": {1: ("elem_type", PBType.SUB, False, "TypeProto")}, + "TypeProtoOptional": {1: ("elem_type", PBType.SUB, False, "TypeProto")}, + "TypeProtoTensor": {1: ("elem_type", PBType.INT), 2: ("shape", PBType.SUB, False, ("TensorShapeProto", lambda: {"dim": []}))}, +} + +def onnx_load(fn: Union[Tensor, str, pathlib.Path], load_external_data: bool=True): + parser = OnnxParser(fn, load_external_data) + onnx_model = parser.parse() + model = dict_to_namespace(onnx_model) + return model + +def gen_result(obj: dict, key_name, val, repeated: bool): + if repeated: obj.setdefault(key_name, []).append(val) + else: obj[key_name] = val + +def dict_to_namespace(d): + if isinstance(d, dict): return SimpleNamespace(**{k: dict_to_namespace(v) for k, v in d.items()}) + elif isinstance(d, list): return [dict_to_namespace(i) for i in d] + return d + +class OnnxParser: + def __init__(self, inp: Union[Tensor, str, pathlib.Path], load_external_data: bool=True): + self.file_path: Union[pathlib.Path, None] = None + self.load_external_data = load_external_data + if not isinstance(inp, Tensor): + self.file_path = pathlib.Path(inp) + self.tensor = Tensor(self.file_path) + else: self.tensor = inp + self.attr_func_dict = { PBType.BYTES: self._handle_bytes, PBType.SUB: self._handle_sub_message, PBType.FLOATS: self._handle_packed_floats, + PBType.INT: self._handle_int64, PBType.INTS: self._handle_packed_int64s, PBType.STRING: self._handle_string, PBType.FLOAT: self._handle_float} + self.registered_handles = {} + for pb_name in PB_INFOS: + res = {} + for fid, config in PB_INFOS[pb_name].items(): + parser_fn, repeated = None, False + if len(config) == 2: name, attr = config + elif len(config) == 3: name, attr, repeated = config + elif len(config) == 4: name, attr, repeated, parser_fn = config + handler_fn = self.attr_func_dict[attr] + def _wrapper_handler(obj, reader, wt, h=handler_fn, n=name, p=parser_fn, r=repeated): return h(obj, n, reader, wt, parser_func=p, repeated=r) + _wrapper_handler._debug_info = f"{fid}, {name} => {handler_fn}" + res[fid] = _wrapper_handler + self.registered_handles[pb_name] = res + + def parse(self): + reader = BufferedReader(TensorIO(self.tensor)) + return self._parse_message(reader, "ModelProto", lambda: {"opset_import": [], "domain": None, "graph": None}) + + def decode_varint(self, reader: BufferedReader) -> int: + result = 0 + shift = 0 + while True: + data = reader.read(1) + if data == b"": raise EOFError("decode_varint EOF") + result |= (data[0] & 0x7F) << shift + if not (data[0] & 0x80): return result + shift += 7 + if shift >= 70: raise ValueError("Varint too long") + + def skip_field_value(self, reader: BufferedReader, wire_type): + if wire_type == WIRETYPE_VARINT: self.decode_varint(reader) + elif wire_type == WIRETYPE_FIXED64: reader.seek(8, os.SEEK_CUR) + elif wire_type == WIRETYPE_FIXED32: reader.seek(4, os.SEEK_CUR) + elif wire_type == WIRETYPE_LENGTH_DELIMITED: reader.seek(self.decode_varint(reader), os.SEEK_CUR) + else: raise ValueError(f"Unknown wire type: {wire_type}") + + def _parse_message(self, reader, message_field_handlers_name, initial_obj_factory=lambda: {}): + message_field_handlers = self.registered_handles[message_field_handlers_name] + obj = initial_obj_factory() + while True: + try: + tag_val = self.decode_varint(reader) + field_number = tag_val >> 3 + wire_type = tag_val & 0x07 + if handler := message_field_handlers.get(field_number): + handler(obj, reader, wire_type) + else: self.skip_field_value(reader, wire_type) + except EOFError: break + if message_field_handlers_name == "TensorProto" and self.load_external_data and obj.get("data_location", 0) == 1: self._parse_external_data(obj) + return obj + + def _handle_delimited(self, reader:BufferedReader, use_tensor=False) -> Tuple[bytes, Tensor]: + str_len = self.decode_varint(reader) + if not use_tensor: return reader.read(str_len) + res = reader.raw._tensor[reader.tell():(reader.tell()+str_len)] + reader.seek(str_len, os.SEEK_CUR) + return res + + def _handle_string(self, obj, key_name, reader, wire_type, parser_func=None, repeated=False): + if wire_type != WIRETYPE_LENGTH_DELIMITED: raise ValueError(f"Expected length-delimited for string field '{key_name}'") + value = self._handle_delimited(reader) + gen_result(obj, key_name, value.decode("utf-8"), repeated) + + def _handle_bytes(self, obj, key_name, reader, wire_type, parser_func=None, repeated=False): + if wire_type != WIRETYPE_LENGTH_DELIMITED: raise ValueError(f"Expected length-delimited for bytes field '{key_name}'") + value = self._handle_delimited(reader, use_tensor=True) + gen_result(obj, key_name, value, repeated) + + def _handle_int64(self, obj, key_name, reader, wire_type, parser_func=None, repeated=False): + if wire_type != WIRETYPE_VARINT: raise ValueError(f"Expected varint for int64 field '{key_name}'") + val = self.decode_varint(reader) + gen_result(obj, key_name, val - 2**64 if val & (1 << 63) else val, repeated) + + def _handle_float(self, obj, key_name, reader, wire_type, parser_func=None, repeated=False): + if wire_type != WIRETYPE_FIXED32: raise ValueError(f"Expected fixed32 for float field '{key_name}'") + val, = struct.unpack(" None: - open(LOGOPS, "a").write(str(args[1]).replace("\n", "").replace(" ", "")+"\n") + open(LOGOPS, "a").write(str(args[0]).replace("\n", "").replace(" ", "")+"\n") return None if __name__ == "__main__": - _pmap({"get_program":extract_ast}) + _pmap("kernel", extract_ast) diff --git a/tinygrad_repo/extra/optimization/extract_policynet.py b/tinygrad_repo/extra/optimization/extract_policynet.py index c6a6865c7..663107f3f 100644 --- a/tinygrad_repo/extra/optimization/extract_policynet.py +++ b/tinygrad_repo/extra/optimization/extract_policynet.py @@ -5,9 +5,9 @@ from tinygrad.nn import Linear from tinygrad.tensor import Tensor from tinygrad.nn.optim import Adam from tinygrad.nn.state import get_parameters, get_state_dict, safe_save, safe_load, load_state_dict -from tinygrad.codegen.opt.search import actions +from tinygrad.opt.search import actions from extra.optimization.helpers import load_worlds, ast_str_to_lin, lin_to_feats, assert_same_lin -from tinygrad.codegen.opt.kernel import Kernel +from tinygrad.opt.kernel import Kernel from tinygrad.helpers import getenv # stuff needed to unpack a kernel @@ -17,7 +17,7 @@ from tinygrad.shape.shapetracker import ShapeTracker from tinygrad.shape.view import View from tinygrad.uop.ops import Variable inf, nan = float('inf'), float('nan') -from tinygrad.codegen.opt.kernel import Opt, OptOps +from tinygrad.opt.kernel import Opt, OptOps INNER = 256 class PolicyNet: diff --git a/tinygrad_repo/extra/optimization/extract_sa_pairs.py b/tinygrad_repo/extra/optimization/extract_sa_pairs.py index 2a91e4932..935860b16 100644 --- a/tinygrad_repo/extra/optimization/extract_sa_pairs.py +++ b/tinygrad_repo/extra/optimization/extract_sa_pairs.py @@ -10,11 +10,11 @@ from tinygrad.shape.shapetracker import ShapeTracker from tinygrad.shape.view import View from tinygrad.uop.ops import Variable inf, nan = float('inf'), float('nan') -from tinygrad.codegen.opt.kernel import Opt, OptOps +from tinygrad.opt.kernel import Opt, OptOps # more stuff -from tinygrad.codegen.opt.kernel import Kernel -from tinygrad.codegen.opt.search import actions +from tinygrad.opt.kernel import Kernel +from tinygrad.opt.search import actions from extra.optimization.helpers import lin_to_feats from extra.optimization.pretrain_valuenet import ValueNet from tinygrad.nn.optim import Adam diff --git a/tinygrad_repo/extra/optimization/generate_dataset.sh b/tinygrad_repo/extra/optimization/generate_dataset.sh old mode 100644 new mode 100755 index 6f7091697..66473154f --- a/tinygrad_repo/extra/optimization/generate_dataset.sh +++ b/tinygrad_repo/extra/optimization/generate_dataset.sh @@ -6,12 +6,24 @@ export CAPTURE_PROCESS_REPLAY=1 rm $LOGOPS test/external/process_replay/reset.py -CI=1 python3 -m pytest -n=auto test/test_ops.py test/test_nn.py test/test_winograd.py test/models/test_real_world.py --durations=20 -GPU=1 python3 -m pytest test/test_tiny.py +python3 -m pytest -n=auto test/ --ignore=test/unit --durations=20 +STEPS=3 python3 examples/hlb_cifar10.py +WINO=1 STEPS=3 python3 examples/hlb_cifar10.py +python3 examples/stable_diffusion.py --noshow +python3 examples/llama.py --prompt "hello" --count 5 +python3 examples/gpt2.py --count 5 +HALF=1 python3 examples/gpt2.py --count 5 +python3 examples/beautiful_mnist.py +python3 examples/beautiful_cartpole.py +python3 examples/mlperf/model_spec.py +python3 examples/yolov8.py ./test/models/efficientnet/Chicken.jpg +examples/openpilot/go.sh +JIT=2 BIG=1 MPS=1 pytest -n=auto test/ --ignore=test/test_fusion_op.py --ignore=test/test_linearizer_failures.py --ignore=test/test_gc.py --ignore=test/test_speed_v_torch.py --ignore=test/test_jit.py +JIT=2 BIG=1 MPS=1 python -m pytest test/test_gc.py +JIT=2 BIG=1 MPS=1 python -m pytest test/test_jit.py +JIT=2 BIG=1 MPS=1 python -m pytest test/test_speed_v_torch.py # extract, sort and uniq extra/optimization/extract_dataset.py sort -u /tmp/ops > /tmp/sops -ls -lh /tmp/ops /tmp/sops -gzip -k /tmp/sops -# mv /tmp/sops.gz extra/datasets/ \ No newline at end of file +ls -lh /tmp/ops /tmp/sops diff --git a/tinygrad_repo/extra/optimization/get_action_space.py b/tinygrad_repo/extra/optimization/get_action_space.py index d3fe0ab52..d27c56823 100644 --- a/tinygrad_repo/extra/optimization/get_action_space.py +++ b/tinygrad_repo/extra/optimization/get_action_space.py @@ -1,8 +1,8 @@ import random from extra.optimization.helpers import load_worlds, ast_str_to_lin -from tinygrad.codegen.opt.search import actions -from tinygrad.codegen.opt.kernel import Kernel -from tinygrad.codegen.opt.heuristic import hand_coded_optimizations +from tinygrad.opt.search import actions +from tinygrad.opt.kernel import Kernel +from tinygrad.opt.heuristic import hand_coded_optimizations from tinygrad.helpers import tqdm tactions = set() diff --git a/tinygrad_repo/extra/optimization/helpers.py b/tinygrad_repo/extra/optimization/helpers.py index 94eacaa8d..bca2eb6b8 100644 --- a/tinygrad_repo/extra/optimization/helpers.py +++ b/tinygrad_repo/extra/optimization/helpers.py @@ -1,17 +1,15 @@ # stuff needed to unpack a kernel from tinygrad import Variable -from tinygrad.codegen.opt.kernel import Opt, OptOps +from tinygrad.opt.kernel import Opt, OptOps from tinygrad.uop.ops import UOp, Ops, KernelInfo from tinygrad.dtype import dtypes, PtrDType from tinygrad.shape.shapetracker import ShapeTracker from tinygrad.shape.view import View -from tinygrad.helpers import getenv -from tinygrad.engine.realize import get_program inf, nan = float('inf'), float('nan') UOps = Ops # kernel unpacker -from tinygrad.codegen.opt.kernel import Kernel +from tinygrad.opt.kernel import Kernel def ast_str_to_ast(ast_str:str) -> UOp: return eval(ast_str) def ast_str_to_lin(ast_str:str, opts=None): return Kernel(ast_str_to_ast(ast_str), opts=opts) def kern_str_to_lin(kern_str:str, opts=None): @@ -28,7 +26,7 @@ from tinygrad.helpers import dedup, DEBUG def load_worlds(filter_reduce=True, filter_noimage=True, filter_novariable=True): fn = Path(__file__).parent.parent / "datasets/sops.gz" ast_strs = dedup(gzip.open(fn).read().decode('utf-8').strip().split("\n")) - assert len(ast_strs) >= getenv("MIN_ASTS", 1000), f"dataset size = {len(ast_strs)} is too small" + assert len(ast_strs) > 5000, f"dataset size = {len(ast_strs)} is too small" if DEBUG >= 1: print(f"loaded {len(ast_strs)=} before filters") if filter_reduce: ast_strs = [x for x in ast_strs if "REDUCE_AXIS" in x] if filter_noimage: ast_strs = [x for x in ast_strs if "dtypes.image" not in x] @@ -103,7 +101,7 @@ def lin_to_feats(lin:Kernel, use_sts=True): return ret from tinygrad.device import Device, Buffer -from tinygrad.codegen.opt.search import _ensure_buffer_alloc, _time_program +from tinygrad.opt.search import _ensure_buffer_alloc, _time_program from tinygrad.helpers import to_function_name, CACHELEVEL, diskcache_get, diskcache_put def time_linearizer(lin:Kernel, rawbufs:list[Buffer], allow_test_size=True, max_global_size=65536, cnt=3, disable_cache=False, clear_l2=False) -> float: # noqa: E501 @@ -116,7 +114,7 @@ def time_linearizer(lin:Kernel, rawbufs:list[Buffer], allow_test_size=True, max_ rawbufs = _ensure_buffer_alloc(rawbufs) var_vals: dict[Variable, int] = {k:int(k.vmax+k.vmin)//2 for k in lin.ast.variables()} - p = get_program(lin.get_optimized_ast(), lin.opts) + p = lin.to_program() tms = _time_program(p, dev.compiler.compile(p.src), var_vals, rawbufs, max_global_size=max_global_size if allow_test_size else None, clear_l2=clear_l2, cnt=cnt, name=to_function_name(lin.name)) diff --git a/tinygrad_repo/extra/optimization/pretrain_valuenet.py b/tinygrad_repo/extra/optimization/pretrain_valuenet.py index c73e429a4..2dd0f90c6 100644 --- a/tinygrad_repo/extra/optimization/pretrain_valuenet.py +++ b/tinygrad_repo/extra/optimization/pretrain_valuenet.py @@ -1,4 +1,4 @@ -from tinygrad.codegen.opt.kernel import Kernel +from tinygrad.opt.kernel import Kernel from tqdm import tqdm, trange import math import random @@ -14,7 +14,7 @@ from tinygrad.shape.shapetracker import ShapeTracker from tinygrad.shape.view import View from tinygrad.uop.ops import Variable inf, nan = float('inf'), float('nan') -from tinygrad.codegen.opt.kernel import Opt, OptOps +from tinygrad.opt.kernel import Opt, OptOps from extra.optimization.helpers import lin_to_feats, MAX_DIMS diff --git a/tinygrad_repo/extra/optimization/rl.py b/tinygrad_repo/extra/optimization/rl.py index 0a92161b1..d45e84b14 100644 --- a/tinygrad_repo/extra/optimization/rl.py +++ b/tinygrad_repo/extra/optimization/rl.py @@ -3,7 +3,7 @@ import numpy as np import math, random from tinygrad.tensor import Tensor from tinygrad.nn.state import get_parameters, get_state_dict, safe_save, safe_load, load_state_dict -from tinygrad.codegen.opt.search import actions, bufs_from_lin, get_kernel_actions +from tinygrad.opt.search import actions, bufs_from_lin, get_kernel_actions from tinygrad.nn.optim import Adam from extra.optimization.extract_policynet import PolicyNet from extra.optimization.helpers import load_worlds, ast_str_to_lin, lin_to_feats, time_linearizer diff --git a/tinygrad_repo/extra/optimization/run_qnet.py b/tinygrad_repo/extra/optimization/run_qnet.py index 3586199a8..6dfca1b37 100644 --- a/tinygrad_repo/extra/optimization/run_qnet.py +++ b/tinygrad_repo/extra/optimization/run_qnet.py @@ -1,6 +1,6 @@ from typing import List, Tuple -from tinygrad.codegen.opt.kernel import Kernel -from tinygrad.codegen.opt.search import get_kernel_actions, actions +from tinygrad.opt.kernel import Kernel +from tinygrad.opt.search import get_kernel_actions, actions _net = None def beam_q_estimate(beam:List[Tuple[Kernel, float]]) -> List[Tuple[Kernel, float]]: diff --git a/tinygrad_repo/extra/optimization/search.py b/tinygrad_repo/extra/optimization/search.py index 658ae953d..6b49f3622 100644 --- a/tinygrad_repo/extra/optimization/search.py +++ b/tinygrad_repo/extra/optimization/search.py @@ -4,8 +4,8 @@ from extra.optimization.helpers import ast_str_to_lin, time_linearizer from tinygrad import dtypes from tinygrad.helpers import BEAM, getenv from tinygrad.device import Device, Compiled -from tinygrad.codegen.opt.kernel import Kernel -from tinygrad.codegen.opt.search import beam_search, bufs_from_lin +from tinygrad.opt.kernel import Kernel +from tinygrad.opt.search import beam_search, bufs_from_lin if __name__ == '__main__': diff --git a/tinygrad_repo/extra/optimization/test_beam_search.py b/tinygrad_repo/extra/optimization/test_beam_search.py index 7042ea914..24c3f943b 100644 --- a/tinygrad_repo/extra/optimization/test_beam_search.py +++ b/tinygrad_repo/extra/optimization/test_beam_search.py @@ -16,9 +16,9 @@ class TestBeamSearch(unittest.TestCase): BEAM.value = self.old_beam def test_variable_ast_beam(self): - vi = Variable("a", 1, 10).bind(3) - a = rand(10, 3)[:vi] - a = (a+1).realize() + with Context(IGNORE_OOB=1): + a = rand(3, 3).reshape((Variable("a", 1, 10).bind(3), 3)) + a = (a+1).realize() def test_big_prime_number(self): a = rand(367, 367) @@ -42,16 +42,18 @@ class TestBeamSearch(unittest.TestCase): def test_variable_big_prime_number(self): v = Variable("v", 1, 400).bind(367) - a = rand(367, 400) - b = rand(400, 367) - c = (a[:, :v] @ b[:v, :]).realize() - np.testing.assert_allclose(c.numpy(), a[:, :367].numpy() @ b[:367, :].numpy(), atol=1e-4, rtol=1e-4) + a = rand(367, 367) + b = rand(367, 367) + with Context(IGNORE_OOB=1): + c = (a.reshape(367, v) @ b.reshape(v, 367)).realize() + np.testing.assert_allclose(c.numpy(), a.numpy() @ b.numpy(), atol=1e-4, rtol=1e-4) def test_variable_shrink_prime_number(self): v = Variable("v", 1, 400).bind(367) a = rand(400, 367) - b = (a.shrink(((0,v), None))+1).reshape(367,367).realize() - np.testing.assert_allclose(b.numpy(), a.numpy()[:367]+1, atol=1e-4, rtol=1e-4) + with Context(IGNORE_OOB=1): + b = (a.shrink(((0,v), None))+1).reshape(367,367).realize() + np.testing.assert_allclose(b.numpy(), a.numpy()[:367]+1, atol=1e-4, rtol=1e-4) def test_no_mutate_rawbuffers(self): a = rand(3, 3).realize() diff --git a/tinygrad_repo/extra/optimization/test_net.py b/tinygrad_repo/extra/optimization/test_net.py index 8e266fca6..efd228475 100644 --- a/tinygrad_repo/extra/optimization/test_net.py +++ b/tinygrad_repo/extra/optimization/test_net.py @@ -6,8 +6,8 @@ from copy import deepcopy from tinygrad.helpers import getenv, colored from tinygrad.tensor import Tensor from tinygrad.nn.state import get_parameters, get_state_dict, safe_save, safe_load, load_state_dict -from tinygrad.codegen.opt.search import bufs_from_lin, actions, get_kernel_actions -from tinygrad.codegen.opt.heuristic import hand_coded_optimizations +from tinygrad.opt.search import bufs_from_lin, actions, get_kernel_actions +from tinygrad.opt.heuristic import hand_coded_optimizations from extra.optimization.helpers import load_worlds, ast_str_to_lin, lin_to_feats, time_linearizer from extra.optimization.extract_policynet import PolicyNet from extra.optimization.pretrain_valuenet import ValueNet diff --git a/tinygrad_repo/extra/optimization/test_time_linearizer.py b/tinygrad_repo/extra/optimization/test_time_linearizer.py index 8764ccd4e..32d27b2f7 100644 --- a/tinygrad_repo/extra/optimization/test_time_linearizer.py +++ b/tinygrad_repo/extra/optimization/test_time_linearizer.py @@ -1,5 +1,5 @@ from extra.optimization.helpers import load_worlds, ast_str_to_lin, time_linearizer -from tinygrad.codegen.opt.search import bufs_from_lin, get_kernel_actions +from tinygrad.opt.search import bufs_from_lin, get_kernel_actions if __name__ == "__main__": ast_strs = load_worlds() diff --git a/tinygrad_repo/extra/perfetto/to_perfetto.py b/tinygrad_repo/extra/perfetto/to_perfetto.py deleted file mode 100644 index f12d1c494..000000000 --- a/tinygrad_repo/extra/perfetto/to_perfetto.py +++ /dev/null @@ -1,42 +0,0 @@ -import sys, pickle, decimal, json -from tinygrad.device import ProfileDeviceEvent, ProfileGraphEvent -from tinygrad.helpers import tqdm, temp, ProfileEvent, ProfileRangeEvent, TracingKey - -devices:dict[str, tuple[decimal.Decimal, decimal.Decimal, int]] = {} -def prep_ts(device:str, ts:decimal.Decimal, is_copy): return int(decimal.Decimal(ts) + devices[device][is_copy]) -def dev_to_pid(device:str, is_copy=False): return {"pid": devices[device][2], "tid": int(is_copy)} -def dev_ev_to_perfetto_json(ev:ProfileDeviceEvent): - devices[ev.device] = (ev.comp_tdiff, ev.copy_tdiff if ev.copy_tdiff is not None else ev.comp_tdiff, len(devices)) - return [{"name": "process_name", "ph": "M", "pid": dev_to_pid(ev.device)['pid'], "args": {"name": ev.device}}, - {"name": "thread_name", "ph": "M", "pid": dev_to_pid(ev.device)['pid'], "tid": 0, "args": {"name": "COMPUTE"}}, - {"name": "thread_name", "ph": "M", "pid": dev_to_pid(ev.device)['pid'], "tid": 1, "args": {"name": "COPY"}}] -def range_ev_to_perfetto_json(ev:ProfileRangeEvent): - name = ev.name.display_name if isinstance(ev.name, TracingKey) else ev.name - return [{"name": name, "ph": "X", "ts": prep_ts(ev.device, ev.st, ev.is_copy), "dur": float(ev.en-ev.st), **dev_to_pid(ev.device, ev.is_copy)}] -def graph_ev_to_perfetto_json(ev:ProfileGraphEvent, reccnt): - ret = [] - for i,e in enumerate(ev.ents): - st, en = ev.sigs[e.st_id], ev.sigs[e.en_id] - name = e.name.display_name if isinstance(e.name, TracingKey) else e.name - ret += [{"name": name, "ph": "X", "ts": prep_ts(e.device, st, e.is_copy), "dur": float(en-st), **dev_to_pid(e.device, e.is_copy)}] - for dep in ev.deps[i]: - d = ev.ents[dep] - ret += [{"ph": "s", **dev_to_pid(d.device, d.is_copy), "id": reccnt+len(ret), "ts": prep_ts(d.device, ev.sigs[d.en_id], d.is_copy), "bp": "e"}] - ret += [{"ph": "f", **dev_to_pid(e.device, e.is_copy), "id": reccnt+len(ret)-1, "ts": prep_ts(e.device, st, e.is_copy), "bp": "e"}] - return ret -def to_perfetto(profile:list[ProfileEvent]): - # Start json with devices. - profile += [ProfileDeviceEvent("TINY")] - - prof_json = [x for ev in profile if isinstance(ev, ProfileDeviceEvent) for x in dev_ev_to_perfetto_json(ev)] - for ev in tqdm(profile, desc="preparing profile"): - if isinstance(ev, ProfileRangeEvent): prof_json += range_ev_to_perfetto_json(ev) - elif isinstance(ev, ProfileGraphEvent): prof_json += graph_ev_to_perfetto_json(ev, reccnt=len(prof_json)) - return {"traceEvents": prof_json} - -if __name__ == "__main__": - fp = sys.argv[1] - with open(fp, "rb") as f: profile = pickle.load(f) - ret = to_perfetto(profile) - with open(fp:=temp("perfetto.json", append_user=True), "w") as f: json.dump(ret, f) - print(f"Saved perfetto output to {fp}. You can use upload this to the perfetto UI or Chrome devtools.") diff --git a/tinygrad_repo/extra/qcom_gpu_driver/gen.sh b/tinygrad_repo/extra/qcom_gpu_driver/gen.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/extra/remu/README.md b/tinygrad_repo/extra/remu/README.md index ce50fe254..3746ea07c 100644 --- a/tinygrad_repo/extra/remu/README.md +++ b/tinygrad_repo/extra/remu/README.md @@ -22,7 +22,7 @@ This will produce a binary in the `extra/remu/target/release` directory. The latest binaries are released in https://github.com/Qazalin/remu/releases. Alternatively, you can [build locally](#build-locally). -Tinygrad does not yet output RDNA3 kernels directly. You can either install comgr or use `AMD_LLVM=1` (default) if you have [LLVM@19](https://github.com/tinygrad/tinygrad/blob/e2ed673c946c8f1774d816c75e52a994c2dd8a88/.github/actions/setup-tinygrad/action.yml#L208). +Tinygrad does not yet output RDNA3 kernels directly. You can either install comgr or use `AMD_LLVM=1` if you have [LLVM@19](https://github.com/tinygrad/tinygrad/blob/e2ed673c946c8f1774d816c75e52a994c2dd8a88/.github/actions/setup-tinygrad/action.yml#L208). `PYTHONPATH="." MOCKGPU=1 AMD=1 python test/test_tiny.py TestTiny.test_plus` runs an emulated RDNA3 kernel with Remu. diff --git a/tinygrad_repo/extra/remu/src/thread.rs b/tinygrad_repo/extra/remu/src/thread.rs index 4662d3fa3..4cb84a561 100644 --- a/tinygrad_repo/extra/remu/src/thread.rs +++ b/tinygrad_repo/extra/remu/src/thread.rs @@ -673,7 +673,6 @@ impl<'a> Thread<'a> { 39 => f32::log2(s0), 42 => 1.0 / s0, 43 => 1.0 / s0, - 46 => 1.0 / f32::sqrt(s0), 51 => f32::sqrt(s0), _ => todo_instr!(instruction)?, } @@ -1247,7 +1246,7 @@ impl<'a> Thread<'a> { } let ret = match op { - 257 | 259 | 299 | 260 | 261 | 264 | 272 | 392 | 426 | 430 | 531 | 537 | 540 | 551 | 567 | 796 => { + 257 | 259 | 299 | 260 | 261 | 264 | 272 | 392 | 426 | 531 | 537 | 540 | 551 | 567 | 796 => { let s0 = f32::from_bits(s0).negate(0, neg).absolute(0, abs); let s1 = f32::from_bits(s1).negate(1, neg).absolute(1, abs); let s2 = f32::from_bits(s2).negate(2, neg).absolute(2, abs); @@ -1259,7 +1258,6 @@ impl<'a> Thread<'a> { 272 => f32::max(s0, s1), 299 => f32::mul_add(s0, s1, f32::from_bits(self.vec_reg[vdst])), 426 => s0.recip(), - 430 => 1.0 / f32::sqrt(s0), 531 => f32::mul_add(s0, s1, s2), 537 => f32::min(f32::min(s0, s1), s2), 540 => f32::max(f32::max(s0, s1), s2), @@ -2627,14 +2625,6 @@ mod test_vop1 { assert_eq!(thread.vec_reg[3], 1071644672); } - #[test] - fn test_v_rsq_f32() { - let mut thread = _helper_test_thread(); - thread.vec_reg[0] = f32::to_bits(4.0); - r(&vec![0x7E005D00, END_PRG], &mut thread); - assert_eq!(f32::from_bits(thread.vec_reg[0]), 0.5); - } - #[test] fn test_v_frexp_exp_i32_f64() { [(3573412790272.0, 42), (69.0, 7), (2.0, 2), (f64::NEG_INFINITY, 0)] diff --git a/tinygrad_repo/extra/remu/test/hwtest.py b/tinygrad_repo/extra/remu/test/hwtest.py new file mode 100644 index 000000000..76bd2f6e6 --- /dev/null +++ b/tinygrad_repo/extra/remu/test/hwtest.py @@ -0,0 +1,202 @@ +import numpy as np +import unittest +import subprocess, struct, math +from typing import cast +from tinygrad.runtime.ops_amd import AMDProgram, AMDDevice +from tinygrad import Tensor, dtypes, Device +from tinygrad.helpers import diskcache, OSX, getenv + +@diskcache +def assemble(code:str) -> bytes: + try: + LLVM_MC = "llvm-mc" if OSX else "/opt/rocm/llvm/bin/llvm-mc" + return subprocess.run([LLVM_MC, "--arch=amdgcn", "--mcpu=gfx1100", "--triple=amdgcn-amd-amdhsa", "-filetype=obj", "-o", "-"], + input=code.encode("utf-8"), stdout=subprocess.PIPE, stderr=subprocess.PIPE, check=True).stdout + except subprocess.CalledProcessError as e: + print("stderr:") + print(e.stderr.decode()) + raise + +# copied from extra/rdna +def get_prg(code:str, v_cnt:int, s_cnt:int): + function_name = "test" + metadata = f""" +amdhsa.kernels: +- .args: + - .address_space: global + .name: buf_0 + .offset: 0 + .size: 8 + .type_name: unsigned int* + .value_kind: global_buffer + .group_segment_fixed_size: 0 + .kernarg_segment_align: 8 + .kernarg_segment_size: 8 + .language: OpenCL C + .language_version: + - 1 + - 2 + .max_flat_workgroup_size: 256 + .name: test + .private_segment_fixed_size: 0 + .sgpr_count: {s_cnt} + .sgpr_spill_count: 0 + .symbol: test.kd + .uses_dynamic_stack: false + .vgpr_count: {v_cnt} + .vgpr_spill_count: 0 + .wavefront_size: 32 +amdhsa.target: amdgcn-amd-amdhsa--gfx1100 +amdhsa.version: +- 1 +- 2 + """ + boilerplate_start = f""" + .rodata + .global {function_name}.kd + .type {function_name}.kd,STT_OBJECT + .align 0x10 + .amdhsa_kernel {function_name}""" + kernel_desc = { + '.amdhsa_group_segment_fixed_size': 0, '.amdhsa_private_segment_fixed_size': 0, '.amdhsa_kernarg_size': 0, + '.amdhsa_next_free_vgpr': v_cnt, # this matters! + '.amdhsa_reserve_vcc': 0, '.amdhsa_reserve_xnack_mask': 0, + '.amdhsa_next_free_sgpr': s_cnt, + '.amdhsa_float_round_mode_32': 0, '.amdhsa_float_round_mode_16_64': 0, '.amdhsa_float_denorm_mode_32': 3, '.amdhsa_float_denorm_mode_16_64': 3, + '.amdhsa_dx10_clamp': 1, '.amdhsa_ieee_mode': 1, '.amdhsa_fp16_overflow': 0, + '.amdhsa_workgroup_processor_mode': 1, '.amdhsa_memory_ordered': 1, '.amdhsa_forward_progress': 0, '.amdhsa_enable_private_segment': 0, + '.amdhsa_system_sgpr_workgroup_id_x': 1, '.amdhsa_system_sgpr_workgroup_id_y': 1, '.amdhsa_system_sgpr_workgroup_id_z': 1, + '.amdhsa_system_sgpr_workgroup_info': 0, '.amdhsa_system_vgpr_workitem_id': 2, # is amdhsa_system_vgpr_workitem_id real? + '.amdhsa_exception_fp_ieee_invalid_op': 0, '.amdhsa_exception_fp_denorm_src': 0, + '.amdhsa_exception_fp_ieee_div_zero': 0, '.amdhsa_exception_fp_ieee_overflow': 0, '.amdhsa_exception_fp_ieee_underflow': 0, + '.amdhsa_exception_fp_ieee_inexact': 0, '.amdhsa_exception_int_div_zero': 0, + '.amdhsa_user_sgpr_dispatch_ptr': 0, '.amdhsa_user_sgpr_queue_ptr': 0, '.amdhsa_user_sgpr_kernarg_segment_ptr': 1, + '.amdhsa_user_sgpr_dispatch_id': 0, '.amdhsa_user_sgpr_private_segment_size': 0, '.amdhsa_wavefront_size32': 1, '.amdhsa_uses_dynamic_stack': 0} + code_start = f""".end_amdhsa_kernel + .text + .global {function_name} + .type {function_name},@function + .p2align 8 + {function_name}: + """ + ret = ".amdgpu_metadata\n" + metadata + ".end_amdgpu_metadata" + boilerplate_start + "\n" + '\n'.join("%s %d" % x for x in kernel_desc.items()) \ + + "\n" + code_start + code + f"\n.size {function_name}, .-{function_name}" + return AMDProgram(cast(AMDDevice, Device["AMD"]), function_name, assemble(ret)) + +def get_output(s:str, n_threads:int=1): + assert n_threads <= 32 + code = "\n".join(["s_load_b64 s[0:1], s[0:1], null", "v_lshlrev_b32_e32 v0, 2, v0", s, + "s_waitcnt 0", + "global_store_b32 v0, v1, s[0:1]", + "s_nop 0", "s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)", "s_endpgm"]) + test = Tensor.zeros((n_threads,), dtype=dtypes.uint32).contiguous().realize().uop.buffer + prg = get_prg(code, 32, 32) + prg(test._buf, global_size=(1, 1, 1), local_size=(n_threads, 1, 1), wait=True) + return test.numpy() + +def f16_to_bits(x:float) -> int: return struct.unpack(' float: return struct.unpack(' int: return struct.unpack('= 2 # batched Muon implementation by @scottjmaddox, and put into practice in the record by @YouJiacheng - - a, b, c = params - X = G - if G.size(-2) > G.size(-1): - X = X.mT - - # Ensure spectral norm is at most 1 - X = X / (X.norm(dim=(-2, -1), keepdim=True) + 1e-7) - # Perform the NS iterations - for _ in range(steps): - A = X @ X.mT - B = b * A + c * A @ A # quintic computation strategy adapted from suggestion by @jxbz, @leloykun, and @YouJiacheng - X = a * X + B @ X - - if G.size(-2) > G.size(-1): - X = X.mT - - return X - -def muon_update(grad, momentum, beta=0.95, ns_steps=5, ns_params=(3.4445, -4.7750, 2.0315), nesterov=True): - if beta: - momentum.mul_(beta).add_(grad) - update = grad.add(momentum,alpha=beta) if nesterov else momentum - else: update = grad - if update.ndim == 4: # for the case of conv filters - update = update.view(len(update), -1) - update = zeropower_via_newtonschulz5(update, steps=ns_steps, params=ns_params) - return update - -class SingleDeviceMuon(torch.optim.Optimizer): - """ - Muon variant for usage in non-distributed settings. - """ - def __init__(self, params, lr=0.02, weight_decay=0.0, momentum=0.95, ns_steps=5, ns_params=(3.4445, -4.7750, 2.0315), nesterov=True): - defaults = dict(lr=lr, weight_decay=weight_decay, momentum=momentum, ns_steps=ns_steps, ns_params=ns_params, nesterov=nesterov) - super().__init__(params, defaults) - - @torch.no_grad() - def step(self, closure=None): - - loss = None - if closure is not None: - with torch.enable_grad(): - loss = closure() - - for group in self.param_groups: - for p in group["params"]: - if p.grad is None: - p.grad = torch.zeros_like(p) # Force synchronization - state = self.state[p] - if len(state) == 0: - state["momentum_buffer"] = torch.zeros_like(p) - update = muon_update(p.grad, state["momentum_buffer"], beta=group["momentum"], ns_steps=group["ns_steps"], - ns_params=group["ns_params"], nesterov=group["nesterov"]) - p.mul_(1.0 - group["lr"] * group["weight_decay"]) - - p.add_(update.reshape(p.shape), alpha=-group["lr"]) - - return loss diff --git a/tinygrad_repo/extra/usbgpu/legacy/patch_exp.py b/tinygrad_repo/extra/usbgpu/legacy/patch_exp.py old mode 100644 new mode 100755 diff --git a/tinygrad_repo/extra/usbgpu/patch.py b/tinygrad_repo/extra/usbgpu/patch.py old mode 100644 new mode 100755 diff --git a/tinygrad_repo/pytest.ini b/tinygrad_repo/pytest.ini deleted file mode 100644 index cccc62e40..000000000 --- a/tinygrad_repo/pytest.ini +++ /dev/null @@ -1,2 +0,0 @@ -[pytest] -norecursedirs = extra diff --git a/tinygrad_repo/ruff.toml b/tinygrad_repo/ruff.toml index 22f9bf566..ac3ee4950 100644 --- a/tinygrad_repo/ruff.toml +++ b/tinygrad_repo/ruff.toml @@ -35,19 +35,10 @@ lint.select = [ line-length = 150 exclude = [ - ".git/", "docs/", + "examples/", "extra/", "tinygrad/runtime/autogen", "test/external/mlperf_resnet", "test/external/mlperf_unet3d", ] - -# detect unused imports in examples -[lint.per-file-ignores] -"examples/**/*.py" = [ - "W6", "E71", "E72", "E112", "E113", "E203", "E272", "E275", - "E303", "E304", "E501", "E702", "E703", "E731", "W191", - "W291", "W293", "UP039", "C416", "RET506", "RET507", "A", - "FURB110", "RUF018", "F541", "F841" -] \ No newline at end of file diff --git a/tinygrad_repo/serve_docs.sh b/tinygrad_repo/serve_docs.sh old mode 100644 new mode 100755 diff --git a/tinygrad_repo/setup.py b/tinygrad_repo/setup.py index 7785a5427..3f56dee42 100644 --- a/tinygrad_repo/setup.py +++ b/tinygrad_repo/setup.py @@ -9,7 +9,7 @@ with open(directory / 'README.md', encoding='utf-8') as f: testing_minimal = [ "numpy", - "torch==2.7.1", + "torch", "pytest", "pytest-xdist", "hypothesis", @@ -18,36 +18,17 @@ testing_minimal = [ ] setup(name='tinygrad', - version='0.11.0', + version='0.10.3', description='You like pytorch? You like micrograd? You love tinygrad! <3', author='George Hotz', license='MIT', long_description=long_description, long_description_content_type='text/markdown', - packages = [ - 'tinygrad', - 'tinygrad.apps', - 'tinygrad.codegen', - 'tinygrad.codegen.opt', - 'tinygrad.codegen.late', - 'tinygrad.engine', - 'tinygrad.frontend', - 'tinygrad.nn', - 'tinygrad.renderer', - 'tinygrad.runtime', - 'tinygrad.runtime.autogen', - 'tinygrad.runtime.autogen.am', - 'tinygrad.runtime.autogen.nv', - 'tinygrad.runtime.graph', - 'tinygrad.runtime.support', - 'tinygrad.runtime.support.am', - 'tinygrad.runtime.support.nv', - 'tinygrad.schedule', - 'tinygrad.shape', - 'tinygrad.uop', - 'tinygrad.viz', - ], - package_data = {'tinygrad': ['py.typed'], 'tinygrad.viz': ['index.html', 'assets/**/*', 'js/*']}, + packages = ['tinygrad', 'tinygrad.runtime.autogen', 'tinygrad.runtime.autogen.am', 'tinygrad.codegen', 'tinygrad.nn', + 'tinygrad.renderer', 'tinygrad.engine', 'tinygrad.viz', 'tinygrad.runtime', 'tinygrad.runtime.support', 'tinygrad.kernelize', + 'tinygrad.runtime.support.am', 'tinygrad.runtime.graph', 'tinygrad.shape', 'tinygrad.uop', 'tinygrad.opt', + 'tinygrad.runtime.support.nv'], + package_data = {'tinygrad': ['py.typed'], 'tinygrad.viz': ['index.html', 'perfetto.html', 'assets/**/*', 'js/*']}, classifiers=[ "Programming Language :: Python :: 3", "License :: OSI Approved :: MIT License" @@ -64,7 +45,6 @@ setup(name='tinygrad', "pre-commit", "ruff", "numpy", - "typeguard", ], #'mlperf': ["mlperf-logging @ git+https://github.com/mlperf/logging.git@5.0.0-rc3"], 'testing_minimal': testing_minimal, @@ -75,7 +55,7 @@ setup(name='tinygrad', ], 'testing': testing_minimal + [ "pillow", - "onnx==1.18.0", + "onnx==1.17.0", "onnx2torch", "onnxruntime", "opencv-python", diff --git a/tinygrad_repo/sz.py b/tinygrad_repo/sz.py old mode 100644 new mode 100755 diff --git a/tinygrad_repo/test/Dockerfile b/tinygrad_repo/test/Dockerfile new file mode 100644 index 000000000..260a0b0bf --- /dev/null +++ b/tinygrad_repo/test/Dockerfile @@ -0,0 +1,12 @@ +FROM ubuntu:22.04 + +# Install python3.10, and pip3 +RUN apt-get update && apt-get install -y --no-install-recommends \ + python3.10 \ + python3-pip \ + && rm -rf /var/lib/apt/lists/* + +# Install python dependencies +COPY . ./tinygrad +WORKDIR tinygrad +RUN pip install -e . diff --git a/tinygrad_repo/tinygrad/schedule/__init__.py b/tinygrad_repo/test/__init__.py similarity index 100% rename from tinygrad_repo/tinygrad/schedule/__init__.py rename to tinygrad_repo/test/__init__.py diff --git a/tinygrad_repo/test/external/external_benchmark_am.py b/tinygrad_repo/test/external/external_benchmark_am.py new file mode 100644 index 000000000..6ac8bbfdb --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_am.py @@ -0,0 +1,9 @@ +from tinygrad.helpers import Profiling +from tinygrad import Device + +if __name__ == "__main__": + am = Device["AMD"] + + # kfd is 0.55ms! + with Profiling("allocation 127.7mb"): + am.allocator.alloc(int(127.7*1024*1024)) diff --git a/tinygrad_repo/test/external/external_benchmark_bert_matmuls.py b/tinygrad_repo/test/external/external_benchmark_bert_matmuls.py new file mode 100644 index 000000000..4f64629b5 --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_bert_matmuls.py @@ -0,0 +1,18 @@ +from tinygrad import Tensor, dtypes +dtypes.default_float = dtypes.float16 +from tinygrad.dtype import to_dtype +from tinygrad.helpers import getenv + +if __name__ == "__main__": + # matmuls in bert layers + BS = getenv("BS", 96//6) + acc_dtype = to_dtype(getenv("ACC_DTYPE", "half")) + tensors = [ + (Tensor.empty(BS, 512, 1024), Tensor.empty(1024, 1024).T), # linear to get qkv + (Tensor.empty(BS, 512, 16, 64).permute(0,2,1,3), Tensor.empty(BS, 512, 16, 64).permute(0,2,3,1)), # q@k + (Tensor.empty(BS, 16, 512, 512), Tensor.empty(BS, 512, 16, 64).permute(0,2,1,3)), # qk@v + ] + for t0, t1 in tensors: + print(f"{t0.shape=}, {t0.uop.st.real_strides()=}, {t1.shape=}, {t1.uop.st.real_strides()=}") + for _ in range(5): + t0.dot(t1, dtype=acc_dtype).realize() diff --git a/tinygrad_repo/test/external/external_benchmark_bert_softmax.py b/tinygrad_repo/test/external/external_benchmark_bert_softmax.py new file mode 100644 index 000000000..176e2061a --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_bert_softmax.py @@ -0,0 +1,18 @@ +from tinygrad import Tensor, dtypes, Context, GlobalCounters +dtypes.default_float = dtypes.float16 +from tinygrad.dtype import to_dtype +from tinygrad.helpers import getenv +from test.test_softmax_fusion import single_kernel_softmax + +if __name__ == "__main__": + # softmax in bert layers + BS = getenv("BS", 96//6) + acc_dtype = to_dtype(getenv("ACC_DTYPE", "half")) + t = Tensor.empty(BS, 16, 512, 512) + t.softmax(-1, dtype="half").realize() + + # test single kernel softmax + GlobalCounters.reset() + with Context(DONT_GROUP_REDUCES=1): + single_kernel_softmax(t, -1, acc_dtype).realize() + diff --git a/tinygrad_repo/test/external/external_benchmark_disk_raw.py b/tinygrad_repo/test/external/external_benchmark_disk_raw.py new file mode 100644 index 000000000..6566ae410 --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_disk_raw.py @@ -0,0 +1,7 @@ +import pathlib +from tinygrad import Tensor, Device, Context + +if __name__ == "__main__": + with Context(DEBUG=2): + disk_llama = Tensor(pathlib.Path("/raid/weights/LLaMA-3/8B/consolidated.00.pth")) + device_llama = disk_llama.to(Device.DEFAULT).realize() diff --git a/tinygrad_repo/test/external/external_benchmark_hcopt.py b/tinygrad_repo/test/external/external_benchmark_hcopt.py new file mode 100644 index 000000000..c10c0e89c --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_hcopt.py @@ -0,0 +1,43 @@ +import random +from tinygrad.helpers import getenv +from tinygrad.opt.search import beam_search, bufs_from_lin +from tinygrad.opt.heuristic import hand_coded_optimizations +from extra.optimization.helpers import load_worlds, ast_str_to_lin, time_linearizer + +def optimize_kernel(k): + # TODO: update this + return hand_coded_optimizations(k) + +if __name__ == '__main__': + hcopt_wins = beam_wins = tie = 0 + hcopt_total = beam_total = 0.0 + + worlds = load_worlds(filter_reduce=False, filter_noimage=True, filter_novariable=False) + random.seed(0) + random.shuffle(worlds) + + for world in worlds[:500]: + k = ast_str_to_lin(world) + rawbufs = bufs_from_lin(k) + + k_hcopt = k.copy() + k_hcopt.apply_opts(optimize_kernel(k_hcopt)) + k_beam = beam_search(k.copy(), rawbufs, getenv("BEAM", 2)) + + disable_cache = bool(getenv("NOCACHE", 0)) + t_hcopt = time_linearizer(k_hcopt, rawbufs, allow_test_size=False, cnt=10, disable_cache=disable_cache, clear_l2=True) * 1e6 + t_beam = time_linearizer(k_beam, rawbufs, allow_test_size=False, cnt=10, disable_cache=disable_cache, clear_l2=True) * 1e6 + + if t_hcopt == t_beam: tie += 1 + elif t_hcopt < t_beam: hcopt_wins += 1 + else: beam_wins += 1 + hcopt_total += t_hcopt + beam_total += t_beam + + print(f"{t_hcopt=:5.2f} {k_hcopt.applied_opts=}") + print("") + print(f"{t_beam=:5.2f} {k_beam.applied_opts=}") + print("*"*20) + + print(f"{hcopt_wins=}, {beam_wins=}, {tie=}") + print(f"{hcopt_total=:.2f}, {beam_total=:.2f}") \ No newline at end of file diff --git a/tinygrad_repo/test/external/external_benchmark_hip_compile.py b/tinygrad_repo/test/external/external_benchmark_hip_compile.py new file mode 100644 index 000000000..2b1d48034 --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_hip_compile.py @@ -0,0 +1,31 @@ +import random, os +from tinygrad.helpers import Timing +from tinygrad.runtime.ops_hip import compile_hip, HIPDevice +from tinygrad.runtime.ops_gpu import compile_cl, CLDevice + +# OMP_NUM_THREADS=1 strace -tt -f -e trace=file python3 test/external/external_benchmark_hip_compile.py +# AMD_COMGR_REDIRECT_LOGS=stdout AMD_COMGR_EMIT_VERBOSE_LOGS=1 python3 test/external/external_benchmark_hip_compile.py + +# issue is in https://github.com/ROCm-Developer-Tools/clr/ + +if __name__ == "__main__": + HIPDevice() + CLDevice() + + # warmup + name = "none"+str(random.randint(0, 1000000)) + compile_cl.__wrapped__(f"void {name}() {{}}") + print("compile cl warmed up") + compile_hip.__wrapped__(f"void {name}() {{}}") + print("compile hip warmed up") + + print("**** benchmark ****") + name = "none"+str(random.randint(0, 1000000)) + # this uses AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC, then it links the lib on the next step + with Timing("compile cl: "): compile_cl.__wrapped__(f"void {name}() {{}}") + # this uses AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC, much slower + with Timing("compile hip: "): compile_hip.__wrapped__(f"void {name}() {{}}") + os._exit(0) + + + diff --git a/tinygrad_repo/test/external/external_benchmark_keccak.py b/tinygrad_repo/test/external/external_benchmark_keccak.py new file mode 100644 index 000000000..1365ca9b7 --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_keccak.py @@ -0,0 +1,20 @@ +from tinygrad import Tensor, dtypes +from tinygrad.engine.jit import TinyJit +from tinygrad.helpers import Timing, getenv + +if __name__ == "__main__": + BS = getenv("BS", 2**14) + BLOCKSIZE = getenv("BLOCKSIZE", 4096) + HASHFN = getenv("HASHFN", "shake_128") + NRUNS = getenv("NRUNS", 5) + + @TinyJit + def hasher(data: Tensor): return data.keccak(HASHFN) + + t = Tensor.randn(BS, BLOCKSIZE, dtype=dtypes.uint8).realize() + ds_mib = t.nbytes() / 1024**2 + + print(f"--- benchmarking (hash: {HASHFN}, data size: {ds_mib} MiB, block size: {BLOCKSIZE} B, batch size: {BS})") + for i in range(NRUNS): + with Timing(f"run: {i+1}, elapsed time: ", (lambda et: f", throughput: {ds_mib / (et*1e-9):.2f} MiB/s")): + hasher(t).realize() diff --git a/tinygrad_repo/test/external/external_benchmark_kernel_launch.py b/tinygrad_repo/test/external/external_benchmark_kernel_launch.py new file mode 100644 index 000000000..5744ba092 --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_kernel_launch.py @@ -0,0 +1,38 @@ +import time +from tinygrad import Tensor, TinyJit, Device, Context +from tinygrad.helpers import Profiling, Timing, GlobalCounters + +# python3 test/test_speed_v_torch.py TestSpeed.test_add_a + +@TinyJit +def plus(a:Tensor, b:Tensor): return a+b + +if __name__ == "__main__": + a = Tensor([1]).realize() + b = Tensor([1]).realize() + for i in range(5): + with Timing(prefix=f"{i}:"): + c = plus(a,b) + Device[c.device].synchronize() + assert c.item() == 2 + for i in range(5): + st = time.perf_counter() + c = plus(a,b) + et = time.perf_counter() - st + Device[c.device].synchronize() + print(f"nosync {i}: {et*1e6:.2f} us") + for i in range(5): + st = time.perf_counter() + c = plus(a,b) + Device[c.device].synchronize() + et = time.perf_counter() - st + print(f"precise {i}: {et*1e6:.2f} us") + assert GlobalCounters.time_sum_s == 0 + with Context(DEBUG=2): + st = time.perf_counter() + c = plus(a,b) + Device[c.device].synchronize() + et = time.perf_counter() - st + print(f"kernel {GlobalCounters.time_sum_s*1e3:.2f} ms / full {et*1e3:.2f} ms -- {et/(GlobalCounters.time_sum_s+1e-12):.2f} x") + with Profiling(): + c = plus(a,b) diff --git a/tinygrad_repo/test/external/external_benchmark_llama_schedule.py b/tinygrad_repo/test/external/external_benchmark_llama_schedule.py new file mode 100644 index 000000000..a48f9e361 --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_llama_schedule.py @@ -0,0 +1,35 @@ +from tinygrad import nn, Tensor, Device, dtypes +from tinygrad.helpers import Timing + +from extra.models.llama import Transformer +from examples.llama3 import MODEL_PARAMS + +if __name__ == "__main__": + Device.DEFAULT = "NULL" + Tensor.training = True + #model_size = "8B" + model_size = "405B" + + with Timing("total "): + with Timing("***** create model in "): + model = Transformer(**MODEL_PARAMS[model_size]["args"], linear=nn.Linear, embedding=nn.Embedding, + max_context=1024, jit=True, disable_kv_cache=True) + + with Timing("***** fake state in "): + Tensor.realize(*[p.assign(Tensor.empty(*p.shape, device=p.device, dtype=p.dtype)) for p in nn.state.get_parameters(model)]) + + with Timing("***** create optim in "): + opt = nn.optim.AdamW(nn.state.get_parameters(model)) + + with Timing("***** run model in "): + toks = Tensor.empty(1, 1024, dtype=dtypes.int) + out = model(toks, 0, temperature=float('nan')) + + with Timing("***** backward in "): + out.mean().backward() + + with Timing("***** realize in "): + out.realize() + + with Timing("***** step in "): + opt.step() diff --git a/tinygrad_repo/test/external/external_benchmark_load_stable_diffusion.py b/tinygrad_repo/test/external/external_benchmark_load_stable_diffusion.py new file mode 100644 index 000000000..6ee0d0a32 --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_load_stable_diffusion.py @@ -0,0 +1,13 @@ +from tinygrad.helpers import fetch, Timing +from tinygrad.device import Device +from tinygrad.nn.state import torch_load, load_state_dict +from examples.stable_diffusion import StableDiffusion + +# run "sudo purge" before testing on OS X to avoid the memory cache + +if __name__ == "__main__": + fn = fetch('https://huggingface.co/CompVis/stable-diffusion-v-1-4-original/resolve/main/sd-v1-4.ckpt', 'sd-v1-4.ckpt') + model = StableDiffusion() + with Timing(): + load_state_dict(model, torch_load(fn)['state_dict'], strict=False) + Device[Device.DEFAULT].synchronize() diff --git a/tinygrad_repo/test/external/external_benchmark_multitensor_allreduce.py b/tinygrad_repo/test/external/external_benchmark_multitensor_allreduce.py new file mode 100644 index 000000000..e2fd001a0 --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_multitensor_allreduce.py @@ -0,0 +1,55 @@ +from tinygrad import Tensor, Device, GlobalCounters, TinyJit, dtypes +from tinygrad.helpers import getenv, Context, RING, DEBUG + +def test(devs: list[str], N: int, iters:int = 10): + @TinyJit + def f(t: Tensor) -> Tensor: t.sum(0).realize() + + secs, gflops, gbs = 0, 0, 0 + for i in range(-3, iters): + t = Tensor.empty((len(devs), N)) + t = t.shard(devs, 0).realize() + GlobalCounters.reset() + f(t) + for d in devs: Device[d].synchronize() + + if i < 0: continue # warm up jit + i_secs = GlobalCounters.time_sum_s + i_gflops = GlobalCounters.global_ops/i_secs/10**9 + i_gbs = (N*4)/i_secs/10**9 + print(f"{'ring_allreduce' if RING >= 2 else 'naive_allreduce'} iter {i+1}/{iters}: {i_secs:.6f} sec {i_gflops:.2f} GFLOP/s {i_gbs:.2f} GB/s") + secs += i_secs + gflops += i_gflops + gbs += i_gbs + + return (gflops/iters, gbs/iters, secs/iters) + +def run(sz, n_gpus=6, iters=10, use_ring=False): + devs = tuple([f"{Device.DEFAULT}:{x}" for x in range(n_gpus)]) + N = sz // dtypes.float32.itemsize + with Context(RING=(2 if use_ring else 0), DEBUG=max(DEBUG.value, 2)): return test(devs, N, iters=iters) + +def main(): + ONLY_RING = getenv("ONLY_RING", 0) + n_gpus = getenv("GPUS", 6) + iters = getenv("ITERS", 10) + + if getenv("BENCHMARK_SPLIT"): + l, r = 0, 512 + while r - l > 1: + m = (l + r) // 2 + (ring_gflops, ring_gbs, ring_secs) = run(m * 1024 * 4, n_gpus=n_gpus, iters=100, use_ring=True) + (naive_gflops, naive_gbs, naive_secs) = run(m * 1024 * 4, n_gpus=n_gpus, iters=100, use_ring=False) + if ring_secs > naive_secs: l = m + else: r = m + print("Better split", r * 1024, "elements") + else: + sz = getenv("SZ", 1000) * 10**6 # size of data on each gpu + print(f"Using {sz/10**9:.2f} GB of numbers on each of {n_gpus} GPUs, {n_gpus*sz/10**9:.2f} GB total.") + (ring_gflops, ring_gbs, ring_secs) = run(sz, use_ring=True, n_gpus=n_gpus, iters=iters) + if not ONLY_RING: (naive_gflops, naive_gbs, naive_secs) = run(sz, use_ring=False, n_gpus=n_gpus, iters=iters) + print(f"Ring:\n {ring_secs:.6f} seconds/iter\n {ring_gflops:.2f} GFLOP/s\n {ring_gbs:.2f} GB/s") + if not ONLY_RING: print(f"Naive:\n {naive_secs:.6f} seconds/iter\n {naive_gflops:.2f} GFLOP/s\n {naive_gbs:.2f} GB/s") + +if __name__ == "__main__": + main() diff --git a/tinygrad_repo/test/external/external_benchmark_openpilot.py b/tinygrad_repo/test/external/external_benchmark_openpilot.py new file mode 100644 index 000000000..de856b2f8 --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_openpilot.py @@ -0,0 +1,64 @@ +import time, sys, hashlib +from pathlib import Path +from onnx.helper import tensor_dtype_to_np_dtype +from tinygrad.frontend.onnx import OnnxRunner, onnx_load +from tinygrad import Tensor, dtypes, TinyJit +from tinygrad.helpers import IMAGE, GlobalCounters, fetch, colored, getenv, trange +from tinygrad.tensor import _from_np_dtype +import numpy as np +from extra.bench_log import BenchEvent, WallTimeEvent + +OPENPILOT_MODEL = sys.argv[1] if len(sys.argv) > 1 else "https://github.com/commaai/openpilot/raw/v0.9.4/selfdrive/modeld/models/supercombo.onnx" + +if __name__ == "__main__": + onnx_model = onnx_load(onnx_path := fetch(OPENPILOT_MODEL)) + run_onnx = OnnxRunner(onnx_model) + + Tensor.manual_seed(100) + input_shapes = {inp.name:tuple(x.dim_value for x in inp.type.tensor_type.shape.dim) for inp in onnx_model.graph.input} + input_types = {inp.name: tensor_dtype_to_np_dtype(inp.type.tensor_type.elem_type) for inp in onnx_model.graph.input} + new_inputs = {k:Tensor.randn(*shp, dtype=_from_np_dtype(input_types[k])).mul(8).realize() for k,shp in input_shapes.items()} + new_inputs_junk = {k:Tensor.randn(*shp, dtype=_from_np_dtype(input_types[k])).mul(8).realize() for k,shp in input_shapes.items()} + new_inputs_junk_numpy = {k:v.numpy() for k,v in new_inputs_junk.items()} + + # benchmark + for _ in range(5): + GlobalCounters.reset() + st = time.perf_counter_ns() + ret = next(iter(run_onnx(new_inputs_junk).values())).cast(dtypes.float32).numpy() + print(f"unjitted: {(time.perf_counter_ns() - st)*1e-6:7.4f} ms") + + # NOTE: the inputs to a JIT must be first level arguments + run_onnx_jit = TinyJit(lambda **kwargs: run_onnx(kwargs), prune=True) + for _ in range(20): + GlobalCounters.reset() + st = time.perf_counter_ns() + with WallTimeEvent(BenchEvent.STEP): + # Need to cast non-image inputs from numpy, this is only realistic way to run model + inputs = {**{k:v for k,v in new_inputs_junk.items() if 'img' in k}, + **{k:Tensor(v) for k,v in new_inputs_junk_numpy.items() if 'img' not in k}} + ret = next(iter(run_onnx_jit(**inputs).values())).cast(dtypes.float32).numpy() + print(f"jitted: {(time.perf_counter_ns() - st)*1e-6:7.4f} ms") + + suffix = "" + if IMAGE.value < 2: suffix += f"_image{IMAGE.value}" # image=2 has no suffix for compatibility + if getenv("FLOAT16") == 1: suffix += "_float16" + path = Path(__file__).parent / "openpilot" / f"{hashlib.md5(OPENPILOT_MODEL.encode()).hexdigest()}{suffix}.npy" + + # validate if we have records + tinygrad_out = next(iter(run_onnx_jit(**new_inputs).values())).cast(dtypes.float32).numpy() + if getenv("SAVE_OUTPUT"): + np.save(path, tinygrad_out) + print(f"saved output to {path}!") + elif getenv("FUZZ") and path.exists(): + known_good_out = np.load(path) + for _ in trange(1000): + ret = next(iter(run_onnx_jit(**new_inputs).values())).cast(dtypes.float32).numpy() + np.testing.assert_allclose(known_good_out, ret, atol=1e-2, rtol=1e-2) + print(colored("fuzz validated!", "green")) + elif path.exists(): + known_good_out = np.load(path) + np.testing.assert_allclose(known_good_out, tinygrad_out, atol=1e-2, rtol=1e-2) + print(colored("outputs validated!", "green")) + else: + print(colored("skipping validation", "yellow")) diff --git a/tinygrad_repo/test/external/external_benchmark_resnet.py b/tinygrad_repo/test/external/external_benchmark_resnet.py new file mode 100644 index 000000000..bef7cf634 --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_resnet.py @@ -0,0 +1,127 @@ +import functools +import time +import unittest + +from tinygrad import Tensor, TinyJit, GlobalCounters, Device +from tinygrad.helpers import getenv, Context +from tinygrad.nn.optim import SGD +from tinygrad.nn.state import get_parameters +from tinygrad.engine.realize import run_schedule + +from extra.models import resnet +from examples.mlperf.initializers import Conv2dHeNormal, Linear +from examples.hlb_cifar10 import UnsyncedBatchNorm + +# benchmark memory or kernel count: DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py +# benchmark speed: BEAM=2 JITCNT=10 DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py +# benchmark only one layer: BEAM=2 DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py BenchmarkResnetTrain.test_layer1_2 +# inspect: DEBUG=2 BEAM=2 DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py +# inspect 1x1 convs: DEBUG=2 BEAM=2 CONV=2 DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py +# inspect 3x3 convs: DEBUG=2 BEAM=2 CONV=2 DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py +# inspect 3x3 convs with batchnorm: DEBUG=2 BEAM=2 CONV=2 BN=1 DEFAULT_FLOAT=HALF python test/external/external_benchmark_resnet.py +# etc + +# use ASSIGN=0 to disable batchnorm/optimizer assigns + +# memory will be slightly high with JITCNT > 1 + +bs = getenv("BS", 64) + +class BenchmarkResnetTrain(unittest.TestCase): + def _get_layer(self, layer_i, slice_i): + # isolate to conv, with or without BN + conv = getenv("CONV", 0) + bn = getenv("BN", 0) + + if not hasattr(self, 'model'): + resnet.Conv2d = Conv2dHeNormal + resnet.Linear = Linear + if not getenv("SYNCBN"): resnet.BatchNorm = functools.partial(UnsyncedBatchNorm, num_devices=1) + self.model = resnet.ResNet50() + self.layers = [self.model.layer1, self.model.layer2, self.model.layer3, self.model.layer4] + + layer = self.layers[layer_i][slice_i] + xy = 112 >> layer_i + xy >>= (1 if slice_i > 0 or layer_i == 0 else 0) # layer 1 is preceded by maxpool2d + name = f"layer{layer_i+1} slice{slice_i+1}" + + # get specific conv + if conv: + convs = [layer.conv1, layer.conv2, layer.conv3] + ([layer.downsample[0]] if layer.downsample else []) + bns = [layer.bn1, layer.bn2, layer.bn3] + ([layer.downsample[1]] if layer.downsample else []) + f = [convs[conv-1]] + if bn: f.append(bns[conv-1]) + f.append(Tensor.relu) + cin = f[0].in_channels + if conv == 3: xy //= convs[1].stride + return f"{name} conv{conv} x{str((bs, cin, xy, xy)):20s} k{str(f[0].weight.shape):20s}" + (" bn" if bn else ""), f, cin, xy + + cin = layer.conv1.in_channels + return f"{name} x{(bs, cin, xy, xy)}", [layer], cin, xy + def _test_layer(self, name, layer, cin, xy): + optim = SGD(get_parameters(layer), bs / 128 * 1.0) # need sgd for some params but not consequential for benchmarking + with Context(TRACK_MATCH_STATS=0): Tensor.realize(*[t.assign(t.detach().contiguous()) for t in get_parameters(optim)]) + + JITCNT = getenv("JITCNT", 1) + Tensor.training = True + @TinyJit + def step(x): + optim.zero_grad() + x.grad = None + + y = x.sequential(layer).contiguous().contiguous_backward() + y.sum().backward() + if getenv("ASSIGN", 1): sched, _ = Tensor.schedule_with_vars(y, x.grad, *optim.schedule_step()) + else: sched, _ = Tensor.schedule_with_vars(y, x.grad, *[t.grad for t in optim.params]) + + for _ in range(JITCNT): + run_schedule(list(sched)) + + CNT = getenv("CNT", 5) + best_tm = None + flops, mem_used, mem, kernels = None, None, None, None + for i in range(CNT): + with Context(TRACK_MATCH_STATS=0): x = Tensor.randn(bs, cin, xy, xy, requires_grad=True).realize() + GlobalCounters.reset() + + st = time.perf_counter() + step(x) + Device[Device.DEFAULT].synchronize() + et = time.perf_counter() + + flops = GlobalCounters.global_ops / JITCNT + mem_used = GlobalCounters.mem_used # a little high with JITCNT > 1 fsr + mem = GlobalCounters.global_mem / JITCNT + if kernels is None: kernels = GlobalCounters.kernel_count // JITCNT + tm = (et-st) / JITCNT + if best_tm is None or tm < best_tm: best_tm = tm + print(f"\r{name:38s}: {best_tm * 1000:>9.2f} ms, {flops / 10**12 / best_tm:>6.2f} tflops, {mem / 10**9 / best_tm:>5.0f} GB/s, " + f"{mem_used / 10**9: 6.2f} GB used, {kernels:>5d} kernels") + return best_tm, flops, mem, kernels + + def test_layer1_1(self): self._est(*self._test_layer(*self._get_layer(0, 0)), 1) + def test_layer1_2(self): self._est(*self._test_layer(*self._get_layer(0, 1)), 2) + def test_layer2_1(self): self._est(*self._test_layer(*self._get_layer(1, 0)), 1) + def test_layer2_2(self): self._est(*self._test_layer(*self._get_layer(1, 1)), 3) + def test_layer3_1(self): self._est(*self._test_layer(*self._get_layer(2, 0)), 1) + def test_layer3_2(self): self._est(*self._test_layer(*self._get_layer(2, 1)), 5) + def test_layer4_1(self): self._est(*self._test_layer(*self._get_layer(3, 0)), 1) + def test_layer4_2(self): self._est(*self._test_layer(*self._get_layer(3, 1)), 2) + + est_tm, est_flops, est_mem, est_kernels = 0, 0, 0, 0 + + @classmethod + def _est(cls, tm, flops, mem, kernels, mult): + cls.est_tm += tm * mult + cls.est_flops += flops * mult + cls.est_mem += mem * mult + cls.est_kernels += kernels * mult + + @classmethod + def tearDownClass(cls): + print(f"\restimated step tm: {cls.est_tm * 1000.0:.2f} ms, {cls.est_flops / 10 ** 12 / cls.est_tm:.3f} tflops, " + f"{cls.est_mem / 10 ** 9 / cls.est_tm:.2f} GB/s, {cls.est_kernels} kernels") + + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_benchmark_schedule.py b/tinygrad_repo/test/external/external_benchmark_schedule.py new file mode 100644 index 000000000..2a47061e6 --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_schedule.py @@ -0,0 +1,62 @@ +from typing import List +from extra.models.resnet import ResNet50 +from tinygrad import Tensor, nn +from tinygrad.helpers import Profiling, Timing, getenv, BEAM, NOOPT, DEBUG, Context, ansilen +from tinygrad.uop.ops import Ops +from tinygrad.opt.kernel import Kernel +from tinygrad.opt.heuristic import hand_coded_optimizations +from tinygrad.codegen import get_rewrites_for_renderer, apply_rewrites, rewrites_for_linearizer +from tinygrad.opt.search import beam_search, bufs_from_lin +from tinygrad.uop.spec import type_verify + +if __name__ == "__main__": + mdl = ResNet50() + for p in nn.state.get_parameters(mdl): p.replace(Tensor.empty(p.shape)) + img = Tensor.empty(64, 3, 224, 224) + + PROFILE = getenv("PYPROFILE", 0) + FORWARD_ONLY = getenv("FORWARD_ONLY", 0) + SCHEDULE_ONLY = getenv("SCHEDULE_ONLY", 0) + LINEARIZE = bool(getenv("LINEARIZE", 1)) + + with Timing("all "): + with Timing("***** model tensor in "): + out = mdl(img) + + if not FORWARD_ONLY: + with Timing("***** model schedule in "): + with Profiling(PROFILE >= 3): + sched = out.schedule() + + if not SCHEDULE_ONLY: + asts = list({x.ast.key:x.ast for x in sched if x.ast.op is Ops.SINK}.values()) + if (restrict_kernel := getenv("RESTRICT_KERNEL", -1)) != -1: asts = asts[restrict_kernel:restrict_kernel+1] + kernels: List[Kernel] = [] + with Timing(f"***** model opts({len(asts):2d}) in "): + with Profiling(PROFILE >= 3): + for ast in asts: + k = Kernel(ast) + if BEAM: + with Context(DEBUG=max(2, DEBUG.value)): k = beam_search(k, bufs_from_lin(k), BEAM.value) + elif NOOPT: pass + else: k.apply_opts(hand_coded_optimizations(k)) + kernels.append(k) + + with Timing("***** model prep in "): + kernels = [(k, k.get_optimized_ast(), get_rewrites_for_renderer(k.opts, linearizer=False)) for k in kernels] + + with Profiling(PROFILE, fn="/tmp/rewrite.prof"): + with Timing("***** model rewrite in "): + rewritten_uops = [] + for i,(k,u,rewrites) in enumerate(kernels): + with Timing(f"rewrite {i:2d} {k.name}{' '*(50-ansilen(k.name))}", enabled=getenv("VERBOSE", 0)): + rewritten_uops.append(apply_rewrites(u, rewrites)) + + if LINEARIZE: + with Timing("***** model linearize in "): + uops_line = [] + for u in rewritten_uops: + uops_line.append(apply_rewrites(u, rewrites_for_linearizer)) + with Timing("***** model verify in "): + for u in uops_line: type_verify(u.arg.lst) + print(sum(len(u.arg.lst) for u in uops_line)) diff --git a/tinygrad_repo/test/external/external_benchmark_sdxl_softmax.py b/tinygrad_repo/test/external/external_benchmark_sdxl_softmax.py new file mode 100644 index 000000000..639d59e41 --- /dev/null +++ b/tinygrad_repo/test/external/external_benchmark_sdxl_softmax.py @@ -0,0 +1,27 @@ +from tinygrad import Tensor, dtypes, GlobalCounters + +if __name__ == "__main__": + t = Tensor.empty(81920, 4096, dtype=dtypes.half) + GlobalCounters.reset() + t.softmax(-1, dtype="half").realize() + GlobalCounters.reset() + t.softmax(-1, dtype="half", _single_kernel=True).realize() + + from tinygrad.opt.kernel import Kernel, Opt, OptOps + from tinygrad.helpers import get_single_element + GlobalCounters.reset() + si = get_single_element(t.softmax(-1, dtype="half", _single_kernel=True).schedule()) + k = Kernel(si.ast) + #k.apply_opt(Opt(OptOps.UPCAST, 0, 4)) + k.apply_opt(Opt(OptOps.UPCAST, 1, 4)) + k.apply_opt(Opt(OptOps.LOCAL, 1, 32)) + #k.apply_opt(Opt(OptOps.LOCAL, 0, 8)) + k.apply_opt(Opt(OptOps.UNROLL, 1, 4)) + k.apply_opt(Opt(OptOps.UNROLL, 0, 4)) + #k.apply_opt(Opt(OptOps.GROUP, 1, 256)) + #k.apply_opt(Opt(OptOps.GROUP, 0, 32)) + #k.apply_opt(Opt(OptOps.GROUP, 1, 32)) + #k.apply_opt(Opt(OptOps.GROUP, 0, 32)) + from tinygrad.engine.realize import CompiledRunner, ExecItem + run = CompiledRunner(prg:=k.to_program()) + ExecItem(run, si.bufs).run() diff --git a/tinygrad_repo/test/external/external_cl_half_max.py b/tinygrad_repo/test/external/external_cl_half_max.py new file mode 100644 index 000000000..7cd6b0c50 --- /dev/null +++ b/tinygrad_repo/test/external/external_cl_half_max.py @@ -0,0 +1,13 @@ +from tinygrad.runtime.ops_gpu import CLDevice, CLProgram, compile_cl + +if __name__ == "__main__": + dev = CLDevice() + lib = compile_cl(""" +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +__kernel void test(__global half *out, __global half *a, __global half *b) { + int gid = get_global_id(0); + out[gid] = max(a[gid], b[gid]); +} +""") + prg = CLProgram(dev, "test", lib) + diff --git a/tinygrad_repo/test/external/external_debug_metal_sd_conv.py b/tinygrad_repo/test/external/external_debug_metal_sd_conv.py new file mode 100644 index 000000000..6c2d24b5a --- /dev/null +++ b/tinygrad_repo/test/external/external_debug_metal_sd_conv.py @@ -0,0 +1,46 @@ +# ruff: noqa: E501 +from tinygrad.opt.kernel import Kernel, Opt, OptOps +from tinygrad.dtype import dtypes +from tinygrad.engine.realize import CompiledRunner +from tinygrad.opt.search import bufs_from_lin +from tinygrad.uop.ops import UOp, Ops +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.shape.view import View + +ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(), arg=0, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 1, 1280, 8, 8, 1, 1, 1), strides=(81920, 0, 64, 8, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.ADD, dtypes.half, arg=None, src=( + UOp(Ops.ADD, dtypes.half, arg=None, src=( + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(), arg=1, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 2, 1, 2560, 4, 10, 4, 10), strides=(0, 163840, 0, 64, 0, 8, 0, 1), offset=-9, mask=((0, 1), (0, 2), (0, 1), (0, 2560), (0, 4), (1, 9), (0, 4), (1, 9)), contiguous=False), View(shape=(2, 1, 1280, 8, 8, 2560, 3, 3), strides=(4096000, 0, 0, 40, 1, 1600, 440, 11), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(), arg=2, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 1, 1280, 8, 8, 2560, 3, 3), strides=(0, 0, 23040, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(), arg=3, src=()), + x17:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 1, 1280, 8, 8, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(), arg=4, src=()), + x17,)),)),)),)) +opts = [Opt(op=OptOps.UPCAST, axis=3, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UNROLL, axis=2, arg=0), Opt(op=OptOps.UNROLL, axis=1, arg=0), Opt(op=OptOps.LOCAL, axis=1, arg=8), Opt(op=OptOps.LOCAL, axis=2, arg=8), Opt(op=OptOps.LOCAL, axis=2, arg=2)] + +k = Kernel(ast) +k.apply_opts(opts) +bufs = bufs_from_lin(k) + +prg = CompiledRunner(k.to_program()) + +for i in range(10): + speed = prg(bufs, var_vals={}, wait=True) + print(f"kernel time: {speed*1e3:.2f} ms") + +# on M1 Max +# 11ms before block 9b0859d71780fef5cf3831e317f74e53f2483229 +# 15ms after block cbcc1c20eb09a1342f6581cfbb99632bade982a8 \ No newline at end of file diff --git a/tinygrad_repo/test/external/external_fuzz_am_interrupts.py b/tinygrad_repo/test/external/external_fuzz_am_interrupts.py new file mode 100644 index 000000000..2ed572428 --- /dev/null +++ b/tinygrad_repo/test/external/external_fuzz_am_interrupts.py @@ -0,0 +1,39 @@ +import subprocess +import random +import time +from concurrent.futures import ThreadPoolExecutor, as_completed + +def run_test(i, full_run=False): + print(f"\rRunning iteration {i}...", end=" ", flush=True) + + p = subprocess.Popen(['python3', 'test/test_tiny.py', 'TestTiny.test_plus'], stdout=subprocess.PIPE, stderr=subprocess.PIPE) + + if not full_run: + time.sleep(random.uniform(0, 1200) / 1000) + p.kill() + _, stderr = p.communicate() + else: + _, stderr = p.communicate() + + if full_run: + stderr_text = stderr.decode() + print(stderr_text) + assert "Ran 1 test in" in stderr_text and "OK" in stderr_text + +max_workers = 4 +with ThreadPoolExecutor(max_workers=max_workers) as executor: + futures = [] + for i in range(1000000): + if i % 100 == 0: + for future in as_completed(futures): + try: future.result() + except Exception as e: + print(f"\nError in iteration: {e}") + futures = [] + + run_test(i, True) + else: + future = executor.submit(run_test, i, False) + futures.append(future) + + if len(futures) > max_workers * 2: futures = [f for f in futures if not f.done()] \ No newline at end of file diff --git a/tinygrad_repo/test/external/external_fuzz_ampt.py b/tinygrad_repo/test/external/external_fuzz_ampt.py new file mode 100644 index 000000000..d35959937 --- /dev/null +++ b/tinygrad_repo/test/external/external_fuzz_ampt.py @@ -0,0 +1,109 @@ +import random +from typing import Optional +from tinygrad.helpers import round_up +from tinygrad.runtime.support.am.amdev import AMPageTableTraverseContext +from test.external.external_test_am import helper_read_entry_components, FakeAM + +class AMPTFuzzer: + def __init__(self, total_size): + self.total_size = total_size + self.alloc_payload = 0 + self.d = FakeAM() + + self.allocations: dict[int, tuple[int, int]] = {} # ptr -> (size, pattern) + + self.min_alloc_size = 0x1000 + self.max_alloc_size = int(total_size * 0.1) + self.alloc_probability = 0.7 + + def generate_pattern(self, ptr: int, size: int) -> int: return random.randint(0, 0xff) + + def fill_memory(self, va, size: int, pattern: int): + ctx = AMPageTableTraverseContext(self.d, self.d.mm.root_page_table, va.va_addr) + pages = list(ctx.next(size)) + + for _offset, _pt, _pte_idx, _n_ptes, _pte_covers in pages: + _vaddr = va.va_addr + _offset + + for i in range(_n_ptes): + pte = helper_read_entry_components(_pt.entries[_pte_idx + i]) + self.d.vram[pte['paddr']] = pattern # Mark this page + assert pte['valid'] == 1 + + # If page has contiguous fragment, all range should be this valid memory + frags_cnt = pte['fragment'] + contig_range = (1 << (frags_cnt + 12)) + start_vaddr = _vaddr & ~(contig_range - 1) + start_paddr = pte['paddr'] - (_vaddr - start_vaddr) + contig_ptes = contig_range // _pte_covers + assert contig_ptes > 0 + + ctx = AMPageTableTraverseContext(self.d, self.d.mm.root_page_table, start_vaddr) + frags_l = list(ctx.next(contig_range)) + for f_offset, f_pt, f_pte_idx, f_n_ptes, f_pte_covers in frags_l: + for j in range(f_n_ptes): + f_pte = helper_read_entry_components(f_pt.entries[f_pte_idx + j]) + assert f_pte['valid'] == 1 + assert f_pte['paddr'] == start_paddr+f_offset+j*f_pte_covers, f"paddr {f_pte['paddr']:#x} not {start_paddr+f_offset+j*f_pte_covers:#x}" + + _vaddr += _pte_covers + _offset += _pte_covers + + return pages + + def verify_memory(self, pages, pattern: int) -> bool: + for _offset, _pt, _pte_idx, _n_ptes, _pte_covers in pages: + for i in range(_n_ptes): + pte = helper_read_entry_components(_pt.entries[_pte_idx + i]) + if self.d.vram[pte['paddr']] != pattern: return False + if pte['valid'] == 0: return False + + return True + + def random_alloc(self) -> Optional[int]: + if self.total_size - self.alloc_payload < self.min_alloc_size: return None + + size = random.randint(self.min_alloc_size, min(self.max_alloc_size, self.total_size - self.alloc_payload)) + size = round_up(size, (2 << 20) if size > (4 << 20) else (4 << 10)) + + try: ptr = self.d.mm.valloc(size) + except MemoryError: + print(f"Failed to allocate {size} bytes. Payload size is {self.alloc_payload}, so fragmenation is {(size / self.total_size)*100.0:.2f}%") + return None + + pattern = self.generate_pattern(ptr, size) + pages = self.fill_memory(ptr, size, pattern) + self.allocations[ptr.va_addr] = (size, pattern, pages, ptr) + self.alloc_payload += size + print(f"Allocated {size} bytes at {ptr.va_addr:x}, pattern: {pattern:02x}") + return ptr + + def random_free(self) -> bool: + if not self.allocations: return False + + ptr = random.choice(list(self.allocations.keys())) + size, pattern, pages, vm = self.allocations[ptr] + + # Verify pattern before freeing + if not self.verify_memory(pages, pattern): + raise RuntimeError(f"Memory corruption detected at {vm.va_addr:x}!") + + print(f"Freeing {size} bytes at {vm.va_addr:x}, pattern verified: {pattern:02x}") + self.alloc_payload -= size + self.d.mm.vfree(vm) + del self.allocations[ptr] + return True + + def run(self): + for i in range(10000000): + if (random.random() < self.alloc_probability or not self.allocations): self.random_alloc() + else: self.random_free() + + print("\nCleaning up remaining allocations...") + while self.allocations: self.random_free() + + print("Fuzzing completed successfully!") + +if __name__ == "__main__": + fuzzer = AMPTFuzzer(1 << 30) + fuzzer.run() diff --git a/tinygrad_repo/test/external/external_fuzz_hcq_signals.py b/tinygrad_repo/test/external/external_fuzz_hcq_signals.py new file mode 100644 index 000000000..cc667c79f --- /dev/null +++ b/tinygrad_repo/test/external/external_fuzz_hcq_signals.py @@ -0,0 +1,31 @@ +import random +from tinygrad import Device +from tinygrad.helpers import getenv, DEBUG + +def main(): + seed = getenv("SEED", 1337) + n_gpus = getenv("GPUS", 3) + iters = getenv("ITERS", 10000000) + only_compute = bool(getenv("ONLY_COMPUTE", 0)) + + print(f"{n_gpus} GPUs for {iters} iterations, {only_compute=}, seed {seed}") + devs = tuple([Device[f"{Device.DEFAULT}:{x}"] for x in range(n_gpus)]) + + for i in range(iters): + dev = random.choice(devs) + q_t = random.choice([dev.hw_copy_queue_t, dev.hw_compute_queue_t] if not only_compute else [dev.hw_compute_queue_t]) + + deps_sigs = random.randint(0, len(devs)) + wait_devs = random.sample(devs, deps_sigs) + + q = q_t() + for d in wait_devs: q.wait(d.timeline_signal, d.timeline_value - 1) + q.wait(dev.timeline_signal, dev.timeline_value - 1).signal(dev.timeline_signal, dev.timeline_value).submit(dev) + dev.timeline_value += 1 + + if sync:=random.randint(0, 10) < 3: dev.synchronize() + if DEBUG >= 2: print(f"{i}: {q_t} {dev.device_id} timeline {dev.timeline_value}, wait for {[d.device_id for d in wait_devs]}, {sync=}") + elif i % 100 == 0: print(f"\rCompleted {i} iterations", end='') + +if __name__ == "__main__": + main() diff --git a/tinygrad_repo/test/external/external_fuzz_tlsf.py b/tinygrad_repo/test/external/external_fuzz_tlsf.py new file mode 100644 index 000000000..029c9bee9 --- /dev/null +++ b/tinygrad_repo/test/external/external_fuzz_tlsf.py @@ -0,0 +1,81 @@ +import random +from typing import Dict, Optional +from tinygrad.helpers import getenv +from tinygrad.runtime.support.memory import TLSFAllocator + +class AllocatorFuzzer: + def __init__(self, total_size): + self.total_size = total_size + self.alloc_payload = 0 + self.mv = memoryview(bytearray(total_size)) + self.alloctor = TLSFAllocator(total_size, block_size=16) + + self.allocations: Dict[int, tuple[int, int]] = {} # ptr -> (size, pattern) + + self.min_alloc_size = 16 + self.max_alloc_size = int(total_size * 0.3) + self.alloc_probability = 0.7 + + def generate_pattern(self, ptr: int, size: int) -> int: return (ptr * 31 + size * 17) & 0xFF + + def fill_memory(self, ptr: int, size: int, pattern: int): + for i in range(min(size, 32)): + self.mv[ptr + i] = pattern + self.mv[ptr + (size - 1 - i)] = pattern + + def verify_memory(self, ptr: int, size: int, pattern: int) -> bool: + for i in range(min(size, 32)): + assert self.mv[ptr + i] == pattern + assert self.mv[ptr + (size - 1 - i)] == pattern + return True + + def random_alloc(self) -> Optional[int]: + if self.total_size - self.alloc_payload < self.min_alloc_size: return None + + size = random.randint(self.min_alloc_size, min(self.max_alloc_size, self.total_size - self.alloc_payload)) + + try: + ptr = self.alloctor.alloc(size) + except MemoryError: + print(f"Failed to allocate {size} bytes. Payload size is {self.alloc_payload}, so fragmenation is {(size / self.total_size)*100.0:.2f}%") + return None + + pattern = self.generate_pattern(ptr, size) + self.fill_memory(ptr, size, pattern) + self.allocations[ptr] = (size, pattern) + self.alloc_payload += size + print(f"Allocated {size} bytes at {ptr:x}, pattern: {pattern:02x}") + return ptr + + def random_free(self) -> bool: + if not self.allocations: return False + + ptr = random.choice(list(self.allocations.keys())) + size, pattern = self.allocations[ptr] + + # Verify pattern before freeing + if not self.verify_memory(ptr, size, pattern): + raise RuntimeError(f"Memory corruption detected at {ptr:x}!") + + print(f"Freeing {size} bytes at {ptr:x}, pattern verified: {pattern:02x}") + self.alloc_payload -= size + self.alloctor.free(ptr) + del self.allocations[ptr] + return True + + def run(self): + for i in range(getenv("ITERS", 100000)): + if (random.random() < self.alloc_probability or not self.allocations): self.random_alloc() + else: self.random_free() + + print("\nCleaning up remaining allocations...") + while self.allocations: self.random_free() + + print("Fuzzing completed successfully!") + +if __name__ == "__main__": + SEED = getenv("SEED", 42) + random.seed(SEED) + + fuzzer = AllocatorFuzzer(1 << 30) + fuzzer.run() diff --git a/tinygrad_repo/test/external/external_gpu_fail_osx.py b/tinygrad_repo/test/external/external_gpu_fail_osx.py new file mode 100644 index 000000000..b11b695e3 --- /dev/null +++ b/tinygrad_repo/test/external/external_gpu_fail_osx.py @@ -0,0 +1,16 @@ +# ugh, OS X OpenCL doesn't support half +from tinygrad.runtime.ops_gpu import CLDevice, CLProgram, CLCompiler + +src = """#pragma OPENCL EXTENSION cl_khr_fp16 : enable +__kernel void max_half(__global half* data0, const __global half* data1) { + int gidx0 = get_group_id(0); + data0[gidx0] = max(data1[gidx0], (half)0.0); +}""" + +if __name__ == "__main__": + dev = CLDevice() + print("created device") + lib = CLCompiler(dev, "test").compile(src) + print("created lib", len(lib)) + prg = CLProgram(dev, "max_half", lib) + print("created prg") \ No newline at end of file diff --git a/tinygrad_repo/test/external/external_hip_compiler_bug.py b/tinygrad_repo/test/external/external_hip_compiler_bug.py new file mode 100644 index 000000000..9dfcf0126 --- /dev/null +++ b/tinygrad_repo/test/external/external_hip_compiler_bug.py @@ -0,0 +1,225 @@ +# [, , ] +from tinygrad import Device, dtypes +from tinygrad.device import Buffer, CompiledRunner + +import ctypes +import gpuctypes.hip as hip +from tinygrad.helpers import to_char_p_p, init_c_var +def get_bytes(arg, get_sz, get_str, check) -> bytes: return (sz := init_c_var(ctypes.c_size_t(), lambda x: check(get_sz(arg, ctypes.byref(x)))), ctypes.string_at(init_c_var(ctypes.create_string_buffer(sz.value), lambda x: check(get_str(arg, x))), size=sz.value))[1] # noqa: E501 +def check(status): + if status != 0: raise RuntimeError(f"HIP Error {status}, {ctypes.string_at(hip.hipGetErrorString(status)).decode()}") +def compile_hip(prg:str, arch="gfx1100") -> bytes: + check(hip.hiprtcCreateProgram(ctypes.byref(prog := hip.hiprtcProgram()), prg.encode(), "".encode(), 0, None, None)) + compile_options = [f'--offload-arch={arch}', '-I/opt/rocm/include'] + status = hip.hiprtcCompileProgram(prog, len(compile_options), to_char_p_p([o.encode() for o in compile_options])) + if status != 0: raise RuntimeError(f"compile failed: {get_bytes(prog, hip.hiprtcGetProgramLogSize, hip.hiprtcGetProgramLog, check).decode()}") + return get_bytes(prog, hip.hiprtcGetCodeSize, hip.hiprtcGetCode, check) + +prefix = """ +typedef long unsigned int size_t; +extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_id(unsigned int); +extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_group_id(unsigned int); +extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_size(unsigned int); +typedef float float2 __attribute__((ext_vector_type(2))); +static inline __attribute__((device)) float2 make_float2(float x, float y) { return {x, y}; } +""" + +code = """ +extern "C" __attribute__((global))void r_2_8_7_7_4_8_3_7_7_4_4_2_2(float* data0, const float* data1, const float* data2) { + int gidx0 = __ockl_get_group_id(2); /* 2 */ + int gidx1 = __ockl_get_group_id(1); /* 8 */ + int gidx2 = __ockl_get_group_id(0); /* 49 */ + int lidx4 = __ockl_get_local_id(1); /* 4 */ + int lidx5 = __ockl_get_local_id(0); /* 8 */ + float2 acc0 = make_float2(0.0f,0.0f); + float2 acc1 = make_float2(0.0f,0.0f); + float2 acc2 = make_float2(0.0f,0.0f); + float2 acc3 = make_float2(0.0f,0.0f); + float2 acc4 = make_float2(0.0f,0.0f); + float2 acc5 = make_float2(0.0f,0.0f); + float2 acc6 = make_float2(0.0f,0.0f); + float2 acc7 = make_float2(0.0f,0.0f); + float2 acc8 = make_float2(0.0f,0.0f); + float2 acc9 = make_float2(0.0f,0.0f); + float2 acc10 = make_float2(0.0f,0.0f); + float2 acc11 = make_float2(0.0f,0.0f); + float2 acc12 = make_float2(0.0f,0.0f); + float2 acc13 = make_float2(0.0f,0.0f); + float2 acc14 = make_float2(0.0f,0.0f); + float2 acc15 = make_float2(0.0f,0.0f); + float2 acc16 = make_float2(0.0f,0.0f); + float2 acc17 = make_float2(0.0f,0.0f); + float2 acc18 = make_float2(0.0f,0.0f); + float2 acc19 = make_float2(0.0f,0.0f); + float2 acc20 = make_float2(0.0f,0.0f); + float2 acc21 = make_float2(0.0f,0.0f); + float2 acc22 = make_float2(0.0f,0.0f); + float2 acc23 = make_float2(0.0f,0.0f); + float2 acc24 = make_float2(0.0f,0.0f); + float2 acc25 = make_float2(0.0f,0.0f); + float2 acc26 = make_float2(0.0f,0.0f); + float2 acc27 = make_float2(0.0f,0.0f); + float2 acc28 = make_float2(0.0f,0.0f); + float2 acc29 = make_float2(0.0f,0.0f); + float2 acc30 = make_float2(0.0f,0.0f); + float2 acc31 = make_float2(0.0f,0.0f); + int alu0 = (gidx2/7); + int alu1 = (gidx2%7); + int alu2 = (alu1*32); + int alu3 = (lidx5*4); + int alu4 = ((gidx0*802816)+(gidx1*100352)+(alu0*1792)+(alu1*16)+(lidx4*448)+(lidx5*2)); + for (int ridx0 = 0; ridx0 < 3; ridx0++) { + for (int ridx1 = 0; ridx1 < 7; ridx1++) { + int alu5 = ((alu0*(-32))+(lidx4*(-8))+(ridx1*(-1))); + bool alu6 = (alu5<(-2)); + bool alu7 = (alu5<0); + bool alu8 = (((alu0*32)+(lidx4*8)+ridx1)<221); + for (int ridx2 = 0; ridx2 < 7; ridx2++) { + int alu9 = ((gidx0*150528)+(ridx0*50176)+(alu0*7168)+(lidx4*1792)+(ridx1*224)+alu2+alu3+ridx2); + int alu10 = ((alu1*(-32))+(lidx5*(-4))+(ridx2*(-1))); + bool alu11 = (alu10<(-2)); + float val0 = 0.0f; + if ((alu6*alu11)) { val0 = data1[alu9+(-675)]; } + float val1 = 0.0f; + if ((alu7*alu11)) { val1 = data1[alu9+(-227)]; } + float val2 = 0.0f; + if (alu11) { val2 = data1[alu9+221]; } + float val3 = 0.0f; + if ((alu8*alu11)) { val3 = data1[alu9+669]; } + bool alu12 = (alu10<0); + bool alu13 = ((alu2+alu3+ridx2)<225); + float val4 = 0.0f; + if ((alu6*alu12*alu13)) { val4 = data1[alu9+(-673)]; } + float val5 = 0.0f; + if ((alu7*alu12*alu13)) { val5 = data1[alu9+(-225)]; } + float val6 = 0.0f; + if ((alu12*alu13)) { val6 = data1[alu9+223]; } + float val7 = 0.0f; + if ((alu8*alu12*alu13)) { val7 = data1[alu9+671]; } + int alu14 = ((gidx1*1176)+(ridx0*49)+(ridx1*7)+ridx2); + float val8 = data2[alu14]; + float val9 = data2[alu14+147]; + float val10 = data2[alu14+294]; + float val11 = data2[alu14+441]; + float val12 = data2[alu14+588]; + float val13 = data2[alu14+735]; + float val14 = data2[alu14+882]; + float val15 = data2[alu14+1029]; + (acc0).x = ((val0*val8)+(acc0).x); + (acc1).x = ((val0*val9)+(acc1).x); + (acc2).x = ((val0*val10)+(acc2).x); + (acc3).x = ((val0*val11)+(acc3).x); + (acc4).x = ((val1*val8)+(acc4).x); + (acc5).x = ((val1*val9)+(acc5).x); + (acc6).x = ((val1*val10)+(acc6).x); + (acc7).x = ((val1*val11)+(acc7).x); + (acc8).x = ((val2*val8)+(acc8).x); + (acc9).x = ((val2*val9)+(acc9).x); + (acc10).x = ((val2*val10)+(acc10).x); + (acc11).x = ((val2*val11)+(acc11).x); + (acc12).x = ((val3*val8)+(acc12).x); + (acc13).x = ((val3*val9)+(acc13).x); + (acc14).x = ((val3*val10)+(acc14).x); + (acc15).x = ((val3*val11)+(acc15).x); + (acc16).x = ((val0*val12)+(acc16).x); + (acc17).x = ((val0*val13)+(acc17).x); + (acc18).x = ((val0*val14)+(acc18).x); + (acc19).x = ((val0*val15)+(acc19).x); + (acc20).x = ((val1*val12)+(acc20).x); + (acc21).x = ((val1*val13)+(acc21).x); + (acc22).x = ((val1*val14)+(acc22).x); + (acc23).x = ((val1*val15)+(acc23).x); + (acc24).x = ((val2*val12)+(acc24).x); + (acc25).x = ((val2*val13)+(acc25).x); + (acc26).x = ((val2*val14)+(acc26).x); + (acc27).x = ((val2*val15)+(acc27).x); + (acc28).x = ((val3*val12)+(acc28).x); + (acc29).x = ((val3*val13)+(acc29).x); + (acc30).x = ((val3*val14)+(acc30).x); + (acc31).x = ((val3*val15)+(acc31).x); + (acc0).y = ((val4*val8)+(acc0).y); + (acc1).y = ((val4*val9)+(acc1).y); + (acc2).y = ((val4*val10)+(acc2).y); + (acc3).y = ((val4*val11)+(acc3).y); + (acc4).y = ((val5*val8)+(acc4).y); + (acc5).y = ((val5*val9)+(acc5).y); + (acc6).y = ((val5*val10)+(acc6).y); + (acc7).y = ((val5*val11)+(acc7).y); + (acc8).y = ((val6*val8)+(acc8).y); + (acc9).y = ((val6*val9)+(acc9).y); + (acc10).y = ((val6*val10)+(acc10).y); + (acc11).y = ((val6*val11)+(acc11).y); + (acc12).y = ((val7*val8)+(acc12).y); + (acc13).y = ((val7*val9)+(acc13).y); + (acc14).y = ((val7*val10)+(acc14).y); + (acc15).y = ((val7*val11)+(acc15).y); + (acc16).y = ((val4*val12)+(acc16).y); + (acc17).y = ((val4*val13)+(acc17).y); + (acc18).y = ((val4*val14)+(acc18).y); + (acc19).y = ((val4*val15)+(acc19).y); + (acc20).y = ((val5*val12)+(acc20).y); + (acc21).y = ((val5*val13)+(acc21).y); + (acc22).y = ((val5*val14)+(acc22).y); + (acc23).y = ((val5*val15)+(acc23).y); + (acc24).y = ((val6*val12)+(acc24).y); + (acc25).y = ((val6*val13)+(acc25).y); + (acc26).y = ((val6*val14)+(acc26).y); + (acc27).y = ((val6*val15)+(acc27).y); + (acc28).y = ((val7*val12)+(acc28).y); + (acc29).y = ((val7*val13)+(acc29).y); + (acc30).y = ((val7*val14)+(acc30).y); + (acc31).y = ((val7*val15)+(acc31).y); + } + } + } + *((float2*)(data0+alu4)) = acc0; + *((float2*)(data0+alu4+12544)) = acc1; + *((float2*)(data0+alu4+25088)) = acc2; + *((float2*)(data0+alu4+37632)) = acc3; + *((float2*)(data0+alu4+112)) = acc4; + *((float2*)(data0+alu4+12656)) = acc5; + *((float2*)(data0+alu4+25200)) = acc6; + *((float2*)(data0+alu4+37744)) = acc7; + *((float2*)(data0+alu4+224)) = acc8; + *((float2*)(data0+alu4+12768)) = acc9; + *((float2*)(data0+alu4+25312)) = acc10; + *((float2*)(data0+alu4+37856)) = acc11; + *((float2*)(data0+alu4+336)) = acc12; + *((float2*)(data0+alu4+12880)) = acc13; + *((float2*)(data0+alu4+25424)) = acc14; + *((float2*)(data0+alu4+37968)) = acc15; + *((float2*)(data0+alu4+50176)) = acc16; + *((float2*)(data0+alu4+62720)) = acc17; + *((float2*)(data0+alu4+75264)) = acc18; + *((float2*)(data0+alu4+87808)) = acc19; + *((float2*)(data0+alu4+50288)) = acc20; + *((float2*)(data0+alu4+62832)) = acc21; + *((float2*)(data0+alu4+75376)) = acc22; + *((float2*)(data0+alu4+87920)) = acc23; + *((float2*)(data0+alu4+50400)) = acc24; + *((float2*)(data0+alu4+62944)) = acc25; + *((float2*)(data0+alu4+75488)) = acc26; + *((float2*)(data0+alu4+88032)) = acc27; + *((float2*)(data0+alu4+50512)) = acc28; + *((float2*)(data0+alu4+63056)) = acc29; + *((float2*)(data0+alu4+75600)) = acc30; + *((float2*)(data0+alu4+88144)) = acc31; +} +""" + +dev = "HIP" +lib = Device[dev].compiler.compile(prefix+code) +#lib = compile_hip(code) +b0 = Buffer(dev, 1605632, dtypes.float) +b1 = Buffer(dev, 301506, dtypes.float) +b2 = Buffer(dev, 9408, dtypes.float) +print(hex(b0._buf.value), hex(b0._buf.value+1605632*4)) +print(hex(b1._buf.value)) +print(hex(b2._buf.value)) +#prg = CompiledRunner("r_2_8_7_7_4_8_3_7_7_4_4_2_2", "", dev, [7, 1, 1], [8, 4, 1], precompiled=lib) +prg = CompiledRunner("r_2_8_7_7_4_8_3_7_7_4_4_2_2", "", dev, [49, 8, 2], [8, 4, 1], precompiled=lib) +print("compiled") +prg([b0, b1, b2], {}) +print("ran") +Device[dev].synchronize() +print("sync") diff --git a/tinygrad_repo/test/external/external_jit_failure.py b/tinygrad_repo/test/external/external_jit_failure.py new file mode 100644 index 000000000..8fc9ad937 --- /dev/null +++ b/tinygrad_repo/test/external/external_jit_failure.py @@ -0,0 +1,17 @@ +from tinygrad import Tensor, TinyJit, Device +import numpy as np + +GPUS = 4 +N = 128 +ds = tuple([Device.canonicalize(f"{Device.DEFAULT}:{i}") for i in range(GPUS)]) +t = Tensor.rand(N, N, N).shard(ds, 0) +n = t.numpy() + +@TinyJit +def allreduce(t:Tensor) -> Tensor: + return t.sum(0) #.realize() + +for i in range(10): + print(i) + tn = allreduce(t).numpy() + np.testing.assert_allclose(tn, n.sum(0), atol=1e-4, rtol=1e-4) diff --git a/tinygrad_repo/test/external/external_metal_compile_fail.py b/tinygrad_repo/test/external/external_metal_compile_fail.py new file mode 100644 index 000000000..d6e2bf982 --- /dev/null +++ b/tinygrad_repo/test/external/external_metal_compile_fail.py @@ -0,0 +1,230 @@ +# AssertionError: Error Domain=AGXMetalG15X_B0 Code=3 "Compiler encountered an internal error" + +src = """ +#include +using namespace metal; +kernel void r_64_32_8_16_4_6_6_4(device float* data0, const device float* data1, + uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]) { + int gidx0 = gid.x; /* 64 */ + int lidx2 = lid.x; /* 8 */ + int gidx1 = gid.y; /* 32 */ + int lidx3 = lid.y; /* 16 */ + int alu0 = ((gidx0*4096)+(gidx1*16)+(lidx2*512)+lidx3); + int alu1 = ((gidx0*147456)+(gidx1*576)+(lidx2*18432)+(lidx3*36)); + float acc0 = 0.0f; + float acc1 = 0.0f; + float acc2 = 0.0f; + float acc3 = 0.0f; + float acc4 = 0.0f; + float acc5 = 0.0f; + float acc6 = 0.0f; + float acc7 = 0.0f; + float acc8 = 0.0f; + float acc9 = 0.0f; + float acc10 = 0.0f; + float acc11 = 0.0f; + float acc12 = 0.0f; + float acc13 = 0.0f; + float acc14 = 0.0f; + float acc15 = 0.0f; + float acc16 = 0.0f; + float acc17 = 0.0f; + float acc18 = 0.0f; + float acc19 = 0.0f; + float acc20 = 0.0f; + float acc21 = 0.0f; + float acc22 = 0.0f; + float acc23 = 0.0f; + float acc24 = 0.0f; + float acc25 = 0.0f; + float acc26 = 0.0f; + float acc27 = 0.0f; + float acc28 = 0.0f; + float acc29 = 0.0f; + float acc30 = 0.0f; + float acc31 = 0.0f; + float acc32 = 0.0f; + float acc33 = 0.0f; + float acc34 = 0.0f; + float acc35 = 0.0f; + for (int ridx0 = 0; ridx0 < 4; ridx0++) { + int alu2 = (ridx0*6); + int alu3 = (alu2+1); + int alu4 = (alu2+2); + int alu5 = (alu2+3); + int alu6 = (alu2+4); + int alu7 = (alu2+5); + int alu8 = (alu2%7); + int alu9 = ((alu8+1)%7); + int alu10 = ((alu8+2)%7); + int alu11 = ((alu8+3)%7); + int alu12 = ((alu8+4)%7); + int alu13 = ((alu8+5)%7); + int alu14 = ((((alu0+(alu3/21))%262144)*144)+(((alu3/7)%3)*3)+(alu9*36)); + int alu15 = ((((alu0+(alu4/21))%262144)*144)+(((alu4/7)%3)*3)+(alu10*36)); + int alu16 = ((((alu0+(alu5/21))%262144)*144)+(((alu5/7)%3)*3)+(alu11*36)); + int alu17 = ((((alu0+(alu6/21))%262144)*144)+(((alu6/7)%3)*3)+(alu12*36)); + int alu18 = ((((alu0+(alu7/21))%262144)*144)+(((alu7/7)%3)*3)+(alu13*36)); + int alu19 = (alu8%7); + int alu20 = ((((alu0+(alu2/21))%262144)*144)+(((alu2/7)%3)*3)+(alu19*36)); + bool alu21 = ((alu2<16)&(alu13<4)); + bool alu22 = ((alu2<17)&(alu12<4)); + bool alu23 = ((alu2<18)&(alu11<4)); + bool alu24 = ((alu2<19)&(alu10<4)); + bool alu25 = ((alu2<20)&(alu9<4)); + bool alu26 = ((alu2<21)&(alu19<4)); + float val0 = (alu25?*(data1+alu14+1):0.0f); + float val1 = (alu25?*(data1+alu14+2):0.0f); + float val2 = (alu25?*(data1+alu14+9):0.0f); + float val3 = (alu25?*(data1+alu14+10):0.0f); + float val4 = (alu25?*(data1+alu14+11):0.0f); + float val5 = (alu25?*(data1+alu14+18):0.0f); + float val6 = (alu25?*(data1+alu14+19):0.0f); + float val7 = (alu25?*(data1+alu14+20):0.0f); + float val8 = (alu25?*(data1+alu14+27):0.0f); + float val9 = (alu25?*(data1+alu14+28):0.0f); + float val10 = (alu25?*(data1+alu14+29):0.0f); + float val11 = (alu24?*(data1+alu15+1):0.0f); + float val12 = (alu24?*(data1+alu15+2):0.0f); + float val13 = (alu24?*(data1+alu15+9):0.0f); + float val14 = (alu24?*(data1+alu15+10):0.0f); + float val15 = (alu24?*(data1+alu15+11):0.0f); + float val16 = (alu24?*(data1+alu15+18):0.0f); + float val17 = (alu24?*(data1+alu15+19):0.0f); + float val18 = (alu24?*(data1+alu15+20):0.0f); + float val19 = (alu24?*(data1+alu15+27):0.0f); + float val20 = (alu24?*(data1+alu15+28):0.0f); + float val21 = (alu24?*(data1+alu15+29):0.0f); + float val22 = (alu23?*(data1+alu16+1):0.0f); + float val23 = (alu23?*(data1+alu16+2):0.0f); + float val24 = (alu23?*(data1+alu16+9):0.0f); + float val25 = (alu23?*(data1+alu16+10):0.0f); + float val26 = (alu23?*(data1+alu16+11):0.0f); + float val27 = (alu23?*(data1+alu16+18):0.0f); + float val28 = (alu23?*(data1+alu16+19):0.0f); + float val29 = (alu23?*(data1+alu16+20):0.0f); + float val30 = (alu23?*(data1+alu16+27):0.0f); + float val31 = (alu23?*(data1+alu16+28):0.0f); + float val32 = (alu23?*(data1+alu16+29):0.0f); + float val33 = (alu22?*(data1+alu17+1):0.0f); + float val34 = (alu22?*(data1+alu17+2):0.0f); + float val35 = (alu22?*(data1+alu17+9):0.0f); + float val36 = (alu22?*(data1+alu17+10):0.0f); + float val37 = (alu22?*(data1+alu17+11):0.0f); + float val38 = (alu22?*(data1+alu17+18):0.0f); + float val39 = (alu22?*(data1+alu17+19):0.0f); + float val40 = (alu22?*(data1+alu17+20):0.0f); + float val41 = (alu22?*(data1+alu17+27):0.0f); + float val42 = (alu22?*(data1+alu17+28):0.0f); + float val43 = (alu22?*(data1+alu17+29):0.0f); + float val44 = (alu21?*(data1+alu18+1):0.0f); + float val45 = (alu21?*(data1+alu18+2):0.0f); + float val46 = (alu21?*(data1+alu18+9):0.0f); + float val47 = (alu21?*(data1+alu18+10):0.0f); + float val48 = (alu21?*(data1+alu18+11):0.0f); + float val49 = (alu21?*(data1+alu18+18):0.0f); + float val50 = (alu21?*(data1+alu18+19):0.0f); + float val51 = (alu21?*(data1+alu18+20):0.0f); + float val52 = (alu21?*(data1+alu18+27):0.0f); + float val53 = (alu21?*(data1+alu18+28):0.0f); + float val54 = (alu21?*(data1+alu18+29):0.0f); + float val55 = (alu26?*(data1+alu20+1):0.0f); + float val56 = (alu26?*(data1+alu20+2):0.0f); + float val57 = (alu26?*(data1+alu20+9):0.0f); + float val58 = (alu26?*(data1+alu20+10):0.0f); + float val59 = (alu26?*(data1+alu20+11):0.0f); + float val60 = (alu26?*(data1+alu20+18):0.0f); + float val61 = (alu26?*(data1+alu20+19):0.0f); + float val62 = (alu26?*(data1+alu20+20):0.0f); + float val63 = (alu26?*(data1+alu20+27):0.0f); + float val64 = (alu26?*(data1+alu20+28):0.0f); + float val65 = (alu26?*(data1+alu20+29):0.0f); + float val66 = (alu25?*(data1+alu14):0.0f); + float val67 = (alu24?*(data1+alu15):0.0f); + float val68 = (alu23?*(data1+alu16):0.0f); + float val69 = (alu22?*(data1+alu17):0.0f); + float val70 = (alu21?*(data1+alu18):0.0f); + float val71 = (alu26?*(data1+alu20):0.0f); + acc0 = (acc0+val71); + acc1 = (acc1+val66); + acc2 = (acc2+val67); + acc3 = (acc3+val68); + acc4 = (acc4+val69); + acc5 = (acc5+val70); + acc6 = (acc6+val57+val55); + acc7 = (acc7+val2+val0); + acc8 = (acc8+val13+val11); + acc9 = (acc9+val24+val22); + acc10 = (acc10+val35+val33); + acc11 = (acc11+val46+val44); + acc12 = (acc12+val60+val58+val56); + acc13 = (acc13+val5+val3+val1); + acc14 = (acc14+val16+val14+val12); + acc15 = (acc15+val27+val25+val23); + acc16 = (acc16+val38+val36+val34); + acc17 = (acc17+val49+val47+val45); + acc18 = (acc18+val63+val61+val59); + acc19 = (acc19+val8+val6+val4); + acc20 = (acc20+val19+val17+val15); + acc21 = (acc21+val30+val28+val26); + acc22 = (acc22+val41+val39+val37); + acc23 = (acc23+val52+val50+val48); + acc24 = (acc24+val64+val62); + acc25 = (acc25+val9+val7); + acc26 = (acc26+val20+val18); + acc27 = (acc27+val31+val29); + acc28 = (acc28+val42+val40); + acc29 = (acc29+val53+val51); + acc30 = (acc30+val65); + acc31 = (acc31+val10); + acc32 = (acc32+val21); + acc33 = (acc33+val32); + acc34 = (acc34+val43); + acc35 = (acc35+val54); + } + *(data0+alu1+1) = acc6; + *(data0+alu1+2) = acc12; + *(data0+alu1+3) = acc18; + *(data0+alu1+4) = acc24; + *(data0+alu1+5) = acc30; + *(data0+alu1+6) = acc1; + *(data0+alu1+7) = acc7; + *(data0+alu1+8) = acc13; + *(data0+alu1+9) = acc19; + *(data0+alu1+10) = acc25; + *(data0+alu1+11) = acc31; + *(data0+alu1+12) = acc2; + *(data0+alu1+13) = acc8; + *(data0+alu1+14) = acc14; + *(data0+alu1+15) = acc20; + *(data0+alu1+16) = acc26; + *(data0+alu1+17) = acc32; + *(data0+alu1+18) = acc3; + *(data0+alu1+19) = acc9; + *(data0+alu1+20) = acc15; + *(data0+alu1+21) = acc21; + *(data0+alu1+22) = acc27; + *(data0+alu1+23) = acc33; + *(data0+alu1+24) = acc4; + *(data0+alu1+25) = acc10; + *(data0+alu1+26) = acc16; + *(data0+alu1+27) = acc22; + *(data0+alu1+28) = acc28; + *(data0+alu1+29) = acc34; + *(data0+alu1+30) = acc5; + *(data0+alu1+31) = acc11; + *(data0+alu1+32) = acc17; + *(data0+alu1+33) = acc23; + *(data0+alu1+34) = acc29; + *(data0+alu1+35) = acc35; + *(data0+alu1) = acc0; +} +""" + +from tinygrad.runtime.ops_metal import MetalDevice, MetalCompiler, MetalProgram + +if __name__ == "__main__": + dev = MetalDevice("METAL") + lib = MetalCompiler().compile(src) + prg = MetalProgram(dev, "r_64_32_8_16_4_6_6_4", lib) + diff --git a/tinygrad_repo/test/external/external_model_benchmark.py b/tinygrad_repo/test/external/external_model_benchmark.py new file mode 100644 index 000000000..838089efe --- /dev/null +++ b/tinygrad_repo/test/external/external_model_benchmark.py @@ -0,0 +1,135 @@ +import csv, pathlib, time +import numpy as np +import torch +torch.set_num_threads(1) +from onnx.helper import tensor_dtype_to_np_dtype +import onnxruntime as ort +from onnx2torch import convert +from tinygrad.frontend.onnx import OnnxRunner, onnx_load +from tinygrad.helpers import OSX, DEBUG, fetch, getenv +from tinygrad import Tensor, Device + +MODELS = { + "resnet50": "https://github.com/onnx/models/raw/main/validated/vision/classification/resnet/model/resnet50-caffe2-v1-9.onnx", + "openpilot": "https://github.com/commaai/openpilot/raw/v0.9.4/selfdrive/modeld/models/supercombo.onnx", + "efficientnet": "https://github.com/onnx/models/raw/main/validated/vision/classification/efficientnet-lite4/model/efficientnet-lite4-11.onnx", + "shufflenet": "https://github.com/onnx/models/raw/main/validated/vision/classification/shufflenet/model/shufflenet-9.onnx", + # TODO: precision issue + # "commavq": "https://huggingface.co/commaai/commavq-gpt2m/resolve/main/gpt2m.onnx", + "dm": "https://github.com/commaai/openpilot/raw/ba7f840a06dbc8ae3c45b3b4976c88a21895aed0/selfdrive/modeld/models/dmonitoring_model.onnx", + + # broken in torch MPS + # "zfnet": "https://github.com/onnx/models/raw/main/archive/vision/classification/zfnet-512/model/zfnet512-9.onnx", + # TypeError: BatchNormalization() got an unexpected keyword argument 'is_test' + # "densenet": "https://github.com/onnx/models/raw/main/archive/vision/classification/densenet-121/model/densenet-3.onnx", + # AssertionError: only onnx version >= 10 supported for slice + # "bert": "https://github.com/onnx/models/raw/main/archive/text/machine_comprehension/bert-squad/model/bertsquad-8.onnx", + # really slow + # "resnet18": "https://github.com/onnx/models/raw/main/archive/vision/classification/resnet/model/resnet18-v2-7.onnx", +} + +CSV = {} +open_csv = None + +def benchmark(mnm, nm, fxn): + tms = [] + for _ in range(3): + st = time.perf_counter_ns() + ret = fxn() + tms.append(time.perf_counter_ns() - st) + print(f"{mnm:15s} {nm:25s} {min(tms)*1e-6:7.2f} ms") + CSV[nm] = min(tms)*1e-6 + return min(tms), ret + +#BASE = pathlib.Path(__file__).parents[2] / "weights" / "onnx" +BASE = pathlib.Path("/tmp/onnx") +def benchmark_model(m, devices, validate_outs=False): + torch.manual_seed(1) + global open_csv, CSV + CSV = {"model": m} + + fn = fetch(MODELS[m]) + onnx_model = onnx_load(fn) + output_names = [out.name for out in onnx_model.graph.output] + excluded = {inp.name for inp in onnx_model.graph.initializer} + input_shapes = {inp.name:tuple(x.dim_value if hasattr(x, "dim_value") and x.dim_value != 0 else 1 for x in inp.type.tensor_type.shape.dim) for inp in onnx_model.graph.input if inp.name not in excluded} # noqa: E501 + input_types = {inp.name: tensor_dtype_to_np_dtype(inp.type.tensor_type.elem_type) for inp in onnx_model.graph.input if inp.name not in excluded} + #input_types = {k:v if v!=np.float16 else np.float32 for k,v in input_types.items()} # cast + np_inputs = {k:torch.randn(shp).numpy().astype(input_types[k]) for k,shp in input_shapes.items()} + assert len(input_shapes) < 30, f"too many input shapes {len(input_shapes)}" + + # print input names + if DEBUG >= 2: print([inp.name for inp in onnx_model.graph.input if inp.name not in excluded]) + for device in devices: + Device.DEFAULT = device + inputs = {k:Tensor(inp) for k,inp in np_inputs.items()} + tinygrad_model = OnnxRunner(onnx_model) + benchmark(m, f"tinygrad_{device.lower()}_jitless", lambda: {k:v.numpy() for k,v in tinygrad_model(inputs).items()}) + + from tinygrad.engine.jit import TinyJit + tinygrad_jitted_model = TinyJit(lambda **kwargs: {k:v.realize() for k,v in tinygrad_model(kwargs).items()}) + for _ in range(3): {k:v.numpy() for k,v in tinygrad_jitted_model(**inputs).items()} + benchmark(m, f"tinygrad_{device.lower()}_jit", lambda: {k:v.numpy() for k,v in tinygrad_jitted_model(**inputs).items()}) # noqa: F821 + del inputs, tinygrad_model, tinygrad_jitted_model + + # convert model to torch + try: + torch_model = convert(fn) + except Exception as e: + # model conversion failed + print(f"{m:16s}onnx2torch {type(e).__name__:>25}") + else: + torch_inputs = [torch.tensor(x) for x in np_inputs.values()] + try: benchmark(m, "torch_cpu", lambda: torch_model(*torch_inputs)) + except Exception as e: print(f"{m:16s}torch_cpu {type(e).__name__:>25}") + + torch_device = "mps" if OSX else "cuda" + torch_mps_model = torch_model.to(torch_device) + torch_mps_inputs = [x.to(torch_device) for x in torch_inputs] + try: benchmark(m, f"torch_{torch_device}", lambda: torch_mps_model(*torch_mps_inputs)) + except Exception as e: print(f"{m:16s}torch_{torch_device} {type(e).__name__:>25}") + + # bench onnxruntime + ort_options = ort.SessionOptions() + ort_options.graph_optimization_level = ort.GraphOptimizationLevel.ORT_ENABLE_ALL + ort_options.log_severity_level = 3 # no warnings + for backend in ["CPU", "CUDA" if not OSX else "CoreML"]: # https://onnxruntime.ai/docs/execution-providers/ + provider = backend+"ExecutionProvider" + if provider not in ort.get_available_providers(): continue + ort_sess = ort.InferenceSession(str(fn), ort_options, [provider]) + try: + benchmark(m, f"onnxruntime_{backend.lower()}", lambda: ort_sess.run(output_names, np_inputs)) + except Exception as e: print(f"{m:16s}onnxruntime_{backend.lower()} {type(e).__name__:>25}") + del ort_sess + + if validate_outs: + for device in devices: + rtol, atol = 2e-3, 2e-3 # tolerance for fp16 models + Device.DEFAULT = device + inputs = {k:Tensor(inp) for k,inp in np_inputs.items()} + tinygrad_model = OnnxRunner(onnx_model) + tinygrad_out = tinygrad_model(inputs) + + ort_sess = ort.InferenceSession(str(fn), ort_options, ["CPUExecutionProvider"]) + onnx_out = ort_sess.run(output_names, np_inputs) + onnx_out = dict([*list(zip(output_names, onnx_out))]) + + assert_allclose(tinygrad_out, onnx_out, rtol=rtol, atol=atol) + print(f"{m:16s}outputs validated on {device=} with rtol={rtol:.1e}, atol={atol:.1e}") + + if open_csv is None: + open_csv = csv.DictWriter(open('onnx_inference_speed.csv', 'w', newline=''), fieldnames=list(CSV.keys())) + open_csv.writeheader() + open_csv.writerow(CSV) + +def assert_allclose(tiny_out:dict, onnx_out:dict, rtol, atol): + assert tiny_out.keys() == onnx_out.keys() + for k in tiny_out.keys(): + tiny_v, onnx_v = tiny_out[k], onnx_out[k] + np.testing.assert_allclose(tiny_v.numpy(), onnx_v, rtol=rtol, atol=atol, err_msg=f"For tensor '{k}' in {tiny_out.keys()}") + +if __name__ == "__main__": + devices = [Device.DEFAULT] if getenv("NOCLANG") else [Device.DEFAULT, "CPU"] + if (model:=getenv("MODEL", "")) != "": benchmark_model(model, devices, validate_outs=True) + else: + for m in MODELS: benchmark_model(m, devices, validate_outs=True) diff --git a/tinygrad_repo/test/external/external_multi_gpu.py b/tinygrad_repo/test/external/external_multi_gpu.py new file mode 100644 index 000000000..32d107df7 --- /dev/null +++ b/tinygrad_repo/test/external/external_multi_gpu.py @@ -0,0 +1,79 @@ +#!/usr/bin/env python3 +# cd extra/disassemblers/ && git clone --recursive github.com:geohot/cuda_ioctl_sniffer.git +# LD_PRELOAD=$PWD/extra/disassemblers/cuda_ioctl_sniffer/out/sniff.so GPU=1 python3 test/external/external_multi_gpu.py +import numpy as np +from tinygrad.tensor import Tensor +from tinygrad.helpers import colored, Timing, getenv +from tinygrad.device import Device + +d0, d1 = f'{Device.DEFAULT}:0', f'{Device.DEFAULT}:1' + +def sync(): + Device[d0].synchronize() + Device[d1].synchronize() + +if __name__ == "__main__": + print("GPU devices", d0, d1) + sz = getenv("N", 1024*1024*256) # 1 GB + + with Timing("GPU initial sync: "): sync() + + with Timing("CPU creation: ", on_exit=lambda x: f", {(sz*4*2)/x:.2f} GB/sec"): + c0 = (Tensor.ones(sz, device="CPU")/2).realize() + c1 = (Tensor.ones(sz, device="CPU")/4).realize() + print(c0.uop.base.realized) + print(c1.uop.base.realized) + + with Timing("CPU -> 0: ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): + a0 = c0.to(d0).realize() + sync() + with Timing("CPU -> 1: ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): + b1 = c1.to(d1).realize() + sync() + + # cross copy. this is (sometimes) going through the CPU + with Timing("0 -> 1: ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): + a1 = a0.to(d1).realize() + sync() + with Timing("1 -> 0: ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): + b0 = b1.to(d0).realize() + sync() + + # sum + with Timing("0+0 -> 0 (sum): ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): + ab0 = (a0 + b0).realize() + sync() + with Timing("1+1 -> 1 (sum): ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): + ab1 = (a1 + b1).realize() + sync() + + # cross device sum (does this work?) + with Timing(colored("0+1 -> 0 (sum): ", "red"), on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): + abx0 = (a0 + b1.to(d0)).realize() + sync() + + with Timing(colored("1+0 -> 1 (sum): ", "red"), on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): + abx1 = (b1 + a0.to(d1)).realize() + sync() + + # copy back + # NOTE: half of this slowness is caused by allocating memory on the CPU + with Timing("0 -> CPU: ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): + cc0 = ab0.numpy() + with Timing("1 -> CPU: ", on_exit=lambda x: f", {(sz*4)/x:.2f} GB/sec"): + cc1 = ab1.numpy() + + # same + print("testing") + np.testing.assert_allclose(cc0, cc1) + + # same (cross) + print("testing (cross)") + np.testing.assert_allclose(cc0, abx0.numpy()) + np.testing.assert_allclose(cc0, abx1.numpy()) + + # devices + print(ab0) + print(ab1) + print(abx0) + print(abx1) diff --git a/tinygrad_repo/test/external/external_osx_profiling.py b/tinygrad_repo/test/external/external_osx_profiling.py new file mode 100644 index 000000000..8ac1e584d --- /dev/null +++ b/tinygrad_repo/test/external/external_osx_profiling.py @@ -0,0 +1,41 @@ +from tinygrad.runtime.ops_gpu import CLProgram, CL, CLBuffer +from tinygrad import dtypes +import time + +N = 1000000 +a = CLBuffer(N, dtypes.float32) +b = CLBuffer(N, dtypes.float32) +c = CLBuffer(N, dtypes.float32) + +prg = CLProgram("test", """__kernel void test(__global float *a, __global float *b, __global float *c) { + int idx = get_global_id(0); + a[idx] = b[idx] + c[idx]; +}""") +prg.clprgs[0](CL.cl_queue[0], [N,], None, a._buf, b._buf, c._buf) +t1 = time.monotonic_ns() +e1 = prg.clprgs[0](CL.cl_queue[0], [N,], None, a._buf, b._buf, c._buf) +CL.synchronize() +t2 = time.monotonic_ns() +time.sleep(3) +t3 = time.monotonic_ns() +e2 = prg.clprgs[0](CL.cl_queue[0], [N,], None, a._buf, b._buf, c._buf) +CL.synchronize() +t4 = time.monotonic_ns() + +print(e1.profile.queued) +print(e1.profile.submit) +print(e1.profile.start) +print(e1.profile.end) + +print(e1, e2) +print(t2-t1, e1.profile.end - e1.profile.start) +print(t4-t3, e2.profile.end - e2.profile.start) +print(t3-t2, e2.profile.queued-e1.profile.end) +print((t3-t2) / (e2.profile.start-e1.profile.end), "ratio") + +print("ratio since boot", t1/e1.profile.start) + +print(e1.profile.start) +print(e1.profile.end) +print(e2.profile.start) +print(e2.profile.end) diff --git a/tinygrad_repo/test/external/external_test_am.py b/tinygrad_repo/test/external/external_test_am.py new file mode 100644 index 000000000..03371129f --- /dev/null +++ b/tinygrad_repo/test/external/external_test_am.py @@ -0,0 +1,194 @@ +import unittest +from tinygrad.runtime.support.am.amdev import AMMemoryManager, AMPageTableEntry +from tinygrad.runtime.support.am.ip import AM_GMC +from tinygrad.runtime.support.hcq import MMIOInterface +from tinygrad.runtime.support.memory import PageTableTraverseContext +from tinygrad.runtime.autogen.am import am +from tinygrad.helpers import mv_address + +class FakeGMC(AM_GMC): + def __init__(self, adev): + self.adev = adev + self.vm_base = 0x0 + self.address_space_mask = (1 << 44) - 1 + def init_hw(self): pass + def flush_tlb(self, *args, **kwargs): pass + +class FakePCIDev: + def __init__(self): self.regions = [(0xc12300000000, 0xc12400000000, 0x0)] + +class FakeAM: + def __init__(self): + self.is_booting, self.smi_dev = True, False + self.pcidev = FakePCIDev() + self.vram_mv = memoryview(bytearray(4 << 30)) + self.vram = MMIOInterface(mv_address(self.vram_mv), self.vram_mv.nbytes) + self.gmc = FakeGMC(self) + self.mm = AMMemoryManager(self, 4 << 30, boot_size=(32 << 20), pt_t=AMPageTableEntry, pte_cnt=[512, 512, 512, 512], + pte_covers=[(1 << ((9 * (3-lv)) + 12)) for lv in range(4)], first_lv=am.AMDGPU_VM_PDB1, first_page_lv=am.AMDGPU_VM_PDB2, + va_base=AMMemoryManager.va_allocator.base) + self.is_booting = False + self.ip_ver = {am.GC_HWIP: (11, 0, 0)} + def paddr2cpu(self, paddr:int) -> int: return paddr + mv_address(self.vram) + def paddr2mc(self, paddr:int) -> int: return paddr + +# * PTE format: +# * 63:59 reserved +# * 58:57 reserved +# * 56 F +# * 55 L +# * 54 reserved +# * 53:52 SW +# * 51 T +# * 50:48 mtype +# * 47:12 4k physical page base address +# * 11:7 fragment +# * 6 write +# * 5 read +# * 4 exe +# * 3 Z +# * 2 snooped +# * 1 system +# * 0 valid +def helper_read_entry_components(entry_val): + return {"paddr": entry_val & 0x0000FFFFFFFFF000, "fragment":(entry_val >> 7) & 0x1f, "valid": entry_val & 0x1, + "read": (entry_val >> 5) & 0x1, "write": (entry_val >> 6) & 0x1, "exec": (entry_val >> 4) & 0x1, + "mtype": (entry_val >> 48) & 0x7, "T": (entry_val >> 51) & 0x1, "L": (entry_val >> 55) & 0x1, "F": (entry_val >> 56) & 0x1} + +class TestAMPageTable(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.d = [FakeAM() for _ in range(2)] + + def test_page_table_walkers(self): + mm = self.d[0].mm + + for va,sz in [(0x10000, 0x3000), (0x11000, 0x300000), (0x10000, 0x2000), (0x11000, 0x5000), + (0x2000000, 0x2000), (0x4000000, 0x4000000), (0x38000, 0x303000), (0x8000, 0x1000)]: + exteranl_va = va + AMMemoryManager.va_allocator.base + mm.map_range(vaddr=exteranl_va, size=sz, paddrs=[(va, sz)]) + + ctx = PageTableTraverseContext(self.d[0], mm.root_page_table, exteranl_va) + results = list(ctx.next(sz)) + + total_covered = 0 + for tup in results: + _offset, _pt, _pte_idx, _n_ptes, _pte_covers = tup + total_covered += _n_ptes * _pte_covers + + assert total_covered == sz, f"Expected total coverage {total_covered} to be {sz}" + + for tup in results: + _offset, _pt, _pte_idx, _n_ptes, _pte_covers = tup + for i in range(_n_ptes): + pte = helper_read_entry_components(_pt.entries[_pte_idx + i]) + assert pte['paddr'] == va + _offset + i * _pte_covers, f"Expected paddr {pte['paddr']:#x} to be {va + _offset + i * _pte_covers:#x}" + assert pte['valid'] == 1 + + mm.unmap_range(va, sz) + + for tup in results: + _offset, _pt, _pte_idx, _n_ptes, _pte_covers = tup + for i in range(_n_ptes): + pte = helper_read_entry_components(_pt.entries[_pte_idx + i]) + assert pte['paddr'] == 0 + assert pte['valid'] == 0 + + def test_map_notaligned(self): + mm0 = self.d[0].mm + + for (va1,sz1),(va2,sz2) in [((0x10000, (0x1000)), (0x11000, (2 << 20)))]: + exteranl_va1 = va1 + AMMemoryManager.va_allocator.base + exteranl_va2 = va2 + AMMemoryManager.va_allocator.base + mm0.map_range(vaddr=exteranl_va1, size=sz1, paddrs=[(va1, sz1)]) + mm0.map_range(vaddr=exteranl_va2, size=sz2, paddrs=[(va2, sz2)]) + mm0.unmap_range(va2, sz2) + mm0.unmap_range(va1, sz1) + + def test_double_map(self): + mm0 = self.d[0].mm + + for va,sz in [(0x10000, 0x3000), (0x1000000, 0x1000000), (0x12000, 0x4000)]: + exteranl_va = va + AMMemoryManager.va_allocator.base + mm0.map_range(vaddr=exteranl_va, size=sz, paddrs=[(va, sz)]) + + with self.assertRaises(AssertionError): + mm0.map_range(vaddr=exteranl_va, size=0x1000, paddrs=[(va, sz)]) + + with self.assertRaises(AssertionError): + mm0.map_range(vaddr=exteranl_va, size=0x100000, paddrs=[(va, sz)]) + + with self.assertRaises(AssertionError): + mm0.map_range(vaddr=exteranl_va + 0x1000, size=0x1000, paddrs=[(va, sz)]) + + with self.assertRaises(AssertionError): + mm0.map_range(vaddr=exteranl_va + 0x2000, size=0x100000, paddrs=[(va, sz)]) + + mm0.unmap_range(vaddr=exteranl_va, size=sz) + + # Finally can map and check paddrs + mm0.map_range(vaddr=exteranl_va + 0x2000, size=0x100000, paddrs=[(0xdead0000, 0x1000), (0xdead1000, 0xff000)]) + + ctx = PageTableTraverseContext(self.d[0], mm0.root_page_table, exteranl_va + 0x2000) + for tup in ctx.next(0x100000): + _offset, _pt, _pte_idx, _n_ptes, _pte_covers = tup + for i in range(_n_ptes): + pte = helper_read_entry_components(_pt.entries[_pte_idx + i]) + assert pte['paddr'] == 0xdead0000 + _offset + i * _pte_covers, f"paddr {pte['paddr']:#x} not {0xdead0000 + _offset + i * _pte_covers:#x}" + assert pte['valid'] == 1 + + mm0.unmap_range(vaddr=exteranl_va + 0x2000, size=0x100000) + + def test_try_bad_unmap(self): + mm0 = self.d[0].mm + + with self.assertRaises(AssertionError): + mm0.unmap_range(0x10000, 0x3000) + + mm0.map_range(0x10000, 0x3000, paddrs=[(0x10000, 0x3000)]) + mm0.unmap_range(0x10000, 0x3000) + + with self.assertRaises(AssertionError): + mm0.unmap_range(0x10000, 0x3000) + + mm0.map_range(0x10000, 0x3000, paddrs=[(0x10000, 0x3000)]) + mm0.unmap_range(0x10000, 0x3000) + + with self.assertRaises(AssertionError): + mm0.unmap_range(0x10000, 0x3000) + + def test_free_pt(self): + mm0 = self.d[0].mm + + # offset from start + for off in [0, 0x3000, 0x10000]: + mm0.map_range(0x1000000 + off, (2 << 20) - off, paddrs=[(0x10000, 0x1000)] * (512 - off // 0x1000)) + mm0.unmap_range(0x1000000 + off, (2 << 20) - off) + mm0.map_range(0x1000000, 2 << 20, paddrs=[(0x10000, 2 << 20)]) + mm0.unmap_range(0x1000000, 2 << 20) + + # offset from end + for off in [0x1000, 0x20000]: + mm0.map_range(0x1000000, (2 << 20) - off, paddrs=[(0x10000, 0x1000)] * (512 - off // 0x1000)) + mm0.unmap_range(0x1000000, (2 << 20) - off) + mm0.map_range(0x1000000, 2 << 20, paddrs=[(0x10000, 2 << 20)]) + mm0.unmap_range(0x1000000, 2 << 20) + + def test_frag_size(self): + mm0 = self.d[0].mm + + def must_cover_checker(va, sz): + ans = (1 << (mm0._frag_size(va=va, sz=sz, must_cover=True) + 12)) + assert va % ans == 0 and sz % ans == 0 and (va % (2 * ans) != 0 or sz % (2 * ans) != 0), f"va {va:#x} sz {sz:#x} ans {ans:#x}" + + def not_cover_checker(va, sz): + ans = (1 << (mm0._frag_size(va=va, sz=sz, must_cover=False) + 12)) + assert va % ans == 0 and ans <= sz and (va % (2 * ans) != 0 or (2 * ans) > sz), f"va {va:#x} sz {sz:#x} ans {ans:#x}" + + for va, sz in [(0x0, 0x1000), (0x1000, 0x2000), (0x1000, 0x3000), (0x2000, 0x2000), (0x4000, 0x8000), (0x8000, 0x4000), (0x10000, 0x4000), + (0x0, 0x4000), (0x10000, 0x4000), (0x10000, 0x40000), (0x10001000, 0x40000), (0x100001000, 0x3000)]: + must_cover_checker(va, sz) + not_cover_checker(va, sz) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_amd.py b/tinygrad_repo/test/external/external_test_amd.py new file mode 100644 index 000000000..dd13353a0 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_amd.py @@ -0,0 +1,28 @@ +import unittest +from tinygrad import Device, Tensor +from tinygrad.engine.schedule import create_schedule +from tinygrad.runtime.ops_amd import AMDDevice + +class TestAMD(unittest.TestCase): + @classmethod + def setUpClass(self): + TestAMD.d0: AMDDevice = Device["AMD"] + TestAMD.a = Tensor([0.,1.], device="AMD").realize() + TestAMD.b = self.a + 1 + si = create_schedule([self.b.uop])[-1] + TestAMD.d0_runner = TestAMD.d0.get_runner(*si.ast) + TestAMD.b.uop.buffer.allocate() + + def test_amd_ring_64bit_doorbell(self): + TestAMD.d0.pm4_write_pointer[0] = TestAMD.d0.pm4_write_pointer[0] + (2 << 32) - TestAMD.d0.pm4_ring.size // 4 + for _ in range(2000): + TestAMD.d0_runner.clprg(TestAMD.b.uop.buffer._buf, TestAMD.a.uop.buffer._buf, + global_size=TestAMD.d0_runner.global_size, local_size=TestAMD.d0_runner.local_size) + TestAMD.d0_runner.clprg(TestAMD.a.uop.buffer._buf, TestAMD.b.uop.buffer._buf, + global_size=TestAMD.d0_runner.global_size, local_size=TestAMD.d0_runner.local_size) + val = TestAMD.a.uop.buffer.as_buffer().cast("f")[0] + assert val == 4000.0, f"got val {val}" + +if __name__ == "__main__": + unittest.main() + diff --git a/tinygrad_repo/test/external/external_test_datasets.py b/tinygrad_repo/test/external/external_test_datasets.py new file mode 100644 index 000000000..e1105e47d --- /dev/null +++ b/tinygrad_repo/test/external/external_test_datasets.py @@ -0,0 +1,172 @@ +from extra.datasets.kits19 import iterate, preprocess +from examples.mlperf.dataloader import batch_load_unet3d, batch_load_retinanet +from test.external.mlperf_retinanet.coco_utils import get_openimages +from test.external.mlperf_retinanet.openimages import postprocess_targets +from test.external.mlperf_retinanet.presets import DetectionPresetTrain, DetectionPresetEval +from test.external.mlperf_retinanet.model.transform import GeneralizedRCNNTransform +from test.external.mlperf_unet3d.kits19 import PytTrain, PytVal +from tinygrad.helpers import temp +from pathlib import Path +from pycocotools.coco import COCO + +import json +import nibabel as nib +import numpy as np +import os +import PIL +import random +import tempfile +import torch +import unittest + +class ExternalTestDatasets(unittest.TestCase): + def _set_seed(self): + np.random.seed(42) + random.seed(42) + torch.manual_seed(42) + +class TestKiTS19Dataset(ExternalTestDatasets): + def _create_samples(self, val, num_samples=2): + self._set_seed() + + img, lbl = np.random.rand(190, 392, 392).astype(np.float32), np.random.randint(0, 100, size=(190, 392, 392)).astype(np.uint8) + img, lbl = nib.Nifti1Image(img, np.eye(4)), nib.Nifti1Image(lbl, np.eye(4)) + dataset = "val" if val else "train" + preproc_pth = Path(tempfile.gettempdir() + f"/{dataset}") + + for i in range(num_samples): + os.makedirs(tempfile.gettempdir() + f"/case_000{i}", exist_ok=True) + nib.save(img, temp(f"case_000{i}/imaging.nii.gz")) + nib.save(lbl, temp(f"case_000{i}/segmentation.nii.gz")) + + preproc_img, preproc_lbl = preprocess(Path(tempfile.gettempdir()) / f"case_000{i}") + preproc_img_pth, preproc_lbl_pth = temp(f"{dataset}/case_000{i}_x.npy"), temp(f"{dataset}/case_000{i}_y.npy") + + os.makedirs(preproc_pth, exist_ok=True) + np.save(preproc_img_pth, preproc_img, allow_pickle=False) + np.save(preproc_lbl_pth, preproc_lbl, allow_pickle=False) + + return preproc_pth, list(preproc_pth.glob("*_x.npy")), list(preproc_pth.glob("*_y.npy")) + + def _create_ref_dataloader(self, preproc_img_pths, preproc_lbl_pths, val): + if val: + dataset = PytVal(preproc_img_pths, preproc_lbl_pths) + else: + dataset = PytTrain(preproc_img_pths, preproc_lbl_pths, patch_size=(128, 128, 128), oversampling=0.4) + + return iter(dataset) + + def _create_tinygrad_dataloader(self, preproc_pth, val, batch_size=1, shuffle=False, seed=42, use_old_dataloader=False): + if use_old_dataloader: + dataset = iterate(list(Path(tempfile.gettempdir()).glob("case_*")), preprocessed_dir=preproc_pth, val=val, shuffle=shuffle, bs=batch_size) + else: + dataset = batch_load_unet3d(preproc_pth, batch_size=batch_size, val=val, shuffle=shuffle, seed=seed) + + return iter(dataset) + + @unittest.skip("flaky") + def test_training_set(self): + preproc_pth, preproc_img_pths, preproc_lbl_pths = self._create_samples(False) + ref_dataset = self._create_ref_dataloader(preproc_img_pths, preproc_lbl_pths, False) + tinygrad_dataset = self._create_tinygrad_dataloader(preproc_pth, False) + + for ref_sample, tinygrad_sample in zip(ref_dataset, tinygrad_dataset): + self._set_seed() + + np.testing.assert_equal(tinygrad_sample[0][:, 0].numpy(), ref_sample[0]) + np.testing.assert_equal(tinygrad_sample[1][:, 0].numpy(), ref_sample[1]) + + def test_validation_set(self): + preproc_pth, preproc_img_pths, preproc_lbl_pths = self._create_samples(True) + ref_dataset = self._create_ref_dataloader(preproc_img_pths, preproc_lbl_pths, True) + tinygrad_dataset = self._create_tinygrad_dataloader(preproc_pth, True, use_old_dataloader=True) + + for ref_sample, tinygrad_sample in zip(ref_dataset, tinygrad_dataset): + np.testing.assert_equal(tinygrad_sample[0][:, 0], ref_sample[0]) + np.testing.assert_equal(tinygrad_sample[1], ref_sample[1]) + +class TestOpenImagesDataset(ExternalTestDatasets): + @classmethod + def setUpClass(cls): + cls.img_mean = [0.485, 0.456, 0.406] + cls.img_std = [0.229, 0.224, 0.225] + cls.img_size = (800, 800) + + def _create_samples(self, subset): + os.makedirs((base_dir := Path(tempfile.gettempdir() + "/openimages")) / f"{subset}/data", exist_ok=True) + os.makedirs(base_dir / Path(f"{subset}/labels"), exist_ok=True) + + lbls, img_size = ["cls_1", "cls_2"], (447, 1024) + cats = [{"id": i, "name": c, "supercategory": None} for i, c in enumerate(lbls)] + imgs = [ + { + "id": i, "file_name": f"img_{i}.jpg", + "height": img_size[0], "width": img_size[1], + "subset": subset, "license": None, "coco_url": None + } + for i in range(len(lbls)) + ] + annots = [ + { + "id": i, "image_id": i, + "category_id": 0, "bbox": [23.217183744, 31.75409775, 964.1241282560001, 326.09017434000003], + "area": 314391.4050683996, "IsOccluded": 0, + "IsInside": 0, "IsDepiction": 0, + "IsTruncated": 0, "IsGroupOf": 0, + "iscrowd": 0 + } + for i in range(len(lbls)) + ] + info = {"dataset": "openimages_mlperf", "version": "v6"} + coco_annotations = {"info": info, "licenses": [], "categories": cats, "images": imgs, "annotations": annots} + + with open(ann_file:=base_dir / Path(f"{subset}/labels/openimages-mlperf.json"), "w") as fp: + json.dump(coco_annotations, fp) + + for i in range(len(lbls)): + img = PIL.Image.new("RGB", img_size[::-1]) + img.save(base_dir / Path(f"{subset}/data/img_{i}.jpg")) + + return base_dir, ann_file + + def _create_ref_dataloader(self, base_dir, ann_file, subset): + self._set_seed() + transforms = DetectionPresetTrain("hflip") if subset == "train" else DetectionPresetEval() + return iter(get_openimages(ann_file.stem, base_dir, subset, transforms)) + + def _create_tinygrad_dataloader(self, base_dir, ann_file, subset, batch_size=1, seed=42): + return iter(batch_load_retinanet(COCO(ann_file), subset == "validation", base_dir, batch_size=batch_size, shuffle=False, seed=seed)) + + def _normalize_img(self, img): + return ((img / 255.0) - np.array(self.img_mean)) / np.array(self.img_std) + + def test_training_set(self): + base_dir, ann_file = self._create_samples((subset:="train")) + transform = GeneralizedRCNNTransform(self.img_size, self.img_mean, self.img_std) + anchors = torch.ones((120087, 4)) + + tinygrad_dataloader = self._create_tinygrad_dataloader(base_dir, ann_file, subset) + ref_dataloader = self._create_ref_dataloader(base_dir, ann_file, subset) + + for ((tinygrad_img, tinygrad_boxes, tinygrad_labels, _, _, _), (ref_img, ref_tgt)) in zip(tinygrad_dataloader, ref_dataloader): + ref_img, ref_tgt = transform(ref_img.unsqueeze(0), [ref_tgt]) + ref_tgt = postprocess_targets(ref_tgt, anchors.unsqueeze(0)) + ref_boxes, ref_labels = ref_tgt[0]["boxes"], ref_tgt[0]["labels"] + + np.testing.assert_allclose(self._normalize_img(tinygrad_img.numpy()), ref_img.tensors.transpose(1, 3).numpy(), rtol=1e-6) + np.testing.assert_equal(tinygrad_boxes[0].numpy(), ref_boxes.numpy()) + np.testing.assert_equal(tinygrad_labels[0].numpy(), ref_labels.numpy()) + + def test_validation_set(self): + base_dir, ann_file = self._create_samples((subset:="validation")) + transform = GeneralizedRCNNTransform(self.img_size, self.img_mean, self.img_std) + + tinygrad_dataloader = self._create_tinygrad_dataloader(base_dir, ann_file, subset) + ref_dataloader = self._create_ref_dataloader(base_dir, ann_file, "val") + + for ((tinygrad_img, _, _, _), (ref_img, _)) in zip(tinygrad_dataloader, ref_dataloader): + ref_img, _ = transform(ref_img.unsqueeze(0)) + np.testing.assert_allclose(self._normalize_img(tinygrad_img.numpy()), ref_img.tensors.transpose(1, 3).numpy(), rtol=1e-6) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_embedding.py b/tinygrad_repo/test/external/external_test_embedding.py new file mode 100644 index 000000000..9d6bd7f2b --- /dev/null +++ b/tinygrad_repo/test/external/external_test_embedding.py @@ -0,0 +1,8 @@ +from tinygrad.tensor import Tensor +from tinygrad.nn import Embedding + +if __name__ == "__main__": + vocab_size = 50257 + dim = 128 + test = Embedding(vocab_size, dim) + ret = test(Tensor([[1,2,3]])).numpy() diff --git a/tinygrad_repo/test/external/external_test_example.py b/tinygrad_repo/test/external/external_test_example.py new file mode 100644 index 000000000..86c3958c8 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_example.py @@ -0,0 +1,73 @@ +import unittest +from tinygrad import Device +from tinygrad.tensor import Tensor +from tinygrad.helpers import getenv, CI + +def multidevice_test(fxn): + exclude_devices = getenv("EXCLUDE_DEVICES", "").split(",") + def ret(self): + for device in Device._devices: + if device in ["REMOTE", "DISK", "NPY", "FAKE", "DSP", "NULL"]: continue + if not CI: print(device) + if device in exclude_devices: + if not CI: print(f"WARNING: {device} test is excluded") + continue + with self.subTest(device=device): + try: + Device[device] + except Exception: + if not CI: print(f"WARNING: {device} test isn't running") + continue + fxn(self, device) + return ret + +class TestExample(unittest.TestCase): + @multidevice_test + def test_convert_to_cpu(self, device): + a = Tensor([[1,2],[3,4]], device=device) + assert a.numpy().shape == (2,2) + b = a.to("CPU") + assert b.numpy().shape == (2,2) + + @multidevice_test + def test_2_plus_3(self, device): + a = Tensor([2], device=device) + b = Tensor([3], device=device) + result = a + b + print(f"{a.numpy()} + {b.numpy()} = {result.numpy()}") + assert result.numpy()[0] == 5. + + @multidevice_test + def test_example_readme(self, device): + x = Tensor.eye(3, device=device, requires_grad=True) + y = Tensor([[2.0,0,-2.0]], device=device, requires_grad=True) + z = y.matmul(x).sum() + z.backward() + + x.grad.numpy() # dz/dx + y.grad.numpy() # dz/dy + + assert x.grad.device == device + assert y.grad.device == device + + @multidevice_test + def test_example_matmul(self, device): + try: + Device[device] + except Exception: + print(f"WARNING: {device} test isn't running") + return + + x = Tensor.eye(64, device=device, requires_grad=True) + y = Tensor.eye(64, device=device, requires_grad=True) + z = y.matmul(x).sum() + z.backward() + + x.grad.numpy() # dz/dx + y.grad.numpy() # dz/dy + + assert x.grad.device == device + assert y.grad.device == device + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_hcq.py b/tinygrad_repo/test/external/external_test_hcq.py new file mode 100644 index 000000000..2ae0371fe --- /dev/null +++ b/tinygrad_repo/test/external/external_test_hcq.py @@ -0,0 +1,326 @@ +import unittest, ctypes, struct, time, array +from tinygrad import Device, Tensor, dtypes +from tinygrad.helpers import to_mv, CI +from tinygrad.device import Buffer, BufferSpec +from tinygrad.engine.realize import get_runner + +def _time_queue(q, d): + st = time.perf_counter() + q.signal(d.timeline_signal, d.timeline_value) + q.submit(d) + d._wait_signal(d.timeline_signal, d.timeline_value) + d.timeline_value += 1 + return time.perf_counter() - st + +@unittest.skipUnless(Device.DEFAULT in ["NV", "AMD"], "Runs only on NV or AMD") +class TestHCQ(unittest.TestCase): + @classmethod + def setUpClass(self): + TestHCQ.d0 = Device[Device.DEFAULT] + #TestHCQ.d1: AMDDevice = Device["AMD:1"] + TestHCQ.a = Tensor([0.,1.], device=Device.DEFAULT).realize() + TestHCQ.b = self.a + 1 + si = self.b.schedule()[-1] + TestHCQ.runner = get_runner(TestHCQ.d0.device, si.ast) + TestHCQ.b.uop.buffer.allocate() + # wow that's a lot of abstraction layers + TestHCQ.addr = struct.pack("QQ", TestHCQ.b.uop.buffer._buf.va_addr, TestHCQ.a.uop.buffer._buf.va_addr) + TestHCQ.addr2 = struct.pack("QQ", TestHCQ.a.uop.buffer._buf.va_addr, TestHCQ.b.uop.buffer._buf.va_addr) + TestHCQ.kernargs_off = TestHCQ.runner._prg.kernargs_offset + TestHCQ.kernargs_size = TestHCQ.runner._prg.kernargs_alloc_size + ctypes.memmove(TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_off, TestHCQ.addr, len(TestHCQ.addr)) + ctypes.memmove(TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_size+TestHCQ.kernargs_off, TestHCQ.addr2, len(TestHCQ.addr2)) + + if Device.DEFAULT == "AMD": + from tinygrad.runtime.ops_amd import HWQueue, HWPM4Queue + TestHCQ.compute_queue = HWPM4Queue + TestHCQ.copy_queue = HWQueue + elif Device.DEFAULT == "NV": + from tinygrad.runtime.ops_nv import HWQueue, HWQueue + # nv need to copy constbuffer there as well + to_mv(TestHCQ.d0.kernargs_ptr, 0x160).cast('I')[:] = array.array('I', TestHCQ.runner._prg.constbuffer_0) + to_mv(TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_size, 0x160).cast('I')[:] = array.array('I', TestHCQ.runner._prg.constbuffer_0) + TestHCQ.compute_queue = HWQueue + TestHCQ.copy_queue = HWQueue + + def setUp(self): + TestHCQ.d0.synchronize() + TestHCQ.a.uop.buffer.copyin(memoryview(bytearray(struct.pack("ff", 0, 1)))) + TestHCQ.b.uop.buffer.copyin(memoryview(bytearray(struct.pack("ff", 0, 0)))) + TestHCQ.d0.synchronize() # wait for copyins to complete + + def test_run_1000_times_one_submit(self): + temp_signal, temp_value = TestHCQ.d0._alloc_signal(value=0), 0 + q = TestHCQ.compute_queue() + for _ in range(1000): + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) + q.signal(temp_signal, temp_value + 1).wait(temp_signal, temp_value + 1) + temp_value += 1 + + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_size, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) + q.signal(temp_signal, temp_value + 1).wait(temp_signal, temp_value + 1) + temp_value += 1 + + q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + q.submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + val = TestHCQ.a.uop.buffer.as_buffer().cast("f")[0] + assert val == 2000.0, f"got val {val}" + + def test_run_1000_times(self): + temp_signal = TestHCQ.d0._alloc_signal(value=0) + q = TestHCQ.compute_queue() + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) + q.signal(temp_signal, 2).wait(temp_signal, 2) + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_size, TestHCQ.runner.p.global_size, + TestHCQ.runner.p.local_size) + for _ in range(1000): + TestHCQ.d0._set_signal(temp_signal, 1) + q.submit(TestHCQ.d0) + TestHCQ.compute_queue().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + val = TestHCQ.a.uop.buffer.as_buffer().cast("f")[0] + assert val == 2000.0, f"got val {val}" + + def test_run_to_3(self): + temp_signal = TestHCQ.d0._alloc_signal(value=0) + q = TestHCQ.compute_queue() + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) + q.signal(temp_signal, 1).wait(temp_signal, 1) + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_size, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) + q.signal(temp_signal, 2).wait(temp_signal, 2) + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) + q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] + assert val == 3.0, f"got val {val}" + + def test_update_exec(self): + q = TestHCQ.compute_queue() + exec_cmd_idx = len(q) + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) + q.update_exec(exec_cmd_idx, (1,1,1), (1,1,1)) + q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] + assert val == 1.0, f"got val {val}" + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] + assert val == 0.0, f"got val {val}, should not be updated" + + @unittest.skipUnless(Device.DEFAULT == "NV", "Only NV supports bind") + def test_bind_run(self): + temp_signal = TestHCQ.d0._alloc_signal(value=0) + q = TestHCQ.compute_queue() + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) + q.signal(temp_signal, 2).wait(temp_signal, 2) + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr+TestHCQ.kernargs_size, TestHCQ.runner.p.global_size, + TestHCQ.runner.p.local_size) + q.bind(TestHCQ.d0) + for _ in range(1000): + TestHCQ.d0._set_signal(temp_signal, 1) + q.submit(TestHCQ.d0) + TestHCQ.compute_queue().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + val = TestHCQ.a.uop.buffer.as_buffer().cast("f")[0] + assert val == 2000.0, f"got val {val}" + + @unittest.skipUnless(Device.DEFAULT == "NV", "Only NV supports bind") + def test_update_exec_binded(self): + q = TestHCQ.compute_queue() + exec_ptr = q.ptr() + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) + q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + q.bind(TestHCQ.d0) + + q.update_exec(exec_ptr, (1,1,1), (1,1,1)) + q.submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] + assert val == 1.0, f"got val {val}" + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] + assert val == 0.0, f"got val {val}, should not be updated" + + @unittest.skipIf(CI, "Can't handle async update on CPU") + def test_wait_signal(self): + temp_signal = TestHCQ.d0._alloc_signal(value=0) + TestHCQ.compute_queue().wait(temp_signal, value=1).signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + with self.assertRaises(RuntimeError): + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value, timeout=50) + # clean up + TestHCQ.d0._set_signal(temp_signal, 1) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value, timeout=100) + TestHCQ.d0.timeline_value += 1 + + @unittest.skipIf(CI, "Can't handle async update on CPU") + def test_wait_copy_signal(self): + temp_signal = TestHCQ.d0._alloc_signal(value=0) + TestHCQ.copy_queue().wait(temp_signal, value=1).signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + with self.assertRaises(RuntimeError): + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value, timeout=50) + # clean up + TestHCQ.d0._set_signal(temp_signal, 1) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value, timeout=100) + TestHCQ.d0.timeline_value += 1 + + def test_run_normal(self): + q = TestHCQ.compute_queue() + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) + q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] + assert val == 1.0, f"got val {val}" + + def test_submit_empty_queues(self): + TestHCQ.compute_queue().submit(TestHCQ.d0) + TestHCQ.copy_queue().submit(TestHCQ.d0) + + def test_signal_timeout(self): + with self.assertRaises(RuntimeError): + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value, timeout=50) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value + 122, timeout=50) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1, timeout=50) + + def test_signal(self): + new_timeline_value = TestHCQ.d0.timeline_value + 0xff + TestHCQ.compute_queue().signal(TestHCQ.d0.timeline_signal, new_timeline_value).submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, new_timeline_value) + TestHCQ.d0.timeline_value = new_timeline_value + 1 # update to not break runtime + + def test_copy_signal(self): + new_timeline_value = TestHCQ.d0.timeline_value + 0xff + TestHCQ.copy_queue().signal(TestHCQ.d0.timeline_signal, new_timeline_value).submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, new_timeline_value) + TestHCQ.d0.timeline_value = new_timeline_value + 1 # update to not break runtime + + def test_run_signal(self): + q = TestHCQ.compute_queue() + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) + q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + q.submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] + assert val == 1.0, f"got val {val}" + + def test_copy_1000_times(self): + q = TestHCQ.copy_queue() + q.copy(TestHCQ.a.uop.buffer._buf.va_addr, TestHCQ.b.uop.buffer._buf.va_addr, 8) + q.copy(TestHCQ.b.uop.buffer._buf.va_addr, TestHCQ.a.uop.buffer._buf.va_addr, 8) + for _ in range(1000): + q.submit(TestHCQ.d0) + TestHCQ.copy_queue().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + # confirm the signal didn't exceed the put value + with self.assertRaises(RuntimeError): + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value + 1, timeout=50) + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] + assert val == 0.0, f"got val {val}" + + def test_copy(self): + q = TestHCQ.copy_queue() + q.copy(TestHCQ.b.uop.buffer._buf.va_addr, TestHCQ.a.uop.buffer._buf.va_addr, 8) + q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + q.submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] + assert val == 1.0, f"got val {val}" + + @unittest.skipUnless(Device.DEFAULT == "NV", "Only NV supports bind") + def test_bind_copy(self): + q = TestHCQ.copy_queue() + q.copy(TestHCQ.a.uop.buffer._buf.va_addr, TestHCQ.b.uop.buffer._buf.va_addr, 8) + q.copy(TestHCQ.b.uop.buffer._buf.va_addr, TestHCQ.a.uop.buffer._buf.va_addr, 8) + q.bind(TestHCQ.d0) + for _ in range(1000): + q.submit(TestHCQ.d0) + TestHCQ.copy_queue().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + # confirm the signal didn't exceed the put value + with self.assertRaises(RuntimeError): + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value + 1, timeout=50) + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] + assert val == 0.0, f"got val {val}" + + def test_copy_bandwidth(self): + # THEORY: the bandwidth is low here because it's only using one SDMA queue. I suspect it's more stable like this at least. + SZ = 2_000_000_000 + a = Buffer(Device.DEFAULT, SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() + b = Buffer(Device.DEFAULT, SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() + q = TestHCQ.copy_queue() + q.copy(a._buf.va_addr, b._buf.va_addr, SZ) + et = _time_queue(q, TestHCQ.d0) + gb_s = (SZ/1e9)/et + print(f"same device copy: {et*1e3:.2f} ms, {gb_s:.2f} GB/s") + assert (0.3 if CI else 10) <= gb_s <= 1000 + + def test_cross_device_copy_bandwidth(self): + SZ = 2_000_000_000 + b = Buffer(f"{Device.DEFAULT}:1", SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() + a = Buffer(Device.DEFAULT, SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() + TestHCQ.d0._gpu_map(b._buf) + q = TestHCQ.copy_queue() + q.copy(a._buf.va_addr, b._buf.va_addr, SZ) + et = _time_queue(q, TestHCQ.d0) + gb_s = (SZ/1e9)/et + print(f"cross device copy: {et*1e3:.2f} ms, {gb_s:.2f} GB/s") + assert (0.3 if CI else 2) <= gb_s <= 50 + + def test_interleave_compute_and_copy(self): + q = TestHCQ.compute_queue() + qc = TestHCQ.copy_queue() + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) # b = [1, 2] + q.signal(sig:=TestHCQ.d0._alloc_signal(value=0), value=1) + qc.wait(sig, value=1) + qc.copy(TestHCQ.a.uop.buffer._buf.va_addr, TestHCQ.b.uop.buffer._buf.va_addr, 8) + qc.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + qc.submit(TestHCQ.d0) + time.sleep(0.02) # give it time for the wait to fail + q.submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + val = TestHCQ.a.uop.buffer.as_buffer().cast("f")[0] + assert val == 1.0, f"got val {val}" + + def test_cross_device_signal(self): + d1 = Device[f"{Device.DEFAULT}:1"] + q1 = TestHCQ.compute_queue() + q2 = TestHCQ.compute_queue() + q1.signal(sig:=TestHCQ.d0._alloc_signal(value=0), value=0xfff) + q2.wait(sig, value=0xfff) + q2.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + q2.submit(TestHCQ.d0) + q1.signal(d1.timeline_signal, d1.timeline_value) + q1.submit(d1) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + d1._wait_signal(d1.timeline_signal, d1.timeline_value) + d1.timeline_value += 1 + + def test_timeline_signal_rollover(self): + # NV 64bit, AMD 32bit + TestHCQ.d0.timeline_value = (1 << 64) - 20 if Device.DEFAULT == "NV" else (1 << 32) - 20 # close value to reset + TestHCQ.compute_queue().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1).submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) + + for _ in range(40): + q = TestHCQ.compute_queue() + q.wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) + q.exec(TestHCQ.runner._prg, TestHCQ.d0.kernargs_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) + q.signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0._wait_signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] + assert val == 1.0, f"got val {val}" + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_hcq_fuzz_failures.py b/tinygrad_repo/test/external/external_test_hcq_fuzz_failures.py new file mode 100644 index 000000000..2ac55c93c --- /dev/null +++ b/tinygrad_repo/test/external/external_test_hcq_fuzz_failures.py @@ -0,0 +1,61 @@ +# ruff: noqa: E501 +import os +os.environ["VALIDATE_HCQ"]="1" + +import unittest, random +import numpy as np +from tinygrad.opt.kernel import Kernel, KernelOptError +from tinygrad.device import is_dtype_supported +from tinygrad.uop.ops import UOp, Ops +from tinygrad.opt.search import Opt, OptOps +from tinygrad import Device, dtypes, Tensor +from test.external.fuzz_linearizer import compare_linearizer, compare_states, get_fuzz_rawbuf_like + +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.shape.view import View + +def helper_test_lin(lin: Kernel, opts, failed_platforms, validate_device, rtol=1e-2, atol=1e-2): + if any(b.dtype.base == dtypes.half for b in lin.membufs) and not is_dtype_supported(dtypes.half): return + if any(b.dtype.base == dtypes.bfloat16 for b in lin.membufs) and not is_dtype_supported(dtypes.bfloat16): return + + try: + lin.apply_opts(opts) + except KernelOptError: + # it's considered fixed if we invalidated the opts + assert Device.DEFAULT not in failed_platforms, f"unexpected success on {Device.DEFAULT}" + return + + (msg, rawbufs, var_vals, ground_truth, state1) = compare_linearizer(lin, rtol=rtol, atol=atol) + if msg in ["PASS", "KernelOptError"]: + # it's considered fixed if we invalidated the opts + assert Device.DEFAULT not in failed_platforms, f"unexpected success on {Device.DEFAULT}" + else: + assert Device.DEFAULT in failed_platforms, f"failed on {Device.DEFAULT} with {msg}" + + validate_lin = lin.copy() + validate_lin.opts = validate_device.renderer + validate_rawbufs = [get_fuzz_rawbuf_like(x, copy=True, force_device=validate_device.dname) for x in rawbufs] + (_msg, _, _, _, state2) = compare_linearizer(validate_lin, validate_rawbufs, var_vals, ground_truth, rtol=rtol, atol=atol) + + if _msg in ["PASS"] and compare_states(state1, state2): + assert Device.DEFAULT not in failed_platforms, f"unexpected success on {Device.DEFAULT}" + else: + assert Device.DEFAULT in failed_platforms, f"failed on {Device.DEFAULT} with {msg}" + + return lin + +class TestHCQFuzzFailures(unittest.TestCase): + def setUp(self): + random.seed(42) + np.random.seed(42) + Tensor.manual_seed(42) + + @unittest.skipUnless(Device.DEFAULT in {"QCOM"}, "for QCOM") + def test_failure_1(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( UOp(Ops.STORE, dtypes.void, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=0, mask=None, contiguous=True),)), src=()), UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 2, 4)), arg=1, src=()), x39:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=0, mask=((0, 1), (0, 6)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=2, src=()), x39,)),)),)), UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 2, 4)), arg=3, src=()), x46:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-6, mask=((0, 1), (6, 12)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=4, src=()), x46,)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=5, src=()), x54:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (12, 13)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=6, src=()), x54,)),)),)),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=7, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-13, mask=((0, 1), (13, 17)), contiguous=False),)), src=()),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=8, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-17, mask=((0, 1), (17, 21)), contiguous=False),)), src=()),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=9, src=()), x68:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (21, 22)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=10, src=()), x68,)),)),)),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=11, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-22, mask=((0, 1), (22, 26)), contiguous=False),)), src=()),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=12, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-26, mask=((0, 1), (26, 30)), contiguous=False),)), src=()),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=13, src=()), x82:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (30, 31)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=14, src=()), x82,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=15, src=()), x90:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (31, 32)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=16, src=()), x90,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=17, src=()), x98:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (32, 33)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=18, src=()), x98,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=19, src=()), x106:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (33, 34)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=20, src=()), x106,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=21, src=()), x114:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (34, 35)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=22, src=()), x114,)),)),)),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=23, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-35, mask=((0, 1), (35, 39)), contiguous=False),)), src=()),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=24, src=()), x125:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (39, 40)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=25, src=()), x125,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=26, src=()), x133:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (40, 41)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=27, src=()), x133,)),)),)),)),)), UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 2, 4)), arg=28, src=()), x140:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-41, mask=((0, 1), (41, 47)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=29, src=()), x140,)),)),)),)), UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 2, 4)), arg=30, src=()), x147:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-47, mask=((0, 1), (47, 53)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=31, src=()), x147,)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=32, src=()), x155:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (53, 54)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=33, src=()), x155,)),)),)),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=34, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-54, mask=((0, 1), (54, 58)), contiguous=False),)), src=()),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=35, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-58, mask=((0, 1), (58, 62)), contiguous=False),)), src=()),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=36, src=()), x169:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (62, 63)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=37, src=()), x169,)),)),)),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=38, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-63, mask=((0, 1), (63, 67)), contiguous=False),)), src=()),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=39, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-67, mask=((0, 1), (67, 71)), contiguous=False),)), src=()),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=40, src=()), x183:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (71, 72)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=41, src=()), x183,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=42, src=()), x191:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (72, 73)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=43, src=()), x191,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=44, src=()), x199:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (73, 74)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=45, src=()), x199,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=46, src=()), x207:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (74, 75)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=47, src=()), x207,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=48, src=()), x215:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (75, 76)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=49, src=()), x215,)),)),)),)),)), UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=50, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-76, mask=((0, 1), (76, 80)), contiguous=False),)), src=()),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=51, src=()), x226:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (80, 81)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=52, src=()), x226,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=53, src=()), x234:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (81, 82)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=54, src=()), x234,)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=55, src=()), x243:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (82, 83)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=56, src=()), x243,)),)),)), UOp(Ops.ADD, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 1, 4)), arg=57, src=()), x250:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 0), offset=0, mask=((0, 1), (83, 84)), contiguous=False),)), src=()),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=58, src=()), x250,)),)),)),)),)),)), UOp(Ops.CAST, dtypes.float, arg=None, src=( UOp(Ops.LOAD, dtypes.float, arg=None, src=( UOp(Ops.DEFINE_GLOBAL, dtypes.imageh((1, 128, 4)), arg=59, src=()), UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 596), strides=(0, 1), offset=-84, mask=((0, 1), (84, 596)), contiguous=False),)), src=()),)),)),)),)),)) # noqa: E501 + + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=4)] + helper_test_lin(Kernel(ast), opts, failed_platforms=[], validate_device=Device["GPU"]) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_hip_compile.py b/tinygrad_repo/test/external/external_test_hip_compile.py new file mode 100644 index 000000000..53ddda0b0 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_hip_compile.py @@ -0,0 +1,39 @@ +import time, unittest +from tinygrad.runtime.support.hip_comgr import compile_hip +from tinygrad import Tensor +from tinygrad.device import Device +from tinygrad.engine.schedule import create_schedule +from tinygrad.opt.kernel import Kernel + +class TestHIPCompileSpeed(unittest.TestCase): + @unittest.skipIf(Device.DEFAULT != "HIP", "only run on HIP") + def test_hip_compile(self): + a, b = Tensor([1,2,3,4,5]), Tensor([1,2,3,4,5]) + out = a + b + lin = Kernel(create_schedule([out.uop])[-1].ast[0]) + lin.linearize() + + reference = """ +#include + typedef long unsigned int size_t; + extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_id(unsigned int); + extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_group_id(unsigned int); + extern "C" __attribute__((device)) __attribute__((const)) size_t __ockl_get_local_size(unsigned int); + extern "C" __attribute__((global))void {name}(int* data0, const int* data1, const int* data2) {{ + int gidx0 = __ockl_get_group_id(0); /* 5 */ + int val0 = data1[gidx0]; + int val1 = data2[gidx0]; + data0[gidx0] = (val0+val1); + }} + """ + + def time_compile(code): + st = time.perf_counter() + compile_hip(code) + return (time.perf_counter() - st) * 1000 + + tinygrad_tm = min([time_compile(Device[Device.DEFAULT].renderer.render(f"test{i}", lin.uops)) for i in range(10)]) + ref_tm = min([time_compile(reference.format(name=f"test{i}")) for i in range(10)]) + print(f"tinygrad {tinygrad_tm:6.2f} ms") + print(f"reference {ref_tm:6.2f} ms") + assert (tinygrad_tm - ref_tm) <= 10 diff --git a/tinygrad_repo/test/external/external_test_hsa_driver.py b/tinygrad_repo/test/external/external_test_hsa_driver.py new file mode 100644 index 000000000..29ffaa234 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_hsa_driver.py @@ -0,0 +1,116 @@ +import ctypes, unittest +from tinygrad.helpers import init_c_struct_t +from tinygrad.device import Device, Buffer, BufferXfer +from tinygrad.dtype import dtypes +from tinygrad.runtime.support.hsa import AQLQueue +from tinygrad.runtime.graph.hsa import VirtAQLQueue, HSAGraph +from tinygrad.engine.realize import ExecItem + +def get_hsa_inc_prog(dev, inc=1): + prg = f""" +extern "C" __attribute__((global)) void test_inc(int* data0) {{ + data0[0] = (data0[0]+{inc}); +}} +""" + return dev.runtime("test_inc", dev.compiler.compile(prg)) + +def get_hsa_buffer_and_kernargs(dev): + test_buf = Buffer(Device.DEFAULT, 1, dtypes.int) + test_buf.copyin(memoryview(bytearray(4))) # zero mem + assert test_buf.as_buffer().cast('I')[0] == 0 # check mem is visible + sync to exec + + args_struct_t = init_c_struct_t(tuple([('f0', ctypes.c_void_p)])) + kernargs = dev.alloc_kernargs(8) + args_st = args_struct_t.from_address(kernargs) + args_st.__setattr__('f0', test_buf._buf) + dev.flush_hdp() + return test_buf, kernargs + +@unittest.skipUnless(Device.DEFAULT == "HSA", "only run on HSA") +class TestHSADriver(unittest.TestCase): + def test_hsa_simple_enqueue(self): + dev = Device[Device.DEFAULT] + queue = AQLQueue(dev, sz=256) + + clprg = get_hsa_inc_prog(dev, inc=1) + test_buf, kernargs = get_hsa_buffer_and_kernargs(dev) + + queue.submit_kernel(clprg, [1,1,1], [1,1,1], kernargs) + queue.wait() + + assert test_buf.as_buffer().cast('I')[0] == 1, f"{test_buf.as_buffer().cast('I')[0]} != 1, all packets executed?" + del queue + + def test_hsa_ring_enqueue(self): + dev = Device[Device.DEFAULT] + + queue_size = 256 + exec_cnt = int(queue_size * 1.5) + queue = AQLQueue(dev, sz=queue_size) + + clprg_inc1 = get_hsa_inc_prog(dev, inc=1) + clprg_inc2 = get_hsa_inc_prog(dev, inc=2) + test_buf, kernargs = get_hsa_buffer_and_kernargs(dev) + + for _ in range(exec_cnt): + queue.submit_kernel(clprg_inc1, [1,1,1], [1,1,1], kernargs) + for _ in range(exec_cnt): + queue.submit_kernel(clprg_inc2, [1,1,1], [1,1,1], kernargs) + queue.wait() + + expected = exec_cnt + exec_cnt * 2 + assert test_buf.as_buffer().cast('I')[0] == expected, f"{test_buf.as_buffer().cast('I')[0]} != {expected}, all packets executed?" + del queue + + def test_hsa_blit_enqueue(self): + dev = Device[Device.DEFAULT] + + queue_size = 256 + exec_cnt = 178 + queue = AQLQueue(dev, sz=queue_size) + + test_buf, kernargs = get_hsa_buffer_and_kernargs(dev) + + # Using VirtAQLQueue to blit them + virt_queue_packets_cnt = 31 + virt_queue = VirtAQLQueue(dev, sz=virt_queue_packets_cnt) + + clprogs = [] + sum_per_blit = 0 + for i in range(virt_queue_packets_cnt): + sum_per_blit += i+1 + clprogs.append(get_hsa_inc_prog(dev, inc=i+1)) + + for i in range(virt_queue_packets_cnt): + virt_queue.submit_kernel(clprogs[i], [1,1,1], [1,1,1], kernargs) + + for _ in range(exec_cnt): + queue.blit_packets(virt_queue.queue_base, virt_queue.packets_count) + queue.wait() + + expected = exec_cnt * sum_per_blit + assert test_buf.as_buffer().cast('I')[0] == expected, f"{test_buf.as_buffer().cast('I')[0]} != {expected}, all packets executed?" + del queue, clprogs + + def test_hsa_copies_sync(self): + d0, d1 = f"{Device.DEFAULT}:0", f"{Device.DEFAULT}:1" + + test_buf0 = Buffer(d0, 1, dtypes.int) + test_buf1 = Buffer(d0, 1, dtypes.int) + test_buf2 = Buffer(d1, 1, dtypes.int) + test_buf0.copyin(memoryview(bytearray(1*4))) + test_buf1.copyin(memoryview(bytearray(1*4))) + test_buf2.copyin(memoryview(bytearray(1*4))) + + jit_cache = [ExecItem(BufferXfer(), [test_buf0, test_buf2]), ExecItem(BufferXfer(), [test_buf2, test_buf1])] + graph = HSAGraph(jit_cache, [], {}) + + for i in range(10000): + test_buf0.copyin(memoryview(bytearray(1*4))) + test_buf2.copyin(memoryview(bytearray(int.to_bytes(4, length=1*4, byteorder='little')))) + graph([], {}) + assert test_buf0.as_buffer().cast('I')[0] == 4 + assert test_buf2.as_buffer().cast('I')[0] == 0 + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_image.py b/tinygrad_repo/test/external/external_test_image.py new file mode 100644 index 000000000..1c2cc397f --- /dev/null +++ b/tinygrad_repo/test/external/external_test_image.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python +import os +import unittest +import numpy as np +if 'IMAGE' not in os.environ: + os.environ['IMAGE'] = '2' +os.environ['GPU'] = '1' +os.environ['OPT'] = '2' +from tinygrad.tensor import Tensor +from tinygrad.nn import Conv2d + +class TestImage(unittest.TestCase): + def test_create_image(self): + t = Tensor.ones(128, 128, 1) + t = t.reshape(128, 32, 4) + 3 + t.realize() + np.testing.assert_array_equal(t.numpy(), np.ones((128,32,4))*4) + + def test_sum_image(self): + t1 = Tensor.ones(16, 16, 1).reshape(16, 4, 4) + 3 + t1.realize() + t1 = t1.sum() + t1.realize() + assert t1.numpy() == 16*4*4*4, f"got {t1.numpy()}" + + def test_add_image(self): + t1 = Tensor.ones(16, 16, 1).reshape(16, 4, 4) + 3 + t2 = Tensor.ones(16, 16, 1).reshape(16, 4, 4) + 4 + t1.realize() + t2.realize() + t3 = t1 + t2 + t3.realize() + np.testing.assert_array_equal(t3.numpy(), np.ones((16,4,4))*9) + + def test_padded_conv(self): + bs, in_chans, out_chans = 1,12,32 + tiny_conv = Conv2d(in_chans, out_chans, 3, bias=None, padding=1) + tiny_dat = Tensor.ones(bs, 12, 64, 128) + tiny_conv(tiny_dat).realize() + + def test_op_conv(self): + bs, in_chans, out_chans = 1,12,32 + tiny_conv = Conv2d(in_chans, out_chans, 3, bias=None, padding=1) + tiny_dconv = Conv2d(out_chans, out_chans, 1, bias=None, padding=0) + tiny_dat = Tensor.ones(bs, 12, 64, 128) + p2 = tiny_conv(tiny_dat).relu() + p2 = tiny_dconv(p2) + p2.realize() + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_jit_on_models.py b/tinygrad_repo/test/external/external_test_jit_on_models.py new file mode 100644 index 000000000..c04a6ed8a --- /dev/null +++ b/tinygrad_repo/test/external/external_test_jit_on_models.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python +import unittest +import numpy as np +from tinygrad import Tensor, dtypes +from tinygrad.engine.jit import TinyJit +from tinygrad.helpers import CI +from test.helpers import derandomize_model + +from examples.llama import Transformer + +def helper_test_jitted_correctness(gen, train, train_jit): + nojit = train(*gen()).numpy() + for _ in range(5): jit = train_jit(*gen()).numpy() + np.testing.assert_allclose(nojit, jit, rtol=1e-3, atol=1e-5) + +class TestJittedModels(unittest.TestCase): + def test_jitted_tiny_llama(self): + old_float = dtypes.default_float + dtypes.default_float = dtypes.float16 + + args_tiny = {"dim": 1024, "hidden_dim": 1024, "n_heads": 8, "n_layers": 8, "norm_eps": 1e-05, "vocab_size": 1000} + model = Transformer(**args_tiny) + derandomize_model(model) + def test(t): return model(t, 0).realize() + + @TinyJit + def test_jit(t): return model(t, 0).realize() + helper_test_jitted_correctness(lambda: (Tensor([[1,]]),), test, test_jit) + dtypes.default_float = old_float + + @unittest.skipUnless(not CI, "huge for CI") + def test_jitted_stable_diffusion(self): + from examples.stable_diffusion import UNetModel, unet_params + model = UNetModel(**unet_params) + derandomize_model(model) + def test(t, t2): return model(t, 801, t2).realize() + + @TinyJit + def test_jit(t, t2): return model(t, 801, t2).realize() + helper_test_jitted_correctness(lambda: (Tensor.randn(1, 4, 16, 16),Tensor.randn(1, 77, 768)), test, test_jit) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_keccak.py b/tinygrad_repo/test/external/external_test_keccak.py new file mode 100644 index 000000000..bccffe8be --- /dev/null +++ b/tinygrad_repo/test/external/external_test_keccak.py @@ -0,0 +1,31 @@ +import unittest, zipfile, re +from tinygrad import Tensor +from tinygrad.helpers import fetch, tqdm + +SHA3_URL = "https://csrc.nist.gov/CSRC/media/Projects/Cryptographic-Algorithm-Validation-Program/documents/sha3/sha-3bytetestvectors.zip" +SHAKE_URL = "https://csrc.nist.gov/CSRC/media/Projects/Cryptographic-Algorithm-Validation-Program/documents/sha3/shakebytetestvectors.zip" + +class TestExternalKeccak(unittest.TestCase): + def test_sha3_224(self): self.check_nist_vectors(SHA3_URL, ["SHA3_224LongMsg.rsp", "SHA3_224ShortMsg.rsp"], "sha3_224") + def test_sha3_256(self): self.check_nist_vectors(SHA3_URL, ["SHA3_256LongMsg.rsp", "SHA3_256ShortMsg.rsp"], "sha3_256") + def test_shake_128(self): self.check_nist_vectors(SHAKE_URL, ["SHAKE128LongMsg.rsp", "SHAKE128ShortMsg.rsp"], "shake_128") + + def check_nist_vectors(self, url: str, filenames: list[str], preset: str): + pattern = r"Len\s*=\s*(?P\d+)\s+Msg\s*=\s*(?P[0-9a-fA-F\s]+)\s+(MD|Output)\s*=\s*(?P[0-9a-fA-F]+)" + vecs_zip = fetch(url) + + for filename in filenames: + vecs = zipfile.ZipFile(vecs_zip).open(filename).read().decode() + + vectors = [ (l, bytes.fromhex(match["Msg"].lower()), bytes.fromhex(match["Output"].lower())) + for match in re.finditer(pattern, vecs) if (l:=int(match["Len"])) < 8192 ] + + self.assertTrue(len(vectors) > 0) + + print("file", filename) + for data_len, data, output in tqdm(vectors): + tinyout = bytes(Tensor(data[:data_len//8]).keccak(preset).data()) + self.assertEqual(tinyout, output) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_llama3_ff.py b/tinygrad_repo/test/external/external_test_llama3_ff.py new file mode 100644 index 000000000..aff88c0ce --- /dev/null +++ b/tinygrad_repo/test/external/external_test_llama3_ff.py @@ -0,0 +1,12 @@ +#!/usr/bin/env python3 +from tinygrad import Tensor, TinyJit, nn +from extra.models.llama import FeedForward + +if __name__ == "__main__": + model = FeedForward(4096, 14336) + for x in nn.state.get_parameters(model): x.replace(x.half()).realize() + jrun = TinyJit(model) + for i in range(5): + print(f"*** run {i}") + jrun(Tensor.rand(1, 4096)) + diff --git a/tinygrad_repo/test/external/external_test_lm_head.py b/tinygrad_repo/test/external/external_test_lm_head.py new file mode 100644 index 000000000..851e0aa88 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_lm_head.py @@ -0,0 +1,10 @@ +from tinygrad import Tensor, nn + +if __name__ == "__main__": + vocab_size = 50257 + n_embd = 768 + lm_head = nn.Linear(n_embd, vocab_size, bias=False) + bs = 4 + seq_len = 1024 + x = Tensor.rand(bs, seq_len, n_embd) + ret = lm_head(x).realize() diff --git a/tinygrad_repo/test/external/external_test_losses.py b/tinygrad_repo/test/external/external_test_losses.py new file mode 100644 index 000000000..cd8efde21 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_losses.py @@ -0,0 +1,40 @@ +from tinygrad import Tensor +from test.external.mlperf_retinanet.focal_loss import sigmoid_focal_loss as ref_sigmoid_focal_loss +from test.external.mlperf_unet3d.dice import DiceCELoss +from examples.mlperf.losses import dice_ce_loss, sigmoid_focal_loss, l1_loss + +import numpy as np +import torch +import unittest + +class ExternalTestLosses(unittest.TestCase): + def setUp(self): + np.random.seed(42) + + def _assert_loss(self, pred, tgt, tinygrad_metrics, ref_metrics, rtol=1e-07, atol=0, **kwargs): + tinygrad_metrics_res = tinygrad_metrics(Tensor(pred), Tensor(tgt), **kwargs) + ref_metrics_res = ref_metrics(torch.from_numpy(pred), torch.from_numpy(tgt), **kwargs) + np.testing.assert_allclose(tinygrad_metrics_res.numpy(), ref_metrics_res.numpy(), rtol=rtol, atol=atol) + + def test_dice_ce_loss(self): + pred, label = np.random.rand(1, 3, 128, 128, 128).astype(np.float32), np.ones((1, 1, 128, 128, 128)).astype(np.uint8) + tinygrad_metrics_res, ref_metrics_res = dice_ce_loss, DiceCELoss(True, True, "NCDHW", False) + self._assert_loss(pred, label, tinygrad_metrics_res, ref_metrics_res, atol=1e-4) + + def test_sigmoid_focal_loss(self): + def _apply_logit(p): return np.log(p / (1 - p)) + pred, tgt = _apply_logit(np.random.rand(5,2).astype(np.float32)), np.random.randint(0, 2, (5, 2)).astype(np.float32) + for reduction in ["mean", "sum", "none"]: + for alpha, gamma in zip([-1, 0.58], [0, 2]): + self._assert_loss(pred, tgt, sigmoid_focal_loss, ref_sigmoid_focal_loss, rtol=1e-4, alpha=alpha, gamma=gamma, reduction=reduction) + + def test_l1_loss(self): + N, C, H, W = 3, 4, 5, 6 + shapes = ((N, C), (N, C, H), (N, C, H, W)) + for reduction in ["mean", "sum", "none"]: + for shape in shapes: + pred, tgt = np.random.randint(shape).astype(np.float32), np.random.randint(shape) + self._assert_loss(pred, tgt, l1_loss, torch.nn.functional.l1_loss, reduction=reduction) + +if __name__ == '__main__': + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/external/external_test_mamba.py b/tinygrad_repo/test/external/external_test_mamba.py new file mode 100644 index 000000000..3213b7c6b --- /dev/null +++ b/tinygrad_repo/test/external/external_test_mamba.py @@ -0,0 +1,24 @@ +import unittest +from tinygrad.helpers import CI +from examples.mamba import Mamba, generate +from transformers import AutoTokenizer + +PROMPT = 'Why is gravity ' +TOKENIZER = AutoTokenizer.from_pretrained("EleutherAI/gpt-neox-20b") + +@unittest.skipIf(CI, "model is slow for CI") +class TestMamba(unittest.TestCase): + def test_mamba_130M(self): + OUT_130M = '''Why is gravity \nnot a good idea?\n\nA:''' + model = Mamba.from_pretrained('130m') + tinyoutput = generate(model, TOKENIZER, PROMPT, n_tokens_to_gen=10) + self.assertEqual(OUT_130M, tinyoutput) + del model + def test_mamba_370M(self): + OUT_370M = '''Why is gravity \nso important?\nBecause it's the only''' + model = Mamba.from_pretrained('370m') + tinyoutput = generate(model, TOKENIZER, PROMPT, n_tokens_to_gen=10) + self.assertEqual(OUT_370M, tinyoutput) + del model +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_metrics.py b/tinygrad_repo/test/external/external_test_metrics.py new file mode 100644 index 000000000..32a0a8757 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_metrics.py @@ -0,0 +1,42 @@ +from tinygrad import Tensor +from test.external.mlperf_unet3d.dice import DiceScore +from examples.mlperf.metrics import dice_score, log_perplexity + +import numpy as np +import torch +import unittest, math + +class ExternalTestMetrics(unittest.TestCase): + def _test_metrics(self, tinygrad_metrics, orig_metrics, pred, label, atol=1e-8, rtol=1e-7): + tinygrad_metrics_res = tinygrad_metrics(Tensor(pred), Tensor(label)).squeeze().numpy() + orig_metrics_res = orig_metrics(torch.from_numpy(pred), torch.from_numpy(label)).numpy() + np.testing.assert_allclose(tinygrad_metrics_res, orig_metrics_res, atol=atol, rtol=rtol) + + def test_dice(self): + pred, label = np.random.rand(1, 3, 128, 128, 128).astype(np.float32), np.ones((1, 1, 128, 128, 128)).astype(np.uint8) + self._test_metrics(dice_score, DiceScore(), pred, label) + + def test_log_perplexity(self): + # equally likely + np.testing.assert_allclose(log_perplexity(Tensor([[[1.0, 1, 1, 1]]]), Tensor([[2]])).numpy(), math.log(4)) + np.testing.assert_allclose(log_perplexity(Tensor([[[1.0]*256]*32]), Tensor([[2]*32])).numpy(), math.log(256), rtol=1e-6) + # pretty correct and incorrect + np.testing.assert_allclose(log_perplexity(Tensor([[[10000., 0, 0, 0]]]), Tensor([[0]])).numpy(), 0) + np.testing.assert_allclose(log_perplexity(Tensor([[[0.0, 10000, 10000, 10000]]]), Tensor([[0]])).numpy(), 10000, rtol=1e-3) + # higher logit -> lower loss + x = Tensor([[[4.0, 3, 2, 1]]]) + for i in range(x.numel()-1): self.assertLess(log_perplexity(x, Tensor([[i]])).item(), log_perplexity(x, Tensor([[i+1]])).item()) + # torch eval examples + np.testing.assert_allclose( + log_perplexity(Tensor([[[0.3659, 0.7025, 0.3104], [0.0097, 0.6577, 0.1947]]]), Tensor([[2, 1]])).exp().numpy(), + 2.7593, rtol=1e-5) + np.testing.assert_allclose( + log_perplexity(Tensor([[[0.3, 0.7, 0.3, 0.1], [0.5, 0.4, 0.1, 0.4],[0.1, 0.1, 0.2, 0.5]], + [[0.1, 0.6, 0.1, 0.5], [0.3, 0.7, 0.3, 0.4], [0.3, 0.7, 0.3, 0.4]]]), Tensor([[2, 1, 3], [1, 0, 1]])).exp().numpy(), + 3.6216, rtol=1e-5) + np.testing.assert_allclose( + log_perplexity(Tensor([[[0.3659, 0.7025, 0.3104], [0.0097, 0.6577, 0.1947]]]), Tensor([[2, 1]]), ignore_index=1).exp().numpy(), + 3.5372, rtol=1e-4) + +if __name__ == '__main__': + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/external/external_test_mnist_data_select.py b/tinygrad_repo/test/external/external_test_mnist_data_select.py new file mode 100644 index 000000000..d4fd6c0a5 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_mnist_data_select.py @@ -0,0 +1,8 @@ +#!/bin/bash +from tinygrad import Tensor +from extra.datasets import fetch_mnist + +if __name__ == "__main__": + X_train, Y_train, X_test, Y_test = fetch_mnist(tensors=True) + samples = Tensor.randint(512, high=X_train.shape[0]) + select = X_train[samples].realize() diff --git a/tinygrad_repo/test/external/external_test_nv.py b/tinygrad_repo/test/external/external_test_nv.py new file mode 100644 index 000000000..1e8aaa377 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_nv.py @@ -0,0 +1,66 @@ +import unittest, struct, array, ctypes +from tinygrad import Device, dtypes, Tensor +from tinygrad.helpers import to_mv +from tinygrad.runtime.ops_nv import NVDevice, HWQueue +from tinygrad.opt.search import Opt, OptOps +from test.test_linearizer_failures import helper_test_lin +from tinygrad.engine.realize import get_runner, CompiledRunner +from test.external.fuzz_linearizer import get_fuzz_rawbufs + +from tinygrad.opt.kernel import Kernel +from tinygrad.uop.ops import LazyOp, Ops, ReduceOps, BufferOps, MemBuffer +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.shape.view import View + +@unittest.skipUnless(Device.DEFAULT == "NV", "NV specific tests/fixes") +class TestNV(unittest.TestCase): + @classmethod + def setUpClass(self): + TestNV.d0: NVDevice = Device["NV"] + TestNV.a = Tensor([0.,1.], device="NV").realize() + TestNV.b = self.a + 1 + si = self.b.schedule()[-1] + TestNV.d0_runner = get_runner(TestNV.d0.device, si.ast) + TestNV.b.uop.buffer.allocate() + TestNV.addr = struct.pack("QQ", TestNV.b.uop.buffer._buf.va_addr, TestNV.a.uop.buffer._buf.va_addr) + + def test_oor_kernels(self): + ast = LazyOp(op=BufferOps.STORE, src=(LazyOp(op=Ops.CAST, src=(LazyOp(op=ReduceOps.SUM, src=(LazyOp(op=Ops.CAST, src=(LazyOp(op=Ops.MUL, src=(LazyOp(op=BufferOps.LOAD, src=(), arg=MemBuffer(idx=1, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(1, 256, 1, 512, 4, 16, 4, 16), strides=(0, 100352, 0, 196, 0, 14, 0, 1), offset=-15, mask=((0, 1), (0, 256), (0, 1), (0, 512), (0, 4), (1, 15), (0, 4), (1, 15)), contiguous=False), View(shape=(256, 1, 512, 7, 7, 512, 3, 3), strides=(2097152, 0, 0, 128, 2, 4096, 1088, 17), offset=0, mask=None, contiguous=False))))), LazyOp(op=BufferOps.LOAD, src=(), arg=MemBuffer(idx=2, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(256, 1, 512, 7, 7, 512, 3, 3), strides=(25088, 0, 49, 7, 1, 0, 0, 0), offset=0, mask=None, contiguous=False),))))), arg=None),), arg=(dtypes.float, False)),), arg=((0, 3, 4), dtypes.float)),), arg=(dtypes.half, False)),), arg=MemBuffer(idx=0, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(1, 1, 512, 1, 1, 512, 3, 3), strides=(0, 0, 4608, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=True),)))) # noqa: E501 + opts = [Opt(op=OptOps.TC, axis=6, arg=(-1, 2, 1)), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.LOCAL, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=2, arg=3), Opt(op=OptOps.UPCAST, axis=1, arg=2)] # noqa: E501 + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=["NV"]) + + def test_error_on_huge_dims(self): + ast = LazyOp(op=BufferOps.STORE, src=(LazyOp(op=ReduceOps.SUM, src=(LazyOp(op=Ops.CAST, src=(LazyOp(op=Ops.MUL, src=(LazyOp(op=BufferOps.LOAD, src=(), arg=MemBuffer(idx=1, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(1, 1, 1024, 683), strides=(0, 0, 0, 1), offset=0, mask=None, contiguous=False),)))), LazyOp(op=BufferOps.LOAD, src=(), arg=MemBuffer(idx=2, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(1, 1, 1024, 683), strides=(0, 0, 683, 1), offset=0, mask=None, contiguous=True),))))), arg=None),), arg=dtypes.float),), arg=(3,)),), arg=MemBuffer(idx=0, dtype=dtypes.float, st=ShapeTracker(views=(View(shape=(1, 1, 1024, 1), strides=(0, 0, 1, 0), offset=0, mask=None, contiguous=True),)))) # noqa: E501 + opts = [Opt(op=OptOps.GROUP, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=1, arg=32), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.LOCAL, axis=0, arg=2)] # noqa: E501 + with self.assertRaises(RuntimeError) as cm: + lin = Kernel(ast) + lin.apply_opts(opts) + rawbufs = get_fuzz_rawbufs(lin) + prg = CompiledRunner(lin.to_program()) + prg(rawbufs, {}, wait=True) + self.assertEqual(str(cm.exception), "This is a runtime error message") + + def test_buf4_usage(self): + TestNV.along = Tensor([105615], device="NV").realize() + ast = LazyOp(op=BufferOps.STORE, src=(LazyOp(op=Ops.SIN, src=(LazyOp(op=Ops.CAST, src=(LazyOp(op=BufferOps.LOAD, src=(), arg=MemBuffer(idx=1, dtype=dtypes.ulong, st=ShapeTracker(views=(View(shape=(3,), strides=(1,), offset=0, mask=None, contiguous=True),)))),), arg=dtypes.float),), arg=None),), arg=MemBuffer(idx=0, dtype=dtypes.float, st=ShapeTracker(views=(View(shape=(3,), strides=(1,), offset=0, mask=None, contiguous=True),)))) # noqa: E501 + temp_runner = get_runner(TestNV.d0.device, (ast,)) + temp_runner([TestNV.b.uop.buffer, TestNV.along.uop.buffer], var_vals={}) + val = TestNV.b.uop.buffer.as_buffer().cast("f")[0] + assert abs(val - 0.80647) < 0.001, f"got val {val}" + + def test_kernargs_no_oob_access(self): + kernargs_start = TestNV.d0._gpu_alloc((2 << 20), map_to_cpu=True).va_addr + kernargs = kernargs_start + ((2 << 20) - TestNV.d0_runner._prg.kernargs_alloc_size) + to_mv(kernargs, 0x160).cast('I')[:] = array.array('I', TestNV.d0_runner._prg.constbuffer_0) + ctypes.memmove(kernargs + TestNV.d0_runner._prg.kernargs_offset, TestNV.addr, len(TestNV.addr)) + + q = HWQueue() + q.exec(TestNV.d0_runner._prg, kernargs, TestNV.d0_runner.global_size, TestNV.d0_runner.local_size) + q.signal(TestNV.d0.timeline_signal, TestNV.d0.timeline_value).submit(TestNV.d0) + TestNV.d0._wait_signal(TestNV.d0.timeline_signal, TestNV.d0.timeline_value) + TestNV.d0.timeline_value += 1 + val = TestNV.b.uop.buffer.as_buffer().cast("f")[0] + assert val == 1.0, f"got val {val}" + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_onnx_backend.py b/tinygrad_repo/test/external/external_test_onnx_backend.py new file mode 100644 index 000000000..57bf7cf4f --- /dev/null +++ b/tinygrad_repo/test/external/external_test_onnx_backend.py @@ -0,0 +1,227 @@ +import tempfile, unittest +from typing import Any, Tuple +from onnx.backend.base import Backend, BackendRep +import onnx.backend.test +import numpy as np +from tinygrad import Tensor, Device, dtypes +from tinygrad.helpers import getenv, OSX +from tinygrad.device import is_dtype_supported + +# pip3 install tabulate +pytest_plugins = 'onnx.backend.test.report', + +from tinygrad.frontend.onnx import OnnxRunner, onnx_load + +class TinygradModel(BackendRep): + def __init__(self, run_onnx, input_names): + super().__init__() + self.fxn = run_onnx + self.input_names = input_names + + def run(self, inputs: Any, **kwargs: Any) -> Tuple[Any, ...]: + real_inputs = dict(zip(self.input_names, inputs)) + ret = self.fxn(real_inputs, debug=2) + return tuple(x.numpy() if isinstance(x, Tensor) else [i.numpy() for i in x] if isinstance(x, list) else np.array(x) for x in ret.values()) + +class TinygradBackend(Backend): + @classmethod + def prepare(cls, model: onnx.ModelProto, device): + input_all = [x.name for x in model.graph.input] + input_initializer = [x.name for x in model.graph.initializer] + net_feed_input = [x for x in input_all if x not in input_initializer] + print("prepare", cls, device, net_feed_input) + with tempfile.NamedTemporaryFile(suffix='.onnx') as f: + onnx.save(model, f.name) + f.flush() + new_model = onnx_load(f.name) + run_onnx = OnnxRunner(new_model) + return TinygradModel(run_onnx, net_feed_input) + + @classmethod + def supports_device(cls, device: str) -> bool: + # NOTE: this is onnx CPU + return device == "CPU" + +backend_test = onnx.backend.test.BackendTest(TinygradBackend, __name__) + +# BUG: segfaults +backend_test.exclude('test_MaxPool1d_stride_padding_dilation_cpu') + +# BUG: buggy onnx tests +backend_test.exclude('test_adam_multiple_cpu') + +# BUG: ORT fails these with runtime error +backend_test.exclude('test_PReLU_1d_multiparam_cpu') +backend_test.exclude('test_PReLU_2d_multiparam_cpu') +backend_test.exclude('test_PReLU_3d_multiparam_cpu') + +# BUG: we don't match ORT here due to some div inaccuracy with floats +backend_test.exclude('test_dynamicquantizelinear_cpu') +backend_test.exclude('test_dynamicquantizelinear_expanded_cpu') + +# BUG: ORT fails these with numerical error but we match ORT numerically +# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_qlinearmatmul_2D_int8_float16 +backend_test.exclude('test_qlinearmatmul_2D_int8_float16_cpu') +# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_qlinearmatmul_3D_int8_float16 +backend_test.exclude('test_qlinearmatmul_3D_int8_float16_cpu') +# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_qlinearmatmul_2D_int8_float32 +backend_test.exclude('test_qlinearmatmul_2D_int8_float32_cpu') +# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_qlinearmatmul_3D_int8_float32 +backend_test.exclude('test_qlinearmatmul_3D_int8_float32_cpu') +# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_maxunpool_export_with_output_shape +backend_test.exclude('test_maxunpool_export_with_output_shape_cpu') +# tested in external_test_onnx_ops.py::TestMainOnnxOps.test_averagepool_3d_dilations_large_count_include_pad_is_1_ceil_mode_is_True +backend_test.exclude('test_averagepool_3d_dilations_large_count_include_pad_is_1_ceil_mode_is_True_cpu') + +# about different dtypes +if not is_dtype_supported(dtypes.float64): + backend_test.exclude('float64') + backend_test.exclude('DOUBLE') + # these have float64 inputs + backend_test.exclude('test_eyelike_with_dtype_cpu') + backend_test.exclude('test_reduce_log_sum_exp*') + backend_test.exclude('test_operator_add*') + backend_test.exclude('test_einsum_*') + backend_test.exclude('test_cumsum_*') + +if not is_dtype_supported(dtypes.float16): + backend_test.exclude('float16') + backend_test.exclude('FLOAT16') + +# dtype cast +backend_test.exclude('STRING') +backend_test.exclude('FLOAT8') +backend_test.exclude('INT4') +backend_test.exclude('UINT4') +backend_test.exclude('BFLOAT16') # not supported in numpy +# TODO: fix these with true onnx float16 +backend_test.exclude('to_FLOAT16') +backend_test.exclude('cast_no_saturate') +backend_test.exclude('test_dequantizelinear_e4m3fn_float16_cpu') +backend_test.exclude('test_max_float16_cpu') +backend_test.exclude('test_min_float16_cpu') +backend_test.exclude('test_mod_mixed_sign_float16_cpu') + +backend_test.exclude('test_dequantizelinear_int4_cpu') +backend_test.exclude('test_dequantizelinear_uint4_cpu') +backend_test.exclude('test_quantizelinear_int4_cpu') +backend_test.exclude('test_quantizelinear_uint4_cpu') + +# no support for FLOAT8 +backend_test.exclude('test_quantizelinear_e4m3fn_cpu') +backend_test.exclude('test_quantizelinear_e5m2_cpu') +backend_test.exclude('test_quantizelinear_e4m3fn_cpu') +backend_test.exclude('test_quantizelinear_e5m2_cpu') +backend_test.exclude('test_dequantizelinear_e4m3fn_cpu') +backend_test.exclude('test_dequantizelinear_e4m3fn_zero_point_cpu') +backend_test.exclude('test_dequantizelinear_e5m2_cpu') + +# we don't support indexes +backend_test.exclude('test_nonzero_*') + +# no support for int pow +backend_test.exclude('test_pow_types_int32_int32_cpu') +backend_test.exclude('test_pow_types_int64_int64_cpu') + +# no boolean ops (2d, 3d, 4d) +backend_test.exclude('test_bitshift_*') + +# no string ops +backend_test.exclude('string') +backend_test.exclude('test_strnorm_*') +backend_test.exclude('test_regex_*') + +# no rnn +backend_test.exclude('test_gru_*') +backend_test.exclude('test_rnn_*') +backend_test.exclude('test_lstm_*') +backend_test.exclude('test_simple_rnn_*') + +# no control flow +# control flow uses AttributeProto.GRAPH +backend_test.exclude('test_if_*') +backend_test.exclude('test_loop*') +backend_test.exclude('test_range_float_type_positive_delta_expanded_cpu') # requires loop +backend_test.exclude('test_affine_grid_2d_align_corners_expanded_cpu') +backend_test.exclude('test_affine_grid_2d_expanded_cpu') +backend_test.exclude('test_affine_grid_3d_align_corners_expanded_cpu') +backend_test.exclude('test_affine_grid_3d_expanded_cpu') +backend_test.exclude('test_range_int32_type_negative_delta_expanded_cpu') + +# unsupported (strange) ops +backend_test.exclude('test_blackmanwindow_*') +backend_test.exclude('test_bernoulli_*') +backend_test.exclude('test_det_*') +backend_test.exclude('test_col2im_*') +backend_test.exclude('test_hammingwindow_*') +backend_test.exclude('test_hannwindow_*') +backend_test.exclude('test_hardmax_*') +backend_test.exclude('test_gridsample_*') +backend_test.exclude('test_dft_*') +backend_test.exclude('test_einsum_batch_diagonal_cpu*') # TODO: equation = '...ii ->...i' +backend_test.exclude('test_einsum_inner_prod_cpu*') # TODO: equation = 'i,i' +backend_test.exclude('test_unique_*') +backend_test.exclude('test_sequence_*') +backend_test.exclude('test_nonmaxsuppression_*') +backend_test.exclude('test_reversesequence_*') +backend_test.exclude('test_roialign_*') +backend_test.exclude('test_tfidfvectorizer_*') +backend_test.exclude('test_stft_*') +backend_test.exclude('test_melweightmatrix_*') + +# more strange ops +backend_test.exclude('test_basic_deform_conv_*') +backend_test.exclude('test_deform_conv_*') +backend_test.exclude('test_lppool_*') +backend_test.exclude('test_scan_*') +backend_test.exclude('test_split_to_sequence_*') +backend_test.exclude('test_resize_downsample_scales_cubic_*') # unsure how to implement cubic +backend_test.exclude('test_resize_downsample_sizes_cubic_*') # unsure how to implement cubic +backend_test.exclude('test_resize_upsample_scales_cubic_*') # unsure how to implement cubic +backend_test.exclude('test_resize_upsample_sizes_cubic_*') # unsure how to implement cubic +backend_test.exclude('test_ai_onnx_ml_tree_ensemble_*') # https://github.com/onnx/onnx/blob/main/onnx/reference/ops/aionnxml/op_tree_ensemble.py#L121 + +# rest of the failing tests +backend_test.exclude('test_resize_tf_crop_and_resize_cpu') # tf_crop_and_resize not implemented +backend_test.exclude('test_resize_tf_crop_and_resize_axes_2_3_cpu') # tf_crop_and_resize not implemented +backend_test.exclude('test_resize_tf_crop_and_resize_axes_3_2_cpu') # tf_crop_and_resize not implemented +backend_test.exclude('test_resize_tf_crop_and_resize_extrapolation_value_cpu') # tf_crop_and_resize value not implemented +backend_test.exclude('test_resize_downsample_scales_linear_antialias_cpu') # antialias not implemented +backend_test.exclude('test_resize_downsample_sizes_linear_antialias_cpu') # antialias not implemented +backend_test.exclude('test_ai_onnx_ml_label_encoder_tensor_value_only_mapping_cpu') # bad data type string +backend_test.exclude('test_ai_onnx_ml_label_encoder_tensor_mapping_cpu') # bad data type string + +backend_test.exclude('test_scatternd_min_cpu') # min not yet supported +backend_test.exclude('test_scatternd_max_cpu') # max not yet supported + +if Device.DEFAULT in ['GPU', 'METAL']: + backend_test.exclude('test_resize_upsample_sizes_nearest_axes_2_3_cpu') + backend_test.exclude('test_resize_upsample_sizes_nearest_axes_3_2_cpu') + backend_test.exclude('test_resize_upsample_sizes_nearest_cpu') + +if Device.DEFAULT == "METAL" or (OSX and Device.DEFAULT == "GPU"): + # numerical inaccuracy + backend_test.exclude('test_mish_cpu') + backend_test.exclude('test_mish_expanded_cpu') + +# disable model tests for now since they are slow +if not getenv("MODELTESTS"): + for x in backend_test.test_suite: + if 'OnnxBackendRealModelTest' in str(type(x)): + backend_test.exclude(str(x).split(" ")[0]) +else: + # model tests all pass! + backend_test.include('test_resnet50') + backend_test.include('test_inception_v1') + backend_test.include('test_inception_v2') + backend_test.include('test_densenet121') + backend_test.include('test_shufflenet') + backend_test.include('test_squeezenet') + backend_test.include('test_bvlc_alexnet') + backend_test.include('test_zfnet512') + backend_test.include('test_vgg19') + +globals().update(backend_test.enable_report().test_cases) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_onnx_ops.py b/tinygrad_repo/test/external/external_test_onnx_ops.py new file mode 100644 index 000000000..8150995d5 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_onnx_ops.py @@ -0,0 +1,414 @@ +# inputs, attributes, and outputs for tests are found here: +# https://github.com/onnx/onnx/blob/main/docs/Operators.md +# https://github.com/microsoft/onnxruntime/blob/main/docs/ContribOperators.md + +from typing import Any +import unittest, onnx, tempfile +from tinygrad import dtypes +from tinygrad.frontend.onnx import OnnxRunner +import numpy as np +from extra.onnx_helpers import validate +from onnx.defs import ONNX_DOMAIN, AI_ONNX_PREVIEW_TRAINING_DOMAIN +MICROSOFT_CONTRIB_OPS_DOMAIN = "com.microsoft" + +class TestOnnxOps(unittest.TestCase): + DOMAIN = None + def helper_build_model(self, op:str, inps:dict[str, np.ndarray], opts:dict[str, Any], outs:list[str]): + onnx_inputs = [onnx.helper.make_tensor_value_info(name, onnx.helper.np_dtype_to_tensor_dtype(arr.dtype), arr.shape) for name, arr in inps.items()] + onnx_outputs = [onnx.helper.make_empty_tensor_value_info(name) for name in outs] + nodes = [onnx.helper.make_node(op, list(inps), list(outs), domain=self.DOMAIN, **opts)] + graph = onnx.helper.make_graph(nodes, f"test_{op.lower()}", onnx_inputs, onnx_outputs) + model = onnx.helper.make_model(graph, producer_name=f"test_{op.lower()}") + return model + + def helper_test_single_op(self, op:str, inps:dict[str, np.ndarray], opts:dict[str, Any], outs:list[str], rtol=1e-3, atol=1e-6): + model = self.helper_build_model(op, inps, opts, outs) + with tempfile.NamedTemporaryFile() as tmp: + onnx.save(model, tmp.name) + validate(tmp.name, inps, rtol, atol) + +class TestMainOnnxOps(TestOnnxOps): + DOMAIN = ONNX_DOMAIN + def test_reshape(self): + inputs = {"in": np.arange(6, dtype=np.float32), "shape": np.array([2,3], dtype=np.int64)} + attributes = {} + outputs = ["out"] + self.helper_test_single_op("Reshape", inputs, attributes, outputs) + + def test_squeeze(self): + # axes is None + inputs = {"data": np.random.randn(1, 3, 1, 1).astype(np.float32)} + attributes = {} + outputs = ["squeezed"] + self.helper_test_single_op("Squeeze", inputs, attributes, outputs) + + def test_conv(self): + # test VALID auto_pad + inputs = { + "x": np.random.randn(1, 3, 384, 384).astype(np.float32), + "w": np.random.randn(1152, 3, 14, 14).astype(np.float32), + "b": np.random.randn(1152).astype(np.float32) + } + attributes = {'auto_pad': 'VALID', 'dilations': (1, 1), 'group': 1, 'kernel_shape': (14, 14), 'strides': (14, 14)} + outputs = ["y"] + self.helper_test_single_op("Conv", inputs, attributes, outputs, atol=1e-4) + + def test_gather(self): + # test const negative indices + inputs = { + "input": np.random.randn(1, 3, 3).astype(np.float32), + "indices": np.array(-2, dtype=np.int64), + } + attributes = {'axis': 1} + outputs = ["y"] + self.helper_test_single_op("Gather", inputs, attributes, outputs) + + def test_maxunpool_export_with_output_shape(self): + # https://github.com/onnx/onnx/blob/main/docs/Operators.md#examples-91 + xT = np.array([[[[5, 6], [7, 8]]]], dtype=np.float32) + xI = np.array([[[[5, 7], [13, 15]]]], dtype=np.int64) + output_shape = np.array((1, 1, 5, 5), dtype=np.int64) + inputs = {"x": xT, "indices": xI, "output_shape": output_shape} + attributes = {"kernel_shape": [2, 2], "strides": [2, 2]} + outputs = ["y"] + self.helper_test_single_op("MaxUnpool", inputs, attributes, outputs) + + def test_averagepool_3d_dilations_large_count_include_pad_is_1_ceil_mode_is_True(self): + # https://github.com/onnx/onnx/blob/main/docs/Operators.md#examples-13 + inputs = {"x": np.random.randn(1, 1, 32, 32, 32).astype(np.float32)} + attributes = {"kernel_shape": (5, 5, 5), "strides": (3, 3, 3), "dilations": (2, 2, 2), "count_include_pad": 1, "ceil_mode": True} + outputs = ["y"] + self.helper_test_single_op("AveragePool", inputs, attributes, outputs) + + def test_isinf(self): + # https://github.com/onnx/onnx/blob/main/docs/Operators.md#isinf + # attributes are int but output expects bool + x = np.array([-1.2, np.nan, np.inf, 2.8, -np.inf, np.inf], dtype=np.float32) + inputs = {"x": x} + attributes = {"detect_negative":1, "detect_positive":1} + outputs = ["y"] + model = self.helper_build_model("IsInf", inputs, attributes, outputs) + outputs = OnnxRunner(model)(inputs) + assert outputs["y"].dtype is dtypes.bool + + def test_quantize_linear(self): + test_cases = [ + {"test_case": "round_half_to_even", "qdtype": np.int8, "qzero_point": 0, "x": [-1.5, -0.5, 0.5, 1.5], "scale": 1.0}, + {"test_case": "round_to_even_before_add_zero_point", "qdtype": np.uint8, "qzero_point": 1, "x": [0.5, 1.5], "scale": 1.0}, + ] + for case in test_cases: + with self.subTest(test_case=case["test_case"]): + inputs = { + "x": np.array([case["x"]], dtype=np.float32), + "y_scale": np.array(case["scale"], dtype=np.float32), + "y_zero_point": np.array(case["qzero_point"], dtype=case["qdtype"]) + } + self.helper_test_single_op("QuantizeLinear", inputs, {}, ["y"]) + + def test_dynamic_quantize_linear(self): + test_cases = [ + {"name": "round_half_to_even", "x": np.array([0, 0.5, 1.5, 255], dtype=np.float32)}, + {"name": "round_zero_point_half_down_to_even", "x": np.array([-1, 509], dtype=np.float32)}, + {"name": "round_zero_point_half_up_to_even", "x": np.array([-11, 499], dtype=np.float32)}, + # other tests from https://github.com/onnx/onnx/blob/main/docs/Operators.md#examples-45 + {"name": "max_adjusted", "x": np.array([-1.0, -2.1, -1.3, -2.5, -3.34, -4.0], dtype=np.float32)}, + {"name": "min_adjusted", "x": np.array([1, 2.1, 1.3, 2.5, 3.34, 4.0, 1.5, 2.6, 3.9, 4.0, 3.0, 2.345], dtype=np.float32).reshape((3, 4))}, + ] + for case in test_cases: + with self.subTest(test_case=case["name"]): + self.helper_test_single_op("DynamicQuantizeLinear", {"x": case["x"]}, {}, ["y", "y_scale", "y_zero_point"]) + + def test_qlinear_conv(self): + for dtype, zero_point in [(np.uint8, 128), (np.int8, 0)]: + for b in (np.ones([32], dtype=np.int32), np.zeros([32], dtype=np.int32)): + with self.subTest(dtype=dtype, zero_point=zero_point): + dtype_min, dtype_max = np.iinfo(dtype).min, np.iinfo(dtype).max + inputs = { + "x": np.random.randint(dtype_min, dtype_max + 1, [1, 3, 224, 224], dtype=dtype), + "x_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "x_zero_point": np.array(zero_point, dtype=dtype), + "w": np.random.randint(dtype_min, dtype_max + 1, [32, 3, 3, 3], dtype=dtype), + "w_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "w_zero_point": np.array(zero_point, dtype=dtype), + "y_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "y_zero_point": np.array(zero_point, dtype=dtype), + "b": b + } + attributes = {'auto_pad': 'NOTSET', 'dilations': (1, 1), 'group': 1, 'kernel_shape': (3, 3), 'pads': (1, 1, 1, 1), 'strides': (2, 2)} + outputs = ["out"] + self.helper_test_single_op("QLinearConv", inputs, attributes, outputs, atol=1) # occasionally inaccurate + + def test_qlinear_matmul(self): + for dtype, zero_point in [(np.uint8, 128), (np.int8, 0)]: + with self.subTest(dtype=dtype, zero_point=zero_point): + dtype_min, dtype_max = np.iinfo(dtype).min, np.iinfo(dtype).max + inputs = { + "A": np.random.randint(dtype_min, dtype_max + 1, [10, 10], dtype=dtype), + "A_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "A_zero_point": np.array(zero_point, dtype=dtype), + "B": np.random.randint(dtype_min, dtype_max + 1, [10, 10], dtype=dtype), + "B_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "B_zero_point": np.array(zero_point, dtype=dtype), + "Y_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "Y_zero_point": np.array(zero_point, dtype=dtype) + } + attributes = {} + outputs = ["Y"] + self.helper_test_single_op("QLinearMatMul", inputs, attributes, outputs) + + for name,val in (("round_half_down_to_even", 1), ("round_half_up_to_even", 3)): + with self.subTest(test_case=name, val=val): + inputs = { + "A": np.array([val], dtype=np.int8), + "A_scale": np.array(0.5, dtype=np.float32), + "A_zero_point": np.array(0, dtype=np.int8), + "B": np.array([1], dtype=np.int8), + "B_scale": np.array(1, dtype=np.float32), + "B_zero_point": np.array(0, dtype=np.int8), + "Y_scale": np.array(1, dtype=np.float32), + "Y_zero_point": np.array(0, dtype=np.int8) + } + attributes = {} + outputs = ["Y"] + self.helper_test_single_op("QLinearMatMul", inputs, attributes, outputs) + + def _run_qlinearmatmul_test(self, quant_type, dtype, dims): + # https://github.com/onnx/onnx/blob/main/docs/Operators.md#examples-111 + if dims == 2: + a = np.array([[208, 236, 0, 238], [3, 214, 255, 29]]) + b = np.array([[152, 51, 244], [60, 26, 255], [0, 127, 246], [127, 254, 247]]) + else: + a = np.array([[[208, 236, 0, 238], [3, 214, 255, 29]], [[208, 236, 0, 238], [3, 214, 255, 29]]]) + b = np.array([[[152, 51, 244], [60, 26, 255], [0, 127, 246], [127, 254, 247]], [[152, 51, 244], [60, 26, 255], [0, 127, 246], [127, 254, 247]]]) + a_zero_point = np.array([113]) + b_zero_point = np.array([114]) + y_zero_point = np.array([118]) + if quant_type == np.int8: + a, b, a_zero_point, b_zero_point, y_zero_point = (x - 127 for x in (a, b, a_zero_point, b_zero_point, y_zero_point)) + a, b, a_zero_point, b_zero_point, y_zero_point = (x.astype(quant_type) for x in (a, b, a_zero_point, b_zero_point, y_zero_point)) + inputs = { + "a": a, "a_scale": np.array([0.0066], dtype=dtype), "a_zero_point": a_zero_point, + "b": b, "b_scale": np.array([0.00705], dtype=dtype), "b_zero_point": b_zero_point, + "y_scale": np.array([0.0107], dtype=dtype), "y_zero_point": y_zero_point + } + self.helper_test_single_op("QLinearMatMul", inputs, {}, ["y"],) + def test_qlinearmatmul_2D_int8_float16(self): self._run_qlinearmatmul_test(np.int8, np.float16, 2) + def test_qlinearmatmul_3D_int8_float16(self): self._run_qlinearmatmul_test(np.int8, np.float16, 3) + def test_qlinearmatmul_2D_int8_float32(self): self._run_qlinearmatmul_test(np.int8, np.float32, 2) + def test_qlinearmatmul_3D_int8_float32(self): self._run_qlinearmatmul_test(np.int8, np.float32, 3) + +class TestTrainingOnnxOps(TestOnnxOps): + # NOTE: ORT doesn't actually support training ops on cpu so we test using functions provided by onnx + DOMAIN = AI_ONNX_PREVIEW_TRAINING_DOMAIN + def _validate_training(self, op:str, onnx_fxn, inps:dict[str, np.ndarray], opts:dict[str, Any], outs:list[str]): + model = self.helper_build_model(op, inps, opts, outs) + if op == "Momentum": del opts['mode'] + runner = OnnxRunner(model) + tiny_out = runner(inps) + onnx_out = onnx_fxn(**inps, **opts) + for (nm, t_out), o_out in zip(tiny_out.items(), onnx_out): + np.testing.assert_allclose(t_out.numpy(), o_out, rtol=1e-3, atol=1e-6, err_msg=f"{nm} failed") + + def test_adagrad_t_greater_than_zero(self): + from onnx.backend.test.case.node.adagrad import apply_adagrad + for t in [1, 3, 100]: + inputs = { + "r": np.array(0.01, dtype=np.float32), + "t": np.array(t, dtype=np.int32), + "x": np.random.randn(3, 3).astype(np.float32), + "g": np.random.randn(3, 3).astype(np.float32), + "h": np.random.randn(3, 3).astype(np.float32), + } + attributes = {"decay_factor": 0.1, "epsilon": 1e-6, "norm_coefficient": 0.01} + outputs = ["X_out", "H_out"] + self._validate_training("Adagrad", apply_adagrad, inputs, attributes, outputs) + + def test_momentum_t_greater_than_zero(self): + from onnx.backend.test.case.node.momentum import apply_momentum, apply_nesterov + for onnx_fxn, mode in ((apply_momentum, "standard"), (apply_nesterov, "nesterov")): + for t in [1, 3, 100]: + inputs = { + "r": np.array(0.01, dtype=np.float32), + "t": np.array(t, dtype=np.int32), + "x": np.random.randn(3, 3).astype(np.float32), + "g": np.random.randn(3, 3).astype(np.float32), + "v": np.random.randn(3, 3).astype(np.float32), + } + attributes = {"alpha": 0.9, "beta": 0.1, "mode": mode, "norm_coefficient": 0.01} + outputs = ["X_out", "V_out"] + self._validate_training("Momentum", onnx_fxn, inputs, attributes, outputs) + + def test_adam_t_greater_than_zero(self): + from onnx.backend.test.case.node.adam import apply_adam + for t in [1, 3, 100]: + inputs = { + "r": np.array(0.01, dtype=np.float32), + "t": np.array(t, dtype=np.int32), + "x": np.random.randn(3, 3).astype(np.float32), + "g": np.random.randn(3, 3).astype(np.float32), + "v": np.random.randn(3, 3).astype(np.float32), + "h": np.random.randn(3, 3).astype(np.float32), + } + attributes = { "alpha": 0.9, "beta": 0.999, "epsilon": 1e-8, "norm_coefficient": 0.01, "norm_coefficient_post": 0.02 } + outputs = ["X_new", "V_new", "H_new"] + self._validate_training("Adam", apply_adam, inputs, attributes, outputs) + +class TestContribOnnxOps(TestOnnxOps): + DOMAIN = MICROSOFT_CONTRIB_OPS_DOMAIN + def test_attention(self): + batch_size, seq_len, input_hidden_size = 2, 8, 256 + num_heads, head_size = 4, 64 + hidden_size = num_heads * head_size + v_hidden_size = hidden_size + + # for mask_index + right_padding_mask = np.random.randint(1, seq_len + 1, size=(batch_size,), dtype=np.int32) + end_positions = np.random.randint(1, seq_len + 1, size=(batch_size,), dtype=np.int32) + start_positions = np.array([np.random.randint(0, end) for end in end_positions], dtype=np.int32) + left_padding_mask = np.concatenate([end_positions, start_positions]) + + base_inps = { + "input": np.random.randn(batch_size, seq_len, input_hidden_size).astype(np.float32), + "weights": np.random.randn(input_hidden_size, hidden_size * 3).astype(np.float32), + # bias is required in ORT (segfaults otherwise), eventhough docs says it's optional + "bias": np.random.randn(hidden_size * 2 + v_hidden_size).astype(np.float32), + } + base_opts = {"num_heads": num_heads} + + test_cases = [ + ({}, {}), + ({}, {"scale": 0.1}), + ({}, {"scale": 1.0}), + ({}, {"unidirectional": 1}), + ({"mask_index": right_padding_mask}, {}), + ({"mask_index": left_padding_mask}, {}), + ({"mask_index": np.random.randint(0, seq_len, size=(batch_size, seq_len), dtype=np.int32)}, {"mask_filter_value": -5000.0}), + ({"mask_index": np.random.randint(0, seq_len, size=(batch_size, seq_len, seq_len), dtype=np.int32)}, {"mask_filter_value": -np.inf}), + # BUG: when `mask_index` is used with `unidirectional`, the first value must be True + # otherwise this will trigger a different ORT behavior where start consecutive Falses will be turned True + # e.g. mask_index = [[0, 0, 1, 0, 1, 1, 1, 1], [0, 0, 1, 0, 1, 1, 1, 1]] + # will need mask[:, :, 0:1, 0:1] = True + ({"mask_index": np.array([[1, 0, 1, 0, 1, 1, 1, 1], [1, 0, 1, 0, 1, 1, 1, 1]], dtype=np.int32)}, {"unidirectional": 1}), + ({ "weights": np.random.randn(input_hidden_size, hidden_size + hidden_size + 128).astype(np.float32), + "bias": np.random.randn(hidden_size + hidden_size + 128).astype(np.float32)}, + {"qkv_hidden_sizes": [hidden_size, hidden_size, 128]}), + # TODO: past is not tested. ORT gives type error for input + ] + + for i, (extra_inps, extra_opts) in enumerate(test_cases): + with self.subTest(f"test_attention_{i}"): + inps = {**base_inps, **extra_inps} + opts = {**base_opts, **extra_opts} + outputs = ["output", "present"] if "past" in inps else ["output"] + self.helper_test_single_op("Attention", inps, opts, outputs, atol=1e-4) + + def test_skip_layer_normalization(self): + shape = (2, 8, 32) + for has_beta in [True, False]: + for has_bias in [True, False]: + with self.subTest(has_beta=has_beta, has_bias=has_bias): + hidden_size = shape[-1] + inputs = { + "input": np.random.randn(*shape).astype(np.float32), + "skip": np.random.randn(*shape).astype(np.float32), + "gamma": np.random.randn(hidden_size).astype(np.float32), + } + if has_beta: inputs["beta"] = np.random.randn(hidden_size).astype(np.float32) + if has_bias: inputs["bias"] = np.random.randn(hidden_size).astype(np.float32) + attributes = {"epsilon": 1e-12} + outputs = ["output", "mean", "inv_std_var", "input_skip_bias_sum"] + self.helper_test_single_op("SkipLayerNormalization", inputs, attributes, outputs) + + def test_bias_gelu(self): + shape = (2,3,4) + inputs = { + "A": np.random.randn(*shape).astype(np.float32), + "B": np.random.randn(shape[-1]).astype(np.float32) + } + attributes = {} + outputs = ["C"] + self.helper_test_single_op("BiasGelu", inputs, attributes, outputs) + + def test_qlinear_add(self): + for dtype, zero_point in [(np.uint8, 128), (np.int8, 0)]: + with self.subTest(dtype=dtype, zero_point=zero_point): + dtype_min, dtype_max = np.iinfo(dtype).min, np.iinfo(dtype).max + inputs = { + "A": np.random.randint(dtype_min, dtype_max + 1, [10, 10], dtype=dtype), + "A_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "A_zero_point": np.array(zero_point, dtype=dtype), + "B": np.random.randint(dtype_min, dtype_max + 1, [10, 10], dtype=dtype), + "B_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "B_zero_point": np.array(zero_point, dtype=dtype), + "C_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "C_zero_point": np.array(zero_point, dtype=dtype) + } + attributes = {} + outputs = ["C"] + self.helper_test_single_op("QLinearAdd", inputs, attributes, outputs, atol=1) # TODO: look into why this is inaccurate + + with self.subTest(test_case="round_half_to_even"): + inputs = { + "A": np.array([1, 1, 1, 1], dtype=np.int8), + "A_scale": np.array(1, dtype=np.float32), + "A_zero_point": np.array(0, dtype=np.int8), + "B": np.array([1, 5, -3, -7], dtype=np.int8), + "B_scale": np.array(1, dtype=np.float32), + "B_zero_point": np.array(0, dtype=np.int8), + "C_scale": np.array(4, dtype=np.float32), + "C_zero_point": np.array(0, dtype=np.int8) + } + attributes = {} + outputs = ["C"] + self.helper_test_single_op("QLinearAdd", inputs, attributes, outputs) + + def test_qlinear_mul(self): + for dtype, zero_point in [(np.uint8, 128), (np.int8, 0)]: + with self.subTest(dtype=dtype, zero_point=zero_point): + dtype_min, dtype_max = np.iinfo(dtype).min, np.iinfo(dtype).max + inputs = { + "A": np.random.randint(dtype_min, dtype_max + 1, [10, 10], dtype=dtype), + "A_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "A_zero_point": np.array(zero_point, dtype=dtype), + "B": np.random.randint(dtype_min, dtype_max + 1, [10, 10], dtype=dtype), + "B_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "B_zero_point": np.array(zero_point, dtype=dtype), + "C_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "C_zero_point": np.array(zero_point, dtype=dtype) + } + attributes = {} + outputs = ["C"] + self.helper_test_single_op("QLinearMul", inputs, attributes, outputs) + + with self.subTest(test_case="round_half_to_even"): + inputs = { + "A": np.array([1, 1, 1, 1], dtype=np.int8), + "A_scale": np.array(1, dtype=np.float32), + "A_zero_point": np.array(0, dtype=np.int8), + "B": np.array([2, 6, -2, -6], dtype=np.int8), + "B_scale": np.array(1, dtype=np.float32), + "B_zero_point": np.array(0, dtype=np.int8), + "C_scale": np.array(4, dtype=np.float32), + "C_zero_point": np.array(0, dtype=np.int8) + } + attributes = {} + outputs = ["C"] + self.helper_test_single_op("QLinearMul", inputs, attributes, outputs) + + def test_qlinear_global_average_pool(self): + for dtype, zero_point in [(np.uint8, 128), (np.int8, 0)]: + with self.subTest(dtype=dtype, zero_point=zero_point): + dtype_min, dtype_max = np.iinfo(dtype).min, np.iinfo(dtype).max + inputs = { + "X": np.random.randint(dtype_min, dtype_max + 1, [1, 3, 32, 32], dtype=dtype), + "x_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "x_zero_point": np.array(zero_point, dtype=dtype), + "y_scale": np.array(np.random.uniform(0.01, 0.1), dtype=np.float32), + "y_zero_point": np.array(zero_point, dtype=dtype) + } + attributes = {"channels_last": 0} + outputs = ["C"] + self.helper_test_single_op("QLinearGlobalAveragePool", inputs, attributes, outputs) + +if __name__ == "__main__": + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/external/external_test_onnx_runner.py b/tinygrad_repo/test/external/external_test_onnx_runner.py new file mode 100644 index 000000000..5cad1e530 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_onnx_runner.py @@ -0,0 +1,77 @@ +import unittest, onnx, tempfile +from tinygrad import dtypes +from tinygrad.frontend.onnx import OnnxRunner, onnx_load +from tinygrad.device import is_dtype_supported +from extra.onnx import data_types +from hypothesis import given, settings, strategies as st +import numpy as np + +data_types.pop(16) # TODO: this is bf16, need to support double parsing first. +device_supported_dtypes = [odt for odt, dtype in data_types.items() if is_dtype_supported(dtype)] +device_unsupported_dtypes = [odt for odt, dtype in data_types.items() if not is_dtype_supported(dtype)] + +class TestOnnxRunnerDtypes(unittest.TestCase): + def _test_input_spec_dtype(self, onnx_data_type, tinygrad_dtype): + input_tensor = onnx.helper.make_tensor_value_info('input', onnx_data_type, ()) + output_tensor = onnx.helper.make_tensor_value_info('output', onnx_data_type, ()) + node = onnx.helper.make_node('Identity', inputs=['input'], outputs=['output']) + graph = onnx.helper.make_graph([node], 'identity_test', [input_tensor], [output_tensor]) + model = onnx.helper.make_model(graph) + tmp = tempfile.NamedTemporaryFile(suffix='.onnx') + onnx.save(model, tmp.name) + tmp.flush() + model = onnx_load(tmp.name) + runner = OnnxRunner(model) + self.assertEqual(len(runner.graph_inputs), 1) + self.assertEqual(runner.graph_inputs['input'].dtype, tinygrad_dtype) + + def _test_initializer_dtype(self, onnx_data_type, tinygrad_dtype): + arr = np.array([0, 1], dtype=onnx.helper.tensor_dtype_to_np_dtype(onnx_data_type)) + initializer = onnx.helper.make_tensor('initializer', onnx_data_type, arr.shape, arr.tobytes(), raw=True) + input_tensor = onnx.helper.make_tensor_value_info('input', onnx_data_type, ()) + output_tensor = onnx.helper.make_tensor_value_info('output', onnx_data_type, ()) + node = onnx.helper.make_node('Identity', inputs=['input'], outputs=['output']) + graph = onnx.helper.make_graph([node], 'identity_test', [input_tensor], [output_tensor], [initializer]) + model = onnx.helper.make_model(graph) + tmp = tempfile.NamedTemporaryFile(suffix='.onnx') + onnx.save(model, tmp.name) + tmp.flush() + model = onnx_load(tmp.name) + runner = OnnxRunner(model) + self.assertEqual(len(runner.graph_inputs), 1) + self.assertEqual(runner.graph_values['initializer'].dtype, tinygrad_dtype) + + def _test_node_attribute_dtype(self, onnx_data_type, tinygrad_dtype): + arr = np.array([0, 1], dtype=onnx.helper.tensor_dtype_to_np_dtype(onnx_data_type)) + output_tensor = onnx.helper.make_tensor_value_info('output', onnx_data_type, arr.shape) + value_tensor = onnx.helper.make_tensor('value', onnx_data_type, arr.shape, arr.tobytes(), raw=True) + node = onnx.helper.make_node('Constant', inputs=[], outputs=['output'], value=value_tensor) + graph = onnx.helper.make_graph([node], 'attribute_test', [], [output_tensor]) + model = onnx.helper.make_model(graph) + tmp = tempfile.NamedTemporaryFile(suffix='.onnx') + tmp.flush() + onnx.save(model, tmp.name) + model = onnx_load(tmp.name) + runner = OnnxRunner(model) + self.assertEqual(runner.graph_nodes[0].opts['value'].dtype, tinygrad_dtype) + + @settings(deadline=1000) # TODO investigate unreliable timing + @given(onnx_data_type=st.sampled_from(device_supported_dtypes)) + def test_supported_dtype_spec(self, onnx_data_type): + tinygrad_dtype = data_types[onnx_data_type] + self._test_input_spec_dtype(onnx_data_type, tinygrad_dtype) + self._test_initializer_dtype(onnx_data_type, tinygrad_dtype) + self._test_node_attribute_dtype(onnx_data_type, tinygrad_dtype) + + @unittest.skipUnless(device_unsupported_dtypes, "No unsupported dtypes for this device to test.") + @settings(deadline=1000) # TODO investigate unreliable timing + @given(onnx_data_type=st.sampled_from(device_unsupported_dtypes)) + def test_unsupported_dtype_spec(self, onnx_data_type): + tinygrad_dtype = dtypes.default_int if dtypes.is_int(data_types[onnx_data_type]) else dtypes.default_float + # TODO: maybe unsupported input spec dtype parsing shouldn't default to a dtype + self._test_input_spec_dtype(onnx_data_type, tinygrad_dtype) + self._test_initializer_dtype(onnx_data_type, tinygrad_dtype) + self._test_node_attribute_dtype(onnx_data_type, tinygrad_dtype) + +if __name__ == '__main__': + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/external/external_test_opt.py b/tinygrad_repo/test/external/external_test_opt.py new file mode 100644 index 000000000..584c3af89 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_opt.py @@ -0,0 +1,240 @@ +#!/usr/bin/env python +import gc, unittest +import numpy as np +import torch + +from tinygrad import GlobalCounters, Tensor, Device +from tinygrad.helpers import getenv, Context +from tinygrad.nn.state import get_parameters +from tinygrad.engine.realize import capturing +from tinygrad.tensor import _to_np_dtype + +class CLCache: + def __init__(self, allowed=None, strict=False, preclear=True, var_vals=None): + self.allowed, self.strict, self.preclear, self.var_vals = allowed, strict, preclear, var_vals if var_vals is not None else {} + self.count = 0 + def add(self, ei): self.count += 1 + def __enter__(self): + if self.preclear: + gc.collect() + for x in [x for x in gc.get_objects() if isinstance(x, Tensor)]: + x.realize() + GlobalCounters.reset() + capturing.append(self) + print("cache: entering") + return self + def __exit__(self, _type, value, traceback): + capturing.clear() + print(f"cache: exiting with size {self.count}", f"allowed {self.allowed}" if self.allowed is not None else "") + if self.allowed is not None: + assert self.count == self.allowed, f"{self.count} != {self.allowed}" + +from extra.models.convnext import ConvNeXt +from extra.models.efficientnet import EfficientNet +from extra.models.resnet import ResNet18 +from extra.models.vit import ViT + +@unittest.skipUnless(Device.DEFAULT == "GPU", "Not Implemented") +class TestInferenceMinKernels(unittest.TestCase): + def setUp(self): + self.training_old = Tensor.training + Tensor.training = False + def tearDown(self): + Tensor.training = self.training_old + + def test_convnext(self): + model = ConvNeXt() + for p in get_parameters(model): p.assign(np.zeros(p.shape, dtype=_to_np_dtype(p.dtype))) + img = Tensor.randn(1, 3, 224, 224) + with CLCache(143): + model(img).realize() + + def test_enet(self): + model = EfficientNet(getenv("ENET_NUM", 0), has_se=False) + for p in get_parameters(model): p.assign(np.zeros(p.shape, dtype=_to_np_dtype(p.dtype))) + img = Tensor.randn(1, 3, 224, 224) + with CLCache(51): + model.forward(img).realize() + + def test_enet_se(self): + model = EfficientNet(getenv("ENET_NUM", 0), has_se=True) + for p in get_parameters(model): p.assign(np.zeros(p.shape, dtype=_to_np_dtype(p.dtype))) + img = Tensor.randn(1, 3, 224, 224) + # TODO: this seems very high + with CLCache(115): + model.forward(img).realize() + + def test_resnet(self): + model = ResNet18() + for p in get_parameters(model): p.assign(np.zeros(p.shape, dtype=_to_np_dtype(p.dtype))) + img = Tensor.randn(1, 3, 224, 224) + with CLCache(23): + model.forward(img).realize() + + def test_vit(self): + model = ViT(embed_dim=192, num_heads=3) + for p in get_parameters(model): p.assign(np.zeros(p.shape, dtype=_to_np_dtype(p.dtype))) + img = Tensor.randn(1, 3, 224, 224) + with CLCache(209) as cache: # NOTE: this is way too high + out = model.forward(img) + assert cache.count == 0, "ViT prerealized?" + out.realize() + + @unittest.skip("llama is fp16 but CI does not have fp16") + def test_llama(self): + from examples.llama import Transformer + args_tiny = {"dim": 512, "hidden_dim": 1024, "n_heads": 8, "n_layers": 4, "norm_eps": 1e-05, "vocab_size": 1000} + model = Transformer(**args_tiny) + for p in get_parameters(model): p.assign(np.zeros(p.shape, dtype=_to_np_dtype(p.dtype))) + inp = Tensor([[1,2,3,4]]) + with CLCache(100): + model(inp, 0).realize() + +@unittest.skipUnless(Device.DEFAULT == "GPU", "Not Implemented") +class TestOptBinOp(unittest.TestCase): + def _test_no_binop_rerun(self, f1, f2=None, allowed=1): + a = Tensor.randn(16, 16) + b = Tensor.randn(16, 16) + with CLCache() as cache: + c = f1(a, b) + if f2 is not None: d = f2(a, b) + c.realize() + if f2 is not None: d.realize() + assert cache.count == allowed, "binop was rerun!" + if f2 is not None: np.testing.assert_allclose(c.numpy().ravel(), d.numpy().ravel(), rtol=1e-3, atol=1e-5) + + def test_no_binop_rerun(self): return self._test_no_binop_rerun(lambda a,b: a*b, lambda a,b: (a*b).reshape(16, 16, 1)) + def test_no_binop_rerun_alt(self): return self._test_no_binop_rerun(lambda a,b: (a*b).reshape(16, 16, 1), lambda a,b: a*b) + def test_no_binop_rerun_reduce_broadcast(self): + return self._test_no_binop_rerun(lambda a,b: a.sum()+b, lambda a,b: a.sum().reshape(1,1)+b, allowed=2) + + @unittest.skip("this test started failing with the new change, based movementop issue") + def test_no_binop_rerun_transposed(self): return self._test_no_binop_rerun(lambda a,b: (a.T*b.T).T, lambda a,b: a*b) + def test_no_binop_rerun_mid_reshape(self): return self._test_no_binop_rerun(lambda a,b: (a*b).reshape(256)+a.reshape(256)) + + # currently non working tests + # def test_no_binop_rerun_preshape(self): return self._test_no_binop_rerun(lambda a,b: a.reshape(16, 16, 1)*b.reshape(16, 16, 1), lambda a,b: a*b) + #def test_no_binop_rerun_reduce(self): return self._test_no_binop_rerun(lambda a,b: (a*b).sum(), lambda a,b: (a*b).reshape(16, 16, 1).sum()) + #def test_no_binop_rerun_reduce_alt(self): return self._test_no_binop_rerun(lambda a,b: a.sum(1)+b[0], lambda a,b: a.sum(1).reshape(1,16)+b[0]) + +@unittest.skipUnless(Device.DEFAULT == "GPU", "Not Implemented") +class TestOptReduceLoop(unittest.TestCase): + def test_loop_left(self): + a = Tensor.randn(16, 16) + b = Tensor.randn(16, 16) + with CLCache() as cache: + t = a.sum(0) + b = t.reshape(16,1).expand(16,16).sum(0) + c = (t+b) + c.realize() + assert cache.count == 2, "loop left fusion broken" + + def test_loop_right(self): + a = Tensor.randn(16, 16) + b = Tensor.randn(16, 16) + with CLCache() as cache: + t = a.sum(0) + b = t.reshape(16,1).expand(16,16).sum(0) + c = (b+t) + c.realize() + assert cache.count == 2, "loop right fusion broken" + +@unittest.skipUnless(Device.DEFAULT == "GPU", "Not Implemented") +class TestOptWChild(unittest.TestCase): + @unittest.skip("this no longer happens, use realize") + def test_unrealized_child(self): + a = Tensor.randn(16, 16) + b = Tensor.randn(16, 16) + with CLCache() as cache: + c = (a*b).sum() + d = c+1 + e = c+2 # noqa: F841 + d.realize() + assert cache.count == 2, "don't fuse if you have children" + +@unittest.skipUnless(Device.DEFAULT == "GPU", "Not Implemented") +class TestOpt(unittest.TestCase): + def test_muladd(self): + a,b,c = [Tensor.randn(2,2).realize() for _ in range(3)] + na,nb,nc = a.numpy(),b.numpy(),c.numpy() + with CLCache(allowed=1): + d = a * b + c + d.realize() + np.testing.assert_allclose(d.numpy(), na*nb+nc, rtol=1e-5, atol=1e-7) + + def test_permute_was_pushed(self): + a = Tensor.randn(16, 16, 16) + with CLCache(2): + c = a.sum(2) + d = c.permute(1,0).contiguous() + d.realize() + np.testing.assert_allclose(a.numpy().sum(2).transpose(1,0), d.numpy(), rtol=1e-3, atol=1e-5) + + def test_permute_was_pushed_through_contract_reshape(self): + a = Tensor.randn(4, 4, 4, 4, 4) + with CLCache(2): + c = a.sum(-1) + d = c.reshape(16,16).permute(1,0).contiguous() + d.realize() + np.testing.assert_allclose(a.numpy().sum(-1).reshape(16,16).transpose(1,0), d.numpy(), rtol=1e-3, atol=1e-5) + + def test_permute_was_pushed_through_contractw1s_reshape(self): + a = Tensor.randn(4, 4, 4, 4, 4) + with CLCache(2): + c = a.sum(-1) + d = c.reshape(16,1,16).permute(2,1,0).contiguous() + d.realize() + np.testing.assert_allclose(a.numpy().sum(-1).reshape(16,1,16).transpose(2,1,0), d.numpy(), rtol=1e-3, atol=1e-5) + + def test_permute_was_pushed_through_expand_reshape(self): + a = Tensor.randn(16, 16, 16) + with CLCache(2): + c = a.sum(2) + d = c.reshape(4,4,4,4).permute(2,3,0,1).contiguous() + d.realize() + np.testing.assert_allclose(a.numpy().sum(2).transpose(1,0).reshape(4,4,4,4), d.numpy(), rtol=1e-3, atol=1e-5) + + def test_no_reduceop_rerun(self): + a = Tensor.randn(16, 16, 16) + with CLCache() as cache: + c = a.sum(2) + d = a.sum(2).permute(1,0) + c.realize() + d.realize() + cache_len = cache.count + np.testing.assert_allclose(c.numpy().transpose(1,0), d.numpy(), rtol=1e-3, atol=1e-5) + assert cache_len == 1, "reduceop was rerun!" + + def test_no_reduceop_rerun_alt(self): + a = Tensor.randn(16, 16, 16) + with CLCache() as cache: + c = a.sum(2).permute(1,0) + d = a.sum(2) + c.realize() + d.realize() + cache_len = cache.count + np.testing.assert_allclose(c.numpy(), d.numpy().transpose(1,0), rtol=1e-3, atol=1e-5) + assert cache_len == 1, "reduceop was rerun!" + + def test_expand_reduce_is_folded_on_same_axis(self): + with Context(FUSE_CONV_BW=1): + for axis in [0, 1]: + for n in [4, 8, 16]: + b = torch.ones(n, n).sum(axis).reshape(n, 1).expand(n, n).sum(axis) + with CLCache(allowed=2): + a = Tensor.ones(n, n).contiguous().sum(axis).reshape(n, 1).expand(n, n).sum(axis) + a.realize() + np.testing.assert_allclose(a.numpy(), b.numpy(), rtol=1e-3, atol=1e-5) + + def test_expand_reduce_is_folded_on_different_axes(self): + with Context(FUSE_CONV_BW=1): + axis1, axis2 = 0, 1 + for n in [4, 8, 16]: + b = torch.ones(n, n).sum(axis1).reshape(n, 1).expand(n, n).sum(axis2) + with CLCache(allowed=2): + a = Tensor.ones(n, n).contiguous().sum(axis1).reshape(n, 1).expand(n, n).sum(axis2) + a.realize() + np.testing.assert_allclose(a.numpy(), b.numpy(), rtol=1e-3, atol=1e-5) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_optim.py b/tinygrad_repo/test/external/external_test_optim.py new file mode 100644 index 000000000..622a0645e --- /dev/null +++ b/tinygrad_repo/test/external/external_test_optim.py @@ -0,0 +1,196 @@ +#!/usr/bin/env python +import unittest, math +import numpy as np +import tensorflow as tf +import tensorflow_addons as tfa +from tensorflow.python.ops import math_ops +from extra.lr_scheduler import LRSchedulerGroup + +from tinygrad.tensor import Tensor +from tinygrad.nn.optim import LAMB, LARS, SGD, OptimizerGroup, AdamW + +from test.external.mlperf_resnet.lars_optimizer import LARSOptimizer + +from examples.mlperf.lr_schedulers import PolynomialDecayWithWarmup, CosineAnnealingLRWithWarmup +from test.external.mlperf_resnet.lars_util import PolynomialDecayWithWarmup as PolynomialDecayWithWarmup_tf + +np.random.seed(1337) +x_init = np.random.randn(1,4).astype(np.float32) +W_init = np.random.randn(4,4).astype(np.float32) +m_init = np.random.randn(1,4).astype(np.float32) + +class TinyNet: + def __init__(self): + self.x = Tensor(x_init.copy(), requires_grad=True) + self.W = Tensor(W_init.copy(), requires_grad=True) + self.m = Tensor(m_init.copy()) + + def forward(self): + out = self.x.matmul(self.W).relu() + out = out.log_softmax(1) + out = out.mul(self.m).add(self.m).sum() + return out + +class TinyNetTF: + def __init__(self): + self.x = tf.Variable(x_init.copy(), trainable=True, name="x") + self.W = tf.Variable(W_init.copy(), trainable=True, name="W") + self.m = tf.constant(m_init.copy()) + + def forward(self): + out = tf.matmul(self.x, self.W) + out = tf.nn.relu(out) + out = tf.nn.log_softmax(out, axis=1) + out = tf.multiply(out, self.m) + self.m + out = tf.reduce_sum(out) + return out + +def step(optim, steps=1, kwargs={}, scheduler=None, schedopts=None, do_optim=True): + net = TinyNet() + optim = optim([net.x, net.W], **kwargs) + if scheduler is not None: scheduler = scheduler(optim, **schedopts) + lrs = [] + for _ in range(steps): + if do_optim: + out = net.forward() + optim.zero_grad() + out.backward() + lrs.append(optim.lr.item() if not isinstance(optim, OptimizerGroup) else optim.optimizers[0].lr.item()) + if do_optim: optim.step() + if scheduler is not None: scheduler.step() + return lrs, net.x.detach().numpy(), net.W.detach().numpy() + +def step_tf(optim, steps=1, kwargs={}, scheduler=None, schedopts=None, do_optim=True): + net = TinyNetTF() + if scheduler is not None: kwargs['lr'] = scheduler(**schedopts) + optim = optim(**kwargs) + lrs = [] + for _ in range(steps): + if do_optim: + with tf.GradientTape() as tape: + out = net.forward() + + lr_t = optim.learning_rate + # refer to test/external/mlperf_resnet/lars_optimizer.py:_prepare_local + if callable(lr_t): lr_t = lr_t(math_ops.cast(optim.iterations, tf.float32)) + lrs.append(lr_t) + + if do_optim: + grads = tape.gradient(out, [net.x, net.W]) + optim.apply_gradients(zip(grads, [net.x, net.W])) + # optim calls scheduler in tf + else: + optim._iterations.assign_add(1) + return lrs, net.x.numpy(), net.W.numpy() + +# skip list is skipping W +def create_tiny_lars(params, lr, skip_list=False): + if skip_list: return OptimizerGroup(LARS([params[0]], lr), SGD([params[1]], lr, classic=True, weight_decay=0., momentum=.9)) + return LARS(params, lr) +def create_tf_lars(lr, skip_list=False): return LARSOptimizer(lr, skip_list=["W"] if skip_list else None) + +def create_tiny_polylr(optim, initial_lr, end_lr, train_steps, warmup, power=2, skip_list=False): + assert power == 2 + if skip_list: return LRSchedulerGroup( + PolynomialDecayWithWarmup(optim[0], initial_lr, end_lr, train_steps, warmup, power), + PolynomialDecayWithWarmup(optim[1], initial_lr, end_lr, train_steps, warmup, power)) + return PolynomialDecayWithWarmup(optim, initial_lr, end_lr, train_steps, warmup, power) +def create_tf_polylr(initial_lr, end_lr, train_steps, warmup, power=2, skip_list=False): + assert power == 2 + return PolynomialDecayWithWarmup_tf(1, 1, train_steps, + initial_learning_rate=initial_lr, end_learning_rate=end_lr, warmup_epochs=warmup) + +class ExternalTestOptim(unittest.TestCase): + def setUp(self): + self.old_training = Tensor.training + Tensor.training = True + def tearDown(self): + Tensor.training = self.old_training + + def _test_optim(self, tinygrad_optim, tensorflow_optim, steps, opts, atol, rtol, tiny_sched=None, tf_sched=None, schedopts=None, do_optim=True): + for x,y in zip(step(tinygrad_optim, steps=steps, kwargs=opts, scheduler=tiny_sched, schedopts=schedopts, do_optim=do_optim), + step_tf(tensorflow_optim, steps=steps, kwargs=opts, scheduler=tf_sched, schedopts=schedopts, do_optim=do_optim)): + np.testing.assert_allclose(x, y, atol=atol, rtol=rtol) + + def _test_lamb(self, steps, opts, atol, rtol): self._test_optim(LAMB, tfa.optimizers.LAMB, steps, opts, atol, rtol) + def _test_lars(self, steps, opts, atol, rtol): self._test_optim(create_tiny_lars, create_tf_lars, steps, opts, atol, rtol) + def _test_lars_polylr(self, steps, opts, schedopts, atol, rtol, do_optim=True): + self._test_optim(create_tiny_lars, create_tf_lars, steps, opts, atol, rtol, + tiny_sched=create_tiny_polylr, tf_sched=create_tf_polylr, schedopts=schedopts, do_optim=do_optim) + + def test_lamb(self): self._test_lamb(1, {'lr': 0.001}, 1e-5, 0) + def test_lamb_high_lr(self): self._test_lamb(1, {'lr': 10}, 1e-5, 1e-5) + + def test_multistep_lamb(self): self._test_lamb(10, {'lr': 0.001}, 1e-5, 0) + def test_multistep_lamb_high_lr(self): self._test_lamb(10, {'lr': 10}, 1e-5, 3e-4) + + def test_lars(self): self._test_lars(1, {'lr': 0.01}, 1e-5, 0) + def test_lars_high_lr(self): self._test_lars(1, {'lr': 10}, 1e-5, 1e-5) + def test_multistep_lars(self): self._test_lars(10, {'lr': 0.001}, 1e-5, 0) + def test_multistep_lars_high_lr(self): self._test_lars(10, {'lr': 10}, 1e-5, 3e-4) + def test_lars_skip(self): self._test_lars(10, {'lr': 10, 'skip_list': True}, 1e-5, 3e-4) + def test_lars_skip_high_lr(self): self._test_lars(1, {'lr': 10, 'skip_list': True}, 1e-5, 1e-5) + def test_lars_skip_multistep(self): self._test_lars(10, {'lr': 0.001, 'skip_list': True}, 1e-5, 0) + def test_lars_skip_multistep_high_lr(self): self._test_lars(10, {'lr': 10, 'skip_list': True}, 1e-5, 3e-4) + + def test_lars_polylr(self): + self._test_lars_polylr(10, {'lr': 1.0}, { + 'initial_lr': 1.0, + 'end_lr': 1e-4, + 'train_steps': 10, + 'warmup': 3 + }, 1e-5, 1e-5) + def test_lars_polylr_large(self): + self._test_lars_polylr(100, {'lr': 10.0}, { + 'initial_lr': 10.0, + 'end_lr': 1e-5, + 'train_steps': 100, + 'warmup': 43 + }, 1e-5, 1e-5, do_optim=False) + def test_lars_polylr_skip(self): + self._test_lars_polylr(10, {'lr': 1.0, 'skip_list': True}, { + 'initial_lr': 1.0, + 'end_lr': 1e-4, + 'train_steps': 10, + 'warmup': 3, + 'skip_list': True + }, 1e-5, 1e-5) + + @unittest.skip("slow, but you can run this locally to check") + def test_lars_polylr_resnet(self): + train_files = 1_281_167 + BS = 624 + steps_per_epoch = train_files // BS + epochs = 45 + warmup_epochs = 5 + self._test_lars_polylr(steps_per_epoch * epochs, {'lr': 10.4}, { + 'initial_lr': 10.4, + 'end_lr': 1e-4, + # step counts for BS=624 EPOCHS=45 resnet + 'train_steps': steps_per_epoch * epochs, + 'warmup': steps_per_epoch * warmup_epochs, + }, 1e-5, 1e-5, do_optim=False) + + +class TestCosineAnnealingLRWithWarmup(unittest.TestCase): + # only tests the lr + def _test_lr(self, base_lr, end_lr, warmup_steps, decay_steps): + net = TinyNet() + optim = AdamW([net.W], lr=0.0) + tiny_lr = CosineAnnealingLRWithWarmup(optim, base_lr, end_lr, warmup_steps, decay_steps) + lr = [] + for _ in range(warmup_steps+decay_steps): + lr.append(optim.lr.item()) + tiny_lr.step() + # reimplemented in python + expected = [] + for i in range(warmup_steps): expected.append((i+1)/warmup_steps*base_lr) + for i in range(decay_steps): expected.append(end_lr+(base_lr-end_lr)*(1+math.cos((i+1)/decay_steps*math.pi))/2) + np.testing.assert_allclose(lr, expected, rtol=1e-5) + + def test_lr_0(self): self._test_lr(3e-4, 8e-5, 3, 5) + def test_lr_1(self): self._test_lr(3e-4, 8e-5, 10, 20) + def test_lr_llama3(self): self._test_lr(8e-5, 8e-7, 20, 100) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_speed_llama.py b/tinygrad_repo/test/external/external_test_speed_llama.py new file mode 100644 index 000000000..3d468e625 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_speed_llama.py @@ -0,0 +1,58 @@ +# NOTE: this only tests the speed of the LLaMA codegen, it doesn't actually run the net +import unittest, time +from examples.llama import Transformer, MODEL_PARAMS +from tinygrad.tensor import Tensor +from tinygrad import Device +from tinygrad.nn.state import get_state_dict +from tinygrad.device import Allocator, Compiled +from tinygrad.engine.realize import method_cache +from tinygrad.helpers import Profiling + +class FakeProgram: + def __init__(self, name:str, prg:bytes): pass + def __call__(self, *bufs, global_size, local_size, vals=(), wait=False): pass + +class FakeAllocator(Allocator[Compiled]): + def _alloc(self, sz, options): return None + def _copyin(self, dest, src:memoryview): pass + +class TestLLaMASpeed(unittest.TestCase): + def test_llama_compile(self): + backup_program = Device[Device.DEFAULT].runtime + backup_allocator = Device[Device.DEFAULT].allocator + backup_compiler = Device[Device.DEFAULT].compiler + Device[Device.DEFAULT].runtime = FakeProgram + Device[Device.DEFAULT].allocator = FakeAllocator(Device.default) + + print("testing llama python run time") + model = Transformer(**MODEL_PARAMS["1"]["7B"]["args"]) + print("built model") + # assign fake tensors to the values + for v in get_state_dict(model).values(): v.assign(Tensor.empty(*v.shape, dtype=v.dtype)) + print("assigned empty tensors, doing warmup") + + def run_llama(st, empty_method_cache=True): + if empty_method_cache: method_cache.clear() + tms = [time.perf_counter()] + for i in range(5): + model(Tensor([[1,2,3,4]]), i).realize() + tms.append(time.perf_counter()) + timings = [(tms[i+1]-tms[i])*1000 for i in range(len(tms)-1)] + print(f"{st:15s} mean runtime: {sum(timings)/len(timings):7.2f}ms, runs: ", ", ".join(f'{x:7.2f}' for x in timings)) + + run_llama("codegen(0)") + run_llama("codegen(1)") + + # test no compiler use for this + Device[Device.DEFAULT].compiler = None + run_llama("methodcache", False) + with Profiling(sort='time', frac=0.1, fn="/tmp/llama.prof", ts=5): + run_llama("profile", False) + + Device[Device.DEFAULT].runtime = backup_program + Device[Device.DEFAULT].allocator = backup_allocator + Device[Device.DEFAULT].compiler = backup_compiler + +if __name__ == '__main__': + TestLLaMASpeed().test_llama_compile() + #unittest.main() diff --git a/tinygrad_repo/test/external/external_test_speed_theoretical.py b/tinygrad_repo/test/external/external_test_speed_theoretical.py new file mode 100644 index 000000000..ea0f26042 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_speed_theoretical.py @@ -0,0 +1,48 @@ +import time, unittest +from tinygrad import Tensor, TinyJit, Device, dtypes +from tinygrad.helpers import getenv, GlobalCounters + +SZMAX = getenv("SZMAX", 10) +SZMIN = min(SZMAX, getenv("SZMIN", 10)) +def _test(tcount, fxn, dtype=dtypes.float): + print(f"**** testing {fxn.__name__} {dtype}") + allgbs = [] + for sz in range(SZMIN, SZMAX+1): + jfxn = TinyJit(fxn) + ts = [Tensor.zeros((2**sz)*1024*1024, dtype=dtype).contiguous().realize() for _ in range(tcount)] + tms = [] + for _ in range(10): + ts = [(x+1).realize() for x in ts] + Device.default.synchronize() + GlobalCounters.global_ops = 0 + GlobalCounters.global_mem = 0 + st = time.perf_counter() + jfxn(*ts).nbytes() + Device.default.synchronize() + tms.append(time.perf_counter() - st) + ops, mem = GlobalCounters.global_ops, GlobalCounters.global_mem + gflops = ops*1e-9/min(tms) + gbs = mem*1e-9/min(tms) + print(f"{ts[0].nbytes()/(1024*1024):10.0f} MB, {min(tms)*1e3:6.2f} ms {gbs:10.2f} GB/s {gflops:10.2f} GFLOPS {str(ts[0].shape):20s}") + allgbs.append(gbs) + return max(allgbs) + +MEMBW = getenv("MEMBW", 10) +class TestRamBandwidth(unittest.TestCase): + def test_add(self): self.assertGreater(_test(2, Tensor.add), MEMBW) + def test_exp(self): self.assertGreater(_test(1, Tensor.exp), MEMBW) + def test_sum(self): self.assertGreater(_test(1, Tensor.sum), MEMBW) + +# ratio between MEM and FLOPS < 1000 +# NOTE: On AMD, (x*x)+1 gets ~30 TFLOPS, (x*x)+3 gets ~60 TFLOPS +def flopsmax(x): + for _ in range(500): x = (x*x)+3 + return x + +class TestFlops(unittest.TestCase): + def test_flops_int8(self): _test(1, flopsmax, dtypes.int8) + def test_flops_fp16(self): _test(1, flopsmax, dtypes.half) + def test_flops_fp32(self): _test(1, flopsmax) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_tlsf.py b/tinygrad_repo/test/external/external_test_tlsf.py new file mode 100644 index 000000000..6db41f038 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_tlsf.py @@ -0,0 +1,78 @@ +import unittest +from tinygrad.runtime.support.memory import TLSFAllocator + +class TestTLSFAllocator(unittest.TestCase): + def setUp(self): + self.allocator = TLSFAllocator(1024, block_size=16) + + def test_basic_alloc_free(self): + addr1 = self.allocator.alloc(32) + self.assertEqual(addr1, 0) + + addr2 = self.allocator.alloc(64) + self.assertEqual(addr2, 32) + + self.allocator.free(addr1) + addr3 = self.allocator.alloc(32) + self.assertEqual(addr3, 0) + + def test_block_size_alignment(self): + addr1 = self.allocator.alloc(20) + addr2 = self.allocator.alloc(35) + + self.assertEqual(addr1 % 16, 0) + self.assertEqual(addr2 % 16, 0) + + def test_merge_blocks(self): + addr1 = self.allocator.alloc(32) + addr2 = self.allocator.alloc(32) + self.allocator.alloc(32) + + self.allocator.free(addr1) + self.allocator.free(addr2) + addr4 = self.allocator.alloc(64) + self.assertEqual(addr4, addr1) + + def test_split_blocks(self): + addr1 = self.allocator.alloc(128) + self.allocator.free(addr1) + + addr2 = self.allocator.alloc(32) + self.assertEqual(addr2, addr1) + + addr3 = self.allocator.alloc(32) + self.assertEqual(addr3, addr1 + 32) + + def test_out_of_memory(self): + with self.assertRaises(MemoryError): + self.allocator.alloc(2048) + + def test_fragmentation_handling(self): + addrs = [] + for _ in range(5): + addrs.append(self.allocator.alloc(32)) + + # Free alternate blocks + for i in range(0, len(addrs), 2): + self.allocator.free(addrs[i]) + + def test_custom_start_address(self): + allocator = TLSFAllocator(1024, start_addr=1000) + addr1 = allocator.alloc(32) + self.assertEqual(addr1, 1000) + + addr2 = allocator.alloc(64) + self.assertEqual(addr2, 1032) + + def test_block_tracking(self): + addr1 = self.allocator.alloc(32) + addr2 = self.allocator.alloc(64) + + self.assertTrue(addr1 in [addr - self.allocator.start_addr for addr in self.allocator.blocks]) + self.assertTrue(addr2 in [addr - self.allocator.start_addr for addr in self.allocator.blocks]) + + self.allocator.free(addr1) + self.assertTrue(addr1 in [addr - self.allocator.start_addr for addr in self.allocator.blocks]) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_train_gpt2.py b/tinygrad_repo/test/external/external_test_train_gpt2.py new file mode 100644 index 000000000..2cac47941 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_train_gpt2.py @@ -0,0 +1,55 @@ +# ruff: noqa: E501 +import unittest + +from tinygrad.uop.ops import UOp, Ops +from tinygrad.opt.search import Opt, OptOps +from tinygrad.dtype import dtypes +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.shape.view import View +from tinygrad.opt.kernel import Kernel + +from test.external.fuzz_linearizer import run_linearizer + +class TestTrainGpt2Kernel(unittest.TestCase): + def test_1(self): + # kernel 244 + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(206045184), arg=0, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1024, 50304, 1), strides=(51511296, 50304, 1, 0), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(3145728), arg=1, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1024, 50304, 768), strides=(786432, 768, 0, 1), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(38633472), arg=2, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1024, 50304, 768), strides=(0, 0, 768, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) + + opts = [Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=3), Opt(op=OptOps.LOCAL, axis=0, arg=2)] + kernel = Kernel(ast) + kernel.apply_opts(opts) + run_linearizer(kernel) + + def test_2(self): + # kernel 254 + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(3145728), arg=0, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1024, 1, 768), strides=(786432, 768, 0, 1), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(38633472), arg=1, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1024, 50304, 768), strides=(0, 0, 768, 1), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(205852672), arg=2, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1024, 50304, 768), strides=(51463168, 50257, 1, 0), offset=0, mask=((0, 4), (0, 1024), (0, 50257), (0, 768)), contiguous=False),)), src=()),)),)),)),)),)) + + opts = [Opt(op=OptOps.LOCAL, axis=1, arg=16), Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=2, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=3, arg=4)] + kernel = Kernel(ast) + kernel.apply_opts(opts) + run_linearizer(kernel) + +if __name__ == "__main__": + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/external/external_test_usb_asm24.py b/tinygrad_repo/test/external/external_test_usb_asm24.py new file mode 100644 index 000000000..3df81b28e --- /dev/null +++ b/tinygrad_repo/test/external/external_test_usb_asm24.py @@ -0,0 +1,73 @@ +import unittest, time +from tinygrad.runtime.support.usb import ASM24Controller +from tinygrad.helpers import Timing +from tinygrad import Tensor, Device +import numpy as np + +class TestASMController(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.ctrl = ASM24Controller() + + def test_write_and_read(self): + base = 0xF000 + data = b"hello!" + self.ctrl.write(base, data) + out = self.ctrl.read(base, len(data)) + self.assertEqual(out, data) + + def test_scsi_write_and_read_from_f000(self): + payload = bytes([0x5B]) * 4096 + self.ctrl.scsi_write(payload, lba=0) + back = self.ctrl.read(0xF000, len(payload)) + self.assertEqual(back, payload) + + def test_scsi_write_speed_4k(self): + payload = bytes([0x5A]) * 4096 + start = time.perf_counter() + self.ctrl.scsi_write(payload, lba=0) + dur_ms = (time.perf_counter() - start) * 1000 + print(f"scsi_write 4K took {dur_ms:.3f} ms") + + def test_read_speed_4k(self): + payload = bytes([0xA5]) * 4096 + self.ctrl.write(0xF000, payload) + start = time.perf_counter() + out = self.ctrl.read(0xF000, 4096) + dur_ms = (time.perf_counter() - start) * 1000 + print(f"read 4K took {dur_ms:.3f} ms") + self.assertEqual(out, payload) + +class TestDevCopySpeeds(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.sz = 512 + cls.dev = Device["AMD"] + if not cls.dev.is_usb(): raise unittest.SkipTest("only test this on USB devices") + + def testCopyCPUtoDefault(self): + for _ in range(10): + t = Tensor.ones(self.sz, self.sz, device="CPU").contiguous().realize() + with Timing(f"copyin of {t.nbytes()/1e6:.2f} MB: ", on_exit=lambda ns: f" @ {t.nbytes()/ns * 1e3:.2f} MB/s"): # noqa: F821 + t.to(Device.DEFAULT).realize() + Device[Device.DEFAULT].synchronize() + del t + + def testCopyDefaulttoCPU(self): + t = Tensor.ones(self.sz, self.sz).contiguous().realize() + for _ in range(10): + with Timing(f"copyout of {t.nbytes()/1e6:.2f} MB: ", on_exit=lambda ns: f" @ {t.nbytes()/ns * 1e3:.2f} MB/s"): + t.to('CPU').realize() + + def testValidateCopies(self): + t = Tensor.randn(self.sz, self.sz, device="CPU").contiguous().realize() + x = t.to(Device.DEFAULT).realize() + Device[Device.DEFAULT].synchronize() + + y = x.to('CPU').realize() + + np.testing.assert_equal(t.numpy(), y.numpy()) + del x, y, t + +if __name__ == "__main__": + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/external/external_test_valid_remove.py b/tinygrad_repo/test/external/external_test_valid_remove.py new file mode 100644 index 000000000..9734b1e39 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_valid_remove.py @@ -0,0 +1,121 @@ +# ruff: noqa: E501 +import unittest + +from tinygrad import Device +from tinygrad.uop.ops import UOp, Ops +from tinygrad.opt.search import Opt, OptOps +from tinygrad.dtype import dtypes +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.shape.view import View +from tinygrad.opt.kernel import Kernel + +class TestOpenpilotValidhack(unittest.TestCase): + def test_valid_removal(self): + Device.DEFAULT = "GPU" + + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.imagef((64, 1024, 4)), arg=0, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 64, 128, 1, 1, 8, 4, 1, 1, 1, 1), strides=(0, 4096, 32, 0, 0, 4, 1, 0, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MAX, dtypes.float, arg=None, src=( + x5:=UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 8, 9, 10)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.imagef((128, 768, 4)), arg=1, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 1, 1, 1, 1, 3, 1, 4, 4, 130, 4, 258), strides=(0, 0, 0, 0, 0, 4, 0, 1, 0, 3072, 0, 12), offset=-3084, mask=((0, 1), (0, 1), (0, 1), (0, 1), (0, 1), (0, 3), (0, 1), (0, 4), (0, 4), (1, 129), (0, 4), (1, 257)), contiguous=False), View(shape=(1, 64, 128, 1, 1, 8, 4, 3, 4, 3, 3), strides=(0, 2064, 2, 0, 0, 0, 0, 2146560, 536640, 135192, 259), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.imagef((8, 108, 4)), arg=2, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 64, 128, 1, 1, 8, 4, 3, 4, 3, 3), strides=(0, 0, 0, 0, 0, 432, 1, 48, 4, 144, 16), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=3, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 64, 128, 1, 1, 8, 4, 1, 1, 1, 1), strides=(0, 0, 0, 0, 0, 4, 1, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + x19:=UOp(Ops.CONST, dtypes.float, arg=0.0, src=( + x20:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 64, 128, 1, 1, 8, 4, 1, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MAX, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.CONST, dtypes.float, arg=1.0, src=( + x20,)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.EXP2, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + x5, + UOp(Ops.CONST, dtypes.float, arg=1.4426950408889634, src=( + x20,)),)),)), + x29:=UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( + x20,)),)),)), + x19,)), + x29,)),)),)),)) + + opts = [Opt(op=OptOps.UPCAST, axis=3, arg=4), Opt(op=OptOps.UNROLL, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.NOLOCALS, axis=None, arg=None)] + kernel = Kernel(ast) + + kernel.apply_opts(opts) + + p = kernel.to_program() + print(p.src) + + def test_const_idx(self): + Device.DEFAULT = "GPU" + + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.imagef((10, 128, 4)), arg=0, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 512, 1), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.imagef((1, 128, 4)), arg=1, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=0, mask=((0, 1), (0, 1), (0, 512)), contiguous=False),)), src=()),)), + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + x18:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=2, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=48128, mask=((0, 1), (1, 2), (0, 512)), contiguous=False),)), src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + x18, + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=45568, mask=((0, 1), (2, 3), (0, 512)), contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + x18, + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=43008, mask=((0, 1), (3, 4), (0, 512)), contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + x18, + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=40448, mask=((0, 1), (4, 5), (0, 512)), contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + x18, + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=37888, mask=((0, 1), (5, 6), (0, 512)), contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + x18, + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=35328, mask=((0, 1), (6, 7), (0, 512)), contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + x18, + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=32768, mask=((0, 1), (7, 8), (0, 512)), contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + x18, + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=30208, mask=((0, 1), (8, 9), (0, 512)), contiguous=False),)), src=()),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.imagef((1, 128, 4)), arg=3, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 10, 512), strides=(0, 0, 1), offset=0, mask=((0, 1), (9, 10), (0, 512)), contiguous=False),)), src=()),)),)),)),)),)) + + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.NOLOCALS, axis=None, arg=None)] + kernel = Kernel(ast) + + kernel.apply_opts(opts) + + p = kernel.to_program() + # ((idx1<1)?read_imagef(data1, smp, (int2)(idx0,0)):(float4)(0.0f,0.0f,0.0f,0.0f)) + print(p.src) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_whisper_librispeech.py b/tinygrad_repo/test/external/external_test_whisper_librispeech.py new file mode 100644 index 000000000..264bb3f06 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_whisper_librispeech.py @@ -0,0 +1,83 @@ +import unittest +import torch +import tqdm +import torchaudio +import pathlib +import jiwer +import os +import numpy as np +from whisper.normalizers import EnglishTextNormalizer +from examples.whisper import init_whisper, transcribe_waveform + +class TestWhisperLibriSpeech(unittest.TestCase): + # reference WERs determined by running https://github.com/openai/whisper/blob/main/notebooks/LibriSpeech.ipynb + # the values should be consistent with the paper D.1.1 https://cdn.openai.com/papers/whisper.pdf#page=22 + # tinygrad WERs do not perfectly match due to what seem to be precision differences vs torch + def test_en_tiny(self): + run_evaluation("tiny.en", 0.056629001883239174, 0.05655609406528749) + + def test_tiny(self): + run_evaluation("tiny", 0.0771121409407306, 0.07558413638335187) + + def test_en_base(self): + run_evaluation("base.en", 0.041412520064205455, 0.04271408904897505) + + def test_en_small(self): + run_evaluation("small.en", 0.03369011117172363, 0.030531615969223228) + +def run_evaluation(model_name, tinygrad_expected_wer, reference_wer): + dataset = LibriSpeech() + batch_size=16 + loader = torch.utils.data.DataLoader(dataset, batch_size=batch_size) + + model, enc = init_whisper(model_name, batch_size=batch_size) + + hypotheses = [] + references = [] + + for audio, texts in tqdm.tqdm(loader): + transcriptions = transcribe_waveform(model, enc, audio.numpy(), truncate=True) + hypotheses.extend(transcriptions) + references.extend(texts) + + normalizer = EnglishTextNormalizer() + normalized_hypotheses = [normalizer(text) for text in hypotheses] + normalized_references = [normalizer(text) for text in references] + wer = jiwer.wer(normalized_hypotheses, normalized_references) + + np.testing.assert_almost_equal(wer, tinygrad_expected_wer) + print(f'tinygrad WER {wer} vs reference WER {reference_wer}') + del model, enc + +class LibriSpeech(torch.utils.data.Dataset): + def __init__(self): + folder = pathlib.Path(__file__).parent.parent.parent / "extra" / "datasets" / "librispeech" + if not os.path.exists(folder): + os.makedirs(folder) + + self.dataset = torchaudio.datasets.LIBRISPEECH( + root=folder, + url="test-clean", + download=True, + ) + + def __len__(self): + return len(self.dataset) + + def __getitem__(self, item): + audio, sample_rate, text, _, _, _ = self.dataset[item] + assert sample_rate == 16000 + return pad_or_trim_tensor(audio[0]), text + +def pad_or_trim_tensor(tensor, target_len=480000): + curr_len = len(tensor) + if curr_len == target_len: + return tensor + elif curr_len < target_len: + return torch.cat((tensor, torch.zeros(target_len - curr_len))) + else: + return tensor[:target_len] + + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_yolo.py b/tinygrad_repo/test/external/external_test_yolo.py new file mode 100644 index 000000000..f28f23aa5 --- /dev/null +++ b/tinygrad_repo/test/external/external_test_yolo.py @@ -0,0 +1,32 @@ +import unittest +from pathlib import Path + +import cv2 + +from examples.yolov3 import Darknet, infer, show_labels +from tinygrad.helpers import fetch + +chicken_img = cv2.imread(str(Path(__file__).parent.parent / 'models/efficientnet/Chicken.jpg')) +car_img = cv2.imread(str(Path(__file__).parent.parent / 'models/efficientnet/car.jpg')) + +class TestYOLO(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.model = Darknet(fetch("https://raw.githubusercontent.com/pjreddie/darknet/master/cfg/yolov3.cfg").read_bytes()) + print("Loading weights file (237MB). This might take a while…") + cls.model.load_weights("https://pjreddie.com/media/files/yolov3.weights") + + @classmethod + def tearDownClass(cls): + del cls.model + + def test_chicken(self): + labels = show_labels(infer(self.model, chicken_img), confidence=0.56) + self.assertEqual(labels, ["bird"]) + + def test_car(self): + labels = show_labels(infer(self.model, car_img)) + self.assertEqual(labels, ["car"]) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_test_yolov8.py b/tinygrad_repo/test/external/external_test_yolov8.py new file mode 100644 index 000000000..5506fae7f --- /dev/null +++ b/tinygrad_repo/test/external/external_test_yolov8.py @@ -0,0 +1,73 @@ +import numpy as np +from examples.yolov8 import YOLOv8, get_variant_multiples, preprocess, label_predictions, postprocess +from tinygrad import Tensor +import unittest +import io, cv2 +import onnxruntime as ort +import ultralytics +from tinygrad.nn.state import safe_load, load_state_dict +from tinygrad.helpers import fetch + +class TestYOLOv8(unittest.TestCase): + def test_all_load_weights(self): + for variant in ['n', 's', 'm', 'l', 'x']: + depth, width, ratio = get_variant_multiples(variant) + TinyYolov8 = YOLOv8(w=width, r=ratio, d=depth, num_classes=80) + state_dict = safe_load(fetch(f'https://gitlab.com/r3sist/yolov8_weights/-/raw/master/yolov8{variant}.safetensors')) + load_state_dict(TinyYolov8, state_dict) + print(f'successfully loaded weights for yolov{variant}') + + def test_predictions(self): + test_image_urls = ['https://raw.githubusercontent.com/ultralytics/yolov5/master/data/images/bus.jpg', 'https://www.aljazeera.com/wp-content/uploads/2022/10/2022-04-28T192650Z_1186456067_UP1EI4S1I0P14_RTRMADP_3_SOCCER-ENGLAND-MUN-CHE-REPORT.jpg'] + variant = 'n' + depth, width, ratio = get_variant_multiples(variant) + TinyYolov8 = YOLOv8(w=width, r=ratio, d=depth, num_classes=80) + state_dict = safe_load(fetch(f'https://gitlab.com/r3sist/yolov8_weights/-/raw/master/yolov8{variant}.safetensors')) + load_state_dict(TinyYolov8, state_dict) + + for i in range(len(test_image_urls)): + img = cv2.imdecode(np.frombuffer(fetch(test_image_urls[i]).read_bytes(), np.uint8), 1) + test_image = preprocess([img]) + predictions = TinyYolov8(test_image) + labels = label_predictions(predictions.numpy()) + assert labels == {5: 1, 0: 4, 11: 1} if i == 0 else labels == {0: 12, 29: 1, 32: 1} + + def test_forward_pass_torch_onnx(self): + variant = 'n' + weights_location = fetch(f'https://gitlab.com/r3sist/yolov8_weights/-/raw/master/yolov8{variant}.safetensors') + weights_location_pt = fetch(f'https://github.com/ultralytics/assets/releases/download/v0.0.0/yolov8{variant}.pt', name=f"yolov8{variant}.pt") # it needs the pt extension # noqa: E501 + weights_location_onnx = weights_location_pt.parent / f"yolov8{variant}.onnx" + + # the ultralytics export prints a lot of unneccesary things + if not weights_location_onnx.is_file(): + model = ultralytics.YOLO(model=weights_location_pt, task='Detect') + model.export(format="onnx",imgsz=[640, 480]) + + depth, width, ratio = get_variant_multiples(variant) + TinyYolov8 = YOLOv8(w=width, r=ratio, d=depth, num_classes=80) + state_dict = safe_load(weights_location) + load_state_dict(TinyYolov8, state_dict) + + image_location = [np.frombuffer(io.BytesIO(fetch('https://raw.githubusercontent.com/ultralytics/yolov5/master/data/images/bus.jpg').read_bytes()).read(), np.uint8)] # noqa: E501 + orig_image = [cv2.imdecode(image_location[0], 1)] + + input_image = preprocess(orig_image) + + onnx_session = ort.InferenceSession(weights_location_onnx) + onnx_input_name = onnx_session.get_inputs()[0].name + onnx_output_name = onnx_session.get_outputs()[0].name + onnx_output = onnx_session.run([onnx_output_name], {onnx_input_name: input_image.numpy()}) + + tiny_output = TinyYolov8(input_image).numpy() + onnx_output = postprocess(Tensor(onnx_output[0])).numpy() + #invalid boxes are multiplied by zero in postprocess + onnx_output = onnx_output[onnx_output[:, 4] != 0] + tiny_output = tiny_output[tiny_output[:, 4] != 0] + + # currently rtol is 0.025 because there is a 1-2% difference in our predictions + # because of the zero padding in SPPF module (line 280) maxpooling layers rather than the -infinity in torch. + # This difference does not make a difference "visually". + np.testing.assert_allclose(onnx_output, tiny_output, atol=5e-4, rtol=0.025) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/external_uop_gc.py b/tinygrad_repo/test/external/external_uop_gc.py new file mode 100644 index 000000000..538cbc3bc --- /dev/null +++ b/tinygrad_repo/test/external/external_uop_gc.py @@ -0,0 +1,70 @@ +import gc +from tinygrad import Tensor, UOp, Device +from tinygrad.shape.shapetracker import views_to_indexed_uops +from tinygrad.engine.realize import method_cache, get_program + +def uops_allocated(): return sum([isinstance(x, UOp) for x in gc.get_objects()]) +def print_uops(): + for x in gc.get_objects(): + if isinstance(x, UOp): print(x) + +def start(): pass +def single_tensor(): Tensor([2]) +def two_plus_two(): Tensor([2])+Tensor([2]) +def two_plus_two_schedule(): (Tensor([2])+Tensor([2])).schedule() +def two_plus_two_kernel(): + si = (Tensor([2])+Tensor([2])).schedule()[-1] + get_program(si.ast, Device.default.renderer) +def two_plus_two_linearize(): + si = (Tensor([2])+Tensor([2])).schedule()[-1] + get_program(si.ast, Device.default.renderer) +def two_plus_two_realize(): (Tensor([2])+Tensor([2])).realize() +def two_plus_two_item(): (Tensor([2])+Tensor([2])).item() +def gradient_test(): + x = Tensor.eye(3, requires_grad=True) + y = Tensor([[2.0,0,-2.0]], requires_grad=True) + z = y.matmul(x).sum() + z.backward() +def realized_eye(): + Tensor.eye(3, requires_grad=True).realize() +def realized_list(): + Tensor([[2.0,0,-2.0]], requires_grad=True).realize() +def kernel_matmul(): + x = Tensor.eye(3, requires_grad=True) + y = Tensor([[2.0,0,-2.0]], requires_grad=True) + z = y.matmul(x) + si = z.schedule()[-1] + get_program(si.ast, Device.default.renderer) +def realized_matmul(): + x = Tensor.eye(3, requires_grad=True) + y = Tensor([[2.0,0,-2.0]], requires_grad=True) + z = y.matmul(x) + Tensor.realize(z) +def realized_gradient(): + x = Tensor.eye(3, requires_grad=True) + y = Tensor([[2.0,0,-2.0]], requires_grad=True) + z = y.matmul(x).sum() + z.backward() + Tensor.realize(x, y, z, x.grad, y.grad) +tests = [start, single_tensor, two_plus_two, two_plus_two_schedule, two_plus_two_kernel, + two_plus_two_linearize, two_plus_two_realize, two_plus_two_item, gradient_test, + realized_eye, realized_list, kernel_matmul, realized_matmul, realized_gradient] + +if __name__ == "__main__": + gc.disable() + start_uops = uops_allocated() + # there's a few consts created as default values + print_uops() + for t in tests: + t() + + # these caches will keep uops alive + method_cache.clear() + views_to_indexed_uops.cache_clear() + + new_uops = uops_allocated() + gc.collect() + new_uops_gc = uops_allocated() + print(f"{t.__name__:30s}: {new_uops:3d} -> {new_uops_gc:3d}") + assert new_uops == start_uops + #print_uops() diff --git a/tinygrad_repo/test/external/fuzz_fast_idiv.py b/tinygrad_repo/test/external/fuzz_fast_idiv.py new file mode 100644 index 000000000..c7bf90b84 --- /dev/null +++ b/tinygrad_repo/test/external/fuzz_fast_idiv.py @@ -0,0 +1,33 @@ +import random +from z3 import Int, Solver, sat +from tinygrad import dtypes, Device +from tinygrad.uop.ops import UOp, Ops, UPat, graph_rewrite, PatternMatcher +from tinygrad.codegen.devectorizer import fast_idiv +random.seed(42) + +z3_renderer = PatternMatcher([ + (UPat((Ops.DEFINE_VAR, Ops.SPECIAL), name="x"), lambda x: UOp(Ops.NOOP, arg=x.arg[0])), + # Because fast_idiv only works for non-negative integers we can emulate machine arithmetic with modulo operations. + (UPat(Ops.SHR, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"(({x.src[0].arg}/(2**{x.src[1].arg}))%{dtypes.max(x.dtype)+1})")), + (UPat(Ops.MUL, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"(({x.src[0].arg}*{x.src[1].arg})%{dtypes.max(x.dtype)+1})")), + (UPat((Ops.CONST, Ops.VCONST), name="x"), lambda x: UOp(Ops.NOOP, arg=str(x.arg))), + (UPat(Ops.CAST, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"{x.src[0].arg}")), +]) + +def render(self) -> str: + ret = graph_rewrite(self.simplify(), z3_renderer) + return ret.arg if ret.op is Ops.NOOP else str(ret) + +if __name__ == "__main__": + x = Int('x') + for _ in range(10_000): + dt = random.choice(dtypes.ints) + u = UOp(Ops.DEFINE_VAR, dt, arg=('x', 0, random.randint(1, dtypes.max(dt))), src=()) + d = random.randint(1, max(1, u.arg[2])) + + expr = fast_idiv(Device[Device.DEFAULT].renderer, u, d) + if expr is None: continue + solver = Solver() + solver.add(x>=u.arg[1], x<=u.arg[2]) + if solver.check(eval(render(expr)) != x/d) == sat: + assert False, f"Failed: {render(expr)} != x//{d} at x={solver.model()[x]}\nx={u}\nd={d}" diff --git a/tinygrad_repo/test/external/fuzz_graph.py b/tinygrad_repo/test/external/fuzz_graph.py new file mode 100644 index 000000000..4e1d492ea --- /dev/null +++ b/tinygrad_repo/test/external/fuzz_graph.py @@ -0,0 +1,128 @@ +import random, ctypes +import numpy as np +from tinygrad.device import Buffer, Device +from tinygrad.helpers import Context, getenv, from_mv +from tinygrad.dtype import dtypes +from tinygrad.tensor import Tensor, _to_np_dtype +from tinygrad.engine.realize import ExecItem, BufferXfer, get_runner +from tinygrad.engine.jit import apply_graph_to_jit + +BUF_LEN = getenv("BUF_LEN", 128) + +cached_prgs = {} +def gen_prg(device, inputs_cnt): + if (device, inputs_cnt) in cached_prgs: return cached_prgs[(device, inputs_cnt)] + + with Context(DEBUG=0): + fst = [Tensor.randn(BUF_LEN, dtype=dtypes.int).realize() for i in range(inputs_cnt)] + s = fst[0] + for i in range(1, inputs_cnt): s = s.bitwise_xor(fst[i]) + + si = s.schedule()[-1] + prg = get_runner(device, si.ast) + cached_prgs[(device, inputs_cnt)] = prg + return prg + +def alloc_rawbuffer(device, fill=False): + rawbuf = Buffer(device, BUF_LEN, dtypes.int).ensure_allocated() + if fill: + with Context(DEBUG=0): + data = np.random.randint(-10000, 10000, size=rawbuf.size, dtype=_to_np_dtype(rawbuf.dtype)) + rawbuf.copyin(Tensor(data).realize().uop.base.realized.as_buffer()) + return rawbuf + +def gen_kernel_ji(device, deps): + assert len(deps) >= 2 + out = alloc_rawbuffer(device) + prg = gen_prg(device, len(deps)) + return ExecItem(prg, [out] + deps) + +def gen_copy_ji(device, deps): + assert len(deps) == 1 + out = alloc_rawbuffer(device) + prg = BufferXfer(deps[0].nbytes, device, deps[0].device) + return ExecItem(prg, [out] + deps) + +def gen_graph(): + input_buffers = [] + all_buffers = [] + jis = [] + + last_n_deps = getenv("LAST_N_DEPS", 0) + + kernel_count = random.randint(2, getenv("MAX_KERNELS", 128)) + for i in range(kernel_count): + target_device_id = random.randint(0, getenv("MAX_DEVICES", 6) - 1) + target_device = f"{Device.DEFAULT}:{target_device_id}" + is_copy = random.randint(0, 10) < 3 + + if is_copy: + deps_pool = [buf for buf in all_buffers[-last_n_deps:] if buf.device != target_device] + if len(deps_pool) == 0: deps = [] + else: deps = random.sample(deps_pool, 1) + else: + deps_pool = [buf for buf in all_buffers[-last_n_deps:] if buf.device == target_device] + deps_count = random.randint(0, min(getenv("MAX_DEPS_COUNT", 6), len(deps_pool))) + if deps_count == 0: deps = [] + else: deps = random.sample(deps_pool, deps_count) + + if len(deps) == 0 or (not is_copy and len(deps) < 2): + buf = alloc_rawbuffer(target_device, fill=True) + input_buffers.append(buf) + all_buffers.append(buf) + elif is_copy: + jis.append(gen_copy_ji(target_device, deps)) + all_buffers.append(jis[-1].bufs[0]) + else: + jis.append(gen_kernel_ji(target_device, deps)) + all_buffers.append(jis[-1].bufs[0]) + + return jis, all_buffers, input_buffers + +def run_jit(jis, all_buffers, input_buffers, var_vals): + with Context(DEBUG=0): + for rawbuf in all_buffers: + if rawbuf in input_buffers: continue + mv = memoryview(bytearray(rawbuf.size * rawbuf.dtype.itemsize)) + ctypes.memset(from_mv(mv), 0, len(mv)) + rawbuf.copyin(mv) + + for ei in jis: ei.run(var_vals, jit=True) + + with Context(DEBUG=0): + res_buffers = [] + for rawbuf in all_buffers: res_buffers.append(rawbuf.as_buffer()) + return res_buffers + +def fuzz_graph(jis, all_buffers, input_buffers): + ground_thruth_bufs = run_jit(jis, input_buffers, all_buffers, {}) + ground_truth_np = [np.frombuffer(x, _to_np_dtype(all_buffers[i].dtype)) for i,x in enumerate(ground_thruth_bufs)] + + for _ in range(getenv("FUZZ_GRAPH_SPLIT_RUNS", 64)): + max_split_points = len(jis) // 3 + split_points = random.randint(0, min(max_split_points, getenv("FUZZ_GRAPH_MAX_SPLITS", 8))) + split = [0] + for i in range(split_points - 1): + split.append(random.randint(split[-1] + 2, len(jis) - 2 * (max_split_points - i))) + split.append(len(jis)) + + graphed_jit = [] + for sp in range(len(split)-1): + graphed_jit += apply_graph_to_jit(jis[split[sp]:split[sp+1]], [], {}) + + for _ in range(getenv("FUZZ_GRAPH_SPLIT_RETRY_RUNS", 4)): + test_bufs = run_jit(graphed_jit, input_buffers, all_buffers, {}) + test_bufs_np = [np.frombuffer(x, _to_np_dtype(all_buffers[i].dtype)) for i,x in enumerate(test_bufs)] + for i in range(len(ground_thruth_bufs)): np.testing.assert_equal(ground_truth_np[i], test_bufs_np[i]) + +if __name__ == "__main__": + SEED = getenv("SEED", 42) + random.seed(SEED) + np.random.seed(SEED) + + next_graph_id = 0 + for i in range(getenv("ITERS", 1000)): + print("Running graph", next_graph_id) + jis, all_buffers, input_buffers = gen_graph() + fuzz_graph(jis, all_buffers, input_buffers) + next_graph_id += 1 diff --git a/tinygrad_repo/test/external/fuzz_kfd.py b/tinygrad_repo/test/external/fuzz_kfd.py new file mode 100644 index 000000000..29c286838 --- /dev/null +++ b/tinygrad_repo/test/external/fuzz_kfd.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +import random +from tqdm import trange +from typing import List +from tinygrad import Device +from tinygrad.runtime.ops_amd import AMDDevice, HWQueue + +if __name__ == "__main__": + dev: List[AMDDevice] = [Device[f"KFD:{i}"] for i in range(6)] + print(f"got {len(dev)} devices") + + buffers = [(rd:=random.choice(dev), rd.allocator.alloc(random.randint(1, 10000))) for i in range(100)] + + for _ in trange(100000): + d1, b1 = random.choice(buffers) + d2, b2 = random.choice(buffers) + d1._gpu_map(b2) + q = HWQueue() + q.signal(sig:=AMDDevice._alloc_signal(10)) + qc = HWQueue() + qc.wait(sig) + qc.copy(b1.va_addr, b2.va_addr, min(b1.size, b2.size)) + d1.completion_signal.value = 1 + qc.signal(d1.completion_signal) + qc.submit(d1) + q.wait(d1.completion_signal) + q.submit(d1) + AMDDevice._wait_on(d1.completion_signal.event_id) diff --git a/tinygrad_repo/test/external/fuzz_linearizer.py b/tinygrad_repo/test/external/fuzz_linearizer.py new file mode 100644 index 000000000..b9711b8d8 --- /dev/null +++ b/tinygrad_repo/test/external/fuzz_linearizer.py @@ -0,0 +1,338 @@ +import random, traceback, ctypes, argparse, os +from typing import Any +import numpy as np +from collections import defaultdict +from extra.optimization.helpers import load_worlds, ast_str_to_lin, kern_str_to_lin + +# We need to insert ioctl before opening devices. +if os.getenv("VALIDATE_HCQ", 0) != 0: + try: + import extra.nv_gpu_driver.nv_ioctl + from tinygrad import Device + _, _ = Device["NV"], Device["CUDA"] + except Exception: pass + + try: + import extra.qcom_gpu_driver.opencl_ioctl + from tinygrad import Device + _, _ = Device["QCOM"], Device["GPU"] + except Exception: pass + +from tinygrad import Tensor, Device, dtypes +from tinygrad.tensor import _to_np_dtype +from tinygrad.opt.kernel import Kernel +from tinygrad.opt.kernel import Opt, OptOps +from tinygrad.opt.search import get_kernel_actions, bufs_from_lin +from tinygrad.engine.realize import CompiledRunner +from tinygrad.helpers import getenv, from_mv, prod, colored, Context, DEBUG, Timing +from tinygrad.uop.ops import UOp, Ops +from tinygrad.device import is_dtype_supported + +def on_linearizer_will_run(): pass +def on_linearizer_did_run(): pass +def compare_states(x, y): return (True, "") + +if getenv("VALIDATE_HCQ"): + if Device.DEFAULT == "NV": + print("VALIDATE_HCQ: Comparing NV to CUDA") + import extra.nv_gpu_driver.nv_ioctl + validate_device = Device["CUDA"] + on_linearizer_will_run = extra.nv_gpu_driver.nv_ioctl.before_launch + on_linearizer_did_run = extra.nv_gpu_driver.nv_ioctl.collect_last_launch_state + compare_states = extra.nv_gpu_driver.nv_ioctl.compare_launch_state + elif Device.DEFAULT == "QCOM": + print("VALIDATE_HCQ: Comparing QCOM to GPU") + import extra.qcom_gpu_driver.opencl_ioctl + validate_device = Device["GPU"] + on_linearizer_will_run = extra.qcom_gpu_driver.opencl_ioctl.before_launch + on_linearizer_did_run = extra.qcom_gpu_driver.opencl_ioctl.collect_last_launch_state + compare_states = extra.qcom_gpu_driver.opencl_ioctl.compare_launch_state + else: + print(colored("VALIDATE_HCQ options is ignored", 'red')) + +def tuplize_uops(uops:list[UOp]) -> tuple: + return tuple([(x.op, x.dtype, tuple(uops.index(x) for x in x.src), x.arg) for x in uops]) + +def get_fuzz_rawbufs(lin): + rawbufs = bufs_from_lin(lin) + + # Reallocate output buffer with additional area to detect out-of-bounds writes. + RED_AREA_SIZE = 1024 + # setting output # TODO: multi-output kernel + rawbufs[0] = get_fuzz_rawbuf_like(rawbufs[0], zero=True, size=rawbufs[0].size+RED_AREA_SIZE) + # setting inputs + with Context(DEBUG=0): + for rawbuf in rawbufs[1:]: + if dtypes.is_unsigned(rawbuf.dtype): + data = np.random.randint(0, 100, size=rawbuf.size, dtype=_to_np_dtype(rawbuf.dtype)) + elif dtypes.is_int(rawbuf.dtype): + data = np.random.randint(-100, 100, size=rawbuf.size, dtype=_to_np_dtype(rawbuf.dtype)) + elif rawbuf.dtype == dtypes.bool: + data = np.random.choice([True, False], size=rawbuf.size) + elif rawbuf.dtype == dtypes.half: + data = np.random.uniform(-1, 1, size=rawbuf.size).astype(dtype=_to_np_dtype(rawbuf.dtype)) + else: + data = np.random.uniform(-10, 10, size=rawbuf.size).astype(dtype=_to_np_dtype(rawbuf.dtype)) + rawbuf.copyin(Tensor(data, device=lin.opts.device).realize().uop.base.realized.as_buffer()) + return rawbufs + +def get_fuzz_rawbuf_like(old_rawbuf, zero=False, copy=False, size=None, force_device=None): + rawbuf = type(old_rawbuf)(force_device or old_rawbuf.device, old_rawbuf.size if size is None else size, old_rawbuf.dtype).allocate() + if copy: + with Context(DEBUG=0): rawbuf.copyin(old_rawbuf.as_buffer()) + elif zero: + with Context(DEBUG=0): + mv = memoryview(bytearray(rawbuf.size * rawbuf.dtype.itemsize)) + ctypes.memset(from_mv(mv), 0, len(mv)) + rawbuf.copyin(mv) + return rawbuf + +def run_linearizer(lin: Kernel, rawbufs=None, var_vals=None) -> tuple[str, Any]: # (error msg, run state) + if rawbufs is None: rawbufs = bufs_from_lin(lin) + if var_vals is None: var_vals = {v: v.min for v in lin.vars} + + # TODO: images needs required_optimization + try: + prg = CompiledRunner(lin.to_program()) + except KeyboardInterrupt: raise + except Exception: + traceback.print_exc() + return "COMPILE_ERROR", None + + if getenv("VALIDATE_HCQ"): on_linearizer_will_run() + try: + prg(rawbufs, var_vals, wait=True) + except KeyboardInterrupt: raise + except Exception: + traceback.print_exc() + return "EXEC_ERROR", None + + if getenv("VALIDATE_HCQ"): run_state = on_linearizer_did_run() + else: run_state = None + + return "PASS", run_state + +def compare_linearizer(lin: Kernel, rawbufs=None, var_vals=None, ground_truth=None, rtol=1e-2, atol=1e-2): + # TODO: for bfloat16 it compiles linearizer, but it does not run because numpy cannot generate bf16 buffer. + has_bf16 = any(b.dtype.base == dtypes.bfloat16 for b in lin.membufs) + + # TODO: raise specific fuzzing errors instead of str, and propagate the error message + try: + if rawbufs is None: + rawbufs = get_fuzz_rawbufs(lin) + else: + rawbufs[0] = get_fuzz_rawbuf_like(rawbufs[0], zero=True) # get a new output buffer + except KeyboardInterrupt: raise + except BaseException: + return ("RAWBUFS_ERROR", rawbufs, var_vals, ground_truth, None) + + if var_vals is None: + # TODO: handle symbolic max case + var_vals = {v: random.randint(v.vmin, v.vmax) for v in lin.ast.variables()} + + if ground_truth is None and not has_bf16: + unoptimized = Kernel(lin.ast) + if run_linearizer(unoptimized, rawbufs, var_vals)[0] != "PASS": + return ("BASELINE_ERROR", rawbufs, var_vals, ground_truth, None) + ground_truth = np.frombuffer(rawbufs[0].as_buffer(), _to_np_dtype(rawbufs[0].dtype)).copy() + + rawbufs[0] = get_fuzz_rawbuf_like(rawbufs[0], zero=True) # get a new output buffer + run_msg, run_state = run_linearizer(lin, rawbufs, var_vals) + if run_msg != "PASS": return (run_msg, rawbufs, var_vals, ground_truth, run_state) + + try: + if not has_bf16: + result = np.frombuffer(rawbufs[0].as_buffer(), _to_np_dtype(rawbufs[0].dtype)) + np.testing.assert_allclose(result, ground_truth, rtol=rtol, atol=atol) + except KeyboardInterrupt: raise + except AssertionError as e: + if DEBUG >= 2: + print(f"COMPARE_ERROR details: {e}") + if getenv("DEBUG_VALUES") > 0: + mismatch_indices = np.where(~np.isclose(result, ground_truth, rtol=rtol, atol=atol)) + mismatched_result = result[mismatch_indices] + mismatched_ground_truth = ground_truth[mismatch_indices] + for i, idx in enumerate(mismatch_indices[0]): + print(f"mismatch at {idx=}: result={mismatched_result[i]} <> ground_truth={mismatched_ground_truth[i]}") + return ("COMPARE_ERROR", rawbufs, var_vals, ground_truth, run_state) + + return ("PASS", rawbufs, var_vals, ground_truth, run_state) + +def fuzz_linearizer(lin: Kernel, rtol=1e-2, atol=1e-2, opts_list=None): + SEED = getenv("SEED", 42) + random.seed(SEED) + np.random.seed(SEED) + print(lin.ast) + print(lin.colored_shape()) + seen_uops = {} + last_lins = [lin] + failures:defaultdict[str, list[tuple[tuple[UOp, ...], list[Opt]]]] = defaultdict(list) + rawbufs, var_vals, ground_truth, validate_rawbufs = None, None, None, None + + FUZZ_ALL_ACTIONS = getenv("FUZZ_ALL_ACTIONS", 0) + FUZZ_MAX_SIZE = getenv("FUZZ_MAX_SIZE", 0) + FUZZ_IGNORE_SIMPLE_OPS = getenv("FUZZ_IGNORE_SIMPLE_OPS", 1) + + if FUZZ_MAX_SIZE > 0 and prod(lin.full_shape) > FUZZ_MAX_SIZE: + print("skipping large kernel") + return failures + if FUZZ_IGNORE_SIMPLE_OPS and _is_simple(lin): + print("skipping simple kernel") + return failures + + test_depth = 1 if opts_list is not None else getenv("DEPTH", 1 if FUZZ_ALL_ACTIONS else 10) + for depth in range(test_depth): + next_lins = [] + for lin in last_lins: + if opts_list is None: actions = get_kernel_actions(lin, include_0=False) + else: + actions = {} + for oi,opts in enumerate(opts_list): + lin2 = lin.copy() + for o in opts: lin2.apply_opt(o) + actions[oi] = lin2 + + if not actions: continue + if depth == 0 and getenv("FUZZ_REQUIRE_TC", 0): + tc_acts = {i: k for k in actions.values() if k.applied_opts[0].op == OptOps.TC} + if len(tc_acts) == 0: return failures + else: actions = tc_acts + + test_lins = list(actions.values()) + if FUZZ_ALL_ACTIONS: print(f"testing {lin.applied_opts=} with {len(actions)} actions") + elif opts_list is None: test_lins = [random.choice(test_lins)] + + for test_lin in test_lins: + if not FUZZ_ALL_ACTIONS and test_lin.applied_opts: print(f"applied opts: {test_lin.applied_opts}") + + # stop if kernel uops repeat + try: tuops = tuplize_uops(test_lin.linearize().uops) + except KeyboardInterrupt: raise + except BaseException as e: + print(test_lin.ast) + print(test_lin.applied_opts) + print(e) + failures["LINEARIZE_ERROR"].append((test_lin.ast, test_lin.applied_opts)) + continue + + if tuops in seen_uops: continue + seen_uops[tuops] = tuple(test_lin.applied_opts) + + if not FUZZ_ALL_ACTIONS: print(test_lin.colored_shape()) + + (msg, rawbufs, var_vals, ground_truth, state1) = compare_linearizer(test_lin, rawbufs, var_vals, ground_truth, rtol=rtol, atol=atol) + if state1 is not None and validate_device is not None: + validate_lin = test_lin.copy() + validate_lin.opts = validate_device.renderer + if validate_rawbufs is None: + validate_rawbufs = [get_fuzz_rawbuf_like(x, copy=True, force_device=validate_device.device) for x in rawbufs] + (_msg, _, _, _, state2) = compare_linearizer(validate_lin, validate_rawbufs, var_vals, ground_truth, rtol=rtol, atol=atol) + + if _msg != "PASS": failures[f"VALIDATE_DEV_{_msg}"].append((validate_lin.ast, validate_lin.applied_opts)) + + ok, err_msg = compare_states(state1, state2) + if not ok: failures["HCQ_COMPARE_FAILURE"].append((err_msg, test_lin.ast, test_lin.applied_opts, state1, state2)) + + if msg != "PASS": + print(test_lin.ast) + print(test_lin.applied_opts) + print(msg) + failures[msg].append((test_lin.ast, test_lin.applied_opts)) + continue + + next_lins.append(test_lin) + + last_lins = next_lins + if FUZZ_ALL_ACTIONS: print(f"depth={depth} total_lins={len(last_lins)} {failures=}") + return failures + +def _is_simple(lin: Kernel) -> bool: + if len(lin.ast.src) > 1: return False + ast:UOp = lin.ast.src[0] + if ast.src[0].op is Ops.CAST and ast.src[0].src[0].op is Ops.LOAD: return True + return False + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description="Run a fuzz testing on one or more kernels", formatter_class=argparse.ArgumentDefaultsHelpFormatter) + parser.add_argument("--ast", type=str, default=None, help="the ast for the kernel to be optimized") + parser.add_argument("--file", type=str, default=None, help="a file containing asts to be optimized, one per line") + parser.add_argument("--beamreplay", type=str, default=None, help="replay asts and opts got from beam with CAPTURE_BEAM") + parser.add_argument("--logfile", type=str, default=None, help="a file containing a tuple of ast and applied_opts, one per line") + parser.add_argument("--expected-failures", type=int, default=0, help="the number of expected failed kernels") + parser.add_argument("--rtol", type=float, default=1e-2, help="relative tolerance for numerical comparison") + parser.add_argument("--atol", type=float, default=1e-2, help="absolute tolerance for numerical comparison") + args = parser.parse_args() + + opts_list = None + if args.ast is not None: + print("loaded AST from CLI") + ast_strs = [args.ast] + elif args.file is not None: + print(f"loading ASTs from file '{args.file}'") + with open(args.file, 'r') as file: + ast_strs = file.readlines() + elif args.beamreplay is not None: + print(f"loading BEAM replay from file '{args.beamreplay}'") + with open(args.beamreplay, 'r') as file: fdata = file.readlines() + ast_strs, opts_list = [x.split(' :: ')[0] for x in fdata if not x.startswith("#")], [x.split(' :: ')[1] for x in fdata if not x.startswith("#")] + + # dedup ast_strs and opts_list + dct = defaultdict(list) + for i in range(len(ast_strs)): dct[ast_strs[i]].append(eval(opts_list[i])) + ast_strs_items = list(dct.keys()) + opts_list = [dct[c] for c in ast_strs_items] + elif args.logfile is not None: + print(f"loading ASTs from LOGKERNS file '{args.file}'") + with open(args.logfile, 'r') as file: + kern_strs = file.readlines() + test_lins = [kern_str_to_lin(kern_str) for kern_str in kern_strs] + ast_strs = [f"{lin.ast}" for lin in test_lins] + else: + print("loading ASTs from world") + ast_strs = load_worlds(filter_reduce=False, filter_novariable=False) + + print(f"{len(ast_strs)=}") + tested = 0 + failed_ids = [] + failures = defaultdict(list) + seen_ast_strs = set() + + try: + for i, ast in enumerate(ast_strs[:getenv("FUZZ_N", len(ast_strs))]): + if (nth := getenv("FUZZ_NTH", -1)) != -1 and i != nth: continue + if getenv("FUZZ_IMAGEONLY") and "dtypes.image" not in ast: continue + if "dtypes.image" in ast and Device.DEFAULT not in {"GPU", "QCOM"}: continue # IMAGE is only for GPU + if ast in seen_ast_strs: continue + seen_ast_strs.add(ast) + + lin = ast_str_to_lin(ast) + if not all(is_dtype_supported(buf.dtype) for buf in lin.bufs): + print("skipping kernel due to not supported dtype") + continue + + with Timing(f"tested ast {i}: "): + tested += 1 + fuzz_failures = fuzz_linearizer(lin, rtol=args.rtol, atol=args.atol, opts_list=(opts_list[i] if opts_list else None)) + if fuzz_failures: failed_ids.append(i) + for k, v in fuzz_failures.items(): + for f in v: + failures[k].append(f) + except KeyboardInterrupt: print(colored("STOPPING...", 'red')) + + for msg, errors in failures.items(): + for i, payload in enumerate(errors): + print(f"{msg} {i} kernel: {payload}") # easier to use with output with verify_kernel.py + + print(f"{tested=}") + if failures: + print(f"{failed_ids=}") + for msg, errors in failures.items(): + print(f"{msg}: {len(errors)}") + if len(failed_ids) == args.expected_failures: + print(colored(f"{len(failed_ids)} failed as expected", "yellow")) + if len(failed_ids) != args.expected_failures: + print(colored(f"failed on {len(failed_ids)} kernels, expected {args.expected_failures}", "red")) + # TODO: fix this + # raise RuntimeError(f"failed on {len(failed_ids)} kernels, expected {args.expected_failures}") + else: + print(colored("all passed", "green")) diff --git a/tinygrad_repo/test/external/fuzz_shape_ops.py b/tinygrad_repo/test/external/fuzz_shape_ops.py new file mode 100644 index 000000000..f60e58e91 --- /dev/null +++ b/tinygrad_repo/test/external/fuzz_shape_ops.py @@ -0,0 +1,87 @@ +from __future__ import annotations +import unittest +from math import prod + +from hypothesis import assume, given, settings, strategies as st +from hypothesis.extra import numpy as stn + +import numpy as np +import torch +from tinygrad import Tensor +from tinygrad.helpers import CI, getenv + + +settings.register_profile(__file__, settings.default, + max_examples=100 if CI else 250, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) + + +# torch wraparound for large numbers +st_int32 = st.integers(-2147483648, 2147483647) + +@st.composite +def st_shape(draw) -> tuple[int, ...]: + s = draw(stn.array_shapes(min_dims=0, max_dims=6, + min_side=0, max_side=128)) + assume(prod(s) <= 1024 ** 2) + assume(prod([d for d in s if d]) <= 1024 ** 4) + return s + +def tensors_for_shape(s:tuple[int, ...]) -> tuple[torch.tensor, Tensor]: + x = np.arange(prod(s)).reshape(s) + return torch.from_numpy(x), Tensor(x) + +def apply(tor, ten, tor_fn, ten_fn=None): + ok = True + try: tor = tor_fn(tor) + except: tor, ok = None, not ok # noqa: E722 + try: ten = ten_fn(ten) if ten_fn is not None else tor_fn(ten) + except: ten, ok = None, not ok # noqa: E722 + return tor, ten, ok + +class TestShapeOps(unittest.TestCase): + @settings.get_profile(__file__) + @given(st_shape(), st_int32, st.one_of(st_int32, st.lists(st_int32))) + def test_split(self, s:tuple[int, ...], dim:int, sizes:int|list[int]): + tor, ten = tensors_for_shape(s) + tor, ten, ok = apply(tor, ten, lambda t: t.split(sizes, dim)) + assert ok + if tor is None and ten is None: return + + assert len(tor) == len(ten) + assert all([np.array_equal(tor.numpy(), ten.numpy()) for (tor, ten) in zip(tor, ten)]) + + @settings.get_profile(__file__) + @given(st_shape(), st_int32, st_int32) + def test_chunk(self, s:tuple[int, ...], dim:int, num:int): + # chunking on a 0 dim is cloning and leads to OOM if done unbounded. + assume((0 <= (actual_dim := len(s)-dim if dim < 0 else dim) < len(s) and s[actual_dim] > 0) or + (num < 16)) + + tor, ten = tensors_for_shape(s) + tor, ten, ok = apply(tor, ten, lambda t: t.chunk(num, dim)) + assert ok + if tor is None and ten is None: return + + assert len(tor) == len(ten) + assert all([np.array_equal(tor.numpy(), ten.numpy()) for (tor, ten) in zip(tor, ten)]) + + @settings.get_profile(__file__) + @given(st_shape(), st_int32) + def test_squeeze(self, s:tuple[int, ...], dim:int): + tor, ten = tensors_for_shape(s) + tor, ten, ok = apply(tor, ten, lambda t: t.squeeze(dim)) + assert ok + if tor is None and ten is None: return + assert np.array_equal(tor.numpy(), ten.numpy()) + + @settings.get_profile(__file__) + @given(st_shape(), st_int32) + def test_unsqueeze(self, s:tuple[int, ...], dim:int): + tor, ten = tensors_for_shape(s) + tor, ten, ok = apply(tor, ten, lambda t: t.unsqueeze(dim)) + assert ok + if tor is None and ten is None: return + assert np.array_equal(tor.numpy(), ten.numpy()) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/fuzz_shapetracker.py b/tinygrad_repo/test/external/fuzz_shapetracker.py new file mode 100644 index 000000000..ba11fa1eb --- /dev/null +++ b/tinygrad_repo/test/external/fuzz_shapetracker.py @@ -0,0 +1,61 @@ +import random +from tinygrad.helpers import DEBUG, getenv +from test.unit.test_shapetracker import CheckingShapeTracker + +def do_permute(st): + perm = list(range(0, len(st.shape))) + random.shuffle(perm) + perm = tuple(perm) + if DEBUG >= 1: print("st.permute(", perm, ")") + st.permute(perm) + +def do_pad(st): + c = random.randint(0, len(st.shape)-1) + pad = tuple((random.randint(0,2), random.randint(0,2)) if i==c else (0,0) for i in range(len(st.shape))) + if DEBUG >= 1: print("st.pad(", pad, ")") + st.pad(pad) + +def do_reshape_split_one(st): + c = random.randint(0, len(st.shape)-1) + poss = [n for n in [1,2,3,4,5] if st.shape[c]%n == 0] + spl = random.choice(poss) + shp = st.shape[0:c] + (st.shape[c]//spl, spl) + st.shape[c+1:] + if DEBUG >= 1: print("st.reshape(", shp, ")") + st.reshape(shp) + +def do_reshape_combine_two(st): + if len(st.shape) < 2: return + c = random.randint(0, len(st.shape)-2) + shp = st.shape[:c] + (st.shape[c] * st.shape[c+1], ) + st.shape[c+2:] + if DEBUG >= 1: print("st.reshape(", shp, ")") + st.reshape(shp) + +def do_shrink(st): + c = random.randint(0, len(st.shape)-1) + while 1: + shrink = tuple((random.randint(0,s), random.randint(0,s)) if i == c else (0,s) for i,s in enumerate(st.shape)) + if all(x= 1: print("st.shrink(", shrink, ")") + st.shrink(shrink) + +def do_flip(st): + flip = tuple(random.random() < 0.5 for _ in st.shape) + if DEBUG >= 1: print("st.flip(", flip, ")") + st.flip(flip) + +def do_expand(st): + c = [i for i,s in enumerate(st.shape) if s==1] + if len(c) == 0: return + c = random.choice(c) + expand = tuple(random.choice([2,3,4]) if i==c else s for i,s in enumerate(st.shape)) + if DEBUG >= 1: print("st.expand(", expand, ")") + st.expand(expand) + +shapetracker_ops = [do_permute, do_pad, do_shrink, do_reshape_split_one, do_reshape_combine_two, do_flip, do_expand] + +if __name__ == "__main__": + random.seed(42) + for _ in range(getenv("CNT", 200)): + st = CheckingShapeTracker((random.randint(2, 10), random.randint(2, 10), random.randint(2, 10))) + for i in range(8): random.choice(shapetracker_ops)(st) + st.assert_same() diff --git a/tinygrad_repo/test/external/fuzz_shapetracker_math.py b/tinygrad_repo/test/external/fuzz_shapetracker_math.py new file mode 100644 index 000000000..c7364ae3e --- /dev/null +++ b/tinygrad_repo/test/external/fuzz_shapetracker_math.py @@ -0,0 +1,46 @@ +import random +from tinygrad.helpers import getenv, DEBUG, colored, trange +from tinygrad.shape.shapetracker import ShapeTracker +from test.external.fuzz_shapetracker import shapetracker_ops +from test.external.fuzz_shapetracker import do_permute, do_reshape_split_one, do_reshape_combine_two, do_flip, do_pad +from test.unit.test_shapetracker_math import st_equal, MultiShapeTracker + +def fuzz_plus() -> tuple[ShapeTracker, ShapeTracker]: + m = MultiShapeTracker([ShapeTracker.from_shape((random.randint(1, 10), random.randint(1, 10), random.randint(1, 10)))]) + for _ in range(4): random.choice(shapetracker_ops)(m) + backup = m.sts[0] + m.sts.append(ShapeTracker.from_shape(m.sts[0].shape)) + for _ in range(4): random.choice(shapetracker_ops)(m) + st_sum = backup + m.sts[1] + return m.sts[0], st_sum + +# shrink and expand aren't invertible, and stride is only invertible in the flip case +invertible_shapetracker_ops = [do_permute, do_reshape_split_one, do_reshape_combine_two, do_flip, do_pad] + +def fuzz_invert() -> tuple[ShapeTracker, ShapeTracker]: + start = ShapeTracker.from_shape((random.randint(1, 10), random.randint(1, 10), random.randint(1, 10))) + m = MultiShapeTracker([start]) + for _ in range(8): random.choice(invertible_shapetracker_ops)(m) + inv = m.sts[0].invert(start.shape) + st_sum = (m.sts[0] + inv) if inv else None + return start, st_sum + +if __name__ == "__main__": + if seed:=getenv("SEED"): random.seed(seed) + total = getenv("CNT", 1000) + for fuzz in [globals()[f'fuzz_{x}'] for x in getenv("FUZZ", "invert,plus").split(",")]: + same_but_neq = 0 + for _ in trange(total, desc=f"{fuzz}"): + st1, st2 = fuzz() + eq = st_equal(st1, st2) + if getenv("CHECK_NEQ") and eq and st1.simplify() != st2.simplify(): + print(colored("same but unequal", "yellow")) + print(st1.simplify()) + print(st2.simplify()) + same_but_neq += 1 + if DEBUG >= 1: + print(f"EXP: {st1}") + print(f"GOT: {st2}") + print(colored("****", "green" if eq else "red")) + if not eq: exit(0) + if getenv("CHECK_NEQ"): print(f"same but unequal {same_but_neq}/{total} = {(same_but_neq/total)*100:.2f}%") diff --git a/tinygrad_repo/test/external/fuzz_shapetracker_size.py b/tinygrad_repo/test/external/fuzz_shapetracker_size.py new file mode 100644 index 000000000..dc76f3aec --- /dev/null +++ b/tinygrad_repo/test/external/fuzz_shapetracker_size.py @@ -0,0 +1,13 @@ +from tinygrad.shape.shapetracker import ShapeTracker +from test.external.fuzz_shapetracker import shapetracker_ops as st_ops +from test.unit.test_shapetracker_math import MultiShapeTracker +from tinygrad.helpers import getenv +import random + +random.seed(getenv("SEED", 42)) +for i in range(getenv("CNT", 2000)): + if getenv("DEBUG", 0) >= 1: print() + N = random.randint(1, 10000) + mst = MultiShapeTracker([ShapeTracker.from_shape((N,))]) # st_ops don't mutate regular shapetrackers for some reason + for j in range(20): random.choice(st_ops)(mst) + assert mst.sts[0].real_size() <= N, f"{N=}, real_size={mst.sts[0].real_size()}, st={mst.sts[0]}" diff --git a/tinygrad_repo/test/external/fuzz_symbolic.py b/tinygrad_repo/test/external/fuzz_symbolic.py new file mode 100644 index 000000000..41970a932 --- /dev/null +++ b/tinygrad_repo/test/external/fuzz_symbolic.py @@ -0,0 +1,92 @@ +import random, operator +import z3 +from tinygrad import Variable, dtypes +from tinygrad.uop.ops import UOp, graph_rewrite +from tinygrad.uop.spec import z3_renderer +from tinygrad.helpers import DEBUG, Context + +seed = random.randint(0, 100) +print(f"Seed: {seed}") +random.seed(seed) + +unary_ops = [lambda a:a+random.randint(-4, 4), lambda a: a*random.randint(-4, 4), + lambda a: a//random.randint(1, 9), lambda a: a%random.randint(1, 9), + lambda a:a.maximum(random.randint(-10, 10)), lambda a:a.minimum(random.randint(-10, 10))] +binary_ops = [lambda a,b: a+b, lambda a,b: a*b, lambda a,b:a.maximum(b), lambda a,b:a.minimum(b)] +comp_ops = [operator.lt, operator.le, operator.gt, operator.ge] + +def random_or_sub_expression_int(depth, expr): + sub_expr = random.choice([e for e in expr.toposort() if e.dtype is not dtypes.bool]) + return random.choice([random_int_expr(depth-1), sub_expr]) + +def random_int_expr(depth=10): + if depth <= 0: return random.choice(v) + expr1 = random_int_expr(depth-1) + + # we give more weight to arithmatic ops than to minimum and maximum + ops = [ + lambda: random.choices(unary_ops, weights=[4, 4, 4, 4, 1, 1])[0](expr1), + # for the second operand its either another random exprssion or some subexpression of the first operand + lambda: random.choices(binary_ops, [8, 1, 1, 1])[0](expr1, random_or_sub_expression_int(depth-1, expr1)), + lambda: random_bool_expr(3, random_or_sub_expression_int(depth-1, expr1)).where(expr1, random_or_sub_expression_int(depth-1, expr1)), + ] + # we give weight proportional to the amount of ops in each branch + return random.choices(ops, weights=[6, 4, 1])[0]() + +def random_bool_expr(depth=10, expr1=None): + if depth == 0: return True + if expr1 is None: expr1 = random_int_expr(depth-1) + expr2 = random.choice([random_or_sub_expression_int(depth-1, expr1), UOp.const(dtypes.int, random.randint(-10, 10))]) + return random.choice(comp_ops)(expr1, expr2) + + +if __name__ == "__main__": + skipped = 0 + for i in range(10000): + if i % 1000 == 0: + print(f"Running test {i}") + upper_bounds = [*list(range(1, 10)), 16, 32, 64, 128, 256] + u1 = Variable("v1", 0, random.choice(upper_bounds)) + u2 = Variable("v2", 0, random.choice(upper_bounds)) + u3 = Variable("v3", 0, random.choice(upper_bounds)) + v = [u1,u2,u3] + expr = random_int_expr(6) + + with Context(CORRECT_DIVMOD_FOLDING=1): + simplified_expr = expr.simplify() + + solver = z3.Solver() + solver.set(timeout=5000) # some expressions take very long verify, but its very unlikely they actually return sat + z3_sink = graph_rewrite(expr.sink(simplified_expr, u1, u2, u3), z3_renderer, ctx=(solver, {})) + z3_expr, z3_simplified_expr = z3_sink.src[0].arg, z3_sink.src[1].arg + check = solver.check(z3_simplified_expr != z3_expr) + if check == z3.unknown and DEBUG>=1: + skipped += 1 + print("Skipped due to timeout or interrupt:\n" + + f"v1=Variable(\"{u1.arg[0]}\", {u1.arg[1]}, {u1.arg[2]})\n" + + f"v2=Variable(\"{u2.arg[0]}\", {u2.arg[1]}, {u2.arg[2]})\n" + + f"v3=Variable(\"{u3.arg[0]}\", {u3.arg[1]}, {u3.arg[2]})\n" + + f"expr = {expr.render(simplify=False)}\n") + elif check == z3.sat: + m = solver.model() + v1, v2, v3 = z3_sink.src[2].arg, z3_sink.src[3].arg, z3_sink.src[4].arg + n1, n2, n3 = m[v1], m[v2], m[v3] + u1_val, u2_val, u3_val = u1.const_like(n1.as_long()), u2.const_like(n2.as_long()), u3.const_like(n3.as_long()) + with Context(CORRECT_DIVMOD_FOLDING=1): + num = expr.simplify().substitute({u1:u1_val, u2:u2_val, u3:u3_val}).ssimplify() + rn = expr.substitute({u1:u1_val, u2:u2_val, u3:u3_val}).ssimplify() + if num==rn: print("z3 found a mismatch but the expressions are equal!!") + assert False, f"mismatched {expr.render()} at v1={m[v1]}; v2={m[v2]}; v3={m[v3]} = {num} != {rn}\n" +\ + "Reproduce with:\n" +\ + f"v1=Variable(\"{u1.arg[0]}\", {u1.arg[1]}, {u1.arg[2]})\n" +\ + f"v2=Variable(\"{u2.arg[0]}\", {u2.arg[1]}, {u2.arg[2]})\n" +\ + f"v3=Variable(\"{u3.arg[0]}\", {u3.arg[1]}, {u3.arg[2]})\n" +\ + f"expr = {expr}\n" +\ + f"v1_val, v2_val, v3_val = UOp.const(dtypes.int, {n1.as_long()}), UOp.const(dtypes.int, {n2.as_long()})," +\ + f"UOp.const(dtypes.int, {n3.as_long()})\n" +\ + "num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify()\n" +\ + "rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify()\n" +\ + "assert num==rn, f\"{num} != {rn}\"\n" + + if DEBUG >= 2: print(f"validated {expr.render()}") + print(f"Skipped {skipped} expressions due to timeout") diff --git a/tinygrad_repo/test/external/graph_batchnorm.py b/tinygrad_repo/test/external/graph_batchnorm.py new file mode 100644 index 000000000..59e3b7961 --- /dev/null +++ b/tinygrad_repo/test/external/graph_batchnorm.py @@ -0,0 +1,61 @@ +import unittest +from tinygrad.nn.state import get_parameters +from tinygrad.tensor import Tensor +from tinygrad.nn import Conv2d, BatchNorm2d, optim + +def model_step(lm): + with Tensor.train(): + x = Tensor.ones(8,12,128,256, requires_grad=False) + optimizer = optim.SGD(get_parameters(lm), lr=0.001) + loss = lm.forward(x).sum() + optimizer.zero_grad() + loss.backward() + del x,loss + optimizer.step() + +class TestBatchnorm(unittest.TestCase): + def test_conv(self): + class LilModel: + def __init__(self): + self.c = Conv2d(12, 32, 3, padding=1, bias=False) + def forward(self, x): + return self.c(x).relu() + lm = LilModel() + model_step(lm) + + def test_two_conv(self): + class LilModel: + def __init__(self): + self.c = Conv2d(12, 32, 3, padding=1, bias=False) + self.c2 = Conv2d(32, 32, 3, padding=1, bias=False) + def forward(self, x): + return self.c2(self.c(x)).relu() + lm = LilModel() + model_step(lm) + + def test_two_conv_bn(self): + class LilModel: + def __init__(self): + self.c = Conv2d(12, 24, 3, padding=1, bias=False) + self.bn = BatchNorm2d(24, track_running_stats=False) + self.c2 = Conv2d(24, 32, 3, padding=1, bias=False) + self.bn2 = BatchNorm2d(32, track_running_stats=False) + def forward(self, x): + x = self.bn(self.c(x)).relu() + return self.bn2(self.c2(x)).relu() + lm = LilModel() + model_step(lm) + + def test_conv_bn(self): + class LilModel: + def __init__(self): + self.c = Conv2d(12, 32, 3, padding=1, bias=False) + self.bn = BatchNorm2d(32, track_running_stats=False) + def forward(self, x): + return self.bn(self.c(x)).relu() + lm = LilModel() + model_step(lm) + + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/mlperf_bert/external_benchmark_bert.py b/tinygrad_repo/test/external/mlperf_bert/external_benchmark_bert.py new file mode 100644 index 000000000..b23abf5e1 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_bert/external_benchmark_bert.py @@ -0,0 +1,102 @@ +import unittest, time + +from tinygrad import Tensor, TinyJit, GlobalCounters, Device +from tinygrad.helpers import getenv, Context +from tinygrad.nn.optim import LAMB +from tinygrad.nn.state import get_parameters +from tinygrad.engine.realize import run_schedule + +from extra.models import bert + +bs = getenv("BS", 16) +seq_len = getenv("SEQ_LEN", 512) + +class BenchmarkBertTrain(unittest.TestCase): + def _get_layer(self, layer_id): + if not hasattr(self, "model"): + dropout_prob = 0.0 if getenv("DISABLE_DROPOUT") else 0.1 + self.model = bert.BertForPretraining(attention_probs_dropout_prob=dropout_prob, hidden_dropout_prob=dropout_prob) + hidden_size = self.model.bert.embeddings.word_embeddings.embed_sz + intermediate_size = self.model.bert.encoder.layer[0].intermediate.dense.weight.shape[0] + + layer_map = { + "embedding": self.model.bert.embeddings, + "attention_self": self.model.bert.encoder.layer[0].attention.self, + "attention_output": self.model.bert.encoder.layer[0].attention.output, + "intermediate": self.model.bert.encoder.layer[0].intermediate, + "output": self.model.bert.encoder.layer[0].output + } + input_shapes = { + "embedding": [(bs, seq_len), (bs, seq_len)], + "attention_self": [(bs, seq_len, hidden_size), (bs, 1, 1, seq_len)], + "attention_output": [(bs, seq_len, hidden_size), (bs, seq_len, 1)], + "intermediate": [(bs, seq_len, hidden_size)], + "output": [(bs, seq_len, intermediate_size), (bs, seq_len, 1)] + }.get(layer_id) + + return f"{layer_id}-layer, Input: {input_shapes}", layer_map.get(layer_id), input_shapes + + def _test_layer(self, name, layer, input_shapes): + optim = LAMB(get_parameters(layer)) + with Context(TRACK_MATCH_STATS=0): Tensor.realize(*[t.assign(t.detach().contiguous()) for t in get_parameters(optim)]) + + JITCNT = getenv("JITCNT", 1) + Tensor.training = True + @TinyJit + def step(inputs): + optim.zero_grad() + for i in inputs: i.grad = None + + y = layer(*inputs).contiguous().contiguous_backward() + y.sum().backward() + if getenv("ASSIGN", 1): sched, _ = Tensor.schedule_with_vars(y, *list(inputs), *optim.schedule_step()) + else: sched, _ = Tensor.schedule_with_vars(y, *list(inputs), *[t.grad for t in optim.params]) + + for _ in range(JITCNT): + run_schedule(sched) + + CNT = getenv("CNT", 5) + best_tm = None + flops, mem_used, mem, kernels = None, None, None, None + for _ in range(CNT): + with Context(TRACK_MATCH_STATS=0): inputs = [Tensor.randn(*shape, requires_grad=False).realize() for shape in input_shapes] + GlobalCounters.reset() + + st = time.perf_counter() + step(inputs) + Device[Device.DEFAULT].synchronize() + et = time.perf_counter() + + flops = GlobalCounters.global_ops / JITCNT + mem_used = GlobalCounters.mem_used + mem = GlobalCounters.global_mem / JITCNT + if kernels is None: kernels = GlobalCounters.kernel_count // JITCNT + tm = (et-st) / JITCNT + if best_tm is None or tm < best_tm: best_tm = tm + print(f"\r{name:70s}: {best_tm * 1000:>9.2f} ms, {flops / 10**12 / best_tm:>6.2f} TFLOPS, {mem / 10**9 / best_tm:>5.0f} GB/s, " + f"{mem_used / 10**9: 6.2f} GB used, {kernels:>5d} kernels") + return best_tm, flops, mem, kernels + + def test_embedding_layer(self): self._est(*self._test_layer(*self._get_layer("embedding")), 1) + def test_attention_self_layer(self): self._est(*self._test_layer(*self._get_layer("attention_self")), 24) # Assumes BERT-large + def test_attention_output_layer(self): self._est(*self._test_layer(*self._get_layer("attention_output")), 24) + def test_intermediate_layer(self): self._est(*self._test_layer(*self._get_layer("intermediate")), 24) + def test_output_layer(self): self._est(*self._test_layer(*self._get_layer("output")), 24) + + est_tm, est_flops, est_mem, est_kernels = 0, 0, 0, 0 + + @classmethod + def _est(cls, tm, flops, mem, kernels, mult): + cls.est_tm += tm * mult + cls.est_flops += flops * mult + cls.est_mem += mem * mult + cls.est_kernels += kernels * mult + + @classmethod + def tearDownClass(cls): + print(f"\restimated step tm: {cls.est_tm * 1000.0:.2f} ms, {cls.est_flops / 10 ** 12 / cls.est_tm:.3f} tflops, " + f"{cls.est_mem / 10 ** 9 / cls.est_tm:.2f} GB/s, {cls.est_kernels} kernels") + + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/external/mlperf_bert/external_test_checkpoint_loading.py b/tinygrad_repo/test/external/mlperf_bert/external_test_checkpoint_loading.py new file mode 100644 index 000000000..5964d9724 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_bert/external_test_checkpoint_loading.py @@ -0,0 +1,55 @@ +# Test whether pretrained weights from first BERT pretraining phase have been loaded correctly +# Usage: +# 1. Download the BERT checkoints with `wikipedia_download.py` +# Command: BASEDIR=/path/to/wiki python3 wikipedia_download.py +# 2. Run this script. (Adjust EVAL_BS and GPUS as needed) +# Command: EVAL_BEAM=4 DEFAULT_FLOAT=half GPUS=6 BASEDIR=/path/to/wiki python3 test/external/mlperf_bert/external_test_checkpoint_loading.py +import os +from tqdm import tqdm + +from tinygrad.tensor import Tensor +from tinygrad.device import Device +from tinygrad.helpers import getenv +from tinygrad.nn.state import get_state_dict + +from examples.mlperf.helpers import get_mlperf_bert_model, get_data_bert +from examples.mlperf.dataloader import batch_load_val_bert +from examples.mlperf.model_train import eval_step_bert + +if __name__ == "__main__": + BASEDIR = os.environ["BASEDIR"] = getenv("BASEDIR", "/raid/datasets/wiki") + INIT_CKPT_DIR = getenv("INIT_CKPT_DIR", BASEDIR) + GPUS = [f"{Device.DEFAULT}:{i}" for i in range(getenv("GPUS", 1))] + EVAL_BS = getenv("EVAL_BS", 4 * len(GPUS)) + max_eval_steps = (10000 + EVAL_BS - 1) // EVAL_BS + + for i in range(10): + assert os.path.exists(os.path.join(BASEDIR, "eval", f"{i}.pkl")), \ + f"File {i}.pkl does not exist in {os.path.join(BASEDIR, 'eval')}" + + required_files = ["checkpoint", "model.ckpt-28252.data-00000-of-00001", "model.ckpt-28252.index", "model.ckpt-28252.meta"] + assert all(os.path.exists(os.path.join(INIT_CKPT_DIR, f)) for f in required_files), \ + f"Missing checkpoint files in INIT_CKPT_DIR: {required_files}" + + Tensor.training = False + + model = get_mlperf_bert_model(INIT_CKPT_DIR) + + for _, x in get_state_dict(model).items(): + x.realize().to_(GPUS) + + eval_accuracy = [] + eval_it = iter(batch_load_val_bert(EVAL_BS)) + + for _ in tqdm(range(max_eval_steps), desc="Evaluating", total=max_eval_steps): + eval_data = get_data_bert(GPUS, eval_it) + eval_result: dict[str, Tensor] = eval_step_bert(model, eval_data["input_ids"], eval_data["segment_ids"], eval_data["input_mask"], \ + eval_data["masked_lm_positions"], eval_data["masked_lm_ids"], \ + eval_data["masked_lm_weights"], eval_data["next_sentence_labels"]) + + mlm_accuracy = eval_result["masked_lm_accuracy"].numpy().item() + eval_accuracy.append(mlm_accuracy) + + total_lm_accuracy = sum(eval_accuracy) / len(eval_accuracy) + assert total_lm_accuracy >= 0.34, "Checkpoint loaded incorrectly. Accuracy should be very close to 0.34085 as per MLPerf BERT README." + print(f"Checkpoint loaded correctly. Accuracy of {total_lm_accuracy*100:.3f}% achieved. (Reference: 34.085%)") diff --git a/tinygrad_repo/test/external/mlperf_bert/preprocessing/create_pretraining_data.py b/tinygrad_repo/test/external/mlperf_bert/preprocessing/create_pretraining_data.py new file mode 100644 index 000000000..54041dfdd --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_bert/preprocessing/create_pretraining_data.py @@ -0,0 +1,435 @@ +# https://github.com/mlcommons/training/blob/1c8a098ae3e70962a4f7422c0b0bd35ae639e357/language_model/tensorflow/bert/cleanup_scripts/create_pretraining_data.py +# NOTE: This is a direct copy of the original script +# NOTE: With python 3.7.12, pip install tensorflow=1.15.5 +"""Create masked LM/next sentence masked_lm TF examples for BERT.""" + +from __future__ import absolute_import +from __future__ import division +from __future__ import print_function + +import os +os.environ['PROTOCOL_BUFFERS_PYTHON_IMPLEMENTATION'] = 'python' # NOTE: This is a workaround for protobuf issue + +import collections +import random +import tokenization +import tensorflow as tf + + +flags = tf.flags + +FLAGS = flags.FLAGS + +flags.DEFINE_string("input_file", None, + "Input raw text file (or comma-separated list of files).") + +flags.DEFINE_string( + "output_file", None, + "Output TF example file (or comma-separated list of files).") + +flags.DEFINE_string("vocab_file", None, + "The vocabulary file that the BERT model was trained on.") + +flags.DEFINE_bool( + "do_lower_case", True, + "Whether to lower case the input text. Should be True for uncased " + "models and False for cased models.") + +flags.DEFINE_integer("max_seq_length", 128, "Maximum sequence length.") + +flags.DEFINE_integer("max_predictions_per_seq", 20, + "Maximum number of masked LM predictions per sequence.") + +flags.DEFINE_integer("random_seed", 12345, "Random seed for data generation.") + +flags.DEFINE_integer( + "dupe_factor", 10, + "Number of times to duplicate the input data (with different masks).") + +flags.DEFINE_float("masked_lm_prob", 0.15, "Masked LM probability.") + +flags.DEFINE_float( + "short_seq_prob", 0.1, + "Probability of creating sequences which are shorter than the " + "maximum length.") + + +class TrainingInstance(object): + """A single training instance (sentence pair).""" + + def __init__(self, tokens, segment_ids, masked_lm_positions, masked_lm_labels, + is_random_next): + self.tokens = tokens + self.segment_ids = segment_ids + self.is_random_next = is_random_next + self.masked_lm_positions = masked_lm_positions + self.masked_lm_labels = masked_lm_labels + + def __str__(self): + s = "" + s += "tokens: %s\n" % (" ".join( + [tokenization.printable_text(x) for x in self.tokens])) + s += "segment_ids: %s\n" % (" ".join([str(x) for x in self.segment_ids])) + s += "is_random_next: %s\n" % self.is_random_next + s += "masked_lm_positions: %s\n" % (" ".join( + [str(x) for x in self.masked_lm_positions])) + s += "masked_lm_labels: %s\n" % (" ".join( + [tokenization.printable_text(x) for x in self.masked_lm_labels])) + s += "\n" + return s + + def __repr__(self): + return self.__str__() + + +def write_instance_to_example_files(instances, tokenizer, max_seq_length, + max_predictions_per_seq, output_files): + """Create TF example files from `TrainingInstance`s.""" + writers = [] + for output_file in output_files: + writers.append(tf.python_io.TFRecordWriter(output_file)) + + writer_index = 0 + + total_written = 0 + for (inst_index, instance) in enumerate(instances): + input_ids = tokenizer.convert_tokens_to_ids(instance.tokens) + input_mask = [1] * len(input_ids) + segment_ids = list(instance.segment_ids) + assert len(input_ids) <= max_seq_length + + while len(input_ids) < max_seq_length: + input_ids.append(0) + input_mask.append(0) + segment_ids.append(0) + + assert len(input_ids) == max_seq_length + assert len(input_mask) == max_seq_length + assert len(segment_ids) == max_seq_length + + masked_lm_positions = list(instance.masked_lm_positions) + masked_lm_ids = tokenizer.convert_tokens_to_ids(instance.masked_lm_labels) + masked_lm_weights = [1.0] * len(masked_lm_ids) + + while len(masked_lm_positions) < max_predictions_per_seq: + masked_lm_positions.append(0) + masked_lm_ids.append(0) + masked_lm_weights.append(0.0) + + next_sentence_label = 1 if instance.is_random_next else 0 + + features = collections.OrderedDict() + features["input_ids"] = create_int_feature(input_ids) + features["input_mask"] = create_int_feature(input_mask) + features["segment_ids"] = create_int_feature(segment_ids) + features["masked_lm_positions"] = create_int_feature(masked_lm_positions) + features["masked_lm_ids"] = create_int_feature(masked_lm_ids) + features["masked_lm_weights"] = create_float_feature(masked_lm_weights) + features["next_sentence_labels"] = create_int_feature([next_sentence_label]) + + tf_example = tf.train.Example(features=tf.train.Features(feature=features)) + + writers[writer_index].write(tf_example.SerializeToString()) + writer_index = (writer_index + 1) % len(writers) + + total_written += 1 + + if inst_index < 20: + tf.logging.info("*** Example ***") + tf.logging.info("tokens: %s" % " ".join( + [tokenization.printable_text(x) for x in instance.tokens])) + + for feature_name in features.keys(): + feature = features[feature_name] + values = [] + if feature.int64_list.value: + values = feature.int64_list.value + elif feature.float_list.value: + values = feature.float_list.value + tf.logging.info( + "%s: %s" % (feature_name, " ".join([str(x) for x in values]))) + + for writer in writers: + writer.close() + + tf.logging.info("Wrote %d total instances", total_written) + + +def create_int_feature(values): + feature = tf.train.Feature(int64_list=tf.train.Int64List(value=list(values))) + return feature + + +def create_float_feature(values): + feature = tf.train.Feature(float_list=tf.train.FloatList(value=list(values))) + return feature + + +def create_training_instances(input_files, tokenizer, max_seq_length, + dupe_factor, short_seq_prob, masked_lm_prob, + max_predictions_per_seq, rng): + """Create `TrainingInstance`s from raw text.""" + all_documents = [[]] + + # Input file format: + # (1) One sentence per line. These should ideally be actual sentences, not + # entire paragraphs or arbitrary spans of text. (Because we use the + # sentence boundaries for the "next sentence prediction" task). + # (2) Blank lines between documents. Document boundaries are needed so + # that the "next sentence prediction" task doesn't span between documents. + for input_file in input_files: + with tf.gfile.GFile(input_file, "r") as reader: + while True: + line = tokenization.convert_to_unicode(reader.readline()) + if not line: + break + line = line.strip() + + # Empty lines are used as document delimiters + if not line: + all_documents.append([]) + tokens = tokenizer.tokenize(line) + if tokens: + all_documents[-1].append(tokens) + + # Remove empty documents + all_documents = [x for x in all_documents if x] + rng.shuffle(all_documents) + + vocab_words = list(tokenizer.vocab.keys()) + instances = [] + for _ in range(dupe_factor): + for document_index in range(len(all_documents)): + instances.extend( + create_instances_from_document( + all_documents, document_index, max_seq_length, short_seq_prob, + masked_lm_prob, max_predictions_per_seq, vocab_words, rng)) + + rng.shuffle(instances) + return instances + + +def create_instances_from_document( + all_documents, document_index, max_seq_length, short_seq_prob, + masked_lm_prob, max_predictions_per_seq, vocab_words, rng): + """Creates `TrainingInstance`s for a single document.""" + document = all_documents[document_index] + + # Account for [CLS], [SEP], [SEP] + max_num_tokens = max_seq_length - 3 + + # We *usually* want to fill up the entire sequence since we are padding + # to `max_seq_length` anyways, so short sequences are generally wasted + # computation. However, we *sometimes* + # (i.e., short_seq_prob == 0.1 == 10% of the time) want to use shorter + # sequences to minimize the mismatch between pre-training and fine-tuning. + # The `target_seq_length` is just a rough target however, whereas + # `max_seq_length` is a hard limit. + target_seq_length = max_num_tokens + if rng.random() < short_seq_prob: + target_seq_length = rng.randint(2, max_num_tokens) + + # We DON'T just concatenate all of the tokens from a document into a long + # sequence and choose an arbitrary split point because this would make the + # next sentence prediction task too easy. Instead, we split the input into + # segments "A" and "B" based on the actual "sentences" provided by the user + # input. + instances = [] + current_chunk = [] + current_length = 0 + i = 0 + while i < len(document): + segment = document[i] + current_chunk.append(segment) + current_length += len(segment) + if i == len(document) - 1 or current_length >= target_seq_length: + if current_chunk: + # `a_end` is how many segments from `current_chunk` go into the `A` + # (first) sentence. + a_end = 1 + if len(current_chunk) >= 2: + a_end = rng.randint(1, len(current_chunk) - 1) + + tokens_a = [] + for j in range(a_end): + tokens_a.extend(current_chunk[j]) + + tokens_b = [] + # Random next + is_random_next = False + if len(current_chunk) == 1 or rng.random() < 0.5: + is_random_next = True + target_b_length = target_seq_length - len(tokens_a) + + # This should rarely go for more than one iteration for large + # corpora. However, just to be careful, we try to make sure that + # the random document is not the same as the document + # we're processing. + for _ in range(10): + random_document_index = rng.randint(0, len(all_documents) - 1) + if random_document_index != document_index: + break + + random_document = all_documents[random_document_index] + random_start = rng.randint(0, len(random_document) - 1) + for j in range(random_start, len(random_document)): + tokens_b.extend(random_document[j]) + if len(tokens_b) >= target_b_length: + break + # We didn't actually use these segments so we "put them back" so + # they don't go to waste. + num_unused_segments = len(current_chunk) - a_end + i -= num_unused_segments + # Actual next + else: + is_random_next = False + for j in range(a_end, len(current_chunk)): + tokens_b.extend(current_chunk[j]) + truncate_seq_pair(tokens_a, tokens_b, max_num_tokens, rng) + + assert len(tokens_a) >= 1 + assert len(tokens_b) >= 1 + + tokens = [] + segment_ids = [] + tokens.append("[CLS]") + segment_ids.append(0) + for token in tokens_a: + tokens.append(token) + segment_ids.append(0) + + tokens.append("[SEP]") + segment_ids.append(0) + + for token in tokens_b: + tokens.append(token) + segment_ids.append(1) + tokens.append("[SEP]") + segment_ids.append(1) + + (tokens, masked_lm_positions, + masked_lm_labels) = create_masked_lm_predictions( + tokens, masked_lm_prob, max_predictions_per_seq, vocab_words, rng) + instance = TrainingInstance( + tokens=tokens, + segment_ids=segment_ids, + is_random_next=is_random_next, + masked_lm_positions=masked_lm_positions, + masked_lm_labels=masked_lm_labels) + instances.append(instance) + current_chunk = [] + current_length = 0 + i += 1 + + return instances + + +MaskedLmInstance = collections.namedtuple("MaskedLmInstance", + ["index", "label"]) + + +def create_masked_lm_predictions(tokens, masked_lm_prob, + max_predictions_per_seq, vocab_words, rng): + """Creates the predictions for the masked LM objective.""" + + cand_indexes = [] + for (i, token) in enumerate(tokens): + if token == "[CLS]" or token == "[SEP]": + continue + cand_indexes.append(i) + + rng.shuffle(cand_indexes) + + output_tokens = list(tokens) + + num_to_predict = min(max_predictions_per_seq, + max(1, int(round(len(tokens) * masked_lm_prob)))) + + masked_lms = [] + covered_indexes = set() + for index in cand_indexes: + if len(masked_lms) >= num_to_predict: + break + if index in covered_indexes: + continue + covered_indexes.add(index) + + masked_token = None + # 80% of the time, replace with [MASK] + if rng.random() < 0.8: + masked_token = "[MASK]" + else: + # 10% of the time, keep original + if rng.random() < 0.5: + masked_token = tokens[index] + # 10% of the time, replace with random word + else: + masked_token = vocab_words[rng.randint(0, len(vocab_words) - 1)] + + output_tokens[index] = masked_token + + masked_lms.append(MaskedLmInstance(index=index, label=tokens[index])) + + masked_lms = sorted(masked_lms, key=lambda x: x.index) + + masked_lm_positions = [] + masked_lm_labels = [] + for p in masked_lms: + masked_lm_positions.append(p.index) + masked_lm_labels.append(p.label) + + return (output_tokens, masked_lm_positions, masked_lm_labels) + + +def truncate_seq_pair(tokens_a, tokens_b, max_num_tokens, rng): + """Truncates a pair of sequences to a maximum sequence length.""" + while True: + total_length = len(tokens_a) + len(tokens_b) + if total_length <= max_num_tokens: + break + + trunc_tokens = tokens_a if len(tokens_a) > len(tokens_b) else tokens_b + assert len(trunc_tokens) >= 1 + + # We want to sometimes truncate from the front and sometimes from the + # back to add more randomness and avoid biases. + if rng.random() < 0.5: + del trunc_tokens[0] + else: + trunc_tokens.pop() + + +def main(_): + tf.logging.set_verbosity(tf.logging.INFO) + + tokenizer = tokenization.FullTokenizer( + vocab_file=FLAGS.vocab_file, do_lower_case=FLAGS.do_lower_case) + + input_files = [] + for input_pattern in FLAGS.input_file.split(","): + input_files.extend(tf.gfile.Glob(input_pattern)) + + tf.logging.info("*** Reading from input files ***") + for input_file in input_files: + tf.logging.info(" %s", input_file) + + rng = random.Random(FLAGS.random_seed) + instances = create_training_instances( + input_files, tokenizer, FLAGS.max_seq_length, FLAGS.dupe_factor, + FLAGS.short_seq_prob, FLAGS.masked_lm_prob, FLAGS.max_predictions_per_seq, + rng) + + output_files = FLAGS.output_file.split(",") + tf.logging.info("*** Writing to output files ***") + for output_file in output_files: + tf.logging.info(" %s", output_file) + + write_instance_to_example_files(instances, tokenizer, FLAGS.max_seq_length, + FLAGS.max_predictions_per_seq, output_files) + + +if __name__ == "__main__": + flags.mark_flag_as_required("input_file") + flags.mark_flag_as_required("output_file") + flags.mark_flag_as_required("vocab_file") + tf.app.run() diff --git a/tinygrad_repo/test/external/mlperf_bert/preprocessing/external_test_preprocessing_part.py b/tinygrad_repo/test/external/mlperf_bert/preprocessing/external_test_preprocessing_part.py new file mode 100644 index 000000000..6db284125 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_bert/preprocessing/external_test_preprocessing_part.py @@ -0,0 +1,79 @@ +# USAGE: +# 1. Download raw text data with `wikipedia_download.py` + +# 2. Install python==3.7.12 and tensorflow==1.15.5 +# Run `create_pretraining_data.py` to create TFRecords on specific part (This will take some time) +# Command: python3 create_pretraining_data.py --input_file=/path/to/part-00XXX-of-00500 --vocab_file=/path/to/vocab.txt \ +# --output_file=/path/to/output.tfrecord --max_seq_length=512 --max_predictions_per_seq=76 +# +# 2.1 For eval: --input_file=/path/to/eval.txt and +# Command: python3 pick_eval_samples.py --input_tfrecord=/path/to/eval.tfrecord --output_tfrecord=/path/to/output_eval.tfrecord + +# 3. Run `wikipedia.py` to preprocess the data with tinygrad (Use python > 3.7) +# Command: BASEDIR=/path/to/basedir python3 wikipedia.py pre-train X (NOTE: part number needs to match part of step 2) +# This will output to /path/to/basedir/train/X.pkl +# +# 3.1 For eval: +# Command: BASEDIR=/path/to/basedir python3 wikipedia.py pre-eval +# This will output to /path/to/basedir/eval.pkl + +# 4. Run this script to verify the correctness of the preprocessing script for specific part +# Command: python3 external_test_preprocessing_part.py --preprocessed_part=/path/to/basedir/train/X.pkl --tf_records=/path/to/output.tfrecord +import os, argparse, pickle +from tqdm import tqdm + +# This is a workaround for protobuf issue +os.environ['PROTOCOL_BUFFERS_PYTHON_IMPLEMENTATION'] = 'python' +os.environ['TF_CPP_MIN_LOG_LEVEL'] = '2' + +import tensorflow as tf + +tf.compat.v1.enable_eager_execution() +tf.compat.v1.logging.set_verbosity(tf.compat.v1.logging.ERROR) + +def _parse_function(proto, max_seq_length, max_predictions_per_seq): + feature_description = { + 'input_ids': tf.io.FixedLenFeature([max_seq_length], tf.int64), + 'input_mask': tf.io.FixedLenFeature([max_seq_length], tf.int64), + 'segment_ids': tf.io.FixedLenFeature([max_seq_length], tf.int64), + 'masked_lm_positions': tf.io.FixedLenFeature([max_predictions_per_seq], tf.int64), + 'masked_lm_ids': tf.io.FixedLenFeature([max_predictions_per_seq], tf.int64), + 'masked_lm_weights': tf.io.FixedLenFeature([max_predictions_per_seq], tf.float32), + 'next_sentence_labels': tf.io.FixedLenFeature([1], tf.int64), + } + return tf.io.parse_single_example(proto, feature_description) + +def load_dataset(file_path, max_seq_length=512, max_predictions_per_seq=76): + dataset = tf.data.TFRecordDataset(file_path) + parse_function = lambda proto: _parse_function(proto, max_seq_length, max_predictions_per_seq) # noqa: E731 + return dataset.map(parse_function) + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description="Verify the correctness of the preprocessing script for specific part", + formatter_class=argparse.ArgumentDefaultsHelpFormatter) + parser.add_argument("--preprocessed_part", type=str, default=None, + help="Path to preprocessed samples file from `wikipedia.py`") + parser.add_argument("--tf_records", type=str, default=None, + help="Path to TFRecords file from `create_pretraining_data.py` (Reference implementation)") + parser.add_argument("--max_seq_length", type=int, default=512, help="Max sequence length. For MLPerf keep it at 512") + parser.add_argument("--max_predictions_per_seq", type=int, default=76, help="Max predictions per sequence. For MLPerf keep it at 76") + parser.add_argument("--is_eval", type=bool, default=False, help="Whether to run eval or train preprocessing") + args = parser.parse_args() + + assert os.path.isfile(args.preprocessed_part), f"The specified file {args.preprocessed_part} does not exist." + assert os.path.isfile(args.tf_records), f"The specified TFRecords file {args.tf_records} does not exist." + + with open(args.preprocessed_part, 'rb') as f: + preprocessed_samples = pickle.load(f) + + dataset = load_dataset(args.tf_records, args.max_seq_length, args.max_predictions_per_seq) + tf_record_count = sum(1 for _ in dataset) + assert tf_record_count == len(preprocessed_samples), f"Samples in reference: {tf_record_count} != Preprocessed samples: {len(preprocessed_samples)}" + print(f"Total samples in the part: {tf_record_count}") + + for i, (reference_example, preprocessed_sample) in tqdm(enumerate(zip(dataset, preprocessed_samples)), desc="Checking samples", total=len(preprocessed_samples)): # noqa: E501 + feature_keys = ["input_ids", "input_mask", "segment_ids", "masked_lm_positions", "masked_lm_ids", "masked_lm_weights", "next_sentence_labels"] + for key in feature_keys: + reference_example_feature = reference_example[key].numpy() + assert (reference_example_feature == preprocessed_sample[key]).all(), \ + f"{key} are not equal at index {i}\nReference: {reference_example_feature}\nPreprocessed: {preprocessed_sample[key]}" diff --git a/tinygrad_repo/test/external/mlperf_bert/preprocessing/pick_eval_samples.py b/tinygrad_repo/test/external/mlperf_bert/preprocessing/pick_eval_samples.py new file mode 100644 index 000000000..d9f0b6440 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_bert/preprocessing/pick_eval_samples.py @@ -0,0 +1,127 @@ +# https://github.com/mlcommons/training/blob/1c8a098ae3e70962a4f7422c0b0bd35ae639e357/language_model/tensorflow/bert/cleanup_scripts/pick_eval_samples.py +# NOTE: This is a direct copy of the original script +"""Script for picking certain number of sampels. +""" + +import argparse +import time +import logging +import collections +import tensorflow as tf + +parser = argparse.ArgumentParser( + description="Eval sample picker for BERT.") +parser.add_argument( + '--input_tfrecord', + type=str, + default='', + help='Input tfrecord path') +parser.add_argument( + '--output_tfrecord', + type=str, + default='', + help='Output tfrecord path') +parser.add_argument( + '--num_examples_to_pick', + type=int, + default=10000, + help='Number of examples to pick') +parser.add_argument( + '--max_seq_length', + type=int, + default=512, + help='The maximum number of tokens within a sequence.') +parser.add_argument( + '--max_predictions_per_seq', + type=int, + default=76, + help='The maximum number of predictions within a sequence.') +args = parser.parse_args() + +max_seq_length = args.max_seq_length +max_predictions_per_seq = args.max_predictions_per_seq +logging.basicConfig(level=logging.INFO) + +def decode_record(record): + """Decodes a record to a TensorFlow example.""" + name_to_features = { + "input_ids": + tf.FixedLenFeature([max_seq_length], tf.int64), + "input_mask": + tf.FixedLenFeature([max_seq_length], tf.int64), + "segment_ids": + tf.FixedLenFeature([max_seq_length], tf.int64), + "masked_lm_positions": + tf.FixedLenFeature([max_predictions_per_seq], tf.int64), + "masked_lm_ids": + tf.FixedLenFeature([max_predictions_per_seq], tf.int64), + "masked_lm_weights": + tf.FixedLenFeature([max_predictions_per_seq], tf.float32), + "next_sentence_labels": + tf.FixedLenFeature([1], tf.int64), + } + + example = tf.parse_single_example(record, name_to_features) + + # tf.Example only supports tf.int64, but the TPU only supports tf.int32. + # So cast all int64 to int32. + for name in list(example.keys()): + t = example[name] + if t.dtype == tf.int64: + t = tf.to_int32(t) + example[name] = t + + return example + + +def create_int_feature(values): + feature = tf.train.Feature(int64_list=tf.train.Int64List(value=list(values))) + return feature + + +def create_float_feature(values): + feature = tf.train.Feature(float_list=tf.train.FloatList(value=list(values))) + return feature + + +if __name__ == '__main__': + tic = time.time() + tf.enable_eager_execution() + + d = tf.data.TFRecordDataset(args.input_tfrecord) + num_examples = 0 + records = [] + for record in d: + records.append(record) + num_examples += 1 + + writer = tf.python_io.TFRecordWriter(args.output_tfrecord) + i = 0 + pick_ratio = num_examples / args.num_examples_to_pick + num_examples_picked = 0 + for i in range(args.num_examples_to_pick): + example = decode_record(records[int(i * pick_ratio)]) + features = collections.OrderedDict() + features["input_ids"] = create_int_feature( + example["input_ids"].numpy()) + features["input_mask"] = create_int_feature( + example["input_mask"].numpy()) + features["segment_ids"] = create_int_feature( + example["segment_ids"].numpy()) + features["masked_lm_positions"] = create_int_feature( + example["masked_lm_positions"].numpy()) + features["masked_lm_ids"] = create_int_feature( + example["masked_lm_ids"].numpy()) + features["masked_lm_weights"] = create_float_feature( + example["masked_lm_weights"].numpy()) + features["next_sentence_labels"] = create_int_feature( + example["next_sentence_labels"].numpy()) + + tf_example = tf.train.Example(features=tf.train.Features(feature=features)) + writer.write(tf_example.SerializeToString()) + num_examples_picked += 1 + + writer.close() + toc = time.time() + logging.info("Picked %d examples out of %d samples in %.2f sec", + num_examples_picked, num_examples, toc - tic) diff --git a/tinygrad_repo/test/external/mlperf_bert/preprocessing/tokenization.py b/tinygrad_repo/test/external/mlperf_bert/preprocessing/tokenization.py new file mode 100644 index 000000000..2d7fc8f15 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_bert/preprocessing/tokenization.py @@ -0,0 +1,415 @@ +# https://github.com/mlcommons/training/blob/1c8a098ae3e70962a4f7422c0b0bd35ae639e357/language_model/tensorflow/bert/cleanup_scripts/tokenization.py +# NOTE: This is a direct copy of the original script +"""Tokenization classes.""" + +from __future__ import absolute_import +from __future__ import division +from __future__ import print_function + +import collections +import re +import unicodedata + +from absl import flags +import six +import tensorflow.compat.v1 as tf + +FLAGS = flags.FLAGS + +flags.DEFINE_bool( + "preserve_unused_tokens", False, + "If True, Wordpiece tokenization will not be applied to words in the vocab." +) + +_UNUSED_TOKEN_RE = re.compile("^\\[unused\\d+\\]$") + + +def preserve_token(token, vocab): + """Returns True if the token should forgo tokenization and be preserved.""" + if not FLAGS.preserve_unused_tokens: + return False + if token not in vocab: + return False + return bool(_UNUSED_TOKEN_RE.search(token)) + + +def validate_case_matches_checkpoint(do_lower_case, init_checkpoint): + """Checks whether the casing config is consistent with the checkpoint name.""" + + # The casing has to be passed in by the user and there is no explicit check + # as to whether it matches the checkpoint. The casing information probably + # should have been stored in the bert_config.json file, but it's not, so + # we have to heuristically detect it to validate. + + if not init_checkpoint: + return + + m = re.match("^.*?([A-Za-z0-9_-]+)/bert_model.ckpt", init_checkpoint) + if m is None: + return + + model_name = m.group(1) + + lower_models = [ + "uncased_L-24_H-1024_A-16", "uncased_L-12_H-768_A-12", + "multilingual_L-12_H-768_A-12", "chinese_L-12_H-768_A-12" + ] + + cased_models = [ + "cased_L-12_H-768_A-12", "cased_L-24_H-1024_A-16", + "multi_cased_L-12_H-768_A-12" + ] + + is_bad_config = False + if model_name in lower_models and not do_lower_case: + is_bad_config = True + actual_flag = "False" + case_name = "lowercased" + opposite_flag = "True" + + if model_name in cased_models and do_lower_case: + is_bad_config = True + actual_flag = "True" + case_name = "cased" + opposite_flag = "False" + + if is_bad_config: + raise ValueError( + "You passed in `--do_lower_case=%s` with `--init_checkpoint=%s`. " + "However, `%s` seems to be a %s model, so you " + "should pass in `--do_lower_case=%s` so that the fine-tuning matches " + "how the model was pre-training. If this error is wrong, please " + "just comment out this check." % (actual_flag, init_checkpoint, + model_name, case_name, opposite_flag)) + + +def convert_to_unicode(text): + """Converts `text` to Unicode (if it's not already), assuming utf-8 input.""" + if six.PY3: + if isinstance(text, str): + return text + elif isinstance(text, bytes): + return text.decode("utf-8", "ignore") + else: + raise ValueError("Unsupported string type: %s" % (type(text))) + elif six.PY2: + if isinstance(text, str): + return text.decode("utf-8", "ignore") + elif isinstance(text, unicode): # noqa: F821 + return text + else: + raise ValueError("Unsupported string type: %s" % (type(text))) + else: + raise ValueError("Not running on Python2 or Python 3?") + + +def printable_text(text): + """Returns text encoded in a way suitable for print or `tf.logging`.""" + + # These functions want `str` for both Python2 and Python3, but in one case + # it's a Unicode string and in the other it's a byte string. + if six.PY3: + if isinstance(text, str): + return text + elif isinstance(text, bytes): + return text.decode("utf-8", "ignore") + else: + raise ValueError("Unsupported string type: %s" % (type(text))) + elif six.PY2: + if isinstance(text, str): + return text + elif isinstance(text, unicode): # noqa: F821 + return text.encode("utf-8") + else: + raise ValueError("Unsupported string type: %s" % (type(text))) + else: + raise ValueError("Not running on Python2 or Python 3?") + + +def load_vocab(vocab_file): + """Loads a vocabulary file into a dictionary.""" + vocab = collections.OrderedDict() + with tf.gfile.GFile(vocab_file, "r") as reader: + while True: + token = convert_to_unicode(reader.readline()) + if not token: + break + token = token.strip() + if token not in vocab: + vocab[token] = len(vocab) + return vocab + + +def convert_by_vocab(vocab, items): + """Converts a sequence of [tokens|ids] using the vocab.""" + output = [] + for item in items: + output.append(vocab[item]) + return output + + +def convert_tokens_to_ids(vocab, tokens): + return convert_by_vocab(vocab, tokens) + + +def convert_ids_to_tokens(inv_vocab, ids): + return convert_by_vocab(inv_vocab, ids) + + +def whitespace_tokenize(text): + """Runs basic whitespace cleaning and splitting on a piece of text.""" + text = text.strip() + if not text: + return [] + tokens = text.split() + return tokens + + +class FullTokenizer(object): + """Runs end-to-end tokenziation.""" + + def __init__(self, vocab_file, do_lower_case=True): + self.vocab = load_vocab(vocab_file) + self.inv_vocab = {v: k for k, v in self.vocab.items()} + self.basic_tokenizer = BasicTokenizer( + do_lower_case=do_lower_case, vocab=self.vocab) + self.wordpiece_tokenizer = WordpieceTokenizer(vocab=self.vocab) + + def tokenize(self, text): + split_tokens = [] + for token in self.basic_tokenizer.tokenize(text): + if preserve_token(token, self.vocab): + split_tokens.append(token) + continue + for sub_token in self.wordpiece_tokenizer.tokenize(token): + split_tokens.append(sub_token) + + return split_tokens + + def convert_tokens_to_ids(self, tokens): + return convert_by_vocab(self.vocab, tokens) + + def convert_ids_to_tokens(self, ids): + return convert_by_vocab(self.inv_vocab, ids) + + +class BasicTokenizer(object): + """Runs basic tokenization (punctuation splitting, lower casing, etc.).""" + + def __init__(self, do_lower_case=True, vocab=tuple()): + """Constructs a BasicTokenizer. + + Args: + do_lower_case: Whether to lower case the input. + vocab: A container of tokens to not mutate during tokenization. + """ + self.do_lower_case = do_lower_case + self.vocab = vocab + + def tokenize(self, text): + """Tokenizes a piece of text.""" + text = convert_to_unicode(text) + text = self._clean_text(text) + + # This was added on November 1st, 2018 for the multilingual and Chinese + # models. This is also applied to the English models now, but it doesn't + # matter since the English models were not trained on any Chinese data + # and generally don't have any Chinese data in them (there are Chinese + # characters in the vocabulary because Wikipedia does have some Chinese + # words in the English Wikipedia.). + text = self._tokenize_chinese_chars(text) + + orig_tokens = whitespace_tokenize(text) + split_tokens = [] + for token in orig_tokens: + if preserve_token(token, self.vocab): + split_tokens.append(token) + continue + if self.do_lower_case: + token = token.lower() + token = self._run_strip_accents(token) + split_tokens.extend(self._run_split_on_punc(token)) + + output_tokens = whitespace_tokenize(" ".join(split_tokens)) + return output_tokens + + def _run_strip_accents(self, text): + """Strips accents from a piece of text.""" + text = unicodedata.normalize("NFD", text) + output = [] + for char in text: + cat = unicodedata.category(char) + if cat == "Mn": + continue + output.append(char) + return "".join(output) + + def _run_split_on_punc(self, text): + """Splits punctuation on a piece of text.""" + chars = list(text) + i = 0 + start_new_word = True + output = [] + while i < len(chars): + char = chars[i] + if _is_punctuation(char): + output.append([char]) + start_new_word = True + else: + if start_new_word: + output.append([]) + start_new_word = False + output[-1].append(char) + i += 1 + + return ["".join(x) for x in output] + + def _tokenize_chinese_chars(self, text): + """Adds whitespace around any CJK character.""" + output = [] + for char in text: + cp = ord(char) + if self._is_chinese_char(cp): + output.append(" ") + output.append(char) + output.append(" ") + else: + output.append(char) + return "".join(output) + + def _is_chinese_char(self, cp): + """Checks whether CP is the codepoint of a CJK character.""" + # This defines a "chinese character" as anything in the CJK Unicode block: + # https://en.wikipedia.org/wiki/CJK_Unified_Ideographs_(Unicode_block) + # + # Note that the CJK Unicode block is NOT all Japanese and Korean characters, + # despite its name. The modern Korean Hangul alphabet is a different block, + # as is Japanese Hiragana and Katakana. Those alphabets are used to write + # space-separated words, so they are not treated specially and handled + # like all of the other languages. + if ((cp >= 0x4E00 and cp <= 0x9FFF) or # + (cp >= 0x3400 and cp <= 0x4DBF) or # + (cp >= 0x20000 and cp <= 0x2A6DF) or # + (cp >= 0x2A700 and cp <= 0x2B73F) or # + (cp >= 0x2B740 and cp <= 0x2B81F) or # + (cp >= 0x2B820 and cp <= 0x2CEAF) or + (cp >= 0xF900 and cp <= 0xFAFF) or # + (cp >= 0x2F800 and cp <= 0x2FA1F)): # + return True + + return False + + def _clean_text(self, text): + """Performs invalid character removal and whitespace cleanup on text.""" + output = [] + for char in text: + cp = ord(char) + if cp == 0 or cp == 0xfffd or _is_control(char): + continue + if _is_whitespace(char): + output.append(" ") + else: + output.append(char) + return "".join(output) + + +class WordpieceTokenizer(object): + """Runs WordPiece tokenziation.""" + + def __init__(self, vocab, unk_token="[UNK]", max_input_chars_per_word=200): + self.vocab = vocab + self.unk_token = unk_token + self.max_input_chars_per_word = max_input_chars_per_word + + def tokenize(self, text): + """Tokenizes a piece of text into its word pieces. + + This uses a greedy longest-match-first algorithm to perform tokenization + using the given vocabulary. + + For example: + input = "unaffable" + output = ["un", "##aff", "##able"] + + Args: + text: A single token or whitespace separated tokens. This should have + already been passed through `BasicTokenizer. + + Returns: + A list of wordpiece tokens. + """ + + text = convert_to_unicode(text) + + output_tokens = [] + for token in whitespace_tokenize(text): + chars = list(token) + if len(chars) > self.max_input_chars_per_word: + output_tokens.append(self.unk_token) + continue + + is_bad = False + start = 0 + sub_tokens = [] + while start < len(chars): + end = len(chars) + cur_substr = None + while start < end: + substr = "".join(chars[start:end]) + if start > 0: + substr = "##" + substr + if substr in self.vocab: + cur_substr = substr + break + end -= 1 + if cur_substr is None: + is_bad = True + break + sub_tokens.append(cur_substr) + start = end + + if is_bad: + output_tokens.append(self.unk_token) + else: + output_tokens.extend(sub_tokens) + return output_tokens + + +def _is_whitespace(char): + """Checks whether `chars` is a whitespace character.""" + # \t, \n, and \r are technically control characters but we treat them + # as whitespace since they are generally considered as such. + if char == " " or char == "\t" or char == "\n" or char == "\r": + return True + cat = unicodedata.category(char) + if cat == "Zs": + return True + return False + + +def _is_control(char): + """Checks whether `chars` is a control character.""" + # These are technically control characters but we count them as whitespace + # characters. + if char == "\t" or char == "\n" or char == "\r": + return False + cat = unicodedata.category(char) + if cat in ("Cc", "Cf"): + return True + return False + + +def _is_punctuation(char): + """Checks whether `chars` is a punctuation character.""" + cp = ord(char) + # We treat all non-letter/number ASCII as punctuation. + # Characters such as "^", "$", and "`" are not in the Unicode + # Punctuation class but we treat them as punctuation anyways, for + # consistency. + if ((cp >= 33 and cp <= 47) or (cp >= 58 and cp <= 64) or + (cp >= 91 and cp <= 96) or (cp >= 123 and cp <= 126)): + return True + cat = unicodedata.category(char) + if cat.startswith("P"): + return True + return False diff --git a/tinygrad_repo/test/external/mlperf_resnet/lars_optimizer.py b/tinygrad_repo/test/external/mlperf_resnet/lars_optimizer.py new file mode 100644 index 000000000..6c1a169a9 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_resnet/lars_optimizer.py @@ -0,0 +1,233 @@ +# https://github.com/mlcommons/training/blob/e3769c8dcf88cd21e1001dd2f894b40a1513ec5d/image_classification/tensorflow2/lars_optimizer.py +# changes: don't call lr_t if it's not a schedule + +# Copyright 2018 The TensorFlow Authors. All Rights Reserved. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +"""Layer-wise Adaptive Rate Scaling optimizer for large-batch training.""" + +from __future__ import absolute_import +from __future__ import division +from __future__ import print_function + +import tensorflow as tf +# from tf2_common.training import optimizer_v2modified +from tensorflow.python.framework import ops +from tensorflow.python.keras import backend_config +from tensorflow.python.keras.optimizer_v2 import optimizer_v2 +from tensorflow.python.ops import array_ops +from tensorflow.python.ops import linalg_ops +from tensorflow.python.ops import math_ops +from tensorflow.python.training import training_ops +from tensorflow.python.ops import state_ops + + +# class LARSOptimizer(optimizer_v2modified.OptimizerV2Modified): +class LARSOptimizer(optimizer_v2.OptimizerV2): + """Layer-wise Adaptive Rate Scaling for large batch training. + + Introduced by "Large Batch Training of Convolutional Networks" by Y. You, + I. Gitman, and B. Ginsburg. (https://arxiv.org/abs/1708.03888) + + Implements the LARS learning rate scheme presented in the paper above. This + optimizer is useful when scaling the batch size to up to 32K without + significant performance degradation. It is recommended to use the optimizer + in conjunction with: + - Gradual learning rate warm-up + - Linear learning rate scaling + - Poly rule learning rate decay + + Note, LARS scaling is currently only enabled for dense tensors. Sparse tensors + use the default momentum optimizer. + """ + + def __init__( + self, + learning_rate, + momentum=0.9, + weight_decay=0.0001, + # The LARS coefficient is a hyperparameter + eeta=0.001, + epsilon=0.0, + name="LARSOptimizer", + # Enable skipping variables from LARS scaling. + # TODO(sameerkm): Enable a direct mechanism to pass a + # subset of variables to the optimizer. + skip_list=None, + use_nesterov=False, + **kwargs): + """Construct a new LARS Optimizer. + + Args: + learning_rate: A `Tensor`, floating point value, or a schedule that is a + `tf.keras.optimizers.schedules.LearningRateSchedule`, or a callable + that takes no arguments and returns the actual value to use. The + learning rate. + momentum: A floating point value. Momentum hyperparameter. + weight_decay: A floating point value. Weight decay hyperparameter. + eeta: LARS coefficient as used in the paper. Dfault set to LARS + coefficient from the paper. (eeta / weight_decay) determines the highest + scaling factor in LARS. + epsilon: Optional epsilon parameter to be set in models that have very + small gradients. Default set to 0.0. + name: Optional name prefix for variables and ops created by LARSOptimizer. + skip_list: List of strings to enable skipping variables from LARS scaling. + If any of the strings in skip_list is a subset of var.name, variable + 'var' is skipped from LARS scaling. For a typical classification model + with batch normalization, the skip_list is ['batch_normalization', + 'bias'] + use_nesterov: when set to True, nesterov momentum will be enabled + **kwargs: keyword arguments. + + Raises: + ValueError: If a hyperparameter is set to a non-sensical value. + """ + if momentum < 0.0: + raise ValueError("momentum should be positive: %s" % momentum) + if weight_decay < 0.0: + raise ValueError("weight_decay should be positive: %s" % weight_decay) + super(LARSOptimizer, self).__init__(name=name, **kwargs) + + self._set_hyper("learning_rate", learning_rate) + + # When directly using class members, instead of + # _set_hyper and _get_hyper (such as learning_rate above), + # the values are fixed after __init(), and not being + # updated during the training process. + # This provides better performance but less flexibility. + self.momentum = momentum + self.weight_decay = weight_decay + self.eeta = eeta + self.epsilon = epsilon or backend_config.epsilon() + self._skip_list = skip_list + self.use_nesterov = use_nesterov + + def _prepare_local(self, var_device, var_dtype, apply_state): + lr_t = self._get_hyper("learning_rate", var_dtype) + local_step = math_ops.cast(self.iterations, var_dtype) + if callable(lr_t): lr_t = math_ops.cast(lr_t(local_step), var_dtype) + learning_rate_t = array_ops.identity(lr_t) + + apply_state[(var_device, var_dtype)].update( + dict( + learning_rate=learning_rate_t, + )) + + def _create_slots(self, var_list): + for v in var_list: + self.add_slot(v, "momentum") + + def compute_lr(self, grad, var, coefficients): + scaled_lr = coefficients["learning_rate"] + if self._skip_list is None or not any(v in var.name + for v in self._skip_list): + w_norm = linalg_ops.norm(var, ord=2) + g_norm = linalg_ops.norm(grad, ord=2) + trust_ratio = array_ops.where( + math_ops.greater(w_norm, 0), + array_ops.where( + math_ops.greater(g_norm, 0), + (self.eeta * w_norm / + (g_norm + self.weight_decay * w_norm + self.epsilon)), 1.0), 1.0) + + scaled_lr = coefficients["learning_rate"] * trust_ratio + # Add the weight regularization gradient + grad = grad + self.weight_decay * var + return scaled_lr, grad + + def _apply_dense(self, grad, var, apply_state=None): + var_device, var_dtype = var.device, var.dtype.base_dtype + coefficients = ((apply_state or {}).get((var_device, var_dtype)) + or self._fallback_apply_state(var_device, var_dtype)) + + scaled_lr, grad = self.compute_lr(grad, var, coefficients) + mom = self.get_slot(var, "momentum") + return training_ops.apply_momentum( + var, + mom, + math_ops.cast(1.0, var.dtype.base_dtype), + grad * scaled_lr, + self.momentum, + use_locking=False, + use_nesterov=self.use_nesterov) + + def _resource_apply_dense(self, grad, var, apply_state=None): + var_device, var_dtype = var.device, var.dtype.base_dtype + coefficients = ((apply_state or {}).get((var_device, var_dtype)) + or self._fallback_apply_state(var_device, var_dtype)) + + scaled_lr, grad = self.compute_lr(grad, var, coefficients) + mom = self.get_slot(var, "momentum") + # Use ApplyKerasMomentum instead of ApplyMomentum + # training_ops.resource_apply_keras_momentum( + # var.handle, + # mom.handle, + # scaled_lr, + # grad, + # coefficients["momentum"], + # use_locking=False, + # use_nesterov=self.use_nesterov) + + mom_t = mom * self.momentum - grad * scaled_lr + mom_t = state_ops.assign(mom, mom_t, use_locking=False) + if self.use_nesterov: + var_t = var + mom_t * self.momentum - grad * scaled_lr + else: + var_t = var + mom_t + return state_ops.assign(var, var_t, use_locking=False).op + + # Fallback to momentum optimizer for sparse tensors + def _apply_sparse(self, grad, var, apply_state=None): + var_device, var_dtype = var.device, var.dtype.base_dtype + coefficients = ((apply_state or {}).get((var_device, var_dtype)) + or self._fallback_apply_state(var_device, var_dtype)) + + mom = self.get_slot(var, "momentum") + return training_ops.sparse_apply_momentum( + var, + mom, + coefficients["learning_rate"], + grad.values, + grad.indices, + self.momentum, + use_locking=False, + use_nesterov=self.use_nesterov) + + def _resource_apply_sparse(self, grad, var, indices, apply_state=None): + var_device, var_dtype = var.device, var.dtype.base_dtype + coefficients = ((apply_state or {}).get((var_device, var_dtype)) + or self._fallback_apply_state(var_device, var_dtype)) + + mom = self.get_slot(var, "momentum") + return training_ops.resource_sparse_apply_keras_momentum( + var.handle, + mom.handle, + coefficients["learning_rate"], + grad, + indices, + self.momentum, + use_locking=False, + use_nesterov=self.use_nesterov) + + def get_config(self): + config = super(LARSOptimizer, self).get_config() + config.update({ + "learning_rate": self._serialize_hyperparameter("learning_rate"), + "momentum": self.momentum, + "weight_decay": self.weight_decay, + "eeta": self.eeta, + "epsilon": self.epsilon, + "use_nesterov": self.use_nesterov, + }) + return config diff --git a/tinygrad_repo/test/external/mlperf_resnet/lars_util.py b/tinygrad_repo/test/external/mlperf_resnet/lars_util.py new file mode 100644 index 000000000..5fd6337c0 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_resnet/lars_util.py @@ -0,0 +1,179 @@ +# https://github.com/mlcommons/training/blob/e237206991d10449d9675d95606459a3cb6c21ad/image_classification/tensorflow2/lars_util.py +# changes: commented out logging +# changes: convert_to_tensor_v2 -> convert_to_tensor +# changes: extend from tf.python.keras.optimizer_v2.learning_rate_schedule.LearningRateScheduler + +# Copyright 2018 The TensorFlow Authors. All Rights Reserved. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================== +"""Enable Layer-wise Adaptive Rate Scaling optimizer in ResNet.""" + +from __future__ import absolute_import +from __future__ import division +from __future__ import print_function + +from absl import flags +import tensorflow as tf + +#from tf2_common.utils.mlp_log import mlp_log +from tensorflow.python.eager import context +from tensorflow.python.framework import ops +from tensorflow.python.ops import math_ops +from tensorflow.python.keras.optimizer_v2 import learning_rate_schedule + +FLAGS = flags.FLAGS + + +def define_lars_flags(): + """Defines flags needed by LARS optimizer.""" + + flags.DEFINE_float( + 'end_learning_rate', default=None, + help=('Polynomial decay end learning rate.')) + + flags.DEFINE_float( + 'lars_epsilon', default=0.0, + help=('Override autoselected LARS epsilon.')) + + flags.DEFINE_float( + 'warmup_epochs', default=None, + help=('Override autoselected polynomial decay warmup epochs.')) + + flags.DEFINE_float( + 'momentum', + default=0.9, + help=('Momentum parameter used in the MomentumOptimizer.')) + + +class PolynomialDecayWithWarmup(learning_rate_schedule.LearningRateSchedule): + """A LearningRateSchedule that uses a polynomial decay with warmup.""" + + def __init__( + self, + batch_size, + steps_per_epoch, + train_steps, + initial_learning_rate=None, + end_learning_rate=None, + warmup_epochs=None, + compute_lr_on_cpu=False, + name=None): + """Applies a polynomial decay to the learning rate with warmup.""" + super(PolynomialDecayWithWarmup, self).__init__() + + self.batch_size = batch_size + self.steps_per_epoch = steps_per_epoch + self.train_steps = train_steps + self.name = name + self.learning_rate_ops_cache = {} + self.compute_lr_on_cpu = compute_lr_on_cpu + + if batch_size < 16384: + self.initial_learning_rate = 10.0 + warmup_epochs_ = 5 + elif batch_size < 32768: + self.initial_learning_rate = 25.0 + warmup_epochs_ = 5 + else: + self.initial_learning_rate = 31.2 + warmup_epochs_ = 25 + + # Override default poly learning rate and warmup epochs + if initial_learning_rate: + self.initial_learning_rate = initial_learning_rate + + if end_learning_rate: + self.end_learning_rate = end_learning_rate + else: + self.end_learning_rate = 0.0001 + + if warmup_epochs is not None: + warmup_epochs_ = warmup_epochs + self.warmup_epochs = warmup_epochs_ + + """ + opt_name = FLAGS.optimizer.lower() + mlp_log.mlperf_print('opt_name', opt_name) + if opt_name == 'lars': + mlp_log.mlperf_print('{}_epsilon'.format(opt_name), FLAGS.lars_epsilon) + mlp_log.mlperf_print('{}_opt_weight_decay'.format(opt_name), + FLAGS.weight_decay) + mlp_log.mlperf_print('{}_opt_base_learning_rate'.format(opt_name), + self.initial_learning_rate) + mlp_log.mlperf_print('{}_opt_learning_rate_warmup_epochs'.format(opt_name), + warmup_epochs_) + mlp_log.mlperf_print('{}_opt_end_learning_rate'.format(opt_name), + self.end_learning_rate) + """ + warmup_steps = warmup_epochs_ * steps_per_epoch + self.warmup_steps = tf.cast(warmup_steps, tf.float32) + self.decay_steps = train_steps - warmup_steps + 1 + """ + mlp_log.mlperf_print('{}_opt_learning_rate_decay_steps'.format(opt_name), + int(self.decay_steps)) + mlp_log.mlperf_print( + '{}_opt_learning_rate_decay_poly_power'.format(opt_name), 2.0) + mlp_log.mlperf_print('{}_opt_momentum'.format(opt_name), FLAGS.momentum) + """ + + self.poly_rate_scheduler = tf.keras.optimizers.schedules.PolynomialDecay( + initial_learning_rate=self.initial_learning_rate, + decay_steps=self.decay_steps, + end_learning_rate=self.end_learning_rate, + power=2.0) + + def __call__(self, step): + if tf.executing_eagerly(): + return self._get_learning_rate(step) + + # In an eager function or graph, the current implementation of optimizer + # repeatedly call and thus create ops for the learning rate schedule. To + # avoid this, we cache the ops if not executing eagerly. + graph = tf.compat.v1.get_default_graph() + if graph not in self.learning_rate_ops_cache: + if self.compute_lr_on_cpu: + with tf.device('/device:CPU:0'): + self.learning_rate_ops_cache[graph] = self._get_learning_rate(step) + else: + self.learning_rate_ops_cache[graph] = self._get_learning_rate(step) + return self.learning_rate_ops_cache[graph] + + def _get_learning_rate(self, step): + with ops.name_scope_v2(self.name or 'PolynomialDecayWithWarmup') as name: + + initial_learning_rate = ops.convert_to_tensor( + self.initial_learning_rate, name='initial_learning_rate') + warmup_steps = ops.convert_to_tensor( + self.warmup_steps, name='warmup_steps') + + warmup_rate = ( + initial_learning_rate * step / warmup_steps) + + poly_steps = math_ops.subtract(step, warmup_steps) + poly_rate = self.poly_rate_scheduler(poly_steps) + + decay_rate = tf.where(step <= warmup_steps, + warmup_rate, poly_rate, name=name) + return decay_rate + + def get_config(self): + return { + 'batch_size': self.batch_size, + 'steps_per_epoch': self.steps_per_epoch, + 'train_steps': self.train_steps, + 'initial_learning_rate': self.initial_learning_rate, + 'end_learning_rate': self.end_learning_rate, + 'warmup_epochs': self.warmup_epochs, + 'name': self.name, + } diff --git a/tinygrad_repo/test/external/mlperf_retinanet/coco_utils.py b/tinygrad_repo/test/external/mlperf_retinanet/coco_utils.py new file mode 100644 index 000000000..756bd6955 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_retinanet/coco_utils.py @@ -0,0 +1,89 @@ +# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/coco_utils.py + +import os +import torch +import torchvision + +from test.external.mlperf_retinanet import transforms as T + +class ConvertCocoPolysToMask(object): + def __init__(self, filter_iscrowd=True): + self.filter_iscrowd = filter_iscrowd + + def __call__(self, image, target): + w, h = image.size + + image_id = target["image_id"] + image_id = torch.tensor([image_id]) + + anno = target["annotations"] + + if self.filter_iscrowd: + anno = [obj for obj in anno if obj['iscrowd'] == 0] + + boxes = [obj["bbox"] for obj in anno] + # guard against no boxes via resizing + boxes = torch.as_tensor(boxes, dtype=torch.float32).reshape(-1, 4) + boxes[:, 2:] += boxes[:, :2] + boxes[:, 0::2].clamp_(min=0, max=w) + boxes[:, 1::2].clamp_(min=0, max=h) + + classes = [obj["category_id"] for obj in anno] + classes = torch.tensor(classes, dtype=torch.int64) + + keypoints = None + if anno and "keypoints" in anno[0]: + keypoints = [obj["keypoints"] for obj in anno] + keypoints = torch.as_tensor(keypoints, dtype=torch.float32) + num_keypoints = keypoints.shape[0] + if num_keypoints: + keypoints = keypoints.view(num_keypoints, -1, 3) + + keep = (boxes[:, 3] > boxes[:, 1]) & (boxes[:, 2] > boxes[:, 0]) + boxes = boxes[keep] + classes = classes[keep] + + target = {} + target["boxes"] = boxes + target["labels"] = classes + target["image_id"] = image_id + + # for conversion to coco api + area = torch.tensor([obj["area"] for obj in anno]) + iscrowd = torch.tensor([obj["iscrowd"] for obj in anno]) + target["area"] = area + target["iscrowd"] = iscrowd + + return image, target + +class CocoDetection(torchvision.datasets.CocoDetection): + def __init__(self, img_folder, ann_file, transforms): + super(CocoDetection, self).__init__(img_folder, ann_file) + self._transforms = transforms + + def __getitem__(self, idx): + img, target = super(CocoDetection, self).__getitem__(idx) + image_id = self.ids[idx] + target = dict(image_id=image_id, annotations=target) + if self._transforms is not None: + img, target = self._transforms(img, target) + return img, target + +def get_openimages(name, root, image_set, transforms): + PATHS = { + "train": os.path.join(root, "train"), + "val": os.path.join(root, "validation"), + } + + t = [ConvertCocoPolysToMask(filter_iscrowd=False)] + + if transforms is not None: + t.append(transforms) + transforms = T.Compose(t) + + img_folder = os.path.join(PATHS[image_set], "data") + ann_file = os.path.join(PATHS[image_set], "labels", f"{name}.json") + + dataset = CocoDetection(img_folder, ann_file, transforms=transforms) + + return dataset \ No newline at end of file diff --git a/tinygrad_repo/test/external/mlperf_retinanet/focal_loss.py b/tinygrad_repo/test/external/mlperf_retinanet/focal_loss.py new file mode 100644 index 000000000..7167b58a1 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_retinanet/focal_loss.py @@ -0,0 +1,51 @@ +# Copied from https://github.com/mlcommons/training/blob/cdd928d4596c142c15a7d86b2eeadbac718c8da2/single_stage_detector/ssd/model/focal_loss.py + +import torch +import torch.nn.functional as F + + +def sigmoid_focal_loss( + inputs: torch.Tensor, + targets: torch.Tensor, + alpha: float = 0.25, + gamma: float = 2, + reduction: str = "none", +): + """ + Original implementation from https://github.com/facebookresearch/fvcore/blob/master/fvcore/nn/focal_loss.py . + Loss used in RetinaNet for dense detection: https://arxiv.org/abs/1708.02002. + + Args: + inputs: A float tensor of arbitrary shape. + The predictions for each example. + targets: A float tensor with the same shape as inputs. Stores the binary + classification label for each element in inputs + (0 for the negative class and 1 for the positive class). + alpha: (optional) Weighting factor in range (0,1) to balance + positive vs negative examples or -1 for ignore. Default = 0.25 + gamma: Exponent of the modulating factor (1 - p_t) to + balance easy vs hard examples. + reduction: 'none' | 'mean' | 'sum' + 'none': No reduction will be applied to the output. + 'mean': The output will be averaged. + 'sum': The output will be summed. + Returns: + Loss tensor with the reduction option applied. + """ + p = torch.sigmoid(inputs) + ce_loss = F.binary_cross_entropy_with_logits( + inputs, targets, reduction="none" + ) + p_t = p * targets + (1 - p) * (1 - targets) + loss = ce_loss * ((1 - p_t) ** gamma) + + if alpha >= 0: + alpha_t = alpha * targets + (1 - alpha) * (1 - targets) + loss = alpha_t * loss + + if reduction == "mean": + loss = loss.mean() + elif reduction == "sum": + loss = loss.sum() + + return loss \ No newline at end of file diff --git a/tinygrad_repo/test/external/mlperf_retinanet/model/boxes.py b/tinygrad_repo/test/external/mlperf_retinanet/model/boxes.py new file mode 100644 index 000000000..96dbceeb9 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_retinanet/model/boxes.py @@ -0,0 +1,65 @@ +# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/model/boxes.py + +import torch +from torch import Tensor +from typing import Tuple + +def _upcast(t: Tensor) -> Tensor: + # Protects from numerical overflows in multiplications by upcasting to the equivalent higher type + if t.is_floating_point(): + return t if t.dtype in (torch.float32, torch.float64) else t.float() + else: + return t if t.dtype in (torch.int32, torch.int64) else t.int() + + +def box_area(boxes: Tensor) -> Tensor: + """ + Computes the area of a set of bounding boxes, which are specified by their + (x1, y1, x2, y2) coordinates. + + Args: + boxes (Tensor[N, 4]): boxes for which the area will be computed. They + are expected to be in (x1, y1, x2, y2) format with + ``0 <= x1 < x2`` and ``0 <= y1 < y2``. + + Returns: + Tensor[N]: the area for each box + """ + boxes = _upcast(boxes) + return (boxes[:, 2] - boxes[:, 0]) * (boxes[:, 3] - boxes[:, 1]) + + +# implementation from https://github.com/kuangliu/torchcv/blob/master/torchcv/utils/box.py +# with slight modifications +def _box_inter_union(boxes1: Tensor, boxes2: Tensor) -> Tuple[Tensor, Tensor]: + area1 = box_area(boxes1) + area2 = box_area(boxes2) + + lt = torch.max(boxes1[:, None, :2], boxes2[:, :2]) # [N,M,2] + rb = torch.min(boxes1[:, None, 2:], boxes2[:, 2:]) # [N,M,2] + + wh = _upcast(rb - lt).clamp(min=0) # [N,M,2] + inter = wh[:, :, 0] * wh[:, :, 1] # [N,M] + + union = area1[:, None] + area2 - inter + + return inter, union + + +def box_iou(boxes1: Tensor, boxes2: Tensor) -> Tensor: + """ + Return intersection-over-union (Jaccard index) between two sets of boxes. + + Both sets of boxes are expected to be in ``(x1, y1, x2, y2)`` format with + ``0 <= x1 < x2`` and ``0 <= y1 < y2``. + + Args: + boxes1 (Tensor[N, 4]): first set of boxes + boxes2 (Tensor[M, 4]): second set of boxes + + Returns: + Tensor[N, M]: the NxM matrix containing the pairwise IoU values for every element in boxes1 and boxes2 + """ + inter, union = _box_inter_union(boxes1, boxes2) + iou = inter / union + return iou \ No newline at end of file diff --git a/tinygrad_repo/test/external/mlperf_retinanet/model/image_list.py b/tinygrad_repo/test/external/mlperf_retinanet/model/image_list.py new file mode 100644 index 000000000..f7a4cf2eb --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_retinanet/model/image_list.py @@ -0,0 +1,27 @@ +# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/model/image_list.py + +import torch +from torch import Tensor +from typing import List, Tuple + + +class ImageList(object): + """ + Structure that holds a list of images (of possibly + varying sizes) as a single tensor. + This works by padding the images to the same size, + and storing in a field the original sizes of each image + """ + + def __init__(self, tensors: Tensor, image_sizes: List[Tuple[int, int]]): + """ + Args: + tensors (tensor) + image_sizes (list[tuple[int, int]]) + """ + self.tensors = tensors + self.image_sizes = image_sizes + + def to(self, device: torch.device) -> 'ImageList': + cast_tensor = self.tensors.to(device) + return ImageList(cast_tensor, self.image_sizes) \ No newline at end of file diff --git a/tinygrad_repo/test/external/mlperf_retinanet/model/transform.py b/tinygrad_repo/test/external/mlperf_retinanet/model/transform.py new file mode 100644 index 000000000..b68e8cfb2 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_retinanet/model/transform.py @@ -0,0 +1,163 @@ +# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/model/transform.py + +import torch + +from torch import nn, Tensor +from typing import List, Tuple, Dict, Optional + +from test.external.mlperf_retinanet.model.image_list import ImageList + +@torch.jit.unused +def _get_shape_onnx(image: Tensor) -> Tensor: + from torch.onnx import operators + return operators.shape_as_tensor(image)[-2:] + +def _resize_image_and_masks(image: Tensor, + target: Optional[Dict[str, Tensor]] = None, + image_size: Optional[Tuple[int, int]] = None, + ) -> Tuple[Tensor, Optional[Dict[str, Tensor]]]: + image = torch.nn.functional.interpolate(image[None], size=image_size, scale_factor=None, mode='bilinear', + recompute_scale_factor=None, align_corners=False)[0] + + if target is None: + return image, target + + if "masks" in target: + mask = target["masks"] + mask = torch.nn.functional.interpolate(mask[:, None].float(), size=image_size, scale_factor=None, + recompute_scale_factor=None)[:, 0].byte() + target["masks"] = mask + return image, target + +class GeneralizedRCNNTransform(nn.Module): + """ + Performs input / target transformation before feeding the data to a GeneralizedRCNN + model. + + The transformations it perform are: + - input normalization (mean subtraction and std division) + - input / target resizing to match image_size + + It returns a ImageList for the inputs, and a List[Dict[Tensor]] for the targets + """ + + def __init__(self, image_size: Optional[Tuple[int, int]], + image_mean: List[float], image_std: List[float],): + super(GeneralizedRCNNTransform, self).__init__() + self.image_size = image_size + self.image_mean = image_mean + self.image_std = image_std + + def forward(self, + images: List[Tensor], + targets: Optional[List[Dict[str, Tensor]]] = None + ) -> Tuple[ImageList, Optional[List[Dict[str, Tensor]]]]: + images = list(img for img in images) + if targets is not None: + # make a copy of targets to avoid modifying it in-place + # once torchscript supports dict comprehension + # this can be simplified as follows + # targets = [{k: v for k,v in t.items()} for t in targets] + targets_copy: List[Dict[str, Tensor]] = [] + for t in targets: + data: Dict[str, Tensor] = {} + for k, v in t.items(): + data[k] = v + targets_copy.append(data) + targets = targets_copy + for i in range(len(images)): + image = images[i] + target_index = targets[i] if targets is not None else None + + if image.dim() != 3: + raise ValueError("images is expected to be a list of 3d tensors " + "of shape [C, H, W], got {}".format(image.shape)) + image = self.normalize(image) + image, target_index = self.resize(image, target_index) + images[i] = image + if targets is not None and target_index is not None: + targets[i] = target_index + + image_sizes = [img.shape[-2:] for img in images] + images = torch.stack(images) + image_sizes_list: List[Tuple[int, int]] = [] + for image_size in image_sizes: + assert len(image_size) == 2 + image_sizes_list.append((image_size[0], image_size[1])) + + image_list = ImageList(images, image_sizes_list) + return image_list, targets + + def normalize(self, image: Tensor) -> Tensor: + if not image.is_floating_point(): + raise TypeError( + f"Expected input images to be of floating type (in range [0, 1]), " + f"but found type {image.dtype} instead" + ) + dtype, device = image.dtype, image.device + mean = torch.as_tensor(self.image_mean, dtype=dtype, device=device) + std = torch.as_tensor(self.image_std, dtype=dtype, device=device) + return (image - mean[:, None, None]) / std[:, None, None] + + def torch_choice(self, k: List[int]) -> int: + """ + Implements `random.choice` via torch ops so it can be compiled with + TorchScript. Remove if https://github.com/pytorch/pytorch/issues/25803 + is fixed. + """ + index = int(torch.empty(1).uniform_(0., float(len(k))).item()) + return k[index] + + def resize(self, + image: Tensor, + target: Optional[Dict[str, Tensor]] = None, + ) -> Tuple[Tensor, Optional[Dict[str, Tensor]]]: + h, w = image.shape[-2:] + image, target = _resize_image_and_masks(image, target, self.image_size) + + if target is None: + return image, target + + bbox = target["boxes"] + bbox = resize_boxes(bbox, (h, w), image.shape[-2:]) + target["boxes"] = bbox + + return image, target + + def postprocess(self, + result: List[Dict[str, Tensor]], + image_shapes: List[Tuple[int, int]], + original_image_sizes: List[Tuple[int, int]] + ) -> List[Dict[str, Tensor]]: + if self.training: + return result + for i, (pred, im_s, o_im_s) in enumerate(zip(result, image_shapes, original_image_sizes)): + boxes = pred["boxes"] + boxes = resize_boxes(boxes, im_s, o_im_s) + result[i]["boxes"] = boxes + return result + + def __repr__(self) -> str: + format_string = self.__class__.__name__ + '(' + _indent = '\n ' + format_string += "{0}Normalize(mean={1}, std={2})".format(_indent, self.image_mean, self.image_std) + format_string += "{0}Resize(height={1}, width={2}, mode='bilinear')".format(_indent, self.image_size[0], + self.image_size[1]) + format_string += '\n)' + return format_string + +def resize_boxes(boxes: Tensor, original_size: List[int], new_size: List[int]) -> Tensor: + ratios = [ + torch.tensor(s, dtype=torch.float32, device=boxes.device) / + torch.tensor(s_orig, dtype=torch.float32, device=boxes.device) + for s, s_orig in zip(new_size, original_size) + ] + ratio_height, ratio_width = ratios + xmin, ymin, xmax, ymax = boxes.unbind(1) + + xmin = xmin * ratio_width + xmax = xmax * ratio_width + ymin = ymin * ratio_height + ymax = ymax * ratio_height + res = torch.stack((xmin, ymin, xmax, ymax), dim=1) + return res \ No newline at end of file diff --git a/tinygrad_repo/test/external/mlperf_retinanet/model/utils.py b/tinygrad_repo/test/external/mlperf_retinanet/model/utils.py new file mode 100644 index 000000000..33c64c16c --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_retinanet/model/utils.py @@ -0,0 +1,123 @@ +# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/model/utils.py + +import torch + +class Matcher(object): + """ + This class assigns to each predicted "element" (e.g., a box) a ground-truth + element. Each predicted element will have exactly zero or one matches; each + ground-truth element may be assigned to zero or more predicted elements. + + Matching is based on the MxN match_quality_matrix, that characterizes how well + each (ground-truth, predicted)-pair match. For example, if the elements are + boxes, the matrix may contain box IoU overlap values. + + The matcher returns a tensor of size N containing the index of the ground-truth + element m that matches to prediction n. If there is no match, a negative value + is returned. + """ + + BELOW_LOW_THRESHOLD = -1 + BETWEEN_THRESHOLDS = -2 + + __annotations__ = { + 'BELOW_LOW_THRESHOLD': int, + 'BETWEEN_THRESHOLDS': int, + } + + def __init__(self, high_threshold, low_threshold, allow_low_quality_matches=False): + # type: (float, float, bool) -> None + """ + Args: + high_threshold (float): quality values greater than or equal to + this value are candidate matches. + low_threshold (float): a lower quality threshold used to stratify + matches into three levels: + 1) matches >= high_threshold + 2) BETWEEN_THRESHOLDS matches in [low_threshold, high_threshold) + 3) BELOW_LOW_THRESHOLD matches in [0, low_threshold) + allow_low_quality_matches (bool): if True, produce additional matches + for predictions that have only low-quality match candidates. See + set_low_quality_matches_ for more details. + """ + self.BELOW_LOW_THRESHOLD = -1 + self.BETWEEN_THRESHOLDS = -2 + assert low_threshold <= high_threshold + self.high_threshold = high_threshold + self.low_threshold = low_threshold + self.allow_low_quality_matches = allow_low_quality_matches + + def __call__(self, match_quality_matrix): + """ + Args: + match_quality_matrix (Tensor[float]): an MxN tensor, containing the + pairwise quality between M ground-truth elements and N predicted elements. + + Returns: + matches (Tensor[int64]): an N tensor where N[i] is a matched gt in + [0, M - 1] or a negative value indicating that prediction i could not + be matched. + """ + if match_quality_matrix.numel() == 0: + # empty targets or proposals not supported during training + if match_quality_matrix.shape[0] == 0: + raise ValueError( + "No ground-truth boxes available for one of the images " + "during training") + + raise ValueError( + "No proposal boxes available for one of the images " + "during training") + + # match_quality_matrix is M (gt) x N (predicted) + # Max over gt elements (dim 0) to find best gt candidate for each prediction + matched_vals, matches = match_quality_matrix.max(dim=0) + if self.allow_low_quality_matches: + all_matches = matches.clone() + else: + all_matches = None + + # Assign candidate matches with low quality to negative (unassigned) values + below_low_threshold = matched_vals < self.low_threshold + between_thresholds = (matched_vals >= self.low_threshold) & ( + matched_vals < self.high_threshold + ) + matches[below_low_threshold] = self.BELOW_LOW_THRESHOLD + matches[between_thresholds] = self.BETWEEN_THRESHOLDS + + if self.allow_low_quality_matches: + assert all_matches is not None + self.set_low_quality_matches_(matches, all_matches, match_quality_matrix) + + return matches + + def set_low_quality_matches_(self, matches, all_matches, match_quality_matrix): + """ + Produce additional matches for predictions that have only low-quality matches. + Specifically, for each ground-truth find the set of predictions that have + maximum overlap with it (including ties); for each prediction in that set, if + it is unmatched, then match it to the ground-truth with which it has the highest + quality value. + """ + # For each gt, find the prediction with which it has highest quality + highest_quality_foreach_gt, _ = match_quality_matrix.max(dim=1) + # Find highest quality match available, even if it is low, including ties + gt_pred_pairs_of_highest_quality = torch.where( + match_quality_matrix == highest_quality_foreach_gt[:, None] + ) + # Example gt_pred_pairs_of_highest_quality: + # tensor([[ 0, 39796], + # [ 1, 32055], + # [ 1, 32070], + # [ 2, 39190], + # [ 2, 40255], + # [ 3, 40390], + # [ 3, 41455], + # [ 4, 45470], + # [ 5, 45325], + # [ 5, 46390]]) + # Each row is a (gt index, prediction index) + # Note how gt items 1, 2, 3, and 5 each have two ties + + pred_inds_to_update = gt_pred_pairs_of_highest_quality[1] + matches[pred_inds_to_update] = all_matches[pred_inds_to_update] \ No newline at end of file diff --git a/tinygrad_repo/test/external/mlperf_retinanet/openimages.py b/tinygrad_repo/test/external/mlperf_retinanet/openimages.py new file mode 100644 index 000000000..d77c99d78 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_retinanet/openimages.py @@ -0,0 +1,25 @@ +from test.external.mlperf_retinanet.model.boxes import box_iou +from test.external.mlperf_retinanet.model.utils import Matcher + +import torch + +# This applies the filtering in https://github.com/mlcommons/training/blob/cdd928d4596c142c15a7d86b2eeadbac718c8da2/single_stage_detector/ssd/model/retinanet.py#L117 +# and https://github.com/mlcommons/training/blob/cdd928d4596c142c15a7d86b2eeadbac718c8da2/single_stage_detector/ssd/model/retinanet.py#L203 +# to match with tinygrad's dataloader implementation. +def postprocess_targets(targets, anchors): + proposal_matcher, matched_idxs = Matcher(0.5, 0.4, allow_low_quality_matches=True), [] + for anchors_per_image, targets_per_image in zip(anchors, targets): + if targets_per_image['boxes'].numel() == 0: + matched_idxs.append(torch.full((anchors_per_image.size(0),), -1, dtype=torch.int64, + device=anchors_per_image.device)) + continue + + match_quality_matrix = box_iou(targets_per_image['boxes'], anchors_per_image) + matched_idxs.append(proposal_matcher(match_quality_matrix)) + + for targets_per_image, matched_idxs_per_image in zip(targets, matched_idxs): + foreground_idxs_per_image = matched_idxs_per_image >= 0 + targets_per_image["boxes"] = targets_per_image["boxes"][matched_idxs_per_image[foreground_idxs_per_image]] + targets_per_image["labels"] = targets_per_image["labels"][matched_idxs_per_image[foreground_idxs_per_image]] + + return targets diff --git a/tinygrad_repo/test/external/mlperf_retinanet/presets.py b/tinygrad_repo/test/external/mlperf_retinanet/presets.py new file mode 100644 index 000000000..fb918581b --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_retinanet/presets.py @@ -0,0 +1,24 @@ +# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/presets.py + +from test.external.mlperf_retinanet import transforms as T + +class DetectionPresetTrain: + def __init__(self, data_augmentation, hflip_prob=0.5, mean=(123., 117., 104.)): + if data_augmentation == 'hflip': + self.transforms = T.Compose([ + T.RandomHorizontalFlip(p=hflip_prob), + T.ToTensor(), + ]) + else: + raise ValueError(f'Unknown data augmentation policy "{data_augmentation}"') + + def __call__(self, img, target): + return self.transforms(img, target) + + +class DetectionPresetEval: + def __init__(self): + self.transforms = T.ToTensor() + + def __call__(self, img, target): + return self.transforms(img, target) \ No newline at end of file diff --git a/tinygrad_repo/test/external/mlperf_retinanet/transforms.py b/tinygrad_repo/test/external/mlperf_retinanet/transforms.py new file mode 100644 index 000000000..0a35347d1 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_retinanet/transforms.py @@ -0,0 +1,77 @@ +# Copied from https://github.com/mlcommons/training/blob/637c82f9e699cd6caf108f92efb2c1d446b630e0/single_stage_detector/ssd/transforms.py + +import torch +import torchvision + +from torch import nn, Tensor +from torchvision.transforms import functional as F +from torchvision.transforms import transforms as T +from typing import List, Tuple, Dict, Optional + +from PIL import Image +Image.MAX_IMAGE_PIXELS = None +from typing import Any + +try: + import accimage +except ImportError: + accimage = None + +@torch.jit.unused +def _is_pil_image(img: Any) -> bool: + if accimage is not None: + return isinstance(img, (Image.Image, accimage.Image)) + else: + return isinstance(img, Image.Image) + +def get_image_size_tensor(img: Tensor) -> List[int]: + # Returns (w, h) of tensor image + torchvision.transforms._functional_tensor._assert_image_tensor(img) + return [img.shape[-1], img.shape[-2]] + +@torch.jit.unused +def get_image_size_pil(img: Any) -> List[int]: + if _is_pil_image(img): + return list(img.size) + raise TypeError("Unexpected type {}".format(type(img))) + +def get_image_size(img: Tensor) -> List[int]: + """Returns the size of an image as [width, height]. + Args: + img (PIL Image or Tensor): The image to be checked. + Returns: + List[int]: The image size. + """ + if isinstance(img, torch.Tensor): + return get_image_size_tensor(img) + + return get_image_size_pil(img) + +class Compose(object): + def __init__(self, transforms): + self.transforms = transforms + + def __call__(self, image, target): + for t in self.transforms: + image, target = t(image, target) + return image, target + + +class RandomHorizontalFlip(T.RandomHorizontalFlip): + def forward(self, image: Tensor, + target: Optional[Dict[str, Tensor]] = None) -> Tuple[Tensor, Optional[Dict[str, Tensor]]]: + if torch.rand(1) < self.p: + image = F.hflip(image) + if target is not None: + width, _ = get_image_size(image) + target["boxes"][:, [0, 2]] = width - target["boxes"][:, [2, 0]] + if "masks" in target: + target["masks"] = target["masks"].flip(-1) + return image, target + + +class ToTensor(nn.Module): + def forward(self, image: Tensor, + target: Optional[Dict[str, Tensor]] = None) -> Tuple[Tensor, Optional[Dict[str, Tensor]]]: + image = F.to_tensor(image) + return image, target \ No newline at end of file diff --git a/tinygrad_repo/test/external/mlperf_unet3d/dice.py b/tinygrad_repo/test/external/mlperf_unet3d/dice.py new file mode 100644 index 000000000..fd236d2b1 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_unet3d/dice.py @@ -0,0 +1,94 @@ +# https://github.com/mlcommons/training/blob/master/image_segmentation/pytorch/model/losses.py + +import torch +import torch.nn as nn +import torch.nn.functional as F + + +class Dice: + def __init__(self, + to_onehot_y: bool = True, + to_onehot_x: bool = False, + use_softmax: bool = True, + use_argmax: bool = False, + include_background: bool = False, + layout: str = "NCDHW"): + self.include_background = include_background + self.to_onehot_y = to_onehot_y + self.to_onehot_x = to_onehot_x + self.use_softmax = use_softmax + self.use_argmax = use_argmax + self.smooth_nr = 1e-6 + self.smooth_dr = 1e-6 + self.layout = layout + + def __call__(self, prediction, target): + if self.layout == "NCDHW": + channel_axis = 1 + reduce_axis = list(range(2, len(prediction.shape))) + else: + channel_axis = -1 + reduce_axis = list(range(1, len(prediction.shape) - 1)) + num_pred_ch = prediction.shape[channel_axis] + + if self.use_softmax: + prediction = torch.softmax(prediction, dim=channel_axis) + elif self.use_argmax: + prediction = torch.argmax(prediction, dim=channel_axis) + + if self.to_onehot_y: + target = to_one_hot(target, self.layout, channel_axis) + + if self.to_onehot_x: + prediction = to_one_hot(prediction, self.layout, channel_axis) + + if not self.include_background: + assert num_pred_ch > 1, \ + f"To exclude background the prediction needs more than one channel. Got {num_pred_ch}." + if self.layout == "NCDHW": + target = target[:, 1:] + prediction = prediction[:, 1:] + else: + target = target[..., 1:] + prediction = prediction[..., 1:] + + assert (target.shape == prediction.shape), \ + f"Target and prediction shape do not match. Target: ({target.shape}), prediction: ({prediction.shape})." + + intersection = torch.sum(target * prediction, dim=reduce_axis) + target_sum = torch.sum(target, dim=reduce_axis) + prediction_sum = torch.sum(prediction, dim=reduce_axis) + + return (2.0 * intersection + self.smooth_nr) / (target_sum + prediction_sum + self.smooth_dr) + + +def to_one_hot(array, layout, channel_axis): + if len(array.shape) >= 5: + array = torch.squeeze(array, dim=channel_axis) + array = F.one_hot(array.long(), num_classes=3) + if layout == "NCDHW": + array = array.permute(0, 4, 1, 2, 3).float() + return array + + +class DiceCELoss(nn.Module): + def __init__(self, to_onehot_y, use_softmax, layout, include_background): + super(DiceCELoss, self).__init__() + self.dice = Dice(to_onehot_y=to_onehot_y, use_softmax=use_softmax, layout=layout, + include_background=include_background) + self.cross_entropy = nn.CrossEntropyLoss() + + def forward(self, y_pred, y_true): + cross_entropy = self.cross_entropy(y_pred, torch.squeeze(y_true, dim=1).long()) + dice = torch.mean(1.0 - self.dice(y_pred, y_true)) + return (dice + cross_entropy) / 2 + + +class DiceScore: + def __init__(self, to_onehot_y: bool = True, use_argmax: bool = True, layout: str = "NCDHW", + include_background: bool = False): + self.dice = Dice(to_onehot_y=to_onehot_y, to_onehot_x=True, use_softmax=False, + use_argmax=use_argmax, layout=layout, include_background=include_background) + + def __call__(self, y_pred, y_true): + return torch.mean(self.dice(y_pred, y_true), dim=0) diff --git a/tinygrad_repo/test/external/mlperf_unet3d/kits19.py b/tinygrad_repo/test/external/mlperf_unet3d/kits19.py new file mode 100644 index 000000000..ac8a918a8 --- /dev/null +++ b/tinygrad_repo/test/external/mlperf_unet3d/kits19.py @@ -0,0 +1,165 @@ +# copied from https://github.com/mlcommons/training/blob/5c08ce57e7f582cc4558035d8324a2bf4c8ca225/image_segmentation/pytorch/data_loading/pytorch_loader.py + +import random +import numpy as np +import scipy.ndimage +from torch.utils.data import Dataset +from torchvision import transforms + + +def get_train_transforms(): + rand_flip = RandFlip() + cast = Cast(types=(np.float32, np.uint8)) + rand_scale = RandomBrightnessAugmentation(factor=0.3, prob=0.1) + rand_noise = GaussianNoise(mean=0.0, std=0.1, prob=0.1) + train_transforms = transforms.Compose([rand_flip, cast, rand_scale, rand_noise]) + return train_transforms + + +class RandBalancedCrop: + def __init__(self, patch_size, oversampling): + self.patch_size = patch_size + self.oversampling = oversampling + + def __call__(self, data): + image, label = data["image"], data["label"] + if random.random() < self.oversampling: + image, label, cords = self.rand_foreg_cropd(image, label) + else: + image, label, cords = self._rand_crop(image, label) + data.update({"image": image, "label": label}) + return data + + @staticmethod + def randrange(max_range): + return 0 if max_range == 0 else random.randrange(max_range) + + def get_cords(self, cord, idx): + return cord[idx], cord[idx] + self.patch_size[idx] + + def _rand_crop(self, image, label): + ranges = [s - p for s, p in zip(image.shape[1:], self.patch_size)] + cord = [self.randrange(x) for x in ranges] + low_x, high_x = self.get_cords(cord, 0) + low_y, high_y = self.get_cords(cord, 1) + low_z, high_z = self.get_cords(cord, 2) + image = image[:, low_x:high_x, low_y:high_y, low_z:high_z] + label = label[:, low_x:high_x, low_y:high_y, low_z:high_z] + return image, label, [low_x, high_x, low_y, high_y, low_z, high_z] + + def rand_foreg_cropd(self, image, label): + def adjust(foreg_slice, patch_size, label, idx): + diff = patch_size[idx - 1] - (foreg_slice[idx].stop - foreg_slice[idx].start) + sign = -1 if diff < 0 else 1 + diff = abs(diff) + ladj = self.randrange(diff) + hadj = diff - ladj + low = max(0, foreg_slice[idx].start - sign * ladj) + high = min(label.shape[idx], foreg_slice[idx].stop + sign * hadj) + diff = patch_size[idx - 1] - (high - low) + if diff > 0 and low == 0: + high += diff + elif diff > 0: + low -= diff + return low, high + + cl = np.random.choice(np.unique(label[label > 0])) + foreg_slices = scipy.ndimage.find_objects(scipy.ndimage.measurements.label(label==cl)[0]) + foreg_slices = [x for x in foreg_slices if x is not None] + slice_volumes = [np.prod([s.stop - s.start for s in sl]) for sl in foreg_slices] + slice_idx = np.argsort(slice_volumes)[-2:] + foreg_slices = [foreg_slices[i] for i in slice_idx] + if not foreg_slices: + return self._rand_crop(image, label) + foreg_slice = foreg_slices[random.randrange(len(foreg_slices))] + low_x, high_x = adjust(foreg_slice, self.patch_size, label, 1) + low_y, high_y = adjust(foreg_slice, self.patch_size, label, 2) + low_z, high_z = adjust(foreg_slice, self.patch_size, label, 3) + image = image[:, low_x:high_x, low_y:high_y, low_z:high_z] + label = label[:, low_x:high_x, low_y:high_y, low_z:high_z] + return image, label, [low_x, high_x, low_y, high_y, low_z, high_z] + + +class RandFlip: + def __init__(self): + self.axis = [1, 2, 3] + self.prob = 1 / len(self.axis) + + def flip(self, data, axis): + data["image"] = np.flip(data["image"], axis=axis).copy() + data["label"] = np.flip(data["label"], axis=axis).copy() + return data + + def __call__(self, data): + for axis in self.axis: + if random.random() < self.prob: + data = self.flip(data, axis) + return data + + +class Cast: + def __init__(self, types): + self.types = types + + def __call__(self, data): + data["image"] = data["image"].astype(self.types[0]) + data["label"] = data["label"].astype(self.types[1]) + return data + + +class RandomBrightnessAugmentation: + def __init__(self, factor, prob): + self.prob = prob + self.factor = factor + + def __call__(self, data): + image = data["image"] + if random.random() < self.prob: + factor = np.random.uniform(low=1.0-self.factor, high=1.0+self.factor, size=1) + image = (image * (1 + factor)).astype(image.dtype) + data.update({"image": image}) + return data + + +class GaussianNoise: + def __init__(self, mean, std, prob): + self.mean = mean + self.std = std + self.prob = prob + + def __call__(self, data): + image = data["image"] + if random.random() < self.prob: + scale = np.random.uniform(low=0.0, high=self.std) + noise = np.random.normal(loc=self.mean, scale=scale, size=image.shape).astype(image.dtype) + data.update({"image": image + noise}) + return data + + +class PytTrain(Dataset): + def __init__(self, images, labels, **kwargs): + self.images, self.labels = images, labels + self.train_transforms = get_train_transforms() + patch_size, oversampling = kwargs["patch_size"], kwargs["oversampling"] + self.patch_size = patch_size + self.rand_crop = RandBalancedCrop(patch_size=patch_size, oversampling=oversampling) + + def __len__(self): + return len(self.images) + + def __getitem__(self, idx): + data = {"image": np.load(self.images[idx]), "label": np.load(self.labels[idx])} + data = self.rand_crop(data) + data = self.train_transforms(data) + return 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By default, process replay doesn't assert kernel diffs. + +Refactor and speedup PRs must enable the assert by including `[pr]` in the pull request title. + +Note that process replay [early stops when over 20% of kernels change, for speed.](https://github.com/tinygrad/tinygrad/pull/5480). + +## Running locally + +To run process replay locally: + +(optional: clear previous process replay runs with `test/external/process_replay/reset.py`) + +1. Run tests with `CAPTURE_PROCESS_REPLAY=1` in your branch. This will pickle process inputs to CACHEDB. +2. Checkout master +3. Run `test/external/process_replay/process_replay.py` + +For reference, see `test/external/process_replay/local.sh`. diff --git a/tinygrad_repo/test/external/process_replay/local.sh b/tinygrad_repo/test/external/process_replay/local.sh new file mode 100755 index 000000000..0d7997334 --- /dev/null +++ b/tinygrad_repo/test/external/process_replay/local.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +set -e +HEAD=$(git rev-parse --abbrev-ref HEAD) +python test/external/process_replay/reset.py +CAPTURE_PROCESS_REPLAY=1 python test/test_ops.py TestOps.test_add +git checkout master +git checkout $HEAD -- test/external/process_replay/process_replay.py +ASSERT_PROCESS_REPLAY=${ASSERT_PROCESS_REPLAY:-1} python test/external/process_replay/process_replay.py +git checkout $HEAD diff --git a/tinygrad_repo/test/external/process_replay/process_replay.py b/tinygrad_repo/test/external/process_replay/process_replay.py new file mode 100755 index 000000000..d26de0116 --- /dev/null +++ b/tinygrad_repo/test/external/process_replay/process_replay.py @@ -0,0 +1,105 @@ +#!/usr/bin/env python3 +# compare kernels created by HEAD against master +import os, multiprocessing, logging, pickle, sqlite3, difflib, warnings, itertools +from typing import Callable, Any +from tinygrad.helpers import VERSION, Context, ContextVar, colored, db_connection, getenv, tqdm +from tinygrad.kernelize.kernelize import get_kernelize_map +from tinygrad.renderer import Renderer, ProgramSpec +from tinygrad.engine.realize import get_program +from tinygrad.uop.ops import UOp, Ops, KernelInfo + +# *** process replay settings + +# internal +PAGE_SIZE = getenv("PAGE_SIZE", 100) +REF = os.getenv("GITHUB_REF_NAME", "") +MAX_DIFF_PCT = getenv("PROCESS_REPLAY_MAX_DIFF_PCT", 20) +TABLE_NAME = f"process_replay_{VERSION}" +os.environ["CAPTURE_PROCESS_REPLAY"] = "0" +early_stop = multiprocessing.Event() +logging.basicConfig(level=logging.INFO, format="%(message)s") +MAX_LINES = 500 +def trunc_log(x): + if len(lines:=repr(x).splitlines()) > MAX_LINES: lines = lines[:MAX_LINES]+[f"WARN: truncated string with {len(lines)} lines"] + logging.info("\n".join(lines)) + +# user config +ASSERT_DIFF = int((flag:="[pr]") in os.getenv("COMMIT_MESSAGE", flag) or flag in os.getenv("PR_TITLE", flag)) +if not getenv("ASSERT_PROCESS_REPLAY", 1): ASSERT_DIFF = 0 +SKIP_PROCESS_REPLAY = (k:="[skip_process_replay]") in os.getenv("COMMIT_MESSAGE", "") or k in os.getenv("PR_TITLE", "") +if REF == "master": SKIP_PROCESS_REPLAY = True +class ProcessReplayWarning(Warning): pass + +# *** replay the function and convert return values to string + +def replay_kernelize(ret:dict[UOp, UOp], big_sink:UOp) -> tuple[str, str, tuple[Any, ...]]: + UOp.unique_num = itertools.count(max([u.arg for u in big_sink.toposort() if u.op is Ops.UNIQUE], default=0)+1) + new_sink = big_sink.substitute(get_kernelize_map(big_sink)) + def to_str(ret:UOp) -> str: + asts = [repr(u.arg.ast) for u in ret.toposort() if u.op is Ops.KERNEL] + return "\n".join([f"{len(asts)} kernels", *asts]) + return to_str(new_sink), to_str(ret[big_sink]), (big_sink,) + +def replay_get_program(p:ProgramSpec, ast:UOp, renderer:Renderer) -> tuple[str, str, tuple[Any, ...]]: + p2 = get_program(ast.replace(arg=KernelInfo(opts_to_apply=p.applied_opts, name=p.name)) if ast.arg is None else ast, renderer) + def to_str(ret:ProgramSpec) -> str: return ret.src + return to_str(p2), to_str(p), (p.ast, renderer, p.applied_opts) + +replayers: dict[str, Callable[..., tuple[str, str, tuple[Any, ...]]]] = {"get_kernelize_map":replay_kernelize, "get_program":replay_get_program} + +# *** run replayers on captured rows and print diffs + +def diff(offset:int) -> None: + if ASSERT_DIFF: warnings.filterwarnings("error", category=ProcessReplayWarning) + if early_stop.is_set(): return None + conn = db_connection() + cur = conn.cursor() + cur.execute(f"SELECT val FROM '{TABLE_NAME}' LIMIT ? OFFSET ?", (PAGE_SIZE, offset)) + changed = 0 + for row in cur.fetchall(): + if changed > MAX_DIFF_PCT: + warnings.warn(f"detected changes in over {MAX_DIFF_PCT}%. skipping further diff generation.", ProcessReplayWarning) + early_stop.set() + break + try: + name, args, kwargs, ctx_vals, loc, ret = pickle.loads(row[0]) + ctx_vars = {k:v.value for k,v in ctx_vals.items() if k != "DEBUG" and (var:=ContextVar._cache.get(k)) is not None and var.value != v.value} + if (replayer:=replayers.get(name)) is None: continue + with Context(**ctx_vars): good, compare, metadata = replayer(ret, *args, **kwargs) + if good != compare: + for m in metadata: trunc_log(m) + logging.info(loc) + for line in difflib.unified_diff(good.splitlines(), compare.splitlines()): + logging.info(colored(line, "red" if line.startswith("-") else "green" if line.startswith("+") else None)) + if ctx_vars: logging.info(ctx_vars) + warnings.warn("PROCESS REPLAY DETECTED CHANGE", ProcessReplayWarning) + except Exception as e: + changed += 1 + warnings.warn(e, ProcessReplayWarning) + conn.commit() + cur.close() + +# *** main loop + +if __name__ == "__main__": + if SKIP_PROCESS_REPLAY: + logging.info("skipping process replay.") + exit(0) + + conn = db_connection() + cur = conn.cursor() + try: row_count = cur.execute(f"select count(*) from '{TABLE_NAME}'").fetchone()[0] + except sqlite3.OperationalError: + warnings.warn(f"{TABLE_NAME} isn't accessible in master, did DB_VERSION change?", ProcessReplayWarning) + exit(int(ASSERT_DIFF)) + finally: + conn.commit() + cur.close() + + logging.info(f"running process replay with {ASSERT_DIFF=}") + with multiprocessing.get_context("spawn").Pool(multiprocessing.cpu_count()) as pool: + inputs = list(range(0, row_count, PAGE_SIZE)) + list(tqdm(pool.imap_unordered(diff, inputs), total=len(inputs))) + pool.close() + pool.join() + pool.terminate() diff --git a/tinygrad_repo/test/external/process_replay/reset.py b/tinygrad_repo/test/external/process_replay/reset.py new file mode 100755 index 000000000..c40b6d096 --- /dev/null +++ b/tinygrad_repo/test/external/process_replay/reset.py @@ -0,0 +1,4 @@ +#!/usr/bin/env python3 +from tinygrad.helpers import db_connection, VERSION +cur = db_connection() +cur.execute(f"drop table if exists process_replay_{VERSION}") diff --git a/tinygrad_repo/test/external/sglang_llama/external_llama_eval.py b/tinygrad_repo/test/external/sglang_llama/external_llama_eval.py new file mode 100644 index 000000000..fd75913c8 --- /dev/null +++ b/tinygrad_repo/test/external/sglang_llama/external_llama_eval.py @@ -0,0 +1,100 @@ +from lm_eval import simple_evaluate +from lm_eval.api.instance import Instance +from lm_eval.api.model import LM +from lm_eval.tasks import TaskManager +from pathlib import Path +import json, argparse + +from examples.llama3 import build_transformer, Tokenizer, MODEL_PARAMS +from tinygrad import Tensor, Device +from tinygrad.helpers import tqdm + +class LLaMaAdaptor(LM): + def __init__( + self, + model_size: str, + checkpoint_path: Path, + max_length: int, + quantize: str | None, + ): + super().__init__() + self.max_length = max_length + self.tokenizer = Tokenizer(str((checkpoint_path if checkpoint_path.is_dir() else checkpoint_path.parent) / "tokenizer.model")) + self.model = build_transformer(checkpoint_path, model_size=model_size, quantize=quantize, max_context=self.max_length) + self.last_seen_toks = [] + def _prefill(self, toks, temperature) -> int: + start_pos = 0 + # we can skip part of the prompt if it is the same as last + for i, (a, b) in enumerate(zip(toks, self.last_seen_toks)): + if a != b: break + else: i = min(len(toks), len(self.last_seen_toks)) + start_pos += i + self.last_seen_toks = toks + toks = toks[i:] + + # prefill the model + for tok in toks: + self.model(Tensor([[tok]]), start_pos, temperature).realize() + start_pos += 1 + return start_pos + + @property + def tokenizer_name(self) -> str: pass + def chat_template(self, chat_template: bool | str = False) -> str: pass + def apply_chat_template(self, chat_history: list[dict[str, str]], add_generation_prompt: bool = True) -> str: + ret = "" + for message in chat_history: + ret += f"<|start_header_id|>{message['role']}<|end_header_id|>\n\n{message['content'].strip()}<|eot_id|>" + if add_generation_prompt: ret += "<|start_header_id|>assistant<|end_header_id|>\n\n" + return ret + + def generate_until(self, requests: list[Instance]) -> list[str]: + continuations = [] + for request in tqdm(requests): + prompt, args = request.args + until = [self.tokenizer.encode(tok) for tok in args.get("until", [])] + toks = [self.tokenizer.bos_id] + self.tokenizer.encode(prompt,allow_special=True) + prompt_len = len(toks) + max_gen_toks = args.get("max_gen_toks") or args.get("max_length") or self.max_length-prompt_len + assert self.max_length >= max_gen_toks, "This eval needs a longer context length" + temperature = args.get("temperature", 0.0) + start_pos = self._prefill(toks[:-1], temperature) + + for _ in range(max_gen_toks): + next_tok = self.model(Tensor([toks[start_pos:]]), start_pos, temperature).item() + if next_tok in self.tokenizer.stop_tokens or next_tok in until: break + toks.append(next_tok) + start_pos += 1 + + continuations.append(self.tokenizer.decode(toks[prompt_len:])) + return continuations + + def loglikelihood(self, requests: list[Instance]) -> list[tuple[float, bool]]: raise NotImplementedError() # needs changes to extra/models/llama.py + def loglikelihood_rolling(self, requests: list[Instance]) -> list[tuple[float, bool]]: raise NotImplementedError() + +if __name__ == '__main__': + print(f"using {Device.DEFAULT} backend") + + parser = argparse.ArgumentParser(description='Run LLaMA evals in tinygrad', formatter_class=argparse.ArgumentDefaultsHelpFormatter) + parser.add_argument('--size', type=str, default="8B", help=f"Size of model to use [{', '.join(list(MODEL_PARAMS.keys()))}]") + parser.add_argument('--chat', action='store_true', help="Use chat model") + parser.add_argument('--ctx', type=int, default=8192, help="Max context length") + parser.add_argument('--quantize', type=str, default=None, help="Quantize the weights to int8 or int4 in memory") + parser.add_argument('--eval', type=str, default="mgsm_en_cot_sglang", help="Run in evaluation mode") + parser.add_argument('--limit', type=int, default=None, help="Limit tests in eval") + parser.add_argument('--num_fewshot', type=int, default=None, help="Number of examples to add to context") + parser.add_argument('--model', type=Path, default="./weights/LLaMa/", help="Location of the weights") + parser.add_argument('--output_path', type=Path, default=None, help="Location of the log file") + args = parser.parse_args() + + # run eval and exit + adaptor = LLaMaAdaptor(model_size=args.size, quantize=args.quantize, + checkpoint_path=args.model, max_length=args.ctx) + task_manager = TaskManager(include_path="./") + results = simple_evaluate(model=adaptor, tasks=args.eval.split(","), task_manager=task_manager, apply_chat_template=args.chat, + num_fewshot=args.num_fewshot, limit=args.limit) + + if args.output_path: args.output_path.write_text(json.dumps(results, indent=2)) + for task_name, val in results["results"].items(): + print(f"{task_name}:") + print("\n".join(f"\t{k}: {v}" for k, v in val.items() if k != "alias")) diff --git a/tinygrad_repo/test/external/sglang_llama/mgsm.yaml b/tinygrad_repo/test/external/sglang_llama/mgsm.yaml new file mode 100644 index 000000000..7c205344f --- /dev/null +++ b/tinygrad_repo/test/external/sglang_llama/mgsm.yaml @@ -0,0 +1,36 @@ +# https://github.com/sgl-project/sglang/blob/main/python/sglang/test/simple_eval_mgsm.py#L41 +task: mgsm_en_cot_sglang +dataset_path: juletxara/mgsm +dataset_name: en +output_type: generate_until +training_split: train +test_split: test +doc_to_target: '{{answer[21:] if answer is not none else answer_number|string}}' +doc_to_text: >- + {{'Solve this math problem. Give the reasoning steps before giving the final answer on the last line by itself in the format of "Answer:". + Do not add anything other than the integer answer after "Answer:".\n\n' + +(question[10:] if answer is not none else question)}} +generation_kwargs: + do_sample: false + temperature: 0.0 + until: [] +metric_list: + - metric: exact_match + aggregation: mean + higher_is_better: true + ignore_case: true + ignore_punctuation: true +filter_list: + - name: "strict-match" + filter: + - function: "regex" + regex_pattern: 'Answer:\s*([\-]?[0-9\.\,]+)' + - function: "take_first" + - filter: + - function: regex + group_select: -1 + regex_pattern: (-?[$0-9.,]{2,})|(-?[0-9]+) + - function: take_first + name: flexible-extract +metadata: + version: 3.0 diff --git a/tinygrad_repo/test/external/speed_beam_v_hcopt.py b/tinygrad_repo/test/external/speed_beam_v_hcopt.py new file mode 100644 index 000000000..e73c6466d --- /dev/null +++ b/tinygrad_repo/test/external/speed_beam_v_hcopt.py @@ -0,0 +1,41 @@ +from tinygrad import Device +from tinygrad.helpers import getenv, DEBUG, BEAM +from tinygrad.opt.search import beam_search, bufs_from_lin +from tinygrad.opt.heuristic import hand_coded_optimizations +from extra.optimization.helpers import load_worlds, ast_str_to_lin, time_linearizer + +if __name__ == "__main__": + filter_reduce = bool(getenv("FILTER_REDUCE")) + ast_strs = load_worlds(filter_reduce=filter_reduce, filter_novariable=True) + dev = Device[Device.DEFAULT] + + test_n = getenv("TEST_N", 10) + single = getenv("NUM", -1) + if single != -1: ast_strs = ast_strs[single:single+1] + + beam_won, tested = 0, 0 + + for num, ast in enumerate(ast_strs[:test_n]): + def new_lin(): return ast_str_to_lin(ast, opts=dev.renderer) + + k = new_lin() + + if not (used_tensor_cores:=k.apply_tensor_cores(getenv("TC", 1))): k.apply_opts(hand_coded_optimizations(k)) + + assert BEAM > 0 + + lins = [(("tc" if used_tensor_cores else "hc"), k)] + if used_tensor_cores: + lins.append(("hc", new_lin())) + lins[-1][1].apply_opts(hand_coded_optimizations(lins[-1][1])) + kb = new_lin() + test_rawbuffers = bufs_from_lin(kb) # allocate scratch buffers for optimization + lins.append((f"beam{BEAM.value}", beam_search(kb, test_rawbuffers, BEAM.value, bool(getenv("BEAM_ESTIMATE", 1))))) + timed = sorted([(nm, tk, time_linearizer(tk, test_rawbuffers, allow_test_size=False, clear_l2=True)) for nm, tk in lins], key=lambda x: x[2]) + if DEBUG >= 1: print(" < ".join(f"{nm:6s} : {lin.colored_shape(30, dense=True)} : {tm*1e6:8.2f} us" for nm, lin, tm in timed)) + + tested += 1 + if timed[0][0].startswith("beam"): + beam_won += 1 + + print(f"{beam_won=} / {tested=} = {beam_won/tested:.3f}") \ No newline at end of file diff --git a/tinygrad_repo/test/external/speed_compare_amd_am.py b/tinygrad_repo/test/external/speed_compare_amd_am.py new file mode 100644 index 000000000..3a422d4ca --- /dev/null +++ b/tinygrad_repo/test/external/speed_compare_amd_am.py @@ -0,0 +1,157 @@ +from tinygrad import Device, dtypes +from tinygrad.helpers import getenv, colorize_float, DEBUG +from extra.optimization.helpers import load_worlds, ast_str_to_lin +from test.external.fuzz_linearizer import get_fuzz_rawbufs +from tinygrad.opt.heuristic import hand_coded_optimizations +from tinygrad.opt.search import bufs_from_lin +from tinygrad.engine.realize import CompiledRunner +from tinygrad.tensor import _to_np_dtype +from tinygrad.runtime.ops_amd import AMDDevice +from contextlib import contextmanager +import numpy as np +import os, random, statistics + +am_signal_pages, am_signal_pool, am_devices = [], [], [] +amd_signal_pages, amd_signal_pool, amd_devices = [], [], [] + +def rebind_vfio(pcibus="0000:44:00.0"): + print("rebind ", pcibus) + os.system("sudo rmmod amdgpu") + os.system("sudo modprobe vfio-pci") + + base = f"/sys/bus/pci/devices/{pcibus}" + if os.path.exists(f"{base}/driver"): + with open(f"{base}/driver/unbind", "w") as f: f.write(pcibus) + with open(f"{base}/driver_override", "w") as f: f.write("vfio-pci") + with open("/sys/bus/pci/drivers_probe", "w") as f: f.write(pcibus) + + os.system("sudo modprobe amdgpu") + os.system("rocm-smi --setprofile compute") + os.system("rocm-smi --setperflevel high") + +@contextmanager +def run_amd(): + global amd_signal_pages, amd_signal_pool, amd_devices + AMDDevice.driverless = False + AMDDevice.signal_pages, AMDDevice.signal_pool, AMDDevice.devices = amd_signal_pages, amd_signal_pool, amd_devices + yield + amd_signal_pages, amd_signal_pool, amd_devices = AMDDevice.signal_pages, AMDDevice.signal_pool, AMDDevice.devices + AMDDevice.signal_pages, AMDDevice.signal_pool, AMDDevice.devices = [], [], [] + +@contextmanager +def run_am(): + global am_signal_pages, am_signal_pool, am_devices + AMDDevice.driverless = True + AMDDevice.signal_pages, AMDDevice.signal_pool, AMDDevice.devices = am_signal_pages, am_signal_pool, am_devices + yield + am_signal_pages, am_signal_pool, am_devices = AMDDevice.signal_pages, AMDDevice.signal_pool, AMDDevice.devices + AMDDevice.signal_pages, AMDDevice.signal_pool, AMDDevice.devices = [], [], [] + +if __name__ == "__main__": + CHECK_CPU = getenv("CHECK_CPU", 0) + SEED = getenv("SEED", 42) + CNT = getenv("CNT", 7) + random.seed(SEED) + np.random.seed(SEED) + + # TODO: NUM=780 is super slow + # NUM=1907 is broken on AMD and AM have some mismatches (0 vs 1) + # kfd feels so bad when taking gpu out while it's running... Need hacks to rebind it before running. + rebind_vfio(pcibus="0000:44:00.0") + + ast_strs = load_worlds(filter_reduce=False, filter_novariable=True) + + with run_am(): + amdev = Device["AMD:1"] + + with run_amd(): + amddev = Device["AMD"] + + if CHECK_CPU: cpudev = Device["CPU"] + + single = getenv("NUM", -1) + if single != -1: ast_strs = ast_strs[single:single+1] + + average_tm_amd, average_tm_am = 0, 0 + for num,ast in enumerate(ast_strs): + with run_amd(): + amdlin = ast_str_to_lin(ast, opts=amddev.renderer) + amdlin.apply_opts(hand_coded_optimizations(amdlin)) + has_bf16 = any(b.dtype == dtypes.bfloat16 for b in amdlin.membufs) + + amd_prg = CompiledRunner(amdlin.to_program()) + amdbufs = bufs_from_lin(amdlin) + test_amdbufs = get_fuzz_rawbufs(amdlin) if not has_bf16 else amdbufs + if not has_bf16: contents = [buf.as_buffer() for buf in test_amdbufs] + + with run_am(): + rdr = amdev.renderer + rdr.device = "AMD:1" + amlin = ast_str_to_lin(ast, opts=amdev.renderer) + amlin.apply_opts(hand_coded_optimizations(amlin)) + am_prg = CompiledRunner(amlin.to_program()) + ambufs = bufs_from_lin(amlin) + test_ambufs = get_fuzz_rawbufs(amlin) if not has_bf16 else ambufs + if not has_bf16: + for i,rawbuf in enumerate(test_ambufs): rawbuf.copyin(contents[i]) + + if CHECK_CPU: + cpu_rdr = cpudev.renderer + cpu_rdr.device = "CPU" + cpulin = ast_str_to_lin(ast, opts=cpu_rdr) + cpulin.apply_opts(hand_coded_optimizations(cpulin)) + cpu_prg = CompiledRunner(cpulin.to_program()) + cpubufs = bufs_from_lin(cpulin) + test_cpubufs = get_fuzz_rawbufs(cpulin) if not has_bf16 else ambufs + if not has_bf16: + for i,rawbuf in enumerate(test_cpubufs): rawbuf.copyin(contents[i]) + + # warmup + tm_amd, tm_am, failed = [], [], False + with run_amd(): + try: + amd_prg(test_amdbufs, {}, wait=True) + for i in range(CNT): tm_amd.append(amd_prg(amdbufs, {}, wait=True)) + except RuntimeError: + print("AMD FAILED") + tm_amd = [1e9] + failed = True + + with run_am(): + try: + am_prg(test_ambufs, {}, wait=True) + for i in range(CNT): tm_am.append(am_prg(ambufs, {}, wait=True)) + except RuntimeError: + print("AM FAILED") + tm_am = [1e9] + failed = True + + if CHECK_CPU: + cpu_prg(test_cpubufs, {}, wait=True) + for i in range(1): cpu_prg(cpubufs, {}, wait=True) + + if not failed and not has_bf16: + with run_amd(): + curesult = np.frombuffer(test_amdbufs[0].as_buffer(), _to_np_dtype(test_amdbufs[0].dtype)) + + with run_am(): + amresult = np.frombuffer(test_ambufs[0].as_buffer(), _to_np_dtype(test_ambufs[0].dtype)) + + if CHECK_CPU: + cpuresult = np.frombuffer(test_cpubufs[0].as_buffer(), _to_np_dtype(test_cpubufs[0].dtype)) + np.testing.assert_allclose(amresult, cpuresult, rtol=1e-2, atol=1e-2) + np.testing.assert_allclose(curesult, cpuresult, rtol=1e-2, atol=1e-2) + + try: + np.testing.assert_allclose(curesult, amresult, rtol=1e-2, atol=1e-2) + except AssertionError as e: + print("AM and AMD results do not match") + print(e) + + bam = statistics.median(tm_am) + bamd = statistics.median(tm_amd) + average_tm_amd += bamd + average_tm_am += bam + ratio = bam/bamd + print(f"{average_tm_am/average_tm_amd:5.2f}x -- {num:4d} {colorize_float(ratio)} {bam*1e6:7.2f} vs {bamd*1e6:7.2f} us", amlin.name) + if DEBUG > 3 and ratio > 1.04: print(f"AM slower {ratio}", amlin.ast, amlin.applied_opts) diff --git a/tinygrad_repo/test/external/speed_compare_cuda_nv.py b/tinygrad_repo/test/external/speed_compare_cuda_nv.py new file mode 100644 index 000000000..f9185a94b --- /dev/null +++ b/tinygrad_repo/test/external/speed_compare_cuda_nv.py @@ -0,0 +1,69 @@ +from tinygrad import Device, dtypes +from tinygrad.helpers import getenv, colorize_float +from extra.optimization.helpers import load_worlds, ast_str_to_lin +from test.external.fuzz_linearizer import get_fuzz_rawbufs +from tinygrad.opt.heuristic import hand_coded_optimizations +from tinygrad.opt.search import bufs_from_lin +from tinygrad.engine.realize import CompiledRunner +from tinygrad.tensor import _to_np_dtype +import numpy as np + +if __name__ == "__main__": + ast_strs = load_worlds(filter_reduce=False, filter_novariable=True) + cudev = Device["CUDA"] + nvdev = Device["NV"] + + # NUM=112 python3 test/external/speed_compare_cuda_nv.py + + single = getenv("NUM", -1) + if single != -1: ast_strs = ast_strs[single:single+1] + + average_tm_cuda, average_tm_nv = 0, 0 + for num,ast in enumerate(ast_strs): + # cuda compile + culin = ast_str_to_lin(ast, opts=cudev.renderer) + culin.apply_opts(hand_coded_optimizations(culin)) + has_bf16 = any(b.dtype == dtypes.bfloat16 for b in culin.membufs) + + cuda_prg = CompiledRunner(culin.to_program()) + cubufs = bufs_from_lin(culin) + test_cubufs = get_fuzz_rawbufs(culin) if not has_bf16 else cubufs + + rdr = nvdev.renderer + rdr.device = "NV" + nvlin = ast_str_to_lin(ast, opts=rdr) + nvlin.apply_opts(hand_coded_optimizations(nvlin)) + nv_prg = CompiledRunner(nvlin.to_program()) + nvbufs = bufs_from_lin(nvlin) + test_nvbufs = get_fuzz_rawbufs(nvlin) if not has_bf16 else nvbufs + if not has_bf16: + for i,rawbuf in enumerate(test_nvbufs): rawbuf.copyin(test_cubufs[i].as_buffer()) + + # warmup + tm_cuda, tm_nv, failed = [], [], False + try: + cuda_prg(test_cubufs, {}, wait=True) + for i in range(5): tm_cuda.append(cuda_prg(cubufs, {}, wait=True)) + except RuntimeError: + print("CUDA FAILED") + tm_cuda = [1e9] + failed = True + + try: + nv_prg(test_nvbufs, {}, wait=True) + for i in range(5): tm_nv.append(nv_prg(nvbufs, {}, wait=True)) + except RuntimeError: + print("NV FAILED") + tm_nv = [1e9] + failed = True + + if not failed and not has_bf16: + curesult = np.frombuffer(test_cubufs[0].as_buffer(), _to_np_dtype(test_cubufs[0].dtype)) + nvresult = np.frombuffer(test_nvbufs[0].as_buffer(), _to_np_dtype(test_nvbufs[0].dtype)) + np.testing.assert_allclose(curesult, nvresult, rtol=1e-2, atol=1e-2) + + average_tm_cuda += min(tm_cuda) + average_tm_nv += min(tm_nv) + ratio = min(tm_nv)/min(tm_cuda) + print(f"{average_tm_nv/average_tm_cuda:5.2f}x -- {num:4d} {colorize_float(ratio)} {min(tm_nv)*1e6:7.2f} us", nvlin.name) + if ratio > 1.04: print(f"NV slower {ratio}", nvlin.ast, nvlin.applied_opts) diff --git a/tinygrad_repo/test/external/speed_compare_cuda_ptx.py b/tinygrad_repo/test/external/speed_compare_cuda_ptx.py new file mode 100644 index 000000000..f5ed26f75 --- /dev/null +++ b/tinygrad_repo/test/external/speed_compare_cuda_ptx.py @@ -0,0 +1,60 @@ +import itertools +from tinygrad import Device +from tinygrad.engine.realize import CompiledRunner +from tinygrad.opt.heuristic import hand_coded_optimizations +from tinygrad.helpers import getenv, colorize_float +from extra.optimization.helpers import load_worlds, ast_str_to_lin +from tinygrad.opt.search import bufs_from_lin +from tinygrad.runtime.ops_cuda import PTXCompiler, PTXRenderer, CUDACompiler + +if __name__ == "__main__": + ast_strs = load_worlds(filter_reduce=False, filter_novariable=True) + # no bfloat16 for ptx at the moment + ast_strs = [x for x in ast_strs if "dtypes.bfloat16" not in x] + dev = Device["CUDA"] + ptx = PTXRenderer(dev.arch) + + # NUM=112 python3 test/external/speed_compare_cuda_ptx.py + + single = getenv("NUM", -1) + if single != -1: ast_strs = ast_strs[single:single+1] + + average_tm_cuda, average_tm_ptx = 0, 0 + for num,ast in enumerate(ast_strs): + # cuda compile + dev.compiler = CUDACompiler(dev.arch) + lin = ast_str_to_lin(ast, opts=dev.renderer) + lin.apply_opts(hand_coded_optimizations(lin)) + cuda_prg = CompiledRunner(lin.to_program()) + + bufs = bufs_from_lin(lin) + + # ptx compile + dev.compiler = PTXCompiler(dev.arch) + lin = ast_str_to_lin(ast, opts=ptx) + lin.apply_opts(hand_coded_optimizations(lin)) + ptx_prg = CompiledRunner(lin.to_program()) + + # warmup + try: + cuda_prg(bufs, {}, wait=True) + except RuntimeError: + print("cuda failed ast:", num) + continue + ptx_prg(bufs, {}, wait=True) + + tm_cuda, tm_ptx = [], [] + for i in range(5): + tm_cuda.append(cuda_prg(bufs, {}, wait=True)) + tm_ptx.append(ptx_prg(bufs, {}, wait=True)) + average_tm_cuda += min(tm_cuda) + average_tm_ptx += min(tm_ptx) + ratio = min(tm_ptx)/min(tm_cuda) + print(f"{average_tm_ptx/average_tm_cuda:5.2f}x -- {num:4d} {colorize_float(ratio)} {min(tm_ptx)*1e6:7.2f} us", lin.name) + if ratio > 1.5: + def fix(x): return x.replace('\t', ' ').strip() + ll1, ll2 = cuda_prg.lib.decode().split('\n'), ptx_prg.lib.decode().split('\n') + if single != -1: + for ln, (l1, l2) in enumerate(itertools.zip_longest(ll1, ll2, fillvalue='')): + print(f"{ln:5d} | {fix(l1):80s} | {fix(l2):80s}") + print(len(ll1), len(ll2), "RATIO", ratio, "us", min(tm_ptx)*1e6) diff --git a/tinygrad_repo/test/external/speed_v_theoretical.py b/tinygrad_repo/test/external/speed_v_theoretical.py new file mode 100644 index 000000000..8b04d4af2 --- /dev/null +++ b/tinygrad_repo/test/external/speed_v_theoretical.py @@ -0,0 +1,101 @@ +import unittest +from tinygrad import Tensor, TinyJit, Device +from tinygrad.helpers import Context, DEBUG, GlobalCounters +from tinygrad.nn import Conv2d +from tinygrad.nn.state import get_parameters + +class TestKernelSpeed(unittest.TestCase): + def _get_tensor(self, *shape:int): + with Context(BEAM=0, DEBUG=0): + # TODO: randn is 20% faster than rand for gemv + return Tensor.randn(shape, dtype="half").realize() + + def _compare(self, tm, tflops, gbs, nv_tflops=None, nv_gbs=None, amd_tflops=None, amd_gbs=None): + if DEBUG >= 1: + print(f"{tm=:.6f}") + print(f"{tflops=:.6f}") + print(f"{gbs=:.3f}") + + if Device.DEFAULT == "NV": + if nv_tflops is not None: + if DEBUG >=1: print(f"tflop/s target: {nv_tflops}") + self.assertGreater(tflops, nv_tflops) + if nv_gbs is not None: + if DEBUG >=1: print(f"gb/s target: {nv_gbs}") + self.assertGreater(gbs, nv_gbs) + + if Device.DEFAULT == "AMD": + if amd_tflops is not None: + if DEBUG >=1: print(f"tflop/s target: {amd_tflops}") + self.assertGreater(tflops, amd_tflops) + if amd_gbs is not None: + if DEBUG >=1: print(f"gb/s target: {amd_gbs}") + self.assertGreater(gbs, amd_gbs) + + def _test_matmul(self, M, K=None, N=None, nv_tflops=None, nv_gbs=None, amd_tflops=None, amd_gbs=None): + # (MxK) @ (KxN) + @TinyJit + def f(a, b) -> Tensor: return (a @ b).realize() + + if N is None: N = M + if K is None: K = M + tms = [] + with Context(BEAM=3): + for i in range(10): + a = self._get_tensor(M, K) + b = self._get_tensor(K, N) + if i >= 3: + GlobalCounters.time_sum_s = 0 + with Context(DEBUG=max(DEBUG.value, 2)): c = f(a, b) + tms.append(GlobalCounters.time_sum_s) + else: + c = f(a, b) + + ops = 2 * M * N * K + mems = a.dtype.itemsize * M * K + b.dtype.itemsize * K * N + c.dtype.itemsize * M * N + tm = min(tms) + tflops = ops / tm / 1e12 + gbs = mems / tm / 1e9 + self._compare(tm, tflops, gbs, nv_tflops, nv_gbs, amd_tflops, amd_gbs) + + def _test_conv_3x3(self, BS, CIN, COUT, H, W, nv_tflops=None, nv_gbs=None, amd_tflops=None, amd_gbs=None): + @TinyJit + def f(conv, x) -> Tensor: return conv(x).realize() + tms = [] + K = 3 + with Context(BEAM=0, DEBUG=0): + conv = Conv2d(CIN, COUT, K, padding=1) + Tensor.realize(*get_parameters(conv)) + + with Context(BEAM=2): + for i in range(10): + x = self._get_tensor(BS, CIN, H, W) + if i >= 3: + GlobalCounters.time_sum_s = 0 + with Context(DEBUG=max(DEBUG.value, 2)): _c = f(conv, x) + tms.append(GlobalCounters.time_sum_s) + else: + _c = f(conv, x) + + # naive algo + ops = 2 * BS * CIN * COUT * K * K * H * W + mems = x.nbytes() + conv.weight.nbytes() + conv.bias.nbytes() + _c.nbytes() + tm = min(tms) + tflops = ops / tm / 1e12 + gbs = mems / tm / 1e9 + self._compare(tm, tflops, gbs, nv_tflops, nv_gbs, amd_tflops, amd_gbs) + + # NOTE: tiny7 was slower than tiny12 + # TODO: why are convs so slow?!? + def test_conv_3x3_256_32_32_256_256(self): self._test_conv_3x3(256, 32, 32, 256, 256, nv_tflops=27, amd_tflops=14) + + # theoretical is nv_tflops=165, amd_tflops=123 + def test_gemm_4096(self): self._test_matmul(4096, nv_tflops=115, amd_tflops=65) + def test_gemm_8192(self): self._test_matmul(8192, nv_tflops=125, amd_tflops=60) + + # theoretical is nv_gbs=1008, amd_gbs=960 + def test_gemv_16384_4096(self): self._test_matmul(16384, 4096, 1, nv_gbs=840, amd_gbs=750) + def test_gemv_4096_16384(self): self._test_matmul(4096, 16384, 1, nv_gbs=830, amd_gbs=750) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/external/verify_kernel.py b/tinygrad_repo/test/external/verify_kernel.py new file mode 100644 index 000000000..5a251ce8a --- /dev/null +++ b/tinygrad_repo/test/external/verify_kernel.py @@ -0,0 +1,78 @@ +import argparse +from collections import defaultdict +from extra.optimization.helpers import kern_str_to_lin, time_linearizer +from test.external.fuzz_linearizer import compare_linearizer +from tinygrad.helpers import colored +from tinygrad.opt.kernel import Kernel + +# Use this with the LOGKERNS options to verify that all executed kernels are valid and evaluate to the same ground truth results + +# Example for GPT2: +# 1) Run the model to log all kernels: `PYTHONPATH=. LOGKERNS=/tmp/gpt2_kerns.txt JIT=1 HALF=1 BEAM=2 CACHELEVEL=0 python3 examples/gpt2.py --count 10 --temperature 0 --timing` # noqa: E501 +# 2) Validate the kernel correctness: `PYTHONPATH=. python3 ./test/external/verify_kernel.py --file /tmp/gpt2_kerns.txt` + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description="Verify the correctness of one or more kernel", formatter_class=argparse.ArgumentDefaultsHelpFormatter) # noqa: E501 + parser.add_argument("--kernel", type=str, default=None, help="a string of a tuple of (ast, applied_opts,)") + parser.add_argument("--file", type=str, default=None, help="a file containing a tuple of ast and applied_opts, one per line") + parser.add_argument("--pkl", type=str, default=None, help="a pickle file containing a single tuple of ast and applied_opts") + parser.add_argument("--rtol", type=float, default=1e-2, help="relative tolerance for numerical comparison") + parser.add_argument("--atol", type=float, default=1e-2, help="absolute tolerance for numerical comparison") + parser.add_argument("--timing", action='store_true', help="show final timing for the kernel") + parser.add_argument("--expected-failures", type=int, default=0, help="the number of expected failed kernels") + args = parser.parse_args() + + if args.kernel is not None: + print("loading kernel from args") + test_lins = [kern_str_to_lin(args.kernel)] + elif args.file is not None: + print(f"loading kernel from file '{args.file}'") + with open(args.file, 'r') as file: + kern_strs = file.readlines() + test_lins = [kern_str_to_lin(kern_str) for kern_str in kern_strs] + elif args.pkl is not None: + print(f"loading kernel from pickle file '{args.file}'") + import pickle + with open(args.pkl, 'rb') as file: + (ast, applied_opts,) = pickle.load(file) + lin = Kernel(ast) + lin.apply_opts(applied_opts) + test_lins = [lin] + + else: + raise RuntimeError("no kernel specified; use --kernel, --file, or --pkl options") + + print(f"verifying {len(test_lins)} kernels") + + failed_ids = [] + failures = defaultdict(list) + for i, test_lin in enumerate(test_lins): + print(f"testing kernel {i}") + print(test_lin.ast) + print(test_lin.applied_opts) + unoptimized_lin = Kernel(test_lin.ast) + print(f"{unoptimized_lin.colored_shape()} -> {test_lin.colored_shape()}") + (msg,rb,vv,gt) = compare_linearizer(test_lin, None, None, None, rtol=args.rtol, atol=args.atol) + if msg != "PASS": + failed_ids.append(i) + failures[msg].append((test_lin.ast, test_lin.applied_opts)) + if args.timing: + tm = time_linearizer(test_lin, rb, allow_test_size=False, cnt=10) + print(f"final time {tm*1e6:9.0f} us") + + for msg, errors in failures.items(): + for i, (ast, opts) in enumerate(errors): + print(f"{msg} {i} AST: {ast}") + print(f"{msg} {i} OPTS: {opts}\n") + + print(f"tested {len(test_lins)} kernels") + if failures: + print(f"{failed_ids=}") + for msg, errors in failures.items(): + print(f"{msg}: {len(errors)}") + if len(failed_ids) == args.expected_failures: + print(colored(f"{len(failed_ids)} failed as expected", "yellow")) + if len(failed_ids) != args.expected_failures: + raise RuntimeError(f"failed on {len(failed_ids)} kernels, expected {args.expected_failures}") + else: + print(colored("all passed", "green")) diff --git a/tinygrad_repo/test/helpers.py b/tinygrad_repo/test/helpers.py new file mode 100644 index 000000000..91667e078 --- /dev/null +++ b/tinygrad_repo/test/helpers.py @@ -0,0 +1,73 @@ +import time, struct +from typing import Any, Callable, Optional +import numpy as np +from tinygrad import Tensor, dtypes, Device +from tinygrad.uop.ops import UOp, Ops, sint, graph_rewrite +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.tensor import _to_np_dtype +from tinygrad.engine.realize import Runner +from tinygrad.kernelize.kernelize import view_left +from tinygrad.dtype import ConstType, DType +from tinygrad.nn.state import get_parameters +from tinygrad.helpers import T, unwrap, CI +from tinygrad.codegen import full_rewrite +from tinygrad.runtime.ops_python import PythonProgram, PythonRenderer, PythonCompiler + +def derandomize_model(model): + for p in get_parameters(model): + p.replace(Tensor.empty(p.shape, device=p.device, dtype=p.dtype)) + p.realize() + +def assert_jit_cache_len(fxn, expected_len): + if not fxn.jit_cache: + assert expected_len == 0, expected_len + return + # until we have a better way of typing the prg in ExecItem + if issubclass(type(fxn.jit_cache[0].prg), Runner) and not type(fxn.jit_cache[0].prg).__name__.endswith('Graph'): + assert len(fxn.jit_cache) == expected_len, f"expected {expected_len}, got {len(fxn.jit_cache)}" + else: + assert len(fxn.jit_cache) == 1, len(fxn.jit_cache) + # until we have a better way of typing the prg in ExecItem + assert type(fxn.jit_cache[0].prg).__name__.endswith('Graph') + assert len(fxn.jit_cache[0].prg.jit_cache) == expected_len + +def rand_for_dtype(dt:DType, size:int): + if dtypes.is_unsigned(dt): + return np.random.randint(0, 100, size=size, dtype=_to_np_dtype(dt)) + elif dtypes.is_int(dt): + return np.random.randint(-100, 100, size=size, dtype=_to_np_dtype(dt)) + elif dt == dtypes.bool: + return np.random.choice([True, False], size=size) + return np.random.uniform(-10, 10, size=size).astype(_to_np_dtype(dt)) + +def ast_const(dtype:DType, val:ConstType, shape:tuple[sint, ...]=(), st:Optional[ShapeTracker]=None, st_src:Optional[tuple[UOp]]=None) -> UOp: + if st_src is None: + st_src = (st.to_uop() if st is not None else ShapeTracker.from_shape(()).reshape((1,)*len(shape)).expand(shape).to_uop(),) + st = unwrap(st_src[0].st) + if all(v.mask is None for v in st.views): return UOp.const(dtype, val).replace(src=(st.to_uop(),)) + return graph_rewrite(UOp.const(dtype, val).view(st).valid(), view_left) + +def timeit(fxn:Callable[..., T], *args, **kwargs) -> tuple[T, float]: + st = time.perf_counter_ns() + ret = fxn(*args, **kwargs) + return ret, (time.perf_counter_ns()-st)*1e-6 + +def eval_uop(uop:UOp, inputs:list[tuple[DType, list[Any]]]|None=None): + allocator = Device['PYTHON'].allocator + bufs = [] + for buf_dt, data in inputs or []: + bufs.append(buf:=allocator.alloc(len(data) * buf_dt.itemsize)) + allocator._copyin(buf, memoryview(struct.pack(str(len(data)) + buf_dt.fmt, *data))) + g = UOp(Ops.DEFINE_GLOBAL, uop.dtype.ptr(), arg=0, src=()) + opts = PythonRenderer() + lst = full_rewrite(UOp.store(g.index(UOp.const(dtypes.int, 0)), uop).sink(), opts) + prog = PythonProgram("run", PythonCompiler().compile(opts.render(lst))) + prog(out_buf:=allocator.alloc(uop.dtype.itemsize), *bufs) + return out_buf.cast(uop.dtype.fmt).tolist()[0] + +def not_support_multi_device(): + # GPU and CUDA don't support multi device if in CI + return CI and REAL_DEV in ("GPU", "CUDA") + +# NOTE: This will open REMOTE if it's the default device +REAL_DEV = (Device.DEFAULT if Device.DEFAULT != "REMOTE" else Device['REMOTE'].properties.real_device) diff --git a/tinygrad_repo/test/mockgpu/amd/amddriver.py b/tinygrad_repo/test/mockgpu/amd/amddriver.py new file mode 100644 index 000000000..2cac02e5a --- /dev/null +++ b/tinygrad_repo/test/mockgpu/amd/amddriver.py @@ -0,0 +1,172 @@ +import pathlib, re, ctypes, mmap, collections, functools, copy, os +import tinygrad.runtime.autogen.kfd as kfd +import tinygrad.runtime.autogen.am.am as am +from tinygrad.helpers import from_mv +from test.mockgpu.driver import VirtDriver, VirtFileDesc, TextFileDesc, DirFileDesc, VirtFile +from test.mockgpu.amd.amdgpu import AMDGPU, gpu_props + +libc = ctypes.CDLL(ctypes.util.find_library("c")) +libc.mmap.argtypes = [ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long] +libc.mmap.restype = ctypes.c_void_p + +def ioctls_from_header(): + # hdrpy = (pathlib.Path(__file__).parent.parent.parent.parent / "tinygrad" / "runtime" / "autogen" / "kfd.py").read_text() + # pattern = r'# (AMDKFD_IOC_[A-Z0-9_]+)\s=\s_(IOW?R?).*\(( 0x[0-9a-fA-F]+) ,\s+struct\s([A-Za-z0-9_]+)\s+\)' + # matches = re.findall(pattern, hdrpy, re.MULTILINE) + hdr = (pathlib.Path(__file__).parent.parent.parent.parent / "extra" / "hip_gpu_driver" / "kfd_ioctl.h").read_text().replace("\\\n", "") + pattern = r'#define\s+(AMDKFD_IOC_[A-Z0-9_]+)\s+AMDKFD_(IOW?R?)\((0x[0-9a-fA-F]+),\s+struct\s([A-Za-z0-9_]+)\)' + matches = re.findall(pattern, hdr, re.MULTILINE) + return type("KFD_IOCTLS", (object, ), {name: int(nr, 0x10) for name, _, nr, _ in matches}), \ + {int(nr, 0x10): getattr(kfd, "struct_"+sname) for name, idir, nr, sname in matches} +kfd_ioctls, kfd_headers = ioctls_from_header() + +class KFDFileDesc(VirtFileDesc): + def __init__(self, fd, driver): + super().__init__(fd) + self.driver = driver + + def ioctl(self, fd, request, argp): return self.driver.kfd_ioctl(request, argp) + def mmap(self, start, sz, prot, flags, fd, offset): return offset + +class DRMFileDesc(VirtFileDesc): + def __init__(self, fd, driver, gpu): + super().__init__(fd) + self.driver, self.gpu = driver, gpu + + def mmap(self, start, sz, prot, flags, fd, offset): return libc.mmap(start, sz, prot, flags|mmap.MAP_ANONYMOUS, -1, 0) + +class AMDDriver(VirtDriver): + def __init__(self, gpus=6): + super().__init__() + + # NOTE: gpu ids start from one (id 0 is skipped in KFDIface._is_usable_gpu) + self.tracked_files += [VirtFile('/dev/kfd', functools.partial(KFDFileDesc, driver=self))] + \ + [VirtFile('/sys/devices/virtual/kfd/kfd/topology/nodes', functools.partial(DirFileDesc, child_names=[str(i+1) for i in range(gpus)]))] + + self.gpus = {} + self.next_fd = (1 << 30) + self.next_handle = 1 + self.next_event = 1 + + self.object_by_handle = {} + self.doorbells = {} + self.next_doorbell = collections.defaultdict(int) + self.mmu_event_ids = [] + + for i in range(gpus): self._prepare_gpu(i+1) + + def _alloc_fd(self): + my_fd = self.next_fd + self.next_fd = self.next_fd + 1 + return my_fd + + def _alloc_handle(self): + handle = self.next_handle + self.next_handle += 1 + return handle + + def _alloc_next_event_slot(self): + ev = self.next_event + self.next_event += 1 + return ev + + def _alloc_doorbell(self, gpu_id): + x = ctypes.addressof(from_mv(self.doorbells[gpu_id])) + self.next_doorbell[gpu_id] * 8 + self.next_doorbell[gpu_id] += 1 + return x + + def _prepare_gpu(self, gpu_id): + self.doorbells[gpu_id] = memoryview(bytearray(0x2000)) + self.gpus[gpu_id] = AMDGPU(gpu_id) + self.tracked_files += [ + VirtFile('/sys/module/amdgpu', functools.partial(TextFileDesc, text="1")), + VirtFile('/sys/module/amdgpu/parameters/ppfeaturemask', functools.partial(TextFileDesc, text="0xffff3fff")), + VirtFile(f'/sys/devices/virtual/kfd/kfd/topology/nodes/{gpu_id}', functools.partial(DirFileDesc, child_names=['gpu_id', 'properties'])), + VirtFile(f'/sys/devices/virtual/kfd/kfd/topology/nodes/{gpu_id}/gpu_id', functools.partial(TextFileDesc, text=f"{gpu_id}")), + VirtFile(f'/sys/devices/virtual/kfd/kfd/topology/nodes/{gpu_id}/properties', + functools.partial(TextFileDesc, text=gpu_props.format(drm_render_minor=gpu_id))), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0', + functools.partial(DirFileDesc, child_names=[str(am.GC_HWID), str(am.SDMA0_HWID), str(am.NBIF_HWID)])), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.GC_HWID}/0/major', functools.partial(TextFileDesc, text='11')), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.GC_HWID}/0/minor', functools.partial(TextFileDesc, text='0')), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.GC_HWID}/0/revision', functools.partial(TextFileDesc, text='0')), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.GC_HWID}/0/base_addr', + functools.partial(TextFileDesc, text='0x00001260\n0x0000A000\n0x0001C000\n0x02402C00')), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.SDMA0_HWID}/0/major', functools.partial(TextFileDesc, text='6')), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.SDMA0_HWID}/0/minor', functools.partial(TextFileDesc, text='0')), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.SDMA0_HWID}/0/revision', functools.partial(TextFileDesc, text='0')), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.SDMA0_HWID}/0/base_addr', + functools.partial(TextFileDesc, text='0x00001260\n0x0000A000\n0x0001C000\n0x02402C00')), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.NBIF_HWID}/0/major', functools.partial(TextFileDesc, text='4')), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.NBIF_HWID}/0/minor', functools.partial(TextFileDesc, text='3')), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.NBIF_HWID}/0/revision', functools.partial(TextFileDesc, text='0')), + VirtFile(f'/sys/class/drm/renderD{gpu_id}/device/ip_discovery/die/0/{am.NBIF_HWID}/0/base_addr', + functools.partial(TextFileDesc, text='0x00000000\n0x00000014\n0x00000D20\n0x00010400\n0x0241B000\n0x04040000')), + VirtFile(f'/dev/dri/renderD{gpu_id}', functools.partial(DRMFileDesc, driver=self, gpu=f"{self.gpus[gpu_id]}")), + ] + + def open(self, name, flags, mode, virtfile): return virtfile.fdcls(self._alloc_fd()) + + def kfd_ioctl(self, req, argp): + nr = req & 0xFF + struct = kfd_headers[nr].from_address(argp) + + if nr == kfd_ioctls.AMDKFD_IOC_ACQUIRE_VM: pass + elif nr == kfd_ioctls.AMDKFD_IOC_ALLOC_MEMORY_OF_GPU: + if struct.gpu_id not in self.gpus: return -1 + struct.handle = self._alloc_handle() + self.object_by_handle[struct.handle] = copy.deepcopy(struct) # save memory struct to know what mem it is + elif nr == kfd_ioctls.AMDKFD_IOC_FREE_MEMORY_OF_GPU: + self.object_by_handle.pop(struct.handle) + elif nr == kfd_ioctls.AMDKFD_IOC_MAP_MEMORY_TO_GPU: + dev_ids = (ctypes.c_int32 * struct.n_devices).from_address(struct.device_ids_array_ptr) + for i in range(struct.n_devices): + gpu = self.gpus[dev_ids[i]] + mem_obj = self.object_by_handle[struct.handle] + gpu.map_range(mem_obj.va_addr, mem_obj.size) + struct.n_success = i + 1 + elif nr == kfd_ioctls.AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU: + dev_ids = (ctypes.c_int32 * struct.n_devices).from_address(struct.device_ids_array_ptr) + for i in range(struct.n_devices): + gpu = self.gpus[dev_ids[i]] + mem_obj = self.object_by_handle[struct.handle] + gpu.unmap_range(mem_obj.va_addr, mem_obj.size) + struct.n_success = i + 1 + elif nr == kfd_ioctls.AMDKFD_IOC_CREATE_EVENT: + struct.event_slot_index = self._alloc_next_event_slot() + struct.event_id = struct.event_slot_index + + if struct.event_type == kfd.KFD_IOC_EVENT_MEMORY: self.mmu_event_ids.append(struct.event_id) + elif nr == kfd_ioctls.AMDKFD_IOC_CREATE_QUEUE: + gpu = self.gpus[struct.gpu_id] + if struct.queue_type == kfd.KFD_IOC_QUEUE_TYPE_SDMA: + gpu.add_sdma_queue(struct.ring_base_address, struct.ring_size, struct.read_pointer_address, struct.write_pointer_address) + elif struct.queue_type == kfd.KFD_IOC_QUEUE_TYPE_COMPUTE: + gpu.add_pm4_queue(struct.ring_base_address, struct.ring_size, struct.read_pointer_address, struct.write_pointer_address) + else: raise RuntimeError("Unsuported, queue") + + # Track writes to doorbell, calling callback + struct.doorbell_offset = self._alloc_doorbell(struct.gpu_id) + self.track_address(struct.doorbell_offset, struct.doorbell_offset + 8, lambda mv,off: None, lambda mv, off: self._emulate_execute()) + elif nr == kfd_ioctls.AMDKFD_IOC_WAIT_EVENTS: + evs = (kfd.struct_kfd_event_data * struct.num_events).from_address(struct.events_ptr) + for ev in evs: + if ev.event_id in self.mmu_event_ids and "MOCKGPU_EMU_FAULTADDR" in os.environ: + ev.memory_exception_data.gpu_id = 1 + ev.memory_exception_data.va = int(os.environ["MOCKGPU_EMU_FAULTADDR"], 16) + ev.memory_exception_data.failure.NotPresent = 1 + else: + name = "unknown" + for k,v in kfd_ioctls.__dict__.items(): + if nr == v: name = k + assert False, f"unknown kfd ioctl, {nr} {name}" + exit(1) + return 0 + + def _emulate_execute(self): + any_progress = True + while any_progress: + any_progress = False + for gpu in self.gpus.values(): + for q in gpu.queues: + if q.executing: any_progress |= q.execute() > 0 diff --git a/tinygrad_repo/test/mockgpu/amd/amdgpu.py b/tinygrad_repo/test/mockgpu/amd/amdgpu.py new file mode 100644 index 000000000..e46e894ad --- /dev/null +++ b/tinygrad_repo/test/mockgpu/amd/amdgpu.py @@ -0,0 +1,353 @@ +import ctypes, time +from test.mockgpu.gpu import VirtGPU +from tinygrad.helpers import getbits, to_mv, init_c_struct_t +import tinygrad.runtime.autogen.amd_gpu as amd_gpu, tinygrad.runtime.autogen.am.pm4_nv as pm4, tinygrad.runtime.autogen.am.soc21 as soc21 + +SDMA_MAX_COPY_SIZE = 0x400000 + +regCOMPUTE_PGM_LO = 0x1bac + amd_gpu.GC_BASE__INST0_SEG0 +regCOMPUTE_USER_DATA_0 = 0x1be0 + amd_gpu.GC_BASE__INST0_SEG0 +regCOMPUTE_NUM_THREAD_X = 0x1ba7 + amd_gpu.GC_BASE__INST0_SEG0 +regGRBM_GFX_INDEX = 0x2200 + amd_gpu.GC_BASE__INST0_SEG1 +regSQ_THREAD_TRACE_BUF0_BASE = 0x39e8 + amd_gpu.GC_BASE__INST0_SEG1 +regSQ_THREAD_TRACE_BUF0_SIZE = 0x39e9 + amd_gpu.GC_BASE__INST0_SEG1 +regSQ_THREAD_TRACE_WPTR = 0x39ef + amd_gpu.GC_BASE__INST0_SEG1 +regSQ_THREAD_TRACE_STATUS = 0x39f4 + amd_gpu.GC_BASE__INST0_SEG1 + +CACHE_FLUSH_AND_INV_TS_EVENT = 0x14 + +WAIT_REG_MEM_FUNCTION_ALWAYS = 0 +WAIT_REG_MEM_FUNCTION_EQ = 3 # == +WAIT_REG_MEM_FUNCTION_NEQ = 4 # != +WAIT_REG_MEM_FUNCTION_GEQ = 5 # >= + +REMU_PATHS = ["extra/remu/target/release/libremu.so", "libremu.so", "/usr/local/lib/libremu.so", + "extra/remu/target/release/libremu.dylib", "libremu.dylib", "/usr/local/lib/libremu.dylib", "/opt/homebrew/lib/libremu.dylib"] +def _try_dlopen_remu(): + for path in REMU_PATHS: + try: + remu = ctypes.CDLL(path) + remu.run_asm.restype = ctypes.c_int32 + remu.run_asm.argtypes = [ctypes.c_void_p, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, + ctypes.c_uint32, ctypes.c_uint32, ctypes.c_uint32, ctypes.c_void_p] + except OSError: pass + else: return remu + print("Could not find libremu.so") + return None +remu = _try_dlopen_remu() + +def create_sdma_packets(): + # TODO: clean up this, if we want to keep it + structs = {} + for name,pkt in [(name,s) for name,s in amd_gpu.__dict__.items() if name.startswith("struct_SDMA_PKT_") and name.endswith("_TAG")]: + names = set() + fields = [] + for pkt_fields in pkt._fields_: + if not pkt_fields[0].endswith("_UNION"): fields.append(pkt_fields) + else: + assert pkt_fields[1]._fields_[0][0] == '_0' + for union_fields in pkt_fields[1]._fields_[0][1]._fields_: + fname = union_fields[0] + if fname in names: fname = pkt_fields[0]+fname + names.add(fname) + # merge together 64-bit fields, otherwise just append them + if fname.endswith("_63_32") and fields[-1][0].endswith("_31_0"): fields[-1] = tuple([fname[:-6], ctypes.c_ulong, 64]) + else: fields.append(tuple([fname, *union_fields[1:]])) + new_name = name[16:-4].lower() + structs[new_name] = init_c_struct_t(tuple(fields)) + assert ctypes.sizeof(structs[new_name]) == ctypes.sizeof(pkt), f"{ctypes.sizeof(structs[new_name])} != {ctypes.sizeof(pkt)}" + return type("SDMA_PKTS", (object, ), structs) +sdma_pkts = create_sdma_packets() + +class AMDQueue: + def __init__(self, base, size, rptr, wptr): + self.queue, self.size = to_mv(base, size).cast("I"), size + self.rptr = to_mv(rptr, 8).cast("Q") if isinstance(rptr, int) else rptr + self.wptr = to_mv(wptr, 8).cast("Q") if isinstance(wptr, int) else wptr + + @property + def executing(self): return self.rptr[0] < self.wptr[0] + +class PM4Executor(AMDQueue): + def __init__(self, gpu, base, size, rptr, wptr): + self.gpu = gpu + self.ib_executor: PM4Executor|None = None + super().__init__(base, size, rptr, wptr) + + def _next_dword(self): + x = self.queue[self.rptr[0] % (self.size // 4)] + self.rptr[0] += 1 + return x + + @property + def executing(self): return self.rptr[0] < self.wptr[0] or self.ib_executor is not None + + def execute(self): + prev_rptr, executed_in_ib, cont = self.rptr[0], 0, True + while self.executing and cont: + if self.ib_executor is not None: + executed_in_ib += self.ib_executor.execute() + if self.ib_executor.executing: break + self.ib_executor = None + continue # this continue is needed if PACKET3_INDIRECT_BUFFER is the last packet and rptr == wptr + header = self._next_dword() + packet_type = header >> 30 + op = (header >> 8) & 0xFF + n = (header >> 16) & 0x3FFF + assert packet_type == 3, "Can parse only packet3" + if op == amd_gpu.PACKET3_SET_SH_REG: self._exec_set_reg(n, pm4.PACKET3_SET_SH_REG_START) + elif op == amd_gpu.PACKET3_SET_UCONFIG_REG: self._exec_set_reg(n, pm4.PACKET3_SET_UCONFIG_REG_START) + elif op == amd_gpu.PACKET3_ACQUIRE_MEM: self._exec_acquire_mem(n) + elif op == amd_gpu.PACKET3_RELEASE_MEM: self._exec_release_mem(n) + elif op == amd_gpu.PACKET3_COPY_DATA: self._exec_copy_data(n) + elif op == amd_gpu.PACKET3_WAIT_REG_MEM: cont = self._exec_wait_reg_mem(n) + elif op == amd_gpu.PACKET3_DISPATCH_DIRECT: self._exec_dispatch_direct(n) + elif op == amd_gpu.PACKET3_INDIRECT_BUFFER: self._exec_indirect_buffer(n) + elif op == amd_gpu.PACKET3_EVENT_WRITE: self._exec_event_write(n) + else: raise RuntimeError(f"PM4: Unknown opcode: {op}") + return (self.rptr[0] - prev_rptr) + executed_in_ib + + def _exec_acquire_mem(self, n): + assert n == 6 + for _ in range(7): self._next_dword() # TODO: implement + + def _exec_release_mem(self, n): + assert n == 6 + mem_event_type = (self._next_dword() >> 0) & 0xff + selectors = self._next_dword() + mem_data_sel = (selectors >> 29) & 0b111 + # int_sel = (selectors >> 24) & 0b11 + # mem_dst_sel = (selectors >> 16) & 0b1 + addr_lo = self._next_dword() + addr_hi = self._next_dword() + val_lo = self._next_dword() + val_hi = self._next_dword() + val = val_lo + (val_hi << 32) + _ = self._next_dword() # ev + + ptr = to_mv(addr_lo + (addr_hi << 32), 8) + if mem_data_sel == 1 or mem_data_sel == 2: ptr.cast('Q')[0] = val + elif mem_data_sel == 3: + if mem_event_type == CACHE_FLUSH_AND_INV_TS_EVENT: ptr.cast('Q')[0] = int(time.perf_counter() * 1e8) + else: raise RuntimeError(f"Unknown {mem_data_sel=} {mem_event_type=}") + else: raise RuntimeError(f"Unknown {mem_data_sel=}") + + def _exec_copy_data(self, n): + assert n == 4 + copy_data_flags = self._next_dword() + src_addr_lo = self._next_dword() + _src_addr_hi = self._next_dword() + dst_addr_lo = self._next_dword() + dst_addr_hi = self._next_dword() + assert copy_data_flags == 0x100204, hex(copy_data_flags) # better fail than silently do the wrong thing + to_mv(dst_addr_hi<<32|dst_addr_lo, 4).cast('I')[0] = self.gpu.regs[src_addr_lo] + + def _exec_wait_reg_mem(self, n): + assert n == 5 + info = self._next_dword() + addr_lo = self._next_dword() + addr_hi = self._next_dword() + val = self._next_dword() + mask = self._next_dword() + _ = self._next_dword() # timeout + + mem_function = (info >> 0) & 0b111 + mem_space = (info >> 4) & 0b1 + mem_op = (info >> 6) & 0b1 + _ = (info >> 8) & 0b1 # mem_engine + + if mem_space == 0 and mem_op == 1: mval = val # hack for memory barrier, should properly handle (req_req, reg_done) + elif mem_space == 0: mval = self.gpu.regs[addr_hi<<32|addr_lo] + elif mem_space == 1: mval = to_mv(addr_lo + (addr_hi << 32), 4).cast('I')[0] + + mval &= mask + + if mem_function == WAIT_REG_MEM_FUNCTION_GEQ: can_cont = bool(mval >= val) + elif mem_function == WAIT_REG_MEM_FUNCTION_NEQ: can_cont = bool(mval != val) + elif mem_function == WAIT_REG_MEM_FUNCTION_EQ: can_cont = bool(mval == val) + else: raise RuntimeError(f"Do not support {mem_function=}") + + if not can_cont: self.rptr[0] = self.rptr[0] - 7 # revert this packet, need to wait again + return can_cont + + def _exec_set_reg(self, n, off): + reg = off + self._next_dword() + for i in range(n): + self.gpu.regs[reg] = self._next_dword() + reg += 1 + + def _exec_dispatch_direct(self, n): + assert n == 3 + gl = [self._next_dword() for _ in range(3)] + _ = self._next_dword() # flags + + prg_addr = (self.gpu.regs[regCOMPUTE_PGM_LO] + (self.gpu.regs[regCOMPUTE_PGM_LO + 1] << 32)) << 8 + args_addr = self.gpu.regs[regCOMPUTE_USER_DATA_0] + (self.gpu.regs[regCOMPUTE_USER_DATA_0 + 1] << 32) + lc = [self.gpu.regs[i] for i in range(regCOMPUTE_NUM_THREAD_X, regCOMPUTE_NUM_THREAD_X+3)] + + prg_sz = 0 + for st,sz in self.gpu.mapped_ranges: + if st <= prg_addr < st+sz: prg_sz = sz - (prg_addr - st) + + assert prg_sz > 0, "Invalid prg ptr (not found in mapped ranges)" + err = remu.run_asm(prg_addr, prg_sz, *gl, *lc, args_addr) + if err != 0: raise RuntimeError("remu does not support the new instruction introduced in this kernel") + + def _exec_indirect_buffer(self, n): + addr_lo = self._next_dword() + addr_hi = self._next_dword() + buf_sz = self._next_dword() & (0x7fffff) + + rptr = memoryview(bytearray(8)).cast('Q') + wptr = memoryview(bytearray(8)).cast('Q') + rptr[0] = 0 + wptr[0] = buf_sz + self.ib_executor = PM4Executor(self.gpu, (addr_hi << 32) | addr_lo, buf_sz * 4, rptr, wptr) + + def _exec_event_write(self, n): + assert n == 0 + event_dw = self._next_dword() + match (event_dw & 0xFF): # event type + case soc21.THREAD_TRACE_FINISH: + old_idx = self.gpu.regs.grbm_index + for se in range(self.gpu.regs.n_se): + self.gpu.regs.grbm_index = 0b011 << 29 | se << 16 # select se, broadcast sa and instance + self.gpu.regs[regSQ_THREAD_TRACE_STATUS] = 1 << 12 # FINISH_PENDING==0 FINISH_DONE==1 BUSY==0 + buf = ((self.gpu.regs[regSQ_THREAD_TRACE_BUF0_SIZE]&0xf)<<32|self.gpu.regs[regSQ_THREAD_TRACE_BUF0_BASE])<<12 # per page addressing + fake_used = 0x1000 # fake one page long trace + self.gpu.regs[regSQ_THREAD_TRACE_WPTR] = ((buf+fake_used)//32) & 0x1FFFFFFF + self.gpu.regs.grbm_index = old_idx + case _: pass # NOTE: for now most events aren't emulated + +class SDMAExecutor(AMDQueue): + def __init__(self, gpu, base, size, rptr, wptr): + self.gpu, self.base = gpu, base + super().__init__(base, size, rptr, wptr) + + def execute(self): + prev_rptr, cont = self.rptr[0], True + while self.executing and cont: + header = self.queue[(self.rptr[0] // 4) % (self.size // 4)] + op = (header >> 0) & 0xff + if op == 0: self.rptr[0] += 4 + elif op == amd_gpu.SDMA_OP_FENCE: self._execute_fence() + elif op == amd_gpu.SDMA_OP_TRAP: self._execute_trap() + elif op == amd_gpu.SDMA_OP_POLL_REGMEM: cont = self._execute_poll_regmem() + elif op == amd_gpu.SDMA_OP_GCR: self._execute_gcr() + elif op == amd_gpu.SDMA_OP_COPY: self._execute_copy() + elif op == amd_gpu.SDMA_OP_TIMESTAMP: self._execute_timestamp() + else: raise RuntimeError(f"Unknown SDMA op {op}") + return self.rptr[0] - prev_rptr + + def _execute_fence(self): + struct = sdma_pkts.fence.from_address(self.base + self.rptr[0] % self.size) + to_mv(struct.addr, 8).cast('Q')[0] = struct.data + self.rptr[0] += ctypes.sizeof(struct) + + def _execute_trap(self): + struct = sdma_pkts.trap.from_address(self.base + self.rptr[0] % self.size) + self.rptr[0] += ctypes.sizeof(struct) + + def _execute_poll_regmem(self): + struct = sdma_pkts.poll_regmem.from_address(self.base + self.rptr[0] % self.size) + + if struct.mem_poll == 0: mval = struct.value & struct.mask + elif struct.mem_poll == 1: mval = to_mv(struct.addr, 4).cast('I')[0] & struct.mask + + if struct.func == WAIT_REG_MEM_FUNCTION_GEQ: can_cont = bool(mval >= struct.value) + elif struct.func == WAIT_REG_MEM_FUNCTION_EQ: can_cont = bool(mval == struct.value) + elif struct.func == WAIT_REG_MEM_FUNCTION_ALWAYS: can_cont = True + else: raise RuntimeError(f"Do not support {struct.func=}") + + if not can_cont: return False + + self.rptr[0] += ctypes.sizeof(struct) + return True + + def _execute_timestamp(self): + struct = sdma_pkts.timestamp.from_address(self.base + self.rptr[0] % self.size) + + mem = to_mv(struct.addr, 8).cast('Q') + mem[0] = int(time.perf_counter() * 1e8) + + self.rptr[0] += ctypes.sizeof(struct) + + def _execute_gcr(self): + struct = sdma_pkts.gcr.from_address(self.base + self.rptr[0] % self.size) + self.rptr[0] += ctypes.sizeof(struct) + + def _execute_copy(self): + struct = sdma_pkts.copy_linear.from_address(self.base + self.rptr[0] % self.size) + count_cnt = to_mv(self.base + self.rptr[0] + 4, 4).cast('I')[0] & 0x3FFFFFFF + ctypes.memmove(struct.dst_addr, struct.src_addr, count_cnt + 1) + self.rptr[0] += ctypes.sizeof(struct) + +class AMDGPURegisters: + def __init__(self, n_se:int=6): + self.n_se = n_se + self.grbm_index = 0b111 << 0x1d # all broadcast. NOTE: only per-se register emulation is currently supported + self.regs: dict[tuple[int, int], int] = {} + def __getitem__(self, addr:int) -> int: + if addr == regGRBM_GFX_INDEX: return self.grbm_index + return self.regs[(addr, getbits(self.grbm_index, 16, 23))] + def __setitem__(self, addr:int, val:int): + if addr == regGRBM_GFX_INDEX: self.grbm_index = val + if getbits(self.grbm_index, 31, 31): + for se in range(self.n_se): self.regs[(addr, se)] = val + else: + self.regs[(addr, getbits(self.grbm_index, 16, 23))] = val + +class AMDGPU(VirtGPU): + def __init__(self, gpuid): + super().__init__(gpuid) + self.regs = AMDGPURegisters() + self.mapped_ranges = set() + self.queues = [] + + def map_range(self, vaddr, size): self.mapped_ranges.add((vaddr, size)) + def unmap_range(self, vaddr, size): self.mapped_ranges.remove((vaddr, size)) + def add_pm4_queue(self, base, size, rptr, wptr): + self.queues.append(PM4Executor(self, base, size, rptr, wptr)) + return len(self.queues) - 1 + def add_sdma_queue(self, base, size, rptr, wptr): + self.queues.append(SDMAExecutor(self, base, size, rptr, wptr)) + return len(self.queues) - 1 + +gpu_props = """cpu_cores_count 0 +simd_count 192 +mem_banks_count 1 +caches_count 206 +io_links_count 1 +p2p_links_count 5 +cpu_core_id_base 0 +simd_id_base 2147488032 +max_waves_per_simd 16 +lds_size_in_kb 64 +gds_size_in_kb 0 +num_gws 64 +wave_front_size 32 +array_count 12 +simd_arrays_per_engine 2 +cu_per_simd_array 8 +simd_per_cu 2 +max_slots_scratch_cu 32 +gfx_target_version 110000 +vendor_id 4098 +device_id 29772 +location_id 34304 +domain 0 +drm_render_minor {drm_render_minor} +hive_id 0 +num_sdma_engines 2 +num_sdma_xgmi_engines 0 +num_sdma_queues_per_engine 6 +num_cp_queues 8 +max_engine_clk_fcompute 2482 +local_mem_size 0 +fw_version 2140 +capability 671588992 +debug_prop 1495 +sdma_fw_version 20 +unique_id 11673270660693242239 +num_xcc 1 +max_engine_clk_ccompute 2400""" diff --git a/tinygrad_repo/test/mockgpu/cuda/cuda.py b/tinygrad_repo/test/mockgpu/cuda/cuda.py new file mode 100644 index 000000000..a5dd5fe0c --- /dev/null +++ b/tinygrad_repo/test/mockgpu/cuda/cuda.py @@ -0,0 +1,170 @@ +from __future__ import annotations +from typing import Any +import ctypes, time +from tinygrad.runtime.autogen import cuda as orig_cuda +from tinygrad.helpers import mv_address + +for attr in dir(orig_cuda): + if not attr.startswith('__'): + globals()[attr] = getattr(orig_cuda, attr) + +try: + gpuocelot_lib = ctypes.CDLL(ctypes.util.find_library("gpuocelot")) + gpuocelot_lib.ptx_run.argtypes = [ctypes.c_char_p, ctypes.c_int, ctypes.POINTER(ctypes.c_void_p), ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int] # noqa: E501 +except Exception: pass + +# Global state +class CUDAState: + def __init__(self): + self.memory: dict[int, memoryview] = {} + self.events: dict[int, float] = {} # Event ID -> timestamp + self.modules: dict[int, memoryview] = {} # Module ID -> code + self.current_context: int|None = None + self.contexts: dict[int, dict] = {} # Context ID -> context data + self.devices: dict[int, dict] = {} # Device ID -> device data + self.next_ptr = 1000 # For memory allocation + self.next_event_id = 1 + self.next_module_id = 1 + self.next_context_id = 1 + +cuda_state = CUDAState() + +# Helper functions +def check_context(): + if cuda_state.current_context is None: + return orig_cuda.CUDA_ERROR_INVALID_VALUE + return orig_cuda.CUDA_SUCCESS + +# CUDA API simulation +def cuInit(flags: int) -> int: + return orig_cuda.CUDA_SUCCESS + +def cuDeviceGet(device, ordinal: int) -> int: + if ordinal < 0: + return orig_cuda.CUDA_ERROR_INVALID_VALUE + device._obj.value = ordinal + cuda_state.devices[ordinal] = {"compute_capability": (3, 5)} + return orig_cuda.CUDA_SUCCESS + +def cuCtxCreate_v2(pctx, flags: int, dev: int) -> int: + ctx_id = cuda_state.next_context_id + cuda_state.next_context_id += 1 + cuda_state.contexts[ctx_id] = {"device": dev, "flags": flags} + pctx._obj.value = ctx_id + return orig_cuda.CUDA_SUCCESS + +def cuCtxSetCurrent(context) -> int: + if context.value not in cuda_state.contexts: + return orig_cuda.CUDA_ERROR_INVALID_VALUE + cuda_state.current_context = context.value + return orig_cuda.CUDA_SUCCESS + +def cuMemAlloc_v2(dptr, bytesize: int) -> int: + x = memoryview(bytearray(bytesize)) + dptr._obj.value = mv_address(x) + cuda_state.memory[dptr._obj.value] = x + return orig_cuda.CUDA_SUCCESS + +def cuMemFree_v2(dptr) -> int: + if dptr.value in cuda_state.memory: + del cuda_state.memory[dptr.value] + return orig_cuda.CUDA_SUCCESS + return orig_cuda.CUDA_ERROR_INVALID_VALUE + +def cuMemcpyHtoDAsync_v2(dst, src: ctypes.c_void_p, bytesize: int, stream: Any) -> int: + ctypes.memmove(dst.value, src, bytesize) + return orig_cuda.CUDA_SUCCESS + +def cuMemcpyDtoH_v2(dst: ctypes.c_void_p, src, bytesize: int) -> int: + ctypes.memmove(dst, src.value, bytesize) + return orig_cuda.CUDA_SUCCESS + +def cuEventCreate(phEvent, flags: int) -> int: + event_id = cuda_state.next_event_id + cuda_state.next_event_id += 1 + cuda_state.events[event_id] = 0.0 + phEvent._obj.value = event_id + return orig_cuda.CUDA_SUCCESS + +def cuEventRecord(hEvent, hStream: Any) -> int: + if hEvent.value not in cuda_state.events: + return orig_cuda.CUDA_ERROR_INVALID_VALUE + cuda_state.events[hEvent.value] = time.perf_counter_ns() + return orig_cuda.CUDA_SUCCESS + +def cuEventSynchronize(hEvent) -> int: + if hEvent.value not in cuda_state.events: + return orig_cuda.CUDA_ERROR_INVALID_VALUE + return orig_cuda.CUDA_SUCCESS + +def cuEventElapsedTime(pMilliseconds, hStart, hEnd) -> int: + if hStart.value not in cuda_state.events or hEnd.value not in cuda_state.events: + return orig_cuda.CUDA_ERROR_INVALID_VALUE + elapsed = (cuda_state.events[hEnd.value] - cuda_state.events[hStart.value]) * 1e-6 + pMilliseconds._obj.value = elapsed + return orig_cuda.CUDA_SUCCESS + +def cuEventDestroy_v2(hEvent) -> int: + if hEvent.value in cuda_state.events: + del cuda_state.events[hEvent.value] + return orig_cuda.CUDA_SUCCESS + +def cuModuleLoadData(module, image: bytes) -> int: + module_id = cuda_state.next_module_id + cuda_state.next_module_id += 1 + cuda_state.modules[module_id] = memoryview(bytearray(image)) + module._obj.value = module_id + return orig_cuda.CUDA_SUCCESS + +def cuModuleGetFunction(hfunc, hmod, name: bytes) -> int: + if hmod.value not in cuda_state.modules: + return orig_cuda.CUDA_ERROR_INVALID_VALUE + hfunc._obj.value = mv_address(cuda_state.modules[hmod.value]) + return orig_cuda.CUDA_SUCCESS + +def cuModuleUnload(hmod) -> int: + if hmod.value in cuda_state.modules: + del cuda_state.modules[hmod.value] + return orig_cuda.CUDA_SUCCESS + +def cuLaunchKernel(f, gx: int, gy: int, gz: int, lx: int, ly: int, lz: int, sharedMemBytes: int, + hStream: Any, kernelParams: Any, extra: Any) -> int: + cargs = [ctypes.cast(getattr(extra, field[0]), ctypes.c_void_p) for field in extra._fields_] + gpuocelot_lib.ptx_run(ctypes.cast(f.value, ctypes.c_char_p), len(cargs), (ctypes.c_void_p*len(cargs))(*cargs), lx, ly, lz, gx, gy, gz, 0) + return orig_cuda.CUDA_SUCCESS + +def cuDeviceComputeCapability(major, minor, dev: int) -> int: + if dev not in cuda_state.devices: + return orig_cuda.CUDA_ERROR_INVALID_VALUE + major._obj.value = 3 + minor._obj.value = 5 + return orig_cuda.CUDA_SUCCESS + +def cuDeviceCanAccessPeer(canAccessPeer, dev: int, peerDev: int) -> int: + canAccessPeer._obj.value = 1 # Always allow peer access in simulation + return orig_cuda.CUDA_SUCCESS + +def cuCtxEnablePeerAccess(peerContext, flags: int) -> int: + return orig_cuda.CUDA_SUCCESS + +def cuMemHostAlloc(pp, bytesize: int, flags: int) -> int: + return cuMemAlloc_v2(pp, bytesize) + +def cuMemFreeHost(p: ctypes.c_void_p) -> int: return cuMemFree_v2(p) + +def cuMemcpyDtoDAsync_v2(dst, src, bytesize: int, stream: Any) -> int: + ctypes.memmove(dst.value, src.value, bytesize) + return orig_cuda.CUDA_SUCCESS + +def cuFuncSetAttribute(hfunc, attrib: int, value: int) -> int: + return orig_cuda.CUDA_SUCCESS + +def cuStreamWaitEvent(stream: Any, event, flags: int) -> int: return orig_cuda.CUDA_SUCCESS +def cuCtxSynchronize() -> int: return orig_cuda.CUDA_SUCCESS + +def cuGetErrorString(error: int, pStr) -> int: + error_str = orig_cuda.cudaError_enum__enumvalues.get(error, "Unknown CUDA error").encode() + buf = ctypes.create_string_buffer(error_str) + # Set the pointer to point to our error string buffer + pStr._obj.value = ctypes.cast(buf, ctypes.POINTER(ctypes.c_char)) + return orig_cuda.CUDA_SUCCESS diff --git a/tinygrad_repo/test/mockgpu/driver.py b/tinygrad_repo/test/mockgpu/driver.py new file mode 100644 index 000000000..7be165cb0 --- /dev/null +++ b/tinygrad_repo/test/mockgpu/driver.py @@ -0,0 +1,39 @@ +from typing import Any +from dataclasses import dataclass + +class VirtFileDesc: + def __init__(self, fd): self.fd, self.off = fd, 0 + def ioctl(self, fd, req, argp): raise NotImplementedError() + def mmap(self, st, sz, prot, flags, fd, off): raise NotImplementedError() + def close(self, fd): return 0 + +class TextFileDesc(VirtFileDesc): + def __init__(self, fd, text): + super().__init__(fd) + self.content = text + + def ioctl(self, fd, req, argp): return 0 + def read_contents(self, size=None): + ret = self.content[self.off:self.off+(size or len(self.content))] + self.off += (size or len(self.content)) + return ret + def seek(self, offset): self.off += offset +class DirFileDesc(VirtFileDesc): + def __init__(self, fd, child_names): + super().__init__(fd) + self.child_names = child_names + + def ioctl(self, fd, req, argp): return 0 + def list_contents(self): return self.child_names + +@dataclass(frozen=True) +class VirtFile: + path: str + fdcls: Any # TODO: fix this Union[VirtFileDesc, functools.partial[VirtFileDesc]] + +class VirtDriver: + def __init__(self): + self.tracked_files = [] + self.tracked_addresses = [] + def track_address(self, staddr, enaddr, rcb, wcb): self.tracked_addresses.append((staddr, enaddr, rcb, wcb)) + def open(self, name, flags, mode, fdcls): raise NotImplementedError() diff --git a/tinygrad_repo/test/mockgpu/gpu.py b/tinygrad_repo/test/mockgpu/gpu.py new file mode 100644 index 000000000..296486b9c --- /dev/null +++ b/tinygrad_repo/test/mockgpu/gpu.py @@ -0,0 +1,4 @@ +class VirtGPU: + def __init__(self, gpuid): self.gpuid = gpuid + def map_range(self, vaddr, size): raise NotImplementedError() + def unmap_range(self, vaddr, size): raise NotImplementedError() diff --git a/tinygrad_repo/test/mockgpu/mockgpu.py b/tinygrad_repo/test/mockgpu/mockgpu.py new file mode 100644 index 000000000..9e60fa397 --- /dev/null +++ b/tinygrad_repo/test/mockgpu/mockgpu.py @@ -0,0 +1,101 @@ +import ctypes, ctypes.util, time, os, builtins, fcntl +from tinygrad.runtime.support.hcq import FileIOInterface +from test.mockgpu.nv.nvdriver import NVDriver +from test.mockgpu.amd.amddriver import AMDDriver +start = time.perf_counter() + +# *** ioctl lib *** +libc = ctypes.CDLL(ctypes.util.find_library("c")) +libc.mmap.argtypes = [ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long] +libc.mmap.restype = ctypes.c_void_p + +drivers = [AMDDriver(), NVDriver()] +tracked_fds = {} + +orignal_memoryview = builtins.memoryview +class TrackedMemoryView: + def __init__(self, data, rcb, wcb): + self.mv = orignal_memoryview(data) + self.rcb, self.wcb = rcb, wcb + + def __getitem__(self, index): + self.rcb(self.mv, index) + return self.mv[index] + + def __setitem__(self, index, value): + self.mv[index] = value + self.wcb(self.mv, index) + + def cast(self, new_type, **kwargs): + self.mv = self.mv.cast('B').cast(new_type, **kwargs) + return self + + @property + def nbytes(self): return self.mv.nbytes + def __len__(self): return len(self.mv) + def __repr__(self): return repr(self.mv) + +def _memoryview(cls, mem): + if isinstance(mem, int) or isinstance(mem, ctypes.Array): + addr = ctypes.addressof(mem) if isinstance(mem, ctypes.Array) else mem + for d in drivers: + for st,en,rcb,wcb in d.tracked_addresses: + if st <= addr <= en: return TrackedMemoryView(mem, rcb, wcb) + return orignal_memoryview(mem) +builtins.memoryview = type("memoryview", (), {'__new__': _memoryview}) # type: ignore + +def _open(path, flags): + for d in drivers: + for x in d.tracked_files: + if path == x.path: + virtfd = d.open(path, flags, 0o777, x) + tracked_fds[virtfd.fd] = virtfd + return virtfd.fd + return os.open(path, flags, 0o777) if os.path.exists(path) else None + +class MockFileIOInterface(FileIOInterface): + def __init__(self, path:str="", flags:int=os.O_RDONLY, fd:int|None=None): + self.path = path + self.fd = fd or _open(path, flags) + + def __del__(self): + if self.fd in tracked_fds: + tracked_fds[self.fd].close(self.fd) + tracked_fds.pop(self.fd) + else: os.close(self.fd) + + def ioctl(self, request, arg): + if self.fd in tracked_fds: + return tracked_fds[self.fd].ioctl(self.fd, request, ctypes.addressof(arg)) + return fcntl.ioctl(self.fd, request, arg) + + def mmap(self, start, sz, prot, flags, offset): + if self.fd in tracked_fds: + return tracked_fds[self.fd].mmap(start, sz, prot, flags, self.fd, offset) + return libc.mmap(start, sz, prot, flags, self.fd, offset) + + def read(self, size=None, binary=False, offset=None): + if binary: raise NotImplementedError() + if self.fd in tracked_fds: + return tracked_fds[self.fd].read_contents(size) + with open(self.fd, "rb" if binary else "r", closefd=False) as file: + if file.tell() >= os.fstat(self.fd).st_size: file.seek(0) + return file.read(size) + + def listdir(self): + if self.fd in tracked_fds: + return tracked_fds[self.fd].list_contents() + return os.listdir(self.path) + + def write(self, content, binary=False, offset=None): raise NotImplementedError() + def seek(self, offset): + if self.fd in tracked_fds: + tracked_fds[self.fd].seek(offset) + else: + os.lseek(self.fd, offset, os.SEEK_CUR) + @staticmethod + def exists(path): return _open(path, os.O_RDONLY) is not None + @staticmethod + def readlink(path): raise NotImplementedError() + @staticmethod + def eventfd(initval, flags=None): NotImplementedError() diff --git a/tinygrad_repo/test/mockgpu/nv/nvdriver.py b/tinygrad_repo/test/mockgpu/nv/nvdriver.py new file mode 100644 index 000000000..d7c330c60 --- /dev/null +++ b/tinygrad_repo/test/mockgpu/nv/nvdriver.py @@ -0,0 +1,257 @@ +import ctypes, mmap, collections, functools, os +import tinygrad.runtime.autogen.nv_gpu as nv_gpu +from typing import Any +from tinygrad.helpers import to_mv +from test.mockgpu.driver import VirtDriver, VirtFileDesc, VirtFile +from test.mockgpu.nv.nvgpu import NVGPU + +MAP_FIXED = 0x10 +libc = ctypes.CDLL(ctypes.util.find_library("c")) +libc.mmap.argtypes = [ctypes.c_void_p, ctypes.c_size_t, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_long] +libc.mmap.restype = ctypes.c_void_p +libc.munmap.argtypes = [ctypes.c_void_p, ctypes.c_size_t] +libc.munmap.restype = ctypes.c_int + +NVSubDevice = collections.namedtuple('NVSubDevice', ['device']) +NVUserMode = collections.namedtuple('NVUserMode', ['subdevice']) +NVVASpace = collections.namedtuple('NVVASpace', ['device']) +NVAllocation = collections.namedtuple('NVAllocation', ['device', 'size']) +NVChannelGroup = collections.namedtuple('NVChannelGroup', ['device']) +NVContextShare = collections.namedtuple('NVContextShare', ['channel_group']) +NVGPFIFO = collections.namedtuple('NVGPFIFO', ['device', 'token']) + +class NVCtlFileDesc(VirtFileDesc): + def __init__(self, fd, driver): + super().__init__(fd) + self.driver = driver + + def ioctl(self, fd, request, argp): return self.driver.ctl_ioctl(request, argp) + def mmap(self, start, sz, prot, flags, fd, offset): return libc.mmap(start, sz, prot, flags|mmap.MAP_ANONYMOUS, -1, 0) + +class NVUVMFileDesc(VirtFileDesc): + def __init__(self, fd, driver): + super().__init__(fd) + self.driver = driver + + def ioctl(self, fd, request, argp): return self.driver.uvm_ioctl(request, argp) + def mmap(self, start, sz, prot, flags, fd, offset): return libc.mmap(start, sz, prot, flags|mmap.MAP_ANONYMOUS, -1, 0) + +class NVDevFileDesc(VirtFileDesc): + def __init__(self, fd, driver, gpu): + super().__init__(fd) + self.driver, self.gpu = driver, gpu + self._mapping_userland = False + + def ioctl(self, fd, request, argp): return self.driver.dev_ioctl(self.gpu, request, argp) + def mmap(self, start, sz, prot, flags, fd, offset): + start = libc.mmap(start, sz, prot, flags|mmap.MAP_ANONYMOUS, -1, 0) + if self._mapping_userland: + self.driver.track_address(start, start+sz, lambda mv,off: None, lambda mv, off: self.driver._gpu_mmio_write(mv, off, self.gpu)) + return start + +class NVDriver(VirtDriver): + def __init__(self, gpus=6): + super().__init__() + + self.tracked_files += [VirtFile('/dev/nvidiactl', functools.partial(NVCtlFileDesc, driver=self)), + VirtFile('/dev/nvidia-uvm', functools.partial(NVUVMFileDesc, driver=self))] + + self.root_handle = None + + self.gpus = {} + self.next_fd = (1 << 29) + self.next_handle = 1 + + self.object_by_handle = {} + self.opened_fds = {} + self.next_doorbell = collections.defaultdict(int) + + for i in range(gpus): self._prepare_gpu(i) + + def _alloc_fd(self): + my_fd = self.next_fd + self.next_fd = self.next_fd + 1 + return my_fd + + def _alloc_handle(self): + handle = self.next_handle + self.next_handle += 1 + return handle + + def _prepare_gpu(self, gpu_id): + self.gpus[gpu_id] = NVGPU(gpu_id) + self.tracked_files += [VirtFile(f'/dev/nvidia{gpu_id}', functools.partial(NVDevFileDesc, driver=self, gpu=self.gpus[gpu_id]))] + + def open(self, name, flags, mode, virtfile): + cl = virtfile.fdcls(self._alloc_fd()) + self.opened_fds[cl.fd] = cl + return cl + + def rm_alloc(self, argp): + struct = nv_gpu.NVOS21_PARAMETERS.from_address(argp) + params_ptr = struct.pAllocParms + if struct.hClass == nv_gpu.NV01_ROOT_CLIENT: self.root_handle = struct.hObjectNew = self._alloc_handle() + elif struct.hClass == nv_gpu.NV01_DEVICE_0: + params:Any = nv_gpu.NV0080_ALLOC_PARAMETERS.from_address(params_ptr) + assert params.hClientShare == self.root_handle + struct.hObjectNew = self._alloc_handle() + self.object_by_handle[struct.hObjectNew] = self.gpus[params.deviceId] + elif struct.hClass == nv_gpu.NV20_SUBDEVICE_0: + assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVGPU) + struct.hObjectNew = self._alloc_handle() + self.object_by_handle[struct.hObjectNew] = NVSubDevice(self.object_by_handle[struct.hObjectParent]) + elif struct.hClass == nv_gpu.TURING_USERMODE_A: + assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVSubDevice) + struct.hObjectNew = self._alloc_handle() + self.object_by_handle[struct.hObjectNew] = NVUserMode(self.object_by_handle[struct.hObjectParent]) + elif struct.hClass == nv_gpu.FERMI_VASPACE_A: + assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVGPU) + struct.hObjectNew = self._alloc_handle() + self.object_by_handle[struct.hObjectNew] = NVVASpace(self.object_by_handle[struct.hObjectParent]) + elif struct.hClass == nv_gpu.NV1_MEMORY_SYSTEM or struct.hClass == nv_gpu.NV1_MEMORY_USER: + assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVGPU) + params = nv_gpu.NV_MEMORY_ALLOCATION_PARAMS.from_address(params_ptr) + struct.hObjectNew = self._alloc_handle() + self.object_by_handle[struct.hObjectNew] = NVAllocation(self.object_by_handle[struct.hObjectParent], params.size) + elif struct.hClass == nv_gpu.KEPLER_CHANNEL_GROUP_A: + assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVGPU) + struct.hObjectNew = self._alloc_handle() + self.object_by_handle[struct.hObjectNew] = NVChannelGroup(self.object_by_handle[struct.hObjectParent]) + elif struct.hClass == nv_gpu.FERMI_CONTEXT_SHARE_A: + assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVChannelGroup) + struct.hObjectNew = self._alloc_handle() + self.object_by_handle[struct.hObjectNew] = NVContextShare(self.object_by_handle[struct.hObjectParent]) + elif struct.hClass == nv_gpu.AMPERE_CHANNEL_GPFIFO_A: + assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVChannelGroup) + struct.hObjectNew = self._alloc_handle() + params = nv_gpu.NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS.from_address(params_ptr) + gpu = self.object_by_handle[struct.hObjectParent].device + gpfifo_token = gpu.add_gpfifo(params.gpFifoOffset, params.gpFifoEntries) + self.object_by_handle[struct.hObjectNew] = NVGPFIFO(gpu, gpfifo_token) + elif struct.hClass == nv_gpu.AMPERE_DMA_COPY_B or struct.hClass == nv_gpu.ADA_COMPUTE_A: + assert struct.hObjectParent in self.object_by_handle and isinstance(self.object_by_handle[struct.hObjectParent], NVGPFIFO) + struct.hObjectNew = self._alloc_handle() + elif struct.hClass == nv_gpu.GT200_DEBUGGER: + struct.hObjectNew = self._alloc_handle() + else: raise RuntimeError(f"Unknown {struct.hClass} to rm_alloc") + return 0 + + def rm_control(self, argp): + struct = nv_gpu.NVOS54_PARAMETERS.from_address(argp) + params_ptr = struct.params + if struct.cmd == nv_gpu.NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2: + params:Any = nv_gpu.NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS.from_address(params_ptr) + params.deviceInstance = params.gpuId # emulate them to be the same + elif struct.cmd == nv_gpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 or struct.cmd == nv_gpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST: + if struct.cmd == nv_gpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST: + params = nv_gpu.NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS.from_address(params_ptr) + else: + params = nv_gpu.NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS.from_address(params_ptr) + + classes = [50021, 51607, 51648, 50543, 51125, 51125, 51125, 51125, 50529, 36967, 36909, 37105, 33868, 36978, 37095, 37094, 36980, 37014, 49270, + 41068, 41088, 41280, 50025, 96, 112, 115, 125, 20608, 20640, 20539, 20540, 41089, 41092, 50034, 50810, 50811, 50814, 51056, 51057, + 51059, 51069, 51071, 51632, 51639, 51639, 51706, 52019, 222, 50287, 50273, 50031, 50017] # from ada102 + params.numClasses = len(classes) + if struct.cmd == nv_gpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST: + clslist = to_mv(params.classList, params.numClasses * 4).cast('I') + for i,c in enumerate(classes): clslist[i] = c + else: + for i,c in enumerate(classes): params.classList[i] = c + elif struct.cmd == nv_gpu.NV2080_CTRL_CMD_GR_GET_INFO: + info = {nv_gpu.NV2080_CTRL_GR_INFO_INDEX_SM_VERSION: nv_gpu.NV2080_CTRL_GR_INFO_SM_VERSION_3_5, + nv_gpu.NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS: 1, + nv_gpu.NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC: 1, + nv_gpu.NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC: 1, + nv_gpu.NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM: 1, + } + + params = nv_gpu.NV2080_CTRL_GR_GET_INFO_PARAMS.from_address(params_ptr) + reqlist = (nv_gpu.NV2080_CTRL_GR_INFO * params.grInfoListSize).from_address(params.grInfoList) + for i in range(params.grInfoListSize): reqlist[i].data = info[reqlist[i].index] + elif struct.cmd == nv_gpu.NV2080_CTRL_CMD_GPU_GET_GID_INFO: + assert struct.hObject in self.object_by_handle and isinstance(self.object_by_handle[struct.hObject], NVSubDevice) + gpu = self.object_by_handle[struct.hObject].device + params = nv_gpu.NV2080_CTRL_GPU_GET_GID_INFO_PARAMS.from_address(params_ptr) + if params.flags != nv_gpu.NV2080_GPU_CMD_GPU_GET_GID_FLAGS_FORMAT_BINARY: raise RuntimeError("Unknown format") + bts = gpu.gpu_uuid(sz=params.length) + for i in range(params.length): params.data[i] = bts[i] + elif struct.cmd == nv_gpu.NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN: + assert struct.hObject in self.object_by_handle and isinstance(self.object_by_handle[struct.hObject], NVGPFIFO) + params = nv_gpu.NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS.from_address(params_ptr) + gpu_fifo = self.object_by_handle[struct.hObject] + params.workSubmitToken = gpu_fifo.token + elif struct.cmd == nv_gpu.NVA06C_CTRL_CMD_GPFIFO_SCHEDULE: pass + elif struct.cmd == nv_gpu.NV2080_CTRL_CMD_PERF_BOOST: pass + elif struct.cmd == nv_gpu.NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE: pass + elif struct.cmd == nv_gpu.NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES: + params = nv_gpu.NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS.from_address(params_ptr) + params.mmuFault.valid = bool("MOCKGPU_EMU_FAULTADDR" in os.environ) + elif struct.cmd == nv_gpu.NV83DE_CTRL_CMD_DEBUG_READ_MMU_FAULT_INFO: + params = nv_gpu.struct_NV83DE_CTRL_DEBUG_READ_MMU_FAULT_INFO_PARAMS.from_address(params_ptr) + params.count = 1 + params.mmuFaultInfoList[0].faultAddress = int(os.environ['MOCKGPU_EMU_FAULTADDR'], base=16) + params.mmuFaultInfoList[0].faultType = 1 + params.mmuFaultInfoList[0].accessType = 1 + else: raise RuntimeError(f"Unknown {struct.cmd} to rm_control") + return 0 + + def ctl_ioctl(self, req, argp): + nr = req & 0xff + if nr == nv_gpu.NV_ESC_RM_ALLOC: return self.rm_alloc(argp) + elif nr == nv_gpu.NV_ESC_RM_ALLOC_MEMORY: pass + elif nr == nv_gpu.NV_ESC_RM_CONTROL: return self.rm_control(argp) + elif nr == nv_gpu.NV_ESC_RM_MAP_MEMORY: + st:Any = nv_gpu.nv_ioctl_nvos33_parameters_with_fd.from_address(argp) + obj = self.object_by_handle[st.params.hMemory] + if isinstance(obj, NVUserMode): + file = self.opened_fds[st.fd] + assert isinstance(file, NVDevFileDesc) + file._mapping_userland = True + elif nr == nv_gpu.NV_ESC_RM_FREE: + st = nv_gpu.NVOS00_PARAMETERS.from_address(argp) + self.object_by_handle.pop(st.hObjectOld) + elif nr == nv_gpu.NV_ESC_CARD_INFO: + for i,gpu in enumerate(self.gpus.values()): + st = nv_gpu.nv_ioctl_card_info_t.from_address(argp + i * ctypes.sizeof(nv_gpu.nv_ioctl_card_info_t)) + st.gpu_id = gpu.gpuid + st.pci_info.device_id = 0x2684 + st.valid = True + else: raise RuntimeError(f"Unknown {nr} to nvidiactl") + return 0 + def uvm_ioctl(self, nr, argp): + if nr == nv_gpu.UVM_INITIALIZE: pass + elif nr == nv_gpu.UVM_MM_INITIALIZE: pass + elif nr == nv_gpu.UVM_REGISTER_GPU: + st:Any = nv_gpu.UVM_REGISTER_GPU_PARAMS.from_address(argp) + assert any(all(st.gpu_uuid.uuid[i] == gpu.gpu_uuid()[i] for i in range(16)) for gpu in self.gpus.values()) + elif nr == nv_gpu.UVM_REGISTER_GPU_VASPACE: pass + elif nr == nv_gpu.UVM_ENABLE_PEER_ACCESS: pass # uvm and shared spaced are setup already, no emulation for now + elif nr == nv_gpu.UVM_CREATE_EXTERNAL_RANGE: + st = nv_gpu.UVM_CREATE_EXTERNAL_RANGE_PARAMS.from_address(argp) + libc.mmap(st.base, st.length, mmap.PROT_READ|mmap.PROT_WRITE, MAP_FIXED|mmap.MAP_SHARED|mmap.MAP_ANONYMOUS, -1, 0) + elif nr == nv_gpu.UVM_MAP_EXTERNAL_ALLOCATION: + st = nv_gpu.UVM_MAP_EXTERNAL_ALLOCATION_PARAMS.from_address(argp) + for gpu_attr_id in range(st.gpuAttributesCount): + gpu = None + for _gpu in self.gpus.values(): + if all(st.perGpuAttributes[gpu_attr_id].gpuUuid.uuid[i] == _gpu.gpu_uuid()[i] for i in range(16)): + gpu = _gpu + break + if gpu is None: return -1 + gpu.map_range(st.base, st.length) + elif nr == nv_gpu.UVM_REGISTER_CHANNEL: pass + elif nr == nv_gpu.UVM_FREE: + st = nv_gpu.UVM_FREE_PARAMS.from_address(argp) + libc.munmap(st.base, st.length) + else: raise RuntimeError(f"Unknown {nr} to nvidia-uvm") + return 0 + + def dev_ioctl(self, dev, req, argp): return 0 + def _gpu_mmio_write(self, mv, off, gpu): + any_progress = True + while any_progress: + any_progress = False + for gpu in self.gpus.values(): + for q in gpu.queues: + if q.ctrl.GPGet != q.ctrl.GPPut: + any_progress |= q.execute() \ No newline at end of file diff --git a/tinygrad_repo/test/mockgpu/nv/nvgpu.py b/tinygrad_repo/test/mockgpu/nv/nvgpu.py new file mode 100644 index 000000000..76239c152 --- /dev/null +++ b/tinygrad_repo/test/mockgpu/nv/nvgpu.py @@ -0,0 +1,194 @@ +import ctypes, ctypes.util, time +import tinygrad.runtime.autogen.nv_gpu as nv_gpu +from enum import Enum, auto +from test.mockgpu.gpu import VirtGPU +from tinygrad.helpers import to_mv, init_c_struct_t + +def make_qmd_struct_type(): + fields = [] + bits = [(name,dt) for name,dt in nv_gpu.__dict__.items() if name.startswith("NVC6C0_QMDV03_00") and isinstance(dt, tuple)] + bits += [(name+f"_{i}",dt(i)) for name,dt in nv_gpu.__dict__.items() for i in range(8) if name.startswith("NVC6C0_QMDV03_00") and callable(dt)] + bits = sorted(bits, key=lambda x: x[1][1]) + for i,(name, data) in enumerate(bits): + if i > 0 and (gap:=(data[1] - bits[i-1][1][0] - 1)) != 0: fields.append((f"_reserved{i}", ctypes.c_uint32, gap)) + fields.append((name.replace("NVC6C0_QMDV03_00_", "").lower(), ctypes.c_uint32, data[0]-data[1]+1)) + return init_c_struct_t(tuple(fields)) +qmd_struct_t = make_qmd_struct_type() +assert ctypes.sizeof(qmd_struct_t) == 0x40 * 4 + +try: + gpuocelot_lib = ctypes.CDLL(ctypes.util.find_library("gpuocelot")) + gpuocelot_lib.ptx_run.argtypes = [ctypes.c_char_p, ctypes.c_int, ctypes.POINTER(ctypes.c_void_p), ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int, ctypes.c_int] # noqa: E501 +except Exception: pass + +class SchedResult(Enum): CONT = auto(); YIELD = auto() # noqa: E702 + +class GPFIFO: + def __init__(self, token, base, entries_cnt): + self.token, self.base, self.entries_cnt = token, base, entries_cnt + self.gpfifo = to_mv(self.base, self.entries_cnt * 8).cast("Q") + self.ctrl = nv_gpu.AmpereAControlGPFifo.from_address(self.base + self.entries_cnt * 8) + self.state = {} + + # Buf exec state + self.buf = None + self.buf_sz = 0 + self.buf_ptr = 0 + + def _next_dword(self): + assert self.buf is not None + x = self.buf[self.buf_ptr] + self.buf_ptr += 1 + return x + + def _next_header(self): + header = self._next_dword() + typ = (header >> 28) & 0b111 + size = (header >> 16) & 0xFFF + subc = (header >> 13) & 0x7 + mthd = (header & 0x1FFF) << 2 + return typ, size, subc, mthd + + def _state(self, reg): return self.state[reg] + def _state64(self, reg): return (self.state[reg] << 32) + self.state[reg + 4] + def _state64_le(self, reg): return (self.state[reg + 4] << 32) + self.state[reg] + + def _reset_buf_state(self): self.buf, self.buf_ptr = None, 0 + def _set_buf_state(self, gpfifo_entry): + ptr = ((gpfifo_entry >> 2) & 0x3fffffffff) << 2 + sz = ((gpfifo_entry >> 42) & 0x1fffff) << 2 + self.buf = to_mv(ptr, sz).cast("I") + self.buf_sz = sz // 4 + + def execute(self) -> bool: + initial_off = self.buf_ptr + while self.ctrl.GPGet != self.ctrl.GPPut: + self._set_buf_state(self.gpfifo[self.ctrl.GPGet]) + + if not self.execute_buf(): + # Buffer isn't executed fully, check if any progress and report. + # Do not move GPGet in this case, will continue from the same state next time. + return self.buf_ptr != initial_off + + self.ctrl.GPGet = (self.ctrl.GPGet + 1) % self.entries_cnt + self._reset_buf_state() + return True + + def execute_buf(self) -> bool: + while self.buf_ptr < self.buf_sz: + init_off = self.buf_ptr + _, size, _, mthd = self._next_header() + cmd_end_off = self.buf_ptr + size + + while self.buf_ptr < cmd_end_off: + res = self.execute_cmd(mthd) + if res == SchedResult.YIELD: + self.buf_ptr = init_off # just revert to the header + return False + mthd += 4 + return True + + def execute_qmd(self, qmd_addr): + qmd = qmd_struct_t.from_address(qmd_addr) + prg_addr = qmd.program_address_lower + (qmd.program_address_upper << 32) + const0 = to_mv(qmd.constant_buffer_addr_lower_0 + (qmd.constant_buffer_addr_upper_0 << 32), 0x160).cast('I') + args_cnt, vals_cnt = const0[80], const0[81] + args_addr = qmd.constant_buffer_addr_lower_0 + (qmd.constant_buffer_addr_upper_0 << 32) + 0x160 + args = to_mv(args_addr, args_cnt*8).cast('Q') + vals = to_mv(args_addr + args_cnt*8, vals_cnt*4).cast('I') + cargs = [ctypes.cast(args[i], ctypes.c_void_p) for i in range(args_cnt)] + [ctypes.cast(vals[i], ctypes.c_void_p) for i in range(vals_cnt)] + gx, gy, gz = qmd.cta_raster_width, qmd.cta_raster_height, qmd.cta_raster_depth + lx, ly, lz = qmd.cta_thread_dimension0, qmd.cta_thread_dimension1, qmd.cta_thread_dimension2 + gpuocelot_lib.ptx_run(ctypes.cast(prg_addr, ctypes.c_char_p), args_cnt+vals_cnt, (ctypes.c_void_p*len(cargs))(*cargs), lx, ly, lz, gx, gy, gz, 0) + if qmd.release0_enable: + rel0 = to_mv(qmd.release0_address_lower + (qmd.release0_address_upper << 32), 0x10).cast('Q') + rel0[0] = qmd.release0_payload_lower + (qmd.release0_payload_upper << 32) + rel0[1] = int(time.perf_counter() * 1e9) + if qmd.release1_enable: + rel1 = to_mv(qmd.release1_address_lower + (qmd.release1_address_upper << 32), 0x10).cast('Q') + rel1[0] = qmd.release1_payload_lower + (qmd.release1_payload_upper << 32) + rel1[1] = int(time.perf_counter() * 1e9) + if qmd.dependent_qmd0_enable: + if qmd.dependent_qmd0_action == 1: self.execute_qmd(qmd.dependent_qmd0_pointer << 8) + else: raise RuntimeError("unsupported dependent qmd action") + + def execute_cmd(self, cmd) -> SchedResult: + if cmd == nv_gpu.NVC56F_SEM_EXECUTE: return self._exec_signal() + elif cmd == nv_gpu.NVC6C0_LAUNCH_DMA: return self._exec_nvc6c0_dma() + elif cmd == nv_gpu.NVC6B5_LAUNCH_DMA: return self._exec_nvc6b5_dma() + elif cmd == nv_gpu.NVC6C0_SEND_SIGNALING_PCAS2_B: return self._exec_pcas2() + elif cmd == 0x0320: return self._exec_load_inline_qmd() # NVC6C0_LOAD_INLINE_QMD_DATA + else: self.state[cmd] = self._next_dword() # just state update + return SchedResult.CONT + + def _exec_signal(self) -> SchedResult: + signal = self._state64_le(nv_gpu.NVC56F_SEM_ADDR_LO) + val = self._state64_le(nv_gpu.NVC56F_SEM_PAYLOAD_LO) + flags = self._next_dword() + typ = (flags >> 0) & 0b111 + timestamp = (flags & (1 << 25)) == (1 << 25) + if typ == 1: + to_mv(signal, 8).cast('Q')[0] = val + if timestamp: to_mv(signal + 8, 8).cast('Q')[0] = int(time.perf_counter() * 1e9) + elif typ == 3: + mval = to_mv(signal, 8).cast('Q')[0] + return SchedResult.CONT if mval >= val else SchedResult.YIELD + else: raise RuntimeError(f"Unsupported type={typ} in exec wait/signal") + return SchedResult.CONT + + def _exec_load_inline_qmd(self): + qmd_addr = self._state64(nv_gpu.NVC6C0_SET_INLINE_QMD_ADDRESS_A) << 8 + assert qmd_addr != 0x0, f"invalid qmd address {qmd_addr}" + qmd_data = [self._next_dword() for _ in range(0x40)] + cdata = (ctypes.c_uint32 * len(qmd_data))(*qmd_data) + ctypes.memmove(qmd_addr, cdata, 0x40 * 4) + self.execute_qmd(qmd_addr) + + def _exec_nvc6c0_dma(self): + addr = self._state64(nv_gpu.NVC6C0_OFFSET_OUT_UPPER) + sz = self._state(nv_gpu.NVC6C0_LINE_LENGTH_IN) + lanes = self._state(nv_gpu.NVC6C0_LINE_COUNT) + assert lanes == 1, f"unsupported lanes > 1 in _exec_nvc6c0_dma: {lanes}" + flags = self._next_dword() + assert flags == 0x41, f"unsupported flags in _exec_nvc6c0_dma: {flags}" + typ, dsize, _, mthd = self._next_header() + assert typ == 6 and mthd == nv_gpu.NVC6C0_LOAD_INLINE_DATA, f"Expected inline data not found after nvc6c0_dma, {typ=} {mthd=}" + copy_data = [self._next_dword() for _ in range(dsize)] + assert len(copy_data) * 4 == sz, f"different copy sizes in _exec_nvc6c0_dma: {len(copy_data) * 4} != {sz}" + cdata = (ctypes.c_uint32 * len(copy_data))(*copy_data) + ctypes.memmove(addr, cdata, sz) + + def _exec_nvc6b5_dma(self): + flags = self._next_dword() + if (flags & 0b11) != 0: + src = self._state64(nv_gpu.NVC6B5_OFFSET_IN_UPPER) + dst = self._state64(nv_gpu.NVC6B5_OFFSET_OUT_UPPER) + sz = self._state(nv_gpu.NVC6B5_LINE_LENGTH_IN) + assert flags == 0x182, f"unsupported flags in _exec_nvc6b5_dma: {flags}" + ctypes.memmove(dst, src, sz) + elif ((flags >> 3) & 0b11) != 0: + src = to_mv(self._state64(nv_gpu.NVC6B5_SET_SEMAPHORE_A), 0x10).cast('Q') + val = self._state(nv_gpu.NVC6B5_SET_SEMAPHORE_PAYLOAD) + src[0] = val + src[1] = int(time.perf_counter() * 1e9) + else: raise RuntimeError("unknown nvc6b5_dma flags") + + def _exec_pcas2(self): + qmd_addr = self._state(nv_gpu.NVC6C0_SEND_PCAS_A) << 8 + typ = self._next_dword() + if typ == 2 or typ == 9: # schedule + self.execute_qmd(qmd_addr) + +class NVGPU(VirtGPU): + def __init__(self, gpuid): + super().__init__(gpuid) + self.regs = {} + self.mapped_ranges = set() + self.queues = [] + + def map_range(self, vaddr, size): self.mapped_ranges.add((vaddr, size)) + def unmap_range(self, vaddr, size): self.mapped_ranges.remove((vaddr, size)) + def add_gpfifo(self, base, entries_count): + self.queues.append(GPFIFO(token:=len(self.queues), base, entries_count)) + return token + def gpu_uuid(self, sz=16): return self.gpuid.to_bytes(sz, byteorder='big', signed=False) diff --git a/tinygrad_repo/test/mockgpu/usb.py b/tinygrad_repo/test/mockgpu/usb.py new file mode 100644 index 000000000..460b46100 --- /dev/null +++ b/tinygrad_repo/test/mockgpu/usb.py @@ -0,0 +1,16 @@ +class MockUSB: + def __init__(self, mem): + self.mem = mem + + def read(self, address, size): + return bytes(self.mem[address:address+size]) + + def write(self, address, data, ignore_cache=False): + self.mem[address:address+len(data)] = data + + def pcie_mem_req(self, address, value=None, size=1): + if value is None: return int.from_bytes(self.mem[address:address+size], "little") + else: self.mem[address:address+size] = value.to_bytes(size, "little") + + def pcie_mem_write(self, address, values, size): + for i, value in enumerate(values): self.pcie_mem_req(address + i * size, value, size) diff --git a/tinygrad_repo/test/models/__init__.py b/tinygrad_repo/test/models/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/tinygrad_repo/test/models/efficientnet/Chicken.jpg b/tinygrad_repo/test/models/efficientnet/Chicken.jpg new file mode 100644 index 0000000000000000000000000000000000000000..9dd4815dbaca705f6fab98300246667f1da0324e GIT binary patch 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/dev/null +++ b/tinygrad_repo/test/models/test_bert.py @@ -0,0 +1,56 @@ +#!/usr/bin/env python +import unittest +import numpy as np +from tinygrad.tensor import Tensor +import torch + +def get_question_samp(bsz, seq_len, vocab_size, seed): + np.random.seed(seed) + in_ids= np.random.randint(vocab_size, size=(bsz, seq_len)) + mask = np.random.choice([True, False], size=(bsz, seq_len)) + seg_ids = np.random.randint(1, size=(bsz, seq_len)) + return in_ids, mask, seg_ids + +def set_equal_weights(mdl, torch_mdl): + from tinygrad.nn.state import get_state_dict + state, torch_state = get_state_dict(mdl), torch_mdl.state_dict() + assert len(state) == len(torch_state) + for k, v in state.items(): + assert k in torch_state + torch_state[k].copy_(torch.from_numpy(v.numpy())) + torch_mdl.eval() + +class TestBert(unittest.TestCase): + def test_questions(self): + from extra.models.bert import BertForQuestionAnswering + from transformers import BertForQuestionAnswering as TorchBertForQuestionAnswering + from transformers import BertConfig + + # small + config = { + 'vocab_size':24, 'hidden_size':2, 'num_hidden_layers':2, 'num_attention_heads':2, + 'intermediate_size':32, 'hidden_dropout_prob':0.1, 'attention_probs_dropout_prob':0.1, + 'max_position_embeddings':512, 'type_vocab_size':2 + } + + # Create in tinygrad + Tensor.manual_seed(1337) + mdl = BertForQuestionAnswering(**config) + + # Create in torch + with torch.no_grad(): + torch_mdl = TorchBertForQuestionAnswering(BertConfig(**config)) + + set_equal_weights(mdl, torch_mdl) + + seeds = (1337, 3141) + bsz, seq_len = 1, 16 + for _, seed in enumerate(seeds): + in_ids, mask, seg_ids = get_question_samp(bsz, seq_len, config['vocab_size'], seed) + out = mdl(Tensor(in_ids), Tensor(mask), Tensor(seg_ids)) + torch_out = torch_mdl.forward(torch.from_numpy(in_ids).long(), torch.from_numpy(mask), torch.from_numpy(seg_ids).long())[:2] + torch_out = torch.cat(torch_out).unsqueeze(2) + np.testing.assert_allclose(out.numpy(), torch_out.detach().numpy(), atol=5e-4, rtol=5e-4) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/models/test_efficientnet.py b/tinygrad_repo/test/models/test_efficientnet.py new file mode 100644 index 000000000..289219651 --- /dev/null +++ b/tinygrad_repo/test/models/test_efficientnet.py @@ -0,0 +1,116 @@ +import ast +import pathlib +import unittest + +import numpy as np +from PIL import Image + +from tinygrad.helpers import getenv +from tinygrad.tensor import Tensor +from extra.models.efficientnet import EfficientNet +from extra.models.vit import ViT +from extra.models.resnet import ResNet50 + +def _load_labels(): + labels_filename = pathlib.Path(__file__).parent / 'efficientnet/imagenet1000_clsidx_to_labels.txt' + return ast.literal_eval(labels_filename.read_text()) + +_LABELS = _load_labels() + +def preprocess(img, new=False): + # preprocess image + aspect_ratio = img.size[0] / img.size[1] + img = img.resize((int(224*max(aspect_ratio,1.0)), int(224*max(1.0/aspect_ratio,1.0)))) + + img = np.array(img) + y0, x0 =(np.asarray(img.shape)[:2] - 224) // 2 + img = img[y0: y0 + 224, x0: x0 + 224] + + # low level preprocess + if new: + img = img.astype(np.float32) + img -= [127.0, 127.0, 127.0] + img /= [128.0, 128.0, 128.0] + img = img[None] + else: + img = np.moveaxis(img, [2, 0, 1], [0, 1, 2]) + img = img.astype(np.float32)[:3].reshape(1, 3, 224, 224) + img /= 255.0 + img -= np.array([0.485, 0.456, 0.406]).reshape((1, -1, 1, 1)) + img /= np.array([0.229, 0.224, 0.225]).reshape((1, -1, 1, 1)) + return img + + +def _infer(model: EfficientNet, img, bs=1): + old_training = Tensor.training + Tensor.training = False + img = preprocess(img) + # run the net + if bs > 1: img = img.repeat(bs, axis=0) + out = model.forward(Tensor(img)) + Tensor.training = old_training + return _LABELS[np.argmax(out.numpy()[0])] + +chicken_img = Image.open(pathlib.Path(__file__).parent / 'efficientnet/Chicken.jpg') +car_img = Image.open(pathlib.Path(__file__).parent / 'efficientnet/car.jpg') + +class TestEfficientNet(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.model = EfficientNet(number=getenv("NUM")) + cls.model.load_from_pretrained() + + @classmethod + def tearDownClass(cls): + del cls.model + + def test_chicken(self): + label = _infer(self.model, chicken_img) + self.assertEqual(label, "hen") + + def test_chicken_bigbatch(self): + label = _infer(self.model, chicken_img, 2) + self.assertEqual(label, "hen") + + def test_car(self): + label = _infer(self.model, car_img) + self.assertEqual(label, "sports car, sport car") + +class TestViT(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.model = ViT() + cls.model.load_from_pretrained() + + @classmethod + def tearDownClass(cls): + del cls.model + + def test_chicken(self): + label = _infer(self.model, chicken_img) + self.assertEqual(label, "cock") + + def test_car(self): + label = _infer(self.model, car_img) + self.assertEqual(label, "racer, race car, racing car") + +class TestResNet(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.model = ResNet50() + cls.model.load_from_pretrained() + + @classmethod + def tearDownClass(cls): + del cls.model + + def test_chicken(self): + label = _infer(self.model, chicken_img) + self.assertEqual(label, "hen") + + def test_car(self): + label = _infer(self.model, car_img) + self.assertEqual(label, "sports car, sport car") + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/models/test_end2end.py b/tinygrad_repo/test/models/test_end2end.py new file mode 100644 index 000000000..82dc8cc7a --- /dev/null +++ b/tinygrad_repo/test/models/test_end2end.py @@ -0,0 +1,164 @@ +import torch +from torch import nn +import unittest +import numpy as np +from tinygrad.nn.state import get_parameters, get_state_dict +from tinygrad.nn import optim, Linear, Conv2d, BatchNorm2d +from tinygrad.tensor import Tensor +from extra.datasets import fetch_mnist +from tinygrad.helpers import CI + +def compare_tiny_torch(model, model_torch, X, Y): + with Tensor.train(): + model_torch.train() + model_state_dict = get_state_dict(model) + for k,v in model_torch.named_parameters(): + if not CI: print(f"initting {k} from torch") + model_state_dict[k].assign(Tensor(v.detach().numpy())).realize() + + optimizer = optim.SGD(get_parameters(model), lr=0.001) + optimizer_torch = torch.optim.SGD(model_torch.parameters(), lr=0.001) + + Xt = torch.Tensor(X.numpy()) + np.testing.assert_allclose(X.numpy(), Xt.detach().numpy()) + + out = model(X) + loss = (out * Y).mean() + + out_torch = model_torch(torch.Tensor(X.numpy())) + loss_torch = (out_torch * torch.Tensor(Y.numpy())).mean() + + # zero and backward + optimizer.zero_grad() + loss.backward() + optimizer_torch.zero_grad() + loss_torch.backward() + + # assert losses match + if not CI: print(loss.realize().numpy()) + if not CI: print(loss_torch.detach().numpy()) + np.testing.assert_allclose(loss.realize().numpy(), loss_torch.detach().numpy(), atol=1e-4) + + for k,v in list(model_torch.named_parameters())[::-1]: + g = model_state_dict[k].grad.numpy() + gt = v.grad.detach().numpy() + if not CI: print("testing grads", k, model_state_dict[k].grad.dtype) + np.testing.assert_allclose(g, gt, atol=1e-3, err_msg=f'grad mismatch {k}') + + # take the steps + optimizer.step() + optimizer_torch.step() + + # assert weights match + for k,v in model_torch.named_parameters(): + if not CI: print("testing weight", k, model_state_dict[k].dtype) + np.testing.assert_allclose(model_state_dict[k].numpy(), v.detach().numpy(), atol=1e-3, err_msg=f'weight mismatch {k}') + +def get_mnist_data(): + _X_train, _Y_train, X_test, Y_test = fetch_mnist() + BS = 32 + num_classes = 10 + X = Tensor(X_test[0:BS].astype(np.float32)) + Y = np.zeros((BS, num_classes), np.float32) + Y[range(BS),Y_test[0:BS]] = -1.0*num_classes + return X, Tensor(Y) + +class TestEnd2End(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.X, cls.Y = get_mnist_data() + + def setUp(self): + torch.manual_seed(123) + + def test_linear_mnist(self): + class LinTiny: + def __init__(self, bias=False): + self.l1 = Linear(784, 128, bias=bias) + self.l2 = Linear(128, 10, bias=bias) + def __call__(self, x): + return self.l2(self.l1(x).relu()).log_softmax(-1) + class LinTorch(nn.Module): + def __init__(self, bias=False): + super().__init__() + self.l1 = nn.Linear(784, 128, bias=bias) + self.l2 = nn.Linear(128, 10, bias=bias) + def forward(self, x): + return self.l2(self.l1(x).relu()).log_softmax(-1) + compare_tiny_torch(LinTiny(), LinTorch(), self.X, self.Y) + + def test_bn_mnist(self): + class LinTiny: + def __init__(self): + self.l1 = Linear(784, 128) + self.l2 = Linear(128, 10) + self.bn1 = BatchNorm2d(128) + def __call__(self, x): + return self.l2(self.bn1(self.l1(x).reshape(x.shape[0], -1, 1, 1)).reshape(x.shape[0], -1).relu()).log_softmax(-1) + class LinTorch(nn.Module): + def __init__(self): + super().__init__() + self.l1 = nn.Linear(784, 128) + self.l2 = nn.Linear(128, 10) + self.bn1 = nn.BatchNorm2d(128) + def forward(self, x): + return self.l2(self.bn1(self.l1(x).reshape(x.shape[0], -1, 1, 1)).reshape(x.shape[0], -1).relu()).log_softmax(-1) + compare_tiny_torch(LinTiny(), LinTorch(), self.X, self.Y) + + def test_bn_alone(self): + np.random.seed(1337) + X = Tensor(np.random.randn(32, 10, 1, 1).astype(np.float32)) + Y = Tensor(np.random.randn(32, 10, 1, 1).astype(np.float32)) + compare_tiny_torch(BatchNorm2d(10), nn.BatchNorm2d(10), X, Y) + + def test_bn_linear(self): + BS, K = 2, 1 + eps = 0 + X = Tensor([1,0]).reshape(BS, K, 1, 1) + Y = Tensor([-1,0]).reshape(BS, K, 1, 1) + class LinTiny: + def __init__(self): + self.l1 = Conv2d(K, K, 1, bias=False) + self.bn1 = BatchNorm2d(K, affine=False, track_running_stats=False, eps=eps) + def __call__(self, x): return self.bn1(self.l1(x)) + class LinTorch(nn.Module): + def __init__(self): + super().__init__() + self.l1 = nn.Conv2d(K, K, 1, bias=False) + self.bn1 = nn.BatchNorm2d(K, affine=False, track_running_stats=False, eps=eps) + def forward(self, x): return self.bn1(self.l1(x)) + model_torch = LinTorch() + with torch.no_grad(): + model_torch.l1.weight[:] = 1. + compare_tiny_torch(LinTiny(), model_torch, X, Y) + + def test_conv_mnist(self): + class LinTiny: + def __init__(self, has_batchnorm=False): + self.c1 = Conv2d(1, 8, 3, stride=2) + self.c2 = Conv2d(8, 16, 3, stride=2) + self.l1 = Linear(16*6*6, 10) + if has_batchnorm: + self.bn1, self.bn2 = BatchNorm2d(8), BatchNorm2d(16) + else: + self.bn1, self.bn2 = lambda x: x, lambda x: x + def __call__(self, x): + return self.l1(self.bn2(self.c2(self.bn1(self.c1(x)).relu())).relu().reshape(x.shape[0], -1)).log_softmax(-1) + class LinTorch(nn.Module): + def __init__(self, has_batchnorm=False): + super().__init__() + self.c1 = nn.Conv2d(1, 8, 3, stride=2) + self.c2 = nn.Conv2d(8, 16, 3, stride=2) + self.l1 = nn.Linear(16*6*6, 10) + if has_batchnorm: + self.bn1, self.bn2 = nn.BatchNorm2d(8), nn.BatchNorm2d(16) + else: + self.bn1, self.bn2 = lambda x: x, lambda x: x + def forward(self, x): + return self.l1(self.bn2(self.c2(self.bn1(self.c1(x)).relu())).relu().reshape(x.shape[0], -1)).log_softmax(-1) + for has_batchnorm in [False, True]: + with self.subTest(has_batchnorm=has_batchnorm): + compare_tiny_torch(LinTiny(has_batchnorm), LinTorch(has_batchnorm), self.X.reshape((-1, 1, 28, 28)), self.Y) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/models/test_mnist.py b/tinygrad_repo/test/models/test_mnist.py new file mode 100644 index 000000000..2f5e93986 --- /dev/null +++ b/tinygrad_repo/test/models/test_mnist.py @@ -0,0 +1,115 @@ +#!/usr/bin/env python +import unittest +import numpy as np +from tinygrad import Tensor, Device +from tinygrad.helpers import CI +from tinygrad.nn.state import get_parameters +from tinygrad.nn import optim, BatchNorm2d +from extra.training import train, evaluate +from extra.datasets import fetch_mnist + +# load the mnist dataset +X_train, Y_train, X_test, Y_test = fetch_mnist() + +# create a model +class TinyBobNet: + def __init__(self): + self.l1 = Tensor.scaled_uniform(784, 128) + self.l2 = Tensor.scaled_uniform(128, 10) + + def parameters(self): + return get_parameters(self) + + def forward(self, x): + return x.dot(self.l1).relu().dot(self.l2) + +# create a model with a conv layer +class TinyConvNet: + def __init__(self, has_batchnorm=False): + # https://keras.io/examples/vision/mnist_convnet/ + conv = 3 + #inter_chan, out_chan = 32, 64 + inter_chan, out_chan = 8, 16 # for speed + self.c1 = Tensor.scaled_uniform(inter_chan,1,conv,conv) + self.c2 = Tensor.scaled_uniform(out_chan,inter_chan,conv,conv) + self.l1 = Tensor.scaled_uniform(out_chan*5*5, 10) + if has_batchnorm: + self.bn1 = BatchNorm2d(inter_chan) + self.bn2 = BatchNorm2d(out_chan) + else: + self.bn1, self.bn2 = lambda x: x, lambda x: x + + def parameters(self): + return get_parameters(self) + + def forward(self, x:Tensor): + x = x.reshape(shape=(-1, 1, 28, 28)) # hacks + x = self.bn1(x.conv2d(self.c1)).relu().max_pool2d() + x = self.bn2(x.conv2d(self.c2)).relu().max_pool2d() + x = x.reshape(shape=[x.shape[0], -1]) + return x.dot(self.l1) + +@unittest.skipIf(CI and Device.DEFAULT == "CPU", "slow") +class TestMNIST(unittest.TestCase): + def test_sgd_onestep(self): + np.random.seed(1337) + model = TinyBobNet() + optimizer = optim.SGD(model.parameters(), lr=0.001) + train(model, X_train, Y_train, optimizer, BS=69, steps=1) + for p in model.parameters(): p.realize() + + def test_sgd_threestep(self): + np.random.seed(1337) + model = TinyBobNet() + optimizer = optim.SGD(model.parameters(), lr=0.001) + train(model, X_train, Y_train, optimizer, BS=69, steps=3) + + def test_sgd_sixstep(self): + np.random.seed(1337) + model = TinyBobNet() + optimizer = optim.SGD(model.parameters(), lr=0.001) + train(model, X_train, Y_train, optimizer, BS=69, steps=6, noloss=True) + + def test_adam_onestep(self): + np.random.seed(1337) + model = TinyBobNet() + optimizer = optim.Adam(model.parameters(), lr=0.001) + train(model, X_train, Y_train, optimizer, BS=69, steps=1) + for p in model.parameters(): p.realize() + + def test_adam_threestep(self): + np.random.seed(1337) + model = TinyBobNet() + optimizer = optim.Adam(model.parameters(), lr=0.001) + train(model, X_train, Y_train, optimizer, BS=69, steps=3) + + def test_conv_onestep(self): + np.random.seed(1337) + model = TinyConvNet() + optimizer = optim.SGD(model.parameters(), lr=0.001) + train(model, X_train, Y_train, optimizer, BS=69, steps=1, noloss=True) + for p in model.parameters(): p.realize() + + def test_conv(self): + np.random.seed(1337) + model = TinyConvNet() + optimizer = optim.Adam(model.parameters(), lr=0.001) + train(model, X_train, Y_train, optimizer, steps=100) + assert evaluate(model, X_test, Y_test) > 0.93 # torch gets 0.9415 sometimes + + def test_conv_with_bn(self): + np.random.seed(1337) + model = TinyConvNet(has_batchnorm=True) + optimizer = optim.AdamW(model.parameters(), lr=0.003) + train(model, X_train, Y_train, optimizer, steps=200) + assert evaluate(model, X_test, Y_test) > 0.94 + + def test_sgd(self): + np.random.seed(1337) + model = TinyBobNet() + optimizer = optim.SGD(model.parameters(), lr=0.001) + train(model, X_train, Y_train, optimizer, steps=600) + assert evaluate(model, X_test, Y_test) > 0.94 # CPU gets 0.9494 sometimes + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/models/test_onnx.py b/tinygrad_repo/test/models/test_onnx.py new file mode 100644 index 000000000..da62c49ff --- /dev/null +++ b/tinygrad_repo/test/models/test_onnx.py @@ -0,0 +1,142 @@ +#!/usr/bin/env python +import os +import time +import unittest +import numpy as np +try: + import onnx +except ModuleNotFoundError: + raise unittest.SkipTest("onnx not installed, skipping onnx test") +from tinygrad.frontend.onnx import OnnxRunner, onnx_load +from tinygrad.tensor import Tensor +from tinygrad.helpers import CI, fetch, temp + +def run_onnx_torch(onnx_model, inputs): + import torch + from onnx2torch import convert + torch_model = convert(onnx_model).float() + with torch.no_grad(): + torch_out = torch_model(*[torch.tensor(x) for x in inputs.values()]) + return torch_out + +OPENPILOT_MODEL = "https://github.com/commaai/openpilot/raw/v0.9.4/selfdrive/modeld/models/supercombo.onnx" + +np.random.seed(1337) + +class TestOnnxModel(unittest.TestCase): + def test_benchmark_openpilot_model(self): + onnx_model = onnx_load(fetch(OPENPILOT_MODEL)) + run_onnx = OnnxRunner(onnx_model) + def get_inputs(): + np_inputs = { + "input_imgs": np.random.randn(*(1, 12, 128, 256)), + "big_input_imgs": np.random.randn(*(1, 12, 128, 256)), + "desire": np.zeros((1, 100, 8)), + "traffic_convention": np.array([[1., 0.]]), + "nav_features": np.zeros((1, 256)), + "features_buffer": np.zeros((1, 99, 128)), + } + inputs = {k:Tensor(v.astype(np.float32), requires_grad=False) for k,v in np_inputs.items()} + return inputs + + for _ in range(7): + inputs = get_inputs() + st = time.monotonic() + tinygrad_out = run_onnx(inputs)['outputs'] + mt = time.monotonic() + tinygrad_out.realize() + mt2 = time.monotonic() + tinygrad_out = tinygrad_out.numpy() + et = time.monotonic() + if not CI: + print(f"ran openpilot model in {(et-st)*1000.0:.2f} ms, waited {(mt2-mt)*1000.0:.2f} ms for realize, {(et-mt2)*1000.0:.2f} ms for GPU queue") + + if not CI: + import cProfile + import pstats + inputs = get_inputs() + pr = cProfile.Profile(timer=time.perf_counter_ns, timeunit=1e-6) + pr.enable() + tinygrad_out = run_onnx(inputs)['outputs'] + tinygrad_out.realize() + tinygrad_out = tinygrad_out.numpy() + if not CI: + pr.disable() + stats = pstats.Stats(pr) + stats.dump_stats(temp("net.prof")) + os.system(f"flameprof {temp('net.prof')} > {temp('prof.svg')}") + ps = stats.sort_stats(pstats.SortKey.TIME) + ps.print_stats(30) + + def test_openpilot_model(self): + onnx_model = onnx_load(fetch(OPENPILOT_MODEL)) + run_onnx = OnnxRunner(onnx_model) + print("got run_onnx") + inputs = { + "input_imgs": np.random.randn(*(1, 12, 128, 256)), + "big_input_imgs": np.random.randn(*(1, 12, 128, 256)), + "desire": np.zeros((1, 100, 8)), + "traffic_convention": np.array([[1., 0.]]), + "nav_features": np.zeros((1, 256)), + "features_buffer": np.zeros((1, 99, 128)), + } + inputs = {k:v.astype(np.float32) for k,v in inputs.items()} + + st = time.monotonic() + print("****** run onnx ******") + tinygrad_out = run_onnx(inputs)['outputs'] + mt = time.monotonic() + print("****** realize ******") + tinygrad_out.realize() + mt2 = time.monotonic() + tinygrad_out = tinygrad_out.numpy() + et = time.monotonic() + print(f"ran openpilot model in {(et-st)*1000.0:.2f} ms, waited {(mt2-mt)*1000.0:.2f} ms for realize, {(et-mt2)*1000.0:.2f} ms for GPU queue") + + onnx_model = onnx.load(fetch(OPENPILOT_MODEL)) + torch_out = run_onnx_torch(onnx_model, inputs).numpy() + print(tinygrad_out, torch_out) + np.testing.assert_allclose(tinygrad_out, torch_out, atol=1e-4, rtol=1e-2) + + @unittest.skip("slow") + def test_efficientnet(self): + input_name, input_new = "images:0", True + self._test_model( + fetch("https://github.com/onnx/models/raw/main/validated/vision/classification/efficientnet-lite4/model/efficientnet-lite4-11.onnx"), + input_name, input_new) + + @unittest.skip("TODO: FIX THIS IT CAUSES SEGFAULT") + def test_shufflenet(self): + input_name, input_new = "gpu_0/data_0", False + self._test_model( + fetch("https://github.com/onnx/models/raw/main/validated/vision/classification/shufflenet/model/shufflenet-9.onnx"), + input_name, input_new) + + @unittest.skip("test is very slow") + def test_resnet(self): + # NOTE: many onnx models can't be run right now due to max pool with strides != kernel_size + input_name, input_new = "data", False + self._test_model( + fetch("https://github.com/onnx/models/raw/main/validated/vision/classification/resnet/model/resnet18-v2-7.onnx"), + input_name, input_new) + + def _test_model(self, fn, input_name, input_new, debug=False): + onnx_model = onnx_load(fn) + print("onnx loaded") + from test.models.test_efficientnet import chicken_img, car_img, preprocess, _LABELS + run_onnx = OnnxRunner(onnx_model) + + def run(img): + inputs = {input_name: preprocess(img, new=input_new)} + tinygrad_out = list(run_onnx(inputs, debug=debug).values())[0].numpy() + return tinygrad_out.argmax() + + cls = run(chicken_img) + print(cls, _LABELS[cls]) + assert _LABELS[cls] == "hen" or _LABELS[cls] == "cock" + cls = run(car_img) + print(cls, _LABELS[cls]) + assert "car" in _LABELS[cls] or _LABELS[cls] == "convertible" + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/models/test_real_world.py b/tinygrad_repo/test/models/test_real_world.py new file mode 100644 index 000000000..66f416633 --- /dev/null +++ b/tinygrad_repo/test/models/test_real_world.py @@ -0,0 +1,175 @@ +import unittest, time, gc +import numpy as np +from tinygrad.device import is_dtype_supported +from tinygrad.nn import optim +from tinygrad.nn.state import get_parameters +from tinygrad.engine.jit import TinyJit +from tinygrad import Tensor, Device, GlobalCounters, dtypes, Variable +from tinygrad.helpers import CI, Context +from extra.lr_scheduler import OneCycleLR +from test.helpers import derandomize_model + +from examples.gpt2 import Transformer as GPT2Transformer, MODEL_PARAMS as GPT2_MODEL_PARAMS +from examples.hlb_cifar10 import SpeedyResNet, hyp +from examples.llama import Transformer as LLaMaTransformer +from examples.stable_diffusion import UNetModel, unet_params +from extra.models.unet import ResBlock +from extra.models.bert import BertForPretraining + +global_mem_used = 0 +def helper_test(nm, gen, model, max_memory_allowed, max_kernels_allowed, all_jitted=False): + with Context(JIT=2): + tms = [] + for _ in range(4): + early_gen = [x.realize() if isinstance(x, Tensor) else x for x in gen()] + GlobalCounters.reset() + Device[Device.DEFAULT].synchronize() + st = time.perf_counter_ns() + model(*early_gen) + Device[Device.DEFAULT].synchronize() + tms.append(time.perf_counter_ns() - st) + mem_used = GlobalCounters.mem_used - global_mem_used + + # TODO: jit should expose this correctly with graph + kernels_used = len(model.jit_cache) if hasattr(model, "jit_cache") else None + print(f"{nm}: used {mem_used/1e9:.2f} GB and {kernels_used} kernels in {min(tms)/1e6:.2f} ms") + assert mem_used/1e9 < max_memory_allowed, f"{nm} used more than {max_memory_allowed:.2f} GB - {mem_used/1e9:.2} GB used" + assert not kernels_used or kernels_used <= max_kernels_allowed, f"{nm} used more than {max_kernels_allowed} kernels, it used {kernels_used}" + if all_jitted: + assert kernels_used > 0 and kernels_used == GlobalCounters.kernel_count or (kernels_used <= GlobalCounters.kernel_count and getattr(Device[Device.DEFAULT], "graph", None)), f"only {kernels_used} out of {GlobalCounters.kernel_count} were jitted" # noqa: E501 + +class TestRealWorld(unittest.TestCase): + def setUp(self): + gc.collect() + global global_mem_used + global_mem_used = GlobalCounters.mem_used + self.old_float = dtypes.default_float + np.random.seed(2002) + + def tearDown(self): + dtypes.default_float = self.old_float + + @unittest.skipIf(CI and Device.DEFAULT == "CPU", "slow, covered by METAL") + @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need dtypes.float16") + def test_stable_diffusion(self): + params = unet_params + params["model_ch"] = 16 + params["ctx_dim"] = 16 + params["num_res_blocks"] = 1 + params["n_heads"] = 2 + model = UNetModel(**params) + derandomize_model(model) + @TinyJit + def test(t, t2): return model(t, Tensor([801]), t2).realize() + helper_test("test_sd", lambda: (Tensor.randn(1, 4, 32, 32),Tensor.randn(1, 77, params["ctx_dim"])), test, 18.0, 515) + + def test_unet_resblock(self): + model = [ResBlock(16, 24, 16) for _ in range(4)] + derandomize_model(model) + @TinyJit + def test(t, t2): + for l in model: t = l(t, t2) + return t.realize() + helper_test("test_unet_resblock", lambda: (Tensor.empty(4, 16, 8, 8), Tensor.empty(1, 24)), test, 0.01, 37) + + @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need dtypes.float16") + def test_llama(self): + dtypes.default_float = dtypes.float16 + + args_tiny = {"dim": 1024, "hidden_dim": 2048, "n_heads": 8, "n_layers": 8, "norm_eps": 1e-05, "vocab_size": 1000} + model = LLaMaTransformer(**args_tiny) + derandomize_model(model) + @TinyJit + def test(t): return model(t, 0).realize() + # TODO: test first token vs rest properly + helper_test("test_llama", lambda: (Tensor([[1,2,3,4]]),), test, 0.27, 168, all_jitted=True) + + @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need dtypes.float16") + def test_gpt2(self): + dtypes.default_float = dtypes.float16 + + args_tiny = {"dim": 1024, "n_heads": 8, "n_layers": 8, "norm_eps": 1e-5, "vocab_size": 1000} + model = GPT2Transformer(**(args_tiny if CI else GPT2_MODEL_PARAMS["gpt2-medium"])) + derandomize_model(model) + @TinyJit + def test(t, v): + with Context(JIT=0): return model(t, v).realize() + helper_test("test_gpt2", lambda: (Tensor([[1,]]),Variable("pos", 1, 100).bind(1)), test, 0.23 if CI else 0.9, 137 if CI else 396, all_jitted=True) + + @unittest.skipIf(CI and Device.DEFAULT == "CPU", "slow") + def test_train_mnist(self): + from examples.beautiful_mnist import Model + with Tensor.train(): + model = Model() + optimizer = optim.Adam(get_parameters(model)) + BS = 32 + + @TinyJit + def train(X): + out = model(X) + loss = out.mean() + optimizer.zero_grad() + loss.backward() + optimizer.step() + + helper_test("train_mnist", lambda: (Tensor.randn(BS, 1, 28, 28),), train, 0.07, 93) + + @unittest.skipIf(CI and Device.DEFAULT in {"CPU", "GPU", "LLVM"}, "slow") + def test_train_cifar(self): + with Tensor.train(): + model = SpeedyResNet(Tensor.ones((12,3,2,2))) + optimizer = optim.SGD(get_parameters(model), lr=0.01, momentum=0.8, nesterov=True, weight_decay=0.15) + BS = 32 + + @TinyJit + def train(X): + out = model(X) + loss = out.mean() + optimizer.zero_grad() + loss.backward() + optimizer.step() + + helper_test("train_cifar", lambda: (Tensor.randn(BS, 3, 32, 32),), train, (1.0/48)*BS, 126) + + @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need dtypes.float16") + def test_train_cifar_hyp(self): + dtypes.default_float = dtypes.float16 + with Tensor.train(): + model = SpeedyResNet(Tensor.ones((12,3,2,2))) + optimizer = optim.SGD(get_parameters(model), lr=0.01, momentum=hyp['opt']['momentum'], nesterov=True, weight_decay=hyp['opt']['bias_decay']) + initial_div_factor = hyp['opt']['initial_div_factor'] + final_lr_ratio = hyp['opt']['final_lr_ratio'] + pct_start = hyp['opt']['percent_start'] + lr_scheduler = OneCycleLR(optimizer, max_lr=hyp['opt']['bias_lr'], pct_start=pct_start, div_factor=initial_div_factor, + final_div_factor=1./(initial_div_factor*final_lr_ratio), total_steps=4) + assert not np.isnan(lr_scheduler.min_lr), "lr too small or initial_div_facotr too big for half" + + def test_bert(self): + with Tensor.train(): + args_tiny = {"attention_probs_dropout_prob": 0.0, "hidden_dropout_prob": 0.0, "vocab_size": 30522, "type_vocab_size": 2, + "max_position_embeddings": 512, "hidden_size": 128, "intermediate_size": 512, "num_attention_heads": 2, "num_hidden_layers": 2} + model = BertForPretraining(**args_tiny) + optimizer = optim.LAMB(get_parameters(model)) + + @TinyJit + def train(input_ids:Tensor, segment_ids:Tensor, attention_mask:Tensor, + masked_positions:Tensor, masked_lm_ids:Tensor, masked_lm_weights:Tensor, next_sentence_labels:Tensor): + lm_logits, seq_relationship_logits = model(input_ids, attention_mask, masked_positions, segment_ids) + loss = model.loss(lm_logits, seq_relationship_logits, masked_lm_ids, masked_lm_weights, next_sentence_labels) + optimizer.zero_grad() + loss.backward() + optimizer.step() + + from examples.mlperf.helpers import get_fake_data_bert + data = get_fake_data_bert(BS=4) + for v in data.values(): v.to_(Device.DEFAULT) + + helper_test("train_bert", lambda: (data["input_ids"], data["segment_ids"], data["input_mask"], data["masked_lm_positions"], \ + data["masked_lm_ids"], data["masked_lm_weights"], data["next_sentence_labels"]), train, 0.25, 347) + + def test_bert_fuse_arange(self): + with Context(FUSE_ARANGE=1): + self.test_bert() + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/models/test_resnet.py b/tinygrad_repo/test/models/test_resnet.py new file mode 100644 index 000000000..f71d68905 --- /dev/null +++ b/tinygrad_repo/test/models/test_resnet.py @@ -0,0 +1,21 @@ +import unittest +from extra.models import resnet + +class TestResnet(unittest.TestCase): + def test_model_load(self): + model = resnet.ResNet18() + model.load_from_pretrained() + + model = resnet.ResNeXt50_32X4D() + model.load_from_pretrained() + + def test_model_load_no_fc_layer(self): + model = resnet.ResNet18(num_classes=None) + model.load_from_pretrained() + + model = resnet.ResNeXt50_32X4D(num_classes=None) + model.load_from_pretrained() + + +if __name__ == '__main__': + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/models/test_rnnt.py b/tinygrad_repo/test/models/test_rnnt.py new file mode 100644 index 000000000..f9d5e2c9d --- /dev/null +++ b/tinygrad_repo/test/models/test_rnnt.py @@ -0,0 +1,47 @@ +#!/usr/bin/env python +import unittest +import numpy as np +from tinygrad.tensor import Tensor +from extra.models.rnnt import LSTM +import torch + +class TestRNNT(unittest.TestCase): + def test_lstm(self): + BS, SQ, IS, HS, L = 2, 20, 40, 128, 2 + + # create in torch + with torch.no_grad(): + torch_layer = torch.nn.LSTM(IS, HS, L) + + # create in tinygrad + layer = LSTM(IS, HS, L, 0.0) + + # copy weights + with torch.no_grad(): + layer.cells[0].weights_ih.assign(Tensor(torch_layer.weight_ih_l0.numpy())) + layer.cells[0].weights_hh.assign(Tensor(torch_layer.weight_hh_l0.numpy())) + layer.cells[0].bias_ih.assign(Tensor(torch_layer.bias_ih_l0.numpy())) + layer.cells[0].bias_hh.assign(Tensor(torch_layer.bias_hh_l0.numpy())) + layer.cells[1].weights_ih.assign(Tensor(torch_layer.weight_ih_l1.numpy())) + layer.cells[1].weights_hh.assign(Tensor(torch_layer.weight_hh_l1.numpy())) + layer.cells[1].bias_ih.assign(Tensor(torch_layer.bias_ih_l1.numpy())) + layer.cells[1].bias_hh.assign(Tensor(torch_layer.bias_hh_l1.numpy())) + + # test initial hidden + for _ in range(3): + x = Tensor.randn(SQ, BS, IS) + z, hc = layer(x, None) + torch_x = torch.tensor(x.numpy()) + torch_z, torch_hc = torch_layer(torch_x) + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-3, rtol=5e-3) + + # test passing hidden + for _ in range(3): + x = Tensor.randn(SQ, BS, IS) + z, hc = layer(x, hc) + torch_x = torch.tensor(x.numpy()) + torch_z, torch_hc = torch_layer(torch_x, torch_hc) + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-3, rtol=5e-3) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/models/test_train.py b/tinygrad_repo/test/models/test_train.py new file mode 100644 index 000000000..605e6f6de --- /dev/null +++ b/tinygrad_repo/test/models/test_train.py @@ -0,0 +1,85 @@ +import unittest +import time +import numpy as np +from tinygrad.nn.state import get_parameters +from tinygrad.nn import optim +from tinygrad.tensor import Device +from tinygrad.helpers import getenv, CI +from extra.training import train +from extra.models.convnext import ConvNeXt +from extra.models.efficientnet import EfficientNet +from extra.models.transformer import Transformer +from extra.models.vit import ViT +from extra.models.resnet import ResNet18 + +BS = getenv("BS", 2) + +def train_one_step(model,X,Y): + params = get_parameters(model) + pcount = 0 + for p in params: + pcount += np.prod(p.shape) + optimizer = optim.SGD(params, lr=0.001) + print("stepping %r with %.1fM params bs %d" % (type(model), pcount/1e6, BS)) + st = time.time() + train(model, X, Y, optimizer, steps=1, BS=BS) + et = time.time()-st + print("done in %.2f ms" % (et*1000.)) + +def check_gc(): + if Device.DEFAULT == "GPU": + from extra.introspection import print_objects + assert print_objects() == 0 + +class TestTrain(unittest.TestCase): + def test_convnext(self): + model = ConvNeXt(depths=[1], dims=[16]) + X = np.zeros((BS,3,224,224), dtype=np.float32) + Y = np.zeros((BS), dtype=np.int32) + train_one_step(model,X,Y) + check_gc() + + @unittest.skipIf(CI, "slow") + @unittest.skipIf(Device.DEFAULT in ["METAL", "WEBGPU"], "too many buffers for webgpu and metal") + def test_efficientnet(self): + model = EfficientNet(0) + X = np.zeros((BS,3,224,224), dtype=np.float32) + Y = np.zeros((BS), dtype=np.int32) + train_one_step(model,X,Y) + check_gc() + + @unittest.skipIf(CI, "slow") + @unittest.skipIf(Device.DEFAULT in ["METAL", "WEBGPU"], "too many buffers for webgpu and metal") + def test_vit(self): + model = ViT() + X = np.zeros((BS,3,224,224), dtype=np.float32) + Y = np.zeros((BS,), dtype=np.int32) + train_one_step(model,X,Y) + check_gc() + + @unittest.skipIf(Device.DEFAULT in ["METAL", "WEBGPU"], "too many buffers for webgpu and metal") + def test_transformer(self): + # this should be small GPT-2, but the param count is wrong + # (real ff_dim is 768*4) + model = Transformer(syms=10, maxlen=6, layers=12, embed_dim=768, num_heads=12, ff_dim=768//4) + X = np.zeros((BS,6), dtype=np.float32) + Y = np.zeros((BS,6), dtype=np.int32) + train_one_step(model,X,Y) + check_gc() + + @unittest.skipIf(CI, "slow") + def test_resnet(self): + X = np.zeros((BS, 3, 224, 224), dtype=np.float32) + Y = np.zeros((BS), dtype=np.int32) + for resnet_v in [ResNet18]: + model = resnet_v() + model.load_from_pretrained() + train_one_step(model, X, Y) + check_gc() + + def test_bert(self): + # TODO: write this + pass + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/models/test_waifu2x.py b/tinygrad_repo/test/models/test_waifu2x.py new file mode 100644 index 000000000..957d34fd5 --- /dev/null +++ b/tinygrad_repo/test/models/test_waifu2x.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python +import pathlib +import unittest +import numpy as np +from tinygrad.tensor import Tensor + +class TestVGG7(unittest.TestCase): + def test_vgg7(self): + from examples.vgg7_helpers.waifu2x import Vgg7, image_load + + # Create in tinygrad + Tensor.manual_seed(1337) + mdl = Vgg7() + mdl.load_from_pretrained() + + # Scale up an image + test_x = image_load(pathlib.Path(__file__).parent / 'waifu2x/input.png') + test_y = image_load(pathlib.Path(__file__).parent / 'waifu2x/output.png') + scaled = mdl.forward_tiled(test_x, 156) + scaled = np.fmax(0, np.fmin(1, scaled)) + np.testing.assert_allclose(scaled, test_y, atol=5e-3, rtol=5e-3) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/models/test_whisper.py b/tinygrad_repo/test/models/test_whisper.py new file mode 100644 index 000000000..f1696fd49 --- /dev/null +++ b/tinygrad_repo/test/models/test_whisper.py @@ -0,0 +1,71 @@ +import unittest +import pathlib +from examples.whisper import init_whisper, load_file_waveform, transcribe_file, transcribe_waveform +from tinygrad.helpers import CI, fetch +from tinygrad import Device, dtypes +from tinygrad.device import is_dtype_supported + +# Audio generated with the command on MacOS: +# say "Could you please let me out of the box?" --file-format=WAVE --data-format=LEUI8@16000 -o test +# We use the WAVE type because it's easier to decode in CI test environments +TEST_FILE_1 = str(pathlib.Path(__file__).parent / "whisper/test.wav") +TRANSCRIPTION_1 = "Could you please let me out of the box?" +TEST_FILE_2 = str(pathlib.Path(__file__).parent / "whisper/test2.wav") +TRANSCRIPTION_2 = "a slightly longer audio file so that we can test batch transcriptions of varying length." +# TODO this file will possibly not survive long. find another 1-2 minute sound file online to transcribe +TEST_FILE_3_URL = 'https://homepage.ntu.edu.tw/~karchung/miniconversations/mc45.mp3' +TRANSCRIPTION_3 = "Just lie back and relax. Is the level of pressure about right? Yes, it's fine, and I'd like conditioner please. Sure. I'm going to start the second lathering now. Would you like some Q-tips? How'd you like it cut? I'd like my bangs and the back trimmed, and I'd like the rest thinned out a bit and layered. Where would you like the part? On the left, right about here. Here, have a look. What do you think? It's fine. Here's a thousand anti-dollars. It's 30-ant extra for the rants. Here's your change and receipt. Thank you, and please come again. So how do you like it? It could have been worse, but you'll notice that I didn't ask her for her card. Hmm, yeah. Maybe you can try that place over there next time." # noqa: E501 + +@unittest.skipIf(CI and Device.DEFAULT in ["CPU"], "slow") +@unittest.skipUnless(is_dtype_supported(dtypes.float16), "need float16 support") +class TestWhisper(unittest.TestCase): + @classmethod + def setUpClass(cls): + model, enc = init_whisper("tiny.en", batch_size=2) + cls.model = model + cls.enc = enc + + @classmethod + def tearDownClass(cls): + del cls.model + del cls.enc + + def test_transcribe_file1(self): + self.assertEqual(transcribe_file(self.model, self.enc, TEST_FILE_1), TRANSCRIPTION_1) + + @unittest.skipIf(CI or Device.DEFAULT == "LLVM", "too many tests for CI") + def test_transcribe_file2(self): + self.assertEqual(transcribe_file(self.model, self.enc, TEST_FILE_2), TRANSCRIPTION_2) + + @unittest.skipIf(CI or Device.DEFAULT == "LLVM", "too many tests for CI") + def test_transcribe_batch12(self): + waveforms = [load_file_waveform(TEST_FILE_1), load_file_waveform(TEST_FILE_2)] + transcriptions = transcribe_waveform(self.model, self.enc, waveforms) + self.assertEqual(2, len(transcriptions)) + self.assertEqual(TRANSCRIPTION_1, transcriptions[0]) + self.assertEqual(TRANSCRIPTION_2, transcriptions[1]) + + def test_transcribe_batch21(self): + waveforms = [load_file_waveform(TEST_FILE_2), load_file_waveform(TEST_FILE_1)] + transcriptions = transcribe_waveform(self.model, self.enc, waveforms) + self.assertEqual(2, len(transcriptions)) + self.assertEqual(TRANSCRIPTION_2, transcriptions[0]) + self.assertEqual(TRANSCRIPTION_1, transcriptions[1]) + + @unittest.skipIf(CI or Device.DEFAULT == "LLVM", "too long for CI") + def test_transcribe_long(self): + waveform = [load_file_waveform(fetch(TEST_FILE_3_URL))] + transcription = transcribe_waveform(self.model, self.enc, waveform) + self.assertEqual(TRANSCRIPTION_3, transcription) + + @unittest.skipIf(CI or Device.DEFAULT == "LLVM", "too long for CI") + def test_transcribe_long_no_batch(self): + waveforms = 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zbdTeGLn26gd4mlL8EsO?XuE+mB4LsO!r(F!1bwfy z5tzC-Ua6v%s}IiZvw5K)pq5c!B1=oqFj)fzT{{649+f5tv>k@*1C5F=SoiduNf#Pa+#avk+}-OJI~-mXSu0xnjjH8fEZt+i)LvJMKipekfAbTYbM zr9fk5PBfJ~O~n>zZ7OY{(@7FC)z)UQttIsryqri&iW*jE^?+5YImH=Vqfu2}f@{O} z!%J6eDv;<5m`aNRt4p+3T~un2-9?sTYiD?}CP>j}Ds;JHbeB_8N&yKEVzwIchxV{V zOH!*4`qbX2x1!9%la^PMwQ7Q!XhFnt->h#s7)EuH_7U2a{K{=c=%D1lsg|*3?A1}z zbM?@`X&*kmH~F96Yo9ltY=`5c5R2kI%Lnplzg9H&S|pE6ZeH|#Tl>?^BR}Bad6s{8 zIQ4:0:0: local memory (65544) exceeds limit (65536) in function 'test' + compiler.compile(src.format(N=65536//8+1)) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_arange.py b/tinygrad_repo/test/test_arange.py new file mode 100644 index 000000000..308c741e5 --- /dev/null +++ b/tinygrad_repo/test/test_arange.py @@ -0,0 +1,221 @@ +import unittest, contextlib +import numpy as np +from tinygrad import Tensor, GlobalCounters, dtypes, nn, Device, Variable +from tinygrad.helpers import CI, Context, getenv +from tinygrad.engine.realize import run_schedule +from tinygrad.opt.kernel import Opt, OptOps, Kernel, KernelOptError +from tinygrad.engine.realize import CompiledRunner, ExecItem +from tinygrad.opt.search import get_kernel_actions +from tinygrad.uop.ops import Ops + +class TestArange(unittest.TestCase): + def _get_flops(self, N, opts=None): + GlobalCounters.reset() + tt = Tensor.arange(N) + sched = tt.schedule() + self.assertEqual(len(sched), 1) + k = Kernel(sched[-1].ast) + if opts is not None: + for o in opts: k.apply_opt(o) + p = k.to_program() + print(p.name) + #print(p.src) + ExecItem(CompiledRunner(p), [tt.uop.buffer]).run() + np.testing.assert_equal(tt.numpy(), np.arange(N)) + return p.estimates.ops + + def test_complexity(self, opts=None, limit=None): + f1 = self._get_flops(256, opts) + f2 = self._get_flops(2560, opts) + print(f"{f1=}, {f2=}") + # add 1 to avoid divide by 0. arange is 0 flops now! + assert (f1 < 6000 and f2 < 6000) or ((f2+1) / (f1+1) < 16), f"bad complexity, flops {(f2+1) / (f1+1):.1f}X while inputs 10X" + if limit is not None and not getenv("PTX"): + # PTX counts index ALU in flops + assert f1 <= limit, f"{f1=}, {limit=}" + + def test_complexity_w_upcast(self): return self.test_complexity([Opt(OptOps.UPCAST, 0, 4)], limit=0) + def test_complexity_w_unroll2(self): return self.test_complexity([Opt(OptOps.UNROLL, 0, 2)], limit=0) + def test_complexity_w_unroll4(self): return self.test_complexity([Opt(OptOps.UNROLL, 0, 4)], limit=0) + def test_complexity_w_unroll8(self): return self.test_complexity([Opt(OptOps.UNROLL, 0, 8)], limit=0) + def test_complexity_w_upcast_and_unroll(self): return self.test_complexity([Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UNROLL, 0, 4)], limit=0) + + if Device.default.renderer.has_local: + # TODO: fix limit + def test_complexity_w_group(self): return self.test_complexity([Opt(OptOps.GROUP, 0, 16)], limit=81920) + def test_complexity_w_group_top(self): return self.test_complexity([Opt(OptOps.GROUPTOP, 0, 16)], limit=106496) + + def test_complexity_w_local(self): return self.test_complexity([Opt(OptOps.LOCAL, 0, 16)], limit=0) + @unittest.skip("doesn't work yet. TODO: this absolutely should work") + def test_complexity_w_local_unroll4(self): return self.test_complexity([Opt(OptOps.LOCAL, 0, 16), Opt(OptOps.UNROLL, 0, 4)], limit=0) + @unittest.skip("doesn't work yet") + def test_complexity_w_local_and_padto(self): return self.test_complexity([Opt(OptOps.LOCAL, 0, 16), Opt(OptOps.PADTO, axis=1, arg=32)]) + + def test_all_opts(self, opts=None, exclude=None): + k = Kernel(Tensor.arange(256).schedule()[-1].ast) + if opts is not None: + for o in opts: k.apply_opt(o) + all_opts_256 = [kk.applied_opts for kk in get_kernel_actions(k, include_0=False).values()] + k = Kernel(Tensor.arange(2560).schedule()[-1].ast) + if opts is not None: + for o in opts: k.apply_opt(o) + all_opts_2560 = [kk.applied_opts for kk in get_kernel_actions(k, include_0=False).values()] + all_opts = [x for x in all_opts_256 if x in all_opts_2560] + for opts in all_opts: + if exclude is not None and opts[-1] in exclude: continue + print(opts) + self.test_complexity(opts) + def test_all_opts_w_local(self): + with contextlib.suppress(KernelOptError): + return self.test_all_opts([Opt(OptOps.LOCAL, 0, 16)], [Opt(op=OptOps.PADTO, axis=1, arg=32)]) + def test_all_opts_w_upcast(self): return self.test_all_opts([Opt(OptOps.UPCAST, 0, 4)]) + def test_all_opts_w_unroll(self): return self.test_all_opts([Opt(OptOps.UNROLL, 0, 4)], [Opt(op=OptOps.GROUP, axis=0, arg=0)]) + def test_all_opts_w_upcast_and_unroll(self): + return self.test_all_opts([Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UNROLL, 0, 4)], [Opt(op=OptOps.GROUP, axis=0, arg=0)]) + +class TestRand(unittest.TestCase): + def test_fused_rand_less_ops(self, noopt=1): + GlobalCounters.reset() + with Context(FUSE_ARANGE=0, NOOPT=noopt): + out = Tensor.rand(16384) + out.realize() + unfused_ops = GlobalCounters.global_ops + + GlobalCounters.reset() + with Context(FUSE_ARANGE=1, NOOPT=noopt): + out = Tensor.rand(16384) + out.realize() + print(f"fused {GlobalCounters.global_ops} unfused {unfused_ops}") + self.assertLessEqual(GlobalCounters.global_ops, unfused_ops*2) + def test_fused_rand_less_ops_opt(self): self.test_fused_rand_less_ops(0) + +DSET, DDIM = 2048, 32 + +class TestIndexing(unittest.TestCase): + def test_arange_2_reduce(self): + needle = Tensor.zeros(16384, dtype=dtypes.int).contiguous() + needle[1337] = 1 + needle.realize() + with Context(NOOPT=1, FUSE_ARANGE=1): + GlobalCounters.reset() + out = ((Tensor.arange(1,16385)-1)*needle).sum() + sched = out.schedule() + self.assertEqual(len(sched), 1) + run_schedule(sched) + self.assertEqual(out.item(), 1337) + + @unittest.skipIf(getenv("PTX"), "broken on ptx for some reason") + def test_manual_index(self): + dataset = Tensor.rand(DSET, DDIM).realize() + idxs = Tensor([0,3,5,6]).realize() + real_index = dataset.numpy()[idxs.numpy()] + print("*** indexing ***") + with Context(NOOPT=1, FUSE_ARANGE=1): + GlobalCounters.reset() + rng = Tensor.ones(4, DDIM, DSET, dtype=dtypes.int)._cumalu(axis=-1, op=Ops.ADD, _include_initial=True).reshape(4, DDIM, DSET, 1) + idxs = idxs.reshape(4,1,1,1).expand(4, DDIM, DSET, 1) + reshape_dataset = dataset.T.reshape(1, DDIM, DSET, 1).expand(4, DDIM, DSET, 1) + full = (rng==idxs).where(reshape_dataset, Tensor.zeros(4, DDIM, DSET, 1)) + X = full.sum(axis=(2,3)) + sched = X.schedule() + self.assertEqual(len(sched), 1) + run_schedule(sched) + assert GlobalCounters.global_ops < 4*DSET, f"too many ops {GlobalCounters.global_ops}" + np.testing.assert_allclose(real_index, X.numpy()) + + def test_index_variable(self): + dataset = Tensor.rand(DSET, DDIM).realize() + v = Variable("v", 0, DDIM-1) + with Context(NOOPT=1, FUSE_ARANGE=1, SPLIT_REDUCEOP=0): + GlobalCounters.reset() + vb = Tensor(v.bind(12)) + comp = dataset[vb].numpy() + # no global ops because they are all indexing + self.assertEqual(GlobalCounters.global_ops, 0) + np.testing.assert_allclose(comp, dataset.numpy()[12]) + + def test_index(self): + dataset = Tensor.rand(DSET, DDIM).realize() + idxs = Tensor([0,3,5,6]).realize() + real_index = dataset.numpy()[idxs.numpy()] + print("*** indexing ***") + with Context(NOOPT=1): + GlobalCounters.reset() + X = dataset[idxs] + assert X.shape == (4,DDIM) + sched = X.schedule() + # TODO: enable these asserts when the scheduler can handle this + #self.assertEqual(len(sched), 1) + run_schedule(sched) + #assert GlobalCounters.global_ops < 4*DSET, f"too many ops {GlobalCounters.global_ops}" + np.testing.assert_allclose(real_index, X.numpy()) + + def test_index_fused(self, noopt=1): + dataset = Tensor.rand(DSET, DDIM).realize() + idxs = Tensor([0,3,5,6]).realize() + real_index = dataset.numpy()[idxs.numpy()] + print("*** indexing ***") + with Context(NOOPT=noopt, FUSE_ARANGE=1): + GlobalCounters.reset() + X = dataset[idxs] + assert X.shape == (4,DDIM) + sched = X.schedule() + self.assertEqual(len(sched), 2) + run_schedule(sched) + assert GlobalCounters.global_ops < 4*DSET, f"too many ops {GlobalCounters.global_ops} != {4*DSET}" + np.testing.assert_allclose(real_index, X.numpy()) + @unittest.skip("not ready") + def test_index_fused_opt(self): self.test_index_fused(0) + + def test_index_fused_out_of_bounds(self): + dataset = Tensor.rand(256, 256).realize() + idxs = Tensor([-19238, -257, 256, 495, 10982377]).realize() + with Context(NOOPT=1, FUSE_ARANGE=1): + X = dataset[idxs] + np.testing.assert_equal(X.numpy(), 0) + + @unittest.skipIf(getenv("PTX"), "broken on ptx for some reason") + def test_index_mnist(self, noopt=1, op_limit=512*784*13, split_reduceop=0): + # WEBGPU generates more ops due to bitpacking of < 4-byte dtypes + if Device.DEFAULT == "WEBGPU": op_limit *= 15 + from tinygrad.nn.datasets import mnist + X_train, Y_train, _, _ = mnist() + with Context(NOOPT=noopt, FUSE_ARANGE=1, SPLIT_REDUCEOP=split_reduceop): + samples = Tensor.randint(getenv("BS", 512), high=X_train.shape[0]).realize() + GlobalCounters.reset() + x = X_train[samples].numpy() + y = Y_train[samples].numpy() + assert GlobalCounters.global_ops < op_limit, f"too many ops {GlobalCounters.global_ops} != {op_limit}" + np.testing.assert_allclose(X_train.numpy()[samples.numpy()], x) + np.testing.assert_allclose(Y_train.numpy()[samples.numpy()], y) + + def test_index_mnist_opt(self): self.test_index_mnist(0) + def test_index_mnist_split(self): self.test_index_mnist(1, split_reduceop=1) + def test_index_mnist_opt_split(self): self.test_index_mnist(0, split_reduceop=1) + + @unittest.skipIf(getenv("PTX"), "broken on ptx for some reason") + def test_llama_embedding(self, noopt=1, op_limit=65536): + # llama3 is 128256 + vocab_size, embed_size = (10, 3) if CI else (32000, 4096) + emb = nn.Embedding(vocab_size, embed_size) + # TODO: why is a new realize needed here + emb_w = emb.weight.realize().numpy() + x = Tensor([1,2,3,4]) + with Context(NOOPT=noopt, FUSE_ARANGE=1): + GlobalCounters.reset() + z = emb(x).realize() + self.assertLessEqual(GlobalCounters.global_ops, op_limit) + self.assertEqual(GlobalCounters.kernel_count, 2) + if getenv("CHECK", 1): + import torch + with torch.no_grad(): + torch_emb = torch.nn.Embedding(vocab_size, embed_size).eval() + torch_emb.weight[:] = torch.tensor(emb_w, dtype=torch.float32) + torch_z = torch_emb(torch.tensor(x.numpy())) + # TODO: reshape to match torch, should we do this in nn? + np.testing.assert_allclose(z.numpy().reshape(4, embed_size), torch_z.detach().numpy(), atol=1e-8, rtol=1e-8) + # at least the arange is being fused + def test_llama_embedding_opt(self): self.test_llama_embedding(0, 1_736_704_000 if CI else 5_898_240_000) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/test_assign.py b/tinygrad_repo/test/test_assign.py new file mode 100644 index 000000000..837e4141e --- /dev/null +++ b/tinygrad_repo/test/test_assign.py @@ -0,0 +1,398 @@ +#!/usr/bin/env python +import unittest +import numpy as np +from tinygrad import dtypes, Tensor, TinyJit, GlobalCounters, Variable +from tinygrad.device import is_dtype_supported +from tinygrad.helpers import temp + +N = 200 # has to be bigger than the cache to fail + +class TestAssign(unittest.TestCase): + def test_simple_assignment(self): + a = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) + b = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) + a.realize() + b.realize() + ba1 = a.uop.base.realized + bb1 = b.uop.base.realized + a += b + a.realize() + ba2 = a.uop.base.realized + assert ba1 == ba2 and ba1 != bb1 + np.testing.assert_allclose(a.numpy(), (np.arange(N*N)*2).reshape((N,N))) + + def test_assign_zeros_good(self): + a = Tensor.zeros(10,10).contiguous() + a.assign(Tensor.ones(10,10)) + b = Tensor.zeros(10,10).contiguous() + a.realize() + np.testing.assert_allclose(b.numpy(), 0) + + def test_assign_zeros(self): + a = Tensor.zeros(10,10).contiguous() + b = Tensor.zeros(10,10).contiguous() + a.assign(Tensor.ones(10,10)) + a.realize() + np.testing.assert_allclose(b.numpy(), 0) + + def test_assign_add(self): + def f(x): + x += 1 + x.realize() + x = Tensor([0]) + f(x) + assert x.item() == 1 + + def test_assign_add_twice(self): + # NOTE: this has two kernels + def f(x): + x += 1 + x += 1 + x.realize() + x = Tensor([0]) + f(x) + assert x.item() == 2 + + def test_assign_add_double(self): + def f(x): + x += 1 + x.realize() + x = Tensor([0]) + f(x) + out = x.item() + assert out == 1, f"expected 1, got {out}" + x = Tensor([0]) + f(x) + out = x.item() + assert out == 1, f"expected 1, got {out}" + + def test_assign_add_jit(self): + @TinyJit + def f(x): + x += 1 + x.realize() + x = Tensor([0]) + for _ in range(5): f(x) + assert x.item() == 5 + + def test_assign_add_jit_other(self): + @TinyJit + def f(x): + x += 1 + x.realize() + x = Tensor([0]) + for _ in range(5): f(x) + assert x.item() == 5 + + y = Tensor([0]) + for _ in range(4): f(y) + assert y.item() == 4 + + def test_assign_other_jit(self): + @TinyJit + def f(x, a): + x.assign(a) + x.realize() + x = Tensor([0]) + for i in range(1, 6): + f(x, x.full_like(i).contiguous()) # const would be implicitly folded without contiguous + assert x.item() == i + + def test_assign_add_other_jit(self): + @TinyJit + def f(x, a): + x += a + x.realize() + x = Tensor([0]) + a = 0 + for i in range(1, 6): + a += i + f(x, x.full_like(i).contiguous()) + assert x.item() == a + + def test_assign_changes(self): + a = Tensor.ones(4).contiguous().realize() + old_a = a + a.assign(Tensor.full((4,), 2.).contiguous()) + # NOTE: old_a is now 2, and this would match the behavior of pytorch + new = a + old_a + np.testing.assert_allclose(new.numpy(), 4) + + def test_assign_diamond_cycle(self): + # NOTE: should *not* raise AssertionError from numpy + with self.assertRaisesRegex(RuntimeError, "cycle"): + a = Tensor.ones(4).contiguous().realize() + times_a = a*3 + a.assign(Tensor.full((4,), 2.).contiguous()) + new = a + (times_a-1) + np.testing.assert_allclose(new.numpy(), 4) + + def test_assign_diamond_contiguous_cycle(self): + with self.assertRaisesRegex(RuntimeError, "cycle"): + a = Tensor.ones(4).contiguous().realize() + times_a = a*3 + a.assign(Tensor.full((4,), 2.)) + new = a.contiguous() + times_a-1 + np.testing.assert_allclose(new.numpy(), 4) + + def test_assign_diamond_possible(self): + a = Tensor.ones(4).contiguous().realize() + times_a = a*3 + a.assign(Tensor.full((4,), 2.)) + new = a + (times_a-1).contiguous() + np.testing.assert_allclose(new.numpy(), 4) + + def test_assign_diamond_possible_contiguous(self): + a = Tensor.ones(4).contiguous().realize() + times_a = a*3 + a.assign(Tensor.full((4,), 2.).contiguous()) + new = a + (times_a-1).contiguous() + np.testing.assert_allclose(new.numpy(), 4) + + def test_assign_diamond_both_contiguous(self): + a = Tensor.ones(4).contiguous().realize() + times_a = a*3 + a.assign(Tensor.full((4,), 2.)) + new = a.contiguous() + (times_a-1).contiguous() + np.testing.assert_allclose(new.numpy(), 4) + + def test_assign_diamond_alt(self): + a = Tensor.ones(4).contiguous().realize() + a.assign(Tensor.full((4,), 2.).contiguous()) + times_a = a*3 + new = a + times_a + np.testing.assert_allclose(new.numpy(), 8) + + def test_double_assign(self): + a = Tensor.ones(4).contiguous().realize() + a += 1 + a += 1 + np.testing.assert_allclose(a.numpy(), 3) + + def test_crossover_assign(self): + a = Tensor.full((4,), 2).contiguous().realize() + b = Tensor.full((4,), 3).contiguous().realize() + a += b + b += a + Tensor.realize(a,b) + np.testing.assert_allclose(a.numpy(), 5) + np.testing.assert_allclose(b.numpy(), 8) + + def test_assign_double_diamond(self): + a = Tensor.full((4,), 2).contiguous().realize() + b = Tensor.full((4,), 3).contiguous().realize() + a_prev = a*4 + b_prev = b+3 + b += a_prev.contiguous() + a += b_prev.contiguous() + Tensor.realize(a, b) + np.testing.assert_equal(b.numpy(), 11) + np.testing.assert_equal(a.numpy(), 8) + + def test_assign_double_diamond_reduce(self): + a0 = Tensor.full((16, 16), 10).contiguous().realize() + a1 = Tensor.full((16, 16), 20).contiguous().realize() + b0 = Tensor.full((16, ), 1).contiguous().realize() + b1 = Tensor.full((16, ), 2).contiguous().realize() + + r0 = (a0 - b1.contiguous()).sum(1) + r1 = (a1 - b0.contiguous()).sum(1) + b0.assign(r0 * b0) + b1.assign(r1 * b1) + Tensor.realize(b0, b1) + np.testing.assert_equal(b0.numpy(), 128) + np.testing.assert_equal(b1.numpy(), 608) + + @unittest.skip("TODO: bring this assert back") + def test_crossunder_assign(self): + # NOTE: should *not* raise AssertionError from numpy + with self.assertRaisesRegex(RuntimeError, "cycle"): + a = Tensor.full((4,), 2).contiguous().realize() + b = Tensor.full((4,), 3).contiguous().realize() + c = a+9 + a += b + b += c + Tensor.realize(a,b) + np.testing.assert_allclose(a.numpy(), 2+3) + np.testing.assert_allclose(b.numpy(), 3+2+9) + + def test_assign_kv_cache(self): + bsz, max_context = 2, 8 + + class Attn: + @TinyJit + def __call__(self, xk:Tensor, start_pos:Variable): + seqlen = xk.shape[1] + if not hasattr(self, "cache_k"): + self.cache_k = Tensor.zeros(bsz, max_context, 1, 1).contiguous() + keys = self.cache_k.shrink((None, (0, start_pos), None, None)).cat(xk, dim=1).contiguous() if start_pos > 0 else xk + self.cache_k.assign(keys.pad((None,(0,max_context-start_pos-seqlen),None,None)).contiguous()).realize() + + attn = Attn() + xk = Tensor.ones(bsz, 3, 1, 1).contiguous() + attn(xk, 0) + for i in range(3,6): + # copied from LLaMA + start_pos = Variable("start_pos", 1, max_context).bind(i) + xk = Tensor.ones(bsz, 1, 1, 1).contiguous() + attn(xk, start_pos) + + out = attn.cache_k.flatten().numpy() + np.testing.assert_allclose(out, [1.,1.,1.,1.,1.,1.,0.,0.,1.,1.,1.,1.,1.,1.,0.,0.]) + + def test_assign_contiguous(self): + b = Tensor.rand(4,4).realize() + a = (Tensor.rand(4,4).realize() + 1) + kc = GlobalCounters.kernel_count + b.assign(a.contiguous()).realize() + assert GlobalCounters.kernel_count - kc == 2 + + def test_assign_contiguous_permute(self): + b = Tensor.rand(4,4).realize() + a = (Tensor.rand(4,4).realize() + 1).permute((1,0)) + kc = GlobalCounters.kernel_count + b.assign(a.contiguous()).realize() + assert GlobalCounters.kernel_count - kc == 2 + + def test_permuted_assignment(self): + a = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) + b = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) + a.realize() + b.realize() + ba1 = a.uop.base.realized + bb1 = b.uop.base.realized + with self.assertRaises((RuntimeError, AssertionError)): + a = a.permute(1,0) + a += b + a.realize() + ba2 = a.uop.base.realized + assert ba1 != ba2 and ba1 != bb1 + np.testing.assert_allclose(a.numpy(), np.arange(N*N).reshape((N,N)) + np.arange(N*N).reshape((N,N)).transpose(1,0)) + + def test_post_permuted_assignment(self): + a = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) + b = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) + a.realize() + b.realize() + #GlobalCounters.cache = [] + ba1 = a.uop.base.realized # noqa: F841 + bb1 = b.uop.base.realized # noqa: F841 + with self.assertRaisesRegex(RuntimeError, "contiguous"): + a.assign(a.permute(1,0) + b) # this should not work! + a.realize() + ba2 = a.uop.base.realized # noqa: F841 + # NOTE: don't test that it's assigned + #assert ba1 == ba2 and ba1 != bb1 + np.testing.assert_allclose(a.numpy(), np.arange(N*N).reshape((N,N)) + np.arange(N*N).reshape((N,N)).transpose(1,0)) + + @unittest.skip("multi output not supported anymore") + def test_simple_assignment_multioutput(self): + a = Tensor.randn(32, 32).realize() + b = Tensor.full((32, ), 1.).contiguous().realize() + c = Tensor.full((32, ), 2.).contiguous().realize() + d = Tensor.full((32, ), 3.).contiguous().realize() + + r = a.sum(axis=1) + b.assign(r + b) + c.assign(r + c) + d.assign(r + d) + + kc = GlobalCounters.kernel_count + Tensor.realize(b, c, d) + assert GlobalCounters.kernel_count - kc == 1 + np.testing.assert_allclose(b.numpy(), a.sum(1).numpy()+1) + np.testing.assert_allclose(c.numpy(), a.sum(1).numpy()+2) + np.testing.assert_allclose(d.numpy(), a.sum(1).numpy()+3) + + # NOTE: if the assign target is read/write in a single kernel, it should be contiguous + + def test_permuted_assignment_correct(self): + a = Tensor.arange(4 * 4).reshape(4, 4).contiguous().realize() + b = Tensor.arange(4 * 4).reshape(4, 4).contiguous().realize() + # TODO: scheduler limitation, should NOT raise AssertionError from numpy. + with self.assertRaisesRegex(RuntimeError, "contiguous"): + a = a.permute(1, 0) + new_val = a + b + a.assign(new_val) + np.testing.assert_equal(a.numpy(), np.arange(4 * 4).reshape(4, 4).transpose(1, 0) + np.arange(4 * 4).reshape(4, 4)) + + def test_permuted_reduceop_child_dual_use(self): + a = Tensor.randn(32, 32, 32).realize() + b = Tensor.full((32, 32), 1.).contiguous().realize() + with self.assertRaisesRegex(RuntimeError, "contiguous"): + r = a.sum(axis=1) + b.assign(r + b.permute(1, 0)) + b.realize() + + @unittest.skip("multi output not supported anymore") + def test_permuted_reduceop_multioutput_dual_use(self): + a = Tensor.randn(32, 32, 32).realize() + b = Tensor.full((32, 32), 1.).contiguous().realize() + c = Tensor.full((32, 32), 2.).contiguous().realize() + + with self.assertRaisesRegex(RuntimeError, "contiguous"): + r = a.sum(axis=1) + b_perm = b.permute(1, 0) + b.assign(r + b) + c.assign(r + b_perm) + Tensor.realize(b, c) + + @unittest.skip("multi output not supported anymore") + def test_permuted_reduceop_multioutput_dual_use_possible(self): + a = Tensor.randn(32, 32, 32, dtype=dtypes.int).realize() + b = Tensor.arange(32 * 32).reshape(32, 32).realize() + c = Tensor.arange(32 * 32).reshape(32, 32).realize() + + kc = GlobalCounters.kernel_count + r = a.sum(axis=1) + b_perm = b.permute(1, 0) + b.assign(r + b) + c.assign(r + b_perm.contiguous()) + Tensor.realize(b, c) + assert GlobalCounters.kernel_count - kc == 2 + np.testing.assert_equal(b.numpy(), a.numpy().sum(1) + np.arange(32 * 32).reshape(32, 32)) + np.testing.assert_equal(c.numpy(), a.numpy().sum(1) + np.arange(32 * 32).reshape(32, 32).transpose(1, 0)) + + def test_permuted_assignment_masked_view_possible(self): + a = Tensor.ones(4, 4).contiguous().realize() + b = a.shrink((None, (0, 2))).pad((None, (0, 2)), value=2) + a.assign(a + b) + kc = GlobalCounters.kernel_count + a.realize() + assert GlobalCounters.kernel_count - kc == 1 + np.testing.assert_equal(a.numpy(), np.ones((4, 4))+np.pad(np.ones((4, 4))[:, 0:2], ((0, 0), (0, 2)), constant_values=2)) + + def test_permuted_assignment_masked_view_not_contiguous(self): + a = Tensor.ones(4, 4).contiguous().realize() + with self.assertRaisesRegex(RuntimeError, "contiguous"): + b = a.shrink((None, (0, 2))).pad((None, (0, 2)), value=2).permute(1, 0) + a.assign(a + b) + a.realize() + + # TODO: is there a way to sneak in a permute such that it returns the wrong answer? + + @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") + def test_setitem_half(self): + a = Tensor.full((8,), 1.0, dtype=dtypes.half).contiguous().realize() + b = Tensor.full((4,), 2.0, dtype=dtypes.half).contiguous().realize() + assign = a[:4].assign(b) + assign.realize() + np.testing.assert_allclose(a.numpy(), [2., 2., 2., 2., 1., 1., 1., 1.]) + + @unittest.skip("don't use output buffer, and mismatch dtype no longer supported") + def test_cast_assignment(self): + a = Tensor(np.arange(N*N, dtype=np.float32)).reshape(N,N) + a.realize() + oba1 = a.uop.base.output_buffer + a.assign(a.cast(dtypes.int32).realize()) + a.realize() + oba2 = a.uop.base.output_buffer + assert oba1 is None and oba2 is None + np.testing.assert_allclose(a.numpy(), np.arange(N*N,dtype=np.int32).reshape((N,N))) + + def test_disk_assignment(self): + a = Tensor.empty(5, device=f"disk:{temp('disk_assignment')}").assign(Tensor.ones(5)).numpy() + np.testing.assert_equal(a, np.ones(5)) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/test_compile_failures.py b/tinygrad_repo/test/test_compile_failures.py new file mode 100644 index 000000000..5ab87c0b6 --- /dev/null +++ b/tinygrad_repo/test/test_compile_failures.py @@ -0,0 +1,18 @@ +import unittest +from tinygrad import Tensor, dtypes, Device +from tinygrad.engine.realize import lower_schedule +from tinygrad.device import is_dtype_supported + +class TestCompileFailures(unittest.TestCase): + def compile(self, out:Tensor): + for _ in lower_schedule(out.schedule()): pass + + @unittest.skipUnless(is_dtype_supported(dtypes.uchar, Device.DEFAULT), f"no uint8 on {Device.DEFAULT}") + def test_interpolate_atari(self): + self.compile(Tensor.empty(210, 160, dtype='uint8').interpolate((64, 64))) + + def test_add_max_uchar(self): + self.compile((Tensor.empty(1024, dtype='uint8') + Tensor.empty(1024, dtype='uint8')).max()) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_const_folding.py b/tinygrad_repo/test/test_const_folding.py new file mode 100644 index 000000000..187a4b514 --- /dev/null +++ b/tinygrad_repo/test/test_const_folding.py @@ -0,0 +1,341 @@ +import unittest, itertools, math +from typing import Any +from tinygrad import Tensor, Device, dtypes +from tinygrad.dtype import DType +from tinygrad.uop.ops import Ops, UOp +from tinygrad.codegen import full_rewrite_to_sink +import numpy as np +from tinygrad.device import is_dtype_supported +from test.helpers import not_support_multi_device + +def _check_ast_count(desired_count:int, t:Tensor): + # NOTE: this has side effect because everything can be scheduled only once + schedule = t.schedule() + asts = [s for s in schedule if s.ast.op is Ops.SINK] + assert len(asts) == desired_count, f"{len(asts)} != {desired_count}" + +class TestUnaryOpsConstFolding(unittest.TestCase): + def test_all_consts_ops(self): + _check_ast_count(0, Tensor.ones(4).exp()) + _check_ast_count(0, Tensor.ones(4).sqrt()) + _check_ast_count(0, Tensor.ones(4) + Tensor.ones(4)) + _check_ast_count(0, Tensor.ones(4) / Tensor.ones(4)) + + def test_cast(self): + _check_ast_count(0, Tensor.ones(4).cast(dtypes.int16)) + _check_ast_count(0, Tensor.full(4, fill_value=-1).cast(dtypes.uint16)) + + @unittest.expectedFailure # no two level fold at lazybuffer + def test_neg_folding(self): + _check_ast_count(0, Tensor([1, 2, 3]).mul(-1).neg()) + _check_ast_count(0, Tensor([1, 2, 3]).neg().mul(-1)) + _check_ast_count(0, Tensor([1, 2, 3]).neg().neg()) + + def test_neg_realized_no_fold(self): + x = Tensor.randn(32, 32) + x = x.clip(0, 1).realize() + _check_ast_count(1, x.neg()) + +class TestBinaryOpsConstFolding(unittest.TestCase): + def test_add_literal_zero(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) + 0) + def test_add_tensor_zero(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) + Tensor.zeros(4)) + def test_literal_zero_add(self): + _check_ast_count(0, 0 + Tensor([1.0, 2, 3, 4])) + def test_tensor_zero_add(self): + _check_ast_count(0, Tensor.zeros(4) + Tensor([1.0, 2, 3, 4])) + + def test_sub_literal_zero(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) - 0) + def test_sub_tensor_zero(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) - Tensor.zeros(4)) + + def test_mul_literal_zero(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) * 0) + def test_mul_tensor_zero(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) * Tensor.zeros(4)) + def test_literal_zero_mul(self): + _check_ast_count(0, 0 * Tensor([1.0, 2, 3, 4]) * 0) + def test_tensor_zero_mul(self): + _check_ast_count(0, Tensor.zeros(4) * Tensor([1.0, 2, 3, 4])) + + def test_mul_literal_one(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) * 1) + def test_mul_tensor_one(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) * Tensor.ones(4)) + def test_literal_one_mul(self): + _check_ast_count(0, 1 * Tensor([1.0, 2, 3, 4])) + def test_tensor_one_mul(self): + _check_ast_count(0, Tensor.ones(4) * Tensor([1.0, 2, 3, 4])) + + def test_bool_tensor_mul_bool(self): + _check_ast_count(0, Tensor([True, False]) * True) + _check_ast_count(0, Tensor([True, False]) * False) + def test_bool_mul_bool_tensor(self): + _check_ast_count(0, True * Tensor([True, False])) + _check_ast_count(0, False * Tensor([True, False])) + + def test_div_literal_one(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) / 1) + def test_div_tensor_one(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) / Tensor.ones(4)) + + @unittest.expectedFailure # TODO: fix + def test_idiv_literal_one(self): + _check_ast_count(0, Tensor([1, 2, 3, 4]) // 1) + @unittest.expectedFailure # TODO: fix + def test_idiv_tensor_one(self): + _check_ast_count(0, Tensor([1, 2, 3, 4]) // Tensor.ones(4, dtype=dtypes.int32)) + + def test_pow_literal_zero(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) ** 0) + def test_pow_tensor_zero(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) ** Tensor.zeros(4)) + + def test_pow_literal_one(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) ** 1) + def test_pow_tensor_one(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) ** Tensor.ones(4)) + def test_literal_one_pow(self): + _check_ast_count(0, 1 ** Tensor([1.0, 2, 3, 4])) + def test_tensor_one_pow(self): + _check_ast_count(0, Tensor.ones(4) ** Tensor([1.0, 2, 3, 4])) + +class TestBitcastConstFolding(unittest.TestCase): + def test_scalar_bitcast(self): + def t(cases: dict[DType, Any]): + for (from_dt, from_v), (to_dt, to_v) in itertools.product(cases.items(), cases.items()): + if not math.isnan(from_v): + r = full_rewrite_to_sink(UOp.const(from_dt, from_v).bitcast(to_dt).sink()).src[0] + self.assertEqual(r.op, Ops.CONST, msg:=f"{from_dt} -> {to_dt} ({from_v} -> {to_v})") + self.assertEqual(r.dtype, to_dt, msg) + np.testing.assert_equal(r.arg, to_v, msg) + + t({dtypes.int8: 0, dtypes.uint8: 0, dtypes.bool: False}) + t({dtypes.int8: 1, dtypes.uint8: 1, dtypes.bool: True}) + + t({dtypes.int8: -1, dtypes.uint8: 2**8-1}) + t({dtypes.int16: -1, dtypes.uint16: 2**16-1, dtypes.float16: float('nan')}) + t({dtypes.int32: -1, dtypes.uint32: 2**32-1, dtypes.float32: float('nan')}) + t({dtypes.int64: -1, dtypes.uint64: 2**64-1, dtypes.float64: float('nan')}) + + t({dtypes.int8: -2**7, dtypes.uint8: 2**7}) + t({dtypes.int16: -2**15, dtypes.uint16: 2**15}) + t({dtypes.int32: -2**31, dtypes.uint32: 2**31}) + t({dtypes.int64: -2**63, dtypes.uint64: 2**63}) + + t({dtypes.int16: 13496, dtypes.uint16: 13496, dtypes.float16: 0.294921875}) + t({dtypes.int32: 1050081145, dtypes.uint32: 1050081145, dtypes.float32: 0.29485681653022766}) + t({dtypes.int64: 4598983288165178391, dtypes.uint64: 4598983288165178391, dtypes.float64: 0.29485681936461233}) + + def test_vec_bitcast(self): + r = full_rewrite_to_sink(UOp.const(dtypes.int32.vec(3), (-1, -2**31, 75)).bitcast(dtypes.uint32.vec(3)).sink()).src[0] + self.assertEqual(r.op, Ops.VECTORIZE) + self.assertEqual(r.dtype, dtypes.uint32.vec(3)) + self.assertEqual(tuple(x.arg for x in r.src), (2**32-1, 2**31, 75)) + +# folds advance indexing into basic indexing +class TestIndexingConstFolding(unittest.TestCase): + def test_scalar_index(self): + t = Tensor.arange(16).float().reshape(1,1,4,4).realize() + # TODO: fold these + _check_ast_count(2, t[:,:,Tensor(1),:]) + _check_ast_count(2, t[:,:,Tensor(1)+2,:]) + _check_ast_count(2, t[:,:,Tensor(1),Tensor(0)]) + + @unittest.expectedFailure + def test_const_tensor_index(self): + # TODO: implement const tensor folded indexing + t = Tensor.arange(16).float().reshape(1,1,4,4).realize() + _check_ast_count(0, t[:,:,Tensor.ones(2,1),:]) + _check_ast_count(0, t[:,:,Tensor.ones(1,2)+2,:]) + _check_ast_count(0, t[:,:,Tensor.ones(1,1),Tensor.zeros(2,1,2)]) + +class TestMovedConstFolding(unittest.TestCase): + def test_add_shrunk_zero(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) + Tensor.zeros(6).shrink(((1, 5),))) + + def test_add_padded_zero(self): + # TODO: it's 1 now, this might be possible to fold + _check_ast_count(1, Tensor([1.0, 2, 3, 4]) + Tensor.zeros(2).pad(((1, 1),))) + + def test_mul_shrunk_one(self): + _check_ast_count(0, Tensor([1.0, 2, 3, 4]) * Tensor.ones(6).shrink(((1, 5),))) + + def test_add_padded_one(self): + _check_ast_count(1, Tensor([1.0, 2, 3, 4]) * Tensor.ones(2).pad(((1, 1),))) + + def test_cast_padded(self): + # NOTE: this is folded due to CAST_BEFORE_VIEW + if is_dtype_supported(dtypes.int16): + _check_ast_count(0, Tensor.ones(4).pad(((1, 1),)).cast(dtypes.int16)) + np.testing.assert_equal(Tensor.ones(4).pad(((1, 1),)).cast(dtypes.int16).numpy(), [0, 1, 1, 1, 1, 0]) + if is_dtype_supported(dtypes.uint16): + _check_ast_count(0, Tensor.full(4, fill_value=-1).pad(((1, 1),)).cast(dtypes.uint16)) + np.testing.assert_equal(Tensor.full(4, fill_value=-1).pad(((1, 1),)).cast(dtypes.uint16).numpy(), [0, 65535, 65535, 65535, 65535, 0]) + # folded + if is_dtype_supported(dtypes.int64): + _check_ast_count(0, Tensor.ones(4).pad(((1, 1),)).cast(dtypes.int64)) + np.testing.assert_equal(Tensor.ones(4).pad(((1, 1),)).cast(dtypes.int64).numpy(), [0, 1, 1, 1, 1, 0]) + +class TestReduceOpsConstFolding(unittest.TestCase): + def test_const_sum(self): + _check_ast_count(0, Tensor.ones(4, 5, 6).sum()) + np.testing.assert_equal(Tensor.ones(4, 5, 6).sum().numpy(), 4 * 5 * 6) + _check_ast_count(0, Tensor.ones(4, 5, 6).sum(axis=0)) + np.testing.assert_equal(Tensor.ones(4, 5, 6).sum(axis=0).numpy(), np.full((5, 6), 4)) + _check_ast_count(0, Tensor(4).sum()) + np.testing.assert_equal(Tensor(4).sum().numpy(), 4) + + def test_padded_const_sum(self): + _check_ast_count(1, Tensor.ones(4).pad(((1, 1),)).sum()) + np.testing.assert_equal(Tensor.ones(4).pad(((1, 1),)).sum().numpy(), 4) + + # NOTE: cannot just count the non-padded area because some Ops f do not have f(0) = 0. + _check_ast_count(1, Tensor.ones(4).pad(((1, 1),)).exp().sum()) + np.testing.assert_allclose(Tensor.ones(4).pad(((1, 1),)).exp().sum().numpy(), 4 * math.e + 2) + + def test_bool_zero_max(self): + _check_ast_count(0, Tensor.full((1, 2), True).shrink(((0, 1), (0, 0))).max((1, 0))) + np.testing.assert_equal(Tensor.full((1, 2), True).shrink(((0, 1), (0, 0))).max((1, 0)).numpy(), False) + + def test_zero_size_ops(self): + for reduceop in [lambda x:x.prod(), lambda x:x.sum()]: # lambda x:x.max() NOTE: numpy gives "reduction operation maximum which has no identity" + _check_ast_count(0, reduceop(Tensor.empty(1, 0))) + np.testing.assert_equal(reduceop(Tensor.empty(shape:=(1, 0))).numpy(), reduceop(np.empty(shape))) + + def test_zero_size_ops_view(self): + for reduceop in [lambda x:x.prod(), lambda x:x.sum()]: + _check_ast_count(0, reduceop(Tensor.empty(1, 0, 4).permute((1, 2, 0)).contiguous())) + np.testing.assert_equal(reduceop(Tensor.empty(shape:=(1, 0))).numpy(), reduceop(np.empty((shape)))) + + def test_zero_size_ops_realized(self): + for reduceop in [lambda x:x.prod(), lambda x:x.sum()]: + _check_ast_count(0, reduceop((Tensor.randn(0, 1)+1).realize())) + np.testing.assert_equal(reduceop((Tensor.randn(shape:=(0, 1))+1).realize()).numpy(), reduceop(np.empty(shape))) + + def test_zero_size_realize_folded(self): + # non contiguous folded output doesn't realize + _check_ast_count(0, Tensor.empty(1, 0).sum()) + # contiguous folded const can still schedule + a = Tensor.empty(1, 0).sum().contiguous() + _check_ast_count(2, a+2) + self.assertIs(a.uop.base.op, Ops.BUFFER) + np.testing.assert_equal((Tensor.empty(1, 0).sum().contiguous()+2).numpy(), 2) + # otherwise we just fuse it + _check_ast_count(1, (Tensor.empty(1, 0).sum()+2).contiguous()) + np.testing.assert_equal((Tensor.empty(1, 0).sum()+2).numpy(), 2) + + def test_const_prod(self): + _check_ast_count(0, Tensor.full((2, 3), fill_value=2).prod()) + np.testing.assert_equal(Tensor.full((2, 3), fill_value=2).prod().numpy(), 2**(2*3)) + _check_ast_count(0, Tensor.full((4, 5, 6), fill_value=2).prod(axis=0)) + np.testing.assert_equal(Tensor.full((4, 5, 6), fill_value=2).prod(axis=0).numpy(), np.full((5, 6), 2**4)) + _check_ast_count(0, Tensor(4).prod()) + np.testing.assert_equal(Tensor(4).prod().numpy(), 4) + + def test_const_max(self): + _check_ast_count(0, Tensor.ones(4, 5, 6).max()) + np.testing.assert_equal(Tensor.ones(4, 5, 6).max().numpy(), 1) + _check_ast_count(0, Tensor(4).max()) + np.testing.assert_equal(Tensor(4).max().numpy(), 4) + + def test_sum_output_dtype(self): + # sum output dtype can be different from input + for dt in dtypes.fields().values(): + if is_dtype_supported(dt): + t = Tensor.ones(16, dtype=dt).reshape(4, 4) + assert t.sum().dtype == t.contiguous().sum().dtype + +@unittest.skipIf(not_support_multi_device(), "no multi") +class TestMultiConstFolding(unittest.TestCase): + def test_multi_const_folding_literal(self): + ds = tuple(f"{Device.DEFAULT}:{i}" for i in range(4)) + t = Tensor.arange(16).float().to(ds).realize() + + # non const folding case creates one ast on each shard + _check_ast_count(4, t + 1) + _check_ast_count(4, 1 + t) + _check_ast_count(4, t * 2) + _check_ast_count(4, 2 * t) + + # const folded + _check_ast_count(0, t + 0) + _check_ast_count(0, 0 + t) + _check_ast_count(0, t * 0) + _check_ast_count(0, 0 * t) + _check_ast_count(0, t * 1) + _check_ast_count(0, 1 * t) + np.testing.assert_equal((t + 0).numpy(), np.arange(16)) + np.testing.assert_equal((t * 0).numpy(), [0] * 16) + np.testing.assert_equal((t * 1).numpy(), np.arange(16)) + + _check_ast_count(0, t ** 0) + _check_ast_count(0, t ** 1) + _check_ast_count(0, 1 ** t) + + def test_multi_const_folding_tensor(self): + ds = tuple(f"{Device.DEFAULT}:{i}" for i in range(4)) + t = Tensor.arange(16).float().to(ds).realize() + zero = Tensor.zeros(16).to(ds).realize() + one = Tensor.ones(16).to(ds).realize() + + # const folded + _check_ast_count(0, t + zero) + _check_ast_count(0, zero + t) + _check_ast_count(0, t * zero) + _check_ast_count(0, zero * t) + _check_ast_count(0, t * one) + _check_ast_count(0, one * t) + np.testing.assert_equal((t + zero).numpy(), np.arange(16)) + np.testing.assert_equal((t * zero).numpy(), [0] * 16) + np.testing.assert_equal((t * one).numpy(), np.arange(16)) + + def test_multi_todo_pow(self): + ds = tuple(f"{Device.DEFAULT}:{i}" for i in range(4)) + t = Tensor.arange(16).float().to(ds).realize() + zero = Tensor.zeros(16).to(ds).realize() + one = Tensor.ones(16).to(ds).realize() + + # TODO: fix pow folding + _check_ast_count(0, t ** zero) + _check_ast_count(0, t ** one) + _check_ast_count(0, one ** t) + +class TestTautologicalCompare(unittest.TestCase): + # without const folding, these would have triggered -Wtautological-compare in clang + def test_lt_false(self): + # bool < False is always false + np.testing.assert_equal((Tensor([True, False]) < False).numpy(), [False, False]) + + def test_true_lt(self): + # True < bool is always false + np.testing.assert_equal((True < Tensor([True, False])).numpy(), [False, False]) + + def test_truth_table(self): + np.testing.assert_equal((Tensor(False) < Tensor(False)).numpy(), False) + np.testing.assert_equal((Tensor(False) < Tensor(True)).numpy(), True) + np.testing.assert_equal((Tensor(True) < Tensor(False)).numpy(), False) + np.testing.assert_equal((Tensor(True) < Tensor(True)).numpy(), False) + + def test_a_eq_a(self): + # self eq is always true for int or bool + a = Tensor([1, 2, 3]) + np.testing.assert_equal((a == a).numpy(), [True, True, True]) + + # not true for nan + a = Tensor([math.nan, 1.0, 2.0]) + np.testing.assert_equal((a == a).numpy(), [False, True, True]) + + def test_a_ne_a(self): + # self not eq is always false for int or bool + a = Tensor([1, 2, 3]) + np.testing.assert_equal((a != a).numpy(), [False, False, False]) + + # not true for nan + a = Tensor([math.nan, 1.0, 2.0]) + np.testing.assert_equal((a != a).numpy(), [True, False, False]) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_copy_speed.py b/tinygrad_repo/test/test_copy_speed.py new file mode 100644 index 000000000..5d0cc69c2 --- /dev/null +++ b/tinygrad_repo/test/test_copy_speed.py @@ -0,0 +1,67 @@ +import unittest +from tinygrad import Tensor +from tinygrad import Device +from tinygrad.helpers import Timing, CI, OSX +import multiprocessing.shared_memory as shared_memory + +N = 4096 +class TestCopySpeed(unittest.TestCase): + @classmethod + def setUpClass(cls): Device[Device.DEFAULT].synchronize() + + def testCopySHMtoDefault(self): + s = shared_memory.SharedMemory(name="test_X", create=True, size=N*N*4) + s.close() + if CI and not OSX: + t = Tensor.empty(N, N, device="disk:/dev/shm/test_X").realize() + else: + t = Tensor.empty(N, N, device="disk:shm:test_X").realize() + for _ in range(3): + with Timing("sync: ", on_exit=lambda ns: f" @ {t.nbytes()/ns:.2f} GB/s"): + with Timing("queue: "): + t.to(Device.DEFAULT).realize() + Device[Device.DEFAULT].synchronize() + s.unlink() + + def testCopyCPUtoDefault(self): + t = Tensor.ones(N, N, device="CPU").contiguous().realize() + print(f"buffer: {t.nbytes()*1e-9:.2f} GB") + for _ in range(3): + with Timing("sync: ", on_exit=lambda ns: f" @ {t.nbytes()/ns:.2f} GB/s"): + with Timing("queue: "): + t.to(Device.DEFAULT).realize() + Device[Device.DEFAULT].synchronize() + + def testCopyCPUtoDefaultFresh(self): + print("fresh copy") + for _ in range(3): + t = Tensor.ones(N, N, device="CPU").contiguous().realize() + with Timing("sync: ", on_exit=lambda ns: f" @ {t.nbytes()/ns:.2f} GB/s"): # noqa: F821 + with Timing("queue: "): + t.to(Device.DEFAULT).realize() + Device[Device.DEFAULT].synchronize() + del t + + def testCopyDefaulttoCPU(self): + t = Tensor.ones(N, N).contiguous().realize() + print(f"buffer: {t.nbytes()*1e-9:.2f} GB") + for _ in range(3): + with Timing("sync: ", on_exit=lambda ns: f" @ {t.nbytes()/ns:.2f} GB/s"): + t.to('CPU').realize() + + @unittest.skipIf(CI, "CI doesn't have 6 GPUs") + @unittest.skipIf(Device.DEFAULT != "GPU", "only test this on GPU") + def testCopyCPUto6GPUs(self): + from tinygrad.runtime.ops_gpu import CLDevice + if len(CLDevice.device_ids) != 6: raise unittest.SkipTest("computer doesn't have 6 GPUs") + t = Tensor.ones(N, N, device="CPU").contiguous().realize() + print(f"buffer: {t.nbytes()*1e-9:.2f} GB") + for _ in range(3): + with Timing("sync: ", on_exit=lambda ns: f" @ {t.nbytes()/ns:.2f} GB/s ({t.nbytes()*6/ns:.2f} GB/s total)"): + with Timing("queue: "): + for g in range(6): + t.to(f"gpu:{g}").realize() + Device["gpu"].synchronize() + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_device_speed.py b/tinygrad_repo/test/test_device_speed.py new file mode 100644 index 000000000..efb790c9f --- /dev/null +++ b/tinygrad_repo/test/test_device_speed.py @@ -0,0 +1,37 @@ +import unittest +from tinygrad import Device +from tinygrad.helpers import Timing, Profiling + +class TestDeviceSpeed(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.dev = Device[Device.DEFAULT] + cls.empty = Device[Device.DEFAULT].renderer.render([]) + + def test_empty_compile(self): + with Timing("compiler "): + self.dev.compiler.compile(self.empty) + + def test_empty_compile_twice(self): + self.dev.compiler.compile(self.empty) + with Timing("compiler "): + self.dev.compiler.compile(self.empty) + + def test_launch_speed(self): + prg_bin = self.dev.compiler.compile(self.empty) + prg = self.dev.runtime("test", prg_bin) + for _ in range(10): prg() # ignore first launches + with Timing("launch 1000x "): + for _ in range(1000): prg() + with Timing("launch 1000x with wait "): + for _ in range(1000): prg(wait=True) + + def test_profile_launch_speed(self): + prg_bin = self.dev.compiler.compile(self.empty) + prg = self.dev.runtime("test", prg_bin) + for _ in range(10): prg() # ignore first launches + with Profiling(): + for _ in range(1000): prg() + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_dtype.py b/tinygrad_repo/test/test_dtype.py new file mode 100644 index 000000000..04a5ac0e8 --- /dev/null +++ b/tinygrad_repo/test/test_dtype.py @@ -0,0 +1,455 @@ +import unittest, math +import numpy as np +import torch +from typing import Any, List +from tinygrad.device import is_dtype_supported +from tinygrad.helpers import getenv, DEBUG, CI +from tinygrad.dtype import DType, DTYPES_DICT, ImageDType, PtrDType, least_upper_dtype, to_dtype, fp8_to_float, float_to_fp8 +from tinygrad import Device, Tensor, dtypes +from tinygrad.tensor import _to_np_dtype +from hypothesis import assume, given, settings, strategies as strat +from test.helpers import rand_for_dtype +from test.unit.test_dtype_spec import _assert_eq, core_dtypes, dtype_ints, dtype_floats, FP8E4M3_MAX, FP8E5M2_MAX +import ml_dtypes +import pytest +pytestmark = pytest.mark.filterwarnings("ignore") + +settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) +settings.load_profile("my_profile") + +if Device.DEFAULT == "CPU": core_dtypes.remove(dtypes.bfloat16) # NOTE: this is for teenygrad, don't remove + +def get_available_cast_dtypes(dtype: DType) -> List[DType]: + if not is_dtype_supported(dtype): return [] + # dont cast internal dtypes + return [v for k, v in DTYPES_DICT.items() if v != dtype and is_dtype_supported(v) and not k.startswith("_")] + +def _test_to_np(a:Tensor, np_dtype, target): + if DEBUG >= 2: print(a) + na = a.numpy() + if DEBUG >= 2: print(na, na.dtype, a.uop.base.realized) + try: + assert na.dtype == np_dtype + np.testing.assert_allclose(na, target) + except AssertionError as e: + raise AssertionError(f"\ntensor {a.numpy()} does not match target {target} with np_dtype {np_dtype}") from e + +def _test_op(fxn, target_dtype:DType, target): + _assert_eq(fxn(), target_dtype, target) +def _test_cast(a:Tensor, target_dtype:DType): + if a.is_floating_point() and dtypes.is_unsigned(target_dtype): + # converting negative float to unsigned integer is undefined + a = a.abs() + if target_dtype == dtypes.half and Device.DEFAULT == "PYTHON": + # TODO: struct.pack cannot pack value > 65504 (max of half) into e format + a = (a > 65504).where(65504, a) + + _test_op(lambda: a.cast(target_dtype), target_dtype, list(a.numpy().astype(_to_np_dtype(target_dtype)))) +def _test_bitcast(a:Tensor, target_dtype:DType, target=None): + if target_dtype == dtypes.bfloat16: raise unittest.SkipTest("no test for bf16 bitcast yet") + if getenv("PTX") and a.dtype == dtypes.int8 and target_dtype.itemsize != a.dtype.itemsize: + raise unittest.SkipTest("shape changing bitcast of int8 broken on PTX") + _test_op(lambda: a.bitcast(target_dtype), target_dtype, target or a.numpy().view(_to_np_dtype(target_dtype)).tolist()) + +class TestDType(unittest.TestCase): + DTYPE: Any = None + DATA: Any = None + @classmethod + def setUpClass(cls): + if not cls.DTYPE or not is_dtype_supported(cls.DTYPE): raise unittest.SkipTest("dtype not supported") + cls.DATA = rand_for_dtype(cls.DTYPE, 10) + def setUp(self): + if self.DTYPE is None: raise unittest.SkipTest("base class") + + def test_to_np(self): + _test_to_np(Tensor(self.DATA, dtype=self.DTYPE), _to_np_dtype(self.DTYPE), np.array(self.DATA, dtype=_to_np_dtype(self.DTYPE))) + + def test_casts_to(self): list(map( + lambda dtype: _test_cast(Tensor(self.DATA, dtype=dtype), self.DTYPE), + get_available_cast_dtypes(self.DTYPE) + )) + def test_casts_from(self): list(map( + lambda dtype: _test_cast(Tensor(self.DATA, dtype=self.DTYPE), dtype), + get_available_cast_dtypes(self.DTYPE) + )) + + def test_same_size_ops(self): + list(map( + lambda dtype: _test_ops(a_dtype=self.DTYPE, b_dtype=dtype) if dtype.itemsize == self.DTYPE.itemsize else None, + get_available_cast_dtypes(self.DTYPE) + )) + def test_upcast_ops(self): + list(map( + lambda dtype: _test_ops(a_dtype=self.DTYPE, b_dtype=dtype) if dtype.itemsize > self.DTYPE.itemsize else None, + get_available_cast_dtypes(self.DTYPE) + )) + def test_upcast_to_ops(self): + list(map( + lambda dtype: _test_ops(a_dtype=dtype, b_dtype=self.DTYPE) if dtype.itemsize < self.DTYPE.itemsize else None, + get_available_cast_dtypes(self.DTYPE) + )) + def test_bitcast(self): + if self.DTYPE == dtypes.bool: raise unittest.SkipTest("no bools in bitcast") + list(map( + lambda dtype: + _test_bitcast(Tensor(self.DATA[:8], dtype=self.DTYPE), dtype) if dtype != dtypes.bool else None, + get_available_cast_dtypes(self.DTYPE) + )) + + def test_dtypes_fields(self): + fields = dtypes.fields() + self.assertIn("float", fields) + self.assertIn("float32", fields) + self.assertEqual(len(fields), 26) + self.assertTrue(all(isinstance(value, DType) for value in fields.values())) + self.assertTrue(all(issubclass(_to_np_dtype(value), np.generic) for value in fields.values() if _to_np_dtype(value) is not None)) + + def test_resulting_and_init_dtypes_match(self): + dtypes = list(map(np.dtype, ["bool", "uint8", "int8", "int16", "int32", "int64", "float32", "float64"])) + data = [1., 2., 0., 0.5, -1.5, 5.25] + for dt in dtypes: + arr = np.asarray(data).astype(dt) + tensor = Tensor(arr) + if not is_dtype_supported(tensor.dtype): continue + tin = tensor.numpy() + tor = torch.as_tensor(arr).detach().numpy() + assert dt == tin.dtype == tor.dtype, f"dtype mismatch: expected={dt} | tinygrad={tin.dtype} | torch={tor.dtype}" + np.testing.assert_allclose(tin, tor, atol=1e-6, rtol=1e-3) + + def test_finfo(self): + if self.DTYPE not in [dtypes.float16, dtypes.bfloat16, dtypes.float32, dtypes.float64]: return + info = np.finfo(_to_np_dtype(self.DTYPE)) + assert info.bits == self.DTYPE.itemsize*8 + assert info.nexp == dtypes.finfo(self.DTYPE)[0] + assert info.nmant == dtypes.finfo(self.DTYPE)[1] + +def _test_ops(a_dtype:DType, b_dtype:DType, target_dtype=None): + target_dtype = target_dtype or least_upper_dtype(a_dtype, b_dtype) + if not is_dtype_supported(a_dtype) or not is_dtype_supported(b_dtype) or not is_dtype_supported(target_dtype): return + if a_dtype == dtypes.bool or b_dtype == dtypes.bool: return + _assert_eq(Tensor([1,2,3,4], dtype=a_dtype)+Tensor([1,2,3,4], dtype=b_dtype), target_dtype, [2,4,6,8]) + _assert_eq((Tensor([1], dtype=a_dtype).cast(b_dtype)+Tensor([1], dtype=a_dtype).cast(b_dtype)).cast(a_dtype), a_dtype, [2]) + _assert_eq(Tensor([1,2,3,4], dtype=a_dtype)*Tensor([1,2,3,4], dtype=b_dtype), target_dtype, [1,4,9,16]) + _assert_eq(Tensor([[1,2],[3,4]], dtype=a_dtype)@Tensor.eye(2, dtype=b_dtype), target_dtype, [[1,2],[3,4]]) + _assert_eq(Tensor([1,1,1,1], dtype=a_dtype)+Tensor.ones((4,4), dtype=b_dtype), target_dtype, 2*Tensor.ones(4,4).numpy()) + +class TestFp8s(unittest.TestCase): + def test_fp8e4m3_creation(self): assert Tensor([-1, 1, 2], dtype=dtypes.fp8e4m3).dtype == dtypes.fp8e4m3 + def test_fp8e5m2_creation(self): assert Tensor([-1, 1, 2], dtype=dtypes.fp8e5m2).dtype == dtypes.fp8e5m2 + +class TestFp8sConversions(unittest.TestCase): + @given(strat.floats(width=32, allow_subnormal=True, allow_nan=False, allow_infinity=False, min_value=-FP8E4M3_MAX, max_value=FP8E4M3_MAX)) + def test_float_to_fp8e4m3(self, x): np.testing.assert_equal(float_to_fp8(x, dtypes.fp8e4m3), ml_dtypes.float8_e4m3fn(x).tobytes()[0]) + + def test_float_to_fp8e4m3_extreme_values(self): + np.testing.assert_equal(float_to_fp8(FP8E4M3_MAX, dtypes.fp8e4m3), 126) + np.testing.assert_equal(float_to_fp8(FP8E4M3_MAX*1.01, dtypes.fp8e4m3), 126) + np.testing.assert_equal(float_to_fp8(math.inf, dtypes.fp8e4m3), 126) + np.testing.assert_equal(float_to_fp8(-FP8E4M3_MAX, dtypes.fp8e4m3), 254) + np.testing.assert_equal(float_to_fp8(-FP8E4M3_MAX*1.01, dtypes.fp8e4m3), 254) + np.testing.assert_equal(float_to_fp8(-math.inf, dtypes.fp8e4m3), 254) + np.testing.assert_equal(float_to_fp8(math.nan, dtypes.fp8e4m3), 127) + np.testing.assert_equal(float_to_fp8(-math.nan, dtypes.fp8e4m3), 255) + + @given(strat.floats(width=32, allow_subnormal=True, allow_nan=False, allow_infinity=False, min_value=-FP8E5M2_MAX, max_value=FP8E5M2_MAX)) + def test_float_to_fp8e5m2(self, x): np.testing.assert_equal(float_to_fp8(x, dtypes.fp8e5m2), ml_dtypes.float8_e5m2(x).tobytes()[0]) + + def test_float_to_fp8e5m2_extreme_values(self): + np.testing.assert_equal(float_to_fp8(FP8E5M2_MAX, dtypes.fp8e5m2), 123) + np.testing.assert_equal(float_to_fp8(FP8E5M2_MAX*1.01, dtypes.fp8e5m2), 123) + np.testing.assert_equal(float_to_fp8(math.inf, dtypes.fp8e5m2), 123) + np.testing.assert_equal(float_to_fp8(-FP8E5M2_MAX, dtypes.fp8e5m2), 251) + np.testing.assert_equal(float_to_fp8(-FP8E5M2_MAX*1.01, dtypes.fp8e5m2), 251) + np.testing.assert_equal(float_to_fp8(-math.inf, dtypes.fp8e5m2), 251) + np.testing.assert_equal(float_to_fp8(math.nan, dtypes.fp8e5m2), 126) + np.testing.assert_equal(float_to_fp8(-math.nan, dtypes.fp8e5m2), 254) + + @given(strat.integers(min_value=0, max_value=255)) + def test_fp8e4m3_to_float(self, x): np.testing.assert_equal(fp8_to_float(x, dtypes.fp8e4m3), np.uint8(x).view(ml_dtypes.float8_e4m3fn).item()) + + @given(strat.integers(min_value=0, max_value=255)) + def test_fp8e5m2_to_float(self, x): np.testing.assert_equal(fp8_to_float(x, dtypes.fp8e5m2), np.uint8(x).view(ml_dtypes.float8_e5m2).item()) + +@unittest.skipUnless(is_dtype_supported(dtypes.bfloat16), "bfloat16 not supported") +class TestBFloat16(unittest.TestCase): + def test_bf16_creation_numpy(self): + data = [-1, 1, 2] + t = Tensor(data, dtype=dtypes.bfloat16) + assert t.dtype == dtypes.bfloat16 + tnp = t.numpy() + assert tnp.dtype == np.float32 + np.testing.assert_allclose(tnp, np.array(data)) + + def test_bf16_ones(self): + t = Tensor.ones(3, 5, dtype=dtypes.bfloat16) + assert t.dtype == dtypes.bfloat16 + np.testing.assert_allclose(t.numpy(), np.ones((3, 5))) + + def test_bf16_eye(self): + t = Tensor.eye(3, dtype=dtypes.bfloat16) + assert t.dtype == dtypes.bfloat16 + np.testing.assert_allclose(t.numpy(), np.eye(3)) + +@unittest.skipUnless(is_dtype_supported(dtypes.bfloat16), "bfloat16 not supported") +class TestBFloat16DType(unittest.TestCase): + def test_bf16_to_float(self): + _test_cast(Tensor([100000], dtype=dtypes.bfloat16), dtypes.float32) + + def test_float_to_bf16(self): + _test_cast(Tensor([100000], dtype=dtypes.float32), dtypes.bfloat16) + + def test_bf16(self): + t = Tensor([10000, -1, -1000, -10000, 20]).cast(dtypes.bfloat16) + t.realize() + back = t.cast(dtypes.float32) + assert tuple(back.numpy().tolist()) == (9984., -1, -1000, -9984, 20) + +@unittest.skipUnless(is_dtype_supported(dtypes.bfloat16), "bfloat16 not supported") +class TestBFloat16DTypeCast(unittest.TestCase): + def test_f16_to_bf16_conversion(self): + original_tensor = Tensor([1.0, 2.0, 3.0], dtype=dtypes.float16) + converted_tensor = original_tensor.cast(dtypes.bfloat16) + self.assertEqual(converted_tensor.dtype, dtypes.bfloat16) + back_to_float32 = converted_tensor.cast(dtypes.float32) + original_to_float32 = original_tensor.cast(dtypes.float32) + np.testing.assert_allclose(back_to_float32.numpy(), original_to_float32.numpy(), rtol=1e-2, atol=1e-3) + + def test_f16_to_bf16_edge_cases(self): + edge_cases = Tensor([0.0, -0.0, float('inf'), float('-inf'), float('nan')], dtype=dtypes.float16) + converted = edge_cases.cast(dtypes.bfloat16).cast(dtypes.float32) + np.testing.assert_equal(converted.numpy(), edge_cases.cast(dtypes.float32).numpy()) + + def test_f16_to_bf16_range_precision(self): + large_value = Tensor([65504.0], dtype=dtypes.float16) # Max representable in float16 + small_value = Tensor([6.1035e-5], dtype=dtypes.float16) # Smallest positive normal float16 + large_converted = large_value.cast(dtypes.bfloat16).cast(dtypes.float32) + small_converted = small_value.cast(dtypes.bfloat16).cast(dtypes.float32) + np.testing.assert_allclose(large_converted.numpy(), large_value.cast(dtypes.float32).numpy(), rtol=1e-2, atol=1e-3) + np.testing.assert_equal(small_converted.numpy(), small_value.cast(dtypes.float32).numpy()) + + def test_f16_to_bf16_randomized(self): + np.random.seed(42) # For reproducibility + random_values = Tensor(np.random.uniform(-65504, 65504, 1000), dtype=dtypes.float16) + converted = random_values.cast(dtypes.bfloat16).cast(dtypes.float32) + np.testing.assert_allclose(converted.numpy(), random_values.cast(dtypes.float32).numpy(), rtol=1e-2, atol=1e-3) + +class TestHalfDType(TestDType): DTYPE = dtypes.half + +class TestFloatDType(TestDType): + DTYPE = dtypes.float + + def test_float_to_uint(self): + _test_op(lambda: Tensor([-0.9, -0.3, 1.2], dtype=dtypes.float32).cast(dtypes.uint32), dtypes.uint32, + [0, 0, 1]) + +class TestDoubleDType(TestDType): + DTYPE = dtypes.double + @unittest.skipIf((CI and Device.DEFAULT in {"CUDA", "NV"}) or getenv("PTX"), "conversion not supported on CI CUDA and PTX") # TODO: why not? + def test_float64_increased_precision(self): + for func in [ + lambda t: t.exp(), + lambda t: t.exp2(), + lambda t: t.log(), + lambda t: t.log2(), + lambda t: t.sqrt(), + lambda t: t.rsqrt(), + lambda t: t.sin(), + lambda t: t.cos(), + lambda t: t.tan(), + lambda t: t.sigmoid(), + ]: + a = [2, 3, 4] + np.testing.assert_allclose(func(Tensor(a, dtype=self.DTYPE)).numpy(), func(torch.tensor(a, dtype=torch.float64)), rtol=1e-12, atol=1e-12) + + def test_float64_to_float32_cast_inf(self): + _test_op(lambda: Tensor([3.4e40, 3.4e38, 1, 0], dtype=dtypes.float64).cast(dtypes.float32), + dtypes.float32, [float('inf'), 3.4e38, 1, 0]) + + +class TestInt8DType(TestDType): + DTYPE = dtypes.int8 + @unittest.skipIf(getenv("CUDA",0)==1 or getenv("PTX", 0)==1, "cuda saturation works differently") + def test_int8_to_uint8_negative(self): + _test_op(lambda: Tensor([-1, -2, -3, -4], dtype=dtypes.int8).cast(dtypes.uint8), dtypes.uint8, [255, 254, 253, 252]) + + def test_int8_to_uint16_negative(self): + _test_op(lambda: Tensor([-1, -2, -3, -4], dtype=dtypes.int8).cast(dtypes.uint16), dtypes.uint16, [2**16-1, 2**16-2, 2**16-3, 2**16-4]) + + @unittest.skipIf(getenv("PTX"), "broken in ptx") + def test_bitcast_alt(self): + a = Tensor([72, -90, 27, 40, -53, 70, 96, 51], dtype=dtypes.int8).bitcast(dtypes.short) + self.assertListEqual(a.tolist(), [-22968, 10267, 18123, 13152]) + +class TestUint8DType(TestDType): + DTYPE = dtypes.uint8 + @unittest.skipIf(getenv("CUDA",0)==1 or getenv("PTX", 0)==1, "cuda saturation works differently") + def test_uint8_to_int8_overflow(self): + _test_op(lambda: Tensor([255, 254, 253, 252], dtype=dtypes.uint8).cast(dtypes.int8), dtypes.int8, [-1, -2, -3, -4]) + +@unittest.skipIf(Device.DEFAULT == "WEBGL", "No bitcast on WebGL") +class TestBitCast(unittest.TestCase): + @given(strat.sampled_from(dtype_ints + dtype_floats), strat.sampled_from(dtype_ints + dtype_floats)) + def test_shape_change_bitcast(self, dt1, dt2): + # NOTE: this has to be assume to prevent hypothesis from skipping all samples + assume(dt2 != dtypes.bfloat16 and dt1 != dtypes.bfloat16) # no test for bf16 bitcast yet + assume(not (getenv("PTX") and dt1 == dtypes.int8)) # TODO: bitcasting int8 fails in PTX + data = rand_for_dtype(dt1, 32).reshape(2, 2, 8) + _test_op(lambda: Tensor(data, dtype=dt1).bitcast(dt2), dt2, data.view(_to_np_dtype(dt2)).tolist()) + + def test_shape_change_bitcast_exceptions(self): + with self.assertRaises(RuntimeError): + # should fail because 3 int8 is 3 bytes but float16 is two and 3 isn't a multiple of 2 + Tensor.empty((3,), dtype=dtypes.int8).bitcast(dtypes.float16) + + with self.assertRaises(RuntimeError): + # should fail because backprop through bitcast is undefined + Tensor.empty((4,), dtype=dtypes.int8, requires_grad=True).bitcast(dtypes.float16) + + def test_bitcast_float_to_int32(self): + a = Tensor([1.,2,3]) + b = a.bitcast(dtypes.int32) + assert b.numpy()[0] == 0x3f800000 + + def test_bitcast_upcasted(self): + a = Tensor.zeros(100, 4, dtype=dtypes.int32).contiguous() + 0x3f800000 + b = a.bitcast(dtypes.float32) + assert b.numpy()[0,0] == 1. + +class TestInt16DType(TestDType): DTYPE = dtypes.int16 + +class TestUint16DType(TestDType): + DTYPE = dtypes.uint16 + + def test_uint16_to_int8_overflow(self): + _test_op(lambda: Tensor([2**16-1, 2**16-2, 1, 0], dtype=dtypes.uint16).cast(dtypes.int8), dtypes.int8, [-1, -2, 1, 0]) + +class TestInt32DType(TestDType): DTYPE = dtypes.int32 +class TestUint32DType(TestDType): DTYPE = dtypes.uint32 + +class TestInt64DType(TestDType): DTYPE = dtypes.int64 +class TestUint64DType(TestDType): + DTYPE = dtypes.uint64 + def test_uint64_load(self): + assert Tensor(2**64 - 1, dtype=dtypes.uint64).numpy() == 2**64 - 1 + +class TestBoolDType(TestDType): DTYPE = dtypes.bool + +class TestPtrDType(unittest.TestCase): + def test_vec_double(self): + dt1 = dtypes.float.vec(4).ptr().vec(4) + dt2 = dtypes.float.vec(4).ptr().vec(4) + self.assertEqual(dt1, dt2) + self.assertEqual(str(dt1), str(dt2)) + + def test_scalar(self): + dt = dtypes.float.vec(4).ptr().scalar() + self.assertEqual(dt.base, dtypes.float.vec(4)) + + dt = dtypes.float.vec(4).ptr().vec(4).scalar() + self.assertEqual(dt.base, dtypes.float.vec(4)) + + dt = dtypes.float.vec(4).scalar() + self.assertEqual(dt, dtypes.float) + + def test_serialize(self): + dt = dtypes.float.vec(4).ptr().vec(4) + self.assertEqual(dt, eval(str(dt))) + + def test_vec_ptr_sz(self): + dt = dtypes.float.ptr(1024).vec(4) + self.assertEqual(dt, eval(str(dt))) + self.assertEqual(str(dt), "dtypes.float.ptr(1024).vec(4)") + + def test_vcount(self): + dt = dtypes.float.ptr().vec(4) + self.assertEqual(dt.vcount, 4) + self.assertEqual(dt.v, 4) + self.assertEqual(dt.count, 1) + + dt = dtypes.float.vec(4).ptr() + self.assertEqual(dt.vcount, 1) + self.assertEqual(dt.v, 1) + self.assertEqual(dt.count, 4) + + dt = dtypes.float.vec(4).ptr().vec(4) + self.assertEqual(dt.vcount, 4) + self.assertEqual(dt.v, 4) + self.assertEqual(dt.count, 4) + +class TestImageDType(unittest.TestCase): + def test_image_scalar(self): + assert dtypes.imagef((10,10)).base.scalar() == dtypes.float32 + assert dtypes.imageh((10,10)).base.scalar() == dtypes.float32 + def test_image_vec(self): + assert dtypes.imagef((10,10)).base.vec(4) == dtypes.float32.vec(4) + assert dtypes.imageh((10,10)).base.vec(4) == dtypes.float32.vec(4) + +class TestEqStrDType(unittest.TestCase): + def test_image_ne(self): + if ImageDType is None: raise unittest.SkipTest("no ImageDType support") + assert dtypes.float == dtypes.float32, "float doesn't match?" + assert dtypes.imagef((1,2,4)) != dtypes.imageh((1,2,4)), "different image dtype doesn't match" + assert dtypes.imageh((1,2,4)) != dtypes.imageh((1,4,2)), "different shape doesn't match" + assert dtypes.imageh((1,2,4)) == dtypes.imageh((1,2,4)), "same shape matches" + assert isinstance(dtypes.imageh((1,2,4)), ImageDType) + def test_ptr_eq(self): + assert dtypes.float32.ptr() == dtypes.float32.ptr() + assert not (dtypes.float32.ptr() != dtypes.float32.ptr()) + def test_strs(self): + if PtrDType is None: raise unittest.SkipTest("no PtrDType support") + self.assertEqual(str(dtypes.imagef((1,2,4))), "dtypes.imagef((1, 2, 4))") + self.assertEqual(str(dtypes.float32.ptr(16)), "dtypes.float.ptr(16)") + +class TestImplicitFunctionTypeChange(unittest.TestCase): + def test_functions(self): + result = [] + for func in [ + lambda t: t.exp(), + lambda t: t.exp2(), + lambda t: t.log(), + lambda t: t.log2(), + lambda t: t.sqrt(), + lambda t: t.sin(), + ]: + t = func(Tensor([4.0, 3.0])).max() == func(Tensor([4.0, 3.0])) + result.append(t.numpy().sum()) + assert all(result) + +class TestTensorMethod(unittest.TestCase): + @given(strat.sampled_from(core_dtypes)) + def test_abs_diff(self, dt): + if dt == dtypes.bool or not is_dtype_supported(dt): return + a, b = Tensor([2], dtype=dt), Tensor([1], dtype=dt) + ret = (a - b).abs() + np.testing.assert_allclose(ret.numpy(), np.abs(a.numpy()-b.numpy())) + +class TestDtypeUsage(unittest.TestCase): + def test_max_w_alu(self): + for d in dtypes.ints: + if is_dtype_supported(d): + t = Tensor([[1, 2], [3, 4]], dtype=d) + (t*t).max().item() + +class TestToDtype(unittest.TestCase): + def test_dtype_to_dtype(self): + dtype = dtypes.int32 + res = to_dtype(dtype) + self.assertIsInstance(res, DType) + self.assertEqual(res, dtypes.int32) + + def test_str_to_dtype(self): + dtype = "int32" + res = to_dtype(dtype) + self.assertIsInstance(res, DType) + self.assertEqual(res, dtypes.int32) + +@unittest.skipUnless(is_dtype_supported(dtypes.bfloat16), f"no bfloat16 on {Device.DEFAULT}") +class TestOpsBFloat16(unittest.TestCase): + def test_cast(self): + # TODO: helper_test_op breaks in unrelated part + # TODO: wrong output with GPU=1 / PYTHON=1 on mac + data = [60000.0, 70000.0, 80000.0] + np.testing.assert_allclose(Tensor(data).cast("bfloat16").numpy(), torch.tensor(data).type(torch.bfloat16).float().numpy()) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_dtype_alu.py b/tinygrad_repo/test/test_dtype_alu.py new file mode 100644 index 000000000..1b0fa9459 --- /dev/null +++ b/tinygrad_repo/test/test_dtype_alu.py @@ -0,0 +1,212 @@ +import unittest + +from tinygrad import Tensor, dtypes, Device +import operator +import numpy as np +from hypothesis import given, strategies as strat, settings, HealthCheck +from tinygrad.dtype import DType +from tinygrad.helpers import CI, getenv +from tinygrad.engine.realize import run_schedule +from tinygrad.uop.ops import GroupOp +from tinygrad.tensor import _to_np_dtype +from tinygrad.device import is_dtype_supported +import pytest, math +pytestmark = pytest.mark.filterwarnings("ignore") + +settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) +settings.load_profile("my_profile") +print(settings.default) + +dtypes_float = (dtypes.float16, dtypes.float32, dtypes.float64) +dtypes_int = (dtypes.int8, dtypes.int16, dtypes.int32, dtypes.int64, dtypes.uint8, dtypes.uint16, dtypes.uint32, dtypes.uint64) +dtypes_bool = (dtypes.bool,) +binary_operations = [operator.add, operator.sub, operator.mul, operator.lt, operator.eq] + +# TODO: LLVM comparing with nan is incorrect +if Device.DEFAULT == "LLVM" or getenv("AMD_LLVM", 0): + binary_operations.remove(operator.lt) + +integer_binary_operations = binary_operations + [(Tensor.bitwise_xor, np.bitwise_xor), (Tensor.bitwise_and, np.bitwise_and), + (Tensor.bitwise_or, np.bitwise_or), operator.mod] +unary_operations = [(Tensor.exp, np.exp), (Tensor.log, np.log), (Tensor.sin, np.sin), + (Tensor.sqrt, np.sqrt), (Tensor.reciprocal, np.reciprocal)] + +# TODO: enable this (this is a dtype issue) +#binary_operations.append(operator.truediv) + +# TODO: (a+b)/2 in tensor.py's maximum can overflow. This requires a new implementation of maximum that can be backpropagated +#binary_operations += [(Tensor.maximum, np.maximum)] + +# TODO: CI CUDA segfaults on sin, WEBGPU sin is not precise enough for large numbers +if (getenv("MOCKGPU") and Device.DEFAULT in {"NV", "CUDA"}) or Device.DEFAULT == "WEBGPU": unary_operations.remove((Tensor.sin, np.sin)) + +class ht: + float64 = strat.floats(width=64, allow_subnormal=False) + float32 = strat.floats(width=32, allow_subnormal=False) + float16 = strat.floats(width=16, allow_subnormal=False) + bfloat16 = strat.floats(width=16, allow_subnormal=False) + uint8 = strat.integers(0, 255) + uint16 = strat.integers(0, 65535) + uint32 = strat.integers(0, 2**32-1) + uint64 = strat.integers(0, 2**64-1) + int8 = strat.integers(-128, 127) + int16 = strat.integers(-32768, 32767) + int32 = strat.integers(-2147483648, 2147483647) + int64 = strat.integers(-9223372036854775808, 9223372036854775807) + bool = strat.booleans() + +def universal_test(a, b, dtype, op): + # The 'nan' cases only fail with Vulkan WebGPU backend (CI) + if (math.isnan(a) or math.isnan(b)) and Device.DEFAULT == "WEBGPU" and CI: return + if not isinstance(op, tuple): op = (op, op) + if op[0] == operator.mod and b == 0: return + ta, tb = Tensor([a], dtype=dtype), Tensor([b], dtype=dtype) + tensor_value = (op[0](ta, tb)).numpy() + numpy_value = op[1](ta.numpy(), tb.numpy()) + if dtype == dtypes.bfloat16: np.testing.assert_allclose(tensor_value, numpy_value, atol=1e-3, rtol=1e-2) + elif dtype in dtypes_float: np.testing.assert_allclose(tensor_value, numpy_value, atol=1e-10) + else: np.testing.assert_equal(tensor_value, numpy_value) + +def universal_test_unary(a, dtype, op): + if not isinstance(op, tuple): op = (op, op) + ta = Tensor([a], dtype=dtype) + out: Tensor = op[0](ta) + sched = out.schedule() + ast = sched[-1].ast + run_schedule(sched) + tensor_value = out.numpy() + numpy_value = op[1](ta.numpy()) + if dtype in (dtypes.float16, dtypes.bfloat16): np.testing.assert_allclose(tensor_value, numpy_value, atol=1e-3, rtol=1e-2) + elif dtype in dtypes_float: np.testing.assert_allclose(tensor_value, numpy_value, atol=1e-6, rtol=1e-5) + else: np.testing.assert_equal(tensor_value, numpy_value) + if op[0] != Tensor.reciprocal: # reciprocal is not supported in most backends + op = [x for x in ast.toposort() if x.op in GroupOp.Unary][0] + assert op.dtype == dtype + +def universal_test_cast(a, in_dtype, dtype): + tensor_value = Tensor([a], dtype=in_dtype).cast(dtype) + numpy_value = np.array([a], dtype=_to_np_dtype(in_dtype)).astype(_to_np_dtype(dtype)) + np.testing.assert_equal(tensor_value.numpy(), numpy_value) + +@unittest.skipIf(Device.DEFAULT == "WEBGPU", "Inf and nan cases are wrong on WebGPU") +def universal_test_midcast(a, b, c, op1, op2, d1:DType, d2:DType): + if not isinstance(op1, tuple): op1 = (op1, op1) + if not isinstance(op2, tuple): op2 = (op2, op2) + at, bt, ct = Tensor([a], dtype=d1), Tensor([b], dtype=d1), Tensor([c], dtype=d2) + an, bn, cn = np.array([a]).astype(_to_np_dtype(d1)), np.array([b]).astype(_to_np_dtype(d1)), np.array([c]).astype(_to_np_dtype(d2)) + tensor_value = op2[0](op1[0](at, bt).cast(d2), ct).numpy() + numpy_value = op2[1](op1[1](an, bn).astype(_to_np_dtype(d2)), cn) + np.testing.assert_allclose(tensor_value, numpy_value, rtol=1e-6 if getenv("PTX") else 1e-7) + +class TestDTypeALU(unittest.TestCase): + @unittest.skipUnless(is_dtype_supported(dtypes.float64, Device.DEFAULT), f"no float64 on {Device.DEFAULT}") + @given(ht.float64, ht.float64, strat.sampled_from(binary_operations)) + def test_float64(self, a, b, op): universal_test(a, b, dtypes.float64, op) + + @given(ht.float32, ht.float32, strat.sampled_from(binary_operations)) + def test_float32(self, a, b, op): universal_test(a, b, dtypes.float32, op) + + @unittest.skipUnless(is_dtype_supported(dtypes.float16, Device.DEFAULT), f"no float16 on {Device.DEFAULT}") + @given(ht.float16, ht.float16, strat.sampled_from(binary_operations)) + def test_float16(self, a, b, op): universal_test(a, b, dtypes.float16, op) + + @unittest.skipUnless(is_dtype_supported(dtypes.bfloat16, Device.DEFAULT), f"no bfloat16 on {Device.DEFAULT}") + @given(ht.bfloat16, ht.bfloat16, strat.sampled_from(binary_operations)) + def test_bfloat16(self, a, b, op): universal_test(a, b, dtypes.bfloat16, op) + + @given(ht.float32, strat.sampled_from(unary_operations)) + def test_float32_unary(self, a, op): universal_test_unary(a, dtypes.float32, op) + + @unittest.skipUnless(is_dtype_supported(dtypes.float16, Device.DEFAULT), f"no float16 on {Device.DEFAULT}") + @given(ht.float16, strat.sampled_from(unary_operations)) + def test_float16_unary(self, a, op): universal_test_unary(a, dtypes.float16, op) + + @unittest.skipUnless(is_dtype_supported(dtypes.bfloat16, Device.DEFAULT), f"no bfloat16 on {Device.DEFAULT}") + @given(ht.bfloat16, strat.sampled_from(unary_operations)) + @unittest.skipIf(Device.DEFAULT in ["AMD"], "broken on AMD?") + def test_bfloat16_unary(self, a, op): universal_test_unary(a, dtypes.bfloat16, op) + + @given(ht.uint8, ht.uint8, strat.sampled_from(integer_binary_operations)) + def test_uint8(self, a, b, op): universal_test(a, b, dtypes.uint8, op) + + @unittest.skipUnless(is_dtype_supported(dtypes.uint16, Device.DEFAULT), f"no uint16 on {Device.DEFAULT}") + @given(ht.uint16, ht.uint16, strat.sampled_from(integer_binary_operations)) + def test_uint16(self, a, b, op): universal_test(a, b, dtypes.uint16, op) + + @unittest.skipUnless(is_dtype_supported(dtypes.uint32, Device.DEFAULT), f"no uint32 on {Device.DEFAULT}") + @given(ht.uint32, ht.uint32, strat.sampled_from(integer_binary_operations)) + def test_uint32(self, a, b, op): universal_test(a, b, dtypes.uint32, op) + + @unittest.skipUnless(is_dtype_supported(dtypes.uint64, Device.DEFAULT), f"no uint64 on {Device.DEFAULT}") + @given(ht.uint64, ht.uint64, strat.sampled_from(integer_binary_operations)) + def test_uint64(self, a, b, op): universal_test(a, b, dtypes.uint64, op) + + @given(ht.int8, ht.int8, strat.sampled_from(integer_binary_operations)) + def test_int8(self, a, b, op): universal_test(a, b, dtypes.int8, op) + + @given(ht.int16, ht.int16, strat.sampled_from(integer_binary_operations)) + def test_int16(self, a, b, op): universal_test(a, b, dtypes.int16, op) + + @given(ht.int32, ht.int32, strat.sampled_from(integer_binary_operations)) + def test_int32(self, a, b, op): universal_test(a, b, dtypes.int32, op) + + @unittest.skipUnless(is_dtype_supported(dtypes.int64, Device.DEFAULT), f"no int64 on {Device.DEFAULT}") + @given(ht.int64, ht.int64, strat.sampled_from(integer_binary_operations)) + def test_int64(self, a, b, op): universal_test(a, b, dtypes.int64, op) + + @given(ht.bool, ht.bool, strat.sampled_from(((operator.add, operator.add), (operator.mul, operator.mul)))) + def test_bool(self, a, b, op): universal_test(a, b, dtypes.bool, op) + + @unittest.skipIf(not CI and Device.DEFAULT == "METAL", "broken on local M3") + @given(ht.int32, ht.int32, ht.float32, strat.sampled_from(integer_binary_operations), strat.sampled_from(binary_operations)) + def test_int32_midcast_float(self, a, b, c, op1, op2): universal_test_midcast(a, b, c, op1, op2, dtypes.int32, dtypes.float32) + + # Metal and CUDA and HIP behave differently than numpy in CI for overflows + skip_overflow = CI and Device.DEFAULT in {"AMD", "NV", "CUDA"} + @given(strat.floats(width=32, min_value=0, max_value=10.0) if skip_overflow else ht.float32, + strat.floats(width=32, min_value=0, max_value=10.0) if skip_overflow else ht.float32, + ht.int32, strat.sampled_from(binary_operations), strat.sampled_from(integer_binary_operations)) + @unittest.skipIf(Device.DEFAULT == "PYTHON", "TODO: fix cast inf to int32 in PYTHON") + def test_float_midcast_int32(self, a, b, c, op1, op2): universal_test_midcast(a, b, c, op1, op2, dtypes.float32, dtypes.int32) + + @unittest.skip("broken. TODO: fix it") + @given(ht.float32, strat.sampled_from(dtypes_float+dtypes_int+dtypes_bool)) + def test_float_cast(self, a, dtype): universal_test_cast(a, dtypes.float32, dtype) + + @unittest.skip("broken. TODO: fix it") + @given(ht.int32, strat.sampled_from(dtypes_float+dtypes_int+dtypes_bool)) + def test_int32_cast(self, a, dtype): universal_test_cast(a, dtypes.int32, dtype) + + @settings(suppress_health_check=[HealthCheck.filter_too_much]) + @given(strat.data(), strat.sampled_from(dtypes_float), strat.sampled_from((dtypes.uint8, dtypes.uint16))) + def test_float_cast_to_unsigned(self, a, float_dtype, unsigned_dtype): + if not is_dtype_supported(float_dtype, Device.DEFAULT): float_dtype = dtypes.float32 + float_strat = {dtypes.float16: ht.float16, dtypes.float32: ht.float32, dtypes.float64: ht.float64}[float_dtype] + float_strat = float_strat.filter(lambda x: 0 < x < dtypes.max(unsigned_dtype)) + universal_test_cast(a.draw(float_strat), float_dtype, unsigned_dtype) + + @settings(suppress_health_check=[HealthCheck.filter_too_much]) + @given(strat.data(), strat.sampled_from(dtypes_float), strat.sampled_from((dtypes.uint8, dtypes.uint16))) + def test_float_cast_to_unsigned_overflow(self, a, float_dtype, unsigned_dtype): + if not is_dtype_supported(float_dtype, Device.DEFAULT): float_dtype = dtypes.float32 + float_strat = {dtypes.float16: ht.float16, dtypes.float32: ht.float32, dtypes.float64: ht.float64}[float_dtype] + overflow_strat = float_strat.filter(lambda x: x > dtypes.max(unsigned_dtype) and x <= dtypes.max(dtypes.int32)) + universal_test_cast(a.draw(overflow_strat), float_dtype, unsigned_dtype) + + @settings(suppress_health_check=[HealthCheck.filter_too_much]) + @given(strat.data(), strat.sampled_from(dtypes_float), strat.sampled_from((dtypes.uint8, dtypes.uint16))) + def test_float_cast_to_unsigned_underflow(self, a, float_dtype, unsigned_dtype): + if not is_dtype_supported(float_dtype, Device.DEFAULT): float_dtype = dtypes.float32 + float_strat = {dtypes.float16: ht.float16, dtypes.float32: ht.float32, dtypes.float64: ht.float64}[float_dtype] + underflow_strat = float_strat.filter(lambda x: x < 0 and x >= dtypes.min(dtypes.int32)) + universal_test_cast(a.draw(underflow_strat), float_dtype, unsigned_dtype) + + @unittest.expectedFailure + def test_unsafe_cast_float_to_int_failure(self): + val = float(dtypes.max(dtypes.int32) - 1) + t1 = Tensor([val], dtype=dtypes.float32).cast(dtypes.int32) + t2 = Tensor(val, dtype=dtypes.float32).cast(dtypes.int32) + np.testing.assert_equal(t1.item(), t2.item()) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_edgecases.py b/tinygrad_repo/test/test_edgecases.py new file mode 100644 index 000000000..001be44e0 --- /dev/null +++ b/tinygrad_repo/test/test_edgecases.py @@ -0,0 +1,301 @@ +# end to end tests of tinygrad that you think might be edge cases. +# using the documentation, write code you think should work. +# you can compare the outputs to torch or numpy, or just tinygrad assert/raise while doing things that should be valid + +# i'm not interested in tests that currently pass, i'm only interested in tests that you think should pass but don't. +# mark them with @unittest.expectedFailure +# all the tests in here didn't pass until bugs were fixed +# get creative! think about things that failed in pytorch or tensorflow for a long time until they were fixed. +# every test should surface a unique bug. if tinygrad throws an error saying something is not supported, this is probably not a bug. +# the tests don't have to test the same parts of the code that these current ones test, more diversity is better + +# focus on making tinygrad throw runtime errors or assertions for valid things, or find clear numerical mismatches from pytorch +# confirm any bugs found are valid by doing the same thing in pytorch in the test. +# for any failing tests, explain in a comment why tinygrad is wrong and what the desired behavior should be. +# don't worry about running mypy or linters. focus on writing more of these tests and running them to confirm broken behavior. +# surface level bugs, like issues with empty tensors, input validation, or nans, are not that interesting. +# focus on bugs that would frustrate real users. + +# these are not bugs, these are desired behavior. don't add failing tests for them: +# tinygrad only accepts tinygrad dtypes or strings of the tinygrad dtype. +# boolean indexing, or anything with unknown output shape of tensor at compile time isn't supported. +# invalid indexing in things like gather and one_hot is not an error in tinygrad. nothing that depends on the value is +# repeat_interleave doesn't support a tensor as the dim. check tinygrad type signature before claiming something is a bug + +import unittest +import numpy as np +import torch +from tinygrad import Tensor, dtypes, nn + +class TestNaNEdgeCases(unittest.TestCase): + # we don't need more of these. it's unclear if torch's behavior is desired here + + @unittest.expectedFailure + def test_max_nan(self): + # Reductions with NaN should propagate NaN like PyTorch. + arr = [1.0, float('nan'), 3.0] + torch_out = torch.tensor(arr).max().item() + out = Tensor(arr).max().numpy() + if np.isnan(torch_out): + self.assertTrue(np.isnan(out)) + else: + np.testing.assert_equal(out, torch_out) + + @unittest.skip("passes on webgpu") + @unittest.expectedFailure + def test_argmax_nan(self): + # PyTorch returns the index of the NaN, tinygrad returns the index of the maximum value. + arr = [1.0, float('nan'), 3.0] + torch_idx = torch.tensor(arr).argmax().item() + idx = Tensor(arr).argmax().item() + self.assertEqual(idx, torch_idx) + + @unittest.expectedFailure + def test_sort_with_nan(self): + # Sorting a tensor containing NaN should keep NaN at the end like PyTorch. + arr = [1.0, float('nan'), 3.0] + torch_vals, torch_idxs = torch.tensor(arr).sort() + vals, idxs = Tensor(arr).sort() + np.testing.assert_equal(vals.numpy(), torch_vals.numpy()) + np.testing.assert_equal(idxs.numpy(), torch_idxs.numpy().astype(np.int32)) + +class TestEmptyTensorEdgeCases(unittest.TestCase): + # we don't need more of these + + @unittest.expectedFailure + def test_sort_empty(self): + # Sorting an empty tensor works in PyTorch and should return empty + # values and indices. tinygrad raises an error instead. + torch_vals, torch_idxs = torch.tensor([]).sort() + values, indices = Tensor([]).sort() + np.testing.assert_equal(values.numpy(), torch_vals.numpy()) + np.testing.assert_equal(indices.numpy(), torch_idxs.numpy().astype(np.int32)) + + @unittest.expectedFailure + def test_max_empty(self): + # Max on an empty tensor should also raise an error. + with self.assertRaises(RuntimeError): + torch.tensor([]).max() + with self.assertRaises(RuntimeError): + Tensor([]).max() + + @unittest.expectedFailure + def test_argmax_empty(self): + # Argmax on an empty tensor should raise an error like torch does. + with self.assertRaises(RuntimeError): + torch.tensor([]).argmax() + with self.assertRaises(RuntimeError): + Tensor([]).argmax() + + @unittest.expectedFailure + def test_masked_select_empty(self): + # Masked select on empty tensors should return an empty tensor. + torch_out = torch.tensor([], dtype=torch.float32).masked_select(torch.tensor([], dtype=torch.bool)) + out = Tensor([], dtype=dtypes.float32).masked_select(Tensor([], dtype=dtypes.bool)) + np.testing.assert_equal(out.numpy(), torch_out.numpy()) + +class TestRollEdgeCases(unittest.TestCase): + # we don't need more of these + + @unittest.expectedFailure + def test_roll_mismatched_dims(self): + with self.assertRaises(RuntimeError): + torch.roll(torch.arange(9).reshape(3, 3), 1, dims=(0, 1)) + with self.assertRaises(RuntimeError): + Tensor.arange(9).reshape(3, 3).roll(1, dims=(0, 1)) + + @unittest.expectedFailure + def test_roll_extra_shift(self): + # tinygrad ignores extra shift values instead of raising + with self.assertRaises(RuntimeError): + torch.roll(torch.arange(10), (1, 2), dims=0) + with self.assertRaises(RuntimeError): + Tensor.arange(10).roll((1, 2), dims=0) + +class TestDropoutProbabilityEdgeCases(unittest.TestCase): + # we don't need more of these + + @unittest.expectedFailure + def test_dropout_rate_one(self): + # out is full of NaNs it should be 0s + with Tensor.train(): + out = Tensor.ones(100).dropout(1.0) + np.testing.assert_allclose(out.numpy(), np.zeros(100)) + + @unittest.expectedFailure + def test_dropout_invalid_prob(self): + # negative dropout probability should raise an error + with self.assertRaises(ValueError): + torch.nn.functional.dropout(torch.ones(10), -0.1, True) + with Tensor.train(): + out = Tensor.ones(10).dropout(-0.1) + np.testing.assert_allclose(out.numpy(), np.ones(10)) + +class TestInputValidation(unittest.TestCase): + # we don't need more of these, input validation bugs are not very interesting, many are WONTFIX + + @unittest.expectedFailure + def test_repeat_negative(self): + # repeating with a negative value should error like PyTorch + with self.assertRaises(RuntimeError): + torch.tensor([1, 2, 3]).repeat(-1, 2) + with self.assertRaises(RuntimeError): + Tensor([1, 2, 3]).repeat(-1, 2) + + @unittest.expectedFailure + def test_negative_weight_decay(self): + with self.assertRaises(ValueError): + torch.optim.AdamW([torch.tensor([1.], requires_grad=True)], lr=0.1, weight_decay=-0.1) + with self.assertRaises(ValueError): + nn.optim.AdamW([Tensor([1.], requires_grad=True)], lr=0.1, weight_decay=-0.1) + + @unittest.expectedFailure + def test_negative_lr(self): + with self.assertRaises(ValueError): + torch.optim.SGD([torch.tensor([1.], requires_grad=True)], lr=-0.1) + with self.assertRaises(ValueError): + nn.optim.SGD([Tensor([1.], requires_grad=True)], lr=-0.1) + + @unittest.expectedFailure + def test_negative_momentum(self): + with self.assertRaises(ValueError): + torch.optim.SGD([torch.tensor([1.], requires_grad=True)], lr=0.1, momentum=-0.1) + with self.assertRaises(ValueError): + nn.optim.SGD([Tensor([1.], requires_grad=True)], lr=0.1, momentum=-0.1) + +class TestZeroFolding(unittest.TestCase): + # we don't need more of these + + # folding rules treat x/x, x//x and x%x as constants even when x can be zero + @unittest.expectedFailure + def test_divide_by_self_with_zero(self): + x = Tensor([0.0, 1.0]) + torch_out = torch.tensor([0.0, 1.0]) / torch.tensor([0.0, 1.0]) + out = (x / x).numpy() + np.testing.assert_allclose(out, torch_out.numpy(), equal_nan=True) + + @unittest.expectedFailure + def test_floordiv_by_self_with_zero(self): + x = Tensor([0]) + with self.assertRaises(RuntimeError): + torch.tensor([0]) // torch.tensor([0]) + with self.assertRaises(RuntimeError): + (x // x).numpy() + + @unittest.expectedFailure + def test_mod_by_self_with_zero(self): + x = Tensor([0]) + with self.assertRaises(RuntimeError): + torch.tensor([0]) % torch.tensor([0]) + with self.assertRaises(RuntimeError): + (x % x).numpy() + +class TestArangeUOpValidationIssue(unittest.TestCase): + # these fail with UOp verification error. + # we don't need more of these involving arange + + @unittest.expectedFailure + def test_large_arange_sum(self): + # Summing a huge arange should either succeed or raise a MemoryError. + n = 2**31 + 3 + expected = (n - 1) * n // 2 + out = Tensor.arange(n).sum().item() + self.assertEqual(out, expected) + + @unittest.expectedFailure + def test_large_arange_index(self): + # Indexing a huge arange should return the correct value instead of failing + # with a UOp verification error. + n = 2**31 + 3 + out = Tensor.arange(n)[0].item() + self.assertEqual(out, 0) + + @unittest.expectedFailure + def test_large_arange_permute(self): + # Permuting a huge tensor should not trigger UOp verification failures. + n = 2**31 + 3 + out = Tensor.arange(n).reshape(n, 1).permute(1, 0) + self.assertEqual(out.shape, (1, n)) + out.realize() + +class TestAssignIssues(unittest.TestCase): + # these are good failures. i'm not sure we need more, but we need to fix these. + + @unittest.expectedFailure + def test_assign_permuted_view_constant(self): + # assigning to a permuted view should modify the underlying tensor + arr = np.arange(6).reshape(2, 3).astype(np.float32) + torch_tensor = torch.tensor(arr) + torch_tensor.t().copy_(torch.tensor([[5.0, 6.0], [7.0, 8.0], [9.0, 10.0]])) + t = Tensor(arr).contiguous().realize() + t.permute(1, 0).assign(Tensor([[5.0, 6.0], [7.0, 8.0], [9.0, 10.0]])) + np.testing.assert_allclose(t.numpy(), torch_tensor.numpy()) + + @unittest.expectedFailure + def test_assign_shrink_view_constant(self): + # assigning to a shrunk view should update the base tensor + arr = np.arange(9).reshape(3, 3).astype(np.float32) + torch_tensor = torch.tensor(arr) + torch_tensor[1:3, 1:3] = torch.ones(2, 2) + t = Tensor(arr).contiguous().realize() + t.shrink(((1, 3), (1, 3))).assign(Tensor.ones(2, 2)) + np.testing.assert_allclose(t.numpy(), torch_tensor.numpy()) + + @unittest.expectedFailure + def test_assign_broadcast(self): + # broadcasting during assign should behave like PyTorch + torch_tensor = torch.zeros(3, 5) + torch_tensor[:] = torch.arange(5) + t = Tensor.zeros(3, 5) + t.assign(Tensor.arange(5)) + np.testing.assert_allclose(t.numpy(), torch_tensor.numpy()) + +class TestUOpValidationIssue(unittest.TestCase): + # these fail with UOp verification error. + # we want more of these with diverse errors! + + @unittest.expectedFailure + def test_tensor_index_overflow(self): + # Advanced indexing on tensors expanded past int32 should not error, but + # tinygrad fails with a UOp verification error. + val = Tensor([1]) + big = val.expand(2**31 + 3) + idx = Tensor([0, 2**31 + 2]) + np.testing.assert_equal(big[idx].numpy(), np.array([1, 1])) + + def test_float_floordiv_scalar(self): + (Tensor.arange(4, dtype=dtypes.float32) // 2).realize() + + def test_float_floordiv_tensor(self): + (Tensor.arange(4, dtype=dtypes.float32) // Tensor.ones(4, dtype=dtypes.float32)).realize() + +class TestEdgeCases(unittest.TestCase): + # add tests exposing new and diverse kinds of bugs that might impact real users here + + @unittest.expectedFailure + def test_circular_pad_negative(self): + # negative pads with circular mode should wrap like PyTorch + arr = np.arange(9).reshape(1, 1, 3, 3).astype(np.float32) + torch_out = torch.nn.functional.pad(torch.tensor(arr), (1, -1, 1, -1), mode='circular') + out = Tensor(arr).pad((1, -1, 1, -1), mode='circular') + np.testing.assert_equal(out.numpy(), torch_out.numpy()) + + @unittest.expectedFailure + def test_arange_float_step(self): + # float steps should match PyTorch exactly + torch_out = torch.arange(0, 2, 0.3).numpy() + out = Tensor.arange(0, 2, 0.3).numpy() + np.testing.assert_allclose(out, torch_out) + + @unittest.skip("this is flaky") + @unittest.expectedFailure + def test_topk_ties_indices(self): + # topk should match PyTorch tie-breaking behavior when values are equal + arr = [1.0, 1.0, 1.0, 1.0] + _, ti = torch.tensor(arr).topk(2) + _, i = Tensor(arr).topk(2) + np.testing.assert_equal(i.numpy(), ti.numpy().astype(np.int32)) + + +if __name__ == "__main__": + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/test_fusion_op.py b/tinygrad_repo/test/test_fusion_op.py new file mode 100644 index 000000000..255479cc4 --- /dev/null +++ b/tinygrad_repo/test/test_fusion_op.py @@ -0,0 +1,68 @@ +import unittest +import time +import numpy as np +from tinygrad import Tensor, dtypes +from tinygrad.engine.realize import lower_schedule_item, run_schedule + +class TestFusionOp(unittest.TestCase): + def test_contiguous_add(self): + def test(contig=False): + bt = Tensor(np.arange(16), dtype=dtypes.float32).reshape(4,4) + x = bt.permute(1,0) + if contig: x = x.contiguous() + return (x.permute(1,0) + bt).data() + assert test() == test(True) + + def test_expand_fuse(self): + bt = Tensor(np.ones((10, 1)), dtype=dtypes.float32) + out = (bt*2).expand(10,10).sum(1) + sched = out.schedule() + run_schedule(sched) + outd = out.tolist() + assert all(x == 20.0 for x in outd) + + def test_recursive_add(self): + st = time.perf_counter() + a = Tensor([1,2,3,4]) + for _ in range(24): a = a + a + sched = a.schedule() + ei = lower_schedule_item(sched[-1]) + self.assertLess(time.perf_counter()-st, 2.0) + assert len(ei.prg.p.src.splitlines()) < 250 + + def test_recursive_add_cmp(self): + st = time.perf_counter() + a = Tensor([1,2,3,4]) + for _ in range(24): a = a + a + sched1 = a.schedule() + b = Tensor([1,2,3,4]) + for _ in range(24): b = b + b + sched2 = b.schedule() + c = Tensor([1,2,3,4]) + for _ in range(23): c = c + c + sched3 = c.schedule() + self.assertEqual(sched1[-1].ast, sched2[-1].ast) + with self.assertRaises(AssertionError): self.assertEqual(sched1[-1].ast, sched3[-1].ast) + self.assertLess(time.perf_counter()-st, 2.0) + + def test_recursive_pad(self): + st = time.perf_counter() + val = 1.0 + a = Tensor(val) + for _ in range(24): a = Tensor.stack(a, a)[0] + sched = a.schedule() + self.assertEqual(len(sched), 1) + self.assertLess(time.perf_counter()-st, 2.0) + + def test_recursive_reshape(self): + st = time.perf_counter() + a = Tensor.empty(32, 32).realize() + b = Tensor.empty(16, 2).realize() + r = a.sum(1) + for _ in range(24): r = r.reshape(16, 2) + b + sched = r.schedule() + self.assertEqual(len(sched), 1) + self.assertLess(time.perf_counter()-st, 2.0) + +if __name__ == '__main__': + unittest.main(verbosity=2) diff --git a/tinygrad_repo/test/test_gc.py b/tinygrad_repo/test/test_gc.py new file mode 100644 index 000000000..faa25a741 --- /dev/null +++ b/tinygrad_repo/test/test_gc.py @@ -0,0 +1,113 @@ +#!/usr/bin/env python +import gc, inspect +import unittest +import numpy as np +from tinygrad.device import Buffer +from tinygrad.engine.realize import run_schedule +from tinygrad.uop.ops import UOp +from tinygrad.tensor import Tensor + +def tensors_allocated(): + gc.collect() + return sum([isinstance(x, Tensor) for x in gc.get_objects()]) + +def bufs_allocated(): + gc.collect() + return sum([isinstance(x, Buffer) for x in gc.get_objects()]) + +class TestGC(unittest.TestCase): + + def test_gc(self): + Tensor.manual_seed(0) + base = tensors_allocated() + a = Tensor.rand(4, 4, requires_grad=True) + b = Tensor.zeros(4, 4, requires_grad=True) + (a*b).mean().backward() + assert (tensors_allocated()-base > 0) + del a,b + assert (tensors_allocated()-base == 2) # one for Tensor._device_rng_counters, and one for Tensor._device_seeds + Tensor.manual_seed(0) + + def test_gc_complex(self): + Tensor.manual_seed(0) + base = tensors_allocated() + a = Tensor(np.zeros((4, 4), dtype=np.float32), requires_grad=True) + b = Tensor.rand(4, 4, requires_grad=True) + assert (tensors_allocated()-base == 4) + (a*b).mean().backward() + assert (tensors_allocated()-base == 6) + del b + assert (tensors_allocated()-base == 4) + b = Tensor(np.zeros((4, 4), dtype=np.float32), requires_grad=True) + print(tensors_allocated()) + (a*b).mean().backward() + print(tensors_allocated()) + assert (tensors_allocated()-base == 6) + del b + assert (tensors_allocated()-base == 4) + Tensor.manual_seed(0) + + def test_schedule_gc(self): + init = bufs_allocated() + x = Tensor.ones(256).contiguous().realize() + y = Tensor.ones(5, 5).contiguous() + y.schedule() + del x + del y + self.assertEqual(bufs_allocated()-init, 0) + + def test_schedule_gc_with_inputs(self): + init = bufs_allocated() + x = Tensor.ones(256).contiguous().realize() + y = x+Tensor.ones(256).contiguous() + ys = y.schedule() + del x + run_schedule(ys) + np.testing.assert_equal(y.numpy(), np.full((256,), 2)) + self.assertEqual(bufs_allocated()-init, 1) + del y + self.assertEqual(bufs_allocated()-init, 0) + + def test_toposort_blocks_gc(self): + init = bufs_allocated() + x = Tensor.ones(4,4).contiguous().realize()+1 + self.assertEqual(bufs_allocated()-init, 1) + # try commenting this part out, it's green! + x.uop.toposort() + del x + if bufs_allocated()-init != 0: + print(inspect.getclosurevars(UOp.toposort().fget)) + raise AssertionError(f"never gced {[x for x in gc.get_objects() if isinstance(x, Buffer)]}") + + def test_buffer_refcount(self): + init = bufs_allocated() + a = Tensor.empty(10) + self.assertEqual(bufs_allocated()-init, 0) + a.realize() + real_buf = a.uop.buffer + # after the Tensor UOp is deleted there shouldn't be any references on the Buffer + self.assertEqual(real_buf.uop_refcount, 1) + self.assertEqual(bufs_allocated()-init, 1) + del a.uop + self.assertEqual(real_buf.uop_refcount, 0) + self.assertEqual(bufs_allocated()-init, 1) # keep the buffer alive + del real_buf + self.assertEqual(bufs_allocated()-init, 0) + + def test_assign_refcount(self): + init = bufs_allocated() + a = Tensor.full((4,), 1.).contiguous() + a.realize() + real_buf = a.uop.buffer + self.assertEqual(real_buf.uop_refcount, 1) + a.assign(Tensor.full((4,), 2.)) + self.assertIs(a.uop.src[0].buffer, real_buf) + # NOTE: this is still 1, we don't count the ASSIGN + self.assertEqual(real_buf.uop_refcount, 1) + a.realize() + del a + self.assertEqual(real_buf.uop_refcount, 0) # no UOps for this Buffer + self.assertEqual(bufs_allocated()-init, 1) # Buffer is alive + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_graph.py b/tinygrad_repo/test/test_graph.py new file mode 100644 index 000000000..19dd6f9fe --- /dev/null +++ b/tinygrad_repo/test/test_graph.py @@ -0,0 +1,261 @@ +import numpy as np +import functools, unittest, ctypes + +from tinygrad.device import Device, Buffer +from tinygrad.tensor import Tensor, _to_np_dtype +from tinygrad.helpers import Context, CI, dedup, from_mv +from tinygrad.dtype import dtypes +from tinygrad.engine.jit import MultiGraphRunner +from tinygrad.engine.realize import ExecItem, BufferXfer, get_runner, CompiledRunner + +np.random.seed(1337) +Tensor.manual_seed(1337) +BUF_SIZE = 4096 if CI else 4096 * 128 +RUN_CNT = 4 if CI else 32 + +cached_prgs = {} +def helper_exec_op(device, outbuf, inbufs): + if (device, len(inbufs)) not in cached_prgs: + with Context(DEBUG=0): + fst = [Tensor.randn(BUF_SIZE, dtype=dtypes.int).realize() for i in range(len(inbufs))] + s = fst[0] + for i in range(1, len(inbufs)): s = s.bitwise_xor(fst[i]) + + si = s.schedule()[-1] + prg = get_runner(device, si.ast) + cached_prgs[(device, len(inbufs))] = prg + + return ExecItem(cached_prgs[(device, len(inbufs))], [outbuf] + inbufs) + +def helper_copy_op(device, dest, src): + prg = BufferXfer(dest.nbytes, device, src.device) + return ExecItem(prg, [dest, src]) + +def helper_alloc_rawbuffer(device, fill=False): + rawbuf = Buffer(device, BUF_SIZE, dtypes.int).ensure_allocated() + if fill: + with Context(DEBUG=0): + data = np.random.randint(-10000, 10000, size=rawbuf.size, dtype=_to_np_dtype(rawbuf.dtype)) + rawbuf.copyin(Tensor(data).realize().uop.base.realized.as_buffer()) + return rawbuf + +def helper_create_offset_rawbuffer(base, offset=0): + x = Buffer(base.device, base.size-offset, base.dtype, base=base, offset=offset) + return x.ensure_allocated() + +def helper_run_jit(jis, bufs, out_buffers): + for rawbuf in out_buffers: + mv = memoryview(bytearray(rawbuf.size * rawbuf.dtype.itemsize)) + ctypes.memset(from_mv(mv), 0, len(mv)) + rawbuf.copyin(mv) + + for ei in jis: ei.run({}, jit=True) + return [rawbuf.as_buffer() for rawbuf in bufs] + +def helper_test_graphs(graph_impl, graphs, runs=RUN_CNT): + reg_ji = [] + bufs = [] + out_buffers = set() + for graph in graphs: + for ji in graph: + out_buffers.update([ji.bufs[i] for i in (ji.prg.p.outs if isinstance(ji.prg, CompiledRunner) else [0])]) + bufs += ji.bufs + reg_ji.append(ji) + bufs = dedup(bufs) + + ground_thruth_bufs = helper_run_jit(reg_ji, bufs, out_buffers) + ground_truth_np = [np.frombuffer(x, _to_np_dtype(bufs[i].dtype)) for i,x in enumerate(ground_thruth_bufs)] + + # Build graphs + gr_ji = [ExecItem(graph_impl(graph, [], {}), []) for graph in graphs] + + for _ in range(runs): + test_bufs = helper_run_jit(gr_ji, bufs, out_buffers) + test_bufs_np = [np.frombuffer(x, _to_np_dtype(bufs[i].dtype)) for i,x in enumerate(test_bufs)] + for i in range(len(ground_thruth_bufs)): np.testing.assert_equal(ground_truth_np[i], test_bufs_np[i]) + +@unittest.skipUnless(Device[Device.DEFAULT].graph is not None, "graph support required") +class TestGraph(unittest.TestCase): + def test_order_2_writes_to_same_buf(self): + d0 = Device.DEFAULT + b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(5)] + + graphs = [ + [helper_exec_op(d0, b0[0], [b0[1], b0[2]]), helper_exec_op(d0, b0[0], [b0[3], b0[4]])] + ] + + helper_test_graphs(Device[d0].graph, graphs) + + def test_order_read_write_same_buf(self): + d0 = Device.DEFAULT + b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(5)] + + graphs = [ + [helper_exec_op(d0, b0[0], [b0[1], b0[2]]), helper_exec_op(d0, b0[1], [b0[3], b0[4]])] + ] + + helper_test_graphs(Device[d0].graph, graphs) + + def test_order_write_read_same_buf(self): + d0 = Device.DEFAULT + b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(5)] + + graphs = [ + [helper_exec_op(d0, b0[0], [b0[1], b0[2]]), helper_exec_op(d0, b0[1], [b0[0], b0[4]])] + ] + + helper_test_graphs(Device[d0].graph, graphs) + + def skip_if_not_multigraph(self): + graph = g.func if isinstance(g:=Device[Device.DEFAULT].graph, functools.partial) else g + if not issubclass(graph, MultiGraphRunner): self.skipTest("graph is not supported (not MultiGraphRunner)") + + def test_order_copy_writed(self): + self.skip_if_not_multigraph() + + d0 = Device.DEFAULT + b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(4)] + + graphs = [ + [helper_exec_op(d0, b0[0], [b0[1], b0[2]]), helper_copy_op(d0, b0[3], b0[0])] + ] + + helper_test_graphs(Device[d0].graph, graphs) + + def test_order_copy_then_read(self): + self.skip_if_not_multigraph() + + d0 = Device.DEFAULT + b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(4)] + + graphs = [ + [helper_copy_op(d0, b0[1], b0[0]), helper_exec_op(d0, b0[3], [b0[1], b0[2]])] + ] + + helper_test_graphs(Device[d0].graph, graphs) + + def test_read_write_several_graphs(self): + d0 = Device.DEFAULT + b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(8)] + + graphs = [ + [helper_exec_op(d0, b0[3], [b0[1], b0[2]])], + [helper_exec_op(d0, b0[4], [b0[1], b0[3]])], + [helper_exec_op(d0, b0[5], [b0[4], b0[2]])] + ] + + helper_test_graphs(Device[d0].graph, graphs) + + graphs = [ + [helper_exec_op(d0, b0[3], [b0[1], b0[2]]), helper_exec_op(d0, b0[4], [b0[1], b0[2]]), helper_exec_op(d0, b0[5], [b0[1], b0[2]])], + [helper_exec_op(d0, b0[2], [b0[6], b0[7]])] + ] + + helper_test_graphs(Device[d0].graph, graphs) + + def test_copies_2_devs(self): + self.skip_if_not_multigraph() + + d0, d1 = Device.DEFAULT, f"{Device.DEFAULT}:1" + b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(3)] + b1 = [helper_alloc_rawbuffer(d1, fill=True) for _ in range(1)] + + graphs = [ + [helper_copy_op(d0, b1[0], b0[0]), helper_exec_op(d0, b0[2], [b0[0], b0[1]])] + ] + + helper_test_graphs(Device[d0].graph, graphs) + + def test_copies_after_graph_global(self): + self.skip_if_not_multigraph() + + d0, d1, d2, d3 = Device.DEFAULT, f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3" + b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(8)] + b1 = [helper_alloc_rawbuffer(d1, fill=True) for _ in range(6)] + b2 = [helper_alloc_rawbuffer(d2, fill=True) for _ in range(6)] + b3 = [helper_alloc_rawbuffer(d3, fill=True) for _ in range(6)] + + graphs = [ + [helper_exec_op(d0, b0[2], [b0[0], b0[1]]), helper_exec_op(d0, b0[3], [b0[0], b0[2]]), helper_exec_op(d0, b0[4], [b0[3], b0[2]]), + helper_exec_op(d0, b0[5], [b0[0], b0[2]]), helper_exec_op(d0, b0[6], [b0[1], b0[2]]), helper_exec_op(d0, b0[7], [b0[0], b0[2]])], + [helper_copy_op(d1, b0[2], b1[0])], + [helper_exec_op(d0, b0[2], [b0[0], b0[1]]), helper_exec_op(d0, b0[3], [b0[0], b0[2]]), helper_exec_op(d0, b0[4], [b0[3], b0[2]]), + helper_exec_op(d0, b0[5], [b0[0], b0[2]]), helper_exec_op(d0, b0[6], [b0[1], b0[2]]), helper_exec_op(d0, b0[7], [b0[0], b0[2]])], + [helper_copy_op(d3, b0[2], b3[0])], + ] + + helper_test_graphs(Device[d0].graph, graphs) + + graphs = [ + [helper_exec_op(d0, b0[2], [b0[0], b0[1]]), helper_exec_op(d0, b0[3], [b0[0], b0[2]]), helper_exec_op(d0, b0[4], [b0[3], b0[2]]), + helper_exec_op(d0, b0[5], [b0[0], b0[2]]), helper_copy_op(d0, b2[0], b0[2]), helper_copy_op(d0, b2[1], b0[5]), + helper_exec_op(d0, b0[7], [b0[0], b0[2]])], + [helper_copy_op(d1, b0[2], b1[0])], + [helper_exec_op(d0, b0[2], [b0[0], b0[1]])], + [helper_copy_op(d3, b0[2], b3[0])], + ] + + helper_test_graphs(Device[d0].graph, graphs) + + graphs = [ + [helper_exec_op(d0, b0[2], [b0[0], b0[1]]), helper_exec_op(d0, b0[3], [b0[0], b0[2]]), helper_exec_op(d0, b0[4], [b0[3], b0[2]]), + helper_exec_op(d0, b0[5], [b0[0], b0[2]]), helper_copy_op(d0, b2[0], b0[2]), helper_copy_op(d0, b2[1], b0[5]), + helper_exec_op(d0, b0[7], [b0[0], b0[2]])], + [helper_copy_op(d1, b0[5], b1[0])], + [helper_copy_op(d3, b0[5], b3[0])], + ] + + helper_test_graphs(Device[d0].graph, graphs) + + graphs = [ + [helper_copy_op(d1, b0[5], b1[0])], + [helper_copy_op(d3, b0[5], b3[0])], + ] + + helper_test_graphs(Device[d0].graph, graphs) + + def test_graph_after_copies_devs(self): + self.skip_if_not_multigraph() + + d0, d1, d2, d3 = Device.DEFAULT, f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3" + b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(8)] + b1 = [helper_alloc_rawbuffer(d1, fill=True) for _ in range(1)] + b2 = [helper_alloc_rawbuffer(d2, fill=True) for _ in range(2)] + b3 = [helper_alloc_rawbuffer(d3, fill=True) for _ in range(2)] + + graphs = [ + [helper_copy_op(d1, b0[0], b1[0])], + [helper_copy_op(d2, b0[1], b2[0]), helper_copy_op(d3, b0[2], b3[0])], + [helper_exec_op(d0, b0[3], [b0[0], b0[2]]), helper_exec_op(d0, b0[4], [b0[3], b0[2]]), + helper_exec_op(d0, b0[5], [b0[0], b0[2]])], + ] + + helper_test_graphs(Device[d0].graph, graphs) + + graphs = [ + [helper_copy_op(d1, b0[0], b1[0])], + [helper_exec_op(d0, b0[2], [b0[0], b0[1]])], + [helper_copy_op(d2, b0[1], b2[0]), helper_copy_op(d3, b0[2], b3[0])], + [helper_exec_op(d0, b0[3], [b0[0], b0[2]]), helper_exec_op(d0, b0[4], [b0[3], b0[2]]), + helper_exec_op(d0, b0[5], [b0[0], b0[2]])], + ] + + helper_test_graphs(Device[d0].graph, graphs) + + def test_graph_offset_bufs(self): + self.skip_if_not_multigraph() + + d0 = Device.DEFAULT + if not hasattr(Device[d0].allocator, "_offset"): self.skipTest("device does not support _offset") + + b0 = [helper_alloc_rawbuffer(d0, fill=True) for _ in range(1)] + b0 += [helper_create_offset_rawbuffer(b0[0]), helper_create_offset_rawbuffer(b0[0])] + + graphs = [ + [helper_copy_op(d0, b0[0], b0[2]), helper_exec_op(d0, b0[1], [b0[0], b0[2]])], + ] + + helper_test_graphs(Device[d0].graph, graphs) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_hcq.py b/tinygrad_repo/test/test_hcq.py new file mode 100644 index 000000000..90a90a7b4 --- /dev/null +++ b/tinygrad_repo/test/test_hcq.py @@ -0,0 +1,539 @@ +import unittest, ctypes, struct, os, random +from tinygrad import Device, Tensor, dtypes +from tinygrad.helpers import getenv, CI, mv_address +from tinygrad.device import Buffer, BufferSpec +from tinygrad.runtime.support.hcq import HCQCompiled, HCQBuffer +from tinygrad.runtime.autogen import libc +from tinygrad.engine.realize import get_runner, CompiledRunner +from tinygrad.opt.kernel import Kernel, Opt, OptOps +from tinygrad import Variable + +MOCKGPU = getenv("MOCKGPU") + +@unittest.skipUnless(issubclass(type(Device[Device.DEFAULT]), HCQCompiled), "HCQ device required to run") +class TestHCQ(unittest.TestCase): + @classmethod + def setUpClass(self): + TestHCQ.d0 = Device[Device.DEFAULT] + TestHCQ.a = Tensor([0.,1.], device=Device.DEFAULT).realize() + TestHCQ.b = self.a + 1 + si = self.b.schedule()[-1] + + TestHCQ.runner = get_runner(TestHCQ.d0.device, si.ast) + TestHCQ.b.uop.buffer.allocate() + + TestHCQ.kernargs_ba_ptr = TestHCQ.runner._prg.fill_kernargs([TestHCQ.b.uop.buffer._buf, TestHCQ.a.uop.buffer._buf]) + TestHCQ.kernargs_ab_ptr = TestHCQ.runner._prg.fill_kernargs([TestHCQ.a.uop.buffer._buf, TestHCQ.b.uop.buffer._buf]) + + def setUp(self): + TestHCQ.d0.synchronize() + TestHCQ.a.uop.buffer.copyin(memoryview(bytearray(struct.pack("ff", 0, 1)))) + TestHCQ.b.uop.buffer.copyin(memoryview(bytearray(struct.pack("ff", 0, 0)))) + TestHCQ.d0.synchronize() # wait for copyins to complete + + # Test signals + def test_signal(self): + for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: + if queue_type is None: continue + + with self.subTest(name=str(queue_type)): + queue_type().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + def test_signal_update(self): + for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: + if queue_type is None: continue + + virt_val = Variable("sig_val", 0, 0xffffffff, dtypes.uint32) + virt_signal = TestHCQ.d0.signal_t(base_buf=HCQBuffer(Variable("sig_addr", 0, 0xffffffffffffffff, dtypes.uint64), 16)) + + with self.subTest(name=str(queue_type)): + q = queue_type().signal(virt_signal, virt_val) + + var_vals = {virt_signal.base_buf.va_addr: TestHCQ.d0.timeline_signal.base_buf.va_addr, virt_val: TestHCQ.d0.timeline_value} + q.submit(TestHCQ.d0, var_vals) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + var_vals = {virt_signal.base_buf.va_addr: TestHCQ.d0.timeline_signal.base_buf.va_addr, virt_val: TestHCQ.d0.timeline_value} + q.submit(TestHCQ.d0, var_vals) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + # Test wait + def test_wait(self): + for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: + if queue_type is None: continue + + with self.subTest(name=str(queue_type)): + fake_signal = TestHCQ.d0.signal_t() + fake_signal.value = 1 + queue_type().wait(fake_signal, 1) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + @unittest.skipIf(MOCKGPU, "Can't handle async update on MOCKGPU for now") + def test_wait_late_set(self): + for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: + if queue_type is None: continue + + with self.subTest(name=str(queue_type)): + fake_signal = TestHCQ.d0.signal_t() + queue_type().wait(fake_signal, 1) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + + with self.assertRaises(RuntimeError): + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value, timeout=500) + + fake_signal.value = 1 + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + + TestHCQ.d0.timeline_value += 1 + + def test_wait_update(self): + for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: + if queue_type is None: continue + + with self.subTest(name=str(queue_type)): + virt_val = Variable("sig_val", 0, 0xffffffff, dtypes.uint32) + virt_signal = TestHCQ.d0.signal_t(base_buf=HCQBuffer(Variable("sig_addr", 0, 0xffffffffffffffff, dtypes.uint64), 16)) + + fake_signal = TestHCQ.d0.signal_t() + q = queue_type().wait(virt_signal, virt_val).signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + + fake_signal.value = 0x30 + + q.submit(TestHCQ.d0, {virt_signal.base_buf.va_addr: fake_signal.base_buf.va_addr, virt_val: fake_signal.value}) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + # Test exec + def test_exec_one_kernel(self): + TestHCQ.d0.hw_compute_queue_t().exec(TestHCQ.runner._prg, TestHCQ.kernargs_ba_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] + assert val == 1.0, f"got val {val}" + + def test_exec_2_kernels_100_times(self): + virt_val = Variable("sig_val", 0, 0xffffffff, dtypes.uint32) + + q = TestHCQ.d0.hw_compute_queue_t() + q.wait(TestHCQ.d0.timeline_signal, virt_val - 1) \ + .exec(TestHCQ.runner._prg, TestHCQ.kernargs_ba_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) \ + .exec(TestHCQ.runner._prg, TestHCQ.kernargs_ab_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) \ + .signal(TestHCQ.d0.timeline_signal, virt_val) + + for _ in range(100): + q.submit(TestHCQ.d0, {virt_val: TestHCQ.d0.timeline_value}) + TestHCQ.d0.timeline_value += 1 + + val = TestHCQ.a.uop.buffer.as_buffer().cast("f")[0] + assert val == 200.0, f"got val {val}" + + def test_exec_update(self): + sint_global = (Variable("sint_global", 0, 0xffffffff, dtypes.uint32),) + tuple(TestHCQ.runner.p.global_size[1:]) + sint_local = (Variable("sint_local", 0, 0xffffffff, dtypes.uint32),) + tuple(TestHCQ.runner.p.local_size[1:]) + + q = TestHCQ.d0.hw_compute_queue_t() + q.exec(TestHCQ.runner._prg, TestHCQ.kernargs_ba_ptr, sint_global, sint_local) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + + q.submit(TestHCQ.d0, {sint_global[0]: 1, sint_local[0]: 1}) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[0] + assert val == 1.0, f"got val {val}" + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] + assert val == 0.0, f"got val {val}, should not be updated" + + def test_exec_update_fuzz(self): + virt_val = Variable("sig_val", 0, 0xffffffff, dtypes.uint32) + virt_local = [Variable(f"local_{i}", 0, 0xffffffff, dtypes.uint32) for i in range(3)] + + a = Tensor.randint((3, 3, 3), dtype=dtypes.int, device=Device.DEFAULT).realize() + b = a + 1 + si = b.schedule()[-1] + k = Kernel(si.ast, opts=TestHCQ.d0.renderer) + for i in range(3): k.apply_opt(Opt(op=OptOps.LOCAL, axis=0, arg=3)) + + runner = CompiledRunner(k.to_program()) + + zb = Buffer(Device.DEFAULT, 3 * 3 * 3, dtypes.int, options=BufferSpec(cpu_access=True, nolru=True)).ensure_allocated() + zt = Buffer(Device.DEFAULT, 3 * 3 * 3, dtypes.int, options=BufferSpec(cpu_access=True, nolru=True)).ensure_allocated() + ctypes.memset(zb._buf.va_addr, 0, zb.nbytes) + kernargs = runner._prg.fill_kernargs([zt._buf, zb._buf]) + + q = TestHCQ.d0.hw_compute_queue_t() + q.memory_barrier() \ + .exec(runner._prg, kernargs, (1,1,1), virt_local) \ + .signal(TestHCQ.d0.timeline_signal, virt_val) + + for x in range(1, 4): + for y in range(1, 4): + for z in range(1, 4): + ctypes.memset(zt._buf.va_addr, 0, zb.nbytes) + + q.submit(TestHCQ.d0, {virt_val: TestHCQ.d0.timeline_value, virt_local[0]: x, virt_local[1]: y, virt_local[2]: z}) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + res_sum = sum(x for x in zt.as_buffer().cast("I")) + assert x * y * z == res_sum, f"want {x * y * z}, got {res_sum}" + + # Test copy + def test_copy(self): + if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") + + TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ + .copy(TestHCQ.b.uop.buffer._buf.va_addr, TestHCQ.a.uop.buffer._buf.va_addr, 8) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] + assert val == 1.0, f"got val {val}" + + def test_copy_long(self): + if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") + + sz = 64 << 20 + buf1 = Buffer(Device.DEFAULT, sz, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() + buf2 = Buffer(Device.DEFAULT, sz, dtypes.int8, options=BufferSpec(host=True, nolru=True)).ensure_allocated() + ctypes.memset(buf2._buf.va_addr, 1, sz) + + TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ + .copy(buf1._buf.va_addr, buf2._buf.va_addr, sz) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + mv_buf1 = buf1.as_buffer().cast('Q') + assert libc.memcmp(mv_address(mv_buf1), buf2._buf.va_addr, sz) == 0 + + @unittest.skipIf(CI, "skip in CI") + def test_copy_64bit(self): + if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") + + for sz in [(1 << 32) - 1, (1 << 32), (1 << 32) + 1, (5 << 30), (6 << 30) - 0x4642ee1]: + buf1 = Buffer(Device.DEFAULT, sz, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() + buf2 = Buffer(Device.DEFAULT, sz, dtypes.int8, options=BufferSpec(host=True, nolru=True)).ensure_allocated() + + ctypes.memset(buf2._buf.va_addr, 0x3e, sz) + buf2_q_view = buf2._buf.cpu_view().view(fmt='Q') + for i in range(0, sz//8, 0x1000): + for j in range(32): buf2_q_view[min(max(i + j - 16, 0), (sz // 8) - 1)] = random.randint(0, 0xffffffffffffffff) + + TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ + .copy(buf1._buf.va_addr, buf2._buf.va_addr, sz) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + mv_buf1 = buf1.as_buffer() + assert libc.memcmp(mv_address(mv_buf1), buf2._buf.va_addr, sz) == 0 + + def test_update_copy(self): + if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") + + virt_src_addr = Variable("virt_src_addr", 0, 0xffffffffffffffff, dtypes.uint64) + virt_dest_addr = Variable("virt_dest_addr", 0, 0xffffffffffffffff, dtypes.uint64) + + q = TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ + .copy(virt_dest_addr, virt_src_addr, 8) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + + q.submit(TestHCQ.d0, {virt_src_addr: TestHCQ.a.uop.buffer._buf.va_addr, virt_dest_addr: TestHCQ.b.uop.buffer._buf.va_addr}) + + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + val = TestHCQ.b.uop.buffer.as_buffer().cast("f")[1] + assert val == 1.0, f"got val {val}" + + def test_update_copy_long(self): + if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") + + virt_src_addr = Variable("virt_src_addr", 0, 0xffffffffffffffff, dtypes.uint64) + virt_dest_addr = Variable("virt_dest_addr", 0, 0xffffffffffffffff, dtypes.uint64) + + sz = 64 << 20 + buf1 = Buffer(Device.DEFAULT, sz, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() + buf2 = Buffer(Device.DEFAULT, sz, dtypes.int8, options=BufferSpec(host=True, nolru=True)).ensure_allocated() + ctypes.memset(buf2._buf.va_addr, 1, sz) + + q = TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ + .copy(virt_dest_addr, virt_src_addr, sz) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + + q.submit(TestHCQ.d0, {virt_src_addr: buf2._buf.va_addr, virt_dest_addr: buf1._buf.va_addr}) + + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + mv_buf1 = buf1.as_buffer().cast('Q') + for i in range(sz//8): assert mv_buf1[i] == 0x0101010101010101, f"offset {i*8} differs, not all copied, got {hex(mv_buf1[i])}" + + # Test bind api + def test_bind(self): + for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: + if queue_type is None: continue + + virt_val = Variable("sig_val", 0, 0xffffffff, dtypes.uint32) + virt_signal = TestHCQ.d0.signal_t(base_buf=HCQBuffer(Variable("sig_addr", 0, 0xffffffffffffffff, dtypes.uint64), 16)) + + with self.subTest(name=str(queue_type)): + fake_signal = TestHCQ.d0.signal_t() + q = queue_type().wait(virt_signal, virt_val).signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value) + q.bind(TestHCQ.d0) + + fake_signal.value = 0x30 + + q.submit(TestHCQ.d0, {virt_signal.base_buf.va_addr: fake_signal.base_buf.va_addr, virt_val: fake_signal.value}) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + # Test multidevice + def test_multidevice_signal_wait(self): + if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") + + try: d1 = Device[f"{Device.DEFAULT}:1"] + except Exception: self.skipTest("no multidevice, test skipped") + + TestHCQ.d0.hw_copy_queue_t().signal(sig:=TestHCQ.d0.signal_t(value=0), value=0xfff) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + + d1.hw_copy_queue_t().wait(sig, value=0xfff) \ + .signal(d1.timeline_signal, d1.timeline_value).submit(d1) + + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + d1.timeline_signal.wait(d1.timeline_value) + d1.timeline_value += 1 + + # Test profile api + def test_speed_exec_time(self): + sig_st, sig_en = TestHCQ.d0.signal_t(), TestHCQ.d0.signal_t() + TestHCQ.d0.hw_compute_queue_t().timestamp(sig_st) \ + .exec(TestHCQ.runner._prg, TestHCQ.kernargs_ba_ptr, TestHCQ.runner.p.global_size, TestHCQ.runner.p.local_size) \ + .timestamp(sig_en) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + et = float(sig_en.timestamp - sig_st.timestamp) + + print(f"exec kernel time: {et:.2f} us") + assert 0.1 <= et <= (15000 if MOCKGPU else 100) + + def test_speed_copy_bandwidth(self): + if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") + + # THEORY: the bandwidth is low here because it's only using one SDMA queue. I suspect it's more stable like this at least. + SZ = 200_000_000 + a = Buffer(Device.DEFAULT, SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() + b = Buffer(Device.DEFAULT, SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() + + sig_st, sig_en = TestHCQ.d0.signal_t(), TestHCQ.d0.signal_t() + TestHCQ.d0.hw_copy_queue_t().timestamp(sig_st) \ + .copy(a._buf.va_addr, b._buf.va_addr, SZ) \ + .timestamp(sig_en) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + et = float(sig_en.timestamp - sig_st.timestamp) + et_ms = et / 1e3 + + gb_s = ((SZ / 1e9) / et_ms) * 1e3 + print(f"same device copy: {et_ms:.2f} ms, {gb_s:.2f} GB/s") + assert (0.2 if MOCKGPU else 10) <= gb_s <= 1000 + + def test_speed_cross_device_copy_bandwidth(self): + if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") + + try: _ = Device[f"{Device.DEFAULT}:1"] + except Exception: self.skipTest("no multidevice, test skipped") + + SZ = 200_000_000 + b = Buffer(f"{Device.DEFAULT}:1", SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() + a = Buffer(Device.DEFAULT, SZ, dtypes.uint8, options=BufferSpec(nolru=True)).allocate() + TestHCQ.d0.allocator.map(b._buf) + + sig_st, sig_en = TestHCQ.d0.signal_t(), TestHCQ.d0.signal_t() + TestHCQ.d0.hw_copy_queue_t().timestamp(sig_st) \ + .copy(a._buf.va_addr, b._buf.va_addr, SZ) \ + .timestamp(sig_en) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + et = float(sig_en.timestamp - sig_st.timestamp) + et_ms = et / 1e3 + + gb_s = ((SZ / 1e9) / et_ms) * 1e3 + print(f"cross device copy: {et_ms:.2f} ms, {gb_s:.2f} GB/s") + assert (0.2 if MOCKGPU else 2) <= gb_s <= 100 + + def test_timeline_signal_rollover(self): + for queue_type in [TestHCQ.d0.hw_compute_queue_t, TestHCQ.d0.hw_copy_queue_t]: + if queue_type is None: continue + + with self.subTest(name=str(queue_type)): + TestHCQ.d0.timeline_value = (1 << 32) - 20 # close value to reset + queue_type().signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1).submit(TestHCQ.d0) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value - 1) + + for _ in range(40): + queue_type().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0.timeline_value += 1 + TestHCQ.d0.synchronize() + + def test_small_copies_from_host_buf(self): + if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") + + buf1 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() + buf2 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(host=True, nolru=True)).ensure_allocated() + + for i in range(256): + ctypes.memset(buf2._buf.va_addr, i, 1) + + TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ + .copy(buf1._buf.va_addr, buf2._buf.va_addr, 1) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + assert buf1.as_buffer()[0] == i + + def test_small_copies_from_host_buf_intercopy(self): + if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") + + buf1 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() + buf2 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() + buf3 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(host=True, nolru=True)).ensure_allocated() + + for i in range(256): + ctypes.memset(buf3._buf.va_addr, i, 1) + + TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ + .copy(buf1._buf.va_addr, buf3._buf.va_addr, 1) \ + .copy(buf2._buf.va_addr, buf1._buf.va_addr, 1) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + assert buf2.as_buffer()[0] == i + + def test_small_copies_from_host_buf_transfer(self): + if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") + + try: _ = Device[f"{Device.DEFAULT}:1"] + except Exception: self.skipTest("no multidevice, test skipped") + + buf1 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() + buf2 = Buffer(f"{Device.DEFAULT}:1", 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() + buf3 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(host=True, nolru=True)).ensure_allocated() + TestHCQ.d0.allocator.map(buf2._buf) + + for i in range(256): + ctypes.memset(buf3._buf.va_addr, i, 1) + + TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ + .copy(buf1._buf.va_addr, buf3._buf.va_addr, 1) \ + .copy(buf2._buf.va_addr, buf1._buf.va_addr, 1) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + assert buf2.as_buffer()[0] == i + + def test_memory_barrier(self): + a = Tensor([0, 1], device=Device.DEFAULT, dtype=dtypes.int8).realize() + b = a + 1 + runner = get_runner(TestHCQ.d0.device, b.schedule()[-1].ast) + + buf1 = Buffer(Device.DEFAULT, 2, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() + buf2 = Buffer(Device.DEFAULT, 2, dtypes.int8, options=BufferSpec(cpu_access=True, nolru=True)).ensure_allocated() + + kernargs_ptr = runner._prg.fill_kernargs([buf1._buf, buf2._buf]) + + for i in range(255): + ctypes.memset(buf2._buf.va_addr, i, 2) + + # Need memory_barrier after direct write to vram + TestHCQ.d0.hw_compute_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ + .memory_barrier() \ + .exec(runner._prg, kernargs_ptr, runner.p.global_size, runner.p.local_size) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + assert buf1.as_buffer()[0] == (i + 1), f"has {buf1.as_buffer()[0]}, need {i + 1}" + + def test_memory_barrier_before_copy(self): + if TestHCQ.d0.hw_copy_queue_t is None: self.skipTest("device does not support copy queue") + + buf1 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() + buf2 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(nolru=True)).ensure_allocated() + buf3 = Buffer(Device.DEFAULT, 1, dtypes.int8, options=BufferSpec(cpu_access=True, nolru=True)).ensure_allocated() + + for i in range(256): + ctypes.memset(buf3._buf.va_addr, i, 1) + + # Need memory_barrier after direct write to vram + TestHCQ.d0.hw_compute_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ + .memory_barrier() \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0.timeline_value += 1 + + TestHCQ.d0.hw_copy_queue_t().wait(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value - 1) \ + .copy(buf1._buf.va_addr, buf3._buf.va_addr, 1) \ + .copy(buf2._buf.va_addr, buf1._buf.va_addr, 1) \ + .signal(TestHCQ.d0.timeline_signal, TestHCQ.d0.timeline_value).submit(TestHCQ.d0) + TestHCQ.d0.timeline_signal.wait(TestHCQ.d0.timeline_value) + TestHCQ.d0.timeline_value += 1 + + assert buf2.as_buffer()[0] == i + + @unittest.skipUnless(MOCKGPU, "Emulate this on MOCKGPU to check the path in CI") + def test_on_device_hang(self): + if not hasattr(self.d0, 'on_device_hang'): self.skipTest("device does not have on_device_hang") + + os.environ["MOCKGPU_EMU_FAULTADDR"] = "0xDEADBEE1" + + # Check api calls + with self.assertRaises(RuntimeError) as ctx: + self.d0.on_device_hang() + + assert "0xDEADBEE1" in str(ctx.exception) + os.environ.pop("MOCKGPU_EMU_FAULTADDR") + + def test_multidevice(self): + try: amd_dev = Device["AMD"] + except Exception: self.skipTest("no AMD device, test skipped") + + try: nv_dev = Device["NV"] + except Exception: self.skipTest("no NV device, test skipped") + + x = amd_dev.signal_t() + y = nv_dev.signal_t() + assert type(x) is amd_dev.signal_t + assert type(y) is nv_dev.signal_t + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/test_hcq_iface.py b/tinygrad_repo/test/test_hcq_iface.py new file mode 100644 index 000000000..bf32bf637 --- /dev/null +++ b/tinygrad_repo/test/test_hcq_iface.py @@ -0,0 +1,105 @@ +import unittest, array, time +from tinygrad.helpers import mv_address +from tinygrad.runtime.support.hcq import MMIOInterface +from tinygrad.runtime.support.usb import USBMMIOInterface +from test.mockgpu.usb import MockUSB + +class TestHCQIface(unittest.TestCase): + def setUp(self): + self.size = 4 << 10 + self.buffer = bytearray(self.size) + self.mv = memoryview(self.buffer).cast('I') + self.mmio = MMIOInterface(mv_address(self.mv), self.size, fmt='I') + + def test_getitem_setitem(self): + self.mmio[1] = 0xdeadbeef + self.assertEqual(self.mmio[1], 0xdeadbeef) + values = array.array('I', [10, 20, 30, 40]) + self.mmio[2:6] = values + read_slice = self.mmio[2:6] + # self.assertIsInstance(read_slice, array.array) + self.assertEqual(read_slice, values.tolist()) + self.assertEqual(self.mv[2:6].tolist(), values.tolist()) + + def test_view(self): + full = self.mmio.view() + self.assertEqual(len(full), len(self.mmio)) + self.mmio[0] = 0x12345678 + self.assertEqual(full[0], 0x12345678) + + # offset-only view + self.mmio[1] = 0xdeadbeef + off = self.mmio.view(offset=4) + self.assertEqual(off[0], 0xdeadbeef) + + # offset + size view: write into sub-view and confirm underlying buffer + values = array.array('I', [11, 22, 33]) + sub = self.mmio.view(offset=8, size=12) + sub[:] = values + self.assertEqual(sub[:], values.tolist()) + self.assertEqual(self.mv[2:5].tolist(), values.tolist()) + + def test_speed(self): + start = time.perf_counter() + for i in range(10000): + self.mmio[3:100] = array.array('I', [i] * 97) + _ = self.mmio[3:100] + end = time.perf_counter() + + mvstart = time.perf_counter() + for i in range(10000): + self.mv[3:100] = array.array('I', [i] * 97) + _ = self.mv[3:100].tolist() + mvend = time.perf_counter() + print(f"speed: hcq {end - start:.6f}s vs plain mv {mvend - mvstart:.6f}s") + +class TestUSBMMIOInterface(unittest.TestCase): + def setUp(self): + self.size = 256 + self.buffer = bytearray(self.size) + self.usb = MockUSB(self.buffer) + self.mmio = USBMMIOInterface(self.usb, 0, self.size, fmt='B', pcimem=False) + + def test_getitem_setitem_byte(self): + self.mmio[1] = 0xAB + self.assertEqual(self.mmio[1], 0xAB) + self.assertEqual(self.usb.mem[1], 0xAB) + + def test_slice_getitem_setitem(self): + values = [1, 2, 3, 4] + self.mmio[10:14] = values + raw = self.mmio[10:14] + self.assertIsInstance(raw, bytes) + self.assertEqual(list(raw), values) + self.assertEqual(list(self.usb.mem[10:14]), values) + + def test_view(self): + self.mmio[0] = 5 + view = self.mmio.view(offset=1, size=3) + self.assertEqual(view[0], self.usb.mem[1]) + view[:] = [7, 8, 9] + self.assertEqual(list(self.usb.mem[1:4]), [7, 8, 9]) + full_view = self.mmio.view() + self.assertEqual(len(full_view), len(self.mmio)) + self.mmio[2] = 0xFE + self.assertEqual(full_view[2], 0xFE) + + def test_pcimem_byte(self): + usb2 = MockUSB(bytearray(self.size)) + mmio_pci = USBMMIOInterface(usb2, 0, self.size, fmt='B', pcimem=True) + mmio_pci[3] = 0x11 + self.assertEqual(mmio_pci[3], 0x11) + self.assertEqual(usb2.mem[3], 0x11) + + def test_pcimem_slice(self): + usb3 = MockUSB(bytearray(self.size)) + mmio_pci = USBMMIOInterface(usb3, 0, self.size, fmt='B', pcimem=True) + values = [2, 3, 4] + mmio_pci[4:7] = values + raw = mmio_pci[4:7] + self.assertIsInstance(raw, bytes) + self.assertEqual(list(raw), values) + self.assertEqual([mmio_pci[i] for i in range(4, 7)], values) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/test_image_dtype.py b/tinygrad_repo/test/test_image_dtype.py new file mode 100644 index 000000000..08d2c04c3 --- /dev/null +++ b/tinygrad_repo/test/test_image_dtype.py @@ -0,0 +1,179 @@ +import unittest +import numpy as np +from tinygrad import Device, dtypes, Tensor, Context +from tinygrad.device import LRUAllocator, is_dtype_supported +from tinygrad.dtype import ImageDType +from tinygrad.engine.realize import lower_schedule +from tinygrad.helpers import prod, unwrap +from test.helpers import REAL_DEV + +IMAGE_SUPPORTED_DEVICES = ("QCOM", "GPU") + +@unittest.skipUnless(REAL_DEV in IMAGE_SUPPORTED_DEVICES, "Images not supported") +class TestImageCopy(unittest.TestCase): + def test_image_copyout_1x1(self, img_type=dtypes.imagef): + it = Tensor.arange(4).cast(img_type((1,1,4))).realize() + buf = it.uop.buffer + out = buf.as_buffer() + np.testing.assert_equal(out.cast(it.dtype.fmt).tolist(), np.arange(4)) + + @unittest.skipUnless(is_dtype_supported(dtypes.half, device="PYTHON"), "need half") + def test_imageh_copyout_1x1(self): self.test_image_copyout_1x1(img_type=dtypes.imageh) + + def test_image_numpy_1x1(self, img_type=dtypes.imagef): + it = Tensor.arange(4).cast(img_type((1,1,4))).realize() + np.testing.assert_equal(it.numpy(), np.arange(4)) + def test_imageh_numpy_1x1(self): self.test_image_numpy_1x1(img_type=dtypes.imageh) + + def test_image_copyout_2x3(self): + it = Tensor.arange(2*3*4).cast(dtypes.imagef((2,3,4))).realize() + buf = it.uop.buffer + out = buf.as_buffer() + np.testing.assert_equal(out.cast('f').tolist(), np.arange(2*3*4)) + + def test_image_roundtrip(self): + sz = (4,2,4) + it = Tensor.rand(prod(sz)).cast(dtypes.imagef(sz)).realize() + buf = it.uop.buffer + out = buf.as_buffer() + + it2 = Tensor.rand(prod(sz)).cast(dtypes.imagef(sz)).realize() + buf2 = it2.uop.buffer + buf2.copyin(out) + + assert (it == it2).sum().item() == prod(sz) + +@unittest.skipUnless(REAL_DEV in IMAGE_SUPPORTED_DEVICES, "Images not supported") +class TestImageDType(unittest.TestCase): + def test_image_and_back(self): + data = Tensor.randn(9*27*4).realize() + tst = data.numpy() + it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize() + assert isinstance(it.uop.base.realized.dtype, ImageDType) + np.testing.assert_equal(tst, it.numpy()) + + @unittest.expectedFailure # this isn't supported anymore, CAST to ImageDType stays ImageDType + def test_image_cast_and_back_collapses(self): + data = Tensor.randn(9*27*4).realize() + tst = data.numpy() + it = data.cast(dtypes.imagef((9,27,4))).realize() + # the underlying UOp is identical + self.assertIs(it.uop.base.realized, data.uop.base.realized) + np.testing.assert_equal(tst, it.numpy()) + + def test_image_and_back_wrong_shape(self): + data = Tensor.randn(9*27*4).realize() + tst = data.numpy() + it = data.cast(dtypes.imagef((9,12,4))).realize() + assert not isinstance(it.uop.base.realized.dtype, ImageDType) + np.testing.assert_equal(tst, it.numpy()) + + def test_shrink_load_float(self): + it = Tensor.randn(4).cast(dtypes.imagef((1,1,4))).realize() + imgv = it.numpy() + np.testing.assert_equal(imgv[0:2], it[0:2].numpy()) + + def test_mul_stays_image(self): + # NOTE: contiguous is needed otherwise this folds + it = Tensor.randn(4).cast(dtypes.imagef((1,1,4))).contiguous().realize() + out = (it*2).realize() + assert isinstance(out.uop.base.realized.dtype, ImageDType) + + def test_sum(self): + it = Tensor.rand(8).cast(dtypes.imagef((1,2,4))).realize() + itn = it.numpy() + np.testing.assert_allclose(np.sum(itn), it.sum().numpy(), rtol=1e-6) + + def test_shrink_max(self): + it = Tensor.randn(8).cast(dtypes.imagef((1,2,4))).realize() + imgv = it.numpy() + np.testing.assert_equal(np.maximum(imgv[0:3], 0), it[0:3].relu().numpy()) + + def test_shrink_to_float(self): + it = Tensor.randn(4, 4).cast(dtypes.imagef((1,4,4))).realize() + imgv = it.numpy() + np.testing.assert_equal(np.maximum(imgv[:, 0], 0), it[:, 0].relu().numpy()) + + @unittest.skipUnless(isinstance(Device.default.allocator, LRUAllocator), "Requires LRU") + def test_lru_alloc(self): + data = Tensor.randn(9*27*4).realize() + it = data.cast(dtypes.imagef((9,27,4))).realize() + b1 = it.uop.base.realized._buf + del it + it = data.cast(dtypes.imagef((9,27,4))).realize() + assert it.uop.base.realized._buf == b1 + + def test_no_lru_alloc(self): + data = Tensor.randn(9*27*4).realize() + it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize() + b1 = it.uop.base.realized._buf + del it + it = data.cast(dtypes.imagef((10,27,4))).contiguous().realize() + assert it.uop.base.realized._buf != b1 + + def test_no_lru_alloc_dtype(self): + data = Tensor.randn(9*27*4).realize() + it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize() + b1 = it.uop.base.realized._buf + del it + it = data.cast(dtypes.imageh((9,27,4))).realize() + assert it.uop.base.realized._buf != b1 + + # issue caused by: don't realize image to image casts. this is part of a larger problem + #@unittest.expectedFailure + # update: passing after tensor_map + def test_lil_model(self): + with Context(IMAGE=2): + x = Tensor.zeros(1, 1) + w1 = Tensor.zeros(1, 8, requires_grad=True) + w2 = Tensor.zeros(8, 2) + loss = x.image_dot(w1).image_dot(w2).float().max() + loss.backward() + sched = unwrap(w1.grad).schedule() + for s,(_,ei) in zip(sched, lower_schedule(sched[:])): + ei.run() + if s.bufs[0].dtype == dtypes.float: + lst = s.bufs[0].as_buffer().cast("f").tolist() + print(lst) + assert not np.any(np.isnan(lst)) + # NOTE: the w1 grad must realize to a seperate kernel + assert w1.grad.uop.is_realized, f"never realized {w1.grad}" + self.assertEqual(w1.grad.uop.base.buffer.dtype, dtypes.float32) + self.assertEqual(len(sched), 10) + +@unittest.skipUnless(REAL_DEV in IMAGE_SUPPORTED_DEVICES, "Images not supported") +class TestImageRealization(unittest.TestCase): + def test_image_dtype_expand(self): + data = Tensor.randn(9*27*4).realize() + it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize() + self.assertEqual(it.dtype, dtypes.imagef((9,27,4))) + it_expanded = it.reshape((9,27,4,1)).expand((9,27,4,4)).contiguous().realize() + self.assertEqual(it_expanded.dtype, dtypes.float32) + + def test_image_dtype_expand_and_back(self): + data = Tensor.randn(9*27*4).realize() + it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize() + self.assertEqual(it.dtype, dtypes.imagef((9,27,4))) + it_expanded = it.reshape((9,27,4,1)).expand((9,27,4,4)) + it2 = it_expanded.sum(3).realize() + self.assertEqual(it2.dtype, dtypes.imagef((9,27,4))) + + def test_image_alu_children(self): + data = Tensor.randn(9*27*4).realize() + it = data.cast(dtypes.imagef((9,27,4))).contiguous().realize() + self.assertEqual(it.dtype, dtypes.imagef((9,27,4))) + it_expanded = it.reshape((9,27,4,1)).expand((9,27,4,4)).contiguous() + alu1 = it_expanded+1 + alu2 = it_expanded.sum(3) + it_expanded.realize() + # NOTE: the parent becomes float, but the alu child will stay image until its output cannot fit the image + self.assertEqual(alu1.dtype, dtypes.imagef((9,27,4))) + alu1.realize() + self.assertEqual(alu1.dtype, dtypes.float32) + # alu2 is back in image because it fits the dtype again + self.assertEqual(alu2.dtype, dtypes.imagef((9,27,4))) + alu2.realize() + self.assertEqual(alu2.dtype, dtypes.imagef((9,27,4))) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_interop.py b/tinygrad_repo/test/test_interop.py new file mode 100644 index 000000000..dafe54319 --- /dev/null +++ b/tinygrad_repo/test/test_interop.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python +import unittest +import torch +import numpy as np + +from tinygrad.helpers import getenv, CI +from tinygrad.tensor import Tensor +from tinygrad.device import Device +from tinygrad.dtype import _from_torch_dtype, _to_torch_dtype + +MOCKGPU = getenv("MOCKGPU") + +@unittest.skipIf(Device.DEFAULT not in ["METAL", "CUDA"] or MOCKGPU, f"no support on {Device.DEFAULT}") +class TestInterop(unittest.TestCase): + def setUp(self): + if Device.DEFAULT == "CUDA": self.torch_device = "cuda" + elif Device.DEFAULT == "METAL": self.torch_device = "mps" + + def test_torch_interop(self): + inp = torch.rand(2, 2, 3, device=torch.device(self.torch_device)) + + if self.torch_device == "mps": torch.mps.synchronize() + else: torch.cuda.synchronize() + + tg_data = Tensor.from_blob(inp.data_ptr(), inp.shape, dtype=_from_torch_dtype(inp.dtype)) + + tg_out = tg_data[:, :, 0] * 0.2989 + tg_data[:, :, 1] * 0.5870 + tg_data[:, :, 2] * 0.1140 + tg_res = tg_out.numpy() + + if self.torch_device == "mps" and CI: + # MPS backend out of memory: https://discuss.pytorch.org/t/mps-back-end-out-of-memory-on-github-action/189773 + # Calculate expected value on cpu. + inp = inp.cpu() + torch_out = inp[:, :, 0] * 0.2989 + inp[:, :, 1] * 0.5870 + inp[:, :, 2] * 0.1140 + + np.testing.assert_allclose(tg_res, torch_out.cpu().numpy(), atol=1e-5, rtol=1e-5) + + def test_torch_interop_write(self): + tg_data = Tensor.randn((4, 4), device=Device.DEFAULT) + + out = torch.empty(4, 4, device=torch.device(self.torch_device), dtype=_to_torch_dtype(tg_data.dtype)) + tg_out = Tensor.from_blob(out.data_ptr(), out.shape, dtype=_from_torch_dtype(out.dtype)) + + tg_out.assign(tg_data).realize() + Device[Device.DEFAULT].synchronize() + + torch_out_np = out.cpu().numpy() + + np.testing.assert_allclose(tg_data.numpy(), torch_out_np, atol=1e-5, rtol=1e-5) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_jit.py b/tinygrad_repo/test/test_jit.py new file mode 100644 index 000000000..1b30ffc3b --- /dev/null +++ b/tinygrad_repo/test/test_jit.py @@ -0,0 +1,673 @@ +#!/usr/bin/env python +import unittest, functools +import numpy as np + +from hypothesis import given, settings, strategies as strat +from test.helpers import assert_jit_cache_len, not_support_multi_device, REAL_DEV +from tinygrad.tensor import Tensor +from tinygrad.engine.jit import TinyJit +from tinygrad.device import Device +from tinygrad.helpers import Context, JIT, GlobalCounters +from tinygrad.dtype import dtypes +from extra.models.unet import ResBlock + +def _simple_test(add, extract=lambda x: x, N=10): + for _ in range(5): + a = Tensor.randn(N, N) + b = Tensor.randn(N, N) + c = add(a, b) + np.testing.assert_allclose(extract(c).numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) + assert_jit_cache_len(add, 1) + +class TestJit(unittest.TestCase): + + @settings(deadline=2e4) + @unittest.skipUnless(REAL_DEV in ["LLVM", "CPU"], f"no support on {REAL_DEV}") + @given(strat.sampled_from([Tensor.exp2, Tensor.log2, Tensor.sin])) + def test_approx_jit_timeout(self, op): + with Context(TRANSCENDENTAL=2): + model = [ResBlock(16, 24, 16) for _ in range(4)] + @TinyJit + def fw_approx(t, t2): + for l in model: t = l(t, t2) + return op(t).realize() + fw_approx(Tensor.empty(4, 16, 8, 8), Tensor.empty(1, 24)) + + def test_simple_jit(self): + @TinyJit + def add(a, b): return (a+b).realize() + _simple_test(add) + + def test_simple_jit_reset(self): + @TinyJit + def add(a, b): return (a+b).realize() + _simple_test(add) + add.reset() + _simple_test(add, N=20) + + def test_simple_jit_norealize(self): + @TinyJit + def add(a, b): return (a+b) + _simple_test(add) + + def test_simple_jit_norealize_list(self): + @TinyJit + def add(a, b): return [a+b] + _simple_test(add, extract=lambda x: x[0]) + + def test_simple_jit_norealize_dict(self): + @TinyJit + def add(a, b): return {"billy": a+b} + _simple_test(add, extract=lambda x: x["billy"]) + + def test_jit_multiple_outputs(self): + @TinyJit + def f(a, b): return (a+b).realize(), (a-b).realize(), (a*b).realize() + for _ in range(5): + a = Tensor.randn(10, 10) + b = Tensor.randn(10, 10) + c, d, e = f(a, b) + np.testing.assert_allclose(c.numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) + np.testing.assert_allclose(d.numpy(), a.numpy()-b.numpy(), atol=1e-4, rtol=1e-5) + np.testing.assert_allclose(e.numpy(), a.numpy()*b.numpy(), atol=1e-4, rtol=1e-5) + assert_jit_cache_len(f, 3) + + def test_nothing_jitted(self): + @TinyJit + def add(a, b): return None + with self.assertRaises(AssertionError): + for _ in range(5): + a = Tensor.randn(10, 10) + b = Tensor.randn(10, 10) + add(a, b) + + def test_jit_zero_does_not_jit(self): + @TinyJit + def add(a, b): return (a+b).realize() + with Context(JIT=0): + for i in range(5): + a = Tensor([i]) + b = Tensor([i]) + c = add(a, b) + np.testing.assert_allclose(c.numpy(), 2*i) + assert_jit_cache_len(add, 0) + + def test_jit_not_capturing(self): + @TinyJit + def add(a, b): + Tensor.zeros(4, 4).contiguous().realize() # no-op kernel is captured + return (a+b).realize() + for i in range(5): + a = Tensor([i]) + b = Tensor([i]) + c = add(a, b) + np.testing.assert_allclose(c.numpy(), 2*i) + assert_jit_cache_len(add, 2) + + @TinyJit + def add2(a, b): + with Context(CAPTURING=0): # not captured + Tensor.zeros(4, 4).contiguous().realize() + return (a+b).realize() + for i in range(5): + a = Tensor([i]) + b = Tensor([i]) + c = add2(a, b) + np.testing.assert_allclose(c.numpy(), 2*i) + assert_jit_cache_len(add2, 1) + + def test_jit_shape_mismatch(self): + @TinyJit + def add(a, b): return (a+b).realize() + for _ in range(5): + a = Tensor.randn(10, 10) + b = Tensor.randn(10, 10) + add(a, b) + bad = Tensor.randn(20, 20) + with self.assertRaises(AssertionError): + add(a, bad) + + def test_jit_shape_views_mismatch(self): + @TinyJit + def add(a): return (a+1).realize() + with self.assertRaises(AssertionError): + for i in range(1,5): + # a has an offset that the kernel doesn't know about + a = Tensor.randn(10, 10).realize()[:, i:i+2] + add(a) + + def test_jit_duplicate_fail(self): + # the jit doesn't support duplicate arguments + @TinyJit + def add(a, b): return (a+b).realize() + a = Tensor.randn(10, 10) + with self.assertRaises(AssertionError): + add(a, a) + + def test_jit_assign(self, dtype=dtypes.float32): + @TinyJit + def add(a): + a += 1 + a.realize() + a = Tensor.zeros(1, dtype=dtype).contiguous().realize() + for _ in range(5): add(a) + self.assertEqual(a.item(), 5) + + def test_jit_assign_int8(self): self.test_jit_assign(dtypes.int8) + + def test_kwargs_jit(self): + @TinyJit + def add_kwargs(first, second): return (first+second).realize() + for _ in range(5): + a = Tensor.randn(10, 10) + b = Tensor.randn(10, 10) + c = add_kwargs(first=a, second=b) + np.testing.assert_allclose(c.numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) + assert_jit_cache_len(add_kwargs, 1) + + def test_reorder_kwargs_jit(self): + @TinyJit + def add_kwargs(first, second): return (first/second).realize() + for _ in range(2): + a = Tensor.randn(10, 10) + b = Tensor.randn(10, 10) + c = add_kwargs(second=b, first=a) + np.testing.assert_allclose(c.numpy(), a.numpy()/b.numpy(), atol=1e-4, rtol=1e-5) + for _ in range(2): + a = Tensor.randn(10, 10) + b = Tensor.randn(10, 10) + c = add_kwargs(first=a, second=b) + np.testing.assert_allclose(c.numpy(), a.numpy()/b.numpy(), atol=1e-4, rtol=1e-5) + assert_jit_cache_len(add_kwargs, 1) + + def test_array_jit(self): + @TinyJit + def add_array(a, arr): return (a+arr[0]).realize() + for i in range(5): + a = Tensor.randn(10, 10) + b = Tensor.randn(10, 10) + a.realize(), b.realize() + c = add_array(a, [b]) + if i >= 2: + # should fail once jitted since jit can't handle arrays + np.testing.assert_allclose(np.any(np.not_equal(c.numpy(),a.numpy()+b.numpy())), True, atol=1e-4, rtol=1e-5) + else: + np.testing.assert_allclose(c.numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) + assert_jit_cache_len(add_array, 1) + + def test_jit_copyin(self): + @TinyJit + def f(a): + return a + Tensor([1,2,3]) + for _ in range(5): + b = Tensor.randn(3) + c = f(b) + np.testing.assert_allclose(c.numpy(), b.numpy()+[1,2,3], atol=1e-4, rtol=1e-5) + + def test_method_jit(self): + class Fun: + def __init__(self): + self.a = Tensor.randn(10, 10) + @TinyJit + def __call__(self, b:Tensor) -> Tensor: + return (self.a+b).realize() + fun = Fun() + for _ in range(5): + b = Tensor.randn(10, 10) + c = fun(b) + np.testing.assert_allclose(c.numpy(), fun.a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) + assert_jit_cache_len(fun.__call__.func.__self__, 1) + + def test_jit_size1_input(self): + @TinyJit + def f(a, b): return (a+b).realize() + a = Tensor([1, 2, 3]) + for i in range(5): + np.testing.assert_allclose(f(a, Tensor([i])).numpy(), (a+i).numpy(), atol=1e-4, rtol=1e-5) + assert_jit_cache_len(f, 1) + + def test_jit_output_non_tensor_fail(self): + @TinyJit + def f(a, b, i): return (a+b).realize(), i + output1, output2 = [], [] + expect1, expect2 = [], [] + for i in range(5): + a = Tensor.randn(10, 10) + b = Tensor.randn(10, 10) + o1, o2 = f(a, b, i) + output1.append(o1.numpy().copy()) + output2.append(o2) + expect1.append(a.numpy().copy()+b.numpy().copy()) + expect2.append(i) + np.testing.assert_allclose(output1, expect1, atol=1e-4, rtol=1e-5) + # the jit only works with Tensor outputs + assert output2 != expect2 + assert_jit_cache_len(f, 1) + + def test_jit_random_regen(self): + def f(a, b): + rn = Tensor.randn(*a.shape) + return ((a+b)*rn).realize() + a = Tensor.randn(10, 10).realize() # realize these before resetting the random seed + b = Tensor.randn(10, 10).realize() + + Tensor.manual_seed(1234) + jf = TinyJit(f) + res = set() + for _ in range(5): + o1 = jf(a, b) + res.add(o1.numpy()[0][0]) + assert len(res) == 5, "All values should be different, rand works in jit." + + Tensor.manual_seed(1234) + jf2 = TinyJit(f) + res2 = set() + for _ in range(5): + o1 = jf2(a, b) + res2.add(o1.numpy()[0][0]) + assert len(res2) == 5, "All values should be different, rand works in jit." + assert res == res2, "Jit rand is not reproducible with the same seed" + + Tensor.manual_seed(3421) + jf3 = TinyJit(f) + res3 = set() + for _ in range(5): + o1 = jf3(a, b) + res3.add(o1.numpy()[0][0]) + assert len(res3) == 5, "All values should be different, rand works in jit." + assert res3 != res2, "Jit rand is diff with diff seeds" + + @unittest.expectedFailure # TODO: fix + def test_jit_v_nojit_random_regen(self): + def f(a, b): + rn = Tensor.randn(*a.shape) + rn = rn * a + rn2 = Tensor.randn(*a.shape) + rn2 = rn2 * b + rn = rn + rn2 + rn2 = rn2 + Tensor.randn(*a.shape) + return ((a+b)*rn).realize(), ((a+b)*rn2).realize() + Tensor.manual_seed(0) + a = Tensor.randn(10, 10).realize() # realize these before resetting the random seed + b = Tensor.randn(10, 10).realize() + + Tensor.manual_seed(1234) + without_jit = set() + for _ in range(5): + o1, o2 = f(a, b) + without_jit.add(o1.numpy()[0][0]) + without_jit.add(o2.numpy()[0][0]) + assert len(without_jit) == 10, "All values should be different." + + Tensor.manual_seed(1234) + jf = TinyJit(f) + with_jit = set() + for _ in range(5): + o1, o2 = jf(a, b) + with_jit.add(o1.numpy()[0][0]) + with_jit.add(o2.numpy()[0][0]) + assert len(with_jit) == 10, "All values should be different." + assert with_jit == without_jit, "Jit rand produced different values from no jit." + + def test_jit_multiple_random_regen(self): + def f(a, b): + rn = Tensor.randn(*a.shape) + rn = rn * a + rn2 = Tensor.randn(*a.shape) + rn2 = rn2 * b + rn = rn + rn2 + rn2 = rn2 + Tensor.randn(*a.shape) + return ((a+b)*rn).realize(), ((a+b)*rn2).realize() + a = Tensor.randn(10, 10).realize() # realize these before resetting the random seed + b = Tensor.randn(10, 10).realize() + + Tensor.manual_seed(1234) + jf = TinyJit(f) + res = set() + for _ in range(5): + o1, o2 = jf(a, b) + res.add(o1.numpy()[0][0]) + res.add(o2.numpy()[0][0]) + assert len(res) == 10, "All values should be different, rand works in jit." + + Tensor.manual_seed(1234) + jf2 = TinyJit(f) + res2 = set() + for _ in range(5): + o1, o2 = jf2(a, b) + res2.add(o1.numpy()[0][0]) + res2.add(o2.numpy()[0][0]) + assert len(res2) == 10, "All values should be different, rand works in jit." + assert res == res2, "Jit rand is not reproducible with the same seed" + + Tensor.manual_seed(3421) + jf3 = TinyJit(f) + res3 = set() + for _ in range(5): + o1, o2 = jf3(a, b) + res3.add(o1.numpy()[0][0]) + res3.add(o2.numpy()[0][0]) + assert len(res3) == 10, "All values should be different, rand works in jit." + assert res3 != res2, "Jit rand is diff with diff seeds" + + #@unittest.expectedFailure # requires contiguous folding + def test_jit_random_after_unrealized_random(self): + @TinyJit + def f(): return Tensor.rand() + Tensor.manual_seed(1234) + Tensor.rand() + res = [f().numpy() for _ in range(3)] + assert res[1] != res[2] + + def test_jit_realization_and_sampling(self): + w = Tensor.eye(5) + + @TinyJit + def foo (x): return w.dot(x).realize() + + arg = [ + Tensor([1,2,3,4,5]), + Tensor([1,3,3,4,6]), + Tensor([1,2,5,4,7]), + Tensor([0,2,3,1,0]), + ] + + Y = [foo(e).numpy() for e in arg] + + foo(Tensor([7,7,7,7,7])) + want = [[1., 2., 3., 4., 5.], + [1., 3., 3., 4., 6.], + [1., 2., 5., 4., 7.], + [0., 2., 3., 1., 0.]] + np.testing.assert_allclose(want, Y) + + def test_jit_buffer_behavior(self): + @TinyJit + def foo(x) -> Tensor: return x.sum().realize() + + result_1 = foo(Tensor([1] * 2)) + result_2 = foo(Tensor([2] * 2)) + result_3 = foo(Tensor([3] * 2)) + + # expect the buffer to share underlying buffer + np.testing.assert_allclose(result_1.numpy(), [2], atol=1e-4, rtol=1e-5) + np.testing.assert_allclose(result_2.numpy(), [6], atol=1e-4, rtol=1e-5) + np.testing.assert_allclose(result_3.numpy(), [6], atol=1e-4, rtol=1e-5) + + def test_jit_batch_split(self): + if Device[Device.DEFAULT].graph is None or JIT >= 2: raise unittest.SkipTest("only test graphs") + + # Create long jit with 83 kernels. + def f(a, b, c, d, e): + for _ in range(80): + a = (a+b).realize() + y = (a*c).realize() + z = (y*d).realize() + w = (z*e) + return w.realize() + + a = Tensor.randn(10, 10).realize() + b = Tensor.randn(10, 10).realize() + c = Tensor.randn(10, 10).realize() + d = Tensor.randn(10, 10).realize() + e = Tensor.randn(10, 10).realize() + + jf = TinyJit(f) + prev = None + for _ in range(5): + o = jf(a, b, c, d, e).numpy() + if prev is not None: np.testing.assert_allclose(o, prev, atol=1e-4, rtol=1e-5) + prev = o + + graph_t = Device[Device.DEFAULT].graph.func if isinstance(Device[Device.DEFAULT].graph, functools.partial) else Device[Device.DEFAULT].graph + # Checking that 2 graphs are inited. + assert isinstance(jf.jit_cache[0].prg, graph_t) + assert isinstance(jf.jit_cache[1].prg, graph_t) + + def test_jit_const_inputs(self): + @TinyJit + def g(x,y,z): return (x+y+z).realize() + for i in range(5): + np.testing.assert_equal(g(Tensor([i]*3), Tensor.ones(3), Tensor.zeros(3)).numpy(), np.array([i+1]*3)) + + def test_jitted_clone(self): + def f(a): return a.clone().realize() + jf = TinyJit(f) + for _ in range(5): + a = Tensor.randn(10, 10, device=Device.DEFAULT).realize() + ja = jf(a) + np.testing.assert_allclose(a.numpy(), ja.numpy(), atol=1e-4, rtol=1e-5) + + @unittest.skipIf(not_support_multi_device(), "no multi") + def test_jitted_transfers(self): + d0, d1 = f"{Device.DEFAULT}:0", f"{Device.DEFAULT}:1" + + def f(a, b): + x = a.to(d1) + y = b.to(d1) + return x.realize(), y.realize() + + jf = TinyJit(f) + for _ in range(5): + a = Tensor.randn(10, 10, device=d0).realize() + b = Tensor.randn(10, 10, device=d0).realize() + xc, yc = jf(a, b) + np.testing.assert_allclose(a.numpy(), xc.numpy(), atol=1e-4, rtol=1e-5) + np.testing.assert_allclose(b.numpy(), yc.numpy(), atol=1e-4, rtol=1e-5) + + def test_jit_several_devs(self): + d0, d1 = f"{Device.DEFAULT}:0", "CPU" + + def f(a, b): + x = a.to(d0).realize() + y = b.to(d0).realize() + return x+y.realize(), x*y.realize() + + jf = TinyJit(f) + for _ in range(5): + a = Tensor.randn(10, 10, device=d1).realize() + b = Tensor.randn(10, 10, device=d1).realize() + zc, wc = jf(a, b) + np.testing.assert_allclose((a.numpy()+b.numpy()), zc.numpy(), atol=1e-4, rtol=1e-5) + np.testing.assert_allclose((a.numpy()*b.numpy()), wc.numpy(), atol=1e-4, rtol=1e-5) + + @unittest.skipIf(not_support_multi_device(), "no multi") + def test_jitted_view(self): + d0, d1 = f"{Device.DEFAULT}:0", f"{Device.DEFAULT}:1" + + def f(a): + x1 = a.sum(axis=(1,)) + x = (x1 + 5).bitcast(dtypes.int32) + y = x.to(d1) + return y.realize() + + jf = TinyJit(f) + for _ in range(5): + a = Tensor.randn(10, 1000, device=d0).realize() + xc = jf(a) + np.testing.assert_allclose((a.numpy().sum(axis=(1,)) + 5).view(np.int32), xc.numpy(), atol=1e-4, rtol=5e-5) + + def test_jit_output_clone(self): + @TinyJit + def f(x:Tensor) -> Tensor: return (x + 1).realize() + + f(Tensor([0.0])) + f(Tensor([0.0])) + + a = f(Tensor([1.0])).clone().realize() + b = f(Tensor([2.0])) + assert abs((a - b).item()) > 0.5 + +@unittest.skip("Pending multioutput implementation #3607") +class TestMultioutputJit(unittest.TestCase): + def _test(self, f): + for _ in range(5): + a, b = Tensor.randn(10, 10), Tensor.randn(10, 10) + out0, out1, out2 = f(a, b) + np.testing.assert_allclose(out0.numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) + np.testing.assert_allclose(out1.numpy(), a.numpy()-b.numpy(), atol=1e-4, rtol=1e-5) + np.testing.assert_allclose(out2.numpy(), a.numpy()*b.numpy(), atol=1e-4, rtol=1e-5) + + def test_jit_multioutput_realize(self): + @TinyJit + def fxn(a, b): return (a+b).realize(), (a-b).realize(), (a*b).realize() + self._test(fxn) + assert_jit_cache_len(fxn, 3) + + def test_jit_multioutput_norealize(self): + @TinyJit + def fxn(a, b): return a+b, a-b, a*b + self._test(fxn) + assert_jit_cache_len(fxn, 1) + + def test_jit_multioutput_mix(self): + @TinyJit + def fxn(a, b): return a+b, a-b, (a*b).realize() + self._test(fxn) + assert_jit_cache_len(fxn, 2) + +class TestJitInsideJit(unittest.TestCase): + def test_jit_jit_error(self): + @TinyJit + def f(t): return t + 1 + + @TinyJit + def g(t): return f(t) * 3 + + # NOTE: first does not raise + g(Tensor([1])).realize() + with self.assertRaisesRegex(RuntimeError, "having TinyJit inside another TinyJit is not supported"): + g(Tensor([1])).realize() + +class TestCopyInsideJit(unittest.TestCase): + def test_copy_inside_jit(self): + @TinyJit + def add(x,y) -> Tensor: return x.to(Device.DEFAULT)+y + for _ in range(5): + # create a Tensor on CPU + a = Tensor.rand(16,16,device="CPU").realize() + b = Tensor.rand(16,16).realize() + out = add(a,b) + np.testing.assert_allclose(out.flatten().tolist(), [x+y for x,y in zip(a.flatten().tolist(), b.flatten().tolist())]) + +class TestJitPrune(unittest.TestCase): + def test_simple_prune(self): + weights = Tensor.rand(16).realize() + def w2(x) -> Tensor: return (weights*2).contiguous() + x + w2_noprune = TinyJit(w2) + w2_prune = TinyJit(w2, prune=True) + + for _ in range(3): + a = Tensor.rand(16).realize() + out = w2_noprune(a) + np.testing.assert_allclose(out.tolist(), [x*2+y for x,y in zip(weights.tolist(), a.tolist())]) + assert len(w2_noprune.captured.jit_cache) == 2 + + for _ in range(3): + a = Tensor.rand(16).realize() + out = w2_prune(a) + np.testing.assert_allclose(out.tolist(), [x*2+y for x,y in zip(weights.tolist(), a.tolist())]) + assert len(w2_prune.captured.jit_cache) == 1 + + def test_prune_w_copy_correct(self): + weights = Tensor.rand(16).realize() + def w2(x) -> Tensor: return (weights*2).contiguous() + x.to(Device.DEFAULT) + w2_noprune = TinyJit(w2) + w2_prune = TinyJit(w2, prune=True) + + for _ in range(3): + a = Tensor.rand(16, device="CPU").realize() + out = w2_noprune(a) + np.testing.assert_allclose(out.tolist(), [x*2+y for x,y in zip(weights.tolist(), a.tolist())]) + + for _ in range(3): + a = Tensor.rand(16, device="CPU").realize() + out = w2_prune(a) + np.testing.assert_allclose(out.tolist(), [x*2+y for x,y in zip(weights.tolist(), a.tolist())]) + + def test_prune_w_independent_copy_correct(self): + weights = Tensor.rand(16, device="CPU").realize() + def w2(x) -> Tensor: return (weights*2).contiguous().to(Device.DEFAULT) + x + w2_noprune = TinyJit(w2) + w2_prune = TinyJit(w2, prune=True) + + for _ in range(3): + a = Tensor.rand(16).realize() + out = w2_noprune(a) + np.testing.assert_allclose(out.tolist(), [x*2+y for x,y in zip(weights.tolist(), a.tolist())]) + + for _ in range(3): + a = Tensor.rand(16).realize() + out = w2_prune(a) + np.testing.assert_allclose(out.tolist(), [x*2+y for x,y in zip(weights.tolist(), a.tolist())]) + + assert len(w2_prune.captured.jit_cache) == 1, "prune should have removed the copy" + +class TestJitFree(unittest.TestCase): + def test_free_intermediates(self): + ext_tensor = Tensor([1,24,23,45,1]) + @TinyJit + def fxn(x:Tensor): + out = (x*2+ext_tensor).reshape(5,1).expand(5, 100).contiguous() + return out.sum() + for i in range(5): + out = fxn(Tensor([i,1,2,3,4])) + self.assertEqual(out.item(), 11400+200*i) + pre_free = GlobalCounters.mem_used + fxn.captured.free_intermediates() + savings_after_free = pre_free - GlobalCounters.mem_used + + # Different allocator implementations have different savings. + expected_savings = 8196 if hasattr(Device[Device.DEFAULT].allocator, '_offset') else 2024 + + self.assertEqual(savings_after_free, expected_savings) + out = fxn(Tensor([11,1,2,3,4])) + self.assertEqual(out.item(), 13600) + + # Try one more time... + pre_free = GlobalCounters.mem_used + fxn.captured.free_intermediates() + fxn.captured.free_intermediates() # 2nd time to validate + savings_after_free = pre_free - GlobalCounters.mem_used + + self.assertEqual(savings_after_free, expected_savings) + out = fxn(Tensor([11,1,2,3,4])) + self.assertEqual(out.item(), 13600) + + def test_updated_not_freed(self): + x = Tensor([1]).realize() + @TinyJit + def fxn(y): + nonlocal x + x += y + return x + for _ in range(5): fxn(Tensor([1])) + self.assertEqual(x.item(), 6) + pre_free = GlobalCounters.mem_used + fxn.captured.free_intermediates() + savings_after_free = pre_free - GlobalCounters.mem_used + self.assertEqual(savings_after_free, 0) + fxn(Tensor([2])) + self.assertEqual(x.item(), 8) + + def test_replan_buffers_memory_layout(self): + if not hasattr(Device[Device.DEFAULT].allocator, '_offset'): raise unittest.SkipTest("replan_buffers_memory_layout useless") + + ext_tensor = Tensor([1,24,23,45,1]) + ext_tensor_2 = Tensor([2,2,2,2,2]) + @TinyJit + def fxn(x:Tensor): + out = (x*ext_tensor_2+ext_tensor).reshape(5,1).expand(5, 100).contiguous() + return out.sum() + for i in range(5): + out = fxn(Tensor([i,1,2,3,4])) + self.assertEqual(out.item(), 11400+200*i) + assert len(set([b.base for item in fxn.captured.jit_cache for b in item.bufs if b is not None])) == 4 + fxn.captured.replan_buffers_memory_layout() + assert len(set([b.base for item in fxn.captured.jit_cache for b in item.bufs if b is not None])) == 2 + + out = fxn(Tensor([11,1,2,3,4])) + self.assertEqual(out.item(), 13600) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_jit_cases.py b/tinygrad_repo/test/test_jit_cases.py new file mode 100644 index 000000000..dd474e353 --- /dev/null +++ b/tinygrad_repo/test/test_jit_cases.py @@ -0,0 +1,78 @@ +import unittest +from tinygrad import TinyJit, Tensor + +# The JIT functions as a "capturing" JIT. +# Whatever kernels ran in the JIT the second run through the function will be the kernels that will run from then on. +# Explicit inputs to the function are updated in the JIT graph to the new inputs. + +# JITs have four tensor types +# 1. Tensors that are explicit in the input, aka what's passed in. TODO: support lists/dicts/classes, anything get_state works on +# 2. Tensors that are explicit in the output, aka what's returned. TODO: same as above +# 3. Tensors that are implicit in the input as a closure. +# 4. Tensors that are implicit in the output because they were assigned to and realized. + +# explicit inputs and outputs are realized on their way in and out of the JIT +# there's a whole bunch of edge cases and weirdness here that needs to be tested and clarified. + +class TestJitCases(unittest.TestCase): + def test_explicit(self): + # this function has an explicit input and an explicit output + @TinyJit + def f(x:Tensor): + ret:Tensor = x*2 + return ret + + for i in range(5): + out = f(Tensor([i])) + self.assertEqual(out.item(), i*2) + + def test_implicit_input(self): + # x is the implicit input (like a weight) + x = Tensor([0]) + + # this function has an implicit input and an explicit output + @TinyJit + def f(): + ret:Tensor = x*2 + return ret + + for i in range(5): + # NOTE: this must be realized here, otherwise the update doesn't happen + # if we were explicitly tracking the implicit input Tensors, we might not need this realize + x.assign(Tensor([i])).realize() + out = f() + self.assertEqual(out.item(), i*2) + + def test_implicit_output(self): + # out is the implicit output (it's assigned to) + out = Tensor([0]) + + # this function has an explicit input and an implicit output + @TinyJit + def f(x:Tensor): + # NOTE: this must be realized here + # if we were explicitly tracking the implicit output Tensors, we might not need this realize + out.assign(x*2).realize() + + for i in range(5): + f(Tensor([i])) + self.assertEqual(out.item(), i*2) + + def test_implicit_io(self): + # x is the implicit input (like a weight) + # out is the implicit output (it's assigned to) + x = Tensor([0]) + out = Tensor([0]) + + # this function has an implicit input and an implicit output + @TinyJit + def f(): + out.assign(x*2).realize() # NOTE: this must be realized here + + for i in range(5): + x.assign(Tensor([i])).realize() + f() + self.assertEqual(out.item(), i*2) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_kernel_cache.py b/tinygrad_repo/test/test_kernel_cache.py new file mode 100644 index 000000000..164b501a4 --- /dev/null +++ b/tinygrad_repo/test/test_kernel_cache.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python +import unittest +from tinygrad.tensor import Tensor +from tinygrad import Device + +class TestKernelCache(unittest.TestCase): + def test_kernel_cache_in_action(self): + if Device.DEFAULT not in ["CPU"]: + self.skipTest("No custom kernel cache is implemented") + + unique_const = 0.6765677269 + a = Tensor.rand(4,4).realize() + b = Tensor.rand(4,4).realize() + x = a + b + unique_const + x.realize() + + a1 = Tensor.rand(4,4).realize() + b1 = Tensor.rand(4,4).realize() + orig_compile_func = Device['CPU'].compiler + Device['CPU'].compiler = None # making it not callable + + try: + x1 = a1 + b1 + unique_const + x1.realize() # Same kernel should be from cache. + finally: + Device['CPU'].compiler = orig_compile_func + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/test_linearizer.py b/tinygrad_repo/test/test_linearizer.py new file mode 100644 index 000000000..44d7e8592 --- /dev/null +++ b/tinygrad_repo/test/test_linearizer.py @@ -0,0 +1,2239 @@ +from typing import Union +import numpy as np +import unittest +from dataclasses import replace + +from test.helpers import ast_const +from tinygrad.opt.kernel import Opt, OptOps, KernelOptError, Kernel +from tinygrad.codegen.lowerer import get_grouped_dims +from tinygrad.uop.ops import UOp, Ops, GroupOp, KernelInfo +from tinygrad.device import Device, Buffer, is_dtype_supported +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.shape.view import View +from tinygrad.tensor import Tensor, _to_np_dtype +from tinygrad.engine.realize import run_schedule, lower_schedule, CompiledRunner, get_program +from tinygrad.opt.heuristic import hand_coded_optimizations +from tinygrad.helpers import prod, Context, getenv, CI, flatten, dedup, AMX +from tinygrad.dtype import DType, dtypes + +def helper_realized_ast(r:Union[Tensor, list[Tensor]]) -> tuple[UOp, list[Buffer]]: + if isinstance(r, Tensor): r = [r] + s = Tensor.schedule(*r) + run_schedule(s[:-1]) # run all kernels except the last one + assert s[-1].ast.op is Ops.SINK, f"helper_realized_ast expects a SINK {s[-1]}" + # now all input buffers in s[-1] should be realized + # create fresh buffers for the outputs + bufs = [Buffer((x).device, x.size, x.dtype).allocate() if i < len(s[-1].ast.src) else x for i,x in enumerate(s[-1].bufs)] + return s[-1].ast, bufs + +def helper_tc_allclose(N:int, M:int, K:int, dtype_in:DType, dtype_out:DType, axis:int=0, tc_select:int=-1, tc_opt:int=0, use_tensor_cores:int=1): + a, b = Tensor.rand(M, K, dtype=dtype_in), Tensor.rand(K, N, dtype=dtype_in) + np_a, np_b = a.numpy(), b.numpy() + r = a.matmul(b, dtype=dtype_out) + if dtype_in == dtypes.bfloat16: r = r.float() + realized_ast, bufs = helper_realized_ast(r) + k = Kernel(realized_ast) + k.apply_tensor_cores(use_tensor_cores, axis=axis, tc_select=tc_select, tc_opt=tc_opt) + prg = CompiledRunner(replace(k.to_program(), device=Device.DEFAULT)) + if use_tensor_cores == 1: assert len([uop for uop in k.uops if uop.op is Ops.WMMA]) > 0, "wmma not triggered" + elif use_tensor_cores == 3: assert len([uop for uop in k.uops if uop.op is Ops.DEFINE_LOCAL]) == 2, "local buffers not triggered" + assert len([x for x in k.applied_opts if x.op is OptOps.TC]) == 1, "tensor core opt not included" + prg.exec(bufs) + if dtype_in == dtypes.half: tc_atol, tc_rtol = 1e-2, 1e-3 + elif dtype_in == dtypes.bfloat16: tc_atol, tc_rtol = 1e-2, 1e-2 + else: tc_atol, tc_rtol = 5e-3, 1e-4 + c = bufs[0].numpy().reshape((M,N)) + np.testing.assert_allclose(c, np_a @ np_b, atol=tc_atol, rtol=tc_rtol) + +def helper_tc_ensure_uops_and_opts_count(N: int, M:int, K:int, dtype_in:DType, dtype_out:DType, axis:int=0, tc_select:int=-1, tc_opt:int=0, + ensure_triggered:bool=True): + a, b = Tensor.rand(M, K, dtype=dtype_in), Tensor.rand(K, N, dtype=dtype_in) + r = a.matmul(b, dtype=dtype_out) + sched = r.schedule() + realized_ast = sched[-1].ast + opts_to_apply = [Opt(OptOps.TC, axis, (tc_select, tc_opt, 1))] + realized_ast = realized_ast.replace(arg=KernelInfo(opts_to_apply=tuple(opts_to_apply))) + + if ensure_triggered: + program = get_program(realized_ast, Device[Device.DEFAULT].renderer) + wmmas = len([uop for uop in program.uops if uop.op is Ops.WMMA]) + tcs = len([x for x in program.applied_opts if x.op is OptOps.TC]) + assert wmmas > 0, "tensor core not triggered" + assert tcs == 1, "tensor core opt not included" + else: + try: + program = get_program(realized_ast, Device[Device.DEFAULT].renderer) + assert False, "OptOps.TC triggered, expected KernelOptError" + except KernelOptError: pass + +class TestLinearizer(unittest.TestCase): + def test_arg_dedup(self): + # NOTE: this realize exists because Tensor.numpy calls .contiguous() internally + # without contiguous folding, rand.to("CPU") and rand.contiguous().to("CPU") are different UOps. + # this test asserts they are the identical Buffer + # having different buffers is fine for correctness, because the outputs match. + a, b = Tensor.randn(4).realize(), Tensor.randn(4).realize() + np_a, np_b = a.numpy(), b.numpy() + c = ((a.shrink(((0, 2),)) - a.shrink(((2, 4),))) - (b.shrink(((0, 2),)) - b.shrink(((2, 4),)))) + lowered = [x[1] for x in lower_schedule(c.schedule())] + for ei in lowered: ei.run() + rawbufs = lowered[-1].bufs + assert len(rawbufs) == 3 and set(rawbufs[1:]) == {a.uop.base.realized, b.uop.base.realized} + np_c = (np_a[:2] - np_a[2:]) - (np_b[:2] - np_b[2:]) + np.testing.assert_allclose(np_c, c.numpy(), atol=1e-4, rtol=1e-4) + + def test_load_removed(self): + a = Tensor.rand(1).realize() + b = Tensor.rand(1).realize() + ta = Tensor.where(Tensor(True), a, b).numpy() + tb = Tensor.where(Tensor(False), a, b).numpy() + np.testing.assert_equal(a.numpy(), ta) + np.testing.assert_equal(b.numpy(), tb) + + def test_multioutput(self): + dtype, st = dtypes.int, ShapeTracker.from_shape((8,)) + g0, g1, g2, g3 = [UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), arg=i) for i in range(4)] + a = UOp(Ops.LOAD, dtype, src=(g2.view(st),)) + b = UOp(Ops.LOAD, dtype, src=(g3.view(st),)) + out0 = UOp(Ops.STORE, dtypes.void, src=(g0.view(st), a + b)) + out1 = UOp(Ops.STORE, dtypes.void, src=(g1.view(st), a * b)) + sink = UOp(Ops.SINK, src=(out0, out1)) + + a_t = Tensor.full(st.shape, 2).contiguous().realize() + b_t = Tensor.full(st.shape, 3).contiguous().realize() + lin = helper_linearizer_ast(sink, [a_t, b_t], wanna_output=[a_t.numpy()+b_t.numpy(), a_t.numpy()*b_t.numpy()])[0] + + stores = [u for u in lin.uops if u.op is Ops.STORE] + mutable_bufs = dedup(flatten([[x for x in u.src[0].toposort() if x.op is Ops.DEFINE_GLOBAL] for u in stores])) + assert len(mutable_bufs) == len(stores) == 2 + self.assertSetEqual(set([u.arg for u in mutable_bufs]), set([0,1])) + + def _test_no_nested_ranges(self, lins, skip=None): + for l in lins: + range_in_acc = flatten([[x for x in u.src if x.op is Ops.RANGE] for u in l.uops if u.op is Ops.DEFINE_ACC]) + ranges = [u.op for u in l.uops if (u.op is Ops.RANGE and u in range_in_acc) or (u.op is Ops.ENDRANGE and u.src[0] in range_in_acc)] + for i,u in enumerate(ranges): + if skip and i in skip: continue + assert ranges[i-1] != u, f"multireduce nested the ranges! {ranges[i-1], {u}}" + + @unittest.expectedFailure + def test_const_alu_indexing(self): + st = ShapeTracker.from_shape((4,)).to_uop() + load = UOp.load(UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1, src=()), st, dtype=dtypes.float) + op = load+UOp.const(dtypes.float, 1.0)*UOp.const(dtypes.float, -1) + store = UOp.store(UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0, src=()), st, op) + Tensor.manual_seed(0) + x = Tensor.randn(4,).realize() + helper_linearizer_ast(store.sink(), [x], wanna_output=[x.numpy()+1*-1], opts=[]) + + # shapeless CONST in AST is not supported + @unittest.expectedFailure + def test_const_alu_indexing_one_const_fine(self): + st = ShapeTracker.from_shape((4,)).to_uop() + load = UOp.load(UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1, src=()), st, dtype=dtypes.float) + op = load+UOp.const(dtypes.float, 1.0) + store = UOp.store(UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0, src=()), st, op) + Tensor.manual_seed(0) + x = Tensor.randn(4,).realize() + helper_linearizer_ast(store.sink(), [x], wanna_output=[x.numpy()+1], opts=[]) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + def test_multireduce(self): + Tensor.manual_seed(0) + x = Tensor.randn(32, dtype=dtypes.float).realize() + st_x = x.uop.st + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + first_x = UOp(Ops.LOAD, dtypes.float, (g1.view(st_x.reshape((1, 32)).expand((32, 32))),)) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (1,))) + second_x = UOp(Ops.LOAD, dtypes.float, (g1.view(st_x.reshape((32, 1))),)) + diff = second_x + first_reduce*ast_const(dtypes.float, -1, (32, 1)) + second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (0,))) + store = UOp(Ops.STORE, dtypes.void, (g0.view(ShapeTracker.from_shape((1, 1))), second_reduce)) + sink = UOp(Ops.SINK, src=(store,)) + opts = [ + [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], # grouping + [Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 1, 8)], + [Opt(OptOps.GROUPTOP, 0, 16), Opt(OptOps.GROUPTOP, 1, 16)], + [Opt(OptOps.GROUPTOP, 0, 32), Opt(OptOps.GROUPTOP, 0, 32)], + [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2)], # unroll reduce + [Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UNROLL, 1, 4)], + [Opt(OptOps.UNROLL, 0, 8), Opt(OptOps.UNROLL, 1, 8)] if Device.DEFAULT not in {"NV", "METAL"} else [], # can't do float8, + [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], # grouping + unrolling + [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], + [Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UNROLL, 2, 8), Opt(OptOps.UNROLL, 2, 8)], + [Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UNROLL, 1, 4), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 0, 8)], + ] + wanna_output = (x.numpy()-x.numpy().sum(-1, keepdims=True)).sum(-1).reshape(1,1) + lins = helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) + self._test_no_nested_ranges(lins, [0]) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + def test_mid_dim_multireduce(self): + Tensor.manual_seed(0) + x = Tensor.randn(27, 32, 5, dtype=dtypes.float).realize() + st_x = x.uop.st + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + first_x = UOp(Ops.LOAD, dtypes.float, (g1.view(st_x.reshape((27, 1, 32, 5)).expand((27, 32, 32, 5))),)) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) + second_x = UOp(Ops.LOAD, dtypes.float, (g1.view(st_x.reshape((27, 32, 1, 5))),)) + diff = second_x + first_reduce*ast_const(dtypes.float, -1, (27, 32, 1, 5)) + second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_reduce)) + sink = UOp(Ops.SINK, src=(store,)) + opts = [ + # locals + [Opt(OptOps.LOCAL, 0, 3)], + [Opt(OptOps.LOCAL, 0, 9)], + [Opt(OptOps.LOCAL, 0, 27)], + # grouping + [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], + [Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 1, 8)], + [Opt(OptOps.GROUPTOP, 0, 16), Opt(OptOps.GROUPTOP, 1, 16)], + [Opt(OptOps.GROUPTOP, 0, 32), Opt(OptOps.GROUPTOP, 0, 32)], + # # unroll + [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2)], + [Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UNROLL, 1, 4)], + [Opt(OptOps.UNROLL, 0, 8), Opt(OptOps.UNROLL, 1, 8)] if Device.DEFAULT not in {"NV", "METAL"} else [], + # # upcasting + [Opt(OptOps.UPCAST, 0, 3)], + [Opt(OptOps.UPCAST, 0, 9)], + # locals with grouping + [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], + # locals with unroll + [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2)], + # locals with upcasting + [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.UPCAST, 0, 9)], + # grouping with unrolling + [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], + [Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UNROLL, 2, 8), Opt(OptOps.UNROLL, 2, 8)], + # grouping with upcasting + [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UPCAST, 0, 3)], + # locals with grouping with unroll + [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], + [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UNROLL, 2, 8), Opt(OptOps.UNROLL, 2, 8)], + # locals with grouping with upcasting + [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.UPCAST, 0, 3), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], + [Opt(OptOps.LOCAL, 0, 9), Opt(OptOps.UPCAST, 0, 3), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], + # grouping with unrolling and upcasting + [Opt(OptOps.UPCAST, 0, 3), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], + [Opt(OptOps.UPCAST, 0, 3), Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UNROLL, 2, 8), Opt(OptOps.UNROLL, 2, 8)], + # locals + grouping + unrolling + upcasting + [Opt(OptOps.LOCAL, 0, 3), Opt(OptOps.UPCAST, 0, 3), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), + Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], + ] + wanna_output = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) + lins = helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) + self._test_no_nested_ranges(lins, [0]) + + def test_triple_multireduce(self): + Tensor.manual_seed(0) + x0 = Tensor.randn(27, 32, 5, dtype=dtypes.float).realize() + x1 = Tensor.randn(27, 32, 5, dtype=dtypes.float).realize() + x2 = Tensor.randn(27, 32, 5, dtype=dtypes.float).realize() + g0, g1, g2, g3 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(4)] + first_x = UOp(Ops.LOAD, dtypes.float, (g1.view(x0.uop.st.reshape((27, 1, 1, 32, 5)).expand((27, 32, 32, 32, 5))),)) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (3,))) + second_x = UOp(Ops.LOAD, dtypes.float, (g2.view(x1.uop.st.reshape((27, 1, 32, 1, 5)).expand((27, 32, 32, 1, 5))),)) + diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 32, 32, 1, 5))) + second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (2,))) + third_x = UOp(Ops.LOAD, dtypes.float, (g3.view(x2.uop.st.reshape((27, 32, 1, 1, 5))),)) + mul = (third_x*second_reduce) + third_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (mul,), (Ops.ADD, (1,))) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 1, 5))), third_reduce)) + sink = UOp(Ops.SINK, src=(store,)) + wanna_output = (x2.numpy()*(x1.numpy()-x0.numpy().sum(axis=1, keepdims=True)).sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,1,5) + lins = helper_linearizer_ast(sink, [x0,x1,x2], wanna_output=[wanna_output]) + self._test_no_nested_ranges(lins, [0]) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + @unittest.skip("this is not supported, it worked by luck") + def test_double_reduce_multireduce(self): + Tensor.manual_seed(0) + x = Tensor.randn(8, 32, 8, 16, dtype=dtypes.float).realize() + st = x.uop.st + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + first_x = UOp(Ops.LOAD, dtypes.float, (g1, st.reshape((8, 1, 32, 8, 1, 16)).expand((8, 32, 32, 8, 16, 16)).to_uop())) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2, 5))) + second_x = UOp(Ops.LOAD, dtypes.float, (g1, st.reshape((8, 32, 1, 8, 16, 1)).to_uop())) + neg_first_reduce = first_reduce * ast_const(dtypes.float, -1, (8, 32, 1, 8, 16, 1)) + squares = (second_x+neg_first_reduce) + squares_sum = UOp(Ops.REDUCE_AXIS, dtypes.float, (squares,), (Ops.ADD, (1, 4))) + store = UOp(Ops.STORE, src=(g0, ShapeTracker.from_shape((8, 1, 1, 8, 1, 1)).to_uop(), squares_sum,)) + sink = UOp(Ops.SINK, src=(store,)) + wanna_output = (x.numpy()-x.numpy().sum(axis=(1,3), keepdims=True)).sum(axis=(1,3)).reshape((8,1,1,8,1,1)) + opts = [ + # openCL / GPU=1 is 256 max threads + # grouping + [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], # first dim of both reduces + [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 3, 2)], # both dims of the second reduce + [Opt(OptOps.GROUPTOP, 2, 2), Opt(OptOps.GROUPTOP, 3, 2)], # second dim of both reduces + [Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.GROUPTOP, 3, 2)], # both dims of the first reduce + # group all reduce dims + [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.GROUPTOP, 2, 2), Opt(OptOps.GROUPTOP, 3, 2)], + # checking how it works with 2 grouped reduces + unrolling + [Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.GROUPTOP, 2, 4), Opt(OptOps.GROUPTOP, 3, 4), + Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], + # Checking how it works with 2 grouped reduces + locals. + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.LOCAL, 0, 4), + Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.GROUPTOP, 2, 2), Opt(OptOps.GROUPTOP, 3, 2)], + # Checking how it works with 2 grouped reduces + locals + unroll. + [Opt(OptOps.LOCAL, 0, 2), + Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.GROUPTOP, 2, 4), Opt(OptOps.GROUPTOP, 3, 4), + Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], + # Checking how it works with 2 grouped reduces + locals + upcast. + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.UPCAST, 0, 2), + Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.GROUPTOP, 2, 2), Opt(OptOps.GROUPTOP, 3, 2)], + # Checking how it works with 2 grouped reduces + locals + upcast + unroll. + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.UPCAST, 0, 2), + Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.GROUPTOP, 2, 4), Opt(OptOps.GROUPTOP, 3, 4), + Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], + ] + lins = helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) + self._test_no_nested_ranges(lins, [0, 1]) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + def test_partial_opt_multireduce(self): + # check how it works with one reduce optimized and one unoptimized + Tensor.manual_seed(0) + x = Tensor.randn(27, 15, 5, dtype=dtypes.float).softmax(1).realize() + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + first_x = UOp(Ops.LOAD, dtypes.float, (g1.view(x.uop.st.reshape((27, 1, 15, 5)).expand((27, 15, 15, 5))),)) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) + second_x = UOp(Ops.LOAD, dtypes.float, (g1.view(x.uop.st.reshape((27, 15, 1, 5))),)) + diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 15, 1, 5))) + second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_reduce)) + sink = UOp(Ops.SINK, src=(store,)) + opts = [ + [Opt(OptOps.GROUPTOP, 0, 3)], # grouping + [Opt(OptOps.GROUPTOP, 1, 3)], + [Opt(OptOps.GROUPTOP, 0, 15)], + [Opt(OptOps.GROUPTOP, 1, 15)], + [Opt(OptOps.UNROLL, 0, 3)], + [Opt(OptOps.UNROLL, 1, 3)], + ] + wanna_output = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) + lins = helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) + self._test_no_nested_ranges(lins, [0]) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + def test_multireduce_with_parallel(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 32, dtype=dtypes.float).realize() + x_p = Tensor.randn(4, 32, dtype=dtypes.float).realize() + g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] + first_x = UOp(Ops.LOAD, dtypes.float, (g1.view(x.uop.st.reshape((4, 1, 32)).expand((4, 32, 32))),)) + first_x_p = UOp(Ops.LOAD, dtypes.float, (g2.view(x_p.uop.st.reshape((4, 1, 32)).expand((4, 32, 32))),)) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) + first_reduce_p = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x_p.alu(Ops.EXP2),), (Ops.ADD, (2,))) + second_x = UOp(Ops.LOAD, dtypes.float, (g1.view(x.uop.st.reshape((4, 32, 1))),)) + diff = (second_x+(first_reduce + first_reduce_p)*ast_const(dtypes.float, -1, (4, 32, 1))) + second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((4, 1, 1))), second_reduce)) + sink = UOp(Ops.SINK, src=(store,)) + opts = [ + # [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], # grouping + # [Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 1, 8)], + # [Opt(OptOps.GROUPTOP, 0, 16), Opt(OptOps.GROUPTOP, 1, 16)], + # [Opt(OptOps.GROUPTOP, 0, 32), Opt(OptOps.GROUPTOP, 0, 32)], + [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2)], # unroll reduce + [Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UNROLL, 1, 4)], + [Opt(OptOps.UNROLL, 0, 8), Opt(OptOps.UNROLL, 1, 8)] if Device.DEFAULT not in {"NV", "METAL"} else [], # can't do float8, + # [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UNROLL, 2, 2), Opt(OptOps.UNROLL, 3, 2)], # grouping + unrolling + # [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UNROLL, 1, 2), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], + # [Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UNROLL, 2, 8), Opt(OptOps.UNROLL, 2, 8)], + # [Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UNROLL, 1, 4), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 0, 8)], + ] + wanna_output = (x.numpy()-(x.numpy().sum(-1, keepdims=True)+np.exp2(x_p.numpy()).sum(-1, keepdims=True))).sum(-1).reshape(4, 1,1) + lins = helper_linearizer_ast(sink, [x,x_p], wanna_output=[wanna_output], opts=opts) + self._test_no_nested_ranges(lins, [0]) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + def test_multiout_multireduce(self): + # check how multireduce works with multioutput + Tensor.manual_seed(0) + x = Tensor.randn(27, 15, 5, dtype=dtypes.float).realize() + g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] + first_x = UOp(Ops.LOAD, dtypes.float, (g2.view(x.uop.st.reshape((27, 1, 15, 5)).expand((27, 15, 15, 5))),)) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) + second_x = UOp(Ops.LOAD, dtypes.float, (g2.view(x.uop.st.reshape((27, 15, 1, 5))),)) + diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 15, 1, 5))) + second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) + store0 = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_reduce)) + second_out = second_reduce * ast_const(dtypes.float, 1/15, (27, 1, 1, 5)) + store1 = UOp(Ops.STORE, src=(g1.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_out)) + sink = UOp(Ops.SINK, src=(store0, store1)) + wanna_output = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) + + helper_linearizer_ast(sink, [x], wanna_output=[wanna_output, wanna_output/15]) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + def test_multiout_intermediate_multireduce(self): + # check how it outputing at different stages of the multireduce works + # TODO: Fails because the stores shapes do not match: store1.shape = (27,15,1,5) != store0.shape = (27,1,1,5) + # so the output shapes are different (FAIL!), + # if we change the shape of store1 to be contiguous, it will match store0 but not the value it's storing (FAIL!) + Tensor.manual_seed(0) + x = Tensor.randn(27, 15, 5, dtype=dtypes.float).realize() + g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] + first_x = UOp(Ops.LOAD, dtypes.float, src=(g2.view(x.uop.st.reshape((27, 1, 15, 5)).expand((27, 15, 15, 5))),)) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) + second_x = UOp(Ops.LOAD, dtypes.float, src=(g2.view(x.uop.st.reshape((27, 15, 1, 5))),)) + diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 15, 1, 5))) + second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) + store0 = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_reduce)) + store1 = UOp(Ops.STORE, src=(g1.view(ShapeTracker(views=(View(shape=(27,15,1,5), strides=(5,0,1,1), offset=0, mask=None, contiguous=False),))), first_reduce)) # noqa: E501 + wanna_output0 = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) + wanna_output1 = x.numpy().sum(axis=1).reshape(27,1,1,5) + + sink = UOp(Ops.SINK, src=(store0, store1)) + with self.assertRaises(RuntimeError): # AST is invalid + helper_linearizer_ast(sink, [x], wanna_output=[wanna_output0, wanna_output1]) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + def test_complete_unroll_multireduce(self): + Tensor.manual_seed(0) + x = Tensor.randn(27, 3, 5, dtype=dtypes.float).realize() + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + first_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((27, 1, 3, 5)).expand((27, 3, 3, 5))),)) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) + second_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((27, 3, 1, 5))),)) + diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 3, 1, 5))) + second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_reduce)) + sink = UOp(Ops.SINK, src=(store,)) + opts = [[Opt(OptOps.UNROLL, 0, 3), Opt(OptOps.UNROLL, 0, 3)]] + wanna_output = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) + helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + def test_upcast_multireduce(self): + Tensor.manual_seed(0) + x = Tensor.randn(27, 3, 5, dtype=dtypes.float).realize() + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + first_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((27, 1, 3, 5)).expand((27, 3, 3, 5))),)) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) + second_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((27, 3, 1, 5))),)) + diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 3, 1, 5))) + second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((27, 1, 1, 5))), second_reduce)) + sink = UOp(Ops.SINK, src=(store,)) + opts = [[Opt(OptOps.UPCAST, 0, 3)]] + wanna_output = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) + helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skip("can't group with multiple reduces yet") + def test_early_endif(self): + # make sure the if block of a grouped reduce can be closed early and the result loaded back in + Tensor.manual_seed(0) + x = Tensor.randn(27, 12, 5, dtype=dtypes.float).realize() + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + first_x = UOp(Ops.LOAD, dtypes.float, (g1, x.uop.st.reshape((27, 1, 12, 5)).expand((27, 12, 12, 5)).to_uop())) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) + second_x = UOp(Ops.LOAD, dtypes.float, (g1, x.uop.st.reshape((27, 12, 1, 5)).to_uop())) + diff = (second_x+first_reduce*ast_const(dtypes.float, -1, (27, 12, 1, 5))) + second_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (diff,), (Ops.ADD, (1,))) + store = UOp(Ops.STORE, src=(g0, ShapeTracker.from_shape((27, 1, 1, 5)).to_uop(), second_reduce)) + sink = UOp(Ops.SINK, src=(store,)) + opts = [[Opt(OptOps.GROUPTOP, 0, 3), Opt(OptOps.GROUPTOP, 1, 3)]] + wanna_output = (x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(27,1,1,5) + helper_linearizer_ast(sink, [x], wanna_output=[wanna_output], opts=opts) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + def test_mean_std_multireduce(self): + Tensor.manual_seed(0) + x = Tensor.randn(15, 25, 35, dtype=dtypes.float).realize() + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + first_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((15, 25, 1, 35)).expand((15, 25, 35, 35))),)) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (3,))) + neg_mean = first_reduce * ast_const(dtypes.float, -1/35, (15, 25, 35, 1)) + second_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((15, 25, 35, 1))),)) + squares = (second_x+neg_mean)*(second_x+neg_mean) + squares_sum = UOp(Ops.REDUCE_AXIS, dtypes.float, (squares,), (Ops.ADD, (2,))) + variance = squares_sum * ast_const(dtypes.float, 1/35, (15, 25, 1, 1)) + std = variance.alu(Ops.SQRT) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((15, 25, 1, 1))), std)) + sink = UOp(Ops.SINK, src=(store,)) + wanna_output = x.numpy().std(axis=2, ddof=0).reshape((15,25,1,1)) + helper_linearizer_ast(sink, [x], wanna_output=[wanna_output]) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + def test_mean_std_multireduce_mid_dim(self): + Tensor.manual_seed(0) + x = Tensor.randn(15, 25, 35, dtype=dtypes.float).realize() + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + first_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((15, 1, 25, 35)).expand((15, 25, 25, 35))),)) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (2,))) + neg_mean = first_reduce * ast_const(dtypes.float, -0.04, (15, 25, 1, 35)) + second_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((15, 25, 1, 35))),)) + squares = (second_x+neg_mean)*(second_x+neg_mean) + squares_sum = UOp(Ops.REDUCE_AXIS, dtypes.float, (squares,), (Ops.ADD, (1,))) + variance = squares_sum * ast_const(dtypes.float, 0.04, (15, 1, 1, 35)) + std = variance.alu(Ops.SQRT) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((15, 1, 1, 35))), std)) + sink = UOp(Ops.SINK, src=(store,)) + wanna_output = x.numpy().std(axis=1, ddof=0).reshape((15,1,1,35)) + helper_linearizer_ast(sink, [x], wanna_output=[wanna_output]) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + @unittest.expectedFailure + def test_mean_std_multireduce_multiout(self): + # TODO: Similar error to test_multiout_intermediate_multireduce (implicit expand vs shape mismatch) + Tensor.manual_seed(0) + x = Tensor.randn(15, 25, 35, dtype=dtypes.float).realize() + g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] + first_x = UOp(Ops.LOAD, dtypes.float, (g2, x.uop.st.reshape((15, 25, 1, 35)).expand((15, 25, 35, 35)).to_uop())) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (3,))) + neg_mean = first_reduce * ast_const(dtypes.float, -1/35, (15, 25, 35, 1)) + second_x = UOp(Ops.LOAD, dtypes.float, (g2, x.uop.st.reshape((15, 25, 35, 1)).to_uop())) + squares = (second_x+neg_mean)*(second_x+neg_mean) + squares_sum = UOp(Ops.REDUCE_AXIS, dtypes.float, (squares,), (Ops.ADD, (2,))) + variance = squares_sum * ast_const(dtypes.float, 1/35, (15, 25, 1, 1)) + std = variance.alu(Ops.SQRT) + store_mean = UOp(Ops.STORE, src=(g1, ShapeTracker.from_shape((15, 25, 1, 1)).to_uop(), neg_mean)) + store_std = UOp(Ops.STORE, src=(g0, ShapeTracker.from_shape((15, 25, 1, 1)).to_uop(), std)) + sink = UOp(Ops.SINK, src=(store_std, store_mean)) + wanna_output = [x.numpy().std(axis=2, ddof=0).reshape(15,25,1,1), x.numpy().mean(axis=2).reshape(15,25,1,1)] + + lins = helper_linearizer_ast(sink, [x], wanna_output=wanna_output) + for k in lins: + assert len([u for u in k.uops if u.op is Ops.DEFINE_ACC]) == 2, "got more than two accs (implies the kernel didn't reuse the mean reduce)" + + @unittest.skipIf(CI and Device.DEFAULT in {"PTX", "AMD", "NV"}, "ocelot/remu doesn't have multiple wave syncs yet") + def test_var_multireduce(self): + Tensor.manual_seed(0) + x = Tensor.randn(3, 27, 32, dtype=dtypes.float).realize() + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + # push reduce (3, 27, 32) -> (3, 27, 1) -> (3, 27, 32) expand to LOAD + first_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((3, 27, 1, 32)).expand((3, 27, 32, 32))),)) + first_reduce = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.ADD, (3,))) + neg_mean = first_reduce * ast_const(dtypes.float, -0.03125, (3, 27, 32, 1)) + # store = UOp(Ops.STORE, src=(g0, ShapeTracker.from_shape((3, 27, 32, 1)).to_uop(), mean)) + # verify_lazyop(store) + second_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((3, 27, 32, 1))),)) + squares = (second_x+neg_mean)*(second_x+neg_mean) + squares_sum = UOp(Ops.REDUCE_AXIS, dtypes.float, (squares,), (Ops.ADD, (2,))) + variance = squares_sum * ast_const(dtypes.float, 0.03125, (3, 27, 1, 1)) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((3, 27, 1, 1))), variance)) + sink = UOp(Ops.SINK, src=(store,)) + wanna_output = x.numpy().var(axis=2, ddof=0).reshape((3,27,1,1)) + helper_linearizer_ast(sink, [x], wanna_output=[wanna_output]) + # tinygrad ref + y_tiny = x.var(axis=2, correction=0).reshape(3,27,1,1) + np.testing.assert_allclose(y_tiny.numpy(), wanna_output, atol=1e-4, rtol=1e-4) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + def test_softmax_multireduce(self): + x = Tensor.rand(4, 32).realize() + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + first_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((4, 1, 32,)).expand((4, 32, 32))),)) + max_x = UOp(Ops.REDUCE_AXIS, dtypes.float, (first_x,), (Ops.MAX, (2,))) + second_x = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((4, 32, 1,))),)) + centered_x = second_x+max_x*ast_const(dtypes.float, -1, (4, 32, 1)) + exp_x = centered_x.alu(Ops.EXP2) + sum_exp_x = UOp(Ops.REDUCE_AXIS, dtypes.float, (exp_x,), (Ops.ADD, (1,))) + # y = exp_x * sum_exp_x.alu(Ops.RECIP) # kernels cannot do a return to full shape + recip_sum_exp_x = sum_exp_x.alu(Ops.RECIP) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((4,1,1))), recip_sum_exp_x)) + sink = UOp(Ops.SINK, src=(store,)) + expected = 1/np.exp2(x.numpy() - x.numpy().max(axis=-1, keepdims=True)).sum(axis=-1, keepdims=True).reshape(4,1,1) + helper_linearizer_ast(sink, [x], wanna_output=[expected]) + + @unittest.skipIf(CI and Device.DEFAULT in {"PTX", "AMD", "NV"}, "very slow") + def test_indexing_multireduce(self): + dataset = Tensor.rand(16384, 256).realize() + idxs = Tensor([0,3,5,6]).realize() + with Context(FUSE_ARANGE=1): + sink = dataset[idxs].contiguous().kernelize().uop.base.src[1].arg.ast + real_index = dataset.numpy()[idxs.numpy()].reshape(4, 256, 1, 1) + helper_linearizer_ast(sink, [dataset, idxs], wanna_output=[real_index]) + + # AssertionError: repeated stores in uops + def test_argmax_multireduce_axis0(self): + t = Tensor.randn(10, 20).realize() + t_max = t.max((0,)).realize() + real_argmax = np.argmax(t.numpy(), axis=0, keepdims=False).reshape(1, 20, 1) + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(20), arg=ShapeTracker(views=(View(shape=(1, 20, 1), strides=(0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(-1), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=10, src=( + x6:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 20, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), # noqa: E501 + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x8:=UOp(Ops.CONST, dtypes.int, arg=-1, src=( + x6,)), + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.MAX, (0,)), src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CAST, dtypes.int, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(200), arg=ShapeTracker(views=(View(shape=(10, 20, 1), strides=(20, 1, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(-1), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(20), arg=ShapeTracker(views=(View(shape=(10, 20, 1), strides=(0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(-1), arg=2, src=()),)),)),)), + UOp(Ops.CONST, dtypes.bool, arg=True, src=( + x21:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(10, 20, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), # noqa: E501 + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (2,)), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(11, 19), strides=(0, 0), offset=0, mask=((0, 11), (9, 19)), contiguous=False), View(shape=(10, 20, 10), strides=(1, 0, 20), offset=0, mask=None, contiguous=False))), src=()),)), # noqa: E501 + UOp(Ops.CONST, dtypes.int, arg=-1, src=( + x28:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(10, 20, 10), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), # noqa: E501 + UOp(Ops.CONST, dtypes.int, arg=0, src=( + x28,)),)),)), + UOp(Ops.CONST, dtypes.int, arg=10, src=( + x21,)),)),)),)),)),)), + x8,)),)),)) + helper_linearizer_ast(ast, [t, t_max], wanna_output=[real_argmax]) + + def test_argmax_multireduce_flat(self): + t = Tensor.randn(10, 20).realize() + t_max = t.max().realize() + real_argmax = np.argmax(t.numpy()) + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(1), arg=ShapeTracker(views=(View(shape=(1, 1), strides=(0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(-1), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=200, src=( + x6:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 1), strides=(0, 0), offset=0, mask=None, contiguous=True),)), src=()),)), # noqa: E501 + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x8:=UOp(Ops.CONST, dtypes.int, arg=-1, src=( + x6,)), + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.MAX, (0,)), src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CAST, dtypes.int, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(200), arg=ShapeTracker(views=(View(shape=(200, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(-1), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(200, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(-1), arg=2, src=()),)),)),)), + UOp(Ops.CONST, dtypes.bool, arg=True, src=( + x21:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(200, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), # noqa: E501 + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(201, 399), strides=(0, 0), offset=0, mask=((0, 201), (199, 399)), contiguous=False), View(shape=(200, 200), strides=(1, 400), offset=0, mask=None, contiguous=False))), src=()),)), # noqa: E501 + UOp(Ops.CONST, dtypes.int, arg=-1, src=( + x28:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(200, 200), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), # noqa: E501 + UOp(Ops.CONST, dtypes.int, arg=0, src=( + x28,)),)),)), + UOp(Ops.CONST, dtypes.int, arg=200, src=( + x21,)),)),)),)),)),)), + x8,)),)),)) + helper_linearizer_ast(ast, [t, t_max], wanna_output=[real_argmax]) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + def test_padto_sum_multireduce(self): + Tensor.manual_seed(0) + N = 17 + x = Tensor.rand(N, N).realize() + opts = [ + [Opt(OptOps.PADTO, 0, 32)], + [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], + # TODO: multireduce pads + # causes an issue because the acc won't be masked in the second reduce + # [Opt(OptOps.PADTO, 1, 32), Opt(OptOps.PADTO, 2, 32)] + ] + + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + x_ld0 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((1, N, N)).expand((N,N,N))),)) + x_ld1 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((N, 1, N))),)) + r0 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld0,), (Ops.ADD, (1,))) + r1 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld1+r0*ast_const(dtypes.float, -1, (N, 1, N)),),(Ops.ADD, (0,))) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((1,1,N))), r1)) + sink = UOp(Ops.SINK, src=(store,)) + helper_linearizer_ast(sink, [x], wanna_output=[(x.numpy()-x.numpy().sum(axis=0, keepdims=True)).sum(axis=0).reshape(1,1,N)], opts=opts) + + x_ld0 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((N, 1, N)).expand((N,N,N))),)) + x_ld1 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((N, N, 1))),)) + r0 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld0,), (Ops.ADD, (2,))) + r1 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld1+r0*ast_const(dtypes.float, -1, (N, N, 1)),), (Ops.ADD, (1,))) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((N,1,1))), r1)) + sink = UOp(Ops.SINK, src=(store,)) + helper_linearizer_ast(sink, [x], wanna_output=[(x.numpy()-x.numpy().sum(axis=1, keepdims=True)).sum(axis=1).reshape(N,1,1)], opts=opts) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + def test_padto_max_multireduce(self): + Tensor.manual_seed(0) + N = 17 + x = Tensor.rand(N, N).realize() + opts = [ + [Opt(OptOps.PADTO, 0, 32)], + [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),] + ] + + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(2)] + x_ld0 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((1, N, N)).expand((N,N,N))),)) + x_ld1 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((N, 1, N))),)) + r0 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld0,), (Ops.MAX, (1,))) + r1 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld1+r0*ast_const(dtypes.float, -1, (N, 1, N)),), (Ops.MAX, (0,))) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((1,1,N))), r1)) + sink = UOp(Ops.SINK, src=(store,)) + helper_linearizer_ast(sink, [x], wanna_output=[(x.numpy()-x.numpy().max(axis=0, keepdims=True)).max(axis=0).reshape(1,1,N)], opts=opts) + + x_ld0 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((N, 1, N)).expand((N,N,N))),)) + x_ld1 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(x.uop.st.reshape((N, N, 1))),)) + r0 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld0,), (Ops.MAX, (2,))) + r1 = UOp(Ops.REDUCE_AXIS, dtypes.float, (x_ld1+r0*ast_const(dtypes.float, -1, (N, N, 1)),), (Ops.MAX, (1,))) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((N,1,1))), r1)) + sink = UOp(Ops.SINK, src=(store,)) + helper_linearizer_ast(sink, [x], wanna_output=[(x.numpy()-x.numpy().max(axis=1, keepdims=True)).max(axis=1).reshape(N,1,1)], opts=opts) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI doesn't support multiple sync threads yet") + def test_padto_where_multireduce(self): + # ternary operators try to use both ridxs + + # we need to make sure the ternary operators nest properly + N = 17 + x = Tensor.rand(N, N).realize() + a = Tensor.rand(1, 1).realize() + b = Tensor.rand(1, 1).realize() + opts = [[Opt(OptOps.PADTO, 0, 32)],[Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),],] + + wanna_output = np.where(0.5*17 < (x.numpy()+np.where(0.75*17 < x.numpy().sum(axis=1,keepdims=True), a.numpy(), b.numpy())).sum(axis=1),0.0,1.0).reshape((N,1,1)) # noqa: E501 + ld0 = x.uop.st.reshape((N, 1, N)).expand((N,N,N)) + ld1 = x.uop.st.reshape((N, N, 1)) + ast = UOp(Ops.SINK, src=( + UOp(Ops.STORE, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, 1, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0),)), + UOp(Ops.WHERE, dtypes.float, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + ast_const(dtypes.float, 0.5*N, (N, 1, 1)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ld1, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1),)),)), + UOp(Ops.WHERE, dtypes.float, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + ast_const(dtypes.float, 0.75*N, (N, N, 1)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( + UOp(Ops.LOAD, dtypes.float, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ld0, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, N, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=2),)),)), + UOp(Ops.LOAD, dtypes.float, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, N, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=3),)),)),)),)),)),)), + ast_const(dtypes.float, 0.0, (N, 1, 1)), + ast_const(dtypes.float, 1.0, (N, 1, 1)),)),)),)) + helper_linearizer_ast(ast, [x,a,b], opts=opts, wanna_output=[wanna_output]) + + ld0 = x.uop.st.reshape((1, N, N)).expand((N,N,N)) + ld1 = x.uop.st.reshape((N, 1, N)) + wanna_output = np.where(0.5*17 < (x.numpy()+np.where(0.75*17 < x.numpy().sum(axis=0,keepdims=True), a.numpy(), b.numpy())).sum(axis=0),0.0,1.0).reshape(1,1,N) # noqa: E501 + ast = UOp(Ops.SINK, src=( + UOp(Ops.STORE, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(1, 1, N), strides=(0, 0, 1), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0, src=()),)), + UOp(Ops.WHERE, dtypes.float, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + ast_const(dtypes.float, 0.5*N, (1, 1, N)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0,)), src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ld1, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1, src=()),)),)), + UOp(Ops.WHERE, dtypes.float, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + ast_const(dtypes.float, 0.75*N, (N, 1, N)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.LOAD, dtypes.float, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ld0, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1, src=()),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, 1, N), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=2, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, 1, N), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=3, src=()),)),)),)),)),)),)), + ast_const(dtypes.float, 0.0, (1, 1, N)), + ast_const(dtypes.float, 1.0, (1, 1, N)),)),)),)) + helper_linearizer_ast(ast, [x,a,b], opts=opts, wanna_output=[wanna_output]) + # pad reduce axis + helper_linearizer_ast(ast, [x,a,b], opts=[[Opt(OptOps.PADTO, 1, 32)],], wanna_output=[wanna_output]) + + ld0 = x.uop.st.reshape((1,1,N,N)).expand((N,N,N,N)) + ld1 = x.uop.st.reshape((N,N,1,1)) + wanna_output = np.where(0.5*17 < (x.numpy()+np.where(0.75*17 < x.numpy().sum(keepdims=True), a.numpy(), b.numpy())).sum(keepdims=True),0.0,1.0).reshape((1,1,1,1))# noqa: E501 + ast = UOp(Ops.SINK, src=( + UOp(Ops.STORE, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(1, 1, 1, 1), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0, src=()),)), + UOp(Ops.WHERE, dtypes.float, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + ast_const(dtypes.float, 0.5*N, (1, 1, 1, 1)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 1)), src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, N, 1, 1), strides=(N, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1),)),)), + UOp(Ops.WHERE, dtypes.float, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + ast_const(dtypes.float, 0.75*N, (N, N, 1, 1)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2, 3)), src=( + UOp(Ops.LOAD, dtypes.float, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, N, N, N), strides=(0, 0, N, 1), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=1),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, N, 1, 1), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=2),)),)), + UOp(Ops.LOAD, dtypes.float, src=( + UOp(Ops.VIEW, dtypes.float.ptr(), arg=ShapeTracker(views=(View(shape=(N, N, 1, 1), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=3),)),)),)),)),)),)), + ast_const(dtypes.float, 0.0, (1, 1, 1, 1)), + ast_const(dtypes.float, 1.0, (1, 1, 1, 1)),)),)),)) + helper_linearizer_ast(ast, [x,a,b], opts=[[Opt(OptOps.PADTO, 0, 32)],], wanna_output=[wanna_output]) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + def test_end_local(self): + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), arg=i) for i in range(2)] + load = UOp(Ops.LOAD, dtypes.int, (g1.view(ShapeTracker.from_shape((32,))),)) + reduce = UOp(Ops.REDUCE_AXIS, dtypes.int, (load,), (Ops.ADD, (0,))) + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker.from_shape((1,))), reduce)) + sink = UOp(Ops.SINK, src=(store,)) + load_t = Tensor.full(load.st_arg.shape, 1).contiguous().realize() + k = helper_linearizer_ast(sink, [load_t], wanna_output=[load_t.numpy().sum()])[1] + self.assertEqual(k.uops[-2].op, Ops.ENDIF) + self.assertEqual(k.uops[-1].op, Ops.SINK) + self.assertLess(k.uops.index([x for x in k.uops if x.op is Ops.STORE][-1]), k.uops.index(k.uops[-1])) + + def test_two_nested_range(self): + a = Tensor.randn(2, ).realize() + out = a.reshape(2, 1).expand(2, 3).sum() + lin = helper_linearizer_opt(out, wanna_output=[np.broadcast_to(a.numpy().reshape(2, 1), (2, 3)).sum()])[0] + ranges = [i for i,u in enumerate(lin.uops) if u.op is Ops.RANGE] + assert len(ranges) == 1 # NOTE: it collapses now + # RANGE -> LOAD -> RANGE -> ASSIGN + #assert any(x.op is Ops.LOAD for x in lin.uops[ranges[0]:ranges[1]]) + + def test_three_nested_range(self): + a = Tensor.randn(2, ).realize() + out = a.reshape(2, 1).expand(2, 3).expand(2, 2, 3).sum() + lin = helper_linearizer_opt(out, wanna_output=[np.broadcast_to(np.broadcast_to(a.numpy().reshape(2, 1), (2, 3)), (2, 2, 3)).sum()])[0] + ranges = [i for i,u in enumerate(lin.uops) if u.op is Ops.RANGE] + assert len(ranges) == 1 # NOTE: it collapses now + # RANGE -> RANGE -> LOAD -> RANGE -> ASSIGN + # NOTE: nothing should toposort between the first two ranges + #assert ranges[0]+1 == ranges[1] + #assert any(x.op is Ops.LOAD for x in lin.uops[ranges[1]:ranges[2]]) + + def test_two_nested_range_alt_indexing(self): + a = Tensor([2, 2]).realize() + out = a.reshape(2, 1).pad(((1, 1), (1, 1)), value=2).sum() + lin = helper_linearizer_opt(out, wanna_output=[24])[0] + ranges = [i for i,u in enumerate(lin.uops) if u.op is Ops.RANGE] + # RANGE -> ALU -> RANGE -> ALU + LOAD -> ASSIGN + assert any(x.op in GroupOp.ALU for x in lin.uops[ranges[0]:ranges[1]]) + assert not any(x.op is Ops.LOAD for x in lin.uops[ranges[0]:ranges[1]]) + assert any(x.op in {*GroupOp.ALU, Ops.LOAD} for x in lin.uops[ranges[1]:]) + + def test_range_outer_op_before_phi(self): + a = Tensor.randn(4, 1).realize() + b = Tensor.randn(1, 1).realize() + out = (a + b[0]).sum() + b[0] + lin = helper_linearizer_opt(out, wanna_output=[(a.numpy()+b.numpy()[0]).sum()+b.numpy()])[0] + ranges = [i for i,u in enumerate(lin.uops) if u.op is Ops.RANGE] + # LOAD -> RANGE -> LOAD -> ASSIGN + assert len([x for x in lin.uops[:ranges[0]] if x.op is Ops.LOAD]) == 1 + + def test_range_outer_op_before_phi_nested_range(self): + a = Tensor.randn(2, ).realize() + b = Tensor.randn(1, 1).realize() + out = (a.reshape(2, 1).expand(2, 3) + b[0]).sum() + b[0] + lin = helper_linearizer_opt(out, wanna_output=[(np.broadcast_to(a.numpy().reshape(2, 1), (2, 3)) + b.numpy()[0]).sum() + b.numpy()])[0] + ranges = [i for i,u in enumerate(lin.uops) if u.op is Ops.RANGE] + assert len(ranges) == 1 # NOTE: it collapses now + #if getenv("PTX"): + # LOAD -> RANGE -> CAST -> ALU -> ALU -> LOAD -> ALU -> RANGE -> ALU -> ASSIGN + # assert lin.uops[ranges[0]-2].op is Ops.LOAD + # assert ranges[1] == ranges[0]+6 + # assert [x.op for x in lin.uops[ranges[1]-2:ranges[1]]] == [Ops.LOAD, Ops.ALU] + # LOAD -> RANGE -> LOAD -> ALU -> RANGE -> ASSIGN + #else: + # assert lin.uops[ranges[0]-2].op is Ops.LOAD + # assert ranges[1] == ranges[0]+3 + # assert [x.op for x in lin.uops[ranges[1]-2:ranges[1]]] == [Ops.LOAD, Ops.ALU] + + def test_range_outer_op_after_phi(self): + a = Tensor.randn(4, 1).realize() + out = a.sum() * a.sum() + lin = helper_linearizer_opt(out, wanna_output=[a.numpy().sum()*a.numpy().sum()])[0] + # RANGE -> LOAD -> ASSIGN -> ALU + end = max(i for i,u in enumerate(lin.uops) if u.op is Ops.ENDRANGE) + # the INDEX can be first + assert lin.uops[end+1].op in GroupOp.ALU or lin.uops[end+2].op in GroupOp.ALU + + def test_range_outer_op_after_phi_nested_range(self): + a = Tensor.randn(2, ).realize() + out = a.reshape(2, 1).expand(2, 3).sum() + a.reshape(2, 1).expand(2, 3).sum() + lin = helper_linearizer_opt(out, wanna_output=[(np.broadcast_to(a.numpy().reshape(2, 1), (2, 3))).sum()*2])[0] + # RANGE -> LOAD -> ASSIGN -> ALU + end = max(i for i,u in enumerate(lin.uops) if u.op is Ops.ENDRANGE) + # the INDEX can be first + assert lin.uops[end+1].op in GroupOp.ALU or lin.uops[end+2].op in GroupOp.ALU + + def test_load_dedup(self): + # for different leaves in the AST, the same loads may occur. + + a = Tensor.randn(4).realize() + # these are of size 3 to avoid float4 coalesce + r = a[:-1] + a[1:] + + k = Kernel(r.schedule()[-1].ast) + k.upcast() + k.linearize() + num_loads = len([uop for uop in k.uops if uop.op is Ops.LOAD]) + assert num_loads <= 4, "more load uops than needed" + assert num_loads >= 4, "unexpected number of uops, maybe this test needs updating?" + + @unittest.skipIf(getenv("PTX"), "broken on ptx for some reason") + def test_load_cache_const_bufs(self): + # make sure const buffers are differentiated from local and mem buffers + ST, DT = ShapeTracker(views=(View(shape=((1,)), strides=(0, 0), offset=0, mask=None, contiguous=False),)).to_uop(), dtypes.int + VAL = ast_const(DT, 2, ST.arg.shape) + g0, g1 = [UOp(Ops.DEFINE_GLOBAL, DT.ptr(), arg=i) for i in range(2)] + + # data1[0] + VAL + a = UOp(Ops.LOAD, DT, (g1.view(ST.arg),)) + VAL + # (literal const 1) + VAL + b = ast_const(DT, 1, ST.arg.shape) + VAL + + store = UOp(Ops.STORE, src=(g0.view(ST.arg), (a+b))) + sink = UOp(Ops.SINK, src=(store,)) + lin = Kernel(sink) + lin.linearize() + assert len(lin.uops) <= 10, "too many uops" + + def test_upcast_cse(self): + # when upcasting, within a subtree, there may be common expressions. + + a, b = Tensor.randn(1).realize(), Tensor.randn(1).realize() + r = a.expand([2]) + b.expand([2]) + + k = Kernel(r.schedule()[-1].ast) + k.upcast() + k.linearize() + num_ops = len([uop for uop in k.uops if uop.op in GroupOp.ALU]) + assert num_ops <= 1, "more alu uops than needed" + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") + def test_reduce_upcast(self): + x, w = Tensor.randn((1,1,3)).realize(), Tensor.randn((1,1,2)).realize() + r = Tensor.conv2d(x,w,padding=1).relu() + + k = Kernel(r.schedule()[-1].ast) + k.upcast() + k.upcast() + k.linearize() + accs = [u for u in k.uops if u.op is Ops.DEFINE_ACC] + stores = [u for u in k.uops if u.op is Ops.STORE] + assert len(accs) == 0 # it's removed now + assert len(stores) == 1 + assert stores[0].src[-1].dtype == dtypes.float.vec(4) + + # NOTE: can reenable, it does work. it just makes BEAM slow + @unittest.expectedFailure + @unittest.skipUnless(Device.DEFAULT == "CPU", "test only for CPU") + def test_upcast_with_locals_cpu(self): + out = Tensor.ones(64,64).contiguous() @ Tensor.ones(64,64).contiguous() + k = Kernel(out.schedule()[-1].ast) + k.apply_opt(Opt(OptOps.LOCAL, axis=0, arg=4)) + prg = k.to_program() + self.assertEqual(len(prg.src.split("for")), 5) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") + @unittest.skipIf(getenv("PTX"), "broken on ptx for some reason") + def test_upcast_with_locals(self): + x, y = Tensor.rand(1,128), Tensor.rand(128, 128) + r = (x@y).relu() + k = Kernel(r.schedule()[-1].ast) + k.apply_opts([Opt(op=OptOps.GROUP, axis=0, arg=8), Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4)]) + k.linearize() + + stores = [u for u in k.uops if u.op is Ops.STORE] + + # the first store is to lds and can be upcasted + assert stores[0].src[-1].dtype == dtypes.float.vec(4) + assert any(x.op is Ops.DEFINE_LOCAL for x in stores[0].toposort()) + # the second store is to gds with no upcasts + assert stores[1].src[-1].dtype == dtypes.float + assert any(x.op is Ops.DEFINE_GLOBAL for x in stores[1].toposort()) + + def test_zero_fold(self): + a, b = Tensor.randn(1).realize(), Tensor.randn(1).realize() + r = Tensor.stack(a, b) + + k = Kernel(r.schedule()[-1].ast) + k.upcast() + k.linearize() + num_ops = len([uop for uop in k.uops if uop.op in GroupOp.ALU]) + assert num_ops == 0, "more alu uops than needed" + + def test_sum_acc_dtype(self): + for tensor_dtype, acc_dtype in ( + (dtypes.bool, dtypes.int), (dtypes.int16, dtypes.int), (dtypes.float16, dtypes.float), (dtypes.bfloat16, dtypes.float)): + if is_dtype_supported(tensor_dtype) and is_dtype_supported(acc_dtype): + a = Tensor([1, 2, 3], dtype=tensor_dtype).sum() + k = Kernel(a.schedule()[-1].ast) + k.linearize() + local = [uop for uop in k.uops if uop.op is Ops.DEFINE_ACC] + assert local[0].dtype == acc_dtype + + def test_arg_acc_dtype(self): + def helper_arg_acc_dtype(c: Tensor, expected_dtype:DType): + k = Kernel(c.schedule()[-1].ast) + k.linearize() + local = [uop for uop in k.uops if uop.op is Ops.DEFINE_ACC] + assert local[0].dtype == expected_dtype + + tests = ( + (dtypes.float16, None, dtypes.float), + (dtypes.bfloat16, None, dtypes.float), + (dtypes.float, None, dtypes.float), + (dtypes.float16, dtypes.float16, dtypes.float16), + (dtypes.bfloat16, dtypes.bfloat16, dtypes.bfloat16), + (dtypes.float, dtypes.float16, dtypes.float16), + ) + for tensor_dtype, acc_dtype, expected_dtype in tests: + if is_dtype_supported(tensor_dtype) and is_dtype_supported(acc_dtype) and is_dtype_supported(expected_dtype): + a, b = Tensor.rand(8, 8, dtype=tensor_dtype), Tensor.rand(8, 8, dtype=tensor_dtype) + helper_arg_acc_dtype(a.sum(dtype=acc_dtype), expected_dtype) + helper_arg_acc_dtype(a.matmul(b, dtype=acc_dtype), expected_dtype) + helper_arg_acc_dtype(Tensor.einsum("ki,ij->kj", a, b, dtype=acc_dtype), expected_dtype) + d, w = Tensor.rand(4, 8, 8, 8, dtype=tensor_dtype), Tensor.rand(8, 8, 2, 2, dtype=tensor_dtype) + helper_arg_acc_dtype(d.conv2d(w, dtype=acc_dtype), expected_dtype) + + # TODO: don't skip bf16 for real device (METAL, AMD) + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + def test_tensor_cores(self): + for tc in Device[Device.DEFAULT].renderer.tensor_cores: + if not is_dtype_supported(tc.dtype_in) or not is_dtype_supported(tc.dtype_out): continue + # for AMX, tc.dims[2] == 1 so reduceop is None thus tensor_cores are not triggered + helper_tc_allclose(tc.dims[0], tc.dims[1], 2 if AMX else tc.dims[2], tc.dtype_in, tc.dtype_out, axis=0, tc_opt=0) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + def test_tensor_cores_emulation(self): + for tc in Device[Device.DEFAULT].renderer.tensor_cores: + if not is_dtype_supported(tc.dtype_in) or not is_dtype_supported(tc.dtype_out): continue + # for AMX, tc.dims[2] == 1 so reduceop is None thus tensor_cores are not triggered + helper_tc_allclose(tc.dims[0], tc.dims[1], 2 if AMX else tc.dims[2], tc.dtype_in, tc.dtype_out, axis=0, tc_opt=0, use_tensor_cores=3) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + def test_tensor_cores_codegen(self): + for tc in Device[Device.DEFAULT].renderer.tensor_cores: + if not is_dtype_supported(tc.dtype_in) or not is_dtype_supported(tc.dtype_out): continue + n, m, k = tc.dims[0], tc.dims[1], 2 if AMX else tc.dims[2] + a, b = Tensor.rand(m, k, dtype=tc.dtype_in), Tensor.rand(k, n, dtype=tc.dtype_in) + r = a.matmul(b, dtype=tc.dtype_out) + sched = r.schedule() + realized_ast = sched[-1].ast + kernel = Kernel(realized_ast) + kernel.apply_tensor_cores(1, axis=0, tc_select=-1, tc_opt=2) + kernel.linearize() + prg = kernel.to_program() + if Device.DEFAULT == "LLVM": + assert "0x201000" in prg.src + elif Device.DEFAULT == "AMD" and getenv("AMD_LLVM", 0): + assert "@llvm.amdgcn.wmma" in prg.src + elif Device[Device.DEFAULT].renderer.suffix == "PTX": + assert "mma.sync.aligned" in prg.src + else: + assert "__WMMA_" in prg.src + + @unittest.skipIf(Device.DEFAULT in ("AMD", "AMD_LLVM") or (Device.DEFAULT == "PYTHON" and getenv("EMULATE_AMD")), "broken for AMD") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + def test_tensor_cores_padded(self): + for tc in Device[Device.DEFAULT].renderer.tensor_cores: + if not is_dtype_supported(tc.dtype_in) or not is_dtype_supported(tc.dtype_out): continue + helper_tc_allclose(tc.dims[0]+(pad:=1), tc.dims[1]+pad, tc.dims[2]+pad, tc.dtype_in, tc.dtype_out, tc_opt=2) + + # AMD compiler bug: AMD miscompiles non-zero padded tc kernels with -O3, producing wrong results, nans or hang (see #9606) + # Internal bug: zero-stride dimensions combined with a mask may produce wrong index/valid for pad == 1 on AMD + @unittest.skipUnless(Device.DEFAULT in ("AMD", "AMD_LLVM") or (Device.DEFAULT == "PYTHON" and getenv("EMULATE_AMD")), "test for AMD's tc") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + @unittest.expectedFailure + def test_tensor_cores_padded_amd(self): + for tc in Device[Device.DEFAULT].renderer.tensor_cores: + if not is_dtype_supported(tc.dtype_in) or not is_dtype_supported(tc.dtype_out): continue + helper_tc_allclose(tc.dims[0]+(pad:=1), tc.dims[1]+pad, tc.dims[2]+pad, tc.dtype_in, tc.dtype_out, tc_opt=2) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + def test_tensor_cores_padded_uops(self): + for tc in Device[Device.DEFAULT].renderer.tensor_cores: + pad = 1 + + # check that TC is triggered for TC_OPT=2 + helper_tc_ensure_uops_and_opts_count(tc.dims[0]+pad, tc.dims[1]+pad, tc.dims[2]+pad, + tc.dtype_in, tc.dtype_out, tc_opt=2, ensure_triggered=True) + + # check that TC is not triggered for TC_OPT<2 + helper_tc_ensure_uops_and_opts_count(tc.dims[0]+pad, tc.dims[1]+pad, tc.dims[2]+pad, + tc.dtype_in, tc.dtype_out, tc_opt=1, ensure_triggered=False) + helper_tc_ensure_uops_and_opts_count(tc.dims[0]+pad, tc.dims[1]+pad, tc.dims[2]+pad, + tc.dtype_in, tc.dtype_out, tc_opt=0, ensure_triggered=False) + + # check excessive padding doesn't trigger padded TC in TC_OPT=2 + helper_tc_ensure_uops_and_opts_count(tc.dims[0]//4, tc.dims[1], tc.dims[2], tc.dtype_in, tc.dtype_out, tc_opt=2, ensure_triggered=False) + helper_tc_ensure_uops_and_opts_count(tc.dims[0], tc.dims[1]//4, tc.dims[2], tc.dtype_in, tc.dtype_out, tc_opt=2, ensure_triggered=False) + if not AMX: # AMX tc.dims[2] == 1 + helper_tc_ensure_uops_and_opts_count(tc.dims[0], tc.dims[1], tc.dims[2]//4, tc.dtype_in, tc.dtype_out, tc_opt=2, ensure_triggered=False) + + @unittest.skipIf(CI and Device.DEFAULT in {"AMD"}, "AMD CI is really slow here") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + def test_tensor_cores_multi_reduce(self): + for tc in Device[Device.DEFAULT].renderer.tensor_cores: + if not is_dtype_supported(tc.dtype_in) or not is_dtype_supported(tc.dtype_out): continue + # this will be a M=G16, N=G32, M=G16, M=G16, K=R16, K=R16, K=R16 with 9 choices of TC MNK axes + golden_result = None + for axis in range(9): + a = Tensor.rand(16, 16, 29, 29, dtype=tc.dtype_in).realize() + b = Tensor.rand(32, 16, 16, 16, dtype=tc.dtype_in).realize() + c = a.conv2d(b, padding=1, dtype=tc.dtype_out) + realized_ast, real_bufs = helper_realized_ast(c) + + k = Kernel(realized_ast) + k.apply_tensor_cores(1, axis=axis, tc_opt=2) + k.linearize() + assert len([uop for uop in k.uops if uop.op is Ops.WMMA]) > 0, "tensor core not triggered" + assert len([x for x in k.applied_opts if x.op is OptOps.TC]) == 1, "tensor core opt not included" + + prg = CompiledRunner(k.to_program()) + # TODO: support this even if numpy doesn't + if _to_np_dtype(real_bufs[0].dtype) is None: continue + real_bufs[0].copyin(np.zeros((real_bufs[0].size, ), dtype=_to_np_dtype(real_bufs[0].dtype)).data) # Zero to check that all values are filled + prg.exec(real_bufs) + result = np.frombuffer(real_bufs[0].as_buffer(), _to_np_dtype(real_bufs[0].dtype)) + + # ensure the results for each choice of axis matches + if golden_result is None: golden_result = np.frombuffer(real_bufs[0].as_buffer(), _to_np_dtype(real_bufs[0].dtype)) + np.testing.assert_allclose(result, golden_result, atol=0.1, rtol=0.2) + + # check that get_kernel_actions produces all 9 options + from tinygrad.opt.search import get_kernel_actions + tc_actions = [k for i, k in get_kernel_actions(Kernel(realized_ast), False).items() if k.applied_opts[0].op == OptOps.TC] + + available_tc = len([x for x in Device[Device.DEFAULT].renderer.tensor_cores if x.dtype_in == tc.dtype_in and x.dtype_out == tc.dtype_out]) + assert len(tc_actions) == 9 * available_tc, f"should contain 9 possible TC actions for every available TC, got {len(tc_actions)}" + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + def test_tensor_cores_unroll_phi(self): + tc = Device[Device.DEFAULT].renderer.tensor_cores[0] + x, y = Tensor.rand(128, 128, dtype=tc.dtype_in), Tensor.rand(128, 128, dtype=tc.dtype_in) + r = x.matmul(y, dtype=tc.dtype_out) + k = helper_linearizer_opt(r, [[Opt(OptOps.UNROLL, 0, 4)]], apply_tc=True, atol=3e-2, rtol=1e-3)[-1] + for u in k.uops: + if u.op is Ops.WMMA: + assert u.src[-1].src[0].op != Ops.ASSIGN + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + @unittest.skipIf(Device.DEFAULT in {"CPU", "LLVM"}, "CPU does not support using a different type for accumulation") + def test_tensor_cores_unroll_casted_phi(self): + tc = [tc for tc in Device[Device.DEFAULT].renderer.tensor_cores if tc.dtype_in != tc.dtype_out][0] + x, y = Tensor.rand(128, 128, dtype=tc.dtype_in), Tensor.rand(128, 128, dtype=tc.dtype_in) + r = x.matmul(y, dtype=tc.dtype_out) + k = helper_linearizer_opt(r, [[Opt(OptOps.UNROLL, 0, 4)]], apply_tc=True, atol=3e-2, rtol=1e-3)[-1] + for u in k.uops: + if u.op is Ops.WMMA: + #assert u.src[-1].dtype == dtypes.float.vec(prod(tc.thread_local_sizes[2])) + assert u.src[-1].src[0].op != Ops.ASSIGN + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + @unittest.skipIf(Device.DEFAULT in {"CPU", "LLVM"}, "CPU does not support using a different type for accumulation") + def test_tensor_cores_unroll_casted_phi_with_children(self): + # all ASSIGN children are outside the loop + tc = [tc for tc in Device[Device.DEFAULT].renderer.tensor_cores if tc.dtype_in != tc.dtype_out][0] + x, y = Tensor.rand(128, 128, dtype=tc.dtype_in), Tensor.rand(128, 128, dtype=tc.dtype_in) + r = x.matmul(y, dtype=tc.dtype_out).relu() + k = helper_linearizer_opt(r, [[Opt(OptOps.UNROLL, 0, 4)]], apply_tc=True, atol=3e-2, rtol=1e-3)[-1] + for u in k.uops: + if u.op is Ops.WMMA: + #assert u.src[-1].dtype == dtypes.float.vec(prod(tc.thread_local_sizes[2])) + assert u.src[-1].src[0].op != Ops.ASSIGN + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") + def test_simple_unroll_no_between_phi_dependencies(self): + x, y = Tensor.rand(128, 128), Tensor.rand(128, 128) + r = (x@y).relu() + k = helper_linearizer_opt(r, [[Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UPCAST, 0, 4)]])[-1] + # the uops graph is RANGE -> DEFINE_ACC -> 4x ALU -> 4x ASSIGN -> ENDRANGE + for u in k.uops: + if u.op is Ops.ASSIGN: + assert u.src[1].op in GroupOp.ALU + # children of ASSIGN are placed after ENDRANGE + if any(x.op is Ops.ASSIGN for x in u.src): + end_range = [i for i, x in enumerate(k.uops) if x.op is Ops.ENDRANGE][0] + assert end_range < k.uops.index(u) + + def test_grouped_dims(self): + def _assert_grouped_dims(prefix, dims, max_sizes, reverse_dims, expected_sizes, assert_same_length = True): + idxs = get_grouped_dims(prefix, dims, max_sizes, reverse_dims) + loop_idxs = dedup(flatten([[y for y in x.toposort() if y.op is Ops.SPECIAL] for x in idxs])) + loop_idxs = sorted(loop_idxs, key=lambda uop: uop.arg[0]) + sizes = [x.arg[1] for x in loop_idxs] + assert len(idxs) == len(dims), f"expected idxs to have same length as dims {len(dims)}, got {len(idxs)}" + if assert_same_length: + assert len(loop_idxs) == min(len(sizes), len(dims)), f"expected idxs to have length {min(len(sizes), len(dims))}, got {len(loop_idxs)}" + assert sizes == expected_sizes, f"expected sizes={expected_sizes}, got {sizes=}" + # TODO: add these back after uop symbolic + # for i in range(len(dims)): + # assert idxs[i].max+1 == dims[i], f"idxs[{i}] should have max {dims[i]-1}" + # for i in range(len(loop_idxs)): + # assert loop_idxs[i].expr.startswith(prefix), f"loop_idxs[{i}] must start with {prefix}" + # assert loop_idxs[i].max+1 == sizes[i], f"loop_idxs[{i}] should have max {sizes[i]-1}" + + # no-op + _assert_grouped_dims("gidx", (2,), (16,16,16), False, [2]) + _assert_grouped_dims("gidx", (2,3), (16,16,16), False, [2,3]) + + # check reverse dims + _assert_grouped_dims("gidx", (2,3), (16,16,16), True, [3,2]) + _assert_grouped_dims("gidx", (2,3,4), (16,16,16), False, [2,3,4]) + + # test splitting globals: len(dims) == len(max) + _assert_grouped_dims("gidx", (64,3,4), (16,16,16), False, [16,12,4]) + _assert_grouped_dims("gidx", (64,3,4), (16,4,16), False, [16,3,16]) + _assert_grouped_dims("gidx", (64,3,4), (16,16,16), True, [16,3,16]) + _assert_grouped_dims("gidx", (128,3,4), (16,4,256), False, [16,3,32]) + _assert_grouped_dims("gidx", (4,4,512), (16,4,256), False, [8,4,256]) + + # prefer group_dim strategy when possible + _assert_grouped_dims("gidx", (512,4,2), (8192,2,2), False, [2048,2]) + + # test splitting globals: len(dims) < len(max) + # len(dim) -> len(limited) + # 1 -> 2 + _assert_grouped_dims("gidx", (128,), (16,16,256), False, [16,8], False) + # 1 -> 3 + _assert_grouped_dims("gidx", (65536,), (16,16,256), False, [16,16,256], False) + # 2 -> 3 + _assert_grouped_dims("gidx", (128,128), (16,16,256), False, [16,16,64], False) + # test when the only divisor is the square root of dim + _assert_grouped_dims("gidx", (121,), (12,12,12), False, [11,11], False) + + # collapse on onto the left most axis + _assert_grouped_dims("gidx", (2,3,4,5), (16,16,16), False, [6,4,5]) + _assert_grouped_dims("gidx", (2,3,4,5), (32,16,16), True, [20,3,2]) + # _assert_grouped_dims("gidx", (Variable("start_pos",1,2),3,4,5), (32,16,16), True, [20,3,Variable("start_pos",1,2)]) + + # collapse on left-most available axis (the left most is too small) + _assert_grouped_dims("gidx", (2,3,4,5), (4,16,16), False, [2,12,5]) + _assert_grouped_dims("gidx", (2,3,4,5), (16,16,16), True, [5,12,2]) + + # _assert_grouped_dims("gidx", (Variable("start_pos",1,2),3,4,5), (16,16,16), False, [Variable("start_pos",1,2)*3,4,5]) + + # dim too large and not factorable + with self.assertRaises(RuntimeError): + get_grouped_dims("gidx", (23,), (16,16,16), False,) + with self.assertRaises(RuntimeError): + get_grouped_dims("gidx", (128,3,4), (16,2,2), False,) + + # too large for sizes + with self.assertRaises(RuntimeError): + get_grouped_dims("gidx", (2,3,4,5,6), (16,16,16)) + + # # variable too large + # with self.assertRaises(AssertionError): + # get_grouped_dims("gidx", (Variable("start_pos",0,16),3,4), (16,16,16), False,) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + def test_default_global_reversed(self): + # shrink so that the dims do not collapse + t = Tensor.ones(5, 6, 7).contiguous().realize().shrink(((0, 4), (0, 5), (0, 6))) + k = helper_linearizer_opt(t+1)[0] + idxs = dedup([uop for uop in k.uops if uop.op is Ops.SPECIAL]) + idxs = sorted(idxs, key=lambda uop: uop.arg[0]) + assert idxs[0].arg == ('gidx0', 6), idxs[0].arg + assert idxs[1].arg == ('gidx1', 5), idxs[1].arg + assert idxs[2].arg == ('gidx2', 4), idxs[2].arg + + def test_sum_collapse(self): + t = Tensor([2]).reshape(1, 1).expand(256, 256).sum() + sched = [si for si in t.schedule() if si.ast.op is Ops.SINK] + # sum_collapse is a full collapse now + assert len(sched) == 1 + assert not any(u.op is Ops.REDUCE_AXIS for u in sched[0].ast.toposort()), "found reduce in sum collapse" + #lin = Kernel(sched[0].ast) + #assert not any(u.op is Ops.RANGE for u in lin.linearize().uops), "found loop in sum collapse" + + def test_assign_fold(self): + a = Tensor.ones(4, 4).contiguous().realize() + m = Tensor.ones(4, 4).shrink(((1, 2), None)).pad(((1, 2), None)) + a.assign(a+m) + a.realize() + np.testing.assert_equal(a.flatten().numpy(), [1.,1.,1.,1.,2.,2.,2.,2.,1.,1.,1.,1.,1.,1.,1.,1.]) + + def test_where_fold(self): + a = Tensor.ones(4, 4).contiguous().realize() + b = a.shrink(((1, 2), None)).pad(((1, 2), None)) + a.assign(b.where(2, a)) + sched = a.schedule() + assert len(sched) == 1 + sched_copy = sched[:] + run_schedule(sched) + np.testing.assert_equal(a.flatten().numpy(), [1.,1.,1.,1.,2.,2.,2.,2.,1.,1.,1.,1.,1.,1.,1.,1.]) + lin = Kernel(sched_copy[-1].ast) + lin.linearize() + assert not any(u.op == Ops.WHERE for u in lin.uops), "found where where where should be folded" + + def test_phi_simplification(self): + def helper(t, max_ops=0): + k = helper_linearizer_opt(t)[-1] + uops = list(k.linearize().uops) + # ignore kernel optimized IF statements for now + if if_op:=next((u for u in uops if u.op is Ops.IF), None): + uops = uops[:uops.index(if_op)] + assert len(set([u.op for u in uops if u.op in {Ops.RANGE, Ops.SPECIAL}])) == 1, "has either specials or ranges, not both" + assert len([u for u in uops if u.op is Ops.ASSIGN]) == 0, "ASSIGN should have been simplified" + # TODO: once uops track min/max this will be fixed + #assert len([u for u in uops if u.op is Ops.MAX]) <= max_ops, "no unnecessary MAX ops" + + helper(Tensor.arange(5.5, (3.5*300), 3.5), max_ops=2) + helper(Tensor.arange(-1, -100, -5), max_ops=2) + # NOTE: both of these split the reduce (this just wasn't tracked before) + #helper(Tensor.arange(-3.2, 6.7, 0.64), max_ops=2) + #helper(Tensor.arange(256), max_ops=2) + helper(Tensor.arange(255), max_ops=2) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") + def test_grouped_store_phis(self): + """ + float4 acc0 = float4(0.0,0.0,0.0,0.0); + { + acc0 = // ... + } + *((device float4*)(data0+alu2)) = float4(acc0.x,acc0.y,acc0.z,acc0.w); + simplifies to: + *((device float4*)(data0+alu2)) = acc0; + """ + x, y = Tensor.randn(64,64), Tensor.randn(64,64) + out = x.matmul(y) + k = helper_linearizer_opt(out)[-1] + # check that the float4 cast collapses + store_vals = [u.src[-1] for u in k.uops if u.op is Ops.STORE] + for val in store_vals: + assert val.dtype == dtypes.float.vec(4) # and val.op is not Ops.VECTORIZE + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") + def test_arange_opts(self): + a = Tensor.arange(128) + helper_linearizer_opt(a, [ + [Opt(OptOps.GROUP, 0, 32)], + [Opt(OptOps.GROUPTOP, 0, 32)], + [Opt(op=OptOps.LOCAL, axis=0, arg=8)], + [Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=0, arg=0)], + [Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=8)], + [Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=8), Opt(op=OptOps.UNROLL, axis=1, arg=4)], # noqa: E501 + ]) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") + def test_grouped_store_values(self): + x = Tensor.randn((4,3,6,6)).realize() + out = x.flip((0,1)).contiguous() + k = helper_linearizer_opt(out)[-1] + store_val = [u.src[-1] for u in k.uops if u.op is Ops.STORE][0] + assert store_val.dtype == dtypes.float.vec(4) and store_val.op is not Ops.VECTORIZE + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") + def test_grouped_store_locals_and_globals(self): + x, y = Tensor.rand(128, 128), Tensor.rand(128, 128) + out = x@y + opt = [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.GROUPTOP, 0, 8), + Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UPCAST, 1, 2)] # upcast accs in both reduces + k = helper_linearizer_opt(out, opts=[opt])[-1] + def get_recursive(uop): return set.union(set(uop.src), [uop], *[get_recursive(v) for v in uop.src]) + local_stores = [u for u in k.uops if u.op is Ops.STORE and any(x.op is Ops.DEFINE_LOCAL for x in get_recursive(u.src[0]))] + global_stores = [u for u in k.uops if u.op is Ops.STORE and any(x.op is Ops.DEFINE_GLOBAL for x in get_recursive(u.src[0]))] + barrier = [u for u in k.uops if u.op is Ops.BARRIER][0] + # check that the float4 cast collapses for all stores + for store in local_stores+global_stores: + assert store.src[-1].dtype.count > 1 # and store.src[2].op is not Ops.VECTORIZE + # # check the children's vins + # TODO: src ALU are not the same, should it? + # assert barrier.src == tuple(local_stores) + assert len([u for u in k.uops if u.op is Ops.IF and u.src[-1] == barrier]) == 1 + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") + def test_grouped_store_local_only(self): + x, y = Tensor.rand(1,128), Tensor.rand(128, 128) + r = (x@y).relu() + k = helper_linearizer_opt(r)[-1] + stores = [u for u in k.uops if u.op is Ops.STORE] + + # the float4 value stores directly in lds and we skip upcast + self.assertEqual(stores[0].src[-1].dtype, dtypes.float.vec(4)) + #assert stores[0].src[-1].op is not Ops.VECTORIZE + + # the global store doesn't change + assert stores[1].src[-1].dtype == dtypes.float + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") + def test_skip_unmatching_upcasts(self): + Tensor.manual_seed(0) + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(9600), arg=ShapeTracker(views=(View(shape=(240, 40, 1, 1), strides=(40, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9600), arg=0, src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(9600), arg=ShapeTracker(views=(View(shape=(240, 40, 1, 1), strides=(1, 240, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9600), arg=1, src=()),)),)),)),)) + opt = [ + Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=16), + Opt(op=OptOps.LOCAL, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=3, arg=2) + ] + k = helper_linearizer_ast(ast, [Tensor.randn(240*40).realize()], opts=[opt])[-1] + out = [u for u in k.uops if u.op is Ops.STORE][0] + assert out.src[-1].op is Ops.VECTORIZE and out.src[-1].dtype == dtypes.float.vec(4) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "test requires float4") + def test_skip_unmatching_upcasts_with_gep(self): + Tensor.manual_seed(0) + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(256), arg=ShapeTracker(views=(View(shape=(8, 32, 1, 1), strides=(32, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(256), arg=0, src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(256), arg=ShapeTracker(views=(View(shape=(8, 32, 1, 1), strides=(1, 8, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(256), arg=1, src=()),)),)),)),)) + opt = [Opt(op=OptOps.LOCAL, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=2, arg=2), Opt(op=OptOps.LOCAL, axis=1, arg=8), + Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=8), + Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=0, arg=2)] + k = helper_linearizer_ast(ast, [Tensor.randn(8*32).realize()], opts=[opt])[-1] + out = [u for u in k.uops if u.op is Ops.STORE][0] + assert out.src[-1].op is Ops.VECTORIZE and out.src[-1].dtype.count != 1 + +@unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "need backends that support float4") +class TestFloat4(unittest.TestCase): + @staticmethod + def count_float4(k, n=4): + return (len([uop for uop in k.uops if uop.op is Ops.LOAD and uop.dtype == dtypes.float.vec(n)]), + len([uop for uop in k.uops if uop.op is Ops.STORE and uop.src[-1].dtype == dtypes.float.vec(n)])) + @staticmethod + def count_half4(k): + return (len([uop for uop in k.uops if uop.op is Ops.LOAD and uop.dtype == dtypes.half.vec(4)]), + len([uop for uop in k.uops if uop.op is Ops.STORE and uop.src[-1].dtype == dtypes.half.vec(4)])) + + def test_float4_basic(self): + a = Tensor.empty(2, 8).realize() + b = Tensor.empty(2, 8).realize() + c = a + b + + s = c.schedule()[0] + k = Kernel(s.ast) + k.apply_opts([Opt(op=OptOps.UPCAST, axis=0, arg=4)]) + k.linearize() + + assert TestFloat4.count_float4(k) == (2, 1) + + @unittest.skipIf(Device.DEFAULT in {"CPU", "LLVM"} and AMX, "CPU with AMX upcasts float up to size 16") + def test_float4_multidim(self): + a = Tensor.empty(2, 8).realize() + b = Tensor.empty(2, 8).realize() + c = a + b + + s = c.schedule()[0] + k = Kernel(s.ast) + k.shift_to(0, 4) # float4 dimension + k.shift_to(0, 2, insert_before=k.shape_len-1) + k.upcast() + k.upcast() + k.local_dims += 1 + k.linearize() + + assert TestFloat4.count_float4(k) == (4, 2) + + @unittest.skipUnless(Device.DEFAULT in {"CPU", "LLVM"} and AMX, "Only CPU with AMX upcasts float up to size 16") + def test_float4_multidim_amx(self): + def kernel_for_shape(size, shift): + a = Tensor.empty(2, size).realize() + b = Tensor.empty(2, size).realize() + c = a + b + + s = c.schedule()[0] + k = Kernel(s.ast) + k.shift_to(0, 4) + k.shift_to(0, shift, insert_before=k.shape_len-1) + k.upcast() + k.upcast() + k.local_dims += 1 + k.linearize() + return k + + sizes = [12, 8, 16] + shifts = [3, 2, 4] + excepted_upcast_size = [4, 8, 16] + expected_output = [(6,3), (2,1), (2,1)] + + for i in range(len(sizes)): + assert TestFloat4.count_float4(kernel_for_shape(sizes[i], shifts[i]), excepted_upcast_size[i]) == expected_output[i] + + def test_float4_unaligned_load(self): + a = Tensor.empty(9).realize().shrink(((1, 9),)) + b = Tensor.empty(9).realize().shrink(((1, 9),)) + c = a + b + + s = c.schedule()[0] + k = Kernel(s.ast) + k.apply_opts([Opt(op=OptOps.UPCAST, axis=0, arg=4)]) + k.linearize() + + assert TestFloat4.count_float4(k) == (0, 1) + + @unittest.skipIf(Device.DEFAULT in {"CPU", "LLVM"} and AMX, "CPU with AMX upcasts float up to size 16") + def test_float4_multidim_unaligned_load(self): + a = Tensor.empty(2, 9).realize().shrink(((0, 2), (1, 9),)) + b = Tensor.empty(2, 9).realize().shrink(((0, 2), (1, 9),)) + c = a + b + + s = c.schedule()[0] + k = Kernel(s.ast) + k.shift_to(len(k.full_unupcasted_shape)-1, 4) # manual trigger float4 dim + k.upcast() + k.shift_to(len(k.full_unupcasted_shape)-1, 2, insert_before=k.shape_len-1) + k.upcast() + k.local_dims += 1 + k.linearize() + + assert TestFloat4.count_float4(k) == (0, 2) + + @unittest.skipUnless(Device.DEFAULT in {"CPU", "LLVM"} and AMX, "Only CPU with AMX upcasts float up to size 16") + def test_float4_multidim_unaligned_load_amx(self): + def kernel_for_shape(size, shift): + a = Tensor.empty(2, size).realize().shrink(((0, 2), (1, size),)) + b = Tensor.empty(2, size).realize().shrink(((0, 2), (1, size),)) + c = a + b + + s = c.schedule()[0] + k = Kernel(s.ast) + k.shift_to(len(k.full_unupcasted_shape)-1, 4) # manual trigger float4 dim + k.upcast() + k.shift_to(len(k.full_unupcasted_shape)-1, shift, insert_before=k.shape_len-1) + k.upcast() + k.local_dims += 1 + k.linearize() + return k + + sizes = [13, 9, 17] + shifts = [3, 2, 4] + excepted_upcast_size = [4, 8, 16] + expected_output = [(0,3), (0,1), (0,1)] + + for i in range(len(sizes)): + assert TestFloat4.count_float4(kernel_for_shape(sizes[i], shifts[i]), excepted_upcast_size[i]) == expected_output[i] + + def test_float4_sometimes_unaligned(self): + a = Tensor.empty(1, 1, 8).realize() + b = Tensor.empty(1, 1, 5).realize().shrink(((0, 1), (0, 1), (1, 5))) + c = a.conv2d(b) + # only the first and last conv dot products are aligned in a, and b is never aligned, so no + # float4 should be emitted (the reduce axis of size 4 is the float4 axis here) + + s = c.schedule()[0] + k = Kernel(s.ast) + k.upcast() + k.linearize() + + assert TestFloat4.count_float4(k) == (0, 0) + + def test_float4_multidim_sometimes_unaligned(self): + a = Tensor.empty(1, 1, 7).realize() + b = Tensor.empty(1, 1, 5).realize().shrink(((0, 1), (0, 1), (1, 5))) + c = a.conv2d(b) + # the first conv dot product is aligned in a. If we upcast the output and reduce + # dimension, then we could do float4 for only that one set of loads, but we currently + # don't. + # UPDATE: now we do this fusion + + s = c.schedule()[0] + k = Kernel(s.ast) + k.upcast() + k.upcast() + k.linearize() + + assert TestFloat4.count_float4(k) in {(0,1), (1,1)} + + def test_float4_noncontiguous(self): + a = Tensor.empty(4, 2).realize() + b = Tensor.empty(4, 2).realize() + c = a + b + + # we will upcast the top axis of sz 4. they should not be coalesced into float4, + # since the top axis is not contiguous. + + s = c.schedule()[0] + k = Kernel(s.ast) + k.shift_to(0, 4, top=True) # top axes are float4 axes + k.upcast() + k.linearize() + + assert TestFloat4.count_float4(k) == (0, 0) + + def test_float4_expand(self): + a = Tensor.empty(9).realize().shrink(((1, 9),)) + b = Tensor.empty(2).realize().reshape((2, 1)).expand((2,4)).reshape((8,)) + c = a + b + + # we will upcast the top axis of sz 4. they should not be coalesced into float4, + # since the top axis is not contiguous. + + s = c.schedule()[0] + k = Kernel(s.ast) + k.shift_to(0, 4) # float4 axis + k.upcast() + k.linearize() + + assert TestFloat4.count_float4(k) == (0, 1) + + def test_float4_heterogeneous(self): + a = Tensor.empty(8).realize() + b = Tensor.empty(9).realize().shrink(((1, 9),)) + c = a + b + + # should float4 b but not a + + s = c.schedule()[0] + k = Kernel(s.ast) + k.shift_to(0, 4) # float4 axis + k.upcast() + k.linearize() + + assert TestFloat4.count_float4(k) == (1, 1) + + def test_half4_load_unrolled(self): + # from llama 7B shard 4 gpus + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(96000), arg=ShapeTracker(views=(View(shape=(1, 3, 32000, 1), strides=(0, 32000, 1, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96000), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(9216), arg=ShapeTracker(views=(View(shape=(1, 3, 32000, 1024), strides=(0, 4096, 0, 1), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(9216), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(32768000), arg=ShapeTracker(views=(View(shape=(1, 3, 32000, 1024), strides=(0, 0, 1024, 1), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(32768000), arg=2, src=()),)),)),)),)),)),)),)) + + # TODO: fix this, expected might change but should be positive + for expected, opts in [ + ((7, 0), [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=3), Opt(op=OptOps.UNROLL, axis=0, arg=4)]), + ((5, 0), [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4)]), + ((2, 0), [Opt(op=OptOps.UNROLL, axis=0, arg=4)]), + ]: + k = Kernel(ast) + k.apply_opts(opts) + k.linearize() + count = TestFloat4.count_half4(k) + assert count == expected, f"{count=}, {expected=}" + + @unittest.skip("this doesn't happen anymore") + def test_float4_acc(self): + # from float32 stable diffusion red tinybox + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(33554432), arg=ShapeTracker(views=(View(shape=(1, 1, 128, 512, 512, 1, 1, 1), strides=(0, 0, 262144, 512, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(33554432), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(67108864), arg=ShapeTracker(views=(View(shape=(1, 1, 1, 256, 4, 514, 4, 514), strides=(0, 0, 0, 262144, 0, 512, 0, 1), offset=-513, mask=((0, 1), (0, 1), (0, 1), (0, 256), (0, 4), (1, 513), (0, 4), (1, 513)), contiguous=False), View(shape=(1, 1, 128, 512, 512, 256, 3, 3), strides=(0, 0, 0, 2056, 1, 4227136, 1058840, 515), offset=0, mask=None, contiguous=False))), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(67108864), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(294912), arg=ShapeTracker(views=(View(shape=(1, 1, 128, 512, 512, 256, 3, 3), strides=(0, 0, 2304, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(294912), arg=2, src=()),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(128), arg=ShapeTracker(views=(View(shape=(1, 1, 128, 512, 512, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(128), arg=3, src=()),)),)),)),)),)) + + for expected, opts in [ + (1, [Opt(op=OptOps.UPCAST, axis=2, arg=4)]), + (4, [Opt(op=OptOps.UPCAST, axis=2, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4)]), + ]: + k = Kernel(ast) + k.apply_opts(opts) + k.linearize() + count = len([uop for uop in k.uops if uop.op is Ops.DEFINE_ACC and uop.dtype == dtypes.float.vec(4)]) + assert count == expected, f"{count=}, {expected=}" + + @unittest.skip("this doesn't happen anymore") + def test_float2_acc(self): + # from resnet + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(212926464), arg=ShapeTracker(views=(View(shape=(1, 256, 1, 64, 1, 114, 1, 114), strides=(0, 831744, 0, 12996, 0, 114, 0, 1), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(212926464), arg=0, src=()),)), + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (4, 6)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(462422016), arg=ShapeTracker(views=(View(shape=(256, 64, 3, 56, 2, 3, 56, 2), strides=(1806336, 28224, 3, 504, 0, 1, 9, 0), offset=0, mask=((0, 256), (0, 64), (0, 3), (0, 56), (0, 1), (0, 3), (0, 56), (0, 1)), contiguous=False), View(shape=(256, 64, 3, 115, 3, 115), strides=(7225344, 112896, 37632, 336, 112, 1), offset=0, mask=((0, 256), (0, 64), (0, 3), (0, 112), (0, 3), (0, 112)), contiguous=False), View(shape=(256, 64, 456, 456), strides=(7617600, 119025, 345, 1), offset=0, mask=((0, 256), (0, 64), (0, 345), (0, 345)), contiguous=False), View(shape=(1, 256, 1, 64, 4, 114, 4, 114), strides=(0, 13307904, 0, 207936, 51984, 456, 114, 1), offset=0, mask=None, contiguous=True))), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(462422016), arg=1, src=()),)),)),)),)),)),)),)) + for expected, opts in [ + (16, [Opt(op=OptOps.LOCAL, axis=1, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=2, arg=2), Opt(op=OptOps.LOCAL, axis=2, arg=3), Opt(op=OptOps.UPCAST, axis=3, arg=4)]), # noqa: E501 + (4, [Opt(op=OptOps.LOCAL, axis=1, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=2, arg=2)]), + ]: + k = Kernel(ast) + k.apply_opts(opts) + k.linearize() + count = len([uop for uop in k.uops if uop.op is Ops.DEFINE_ACC and uop.dtype == dtypes.float.vec(2)]) + assert count == expected, f"{count=}, {expected=}" + +class TestHandCodedOpts(unittest.TestCase): + def test_masked_upcast(self): + layer_1 = Tensor.cat(*[Tensor.empty(5) for _ in range(4)]) + layer_2 = Tensor.cat(layer_1.unsqueeze(0), Tensor.empty(6, 20)) + + s = layer_2.schedule()[-1] + k = Kernel(s.ast) + k.apply_opts(hand_coded_optimizations(k)) + assert len(k.bufs) == 6 # make sure all ops are done in one kernel + # masked upcast should upcast masked axis of size 7 + # masked upcast should not upcast large (20) last axis + # float4/other hcopt shouldn't upcast last axis, since we already have 7 upcast, and the last axis is not very contiguous + assert k.upcasted == 1 and k.full_shape[-1] == 7 + + @unittest.skipIf(Device.DEFAULT in {"METAL", "WEBGPU"}, "METAL/WEBGPU split this kernel since it has 37 buffers") + def test_masked_upcast_wino(self): + monster = Tensor.stack(*[Tensor.stack(*[Tensor.empty(16) for _ in range(6)]) for _ in range(6)]) + + s = monster.schedule()[-1] + k = Kernel(s.ast) + k.apply_opts(hand_coded_optimizations(k)) + assert len(k.bufs) == 37 # make sure all ops are done in one kernel + # should upcast the two Tensor.stacks + assert k.upcasted >= 2 and k.full_shape[k.shape_len-k.upcasted:k.shape_len].count(6) == 2 + + def test_masked_upcast_wino_full(self): + with Context(WINO=1): + x,w = Tensor.rand(1,4,8,8, requires_grad=True).realize(), Tensor.rand(4,4,3,3, requires_grad=True).realize() + out = Tensor.conv2d(x,w, padding=1) + out.mean().backward() + + upcasts = [] + wino_schedule = out.schedule() + # collect upcasts of tile transform kernels + for i, si in enumerate(wino_schedule): + k = Kernel(si.ast) + k.apply_opts(hand_coded_optimizations(k)) + if k.reduceop is not None: continue # not a tile transform kernel (there is a gemm reduce kernel) + if len(k.bufs) < 22: continue # not a tile transform kernel (there's a permute kernel at the end) + upcasts.append(tuple(k.full_shape[k.shape_len - k.upcasted:k.shape_len])) + assert len(upcasts) == 3 # 3 transformation matrices + assert len(wino_schedule) <= 4 # 4 kernels + # this test case's inputs are too small, so one of the 4-stacks became a local, which is fine i guess + assert upcasts.count((6, 6)) == 2 #and upcasts.count((4, 4)) == 1 + + backward_schedule = Tensor.schedule(x.grad, w.grad) + for si in backward_schedule: + k = Kernel(si.ast) + k.apply_opts(hand_coded_optimizations(k)) + k.linearize() + if len(k.bufs) < 20: continue # not a tile transform kernel + # heuristic number to make sure that at least some upcasts but not too many upcasts are being done + assert 6 <= prod(k.full_shape[k.shape_len - k.upcasted:k.shape_len]) <= 216 + assert len(backward_schedule) <= 13 # just the current number, but it could be better + + def test_masked_upcast_many(self): + layer_1 = Tensor.cat(Tensor.rand(3, 4), Tensor.rand(4, 4)) + layer_2 = Tensor.cat(layer_1.unsqueeze(0), Tensor.rand(6, 7, 4)) + layer_3 = Tensor.cat(layer_2.unsqueeze(0), Tensor.rand(6, 7, 7, 4)) + + k = helper_linearizer_opt(layer_3)[-1] + assert len(k.bufs) == 5 # make sure all ops are done in one kernel + # check that we don't do too many upcasts + assert prod(k.full_shape[k.shape_len-k.upcasted:k.shape_len]) <= 49 + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + def test_matvec(self): + N = 128 + a = Tensor.rand(1, N).realize() + b = Tensor.rand(N, N).realize() + c = a @ b + + k = helper_linearizer_opt(c)[-1] + + assert k.group_for_reduces == 1 + assert k.local_dims == 1 + assert k.upcasted == 1 + +def helper_linearizer_ast(ast:UOp, inputs:list[Tensor], *args, **kwargs): + assert isinstance(ast, UOp), "ast must be UOp" + inbufs = [x.uop.base.buffer for x in inputs] + outbufs = [Buffer(inbufs[-1].device if inbufs else Device.DEFAULT, out.st_arg.size, out.src[1].dtype).allocate() \ + for out in ast.src] + return _helper_linearizer_opt_ast(ast, outbufs+inbufs, *args, **kwargs) + +def helper_linearizer_opt(r:Union[Tensor, list[Tensor]], *args, **kwargs): + realized_ast, real_bufs = helper_realized_ast(r) + return _helper_linearizer_opt_ast(realized_ast, real_bufs, *args, **kwargs) + +def copyout_outputs(lin:Kernel, outbufs:list[Buffer]) -> list[np.ndarray]: + ret = [] + for i,x in enumerate(outbufs): + shape: tuple[int, ...] = lin.ast.src[i].st_arg.shape + ret.append(np.frombuffer(x.as_buffer(), _to_np_dtype(x.dtype)).reshape(shape)) + return ret + +def reset_bufs(bufs:list[Buffer]): + for buf in bufs: buf.copyin(np.zeros((buf.size, ), dtype=_to_np_dtype(buf.dtype)).data) # Zero to check that all values are filled + +def _helper_linearizer_opt_ast(realized_ast:UOp, real_bufs:list[Buffer], opts=[], + apply_tc=False, atol=1e-4, rtol=1e-4, color_sizes=[], wanna_output=[]) -> list[Kernel]: + lins: list[Kernel] = [] + outbufs = [real_bufs[x.src[0].base.arg] for x in realized_ast.src] + device = real_bufs[0].device + + def get_prg(k:Kernel): return CompiledRunner(replace(k.to_program(), device=device)) + + def check_opt(opts, create_k, expected_color_size): + k = create_k() + lins.append(k) + if apply_tc: + assert k.apply_tensor_cores(1, extra_opts=opts), "no tensor core triggered" + else: + k.apply_opts(opts) + if expected_color_size is not None: + cs = list(zip(k.colors(), k.full_shape)) + assert cs == expected_color_size, f"expected={expected_color_size} got={cs}" + prg = get_prg(k) + reset_bufs(outbufs) + prg.exec(real_bufs) + + for x,want in zip(copyout_outputs(k, outbufs), wanna_output): np.testing.assert_allclose(x, want, atol=atol, rtol=rtol) + + # Get baseline if it is not provided, which is not optimized at all. + k = Kernel(realized_ast) + lins.append(k) + prg = get_prg(k) + prg.exec(real_bufs) + if len(wanna_output) == 0: wanna_output = copyout_outputs(k, outbufs) + else: + for buf,want in zip(copyout_outputs(k, outbufs), wanna_output): np.testing.assert_allclose(buf, want, atol=atol, rtol=rtol) + + # Check correctness of handcoded optimiztions. + k = Kernel(realized_ast) + k.apply_opts(hand_coded_optimizations(k)) + lins.append(k) + prg = get_prg(k) + reset_bufs(outbufs) + prg.exec(real_bufs) + for buf,want in zip(copyout_outputs(k, outbufs), wanna_output): np.testing.assert_allclose(buf, want, atol=atol, rtol=rtol) + for i,x in enumerate(opts): # Check custom transformations if any. + check_opt(x, lambda: Kernel(realized_ast), color_sizes[i] if i < len(color_sizes) else None) + return lins + +class TestKernelOpts(unittest.TestCase): + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + def test_local_and_grouped_reduce(self): + N = 128 + Tensor.manual_seed(1882) + a = Tensor.rand(4, 4, N, N) + b = Tensor.rand(4, 4, N) + r = (b.sqrt() + ((a+1).sum(axis=3).exp())) + helper_linearizer_opt(r, [ + [Opt(OptOps.LOCAL, 0, 2)], + [Opt(OptOps.LOCAL, 0, 8)], + [Opt(OptOps.LOCAL, 0, 16)], # Checking how it works with locals + [Opt(OptOps.GROUPTOP, 0, 2)], + [Opt(OptOps.GROUPTOP, 0, 32)], + [Opt(OptOps.GROUPTOP, 0, 64)], # Checking how it works with grouped reduce + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.GROUPTOP, 0, 2)], + [Opt(OptOps.LOCAL, 0, 16), Opt(OptOps.GROUPTOP, 0, 16)], + [Opt(OptOps.LOCAL, 0, 32), Opt(OptOps.GROUPTOP, 0, 2)], + # Checking how it works with locals + grouped reduce + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.GROUPTOP, 0, 64)], + # Checking how it works with locals + grouped reduce + upcasts + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.UPCAST, 0, 8), Opt(OptOps.UNROLL, 1, 4)], + # many local + many group + [Opt(OptOps.GROUP, 0, 2)] * 4, + [Opt(OptOps.LOCAL, 0, 2)] * 4, + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.GROUP, 0, 2)] * 4, + ]) + + def test_upcasts(self): + N = 16 + Tensor.manual_seed(1772) + a = Tensor.rand(N, N) + b = Tensor.rand(N, N) + r = (a+b).sqrt() * ((a+1).exp()) + helper_linearizer_opt(r, [ + [Opt(OptOps.UPCAST, 0, 2)], + [Opt(OptOps.UPCAST, 0, 4)], + [Opt(OptOps.UPCAST, 0, 8)], # Checking how it works with upcasts + ]) + + def test_full_upcast(self): + Tensor.manual_seed(1772) + a = Tensor.rand(4) + b = Tensor.rand(4) + r = (a+b).sqrt() * ((a+1).exp()) + helper_linearizer_opt(r, [ + [Opt(OptOps.UPCAST, 0, 4)], # Checking how it works with upcasts + ]) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + def test_matmul(self): + N = 128 + Tensor.manual_seed(1552) + a = Tensor.rand(N, N) + b = Tensor.rand(N, N) + r = a@b + helper_linearizer_opt(r, [ + [Opt(OptOps.UPCAST, 0, 2)], + [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UPCAST, 1, 4)], # Checking how it works with upcasts + [Opt(OptOps.LOCAL, 0, 2)], + [Opt(OptOps.LOCAL, 1, 32)], + [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 1, 4)], + [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 1, 32)], + [Opt(OptOps.LOCAL, 0, 16), Opt(OptOps.LOCAL, 1, 8)], # Checking how it works with locals + [Opt(OptOps.GROUPTOP, 0, 2)], + [Opt(OptOps.GROUPTOP, 0, 32)], + [Opt(OptOps.GROUPTOP, 0, 32), Opt(OptOps.UNROLL, 0, 4)], # Checking how it works with grouped_reduce + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.LOCAL, 1, 2), Opt(OptOps.GROUPTOP, 0, 32)], + [Opt(OptOps.LOCAL, 0, 8), Opt(OptOps.GROUPTOP, 0, 32)], + [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 0, 8), Opt(OptOps.GROUPTOP, 0, 4)], # Checking how it works with local+grouped_reduce + # Checking all together + [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UPCAST, 0, 4), + Opt(OptOps.UPCAST, 1, 2)], + # Full global upcast + local + [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UPCAST, 0, 8)], + ]) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + def test_double_reduce(self): + N = 128 + Tensor.manual_seed(1552) + a = Tensor.rand(8, N, 8, N) + r = a.sum(axis=(1,3)) + helper_linearizer_opt(r, [ + # openCL / GPU=1 is 256 max threads + [Opt(OptOps.GROUPTOP, 0, 2)], [Opt(OptOps.GROUPTOP, 0, 32)], + [Opt(OptOps.GROUPTOP, 1, 2)], [Opt(OptOps.GROUPTOP, 1, 32)], # Checking how it works with 1 grouped_reduce. + [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 2)], + [Opt(OptOps.GROUPTOP, 0, 16), Opt(OptOps.GROUPTOP, 1, 2)], + [Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 64)], # Checking how it works with 2 grouped_reduces. + [Opt(OptOps.GROUPTOP, 0, 16), Opt(OptOps.GROUPTOP, 1, 2), Opt(OptOps.UNROLL, 0, 4)], + [Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 32), Opt(OptOps.UNROLL, 2, 4)], # Checking how it works with 2 grouped_reduces + upcasts. + [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 1, 4), Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4)], + # Checking how it works with 2 grouped_reduces + upcasts + locals. + [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 1, 4), Opt(OptOps.GROUPTOP, 0, 2), Opt(OptOps.GROUPTOP, 1, 32), Opt(OptOps.UNROLL, 1, 4)], + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.LOCAL, 1, 2), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UPCAST, 0, 2)], + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.LOCAL, 1, 2), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UPCAST, 0, 2), + Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.UNROLL, 1, 4)], # Checking how it works with 2 grouped_reduces + upcasts + locals. + [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.LOCAL, 1, 4), Opt(OptOps.GROUPTOP, 0, 4), Opt(OptOps.GROUPTOP, 1, 4), Opt(OptOps.UPCAST, 0, 2), + Opt(OptOps.UPCAST, 0, 2)], # No globals + ]) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + def test_invalid_tensor_core_extra_opts(self): + N = 128 + Tensor.manual_seed(1552) + a = Tensor.rand(N, N) + b = Tensor.rand(N, N) + realized_ast, _ = helper_realized_ast(a@b) + invalid_opts = [ + [Opt(OptOps.LOCAL, 2, 2)], + [Opt(OptOps.UPCAST, 2, 2)], + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.LOCAL, 2, 2)], + ] + for x in invalid_opts: + k = Kernel(realized_ast) + with self.assertRaises(AssertionError): + assert k.apply_tensor_cores(use_tensor_cores=1, extra_opts=x), "no valid tensor core" # for METAL in runners + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + def test_buf_index_not_found_tensor_core(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(256), arg=ShapeTracker(views=(View(shape=(1, 256), strides=(0, 1), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(256), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(256), arg=ShapeTracker(views=(View(shape=(1243, 256), strides=(0, 1), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(256), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(1243), arg=ShapeTracker(views=(View(shape=(1243, 256), strides=(1, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1243), arg=2, src=()),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1243), arg=ShapeTracker(views=(View(shape=(1243, 256), strides=(1, 0), offset=0, mask=None, contiguous=False),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1243), arg=3, src=()),)),)),)),)),)),)) + k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) + with self.assertRaises(KernelOptError): + k.apply_opt(Opt(OptOps.TC, 0, (-1, 1, 1))) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + @unittest.skipUnless(any(tc.dtype_in == tc.dtype_out == dtypes.half for tc in Device[Device.DEFAULT].renderer.tensor_cores), + "test requires tensor cores with accumulation in half") # testing with half suffices. + def test_tensor_core_opts(self): + N = 128 + Tensor.manual_seed(1552) + a, b = Tensor.rand(N, N, dtype=dtypes.half), Tensor.rand(N, N, dtype=dtypes.half) + r = a.matmul(b, dtype=dtypes.half) + atol, rtol = 0.25, 0.01 + helper_linearizer_opt(r, [ + [], + [Opt(OptOps.UPCAST, 0, 4)], + [Opt(OptOps.UPCAST, 1, 4)], + [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UPCAST, 1, 4)], # check upcasts + [Opt(OptOps.UNROLL, 0, 2)], # check unroll + [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UNROLL, 0, 2)], # check combo of unroll and local + [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.UNROLL, 0, 2)], + [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.UNROLL, 0, 4)], + [Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.UPCAST, 0, 4)], # check permutations + [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UPCAST, 0, 4)], + [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UPCAST, 1, 4)], + [Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UNROLL, 0, 4)], + ], apply_tc=True, atol=atol, rtol=rtol) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + @unittest.skipUnless(any(tc.dtype_in == tc.dtype_out == dtypes.half for tc in Device[Device.DEFAULT].renderer.tensor_cores), + "test requires tensor cores with accumulation in half") # testing with half suffices. + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + def test_tensor_core_opts_locals(self): + N = 128 + Tensor.manual_seed(1552) + a, b = Tensor.rand(N, N, dtype=dtypes.half), Tensor.rand(N, N, dtype=dtypes.half) + r = a.matmul(b, dtype=dtypes.half) + atol, rtol = 0.25, 0.01 + helper_linearizer_opt(r, [ + [Opt(OptOps.UNROLL, 0, 0)], # check full unroll of reduce with locals + [Opt(OptOps.LOCAL, 0, 4)], # check local + [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.LOCAL, 0, 2)], + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.UPCAST, 1, 4), Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UPCAST, 0, 4)], + ], apply_tc=True, atol=atol, rtol=rtol) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared memory") + @unittest.skipUnless(any(tc.dtype_in == tc.dtype_out == dtypes.half for tc in Device[Device.DEFAULT].renderer.tensor_cores), + "test requires tensor cores with accumulation in half") # testing with half suffices. + # NOTE: the METAL test is broken, likely due to a compiler bug. passes on CI with -O0 and with default opt level locally on M3 + @unittest.skipIf(Device.DEFAULT == "METAL", "broken for METAL") + @unittest.skip("feature was removed") + def test_tensor_core_opts_group(self): + N = 128 + Tensor.manual_seed(1552) + a, b = Tensor.rand(N, N, dtype=dtypes.half), Tensor.rand(N, N, dtype=dtypes.half) + r = a.matmul(b, dtype=dtypes.half) + atol, rtol = 0.25, 0.01 + helper_linearizer_opt(r, [ + [Opt(OptOps.GROUP, 0, 2)], + [Opt(OptOps.GROUPTOP, 0, 4)], + [Opt(OptOps.UPCAST, 0, 4), Opt(OptOps.GROUP, 0, 2)], + [Opt(OptOps.LOCAL, 0, 4), Opt(OptOps.GROUP, 0, 2)], + [Opt(OptOps.UNROLL, 0, 4), Opt(OptOps.GROUP, 0, 2)], + [Opt(OptOps.UPCAST, 0, 2), Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.GROUP, 0, 2)], + [Opt(OptOps.LOCAL, 0, 2), Opt(OptOps.GROUPTOP, 0, 8), Opt(OptOps.UNROLL, 0, 2), Opt(OptOps.UPCAST, 1, 2)], + ], apply_tc=True, atol=atol, rtol=rtol) + + def test_padto_matmul(self): + if (CI and Device.DEFAULT in ["AMD", "NV", "CUDA"]): + self.skipTest("super slow on CUDA and AMD because of the big grid dims") + N = 17 * 17 + Tensor.manual_seed(289) + a = Tensor.rand(N, N) + b = Tensor.rand(N, N) + helper_linearizer_opt(a@b, [ + [Opt(OptOps.PADTO, 0, 32)], + [Opt(OptOps.PADTO, 1, 32)], + [Opt(OptOps.PADTO, 2, 32)], + [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.PADTO, 1, 32)], + [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.PADTO, 1, 32), Opt(OptOps.PADTO, 2, 32)], + # can optimize further post PADTO + [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.PADTO, 1, 32), Opt(OptOps.UPCAST, 0, 2), Opt(OptOps.UPCAST, 1, 2),], + ]) + + def test_padto_upcasted_not_ok(self): + N = 4 + a = Tensor.rand(N, N) + b = Tensor.rand(N, N) + helper_linearizer_opt(a@b, [ + [Opt(OptOps.UPCAST, 0, 0)], + [Opt(OptOps.UPCAST, 1, 0)], + [Opt(OptOps.UNROLL, 0, 0)], + [Opt(OptOps.PADTO, 0, 8)], + [Opt(OptOps.PADTO, 1, 8)], + [Opt(OptOps.PADTO, 2, 8)], + ]) + with self.assertRaises(KernelOptError): + helper_linearizer_opt(a@b, [[Opt(OptOps.UPCAST, 0, 0), Opt(OptOps.PADTO, 2, 8)]]) + with self.assertRaises(KernelOptError): + helper_linearizer_opt(a@b, [[Opt(OptOps.UPCAST, 1, 0), Opt(OptOps.PADTO, 2, 8)]]) + with self.assertRaises(KernelOptError): + helper_linearizer_opt(a@b, [[Opt(OptOps.UNROLL, 0, 0), Opt(OptOps.PADTO, 2, 8)]]) + + def test_padto_sum_ok(self): + N = 18 * 18 + # NOTE: this setup prevents 17 * 17 contiguous merged into one dimension + a = Tensor.rand(N, N).realize().shrink(((0, 17), (0, 17))) * 100 + b = (Tensor.rand(N, N) < 0.5).realize().shrink(((0, 17), (0, 17))) + + helper_linearizer_opt(a.sum(0), [ + [Opt(OptOps.PADTO, 0, 32)], + [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], + ]) + helper_linearizer_opt(a.sum(1), [ + [Opt(OptOps.PADTO, 0, 32)], + [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], + ]) + + # can pad sum reduce axis if there's no unsafe ops prior to sum + for axis in (0, 1): + helper_linearizer_opt(a.sum(), [[Opt(OptOps.PADTO, axis, 32)],]) + helper_linearizer_opt(a.sum(0), [[Opt(OptOps.PADTO, axis, 32)],]) + helper_linearizer_opt(b.sum(), [[Opt(OptOps.PADTO, axis, 32)],]) + helper_linearizer_opt(b.sum(0), [[Opt(OptOps.PADTO, axis, 32)],]) + helper_linearizer_opt(b.sum(dtype=dtypes.bool), [[Opt(OptOps.PADTO, axis, 32)],]) + # TODO: why? + if Device.DEFAULT != "WEBGPU": + helper_linearizer_opt(b.sum(0, dtype=dtypes.bool), [[Opt(OptOps.PADTO, axis, 32)],]) + helper_linearizer_opt(b.sum(1, dtype=dtypes.bool), [[Opt(OptOps.PADTO, axis, 32)],]) + + # having unsafe ops after sum is fine + helper_linearizer_opt(a.sum().exp(), [[Opt(OptOps.PADTO, 0, 32)],]) + helper_linearizer_opt(a.sum(0).exp(), [[Opt(OptOps.PADTO, 1, 32)],]) + + def test_padto_sum_not_ok(self): + N = 18 * 18 + # NOTE: this setup prevents 17 * 17 contiguous merged into one dimension + a = Tensor.rand(N, N).shrink(((0, 17), (0, 17))).exp() + # exp is not safe to pad + with self.assertRaises(KernelOptError): + helper_linearizer_opt(a.exp().sum(), [[Opt(OptOps.PADTO, 0, 32)],]) + with self.assertRaises(KernelOptError): + helper_linearizer_opt(a.exp().sum(0), [[Opt(OptOps.PADTO, 1, 32)],]) + + b = a < 1 + # lt is not safe to pad + with self.assertRaises(KernelOptError): + helper_linearizer_opt(b.sum(), [[Opt(OptOps.PADTO, 0, 32)],]) + with self.assertRaises(KernelOptError): + helper_linearizer_opt(b.sum(0), [[Opt(OptOps.PADTO, 1, 32)],]) + + def test_padto_max(self): + N = 18 * 18 + # NOTE: this setup prevents 17 * 17 contiguous merged into one axis + a = -Tensor.rand(N, N).shrink(((0, 17), (0, 17))) * 100 + + helper_linearizer_opt(a.max(0), [ + [Opt(OptOps.PADTO, 0, 32)], + [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], + ]) + helper_linearizer_opt(a.max(1), [ + [Opt(OptOps.PADTO, 0, 32)], + [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], + ]) + + # cannot pad max kernel on reduce + with self.assertRaises(KernelOptError): + helper_linearizer_opt(a.max(), [[Opt(OptOps.PADTO, 0, 32)],]) + with self.assertRaises(KernelOptError): + helper_linearizer_opt(a.max(0), [[Opt(OptOps.PADTO, 1, 32)],]) + + def test_padto_where(self): + Tensor.manual_seed(0) + N = 17 * 17 + a = (Tensor.randn(N, N).realize().max(axis=0, keepdim=True) > 1).where(1, 0) + helper_linearizer_opt(a.max(0), [ + [Opt(OptOps.PADTO, 0, 32)], + [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], + ]) + + def test_padto_where_multioutput(self): + Tensor.manual_seed(0) + N = 17 * 17 + r = Tensor.randn(N, N).realize().max(axis=0, keepdim=True) > 1 + a0 = r.where(1, 0) + a1 = r.where(2, 0) + helper_linearizer_opt([a0.max(0), a1.max(0)], [ + [Opt(OptOps.PADTO, 0, 32)], + [Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8),], + ]) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + def test_padto_group(self): + Tensor.manual_seed(0) + g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] + ld0 = UOp(Ops.LOAD, dtypes.float, src=(g1.view(ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 18, 0, 3, 0, 1), offset=0, mask=None, contiguous=False),))),)) # noqa: E501 + ld1 = UOp(Ops.LOAD, dtypes.float, src=(g2.view(ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),))),)) # noqa: E501 + store = UOp(Ops.STORE, src=(g0.view(ShapeTracker(views=(View(shape=(1, 1, 1, 1, 1, 4, 1, 6, 1, 3), strides=(0, 0, 0, 0, 0, 18, 0, 3, 0, 1), offset=0, mask=None, contiguous=True),))), UOp(Ops.REDUCE_AXIS, dtypes.float, (ld0*ld1,), (Ops.ADD, (0, 2, 4, 6)),))) # noqa: E501 + sink = UOp(Ops.SINK, src=(store,)) + data1 = Tensor.randn(2, 1, 4, 1, 3, 4, 2, 6, 1, 3).realize() + data2 = Tensor.randn(2, 1, 4, 1, 3, 4, 2, 6, 1, 3).realize() + helper_linearizer_ast(sink, [data1, data2], opts=[ + #[Opt(OptOps.PADTO, 0, 32), Opt(OptOps.GROUP, 0, 4)], + #[Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8)], + #[Opt(OptOps.PADTO, 0, 32), Opt(OptOps.UPCAST, 0, 8), Opt(OptOps.GROUP, 0, 4)] + ]) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test requires locals") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared") + def test_color_shapes_with_local(self): + N = 32 + Tensor.manual_seed(1552) + a = Tensor.rand(N, N) + b = Tensor.rand(N, N) + r = a@b + opts_shapes = [ + ([Opt(OptOps.LOCAL, 0, 2)], [("blue",16),("blue",32),("cyan",2),("red",32)]), + ([Opt(OptOps.LOCAL, 0, 2),Opt(OptOps.GROUP, 0, 2)], [("blue",16),("blue",32),("cyan",2),("green",2),("red",16)]), + # check to ensure local_dims are stable for full UNROLL of first_reduce + ([Opt(OptOps.LOCAL, 0, 2),Opt(OptOps.UNROLL, 0, 0)], [("blue",16),("blue",32),("cyan",2),("magenta",32)]), + ([Opt(OptOps.UNROLL, 0, 0),Opt(OptOps.LOCAL, 0, 2)], [("blue",16),("blue",32),("cyan",2),("magenta",32)]), + # check behavior for full UNROLL on an existing GROUP + ([Opt(OptOps.LOCAL, 0, 2),Opt(OptOps.GROUP, 0, 0),Opt(OptOps.UNROLL, 0, 2)], [("blue",16),("blue",32),("cyan",2),("green",16),("magenta",2)]), + ([Opt(OptOps.LOCAL, 0, 2),Opt(OptOps.GROUP, 0, 0),Opt(OptOps.UNROLL, 0, 0)], [("blue",16),("blue",32),("cyan",2),("magenta",32)]), + ([Opt(OptOps.GROUP, 0, 0),Opt(OptOps.LOCAL, 0, 2),Opt(OptOps.UNROLL, 0, 0)], [("blue",16),("blue",32),("cyan",2),("magenta",32)]), + ([Opt(OptOps.GROUP, 0, 2),Opt(OptOps.UNROLL, 0, 0)], [("blue",32),("blue",32),("red",16),("magenta",2)]), + ] + helper_linearizer_opt(r, [x[0] for x in opts_shapes], color_sizes=[x[1] for x in opts_shapes]) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_linearizer_dumb.py b/tinygrad_repo/test/test_linearizer_dumb.py new file mode 100644 index 000000000..669d0a5d0 --- /dev/null +++ b/tinygrad_repo/test/test_linearizer_dumb.py @@ -0,0 +1,199 @@ +# ruff: noqa: E501 +# tests where the Linearizer is doing something dumb +# like test_linearizer_failures, but they don't have to fail + +import unittest +from tinygrad import Device, dtypes +from tinygrad.device import is_dtype_supported +from tinygrad.uop.ops import UOp, Ops +from tinygrad.helpers import getenv +from tinygrad.shape.shapetracker import ShapeTracker, View +from tinygrad.opt.search import Opt, OptOps +from tinygrad.opt.kernel import Kernel + +class TestLinearizerDumb(unittest.TestCase): + @unittest.skipUnless(Device.DEFAULT == "METAL", "only tested on METAL") + def test_unmerged_ifs(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(1605632), arg=ShapeTracker(views=(View(shape=(64, 1, 512, 7, 7, 1, 1, 1), strides=(25088, 0, 49, 7, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1605632), arg=0, src=()),)), + UOp(Ops.MAX, dtypes.half, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(1605632), arg=ShapeTracker(views=(View(shape=(1, 64, 1, 512, 4, 9, 4, 9), strides=(0, 25088, 0, 49, 0, 7, 0, 1), offset=-8, mask=((0, 1), (0, 64), (0, 1), (0, 512), (0, 4), (1, 8), (0, 4), (1, 8)), contiguous=False), View(shape=(64, 1, 512, 7, 7, 512, 3, 3), strides=(663552, 0, 0, 36, 1, 1296, 360, 10), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1605632), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(2359296), arg=ShapeTracker(views=(View(shape=(64, 1, 512, 7, 7, 512, 3, 3), strides=(0, 0, 4608, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(2359296), arg=2, src=()),)),)),)),)),)),)), + UOp(Ops.CONST, dtypes.half, arg=0.9999950000374996, src=( + x16:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(64, 1, 512, 7, 7, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.CONST, dtypes.half, arg=0.0, src=( + x16,)),)),)),)) + opts = [Opt(op=OptOps.TC, axis=2, arg=(-1, 2, 1)), Opt(op=OptOps.UPCAST, axis=2, arg=0), Opt(op=OptOps.UNROLL, axis=1, arg=0)] + k = Kernel(ast, opts=Device["METAL"].renderer) + k.apply_opts(opts) + prg = k.to_program() + print(prg.src) + Device[Device.DEFAULT].compiler.compile_cached(prg.src) + gate_count = len([x for x in prg.src.splitlines() if "if" in x]) + assert gate_count == 1, f"must have only one gate {gate_count} != 1" + assert len([u for u in k.uops if u.op is Ops.IF]) == 1, "must have a single IF" + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "need local") + def test_max_simplify_and_cancel(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(1000), arg=ShapeTracker(views=(View(shape=(1000, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1000), arg=0, src=()),)), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CAST, dtypes.int, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1000), arg=ShapeTracker(views=(View(shape=(1000, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1000), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(1000, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=2, src=()),)),)),)), + UOp(Ops.CONST, dtypes.bool, arg=True, src=( + x14:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1000, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1001, 1999), strides=(0, 0), offset=0, mask=((0, 1001), (999, 1999)), contiguous=False), View(shape=(1000, 1000), strides=(1, 2000), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=-1, src=( + x21:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1000, 1000), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=0, src=( + x21,)),)),)), + UOp(Ops.CONST, dtypes.int, arg=1000, src=( + x14,)),)),)),)),)) + opts = [Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=8)] + k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) + k.apply_opts(opts) + prg = k.to_program() + print(prg.src) + assert prg.uops is not None and not any(uop.op is Ops.MAX for uop in prg.uops), "leftover MAX" + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "need local") + def test_expander_new_srcs(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(25, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(26, 49), strides=(0, -1), offset=48, mask=((0, 26), (24, 49)), contiguous=False), View(shape=(25, 25), strides=(1, 50), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=1, src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.GROUP, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0)] + k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) + k.apply_opts(opts) + prg = k.to_program() + print(prg.src) + if_uops = [u for u in k.uops if u.op is Ops.IF] + self.assertIn(len(if_uops), {1,2,3}) + conditions = if_uops[0].src[0].toposort() + self.assertLessEqual(len(conditions), 9) + + # this was a bug in embedding, someday we should fold this anyway + @unittest.skipUnless(is_dtype_supported(dtypes.half), f"half dtype not supported on {Device.DEFAULT}") + def test_llama_embedding(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(4096), arg=ShapeTracker(views=(View(shape=(4096, 1, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(4096), arg=0, src=()),)), + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (2,)), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(32001, 63999), strides=(0, 0), offset=0, mask=((0, 32001), (31999, 63999)), contiguous=False), View(shape=(4096, 32000, 32000), strides=(0, 1, 64000), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=1, src=( + x16:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4096, 32000, 32000), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=0, src=( + x16,)),)),)), + UOp(Ops.CONST, dtypes.int, arg=-1, src=( + x19:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4096, 32000, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(1), arg=ShapeTracker(views=(View(shape=(4096, 32000, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1), arg=1, src=()),)),)),)), + UOp(Ops.CONST, dtypes.bool, arg=True, src=( + x19,)),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(131072000), arg=ShapeTracker(views=(View(shape=(4096, 32000, 1), strides=(1, 4096, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(131072000), arg=2, src=()),)),)),)),)),)),)),)),)) + k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) + prg = k.to_program() + print(prg.src) + + @unittest.expectedFailure + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "need float4") + def test_unrolled_float4_align(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(1, 1), strides=(0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 1)), src=( + UOp(Ops.WHERE, dtypes.float, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.LOAD, dtypes.long, arg=None, src=( + UOp(Ops.VIEW, dtypes.long.ptr(18), arg=ShapeTracker(views=(View(shape=(3, 6), strides=(6, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.long.ptr(18), arg=1, src=()),)),)), + UOp(Ops.CONST, dtypes.long, arg=-1, src=( + x11:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(3, 6), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.CONST, dtypes.bool, arg=True, src=( + x11,)),)), + UOp(Ops.CONST, dtypes.float, arg=0.0, src=( + x11,)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(18), arg=ShapeTracker(views=(View(shape=(3, 6), strides=(6, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(18), arg=2, src=()),)),)),)),)),)),)) + opts = [Opt(op=OptOps.UNROLL, axis=0, arg=0)] + k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) + k.apply_opts(opts) + prg = k.to_program() + print(prg.src) + load_idxs = [x.src[1] for x in k.uops if x.op is Ops.LOAD and x.src[0].arg == 2] + assert load_idxs[0] < load_idxs[1], f"first loaded idx {load_idxs[0].arg} then {load_idxs[1].arg}!" + + @unittest.expectedFailure + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "need float4") + @unittest.skipIf(getenv("PTX"), "this is somehow correct in PTX") + def test_upcasted_stores_out_of_order(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(9360), arg=ShapeTracker(views=(View(shape=(4, 5, 13, 1, 1, 1, 1, 1, 4, 3, 3), strides=(2340, 468, 36, 0, 0, 0, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9360), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (6,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(144), arg=ShapeTracker(views=(View(shape=(4, 5, 13, 1, 1, 1, 4, 1, 4, 3, 3), strides=(0, 0, 0, 0, 0, 0, 1, 0, 4, 48, 16), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(144), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1040), arg=ShapeTracker(views=(View(shape=(4, 5, 13, 1, 1, 1, 4, 1, 4, 3, 3), strides=(260, 13, 1, 0, 0, 0, 65, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1040), arg=2, src=()),)),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.UPCAST, axis=2, arg=0)] + k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) + k.apply_opts(opts) + prg = k.to_program() + print(prg.src) + store_idxs = [x.src[1] for x in k.uops if x.op is Ops.STORE] + for i in range(len(store_idxs) - 1): + first_bounds = store_idxs[i].vmin+store_idxs[i].vmax + next_bounds = store_idxs[i+1].vmin+store_idxs[i+1].vmax + assert first_bounds < next_bounds, f"first stored (max) idx {first_bounds} then {next_bounds}!" + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_linearizer_failures.py b/tinygrad_repo/test/test_linearizer_failures.py new file mode 100644 index 000000000..a5e5a1a0e --- /dev/null +++ b/tinygrad_repo/test/test_linearizer_failures.py @@ -0,0 +1,1706 @@ +# ruff: noqa: E501 +import unittest, random +import numpy as np +from tinygrad.opt.kernel import Kernel, KernelOptError +from tinygrad.device import is_dtype_supported +from tinygrad.uop.ops import UOp, Ops +from tinygrad.opt.search import Opt, OptOps +from tinygrad import Device, dtypes, Tensor +from tinygrad.helpers import CI +from test.external.fuzz_linearizer import compare_linearizer + +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.shape.view import View + +def helper_test_lin(lin: Kernel, opts, failed_platforms, rtol=1e-2, atol=1e-2): + if any(b.dtype.base == dtypes.half for b in lin.membufs) and not is_dtype_supported(dtypes.half): return + if any(b.dtype.base == dtypes.bfloat16 for b in lin.membufs) and not is_dtype_supported(dtypes.bfloat16): return + + try: + lin.apply_opts(opts) + except KernelOptError: + # it's considered fixed if we invalidated the opts + assert Device.DEFAULT not in failed_platforms, f"unexpected success on {Device.DEFAULT}" + return + + compare_result = compare_linearizer(lin, rtol=rtol, atol=atol) + if compare_result[0] in ["PASS", "KernelOptError"]: + # it's considered fixed if we invalidated the opts + assert Device.DEFAULT not in failed_platforms, f"unexpected success on {Device.DEFAULT}" + else: + assert Device.DEFAULT in failed_platforms, f"failed on {Device.DEFAULT} with {compare_result[0]}" + return lin + +@unittest.skipIf(CI and Device.DEFAULT in {"CUDA", "NV"}, "failed on CUDA CI") +class TestLinearizerFailures(unittest.TestCase): + def setUp(self): + random.seed(42) + np.random.seed(42) + Tensor.manual_seed(42) + + def test_failure_1(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(512), arg=ShapeTracker(views=(View(shape=(32, 16, 1), strides=(16, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(512), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(512), arg=ShapeTracker(views=(View(shape=(32, 16, 16), strides=(16, 1, 0), offset=0, mask=None, contiguous=False),)), src=( + x8:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(512), arg=1, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(32, 16, 1), strides=(0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=2, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(512), arg=ShapeTracker(views=(View(shape=(32, 16, 1), strides=(16, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + x8,)),)),)),)),)) + helper_test_lin(Kernel(ast), [], failed_platforms=[]) + + def test_failure_2(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(21312), arg=ShapeTracker(views=(View(shape=(32, 2, 37, 9, 1, 1), strides=(666, 333, 9, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(21312), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.MAX, (4, 5)), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(197119), arg=ShapeTracker(views=(View(shape=(32, 2, 111, 27), strides=(6160, 3080, 28, 1), offset=0, mask=((0, 32), (0, 2), (0, 110), (0, 27)), contiguous=False), View(shape=(32, 2, 37, 9, 2, 2), strides=(5994, 2997, 81, 3, 27, 1), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(197119), arg=1, src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.LOCAL, axis=0, arg=32)] + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_3(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(4096), arg=ShapeTracker(views=(View(shape=(32, 8, 16, 1), strides=(128, 16, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4096), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(65536), arg=ShapeTracker(views=(View(shape=(32, 8, 16, 16), strides=(2048, 256, 16, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(65536), arg=1, src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.GROUP, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=2), Opt(op=OptOps.UNROLL, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.LOCAL, axis=0, arg=32)] + # METAL: AssertionError: Error Domain=AGXMetalG13X Code=3 "Threadgroup memory size (65536) exceeds the maximum threadgroup memory allowed (32768)" UserInfo={NSLocalizedDescription=Threadgroup memory size (65536) exceeds the maximum threadgroup memory allowed (32768)} + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_5(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(1, 1, 1, 1, 1, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 4, 6)), src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + x5:=UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.CONST, dtypes.float, arg=0.1464405059814453, src=( + x8:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 1, 4, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.float, arg=1.0, src=( + x8,)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 1, 4, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=1, src=()),)),)),)), + x5,)),)),)),)) + opts = [Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=0)] + # EXEC_ERROR, it has no global_size + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_6(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(10), arg=ShapeTracker(views=(View(shape=(10, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(10), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(11, 19), strides=(0, 0), offset=0, mask=((0, 11), (9, 19)), contiguous=False), View(shape=(10, 10), strides=(1, 20), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=-1, src=( + x9:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(10, 10), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=0, src=( + x9,)),)),)), + UOp(Ops.CONST, dtypes.int, arg=10, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(10, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=2), Opt(op=OptOps.UPCAST, axis=0, arg=0)] + # COMPILE FAILED, KeyError: Ops.CONST + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_7(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(18939904), arg=ShapeTracker(views=(View(shape=(512, 32, 1, 34, 1, 34), strides=(36992, 1156, 0, 34, 0, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(18939904), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2, 4)), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(37748736), arg=ShapeTracker(views=(View(shape=(512, 32, 6, 8, 4, 6, 8, 4), strides=(2048, 64, 6291456, 8, 0, 1048576, 1, 0), offset=0, mask=((0, 512), (0, 32), (0, 6), (0, 8), (0, 1), (0, 6), (0, 8), (0, 1)), contiguous=False), View(shape=(512, 32, 6, 35, 6, 35), strides=(1179648, 36864, 6144, 192, 32, 1), offset=0, mask=((0, 512), (0, 32), (0, 6), (0, 32), (0, 6), (0, 32)), contiguous=False), View(shape=(512, 32, 238, 238), strides=(1411200, 44100, 210, 1), offset=0, mask=((0, 512), (0, 32), (0, 210), (0, 210)), contiguous=False), View(shape=(512, 32, 7, 34, 7, 34), strides=(1812608, 56644, 8092, 238, 34, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(37748736), arg=1, src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=4)] + # test/test_linearizer_failures.py Fatal Python error: Segmentation fault + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_8(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(1, 1, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=0, src=()),)), + UOp(Ops.SQRT, dtypes.float, arg=None, src=( + UOp(Ops.RECIP, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + x9:=UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(4096), arg=ShapeTracker(views=(View(shape=(1, 1, 4096), strides=(0, 0, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4096), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(4096), arg=ShapeTracker(views=(View(shape=(1, 1, 4096), strides=(0, 0, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4096), arg=2, src=()),)),)),)), + x9,)),)), + UOp(Ops.CONST, dtypes.float, arg=0.000244140625, src=( + x17:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 1, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()),)),)), + UOp(Ops.CONST, dtypes.float, arg=1e-06, src=( + x17,)),)),)),)),)),)) + opts = [Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4)] + # fatal error: bracket nesting level exceeded maximum of 256 + # note: use -fbracket-depth=N to increase maximum nesting level + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_9(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(13500), arg=ShapeTracker(views=(View(shape=(1, 1, 1, 3, 1, 1, 1, 1, 5, 15, 5, 3, 4), strides=(0, 0, 0, 4500, 0, 0, 0, 0, 900, 60, 12, 4, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(13500), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(6), arg=ShapeTracker(views=(View(shape=(1, 2, 1, 3, 1, 1, 1, 1, 5, 15, 5, 3, 4), strides=(0, 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(9000), arg=ShapeTracker(views=(View(shape=(1, 2, 1, 3, 1, 1, 1, 1, 5, 15, 5, 3, 4), strides=(0, 4500, 0, 0, 0, 0, 0, 0, 900, 60, 12, 4, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9000), arg=2, src=()),)),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=0, arg=32)] + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_10(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(1024), arg=ShapeTracker(views=(View(shape=(1, 1, 1024, 1), strides=(0, 0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1024), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.half, arg=(Ops.ADD, (3,)), src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(50257), arg=ShapeTracker(views=(View(shape=(1, 1, 1024, 50257), strides=(0, 0, 0, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(50257), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(51463168), arg=ShapeTracker(views=(View(shape=(1, 1, 1024, 50257), strides=(0, 0, 1, 1024), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(51463168), arg=2, src=()),)),)),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(1024), arg=ShapeTracker(views=(View(shape=(1, 1, 1024, 1), strides=(0, 0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1024), arg=3, src=()),)),)),)),)),)) + helper_test_lin(Kernel(ast), [], failed_platforms=[]) + + def test_failure_11(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(64), arg=ShapeTracker(views=(View(shape=(1, 64, 1, 1), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=0, src=()),)), + UOp(Ops.RECIP, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 3)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MAX, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1179648), arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True),)), src=( + x12:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1179648), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(64), arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + x15:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=2, src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=0.0, src=( + x17:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(64), arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + x20:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=3, src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=1.0, src=( + x17,)),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.CONST, dtypes.float, arg=1.0, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(512, 64, 3, 3, 2, 2), strides=(0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=()),)), + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MAX, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1179648), arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True), View(shape=(512, 64, 3, 3, 2, 2), strides=(2304, 36, 12, 2, 6, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( + x12,)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(64), arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 3, 2, 2), strides=(2304, 36, 12, 2, 6, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( + x15,)),)),)), + x39:=UOp(Ops.CONST, dtypes.float, arg=0.0, src=( + x40:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 3, 2, 2), strides=(2304, 36, 12, 2, 6, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(64), arg=ShapeTracker(views=(View(shape=(512, 64, 6, 6), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 3, 2, 2), strides=(2304, 36, 12, 2, 6, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( + x20,)),)),)), + UOp(Ops.CONST, dtypes.float, arg=1.0, src=( + x40,)),)), + UOp(Ops.SQRT, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.RECIP, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(64), arg=ShapeTracker(views=(View(shape=(64,), strides=(1,), offset=0, mask=None, contiguous=True), View(shape=(512, 64, 6, 6), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 3, 2, 2), strides=(2304, 36, 12, 2, 6, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=4, src=()),)),)), + UOp(Ops.CONST, dtypes.float, arg=5.425347222222222e-05, src=( + x53:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(64,), strides=(0,), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 3, 2, 2), strides=(2304, 36, 12, 2, 6, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=()),)),)), + UOp(Ops.CONST, dtypes.float, arg=1e-05, src=( + x53,)),)),)),)),)),)), + x39,)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(294912), arg=ShapeTracker(views=(View(shape=(512, 64, 3, 3, 2, 2), strides=(576, 9, 3, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(294912), arg=5, src=()),)),)),)),)),)), + UOp(Ops.RECIP, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(294912), arg=ShapeTracker(views=(View(shape=(512, 64, 3, 3, 2, 2), strides=(576, 9, 3, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(294912), arg=6, src=()),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(294912), arg=ShapeTracker(views=(View(shape=(512, 64, 3, 3, 2, 2), strides=(576, 9, 3, 1, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 3, 2, 3, 2), strides=(2304, 36, 12, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(512, 64, 6, 6), strides=(2304, 36, 6, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(294912), arg=7, src=()),)),)),)),)),)),)),)),)) + helper_test_lin(Kernel(ast), [], failed_platforms=[]) + + def test_failure_12(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(72), arg=ShapeTracker(views=(View(shape=(1, 1, 1, 1, 1, 4, 1, 6, 1, 3), strides=(0, 0, 0, 0, 0, 18, 0, 3, 0, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(72), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 4, 6)), src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + x5:=UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(72), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 18, 0, 3, 0, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(72), arg=1, src=()),)),)), + UOp(Ops.CONST, dtypes.float, arg=1.0, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=2, src=()),)),)),)), + x5,)),)),)),)) + opts = [Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.GROUP, axis=0, arg=4)] + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + # both kernels are correct from a code standpoint, but generate different results due to precision errors (switching to float results in output matches) + def test_failure_13(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(768), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1), strides=(384, 0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(768), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.half, arg=(Ops.ADD, (3,)), src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(103728), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 51864), strides=(51864, 0, 0, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(103728), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(19915776), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 51864), strides=(0, 0, 1, 384), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(19915776), arg=2, src=()),)),)),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(19968), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1), strides=(0, 0, 1, 0), offset=19584, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(19968), arg=3, src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.GROUP, axis=0, arg=4)] + helper_test_lin(Kernel(ast), opts, failed_platforms=["METAL", "GPU", "CUDA"]) + + def test_failure_14(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(72), arg=ShapeTracker(views=(View(shape=(1, 1, 1, 1, 1, 4, 1, 6, 1, 3), strides=(0, 0, 0, 0, 0, 18, 0, 3, 0, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(72), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 4, 6)), src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + x5:=UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(72), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 18, 0, 3, 0, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(72), arg=1, src=()),)),)), + UOp(Ops.CONST, dtypes.float, arg=1.0, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 3, 4, 2, 6, 1, 3), strides=(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=2, src=()),)),)),)), + x5,)),)),)),)) + opts = [Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4)] + # COMPILE_ERROR on METAL in fuzz_linearizer: unused variables and undeclared variables + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_15(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(21952), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 1, 1, 1), strides=(0, 0, 196, 14, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(21952), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(94080), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 480, 1, 1), strides=(0, 0, 0, 14, 1, 196, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(94080), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(53760), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 480, 1, 1), strides=(0, 0, 480, 0, 0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(53760), arg=2, src=()),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(112), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(112), arg=3, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(112), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(112), arg=4, src=()),)),)),)), + UOp(Ops.SQRT, dtypes.float, arg=None, src=( + UOp(Ops.RECIP, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(112), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(112), arg=5, src=()),)),)), + UOp(Ops.CONST, dtypes.float, arg=1e-05, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(112), arg=ShapeTracker(views=(View(shape=(1, 1, 112, 14, 14, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(112), arg=6, src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=2), Opt(op=OptOps.PADTO, axis=1, arg=32), Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.LOCAL, axis=1, arg=16)] + # COMPILE_ERROR on METAL in fuzz_linearizer ast 115: Error Domain=AGXMetalG14X Code=3 "Compiler encountered an internal error" + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_16(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(13), arg=ShapeTracker(views=(View(shape=(1, 13, 1), strides=(0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(13), arg=0, src=()),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(13312), arg=ShapeTracker(views=(View(shape=(1, 13, 1024), strides=(0, 1024, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(13312), arg=1, src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=0.0009765625, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 13, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) + opts = [Opt(op=OptOps.GROUP, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=0), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.GROUP, axis=0, arg=8), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=1, arg=4)] + # COMPILE_ERROR on METAL/GPU (probably HIP/CUDA too) in fuzz_linearizer ast 154: bracket nesting level exceeded maximum of 256 + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_17(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(62720), arg=ShapeTracker(views=(View(shape=(2, 1, 40, 1, 28, 28, 1, 1), strides=(31360, 0, 784, 0, 28, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(62720), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(9600), arg=ShapeTracker(views=(View(shape=(2, 1, 40, 240, 28, 28, 1, 1), strides=(0, 0, 1, 40, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9600), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(376320), arg=ShapeTracker(views=(View(shape=(2, 1, 40, 240, 28, 28, 1, 1), strides=(188160, 0, 0, 784, 28, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(376320), arg=2, src=()),)),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=1, arg=32), Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.GROUPTOP, axis=0, arg=16), Opt(op=OptOps.PADTO, axis=1, arg=32), Opt(op=OptOps.LOCAL, axis=1, arg=4)] + # COMPILE_ERROR on METAL in fuzz_linearizer ast 178: Error Domain=AGXMetalG14X Code=3 "Compiler encountered an internal error" + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_18(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(768), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1), strides=(384, 0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(768), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(768), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1), strides=(384, 0, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(768), arg=1, src=()),)),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(3072), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1536), strides=(1536, 0, 0, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(3072), arg=2, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(589824), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1536), strides=(0, 0, 1536, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(589824), arg=3, src=()),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(384), arg=ShapeTracker(views=(View(shape=(2, 1, 384, 1), strides=(0, 0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(384), arg=4, src=()),)),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.GROUPTOP, axis=0, arg=256), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=3)] + # COMPILE_ERROR on METAL in fuzz_linearizer ast 239: Error Domain=AGXMetalG14X Code=3 "Compiler encountered an internal error" + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_19(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(4536), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 1, 9, 7, 3, 3), strides=(2268, 0, 567, 0, 63, 9, 3, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4536), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(144), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 4, 9, 7, 3, 3), strides=(0, 0, 36, 9, 0, 0, -3, -1), offset=8, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(144), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(504), arg=ShapeTracker(views=(View(shape=(2, 1, 4, 4, 9, 7, 3, 3), strides=(252, 0, 0, 63, 7, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(504), arg=2, src=()),)),)),)),)),)),)) + opts = [Opt(op=OptOps.LOCAL, axis=2, arg=3), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=7), Opt(op=OptOps.UPCAST, axis=2, arg=3), Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.LOCAL, axis=0, arg=3)] + # COMPILE_ERROR on METAL in fuzz_linearizer ast 379: Error Domain=AGXMetalG14X Code=3 "Compiler encountered an internal error" + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_20(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(4, 4), strides=(4, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=0, src=()),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(4), arg=ShapeTracker(views=(View(shape=(4, 4), strides=(0, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4), arg=1, src=()),)),)), + UOp(Ops.CONST, dtypes.float, arg=1.0, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 4), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=0, arg=0)] + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_21(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(2925), arg=ShapeTracker(views=(View(shape=(45, 65), strides=(65, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(2925), arg=0, src=()),)), + UOp(Ops.CONST, dtypes.float, arg=1.0, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(45, 65), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)) + opts = [Opt(op=OptOps.PADTO, axis=0, arg=32)] + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + #@unittest.skipIf(Device.DEFAULT in ("LLVM", "METAL", "CPU"), "flaky") + @unittest.skip("flaky everywhere") + def test_failure_22(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(1, 96, 1, 1), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=0, src=()),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + x4:=UOp(Ops.CONST, dtypes.float, arg=0.000244140625, src=( + x5:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 96, 1, 1), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 3)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(393216), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(393216), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=2, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=3, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=4, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=5, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=6, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(32, 96, 8, 16), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=7, src=()),)),)),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=8, src=()),)),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=9, src=()),)),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=10, src=()),)),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=11, src=()),)),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=12, src=()),)),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=13, src=()),)),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=14, src=()),)),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(276461), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 8640, 180, 18, 1), offset=19, mask=((1, 2), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(276461), arg=15, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(544301), arg=ShapeTracker(views=(View(shape=(2, 32, 48, 8, 16), strides=(0, 17280, 180, 18, 1), offset=19, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(2, 32, 48, 8, 16), strides=(0, 12288, 128, 16, 1), offset=0, mask=((0, 1), (0, 32), (0, 48), (0, 8), (0, 16)), contiguous=False), View(shape=(1536, 2, 128), strides=(128, 196608, 1), offset=0, mask=None, contiguous=False), View(shape=(32, 96, 8, 16), strides=(12288, 128, 16, 1), offset=0, mask=None, contiguous=True))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(544301), arg=16, src=()),)),)),)),)),)),)),)),)),)),)),)),)), + UOp(Ops.RECIP, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(1, 96, 1, 1), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=17, src=()),)),)), + UOp(Ops.CONST, dtypes.float, arg=2.0, src=( + x5,)),)),)),)), + x79:=UOp(Ops.RECIP, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(96), arg=ShapeTracker(views=(View(shape=(1, 96, 1, 1), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(96), arg=18, src=()),)),)), + x4,)), + UOp(Ops.CONST, dtypes.float, arg=1e-05, src=( + x5,)),)),)),)), + x79,)),)),)),)) + opts = [] + helper_test_lin(Kernel(ast), opts, failed_platforms=["METAL", "CUDA"]) + + def test_failure_23(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(9600), arg=ShapeTracker(views=(View(shape=(240, 40, 1, 1), strides=(40, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9600), arg=0, src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(9600), arg=ShapeTracker(views=(View(shape=(240, 40, 1, 1), strides=(1, 240, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9600), arg=1, src=()),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.LOCAL, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=3, arg=2)] + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_24(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(256), arg=ShapeTracker(views=(View(shape=(8, 32, 1, 1), strides=(32, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(256), arg=0, src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(256), arg=ShapeTracker(views=(View(shape=(8, 32, 1, 1), strides=(1, 8, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(256), arg=1, src=()),)),)),)),)) + opts = [Opt(op=OptOps.LOCAL, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=2, arg=2), Opt(op=OptOps.LOCAL, axis=1, arg=8), Opt(op=OptOps.UPCAST, axis=2, arg=0), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=0, arg=2)] + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + # this is the cause of the GPT2 BEAM instability. bisects to PR#3530 O(n) arange attempt + def test_failure_25(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(1024), arg=ShapeTracker(views=(View(shape=(1024, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1024), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1025, 2047), strides=(0, 0), offset=0, mask=((0, 1025), (1023, 2047)), contiguous=False), View(shape=(1024, 1024), strides=(1, 2048), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=1, src=( + x9:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 1024), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=0, src=( + x9,)),)),)), + UOp(Ops.CONST, dtypes.int, arg=-1, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) + opts = [Opt(op=OptOps.GROUP, axis=0, arg=16), Opt(op=OptOps.UNROLL, axis=0, arg=4)] + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + # COMPARE_ERROR from GPT2 kernel - stems from uops.py self.simplify_phi_loops + def test_failure_26(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(128), arg=ShapeTracker(views=(View(shape=(128, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(128), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(129, 255), strides=(0, 0), offset=0, mask=((0, 129), (127, 255)), contiguous=False), View(shape=(128, 128), strides=(1, 256), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=1, src=( + x9:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(128, 128), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=0, src=( + x9,)),)),)), + UOp(Ops.CONST, dtypes.int, arg=-1, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(128, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) + all_failing_opts = [ + [Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.GROUPTOP, axis=0, arg=32), Opt(op=OptOps.UNROLL, axis=0, arg=0)], + [Opt(op=OptOps.GROUPTOP, axis=0, arg=32), Opt(op=OptOps.UNROLL, axis=0, arg=0), Opt(op=OptOps.UPCAST, axis=0, arg=4)], + [Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=0, arg=0)], + [Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0)], + [Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.UNROLL, axis=0, arg=4)], + [Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0)], + [Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.UNROLL, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=4)], + [Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=8), Opt(op=OptOps.UNROLL, axis=1, arg=4)], + [Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.GROUP, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.UNROLL, axis=1, arg=4)], + [Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.GROUP, axis=0, arg=16), Opt(op=OptOps.UNROLL, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0)], + [Opt(op=OptOps.GROUP, axis=0, arg=8), Opt(op=OptOps.UNROLL, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=16), Opt(op=OptOps.UPCAST, axis=0, arg=0)], + ] + for opts in all_failing_opts: + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + # COMPARE_ERROR from GPT2 kernel - just the first element off + # testing ast 41 + # 0 ━┳ STORE MemBuffer(idx=0, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(1, 16, 13, 1), strides=(0, 13, 1, 0), offset=0, mask=None, contiguous=True),))) + # 1 ┗━┳ MAX (3,) + # 2 ┗━━ LOAD MemBuffer(idx=1, dtype=dtypes.half, st=ShapeTracker(views=(View(shape=(1, 16, 13, 13), strides=(0, 169, 13, 1), offset=0, mask=None, contiguous=True),))) + # 208 13 + # ... + # Mismatched elements: 1 / 1232 (0.0812%) + # Max absolute difference: 0.8687 + # Max relative difference: 1. + # x: array([0. , 0.996, 0.829, ..., 0. , 0. , 0. ], dtype=float16) + # y: array([0.8687, 0.996 , 0.829 , ..., 0. , 0. , 0. ], dtype=float16) + # COMPARE FAILED!! + def test_failure_27(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(208), arg=ShapeTracker(views=(View(shape=(1, 16, 13, 1), strides=(0, 13, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(208), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.half, arg=(Ops.MAX, (3,)), src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(2704), arg=ShapeTracker(views=(View(shape=(1, 16, 13, 13), strides=(0, 169, 13, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(2704), arg=1, src=()),)),)),)),)),)) + all_failing_opts = [ + [Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=7), Opt(op=OptOps.UPCAST, axis=0, arg=0)], + ] + for opts in all_failing_opts: + helper_test_lin(Kernel(ast), opts, failed_platforms=[]) + + def test_failure_28(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.bfloat16.ptr(1), arg=ShapeTracker(views=(View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.bfloat16.ptr(1), arg=0, src=()),)), + UOp(Ops.WHERE, dtypes.bfloat16, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + x5:=UOp(Ops.CAST, dtypes.bfloat16, arg=None, src=( + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(1), arg=ShapeTracker(views=(View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1), arg=1, src=()),)),)),)), + x9:=UOp(Ops.CONST, dtypes.bfloat16, arg=230.0, src=( + x10:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True),)), src=()),)),)), + UOp(Ops.ADD, dtypes.bfloat16, arg=None, src=( + UOp(Ops.MUL, dtypes.bfloat16, arg=None, src=( + UOp(Ops.MUL, dtypes.bfloat16, arg=None, src=( + x5, + UOp(Ops.CONST, dtypes.bfloat16, arg=0.004347826086956522, src=( + x10,)),)), + UOp(Ops.CONST, dtypes.bfloat16, arg=0.199374800625, src=( + x10,)),)), + UOp(Ops.CONST, dtypes.bfloat16, arg=1.99375e-07, src=( + x10,)),)), + UOp(Ops.ADD, dtypes.bfloat16, arg=None, src=( + UOp(Ops.MUL, dtypes.bfloat16, arg=None, src=( + UOp(Ops.MUL, dtypes.bfloat16, arg=None, src=( + UOp(Ops.ADD, dtypes.bfloat16, arg=None, src=( + x5, + x9,)), + UOp(Ops.CONST, dtypes.bfloat16, arg=0.0012987012987012987, src=( + x10,)),)), + UOp(Ops.CONST, dtypes.bfloat16, arg=-0.19439062499999998, src=( + x10,)),)), + UOp(Ops.CONST, dtypes.bfloat16, arg=0.199375, src=( + x10,)),)),)),)),)) + helper_test_lin(Kernel(ast), opts=[], failed_platforms=[]) + + def test_failure_29(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(25690112), arg=ShapeTracker(views=(View(shape=(128, 1, 64, 56, 56, 1, 1, 1), strides=(200704, 0, 3136, 56, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(25690112), arg=0, src=()),)), + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(25690112), arg=ShapeTracker(views=(View(shape=(1, 128, 1, 64, 4, 58, 4, 58), strides=(0, 200704, 0, 3136, 0, 56, 0, 1), offset=-57, mask=((0, 1), (0, 128), (0, 1), (0, 64), (0, 4), (1, 57), (0, 4), (1, 57)), contiguous=False), View(shape=(128, 1, 64, 56, 56, 64, 3, 3), strides=(3444736, 0, 0, 232, 1, 53824, 13688, 59), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(25690112), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(36864), arg=ShapeTracker(views=(View(shape=(128, 1, 64, 56, 56, 64, 3, 3), strides=(0, 0, 576, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(36864), arg=2, src=()),)),)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.TC, axis=0, arg=(-1, 1, 1)), Opt(op=OptOps.PADTO, axis=2, arg=32)] + helper_test_lin(Kernel(ast), opts, failed_platforms=[], atol=1.0) + + def test_failure_30(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(2952192), arg=ShapeTracker(views=(View(shape=(256, 1, 12, 31, 31, 1, 1, 1), strides=(11532, 0, 961, 31, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(2952192), arg=0, src=()),)), + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(786432), arg=ShapeTracker(views=(View(shape=(256, 1, 12, 31, 31, 3, 2, 2), strides=(3072, 0, 0, 32, 1, 1024, 32, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(786432), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(144), arg=ShapeTracker(views=(View(shape=(256, 1, 12, 31, 31, 3, 2, 2), strides=(0, 0, 12, 0, 0, 4, 2, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(144), arg=2, src=()),)),)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.PADTO, axis=3, arg=32), Opt(op=OptOps.LOCAL, axis=3, arg=32), Opt(op=OptOps.UPCAST, axis=3, arg=4), Opt(op=OptOps.UPCAST, axis=3, arg=0)] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + # from METAL=1 fuzz_linearizer command in test.yml + def test_failure_31(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(208), arg=ShapeTracker(views=(View(shape=(1, 16, 13, 1), strides=(0, 13, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(208), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3,)), src=( + UOp(Ops.EXP2, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(2704), arg=ShapeTracker(views=(View(shape=(1, 16, 13, 13), strides=(0, 169, 13, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(2704), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(208), arg=ShapeTracker(views=(View(shape=(1, 16, 13, 13), strides=(0, 13, 1, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(208), arg=2, src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=1.4426950408889634, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 16, 13, 13), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)),)) + opts = [Opt(op=OptOps.UNROLL, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=1, arg=32)] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + @unittest.skipIf(CI, "for real AMD GPU") + def test_failure_32(self): + # kernel from beaming resnet + # Memory access fault on tinybox red + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(12845056), arg=ShapeTracker(views=(View(shape=(256, 1, 256, 14, 14, 1, 1, 1), strides=(50176, 0, 196, 14, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(12845056), arg=0, src=()),)), + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(12845056), arg=ShapeTracker(views=(View(shape=(1, 256, 1, 256, 4, 16, 4, 16), strides=(0, 50176, 0, 196, 0, 14, 0, 1), offset=-15, mask=((0, 1), (0, 256), (0, 1), (0, 256), (0, 4), (1, 15), (0, 4), (1, 15)), contiguous=False), View(shape=(256, 1, 256, 14, 14, 256, 3, 3), strides=(1048576, 0, 0, 64, 1, 4096, 1088, 17), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(12845056), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(589824), arg=ShapeTracker(views=(View(shape=(256, 1, 256, 14, 14, 256, 3, 3), strides=(0, 0, 2304, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(589824), arg=2, src=()),)),)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.TC, axis=2, arg=(-1, 2, 1)), Opt(op=OptOps.UPCAST, axis=2, arg=7), Opt(op=OptOps.UNROLL, axis=1, arg=0), Opt(op=OptOps.LOCAL, axis=1, arg=16)] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[], atol=0.1, rtol=0.05) + + def test_failure_33(self): + # Ops.UNMUL left after linearize + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + x5:=UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(26040), arg=ShapeTracker(views=(View(shape=(32640,), strides=(1,), offset=0, mask=((0, 26040),), contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(26040), arg=1, src=()),)),)), + UOp(Ops.WHERE, dtypes.float, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + x5, + x10:=UOp(Ops.CONST, dtypes.float, arg=0.0, src=( + x11:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(32640,), strides=(0,), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.WHERE, dtypes.float, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.WHERE, dtypes.float, arg=None, src=( + x18:=UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(32640,), strides=(0,), offset=0, mask=((0, 26040),), contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.float, arg=0.06788442333021306, src=( + x11,)), + x10,)), + x5,)), + UOp(Ops.WHERE, dtypes.float, arg=None, src=( + x18, + UOp(Ops.CONST, dtypes.float, arg=-0.03394221166510653, src=( + x11,)), + x10,)),)), + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(6600), arg=ShapeTracker(views=(View(shape=(32640,), strides=(1,), offset=-26040, mask=((26040, 32640),), contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6600), arg=2, src=()),)),)), + UOp(Ops.WHERE, dtypes.float, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(32640,), strides=(0,), offset=0, mask=((26040, 32640),), contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.float, arg=-0.18257418583505536, src=( + x11,)), + x10,)),)),)), + x10,)), + UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( + x11,)), + UOp(Ops.CONST, dtypes.float, arg=1.0, src=( + x11,)),)), + x10,)),)),)),)),)) + opts = [Opt(op=OptOps.GROUPTOP, axis=0, arg=16)] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + # from fuzzing on metal + def test_failure_34(self, unroll=False): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(720), arg=ShapeTracker(views=(View(shape=(4, 1, 6, 10, 3, 1, 1, 1), strides=(180, 0, 30, 3, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(720), arg=0, src=()),)), + UOp(Ops.MAX, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (6, 7)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(308), arg=ShapeTracker(views=(View(shape=(4, 1, 6, 10, 3, 1, 2, 5), strides=(77, 0, 0, 7, 1, 0, 7, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(308), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(60), arg=ShapeTracker(views=(View(shape=(4, 1, 6, 10, 3, 1, 2, 5), strides=(0, 0, 10, 0, 0, 0, 5, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(60), arg=2, src=()),)),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=0.0, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 1, 6, 10, 3, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) + opts = [Opt(op=OptOps.TC, axis=0, arg=(-1, 2, 1)), Opt(op=OptOps.UNROLL, axis=0, arg=0)] if unroll else [Opt(op=OptOps.TC, axis=0, arg=(-1, 2, 1))] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + def test_failure_35(self): self.test_failure_34(True) + + # from world fuzz_linearizer: PYTHONPATH=. METAL=1 FUZZ_ALL_ACTIONS=1 DEPTH=1 FUZZ_N=100 FUZZ_NTH=84 python3 ./test/external/fuzz_linearizer.py + def test_failure_36(self): + # Ops.UNMUL left after linearize + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.uchar.ptr(5), arg=ShapeTracker(views=(View(shape=(5, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(5), arg=0, src=()),)), + UOp(Ops.CAST, dtypes.uchar, arg=None, src=( + UOp(Ops.ADD, dtypes.uint, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.uint, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.CAST, dtypes.uint, arg=None, src=( + UOp(Ops.WHERE, dtypes.uchar, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(6, 9), strides=(0, 0), offset=0, mask=((0, 6), (4, 9)), contiguous=False), View(shape=(5, 5), strides=(1, 10), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.CONST, dtypes.uchar, arg=1, src=( + x11:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(5, 5), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.uchar, arg=0, src=( + x11,)),)),)),)), + UOp(Ops.CONST, dtypes.uint, arg=-1, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(5, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=0)] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + # BEGIN METAL=1 ./examples/beautiful_mnist.py failures + # log : PYTHONPATH=. LOGKERNS=/tmp/beautiful_mnist.kernels.txt METAL=1 python3 ./examples/beautiful_mnist.py + def test_failure_37(self): + # beautiful mnist kernel number 28: 6 possible TC axis_choices (3 for axis_buf1 and 2 reduce) and all fail + # fuzz: PYTHONPATH=. METAL=1 FUZZ_ALL_ACTIONS=1 DEPTH=1 FUZZ_NTH=28 DEBUG=2 python3 ./test/external/fuzz_linearizer.py --logfile /tmp/beautiful_mnist.kernels.txt + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(9437184), arg=ShapeTracker(views=(View(shape=(512, 1, 32, 24, 24, 1, 1, 1), strides=(18432, 0, 576, 24, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9437184), arg=0, src=()),)), + UOp(Ops.MAX, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (6, 7)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.uchar, arg=None, src=( + UOp(Ops.VIEW, dtypes.uchar.ptr(401408), arg=ShapeTracker(views=(View(shape=(512, 1, 32, 24, 24, 1, 5, 5), strides=(784, 0, 0, 28, 1, 0, 28, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(401408), arg=1, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(800), arg=ShapeTracker(views=(View(shape=(512, 1, 32, 24, 24, 1, 5, 5), strides=(0, 0, 25, 0, 0, 0, 5, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(800), arg=2, src=()),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(32), arg=ShapeTracker(views=(View(shape=(512, 1, 32, 24, 24, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(32), arg=3, src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=0.0, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(512, 1, 32, 24, 24, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) + for axis in [0,1,2,3,4,5]: + opts = [Opt(op=OptOps.TC, axis=axis, arg=(-1, 2, 1))] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + def test_failure_38(self): + # beautiful mnist kernel number 87: 6 possible TC axis_choices (2 for axis_buf1 and 3 reduce) and first/second reduce axis fail for both axis_buf1 choices + # fuzz: PYTHONPATH=. METAL=1 FUZZ_ALL_ACTIONS=1 DEPTH=1 FUZZ_NTH=87 DEBUG=2 python3 ./test/external/fuzz_linearizer.py --logfile /tmp/beautiful_mnist.kernels.txt + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(204800), arg=ShapeTracker(views=(View(shape=(1, 1, 32, 1, 1, 1, 5, 5, 256), strides=(0, 0, 6400, 0, 0, 0, 1280, 256, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(204800), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 3, 4)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.uchar, arg=None, src=( + UOp(Ops.VIEW, dtypes.uchar.ptr(401408), arg=ShapeTracker(views=(View(shape=(2, 1, 32, 24, 24, 1, 5, 5, 256), strides=(784, 0, 0, 28, 1, 0, 28, 1, 1568), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(401408), arg=1, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(9437184), arg=ShapeTracker(views=(View(shape=(2, 1, 32, 24, 24, 1, 5, 5, 256), strides=(18432, 0, 576, 24, 1, 0, 0, 0, 36864), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9437184), arg=2, src=()),)),)),)),)),)),)) + for axis in [0,1,3,4]: + opts = [Opt(op=OptOps.TC, axis=axis, arg=(-1, 2, 1))] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + @unittest.skip("very slow, similar to test_failure_37") + def test_failure_39(self): + # beautiful mnist kernel number 127: 6 possible TC axis_choices (3 for axis_buf1 and 2 reduce) and all fail + # fuzz: PYTHONPATH=. METAL=1 FUZZ_ALL_ACTIONS=1 DEPTH=1 FUZZ_NTH=127 DEBUG=2 python3 ./test/external/fuzz_linearizer.py --logfile /tmp/beautiful_mnist.kernels.txt + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(184320000), arg=ShapeTracker(views=(View(shape=(10000, 1, 32, 24, 24, 1, 1, 1), strides=(18432, 0, 576, 24, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(184320000), arg=0, src=()),)), + UOp(Ops.MAX, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (6, 7)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.uchar, arg=None, src=( + UOp(Ops.VIEW, dtypes.uchar.ptr(7840000), arg=ShapeTracker(views=(View(shape=(10000, 1, 32, 24, 24, 1, 5, 5), strides=(784, 0, 0, 28, 1, 0, 28, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(7840000), arg=1, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(800), arg=ShapeTracker(views=(View(shape=(10000, 1, 32, 24, 24, 1, 5, 5), strides=(0, 0, 25, 0, 0, 0, 5, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(800), arg=2, src=()),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(32), arg=ShapeTracker(views=(View(shape=(10000, 1, 32, 24, 24, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(32), arg=3, src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=0.0, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(10000, 1, 32, 24, 24, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) + for axis in [0,1,2,3,4,5]: + opts = [Opt(op=OptOps.TC, axis=axis, arg=(-1, 2, 1))] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + def test_failure_40(self): + # beautiful mnist kernel number 3: + # fuzz: PYTHONPATH=. METAL=1 FUZZ_ALL_ACTIONS=1 DEPTH=2 DEBUG=2 FUZZ_NTH=3 python3 ./test/external/fuzz_linearizer.py --logfile /tmp/beautiful_mnist.kernels.txt + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(60000), arg=ShapeTracker(views=(View(shape=(60000, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(60000), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(60001, 119999), strides=(0, 0), offset=0, mask=((0, 60001), (59999, 119999)), contiguous=False), View(shape=(60000, 60000), strides=(1, 120000), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=1, src=( + x9:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(60000, 60000), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=0, src=( + x9,)),)),)), + UOp(Ops.CONST, dtypes.int, arg=-1, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(60000, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) + for amt in [16,32]: + opts = [Opt(op=OptOps.GROUPTOP, axis=0, arg=amt), Opt(op=OptOps.UNROLL, axis=0, arg=0)] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + # END METAL=1 ./examples/beautiful_mnist.py failures + + @unittest.skipIf(CI, "for real AMD GPU") + def test_failure_41(self): + # One more resnet crash with a page fault on AMD. Checked on rocm6.1.3, -O1 works, -O2 fails + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(25690112), arg=ShapeTracker(views=(View(shape=(256, 1, 128, 28, 28, 1, 1, 1), strides=(100352, 0, 784, 28, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(25690112), arg=0, src=()),)), + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(102760448), arg=ShapeTracker(views=(View(shape=(1, 256, 1, 128, 4, 58, 4, 58), strides=(0, 401408, 0, 3136, 0, 56, 0, 1), offset=-57, mask=((0, 1), (0, 256), (0, 1), (0, 128), (0, 4), (1, 57), (0, 4), (1, 57)), contiguous=False), View(shape=(256, 1, 128, 28, 28, 128, 3, 3), strides=(6889472, 0, 0, 464, 2, 53824, 13688, 59), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(102760448), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(147456), arg=ShapeTracker(views=(View(shape=(256, 1, 128, 28, 28, 128, 3, 3), strides=(0, 0, 1152, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(147456), arg=2, src=()),)),)),)),)),)),)),)),)) + opts=[Opt(op=OptOps.TC, axis=5, arg=(-1, 2, 1)), Opt(op=OptOps.UNROLL, axis=0, arg=0)] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=["AMD", "HIP"], atol=0.02) + + # llama3 8B failure with BEAM=2 https://github.com/tinygrad/tinygrad/actions/runs/10150118124/job/28066519425#step:14:1, these don't compile + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test needs local") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test needs shared") + def test_failure_42(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(25, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(26, 49), strides=(0, -1), offset=48, mask=((0, 26), (24, 49)), contiguous=False), View(shape=(25, 25), strides=(1, 50), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=1, src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.GROUP, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.UPCAST, axis=0, arg=2), Opt(op=OptOps.PADTO, axis=0, arg=32)] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test needs local") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test needs shared") + def test_failure_43(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(25, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(26, 49), strides=(0, -1), offset=48, mask=((0, 26), (24, 49)), contiguous=False), View(shape=(25, 25), strides=(1, 50), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=1, src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.GROUP, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=0)] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test needs local") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test needs shared") + def test_failure_44(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(25, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(25), arg=ShapeTracker(views=(View(shape=(26, 49), strides=(0, -1), offset=48, mask=((0, 26), (24, 49)), contiguous=False), View(shape=(25, 25), strides=(1, 50), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(25), arg=1, src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.GROUP, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=0, arg=32), Opt(op=OptOps.LOCAL, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4)] + k = helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + assert k is not None + ifs = [u for u in k.uops if u.op is Ops.IF] + self.assertEqual(len(ifs), 3) + #for st in k.uops.sink.src: self.assertEqual(len(st.src), 4) + self.assertLessEqual(len(ifs[0].src[0].toposort()), 17) + + def test_failure_45(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(6), arg=ShapeTracker(views=(View(shape=(2, 3, 1, 1, 1), strides=(3, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2, 3)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(6), arg=ShapeTracker(views=(View(shape=(2, 3, 2, 3, 1), strides=(0, 0, 3, 1, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6), arg=1, src=()),)),)), + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(1), arg=ShapeTracker(views=(View(shape=(2, 3, 2, 3, 1), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1), arg=2, src=()),)),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (4,)), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(3, 3), strides=(0, 0), offset=0, mask=((0, 3), (1, 3)), contiguous=False), View(shape=(2, 3, 2, 3, 3), strides=(0, 0, 1, 0, 4), offset=0, mask=((0, 2), (0, 3), (0, 2), (0, 3), (0, 2)), contiguous=False))), src=()),)), + x20:=UOp(Ops.CONST, dtypes.int, arg=1, src=( + x21:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 3, 2, 3, 3), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + x22:=UOp(Ops.CONST, dtypes.int, arg=0, src=( + x21,)),)),)), + x23:=UOp(Ops.CONST, dtypes.int, arg=-1, src=( + x24:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 3, 2, 3, 1), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), + x25:=UOp(Ops.CONST, dtypes.bool, arg=True, src=( + x24,)),)), + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(6), arg=ShapeTracker(views=(View(shape=(2, 3, 2, 3, 1), strides=(3, 1, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(6), arg=3, src=()),)),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (4,)), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(4, 5), strides=(0, 0), offset=0, mask=((0, 4), (2, 5)), contiguous=False), View(shape=(2, 3, 2, 3, 3), strides=(0, 0, 0, 1, 6), offset=0, mask=None, contiguous=False))), src=()),)), + x20, + x22,)),)), + x23,)),)), + x25,)),)),)),)),)),)),)) + # ValueError: size mismatched, can't reshape self.shape=(6, 2, 3, 3) -> new_shape=(6, 2, 3, 1, 2) + opts = [Opt(op=OptOps.UNROLL, axis=2, arg=0)] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + def test_failure_46(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(512), arg=ShapeTracker(views=(View(shape=(512, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(512), arg=0, src=()),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(10), arg=ShapeTracker(views=(View(shape=(512, 10), strides=(0, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(10), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(512), arg=ShapeTracker(views=(View(shape=(512, 10), strides=(1, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(512), arg=2, src=()),)),)),)), + UOp(Ops.CONST, dtypes.bool, arg=True, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(512, 10), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.bool.ptr(512), arg=ShapeTracker(views=(View(shape=(512, 10), strides=(1, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.bool.ptr(512), arg=3, src=()),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(1), arg=ShapeTracker(views=(View(shape=(512, 10), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(1), arg=4, src=()),)),)),)),)), + UOp(Ops.RECIP, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(512), arg=ShapeTracker(views=(View(shape=(512, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(512), arg=5, src=()),)),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=2)] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + def test_failure_47(self): + # upcast an arange, failed with UOP_IS_SYMBOLIC=1 (fixed!) + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(60000), arg=ShapeTracker(views=(View(shape=(60000, 1), strides=(1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(60000), arg=0, src=()),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(60001, 119999), strides=(0, 0), offset=0, mask=((0, 60001), (59999, 119999)), contiguous=False), View(shape=(60000, 60000), strides=(1, 120000), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=1, src=( + x9:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(60000, 60000), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=0, src=( + x9,)),)),)), + UOp(Ops.CONST, dtypes.int, arg=-1, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(60000, 1), strides=(0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=3)] + helper_test_lin(Kernel(ast), opts=opts, failed_platforms=[]) + + @unittest.skipUnless(not CI and Device.DEFAULT in ("NV", "CUDA"), "for real NV") + def test_failure_48(self): + # with UOP_IS_SYMBOLIC=1, generates the wrong IDIV (fixed!) + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(4194304), arg=ShapeTracker(views=(View(shape=(1, 1, 64, 1, 1, 256, 1, 1, 256), strides=(0, 0, 65536, 0, 0, 256, 0, 0, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4194304), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (3, 4)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(205520896), arg=ShapeTracker(views=(View(shape=(1, 1, 64, 56, 56, 256, 1, 1, 256), strides=(0, 0, 0, 56, 1, 3136, 0, 0, 802816), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(205520896), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(51380224), arg=ShapeTracker(views=(View(shape=(1, 1, 64, 56, 56, 256, 1, 1, 256), strides=(0, 0, 3136, 56, 1, 0, 0, 0, 200704), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(51380224), arg=2, src=()),)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.TC, axis=0, arg=(-1, 0, 1)), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=2)] + helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) + + def test_failure_49(self): + # with UOP_IS_SYMBOLIC=1, on METAL it breaks store fusion and has A+B and B+A being two different UOp + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(60), arg=ShapeTracker(views=(View(shape=(10, 6, 1), strides=(6, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(60), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(100), arg=ShapeTracker(views=(View(shape=(10, 6, 10), strides=(10, 0, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(100), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(60), arg=ShapeTracker(views=(View(shape=(10, 6, 10), strides=(0, 1, 6), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(60), arg=2, src=()),)),)),)),)),)),)) + opts = [Opt(op=OptOps.TC, axis=0, arg=(-1, 2, 1)), Opt(op=OptOps.UPCAST, axis=0, arg=2)] + helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) + + def test_failure_50(self): + # from BEAM_COMPARE=2 running tinyphysics.onnx model + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.bool.ptr(400), arg=ShapeTracker(views=(View(shape=(1, 1, 20, 1, 20), strides=(0, 0, 20, 0, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.bool.ptr(400), arg=0, src=()),)), + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.bool, arg=(Ops.ADD, (3,)), src=( + UOp(Ops.MUL, dtypes.bool, arg=None, src=( + UOp(Ops.LOAD, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.bool.ptr(400), arg=ShapeTracker(views=(View(shape=(1, 1, 20, 20, 20), strides=(0, 0, 0, 20, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.bool.ptr(400), arg=1, src=()),)),)), + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(20), arg=ShapeTracker(views=(View(shape=(1, 1, 20, 20, 20), strides=(0, 0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(20), arg=2, src=()),)),)), + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(20), arg=ShapeTracker(views=(View(shape=(1, 1, 20, 20, 20), strides=(0, 0, 0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(20), arg=3, src=()),)),)),)), + UOp(Ops.CONST, dtypes.bool, arg=True, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 1, 20, 20, 20), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)), + UOp(Ops.CONST, dtypes.bool, arg=True, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 1, 20, 1, 20), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=2)] + helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) + + def test_failure_51(self): + # regression test for #7019, training bert on tinybox red + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(12288), arg=ShapeTracker(views=(View(shape=(12, 1024, 1), strides=(1024, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(12288), arg=0, src=()),)), + UOp(Ops.RECIP, dtypes.half, arg=None, src=( + UOp(Ops.ADD, dtypes.half, arg=None, src=( + UOp(Ops.CONST, dtypes.half, arg=1.0, src=( + x6:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(12, 1024, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.EXP2, dtypes.half, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.CONST, dtypes.half, arg=2.0, src=( + x6,)), + UOp(Ops.ADD, dtypes.half, arg=None, src=( + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (2,)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(5768192), arg=ShapeTracker(views=(View(shape=(12, 1024, 1024), strides=(524288, 0, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(5768192), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(1048576), arg=ShapeTracker(views=(View(shape=(12, 1024, 1024), strides=(0, 1024, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1048576), arg=2, src=()),)),)),)),)),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(1024), arg=ShapeTracker(views=(View(shape=(12, 1024, 1), strides=(0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1024), arg=3, src=()),)),)),)),)), + UOp(Ops.CONST, dtypes.half, arg=-1.4426950408889634, src=( + x6,)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.TC, axis=0, arg=(-1, 2, 1))] + helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) + + @unittest.skip("allocating over 200MB buffer") + @unittest.skipIf(CI and Device.DEFAULT in {"METAL"}, "hangs metal gpu CI") + def test_failure_52(self): + # resnet beam. + # NV also fails with a pf. + # CUDA Error 700, an illegal memory access was encountered + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(205520896), arg=ShapeTracker(views=(View(shape=(256, 1, 64, 112, 112, 1, 1, 1), strides=(802816, 0, 12544, 112, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(205520896), arg=0, src=()),)), + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(38535168), arg=ShapeTracker(views=(View(shape=(1, 256, 1, 3, 8, 230, 8, 230), strides=(0, 150528, 0, 50176, 0, 224, 0, 1), offset=-675, mask=((0, 1), (0, 256), (0, 1), (0, 3), (0, 8), (3, 227), (0, 8), (3, 227)), contiguous=False), View(shape=(256, 1, 64, 112, 112, 3, 7, 7), strides=(10156800, 0, 0, 3680, 2, 3385600, 425040, 231), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(38535168), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(9408), arg=ShapeTracker(views=(View(shape=(256, 1, 64, 112, 112, 3, 7, 7), strides=(0, 0, 147, 0, 0, 49, 7, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(9408), arg=2, src=()),)),)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.TC, axis=0, arg=(-1, 2, 1)), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=16)] + helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) + + def test_failure_53(self): + # COMPILE_ERROR, val scope issue + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.uchar.ptr(1024), arg=ShapeTracker(views=(View(shape=(1024, 1, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(1024), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.uchar, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.MUL, dtypes.uchar, arg=None, src=( + UOp(Ops.LOAD, dtypes.uchar, arg=None, src=( + UOp(Ops.VIEW, dtypes.uchar.ptr(50000), arg=ShapeTracker(views=(View(shape=(1024, 50000, 1), strides=(0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(50000), arg=1, src=()),)),)), + UOp(Ops.CAST, dtypes.uchar, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(1024), arg=ShapeTracker(views=(View(shape=(1024, 50000, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1024), arg=2, src=()),)),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (2,)), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(50001, 99999), strides=(0, 0), offset=0, mask=((0, 50001), (49999, 99999)), contiguous=False), View(shape=(1024, 50000, 50000), strides=(0, 1, 100000), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=1, src=( + x20:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 50000, 50000), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=0, src=( + x20,)),)),)), + UOp(Ops.CONST, dtypes.int, arg=-1, src=( + x23:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 50000, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), + UOp(Ops.CONST, dtypes.bool, arg=True, src=( + x23,)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.GROUPTOP, axis=1, arg=16)] + helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=["AMD", "GPU", "METAL", "NV", "CUDA"]) + + @unittest.skipIf(CI and Device.DEFAULT in {"METAL"}, "hangs metal gpu CI") + def test_failure_54(self): + # resnet beam + # HIP: Memory access fault by GPU node-1 (Agent handle: 0x56c21f1d1480) on address 0x730cc242e000. Reason: Page not present or supervisor privilege. + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(51380224), arg=ShapeTracker(views=(View(shape=(256, 1, 64, 56, 56, 1, 1, 1), strides=(200704, 0, 3136, 56, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(51380224), arg=0, src=()),)), + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(51380224), arg=ShapeTracker(views=(View(shape=(1, 256, 1, 64, 4, 58, 4, 58), strides=(0, 200704, 0, 3136, 0, 56, 0, 1), offset=-57, mask=((0, 1), (0, 256), (0, 1), (0, 64), (0, 4), (1, 57), (0, 4), (1, 57)), contiguous=False), View(shape=(256, 1, 64, 56, 56, 64, 3, 3), strides=(3444736, 0, 0, 232, 1, 53824, 13688, 59), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(51380224), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(36864), arg=ShapeTracker(views=(View(shape=(256, 1, 64, 56, 56, 64, 3, 3), strides=(0, 0, 576, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(36864), arg=2, src=()),)),)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.TC, axis=2, arg=(-1, 2, 1)), Opt(op=OptOps.UPCAST, axis=2, arg=7), Opt(op=OptOps.UPCAST, axis=1, arg=2)] + helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=["HIP", "AMD"]) + + @unittest.skipIf(CI and Device.DEFAULT in {"METAL"}, "hangs metal gpu CI") + def test_failure_55(self): + W = 2 + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(W * 200704), arg=ShapeTracker(views=(View(shape=(W, 1, 64, 56, 56, 1, 1, 1), strides=(200704, 0, 3136, 56, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(W * 200704), arg=0, src=()),)), + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(W * 200704), arg=ShapeTracker(views=(View(shape=(1, W, 1, 64, 4, 58, 4, 58), strides=(0, 200704, 0, 3136, 0, 56, 0, 1), offset=-57, mask=((0, 1), (0, W), (0, 1), (0, 64), (0, 4), (1, 57), (0, 4), (1, 57)), contiguous=False), View(shape=(W, 1, 64, 56, 56, 64, 3, 3), strides=(3444736, 0, 0, 232, 1, 53824, 13688, 59), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(W * 200704), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(W * 18432), arg=ShapeTracker(views=(View(shape=(W, 1, 64, 56, 56, 64, 3, 3), strides=(0, 0, 576, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(W * 18432), arg=2, src=()),)),)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.SWAP, axis=1, arg=2)] + helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) + + def test_failure_56(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(1, 16, 1, 1), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 3)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + x7:=UOp(Ops.CONST, dtypes.float, arg=0.0, src=( + x8:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.MAX, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(247808), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(1936, 121, 11, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(247808), arg=1, src=()),)),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=2, src=()),)),)), + UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( + x8,)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=3, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=4, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=5, src=()),)),)),)), + x7,)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(204800), arg=ShapeTracker(views=(View(shape=(128, 16, 5, 2, 5, 2), strides=(1600, 100, 20, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(128, 16, 11, 11), strides=(1600, 100, 10, 1), offset=0, mask=((0, 128), (0, 16), (0, 10), (0, 10)), contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(204800), arg=6, src=()),)),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=2, arg=32)] + helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) + + def test_failure_57(self): + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(1, 16, 1, 1), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (0, 2, 3)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + x7:=UOp(Ops.CONST, dtypes.float, arg=0.0, src=( + x8:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.MAX, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(247808), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(1936, 121, 11, 1), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(247808), arg=1, src=()),)),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=2, src=()),)),)), + UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( + x8,)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=3, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=4, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(16), arg=ShapeTracker(views=(View(shape=(128, 16, 11, 11), strides=(0, 1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16), arg=5, src=()),)),)),)), + x7,)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(204800), arg=ShapeTracker(views=(View(shape=(128, 16, 5, 2, 5, 2), strides=(1600, 100, 20, 2, 4, 1), offset=0, mask=None, contiguous=False), View(shape=(128, 16, 11, 11), strides=(1600, 100, 10, 1), offset=0, mask=((0, 128), (0, 16), (0, 10), (0, 10)), contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(204800), arg=6, src=()),)),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=0), Opt(op=OptOps.PADTO, axis=1, arg=32)] + helper_test_lin(Kernel(ast, opts=Device[Device.DEFAULT].renderer), opts=opts, failed_platforms=[]) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test needs local") + def test_failure_59(self): + # stable diffusion with SINGLE_KERNEL_SOFTMAX=1 + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(268435456), arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 1, 1), strides=(134217728, 16777216, 4096, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(268435456), arg=0, src=()),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.EXP2, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(268435456), arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 1, 1), strides=(134217728, 16777216, 4096, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + x9:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(268435456), arg=1, src=()),)),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.MAX, (5,), True), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(268435456), arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 1, 4096), strides=(134217728, 16777216, 4096, 0, 0, 1), offset=0, mask=None, contiguous=False),)), src=( + x9,)),)),)), + UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( + x15:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 1, 1), strides=(0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=1.4426950408889634, src=( + x15,)),)),)), + UOp(Ops.RECIP, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (4,)), src=( + UOp(Ops.EXP2, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(268435456), arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 4096, 1), strides=(134217728, 16777216, 4096, 0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( + x9,)),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.MAX, (5,), True), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(268435456), arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 4096, 4096), strides=(134217728, 16777216, 4096, 0, 0, 1), offset=0, mask=None, contiguous=False),)), src=( + x9,)),)),)), + UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( + x29:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 8, 4096, 4096, 4096, 1), strides=(0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=1.4426950408889634, src=( + x29,)),)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UNROLL, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.LOCAL, axis=1, arg=16)] + # NOTE: this is slow to run, just confirm it can generate the program without Exception + Kernel(ast, opts=Device[Device.DEFAULT].renderer).apply_opts(opts).to_program() + + @unittest.expectedFailure + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_local, "test needs local") + def test_failure_60(self): + # TestSymbolicOps.test_attention + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(80), arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), 1, 1), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x2:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)), + x2,)), + UOp(Ops.CONST, dtypes.int, arg=4, src=()),)), UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x1:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)), + x1,)), 0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(80), arg=0, src=()),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.EXP2, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(80), arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), 1, 1), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x2:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)), + x2,)), + UOp(Ops.CONST, dtypes.int, arg=4, src=()),)), UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x1:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)), + x1,)), 0, 1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(80), arg=1, src=()),)),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.MAX, (5,), True), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(80), arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=())), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=4, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x3:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), + x3,)), UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x1:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x1, + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), + x1,)), 0, UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=0, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x3:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), + x3,)), 0, 1), offset=0, mask=None, contiguous=False),)), src=( + x14:=UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(80), arg=2, src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( + x16:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), 1, 1), strides=(0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=1.4426950408889634, src=( + x16,)),)),)), + UOp(Ops.RECIP, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (4,)), src=( + UOp(Ops.EXP2, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(80), arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), 1), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=4, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x3:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), + x3,)), UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x1:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x1, + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), + x1,)), 0, UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=0, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x3:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), + x3,)), 1, 0), offset=0, mask=None, contiguous=False),)), src=( + x14,)),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.MAX, (5,), True), src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(80), arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=())), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=4, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), UOp(Ops.MUL, dtypes.int, arg=None, src=( + x0:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x0, + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), 0, UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=0, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), 1), offset=0, mask=None, contiguous=False), View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=())), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=4, src=()), + x2:=UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), + x2,)), UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x1:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + x2:=UOp(Ops.MUL, dtypes.int, arg=None, src=( + x1, + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), + x2,)), 0, UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=0, src=()), + x2:=UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), + x2,)), UOp(Ops.MUL, dtypes.int, arg=None, src=( + x0:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x0, + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), 1), offset=0, mask=None, contiguous=False))), src=( + x14,)),)),)), + UOp(Ops.CONST, dtypes.float, arg=-1.0, src=( + x30:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=())), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=False), View(shape=(2, 4, 1, UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()), 1), strides=(UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=4, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x3:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), + x3,)), UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x1:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x1, + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), + x1,)), 0, UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.CONST, dtypes.int, arg=0, src=()), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x3:=UOp(Ops.CONST, dtypes.int, arg=1, src=()), + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10), src=()),)),)), + x3,)), 1, 0), offset=0, mask=None, contiguous=False))), src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=1.4426950408889634, src=( + x30,)),)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.LOCAL, axis=0, arg=2), Opt(op=OptOps.LOCAL, axis=0, arg=4)] + # NOTE: this is slow to run, just confirm it can generate the program without Exception + Kernel(ast, opts=Device[Device.DEFAULT].renderer).apply_opts(opts).to_program() + + def test_failure_61(self): + # WINO=1 JITBEAM=4 python3 examples/beautiful_cifar.py + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(1024), arg=ShapeTracker(views=(View(shape=(1024, 1, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1024), arg=0, src=()),)), + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + x7:=UOp(Ops.CONST, dtypes.half, arg=0.6931471805599453, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 1, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (1,)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.CONST, dtypes.half, arg=-1.0, src=( + x14:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 10, 1), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.ADD, dtypes.half, arg=None, src=( + UOp(Ops.CONST, dtypes.half, arg=-0.010000000000000002, src=( + x14,)), + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(1024), arg=ShapeTracker(views=(View(shape=(1024, 10, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(1024), arg=1, src=()),)),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.int, arg=(Ops.ADD, (2,), True), src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.VALID, dtypes.bool, arg=None, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(11, 19), strides=(0, 0), offset=0, mask=((0, 11), (9, 19)), contiguous=False), View(shape=(1024, 10, 10), strides=(0, 1, 20), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=1, src=( + x30:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 10, 10), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.CONST, dtypes.int, arg=0, src=( + x30,)),)),)), + UOp(Ops.CONST, dtypes.int, arg=-1, src=( + x14,)),)),)), + UOp(Ops.CONST, dtypes.bool, arg=True, src=( + x14,)),)),)), + UOp(Ops.CONST, dtypes.half, arg=-0.4, src=( + x14,)),)),)),)),)),)),)),)), + UOp(Ops.RECIP, dtypes.half, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.VIEW, dtypes.half.ptr(1024), arg=ShapeTracker(views=(View(shape=(1024, 1, 1), strides=(1, 0, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(1024), arg=2, src=()),)),)), + x7,)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.LOCAL, axis=0, arg=32), Opt(op=OptOps.GROUP, axis=1, arg=0)] + helper_test_lin(Kernel(ast), opts, failed_platforms=["AMD", "METAL", "CUDA", "NV"]) + + def test_failure_62(self): + # WINO=1 DEFAULT_FLOAT=HALF FUSE_ARANGE=1 JITBEAM=4 BS=1024 STEPS=500 python examples/hlb_cifar10.py + # RuntimeError: UOp verification failed at 4 on Ops.LOAD dtypes.half 2 [, ] None + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(11808768), arg=0, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 1, 12, 31, 31, 1, 1, 1), strides=(11532, 0, 961, 31, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.CAST, dtypes.half, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (5, 6, 7)), src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.half, arg=None, src=( + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(3145728), arg=1, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 1, 12, 31, 31, 3, 2, 2), strides=(3072, 0, 0, 32, 1, 1024, 32, 1), offset=0, mask=None, contiguous=False),)), src=()),)), + UOp(Ops.LOAD, dtypes.half, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.half.ptr(144), arg=2, src=()), + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1024, 1, 12, 31, 31, 3, 2, 2), strides=(0, 0, 12, 0, 0, 4, 2, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)),)),)) + opts = [Opt(op=OptOps.LOCAL, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=1, arg=3), Opt(op=OptOps.LOCAL, axis=0, arg=8), Opt(op=OptOps.PADTO, axis=2, arg=32), Opt(op=OptOps.UPCAST, axis=2, arg=4), Opt(op=OptOps.UPCAST, axis=2, arg=0), Opt(op=OptOps.GROUP, axis=0, arg=0)] + helper_test_lin(Kernel(ast), opts, failed_platforms=["AMD", "HIP", "NV", "CUDA"]) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_linearizer_overflows.py b/tinygrad_repo/test/test_linearizer_overflows.py new file mode 100644 index 000000000..9192d6145 --- /dev/null +++ b/tinygrad_repo/test/test_linearizer_overflows.py @@ -0,0 +1,195 @@ +# ruff: noqa: E501 +import unittest +from tinygrad import dtypes, Device +from tinygrad.helpers import CI +from tinygrad.opt.kernel import Kernel +from tinygrad.opt.search import Opt, OptOps, bufs_from_lin +from extra.optimization.helpers import time_linearizer + +# stuff needed to unpack a kernel +from tinygrad.uop.ops import UOp, Ops +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.shape.view import View + +def _test_overflow(ast, opts): + lin = Kernel(ast) + lin.apply_opts(opts) + lin.linearize() + bufs = bufs_from_lin(lin) + print(bufs) + time_linearizer(lin, bufs) + +# NOTE: if you want these to trigger, set launch bounds on HIP kernels +@unittest.skip("unneeded without launch bounds") +class TestLinearizerOverflow(unittest.TestCase): + def test_overflow_1(self): + ast = UOp(Ops.SINK, None, arg=None, src=( + UOp(Ops.STORE, None, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(51380224), arg=0, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(64, 1, 64, 112, 112, 1, 1, 1), strides=(802816, 0, 12544, 112, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.MAX, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9633792), arg=1, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 64, 1, 3, 8, 230, 8, 230), strides=(0, 150528, 0, 50176, 0, 224, 0, 1), offset=-675, mask=((0, 1), (0, 64), (0, 1), (0, 3), (0, 8), (3, 227), (0, 8), (3, 227)), contiguous=False), View(shape=(64, 1, 64, 112, 112, 3, 7, 7), strides=(10156800, 0, 0, 3680, 2, 3385600, 425040, 231), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(9408), arg=2, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(64, 1, 64, 112, 112, 3, 7, 7), strides=(0, 0, 147, 0, 0, 49, 7, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), + x16:=UOp(Ops.CONST, dtypes.float, arg=0.0, src=( + x17:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(64, 1, 64, 112, 112, 1, 1, 1), strides=(0, 0, 0, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=3, src=()), + x20:=UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(64, 1, 64, 112, 112, 1, 1, 1), strides=(0, 0, 1, 0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.SQRT, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + x23:=UOp(Ops.CONST, dtypes.float, arg=1.0, src=( + x17,)), + UOp(Ops.RECIP, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + x23, + UOp(Ops.CONST, dtypes.float, arg=1e-05, src=( + x17,)),)),)),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64), arg=4, src=()), + x20,)),)), + x16,)),)),)) + opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.LOCAL, axis=2, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=2, arg=0)] + _test_overflow(ast, opts) + + # From BEAM on hlb_cifar.py + def test_overflow_2(self): + ast = UOp(Ops.SINK, None, arg=None, src=( + UOp(Ops.STORE, None, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(33554432), arg=0, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(512, 1, 64, 32, 32, 1, 1, 1), strides=(65536, 0, 1024, 32, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(16777216), arg=1, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 512, 1, 32, 4, 34, 4, 34), strides=(0, 32768, 0, 1024, 0, 32, 0, 1), offset=-33, mask=((0, 1), (0, 512), (0, 1), (0, 32), (0, 4), (1, 33), (0, 4), (1, 33)), contiguous=False), View(shape=(512, 1, 64, 32, 32, 32, 3, 3), strides=(591872, 0, 0, 136, 1, 18496, 4760, 35), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(18432), arg=2, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(512, 1, 64, 32, 32, 32, 3, 3), strides=(0, 0, 288, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.LOCAL, axis=2, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=2, arg=0), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=0)] + _test_overflow(ast, opts) + + # from BEAM on default simple_conv.py (which is quite large): + def test_overflow_3(self): + ast = UOp(Ops.SINK, None, arg=None, src=( + UOp(Ops.STORE, None, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(33554432), arg=0, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(16, 1, 128, 128, 128, 1, 1, 1), strides=(2097152, 0, 16384, 128, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(33554432), arg=1, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 16, 1, 128, 4, 130, 4, 130), strides=(0, 2097152, 0, 16384, 0, 128, 0, 1), offset=-129, mask=((0, 1), (0, 16), (0, 1), (0, 128), (0, 4), (1, 129), (0, 4), (1, 129)), contiguous=False), View(shape=(16, 1, 128, 128, 128, 128, 3, 3), strides=(34611200, 0, 0, 520, 1, 270400, 68120, 131), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(147456), arg=2, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(16, 1, 128, 128, 128, 128, 3, 3), strides=(0, 0, 1152, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.LOCAL, axis=2, arg=8), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=2, arg=2)] + _test_overflow(ast, opts) + + # from BEAM on BS=4 simple_conv.py: + def test_overflow_4(self): + ast = UOp(Ops.SINK, None, arg=None, src=( + UOp(Ops.STORE, None, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(8388608), arg=0, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(4, 1, 128, 128, 128, 1, 1, 1), strides=(2097152, 0, 16384, 128, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(8388608), arg=1, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 4, 1, 128, 4, 130, 4, 130), strides=(0, 2097152, 0, 16384, 0, 128, 0, 1), offset=-129, mask=((0, 1), (0, 4), (0, 1), (0, 128), (0, 4), (1, 129), (0, 4), (1, 129)), contiguous=False), View(shape=(4, 1, 128, 128, 128, 128, 3, 3), strides=(34611200, 0, 0, 520, 1, 270400, 68120, 131), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(147456), arg=2, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(4, 1, 128, 128, 128, 128, 3, 3), strides=(0, 0, 1152, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=3, arg=4), Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=2, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=2, arg=4)] + _test_overflow(ast, opts) + + # from BEAM on BS=2 simple_conv.py: + def test_overflow_5(self): + ast = UOp(Ops.SINK, None, arg=None, src=( + UOp(Ops.STORE, None, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4194304), arg=0, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(2, 1, 128, 128, 128, 1, 1, 1), strides=(2097152, 0, 16384, 128, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(4194304), arg=1, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 2, 1, 128, 4, 130, 4, 130), strides=(0, 2097152, 0, 16384, 0, 128, 0, 1), offset=-129, mask=((0, 1), (0, 2), (0, 1), (0, 128), (0, 4), (1, 129), (0, 4), (1, 129)), contiguous=False), View(shape=(2, 1, 128, 128, 128, 128, 3, 3), strides=(34611200, 0, 0, 520, 1, 270400, 68120, 131), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(147456), arg=2, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(2, 1, 128, 128, 128, 128, 3, 3), strides=(0, 0, 1152, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.LOCAL, axis=2, arg=2), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=2, arg=2)] + _test_overflow(ast, opts) + + # from BEAM on BS=3 simple_conv.py: + def test_overflow_6(self): + ast = UOp(Ops.SINK, None, arg=None, src=( + UOp(Ops.STORE, None, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6291456), arg=0, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(3, 1, 128, 128, 128, 1, 1, 1), strides=(2097152, 0, 16384, 128, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6291456), arg=1, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 3, 1, 128, 4, 130, 4, 130), strides=(0, 2097152, 0, 16384, 0, 128, 0, 1), offset=-129, mask=((0, 1), (0, 3), (0, 1), (0, 128), (0, 4), (1, 129), (0, 4), (1, 129)), contiguous=False), View(shape=(3, 1, 128, 128, 128, 128, 3, 3), strides=(34611200, 0, 0, 520, 1, 270400, 68120, 131), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(147456), arg=2, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(3, 1, 128, 128, 128, 128, 3, 3), strides=(0, 0, 1152, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.UPCAST, axis=3, arg=0), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=2, arg=8), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=3, arg=2)] + _test_overflow(ast, opts) + + # from BEAM on BS=3 simple_conv.py: (alt) + def test_overflow_7(self): + ast = UOp(Ops.SINK, None, arg=None, src=( + UOp(Ops.STORE, None, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6291456), arg=0, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(3, 1, 128, 128, 128, 1, 1, 1), strides=(2097152, 0, 16384, 128, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)), src=()), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (7, 6, 5)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(6291456), arg=1, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(1, 3, 1, 128, 4, 130, 4, 130), strides=(0, 2097152, 0, 16384, 0, 128, 0, 1), offset=-129, mask=((0, 1), (0, 3), (0, 1), (0, 128), (0, 4), (1, 129), (0, 4), (1, 129)), contiguous=False), View(shape=(3, 1, 128, 128, 128, 128, 3, 3), strides=(34611200, 0, 0, 520, 1, 270400, 68120, 131), offset=0, mask=None, contiguous=False))), src=()),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(147456), arg=2, src=()), + UOp(Ops.VIEW, None, arg=ShapeTracker(views=(View(shape=(3, 1, 128, 128, 128, 128, 3, 3), strides=(0, 0, 1152, 0, 0, 9, 3, 1), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) + opts = [Opt(op=OptOps.UPCAST, axis=3, arg=4), Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=2, arg=8), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=2, arg=4)] + _test_overflow(ast, opts) + +@unittest.skipIf(Device.DEFAULT not in {"GPU", "HSA", "CUDA", "METAL"}, "only backends with locals") +@unittest.skipIf(CI, "slow") +class TestLinearizerOverflowAlt(unittest.TestCase): + def test_overflow_1(self): + BS = 2 + g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] + in_st_1 = ShapeTracker(views=(View(shape=(1, BS, 1, 3, 8, 230, 8, 230), strides=(0, 150528, 0, 50176, 0, 224, 0, 1), offset=-675, mask=((0, 1), (0, BS), (0, 1), (0, 3), (0, 8), (3, 227), (0, 8), (3, 227)), contiguous=False), + View(shape=(BS, 1, 64, 112, 112, 3, 7, 7), strides=(10156800, 0, 0, 3680, 2, 3385600, 425040, 231), offset=0, mask=None, contiguous=False))).to_uop() + in_st_2 = ShapeTracker(views=(View(shape=(BS, 1, 64, 112, 112, 3, 7, 7), strides=(0, 0, 147, 0, 0, 49, 7, 1), offset=0, mask=None, contiguous=False),)).to_uop() + ot_st = ShapeTracker(views=(View(shape=(BS, 1, 64, 112, 112, 1, 1, 1), strides=(802816, 0, 12544, 112, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)).to_uop() + prod = UOp(Ops.LOAD, dtypes.float, (g1.view(in_st_1.arg),)) * UOp(Ops.LOAD, dtypes.float, (g2.view(in_st_2.arg),)) + store = UOp(Ops.STORE, src=(g0.view(ot_st.arg), UOp(Ops.REDUCE_AXIS, dtypes.float, (prod,), (Ops.ADD, (7, 6, 5))))) + ast = UOp(Ops.SINK, src=(store,)) + opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.LOCAL, axis=2, arg=2), Opt(op=OptOps.UPCAST, axis=0, arg=2)] + _test_overflow(ast, opts) + def test_overflow_2(self): + BS = 2 + g0, g1, g2 = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=i) for i in range(3)] + in_st_1 = ShapeTracker(views=(View(shape=(1, BS, 1, 3, 8, 230, 8, 230), strides=(0, 150528, 0, 50176, 0, 224, 0, 1), offset=-675, mask=((0, 1), (0, BS), (0, 1), (0, 3), (0, 8), (3, 227), (0, 8), (3, 227)), contiguous=False), + View(shape=(BS, 1, 64, 112, 112, 3, 7, 7), strides=(10156800, 0, 0, 3680, 2, 3385600, 425040, 231), offset=0, mask=None, contiguous=False))).to_uop() + in_st_2 = ShapeTracker(views=(View(shape=(BS, 1, 64, 112, 112, 3, 7, 7), strides=(0, 0, 147, 0, 0, 49, 7, 1), offset=0, mask=None, contiguous=False),)).to_uop() + ot_st = ShapeTracker(views=(View(shape=(BS, 1, 64, 112, 112, 1, 1, 1), strides=(802816, 0, 12544, 112, 1, 0, 0, 0), offset=0, mask=None, contiguous=True),)).to_uop() + prod = UOp(Ops.LOAD, dtypes.float, (g1.view(in_st_1.arg),)) * UOp(Ops.LOAD, dtypes.float, (g2.view(in_st_2.arg),)) + store = UOp(Ops.STORE, src=(g0.view(ot_st.arg), UOp(Ops.REDUCE_AXIS, dtypes.float, (prod,), (Ops.ADD, (7, 6, 5))))) + ast = UOp(Ops.SINK, src=(store,)) + opts = [Opt(op=OptOps.LOCAL, axis=3, arg=16), Opt(op=OptOps.UPCAST, axis=1, arg=4), Opt(op=OptOps.LOCAL, axis=2, arg=16), Opt(op=OptOps.UPCAST, axis=4, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=5, arg=2)] + _test_overflow(ast, opts) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_memory_planner.py b/tinygrad_repo/test/test_memory_planner.py new file mode 100644 index 000000000..0ba3f9040 --- /dev/null +++ b/tinygrad_repo/test/test_memory_planner.py @@ -0,0 +1,124 @@ +import unittest +from tinygrad import dtypes, Device +from tinygrad.device import Buffer +from tinygrad.engine.memory import _internal_memory_planner + +global_map = {} +def b(i, base=None, offset=0, pin=False, size=16): + global global_map + if i in global_map: return global_map[i] + global_map[i] = Buffer(Device.DEFAULT, size, dtypes.int8, base=global_map[base] if base is not None else None, offset=offset) + if pin: global_map[i].ref(1) + return global_map[i] + +def check_assign(buffers:list[list[Buffer]|tuple[Buffer, ...]]): + assigned = _internal_memory_planner(buffers, noopt_buffers=None) + + taken_parts = set() + first_appearance, last_appearance = {}, {} + for i,u in enumerate(buffers): + for buf in u: + if buf.is_allocated() or buf.base.is_allocated() or buf.uop_refcount > 0: continue + if buf.base not in first_appearance: first_appearance[buf.base] = i + last_appearance[buf.base] = i + + for i,u in enumerate(buffers): + for buf in u: + if buf.is_allocated() or buf.base.is_allocated() or buf.uop_refcount > 0: continue + cur, base = assigned.get(buf, buf), assigned.get(buf.base, buf.base) + if buf._base is not None: + assert cur.base == base.base and cur.offset == buf.offset + base.offset, f"failed: {buf} {cur} {base} {buf.offset} {base.offset}" + else: + for part in taken_parts: + assert buf.base == part[3] or part[0] != cur.base or part[1] + part[2] <= cur.offset or part[1] >= cur.offset + buf.nbytes + if first_appearance[buf.base] == i: taken_parts.add((cur.base, cur.offset, buf.nbytes, buf.base)) + if last_appearance[buf.base] == i: taken_parts.remove((cur.base, cur.offset, buf.nbytes, buf.base)) + +class TestMemoryPlanner(unittest.TestCase): + def setUp(self): + global global_map + global_map = {} + + def test_simple_buffer(self): + bs = [ + [b(0), b(1), b(2)], + [b(1), b(2), b(3)], + [b(4), b(3)], + [b(5), b(2)], + ] + check_assign(bs) + + def test_simple_pinned(self): + bs = [ + [b(0, pin=True), b(1), b(2, pin=True)], + [b(1), b(2), b(3)], + [b(4), b(3)], + [b(5), b(2)], + ] + check_assign(bs) + + def test_all_pinned(self): + bs = [ + [b(0, pin=True), b(1, pin=True)], + [b(1), b(2, pin=True)], + [b(4, pin=True), b(3, pin=True)], + ] + check_assign(bs) + + def test_simple_buffer_offset(self): + bs = [ + [b(0, pin=True), b(1, base=0, offset=1, size=8), b(2)], + [b(1), b(2), b(3, base=0, offset=1, size=8)], + [b(4), b(3)], + ] + check_assign(bs) + + def test_buffer_offset(self): + bs = [ + [b(0, pin=True), b(1, base=0, offset=1, size=8), b(2)], + [b(1), b(2), b(3, base=0, offset=1, size=8)], + [b(4), b(3)], + [b(5, base=2, offset=2, size=8), b(3)], + [b(6), b(5), b(0)], + [b(7), b(8, pin=True)], + [b(8), b(9, base=2, offset=2, size=8)], + [b(9), b(3), b(5)], + ] + check_assign(bs) + + def test_buffer_offset2(self): + bs = [ + [b(0, pin=True), b(1), b(2)], + [b(1), b(2), b(3)], + [b(4), b(3)], + [b(5), b(3)], + [b(6), b(5), b(0)], + [b(7), b(8, pin=True)], + [b(8), b(9)], + [b(9), b(3), b(5)], + [b(11), b(0)], + [b(11), b(10), b(5)], + [b(12), b(11), b(0)], + [b(6), b(12), b(7)], + [b(13), b(6), b(11)], + ] + check_assign(bs) + + def test_all_offsets_of_one(self): + bs = [ + [b(0, pin=True), b(1)], + [b(3, base=1, offset=0, size=8), b(2, base=0, offset=0, size=8)], + [b(5, base=1, offset=8, size=8), b(4, base=0, offset=8, size=8)], + [b(7, base=1, offset=4, size=8), b(6, base=0, offset=4, size=8)], + + [b(4), b(5), b(2)], + [b(3), b(7)], + [b(10), b(6), b(7)], + [b(11), b(3), b(2)], + [b(12), b(5), b(4), b(3), b(2)], + [b(13), b(6), b(12), b(7)], + ] + check_assign(bs) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/test_metal.py b/tinygrad_repo/test/test_metal.py new file mode 100644 index 000000000..3230b7b73 --- /dev/null +++ b/tinygrad_repo/test/test_metal.py @@ -0,0 +1,75 @@ +import unittest +from tinygrad.device import CompileError, Device, Compiler +if Device.DEFAULT=="METAL": + from tinygrad.runtime.ops_metal import MetalDevice, MetalCompiler, MetalProgram +@unittest.skipIf(Device.DEFAULT!="METAL", "Metal support required") +class TestMetal(unittest.TestCase): + def test_alloc_oom(self): + device = MetalDevice("metal") + with self.assertRaises(MemoryError): + device.allocator.alloc(10000000000000000000) + + def test_compile_error(self): + compiler = MetalCompiler() + with self.assertRaises(CompileError): + compiler.compile("this is not valid metal") + + def test_compile_success(self): + compiler = MetalCompiler() + ret = compiler.compile(""" +#include + using namespace metal; + kernel void E_4n1(device int* data0, const device int* data1, const device int* data2, + uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]) { + int val0 = *(data1+0); + int val1 = *(data1+1); + int val2 = *(data1+2); + int val3 = *(data1+3); + int val4 = *(data2+0); + int val5 = *(data2+1); + int val6 = *(data2+2); + int val7 = *(data2+3); + *(data0+0) = (val0+val4); + *(data0+1) = (val1+val5); + *(data0+2) = (val2+val6); + *(data0+3) = (val3+val7); + } +""") + assert ret is not None + + def test_failed_newLibraryWithData(self): + device = MetalDevice("metal") + compiler = MetalCompiler() + compiled = compiler.compile(""" +#include +kernel void r_5(device int* data0, const device int* data1, uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]){ + data0[0] = 0; +} +""") + with self.assertRaises(RuntimeError): + compiled = compiled[:40] # corrupt the compiled program + MetalProgram(device, "r_5", compiled) + + def test_program_w_empty_compiler(self): + device = MetalDevice("metal") + compiler = Compiler(device) + compiled = compiler.compile(""" +#include +kernel void r_5(device int* data0, const device int* data1, uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]){ + data0[0] = 0; +} +""") + MetalProgram(device, "r_5", compiled) + + def test_bad_program_w_empty_compiler(self): + device = MetalDevice("metal") + compiler = Compiler(device) + # this does not raise + compiled = compiler.compile(""" +#include +kernel void r_5(device int* data0, const device int* data1, uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]){ + invalid codes; +} +""") + with self.assertRaises(RuntimeError): + MetalProgram(device, "r_5", compiled) \ No newline at end of file diff --git a/tinygrad_repo/test/test_method_cache.py b/tinygrad_repo/test/test_method_cache.py new file mode 100644 index 000000000..497b40692 --- /dev/null +++ b/tinygrad_repo/test/test_method_cache.py @@ -0,0 +1,48 @@ +import unittest +from tinygrad import Tensor, Device, Variable +from examples.gpt2 import Transformer +from tinygrad.nn.state import get_state_dict + +class TestMethodCache(unittest.TestCase): + def setUp(self): + self.backup_compiler = Device[Device.DEFAULT].compiler + def tearDown(self): + Device[Device.DEFAULT].compiler = self.backup_compiler + + def test_simple_methodcache(self): + a = Tensor([1]) + b = Tensor([2]) + c = Tensor([3]) + d = Tensor([4]) + (a+b).realize() + Device[Device.DEFAULT].compiler = None + (c+d).realize() + + def test_nested_methodcache(self): + a,b,c,d = Tensor([1]), Tensor([2]), Tensor([3]), Tensor([4]) + ((a+b)+(a+b)).realize() + Device[Device.DEFAULT].compiler = None + ((c+d)+(c+d)).realize() + + def test_nested_methodcache_swap(self): + a,b,c,d = Tensor([1]), Tensor([2]), Tensor([3]), Tensor([4]) + ((a+b)+(c+d)).realize() + Device[Device.DEFAULT].compiler = None + ((c+d)+(a+b)).realize() + + @unittest.skip("incorrect use of transformer") + def test_small_transformer(self): + args_tiny = {"dim": 16, "n_heads": 8, "n_layers": 8, "norm_eps": 1e-05, "vocab_size": 10} + model = Transformer(**args_tiny) + for v in get_state_dict(model).values(): v.assign(Tensor.empty(*v.shape, dtype=v.dtype).realize()) + # NOTE: you have to do this twice due to the k-v cache + for i in range(3): model(Tensor([[1,2,3,4]]), Variable("start_pos", 0, 10).bind(i)).realize() + for i in range(3): model(Tensor([[1,2,3,4]]), Variable("start_pos", 0, 10).bind(i)).realize() + Device[Device.DEFAULT].compiler = None + for i in range(3): model(Tensor([[1,2,3,4]]), Variable("start_pos", 0, 10).bind(i)).realize() + +if __name__ == '__main__': + unittest.main() + + + diff --git a/tinygrad_repo/test/test_multitensor.py b/tinygrad_repo/test/test_multitensor.py new file mode 100644 index 000000000..7168339d4 --- /dev/null +++ b/tinygrad_repo/test/test_multitensor.py @@ -0,0 +1,1267 @@ +import unittest, functools, random +from tinygrad import Tensor, Device, nn, GlobalCounters, TinyJit, dtypes, Variable +from tinygrad.device import is_dtype_supported +from tinygrad.uop.ops import Ops, UOp +from tinygrad.helpers import CI, getenv, prod, Context, OSX +from tinygrad.nn.state import get_parameters, get_state_dict +from tinygrad.engine.realize import lower_schedule, BufferCopy, CompiledRunner, run_schedule +import numpy as np +from hypothesis import given, strategies as strat, settings +from test.helpers import REAL_DEV, not_support_multi_device + +settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) +settings.load_profile("my_profile") + +d0 = f"{Device.DEFAULT}:0" +d1 = f"{Device.DEFAULT}:1" +d2 = f"{Device.DEFAULT}:2" +d3 = f"{Device.DEFAULT}:3" +d4 = f"{Device.DEFAULT}:4" +d5 = f"{Device.DEFAULT}:5" +devices_2 = (d1, d2) +devices_3 = (d1, d2, d3) +devices_4 = (d1, d2, d3, d4) +N = 128 + +# shard_x is "data parallel" +# shard_w is "model parallel" + +def _test_allreduce(t:Tensor): + aa = (t[0:64] + t[64:128] + t[128:192] + t[192:256]).repeat([4,1]).realize() + ts = t.shard(devices_4, 0).realize() + b = Tensor(UOp.allreduce(ts.uop, Ops.ADD, ts.device)) + b.realize() + return aa, b + +@unittest.skipIf(not_support_multi_device(), "no multi") +class TestMultiTensor(unittest.TestCase): + def test_to(self): + X = Tensor.ones(256).contiguous().realize() + X.to_(devices_2) + assert X.shape == (256,) + (X + X).realize() + + def test_gradient(self): + X = Tensor.ones(256).contiguous().realize() + X.to_(devices_2) + grad = X.sum().gradient(X)[0] + grad.realize() + + def test_shard(self): + X = Tensor.ones(256).contiguous().realize() + X.shard_(devices_2, 0) + for lb in X.uop.src: + assert lb.shape == (128,) + (X + X).realize() + + def test_shard_not_multiple(self): + X = Tensor.ones(256).contiguous().realize() + with self.assertRaises(RuntimeError): + X.shard_(devices_3, 0) + + def test_tensor_from_multi(self): + X = Tensor([1, 2], dtype=dtypes.int).shard_(devices_2, 0) + Y = Tensor(X.uop) + self.assertEqual(Y.device, Device.DEFAULT) + np.testing.assert_equal(X.numpy(), Y.numpy()) + + with self.assertRaises(AssertionError): + _ = Tensor(X.uop, dtype=dtypes.float) + + def test_sharded_arange(self): + sharded_arange = Tensor.arange(1000).shard(devices_2, 0) + sharded_arange.realize() + np.testing.assert_equal(sharded_arange.numpy(), np.arange(1000)) + + # TODO: fix this to not copy on the src device + @unittest.expectedFailure + def test_shard_no_recompile(self): + X = Tensor.ones(256).contiguous().realize() + X.shard_(devices_2, 0) + out = (X + X) + sched = out.schedule() + names = [] + for si, ei in lower_schedule(sched): + if isinstance(ei.prg, CompiledRunner): names.append(ei.prg.p.name) + ei.run() + self.assertEqual(len(set(names)), 1, "function was relinearized") + + @unittest.skip("this doesn't fold because shard_ calls contiguous on all lbs") + def test_sharded_memory(self): + # Buffer may be stuck in track_cross_buffer + for x in (d0, d1, d2, d3, d4): Device[x].synchronize() + mem_base = GlobalCounters.mem_used + + X = Tensor.ones(256).contiguous().realize() + assert GlobalCounters.mem_used-mem_base== X.dtype.itemsize * 256, GlobalCounters.mem_used-mem_base + X.shard_(devices_4).realize() + for x in (d0, d1, d2, d3, d4): Device[x].synchronize() + assert GlobalCounters.mem_used-mem_base == X.dtype.itemsize * 256 * 4, GlobalCounters.mem_used-mem_base + + X = Tensor.ones(256).contiguous().realize() + assert GlobalCounters.mem_used-mem_base == X.dtype.itemsize * 256, GlobalCounters.mem_used-mem_base + X.shard_(devices_4, axis=0).realize() + for x in (d0, d1, d2, d3, d4): Device[x].synchronize() + assert GlobalCounters.mem_used-mem_base == X.dtype.itemsize * 256, GlobalCounters.mem_used-mem_base + + X = Tensor.ones(256).realize() + assert GlobalCounters.mem_used-mem_base == 0 + X.shard_(devices_4).realize() + assert GlobalCounters.mem_used-mem_base == 0 + + X = Tensor.ones(256).realize() + assert GlobalCounters.mem_used-mem_base == 0 + X.shard_(devices_4, axis=0).realize() + assert GlobalCounters.mem_used-mem_base == 0 + + def test_shard_same_device(self): + X = Tensor.ones(256).contiguous().realize() + X.shard_((d1, X.device), 0) + (X + X).realize() + + def test_shard_plus_one_sum(self): + X = Tensor.ones(256).contiguous().realize() + X.shard_((d1, d2), 0) + (X + 1).sum().realize() + + def test_shard_plus_one_sum_d0(self): + X = Tensor.ones(256).contiguous().realize() + X.shard_((d0, d2), 0) + (X + 1).sum().realize() + + def test_numpy(self): + X = Tensor.ones(256) + X.shard_((d1, d2), 0) + np.testing.assert_allclose(X.numpy(), 1) + + def _test_simple_add_axis(self, shard_x, shard_w): + X = Tensor.ones(256).contiguous().realize() + W = Tensor.ones(256).contiguous().realize() + X.shard_((d1, d2), shard_x) + W.shard_((d1, d2), shard_w) + O = X + W + np.testing.assert_allclose(O.numpy(), 2) + + def test_simple_add(self): return self._test_simple_add_axis(None, None) + def test_simple_add_X(self): return self._test_simple_add_axis(0, None) + def test_simple_add_W(self): return self._test_simple_add_axis(None, 0) + def test_simple_add_XW(self): return self._test_simple_add_axis(0, 0) + + def test_four_add(self): + X = Tensor.ones(256, 256).contiguous().realize() + W = Tensor.ones(256, 256).contiguous().realize() + X.shard_(devices_4, 1) + W.shard_(devices_4, None) + O = X + W + np.testing.assert_allclose(O.numpy(), 2) + + def test_elementwise_dtype(self): + Tensor.manual_seed(0) + X = Tensor.randn(8, 8).realize() + W = Tensor.randn(8, 8).realize() + X.shard_(devices_4, 0) + W.shard_(devices_4, 0) + O = X.shrink(((0, 2), None)) * W.shrink(((0, 2), None)) < 2 + np.testing.assert_allclose(O.numpy(), X.numpy()[0:2]*W.numpy()[0:2] < 2) + + def test_shrink_on_shard_axis(self): + X = Tensor.arange(4*4).reshape(4,4).realize() + X_np = X.numpy() + X.shard_(devices_2, 0) + # only shrink on the device that owns the shard, this is enabled by the mselect simplifier + for i in range(2): + xt = X[i*2:i*2+2].contiguous() + sched = xt.schedule() + #kernels = [s for s in sched if s.ast.op is Ops.SINK] + #self.assertEqual(len(kernels), 1) + #self.assertEqual(kernels[0].bufs[0].device, devices_2[i]) + run_schedule(sched) + np.testing.assert_equal(xt.numpy(), X_np[i*2:i*2+2]) + + @given(strat.sampled_from((4, 5)), strat.sampled_from((devices_2, devices_3)), + strat.sampled_from((Ops.ADD, Ops.MUL, Ops.MAX)), + strat.sampled_from((None, 0, 1)), strat.sampled_from((None, 0, 1)), strat.sampled_from((1, 0, -1))) + def test_simple_reduce(self, N, devices, rop, shard_axis, reduce_axis, sign): + N = N * len(devices) + X = Tensor.rand(N*N).reshape(N, N).mul(sign) + n = X.numpy() + X.shard_(devices, shard_axis) + f = {Ops.ADD: lambda x: x.sum(reduce_axis), Ops.MUL: lambda x: x.prod(reduce_axis), + Ops.MAX: lambda x: x.max(reduce_axis)}[rop] + fX = f(X) + fn = f(n) + np.testing.assert_allclose(fX.numpy(), fn, rtol=1e-6, atol=1e-6) + + def test_allreduce_naive(self): + with Context(RING=0): + a,b = _test_allreduce(Tensor.rand(256, 256)) + np.testing.assert_almost_equal(a.numpy(), b.numpy(), decimal=5) + + def test_allreduce_ring(self): + with Context(RING=2): + a,b = _test_allreduce(Tensor.rand(256, 256)) + np.testing.assert_almost_equal(a.numpy(), b.numpy(), decimal=5) + + def test_copy_jit(self): + @TinyJit + def copy_tensor(x:Tensor): return (x.to(f"{x.device.split(':')[0]}:1") + 1) + for _ in range(5): + t = Tensor.rand(256).realize() + x = copy_tensor(t) + np.testing.assert_equal((t+1).numpy(), x.numpy()) + + def test_allreduce_naive_jit(self): + with Context(RING=0): + jit_allreduce = TinyJit(_test_allreduce) + for _ in range(5): + a,b = jit_allreduce(Tensor.rand(256, 256)) + np.testing.assert_almost_equal(a.numpy(), b.numpy(), decimal=5) + + def test_allreduce_ring_jit(self): + with Context(RING=2): + jit_allreduce = TinyJit(_test_allreduce) + for _ in range(5): + a,b = jit_allreduce(Tensor.rand(256, 256)) + np.testing.assert_almost_equal(a.numpy(), b.numpy(), decimal=5) + + def test_multitensor_jit_input(self): + @TinyJit + def f(x): return (x+1).contiguous().sum() + for _ in range(5): + tt = Tensor.arange(0, 4).contiguous().realize().shard((d1,d2), 0).realize() + out = f(tt) + assert out.item() == 1+2+3+4 + + def test_multitensor_inside_jit(self): + @TinyJit + def f(x): return (x.shard((d1,d2), 0)+1).contiguous().sum() + for _ in range(5): + tt = Tensor.arange(0, 4).contiguous().realize() + out = f(tt) + assert out.item() == 1+2+3+4 + + def test_fuzz_allreduce(self): + random.seed(41) + for it in range(2): + for n in range(2, 4+1): + shape = tuple([(n if i == 0 else 1) * random.randint(1, 10) for i in range(random.randint(1, 4))]) + t = Tensor.rand(shape).shard_(tuple([d0, d1, d2, d3][:n]), 0) + with Context(RING=0): + a = Tensor(UOp.allreduce(t.uop, Ops.ADD, t.device)) + with Context(RING=2): + b = Tensor(UOp.allreduce(t.uop, Ops.ADD, t.device)) + diff = a - b + mean_err = diff.reshape((prod(diff.shape),)).abs().mean().numpy() + max_err = diff.reshape((prod(diff.shape),)).abs().max().numpy() + assert mean_err < 1e-6, f"big mean error, iteration {it}_{n}" + assert max_err < 1e-6, f"big max error, iteration {it}_{n}" + + def _test_matmul_shard_axis(self, shard_x, shard_w, device): + X = Tensor.kaiming_uniform(N, N).realize() + W = Tensor.kaiming_uniform(N, N).realize() + Xs = X.shard(device, shard_x) + Ws = W.shard(device, shard_w) + O = (Xs@Ws) + np.testing.assert_allclose(X.numpy() @ W.numpy(), O.to(Device.DEFAULT).numpy(), atol=1e-5) + + def _test_double_matmul_shard_axis(self, shard_x, shard_w, device): + X = Tensor.kaiming_uniform(N, N).realize() + W1 = Tensor.kaiming_uniform(N, N).realize() + W2 = Tensor.kaiming_uniform(N, N).realize() + Xs = X.shard(device, shard_x) + W1s = W1.shard(device, shard_w) + W2s = W2.shard(device, shard_w) + O = (Xs@W1s)@W2s + np.testing.assert_allclose((X.numpy() @ W1.numpy()) @ W2.numpy(), O.to(Device.DEFAULT).numpy(), atol=1e-5) + + def test_matmul_shard_none(self): return self._test_matmul_shard_axis(None, None, devices_2) + def test_matmul_shard_X_0(self): return self._test_matmul_shard_axis(0, None, devices_2) + def test_matmul_shard_X_1(self): return self._test_matmul_shard_axis(1, None, devices_2) + def test_matmul_shard_W_0(self): return self._test_matmul_shard_axis(None, 0, devices_2) + def test_matmul_shard_W_1(self): return self._test_matmul_shard_axis(None, 1, devices_2) + + def test_matmul_shard_0_0(self): return self._test_matmul_shard_axis(0, 0, devices_2) + def test_matmul_shard_0_1(self): return self._test_matmul_shard_axis(0, 1, devices_2) + def test_matmul_shard_1_0(self): return self._test_matmul_shard_axis(1, 0, devices_2) + def test_matmul_shard_1_1(self): return self._test_matmul_shard_axis(1, 1, devices_2) + + def test_double_matmul_shard_X_0(self): return self._test_double_matmul_shard_axis(0, None, devices_2) + def test_double_matmul_shard_X_1(self): return self._test_double_matmul_shard_axis(1, None, devices_2) + def test_double_matmul_shard_W_0(self): return self._test_double_matmul_shard_axis(None, 0, devices_2) + def test_double_matmul_shard_W_1(self): return self._test_double_matmul_shard_axis(None, 1, devices_2) + + def test_conv_data_shard(self): + conv = nn.Conv2d(3, 16, 3, bias=False) + for p in get_parameters(conv): p.shard_(devices_2) + fake_image = Tensor.rand((2, 3, 32, 32)).shard(devices_2, axis=0) + out = conv(fake_image) + out.numpy() + + def test_conv_bias_data_shard(self): + conv = nn.Conv2d(3, 16, 3) + for p in get_parameters(conv): p.shard_(devices_2) + fake_image = Tensor.rand((2, 3, 32, 32)).shard(devices_2, axis=0) + out = conv(fake_image) + out.numpy() + + def test_backprop_conv(self): + with Tensor.train(): + conv = nn.Conv2d(3, 16, 3) + for p in get_parameters(conv): p.shard_(devices_2) + optim = nn.optim.Adam(get_parameters(conv)) + fake_image = Tensor.rand((2, 3, 32, 32)).shard(devices_2, axis=0) + out = conv(fake_image) + optim.zero_grad() + out.mean().backward() + #for p in get_parameters(conv): p.grad.realize() + optim.step() + out.numpy() + + def test_backprop_conv_wino(self): + with Context(WINO=1): self.test_backprop_conv() + + def test_backward_sum(self): + x = Tensor([[1.,2,3,4], [5,6,7,8]]).shard(devices_2, axis=0) + w = Tensor([1.,2,3,4], requires_grad=True).shard(devices_2) + out = x * w + out.mean().backward() + tst = w.grad.numpy() + np.testing.assert_allclose(tst, [0.75, 1., 1.25, 1.5]) + + def test_lr_scheduler_OneCycleLR(self): + from extra.lr_scheduler import OneCycleLR + conv = nn.Conv2d(3, 16, 3) + for p in get_parameters(conv): p.shard_(devices_2) + optim = nn.optim.SGD(get_parameters(conv)) + lr_sched = OneCycleLR(optim, max_lr=0.1, pct_start=0.1, div_factor=100, final_div_factor=0.1, total_steps=10) + lr_sched.step() + + def test_embedding(self): + B, T, embed_size, vocab_size = 4, 10, 20, 28 + + layer = nn.Embedding(vocab_size, embed_size) + x = Tensor(np.random.randint(0, vocab_size, (B, T), dtype=np.int32)) + z = layer(x) + + layer_sharded = nn.Embedding(vocab_size, embed_size) + layer_sharded.weight.replace(layer.weight.shard(devices_2, axis=1)).realize() + x_sharded = x.shard(devices_2, axis=None) + z_shard = layer_sharded(x_sharded) + + np.testing.assert_allclose(z.numpy(), z_shard.numpy(), atol=1e-6, rtol=1e-6) + + def test_rmsnorm(self): + B, T, embed_size = 4, 10, 20 + + norm = nn.RMSNorm(embed_size) + x = Tensor.rand((B, T, embed_size)).contiguous().realize() + y = norm(x) + + # for norm layers, the correct way to shard weights is duplication + norm_sharded = nn.RMSNorm(embed_size) + norm_sharded.weight.shard_(devices_2, axis=None).realize() + + # if x is being sharded, then all-reduce is involved + x_sharded = x.shard(devices_2, axis=2).realize() + y_shard = norm_sharded(x_sharded).realize() + np.testing.assert_allclose(y.numpy(), y_shard.numpy(), atol=1e-6, rtol=1e-6) + + # if x is being duplicated, then the operations remain inside each GPU + # which is the common case + x_sharded = x.shard(devices_2, axis=None).realize() + y_shard = norm_sharded(x_sharded).realize() + np.testing.assert_allclose(y.numpy(), y_shard.numpy(), atol=1e-6, rtol=1e-6) + + # NOTE: this is failing on LLVM CI, no idea why. Works locally. + @unittest.skipIf(CI and REAL_DEV in ("CUDA", "NV", "LLVM", "CPU"), "slow, and flaky on LLVM/CPU") + @unittest.skipIf(REAL_DEV == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") + def test_data_parallel_resnet(self): + from extra.models.resnet import ResNet18 + + fake_image = Tensor.rand((2, 3, 224//8, 224//8)) + fake_image_sharded = fake_image.shard(devices_2, axis=0) + m = ResNet18() + m.load_from_pretrained() + real_output = m(fake_image).log_softmax().numpy() + for p in get_parameters(m): p.shard_(devices_2).realize() + GlobalCounters.reset() + shard_output = m(fake_image_sharded).log_softmax().realize() + shard_output_np = shard_output.numpy() + np.testing.assert_allclose(real_output, shard_output_np, atol=1e-6, rtol=1e-6) + + def _test_model_train_step(self, m, fake_image, labels): + from tinygrad.nn.optim import LARS + optimizer = LARS(get_parameters(m), 0.1) # set requires_grad for all params + + optimizer.zero_grad() + m.load_from_pretrained() + output = m(fake_image).sparse_categorical_crossentropy(labels, label_smoothing=0.1) + output.backward() + grad = m.conv1.weight.grad.numpy() + + fake_image_sharded = fake_image.shard(devices_2, axis=0) + labels_sharded = labels.shard(devices_2, axis=0) + for p in get_parameters(m): p.shard_(devices_2).realize() + GlobalCounters.reset() + optimizer.zero_grad() + shard_output = m(fake_image_sharded).sparse_categorical_crossentropy(labels_sharded, label_smoothing=0.1) + shard_output.backward() + shard_grad = m.conv1.weight.grad.numpy() + # sometimes there is zeros in these grads... why? + np.testing.assert_allclose(grad, shard_grad, atol=1e-5, rtol=1e-5) + + @unittest.skipIf(CI and REAL_DEV in ("CUDA", "NV", "LLVM", "CPU"), "slow, and flaky on LLVM/CPU") + @unittest.skipIf(REAL_DEV == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") + def test_data_parallel_resnet_train_step(self): + from extra.models.resnet import ResNet18 + fake_image = Tensor.rand((2, 3, 224//8, 224//8)) + labels = Tensor.randint(2, low=0, high=1000) + m = ResNet18() + self._test_model_train_step(m, fake_image, labels) + + def test_data_parallel_simple_train_step(self): + class Model: + def __init__(self): self.conv1 = nn.Linear(128,128) + def __call__(self, x): return self.conv1(x) + def load_from_pretrained(self): pass + + fake_image = Tensor.rand((128,)) + labels = Tensor.randint(2, low=0, high=127) + m = Model() + self._test_model_train_step(m, fake_image, labels) + + def test_assign_kv_cache_multi(self): + bsz, max_context = 2, 8 + + class Attn: + @TinyJit + def __call__(self, xk:Tensor, start_pos:UOp): + seqlen = xk.shape[1] + if not hasattr(self, "cache_k"): + self.cache_k = Tensor.zeros(bsz, max_context, 1, 1).shard(devices_2).contiguous().realize() + keys = self.cache_k.shrink((None, (0, start_pos), None, None)).cat(xk, dim=1).contiguous() if start_pos > 0 else xk + self.cache_k.assign(keys.pad((None,(0,max_context-start_pos-seqlen),None,None)).contiguous()).realize() + + attn = Attn() + xk = Tensor.ones(bsz, 3, 1, 1).shard(devices_2).contiguous() + attn(xk, 0) + for i in range(3,6): + # copied from LLaMA + start_pos = Variable("start_pos", 1, max_context).bind(i) + xk = Tensor.ones(bsz, 1, 1, 1).shard(devices_2).contiguous() + attn(xk, start_pos) + + out = attn.cache_k.flatten().numpy() + np.testing.assert_allclose(out, [1.,1.,1.,1.,1.,1.,0.,0.,1.,1.,1.,1.,1.,1.,0.,0.]) + + def test_multi_tensor_jit_param(self): + @TinyJit + def jf(a, b) -> Tensor: + return (a + b).realize() + + for _ in range(5): + a = Tensor.ones(256).contiguous().realize() + b = Tensor.ones(256).contiguous().realize() + a.shard_(devices_2) + b.shard_(devices_2) + c = jf(a, b) + np.testing.assert_allclose(c.numpy(), a.numpy()+b.numpy(), atol=1e-4, rtol=1e-5) + assert len(jf.jit_cache) > 0 + + def test_multi_tensor_jit_body(self): + @TinyJit + def jf() -> Tensor: + a = Tensor.ones(256).contiguous().realize() + b = Tensor.ones(256).contiguous().realize() + a.shard_(devices_2) + b.shard_(devices_2) + return (a + b).realize() + + for _ in range(5): + r = jf() + np.testing.assert_allclose(r.numpy(), np.ones(256)+np.ones(256), atol=1e-4, rtol=1e-5) + assert len(jf.jit_cache) > 0 + + @unittest.skip("test broken") + def test_multi_device_jit_graph(self): + if Device[d0].graph is None or Device[d1].graph is None: raise unittest.SkipTest("only test graphs") + + @TinyJit + def jf(a: Tensor, b: Tensor, c: Tensor, d:Tensor): + # Create 80 entries on device 0: 2 batches. + for _ in range(40): + a = ((a + b).realize() + (a * b).realize()).realize() + # Create 80 entries on device 1: 2 batches. + for _ in range(40): + c = ((c + d).realize() + (c * d).realize()).realize() + # Create a copy from device 0 to 1: 1 entry. + a = a.to(d1).realize() + # Creates one last entry on device 1: 1 batch. + return (a + c).realize() + + a = Tensor.randn(10, 10, device=d0).realize() + b = Tensor.randn(10, 10, device=d0).realize() + c = Tensor.randn(10, 10, device=d1).realize() + d = Tensor.randn(10, 10, device=d1).realize() + + ref = jf(a, b, c, d).numpy() + for _ in range(5): + o = jf(a, b, c, d).numpy() + np.testing.assert_allclose(ref, o, atol=1e-4, rtol=1e-5) + + graph_d0 = Device[d0].graph.func if isinstance(Device[d0].graph, functools.partial) else Device[d0].graph + graph_d1 = Device[d1].graph.func if isinstance(Device[d1].graph, functools.partial) else Device[d1].graph + # Checking that 2 graphs per device, 1 copy and 1 last graph on device 1 are created. + assert isinstance(jf.jit_cache[0].prg, graph_d0) + assert isinstance(jf.jit_cache[1].prg, graph_d0) + assert isinstance(jf.jit_cache[2].prg, graph_d1) + assert isinstance(jf.jit_cache[3].prg, graph_d1) + assert isinstance(jf.jit_cache[4].prg, BufferCopy) + assert isinstance(jf.jit_cache[5].prg, graph_d1) + + @unittest.skip("no longer supports uneven shard") + def test_uneven_shard(self): + for N in range(1, 6): + X = Tensor.rand(4, 1, 257).contiguous().realize() + n = X.numpy() + devices = tuple(f"{Device.DEFAULT}:{i}" for i in range(N)) + X.shard_(devices, 2) + np.testing.assert_equal(X.numpy(), n) + np.testing.assert_equal(X.reshape(2, 2, 257).numpy(), n.reshape((2, 2, 257))) + np.testing.assert_equal(X.shrink(((0,2), (0, 1), (0,257))).numpy(), n[0:2, 0:1, 0:257]) + np.testing.assert_equal(X.expand((4, 4, 257)).numpy(), np.tile(n, (1, 4, 1))) + np.testing.assert_equal(X.permute((0, 2, 1)).numpy(), np.transpose(n, (0, 2, 1))) + + @unittest.skip("no longer supports uneven shard") + def test_uneven_multiple_zeros(self): + for data in ([1, 2, 3, 4], [1, 2, 3], [1, 2], [1], []): + for N in (1, 2, 3, 4): + devices = tuple(f"{Device.DEFAULT}:{i}" for i in range(N)) + # make sure something is computed on each device + X = ((Tensor(data).shard(devices, axis=0) + 1).realize() - 1).realize() + np.testing.assert_equal(X.numpy(), data) + + @unittest.skip("no longer supports uneven shard") + def test_uneven_shard_with_empty(self): + N = 4 + X = Tensor.rand(16, 1, 3).contiguous().realize() + np_x = X.numpy() + devices = tuple(f"{Device.DEFAULT}:{i}" for i in range(N)) + + # test empty shard + np.testing.assert_equal(X.shard(devices, 0).numpy(), np_x) + + # test reshape with empty shard + np.testing.assert_equal(X.shard(devices, 0).reshape(8, 1, 6).numpy(), np_x.reshape(8, 1, 6)) + + @unittest.skip("no longer supports uneven shard") + def test_multiple_uneven_shard(self): + N = 4 + X = Tensor.rand(4, 1, 257).contiguous().realize() + Y = Tensor.rand(4, 1, 257).contiguous().realize() + np_x, np_y = X.numpy(), Y.numpy() + devices = tuple(f"{Device.DEFAULT}:{i}" for i in range(N)) + X.shard_(devices, 2) + Y.shard_(devices, 2) + np.testing.assert_equal(X.numpy(), np_x) + np.testing.assert_equal(Y.numpy(), np_y) + np.testing.assert_equal((X + Y).numpy(), np_x + np_y) + + def test_bn_ast_on_devices(self): + t = Tensor.empty((16, 64, 112, 112)).shard(devices_4, axis=0) + bn = nn.BatchNorm2d(64) + for p in get_parameters(bn): p.shard_(devices_4).realize() + + out = bn(t) + scheds = [sched for sched in out.schedule() if sched.bufs[0].device in devices_4 and sched.ast.op is not Ops.COPY] + assert set(sched.bufs[0].device for sched in scheds) == set(devices_4), "should have ast on each shard device" + asts = [sched.ast for sched in scheds] + self.assertEqual(len(asts), 4) + # ast are the same on devices + self.assertEqual(len(set(asts)), 1) + + def test_reshape_on_axis(self): + t0 = Tensor.rand((26, 15, 7)).shard(devices_3, axis=1) + + # test split and rejoin to the right + t1 = t0.reshape((26, 3, 5, 7)) + t2 = t0.reshape((26, 3, 35)) + t3 = t1.reshape((26, 15, 7)) + t4 = t2.reshape((26, 105,)) + + for t in [t0, t1, t2, t3, t4]: + assert t.uop.axis == 1 + np.testing.assert_allclose(t.numpy().flatten(), t0.numpy().flatten()) + + # test shape-one axis + t5 = t4.reshape((26, 1, 105)) + assert t5.uop.axis == 2 + np.testing.assert_allclose(t.numpy().flatten(), t5.numpy().flatten()) + + # test split and rejoin to the right and reshape to the left + t5 = t0.reshape((2, 13, 3, 5, 7)) + t6 = t0.reshape((13, 2, 3, 7, 5)) + t7 = t0.reshape((1, 13, 2, 3, 1, 7, 5)) + assert t5.uop.axis == 2 + assert t6.uop.axis == 2 + assert t7.uop.axis == 3 + np.testing.assert_allclose(t5.numpy().flatten(), t0.numpy().flatten()) + np.testing.assert_allclose(t6.numpy().flatten(), t0.numpy().flatten()) + np.testing.assert_allclose(t7.numpy().flatten(), t0.numpy().flatten()) + + # test no left join + with self.assertRaises((AssertionError, ValueError)): + t0.reshape((26*15,7)).schedule() + + @unittest.skip("no longer supports uneven shard") + def test_reshape_on_axis_uneven(self): + def reshape_helper(t0, t, t_axis): + assert t.uop.axis == t_axis + np.testing.assert_allclose(t0.reshape(t.shape).numpy(), t.numpy()) + + t0 = Tensor.rand((4, 42, 15)).shard(devices_3, axis=1, splits=[14, 7, 21]) + + # ok to reshape as long as elements remain on same device + reshape_helper(t0, t0.reshape(2, 2, 42, 3, 5), 2) + # split to the right + reshape_helper(t0, t0.reshape(2, 2, 6, 7, 15), 2) + # split off and merge to the right + reshape_helper(t0, t0.reshape(4, 6, 105), 1) + # really blend the axes together + reshape_helper(t0, t0.reshape(4, 30, 21), 1) + # split off 1-shape + reshape_helper(t0, t0.reshape(4, 1, 42, 15), 2) + reshape_helper(t0, t0.reshape(4, 6, 1, 7, 15), 1) + + # assert if cannot maintain shard axis without moving items between devices + with self.assertRaises(AssertionError): t0.reshape(4, 7, 6, 15) + # assert for degenerate reshape + with self.assertRaises(AssertionError): t0.reshape(4, 5, 7, 15) + # assert for cannot maintain axis + with self.assertRaises(AssertionError): t0.reshape(4, 3, 2, 7, 15) + + # it doesn't work like this anymore + # NOTE: this never failed in assign_multi, it failed tensor spec because MULTI was never pushed in the graph + @unittest.expectedFailure + def test_mlb_assign_change_axis(self): + t_none = Tensor.zeros((16, 16)).shard(devices_2).contiguous().realize() + t_zero = Tensor.ones((16, 16)).shard(devices_2, axis=0) + with self.assertRaises(RuntimeError): + # don't allow assigns that change axes + t_none.assign(t_zero) + t_none.schedule() + + def test_init_rand_with_multiple_devices_fail(self): + # init rand with multi device is not allowed + with self.assertRaises(ValueError): + Tensor.rand(256, device=devices_2) + + def test_rand_on_multiple_devices(self): + # different devices generate different rand + d0_rand = Tensor.rand(256, device=d0).realize() + d1_rand = Tensor.rand(256, device=d1).realize() + assert not np.allclose(d0_rand.numpy(), d1_rand.numpy()) + + def test_rand_on_multiple_devices_manual_seed(self): + Tensor.manual_seed(123) + d0_rand = Tensor.rand(2, device=d0).tolist() + d1_rand = Tensor.rand(2, device=d1).tolist() + + # manual_seed again gives the same values + Tensor.manual_seed(123) + d0_rand2 = Tensor.rand(2, device=d0).tolist() + d1_rand2 = Tensor.rand(2, device=d1).tolist() + self.assertEqual(d0_rand, d0_rand2) + self.assertEqual(d1_rand, d1_rand2) + + # device seed is only determined by init order, so flipping init order flips rands + Tensor.manual_seed(123) + d1_rand_flip = Tensor.rand(2, device=d1).tolist() + d0_rand_flip = Tensor.rand(2, device=d0).tolist() + self.assertEqual(d0_rand, d1_rand_flip) + self.assertEqual(d1_rand, d0_rand_flip) + + def test_rand_like_on_shard(self, axis=None): + t = Tensor.empty((16, 16)).shard(devices_2, axis=axis) + t2 = Tensor.rand_like(t) + self.assertEqual(t.shape, t2.shape) + self.assertEqual(t.device, t2.device) + self.assertEqual(t.dtype, t2.dtype) + self.assertEqual(t.uop.axis, t2.uop.axis) + t2.realize() + def test_rand_like_on_shard_axis(self): self.test_rand_like_on_shard(0) + + def test_rand_like_from_alu(self): + a = Tensor.ones(4, 4).shard(devices_4, axis=0) + aa = a + a + self.assertEqual(aa.device, devices_4) + self.assertEqual(aa.uop.axis, 0) + raa = aa.rand_like() + self.assertEqual(raa.device, devices_4) + self.assertEqual(raa.uop.axis, 0) + + b = Tensor.empty(4, 4).shard(devices_4, axis=None) + ab = a + b + self.assertEqual(ab.device, devices_4) + self.assertEqual(ab.uop.axis, 0) + rab = ab.rand_like() + self.assertEqual(rab.device, devices_4) + self.assertEqual(rab.uop.axis, 0) + + @unittest.skip("no longer supports uneven shard") + def test_rand_like_uneven_shard(self): + t = Tensor.empty((4, 42, 15)).shard(devices_3, axis=1) + t2 = Tensor.rand_like(t) + self.assertEqual(t.shape, t2.shape) + self.assertEqual(t.device, t2.device) + self.assertEqual(t.dtype, t2.dtype) + self.assertEqual(t.uop.axis, t2.uop.axis) + assert all(tlb.shape == t2lb.shape for tlb, t2lb in zip(t.uop.src, t2.uop.src)) + + def test_rand_like_none_shard(self): + t = Tensor.empty((16, 16)).shard(devices_2) + t2 = Tensor.rand_like(t) + self.assertEqual(t.shape, t2.shape) + self.assertEqual(t.device, t2.device) + self.assertEqual(t.dtype, t2.dtype) + self.assertEqual(t.uop.axis, t2.uop.axis) + + def test_rand_like_arg_dtype(self): + t = Tensor.empty((16, 16), dtype=dtypes.int32).shard(devices_2, axis=1) + t2 = Tensor.rand_like(t, dtype=dtypes.float32) + self.assertEqual(t.dtype, dtypes.int32) + self.assertEqual(t2.dtype, dtypes.float32) + + def test_rand_like_arg_device(self): + # axis=None + t = Tensor.empty((16, 16)).shard((d1, d2), axis=None) + with self.assertRaises(RuntimeError): + Tensor.rand_like(t, device=(d3, d4)) + + # axis=1 + t = Tensor.empty((16, 16)).shard((d1, d2), axis=1) + with self.assertRaises(RuntimeError): + Tensor.rand_like(t, device=(d3, d4)) + + def test_dropout_on_shard(self): + with Tensor.train(): + X = Tensor.ones(256).to(devices_2) + output = X.dropout(0.5).numpy() + unique, counts = np.unique(output, return_counts=True) + assert set(unique) == {0, 2}, unique + assert 100 < counts[0] < 156, counts[0] + + def test_dropout_on_shard_axis(self): + with Tensor.train(): + X = Tensor.ones(512).shard(devices_2, axis=0) + output = X.dropout(0.5).numpy() + unique, counts = np.unique(output, return_counts=True) + assert set(unique) == {0, 2}, unique + assert 200 < counts[0] < 312, counts[0] + + @unittest.skip("no longer supports uneven shard") + def test_dropout_on_uneven_shard_axis(self): + with Tensor.train(): + X = Tensor.ones(256).shard(devices_3, axis=0) + output = X.dropout(0.5).numpy() + unique, counts = np.unique(output, return_counts=True) + assert set(unique) == {0, 2}, unique + assert 100 < counts[0] < 156, counts[0] + + @unittest.skip("TODO: this requires forced_realize to be deleted.") + def test_shard_memory(self): + devices = (d0, d1, d2, d3) + t = Tensor.zeros(16, 16).contiguous() + t.shard_(devices, axis=0).realize() + assert all([lb is lb.base and lb.realized.base.size == 4 * 16 for lb in t.uop.src]) + + @unittest.skip("this is unreliable on OSX") + def test_clone(self): + t = Tensor.rand(16, 16).shard(devices_2, axis=None) + np.testing.assert_allclose(t.numpy(), t.clone().numpy()) + + t = Tensor.rand(16, 16).shard(devices_2, axis=0) + np.testing.assert_allclose(t.numpy(), t.clone().numpy()) + + def test_multi_const_folding(self): + with Context(TRACK_MATCH_STATS=0): + a = Tensor.arange(3).realize() + zeros = Tensor.zeros(3).realize() + b = a.to(devices_2)*zeros.to(devices_2) + sched = b.schedule() + self.assertEqual(len(sched), 0) + self.assertListEqual(b.tolist(), [0, 0, 0]) + +@unittest.skipIf(not_support_multi_device(), "no multi") +class TestHandleData(unittest.TestCase): + def test_copied_to_device(self): + device = (d0, d1, d2, d3) + t = Tensor([1, 2, 3, 4]).shard(device).realize() + not_covered = t.to(d5) + sched = not_covered.schedule() + assert len(sched) == 1 + # setup again because create_schedule has side effect + t = Tensor([1, 2, 3, 4]).shard(device).realize() + not_covered = t.to(d5) + assert not_covered.realize().tolist() == [1, 2, 3, 4] + + for d in device: + t = Tensor([1, 2, 3, 4]).shard(device).realize() + covered = t.to(d) + sched = covered.schedule() + # TODO: this isn't optimized out anymore + #assert len(sched) == 0 + # setup again because create_schedule has side effect + t = Tensor([1, 2, 3, 4]).shard(device).realize() + covered = t.to(d) + assert covered.realize().tolist() == [1, 2, 3, 4] + +@unittest.skipIf(not_support_multi_device(), "no multi") +class TestShrinkMultiTensorShardedAxis(unittest.TestCase): + # shrink a multitensor on sharded axis + def test_shrink_bad_args(self): + t = Tensor.arange(64).reshape(8, 8).contiguous().realize() + t.shard_([f"{Device.DEFAULT}:{i}" for i in range(4)], axis=0) + + with self.assertRaises(AssertionError): + # sharded axis shrink on non-device boundry is not allowed + a = t.shrink(((0, 3), (0, 8))) + a.schedule() + with self.assertRaises(AssertionError): + # cannot shrink sharded and non-sharded axis at the same time + a = t.shrink(((0, 2), (2, 4))) + a.schedule() + + a = t.shrink(((0, 2), (0, 8))) + a.schedule() + assert a.shape == (2, 8) + + p = a.pad(((0, 6), (0, 0))) + p.schedule() + assert p.shape == (8, 8) + + @given(strat.sampled_from([dtypes.float, dtypes.int, dtypes.int64, dtypes.int16])) + def test_ops(self, dtype): + if not is_dtype_supported(dtype): return + t = Tensor.arange(64).reshape(8, 8).contiguous().realize() + t.shard_([f"{Device.DEFAULT}:{i}" for i in range(4)], axis=0) + for i in range(4): + print(f"{i=}") + a = t.shrink(((0+2*i,2+2*i),None)) + b = Tensor(t.numpy()[0+2*i:2+2*i]) + assert a.shape == b.shape == (2, 8) + np.testing.assert_allclose(a.numpy(), b.numpy()) + # cast + np.testing.assert_allclose(a.float().numpy(), b.float().numpy()) + + # elementwise + np.testing.assert_allclose(a.exp().numpy(), b.exp().numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.reciprocal().numpy(), b.reciprocal().numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.pow(-0.5).numpy(), b.pow(-0.5).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose((a+a).numpy(), (b+b).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_equal((a+1).numpy(), (b+1).numpy()) + np.testing.assert_equal((1+a).numpy(), (1+b).numpy()) + np.testing.assert_allclose((a.where(a+a, a)).numpy(), (b.where(b+b, b)).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose((a.where(1, 0)).numpy(), (b.where(1, 0)).numpy(), rtol=1e-7, atol=1e-3) + + # reduce + np.testing.assert_allclose(a.max().numpy(), b.max().numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.sum().numpy(), b.sum().numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.mean().numpy(), b.mean().numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.max(0).numpy(), b.max(0).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.sum(0).numpy(), b.sum(0).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.mean(0).numpy(), b.mean(0).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.max(1).numpy(), b.max(1).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.sum(1).numpy(), b.sum(1).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.mean(1).numpy(), b.mean(1).numpy(), rtol=1e-7, atol=1e-3) + + # pad it back + np.testing.assert_allclose(a.pad(((2*i, 2*(4-i-1)), None)).numpy(), b.pad(((2*i, 2*(4-i-1)), None)).numpy(), rtol=1e-7, atol=1e-3) + + # other movement + np.testing.assert_allclose(a.pad((None, (1, 1))).numpy(), b.pad((None, (1, 1))).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.shrink((None, (1, 3))).numpy(), b.shrink((None, (1, 3))).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.permute((1, 0)).numpy(), b.permute((1, 0)).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.reshape((2, 2, 4)).numpy(), b.reshape((2, 2, 4)).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.reshape((2, 1, 8)).expand((2, 5, 8)).numpy(), b.reshape((2, 1, 8)).expand((2, 5, 8)).numpy(), rtol=1e-7, atol=1e-3) + np.testing.assert_allclose(a.flip(-1).numpy(), b.flip(-1).numpy(), rtol=1e-7, atol=1e-3) + + @unittest.skip("no longer supports uneven shard") + def test_uneven(self): + t = Tensor.arange(24).reshape(3, 8).contiguous().realize() + t.shard_([f"{Device.DEFAULT}:{i}" for i in range(2)], axis=0) + + a = t.shrink(((0, 2), None)) + b = t.shrink(((2, 3), None)) + na = t.numpy()[0:2] + nb = t.numpy()[2:3] + np.testing.assert_equal(a.numpy(), na) + np.testing.assert_equal(b.numpy(), nb) + np.testing.assert_equal((a+1).numpy(), na+1) + np.testing.assert_equal((b+1).numpy(), nb+1) + np.testing.assert_equal((1+a).numpy(), 1+na) + np.testing.assert_equal((1+b).numpy(), 1+nb) + np.testing.assert_equal((a+a).numpy(), na+na) + np.testing.assert_equal((b+b).numpy(), nb+nb) + + # @unittest.skip("why didn't this work?") + def test_add_two_partitions(self): + t = Tensor.arange(64).reshape(8, 8).contiguous().realize() + t.shard_([f"{Device.DEFAULT}:{i}" for i in range(4)], axis=0) + + a = t.shrink(((2, 4), None)) + b = t.shrink(((6, 8), None)) + na = t.numpy()[2:4] + nb = t.numpy()[6:8] + np.testing.assert_equal(a.numpy(), na) + np.testing.assert_equal(b.numpy(), nb) + np.testing.assert_equal((a+b).numpy(), na+nb) + c = a.pad(((2, 4), None)) + b.pad(((6, 0), None)) + c.realize() + expected = np.concatenate([np.zeros_like(t.numpy()[0:2]), na, np.zeros_like(t.numpy()[4:6]), nb]) + np.testing.assert_equal(c.numpy(), expected) + + def test_add_different_tensors(self): + devices = [f"{Device.DEFAULT}:{i}" for i in range(4)] + x = Tensor.arange(64).reshape(8, 8).contiguous().realize().shard(devices, axis=0) + + to_add = [] + for i in range(len(devices)): + to_add.append((Tensor.ones(2, 8) * i).shard(devices)) + + added:list[Tensor] = [] + for bound, a in zip(x.uop.bounds, to_add): + added.append(x[bound[0]:bound[1]] + a) + + output = added[0].cat(*added[1:]) + expected = np.arange(64).reshape((8,8)) + np.array([[0,0,1,1,2,2,3,3] for _ in range(8)]).T + np.testing.assert_allclose(output.numpy(), expected) + +@unittest.skipIf(not_support_multi_device(), "no multi") +@unittest.skipIf(REAL_DEV == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") +class TestBatchNorm(unittest.TestCase): + def test_unsynced_backprop_conv_bn(self): + with Tensor.train(): + from extra.lr_scheduler import OneCycleLR + + convs = [nn.Conv2d(3, 16, 3), nn.Conv2d(3, 16, 3)] + bns = [nn.BatchNorm2d(16), nn.BatchNorm2d(16)] + + for p in get_parameters(convs + bns): + p.shard_((d1, d2)) + optim = nn.optim.Adam(get_parameters(convs + bns)) + lr_sched = OneCycleLR(optim, max_lr=0.1, pct_start=0.1, div_factor=100, final_div_factor=0.1, total_steps=10) + lr_sched.step() + + fake_image = Tensor.rand((8, 3, 32, 32)).shard((d1, d2), axis=0) + + f1 = fake_image.shrink(((0, 4), None, None, None)) + f2 = fake_image.shrink(((4, 8), None, None, None)) + + out1 = bns[0](convs[0](f1)) + out2 = bns[1](convs[1](f2)) + out = out1.cat(out2) + optim.zero_grad() + out.mean().backward() + optim.step() + out.numpy() + + @unittest.skipIf(REAL_DEV == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") + def test_unsynced_backprop_standalone_bn(self): + from extra.lr_scheduler import OneCycleLR + GPUS = (d1, d2) + + class BatchNorm: + def __init__(self, num_features): + self.bns:list[nn.BatchNorm2d] = [] + for _ in GPUS: + bn = nn.BatchNorm2d(num_features, track_running_stats=False, eps=1e-12, momentum=0.85, affine=True) + self.bns.append(bn) + + def __call__(self, x:Tensor): + bn_ts = [] + each = x.shape[0]//len(self.bns) + for i, bn in enumerate(self.bns): + xi = x.shrink(((each*(i), each*(i+1)), None, None, None)) + bni = bn(xi) + bn_ts.append(bni) + return bn_ts[0].cat(*bn_ts[1:]) + + with Tensor.train(): + conv = nn.Conv2d(3, 16, 3) + bn = BatchNorm(16) + + for p in get_parameters([conv, bn]): + p.shard_(GPUS) + optim = nn.optim.Adam(get_parameters([conv, bn])) + lr_sched = OneCycleLR(optim, max_lr=0.1, pct_start=0.1, div_factor=100, final_div_factor=0.1, total_steps=10) + lr_sched.step() + + fake_image = Tensor.rand((8, 3, 32, 32)).shard(GPUS, axis=0) + + out = bn(conv(fake_image)) + optim.zero_grad() + out.mean().backward() + optim.step() + + def test_unsynced_backprop_sync_weights(self): + from extra.lr_scheduler import OneCycleLR + from examples.hlb_cifar10 import UnsyncedBatchNorm + GPUS = (d1, d2) + + with Tensor.train(): + conv = nn.Conv2d(3, 16, 3) + bn = UnsyncedBatchNorm(16, num_devices=len(GPUS)) + + for k, p in get_state_dict([conv, bn]).items(): + if 'running_mean' in k or 'running_var' in k: + p.shard_(GPUS, axis=0) + else: + p.to_(GPUS) + optim = nn.optim.Adam(get_parameters([conv, bn])) + lr_sched = OneCycleLR(optim, max_lr=0.1, pct_start=0.1, div_factor=100, final_div_factor=0.1, total_steps=10) + lr_sched.step() + + fake_image = Tensor.rand((8, 3, 32, 32)).shard(GPUS, axis=0) + + out = bn(conv(fake_image)) + optim.zero_grad() + out.mean().backward() + optim.step() + + @given(strat.sampled_from((False, True))) + def test_batchnorm(self, is_training): + devices = [f"{Device.DEFAULT}:{i}" for i in range(4)] + x = Tensor.arange(4096).reshape(8, 8, 8, 8).contiguous().realize().shard(devices, axis=0) + + with Tensor.train(is_training): + bns = [] + for _ in range(len(devices)): + bn = nn.BatchNorm2d(8) + for p in get_parameters(bn): + p.shard_(devices) + bn.weight.requires_grad = True + bn.bias.requires_grad = True + bns.append(bn) + + bn_ts = [] + for bound, bn in zip(x.uop.bounds, bns): + bni = bn(x[bound[0]:bound[1]]) + bn_ts.append(bni) + + bn_ts[0].cat(*bn_ts[1:]).numpy() + + def test_synced_vs_unsynced_bn(self): + from examples.hlb_cifar10 import UnsyncedBatchNorm + from tinygrad.nn import BatchNorm2d + devices = [f"{Device.DEFAULT}:{i}" for i in range(4)] + x = Tensor.ones(8, 8, 8, 8).contiguous().realize().shard(devices, axis=0) + + with Tensor.train(): + synced_bn = BatchNorm2d(8) + unsynced_bn = UnsyncedBatchNorm(8, num_devices=len(devices)) + + for p in get_parameters(synced_bn): + p.shard_(devices) + for k, p in get_state_dict(unsynced_bn).items(): + if 'running_mean' in k or 'running_var' in k: + p.shard_(devices, axis=0) + else: + p.to_(devices) + + synced_out = synced_bn(x) + synced_si = list(synced_out.schedule()) + unsynced_out = unsynced_bn(x) + unsynced_si = list(unsynced_out.schedule()) + + # TODO: test synced / unsynced batchnorm cross device kernel and copies + assert synced_si + assert unsynced_si + +def helper_test_shard_op(shps, fxn, atol=1e-6, rtol=1e-3): + for shp in shps: + single_in = Tensor.randn(shp) + multi_in = single_in.shard(devices_2, axis=0) + + single_out = fxn(single_in).numpy() + multi_out = fxn(multi_in).numpy() + + try: + assert single_out.shape == multi_out.shape, f"shape mismatch: single={single_out.shape} | multi={multi_out.shape}" + assert single_out.dtype == multi_out.dtype, f"dtype mismatch: single={single_out.dtype} | multi={multi_out.dtype}" + np.testing.assert_allclose(single_out, multi_out, atol=atol, rtol=rtol) + except Exception as e: + raise Exception(f"Failed shape {single_out.shape}: {e}") + +@unittest.skipIf(not_support_multi_device(), "no multi") +class TestTensorOps(unittest.TestCase): + def test_interpolate(self): + helper_test_shard_op([(4,16,16),(4,24,24)], lambda x: Tensor.interpolate(x, (19,19))) + + def test_bitcast(self): + helper_test_shard_op([(256,), (256,)], lambda x: x.bitcast(dtypes.int)) + +@unittest.skipIf(not_support_multi_device(), "no multi") +class TestMultiRamUsage(unittest.TestCase): + def setUp(self): + self.baseline = GlobalCounters.mem_used + self.N = 100 + def assertUsed(self, amt, strict=True): + used = GlobalCounters.mem_used - self.baseline + print(f"used {used} bytes") + if strict: self.assertEqual(used, amt) + else: self.assertLessEqual(used, amt) + + def test_zeros(self): + _ = Tensor.zeros(self.N, self.N).contiguous().realize() + self.assertUsed(self.N*self.N*4) + + def test_zeros_del(self): + _ = Tensor.zeros(self.N, self.N).contiguous().realize() + del _ + self.assertUsed(0) + + def test_zeros_copy(self): + _ = Tensor.zeros(self.N, self.N).contiguous().to(devices_2).realize() + # NOTE: the first one on the DEFAULT device should be freed + self.assertUsed(self.N*self.N*4*2) + + def test_zeros_shard(self, devices=(d1, d2)): + _ = Tensor.zeros(self.N, self.N).contiguous().shard(devices, axis=0).realize() + self.assertUsed(self.N*self.N*4) # sharding should not increase total ram usage + def test_zeros_shard_self(self): self.test_zeros_shard((d0, d1)) + + def test_zeros_contiguous_shard(self): + _ = Tensor.zeros(self.N, self.N).contiguous().shard(devices_2, axis=0).contiguous().realize() + self.assertUsed(self.N*self.N*4) # sharding should not increase total ram usage + +@unittest.skipIf(not_support_multi_device(), "need multi") +class TestMultiFromUnrenderable(unittest.TestCase): + def test_from_npy(self): + t = Tensor(np.arange(100, dtype=np.uint32)) + ll = t.shard((d0, d1), axis=0) + 1 + np.testing.assert_equal(ll.numpy(), np.arange(100)+1) + +@unittest.skipIf(not_support_multi_device(), "need multi") +class TestMultiAssign(unittest.TestCase): + device = tuple(f"{Device.DEFAULT}:{i}" for i in range(2)) + + def test_multi_assign_realized(self): + out = Tensor.zeros(4).shard(self.device, 0).contiguous().realize() + ones = Tensor.ones(4).shard(self.device, 0).contiguous().realize() + out.assign(ones).realize() + self.assertListEqual(out.tolist(), [1,1,1,1]) + + def test_multi_assign_unrealized(self): + out = Tensor.zeros(4).contiguous().realize().shard(self.device, 0) + ones = Tensor.ones(4).shard(self.device, 0).contiguous().realize() + out.assign(ones).realize() + self.assertListEqual(out.tolist(), [1,1,1,1]) + + def test_multi_assign_both_unrealized(self): + out = Tensor.zeros(4).contiguous().realize().shard(self.device, 0) + ones = Tensor.ones(4).contiguous().realize().shard(self.device, 0) + out.assign(ones).realize() + self.assertListEqual(out.tolist(), [1,1,1,1]) + + def test_multi_assign_piece(self): + out = Tensor.zeros(4,4).shard(self.device, 0).contiguous().realize() + ones = Tensor.ones(4,1).shard(self.device, 0).contiguous().realize() + out[:, 2:3].assign(ones).realize() + self.assertListEqual(out.tolist(), [[0,0,1,0], [0,0,1,0], [0,0,1,0], [0,0,1,0]]) + + def test_multi_assign_piece_noncontig(self): + out = Tensor.zeros(4,4).contiguous().realize().shard(self.device, 0).realize() + ones = Tensor.ones(4,1).shard(self.device, 0).contiguous().realize() + out[:, 2:3].assign(ones).realize() + self.assertListEqual(out.tolist(), [[0,0,1,0], [0,0,1,0], [0,0,1,0], [0,0,1,0]]) + + @unittest.expectedFailure + def test_multi_assign_piece_unrealized(self): + out = Tensor.zeros(4,4).contiguous().realize().shard(self.device, 0) + ones = Tensor.ones(4,1).shard(self.device, 0).contiguous().realize() + out[:, 2:3].assign(ones).realize() + self.assertListEqual(out.tolist(), [[0,0,1,0], [0,0,1,0], [0,0,1,0], [0,0,1,0]]) + + def test_multi_assign_var_offset(self): + out = Tensor.zeros(4,4).contiguous().realize().shard(self.device, 0).realize() + ones = Tensor.ones(4,1).shard(self.device, 0).contiguous().realize() + vi = Variable("i", 0, 3).bind(2) + out[:, vi:vi+1].assign(ones).realize() + self.assertListEqual(out.tolist(), [[0,0,1,0], [0,0,1,0], [0,0,1,0], [0,0,1,0]]) + + def test_multi_assign_var_offset_jit_none(self): self.test_multi_assign_var_offset_jit(None) + def test_multi_assign_var_offset_jit(self, shard_axis=0): + out = Tensor.zeros(4,6).contiguous().realize().shard(self.device, shard_axis).realize() + ones = Tensor.ones(4,1).shard(self.device, shard_axis).contiguous().realize() + + @TinyJit + def f(out:Tensor, vi): + out[:, vi:vi+1].assign(ones).realize() + ones.assign(ones+1).realize() + + vi = Variable("i", 0, 5) + for i in range(1,5): + GlobalCounters.reset() + f(out, vi.bind(i)) + self.assertListEqual(out.tolist(), [[0,1,2,3,4,0]]*4) + +@unittest.skipIf(not_support_multi_device(), "need multi") +class TestMultiTransformer(unittest.TestCase): + def test_transformer(self): + device = tuple(f"{Device.DEFAULT}:{i}" for i in range(2)) + + from extra.models.llama import Transformer + args = {"dim": 32, "n_heads": 1, "n_kv_heads": 1, "n_layers": 2, "norm_eps": 1e-5, "rope_theta": 500000, "vocab_size": 1024, + "hidden_dim": 32, "max_context": 12} + real_model = Transformer(**args) + shard_model = Transformer(**args) + + # copy state + nn.state.load_state_dict(shard_model, nn.state.get_state_dict(real_model)) + + # shard + for k,v in nn.state.get_state_dict(shard_model).items(): + if 'scale' in k: v.shard_(device, axis=None) # from quantized + elif '.attention.' in k: v.shard_(device, axis=-1) + elif '.feed_forward.w1.' in k: v.shard_(device, axis=0) + elif '.feed_forward.w3.' in k: v.shard_(device, axis=0) + elif '.feed_forward.' in k: v.shard_(device, axis=-1) + elif 'tok_embeddings.weight' in k: v.shard_(device, axis=0) + elif 'output.weight' in k: v.shard_(device, axis=0) + else: v.shard_(device, axis=None) + + last_tok = 0 + for i in range(10): + real_tok = real_model(Tensor([[last_tok]], device=Device.DEFAULT), i).item() + shard_tok = shard_model(Tensor([[last_tok]], device=device), i).item() + + # test kv cache + kv1 = real_model.layers[0].attention.cache_kv.numpy() + kv2 = shard_model.layers[0].attention.cache_kv.numpy() + #print(np.concatenate([kv1[:, :, :, :, 0:1], kv2[:, :, :, :, 0:1]], axis=4)) + np.testing.assert_allclose(kv1, kv2, atol=1e-5, rtol=1e-5, err_msg=f"issue at token {i}") + + # test token + self.assertEqual(real_tok, shard_tok, f"issue at token {i}") + last_tok = real_tok + + @unittest.skip("super slow") + def test_llama1b_full(self): + from tinygrad.helpers import fetch + fetch("https://huggingface.co/bofenghuang/Meta-Llama-3-8B/resolve/main/original/tokenizer.model", "tokenizer.model", subdir="llama3-1b-instruct") + model = fetch("https://huggingface.co/bartowski/Llama-3.2-1B-Instruct-GGUF/resolve/main/Llama-3.2-1B-Instruct-Q6_K.gguf", + "Llama-3.2-1B-Instruct-Q6_K.gguf", subdir="llama3-1b-instruct") + + device = tuple(f"{Device.DEFAULT}:{i}" for i in range(2)) + from examples.llama3 import build_transformer + real_model = build_transformer(model, model_size="1B", device=Device.DEFAULT) + shard_model = build_transformer(model, model_size="1B", device=device) + + last_tok = 0 + real_tok = real_model(Tensor([[last_tok]], device=Device.DEFAULT), 0) + shard_tok = shard_model(Tensor([[last_tok]], device=device), 0) + self.assertEqual(real_tok.item(), shard_tok.item()) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_net_speed.py b/tinygrad_repo/test/test_net_speed.py new file mode 100644 index 000000000..9344ebe72 --- /dev/null +++ b/tinygrad_repo/test/test_net_speed.py @@ -0,0 +1,87 @@ +#!/usr/bin/env python +import time +import unittest +import torch +from tinygrad import Tensor, Device +from tinygrad.helpers import Profiling, CI + +@unittest.skipIf(CI and Device.DEFAULT in {"CUDA", "NV"}, "slow") +class TestConvSpeed(unittest.TestCase): + + def test_mnist(self): + # https://keras.io/examples/vision/mnist_convnet/ + conv = 3 + inter_chan, out_chan = 32, 64 + + # ****** torch baseline ******* + + torch.backends.mkldnn.enabled = False + + conv = 3 + inter_chan, out_chan = 32, 64 + c1 = torch.randn(inter_chan,1,conv,conv, requires_grad=True) + c2 = torch.randn(out_chan,inter_chan,conv,conv, requires_grad=True) + l1 = torch.randn(out_chan*5*5, 10, requires_grad=True) + + c2d = torch.nn.functional.conv2d + mp = torch.nn.MaxPool2d((2,2)) + lsm = torch.nn.LogSoftmax(dim=1) + + cnt = 5 + fpt, bpt = 0.0, 0.0 + for i in range(cnt): + et0 = time.time() + x = torch.randn(128, 1, 28, 28, requires_grad=True) + x = mp(c2d(x,c1).relu()) + x = mp(c2d(x,c2).relu()) + x = x.reshape(x.shape[0], -1) + out = lsm(x.matmul(l1)) + out = out.mean() + et1 = time.time() + out.backward() + et2 = time.time() + fpt += (et1-et0) + bpt += (et2-et1) + + fpt_baseline = (fpt*1000/cnt) + bpt_baseline = (bpt*1000/cnt) + print("torch forward pass: %.3f ms" % fpt_baseline) + print("torch backward pass: %.3f ms" % bpt_baseline) + + # ****** tinygrad compare ******* + + c1 = Tensor(c1.detach().numpy(), requires_grad=True) + c2 = Tensor(c2.detach().numpy(), requires_grad=True) + l1 = Tensor(l1.detach().numpy(), requires_grad=True) + + cnt = 5 + fpt, bpt = 0.0, 0.0 + for i in range(1+cnt): + et0 = time.time() + x = Tensor.randn(128, 1, 28, 28) + x = x.conv2d(c1).relu().avg_pool2d() + x = x.conv2d(c2).relu().max_pool2d() + x = x.reshape(shape=(x.shape[0], -1)) + out = x.dot(l1).log_softmax() + out = out.mean() + out.backward() # NOTE: we have to now compute this here, but it doesn't realize + out.realize() + et1 = time.time() + [x.grad.realize() for x in [c1, c2, l1]] + et2 = time.time() + if i == 0: + pr = Profiling(sort='time', frac=0.2) + pr.__enter__() + else: + fpt += (et1-et0) + bpt += (et2-et1) + + pr.__exit__() + fpt = (fpt*1000/cnt) + bpt = (bpt*1000/cnt) + print("forward pass: %.3f ms, %.2fx off baseline %.3f ms" % (fpt, fpt/fpt_baseline, fpt_baseline)) + print("backward pass: %.3f ms, %.2fx off baseline %.3f ms" % (bpt, bpt/bpt_baseline, bpt_baseline)) + + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_nn.py b/tinygrad_repo/test/test_nn.py new file mode 100755 index 000000000..000e45916 --- /dev/null +++ b/tinygrad_repo/test/test_nn.py @@ -0,0 +1,709 @@ +#!/usr/bin/env python +import unittest +import numpy as np +import torch +from tinygrad import Tensor, Device, TinyJit +from tinygrad.uop.ops import Ops +from tinygrad.helpers import GlobalCounters, CI, Context, OSX +from tinygrad.nn import Conv1d, ConvTranspose1d, Conv2d, ConvTranspose2d, Linear, Embedding +from tinygrad.nn import BatchNorm, LayerNorm, LayerNorm2d, GroupNorm, InstanceNorm, RMSNorm, LSTMCell +from tinygrad.nn.state import load_state_dict +from tinygrad.engine.realize import run_schedule +from test.helpers import not_support_multi_device + +@unittest.skipIf(CI and Device.DEFAULT in {"CUDA", "NV"}, "slow") +class TestNN(unittest.TestCase): + def test_sparse_cat_cross_entropy(self): + # create in tinygrad + input_tensor = Tensor.randn(6, 5) # not square to test that mean scaling uses the correct dimension + target = Tensor([0, 0, 0, 1, 2, 3]) # torch doesn't support target=-1 + torch_input = torch.tensor(input_tensor.numpy()) + torch_target = torch.tensor(target.numpy(), dtype=torch.long) + + for smoothing in [0.0, 0.1, 0.5, 1.0]: + for ignore_index in [-1, 0, 2]: + for reduction in ["none", "sum", "mean"]: + loss = input_tensor.sparse_categorical_crossentropy(target, label_smoothing=smoothing, ignore_index=ignore_index, reduction=reduction) + torch_loss = torch.nn.CrossEntropyLoss(reduction=reduction, label_smoothing=smoothing, ignore_index=ignore_index)(torch_input, torch_target) + np.testing.assert_allclose(loss.numpy(), torch_loss.detach().numpy(), atol=1e-5, rtol=1e-6) + + # also test with a batch dimension (of size 1) + loss = input_tensor.unsqueeze(0).sparse_categorical_crossentropy( + target.unsqueeze(0), label_smoothing=smoothing, ignore_index=ignore_index, reduction=reduction + ) + torch_loss = torch.nn.CrossEntropyLoss(reduction=reduction, label_smoothing=smoothing, ignore_index=ignore_index)( + torch_input.unsqueeze(0).permute(0,2,1), torch_target.unsqueeze(0) + ) + np.testing.assert_allclose(loss.numpy(), torch_loss.detach().numpy(), atol=1e-5, rtol=1e-6) + + def test_batchnorm2d(self, training=False, threed=False, track_running_stats=True): + with Tensor.train(training): + szs = [4, 8, 16, 32] + for sz in szs: + # create in tinygrad + bn = BatchNorm(sz, eps=1e-5, track_running_stats=track_running_stats) + bn.weight = Tensor.randn(sz) + bn.bias = Tensor.randn(sz) + if track_running_stats: + bn.running_mean = Tensor.randn(sz) + bn.running_var = Tensor.randn(sz) + bn.running_var.numpy()[bn.running_var.numpy() < 0] = 0 + + # create in torch + with torch.no_grad(): + if threed: + tbn = torch.nn.BatchNorm3d(sz, track_running_stats=track_running_stats).eval() + else: + tbn = torch.nn.BatchNorm2d(sz, track_running_stats=track_running_stats).eval() + tbn.training = training + tbn.weight[:] = torch.tensor(bn.weight.numpy()) + tbn.bias[:] = torch.tensor(bn.bias.numpy()) + if track_running_stats: + tbn.running_mean[:] = torch.tensor(bn.running_mean.numpy()) + tbn.running_var[:] = torch.tensor(bn.running_var.numpy()) + + if track_running_stats: + np.testing.assert_allclose(bn.running_mean.numpy(), tbn.running_mean.detach().numpy(), rtol=1e-5, atol=1e-6) + np.testing.assert_allclose(bn.running_var.numpy(), tbn.running_var.detach().numpy(), rtol=1e-5, atol=1e-6) + + # trial + if threed: + inn = Tensor.randn(2, sz, 3, 3, 3) + else: + inn = Tensor.randn(2, sz, 3, 3) + + # in tinygrad + outt = bn(inn) + + # in torch + toutt = tbn(torch.tensor(inn.numpy())) + + # close + np.testing.assert_allclose(outt.numpy(), toutt.detach().numpy(), rtol=5e-4, atol=1e-6) + if track_running_stats: + np.testing.assert_allclose(bn.running_mean.numpy(), tbn.running_mean.detach().numpy(), rtol=1e-5, atol=1e-6) + np.testing.assert_allclose(bn.running_var.numpy(), tbn.running_var.detach().numpy(), rtol=1e-5, atol=1e-6) + + def test_batchnorm2d_training(self): self.test_batchnorm2d(True, False, True) + def test_batchnorm2d_no_running_stats(self): self.test_batchnorm2d(False, False, False) + def test_batchnorm2d_training_no_running_stats(self): self.test_batchnorm2d(True, False, False) + def test_batchnorm3d(self): self.test_batchnorm2d(False, True, True) + def test_batchnorm3d_training(self): self.test_batchnorm2d(True, True, True) + def test_batchnorm3d_no_running_stats(self): self.test_batchnorm2d(False, True, False) + def test_batchnorm3d_training_no_running_stats(self): self.test_batchnorm2d(True, True, False) + + def test_batchnorm_axis(self): + sz = (2, 4, 3, 2, 2) + x = Tensor.randn(sz) + weight = Tensor.randn(2, 3) + bias = Tensor.randn(2, 3) + mean = Tensor.randn(2, 3) + invstd = Tensor.randn(2, 3) + a = (x.batchnorm(weight, bias, mean, invstd, axis=(0, 2)) + .permute(1, 0, 2, 3, 4).reshape(4, 6, 2, 2)) + b = (x.permute(1, 0, 2, 3, 4).reshape(4, 6, 2, 2) + .batchnorm(weight.flatten(), bias.flatten(), mean.flatten(), invstd.flatten())) + t_x = torch.tensor(x.permute(1, 0, 2, 3, 4).reshape(4, 6, 2, 2).numpy()) + t_weight, t_bias = torch.tensor(weight.flatten().numpy()), torch.tensor(bias.flatten().numpy()) + t_mean, t_invstd = torch.tensor(mean.flatten().numpy()), torch.tensor(invstd.flatten().numpy()) + torch.nn.functional.batch_norm(t_x, t_mean, 1.0 / t_invstd**2, t_weight, t_bias) + + np.testing.assert_allclose(a.numpy(), b.numpy()) + + def test_linear(self): + def _test_linear(x, in_dim, out_dim): + # create in tinygrad + model = Linear(in_dim, out_dim) + z = model(x) + + # create in torch + with torch.no_grad(): + torch_layer = torch.nn.Linear(in_dim, out_dim).eval() + torch_layer.weight[:] = torch.tensor(model.weight.numpy(), dtype=torch.float32) + torch_layer.bias[:] = torch.tensor(model.bias.numpy(), dtype=torch.float32) + torch_x = torch.tensor(x.numpy(), dtype=torch.float32) + torch_z = torch_layer(torch_x) + + # test + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) + + BS, T, in_dim, out_dim = 4, 2, 8, 16 + _test_linear(Tensor.randn(BS, in_dim), in_dim, out_dim) + _test_linear(Tensor.randn(BS, T, in_dim), in_dim, out_dim) # test with more dims + + def test_conv1d(self): + BS, C1, W = 4, 16, 224//4 + C2, K, S, P = 64, 7, 2, 1 + + # create in tinygrad + layer = Conv1d(C1, C2, kernel_size=K, stride=S, padding=P) + + # create in torch + with torch.no_grad(): + torch_layer = torch.nn.Conv1d(C1, C2, kernel_size=K, stride=S, padding=P).eval() + torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) + torch_layer.bias[:] = torch.tensor(layer.bias.numpy(), dtype=torch.float32) + + # test + x = Tensor.uniform(BS, C1, W) + z = layer(x) + torch_x = torch.tensor(x.numpy()) + torch_z = torch_layer(torch_x) + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) + + def test_conv2d(self): + BS, C1, H, W = 4, 16, 224//4, 224//4 + C2, K, S, P = 64, 7, 2, 1 + + # create in tinygrad + layer = Conv2d(C1, C2, kernel_size=K, stride=S, padding=P) + + # create in torch + with torch.no_grad(): + torch_layer = torch.nn.Conv2d(C1, C2, kernel_size=K, stride=S, padding=P).eval() + torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) + torch_layer.bias[:] = torch.tensor(layer.bias.numpy(), dtype=torch.float32) + + # test + x = Tensor.uniform(BS, C1, H, W) + z = layer(x) + torch_x = torch.tensor(x.numpy()) + torch_z = torch_layer(torch_x) + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) + + def test_conv1d_same_padding(self): + BS, C1, W = 8, 3, 32 + C2, K, S, P = 16, 3, 1, 'same' + + # create in tinygrad + layer = Conv1d(C1, C2, kernel_size=K, stride=S, padding=P) + + # create in torch + with torch.no_grad(): + torch_layer = torch.nn.Conv1d(C1, C2, kernel_size=K, stride=S, padding=P).eval() + torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) + torch_layer.bias[:] = torch.tensor(layer.bias.numpy(), dtype=torch.float32) + + # test + x = Tensor.uniform(BS, C1, W) + z = layer(x) + torch_x = torch.tensor(x.numpy()) + torch_z = torch_layer(torch_x) + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) + + def _run_conv2d_same_padding_test(self, BS, C1, C2, H, W, K, S, padding='same', D=1): + # create in tinygrad + layer = Conv2d(C1, C2, kernel_size=K, stride=S, padding=padding, dilation=D) + + # create in torch + with torch.no_grad(): + torch_layer = torch.nn.Conv2d(C1, C2, kernel_size=K, stride=S, padding=padding, dilation=D).eval() + torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) + torch_layer.bias[:] = torch.tensor(layer.bias.numpy(), dtype=torch.float32) + + # test + x = Tensor.uniform(BS, C1, H, W) + z = layer(x) + torch_x = torch.tensor(x.numpy()) + torch_z = torch_layer(torch_x) + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) + + def test_conv2d_same_padding_odd_input(self): + BS, C1, H, W = 16, 16, 29, 31 + C2, K, S, P = 32, 5, 1, 'same' + self._run_conv2d_same_padding_test(BS, C1, C2, H, W, K, S, P) + + def test_conv2d_same_padding_large_kernel(self): + BS, C1, H, W = 16, 16, 28, 33 + C2, K, S, P = 32, 9, 1, 'same' + self._run_conv2d_same_padding_test(BS, C1, C2, H, W, K, S, P) + + def test_conv2d_same_padding_with_dilation(self): + BS, C1, H, W = 16, 3, 28, 28 + C2, K, S, P, D = 32, 3, 1, 'same', 3 + self._run_conv2d_same_padding_test(BS, C1, C2, H, W, K, S, P, D) + + def test_conv2d_same_padding_invalid_stride(self): + C1, C2, K, S, P = 16, 32, 2, 2, 'same' + self.assertRaises(ValueError, Conv2d, C1, C2, kernel_size=K, stride=S, padding=P) + + def test_conv2d_same_padding_invalid_padding_str(self): + C1, C2, K, S, P = 16, 32, 2, 1, 'not_same' + self.assertRaises(ValueError, Conv2d, C1, C2, kernel_size=K, stride=S, padding=P) + + @unittest.skip("Takes too long to compile for Compiled backends") + def test_conv2d_winograd(self): + BS, C1, H, W = 2, 8, 16, 16 + C2, K, S, P = 8, 3, 1, 1 + + # create in tinygrad + layer = Conv2d(C1, C2, kernel_size=K, stride=S, padding=P) + layer.weight.requires_grad = True + layer.bias.requires_grad = True + + # create in torch + torch_layer = torch.nn.Conv2d(C1, C2, kernel_size=K, stride=S, padding=P).eval() + torch_layer.weight = torch.nn.Parameter(torch.tensor(layer.weight.numpy(), dtype=torch.float32)) + torch_layer.bias = torch.nn.Parameter(torch.tensor(layer.bias.numpy(), dtype=torch.float32)) + + # test + x = Tensor.uniform(BS, C1, H, W, requires_grad=True) + + with Context(WINO=1): + z = layer(x) + + torch_x = torch.tensor(x.numpy(), requires_grad=True) + torch_z = torch_layer(torch_x) + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) + + m = z.mean() + m.backward() + gw = layer.weight.grad.realize() + gb = layer.bias.grad.realize() + gx = x.grad.realize() + + torch_z.mean().backward() + np.testing.assert_allclose(gw.numpy(), torch_layer.weight.grad.numpy(), atol=5e-4, rtol=1e-5) + np.testing.assert_allclose(gb.numpy(), torch_layer.bias.grad.numpy(), atol=5e-4, rtol=1e-5) + np.testing.assert_allclose(gx.numpy(), torch_x.grad.numpy(), atol=5e-4, rtol=1e-5) + + def test_conv_transpose1d(self): + BS, C1, W = 4, 16, 224//4 + C2, K, S, P = 64, 7, 2, 1 + + # create in tinygrad + layer = ConvTranspose1d(C1, C2, kernel_size=K, stride=S, padding=P) + + # create in torch + with torch.no_grad(): + torch_layer = torch.nn.ConvTranspose1d(C1, C2, kernel_size=K, stride=S, padding=P).eval() + torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) + torch_layer.bias[:] = torch.tensor(layer.bias.numpy(), dtype=torch.float32) + + # test + x = Tensor.uniform(BS, C1, W) + z = layer(x) + torch_x = torch.tensor(x.numpy()) + torch_z = torch_layer(torch_x) + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) + + def test_conv_transpose2d(self): + BS, C1, H, W = 4, 16, 224//4, 224//4 + C2, K, S, P = 64, 7, 2, 1 + + # create in tinygrad + layer = ConvTranspose2d(C1, C2, kernel_size=K, stride=S, padding=P) + + # create in torch + with torch.no_grad(): + torch_layer = torch.nn.ConvTranspose2d(C1, C2, kernel_size=K, stride=S, padding=P).eval() + torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) + torch_layer.bias[:] = torch.tensor(layer.bias.numpy(), dtype=torch.float32) + + # test + x = Tensor.uniform(BS, C1, H, W) + z = layer(x) + torch_x = torch.tensor(x.numpy()) + torch_z = torch_layer(torch_x) + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-4, rtol=1e-5) + + @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") + def test_groupnorm(self): + BS, H, W, C, G = 20, 10, 10, 6, 3 + + # create in torch + torch_layer = torch.nn.GroupNorm(G, C).eval() + + # create in tinygrad + layer = GroupNorm(G, C) + layer.weight = Tensor(torch_layer.weight.detach().numpy(), requires_grad=True) + layer.bias = Tensor(torch_layer.bias.detach().numpy(), requires_grad=True) + + for _ in range(10): + # forward + x = Tensor.randn(BS, C, H, W, requires_grad=True) + z = layer(x) + z.sum().backward() + + torch_x = torch.tensor(x.numpy(), requires_grad=True) + torch_z = torch_layer(torch_x) + torch_z.sum().backward() + + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) + np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=5e-4, rtol=5e-4) + np.testing.assert_allclose(layer.weight.grad.numpy(), torch_layer.weight.grad.detach().numpy(), atol=5e-4, rtol=5e-4) + np.testing.assert_allclose(layer.bias.grad.numpy(), torch_layer.bias.grad.detach().numpy(), atol=5e-4, rtol=5e-4) + + @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") + def test_layernorm(self): + N, C, H, W = 20, 5, 10, 10 + + # create in torch + torch_layer = torch.nn.LayerNorm([H, W]).eval() + + # create in tinygrad + layer = LayerNorm([H, W]) + layer.weight = Tensor(torch_layer.weight.detach().numpy(), requires_grad=True) + layer.bias = Tensor(torch_layer.bias.detach().numpy(), requires_grad=True) + + for _ in range(10): + # forward + x = Tensor.randn(N, C, H, W, requires_grad=True) + z = layer(x) + z.sum().backward() + + torch_x = torch.tensor(x.numpy(), requires_grad=True) + torch_z = torch_layer(torch_x) + torch_z.sum().backward() + + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) + np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=5e-4, rtol=5e-4) + np.testing.assert_allclose(layer.weight.grad.numpy(), torch_layer.weight.grad.detach().numpy(), atol=5e-4, rtol=5e-4) + np.testing.assert_allclose(layer.bias.grad.numpy(), torch_layer.bias.grad.detach().numpy(), atol=5e-4, rtol=5e-4) + + @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") + def test_layernorm_2d(self): + N, C, H, W = 20, 5, 10, 10 + + # create in torch + torch_layer = torch.nn.LayerNorm([C]).eval() + + # create in tinygrad + layer = LayerNorm2d(C) + layer.weight = Tensor(torch_layer.weight.detach().numpy(), requires_grad=True) + layer.bias = Tensor(torch_layer.bias.detach().numpy(), requires_grad=True) + + for _ in range(10): + # forward + x = Tensor.randn(N, C, H, W, requires_grad=True) + z = layer(x) + z.sum().backward() + + torch_x = torch.tensor(x.numpy(), requires_grad=True) + torch_z = torch_layer(torch_x.permute(0,2,3,1)).permute(0,3,1,2) + torch_z.sum().backward() + + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) + np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=5e-4, rtol=5e-4) + np.testing.assert_allclose(layer.weight.grad.numpy(), torch_layer.weight.grad.detach().numpy(), atol=5e-4, rtol=5e-4) + np.testing.assert_allclose(layer.bias.grad.numpy(), torch_layer.bias.grad.detach().numpy(), atol=5e-4, rtol=5e-4) + + @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") + def test_instancenorm_2d(self): + N, C, H, W = 20, 10, 10, 10 + + # create in torch + torch_layer = torch.nn.InstanceNorm2d(C, affine=True).eval() + + # create in tinygrad + layer = InstanceNorm(C) + layer.weight = Tensor(torch_layer.weight.detach().numpy(), requires_grad=True) + layer.bias = Tensor(torch_layer.bias.detach().numpy(), requires_grad=True) + + for _ in range(10): + # forward + x = Tensor.randn(N, C, H, W, requires_grad=True) + z = layer(x) + z.sum().backward() + + torch_x = torch.tensor(x.numpy(), requires_grad=True) + torch_z = torch_layer(torch_x) + torch_z.sum().backward() + + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) + np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=1e-3, rtol=1e-3) + np.testing.assert_allclose(layer.weight.grad.numpy(), torch_layer.weight.grad.detach().numpy(), atol=1e-3, rtol=1e-3) + np.testing.assert_allclose(layer.bias.grad.numpy(), torch_layer.bias.grad.detach().numpy(), atol=1e-3, rtol=1e-3) + + @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") + def test_instancenorm_3d(self): + N, C, D, H, W = 20, 10, 10, 10, 10 + + # create in torch + torch_layer = torch.nn.InstanceNorm3d(C, affine=True).eval() + + # create in tinygrad + layer = InstanceNorm(C) + layer.weight = Tensor(torch_layer.weight.detach().numpy(), requires_grad=True) + layer.bias = Tensor(torch_layer.bias.detach().numpy(), requires_grad=True) + + for _ in range(10): + # forward + x = Tensor.randn(N, C, D, H, W, requires_grad=True) + z = layer(x) + z.sum().backward() + + torch_x = torch.tensor(x.numpy(), requires_grad=True) + torch_z = torch_layer(torch_x) + torch_z.sum().backward() + + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) + np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=1e-3, rtol=1e-3) + np.testing.assert_allclose(layer.weight.grad.numpy(), torch_layer.weight.grad.detach().numpy(), atol=2e-3, rtol=1e-3) + np.testing.assert_allclose(layer.bias.grad.numpy(), torch_layer.bias.grad.detach().numpy(), atol=1e-3, rtol=1e-3) + + @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") + def test_rmsnorm(self): + class TorchRMSNorm(torch.nn.Module): + # https://github.com/meta-llama/llama/blob/be327c427cc5e89cc1d3ab3d3fec4484df771245/llama/model.py#L34C1-L77C36 + def __init__(self, dim: int, eps: float = 1e-6, elementwise_affine: bool = True): + super().__init__() + self.eps = eps + self.elementwise_affine = elementwise_affine + self.weight = torch.nn.Parameter(torch.ones(dim)) if elementwise_affine else None + + def _norm(self, x): + return x * torch.rsqrt(x.pow(2).mean(-1, keepdim=True) + self.eps) + + def forward(self, x): + output = self._norm(x.float()).type_as(x) + return output if self.weight is None else output * self.weight + + B, T, embed_size = 4, 10, 20 + torch_layer = TorchRMSNorm(embed_size) + layer = RMSNorm(embed_size) + layer.weight.requires_grad = True + + for _ in range(10): + # forward + x = Tensor.randn(B, T, embed_size, requires_grad=True) + z = layer(x) + z.sum().backward() + + torch_x = torch.tensor(x.numpy(), requires_grad=True) + torch_z = torch_layer(torch_x) + torch_z.sum().backward() + + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) + np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=1e-3, rtol=1e-3) + np.testing.assert_allclose(layer.weight.grad.numpy(), torch_layer.weight.grad.detach().numpy(), atol=2e-3, rtol=1e-3) + + torch_layer = TorchRMSNorm(embed_size, elementwise_affine=False) + layer = RMSNorm(embed_size, elementwise_affine=False) + + for _ in range(10): + # forward + x = Tensor.randn(B, T, embed_size, requires_grad=True) + z = layer(x) + z.sum().backward() + + torch_x = torch.tensor(x.numpy(), requires_grad=True) + torch_z = torch_layer(torch_x) + torch_z.sum().backward() + + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=5e-6, rtol=5e-6) + np.testing.assert_allclose(x.grad.numpy(), torch_x.grad.detach().numpy(), atol=1e-3, rtol=1e-3) + + def test_embedding(self): + B, T, embed_size, vocab_size = 4, 10, 20, 28 + + # create in tinygrad + layer = Embedding(vocab_size, embed_size) + + with torch.no_grad(): + torch_layer = torch.nn.Embedding(vocab_size, embed_size).eval() + torch_layer.weight[:] = torch.tensor(layer.weight.numpy(), dtype=torch.float32) + + # test + x = Tensor(np.random.randint(0, vocab_size, (B, T), dtype=np.int32)) + z = layer(x) + torch_x = torch.tensor(x.numpy()) + torch_z = torch_layer(torch_x) + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=1e-8, rtol=1e-8) + + # test with empty input length + x = Tensor(np.random.randint(0, vocab_size, (B, 0), dtype=np.int32)) + z = layer(x) + torch_x = torch.tensor(x.numpy()) + torch_z = torch_layer(torch_x) + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=1e-8, rtol=1e-8) + + # test with jit enabled + @TinyJit + def layer_jit(x): + return layer(x).realize() + + for _ in range(3): + x = Tensor(np.random.randint(0, vocab_size, (B, T), dtype=np.int32)) + z = layer_jit(x) + torch_x = torch.tensor(x.numpy()) + torch_z = torch_layer(torch_x) + np.testing.assert_allclose(z.numpy(), torch_z.detach().numpy(), atol=1e-8, rtol=1e-8) + + def test_embedding_one_kernel(self, ops=41410, kcount=3): + GlobalCounters.reset() + layer = Embedding(20, 30) + layer.weight = Tensor.zeros_like(layer.weight).contiguous() + a = Tensor([[1, 5, 9, 11], + [12, 19, 8, 1]]) + result = layer(a) + schedule = result.schedule() + self.assertEqual(kcount, len([item for item in schedule if item.ast.op is Ops.SINK]), "first run realizes weight and embedding") + run_schedule(schedule) + + b = Tensor([[1, 2, 3], + [4, 5, 6], + [7, 8, 9]]) + result = layer(b) + schedule = result.schedule() + self.assertEqual(1, len([item for item in schedule if item.ast.op is Ops.SINK]), "second run realizes embedding only") + run_schedule(schedule) + print(f"Embedding used {GlobalCounters.global_ops} ops") + self.assertLessEqual(GlobalCounters.global_ops, ops) + + # TODO: fused with opts uses more ops + def test_embedding_one_kernel_fused(self): + with Context(FUSE_ARANGE=1, NOOPT=0): + self.test_embedding_one_kernel(ops=612_000, kcount=2) + + def test_embedding_one_kernel_fused_noopt(self): + with Context(FUSE_ARANGE=1, NOOPT=1): + self.test_embedding_one_kernel(ops=0, kcount=2) + + def test_embedding_shape(self): + vocab_size, embed_size = 10, 16 + layer = Embedding(vocab_size, embed_size) + for rank in range(5): + shp = (1,) * rank + a = Tensor([3]).reshape(shp) + result = layer(a) + self.assertEqual(result.shape, shp + (embed_size,)) + + def test_load_state_dict(self): + layer = Conv2d(3, 5, kernel_size=3) + + state_dict = { + 'weight': Tensor.randn(5, 3, 3, 3), + 'bias': Tensor.randn(5), + } + load_state_dict(layer, state_dict) + + np.testing.assert_allclose(layer.weight.numpy(), state_dict['weight'].numpy()) + np.testing.assert_allclose(layer.bias.numpy(), state_dict['bias'].numpy()) + + @unittest.skipIf(not_support_multi_device(), "no multi") + def test_load_state_dict_sharded_model(self): + devices = (f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3") + + layer = Conv2d(3, 5, kernel_size=3) + layer.weight.shard_(devices, 3) + layer.bias.shard_(devices, None) + state_dict = { + 'weight': Tensor.randn(5, 3, 3, 3).realize(), + 'bias': Tensor.randn(5).realize(), + } + load_state_dict(layer, state_dict) + + # sharded model shards the state_dict + self.assertEqual(layer.weight.device, devices) + self.assertEqual(layer.weight.uop.axis, 3) + self.assertEqual(layer.bias.device, devices) + self.assertEqual(layer.bias.uop.axis, None) + np.testing.assert_allclose(layer.weight.numpy(), state_dict['weight'].numpy()) + np.testing.assert_allclose(layer.bias.numpy(), state_dict['bias'].numpy()) + + @unittest.skipIf(not_support_multi_device, "no multi") + def test_load_state_dict_sharded_dict(self): + devices = (f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3") + + layer = Conv2d(3, 5, kernel_size=3) + state_dict = { + 'weight': Tensor.randn(5, 3, 3, 3).shard(devices, 3), + 'bias': Tensor.randn(5).shard(devices, None), + } + load_state_dict(layer, state_dict) + + # NOTE: model is not sharded, still not sharded after load_state_dict + self.assertEqual(layer.weight.device, Device.DEFAULT) + self.assertEqual(layer.bias.device, Device.DEFAULT) + np.testing.assert_allclose(layer.weight.numpy(), state_dict['weight'].numpy()) + np.testing.assert_allclose(layer.bias.numpy(), state_dict['bias'].numpy()) + + @unittest.skipIf(not_support_multi_device(), "no multi") + def test_load_state_dict_sharded_model_dict_same_axis(self): + devices = (f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3") + + layer = Conv2d(3, 5, kernel_size=3) + layer.weight.shard_(devices, 3) + layer.bias.shard_(devices, None) + + state_dict = { + 'weight': Tensor.randn(5, 3, 3, 3).shard(devices, 3), + 'bias': Tensor.randn(5).shard(devices, None), + } + load_state_dict(layer, state_dict) + + self.assertEqual(layer.weight.device, devices) + self.assertEqual(layer.weight.uop.axis, 3) + self.assertEqual(layer.bias.device, devices) + self.assertEqual(layer.bias.uop.axis, None) + np.testing.assert_allclose(layer.weight.numpy(), state_dict['weight'].numpy()) + np.testing.assert_allclose(layer.bias.numpy(), state_dict['bias'].numpy()) + + @unittest.skipIf(not_support_multi_device, "no multi") + def test_load_state_dict_sharded_model_dict_different_axis(self): + devices = (f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3") + devices5 = (f"{Device.DEFAULT}:1", f"{Device.DEFAULT}:2", f"{Device.DEFAULT}:3", f"{Device.DEFAULT}:4", f"{Device.DEFAULT}:5") + + layer = Conv2d(3, 5, kernel_size=3) + layer.weight.shard_(devices, 3) + layer.bias.shard_(devices, None) + + # different shard axis + state_dict = { + 'weight': Tensor.randn(5, 3, 3, 3).shard(devices, None), + 'bias': Tensor.randn(5).shard(devices5, 0), + } + load_state_dict(layer, state_dict) + + # NOTE: model and state_dict shard differently, use the state_dict sharding # TODO: revisit this? + self.assertEqual(layer.weight.device, devices) + self.assertEqual(layer.weight.uop.axis, None) + self.assertEqual(layer.bias.device, devices5) + self.assertEqual(layer.bias.uop.axis, 0) + np.testing.assert_allclose(layer.weight.numpy(), state_dict['weight'].numpy()) + np.testing.assert_allclose(layer.bias.numpy(), state_dict['bias'].numpy()) + + def test_load_state_dict_shape_mismatch(self): + d1, d2 = 2, 4 + layer = Linear(d1, d1, bias=False) + state_dict = {'weight': Tensor.randn(d2, d2)} + with self.assertRaisesRegex(ValueError, r'Shape mismatch in layer `weight`: Expected shape \(2, 2\), but found \(4, 4\) in state dict.'): + load_state_dict(layer, state_dict) + + def test_lstm_cell(self): + layer = LSTMCell(32, 16) + with torch.no_grad(): + torch_layer = torch.nn.LSTMCell(32, 16) + layer.weight_hh.assign(torch_layer.weight_hh.numpy()) + layer.weight_ih.assign(torch_layer.weight_ih.numpy()) + layer.bias_hh.assign(torch_layer.bias_hh.numpy()) + layer.bias_ih.assign(torch_layer.bias_ih.numpy()) + + inp = Tensor.randn(1, 32) + out_h, out_c = layer(inp) + torch_out_h, torch_out_c = torch_layer(torch.tensor(inp.numpy())) + np.testing.assert_allclose(out_h.numpy(), torch_out_h.numpy(), atol=1e-6) + np.testing.assert_allclose(out_c.numpy(), torch_out_c.numpy(), atol=1e-6) + + out_h, out_c = layer(inp, (out_h, out_c)) + torch_out_h, torch_out_c = torch_layer(torch.tensor(inp.numpy()), (torch_out_h, torch_out_c)) + np.testing.assert_allclose(out_h.numpy(), torch_out_h.numpy(), atol=1e-6) + np.testing.assert_allclose(out_c.numpy(), torch_out_c.numpy(), atol=1e-6) + + def test_lstm_cell_no_bias(self): + layer = LSTMCell(32, 16, bias=False) + inp = Tensor.randn(1, 32) + out_h, out_c = layer(inp) + out_h.realize() + out_c.realize() + h = Tensor.randn(1, 16) + c = Tensor.randn(1, 16) + out_h, out_c = layer(inp, (h, c)) + out_h.realize() + out_c.realize() + assert layer.bias_hh is None + assert layer.bias_ih is None + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_ocl.py b/tinygrad_repo/test/test_ocl.py new file mode 100644 index 000000000..04b8e2523 --- /dev/null +++ b/tinygrad_repo/test/test_ocl.py @@ -0,0 +1,31 @@ +import unittest +from tinygrad import Device +from tinygrad.device import Buffer +from tinygrad.dtype import dtypes +from tinygrad.helpers import CI +from tinygrad.runtime.ops_gpu import CLDevice, CLAllocator, CLCompiler, CLProgram + +@unittest.skipUnless(Device.DEFAULT == "GPU", "Runs only on OpenCL (GPU)") +class TestCLError(unittest.TestCase): + @unittest.skipIf(CI, "dangerous for CI, it allocates tons of memory") + def test_oom(self): + with self.assertRaises(RuntimeError) as err: + allocator = CLAllocator(CLDevice()) + for i in range(1_000_000): + allocator.alloc(1_000_000_000) + assert str(err.exception) == "OpenCL Error -6: CL_OUT_OF_HOST_MEMORY" + + def test_invalid_kernel_name(self): + device = Device[Device.DEFAULT] + with self.assertRaises(RuntimeError) as err: + CLProgram(device, name="", lib=CLCompiler(device, "test").compile("__kernel void test(__global int* a) { a[0] = 1; }")) + assert str(err.exception) == "OpenCL Error -46: CL_INVALID_KERNEL_NAME" + + def test_unaligned_copy(self): + data = list(range(65)) + unaligned = memoryview(bytearray(data))[1:] + buffer = Buffer("GPU", 64, dtypes.uint8).allocate() + buffer.copyin(unaligned) + result = memoryview(bytearray(len(data) - 1)) + buffer.copyout(result) + assert unaligned == result, "Unaligned data copied in must be equal to data copied out." diff --git a/tinygrad_repo/test/test_ops.py b/tinygrad_repo/test/test_ops.py new file mode 100644 index 000000000..b7ed67b1b --- /dev/null +++ b/tinygrad_repo/test/test_ops.py @@ -0,0 +1,3062 @@ +import time, math, unittest, functools +import numpy as np +from typing import List, Callable +import torch +import warnings +from tinygrad.helpers import getenv, IMAGE, DEBUG, CI, Context, TRANSCENDENTAL, OSX +from tinygrad import Tensor, Device, dtypes +from tinygrad.tensor import _to_np_dtype +from tinygrad.device import is_dtype_supported + +if getenv("TINY_BACKEND"): + import tinygrad.frontend.torch # noqa: F401 # pylint: disable=unused-import + torch.set_default_device("tiny") + +if CI: + warnings.filterwarnings("ignore", message="Non-empty compiler output encountered") + +FORWARD_ONLY = getenv("FORWARD_ONLY", 0) +PRINT_TENSORS = getenv("PRINT_TENSORS", 0) + +def helper_test_op(shps, torch_fxn, tinygrad_fxn=None, atol=1e-6, rtol=1e-3, grad_atol=1e-4, grad_rtol=1e-3, + forward_only=False, vals=None, low=-2, high=2): + if tinygrad_fxn is None: tinygrad_fxn = torch_fxn + ts, tst = prepare_test_op(low, high, shps, vals, forward_only) + + st = time.monotonic() + out = torch_fxn(*ts) + torch_fp = time.monotonic() - st + + # move inputs to a different device, test the device of intermediate tensors are correct + if mt:=getenv("MOVE_TENSOR", ""): + for t in tst: t.to_(mt) + + st = time.monotonic() + ret = tinygrad_fxn(*tst).realize() + tinygrad_fp = time.monotonic() - st + + def compare(s, tinygrad_output, torch_output, atol, rtol): + if PRINT_TENSORS: print(s, tinygrad_output, torch_output) + try: + assert tinygrad_output.shape == torch_output.shape, f"shape mismatch: tinygrad={tinygrad_output.shape} | torch={torch_output.shape}" + assert tinygrad_output.dtype == torch_output.dtype, f"dtype mismatch: tinygrad={tinygrad_output.dtype} | torch={torch_output.dtype}" + if np.issubdtype(tinygrad_output.dtype, np.floating): + np.testing.assert_allclose(tinygrad_output, torch_output, atol=atol, rtol=rtol) + else: + np.testing.assert_equal(tinygrad_output, torch_output) + except Exception as e: + raise Exception(f"{s} failed shape {tinygrad_output.shape}: {e}") + + if DEBUG >= 6: + np.set_printoptions(linewidth=200, suppress=True) + print(ret.numpy()) + print(out.detach().cpu().numpy()) + compare("forward pass", ret.numpy(), out.detach().cpu().numpy(), atol=atol, rtol=rtol) + + torch_fbp, tinygrad_fbp = np.nan, np.nan + if not forward_only and not FORWARD_ONLY and ts and tst: + st = time.monotonic() + torch_grads = torch.autograd.grad(torch_fxn(*ts).sum(), ts) + torch_fbp = time.monotonic() - st + + st = time.monotonic() + # NOTE: we now have to recompute the forward pass since we realized it + tiny_grads = tinygrad_fxn(*tst).sum().gradient(*tst) + Tensor.realize(*tiny_grads) + tinygrad_fbp = time.monotonic() - st + + for i, (t, torch_grad) in enumerate(zip(tiny_grads, torch_grads)): + compare(f"backward pass tensor {i}", t.numpy(), torch_grad.detach().cpu().numpy(), atol=grad_atol, rtol=grad_rtol) + + if not CI: + print("\ntesting %40r torch/tinygrad fp: %.2f / %.2f ms bp: %.2f / %.2f ms " % \ + (shps, torch_fp*1000, tinygrad_fp*1000, torch_fbp*1000, tinygrad_fbp*1000), end="") + +def prepare_test_op(low, high, shps, vals, forward_only=False): + if shps is None: + ts = [torch.tensor(x, requires_grad=(not forward_only)) for x in vals] + else: + np.random.seed(0) + np_data = [np.random.uniform(low=low, high=high, size=size).astype(_to_np_dtype(dtypes.default_float)) for size in shps] + ts = [torch.tensor(data, requires_grad=(not forward_only)) for data in np_data] + for i in range(len(ts)): + # NOTE: torch default int64 for python ints input + if ts[i].dtype == torch.int64: ts[i] = ts[i].type(torch.int32) + tst = [Tensor(x.detach().cpu().numpy(), requires_grad=(not forward_only and not FORWARD_ONLY)) for x in ts] + return ts, tst + +class TestOps(unittest.TestCase): + + def helper_test_exception(self, shps, torch_fxn, tinygrad_fxn, expected, forward_only=False, exact=False, vals=None, low=-1.5, high=1.5): + if getenv("MOCKGPU") and Device.DEFAULT == "NV": self.skipTest('helper_test_exception fails in CI CUDA') + ts, tst = prepare_test_op(low, high, shps, vals, forward_only) + with self.assertRaises(expected) as torch_cm: + torch_fxn(*ts) + with self.assertRaises(expected) as tinygrad_cm: + tinygrad_fxn(*tst) + if exact: self.assertEqual(str(torch_cm.exception), str(tinygrad_cm.exception)) + if not CI: print("\ntesting %40r torch/tinygrad exception: %s / %s" % (shps, torch_cm.exception, tinygrad_cm.exception), end="") + + def test_full_like(self): + a = Tensor([[1,2,3],[4,5,6]], dtype=dtypes.float32) + b = torch.tensor([[1,2,3],[4,5,6]], dtype=torch.float32) + helper_test_op([], lambda: torch.full_like(b, 4), lambda: Tensor.full_like(a, 4), forward_only=True) + + a = Tensor([[1,2,3],[4,5,6]], dtype=dtypes.int32) + b = torch.tensor([[1,2,3],[4,5,6]], dtype=torch.int32) + helper_test_op([], lambda: torch.full_like(b, 4), lambda: Tensor.full_like(a, 4), forward_only=True) + + def test_full(self): + helper_test_op([], lambda: torch.full((45,65), 4, dtype=torch.int32), lambda: Tensor.full((45,65), 4), forward_only=True) + + def test_negative_dims(self): + creation_methods: List[Callable[..., Tensor]] = [ + Tensor.empty, + Tensor.rand, + Tensor.zeros, + Tensor.ones, + Tensor.randn, + Tensor.randint, + Tensor.normal, + Tensor.uniform, + Tensor.scaled_uniform, + Tensor.glorot_uniform + ] + + for method in creation_methods: + with self.assertRaises(ValueError): method(-3, 2) + with self.assertRaises(ValueError): method((2, -3)) + with self.assertRaises(ValueError): method((2, -3, 0)) + + def test_negative_dims_full(self): + with self.assertRaises(ValueError): Tensor.full((-3,), 2) + with self.assertRaises(ValueError): Tensor.full((2, -3), 4) + with self.assertRaises(ValueError): Tensor.full((2, -3, 0), 4) + + def test_negative_dims_eye(self): + with self.assertRaises(ValueError): Tensor.eye(-3, 3) + with self.assertRaises(ValueError): Tensor.eye(3, -3) + with self.assertRaises(ValueError): Tensor.eye(-3, -3) + + def test_negative_dims_kaiming(self): + creation_methods = [Tensor.kaiming_uniform, Tensor.kaiming_normal] + for method in creation_methods: + with self.assertRaises(ValueError): method(-3, 3) + with self.assertRaises(ValueError): method((-3, 3), 3) + with self.assertRaises(ValueError): method((-3, -3), 3) + + def test_zeros(self): + helper_test_op([], lambda: torch.zeros(45,65), lambda: Tensor.zeros(45,65), forward_only=True) + helper_test_op([], lambda: torch.zeros([45,65]), lambda: Tensor.zeros([45,65]), forward_only=True) + helper_test_op([], lambda: torch.zeros([]), lambda: Tensor.zeros([]), forward_only=True) + + def test_zeros_like(self): + a = Tensor([[1,2,3],[4,5,6]], dtype=dtypes.float32) + b = torch.tensor([[1,2,3],[4,5,6]], dtype=torch.float32) + helper_test_op([], lambda: torch.zeros_like(b), lambda: Tensor.zeros_like(a), forward_only=True) + + a = Tensor([[1,2,3],[4,5,6]], dtype=dtypes.int32) + b = torch.tensor([[1,2,3],[4,5,6]], dtype=torch.int32) + helper_test_op([], lambda: torch.zeros_like(b), lambda: Tensor.zeros_like(a), forward_only=True) + + def test_empty_0(self): + helper_test_op([], lambda: torch.empty(45,65)*0/0, lambda: Tensor.empty(45,65)*0/0, forward_only=True) + + def test_ones(self): + helper_test_op([], lambda: torch.ones(45,65), lambda: Tensor.ones(45,65), forward_only=True) + helper_test_op([], lambda: torch.ones([45,65]), lambda: Tensor.ones([45,65]), forward_only=True) + helper_test_op([], lambda: torch.ones([]), lambda: Tensor.ones([]), forward_only=True) + + def test_ones_like(self): + a = Tensor([[1,2,3],[4,5,6]], dtype=dtypes.float32) + b = torch.tensor([[1,2,3],[4,5,6]], dtype=torch.float32) + helper_test_op([], lambda: torch.ones_like(b), lambda: Tensor.ones_like(a), forward_only=True) + + a = Tensor([[1,2,3],[4,5,6]], dtype=dtypes.int32) + b = torch.tensor([[1,2,3],[4,5,6]], dtype=torch.int32) + helper_test_op([], lambda: torch.ones_like(b), lambda: Tensor.ones_like(a), forward_only=True) + + def test_eye(self): + helper_test_op([], lambda: torch.eye(10), lambda: Tensor.eye(10), forward_only=True) + helper_test_op([], lambda: torch.eye(3, 5), lambda: Tensor.eye(3, 5), forward_only=True) + helper_test_op([], lambda: torch.eye(5, 3), lambda: Tensor.eye(5, 3), forward_only=True) + helper_test_op([], lambda: torch.eye(1), lambda: Tensor.eye(1), forward_only=True) + helper_test_op([], lambda: torch.eye(0), lambda: Tensor.eye(0), forward_only=True) + + def test_split(self): + def tensor(s): return torch.arange(math.prod(s), dtype=torch.int32).reshape(s), Tensor.arange(math.prod(s)).reshape(s) + test_cases = [ + (tensor((10,)), 5, {}), + (tensor((10,)), [1,4,5], {}), + (tensor((10,)), 3, {}), + (tensor((3,4,)), 1, {}), + (tensor((3,4,)), 1, {'dim':1}), + (tensor((4,4,)), [2,2], {}), + (tensor((4,4,)), [2,2], {'dim':1}), + (tensor((10000,)), 2500, {}), + ] + + for (tor, ten), sizes, args in test_cases: + tor_splits, ten_splits = tor.split(sizes, **args), ten.split(sizes, **args) + assert len(tor_splits) == len(ten_splits) + for tor_chunk, ten_chunk in zip(tor_splits, ten_splits): + helper_test_op([], lambda: tor_chunk, lambda: ten_chunk, forward_only=True) + + def test_chunk(self): + tor = torch.arange(13, dtype=torch.int32).repeat(8, 1).chunk(6, 1) + ten = Tensor.arange(13).repeat((8, 1)).chunk(6, 1) + assert len(tor) == len(ten) + for i in range(len(tor)): + helper_test_op([], lambda: tor[i], lambda: ten[i], forward_only=True) + + tor = torch.arange(13, dtype=torch.int32).repeat(8, 1).chunk(6, 0) + ten = Tensor.arange(13).repeat((8, 1)).chunk(6, 0) + assert len(tor) == len(ten) + for i in range(len(tor)): + helper_test_op([], lambda: tor[i], lambda: ten[i], forward_only=True) + + tor = torch.arange(13, dtype=torch.int32).repeat(8, 1).chunk(3, -1) + ten = Tensor.arange(13).repeat((8, 1)).chunk(3, -1) + assert len(tor) == len(ten) + for i in range(len(tor)): + helper_test_op([], lambda: tor[i], lambda: ten[i], forward_only=True) + + tor = torch.arange(13, dtype=torch.int32).repeat(8, 3, 3).chunk(3, -2) + ten = Tensor.arange(13).repeat((8, 3, 3)).chunk(3, -2) + assert len(tor) == len(ten) + for i in range(len(tor)): + helper_test_op([], lambda: tor[i], lambda: ten[i], forward_only=True) + + def test_unfold(self): + helper_test_op([(8,)], lambda x: x.unfold(0, 2, 1)) + helper_test_op([(8,)], lambda x: x.unfold(0, 2, 2)) + helper_test_op([(8,)], lambda x: x.unfold(0, 7, 3)) + helper_test_op([(3,3,3)], lambda x: x.unfold(2, 2, 8)) + helper_test_op([(3,3,3)], lambda x: x.unfold(1, 0, 8)) + helper_test_op([(3,3,3,3,3)], lambda x: x.unfold(-1, 2, 2)) + + self.helper_test_exception([(8,)], lambda x: x.unfold(0, 9, 3), lambda x: x.unfold(0, 9, 3), expected=RuntimeError) + self.helper_test_exception([(8,)], lambda x: x.unfold(1, 8, 3), lambda x: x.unfold(1, 8, 3), expected=IndexError) + self.helper_test_exception([(8,)], lambda x: x.unfold(0, -1, 3), lambda x: x.unfold(0, 9, 3), expected=RuntimeError) + self.helper_test_exception([(8,)], lambda x: x.unfold(0, 1, -1), lambda x: x.unfold(0, 9, 3), expected=RuntimeError) + + def test_meshgrid(self): + x, xt = torch.tensor([0.,1.,2.], requires_grad=True), Tensor([0.,1.,2.], requires_grad=True) + y, yt = torch.tensor([3.,4.,5.,6.], requires_grad=True), Tensor([3.,4.,5.,6.], requires_grad=True) + z, zt = torch.tensor([7.,8.,9.], requires_grad=True), Tensor([7.,8.,9.], requires_grad=True) + for indexing in ("ij", "xy"): + tor = torch.meshgrid(x, indexing=indexing) + ten = xt.meshgrid(indexing=indexing) + self.assertEqual(len(tor), len(ten)) + for tor_i, ten_i in zip(tor, ten): + helper_test_op([], lambda: tor_i, lambda: ten_i) + tor = torch.meshgrid(x, y, indexing=indexing) + ten = xt.meshgrid(yt, indexing=indexing) + self.assertEqual(len(tor), len(ten)) + for tor_i, ten_i in zip(tor, ten): + helper_test_op([], lambda: tor_i, lambda: ten_i) + tor = torch.meshgrid(x, torch.tensor(10., requires_grad=True), y, z, indexing=indexing) + ten = xt.meshgrid(Tensor(10., requires_grad=True), yt, zt, indexing=indexing) + self.assertEqual(len(tor), len(ten)) + for tor_i, ten_i in zip(tor, ten): + helper_test_op([], lambda: tor_i, lambda: ten_i) + + self.helper_test_exception([], lambda: torch.meshgrid(x, indexing="bad"), lambda: xt.meshgrid(indexing="bad"), expected=RuntimeError) + + def test_arange(self): + helper_test_op([], lambda: torch.arange(10, dtype=torch.int32), lambda: Tensor.arange(10), forward_only=True) + helper_test_op([], lambda: torch.arange(36, dtype=torch.int32), lambda: Tensor.arange(36), forward_only=True) + helper_test_op([], lambda: torch.arange(5, 10, 3, dtype=torch.int32), lambda: Tensor.arange(5, 10, 3), forward_only=True) + helper_test_op([], lambda: torch.arange(10, 5, -3, dtype=torch.int32), lambda: Tensor.arange(10, 5, -3), forward_only=True) + helper_test_op([], lambda: torch.arange(11, 5, -3, dtype=torch.int32), lambda: Tensor.arange(11, 5, -3), forward_only=True) + helper_test_op([], lambda: torch.arange(1, 78, 2, dtype=torch.int32), lambda: Tensor.arange(1, 78, 2), forward_only=True) + helper_test_op([], lambda: torch.arange(5.5, 175.5, 2.5), lambda: Tensor.arange(5.5, 175.5, 2.5), forward_only=True) + helper_test_op([], lambda: torch.arange(-30.2, -0.3, 0.75), lambda: Tensor.arange(-30.2, -0.3, 0.75), forward_only=True) + helper_test_op([], lambda: torch.arange(-50.3, -380.2, -2.25), lambda: Tensor.arange(-50.3, -380.2, -2.25), forward_only=True) + + def test_arange_big(self): + helper_test_op([], lambda: torch.arange(256, dtype=torch.int32), lambda: Tensor.arange(256), forward_only=True) + + def test_arange_4096(self): + helper_test_op([], lambda: torch.arange(4096, dtype=torch.int32), lambda: Tensor.arange(4096), forward_only=True) + + def test_linspace(self): + helper_test_op([], lambda: torch.linspace(5, 10, 3), lambda: Tensor.linspace(5, 10, 3), forward_only=True) + helper_test_op([], lambda: torch.linspace(5, 10, 1), lambda: Tensor.linspace(5, 10, 1), forward_only=True) + helper_test_op([], lambda: torch.linspace(5, 10, 0), lambda: Tensor.linspace(5, 10, 0), forward_only=True) + helper_test_op([], lambda: torch.linspace(5, 10, 30), lambda: Tensor.linspace(5, 10, 30), forward_only=True) + helper_test_op([], lambda: torch.linspace(-5.5, 5.5, 10), lambda: Tensor.linspace(-5.5, 5.5, 10), forward_only=True) + helper_test_op([], lambda: torch.linspace(5.5, -5.5, 10), lambda: Tensor.linspace(5.5, -5.5, 10), forward_only=True) + helper_test_op([], lambda: torch.linspace(5, 10, 3, dtype=torch.int32), lambda: Tensor.linspace(5, 10, 3, dtype="int32"), forward_only=True) + helper_test_op([], lambda: torch.linspace(5, 10, 20, dtype=torch.int32), lambda: Tensor.linspace(5, 10, 20, dtype="int32"), forward_only=True) + helper_test_op([], lambda: torch.linspace(5, -5, 20, dtype=torch.int32), lambda: Tensor.linspace(5, -5, 20, dtype="int32"), forward_only=True) + self.helper_test_exception([], lambda: torch.linspace(5, 10, 3, dtype=torch.bool), lambda: Tensor.linspace(5, 10, 3, dtype="bool"), + expected=(RuntimeError, ValueError)) + self.helper_test_exception([], lambda: torch.linspace(1, 2, -1), lambda: Tensor.linspace(1, 2, -1), expected=(RuntimeError, ValueError)) + + def test_sum_fake(self): + helper_test_op([(256, 1)], lambda x: x.sum(axis=1)) + + def test_sum_collapse(self): + helper_test_op([], lambda: torch.ones(256,256).sum(axis=1), lambda: Tensor.ones(256,256).sum(axis=1), forward_only=True) + + def test_sum_collapse_neg(self): + helper_test_op([], lambda: (-torch.ones(3,3)).sum(axis=1), lambda: (-Tensor.ones(3,3)).sum(axis=1), forward_only=True) + + def test_sum_pad_collapse(self): + helper_test_op([], lambda: torch.nn.functional.pad(torch.ones(256,256), pad=(0,64,0,0)).sum(axis=1), + lambda: Tensor.ones(256,256).pad(((0,0), (0,64))).sum(axis=1), forward_only=True) + + # this is more complex and won't fold for a while + def test_sum_cat_collapse(self): + helper_test_op([], lambda: torch.cat([torch.ones(256,256), torch.zeros(256,64)], dim=1).sum(axis=1), + lambda: Tensor.cat(Tensor.ones(256,256), Tensor.zeros(256,64), dim=1).sum(axis=1), forward_only=True) + + def test_max_dont_collapse(self): + helper_test_op([], lambda: torch.ones(256,256).max(1)[0], lambda: Tensor.ones(256,256).max(1), forward_only=True) + + def test_where(self): + helper_test_op( + [(100,)], + lambda x: torch.where(x > 0.5, 4, 2).type(torch.int32), + lambda x: (x > 0.5).where(4, 2), forward_only=True) + + for shps in [[(8,),(1,),(1,)], [(10,10),(10,),(10,)], [(100,)]*3, [(10,10)]*3]: + helper_test_op( + shps, + lambda x, a, b: torch.where(x > 0.5, a, b), + lambda x, a, b: (x > 0.5).where(a, b), forward_only=True) + + def test_where_permute(self): + helper_test_op( + [(5, 5)], + lambda x: torch.where(x > 0.5, 4, 2).type(torch.int32).permute((1, 0)), + lambda x: (x > 0.5).where(4, 2).permute((1, 0)), forward_only=True) + + def _test_cmp(self, fxn, reverse=True): + # test different dtypes + helper_test_op(None, fxn, fxn, forward_only=True, vals=[[0.,1,2], [2.,1,0]]) + helper_test_op(None, fxn, fxn, forward_only=True, vals=[[0,1,2], [2,1,0]]) + helper_test_op(None, fxn, fxn, forward_only=True, vals=[[True, True, False], [False,True,False]]) + # test broadcasting + for shps in [[(3, 4, 5), (3, 4, 5)], [(3, 4, 5), (5,)], [(5,), (3, 4, 5)]]: + helper_test_op(shps, fxn, fxn, forward_only=True) + # test cmp with const + helper_test_op(None, lambda x,y: fxn(x,2), lambda x,y: fxn(x,2), forward_only=True, vals=[[0.,1,2], [2.,1,0]]) + if reverse: helper_test_op(None, lambda x,y: fxn(2,y), lambda x,y: fxn(2,y), forward_only=True, vals=[[0.,1,2], [2.,1,0]]) + # test special floats # TODO: fix nan + specials = [0.0, 1.0, -1.0, math.inf, -math.inf]#, math.nan] + for s0 in specials: + for s1 in specials: + helper_test_op(None, fxn, fxn, forward_only=True, vals=[[s0], [s1]]) + + def test_cmp_eq(self): self._test_cmp(lambda x,y: x==y, reverse=False) + def test_cmp_gt(self): self._test_cmp(lambda x,y: x>y) + def test_cmp_ge(self): self._test_cmp(lambda x,y: x>=y) + def test_cmp_lt(self): self._test_cmp(lambda x,y: x 0).where(1//t, t).numpy(), [-1, 0, 1, 0]) + + def test_scalar_div(self): + helper_test_op([(45,65)], lambda x: x/255) + helper_test_op([(45,65)], lambda x: x/1) + helper_test_op([(45,65)], lambda x: 1/x) + helper_test_op([(45,65)], lambda x: x/2) + helper_test_op([(45,65)], lambda x: 2/x) + helper_test_op([()], lambda x: x/2) + helper_test_op([()], lambda x: 2/x) + + def test_mod(self): + a = [-4, 7, 5, 4, -7, 8, -9] + b = [2, -3, 8, -2, 3, 5, -5] + for float_a in [True, False]: + for float_b in [True, False]: + va = [float(ai) for ai in a] if float_a else a + vb = [float(bi) for bi in b] if float_b else b + helper_test_op(None, lambda x,y: x%y, Tensor.mod, forward_only=True, vals=[va, vb]) + helper_test_op(None, lambda x,y: x%y, forward_only=True, vals=[va, vb]) + helper_test_op(None, lambda x: x%2, forward_only=True, vals=[va]) + helper_test_op(None, lambda x: x%3, forward_only=True, vals=[va]) + helper_test_op(None, lambda x: x%3.5, forward_only=True, vals=[va]) + helper_test_op(None, lambda x: 100%x, forward_only=True, vals=[va]) + helper_test_op(None, lambda x: 100.5%x, forward_only=True, vals=[va]) + + def test_mul_naninf(self): + helper_test_op([(45,65)], lambda x: x*math.inf) + helper_test_op([(45,65)], lambda x: x*-math.inf) + helper_test_op([(45,65)], lambda x: x*math.nan) + def test_div_naninf(self): + helper_test_op([(45,65)], lambda x: x/math.inf) + helper_test_op([(45,65)], lambda x: x/-math.inf) + helper_test_op([(45,65)], lambda x: x/math.nan) + helper_test_op([(45,65)], lambda x: math.inf/x) + helper_test_op([(45,65)], lambda x: (-math.inf)/x) + helper_test_op([(45,65)], lambda x: math.nan/x) + + def test_pow_full(self): + helper_test_op([(45,65), (45,65)], lambda x,y: x**y) + helper_test_op([(45,65), (45,65)], lambda x,y: x.pow(y)) + + def test_pow(self): + helper_test_op([(45,65)], lambda x: x**0) + helper_test_op([(45,65)], lambda x: x**1) + helper_test_op([(45,65)], lambda x: x**2) + helper_test_op([(45,65)], lambda x: x**3) + helper_test_op([(45,65)], lambda x: x**-2) + helper_test_op([()], lambda x: x**2) + helper_test_op([()], lambda x: x**-2) + # Regression tests for https://github.com/tinygrad/tinygrad/issues/1151 + helper_test_op([(45,65)], lambda x: x**3, low=-30, high=-27) + helper_test_op([()], lambda x: x**3, low=-30, high=-27) + # Regression tests for https://github.com/tinygrad/tinygrad/issues/1251 + helper_test_op([(45,65)], lambda x: x**0.2, low=-30, high=-27) + helper_test_op([(45,65)], lambda x: x**1.2, low=-30, high=-27) + helper_test_op([()], lambda x: x**0.2, low=-30, high=-27) + helper_test_op([()], lambda x: x**1.2, low=-30, high=-27) + a, b = Tensor([0.0], requires_grad=True), torch.tensor([0.0], requires_grad=True) + helper_test_op([], lambda: b**1.1, lambda: a**1.1) + + def test_pow_const(self): + helper_test_op([(45,65)], lambda x: x**0.0) + helper_test_op([(45,65)], lambda x: x**1.0) + helper_test_op([(45,65)], lambda x: x**-1.0) + helper_test_op([(45,65)], lambda x: x**8.0) + helper_test_op([(45,65)], lambda x: x**5.5) + helper_test_op([(45,65)], lambda x: x**-5.5) + # helper_test_op([(45,65)], lambda x: x**-8.0) # TODO: fix this + helper_test_op([(45,65)], lambda x: 1.0**x) + helper_test_op([(45,65)], lambda x: 5.5**x) + helper_test_op([(45,65)], lambda x: (-5.5)**x) + helper_test_op([(45,65)], lambda x: 8.0**x) + helper_test_op([(45,65)], lambda x: x**2.0) + helper_test_op([(45,65)], lambda x: 2.0**x) + helper_test_op([()], lambda x: x**2.0) + helper_test_op([()], lambda x: 2.0**x) + helper_test_op(None, lambda x: 0**x, vals=[[-2.,-1,0,1,2,3]]) + helper_test_op(None, lambda x: 0.7**x, vals=[[-2.,-1,0,1,2,3]]) + helper_test_op(None, lambda x: (-2)**x, vals=[[-2.,-1,0,1,2,3]]) + # float to power of int + helper_test_op(None, lambda x: 0.7**x, vals=[[-2,-1,0,1,2,3]], forward_only=True) + + def test_pow_const_direct(self): + # x ** c + def get_tiny_gradient(x, c): + t = Tensor([x], dtype=dtypes.float) + return (t ** c)[0].gradient(t)[0].item() + def get_torch_gradient(x, c): + t = torch.tensor([x], dtype=torch.float, requires_grad=True) + return torch.autograd.grad(t ** c, t)[0].item() + for x in [-math.inf, 0, 1, math.inf]: + for c in [-1, 0, 0.3, 1, 2]: + tiny_out = get_tiny_gradient(x, c) + torch_out = get_torch_gradient(x, c) + if math.isnan(tiny_out): + assert math.isnan(torch_out) + else: + self.assertAlmostEqual(tiny_out, torch_out, msg=f"{x}, {c}") + + def test_pow_zero_tensor(self): + helper_test_op(None, lambda x,y: x**y, vals=[[0.0], [0.0]]) + # TODO: fix WEBGPU + if Device.DEFAULT != "WEBGPU": + helper_test_op(None, lambda x,y: x**y, vals=[[0.0], [0.3]]) + helper_test_op(None, lambda x,y: x**y, vals=[[0.0], [-0.3]]) + def test_pow_zero_const(self): + helper_test_op(None, lambda x: x**0.3, vals=[[0.0]]) + helper_test_op(None, lambda x: x**0.0, vals=[[0.0]]) + helper_test_op(None, lambda x: x**-0.3, vals=[[0.0]]) + helper_test_op(None, lambda x: x**-1.0, vals=[[-1.0, 0.0, 1.0]]) + + @unittest.skip("not supported") + def test_pow_int(self): + def _test(base, exponent): helper_test_op(None, lambda x,y: x**y, vals=[base, exponent], forward_only=True) + + for base in ([1, 2, 3], [-1, -2, -3]): + for exponent in ([2, 3, 4], [-2, -3, -4]): + _test(base, exponent) + # NOTE: torch 0 ** -1 is 0 + _test([0, 0, 0], [0, 1, 2]) + + np.testing.assert_equal((Tensor(11) ** Tensor(7)).item(), 11 ** 7) + np.testing.assert_equal((Tensor([11]) ** Tensor(7)).item(), 11 ** 7) + # TODO: fix non-precise int pow + with self.assertRaises(AssertionError): np.testing.assert_equal((Tensor(11) ** Tensor([7])).item(), 11 ** 7) + with self.assertRaises(AssertionError): np.testing.assert_equal((Tensor([11]) ** Tensor([7])).item(), 11 ** 7) + + # pow to a const int + helper_test_op([], lambda: torch.tensor([2], dtype=torch.int) ** torch.tensor(-2, dtype=torch.int), + lambda: Tensor([2]) ** Tensor(-2), forward_only=True) + + def test_sqrt(self): + helper_test_op([(45,65)], lambda x: x.sqrt()) + helper_test_op(None, lambda x: x.sqrt(), vals=[[0.0]]) + helper_test_op([()], lambda x: x.sqrt()) + def test_rsqrt(self): + helper_test_op([(45,65)], lambda x: x.rsqrt()) + helper_test_op(None, lambda x: x.rsqrt(), vals=[[0.0]]) + helper_test_op([()], lambda x: x.rsqrt()) + + def test_xor(self): + data = [[1,-8,1],[32,1,6]] + tor = torch.tensor(data, dtype=torch.int) + ten = Tensor(data, dtype=dtypes.int32) + helper_test_op([], lambda: tor^tor, lambda: ten^ten, forward_only=True) + helper_test_op([], lambda: tor^0x1337, lambda: ten^0x1337, forward_only=True) + helper_test_op([], lambda: 0x1337^tor, lambda: 0x1337^ten, forward_only=True) + + self.helper_test_exception([(4), (4)], torch.bitwise_xor, Tensor.bitwise_xor, expected=RuntimeError) + + def test_and(self): + data = [[1,-8,1],[32,1,6]] + tor = torch.tensor(data, dtype=torch.int) + ten = Tensor(data, dtype=dtypes.int32) + helper_test_op([], lambda: tor&tor, lambda: ten&ten, forward_only=True) + helper_test_op([], lambda: tor&0x1337, lambda: ten&0x1337, forward_only=True) + helper_test_op([], lambda: 0x1337&tor, lambda: 0x1337&ten, forward_only=True) + + data = [[True, True, False, False], [True, False, True, False]] + tor0, tor1 = torch.tensor(data[0], dtype=torch.bool), torch.tensor(data[1], dtype=torch.bool) + ten0, ten1 = Tensor(data[0], dtype=dtypes.bool), Tensor(data[1], dtype=dtypes.bool) + helper_test_op([], lambda: tor0&tor1, lambda: ten0&ten1, forward_only=True) + + helper_test_op(None, lambda x: (1 < x) & (x < 2), forward_only=True, vals=[[1.2, 1.2, 1.2, 3.2]]) + + self.helper_test_exception([(4), (4)], torch.bitwise_and, Tensor.bitwise_and, expected=RuntimeError) + + def test_or(self): + data = [[1,-8,1],[32,1,6]] + tor = torch.tensor(data, dtype=torch.int) + ten = Tensor(data, dtype=dtypes.int32) + helper_test_op([], lambda: tor|tor, lambda: ten|ten, forward_only=True) + helper_test_op([], lambda: tor|0x1337, lambda: ten|0x1337, forward_only=True) + helper_test_op([], lambda: 0x1337|tor, lambda: 0x1337|ten, forward_only=True) + + data = [[True, True, False, False], [True, False, True, False]] + tor0, tor1 = torch.tensor(data[0], dtype=torch.bool), torch.tensor(data[1], dtype=torch.bool) + ten0, ten1 = Tensor(data[0], dtype=dtypes.bool), Tensor(data[1], dtype=dtypes.bool) + helper_test_op([], lambda: tor0|tor1, lambda: ten0|ten1, forward_only=True) + + self.helper_test_exception([(4), (4)], torch.bitwise_or, Tensor.bitwise_or, expected=RuntimeError) + + def test_bitwise_not(self): + data = [[1,-8,1],[32,1,6]] + tor = torch.tensor(data, dtype=torch.int) + ten = Tensor(data, dtype=dtypes.int32) + helper_test_op([], lambda: tor.bitwise_not(), lambda: ten.bitwise_not(), forward_only=True) + helper_test_op([], lambda: ~tor, lambda: ~ten, forward_only=True) + + data = [[True, False]] + tor = torch.tensor(data, dtype=torch.bool) + ten = Tensor(data, dtype=dtypes.bool) + helper_test_op([], lambda: tor.bitwise_not(), lambda: ten.bitwise_not(), forward_only=True) + helper_test_op([], lambda: ~tor, lambda: ~ten, forward_only=True) + + self.helper_test_exception([(4)], torch.bitwise_not, Tensor.bitwise_not, expected=RuntimeError) + + def test_lshift(self): + data = [[0,1,2],[1<<8,1<<16,1<<31-1]] + tor = torch.tensor(data, dtype=torch.int) + ten = Tensor(data, dtype=dtypes.uint32) + # cast to int32 because torch does not support uint32 + helper_test_op([], lambda: tor << 0, lambda: (ten << 0).cast(dtypes.int32), forward_only=True) + helper_test_op([], lambda: tor << 2, lambda: (ten << 2).cast(dtypes.int32), forward_only=True) + helper_test_op([], lambda: tor << 31, lambda: (ten << 31).cast(dtypes.int32), forward_only=True) + helper_test_op([], lambda: tor.__lshift__(2), lambda: ten.__lshift__(2).cast(dtypes.int32), forward_only=True) + helper_test_op([], lambda: tor.bitwise_left_shift(2), lambda: ten.lshift(2).cast(dtypes.int32), forward_only=True) + + def test_rshift(self): + data = [[0,1,2],[1<<8,1<<16,1<<31-1]] + tor = torch.tensor(data, dtype=torch.int) + ten = Tensor(data, dtype=dtypes.uint32) + # cast to int32 because torch does not support uint32 + helper_test_op([], lambda: tor >> 0, lambda: (ten >> 0).cast(dtypes.int32), forward_only=True) + helper_test_op([], lambda: tor >> 2, lambda: (ten >> 2).cast(dtypes.int32), forward_only=True) + helper_test_op([], lambda: tor >> 31, lambda: (ten >> 31).cast(dtypes.int32), forward_only=True) + helper_test_op([], lambda: tor.__rshift__(2), lambda: ten.__rshift__(2).cast(dtypes.int32), forward_only=True) + helper_test_op([], lambda: tor.bitwise_right_shift(2), lambda: ten.rshift(2).cast(dtypes.int32), forward_only=True) + + def test_idiv_shift_rewrite_negative(self): + a = Tensor(-5).idiv(2).item() + b = Tensor(-5).contiguous().idiv(2).item() + self.assertEqual(a, b) + self.assertEqual(Tensor(-1).contiguous().idiv(4).item(), 0) # NOTE this is trunc-div behaviour + + def test_sin(self): + helper_test_op([(45,65)], lambda x: x.sin()) + helper_test_op([()], lambda x: x.sin()) + # works on real CUDA but not CI + if not ((getenv("MOCKGPU") and Device.DEFAULT == "NV") or Device.DEFAULT == "WEBGPU"): + helper_test_op(None, lambda x: x.sin(), vals=[[math.nan, math.inf, -math.inf, 0.0]]) + helper_test_op(None, lambda x: x.sin(), vals=[[1e1, 1e2, 1e3, 1e4, 1e5, 1e6, -1e1, -1e2, -1e3, -1e4, -1e5, -1e6]], + atol=3e-3, rtol=3e-3, grad_atol=3e-3, grad_rtol=3e-3) + def test_cos(self): + helper_test_op([(45,65)], lambda x: x.cos()) + helper_test_op([()], lambda x: x.cos()) + if not ((getenv("MOCKGPU") and Device.DEFAULT == "NV") or Device.DEFAULT == "WEBGPU"): + helper_test_op(None, lambda x: x.sin(), vals=[[math.nan, math.inf, -math.inf, 0.0]]) + helper_test_op(None, lambda x: x.cos(), vals=[[1e1, 1e2, 1e3, 1e4, 1e5, 1e6, -1e1, -1e2, -1e3, -1e4, -1e5, -1e6]], + atol=3e-3, rtol=3e-3, grad_atol=3e-3, grad_rtol=3e-3) + def test_tan(self): + # NOTE: backward has much higher diff with input close to pi/2 and -pi/2 + helper_test_op([(45,65)], lambda x: x.tan(), low=-1.5, high=1.5) + helper_test_op([(45,65)], lambda x: x.tan(), low=-5, high=5) + helper_test_op([()], lambda x: x.tan()) + if not ((getenv("MOCKGPU") and Device.DEFAULT == "NV") or Device.DEFAULT == "WEBGPU"): + helper_test_op(None, lambda x: x.sin(), vals=[[math.nan, math.inf, -math.inf, 0.0]]) + helper_test_op(None, lambda x: x.cos(), vals=[[1e1, 1e2, 1e3, 1e4, 1e5, 1e6, -1e1, -1e2, -1e3, -1e4, -1e5, -1e6]], + atol=3e-3, rtol=3e-3, grad_atol=3e-3, grad_rtol=3e-3) + + def test_asin(self): + helper_test_op([(45,65)], lambda x: x.asin(), low=-1, high=1) + helper_test_op([(45,65)], lambda x: x.asin(), low=-300, high=-297) + helper_test_op([(45,65)], lambda x: x.asin(), low=300, high=303) + def test_acos(self): + # high grad atol + helper_test_op([(45,65)], lambda x: x.acos(), low=-1, high=1) + helper_test_op([(45,65)], lambda x: x.acos(), low=-300, high=-297) + helper_test_op([(45,65)], lambda x: x.acos(), low=300, high=303) + def test_atan(self): + helper_test_op([(45,65)], lambda x: x.atan()) + helper_test_op([(45,65)], lambda x: x.atan(), low=-300, high=-297) + helper_test_op([(45,65)], lambda x: x.atan(), low=300, high=303) + + def test_relu(self): + helper_test_op([(64,64)], lambda x: x.relu()) + helper_test_op([()], lambda x: x.relu()) + def test_relu_exact(self): + helper_test_op(None, lambda x: x.relu(), vals=[[-1.,0,1]]) + def test_relu_maximum_exact(self): + helper_test_op(None, lambda x: torch.maximum(x, torch.zeros_like(x, requires_grad=False)), lambda x: Tensor.maximum(x, 0), vals=[[-1.,0,1]]) + def test_leaky_relu(self): + helper_test_op([(45,65)], lambda x: torch.nn.functional.leaky_relu(x,0.01), Tensor.leaky_relu) + helper_test_op([()], lambda x: torch.nn.functional.leaky_relu(x,0.01), Tensor.leaky_relu) + def test_celu(self): + for val in range(1, 5): + helper_test_op([(45,65)], lambda x: torch.nn.functional.celu(x,val), lambda x: x.celu(val)) + helper_test_op([()], lambda x: torch.nn.functional.celu(x,val), lambda x: x.celu(val)) + def test_selu(self): + helper_test_op([(45,65)], torch.nn.functional.selu, Tensor.selu) + helper_test_op([()], torch.nn.functional.selu, Tensor.selu) + def test_silu(self): + helper_test_op([(45,65)], torch.nn.functional.silu, Tensor.silu) + helper_test_op([()], torch.nn.functional.silu, Tensor.silu) + def test_swish(self): + helper_test_op([(45,65)], torch.nn.functional.silu, Tensor.swish) + helper_test_op([()], torch.nn.functional.silu, Tensor.swish) + + def test_abs(self): + helper_test_op([(45,65)], torch.abs, Tensor.abs) + helper_test_op([()], torch.abs, Tensor.abs) + def test_abs_exact(self): + helper_test_op(None, torch.abs, Tensor.abs, vals=[[-1.,0,1]]) + + @unittest.skipIf(TRANSCENDENTAL and Device.DEFAULT=="AMD", "TODO: remu crashes") + def test_log(self): + helper_test_op([(45,65)], torch.log, Tensor.log) + helper_test_op(None, torch.log, Tensor.log, vals=[[math.inf, -math.inf, math.nan]]) + helper_test_op([()], torch.log, Tensor.log) + def test_log2(self): + helper_test_op([(45,65)], torch.log2, Tensor.log2) + helper_test_op(None, torch.log2, Tensor.log2, vals=[[math.inf, -math.inf, math.nan]]) + helper_test_op([()], torch.log2, Tensor.log2) + + @unittest.skipIf(TRANSCENDENTAL and Device.DEFAULT=="AMD", "TODO: remu crashes") + def test_exp(self): + helper_test_op([(45,65)], torch.exp, Tensor.exp) + helper_test_op(None, torch.exp, Tensor.exp, vals=[[math.inf, -math.inf, math.nan]]) + helper_test_op([()], torch.exp, Tensor.exp) + def test_exp2(self): + helper_test_op([(45,65)], torch.exp2, Tensor.exp2) + helper_test_op(None, torch.exp2, Tensor.exp2, vals=[[math.inf, -math.inf, math.nan]]) + helper_test_op([()], torch.exp2, Tensor.exp2) + + def test_sign(self): + helper_test_op([(45,65)], torch.sign, Tensor.sign) + helper_test_op([()], torch.sign, Tensor.sign) + def test_sign_exact(self): + helper_test_op(None, torch.sign, Tensor.sign, vals=[[-1.,0,1]]) + + def test_copysign(self): + helper_test_op([(45,65), (45,65)], torch.copysign, Tensor.copysign) + helper_test_op([(45,65), (45,1)], torch.copysign, Tensor.copysign) + helper_test_op([(45,1), (1,65)], torch.copysign, Tensor.copysign) + helper_test_op([(), ()], torch.copysign, Tensor.copysign) + def test_copysign_exact(self): + for i in [-1.,0.,1.]: + for j in [-1., 0., 1.]: + helper_test_op(None, torch.copysign, Tensor.copysign, vals=[[i], [j]]) + + def test_softsign(self): + helper_test_op([(45,65)], torch.nn.functional.softsign, Tensor.softsign) + helper_test_op([()], torch.nn.functional.softsign, Tensor.softsign) + def test_softsign_exact(self): + helper_test_op(None, torch.nn.functional.softsign, Tensor.softsign, vals=[[-1.,0,1]]) + + def test_sigmoid(self): + helper_test_op([(45,65)], torch.sigmoid, Tensor.sigmoid) + helper_test_op([()], torch.sigmoid, Tensor.sigmoid) + def test_sigmoid_extreme(self): + helper_test_op([(45,65)], torch.sigmoid, Tensor.sigmoid, low=300, high=400) + helper_test_op([(45,65)], torch.sigmoid, Tensor.sigmoid, low=-400, high=-300) + x = Tensor([300.0]) + self.assertAlmostEqual(x.sigmoid()[0].gradient(x)[0].item(), 0.0) + x = Tensor([-300.0]) + self.assertAlmostEqual(x.sigmoid()[0].gradient(x)[0].item(), 0.0) + def test_sigmoid_alt_extreme(self): + def sigmoid(x:Tensor): return x.exp() / (1 + x.exp()) + x = Tensor([300.0]) + self.assertAlmostEqual(sigmoid(x)[0].gradient(x)[0].item(), 0.0) + x = Tensor([-300.0]) + self.assertAlmostEqual(sigmoid(x)[0].gradient(x)[0].item(), 0.0) + + def test_logsigmoid(self): + helper_test_op([(45,65)], torch.nn.functional.logsigmoid, Tensor.logsigmoid) + helper_test_op([()], torch.nn.functional.logsigmoid, Tensor.logsigmoid) + + def test_hardsigmoid(self): + helper_test_op([(45,65)], torch.nn.functional.hardsigmoid, Tensor.hardsigmoid) + helper_test_op([()], torch.nn.functional.hardsigmoid, Tensor.hardsigmoid) + def test_hardsigmoid_extreme(self): + helper_test_op([(45,65)], torch.sigmoid, Tensor.sigmoid, low=300, high=400) + helper_test_op([(45,65)], torch.sigmoid, Tensor.sigmoid, low=-400, high=-300) + def test_softplus(self): + helper_test_op([(45,65)], torch.nn.functional.softplus, Tensor.softplus, grad_atol=1e-6) + helper_test_op([(45,65)], lambda t: torch.nn.functional.softplus(t, beta=3), lambda t: Tensor.softplus(t, beta=3), grad_atol=1e-6) + helper_test_op([(45,65)], lambda t: torch.nn.functional.softplus(t, beta=1/3), lambda t: Tensor.softplus(t, beta=1/3), grad_atol=1e-6) + # # TODO: support threshold and enable this + # helper_test_op([(45,65)], torch.nn.functional.softplus, Tensor.softplus, grad_atol=1e-6, low=300, high=400) + helper_test_op([(45,65)], torch.nn.functional.softplus, Tensor.softplus, grad_atol=1e-6, low=-400, high=-300) + helper_test_op([()], torch.nn.functional.softplus, Tensor.softplus, grad_atol=1e-6) + + def test_erf(self): + helper_test_op([(45,65)], torch.erf, Tensor.erf) + helper_test_op([(45,65)], torch.erf, Tensor.erf, low=300, high=400) + helper_test_op([(45,65)], torch.erf, Tensor.erf, low=-400, high=-300) + helper_test_op([()], torch.erf, Tensor.erf) + + def test_gelu(self): + helper_test_op([(45,65)], lambda x: torch.nn.functional.gelu(x, approximate="tanh"), Tensor.gelu) + def test_gelu_extreme(self): + helper_test_op([(45,65)], lambda x: torch.nn.functional.gelu(x, approximate="tanh"), Tensor.gelu, low=300, high=400) + helper_test_op([(45,65)], lambda x: torch.nn.functional.gelu(x, approximate="tanh"), Tensor.gelu, low=-400, high=-300) + def test_quick_gelu(self): + helper_test_op([(45,65)], lambda x: x * torch.sigmoid(1.702 * x), Tensor.quick_gelu) + helper_test_op([()], lambda x: x * torch.sigmoid(1.702 * x), Tensor.quick_gelu) + def test_quick_gelu_extreme(self): + helper_test_op([(45,65)], lambda x: x * torch.sigmoid(1.702 * x), Tensor.quick_gelu, low=300, high=400) + helper_test_op([(45,65)], lambda x: x * torch.sigmoid(1.702 * x), Tensor.quick_gelu, low=-400, high=-300) + + def test_elu(self): + helper_test_op([(45,65)], torch.nn.functional.elu, Tensor.elu) + helper_test_op([(45,65)], lambda x: torch.nn.functional.elu(x, alpha=0.1), lambda x: Tensor.elu(x, alpha=0.1)) + helper_test_op([()], torch.nn.functional.elu, Tensor.elu) + def test_relu6(self): + helper_test_op([(45,65)], torch.nn.functional.relu6, Tensor.relu6) + helper_test_op([()], torch.nn.functional.relu6, Tensor.relu6) + def test_hardswish(self): + helper_test_op([(45,65)], torch.nn.functional.hardswish, Tensor.hardswish, grad_atol=1e-6) + helper_test_op([()], torch.nn.functional.hardswish, Tensor.hardswish, grad_atol=1e-6) + def test_mish(self): + helper_test_op([(45,65)], torch.nn.functional.mish, Tensor.mish) + helper_test_op([()], torch.nn.functional.mish, Tensor.mish) + + def test_small_cumsum(self): + helper_test_op([(10)], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) + def test_simple_cumsum(self): + helper_test_op([(512)], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) + helper_test_op([(1022)], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) + def test_cumsum(self): + helper_test_op([()], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) + self.helper_test_exception([()], lambda x: torch.cumsum(x, dim=1), lambda x: Tensor.cumsum(x, axis=1), expected=IndexError) + helper_test_op([(20,)], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) + self.helper_test_exception([(20,)], lambda x: torch.cumsum(x, dim=1), lambda x: Tensor.cumsum(x, axis=1), expected=IndexError) + self.helper_test_exception([(20,)], lambda x: torch.cumsum(x, dim=-2), lambda x: Tensor.cumsum(x, axis=-2), expected=IndexError) + helper_test_op([(20,30)], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) + helper_test_op([(20,30)], lambda x: torch.cumsum(x, dim=1), lambda x: Tensor.cumsum(x, axis=1)) + helper_test_op([(20,30,40)], lambda x: torch.cumsum(x, dim=2), lambda x: Tensor.cumsum(x, axis=2)) + helper_test_op([(20,30,40)], lambda x: torch.cumsum(x, dim=-1), lambda x: Tensor.cumsum(x, axis=-1)) + def test_cumsum_zero_axis(self): + helper_test_op([(2,0,4)], lambda x: torch.cumsum(x, dim=1), lambda x: Tensor.cumsum(x, axis=1)) + helper_test_op([(0,3)], lambda x: torch.cumsum(x, dim=0), lambda x: Tensor.cumsum(x, axis=0)) + helper_test_op([(2,3,0)], lambda x: torch.cumsum(x, dim=2), lambda x: Tensor.cumsum(x, axis=2)) + + def test_small_cumprod(self): + helper_test_op([(10)],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) + def test_simple_cumprod(self): + helper_test_op([(512)],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) + helper_test_op([(1022)],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) + def test_cumprod(self): + helper_test_op([()],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) + self.helper_test_exception([()],lambda x: torch.cumprod(x, dim=1),lambda x: Tensor.cumprod(x, axis=1),expected=IndexError) + helper_test_op([(20,)],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) + self.helper_test_exception([(20,)],lambda x: torch.cumprod(x, dim=1),lambda x: Tensor.cumprod(x, axis=1),expected=IndexError) + self.helper_test_exception([(20,)],lambda x: torch.cumprod(x, dim=-2),lambda x: Tensor.cumprod(x, axis=-2),expected=IndexError) + helper_test_op([(20, 30)],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) + helper_test_op([(20, 30)],lambda x: torch.cumprod(x, dim=1),lambda x: Tensor.cumprod(x, axis=1)) + helper_test_op([(20, 30, 40)],lambda x: torch.cumprod(x, dim=2),lambda x: Tensor.cumprod(x, axis=2)) + helper_test_op([(20, 30, 40)],lambda x: torch.cumprod(x, dim=-1),lambda x: Tensor.cumprod(x, axis=-1)) + def test_cumprod_zero_axis(self): + helper_test_op([(2, 0, 4)],lambda x: torch.cumprod(x, dim=1),lambda x: Tensor.cumprod(x, axis=1)) + helper_test_op([(0, 3)],lambda x: torch.cumprod(x, dim=0),lambda x: Tensor.cumprod(x, axis=0)) + helper_test_op([(2, 3, 0)],lambda x: torch.cumprod(x, dim=2),lambda x: Tensor.cumprod(x, axis=2)) + + def test_small_cummax(self): + helper_test_op([(10)], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) + def test_simple_cummax(self): + helper_test_op([(512)], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) + helper_test_op([(1022)], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) + def test_cummax(self): + helper_test_op([()], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) + # TODO: torch allows this? + # self.helper_test_exception([()], lambda x: torch.cummax(x, dim=1).values, lambda x: Tensor.cummax(x, axis=1), expected=IndexError) + helper_test_op([(20,)], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) + self.helper_test_exception([(20,)], lambda x: torch.cummax(x, dim=1).values, lambda x: Tensor.cummax(x, axis=1), expected=IndexError) + self.helper_test_exception([(20,)], lambda x: torch.cummax(x, dim=-2).values, lambda x: Tensor.cummax(x, axis=-2), expected=IndexError) + helper_test_op([(20,30)], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) + helper_test_op([(20,30)], lambda x: torch.cummax(x, dim=1).values, lambda x: Tensor.cummax(x, axis=1)) + helper_test_op([(20,30,40)], lambda x: torch.cummax(x, dim=2).values, lambda x: Tensor.cummax(x, axis=2)) + helper_test_op([(20,30,40)], lambda x: torch.cummax(x, dim=-1).values, lambda x: Tensor.cummax(x, axis=-1)) + def test_cummax_zero_axis(self): + helper_test_op([(2,0,4)], lambda x: torch.cummax(x, dim=1).values, lambda x: Tensor.cummax(x, axis=1)) + helper_test_op([(0,3)], lambda x: torch.cummax(x, dim=0).values, lambda x: Tensor.cummax(x, axis=0)) + helper_test_op([(2,3,0)], lambda x: torch.cummax(x, dim=2).values, lambda x: Tensor.cummax(x, axis=2)) + + def test_argmax(self): + # check if it returns the first index for multiple occurences + helper_test_op(None, lambda x: x.argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[2, 2]]) + helper_test_op(None, lambda x: x.argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[1, 2, 2]]) + np.testing.assert_equal(Tensor([2,2]).argmax().numpy(), 0) + np.testing.assert_equal(Tensor([1,2,2]).argmax().numpy(), 1) + helper_test_op([(10,20)], lambda x: x.argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True) + helper_test_op([(10,20)], lambda x: x.argmax(0, False).type(torch.int32), lambda x: x.argmax(0, False), forward_only=True) + helper_test_op([(10,20)], lambda x: x.argmax(1, False).type(torch.int32), lambda x: x.argmax(1, False), forward_only=True) + helper_test_op([(10,20)], lambda x: x.argmax(1, True).type(torch.int32), lambda x: x.argmax(1, True), forward_only=True) + # regression test for bitwise_not then argmax + helper_test_op(None, lambda x: (~x).argmax().type(torch.int32), lambda x: (~x).argmax(), forward_only=True, vals=[[2, 2]]) + + helper_test_op(None, lambda x: x.argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[0, -2**31]]) + helper_test_op(None, lambda x: x.argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[-2**31, 0]]) + # NOTE: torch does not support this on bool + helper_test_op(None, lambda x: x.type(torch.int32).argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[False, True]]) + helper_test_op(None, lambda x: x.type(torch.int32).argmax().type(torch.int32), lambda x: x.argmax(), forward_only=True, vals=[[True, False]]) + + def test_argmin(self): + # check if it returns the first index for multiple occurences + helper_test_op(None, lambda x: x.argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[2, 2]]) + helper_test_op(None, lambda x: x.argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[3, 2, 2]]) + np.testing.assert_equal(Tensor([2,2]).argmin().numpy(), 0) + np.testing.assert_equal(Tensor([3,2,2]).argmin().numpy(), 1) + helper_test_op([(10,20)], lambda x: x.argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True) + helper_test_op([(10,20)], lambda x: x.argmin(0, False).type(torch.int32), lambda x: x.argmin(0, False), forward_only=True) + helper_test_op([(10,20)], lambda x: x.argmin(1, False).type(torch.int32), lambda x: x.argmin(1, False), forward_only=True) + helper_test_op([(10,20)], lambda x: x.argmin(1, True).type(torch.int32), lambda x: x.argmin(1, True), forward_only=True) + + helper_test_op(None, lambda x: x.argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[0, -2**31]]) + helper_test_op(None, lambda x: x.argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[-2**31, 0]]) + # NOTE: torch does not support this on bool + helper_test_op(None, lambda x: x.type(torch.int32).argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[False, True]]) + helper_test_op(None, lambda x: x.type(torch.int32).argmin().type(torch.int32), lambda x: x.argmin(), forward_only=True, vals=[[True, False]]) + + def test_sort(self): + for dim in [-1, 0, 1]: + for descending in [True, False]: + helper_test_op([(8,8,6)], lambda x: x.sort(dim, descending).values, lambda x: x.sort(dim, descending)[0], forward_only=True) + helper_test_op([(8,8,6)], lambda x: x.sort(dim, descending).indices.type(torch.int32), lambda x: x.sort(dim, descending)[1], + forward_only=True) + # repeated values + helper_test_op(None, lambda x: x.sort(stable=True).values, lambda x: x.sort()[0], forward_only=True, vals=[[0, 1] * 9]) + helper_test_op(None, lambda x: x.sort(stable=True).indices.type(torch.int32), lambda x: x.sort()[1], forward_only=True, vals=[[0, 1] * 9]) + helper_test_op(None, lambda x: x.sort(stable=True, descending=True).values, + lambda x: x.sort(descending=True)[0], forward_only=True, vals=[[0, 1] * 9]) + helper_test_op(None, lambda x: x.sort(stable=True, descending=True).indices.type(torch.int32), + lambda x: x.sort(descending=True)[1], forward_only=True, vals=[[0, 1] * 9]) + + def test_topk(self): + helper_test_op([(10)], lambda x: x.topk(3).values, lambda x: x.topk(3)[0], forward_only=True) + helper_test_op([(10)], lambda x: x.topk(3).indices.type(torch.int32), lambda x: x.topk(3)[1], forward_only=True) + for dim in [0, 1, -1]: + for largest in [True, False]: + for sorted_ in [True]: # TODO support False + helper_test_op([(6,5,4)], + lambda x: x.topk(4, dim, largest, sorted_).values, + lambda x: x.topk(4, dim, largest, sorted_)[0], forward_only=True) + helper_test_op([(5,5,4)], + lambda x: x.topk(4, dim, largest, sorted_).indices.type(torch.int32), + lambda x: x.topk(4, dim, largest, sorted_)[1], forward_only=True) + # repeated values + value, indices = Tensor([1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0]).topk(3) + np.testing.assert_equal(value.numpy(), [1, 1, 1]) + np.testing.assert_equal(indices.numpy(), [0, 1, 3]) + value, indices = Tensor([1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0]).topk(3, largest=False) + np.testing.assert_equal(value.numpy(), [0, 0, 0]) + np.testing.assert_equal(indices.numpy(), [2, 4, 6]) + self.helper_test_exception([(4)], lambda x: x.topk(5), lambda x: x.topk(5), expected=(RuntimeError, ValueError)) + + def test_einsum(self): + # matrix transpose + helper_test_op([(150,150)], lambda a: torch.einsum('ij->ji', a), lambda a: Tensor.einsum('ij->ji', a)) + helper_test_op([(150,150)], lambda a: torch.einsum('ij -> ji', a), lambda a: Tensor.einsum('ij -> ji', a)) + helper_test_op([(150,150)], lambda a: torch.einsum('ji', a), lambda a: Tensor.einsum('ji', a)) + helper_test_op([(20,30,40)], lambda a: torch.einsum('jki', a), lambda a: Tensor.einsum('jki', a)) + helper_test_op([(20,30,40)], lambda a: torch.einsum('dog', a), lambda a: Tensor.einsum('dog', a)) + # no -> and empty rhs + helper_test_op([(20,30),(30,40)], lambda a, b: torch.einsum('ij,jk', a, b), lambda a, b: Tensor.einsum('ij,jk', a, b)) + # sum all elements + helper_test_op([(20,30,40)], lambda a: torch.einsum('ijk->', a), lambda a: Tensor.einsum('ijk->', a)) + # column sum + helper_test_op([(50,50)], lambda a: torch.einsum('ij->j', a), lambda a: Tensor.einsum('ij->j', a)) + # row sum + helper_test_op([(15,15)], lambda a: torch.einsum('ij->i', a), lambda a: Tensor.einsum('ij->i', a)) + # matrix-vector multiplication + helper_test_op([(15,20), (20,)], lambda a,b: torch.einsum('ik,k->i', a,b), lambda a,b: Tensor.einsum('ik,k->i', a, b)) + # matrix-matrix multiplication + helper_test_op([(15,20), (20,30)], lambda a,b: torch.einsum('ik,kj->ij', a,b), lambda a,b: Tensor.einsum('ik,kj->ij', a, b)) + # matrix-matrix multiplication, different letter order + helper_test_op([(15,20), (20,30)], lambda a,b: torch.einsum('jk,ki->ji', a,b), lambda a,b: Tensor.einsum('jk,ki->ji', a, b)) + # dot product + helper_test_op([(30),(30)], lambda a,b: torch.einsum('i,i->i', [a,b]), lambda a,b: Tensor.einsum('i,i->i', [a,b])) + # hadamard product + helper_test_op([(30,40),(30,40)], lambda a,b: torch.einsum('ij,ij->ij', a,b), lambda a,b: Tensor.einsum('ij,ij->ij', a,b)) + # outer product + helper_test_op([(15,), (15,)], lambda a,b: torch.einsum('i,j->ij', a,b), lambda a,b: Tensor.einsum('i,j->ij',a,b)) + # batch matrix multiplication + helper_test_op([(10,20,30),(10,30,40)], lambda a,b: torch.einsum('ijk,ikl->ijl', [a, b]), lambda a,b: Tensor.einsum('ijk,ikl->ijl', [a, b])) + # batch matrix multiplication, result permuted + helper_test_op([(10,20,25),(10,25,32)], lambda a,b: torch.einsum('ijk,ikl->jil', [a, b]), lambda a,b: Tensor.einsum('ijk,ikl->jil', [a, b])) + # batch matrix multiplication, result & input permuted + helper_test_op([(20,10,25),(10,25,32)], lambda a,b: torch.einsum('jik,ikl->jil', [a, b]), lambda a,b: Tensor.einsum('jik,ikl->jil', [a, b])) + # batch matrix multiplication, result with different letters + helper_test_op([(10,20,30),(10,30,40)], lambda a,b: torch.einsum('ijk,ika->ija', [a, b]), lambda a,b: Tensor.einsum('ijk,ika->ija', [a, b])) + # tensor contraction + helper_test_op([(3,5,8,10),(11,13,5,16,8)], lambda a,b: torch.einsum('pqrs,tuqvr->pstuv', a,b), + lambda a,b: Tensor.einsum('pqrs,tuqvr->pstuv', a,b), atol=1e-5) + # tensor contraction, input permuted + helper_test_op([(3,8,10,5),(11,5,13,16,8)], lambda a,b: torch.einsum('prsq,tquvr->pstuv', a,b), + lambda a,b: Tensor.einsum('prsq,tquvr->pstuv', a,b), atol=1e-5) + # tensor contraction, result with different letters + helper_test_op([(3,5,8,10),(11,13,5,16,8)], lambda a,b: torch.einsum('zqrs,tuqvr->zstuv', a,b), + lambda a,b: Tensor.einsum('zqrs,tuqvr->zstuv', a,b), atol=1e-5) + # bilinear transformation + helper_test_op([(2,3),(5,3,7),(2,7)], lambda a,b,c: torch.einsum('ik,jkl,il->ij', [a,b,c]), lambda a,b,c: Tensor.einsum('ik,jkl,il->ij', [a,b,c])) + + def test_einsum_ellipsis(self): + """The expected behavior for einsum is described in the PyTorch docs: https://pytorch.org/docs/stable/generated/torch.einsum.html""" + # test ellipsis + helper_test_op([(3, 8, 9), (3, 8, 9)], lambda a, b: torch.einsum('...id, ...jd -> ...ij', [a, b]), + lambda a, b: Tensor.einsum('...id, ...jd -> ...ij', [a, b])) + # ellipsis will come first in the output before the subscript labels, if rhs is not specified + helper_test_op([(3, 8, 9), (3, 8, 9)], lambda a, b: torch.einsum('...id, ...jd', [a, b]), + lambda a, b: Tensor.einsum('...id, ...jd', [a, b])) + # multiple ellipsis in different operands with different shapes are allowed + helper_test_op([(2, 3, 4, 5), (5, 2, 4)], lambda a, b: torch.einsum('i...j,ji...->...', [a, b]), + lambda a, b: Tensor.einsum('i...j,ji...->...', [a, b])) + # match torch ellipsis handling + helper_test_op([(32, 7, 24, 24, 24), (32, 7, 24, 24, 24)], lambda a, b: torch.einsum('ij...,ij...->ij', [a, b]), + lambda a, b: Tensor.einsum('ij...,ij...->ij', [a, b])) + # multiple ellipsis in one operand are not allowed. This test shall raise an exception. + with self.assertRaises(RuntimeError): + helper_test_op([(2, 3, 4), (2, 3, 4)], lambda a, b: torch.einsum('...ik..., ...jk ->', [a, b]), + lambda a, b: Tensor.einsum('...ik..., ...jk ->', [a, b])) + # multiple ellipsis must broadcast together. This test shall raise an exception. + with self.assertRaises(RuntimeError): + helper_test_op([(2, 3, 4, 5), (5, 2, 7)], lambda a, b: torch.einsum('i...j,ji...->...', [a, b]), + lambda a, b: Tensor.einsum('i...j,ji...->...', [a, b])) + + def test_einsum_shape_check(self): + a = Tensor.zeros(3,8,10,5) + b = Tensor.zeros(11,5,13,16,8) + with self.assertRaises(AssertionError): + Tensor.einsum('pqrs,tuqvr->pstuv',a,b) + + def test_einsum_arity_check1(self): + a = Tensor.zeros(10,15) + b = Tensor.zeros(15,20) + c = Tensor.zeros(20,10) + with self.assertRaises(AssertionError): + Tensor.einsum('ij,jk->ij', a,b,c) + + def test_einsum_arity_check2(self): + a = Tensor.zeros(10,10) + with self.assertRaises(AssertionError): + Tensor.einsum('ij,jk->ij', a) + + @unittest.skipIf(IMAGE>0, "no 1d dot for images") + def test_dot_1d(self): + helper_test_op([(65), (65)], lambda x,y: x.matmul(y), Tensor.dot) + helper_test_op([(65), (65,45)], lambda x,y: x.matmul(y), Tensor.dot) + helper_test_op([(45,65), (65)], lambda x,y: x.matmul(y), Tensor.dot) + helper_test_op([(8,45,65), (65)], lambda x,y: x.matmul(y), Tensor.dot) + helper_test_op([(65), (8,65,45)], lambda x,y: x.matmul(y), Tensor.dot) + self.helper_test_exception([(4), (1,2)], lambda x, y: x.matmul(y), Tensor.dot, expected=RuntimeError) + self.helper_test_exception([(2,1), (4)], lambda x, y: x.matmul(y), Tensor.dot, expected=RuntimeError) + self.helper_test_exception([(1), (4)], lambda x, y: x.matmul(y), Tensor.dot, expected=RuntimeError) + def test_dot(self): + helper_test_op([(45,65), (65,100)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-5) + helper_test_op([(8,45,65), (8,65,100)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-5) + self.helper_test_exception([(2, 4), (1, 3)], lambda x, y: x.matmul(y), Tensor.dot, expected=RuntimeError) + self.helper_test_exception([(2, 1), (4, 3)], lambda x, y: x.matmul(y), Tensor.dot, expected=RuntimeError) + with self.assertRaises(RuntimeError): + a = Tensor(3.14) + a.matmul(a) + def test_mulacc_with_zero_strides(self): + helper_test_op( + [], + lambda: torch.tensor(1.0).reshape((1,1,1)).expand(2,4,3).mul(torch.tensor(1.0).reshape((1,1,1)).expand(2,4,3)).sum(-1), + lambda: Tensor(1.0).reshape((1,1,1)).expand(2,4,3).mul(Tensor(1.0).reshape((1,1,1)).expand(2,4,3)).sum(-1), + forward_only=True + ) + a = [[1.,1.,1.,1.], [1.,1.,1.,1.]] + b = [1.,1.,1.,1.] + helper_test_op( + [], + lambda: torch.tensor(a).reshape((2,4,1)).expand(2,4,3).mul(torch.tensor(b).reshape((1,4,1)).expand(2,4,3)).sum([0,2]), + lambda: Tensor(a).reshape((2,4,1)).expand(2,4,3).mul(Tensor(b).reshape((1,4,1)).expand(2,4,3)).sum([0,2]), + forward_only=True + ) + helper_test_op( + [], + lambda: torch.ones((1,2)).matmul(torch.ones((2,3))), lambda: Tensor.ones((1,2)).dot(Tensor.ones((2,3))), + forward_only=True + ) + + def test_matmul_simple(self): + helper_test_op([(4), (4,4)], lambda x,y: x.matmul(y), Tensor.dot) + def test_matmul(self): + helper_test_op([(64), (64,99)], lambda x,y: x.matmul(y), Tensor.dot) + + @unittest.skipIf(IMAGE>0, "no batched matmul on images") + def test_matmul_batched(self): + helper_test_op([(3), (1,3,3,5)], lambda x,y: x.matmul(y), Tensor.dot) + + @unittest.skipIf(IMAGE>0, "no batched matmul on images") + def test_matmul_batched_vector(self): + helper_test_op([(4,3), (1,3,3,5)], lambda x,y: x.matmul(y), Tensor.dot) + def test_small_gemm(self): + helper_test_op([(8,8), (8,8)], lambda x,y: x.matmul(y), lambda x,y: x@y) + def test_9_gemm(self): + helper_test_op([(9,9), (9,9)], lambda x,y: x.matmul(y), lambda x,y: x@y) + def test_small_gemm_padded(self): + helper_test_op([(9,9), (9,9)], + lambda x,y: torch.nn.functional.pad(x, (0,7,0,7)).matmul(torch.nn.functional.pad(y, (0,7,0,7))), + lambda x,y: x.pad(((0,7),(0,7)))@y.pad(((0,7),(0,7)))) + def test_small_gemm_range(self): + helper_test_op(None, lambda x,y: x.matmul(y), lambda x,y: x@y, vals=[np.arange(0,64,dtype=np.float32).reshape(8,8), + np.arange(64,128,dtype=np.float32).reshape(8,8)]) + def test_small_gemm_eye(self): + helper_test_op(None, lambda x,y: x.matmul(y), lambda x,y: x@y, vals=[np.eye(8).astype(np.float32), np.eye(8).astype(np.float32)]) + @unittest.skipIf(CI and Device.DEFAULT in ["NV", "LLVM", "GPU", "CUDA"] or IMAGE, "not supported on these in CI/IMAGE") + def test_gemm_fp16(self): + helper_test_op([(64,64), (64,64)], lambda x,y: x.half().matmul(y.half()), atol=5e-3, rtol=5e-3) + def test_gemm(self): + helper_test_op([(64,64), (64,64)], lambda x,y: x.matmul(y)) + def test_big_gemm(self): + helper_test_op([(256,256), (256,256)], lambda x,y: x.matmul(y), atol=1e-4) + @unittest.skipIf(IMAGE>0, "no 0 in shape matmul on images") + def test_gemm_with_zeros_shape(self): + helper_test_op([(8,8), (8,0)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) + helper_test_op([(0,8), (8,8)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) + helper_test_op([(0,8), (8,0)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) + helper_test_op([(8,0), (0,8)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) + helper_test_op([(0,0), (0,0)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) + helper_test_op([(0), (0,8)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) + helper_test_op([(0), (0)], lambda x,y: x.matmul(y), Tensor.dot, atol=1e-7) + def test_broadcastdot(self): + helper_test_op([(10,45,65), (65,45)], lambda x,y: x @ y, Tensor.dot, atol=1e-4) + with self.assertRaises(RuntimeError): + a = Tensor(3.14) + b = Tensor.ones(3,3) + a @ b + def test_multidot(self): + helper_test_op([(10,45,65), (10,65,45)], lambda x,y: x @ y, Tensor.dot, atol=1e-4) + helper_test_op([(3,3,45,65), (3,3,65,45)], lambda x,y: x @ y, Tensor.dot, atol=1e-4) + + def test_sum_simple(self): + helper_test_op(None, lambda x: x.sum(), vals=[[1.,1.]]) + # NOTE: simple test for locals + # FORWARD_ONLY=1 DEBUG=4 python3 test/test_ops.py TestOps.test_sum_full + def test_sum_full(self): + helper_test_op([(16384)], lambda x: x.sum()) + def test_sum_relu(self): + helper_test_op([(3,4,5)], lambda x: x.relu().sum().relu()) + def test_sum_tiny(self): + helper_test_op([(4,2,2)], lambda x: x.sum(axis=(0,2))) + def test_sum(self): + helper_test_op([(45,3)], lambda x: x.sum()) + helper_test_op([(3,4,5,6)], lambda x: x.sum(axis=3)) + helper_test_op([(3,4,5,6)], lambda x: x.sum(axis=(1,3))) + helper_test_op([(3,4,5,6)], lambda x: x.sum(axis=(0,2))) + helper_test_op([(3,4,5,6)], lambda x: x.sum(axis=(1,2))) + helper_test_op([(3,4,5,6)], lambda x: x.sum(axis=1)) + helper_test_op([(3,4,5,6)], lambda x: x.sum(axis=1, keepdim=True)) + helper_test_op([()], lambda x: x.sum()) + helper_test_op([()], lambda x: x.sum(0)) + helper_test_op([()], lambda x: x.sum(-1)) + helper_test_op([()], lambda x: x.sum(())) + self.helper_test_exception([(3,4,5,6)], lambda x: x.sum(5), lambda x: x.sum(5), expected=IndexError) + self.helper_test_exception([()], lambda x: x.sum(1), lambda x: x.sum(1), expected=IndexError) + self.helper_test_exception([()], lambda x: x.sum((1,)), lambda x: x.sum((1,)), expected=IndexError) + + def test_sum_dtype_arg(self): + helper_test_op([(45,3)], lambda x: x.sum(), lambda x: x.sum(dtype=dtypes.float32)) + if is_dtype_supported(dtypes.float64): helper_test_op([(45,3)], lambda x: x.sum(dtype=torch.float64), lambda x: x.sum(dtype=dtypes.float64)) + + with self.assertRaises(AttributeError): Tensor([1.0, 2.0]).sum(dtype="") + + def test_sum_with_zeros_shape(self): + helper_test_op([(4, 0)], lambda x: x.sum(axis=(0,))) + helper_test_op([(4, 0)], lambda x: x.sum(axis=(1,))) + helper_test_op([(4, 0)], lambda x: x.sum(axis=(0,1))) + + def test_prod(self): + helper_test_op(None, lambda x: x.prod(), vals=[[1.0, 2.0, 3.0]]) + with Context(NOOPT=1): helper_test_op(None, lambda x: x.prod(), vals=[[1.0, 2.0, 3.0]]) + helper_test_op([(3,4,5,6)], lambda x: x.prod(dim=3), lambda x: x.prod(axis=3)) + helper_test_op([(3,4,5,6)], lambda x: x.prod(dim=1), lambda x: x.prod(axis=1)) + helper_test_op([(3,4,5,6)], lambda x: x.prod(dim=1, keepdim=True), lambda x: x.prod(axis=1, keepdim=True)) + helper_test_op([()], lambda x: x.prod()) + helper_test_op([()], lambda x: x.prod(0)) + helper_test_op([()], lambda x: x.prod(-1)) + + def test_prod_dtype_arg(self): + with self.assertRaises(AttributeError): Tensor([1.0, 2.0]).prod(dtype="") + + def test_min(self): + helper_test_op([(3,3)], lambda x: x.min()) + helper_test_op([(45,3)], lambda x: x.min()) + helper_test_op([(45,3)], lambda x: x.min().mul(0.5)) + helper_test_op([()], lambda x: x.min()) + + helper_test_op(None, lambda x: x.min(), forward_only=True, vals=[[0, -2**31]]) + helper_test_op(None, lambda x: x.min(), forward_only=True, vals=[[-2**31, 0]]) + helper_test_op(None, lambda x: x.min(), forward_only=True, vals=[[False, True]]) + helper_test_op(None, lambda x: x.min(), forward_only=True, vals=[[True, False]]) + + def test_max(self): + helper_test_op([(45,3)], lambda x: x.max()) + helper_test_op([(45,3)], lambda x: x.max().mul(0.5)) + helper_test_op(None, lambda x: x.max().mul(0.5), vals=[[[1.0,1.0,0.0,1.0]],]) + helper_test_op([(3,4,5,6)], lambda x: x.max(axis=1)[0], lambda x: x.max(axis=1)) + helper_test_op([()], lambda x: x.max()) + + helper_test_op(None, lambda x: x.max(), forward_only=True, vals=[[0, -2**31]]) + helper_test_op(None, lambda x: x.max(), forward_only=True, vals=[[-2**31, 0]]) + helper_test_op(None, lambda x: x.max(), forward_only=True, vals=[[False, True]]) + helper_test_op(None, lambda x: x.max(), forward_only=True, vals=[[True, False]]) + + @unittest.skipIf(Device.DEFAULT == "QCOM", "OpenCL fails to compile this (both on GPU(qcom)/QCOM backends)") + def test_any(self): + helper_test_op([(3,4,5,6)], lambda x: x.any(), forward_only=True) + helper_test_op(None, lambda x: x.any(), vals=[[True, True]], forward_only=True) + helper_test_op(None, lambda x: x.any(), vals=[[True, False]], forward_only=True) + helper_test_op(None, lambda x: x.any(), vals=[[False, False]], forward_only=True) + helper_test_op([()], lambda x: x.any(), forward_only=True) + def test_any_axis(self): + helper_test_op([(3,4,5,6)], lambda x: x.any(axis=(1,2)), forward_only=True) + def test_any_zero_axis(self): + helper_test_op([(1,0,3,0,5)], lambda x: x.any(axis=(1,3)), forward_only=True) + + @unittest.skipIf(Device.DEFAULT == "QCOM", "OpenCL fails to compile this (both on GPU(qcom)/QCOM backends)") + def test_all(self): + helper_test_op([(3,4,5,6)], lambda x: x.all(), forward_only=True) + helper_test_op(None, lambda x: x.all(), vals=[[True, True]], forward_only=True) + helper_test_op(None, lambda x: x.all(), vals=[[True, False]], forward_only=True) + helper_test_op(None, lambda x: x.all(), vals=[[False, False]], forward_only=True) + helper_test_op([()], lambda x: x.all(), forward_only=True) + def test_all_axis(self): + helper_test_op([(3,4,5,6)], lambda x: x.all(axis=(1,2)), forward_only=True) + def test_all_zero_axis(self): + helper_test_op([(1,0,3,0,5)], lambda x: x.all(axis=(1,3)), forward_only=True) + + def test_isclose(self): + helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x), forward_only=True) + helper_test_op([(3, 4, 5, 6), (3, 4, 5, 6)], lambda x,y: x.isclose(y), forward_only=True) + helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x, equal_nan=True), forward_only=True) + helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x + 1e-6), forward_only=True) + helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x + 1e-9), forward_only=True) + helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x + 1e-6, atol=0.0), forward_only=True) + helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x + 1e-9, atol=0.0), forward_only=True) + helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x + 1e-6, rtol=0.01), forward_only=True) + helper_test_op([(3, 4, 5, 6)], lambda x: x.isclose(x + 1e-9, rtol=0.01), forward_only=True) + helper_test_op(None, lambda x,y: x.isclose(y), vals=[[1e-7, 1e-8, 1e-9], [0.0, 0.0, 0.0]], forward_only=True) + + @unittest.skipIf(Device.DEFAULT == "WEBGPU" and CI, "isinf check of 'nan' fails on CI software-based vulkan") + def test_isclose_edge_cases(self): + for a in [math.inf, -math.inf, math.nan, 0.0]: + for b in [math.inf, -math.inf, math.nan, 0.0]: + helper_test_op(None, lambda x,y: x.isclose(y), vals=[[a], [b]], forward_only=True) + helper_test_op(None, lambda x,y: x.isclose(y, equal_nan=True), vals=[[a], [b]], forward_only=True) + + def test_mean(self): + helper_test_op([(3,4,5,6)], lambda x: x.mean()) + helper_test_op([()], lambda x: x.mean()) + def test_mean_axis(self): + helper_test_op([(3,4,5,6)], lambda x: x.mean(axis=(1,2))) + def test_mean_zero_axis(self): + helper_test_op([(1,0,3,0,5)], lambda x: x.mean(axis=(1,3))) + + def test_var(self): + helper_test_op([(15, 25, 35)], lambda x: x.var()) + helper_test_op([(15, 25, 35)], lambda x: x.var(correction=0)) + helper_test_op([(15, 25, 35)], lambda x: x.var(correction=5)) + # TODO: fix this + # helper_test_op([(10, 2)], lambda x: x.var(correction=50)) + def test_var_axis(self): + helper_test_op([(15, 25, 35)], lambda x: x.var(0)) + helper_test_op([(15, 25, 35)], lambda x: x.var(2)) + helper_test_op([(15, 25, 35)], lambda x: x.var([1, 2])) + helper_test_op([(15, 25, 35)], lambda x: x.var(0, correction=0)) + helper_test_op([(15, 25, 35)], lambda x: x.var(2, correction=0)) + helper_test_op([(15, 25, 35)], lambda x: x.var([1, 2], correction=0)) + def test_var_zero_in_axis(self): + with warnings.catch_warnings(): + warnings.filterwarnings("ignore", message="var\\(\\): degrees of freedom is <= 0") + helper_test_op([(1,0,3,0,5)], lambda x: x.var(axis=(1,3))) + helper_test_op([(1,0,3,0,5)], lambda x: x.var(axis=(1,3), correction=0)) + helper_test_op([(1,0,3,0,5)], lambda x: x.var(axis=(1,3), correction=5)) + def test_var_one_in_axis(self): + with warnings.catch_warnings(): + warnings.filterwarnings("ignore", message="var\\(\\): degrees of freedom is <= 0") + helper_test_op([(1,2,3,1,5)], lambda x: x.var(axis=(0,3))) + # TODO: fix backward + helper_test_op([(1,2,3,1,5)], lambda x: x.var(axis=(0,3), correction=5), forward_only=True) + helper_test_op([(1,2,3,1,5)], lambda x: x.var(axis=(0,4), correction=5), forward_only=True) + helper_test_op([(1,)], lambda x: x.var(axis=(0,), correction=0)) + helper_test_op([(1,2,3,1,5)], lambda x: x.var(axis=(0,3), correction=0)) + helper_test_op([(1,2,3,1,5)], lambda x: x.var(axis=(0,4))) + helper_test_op([(1,2,3,1,5)], lambda x: x.var(axis=(0,4), correction=0)) + def test_var_keepdim(self): + helper_test_op([(15, 25, 35)], lambda x: x.var(keepdim=True)) + helper_test_op([(15, 25, 35)], lambda x: x.var(0, keepdim=True, correction=0)) + + def test_std(self): + helper_test_op([(15, 25, 35)], lambda x: x.std()) + helper_test_op([(15, 25, 35)], lambda x: x.std(correction=0)) + helper_test_op([(15, 25, 35)], lambda x: x.std(correction=5)) + def test_std_axis(self): + helper_test_op([(15, 25, 35)], lambda x: x.std(0)) + helper_test_op([(15, 25, 35)], lambda x: x.std(2)) + helper_test_op([(15, 25, 35)], lambda x: x.std([1, 2])) + helper_test_op([(15, 25, 35)], lambda x: x.std(0, correction=0)) + helper_test_op([(15, 25, 35)], lambda x: x.std(2, correction=0)) + helper_test_op([(15, 25, 35)], lambda x: x.std([1, 2], correction=0)) + def test_std_zero_in_axis(self): + with warnings.catch_warnings(): + warnings.filterwarnings("ignore", message="std\\(\\): degrees of freedom is <= 0") + helper_test_op([(1,0,3,0,5)], lambda x: x.std(axis=(1,3))) + helper_test_op([(1,0,3,0,5)], lambda x: x.std(axis=(1,3), correction=0)) + helper_test_op([(1,0,3,0,5)], lambda x: x.std(axis=(1,3), correction=5)) + def test_std_one_in_axis(self): + with warnings.catch_warnings(): + warnings.filterwarnings("ignore", message="std\\(\\): degrees of freedom is <= 0") + helper_test_op([(1,2,3,1,5)], lambda x: x.std(axis=(0,3))) + helper_test_op([(1,2,3,1,5)], lambda x: x.std(axis=(0,3), correction=5)) + helper_test_op([(1,2,3,1,5)], lambda x: x.std(axis=(0,4), correction=5)) + # TODO: fix backward + helper_test_op([(1,)], lambda x: x.std(axis=(0,), correction=0), forward_only=True) + helper_test_op([(1,2,3,1,5)], lambda x: x.std(axis=(0,3), correction=0), forward_only=True) + helper_test_op([(1,2,3,1,5)], lambda x: x.std(axis=(0,4))) + helper_test_op([(1,2,3,1,5)], lambda x: x.std(axis=(0,4), correction=0)) + def test_std_keepdim(self): + helper_test_op([(15, 25, 35)], lambda x: x.std(keepdim=True)) + helper_test_op([(15, 25, 35)], lambda x: x.std(0, keepdim=True, correction=0)) + def test_std_mean(self): + helper_test_op([(15,25,35)], lambda x: torch.stack(torch.std_mean(x)), + lambda x: Tensor.stack(*x.std_mean())) + helper_test_op([(15,25,35)], lambda x: torch.stack(torch.std_mean(x, correction=5)), + lambda x: Tensor.stack(*x.std_mean(correction=5))) + helper_test_op([(15,25,35)], lambda x: torch.stack(torch.std_mean(x, keepdim=True, correction=0)), + lambda x: Tensor.stack(*x.std_mean(keepdim=True, correction=0))) + helper_test_op([(3,4,5,6)], lambda x: torch.stack(torch.std_mean(x, axis=(1,2))), + lambda x: Tensor.stack(*x.std_mean(axis=(1,2)))) + + @unittest.skip("TODO: this fails because of loaded nan in mul folding") + def test_std_mean_loaded_nan(self): + helper_test_op([(1,0,3,0,5)], lambda x: torch.stack(torch.std_mean(x, axis=(1,3))), + lambda x: Tensor.stack(*x.std_mean(axis=(1,3)))) + def test_softmax(self): + helper_test_op([(45,65)], torch.nn.Softmax(dim=1), Tensor.softmax, atol=1e-7, grad_atol=1e-7) + helper_test_op([(45)], torch.nn.Softmax(dim=0), Tensor.softmax, atol=1e-7, grad_atol=1e-7) + helper_test_op([()], torch.nn.Softmax(dim=0), Tensor.softmax, atol=1e-7, grad_atol=1e-7) + helper_test_op([()], torch.nn.Softmax(dim=-1), Tensor.softmax, atol=1e-7, grad_atol=1e-7) + def test_softmax_other_axis(self): + helper_test_op([(10,10,10)], lambda x: x.softmax(0), atol=1e-7, grad_atol=2e-7) + helper_test_op([(10,10,10)], lambda x: x.softmax(1), atol=1e-7, grad_atol=2e-7) + helper_test_op([(10,10,10)], lambda x: x.softmax(2), atol=1e-7, grad_atol=2e-7) + def test_softmax_argmax(self): + helper_test_op([(45,65)], lambda x: x.softmax(0).argmax().type(torch.int32), + lambda x: x.softmax(0).argmax(), forward_only=True, atol=1e-7, grad_atol=1e-7) + helper_test_op([(45,65)], lambda x: x.softmax(1).argmax().type(torch.int32), + lambda x: x.softmax(1).argmax(), forward_only=True, atol=1e-7, grad_atol=1e-7) + def test_log_softmax(self): + helper_test_op([(45,65)], torch.nn.LogSoftmax(dim=1), Tensor.log_softmax, atol=1e-7, grad_atol=1e-7) + helper_test_op([(45)], torch.nn.LogSoftmax(dim=0), Tensor.log_softmax, atol=1e-7, grad_atol=1e-7) + helper_test_op([()], torch.nn.LogSoftmax(dim=0), Tensor.log_softmax, atol=1e-7, grad_atol=1e-7) + helper_test_op([()], torch.nn.LogSoftmax(dim=-1), Tensor.log_softmax, atol=1e-7, grad_atol=1e-7) + def test_log_softmax_other_axis(self): + helper_test_op([(10,10,10)], lambda x: x.log_softmax(0), atol=1e-7, grad_atol=1e-7) + helper_test_op([(10,10,10)], lambda x: x.log_softmax(1), atol=1e-7, grad_atol=1e-7) + helper_test_op([(10,10,10)], lambda x: x.log_softmax(2), atol=1e-7, grad_atol=1e-7) + + def test_logsumexp(self): + helper_test_op([(45,65)], lambda x: torch.logsumexp(x, dim=0), lambda x: x.logsumexp(0), atol=1e-7, grad_atol=1e-7) + helper_test_op([(45,65)], lambda x: torch.logsumexp(x, dim=0, keepdim=True), lambda x: x.logsumexp(0, True), atol=1e-7, grad_atol=1e-7) + helper_test_op([(45,65)], lambda x: torch.logsumexp(x, dim=1), lambda x: x.logsumexp(1), atol=1e-7, grad_atol=1e-7) + helper_test_op([(6,6,6)], lambda x: torch.logsumexp(x, dim=2), lambda x: x.logsumexp(2), atol=1e-7, grad_atol=1e-7) + helper_test_op([(6,6,6,6)], lambda x: torch.logsumexp(x, dim=2), lambda x: x.logsumexp(2), atol=1e-7, grad_atol=1e-7) + helper_test_op([(6,6,6,6)], lambda x: torch.logsumexp(x, dim=3), lambda x: x.logsumexp(3), atol=1e-7, grad_atol=1e-7) + helper_test_op([(45)], lambda x: torch.logsumexp(x, dim=0), lambda x: x.logsumexp(0), atol=1e-7, grad_atol=1e-7) + helper_test_op([()], lambda x: torch.logsumexp(x, dim=0), lambda x: x.logsumexp(0), atol=1e-7, grad_atol=1e-7) + helper_test_op([()], lambda x: torch.logsumexp(x, dim=-1), lambda x: x.logsumexp(-1), atol=1e-7, grad_atol=1e-7) + + def test_logcumsumexp(self): + helper_test_op([(45,65)], lambda x: torch.logcumsumexp(x, dim=0), lambda x: x.logcumsumexp(0), atol=1e-7, grad_atol=1e-7) + helper_test_op([(45,65)], lambda x: torch.logcumsumexp(x, dim=1), lambda x: x.logcumsumexp(1), atol=1e-7, grad_atol=1e-7) + helper_test_op([(6,6,6)], lambda x: torch.logcumsumexp(x, dim=2), lambda x: x.logcumsumexp(2), atol=1e-7, grad_atol=1e-7) + helper_test_op([(6,6,6,6)], lambda x: torch.logcumsumexp(x, dim=2), lambda x: x.logcumsumexp(2), atol=1e-7, grad_atol=1e-7) + helper_test_op([(6,6,6,6)], lambda x: torch.logcumsumexp(x, dim=3), lambda x: x.logcumsumexp(3), atol=1e-7, grad_atol=1e-7) + helper_test_op([(45)], lambda x: torch.logcumsumexp(x, dim=0), lambda x: x.logcumsumexp(0), atol=1e-7, grad_atol=1e-7) + helper_test_op([()], lambda x: torch.logcumsumexp(x, dim=0), lambda x: x.logcumsumexp(0), atol=1e-7, grad_atol=1e-7) + helper_test_op([()], lambda x: torch.logcumsumexp(x, dim=0), lambda x: x.logcumsumexp(), atol=1e-7, grad_atol=1e-7) + helper_test_op([()], lambda x: torch.logcumsumexp(x, dim=-1), lambda x: x.logcumsumexp(-1), atol=1e-7, grad_atol=1e-7) + + def test_logcumsumexp_numerical(self): + helper_test_op(None, lambda x: torch.logcumsumexp(x, dim=0), lambda x: x.logcumsumexp(), atol=1e-7, grad_atol=1e-7, vals=[[0.0, 100.0]]) + + def test_sinh(self): + helper_test_op([(45,65)], lambda x: x.sinh(), grad_atol=1e-6) + # TODO: backward nan instead of inf + helper_test_op([(45,65)], lambda x: x.sinh(), grad_atol=1e-6, low=-300, high=-297, forward_only=True) + helper_test_op([(45,65)], lambda x: x.sinh(), grad_atol=1e-6, low=300, high=303, forward_only=True) + def test_cosh(self): + helper_test_op([(45,65)], lambda x: x.cosh(), grad_atol=1e-6) + # TODO: backward nan instead of inf + helper_test_op([(45,65)], lambda x: x.cosh(), grad_atol=1e-6, low=-300, high=-297, forward_only=True) + helper_test_op([(45,65)], lambda x: x.cosh(), grad_atol=1e-6, low=300, high=303, forward_only=True) + def test_tanh(self): + helper_test_op([(45,65)], lambda x: x.tanh(), grad_atol=1e-6) + def test_tanh_extreme(self): + helper_test_op([(45,65)], lambda x: x.tanh(), grad_atol=1e-6, low=-300, high=-297) + helper_test_op([(45,65)], lambda x: x.tanh(), grad_atol=1e-6, low=300, high=303) + def test_hardtanh(self): + for val in range(10, 30, 5): + helper_test_op([(45,65)], lambda x: torch.nn.functional.hardtanh(x, -val, val), lambda x: x.hardtanh(-val, val), grad_atol=1e-6) + helper_test_op([()], lambda x: torch.nn.functional.hardtanh(x, -val, val), lambda x: x.hardtanh(-val, val), grad_atol=1e-6) + def test_asinh(self): + helper_test_op([(45,65)], lambda x: x.asinh(), grad_atol=1e-6) + # TODO: this one has larger tol? + helper_test_op([(45,65)], lambda x: x.asinh(), atol=1e-2, rtol=2e-2, grad_rtol=2e-2, low=-300, high=-297) + helper_test_op([(45,65)], lambda x: x.asinh(), grad_atol=1e-6, low=300, high=303) + def test_acosh(self): + helper_test_op([(45,65)], lambda x: x.acosh(), grad_atol=1e-6) + helper_test_op([(45,65)], lambda x: x.acosh(), grad_atol=1e-3, grad_rtol=1e-2, low=-300, high=-297) + helper_test_op([(45,65)], lambda x: x.acosh(), grad_atol=1e-6, low=300, high=303) + def test_atanh(self): + helper_test_op([(45,65)], lambda x: x.atanh(), grad_atol=1e-6) + helper_test_op([(45,65)], lambda x: x.atanh(), grad_atol=1e-6, low=-300, high=-297) + helper_test_op([(45,65)], lambda x: x.atanh(), grad_atol=1e-6, low=300, high=303) + + def test_topo_sort(self): + helper_test_op([(45,65)], lambda x: (x+x)*x, grad_atol=1e-6) + helper_test_op([()], lambda x: (x+x)*x, grad_atol=1e-6) + + def test_flip_eye_crash(self): + helper_test_op([], lambda: (torch.eye(10)@torch.eye(10).flip(0)), + lambda: (Tensor.eye(10)@Tensor.eye(10).flip(0)), forward_only=True) + + def test_broadcast_full(self): + for torch_op, tinygrad_op in [(torch.add, Tensor.add), (torch.sub, Tensor.sub), (torch.mul, Tensor.mul), + (torch.div, Tensor.div), (torch.pow, Tensor.pow)]: + for shapes in [((5,13,24,16), (5,1,24,1)), ((1,3,1,7,1), (2,1,5,1,8))]: + with self.subTest(op=torch_op.__name__, shapes=shapes): + if tinygrad_op != Tensor.pow: + helper_test_op(shapes, torch_op, tinygrad_op) + else: + helper_test_op(shapes, torch_op, tinygrad_op, low=0, high=3) + + def test_broadcast_simple(self): + helper_test_op([(45,65), (45,1)], lambda x,y: x/y) + helper_test_op([(45,65), ()], lambda x,y: x/y) + + def test_broadcast_partial(self): + for torch_op, tinygrad_op in [(torch.add, Tensor.add), (torch.sub, Tensor.sub), (torch.mul, Tensor.mul), + (torch.div, Tensor.div), (torch.pow, Tensor.pow)]: + for shapes in [((1,32,32,32), (1,32,1,1)), ((5,13,24,16,2), (1,13,24,1,1)), + ((4,1), (4,5)), ((1,4), (5,4))]: + with self.subTest(op=torch_op.__name__, shapes=shapes): + # NOTE: ANE backwards? + if tinygrad_op != Tensor.pow: + helper_test_op(shapes, torch_op, tinygrad_op) + else: + helper_test_op(shapes, torch_op, tinygrad_op, low=0, high=3) + + def test_slice_in_bounds_1dim(self): + helper_test_op([(3)], lambda x: x[1:3]) + helper_test_op([(3)], lambda x: x[0:2]) + helper_test_op([(3)], lambda x: x[-2:2]) + + def test_slice_on_0dim_tensor(self): + helper_test_op([()], lambda x: x[None]) + + with self.assertRaises(IndexError): + a = Tensor(3.14) + a[0] + + def test_slice_int_indexing(self): + helper_test_op([(3)], lambda x: x[0]) + helper_test_op([(3)], lambda x: x[2]) + helper_test_op([(3)], lambda x: x[-1]) + helper_test_op([(3)], lambda x: x[-3]) + helper_test_op([(10,10)], lambda x: x[1]) + helper_test_op([(3,3,3)], lambda x: x[1,1,1]) + + def test_slice_in_bounds_multidim(self): + helper_test_op([(3,3,3)], lambda x: x[1:2]) + helper_test_op([(3,3,3)], lambda x: x[1:2, 2]) + helper_test_op([(3,3,3)], lambda x: x[1:2, 1:2]) + helper_test_op([(3,3,3)], lambda x: x[1:2, 1:2, 0:-1]) + + def test_slice_with_none(self): + helper_test_op([(3,3,3)], lambda x: x[None]) + helper_test_op([(3,3,3)], lambda x: x[1:2, None]) + helper_test_op([(3,3,3)], lambda x: x[1:2, None, 1:2]) + helper_test_op([(3,3,3)], lambda x: x[1:2, 1:2, None, -1]) + helper_test_op([(3,3,3)], lambda x: x[None, None, 1, None, 2, 0:2]) + + def test_slice_with_const_tensor(self): + t = Tensor.zeros(1, dtype=dtypes.int) + helper_test_op([(3,3,3)], lambda x: x[:, [0], :], lambda x: x[:, t, :]) + helper_test_op([(3,3,3)], lambda x: x[:, [0], :], lambda x: x[:, t.contiguous(), :]) + + def test_slice_one_endpoint_out_of_bounds(self): + helper_test_op([(3,3,3)], lambda x: x[0:4]) + helper_test_op([(3,3,3)], lambda x: x[-6:4]) + helper_test_op([(3,3,3)], lambda x: x[1:50]) + helper_test_op([(3,3,3)], lambda x: x[1:50, 1:2, -1]) + + def test_slice_stride_gt_one(self): + helper_test_op([(7,5,10)], lambda x: x[::2, ::3, ::4]) + helper_test_op([(7,5,10)], lambda x: x[1:5:2, ::3, ::4]) + helper_test_op([(7,5,10)], lambda x: x[1:5:2, 3, ::4]) + helper_test_op([(7,5,10)], lambda x: x[1:5:2, None, None, 3, None, ::4]) + + def test_slice_negative_strides(self): + # Torch doesn't support slicing with negative steps + a = np.random.randn(10, 10, 10).astype(np.float32) + t = Tensor(a) + np.testing.assert_allclose(a[::-1], t[::-1].numpy()) + np.testing.assert_allclose(a[::-2], t[::-2].numpy()) + np.testing.assert_allclose(a[:, 2:0:-1], t[:, 2:0:-1].numpy()) + np.testing.assert_allclose(a[:, 2:0:-1, 3:1:-2], t[:, 2:0:-1, 3:1:-2].numpy()) + np.testing.assert_allclose(a[4:0:-3, 2:0:-1, -1:-5:-2], t[4:0:-3, 2:0:-1, -1:-5:-2].numpy()) + np.testing.assert_allclose(a[2:5:-1, :, :], t[2:5:-1, :, :].numpy()) # shape = (0, 10, 10) + np.testing.assert_allclose(a[:, 2:5:-1, :], t[:, 2:5:-1, :].numpy()) # shape = (0, 10, 10) + np.testing.assert_allclose(a[:, :, 2:5:-1], t[:, :, 2:5:-1].numpy()) # shape = (0, 10, 10) + + def test_slice_both_endpoints_out_of_bounds(self): + helper_test_op([(3,3,3)], lambda x: x[5:10]) + helper_test_op([(3,3,3)], lambda x: x[-15:-7]) + + def test_slice_start_gt_end(self): + helper_test_op([(3,3,3)], lambda x: x[-2:2]) + helper_test_op([(3,3,3)], lambda x: x[-2:-5]) + + def test_slice_empty(self): + helper_test_op([(10,10)], lambda x: x[1:1]) + + def test_slice_zero_in_shape(self): + helper_test_op([(10,10)], lambda x: x[1:1]) # x.shape = (0, 10) + helper_test_op([(3,3,3)], lambda x: x[-2:-5]) # x.shape = (0, 3, 3) + + def test_slice_errors(self): + a = Tensor.ones(4, 3) + b = Tensor(2) + with self.assertRaisesRegex(IndexError, "too many"): a[1, 77, 77, 77] # IndexError: (finds too many indices before the out of bounds) + with self.assertRaisesRegex(IndexError, "out of bounds"): a[1, 3] # IndexError: (out of bounds). + with self.assertRaisesRegex(IndexError, "out of bounds"): a[1, -4] + with self.assertRaisesRegex(IndexError, "single ellipsis"): a[..., ...] # IndexError: only single ellipsis + with self.assertRaises(ValueError): a[::0, 1] # no 0 strides + with self.assertRaises(TypeError): a[:Tensor([3]), 1] # Tensor can't be used as a slice parameter + with self.assertRaises(IndexError): b[:] # slice cannot be applied to a 0-dim tensor + + def test_slice_ellipsis(self): + helper_test_op([(3,3,3,3)], lambda x: x[..., 0]) + helper_test_op([(3,3,3,3)], lambda x: x[0, ...]) + helper_test_op([(3,3,3,3)], lambda x: x[0, ..., 0]) + helper_test_op([(3,3,3,3)], lambda x: x[0:3, ..., 2:3]) + helper_test_op([(3,3,3,3)], lambda x: x[None, 0:3, ..., 0, None]) + + # this was the failure in llama early realizing freqs_cis + def test_double_slice(self): + helper_test_op([(4,4)], lambda x: x[:, 1:2][1:2]) + helper_test_op([(4,4)], lambda x: x[1:3][1:2]) + helper_test_op([(4,4)], lambda x: x[:, 1:2][0:1]) + helper_test_op([(4,4)], lambda x: x[:, 1:2][:, 0:1]) + + def test_pad(self): + helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (1,2,3,4)), lambda x: x.pad(padding=(1,2,3,4))) + helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (-1,2,-3,4)), lambda x: x.pad(padding=(-1,2,-3,4))) + helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (1,2,3,4), value=5), lambda x: x.pad(padding=(1,2,3,4),value=5)) + helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (-1,2,-3,4), value=5), lambda x: x.pad(padding=(-1,2,-3,4),value=5)) + helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (1,2,3,4), value=math.inf), lambda x: x.pad(padding=(1,2,3,4),value=math.inf)) + helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (-1,2,-3,4), value=-math.inf), + lambda x: x.pad(padding=(-1,2,-3,4),value=-math.inf)) + helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x, (1,2,3,4)),lambda x: x.pad(((3,4),(1,2)))) + helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x, (-1,2,-3,4)), lambda x: x.pad(((-3,4), (-1,2)))) + helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x, (1,2,3,4), value=5), lambda x: x.pad(((3,4), (1,2)), value=5)) + helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x, (0,0,3,4), value=1), lambda x: x.pad(((3,4), None), value=1)) + helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x, (0,0,0,0), value=1), lambda x: x.pad((None, None), value=1)) + # raise error for uneven pads + self.helper_test_exception([(3,3)], lambda x: torch.nn.functional.pad(x, (2,0,2)), lambda x: x.pad((2,0,2)), + expected=(RuntimeError, ValueError)) + # raise error for too many or too little pads + self.helper_test_exception([(3,3)], lambda x: torch.nn.functional.pad(x, (0,0,0,0,1,0,3,0)), lambda x: x.pad((0,0,0,0,1,0,3,0)), + expected=(RuntimeError, ValueError)) + # raise error for mode string typo + self.helper_test_exception([(3,3,3)], lambda x: torch.nn.functional.pad(x, (3,0), mode="typo"), lambda x: x.pad((3,0), mode="typo"), + expected=NotImplementedError) + x = Tensor.ones(3,3) + with self.assertRaises(ValueError): x.pad((None,(0,1),(3,0))) + with self.assertRaises(ValueError): x.pad(((0,1),)) + + def test_pad_reflect_mode(self): + helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (0,2,3,2), mode="reflect"), lambda x: x.pad((0,2,3,2), mode="reflect")) + helper_test_op([(5,5,5)], lambda x: torch.nn.functional.pad(x, (0,2), mode="reflect"), lambda x: x.pad((0,2), mode="reflect")) + helper_test_op([(1,1,5,5,5)], lambda x: torch.nn.functional.pad(x, (1,2,3,4,1,2), mode="reflect"), + lambda x: x.pad((1,2,3,4,1,2), mode="reflect")) + helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (-1,2,2,-1), mode="reflect"), lambda x: x.pad((-1,2,2,-1), mode="reflect")) + helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (3,-3,0,-3), mode="reflect"), lambda x: x.pad((3,-3,0,-3), mode="reflect")) + helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (3,-5,1,-5), mode="reflect"), lambda x: x.pad((3,-5,1,-5), mode="reflect")) + helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (0,0,0,-5), mode="reflect"), lambda x: x.pad((0,0,0,-5), mode="reflect")) + + # max pad size for reflect is exactly once: pad < input size + helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (4,4,0,4), mode="reflect"), lambda x:x.pad((4,4,0,4),mode="reflect")) + # raise error for relfection padding when: pad >= input size + self.helper_test_exception([(1,1,5,5)], + lambda x: torch.nn.functional.pad(x, (3,5,0,0),mode="reflect"), lambda x: x.pad((3,5,0,0),mode="reflect"), + expected=(RuntimeError, ValueError)) + + def test_pad_replicate_mode(self): + helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (0,2,3,2), mode="replicate"), lambda x: x.pad((0,2,3,2), mode="replicate")) + helper_test_op([(5,5,5)], lambda x: torch.nn.functional.pad(x, (0,2), mode="replicate"), lambda x: x.pad((0,2), mode="replicate")) + helper_test_op([(1,1,5,5,5)], lambda x: torch.nn.functional.pad(x, (1,2,3,4,1,2),mode="replicate"),lambda x:x.pad((1,2,3,4,1,2),mode="replicate")) + helper_test_op([(3,3,3,3)], lambda x: torch.nn.functional.pad(x, (-1,2,2,-1), mode="replicate"), lambda x: x.pad((-1,2,2,-1), mode="replicate")) + helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (3,-3,0,-3), mode="replicate"), lambda x: x.pad((3,-3,0,-3), mode="replicate")) + helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (3,-5,1,-5), mode="replicate"), lambda x: x.pad((3,-5,1,-5), mode="replicate")) + helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (0,0,0,-5), mode="replicate"), lambda x: x.pad((0,0,0,-5), mode="replicate")) + + # no max pad sizes for replicate + helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (3,11,0,30), mode="replicate"), lambda x: x.pad((3,11,0,30), mode="replicate")) + + def test_pad_circular_mode(self): + helper_test_op([(1,1,5,5)], lambda x: torch.nn.functional.pad(x, (0,2,3,2), mode="circular"), lambda x: x.pad((0,2,3,2), mode="circular")) + helper_test_op([(5,5,5)], lambda x: torch.nn.functional.pad(x, (0,2), mode="circular"), lambda x: x.pad((0,2), mode="circular")) + helper_test_op([(1,1,5,5,5)], lambda x: torch.nn.functional.pad(x, (1,2,3,5,1,2),mode="circular"),lambda x:x.pad((1,2,3,5,1,2),mode="circular")) + # circular pad cannot wrap around more than once + self.helper_test_exception([(1,1,5,5)], + lambda x: torch.nn.functional.pad(x, (3,6,0,0), mode="circular"), lambda x: x.pad((3,6,0,0), mode="circular"), + expected=(RuntimeError, ValueError)) + with self.assertRaises(NotImplementedError): + # negative pads with circular pads is not supported + Tensor.randn(1,1,5,5).pad((3,-5,1,-5), mode="circular") + + def test_pad_reshape(self): + helper_test_op([(1, 2)], + lambda x: torch.nn.functional.pad(x, (0, 1, 1, 0)).reshape((3, 2)), + lambda x: x.pad((0, 1, 1, 0)).reshape((3, 2))) + helper_test_op([(1, 2)], + lambda x: torch.nn.functional.pad(x, (0, 2, 1, 1)).reshape((4, 3)), + lambda x: x.pad((0, 2, 1, 1)).reshape((4, 3))) + helper_test_op([(1, 1, 1, 2)], + lambda x: torch.nn.functional.pad(x, (0, 4, 2, 2, 1, 2, 0, 2)).reshape((4, 3, 6, 5)), + lambda x: x.pad(((0, 2), (1, 2), (2, 2), (0, 4))).reshape((4, 3, 6, 5))) + + def test_pad_slice(self): + for value in 0., 3.456: + helper_test_op([(1)], lambda x: torch.nn.functional.pad(x,(1,0), value=value)[0], lambda x: x.pad(((1,0),), value=value)[0]) + helper_test_op([(4)], lambda x: torch.nn.functional.pad(x,(1,0), value=value)[0], lambda x: x.pad(((1,0),), value=value)[0]) + helper_test_op([(4)], lambda x: torch.nn.functional.pad(x,(3,0), value=value)[0:1], lambda x: x.pad(((3,0),), value=value)[0:1]) + helper_test_op([(4)], lambda x: torch.nn.functional.pad(x,(0,3), value=value)[6], lambda x: x.pad(((0,3),), value=value)[6]) + helper_test_op([(4)], lambda x: torch.nn.functional.pad(x,(0,3), value=value)[4:6], lambda x: x.pad(((0,3),), value=value)[4:6]) + helper_test_op([(5,5)], lambda x: torch.nn.functional.pad(x,(0,0,1,0), value=value)[0], lambda x: x.pad(((1,0),(0,0)), value=value)[0]) + helper_test_op([(2,2)], lambda x: torch.nn.functional.pad(x,(0,1,0,0), value=value)[0,2], lambda x: x.pad(((0,0),(0,1)), value=value)[0,2]) + helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(0,0,1,0), value=value)[0,2], lambda x: x.pad(((1,0),(0,0)), value=value)[0,2]) + helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(0,0,0,2), value=value)[5], lambda x: x.pad(((0,2),(0,0)), value=value)[5]) + helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(0,0,0,2), value=value)[3:5], lambda x: x.pad(((0,2),(0,0)), value=value)[3:5]) + helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(3,0,0,0), value=value)[1,0], lambda x: x.pad(((0,0),(3,0)), value=value)[1,0]) + helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(3,0,0,0), value=value)[1,0:4], lambda x: x.pad(((0,0),(3,0)), value=value)[1,0:4]) + helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(3,4,1,2), value=value)[0], lambda x: x.pad(((1,2),(3,4)), value=value)[0]) + helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(3,4,1,2), value=value)[:,1], lambda x: x.pad(((1,2),(3,4)), value=value)[:,1]) + helper_test_op([(4,4)], lambda x: torch.nn.functional.pad(x,(3,4,1,2), value=value)[:,4], lambda x: x.pad(((1,2),(3,4)), value=value)[:,4]) + helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x,(0,3,0,0), value=value)[:,4:6], lambda x: x.pad(((0,0),(0,3)), value=value)[:,4:6]) + helper_test_op([(3,3)], lambda x: torch.nn.functional.pad(x,(0,1,3,2), value=value)[0:2,:], lambda x: x.pad(((3,2),(0,1)), value=value)[0:2,:]) + helper_test_op([(3,3,3)], lambda x: torch.nn.functional.pad(x,(1,1,0,1,3,2), value=value)[0:2,:,:], + lambda x: x.pad(((3,2),(0,1),(1,1)), value=value)[0:2,:,:]) + helper_test_op([(3,3,3)], lambda x: torch.nn.functional.pad(x,(1,1,0,1,3,2), value=value)[2:4,:,:], + lambda x: x.pad(((3,2),(0,1),(1,1)), value=value)[2:4,:,:]) + + def test_stack_slice(self): + helper_test_op([(4)], lambda x: torch.stack([x for i in range(3)])[0,:], lambda x: Tensor.stack(*[x for i in range(3)])[0,:]) + helper_test_op([(5)], lambda x: torch.stack([x for i in range(3)])[0,0], lambda x: Tensor.stack(*[x for i in range(3)])[0,0]) + helper_test_op([(4,4)], lambda x: torch.stack([x for i in range(4)])[3], lambda x: Tensor.stack(*[x for i in range(4)])[3]) + + def test_transpose(self): + helper_test_op([(3,3)], lambda x: x.T) + helper_test_op([(3,3,3)], lambda x: x.transpose(1,2)) + helper_test_op([(3,3,3)], lambda x: x.transpose(0,2)) + + def test_permute(self): + helper_test_op([(1,2,3,4)], lambda x: x.permute((3,0,2,1))) + helper_test_op([(3,4,5,6)], lambda x: x.permute((3,2,1,0))) + helper_test_op([(3,4,5,6)], lambda x: x.permute((-2,-1,1,0))) + helper_test_op([()], lambda x: x.permute(())) + self.helper_test_exception([(3,4,5,6)], lambda x: x.permute((0,2)), lambda x: x.permute((0,2)), expected=RuntimeError) + self.helper_test_exception([(3,4,5,6)], lambda x: x.permute((0,1,2,3,3,3)), lambda x: x.permute((0,1,2,3,3,3)), expected=RuntimeError) + self.helper_test_exception([(3,4,5,6)], lambda x: x.permute((0,0,1,2,3)), lambda x: x.permute((0,0,1,2,3)), expected=RuntimeError) + + def test_reshape(self): + helper_test_op([(4,3,6,6)], lambda x: x.reshape((12,6,6))) + helper_test_op([(4,3,6,6)], lambda x: x.reshape((-1,3,6,6))) + helper_test_op([(4,3,6,6)], lambda x: x.reshape((-1,1,6,6))) + helper_test_op([(4,3,6,6)], lambda x: x.reshape((4,3,6,6)), lambda x: x.reshape((None,None,6,6))) + helper_test_op([()], lambda x: x.reshape(())) + helper_test_op([(1,)], lambda x: x.reshape(())) + helper_test_op([()], lambda x: x.reshape((1,))) + helper_test_op([()], lambda x: x.reshape((1,1,1))) + self.helper_test_exception([(3,4)], lambda x: x.reshape((-1,-1,2)), lambda x: x.reshape((-1,-1,2)), expected=RuntimeError) + self.helper_test_exception([(3,4)], lambda x: x.reshape((-1,-1,-1,2)), lambda x: x.reshape((-1,-1,-1,2)), expected=RuntimeError) + + with self.assertRaises(ValueError): + x = Tensor.ones((4,3,6,6)) + x.reshape([]) + + def test_view(self): + helper_test_op([(4,3,6,6)], lambda x: x.view((12,6,6))) + helper_test_op([(4,3,6,6)], lambda x: x.view((-1,3,6,6))) + helper_test_op([(6,)], lambda x: x.view(2, 3)) + helper_test_op([(6,1)], lambda x: x.view([2, 3])) + helper_test_op([(1,6)], lambda x: x.view((3, 2))) + helper_test_op([(3,2)], lambda x: x.view((2, 3))) + helper_test_op([(3,2)], lambda x: x.view(6)) + + def test_flip(self): + helper_test_op([(4,3,6,6)], lambda x: x.flip((0,))) + helper_test_op([(4,3,6,6)], lambda x: x.flip((0,1))) + helper_test_op([(4,3,6,6)], lambda x: x.flip((0,1,3))) + helper_test_op([(4,3,6,6)], lambda x: x.flip((3,))) + helper_test_op([(4,3,6,6)], lambda x: x.flip((0,1,3)).flip(0)) + helper_test_op([(4,3,6,6)], lambda x: x.flip((-1,))) + helper_test_op([()], lambda x: x.flip(())) + helper_test_op([(1,)], lambda x: x.flip(())) + helper_test_op([(4,3,6,6)], lambda x: x.flip(())) + self.helper_test_exception([(3,4)], lambda x: x.flip((0,0)), lambda x: x.flip((0,0)), expected=RuntimeError) + self.helper_test_exception([(3,4)], lambda x: x.flip((1,1)), lambda x: x.flip((1,1)), expected=RuntimeError) + self.helper_test_exception([(3,4)], lambda x: x.flip((1,-1)), lambda x: x.flip((1,-1)), expected=RuntimeError) + + def test_squeeze(self): + helper_test_op([(1,3,6,6)], lambda x: x.squeeze(0)) + helper_test_op([(4,3,1,6)], lambda x: x.squeeze(1)) + helper_test_op([(4,3,6,6)], lambda x: x.squeeze(3)) + self.helper_test_exception([(4,3,6,6)], lambda x: torch.squeeze(x, 50), lambda x: x.squeeze(dim=50), expected=IndexError) + self.helper_test_exception([(4,3,6,6)], lambda x: torch.squeeze(x, -50), lambda x: x.squeeze(dim=-50), expected=IndexError) + helper_test_op([(4,3,6,1)], lambda x: x.squeeze(-1)) + helper_test_op([(4,3,6,6)], lambda x: x.squeeze()) + helper_test_op([(1,3,6,6)], lambda x: x.squeeze()) + helper_test_op([(2,3,1)], lambda x: x.squeeze()) + helper_test_op([()], lambda x: x.squeeze(-1)) + helper_test_op([()], lambda x: x.squeeze(0)) + helper_test_op([()], lambda x: x.squeeze()) + self.helper_test_exception([()], lambda x: torch.squeeze(x, 10), lambda x: x.squeeze(dim=10), expected=IndexError) + self.helper_test_exception([()], lambda x: torch.squeeze(x, 1), lambda x: x.squeeze(dim=1), expected=IndexError) + self.helper_test_exception([()], lambda x: torch.squeeze(x, -2), lambda x: x.squeeze(dim=-2), expected=IndexError) + + def test_unsqueeze(self): + helper_test_op([(4,3,6,6)], lambda x: x.unsqueeze(0)) + helper_test_op([(4,3,6,6)], lambda x: x.unsqueeze(4)) + helper_test_op([(4,3,6,6)], lambda x: x.unsqueeze(-1)) + helper_test_op([(4,3,6,6)], lambda x: x.unsqueeze(-3)) + helper_test_op([()], lambda x: x.unsqueeze(0)) + + def test_flatten(self): + for axis in range(3): + helper_test_op([(4,3,6,6)], lambda x: x.flatten(start_dim=axis)) + for axis in range(3): + helper_test_op([(4,3,6,6)], lambda x: x.flatten(end_dim=axis)) + helper_test_op([(4,3,6,6)], lambda x: x.flatten(start_dim=1, end_dim=3)) + helper_test_op([()], lambda x: x.flatten()) + helper_test_op([(1,)], lambda x: x.flatten()) + + def test_unflatten(self): + helper_test_op([(4,3,6,6)], lambda x: x.unflatten(0, (2, 2))) + helper_test_op([(4,3,6,6)], lambda x: x.unflatten(3, (3, 2))) + helper_test_op([(4,3,6,6)], lambda x: x.unflatten(-1, (3, 2, 1))) + + def test_roll(self): + helper_test_op([(2, 4)], lambda x: torch.roll(x, 1, 0), lambda x: x.roll(1, 0)) + helper_test_op([(2, 4)], lambda x: torch.roll(x, -1, 0), lambda x: x.roll(-1, 0)) + helper_test_op([(2, 4)], lambda x: torch.roll(x, shifts=(2, 1), dims=(0, 1)), lambda x: x.roll(shifts=(2, 1), dims=(0, 1))) + helper_test_op([(2, 4, 6)], lambda x: torch.roll(x, 1, 0), lambda x: x.roll(1, 0)) + helper_test_op([(2, 4)], lambda x: torch.roll(x, 1, -1), lambda x: x.roll(1, -1)) + helper_test_op([(2, 4)], lambda x: torch.roll(x, -1, -1), lambda x: x.roll(-1, -1)) + helper_test_op([(2, 4)], lambda x: torch.roll(x, 5, 0), lambda x: x.roll(5, 0)) + helper_test_op([(2, 4)], lambda x: torch.roll(x, -5, 0), lambda x: x.roll(-5, 0)) + helper_test_op([(2, 4, 6)], lambda x: torch.roll(x, shifts=(2, -3), dims=(0, 2)), lambda x: x.roll(shifts=(2, -3), dims=(0, 2))) + helper_test_op([(2, 4, 6)], lambda x: torch.roll(x, shifts=(1, 2, -1), dims=(0, 1, 2)), lambda x: x.roll(shifts=(1, 2, -1), dims=(0, 1, 2))) + helper_test_op([(2, 4)], lambda x: torch.roll(x, 0, 0), lambda x: x.roll(0, 0)) + helper_test_op([(2, 4, 6)], lambda x: torch.roll(x, shifts=(0, 0), dims=(0, 1)), lambda x: x.roll(shifts=(0, 0), dims=(0, 1))) + helper_test_op([(2, 4, 6)], lambda x: torch.roll(x, shifts=(0, 2), dims=(0, 1)), lambda x: x.roll(shifts=(0, 2), dims=(0, 1))) + + def test_detach(self): + helper_test_op([(4,3,6,6)], lambda x: x.detach(), forward_only=True) + helper_test_op([()], lambda x: x.detach(), forward_only=True) + + def test_expand(self): + helper_test_op([(4,3,1,6)], lambda x: x.expand((4,3,2,6))) + helper_test_op([(1,1,1,1)], lambda x: x.expand((4,3,2,6))) + helper_test_op([(4,3,1,6)], lambda x: x.expand((6,1,4,3,2,6))) + helper_test_op([(4,3,1,6)], lambda x: x.expand((0,1,4,3,2,6))) + helper_test_op([(4,3,1,6)], lambda x: x.expand((4,3,0,6))) + helper_test_op([()], lambda x: x.expand((4,3,2,6))) + helper_test_op([()], lambda x: x.expand([])) + + with self.assertRaises((ValueError, RuntimeError)): Tensor.ones(4,3,1,6).expand(4,1,1,6) + with self.assertRaises((ValueError, RuntimeError)): Tensor.ones(4,3,1,6).expand(4,6,1,6) + with self.assertRaises((ValueError, RuntimeError)): Tensor.ones(4,3,1,6).expand(3,1,6) + with self.assertRaises((ValueError, RuntimeError)): Tensor.ones(4,3,2,6).expand(4,3,0,6) + + @unittest.skip("very slow") + def test_sd_big_conv(self): + # internal shape (1, 1, 512, 62, 62, 512, 3, 3) overflows a int + helper_test_op([(1,256,64,64), (512,256,3,3)], + lambda x,w: torch.nn.functional.conv2d(x, w), + lambda x,w: x.conv2d(w), atol=1e-3) + + @unittest.skip("slow") + def test_large_bs_conv(self): + # large batch size can cause OpenCL image to exceed max image height on macOS + # (or cause the conv kernel to overflow short sampling coords) + helper_test_op([(4096,3,3,3), (1,3,3,3)], + lambda x,w: torch.nn.functional.conv2d(x, w), + lambda x,w: x.conv2d(w), atol=1e-3) + + @unittest.skip("slow") + def test_large_ic_conv(self): + # large input channel count can cause OpenCL image to exceed max image width on macOS + helper_test_op([(1,2048,3,3), (1,2048,3,3)], + lambda x,w: torch.nn.functional.conv2d(x, w), + lambda x,w: x.conv2d(w)) + + def test_biased_conv2d(self): + C = 8 + helper_test_op([(1,C,5,5), (C,C,1,1), (C,)], + lambda x,w,b: torch.nn.functional.conv2d(torch.nn.functional.conv2d(x,w,b).relu(),w,b), + lambda x,w,b: Tensor.conv2d(x,w,b).relu().conv2d(w,b)) + + def test_simple_conv2d(self): + helper_test_op([(1,4,9,9), (4,4,3,3)], + lambda x,w: torch.nn.functional.conv2d(x,w), + lambda x,w: Tensor.conv2d(x,w), grad_rtol=1e-5) + + def test_simple_conv2d_bias(self): + helper_test_op([(1,4,9,9), (4,4,3,3), (4,)], + lambda x,w,b: torch.nn.functional.conv2d(x,w,b), + lambda x,w,b: Tensor.conv2d(x,w,b), grad_rtol=1e-5) + + @unittest.skipIf(IMAGE>0, "no conv3d on images") + def test_simple_conv3d(self): + helper_test_op([(1,4,9,9,9), (4,4,3,3,3)], + lambda x,w: torch.nn.functional.conv3d(x,w), + lambda x,w: Tensor.conv2d(x,w), grad_rtol=1e-5) + + @unittest.skipIf(IMAGE>0, "no conv3d on images") + def test_padded_conv3d(self): + helper_test_op([(1,4,5,5,5), (4,4,3,3,3)], + lambda x,w: torch.nn.functional.conv3d(x,w,padding=1), + lambda x,w: Tensor.conv2d(x,w,padding=[1,1,1,1,1,1]), grad_rtol=1e-5) + + def test_simple_conv2d_m4(self): + helper_test_op([(1,16,18,18), (16,16,3,3)], + lambda x,w: torch.nn.functional.conv2d(x,w), + lambda x,w: Tensor.conv2d(x,w), atol=1e-05, grad_rtol=1e-5) + + def test_simple_conv2d_1x1(self): + helper_test_op([(1,4,9,9), (4,4,1,1)], + lambda x,w: torch.nn.functional.conv2d(x,w), + lambda x,w: Tensor.conv2d(x,w), grad_rtol=1e-5) + + def test_simple_conv2d_1x1_m4(self): + helper_test_op([(1,16,32,32), (16,16,1,1)], + lambda x,w: torch.nn.functional.conv2d(x,w), + lambda x,w: Tensor.conv2d(x,w), grad_rtol=1e-5) + + def test_nested_conv2d(self): + helper_test_op([(1,32,9,9), (32,32,3,3), (32,32,3,3)], + lambda x,w1,w2: torch.nn.functional.conv2d(torch.nn.functional.conv2d(x,w1).relu(), w2), + lambda x,w1,w2: x.conv2d(w1).relu().conv2d(w2)) + + # expect reduce nodes == 3 + def test_simple_conv2d_nhwc(self): + # weights (from tf): filter_height x filter_width x in_channels x out_channels + helper_test_op([(2,9,9,10), (3,3,10,20)], + lambda x,w: torch.nn.functional.conv2d(x.permute(0,3,1,2),w.permute(3,2,0,1)), + lambda x,w: Tensor.conv2d(x.permute(0,3,1,2),w.permute(3,2,0,1)), atol=1e-5, grad_rtol=1e-5) + + def test_simple_conv2d_batched(self): + helper_test_op([(2,4,9,9), (4,4,3,3)], + lambda x,w: torch.nn.functional.conv2d(x,w), + lambda x,w: Tensor.conv2d(x,w), grad_rtol=1e-5) + + # conv transpose + + def test_simple_conv_transpose2d(self): + helper_test_op([(2,4,9,9), (4,4,3,3)], + lambda x,w: torch.nn.functional.conv_transpose2d(x,w), + lambda x,w: Tensor.conv_transpose2d(x,w), grad_rtol=1e-5) + + def test_bias_conv_transpose2d(self): + helper_test_op([(2,4,9,9), (4,4,3,3), (4,)], + lambda x,w,b: torch.nn.functional.conv_transpose2d(x,w,b), + lambda x,w,b: Tensor.conv_transpose2d(x,w,b), grad_rtol=1e-5) + + def test_grouped_conv_transpose2d(self): + helper_test_op([(2,4,9,9), (4,4,3,3)], + lambda x,w: torch.nn.functional.conv_transpose2d(x,w,groups=2), + lambda x,w: Tensor.conv_transpose2d(x,w,groups=2), grad_rtol=1e-5) + + def test_padded_conv_transpose2d(self): + for padding in [(1,2), (2,1), 2, 1, 0]: + helper_test_op([(2,4,9,9), (4,4,3,3)], + lambda x,w: torch.nn.functional.conv_transpose2d(x,w,padding=padding), + lambda x,w: Tensor.conv_transpose2d(x,w,padding=padding), grad_rtol=1e-5) + self.helper_test_exception([(2,16,2,2), (32,16,3,3)], lambda x,w: torch.nn.functional.conv_transpose2d(x,w,padding=(1,1,1)), + lambda x,w: Tensor.conv_transpose2d(x,w,padding=(1,1,1)), expected=(RuntimeError, ValueError)) + + def test_dilated_conv_transpose2d(self): + for dilation in [(1,2), (2,1), 2, 1]: + helper_test_op([(2,4,9,9), (4,4,3,3)], + lambda x,w: torch.nn.functional.conv_transpose2d(x,w,dilation=dilation), + lambda x,w: Tensor.conv_transpose2d(x,w,dilation=dilation), grad_rtol=1e-5) + + def test_strided_conv_transpose2d(self): + for stride in [(2,1), (1,2), 1]: + helper_test_op([(2,4,4,5), (4,4,3,3)], + lambda x,w: torch.nn.functional.conv_transpose2d(x,w, stride=stride), + lambda x,w: Tensor.conv_transpose2d(x,w,stride=stride), atol=1e-5, grad_rtol=1e-5) + + def test_output_padded_conv_transpose2d(self): + for output_padding, stride in [((1,1), (2,3)), ((2,1), (3,2))]: + helper_test_op([(2,4,6,5), (4,4,3,3),(4,)], + lambda x,w,b: torch.nn.functional.conv_transpose2d(x,w,b,output_padding=output_padding,stride=stride), + lambda x,w,b: Tensor.conv_transpose2d(x,w,b,output_padding=output_padding,stride=stride), grad_rtol=1e-5) + + @unittest.skipIf(IMAGE>0, "no conv3d on images") + def test_simple_conv_transpose3d(self): + helper_test_op([(2,4,9,9,9), (4,4,3,3,3)], + lambda x,w: torch.nn.functional.conv_transpose3d(x,w), + lambda x,w: Tensor.conv_transpose2d(x,w), grad_rtol=1e-5) + + @unittest.skipIf((IMAGE>0), "no conv1d on images") + def test_conv1d(self): + for bs in [1,8]: + for cin in [1,3]: + for H in [1,2,5]: + for groups in [1,3] if cin == 3 and H == 5 else [1]: + with self.subTest(batch_size=bs, channels=cin, groups=groups, height=H): + helper_test_op([(bs,cin,11), (6,cin//groups,H)], + lambda x,w: torch.nn.functional.conv1d(x,w,groups=groups), + lambda x,w: Tensor.conv2d(x,w,groups=groups), grad_rtol=1e-5) + + @unittest.skipIf(IMAGE>0, "no conv1d on images") + def test_simple_padding_conv1d(self): + bs = 6 + cin = 2 + groups = 1 + H = 5 + p = (1,1) + helper_test_op([(bs,cin,11), (6,cin//groups,H)], + lambda x,w: torch.nn.functional.conv1d(torch.nn.functional.pad(x, p),w), + lambda x,w: Tensor.conv2d(x,w,padding=p)) + + @unittest.skipIf(IMAGE>0, "no conv1d on images") + def test_strided_conv1d_simple(self): + bs, H = 2, 3 + helper_test_op([(bs,1,5), (1,1,H)], + lambda x,w: torch.nn.functional.conv1d(x,w,stride=2), + lambda x,w: Tensor.conv2d(x,w,stride=2)) + + @unittest.skipIf(IMAGE>0, "no conv1d on images") + def test_asymmetric_padding_conv1d(self): + for p in [(0,1), (2,1), (2,0)]: + with self.subTest(p): + for n in [3,4]: + for k in [2]: + helper_test_op([(1,1,n), (1,1,k)], + lambda x,w: torch.nn.functional.conv1d(torch.nn.functional.pad(x, p),w), + lambda x,w: Tensor.conv2d(x,w,padding=p)) + + def _test_conv2d(self, bs=1, cin=1, cout=6): + for H in [2,3]: + for W in [1,3,5]: + for groups in [1,3] if cin == 3 and cout == 6 and H == 3 and W == 3 else [1]: + with self.subTest(batch_size=bs, channels=cin, groups=groups, height=H, width=W): + helper_test_op([(bs,cin,5,7), (cout,cin//groups,H,W)], + lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups), + lambda x,w: Tensor.conv2d(x,w,groups=groups), grad_rtol=1e-5) + def test_conv2d(self): self._test_conv2d(bs=1, cin=3) + def test_conv2d_bs_4_cin_3(self): self._test_conv2d(bs=4, cin=3, cout=2) + def test_conv2d_bs_1_cin_1(self): self._test_conv2d(bs=1, cin=1) + def test_conv2d_bs_4_cin_1(self): self._test_conv2d(bs=4, cin=1) + + def test_conv2d_errors(self): + # kernel size cannot be larger than input size + self.helper_test_exception([(1,1,6,7), (6,1,3,3)], + lambda x,w:torch.nn.functional.conv2d(x,w,dilation=3), + lambda x,w: Tensor.conv2d(x,w,dilation=3), expected=(RuntimeError, AssertionError)) + # regression test for https://github.com/tinygrad/tinygrad/pull/7549/ + self.helper_test_exception([(2,16,2,2), (32,16,3,3)], lambda x,w:torch.nn.functional.conv2d(x,w), lambda x,w: Tensor.conv2d(x,w), + expected=(RuntimeError, AssertionError)) + self.helper_test_exception([(2,16,2,2), (32,16,3,3)], lambda x,w:torch.nn.functional.conv2d(x,w,padding=(1,1,1)), + lambda x,w: Tensor.conv2d(x,w,padding=(1,1,1)), expected=(RuntimeError, ValueError)) + + def test_large_input_conv2d(self): + bs = 4 + cin = 16 + groups = 1 + H = 5 + W = 2 + helper_test_op([(bs,cin,64,64), (6,cin//groups,H,W)], + lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups), + # needed to relax tolerance for larger input + lambda x,w: Tensor.conv2d(x,w,groups=groups), atol=1e-4, grad_atol=3e-4, grad_rtol=1e-4) + + def test_simple_grouped_conv2d(self): + bs = 1 + groups = 2 + rcout = 1 + cin = 2 + helper_test_op([(bs,groups*cin,1,1), (groups*rcout,cin,1,1)], + lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups), + lambda x,w: Tensor.conv2d(x,w,groups=groups), grad_rtol=1e-5) + + def test_medium_grouped_conv2d(self): + bs = 1 + groups = 2 + rcout = 2 + cin = 2 + helper_test_op([(bs,groups*cin,1,1), (groups*rcout,cin,1,1)], + lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups), + lambda x,w: Tensor.conv2d(x,w,groups=groups), grad_rtol=1e-5) + + def test_depthwise_conv2d(self): + bs = 1 + groups = 32 + rcout = 1 + cin = 1 + helper_test_op([(bs,groups*cin,32,32), (groups*rcout,cin,1,1)], + lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups), + lambda x,w: Tensor.conv2d(x,w,groups=groups), grad_rtol=1e-5) + + def test_grouped_conv2d(self): + bs = 4 + groups = 5 + rcout = 7 + cin = 3 + helper_test_op([(bs,groups*cin,5,5), (groups*rcout,cin,3,3)], + lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups), + lambda x,w: Tensor.conv2d(x,w,groups=groups), grad_rtol=1e-5) + + def test_fancy_conv2d(self): + bs = 2 + cin = 3 + cout = 1 + groups = 3 + H,W = 3,3 + helper_test_op([(bs,cin,11,28), (groups*cout,cin//groups,H,W)], + lambda x,w: torch.nn.functional.conv2d(x,w,groups=groups), + lambda x,w: Tensor.conv2d(x,w,groups=groups), grad_rtol=1e-5) + + def test_strided_conv2d_simple(self): + bs,H,W = 2,3,1 + helper_test_op([(bs,1,5,1), (1,1,H,W)], + lambda x,w: torch.nn.functional.conv2d(x,w,stride=2), + lambda x,w: Tensor.conv2d(x,w,stride=2)) + + @unittest.skipIf(Device.DEFAULT != "LLVM", "DEVECTORIZE=0 only for LLVM") + def test_strided_conv2d_simple_vec(self): + with Context(DEVECTORIZE=0): self.test_strided_conv2d_simple() + + def test_strided_conv2d(self): + bs = 4 + cin = 3 + H,W = 3,3 + with self.subTest(stride := 2): + helper_test_op([(bs,cin,11,28), (4,cin,H,W)], + lambda x,w: torch.nn.functional.conv2d(x,w,stride=2), + lambda x,w: Tensor.conv2d(x,w,stride=stride)) + with self.subTest(stride := (2,1)): + helper_test_op([(bs,cin,11,28), (4,cin,H,W)], + lambda x,w: torch.nn.functional.conv2d(x,w,stride=stride), + lambda x,w: Tensor.conv2d(x,w,stride=(2,1))) + + def test_negative_padding_conv2d(self): + n,k = 10, 3 + helper_test_op([(1,1,n,n), (1,1,k,k)], + lambda x,w: torch.nn.functional.conv2d(x[:, :, 1:-1, 1:-1],w), + lambda x,w: Tensor.conv2d(x,w,padding=-1)) + helper_test_op([(1,1,n,n), (1,1,k,k)], + lambda x,w: torch.nn.functional.conv2d(x[:, :, 1:, 1:],w), + lambda x,w: Tensor.conv2d(x,w,padding=(-1,0,-1,0))) + + def test_simple_padding_conv2d(self): + p = (1,1,1,1) + helper_test_op(None, + lambda x,w: torch.nn.functional.conv2d(torch.nn.functional.pad(x, p),w), + lambda x,w: Tensor.conv2d(x,w,padding=p), vals=[[[[[2.,3.]]]], [[[[1.]]]]]) + + def test_asymmetric_padding_conv2d(self): + for p in [(0,1,0,1), (2,1,2,1), (2,0,2,1)]: + with self.subTest(p): + for n in [3,4]: + for k in [2]: + helper_test_op([(1,1,n,n), (1,1,k,k)], + lambda x,w: torch.nn.functional.conv2d(torch.nn.functional.pad(x, p),w), + lambda x,w: Tensor.conv2d(x,w,padding=p)) + helper_test_op([(1,1,n,n), (1,1,k,k)], + lambda x,w: torch.nn.functional.conv2d(torch.nn.functional.pad(x, p),w), + lambda x,w: Tensor.conv2d(x,w,padding=p)) + + def test_padded_conv2d_p21(self): + bs,cin,H,W,padding = 4, 3, 3, 3, (2,1) + helper_test_op([(bs,cin,11,28), (4,cin,H,W)], + lambda x,w: torch.nn.functional.conv2d(x,w,padding=padding), + lambda x,w: Tensor.conv2d(x,w,padding=padding)) + + def test_padded_conv2d_p22(self): + bs,cin,H,W,padding = 4, 3, 3, 3, (2,2) + helper_test_op([(bs,cin,11,28), (4,cin,H,W)], + lambda x,w: torch.nn.functional.conv2d(x,w,padding=padding), + lambda x,w: Tensor.conv2d(x,w,padding=padding)) + + def test_padded_conv2d_1x1(self): + bs,cin,H,W,padding = 4, 3, 1, 1, 2 + helper_test_op([(bs,cin,11,28), (4,cin,H,W)], + lambda x,w: torch.nn.functional.conv2d(x,w,padding=padding), + lambda x,w: Tensor.conv2d(x,w,padding=padding)) + + def test_padded_conv2d_bs1(self): + bs,cin,H,W,padding = 1, 3, 3, 3, 1 + helper_test_op([(bs,cin,11,28), (4,cin,H,W)], + lambda x,w: torch.nn.functional.conv2d(x,w,padding=padding), + lambda x,w: Tensor.conv2d(x,w,padding=padding)) + + def test_padding_add(self): + helper_test_op([(64,64), (60,60)], + lambda x,w: x+torch.nn.functional.pad(w, (2,2,2,2)), + lambda x,w: x+w.pad((2,2,2,2))) + + def test_dilated_conv2d(self): + bs = 4 + cin = 3 + H,W = 3,3 + for d in [2, (2,1)]: + with self.subTest(dilation := d): + helper_test_op([(bs,cin,11,28), (4,cin,H,W)], + lambda x,w: torch.nn.functional.conv2d(x,w,dilation=dilation), + lambda x,w: Tensor.conv2d(x,w,dilation=dilation)) + + def test_max_pool2d_simple(self): + ksz = (2,2) + helper_test_op([(1,1,2,3)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=ksz), + lambda x: Tensor.max_pool2d(x, kernel_size=ksz)) + + def test_max_pool2d(self): + for ksz in [(2,2), (3,3), 2, 3, (3,2), (5,5), (5,1)]: + with self.subTest(kernel_size=ksz): + helper_test_op([(32,2,11,28)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=ksz), + lambda x: Tensor.max_pool2d(x, kernel_size=ksz)) + + def test_max_pool2d_padding(self): + for ksz in [(2,2), (3,3), 2, 3, (3,2)]: + for p in [1, (1,0), (0,1)]: + with self.subTest(kernel_size=ksz, padding=p): + helper_test_op([(32,2,11,28)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=ksz, padding=p), + lambda x: Tensor.max_pool2d(x, kernel_size=ksz, padding=p)) + self.helper_test_exception([(32,2,110,28)], lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(2,2), padding=(1,1,1)), + lambda x: Tensor.max_pool2d(x, kernel_size=(2,2), padding=(1,1,1)), expected=(RuntimeError, ValueError)) + + def test_max_pool2d_asymmetric_padding(self): + shape = (32,2,111,28) + for p in [(0,1,0,1), (2,1,2,1), (2,0,2,1)]: + with self.subTest(padding=p): + helper_test_op([shape], + lambda x: torch.nn.functional.max_pool2d(torch.nn.functional.pad(x, p, value=float("-inf")), kernel_size=(5,5)), + lambda x: Tensor.max_pool2d(x, kernel_size=(5,5), padding=p)) + + def test_max_pool2d_padding_int(self): + ksz = (2,2) + helper_test_op([(32,2,11,28)], + lambda x: torch.nn.functional.max_pool2d(x.int(), kernel_size=ksz, padding=1), + lambda x: Tensor.max_pool2d(x.int(), kernel_size=ksz, padding=1), forward_only=True) + + def test_max_pool2d_bigger_stride(self): + for stride in [(2,3), (3,2), 2, 3]: + with self.subTest(stride=stride): + helper_test_op([(32,2,11,28)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(2,2), stride=stride), + lambda x: Tensor.max_pool2d(x, kernel_size=(2,2), stride=stride)) + + def test_max_pool2d_bigger_stride_dilation(self): + for stride, dilation in zip([(2,3), (3,2), 2, 3, 4], [(3,2), (2,3), 2, 3, 6]): + with self.subTest(stride=stride): + helper_test_op([(32,2,11,28)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(2,2), stride=stride, dilation=dilation), + lambda x: Tensor.max_pool2d(x, kernel_size=(2,2), stride=stride, dilation=dilation)) + + @unittest.skipIf( Device.DEFAULT in {"CUDA", "NV"}, "CUDA fails on this") + def test_max_pool2d_unit_stride(self): + helper_test_op([(3, 2, 17, 14)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(5,5), stride=1), + lambda x: Tensor.max_pool2d(x, kernel_size=(5,5), stride=1)) + + def test_max_pool2d_smaller_stride(self): + for stride in [(2,3), (3,2), 2, 3]: + with self.subTest(stride=stride): + helper_test_op([(3, 2, 17, 14)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(5,5), stride=stride), + lambda x: Tensor.max_pool2d(x, kernel_size=(5,5), stride=stride)) + + def test_max_pool2d_dilation(self): + for dilation in [(2, 3), (3, 2), 2, 3]: + helper_test_op([(3, 2, 17, 14)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(5,5), dilation=dilation), + lambda x: Tensor.max_pool2d(x, kernel_size=(5,5), dilation=dilation)) + + def test_max_pool2d_ceil_mode(self): + shape = (1,1,6,6) + for ksz in [(3,3), 3, (3,2), 4]: + with self.subTest(kernel_size=ksz): + helper_test_op([shape], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=ksz, padding=1, stride=3, ceil_mode=True), + lambda x: Tensor.max_pool2d(x, kernel_size=ksz, padding=1, stride=3, ceil_mode=True)) + + def test_max_pool2d_ceil_mode_output_size_reduce_by_one(self): + # sliding window ignored from end region + helper_test_op([(1,1,5,5)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(3,3), stride=3, padding=1, ceil_mode=True), + lambda x: Tensor.max_pool2d(x, kernel_size=(3,3), stride=3, padding=1, ceil_mode=True)) + + def test_max_pool2d_return_indices(self): + # batch and multi-channel + helper_test_op([(2,3,6,6)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(2,2), return_indices=True)[1].type(torch.int32), + lambda x: Tensor.max_pool2d(x, kernel_size=(2,2), return_indices=True)[1], forward_only=True) + # dilation + helper_test_op([(1,1,10,10)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(3,2), dilation=(2,3), return_indices=True)[1].type(torch.int32), + lambda x: Tensor.max_pool2d(x, kernel_size=(3,2), dilation=(2,3), return_indices=True)[1], forward_only=True) + # padding + helper_test_op([(1,1,5,5)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(3,3), padding=1, return_indices=True)[1].type(torch.int32), + lambda x: Tensor.max_pool2d(x, kernel_size=(3,3), padding=1, return_indices=True)[1], forward_only=True) + # ceil mode padding + helper_test_op([(1, 1, 7, 7)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(2, 2), stride=(2, 2), ceil_mode=True, return_indices=True)[1].type(torch.int32), + lambda x: Tensor.max_pool2d(x, kernel_size=(2, 2), stride=(2, 2), ceil_mode=True, return_indices=True)[1], + forward_only=True) + # global maxpool + helper_test_op([(1,1,12,13)], + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(12, 13), return_indices=True)[1].type(torch.int32), + lambda x: Tensor.max_pool2d(x, kernel_size=(12, 13), return_indices=True)[1], + forward_only=True) + # multiple identical values in same window and overlapping windows + helper_test_op(None, + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(3,3), stride=1, return_indices=True)[1].type(torch.int32), + lambda x: Tensor.max_pool2d(x, kernel_size=(3,3), stride=1, return_indices=True)[1], + vals=[[[[[1]*6]*6]]], forward_only=True) # Tensor.ones(1,1,6,6) + # overlapping max indices + helper_test_op(None, + lambda x: torch.nn.functional.max_pool2d(x, kernel_size=(2,2), stride=1, return_indices=True)[1].type(torch.int32), + lambda x: Tensor.max_pool2d(x, kernel_size=(2,2), stride=1, return_indices=True)[1], + vals=[[[[[1,2]*3]*6]]], forward_only=True) # Tensor([1,2,1,2,1,2]).expand(1,1,6,6) + + def test_max_unpool2d(self): + args = {"kernel_size":(5,5), "stride":(6,5)} + helper_test_op([(8,3,50,50)], + lambda x: torch.nn.functional.max_unpool2d(*torch.nn.functional.max_pool2d(x, return_indices=True, **args), **args), + lambda x: Tensor.max_unpool2d(*Tensor.max_pool2d(x, return_indices=True, **args), **args), forward_only=True) + args = {"kernel_size":(3,3), "stride":(6,7), "padding":1} + helper_test_op([(8,3,30,30)], + lambda x: torch.nn.functional.max_unpool2d(*torch.nn.functional.max_pool2d(x, return_indices=True, **args), **args, output_size=(30,30)), + lambda x: Tensor.max_unpool2d(*Tensor.max_pool2d(x, return_indices=True, **args), **args, output_size=(30,30)), forward_only=True) + # batch_size and channel_size of output_size are ignored + helper_test_op([(1,3,7,6)], + lambda x: torch.nn.functional.max_unpool2d(*torch.nn.functional.max_pool2d(x, kernel_size=(2,2), return_indices=True), + kernel_size=(2,2), output_size=(99,99,7,6)), + lambda x: Tensor.max_unpool2d(*Tensor.max_pool2d(x, kernel_size=(2,2), return_indices=True), + kernel_size=(2,2), output_size=(99,99,7,6)), forward_only=True) + + def test_avg_pool2d(self): + shape = (32,2,111,28) + for ksz in [(2,2), (3,3), (3,2), (5,5), (5,1)]: + with self.subTest(kernel_size=ksz): + helper_test_op([shape], + lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=ksz), + lambda x: Tensor.avg_pool2d(x, kernel_size=ksz), rtol=1e-5) + + # regression test for https://github.com/tinygrad/tinygrad/pull/7581 + helper_test_op([(1,1,8,8)], + lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=(1,2), padding=(0,1), stride=(5,1)), + lambda x: Tensor.avg_pool2d(x, kernel_size=(1,2), padding=(0,1), stride=(5,1)), rtol=1e-5) + + def test_avg_pool2d_padding(self): + shape = (32,2,111,28) + for ksz in [(2,2), (3,3), 2, 3, (3,2)]: + for p in [1, (1,0), (0,1)]: + with self.subTest(kernel_size=ksz, padding=p): + helper_test_op([shape], + lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=ksz, padding=p), + lambda x: Tensor.avg_pool2d(x, kernel_size=ksz, padding=p), rtol=1e-5) + with self.assertRaises(ValueError): + Tensor.avg_pool2d(Tensor.randn((32,2,111,28)), kernel_size=(2,2), padding=(1,1,1)) + + def test_avg_pool2d_asymmetric_padding(self): + shape = (32,2,111,28) + for p in [(0,1,0,1), (2,1,2,1), (2,0,2,1)]: + with self.subTest(padding=p): + helper_test_op([shape], + lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=(5,5), padding=1), + lambda x: Tensor.avg_pool2d(x, kernel_size=(5,5), padding=1), rtol=1e-5) + self.helper_test_exception([shape], lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=(2,2), padding=(1,1,1)), + lambda x: Tensor.avg_pool2d(x, kernel_size=(2,2), padding=(1,1,1)), expected=(RuntimeError, ValueError)) + + def test_avg_pool2d_padding_not_counted(self): + shape = (32,2,111,28) + for ksz in [(2,2), (3,3), 2, 3, (3,2)]: + with self.subTest(kernel_size=ksz): + helper_test_op([shape], + lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=ksz, padding=1, count_include_pad=False), + lambda x: Tensor.avg_pool2d(x, kernel_size=ksz, padding=1, count_include_pad=False), rtol=1e-5) + + def test_avg_pool2d_ceil_mode(self): + shape = (1,1,6,6) + for ksz in [(3,3), 3, (3,2), 4]: + with self.subTest(kernel_size=ksz): + helper_test_op([shape], + lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=ksz, padding=1, stride=3, ceil_mode=True), + lambda x: Tensor.avg_pool2d(x, kernel_size=ksz, padding=1, stride=3, ceil_mode=True), rtol=1e-5) + + def test_avg_pool2d_ceil_mode_padding_not_counted(self): + shape = (1,1,6,6) + for ksz in [(3,3), 3, (3,2), 4]: + with self.subTest(kernel_size=ksz): + helper_test_op([shape], + lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=ksz, padding=1, stride=3, ceil_mode=True, count_include_pad=False), + lambda x: Tensor.avg_pool2d(x, kernel_size=ksz, padding=1, stride=3, ceil_mode=True, count_include_pad=False), rtol=1e-5) + + def test_avg_pool2d_ceil_mode_output_size_reduce_by_one(self): + # sliding window ignored from end region + helper_test_op([(1,1,5,5)], + lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=(3,3), stride=3, padding=1, ceil_mode=True), + lambda x: Tensor.avg_pool2d(x, kernel_size=(3,3), stride=3, padding=1, ceil_mode=True)) + + def test_avg_pool2d_ceil_mode_include_pad_output_size_reduce_by_one(self): + # sliding window ignored from end region + helper_test_op([(1,1,5,5)], + lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=(3,3), stride=3, padding=1, ceil_mode=True, count_include_pad=True), + lambda x: Tensor.avg_pool2d(x, kernel_size=(3,3), stride=3, padding=1, ceil_mode=True, count_include_pad=True)) + + def test_global_avg_pool2d(self): + helper_test_op([(32,2,111,28)], + lambda x: torch.nn.functional.avg_pool2d(x, kernel_size=(111,28)), + lambda x: Tensor.avg_pool2d(x, kernel_size=(111,28)), rtol=1e-5) + + def test_avg_pool3d_failure(self): + with Context(NOOPT=0): + helper_test_op([(1,1,16,16,16)], + lambda x: torch.nn.functional.avg_pool3d(x, kernel_size=(8,8,8), stride=5, padding=1, count_include_pad=False), + lambda x: Tensor.avg_pool2d(x, kernel_size=(8,8,8), stride=5, padding=1, count_include_pad=False), rtol=1e-5, forward_only=True) + + def test_avg_pool3d_noopt(self): + with Context(NOOPT=1): + helper_test_op([(1,1,16,16,16)], + lambda x: torch.nn.functional.avg_pool3d(x, kernel_size=(8,8,8), stride=5, padding=1, count_include_pad=False), + lambda x: Tensor.avg_pool2d(x, kernel_size=(8,8,8), stride=5, padding=1, count_include_pad=False), rtol=1e-5, forward_only=True) + + def test_interpolate_linear(self): + for in_sz, out_sz in [((52,),(29,)), ((29,),(52,))]: + helper_test_op([(2,3)+in_sz], + lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode="linear"), + lambda x: Tensor.interpolate(x, size=out_sz, mode="linear")) + + def test_interpolate_linear_corners_aligned(self): + for in_sz, out_sz in [((52,),(29,)), ((29,),(52,))]: + helper_test_op([(2,3)+in_sz], + lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode="linear", align_corners=True), + lambda x: Tensor.interpolate(x, size=out_sz, mode="linear", align_corners=True)) + + def test_interpolate_nearest(self, mode="nearest"): + for in_sz, out_sz in [((13,),(9,)), ((9,),(13,))]: + helper_test_op([(2,3)+in_sz], + lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode=mode), + lambda x: Tensor.interpolate(x, size=out_sz, mode=mode)) + for in_sz, out_sz in [((13,10),(9,11)), ((13,9),(11,10)), ((9,11),(10,13))]: + helper_test_op([(2,3)+in_sz], + lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode=mode), + lambda x: Tensor.interpolate(x, size=out_sz, mode=mode)) + for in_sz, out_sz in [((5,2,8),(3,6,4))]: + helper_test_op([(2,3)+in_sz], + lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode=mode), + lambda x: Tensor.interpolate(x, size=out_sz, mode=mode)) + + def test_interpolate_nearest_exact(self): self.test_interpolate_nearest("nearest-exact") + + def test_interpolate_bilinear(self): + for in_sz, out_sz in [((12,20),(9,31)), ((12,9),(31,20)), ((9,31),(20,12))]: + helper_test_op([(2,3)+in_sz], + lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode="bilinear"), + lambda x: Tensor.interpolate(x, size=out_sz, mode="linear"), atol=1e-4) + + def test_interpolate_bilinear_corners_aligned(self): + for in_sz, out_sz in [((12,20),(9,31)), ((12,9),(31,20)), ((9,31),(20,12))]: + helper_test_op([(2,3)+in_sz], + lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode="bilinear", align_corners=True), + lambda x: Tensor.interpolate(x, size=out_sz, mode="linear", align_corners=True), atol=1e-4) + + def test_interpolate_trilinear(self): + for in_sz, out_sz in [((5,2,8),(3,6,4))]: + helper_test_op([(2,3)+in_sz], + lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode="trilinear"), + lambda x: Tensor.interpolate(x, size=out_sz, mode="linear"), atol=1e-4) + + def test_interpolate_trilinear_corners_aligned(self): + for in_sz, out_sz in [((5,2,8),(3,6,4))]: + helper_test_op([(2,3)+in_sz], + lambda x: torch.nn.functional.interpolate(x, size=out_sz, mode="trilinear", align_corners=True), + lambda x: Tensor.interpolate(x, size=out_sz, mode="linear", align_corners=True), atol=1e-4) + + def test_cat(self): + for dim in range(-2, 3): + helper_test_op([(45,65,9), (45,65,9), (45,65,9)], lambda x,y,z: torch.cat((x,y,z), dim), lambda x,y,z: x.cat(y, z, dim=dim)) + + # zero in non-cat axis + helper_test_op([(45,0,9), (45,0,9), (45,0,9)], lambda x,y,z: torch.cat((x,y,z), 0), lambda x,y,z: x.cat(y, z, dim=0)) + + # zero in cat axis + helper_test_op([(45,0,9), (45,1,9), (45,2,9)], lambda x,y,z: torch.cat((x,y,z), 1), lambda x,y,z: x.cat(y, z, dim=1)) + helper_test_op([(45,0,9), (45,0,9), (45,0,9)], lambda x,y,z: torch.cat((x,y,z), 1), lambda x,y,z: x.cat(y, z, dim=1)) + + with self.assertRaises(IndexError): + a = Tensor(3.14) + a.cat(a) + + def test_multicat(self): + for dim in range(-1, 2): + helper_test_op([(45,65), (45,65), (45,65)], lambda x,y,z: torch.cat((x,y,z), dim), lambda x,y,z: x.cat(y, z, dim=dim)) + + def test_stack(self): + for dim in range(-1, 3): + helper_test_op([(45,65,3), (45,65,3), (45,65,3)], lambda x, y, z: torch.stack((x, y, z), dim), lambda x, y, z: Tensor.stack(x, y, z, dim=dim)) + + with self.assertRaises(IndexError): + Tensor.stack(Tensor.randn(45, 65, 3), dim=77) + + a = Tensor(3.14) + np.testing.assert_allclose(Tensor.stack(a, a).numpy(), Tensor([3.14, 3.14]).numpy()) + + def test_repeat(self): + x = Tensor.randn(4, 6, 3) + base_repeats = [2, 4, 3] + + for reps in [[], [4], [2, 1], [3, 2, 2]]: + repeats = base_repeats + reps + helper_test_op([(4, 6, 3)], lambda x: x.repeat(*repeats), lambda x: x.repeat(repeats)) + helper_test_op([()], lambda x: x.repeat(*repeats), lambda x: x.repeat(repeats)) + + with self.assertRaises(ValueError): + x.repeat((2, 4)) + + np.testing.assert_allclose(x.repeat((2, 0, 4)).numpy(), Tensor.zeros(8, 0, 12).numpy()) + + def test_repeat_interleave(self): + helper_test_op([(3, 3)], lambda x: x.repeat_interleave(6)) + helper_test_op([(3, 3)], lambda x: x.repeat_interleave(2, 1)) + helper_test_op([(3, 3)], lambda x: x.repeat_interleave(2, 0)) + helper_test_op([(3, 3)], lambda x: x.repeat_interleave(2, -1)) + helper_test_op([(3, 3)], lambda x: x.repeat_interleave(2, -2)) + + def test_simple_repeat(self): + repeats = [3, 3, 4] + helper_test_op([(3, 3)], lambda x: x.repeat(*repeats), lambda x: x.repeat(repeats)) + + def test_clip(self): + helper_test_op([(45,65)], lambda x: x.clip(-2.3, 1.2)) + helper_test_op([(45,65)], lambda x: x.clip(0, 0)) + helper_test_op([(45,65)], lambda x: x.clip(10, 100)) + helper_test_op([(45,65)], lambda x: x.clip(0, 0.1)) + helper_test_op([(45,65)], lambda x: x.clip(-0.3, -0.2)) + helper_test_op([(45,65)], lambda x: x.clip(3, 0)) # min > max + helper_test_op([(45,65)], lambda x: x.clip(None, 0)) + helper_test_op([(45,65)], lambda x: x.clip(0, None)) + self.helper_test_exception([(45,65)], lambda x: x.clip(None, None), lambda x: x.clip(None, None), RuntimeError) + + def test_matvecmat(self): + helper_test_op([(1,128), (128,128), (128,128)], lambda x,y,z: (x@y).relu()@z) + + def test_matvec(self): + helper_test_op([(1,128), (128,128)], lambda x,y: (x@y).relu()) + + @unittest.skip("this test is broken #862") + def test_max_nan(self): + n = Tensor([1, float("nan")]).max().numpy() + assert math.isnan(n.item()), f"{n.item()} is not nan" + + def test_inf_where(self): + x = Tensor.full((3, 3), float("inf")) + n = (x < 0).where(x, 1).numpy() + assert np.all(n == 1.) + + def _get_index_randoms(self): + # indices cannot have gradient + a = torch.randint(low=-1, high=1, size=(2,1,1,1,1,1), dtype=torch.int64, requires_grad=False) + b = torch.randint(high=1, size=(1,3,1,1,1,1), dtype=torch.int64, requires_grad=False) + c = torch.randint(low=-5, high=5, size=(1,1,4,1,1,1), dtype=torch.int64, requires_grad=False) + d = torch.randint(high=4, size=(2,1,1,5,1,1), dtype=torch.int64, requires_grad=False) + e = torch.randint(high=1, size=(1,1,1,1,6,1), dtype=torch.int64, requires_grad=False) + i, j, k, o, p = [Tensor(tor.detach().cpu().numpy().astype(np.int32), requires_grad=False) for tor in [a,b,c,d,e]] + return a,b,c,d,e,i,j,k,o,p + + @unittest.skipIf(Device.DEFAULT == "WEBGPU", "WEBGPU can only run kernels with up to 10 buffers") + def test_slice_fancy_indexing_no_dim_collapse(self): + a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() + # no dim collapse from int or dim injection from None + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,c,d,e], lambda x: x[i,j,k,o,p]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[:,b,c,d,:], lambda x: x[:,j,k,o,:]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,...], lambda x: x[i,j,...]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,...,e], lambda x: x[i,...,p]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[...,c,:,e], lambda x: x[...,k,:,p]) + + def test_slice_fancy_indexing_dim_collapse_int(self): + a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() + # dim collapse from int + helper_test_op([(2,5,6,5,3,4)], lambda x: x[1,b,c,d,e], lambda x: x[1,j,k,o,p]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,3,d,e], lambda x: x[i,j,3,o,p]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[1,b,2,d,2], lambda x: x[1,j,2,o,2]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,2,2,2,e], lambda x: x[i,2,2,2,p]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[1,:,3:11:2,d,0:2], lambda x: x[1,:,3:11:2,o,0:2]) + + def test_slice_fancy_indexing_dim_inject_none(self): + a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() + # dim injection from None + helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,b,c,d,e], lambda x: x[None,j,k,o,p]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,c,d,None], lambda x: x[i,j,k,o,None]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,None,d,e], lambda x: x[i,j,None,o,p]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,b,c,d,None], lambda x: x[None,j,k,o,None]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,:,None,d,e], lambda x: x[i,:,None,o,p]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,None,None,None,None], lambda x: x[None,None,None,None,None]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,None,b,c,d,e], lambda x: x[None,None,j,k,o,p]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,None,b,c,None,None], lambda x: x[None,None,j,k,None,None]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,None,None,c,d,e], lambda x: x[i,None,None,k,o,p]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,None,None,c,None,None], lambda x: x[i,None,None,k,None,None]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,None,b,None,d,e], lambda x: x[None,None,j,None,o,p]) + + def test_slice_fancy_indexing_dim_inject_and_collapse(self): + a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() # noqa + # dim injection and collapse + helper_test_op([(2,5,6,5,3,4)], lambda x: x[1,b,None,d,1], lambda x: x[1,j,None,o,1]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[None,b,2,d,None], lambda x: x[None,j,2,o,None]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[...,1,d,None], lambda x: x[...,1,o,None]) + + def test_slice_fancy_indexing_with_tensors(self): + # indexing using idx with different dim + helper_test_op([(2,3)], lambda x: x[torch.tensor([[0,0,0],[0,0,0]]), torch.tensor(1)], + lambda x: x[Tensor([[0,0,0],[0,0,0]]), Tensor(1)]) + helper_test_op([(2,3)], lambda x: x[torch.tensor([1]), torch.tensor([[0,0,0],[0,0,0]])], + lambda x: x[Tensor([1]), Tensor([[0,0,0],[0,0,0]])]) + helper_test_op([(2,3)], lambda x: x[torch.tensor([[0,0,0],[0,0,0]]), torch.tensor([2,1,1])], + lambda x: x[Tensor([[0,0,0],[0,0,0]]), Tensor([2,1,1])]) + helper_test_op([(2,3)], lambda x: x[torch.tensor([[0,1,-1],[-1,-2,0]]), torch.tensor([2,1,-1])], + lambda x: x[Tensor([[0,1,-1],[-1,-2,0]]), Tensor([2,1,-1])]) + + @unittest.skipIf(Device.DEFAULT == "WEBGPU", "WEBGPU can only run kernels with up to 10 buffers") + def test_slice_fancy_indexing_list_indices(self): + a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() + helper_test_op([(2,5,6,5,3,4)], lambda x: x[[[0]]], lambda x: x[[[0]]]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[[0],b,c,d,:], lambda x: x[[0],j,k,o,:]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[[[[0]]],b,c,d,[[1]]], lambda x: x[[[[0]]],j,k,o,[[1]]]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[[1,0],b,c,d,:], lambda x: x[[1,0],j,k,o,:]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,c,[1,2,3],...], lambda x: x[i,j,k,[1,2,3],...]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,c,[[1],[2],[3]],...], lambda x: x[i,j,k,[[1],[2],[3]],...]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,[2,1,0],c,[2,1,0],e], lambda x: x[i,[2,1,0],k,[2,1,0],p]) + + def test_slice_fancy_indexing_tuple_indices(self): + a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() + helper_test_op([(2,5,6,5,3,4)], lambda x: x[(((0,),),)], lambda x: x[(((0,),),)]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[(0,),b,c,d,:], lambda x: x[(0,),j,k,o,:]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[(1,0),b,c,d,:], lambda x: x[(1,0),j,k,o,:]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,b,c,(1,2,3),...], lambda x: x[i,j,k,(1,2,3),...]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[a,((2,),(1,),(0,)),c,(2,1,0)], lambda x: x[i,((2,),(1,),(0,)),k,(2,1,0)]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[1,(2,1,0),None,c,(2,1,0),e], lambda x: x[1,(2,1,0),None,k,(2,1,0),p]) + + @unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") + def test_slice_fancy_indexing_list_with_tensors(self): + a,b,c,d,e,i,j,k,o,p = self._get_index_randoms() + helper_test_op([(2,5,6,5,3,4)], lambda x: x[[a]], lambda x: x[[i]]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[[a,1]], lambda x: x[[i,1]]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[[a,[1,1]]], lambda x: x[[i,[1,1]]]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[[a,(1,1)]], lambda x: x[[i,(1,1)]]) + helper_test_op([(2,5,6,5,3,4)], lambda x: x[[a,b,c,d,e]], lambda x: x[[i,j,k,o,p]]) + + def test_slice_fancy_indexing_errors(self): + a = Tensor.ones(10,11,12) + # tensors used as indices must be int tensors + with self.assertRaises(IndexError): a[Tensor(1.1)] + with self.assertRaises(IndexError): a[Tensor([True, True])] + # shape mismatch, cannot broadcast. either exception is okay + with self.assertRaises((IndexError, ValueError)): a[Tensor.randint(3,1,1,1), Tensor.randint(1,4,1,1), Tensor.randint(2,4,4,1)] + with self.assertRaises((IndexError, ValueError)): a[Tensor.randint(3,1,1,1), Tensor.randint(1,4,1,1,1)] + + def test_gather(self): + # indices cannot have gradient + # indices cannot be negative (torch gather) + b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) + a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) + helper_test_op([(4,5,6)], lambda x: x.gather(dim=0, index=b), lambda x: x.gather(dim=0, index=a)) + helper_test_op([(4,5,6)], lambda x: x.gather(dim=1, index=b), lambda x: x.gather(dim=1, index=a)) + helper_test_op([(4,5,6)], lambda x: x.gather(dim=2, index=b), lambda x: x.gather(dim=2, index=a)) + helper_test_op([(3,4,5)], lambda x: x.gather(dim=0, index=b), lambda x: x.gather(dim=0, index=a)) + helper_test_op([(4,5,6)], lambda x: x.gather(dim=-1, index=b), lambda x: x.gather(dim=-1, index=a)) + helper_test_op([(4,5,6)], lambda x: x.gather(dim=-2, index=b), lambda x: x.gather(dim=-2, index=a)) + helper_test_op([(4,5,6)], lambda x: x.gather(dim=-3, index=b), lambda x: x.gather(dim=-3, index=a)) + self.helper_test_exception([(4,5,6)], lambda x: x.gather(dim=0, index=torch.tensor([1], dtype=torch.int64)), + lambda x: x.gather(dim=0, index=Tensor([1], dtype=dtypes.int32)), expected=(RuntimeError, AssertionError)) + self.helper_test_exception([(2,1,1)], lambda x: x.gather(dim=0, index=b), + lambda x: x.gather(dim=0, index=a), expected=(RuntimeError, AssertionError)) + helper_test_op(None, lambda x: x.gather(dim=0, index=torch.tensor([2, 1, 0, 1, 2], requires_grad=False)), + lambda x: x.gather(dim=0, index=Tensor([2, 1, 0, 1, 2])), + vals=[[1., 2., 3.]]) + + @unittest.expectedFailure + @unittest.skipIf(torch._C._get_privateuse1_backend_name() == "tiny", 'results in a success instead of a failure') + def test_gather_failure(self): + # gather with inf values do not work, other values results in nan + helper_test_op(None, lambda x: x.gather(dim=0, index=torch.tensor([2, 1, 0, 1, 2], requires_grad=False)), + lambda x: x.gather(dim=0, index=Tensor([2, 1, 0, 1, 2])), + vals=[[-float("inf"), 2., 3.]]) + + def test_scatter(self): + b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) + a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) + for dim in (0,1,2,-1,-2,-3): + helper_test_op([(4,5,6), (4,5,6)], lambda x,src: x.scatter(dim=dim, index=b, src=src), + lambda x,src: x.scatter(dim=dim, index=a, src=src), forward_only=True) + + helper_test_op([(3,4,5), (3,4,5)], lambda x,src: x.scatter(dim=1, index=b, src=src), + lambda x,src: x.scatter(dim=1, index=a, src=src), forward_only=True) + helper_test_op([(10,3,10), (10,10,10)], lambda x,src: x.scatter(dim=1, index=b, src=src), + lambda x,src: x.scatter(dim=1, index=a, src=src), forward_only=True) + + self.helper_test_exception([(2,3,10), (10,10,10)], lambda x,src: x.scatter(dim=1, index=b, src=src), + lambda x,src: x.scatter(dim=1, index=a, src=src), expected=(RuntimeError, AssertionError)) + self.helper_test_exception([(10,3,10), (10,3,10)], lambda x,src: x.scatter(dim=1, index=b, src=src), + lambda x,src: x.scatter(dim=1, index=a, src=src), expected=(RuntimeError, AssertionError)) + self.helper_test_exception([(3,4,5), (3,4,5)], lambda x,src: x.scatter(dim=1, index=b, src=src, mode="typo"), + lambda x,src: x.scatter(dim=1, index=a, src=src, mode="typo"), expected=TypeError) + self.helper_test_exception([(3,4,5), (3,4,5)], lambda x,src: x.half().scatter(dim=1, index=b, src=src), + lambda x,src: x.half().scatter(dim=1, index=a, src=src), expected=RuntimeError) + + helper_test_op([(4,5,6)], lambda x: x.scatter(dim=1, index=b, value=3), lambda x: x.scatter(dim=1, index=a, src=3), forward_only=True) + helper_test_op([(4,5,6)], lambda x: x.scatter(dim=1, index=b, value=float("inf")), + lambda x: x.scatter(dim=1, index=a, src=float("inf")), forward_only=True) + + # overlapping indices with 0s + b = torch.tensor([0,0], requires_grad=False) + a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) + helper_test_op(None, + lambda x,src: x.scatter(0, b, src), + lambda x,src: x.scatter(0, a, src), forward_only=True, + vals=[[1.,2.,3.,4.], [1.,0.]]) + + def test_scatter_add(self): + b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) + a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) + helper_test_op([(4,5,6)], lambda x: x.scatter(dim=1, index=b, value=float("inf"), reduce="add"), + lambda x: x.scatter(dim=1, index=a, src=float("inf"), reduce="add"), forward_only=True) + + # TODO: fails for webgpu + if Device.DEFAULT != "WEBGPU": + helper_test_op([(4,5,6)], + lambda x: x.scatter(1, b, float("nan"), reduce="add"), + lambda x: x.scatter(1, a, float("nan"), reduce="add"), forward_only=True) + + def test_scatter_mul(self): + b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) + a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) + helper_test_op([(4,5,6)], lambda x: x.scatter(dim=1, index=b, value=float("inf"), reduce="multiply"), + lambda x: x.scatter(dim=1, index=a, src=float("inf"), reduce="multiply"), forward_only=True) + + # TODO: fails for webgpu + if Device.DEFAULT != "WEBGPU": + helper_test_op([(4,5,6)], + lambda x: x.scatter(1, b, float("nan"), reduce="multiply"), + lambda x: x.scatter(1, a, float("nan"), reduce="multiply"), forward_only=True) + + def test_scatter_no_reduce_tensor_src(self): + with self.assertRaises(TypeError): + Tensor.ones(4).scatter(dim=1, index=Tensor([0]), src=Tensor.ones(4), reduce="add") + + def test_scatter_reduce(self): + b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) + a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) + for reduce in ("sum", "prod", "mean", "amin", "amax"): + for dim in (-1,1,-3): + helper_test_op([(4,5,6), (4,5,6)], + lambda x,src: x.scatter_reduce(dim=dim, index=b, src=src, reduce=reduce), + lambda x,src: x.scatter_reduce(dim=dim, index=a, src=src, reduce=reduce), forward_only=True) + helper_test_op([(4,5,6), (4,5,6)], + lambda x,src: x.scatter_reduce(dim=dim, index=b, src=src, reduce=reduce, include_self=False), + lambda x,src: x.scatter_reduce(dim=dim, index=a, src=src, reduce=reduce, include_self=False), forward_only=True) + + def test_scatter_reduce_prod_zeros(self): + b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) + a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) + x = Tensor.zeros([4,5,6]).float() + y = torch.zeros([4,5,6]).float() + helper_test_op([(4,5,6)], + lambda src: y.scatter_reduce(dim=1, index=b, src=src, reduce="prod"), + lambda src: x.scatter_reduce(dim=1, index=a, src=src, reduce="prod"), forward_only=True) + + def test_scatter_reduce_errors(self): + b = torch.randint(3, size=[3,4,5], dtype=torch.int64, requires_grad=False) + a = Tensor(b.detach().cpu().numpy().astype(np.int32), dtype=dtypes.int32, requires_grad=False) + # invalid reduce arg + self.helper_test_exception([(4,5,6), (4,5,6)], + lambda x,src: x.scatter_reduce(dim=0, index=b, src=src, reduce="INVALID"), + lambda x,src: x.scatter_reduce(dim=0, index=a, src=src, reduce="INVALID"), + RuntimeError) + # dtype mismatch + self.helper_test_exception([(4,5,6), (4,5,6)], + lambda x,src: x.half().scatter_reduce(dim=0, index=b, src=src, reduce="sum"), + lambda x,src: x.half().scatter_reduce(dim=0, index=a, src=src, reduce="sum"), + RuntimeError) + + def test_scaled_dot_product_attention(self): + helper_test_op([(32,8,16,64), (32,8,16,64), (32,8,16,64)], torch.nn.functional.scaled_dot_product_attention, Tensor.scaled_dot_product_attention) + helper_test_op([(32,8,16,64), (32,8,16,64), (32,8,16,64), (32,8,16,16)], + lambda x,y,z,m: torch.nn.functional.scaled_dot_product_attention(x,y,z,attn_mask=m), + lambda x,y,z,m: Tensor.scaled_dot_product_attention(x,y,z,attn_mask=m)) + + def test_scaled_dot_product_attention_mismatch_ls(self): + helper_test_op([(32,8,4,64), (32,8,16,64), (32,8,16,64)], torch.nn.functional.scaled_dot_product_attention, Tensor.scaled_dot_product_attention) + + def test_scaled_dot_product_attention_causal(self): + helper_test_op([(32,8,16,64), (32,8,16,64), (32,8,16,64)], + lambda x,y,z: torch.nn.functional.scaled_dot_product_attention(x,y,z,is_causal=True), + lambda x,y,z: Tensor.scaled_dot_product_attention(x,y,z,is_causal=True)) + + self.helper_test_exception([(32,8,16,64), (32,8,16,64), (32,8,16,64), (32,8,16,16)], + lambda x,y,z,m: torch.nn.functional.scaled_dot_product_attention(x,y,z,is_causal=True,attn_mask=m), + lambda x,y,z,m: Tensor.scaled_dot_product_attention(x,y,z,is_causal=True,attn_mask=m), + expected=RuntimeError) + + def test_binary_crossentropy(self): + helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy(x.sigmoid(),y.clip(0,1)), + lambda x,y: x.sigmoid().binary_crossentropy(y.clip(0,1))) + helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy_with_logits(x,y.clip(0,1)), + lambda x,y: x.binary_crossentropy_logits(y.clip(0,1))) + helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy_with_logits(x,y.clip(0,1)), + lambda x,y: x.sigmoid().binary_crossentropy(y.clip(0,1))) + helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy(x.sigmoid(),y.clip(0,1)), + lambda x,y: x.binary_crossentropy_logits(y.clip(0,1))) + def test_binary_crossentropy_reductions(self): + for r in ("mean", "sum", "none"): + helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy(x.sigmoid(), y.clip(0,1), reduction=r), + lambda x,y: x.sigmoid().binary_crossentropy(y.clip(0,1), reduction=r)) + helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy_with_logits(x, y.clip(0,1), reduction=r), + lambda x,y: x.binary_crossentropy_logits(y.clip(0,1), reduction=r)) + def test_binary_crossentropy_logits_pos_weights(self): + pos_weight = [0.25, 0.5, 0.75, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0] + helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.binary_cross_entropy_with_logits(x,y.clip(0,1), + pos_weight=torch.tensor(pos_weight)), + lambda x,y: x.binary_crossentropy_logits(y.clip(0,1),pos_weight=Tensor(pos_weight))) + def test_cross_entropy_class_probabilities(self): + helper_test_op([(32,), (32,)], lambda x,y: torch.nn.functional.cross_entropy(x, y), lambda x,y: x.cross_entropy(y)) + helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.cross_entropy(x, y), lambda x,y: x.cross_entropy(y)) + helper_test_op([(32,4,4,4), (32,4,4,4)], lambda x,y: torch.nn.functional.cross_entropy(x, y), lambda x,y: x.cross_entropy(y)) + + def test_cross_entropy_class_indices(self): + classes = np.random.randint(0, 10, (32,), dtype=np.int32).tolist() + helper_test_op([(32,10)], lambda x: torch.nn.functional.cross_entropy(x, torch.tensor(classes)), + lambda x: x.cross_entropy(Tensor(classes))) + self.helper_test_exception([(32,10), (32,1)], lambda x,y: torch.nn.functional.cross_entropy(x, y), + lambda x,y: x.cross_entropy(y), expected=(AssertionError, RuntimeError)) + + def test_cross_entropy_reductions(self): + for r in ("mean", "sum", "none"): + helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.cross_entropy(x, y, reduction=r), + lambda x,y: x.cross_entropy(y, reduction=r)) + self.helper_test_exception([(32,10), (32,10)], lambda x,y: torch.nn.functional.cross_entropy(x, y, reduction="typo"), + lambda x,y: x.cross_entropy(y, reduction="typo"), expected=ValueError) + + def test_cross_entropy_smoothing(self): + for ls in (0., 0.3, 0.7, 1.): + helper_test_op([(32,10), (32,10)], lambda x,y: torch.nn.functional.cross_entropy(x, y, label_smoothing=ls), + lambda x,y: x.cross_entropy(y, label_smoothing=ls)) + classes = np.random.randint(0, 10, (32,), dtype=np.int32).tolist() + helper_test_op([(32,10)], lambda x: torch.nn.functional.cross_entropy(x, torch.tensor(classes), label_smoothing=ls), + lambda x: x.cross_entropy(Tensor(classes), label_smoothing=ls)) + + def test_nll_loss(self): + target = np.random.randint(0, 10, (32,), dtype=np.int32).tolist() + helper_test_op([(32,10)], + lambda x: torch.nn.functional.nll_loss(torch.nn.functional.log_softmax(x, dim=1), torch.tensor(target)), + lambda x: x.log_softmax(axis=1).nll_loss(Tensor(target))) + + def test_nll_loss_3d(self): + target = np.random.randint(0, 10, (32,3,3,3), dtype=np.int32).tolist() + helper_test_op([(32,10,3,3,3)], + lambda x: torch.nn.functional.nll_loss(torch.nn.functional.log_softmax(x, dim=1), torch.tensor(target)), + lambda x: x.log_softmax(axis=1).nll_loss(Tensor(target))) + + def test_nll_loss_reductions(self): + target = np.random.randint(0, 10, (32,), dtype=np.int32).tolist() + for r in ("mean", "sum", "none"): + helper_test_op([(32,10)], + lambda x: torch.nn.functional.nll_loss(torch.nn.functional.log_softmax(x, dim=1), torch.tensor(target), reduction=r), + lambda x: x.log_softmax(axis=1).nll_loss(Tensor(target), reduction=r)) + self.helper_test_exception([(32,10)], + lambda x: torch.nn.functional.nll_loss(x, torch.tensor(target), reduction="typo"), + lambda x: x.nll_loss(Tensor(target), reduction="typo"), expected=ValueError) + + def test_nll_loss_weight(self): + target = np.random.randint(0, 10, (32,), dtype=np.int32).tolist() + weight = np.random.normal(0, 1, (10,)).astype(np.float32).tolist() + for r in ("mean", "sum", "none"): + helper_test_op([(32,10)], + lambda x: torch.nn.functional.nll_loss(torch.nn.functional.log_softmax(x, dim=1), torch.tensor(target), torch.tensor(weight), reduction=r), + lambda x: x.log_softmax(axis=1).nll_loss(Tensor(target), Tensor(weight), reduction=r)) + + def test_nll_loss_3d_weight(self): + target = np.random.randint(0, 10, (32,3,3,3), dtype=np.int32).tolist() + weight = np.random.normal(0, 1, (10,)).astype(np.float32).tolist() + for r in ("mean", "sum", "none"): + helper_test_op([(32,10,3,3,3)], + lambda x: torch.nn.functional.nll_loss(torch.nn.functional.log_softmax(x, dim=1), torch.tensor(target), torch.tensor(weight), reduction=r), + lambda x: x.log_softmax(axis=1).nll_loss(Tensor(target), Tensor(weight), reduction=r)) + + def test_nll_loss_ignore_index(self): + logits = [[2.0, 0.5, -1.0], + [1.5, 2.5, -0.5], + [0.0, -2.0, 1.0]] + target = [0, 1, 2] + helper_test_op(None, lambda x: torch.nn.functional.nll_loss(torch.nn.functional.log_softmax(x, dim=1), torch.tensor(target), ignore_index=1), + lambda x: x.log_softmax().nll_loss(Tensor(target), ignore_index=1), + vals=[logits]) + + def test_one_hot(self): + data = [1, 2, 4] + helper_test_op([], lambda: torch.nn.functional.one_hot(torch.tensor(data), 6).type(torch.int32), + lambda: Tensor(data).one_hot(6), forward_only=True) + helper_test_op([], lambda: torch.nn.functional.one_hot(torch.tensor(data)).type(torch.int32), + lambda: Tensor(data).one_hot(), forward_only=True) + data = [[[1, 2, 3], [0, 3, 5]], [[1, 2, 3], [0, 3, 5]]] + helper_test_op([], lambda: torch.nn.functional.one_hot(torch.tensor(data), 8).type(torch.int32), + lambda: Tensor(data).one_hot(8), forward_only=True) + helper_test_op([], lambda: torch.nn.functional.one_hot(torch.tensor(data)).type(torch.int32), + lambda: Tensor(data).one_hot(), forward_only=True) + + def test_masked_fill(self): + helper_test_op([(32,10)], lambda x: x.masked_fill((x>0.1).detach(), -math.inf)) + helper_test_op([(32,10)], lambda x: x.masked_fill((x<0.1).detach(), -math.inf)) + + def test_masked_select(self): + helper_test_op([(32, 10)], lambda x: x.masked_select(x>0.5), lambda x: x.masked_select(x>0.5), forward_only=True) + helper_test_op([(32, 10)], lambda x: x.masked_select(torch.tensor(True)), lambda x: x.masked_select(Tensor(True)), forward_only=True) + + @unittest.skipIf(Device.DEFAULT == "QCOM", "OpenCL fails to compile this (both on GPU(qcom)/QCOM backends)") + def test_cast(self): + helper_test_op([(3, 3)], lambda x: x.float()) + helper_test_op(None, lambda x: x.float(), vals=[[0, 1, 2, 3]], forward_only=True) + helper_test_op(None, lambda x: x.float(), vals=[[True, False]], forward_only=True) + helper_test_op([(3, 3)], lambda x: x.int(), forward_only=True) + helper_test_op([(3, 3)], lambda x: x.bool(), forward_only=True) + + def test_bitcast(self): + helper_test_op([(3, 3)], lambda x: x.view(torch.int32), lambda x: x.bitcast(dtypes.int32), forward_only=True) + +@unittest.skipUnless(is_dtype_supported(dtypes.uchar), f"no uint8 on {Device.DEFAULT}") +class TestOpsUint8(unittest.TestCase): + def test_cast(self): + helper_test_op([(2,3,64,64)], lambda x: x.type(torch.uint8), lambda x: x.cast('uint8'), forward_only=True) + + def test_cast_relu(self): + helper_test_op([(2,3,64,64)], lambda x: x.relu().type(torch.uint8), lambda x: x.relu().cast('uint8'), forward_only=True) + + def test_interpolate_bilinear(self): + out_sz = (10, 10) + helper_test_op([(2,3,64,64)], + lambda x: torch.nn.functional.interpolate((10*x).relu().type(torch.uint8), size=out_sz, mode="bilinear"), + lambda x: Tensor.interpolate((10*x).relu().cast('uint8'), size=out_sz, mode="linear"), forward_only=True) + + def test_interpolate_nearest(self): + out_sz = (10, 10) + helper_test_op([(2,3,64,64)], + lambda x: torch.nn.functional.interpolate((10*x).relu().type(torch.uint8), size=out_sz, mode="nearest"), + lambda x: Tensor.interpolate((10*x).relu().cast('uint8'), size=out_sz, mode="nearest"), forward_only=True) + + def test_interpolate_nearest_exact(self): + out_sz = (10, 10) + helper_test_op([(2,3,64,64)], + lambda x: torch.nn.functional.interpolate((10*x).relu().type(torch.uint8), size=out_sz, mode="nearest-exact"), + lambda x: Tensor.interpolate((10*x).relu().cast('uint8'), size=out_sz, mode="nearest-exact"), forward_only=True) + + def test_min(self): + helper_test_op(None, + lambda x: x.type(torch.uint8).min(), + lambda x: x.cast(dtypes.uint8).min(), forward_only=True, vals=[[[0, 1, 2], [3, 4, 5]]]) + helper_test_op(None, + lambda x: x.type(torch.uint8).min(), + lambda x: x.cast(dtypes.uint8).min(), forward_only=True, vals=[[0, 128, 255, 64, 32, 16]]) + +if __name__ == '__main__': + np.random.seed(1337) + unittest.main(verbosity=2) diff --git a/tinygrad_repo/test/test_opt_gemm.py b/tinygrad_repo/test/test_opt_gemm.py new file mode 100644 index 000000000..f38caf2f3 --- /dev/null +++ b/tinygrad_repo/test/test_opt_gemm.py @@ -0,0 +1,45 @@ +import numpy as np +import unittest +from tinygrad import Tensor +from tinygrad.helpers import get_single_element +from tinygrad.opt.kernel import Kernel, Opt, OptOps +from tinygrad.engine.realize import CompiledRunner, ExecItem + +class TestOptGemm(unittest.TestCase): + @classmethod + def setUpClass(cls): + N = 64 + cls.a = Tensor.randn(N, N).contiguous().realize() + cls.b = Tensor.randn(N, N).contiguous().realize() + cls.res = cls.a.T.numpy() @ cls.b.T.numpy() + + def _test_gemm_unrolled_permute_l(self, opts=[]): + t = self.a.T @ self.b.T + # TODO: this should be a generic test helper + si = get_single_element(t.schedule()) + k = Kernel(si.ast) + k.apply_opts(opts) + run = CompiledRunner(k.to_program()) + ExecItem(run, si.bufs).run() + test = si.bufs[0].numpy().reshape(self.res.shape) + np.testing.assert_allclose(self.res, test, atol=1e-4) + + def test_gemm_unrolled_permute_l_44(self): + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=4)] + self._test_gemm_unrolled_permute_l(opts) + + def test_gemm_unrolled_permute_l_424(self): + # was failing with LLVM + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=2), Opt(op=OptOps.UPCAST, axis=0, arg=4)] + self._test_gemm_unrolled_permute_l(opts) + + def test_gemm_unrolled_permute_l_42(self): + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UPCAST, axis=1, arg=2)] + self._test_gemm_unrolled_permute_l(opts) + + def test_gemm_unrolled_permute_l_22(self): + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=2), Opt(op=OptOps.UPCAST, axis=1, arg=2)] + self._test_gemm_unrolled_permute_l(opts) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_optim.py b/tinygrad_repo/test/test_optim.py new file mode 100644 index 000000000..283378e70 --- /dev/null +++ b/tinygrad_repo/test/test_optim.py @@ -0,0 +1,136 @@ +import numpy as np +import torch +import unittest +from tinygrad import Tensor, Device, dtypes +from tinygrad.nn.optim import Adam, SGD, AdamW +from tinygrad.helpers import CI +from tinygrad.device import is_dtype_supported + +np.random.seed(1337) +x_init = np.random.randn(1,4).astype(np.float32) +W_init = np.random.randn(4,4).astype(np.float32) +m_init = np.random.randn(1,4).astype(np.float32) + +class TeenyNet: + def __init__(self, tensor): + self.x = tensor(x_init.copy(), requires_grad=True) + self.W = tensor(W_init.copy(), requires_grad=True) + def forward(self): + return (self.x * self.W).sum() + +class TinyNet: + def __init__(self, tensor): + self.x = tensor(x_init.copy(), requires_grad=True) + self.W = tensor(W_init.copy(), requires_grad=True) + self.m = tensor(m_init.copy()) + + def forward(self): + out = self.x.matmul(self.W).relu() + # print(out.detach().numpy()) + out = out.log_softmax(1) + out = out.mul(self.m).add(self.m).sum() + return out + +def step(tensor, optim, steps=1, teeny=False, **kwargs): + net = TeenyNet(tensor) if teeny else TinyNet(tensor) + optim = optim([net.x, net.W], **kwargs) + for _ in range(steps): + out = net.forward() + optim.zero_grad() + out.backward() + optim.step() + return net.x.detach().numpy(), net.W.detach().numpy() + +@unittest.skipIf(CI and Device.DEFAULT in {"CUDA", "NV"}, "slow") +class TestOptim(unittest.TestCase): + def setUp(self): + self.old_training = Tensor.training + Tensor.training = True + def tearDown(self): + Tensor.training = self.old_training + + def _test_optim(self, tinygrad_optim, torch_optim, steps, opts, atol, rtol): + for x,y in zip(step(Tensor, tinygrad_optim, steps, **opts), + step(torch.tensor, torch_optim, steps, **opts)): + np.testing.assert_allclose(x, y, atol=atol, rtol=rtol) + + def _test_sgd(self, steps, opts, atol, rtol): self._test_optim(SGD, torch.optim.SGD, steps, opts, atol, rtol) + def _test_adam(self, steps, opts, atol, rtol): self._test_optim(Adam, torch.optim.Adam, steps, opts, atol, rtol) + def _test_adamw(self, steps, opts, atol, rtol): self._test_optim(AdamW, torch.optim.AdamW, steps, opts, atol, rtol) + + def test_multistep_sgd_high_lr_teeny(self): self._test_sgd(2, {'lr': 1.1, 'teeny': True}, 1e-6, 1e-5) + def test_multistep_adam_high_lr_teeny(self): self._test_adam(2, {'lr': 1.1, 'teeny': True}, 2e-4, 5e-4) + + def test_sgd(self): self._test_sgd(1, {'lr': 0.001}, 1e-6, 0) + def test_sgd_high_lr(self): self._test_sgd(1, {'lr': 10}, 1e-6, 1e-5) + def test_sgd_wd(self): self._test_sgd(1, {'lr': 0.001, 'weight_decay': 0.1}, 1e-6, 0) + def test_sgd_high_lr_wd(self): self._test_sgd(1, {'lr': 10, 'weight_decay': 0.1}, 1e-6, 1e-5) + + def test_multistep_sgd(self): self._test_sgd(10, {'lr': 0.001}, 1e-6, 0) + def test_multistep_sgd_high_lr(self): self._test_sgd(10, {'lr': 10}, 1e-6, 3e-4) + def test_multistep_sgd_wd(self): self._test_sgd(10, {'lr': 0.001, 'weight_decay': 0.1}, 1e-6, 0) + def test_multistep_sgd_high_lr_wd(self): self._test_sgd(10, {'lr': 9, 'weight_decay': 0.1}, 1e-6, 3e-4) + + def test_multistep_sgd_momentum(self): self._test_sgd(10, {'lr': 0.001, 'momentum': 0.9}, 1e-6, 0) + def test_multistep_sgd_high_lr_momentum(self): self._test_sgd(10, {'lr': 10, 'momentum': 0.9}, 1e-5, 3e-4) + def test_multistep_sgd_momentum_wd(self): self._test_sgd(10, {'lr': 0.001, 'momentum': 0.9, 'weight_decay': 0.1}, 1e-6, 0) + def test_multistep_sgd_high_lr_momentum_wd(self): self._test_sgd(10, {'lr': 10, 'momentum': 0.9, 'weight_decay': 0.1}, 1e-5, 3e-4) + + def test_multistep_sgd_nesterov_momentum(self): self._test_sgd(10, {'lr': 0.001, 'momentum': 0.9, 'nesterov': True}, 1e-5, 0) + def test_multistep_sgd_high_lr_nesterov_momentum(self): self._test_sgd(10, {'lr': 10, 'momentum': 0.9, 'nesterov': True}, 1e-5, 3e-4) + def test_multistep_sgd_nesterov_momentum_wd(self): + self._test_sgd(10, {'lr': 0.001, 'momentum': 0.9, 'nesterov': True, 'weight_decay': 0.1}, 1e-5, 0) + def test_multistep_sgd_high_lr_nesterov_momentum_wd(self): + self._test_sgd(10, {'lr': 9, 'momentum': 0.9, 'nesterov': True, 'weight_decay': 0.1}, 1e-5, 3e-4) + + def test_adam(self): self._test_adam(1, {'lr': 0.001}, 1e-5, 0) + def test_adam_high_lr(self): self._test_adam(1, {'lr': 10}, 1e-4, 1e-4) + def test_adamw(self): self._test_adamw(1, {'lr': 0.001}, 1e-5, 0) + def test_adamw_high_lr(self): self._test_adamw(1, {'lr': 10}, 1e-4, 1e-4) + + def test_multistep_adam(self): self._test_adam(10, {'lr': 0.001}, 1e-5, 0) + def test_multistep_adam_high_lr(self): self._test_adam(10, {'lr': 10}, 2e-3, 5e-4) + + def test_multistep_adamw(self): self._test_adamw(10, {'lr': 0.001}, 1e-5, 0) + def test_multistep_adamw_high_lr(self): self._test_adamw(10, {'lr': 10}, 5e-4, 2e-3) + + def test_duped_weights(self): + for Opt in [Adam, AdamW, SGD]: + losses = [] + for i in range(2): + w = Tensor(x_init.copy()) + opt = Opt([w], lr=0.1) if i == 0 else Opt([w, w], lr=0.1) + + loss = None + for _ in range(3): + loss = w.sum() + opt.zero_grad() + loss.backward() + opt.step() + losses.append(loss.numpy()) + + np.testing.assert_allclose(losses[0], losses[1], atol=1e-4, rtol=0) + + @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") + def test_mixed_precision(self): + old_default_float, dtypes.default_float = dtypes.default_float, dtypes.half + # weight update would overflow without upcasting + self._test_sgd(10, {'lr': 1e10}, 1e-6, 3e-4) + self._test_adam(1, {'lr': 1e10}, 1e-4, 1e-4) + self._test_adamw(1, {'lr': 1e10}, 1e-4, 1e-4) + dtypes.default_float = old_default_float + + def test_assert_tensor_train(self): + t = Tensor.ones((1,1), requires_grad=True) + optimizer = Adam([t]) + optimizer.zero_grad() + old_state = Tensor.training + t.sum().backward() + Tensor.training = False + self.assertRaises(RuntimeError, optimizer.step) + Tensor.training = True + optimizer.step() + Tensor.training = old_state + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_pickle.py b/tinygrad_repo/test/test_pickle.py new file mode 100644 index 000000000..93758eef6 --- /dev/null +++ b/tinygrad_repo/test/test_pickle.py @@ -0,0 +1,174 @@ +import unittest, pickle, types +import numpy as np +from tinygrad import Tensor, TinyJit, Variable, dtypes +from tinygrad.helpers import GlobalCounters, ContextVar, Context +from tinygrad.uop.ops import PatternMatcher, UPat, UOp, Ops + +class TestPickle(unittest.TestCase): + def test_pickle_code_object(self): + y = lambda x: x*2 # noqa: E731 + code_str = pickle.dumps(y.__code__) + fxn = types.FunctionType(pickle.loads(code_str), globals()) + self.assertEqual(fxn(2), 4) + + def test_pickle_pattern_matcher(self): + pm = PatternMatcher([(UPat.cvar('x'), lambda x: x*2)]) + sink = UOp.const(dtypes.int, 2) + tt = pm.rewrite(sink) + pm_str = pickle.dumps(pm) + pm2 = pickle.loads(pm_str) + self.assertEqual(pm2.rewrite(sink).key, tt.key) + + def test_pickle_main_pattern_matcher(self): + from tinygrad.codegen.devectorizer import sym + ssym = pickle.dumps(sym) + dsym = pickle.loads(ssym) + self.assertEqual(dsym.patterns[0][0].location, sym.patterns[0][0].location) + + def test_pickle_realized_tensor(self): + print("** init") + t = Tensor.rand(10, 10).realize() + st = pickle.dumps(t) + t_values = t.numpy() + del t # free buffers + print("** post pickle") + init = GlobalCounters.kernel_count + t2:Tensor = pickle.loads(st) + np.testing.assert_equal(t_values, t2.numpy()) + # expect at most one COPY kernel + self.assertLessEqual(GlobalCounters.kernel_count-init, 1) + + def test_pickle_realized_tensor_alt(self): + print("** init") + t = Tensor.rand(10, 10).to("CPU").realize() + st = pickle.dumps(t) + t_values = t.numpy() + del t # free buffers + print("** post pickle") + init = GlobalCounters.kernel_count + t2:Tensor = pickle.loads(st) + np.testing.assert_equal(t_values, t2.numpy()) + self.assertEqual(GlobalCounters.kernel_count-init, 0) + + def test_pickle_realized_tensor_alt2(self): + print("** init") + t = Tensor.rand(10, 10).to("CPU").realize() + tensor_uop = t.uop + assert tensor_uop.is_realized, f"expected {tensor_uop} to be realized" + t_values = t.numpy() + # pickle + st = pickle.dumps(t) + # free buffers + del t + del tensor_uop + print("** post pickle") + t2:Tensor = pickle.loads(st) + assert t2.uop.is_realized, f"expected {t2.uop} to be realized" + np.testing.assert_equal(t_values, t2.numpy()) + + # NOTE: currently Buffer exists on the uop, not tensor + def test_pickle_buffer_uop(self): + t = Tensor.arange(4).realize() + a = t.uop + assert a.op is Ops.BUFFER + self.assertIsNotNone(buffer:=a.realized) + s = pickle.dumps(a) + # free buffers + del a + del buffer + a2:UOp = pickle.loads(s) + self.assertListEqual(a2.realized.as_buffer().cast("I").tolist(), [0, 1, 2, 3]) + + def test_pickle_unrealized_tensor(self): + t = Tensor.ones(10, 10) + st = pickle.dumps(t) + t2:Tensor = pickle.loads(st) + np.testing.assert_equal(t.numpy(), t2.numpy()) + + def test_pickle_variable(self): + v = Variable("i", 1, 20).bind(10) + t1 = Tensor.ones(10, v).contiguous() + t2 = Tensor.ones(10, v).contiguous() + ret = (t1+t2).sum(1) + st = pickle.dumps(ret) + del ret + vt2 = pickle.loads(st) + np.testing.assert_equal(vt2.numpy(), 20) + + def test_pickle_buffer_view(self): + t = Tensor.arange(10, device="CPU").contiguous().realize() + vt = t[3:5].contiguous().realize() + assert hasattr(vt.uop.buffer, 'base') + ref_value = vt.tolist() + st = pickle.dumps(vt) + del t, vt + vt2 = pickle.loads(st) + assert hasattr(vt2.uop.buffer, 'base') + assert ref_value == vt2.tolist() + + def test_pickle_numpy(self): + t = Tensor(np.array([1,2,3,4.]), dtype=dtypes.float32) + st = pickle.dumps(t) + t2:Tensor = pickle.loads(st) + np.testing.assert_equal(t.numpy(), t2.numpy()) + + def test_pickle_jit(self): + @TinyJit + def add(a, b): return a.sum()+b+1 + for _ in range(3): add(Tensor.rand(10, 10), Tensor.rand(10, 10)) + st = pickle.dumps(add) + del add + + add_fxn = pickle.loads(st) + x = Tensor.ones(10, 10).contiguous().realize() + y = Tensor.ones(10, 10).contiguous().realize() + print("post jit") + out = add_fxn(x, y) + np.testing.assert_equal(out.numpy(), 102) + + def test_pickle_context_var(self): + v = ContextVar("test_var", 0) + with Context(test_var=1): + vs = pickle.dumps(v) + v2 = pickle.loads(vs) + self.assertEqual(v2.value, 1) + + def test_pickle_schedule(self): + a = Tensor([1,2]) + out = a + 2 + sched = out.schedule() + pk = pickle.dumps(sched) + sched_pk = pickle.loads(pk) + self.assertEqual(sched_pk[-1].ast, sched[-1].ast) + + def test_pickle_renderer(self): + from tinygrad.device import Device + pk = pickle.dumps(Device.default.renderer) + pickle.loads(pk) + +class TestPickleJIT(unittest.TestCase): + @classmethod + def setUpClass(cls): + N = 10 + @TinyJit + def add(a, b): return a.sum()+b+1 + for _ in range(3): add(Tensor.rand(N, N), Tensor.rand(N, N)) + cls.st = pickle.dumps(add) + del add + + def test_inspect(self): + import io + class FakeClass: + def __init__(self, *args, **kwargs): + print(self.module, self.name) + class InspectUnpickler(pickle.Unpickler): + def find_class(self, module, name): return type("SpecializedFakeClass", (FakeClass,), {"name": name, "module": module}) + InspectUnpickler(io.BytesIO(self.st)).load() + + @unittest.skip("we are still saving intermediate buffers") + def test_size(self): + # confirm no intermediate buffers are saved + self.assertLess(len(self.st), 1_000_000) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_profiler.py b/tinygrad_repo/test/test_profiler.py new file mode 100644 index 000000000..c64c27116 --- /dev/null +++ b/tinygrad_repo/test/test_profiler.py @@ -0,0 +1,163 @@ +import unittest, struct, contextlib, statistics +from tinygrad import Device, Tensor, dtypes, TinyJit +from tinygrad.helpers import CI, getenv, Context +from tinygrad.device import Buffer, BufferSpec, Compiled, ProfileRangeEvent, ProfileDeviceEvent, ProfileGraphEvent +from tinygrad.runtime.support.hcq import HCQCompiled +from tinygrad.engine.realize import get_runner + +MOCKGPU = getenv("MOCKGPU") + +@contextlib.contextmanager +def helper_collect_profile(*devs): + for dev in devs: dev.synchronize() + Compiled.profile_events = [x for x in Compiled.profile_events if isinstance(x, ProfileDeviceEvent) and x.device.startswith("METAL")] + + profile_list = [] + with Context(PROFILE=1): + yield profile_list + for dev in devs: dev.synchronize() + for dev in devs: dev._at_profile_finalize() + for x in Compiled.profile_events: profile_list.append(x) + +def helper_profile_filter_device(profile, device:str): + assert any(getattr(x, "device", None) == device and isinstance(x, ProfileDeviceEvent) for x in profile), f"device {device} is not registred" + dev_events = [x for x in profile if getattr(x, "device", None) == device and isinstance(x, ProfileDeviceEvent)] + assert len(dev_events) == 1, "only one device registration event is expected" + return [x for x in profile if getattr(x, "device", None) == device], dev_events[0] + +@unittest.skipUnless(issubclass(type(Device[Device.DEFAULT]), HCQCompiled) or Device.DEFAULT in {"METAL"}, "HCQ device required to run") +class TestProfiler(unittest.TestCase): + @classmethod + def setUpClass(self): + TestProfiler.d0 = Device[Device.DEFAULT] + + TestProfiler.a = Tensor([0.,1.], device=Device.DEFAULT).realize() + TestProfiler.b = self.a + 1 + si = self.b.schedule()[-1] + + TestProfiler.runner = get_runner(TestProfiler.d0.device, si.ast) + TestProfiler.b.uop.buffer.allocate() + + def test_profile_kernel_run(self): + runner_name = TestProfiler.runner._prg.name + with helper_collect_profile(TestProfiler.d0) as profile: + TestProfiler.runner([TestProfiler.b.uop.buffer, TestProfiler.a.uop.buffer], var_vals={}) + + profile, _ = helper_profile_filter_device(profile, TestProfiler.d0.device) + kernel_runs = [x for x in profile if isinstance(x, ProfileRangeEvent)] + assert len(kernel_runs) == 1, "one kernel run is expected" + assert kernel_runs[0].name == runner_name, "kernel name is not correct" + assert not kernel_runs[0].is_copy, "kernel should not be copy" + + def test_profile_copyin(self): + buf1 = Buffer(Device.DEFAULT, 2, dtypes.float, options=BufferSpec(nolru=True)).ensure_allocated() + + with helper_collect_profile(TestProfiler.d0) as profile: + buf1.copyin(memoryview(bytearray(struct.pack("ff", 0, 1)))) + + profile, _ = helper_profile_filter_device(profile, TestProfiler.d0.device) + kernel_runs = [x for x in profile if isinstance(x, ProfileRangeEvent)] + assert len(kernel_runs) == 1, "one kernel run is expected" + assert kernel_runs[0].is_copy, "kernel should be copy" + + def test_profile_multiops(self): + runner_name = TestProfiler.runner._prg.name + buf1 = Buffer(Device.DEFAULT, 2, dtypes.float, options=BufferSpec(nolru=True)).ensure_allocated() + + with helper_collect_profile(TestProfiler.d0) as profile: + buf1.copyin(memoryview(bytearray(struct.pack("ff", 0, 1)))) + TestProfiler.runner([buf1, TestProfiler.a.uop.buffer], var_vals={}) + buf1.copyout(memoryview(bytearray(buf1.nbytes))) + + profile, _ = helper_profile_filter_device(profile, TestProfiler.d0.device) + evs = [x for x in profile if isinstance(x, ProfileRangeEvent)] + + assert len(evs) == 3, "3 kernel runs are expected" + assert evs[0].is_copy, "kernel should be copy" + assert evs[1].name == runner_name, "kernel name is not correct" + assert not evs[1].is_copy, "kernel should not be copy" + assert evs[2].is_copy, "kernel should be copy" + + for i in range(1, 3): + assert evs[i].st > evs[i-1].en, "timestamp not aranged" + + def test_profile_multidev(self): + d1 = Device[f"{Device.DEFAULT}:1"] + buf1 = Buffer(Device.DEFAULT, 2, dtypes.float, options=BufferSpec(nolru=True)).ensure_allocated() + buf2 = Buffer(f"{Device.DEFAULT}:1", 2, dtypes.float, options=BufferSpec(nolru=True)).ensure_allocated() + + with helper_collect_profile(TestProfiler.d0, d1) as profile: + buf1.copyin(memoryview(bytearray(struct.pack("ff", 0, 1)))) + buf2.copyin(memoryview(bytearray(struct.pack("ff", 0, 1)))) + + profile0, _ = helper_profile_filter_device(profile, TestProfiler.d0.device) + profile1, _ = helper_profile_filter_device(profile, d1.device) + + for p in [profile0, profile1]: + evs = [x for x in p if isinstance(x, ProfileRangeEvent)] + assert len(evs) == 1, "one kernel runs are expected" + assert evs[0].is_copy, "kernel should be copy" + + def test_profile_multidev_transfer(self): + d1 = Device[f"{Device.DEFAULT}:1"] + + buf1 = Tensor.randn(10, 10, device=f"{Device.DEFAULT}:0").realize() + with helper_collect_profile(TestProfiler.d0, d1) as profile: + buf1.to(f"{Device.DEFAULT}:1").realize() + + profile0, _ = helper_profile_filter_device(profile, TestProfiler.d0.device) + kernel_runs = [x for x in profile0 if isinstance(x, ProfileRangeEvent)] + assert len(kernel_runs) == 1, "one kernel run is expected" + assert kernel_runs[0].is_copy, "kernel should be copy" + + @unittest.skipIf(Device.DEFAULT in "METAL" or (MOCKGPU and Device.DEFAULT == "AMD"), "AMD mockgpu does not support queue wait interrupts") + def test_profile_graph(self): + d1 = Device[f"{Device.DEFAULT}:1"] + + def f(a): + x = (a + 1).realize() + return x, x.to(d1.device).realize() + + a = Tensor.randn(10, 10, device=TestProfiler.d0.device).realize() + with helper_collect_profile(TestProfiler.d0, d1) as profile: + jf = TinyJit(f) + for _ in range(3): jf(a) + del jf + + graph_evs = [x for x in profile if isinstance(x, ProfileGraphEvent)] + + _, _ = helper_profile_filter_device(profile, TestProfiler.d0.device) + _, _ = helper_profile_filter_device(profile, d1.device) + + assert len(graph_evs) == 1, "one graph event is expected" + assert len(graph_evs[0].ents) == 2, "two entities are expected" + + @unittest.skipIf(CI or not issubclass(type(Device[Device.DEFAULT]), HCQCompiled), "skip CI") + def test_dev_jitter_matrix(self): + dev_cnt = 6 + devs = [Device[f"{Device.DEFAULT}:{i}"] for i in range(dev_cnt)] + for dev in devs: dev.synchronize() + for dev in devs: dev._at_profile_finalize() + + def _sync_d2d(d1:HCQCompiled, d2:HCQCompiled): + d1.hw_compute_queue_t().signal(d1.timeline_signal, d1.timeline_value).wait(d2.timeline_signal, d2.timeline_value) \ + .timestamp(d1.timeline_signal).signal(d1.timeline_signal, d1.timeline_value+1).submit(d1) + d2.hw_compute_queue_t().signal(d2.timeline_signal, d2.timeline_value).wait(d1.timeline_signal, d1.timeline_value) \ + .timestamp(d2.timeline_signal).signal(d2.timeline_signal, d2.timeline_value+1).submit(d2) + d1.timeline_value += 2 + d2.timeline_value += 2 + d1.timeline_signal.wait(d1.timeline_value - 1) + d2.timeline_signal.wait(d2.timeline_value - 1) + return d2.timeline_signal.timestamp - d1.timeline_signal.timestamp + + # then test it by timing the GPU to GPU times + jitter_matrix = [[float('nan')] * len(devs) for _ in range(len(devs))] + pairs = [(p1, p2) for p1 in enumerate(devs) for p2 in enumerate(devs) if p1 != p2] + for (i1, d1), (i2, d2) in pairs: + cpu_diff = d1.gpu2cpu_compute_time_diff - d2.gpu2cpu_compute_time_diff + jitter_matrix[i1][i2] = statistics.median(_sync_d2d(d1, d2) - _sync_d2d(d2, d1) for _ in range(20)) / 2 - cpu_diff + assert abs(jitter_matrix[i1][i2]) < 0.5, "jitter should be less than 0.5ms" + print("pairwise clock jitter matrix (us):\n" + '\n'.join([''.join([f'{float(item):8.3f}' for item in row]) for row in jitter_matrix])) + +if __name__ == "__main__": + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/test_quantize_onnx.py b/tinygrad_repo/test/test_quantize_onnx.py new file mode 100644 index 000000000..7b1dd2747 --- /dev/null +++ b/tinygrad_repo/test/test_quantize_onnx.py @@ -0,0 +1,368 @@ +# ruff: noqa: E501 +import numpy as np +import unittest +from dataclasses import replace +from tinygrad import Tensor, Context, Device, dtypes +from tinygrad.uop.ops import Ops, UOp # noqa: F401 # pylint: disable=unused-import +from tinygrad.opt.kernel import Kernel, Opt, OptOps +from tinygrad.engine.realize import CompiledRunner, ExecItem, lower_schedule_item +from tinygrad.opt.search import bufs_from_lin +from tinygrad.shape.shapetracker import ShapeTracker, View # noqa: F401 # pylint: disable=unused-import + +N = 512 + +def create_gemm_model(model_path:str, batch_size=N, in_size=N, out_size=N, bias=False): + import onnx + from onnx import helper, numpy_helper, TensorProto + # Define input and output + input_tensor = helper.make_tensor_value_info("input", TensorProto.FLOAT, [batch_size, in_size]) + output_tensor = helper.make_tensor_value_info("output", TensorProto.FLOAT, [batch_size, out_size]) + + # Create random weights and bias + W_data = np.random.randn(in_size, out_size).astype(np.float32) + W_init = numpy_helper.from_array(W_data, name="W") + + if bias: + B_data = np.random.randn(out_size).astype(np.float32) + B_init = numpy_helper.from_array(B_data, name="B") + gemm_node = helper.make_node("Gemm", inputs=["input", "W", "B"], outputs=["output"], alpha=1.0, beta=1.0, transB=0) + graph_def = helper.make_graph([gemm_node], "SingleGemmGraph", [input_tensor], [output_tensor], initializer=[W_init, B_init]) + else: + gemm_node = helper.make_node("Gemm", inputs=["input", "W"], outputs=["output"], alpha=1.0, beta=1.0, transB=0) + graph_def = helper.make_graph([gemm_node], "SingleGemmGraph", [input_tensor], [output_tensor], initializer=[W_init]) + + # Create and save the model + model_def = helper.make_model(graph_def, producer_name="single_gemm_example") + onnx.save_model(model_def, model_path) + return model_path + +def sexec(out:Tensor, opts:list[Opt], replace_src=None, run_count=3): + si = out.schedule()[-1] + k = Kernel(si.ast, opts=Device[Device.DEFAULT].renderer) + #opts = [Opt(op=OptOps.UPCAST, axis=0, arg=128)] #, Opt(op=OptOps.UNROLL, axis=0, arg=4)] + k.apply_opts(opts) + prg = k.to_program() + if replace_src is not None: + old_name = prg.src.split("__attribute__((noinline)) void ")[1].split("(")[0] + prg = replace(prg, src=replace_src + "/* DSP boilerplate */" + prg.src.split("/* DSP boilerplate */")[1].replace(old_name, "fxn")) + ei = ExecItem(CompiledRunner(prg), [x.ensure_allocated() for x in si.bufs], si.metadata) + for _ in range(run_count): ei.run(wait=True) + +def get_quantized_model(sz): + from onnxruntime.quantization import quantize_static, QuantFormat, QuantType, CalibrationDataReader + class FakeDataReader(CalibrationDataReader): + def __init__(self): self.cnt = 0 + def get_next(self) -> dict: + self.cnt += 1 + if self.cnt == 100: return None + return {"input": np.random.uniform(size=(sz, sz)).astype(np.float32)} + out_file = "/tmp/test_out.onnx" + quantize_static(create_gemm_model("/tmp/test_in.onnx", sz, sz, sz), out_file, + FakeDataReader(), quant_format=QuantFormat.QDQ, per_channel=False, reduce_range=False, + activation_type=QuantType.QUInt8, weight_type=QuantType.QInt8, + extra_options={"ActivationSymmetric": False}) + return out_file + +@unittest.skipIf(Device.DEFAULT != "CPU", "only tests for CPU") +class TestQuantizeOnnxCPU(unittest.TestCase): + def test_quant_128(self, sz=128): + try: + import onnx # noqa: F401 # pylint: disable=unused-import + except ImportError: + raise unittest.SkipTest() + from tinygrad.frontend.onnx import OnnxRunner, onnx_load + out_file = get_quantized_model(sz) + onnx_model = onnx_load(out_file) + run_onnx = OnnxRunner(onnx_model) + inp = Tensor(np.random.uniform(size=(sz, sz)).astype(np.float32)) + with Context(DONT_REALIZE_EXPAND=1, QUANTIZE=1): + sched = run_onnx({"input":inp})["output"].schedule() + ei = lower_schedule_item(sched[-2]) + daccs = [u for u in ei.prg.p.uops if u.op is Ops.DEFINE_ACC] + assert all(u.dtype.scalar() is dtypes.int for u in daccs) + +@unittest.skipIf(Device.DEFAULT != "DSP", "only tests for DSP") +class TestQuantizeOnnx(unittest.TestCase): + def test_quant_128(self): self.test_quant(128) + def test_quant(self, sz=512): + from examples.benchmark_onnx import load_onnx_model + # divide is ~1500-2000 without reduce_range, 750-900 with it + out_file = get_quantized_model(sz) + run_onnx_jit, _ = load_onnx_model(out_file) + with Context(DONT_REALIZE_EXPAND=1): + run_onnx_jit(input=Tensor(np.random.uniform(size=(sz, sz)).astype(np.float32))) + + def test_prequant_conv2d_1x1(self): + X = Tensor(np.random.uniform(0, 255, size=(1, 32, 128, 128)).astype(np.uint8)) + W = Tensor(np.random.uniform(0, 255, size=(64, 32, 1, 1)).astype(np.uint8)) + out = X.conv2d(W, dtype=X.dtype) + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=128), Opt(op=OptOps.UNROLL, axis=0, arg=4)] + sexec(out, opts) + + def test_prequant_gemm(self): + N = 512 + X = Tensor(np.random.uniform(0, 255, size=(N,N)).astype(np.uint8)) + W = Tensor(np.random.uniform(0, 255, size=(N,N)).astype(np.uint8)) + out = X.matmul(W, dtype=X.dtype) + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=128), Opt(op=OptOps.UNROLL, axis=0, arg=4)] + sexec(out, opts) + + # TODO: this has to work + def test_prequant_gemm_intacc_early(self, xi=np.int8, wi=np.int8): + N = 512 + X = Tensor(np.random.uniform(0, 255, size=(N,N)).astype(xi)) + W = Tensor(np.random.uniform(0, 255, size=(N,N)).astype(wi)) + with Context(DONT_REALIZE_EXPAND=1): + # this divide is interesting and forces the accumulator to actually be an int + out = (X.cast("int").matmul(W.cast("int"))//1000).cast("int8") + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=128), Opt(op=OptOps.UNROLL, axis=0, arg=4)] + sexec(out, opts) + + def test_prequant_gemm_handcode(self): + src = """typedef int int128 __attribute__((aligned(512),vector_size(512))); + typedef int int32 __attribute__((aligned(128),vector_size(128))); + typedef int int64 __attribute__((aligned(256),vector_size(256))); + typedef unsigned char unsigned_char4 __attribute__((aligned(4),vector_size(4))); + typedef signed char signed_char128 __attribute__((aligned(128),vector_size(128))); + typedef unsigned char unsigned_char128 __attribute__((aligned(128),vector_size(128))); + typedef unsigned char unsigned_char256 __attribute__((aligned(256),vector_size(256))); + union V256 { + unsigned_char256 vec256; + struct { + unsigned_char128 lo128; + unsigned_char128 hi128; + }; + }; + __attribute__((noinline)) void fxn(unsigned char* restrict __attribute__((align_value(128))) data0, + unsigned char* restrict __attribute__((align_value(128))) data1, + signed char* restrict __attribute__((align_value(128))) data2) { + for (int ridx0 = 0; ridx0 < 512; ridx0++) { + int alu0 = (ridx0<<9); + for (int ridx1 = 0; ridx1 < 4; ridx1++) { + int alu1 = (ridx1<<7); + int32 acc0 = __builtin_HEXAGON_V6_vd0_128B(); + int32 acc1 = __builtin_HEXAGON_V6_vd0_128B(); + int32 acc2 = __builtin_HEXAGON_V6_vd0_128B(); + int32 acc3 = __builtin_HEXAGON_V6_vd0_128B(); + + for (int ridx2 = 0; ridx2 < 128; ridx2++) { + unsigned_char4 val0 = *((unsigned_char4*)((data1+(alu0+(ridx2<<2))))); + int alu2 = (alu1+(ridx2<<11)); + signed_char128 x0 = *((signed_char128*)((data2+alu2))); + signed_char128 x1 = *((signed_char128*)((data2+(alu2+512)))); + signed_char128 x2 = *((signed_char128*)((data2+(alu2+1024)))); + signed_char128 x3 = *((signed_char128*)((data2+(alu2+1536)))); + + union V256 ss01; + // ss01.lo128 = (x0[0], x1[0], x0[2], x1[2], x0[4], x1[4], ...) + // ss01.hi128 = (x0[1], x1[1], x0[3], x1[3], x0[5], x1[5], ...) + ss01.vec256 = __builtin_HEXAGON_V6_vshufoeb_128B(x1, x0); + + union V256 ss23; + // ss23.lo128 = (x2[0], x3[0], x2[2], x3[2], x2[4], x3[4], ...) + // ss23.hi128 = (x2[1], x3[1], x2[3], x3[3], x2[5], x3[5], ...) + ss23.vec256 = __builtin_HEXAGON_V6_vshufoeb_128B(x3, x2); + + union V256 sslo; + // sslo.lo128 = (x0[0], x1[0], x2[0], x3[0], x0[4], x1[4], ...) + // sslo.hi128 = (x0[2], x1[2], x2[2], x3[2], x0[6], x1[6], ...) + sslo.vec256 = __builtin_HEXAGON_V6_vdealvdd_128B(ss23.lo128, ss01.lo128, 2); + + union V256 sshi; + // sshi.lo128 = (x0[1], x1[1], x2[1], x3[1], x0[5], x1[5], ...) + // sshi.hi128 = (x0[3], x1[3], x2[3], x3[3], x0[7], x1[7], ...) + sshi.vec256 = __builtin_HEXAGON_V6_vdealvdd_128B(ss23.hi128, ss01.hi128, 2); + + //unsigned_char128 w0 = (unsigned_char128){val0[0],val0[1],val0[2],val0[3],val0[0],val0[1],val0[2],val0[3],... + unsigned_char128 w0 = __builtin_HEXAGON_V6_lvsplatw_128B(*((unsigned int*)&val0)); + + acc0 = __builtin_HEXAGON_V6_vrmpybusv_acc_128B(acc0, w0, sslo.lo128); + acc1 = __builtin_HEXAGON_V6_vrmpybusv_acc_128B(acc1, w0, sshi.lo128); + acc2 = __builtin_HEXAGON_V6_vrmpybusv_acc_128B(acc2, w0, sslo.hi128); + acc3 = __builtin_HEXAGON_V6_vrmpybusv_acc_128B(acc3, w0, sshi.hi128); + } + acc0 /= 1000; + acc1 /= 1000; + acc2 /= 1000; + acc3 /= 1000; + // ','.join([f"acc{j}[{i}]" for i in range(32) for j in range(4)]) + // acc0[0], acc0[1], acc0[2], ..... acc3[30], acc3[31] + unsigned_char128 packed = __builtin_HEXAGON_V6_vpackhub_sat_128B(__builtin_HEXAGON_V6_vpackwh_sat_128B(acc3, acc2), + __builtin_HEXAGON_V6_vpackwh_sat_128B(acc1, acc0)); + packed = __builtin_HEXAGON_V6_vshuffb_128B(packed); + packed = __builtin_HEXAGON_V6_vshuffb_128B(packed); + // acc0[0], acc1[0], acc2[0], ..... acc2[31], acc3[31] + *((unsigned_char128*)((data0+(alu0+alu1)))) = packed; + } + } + }""" + self.test_prequant_gemm_intacc(np.uint8, np.int8, src) + + def test_prequant_gemm_intacc_32(self): + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=0), Opt(op=OptOps.UPCAST, axis=0, arg=4), Opt(op=OptOps.UNROLL, axis=0, arg=0)] + self.test_prequant_gemm_intacc(np.uint8, np.int8, N=32, opts=opts) + def test_prequant_gemm_intacc_128(self): self.test_prequant_gemm_intacc(np.uint8, np.int8, N=128) + def test_prequant_gemm_intacc_256(self): self.test_prequant_gemm_intacc(np.uint8, np.int8, N=256) + def test_prequant_gemm_intacc(self, xi=np.uint8, wi=np.uint8, replace_src=None, N=512, clip=True, opts=None): + X = Tensor(m1:=(np.random.uniform(0, 255, size=(N,N)).astype(xi))).realize() + W = Tensor(m2:=(np.random.uniform(0, 255, size=(N,N)).astype(wi))).realize() + # ugh, it's so broken with those casts. need DONT_REALIZE_EXPAND=1 python3 test/test_quantize_onnx.py TestQuantizeOnnx.test_prequant + tg_dtype = dtypes.int8 if xi == np.int8 else dtypes.uint8 + with Context(DONT_REALIZE_EXPAND=1): + out = (X.int().matmul(W.int())//1000) + if clip: out = out.clip(dtypes.min(tg_dtype),dtypes.max(tg_dtype)) + out = out.cast(tg_dtype) + opts = [Opt(op=OptOps.UPCAST, axis=1, arg=128), Opt(op=OptOps.UNROLL, axis=0, arg=4)] if opts is None else opts + sexec(out, opts, replace_src, run_count=1) + tout = out.numpy() + mout = ((m1.astype(np.int32) @ m2.astype(np.int32)) // 1000) + if clip: mout = mout.clip(dtypes.min(tg_dtype),dtypes.max(tg_dtype)) + mout = mout.astype(xi) + print(tout) + print(mout) + np.testing.assert_equal(tout, mout) + + def test_prequant_gemm_intacc_wi(self): self.test_prequant_gemm_intacc(wi=np.int8) + def test_prequant_gemm_intacc_xiwi(self): self.test_prequant_gemm_intacc(xi=np.int8, wi=np.int8) + def test_prequant_gemm_intacc_xiwi_noclip(self): self.test_prequant_gemm_intacc(xi=np.int8, wi=np.int8, clip=False) + + def test_prequant_gemv(self): + N = 2048 + # ugh, it's so broken with those casts. need DONT_REALIZE_EXPAND=1 python3 test/test_quantize_onnx.py TestQuantizeOnnx.test_prequant + X = Tensor(np.random.uniform(0, 255, size=(1,N)).astype(np.uint8)).realize() + W = Tensor(np.random.uniform(0, 255, size=(N,N)).astype(np.uint8)).realize() + #out = X.cast(dtypes.int) @ W.cast(dtypes.int) + #out = X @ W + out = X.matmul(W, dtype=X.dtype) + opts = [Opt(op=OptOps.UPCAST, axis=0, arg=128), Opt(op=OptOps.UNROLL, axis=0, arg=4)] + sexec(out, opts) + +@unittest.skipIf(Device.DEFAULT != "DSP", "only tests for DSP") +class TestDSPCache(unittest.TestCase): + def test_cache_speed(self): + # string becuase this breaks Python language server for syntax highlight for some reason + ast = eval("""UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.uchar.ptr(25088), arg=ShapeTracker(views=(View(shape=(1, 28, 28, 32, 1), strides=(0, 896, 32, 1, 0), offset=0, mask=None, contiguous=True),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(25088), arg=0, src=()),)), + UOp(Ops.CAST, dtypes.uchar, arg=None, src=( + UOp(Ops.XOR, dtypes.int, arg=None, src=( + UOp(Ops.MAX, dtypes.int, arg=None, src=( + UOp(Ops.XOR, dtypes.int, arg=None, src=( + UOp(Ops.MAX, dtypes.int, arg=None, src=( + UOp(Ops.CAST, dtypes.int, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.ADD, (4,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.int, arg=None, src=( + UOp(Ops.LOAD, dtypes.uchar, arg=None, src=( + UOp(Ops.VIEW, dtypes.uchar.ptr(150528), arg=ShapeTracker(views=(View(shape=(1, 28, 28, 32, 192), strides=(0, 5376, 192, 0, 1), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.uchar.ptr(150528), arg=1, src=()),)),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=0.012368360534310341, src=( + x22:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 28, 28, 32, 192), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.int, arg=None, src=( + UOp(Ops.LOAD, dtypes.char, arg=None, src=( + UOp(Ops.VIEW, dtypes.char.ptr(6144), arg=ShapeTracker(views=(View(shape=(32, 48, 4), strides=(4, 128, 1), offset=0, mask=None, contiguous=False), View(shape=(1, 28, 28, 32, 192), strides=(0, 0, 0, 192, 1), offset=0, mask=None, contiguous=False))), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.char.ptr(6144), arg=2, src=()),)),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=0.007441135589033365, src=( + x22,)),)),)),)), + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.CAST, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.int, arg=None, src=( + UOp(Ops.VIEW, dtypes.int.ptr(32), arg=ShapeTracker(views=(View(shape=(1, 28, 28, 32, 1), strides=(0, 0, 0, 1, 0), offset=0, mask=None, contiguous=False),)), src=( + UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(32), arg=3, src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=9.203465015161783e-05, src=( + x36:=UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 28, 28, 32, 1), strides=(0, 0, 0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=33.812857328652136, src=( + x36,)),)), + UOp(Ops.CONST, dtypes.float, arg=0.4999999, src=( + x36,)),)), + UOp(Ops.CONST, dtypes.float, arg=136.0, src=( + x36,)),)),)), + UOp(Ops.CONST, dtypes.int, arg=0, src=( + x36,)),)), + x41:=UOp(Ops.CONST, dtypes.int, arg=-1, src=( + x36,)),)), + UOp(Ops.CONST, dtypes.int, arg=-256, src=( + x36,)),)), + x41,)),)),)),))""") + opts = [Opt(op=OptOps.UNROLL, axis=0, arg=8), Opt(op=OptOps.UPCAST, axis=1, arg=32), Opt(op=OptOps.UPCAST, axis=0, arg=4)] + with Context(DEVECTORIZE=0, QUANTIZE=1): + k = Kernel(ast, opts=Device[Device.DEFAULT].renderer) + k.apply_opts(opts) + prg = k.to_program() + #print(prg.src) + + new_src = """ +typedef int int32 __attribute__((aligned(128),vector_size(128))); +typedef signed char signed_char128 __attribute__((aligned(128),vector_size(128))); +typedef unsigned char unsigned_char8 __attribute__((aligned(8),vector_size(8))); +typedef unsigned char unsigned_char4 __attribute__((aligned(4),vector_size(4))); +typedef unsigned char unsigned_char128 __attribute__((aligned(128),vector_size(128))); +__attribute__((noinline)) void r_196_24_8_32_4(unsigned char* restrict __attribute__((align_value(128))) data0, unsigned char* restrict __attribute__((align_value(128))) data1, signed char* restrict __attribute__((align_value( +128))) data2, int* restrict __attribute__((align_value(128))) data3) { + int32 cast0 = (int32){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + int32 val0 = *((int32*)((data3+0))); + for (int ridx0 = 0; ridx0 < 196; ridx0++) { + int32 acc0 = cast0; + int32 acc1 = cast0; + int32 acc2 = cast0; + int32 acc3 = cast0; + __builtin_HEXAGON_Y2_dcfetch(data1+ridx0*768); + __builtin_HEXAGON_Y2_dcfetch(data1+ridx0*768+192); + __builtin_HEXAGON_Y2_dcfetch(data1+ridx0*768+384); + __builtin_HEXAGON_Y2_dcfetch(data1+ridx0*768+576); + for (int ridx1 = 0; ridx1 < 24; ridx1++) { + signed_char128 val1 = *((signed_char128*)((data2+(ridx1<<8)))); + signed_char128 val2 = *((signed_char128*)((data2+((1+(ridx1<<1))<<7)))); + + int alu0 = ((ridx0*768)+(ridx1<<3)); + + unsigned_char8 val3 = *((unsigned_char8*)((data1+alu0))); + __builtin_HEXAGON_Y2_dcfetch(((data1+alu0)+16)); + unsigned_char8 val4 = *((unsigned_char8*)((data1+(alu0+192)))); + __builtin_HEXAGON_Y2_dcfetch(((data1+(alu0+192))+16)); + unsigned_char8 val5 = *((unsigned_char8*)((data1+(alu0+384)))); + __builtin_HEXAGON_Y2_dcfetch(((data1+(alu0+384))+16)); + unsigned_char8 val6 = *((unsigned_char8*)((data1+(alu0+576)))); + __builtin_HEXAGON_Y2_dcfetch(((data1+(alu0+576))+16)); + + unsigned_char4 alu5 = __builtin_shufflevector(val3, val3, 0, 1, 2, 3); + unsigned_char4 alu6 = __builtin_shufflevector(val4, val4, 0, 1, 2, 3); + unsigned_char4 alu7 = __builtin_shufflevector(val5, val5, 0, 1, 2, 3); + unsigned_char4 alu8 = __builtin_shufflevector(val6, val6, 0, 1, 2, 3); + acc0 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc0, val1, (*((unsigned int*)&alu5))); + acc1 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc1, val1, (*((unsigned int*)&alu6))); + acc2 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc2, val1, (*((unsigned int*)&alu7))); + acc3 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc3, val1, (*((unsigned int*)&alu8))); + + unsigned_char4 alu9 = __builtin_shufflevector(val3, val3, 4, 5, 6, 7); + unsigned_char4 alu10 = __builtin_shufflevector(val4, val4, 4, 5, 6, 7); + unsigned_char4 alu11 = __builtin_shufflevector(val5, val5, 4, 5, 6, 7); + unsigned_char4 alu12 = __builtin_shufflevector(val6, val6, 4, 5, 6, 7); + acc0 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc0, val2, (*((unsigned int*)&alu9))); + acc1 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc1, val2, (*((unsigned int*)&alu10))); + acc2 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc2, val2, (*((unsigned int*)&alu11))); + acc3 = __builtin_HEXAGON_V6_vrmpybus_acc_128B(acc3, val2, (*((unsigned int*)&alu12))); + } + unsigned_char128 alu18 = __builtin_HEXAGON_V6_vpackhub_sat_128B(__builtin_HEXAGON_V6_vpackwh_sat_128B((((((acc3+val0)*203)+32767)/65536)+136), (((((acc2+val0)*203)+32767)/65536)+136)), __builtin_HEXAGON_V6_vpackwh_sat_128B((((((acc1+val0)*203)+32767)/65536)+136), (((((acc0+val0)*203)+32767)/65536)+136))); + *((unsigned_char128*)((data0+(ridx0<<7)))) = alu18; + } +} +""" + prg = replace(prg, src=new_src+prg.src.split("/* DSP boilerplate */ ")[1]) + rt = CompiledRunner(prg) + #Device.default.compiler.disassemble(rt.lib) + ei = ExecItem(rt, bufs_from_lin(k)) + tm = ei.run(wait=True) + print(f"final time {tm*1e6:.2f} us") + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/test_randomness.py b/tinygrad_repo/test/test_randomness.py new file mode 100644 index 000000000..435778efb --- /dev/null +++ b/tinygrad_repo/test/test_randomness.py @@ -0,0 +1,360 @@ +import unittest, math +from functools import partial + +import numpy as np +import torch +from tinygrad import nn, dtypes, Tensor, Device, TinyJit +from tinygrad.helpers import getenv, CI +from tinygrad.device import is_dtype_supported +from tinygrad.engine.realize import lower_schedule, CompiledRunner +from hypothesis import given, settings, strategies as strat +from test.helpers import not_support_multi_device + +settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) +settings.load_profile("my_profile") + +# https://gist.github.com/devries/11405101 +def ksprob(a): + fac, total, termbf = 2.0, 0.0, 0.0 + a2 = -2.0 * a * a + for j in range(1, 101): + term = fac * math.exp(a2 * j * j) + total += term + if math.fabs(term) <= 0.001 * termbf or math.fabs(term) <= 1e-8 * total: + return total + fac = -fac + termbf = math.fabs(term) + return 1.0 + +def kstest(l1, l2): + n1, n2 = len(l1), len(l2) + l1.sort() + l2.sort() + j1, j2, d, fn1, fn2 = 0, 0, 0.0, 0.0, 0.0 + while j1 < n1 and j2 < n2: + d1, d2 = l1[j1], l2[j2] + if d1 <= d2: + fn1 = (float(j1) + 1.0) / float(n1) + j1 += 1 + if d2 <= d1: + fn2 = (float(j2) + 1.0) / float(n2) + j2 += 1 + dtemp = math.fabs(fn2 - fn1) + if dtemp > d: + d = dtemp + ne = float(n1 * n2) / float(n1 + n2) + nesq = math.sqrt(ne) + prob = ksprob((nesq + 0.12 + 0.11 / nesq) * d) + return prob + +def equal_distribution(tiny_func, torch_func=None, numpy_func=None, shape=(40, 43), alpha=0.04): + Tensor.manual_seed(1337) + torch.manual_seed(1337) + np.random.seed(1337) + assert not (torch_func is None and numpy_func is None), "no function to compare with" + x1 = tiny_func(*shape).numpy().flatten() + x2 = tiny_func(shape).numpy().flatten() + if numpy_func is not None: y = numpy_func(shape).flatten() + if torch_func is not None: z = torch_func(shape).numpy().flatten() + return (numpy_func is None or (kstest(x1, y) >= alpha and kstest(x2, y) >= alpha)) and \ + (torch_func is None or (kstest(x1, z) >= alpha and kstest(x2, z) >= alpha)) + +def normal_test(func, shape=(20, 23), alpha=0.05): return equal_distribution(func, numpy_func=lambda x: np.random.randn(*x), shape=shape, alpha=alpha) + +class TestRandomness(unittest.TestCase): + def test_rand(self): + self.assertFalse(normal_test(Tensor.rand)) + self.assertTrue(equal_distribution(Tensor.rand, torch.rand, lambda x: np.random.rand(*x))) + + @unittest.skipUnless(is_dtype_supported(dtypes.float16) and is_dtype_supported(dtypes.ulong), "need float16 and ulong support") + def test_rand_float16(self): + N = 128 + x = Tensor.rand((2, N, N), dtype=dtypes.float16) + assert x.dtype == dtypes.float16 + nx = x.numpy() + # seed dependant, check output range is [0, 1) + assert nx[nx == 1].size == 0 + assert nx[nx == 0].size > 0 + equal_distribution(lambda *x: Tensor.rand(*x, dtype=dtypes.float16), torch.rand, lambda x: np.random.rand(*x), shape=(2, N, N)) + + @unittest.skipIf(CI and Device.DEFAULT in {"NV", "CUDA"}, "gpuocelot doesn't support certain ops needed for threefry") + def test_threefry_against_reference(self): + Tensor.manual_seed(1337) + + # reference generated using + """ + key0 = 1337 + key1 = 0 + values = jax.extend.random.threefry_2x32((np.uint32(key1), np.uint32(key0)), np.arange(20, dtype=np.uint32)) + print(f"[{', '.join(f'{v}' for v in values)}]") + """ + jr = np.array([2221762175, 1752107825, 653745012, 1967534793, 1395205442, 3840423848, 2159346757, + 603508235, 3319473678, 3363866483, 3544324138, 1436466838, 2169858556, 2570072943, + 2387150698, 3678370550, 2911697663, 403244401, 2560861638, 1692360114]) + + counts = Tensor.arange(20, dtype=dtypes.uint32) + counts0, counts1 = counts.chunk(2) + r = Tensor._threefry_random_bits(Tensor([0, 1337], dtype='uint32'), counts0, counts1).numpy() + + np.testing.assert_allclose(jr, r) + + @unittest.skipIf(getenv("PTX"), "fails with PTX") + def test_threefry_doesnt_use_long(self): + for (_,ei) in lower_schedule(Tensor.rand(20).schedule()): + if isinstance(ei.prg, CompiledRunner): + for u in ei.prg.p.uops: + self.assertNotIn(u.dtype, {dtypes.long, dtypes.ulong}, msg=f"long found in {ei.prg.p.name}") + + def test_threefry_against_reference_full(self): + Tensor.manual_seed(1337) + + # reference generated using + """ + key0 = 1337 + key1 = int.from_bytes(hashlib.sha256(int(0).to_bytes(4)).digest(), "big") & 0xffffffff + values = jax.extend.random.threefry_2x32((np.uint32(key1), np.uint32(key0)), np.arange(20, dtype=np.uint32)) + values = (values >> (32 - 23)) | np.array(1, dtype=np.float32).view(np.uint32) + values = values.view(np.float32) - 1 + print(f"[{', '.join(f'{v}' for v in values)}]") + """ + jr = np.array([0.9073467254638672, 0.8235964775085449, 0.6872662305831909, 0.9920015335083008, 0.4941047430038452, + 0.3108327388763428, 0.09639489650726318, 0.004686474800109863, 0.8435229063034058, 0.824237585067749, + 0.5873836278915405, 0.4232727289199829, 0.2530076503753662, 0.40300023555755615, 0.03966474533081055, + 0.27904558181762695, 0.9150195121765137, 0.48057758808135986, 0.23821306228637695, 0.7676635980606079], dtype=np.float32) + r = Tensor.rand(20).numpy() + np.testing.assert_allclose(r, jr, atol=1e-5, rtol=1e-5) + + # next 20, np.arange(20, 40, dtype=np.uint32) + jr = np.array([0.7444133758544922, 0.7713677883148193, 0.8233780860900879, 0.43871235847473145, 0.517757773399353, + 0.6437174081802368, 0.967403769493103, 0.26167726516723633, 0.6825339794158936, 0.14966607093811035, + 0.28920769691467285, 0.017063498497009277, 0.2627382278442383, 0.9525482654571533, 0.9351049661636353, + 0.43904995918273926, 0.043945908546447754, 0.6616791486740112, 0.6667773723602295, 0.5228077173233032], dtype=np.float32) + r = Tensor.rand(20).numpy() + np.testing.assert_allclose(r, jr, atol=1e-5, rtol=1e-5) + + # next 10, np.arange(40, 50, dtype=np.uint32) + jr = np.array([0.9614430665969849, 0.059279561042785645, 0.01909029483795166, 0.47882091999053955, 0.9677121639251709, + 0.36863112449645996, 0.3102607727050781, 0.06608951091766357, 0.35329878330230713, 0.26518797874450684], dtype=np.float32) + r = Tensor.rand(10).numpy() + np.testing.assert_allclose(r, jr, atol=1e-5, rtol=1e-5) + + @unittest.skipIf(not_support_multi_device(), "no multi") + def test_threefry_tensors_cnt(self): + Tensor.manual_seed(1337) + + Tensor.rand(20).realize() + + assert len(Tensor._device_rng_counters) == 1 + assert len(Tensor._device_seeds) == 1 + + Tensor.rand(20, device=f"{Device.DEFAULT}:1").realize() + + assert len(Tensor._device_rng_counters) == 2 + assert len(Tensor._device_seeds) == 2 + + Tensor.manual_seed(2) + + assert len(Tensor._device_rng_counters) == 0 + assert len(Tensor._device_seeds) == 0 + + @unittest.skipIf(not_support_multi_device(), "no multi") + def test_threefry_same_kernels(self): + Tensor.manual_seed(0) + + Tensor.rand(1).realize() + + s = Tensor.rand(20).schedule() + s2 = Tensor.rand(20).schedule() + + assert len(s) == len(s2), f"{len(s)} != {len(s2)}" + for x,y in zip(s, s2): + if not (x.ast == y.ast): + print(f"{x.ast} != {y.ast}") + + Tensor.rand(1, device=f"{Device.DEFAULT}:1").realize() + + s3 = Tensor.rand(20, device=f"{Device.DEFAULT}:1").schedule() + s4 = Tensor.rand(20, device=f"{Device.DEFAULT}:1").schedule() + + assert len(s3) == len(s4), f"{len(s3)} != {len(s4)}" + assert len(s2) == len(s4), f"{len(s)} != {len(s3)}" + for x,y in zip(s3, s4): + if not (x.ast == y.ast): + print(f"{x.ast} != {y.ast}") + + @unittest.skipUnless(is_dtype_supported(dtypes.bfloat16), "need bfloat16 support") + def test_rand_bfloat16(self): + N = 128 + x = Tensor.rand((2, N, N), dtype=dtypes.bfloat16) + assert x.dtype == dtypes.bfloat16 + nx = x.numpy() + assert nx[nx == 1].size == 0 + assert nx[nx == 0].size > 0 + equal_distribution(lambda *x: Tensor.rand(*x, dtype=dtypes.bfloat16).float(), torch.rand, lambda x: np.random.rand(*x), shape=(2, N, N)) + + def test_rand_like(self): + empty = Tensor.empty((80, 44)) + rand = Tensor.rand_like(empty) + assert rand.shape == empty.shape + assert rand.dtype == empty.dtype + assert rand.device == empty.device + + def test_randn_like(self): + empty = Tensor.empty((80, 44)) + rand = Tensor.randn_like(empty) + assert rand.shape == empty.shape + assert rand.dtype == empty.dtype + assert rand.device == empty.device + + def test_rand_like_zero_shape(self): + empty = Tensor.empty(0, 20) + rand = Tensor.rand_like(empty) + assert rand.shape == empty.shape + assert rand.dtype == empty.dtype + assert rand.device == empty.device + + def test_rand_like_more_dims(self): + empty = Tensor.empty((1, 2, 3, 4, 5, 6)) + rand = Tensor.rand_like(empty) + assert rand.shape == empty.shape + assert rand.dtype == empty.dtype + assert rand.device == empty.device + + def test_rand_like_dtype(self): + empty = Tensor.empty((80, 44), dtype=dtypes.float16) + rand = Tensor.rand_like(empty) + assert rand.shape == empty.shape + assert rand.dtype == empty.dtype + assert rand.device == empty.device + + empty = Tensor.empty((80, 44)) + rand = Tensor.rand_like(empty, dtype=dtypes.float16) + assert rand.shape == empty.shape + assert rand.dtype == dtypes.float16 + assert rand.device == empty.device + + def test_randn_like_dtype(self): + empty = Tensor.empty((80, 44), dtype=dtypes.float16) + rand = Tensor.randn_like(empty) + assert rand.shape == empty.shape + assert rand.dtype == empty.dtype + assert rand.device == empty.device + + empty = Tensor.empty((80, 44)) + rand = Tensor.randn_like(empty, dtype=dtypes.float16) + assert rand.shape == empty.shape + assert rand.dtype == dtypes.float16 + assert rand.device == empty.device + + def test_randn(self): + self.assertEqual(Tensor.randn(3,3,dtype=dtypes.half).dtype, dtypes.half) + self.assertTrue(normal_test(Tensor.randn)) + self.assertTrue(equal_distribution(Tensor.randn, torch.randn, lambda x: np.random.randn(*x))) + + @given(strat.sampled_from([dtypes.float, dtypes.float16, dtypes.bfloat16])) + @unittest.skipIf(Device.DEFAULT in ["HSA", "AMD"], "bfloat16 local buffer broken in HSA") + def test_randn_finite(self, default_float): + if not is_dtype_supported(default_float): return + old_default_float = dtypes.default_float + # low precision can result in inf from randn + dtypes.default_float = default_float + t = Tensor.randn(256, 256) + mx = t.max().numpy().item() + mn = t.min().numpy().item() + print(f"testing with {default_float=}") + assert math.isfinite(mx), mx + assert math.isfinite(mn), mn + dtypes.default_float = old_default_float + + def test_randint(self): + self.assertFalse(normal_test(Tensor.randint)) + self.assertTrue(equal_distribution(partial(Tensor.randint, low=-2, high=5), + numpy_func=lambda x: np.random.randint(low=-2, high=5, size=x))) + self.assertTrue(equal_distribution(partial(Tensor.randint, low=-2, high=5, dtype="int32"), + numpy_func=lambda x: np.random.randint(low=-2, high=5, size=x))) + self.assertTrue(Tensor.randint(1, device="CPU").device=="CPU") + # check types of args + with self.assertRaises(TypeError): Tensor.randint((3, 4), low=0.1, high=3) + with self.assertRaises(TypeError): Tensor.randint((3, 4), low=0, high=3.5) + with self.assertRaises(TypeError): Tensor.randint((3, 4), low=1, high=3, dtype="float") + with self.assertRaises(TypeError): Tensor.randint((3, 4), low=0, high=3, dtype=dtypes.float32) + + def test_normal(self): + self.assertTrue(normal_test(Tensor.normal)) + self.assertTrue(equal_distribution(Tensor.normal, lambda x: torch.nn.init.normal_(torch.empty(x), mean=0, std=1), + lambda x: np.random.normal(loc=0, scale=1, size=x))) + + def test_uniform(self): + self.assertFalse(normal_test(Tensor.uniform)) + self.assertTrue(equal_distribution(Tensor.uniform, lambda x: torch.nn.init.uniform_(torch.empty(x)), lambda x: np.random.uniform(size=x))) + self.assertTrue(equal_distribution(partial(Tensor.uniform, low=-100, high=100, dtype=dtypes.int32), + numpy_func=lambda x: np.random.randint(low=-100, high=100, size=x))) + + def test_scaled_uniform(self): + self.assertFalse(normal_test(Tensor.scaled_uniform)) + self.assertTrue(equal_distribution(Tensor.scaled_uniform, lambda x: torch.nn.init.uniform_(torch.empty(x), a=-1, b=1) / math.sqrt(math.prod(x)), + lambda x: np.random.uniform(-1, 1, size=x) / math.sqrt(math.prod(x)))) + + def test_glorot_uniform(self): + self.assertFalse(normal_test(Tensor.glorot_uniform)) + self.assertTrue(equal_distribution(Tensor.glorot_uniform, lambda x: torch.nn.init.xavier_uniform_(torch.empty(x)), + lambda x: np.random.uniform(-1, 1, size=x) * math.sqrt(6 / (x[0] + math.prod(x[1:]))))) + + def test_kaiming_uniform(self): + for shape in [(32, 128, 3, 3), (80, 44), (3, 55, 35)]: + self.assertTrue(equal_distribution(Tensor.kaiming_uniform, lambda x: torch.nn.init.kaiming_uniform_(torch.empty(x)), shape=shape)) + + def test_kaiming_normal(self): + for shape in [(32, 128, 3, 3), (80, 44), (3, 55, 35)]: + self.assertTrue(equal_distribution(Tensor.kaiming_normal, lambda x: torch.nn.init.kaiming_normal_(torch.empty(x)), shape=shape)) + + def test_multinomial(self): + self.assertRaises(AssertionError, lambda: Tensor(2).multinomial(1, replacement=False)) + self.assertRaises(AssertionError, lambda: Tensor([1, 9]).multinomial(0, replacement=False)) + def _check_with_torch(w, num_samples, replacement): + tiny_res = Tensor(w).multinomial(num_samples, replacement=replacement) + torch_res = torch.tensor(w).multinomial(num_samples, replacement=replacement) + self.assertEqual(tiny_res.shape, torch_res.shape) + if torch_res.ndim == 1: + tiny_res = tiny_res.unsqueeze(0) + torch_res = torch_res.unsqueeze(0) + for i in range(torch_res.shape[0]): + self.assertTrue(equal_distribution(lambda *_: tiny_res[i], lambda _: torch_res[i])) + _check_with_torch(w=[0.231, 0., 1., 0.5], num_samples=2000, replacement=True) + _check_with_torch(w=[[0.2, 0.8]], num_samples=2000, replacement=True) # 2D but only 1 row + _check_with_torch(w=[[0.453, 0., 1., 0.81], [0.1, 0.8, 0., 0.1]], num_samples=2000, replacement=True) + # no-replacement isn't supported, unless taking only one sample + w = [0.1, 0.9] + self.assertRaises(AssertionError, lambda: Tensor(w).multinomial(100, replacement=False)) + + @TinyJit + def sample_one(): return Tensor(w).multinomial(1, replacement=False).realize() + + tiny_samples = [sample_one().item() for _ in range(1000)] + torch_samples = [torch.tensor(w).multinomial(1, replacement=False).item() for _ in range(1000)] + self.assertTrue(equal_distribution(lambda *_: Tensor(tiny_samples), lambda _: torch.tensor(torch_samples))) + + def test_multinomial_counterexample(self): + tiny_res = Tensor([0.3, 0.6, 0.1]).multinomial(4000, replacement=True) + torch_res = torch.tensor([0.3, 0.6, 0.1]).multinomial(4000, replacement=True) + self.assertTrue(equal_distribution(lambda *_: tiny_res, lambda _: torch_res)) + torch_res = torch.tensor([0.2, 0.7, 0.1]).multinomial(4000, replacement=True) + self.assertFalse(equal_distribution(lambda *_: tiny_res, lambda _: torch_res)) + + def test_conv2d_init(self): + params = (128, 256, (3,3)) + assert equal_distribution(lambda *_: nn.Conv2d(*params).weight, lambda _: torch.nn.Conv2d(*params).weight.detach()) + assert equal_distribution(lambda *_: nn.Conv2d(*params).bias, lambda _: torch.nn.Conv2d(*params).bias.detach()) + + def test_linear_init(self): + params = (64, 256) + assert equal_distribution(lambda *_: nn.Linear(*params).weight, lambda _: torch.nn.Linear(*params).weight.detach()) + assert equal_distribution(lambda *_: nn.Linear(*params).bias, lambda _: torch.nn.Linear(*params).bias.detach()) + + def test_bn_init(self): + params = (64,) + assert equal_distribution(lambda *_: nn.BatchNorm2d(*params).weight, lambda _: torch.nn.BatchNorm2d(*params).weight.detach()) + assert equal_distribution(lambda *_: nn.BatchNorm2d(*params).bias, lambda _: torch.nn.BatchNorm2d(*params).bias.detach()) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/test_remote.py b/tinygrad_repo/test/test_remote.py new file mode 100644 index 000000000..a4e5ed530 --- /dev/null +++ b/tinygrad_repo/test/test_remote.py @@ -0,0 +1,65 @@ +import numpy as np, unittest, string +from hypothesis import given, strategies as st +from tinygrad import Device, Tensor, TinyJit +from tinygrad.runtime.ops_remote import RemoteDevice, parse_hosts +from tinygrad.helpers import LazySeq, all_same + +def multihost_env(devices): + def same_hosts(devices): return all_same([h for h,_ in devices]) + return isinstance(devices, list) and len(devices) >= 12 and not same_hosts(devices[0:12]) and same_hosts(devices[0:6]) and same_hosts(devices[6:12]) + +@unittest.skipUnless(Device.DEFAULT == "REMOTE" and multihost_env(RemoteDevice.devices), "Requires special environment") +class TestRemoteMultiHost(unittest.TestCase): + def test_mutlihost_transfer(self): + a = Tensor.arange(0, 16, device='REMOTE:0').contiguous().realize() + b = a.to('REMOTE:6').contiguous().realize() + np.testing.assert_equal(b.numpy(), np.arange(0, 16)) + + # NOTE: remote graph currently throws GraphException on host mismatch, this just checks that it is being handled, not that jit graph is being used + def test_multihost_matmul_jit(self): + @TinyJit + def do(a:Tensor, b:Tensor): return (a @ b).contiguous().realize() + ds = ('REMOTE:0', 'REMOTE:1', 'REMOTE:6', 'REMOTE:7') + for _ in range(3): + na, nb = np.random.rand(128, 128).astype(np.float32), np.random.rand(128, 128).astype(np.float32) + a, b = Tensor(na).shard(ds, 0).contiguous().realize(), Tensor(nb).shard(ds, 0).contiguous().realize() + nc = na @ nb + c = do(a, b) + np.testing.assert_allclose(nc, c.numpy(), rtol=3e-2, atol=1e-4) # tolerances from extra/gemm/simple_matmul.py + +class TestParseHosts(unittest.TestCase): + def assert_seq(self, result:LazySeq, host:str): + self.assertIsInstance(result, LazySeq) + for i in [0, 1, 5, 10]: self.assertEqual(result[i], (host, i)) + + @given(st.sampled_from(["", "localhost", "192.168.1.1:8080", "host"])) + def test_single_host_no_count(self, host:str): + self.assert_seq(parse_hosts(host), host) + + @given(host=st.sampled_from(["localhost", "host", "192.168.1.1:8080"]), count=st.integers(0, 10)) + def test_single_host_with_count(self, host:str, count:int): + self.assertEqual(parse_hosts(f"{host}*{count}"), [(host, i) for i in range(count)]) + + def test_multiple_hosts_with_counts_simple(self): + self.assertEqual(parse_hosts("host1*2,host2*3"), [("host1", i) for i in range(2)] + [("host2", i) for i in range(3)]) + + @given(st.lists(st.tuples(st.text(alphabet=string.ascii_letters + string.digits + ".-:"), st.integers(1, 16)), min_size=1)) + def test_multiple_hosts_with_counts_sampled(self, host_count_pairs): + hosts_str = ",".join(f"{host}*{count}" for host, count in host_count_pairs) + expected = [(host, i) for host, count in host_count_pairs for i in range(count)] + self.assertEqual(parse_hosts(hosts_str), expected) + + @given(st.sampled_from(["host1*2,host2", "a*1,b", "x*3,y*2,z"])) + def test_mixed_hosts_fails(self, hosts): + with self.assertRaises(AssertionError): parse_hosts(hosts) + + @given(st.sampled_from(["host*abc", "test*xyz", "a*1.5"])) + def test_invalid_count_fails(self, hosts): + with self.assertRaises(ValueError): parse_hosts(hosts) + + @given(st.sampled_from(["host*2*3", "a*1*2*3", "test*x*y"])) + def test_multiple_asterisks_fails(self, hosts): + with self.assertRaises(ValueError): parse_hosts(hosts) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_renderer_failures.py b/tinygrad_repo/test/test_renderer_failures.py new file mode 100644 index 000000000..3dd795ead --- /dev/null +++ b/tinygrad_repo/test/test_renderer_failures.py @@ -0,0 +1,121 @@ +import unittest +from typing import List, cast +import numpy as np +from tinygrad.device import Buffer, Device, is_dtype_supported +from tinygrad.dtype import dtypes, ConstType +from tinygrad.engine.realize import CompiledRunner +from tinygrad.helpers import dedup, flatten, prod +from tinygrad.renderer.cstyle import CStyleLanguage +from tinygrad.renderer.ptx import PTXRenderer +from tinygrad.renderer.wgsl import WGSLRenderer +from tinygrad.runtime.ops_python import PythonRenderer +from tinygrad.uop.ops import UOp, Ops, python_alu +from tinygrad.renderer import ProgramSpec +from tinygrad.tensor import Tensor, _to_np_dtype +from tinygrad.codegen import full_rewrite +from tinygrad.engine.realize import lower_schedule_item + +def _test_uop_result(inputs:List[Tensor], stores:List[UOp], local_size=None): + for x in inputs: x.realize() + # NOTE: we only toposort the stores + uops: List[UOp] = [] + def _recursive_add(uop:UOp) -> List[UOp]: return flatten([_recursive_add(x) for x in uop.src])+[uop] + uops = dedup(flatten(_recursive_add(st) for st in stores)) + outbufs = [Buffer(Device.DEFAULT, sz:=(1 if local_size is None else prod(local_size)), (dtype:=u.src[1].dtype), \ + initial_value=np.zeros(sz, dtype=_to_np_dtype(dtype)).data) for u in uops if u.op is Ops.STORE] + inbufs = [cast(UOp,x.uop).base.buffer for x in inputs] + src = Device[Device.DEFAULT].renderer.render(uops) + ei = CompiledRunner(ProgramSpec("test", src, Device.DEFAULT, uops[-1], uops=uops, local_size=local_size)) + ei.exec(outbufs+inbufs) + return [np.frombuffer(x.as_buffer(), _to_np_dtype(x.dtype)) for x in outbufs] + +def _setup_and_test_alu(alu_op:Ops, input_val:ConstType, *alu_src_uops:UOp): + dtype = alu_src_uops[0].dtype + a = UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), (), 0) + b = UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), (), 1) + idx = UOp.const(dtypes.int, 0) + ld = UOp(Ops.LOAD, dtype, (b.index(idx),)) + alu = ld.alu(alu_op, *alu_src_uops) + store = UOp.store(a.index(idx), alu) + sink = UOp(Ops.SINK, dtypes.void, (store,)) + uops = full_rewrite(sink, Device[Device.DEFAULT].renderer) + return _test_uop_result([Tensor([input_val])], uops)[0] + +class TestRendererFailures(unittest.TestCase): + @unittest.skipIf(not isinstance(Device[Device.DEFAULT].renderer, (PTXRenderer, PythonRenderer)), "test is for ptx or python renderer") + def test_gated_store_with_alu(self): + a = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) + gate_alu = (lidx0:=UOp(Ops.SPECIAL, dtypes.int, (), ('lidx0', 4))).ne(0) + gated_alu_store = UOp(Ops.STORE, dtypes.void, (a.index(lidx0, gate_alu), UOp.const(dtypes.int, 1))) + sink = UOp(Ops.SINK, dtypes.void, (gated_alu_store,)) + uops = full_rewrite(sink, Device[Device.DEFAULT].renderer) + ret = _test_uop_result([], uops, local_size=[4, 1, 1])[0] + np.testing.assert_equal(ret, [0, 1, 1, 1]) + + @unittest.skipIf(not isinstance(Device[Device.DEFAULT].renderer, (PTXRenderer, PythonRenderer)), "test is for ptx or python renderer") + def test_gated_store_with_alu_2d(self): + a = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) + gate_alu_0 = (lidx0:=UOp(Ops.SPECIAL, dtypes.int, (), ('lidx0', 4))).ne(0) + gate_alu_1 = (lidx1:=UOp(Ops.SPECIAL, dtypes.int, (), ('lidx1', 2))).ne(0) + gated_alu_store = UOp(Ops.STORE, dtypes.void, (a.index(lidx0+lidx1*4, gate_alu_0&gate_alu_1), UOp.const(dtypes.int, 1))) + sink = UOp(Ops.SINK, dtypes.void, (gated_alu_store,)) + uops = full_rewrite(sink, Device[Device.DEFAULT].renderer) + ret = _test_uop_result([], uops, local_size=[4, 2, 1])[0] + np.testing.assert_equal(ret, [0, 0, 0, 0, 0, 1, 1, 1]) + +@unittest.skipIf(not isinstance(Device[Device.DEFAULT].renderer, CStyleLanguage), "uops are for cstyle") +class TestCStyleFailures(unittest.TestCase): + def test_inline_const_alu(self): + # CPU doesn't use the max function + ret = _setup_and_test_alu(Ops.MAX, 1, UOp.const(dtypes.int, dtypes.min(dtypes.int)+1)) + self.assertEqual(ret[0], 1) + + def _test_src_strip_paren(self, op: Ops, should_strip_paren:bool=True): + dtype = "bool" if op in (Ops.OR, Ops.XOR, Ops.AND) else None + ret = Tensor.empty(1, dtype=dtype) + for _ in range(5): ret = python_alu[op](ret, Tensor.empty(1, dtype=dtype)) + schedule = ret.schedule() + assert len(schedule) == 1 + ei = lower_schedule_item(schedule[0]) + src = ei.prg.p.src + self.assertEqual("("*5 not in src, should_strip_paren) + + def test_repeat_add(self): self._test_src_strip_paren(Ops.ADD) + def test_repeat_mul(self): self._test_src_strip_paren(Ops.MUL) + def test_repeat_xor(self): self._test_src_strip_paren(Ops.XOR) + def test_repeat_or(self): self._test_src_strip_paren(Ops.OR) + def test_repeat_and(self): self._test_src_strip_paren(Ops.AND) + def test_repeat_sub(self): self._test_src_strip_paren(Ops.SUB, should_strip_paren=False) + +@unittest.skipUnless(isinstance(Device[Device.DEFAULT].renderer, WGSLRenderer), "tests for wgsl renderer") +class TestWGSLFailures(unittest.TestCase): + def test_multiply_infinity(self): + # multiplying a positive constant by infinity should return infinity + # WGSL pipelines do not handle this reliably, some of which return zero, unless infinity always comes from a read on a dynamic buffer + ret = _setup_and_test_alu(Ops.MUL, 5.0, UOp.const(dtypes.float32, float("inf"))) + self.assertEqual(ret[0], float("inf")) + +@unittest.skipIf(not isinstance(Device[Device.DEFAULT].renderer, PTXRenderer), "tests for ptx renderer") +class TestPTXFailures(unittest.TestCase): + @unittest.skip("INDEX can only have a gate ALU parent, not an IF") + def test_gated_store_with_if(self): + a = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) + gate_alu = (lidx0:=UOp(Ops.SPECIAL, dtypes.int, (), ('lidx0', 4))).ne(0) + val = UOp.const(dtypes.int, 1) + if_uop = UOp(Ops.IF, dtypes.void, (gate_alu,)) + gated_alu_store = UOp(Ops.STORE, dtypes.void, (a.index(lidx0, if_uop), val)) + sink = UOp(Ops.SINK, dtypes.void, (gated_alu_store,)) + uops = full_rewrite(sink, Device[Device.DEFAULT].renderer) + ret = _test_uop_result([], uops, local_size=[4, 1, 1])[0] + np.testing.assert_equal(ret, [0, 1, 1, 1]) + + @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") + def test_gated_define_acc_with_half_dtype(self): + a = Tensor.randn(32, 32, dtype=dtypes.half).realize() + b = Tensor.randn(34, 32, dtype=dtypes.half).realize() + result = a.pad((1,1)).matmul(b, dtype=dtypes.half).numpy() + reference = a.pad((1,1)).matmul(b, dtype=dtypes.float).numpy() + np.testing.assert_allclose(result, reference, atol=1e-2, rtol=1e-2) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_sample.py b/tinygrad_repo/test/test_sample.py new file mode 100644 index 000000000..ae7132792 --- /dev/null +++ b/tinygrad_repo/test/test_sample.py @@ -0,0 +1,21 @@ +import unittest +import numpy as np +from tinygrad import Tensor, Variable, Device +from tinygrad.helpers import OSX + +@unittest.skipIf(Device.DEFAULT == "WEBGPU" and not OSX, "WEBGPU Vulkan can only run kernels with up to 10 buffers") +class TestSample(unittest.TestCase): + def test_sample(self): + X = Tensor.rand(10000, 50).realize() + BS = 16 + idxs = np.random.randint(0, X.shape[0], size=(BS)) + # this uncovered a bug with arg sort order + batch = [Variable(f'idx{i}', 0, X.shape[0]-1).bind(s) for i,s in enumerate(idxs.tolist())] + x = Tensor.cat(*[X.shrink(((batch[i], batch[i]+1), None)) for i in range(BS)]) + print(idxs) + ret = x.numpy() + base = X.numpy()[idxs] + np.testing.assert_equal(ret, base) + +if __name__ == '__main__': + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/test_schedule.py b/tinygrad_repo/test/test_schedule.py new file mode 100644 index 000000000..ae04c4690 --- /dev/null +++ b/tinygrad_repo/test/test_schedule.py @@ -0,0 +1,2669 @@ +# this will be the new test_ops for the next level +# schedule confirms the right things are capable of fusing +# NOTE: this has overlap with external_test_opt.py + +import unittest +import numpy as np +import functools +from typing import List, Optional, Union, cast +from hypothesis import assume, given, strategies as strat + +from tinygrad import nn, dtypes, Device, Tensor +from tinygrad.device import is_dtype_supported +from tinygrad.dtype import DType, ImageDType +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.uop.ops import PatternMatcher, UOp, Ops, GroupOp, UPat, graph_rewrite, track_rewrites +from tinygrad.uop.symbolic import symbolic_simple +from tinygrad.helpers import CI, DEBUG, FUSE_ARANGE, SPLIT_REDUCEOP, GlobalCounters, Context, getenv, all_same, temp +from tinygrad.kernelize.kernelize import merge_views, get_kernelize_map, Kernel +from tinygrad.engine.schedule import ScheduleItem, create_schedule_with_vars +from tinygrad.engine.realize import CompiledRunner, run_schedule, lower_schedule + +class KernelCountException(Exception): pass +def check_schedule(t:Union[Tensor, List[Tensor], UOp], allowed:int, to_prerealize:Optional[List[Tensor]]=None, filter_sink=True): + if to_prerealize: + with Context(DEBUG=0, TRACK_MATCH_STATS=0): Tensor.realize(*to_prerealize) + if isinstance(t, Tensor): sched = t.schedule() + elif isinstance(t, List) and isinstance(t[0], Tensor): sched = Tensor.schedule(*t) + else: + assert isinstance(t, UOp), f"can't schedule {t}" + sink = UOp.sink(t) if t.op is not Ops.SINK else t + becomes_map = get_kernelize_map(sink) + sched, _ = create_schedule_with_vars(sink.substitute(becomes_map)) + # test lowering all the ScheduleItems to ExecItems + kernel_cnt = len([si for si,ei in lower_schedule(sched.copy()) if isinstance(ei.prg, CompiledRunner) or not filter_sink]) + if kernel_cnt != allowed: + print(f"SCHEDULE ISSUE, expecting {allowed} got {len(sched)}") + if DEBUG >= 3: + for i,s in enumerate(sched): + print("kernel", i+1) + print(s.ast) + raise KernelCountException(f"{kernel_cnt} != {allowed}") + return sched + +def _realize_weights(m): + for p in nn.state.get_parameters(m): p.realize() + +def _test_conv2d(allowed:int, dtype:DType=dtypes.float, **kwargs): + old_default_float, dtypes.default_float = dtypes.default_float, dtype + dtypes.default_float = dtype + Tensor.manual_seed(0) + BS, CIN = 2, 3 + img = Tensor.randn(BS, CIN, 64, 64, requires_grad=True).realize() + w = Tensor.uniform(16, CIN, 3, 3, requires_grad=True).realize() + ret = Tensor.conv2d(img, w).relu().mean().backward() + dtypes.default_float = old_default_float + with Context(**kwargs): s = Tensor.schedule(ret, img.grad, w.grad) + run_schedule(s.copy()) + cnt = len([si for si in s if si.ast.op is Ops.SINK]) + assert cnt == allowed, f"expected {allowed} kernels, got {cnt}" + if getenv("CHECK", 1): + import torch + ref_img = torch.tensor(img.numpy(), requires_grad=True) + ref_w = torch.tensor(w.numpy(), requires_grad=True) + torch.nn.functional.conv2d(ref_img, ref_w).relu().mean().backward() + assert ref_img.grad is not None and ref_w.grad is not None and img.grad is not None and w.grad is not None + np.testing.assert_allclose(img.grad.numpy(), ref_img.grad.detach().numpy(), atol=1e-6 if dtype == dtypes.float else 1e-2) + np.testing.assert_allclose(w.grad.numpy(), ref_w.grad.detach().numpy(), atol=1e-6 if dtype == dtypes.float else 1e-2) + +@track_rewrites(name=True) +def schedule_graph_rewrite(big_sink:UOp): return get_kernelize_map(big_sink)[big_sink] + +class TestSchedule(unittest.TestCase): + def test_arange_avgpool2d(self, kcount=2): + x = Tensor.arange(25).reshape(1,1,5,5).cast(dtypes.float32) + t = x.avg_pool2d(padding=1) + sched = t.schedule() + self.assertEqual(len(sched), kcount) + run_schedule(sched) + import torch + torch_out = torch.nn.functional.avg_pool2d(torch.arange(25).reshape(1,1,5,5).float(), kernel_size=(2,2), padding=1).numpy() + np.testing.assert_allclose(t.numpy(), torch_out) + + def test_arange_avgpool2d_fused_noopt(self): + with Context(FUSE_ARANGE=1, NOOPT=1): self.test_arange_avgpool2d(kcount=1) + + # linearizer error + @unittest.skip("recursion error no longer raised") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.supports_float4, "needs supports_float4 to fail") + def test_arange_avgpool2d_fused(self): + with self.assertRaises(RecursionError): + with Context(FUSE_ARANGE=1, NOOPT=0): self.test_arange_avgpool2d(kcount=1) + + # when we're fusing a reduce, all ReduceOps must have the same N in the dimensions + # all permutes, reshapes, expands and shrinks push through the reduce + def test_arange_sum(self): + a = Tensor.arange(6).reshape(3, 2).sum(axis=1) + with Context(FUSE_ARANGE=1): + run_schedule(check_schedule(a, 1)) + self.assertListEqual(a.tolist(), [1, 5, 9]) + + def test_arange_sum_alt(self): + a = (Tensor.arange(5).reshape(1,5).expand(6,5)*Tensor(2)).reshape(1,6,5).sum(axis=2) + with Context(FUSE_ARANGE=1): + run_schedule(check_schedule(a, 1)) + np.testing.assert_equal(a.numpy(), 20) + + def test_permute_arange(self): + a = Tensor.arange(6).reshape(6, 1, 1).permute(2, 0, 1).sum(axis=1) + with Context(FUSE_ARANGE=1): + run_schedule(check_schedule(a, 1)) + self.assertListEqual(a.tolist(), [[15]]) + + @unittest.skipIf(Device.DEFAULT == "CPU", "devices must mismatch") + def test_error_on_device_mismatch(self): + a = Tensor.empty(10) + b = Tensor.empty(10, device="CPU") + c = a+b + with self.assertRaisesRegex(RuntimeError, "all buffers must be on the same device"): check_schedule(c, 1) + + @unittest.skipIf(Device.DEFAULT == "CPU", "devices must mismatch") + def test_error_on_device_mismatch_alt(self): + a = Tensor.empty(10) + b = Tensor.empty((1,), device="CPU").expand(10).contiguous() + c = a+b + with self.assertRaisesRegex(RuntimeError, "all buffers must be on the same device"): check_schedule(c, 1) + + @unittest.skipUnless(is_dtype_supported(dtypes.half) and getenv("CAST_AFTER_EXPAND"), "need half and CAST_AFTER_EXPAND=1") + @unittest.skip("CAST_AFTER_EXPAND is not supported") + def test_expand_buffer_before_cast(self): + a = Tensor.randn(4, 2, 1).realize().permute((1, 0, 2)) + b = a.cast(dtypes.half).expand((2, 4, 4))+2 + run_schedule(check_schedule(b, 1)) + np.testing.assert_allclose(b.numpy(), np.broadcast_to(a.numpy().astype(np.float16), (2, 4, 4))+2) + + def test_indexing_scalars_simple(self): + X = Tensor.randn(2, 2).realize() + xt = X[Tensor(1)][Tensor(0)] + with Context(FUSE_ARANGE=1): + run_schedule(check_schedule(xt, 2)) + np.testing.assert_equal(xt.numpy(), X.numpy()[1][0]) + + @unittest.skipIf(CI and Device.DEFAULT == "NV", "crashes on NV CI") + def test_add_chain_buffers(self): + N = 31 + with Context(TRACK_MATCH_STATS=0, DEBUG=0): + bufs = [Tensor(i).reshape((1,)).contiguous().realize() for i in range(N)] + for X in range(1,N): + root = bufs[0] + for i in range(1,N,X): + root = root + functools.reduce(lambda a,b:a+b, bufs[i:i+X]) + self.assertEqual(root.item(), sum(range(N))) + + @given(strat.sampled_from(range(2,4)), strat.sampled_from(range(2,4)), strat.sampled_from(range(0,4)), strat.sampled_from(range(0,4))) + def test_indexing_scalars(self, x, y, a, b): + assume(a1 children but should still fuse + # run_schedule(check_schedule(out, 1)) + run_schedule(check_schedule(out, 3)) + np.testing.assert_allclose(out.numpy(), \ + (c.numpy()*a.numpy().sum(axis=-1,keepdims=True)).sum(-1) + (b.numpy()*a.numpy().sum(axis=-1,keepdims=True)).sum(-1), atol=1e-4, rtol=1e-4) + + def test_reduce_expand_reduce_fusion(self): + Tensor.manual_seed(0) + a = Tensor.randn(4, 32).realize() + out = (a+a.sum(-1, keepdim=True)).sum(-1) + # run_schedule(check_schedule(out, 1)) + run_schedule(check_schedule(out, 2)) + np.testing.assert_allclose(out.numpy(), (a.numpy()+a.numpy().sum(axis=-1,keepdims=True)).sum(axis=-1), atol=1e-4, rtol=1e-4) + + def test_reduce_expand_reduce_expand_fusion(self): + Tensor.manual_seed(0) + a = Tensor.randn(4, 32).realize() + out = a+(a+a.sum(-1,keepdim=True)).sum(-1, keepdim=True) + # run_schedule(check_schedule(out, 2)) + run_schedule(check_schedule(out, 3)) + np.testing.assert_allclose(out.numpy(), \ + a.numpy()+(a.numpy()+a.numpy().sum(axis=-1,keepdims=True)).sum(axis=-1,keepdims=True), atol=1e-4, rtol=1e-4) + + def test_branching_reduces_and_expands_fusion(self): + Tensor.manual_seed(0) + a = Tensor.randn(4, 32).realize() + out0 = a+a.sum(-1, keepdim=True) + out1 = out0.sum(-1) + # run_schedule(check_schedule(out, 2)) + run_schedule(check_schedule([out0, out1], 3)) + np.testing.assert_allclose(out0.numpy(), a.numpy()+a.numpy().sum(axis=-1,keepdims=True), atol=1e-4, rtol=1e-4) + np.testing.assert_allclose(out1.numpy(), (a.numpy()+a.numpy().sum(axis=-1,keepdims=True)).sum(axis=-1), atol=1e-4, rtol=1e-4) + + def test_multireduce_fusion_simple_sequential(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 32).realize() + y = Tensor.randn(4, 32).realize() + out = (y + x.sum(axis=-1, keepdim=True)).sum(axis=-1) + # run_schedule(check_schedule(out, 1)) + run_schedule(check_schedule(out, 2)) + np.testing.assert_allclose(out.numpy(), (y.numpy() + x.numpy().sum(axis=-1, keepdims=True)).sum(axis=-1), atol=1e-4, rtol=1e-4) + + def test_multireduce_fusion_simple_parallel(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 32).realize() + y = Tensor.randn(4, 32).realize() + out = y.sum(axis=-1) + x.sum(axis=-1) + # run_schedule(check_schedule(out, 1)) + run_schedule(check_schedule(out, 2)) + np.testing.assert_allclose(out.numpy(), y.numpy().sum(axis=-1) + x.numpy().sum(axis=-1), atol=1e-4, rtol=1e-4) + + def test_multireduce_fusion_sequential(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 32).realize() + out = x.std(-1) + # run_schedule(check_schedule(out, 1)) + run_schedule(check_schedule(out, 2)) + np.testing.assert_allclose(out.numpy(), x.numpy().std(axis=-1, ddof=1), atol=1e-4, rtol=1e-4) + + def test_multireduce_fusion_parallel(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 32).realize() + y = Tensor.randn(4, 32).realize() + out = x.std(-1) + y.std(-1) + # run_schedule(check_schedule(out, 1)) + run_schedule(check_schedule(out, 4)) + np.testing.assert_allclose(out.numpy(), x.numpy().std(axis=-1, ddof=1) + y.numpy().std(axis=-1, ddof=1), atol=1e-4, rtol=1e-4) + + def test_multireduce_diffops_sequential(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 32).realize() + out = (x - x.max(-1, keepdim=True)).sum(-1) + # run_schedule(check_schedule(out, 1)) + run_schedule(check_schedule(out, 2)) + np.testing.assert_allclose(out.numpy(), (x.numpy() - x.numpy().max(axis=-1, keepdims=True)).sum(axis=-1), atol=1e-4, rtol=1e-4) + + def test_multireduce_fusion_diffops_parallel(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 32).realize() + y = Tensor.randn(4, 32).realize() + out = x.sum(-1) + y.max(-1) + # run_schedule(check_schedule(out, 1)) + run_schedule(check_schedule(out, 2)) + np.testing.assert_allclose(out.numpy(), x.numpy().sum(axis=-1) + y.numpy().max(axis=-1), atol=1e-4, rtol=1e-4) + + def test_multireduce_fusion_sequential_and_parallel(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 32).realize() + y = Tensor.randn(4, 32).realize() + mu = (x - x.max(axis=-1, keepdim=True)).mean(axis=-1, keepdim=True) + (y - y.max(axis=-1, keepdim=True)).mean(axis=-1, keepdim=True) + out = [((x - mu).square().sum(-1)/x.shape[-1]).sqrt(), ((y - mu).square().sum(-1)/y.shape[-1]).sqrt()] + np_mu = (x.numpy() - x.numpy().max(axis=-1, keepdims=True)).mean(axis=-1, keepdims=True) + \ + (y.numpy() - y.numpy().max(axis=-1, keepdims=True)).mean(axis=-1, keepdims=True) + # run_schedule(check_schedule(out, 1)) + run_schedule(check_schedule(out, 6)) + np.testing.assert_allclose(out[0].numpy(), np.sqrt(np.square(x.numpy() - np_mu).sum(-1)/x.shape[-1]), atol=1e-4, rtol=1e-4) + np.testing.assert_allclose(out[1].numpy(), np.sqrt(np.square(y.numpy() - np_mu).sum(-1)/y.shape[-1]), atol=1e-4, rtol=1e-4) + + def test_multimatmul_fusion(self): + Tensor.manual_seed(0) + a,b = Tensor.randn(4, 64).realize(), Tensor.rand(64,8).realize() + c,d = Tensor.randn(4, 64).realize(), Tensor.rand(64,8).realize() + out = a@b + c@d + # run_schedule(check_schedule(out, 1)) + run_schedule(check_schedule(out, 2)) + np.testing.assert_allclose(out.numpy(), a.numpy()@b.numpy() + c.numpy()@d.numpy(), atol=1e-4, rtol=1e-4) + + def test_softmax_fusion(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 12, 64, 64).realize() + out = x.softmax() + run_schedule(check_schedule(out, 3)) + expected = (x_exp:=np.exp(x.numpy()-x.numpy().max(-1, keepdims=True)))/x_exp.sum(-1, keepdims=True) + np.testing.assert_allclose(out.numpy(), expected, atol=1e-4, rtol=1e-4) + + @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") + def test_softmax_upcast(self): + # input half, softmax in float + Tensor.manual_seed(0) + x = Tensor.randn(4, 12, 64, 64, dtype=dtypes.half).realize() + out = x.softmax(dtype=dtypes.float) + sched = out.schedule() + self.assertEqual(len(sched), 3) + self.assertEqual(sched[0].bufs[0].dtype, dtypes.half) + + # input float, softmax in float + Tensor.manual_seed(0) + x = Tensor.randn(4, 12, 64, 64, dtype=dtypes.float).realize() + out = x.softmax(dtype=dtypes.float) + sched = out.schedule() + self.assertEqual(len(sched), 3) + self.assertEqual(sched[0].bufs[0].dtype, dtypes.float) + + def test_softmax_backward(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 12, 64, 64, requires_grad=True).realize() + x.softmax().sum().backward() + run_schedule(check_schedule(x.grad, 4)) + + # changed by: multireduce spec + def test_layernorm_onelayer_fusion(self): + Tensor.manual_seed(0) + layer = nn.LayerNorm([10, 10]) + layer.weight = Tensor.randn(10,10).realize() + layer.bias = Tensor.randn(10,10).realize() + x = Tensor.randn(20, 5, 10, 10).realize() + out = layer(x) + # run_schedule(check_schedule(out, 2)) + run_schedule(check_schedule(out, 3)) + y = (x.numpy() - x.numpy().mean(layer.axis, keepdims=True)) + expected = y / np.sqrt((y*y).mean(layer.axis, keepdims=True) + layer.eps) + np.testing.assert_allclose(out.numpy(), expected * layer.weight.numpy() + layer.bias.numpy(), atol=1e-4, rtol=1e-4) + + def test_scaled_dot_product_attention_fusion(self): + x, y, z, m = (Tensor.empty(32, 8, 16, 16) for _ in range(4)) + out = Tensor.scaled_dot_product_attention(x, y, z, attn_mask=m) + check_schedule(out, 5) + + def test_scaled_dot_product_attention_causal_fusion(self): + x, y, z = (Tensor.empty(32, 8, 16, 16) for _ in range(3)) + out = Tensor.scaled_dot_product_attention(x, y, z, is_causal=True) + check_schedule(out, 5) + + def test_adam_step_fusion(self): + with Tensor.train(): + x = Tensor.empty(4, 64, 32) + layer = nn.Linear(32, 32*4) + _realize_weights(layer) + opt = nn.optim.Adam(nn.state.get_parameters(layer), lr=1e-4) + layer(x).relu().sum().backward() + check_schedule(opt.schedule_step(), 16) + + def test_adam_conv_fuse(self): + with Tensor.train(): + img = Tensor.empty(2,3,4,4) + c1 = nn.Conv2d(3,32,3) + _realize_weights(c1) + opt = nn.optim.Adam(nn.state.get_parameters(c1), lr=1e-4) + opt.zero_grad() + c1(img).relu().sum().backward() + check_schedule(opt.schedule_step(), 16) + + def test_adam_2convs_fuse(self): + with Tensor.train(): + img = Tensor.empty(2,3,4,4) + c1 = nn.Conv2d(3,16,3,bias=False) + c2 = nn.Conv2d(16,32,2,bias=False) + _realize_weights([c1, c2]) + opt = nn.optim.Adam(nn.state.get_parameters([c1, c2]), lr=1e-4) + opt.zero_grad() + c2(c1(img).relu()).relu().sum().backward() + check_schedule(opt.schedule_step(), 20) + + def test_sgd_conv_fuse(self): + with Tensor.train(): + img = Tensor.empty(2,3,4,4) + c1 = nn.Conv2d(3,32,3) + _realize_weights(c1) + opt = nn.optim.SGD(nn.state.get_parameters(c1)) + opt.zero_grad() + c1(img).relu().sum().backward() + check_schedule(opt.schedule_step(), 3) + + def test_sgd_2convs_fuse(self): + with Tensor.train(): + img = Tensor.empty(2,3,4,4) + c1 = nn.Conv2d(3,16,3,bias=False) + c2 = nn.Conv2d(16,32,2,bias=False) + _realize_weights([c1, c2]) + opt = nn.optim.SGD(nn.state.get_parameters([c1, c2])) + opt.zero_grad() + c2(c1(img).relu()).relu().sum().backward() + check_schedule(opt.schedule_step(), 7) + + @unittest.skipUnless(is_dtype_supported(dtypes.ulong), "Needs ulong") + def test_fold_2convs_sgd_nesterov_momentum_wd(self): + with Tensor.train(): + img = Tensor.empty(2,3,4,4) + c1 = nn.Conv2d(3,16,3,bias=False) + c2 = nn.Conv2d(16,32,2,bias=False) + _realize_weights([c1, c2]) + opt = nn.optim.SGD(nn.state.get_parameters([c1, c2]), nesterov=True, momentum=0.9, weight_decay=0.1) + opt.zero_grad() + c2(c1(img).relu()).relu().sum().backward() + check_schedule(opt.schedule_step(), 13) + + def test_sgd_4convs_fuse(self): + with Tensor.train(): + img = Tensor.empty(2,3,16,16) + c1 = nn.Conv2d(3,4,3,bias=False) + c2 = nn.Conv2d(4,8,3,bias=False) + c3 = nn.Conv2d(8,16,3,bias=False) + c4 = nn.Conv2d(16,32,3,bias=False) + _realize_weights([c1, c2, c3, c4]) + opt = nn.optim.SGD(nn.state.get_parameters([c1, c2, c3, c4])) + opt.zero_grad() + c4(c3(c2(c1(img).relu()).relu()).relu()).relu().sum().backward() + check_schedule(opt.schedule_step(), 17) + + def test_sgd_4convs_fuse_conv_bw(self): + with Tensor.train(): + img = Tensor.empty(2,3,16,16) + c1 = nn.Conv2d(3,4,3,bias=False) + c2 = nn.Conv2d(4,8,3,bias=False) + c3 = nn.Conv2d(8,16,3,bias=False) + c4 = nn.Conv2d(16,32,3,bias=False) + _realize_weights([c1, c2, c3, c4]) + opt = nn.optim.SGD(nn.state.get_parameters([c1, c2, c3, c4])) + opt.zero_grad() + c4(c3(c2(c1(img).relu()).relu()).relu()).relu().sum().backward() + with Context(FUSE_CONV_BW=1): check_schedule(opt.schedule_step(), 14) + + @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") + def test_prefer_half_buffer(self): + x = Tensor.ones(4).contiguous().realize() + # y = Tensor.ones(4).contiguous().realize() + z = Tensor.ones(4, 4).contiguous().realize() + + # should not create extra kernel if output will be realized anyways + dummy = x.sum().half().float() + check_schedule(dummy, 1) + dummy = x.sum().half().float().contiguous() + 1 + check_schedule(dummy, 2) + + # shared between two outputs + shared = x.sum().half().float() + a = shared * 2 + b = shared * 3 + sched = check_schedule([a, b], 3) + # store reduceop in half + self.assertEqual(sched[0].bufs[0].dtype, dtypes.half) + # fuse cast with the child kernel + self.assertEqual(sched[1].bufs[0].dtype, dtypes.float) + self.assertEqual(sched[2].bufs[0].dtype, dtypes.float) + + # reduce + a = z.sum(axis=0).half().float().sum(axis=0) + sched = check_schedule(a, 2) + self.assertEqual(sched[0].bufs[0].dtype, dtypes.half) + self.assertEqual(sched[1].bufs[0].dtype, dtypes.float) + + # expand + # expand will realize just after the .float(), so requires change to realize-before-expand + # normal = (x.sum().half().float().reshape(1) * y).sum() + # sched = check_schedule(normal, 2) + # for si in sched[:-1]: assert all(out.dtype == dtypes.half for out in si.outputs[:-1]) + + # parallel reduce + # a = x.sum().half().float() * y.sum().half().float() + # b = a + 1 + # c = a + 2 + # sched = check_schedule([b, c], 4) + # doesn't store either in half because it doesn't chase + + def test_reduce_simple_chase(self): + a = Tensor.empty(4, 4, 4) + r = a.sum(0) + 6 + b = r.sum(0) * 4 + c = r.sum(1) * 2 + schedule = check_schedule([b, c], 3) + self.assertIs(store_val(schedule[0]).op, Ops.ADD) + + def test_multireduce_simple_chase(self): + Tensor.manual_seed(0) + a = Tensor.randn(4, 4, 4).realize() + r = (a + (a.sum(0, keepdim=True) + 6)).sum(0) * 2 + b = r.sum(0) + 8 + c = r.sum(1) + 12 + np_r = (a.numpy() + (a.numpy().sum(0) + 6)).sum(0) * 2 + # schedule = check_schedule([b,c], 3) + # self.assertIs(schedule[0].ast[0].src[0].arg, Ops.MUL) + schedule = check_schedule([b,c], 4) + run_schedule(schedule) + np.testing.assert_allclose(b.numpy(), np_r.sum(0) + 8, atol=1e-4, rtol=1e-4) + np.testing.assert_allclose(c.numpy(), np_r.sum(1) + 12, atol=1e-4, rtol=1e-4) + + def test_push_permute_chase(self): + a = Tensor.empty(4, 4, 4) + b = Tensor.empty(4, 4) + r = a.sum(2) + b + d = r.T * 4 + e = r * d + schedule = check_schedule([d, e], 3) + self.assertIs(store_val(schedule[0]).op, Ops.ADD) + + def test_multireduce_push_permute_chase(self): + Tensor.manual_seed(0) + a = Tensor.randn(4, 4, 4).realize() + b = Tensor.randn(4, 4).realize() + r = a.sum(2) + b + d = r.T * 4 + e = r * (d + a).sum(2) + schedule = check_schedule([d, e], 3) # make sure it doesn't fuse + self.assertIs(store_val(schedule[0]).op, Ops.ADD) + run_schedule(schedule) + np.testing.assert_allclose(d.numpy(), (a.numpy().sum(2) + b.numpy()).T * 4, atol=1e-4, rtol=1e-4) + np.testing.assert_allclose(e.numpy(), (a.numpy().sum(2) + b.numpy()) * (d.numpy() + a.numpy()).sum(2), atol=1e-4, rtol=1e-4) + + def test_push_shrink_chase(self): + a = Tensor.empty(16, 16) + b = Tensor.empty(4) + c = Tensor.empty(16, ) + r = a.sum(1) + c + d = r[:4] * b + schedule = check_schedule(d, 2) + self.assertIs(store_val(schedule[0]).op, Ops.ADD) + + def test_multireduce_push_shrink_chase(self): + Tensor.manual_seed(0) + a = Tensor.randn(16, 16).realize() + b = Tensor.randn(4).realize() + c = Tensor.randn(16, ).realize() + d = Tensor.randn(16, 16).realize() + r = a.sum(1) + c + out = r[:4] * b + d.sum(1)[:4] + # schedule = check_schedule(out, 2) + schedule = check_schedule(out, 3) + self.assertIs(store_val(schedule[0]).op, Ops.ADD) + run_schedule(schedule) + np.testing.assert_allclose(out.numpy(), (a.numpy().sum(1) + c.numpy())[:4] * b.numpy() + d.numpy().sum(1)[:4], atol=1e-4, rtol=1e-4) + + def test_midreduce_nochase(self): + a = Tensor.empty(16, 16) + b = (a.sum(0) + a.max(1)) + 2 + schedule = check_schedule(b, 2) + self.assertIs(store_val(schedule[0]).op, Ops.REDUCE_AXIS) + + def test_multireduce_midreduce_nochase(self): + Tensor.manual_seed(0) + a = Tensor.randn(16, 16).realize() + b = (a.sum(0)+a.max(0) + a.max(1)+a.sum(1)) + 2 + # schedule = check_schedule(b, 2) + schedule = check_schedule(b, 4) + self.assertIs(store_val(schedule[0]).op, Ops.REDUCE_AXIS) + run_schedule(schedule) + np.testing.assert_allclose(b.numpy(), a.numpy().sum(0)+a.numpy().max(0) + a.numpy().max(1)+a.numpy().sum(1)+2, atol=1e-4, rtol=1e-4) + + # changed by: multireduce spec + # pattern in test_transformer + def test_partial_fuse1(self): + Tensor.manual_seed(0) + a = Tensor.randn(16, 16).realize() + b = Tensor.randn(16, 16).realize() + c = a.sum() + 2 + d = (a.sum() - b.sum()) * 4 + # run_schedule(check_schedule([c, d], 1)) + run_schedule(check_schedule([c, d], 3)) + np.testing.assert_allclose(c.numpy(), a.numpy().sum()+2, atol=1e-4, rtol=1e-4) + np.testing.assert_allclose(d.numpy(), (a.numpy().sum() - b.numpy().sum()) * 4, atol=1e-4, rtol=1e-4) + + # changed by: multireduce spec + # pattern in conv + def test_partial_fuse2(self): + Tensor.manual_seed(0) + a = Tensor.randn(16, 16).realize() + b = Tensor.randn(16, 16).realize() + c = a.sum() + 2 + d = b.sum() - c + # run_schedule(check_schedule([c, d], 1)) + run_schedule(check_schedule([c, d], 2)) + np.testing.assert_allclose(c.numpy(), a.numpy().sum()+2, atol=1e-4, rtol=1e-4) + np.testing.assert_allclose(d.numpy(), b.numpy().sum()-(a.numpy().sum()+2), atol=1e-4, rtol=1e-4) + + # changed by: multireduce spec + # pattern in adam + @unittest.expectedFailure + def test_partial_fuse3(self): + Tensor.manual_seed(0) + a = Tensor.randn(16, 16).realize() + b = Tensor.randn(16, 16).realize() + c = a.sum() + 2 + d = a.sum() * 2 + e = c * d + f = b.sum() - e + # run_schedule(check_schedule([c, d, e, f], 1)) + run_schedule(check_schedule([c, d, e, f], 2)) + np.testing.assert_allclose(c.numpy(), c_np:=a.numpy().sum()+2, atol=1e-4, rtol=1e-4) + np.testing.assert_allclose(d.numpy(), d_np:=a.numpy().sum()*2, atol=1e-4, rtol=1e-4) + np.testing.assert_allclose(e.numpy(), e_np:=c_np*d_np, atol=1e-4, rtol=1e-4) + np.testing.assert_allclose(f.numpy(), b.numpy().sum() - e_np, atol=1e-4, rtol=1e-4) + + # changed by: multireduce spec + @unittest.expectedFailure + def test_partial_fuse4(self): + Tensor.manual_seed(0) + a = Tensor.randn(16, 16).realize() + b = Tensor.randn(16, 16).realize() + c = a.sum() + 2 + d = a.sum() * 2 + e = c * d + f = (b - d).sum() - e + # run_schedule(check_schedule([c, d, e, f], 1)) + run_schedule(check_schedule([c, d, e, f], 3)) + np.testing.assert_allclose(c.numpy(), c_np:=a.numpy().sum()+2, atol=1e-4, rtol=1e-4) + np.testing.assert_allclose(d.numpy(), d_np:=a.numpy().sum()*2, atol=1e-4, rtol=1e-4) + np.testing.assert_allclose(e.numpy(), e_np:=c_np*d_np, atol=1e-4, rtol=1e-4) + np.testing.assert_allclose(f.numpy(), (b.numpy()-d_np).sum()-e_np, atol=1e-4, rtol=1e-4) + + def test_pad_reduce_safe(self): + Tensor.manual_seed(0) + a = Tensor.rand(3, 4, 5).realize() + b = Tensor.rand(3, 4, 5).realize() + out = (a + b).pad(((0, 1), (0, 1), (0, 1)), value=1.0).sum().contiguous() + run_schedule(check_schedule(out, 1)) + np.testing.assert_allclose(out.numpy(), np.pad(a.numpy()+b.numpy(), ((0, 1), (0, 1), (0, 1)), constant_values=1.0).sum(), atol=1e-5, rtol=1e-6) + + def test_multireduce_pad_reduce_safe(self): + Tensor.manual_seed(0) + a = Tensor.randn(3, 4, 5).realize() + b = Tensor.randn(3, 4, 5).realize() + out = (a.pad(((0, 1), (0, 1), (0, 1)), value=1.0).sum(keepdim=True)+b.pad(((0, 1), (0, 1), (0, 1)), value=1.0).sum()).contiguous() + # run_schedule(check_schedule(out, 1)) + run_schedule(check_schedule(out, 2)) + np.testing.assert_allclose(out.numpy(), np.pad(a.numpy(), ((0, 1), (0, 1), (0, 1)), constant_values=1.0).sum(keepdims=True) + \ + np.pad(b.numpy(), ((0, 1), (0, 1), (0, 1)), constant_values=1.0).sum(), atol=1e-4, rtol=1e-4) + + def test_pad_reduce_unsafe(self): + Tensor.manual_seed(0) + a = Tensor.rand(3, 4, 5).realize() + out = a.log2().pad(((0, 1), (0, 1), (0, 1)), value=1.0).sum().contiguous() + run_schedule(check_schedule(out, 2)) + np.testing.assert_allclose(out.numpy(), np.pad(np.log2(a.numpy()), ((0, 1), (0, 1), (0, 1)), constant_values=1.0).sum(), atol=1e-5, rtol=1e-6) + + def test_multireduce_pad_reduce_unsafe(self): + Tensor.manual_seed(0) + a = Tensor.randn(3, 4, 5).abs().realize() + b = Tensor.randn(3, 4, 5).abs().realize() + out = (a.log2().pad(((0, 1), (0, 1), (0, 1)), value=1.0).sum()+b).abs().log2().pad(((0, 1), (0, 1), (0, 1)), value=1.0).sum().contiguous() + # run_schedule(check_schedule(out, 1)) + run_schedule(check_schedule(out, 4)) + np.testing.assert_allclose(out.numpy(), np.pad(np.log2(np.abs(np.pad(np.log2(a.numpy()), ((0, 1), (0, 1), (0, 1)), constant_values=1.0).sum() + \ + b.numpy())), ((0, 1), (0, 1), (0, 1)), constant_values=1.0).sum(), atol=3e-4, rtol=1e-6) + + def test_shrink_pad_safe(self): + a = Tensor.ones((3, )).contiguous().realize() + b = Tensor.ones((3, )).contiguous().realize() + out = (a + b).shrink(((0, 1),)).pad(((0, 1),)).contiguous() + run_schedule(check_schedule(out, 1)) + np.testing.assert_equal(out.numpy(), [2, 0]) + + def test_shrink_pad_unsafe(self): + a = Tensor.ones((3, )).contiguous().realize() + out = a.exp2().shrink(((0, 1),)).pad(((0, 1),)).contiguous() + run_schedule(check_schedule(out, 2)) + np.testing.assert_equal(out.numpy(), [2, 0]) + + def test_base_change_shrink_pad(self): + a = Tensor.ones(3, 3).contiguous().realize() + b = a.exp2() + c = b[:-1, :-1] + d = c.pad(((0, 1), (0, 1))) * 2 + run_schedule(check_schedule(d, 2)) + np.testing.assert_equal(d.numpy(), np.pad(np.exp2(a.numpy())[:-1, :-1], ((0, 1), (0, 1)))*2) + + def test_base_change_expand_pad(self): + a = Tensor.ones(3, 3).contiguous().realize() + b = a.exp2() + c = b[:, None, :] + d = c.pad(((0, 0), (1, 1), (0, 0))) * 2 + run_schedule(check_schedule(d, 2)) + np.testing.assert_equal(d.numpy(), np.pad(np.exp2(a.numpy())[:, None, :], ((0, 0), (1, 1), (0, 0)))*2) + + def test_fuse_arange_pad_replicate_mode(self): + x = Tensor.empty(3,3,3,3, requires_grad=True) + y = x.pad((-1,2,2,-1), mode="replicate") + dx = y.sum().gradient(x)[0] + with Context(FUSE_ARANGE=1): + sched = check_schedule(dx, 3) + run_schedule(sched) + np.testing.assert_allclose(dx.numpy(), [[[[0.,3.,9.],[0,1.,3.],[0.,0.,0.]]]*3]*3) + + # TODO like openpilot with imagef + @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") + def test_base_change_expand_expand(self): + a = Tensor.ones(4, 4).contiguous().realize() + b = a.cast(dtypes.half).expand(2, 4, 4) + c = b.cast(dtypes.int).expand(2, 2, 4, 4) + run_schedule(check_schedule(c, 2)) + np.testing.assert_equal(c.numpy(), np.ones(((2, 2, 4, 4)), dtype=np.int32)) + + def test_base_change_pad_expand(self): + a = Tensor.full((4, 4), 1.).contiguous().realize() + b = Tensor.full((4, 4), 2.).contiguous().realize() + c = (a + b).pad(((1, 1), (1, 1))) + d = c.cast(dtypes.int).expand((2, 6, 6)) * 4 + run_schedule(check_schedule(d, 2)) + c_np = np.pad((np.full((4, 4), 2., dtype=np.float32) + np.full((4, 4), 1., dtype=np.float32)), ((1, 1), (1, 1)), constant_values=0.0) + np.testing.assert_equal(d.numpy(), np.broadcast_to(c_np.astype(np.half), (2, *c_np.shape)) * 4) + + def test_pad_reduce_unsafe_multiview_st(self): + P = Tensor.ones(3, 3).contiguous() + sums = P.sum(axis=1, keepdim=True) + P /= sums + p = P[0] + p = p.pad(((1, 0), )) + p = p.repeat([2]) + run_schedule(check_schedule(p, 3)) + tiny_ret = p.numpy() + + P = np.ones((3, 3), dtype=np.float32) + sums = P.sum(axis=1, keepdims=True) + P /= sums + p = P[0] + p = np.pad(p, (1, 0), 'constant') + p = np.tile(p, 2) + np.testing.assert_allclose(tiny_ret, p) + + def test_bitcast_fuses(self): + x = Tensor.empty(1, dtype=dtypes.float32) + a = x.exp2().bitcast(dtypes.int32) + b = x.bitcast(dtypes.int32) + check_schedule(a+b, 1) # this should fuse when it makes sense + + @unittest.skip("disabling subbuffer manually isn't supported anymore") + def test_bitcast_disable_subbufer(self): + x = cast(UOp, Tensor.empty(1, dtype=dtypes.float32).realize().uop) + a = x.alu(Ops.EXP2).cast(dtypes.int32, True, allow_buffer_view=False) + b = x.cast(dtypes.int32, True, allow_buffer_view=False) + b = a.alu(Ops.ADD, b) + check_schedule(b, 1) + + def test_reduceop_reshape_dont_push(self): + Tensor.manual_seed(0) + x = Tensor.randn(10, 20).realize() + out = x.argmax(1) + run_schedule(check_schedule(out, 3)) # TODO: push a reduceop through a reshape + + def test_conv2d(self): _test_conv2d(7) + def test_conv2d_fused(self): _test_conv2d(5, FUSE_CONV_BW=1) + + @unittest.skipUnless(is_dtype_supported(dtypes.half) and is_dtype_supported(dtypes.ulong), "need half and ulong") + def test_conv2d_half(self): _test_conv2d(7, dtype=dtypes.half) + @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") + @unittest.skipIf(Device.DEFAULT == "WEBGPU", "Causes other tests to fail") + @unittest.expectedFailure + def test_conv2d_fused_half(self): _test_conv2d(5, dtype=dtypes.half) + + def test_schedule_mem_used(self): + base = GlobalCounters.mem_used + Tensor.ones(256).contiguous().realize() + Tensor.ones(5, 5).contiguous().schedule() + self.assertEqual(GlobalCounters.mem_used-base, 0) + + @unittest.skip("TODO: this is consistently creating non reproducible failures") + def test_schedule_mem_used_with_inputs(self): + base = GlobalCounters.mem_used + x = Tensor.ones(256).contiguous().realize() + (x+Tensor.ones(256).contiguous()).schedule() + self.assertEqual(GlobalCounters.mem_used-base, 1024) + + def test_const_schedule(self): + constv = Tensor.empty(2, 2).uop.const_like(10) + check_schedule(constv, 0) + + def test_const_schedule_contig(self): + constv = Tensor.empty(2, 2).uop.const_like(10).contiguous() + check_schedule(constv, 1) + + @unittest.skipIf(Device.DEFAULT != "GPU", "image only supported on GPU") + def test_image_matmul(self): + with Context(IMAGE=2): + x = Tensor.randn((9, 9)).realize() + y = Tensor.randn((9, 9)).realize() + out = x@y + run_schedule(check_schedule(out, 3)) + np.testing.assert_allclose(out.numpy(), x.numpy()@y.numpy(), atol=1e-4, rtol=1e-4) + self.assertIsInstance(out.dtype, ImageDType) + self.assertIsNotNone(out.uop.base.realized) + self.assertIsInstance(out.uop.base.realized.dtype, ImageDType) + + def _test_fusion(self, shapes, f, cnt): + with Context(DEBUG=0, TRACK_MATCH_STATS=0): args = [Tensor.randn(s).realize() for s in shapes] + run_schedule(check_schedule(compare:=f(*args), cnt)) + if getenv("COMPARE", 1): + import torch + good = f(*[torch.tensor(x.numpy()) for x in args]) + np.testing.assert_allclose(compare.numpy(), good.numpy(), atol=1e-4, rtol=1e-4) + + def test_late_fusion_simple(self): + self._test_fusion([(4, 4), (4, 1)], lambda a,b:a.sum(1, keepdim=True)+b, 1) + + def test_late_fusion_post_reshape(self): + self._test_fusion([(4, 4), (1, 4)], lambda a,b:a.sum(1).reshape(b.shape)+b, 1) + + def test_late_fusion_post_permute(self): + self._test_fusion([(4, 6, 4), (4, 4, 1)], lambda a,b:a.sum(1, keepdim=True).permute((2, 0, 1))+b, 2) + + def test_late_fusion_double_transpose(self): + self._test_fusion([(32, 16, 1)], + lambda a:(a.expand(32, 16, 16).sum((2,), keepdim=True).permute((1, 0, 2))+2).permute((1, 0, 2)).contiguous(), 1) + + def test_late_fusion_post_expand(self): + self._test_fusion([(32, 32)], lambda a:a-a.sum(1), 2) + + def test_cast_padded_view(self): + a = Tensor.arange(4).reshape(1, 4) + casted_view = a.pad(((0, 1), (0, 0))).cast(dtypes.float) + casted_view.realize() + self.assertEqual(casted_view.uop.base.realized.size, 4) + realized_view = casted_view.contiguous().realize() + self.assertEqual(realized_view.uop.base.realized.size, 8) + self.assertListEqual(realized_view.tolist(), [[0.0, 1.0, 2.0, 3.0], [0.0, 0.0, 0.0, 0.0]]) + + # NOTE: we only reorder CAST if it's an EXPAND + def test_cast_after_shrink(self): + a = Tensor.arange(4).reshape(1, 4) + casted_view = a.shrink(((0, 1), (0, 2))).cast(dtypes.float) + casted_view.realize() + self.assertEqual(casted_view.uop.base.realized.size, 2) + realized_view = casted_view.contiguous().realize() + self.assertEqual(realized_view.uop.base.realized.size, 2) + self.assertListEqual(realized_view.tolist(), [[0, 1]]) + + def test_cast_const_view(self): + a = Tensor.ones((4, 4), dtype=dtypes.float32) + casted_view = a.cast(dtypes.int32) + run_schedule(check_schedule(casted_view, 0)) + self.assertIsNone(casted_view.uop.base.realized) + realized_const_view = casted_view.contiguous() + run_schedule(check_schedule(realized_const_view, 1)) + self.assertListEqual(realized_const_view.tolist(), [[1, 1, 1, 1], [1, 1, 1, 1], [1, 1, 1, 1], [1, 1, 1, 1]]) + + @given(strat.sampled_from(dtypes.all), strat.sampled_from(dtypes.all)) + def test_cast_padded_const(self, dt1, dt2): + assume(is_dtype_supported(dt1) and is_dtype_supported(dt2)) + a = Tensor(1, dtype=dt1).reshape(1, 1).pad(((1, 1), None)) + casted_view = a.cast(dt2) + run_schedule(check_schedule(casted_view, 0)) + realized_const_view = casted_view.contiguous() + run_schedule(check_schedule(realized_const_view, 1)) + np.testing.assert_equal(realized_const_view.numpy(), [[0], [1], [0]]) + +class TestIndexing(unittest.TestCase): + def check_schedule(self, xt:Union[Tensor,List[Tensor]], cnt:int): + with Context(FUSE_ARANGE=getenv("FUSE_ARANGE", 1)): + lst = [xt] if isinstance(xt, Tensor) else xt + s = Tensor.schedule(*lst) + lowered = [x[1] for x in lower_schedule(s.copy())] + kernels = [ei for ei in list(lowered) if isinstance(ei.prg, CompiledRunner)] + if FUSE_ARANGE: self.assertEqual(len(kernels), cnt) + for ei in lowered: ei.run(do_update_stats=True) + return s + + def test_simple_indexing(self): + X = Tensor.randn(10, 10).realize() + idxs = Tensor([0, 2]).realize() + xt = X[idxs] + self.check_schedule(xt, 2) + np.testing.assert_equal(xt.numpy(), X.numpy()[idxs.numpy()]) + + def test_simple_indexing_alt(self): + X = Tensor.arange(16).reshape(4, 4) + xt = X[[1, 2], [1, 2]] + self.check_schedule(xt, 5) + np.testing.assert_equal(xt.numpy(), (np.arange(16).reshape(4, 4))[[1, 2], [1, 2]]) + + def test_advanced_indexing(self): + X = Tensor.arange(10)+1 + xt = X[[0]] + self.check_schedule(xt, 2) + np.testing.assert_equal(xt.numpy(), (np.arange(10)+1)[[0]]) + + def test_advanced_indexing_alt(self): + X = Tensor.arange(6).reshape(3, 2)+1 + xt = X[[Tensor([2]), Tensor([1])]] + self.check_schedule(xt, 6) + np.testing.assert_equal(xt.numpy(), 6) + + def test_advanced_simple_indexing_combined(self): + X = Tensor.arange(16).reshape(4, 4) + xt = X[1:2, [1, 2]] + self.check_schedule(xt, 4) + + def test_push_through_reshape(self): + Tensor.manual_seed(0) + x = Tensor.randn(10, 20).realize() + out = x.argmax(1) + self.check_schedule(out, 2) + np.testing.assert_allclose(out.numpy(), np.argmax(x.numpy(), 1)) + + def test_arange_push_through_expand(self): + Tensor.manual_seed(0) + a = Tensor.arange(4,) + b = Tensor.randn(4, 4).realize() + out = (a+b).sum() + self.check_schedule(out, 1) + np.testing.assert_allclose(out.numpy(), (np.arange(4)+b.numpy()).sum(), atol=1e-5) + + def test_argmin(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 32).realize() + out = x.argmin(-1) + self.check_schedule(out, 2) + np.testing.assert_equal(out.numpy(), x.numpy().argmin(axis=-1)) + + def test_argmax(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 32).realize() + out = x.argmax(-1) + self.check_schedule(out, 2) + np.testing.assert_equal(out.numpy(), x.numpy().argmax(axis=-1)) + + def test_arange_transposed(self): + Tensor.manual_seed(0) + x = Tensor.randint(4, 1).realize() + a = ((Tensor.arange(4,)*x).T).sum() + self.check_schedule(a, 1) + np.testing.assert_equal(a.numpy(), (np.arange(4)*x.numpy()).T.sum()) + + def test_div_padded_arange(self): + x = Tensor.full((2,2), 16) + y = x.idiv(Tensor.linspace(2, 8, steps=4, dtype=dtypes.int).reshape(2,2)).pad(((1,1), (1,1))) + out = y.sum(axis=1) + with Context(FUSE_ARANGE=1): run_schedule(check_schedule(out, 2)) + self.assertListEqual(out.tolist(), [0, 12, 4, 0]) + + def test_arange_transposed_descendants(self): + Tensor.manual_seed(0) + x = Tensor.randint(4, 1).realize() + a = (Tensor.arange(4,)*x).T + b = Tensor.randint(4, 4).realize() + out = (a+b).sum() + self.check_schedule(out, 1) + np.testing.assert_equal(out.numpy(), ((np.arange(4)*x.numpy()).T+b.numpy()).sum()) + + def test_arange_index(self): + Tensor.manual_seed(0) + x = Tensor.randn(5, 2).realize() + a = Tensor.arange(10) + out = (x + a[2]).sum() + self.check_schedule(out, 1) + np.testing.assert_allclose(out.numpy(), (x.numpy()+np.arange(10)[2]).sum(), atol=1e-5, rtol=1e-6) + + def test_arange_index_shrink(self): + Tensor.manual_seed(0) + with Context(TRACK_MATCH_STATS=0): + x = Tensor.randn(11).realize() + a = Tensor.arange(22) + out = (x + a[:11]).sum() + self.check_schedule(out, 1) + + def test_arange_index_contiguous(self): + Tensor.manual_seed(0) + x = Tensor.randn(5, 2).realize() + a = Tensor.arange(10).contiguous() + out = (x + a[2]).sum() + self.check_schedule(out, 3) + np.testing.assert_allclose(out.numpy(), (x.numpy()+np.arange(10)[2]).sum(), atol=1e-5, rtol=1e-6) + + def test_arange_index_child(self): + Tensor.manual_seed(0) + x = Tensor.randn(5, 2).realize() + a = Tensor.arange(10)+1 + out = (x + a[2]).sum() + self.check_schedule(out, 1) + np.testing.assert_allclose(out.numpy(), (x.numpy()+(np.arange(10)+1)[2]).sum(), atol=1e-5, rtol=1e-6) + + def test_arange_index_contiguous_child(self): + Tensor.manual_seed(0) + x = Tensor.randn(5, 2).realize() + a = (Tensor.arange(10)+1).contiguous() + out = (x + a[2]).sum() + self.check_schedule(out, 3) + np.testing.assert_allclose(out.numpy(), (x.numpy()+(np.arange(10)+1)[2]).sum(), atol=1e-5, rtol=1e-6) + + def test_arange_childless_base(self): + a = Tensor.arange(4) + self.check_schedule(a, 1) + np.testing.assert_equal(a.numpy(), np.arange(4)) + + def test_arange_childless_view(self): + a = Tensor.arange(4).reshape(2, 2) + a[0] = 4 + np.testing.assert_equal(a.numpy(), [[4, 4], [2, 3]]) + + def test_arange_group_childless_base(self): + Tensor.manual_seed(0) + x = Tensor.randint(4).realize() + a = Tensor.arange(4)+x + self.check_schedule(a, 1) + np.testing.assert_equal(a.numpy(), np.arange(4)+x.numpy()) + + def test_arange_group_childless_view(self): + Tensor.manual_seed(0) + x = Tensor.ones(4).contiguous().realize() + a = Tensor.arange(4)+x + a[0] = 6 + np.testing.assert_equal(a.numpy(), [6., 2., 3., 4.]) + + @unittest.skip("BUFFER_VIEW no longer supported on non-disk devices") + def test_arange_view_op(self): + a = Tensor.arange(12).reshape(4, 3).shrink(((1, 2), (1, 3))).contiguous() + sched = self.check_schedule(a, 1) + self.assertIs(sched[1].ast.op, Ops.BUFFER_VIEW) + np.testing.assert_equal(a.numpy(), [[4, 5]]) + + @unittest.skipIf(Device.DEFAULT == "CPU", "tests copy from ext device") + def test_arange_shrink_copy(self): + a = Tensor.arange(12).reshape(4, 3).shrink(((1, 2), (1, 3))).to("CPU") + sched = self.check_schedule(a, 2) # NOTE: there is a contiguous between REDUCE_AXIS and COPY + self.assertIs(sched[-1].ast.op, Ops.COPY) + np.testing.assert_equal(a.numpy(), [[4, 5]]) + + @unittest.skipIf(Device.DEFAULT == "CPU", "tests copy from ext device") + def test_arange_expand_copy(self): + a = Tensor.arange(4).reshape(2, 2, 1).expand(2, 2, 2).contiguous().to("CPU") + sched = self.check_schedule(a, 2) # NOTE: there is a contiguous between REDUCE_AXIS and COPY + self.assertIs(sched[2].ast.op, Ops.COPY) + self.assertIs(store_val(sched[1]).op, Ops.LOAD) + self.assertIs(store_val(sched[0]).op, Ops.ADD) + np.testing.assert_equal(a.numpy(), [[[0, 0], [1, 1]], [[2, 2], [3, 3]]]) + + @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") + def test_precompute_freqs_cis(self): + from extra.models.llama import precompute_freqs_cis + args = {"dim":32 if CI else 128, "end":2048 if CI else 8192, "theta":10000} + fused = precompute_freqs_cis(**args) + with Context(FUSE_ARANGE=1): + run_schedule(check_schedule(fused, 3)) + if getenv("CHECK", 1): + ref = precompute_freqs_cis(**args) + run_schedule(check_schedule(ref, 3)) + np.testing.assert_equal(fused.numpy(), ref.numpy()) + + def test_fuse_assign_contiguous(self): + x = Tensor.zeros(4, 4, dtype=dtypes.int).contiguous().realize() + a = Tensor.arange(8).reshape(4, 2) + self.check_schedule(x.shrink((None, (0, 2))).assign(a.contiguous()), 2) + np.testing.assert_equal(x.numpy(), [[0, 1, 0, 0], [2, 3, 0, 0], [4, 5, 0, 0], [6, 7, 0, 0]]) + + def test_assign_non_contiguous(self): + x = Tensor.zeros(4, 4, dtype=dtypes.int).contiguous().realize() + y = Tensor.randint(4, 2) + a = Tensor.arange(8).reshape(4, 2)+y + x.shrink((None, (0, 2))).assign(a).realize() + xref = np.zeros((4, 4), dtype=int) + xref[:, :2] = np.arange(8).reshape(4, 2)+y.numpy() + np.testing.assert_equal(x.numpy(), xref) + + def test_sparse_categorical_crossentropy_simple(self): + X = Tensor([[0, 2, 3], [1, 2, 3]]).realize() + Y = Tensor([1, 2]).realize() + loss = X.sparse_categorical_crossentropy(Y) + self.check_schedule(loss, 4) + np.testing.assert_allclose(loss.item(), 0.878309, atol=1e-5, rtol=1e-6) + + @unittest.skipIf(Device.DEFAULT == "WEBGPU", "Validation error on WebGPU") + def test_mnist_val(self): + from tinygrad.nn.datasets import mnist + import torch + _, Y_train, _, _ = mnist() + samples = Tensor.randint(BS:=getenv("BS", 512), high=cast(int,Y_train.shape[-1])).realize() + yt = Tensor.randn(BS, 10).realize() + with Context(SPLIT_REDUCEOP=0): + loss = yt.sparse_categorical_crossentropy(Y_train[samples]) + self.check_schedule(loss, 6) + loss_fused = loss.numpy() + loss_ref = torch.nn.CrossEntropyLoss()(torch.tensor(yt.numpy()), torch.tensor(Y_train.numpy())[torch.tensor(samples.numpy())]) + np.testing.assert_allclose(loss_fused, loss_ref.numpy(), atol=1e-6, rtol=1e-6) + + @unittest.expectedFailure + def test_arange_fuse_grouped_children(self): + X = Tensor.randn(4, 4).realize() + r = (X+Tensor.arange(16).reshape(4, 4)).sum() + out0 = r+2 + out1 = r+3 + self.check_schedule([out0, out1], 1) + r_ref = (X.numpy()+np.arange(16).reshape(4, 4)).sum() + np.testing.assert_allclose(out0.numpy(), r_ref+2, rtol=2e-7) + np.testing.assert_allclose(out1.numpy(), r_ref+3, rtol=2e-7) + + def test_dont_fold_arange_contiguous_view(self): + X = Tensor.randn(4, 4).realize() + r = (X+Tensor.arange(16).reshape(4, 4).contiguous()).sum(1, keepdim=True) + self.check_schedule([r], 2) + np.testing.assert_allclose(r.numpy(), (X.numpy()+np.arange(16).reshape(4, 4)).sum(1, keepdims=True), atol=1e-5, rtol=1e-6) + + @unittest.skip("multi output isn't supported") + def test_multiview_arange_children(self): + X = Tensor.randn(2,3,4,4).numpy() + with Context(FUSE_ARANGE=1): + compare = Tensor(X).interpolate(size=(2, 2), mode="linear").numpy() + with Context(FUSE_ARANGE=0, TRACK_MATCH_STATS=0): + ref = Tensor(X).interpolate(size=(2, 2), mode="linear").numpy() + np.testing.assert_allclose(ref, compare, atol=1e-5, rtol=1e-6) + + def test_recursive_swizzle(self): + a = Tensor([1,2,3,4]).realize() + for _ in range(24): a = a + a + new_uop = a.reshape(4,1).realize().uop + self.assertEqual(new_uop.st, ShapeTracker.from_shape((4,)).reshape((4, 1))) + self.assertEqual(swizzle_cnt(new_uop), 0) + + def test_no_rewrite_elementwise(self): + a = Tensor.empty(32, 32) + b = Tensor.empty(32, 32) + sink = (a+b).schedule()[0].ast + self.assertEqual(swizzle_cnt(sink), 0) + + def test_simple_store_reshape(self): + a = Tensor.empty(32, 32).sum(axis=1)+Tensor.empty(1,32) + ast = a.schedule()[0].ast + self.assertEqual(ast.shape, (32, 1)) + self.assertEqual(a.uop.shape, (1, 32)) + + def test_no_reshape_reduceop(self): + a = Tensor.empty(32, 32).sum(axis=(1,)).contiguous() + ast = a.schedule()[0].ast + self.assertEqual(ast.shape, (32, 1)) + self.assertEqual(a.uop.shape, (32,)) + +def swizzle_cnt(u:UOp) -> int: + return len([x for x in u.toposort() if x.op is Ops.VIEW and len(x.src) != 0 and x.src[0].op not in {Ops.BUFFER, Ops.DEFINE_GLOBAL, Ops.ASSIGN}]) + +class TestSwizzle(unittest.TestCase): + def test_swizzle_simple(self): + Tensor.manual_seed(0) + with Context(DEBUG=0, TRACK_MATCH_STATS=0): + a = Tensor.randint(32, 32).realize() + r = (a+a).sum(1).sum(0) + # double reduce collapses to a single reduce + with Context(DONT_GROUP_REDUCES=1): + run_schedule(check_schedule(r, 1)) + self.assertEqual(r.numpy(), (a.numpy()+a.numpy()).sum(1).sum(0)) + + def test_single_swizzle(self): + Tensor.manual_seed(0) + with Context(DEBUG=0, TRACK_MATCH_STATS=0): + a = Tensor.randint(4, 1).realize() + b = Tensor.ones((1, 1), dtype=a.dtype).contiguous().realize() + # ADD(REDUCE(RESHAPE(LOAD)), LOAD) to ADD(REDUCE(RESHAPE(LOAD))), RESHAPE(LOAD) + r = a.sum(0)+b + run_schedule(check_schedule(r, 1)) + self.assertEqual(r.numpy(), a.numpy().sum(0)+1) + + def test_double_swizzle_possible(self): + Tensor.manual_seed(0) + with Context(DEBUG=0, TRACK_MATCH_STATS=0): + a = Tensor.randint(4,).realize() + b = Tensor.randint(4,).realize() + # parallel reduce! + add = a.sum(0)+b.sum(0) + with Context(DONT_GROUP_REDUCES=1): + run_schedule(check_schedule(add, 1)) + self.assertEqual(add.numpy(), a.numpy().sum(0)+b.numpy().sum(0)) + + @unittest.skip("TODO: how do we express the norm") + def test_softmax_one_kernel(self): + Tensor.manual_seed(0) + with Context(DEBUG=0, TRACK_MATCH_STATS=0): + a = Tensor.randn(32, 32).realize() + t = a.softmax() + with Context(DONT_GROUP_REDUCES=1, DONT_REALIZE_EXPAND=1): + check_schedule(t, 1) + + def test_argmax_one_kernel(self): + Tensor.manual_seed(0) + with Context(DEBUG=0, TRACK_MATCH_STATS=0): + a = Tensor.randn(10, 20).realize() + t = a.argmax(0) + with Context(DONT_GROUP_REDUCES=1, DONT_REALIZE_EXPAND=1): t.realize() + + def test_swizzle_reduceop(self): + Tensor.manual_seed(0) + x = Tensor.randn(4,4).realize() + y = Tensor.randn(4,4,4).realize() + out = x.reshape(4,4,1).expand(4,4,4).sum(axis=(1,))+y + with Context(DONT_REALIZE_EXPAND=1, DONT_GROUP_REDUCES=1): + run_schedule(check_schedule(out, 1)) + np.testing.assert_allclose(out.numpy(), np.tile(x.numpy().reshape(4,4,1), (1,1,4)).sum(axis=1)+y.numpy()) + + def test_permute_rewrite(self): + x = Tensor.randn(4, 4, 16).realize() + y = Tensor.randn(4, 1, 16).realize() + z = Tensor.randn(4, 4, 1).realize() + t = (x*y).sum(axis=(0, 2)).reshape(1, 4, 1).permute(0, 2, 1)+z + with Context(DONT_GROUP_REDUCES=1, DONT_REALIZE_EXPAND=1): run_schedule(check_schedule(t, 1)) + t_np = (x.numpy()*y.numpy()).sum(axis=(0, 2)).reshape(1, 4, 1).transpose(0, 2, 1)+z.numpy() + np.testing.assert_allclose(t.numpy(), t_np, atol=1e-6, rtol=1e-3) + + @unittest.skip("TODO: this swizzle isn't resolvable when there's a mask") + def test_swizzle_failure_permute(self): + a = Tensor.empty(45,65).T.reshape(65,1,45).pad((None,None,(0,45))).expand(65,45,90) + b = Tensor.empty(45,65) + a_reduce = a.sum(axis=(2,), keepdim=True).sum(axis=(1,)) + b_reduce = b.sum(axis=(0,)) + t = a_reduce+b_reduce + with Context(DONT_GROUP_REDUCES=1, DONT_REALIZE_EXPAND=1): run_schedule(check_schedule(t, 1)) + + def test_parallel_reduce_possible(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 2, 2).realize() + y = Tensor.randn(4, 2, 2).realize() + t = x.sum(axis=1)+y.sum(axis=1) + with Context(DONT_GROUP_REDUCES=1): run_schedule(check_schedule(t, 1)) + np.testing.assert_allclose(t.numpy(), x.numpy().sum(axis=1)+y.numpy().sum(axis=1), atol=1e-6, rtol=1e-3) + + # kernels can only have 1 or n in each dim + @unittest.expectedFailure + def test_dont_parallelize_different_n(self): + Tensor.manual_seed(0) + x = Tensor.randn(4, 2, 2).realize() + y = Tensor.randn(4, 3, 2).realize() + t = x.sum(axis=1)+y.sum(axis=1) + with Context(DONT_GROUP_REDUCES=1): run_schedule(check_schedule(t, 1)) + np.testing.assert_allclose(t.numpy(), x.numpy().sum(axis=1)+y.numpy().sum(axis=1), atol=1e-6, rtol=1e-3) + + def test_unsafe_pad(self): + x = Tensor.full((2,2), 1.0).contiguous() + y = x*x.sum((1,)).reciprocal() + t = y.pad(((0,1),None)) + run_schedule(check_schedule(t, 3)) + np.testing.assert_equal(t.numpy(), [[0.5, 0.5], [0.5, 0.5], [0., 0.]]) + +def store_val(si:ScheduleItem): return si.ast.src[0].src[1] +zero_pm = UPat(Ops.CONST, arg=0) +class TestView(unittest.TestCase): + def test_all_masked_out(self): + # start with non CONST Ops + a = Tensor.rand(10, 10).realize() + # all masked out, degrades to const 0 + b = a.pad(((0, 10), None))[10:] + sched = check_schedule(b.contiguous(), 1) + assert zero_pm.match(store_val(sched[-1]), {}) + run_schedule(sched) + np.testing.assert_equal(b.numpy(), 0) + + def test_mask_dim_1(self): + # mask out dim = 1 works too + a = Tensor.rand(10, 10).realize() + b = a.pad((None, (0, 10)))[:, 10:] + assert b.shape == (10, 10) + sched = check_schedule(b.contiguous(), 1) + self.assertEqual(sched[-1].ast.full_shape, (10, 10)) + assert zero_pm.match(store_val(sched[-1]), {}) + run_schedule(sched) + np.testing.assert_equal(b.numpy(), 0) + + def test_zero_size_alt(self): + a = Tensor.empty(135, 0, 9) + b = a.pad(((0, 0), (0, 0), (18, 0))) + check_schedule(b, 0) + + def test_partial_mask(self): + # partial masked out does not degrade into CONST + a = Tensor.rand(10, 10).realize() + b = a.pad(((0, 5), None))[5:] + assert b.shape == (10, 10) + sched = check_schedule(b.contiguous(), 1) + self.assertEqual(store_val(sched[-1]).op, Ops.LOAD) + self.assertEqual(store_val(sched[-1]).st_arg, b.uop.st) + run_schedule(sched) + np.testing.assert_allclose(b.numpy(), np.pad(a.numpy(), ((0, 5), (0, 0)))[5:]) + + # a*VIEW(x), where VIEW(x) = 0 + # x collapses along with its children + def test_parent_view_collapses(self): + a = Tensor([1, 2]) + b = Tensor.arange(3).contiguous() + bv = b.pad(((0, 2),))[-2:] + # this becomes a late a*0 + late_mul = a*bv + check_schedule(late_mul, 0) + # the arange doesn't realize + self.assertIsNone(b.uop.base.realized) + # mul doesn't realize + self.assertIsNone(late_mul.uop.base.realized) + self.assertEqual(late_mul.tolist(), [0, 0]) + + # SINK has two branches: + # a*VIEW(x), where VIEW(x) = 0 + # x+2 + # as long as one child realizes, x does not collapse + def test_parent_multiple_children_no_collapse(self): + a = Tensor([1, 2]) + b = Tensor.arange(3).contiguous() + bv = b.pad(((0, 2),))[-2:] + late_mul = a*bv + other_child = b+2 + s = check_schedule([late_mul, other_child], 2) + # the arange becomes a BUFFER + self.assertIs(b.uop.base.op, Ops.BUFFER) + # mul still collapses + self.assertIs(late_mul.uop.base.op, Ops.CONST) + run_schedule(s) + self.assertEqual(other_child.tolist(), [2, 3, 4]) + +def tensor_rewrite(t) -> UOp: return graph_rewrite(t.uop.base, merge_views+symbolic_simple) +class TestSimplifier(unittest.TestCase): + def test_sink_childless_const(self): + x = Tensor(0) + check_schedule(x, 0) + + def test_sink_childless_const_alt_expanded(self): + x = Tensor.zeros(4, 4).contiguous() + check_schedule(x, 1) + + def test_all_const_uops(self): + a = Tensor(4)*Tensor(2) + sink = tensor_rewrite(a) + assert UPat.cvar().match(sink, {}) + + def test_masked_const_elementwise(self): + a = Tensor.eye(10)@Tensor.eye(10) + sink = tensor_rewrite(a) + assert UPat(Ops.REDUCE_AXIS, src=(UPat.cvar().view()*UPat.cvar().view(),)).match(sink, {}) + + def test_elementwise_ops(self): + a = Tensor.empty(4, 4, dtype=dtypes.int) + sink = tensor_rewrite(a*0) + assert UPat(Ops.CONST, arg=0).match(sink, {}) + self.assertIs(tensor_rewrite(a*1).base, a.uop.base) + self.assertIs(tensor_rewrite(a+0).base, a.uop.base) + + def test_cast_folding(self): + a = Tensor(1.0).cast(dtypes.int) + sink = tensor_rewrite(a) + assert UPat.cvar(dtype=dtypes.int).match(sink, {}) + + def test_const_folding_mul(self): + a = Tensor([1]) + sink = tensor_rewrite(a*0) + assert UPat(Ops.CONST, arg=0).match(sink, {}), f"expected {sink} to collapse to a const 0" + assert sink.shape == a.shape + + def test_const_folding_ne(self): + a = Tensor([1]) + sink = tensor_rewrite(a != a) + assert UPat(Ops.CONST, arg=False).match(sink, {}), f"expected {sink} to collapse to a const False" + assert sink.shape == a.shape + + def test_const_folding_lt(self): + a = Tensor([1]) + sink = tensor_rewrite(a < a) + assert UPat(Ops.CONST, arg=False).match(sink, {}), f"expected {sink} to collapse to a const False" + assert sink.shape == a.shape + +tensor_const_pm = PatternMatcher([ + (UPat(Ops.CONST, src=(UPat(Ops.VIEW, src=(UPat(Ops.DEVICE),)),)), lambda: True), + (UPat(Ops.BIND, src=(UPat(Ops.DEFINE_VAR, src=(UPat(Ops.VIEW, src=(UPat(Ops.DEVICE),)))), UPat(Ops.CONST))), lambda: True), +]) +class TestConst(unittest.TestCase): + # ** part 1: basic functionality of a tensor directly created from CONST + + def test_tensor_const(self): + a = Tensor(1) + print(a.uop) + self.assertTrue(tensor_const_pm.rewrite(a.uop)) + + def test_tensor_variable(self): + vv = UOp.variable("a", 0, 10).bind(1) + a = Tensor(vv) + print(a.uop) + self.assertTrue(tensor_const_pm.rewrite(a.uop)) + + def test_const_schedule(self): + a = Tensor.ones((4, 4)) + sched = a.schedule() + self.assertEqual(len(sched), 0) + + def test_const_contiguous_schedule(self): + # this ends up in the big graph + a = Tensor.ones((4,)).contiguous() + sched = a.schedule() + self.assertEqual(len(sched), 1) + + def test_const_ast(self): + a = Tensor.ones((4,)).pad((1, 1)).contiguous() + sched = a.schedule() + print(sched[0].ast) + const_ast_pattern = UPat(Ops.SINK, src=(UPat.store(UPat(), UPat.where(UPat(Ops.VALID), UPat.cvar("x"), UPat(Ops.CONST, arg=0))),)) + self.assertEqual(len(const_ast_pattern.match(sched[0].ast, {})), 1) + run_schedule(sched) + self.assertListEqual(a.tolist(), [0, 1, 1, 1, 1, 0]) + + def test_unmasked_const_ast(self): + a = Tensor.ones((4,)).contiguous() + sched = a.schedule() + print(sched[0].ast) + const_ast_pattern = UPat(Ops.SINK, src=(UPat.store(UPat(), UPat(Ops.CONST)),)) + self.assertEqual(len(const_ast_pattern.match(sched[0].ast, {})), 1) + run_schedule(sched) + self.assertListEqual(a.tolist(), [1, 1, 1, 1]) + + # ** part 2: scheduler behavior when const folding happens later + + def test_const_folding_no_realize(self): + a = Tensor([1, 2, 3, 4])*0 + sched = a.schedule() + self.assertEqual(len(sched), 0) + + def test_src_const_folding(self): + with Context(TRACK_MATCH_STATS=0): + a = Tensor.full((4,), 1).contiguous().realize() + b = Tensor.full((4,), 2).contiguous().realize() + mul0 = a*0 + add = b+mul0 + sched = add.schedule() + self.assertEqual(len(sched), 0) + # b+0 and b share the same underlying device memory + self.assertIs(add.uop.buffer, b.uop.buffer) + self.assertListEqual(add.tolist(), [2, 2, 2, 2]) + + def test_src_masked_const_folding(self): + with Context(TRACK_MATCH_STATS=0): + a = Tensor.full((4,), 1).contiguous().realize() + b = Tensor.full((6,), 2).contiguous().realize() + mul0 = a*0 + add = b+mul0.pad((1, 1), value=2) + sched = add.schedule() + self.assertEqual(len(sched), 1) + run_schedule(sched) + # add gets assigned to a new buffer + self.assertIsNot(add.uop.base.realized, b.uop.base.realized) + self.assertListEqual(add.tolist(), [4, 2, 2, 2, 2, 4]) + + # ** part 3: Tensor variable bindings + + #@unittest.expectedFailure # TODO: should schedule assert if you try to realize a Variable? + def test_var_schedule(self): + vv = UOp.variable("a", 0, 10).bind(1) + a = Tensor(vv) + sched = a.schedule() + self.assertEqual(len(sched), 0) + + def test_add_tvar(self): + vv = UOp.variable("a", 0, 10).bind(1) + a = Tensor(vv)+2 + sched, var_vals = a.schedule_with_vars() + self.assertEqual(len(sched), 1) + run_schedule(sched, var_vals) + self.assertEqual(a.tolist(), 3) + +@unittest.skipIf(Device.DEFAULT == "CPU", "tests copy from another device to cpu") +class TestCopyFolding(unittest.TestCase): + def test_const_copy_is_free(self): + b = Tensor(1).to("CPU") + check_schedule(b, 0, filter_sink=False) + assert b.item() == 1 + + def test_late_const_copy_folding(self): + a = Tensor.arange(3).realize() + zeros = Tensor.zeros(3).realize() + b = (a*zeros).to("CPU") + run_schedule(check_schedule(b, 0, filter_sink=False)) + self.assertListEqual(b.tolist(), [0, 0, 0]) + + def test_alu_after_copy(self): + a = Tensor.ones((4,)).to("CPU") + b = Tensor.empty(4, device="CPU") + add = a+b + add.kernelize() + assert all_same([x.device for x in add.uop.src]), f"ALU has different devices! {[x.device for x in add.src]}" + + def test_copy_to_same_device(self): + a = Tensor.empty(4).uop + b = a.copy_to_device(a.device) + check_schedule(b, 0, filter_sink=False) + b = schedule_graph_rewrite(b) + # NOTE: Tensor.empty(4) always creates a VIEW(BUFFER) with ShapeTracker((4,)), we simplify this to jsut a BUFFER + # in the scheduler because buffer already has shape (4,) + self.assertIs(b, a.base) + + def test_copy_to_same_device_alt(self): + a = Tensor.empty(4, 4).uop + b = a.copy_to_device(a.device) + check_schedule(b, 0, filter_sink=False) + b = schedule_graph_rewrite(b) + self.assertIs(b.base, a.base) + + def test_clone(self): + a = Tensor.empty(4) + check_schedule(a.clone(), 1, filter_sink=False) + + # NOTE: moving copy before view might change this + def test_shrink_copy(self): + a = Tensor.arange(4) + view = a.shrink(((0, 2),)) + b = view.clone() + # NOTE: this was sort of a bug making this 2 + run_schedule(check_schedule(b, 2, filter_sink=False)) + self.assertEqual(b.uop.base.buffer.size, 2) + self.assertEqual(b.uop.size, 2) + self.assertListEqual(b.tolist(), [0, 1]) + + def test_expanded_copy(self): + a = Tensor.arange(2) + view = a.reshape(2, 1).expand(2, 2) + b = view.clone() + run_schedule(check_schedule(b, 2, filter_sink=False)) + self.assertEqual(b.uop.base.buffer.size, 4) + self.assertEqual(b.uop.size, 4) + self.assertListEqual(b.tolist(), [[0, 0], [1, 1]]) + + def test_permuted_copy(self): + a = Tensor.arange(4) + b = a.reshape(2, 2).permute(1, 0) + b.realize() + self.assertListEqual(b.tolist(), [[0, 2], [1, 3]]) + + def test_permute_on_disk(self): + with open(temp('dt_arange_4_permute'), "wb") as f: f.write(Tensor.arange(4).realize().uop.base.buffer.as_buffer()) + a = Tensor.empty(4, dtype=dtypes.int32, device=f"disk:{temp('dt_arange_4_permute')}") + b = a.reshape(2, 2).permute(1, 0).to("CPU") + b.realize() + self.assertListEqual(b.tolist(), [[0, 2], [1, 3]]) + + def test_permute_after_shrink(self): + a = Tensor.arange(5) + b = a.shrink(((0, 4),)).reshape(2, 2).permute(1, 0).to("CPU") + b.realize() + self.assertListEqual(b.tolist(), [[0, 2], [1, 3]]) + + # NOTE: disk permute must come after COPY + # TODO: this is wrong because of the permute + @unittest.expectedFailure + def test_permute_after_shrink_on_disk(self): + with open(temp('dt_arange_5_permute'), "wb") as f: f.write(Tensor.arange(5).realize().uop.base.buffer.as_buffer()) + a = Tensor.empty(5, dtype=dtypes.int32, device=f"disk:{temp('dt_arange_5_permute')}") + b = a.shrink(((0, 4),)).reshape(2, 2).permute(1, 0).to("CPU") + b.realize() + self.assertListEqual(b.tolist(), [[0, 2], [1, 3]]) + +class TestBufferUOp(unittest.TestCase): + # BUFFER has a ShapeTracker of shape=(n,) and stride=(1,) + def test_buffer_has_buffer(self): + buf = Tensor.empty(10) + self.assertIsNotNone(buf.uop.buffer) + self.assertEqual(buf.uop.st, ShapeTracker.from_shape((10,))) + # the device Buffer remains unallocated until it's we run the schedule + self.assertFalse(buf.uop.buffer.is_allocated()) + add = buf+1 + sched = add.schedule() + self.assertFalse(buf.uop.buffer.is_allocated()) + run_schedule(sched) + self.assertTrue(buf.uop.buffer.is_allocated()) + + def test_buffer_has_unique_buffer(self): + buf = Tensor.empty(10) + buf1 = buf.uop.buffer + buf2 = buf.uop.buffer + self.assertIs(buf1, buf2) + + # we also allow VIEW(BUFFER) to access the underlying device Buffer, as long as it's contiguous + def test_buffer_view_allowed(self): + add = Tensor.empty(1, 1)+Tensor.empty(1, 1) + add.realize() + self.assertIsNotNone(add.uop.buffer) + self.assertEqual(add.uop.shape, (1, 1)) + + def test_buffer_view_not_allowed(self): + permuted_view = Tensor.empty(1, 2, 3).permute(0, 2, 1) + merged = graph_rewrite(permuted_view.uop, merge_views) + with self.assertRaisesRegex(AssertionError, "VIEW only works here if it's contiguous"): + merged.buffer # cannot access Buffer of a non contiguous VIEW + + def test_buffer_only_after_realize(self): + a = Tensor([1])+Tensor([2]) + # accessing realized will return None + self.assertIsNone(a.uop.realized) + # accessing Buffer will assert + with self.assertRaisesRegex(AssertionError, "must be BUFFER"): + a.uop.buffer # there is no BUFFER on an unrealized ADD + # Buffer only exists once we realize it + a.realize() + self.assertIsNotNone(a.uop.buffer) + + def test_const_does_not_realize(self): + a = Tensor(1)+Tensor(2) + run_schedule(check_schedule(a, 0)) + self.assertIsNone(a.uop.base.realized) + + def test_var_does_not_realize(self): + a = Tensor(UOp.variable("a", 0, 10).bind(1)) + run_schedule(check_schedule(a, 0)) + self.assertIsNone(a.uop.base.realized) + + def test_view_does_not_realize(self): + a = Tensor.randn(1, 4).expand(4, 4) + a.realize() + self.assertEqual(a.uop.base.realized.size, 4) + a2 = a.contiguous().realize() + self.assertEqual(a2.uop.base.realized.size, 16) + +class TestContiguous(unittest.TestCase): + def test_contiguous_buffer(self): + a = Tensor.empty(4) + b = a.contiguous() + check_schedule(b, 0) + + def test_contiguous_buffer_view(self): + a = Tensor.empty(4) + b = a.reshape((2, 2)).contiguous() + check_schedule(b, 0) + + def test_non_contiguous_buffer_view(self): + a = Tensor.empty(4, 1) + b = a.expand((4, 4)).contiguous() + check_schedule(b, 1) + + def test_size_change_buffer_view(self): + a = Tensor.empty(4) + b = a.reshape((1, 1, 4)).shrink(((0, 1), (0, 1), (0, 3))).contiguous() + check_schedule(b, 1) + + def test_double_contiguous_realizes_once(self): + a = Tensor.empty(4, 1) + b = a.expand((4, 4)).contiguous().contiguous() + check_schedule(b, 1) + + def test_view_does_not_realize(self): + a = Tensor.empty(4) + b = a.expand((4, 4)) + check_schedule(b, 0) + self.assertEqual(b.uop.base.buffer.size, 4) + + def test_contiguous_view_realizes(self): + a = Tensor.empty(4) + b = a.expand((4, 4)).contiguous() + check_schedule(b, 1) + self.assertEqual(b.uop.base.buffer.size, 16) + +class TestUOpBecome(unittest.TestCase): + # the simplest case, if we create a new BUFFER for this tensor UOp + def test_new_buffer(self): + a = Tensor.empty(4, 4) + b = Tensor.empty(4, 4) + add = a+b + check_schedule(add, 1) + # NOTE: realized base is always a flat buffer + assert UPat(Ops.BUFFER).match(add.uop.base, {}) + # the Tensor UOp can optionally stack a VIEW on top of the BUFFER, in this case to preserve the (4, 4) shape of the tensor + assert add.uop is not add.uop.base + self.assertEqual(add.uop.size, 16) + self.assertEqual(add.uop.shape, (4, 4)) + + def test_new_buffer_view(self): + a = Tensor.empty(4, 4) + b = Tensor.empty(4, 4) + add = (a+b).reshape(8, 2) + check_schedule(add, 1) + assert UPat(Ops.BUFFER).match(add.uop.base, {}) + # the shape is preserverd in the becomes_map. + self.assertEqual(add.uop.shape, (8, 2)) + assert add.uop is not add.uop.base + + def test_new_flat_buffer(self): + a = Tensor.empty(4,) + b = Tensor.empty(4,) + add = a+b + check_schedule(add, 1) + # BUFFER already has a shape (4,), this tensor just becomes a contiguous BUFFER + assert UPat(Ops.BUFFER).match(add.uop, {}) + + # sometimes we prefer to perform an op before movement ops, in this case we should stack the mops on top of the new buffer + + # NOTE: this expand is not reordered because there's before it to fuse + def test_reorder_expand(self): + a = Tensor.empty(4, 1) + b = a.expand(4, 4).reciprocal() + check_schedule(b, 1) + self.assertEqual(b.uop.base.buffer.size, 16) + self.assertEqual(b.uop.st, ShapeTracker.from_shape((4, 4))) + + def test_reorder_expand_alt(self): + x = Tensor.empty(4, 1) + y = Tensor.empty(4, 1) + img = Tensor.empty(4, 4) + z = (img*x) / y + check_schedule(z, 1) + + def test_become_existing_buffer(self): + a = Tensor.empty(4, 4) + b = a*1 + assert UPat(Ops.MUL).match(b.uop, {}) # before scheduling it's a mul + check_schedule(b, 0) + assert UPat(Ops.VIEW, src=(UPat(Ops.BUFFER))).match(b.uop, {}) # scheduling merges all MovementOps into a single VIEW + self.assertIs(a.uop.base.buffer, b.uop.base.buffer) + + def test_become_buf_with_mops(self): + a = Tensor.empty(2, 4, 2) + noop = a.shrink(((1, 2), (0, 4), (0, 2))).reshape(4, 2)*1+0 + # before realizing, this tensor is base + assert noop.uop is noop.uop.base + noop.realize() + # it becomes a realized view after realize + assert noop.uop is not noop.uop.base + assert noop.uop.base.op is Ops.BUFFER + late_add = noop+2 + late_add.realize() + + def test_become_const_in_base(self): + a = Tensor.empty(4) + b = a*0 + assert UPat(Ops.MUL).match(b.uop, {}) # before scheduling it's a mul + check_schedule(b, 0) + assert UPat(Ops.CONST, arg=0).match(b.uop.base, {}) # scheduling replaces the tensor uop with a VIEW(BUFFER) + + def test_become_const_in_view(self): + # if we shrink the base down to a size 0, only the VIEW becomes CONST, base is unchanged. + add = Tensor.empty(2, 2)+Tensor.empty(2, 2) + b = add.shrink(((0, 1), (0, 0))) + check_schedule(b, 0) + assert UPat(Ops.CONST, arg=0).match(b.uop, {}) + self.assertEqual(b.shape, (1, 0)) + # the base is untouched. + assert UPat(Ops.ADD).match(add.uop, {}) + + def test_become_const_from_const(self): + const_add = Tensor(1)+Tensor(2) + assert UPat(Ops.ADD).match(const_add.uop, {}) + check_schedule(const_add, 0) + assert UPat(Ops.CONST, arg=3).match(const_add.uop.base, {}) + + # tensors can become another realized tensor source + def test_become_existing_buf_simple(self): + a = Tensor.empty(4, 4) + b = a+0 + check_schedule(b, 0) + assert b.uop.base.op is Ops.BUFFER + self.assertIs(a.uop, b.uop) + + # they can also chain other movement ops on top of the tensor source + def test_become_existing_buf_view(self): + a = Tensor.empty(4, 4) + b = a.permute((1, 0))+0 + check_schedule(b, 0) + self.assertEqual(b.uop.st, a.uop.permute((1, 0)).st) + + def test_become_existing_buf_view_alt(self): + a = Tensor.empty(4, 4) + b = a.permute((1, 0)).reshape((8, 2))+0 + check_schedule(b, 0) + self.assertEqual(b.uop.st, a.uop.permute((1, 0)).reshape((8, 2)).st) + + # they can also have other base parents that simplified, in that case we just backtrack to the chained mops + def test_become_existing_buf_complex(self): + a = Tensor.empty(4, 4) + b = (a.permute((1, 0))+0).reshape((8, 2))+0 + check_schedule(b, 0) + self.assertEqual(b.uop.st, a.uop.permute((1, 0)).reshape((8, 2)).st) + assert b.uop.base.op is Ops.BUFFER + + def test_become_multiple_choices(self): + a = Tensor.empty(16) + b = (a.reshape(1, 1, 4, 1, 4)+0).reshape(1, 1, 4, 4).shrink(((0, 1), (0, 1), (0, 3), (0, 3)))+0 + c = (a.reshape(1, 1, 4, 4)+0).shrink(((0, 1), (0, 1), (0, 3), (0, 3)))+0 + check_schedule([b, c], 0) + assert all_same([x.uop.base.realized for x in [a,b,c]]) + # these movement ops result in the same ShapeTracker + assert b.uop.st == c.uop.st + assert b.uop is c.uop + assert UPat(Ops.VIEW, src=(UPat(Ops.BUFFER),)).match(c.uop, {}) + + def test_setitem_becomes_subbuffer(self): + a = Tensor.full((4,), 2.).contiguous().realize() + b = a.shrink(((0, 2),)).assign(Tensor.full((2,), 1.0)) + b.realize() + assert a.uop.is_realized + assert a.uop.buffer._base is None + # b is a subbuffer of a + assert b.uop.op is Ops.BUFFER_VIEW + assert b.uop.src[0] is a.uop + + def test_setitem_offset(self): + a = Tensor.full((16,), 0.).contiguous().realize() + b = Tensor.full((16,), 1.).contiguous().realize() + a_view = a[4:].reshape(3, 4).shrink(((0,2),(0,2))).reshape((4,)) + b.shrink(((0,4),)).assign(a_view).realize() + self.assertListEqual(b.tolist(), [0.0, 0.0, 0.0, 0.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0]) + +if __name__ == '__main__': + unittest.main(verbosity=2) diff --git a/tinygrad_repo/test/test_search.py b/tinygrad_repo/test/test_search.py new file mode 100644 index 000000000..af2c4f0a3 --- /dev/null +++ b/tinygrad_repo/test/test_search.py @@ -0,0 +1,140 @@ +import unittest + +from tinygrad.opt.kernel import Opt, OptOps, Kernel +from tinygrad.uop.ops import UOp, Ops +from tinygrad.opt.search import bufs_from_lin, actions, beam_search +from tinygrad.device import Device +from tinygrad.tensor import Tensor +from tinygrad.dtype import dtypes +from tinygrad.helpers import Context, GlobalCounters +from tinygrad.engine.realize import capturing +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.shape.view import View +from extra.optimization.helpers import time_linearizer + +class TestBEAM(unittest.TestCase): + def test_dynamic_beam(self): + # TODO: make this infra globally usable + class Capture: + def __init__(self): self.captured = [] + def add(self, x): self.captured.append(x) + + capturing.append(Capture()) + kernel_count = GlobalCounters.kernel_count + with Context(BEAM=1): Tensor.zeros(16).contiguous().realize() + assert GlobalCounters.kernel_count == kernel_count + 1 + k_beam_1 = capturing[0].captured + capturing.clear() + + capturing.append(Capture()) + kernel_count = GlobalCounters.kernel_count + with Context(BEAM=0): Tensor.zeros(16).contiguous().realize() + assert GlobalCounters.kernel_count == kernel_count + 1 + k_beam_0 = capturing[0].captured + capturing.clear() + self.assertNotEqual(k_beam_0[-1].prg.p.src, k_beam_1[-1].prg.p.src) + + def test_get_kernel_actions(self): + from test.test_linearizer import helper_realized_ast + a = Tensor.rand(4, 3) + b = Tensor.rand(3) + realized_ast, _ = helper_realized_ast(a @ b) + from tinygrad.opt.search import get_kernel_actions + lins = get_kernel_actions(Kernel(realized_ast), False).values() + + # ensure amt=0 are not duplicated + if Opt(OptOps.UPCAST, 0, 0) in actions: + assert len([x for x in lins if x.applied_opts[0] == Opt(OptOps.UPCAST, axis=0, arg=4)]) == 0, "did not de-dup UPCAST" + if Opt(OptOps.LOCAL, 0, 0) in actions: + assert len([x for x in lins if x.applied_opts[0] == Opt(OptOps.LOCAL, axis=0, arg=4)]) == 0, "did not de-dup LOCAL" + if Opt(OptOps.UNROLL, 0, 0) in actions: + assert len([x for x in lins if x.applied_opts[0] == Opt(OptOps.UNROLL, axis=0, arg=3)]) == 0, "did not de-dup UNROLL" + if Opt(OptOps.GROUP, 0, 0) in actions: + assert len([x for x in lins if x.applied_opts[0] == Opt(OptOps.GROUP, axis=0, arg=3)]) == 0, "did not de-dup GROUP" + if Opt(OptOps.GROUPTOP, 0, 0) in actions: + assert len([x for x in lins if x.applied_opts[0] == Opt(OptOps.GROUPTOP, axis=0, arg=3)]) == 0, "did not de-dup GROUPTOP" + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.tensor_cores, "test requires tensor cores") + def test_search_over_shape(self): + from test.test_linearizer import helper_realized_ast + from tinygrad.opt.search import get_kernel_actions + + dtype_pairs = [(tc.dtype_in, tc.dtype_out) for tc in Device[Device.DEFAULT].renderer.tensor_cores] + multi_shape_dtype_pairs = [dts for dts in dtype_pairs if dtype_pairs.count(dts) > 1] + + if len(multi_shape_dtype_pairs) == 0: raise unittest.SkipTest("only one tc available per dtype pair to search over") + + for (dtype_in, dtype_out) in multi_shape_dtype_pairs: + a = Tensor.rand(16, 16, dtype=dtype_in) + b = Tensor.rand(16, 16, dtype=dtype_in) + realized_ast, _ = helper_realized_ast(a.matmul(b, dtype=dtype_out)) + + lins = get_kernel_actions(Kernel(realized_ast)).values() + assert len(set(lin.tensor_core.dims for lin in lins if lin.tensor_core is not None)) > 1 + + def test_get_kernel_actions_preserves_actions_state(self): + from test.test_linearizer import helper_realized_ast + from tinygrad.opt.search import get_kernel_actions + a = Tensor.rand(16, 16) + b = Tensor.rand(16, 16) + realized_ast, _ = helper_realized_ast(a @ b) + actions_before = actions.copy() + get_kernel_actions(Kernel(realized_ast)) + actions_after = actions.copy() + assert actions_after == actions_before, "actions state was not preserved" + + def test_filter_global_buffer(self): + # taken from https://github.com/tinygrad/tinygrad/issues/4612 + ast = UOp(Ops.SINK, dtypes.void, arg=None, src=( + UOp(Ops.STORE, dtypes.void, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(256), arg=ShapeTracker(views=(View(shape=(1, 1, 256), strides=(0, 0, 1), offset=0, mask=None, contiguous=True),)), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(256), arg=0, src=()),)), + UOp(Ops.REDUCE_AXIS, dtypes.float, arg=(Ops.MAX, (1,)), src=( + UOp(Ops.MUL, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.ADD, dtypes.float, arg=None, src=( + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(64128), arg=ShapeTracker(views=(View(shape=(384768,), strides=(1,), offset=0, mask=((0, 64128),), contiguous=False), View(shape=(1, 501, 256), strides=(0, 1, 501), offset=256512, mask=None, contiguous=False))), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64128), arg=1, src=()),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(64128), arg=ShapeTracker(views=(View(shape=(384768,), strides=(1,), offset=-64128, mask=((64128, 128256),), contiguous=False), View(shape=(1, 501, 256), strides=(0, 1, 501), offset=256512, mask=None, contiguous=False))), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64128), arg=2, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(64128), arg=ShapeTracker(views=(View(shape=(384768,), strides=(1,), offset=-128256, mask=((128256, 192384),), contiguous=False), View(shape=(1, 501, 256), strides=(0, 1, 501), offset=256512, mask=None, contiguous=False))), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64128), arg=3, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(64128), arg=ShapeTracker(views=(View(shape=(384768,), strides=(1,), offset=-192384, mask=((192384, 256512),), contiguous=False), View(shape=(1, 501, 256), strides=(0, 1, 501), offset=256512, mask=None, contiguous=False))), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64128), arg=4, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(64128), arg=ShapeTracker(views=(View(shape=(384768,), strides=(1,), offset=-256512, mask=((256512, 320640),), contiguous=False), View(shape=(1, 501, 256), strides=(0, 1, 501), offset=256512, mask=None, contiguous=False))), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64128), arg=5, src=()),)),)),)), + UOp(Ops.LOAD, dtypes.float, arg=None, src=( + UOp(Ops.VIEW, dtypes.float.ptr(64128), arg=ShapeTracker(views=(View(shape=(384768,), strides=(1,), offset=-320640, mask=((320640, 384768),), contiguous=False), View(shape=(1, 501, 256), strides=(0, 1, 501), offset=256512, mask=None, contiguous=False))), src=( # noqa: E501 + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(64128), arg=6, src=()),)),)),)), + UOp(Ops.CONST, dtypes.float, arg=1.4285714285714286, src=( + UOp(Ops.VIEW, dtypes.void, arg=ShapeTracker(views=(View(shape=(1, 501, 256), strides=(0, 0, 0), offset=0, mask=None, contiguous=False),)), src=()),)),)),)),)),)) # noqa: E501 + lin = Kernel(ast) + + bufs = bufs_from_lin(lin) + best_lin = beam_search(lin, bufs, 2) + assert best_lin + # need disable_cache to trigger. + tm = time_linearizer(best_lin, bufs, allow_test_size=False, cnt=2, disable_cache=True) + assert tm + + def test_beam_unnamed_kernels(self): + a = Tensor.rand(100) + b = Tensor.rand(100) + si = (a+b).schedule()[-1] + lin = Kernel(si.ast) + bufs = bufs_from_lin(lin) + # TODO: beam should have better instrumentation so we don't have to check this indirect thing + kcount = len(Kernel.kernel_cnt) + beam_search(lin, bufs, 3, disable_cache=True) + self.assertEqual(kcount, len(Kernel.kernel_cnt)) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_setitem.py b/tinygrad_repo/test/test_setitem.py new file mode 100644 index 000000000..d6de6e93f --- /dev/null +++ b/tinygrad_repo/test/test_setitem.py @@ -0,0 +1,180 @@ +import unittest +from tinygrad import Tensor, TinyJit, Variable, dtypes +from tinygrad.helpers import Context +import numpy as np + +class TestSetitem(unittest.TestCase): + def test_simple_setitem(self): + cases = ( + ((6,6), (slice(2,4), slice(3,5)), Tensor.ones(2,2)), + ((6,6), (slice(2,4), slice(3,5)), Tensor([1.,2.])), + ((6,6), (slice(2,4), slice(3,5)), 1.0), + ((6,6), (3, 4), 1.0), + ((6,6), (3, None, 4, None), 1.0), + ((4,4,4,4), (Ellipsis, slice(1,3), slice(None)), Tensor(4)), + ((4,4,4,4), (Ellipsis, slice(1,3)), 4), + ((4,4,4,4), (2, slice(1,3), None, 1), 4), + ((4,4,4,4), (slice(1,3), slice(None), slice(0,4,2)), 4), + ((4,4,4,4), (slice(1,3), slice(None), slice(None), slice(0,3)), 4), + ((6,6), (slice(1,5,2), slice(0,5,3)), 1.0), + ((6,6), (slice(5,1,-2), slice(5,0,-3)), 1.0), + ) + for shp, slc, val in cases: + t = Tensor.zeros(shp).contiguous() + t[slc] = val + n = np.zeros(shp) + n[slc] = val.numpy() if isinstance(val, Tensor) else val + np.testing.assert_allclose(t.numpy(), n) + + def test_padded_setitem(self): + t = Tensor.arange(10) + t[4:1:-2] = 11 + self.assertListEqual(t.tolist(), [0, 1, 11, 3, 11, 5, 6, 7, 8, 9]) + + def test_setitem_inplace_mul(self): + t = Tensor.arange(10).realize() + t[:3] *= 10 + self.assertListEqual(t.tolist(), [0, 10, 20, 3, 4, 5, 6, 7, 8, 9]) + + def test_setitem_into_unrealized(self): + t = Tensor.arange(4).reshape(2, 2) + t[1] = 5 + np.testing.assert_allclose(t.numpy(), [[0, 1], [5, 5]]) + + def test_setitem_dtype(self): + for dt in (dtypes.int, dtypes.float, dtypes.bool): + for v in (5., 5, True): + t = Tensor.ones(6,6, dtype=dt).contiguous() + t[1] = v + self.assertEqual(t.dtype, dt) + + def test_setitem_into_noncontiguous(self): + t = Tensor.ones(4) + self.assertFalse(t.uop.st.contiguous) + with self.assertRaises(RuntimeError): t[1] = 5 + + @unittest.skip("TODO: flaky") + def test_setitem_inplace_operator(self): + t = Tensor.arange(4).reshape(2, 2).contiguous() + t[1] += 2 + np.testing.assert_allclose(t.numpy(), [[0, 1], [4, 5]]) + + t = Tensor.arange(4).reshape(2, 2).contiguous() + t[1] -= 1 + np.testing.assert_allclose(t.numpy(), [[0, 1], [1, 2]]) + + t = Tensor.arange(4).reshape(2, 2).contiguous() + t[1] *= 2 + np.testing.assert_allclose(t.numpy(), [[0, 1], [4, 6]]) + + # NOTE: have to manually cast setitem target to least_upper_float for div + t = Tensor.arange(4, dtype=dtypes.float).reshape(2, 2).contiguous() + t[1] /= 2 + np.testing.assert_allclose(t.numpy(), [[0, 1], [1, 1.5]]) + + t = Tensor.arange(4).reshape(2, 2).contiguous() + t[1] **= 2 + np.testing.assert_allclose(t.numpy(), [[0, 1], [4, 9]]) + + t = Tensor.arange(4).reshape(2, 2).contiguous() + t[1] ^= 5 + np.testing.assert_allclose(t.numpy(), [[0, 1], [7, 6]]) + + #@unittest.expectedFailure + # update: passing after delete_forced_realize + def test_setitem_consecutive_inplace_operator(self): + t = Tensor.arange(4).reshape(2, 2).contiguous() + t[1] += 2 + t = t.contiguous() + # TODO: RuntimeError: can't double realize in one schedule + t[1] -= 1 + np.testing.assert_allclose(t.numpy(), [[0, 1], [3, 4]]) + + def test_setitem_overlapping_indices(self): + t = Tensor([1,2,3,4]) + # regular overlapping indices + t[[1,1]] = Tensor([5,6]) + np.testing.assert_allclose(t.numpy(), [1,6,3,4]) + + # overlapping indices with zero value overlapped + t[[1,1]] = Tensor([0,1]) + np.testing.assert_allclose(t.numpy(), [1,1,3,4]) + + def test_setitem_overlapping_indices_with_0(self): + t = Tensor([1,2,3,4]) + t[[1,1]] = Tensor([1,0]) + np.testing.assert_allclose(t.numpy(), [1,0,3,4]) + + def test_setitem_with_1_in_shape(self): + t = Tensor([[1],[2],[3]]) + t[[0,0]] = Tensor([[1],[2]]) + np.testing.assert_allclose(t.numpy(), [[2],[2],[3]]) + + def test_fancy_setitem(self): + t = Tensor.zeros(6,6).contiguous() + t[[1,2], [3,2]] = 3 + n = np.zeros((6,6)) + n[[1,2], [3,2]] = 3 + np.testing.assert_allclose(t.numpy(), n) + + def test_simple_jit_setitem(self): + @TinyJit + def f(t:Tensor, a:Tensor): + t[2:4, 3:5] = a + + for i in range(1, 6): + t = Tensor.zeros(6, 6).contiguous().realize() + a = Tensor.full((2, 2), fill_value=i, dtype=dtypes.float).contiguous() + f(t, a) + + n = np.zeros((6, 6)) + n[2:4, 3:5] = np.full((2, 2), i) + np.testing.assert_allclose(t.numpy(), n) + + def test_jit_setitem_variable_offset(self): + with Context(IGNORE_OOB=1): + @TinyJit + def f(t:Tensor, a:Tensor, v:Variable): + t.shrink(((v,v+1), None)).assign(a).realize() + + t = Tensor.zeros(6, 6).contiguous().realize() + n = np.zeros((6, 6)) + + for i in range(6): + v = Variable("v", 0, 6).bind(i) + a = Tensor.full((1, 6), fill_value=i+1, dtype=dtypes.float).contiguous() + n[i, :] = i+1 + f(t, a, v) + np.testing.assert_allclose(t.numpy(), n) + np.testing.assert_allclose(t.numpy(), [[1,1,1,1,1,1],[2,2,2,2,2,2],[3,3,3,3,3,3],[4,4,4,4,4,4],[5,5,5,5,5,5],[6,6,6,6,6,6]]) + + def test_setitem_overlapping_inplace1(self): + t = Tensor([[3.0], [2.0], [1.0]]).contiguous() + t[1:] = t[:-1] + self.assertEqual(t.tolist(), [[3.0], [3.0], [2.0]]) + + def test_setitem_overlapping_inplace2(self): + t = Tensor([[3.0], [2.0], [1.0]]).contiguous() + t[:-1] = t[1:] + self.assertEqual(t.tolist(), [[2.0], [1.0], [1.0]]) + +class TestWithGrad(unittest.TestCase): + def test_no_requires_grad_works(self): + z = Tensor.rand(8, 8) + x = Tensor.rand(8) + z[:3] = x + + def test_set_into_requires_grad(self): + z = Tensor.rand(8, 8, requires_grad=True) + x = Tensor.rand(8) + with self.assertRaises(NotImplementedError): + z[:3] = x + + def test_set_with_requires_grad(self): + z = Tensor.rand(8, 8) + x = Tensor.rand(8, requires_grad=True) + with self.assertRaises(NotImplementedError): + z[:3] = x + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_softmax_fusion.py b/tinygrad_repo/test/test_softmax_fusion.py new file mode 100644 index 000000000..23e1a4b77 --- /dev/null +++ b/tinygrad_repo/test/test_softmax_fusion.py @@ -0,0 +1,177 @@ +import unittest +import numpy as np +from tinygrad import Tensor, GlobalCounters, Context, Device +from tinygrad.dtype import DTypeLike, dtypes +from tinygrad.helpers import DEBUG, get_single_element +from tinygrad.engine.realize import lower_schedule_item +from tinygrad.device import is_dtype_supported + +def single_kernel_softmax(x_in:Tensor, axis=-1, dtype:DTypeLike|None=None) -> Tensor: + # only support axis =-1 + x = x_in.reshape(-1, x_in.shape[-1]) + nr_dim, r_dim = x.shape + + inp = x.reshape(nr_dim, 1, 1, r_dim).expand(nr_dim, r_dim, 1, r_dim) + imx = x.reshape(nr_dim, 1, r_dim, 1).expand(nr_dim, r_dim, r_dim, r_dim).max(axis=-2, keepdim=True) + m = inp - imx.detach() + if dtype is not None: m = m.cast(dtype) + e = m.exp() + ss = e.sum(axis=-1, keepdim=True) + + inp = x.reshape(nr_dim, r_dim, 1, 1) + imx = x.reshape(nr_dim, 1, r_dim, 1).expand(nr_dim, r_dim, r_dim, 1).max(axis=-2, keepdim=True) + m = inp - imx.detach() + if dtype is not None: m = m.cast(dtype) + e = m.exp() + + out = e.div(ss).reshape(x_in.shape) + return out + +def run_one_schedule_item(out): lower_schedule_item(get_single_element(out.schedule())).run() + +class TestFuse(unittest.TestCase): + def _test_fuse(self, fxn, *args, atol=1e-7, allow_multiple=False, **kwargs): + GlobalCounters.reset() + out_single = fxn(*args, **kwargs).fuse() + if not allow_multiple: run_one_schedule_item(out_single) + np_single = out_single.numpy() + GlobalCounters.reset() + np_multi = fxn(*args, **kwargs).numpy() + np.testing.assert_allclose(np_single, np_multi, atol=atol) + + def test_fuse_norm(self): + a = Tensor.rand(50,50).realize() + self._test_fuse(lambda a: a / a.mean(axis=1), a) + + def test_fuse_argmax(self): + a = Tensor.rand(50,50).realize() + self._test_fuse(lambda a: a.argmax(axis=-1), a) + + def test_fuse_softmax(self): + a = Tensor.rand(50,50).realize() + self._test_fuse(lambda a: a.softmax(axis=-1), a) + + def test_fuse_gemm_softmax(self): + a = Tensor.rand(50,50).realize() + b = Tensor.rand(50,50).realize() + self._test_fuse(lambda a,b: ((a@b).relu()+a).contiguous().softmax(axis=-1), a,b, allow_multiple=True) + + @unittest.skipUnless(is_dtype_supported(dtypes.float16, Device.DEFAULT), f"no float16 on {Device.DEFAULT}") + def test_fuse_softmax_dtype(self): + a = Tensor.rand(50,50).realize() + self._test_fuse(lambda a: a.softmax(axis=-1, dtype='half'), a, atol=3e-4) + + def test_fuse_arange_eye(self): + self._test_fuse(lambda: Tensor.arange(10).reshape(10,1).expand(10,10) == Tensor.arange(10).reshape(1,10).expand(10,10)) + + def test_double_gemm(self): + N = 32 + with Context(TRACK_MATCH_STATS=0, DEBUG=0): + a = (Tensor.rand(N,N)-0.5).realize() + b = (Tensor.rand(N,N)-0.5).realize() + c = (Tensor.rand(N,N)-0.5).realize() + self._test_fuse(lambda a,b,c: a@b@c, a, b, c, atol=1e-5) + + def test_embedding(self): + with Context(TRACK_MATCH_STATS=0, DEBUG=0): + vocab_sz = 123 + embed_sz = 16 + weight = (Tensor.rand(vocab_sz, embed_sz)-0.5).realize() + a = Tensor([1, 1, 2, 3]).realize() + def embedding(idx:Tensor): + arange = Tensor.arange(vocab_sz).unsqueeze(-1) + big_shp = idx.shape + (vocab_sz, embed_sz) + arange, vals = arange.expand(big_shp), weight.expand(big_shp) + idx = idx.reshape(idx.shape+(1, 1)).expand(big_shp) + return (arange == idx).mul(vals).sum(-2, dtype=vals.dtype) + self._test_fuse(embedding, a, atol=1e-5) + + @unittest.skip("still broken") + def test_flash_attention(self): + BS = 4 + HEADS = 2 + MATDIM = 16 + EMB = 8 + with Context(TRACK_MATCH_STATS=0, DEBUG=0): + q = Tensor.randn(BS, HEADS, MATDIM, EMB).realize() + k = Tensor.randn(BS, HEADS, MATDIM, EMB).realize() + v = Tensor.randn(BS, HEADS, MATDIM, EMB).realize() + # TODO: OPT is breaking things. NOOPT isn't linearizing + with Context(NOOPT=1): + self._test_fuse(Tensor.scaled_dot_product_attention, q, k, v) + +class TestSoftmaxFusion(unittest.TestCase): + @classmethod + def setUpClass(cls): + with Context(TRACK_MATCH_STATS=0): cls.test = Tensor.rand(32, 10).contiguous().realize() + + def setUp(self): + GlobalCounters.reset() + + def test_norm(self): + print("*** norm ***") + with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2)): + # NOTE: there's an implied expand on the mean here + sout = self.test / self.test.mean(-1, keepdim=True) + sout.realize() + + print("*** single kernel norm ***") + with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2)): + inp = self.test.reshape(32, 10, 1) + div = self.test.reshape(32, 1, 10).expand(32, 10, 10).mean(axis=-1, keepdim=True) + out = (inp / div).reshape(32, 10) + out.realize() + + np.testing.assert_allclose(sout.numpy(), out.numpy()) + + def test_softmax(self): + # this is the softmax from scaled_dot_product_attention + # it becomes 3 kernels + print("*** softmax ***") + with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2)): + sout = self.test.softmax(-1) + sout.realize() + + print("*** single kernel softmax ***") + # NOTE: DONT_GROUP_REDUCES is required here + with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2), DONT_GROUP_REDUCES=1): + out = single_kernel_softmax(self.test) + out.realize() + + np.testing.assert_allclose(sout.numpy(), out.numpy()) + + def test_auto_softmax(self): + print("*** softmax ***") + with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2)): + sout = self.test.softmax(-1) + sout.realize() + + print("*** auto single kernel softmax ***") + with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2)): + out = self.test.contiguous().softmax(-1).fuse() + run_one_schedule_item(out) + + np.testing.assert_allclose(sout.numpy(), out.numpy()) + + @unittest.skip("recursion error no longer raised") + def test_softmax_bw(self): + print("*** softmax bw ***") + self.test.requires_grad_() + with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2)): + self.test.softmax(-1).sum().backward() + sg = self.test.grad.realize() + + self.test.grad = None + + print("*** single kernel softmax bw ***") + # NOTE: DONT_GROUP_REDUCES is required here + # TODO: fix RecursionError with DONT_GROUP_REDUCES + with self.assertRaises(RecursionError): + with Context(NOOPT=1, DEBUG=max(DEBUG.value, 2), DONT_GROUP_REDUCES=1): + single_kernel_softmax(self.test).sum().backward() + g = self.test.grad.realize() + + np.testing.assert_allclose(sg.numpy(), g.numpy(), atol=1e-7) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_specific_conv.py b/tinygrad_repo/test/test_specific_conv.py new file mode 100644 index 000000000..ed6492b5d --- /dev/null +++ b/tinygrad_repo/test/test_specific_conv.py @@ -0,0 +1,55 @@ +import unittest +from tinygrad.helpers import CI +from tinygrad import Tensor, Device, dtypes +from tinygrad.device import is_dtype_supported +# similar to test/external/external_test_gpu_ast.py, but universal + +@unittest.skipIf(Device.DEFAULT in {"CUDA", "NV"} and CI, "slow on CUDA CI") +class TestSpecific(unittest.TestCase): + # from openpilot + + # 1x1 6 <- 24 + def test_1x1_6_24(self): + x = Tensor.randn(1, 24*4, 32, 64) + w = Tensor.randn(6*4, 24*4, 1, 1) + x.conv2d(w).permute(0,2,3,1).reshape(32, 384, 4).contiguous().realize() + + def test_vec_mul(self): + # this forces it to be an image... + x = Tensor.ones(1, 512, 4).contiguous().reshape(1, 2048) + w = Tensor.randn(2048, 512) + (x @ w).reshape(1, 128, 4).contiguous().realize() + + @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need float16 support") + def test_big_vec_mul(self): + # from LLaMA + # 0 buffer<4096, dtypes.float> [View((1024, 1, 1, 4), (4, 0, 0, 1), 0, None)] + # 1 buffer<4096, dtypes.float> [View((1024, 1024, 4, 4), (0, 4, 1, 0), 0, None)] + # 2 buffer<16777216, dtypes.half> [View((1024, 1024, 4, 4), (16384, 4, 1, 4096), 0, None)] + x = Tensor.randn(4096).realize() + w = Tensor.randn(4096, 4096, dtype=dtypes.float16).realize() + (x @ w.T).realize() + + # from https://dl.acm.org/doi/pdf/10.1145/3495243.3517020 + + # ~260 GFLOPS on Adreno 640, should be 260*(720/890)*(596/710) = 176.5 on downclocked 630 + # we get 170 + def test_1x1_28_28(self): + x = Tensor.randn(1, 256, 28, 28) + w = Tensor.randn(256, 256, 1, 1) + x.conv2d(w).permute(0,2,3,1).reshape(28, 28*256//4, 4).contiguous().realize() + + # 132 GFLOPS on Adreno 640, should be 132*(720/890)*(596/710) = 90 on downclocked 630 + # gets 54 with broken opt, 74 without opt, and 146 if we pad and opt 3! + def test_3x3_28_28_stride_2(self): + x = Tensor.randn(1, 288, 36, 36) + w = Tensor.randn(384, 288, 3, 3) + x.conv2d(w, stride=2).permute(0,2,3,1).reshape(17, 17*384//4, 4).contiguous().realize() + + def test_3x3_28_28_stride_2_padded(self): + x = Tensor.randn(1, 288, 36, 36) + w = Tensor.randn(384, 288, 3, 3) + x.conv2d(w, stride=2, padding=1).permute(0,2,3,1).reshape(18, 18*384//4, 4).contiguous().realize() + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_speed_v_torch.py b/tinygrad_repo/test/test_speed_v_torch.py new file mode 100644 index 000000000..b6c728ad1 --- /dev/null +++ b/tinygrad_repo/test/test_speed_v_torch.py @@ -0,0 +1,287 @@ +import os +os.environ["NVIDIA_TF32_OVERRIDE"] = "0" +os.environ["MKL_NUM_THREADS"] = "1" +os.environ["NUMEXPR_NUM_THREADS"] = "1" +os.environ["OMP_NUM_THREADS"] = "1" +os.environ["VECLIB_MAXIMUM_THREADS"] = "1" +import unittest +import torch +torch.set_num_threads(1) +import time +import numpy as np +np.set_printoptions(linewidth=160) +from tinygrad import Tensor, Device, GlobalCounters, TinyJit +from tinygrad.nn import Conv2d +from tinygrad.helpers import colorize_float, getenv, CI + +IN_CHANS = [int(x) for x in getenv("IN_CHANS", "4,16,64").split(",")] + +torch_dt = torch.float16 if getenv("HALF", 0) else torch.float32 +torch_device = torch.device('mps' if getenv("MPS", 0) else ('cuda' if getenv("TORCHCUDA", 0) else 'cpu')) +if str(torch_device) == "mps": + import torch.mps + def sync(): torch.mps.synchronize() +elif str(torch_device) == "cuda": + import torch.cuda + def sync(): torch.cuda.synchronize() +else: + def sync(): pass + +save_ops, save_mem = 0, 0 +CNT = getenv("CNT", 8) +def helper_test_speed(f1, *args): + global save_ops, save_mem + ets = [] + ret = None + cache_defeat = np.zeros((2048,2048)) + for i in range(CNT): + del ret + + # operation cache defeats + args = [(x+1).realize() if isinstance(x, Tensor) else (None if x is None else (x+1)) for x in args] + args = [(x-1).realize() if isinstance(x, Tensor) else (None if x is None else (x-1)) for x in args] + + # force syncing + [x.numpy() if isinstance(x, Tensor) or str(torch_device) == "cpu" else x.cpu().numpy() for x in args if x is not None] + + # clear 32MB global memory cache (CPU and global memory only) + cache_defeat += 1 + + # manual pre sync + if isinstance(args[0], Tensor): + local_device = Device[args[0].device] + local_device.synchronize() + else: sync() + + GlobalCounters.global_ops = 0 + GlobalCounters.global_mem = 0 + st = time.perf_counter() + ret = f1(*args) + if isinstance(ret, Tensor): local_device.synchronize() + else: sync() + et = (time.perf_counter() - st) * 1000 + if i >= 1: ets.append(et) + if GlobalCounters.global_ops: + save_ops, save_mem = GlobalCounters.global_ops, GlobalCounters.global_mem + return ret.numpy() if isinstance(ret, Tensor) else ret.cpu().numpy(), np.min(ets) + +def helper_test_generic_square(name, N, f1, f2, onearg=False): + torch.manual_seed(0) + torch_a = (torch.rand(N, N, dtype=torch_dt) - 0.5).to(torch_device) + torch_b = (torch.rand(N, N, dtype=torch_dt) - 0.5).to(torch_device) if not onearg else None + + tiny_a = Tensor(torch_a.cpu().numpy()) + tiny_b = Tensor(torch_b.cpu().numpy()) if not onearg else None + + helper_test_generic(f"{name:30s} {N:5d}x{N:5d}", f1, (torch_a, torch_b), TinyJit(f2), (tiny_a, tiny_b)) + +def helper_test_matvec(name, N, M): + torch.manual_seed(0) + torch_a = (torch.rand(N, dtype=torch_dt) - 0.5).to(torch_device) + torch_b = (torch.rand(N, M, dtype=torch_dt) - 0.5).to(torch_device) + + tiny_a = Tensor(torch_a.cpu().numpy()) + tiny_b = Tensor(torch_b.cpu().numpy()) + + helper_test_generic(f"{name:30s} {N:5d}x{M:5d}", lambda a,b: a@b, (torch_a, torch_b), TinyJit(lambda a,b:a@b), (tiny_a, tiny_b)) + +prefix = None +def helper_test_generic(name, f1, f1_args, f2, f2_args): + global prefix + with torch.no_grad(): + val_torch, et_torch = helper_test_speed(f1, *f1_args) + val_tinygrad, et_tinygrad = helper_test_speed(f2, *f2_args) + + desc = "faster" if et_torch > et_tinygrad else "slower" + flops = save_ops*1e-6 + mem = save_mem*1e-6 + print(("\r" if not CI else "")+f"{name:42s} {et_torch:7.2f} ms ({flops/et_torch:9.2f} GFLOPS {mem/et_torch:7.2f} GB/s) in torch, {et_tinygrad:7.2f} ms ({flops/et_tinygrad:9.2f} GFLOPS {mem/et_tinygrad:7.2f} GB/s) in tinygrad, {colorize_float(et_tinygrad/et_torch)} {desc} {flops:10.2f} MOPS {mem:8.2f} MB") # noqa: E501 + atol, rtol = (1e-2, 1e-2) if torch_dt == torch.float16 else (1e-3, 1e-3) + np.testing.assert_allclose(val_tinygrad, val_torch, atol=atol, rtol=rtol) + +def helper_test_conv(bs, in_chans, out_chans, kernel_size, img_size_y, img_size_x): + torch.manual_seed(0) + torch_dat = torch.rand(bs, in_chans, img_size_y, img_size_x, dtype=torch_dt).to(torch_device) + torch_conv = torch.nn.Conv2d(in_chans, out_chans, kernel_size, bias=None, dtype=torch_dt).to(torch_device) + + tiny_dat = Tensor(torch_dat.cpu().numpy()) + tiny_conv = Conv2d(in_chans, out_chans, kernel_size, bias=None) + tiny_conv.weight = Tensor(torch_conv.weight.detach().cpu().numpy()) + + def f1(torch_dat): return torch_conv(torch_dat) + def f2(tiny_dat): return tiny_conv(tiny_dat).realize() + helper_test_generic(f"conv bs:{bs:3d} chans:{in_chans:3d} -> {out_chans:3d} k:{kernel_size}", f1, (torch_dat,), TinyJit(f2), (tiny_dat,)) + +@unittest.skipIf(getenv("BIG") == 0, "no big tests") +@unittest.skipIf(getenv("MOCKGPU"), "no MOCKGPUs") +class TestBigSpeed(unittest.TestCase): + def test_add(self): + def f(a, b): return a+b + helper_test_generic_square('add', 8192, f, f) + def test_exp(self): + def f(a, b): return a.exp() + helper_test_generic_square('exp', 8192, f, f, onearg=True) + def test_gemm_2048(self): + def f(a, b): return a @ b + helper_test_generic_square('gemm', 2048, f, f) + def test_gemm_4096(self): + def f(a, b): return a @ b + helper_test_generic_square('gemm', 4096, f, f) + def test_large_conv_1x1(self): helper_test_conv(bs=32, in_chans=128, out_chans=128, kernel_size=1, img_size_y=128, img_size_x=128) + def test_large_conv_3x3(self): helper_test_conv(bs=4, in_chans=128, out_chans=128, kernel_size=3, img_size_y=130, img_size_x=130) + def test_large_conv_5x5(self): helper_test_conv(bs=4, in_chans=128, out_chans=128, kernel_size=5, img_size_y=132, img_size_x=132) + def test_matvec_4096_16384(self): helper_test_matvec('matvec_4096_16384', 4096, 16384) + def test_matvec_16384_4096(self): helper_test_matvec('matvec_16384_4096', 16384, 4096) + +@unittest.skipIf(getenv("BIG") == 1, "only big tests") +@unittest.skipIf(getenv("MOCKGPU"), "no MOCKGPUs") +class TestSpeed(unittest.TestCase): + def test_sub(self): + def f(a, b): return a-b + helper_test_generic_square('sub', 4096, f, f) + + def test_pow(self): + def f(a, b): return a.pow(b) + helper_test_generic_square('pow', 2048, f, f) + + def test_sum(self): + def f(a, b): return a.sum() + helper_test_generic_square('sum', 2048, f, f, onearg=True) + helper_test_generic_square('sum', 4096, f, f, onearg=True) + + def test_partial_sum(self): + R = 256 + def f(a, b): return a.reshape(int(4096//R), int(4096*R)).sum(axis=1) + helper_test_generic_square('partial_sum', 4096, f, f, onearg=True) + + @unittest.skip("not really used in models") + def test_cumsum(self): + def f0(a, b): return a.cumsum(axis=0) + def f1(a, b): return a.cumsum(axis=1) + helper_test_generic_square('cumsum_0', 256, f0, f0, onearg=True) + helper_test_generic_square('cumsum_1', 256, f1, f1, onearg=True) + + def test_cat(self): + helper_test_generic_square('cat_0', 2048, lambda x,y: torch.cat((x,y),dim=0), lambda x,y: x.cat(y,dim=0)) + helper_test_generic_square('cat_1', 2048, lambda x,y: torch.cat((x,y),dim=1), lambda x,y: x.cat(y,dim=1)) + + def test_array_packing(self): + N = 2048 + def f(a, b): return a.reshape(N, N // 32, 32).permute(1,0,2).contiguous() + helper_test_generic_square('array_packing', N, f, f, onearg=True) + + def test_permute(self): + for N in [1024, 4096]: + # this is a 64MB tensor, M1 L1 cache is 128kB + # to fit easily in L1, rotations should be 128x128 chunks. 128x128 is also the AMX size + def f(a, b): return a.permute(1,0).contiguous() + helper_test_generic_square('permute', N, f, f, onearg=True) + + def test_double_permute(self): + N = 64 + torch.manual_seed(0) + torch_a = (torch.rand(N, N, N, N, dtype=torch_dt) - 0.5).to(torch_device) + tiny_a = Tensor(torch_a.cpu().numpy()) + def f(a): return a.permute(1,0,3,2).contiguous() + helper_test_generic(f"double_permute {tiny_a.shape}", f, (torch_a,), TinyJit(lambda a: f(a).realize()), (tiny_a,)) + + def test_neg(self): + def f(a, b): return -a + helper_test_generic_square('neg', 4096, f, f, onearg=True) + + def test_exp(self): + def f(a, b): return a.exp() + helper_test_generic_square('exp', 2048, f, f, onearg=True) + + def test_sqrt(self): + def f(a, b): return a.sqrt() + helper_test_generic_square('sqrt', 2048, f, f, onearg=True) + + def test_relu(self): + def f(a, b): return a.relu() + helper_test_generic_square('relu', 4096, f, f, onearg=True) + + def test_max(self): + def f(a, b): return a.max() + helper_test_generic_square('max', 4096, f, f, onearg=True) + + def test_mul_sum(self): + def f(a, b): return (a*b).sum() + helper_test_generic_square('mul_sum', 4096, f, f) + + def test_add_a(self): + def f(a, b): return a + b + helper_test_generic_square('add', 1, f, f) + + def test_add_big(self): + for N in [1024, 4096]: + def f(a, b): return a + b + helper_test_generic_square('add', N, f, f) + + def test_add_constant(self): + def f(a, b): return a+2.0 + helper_test_generic_square('add_constant', 4096, f, f, onearg=True) + + def test_add_sq(self): + def f(a, b): return a*a + b*b + helper_test_generic_square('add_sq', 4096, f, f) + + def test_gemm(self): + def f(a, b): return a @ b + helper_test_generic_square('gemm', 1024, f, f) + + def test_gemm_small(self): + def f(a, b): return a @ b + helper_test_generic_square('gemm', 256, f, f) + + def test_gemm_unrolled(self): + N = 512 + def f1(a, b): return a@b.T + def f2(a, b): return (a.reshape(N, 1, N).expand(N, N, N) * b.reshape(1, N, N).expand(N, N, N)).sum(axis=2) + helper_test_generic_square('gemm_unrolled', N, f1, f2) + + def test_gemm_unrolled_permute_l(self): + N = 512 + def f1(a, b): return a.T@b.T + def f2(a, b): return (a.permute(1,0).reshape(N, 1, N).expand(N, N, N) * b.reshape(1, N, N).expand(N, N, N)).sum(axis=2) + helper_test_generic_square('gemm_unrolled_permute_l', N, f1, f2) + + def test_gemm_unrolled_permute_r(self): + N = 512 + def f1(a, b): return a@b + def f2(a, b): return (a.reshape(N, 1, N).expand(N, N, N) * b.permute(1,0).reshape(1, N, N).expand(N, N, N)).sum(axis=2) + helper_test_generic_square('gemm_unrolled_permute_r', N, f1, f2) + + def test_gemm_unrolled_permute_lr(self): + N = 512 + def f1(a, b): return a.T@b + def f2(a, b): return (a.permute(1,0).reshape(N, 1, N).expand(N, N, N) * b.permute(1,0).reshape(1, N, N).expand(N, N, N)).sum(axis=2) + helper_test_generic_square('gemm_unrolled_permute_lr', N, f1, f2) + + def test_matvec_1024_1024(self): helper_test_matvec('matvec_1024_1024', 1024, 1024) + def test_matvec_1024_4096(self): helper_test_matvec('matvec_1024_4096', 1024, 4096) + def test_matvec_4096_1024(self): helper_test_matvec('matvec_4096_1024', 4096, 1024) + def test_matvec_4096_4096(self): helper_test_matvec('matvec_4096_4096', 4096, 4096) + + def test_openpilot_conv2d(self): + bs, in_chans, out_chans = 1,12,32 + torch.manual_seed(0) + torch_dat = torch.rand(bs, 64, 128, 12, dtype=torch_dt).to(torch_device) + torch_conv = torch.nn.Conv2d(in_chans, out_chans, 3, bias=None, padding=1, dtype=torch_dt).to(torch_device) + + tiny_dat = Tensor(torch_dat.cpu().numpy()) + tiny_conv = Conv2d(in_chans, out_chans, 3, bias=None, padding=1) + tiny_conv.weight = Tensor(torch_conv.weight.detach().cpu().numpy()) + + def f1(torch_dat): return torch_conv(torch_dat.permute(0,3,1,2)) + def f2(tiny_dat): return tiny_conv(tiny_dat.permute(0,3,1,2)).realize() + helper_test_generic(f"conv bs:{bs:3d} chans:{in_chans:3d} -> {out_chans:3d} k:3", f1, (torch_dat,), TinyJit(f2), (tiny_dat,)) + + def test_conv2d(self): + for bs in [32]: + for in_chans in IN_CHANS: + for out_chans in [32]: + helper_test_conv(bs, in_chans, out_chans, 3, 34, 34) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_stunning.py b/tinygrad_repo/test/test_stunning.py new file mode 100644 index 000000000..0429a4051 --- /dev/null +++ b/tinygrad_repo/test/test_stunning.py @@ -0,0 +1,59 @@ +import unittest +from tinygrad import nn, Tensor, Variable, Context, Device +from tinygrad.helpers import trange + +class Model: + def __init__(self): self.layer = nn.Linear(28*28, 10) + def __call__(self, x:Tensor) -> Tensor: return self.layer(x.flatten(1)) + +class TestStunning(unittest.TestCase): + def test_indexing_variable(self): + a = Tensor.arange(100*10).reshape(100, 10).contiguous() + + # index without variable + nv = a[12].tolist() + + # index with variable + vi = Variable('i', 0, a.shape[0]-1) + wv = a[vi.bind(12)].tolist() + + self.assertListEqual(nv, wv) + + def test_indexing_two_bind(self): + a = Tensor.arange(100*10).reshape(100, 10).contiguous() + + nv = a[12].cat(a[76]).tolist() + + vi = Variable('i', 0, a.shape[0]-1) + with self.assertRaisesRegex(AssertionError, "different values for the same key"): + wv = a[vi.bind(12)].cat(a[vi.bind(76)]).tolist() + self.assertListEqual(nv, wv) + + @unittest.skipIf(Device.DEFAULT in {"WEBGPU", "NV", "CUDA"}, "Too many buffers / too slow") + @unittest.skip("This is binding a Variable to two different values") + def test_simple_train(self, steps=6, bs=4, adam=True): + X_train, Y_train, _, _ = nn.datasets.mnist() + model = Model() + if adam: opt = nn.optim.Adam(nn.state.get_parameters(model)) + else: opt = nn.optim.SGD(nn.state.get_parameters(model), momentum=0.1) + samples = Tensor.randint(steps, bs, high=X_train.shape[0]) + Y_train = Y_train.one_hot(10) + X_samp, Y_samp = X_train[samples], Y_train[samples] + vi = Variable('i', 0, samples.shape[0]-1) + with Context(FUSE_ARANGE=1, SPLIT_REDUCEOP=0): + with Tensor.train(): + losses = [] + for i in range(samples.shape[0]): + vib = vi.bind(i) + opt.zero_grad() + pred = model(X_samp[vib].realize()) + loss = (pred - Y_samp[vib]).square().mean() + losses.append(loss.backward()) + opt.schedule_step() + #losses = Tensor.stack(*losses) + + # run + for i in (t:=trange(len(losses))): t.set_description(f"loss: {losses[i].item():6.2f}") + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_subbuffer.py b/tinygrad_repo/test/test_subbuffer.py new file mode 100644 index 000000000..c469a5742 --- /dev/null +++ b/tinygrad_repo/test/test_subbuffer.py @@ -0,0 +1,184 @@ +import unittest +from tinygrad import Device, dtypes, Tensor +from tinygrad.device import Buffer +from tinygrad.helpers import Context +from test.helpers import REAL_DEV + +@unittest.skipUnless(hasattr(Device[Device.DEFAULT].allocator, "_offset"), "subbuffer not supported") +class TestSubBuffer(unittest.TestCase): + def setUp(self): + self.buf = Buffer(Device.DEFAULT, 10, dtypes.uint8).ensure_allocated() + self.buf.copyin(memoryview(bytearray(range(10)))) + self.buf_unalloc = Buffer(Device.DEFAULT, 10, dtypes.uint8) + + def test_subbuffer(self): + vbuf = self.buf.view(2, dtypes.uint8, offset=3).ensure_allocated() + tst = vbuf.as_buffer().tolist() + assert tst == [3, 4] + + def test_subbuffer_cast(self): + # NOTE: bitcast depends on endianness + vbuf = self.buf.view(2, dtypes.uint16, offset=3).ensure_allocated() + tst = vbuf.as_buffer().cast("H").tolist() + assert tst == [3|(4<<8), 5|(6<<8)] + + def test_subbuffer_double(self): + vbuf = self.buf.view(4, dtypes.uint8, offset=3).ensure_allocated() + vvbuf = vbuf.view(2, dtypes.uint8, offset=1).ensure_allocated() + tst = vvbuf.as_buffer().tolist() + assert tst == [4, 5] + + def test_subbuffer_len(self): + vbuf = self.buf.view(5, dtypes.uint8, 2).ensure_allocated() + mv = vbuf.as_buffer() + assert len(mv) == 5 + mv = vbuf.as_buffer(allow_zero_copy=True) + assert len(mv) == 5 + + def test_subbuffer_used(self): + t = Tensor.arange(0, 10, dtype=dtypes.uint8).realize() + vt = t[2:4].realize() + out = (vt + 100).tolist() + assert out == [102, 103] + + @unittest.skipIf(REAL_DEV not in {"CUDA", "NV", "AMD"}, "only NV, AMD, CUDA") + def test_subbuffer_transfer(self): + t = Tensor.arange(0, 10, dtype=dtypes.uint8).realize() + vt = t[2:5].contiguous().realize() + out = vt.to(f"{Device.DEFAULT}:1").realize().tolist() + assert out == [2, 3, 4] + + def test_subbuffer_deallocate(self): + with Context(LRU=0): + vbuf = self.buf.view(2, dtypes.uint8, offset=3).ensure_allocated() + self.buf.deallocate() + vbuf.deallocate() + + # Allocate a fake one on the same place + _ = Buffer(Device.DEFAULT, 10, dtypes.uint8).ensure_allocated() + + self.buf.ensure_allocated() + self.buf.copyin(memoryview(bytearray(range(10, 20)))) + + vbuf.ensure_allocated() + + tst = vbuf.as_buffer().tolist() + assert tst == [13, 14] + + def test_subbuffer_is_allocated(self): + buf = self.buf_unalloc + sub_buf = buf.view(3, dtypes.uint8, offset=4) + self.assertFalse(buf.is_allocated()) + self.assertFalse(buf.is_initialized()) + self.assertFalse(sub_buf.is_allocated()) + self.assertFalse(sub_buf.is_initialized()) + + # base buffer alloc + buf.allocate() + self.assertTrue(buf.is_allocated()) + self.assertTrue(buf.is_initialized()) + self.assertTrue(sub_buf.is_allocated()) + self.assertFalse(sub_buf.is_initialized()) + + # sub buffer alloc + sub_buf.allocate() + self.assertTrue(sub_buf.is_initialized()) + + # sub buffer dealloc + sub_buf.deallocate() + self.assertTrue(buf.is_allocated()) + self.assertTrue(buf.is_initialized()) + self.assertTrue(sub_buf.is_allocated()) + self.assertFalse(sub_buf.is_initialized()) + + # base buffer dealloc + buf.deallocate() + self.assertFalse(buf.is_allocated()) + self.assertFalse(buf.is_initialized()) + self.assertFalse(sub_buf.is_allocated()) + self.assertFalse(sub_buf.is_initialized()) + + # sub buffer alloc + sub_buf.ensure_allocated() + self.assertTrue(buf.is_allocated()) + self.assertTrue(buf.is_initialized()) + self.assertTrue(sub_buf.is_allocated()) + self.assertTrue(sub_buf.is_initialized()) + + def test_subbuffer_copy_in_out(self): + sub_buf = self.buf.view(3, dtypes.uint8, offset=3).ensure_allocated() # [3:6] + data_out_sub = bytearray([0]*3) + sub_buf.copyout(memoryview(data_out_sub)) + assert data_out_sub == bytearray(range(3, 6)) + sub_buf.copyin(memoryview(bytearray(range(3)))) + assert sub_buf.as_buffer().tolist() == list(range(3)) + assert self.buf.as_buffer().tolist()[3:6] == list(range(3)) + sub_buf.copyout(memoryview(data_out_sub)) + assert data_out_sub == bytearray(range(3)) + data_out_base = bytearray([0]*10) + self.buf.copyout(memoryview(data_out_base)) + assert data_out_base[0:3] == bytearray(range(0, 3)) + assert data_out_base[3:6] == data_out_sub + assert data_out_base[6:10] == bytearray(range(6, 10)) + + def test_subbuffer_copy_in_out_view_of_view(self): + view1 = self.buf.view(7, dtypes.uint8, offset=2).ensure_allocated() # [2:9] + view2 = view1.view(3, dtypes.uint8, offset=2).ensure_allocated() # [4:7] + self.assertTrue(view1.is_allocated()) + self.assertTrue(view2.is_allocated()) + + data_in = bytearray([7, 8, 9]) + view2.copyin(memoryview(data_in)) + data_out_v2 = bytearray([0]*3) + view2.copyout(memoryview(data_out_v2)) + assert data_in == data_out_v2 + + expected_base_data = bytearray([0]*10) + expected_base_data = memoryview(bytearray(range(10))) + expected_base_data[4:7] = data_in + + data_out_base = bytearray([0]*10) + self.buf.copyout(memoryview(data_out_base)) + assert expected_base_data == data_out_base + + def test_subbuffer_alloc(self): + sub_buf = self.buf.view(4, dtypes.int8, offset=3) + sub_buf.allocate() + sub_buf.copyin(memoryview(bytearray(range(10, 14)))) + assert self.buf.as_buffer().tolist()[3:7] == sub_buf.as_buffer().tolist() + + sub_buf = self.buf_unalloc.view(4, dtypes.int8, offset=3) + sub_buf.allocate() + sub_buf.copyin(memoryview(bytearray(range(10, 14)))) + assert self.buf_unalloc.as_buffer().tolist()[3:7] == sub_buf.as_buffer().tolist() + + def test_subbuffer_dealloc(self): + sub_buf = self.buf.view(4, dtypes.int8, offset=3).ensure_allocated() + sub_buf.deallocate() + assert self.buf.as_buffer().tolist() == list(range(10)) + + def test_subbuffer_double_dealloc(self): + sub_buf = self.buf.view(3, dtypes.uint8, offset=4).ensure_allocated() + self.buf.deallocate() + with self.assertRaises(AssertionError): + self.buf.deallocate() + sub_buf.deallocate() + with self.assertRaises(AssertionError): + sub_buf.deallocate() + + def test_subbuffer_uaf(self): + sub_buf = self.buf.view(4, dtypes.int8, offset=3).ensure_allocated() + assert self.buf.as_buffer().tolist(), list(range(10)) + sub_buf.deallocate() + with self.assertRaises(AssertionError): + sub_buf.as_buffer().tolist() + assert self.buf.as_buffer().tolist(), list(range(10)) + + sub_buf = self.buf.view(4, dtypes.int8, offset=3).ensure_allocated() + assert sub_buf.as_buffer().tolist(), list(range(3, 7)) + self.buf.deallocate() + with self.assertRaises(AssertionError): + sub_buf.as_buffer().tolist() + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_symbolic_jit.py b/tinygrad_repo/test/test_symbolic_jit.py new file mode 100644 index 000000000..881ce3348 --- /dev/null +++ b/tinygrad_repo/test/test_symbolic_jit.py @@ -0,0 +1,327 @@ +import unittest + +from test.helpers import assert_jit_cache_len +from tinygrad import Variable, Tensor, TinyJit +from tinygrad.helpers import Context +import numpy as np + +class TestSymbolicJit(unittest.TestCase): + def setUp(self): + # A lot of these test are out of bounds, so we ignore the bounds check + self.context = Context(IGNORE_OOB=1) + self.context.__enter__() + + def tearDown(self): + self.context.__exit__(None, None, None) + + def test_plus1(self): + def f(a): return (a+1).realize() + jf = TinyJit(f) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(3, i) + symbolic = jf(a.reshape(3, vi)).reshape(3, i).numpy() + expected = f(a).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 1) + + def test_add(self): + def f(a, b): return (a+b).realize() + jf = TinyJit(f) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(3, i) + b = Tensor.rand(3, i) + symbolic = jf(a.reshape(3, vi), b.reshape(3, vi)).reshape(3, i).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 1) + + def test_matmul(self): + def f(a, b): return (a@b).realize() + jf = TinyJit(f) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(3, i) + b = Tensor.rand(i, 5) + symbolic = jf(a.reshape(3, vi), b.reshape(vi, 5)).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 1) + + def test_mixed_with_no_symbol_kernel(self): + def f(a, b): + s = (a@b).realize() + s = (s+s).realize() # this one does not have symbols in input + return s + jf = TinyJit(f) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(3, i) + b = Tensor.rand(i, 5) + symbolic = jf(a.reshape(3, vi), b.reshape(vi, 5)).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 2) + + def test_attention(self): + def f(q, k, v): return Tensor.scaled_dot_product_attention(q.transpose(1, 2), k.transpose(1, 2), v.transpose(1, 2)).realize() + jf = TinyJit(f) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + q = Tensor.rand(2, 1, 4, 8) + k = Tensor.rand(2, i, 4, 8) + v = Tensor.rand(2, i, 4, 8) + symbolic = jf(q, k.reshape(2, vi, 4, 8), v.reshape(2, vi, 4, 8)).reshape(2, 4, 1, 8).numpy() + expected = f(q, k, v).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 5) + + def test_cat_dim0(self): + def f(a, b): return a.cat(b, dim=0).realize() + jf = TinyJit(f) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(i, 3) + b = Tensor.rand(2, 3) + symbolic = jf(a.reshape(vi, 3), b).reshape(i+2, 3).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 1) + + def test_cat_dim1(self): + def f(a, b): return a.cat(b, dim=1).realize() + jf = TinyJit(f) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(3, i) + b = Tensor.rand(3, 2) + symbolic = jf(a.reshape(3, vi), b).reshape(3, i+2).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 1) + + def test_cat_dim0_two_vars(self): + def f(a, b): return a.cat(b, dim=0).realize() + jf = TinyJit(f) + for i in range(1, 5): + for j in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + vj = Variable("j", 1, 10).bind(j) + a = Tensor.rand(i, 3) + b = Tensor.rand(j, 3) + symbolic = jf(a.reshape(vi, 3), b.reshape(vj, 3)).reshape(i+j, 3).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 1) + + def test_cat_dim1_two_vars(self): + def f(a, b): return a.cat(b, dim=1).realize() + jf = TinyJit(f) + for i in range(1, 5): + for j in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + vj = Variable("j", 1, 10).bind(j) + a = Tensor.rand(3, i) + b = Tensor.rand(3, j) + symbolic = jf(a.reshape(3, vi), b.reshape(3, vj)).reshape(3, i+j).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 1) + + def test_two_vars_plus1_ij(self): + def f(a, b): return (a@b+1).realize() + jf = TinyJit(f) + for i in range(1, 5): + for j in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + vj = Variable("j", 1, 10).bind(j) + a = Tensor.rand(i, 3) + b = Tensor.rand(3, j) + symbolic = jf(a.reshape(vi, 3), b.reshape(3, vj)).reshape(i, j).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 1) + + def test_two_vars_plus1_ji(self): + def f(a, b): return (a@b+1).realize() + jf = TinyJit(f) + for i in range(1, 5): + for j in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + vj = Variable("j", 1, 10).bind(j) + a = Tensor.rand(j, 3) + b = Tensor.rand(3, i) + symbolic = jf(a.reshape(vj, 3), b.reshape(3, vi)).reshape(j, i).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 1) + + def test_jit_symbolic_shape_mismatch(self): + @TinyJit + def add(a, b): return (a+b).realize() + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(3, i).reshape(3, vi) + b = Tensor.rand(3, i).reshape(3, vi) + add(a, b) + vi2 = Variable("i", 1, 10).bind(7) + a = Tensor.rand(3, 7).reshape(3, vi2) + bad = Tensor.rand(4, 7).reshape(4, vi2) + with self.assertRaises(AssertionError): + add(a, bad) + + def test_shrink(self): + # shrink is a movement, so we pair it with a simple function to test the JIT interaction + def f(a): return (a+1).realize() + jf = TinyJit(f) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(7, 11) + symbolic = a.shrink(((3,5),(vi,vi+2))) + symbolic = jf(symbolic).numpy() + expected = f(a.shrink(((3,5),(i,i+2)))).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 1) + + def test_slice(self): + # slice is a movement, so we pair it with a simple function to test the JIT interaction + def f(a): return (a+1).realize() + jf = TinyJit(f) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(7, 11) + symbolic = a[3:5, vi:vi+2] + symbolic = jf(symbolic).numpy() + expected = f(a[3:5, i:i+2]).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 1) + + def test_slice_var_shape(self): + def f(a): return (a+1).realize() + jf = TinyJit(f) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.ones(vi, 11).contiguous() + symbolic = a[:, 1:2] + symbolic = jf(symbolic).reshape(i, 1).numpy() + expected = f(a.reshape(i, 11)[:, 1:2]).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + assert_jit_cache_len(jf, 1) + + def test_ones_sum(self): + def f(a): return a.sum().realize() + jf = TinyJit(f) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + t = Tensor.ones(i) + symbolic = jf(t.reshape(vi)).item() + expected = f(t).item() + np.testing.assert_equal(symbolic, expected) + + def test_mean(self): + def f(a): return a.mean().realize() + def f0(a): return a.mean(0).realize() + def f1(a): return a.mean(1).realize() + jf = TinyJit(f) + jf0 = TinyJit(f0) + jf1 = TinyJit(f1) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + # aixs = None + a = Tensor.rand(i, 3) + symbolic = jf(a.reshape(vi, 3)).numpy() + expected = a.mean().numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + # aixs = 0 + a = Tensor.rand(i, 3) + symbolic = jf0(a.reshape(vi, 3)).numpy() + expected = a.mean(0).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + # aixs = 1 + a = Tensor.rand(i, 3) + symbolic = jf1(a.reshape(vi, 3)).reshape(i).numpy() + expected = a.mean(1).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_mean_2d(self): + def f(a): return a.mean().realize() + def f0(a): return a.mean(0).realize() + def f1(a): return a.mean(1).realize() + jf = TinyJit(f) + jf0 = TinyJit(f0) + jf1 = TinyJit(f1) + for i in range(1, 5): + for j in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + vj = Variable("j", 1, 10).bind(j) + # aixs = None + a = Tensor.rand(i, j) + symbolic = jf(a.reshape(vi, vj)).numpy() + expected = a.mean().numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + # aixs = 0 + a = Tensor.rand(i, j) + symbolic = jf0(a.reshape(vi, vj)).reshape(j).numpy() + expected = a.mean(0).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + # aixs = 1 + a = Tensor.rand(i, j) + symbolic = jf1(a.reshape(vi, vj)).reshape(i).numpy() + expected = a.mean(1).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_var(self): + def f(a): return a.var().realize() + def f0(a): return a.var(0).realize() + def f1(a): return a.var(1).realize() + jf = TinyJit(f) + jf0 = TinyJit(f0) + jf1 = TinyJit(f1) + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + # aixs = None + a = Tensor.rand(i, 3) + symbolic = jf(a.reshape(vi, 3)).numpy() + expected = a.var().numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + # aixs = 0 + a = Tensor.rand(i, 3) + symbolic = jf0(a.reshape(vi, 3)).numpy() + expected = a.var(0).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + # aixs = 1 + a = Tensor.rand(i, 3) + symbolic = jf1(a.reshape(vi, 3)).reshape(i).numpy() + expected = a.var(1).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_var_2d(self): + def f(a): return a.var().realize() + def f0(a): return a.var(0).realize() + def f1(a): return a.var(1).realize() + jf = TinyJit(f) + jf0 = TinyJit(f0) + jf1 = TinyJit(f1) + for i in range(1, 5): + for j in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + vj = Variable("j", 1, 10).bind(j) + # aixs = None + a = Tensor.rand(i, j) + symbolic = jf(a.reshape(vi, vj)).numpy() + expected = a.var().numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + # aixs = 0 + a = Tensor.rand(i, j) + symbolic = jf0(a.reshape(vi, vj)).reshape(j).numpy() + expected = a.var(0).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + # aixs = 1 + a = Tensor.rand(i, j) + symbolic = jf1(a.reshape(vi, vj)).reshape(i).numpy() + expected = a.var(1).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_symbolic_ops.py b/tinygrad_repo/test/test_symbolic_ops.py new file mode 100644 index 000000000..082d04655 --- /dev/null +++ b/tinygrad_repo/test/test_symbolic_ops.py @@ -0,0 +1,282 @@ +import unittest +from tinygrad import Tensor, Variable +from tinygrad.shape.shapetracker import View +from tinygrad.helpers import Context, GlobalCounters +from tinygrad.uop.ops import sym_infer +from tinygrad.dtype import dtypes +from tinygrad.device import Device +from examples.gpt2 import Attention +import numpy as np + +class TestSymbolicOps(unittest.TestCase): + def setUp(self): + # A lot of these test are out of bounds, so we ignore the bounds check + self.context = Context(IGNORE_OOB=1) + self.context.__enter__() + + def tearDown(self): + self.context.__exit__(None, None, None) + + def test_plus1(self): + def f(a): return (a+1).realize() + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(3, i) + symbolic = f(a.reshape(3, vi)).reshape(3, i).numpy() + expected = f(a).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_add(self): + def f(a, b): return (a+b).realize() + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(3, i) + b = Tensor.rand(3, i) + symbolic = f(a.reshape(3, vi), b.reshape(3, vi)).reshape(3, i).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_matmul(self): + def f(a, b): return (a@b).realize() + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(3, i) + b = Tensor.rand(i, 5) + symbolic = f(a.reshape(3, vi), b.reshape(vi, 5)).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_attention(self, dropout_p=0.0, imin=1, imax=5, use_symbolic=True): + def f(q, k, v): return Tensor.scaled_dot_product_attention(q.transpose(1, 2), k.transpose(1, 2), v.transpose(1, 2), dropout_p=dropout_p).realize() + for i in range(imin, imax): + vi = Variable("i", 1, 10).bind(i) if use_symbolic else i + q = Tensor.rand(2, 1, 4, 8) + k = Tensor.rand(2, i, 4, 8) + v = Tensor.rand(2, i, 4, 8) + Tensor.realize(q, k, v) + GlobalCounters.reset() + symbolic = f(q, k.reshape(2, vi, 4, 8), v.reshape(2, vi, 4, 8)).reshape(2, 4, 1, 8).numpy() + expected = f(q, k, v).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_attention_cmp_symbolic(self): + # symbolic isn't seeing if i == i, so it's not putting them on the same axis + self.test_attention(imin=4, imax=5, use_symbolic=False) + self.test_attention(imin=4, imax=5, use_symbolic=True) + + # until this works, symbolic single kernel softmax won't + @unittest.expectedFailure + def test_attention_simple_view(self): + i = Variable("i", 2, 10) + v1 = View.create((2,4,1,i,i), ((i*4),i,0,0,1)) + v2 = View.create((2,4,1,i,i,i), (((i*i)*4),(i*i),0,0,i,1)) + self.assertIsNotNone(v1+v2) + + def test_attention_training(self): + with Tensor.train(): + self.test_attention(dropout_p=0.0) + with self.assertRaises(ValueError): + # symbolic shape dropout is not supported + self.test_attention(dropout_p=0.5) + + def test_attention_pos_0_sz_0(self): + Attention(128, 8)(Tensor.ones(1, 0, 128), Variable("start_pos", 0, 128).bind(0), None) + + def test_attention_pos_0_sz_1(self): + Attention(128, 8)(Tensor.ones(1, 1, 128), Variable("start_pos", 0, 128).bind(0), None) + + def test_attention_pos_0_sz_2(self): + Attention(128, 8)(Tensor.ones(1, 2, 128), Variable("start_pos", 0, 128).bind(0), None) + + def test_cat_dim0(self): + def f(a, b): return a.cat(b, dim=0).realize() + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(i, 3) + b = Tensor.rand(2, 3) + symbolic = f(a.reshape(vi, 3), b).reshape(i+2, 3).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_cat_dim1(self): + def f(a, b): return a.cat(b, dim=1).realize() + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(3, i) + b = Tensor.rand(3, 2) + symbolic = f(a.reshape(3, vi), b).reshape(3, i+2).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_cat_dim0_two_vars(self): + def f(a, b): return a.cat(b, dim=0).realize() + for i in range(1, 5): + for j in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + vj = Variable("j", 1, 10).bind(j) + a = Tensor.rand(i, 3) + b = Tensor.rand(j, 3) + symbolic = f(a.reshape(vi, 3), b.reshape(vj, 3)).reshape(i+j, 3).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_cat_dim1_two_vars(self): + def f(a, b): return a.cat(b, dim=1).realize() + for i in range(1, 5): + for j in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + vj = Variable("j", 1, 10).bind(j) + a = Tensor.rand(3, i) + b = Tensor.rand(3, j) + symbolic = f(a.reshape(3, vi), b.reshape(3, vj)).reshape(3, i+j).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_two_vars_plus1_ij(self): + def f(a, b): return (a@b+1).realize() + for i in range(1, 5): + for j in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + vj = Variable("j", 1, 10).bind(j) + a = Tensor.rand(i, 3) + b = Tensor.rand(3, j) + symbolic = f(a.reshape(vi, 3), b.reshape(3, vj)).reshape(i, j).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_two_vars_plus1_ji(self): + # reverse the order of variables + def f(a, b): return (a@b+1).realize() + for i in range(1, 5): + for j in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + vj = Variable("j", 1, 10).bind(j) + a = Tensor.rand(j, 3) + b = Tensor.rand(3, i) + symbolic = f(a.reshape(vj, 3), b.reshape(3, vi)).reshape(j, i).numpy() + expected = f(a, b).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_shrink(self): + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(7, 11) + symbolic = a.shrink(((3,5),(vi,vi+2))) + symbolic = symbolic.numpy() + expected = a.shrink(((3,5),(i,i+2))).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_slice(self): + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(7, 11) + symbolic = a[3:5, vi:vi+2] + symbolic = symbolic.numpy() + expected = a[3:5, i:i+2].numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_slice_no_start(self): + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(7, 11) + symbolic = a[3:5, :vi:1].reshape(2,i) + symbolic = symbolic.numpy() + expected = a[3:5, :i:1].numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_expand_padded(self): + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor(1).unsqueeze(0).pad((0, 1)).unsqueeze(0) + symbolic = a.expand(vi, 2).reshape(i, 2).numpy() + expected = a.expand(i, 2).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_slice_var_shape(self): + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.ones(vi, 11).contiguous() + symbolic = a[:, 1:2].reshape(i, 1).numpy() + expected = a.reshape(i, 11)[:, 1:2].numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_ones_sum(self): + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + t = Tensor.ones(i) + symbolic = t.reshape(vi).sum().item() + expected = t.sum().item() + np.testing.assert_equal(symbolic, expected) + + def test_mean(self): + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + for axis in [None, 0, 1]: + a = Tensor.rand(i, 3) + expected = a.mean(axis).numpy() + symbolic = a.reshape(vi, 3).mean(axis).reshape(expected.shape).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_mean_2d(self): + for i in range(1, 5): + for j in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + vj = Variable("j", 1, 10).bind(j) + for axis in [None, 0, 1]: + a = Tensor.rand(i, j) + expected = a.mean(axis).numpy() + symbolic = a.reshape(vi, vj).mean(axis).reshape(expected.shape).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_var(self): + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + for axis in [None, 0, 1]: + a = Tensor.rand(i, 3) + expected = a.var(axis).numpy() + symbolic = a.reshape(vi, 3).var(axis).reshape(expected.shape).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_var_2d(self): + for i in range(1, 5): + for j in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + vj = Variable("j", 1, 10).bind(j) + for axis in [None, 0, 1]: + a = Tensor.rand(i, j) + expected = a.var(axis).numpy() + symbolic = a.reshape(vi, vj).var(axis).reshape(expected.shape).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=1e-6) + + def test_bitcast_down(self): + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(i, 3) + expected = a.bitcast(dtypes.uint8).numpy() + symbolic = a.reshape(vi, 3).bitcast(dtypes.uint8).reshape(expected.shape).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=0) + + @unittest.skipIf(Device.DEFAULT == "WEBGPU", "no uint64") + def test_bitcast_up(self): + for i in range(1, 5): + vi = Variable("i", 1, 10).bind(i) + a = Tensor.rand(i, 4) + expected = a.bitcast(dtypes.uint64).numpy() + symbolic = a.reshape(vi, 4).bitcast(dtypes.uint64).reshape(expected.shape).numpy() + np.testing.assert_allclose(symbolic, expected, atol=1e-6, rtol=0) + + @unittest.expectedFailure + def test_conv2d_ceildiv_edge_case(self): + v = Variable('v', 11, 50_000) + val = 39601 + x = Tensor.randn(1, 22, 39601).reshape(1, 22, v.bind(val)) + weight = Tensor.randn(256, 22, 12) + + result = x.conv2d(weight=weight, groups=1, stride=6, dilation=1, padding=(3, 3)) + var_val = {v: val} + shape = tuple(sym_infer(s, var_val) for s in result.shape) + self.assertEqual(shape, (1, 256, 6600)) # TODO: fails if ceildiv is incorrect + # TODO: test output is correct + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_tensor.py b/tinygrad_repo/test/test_tensor.py new file mode 100644 index 000000000..704f69740 --- /dev/null +++ b/tinygrad_repo/test/test_tensor.py @@ -0,0 +1,910 @@ +import subprocess +import numpy as np +import torch +import unittest, copy, mmap, random, math, array +from tinygrad import Tensor, Device, dtypes +from tinygrad.tensor import _METADATA +from tinygrad.helpers import getenv, temp, mv_address +from extra.gradcheck import numerical_jacobian, jacobian, gradcheck +from hypothesis import given, settings, strategies as strat +from tinygrad.device import is_dtype_supported +from tinygrad.uop.ops import Ops, UOp +from tinygrad.runtime.support.compiler_cuda import PTX +from tinygrad.codegen import full_rewrite +from tinygrad.dtype import DType + +settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) +settings.load_profile("my_profile") + +x_init = np.random.randn(1,3).astype(np.float32) +U_init = np.random.randn(3,3).astype(np.float32) +V_init = np.random.randn(3,3).astype(np.float32) +W_init = np.random.randn(3,3).astype(np.float32) +m_init = np.random.randn(1,3).astype(np.float32) +gradient = np.random.randn(1,3).astype(np.float32) + +class TestTinygrad(unittest.TestCase): + def test_zerodim_initialization(self): + self.assertEqual(Tensor(55).shape, ()) + self.assertEqual(Tensor(3.14).shape, ()) + + def test_plus_equals(self): + a = Tensor.randn(10,10) + b = Tensor.randn(10,10) + c = a + b + val1 = c.numpy() + a += b + val2 = a.numpy() + np.testing.assert_allclose(val1, val2) + + def test_backward_pass(self): + def test_tinygrad(): + x = Tensor(x_init, requires_grad=True) + W = Tensor(W_init, requires_grad=True) + m = Tensor(m_init) + out = x.dot(W).relu() + out = out.log_softmax() + out = out.mul(m).add(m).sum() + out.backward() + return out.numpy(), x.grad.numpy(), W.grad.numpy() + + def test_pytorch(): + x = torch.tensor(x_init, requires_grad=True) + W = torch.tensor(W_init, requires_grad=True) + m = torch.tensor(m_init) + out = x.matmul(W).relu() + out = torch.nn.functional.log_softmax(out, dim=1) + out = out.mul(m).add(m).sum() + out.backward() + return out.detach().numpy(), x.grad, W.grad + + for x,y in zip(test_tinygrad(), test_pytorch()): + np.testing.assert_allclose(x, y, atol=1e-5) + + # A simple test is to check that we can accumulate gradients (run backward twice or more times) + def test_accumulate_gradients(self): + x = Tensor(x_init, requires_grad=True) + W = Tensor(W_init, requires_grad=True) + m = Tensor(m_init) + out = x.dot(W).relu() + out = out.log_softmax() + out = out.mul(m).add(m).sum() + out.backward() + xgrad,wgrad = x.grad, W.grad + out.backward() + xgrad2,wgrad2 = x.grad, W.grad + out.backward() # no need to retain again since we will not re-run backward + xgrad3,wgrad3 = x.grad, W.grad + np.testing.assert_allclose(xgrad3.numpy(), xgrad.numpy() * 3., atol=1e-6) + np.testing.assert_allclose(wgrad3.numpy(), wgrad.numpy() * 3., atol=1e-6) + np.testing.assert_allclose(xgrad2.numpy(), xgrad.numpy() * 2., atol=1e-6) + np.testing.assert_allclose(wgrad2.numpy(), wgrad.numpy() * 2., atol=1e-6) + + def test_second_order_backward_pass(self): + def test_pytorch(): + x_val = torch.tensor([2.0], requires_grad=True) + f = x_val**3 + first_derivative = torch.autograd.grad(outputs=f, inputs=x_val, create_graph=True)[0] + second_derivative = torch.autograd.grad(outputs=first_derivative, inputs=x_val)[0] + # d^2f/dx^2 = 6x = 6*2 = 12 + return second_derivative.numpy() + + def test_tinygrad(): + x_val = Tensor(2.0) + f = x_val**3 + first_derivative = f.gradient(x_val)[0] + second_derivative = first_derivative.gradient(x_val)[0] + return second_derivative.numpy() + + np.testing.assert_allclose(test_tinygrad(), test_pytorch(), atol=1e-5) + + # passing `gradient` to backward + def test_backward_pass_vjp(self): + def test_tinygrad(): + x = Tensor(x_init, requires_grad=True) + W = Tensor(W_init, requires_grad=True) + m = Tensor(m_init) + out = x.dot(W).relu() + out = out.log_softmax() + out = out.mul(m).add(m) + out.backward(Tensor(gradient)) + return out.numpy(), x.grad.numpy(), W.grad.numpy() + + def test_pytorch(): + x = torch.tensor(x_init, requires_grad=True) + W = torch.tensor(W_init, requires_grad=True) + m = torch.tensor(m_init) + out = x.matmul(W).relu() + out = torch.nn.functional.log_softmax(out, dim=1) + out = out.mul(m).add(m) + out.backward(torch.tensor(gradient)) + return out.detach().numpy(), x.grad, W.grad + + for x,y in zip(test_tinygrad(), test_pytorch()): + np.testing.assert_allclose(x, y, atol=1e-5) + + def test_backward_pass_diamond_model(self): + def test_tinygrad(): + u = Tensor(U_init, requires_grad=True) + v = Tensor(V_init, requires_grad=True) + w = Tensor(W_init, requires_grad=True) + x = u.mul(v).relu() + y = u.mul(w).relu() + out = x.add(y).mul(y).relu() + out = out.log_softmax() + out = out.sum() + out.backward() + return out.numpy(), u.grad.numpy(), v.grad.numpy(), w.grad.numpy() + + def test_pytorch(): + u = torch.tensor(U_init, requires_grad=True) + v = torch.tensor(V_init, requires_grad=True) + w = torch.tensor(W_init, requires_grad=True) + x = u.mul(v).relu() + y = u.mul(w).relu() + out = x.add(y).mul(y).relu() + out = torch.nn.functional.log_softmax(out, dim=1) + out = out.sum() + out.backward() + return out.detach().numpy(), u.grad, v.grad, w.grad + + for x,y in zip(test_tinygrad(), test_pytorch()): + np.testing.assert_allclose(x, y, atol=1e-5, rtol=1e-6) + + @unittest.expectedFailure + def test_const_backward_pass(self): + init = 3.5 + + def test_pytorch(): + w1 = torch.tensor(init, requires_grad=True) + w2 = torch.tensor(init, requires_grad=True) + out = w1.add(w2) + out.backward() + return w1.grad, w2.grad + + def test_tinygrad(): + w1 = Tensor(init, requires_grad=True) + w2 = Tensor(init, requires_grad=True) + out = w1.add(w2) + out.backward() + return w1.grad.numpy(), w2.grad.numpy() + + for x, y in zip(test_tinygrad(), test_pytorch()): + np.testing.assert_allclose(x, y, atol=1e-5) + + def test_nograd(self): + x = Tensor(x_init, requires_grad=False) + m = Tensor(m_init, requires_grad=False) + W = Tensor(W_init, requires_grad=True) + tmp = x.mul(m) + mm = tmp.matmul(W) + out = mm.relu() + out = out.sum() + out.backward() + assert x.grad is None + assert m.grad is None + assert tmp.grad is None + assert mm.grad is not None + assert W.grad is not None + + def test_dropout(self): + with Tensor.train(): + n, rate = 1_000_000, 0.1 + w = Tensor.ones(n).dropout(rate) + non_zeros = np.count_nonzero(w.numpy()) + expected = n * (1 - rate) + np.testing.assert_allclose(non_zeros, expected, rtol=2e-3) + + def test_jacobian(self): + W = np.random.RandomState(42069).random((10, 5)).astype(np.float32) + x = np.random.RandomState(69420).random((1, 10)).astype(np.float32) + + torch_x = torch.tensor(x, requires_grad=True) + torch_W = torch.tensor(W, requires_grad=True) + def torch_func(x): return torch.nn.functional.log_softmax(x.matmul(torch_W).relu(), dim=1) + PJ = torch.autograd.functional.jacobian(torch_func, torch_x).squeeze().numpy() + + tiny_x = Tensor(x, requires_grad=True) + tiny_W = Tensor(W, requires_grad=True) + def tiny_func(x): return x.dot(tiny_W).relu().log_softmax() + J = jacobian(tiny_func, tiny_x) + NJ = numerical_jacobian(tiny_func, tiny_x) + + np.testing.assert_allclose(PJ, J, atol = 1e-5) + np.testing.assert_allclose(PJ, NJ, atol = 1e-3) + + def test_gradcheck(self): + W = np.random.RandomState(1337).random((10, 5)).astype(np.float32) + x = np.random.RandomState(7331).random((1, 10)).astype(np.float32) + + tiny_x = Tensor(x, requires_grad=True) + tiny_W = Tensor(W, requires_grad=True) + def tiny_func(x): return x.dot(tiny_W).relu().log_softmax() + + self.assertTrue(gradcheck(tiny_func, tiny_x, eps = 1e-3)) + + # coarse approx. since a "big" eps and the non-linearities of the model + self.assertFalse(gradcheck(tiny_func, tiny_x, eps = 1e-5)) + + def test_random_fns_are_deterministic_with_seed(self): + for random_fn in [Tensor.randn, Tensor.normal, Tensor.uniform, Tensor.scaled_uniform, Tensor.glorot_uniform, Tensor.kaiming_normal]: + with self.subTest(msg=f"Tensor.{random_fn.__name__}"): + Tensor.manual_seed(1337) + a = random_fn(10,10).realize() + Tensor.manual_seed(1337) + b = random_fn(10,10).realize() + np.testing.assert_allclose(a.numpy(), b.numpy()) + + def test_randperm(self): + Tensor.manual_seed(0) + a = Tensor.randperm(10).realize() + np.testing.assert_equal(a.numpy(), [5, 2, 8, 1, 3, 7, 9, 6, 0, 4]) + b = Tensor.randperm(1000).realize() + np.testing.assert_equal(set(b.numpy()), set(range(1000))) + + def test_randn_isnt_inf_on_zero(self): + # simulate failure case of rand handing a zero to randn + original_rand, Tensor.rand = Tensor.rand, Tensor.zeros + try: self.assertNotIn(np.inf, Tensor.randn(16).numpy()) + except: raise + finally: Tensor.rand = original_rand + + def test_zeros_like_has_same_dtype_and_shape(self): + for datatype in [dtypes.float16, dtypes.float32, dtypes.int8, dtypes.int32, dtypes.int64, dtypes.uint8]: + a = Tensor([1, 2, 3], dtype=datatype) + b = Tensor.zeros_like(a) + assert a.dtype == b.dtype, f"dtype mismatch {a.dtype=} != {b.dtype}" + assert a.shape == b.shape, f"shape mismatch {a.shape} != {b.shape}" + + a = Tensor([1, 2, 3]) + b = Tensor.zeros_like(a, dtype=dtypes.int8) + assert a.dtype == dtypes.default_int and b.dtype == dtypes.int8, "a.dtype should be int and b.dtype should be char" + assert a.shape == b.shape, f"shape mismatch {a.shape} != {b.shape}" + + def test_ones_like_has_same_dtype_and_shape(self): + for datatype in [dtypes.float16, dtypes.float32, dtypes.int8, dtypes.int32, dtypes.int64, dtypes.uint8]: + a = Tensor([1, 2, 3], dtype=datatype) + b = Tensor.ones_like(a) + assert a.dtype == b.dtype, f"dtype mismatch {a.dtype=} != {b.dtype}" + assert a.shape == b.shape, f"shape mismatch {a.shape} != {b.shape}" + + a = Tensor([1, 2, 3]) + b = Tensor.ones_like(a, dtype=dtypes.int8) + assert a.dtype == dtypes.default_int and b.dtype == dtypes.int8, "a.dtype should be int and b.dtype should be char" + assert a.shape == b.shape, f"shape mismatch {a.shape} != {b.shape}" + + def test_rand_like_device(self): + a = Tensor.ones(3, 3, device="CPU") + b = Tensor.rand_like(a) + self.assertEqual(b.device, a.device) + + def test_ndim(self): + assert Tensor(1).ndim == 0 + assert Tensor.randn(1).ndim == 1 + assert Tensor.randn(2,2,2).ndim == 3 + assert Tensor.randn(1,1,1,1,1,1).ndim == 6 + + def test_argfix(self): + for f in [Tensor.zeros, Tensor.ones, Tensor.rand, Tensor.randn, Tensor.empty]: + self.assertEqual(f().shape, ()) + self.assertEqual(f(1).shape, (1,)) + self.assertEqual(f(10,20,40).shape, (10,20,40)) + self.assertEqual(f([]).shape, ()) + self.assertEqual(f([1]).shape, (1,)) + self.assertEqual(f([10,20,40]).shape, (10,20,40)) + self.assertEqual(f(()).shape, ()) + self.assertEqual(f((1,)).shape, (1,)) + self.assertEqual(f((10,20,40)).shape, (10,20,40)) + + with self.assertRaises(ValueError): f((2, 2), 2, 2) + with self.assertRaises(ValueError): f((2, 2), (2, 2)) + with self.assertRaises(ValueError): f((128, 128), 0.0, 0.01) + + def test_numel(self): + assert Tensor.randn(10, 10).numel() == 100 + assert Tensor.randn(1,2,5).numel() == 10 + assert Tensor.randn(1,1,1,1,1,1).numel() == 1 + assert Tensor([]).numel() == 0 + assert Tensor.randn(1,0,2,5).numel() == 0 + assert Tensor(3).numel() == 1 + + def test_len(self): + assert len(torch.zeros(7)) == len(Tensor.zeros(7)) + assert len(torch.zeros(10,20)) == len(Tensor.zeros(10,20)) + assert len(torch.zeros(10,20)) == len(Tensor.zeros(10,20,30)) + assert len(torch.zeros(1).flatten()) == len(Tensor.zeros(1).flatten()) + with self.assertRaises(TypeError): len(Tensor(3)) + + def test_size(self): + t1, t2 = torch.zeros(10,20), Tensor.zeros(10,20) + assert t1.size() == t2.size() + assert t1.size(0) == t2.size(0) + assert t1.size(1) == t2.size(1) + assert t1.size(-1) == t2.size(-1) + assert t1.size(-2) == t2.size(-2) + with self.assertRaises(IndexError): t2.size(2) + + def test_tolist(self): + # NOTE: float16 Tensor.tolist() requires python 3.12 + for arr in [[1,2,3], [1.5,2,3], [[1,2,3], [4,5,6]], 3]: + assert Tensor(arr).tolist() == torch.tensor(arr).tolist() == arr + + def test_element_size(self): + for _, dtype in dtypes.fields().items(): + assert dtype.itemsize == Tensor.randn(3, dtype=dtype).element_size(), f"Tensor.element_size() not matching Tensor.dtype.itemsize for {dtype}" + + def test_deepwalk_ctx_check(self): + layer = Tensor.uniform(1, 1, requires_grad=True) + x = Tensor.randn(1, 1, 1) + x.dot(layer).mean().backward() + x = Tensor.randn(1, 1, 1) + x.dot(layer).mean().backward() + + def test_zerosized_tensors(self): + np.testing.assert_equal(Tensor([]).numpy(), np.array([])) + np.testing.assert_equal(Tensor(None).numpy(), np.array([])) + + def test_tensor_ndarray_dtype(self): + arr = np.array([1]) # where dtype is implicitly int64 + assert Tensor(arr).dtype == dtypes.int64 + assert Tensor(arr, dtype=dtypes.float32).dtype == dtypes.float32 # check if ndarray correctly casts to Tensor dtype + assert Tensor(arr, dtype=dtypes.float64).dtype == dtypes.float64 # check that it works for something else + + def test_tensor_from_blob(self): + x = memoryview(bytearray(16)).cast('I') + + t = Tensor.from_blob(mv_address(x), (4,), dtype=dtypes.int, device="CPU") + z = (t+1) + np.testing.assert_equal(z.numpy(), [1, 1, 1, 1]) + + x[:] = array.array('I', [0, 1, 2, 3]) + z = (t+1) + np.testing.assert_equal(z.numpy(), [1, 2, 3, 4]) + + def test_tensor_list_dtype(self): + for arr in ([1], [[[1]]], [[1,1],[1,1]], [[[1,1],[1,1]],[[1,1],[1,1]]]): + assert Tensor(arr).dtype == dtypes.default_int + assert Tensor(arr, dtype=dtypes.float32).dtype == dtypes.float32 + assert Tensor(arr, dtype=dtypes.float64).dtype == dtypes.float64 + + for arr in ([True], [[[False]]], [[True,False],[True,False]], [[[False,True],[False,False]],[[True,True],[False,True]]]): + assert Tensor(arr).dtype == dtypes.bool + assert Tensor(arr, dtype=dtypes.float32).dtype == dtypes.float32 + assert Tensor(arr, dtype=dtypes.float64).dtype == dtypes.float64 + + # empty tensor defaults + for arr in ([], [[[]]], [[],[]]): + t = Tensor(arr) + assert t.dtype == dtypes.default_float + np.testing.assert_allclose(t.numpy(), np.array(arr)) + + # mixture of bool and int + for arr in ([True, 3], [[True],[3]], [[[True]], [[3]]], [[True, 3], [3, True]]): + t = Tensor(arr) + assert t.dtype == dtypes.default_int + np.testing.assert_allclose(t.numpy(), np.array(arr)) + + # mixture of bool, int and float + for arr in ([[True,True],[3.,True]], [[0,1],[3.,4]], [[[0],[1]],[[3.],[4]]], [[[True],[1]],[[3.],[4]]]): + t = Tensor(arr) + assert t.dtype == dtypes.default_float + np.testing.assert_allclose(t.numpy(), np.array(arr)) + + def test_tensor_list_shapes(self): + self.assertEqual(Tensor([[[]]]).shape, (1,1,0)) + self.assertEqual(Tensor([[],[]]).shape, (2,0)) + self.assertEqual(Tensor([[[[]],[[]]], [[[]],[[]]], [[[]],[[]]]]).shape, (3,2,1,0)) + + def test_tensor_list_errors(self): + # inhomogeneous shape + with self.assertRaises(ValueError): Tensor([[],[[]]]) + with self.assertRaises(ValueError): Tensor([[1],[]]) + with self.assertRaises(ValueError): Tensor([[1],[1],1]) + with self.assertRaises(ValueError): Tensor([[[1,1,1],[1,1]]]) + with self.assertRaises(ValueError): Tensor([[1,1,1],[[1,1,1]]]) + + def test_tensor_mixed_list_tuple(self): + def _list_or_tuple(): return list if random.random() < 0.5 else tuple + def _generate_data(depth): + if depth == 0: return _list_or_tuple()() + if depth == 1: return _list_or_tuple()([random.random(), random.random()]) + return _list_or_tuple()([_generate_data(depth-1), _generate_data(depth-1)]) + + for depth in range(7): + for _ in range(20): + data = _generate_data(depth) + np.testing.assert_allclose(Tensor(data).numpy(), np.array(data)) + + def test_tensor_list_special_values(self): + if is_dtype_supported(dtypes.float16): + data = [math.nan, -math.inf, 65504, 65519, 65519.999, 65520, 65520.1] + data = data + [-x for x in data] + with np.errstate(over='ignore'): np.testing.assert_allclose(Tensor(data, dtype=dtypes.float16).numpy(), np.array(data).astype(np.float16)) + + # uint32 + data = [1 << 33, 1 << 32, 1 << 32 - 1, 1] + data = data + [-x for x in data] + np.testing.assert_allclose(Tensor(data, dtype=dtypes.uint32).numpy(), np.array(data).astype(np.uint32)) + + # int32 + data = [1 << 33, 1 << 32, 1 << 32 - 1, 1] + data = data + [-x for x in data] + np.testing.assert_allclose(Tensor(data, dtype=dtypes.int32).numpy(), np.array(data).astype(np.int32)) + + def test_tensor_list_ndarray(self): + data = [np.array([1, 2, 3]), np.array([1, 2, 3]), np.array([1, 2, 3])] + np.testing.assert_equal(Tensor(data).numpy(), np.array(data)) + data = [np.array([1.0, 2.0, 3.0]), np.array([1, 2, 3]), np.array([1, 2, 3])] + np.testing.assert_equal(Tensor(data).numpy(), np.array(data)) + data = [np.array(1.0), np.array(2.0), np.array(3.0)] + np.testing.assert_equal(Tensor(data).numpy(), np.array(data)) + + def test_tensor_dtype_errors(self): + with self.assertRaises(AttributeError): Tensor([3], dtype="typo") + with self.assertRaises(AttributeError): Tensor([3], dtype=(dtypes.int,)) + + def test_tensor_bytes(self): + data = b"abc123" + t = Tensor(data) + assert t.dtype == dtypes.uint8 + assert t.shape == (6,) + np.testing.assert_equal(t.numpy(), list(data)) + + def test_tensor_copy(self): + x = copy.deepcopy(Tensor.ones((3,3,3))) + np.testing.assert_allclose(x.numpy(), np.ones((3,3,3))) + + def test_copy_from_disk(self): + t = Tensor.randn(30).to(f"disk:{temp('test_copy_from_disk')}") + a = t[10:20] + dev = a.to(Device.DEFAULT) + np.testing.assert_allclose(a.numpy(), dev.numpy()) + + # Regression test for https://github.com/tinygrad/tinygrad/issues/1751 + def test_copy_from_numpy_unaligned(self): + # 2**15 is the minimum for repro + arr = np.random.randn(2**15).astype(np.float32) + fn = temp('test_copy_from_numpy_unaligned') + with open(fn, 'wb') as f: f.write(b't' + arr.tobytes()) + with open(fn, "a+b") as f: memview = memoryview(mmap.mmap(f.fileno(), arr.nbytes + 1)) + ua_arr = np.frombuffer(memview[1:], dtype=arr.dtype, count=arr.shape[0]) + np.testing.assert_allclose(arr, ua_arr) + assert not ua_arr.flags.aligned + # force device copy - to() is opt'd away - Tensor(dev)/1 is ignored + np.testing.assert_allclose(ua_arr, (Tensor(ua_arr)/Tensor(1)).numpy()) + + def test_item_to_tensor_to_item(self): + for a in [0, 1, 2, 3, -1, -100, 100, -101.1, 2.345, 100.1, True, False]: + item = Tensor(a).item() + assert type(item) is type(a), a + np.testing.assert_allclose(item, a), a + buffered_item = Tensor([a]).item() + assert type(buffered_item) is type(a), a + np.testing.assert_allclose(buffered_item, a), a + reshaped_item = Tensor([a]).reshape((1, 1, 1, 1, 1)).item() + assert type(reshaped_item) is type(a), a + np.testing.assert_allclose(reshaped_item, a), a + + def test_no_bool(self): + with self.assertRaises(TypeError): + if Tensor(3): + print("hi") + + with self.assertRaises(TypeError): + _a = Tensor([3]) in [Tensor([3]), Tensor([4]), Tensor([5])] + + def test_repr_with_grad(self): + a = Tensor([1.0], requires_grad=True) + b = Tensor([1]) + c = (a + b).sum().backward() + print(a) + print(c) + + def test_env_overwrite_default_device(self): + subprocess.run(['DISK=1 python3 -c "from tinygrad import Device; assert Device.DEFAULT != \\"DISK\\""'], + shell=True, check=True) + subprocess.run(['NPY=1 python3 -c "from tinygrad import Device; assert Device.DEFAULT != \\"NPY\\""'], + shell=True, check=True) + subprocess.run([f'{Device.DEFAULT}=1 python3 -c "from tinygrad import Device; assert Device.DEFAULT == \\"{Device.DEFAULT}\\""'], + shell=True, check=True) + subprocess.run([f'DISK=1 {Device.DEFAULT}=1 python3 -c "from tinygrad import Device; assert Device.DEFAULT == \\"{Device.DEFAULT}\\""'], + shell=True, check=True) + subprocess.run([f'NPY=1 {Device.DEFAULT}=1 python3 -c "from tinygrad import Device; assert Device.DEFAULT == \\"{Device.DEFAULT}\\""'], + shell=True, check=True) + + def test_no_attributeerror_after_apply_uop_exception(self): + try: + Tensor.arange(4).reshape(3,2) + except ValueError: + Tensor.zeros(2, 2).realize() + + def test_shrink(self): + t = Tensor.arange(32).contiguous().realize() + self.assertListEqual(t[16:20].tolist(), [16,17,18,19]) + +@unittest.skip("this test is just flaky, sync issue") +class TestMoveTensor(unittest.TestCase): + d0, d1 = f"{Device.DEFAULT}:0", f"{Device.DEFAULT}:1" + @given(strat.sampled_from([d0, d1]), strat.sampled_from([d0, d1]), + strat.sampled_from([dtypes.float16, dtypes.float32]), strat.sampled_from([True, False, None])) + def test_to_preserves(self, src, dest, dtype, requires_grad): + if not is_dtype_supported(dtype): + return + s = Tensor([1, 2, 3], device=src, dtype=dtype, requires_grad=requires_grad) + if requires_grad: s.sum().backward() + t = s.to(dest) + np.testing.assert_equal(s.numpy(), t.numpy()) + assert s.dtype == t.dtype + assert s.requires_grad == t.requires_grad + if requires_grad: + np.testing.assert_equal(s.grad.numpy(), t.grad.numpy()) + + @given(strat.sampled_from([dtypes.float16, dtypes.float32]), strat.sampled_from([True, False, None])) + def test_shard_preserves(self, dtype, requires_grad): + s = Tensor([1, 2, 3], dtype=dtype, requires_grad=requires_grad) + t = s.shard((f"{Device.DEFAULT}:0", f"{Device.DEFAULT}:1")) + np.testing.assert_equal(s.numpy(), t.numpy()) + assert s.dtype == t.dtype + assert s.requires_grad == t.requires_grad + + @given(strat.sampled_from([d0, d1])) + def test_same_dev(self, dev): + x = Tensor([1,2,3], device=dev) + y = x.to(dev) + assert x is y + + def test_to_grad(self): + x = Tensor.eye(3, requires_grad=True, device=self.d0) + y = Tensor([[2.0,0,-2.0]], requires_grad=True, device=self.d0) + z = y.matmul(x).to(self.d1).sum() + z.backward() + np.testing.assert_equal(x.grad.numpy(), [[2,2,2],[0,0,0],[-2,-2,-2]]) + +class TestZeroShapeTensor(unittest.TestCase): + def test_shape_stride(self): + t = Tensor.empty(3, 2, 0) + assert t.shape == (3, 2, 0) + # numpy has stride 0, 0, 0; torch has stride 2, 1, 1 + assert t.uop.st.real_strides() == (0, 0, 0) + + t = Tensor.empty(3, 0, 2) + assert t.shape == (3, 0, 2) + # numpy has stride 0, 0, 0; torch has stride 2, 2, 1 + assert t.uop.st.real_strides() == (0, 0, 0) + + t = Tensor.empty(0, 0, 0) + assert t.shape == (0, 0, 0) + # numpy has stride 0, 0, 0; torch has stride 1, 1, 1 + assert t.uop.st.real_strides() == (0, 0, 0) + + def test_rand(self): + t = Tensor.rand(3, 2, 0) + assert t.shape == (3, 2, 0) + np.testing.assert_equal(t.numpy(), np.zeros((3, 2, 0))) + t = Tensor.rand(0) + assert t.shape == (0,) + np.testing.assert_equal(t.numpy(), np.zeros((0,))) + t = Tensor.rand(0, 0, 0) + assert t.shape == (0, 0, 0) + np.testing.assert_equal(t.numpy(), np.zeros((0, 0, 0))) + + def test_full(self): + t = Tensor.zeros(3, 2, 0) + assert t.shape == (3, 2, 0) + np.testing.assert_equal(t.numpy(), np.zeros((3, 2, 0))) + t = Tensor.full((3, 2, 0), 12) + assert t.shape == (3, 2, 0) + np.testing.assert_equal(t.numpy(), np.full((3, 2, 0), 12)) + + def test_reshape(self): + t = Tensor.zeros(3, 2, 0) + a = t.reshape(7, 0) + assert a.shape == (7, 0) + np.testing.assert_equal(a.numpy(), np.zeros((7, 0))) + a = t.reshape(0) + assert a.shape == (0,) + np.testing.assert_equal(a.numpy(), np.zeros((0,))) + with self.assertRaises(ValueError): + # cannot reshape from size 0 to size 1 + a = t.reshape(()) + + def test_expand(self): + t = Tensor.full((1, 2, 0), 12).expand((6, 2, 0)) + assert t.shape == (6, 2, 0) + np.testing.assert_equal(t.numpy(), np.full((6, 2, 0), 12)) + + def test_pad(self): + t = Tensor.rand(3, 2, 0).pad((None, None, (1, 1)), value=1) + assert t.shape == (3, 2, 2) + np.testing.assert_equal(t.numpy(), np.ones((3, 2, 2))) + + t = Tensor.rand(3, 2, 0).pad((None, (1, 1), None), value=1) + assert t.shape == (3, 4, 0) + np.testing.assert_equal(t.numpy(), np.ones((3, 4, 0))) + + t = Tensor.rand(3, 2, 0).pad(((1, 1), None, None), value=1) + assert t.shape == (5, 2, 0) + np.testing.assert_equal(t.numpy(), np.ones((5, 2, 0))) + + def test_shrink_into_zero(self): + t = Tensor.rand(3, 4).realize() + assert t.shrink((None, (2, 2))).realize().shape == (3, 0) + assert t.shrink(((2, 2), None)).realize().shape == (0, 4) + assert t.shrink(((2, 2), (2, 2))).realize().shape == (0, 0) + + def test_cat(self): + a = Tensor.rand(3, 2, 2) + b = Tensor.rand(3, 2, 0) + + t = a.cat(b, dim=2) + assert t.shape == (3, 2, 2) + np.testing.assert_equal(t.numpy(), a.numpy()) + + t = b.cat(a, dim=2) + assert t.shape == (3, 2, 2) + np.testing.assert_equal(t.numpy(), a.numpy()) + + t = b.cat(b, dim=0) + assert t.shape == (6, 2, 0) + np.testing.assert_equal(t.numpy(), np.zeros((6, 2, 0))) + t = b.cat(b, dim=1) + assert t.shape == (3, 4, 0) + np.testing.assert_equal(t.numpy(), np.zeros((3, 4, 0))) + t = b.cat(b, dim=2) + assert t.shape == (3, 2, 0) + np.testing.assert_equal(t.numpy(), np.zeros((3, 2, 0))) + + def test_elementwise(self): + a = Tensor.rand(3, 2, 0) + a_exp = a.exp() + assert a_exp.shape == (3, 2, 0) + np.testing.assert_equal(a_exp.numpy(), np.exp(a.numpy())) + + b = Tensor.rand(3, 2, 0) + assert b.shape == (3, 2, 0) + ab = a * b + assert ab.shape == (3, 2, 0) + np.testing.assert_equal(ab.numpy(), a.numpy() * b.numpy()) + + mask = (Tensor.rand(3, 2, 0) > 0.5) + assert mask.shape == (3, 2, 0) + c = mask.where(a, b) + assert c.shape == (3, 2, 0) + np.testing.assert_equal(c.numpy(), np.where(mask.numpy(), a.numpy(), b.numpy())) + + def test_reduce_over_non_zero(self): + a = Tensor.ones(3, 2, 0).sum(axis=1) + assert a.shape == (3, 0) + np.testing.assert_equal(a.numpy(), np.sum(np.zeros((3, 2, 0)), axis=1)) + + def test_reduce_over_zero(self): + a = Tensor.ones(3, 2, 0).sum(axis=2) + assert a.shape == (3, 2) + np.testing.assert_equal(a.numpy(), np.sum(np.zeros((3, 2, 0)), axis=2)) + + a = Tensor.ones(3, 2, 0).sum(axis=2, keepdim=True) + assert a.shape == (3, 2, 1) + np.testing.assert_equal(a.numpy(), np.sum(np.zeros((3, 2, 0)), axis=2, keepdims=True)) + + def test_clone(self): + a = Tensor.rand(16, 16).realize() + b = a.clone() + np.testing.assert_allclose(a.numpy(), b.numpy()) + self.assertIsNot(a.uop.base.buffer, b.uop.base.buffer) + + a = Tensor.rand(16, 16).mul(5.0).add(5.0).realize() + b = a.clone() + np.testing.assert_allclose(a.numpy(), b.numpy()) + self.assertIsNot(a.uop.base.buffer, b.uop.base.buffer) + + def test_clone_with_shrink(self): + a = Tensor.rand(16, 16) + b = a.shrink(((2, 10), None)).clone() + b.realize() + self.assertIsNot(a.uop.base.buffer, b.uop.base.buffer) + + def test_clone_with_shrink_realized(self): + a = Tensor.rand(16, 16).realize() + b = a.shrink(((2, 10), None)).clone() + b.realize() + self.assertIsNot(a.uop.base.buffer, b.uop.base.buffer) + + def test_clone_with_grad(self): + a = Tensor.rand(16, 16, requires_grad=True) + a.mul(5.0).add(5.0).mean().backward() + b = a.clone() + assert a.grad is not None + assert b.grad is not None + np.testing.assert_allclose(a.grad.numpy(), b.grad.numpy()) + + def test_reduce_default(self): + np.testing.assert_equal(Tensor([]).max().numpy(), -float("inf")) + np.testing.assert_equal(Tensor([]).min().numpy(), float("inf")) + np.testing.assert_equal(Tensor([]).sum().numpy(), 0) + np.testing.assert_equal(Tensor([]).mean().numpy(), float("nan")) + +class TestTensorCreationDevice(unittest.TestCase): + # test auxiliary tensors are created on the same device + def test_one_hot(self): + y = Tensor([1, 2, 3]).to("CPU") + x = y.one_hot(10) + x.realize() + +class TestTrainMode(unittest.TestCase): + def test_train_mode(self): + assert not Tensor.training + @Tensor.train() + def f(): + assert Tensor.training + f() + assert not Tensor.training + +class TestInferenceMode(unittest.TestCase): + def test_inference(self): + x = Tensor(x_init, requires_grad=True) + m = Tensor(m_init, requires_grad=True) + W = Tensor(W_init, requires_grad=True) + tmp = x.mul(m) + mm = tmp.matmul(W) + out = mm.relu() + out = out.sum() + #out.backward() + assert x.grad is None + assert m.grad is None + assert tmp.grad is None + assert mm.grad is None + assert W.grad is None + assert W.requires_grad + + def test_no_grad_mode_context_manager(self): + x = Tensor(x_init, requires_grad=True) + m = Tensor(m_init, requires_grad=True) + W = Tensor(W_init, requires_grad=True) + def f(x, m, W): + tmp = x.mul(m) + mm = tmp.matmul(W) + out = mm.relu() + out = out.sum() + #out.backward() + assert x.grad is None + assert m.grad is None + assert tmp.grad is None + assert mm.grad is None + assert W.grad is None + f(x, m, W) + +class TestTensorMetadata(unittest.TestCase): + def setUp(self) -> None: _METADATA.set(None) + + # NOOPs are not included in kernel metadata + @unittest.skip("why would this be true?") + def test_exclude_noop_metadata(self): + a = Tensor.rand(4, 4)*1 + self.assertEqual(a.uop.metadata[0].name, "__mul__") + k = a.schedule()[-1] + self.assertEqual([m.name for m in k.metadata], ["rand"]) + + # we exclude const from kernel metadata because tensor methods can share the same CONST UOp + @unittest.skip("TODO: flaky") + def test_exclude_const_metadata(self): + a = Tensor.arange(4) + b = Tensor.full((4,), -1, dtype=dtypes.int).contiguous() + sched = Tensor.schedule(a, b) + self.assertEqual([m.name for m in sched[0].metadata], ["arange"]) + self.assertEqual([m.name for m in sched[1].metadata], ["contiguous"]) + + def test_matmul(self): + x = Tensor.rand(3, requires_grad=True) + W = Tensor.rand(3, 3, requires_grad=True) + out = x.matmul(W) + self.assertEqual(out.uop.metadata[0].name, "matmul") + si = out.schedule()[-1] + self.assertEqual(len(si.metadata), 1) + self.assertEqual(si.metadata[0].name, "matmul") + + def test_relu(self): + x = Tensor.rand(3, requires_grad=True) + out = x.relu() + self.assertEqual(out.uop.metadata[0].name, "relu") + si = out.schedule()[-1] + self.assertEqual(len(si.metadata), 1) + self.assertEqual(si.metadata[0].name, "relu") + + def test_complex(self): + x = Tensor.rand(3, requires_grad=True) + y = Tensor.rand(3, requires_grad=True) + out = x.relu() * y.sigmoid() + self.assertEqual(out.uop.metadata[0].name, "__mul__") + self.assertEqual(out.uop.src[0].metadata[0].name, "relu") + self.assertEqual(out.uop.src[1].metadata[0].name, "sigmoid") + si = out.schedule()[-1] + self.assertEqual(len(si.metadata), 3) + self.assertEqual(set(m.name for m in si.metadata), {"relu", "sigmoid", "__mul__"}) + + def test_complex_backward(self): + x = Tensor.rand(3, requires_grad=True).realize() + y = Tensor.rand(3, requires_grad=True).realize() + out = (x.relu() * y.sigmoid()).sum() + self.assertEqual(out.uop.metadata[0].name, "sum") + out.backward() + self.assertEqual(x.grad.uop.metadata[0].name, "relu") + self.assertTrue(x.grad.uop.metadata[0].backward) + self.assertEqual(y.grad.uop.metadata[0].name, "sigmoid") + self.assertTrue(y.grad.uop.metadata[0].backward) + si = Tensor.schedule(out, x.grad, y.grad)[-1] + self.assertEqual(len(si.metadata), 4, f"failed with {si.metadata}") + self.assertSetEqual(set(m.name for m in si.metadata), {"sigmoid", "__mul__", "relu"}) + bw = [m for m in si.metadata if m.backward] + self.assertEqual(len(bw), 2) + self.assertEqual(bw[0].name, "sigmoid") + +class TestIdxUpcast(unittest.TestCase): + def _find_op(self, ast: UOp, op: Ops): + if ast.op is op: return ast + for src in ast.src: + if (ret:=self._find_op(src, op)) is not None: return ret + def _schedule_render(self, a: Tensor): + schedule, _ = a.schedule_with_vars() + for s in schedule: + if s.ast.op is Ops.SINK: + renderer = Device[s.bufs[0].device].renderer + uops = full_rewrite(s.ast, renderer) + renderer.render(uops) + return uops + + def _assert(self, dtype: DType, a: Tensor): + uops = self._schedule_render(a) + # Assert the dtype of the INDEX value, This will need be updated if UOp spec changes + store = next(uop for uop in uops if uop.op is Ops.STORE) + assert store.op is Ops.STORE + idx = self._find_op(store, Ops.INDEX) + if idx is not None: # PTX turns Ops.INDEX into pointer arithmetic earlier than cstyle, plus it's already cast to int64 + assert idx.op is Ops.INDEX + idx_val = idx.src[1] + assert idx_val.dtype is dtype + + # use expand to generate kernel that uses large idx + def do_op_then_assert(self, dtype: DType, dim1, dim2, dim3): + self._assert(dtype, Tensor.empty(dim1, dim2, 1).expand(-1, -1, dim3).contiguous()) + + @unittest.skipUnless(is_dtype_supported(dtypes.long), "int64 is supported") + def test_overflow(self): + # 2**11, 2**11, 2**11 -> 2**33 will overflow when indexed + self.do_op_then_assert(dtypes.long, 2048, 2048, 2048) + + @unittest.skipUnless(is_dtype_supported(dtypes.long), "int64 is supported") + def test_overflow_sym(self): + self.do_op_then_assert(dtypes.long, 2048, 2048, UOp.variable("dim3", 0, 2048).bind(32)) + + def test_regular(self): + self.do_op_then_assert(dtypes.int, 64, 64, 64) + + def test_regular_sym(self): + self.do_op_then_assert(dtypes.int, 2048, 2048, UOp.variable("dim3", 0, 64).bind(32)) + + @unittest.skipIf(PTX, "PTX always convert Ops.INDEX to int64") + def test_symfold(self): + # This would cause an overflow, but after sym fold it's within int32 + a = Tensor.arange(65535) + uops = self._schedule_render(a) + assert all(uop.dtype is not dtypes.long for uop in uops) + + @unittest.skipIf(is_dtype_supported(dtypes.long), "int64 is supported") + def test_int64_unsupported_overflow_sym(self): + with self.assertRaises(KeyError): + self.do_op_then_assert(dtypes.long, 2048, 2048, UOp.variable("dim3", 0, 2048).bind(32)) + + @unittest.skipIf(is_dtype_supported(dtypes.long), "int64 is supported") + def test_int64_unsupported_overflow(self): + with self.assertRaises(KeyError): + self.do_op_then_assert(dtypes.long, 2048, 2048, 2048) + + @unittest.skip("This is kept for reference, it requires large memory to run") + def test_overflow_kernel_run(self): + # This creates a total of 2**31+10 elements, requiring at least 2147 MB memory to run + # Modified example from issue 3271 + a = Tensor.empty(2**11, 2**11, 1, dtype=dtypes.int8).permute((2, 0, 1)).expand((2**9+10, -1, -1)).contiguous() + a.realize() + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_tensor_data.py b/tinygrad_repo/test/test_tensor_data.py new file mode 100644 index 000000000..214a89d5a --- /dev/null +++ b/tinygrad_repo/test/test_tensor_data.py @@ -0,0 +1,82 @@ +import unittest, struct +from tinygrad import Tensor, dtypes + +# format types: https://docs.python.org/3/library/struct.html + +class TestTensorBytes(unittest.TestCase): + def test_bytes(self): + lst = Tensor(bytes(b"\xaa\xbb\xcc\xdd")) + assert lst.tolist() == [170, 187, 204, 221] + + def test_float_bytes(self): + lst = Tensor(bytes(struct.pack("ff", 0.234, 0.8585)), dtype=dtypes.float32) + assert lst.shape == (2,) + assert abs(lst.tolist()[0] - 0.234) < 1e-6 + assert abs(lst.tolist()[1] - 0.8585) < 1e-6 + +class TestTensorData(unittest.TestCase): + def test_data(self): + a = Tensor([1,2,3,4], dtype=dtypes.int32) + dat = a.data() + assert dat.itemsize == 4 + assert list(dat) == [1,2,3,4] + assert dat.shape == (4,) + assert dat[0] == 1 + assert dat[1] == 2 + + def test_data_empty(self): + a = Tensor([], dtype=dtypes.int32) + dat = a.data() + assert dat.itemsize == 4 + assert list(dat) == [] + assert dat.shape == (0,) + + def test_data_empty_multi_dim(self): + a = Tensor([], dtype=dtypes.int32).reshape(0, 2) + dat = a.data() + assert dat.itemsize == 4 + assert list(dat) == [] + assert dat.shape == (0,) + + def test_data_uint8(self): + a = Tensor([1,2,3,4], dtype=dtypes.uint8) + dat = a.data() + assert dat.format == "B" + assert dat.itemsize == 1 + assert dat[0] == 1 + assert dat[1] == 2 + + def test_data_nested(self): + a = Tensor([[1,2],[3,4]], dtype=dtypes.int32) + dat = a.data() + assert dat.format == "i" + assert dat.itemsize == 4 + assert dat.tolist() == [[1, 2], [3, 4]] + assert dat.shape == (2,2) + assert dat[0, 0] == 1 + assert dat[1, 1] == 4 + + def test_data_const(self): + a = Tensor(3, dtype=dtypes.int32) + dat = a.data() + assert dat.format == "i" + assert dat.itemsize == 4 + assert dat.tolist() == 3 + assert dat.shape == () + + def test_data_float32(self): + a = Tensor([[1,2.5],[3,4]], dtype=dtypes.float32) + dat = a.data() + assert dat.format == "f" + assert dat[0, 1] == 2.5 + + @unittest.skip("requires python 3.12") + def test_data_float16(self): + a = Tensor([[1,2.5],[3,4]], dtype=dtypes.float16) + dat = a.data() + assert dat.format == "e" + assert dat.shape == (2,2) + # NOTE: python can't deref float16 + +if __name__ == '__main__': + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/test_tensor_uop.py b/tinygrad_repo/test/test_tensor_uop.py new file mode 100644 index 000000000..19541ead3 --- /dev/null +++ b/tinygrad_repo/test/test_tensor_uop.py @@ -0,0 +1,121 @@ +#!/usr/bin/env python +import numpy as np +import unittest +from tinygrad import Tensor, Device, dtypes +from tinygrad.engine.realize import run_schedule +from tinygrad.uop.ops import Ops, UOp, UPat + +class TestTensorUOp(unittest.TestCase): + def test_fromcpu_shape_tracker(self): + def helper(a: np.ndarray): + print(a.shape, a.strides, a.flags.c_contiguous) + b = Tensor(a).uop + #assert b.st.contiguous == a.flags.c_contiguous + assert b.st.shape == a.shape + np.testing.assert_equal(a, Tensor(b).numpy()) + + for ndims in range(1, 4): + a = np.random.randn(*(4,)*ndims).astype(np.float32) + for stride in [-2, 1, 2]: + for start in [0, 1]: + helper(a[(slice(start, None, stride),)*ndims]) + + def test_shuffle_pad_ops_cmpeq(self): + y = Tensor([1]).cat(Tensor([1]) == 0).numpy() + z = Tensor([1, 0]).numpy() + np.testing.assert_allclose(y, z) + + def test_shuffle_pad_ops_div(self): + y = Tensor([1]).cat(Tensor([1]).div(Tensor([2.0]))).numpy() + z = Tensor([1, 0.5]).numpy() + np.testing.assert_allclose(y, z) + + def test_shuffle_pad_ops_log(self): + y = Tensor([1]).cat(Tensor([1]).log()).numpy() + z = Tensor([1, 0]).numpy() + np.testing.assert_allclose(y, z) + + def test_shuffle_pad_ops_exp(self): + y = Tensor([1]).cat(Tensor([1]).exp()).numpy() + z = Tensor([1, np.e]).numpy() + np.testing.assert_allclose(y, z) + + def test_device_0_is_the_same_device(self): + a = Tensor([1, 2, 3], f"{Device.DEFAULT}") + b = Tensor([1, 2, 3], f"{Device.DEFAULT}:0") + assert a.device == b.device + + def test_shrink_const_into_zero(self): + # regression test to make sure the shapetracker is preserved + a = Tensor.zeros(4,4,4).shrink((None, (0,0), None)) + b = Tensor.zeros(4,1,4) + c = a.cat(b, dim=1) + np.testing.assert_allclose(c.numpy(), np.concatenate((a.numpy(), b.numpy()), axis=1)) + + def test_shrink_const_then_cast(self): + # regression test to make sure the shapetracker is preserved + a = Tensor.zeros(4,4,4).shrink((None, (0,0), None)).cast(dtypes.int32) + b = Tensor.zeros(4,1,4) + c = a.cat(b, dim=1) + np.testing.assert_allclose(c.numpy(), np.concatenate((a.numpy(), b.numpy()), axis=1)) + + def test_const_dtype(self): + lb: UOp = Tensor([1], dtype=dtypes.int).uop + assert lb.const_like(1).base.arg == 1 + assert type(lb.const_like(1).base.arg) is int + + lb: UOp = Tensor([1], dtype=dtypes.float).uop + assert lb.const_like(1).base.arg == 1.0 + assert type(lb.const_like(1).base.arg) is float + + def test_contiguous_alu(self): + a = Tensor.randn(2, 2).realize() + b = Tensor.randn(2, 2).realize() + add = (a+b).contiguous() + out = add+2 + sched = out.schedule() + self.assertEqual(len(sched), 2) + run_schedule(sched) + np.testing.assert_allclose(out.numpy(), a.numpy()+b.numpy()+2) + + # NOTE: contiguous on a buffer collapses + def test_contiguous_empty(self): + empty = Tensor.empty(1).contiguous() + sched = empty.schedule() + self.assertEqual(len(sched), 0) + + def test_contiguous_folded_alu(self): + a = Tensor.empty(8, 8) + # NOTE: the buffer for mul_0 late folds to just a CONST + mul_0 = a*0 + out = mul_0.shrink(((4, 8), (0, 8))).contiguous() + out.realize() + self.assertEqual(out.tolist(), Tensor.zeros(4, 8).tolist()) + +reduce_kernel = UPat(Ops.SINK, src=(UPat(Ops.STORE, src=(UPat(), UPat(Ops.REDUCE_AXIS))))) +class TestReduceOp(unittest.TestCase): + def test_no_split_reduce_kernel(self): + a = Tensor.rand(4, 4).realize() + a = a.sum() + sched = a.schedule() + assert len(sched) == 1 + assert reduce_kernel.match(sched[0].ast, {}) + + def test_split_reduce_kernel_dim0(self): + a = Tensor.rand(256, 255).realize() + a = a.sum() + sched = a.schedule() + assert len(sched) == 2 + for s in sched: + assert reduce_kernel.match(s.ast, {}) + + def test_split_reduce_kernel_dim1(self): + a = Tensor.rand(255, 256).realize() + a = a.sum() + sched = a.schedule() + assert len(sched) == 2 + for s in sched: + assert reduce_kernel.match(s.ast, {}) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/test_tensor_variable.py b/tinygrad_repo/test/test_tensor_variable.py new file mode 100644 index 000000000..a680cf9a6 --- /dev/null +++ b/tinygrad_repo/test/test_tensor_variable.py @@ -0,0 +1,96 @@ +import unittest +import numpy as np +from tinygrad import Tensor, Variable +from tinygrad.helpers import Context + +class TestTensorVariable(unittest.TestCase): + def test_add_tvar(self): + vv = Variable("a", 0, 10).bind(1) + ret = (Tensor(vv) + 3).item() + assert ret == 4 + + def test_inner_tvar_node(self): + vv = Variable("w", 0, 10).bind(2) + ret = Tensor.from_uop(vv * 4).item() + assert ret == 8 + + def test_inner_tvar_mul(self): + vv = Variable("w", 0, 10).bind(2) + assert (Tensor(3) * vv).item() == 6 + + def test_inner_tvar_mul_node(self): + vv = Variable("w", 0, 10).bind(2) + assert (Tensor(3) * (vv * 4)).item() == 24 + + def test_symbolic_mean(self): + with Context(IGNORE_OOB=1): + vv = Variable("a", 1, 10).bind(2) + t = Tensor.ones(2, 2).contiguous().reshape(2, vv) + ret = t.mean().item() + assert ret == 1 + + def test_symbolic_mean_2d(self): + with Context(IGNORE_OOB=1): + vv = Variable("a", 1, 10).bind(2) + vv2 = Variable("b", 1, 10).bind(2) + t = Tensor.ones(2, 2).contiguous().reshape(vv2, vv) + ret = t.mean().item() + assert ret == 1 + + def test_symbolic_mean_2d_axis_1(self): + with Context(IGNORE_OOB=1): + vv = Variable("a", 1, 10).bind(2) + vv2 = Variable("b", 1, 10).bind(2) + t = Tensor.ones(2, 2).contiguous().reshape(vv2, vv) + ret = t.mean(axis=1).reshape(2, 1).numpy() + assert np.all(ret == 1) + + def test_symbolic_mean_2d_add(self): + with Context(IGNORE_OOB=1): + add_term = Variable("c", 0, 10).bind(1) + vv = Variable("a", 1, 10).bind(1) + vv2 = Variable("b", 1, 10).bind(1) + t = Tensor.ones(2, 2).contiguous().reshape(vv2+add_term, vv+add_term) + ret = t.mean().item() + assert ret == 1 + + def test_symbolic_var(self): + with Context(IGNORE_OOB=1): + vv = Variable("a", 1, 10).bind(2) + t = Tensor.ones(2, 2).contiguous().reshape(2, vv) + ret = t.var().item() + assert ret == 0 + + def test_symbolic_pad(self): + vv = Variable("a", 1, 10).bind(2) + t = Tensor.ones(2, 2).contiguous() + t = t.pad([vv, vv, vv, vv]).mean() + ones = 4 + zeros = 6+6+4+4+6+6 + self.assertAlmostEqual(t.item(), ones/(ones+zeros)) + + def test_symbolic_arange(self): + vv = Variable("a", 1, 10) + ret = Tensor.arange(0, vv.bind(4)) + self.assertListEqual(ret.reshape(4).tolist(), [0,1,2,3]) + + def test_symbolic_arange_sym_start(self): + vv = Variable("a", 1, 6) + ret = Tensor.arange(vv.bind(4), 7) + self.assertListEqual(ret.reshape(3).tolist(), [4,5,6]) + + # TODO: add vmin/vmax pattern for symbolic denominator + @unittest.expectedFailure + def test_symbolic_arange_sym_step(self): + vv = Variable("step", 1, 3) + ret = Tensor.arange(0, 10, vv.bind(2)) + self.assertListEqual(ret.reshape(5).tolist(), [0,2,4,6,8]) + + def test_symbolic_arange_two_vars(self): + begin = Variable("b", 1, 5) + end = Variable("e", 6, 10) + ret = Tensor.arange(begin.bind(4), end.bind(7)) + self.assertListEqual(ret.reshape(3).tolist(), [4,5,6]) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_tiny.py b/tinygrad_repo/test/test_tiny.py new file mode 100644 index 000000000..a38c7ed62 --- /dev/null +++ b/tinygrad_repo/test/test_tiny.py @@ -0,0 +1,119 @@ +# basic self-contained tests of the external functionality of tinygrad +import unittest, random +from tinygrad import Tensor, Context, Variable, TinyJit, dtypes, Device, nn +from tinygrad.helpers import IMAGE, CI + +class TestTiny(unittest.TestCase): + + # *** basic functionality *** + + def test_plus(self): + out = Tensor([1.,2,3]) + Tensor([4.,5,6]) + self.assertListEqual(out.tolist(), [5.0, 7.0, 9.0]) + + def test_plus_int(self): + out = Tensor([1,2,3], dtype=dtypes.int) + Tensor([4,5,6], dtype=dtypes.int) + self.assertListEqual(out.tolist(), [5, 7, 9]) + + def test_plus_big(self): + out = Tensor.ones(16).contiguous() + Tensor.ones(16).contiguous() + self.assertListEqual(out.tolist(), [2]*16) + + def test_cat(self): + out = Tensor.cat(Tensor.ones(8).contiguous(), Tensor.ones(8).contiguous()) + self.assertListEqual(out.tolist(), [1]*16) + + def test_sum(self): + out = Tensor.ones(256).contiguous().sum() + self.assertEqual(out.item(), 256) + + def test_gemm(self, N=64, out_dtype=dtypes.float): + a = Tensor.ones(N,N).contiguous() + b = Tensor.eye(N).contiguous() + self.assertListEqual((out:=a@b).flatten().tolist(), [1.0]*(N*N)) + if IMAGE < 2: self.assertEqual(out.dtype, out_dtype) + + # *** randomness *** + + def test_random(self): + out = Tensor.rand(10) + for x in out.tolist(): + self.assertGreaterEqual(x, 0.0) + self.assertLessEqual(x, 1.0) + + # *** JIT (for Python speed) *** + + def test_jit(self): + cnt = 0 + random.seed(0) + def new_rand_list(ln=10): return [random.randint(0, 100000) for _ in range(ln)] + + @TinyJit + def fxn(a,b) -> Tensor: + nonlocal cnt + cnt += 1 + return a+b + + for _ in range(3): + la,lb = new_rand_list(), new_rand_list() + fa,fb = Tensor(la), Tensor(lb) + ret = fxn(fa, fb) + # math is correct + self.assertListEqual(ret.tolist(), [a+b for a,b in zip(la, lb)]) + + # function is only called twice + self.assertEqual(cnt, 2) + + # *** BEAM (for Kernel speed) *** + + def test_beam(self): + with Context(BEAM=1, IGNORE_BEAM_CACHE=1): self.test_plus() + + # *** symbolic (to allow less recompilation) *** + + def test_symbolic(self): + i = Variable('i', 1, 10) + with Context(IGNORE_OOB=1): + for s in [2,5]: + ret = Tensor.ones(s).contiguous().reshape(i.bind(s)) + 1 + self.assertListEqual(ret.reshape(s).tolist(), [2.0]*s) + + def test_symbolic_reduce(self): + i = Variable('i', 1, 10) + with Context(IGNORE_OOB=1): + for s in [2,5]: + ret = Tensor.ones(s).contiguous().reshape(i.bind(s)).sum() + self.assertEqual(ret.item(), s) + + # *** a model *** + + # TODO: this is failing because of how swizzling rewrites the ShapeTracker of the final STORE + @unittest.skipIf(IMAGE>0 or (CI and Device.DEFAULT == "DSP"), "failing because of make things that can't be images not images") + def test_mnist(self): + layers = [ + nn.Conv2d(1, 32, 5), Tensor.relu, + nn.Conv2d(32, 32, 5), Tensor.relu, + nn.BatchNorm(32), Tensor.max_pool2d, + nn.Conv2d(32, 64, 3), Tensor.relu, + nn.Conv2d(64, 64, 3), Tensor.relu, + nn.BatchNorm(64), Tensor.max_pool2d, + lambda x: x.flatten(1), nn.Linear(576, 10)] + + # replace random weights with ones + Tensor.realize(*[p.replace(Tensor.ones_like(p).contiguous()) for p in nn.state.get_parameters(layers)]) + + # run model inference + probs = Tensor.rand(1, 1, 28, 28).sequential(layers).tolist() + self.assertEqual(len(probs[0]), 10) + + # *** image *** + + @unittest.skipIf(Device.DEFAULT != "GPU", "image only supported on GPU") + def test_image(self): + with Context(IMAGE=2): self.test_gemm(N=4, out_dtype=dtypes.imagef((4, 1, 4))) + + def test_beam_image(self): + with Context(BEAM=1, IGNORE_BEAM_CACHE=1): self.test_image() + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_to_numpy.py b/tinygrad_repo/test/test_to_numpy.py new file mode 100644 index 000000000..deaa9fc9f --- /dev/null +++ b/tinygrad_repo/test/test_to_numpy.py @@ -0,0 +1,17 @@ +from tinygrad.tensor import Tensor +import numpy as np +import pickle +import unittest + +class TestToNumpy(unittest.TestCase): + def test_numpy_is_numpy(self): + output = Tensor.ones((1, 3, 4096)).realize().numpy() + new = np.copy(output) + print(type(new)) + serialized = pickle.dumps(new) + out = pickle.loads(serialized) + assert out.shape == (1,3,4096) + assert (out==1).all() + +if __name__ == '__main__': + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/test_transcendental.py b/tinygrad_repo/test/test_transcendental.py new file mode 100644 index 000000000..932cfa293 --- /dev/null +++ b/tinygrad_repo/test/test_transcendental.py @@ -0,0 +1,163 @@ +import unittest +from tinygrad import Tensor, Device, dtypes +from tinygrad.tensor import _to_np_dtype +from tinygrad.helpers import Context, getenv, CI, OSX +from test.test_schedule import check_schedule +from test.test_dtype_alu import ht, dtypes_float +from tinygrad.device import is_dtype_supported +import numpy as np +import math +from hypothesis import given, settings, strategies as strat + +settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) +settings.load_profile("my_profile") + +class TestTranscendentalMath(unittest.TestCase): + @unittest.skipUnless(is_dtype_supported(dtypes.float64, Device.DEFAULT), f"no float64 on {Device.DEFAULT}") + @unittest.skipIf(getenv("MOCKGPU") and Device.DEFAULT in {"NV", "CUDA"}, "crashed") + @given(ht.float64, strat.sampled_from([(Tensor.exp, np.exp), (Tensor.log, np.log), (Tensor.sin, np.sin)])) + def test_float64(self, x, op): + if op[0] == Tensor.sin: + # TODO: reduction does not work # 536870912.125 # 2914593.01171875 # 134217728.03125 # 230581075.65625 # 139216373.71875 + if abs(x) > 100_000_000: return + with Context(TRANSCENDENTAL=2), np.errstate(all='ignore'): + np.testing.assert_allclose(op[0](Tensor([x], dtype=dtypes.float64)).numpy(), + op[1](np.array([x], dtype=_to_np_dtype(dtypes.float64))), + atol=3e-2, rtol=1e-5) # sin can have bigger atol for very big x + + @unittest.skipIf(getenv("MOCKGPU") and Device.DEFAULT in {"NV", "CUDA"}, "crashed") + @given(ht.float32, strat.sampled_from([(Tensor.exp, np.exp),(Tensor.log, np.log)] + + ([(Tensor.sin, np.sin)] if is_dtype_supported(dtypes.ulong) else []))) + def test_float32(self, x, op): + # wrong nan behavior on Vulkan + if (math.isnan(x) or (x < 0 and op[0] == Tensor.log)) and CI and Device.DEFAULT == "WEBGPU" and not OSX: return + with Context(TRANSCENDENTAL=2), np.errstate(all='ignore'): + np.testing.assert_allclose(op[0](Tensor([x], dtype=dtypes.float32)).numpy(), + op[1](np.array([x], dtype=_to_np_dtype(dtypes.float32))), + atol=2e-5, rtol=1e-5) + + @unittest.skipUnless(is_dtype_supported(dtypes.float16, Device.DEFAULT), f"no float16 on {Device.DEFAULT}") + @given(ht.float16, strat.sampled_from([(Tensor.exp, np.exp),(Tensor.log, np.log)] + + ([(Tensor.sin, np.sin)] if is_dtype_supported(dtypes.ulong) else []))) + def test_float16(self, x, op): + # wrong nan behavior on Vulkan + if (math.isnan(x) or (x < 0 and op[0] == Tensor.log)) and CI and Device.DEFAULT == "WEBGPU" and not OSX: return + with Context(TRANSCENDENTAL=2), np.errstate(all='ignore'): + np.testing.assert_allclose(op[0](Tensor([x], dtype=dtypes.float16)).numpy(), + op[1](np.array([x], dtype=_to_np_dtype(dtypes.float16))), + atol=1e-2, rtol=5e-3) # exp can have bigger rtol + + @given(strat.sampled_from([(dtypes.float64, 709.5), (dtypes.float32, 88.7), (dtypes.float16, 11)])) + def test_exp_near_inf(self, dtype_x): + # reordering compute might return inf + dtype, x = dtype_x + if not is_dtype_supported(dtype): return + with Context(TRANSCENDENTAL=2): + y = Tensor([x], dtype=dtype).exp().numpy() + expected = np.exp(np.array([x], dtype=_to_np_dtype(dtype))) + np.testing.assert_allclose(y, expected, rtol=5e-3) + +class TestFromFuzzer(unittest.TestCase): + @given(strat.sampled_from(dtypes_float)) + @unittest.skipUnless(is_dtype_supported(dtypes.ulong), "Needs ulong") + def test_sin(self, dtype): + if not is_dtype_supported(dtype): return + if dtype == dtypes.float64: + # crashes in CI CUDA + if getenv("MOCKGPU") and Device.DEFAULT in {"NV", "CUDA"}: return + def _test_value(n: float, unit: float=1.0): + next_float = np.nextafter(1.0, 2.0, dtype=_to_np_dtype(dtype)) + ulp = next_float - 1.0 + ulp = unit * ulp + with Context(TRANSCENDENTAL=2): + np.testing.assert_allclose(Tensor([n], dtype=dtype).sin().numpy(), np.sin(np.array([n], dtype=_to_np_dtype(dtype))), atol=ulp, rtol=1e-5) + _test_value(-35.0) + _test_value(-25.0) + _test_value(25.0) + _test_value(30.0) # 30.0 == switch_over + _test_value(35.0) + _test_value(0.0) + _test_value(np.pi / 2) + # worst case of ulp 1.5 + _test_value(np.pi * 2, unit=1.5) + + @given(strat.sampled_from(dtypes_float)) + @unittest.skipIf(Device.DEFAULT == "WEBGPU" and CI, "Nan location mismatch on Vulkan, Metal works") + def test_log2(self, dtype): + if not is_dtype_supported(dtype): return + if dtype == dtypes.float64: + # crashes in CI CUDA + if getenv("MOCKGPU") and Device.DEFAULT in {"NV", "CUDA"}: return + def _test_value(n: float, unit: float=1.0): + next_float = np.nextafter(1.0, 2.0, dtype=_to_np_dtype(dtype)) + ulp = next_float - 1.0 + ulp = unit * ulp + with Context(TRANSCENDENTAL=2): + np.testing.assert_allclose(Tensor([n], dtype=dtype).log2().numpy(), np.log2(np.array([n], dtype=_to_np_dtype(dtype))), atol=ulp, rtol=1e-5) + fmin = np.finfo(_to_np_dtype(dtype)).tiny + for scale in [1.0, 1e10, 1e20, 1e30]: + _test_value(fmin * scale) + _test_value(-fmin * scale) + _test_value(0) + _test_value(0.0000009) + +class TestTranscendentalSchedule(unittest.TestCase): + @unittest.skipUnless(is_dtype_supported(dtypes.ulong), "Needs ulong") + def test_transcendental_sin_fusion(self): + with Context(TRANSCENDENTAL=2): + a = Tensor.empty(10) + b = Tensor.empty(10) + c = a.sin() + b.sin() + c = c.sin() + check_schedule(c, 1) + + def test_transcendental_log2_fusion(self): + with Context(TRANSCENDENTAL=2): + a = Tensor.empty(10) + b = Tensor.empty(10) + c = a.log2() + b.log2() + c = c.log2() + check_schedule(c, 1) + + def test_transcendental_exp2_fusion(self): + with Context(TRANSCENDENTAL=2): + a = Tensor.empty(10) + b = Tensor.empty(10) + c = a.exp2() + b.exp2() + c = c.exp2() + check_schedule(c, 1) + +class TestTranscendentalVectorized(unittest.TestCase): + def _vectorized_data(self, low, high, vec_size): + np_data = np.linspace(low, high, num=(128 // vec_size) * vec_size, dtype=np.float32).reshape(-1, vec_size) + data = Tensor(np_data, dtype=dtypes.float32.vec(vec_size)) + return data, np_data + + def _test_vectorized_op(self, fxn, np_fxn, data_range, vec_size, param_range=None): + data, np_data = self._vectorized_data(data_range[0], data_range[1], vec_size) + if param_range: + param, np_param = self._vectorized_data(param_range[0], param_range[1], vec_size) + out, np_out = fxn(data, param), np_fxn(np_data, np_param) + else: + out, np_out = fxn(data), np_fxn(np_data) + np.testing.assert_allclose(out.numpy(), np_out, rtol=1e-4) + + def test_exp2_vectorized(self): + for vec_size in [1,2,3,4,5,127,128]: self._test_vectorized_op(Tensor.exp2, np.exp2, (-100, 100), vec_size) + + def test_log2_vectorized(self): + for vec_size in [1,2,3,4,5,127,128]: self._test_vectorized_op(Tensor.log2, np.log2, (0.001, 200), vec_size) + + @unittest.skipIf(getenv("DSP"), "requires int division") + def test_sin_vectorized(self): + for vec_size in [1,2,3,4,5,127,128]: self._test_vectorized_op(Tensor.sin, np.sin, (-100, 100), vec_size) + + def test_pow_vectorized(self): + # np.pow returns nan for negative values raised to a non-integral power + for vec_size in [1,2,3,4,5,127,128]: self._test_vectorized_op(Tensor.pow, np.pow, (0.001, 200), vec_size, param_range=(-10, 10)) + + def test_sqrt_vectorized(self): + for vec_size in [1,2,3,4,5,127,128]: self._test_vectorized_op(Tensor.sqrt, np.sqrt, (0, 100), vec_size) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/test_uop_graph.py b/tinygrad_repo/test/test_uop_graph.py new file mode 100644 index 000000000..7ea59f2db --- /dev/null +++ b/tinygrad_repo/test/test_uop_graph.py @@ -0,0 +1,780 @@ +from typing import List +import unittest, pytest +from tinygrad import dtypes, Variable +from tinygrad.helpers import DEBUG, Context +from tinygrad.uop.ops import Ops, UOp, UPat, PatternMatcher, track_rewrites, graph_rewrite, GroupOp +from tinygrad.uop.symbolic import sym +from tinygrad.codegen import full_rewrite, full_rewrite_to_sink +from tinygrad.codegen.expander import expander + +simple_pm = PatternMatcher([ + (UPat.cvar('x', dtypes.int), lambda x: UOp.const(dtypes.float, 1.0) + UOp.const(dtypes.float, 2.0)), + (UPat.cvar('x') + UPat.cvar('y'), lambda x,y: UOp.const(dtypes.float, x.arg+y.arg)), + (UPat.cvar('x') * UPat.cvar('y') * UPat.cvar('z'), lambda x,y,z: UOp.const(dtypes.float, x.arg*y.arg*z.arg)), + ((UPat.var('x') + UPat.cvar('c1')) + UPat.cvar('c2'), lambda x,c1,c2: x + (c1.arg+c2.arg)), +]) + +def to_uops_list(u:List[UOp]) -> List[UOp]: + # we strip the SINK here for legacy reasons + ret = full_rewrite(UOp.sink(*u)) + assert ret[-1].op is Ops.SINK + return ret[:-1] + +class TestGraphRewriteConst(unittest.TestCase): + def test_gep_const(self): + v1 = UOp.const(dtypes.int.vec(3), (0,1,2)) + v2 = v1.gep(1) + ret = graph_rewrite(v2, sym) + self.assertEqual(ret.dtype, dtypes.int) + self.assertEqual(ret.arg, 1) + + def test_gep_const_single(self): + v1 = UOp.const(dtypes.int.vec(3), 4) + v2 = v1.gep(1) + ret = graph_rewrite(v2, sym) + self.assertEqual(ret.dtype, dtypes.int) + self.assertEqual(ret.arg, 4) + + def test_add_const(self): + v1 = UOp.const(dtypes.int.vec(3), (0,1,2)) + v2 = UOp.const(dtypes.int.vec(3), (5,6,7)) + ret = graph_rewrite(v1+v2, sym) + self.assertEqual(ret.op, Ops.VCONST) + self.assertEqual(ret.dtype, dtypes.int.vec(3)) + self.assertEqual(ret.arg, (5,7,9)) + + def test_add_const_lose_v(self): + v1 = UOp.const(dtypes.int.vec(3), (0,1,2)) + v2 = UOp.const(dtypes.int.vec(3), (2,1,0)) + ret = graph_rewrite(v1+v2, sym) + self.assertEqual(ret.op, Ops.CONST) + self.assertEqual(ret.dtype, dtypes.int.vec(3)) + self.assertEqual(ret.arg, 2) + +xfail_broken_const_wraparound = pytest.mark.xfail(reason="const folding does not properly implement modular arithmetic") +class TestModularWraparound(unittest.TestCase): + def _test(self, uop:UOp, expected:int): + results = to_uops_list([uop]) + self.assertEqual(len(results), 1) + self.assertEqual(results[0].op, Ops.CONST) + self.assertEqual(results[0].dtype, uop.dtype) + self.assertEqual(results[0].arg, expected) + + @xfail_broken_const_wraparound + def test_cast(self): + t = self._test + t(UOp.const(dtypes.uint, 0xABCD17D6).cast(dtypes.uint8), 0xD6) + t(UOp.const(dtypes.uint, 0xABCD17D6).cast(dtypes.uint8).cast(dtypes.uint), 0xD6) + + @xfail_broken_const_wraparound + def test_mul(self): + t = self._test + t(UOp.const(dtypes.uint, 0xABCD17D6) * 0xAABBCCDD, 1147018174) + t(UOp.const(dtypes.int, 0xABCD17D6) * 10, -1241321892) + + @xfail_broken_const_wraparound + def test_div(self): + t = self._test + t(UOp.const(dtypes.uint, 0xABCD17D6) * 0xAABBCCDD // 11, 104274379) + t(UOp.const(dtypes.int, 0xABCD17D6) * 10 // 11, -112847444) + + @xfail_broken_const_wraparound + def test_neg(self): + t = self._test + t(-UOp.const(dtypes.uint8, 1), 0xFF) + t(-UOp.const(dtypes.uint16, 1), 0xFFFF) + t(-UOp.const(dtypes.uint32, 1), 0xFFFFFFFF) + t(-UOp.const(dtypes.uint64, 1), 0xFFFFFFFFFFFFFFFF) + + @xfail_broken_const_wraparound + def test_neg_min_int(self): + t = self._test + t(-UOp.const(dtypes.int8, -2**7), -2**7) + t(-UOp.const(dtypes.int16, -2**15), -2**15) + t(-UOp.const(dtypes.int32, -2**31), -2**31) + t(-UOp.const(dtypes.int64, -2**63), -2**63) + + @xfail_broken_const_wraparound + def test_payne_hanek_reduction_bug(self): + t = self._test + a = (UOp.const(dtypes.uint, 43748177600).cast(dtypes.uint) | 36).cast(dtypes.ulong) + b = 2536655455 * a + 4294967296 * UOp.const(dtypes.ulong, 25366554550) + c = (b + 2261737165) // 4611686018427387904 + t(c, 0) + +class TestGraphRewrite(unittest.TestCase): + def test_dedup(self): + v1 = UOp(Ops.DEFINE_VAR, dtypes.float) + v2 = UOp(Ops.DEFINE_VAR, dtypes.float) + nout = graph_rewrite(v1+v2, PatternMatcher([])) + self.assertIs(nout.src[0], nout.src[1]) + + # NOTE: this shows why we can't have a UOp in arg + @unittest.expectedFailure + def test_no_dedup_args(self): + a1 = UOp(Ops.DEFINE_VAR, dtypes.int, (), ("a1", UOp.const(dtypes.int, 0), UOp.const(dtypes.int, 11))) + a2 = UOp(Ops.DEFINE_VAR, dtypes.int, (), ("a2", UOp.const(dtypes.int, 0), UOp.const(dtypes.int, 11))) + sink = a1.sink(a2) + define_vars = [x for x in graph_rewrite(sink, PatternMatcher([])).toposort() if x.op is Ops.DEFINE_VAR] + self.assertEqual(len(define_vars), 1) + + def test_simple(self): + c1 = UOp.const(dtypes.float, 1.0) + c2 = UOp.const(dtypes.float, 2.0) + nout = graph_rewrite(c1+c2, simple_pm) + self.assertEqual(nout.op, Ops.CONST) + self.assertEqual(nout.arg, 3.0) + + def test_depth_2_late(self): + c1 = UOp.const(dtypes.float, 1.0) + c2 = UOp.const(dtypes.float, 2.0) + c3 = UOp.const(dtypes.float, 3.0) + nout = graph_rewrite(c1*c2*(c3+c3), simple_pm) + self.assertEqual(nout.op, Ops.CONST) + self.assertEqual(nout.arg, 12.0) + + def test_double(self): + c1 = UOp.const(dtypes.float, 1.0) + c2 = UOp.const(dtypes.float, 2.0) + c3 = UOp.const(dtypes.float, 3.0) + nout = graph_rewrite(c1+c2+c3, simple_pm) + self.assertEqual(nout.op, Ops.CONST) + self.assertEqual(nout.arg, 6.0) + + def test_triple(self): + c1 = UOp.const(dtypes.float, 1.0) + c2 = UOp.const(dtypes.float, 2.0) + c3 = UOp.const(dtypes.float, 3.0) + c4 = UOp.const(dtypes.float, 4.0) + nout = graph_rewrite(c1+c2+c3+c4, simple_pm) + self.assertEqual(nout.op, Ops.CONST) + self.assertEqual(nout.arg, 10.0) + + def test_diamond(self): + c1 = UOp.const(dtypes.float, 1.0) + c2 = UOp.const(dtypes.float, 2.0) + c3 = UOp.const(dtypes.float, 3.0) + nout = graph_rewrite((c1+c2)+(c1+c3), simple_pm) + self.assertEqual(nout.op, Ops.CONST) + self.assertEqual(nout.arg, 7.0) + + def test_magic_4(self): + c1 = UOp.const(dtypes.int, 4.0) + nout = graph_rewrite(c1, simple_pm) + self.assertEqual(nout.op, Ops.CONST) + self.assertEqual(nout.arg, 3.0) + + def test_depth_2_fold(self): + v = UOp(Ops.DEFINE_VAR, dtypes.float) + c1 = UOp.const(dtypes.float, 1.0) + c2 = UOp.const(dtypes.float, 2.0) + nout = graph_rewrite(v+c1+c2, simple_pm) + self.assertEqual(nout.op, Ops.ADD) + self.assertEqual(nout.src[0].op, Ops.DEFINE_VAR) + self.assertEqual(nout.src[1].op, Ops.CONST) + self.assertEqual(nout.src[1].arg, 3.0) + + def test_commutative_work(self): + a = UOp.variable('a', 0, 1) + b = UOp.variable('b', 0, 1) + self.assertIs((a+b).simplify(), (b+a).simplify()) + + def test_consts_go_last_right_away(self): + a = UOp.variable('a', 0, 1) + tst = (2+a).simplify() + self.assertIs(tst.src[0], a) + self.assertIs(tst.src[1], a.const_like(2)) + + def test_consts_go_last(self): + a = UOp.variable('a', 0, 1) + b = UOp.variable('b', 0, 1) + c = UOp.variable('c', 0, 1) + d = UOp.variable('d', 0, 1) + outs = [2+a, 2+a+d+3+b+c+4, UOp(Ops.ADD, a.dtype, src=(a.const_like(2), a)), (4+d)+c+(2+a)+b] + for out in outs: + sink = graph_rewrite(out, sym) + print(sink.render()) + self.assertEqual(sink.op, Ops.ADD) + self.assertEqual(sink.src[1].op, Ops.CONST) + self.assertEqual(len([x for x in sink.toposort() if x.op is Ops.CONST]), 1) + +class TestUOpGraph(unittest.TestCase): + def test_add_constant_fold(self): + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) + out = UOp(Ops.ADD, dtypes.float, (c1, c2)) + uops = to_uops_list([out]) + self.assertEqual(len(uops), 1) + out = uops[-1] + self.assertEqual(out.op, Ops.CONST) + self.assertEqual(out.arg, 3.0) + + def test_where_same_fold(self): + v = UOp.variable('tmp', 0, 1) + c0 = UOp(Ops.CONST, dtypes.int, arg=0) + vc = UOp(Ops.CMPNE, dtypes.bool, (v, c0)) + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + out = UOp(Ops.WHERE, dtypes.float, (vc, c1, c1)) + uops = to_uops_list([out]) + self.assertEqual(len(uops), 1) + out = uops[-1] + self.assertEqual(out.op, Ops.CONST) + self.assertEqual(out.arg, 1.0) + + def test_where_const_fold(self): + bf = UOp(Ops.CONST, dtypes.bool, arg=False) + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) + out = UOp(Ops.WHERE, dtypes.float, (bf, c1, c2)) + uops = to_uops_list([out]) + self.assertEqual(len(uops), 1) + out = uops[-1] + self.assertEqual(out.op, Ops.CONST) + self.assertEqual(out.arg, 2.0) + + def test_const_cast(self): + bf = UOp(Ops.CONST, dtypes.bool, arg=False) + out = UOp(Ops.CAST, dtypes.int, (bf,)) + uops = to_uops_list([out]) + self.assertEqual(len(uops), 1) + out = uops[-1] + self.assertEqual(out.op, Ops.CONST) + self.assertEqual(out.arg, 0) + + @unittest.skip("this test isn't valid uops") + def test_noop_vectorize_fold(self): + d0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0) + idx = UOp.const(dtypes.int, 0) + ld = UOp(Ops.LOAD, dtypes.float.vec(2), (d0, idx)) + vec = UOp(Ops.VECTORIZE, dtypes.float.vec(2), (ld,)) + x = UOp(Ops.GEP, dtypes.float, (vec, ), arg=0) + alu = UOp(Ops.SQRT, dtypes.float, (x, )) + out = UOp(Ops.STORE, dtypes.void, (d0, idx, alu)) + uops = to_uops_list([out]) + self.assertEqual(len([x for x in uops if x.op is Ops.VECTORIZE]), 0) + + def test_gep_vec_fold(self): + d0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) + d1 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 1) + d2 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 2) + idx = UOp.const(dtypes.int, 0) + def _test_vec(geps, count=4): + vec = UOp(Ops.VECTORIZE, dtypes.float.vec(count), geps) + out = UOp(Ops.STORE, dtypes.void, (d0.index(idx), vec)) + uops = to_uops_list([out]) + if DEBUG >= 4: + from tinygrad import Device + print(Device[Device.DEFAULT].renderer.render(uops)) + return uops[-1].src[-1] + + # possible + val = UOp(Ops.LOAD, dtypes.float.vec(4), (d1.index(idx),)) + xyzw = tuple(UOp(Ops.GEP, dtypes.float, (val,), (i,)) for i in range(4)) + self.assertIs(_test_vec(xyzw).op, Ops.LOAD) + + # unaligned + val = UOp(Ops.LOAD, dtypes.float.vec(4), (d1.index(idx),)) + wzyx = tuple(UOp(Ops.GEP, dtypes.float, (val,), (i,)) for i in reversed(range(4))) + self.assertIs(_test_vec(wzyx).op, Ops.VECTORIZE) + + # different_size + val = UOp(Ops.LOAD, dtypes.float.vec(2), (d1.index(idx),)) + xy = tuple(UOp(Ops.GEP, dtypes.float, (val, ), (i,)) for i in range(2)) + self.assertIs(_test_vec(xy+xy).op, Ops.VECTORIZE) + val = UOp(Ops.LOAD, dtypes.float.vec(4), (d1.index(idx),)) + xy = tuple(UOp(Ops.GEP, dtypes.float, (val, ), (i,)) for i in range(2)) + self.assertIs(_test_vec(xy, count=2).op, Ops.VECTORIZE) + + # different vals + val1 = UOp(Ops.LOAD, dtypes.float.vec(2), (d1.index(idx),)) + val2 = UOp(Ops.LOAD, dtypes.float.vec(2), (d2.index(idx),)) + xy1 = tuple(UOp(Ops.GEP, dtypes.float, (val1, ), (i,)) for i in range(2)) + xy2 = tuple(UOp(Ops.GEP, dtypes.float, (val2, ), (i,)) for i in range(2)) + self.assertIs(_test_vec(xy1+xy2).op, Ops.VECTORIZE) + + def test_gep_vec_const_fold(self): + for vec_size in [2, 4, 8]: + consts = [UOp.const(dtypes.float, float(i)) for i in range(vec_size)] + vec = UOp(Ops.VECTORIZE, dtypes.float.vec(vec_size), tuple(consts)) + uops = to_uops_list([UOp(Ops.GEP, dtypes.float, (vec,), (i,)) for i in range(vec_size)]) + for uop, const in zip(uops, consts): + self.assertEqual(uop, const) + + def test_wmma_vectorize_fold(self): + for i in [2, 4, 8]: + vec = UOp(Ops.VECTORIZE, dtypes.half.vec(i), tuple(UOp.const(dtypes.half, 0.0) for _ in range(i))) + var = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i)) + acc = UOp.variable('acc', 0, 1, dtypes.half.vec(i)) + wmma = UOp(Ops.WMMA, dtypes.half.vec(i), (vec, var, acc)) + uops = to_uops_list([wmma]) + self.assertEqual(uops[0], acc) + self.assertEqual(len(uops), 1) + + for i in [2, 4, 8]: + var = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i)) + vec = UOp(Ops.VECTORIZE, dtypes.half.vec(i), tuple(UOp.const(dtypes.half, 0.0) for _ in range(i))) + acc = UOp.variable('acc', 0, 1, dtypes.half.vec(i)) + wmma = UOp(Ops.WMMA, dtypes.half.vec(i), (var, vec, acc)) + uops = to_uops_list([wmma]) + self.assertEqual(uops[0], acc) + self.assertEqual(len(uops), 1) + + @unittest.skip("wmma is wrong here, it needs an arg") + def test_wmma_vectorize_no_fold(self): + for i in [4, 8]: + vec = UOp(Ops.VECTORIZE, dtypes.half.vec(i), + tuple(UOp.const(dtypes.half, 0.0) for _ in range(i//2)) + + tuple(UOp(Ops.DEFINE_VAR, dtypes.half, arg=(f'tmp{j}', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) for j in range(i//2))) + var = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=(f'tmp{i}', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) + acc = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=('acc', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) + wmma = UOp(Ops.WMMA, dtypes.half.vec(i), (vec, var, acc)) + uops = to_uops_list([wmma]) + self.assertEqual(uops[-1], wmma) + + for i in [4, 8]: + var = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=(f'tmp{i}', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) + vec = UOp(Ops.VECTORIZE, dtypes.half.vec(i), + tuple(UOp.const(dtypes.half, 0.0) for _ in range(i//2)) + + tuple(UOp(Ops.DEFINE_VAR, dtypes.half, arg=(f'tmp{j}', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) for j in range(i//2))) + acc = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=('acc', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) + wmma = UOp(Ops.WMMA, dtypes.half.vec(i), (var, vec, acc)) + uops = to_uops_list([wmma]) + self.assertEqual(uops[-1], wmma) + + for i in [2, 4, 8]: + vec = UOp(Ops.VECTORIZE, dtypes.half.vec(i), + tuple(UOp.const(dtypes.half, 1.0 if j == 0 else 0.0) for j in range(i))) + var = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=(f'tmp{i}', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) + acc = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=('acc', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) + wmma = UOp(Ops.WMMA, dtypes.half.vec(i), (vec, var, acc)) + uops = to_uops_list([wmma]) + self.assertEqual(uops[-1], wmma) + + for i in [2, 4, 8]: + var = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=(f'tmp{i}', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) + vec = UOp(Ops.VECTORIZE, dtypes.half.vec(i), + tuple(UOp.const(dtypes.half, 1.0 if j == 0 else 0.0) for j in range(i))) + acc = UOp(Ops.DEFINE_VAR, dtypes.half.vec(i), arg=('acc', UOp.const(dtypes.half, 0), UOp.const(dtypes.half, 1))) + wmma = UOp(Ops.WMMA, dtypes.half.vec(i), (var, vec, acc)) + uops = to_uops_list([wmma]) + self.assertEqual(uops[-1], wmma) + + def test_cast_alu_fold(self): + d0 = UOp(Ops.DEFINE_GLOBAL, dtypes.bool.ptr(), arg=0) + d1 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), arg=1) + idx = UOp.const(dtypes.int, 0) + ld = UOp(Ops.LOAD, dtypes.int, (d1.index(idx),)) + alu = (ld<1).cast(dtypes.bool) + out = UOp(Ops.STORE, dtypes.void, (d0.index(idx), alu)) + uops = to_uops_list([out]) + self.assertEqual(len([x for x in uops if x.op is Ops.CAST]), 0) + + def test_double_cast_fold(self): + d0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0) + d1 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), arg=1) + idx = UOp.const(dtypes.int, 0) + ld = UOp(Ops.LOAD, dtypes.int, (d1.index(idx),)) + alu = ld.cast(dtypes.float).cast(dtypes.float) + out = UOp(Ops.STORE, dtypes.void, (d0.index(idx), alu)) + uops = to_uops_list([out]) + self.assertEqual(len([x for x in uops if x.op is Ops.CAST]), 1) + + def test_depth_2_const_fold(self): + v = UOp.variable("tmp", 0, 1) + c2 = UOp(Ops.CONST, dtypes.int, arg=2) + c4 = UOp(Ops.CONST, dtypes.int, arg=4) + vc = UOp(Ops.ADD, dtypes.int, (v, c2)) + out = UOp(Ops.ADD, dtypes.int, (vc, c4)) + uops = to_uops_list([out]) + self.assertEqual(len(uops), 3) + out = uops[-1] + self.assertEqual(out.op, Ops.ADD) + self.assertEqual(out.src[1].op, Ops.CONST) + self.assertEqual(out.src[1].arg, 6) + + def test_bitcast_to_same_dtype_fold(self): + for dt in dtypes.ints + dtypes.floats + (dtypes.bool,): + d0 = UOp(Ops.DEFINE_GLOBAL, dt.ptr(), arg=0) + v = UOp(Ops.LOAD, dt, (d0.index(UOp.const(dtypes.int, 0)),)) + uops = to_uops_list([v.bitcast(dt)]) + self.assertEqual(len([x for x in uops if x.op is Ops.BITCAST]), 0, f"dtype = {dt}") + + def test_in_out_of_bounds_access(self): + with Context(IGNORE_OOB=0): + glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(16), (), 0) + ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(UOp.const(dtypes.int, 0)),)) + to_uops_list([ld0]) + ld1 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(UOp.const(dtypes.int, 15)),)) + to_uops_list([ld1]) + ld1 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(UOp.const(dtypes.int, 7)),)) + to_uops_list([ld1]) + + ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(UOp.const(dtypes.int, 42)),)) + with self.assertRaises(RuntimeError): to_uops_list([ld0]) + + def test_in_out_of_bounds_access_symbolic(self): + with Context(IGNORE_OOB=0): + glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(16), (), 0) + ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(Variable("i", 1, 10)),)) + to_uops_list([ld0]) + ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(Variable("i", 0, 15)),)) + to_uops_list([ld0]) + + ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(Variable("i", 0, 20)),)) + with self.assertRaises(RuntimeError): to_uops_list([ld0]) + + def test_in_out_of_bounds_access_gated_store(self): + with Context(IGNORE_OOB=0): + glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(16), (), 0) + v = Variable("v", 0, 20) + st0 = UOp(Ops.STORE, dtypes.void, (glbl0.index(v), UOp.const(dtypes.int, 0), v<16)) + to_uops_list([st0]) + + st1 = UOp(Ops.STORE, dtypes.void, (glbl0.index(v), v, v<20)) + with self.assertRaises(RuntimeError): to_uops_list([st1]) + + def test_in_bounds_access_gated_local(self): + with Context(IGNORE_OOB=0): + # Define buffers + gbuf = UOp(Ops.DEFINE_GLOBAL, dtypes.uint.ptr(400), (), 0) + sbuf = UOp(Ops.DEFINE_LOCAL, dtypes.uint.ptr(8, local=True), (), "temp0") + + # Define indices, valids and barrier + gidx = UOp(Ops.SPECIAL, dtypes.int, (), ("gidx0", 416)) + lidx = UOp(Ops.SPECIAL, dtypes.int, (), ("lidx0", 10)) + + gate = (gidx<400) & (lidx<8) + + local_store = UOp(Ops.STORE, dtypes.void, (sbuf.index(lidx), UOp.const(dtypes.uint, 1), lidx<8)) + + barrier = UOp(Ops.BARRIER, dtypes.void, (local_store,)) + if_barrier = UOp(Ops.IF, dtypes.void, (gate, barrier)) + + # Load from local memory (after the IF/barrier) + local_load = UOp(Ops.LOAD, dtypes.uint, (sbuf.index(lidx), if_barrier)) + + # Store to global memory + global_store = UOp(Ops.STORE, dtypes.void, (gbuf.index(gidx), local_load)) + to_uops_list([global_store]) + + def test_out_of_bounds_off_by_one_access(self): + with Context(IGNORE_OOB=0): + glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(16), (), 0) + ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(UOp.const(dtypes.int, 16)),)) + with self.assertRaises(RuntimeError): to_uops_list([ld0]) + + def test_in_out_bounds_access_with_mask(self): + with Context(IGNORE_OOB=0): + glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(16), (), 0) + gidx0 = UOp(Ops.SPECIAL, dtype=dtypes.int, arg=("gidx0", 42)) + ld0 = UOp(Ops.LOAD, dtypes.int, (glbl0.index(gidx0, (5=0)&(ld0<32)),)) + to_uops_list([ld1]) + + ld1 = UOp(Ops.LOAD, dtypes.int, (glbl1.index(ld0*2, (ld0>=0)&(ld0<64)),)) + with self.assertRaises(RuntimeError): to_uops_list([ld1]) + + def test_fold_gated_load(self): + glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) + glbl1 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 1) + glbl2 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 2) + idx = UOp.const(dtypes.int, 0) + ld0 = UOp(Ops.LOAD, dtypes.int, (glbl1.index(idx, UOp.const(dtypes.bool, False)),)) + ld1 = UOp(Ops.LOAD, dtypes.int, (glbl2.index(idx, UOp.const(dtypes.bool, True)),)) + uops = to_uops_list([UOp(Ops.STORE, dtypes.void, (glbl0.index(idx), ld1+ld0))]) + ld0 = uops[-1].src[-1] + # the gate and invalid value are deleted from ld1 + self.assertEqual(ld0, UOp.load(glbl2.index(idx), dtype=dtypes.int)) + + def test_fold_gated_load_local(self): + glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) + smem = UOp(Ops.DEFINE_LOCAL, dtypes.int.ptr(size=18, local=True), (), "temp") + lidx = UOp(Ops.SPECIAL, dtypes.int, (), ("lidx0", 16)) + st = UOp(Ops.STORE, dtypes.void, (smem.index(lidx), UOp.load(glbl0.index(lidx), dtype=dtypes.int))) + barrier = UOp(Ops.BARRIER, dtypes.void, (st, )) + ld0 = UOp(Ops.LOAD, dtypes.int, (smem.index(lidx+1, UOp.const(dtypes.bool, False)), barrier)) + ld1 = UOp(Ops.LOAD, dtypes.int, (smem.index(lidx+2, UOp.const(dtypes.bool, True)), barrier)) + uops = to_uops_list([UOp(Ops.STORE, dtypes.void, (glbl0.index(lidx), ld1+ld0))]) + + ld0 = uops[-1].src[-1] + # the gate and invalid value are deleted from ld1 + self.assertEqual(ld0.src[0], smem.index(lidx+2)) + + def test_fold_gated_store(self): + glbl = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) + idx0 = UOp.const(dtypes.int, 0) + idx1 = UOp.const(dtypes.int, 0) + val = UOp.const(dtypes.int, 42) + st0 = UOp(Ops.STORE, dtypes.void, (glbl.index(idx0, UOp.const(dtypes.bool, False)), val)) + st1 = UOp(Ops.STORE, dtypes.void, (glbl.index(idx1, UOp.const(dtypes.bool, True)), val)) + uops = to_uops_list([st0, st1]) + # only the second store happens + self.assertEqual(len(uops), 5) + self.assertEqual(uops[-1], UOp.store(glbl.index(idx1), val)) + + @unittest.skip("this is a uop type error") + def test_asserts_bad_gate(self): + glbl0 = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) + idx = UOp.const(dtypes.int, 0) + bad_gate = UOp.const(dtypes.int, 1) + with self.assertRaises(AssertionError): to_uops_list([UOp(Ops.STORE, dtypes.void, (glbl0, idx, UOp.const(dtypes.int, 42), bad_gate))]) + + def test_switched_range_order(self): + glbl = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) + c2 = UOp.const(dtypes.int, 2) + cf = UOp.const(dtypes.float, 0.0) + r1 = UOp(Ops.RANGE, dtypes.int, (c2,), 0) + r2 = UOp(Ops.RANGE, dtypes.int, (c2,), 1) + alu = UOp(Ops.MUL, dtypes.int, (r2, r1)) + store = UOp(Ops.STORE, dtypes.void, (glbl.index(alu), cf)) + uops = to_uops_list([store]) + ranges = [x for x in uops if x.op is Ops.RANGE] + endranges = [x for x in uops if x.op is Ops.ENDRANGE] + # ranges are closed in the right order + self.assertEqual(endranges[-1].src[0], ranges[0]) + +@track_rewrites() +def expander_rewrite(sink): return graph_rewrite(sink, sym + expander) + +class TestExpander(unittest.TestCase): + def test_expand_add_broadcast(self): + e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(x for x in range(4))),), ((1,4),)) + sink = expander_rewrite(e1+3) + assert sink.op is Ops.UNROLL and len(sink.src[0].arg) == 4 + self.assertTupleEqual(sink.src[0].arg, (3,4,5,6)) + + def test_contract_simple(self): + e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(x for x in range(4))),), ((1,4),)) + con = UOp(Ops.CONTRACT, dtypes.int.vec(4), (e1,), ((1,4),)) + sink = expander_rewrite(con) + self.assertEqual(sink.op, Ops.VCONST) + self.assertTupleEqual(sink.arg, (0,1,2,3)) + + def test_contract_axis_1(self): + e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(16), tuple(x for x in range(16))),), ((1,4),(2,4))) + con = UOp(Ops.CONTRACT, dtypes.int.vec(4), (e1,), ((1,4),)) + sink = expander_rewrite(con) + assert sink.op is Ops.UNROLL and len(sink.src[0].arg) == 16 and sink.arg == ((2,4),) + assert sink.src[0].op is Ops.VCONST + self.assertTupleEqual(sink.src[0].arg[0:4], (0,4,8,12)) + self.assertTupleEqual(sink.src[0].arg[12:], (3,7,11,15)) + + def test_contract_axis_2(self): + e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(16), tuple(x for x in range(16))),), ((1,4),(2,4))) + con = UOp(Ops.CONTRACT, dtypes.int.vec(4), (e1,), ((2,4),)) + sink = expander_rewrite(con) + assert sink.op is Ops.UNROLL and len(sink.src[0].arg) == 16 and sink.arg == ((1,4),) + assert sink.src[0].op is Ops.VCONST + self.assertTupleEqual(sink.src[0].arg[0:4], (0,1,2,3)) + self.assertTupleEqual(sink.src[0].arg[12:], (12,13,14,15)) + + def test_contract_axis_2_big(self): + e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(16), tuple(x for x in range(16))),), ((1,2),(2,2),(3,2),(4,2))) + con = UOp(Ops.CONTRACT, dtypes.int.vec(2), (e1,), ((2,2),)) + sink = expander_rewrite(con) + assert sink.op is Ops.UNROLL and sink.arg == ((1, 2), (3, 2), (4, 2)) + self.assertTupleEqual(sink.src[0].arg[0:2], (0,4)) + self.assertTupleEqual(sink.src[0].arg[12:14], (10,14)) + + def test_contract_multi_axis(self): + e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(16), tuple(x for x in range(16))),), ((1,2),(2,2),(3,2),(4,2))) + sink = expander_rewrite(UOp(Ops.CONTRACT, dtypes.int.vec(4), (e1,), ((3, 2), (2, 2)))) + assert sink.op is Ops.UNROLL and sink.arg == ((1, 2), (4, 2)) + self.assertTupleEqual(sink.src[0].arg[0:4], (0, 4, 2, 6)) + sink = expander_rewrite(UOp(Ops.CONTRACT, dtypes.int.vec(4), (e1,), ((2, 2), (3, 2)))) + assert sink.op is Ops.UNROLL and sink.arg == ((1, 2), (4, 2)) + self.assertTupleEqual(sink.src[0].arg[0:4], (0, 2, 4, 6)) + + def test_contract_mid(self): + e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(8), tuple(x for x in range(8))),), ((1,2),(2,2),(3,2))) + con = UOp(Ops.CONTRACT, dtypes.int.vec(2), (e1,), ((2,2),)) + sink = expander_rewrite(con) + assert sink.op is Ops.UNROLL and sink.arg == ((1,2),(3,2)) + assert sink.src[0].op is Ops.VCONST and len(sink.src[0].arg) == 8 + self.assertTupleEqual(sink.src[0].arg, (0,2,1,3,4,6,5,7)) + + def test_contract_no_expand(self): + e1 = UOp(Ops.DEFINE_VAR, dtypes.int) + con = UOp(Ops.CONTRACT, dtypes.int.vec(2), (e1,), ((2,2),)) + sink = expander_rewrite(con) + assert sink.op is Ops.VECTORIZE and len(sink.src) == 2 + assert sink.src[0] == sink.src[1] + + def test_contract_half_expand(self): + e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(x for x in range(4))),), ((1,4),)) + con = UOp(Ops.CONTRACT, dtypes.int.vec(8), (e1,), ((1,4), (2,2))) + sink = expander_rewrite(con) + assert sink.op is Ops.VCONST and len(sink.arg) == 8 + assert sink.arg[0] == sink.arg[1] + assert sink.arg[0] != sink.arg[2] + assert sink.arg[6] == sink.arg[7] + + def test_expand_same_axis(self): + e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(x for x in range(4))),), ((1,4),)) + e2 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(4*x for x in range(4))),), ((1,4),)) + sink = expander_rewrite(e1+e2) + self.assertEqual(sink.op, Ops.UNROLL) + self.assertEqual(sink.src[0].op, Ops.VCONST) + self.assertTupleEqual(sink.src[0].arg, (0,5,10,15)) + + def test_expand_different_axis(self, flip=False): + e1 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(4*x for x in range(4))),), ((1,4),)) + e2 = UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(4), tuple(x for x in range(4))),), ((2,4),)) + sink = expander_rewrite((e2+e1) if flip else (e1+e2)) + assert sink.op is Ops.UNROLL and len(sink.src[0].arg) == 16 + assert sink.arg == ((1, 4), (2, 4)) + self.assertTupleEqual(sink.src[0].arg, (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)) + + def test_expand_different_axis_flip(self): self.test_expand_different_axis(True) + + @unittest.skip("no longer supported") + def test_reduce_known_axis(self): + e1 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((1,4),)) + sink = UOp(Ops.REDUCE, dtypes.int, (3*e1,e1), Ops.ADD) + sink = expander_rewrite(sink) + assert sink.op is Ops.CONST + self.assertEqual(sink.arg, 3*(0+1+2+3)) + + @unittest.skip("no longer supported") + def test_reduce_const(self): + e1 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((1,4),)) + sink = UOp(Ops.REDUCE, dtypes.int, (UOp.const(dtypes.int, 3), e1), Ops.ADD) + sink = expander_rewrite(sink) + assert sink.op is Ops.CONST + self.assertEqual(sink.arg, 3*4) + + @unittest.skip("no longer supported") + def test_double_expand(self): + e1 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((2,4),)) + e2 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, 4+x) for x in range(4)), ((2,4),)) + e = UOp(Ops.UNROLL, dtypes.int, (e1, e2), ((1,2),)) + sink = expander_rewrite(e) + assert sink.op is Ops.UNROLL and len(sink.src) == 8 + assert sink.arg == ((1, 2), (2, 4)) + self.assertListEqual([x.arg for x in sink.src], [0,1,2,3,4,5,6,7]) + + @unittest.skip("no longer supported") + def test_double_expand_reverse(self): + e1 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((1,4),)) + e2 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, 4+x) for x in range(4)), ((1,4),)) + e = UOp(Ops.UNROLL, dtypes.int, (e1, e2), ((2,2),)) + sink = expander_rewrite(e) + assert sink.op is Ops.UNROLL and len(sink.src) == 8 + assert sink.arg == ((1, 4), (2, 2)) + self.assertListEqual([x.arg for x in sink.src], [0, 4, 1, 5, 2, 6, 3, 7]) + + @unittest.skip("no longer supported") + def test_double_expand_middle(self): + e1 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((1,2),(3,2))) + e2 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, 4+x) for x in range(4)), ((1,2),(3,2))) + e = UOp(Ops.UNROLL, dtypes.int, (e1, e2), ((2,2),)) + sink = expander_rewrite(e) + assert sink.op is Ops.UNROLL and len(sink.src) == 8 + assert sink.arg == ((1, 2), (2, 2), (3, 2)) + self.assertListEqual([x.arg for x in sink.src], [0, 1, 4, 5, 2, 3, 6, 7]) + + # does this need to work? + @unittest.expectedFailure + @unittest.skip + def test_reduce_different_axis(self): + e1 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((1,4),)) + e2 = UOp(Ops.UNROLL, dtypes.int, tuple(UOp.const(dtypes.int, x) for x in range(4)), ((2,4),)) + sink = UOp(Ops.REDUCE, dtypes.int, (e1,e2), Ops.ADD) + sink = expander_rewrite(sink) + print(sink) + +class TestIFUOps(unittest.TestCase): + def test_create_ifs(self): + gbuf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) + sbuf = UOp(Ops.DEFINE_LOCAL, dtypes.float.ptr(size=4, local=True), (), "smem") + valid = UOp(Ops.SPECIAL, dtypes.int, (), ("gidx0", 10))<5 + lidx = UOp(Ops.SPECIAL, dtypes.int, (), ("lidx0", 4)) + gate = valid&(lidx.ne(2)) + idx = UOp.const(dtypes.int, 0) + st = UOp(Ops.STORE, dtypes.void, (sbuf.index(idx), UOp.const(dtypes.float, 42))) + barrier = UOp(Ops.BARRIER, dtypes.void, (st,)) + lbuf = UOp(Ops.LOAD, dtypes.float, (sbuf.index(UOp.const(dtypes.int, 0)), barrier)) + store = UOp(Ops.STORE, dtypes.void, (gbuf.index(UOp.const(dtypes.int, 0), gate), lbuf)) + sink = UOp(Ops.SINK, dtypes.void, (store,)) + sink = full_rewrite_to_sink(sink) + if_uops = [u for u in sink.toposort() if u.op is Ops.IF] + self.assertEqual(len(if_uops), 1) + self.assertEqual(if_uops[0].src[0], gate) + for st in sink.src: + self.assertEqual(len(st.src), 2) + + def test_expand_ifs_one_gate(self): + gbuf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) + sbuf = UOp(Ops.DEFINE_LOCAL, dtypes.float.ptr(size=16, local=True), (), "smem") + valid = UOp(Ops.SPECIAL, dtypes.int, (), ("gidx0", 4))<1 + lidx = UOp(Ops.SPECIAL, dtypes.int, (), ("lidx0", 16)) + gate = valid&(lidx.ne(2)) + st = UOp(Ops.STORE, dtypes.void, (sbuf, lidx, UOp.const(dtypes.float, 42))) + barrier = UOp(Ops.BARRIER, dtypes.void, (st,)) + lbufs = [UOp(Ops.LOAD, dtypes.float, (sbuf.index(UOp.const(dtypes.int, i)), barrier)) for i in range(4)] + stores = [UOp(Ops.STORE, dtypes.void, (gbuf.index(UOp.const(dtypes.int, i), gate), lbufs[i])) for i in range(4)] + sink = UOp(Ops.SINK, dtypes.void, tuple(stores)) + sink = full_rewrite_to_sink(sink) + if_uops = [u for u in sink.toposort() if u.op is Ops.IF] + self.assertEqual(len(if_uops), 1) + self.assertEqual(if_uops[0].src[0], gate) + for st in sink.src: + self.assertEqual(len(st.src), 2) + + # this will be fixed with the merge gated stores bounty + @unittest.expectedFailure + def test_expand_ifs_dumb(self): + buf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) + valid = UOp(Ops.SPECIAL, dtypes.int, (), ("gidx0", 10))<5 + lidx = UOp(Ops.SPECIAL, dtypes.int, (), ("lidx0", 4)) + gate = valid&(lidx.ne(2)) + stores = [UOp(Ops.STORE, dtypes.void, (buf, UOp.const(dtypes.int, i), UOp.const(dtypes.float, i), gate)) for i in range(4)] + sink = UOp(Ops.SINK, dtypes.void, tuple(stores)) + sink = full_rewrite_to_sink(sink) + if_uops = [u for u in sink.toposort() if u.op is Ops.IF] + self.assertEqual(len(if_uops), 1) + self.assertEqual(if_uops[0].src[0], gate) + for st in sink.src: + self.assertEqual(len(st.src), 2) + +class TestUOpTags(unittest.TestCase): + def test_inc_by_one(self): + g = UOp.const(dtypes.int, 1) + UOp.const(dtypes.int, 1) + assert g.ssimplify() == 2 + pm_plus_1 = PatternMatcher([(UPat(Ops.CONST, name="x"), lambda x: x.replace(arg=x.arg+1, tag=1) if x.tag is None else None)]) + pm_strip_tags = PatternMatcher([(UPat(GroupOp.All, name="x"), lambda x: x.replace(tag=None) if x.tag is not None else None)]) + g = graph_rewrite(g, pm_plus_1) + assert g.ssimplify() == 4 + g = graph_rewrite(g, pm_plus_1) + assert g.ssimplify() == 4 + g = graph_rewrite(g, pm_strip_tags) + assert g.ssimplify() == 4 + g = graph_rewrite(g, pm_plus_1) + assert g.ssimplify() == 6 + +if __name__ == '__main__': + unittest.main(verbosity=2) diff --git a/tinygrad_repo/test/test_uops.py b/tinygrad_repo/test/test_uops.py new file mode 100644 index 000000000..953f18af6 --- /dev/null +++ b/tinygrad_repo/test/test_uops.py @@ -0,0 +1,661 @@ +from typing import Optional, Any +import unittest, math +import numpy as np +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.shape.view import View # noqa F401 +from tinygrad.tensor import Tensor, _to_np_dtype +from tinygrad.helpers import CI, DEBUG, getenv, Timing +from tinygrad.dtype import dtypes, DType +from tinygrad.device import Buffer, Device +from tinygrad.uop.ops import Ops, UOp, UPat, KernelInfo, exec_alu # noqa F401 +from tinygrad.uop.spec import spec +from tinygrad.renderer import ProgramSpec +from tinygrad.kernelize.kernelize import fix_kernel_ops +from tinygrad.engine.realize import CompiledRunner, get_program +from tinygrad.codegen import full_rewrite +from tinygrad.uop.symbolic import sym +from tinygrad.device import is_dtype_supported +from tinygrad.opt.kernel import Opt, OptOps + +def to_uops_list(u:list[UOp], opts=None, skip_check=False) -> list[UOp]: return full_rewrite(UOp.sink(*u), opts) + +def _uops_to_prg(uops_list): + uops = full_rewrite(ast:=UOp.sink(*uops_list), opts=Device[Device.DEFAULT].renderer) + src = Device[Device.DEFAULT].renderer.render(uops) + has_local = Device[Device.DEFAULT].renderer.has_local + return CompiledRunner(ProgramSpec("test", src, Device.DEFAULT, ast, uops=uops, + global_size=[1,1,1] if has_local else None, local_size=[1,1,1] if has_local else None)) + +def uop(uops:list[UOp], uop:Ops, dtype:Optional[DType], src:tuple[UOp, ...], arg:Any=None) -> UOp: + uops.append(UOp(uop, dtype, tuple(src), arg)) + return uops[-1] + +def _test_single_value(vals, op, dts): + uops = [] + output_dtype = dtypes.bool if op in (Ops.CMPLT, Ops.CMPNE) else dts[-1] + buf_store = uop(uops, Ops.DEFINE_GLOBAL, output_dtype.ptr(), (), 0) + buf_loads = [uop(uops, Ops.DEFINE_GLOBAL, dtype.ptr(), (), i+1) for i,dtype in enumerate(dts)] + loads = (uop(uops, Ops.LOAD, dtype, [buf_loads[i].index(uop(uops, Ops.CONST, dtypes.int32, (), 0))]) for i, dtype in enumerate(dts)) + alu = uop(uops, op, output_dtype, loads) + out = uop(uops, Ops.STORE, dtypes.void, (buf_store.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), alu)) + buf = Buffer(Device.DEFAULT, 1, output_dtype).allocate() + buf2 = [Buffer(Device.DEFAULT, 1, dtype).allocate().copyin(np.array([a], dtype=_to_np_dtype(dtype)).data) for a,dtype in zip(vals, dts)] + prg = _uops_to_prg([out]) + prg.exec([buf]+buf2) + ret = np.empty(1, _to_np_dtype(output_dtype)) + buf.copyout(ret.data) + return ret[0] + +def _test_single_value_const(vals, op, dts): + uops = [] + output_dtype = dtypes.bool if op in (Ops.CMPLT, Ops.CMPNE) else dts[-1] + buf_store = uop(uops, Ops.DEFINE_GLOBAL, output_dtype.ptr(), (), 0) + loads = (uop(uops, Ops.CONST, dtype, [], a) for a,dtype in zip(vals, dts)) + alu = uop(uops, op, output_dtype, loads) + out = uop(uops, Ops.STORE, dtypes.void, (buf_store.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), alu)) + buf = Buffer(Device.DEFAULT, 1, output_dtype).allocate() + prg = _uops_to_prg([out]) + prg.exec([buf]) + ret = np.empty(1, _to_np_dtype(output_dtype)) + buf.copyout(ret.data) + return ret[0] + +def _test_uops_result(output_dtype, uops, res): + # uops = [] + buf_store = uop(uops, Ops.DEFINE_GLOBAL, output_dtype.ptr(), (), 0) + # res = output_fn(uops) + out = uop(uops, Ops.STORE, dtypes.void, (buf_store.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), res)) + buf = Buffer(Device.DEFAULT, 1, output_dtype).allocate() + prg = _uops_to_prg([out]) + prg.exec([buf]) + ret = np.empty(1, _to_np_dtype(output_dtype)) + buf.copyout(ret.data) + return ret[0] + +class TestUOps(unittest.TestCase): + def _equal(self, v1, v2): + assert isinstance(v2, (float, int, bool)) + if isinstance(v2, float): + np.testing.assert_allclose(v1, v2, rtol=2e-7) + else: + np.testing.assert_equal(v1, v2) + + def _test_uop_fxn(self, op, fxn, dts=(dtypes.float32, )): + for f in [_test_single_value, _test_single_value_const]: + for a in [-2.0, 0.0, 1.0]: + a = dtypes.as_const(a, dts[0]) + self._equal(f([a], op, dts), fxn(a)) + + def _test_bop_fxn(self, op, fxn, dts=(dtypes.float32, )*2, no_b_zero=False, no_b_neg=False): + for f in [_test_single_value, _test_single_value_const]: + for a in [-2.0, 0.0, 1.0]: + for b in [-3.0, 1.0] + ([] if no_b_zero else [0.0]): + a = dtypes.as_const(a, dts[0]) + b = dtypes.as_const(abs(b) if no_b_neg else b, dts[1]) + self._equal(f([a,b], op, dts), fxn(a,b)) + + def _test_top_fxn(self, op, fxn, dts=(dtypes.float32, )*3): + for f in [_test_single_value, _test_single_value_const]: + for a in [-2.0, 0, 1]: + for b in [-3.0, 3.0]: + for c in [-4.0, 4.0]: + a = dtypes.as_const(a, dts[0]) + b = dtypes.as_const(b, dts[1]) + c = dtypes.as_const(c, dts[2]) + self._equal(f([a,b,c], op, dts), fxn(a,b,c)) + +class TestFloatUOps(TestUOps): + @unittest.skipIf(Device.DEFAULT == "CPU", 'not supported as uop') + def test_exp2(self): self._test_uop_fxn(Ops.EXP2, lambda a: np.exp2(a)) + @unittest.skipIf(Device.DEFAULT == "CPU", 'not supported as uop') + def test_log2(self): self._test_uop_fxn(Ops.LOG2, lambda a: math.log2(a) if a > 0 else float('-inf' if a==0 else 'nan')) + @unittest.skipIf(Device.DEFAULT == "CPU", 'not supported as uop') + def test_sin(self): self._test_uop_fxn(Ops.SIN, lambda a: math.sin(a)) + def test_recip(self): self._test_uop_fxn(Ops.RECIP, lambda a: 1/a if a != 0 else float('inf')) + def test_sqrt(self): self._test_uop_fxn(Ops.SQRT, lambda a: math.sqrt(a) if a >= 0 else float('nan')) + + def test_add(self): self._test_bop_fxn(Ops.ADD, lambda a,b: a+b) + def test_mul(self): self._test_bop_fxn(Ops.MUL, lambda a,b: a*b) + def test_max(self): self._test_bop_fxn(Ops.MAX, lambda a,b: max(a,b)) + def test_cmplt(self): self._test_bop_fxn(Ops.CMPLT, lambda a,b: a>int(b), (dtypes.int32, dtypes.int32), no_b_neg=True) + @unittest.skipUnless(getenv("PTX"), "only ptx uses bitshifts") + def test_shl_int32(self): self._test_bop_fxn(Ops.SHL, lambda a,b: int(a)<= 4: print(Device[Device.DEFAULT].renderer.render(uops)) + if_uop = next(u for u in uops if u.op is Ops.IF) + endif = next(u for u in uops if u.op is Ops.ENDIF) + assert endif.src[0] is if_uop + gated_uops = tuple(uops[uops.index(if_uop)+1:uops.index(endif)]) + self.assertEqual(len(gated_uops), 1) + self.assertIs(gated_uops[-1].op, Ops.STORE) + + def test_gate_some_stores(self): + gmem0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) + gmem1 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 1) + gidx0 = UOp(Ops.SPECIAL, dtypes.int, (), ('gidx0', 4)) + idx = gidx0 * UOp.const(dtypes.int, 2) + idx0 = UOp(Ops.INDEX, dtypes.float.ptr(), (gmem0, idx, gidx0= 4: print(Device[Device.DEFAULT].renderer.render(uops)) + if_uop = next(u for u in uops if u.op is Ops.IF) + endif = next(u for u in uops if u.op is Ops.ENDIF) + assert endif.src[0] is if_uop + gated_uops = tuple(uops[uops.index(if_uop)+1:uops.index(endif)]) + self.assertEqual(len(gated_uops), 1) + self.assertIs(gated_uops[-1].op, Ops.STORE) + + # scaled down version of TestLinearizerDumb.test_unmerged_ifs + def test_merge_ifs_alt(self): + gmem0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) + gmem1 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 1) + gidx0 = UOp(Ops.SPECIAL, dtypes.int, (), ('gidx0', 4)) + idx = gidx0*UOp.const(dtypes.int, 2) + gate = gidx0= 4: print(Device[Device.DEFAULT].renderer.render(uops)) + ifs = [u for u in uops if u.op is Ops.IF] + endifs = [u for u in uops if u.op is Ops.ENDIF] + self.assertEqual(len(ifs), 1) + self.assertEqual(len(endifs), 1) + gated_uops = tuple(uops[uops.index(ifs[0])+1:uops.index(endifs[0])]) + self.assertEqual(len(gated_uops), 2) + for x in gated_uops: self.assertIs(x.op, Ops.STORE) + +class TestLocalAccess(unittest.TestCase): + # NOTE: this is failing on METAL CI, no idea why. Works locally. + @unittest.skipIf(Device.DEFAULT == "METAL" and CI, "failing only in CI") + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared memory") + def test_local_basic(self): + uops = [] + smem = uop(uops, Ops.DEFINE_LOCAL, dtypes.float32.ptr(size=16, local=True), (), 'smem') + st = uop(uops, Ops.STORE, dtypes.void, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), uop(uops, Ops.CONST, dtypes.float32, (), 42.0))) + barr = uop(uops, Ops.BARRIER, dtypes.void, (st,)) + sres = uop(uops, Ops.LOAD, dtypes.float32, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), barr)) + self.assertEqual(_test_uops_result(dtypes.float32, uops, sres), 42) + + # NOTE: webgpu specific, since only webgpu performs bitpacking + @unittest.skipUnless(Device.DEFAULT == "WEBGPU", "Test local access with packed data type") + def test_local_packed(self): + uops = [] + smem = uop(uops, Ops.DEFINE_LOCAL, dtypes.uint8.ptr(size=16, local=True), (), 'smem') + st = uop(uops, Ops.STORE, dtypes.void, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), uop(uops, Ops.CONST, dtypes.uint8, (), 42))) + barr = uop(uops, Ops.BARRIER, dtypes.void, (st,)) + sres = uop(uops, Ops.LOAD, dtypes.uint8, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 0)), barr)) + self.assertEqual(_test_uops_result(dtypes.uint8, uops, sres), 42) + + # NOTE: webgpu specific, since only webgpu performs bitpacking + @unittest.skipUnless(Device.DEFAULT == "WEBGPU", "Test local memory size for packed data types") + def test_packed_smem_size(self): + _dtypes = [dtypes.char, dtypes.uchar, dtypes.short, dtypes.ushort, dtypes.half] + size = 16 + for dtype in _dtypes: + temp = UOp(Ops.DEFINE_LOCAL, dtype.ptr(size=size, local=True), (), 'smem') + uops = to_uops_list([temp], opts=Device[Device.DEFAULT].renderer) + out = Device[Device.DEFAULT].renderer.render(uops) + # half is supported in wgsl, so it doesn't have to be packed + corrected_size = size//(4//dtype.itemsize) if dtype != dtypes.half else size + self.assertIn(f"temp0: array<{Device[Device.DEFAULT].renderer.buf_map(dtype)},{corrected_size}>;", out) + + @unittest.skipUnless(Device[Device.DEFAULT].renderer.has_shared, "test requires shared memory") + @unittest.skip("tinygrad doesn't support this behavior") + def test_local_indirect(self): + uops = [] + smem = uop(uops, Ops.DEFINE_LOCAL, dtypes.int32.ptr(size=16, local=True), (), 'smem') + st1 = uop(uops, Ops.STORE, dtypes.void, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 1)), uop(uops, Ops.CONST, dtypes.int32, (), 2))) + st2 = uop(uops, Ops.STORE, dtypes.void, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 2)), uop(uops, Ops.CONST, dtypes.int32, (), 42))) + barr = uop(uops, Ops.BARRIER, dtypes.void, (st1,st2)) + ofs = uop(uops, Ops.LOAD, dtypes.int32, (smem.index(uop(uops, Ops.CONST, dtypes.int32, (), 1)), barr)) + sres = uop(uops, Ops.LOAD, dtypes.int32, (smem.index(ofs),)) + self.assertEqual(_test_uops_result(dtypes.int32, uops, sres), 42) + +@unittest.skipUnless(getenv("PTX"), "This only tests assembly backends") +class TestAssembly(unittest.TestCase): + def test_bitshift_left(self): + g1 = UOp(Ops.DEFINE_GLOBAL, dtypes.int32.ptr(), (), 0) + c1 = UOp(Ops.CONST, dtypes.int, (), 2) + c2 = UOp(Ops.CONST, dtypes.int, (), 3) + l1 = UOp(Ops.LOAD, dtypes.int, (g1.index(c1),)) + a1 = UOp(Ops.MUL, dtypes.int, (l1, c1)) + a2 = UOp(Ops.MUL, dtypes.int, (l1, c2)) + uops = to_uops_list([a1,a2], opts=Device[Device.DEFAULT].renderer) + Device[Device.DEFAULT].renderer.render(uops) + ops = [x.op for x in uops] + self.assertIn(Ops.SHL, ops) + self.assertIn(Ops.MUL, ops) + + def test_division_power_of_two(self): + for dt in (dtypes.int32, dtypes.uint32): + g = UOp(Ops.DEFINE_GLOBAL, dt.ptr(), (), 0) + c = UOp(Ops.CONST, dt, (), 2) + l = UOp(Ops.LOAD, dt, (g.index(c),)) + a = UOp(Ops.IDIV, dt, (l, c)) + uops = to_uops_list([a], opts=Device[Device.DEFAULT].renderer) + Device[Device.DEFAULT].renderer.render(uops) + ops = [x.op for x in uops] + self.assertIn(Ops.SHR, ops, f"For dtype={dt} divison by power of two did not simplify to shift") + self.assertNotIn(Ops.IDIV, ops, f"For dtype={dt} divison by power of two did not simplify to shift") + + def test_fast_idiv_and_mod(self): + g = UOp(Ops.DEFINE_GLOBAL, dtypes.uint32.ptr(), (), 0) + c = UOp(Ops.CONST, dtypes.uint, (), 3) + l = UOp(Ops.LOAD, dtypes.uint, (g.index(c),)) + a = UOp(Ops.IDIV, dtypes.uint, (l, c)) + uops = to_uops_list([a], opts=Device[Device.DEFAULT].renderer) + Device[Device.DEFAULT].renderer.render(uops) + ops = [x.op for x in uops] + self.assertIn(Ops.SHR, ops) + self.assertNotIn(Ops.IDIV, ops) + + b = UOp(Ops.MOD, dtypes.uint, (l, c)) + uops = to_uops_list([b], opts=Device[Device.DEFAULT].renderer) + Device[Device.DEFAULT].renderer.render(uops) + ops = [x.op for x in uops] + self.assertIn(Ops.SHR, ops) + self.assertNotIn(Ops.MOD, ops) + + @unittest.expectedFailure + def test_fast_idiv_overflow(self): + # This will be possible with a slightly different method for fast_idiv + g = UOp(Ops.DEFINE_GLOBAL, dtypes.uint32.ptr(), (), 0) + c = UOp(Ops.CONST, dtypes.uint, (), 7) + l = UOp(Ops.LOAD, dtypes.uint, (g.index(c),)) + a = UOp(Ops.IDIV, dtypes.uint, (l, c)) + uops = to_uops_list([a], opts=Device[Device.DEFAULT].renderer) + Device[Device.DEFAULT].renderer.render(uops) + ops = [x.op for x in uops] + self.assertIn(Ops.SHR, ops) + self.assertNotIn(Ops.IDIV, ops) + + def test_mulacc_unrolled(self): + # test that acc = acc + a0*b0 + a1*b1 + a2*b2 + a3*b3 + # is not acc = acc + (a0*b0 + a1*b1 + a2*b2 + a3*b3) + a = Tensor.empty(1024) + b = Tensor.empty(1024) + c = (a*b).sum() + ast = c.schedule()[-1].ast + opts_to_apply = [Opt(OptOps.UNROLL, 0, 4)] + ast = ast.replace(arg=KernelInfo(opts_to_apply=tuple(opts_to_apply))) + program = get_program(ast, Device[Device.DEFAULT].renderer) + uops = program.uops + self.assertEqual(len([x.op for x in uops if x.op is Ops.MULACC]), 4) + +class TestUOpMethod(unittest.TestCase): + @unittest.skip("uops lt no longer ordered") + def test_compare_alu_same_src_different_arg(self): + a = UOp(Ops.CONST, dtypes.float, (), 2.0) + b = UOp(Ops.CONST, dtypes.float, (), 3.0) + + add = UOp(Ops.ADD, dtypes.float, (a, b)) + mul = UOp(Ops.MUL, dtypes.float, (a, b)) + assert (add < mul) or (mul < add), "add and mul with same src should have an order" + + def test_uop_variables(self): + a = UOp.variable("a", 1, 10) + uop_var = Tensor(a.bind(1)) + st_var = Tensor.empty((2, 1)).reshape((2, a.bind(1))) + _, var_vals = (uop_var+st_var).schedule_with_vars() + self.assertEqual(len(var_vals), 1) + self.assertEqual(list(var_vals)[0], a) + + def test_const_factor(self): + gidx0 = UOp(Ops.SPECIAL, dtypes.int, (), ('gidx0', 8)) + self.assertEqual(UOp(Ops.CONST, dtypes.int, (), 17).const_factor(), 17) + self.assertEqual(gidx0.const_factor(), 1) + self.assertEqual((gidx0*3).const_factor(), 3) + self.assertEqual((gidx0*3+6).const_factor(), 3) + self.assertEqual((gidx0*3+1).const_factor(), 1) + + def test_replace(self): + x = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), (), 0) + self.assertIs(x.replace(arg=None).arg, None) + with self.assertRaises(AssertionError): x.replace(field="a") + + def test_device(self): + x = UOp(Ops.VIEW, dtypes.int, (UOp.new_buffer(Device.DEFAULT, 1, dtypes.int), UOp.const(dtypes.int, 1)), ShapeTracker.from_shape(())) + self.assertEqual(x.device, Device.DEFAULT) + # NOTE: CONST doesn't have device + buffer, const = x.src + self.assertEqual(buffer.device, Device.DEFAULT) + self.assertEqual(const._device, None) + with self.assertRaises(AssertionError): const.device + +class TestUOpStr(unittest.TestCase): + def test_uop_str(self): + a = UOp(Ops.CONST, dtypes.float, (), 2.0) + UOp(Ops.CONST, dtypes.float, (), 3.0) + for _ in range(20): a = a + a + assert len(str(a)) < 10_000, "exponential string growth" + assert str(eval(str(a))) == str(a) + + def test_vectorized_str(self): + vec = UOp(Ops.VECTORIZE, dtypes.int.vec(4), tuple(UOp.const(dtypes.int, x) for x in range(4))) + assert str(eval(str(vec))) == str(vec) + + def test_device_arg(self): + device = UOp(Ops.DEVICE, arg="GPU") + assert str(eval(str(device))) == str(device) + + def test_reduceop_arg(self): + sum_uop = Tensor.empty(32, 32).sum().uop + assert str(eval(str(sum_uop))) == str(sum_uop) + +@unittest.skip("uop no longer has order like this") +class TestIndexingOrdering(unittest.TestCase): + # NOTE: these tests skip type_verify since they add dtype to STORE + @unittest.expectedFailure + def test_simple_order(self): + buf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) + st0 = UOp(Ops.STORE, dtypes.float.vec(4), (buf, UOp.const(dtypes.int, 0), UOp.const(dtypes.float.vec(4), 42))) + st1 = UOp(Ops.STORE, dtypes.float, (buf, UOp.const(dtypes.int, 4), UOp.const(dtypes.float, 10))) + uops = to_uops_list([st1, st0], skip_check=True) + stores = [st for st in uops if st.op is Ops.STORE] + assert stores[0].src[1] < stores[1].src[1], f"stored at idx {stores[1].src[1].arg} AFTER {stores[0].src[1].arg}" + + @unittest.expectedFailure + def test_ordering_multi_output(self): + buf0 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) + buf1 = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 1) + st0_0 = UOp(Ops.STORE, dtypes.float.vec(4), (buf0, UOp.const(dtypes.int, 0), UOp.const(dtypes.float.vec(4), 42))) + st1_0 = UOp(Ops.STORE, dtypes.float, (buf0, UOp.const(dtypes.int, 4), UOp.const(dtypes.float, 10))) + st0_1 = UOp(Ops.STORE, dtypes.float.vec(4), (buf1, UOp.const(dtypes.int, 0), UOp.const(dtypes.float.vec(4), 42))) + st1_1 = UOp(Ops.STORE, dtypes.float, (buf1, UOp.const(dtypes.int, 4), UOp.const(dtypes.float, 10))) + uops = to_uops_list([st0_0, st1_0, st0_1, st1_1], skip_check=True) + stores = [st for st in uops if st.op is Ops.STORE] + print("\n".join(map(str, stores))) + # buf0 stores come first + self.assertEqual(stores[0].src[0].arg, stores[1].src[0].arg) + # buf1 stores come next + self.assertEqual(stores[2].src[0].arg, stores[3].src[0].arg) + # both stores are aligned based on idx + assert stores[0].src[1] < stores[1].src[1], f"stored at idx {stores[1].src[1].arg} AFTER {stores[0].src[1].arg}" + assert stores[2].src[1] < stores[3].src[1], f"stored at idx {stores[1].src[1].arg} AFTER {stores[0].src[1].arg}" + + def test_simple_order_with_special(self): + buf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) + gidx0 = UOp(Ops.SPECIAL, dtypes.int, (), ('gidx0', 4)) + st0 = UOp(Ops.STORE, dtypes.float.vec(4), (buf, gidx0+UOp.const(dtypes.int, 0), UOp.const(dtypes.float.vec(4), 42))) + st1 = UOp(Ops.STORE, dtypes.float, (buf, UOp.const(dtypes.int, 4), UOp.const(dtypes.float, 10))) + uops = full_rewrite(UOp.sink(st1, st0)) + stores = [st for st in uops if st.op is Ops.STORE] + assert stores[0].src[1] < stores[1].src[1], f"stored at idx {stores[1].src[1].arg} AFTER {stores[0].src[1].arg}" + +class TestUPatHelpers(unittest.TestCase): + def test_location(self): + self.assertEqual(sym.patterns[-1][0].location[0].replace("\\", "/").split("/")[-1], "symbolic.py") + self.assertEqual(fix_kernel_ops.patterns[0][0].location[0].replace("\\", "/").split("/")[-1], "kernelize.py") + self.assertEqual(spec.patterns[0][0].location[0].replace("\\", "/").split("/")[-1], "spec.py") + test_upat = UPat(Ops.CONST, dtypes.bool) + self.assertEqual(test_upat.location[0].split("/")[-1], __file__.replace("\\", "/").split("/")[-1]) + test_upat_named = test_upat.named("test_name") + self.assertEqual(test_upat.location[0], test_upat_named.location[0]) + self.assertNotEqual(test_upat.location[1], test_upat_named.location[1]) + +class TestUopsObject(unittest.TestCase): + # LOL, running this test breaks all instances of "4" + """ + @unittest.expectedFailure + def test_immutable(self): + const_4 = UOp.const(dtypes.int, 4) + with self.assertRaises(Exception): + const_4.arg = 5 + """ + + def test_timing(self): + with Timing("create 10k uops:"): ret = [UOp(Ops.CONST, dtypes.int, arg=10000000+i) for i in range(10000)] + assert len(ret) == 10000 + + +class TestShapeSpec(unittest.TestCase): + # ** CONST is CONST(VIEW(DEVICE)) -> RESHPAE -> EXPAND + + def test_expanded_const(self): + a = Tensor(1).uop + self.assertEqual(a.st, ShapeTracker.from_shape(())) + a = Tensor.ones((4, 4)).uop + self.assertEqual(a.st, ShapeTracker.from_shape(()).reshape((1,1)).expand((4,4))) + + def test_padded_const(self): + a = Tensor.ones((1, 1)).pad(((1, 1), (1, 1))) + ast = a.contiguous().schedule()[0].ast + valid_pattern = UPat(Ops.WHERE, src=(UPat(Ops.VALID), UPat.cvar(), UPat.cvar())) + valid_ternary = [x for x in ast.toposort() if valid_pattern.match(x, {})][0] + # the WHERE outputs a contiguous (3, 3) + self.assertEqual(valid_ternary.st, ShapeTracker.from_shape((3, 3))) + valid, x, y = valid_ternary.src + # very notably, only the first source is padded + self.assertIsNotNone(valid.st.views[-1].mask) + assert x.st.views[-1].mask is y.st.views[-1].mask is None + assert all(s.shape == (3, 3) for s in valid_ternary.src) + + # NOTE: CONST ShapeTracker comes from its source + def test_scalar_const(self): + a = Tensor(0).uop + self.assertEqual(a.st, ShapeTracker.from_shape(())) + + def test_scalar_var(self): + vv = UOp.variable("a", 1, 4).bind(2) + t = Tensor(vv).uop + self.assertEqual(t.st, ShapeTracker.from_shape(())) + + # ** ASSIGN is ASSIGN(VIEW(BUFFER), new_val) + + def test_assign_flat(self): + buffer = Tensor.arange(4).realize() + a = buffer.assign(Tensor.zeros((4,), dtype=dtypes.int)) + assign_pattern = UPat(Ops.ASSIGN, src=(UPat(Ops.BUFFER), UPat())) + assert assign_pattern.match(a.uop, {}) + a.realize() + self.assertEqual(buffer.tolist(), [0, 0, 0, 0]) + + def test_assign_permuted(self): + buffer = Tensor.arange(4).reshape(2, 1, 2).contiguous().realize() + a = buffer.permute((1, 2, 0)).assign(Tensor.arange(4).reshape(1, 2, 2).contiguous()) + a.realize() + self.assertEqual(buffer.tolist(), [[[0, 2]], [[1, 3]]]) + + def test_assign_reshaped(self): + buffer = Tensor.ones((4,)).contiguous().realize() + a = buffer.reshape((2, 2)).assign(Tensor.zeros((2, 2))) + assign_pattern = UPat(Ops.ASSIGN, src=(UPat(Ops.RESHAPE, src=(UPat(Ops.BUFFER))), UPat())) + assert assign_pattern.match(a.uop, {}) + a.realize() + self.assertEqual(buffer.tolist(), [0, 0, 0, 0]) + + # setitem is a partial assign + def test_setitem(self): + a = Tensor.ones((4,)).contiguous().realize() + assign = a.shrink(((1, 2),)).assign(Tensor.zeros((1,))) + # the ASSIGN UOp has size=1 + self.assertEqual(assign.uop.size, 1) + # the ASSIGN views the buffer with a shrunk st + self.assertEqual(assign.uop.src[0].st, ShapeTracker.from_shape((4,)).shrink(((1, 2),))) + # the underlying BUFFER has a size=4 + self.assertEqual(assign.uop.buf_uop.size, 4) + # NOTE: output shape is different from the BUFFER shape + self.assertNotEqual(assign.uop.shape, a.uop.shape) + assign.realize() + self.assertEqual(a.tolist(), [1, 0, 1, 1]) + + def test_buffer_st(self): + a = UOp.new_buffer(Device.DEFAULT, 10, dtypes.float) + self.assertEqual(a.st, ShapeTracker.from_shape((10,))) + + def test_ops_st(self): + # view / mop + a = Tensor.empty(4, 2, 1).permute((1, 2, 0)).uop + self.assertEqual(a.st, ShapeTracker.from_shape((4, 2, 1)).permute((1, 2, 0))) + # alu / reduce + alu = a*2 + self.assertEqual(alu.st, ShapeTracker.from_shape((2, 1, 4))) + r = Tensor.empty(4, 4).sum(axis=1) + self.assertEqual(r.uop.st, ShapeTracker.from_shape((4,))) + + def test_st_wmma_none(self): + A = UOp(Ops.DEFINE_VAR, dtypes.float.vec(16), arg=('a', UOp.const(dtypes.float, 0), UOp.const(dtypes.float, 1))) + B = UOp(Ops.DEFINE_VAR, dtypes.float.vec(16), arg=('b', UOp.const(dtypes.float, 0), UOp.const(dtypes.float, 2))) + C = UOp(Ops.DEFINE_VAR, dtypes.float.vec(16), arg=('c', UOp.const(dtypes.float, 0), UOp.const(dtypes.float, 3))) + wmma = UOp(Ops.WMMA, dtypes.float.vec(16), (A, B, C)) + assert wmma.st is None + +class TestUOpChildren(unittest.TestCase): + def test_children_exist(self): + a = UOp.variable("weird_name_234", 0, 10) + b = a*a + self.assertEqual(len(a.children), 1) + self.assertIs(list(a.children)[0](), b) + + def test_children_cleaned_up(self): + a = UOp.variable("weird_name_235", 0, 10) + b = a*a + self.assertEqual(len(a.children), 1) + del b + self.assertEqual(len(a.children), 0) + + def test_children_cleaned_up_two(self): + a = UOp.variable("weird_name_236", 0, 10) + b = a*a + c = a*2 + self.assertEqual(len(a.children), 2) + del b + self.assertEqual(len(a.children), 1) + del c + self.assertEqual(len(a.children), 0) + +if __name__ == '__main__': + unittest.main(verbosity=2) diff --git a/tinygrad_repo/test/test_uops_stats.py b/tinygrad_repo/test/test_uops_stats.py new file mode 100644 index 000000000..b534c0b0e --- /dev/null +++ b/tinygrad_repo/test/test_uops_stats.py @@ -0,0 +1,249 @@ +import unittest +from tinygrad import Tensor +from tinygrad.helpers import getenv, GlobalCounters +from tinygrad.engine.realize import lower_schedule_item, ProgramSpec +from tinygrad.renderer import Estimates +from tinygrad.codegen import full_rewrite +from tinygrad.uop.ops import Ops, UOp +from tinygrad.dtype import dtypes +from tinygrad.opt.kernel import Kernel, Opt, OptOps, KernelOptError +from tinygrad.device import Device + +def flops_mem(uops, ignore_indexing=False): + est = Estimates.from_uops(uops, ignore_indexing) + return est.ops, est.lds + +# **************** new FlopCounter **************** + +def get_stats(x:Tensor): + si = x.schedule()[-1] + ei = lower_schedule_item(si) + return ei.prg.estimates.ops, ei.prg.estimates.mem + +class TestMemoryCount(unittest.TestCase): + def test_add(self): + a = Tensor.empty(1024, 1024, dtype=dtypes.uint8) + b = Tensor.empty(1024, 1024, dtype=dtypes.uint8) + _, mem = get_stats(a+b) + self.assertEqual(mem, 1024*1024*3) # 2 reads + 1 write + + def test_add_const(self): + a = Tensor.empty(1024, 1024, dtype=dtypes.uint8) + _, mem = get_stats(a+3) + self.assertEqual(mem, 1024*1024*2) # 1 read + 1 write + + @unittest.skip("depends on subbuffer working") + def test_add_slice(self): + a = Tensor.empty(1024, 1024, dtype=dtypes.uint8)[:512] + _, mem = get_stats(a+3) + self.assertEqual(mem, 512*1024*2) # 1 read + 1 write + + def test_expanded(self): + a = Tensor.empty(1024, 1, dtype=dtypes.uint8).expand(1024, 1024) + b = Tensor.empty(1024, 1024, dtype=dtypes.uint8) + _, mem = get_stats(a+b) + self.assertEqual(mem, 1024*1024*2 + 1024) # 1 full read + 1 lil read + 1 write + + def test_both_expanded(self): + # TODO: this probably should be a full write + a = Tensor.empty(1024, 1, dtype=dtypes.uint8).expand(1024, 1024) + b = Tensor.empty(1024, 1, dtype=dtypes.uint8).expand(1024, 1024) + _, mem = get_stats(a+b) + self.assertEqual(mem, 1024*1024 + 2*1024) # 2 lil reads + 1 write + + def test_self_add(self): + a = Tensor.empty(1024, 1024, dtype=dtypes.uint8) + _, mem = get_stats(a+a) + self.assertEqual(mem, 1024*1024*2) # 1 read + 1 write + + def test_self_add_transposed(self): + a = Tensor.empty(1024, 1024, dtype=dtypes.uint8) + _, mem = get_stats(a+a.T) + self.assertEqual(mem, 1024*1024*2) # 1 read + 1 write + + def test_self_add_assign(self): + a = Tensor.empty(1024, 1024, dtype=dtypes.uint8).realize() + _, mem = get_stats(a.assign(a+a)) + self.assertEqual(mem, 1024*1024*2) # 1 read + 1 write + + @unittest.skipIf(Device.DEFAULT == "CPU", "test copy to CPU from other device") + def test_copyout(self): + a = Tensor.empty(32, dtype=dtypes.uint8).to("CPU") + _, mem = get_stats(a) + self.assertEqual(mem, 32*1) + a = Tensor.empty(32, dtype=dtypes.uint32).to("CPU") + _, mem = get_stats(a) + self.assertEqual(mem, 32*4) + +# NOTE: this still isn't testing unroll using the acc +@unittest.skipUnless(getenv("PYTHON"), "only run test on emulated tensor cores") +class TestUOpsStatsMatmulHalf(unittest.TestCase): + def test_simple_matmul_half(self, N=16): + GlobalCounters.reset() + a, b = Tensor.empty(N, N, dtype=dtypes.half), Tensor.empty(N, N, dtype=dtypes.half) + c = a.matmul(b) + c.realize() + expected_ops = N ** 3 * 2 + self.assertEqual(expected_ops, GlobalCounters.global_ops) + + def test_bigger_matmul_half(self): self.test_simple_matmul_half(64) + + def test_batched_matmul_half(self, N=16): + GlobalCounters.reset() + a, b = Tensor.empty(4, N, N, dtype=dtypes.half), Tensor.empty(1, N, N, dtype=dtypes.half) + c = a.matmul(b) + c.realize() + expected_ops = 4 * N ** 3 * 2 + self.assertEqual(expected_ops, GlobalCounters.global_ops) + +class TestUOpsStats(unittest.TestCase): + @unittest.skipIf(getenv("PTX"), "wrong in PTX") + def test_simple_add(self): + a = Tensor.empty(100,100) + b = Tensor.empty(100,100) + c = a+b + ops, mem = get_stats(c) + expected_ops = c.numel() + expected_mem = a.nbytes() + b.nbytes() + c.nbytes() + self.assertEqual(mem, expected_mem) + # NOTE; ops also include indexing ops + assert expected_ops <= ops and ops <= expected_ops * 2 + + @unittest.skipIf(getenv("PTX"), "wrong in PTX") + def test_simple_add_sq(self): + a = Tensor.empty(100,100) + b = Tensor.empty(100,100) + c = (a+b)*(a+b) + ops, mem = get_stats(c) + expected_ops = c.numel()*2 + expected_mem = a.nbytes() + b.nbytes() + c.nbytes() + self.assertEqual(mem, expected_mem) + # NOTE; ops also include indexing ops + assert expected_ops <= ops and ops <= expected_ops * 2 + + def test_simple_matmul(self, M=1024, N=1024, K=1024): + a = Tensor.empty(M,N) + b = Tensor.empty(N,K) + c = a@b + ops, mem = get_stats(c) + expected_ops = c.numel() * N * 2 + required_mem = a.nbytes() + b.nbytes() + c.nbytes() + assert expected_ops <= ops and ops <= expected_ops * 1.2 + # NOTE: it's hard to assert on the memory here, all depends on caching + assert required_mem <= mem + + def test_simple_matmul_8192(self): self.test_simple_matmul(8192, 8192, 8192) + + #MULACC should have the same stats as MUL + ADD + def test_mulacc(self): + globl = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), tuple()) + o1 = UOp(Ops.CONST, dtypes.int, tuple(), 1) + o2 = UOp(Ops.CONST, dtypes.int, tuple(), 2) + u1 = UOp(Ops.LOAD, dtypes.int, (globl.index(o1),)) + u2 = UOp(Ops.LOAD, dtypes.int, (globl.index(o2),)) + u3 = UOp(Ops.CONST, dtypes.int, tuple(), 3) + u4 = UOp(Ops.MUL, dtypes.int, (u1,u2)) + u5 = UOp(Ops.ADD, dtypes.int, (u4,u3)) + uops = full_rewrite(u5.sink()) + + globl = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), tuple()) + o1 = UOp(Ops.CONST, dtypes.int, tuple(), 1) + o2 = UOp(Ops.CONST, dtypes.int, tuple(), 2) + u1 = UOp(Ops.LOAD, dtypes.int, (globl.index(o1),)) + u2 = UOp(Ops.LOAD, dtypes.int, (globl.index(o2),)) + u3 = UOp(Ops.CONST, dtypes.int, tuple(), 3) + u4 = UOp(Ops.MULACC, dtypes.int, (u1,u2,u3)) + uops_fma = full_rewrite(u4.sink()) + + self.assertEqual(flops_mem(uops), flops_mem(uops_fma)) + +N = 64 +@unittest.skipIf(getenv("PTX"), "wrong in PTX") # maybe? +class TestStatsOptimized(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.ast_gemm = (Tensor.empty(N, N) @ Tensor.empty(N, N)).schedule()[-1].ast + cls.ast_reduce = (Tensor.empty(N*N).sum()).schedule()[-1].ast + + def check_gemm(self, p:ProgramSpec, extra_flops=0): + #p.uops.print() + #print(p.src) + print(p.name, p.estimates.ops, p.estimates.mem, p.estimates.lds) + self.assertEqual(p.estimates.ops, 2*N*N*N + extra_flops) # N**3 mulaccs + self.assertEqual(p.estimates.mem, 3*N*N*4) # 3 NxN mats with floats + + def test_gemm(self): + p = Kernel(self.ast_gemm).to_program() + self.check_gemm(p) + self.assertEqual(p.estimates.lds, 2*N*N*N*4 + 4*N*N) + + def test_gemm_tc_unroll(self): + k = Kernel(self.ast_gemm) + if not k.apply_tensor_cores(): self.skipTest("no tensor cores") + k.apply_opt(Opt(OptOps.UNROLL, 0, 2)) + p = k.to_program() + print(p.src) + self.check_gemm(p) + + # this is a good lesson about why UPCASTing is a good idea + + def test_gemm_one_upcasted(self): + k = Kernel(self.ast_gemm) + k.apply_opt(Opt(OptOps.UPCAST, 0, 4)) + p = k.to_program() + self.check_gemm(p) + self.assertEqual(p.estimates.lds, N*N*N*4 + N*N*N*4//4 + 4*N*N) + + def test_gemm_upcasted(self): + k = Kernel(self.ast_gemm) + k.apply_opt(Opt(OptOps.UPCAST, 0, 4)) + k.apply_opt(Opt(OptOps.UPCAST, 1, 4)) + k.apply_opt(Opt(OptOps.UNROLL, 0, 4)) + p = k.to_program() + self.check_gemm(p) + self.assertEqual(p.estimates.lds, 2*N*N*N*4//4 + 4*N*N) + + def test_gemm_upcasted_locals(self): + k = Kernel(self.ast_gemm) + k.apply_opt(Opt(OptOps.UPCAST, 0, 4)) + k.apply_opt(Opt(OptOps.UPCAST, 1, 4)) + try: + k.apply_opt(Opt(OptOps.LOCAL, 0, 5)) + k.apply_opt(Opt(OptOps.LOCAL, 1, 5)) + except KernelOptError: + raise unittest.SkipTest("no locals") + p = k.to_program() + self.check_gemm(p) + self.assertEqual(p.estimates.lds, 2*N*N*N*4//4 + 4*N*N) + + def test_gemm_group(self): + k = Kernel(self.ast_gemm) + try: + k.apply_opt(Opt(OptOps.GROUP, 0, 4)) + except KernelOptError: + raise unittest.SkipTest("no locals") + SZ = N*N*4 + p = k.to_program() + # NOTE: these are sort of wrong. they aren't honoring the IF statement + self.check_gemm(p, extra_flops=SZ*4) + self.assertEqual(p.estimates.lds, 2*N*N*N*4 + SZ*4 + (SZ*4 + 4*N*N)*4) + + def test_reduce(self): + k = Kernel(self.ast_reduce) + p = k.to_program() + print(p.name, p.estimates.ops, p.estimates.mem, p.estimates.lds) + self.assertEqual(p.estimates.ops, N*N) + self.assertEqual(p.estimates.mem, N*N*4 + 4) + + def test_reduce_group(self): + k = Kernel(self.ast_reduce) + try: + k.apply_opt(Opt(OptOps.GROUP, 0, 50)) + except KernelOptError: + raise unittest.SkipTest("no locals") + p = k.to_program() + # NOTE: these are wrong, they don't respect the if statement + print(p.name, p.estimates.ops, p.estimates.mem, p.estimates.lds) + +if __name__ == '__main__': + unittest.main(verbosity=2) diff --git a/tinygrad_repo/test/test_winograd.py b/tinygrad_repo/test/test_winograd.py new file mode 100644 index 000000000..515694c6c --- /dev/null +++ b/tinygrad_repo/test/test_winograd.py @@ -0,0 +1,96 @@ +import unittest +import numpy as np +from tinygrad import Tensor, GlobalCounters, dtypes, Context, nn +from tinygrad.uop.ops import Ops +from tinygrad.helpers import Timing, CI, Profiling, WINO, DEBUG, getenv +from tinygrad.opt.kernel import Kernel +from tinygrad.opt.heuristic import hand_coded_optimizations + +class TestWinogradClose(unittest.TestCase): + def test_close(self): + inp = Tensor.rand(1, 16, 16, 16) + conv = nn.Conv2d(16, 16, 3) + conv(inp).realize() # warmup + GlobalCounters.reset() + print("non winograd") + with Context(WINO=0): + cmp = conv(inp).realize() # warmup + GlobalCounters.reset() + print("winograd") + with Context(WINO=1): + test = conv(inp).realize() + np.testing.assert_allclose(cmp.numpy(), test.numpy(), atol=1e-5) + +class TestWinograd(unittest.TestCase): + def setUp(self): + self.old = WINO.value + WINO.value = 1 + def tearDown(self): + WINO.value = self.old + + def test_speed(self): + x = Tensor.empty(1,4,9,9) + w = Tensor.empty(4,4,3,3) + + with Timing("running conv: "): + out = Tensor.conv2d(x, w) + + with Timing("scheduling: "): + sched = out.schedule() + + for i,s in enumerate(sched): + if s.ast.op is not Ops.SINK: continue + ops = s.ast.toposort() + with Timing(f"linearize {i} with {len(ops):4d} ops: "): + l = Kernel(s.ast) + l.apply_opts(hand_coded_optimizations(l)) + assert len(l.sts) <= 256 # just the current value to prevent regression + if DEBUG >= 2: print(f"{len(l.sts):4d} shapetrackers with max {max(len(x.views) for x in l.sts)} views") + for st in l.sts: + assert len(st.views) <= 2, "too many views in winograd" + if DEBUG >= 3: + print(f"{len(st.views):3d} views") + for v in st.views: print(v) + + def test_profile(self): + x,w = Tensor.rand(1,4,9,9).realize(), Tensor.rand(4,4,3,3).realize() + with Profiling(enabled=not CI, sort='time'): + out = Tensor.conv2d(x,w).realize() + out.numpy() + + def test_four_kernels(self): + x,w = Tensor.rand(1,4,9,9).realize(), Tensor.rand(4,4,3,3).realize() + GlobalCounters.reset() + out = Tensor.conv2d(x,w).realize() + assert GlobalCounters.kernel_count == 4 + out.numpy() + + @unittest.skipIf(getenv("PTX"), "winograd uses too much in PTX") + def test_counters(self): + IC, OC, X, Y = 4,4,9,9 + #OC, IC, X, Y = 512, 256, 8, 8 + x,w = Tensor.rand(1,IC,Y,X).realize(), Tensor.rand(OC,IC,3,3).realize() + GlobalCounters.reset() + Tensor.conv2d(x,w).realize() + ops_wino, mem_wino = GlobalCounters.global_ops, GlobalCounters.global_mem + WINO.value = 0 + GlobalCounters.reset() + Tensor.conv2d(x,w).realize() + ops_normal, mem_normal = GlobalCounters.global_ops, GlobalCounters.global_mem + + ops_ratio, mem_ratio = ops_wino/ops_normal, mem_wino/mem_normal + print(f"ops: normal {ops_normal:9d} wino {ops_wino:9d} ratio {ops_ratio:.2f}") + print(f"mem: normal {mem_normal:9d} wino {mem_wino:9d} ratio {mem_ratio:.2f}") + self.assertLess(ops_ratio, 2.6) # TODO: there's issues with factorization now + self.assertLess(mem_ratio, 10) + + def test_dtype(self): + IC, OC, X, Y = 4,4,9,9 + x,w = Tensor.empty(1,IC,Y,X), Tensor.empty(OC,IC,3,3) + self.assertEqual(Tensor.conv2d(x,w).dtype, dtypes.default_float) + + x,w = Tensor.empty(1,IC,Y,X,dtype=dtypes.half), Tensor.empty(OC,IC,3,3,dtype=dtypes.half) + self.assertEqual(Tensor.conv2d(x,w).dtype, dtypes.half) + +if __name__ == '__main__': + unittest.main(verbosity=2) diff --git a/tinygrad_repo/test/test_zero_copy.py b/tinygrad_repo/test/test_zero_copy.py new file mode 100644 index 000000000..c8625780d --- /dev/null +++ b/tinygrad_repo/test/test_zero_copy.py @@ -0,0 +1,27 @@ +import unittest +from tinygrad import Tensor, Device +import time + +def time_tensor_numpy(out:Tensor): + times = [] + for _ in range(5): + st = time.perf_counter() + out.uop.base.realized.as_buffer(allow_zero_copy=True) + et = time.perf_counter() - st + times.append(et) + return min(times) + +N = 4096 +class TestZeroCopy(unittest.TestCase): + @unittest.skipIf(Device.DEFAULT not in {"CPU", "LLVM", "METAL"}, "device isn't zero copy") + def test_zero_copy_from_default_to_cpu(self): + demo = Tensor.rand(1).realize() + t1 = time_tensor_numpy(demo) + out = Tensor.rand(N, N).realize() + t2 = time_tensor_numpy(out) + gbps = out.nbytes()*1e-9/max(t2-t1, 1e-10) + print(f"time(base): {t1*1e3:.2f} ms, time(copy): {t2*1e3:.2f} ms : copy speed {gbps:.2f} GB/s") + self.assertGreater(gbps, 600) # more than 600 GB/s = no copy + +if __name__ == '__main__': + unittest.main(verbosity=2) diff --git a/tinygrad_repo/test/testextra/__init__.py b/tinygrad_repo/test/testextra/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/tinygrad_repo/test/testextra/test_bench_log.py b/tinygrad_repo/test/testextra/test_bench_log.py new file mode 100644 index 000000000..dd63f916e --- /dev/null +++ b/tinygrad_repo/test/testextra/test_bench_log.py @@ -0,0 +1,108 @@ +import unittest, time +from unittest.case import skipIf + +from extra.bench_log import BenchEvent, InstantBenchEvent, WallTimeEvent, KernelTimeEvent, log_event_instant, _events, clear_events +from tinygrad.helpers import Context, CI +from tinygrad.tensor import Tensor +from tinygrad.device import Device + +class TestBenchLog(unittest.TestCase): + def setUp(self): + clear_events() + + def test_log_single_wall_time(self): + for event in BenchEvent: + with WallTimeEvent(event): + time.sleep(0.1) + + # check event list + for event in BenchEvent: + self.assertEqual(len(_events[event]["wall"]), 1) + self.assertGreater(_events[event]["wall"][0], 0) + + def test_log_double_wall_time(self): + for event in BenchEvent: + with WallTimeEvent(event): + time.sleep(0.1) + + for event in reversed(BenchEvent): + with WallTimeEvent(event): + time.sleep(0.2) + + # check event list + for event in BenchEvent: + self.assertEqual(len(_events[event]["wall"]), 2) + self.assertGreater(_events[event]["wall"][0], 0) + self.assertGreater(_events[event]["wall"][1], 0) + + @skipIf(CI and Device.DEFAULT == "CUDA", "ci cuda timing is not accurate") + def test_log_single_kernel_time(self): + wall_times = [] + + with Context(DEBUG=2): + for event in BenchEvent: + with KernelTimeEvent(event): + st = time.perf_counter() + Tensor.rand(32, 32).sum().realize().item() + wall_times.append(time.perf_counter() - st) + + # check event list + for event in BenchEvent: + self.assertEqual(len(_events[event]["kernel"]), 1) + self.assertLess(_events[event]["kernel"][0], wall_times[0]) + self.assertGreater(_events[event]["kernel"][0], 0) + + @skipIf(CI and Device.DEFAULT == "CUDA", "ci cuda timing is not accurate") + def test_interleaved_wall_kernel_time(self): + wall_times = [] + with Context(DEBUG=2): + for event in BenchEvent: + with KernelTimeEvent(event): + st = time.perf_counter() + Tensor.rand(32, 32).sum().realize().item() + wall_times.append(time.perf_counter() - st) + + with WallTimeEvent(event): + st = time.perf_counter() + Tensor.rand(32, 32).sum().realize().item() + wall_times.append(time.perf_counter() - st) + + # check event list + for event in BenchEvent: + self.assertEqual(len(_events[event]["wall"]), 1) + self.assertEqual(len(_events[event]["kernel"]), 1) + self.assertLess(_events[event]["kernel"][0], wall_times[0]) + self.assertGreater(_events[event]["kernel"][0], 0) + + @skipIf(CI and Device.DEFAULT == "CUDA", "ci cuda timing is not accurate") + def test_stacked_wall_kernel_time(self): + with Context(DEBUG=2): + for event in BenchEvent: + with KernelTimeEvent(event): + with WallTimeEvent(event): + Tensor.rand(32, 32).sum().realize().item() + + for event in BenchEvent: + with WallTimeEvent(event): + with KernelTimeEvent(event): + Tensor.rand(32, 32).sum().realize().item() + + for event in BenchEvent: + self.assertEqual(len(_events[event]["wall"]), 2) + self.assertEqual(len(_events[event]["kernel"]), 2) + self.assertLess(_events[event]["kernel"][0], _events[event]["wall"][0]) + self.assertGreater(_events[event]["kernel"][0], 0) + self.assertLess(_events[event]["kernel"][1], _events[event]["wall"][1]) + self.assertGreater(_events[event]["kernel"][1], 0) + + def test_log_instant_event(self): + for event in InstantBenchEvent: + log_event_instant(event, 1000) + + # check event list + for event in InstantBenchEvent: + self.assertEqual(len(_events[event]), 1) + self.assertEqual(_events[event][0], 1000) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/testextra/test_export_model.py b/tinygrad_repo/test/testextra/test_export_model.py new file mode 100644 index 000000000..2b84e71f6 --- /dev/null +++ b/tinygrad_repo/test/testextra/test_export_model.py @@ -0,0 +1,69 @@ +import unittest +from extra.export_model import export_model, EXPORT_SUPPORTED_DEVICE +from tinygrad.tensor import Tensor, Device +from tinygrad import dtypes +import json + +class MockMultiInputModel: + def forward(self, x1, x2, x3): + return x1 + x2 + x3 + +class MockMultiOutputModel: + def __call__(self, x1): + return x1 + 2.0, x1.pad(((0, 0), (0, 1))) + 1.0 + +# TODO: move compile_efficientnet tests here +@unittest.skipUnless(Device.DEFAULT in EXPORT_SUPPORTED_DEVICE, f"Model export is not supported on {Device.DEFAULT}") +class TextModelExport(unittest.TestCase): + def test_multi_input_model_export(self): + model = MockMultiInputModel() + inputs = [Tensor.rand(2,2), Tensor.rand(2,2), Tensor.rand(2,2)] + prg, inp_sizes, _, _ = export_model(model, "", *inputs) + prg = json.loads(prg) + + assert len(inputs) == len(prg["inputs"]) == len(inp_sizes), f"Model and exported inputs don't match: mdl={len(inputs)}, prg={len(prg['inputs'])}, inp_sizes={len(inp_sizes)}" # noqa: E501 + + for i in range(len(inputs)): + assert f"input{i}" in inp_sizes, f"input{i} not captured in inp_sizes" + assert f"input{i}" in prg["buffers"], f"input{i} not captured in exported buffers" + + for i, exported_input in enumerate(prg["inputs"]): + assert inputs[i].dtype.name == exported_input["dtype"], f"Model and exported input dtype don't match: mdl={inputs[i].dtype.name}, prg={exported_input['dtype']}" # noqa: E501 + + def test_multi_output_model_export(self): + model = MockMultiOutputModel() + input_tensor = Tensor.rand(2,2) + outputs = model(input_tensor) + prg, _, out_sizes, _ = export_model(model, "", input_tensor) + prg = json.loads(prg) + + assert len(outputs) == len(prg["outputs"]) == len(out_sizes), f"Model and exported outputs don't match: mdl={len(outputs)}, prg={len(prg['outputs'])}, inp_sizes={len(out_sizes)}" # noqa: E501 + + for i in range(len(outputs)): + assert f"output{i}" in out_sizes, f"output{i} not captured in out_sizes" + assert f"output{i}" in prg["buffers"], f"output{i} not captured in exported buffers" + + for i, exported_output in enumerate(prg["outputs"]): + assert outputs[i].dtype.name == exported_output["dtype"], f"Model and exported output dtype don't match: mdl={outputs[i].dtype.name}, prg={exported_output['dtype']}" # noqa: E501 + +@unittest.skipUnless(Device.DEFAULT == "WEBGPU", "Testing WebGPU specific model export behavior") +class TextModelExportWebGPU(unittest.TestCase): + def test_exported_input_output_dtypes(self): + class MyModel: + def forward(self, *inputs): return tuple([(inp+2).cast(inp.dtype) for inp in inputs]) + model = MyModel() + # [:-1] because "ulong" and "long" is not supported + inputs = [Tensor.randn(2, dtype=dt) for dt in dtypes.uints[:-1] + dtypes.sints[:-1] + (dtypes.bool, dtypes.float)] + prg, _, _, _ = export_model(model, "webgpu", *inputs) + expected_buffer_types = ["Uint"]*len(dtypes.uints[:-1]) + ["Int"]*len(dtypes.sints[:-1]) + ["Int", "Float"] + for i, expected_buffer_type in enumerate(expected_buffer_types): + dt = inputs[i].dtype + expected_arr_prefix = f"{expected_buffer_type}{dt.itemsize*8}" + # test input buffers + self.assertIn(f"new {expected_arr_prefix}Array(gpuWriteBuffer{i}.getMappedRange()).set(_input{i});", prg) + # test output buffers + self.assertIn(f"const resultBuffer{i} = new {expected_arr_prefix}Array(gpuReadBuffer{i}.size/{dt.itemsize});", prg) + self.assertIn(f"resultBuffer{i}.set(new {expected_arr_prefix}Array(gpuReadBuffer{i}.getMappedRange()));", prg) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/testextra/test_f16_decompress.py b/tinygrad_repo/test/testextra/test_f16_decompress.py new file mode 100644 index 000000000..680687703 --- /dev/null +++ b/tinygrad_repo/test/testextra/test_f16_decompress.py @@ -0,0 +1,16 @@ +import unittest +from extra.f16_decompress import u32_to_f16 +from tinygrad.tensor import Tensor +from tinygrad.device import is_dtype_supported +from tinygrad import dtypes +import numpy as np + +class TestF16Decompression(unittest.TestCase): + @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need float16") + def test_u32_to_f16(self): + a = Tensor.randn(50, dtype=dtypes.float16) + f16_as_u32 = a.bitcast(dtypes.uint32) + f16 = u32_to_f16(f16_as_u32) + ref = a.numpy() + out = f16.numpy().astype(np.float16) + np.testing.assert_allclose(out, ref) diff --git a/tinygrad_repo/test/testextra/test_lr_scheduler.py b/tinygrad_repo/test/testextra/test_lr_scheduler.py new file mode 100644 index 000000000..ce7464ecf --- /dev/null +++ b/tinygrad_repo/test/testextra/test_lr_scheduler.py @@ -0,0 +1,125 @@ +import numpy as np +import torch +import unittest +from tinygrad.tensor import Tensor +from tinygrad.nn.state import get_parameters +from tinygrad.nn.optim import Adam, SGD +from tinygrad.helpers import DEBUG +from extra.lr_scheduler import MultiStepLR, ReduceLROnPlateau, CosineAnnealingLR, OneCycleLR +from extra.training import train, evaluate +from extra.datasets import fetch_mnist + +np.random.seed(1337) +Tensor.manual_seed(1337) + +X_train, Y_train, X_test, Y_test = fetch_mnist() + +class TinyBobNet: + def __init__(self): + self.l1 = Tensor.scaled_uniform(784, 128) + self.l2 = Tensor.scaled_uniform(128, 10) + + def parameters(self): + return get_parameters(self) + + def forward(self, x): + return x.dot(self.l1).relu().dot(self.l2).log_softmax() + +def lr_scheduler_training(sched_fn=None, args=None): + model = TinyBobNet() + optim = Adam(model.parameters(), lr=0.01) + if sched_fn is not None: sched = sched_fn(optim, **args) + for _ in range(25): + train(model, X_train, Y_train, optim, 100) + if sched_fn is not None: + if isinstance(sched, ReduceLROnPlateau): + sched.step(evaluate(model, X_test, Y_test)) + else: + sched.step() + return evaluate(model, X_test, Y_test) + +def current_lr(optim): return optim.param_groups[0]['lr'] if hasattr(optim, 'param_groups') else optim.lr +def get_lrs(optim, sched, epochs, steps=1, accs=None): + lr = current_lr(optim) + if not isinstance(lr, float): lr = lr.numpy()[0] + lrs = [lr] + for e in range(epochs): + for _ in range(steps): + optim.step() + sched.step() if accs is None else sched.step(accs[e]) + lr = current_lr(optim) + if not isinstance(lr, float): lr = lr.numpy()[0] + lrs.append(lr) + return lrs + +class TestLrScheduler(unittest.TestCase): + def setUp(self): + self.old_training = Tensor.training + Tensor.training = True + def tearDown(self): + Tensor.training = self.old_training + + def _test_lr_scheduler(self, tinygrad_sched, torch_sched, epochs, opts, atol, rtol, adam=True): + accs = opts.pop('accs', None) + test_tensor = Tensor([0.], requires_grad=True) # NOTE: optimizers are broken on 0-dim tensors because it broadcasts to [lr] + test_tensor.mean().backward() + if adam: + tinygrad_optim, torch_optim = Adam([test_tensor], lr=0.01), torch.optim.Adam([torch.tensor([0.], requires_grad=True)], lr=0.01) + else: + tinygrad_optim, torch_optim = SGD([test_tensor], lr=0.01), torch.optim.SGD([torch.tensor([0.], requires_grad=True)], lr=0.01) + tinygrad_sched, torch_sched = tinygrad_sched(tinygrad_optim, **opts), torch_sched(torch_optim, **opts) + + tinygrad_lrs = get_lrs(tinygrad_optim, tinygrad_sched, epochs, accs=accs) + torch_lrs = get_lrs(torch_optim, torch_sched, epochs, accs=accs) + + np.testing.assert_allclose(tinygrad_lrs, torch_lrs, atol=atol, rtol=rtol) + + def _test_multisteplr(self, epochs, opts, atol, rtol, adam=True): + self._test_lr_scheduler(MultiStepLR, torch.optim.lr_scheduler.MultiStepLR, epochs, opts, atol, rtol, adam=adam) + def _test_reducelronplateau(self, epochs, opts, atol, rtol): + opts['accs'] = np.random.randn(epochs) + self._test_lr_scheduler(ReduceLROnPlateau, torch.optim.lr_scheduler.ReduceLROnPlateau, epochs, opts, atol, rtol) + def _test_cosineannealinglr(self, epochs, opts, atol, rtol): + opts['T_max'] = epochs + self._test_lr_scheduler(CosineAnnealingLR, torch.optim.lr_scheduler.CosineAnnealingLR, epochs, opts, atol, rtol) + def _test_onecyclelr(self, epochs, opts, atol, rtol): + opts['total_steps'] = epochs + self._test_lr_scheduler(OneCycleLR, torch.optim.lr_scheduler.OneCycleLR, epochs, opts, atol, rtol) + + def test_multisteplr(self): self._test_multisteplr(10, {'milestones': [1, 2, 7]}, 1e-6, 1e-6) + def test_multisteplr_gamma(self): self._test_multisteplr(10, {'milestones': [1, 2, 7], 'gamma': 0.1337}, 1e-6, 1e-6) + + def test_reducelronplateau(self): self._test_reducelronplateau(100, {}, 1e-6, 1e-6) + def test_reducelronplateau_max(self): self._test_reducelronplateau(100, {'mode': 'max'}, 1e-6, 1e-6) + def test_reducelronplateau_factor(self): self._test_reducelronplateau(100, {'factor': 0.1337}, 1e-6, 1e-6) + def test_reducelronplateau_patience(self): self._test_reducelronplateau(100, {'patience': 3}, 1e-6, 1e-6) + def test_reducelronplateau_threshold(self): self._test_reducelronplateau(100, {'threshold': 1e-6}, 1e-6, 1e-6) + def test_reducelronplateau_threshold_mode(self): self._test_reducelronplateau(100, {'threshold_mode': 'abs'}, 1e-6, 1e-6) + + def test_cosineannealinglr(self): self._test_cosineannealinglr(100, {}, 1e-6, 1e-6) + def test_cosineannealinglr_eta_min(self): self._test_cosineannealinglr(100, {'eta_min': 0.001}, 1e-6, 1e-6) + + def test_multistep_2step(self): + # was making this fail with LRU=1, some issue with epoch_counter + if DEBUG>=2: print("first") + self._test_multisteplr(1, {'milestones': [1]}, 1e-6, 1e-6, adam=False) + if DEBUG>=2: print("second") + self._test_multisteplr(1, {'milestones': [1], 'gamma': 0.133}, 1e-6, 1e-6, adam=False) + if DEBUG>=2: print("third") + + def test_onecyclelr(self): self._test_onecyclelr(100, {'pct_start': 0.3, 'anneal_strategy': 'linear', + 'cycle_momentum': False, 'div_factor': 25.0, + 'final_div_factor': 10000.0, 'max_lr':1e-5}, 1e-6, 1e-6) + @unittest.skip("slow") + def test_training(self): + without = lr_scheduler_training() + sched_fns = [MultiStepLR, ReduceLROnPlateau, CosineAnnealingLR, OneCycleLR] + argss = [{'milestones': [5, 7, 10, 15], 'gamma': 0.5}, {'factor': 0.5, 'patience': 2}, {'T_max': 25, 'eta_min': 0.001}, + {'pct_start': 0.3, 'anneal_strategy': 'linear', 'cycle_momentum': False, 'div_factor': 25.0, 'final_div_factor': 10000.0, + 'max_lr':1e-5, 'total_steps': 25}] + for sched_fn, args in zip(sched_fns, argss): + with_sched = lr_scheduler_training(sched_fn, args) + assert with_sched > without + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/testextra/test_mockgpu.py b/tinygrad_repo/test/testextra/test_mockgpu.py new file mode 100644 index 000000000..0f1d61648 --- /dev/null +++ b/tinygrad_repo/test/testextra/test_mockgpu.py @@ -0,0 +1,13 @@ +from tinygrad.helpers import getenv +import unittest, importlib + +@unittest.skipUnless(getenv("MOCKGPU"), 'Testing mockgpu') +class TestMockGPU(unittest.TestCase): + # https://github.com/tinygrad/tinygrad/pull/7627 + def test_import_typing_extensions(self): + import test.mockgpu.mockgpu # noqa: F401 # pylint: disable=unused-import + import typing_extensions + importlib.reload(typing_extensions) # pytest imports typing_extension before mockgpu + +if __name__ == '__main__': + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/unit/__init__.py b/tinygrad_repo/test/unit/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/tinygrad_repo/test/unit/test_allreduce.py b/tinygrad_repo/test/unit/test_allreduce.py new file mode 100644 index 000000000..a30309660 --- /dev/null +++ b/tinygrad_repo/test/unit/test_allreduce.py @@ -0,0 +1,29 @@ +import unittest +from tinygrad import Tensor +from tinygrad.helpers import Context +from tinygrad.uop.ops import Ops + +class TestRingAllReduce(unittest.TestCase): + def test_schedule_ring(self): + with Context(RING=2): + N = 4 + ds = tuple(f"CPU:{i}" for i in range(N)) + t = Tensor.empty(N, N*100).shard(ds, axis=0).realize() + schedules = t.sum(0).schedule_with_vars()[0] + copies = [si for si in schedules if si.ast.op is Ops.COPY] + pairs = [(c.bufs[0].device, c.bufs[1].device) for c in copies] + # N*(N-1) scatter reduce, and N*(N-1) allgather + self.assertEqual(len(pairs), N*(N-1)*2) + # copy topology forms a ring + self.assertEqual(len(set(pairs)), N) + + def test_correct_ring(self): + with Context(RING=2): + N = 4 + ds = tuple(f"CPU:{i}" for i in range(N)) + t = Tensor.ones(N, N*100).contiguous().shard(ds, axis=0).realize() + out = t.sum(0) + self.assertListEqual(out.tolist(), [4]*N*100) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_attention.py b/tinygrad_repo/test/unit/test_attention.py new file mode 100644 index 000000000..9929dbc32 --- /dev/null +++ b/tinygrad_repo/test/unit/test_attention.py @@ -0,0 +1,20 @@ +import unittest +from tinygrad import Tensor, dtypes + +# TODO: test_scheduler, but just in uint +class TestAttention(unittest.TestCase): + def test_half_qkv_buffers(self): + BS, seqlen, dim = 10, 4, 100 + q = Tensor.ones(BS, seqlen, dim, dtype=dtypes.half).contiguous().realize() + k = Tensor.ones(BS, seqlen, dim, dtype=dtypes.half).contiguous().realize() + v = Tensor.ones(BS, seqlen, dim, dtype=dtypes.half).contiguous().realize() + attn = q.scaled_dot_product_attention(k, v) + sched = attn.schedule() + # attention has 5 kernels now + self.assertEqual(len(sched), 5) + softmax_inputs = sched[1:4] + for si in softmax_inputs: + assert all(b.dtype == dtypes.half for b in si.bufs), f"non half {si.bufs=}" + +if __name__ == '__main__': + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/unit/test_block_reorder.py b/tinygrad_repo/test/unit/test_block_reorder.py new file mode 100644 index 000000000..cf6df95aa --- /dev/null +++ b/tinygrad_repo/test/unit/test_block_reorder.py @@ -0,0 +1,76 @@ +import unittest, random +from tinygrad.dtype import dtypes +from tinygrad.uop.ops import print_uops, UOp, Ops +from tinygrad.codegen.linearize import block_reorder +from tinygrad.renderer.cstyle import OpenCLRenderer + +def is_toposorted(lst:list[UOp]): + seen = set() + for u in lst: + if any(p not in seen for p in u.src): return False + seen.add(u) + return True + +class TestBlockReorder(unittest.TestCase): + def _test_randomize(self, golden:list[UOp]): + # test random order is always same + for _ in range(50): + # shuffle and form a valid toposort + lst = golden[:] + random.shuffle(lst) + topolst = [] + for u in lst: + for p in u.toposort(): + if p not in topolst: topolst.append(p) + assert is_toposorted(topolst) + + for x,y in zip(golden, this_order:=block_reorder(topolst)): + if x is not y: + print_uops(golden) + print_uops(this_order) + self.assertIs(x, y) + + def _test_render(self, golden:list[UOp]): + return OpenCLRenderer().render(golden) + + def test_loads(self): + a = UOp(Ops.DEFINE_GLOBAL, dtype=dtypes.float.ptr(), arg=0) + b = UOp(Ops.DEFINE_GLOBAL, dtype=dtypes.float.ptr(), arg=1) + c = UOp(Ops.DEFINE_GLOBAL, dtype=dtypes.float.ptr(), arg=2) + v1 = UOp(Ops.SPECIAL, dtype=dtypes.int, arg=("gidx0", 4)) + v2 = UOp(Ops.SPECIAL, dtype=dtypes.int, arg=("gidx1", 4)) + v1 = v1*27 + v2 = v2*4 + loads = [ + a.index(v1).load(dtype=dtypes.float), + a.index(v1+1).load(dtype=dtypes.float), + a.index(v1+2).load(dtype=dtypes.float), + a.index(v1+3).load(dtype=dtypes.float), + b.index(v2).load(dtype=dtypes.float), + b.index(v2+1).load(dtype=dtypes.float), + b.index(v2+2).load(dtype=dtypes.float), + b.index(v2+3).load(dtype=dtypes.float)] + #random.shuffle(loads) + sink = c.store(sum(loads)).sink() + + # determine golden order + golden = block_reorder(list(sink.toposort())) + + # render for test + print(self._test_render(golden)) + #print_uops(golden) + + # assert the loads are in this order + self.assertListEqual([g.src[0].src[1].render() for g in golden if g.op is Ops.LOAD], + ['(gidx1*4)', '((gidx1*4)+1)', '((gidx1*4)+2)', '((gidx1*4)+3)', + '(gidx0*27)', '((gidx0*27)+1)', '((gidx0*27)+2)', '((gidx0*27)+3)']) + + # assert math is after loads + first_math = [i for i,g in enumerate(golden) if g.op is Ops.ADD and g.dtype == dtypes.float][0] + assert not any(x.op is Ops.LOAD for x in golden[first_math:]) + + # confirm the sort is stable + self._test_randomize(golden) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_conv.py b/tinygrad_repo/test/unit/test_conv.py new file mode 100644 index 000000000..6091a9c46 --- /dev/null +++ b/tinygrad_repo/test/unit/test_conv.py @@ -0,0 +1,132 @@ +import unittest +import numpy as np +from tinygrad.tensor import Tensor +from tinygrad.helpers import Context + +class TestConv(unittest.TestCase): + def test_simple(self): + x = Tensor.ones(1,12,16,32).contiguous().realize() + w = Tensor.ones(32,12,3,3).contiguous().realize() + ret = x.conv2d(w, stride=(2,2), padding=(1,1)).numpy() + # it's not 108 around the padding + assert (ret[:, :, 1:-1, 1:-1] == 108).all() + assert ret[0,0,0,0] == 48 + assert ret[0,0,0,1] == 72 + + def test_simple_rand(self): + x = Tensor.rand(1,12,16,32) + w = Tensor.rand(32,12,3,3) + x.conv2d(w, stride=(2,2), padding=(1,1)).numpy() + + def test_many_simple(self): + x = Tensor(np.arange(8*2*8).reshape(1,8,2,8).astype(np.float32)) + #w = Tensor(np.arange(8*8*1*1).reshape(8,8,1,1).astype(np.float32)) + w = Tensor.eye(8).reshape((8,8,1,1)) + ret = x.conv2d(w, stride=(1,2), padding=(0,0)).numpy() + print(ret) + + def test_lazycache(self): + x = Tensor.rand(1, 32) + y = Tensor.rand(32) + out = x + y.reshape((1,32,1)).reshape((1,32)) + y.reshape((1,32,1)).reshape((1,32)) + out.numpy() + + def test_simple_biased(self): + C = 8 + x = Tensor.rand(1,C,5,5) + w = Tensor.eye(C).reshape((C,C,1,1)) + b = Tensor(np.arange(C).astype(np.float32)) + ret = Tensor.conv2d(x,w,b).relu().conv2d(w,b) + + print(ret.numpy()) + + def test_two_binops_no_rerun_small(self): + x = Tensor.rand(1,1,32,32) + w = Tensor.rand(1,1,3,3) + out = x.conv2d(w, padding=(1,1)) + np.testing.assert_allclose(out.relu().numpy(), np.maximum(out.numpy(), 0)) + + def test_two_binops_no_rerun(self): + x = Tensor.randn(1,12,16,32) + w = Tensor.randn(32,12,3,3) + out = x.conv2d(w, stride=(2,2), padding=(1,1)) + r1, r2 = out.relu(), (out-1) + np.testing.assert_allclose(r1.numpy(), np.maximum(out.numpy(), 0)) + np.testing.assert_allclose(r2.numpy(), out.numpy() - 1) + + def test_two_overlapping_binops_no_rerun(self): + x = Tensor.randn(1,12,16,32) + w = Tensor.randn(32,12,3,3) + out = x.conv2d(w, stride=(2,2), padding=(1,1)) + r1, r2 = out.relu(), out.elu() + np.testing.assert_allclose(r1.numpy(), np.maximum(out.numpy(), 0)) + np.testing.assert_allclose(r2.numpy(), np.where(out.numpy() > 0, out.numpy(), (np.exp(out.numpy()) - 1)), atol=1e-5) + + def test_two_overlapping_binops_no_rerun_wino(self): + with Context(WINO=1): + x = Tensor.randn(1,4,16,16) + w = Tensor.randn(6,4,3,3) + out = x.conv2d(w, padding=(1,1)) + r1, r2 = out.relu(), out.elu() + np.testing.assert_allclose(r1.numpy(), np.maximum(out.numpy(), 0)) + np.testing.assert_allclose(r2.numpy(), np.where(out.numpy() > 0, out.numpy(), (np.exp(out.numpy()) - 1)), atol=1e-5) + + def test_first_three(self): + x = Tensor.rand(1,12,16,32) + + w = Tensor.rand(32,12,3,3) + x = x.conv2d(w, stride=(2,2), padding=(1,1)).elu() + + w = Tensor.rand(32,1,3,3) + x = x.conv2d(w, padding=(1,1), groups=32).elu() + + w = Tensor.rand(16,32,1,1) + x = x.conv2d(w).elu() + + x = x.numpy() + print(x.shape) + + def test_elu(self): + x = Tensor.rand(1,12,16,32) + + w = Tensor.rand(32,12,3,3) + x = x.conv2d(w, stride=(2,2), padding=(1,1)) + + x = x.elu() + + w = Tensor.rand(32,1,3,3) + x = x.conv2d(w, padding=(1,1), groups=32) + x.numpy() + + def test_reduce_relu(self): + x = Tensor.rand(1,12,16,32) + x = x.sum(keepdim=True).relu() + x.numpy() + + def test_bias(self): + from tinygrad.nn import Conv2d + x = Tensor.rand(1,12,16,32) + c = Conv2d(12, 32, 3) + x = c(x).relu() + w = Tensor.uniform(32, 1, 3, 3) + x = x.conv2d(w, groups=32) + x.numpy() + + def test_multiadd(self): + w = Tensor.rand(32) + x = Tensor.rand(32).relu() + (w+x).numpy() + + def test_reorder(self): + x = Tensor.rand(1,12,16,32) + w = Tensor.rand(12,12,3,3) + x = x.conv2d(w, padding=(1,1)) + print(x.shape) + x = x.reshape((1, 12, 32, 16)) + x += 1 + x += 1 + x = x.reshape((1, 12, 16, 32)) + x.numpy() + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_conv_shapetracker.py b/tinygrad_repo/test/unit/test_conv_shapetracker.py new file mode 100644 index 000000000..e812827ac --- /dev/null +++ b/tinygrad_repo/test/unit/test_conv_shapetracker.py @@ -0,0 +1,55 @@ +#!/usr/bin/env python +import unittest +from tinygrad.uop.ops import Ops +from tinygrad.tensor import Tensor +from tinygrad.nn import Conv2d +from tinygrad.shape.shapetracker import ShapeTracker, View +from tinygrad.helpers import prod +from test.unit.test_shapetracker import shapetracker_getitem + +class TestConvShapetracker(unittest.TestCase): + def test_conv_3x3_one_view(self): + conv = Conv2d(16, 32, (3, 3)) + # first run to init the weights, they are scheduled. + conv(Tensor.empty(1, 16, 10, 10)).schedule() + # run it again to get the kernels + sched = [si for si in conv(Tensor.empty(1, 16, 10, 10)).schedule() if si.ast.op is Ops.SINK] + assert len(sched) == 1, f"conv should only have one kernel, getting {len(sched)}" + for st in [x.st_arg for x in sched[0].ast.toposort() if x.op is Ops.LOAD]: + assert len(st.views) == 1 + + def test_conv_2x2_backward_one_view(self): + X = Tensor.rand(1, 1, 3, 3, requires_grad=True) + conv = Conv2d(1, 1, (2, 2), bias=False) + conv(X).mean().backward() + si = X.grad.schedule()[-1] + print(si) + ldb = [x for x in si.ast.toposort() if x.op is Ops.LOAD][0] + st: ShapeTracker = ldb.st_arg.simplify() + print(si.bufs[1].size) + self.assertEqual(si.bufs[1].size, st.real_size()) + for v in st.views: print(v) + + # same st + test_st = ShapeTracker(( + View(shape=(1, 1, 2, 4, 2, 4), strides=(0, 0, 2, 8, 1, 4), offset=0, mask=((0, 1), (0, 1), (0, 2), (0, 2), (0, 2), (0, 2)), contiguous=False), + View(shape=(1, 1, 1, 1, 3, 3, 3, 3), strides=(0, 0, 0, 0, 24, 8, 3, 1), offset=0, + mask=((0, 1), (0, 1), (0, 1), (0, 1), (0, 2), (0, 3), (0, 2), (0, 3)), contiguous=False))) + #test_st = ShapeTracker(( + # View(shape=(2,4), strides=(1,4), offset=0, mask=None, contiguous=False), + #)).simplify() + #View(shape=(1, 1, 2, 4, 2, 4), strides=(0, 0, 2, 8, 1, 4), offset=0, mask=((0, 1), (0, 1), (0, 2), (0, 2), (0, 2), (0, 2)), contiguous=False), + #View(shape=(1, 1, 1, 1, 3, 3, 3, 3), strides=(0, 0, 0, 0, 24, 8, 3, 1), offset=0, + # mask=((0, 1), (0, 1), (0, 1), (0, 1), (0, 2), (0, 3), (0, 2), (0, 3)), contiguous=False))).simplify() + print("*** new ***") + for v in test_st.views: print(v) + for i in range(prod(st.shape)): + i1, i2 = shapetracker_getitem(st, i), shapetracker_getitem(test_st, i) + print(i, i1, i2, si.bufs[1].size, i1==i2) + #self.assertEqual(i1, i2) + + with self.assertRaises(AssertionError): + assert len(st.views) <= 2 + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_device.py b/tinygrad_repo/test/unit/test_device.py new file mode 100644 index 000000000..f055e8e5f --- /dev/null +++ b/tinygrad_repo/test/unit/test_device.py @@ -0,0 +1,65 @@ +#!/usr/bin/env python +import unittest, os, subprocess, sys +from tinygrad import Tensor +from tinygrad.device import Device, Compiler +from tinygrad.helpers import diskcache_get, diskcache_put, getenv, Context + +class TestDevice(unittest.TestCase): + def test_canonicalize(self): + self.assertEqual(Device.canonicalize(None), Device.DEFAULT) + self.assertEqual(Device.canonicalize("CPU"), "CPU") + self.assertEqual(Device.canonicalize("cpu"), "CPU") + self.assertEqual(Device.canonicalize("GPU"), "GPU") + self.assertEqual(Device.canonicalize("GPU:0"), "GPU") + self.assertEqual(Device.canonicalize("gpu:0"), "GPU") + self.assertEqual(Device.canonicalize("GPU:1"), "GPU:1") + self.assertEqual(Device.canonicalize("gpu:1"), "GPU:1") + self.assertEqual(Device.canonicalize("GPU:2"), "GPU:2") + self.assertEqual(Device.canonicalize("disk:/dev/shm/test"), "DISK:/dev/shm/test") + self.assertEqual(Device.canonicalize("disk:000.txt"), "DISK:000.txt") + + def test_getitem_not_exist(self): + with self.assertRaises(ModuleNotFoundError): + Device["TYPO"] + + def test_lowercase_canonicalizes(self): + device = Device.DEFAULT + Device.DEFAULT = device.lower() + self.assertEqual(Device.canonicalize(None), device) + Device.DEFAULT = device + +class MockCompiler(Compiler): + def __init__(self, key): super().__init__(key) + def compile(self, src) -> bytes: return src.encode() + +class TestCompiler(unittest.TestCase): + def test_compile_cached(self): + diskcache_put("key", "123", None) # clear cache + getenv.cache_clear() + with Context(DISABLE_COMPILER_CACHE=0): + self.assertEqual(MockCompiler("key").compile_cached("123"), str.encode("123")) + self.assertEqual(diskcache_get("key", "123"), str.encode("123")) + + def test_compile_cached_disabled(self): + diskcache_put("disabled_key", "123", None) # clear cache + getenv.cache_clear() + with Context(DISABLE_COMPILER_CACHE=1): + self.assertEqual(MockCompiler("disabled_key").compile_cached("123"), str.encode("123")) + self.assertIsNone(diskcache_get("disabled_key", "123")) + + def test_device_compile(self): + getenv.cache_clear() + with Context(DISABLE_COMPILER_CACHE=1): + a = Tensor([0.,1.], device=Device.DEFAULT).realize() + (a + 1).realize() + +class TestRunAsModule(unittest.TestCase): + def test_module_runs(self): + p = subprocess.run([sys.executable, "-m", "tinygrad.device"],stdout=subprocess.PIPE, stderr=subprocess.PIPE, + env={**os.environ, "DEBUG": "1"}, timeout=10,) + out = (p.stdout + p.stderr).decode() + self.assertEqual(p.returncode, 0, msg=out) + self.assertIn("CPU", out) # for sanity check + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/unit/test_disk_cache.py b/tinygrad_repo/test/unit/test_disk_cache.py new file mode 100644 index 000000000..6ddf1abe7 --- /dev/null +++ b/tinygrad_repo/test/unit/test_disk_cache.py @@ -0,0 +1,108 @@ +import unittest +import pickle +from tinygrad.helpers import diskcache_get, diskcache_put, diskcache, diskcache_clear + +def remote_get(table,q,k): q.put(diskcache_get(table, k)) +def remote_put(table,k,v): diskcache_put(table, k, v) + +class DiskCache(unittest.TestCase): + def test_putget(self): + table = "test_putget" + diskcache_put(table, "hello", "world") + self.assertEqual(diskcache_get(table, "hello"), "world") + diskcache_put(table, "hello", "world2") + self.assertEqual(diskcache_get(table, "hello"), "world2") + + def test_putcomplex(self): + table = "test_putcomplex" + diskcache_put(table, "k", ("complex", 123, "object")) + ret = diskcache_get(table, "k") + self.assertEqual(ret, ("complex", 123, "object")) + + def test_getotherprocess(self): + table = "test_getotherprocess" + from multiprocessing import Process, Queue + diskcache_put(table, "k", "getme") + q = Queue() + p = Process(target=remote_get, args=(table,q,"k")) + p.start() + p.join() + self.assertEqual(q.get(), "getme") + + def test_putotherprocess(self): + table = "test_putotherprocess" + from multiprocessing import Process + p = Process(target=remote_put, args=(table,"k", "remote")) + p.start() + p.join() + self.assertEqual(diskcache_get(table, "k"), "remote") + + def test_no_table(self): + self.assertIsNone(diskcache_get("faketable", "k")) + + def test_ret(self): + table = "test_ret" + self.assertEqual(diskcache_put(table, "key", ("vvs",)), ("vvs",)) + + def test_non_str_key(self): + table = "test_non_str_key" + diskcache_put(table, 4, 5) + self.assertEqual(diskcache_get(table, 4), 5) + self.assertEqual(diskcache_get(table, "4"), 5) + + def test_decorator(self): + calls = 0 + @diskcache + def hello(x): + nonlocal calls + calls += 1 + return "world"+x + self.assertEqual(hello("bob"), "worldbob") + self.assertEqual(hello("billy"), "worldbilly") + kcalls = calls + self.assertEqual(hello("bob"), "worldbob") + self.assertEqual(hello("billy"), "worldbilly") + self.assertEqual(kcalls, calls) + + def test_dict_key(self): + table = "test_dict_key" + fancy_key = {"hello": "world", "goodbye": 7, "good": True, "pkl": pickle.dumps("cat")} + fancy_key2 = {"hello": "world", "goodbye": 8, "good": True, "pkl": pickle.dumps("cat")} + fancy_key3 = {"hello": "world", "goodbye": 8, "good": True, "pkl": pickle.dumps("dog")} + diskcache_put(table, fancy_key, 5) + self.assertEqual(diskcache_get(table, fancy_key), 5) + diskcache_put(table, fancy_key2, 8) + self.assertEqual(diskcache_get(table, fancy_key2), 8) + self.assertEqual(diskcache_get(table, fancy_key), 5) + self.assertEqual(diskcache_get(table, fancy_key3), None) + + def test_table_name(self): + table = "test_gfx1010:xnack-" + diskcache_put(table, "key", "test") + self.assertEqual(diskcache_get(table, "key"), "test") + + @unittest.skip("disabled by default because this drops cache table") + def test_clear_cache(self): + # clear cache to start + diskcache_clear() + tables = [f"test_clear_cache:{i}" for i in range(3)] + for table in tables: + # check no entries + self.assertIsNone(diskcache_get(table, "k")) + for table in tables: + diskcache_put(table, "k", "test") + # check insertion + self.assertEqual(diskcache_get(table, "k"), "test") + + diskcache_clear() + for table in tables: + # check no entries again + self.assertIsNone(diskcache_get(table, "k")) + + # calling multiple times is fine + diskcache_clear() + diskcache_clear() + diskcache_clear() + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/unit/test_disk_tensor.py b/tinygrad_repo/test/unit/test_disk_tensor.py new file mode 100644 index 000000000..74a8fee8b --- /dev/null +++ b/tinygrad_repo/test/unit/test_disk_tensor.py @@ -0,0 +1,414 @@ +import pathlib, tempfile, unittest +import numpy as np +from tinygrad import Tensor, Device, dtypes +from tinygrad.dtype import DType +from tinygrad.nn.state import safe_load, safe_save, get_state_dict, torch_load +from tinygrad.helpers import Timing, fetch, temp, CI, OSX +from tinygrad.device import is_dtype_supported + +def compare_weights_both(url): + import torch + fn = fetch(url) + tg_weights = get_state_dict(torch_load(fn)) + torch_weights = get_state_dict(torch.load(fn, map_location=torch.device('cpu'), weights_only=False), tensor_type=torch.Tensor) + assert list(tg_weights.keys()) == list(torch_weights.keys()) + for k in tg_weights: + if tg_weights[k].dtype == dtypes.bfloat16: tg_weights[k] = torch_weights[k].float() # numpy doesn't support bfloat16 + if torch_weights[k].dtype == torch.bfloat16: torch_weights[k] = torch_weights[k].float() # numpy doesn't support bfloat16 + if torch_weights[k].requires_grad: torch_weights[k] = torch_weights[k].detach() + np.testing.assert_equal(tg_weights[k].numpy(), torch_weights[k].numpy(), err_msg=f"mismatch at {k}, {tg_weights[k].shape}") + print(f"compared {len(tg_weights)} weights") + +class TestTorchLoad(unittest.TestCase): + # pytorch pkl format + def test_load_enet(self): compare_weights_both("https://github.com/lukemelas/EfficientNet-PyTorch/releases/download/1.0/efficientnet-b0-355c32eb.pth") + # pytorch zip format + def test_load_enet_alt(self): compare_weights_both("https://download.pytorch.org/models/efficientnet_b0_rwightman-3dd342df.pth") + # pytorch zip format + def test_load_convnext(self): compare_weights_both('https://dl.fbaipublicfiles.com/convnext/convnext_tiny_1k_224_ema.pth') + + @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need float16 support") + def test_load_llama2bfloat(self): compare_weights_both("https://huggingface.co/qazalin/bf16-lightweight/resolve/main/consolidated.00.pth?download=true") + + # pytorch tar format + def test_load_resnet(self): compare_weights_both('https://download.pytorch.org/models/resnet50-19c8e357.pth') + +test_fn = pathlib.Path(__file__).parents[2] / "weights/LLaMA/7B/consolidated.00.pth" +#test_size = test_fn.stat().st_size +test_size = 1024*1024*1024*2 + +def _test_bitcasted(t: Tensor, dt: DType, expected): + np.testing.assert_allclose(t.bitcast(dt).numpy(), expected) + +# sudo su -c 'sync; echo 1 > /proc/sys/vm/drop_caches' && python3 test/unit/test_disk_tensor.py TestRawDiskBuffer.test_readinto_read_speed +class TestRawDiskBuffer(unittest.TestCase): + @unittest.skipIf(not test_fn.exists(), "download LLaMA weights for read in speed tests") + def test_readinto_read_speed(self): + tst = np.empty(test_size, np.uint8) + with open(test_fn, "rb") as f: + with Timing("copy in ", lambda et_ns: f" {test_size/et_ns:.2f} GB/s"): + f.readinto(tst) + def test_bitcasts_on_disk(self): + _, tmp = tempfile.mkstemp() + # ground truth = https://evanw.github.io/float-toy/ + t = Tensor.empty((128, 128), dtype=dtypes.uint8, device=f"disk:{tmp}") # uint8 + # all zeroes + _test_bitcasted(t, dtypes.float16, 0.0) + _test_bitcasted(t, dtypes.uint16, 0) + _test_bitcasted(t, dtypes.float32, 0.0) + _test_bitcasted(t, dtypes.uint32, 0) + # pi in float16 stored via int16 + t.bitcast(dtypes.uint16).assign(Tensor.full((128, 64), 0x4248, dtype=dtypes.uint16)).realize() + _test_bitcasted(t, dtypes.float16, 3.140625) + _test_bitcasted(t, dtypes.float32, 50.064727) + _test_bitcasted(t, dtypes.uint16, 0x4248) + _test_bitcasted(t, dtypes.uint32, 0x42484248) + # pi in float32 stored via float32 + t.bitcast(dtypes.float32).assign(Tensor.full((128, 32), 3.1415927, dtype=dtypes.float32)).realize() + _test_bitcasted(t, dtypes.float32, 3.1415927) + _test_bitcasted(t, dtypes.uint32, 0x40490FDB) + # doesn't suport normal cast + with self.assertRaises(NotImplementedError): + Tensor.empty((4,), dtype=dtypes.int16, device=f"disk:{tmp}").cast(dtypes.float16).realize() + + # Those two should be moved to test_dtype.py:test_shape_change_bitcast after bitcast works on non-disk + with self.assertRaises(RuntimeError): + # should fail because 3 int8 is 3 bytes but float16 is two and 3 isn't a multiple of 2 + Tensor.empty((3,), dtype=dtypes.int8, device=f"DISK:{tmp}").bitcast(dtypes.float16) + + with self.assertRaises(RuntimeError): + # should fail because backprop through bitcast is undefined + Tensor.empty((4,), dtype=dtypes.int8, requires_grad=True, device=f"DISK:{tmp}").bitcast(dtypes.float16) + + pathlib.Path(tmp).unlink() + +@unittest.skipUnless(is_dtype_supported(dtypes.uint8), "need uint8") +class TestSafetensors(unittest.TestCase): + def test_real_safetensors(self): + import torch + from safetensors.torch import save_file + torch.manual_seed(1337) + tensors = { + "weight1": torch.randn((16, 16)), + "weight2": torch.arange(0, 17, dtype=torch.uint8), + "weight3": torch.arange(0, 17, dtype=torch.int32).reshape(17,1,1), + "weight4": torch.arange(0, 2, dtype=torch.uint8), + } + save_file(tensors, temp("real.safetensors")) + + ret = safe_load(temp("real.safetensors")) + for k,v in tensors.items(): np.testing.assert_array_equal(ret[k].numpy(), v.numpy()) + safe_save(ret, temp("real.safetensors_alt")) + with open(temp("real.safetensors"), "rb") as f: + with open(temp("real.safetensors_alt"), "rb") as g: + assert f.read() == g.read() + ret2 = safe_load(temp("real.safetensors_alt")) + for k,v in tensors.items(): np.testing.assert_array_equal(ret2[k].numpy(), v.numpy()) + + def test_real_safetensors_open(self): + fn = temp("real_safe") + state_dict = {"tmp": Tensor.rand(10,10)} + safe_save(state_dict, fn) + import os + assert os.path.getsize(fn) == 8+0x40+(10*10*4) + from safetensors import safe_open + with safe_open(fn, framework="pt", device="cpu") as f: + assert sorted(f.keys()) == sorted(state_dict.keys()) + for k in f.keys(): + np.testing.assert_array_equal(f.get_tensor(k).numpy(), state_dict[k].numpy()) + + @unittest.skip("this test takes 7 seconds. TODO: make disk assign lazy") + def test_efficientnet_safetensors(self): + from extra.models.efficientnet import EfficientNet + model = EfficientNet(0) + state_dict = get_state_dict(model) + safe_save(state_dict, temp("eff0")) + state_dict_loaded = safe_load(temp("eff0")) + assert sorted(state_dict_loaded.keys()) == sorted(state_dict.keys()) + for k,v in state_dict.items(): + np.testing.assert_array_equal(v.numpy(), state_dict_loaded[k].numpy()) + + # load with the real safetensors + from safetensors import safe_open + with safe_open(temp("eff0"), framework="pt", device="cpu") as f: + assert sorted(f.keys()) == sorted(state_dict.keys()) + for k in f.keys(): + np.testing.assert_array_equal(f.get_tensor(k).numpy(), state_dict[k].numpy()) + + def _test_huggingface_enet_safetensors(self, fn): + state_dict = safe_load(fn) + assert len(state_dict.keys()) == 244 + assert 'blocks.2.2.se.conv_reduce.weight' in state_dict + assert state_dict['blocks.0.0.bn1.num_batches_tracked'].numpy() == 276570 + assert state_dict['blocks.2.0.bn2.num_batches_tracked'].numpy() == 276570 + + def test_huggingface_enet_safetensors(self): + # test a real file + fn = fetch("https://huggingface.co/timm/mobilenetv3_small_075.lamb_in1k/resolve/main/model.safetensors") + self._test_huggingface_enet_safetensors(fn) + + def test_huggingface_enet_safetensors_fromurl(self): + # test tensor input + t = Tensor.from_url("https://huggingface.co/timm/mobilenetv3_small_075.lamb_in1k/resolve/main/model.safetensors") + self._test_huggingface_enet_safetensors(t) + + def test_metadata(self): + metadata = {"hello": "world"} + safe_save({}, temp('metadata.safetensors'), metadata) + import struct + with open(temp('metadata.safetensors'), 'rb') as f: + dat = f.read() + sz = struct.unpack(">Q", dat[0:8])[0] + import json + assert json.loads(dat[8:8+sz])['__metadata__']['hello'] == 'world' + + def test_save_all_dtypes(self): + for dtype in dtypes.fields().values(): + if dtype in [dtypes.bfloat16]: continue # not supported in numpy + if dtype in [dtypes.double, *dtypes.fp8s] and Device.DEFAULT == "METAL": continue # not supported on METAL + path = temp(f"ones.{dtype}.safetensors") + ones = Tensor(np.random.rand(10,10), dtype=dtype) + safe_save(get_state_dict(ones), path) + np.testing.assert_equal(ones.numpy(), list(safe_load(path).values())[0].numpy()) + + def test_load_supported_types(self): + import torch + from safetensors.torch import save_file + from safetensors.numpy import save_file as np_save_file + torch.manual_seed(1337) + tensors = { + "weight_F16": torch.randn((2, 2), dtype=torch.float16), + "weight_F32": torch.randn((2, 2), dtype=torch.float32), + "weight_U8": torch.tensor([1, 2, 3], dtype=torch.uint8), + "weight_I8": torch.tensor([-1, 2, 3], dtype=torch.int8), + "weight_I32": torch.tensor([-1, 2, 3], dtype=torch.int32), + "weight_I64": torch.tensor([-1, 2, 3], dtype=torch.int64), + "weight_F64": torch.randn((2, 2), dtype=torch.double), + "weight_BOOL": torch.tensor([True, False], dtype=torch.bool), + "weight_I16": torch.tensor([127, 64], dtype=torch.short), + "weight_BF16": torch.randn((2, 2), dtype=torch.bfloat16), + } + save_file(tensors, temp("dtypes.safetensors")) + + loaded = safe_load(temp("dtypes.safetensors")) + for k,v in loaded.items(): + if v.dtype != dtypes.bfloat16: + assert v.numpy().dtype == tensors[k].numpy().dtype + np.testing.assert_allclose(v.numpy(), tensors[k].numpy()) + + # pytorch does not support U16, U32, and U64 dtypes. + tensors = { + "weight_U16": np.array([1, 2, 3], dtype=np.uint16), + "weight_U32": np.array([1, 2, 3], dtype=np.uint32), + "weight_U64": np.array([1, 2, 3], dtype=np.uint64), + } + np_save_file(tensors, temp("dtypes.safetensors")) + + loaded = safe_load(temp("dtypes.safetensors")) + for k,v in loaded.items(): + assert v.numpy().dtype == tensors[k].dtype + np.testing.assert_allclose(v.numpy(), tensors[k]) + +def helper_test_disk_tensor(fn, data, np_fxn, tinygrad_fxn=None): + if tinygrad_fxn is None: tinygrad_fxn = np_fxn + pathlib.Path(temp(fn)).unlink(missing_ok=True) + tinygrad_tensor = Tensor(data, device="CPU").to(f"disk:{temp(fn)}") + numpy_arr = np.array(data) + tinygrad_fxn(tinygrad_tensor) + np_fxn(numpy_arr) + np.testing.assert_allclose(tinygrad_tensor.numpy(), numpy_arr) + +class TestDiskTensor(unittest.TestCase): + def test_empty(self): + pathlib.Path(temp("dt_empty")).unlink(missing_ok=True) + Tensor.empty(100, 100, device=f"disk:{temp('dt_empty')}") + + def test_simple_read(self): + fn = pathlib.Path(temp("dt_simple_read")) + fn.unlink(missing_ok=True) + fn.write_bytes(bytes(range(256))) + t = Tensor.empty(16, 16, device=f"disk:{temp('dt_simple_read')}", dtype=dtypes.uint8) + out = t[1].to(Device.DEFAULT).tolist() + assert out == list(range(16, 32)) + + def test_simple_read_bitcast(self): + fn = pathlib.Path(temp("dt_simple_read_bitcast")) + fn.unlink(missing_ok=True) + fn.write_bytes(bytes(range(256))*2) + t = Tensor.empty(16, 16*2, device=f"disk:{temp('dt_simple_read_bitcast')}", dtype=dtypes.uint8) + out = t[1].bitcast(dtypes.uint16).to(Device.DEFAULT).tolist() + tout = [(x//256, x%256) for x in out] + assert tout == list([(x+1,x) for x in range(32,64,2)]) + + def test_simple_read_bitcast_alt(self): + fn = pathlib.Path(temp("dt_simple_read_bitcast_alt")) + fn.unlink(missing_ok=True) + fn.write_bytes(bytes(range(256))*2) + t = Tensor.empty(16, 16*2, device=f"disk:{temp('dt_simple_read_bitcast_alt')}", dtype=dtypes.uint8) + out = t.bitcast(dtypes.uint16)[1].to(Device.DEFAULT).tolist() + tout = [(x//256, x%256) for x in out] + assert tout == list([(x+1,x) for x in range(32,64,2)]) + + def test_write_ones(self): + pathlib.Path(temp("dt_write_ones")).unlink(missing_ok=True) + + out = Tensor.ones(10, 10, device="CPU").contiguous() + outdisk = out.to(f"disk:{temp('dt_write_ones')}") + print(outdisk) + outdisk.realize() + del out, outdisk + + import struct + # test file + with open(temp("dt_write_ones"), "rb") as f: + assert f.read() == struct.pack(' bf16 + with open(temp('dt_bf16_disk_write_read_f32'), "rb") as f: dat = f.read() + adat = b''.join([dat[i+2:i+4] for i in range(0, len(dat), 4)]) + with open(temp('dt_bf16_disk_write_read_bf16'), "wb") as f: f.write(adat) + + t = Tensor.empty(5, dtype=dtypes.bfloat16, device=f"disk:{temp('dt_bf16_disk_write_read_bf16')}") + ct = t.llvm_bf16_cast(dtypes.float) + assert ct.numpy().tolist() == [9984., -1, -1000, -9984, 20] + + def test_copy_from_disk(self): + fn = pathlib.Path(temp("dt_copy_from_disk")) + fn.unlink(missing_ok=True) + fn.write_bytes(bytes(range(256))*1024) + + t = Tensor.empty(256*1024, device=f"disk:{temp('dt_copy_from_disk')}", dtype=dtypes.uint8) + on_dev = t.to(Device.DEFAULT).realize() + np.testing.assert_equal(on_dev.numpy(), t.numpy()) + + def test_copy_from_disk_offset(self): + fn = pathlib.Path(temp("dt_copy_from_disk_offset")) + fn.unlink(missing_ok=True) + fn.write_bytes(bytes(range(256))*1024) + + for off in [314, 991, 2048, 4096]: + t = Tensor.empty(256*1024, device=f"disk:{temp('dt_copy_from_disk_offset')}", dtype=dtypes.uint8)[off:] + on_dev = t.to(Device.DEFAULT).realize() + np.testing.assert_equal(on_dev.numpy(), t.numpy()) + + def test_copy_from_disk_huge(self): + if CI and not hasattr(Device["DISK"], 'io_uring'): self.skipTest("slow on ci without iouring") + + fn = pathlib.Path(temp("dt_copy_from_disk_huge")) + fn.unlink(missing_ok=True) + fn.write_bytes(bytes(range(256))*1024*256) + + for off in [0, 551]: + t = Tensor.empty(256*1024*256, device=f"disk:{temp('dt_copy_from_disk_huge')}", dtype=dtypes.uint8)[off:] + on_dev = t.to(Device.DEFAULT).realize() + np.testing.assert_equal(on_dev.numpy(), t.numpy()) + + @unittest.skip("this allocates a lot of RAM") + @unittest.skipUnless(OSX, "seems to only be an issue on macOS with file size >2 GiB") + def test_copy_to_cpu_not_truncated(self): + with open((fn:=temp("dt_copy_to_cpu_not_truncated")), "wb") as f: f.write(b'\x01' * (size := int(2 * 1024**3)) + (test := b"test")) + x = Tensor.empty(size + len(test), dtype=dtypes.uint8, device=f"disk:{fn}").to("CPU").realize() + assert x[size:].data().tobytes() == test + +class TestPathTensor(unittest.TestCase): + def setUp(self): + self.temp_dir = tempfile.TemporaryDirectory() + self.test_file = pathlib.Path(self.temp_dir.name) / "test_file.bin" + self.test_data = np.arange(100, dtype=np.uint8).tobytes() + with open(self.test_file, "wb") as f: + f.write(self.test_data) + + def tearDown(self): + self.temp_dir.cleanup() + + def test_path_tensor_no_device(self): + t = Tensor(self.test_file) + self.assertEqual(t.shape, (100,)) + self.assertEqual(t.dtype, dtypes.uint8) + self.assertTrue(t.device.startswith("DISK:")) + np.testing.assert_array_equal(t.numpy(), np.frombuffer(self.test_data, dtype=np.uint8)) + + def test_path_tensor_with_device(self): + t = Tensor(self.test_file, device="CPU") + self.assertEqual(t.shape, (100,)) + self.assertEqual(t.dtype, dtypes.uint8) + self.assertEqual(t.device, "CPU") + np.testing.assert_array_equal(t.numpy(), np.frombuffer(self.test_data, dtype=np.uint8)) + + def test_path_tensor_empty_file(self): + empty_file = pathlib.Path(self.temp_dir.name) / "empty_file.bin" + empty_file.touch() + t = Tensor(empty_file) + self.assertEqual(t.shape, (0,)) + self.assertEqual(t.dtype, dtypes.uint8) + self.assertTrue(t.device.startswith("DISK:")) + + def test_path_tensor_non_existent_file(self): + non_existent_file = pathlib.Path(self.temp_dir.name) / "non_existent.bin" + with self.assertRaises(FileNotFoundError): + Tensor(non_existent_file) + + def test_path_tensor_with_dtype(self): + t = Tensor(self.test_file, dtype=dtypes.int16) + self.assertEqual(t.shape, (50,)) + self.assertEqual(t.dtype, dtypes.int16) + self.assertTrue(t.device.startswith("DISK:")) + np.testing.assert_array_equal(t.numpy(), np.frombuffer(self.test_data, dtype=np.int16)) + + def test_path_tensor_copy_to_device(self): + t = Tensor(self.test_file) + t_cpu = t.to("CPU") + self.assertEqual(t_cpu.device, "CPU") + np.testing.assert_array_equal(t_cpu.numpy(), np.frombuffer(self.test_data, dtype=np.uint8)) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/unit/test_dtype_spec.py b/tinygrad_repo/test/unit/test_dtype_spec.py new file mode 100644 index 000000000..0e78af19d --- /dev/null +++ b/tinygrad_repo/test/unit/test_dtype_spec.py @@ -0,0 +1,552 @@ +import unittest, math, operator, subprocess +from tinygrad.tensor import Tensor, dtypes, Device +from tinygrad.dtype import DType, DTYPES_DICT, truncate, truncate_fp16, truncate_bf16, _to_np_dtype, least_upper_dtype, least_upper_float +from tinygrad.device import is_dtype_supported +from tinygrad.helpers import getenv, CI, DEBUG +from hypothesis import given, settings, strategies as strat +import numpy as np +import torch +import ml_dtypes + +settings.register_profile("my_profile", max_examples=200, deadline=None, derandomize=getenv("DERANDOMIZE_CI", False)) +settings.load_profile("my_profile") + +core_dtypes = list(DTYPES_DICT.values()) +dtype_ints = [dt for dt in core_dtypes if dtypes.is_int(dt) and is_dtype_supported(dt)] +dtype_floats = [dt for dt in core_dtypes if dtypes.is_float(dt) and is_dtype_supported(dt)] + +FP8E4M3_MAX = 448.0 +FP8E5M2_MAX = 57344.0 + +def _assert_eq(tensor:Tensor, target_dtype:DType, target, tol_target_dtype:float=1e-7): + if DEBUG >= 2: print(tensor.numpy()) + try: + assert tensor.dtype == target_dtype + np.testing.assert_allclose(tensor.numpy(), target, rtol={dtypes.float16:1e-3, dtypes.bfloat16:1e-2}.get(target_dtype, tol_target_dtype)) + except AssertionError as e: + raise AssertionError(f"\ntensor {tensor.numpy()} dtype {tensor.dtype} does not match target {target} with dtype {target_dtype}") from e + +class TestHelpers(unittest.TestCase): + signed_ints = (dtypes.int8, dtypes.int16, dtypes.int32, dtypes.int64) + uints = (dtypes.uint8, dtypes.uint16, dtypes.uint32, dtypes.uint64) + floats = (dtypes.float16, dtypes.float32, dtypes.float64) + + @given(strat.sampled_from(signed_ints+uints), strat.integers(min_value=1, max_value=8)) + def test_is_int(self, dtype, amt): + assert dtypes.is_int(dtype.vec(amt) if amt > 1 else dtype) + assert not dtypes.is_float(dtype.vec(amt) if amt > 1 else dtype) + + @given(strat.sampled_from(uints), strat.integers(min_value=1, max_value=8)) + def test_is_unsigned_uints(self, dtype, amt): + assert dtypes.is_unsigned(dtype.vec(amt) if amt > 1 else dtype) + + @given(strat.sampled_from(signed_ints), strat.integers(min_value=1, max_value=8)) + def test_is_unsigned_signed_ints(self, dtype, amt): + assert not dtypes.is_unsigned(dtype.vec(amt) if amt > 1 else dtype) + + @given(strat.sampled_from(floats), strat.integers(min_value=1, max_value=8)) + def test_is_float(self, dtype, amt): + assert dtypes.is_float(dtype.vec(amt) if amt > 1 else dtype) + assert not dtypes.is_int(dtype.vec(amt) if amt > 1 else dtype) + assert not dtypes.is_unsigned(dtype.vec(amt) if amt > 1 else dtype) + + def test_bf16_is_float(self): + assert dtypes.is_float(dtypes.bfloat16) + + def test_fp8s_are_float(self): + assert dtypes.is_float(dtypes.fp8e4m3) + assert dtypes.is_float(dtypes.fp8e5m2) + + @given(strat.sampled_from([d for d in DTYPES_DICT.values() if dtypes.is_float(d) or dtypes.is_int(d)]), strat.integers(min_value=2, max_value=8)) + def test_scalar(self, dtype, amt): + assert dtype.vec(amt).scalar() == dtype + + def test_from_py(self): + assert dtypes.from_py(True) == dtypes.bool + assert dtypes.from_py(2) == dtypes.default_int + assert dtypes.from_py(3.0) == dtypes.default_float + assert dtypes.from_py([]) == dtypes.default_float + assert dtypes.from_py(()) == dtypes.default_float + assert dtypes.from_py([True]) == dtypes.bool + assert dtypes.from_py([True, 2]) == dtypes.default_int + assert dtypes.from_py([True, 3.0]) == dtypes.default_float + assert dtypes.from_py([2, 3.0]) == dtypes.default_float + assert dtypes.from_py([True, 2, 3.0]) == dtypes.default_float + with self.assertRaises(RuntimeError): dtypes.from_py(None) + with self.assertRaises(RuntimeError): dtypes.from_py([None]) + with self.assertRaises(RuntimeError): dtypes.from_py({}) + with self.assertRaises(RuntimeError): dtypes.from_py(set()) + + def test_dtype_range(self): + for dt in core_dtypes: + if dtypes.is_float(dt): + np.testing.assert_equal(dtypes.min(dt), -math.inf) + np.testing.assert_equal(dtypes.max(dt), math.inf) + np.testing.assert_equal(dt.min, -math.inf) + np.testing.assert_equal(dt.max, math.inf) + elif dtypes.is_int(dt): + info = np.iinfo(_to_np_dtype(dt)) + np.testing.assert_equal(dtypes.min(dt), info.min) + np.testing.assert_equal(dtypes.max(dt), info.max) + np.testing.assert_equal(dt.min, info.min) + np.testing.assert_equal(dt.max, info.max) + else: + assert dt == dtypes.bool, dt + np.testing.assert_equal(dtypes.min(dt), False) + np.testing.assert_equal(dtypes.max(dt), True) + np.testing.assert_equal(dt.min, False) + np.testing.assert_equal(dt.max, True) + + def test_truncate_fp16(self): + self.assertEqual(truncate_fp16(1), 1) + self.assertEqual(truncate_fp16(65504), 65504) + self.assertEqual(truncate_fp16(65519.999), 65504) + self.assertEqual(truncate_fp16(65520), math.inf) + + def test_truncate_bf16(self): + self.assertEqual(truncate_bf16(1), 1) + self.assertAlmostEqual(truncate_bf16(1.1), 1.09375, places=7) + for a in [1234, 23456, -777.777]: + self.assertEqual(truncate_bf16(a), torch.tensor([a], dtype=torch.bfloat16).item()) + # TODO: torch bfloat 1.1 gives 1.1015625 instead of 1.09375 + max_bf16 = torch.finfo(torch.bfloat16).max + self.assertEqual(truncate_bf16(max_bf16), max_bf16) + self.assertEqual(truncate_bf16(min_bf16:=-max_bf16), min_bf16) + self.assertEqual(truncate_bf16(max_bf16 * 1.00001), math.inf) + self.assertEqual(truncate_bf16(min_bf16 * 1.00001), -math.inf) + + @given(strat.floats(width=32, allow_subnormal=True, allow_nan=True, allow_infinity=True)) + def test_truncate_fp8e4m3(self, x): + if x > FP8E4M3_MAX: np.testing.assert_equal(truncate[dtypes.fp8e4m3](x), FP8E4M3_MAX) + elif x < -FP8E4M3_MAX: np.testing.assert_equal(truncate[dtypes.fp8e4m3](x), -FP8E4M3_MAX) + else: np.testing.assert_equal(truncate[dtypes.fp8e4m3](x), ml_dtypes.float8_e4m3fn(x)) + + @given(strat.floats(width=32, allow_subnormal=True, allow_nan=True, allow_infinity=True)) + def test_truncate_fp8e5m2(self, x): + if x > FP8E5M2_MAX: np.testing.assert_equal(truncate[dtypes.fp8e5m2](x), FP8E5M2_MAX) + elif x < -FP8E5M2_MAX: np.testing.assert_equal(truncate[dtypes.fp8e5m2](x), -FP8E5M2_MAX) + else: np.testing.assert_equal(truncate[dtypes.fp8e5m2](x), ml_dtypes.float8_e5m2(x)) + +class TestTypeSpec(unittest.TestCase): + def setUp(self): + self.old_default_int, self.old_default_float = dtypes.default_int, dtypes.default_float + def tearDown(self): + dtypes.default_int, dtypes.default_float = self.old_default_int, self.old_default_float + + def test_set_dtype_default(self): + for default_int in [dtypes.int8, dtypes.int16, dtypes.int32, dtypes.int64]: + dtypes.default_int = default_int + assert dtypes.default_int == default_int + + for default_float in [*dtypes.fp8s, dtypes.float16, dtypes.bfloat16, dtypes.float32, dtypes.float64]: + dtypes.default_float = default_float + assert dtypes.default_float == default_float + + @unittest.skip("this test is slow and spawning whole pythons") + def test_env_set_default_float(self): + # check default + subprocess.run(['python3 -c "from tinygrad import dtypes; assert dtypes.default_float == dtypes.float"'], + shell=True, check=True) + # check change + subprocess.run(['DEFAULT_FLOAT=HALF python3 -c "from tinygrad import dtypes; assert dtypes.default_float == dtypes.half"'], + shell=True, check=True) + # check invalid + with self.assertRaises(subprocess.CalledProcessError): + subprocess.run(['DEFAULT_FLOAT=INT32 python3 -c "from tinygrad import dtypes"'], + shell=True, check=True) + + with self.assertRaises(subprocess.CalledProcessError): + subprocess.run(['DEFAULT_FLOAT=TYPO python3 -c "from tinygrad import dtypes"'], + shell=True, check=True) + + @unittest.skipUnless(is_dtype_supported(dtypes.int8), f"no int8 on {Device.DEFAULT}") + def test_dtype_str_arg(self): + n = np.random.normal(0, 1, (10, 10)).astype(np.float32) + tested = 0 + for dtype_str, dtype in [ + ("bool", dtypes.bool), ("int8", dtypes.int8), ("int", dtypes.int), ("uint32", dtypes.uint32), ("float32", dtypes.float32)]: + np.testing.assert_equal(Tensor(n, dtype=dtype_str).numpy(), Tensor(n, dtype=dtype).numpy()) + np.testing.assert_equal(Tensor(n).cast(dtype_str).numpy(), Tensor(n).cast(dtype).numpy()) + if dtype.itemsize == 4: + np.testing.assert_equal(Tensor(n).bitcast(dtype_str).numpy(), Tensor(n).bitcast(dtype).numpy()) + tested += 1 + assert tested == 3 + + with self.assertRaises(AttributeError): Tensor([1, 2, 3], dtype="nonexistdtype") + with self.assertRaises(AttributeError): Tensor([1, 2, 3], dtype="") + + np.testing.assert_equal(Tensor(n).sum(dtype="int16").numpy(), Tensor(n).sum(dtype=dtypes.int16).numpy()) + + @given(strat.sampled_from(dtype_ints), strat.sampled_from(dtype_floats)) + def test_creation(self, default_int, default_float): + dtypes.default_int, dtypes.default_float = default_int, default_float + _assert_eq(Tensor(True), dtypes.bool, True) + _assert_eq(Tensor(None), dtypes.default_float, []) + _assert_eq(Tensor(2), dtypes.default_int, 2) + _assert_eq(Tensor(2.34), dtypes.default_float, 2.34) + _assert_eq(Tensor([]), dtypes.default_float, []) + _assert_eq(Tensor([1]), dtypes.default_int, [1]) + _assert_eq(Tensor([1.1]), dtypes.default_float, [1.1]) + + _assert_eq(Tensor.eye(0), dtypes.default_float, np.eye(0)) + _assert_eq(Tensor.eye(3), dtypes.default_float, np.eye(3)) + if is_dtype_supported(dtypes.int64): + _assert_eq(Tensor.eye(3, dtype=dtypes.int64), dtypes.int64, np.eye(3)) + if is_dtype_supported(dtypes.float16): + _assert_eq(Tensor.eye(3, dtype=dtypes.float16), dtypes.float16, np.eye(3)) + + @given(strat.sampled_from(dtype_ints), strat.sampled_from(dtype_floats)) + def test_full(self, default_int, default_float): + dtypes.default_int, dtypes.default_float = default_int, default_float + + _assert_eq(Tensor.zeros((2, 3)), dtypes.default_float, np.zeros((2, 3))) + if is_dtype_supported(dtypes.int64): + _assert_eq(Tensor.zeros((2, 3), dtype=dtypes.int64), dtypes.int64, np.zeros((2, 3))) + if is_dtype_supported(dtypes.float16): + _assert_eq(Tensor.zeros((2, 3), dtype=dtypes.float16), dtypes.float16, np.zeros((2, 3))) + + _assert_eq(Tensor.ones((2, 3)), dtypes.default_float, np.ones((2, 3))) + if is_dtype_supported(dtypes.int64): + _assert_eq(Tensor.ones((2, 3), dtype=dtypes.int64), dtypes.int64, np.ones((2, 3))) + if is_dtype_supported(dtypes.float16): + _assert_eq(Tensor.ones((2, 3), dtype=dtypes.float16), dtypes.float16, np.ones((2, 3))) + + _assert_eq(Tensor.full((2, 3), 3.0), dtypes.default_float, np.full((2, 3), 3.0)) + _assert_eq(Tensor.full((2, 3), 3), dtypes.default_int, np.full((2, 3), 3)) + _assert_eq(Tensor.full((2, 3), True), dtypes.bool, np.full((2, 3), True)) + if is_dtype_supported(dtypes.int64): + _assert_eq(Tensor.full((2, 3), 3, dtype=dtypes.int64), dtypes.int64, np.full((2, 3), 3)) + _assert_eq(Tensor.full((2, 3), 3.0, dtype=dtypes.int64), dtypes.int64, np.full((2, 3), 3)) + if is_dtype_supported(dtypes.float16): + _assert_eq(Tensor.full((2, 3), 3, dtype=dtypes.float16), dtypes.float16, np.full((2, 3), 3)) + _assert_eq(Tensor.full((2, 3), 3.0, dtype=dtypes.float16), dtypes.float16, np.full((2, 3), 3)) + + @given(strat.sampled_from(dtype_ints), strat.sampled_from(dtype_floats)) + def test_reduce_0d_default(self, default_int, default_float): + dtypes.default_int, dtypes.default_float = default_int, default_float + _assert_eq(Tensor.ones((2,3,0)).sum(2), dtypes.default_float, np.zeros((2, 3))) + # TODO: what should this one be? + # _assert_eq(Tensor.ones((2,3,0), dtype=dtypes.default_int).sum(2), dtypes.default_int, np.zeros((2, 3))) + _assert_eq(Tensor.ones((2,3,0), dtype=dtypes.int32).sum(2), dtypes.int32, np.zeros((2, 3))) + + @given(strat.sampled_from(dtype_ints), strat.sampled_from(dtype_floats)) + def test_arange(self, default_int, default_float): + dtypes.default_int, dtypes.default_float = default_int, default_float + + _assert_eq(Tensor.arange(5), dtypes.default_int, np.arange(5)) + _assert_eq(Tensor.arange(120), dtypes.default_int, np.arange(120)) + _assert_eq(Tensor.arange(5.0), dtypes.default_float, np.arange(5)) + if is_dtype_supported(dtypes.int16): + _assert_eq(Tensor.arange(5, dtype=dtypes.int16), dtypes.int16, np.arange(5)) + if is_dtype_supported(dtypes.int64): + _assert_eq(Tensor.arange(5, dtype=dtypes.int64), dtypes.int64, np.arange(5)) + if is_dtype_supported(dtypes.float16): + _assert_eq(Tensor.arange(5, dtype=dtypes.float16), dtypes.float16, np.arange(5)) + _assert_eq(Tensor.arange(3, 9, 0.7), dtypes.default_float, np.arange(3, 9, 0.7), 1e-6 if Device.DEFAULT == "WEBGPU" else 1e-7) + _assert_eq(Tensor.arange(3, 8.5, 3), dtypes.default_float, np.arange(3, 8.5, 3)) + # stop-start and step have different signs + _assert_eq(Tensor.arange(3, 5, -2), dtypes.default_int, np.arange(3, 5, -2)) + _assert_eq(Tensor.arange(5.0, 3.0), dtypes.default_float, np.arange(5.0, 3.0)) + + @given(strat.sampled_from(core_dtypes), strat.sampled_from([operator.gt, operator.ge, operator.le, operator.lt, operator.eq, operator.ne])) + def test_bool_ops(self, dtype, op): + assert op(Tensor.ones(4, 4, dtype=dtype), Tensor.ones(4, 4, dtype=dtype)).dtype == dtypes.bool + + @given(strat.sampled_from(core_dtypes), strat.sampled_from(dtype_ints), strat.sampled_from(dtype_floats)) + def test_functions_return_index(self, dtype, default_int, default_float): + dtypes.default_int, dtypes.default_float = default_int, default_float + assert Tensor([0, 1], dtype=dtype).argmax().dtype == dtypes.int32 + assert Tensor([0, 1], dtype=dtype).argmin().dtype == dtypes.int32 + assert Tensor([0, 1], dtype=dtype).multinomial().dtype == dtypes.int32 + + @given(strat.sampled_from(core_dtypes), strat.sampled_from(dtype_ints)) + def test_tensor_indexing_returns_same_dtype(self, data_dtype, indices_dtype): + X_data = Tensor.ones(60000, 1, 28, 28, dtype=data_dtype) + indices = Tensor.randint(512, high=X_data.shape[0]).cast(indices_dtype) + assert X_data[indices].dtype == X_data.dtype + + @given(strat.sampled_from(core_dtypes), strat.sampled_from(dtype_ints)) + def test_gather_returns_same_dtype(self, data_dtype, indices_dtype): + X_data = Tensor([[1, 0], [0, 1]], dtype=data_dtype) + indices = Tensor([[0, 0], [1, 0]], dtype=indices_dtype) + assert X_data.gather(0, indices).dtype == X_data.dtype + assert X_data.gather(1, indices).dtype == X_data.dtype + + @given(strat.sampled_from(dtype_floats), strat.sampled_from(dtype_floats)) + def test_attention_returns_same_dtype(self, data_dtype, default_float): + dtypes.default_float = default_float + query = Tensor.rand(32, 8, 128, 64, dtype=data_dtype) + key = Tensor.rand(32, 8, 128, 64, dtype=data_dtype) + value = Tensor.rand(32, 8, 128, 64, dtype=data_dtype) + mask = (Tensor.rand(32, 8, 128, 128) < 0.5) + assert query.scaled_dot_product_attention(key, value, is_causal=True).dtype == data_dtype + assert query.scaled_dot_product_attention(key, value, is_causal=True, dropout_p=0.3).dtype == data_dtype + assert query.scaled_dot_product_attention(key, value, is_causal=False).dtype == data_dtype + assert query.scaled_dot_product_attention(key, value, attn_mask=mask).dtype == data_dtype + +class TestTypePromotion(unittest.TestCase): + @given(strat.sampled_from(core_dtypes)) + def test_self_promo_to_self(self, dtype): + assert least_upper_dtype(dtype) == dtype + assert least_upper_dtype(dtype, dtype) == dtype + assert least_upper_dtype(dtype, dtype, dtype) == dtype + + @given(strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes)) + def test_promo_resulted_higher_than_inputs(self, dtype1, dtype2): + result = least_upper_dtype(dtype1, dtype2) + assert not (result < dtype1) and not (result < dtype2) + + def test_dtype_promo(self): + assert least_upper_dtype(dtypes.bool, dtypes.int8) == dtypes.int8 + assert least_upper_dtype(dtypes.int8, dtypes.uint8) == dtypes.int16 + assert least_upper_dtype(dtypes.uint8, dtypes.int16) == dtypes.int16 + assert least_upper_dtype(dtypes.int16, dtypes.uint16) == dtypes.int32 + assert least_upper_dtype(dtypes.uint16, dtypes.int32) == dtypes.int32 + assert least_upper_dtype(dtypes.int32, dtypes.uint32) == dtypes.int64 + assert least_upper_dtype(dtypes.uint32, dtypes.int64) == dtypes.int64 + # similar to jax but we don't use weak type + assert least_upper_dtype(dtypes.int64, dtypes.uint64) == dtypes.float16 + assert least_upper_dtype(dtypes.float16, dtypes.float32) == dtypes.float32 + assert least_upper_dtype(dtypes.float32, dtypes.float64) == dtypes.float64 + + assert least_upper_dtype(dtypes.bool, dtypes.float32) == dtypes.float32 + assert least_upper_dtype(dtypes.bool, dtypes.float64) == dtypes.float64 + assert least_upper_dtype(dtypes.float16, dtypes.int64) == dtypes.float16 + assert least_upper_dtype(dtypes.float16, dtypes.uint64) == dtypes.float16 + assert least_upper_dtype(dtypes.fp8e4m3, dtypes.fp8e5m2) == dtypes.half + +class TestAutoCastType(unittest.TestCase): + def setUp(self): + self.old_default_int, self.old_default_float = dtypes.default_int, dtypes.default_float + def tearDown(self): + dtypes.default_int, dtypes.default_float = self.old_default_int, self.old_default_float + + @given(strat.sampled_from(dtype_floats), strat.sampled_from(dtype_floats)) + def test_least_upper_float_input_is_float(self, input_dtype, default_float): + dtypes.default_float = default_float + self.assertEqual(least_upper_float(input_dtype), input_dtype) + + @given(strat.sampled_from(dtype_ints), strat.sampled_from(dtype_floats)) + def test_least_upper_float_input_is_int(self, input_dtype, default_float): + dtypes.default_float = default_float + self.assertEqual(least_upper_float(input_dtype), default_float) + + @given(strat.sampled_from([d for d in core_dtypes if dtypes.is_int(d) and is_dtype_supported(d)])) + def test_int_to_float_unary_func(self, dtype): + for func in [ + lambda t: t.exp(), + lambda t: t.exp2(), + lambda t: t.log(), + lambda t: t.log2(), + lambda t: t.sqrt(), + lambda t: t.rsqrt(), + lambda t: t.sin(), + lambda t: t.cos(), + lambda t: t.tan(), + lambda t: t.sigmoid(), + ]: + a = [2, 3, 4] + # float16 can have larger precision errors + np.testing.assert_allclose(func(Tensor(a, dtype=dtype)).numpy(), func(torch.tensor(a)), rtol=1e-3, atol=1e-3) + + @given(strat.sampled_from(core_dtypes)) + def test_broadcast_scalar(self, dt): + assert (Tensor.ones(4, 4, dtype=dt) + 2.3).dtype == (dt if dtypes.is_float(dt) else dtypes.default_float) + assert (Tensor.ones(4, 4, dtype=dt) + 2).dtype == (dt if dtypes.is_float(dt) or dtypes.is_int(dt) else dtypes.default_int) + assert (Tensor.ones(4, 4, dtype=dt) + True).dtype == dt + + @given(strat.sampled_from(dtype_floats)) + def test_int_div_int(self, default_float): + dtypes.default_float = default_float + self.assertEqual(Tensor([1]).div(Tensor([2])).dtype, default_float) + + def test_sum(self): + assert (Tensor([0, 1], dtype=dtypes.bool)).sum().dtype == dtypes.int32 + assert (Tensor([0, 1], dtype=dtypes.int8)).sum().dtype == dtypes.int32 + assert (Tensor([0, 1], dtype=dtypes.int16)).sum().dtype == dtypes.int32 + assert (Tensor([0, 1], dtype=dtypes.int32)).sum().dtype == dtypes.int32 + assert (Tensor([0, 1], dtype=dtypes.int64)).sum().dtype == dtypes.int64 + assert (Tensor([0, 1], dtype=dtypes.uint8)).sum().dtype == dtypes.uint32 + assert (Tensor([0, 1], dtype=dtypes.uint16)).sum().dtype == dtypes.uint32 + assert (Tensor([0, 1], dtype=dtypes.uint32)).sum().dtype == dtypes.uint32 + assert (Tensor([0, 1], dtype=dtypes.uint64)).sum().dtype == dtypes.uint64 + assert (Tensor([0, 1], dtype=dtypes.float16)).sum().dtype == dtypes.float16 + #assert (Tensor([0, 1], dtype=dtypes.bfloat16)).sum().dtype == dtypes.bfloat16 + assert (Tensor([0, 1], dtype=dtypes.float32)).sum().dtype == dtypes.float32 + assert (Tensor([0, 1], dtype=dtypes.float64)).sum().dtype == dtypes.float64 + + @unittest.skipUnless(is_dtype_supported(dtypes.float16), "need float16") + def test_sum_dtype_arg(self): + t = Tensor([40000, 40000], dtype=dtypes.float16) + # default float16 sum returns in float16, overflowed in this case + assert t.sum().dtype == dtypes.float16 + assert math.isinf(t.sum().numpy().item()) + # specifiying dtype and it's not downcasted + assert t.sum(dtype=dtypes.float32).dtype == dtypes.float32 + np.testing.assert_allclose(t.sum(dtype=dtypes.float32).numpy(), 80000) + + def test_prod_dtype_arg(self): + t = Tensor([100, 200], dtype=dtypes.int32) + assert t.prod().dtype == dtypes.int32 + np.testing.assert_allclose(t.prod().numpy(), 20000) + assert t.prod(dtype=dtypes.float32).dtype == dtypes.float32 + np.testing.assert_allclose(t.prod(dtype=dtypes.float32).numpy(), 20000) + + def test_mean(self): + assert (Tensor([0, 1], dtype=dtypes.bool)).mean().dtype == dtypes.float32 + assert (Tensor([0, 1], dtype=dtypes.int8)).mean().dtype == dtypes.float32 + assert (Tensor([0, 1], dtype=dtypes.int16)).mean().dtype == dtypes.float32 + assert (Tensor([0, 1], dtype=dtypes.int32)).mean().dtype == dtypes.float32 + assert (Tensor([0, 1], dtype=dtypes.int64)).mean().dtype == dtypes.float32 + assert (Tensor([0, 1], dtype=dtypes.uint8)).mean().dtype == dtypes.float32 + assert (Tensor([0, 1], dtype=dtypes.uint16)).mean().dtype == dtypes.float32 + assert (Tensor([0, 1], dtype=dtypes.uint32)).mean().dtype == dtypes.float32 + assert (Tensor([0, 1], dtype=dtypes.uint64)).mean().dtype == dtypes.float32 + assert (Tensor([0, 1], dtype=dtypes.float16)).mean().dtype == dtypes.float16 + #assert (Tensor([0, 1], dtype=dtypes.bfloat16)).mean().dtype == dtypes.bfloat16 + assert (Tensor([0, 1], dtype=dtypes.float32)).mean().dtype == dtypes.float32 + assert (Tensor([0, 1], dtype=dtypes.float64)).mean().dtype == dtypes.float64 + + def test_cumsum(self): + assert (Tensor([0, 1], dtype=dtypes.bool)).cumsum(0).dtype == dtypes.int32 + assert (Tensor([0, 1], dtype=dtypes.int8)).cumsum(0).dtype == dtypes.int32 + assert (Tensor([0, 1], dtype=dtypes.int16)).cumsum(0).dtype == dtypes.int32 + assert (Tensor([0, 1], dtype=dtypes.int32)).cumsum(0).dtype == dtypes.int32 + assert (Tensor([0, 1], dtype=dtypes.int64)).cumsum(0).dtype == dtypes.int64 + assert (Tensor([0, 1], dtype=dtypes.uint8)).cumsum(0).dtype == dtypes.uint32 + assert (Tensor([0, 1], dtype=dtypes.uint16)).cumsum(0).dtype == dtypes.uint32 + assert (Tensor([0, 1], dtype=dtypes.uint32)).cumsum(0).dtype == dtypes.uint32 + assert (Tensor([0, 1], dtype=dtypes.uint64)).cumsum(0).dtype == dtypes.uint64 + assert (Tensor([0, 1], dtype=dtypes.float16)).cumsum(0).dtype == dtypes.float16 + #assert (Tensor([0, 1], dtype=dtypes.bfloat16)).cumsum(0).dtype == dtypes.bfloat16 + assert (Tensor([0, 1], dtype=dtypes.float32)).cumsum(0).dtype == dtypes.float32 + assert (Tensor([0, 1], dtype=dtypes.float64)).cumsum(0).dtype == dtypes.float64 + + @given(strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes)) + def test_matmul(self, dt1, dt2, acc_dt): + t1 = Tensor([0, 1], dtype=dt1) + t2 = Tensor([0, 1], dtype=dt2) + self.assertEqual(t1.matmul(t2).dtype, least_upper_dtype(t1.dtype, t2.dtype)) + # if dtype is specified, return in dtype + self.assertEqual(t1.matmul(t2, dtype=acc_dt).dtype, acc_dt) + + @given(strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes)) + def test_linear(self, dt1, dt2, dt3, acc_dt): + x = Tensor([0, 1], dtype=dt1) + w = Tensor([0, 1], dtype=dt2) + b = Tensor([0, 1], dtype=dt3) + self.assertEqual(x.linear(w).dtype, least_upper_dtype(x.dtype, w.dtype)) + self.assertEqual(x.linear(w, b).dtype, least_upper_dtype(least_upper_dtype(x.dtype, w.dtype), b.dtype)) + # if dtype is specified, return in dtype + self.assertEqual(x.linear(w, dtype=acc_dt).dtype, acc_dt) + self.assertEqual(x.linear(w, b, dtype=acc_dt).dtype, acc_dt) + + @staticmethod + def check_where_alternate_input_other(input_, other, data_type): + assert (Tensor([True, False]).where(input_, other)).dtype == data_type + assert (Tensor([True, False]).where(other, input_)).dtype == data_type + + @given(strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes)) + def test_where_no_scalar(self, dt1, dt2): + self.check_where_alternate_input_other(Tensor(2, dtype=dt1), Tensor(3, dtype=dt2), least_upper_dtype(dt1, dt2)) + + @given(strat.sampled_from(core_dtypes)) + def test_where_one_scalar(self, dt): + t = Tensor(2, dtype=dt) + self.check_where_alternate_input_other(t, 3.2, (dt if dtypes.is_float(dt) else dtypes.default_float)) + self.check_where_alternate_input_other(t, 3, (dt if dtypes.is_float(dt) or dtypes.is_int(dt) else dtypes.default_int)) + self.check_where_alternate_input_other(t, True, dt) + + def test_where_two_scalars(self): + self.check_where_alternate_input_other(3.1, 3.2, dtypes.default_float) + self.check_where_alternate_input_other(3.1, 3, dtypes.default_float) + self.check_where_alternate_input_other(3.1, True, dtypes.default_float) + self.check_where_alternate_input_other(3, 2, dtypes.default_int) + self.check_where_alternate_input_other(3, True, dtypes.default_int) + self.check_where_alternate_input_other(False, True, dtypes.bool) + + @given(strat.sampled_from(core_dtypes), strat.sampled_from(core_dtypes)) + def test_maximum(self, dt1, dt2): + assert Tensor([0, 1, 2], dtype=dt1).maximum(Tensor([2, 0, 5], dtype=dt2)).dtype == least_upper_dtype(dt1, dt2) + + @given(strat.sampled_from(core_dtypes)) + def test_maximum_const(self, dt): + assert Tensor([1, 2], dtype=dt).maximum(3.1).dtype == (dt if dtypes.is_float(dt) else dtypes.default_float) + assert Tensor([1, 2], dtype=dt).maximum(3).dtype == (dt if dtypes.is_float(dt) or dtypes.is_int(dt) else dtypes.default_int) + assert Tensor([1, 2], dtype=dt).maximum(True).dtype == dt + + def test_div(self): + assert (Tensor([1, 2], dtype=dtypes.int32) / Tensor([2, 2], dtype=dtypes.int32)).dtype == dtypes.default_float + assert (Tensor([1, 2], dtype=dtypes.int16) / Tensor([2, 2], dtype=dtypes.int32)).dtype == dtypes.default_float + assert (Tensor([1, 2], dtype=dtypes.float32) / Tensor([2, 2], dtype=dtypes.float16)).dtype == dtypes.float32 + assert (Tensor([1, 2], dtype=dtypes.int32) / Tensor([2, 2], dtype=dtypes.float16)).dtype == dtypes.float16 + + def test_div_const(self): + assert (Tensor([1, 2], dtype=dtypes.int32) / 2).dtype == dtypes.default_float + assert (Tensor([1, 2], dtype=dtypes.int32) / 2.0).dtype == dtypes.default_float + assert (Tensor([1, 2], dtype=dtypes.float16) / 2).dtype == dtypes.float16 + assert (Tensor([1, 2], dtype=dtypes.float16) / 2.0).dtype == dtypes.float16 + + def test_gradient_dtype(self): + old_default_float = dtypes.default_float + + for default_dtype in [dtypes.float16, dtypes.bfloat16, dtypes.float32, dtypes.float64]: + if not is_dtype_supported(default_dtype): continue + dtypes.default_float = default_dtype + for dtype in [dtypes.float16, dtypes.bfloat16, dtypes.float32, dtypes.float64]: + if not is_dtype_supported(dtype): continue + if DEBUG >= 2: + print(f"testing {default_dtype=}, {dtype=}") + a = Tensor([1, 2, 3], dtype=dtype, requires_grad=True) + b = (a * 5).sum() + b.backward() # if there is dtype mismatch, lazy should assert + assert a.grad.dtype == a.dtype + np.testing.assert_allclose(a.grad.numpy(), [5, 5, 5]) + + dtypes.default_float = old_default_float + + @unittest.skipIf(CI, "TODO: broken RuntimeError: Attempting to relocate against an undefined symbol 'fmaxf'") + @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") + def test_backward_sum_acc_dtype(self): + # test acc of sum in the backward is upcasted to float + t = Tensor([5, -5], dtype=dtypes.half, requires_grad=True) + t.reshape(2, 1).expand(2, 10001).max().backward() + np.testing.assert_allclose(t.grad.numpy(), [1, 0]) + + @unittest.skipIf(Device.DEFAULT == "PYTHON", "very slow") + @unittest.skipIf(CI and Device.DEFAULT == "AMD", "very slow") + @unittest.skipIf(Device.DEFAULT == "WEBGPU", "Binding size is larger than the maximum storage buffer binding size") + @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") + def test_mean_half_precision_underflow(self): + N = 10000 + x = 0.001 + t = Tensor([[x]], dtype=dtypes.half, requires_grad=True).expand(N, N).contiguous() + np.testing.assert_allclose(t.mean(axis=1).numpy(), np.array([x] * N, dtype=np.float16), rtol=1e-3) + + @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") + def test_mean_half_precision_overflow(self): + N = 256 + t = Tensor([60000] * N*N, dtype=dtypes.half, requires_grad=True).reshape(N, N) + np.testing.assert_allclose(t.mean().numpy(), 60000) + t.square().mean().backward() + np.testing.assert_allclose(t.grad.numpy().flatten(), [60000 * 2 / (N*N)] * N*N) + + @unittest.skipIf(Device.DEFAULT == "WEBGPU", "Precision error") + @unittest.skipUnless(is_dtype_supported(dtypes.half), "need half") + def test_softmax_dtype(self): + data = [1, 2, 3] + t = Tensor(data, dtype=dtypes.half) + tt = torch.tensor(data, dtype=torch.half) + + out = t.softmax(0) + self.assertEqual(out.dtype, dtypes.half) + np.testing.assert_allclose(out.numpy(), tt.softmax(0).numpy(), rtol=1e-3) + out = t.softmax(0, dtype=dtypes.float) + self.assertEqual(out.dtype, dtypes.float) + np.testing.assert_allclose(out.numpy(), tt.softmax(0, dtype=torch.float).numpy(), rtol=1e-3) + out = t.log_softmax(0) + self.assertEqual(out.dtype, dtypes.half) + np.testing.assert_allclose(out.numpy(), tt.log_softmax(0).numpy(), rtol=1e-3) + out = t.log_softmax(0, dtype=dtypes.float) + self.assertEqual(out.dtype, dtypes.float) + np.testing.assert_allclose(out.numpy(), tt.log_softmax(0, dtype=torch.float).numpy(), rtol=1e-3) \ No newline at end of file diff --git a/tinygrad_repo/test/unit/test_elf.py b/tinygrad_repo/test/unit/test_elf.py new file mode 100644 index 000000000..cdf02b772 --- /dev/null +++ b/tinygrad_repo/test/unit/test_elf.py @@ -0,0 +1,29 @@ +import unittest, subprocess, platform +from tinygrad.runtime.ops_cpu import ClangJITCompiler +from tinygrad.runtime.support.elf import elf_loader + +class TestElfLoader(unittest.TestCase): + def test_load_clang_jit_strtab(self): + src = ''' + int something; // will be a load from a relocation (needed for .rela.text to exist) + int test(int x) { + return something + x; + } + ''' + args = ('-x', 'c', '-c', '-target', f'{platform.machine()}-none-unknown-elf', '-march=native', '-fPIC', '-O2', '-ffreestanding', '-nostdlib') + obj = subprocess.check_output(('clang',) + args + ('-', '-o', '-'), input=src.encode('utf-8')) + _, sections, _ = elf_loader(obj) + section_names = [sh.name for sh in sections] + assert '.text' in section_names and '.rela.text' in section_names, str(section_names) + def test_clang_jit_compiler_external_raise(self): + src = ''' + int evil_external_function(int); + int test(int x) { + return evil_external_function(x+2)*2; + } + ''' + with self.assertRaisesRegex(RuntimeError, 'evil_external_function'): + ClangJITCompiler().compile(src) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_gguf.py b/tinygrad_repo/test/unit/test_gguf.py new file mode 100644 index 000000000..b36ad14fa --- /dev/null +++ b/tinygrad_repo/test/unit/test_gguf.py @@ -0,0 +1,107 @@ +import os, unittest, ctypes +from tinygrad import dtypes, Tensor, fetch, Device +import numpy as np +from tinygrad.nn.state import ggml_data_to_tensor, gguf_load +from tinygrad.device import is_dtype_supported +try: + import ggml +except ModuleNotFoundError: + raise unittest.SkipTest("ggml not installed, skipping gguf test") + +ggml_test_block_count = 4 +ggml_type_to_np_dtype = { + ggml.GGML_TYPE_F16: np.float16, ggml.GGML_TYPE_F32:np.float32, ggml.GGML_TYPE_F64:np.float64, + ggml.GGML_TYPE_I8:np.int8, ggml.GGML_TYPE_I16: np.int16, ggml.GGML_TYPE_I32: np.int32, ggml.GGML_TYPE_I64: np.int64, +} +np_dtype_to_ctype = { np.float16: ctypes.c_uint16 } +gguf_val_getters = [ + ggml.gguf_get_val_u8, ggml.gguf_get_val_i8, ggml.gguf_get_val_u16, ggml.gguf_get_val_i16, + ggml.gguf_get_val_u32, ggml.gguf_get_val_i32, ggml.gguf_get_val_f32, ggml.gguf_get_val_bool, + lambda *args: ggml.gguf_get_val_str(*args).decode("utf-8"), None, + ggml.gguf_get_val_u64, ggml.gguf_get_val_i64, ggml.gguf_get_val_f64, +] + +def ggml_tensor_to_numpy(tensor: ggml.ggml_tensor_p): + ctx: ggml.ggml_context_p | None = None + ggml_type, n_dims, n_els = tensor.contents.type, ggml.ggml_n_dims(tensor), ggml.ggml_nelements(tensor) + shape = tuple(reversed(tensor.contents.ne[:n_dims])) + if ggml_type not in ggml_type_to_np_dtype: + ctx = ggml.ggml_init(ggml.ggml_init_params(mem_size=n_els * 5 + 500, mem_buffer=None)) + ntensor = ggml.ggml_new_tensor(ctx, ggml.GGML_TYPE_F32, n_dims, tensor.contents.ne) + type_traits = ggml.ggml_internal_get_type_traits(ggml_type) + type_traits.to_float(ggml.ggml_get_data(tensor), ggml.ggml_get_data_f32(ntensor), n_els) + tensor, ggml_type = ntensor, ggml.GGML_TYPE_F32 + + np_type = ggml_type_to_np_dtype[ggml_type] + ctypes_type = np_dtype_to_ctype.get(np_type, None) or np.ctypeslib.as_ctypes_type(np_type) + data = ggml.ggml_get_data(tensor) + if data is None: raise ValueError("tensor data is None") + arr = (ctypes_type * ggml.ggml_nelements(tensor)).from_address(data) + strides = tuple(reversed(tensor.contents.nb[:n_dims])) + output = np.ctypeslib.as_array(arr) + output.dtype = np_type + return np.lib.stride_tricks.as_strided(output, shape=shape, strides=strides), ctx + +@unittest.skipIf(any(not is_dtype_supported(t) for t in [ dtypes.uint8, dtypes.half ]), "Backend must support uint8 and half") +class TestGGUF(unittest.TestCase): + def setUp(self) -> None: + params = ggml.ggml_init_params(mem_size=0, mem_buffer=None, no_alloc=False) + self.ctx = ctypes.cast(ggml.ggml_init(params), ctypes.POINTER(ctypes.c_void_p)) + def tearDown(self) -> None: ggml.ggml_free(self.ctx) + + def test_load_tinyllama_q8_0(self): self._test_gguf_load("https://huggingface.co/ggml-org/models/resolve/main/tinyllamas/stories15M-q8_0.gguf?download=true") + def test_load_tinyllama_q4_0(self): self._test_gguf_load("https://huggingface.co/ggml-org/models/resolve/main/tinyllamas/stories15M-q4_0.gguf?download=true") + def test_load_gpt2_q4_1(self): self._test_gguf_load("https://huggingface.co/PrunaAI/gpt2-GGUF-smashed/resolve/main/gpt2.Q4_1.gguf?download=true") + def test_load_sample_q6_k(self): self._test_gguf_load("https://huggingface.co/Isotr0py/test-gguf-sample/resolve/main/Quant_Q6_K_1024.gguf?download=true") + + def test_dequantization_q4_0(self): self._test_dequantization(ggml.GGML_TYPE_Q4_0) + def test_dequantization_q4_1(self): self._test_dequantization(ggml.GGML_TYPE_Q4_1) + def test_dequantization_q8_0(self): self._test_dequantization(ggml.GGML_TYPE_Q8_0) + def test_dequantization_q6_k(self): self._test_dequantization(ggml.GGML_TYPE_Q6_K) + + def test_expected_failure_unknown_type(self): + with self.assertRaises(ValueError): + ggml_data_to_tensor(Tensor.empty(512, dtype=dtypes.uint8), 256, 1337) + + def _test_dequantization(self, ttype: int): + type_traits = ggml.ggml_internal_get_type_traits(ttype) + n_el, n_bytes = ggml_test_block_count * type_traits.blck_size, ggml_test_block_count * type_traits.type_size + + data_in = (np.random.random((n_el,)).astype(np.float32) * 100 - 50).ctypes.data_as(ctypes.POINTER(ctypes.c_float)) + + c_q_data, c_dq_data = (ctypes.c_char * n_bytes)(0), (ctypes.c_float * n_el)(0) + type_traits.from_float(data_in, c_q_data, n_el) + type_traits.to_float(c_q_data, c_dq_data, n_el) + + q_tensor = Tensor(np.frombuffer(c_q_data, dtype=np.uint8, count=n_bytes)) + dq_tensor = ggml_data_to_tensor(q_tensor, n_el, ttype).reshape(n_el) + + np.testing.assert_equal(dq_tensor.numpy(), np.frombuffer(c_dq_data, dtype=np.float32)) + + def _test_gguf_load(self, url: str): + fp = fetch(url) + model_size = os.stat(fp).st_size + gguf_tensor = Tensor.empty(model_size, dtype=dtypes.uint8, device=f"disk:{fp}").to(Device.DEFAULT) + kv_data, tensors = gguf_load(gguf_tensor) + + gguf_params = ggml.gguf_init_params(ctx=self.ctx, no_alloc=False) + gguf_ctx = ggml.gguf_init_from_file(str(fp).encode("utf8"), gguf_params) + param_ctx = gguf_params.ctx.contents.value + + for ggml_tensor_idx in range(ggml.gguf_get_n_tensors(gguf_ctx)): + tensor_name = ggml.gguf_get_tensor_name(gguf_ctx, ggml_tensor_idx) + ggml_tensor = ggml.ggml_get_tensor(param_ctx, tensor_name) + ggml_tensor_numpy, temp_ctx = ggml_tensor_to_numpy(ggml_tensor) + tensor = tensors.get(tensor_name.decode("utf-8")) + np.testing.assert_equal(tensor.numpy(), ggml_tensor_numpy) + if temp_ctx is not None: ggml.ggml_free(temp_ctx) + + for gguf_key_id in range(ggml.gguf_get_n_kv(gguf_ctx)): + v = kv_data[ggml.gguf_get_key(gguf_ctx, gguf_key_id).decode("utf-8")] + v_type = ggml.gguf_get_kv_type(gguf_ctx, gguf_key_id) + if (get_fn := gguf_val_getters[v_type]) is not None: self.assertEqual(get_fn(gguf_ctx, gguf_key_id), v) + + ggml.gguf_free(gguf_ctx) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_gradient.py b/tinygrad_repo/test/unit/test_gradient.py new file mode 100644 index 000000000..2739fe900 --- /dev/null +++ b/tinygrad_repo/test/unit/test_gradient.py @@ -0,0 +1,147 @@ +from typing import Callable +import unittest, math +import torch +import numpy as np +from tinygrad import Tensor +from tinygrad.dtype import dtypes +from tinygrad.uop.ops import UOp +from tinygrad.gradient import compute_gradient + +class TestGradient(unittest.TestCase): + def _cmp_nan_okay(self, x, y): + if math.isnan(x) and math.isnan(y): return + self.assertAlmostEqual(x, y, places=5) + + def _test_one_input_function(self, f:Callable, jf:Callable|None=None): + if jf is None: jf = f + x = UOp.variable('x', -math.inf, math.inf, dtype=dtypes.float) + gx = compute_gradient(f(x), UOp.const(dtypes.float, 1.0), set([x]))[x] + + for val in [-5., -2.0, 0.0, 2.0, 5.]: + tg_out = gx.substitute({x: x.const_like(val)}).ssimplify() + tx = torch.tensor([val], dtype=torch.float, requires_grad=True) + torch_out = torch.autograd.grad(jf(tx), tx)[0].item() + self._cmp_nan_okay(tg_out, torch_out) + + def _test_two_input_function(self, f:Callable, jf:Callable|None=None): + if jf is None: jf = f + x = UOp.variable('x', -math.inf, math.inf, dtype=dtypes.float) + y = UOp.variable('y', -math.inf, math.inf, dtype=dtypes.float) + grads = compute_gradient(f(x, y), UOp.const(dtypes.float, 1.0), set([x, y])) + gx, gy = grads[x], grads[y] + + for valx in [-5., -2.0, 0.0, 2.0, 5.]: + for valy in [-5., -2.0, 0.0, 2.0, 5.]: + # Substitute the values into the gradient expressions + substitutions = {x: x.const_like(valx), y: y.const_like(valy)} + tg_out_x = gx.substitute(substitutions).ssimplify() + tg_out_y = gy.substitute(substitutions).ssimplify() + + tx = torch.tensor([valx], dtype=torch.float, requires_grad=True) + ty = torch.tensor([valy], dtype=torch.float, requires_grad=True) + torch_grad = torch.autograd.grad(jf(tx, ty), [tx, ty]) + torch_out_x, torch_out_y = [x.item() for x in torch_grad] + + self._cmp_nan_okay(tg_out_x, torch_out_x) + self._cmp_nan_okay(tg_out_y, torch_out_y) + + # unary ops unit + def test_recip(self): self._test_one_input_function(lambda x: 1.0/x) + def test_sin(self): self._test_one_input_function(lambda x: x.sin()) + def test_sqrt(self): self._test_one_input_function(lambda x: x.sqrt()) + def test_log2(self): self._test_one_input_function(lambda x: x.log2()) + def test_exp2(self): self._test_one_input_function(lambda x: x.exp2()) + + # binary ops unit + def test_add(self): self._test_two_input_function(lambda x,y: x+y) + def test_mul(self): self._test_two_input_function(lambda x,y: x*y) + + # chain rule + def test_chain(self): self._test_one_input_function(lambda x: x.sin().sqrt()) + def test_chain_binop(self): self._test_two_input_function(lambda x,y: (x*y)+x*y) + def test_big_add_sin(self): self._test_two_input_function(lambda x,y: x.sin()+3.0/y) + def test_big_chain(self): self._test_two_input_function(lambda x,y: (1.0/x*y)+x*y) + def test_where(self): self._test_two_input_function(lambda x,y: (x 0, + f"Expected +inf for reciprocal(0.0), got {optimized_recip_zero.arg}") + + @unittest.skip("broken") + def test_full_graph_rewrite_modulo_negative_dividend(self): + x_var_uop = UOp.variable('x', -5, -1) + optimized_sink = full_rewrite_to_sink((x_var_uop % 3).sink()) + for x_value in range(-5, 0): + self.assertEqual(x_value % 3, evaluate_uop(optimized_sink.src[0], {'x': x_value})) + + @unittest.skip("broken") + def test_full_graph_rewrite_division_negative_divisor(self): + x_var_uop = UOp.variable('x', 1, 5) + optimized_sink = full_rewrite_to_sink((x_var_uop // -2).sink()) + for x_value in range(1, 6): + self.assertEqual(x_value // -2, evaluate_uop(optimized_sink.src[0], {'x': x_value})) + +class TestGEPAndVectorizeRewrite(unittest.TestCase): + def test_gep_single_element_extraction(self): + # GEP on a vector dtype to extract a single element + base_vector = UOp.const(dtypes.float32.vec(4), (1.0, 2.0, 3.0, 4.0)) + self.assertEqual(apply_rewrite(base_vector.gep(2)).arg, 3.0) + + def test_gep_tuple_extraction(self): + # GEP on a vector dtype to extract multiple elements as a vector + base_vector = UOp.const(dtypes.float32.vec(4), (1.0, 2.0, 3.0, 4.0)) + optimized_uop = apply_rewrite(base_vector.gep((2, 3))) + self.assertEqual([sub_uop.arg for sub_uop in optimized_uop.src], [3.0, 4.0]) + + def test_gep_on_vconst(self): + # GEP on a VCONST to extract a single element + vconst = UOp(Ops.VCONST, dtypes.float32.vec(4), arg=(1.0, 2.0, 3.0, 4.0)) + self.assertEqual(apply_rewrite(vconst.gep(2)).arg, 3.0) + + def test_gep_tuple_on_vconst(self): + # GEP on a VCONST using a tuple to extract multiple elements + vconst = UOp(Ops.VCONST, dtypes.float32.vec(4), arg=(7.0, 8.0, 9.0, 10.0)) + optimized_uop = apply_rewrite(vconst.gep((1, 3))) + self.assertEqual([sub_uop.arg for sub_uop in optimized_uop.src], [8.0, 10.0]) + + def test_gep_gep_simplification(self): + # Nested GEP simplification on a vector dtype + base_vector = UOp.const(dtypes.float32.vec(4), (10.0, 20.0, 30.0, 40.0)) + gep_inner = base_vector.gep(1) # Extract 2nd element (20.0) + self.assertEqual(apply_rewrite(gep_inner.gep(0)).arg, 20.0) + + def test_vectorize_multiple_elements(self): + # Vectorizing multiple elements using GEP + base_vector = UOp.const(dtypes.float32.vec(4), (5.0, 10.0, 15.0, 20.0)) + vectorized_uop = UOp(Ops.VECTORIZE, dtypes.float32.vec(4), src=(base_vector.gep(0), base_vector.gep(1), base_vector.gep(2), base_vector.gep(3))) + optimized_uop = apply_rewrite(vectorized_uop) + self.assertEqual([sub_uop.arg for sub_uop in optimized_uop.src], [5.0, 10.0, 15.0, 20.0]) + + +import inspect +from tinygrad.uop.ops import graph_rewrite, _substitute, track_rewrites +from tinygrad.uop.symbolic import symbolic_simple + +class TestBottomUpRewrite(unittest.TestCase): + def test_const_folding(self): + a = UOp.const(dtypes.int, 5) + ret = (a*3) + (a*7) + gt = graph_rewrite(ret, symbolic_simple) + ret = graph_rewrite(ret, symbolic_simple, bottom_up=True) + self.assertIs(gt, ret) + +# normally .substitute would be fine, but it's not tracked +@track_rewrites() +def named_substitute(name:str, uop:UOp, rel:dict[UOp, UOp]): return graph_rewrite(uop, _substitute, rel, bottom_up=True) +def substitute(uop:UOp, rel:dict[UOp, UOp]): return named_substitute(inspect.stack()[1].function, uop, rel) + +class TestSubstitute(unittest.TestCase): + # these work because the substituted things don't have parents + def test_simple(self): + a = UOp.variable('a', 0, 10) + b = UOp.variable('b', 0, 10) + ret = a + 4 + ret = substitute(ret, {a:b}) + self.assertIs(ret, b+4) + + def test_double(self): + a = UOp.variable('a', 0, 10) + b = UOp.variable('b', 0, 10) + c = UOp.variable('c', 0, 10) + ret = (a + 4) + b + ret = substitute(ret, {a:c, b:c}) + self.assertIs(ret, (c + 4) + c) + + def test_diamond(self): + a = UOp.variable('a', 0, 10) + b = UOp.variable('b', 0, 10) + ret = (a + 4) + (a + 5) + ret = substitute(ret, {a:b}) + self.assertIs(ret, (b + 4) + (b + 5)) + + # this works because there's nothing above the substituted node + def test_sin(self): + a = UOp.variable('a', 0, 10) + b = UOp.variable('b', 0, 10) + ret = a.sin().sin() + ret = substitute(ret, {a.sin():b}) + self.assertIs(ret, b.sin()) + + # broken due to infinite recursion + # NOTE: VIZ hangs and doesn't recover if you click this one + @unittest.skip("recursion error no longer raised") + def test_assert_inf_recurse(self): + a = UOp.variable('a', 0, 10) + n1 = a.sin() + ret = n1 + with self.assertRaises(RecursionError): + ret = substitute(ret, {n1:n1.sqrt()}) + + def test_sin_to_sqrt(self): + a = UOp.variable('a', 0, 10) + n1 = a.sin() + ret = n1.sin() + ret = substitute(ret, {a.sin():a.sqrt()}) + self.assertIs(ret, a.sqrt().sin()) + + def test_double_sin_to_sqrt(self): + a = UOp.variable('a', 0, 10) + n1 = a.sin() + ret = n1.sin() + # NOTE: this would work if it had gone in the opposite order + ret = substitute(ret, {a.sin():a.sqrt(), n1.sin():n1.sqrt()}) + self.assertIs(ret, a.sqrt().sqrt()) + + def test_tagged_replace(self): + a = UOp.variable('a', 0, 10) + b = UOp.variable('b', 0, 10) + ret = (a+4).replace(tag=1) + ret = substitute(ret, {a:b}) + # the srcs are rewritten but we keep tag + self.assertIs(ret, (b+4).replace(tag=1)) + +class TestRecurse(unittest.TestCase): + def test_no_inf_loop(self): + a = UOp.variable('a', 0, 10) + pm = PatternMatcher([(UPat(Ops.DEFINE_VAR, name="x"), lambda x: x)]) + graph_rewrite(a, pm) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_helpers.py b/tinygrad_repo/test/unit/test_helpers.py new file mode 100644 index 000000000..282f69694 --- /dev/null +++ b/tinygrad_repo/test/unit/test_helpers.py @@ -0,0 +1,367 @@ +import ctypes, gzip, unittest +from tinygrad import Variable +from tinygrad.helpers import Context, ContextVar, argfix +from tinygrad.helpers import merge_dicts, strip_parens, prod, round_up, fetch, fully_flatten, from_mv, to_mv, polyN, time_to_str, cdiv, cmod, getbits +from tinygrad.tensor import get_shape +from tinygrad.shape.view import get_contraction, get_contraction_with_reduce +import numpy as np + +VARIABLE = ContextVar("VARIABLE", 0) + +class TestContextVars(unittest.TestCase): + # Ensuring that the test does not modify variables outside the tests. + ctx = Context() + def setUp(self): TestContextVars.ctx.__enter__() + def tearDown(self): TestContextVars.ctx.__exit__() + + def test_initial_value_is_set(self): + _TMP = ContextVar("_TMP", 5) + self.assertEqual(_TMP.value, 5) + + def test_cannot_recreate(self): + _TMP2 = ContextVar("_TMP2", 1) + with self.assertRaises(RuntimeError): + _TMP2 = ContextVar("_TMP2", 2) + + def test_new_var_inside_context(self): + with Context(VARIABLE=1): + _TMP3 = ContextVar("_TMP3", 1) + with self.assertRaises(RuntimeError): + _TMP3 = ContextVar("_TMP3", 2) + + def test_value_across_modules(self): + # Mocking module import by invoking the code but not in our globals(). + exec('from tinygrad.helpers import ContextVar;C = ContextVar("C", 13)', {}) # pylint:disable=exec-used + # It should not matter that the first creation was in another module. + with self.assertRaises(RuntimeError): + _C = ContextVar("C", 0) + + def test_assignment_across_modules(self): + B = ContextVar("B", 1) + # local assignment + B.value = 2 + self.assertEqual(B.value, 2) + with self.assertRaises(RuntimeError): + # Assignment in another module. + exec('from tinygrad.helpers import ContextVar;B = ContextVar("B", 0);B.value = 3;', {}) # pylint:disable=exec-used + + def test_context_assignment(self): + with Context(VARIABLE=1): + self.assertEqual(VARIABLE.value, 1) + self.assertEqual(VARIABLE.value, 0) + + def test_unknown_param_to_context(self): + with self.assertRaises(KeyError): + with Context(SOMETHING_ELSE=1): + pass + + def test_nested_context(self): + with Context(VARIABLE=1): + with Context(VARIABLE=2): + MORE = ContextVar("MORE", 2) + with Context(VARIABLE=3, MORE=3): + self.assertEqual(VARIABLE.value, 3) + self.assertEqual(MORE.value, 3) + self.assertEqual(VARIABLE.value, 2) + self.assertEqual(MORE.value, 2) + self.assertEqual(VARIABLE.value, 1) + self.assertEqual(MORE.value, 2) # TODO: should this raise? + self.assertEqual(VARIABLE.value, 0) + + def test_decorator(self): + @Context(VARIABLE=1, DEBUG=4) + def test(): + self.assertEqual(VARIABLE.value, 1) + + self.assertEqual(VARIABLE.value, 0) + test() + self.assertEqual(VARIABLE.value, 0) + + def test_context_exit_reverts_updated_values(self): + D = ContextVar("D", 1) + D.value = 2 + with Context(D=3): + ... + assert D.value == 2, f"Expected D to be 2, but was {D.value}. Indicates that Context.__exit__ did not restore to the correct value." + +class TestMergeDicts(unittest.TestCase): + def test_merge_dicts(self): + a = {"a": 1, "b": 2} + b = {"a": 1, "c": 3} + c = {} + d = {"a": 2, "b": 2} + assert merge_dicts([a, b]) == {"a": 1, "b": 2, "c": 3} + assert merge_dicts([a, c]) == a + assert merge_dicts([a, b, c]) == {"a": 1, "b": 2, "c": 3} + with self.assertRaises(AssertionError): + merge_dicts([a, d]) + +class TestStripParens(unittest.TestCase): + def test_simple(self): self.assertEqual("1+2", strip_parens("(1+2)")) + def test_nested(self): self.assertEqual("1+(2+3)", strip_parens("(1+(2+3))")) + def test_casted_no_strip(self): self.assertEqual("(int)(1+2)", strip_parens("(int)(1+2)")) + +class TestProd(unittest.TestCase): + def test_empty(self): self.assertEqual(1, prod(tuple())) + def test_ints(self): self.assertEqual(30, prod((2, 3, 5))) + def test_variable(self): self.assertEqual("(a*12)", prod((Variable("a", 1, 5), 3, 4)).render()) + def test_variable_order(self): self.assertEqual("(a*12)", prod((3, 4, Variable("a", 1, 5))).render()) + +class TestRoundUp(unittest.TestCase): + def test_round_up(self): + self.assertEqual(round_up(-3,4), 0) + self.assertEqual(round_up(-4,4), -4) + self.assertEqual(round_up(6,4), 8) + self.assertEqual(round_up(8,4), 8) + self.assertEqual(round_up(232, 24984), 24984) + self.assertEqual(round_up(24984, 232), 25056) + +@unittest.skip("no fetch tests because they need internet") +class TestFetch(unittest.TestCase): + def test_fetch_bad_http(self): + self.assertRaises(Exception, fetch, 'http://www.google.com/404', allow_caching=False) + + def test_fetch_small(self): + assert (len(fetch('https://google.com', allow_caching=False).read_bytes())>0) + + def test_fetch_img(self): + from PIL import Image + img = fetch("https://avatars.githubusercontent.com/u/132956020", allow_caching=False) + with Image.open(img) as pimg: + assert pimg.size == (77, 77), pimg.size + + def test_fetch_subdir(self): + from PIL import Image + img = fetch("https://avatars.githubusercontent.com/u/132956020", allow_caching=False, subdir="images") + with Image.open(img) as pimg: + assert pimg.size == (77, 77), pimg.size + assert img.parent.name == "images" + + def test_fetch_gunzip_valid(self): + # compare fetch(gunzip=True) to fetch(gunzip=False) plus decompressing afterwards + gzip_url: str = 'https://ftp.gnu.org/gnu/gzip/gzip-1.13.tar.gz' + fp_gz = fetch(gzip_url, gunzip=True) + fp_no_gz = fetch(gzip_url, gunzip=False) + with open(fp_gz, 'rb') as f: content_gz = f.read() + with open(fp_no_gz, 'rb') as f: content_no_gz = gzip.decompress(f.read()) + assert fp_gz.stat().st_size > fp_no_gz.stat().st_size + assert isinstance(content_gz, bytes) and isinstance(content_no_gz, bytes) + assert len(content_gz) == len(content_no_gz) + assert content_gz == content_no_gz + + def test_fetch_gunzip_invalid(self): + # given a non-gzipped file, fetch(gunzip=True) fails + no_gzip_url: str = 'https://ftp.gnu.org/gnu/gzip/gzip-1.13.zip' + with self.assertRaises(gzip.BadGzipFile): + fetch(no_gzip_url, gunzip=True) + + def test_fetch_user_agent(self): + fetch("https://csrc.nist.gov/CSRC/media/Projects/lightweight-cryptography/documents/finalist-round/updated-submissions/sparkle.zip", + allow_caching=False) + +class TestFullyFlatten(unittest.TestCase): + def test_fully_flatten(self): + self.assertEqual(fully_flatten([[1, 3], [1, 2]]), [1, 3, 1, 2]) + self.assertEqual(fully_flatten(((1, 3), (1, 2))), [1, 3, 1, 2]) + self.assertEqual(fully_flatten([[[1], [3]], [[1], [2]]]), [1, 3, 1, 2]) + self.assertEqual(fully_flatten([[[[1], 2], 3], 4]), [1, 2, 3, 4]) + self.assertEqual(fully_flatten([[1, 2, [3, 4]], [5, 6], 7]), [1, 2, 3, 4, 5, 6, 7]) + self.assertEqual(fully_flatten([[1, "ab"], [True, None], [3.14, [5, "b"]]]), [1, "ab", True, None, 3.14, 5, "b"]) + + def test_fully_flatten_numpy(self): + self.assertEqual(fully_flatten([np.array([])]), []) + self.assertEqual(fully_flatten([np.array(3)]), [3]) + self.assertEqual(fully_flatten([np.array([3])]), [3]) + self.assertEqual(fully_flatten([np.array([[3]])]), [3]) + self.assertEqual(fully_flatten([np.array([1, 3]), np.array([1, 2])]), [1, 3, 1, 2]) + self.assertEqual(fully_flatten((np.array([1, 3]), np.array([1, 2]))), [1, 3, 1, 2]) + self.assertEqual(fully_flatten([np.array([[1], [3]]), np.array([[1], [2]])]), [1, 3, 1, 2]) + self.assertEqual(fully_flatten([[1, "ab"], [True, None], np.array([[3.14], [6.28]])]), [1, "ab", True, None, 3.14, 6.28]) + +class TestMemoryview(unittest.TestCase): + def test_from_mv_to_mv(self): + base = memoryview(bytearray(b"\x11\x22\x33"*40)) + ct = from_mv(base) + mv = to_mv(ctypes.addressof(ct), len(base)) + mv[0] = 2 + assert base[0] == 2 + +class TestGetContraction(unittest.TestCase): + def test_contraction_with_reduce(self): + r = get_contraction((16, 1, 1, 1), (16, 1, 1)) + self.assertEqual(r, [[0], [], [1, 2, 3]]) + r = get_contraction_with_reduce((16, 1, 1, 1), (16, 1, 1), (1,)) + self.assertEqual(r, [[0], [1, 2], [3]]) + + r = get_contraction((16, 1, 1, 1, 1), (16, 1, 1, 1)) + self.assertEqual(r, [[0], [], [], [1, 2, 3, 4]]) + r = get_contraction_with_reduce((16, 1, 1, 1, 1), (16, 1, 1, 1), (1,)) + self.assertEqual(r, [[0], [1, 2], [3], [4]]) + + r = get_contraction_with_reduce((2, 512, 1, 1), (2, 1, 512), (1,)) + self.assertIsNone(r) + + def test_contraction(self): + r = get_contraction((1,2,3,4), (2,3,4)) + self.assertEqual(r, [[0, 1], [2], [3]]) + + r = get_contraction((2,1,3,4), (2,3,4)) + self.assertEqual(r, [[0], [1, 2], [3]]) + + r = get_contraction((1,2,3,1,4), (1,2,3,4)) + self.assertEqual(r, [[], [0, 1], [2], [3, 4]]) + + r = get_contraction((1,2,3,1,4,1,1), (2,3,4)) + self.assertEqual(r, [[0, 1], [2], [3, 4, 5, 6]]) + + r = get_contraction((1,2,3,4), (1,2,3*4)) + self.assertEqual(r, [[], [0, 1], [2, 3]]) + + r = get_contraction((1,2,3,4), (2,1,3,4)) + self.assertEqual(r, [[0, 1], [], [2], [3]]) + + r = get_contraction((1,2,3,4), (1,1,2*3*4,1)) + self.assertEqual(r, [[], [], [0,1,2,3], []]) + + r = get_contraction((2,1,3,4), (1,2,3,4)) + self.assertEqual(r, [[], [0], [1, 2], [3]]) + + r = get_contraction((1,2,3,4), (2*3*4,1,1,1)) + self.assertEqual(r, [[0, 1, 2, 3], [], [], []]) + + r = get_contraction((4,4,4,4), (16,1,16)) + self.assertEqual(r, [[0, 1], [], [2, 3]]) + + r = get_contraction((1,2,3,4,1,1,1), (2,3,4)) + self.assertEqual(r, [[0, 1], [2], [3, 4, 5, 6]]) + + r = get_contraction((1,2,3,4), (1,2,3,4,1)) + self.assertEqual(r, [[], [0, 1], [2], [3], []]) + + r = get_contraction((14,1,384,14,1,1,1,1), (1,14,384,14)) + self.assertEqual(r, [[], [0], [1,2], [3,4,5,6,7]]) + + r = get_contraction((14,1,384,1,14,1,1,1,1), (1,14,384,14)) + self.assertEqual(r, [[], [0], [1,2], [3,4,5,6,7,8]]) + + r = get_contraction((512, 512), (1, 1, 512, 1, 1, 1, 1, 512)) + self.assertEqual(r, [[], [], [0], [], [], [], [], [1]]) + + r = get_contraction((1,2,3,4), (1,2,6,2)) + self.assertEqual(r, None) + + def test_contraction_ones(self): + r = get_contraction((1,), (1,1,1)) + self.assertEqual(r, [[], [], [0]]) + + r = get_contraction((1,1), (1,1,1)) + self.assertEqual(r, [[], [], [0, 1]]) + + r = get_contraction((1,1,1,1), (1,)) + self.assertEqual(r, [[0,1,2,3]]) + + r = get_contraction((1,1,1,1), (1,1)) + self.assertEqual(r, [[], [0,1,2,3]]) + + r = get_contraction((1,1,1,1), (1,1,1)) + self.assertEqual(r, [[], [], [0,1,2,3]]) + + r = get_contraction((1,1,1,1), (1,1,1,1)) + self.assertEqual(r, [[], [], [], [0,1,2,3]]) + +class TestGetShape(unittest.TestCase): + def test_get_shape(self): + assert get_shape(2) == () + assert get_shape([]) == (0,) + assert get_shape([[]]) == (1, 0) + assert get_shape([[1, 2]]) == (1, 2) + assert get_shape([[1, 2], (3, 4)]) == (2, 2) + + def test_inhomogeneous_shape(self): + with self.assertRaises(ValueError): get_shape([[], [1]]) + with self.assertRaises(ValueError): get_shape([[1, [2]], [1]]) + +class TestPolyN(unittest.TestCase): + def test_float(self): + np.testing.assert_allclose(polyN(1.0, [1.0, -2.0, 1.0]), 0.0) + np.testing.assert_allclose(polyN(2.0, [1.0, -2.0, 1.0]), 1.0) + np.testing.assert_allclose(polyN(3.0, [1.0, -2.0, 1.0]), 4.0) + np.testing.assert_allclose(polyN(4.0, [1.0, -2.0, 1.0]), 9.0) + + def test_tensor(self): + from tinygrad.tensor import Tensor + np.testing.assert_allclose(polyN(Tensor([1.0, 2.0, 3.0, 4.0]), [1.0, -2.0, 1.0]).numpy(), [0.0, 1.0, 4.0, 9.0]) + + def test_uop(self): + from tinygrad.dtype import dtypes + from tinygrad.uop.ops import UOp + from test.helpers import eval_uop + np.testing.assert_allclose(eval_uop(polyN(UOp.const(dtypes.float, 1.0), [1.0, -2.0, 1.0])), 0.0) + np.testing.assert_allclose(eval_uop(polyN(UOp.const(dtypes.float, 2.0), [1.0, -2.0, 1.0])), 1.0) + np.testing.assert_allclose(eval_uop(polyN(UOp.const(dtypes.float, 3.0), [1.0, -2.0, 1.0])), 4.0) + np.testing.assert_allclose(eval_uop(polyN(UOp.const(dtypes.float, 4.0), [1.0, -2.0, 1.0])), 9.0) + +class TestTimeToStr(unittest.TestCase): + def test_seconds(self): self.assertEqual(" 10.01s ", time_to_str(10.01)) + def test_boundary_sec_ms(self): self.assertEqual("10000.00ms", time_to_str(10)) + def test_milliseconds(self): self.assertEqual(" 500.00ms", time_to_str(0.5)) + def test_boundary_ms_us(self): self.assertEqual("10000.00us", time_to_str(0.01)) + def test_microseconds(self): self.assertEqual(" 100.00us", time_to_str(0.0001)) + def test_zero(self): self.assertEqual(" 0.00us", time_to_str(0)) + def test_width_formatting(self): self.assertEqual(" 10.01s ", time_to_str(10.01, w=6)) + +class TestCStyleDivMod(unittest.TestCase): + def test_div_pos(self): + self.assertEqual(cdiv(-9, 5), -1) + self.assertEqual(cdiv(-4, 5), 0) + self.assertEqual(cdiv(0, 5), 0) + self.assertEqual(cdiv(4, 5), 0) + self.assertEqual(cdiv(9, 5), 1) + def test_div_neg(self): + self.assertEqual(cdiv(-9, -5), 1) + self.assertEqual(cdiv(-4, -5), 0) + self.assertEqual(cdiv(0, -5), 0) + self.assertEqual(cdiv(4, -5), 0) + self.assertEqual(cdiv(9, -5), -1) + def test_mod_pos(self): + self.assertEqual(cmod(-9, 5), -4) + self.assertEqual(cmod(-4, 5), -4) + self.assertEqual(cmod(0, 5), 0) + self.assertEqual(cmod(4, 5), 4) + self.assertEqual(cmod(9, 5), 4) + def test_mod_neg(self): + self.assertEqual(cmod(-9, -5), -4) + self.assertEqual(cmod(-4, -5), -4) + self.assertEqual(cmod(0, -5), 0) + self.assertEqual(cmod(4, -5), 4) + self.assertEqual(cmod(9, -5), 4) + +class TestGetBits(unittest.TestCase): + def test_low_bits(self): + self.assertEqual(getbits(0b11010110, 0, 3), 0b0110) + + def test_high_bits(self): + self.assertEqual(getbits(0b11010110, 4, 7), 0b1101) + + def test_middle_bits(self): + self.assertEqual(getbits(0b11010110, 3, 5), 0b010) + + def test_full_range(self): + self.assertEqual(getbits(0b11010110, 0, 7), 0b11010110) + + def test_single_bit(self): + self.assertEqual(getbits(0b100000000, 8, 8), 1) + +class TestArgFix(unittest.TestCase): + def test_none(self): + self.assertEqual(argfix(None), (None, )) + self.assertEqual(argfix(None, None), (None, None)) + def test_positional_arguments(self): + self.assertEqual(argfix(1, 2, 3), (1, 2, 3)) + def test_tuple(self): + self.assertEqual(argfix((1., 2., 3.)), (1., 2., 3.)) + def test_list(self): + self.assertEqual(argfix([True, False]), (True, False)) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_indexing.py b/tinygrad_repo/test/unit/test_indexing.py new file mode 100644 index 000000000..da5d61944 --- /dev/null +++ b/tinygrad_repo/test/unit/test_indexing.py @@ -0,0 +1,1573 @@ +# test cases are modified from pytorch test_indexing.py https://github.com/pytorch/pytorch/blob/597d3fb86a2f3b8d6d8ee067e769624dcca31cdb/test/test_indexing.py + +import unittest, random, warnings +import numpy as np + +from tinygrad import Tensor, dtypes, Device, TinyJit +from tinygrad.device import is_dtype_supported +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.shape.view import View +from tinygrad.helpers import CI, all_same, prod + +random.seed(42) + +def numpy_testing_assert_equal_helper(a, b): + if isinstance(a, Tensor): a = a.numpy() + if isinstance(b, Tensor): b = b.numpy() + np.testing.assert_equal(a, b) + +def consec(shape, start=1): + return Tensor.arange(prod(shape)).reshape(shape)+start + +# creates strided tensor with base set to reference tensor's base, equivalent to torch.set_() +def set_(reference: Tensor, shape, strides, offset): + raise NotImplementedError("need to implement without calling uop.view") + if reference.uop.base.realized is None: reference.realize() + assert reference.uop.base.realized, "base has to be realized before setting it to strided's base" + strided = Tensor(reference.uop.view(ShapeTracker((View.create(shape=shape, strides=strides, offset=offset),)))) + assert strided.uop.st.real_strides() == strides, "real_strides should equal strides for strided" + return strided + +def clone(original:Tensor): return original.clone() +def copy_(src:Tensor, other:Tensor) -> Tensor: return src.clone() +# this is fine for tested usecases since as geohotstan understands, +# data_ptr is used to compare if operations needed between tensors is the same +def data_ptr(tensor:Tensor): return tensor.uop + +# https://pytorch.org/docs/stable/generated/torch.Tensor.index_put_.html +def index_put_(tensor:Tensor, indices, values, accumulate) -> Tensor: + if accumulate: tensor[indices] += values + else: tensor[indices] = values + +# https://pytorch.org/docs/stable/generated/torch.argsort.html +def argsort(tensor:Tensor) -> Tensor: + pass + +# https://pytorch.org/docs/stable/generated/torch.all.html +def all_(tensor:Tensor) -> Tensor: + return tensor != 0 + +# https://pytorch.org/docs/stable/generated/torch.diagonal.html +def diagonal(tensor:Tensor) -> Tensor: + assert tensor.ndim == 2 and all_same(tensor.shape), 'only support 2 ndim square tensors' + return (Tensor.eye(tensor.shape[0]) * tensor).sum(0) + +# https://numpy.org/doc/stable/reference/generated/numpy.unravel_index.html +def unravel_index(tensor, shape): + pass + +# https://github.com/pytorch/pytorch/blob/79811e765c23242210ebdc623539d2103a166463/torch/testing/_creation.py#L38 +def make_tensor(shape, dtype:dtypes, noncontiguous) -> Tensor: + r"""Creates a tensor with the given :attr:`shape`, :attr:`device`, and :attr:`dtype`, and filled with + values uniformly drawn from ``[low, high)``. + + If :attr:`low` or :attr:`high` are specified and are outside the range of the :attr:`dtype`'s representable + finite values then they are clamped to the lowest or highest representable finite value, respectively. + If ``None``, then the following table describes the default values for :attr:`low` and :attr:`high`, + which depend on :attr:`dtype`. + + +---------------------------+------------+----------+ + | ``dtype`` | ``low`` | ``high`` | + +===========================+============+==========+ + | boolean type | ``0`` | ``2`` | + +---------------------------+------------+----------+ + | unsigned integral type | ``0`` | ``10`` | + +---------------------------+------------+----------+ + | signed integral types | ``-9`` | ``10`` | + +---------------------------+------------+----------+ + | floating types | ``-9`` | ``9`` | + +---------------------------+------------+----------+ + | complex types | ``-9`` | ``9`` | + +---------------------------+------------+----------+ + """ + contiguous = not noncontiguous + if dtype == dtypes.bool: return Tensor.randint(shape=shape, low=0, high=2, contiguous=contiguous).cast(dtypes.bool) + elif dtype.is_unsigned(): return Tensor.randint(shape=shape, low=0, high=10, contiguous=contiguous).cast(dtype) + elif dtype.is_int(): return Tensor.randint(shape=shape, low=-9, high=10, contiguous=contiguous).cast(dtype) # signed int + elif dtype.is_float(): return Tensor.rand(shape=shape, low=-9, high=9, dtype=dtype, contiguous=contiguous) + else: raise NotImplementedError(f"{dtype} not implemented") + +class TestIndexing(unittest.TestCase): + def test_index(self): + + reference = consec((3, 3, 3)) + + numpy_testing_assert_equal_helper(reference[0], consec((3, 3))) + numpy_testing_assert_equal_helper(reference[1], consec((3, 3), 10)) + numpy_testing_assert_equal_helper(reference[2], consec((3, 3), 19)) + numpy_testing_assert_equal_helper(reference[0, 1], consec((3,), 4)) + numpy_testing_assert_equal_helper(reference[0:2], consec((2, 3, 3))) + numpy_testing_assert_equal_helper(reference[2, 2, 2], 27) + numpy_testing_assert_equal_helper(reference[:], consec((3, 3, 3))) + + # indexing with Ellipsis + numpy_testing_assert_equal_helper(reference[..., 2], np.array([[3., 6., 9.],[12., 15., 18.],[21., 24., 27.]])) + numpy_testing_assert_equal_helper(reference[0, ..., 2], np.array([3., 6., 9.])) + numpy_testing_assert_equal_helper(reference[..., 2], reference[:, :, 2]) + numpy_testing_assert_equal_helper(reference[0, ..., 2], reference[0, :, 2]) + numpy_testing_assert_equal_helper(reference[0, 2, ...], reference[0, 2]) + numpy_testing_assert_equal_helper(reference[..., 2, 2, 2], 27) + numpy_testing_assert_equal_helper(reference[2, ..., 2, 2], 27) + numpy_testing_assert_equal_helper(reference[2, 2, ..., 2], 27) + numpy_testing_assert_equal_helper(reference[2, 2, 2, ...], 27) + numpy_testing_assert_equal_helper(reference[...], reference) + + reference_5d = consec((3, 3, 3, 3, 3)) + numpy_testing_assert_equal_helper(reference_5d[..., 1, 0], reference_5d[:, :, :, 1, 0]) + numpy_testing_assert_equal_helper(reference_5d[2, ..., 1, 0], reference_5d[2, :, :, 1, 0]) + numpy_testing_assert_equal_helper(reference_5d[2, 1, 0, ..., 1], reference_5d[2, 1, 0, :, 1]) + numpy_testing_assert_equal_helper(reference_5d[...], reference_5d) + + # None indexing + numpy_testing_assert_equal_helper(reference[2, None], reference[2].unsqueeze(0)) + numpy_testing_assert_equal_helper(reference[2, None, None], reference[2].unsqueeze(0).unsqueeze(0)) + numpy_testing_assert_equal_helper(reference[2:4, None], reference[2:4].unsqueeze(1)) + numpy_testing_assert_equal_helper(reference[None, 2, None, None], reference.unsqueeze(0)[:, 2].unsqueeze(0).unsqueeze(0)) + numpy_testing_assert_equal_helper(reference[None, 2:5, None, None], reference.unsqueeze(0)[:, 2:5].unsqueeze(2).unsqueeze(2)) + + # indexing 0-length slice + numpy_testing_assert_equal_helper(np.empty((0, 3, 3)), reference[slice(0)]) + numpy_testing_assert_equal_helper(np.empty((0, 3)), reference[slice(0), 2]) + numpy_testing_assert_equal_helper(np.empty((0, 3)), reference[2, slice(0)]) + numpy_testing_assert_equal_helper(np.empty([]), reference[2, 1:1, 2]) + + # indexing with step + reference = consec((10, 10, 10)) + numpy_testing_assert_equal_helper(reference[1:5:2], Tensor.stack(reference[1], reference[3], dim=0)) + numpy_testing_assert_equal_helper(reference[1:6:2], Tensor.stack(reference[1], reference[3], reference[5], dim=0)) + numpy_testing_assert_equal_helper(reference[1:9:4], Tensor.stack(reference[1], reference[5], dim=0)) + numpy_testing_assert_equal_helper(reference[2:4, 1:5:2], Tensor.stack(reference[2:4, 1], reference[2:4, 3], dim=1)) + numpy_testing_assert_equal_helper(reference[3, 1:6:2], Tensor.stack(reference[3, 1], reference[3, 3], reference[3, 5], dim=0)) + numpy_testing_assert_equal_helper(reference[None, 2, 1:9:4], Tensor.stack(reference[2, 1], reference[2, 5], dim=0).unsqueeze(0)) + numpy_testing_assert_equal_helper(reference[:, 2, 1:6:2], Tensor.stack(reference[:, 2, 1], reference[:, 2, 3], reference[:, 2, 5], dim=1)) + + lst = [list(range(i, i+10)) for i in range(0, 100, 10)] + tensor = Tensor(lst) + for _ in range(100): + idx1_start = random.randrange(10) + idx1_end = idx1_start + random.randrange(1, 10 - idx1_start + 1) + idx1_step = random.randrange(1, 8) + idx1 = slice(idx1_start, idx1_end, idx1_step) + if random.randrange(2) == 0: + idx2_start = random.randrange(10) + idx2_end = idx2_start + random.randrange(1, 10 - idx2_start + 1) + idx2_step = random.randrange(1, 8) + idx2 = slice(idx2_start, idx2_end, idx2_step) + lst_indexed = [l[idx2] for l in lst[idx1]] + tensor_indexed = tensor[idx1, idx2] + else: + lst_indexed = lst[idx1] + tensor_indexed = tensor[idx1] + numpy_testing_assert_equal_helper(tensor_indexed, np.array(lst_indexed)) + + self.assertRaises(ValueError, lambda: reference[1:9:0]) + # NOTE torch doesn't support this but numpy does so we should too. Torch raises ValueError + # see test_slice_negative_strides in test_ops.py + # self.assertRaises(ValueError, lambda: reference[1:9:-1]) + + self.assertRaises(IndexError, lambda: reference[1, 1, 1, 1]) + self.assertRaises(IndexError, lambda: reference[1, 1, 1, 1:1]) + self.assertRaises(IndexError, lambda: reference[3, 3, 3, 3, 3, 3, 3, 3]) + + self.assertRaises(IndexError, lambda: reference[0.0]) + self.assertRaises(TypeError, lambda: reference[0.0:2.0]) + self.assertRaises(IndexError, lambda: reference[0.0, 0.0:2.0]) + self.assertRaises(IndexError, lambda: reference[0.0, :, 0.0:2.0]) + self.assertRaises(IndexError, lambda: reference[0.0, ..., 0.0:2.0]) + self.assertRaises(IndexError, lambda: reference[0.0, :, 0.0]) + + # TODO: delitem + # def delitem(): del reference[0] + # self.assertRaises(TypeError, delitem) + + # TODO: LLVM is quite fast, why are other compiled backends slow? + @unittest.skipIf(CI and Device.DEFAULT in ["CPU", "GPU", "METAL", "NV", "AMD"], "slow") + def test_advancedindex(self): + # integer array indexing + + # pick a random valid indexer type + def ri(indices): + choice = random.randint(0, 2) + if choice == 0: return Tensor(indices) + if choice == 1: return list(indices) + return tuple(indices) + + def validate_indexing(x): + numpy_testing_assert_equal_helper(x[[0]], consec((1,))) + numpy_testing_assert_equal_helper(x[ri([0]),], consec((1,))) + numpy_testing_assert_equal_helper(x[ri([3]),], consec((1,), 4)) + numpy_testing_assert_equal_helper(x[[2, 3, 4]], consec((3,), 3)) + numpy_testing_assert_equal_helper(x[ri([2, 3, 4]),], consec((3,), 3)) + numpy_testing_assert_equal_helper(x[ri([0, 2, 4]),], np.array([1, 3, 5])) + + def validate_setting(x): + x[[0]] = -2 + numpy_testing_assert_equal_helper(x[[0]], np.array([-2])) + x[[0]] = -1 + numpy_testing_assert_equal_helper(x[ri([0]), ], np.array([-1])) + x[[2, 3, 4]] = 4 + numpy_testing_assert_equal_helper(x[[2, 3, 4]], np.array([4, 4, 4])) + x[ri([2, 3, 4]), ] = 3 + numpy_testing_assert_equal_helper(x[ri([2, 3, 4]), ], np.array([3, 3, 3])) + x[ri([0, 2, 4]), ] = Tensor([5, 4, 3]) + numpy_testing_assert_equal_helper(x[ri([0, 2, 4]), ], np.array([5, 4, 3])) + + # Case 1: Purely Integer Array Indexing + reference = consec((10,)) + validate_indexing(reference) + # setting values + validate_setting(reference) + + # Tensor with stride != 1 + # strided is [1, 3, 5, 7] + + # # TODO: set stride + # reference = consec((10,)) + # strided = set_(reference, (4,), (2,), 0) + + # numpy_testing_assert_equal_helper(strided[[0]], np.array([1])) + # numpy_testing_assert_equal_helper(strided[ri([0]), ], np.array([1])) + # numpy_testing_assert_equal_helper(strided[ri([3]), ], np.array([7])) + # numpy_testing_assert_equal_helper(strided[[1, 2]], np.array([3, 5])) + # numpy_testing_assert_equal_helper(strided[ri([1, 2]), ], np.array([3, 5])) + # numpy_testing_assert_equal_helper(strided[ri([[2, 1], [0, 3]]), ], + # np.array([[5, 3], [1, 7]])) + + # stride is [4, 8] + + # strided = set_(reference, (2,), (4,), offset=4) + + # numpy_testing_assert_equal_helper(strided[[0]], np.array([5])) + # numpy_testing_assert_equal_helper(strided[ri([0]), ], np.array([5])) + # numpy_testing_assert_equal_helper(strided[ri([1]), ], np.array([9])) + # numpy_testing_assert_equal_helper(strided[[0, 1]], np.array([5, 9])) + # numpy_testing_assert_equal_helper(strided[ri([0, 1]), ], np.array([5, 9])) + # numpy_testing_assert_equal_helper(strided[ri([[0, 1], [1, 0]]), ], + # np.array([[5, 9], [9, 5]])) + + # reference is 1 2 + # 3 4 + # 5 6 + reference = consec((3, 2)) + numpy_testing_assert_equal_helper(reference[ri([0, 1, 2]), ri([0])], np.array([1, 3, 5])) + numpy_testing_assert_equal_helper(reference[ri([0, 1, 2]), ri([1])], np.array([2, 4, 6])) + numpy_testing_assert_equal_helper(reference[ri([0]), ri([0])], consec((1,))) + numpy_testing_assert_equal_helper(reference[ri([2]), ri([1])], consec((1,), 6)) + numpy_testing_assert_equal_helper(reference[[ri([0, 0]), ri([0, 1])]], np.array([1, 2])) + numpy_testing_assert_equal_helper(reference[[ri([0, 1, 1, 0, 2]), ri([1])]], np.array([2, 4, 4, 2, 6])) + numpy_testing_assert_equal_helper(reference[[ri([0, 0, 1, 1]), ri([0, 1, 0, 0])]], np.array([1, 2, 3, 3])) + + rows = ri([[0, 0], + [1, 2]]) + columns = [0], + numpy_testing_assert_equal_helper(reference[rows, columns], np.array([[1, 1], + [3, 5]])) + + rows = ri([[0, 0], + [1, 2]]) + columns = ri([1, 0]) + numpy_testing_assert_equal_helper(reference[rows, columns], np.array([[2, 1], + [4, 5]])) + rows = ri([[0, 0], + [1, 2]]) + columns = ri([[0, 1], + [1, 0]]) + numpy_testing_assert_equal_helper(reference[rows, columns], np.array([[1, 2], + [4, 5]])) + + # setting values + reference[ri([0]), ri([1])] = -1 + numpy_testing_assert_equal_helper(reference[ri([0]), ri([1])], np.array([-1])) + reference[ri([0, 1, 2]), ri([0])] = Tensor([-1, 2, -4]) + numpy_testing_assert_equal_helper(reference[ri([0, 1, 2]), ri([0])], + np.array([-1, 2, -4])) + reference[rows, columns] = Tensor([[4, 6], [2, 3]]) + numpy_testing_assert_equal_helper(reference[rows, columns], + np.array([[4, 6], [2, 3]])) + + # Verify still works with Transposed (i.e. non-contiguous) Tensors + reference = Tensor([[0, 1, 2, 3], + [4, 5, 6, 7], + [8, 9, 10, 11]]).T + + # Transposed: [[0, 4, 8], + # [1, 5, 9], + # [2, 6, 10], + # [3, 7, 11]] + + numpy_testing_assert_equal_helper(reference[ri([0, 1, 2]), ri([0])], np.array([0, 1, 2])) + numpy_testing_assert_equal_helper(reference[ri([0, 1, 2]), ri([1])], np.array([4, 5, 6])) + numpy_testing_assert_equal_helper(reference[ri([0]), ri([0])], np.array([0])) + numpy_testing_assert_equal_helper(reference[ri([2]), ri([1])], np.array([6])) + numpy_testing_assert_equal_helper(reference[[ri([0, 0]), ri([0, 1])]], np.array([0, 4])) + numpy_testing_assert_equal_helper(reference[[ri([0, 1, 1, 0, 3]), ri([1])]], np.array([4, 5, 5, 4, 7])) + numpy_testing_assert_equal_helper(reference[[ri([0, 0, 1, 1]), ri([0, 1, 0, 0])]], np.array([0, 4, 1, 1])) + + rows = ri([[0, 0], + [1, 2]]) + columns = [0], + numpy_testing_assert_equal_helper(reference[rows, columns], np.array([[0, 0], [1, 2]])) + + rows = ri([[0, 0], + [1, 2]]) + columns = ri([1, 0]) + numpy_testing_assert_equal_helper(reference[rows, columns], np.array([[4, 0], [5, 2]])) + rows = ri([[0, 0], + [1, 3]]) + columns = ri([[0, 1], + [1, 2]]) + numpy_testing_assert_equal_helper(reference[rows, columns], np.array([[0, 4], [5, 11]])) + + # TODO: non contiguous setitem + ''' + # setting values + reference[ri([0]), ri([1])] = -1 + numpy_testing_assert_equal_helper(reference[ri([0]), ri([1])], + np.array([-1])) + reference[ri([0, 1, 2]), ri([0])] = np.array([-1, 2, -4]) + numpy_testing_assert_equal_helper(reference[ri([0, 1, 2]), ri([0])], + np.array([-1, 2, -4])) + reference[rows, columns] = np.array([[4, 6], [2, 3]]) + numpy_testing_assert_equal_helper(reference[rows, columns], + np.array([[4, 6], [2, 3]])) + ''' + + # stride != 1 + + # strided is [[1 3 5 7], + # [9 11 13 15]] + + # # TODO: set stride + # reference = Tensor.arange(0., 24).reshape(3, 8) + # strided = set_(reference, (2,4), (8,2), 1) + + # numpy_testing_assert_equal_helper(strided[ri([0, 1]), ri([0])], np.array([1, 9])) + # numpy_testing_assert_equal_helper(strided[ri([0, 1]), ri([1])], np.array([3, 11])) + # numpy_testing_assert_equal_helper(strided[ri([0]), ri([0])], np.array([1])) + # numpy_testing_assert_equal_helper(strided[ri([1]), ri([3])], np.array([15])) + # numpy_testing_assert_equal_helper(strided[[ri([0, 0]), ri([0, 3])]], np.array([1, 7])) + # numpy_testing_assert_equal_helper(strided[[ri([1]), ri([0, 1, 1, 0, 3])]], np.array([9, 11, 11, 9, 15])) + # numpy_testing_assert_equal_helper(strided[[ri([0, 0, 1, 1]), ri([0, 1, 0, 0])]], np.array([1, 3, 9, 9])) + + # rows = ri([[0, 0], + # [1, 1]]) + # columns = [0], + # numpy_testing_assert_equal_helper(strided[rows, columns], np.array([[1, 1], [9, 9]])) + + # rows = ri([[0, 1], + # [1, 0]]) + # columns = ri([1, 2]) + # numpy_testing_assert_equal_helper(strided[rows, columns], np.array([[3, 13], [11, 5]])) + # rows = ri([[0, 0], + # [1, 1]]) + # columns = ri([[0, 1], + # [1, 2]]) + # numpy_testing_assert_equal_helper(strided[rows, columns], np.array([[1, 3], [11, 13]])) + + # setting values + + # strided is [[10, 11], + # [17, 18]] + + # # TODO: set stride + # reference = Tensor.arange(0., 24).reshape(3, 8) + # strided = set_(reference, (2,2), (7,1), 10) + + # numpy_testing_assert_equal_helper(strided[ri([0]), ri([1])], np.array([11])) + + # TODO non contiguous setitem + ''' + strided[ri([0]), ri([1])] = -1 + numpy_testing_assert_equal_helper(strided[ri([0]), ri([1])], + Tensor([-1])) + ''' + # # TODO: set stride + # reference = Tensor.arange(0., 24).reshape(3, 8) + # strided = set_(reference, (2,2), (7,1), 10) + + # numpy_testing_assert_equal_helper(strided[ri([0, 1]), ri([1, 0])], np.array([11, 17])) + + # TODO non contiguous setitem + ''' + strided[ri([0, 1]), ri([1, 0])] = Tensor([-1, 2]) + numpy_testing_assert_equal_helper(strided[ri([0, 1]), ri([1, 0])], + Tensor([-1, 2])) + ''' + + # # TODO: set stride + # reference = Tensor.arange(0., 24).realize().reshape(3, 8) + # strided = set_(reference, (2,2), (7,1), 10) + + # rows = ri([[0], + # [1]]) + # columns = ri([[0, 1], + # [0, 1]]) + # numpy_testing_assert_equal_helper(strided[rows, columns], np.array([[10, 11], [17, 18]])) + + # TODO non contiguous setitem + ''' + strided[rows, columns] = Tensor([[4, 6], [2, 3]]) + numpy_testing_assert_equal_helper(strided[rows, columns], + Tensor([[4, 6], [2, 3]])) + ''' + + # Tests using less than the number of dims, and ellipsis + + # reference is 1 2 + # 3 4 + # 5 6 + reference = consec((3, 2)) + numpy_testing_assert_equal_helper(reference[ri([0, 2]),], np.array([[1, 2], [5, 6]])) + numpy_testing_assert_equal_helper(reference[ri([1]), ...], np.array([[3, 4]])) + numpy_testing_assert_equal_helper(reference[..., ri([1])], np.array([[2], [4], [6]])) + + # verify too many indices fails + with self.assertRaises(IndexError): reference[ri([1]), ri([0, 2]), ri([3])] + + # test invalid index fails + reference = Tensor.empty(10) + for err_idx in (10, -11): + with self.assertRaises(IndexError): + reference[err_idx] + # NOTE cannot check for out of bounds with Tensor indexing + # see tensor.py: __getitem__ (Tiny Things) + ''' + with self.assertRaises(IndexError): + reference[Tensor([err_idx], dtype=dtypes.int64)] + with self.assertRaises(IndexError): + reference[[err_idx]] + ''' + + def tensor_indices_to_np(tensor: Tensor, indices): + npt = tensor.numpy() + idxs = tuple(i.numpy().tolist() if isinstance(i, Tensor) and i.dtype == dtypes.int64 else + i for i in indices) + return npt, idxs + + def get_numpy(tensor, indices): + npt, idxs = tensor_indices_to_np(tensor, indices) + return Tensor(npt[idxs]) + + def set_numpy(tensor:Tensor, indices, value): + if not isinstance(value, int): + value = value.numpy() + npt, idxs = tensor_indices_to_np(tensor, indices) + npt[idxs] = value + return npt + + def assert_get_eq(tensor, indexer): + numpy_testing_assert_equal_helper(tensor[indexer], get_numpy(tensor, indexer)) + + def assert_set_eq(tensor: Tensor, indexer, val): + pyt = clone(tensor) + numt = clone(tensor) + pyt[indexer] = val + numt = set_numpy(numt, indexer, val) + numpy_testing_assert_equal_helper(pyt, numt) + + # NOTE: torch initiates the gradients using g0cpu (rand as gradients) + def assert_backward_eq(tensor: Tensor, indexer): + cpu = clone(tensor.float()) + cpu.requires_grad = True + outcpu = cpu[indexer].sum() + outcpu.backward() + dev = cpu.detach() + dev.requires_grad = True + outdev = dev[indexer].sum() + outdev.backward() + numpy_testing_assert_equal_helper(cpu.grad, dev.grad) + + def get_set_tensor(indexed: Tensor, indexer): + set_size = indexed[indexer].shape + set_count = indexed[indexer].numel() + set_tensor = Tensor.randint(set_count, high=set_count).reshape(set_size) #.cast(dtypes.float64) + return set_tensor + + # Tensor is 0 1 2 3 4 + # 5 6 7 8 9 + # 10 11 12 13 14 + # 15 16 17 18 19 + reference = Tensor.arange(0., 20).reshape(4, 5) + + indices_to_test = [ + # grab the second, fourth columns + [slice(None), [1, 3]], + + # first, third rows, + [[0, 2], slice(None)], + + # weird shape + [slice(None), [[0, 1], + [2, 3]]], + # negatives + [[-1], [0]], + [[0, 2], [-1]], + [slice(None), [-1]], + ] + + # only test dupes on gets + get_indices_to_test = indices_to_test + [[slice(None), [0, 1, 1, 2, 2]]] + + for indexer in get_indices_to_test: + assert_get_eq(reference, indexer) + assert_backward_eq(reference, indexer) + + for indexer in indices_to_test: + assert_set_eq(reference, indexer, 44) + assert_set_eq(reference, indexer, get_set_tensor(reference, indexer)) + + reference = Tensor.arange(0., 160).reshape(4, 8, 5) + + indices_to_test = [ + [slice(None), slice(None), [0, 3, 4]], + [slice(None), [2, 4, 5, 7], slice(None)], + [[2, 3], slice(None), slice(None)], + [slice(None), [0, 2, 3], [1, 3, 4]], + [slice(None), [0], [1, 2, 4]], + [slice(None), [0, 1, 3], [4]], + [slice(None), [[0, 1], [1, 0]], [[2, 3]]], + [slice(None), [[0, 1], [2, 3]], [[0]]], + [slice(None), [[5, 6]], [[0, 3], [4, 4]]], + [[0, 2, 3], [1, 3, 4], slice(None)], + [[0], [1, 2, 4], slice(None)], + [[0, 1, 3], [4], slice(None)], + [[[0, 1], [1, 0]], [[2, 1], [3, 5]], slice(None)], + [[[0, 1], [1, 0]], [[2, 3]], slice(None)], + [[[0, 1], [2, 3]], [[0]], slice(None)], + [[[2, 1]], [[0, 3], [4, 4]], slice(None)], + [[[2]], [[0, 3], [4, 1]], slice(None)], + # non-contiguous indexing subspace + [[0, 2, 3], slice(None), [1, 3, 4]], + + # less dim, ellipsis + [[0, 2], ], + [[0, 2], slice(None)], + [[0, 2], Ellipsis], + [[0, 2], slice(None), Ellipsis], + [[0, 2], Ellipsis, slice(None)], + [[0, 2], [1, 3]], + [[0, 2], [1, 3], Ellipsis], + [Ellipsis, [1, 3], [2, 3]], + [Ellipsis, [2, 3, 4]], + [Ellipsis, slice(None), [2, 3, 4]], + [slice(None), Ellipsis, [2, 3, 4]], + + # ellipsis counts for nothing + [Ellipsis, slice(None), slice(None), [0, 3, 4]], + [slice(None), Ellipsis, slice(None), [0, 3, 4]], + [slice(None), slice(None), Ellipsis, [0, 3, 4]], + [slice(None), slice(None), [0, 3, 4], Ellipsis], + [Ellipsis, [[0, 1], [1, 0]], [[2, 1], [3, 5]], slice(None)], + [[[0, 1], [1, 0]], [[2, 1], [3, 5]], Ellipsis, slice(None)], + [[[0, 1], [1, 0]], [[2, 1], [3, 5]], slice(None), Ellipsis], + ] + + for indexer in indices_to_test: + assert_get_eq(reference, indexer) + + assert_set_eq(reference, indexer, 212) + assert_set_eq(reference, indexer, get_set_tensor(reference, indexer)) + assert_backward_eq(reference, indexer) + + reference = Tensor.arange(0., 1296).reshape(3, 9, 8, 6) + + indices_to_test = [ + [slice(None), slice(None), slice(None), [0, 3, 4]], + [slice(None), slice(None), [2, 4, 5, 7], slice(None)], + [slice(None), [2, 3], slice(None), slice(None)], + [[1, 2], slice(None), slice(None), slice(None)], + [slice(None), slice(None), [0, 2, 3], [1, 3, 4]], + [slice(None), slice(None), [0], [1, 2, 4]], + [slice(None), slice(None), [0, 1, 3], [4]], + [slice(None), slice(None), [[0, 1], [1, 0]], [[2, 3]]], + [slice(None), slice(None), [[0, 1], [2, 3]], [[0]]], + [slice(None), slice(None), [[5, 6]], [[0, 3], [4, 4]]], + [slice(None), [0, 2, 3], [1, 3, 4], slice(None)], + [slice(None), [0], [1, 2, 4], slice(None)], + [slice(None), [0, 1, 3], [4], slice(None)], + [slice(None), [[0, 1], [3, 4]], [[2, 3], [0, 1]], slice(None)], + [slice(None), [[0, 1], [3, 4]], [[2, 3]], slice(None)], + [slice(None), [[0, 1], [3, 2]], [[0]], slice(None)], + [slice(None), [[2, 1]], [[0, 3], [6, 4]], slice(None)], + [slice(None), [[2]], [[0, 3], [4, 2]], slice(None)], + [[0, 1, 2], [1, 3, 4], slice(None), slice(None)], + [[0], [1, 2, 4], slice(None), slice(None)], + [[0, 1, 2], [4], slice(None), slice(None)], + [[[0, 1], [0, 2]], [[2, 4], [1, 5]], slice(None), slice(None)], + [[[0, 1], [1, 2]], [[2, 0]], slice(None), slice(None)], + [[[2, 2]], [[0, 3], [4, 5]], slice(None), slice(None)], + [[[2]], [[0, 3], [4, 5]], slice(None), slice(None)], + [slice(None), [3, 4, 6], [0, 2, 3], [1, 3, 4]], + [slice(None), [2, 3, 4], [1, 3, 4], [4]], + [slice(None), [0, 1, 3], [4], [1, 3, 4]], + [slice(None), [6], [0, 2, 3], [1, 3, 4]], + [slice(None), [2, 3, 5], [3], [4]], + [slice(None), [0], [4], [1, 3, 4]], + [slice(None), [6], [0, 2, 3], [1]], + [slice(None), [[0, 3], [3, 6]], [[0, 1], [1, 3]], [[5, 3], [1, 2]]], + [[2, 2, 1], [0, 2, 3], [1, 3, 4], slice(None)], + [[2, 0, 1], [1, 2, 3], [4], slice(None)], + [[0, 1, 2], [4], [1, 3, 4], slice(None)], + [[0], [0, 2, 3], [1, 3, 4], slice(None)], + [[0, 2, 1], [3], [4], slice(None)], + [[0], [4], [1, 3, 4], slice(None)], + [[1], [0, 2, 3], [1], slice(None)], + [[[1, 2], [1, 2]], [[0, 1], [2, 3]], [[2, 3], [3, 5]], slice(None)], + + # less dim, ellipsis + [Ellipsis, [0, 3, 4]], + [Ellipsis, slice(None), [0, 3, 4]], + [Ellipsis, slice(None), slice(None), [0, 3, 4]], + [slice(None), Ellipsis, [0, 3, 4]], + [slice(None), slice(None), Ellipsis, [0, 3, 4]], + [slice(None), [0, 2, 3], [1, 3, 4]], + [slice(None), [0, 2, 3], [1, 3, 4], Ellipsis], + [Ellipsis, [0, 2, 3], [1, 3, 4], slice(None)], + [[0], [1, 2, 4]], + [[0], [1, 2, 4], slice(None)], + [[0], [1, 2, 4], Ellipsis], + [[0], [1, 2, 4], Ellipsis, slice(None)], + [[1], ], + [[0, 2, 1], [3], [4]], + [[0, 2, 1], [3], [4], slice(None)], + [[0, 2, 1], [3], [4], Ellipsis], + [Ellipsis, [0, 2, 1], [3], [4]], + ] + + for indexer in indices_to_test: + assert_get_eq(reference, indexer) + assert_set_eq(reference, indexer, 1333) + assert_set_eq(reference, indexer, get_set_tensor(reference, indexer)) + + indices_to_test += [ + [slice(None), slice(None), [[0, 1], [1, 0]], [[2, 3], [3, 0]]], + [slice(None), slice(None), [[2]], [[0, 3], [4, 4]]], + ] + for indexer in indices_to_test: + assert_get_eq(reference, indexer) + assert_set_eq(reference, indexer, 1333) + assert_backward_eq(reference, indexer) + + # TODO setitem backward + ''' + def test_set_item_to_scalar_tensor(self): + m = random.randint(1, 10) + n = random.randint(1, 10) + z = Tensor.randn([m, n]) + a = 1.0 + w = Tensor(a, requires_grad=True) + z[:, 0] = w + z.sum().backward() + numpy_testing_assert_equal_helper(w.grad, m * a) + ''' + + def test_single_int(self): + v = Tensor.randn(5, 7, 3) + numpy_testing_assert_equal_helper(v[4].shape, (7, 3)) + + def test_multiple_int(self): + v = Tensor.randn(5, 7, 3) + numpy_testing_assert_equal_helper(v[4].shape, (7, 3)) + numpy_testing_assert_equal_helper(v[4, :, 1].shape, (7,)) + + def test_none(self): + v = Tensor.randn(5, 7, 3) + numpy_testing_assert_equal_helper(v[None].shape, (1, 5, 7, 3)) + numpy_testing_assert_equal_helper(v[:, None].shape, (5, 1, 7, 3)) + numpy_testing_assert_equal_helper(v[:, None, None].shape, (5, 1, 1, 7, 3)) + numpy_testing_assert_equal_helper(v[..., None].shape, (5, 7, 3, 1)) + + def test_step(self): + v = Tensor.arange(10) + numpy_testing_assert_equal_helper(v[::1], v) + numpy_testing_assert_equal_helper(v[::2], [0, 2, 4, 6, 8]) + numpy_testing_assert_equal_helper(v[::3], [0, 3, 6, 9]) + numpy_testing_assert_equal_helper(v[::11], [0]) + numpy_testing_assert_equal_helper(v[1:6:2], [1, 3, 5]) + + def test_step_assignment(self): + v = Tensor.zeros(4, 4).contiguous() + v[0, 1::2] = Tensor([3., 4.]) + numpy_testing_assert_equal_helper(v[0].numpy().tolist(), [0, 3, 0, 4]) + numpy_testing_assert_equal_helper(v[1:].sum(), 0) + + @unittest.skip("bool indexing not supported") + def test_bool_indices(self): + v = Tensor.randn(5, 7, 3) + boolIndices = Tensor([True, False, True, True, False], dtype=dtypes.bool) + numpy_testing_assert_equal_helper(v[boolIndices].shape, (3, 7, 3)) + numpy_testing_assert_equal_helper(v[boolIndices], Tensor.stack([v[0], v[2], v[3]])) + + v = Tensor([True, False, True], dtype=dtypes.bool) + boolIndices = Tensor([True, False, False], dtype=dtypes.bool) + uint8Indices = Tensor([1, 0, 0], dtype=dtypes.uint8) + with warnings.catch_warnings(record=True) as w: + numpy_testing_assert_equal_helper(v[boolIndices].shape, v[uint8Indices].shape) + numpy_testing_assert_equal_helper(v[boolIndices], v[uint8Indices]) + numpy_testing_assert_equal_helper(v[boolIndices], Tensor([True])) + numpy_testing_assert_equal_helper(len(w), 2) + + @unittest.skip("bool indexing not supported") + def test_bool_indices_accumulate(self): + mask = Tensor.zeros(size=(10, ), dtype=dtypes.bool) + y = Tensor.ones(size=(10, 10)) + index_put_(y, (mask, ), y[mask], accumulate=True) + numpy_testing_assert_equal_helper(y, Tensor.ones(size=(10, 10))) + + @unittest.skip("bool indexing not supported") + def test_multiple_bool_indices(self): + v = Tensor.randn(5, 7, 3) + # note: these broadcast together and are transposed to the first dim + mask1 = Tensor([1, 0, 1, 1, 0], dtype=dtypes.bool) + mask2 = Tensor([1, 1, 1], dtype=dtypes.bool) + numpy_testing_assert_equal_helper(v[mask1, :, mask2].shape, (3, 7)) + + @unittest.skip("bool indexing not supported") + def test_byte_mask(self): + v = Tensor.randn(5, 7, 3) + mask = Tensor([1, 0, 1, 1, 0], dtype=dtypes.uint8) + with warnings.catch_warnings(record=True) as w: + numpy_testing_assert_equal_helper(v[mask].shape, (3, 7, 3)) + numpy_testing_assert_equal_helper(v[mask], Tensor.stack([v[0], v[2], v[3]])) + numpy_testing_assert_equal_helper(len(w), 2) + + v = Tensor([1.]) + numpy_testing_assert_equal_helper(v[v == 0], Tensor([])) + + @unittest.skip("bool indexing not supported") + def test_byte_mask_accumulate(self): + mask = Tensor.zeros(size=(10, ), dtype=dtypes.uint8) + y = Tensor.ones(size=(10, 10)) + with warnings.catch_warnings(record=True) as w: + warnings.simplefilter("always") + index_put_(y, (mask, ), y[mask], accumulate=True) + numpy_testing_assert_equal_helper(y, Tensor.ones(size=(10, 10))) + numpy_testing_assert_equal_helper(len(w), 2) + + # TODO setitem + # NOTE: tinygrad doesn't support idx.max that big + ''' + def test_index_put_accumulate_large_tensor(self): + # This test is for tensors with number of elements >= INT_MAX (2^31 - 1). + N = (1 << 31) + 5 + dt = dtypes.int8 + a = Tensor.ones(N, dtype=dt).contiguous() + indices = Tensor([-2, 0, -2, -1, 0, -1, 1], dtype=dtypes.int64) + values = Tensor([6, 5, 6, 6, 5, 7, 11], dtype=dt) + + index_put_(a, (indices, ), values, accumulate=True) + + numpy_testing_assert_equal_helper(a[0], 11) + numpy_testing_assert_equal_helper(a[1], 12) + numpy_testing_assert_equal_helper(a[2], 1) + numpy_testing_assert_equal_helper(a[-3], 1) + numpy_testing_assert_equal_helper(a[-2], 13) + numpy_testing_assert_equal_helper(a[-1], 14) + + a = Tensor.ones((2, N), dtype=dt).contiguous() + indices0 = np.array([0, -1, 0, 1], dtype=dtypes.int64) + indices1 = np.array([-2, -1, 0, 1], dtype=dtypes.int64) + values = np.array([12, 13, 10, 11], dtype=dt) + + index_put_(a, (indices0, indices1), values, accumulate=True) + + numpy_testing_assert_equal_helper(a[0, 0], 11) + numpy_testing_assert_equal_helper(a[0, 1], 1) + numpy_testing_assert_equal_helper(a[1, 0], 1) + numpy_testing_assert_equal_helper(a[1, 1], 12) + numpy_testing_assert_equal_helper(a[:, 2], Tensor.ones(2, dtype=dtypes.int8)) + numpy_testing_assert_equal_helper(a[:, -3], Tensor.ones(2, dtype=dtypes.int8)) + numpy_testing_assert_equal_helper(a[0, -2], 13) + numpy_testing_assert_equal_helper(a[1, -2], 1) + numpy_testing_assert_equal_helper(a[-1, -1], 14) + numpy_testing_assert_equal_helper(a[0, -1], 1) + ''' + + # TODO fancy setitem + ''' + def test_index_put_accumulate_duplicate_indices(self): + for i in range(1, 512): + # generate indices by random walk, this will create indices with + # lots of duplicates interleaved with each other + delta = Tensor.uniform(low=-1, high=1, dtype=dtypes.double) + indices = delta.cumsum(0).cast(dtypes.int64) + + # input = torch.randn(indices.abs().max() + 1) + input = Tensor.randn(indices.abs().max().item() + 1) + # values = torch.randn(indices.size(0)) + values = Tensor.randn(indices.shape(0)) + output = index_put_(input, (indices,), values, accumulate=True) + + input_list = input.numpy().tolist() + indices_list = indices.numpy().tolist() + values_list = values.numpy().tolist() + for i, v in zip(indices_list, values_list): + input_list[i] += v + + numpy_testing_assert_equal_helper(output, input_list) + ''' + + @unittest.skipUnless(is_dtype_supported(dtypes.long), f"long dtype not supported on {Device.DEFAULT}") + def test_index_ind_dtype(self): + x = Tensor.randn(4, 4) + # ind_long = torch.randint(4, (4,), dtype=torch.long) + # TODO should we spend an extra line to allow for randint other dtypes? + # copied from randint + ind_long = (Tensor.rand((4,),)*(4-0)+0).cast(dtypes.int64) + # ind_int = ind_long.int() + ind_int = (ind_long).cast(dtypes.int32) + ref = x[ind_long, ind_long] + res = x[ind_int, ind_int] + numpy_testing_assert_equal_helper(ref, res) + ref = x[ind_long, :] + res = x[ind_int, :] + numpy_testing_assert_equal_helper(ref, res) + ref = x[:, ind_long] + res = x[:, ind_int] + numpy_testing_assert_equal_helper(ref, res) + # no repeating indices for index_put + # TODO fancy setitem + ''' + src = Tensor.randn(4) + ind_long = Tensor.arange(4, dtype=dtypes.int64) + ind_int = ind_long.cast(dtypes.int32) + for accum in (True, False): + inp_ref = clone(x) + inp_res = clone(x) + index_put_(inp_ref, (ind_long, ind_long), src, accum) + index_put_(inp_res, (ind_int, ind_int), src, accum) + numpy_testing_assert_equal_helper(inp_ref, inp_res) + ''' + + # TODO empty setitem + ''' + def test_index_put_accumulate_empty(self): + # Regression test for https://github.com/pytorch/pytorch/issues/94667 + input = Tensor.rand([], dtype=dtypes.float32) + with self.assertRaises(RuntimeError): + index_put_(input, [], np.array([1.0]), True) + ''' + + @unittest.skip("bool indexing not supported") + def test_multiple_byte_mask(self): + v = Tensor.randn(5, 7, 3) + # note: these broadcast together and are transposed to the first dim + mask1 = Tensor([1, 0, 1, 1, 0], dtype=dtypes.uint8) + mask2 = Tensor([1, 1, 1], dtype=dtypes.uint8) + with warnings.catch_warnings(record=True) as w: + warnings.simplefilter("always") + numpy_testing_assert_equal_helper(v[mask1, :, mask2].shape, (3, 7)) + numpy_testing_assert_equal_helper(len(w), 2) + + @unittest.skip("bool indexing not supported") + def test_byte_mask2d(self): + v = Tensor.randn(5, 7, 3) + c = Tensor.randn(5, 7) + num_ones = (c > 0).sum() + r = v[c > 0] + numpy_testing_assert_equal_helper(r.shape, (num_ones, 3)) + + @unittest.skip("bool indexing not supported") + def test_jit_indexing(self): + def fn1(x): + x[x < 50] = 1.0 + return x + + def fn2(x): + x[0:50] = 1.0 + return x + + scripted_fn1 = TinyJit(fn1) + scripted_fn2 = TinyJit(fn2) + data = Tensor.arange(100, dtype=dtypes.float) + out = scripted_fn1(clone(data)) + ref = Tensor(np.concatenate((np.ones(50), np.arange(50, 100))), dtype=dtypes.float) + numpy_testing_assert_equal_helper(out, ref) + out = scripted_fn2(clone(data)) + numpy_testing_assert_equal_helper(out, ref) + + def test_int_indices(self): + v = Tensor.randn(5, 7, 3) + numpy_testing_assert_equal_helper(v[[0, 4, 2]].shape, (3, 7, 3)) + numpy_testing_assert_equal_helper(v[:, [0, 4, 2]].shape, (5, 3, 3)) + numpy_testing_assert_equal_helper(v[:, [[0, 1], [4, 3]]].shape, (5, 2, 2, 3)) + + # TODO fancy setitem + ''' + def test_index_put_src_datatype(self, dtype): + src = Tensor.ones(3, 2, 4, dtype=dtype) + vals = Tensor.ones(3, 2, 4, dtype=dtype) + indices = (np.array([0, 2, 1]),) + res = index_put_(src, indices, vals, accumulate=True) + numpy_testing_assert_equal_helper(res.shape, src.shape) + ''' + + def test_index_src_datatype(self): + src = Tensor.ones(3, 2, 4) + # test index + res = src[[0, 2, 1], :, :] + numpy_testing_assert_equal_helper(res.shape, src.shape) + # test index_put, no accum + # TODO fancy setitem + ''' + src[[0, 2, 1], :, :] = res + numpy_testing_assert_equal_helper(res.shape, src.shape) + ''' + + def test_int_indices2d(self): + # From the NumPy indexing example + x = Tensor.arange(0, 12).reshape(4, 3) + rows = Tensor([[0, 0], [3, 3]]) + columns = Tensor([[0, 2], [0, 2]]) + numpy_testing_assert_equal_helper(x[rows, columns].numpy().tolist(), [[0, 2], [9, 11]]) + + def test_int_indices_broadcast(self): + # From the NumPy indexing example + x = Tensor.arange(0, 12).reshape(4, 3) + rows = Tensor([0, 3]) + columns = Tensor([0, 2]) + result = x[rows[:, None], columns] + numpy_testing_assert_equal_helper(result.numpy().tolist(), [[0, 2], [9, 11]]) + + # TODO jax supports empty tensor indexing + @unittest.skip("empty tensor indexing not supported") + def test_empty_index(self): + x = Tensor.arange(0, 12).reshape(4, 3) + idx = Tensor([], dtype=dtypes.int64) + numpy_testing_assert_equal_helper(x[idx].numel(), 0) + + # TODO empty setitem + ''' + # empty assignment should have no effect but not throw an exception + y = clone(x) + y[idx] = -1 + numpy_testing_assert_equal_helper(x, y) + + mask = Tensor.zeros(4, 3).cast(dtypes.bool) + y[mask] = -1 + numpy_testing_assert_equal_helper(x, y) + ''' + + # TODO jax supports empty tensor indexing + @unittest.skip("empty tensor indexing not supported") + def test_empty_ndim_index(self): + x = Tensor.randn(5) + numpy_testing_assert_equal_helper(Tensor.empty(0, 2), x[Tensor.empty(0, 2, dtype=dtypes.int64)]) + + x = Tensor.randn(2, 3, 4, 5) + numpy_testing_assert_equal_helper(Tensor.empty(2, 0, 6, 4, 5), + x[:, Tensor.empty(0, 6, dtype=dtypes.int64)]) + + x = Tensor.empty(10, 0) + numpy_testing_assert_equal_helper(x[[1, 2]].shape, (2, 0)) + numpy_testing_assert_equal_helper(x[[], []].shape, (0,)) + with self.assertRaises(IndexError): + x[:, [0, 1]] + + def test_empty_slice(self): + x = Tensor.randn(2, 3, 4, 5) + y = x[:, :, :, 1] + z = y[:, 1:1, :] + numpy_testing_assert_equal_helper((2, 0, 4), z.shape) + # this isn't technically necessary, but matches NumPy stride calculations. + # NOTE: this is empty and shouldn't have strides + #numpy_testing_assert_equal_helper((60, 20, 5), z.uop.st.real_strides()) + # NOTE tinygrad's int slicing implementation makes this not contiguous + # self.assertTrue(z.uop.st.contiguous) + + @unittest.skip("bool indexing not supported") + def test_index_getitem_copy_bools_slices(self): + true = Tensor(1, dtype=dtypes.uint8) + false = Tensor(0, dtype=dtypes.uint8) + + tensors = [Tensor.randn(2, 3), Tensor(3.)] + + for a in tensors: + self.assertNotEqual(data_ptr(a), data_ptr(a[True])) + numpy_testing_assert_equal_helper(Tensor.empty(0, *a.shape), a[False]) + self.assertNotEqual(data_ptr(a), data_ptr(a[true])) + numpy_testing_assert_equal_helper(Tensor.empty(0, *a.shape), a[false]) + self.assertEqual(data_ptr(a), data_ptr(a[None])) + self.assertEqual(data_ptr(a), data_ptr(a[...])) + + @unittest.skip("bool indexing not supported") + def test_index_setitem_bools_slices(self): + true = Tensor(1, dtype=dtypes.uint8) + false = Tensor(0, dtype=dtypes.uint8) + + tensors = [Tensor.randn(2, 3), Tensor(3)] + + for a in tensors: + # prefix with a 1,1, to ensure we are compatible with numpy which cuts off prefix 1s + # (some of these ops already prefix a 1 to the size) + neg_ones = Tensor.ones_like(a) * -1 + neg_ones_expanded = neg_ones.unsqueeze(0).unsqueeze(0) + a[True] = neg_ones_expanded + numpy_testing_assert_equal_helper(a, neg_ones) + a[False] = 5 + numpy_testing_assert_equal_helper(a, neg_ones) + a[true] = neg_ones_expanded * 2 + numpy_testing_assert_equal_helper(a, neg_ones * 2) + a[false] = 5 + numpy_testing_assert_equal_helper(a, neg_ones * 2) + a[None] = neg_ones_expanded * 3 + numpy_testing_assert_equal_helper(a, neg_ones * 3) + a[...] = neg_ones_expanded * 4 + numpy_testing_assert_equal_helper(a, neg_ones * 4) + if a.dim() == 0: + with self.assertRaises(IndexError): + a[:] = neg_ones_expanded * 5 + + @unittest.skip("bool indexing not supported") + def test_index_scalar_with_bool_mask(self): + a = Tensor(1) + uintMask = Tensor(True, dtype=dtypes.uint8) + boolMask = Tensor(True, dtype=dtypes.bool) + numpy_testing_assert_equal_helper(a[uintMask], a[boolMask]) + numpy_testing_assert_equal_helper(a[uintMask].dtype, a[boolMask].dtype) + + a = Tensor(True, dtype=dtypes.bool) + numpy_testing_assert_equal_helper(a[uintMask], a[boolMask]) + numpy_testing_assert_equal_helper(a[uintMask].dtype, a[boolMask].dtype) + + @unittest.skip("bool indexing not supported") + def test_setitem_expansion_error(self): + true = Tensor(True) + a = Tensor.randn(2, 3) + # check prefix with non-1s doesn't work + # a_expanded = a.expand(torch.Size([5, 1]) + a.size()) + a_expanded = a.expand((5, 1) + a.shape) + # NumPy: ValueError + with self.assertRaises(RuntimeError): + a[True] = a_expanded + with self.assertRaises(RuntimeError): + a[true] = a_expanded + + def test_getitem_scalars_simple(self): + src = Tensor([[[1.,2.],[3.,4.]], [[1,1],[1,1]]]) + a = src[0].mul(src[1]) + self.assertEqual(a[0,1].item(), 2) + + @unittest.skipUnless(is_dtype_supported(dtypes.int64), "need dtypes.int64") + def test_getitem_scalars(self): + zero = Tensor(0, dtype=dtypes.int64) + one = Tensor(1, dtype=dtypes.int64) + + # non-scalar indexed with scalars + a = Tensor.randn(2, 3).realize() + numpy_testing_assert_equal_helper(a[0], a[zero]) + numpy_testing_assert_equal_helper(a[0][1], a[zero][one]) + numpy_testing_assert_equal_helper(a[0, 1], a[zero, one]) + numpy_testing_assert_equal_helper(a[0, one], a[zero, 1]) + + # indexing by a scalar should slice (not copy) + numpy_testing_assert_equal_helper(a[0, 1], a[zero, one]) + numpy_testing_assert_equal_helper(a[1], a[one.cast(dtypes.int32)]) + numpy_testing_assert_equal_helper(a[1], a[one.cast(dtypes.int16)]) + + # scalar indexed with scalar + r = Tensor.randn().realize() + with self.assertRaises(IndexError): + r[:] + with self.assertRaises(IndexError): + r[zero] + numpy_testing_assert_equal_helper(r, r[...]) + + # TODO fancy setitem + ''' + def test_setitem_scalars(self): + zero = Tensor(0, dtype=dtypes.int64) + + # non-scalar indexed with scalars + a = Tensor.randn(2, 3).contiguous() + a_set_with_number = clone(a).contiguous() + a_set_with_scalar = clone(a).contiguous() + b = Tensor.randn(3) + + a_set_with_number[0] = b + a_set_with_scalar[zero] = b + numpy_testing_assert_equal_helper(a_set_with_number, a_set_with_scalar) + a[1, zero] = 7.7 + # TODO: weird inaccuracy Max relative difference: 2.47707621e-08 + # numpy_testing_assert_equal_helper(7.7, a[1, 0]) + np.testing.assert_allclose(7.7, a[1, 0].numpy(), rtol=1e-7) + + # scalar indexed with scalars + r = Tensor.randn().contiguous() + with self.assertRaises(IndexError): + r[:] = 8.8 + with self.assertRaises(IndexError): + r[zero] = 8.8 + r[...] = 9.9 + # TODO: weird inaccuracy Max relative difference: 3.85322971e-08 + # numpy_testing_assert_equal_helper(9.9, r) + np.testing.assert_allclose(9.9, r, rtol=1e-7) + ''' + + @unittest.skip("getitem expects elementwise ops folding to be instant, but it happens late in the scheduler") + def test_getitem_casted_scalars_folding(self): + Tensor.manual_seed(0) + # cast of const is just another const, don't need extra kernels for this + a = Tensor.randn(2, 3) + one = Tensor(1, dtype=dtypes.int64) + self.assertEqual(data_ptr(a[1]), data_ptr(a[one.cast(dtypes.int32)])) + self.assertEqual(data_ptr(a[1]), data_ptr(a[one.cast(dtypes.int16)])) + + @unittest.skip("does not fold now") + def test_getitem_scalars_simple_folding(self): + a = Tensor.randn(2, 3) + zero = Tensor(0, dtype=dtypes.int64) + one = Tensor(1, dtype=dtypes.int64) + self.assertEqual(data_ptr(a[0, 1]), data_ptr(a[zero, one])) + + def test_basic_advanced_combined(self): + # From the NumPy indexing example + x = Tensor.arange(0, 12).reshape(4, 3) + numpy_testing_assert_equal_helper(x[1:2, 1:3], x[1:2, [1, 2]]) + numpy_testing_assert_equal_helper(x[1:2, 1:3].numpy().tolist(), [[4, 5]]) + + # Check that it is a copy + unmodified = clone(x) + x[1:2, [1, 2]].zeros_like() + numpy_testing_assert_equal_helper(x, unmodified) + + # But assignment should modify the original + # TODO fancy setitem + ''' + unmodified = clone(x) + x[1:2, [1, 2]] = 0 + self.assertNotEqual(x, unmodified) + ''' + + def test_int_assignment(self): + x = Tensor.arange(0, 4).reshape(2, 2) + x[1] = 5 + numpy_testing_assert_equal_helper(x.numpy().tolist(), [[0, 1], [5, 5]]) + + x = Tensor.arange(0, 4).reshape(2, 2) + x[1] = Tensor.arange(5, 7) + numpy_testing_assert_equal_helper(x.numpy().tolist(), [[0, 1], [5, 6]]) + + # TODO fancy setitem + ''' + def test_byte_tensor_assignment(self): + x = Tensor.arange(0., 16).reshape(4, 4) + b = Tensor([True, False, True, False], dtype=dtypes.uint8) + value = Tensor([3., 4., 5., 6.]) + + with warnings.catch_warnings(record=True) as w: + x[b] = value + numpy_testing_assert_equal_helper(len(w), 1) + + numpy_testing_assert_equal_helper(x[0], value) + numpy_testing_assert_equal_helper(x[1], Tensor.arange(4., 8)) + numpy_testing_assert_equal_helper(x[2], value) + numpy_testing_assert_equal_helper(x[3], Tensor.arange(12., 16)) + ''' + + @unittest.skip("Tensor unpacking not supported") + def test_variable_slicing(self): + x = Tensor.arange(0, 16).reshape(4, 4) + indices = Tensor([0, 1], dtype=dtypes.int32) + i, j = indices + numpy_testing_assert_equal_helper(x[i:j], x[0:1]) + + def test_ellipsis_tensor(self): + x = Tensor.arange(0, 9).reshape(3, 3) + idx = Tensor([0, 2]) + numpy_testing_assert_equal_helper(x[..., idx].numpy().tolist(), [[0, 2], + [3, 5], + [6, 8]]) + numpy_testing_assert_equal_helper(x[idx, ...].numpy().tolist(), [[0, 1, 2], + [6, 7, 8]]) + + # TODO unravel_index + ''' + def test_unravel_index_errors(self): + with self.assertRaises(TypeError): + unravel_index( + Tensor(0.5), + (2, 2)) + + with self.assertRaises(TypeError): + unravel_index( + Tensor([]), + (10, 3, 5)) + + with self.assertRaises(TypeError): + unravel_index( + Tensor([1], dtype=dtypes.int64), + Tensor([1, 2, 3])) + + with self.assertRaises(TypeError): + unravel_index( + Tensor([1], dtype=dtypes.int64), + (1, 2, 2.0)) + + with self.assertRaises(ValueError): + unravel_index( + Tensor(0), + (2, -3)) + ''' + + def test_invalid_index(self): + x = Tensor.arange(0, 16).reshape(4, 4) + self.assertRaises(TypeError, lambda: x["0":"1"]) + + def test_out_of_bound_index(self): + x = Tensor.arange(0, 100).reshape(2, 5, 10) + self.assertRaises(IndexError, lambda: x[0, 5]) + self.assertRaises(IndexError, lambda: x[4, 5]) + self.assertRaises(IndexError, lambda: x[0, 1, 15]) + self.assertRaises(IndexError, lambda: x[:, :, 12]) + + def test_zero_dim_index(self): + x = Tensor(10) + numpy_testing_assert_equal_helper(x, x.item()) + + def runner(): + print(x[0]) + return x[0] + + self.assertRaises(IndexError, runner) + + # TODO fancy setitem + ''' + def test_cpu_indices(self): + idx = Tensor([0, 1]) + b = Tensor.zeros(2) + x = Tensor.ones(10).contiguous() + x[idx] = b # index_put_ + ref = Tensor.ones(10).contiguous() + ref[:2] = 0 + numpy_testing_assert_equal_helper(x, ref) + out = x[idx] # index + numpy_testing_assert_equal_helper(out, Tensor.zeros(2)) + ''' + + def test_take_along_dim(self): + def _test_against_numpy(t: Tensor, indices: Tensor, dim): + actual = t.gather(dim, indices) + t_np = t.numpy() + indices_np = indices.numpy() + expected = np.take_along_axis(t_np, indices_np, axis=dim) + numpy_testing_assert_equal_helper(actual, expected) + + # TODO argsort + ''' + for shape in [(3, 2), (2, 3, 5), (2, 4, 0), (2, 3, 1, 4)]: + for noncontiguous in [True, False]: + for dtype in (dtypes.float32, dtypes.int64): + t = make_tensor(shape, dtype=dtype, noncontiguous=noncontiguous) + for dim in list(range(t.ndim)) + [None]: + if dim is None: + indices = argsort(t.reshape(-1)) + else: + indices = argsort(t, dim=dim) + + _test_against_numpy(t, indices, dim) + ''' + + # test broadcasting + t = Tensor.ones((3, 4, 1)) + indices = Tensor.ones((1, 2, 5), dtype=dtypes.int64) + + _test_against_numpy(t, indices, 1) + + # test empty indices + t = Tensor.ones((3, 4, 5)) + indices = Tensor.ones((3, 0, 5), dtype=dtypes.int64) + + _test_against_numpy(t, indices, 1) + + # TODO argsort + ''' + def test_take_along_dim_invalid(self): + for dtype in (dtypes.int64, dtypes.float32): + shape = (2, 3, 1, 4) + dim = 0 + t = make_tensor(shape, dtype=dtype) + indices = argsort(t, dim=dim) + + # dim of `t` and `indices` does not match + with self.assertRaises(RuntimeError, "input and indices should have the same number of dimensions"): + t.gather(0, indices[0]) + + # invalid `indices` dtype + with self.assertRaises(RuntimeError): + t.gather(0, indices.cast(dtypes.bool)) + + with self.assertRaises(RuntimeError): + t.gather(0, indices.cast(dtypes.float32)) + + with self.assertRaises(RuntimeError): + t.gather(0, indices.cast(dtypes.int32)) + + # invalid axis + with self.assertRaises(IndexError): + t.gather(-7, indices) + + with self.assertRaises(IndexError): + t.gather(7, indices) + ''' + +class TestNumpy(unittest.TestCase): + def test_index_no_floats(self): + a = Tensor([[[5.]]]) + + self.assertRaises(IndexError, lambda: a[0.0]) + self.assertRaises(IndexError, lambda: a[0, 0.0]) + self.assertRaises(IndexError, lambda: a[0.0, 0]) + self.assertRaises(IndexError, lambda: a[0.0, :]) + self.assertRaises(IndexError, lambda: a[:, 0.0]) + self.assertRaises(IndexError, lambda: a[:, 0.0, :]) + self.assertRaises(IndexError, lambda: a[0.0, :, :]) + self.assertRaises(IndexError, lambda: a[0, 0, 0.0]) + self.assertRaises(IndexError, lambda: a[0.0, 0, 0]) + self.assertRaises(IndexError, lambda: a[0, 0.0, 0]) + self.assertRaises(IndexError, lambda: a[-1.4]) + self.assertRaises(IndexError, lambda: a[0, -1.4]) + self.assertRaises(IndexError, lambda: a[-1.4, 0]) + self.assertRaises(IndexError, lambda: a[-1.4, :]) + self.assertRaises(IndexError, lambda: a[:, -1.4]) + self.assertRaises(IndexError, lambda: a[:, -1.4, :]) + self.assertRaises(IndexError, lambda: a[-1.4, :, :]) + self.assertRaises(IndexError, lambda: a[0, 0, -1.4]) + self.assertRaises(IndexError, lambda: a[-1.4, 0, 0]) + self.assertRaises(IndexError, lambda: a[0, -1.4, 0]) + # these two trigger slice internal type verification first + self.assertRaises(TypeError, lambda: a[0.0:, 0.0]) + self.assertRaises(TypeError, lambda: a[0.0:, 0.0,:]) + + def test_none_index(self): + # `None` index adds newaxis + a = Tensor([1, 2, 3]) + numpy_testing_assert_equal_helper(a[None].ndim, a.ndim+1) + + def test_empty_tuple_index(self): + # Empty tuple index creates a view + a = Tensor([1, 2, 3]) + numpy_testing_assert_equal_helper(a[()], a) + #self.assertEqual(data_ptr(a[()]), data_ptr(a)) + + # TODO jax supports empty tensor indexing + @unittest.skip("empty tensor indexing not supported") + def test_empty_fancy_index(self): + # Empty list index creates an empty array + a = Tensor([1, 2, 3]) + numpy_testing_assert_equal_helper(a[[]], np.array([])) + + b = Tensor([]).cast(dtypes.int64) + numpy_testing_assert_equal_helper(a[[]], np.array([])) + + b = Tensor([]).float() + self.assertRaises(IndexError, lambda: a[b]) + + def test_ellipsis_index(self): + a = Tensor([[1, 2, 3], + [4, 5, 6], + [7, 8, 9]]) + self.assertIsNot(a[...], a) + numpy_testing_assert_equal_helper(a[...], a) + # `a[...]` was `a` in numpy <1.9. + #numpy_testing_assert_equal_helper(data_ptr(a[...]), data_ptr(a)) + + # Slicing with ellipsis can skip an + # arbitrary number of dimensions + numpy_testing_assert_equal_helper(a[0, ...], a[0]) + numpy_testing_assert_equal_helper(a[0, ...], a[0, :]) + numpy_testing_assert_equal_helper(a[..., 0], a[:, 0]) + + # In NumPy, slicing with ellipsis results in a 0-dim array. In PyTorch + # we don't have separate 0-dim arrays and scalars. + numpy_testing_assert_equal_helper(a[0, ..., 1], np.array(2)) + + # Assignment with `(Ellipsis,)` on 0-d arrays + b = np.array(1) + b[(Ellipsis,)] = 2 + numpy_testing_assert_equal_helper(b, 2) + + def test_single_int_index(self): + # Single integer index selects one row + a = Tensor([[1, 2, 3], + [4, 5, 6], + [7, 8, 9]]) + + numpy_testing_assert_equal_helper(a[0], [1, 2, 3]) + numpy_testing_assert_equal_helper(a[-1], [7, 8, 9]) + + self.assertRaises(IndexError, a.__getitem__, 1 << 30) + self.assertRaises(IndexError, a.__getitem__, 1 << 64) + + @unittest.skip("bool indexing not supported") + def test_single_bool_index(self): + # Single boolean index + a = Tensor([[1, 2, 3], + [4, 5, 6], + [7, 8, 9]]) + + numpy_testing_assert_equal_helper(a[True], a[None]) + numpy_testing_assert_equal_helper(a[False], a[None][0:0]) + + @unittest.skip("bool indexing not supported") + def test_boolean_shape_mismatch(self): + arr = Tensor.ones((5, 4, 3)) + + index = Tensor([True]) + self.assertRaises(IndexError, lambda: arr[index]) + + index = Tensor([False] * 6) + self.assertRaises(IndexError, lambda: arr[index]) + + index = Tensor.zeros(4, 4, dtype=dtypes.uint8) + self.assertRaises(IndexError, lambda: arr[index]) + self.assertRaises(IndexError, lambda: arr[(slice(None), index)]) + + @unittest.skip("bool indexing not supported") + def test_boolean_indexing_onedim(self): + # Indexing a 2-dimensional array with + # boolean array of length one + a = Tensor([[0., 0., 0.]]) + b = Tensor([True]) + numpy_testing_assert_equal_helper(a[b], a) + # boolean assignment + a[b] = 1. + numpy_testing_assert_equal_helper(a, Tensor([[1., 1., 1.]])) + + @unittest.skip("bool indexing not supported") + def test_boolean_assignment_value_mismatch(self): + # A boolean assignment should fail when the shape of the values + # cannot be broadcast to the subscription. (see also gh-3458) + a = Tensor.arange(0, 4) + + def f(a, v): + a[a > -1] = Tensor(v) + + self.assertRaises(Exception, f, a, []) + self.assertRaises(Exception, f, a, [1, 2, 3]) + self.assertRaises(Exception, f, a[:1], [1, 2, 3]) + + @unittest.skip("bool indexing not supported") + def test_boolean_indexing_twodim(self): + # Indexing a 2-dimensional array with + # 2-dimensional boolean array + a = Tensor([[1, 2, 3], + [4, 5, 6], + [7, 8, 9]]) + b = Tensor([[True, False, True], + [False, True, False], + [True, False, True]]) + numpy_testing_assert_equal_helper(a[b], Tensor([1, 3, 5, 7, 9])) + numpy_testing_assert_equal_helper(a[b[1]], Tensor([[4, 5, 6]])) + numpy_testing_assert_equal_helper(a[b[0]], a[b[2]]) + + # boolean assignment + a[b] = 0 + numpy_testing_assert_equal_helper(a, Tensor([[0, 2, 0], + [4, 0, 6], + [0, 8, 0]])) + + @unittest.skip("bool indexing not supported") + def test_boolean_indexing_weirdness(self): + # Weird boolean indexing things + a = Tensor.ones((2, 3, 4)) + numpy_testing_assert_equal_helper((0, 2, 3, 4), a[False, True, ...].shape) + numpy_testing_assert_equal_helper(Tensor.ones(1, 2), a[True, [0, 1], True, True, [1], [[2]]]) + self.assertRaises(IndexError, lambda: a[False, [0, 1], ...]) + + @unittest.skip("bool indexing not supported") + def test_boolean_indexing_weirdness_tensors(self): + # Weird boolean indexing things + false = Tensor(False) + true = Tensor(True) + a = Tensor.ones((2, 3, 4)) + numpy_testing_assert_equal_helper((0, 2, 3, 4), a[False, True, ...].shape) + numpy_testing_assert_equal_helper(Tensor.ones(1, 2), a[true, [0, 1], true, true, [1], [[2]]]) + self.assertRaises(IndexError, lambda: a[false, [0, 1], ...]) + + @unittest.skip("bool indexing not supported") + def test_boolean_indexing_alldims(self): + true = Tensor(True) + a = Tensor.ones((2, 3)) + numpy_testing_assert_equal_helper((1, 2, 3), a[True, True].shape) + numpy_testing_assert_equal_helper((1, 2, 3), a[true, true].shape) + + @unittest.skip("bool indexing not supported") + def test_boolean_list_indexing(self): + # Indexing a 2-dimensional array with + # boolean lists + a = Tensor([[1, 2, 3], + [4, 5, 6], + [7, 8, 9]]) + b = [True, False, False] + c = [True, True, False] + numpy_testing_assert_equal_helper(a[b], Tensor([[1, 2, 3]])) + numpy_testing_assert_equal_helper(a[b, b], Tensor([1])) + numpy_testing_assert_equal_helper(a[c], Tensor([[1, 2, 3], [4, 5, 6]])) + numpy_testing_assert_equal_helper(a[c, c], Tensor([1, 5])) + + def test_everything_returns_views(self): + # Before `...` would return a itself. + a = Tensor([5]) + + self.assertIsNot(a, a[()]) + self.assertIsNot(a, a[...]) + self.assertIsNot(a, a[:]) + + def test_broaderrors_indexing(self): + a = Tensor.zeros(5, 5) + self.assertRaises(IndexError, a.__getitem__, ([0, 1], [0, 1, 2])) + self.assertRaises(IndexError, a.contiguous().__setitem__, ([0, 1], [0, 1, 2]), 0) + + # TODO out of bound getitem does not raise error + ''' + def test_trivial_fancy_out_of_bounds(self): + a = Tensor.zeros(5) + ind = Tensor.ones(20, dtype=dtypes.int64) + ind[-1] = 10 + self.assertRaises(IndexError, a.__getitem__, ind) + self.assertRaises(IndexError, a.__setitem__, ind, 0) + ind = Tensor.ones(20, dtype=dtypes.int64) + ind[0] = 11 + self.assertRaises(IndexError, a.__getitem__, ind) + self.assertRaises(IndexError, a.__setitem__, ind, 0) + ''' + + # TODO fancy setitem + ''' + def test_index_is_larger(self): + # Simple case of fancy index broadcasting of the index. + a = Tensor.zeros((5, 5)) + a[[[0], [1], [2]], [0, 1, 2]] = Tensor([2., 3., 4.]) + + self.assertTrue((a[:3, :3] == all_(Tensor([2., 3., 4.])))) + ''' + + # TODO fancy setitem + ''' + def test_broadcast_subspace(self): + a = Tensor.zeros((100, 100)) + v = Tensor.arange(0., 100)[:, None] + b = Tensor.arange(99, -1, -1).cast(dtypes.int64) + a[b] = v + expected = b.float().unsqueeze(1).expand(100, 100) + numpy_testing_assert_equal_helper(a, expected) + ''' + + # TODO fancy setitem + ''' + def test_truncate_leading_1s(self): + col_max = Tensor.randn(1, 4) + kernel = col_max.T * col_max # [4, 4] tensor + kernel2 = clone(kernel) + # Set the diagonal + # len(torch.tensor) is just tensor.shape[0] + kernel[range(kernel.shape[0]), range(kernel.shape[0])] = col_max.square() + kernel2 = diagonal(kernel2) + # torch.diagonal(kernel2).copy_(torch.square(col_max.view(4))) + kernel2 = copy_(kernel2, col_max.reshape(4).square()) + numpy_testing_assert_equal_helper(kernel, kernel2) + ''' + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_keccak.py b/tinygrad_repo/test/unit/test_keccak.py new file mode 100644 index 000000000..c32a74f8d --- /dev/null +++ b/tinygrad_repo/test/unit/test_keccak.py @@ -0,0 +1,42 @@ +from typing_extensions import Callable +import hashlib, random, unittest +from tinygrad import Tensor, Device, getenv, dtypes +from tinygrad.device import is_dtype_supported + +@unittest.skipUnless(is_dtype_supported(dtypes.uint8) and is_dtype_supported(dtypes.uint64), "Device must support uint8 and uint64") +@unittest.skipIf(getenv("MOCKGPU") and Device.DEFAULT == "NV", "crashes in NV CI") +class TestKeccak(unittest.TestCase): + def setUp(self) -> None: random.seed(1337) + + def test_shape_keeping(self): + s = (1, 2, 3, 4) + for i in range(len(s)): + out_shape = Tensor.randint(*s[i:], high=255, dtype=dtypes.uint8).keccak().shape + self.assertTupleEqual(s[i:-1], out_shape[:-1]) + + def test_sha3_224(self): self._test_preset("sha3_224", [143, 144]) + def test_sha3_256(self): self._test_preset("sha3_256", [135, 136]) + def test_shake_128(self): self._test_preset("shake_128", [167, 168], lambda d: hashlib.shake_128(d).digest(16)) + + def _test_preset(self, name: str, special_sizes: list[int], hasher: Callable[[bytes], bytes] | None = None): + def default_hasher(d: bytes) -> bytes: return getattr(hashlib, name)(d).digest() + if hasher is None: hasher = default_hasher + + for n in (special_sizes + [special_sizes[0] - 1]): + a, b = random.randbytes(n), random.randbytes(n) + + ha_ref, hb_ref = hasher(a), hasher(b) + tres = Tensor.stack(*(Tensor(d) for d in (a, b))).keccak(name) + ha, hb = tres[0].data(), tres[1].data() + + self.assertEqual(ha_ref, ha) + self.assertEqual(ha_ref, Tensor(a).keccak(name).data()) + self.assertEqual(hb_ref, hb) + + def test_abc(self): + # https://www.di-mgt.com.au/sha_testvectors.html + out = Tensor(b"abc").keccak() + self.assertEqual(bytes(out.tolist()), bytearray.fromhex("3a985da74fe225b2 045c172d6bd390bd 855f086e3e9d525b 46bfe24511431532")) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/unit/test_kernelize.py b/tinygrad_repo/test/unit/test_kernelize.py new file mode 100644 index 000000000..2b0bcee5b --- /dev/null +++ b/tinygrad_repo/test/unit/test_kernelize.py @@ -0,0 +1,33 @@ +import unittest +from tinygrad import Tensor +from tinygrad.uop import Ops + +class TestKernelize(unittest.TestCase): + def test_add_reshaped(self): + a = Tensor.ones(16,16).contiguous() + b = Tensor.zeros(16,16).contiguous() + ret = (a+b).sum(axis=1) + ret_reshaped_1 = ret.reshape(4,4) + ret_reshaped_2 = ret.reshape(2,8) + ret.kernelize() + self.assertIs(ret_reshaped_1.uop.src[0], ret_reshaped_2.uop.src[0]) + + def test_two_reduce(self): + a = Tensor.ones(16,16).contiguous() + a1 = a.sum(axis=1) + a0 = a1.sum(axis=0) + a0.kernelize() + self.assertIs(a1.uop.base.op, Ops.ASSIGN) + + def test_two_reduce_w_add(self): + a = Tensor.ones(16,16).contiguous() + a1 = a.sum(axis=1) + a0 = (a1+1).sum(axis=0) + a0.kernelize() + # NOTE: the +1 is fused with a1, so a1 is not kernelized + self.assertIs(a1.uop.base.op, Ops.REDUCE_AXIS) + # the input to the REDUCE_AXIS is an ASSIGN though + self.assertIs(a1.uop.base.src[0].base.op, Ops.ASSIGN) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_linearizer_rewrite.py b/tinygrad_repo/test/unit/test_linearizer_rewrite.py new file mode 100644 index 000000000..f42755804 --- /dev/null +++ b/tinygrad_repo/test/unit/test_linearizer_rewrite.py @@ -0,0 +1,32 @@ +import unittest +from tinygrad import Tensor, Context, Device +from tinygrad.engine.realize import get_program +from tinygrad.renderer import Opt, OptOps +from tinygrad.uop.ops import KernelInfo + +class TestLinearizerRewrite(unittest.TestCase): + def test_reduction(self): + t = Tensor.ones((64,64), device="NULL").contiguous().realize() + out = (t*2).sum(axis=1) + with Context(SPLIT_REDUCEOP=0, DEVECTORIZE=0): + si = out.schedule()[-1] + opts_to_apply = [] + opts_to_apply.append(Opt(OptOps.UPCAST, 0, 4)) + opts_to_apply.append(Opt(OptOps.UNROLL, 0, 4)) + ast = si.ast.replace(arg=KernelInfo(opts_to_apply=tuple(opts_to_apply))) + prg = get_program(ast, Device["CPU"].renderer) + print(prg.src) + + def test_arange(self): + out = Tensor.arange(32, device="NULL") + with Context(SPLIT_REDUCEOP=0, DEVECTORIZE=0): + si = out.schedule()[-1] + opts_to_apply = [] + opts_to_apply.append(Opt(OptOps.UPCAST, 0, 4)) + opts_to_apply.append(Opt(OptOps.UNROLL, 0, 4)) + ast = si.ast.replace(arg=KernelInfo(opts_to_apply=tuple(opts_to_apply))) + prg = get_program(ast, Device["CPU"].renderer) + print(prg.src) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_masked_st.py b/tinygrad_repo/test/unit/test_masked_st.py new file mode 100644 index 000000000..ce88a710a --- /dev/null +++ b/tinygrad_repo/test/unit/test_masked_st.py @@ -0,0 +1,32 @@ +import unittest +from tinygrad.tensor import Tensor + +class TestMaskedShapeTracker(unittest.TestCase): + def test_mul_masked(self): + a = Tensor([1,1,1,1,1]) + b = Tensor([1,1]).pad(((0,3),)) + c = a*b + assert c.shape == a.shape + #assert c.uop.st.views[0].mask is not None + ret = c.data() + assert ret.tolist() == [1.0, 1.0, 0.0, 0.0, 0.0] + + def test_mul_both_masked(self): + a = Tensor([1,1]).pad(((0,3),)) + b = Tensor([1,1]).pad(((0,3),)) + c = a*b + assert c.shape == a.shape + #assert c.uop.st.views[0].mask is not None + ret = c.data() + assert ret.tolist() == [1.0, 1.0, 0.0, 0.0, 0.0] + + def test_add_masked(self): + a = Tensor([1,1]).pad(((0,2),)) + b = Tensor([1,1]).pad(((0,2),)) + c = a+b + #assert c.uop.st.views[0].mask is not None + ret = c.data() + assert ret.tolist() == [2.0, 2.0, 0.0, 0.0] + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_microbenchmarks.py b/tinygrad_repo/test/unit/test_microbenchmarks.py new file mode 100644 index 000000000..71b43c880 --- /dev/null +++ b/tinygrad_repo/test/unit/test_microbenchmarks.py @@ -0,0 +1,43 @@ +import unittest, time +from tinygrad.uop.ops import UOp +from tinygrad.dtype import dtypes + +# it's about 1 ms per 1k UOps on M3 +N = 10000 + +class TestMicrobenchmarks(unittest.TestCase): + def setUp(self): + self.st = time.perf_counter() + def tearDown(self): + et = (time.perf_counter() - self.st) + print(f"{self._testMethodName} {et*1e3:.2f} ms") + + def test_uop_instant_creation(self): + for i in range(N): UOp.const(dtypes.int, 100+i) + + def test_uop_list_creation(self): + [UOp.const(dtypes.int, 100+i) for i in range(N)] + + def test_uop_add_2n(self): + a = UOp.const(dtypes.int, 2) + for _ in range(N): a = a + a + + def test_uop_toposort(self): + a = UOp.const(dtypes.int, 0) + for i in range(N): a = a + UOp.const(dtypes.int, 100+i) + self.setUp() + self.assertEqual(len(a.toposort()), 2*N+1) + + def test_uop_toposort_2n(self): + a = UOp.const(dtypes.int, 0) + for i in range(N): a = a + a + self.setUp() + self.assertEqual(len(a.toposort()), N+1) + + def test_uop_simplify(self): + a = UOp.const(dtypes.int, 2) + for _ in range(N): (a+a).simplify() + +if __name__ == '__main__': + unittest.main() + diff --git a/tinygrad_repo/test/unit/test_mnist_dataset.py b/tinygrad_repo/test/unit/test_mnist_dataset.py new file mode 100644 index 000000000..9db9a9e37 --- /dev/null +++ b/tinygrad_repo/test/unit/test_mnist_dataset.py @@ -0,0 +1,14 @@ +import unittest +from tinygrad.helpers import GlobalCounters +from tinygrad.nn.datasets import mnist + +class TestDataset(unittest.TestCase): + def test_dataset_is_realized(self): + X_train, _, _, _ = mnist() + X_train[0].contiguous().realize() + start = GlobalCounters.kernel_count + X_train[0].contiguous().realize() + self.assertEqual(GlobalCounters.kernel_count-start, 1) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_pattern_matcher.py b/tinygrad_repo/test/unit/test_pattern_matcher.py new file mode 100644 index 000000000..156d4d0cb --- /dev/null +++ b/tinygrad_repo/test/unit/test_pattern_matcher.py @@ -0,0 +1,215 @@ +import unittest, itertools +from tinygrad.dtype import dtypes +from tinygrad.uop.ops import Ops, UOp, GroupOp # noqa: F401 +from tinygrad.uop.ops import PatternMatcher, UPat + +class TestPatternMatcher(unittest.TestCase): + def test_simple_match(self): + matcher = PatternMatcher([(UPat(Ops.CONST, name="x", dtype=dtypes.float), lambda x: x.rtag())]) + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c2 = UOp(Ops.CONST, dtypes.int, arg=1) + self.assertEqual(matcher.rewrite(c1), c1.rtag()) + self.assertEqual(matcher.rewrite(c2), None) + + def test_upat_any(self): + def test(a, x=None, y=None, z=None): + #print(x,y,z) + if y is not None: return (a+y).rtag() + matcher = PatternMatcher([ + (UPat.var("a")+UPat.any(UPat.var("x"), UPat.var("y"), UPat.var("z")), test), + ]) + v1 = UOp.variable("a", 0, 10) + v2 = UOp.variable("b", 0, 10) + c1 = v1+v2 + self.assertEqual(matcher.rewrite(c1), c1.rtag()) + + def test_minimum_len(self): + matcher = PatternMatcher([ + (UPat(Ops.NOOP, src=(UPat(Ops.NOOP), UPat(Ops.NOOP)), allow_any_len=True), lambda: True), + ]) + self.assertTrue(matcher.rewrite(UOp(Ops.NOOP, src=(UOp(Ops.NOOP), UOp(Ops.NOOP), UOp(Ops.NOOP),)))) + self.assertTrue(matcher.rewrite(UOp(Ops.NOOP, src=(UOp(Ops.NOOP), UOp(Ops.NOOP))))) + self.assertIsNone(matcher.rewrite(UOp(Ops.NOOP, src=(UOp(Ops.NOOP),)))) + + @unittest.skip("closures aren't supported on pattern matchers") + def test_match_sz_0(self): + match_cnt = 0 + def fxn(x): + nonlocal match_cnt + match_cnt += 1 + assert len(x.src) == 0 + return UOp(Ops.CONST, src=(UOp(Ops.CONST),)) + matcher = PatternMatcher([(UPat(Ops.CONST, src=(), name="x"), fxn)]) + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + # second rewrite shouldn't match anything + c1 = matcher.rewrite(c1) + c1 = matcher.rewrite(c1) + self.assertEqual(match_cnt, 1) + + def test_match_sz_0_ctx(self): + def fxn(ctx, x): + ctx.append(True) + assert len(x.src) == 0 + return UOp(Ops.CONST, src=(UOp(Ops.CONST),)) + matcher = PatternMatcher([(UPat(Ops.CONST, src=(), name="x"), fxn)]) + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + # second rewrite shouldn't match anything + ctx = [] + c1 = matcher.rewrite(c1, ctx) + c1 = matcher.rewrite(c1, ctx) + self.assertEqual(len(ctx), 1) + + def test_uop(self): + matcher = PatternMatcher([(UPat(Ops.CONST, name="x"), lambda x: x.rtag())]) + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c2 = UOp(Ops.ADD, dtypes.float, (c1, c1)) + self.assertEqual(matcher.rewrite(c1), c1.rtag()) + self.assertEqual(matcher.rewrite(c2), None) + + def test_uop_set(self): + matcher = PatternMatcher([(UPat((Ops.CONST, Ops.CAST), name="x"), lambda x: x.rtag())]) + c1 = UOp(Ops.CONST, dtypes.bool, arg=False) + c2 = UOp(Ops.CAST, dtypes.int, (c1,)) + c3 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c4 = UOp(Ops.ADD, dtypes.float, (c3, c3)) + self.assertEqual(matcher.rewrite(c1), c1.rtag()) + self.assertEqual(matcher.rewrite(c2), c2.rtag()) + self.assertEqual(matcher.rewrite(c4), None) + + def test_arg(self): + matcher = PatternMatcher([ + (UPat(Ops.CONST, arg=0, name="x"), lambda x: x.rtag()), + (UPat(Ops.CONST, arg=False, name="x"), lambda x: x.rtag()), + (UPat(Ops.MAX, name="x"), lambda x: x.rtag()), + ]) + c1 = UOp(Ops.CONST, dtypes.float, arg=0.0) + c2 = UOp(Ops.CONST, dtypes.bool, arg=False) + c3 = UOp(Ops.MAX, dtypes.float, (c1, c1)) + c4 = UOp(Ops.MUL, dtypes.float, (c1, c1)) + c5 = UOp(Ops.CONST, dtypes.int, arg=-1) + self.assertEqual(matcher.rewrite(c1), c1.rtag()) + self.assertEqual(matcher.rewrite(c2), c2.rtag()) + self.assertEqual(matcher.rewrite(c3), c3.rtag()) + self.assertEqual(matcher.rewrite(c4), None) + self.assertEqual(matcher.rewrite(c5), None) + + def test_filter_arg(self): + matcher = PatternMatcher([ + (UPat(Ops.MUL, src=[UPat(Ops.CONST, name="c"), UPat(Ops.CONST, arg=2)], name="x"), + lambda x,c: x.rtag() if c.arg in {1, -1} else None) + ]) + y1 = UOp(Ops.CONST, dtypes.int, arg=1) + y2 = UOp(Ops.CONST, dtypes.int, arg=2) + y3 = UOp(Ops.CONST, dtypes.int, arg=-1) + c1 = UOp(Ops.MUL, dtypes.int, (y1, y2)) + c2 = UOp(Ops.MUL, dtypes.int, (y2, y2)) + c3 = UOp(Ops.MUL, dtypes.int, (y3, y2)) + c4 = UOp(Ops.MUL, dtypes.int, (y2, y1)) + c5 = UOp(Ops.MUL, dtypes.int, (y2, y3)) + self.assertEqual(matcher.rewrite(c1), c1.rtag()) + self.assertEqual(matcher.rewrite(c2), None) + self.assertEqual(matcher.rewrite(c3), c3.rtag()) + self.assertEqual(matcher.rewrite(c4), c4.rtag()) + self.assertEqual(matcher.rewrite(c5), c5.rtag()) + + def test_dup_name(self): + matcher = PatternMatcher([(UPat(GroupOp.ALU, name="x", src=(UPat(Ops.CONST, name="y"), UPat(Ops.CONST, name="y"))), lambda x, y: x.rtag())]) + y1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + y2 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c1 = UOp(Ops.ADD, dtypes.float, (y1, y1)) + c2 = UOp(Ops.ADD, dtypes.float, (y1, y2)) + self.assertEqual(matcher.rewrite(c1), c1.rtag()) + self.assertEqual(matcher.rewrite(c2), c1.rtag()) + + def test_dtype(self): + matcher = PatternMatcher([(UPat(Ops.CONST, name="x", dtype=dtypes.float32), lambda x: x.rtag())]) + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c2 = UOp(Ops.CONST, dtypes.float64, arg=1.0) + self.assertEqual(matcher.rewrite(c1), c1.rtag()) + self.assertEqual(matcher.rewrite(c2), None) + + def test_dtype_set(self): + matcher = PatternMatcher([(UPat(Ops.CONST, name="x", dtype={dtypes.float32, dtypes.float64}), lambda x: x.rtag())]) + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c2 = UOp(Ops.CONST, dtypes.float64, arg=1.0) + c3 = UOp(Ops.CONST, dtypes.float16, arg=1.0) + c4 = UOp(Ops.CONST, dtypes.int, arg=1) + self.assertEqual(matcher.rewrite(c1), c1.rtag()) + self.assertEqual(matcher.rewrite(c2), c2.rtag()) + self.assertEqual(matcher.rewrite(c3), None) + self.assertEqual(matcher.rewrite(c4), None) + + def test_src_one(self): + matcher = PatternMatcher([(UPat(GroupOp.ALU, name="x", src=(UPat(Ops.CONST), UPat(Ops.CONST))), lambda x: x.rtag())]) + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) + c3 = UOp(Ops.ADD, dtypes.float, (c1,c2)) + self.assertEqual(matcher.rewrite(c3), c3.rtag()) + self.assertEqual(matcher.rewrite(c2), None) + # that CONST/ALU -> ALU/CONST rewrite is now instant + """ + matcher = PatternMatcher([(UPat(GroupOp.ALU, name="x", src=(UPat(Ops.CONST), UPat(GroupOp.ALU))), lambda x: x)]) + c4 = UOp(Ops.ADD, dtypes.float, (c1,c3)) + c5 = UOp(Ops.ADD, dtypes.float, (c3,c1)) + self.assertEqual(matcher.rewrite(c3), None) + self.assertEqual(matcher.rewrite(c4), c4) + self.assertEqual(matcher.rewrite(c5), None) + """ + + def test_src_permutations(self): + matcher = PatternMatcher([(UPat(GroupOp.ALU, name="x", src=[UPat(Ops.CONST), UPat(GroupOp.ALU)]), lambda x: x.rtag())]) + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) + c3 = UOp(Ops.ADD, dtypes.float, (c1,c2)) + c4 = UOp(Ops.ADD, dtypes.float, (c3,c2)) + c5 = UOp(Ops.ADD, dtypes.float, (c2,c3)) + c6 = UOp(Ops.ADD, dtypes.float, (c3,c4)) + self.assertEqual(matcher.rewrite(c3), None) + self.assertEqual(matcher.rewrite(c4), c4.rtag()) + self.assertEqual(matcher.rewrite(c5), c5.rtag()) + self.assertEqual(matcher.rewrite(c6), None) + + def test_src_repeat(self): + matcher = PatternMatcher([(UPat(GroupOp.ALU, name="x", src=UPat(Ops.CONST)), lambda x: x.rtag())]) + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) + c3 = UOp(Ops.ADD, dtypes.float, (c1,c2)) + c4 = UOp(Ops.ADD, dtypes.float, (c2,c3)) + self.assertEqual(matcher.rewrite(c3), c3.rtag()) + self.assertEqual(matcher.rewrite(c4), None) + + def test_allow_len(self): + matcher = PatternMatcher([(UPat(Ops.MULACC, name="x", src=(UPat(Ops.CONST),), allow_any_len=True), lambda x: x.rtag())]) + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) + c3 = UOp(Ops.CONST, dtypes.float, arg=3.0) + c4 = UOp(Ops.EXP2, dtypes.float, (c1,)) + c5 = UOp(Ops.ADD, dtypes.float, (c1,c2)) + c6 = UOp(Ops.MULACC, dtypes.float, (c1,c2,c3)) + self.assertEqual(matcher.rewrite(c4), None) + self.assertEqual(matcher.rewrite(c5), None) + self.assertEqual(matcher.rewrite(c6), c6.rtag()) + + def test_deep_src_permutations(self): + c1 = UOp(Ops.CONST, dtypes.float, arg=1.0) + c2 = UOp(Ops.CONST, dtypes.float, arg=2.0) + u1 = (c1 + c2) + c1 + u2 = (c2 + c1) + c1 + matcher = PatternMatcher([ + (UPat(GroupOp.ALU, src=[UPat(GroupOp.ALU, src=[UPat(name='a'), UPat(name='b')]), UPat(name='b')]), lambda a,b: b) + ]) + self.assertIsNotNone(matcher.rewrite(u1)) + self.assertIsNotNone(matcher.rewrite(u2)) + + def _assert_eq_upat(self, a:UPat, b:UPat): + assert (sorted(map(str,a.op)) if a.op else [] == (sorted(map(str,b.op)) if b.op else [])) + assert (sorted(a.dtype) if a.dtype else [] == (sorted(b.dtype) if b.dtype else [])) + assert (a.name, type(a.src)) == (b.name, type(b.src)) + def simple_src(u:UPat): + if u.src is None: return [] + if isinstance(u.src, itertools.repeat): return next(u.src[0]) + return u.src[0] + for a,b in zip(simple_src(a), simple_src(b)): self._assert_eq_upat(a, b) + +if __name__ == '__main__': + unittest.main(verbosity=2) diff --git a/tinygrad_repo/test/unit/test_qcom.py b/tinygrad_repo/test/unit/test_qcom.py new file mode 100644 index 000000000..4794cdb17 --- /dev/null +++ b/tinygrad_repo/test/unit/test_qcom.py @@ -0,0 +1,73 @@ +#!/usr/bin/env python +import unittest +from tinygrad.device import Device, BufferSpec +from tinygrad.dtype import dtypes + +@unittest.skipUnless(Device.DEFAULT == "QCOM", "QCOM device required to run") +class TestQcom(unittest.TestCase): + def test_image_pitch(self): + dev = Device["QCOM"] + + def __validate(imgdt, expected_pitch): + img = dev.allocator.alloc(imgdt.shape[0] * imgdt.shape[1] * 16, options:=BufferSpec(image=imgdt)) + pitch = (img.descriptor[2] & 0x1fffff80) >> 7 + assert pitch == expected_pitch, f"Failed pitch for image: {imgdt}. Got 0x{pitch:X}, expected 0x{expected_pitch:X}" + dev.allocator.free(img, imgdt.shape[0] * imgdt.shape[1] * 16, options) + + __validate(dtypes.imageh((1, 201)), 0x680) + __validate(dtypes.imageh((16, 216)), 0x700) + __validate(dtypes.imageh((16, 9)), 0x80) + __validate(dtypes.imageh((48, 64)), 0x200) + __validate(dtypes.imageh((32, 128)), 0x400) + __validate(dtypes.imageh((96, 128)), 0x400) + __validate(dtypes.imageh((64, 256)), 0x840) + __validate(dtypes.imageh((64, 9)), 0x80) + __validate(dtypes.imageh((192, 256)), 0x840) + __validate(dtypes.imageh((64, 768)), 0x1840) + __validate(dtypes.imageh((256, 49)), 0x1C0) + __validate(dtypes.imageh((128, 9)), 0x80) + __validate(dtypes.imageh((16, 1024)), 0x2080) + __validate(dtypes.imageh((64, 512)), 0x1040) + __validate(dtypes.imageh((16, 512)), 0x1080) + __validate(dtypes.imageh((132, 64)), 0x200) + __validate(dtypes.imageh((4, 512)), 0x1200) + __validate(dtypes.imageh((8, 512)), 0x1100) + __validate(dtypes.imageh((128, 128)), 0x400) + __validate(dtypes.imageh((32, 512)), 0x1040) + __validate(dtypes.imageh((26, 64)), 0x200) + __validate(dtypes.imageh((32, 516)), 0x1040) + __validate(dtypes.imageh((32, 1024)), 0x2040) + __validate(dtypes.imageh((16, 2048)), 0x4080) + __validate(dtypes.imageh((8, 2048)), 0x4100) + __validate(dtypes.imageh((4, 4096)), 0x8200) + + __validate(dtypes.imagef((16, 49)), 0x380) + __validate(dtypes.imagef((16, 1024)), 0x4080) + __validate(dtypes.imagef((256, 64)), 0x400) + __validate(dtypes.imagef((64, 512)), 0x2040) + __validate(dtypes.imagef((16, 512)), 0x2080) + __validate(dtypes.imagef((132, 64)), 0x400) + __validate(dtypes.imagef((4, 512)), 0x2200) + __validate(dtypes.imagef((4, 16)), 0x200) + __validate(dtypes.imagef((2, 16)), 0x400) + __validate(dtypes.imagef((8, 512)), 0x2100) + __validate(dtypes.imagef((12, 64)), 0x400) + __validate(dtypes.imagef((3, 32)), 0x400) + __validate(dtypes.imagef((128, 128)), 0x840) + __validate(dtypes.imagef((32, 512)), 0x2040) + __validate(dtypes.imagef((8, 3072)), 0xC100) + __validate(dtypes.imagef((4, 2048)), 0x8200) + __validate(dtypes.imagef((4, 1024)), 0x4200) + __validate(dtypes.imagef((4, 4096)), 0x10200) + __validate(dtypes.imagef((10, 384)), 0x1900) + __validate(dtypes.imagef((24, 64)), 0x400) + __validate(dtypes.imagef((128, 12)), 0xC0) + __validate(dtypes.imagef((10, 24)), 0x200) + __validate(dtypes.imagef((1, 129)), 0x840) + __validate(dtypes.imagef((1, 32)), 0x200) + __validate(dtypes.imagef((1, 64)), 0x400) + __validate(dtypes.imagef((1, 1239)), 0x4D80) + __validate(dtypes.imagef((1, 1)), 0x40) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/unit/test_rearrange_einops.py b/tinygrad_repo/test/unit/test_rearrange_einops.py new file mode 100644 index 000000000..faf159b98 --- /dev/null +++ b/tinygrad_repo/test/unit/test_rearrange_einops.py @@ -0,0 +1,321 @@ +# modified from +# https://github.com/arogozhnikov/einops/blob/master/tests/test_examples.py +# https://github.com/arogozhnikov/einops/blob/master/tests/test_ops.py +# https://github.com/arogozhnikov/einops/blob/master/tests/test_parsing.py + +import numpy as np +import unittest +from tinygrad import Tensor + + +class test_rearrange_examples(unittest.TestCase): + def test1(self): + # transpose + x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) + y = x.rearrange("b c h w -> b h w c") + assert tuple(y.shape) == (10, 30, 40, 20) + + def test2(self): + # view / reshape + x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) + y = x.rearrange("b c h w -> b (c h w)") + assert tuple(y.shape) == (10, 20 * 30 * 40) + + def test3(self): + # depth-to-space + x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) + y = x.rearrange("b (c h1 w1) h w -> b c (h h1) (w w1)", h1=2, w1=2) + assert tuple(y.shape) == (10, 5, 30 * 2, 40 * 2) + + def test4(self): + # space-to-depth + x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) + y = x.rearrange("b c (h h1) (w w1) -> b (h1 w1 c) h w", h1=2, w1=2) + assert tuple(y.shape) == (10, 20 * 4, 30 // 2, 40 // 2) + + def test5(self): + # simple transposition + x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) + y = x.rearrange("b1 sound b2 letter -> b1 b2 sound letter") + assert tuple(y.shape) == (10, 30, 20, 40) + + def test6(self): + # parsing parameters + x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) + t = x.rearrange("b c h w -> (b h w) c") + t = t[:, ::2] # replacement for dot-product, just changes size of second axis + assert tuple(t.shape) == (10 * 30 * 40, 10) + + def test7(self): + x = Tensor(np.arange(10 * 20 * 30 * 40).reshape([10, 20, 30, 40])) + # split of embedding into groups + y1, y2 = x.rearrange("b (c g) h w -> g b c h w", g=2) + assert tuple(y1.shape) == (10, 10, 30, 40) + assert tuple(y2.shape) == (10, 10, 30, 40) + + def test8(self): + x = Tensor(np.arange(10 * 20 * 1 * 1).reshape([10, 20, 1, 1])) + # squeeze - unsqueeze + y = x.rearrange("b c () () -> b c") + assert tuple(y.shape) == (10, 20) + y = y.rearrange("b c -> c b () ()") + assert tuple(y.shape) == (20, 10, 1, 1) + + def test9(self): + x = Tensor(np.arange(10 * 20 * 1 * 1).reshape([10, 20, 1, 1])) + # squeeze - unsqueeze + y = x.rearrange("b c 1 1 -> b c") + assert tuple(y.shape) == (10, 20) + y = y.rearrange("b1 c -> c b1 1 1") + assert tuple(y.shape) == (20, 10, 1, 1) + + def test_tensor_train_example_numpy(self): + # kept here just for a collection, only tested for numpy + # https://arxiv.org/pdf/1509.06569.pdf, (5) + x = Tensor.ones([3, 4, 5, 6]) + rank = 4 + + # creating appropriate Gs + Gs = [Tensor.ones([d, d, rank, rank]) for d in x.shape] + Gs[0] = Gs[0][:, :, :1, :] + Gs[-1] = Gs[-1][:, :, :, :1] + + # einsum way + y = x.reshape((1,) + x.shape) + for G in Gs: + # taking partial results left-to-right + # y = numpy.einsum('i j alpha beta, alpha i ... -> beta ... j', G, y) + y = Tensor(np.einsum("i j a b, a i ... -> b ... j", G.numpy(), y.numpy())) + y1 = y.reshape(-1) + + # alternative way + y = x.reshape(-1) + for G in Gs: + i, j, alpha, beta = G.shape + y = y.rearrange("(i rest alpha) -> rest (alpha i)", alpha=alpha, i=i) + y = y @ G.rearrange("i j alpha beta -> (alpha i) (j beta)") + y = y.rearrange("rest (beta j) -> (beta rest j)", beta=beta, j=j) + y2 = y + assert np.allclose(y1.numpy(), y2.numpy()) + + # yet another way + y = x + for G in Gs: + i, j, alpha, beta = G.shape + y = y.rearrange("i ... (j alpha) -> ... j (alpha i)", alpha=alpha, i=i) + y = y @ G.rearrange("i j alpha beta -> (alpha i) (j beta)") + y3 = y.reshape(-1) + assert np.allclose(y1.numpy(), y3.numpy()) + + +class test_rearrange_ops(unittest.TestCase): + def test_rearrange_errors(self): + x = Tensor.zeros([1, 1, 1, 1, 1]) + x.rearrange("a b c d ... -> a b c ... d") + bad_patterns = [ + "a b c d (...) -> a b c ... d", # collapsed ellipsis on input + "a b (c d ... -> a b c ... d", # unbalanced brackets + "a b* c d ... -> a b c ... d", # not alphanumeric + "a b c d -> a b c d -> a b c d", # two "->" + "a ... c ... -> ... a ... c", # two "..." + "a b c d e -> f b c d e", # name mismatch + ] + for pattern in bad_patterns: + with self.assertRaises(AssertionError): + x.rearrange(pattern) + + x.rearrange("... -> (...)") + with self.assertRaises(AssertionError): + x.rearrange("(...) -> (...)") + + y = Tensor.zeros([8, 1]) + y.rearrange("(a1 a2 a3) b -> b a3 a2 a1", a1=2, a2=2) + with self.assertRaises(RuntimeError): + ## should fail as not enough dimensions specified + y.rearrange("(a1 a2 a3) b -> b a3 a2 a1", a1=2) + with self.assertRaises(ValueError): + ## should fail as 6 does not divide 8 + y.rearrange("(a1 a2 a3) b -> b a3 a2 a1", a1=3, a2=2) + with self.assertRaises(AssertionError): + ## incorrect dimension provided for an axis that is only permuted + y.rearrange("(a1 a2 a3) b -> b a3 a2 a1", a1=2, a2=2, b=2) + with self.assertRaises(AssertionError): + ## unused axis provided + y.rearrange("(a b c) d -> a b c d", b=2, c=2, e=2) + + def test_rearrange_ellipsis_ops(self): + identity_patterns = [ + "...->...", + "a b c d e-> a b c d e", + "a b c d e ...-> ... a b c d e", + "a b c d e ...-> a ... b c d e", + "... a b c d e -> ... a b c d e", + "a ... e-> a ... e", + "a ... -> a ... ", + "a ... c d e -> a (...) c d e", + ] + + equivalent_rearrange_patterns = [ + ("a b c d e -> (a b) c d e", "a b ... -> (a b) ... "), + ("a b c d e -> a b (c d) e", "... c d e -> ... (c d) e"), + ("a b c d e -> a b c d e", "... -> ... "), + ("a b c d e -> (a b c d e)", "... -> (...)"), + ("a b c d e -> b (c d e) a", "a b ... -> b (...) a"), + ("a b c d e -> b (a c d) e", "a b ... e -> b (a ...) e"), + ] + + xnp = np.arange(2 * 3 * 4 * 5 * 6).reshape([2, 3, 4, 5, 6]) + x = Tensor(xnp) + for pattern in identity_patterns: + assert np.array_equal(xnp, x.rearrange(pattern).numpy()), pattern + + for pattern1, pattern2 in equivalent_rearrange_patterns: + assert np.array_equal(x.rearrange(pattern1).numpy(), x.rearrange(pattern2).numpy()) + + def test_rearrange_consistency(self): + shape = [1, 2, 3, 5, 7, 11] + xnp = np.arange(np.prod(shape)).reshape(shape) + x = Tensor(xnp) + for pattern in [ + "a b c d e f -> a b c d e f", + "b a c d e f -> a b d e f c", + "a b c d e f -> f e d c b a", + "a b c d e f -> (f e) d (c b a)", + "a b c d e f -> (f e d c b a)", + ]: + result = x.rearrange(pattern).numpy() + assert len(np.setdiff1d(xnp, result)) == 0 + assert result.dtype == xnp.dtype + + result = x.rearrange("a b c d e f -> a (b) (c d e) f").numpy() + assert np.array_equal(xnp.flatten(), result.flatten()) + + result = x.rearrange("a aa aa1 a1a1 aaaa a11 -> a aa aa1 a1a1 aaaa a11").numpy() + assert np.array_equal(xnp, result) + + result1 = x.rearrange("a b c d e f -> f e d c b a").numpy() + result2 = x.rearrange("f e d c b a -> a b c d e f").numpy() + assert np.array_equal(result1, result2) + + result = x.rearrange("a b c d e f -> (f d) c (e b) a").rearrange("(f d) c (e b) a -> a b c d e f", b=2, d=5).numpy() + assert np.array_equal(xnp, result) + + sizes = dict(zip("abcdef", shape)) + temp = x.rearrange("a b c d e f -> (f d) c (e b) a", **sizes) + result = temp.rearrange("(f d) c (e b) a -> a b c d e f", **sizes).numpy() + assert np.array_equal(xnp, result) + + x2 = np.arange(2 * 3 * 4).reshape([2, 3, 4]) + result = Tensor(x2).rearrange("a b c -> b c a").numpy() + assert x2[1, 2, 3] == result[2, 3, 1] + assert x2[0, 1, 2] == result[1, 2, 0] + + def test_rearrange_permutations(self): + # tests random permutation of axes against two independent numpy ways + for n_axes in range(1, 10): + x = np.arange(2**n_axes).reshape([2] * n_axes) + permutation = np.random.permutation(n_axes) + left_expression = " ".join("i" + str(axis) for axis in range(n_axes)) + right_expression = " ".join("i" + str(axis) for axis in permutation) + expression = left_expression + " -> " + right_expression + result = Tensor(x).rearrange(expression).numpy() + + for pick in np.random.randint(0, 2, [10, n_axes]): + assert x[tuple(pick)] == result[tuple(pick[permutation])] + + for n_axes in range(1, 10): + x = np.arange(2**n_axes).reshape([2] * n_axes) + permutation = np.random.permutation(n_axes) + left_expression = " ".join("i" + str(axis) for axis in range(n_axes)[::-1]) + right_expression = " ".join("i" + str(axis) for axis in permutation[::-1]) + expression = left_expression + " -> " + right_expression + result = Tensor(x).rearrange(expression).numpy() + assert result.shape == x.shape + expected_result = np.zeros_like(x) + for original_axis, result_axis in enumerate(permutation): + expected_result |= ((x >> original_axis) & 1) << result_axis + + assert np.array_equal(result, expected_result) + +def check_expression_helper(expression: str): + Tensor.ones((1, 2, 3, 4, 5, 6, 7)) + +class test_rearrange_parsing(unittest.TestCase): + def test_elementary_axis_name(self): + for name in [ + "a", + "b", + "h", + "dx", + "h1", + "zz", + "i9123", + "somelongname", + "Alex", + "camelCase", + "u_n_d_e_r_score", + "unreasonablyLongAxisName", + ]: + Tensor.ones((1,)).rearrange(f"{name} -> {name}") + + for name in ["2b", "12", "_startWithUnderscore", "endWithUnderscore_", "_"]: + with self.assertRaises(AssertionError): + Tensor.ones((1,)).rearrange(f"{name} -> {name}") + + with self.assertRaises(RuntimeError): + Tensor.ones((1,)).rearrange(" -> ") + + def test_invalid_expressions(self): + # double ellipsis should raise an error + def _test_expression(expression: str): + Tensor.ones((2, 3, 4, 5, 6)).rearrange(f"{expression} -> {expression}") + + _test_expression("... a b c d") + with self.assertRaises(AssertionError): + _test_expression("... a b c d ...") + with self.assertRaises(AssertionError): + _test_expression("... a b c (d ...)") + with self.assertRaises(AssertionError): + _test_expression("(... a) b c (d ...)") + + # double/missing/enclosed parenthesis + Tensor.ones((2, 3, 4, 5, 6)).rearrange("a b c d ... -> (a) b c (d ...)") + with self.assertRaises(AssertionError): + _test_expression("(a)) b c (d ...)") + with self.assertRaises(AssertionError): + _test_expression("(a b c (d ...)") + with self.assertRaises(AssertionError): + _test_expression("(a) (()) b c (d ...)") + with self.assertRaises(AssertionError): + _test_expression("(a) ((b c) (d ...))") + + # invalid identifiers + _test_expression("camelCase under_scored cApiTaLs ß ...") + with self.assertRaises(AssertionError): + _test_expression("1a") + with self.assertRaises(AssertionError): + _test_expression("_pre") + with self.assertRaises(AssertionError): + _test_expression("...pre") + with self.assertRaises(AssertionError): + _test_expression("pre...") + + def test_unicode_ellipsis(self): + equivalent_rearrange_patterns = [ + ("a b … -> (a b) … ", "a b ... -> (a b) ... "), + ("… c d e -> … (c d) e", "... c d e -> ... (c d) e"), + ("… -> … ", "... -> ... "), + ("… -> (…)", "... -> (...)"), + ("a b … -> b (…) a", "a b ... -> b (...) a"), + ("a b … e -> b (a …) e", "a b ... e -> b (a ...) e"), + ] + + xnp = np.arange(2 * 3 * 4 * 5 * 6).reshape([2, 3, 4, 5, 6]) + x = Tensor(xnp) + + for pattern1, pattern2 in equivalent_rearrange_patterns: + assert np.array_equal(x.rearrange(pattern1).numpy(), x.rearrange(pattern2).numpy()) + + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/unit/test_rewrite_map.py b/tinygrad_repo/test/unit/test_rewrite_map.py new file mode 100644 index 000000000..adc8cd2f8 --- /dev/null +++ b/tinygrad_repo/test/unit/test_rewrite_map.py @@ -0,0 +1,202 @@ +import unittest +from tinygrad import dtypes +from tinygrad.uop.ops import UOp, graph_rewrite_map, _substitute +from tinygrad.uop.symbolic import symbolic + +class TestRewriteMap(unittest.TestCase): + def test_substitute(self): + a = UOp.variable('a', 0, 10) + b = UOp.variable('b', 0, 10) + c = UOp.variable('c', 0, 10) + e = UOp.variable('e', 0, 10) + ret = (a+b)*c + sub = {a+b: e} + sub_map = graph_rewrite_map(ret, _substitute, sub, bottom_up=True) + self.assertIs(sub_map[a+b], e) + self.assertIs(sub_map[(a+b)*c], e*c) + + def test_substitute_depth_2(self): + a = UOp.variable('a', 0, 10) + b = UOp.variable('b', 0, 10) + c = UOp.variable('c', 0, 10) + d = UOp.variable('d', 0, 10) + e = UOp.variable('e', 0, 10) + f = UOp.variable('f', 0, 10) + ret = (a+b)*c+d + sub = {a+b: e, (a+b)*c: f} + sub_map = graph_rewrite_map(ret, _substitute, sub, bottom_up=True) + self.assertIs(sub_map[a+b], e) + self.assertIs(sub_map[(a+b)*c], f) + + def test_multistage_substitute(self): + a = UOp.variable('a', 0, 10) + b = UOp.variable('b', 0, 10) + c = UOp.variable('c', 0, 10) + d = UOp.variable('d', 0, 10) + sub1 = {a+b:c} + start = (a+b)*c + # stage 1: (a+b)*c -> c*c + sub_map1 = graph_rewrite_map(start, _substitute, sub1, bottom_up=True) + self.assertIs(sub_map1[(a+b)*c], c*c) + # stage 2: c*c -> d + sub2 = {c*c:d} + sub_map2 = graph_rewrite_map(sub_map1[start], _substitute, sub2, input_map=sub_map1, bottom_up=True) + # (a+b)*c -> c*c -> d + self.assertIs(sub_map2[(a+b)*c], d) + + def test_add_zero(self): + # Build a small graph: add(0, add(const=0, const=5)) + zero_node = UOp.const(dtypes.int, 0) + five_node = UOp.const(dtypes.int, 5) + inner_add = zero_node + five_node + root_add = zero_node + inner_add + + # Perform top-down rewrite + node_map = graph_rewrite_map(root_add, symbolic) + + # We expect that add(0, add(0, 5)) -> add(0, 5) -> 5 + # Check the mapping + assert node_map[root_add] == five_node + assert node_map[inner_add] == five_node + # zero_node and five_node map to themselves + assert node_map[zero_node] == zero_node + assert node_map[five_node] == five_node + + def test_double_neg(self): + """ + Test rewriting neg(neg(5)) => 5 using symbolic. + """ + # In some versions of TinyGrad, you might do: (-(-five_node)) + five_node = UOp.const(dtypes.int, 5) + # If your code allows UOp(...), do that; else you might do something like: + # double_neg_five = -(-five_node) + # But let's be explicit: + neg_five = -five_node + double_neg_five = -neg_five + + node_map = graph_rewrite_map(double_neg_five, symbolic) + + # node_map should map double_neg_five -> five_node + self.assertEqual(node_map[double_neg_five], five_node) + # five_node maps to itself + self.assertEqual(node_map[five_node], five_node) + + def test_add_zero_and_double_neg(self): + """ + Combine both rewrites: add(0, neg(neg(5))) => add(0, 5) => 5 + """ + zero_node = UOp.const(dtypes.int, 0) + five_node = UOp.const(dtypes.int, 5) + neg_five = -five_node + double_neg_five = -neg_five + root_add = zero_node + double_neg_five + + node_map = graph_rewrite_map(root_add, symbolic) + + # node_map: root_add -> five_node, double_neg_five -> five_node + self.assertEqual(node_map[root_add], five_node) + self.assertEqual(node_map[double_neg_five], five_node) + # zero_node, five_node map to themselves + self.assertEqual(node_map[zero_node], zero_node) + self.assertEqual(node_map[five_node], five_node) + + def test_multi_var_rewrites(self): + x_var = UOp.variable('x', 0, 10) + y_var = UOp.variable('y', -5, 5) + zero_node = UOp.const(dtypes.int, 0) + + sum_with_zero = y_var + zero_node # (y + 0) + combined = x_var + sum_with_zero # x + (y + 0) + double_neg = -(-combined) # neg(neg(x + y)) + final_expr = zero_node + double_neg # 0 + (x + y) + + node_map = graph_rewrite_map(final_expr, symbolic) + + # The final root should be (x_var + y_var). + expected = x_var + y_var + + # Each sub-expression has its own "final" result. + # (y + 0) -> y_var + self.assertEqual(node_map[sum_with_zero], y_var) + # (x + (y+0)) -> (x + y) + self.assertEqual(node_map[combined], expected) + # neg(neg(x+y)) -> (x + y) + self.assertEqual(node_map[double_neg], expected) + # 0 + (x+y) -> (x + y) + self.assertEqual(node_map[final_expr], expected) + + # x_var, y_var, zero_node remain unchanged + self.assertEqual(node_map[x_var], x_var) + self.assertEqual(node_map[y_var], y_var) + self.assertEqual(node_map[zero_node], zero_node) + + def test_complex_multi_var_edges(self): + """ + Build a multi-variable expression with multiple intermediates: + + x_var = UOp.variable('x', 1, 10) + y_var = UOp.variable('y', -5, 5) + z_var = UOp.variable('z', 0, 5) + zero_node = UOp.const(dtypes.int, 0) + one_node = UOp.const(dtypes.int, 1) + + yz_sum = y_var + z_var + yz_sum_zero = yz_sum + zero_node -> rewrites to yz_sum + yz_neg = -yz_sum_zero -> -(y+z) + yz_dneg = -yz_neg -> y+z (double neg gone) + x_plus_yz = x_var + yz_dneg -> x + (y+z) + double_neg_x = -(-x_plus_yz) -> x + (y+z) + final_expr = double_neg_x * one_node -> x + (y+z) + + We expect the final result to be (x + (y+z)). + Each original node should map to the final node that replaces it, + which might be structurally equivalent but not the same reference. + """ + x_var = UOp.variable('x', 1, 10) + y_var = UOp.variable('y', -5, 5) + z_var = UOp.variable('z', 0, 5) + zero_node = UOp.const(dtypes.int, 0) + one_node = UOp.const(dtypes.int, 1) + + # Build sub-expressions + yz_sum = y_var + z_var # (y + z) + yz_sum_zero = yz_sum + zero_node # (y + z) + 0 + yz_neg = -yz_sum_zero # -(y+z) + yz_dneg = -yz_neg # -(-(y+z)) -> (y+z) + x_plus_yz = x_var + yz_dneg # x + (y+z) + double_neg_x = -(-x_plus_yz) # neg(neg(x+(y+z))) -> x+(y+z) + final_expr = double_neg_x * one_node # (x+(y+z)) * 1 -> x+(y+z) + + node_map = graph_rewrite_map(final_expr, symbolic) + + # (y + z) is unchanged + self.assertEqual(node_map[yz_sum], yz_sum) + + # (y+z) + 0 => (y+z) + self.assertEqual(node_map[yz_sum_zero], yz_sum) + + # -(y+z) remains -(y+z), but might be a new UOp with updated children + # Compare structurally to -(y_var + z_var). + self.assertEqual(node_map[yz_neg], -yz_sum) + + # -(-(y+z)) => (y+z) + self.assertEqual(node_map[yz_dneg], yz_sum) + + # x + (y+z) => might get recreated if yz_dneg was changed, so compare to x + yz_sum + self.assertEqual(node_map[x_plus_yz], x_var + yz_sum) + + # -(-(x+(y+z))) => x + (y+z) + self.assertEqual(node_map[double_neg_x], x_var + yz_sum) + + # (x+(y+z)) * 1 => x+(y+z) + self.assertEqual(node_map[final_expr], x_var + yz_sum) + + # Unchanged atomic nodes map to themselves + self.assertEqual(node_map[x_var], x_var) + self.assertEqual(node_map[y_var], y_var) + self.assertEqual(node_map[z_var], z_var) + self.assertEqual(node_map[zero_node], zero_node) + self.assertEqual(node_map[one_node], one_node) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/unit/test_rewrite_tracked_childen.py b/tinygrad_repo/test/unit/test_rewrite_tracked_childen.py new file mode 100644 index 000000000..6cddd6f28 --- /dev/null +++ b/tinygrad_repo/test/unit/test_rewrite_tracked_childen.py @@ -0,0 +1,63 @@ +import unittest +from tinygrad import Tensor +from tinygrad.uop.ops import PatternMatcher, Ops, UPat, graph_rewrite, RewriteContext, UOp +from tinygrad.kernelize.kernelize import sym, merge_views + +class TestRewriteTrackedChildren(unittest.TestCase): + @unittest.skip("track_children no longer supported") + def test_children_in_context(self): + def print_children(ctx:RewriteContext, sink:UOp): + view_w_child = sink.src[0].src[0].src[0] + assert view_w_child.op is Ops.VIEW + assert set([x.arg for x in ctx.children[view_w_child]]) == set((2,3)) + ctx.update_children() + assert set([x.arg for x in ctx.children[view_w_child]]) == set((3,4)) + # this is the 3 + assert len(ctx.children[sink.src[0].src[1]]) == 1 + assert next(iter(ctx.children[sink.src[0].src[1]])).op is Ops.ADD + # this is the 4 + assert len(ctx.children[sink.src[0].src[0]]) == 1 + assert next(iter(ctx.children[sink.src[0].src[0]])).op is Ops.ADD + rewrite = PatternMatcher([ + (UPat(Ops.CONST, arg=2, name="x"), lambda x: x.replace(arg=4)), + (UPat(Ops.SINK, name="sink"), print_children) + ]) + a = Tensor(2) + b = Tensor(3) + c = a + b + sink = c.uop.sink() + sink = graph_rewrite(sink, rewrite, track_children=True) + + def test_simple_child(self): + rewrite = PatternMatcher([ + (UPat(Ops.CONST, arg=2, name="x"), lambda x: x.replace(arg=4)), + ]) + a = Tensor(2) + b = Tensor(3) + c = a + b + sink = c.uop + view_w_child = a.uop.src[0] + print([x().arg for x in view_w_child.children]) + print([x.arg for x in sink.get_children_map()[view_w_child]]) + self.assertSetEqual(set([x.arg for x in sink.get_children_map()[view_w_child]]), set((2,3))) + # children can either be added to or removed from the map with graph_rewrite + # added to is easy to detect, just hook the UOp constructor + # when are children removed? + # * if a rewrite rule returns a UOp, the matched node is removed from the graph + sink = graph_rewrite(sink, rewrite) + print([x().arg for x in view_w_child.children]) + print([x.arg for x in sink.get_children_map()[view_w_child]]) + self.assertSetEqual(set([x.arg for x in sink.get_children_map()[view_w_child]]), set((3,4))) + + @unittest.skip("track_children no longer supported") + def test_child_after_parent_update(self): + def print_children(ctx, r): + ctx.update_children() + print(ctx.children[r]) + extra = PatternMatcher([(UPat(Ops.REDUCE_AXIS, name="r"), print_children)]) + a = Tensor.empty(3, 3) + r = (a+0).sum() + graph_rewrite(r.uop, merge_views+sym+extra, track_children=True) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_search.py b/tinygrad_repo/test/unit/test_search.py new file mode 100644 index 000000000..cb9eb3d3c --- /dev/null +++ b/tinygrad_repo/test/unit/test_search.py @@ -0,0 +1,55 @@ +import unittest +from tinygrad import Tensor, Device +from tinygrad.opt.kernel import Kernel +from tinygrad.device import Buffer +from tinygrad.opt.search import get_test_global_size, bufs_from_lin +from tinygrad.helpers import GlobalCounters +from extra.optimization.helpers import time_linearizer + +class TestSearchUtil(unittest.TestCase): + def test_get_test_global_size(self): + self.assertEqual(get_test_global_size([256, 256, 256], 65536, {}), ([256, 16, 16], 256.0)) + self.assertEqual(get_test_global_size([65536, 1, 1], 256, {}), ([256, 1, 1], 256.0)) + self.assertEqual(get_test_global_size([77, 1, 1], 16, {}), ([9, 1, 1], 77/9)) + + def test_bufs_from_lin(self): + a = Tensor([1,2,3,4]).realize() + si = (a+1).schedule()[0] + rawbufs = bufs_from_lin(lin:=Kernel(si.ast)) + assert len(rawbufs) == len(lin.membufs) == 2 + assert all(r is not None for r in rawbufs) + assert all(isinstance(r, Buffer) for r in rawbufs) + assert all(r.size > 0 for r in rawbufs) + + def test_bufs_from_lin_alt(self): + a = Tensor.randn(4, 4).realize() + b = a+a[0] + si = b.schedule()[0] + rawbufs = bufs_from_lin(k:=Kernel(si.ast)) + assert len(rawbufs) == len(k.membufs) == 2 + assert all(r is not None for r in rawbufs) + assert all(isinstance(r, Buffer) for r in rawbufs) + assert all(r.size > 0 for r in rawbufs) + +class TestTimeLinearizer(unittest.TestCase): + @unittest.skipIf(Device.DEFAULT == "WEBGPU", "WebGPU timestamps are low precision, tm is 0") + def test_reasonable_time(self): + a = Tensor([1,2,3,4]).realize() + si = (a+1).schedule()[0] + # create fresh empty buffers + rawbufs = [Buffer(b.device, b.size, b.dtype).allocate() for b in si.bufs] + tm = time_linearizer(Kernel(si.ast), rawbufs, allow_test_size=False, cnt=10, disable_cache=True) + assert tm > 0 and tm != float('inf') + + # Ensure that the kernel count is not incremented by time_linearizer when clearing l2 + def test_kernel_count(self): + ast = Tensor.zeros(16).contiguous().kernelize().uop.src[1].arg.ast + lin = Kernel(ast) + bufs = bufs_from_lin(lin) + + kernel_count = GlobalCounters.kernel_count + time_linearizer(lin, bufs, allow_test_size=False, cnt=2, disable_cache=True, clear_l2=True) + assert GlobalCounters.kernel_count == kernel_count, "kernel count was incremented by time_linearizer" + +if __name__ == "__main__": + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/unit/test_shapetracker.py b/tinygrad_repo/test/unit/test_shapetracker.py new file mode 100644 index 000000000..23fda9259 --- /dev/null +++ b/tinygrad_repo/test/unit/test_shapetracker.py @@ -0,0 +1,917 @@ +#!/usr/bin/env python +import unittest +import numpy as np +from tinygrad.dtype import dtypes +from tinygrad.helpers import prod +from tinygrad.shape.shapetracker import ShapeTracker, View +from tinygrad import Variable +from tinygrad.uop.ops import UOp, Ops, graph_rewrite +from tinygrad.codegen.devectorizer import sym +from itertools import product + +def shapetracker_getitem(st:ShapeTracker, val:int): + idx, valid = st.reshape((st.size,)).to_indexed_uops([UOp.const(dtypes.int, val)]) + idx, valid = graph_rewrite(idx, sym), graph_rewrite(valid, sym) + assert idx.op is Ops.CONST and valid.op is Ops.CONST + return idx.arg, valid.arg + +class CheckingShapeTracker: + def __init__(self, shape): + self.st = ShapeTracker.from_shape(shape) + self.t = np.arange(prod(shape), dtype=np.int32).reshape(shape) + + @property + def shape(self): + return self.t.shape + + def simplify(self): + self.st = self.st.simplify() + return self + + def reshape(self, new_shape): + self.st = self.st.reshape(new_shape) + self.t = self.t.reshape(new_shape) + return self + + def permute(self, axis): + self.st = self.st.permute(axis) + self.t = np.transpose(self.t, axis) + return self + + def expand(self, new_shape): + self.st = self.st.expand(new_shape) + self.t = np.broadcast_to(self.t, new_shape) + return self + + def flip(self, arg): + self.st = self.st.flip(arg) + self.t = np.flip(self.t, tuple(i for i in range(len(arg)) if arg[i])) + return self + + def shrink(self, arg): + self.st = self.st.shrink(arg) + self.t = self.t[tuple([slice(x[0], x[1]) for x in arg])] + return self + + def pad(self, arg): + self.st = self.st.pad(arg) + self.t = np.pad(self.t, arg, constant_values=-1) + return self + + def __getitem__(self, val): + return self.t.flatten()[val] + + @property + def views(self): return self.st.views + + @property + def contiguous(self): return self.st.contiguous + + def assert_same(self): + x = [(v[0] if (v:=shapetracker_getitem(self.st, i))[1] else -1) for i in range(prod(self.st.shape))] + y = [self[i] for i in range(prod(self.shape))] + assert self.st.shape == self.shape + assert x == y, f"mismatch shapetracker:{x} real:{y}" + +@unittest.skip("don't create shapetrackers with views") +class TestRealIssues(unittest.TestCase): + def test_reshape_doesnt_multiview(self): + self.st = ShapeTracker((View.create((256, 256, 2, 2, 2, 2, 2, 256, 8, 2), (0, 8, 0, 4, 0, 0, 2, 16384, 2048, 1), 0, None),)) + self.st.reshape((128, 2, 256, 2, 2, 2, 2, 2, 256, 8, 2)) + assert len(self.st.views) == 1 + + def test_reshape_stable_diffusion(self): + # regression test for https://github.com/tinygrad/tinygrad/pull/2616 + st = ShapeTracker((View((2, 1920, 32, 32), (1310720, 1024, 32, 1), 0, ((0, 2), (0, 1280), (0, 32), (0, 32)), False),)) + st = st.reshape((2, 32, 240, 256)) + assert len(st.views) == 2 + + def test_reshape_trailing_invalid_ones(self): + st = ShapeTracker((View(shape=(1, 1, 5), strides=(0, 0, 1), offset=-5, mask=((1, 1), (0, 1), (0, 5)), contiguous=False),)) + st = st.reshape((5,)) + assert len(st.views) == 1 + assert st.views[0].mask == ((0,0),) + +class TestRealDoesntSimplify(unittest.TestCase): + def tearDown(self): + st = self.st.real_strides() + print(st) + self.st = self.st.simplify() + assert len(self.st.views) != 1 + assert None in st + + def test_1(self): + self.st = ShapeTracker(( + View.create((8, 3, 1, 2, 11, 1), (33, 11, 0, 0, 1, 0), 0, None), + View.create((8, 6, 11), (66, 11, 1), 0, None))) + self.assertEqual(self.st.real_strides(), (33, None, 1)) + + def test_2(self): + self.st = ShapeTracker(( + View.create((2, 2, 4, 3, 3), (72, 9, 18, -3, -1), 8, None), + View.create((4, 4, 3, 3), (36, 9, 3, 1), 0, None))) + self.assertEqual(self.st.real_strides(), (None, 18, -3, -1)) + +class TestRealStrides(unittest.TestCase): + def test_1(self): + st = ShapeTracker(( + View.create((2048,), (1,), 0, ((0, 512),)), + View.create((16, 32, 4), (128, 4, 1), 0, None), + )) + self.assertEqual(st.real_strides(), (None, 4, 1)) + + def test_2(self): + # test/test_ops.py::TestOps::test_simple_padding_conv1d + st = ShapeTracker(( + View.create((6, 2, 5, 14), (90, 45, 1, 5), 0, ((0, 6), (0, 2), (0, 5), (0, 9))), + View.create((6, 2, 78), (140, 70, 1), 0, ((0, 6), (0, 2), (0, 70))), + View.create((6, 2, 13, 6), (156, 78, 1, 13), 0, None), + )) + self.assertEqual(st.real_strides(), (90, 45, None, None)) + + def test_3(self): + # test/test_ops.py::TestOps::test_simple_cumsum + st = ShapeTracker(( + View.create((4, 256, 512), (256, 0, 1), 0, ((0, 4), (0, 256), (0, 256))), + View.create((4, 131327), (131072, 1), 0, ((0, 4), (0, 131072))), + View.create((4, 511, 257), (131327, 1, 511), 0, None), + )) + self.assertEqual(st.real_strides(), (256, None, None)) + + def test_4(self): + # test/test_nn.py::TestNN::test_conv_transpose1d + st = ShapeTracker(( + View.create((4, 16, 56, 2), (896, 56, 1, 0), 0, ((0, 4), (0, 16), (0, 56), (0, 1))), + View.create((1, 4, 1, 16, 8, 121), (0, 1792, 0, 112, 0, 1), -5, ((0, 1), (0, 4), (0, 1), (0, 16), (0, 8), (5, 116))), + View.create((4, 64, 115, 16, 7), (15488, 0, 1, 968, 122), 0, None), + )) + self.assertEqual(st.real_strides(), (896, 0, None, 56, None)) + + def test_5(self): + # test/test_ops.py::TestOps::test_conv2d + st = ShapeTracker(( + View.create((1, 3, 1, 12, 2, 8), (0, 132, 0, 12, 1, 2), 0, ((0, 1), (0, 3), (0, 1), (0, 11), (0, 2), (0, 6))), + View.create((1, 3, 22, 21), (0, 192, 16, 1), 0, ((0, 1), (0, 3), (0, 12), (0, 16))), + View.create((3, 11, 7, 2, 3), (462, 21, 1, 231, 7), 0, None), + )) + self.assertEqual(st.real_strides(), (132, None, None, None, None)) + +class TestRealSimplifies(unittest.TestCase): + def tearDown(self): + st = self.st.real_strides() + self.st = self.st.simplify() + assert len(self.st.views) == 1 + print(self.st.views[-1].strides, st) + self.assertEqual(self.st.views[-1].strides, st) + + def test_1(self): + self.st = ShapeTracker(( + View.create((1, 3, 2, 11, 4, 28), (0, 308, 0, 28, 0, 1), 0, None), + View.create((1, 3, 2, 11, 26, 1, 1, 3), (0, 2464, 0, 112, 1, 0, 0, 29), 0, None))) + + def test_2(self): + self.st = ShapeTracker(( + View.create((8, 3, 3, 11, 2, 28), (924, 308, 0, 28, 0, 1), 0, None), + View.create((8, 1, 6, 10, 28, 3, 2, 1), (5544, 0, 0, 56, 1, 1848, 672, 0), 0, None))) + +class TestViewMinify(unittest.TestCase): + def test_minifies(self): + assert len(View.create((10,10)).minify().shape) == 1 + assert len(View.create((10,10)).permute((1,0)).minify().shape) == 2 + assert len(View.create((10,10,10,10)).permute((1,0,2,3)).minify().shape) == 3 + +class TestIndexExpressions2d(unittest.TestCase): + def setUp(self): + shapes = [(30, 5), (15, 10), (15, 1), (5, 10), (5, 1)] # Make sure dim0 is a multiple of 5, one of the tests divides this dimension by 5 + offsets = [0, 1, 15, 28, 10000] + self.sts = [ShapeTracker.from_shape((prod(base_shape)+offset,)).shrink(((offset, offset+prod(base_shape)),)).\ + reshape(base_shape) for base_shape in shapes for offset in offsets] + self.offset = [offset for base_shape in shapes for offset in offsets] + self.shapes = [shape for shape in shapes for offset in offsets] + self.idxs_exprs = [] + + def tearDown(self): + for st, offset, shape, idxs_expr in zip(self.sts, self.offset, self.shapes, self.idxs_exprs): + numel = prod(shape) + self.check_bounds(idxs_expr(self.default_idxs(st.shape)), offset, numel) + idx0s = [(0,0), (0, min(1, st.shape[0]-1)), (0, st.shape[0]-1), (min(3, st.shape[0]-1), min(6, st.shape[0]-1)), (st.shape[0]-1, st.shape[0]-1)] + idx1s = [(0,0), (0, min(1, st.shape[1]-1)), (0, st.shape[1]-1), (min(3, st.shape[1]-1), min(6, st.shape[1]-1)), (st.shape[1]-1, st.shape[1]-1)] + idx2s = [(0,0), (0, min(1, st.shape[2]-1)), (0, st.shape[2]-1), (min(3, st.shape[2]-1), min(6, st.shape[2]-1)), + (st.shape[2]-1, st.shape[2]-1)] if len(st.shape) == 3 else [None for _ in idx0s] + for idx0, idx1, idx2 in product(idx0s, idx1s, idx2s): + idxs = [Variable(f"idx{i}", idx[0], idx[1]) for i, idx in enumerate((idx0, idx1, idx2)) if idx is not None] + self.check_bounds(idxs_expr(idxs), offset, numel) + + def default_idx(self, shape): + return Variable("idx", 0, prod(shape)-1) + + def default_idxs(self, shape): + return [Variable(f"idx{i}", 0, d-1) for i,d in enumerate(shape)] + + def check_bounds(self, expr, offset, numel): + assert expr.vmin >= offset + assert expr.vmax <= offset + numel - 1 + + def test_noop(self): + for st, base_shape, offset in zip(self.sts, self.shapes, self.offset): + self.idxs_exprs.append(lambda idxs, base_shape=base_shape, offset=offset: idxs[0]*base_shape[1] + idxs[1] + offset) + + def test_permute(self): + new_st = [] + for st, base_shape, offset in zip(self.sts, self.shapes, self.offset): + st = st.permute((1, 0)) + self.idxs_exprs.append(lambda idxs, base_shape=base_shape, offset=offset: idxs[0] + idxs[1]*base_shape[1] + offset) + new_st.append(st) + self.sts = new_st + + def test_reshape(self): + new_st = [] + for st, base_shape, offset in zip(self.sts, self.shapes, self.offset): + st = st.reshape((base_shape[0], 1, base_shape[1])) + self.idxs_exprs.append(lambda idxs, base_shape=base_shape, offset=offset: idxs[0]*base_shape[1] + idxs[2] + offset) + new_st.append(st) + self.sts = new_st + + def test_reshape_expand(self): + new_st = [] + for st, base_shape, offset in zip(self.sts, self.shapes, self.offset): + st = st.reshape((base_shape[0], 1, base_shape[1])) + st = st.expand((base_shape[0], base_shape[1], base_shape[1])) + self.idxs_exprs.append(lambda idxs, base_shape=base_shape, offset=offset: idxs[0]*base_shape[1] + idxs[2] + offset) + new_st.append(st) + self.sts = new_st + + def test_permute_reshape_1(self): # This tests multiple views + new_st = [] + for st, base_shape, offset in zip(self.sts, self.shapes, self.offset): + st = st.permute((1, 0)) + st = st.reshape((base_shape[0]//5, 1, base_shape[1]*5)) + self.idxs_exprs.append(lambda idxs, base_shape=base_shape, offset=offset: (idxs[0]*(base_shape[1]*5)+idxs[2])%base_shape[0]*base_shape[1] + \ + (idxs[0]*(base_shape[1]*5)+idxs[2])//base_shape[0] + offset) + new_st.append(st) + self.sts = new_st + + def test_permute_reshape_2(self): + new_st = [] + for st, base_shape, offset in zip(self.sts, self.shapes, self.offset): + st = st.permute((1, 0)) + st = st.reshape((1, base_shape[0]//5, base_shape[1]*5)) + self.idxs_exprs.append(lambda idxs, base_shape=base_shape, offset=offset: (idxs[1]*(base_shape[1]*5)+idxs[2])%base_shape[0]*base_shape[1] + \ + (idxs[1]*(base_shape[1]*5)+idxs[2])//base_shape[0] + offset) + new_st.append(st) + self.sts = new_st + + def test_reshaping_splitting(self): + self.st = CheckingShapeTracker((5,10,5,10)) + self.st.permute((1, 0, 3, 2)) + self.st.pad(((0,0), (0,5), (0,0), (0,5))) + self.st.reshape((10,2,5,10,2,5)) + assert len(self.st.views) == 1 + self.st.assert_same() + + def test_reshape_splitting_1(self): + self.st = CheckingShapeTracker((1,10,1)) + self.st.pad(((0,4),(0,0),(1,0))) + self.st.reshape((5,5,2,2)) + assert len(self.st.views) == 1 + self.st.assert_same() + + def test_reshape_combining_1(self): + self.st = CheckingShapeTracker((2,1,10)) + self.st.pad(((2,6), (0,0), (0,0))) + self.st.reshape((100,)) + assert len(self.st.views) == 1 + self.st.assert_same() + + def test_reshape_combining_2(self): + self.st = CheckingShapeTracker((1,1,5)) + self.st.pad(((3,6), (0,0), (0,5))) + self.st.reshape((100,)) + assert len(self.st.views) == 1 + self.st.assert_same() + + def test_reshape_combining_3(self): + self.st = CheckingShapeTracker((1,1,4)) + self.st.pad(((3,6), (0,0), (1,5))) + self.st.reshape((100,)) + assert len(self.st.views) == 1 + assert self.st.views[0].mask[0] == (31, 35) + self.st.assert_same() + + def test_reshape_combining_4(self): + # interestingly this one is quite slow + self.st = CheckingShapeTracker((1,1,5,5,1,1,5)) + self.st.pad(((2,1), (0,0), (0,2), (0,0), (2,1), (0,0), (0,2))) + self.st.reshape((28,5,28)) + assert len(self.st.views) == 1 + self.st.assert_same() + + def test_reshape_splitting_combining(self): + self.st = CheckingShapeTracker((1,5,5)) + self.st.pad(((0,4), (0,5), (0,0))) + self.st.reshape((10,25)) + assert len(self.st.views) == 1 + self.st.assert_same() + + def test_reshape_only_1s(self): + self.st = CheckingShapeTracker((1, 1, 1, 4, 1, 3, 5, 1)) + self.st.pad(((0,4), (0,0), (0,0), (1,1), (0,0), (0,0), (0,0), (0,0))) + self.st.reshape((5, 6, 3, 5)) + assert len(self.st.views) == 1 + self.st.assert_same() + self.st.reshape((1, 1, 5, 6, 3, 5, 1, 1)) + assert len(self.st.views) == 1 + self.st.assert_same() + self.st.reshape((1, 5, 6, 1, 3, 1, 5, 1)) + assert len(self.st.views) == 1 + self.st.assert_same() + + def test_zero_mask_1(self): + self.st = CheckingShapeTracker((1, 3, 2)) + self.st.pad(((0,0), (0,3), (0,0))) + self.st.shrink(((0,1), (3,6), (0,2))) + self.st.reshape((3,2)) + assert len(self.st.views) == 1 + self.st.assert_same() + self.st.reshape((1, 3, 1, 2, 1)) + assert len(self.st.views) == 1 + self.st.assert_same() + + def test_zero_mask_2(self): + self.st = CheckingShapeTracker((1, 3, 2)) + self.st.pad(((0,2), (0,3), (0,0))) + self.st.shrink(((2,3), (3,6), (0,2))) + self.st.reshape((3,2)) + assert len(self.st.views) == 1 + self.st.assert_same() + self.st.reshape((1, 3, 1, 2, 1)) + assert len(self.st.views) == 1 + self.st.assert_same() + + def test_expanded_reshaped(self): + self.st = CheckingShapeTracker((1, 3, 2, 1)) + self.st.expand((5, 3, 2, 2)) + self.st.pad(((0,0), (0,3), (0,0), (0, 0))) + self.st.reshape((5, 2, 3, 2, 2)) + assert len(self.st.views) == 1 + self.st.assert_same() + + def test_splitting_big(self): + self.st = CheckingShapeTracker((1, 5, 1, 15, 1)) + self.st.pad(((0,0), (0,5), (0,0), (0,15), (0,0))) + self.st.reshape((10, 1, 30)) + self.st.permute((2,1,0)) + self.st.reshape((2,3,5,2,5)) + assert len(self.st.views) == 1 + v = self.st.views[-1] + assert v.strides == (0, 5, 1, 0, 15) and v.mask == ((0, 1), (0, 3), (0, 5), (0, 1), (0, 5)) + self.st.assert_same() + + def test_combining_big(self): + self.st = CheckingShapeTracker((1,3,1,5,3,1)) + self.st.pad(((0,0),(2,2),(0,0),(0,0),(0,0),(0,0))) + self.st.reshape((1,1,1,105,1,1)) + assert len(self.st.views) == 1 + v = self.st.views[-1] + assert v.strides == (0, 0, 0, 1, 0, 0) and v.mask == ((0, 1), (0, 1), (0, 1), (30, 75), (0, 1), (0, 1)) and v.offset == -30 + self.st.assert_same() + + def test_pad_reshape(self): + self.st = CheckingShapeTracker((4,)) + self.st.pad(((2,2),)) + self.st.reshape((4,2)) + assert len(self.st.views) == 1 + self.st.assert_same() + +class TestSimplifyingShapeTracker(unittest.TestCase): + def setUp(self): + self.st = CheckingShapeTracker((1, 10)) + + def tearDown(self): + self.st.assert_same() + + # multiview simplify + def test_expand_contract_simple(self): + self.st = self.st.expand((10, 10)) + self.st = self.st.reshape((100,)) + print(self.st.views) + assert (len(self.st.views) == 2) + self.st = self.st.reshape((10, 10)) + print(self.st.views) + + self.st = self.st.simplify() + print(self.st.views) + assert (len(self.st.views) == 1) + + # multiview simplify + def test_expand_contract_different_shape(self): + self.st.expand((10, 10)) + self.st.reshape((100,)) + print(self.st.views) + assert (len(self.st.views) == 2) + self.st.reshape((2, 5, 2, 5)) + print(self.st.views) + + self.st = self.st.simplify() + print(self.st.views) + assert (len(self.st.views) == 1) + + # multiview simplify + def test_expand_contract_still_complex(self): + self.st.expand((10, 10)) + self.st.reshape((100,)) + print(self.st.views) + assert (len(self.st.views) == 2) + self.st.reshape((5, 20)) + + self.st = self.st.simplify() + print(self.st.views) + assert (len(self.st.views) == 2) + +# Tensor.zeros(2, 4).permute(1,0).reshape(2, 4) +# (d1*4 + d0%4), d1=x//4, d0=x%4 = ((x//4)*4) + (x%4)%4 + +class TestComplexShapeTracker(unittest.TestCase): + def test_add_1s(self): + self.st = CheckingShapeTracker((4, 4)) + self.st.permute((1,0)) + self.st.reshape((1,4,1,4,1)) + assert not self.st.contiguous + self.st.permute((0,3,2,1,4)) + assert self.st.contiguous + + def test_permute_1s_simple(self): + self.st = CheckingShapeTracker((1, 16, 9,9)) + self.st.permute((1,0,2,3)) + assert self.st.contiguous + self.st = CheckingShapeTracker((2, 16, 9,9)) + self.st.permute((1,0,2,3)) + assert not self.st.contiguous + + def test_remove_1s_simple(self): + self.st = CheckingShapeTracker((1, 16, 1, 1)) + self.st.reshape((16,)) + assert self.st.contiguous + + def test_remove_1s(self): + self.st = CheckingShapeTracker((1, 4, 1, 4, 1)) + self.st.permute((0,3,2,1,4)) + self.st.reshape((4,4)) + assert not self.st.contiguous + self.st.permute((1,0)) + assert self.st.contiguous + + def test_permute_reshape(self): + self.st = CheckingShapeTracker((4, 4)) + self.st.permute((1,0)) + self.st.reshape((2, 2, 2, 2)) + # TODO: should also be tested by test_super_complex + assert len(self.st.views) == 1 + + def test_factorize_split(self): + self.st = CheckingShapeTracker((4, 4)) + self.st.permute((1,0)) + self.st.reshape((2, 2, 2, 2)) + self.st.permute((2,3,0,1)) + assert self.st.contiguous + + def test_factorize_combine(self): + self.st = CheckingShapeTracker((4, 4, 4)) + self.st.permute((2, 0, 1)) + self.st.reshape((4, 16)) + self.st.permute((1, 0)) + assert self.st.contiguous + + def test_factorize_combine_add_ones(self): + self.st = CheckingShapeTracker((4, 4, 4)) + self.st.permute((2, 0, 1)) + self.st.reshape((4, 16, 1, 1)) + self.st.permute((1, 0, 2, 3)) + assert self.st.contiguous + + def test_fancy_factorize(self): + self.st = CheckingShapeTracker((32, 3, 3, 1)) + self.st.reshape((8, 4, 3, 3)) + assert len(self.st.views) == 1 + + def test_super_complex_2_fail(self): + self.st = CheckingShapeTracker((4, 4, 4)) + self.st.permute((2, 0, 1)) + self.st.reshape((16, 4)) + assert len(self.st.views) != 1 + + def test_work(self): + self.st = CheckingShapeTracker((64, 1024, 4)) + self.st.reshape((1, 64, 128, 32)) + self.st.permute((0, 3, 1, 2)) + self.st.reshape((1, 32, 1, 64, 128)) + self.st.permute((0, 3, 4, 1, 2)) + assert self.st.contiguous + + def test_work2(self): + self.st = CheckingShapeTracker((64, 1024, 4)) + self.st.reshape((1, 64, 128, 32)) + self.st.permute((0, 3, 1, 2)) + self.st.reshape((1, 1, 32, 64, 128)) + self.st.permute((0, 3, 4, 1, 2)) + self.st.reshape((64, 1024, 4)) + print(self.st.views) + assert self.st.contiguous + +class TestShapeTrackerEquality(unittest.TestCase): + def test_simple_equals(self): + self.assertEqual(ShapeTracker.from_shape((10,10)), ShapeTracker.from_shape((10,10))) + def test_other_equals(self): + st1 = ShapeTracker(views=(View(shape=(3,), strides=(1,), offset=0, mask=None, contiguous=True))) + st2 = ShapeTracker(views=(View(shape=(3,), strides=(1,), offset=0, mask=None, contiguous=True))) + self.assertEqual(st1, st2) + +class TestSingleShapeTracker(unittest.TestCase): + def setUp(self): + self.st = CheckingShapeTracker((7,4)) + + def tearDown(self): + self.st.assert_same() + + def test_reshape(self): + self.st.reshape((7,1,4)) + assert self.st.contiguous + + def test_permute(self): + self.st.permute((1,0)) + assert not self.st.contiguous + + def test_shrink(self): + self.st.shrink(((1,2), (0,4))) + assert not self.st.contiguous + + def test_double_permute(self): + self.st.permute((1,0)) + self.st.permute((1,0)) + assert self.st.contiguous + + def test_reshape_permute(self): + self.st.reshape((7,1,4)) + self.st.permute((0,1,2)) + assert self.st.contiguous + + def test_reshape_permute_yes(self): + self.st.reshape((7,1,4)) + self.st.permute((0,2,1)) + assert self.st.contiguous + + def test_reshape_permute_no(self): + self.st.reshape((4,7)) + self.st.permute((1,0)) + assert not self.st.contiguous + +class TestShapeTrackerFuzzFailures(unittest.TestCase): + def setUp(self): + self.st = CheckingShapeTracker((3,3,3)) + def tearDown(self): + self.st.assert_same() + def test_case_1(self): + self.st.shrink(((1, 2), (1, 3), (1, 3))) + self.st.reshape((1, 4)) + self.st.shrink(((0, 1), (1, 3))) + self.st = self.st.simplify() + def test_case_2(self): + self.st.flip( (True, False, True) ) + self.st.reshape( (3, 9) ) + self.st.shrink( ((1, 2), (1, 5)) ) + self.st.flip( (True, True) ) + def test_case_3(self): + self.st.shrink( ((0, 2), (0, 2), (0, 1)) ) + self.st.permute( (1, 0, 2) ) + self.st.reshape( (4,) ) + self.st.shrink( ((0, 3),) ) + self.st.flip( (True, False) ) + def test_case_4(self): + self.st.reshape( (3, 3, 3, 1) ) + self.st.pad( ((0, 0), (0, 0), (0, 0), (1, 1)) ) + self.st.shrink( ((0, 2), (1, 2), (0, 2), (0, 1)) ) + self.st.expand( (2, 1, 2, 3) ) + +class TestMaskedShapeTracker(unittest.TestCase): + def test_pad_1x1(self): + self.st = CheckingShapeTracker((1,1)) + self.st.pad(((1,1), (1,1))) + self.st.assert_same() + + def test_pad_2x2(self): + self.st = CheckingShapeTracker((2,2)) + self.st.pad(((1,1), (1,1))) + self.st.assert_same() + + def test_pad_reshape(self): + st1 = CheckingShapeTracker((1, 2)) + st1.pad(((1, 0), (0, 1))) + st1.reshape((3, 2)) + st1.assert_same() + + st2 = CheckingShapeTracker((1, 2)) + st2.pad(((1, 1), (0, 2))) + st2.reshape((4, 3)) + st2.assert_same() + + st3 = CheckingShapeTracker((1, 1, 1, 2)) + st3.pad(((0, 2), (1, 2), (2, 2), (0, 4))) + st3.reshape((4, 3, 6, 5)) + st3.assert_same() + + def test_axis_is_masked(self): + st = ShapeTracker.from_shape((100, 100, 100, 100)).pad(((0,1),(0,0),(2,0), (0,0))) + assert st.axis_is_masked(0) + assert not st.axis_is_masked(1) + assert st.axis_is_masked(2) + assert not st.axis_is_masked(3) + + def test_axis_is_masked_rw1(self): + st = ShapeTracker(views=(View(shape=(1, 2, 1, 4, 4, 13, 4, 13), strides=(0, 324, 0, 81, 0, 9, 0, 1), offset=-20, + mask=((0, 1), (0, 2), (0, 1), (0, 4), (0, 4), (2, 11), (0, 4), (2, 11)), contiguous=False), + View(shape=(2, 4, 11, 11, 4, 3, 3), strides=(10816, 0, 52, 1, 2704, 728, 14), offset=0, + mask=None, contiguous=False))) + assert not st.axis_is_masked(0) + +class TestShapeTracker(unittest.TestCase): + def setUp(self): + self.st = CheckingShapeTracker((7,4)) + self.apply = lambda fxn: [fxn(x) for x in [self.st]] + + def tearDown(self): + self.st.assert_same() + + def test_noop(self): + pass + + def test_simple_split(self): + self.test_permute() + self.apply(lambda x: x.reshape((prod(self.st.shape), ))) + + def test_simple_pad(self): + self.st.pad(((1,1), (1,1))) + + def test_pad_shrink(self): + self.st.pad(((1,1), (1,1))) + self.st.shrink(((0,4), (0,4))) + + def test_pad_one_sided(self): + self.st.pad(((0,1), (0,0))) + + def test_pad_reshape(self): + self.st.pad(((0,1), (0,0))) + self.st.reshape((8*4,)) + + def test_pad_pad(self): + self.st.pad(((1,1), (1,1))) + self.st.pad(((1,1), (1,1))) + + def test_pad_permute(self): + self.st.pad(((1,1), (2,2))) + self.st.permute((1,0)) + + def test_pad_expand(self): + self.st.reshape((7,4,1)) + self.st.pad(((1,1), (1,1), (0,0))) + self.st.expand((9,6,4)) + + def test_pad_expand_alt(self): + self.st.pad(((1,1), (1,1))) + self.st.reshape((9,6,1)) + self.st.expand((9,6,4)) + + def test_pad_flip(self): + self.st.pad(((1,4), (1,3))) + self.st.flip((True, False)) + + def test_pad_flip_int(self): + self.st.pad(((1,4), (1,3))) + self.st.flip((0, 1)) + + def test_reshape(self): + new_shape = self.st.shape[::-1] + self.apply(lambda x: x.reshape(new_shape)) + + def test_permute(self): + if len(self.st.shape) == 2: self.apply(lambda x: x.permute((1,0))) + elif len(self.st.shape) == 3: self.apply(lambda x: x.permute((2,0,1))) + + def test_reshape_with_1(self): + new_shape = (self.st.shape[0], 1, self.st.shape[1]) + self.apply(lambda x: x.reshape(new_shape)) + + def test_expand(self): + self.test_reshape_with_1() + new_shape = list(self.st.shape) + new_shape[1] = 2 + self.apply(lambda x: x.expand(tuple(new_shape))) + + def test_flip_0(self): + self.apply(lambda x: x.flip((True, False))) + + def test_flip_1(self): + self.apply(lambda x: x.flip((False, True))) + + def test_flip_01(self): + self.apply(lambda x: x.flip((True, True))) + + def test_slice_0(self): + self.apply(lambda x: x.shrink(((1, x.shape[0]), (0, x.shape[1])))) + + def test_slice_1(self): + self.apply(lambda x: x.shrink(((0, x.shape[0]), (1, x.shape[1])))) + + def test_slice_1c1(self): + self.apply(lambda x: x.shrink(((0, 1), (0, 1)))) + + def test_slice_1c2(self): + self.apply(lambda x: x.shrink(((1, 2), (1, 2)))) + + def test_double_permute(self): + self.apply(lambda x: x.permute((1, 0))) + self.apply(lambda x: x.permute((1, 0))) + + def test_slice_permute(self): + self.apply(lambda x: x.shrink(((0, 2), (2, 4)))) + self.apply(lambda x: x.permute((1, 0))) + + def test_slice_expand(self): + self.apply(lambda x: x.shrink(((0, 2), (3, 4)))) + self.apply(lambda x: x.expand((2, 10))) + + def test_double_flip(self): + self.apply(lambda x: x.flip((True, False))) + self.apply(lambda x: x.flip((True, False))) + + def test_flip(self): self.apply(lambda x: x.flip((True, False))) + def test_flip2(self): self.apply(lambda x: x.flip((False, True))) + def test_flip3(self): self.apply(lambda x: x.flip((True, True))) + + def test_reshape_then_permute(self): + self.test_reshape() + self.test_permute() + + def test_reshape_then_expand(self): + self.test_reshape() + self.test_expand() + + def test_permute_then_reshape(self): + self.test_permute() + self.test_reshape() + + def test_expand_then_reshape(self): + self.test_expand() + self.test_reshape() + + def test_combo(self): + self.test_permute() + self.test_reshape() + self.test_slice_1() + self.test_expand() + self.test_permute() + +class TestShapeTrackerSize(unittest.TestCase): + def test_simple_size(self): + st = ShapeTracker.from_shape((100, 100)) + self.assertEqual(st.real_size(), 100*100) + + def test_0_in_shape_size(self): + st = ShapeTracker.from_shape((0, 100)) + self.assertEqual(st.real_size(), 0) + st = ShapeTracker.from_shape((100, 0)) + self.assertEqual(st.real_size(), 0) + + def test_expand_size(self): + st = ShapeTracker.from_shape((100, 100)) + st = st.reshape((100, 100, 1)) + st = st.expand((100, 100, 100)) + self.assertEqual(st.real_size(), 100*100) + + def test_expand_size_flatten(self): + st = ShapeTracker.from_shape((100, 100)) + st = st.reshape((100, 100, 1)) + st = st.expand((100, 100, 100)) + st = st.reshape((100*100*100,)) + self.assertEqual(st.real_size(), 100*100) + + def test_shrink_size_axis_0(self): + st = ShapeTracker.from_shape((100, 100)) + st = st.shrink(((0, 50), (0, 100))) + self.assertEqual(st.real_size(), 50*100) + + def test_shrink_size_axis_0_variable(self): + st = ShapeTracker.from_shape((100, 100)) + st = st.shrink(((0, Variable("a", 0, 50)), (0, 100))) + self.assertEqual(st.real_size(), 50*100) + + def test_shrink_size_axis_1(self): + st = ShapeTracker.from_shape((100, 100)) + st = st.shrink(((0, 100), (0, 50))) + self.assertEqual(st.real_size(), 9950) # careful here + + def test_size_variable(self): + st = ShapeTracker(views=(View(shape=(1, 1, 1, (Variable('start_pos', 0, 8192)+1), 1, 8, 4, 128), strides=(0, 0, 0, 1024, 0, 128, 0, 1), + offset=0, mask=None, contiguous=False), View(shape=(1, 32, 1, (Variable('start_pos', 0, 8192)+1), 128), + strides=(0, 128, 0, 4096, 1), offset=0, mask=None, contiguous=False))) + self.assertEqual(st.real_size(), 8389632) + + def test_pad_size_simple(self): + st = ShapeTracker.from_shape((10,)).pad(((2,4),)) + self.assertEqual(st.real_size(), 10) + + def test_pad_size_multiview(self): + st = ShapeTracker.from_shape((10,10)).pad(((2,4), (3,1))).reshape((16*14,)) + self.assertEqual(st.real_size(), 100) + + def test_flip_size(self): + st = ShapeTracker.from_shape((10,10)).pad(((2,4), (3,1))).flip((True, True)) + self.assertEqual(st.real_size(), 100) + +class TestConsecutive(unittest.TestCase): + @classmethod + def setUpClass(self): + from tinygrad.tensor import Tensor # easier test setup + self.t = Tensor([[1, 2, 3, 4], [5, 6, 7, 8]]) + self.const = Tensor(2) + self.ones = Tensor.ones(2, 4) + + def test_unmodified(self): + assert self.t.uop.st.consecutive + assert self.t.reshape(4, 2).uop.st.consecutive + assert self.t.reshape(1, 8).uop.st.consecutive + + def test_sliced(self): + assert self.t[0].uop.st.consecutive + assert self.t[0, 1:2].uop.st.consecutive + assert self.t[1].uop.st.consecutive + assert not self.t[:, 0].uop.st.consecutive + assert not self.t[:, 1].uop.st.consecutive + + def test_padded(self): + assert not self.t.pad(((1, 1), None)).uop.st.consecutive + assert not self.t.pad((None, (1, 1))).uop.st.consecutive + + def test_const(self): + assert self.const.uop.st.consecutive + + def test_ones(self): + assert not self.ones.uop.st.consecutive + assert not self.ones[0, :].uop.st.consecutive + # consecutive if sliced into size 1 + assert self.ones[0, 0].uop.st.consecutive + +class TestRender(unittest.TestCase): + def test_render(self): + st = ShapeTracker.from_shape((2, 3)) + idx, valid = st.to_indexed_uops() + self.assertEqual(idx.render(), "((ridx0*3)+ridx1)") + self.assertEqual(valid.render(), "True") + + st = st.pad(((0, 1), (0, 0))) + idx, valid = st.to_indexed_uops() + self.assertEqual(idx.render(), "((ridx0*3)+ridx1)") + self.assertEqual(valid.render(), "(ridx0<2)") + +class TestVariableReshape(unittest.TestCase): + def test_reshape(self): + st = ShapeTracker.from_shape((3,)) + st = st.reshape((Variable("i", 1, 10),)) + assert len(st.views) == 1 + + def test_reshape_stride_0(self): + st = ShapeTracker.from_shape((3,), (0,)) + st = st.reshape((Variable("i", 1, 10).bind(3),)) + assert len(st.views) == 1, f"multiview {st}" + + def test_reshape_bound(self): + st = ShapeTracker.from_shape((3,)) + st = st.reshape((Variable("i", 1, 10).bind(3),)) + assert len(st.views) == 1 + + def test_add(self): + st1 = ShapeTracker.from_shape((3,)) + st2 = ShapeTracker.from_shape((Variable("i", 1, 10),)) + st = st1+st2 + assert len(st.views) == 1 + + def test_add_stride_0(self): + st1 = ShapeTracker.from_shape((3,), (0,)) + st2 = ShapeTracker.from_shape((Variable("i", 1, 10).bind(3),), (0,)) + st = st1+st2 + assert len(st.views) == 1, f"multiview {st}" + + def test_add_bound(self): + st1 = ShapeTracker.from_shape((3,)) + st2 = ShapeTracker.from_shape((Variable("i", 1, 10).bind(3),)) + st = st1+st2 + assert len(st.views) == 1 + + def test_simplify(self): + st1 = ShapeTracker.from_shape((3,)) + st2 = ShapeTracker.from_shape((Variable("i", 1, 10).bind(3),)) + st = ShapeTracker((st1.views[0], st2.views[0])) + st = st.simplify() + assert len(st.views) == 1 + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_shapetracker_math.py b/tinygrad_repo/test/unit/test_shapetracker_math.py new file mode 100644 index 000000000..efd017f50 --- /dev/null +++ b/tinygrad_repo/test/unit/test_shapetracker_math.py @@ -0,0 +1,178 @@ +import unittest +from tinygrad.helpers import prod +from tinygrad.shape.view import View +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad import Variable +from test.unit.test_shapetracker import shapetracker_getitem + +class MultiShapeTracker: + def __init__(self, sts:list[ShapeTracker]): self.sts = sts + @property + def shape(self): return self.sts[0].shape + def reshape(self, arg): self.sts = [x.reshape(arg) for x in self.sts] + def permute(self, arg): self.sts = [x.permute(arg) for x in self.sts] + def expand(self, arg): self.sts = [x.expand(arg) for x in self.sts] + def shrink(self, arg): self.sts = [x.shrink(arg) for x in self.sts] + def flip(self, arg): self.sts = [x.flip(arg) for x in self.sts] + def pad(self, arg): self.sts = [x.pad(arg) for x in self.sts] + +def st_equal(st1:ShapeTracker, st2:ShapeTracker) -> bool: + if st1.shape != st2.shape: return False + if st1 == st2: return True + for i in range(0, prod(st1.shape)): + st1_off, st1_v = shapetracker_getitem(st1, i) + st2_off, st2_v = shapetracker_getitem(st2, i) + if st1_v != st2_v or (st1_off != st2_off and st1_v): + print(f"ST MISMATCH @ {i}, {st1_v=} != {st2_v=}, {st1_off=} != {st2_off=}") + print(st1) + print(st2) + return False + return True + +class TestShapeTrackerBasics(unittest.TestCase): + def test_pad_shrink_removes_mask(self): + a = ShapeTracker.from_shape((10, 10)) + a = a.pad(((0,2), (0,2))) + a = a.shrink(((0,10), (0,10))) + assert len(a.views) == 1 and a.views[-1].mask is None + + def test_pad_shrink_leaves_mask(self): + a = ShapeTracker.from_shape((10, 10)) + a = a.pad(((0,2), (0,2))) + a = a.shrink(((0,10), (0,11))) + assert len(a.views) == 1 and a.views[-1].mask is not None + + def test_reshape_makes_same(self): + a = ShapeTracker.from_shape((2, 5)) + x = a.pad( ((2, 0), (0, 0)) ) + x = x.reshape( (2, 2, 5) ) + x1 = x.reshape( (4, 5) ) + x1 = x1.reshape( (2, 2, 5) ) + assert x == x1.simplify() + + def test_simplify_is_correct(self): + multiv = ShapeTracker(views=(View(shape=(15, 3), strides=(9, 1), offset=6, mask=None, contiguous=False), + View(shape=(4, 3), strides=(12, 4), offset=0, mask=None, contiguous=False))) + assert st_equal(multiv, multiv.simplify()) + +class TestShapeTrackerAdd(unittest.TestCase): + def test_simple_add_reshape(self): + a = ShapeTracker.from_shape((10, 10)) + a = a.reshape((100,)) + b = ShapeTracker.from_shape((100,)) + assert a+b == b + + def test_simple_add_permute(self): + a = ShapeTracker.from_shape((10, 10)) + a = a.permute((1,0)) + b = ShapeTracker.from_shape((10, 10)) + b = b.permute((1,0)) + assert a+b == ShapeTracker.from_shape((10, 10)) + + def test_plus_real1(self): + st = MultiShapeTracker([ShapeTracker.from_shape((15, 9))]) + st.shrink( ((0, 15), (6, 9)) ) + backup = st.sts[0] + st.sts.append(ShapeTracker.from_shape(backup.shape)) + st.reshape( (45,) ) + st.flip( (True,) ) + st.reshape( (15, 3) ) + assert st_equal(backup + st.sts[1], st.sts[0]) + + def test_off_by_one(self): + st1 = ShapeTracker(views=(View(shape=(5,), strides=(1,), offset=0, mask=None, contiguous=True), + View(shape=(5,), strides=(1,), offset=0, mask=None, contiguous=True))) + st2 = ShapeTracker(views=(View(shape=(4,), strides=(1,), offset=0, mask=None, contiguous=True), + View(shape=(5,), strides=(1,), offset=0, mask=None, contiguous=True))) + assert not (st_equal(st1, st2)) + +class TestShapeTrackerAddVariable(unittest.TestCase): + def test_self_add(self): + j = Variable("j", 0, 20).bind(10) + a = ShapeTracker.from_shape((10,10)) + x = a.reshape((10, j)) + out = x + x + assert out == x + + def test_self_add_reshape(self): + j = Variable("j", 0, 20).bind(10) + a = ShapeTracker.from_shape((10,10)) + x = a.reshape((10, j)) + out = x.reshape((5, 2, j)) + x + assert out == x + + def test_merge_symbolic_views(self): + var_i = Variable('i', 1, 10) + var_j = Variable('i', 1, 10) + vm1 = View(shape=(var_i, var_j, 3), strides=(3, 0, 1), offset=0, mask=None, contiguous=False) + vm2 = View(shape=(var_i, var_j, 3), strides=(var_j*3, 3, 1), offset=0, mask=None, contiguous=True) + ShapeTracker((vm1,)) + ShapeTracker((vm2,)) + + def test_merge_symbolic_views_2(self): + var_i = Variable('i', 1, 10) + var_j = Variable('j', 1, 10) + vm1 = View(shape=(var_i, var_j), strides=(0, 0), offset=0, mask=None, contiguous=False) + vm2 = View(shape=(var_i, var_j), strides=(var_j, 1), offset=0, mask=None, contiguous=True) + ret = (ShapeTracker((vm1,)) + ShapeTracker((vm2,))).reshape((var_i, var_j, 1)) + ret_2 = ShapeTracker((vm1,)) + ShapeTracker((vm2,)).reshape((var_i, var_j, 1)) + assert ret == ret_2 + +class TestShapeTrackerInvert(unittest.TestCase): + def test_invert_reshape(self): + a = ShapeTracker.from_shape((10, 10)) + x = a.reshape((5, 20)) + ap = ShapeTracker.from_shape(x.shape) + x.invert(a.shape) + assert ap == a, f"{ap} != {a}" + + def test_invert_permute(self): + a = ShapeTracker.from_shape((5, 20)) + x = a.permute((1,0)) + ap = x + x.invert(a.shape) + assert ap == a, f"{ap} != {a}" + + def test_invert_permute_3(self): + a = ShapeTracker.from_shape((8, 4, 5)) + x = a.permute((1,2,0)) + ap = x + x.invert(a.shape) + assert ap == a, f"{ap} != {a}" + + def test_invert_real1(self): + a = ShapeTracker.from_shape((3, 6, 10)) + x = a.reshape( (3, 3, 2, 10) ) + x = x.permute( (2, 1, 3, 0) ) + ap = x + x.invert(a.shape) + assert ap == a, f"{ap} != {a}" + + def test_cant_invert_expand(self): + a = ShapeTracker.from_shape((10, 1)) + x = a.expand((10,10)) + assert x.invert(a.shape) is None + + def test_cant_invert_shrink(self): + a = ShapeTracker.from_shape((10, 10)) + x = a.shrink(((0,10),(2,8))) + assert x.invert(a.shape) is None + + def test_can_invert_flip(self): + a = ShapeTracker.from_shape((20, 10)) + x = a.flip((True,False)) + ap = x + x.invert(a.shape) + assert st_equal(ap, a) + + def test_can_invert_flip_permute(self): + a = ShapeTracker.from_shape((20, 10)) + x = a.permute((1,0)) + x = x.flip((True,False)) + ap = x + x.invert(a.shape) + assert st_equal(ap, a) + + def test_invert_failure(self): + a = ShapeTracker.from_shape((2, 5)) + x = a.pad( ((2, 0), (0, 0)) ) + x = x.reshape( (2, 2, 5) ) + x = x.reshape( (4, 5) ) + ap = x + x.invert(a.shape) + assert st_equal(ap, a) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_shm_tensor.py b/tinygrad_repo/test/unit/test_shm_tensor.py new file mode 100644 index 000000000..6c9ab2486 --- /dev/null +++ b/tinygrad_repo/test/unit/test_shm_tensor.py @@ -0,0 +1,38 @@ +import unittest +import multiprocessing.shared_memory as shared_memory +from tinygrad.helpers import CI +from tinygrad.tensor import Tensor, Device +import numpy as np + +class TestRawShmBuffer(unittest.TestCase): + def test_e2e(self): + t = Tensor.randn(2, 2, 2).realize() + + # copy to shm + shm_name = (s := shared_memory.SharedMemory(create=True, size=t.nbytes())).name + s.close() + t_shm = t.to(f"disk:shm:{shm_name}").realize() + + # copy from shm + t2 = t_shm.to(Device.DEFAULT).realize() + + assert np.allclose(t.numpy(), t2.numpy()) + s.unlink() + + @unittest.skipIf(CI, "CI doesn't like big shared memory") + def test_e2e_big(self): + t = Tensor.randn(2048, 2048, 8).realize() + + # copy to shm + shm_name = (s := shared_memory.SharedMemory(create=True, size=t.nbytes())).name + s.close() + t_shm = t.to(f"disk:shm:{shm_name}").realize() + + # copy from shm + t2 = t_shm.to(Device.DEFAULT).realize() + + assert np.allclose(t.numpy(), t2.numpy()) + s.unlink() + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/unit/test_simple_schedule.py b/tinygrad_repo/test/unit/test_simple_schedule.py new file mode 100644 index 000000000..baf6caef5 --- /dev/null +++ b/tinygrad_repo/test/unit/test_simple_schedule.py @@ -0,0 +1,15 @@ +import unittest +from tinygrad import Tensor +from tinygrad.uop.ops import Ops + +class TestSimpleSchedule(unittest.TestCase): + def test_reduce_doesnt_split(self): + a = Tensor.empty(16,16).sum(axis=1) + a1 = a.reshape(4,4) + a2 = a.reshape(16,1,1) + Tensor.kernelize(a1, a2) + kernels = [x for x in a1.uop.sink(a2.uop).toposort() if x.op is Ops.KERNEL] + self.assertEqual(len(kernels), 1) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_simplify_valid_idx.py b/tinygrad_repo/test/unit/test_simplify_valid_idx.py new file mode 100644 index 000000000..8ef89d56b --- /dev/null +++ b/tinygrad_repo/test/unit/test_simplify_valid_idx.py @@ -0,0 +1,416 @@ +import unittest, itertools + +from tinygrad.codegen import full_rewrite_to_sink +from tinygrad.dtype import dtypes +from tinygrad.uop.ops import UOp, Ops +from tinygrad.uop.symbolic import simplify_valid + +def get_gated_load_uop(valid:UOp, idx:UOp): + return UOp(Ops.LOAD, dtypes.float, ( + UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), arg=0).index(idx, valid), + UOp.const(dtypes.float, 0.0) + )) + +def get_load_image_uop(image_shape:tuple[int, ...], valid:UOp, idx:tuple[UOp, UOp]): + return UOp(Ops.LOAD, dtypes.float.vec(4), ( + UOp(Ops.DEFINE_GLOBAL, dtypes.imagef(image_shape), arg=0).index(UOp(Ops.VECTORIZE, dtypes.int.vec(2), idx), valid), + UOp(Ops.VECTORIZE, dtypes.float.vec(4), src=(UOp.const(dtypes.float, 0.0),) * 4) + )) + +def Special(expr, nmax): return UOp(Ops.SPECIAL, dtypes.int, (), (expr, nmax)) +def Variable(expr, nmin, nmax): return UOp.variable(expr, nmin, nmax) +def Range(n, nmax): return UOp(Ops.RANGE, dtypes.int, arg=n, src=(UOp.const(dtypes.int, nmax),)) + +class TestHelpers(unittest.TestCase): + def test_is_increasing(self): + idx1 = Special("idx1", 32) + idx2 = Special("idx2", 64) + ridx0 = Variable("ridx0", 0, 5) + ridx1 = Variable("ridx1", 0, 2) + ridx2 = Variable("ridx2", 0, 2) + # (ridx0+(idx1*48)+(ridx2*6)+(-6)),((idx2*2)+ridx1+(-1))) + f0 = ((idx1*24)+(ridx2*3)+ridx0+765)%768 + f1 = ridx0+(idx1*48)+(ridx2*6)+(-6) + f2 = (idx2*2)+ridx1+((idx1+((ridx2+7)//8)+31)//32)+(-2) + f3 = (idx2*2)+ridx1+(-1) + + self.assertFalse(f0.is_increasing()) + self.assertTrue(f1.is_increasing()) + self.assertTrue(f2.is_increasing()) + self.assertTrue(f3.is_increasing()) + + rng = UOp(Ops.RANGE, dtypes.int, arg=(2, True), src=(UOp(Ops.CONST, dtypes.int, arg=5, src=()),)) + self.assertTrue(rng.is_increasing()) + self.assertTrue((rng+2).is_increasing()) + +class TestValidIdxSimplification(unittest.TestCase): + def check(self, load, sidx, svalid): + load = full_rewrite_to_sink(load.sink()).src[0] + idx, valid = load.src[0].src[1], load.src[0].src[2] + self.assertEqual(idx.render(simplify=False), sidx) + self.assertEqual(valid.render(simplify=False), svalid) + + def test_cumsum(self): + gidx0 = Special("gidx0", 5) + lidx0 = Special("lidx0", 4) + gate = (gidx0*4+lidx0<19).ne(True) + idx = gidx0*4+lidx0-19 + load = get_gated_load_uop(gate, idx) + self.check(load, + "0", + "(((lidx0+(gidx0*4))<19)!=True)") + + def test_simplify_within_valid1(self): + ridx0 = Range(0, 4) + ridx1 = Range(1, 4) + ridx2 = Range(2, 4) + ridx3 = Range(3, 4) + valid = ((ridx0*3+ridx1)<8) & ((((ridx0*3+ridx1)//8+ridx2*3+ridx3)%4)<2) + idx = ridx0+ridx1+ridx2+ridx3 + load = get_gated_load_uop(valid, idx) + self.check(load, + "(((ridx0+ridx1)+ridx2)+ridx3)", + "((((ridx0*3)+ridx1)<8)&((((ridx2*3)+ridx3)%4)<2))") + + def test_simplify_within_valid2(self): + gidx0 = Special("gidx0", 56) + ridx0 = Range(0, 3) + alu0 = gidx0+ridx0 + valid = (alu0 < 57) & (alu0 >= 1) + self.assertIsNone(simplify_valid(valid)) + + def test_valid_order_matters1(self): + ridx0 = Range(0, 2) + v0 = ridx0<1 + v1 = ((ridx0*5+1)%6)<5 + self.assertEqual(simplify_valid(v0&v1).render(), "(ridx0<1)") + self.assertEqual(simplify_valid(v1&v0).render(), "(ridx0<1)") + + def test_valid_order_matters2(self): + gidx0 = Special("gidx0", 13) + gidx1 = Special("gidx1", 13) + ridx0 = Range(0, 4) + alu0 = (gidx1+(ridx0*13)) + v0 = (gidx0+11)%14<11 + v1 = (alu0+((gidx0+39)//42))%14<11 + v2 = gidx0<3 + v3 = alu0<42 + + for v in itertools.permutations([v0,v1,v2,v3]): + self.assertEqual(simplify_valid(v[0]&v[1]&v[2]&v[3]).render(), "False") + + def test_simplify_valid_from_div(self): + x = Variable("x", -100, 100) + valid = ((x<0)&((100%x).cast(dtypes.bool))) + self.assertIsNone(simplify_valid(valid)) + + @unittest.expectedFailure # TODO: fix + def test_from_merge_views(self): + # taken from test_merges_from_fuzzer1 + # generated by + # v0 = View(shape=(2, 4), strides=(2, 1), offset=-2, mask=((0, 2), (2, 4)), contiguous=False) + # v1 = View(shape=(2, 4, 2, 2), strides=(4, 0, -2, -1), offset=3, mask=None, contiguous=False) + # s = ShapeTracker((v0, v1)) + # idx, valid = s.to_indexed_uops() + # print(f"{idx.render()=}") + # print(f"{valid.render()=}") + + # s = ShapeTracker((View(shape=(2, 4, 2, 2), strides=(2, 0, 0, -1), offset=1, mask=((0, 2), (0, 4), (0, 1), (0, 2)), contiguous=False),)) + # idx, valid = s.to_indexed_uops() + # print(f"{idx.render()=}") + # print(f"{valid.render()=}") + ridx0 = Range(0, 2) + ridx2 = Range(2, 2) + ridx3 = Range(3, 2) + idx = (((ridx0*2)+((((ridx2*2)+(ridx3*3))+3)%4))+-2) + valid = ((((((ridx2*2)+(ridx3*3))+3)%4)<2)!=True) # noqa: E712 + load = get_gated_load_uop(valid, idx) + self.check(load, + "(((ridx0*2)+(ridx3*-1))+1)", + "(ridx2<1)") + + def test_load_in_valid(self): + # from FUSE_ARANGE=1 python test/test_ops.py TestOps.test_scatter_add + # can lead to OOB + ridx2 = Range(2, 4) + lidx0 = Special("lidx0", 3) + gidx0 = Special("gidx0", 2) + idx=(((lidx0+(gidx0*3))+(ridx2*5))+40) + valid = (lidx0+(gidx0*3)) < 5 + val7 = get_gated_load_uop(valid, idx) + valid2 = valid & val7.cast(dtypes.bool).logical_not() + self.assertIsNone(simplify_valid(valid2)) + + def test_valid_becomes_const1(self): + # from DSP mobilenetv2 + ridx0 = Range(0, 30) + ridx1 = Range(1, 7) + ridx2 = Range(2, 2) + alu11 = (ridx1+ridx2) + alu15 = ((alu11+1)//7) + idx = (alu15*-31)+(((((alu11+218)//224)+ridx0)%30)*1568) + valid = (ridx2<1)&(ridx1<6) + load = get_gated_load_uop(valid, idx) + self.check(load, + "(ridx0*1568)", + "((ridx2<1)&(ridx1<6))") + + def test_valid_becomes_const1_z3(self): + from z3 import Ints, Solver, And, If, Not, unsat + ridx0, ridx1, ridx2, alu11, alu15 = Ints('ridx0 ridx1 ridx2 alu11 alu15') + alu11 = (ridx1+ridx2) + alu15 = ((alu11+1)/7) + idx = (alu15*-31)+(((((alu11+218)/224)+ridx0)%30)*1568) + valid = (ridx2<1)&(ridx1<6) + load = If(valid, idx, 0) + + # correct simplification + s = Solver() + s.add(And(0<=ridx0, ridx0<30, 0<=ridx1, ridx1<7, 0<=ridx2, ridx2<2)) + simplifed_idx = (ridx0*1568) + simplifed_load = If(valid, simplifed_idx, 0) + s.add(Not(load == simplifed_load)) # Check if they are NOT equivalent + assert s.check() == unsat, f"The expressions are not equivalent. {s.model()=}" + + # new solver for a wrong simplified expression + s = Solver() + s.add(And(0<=ridx0, ridx0<30, 0<=ridx1, ridx1<7, 0<=ridx2, ridx2<2)) + wrong_simplifed_idx = (ridx0*1567)+ridx1 + wrong_simplifed_load = If(valid, wrong_simplifed_idx, 0) + s.add(Not(load == wrong_simplifed_load)) # Check if they are NOT equivalent + assert s.check() != unsat, "The expressions are equivalent??" + print("The expressions are not equivalent.") + print(s.model()) + + @unittest.expectedFailure # TODO: improve uop_given_valid + def test_valid_becomes_const2(self): + ridx0 = Range(0, 4) + ridx1 = Range(1, 4) + ridx2 = Range(2, 4) + ridx3 = Range(3, 4) + idx= ((ridx0+ridx1+ridx2+ridx3+28)//30) + valid = ((ridx0+ridx1)<1).ne(True) & ((ridx2+ridx3)<1).ne(True) + load = get_gated_load_uop(valid, idx) + self.check(load, + "1", + "((((ridx0+ridx1)<1)!=True)&(((ridx2+ridx3)<1)!=True))") + +class TestImageSimplification(unittest.TestCase): + def check(self, load, svalid, sidx0, sidx1): + load = full_rewrite_to_sink(load.sink()).src[0] + idx = load.src[0].src[1] + self.assertEqual(idx.op, Ops.VECTORIZE) + self.assertEqual(len(idx.src), 2) + idx0, idx1 = idx.src[0], idx.src[1] + self.assertEqual(idx0.render(simplify=False), sidx0) + self.assertEqual(idx1.render(simplify=False), sidx1) + if svalid is not None: + self.assertEqual(load.src[0].src[2].render(simplify=False), svalid) + else: + self.assertEqual(len(load.src[0].src), 2, "svalid is None but load still has a valid") + + def test_idx_gt_c(self): + # (idx1 < c+1).ne(True) ? (..., idx1-1+c) : 0 can drop the valid + # (idx1 < c+1).ne(True) -> idx > c + gidx0 = Special("gidx0", 32) + gidx1 = Special("gidx1", 32) + shape = (10, 10, 4) + load = get_load_image_uop(shape, (gidx1<1).ne(True), (gidx0, gidx1-1)) + self.check(load, None, "gidx0", "(gidx1+-1)") + load = get_load_image_uop(shape, (gidx1<1).ne(True), (gidx0, gidx1-2)) + self.check(load, None, "gidx0", "(gidx1+-2)") + + # should match any one of the AND clause and drop the matched statement from valid + valid = (gidx0<1).ne(True) & (gidx1<1).ne(True) + load = get_load_image_uop(shape, valid, (gidx0+1, gidx1-1)) + self.check(load, "((gidx0<1)!=True)", "(gidx0+1)", "(gidx1+-1)") + + valid = (gidx0<1).ne(True) & (gidx1<1).ne(True) + load = get_load_image_uop(shape, valid, (gidx0, gidx1-1)) + self.check(load, "((gidx0<1)!=True)", "gidx0", "(gidx1+-1)") + + def test_idx_lt_bound(self): + # (idx1 < image_bound) ? (..., idx1) : 0 can drop the valid + gidx0 = Special("gidx0", 32) + gidx1 = Special("gidx1", 32) + load = get_load_image_uop((10, 10, 4), gidx1<10, (gidx0, gidx1)) + self.check(load, None, "gidx0", "gidx1") + + # same thing, valid has a div + load = get_load_image_uop((10, 10, 4), gidx1//2<5, (gidx0, gidx1)) + self.check(load, None, "gidx0", "gidx1") + + # 10x20 image, not out of bound + load = get_load_image_uop((20, 10, 4), gidx1<10, (gidx0, gidx1)) + self.check(load, "(gidx1<10)", "gidx0", "gidx1") + + def test_generic_idx_lt_bound(self): + # (idx1 < image_bound - c) ? (..., idx1 + c) : 0 can drop the valid + gidx0 = Special("gidx0", 32) + gidx1 = Special("gidx1", 32) + shape = (10, 10, 4) + load = get_load_image_uop(shape, (gidx1<8), (gidx0, gidx1+2)) + self.check(load, None, "gidx0", "(gidx1+2)") + + load = get_load_image_uop(shape, (gidx1<5), (gidx0, gidx1+5)) + self.check(load, None, "gidx0", "(gidx1+5)") + + def test_valid_empty_set(self): + gidx0 = Special("gidx0", 32) + gidx1 = Special("gidx1", 32) + shape = (32, 32, 4) + idx = (gidx0%2, gidx1+2) + # not empty + load = get_load_image_uop(shape, gidx0<8, idx) + self.check(load, "(gidx0<8)", "(gidx0%2)", "(gidx1+2)") + + # empty -> invalid + load = get_load_image_uop(shape, (gidx0<8) & (gidx0<8).ne(True), idx) + load = full_rewrite_to_sink(load.sink()).src[0] + self.assertEqual(load.op, Ops.VECTORIZE) + self.assertEqual(load.dtype.count, 4) + + def test_openpilot_conv1(self): + # first conv in openpilot + # kernel in tinygrad ae5d1407ee844a97a52ad3756835d38e7e2b9e1b https://gist.github.com/chenyuxyz/39c2d4e9a076b46731c67d345ff066b6 + idx1 = Special("idx1", 32) + idx2 = Special("idx2", 64) + # ridx0 = Variable("ridx0", 0, 5) + # ridx1 = Variable("ridx1", 0, 2) + # ridx2 = Variable("ridx2", 0, 2) + ridx0 = Range(0, 6) + ridx1 = Range(1, 3) + ridx2 = Range(2, 3) + + alu1 = ((idx2*2)+ridx1) + alu4 = ((idx1*48)+(ridx2*6)+ridx0) + + valid = ((((idx2*2)+(ridx1))<1).ne(True))&((((idx1*8)+(ridx2))<1).ne(True)) + shape = (128, 1536, 4) + idx = ((alu4+1530)%1536, alu1+((idx1+((ridx2+7)//8)+31)//32)+(-2)) + + load = get_load_image_uop(shape, valid, idx) + self.check(load, None, "((((idx1*48)+(ridx2*6))+ridx0)+-6)", "(((idx2*2)+ridx1)+-1)") + + def test_openpilot_conv2(self): + # conv in test/external/external_test_valid_remove.py + idx1 = Special("idx1", 32) + idx2 = Special("idx2", 64) + # ridx0 = Variable("ridx0", 0, 2) + # ridx1 = Variable("ridx1", 0, 2) + # ridx2 = Variable("ridx2", 0, 2) + ridx0 = Range(0, 3) + ridx1 = Range(1, 3) + ridx2 = Range(2, 3) + + alu1 = ((idx2*2)+ridx1) + alu3 = ((idx1*24)+(ridx2*3)+ridx0) + + valid = ((((idx2*2)+ridx1)<1).ne(True))&((((idx1*8)+ridx2)<1).ne(True)) + shape = (128, 768, 4) + idx = ((alu3+765)%768, alu1+((idx1+((ridx2+7)//8)+31)//32)+(-2)) + load = get_load_image_uop(shape, valid, idx) + + self.check(load, None, "((((idx1*24)+(ridx2*3))+ridx0)+-3)", "(((idx2*2)+ridx1)+-1)") + + def test_openpilot_conv3(self): + # in openpilot 0.9.7 + idx0 = Special("idx0", 64) + idx1 = Special("idx1", 2) + idx2 = Special("idx2", 4) + ridx0 = Range(0, 7) + ridx1 = Range(1, 7) + + alu2 = ((idx2*2)+ridx0) + alu4 = ((idx1*8)+ridx1) + alu6 = ((idx1*512)+(ridx1*64)+idx0) + + valid = (alu2<11)&(alu4<3).ne(True) + shape = (8, 1024, 4) + idx = (((alu6+832)%1024),(alu2+((idx1+((ridx1+5)//8)+1)//2)+(-4))) + + load = get_load_image_uop(shape, valid, idx) + + self.check(load, + "((((idx2*2)+ridx0)<11)&((((idx1*8)+ridx1)<3)!=True))", + "(((idx0+((idx1*512)+(ridx1*64)))+832)%1024)", + "((((idx2*2)+ridx0)+(((idx1+((ridx1+5)//8))+1)//2))+-4)") + + def test_simplify1(self): + # idx has the form (A % m, A // m + k) and valid has (c0 < A) and (A < c1) + gidx = Special("gidx", 512) + valid = (gidx<488) & (gidx<480).ne(True) + idx = ((gidx*3+18)%26, (gidx*3+18)//26-56) + load = get_load_image_uop((1, 26, 4), valid, idx) + self.check(load, None, "((gidx*3)+-1438)", "0") + + def test_simplify2(self): + # from GPU=1 DEBUG=4 FORWARD_ONLY=1 IMAGE=2 python3 test/test_ops.py TestOps.test_simple_padding_conv2d + lidx = Special("lidx", 4) + valid = (lidx<3) & (lidx<1).ne(True) + idx = ((lidx+1)%2, (lidx+1)//2-1) + load = get_load_image_uop((1, 2, 4), valid, idx) + self.check(load, None, "(lidx+-1)", "0") + + def test_simplify3(self): + # from openpilot + idx0 = Special("idx0", 265) + valid = (idx0<201).ne(True) + idx = ((idx0+55)%64, (idx0+55)//64-4) + load = get_load_image_uop((1, 64, 4), valid, idx) + self.check(load, None, "(idx0+-201)", "0") + + def test_simplify4(self): + idx0 = Special("idx0", 512) + shape = (4, 64, 4) + alu2 = ((idx0*4+1)%32) + alu3 = ((idx0*4+2)%32) + alu4 = ((idx0*4+3)%32) + alu5 = (idx0*4%32) + alu8 = (idx0//8%32//4) + alu9 = idx0<256 + + # TODO: can this be simplified further? + load = get_load_image_uop(shape, alu9, (((alu8+(alu2*8))%64),(alu2//8))) + self.check(load, "(idx0<256)", "(((((idx0%8)*32)+(idx0//32))+8)%64)", "((idx0%8)//2)") + + load = get_load_image_uop(shape, alu9, (((alu8+(alu3*8))%64),(alu3//8))) + self.check(load, "(idx0<256)", "(((((idx0%8)*32)+(idx0//32))+16)%64)", "((idx0%8)//2)") + + load = get_load_image_uop(shape, alu9, (((alu8+(alu4*8))%64),(alu4//8))) + self.check(load, "(idx0<256)", "(((((idx0%8)*32)+(idx0//32))+24)%64)", "((idx0%8)//2)") + + load = get_load_image_uop(shape, alu9, (((alu8+(alu5*8))%64),(alu5//8))) + self.check(load, "(idx0<256)", "((((idx0%8)*32)+(idx0//32))%64)", "((idx0%8)//2)") + + def test_simplify5(self): + # openpilot 0.9.7, chunk replacement to simplify + shape = (10, 384, 4) + idx0 = Special("idx0", 16) + idx1 = Special("idx1", 24) + alu0 = idx0*4 + alu1 = (idx1*256)+alu0 + alu2 = idx1//3 + alu3 = ((alu1+1)%768) + idx = ((idx0+((((alu3//640)+alu2)%8)*16)+128),((alu3//64)%10)) + valid = alu3<640 + + load = get_load_image_uop(shape, valid, idx) + self.check(load, "(((idx0+(idx1*64))%192)<160)", "((idx0+((idx1//3)*16))+128)", "(((idx0+(idx1*64))%192)//16)") + + def test_simplify6(self): + # from openpilot + # the valid implies the numerator of the div/mod is positive and can be simplified with floordiv rules + idx1 = Special("idx1", 16) + idx2 = Special("idx2", 64) + ridx3 = Range(3, 3) + ridx4 = Range(4, 3) + ridx5 = Range(5, 3) + alu0 = ((idx2*1536)+(ridx4*768)+ridx3+(idx1*24)+(ridx5*3)+-771)%768 + alu1 = ((idx2*1536)+(ridx4*768)+ridx3+(idx1*24)+(ridx5*3)+-771)//768 + valid = (((idx2+ridx4)<1)!=1)&(((idx1+ridx5)<1)!=1) + load = get_load_image_uop((128, 768, 4), valid, (alu0, alu1)) + self.check(load, None, "((((idx1*24)+ridx3)+(ridx5*3))+-3)", "(((idx2*2)+ridx4)+-1)") + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_symbolic_failures.py b/tinygrad_repo/test/unit/test_symbolic_failures.py new file mode 100644 index 000000000..0fc5ee246 --- /dev/null +++ b/tinygrad_repo/test/unit/test_symbolic_failures.py @@ -0,0 +1,161 @@ +import unittest +from tinygrad import Variable, dtypes +from tinygrad.helpers import Context +from tinygrad.uop.ops import Ops, UOp + + +class TestFuzzFailure(unittest.TestCase): + def setUp(self): + self.context = Context(CORRECT_DIVMOD_FOLDING=1) + self.context.__enter__() + + def tearDown(self): + self.context.__exit__(None, None, None) + + def test_fuzz_failure1(self): + v1=Variable('v1', 0, 8) + v2=Variable('v2', 0, 2) + v3=Variable('v3', 0, 1) + expr = (((((((((((((((((((((((0//4)%2)//8)+-2)+-4)+-3)+v1)+-4)+v2)+-2)+v3)+v2)//3)%7)*1)//2)+v2)*-1)+2)+1)+0)+-3)+v3) + v1_val, v2_val, v3_val = v1.const_like(8), v2.const_like(0), v3.const_like(0) + num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + self.assertEqual(num, rn) + + def test_fuzz_failure2(self): + v1=Variable('v1', 0, 16) + v2=Variable('v2', 0, 5) + v3=Variable('v3', 0, 3) + expr = (((((((((((((((((((((((((0*4)//5)*2)*-1)*-2)+-4)*4)*2)*3)*4)+-4)*4)+v2)+v2)+v3)//3)+v2)+v1)//9)+3)+1)//1)+-4)//4)*2) + expr = (((((v1+(v2+(((v3+(v2*2))+1)//3)))+4)//9)+-57)//(9*4)) + v1_val, v2_val, v3_val = v1.const_like(6), v2.const_like(0), v3.const_like(0) + num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + self.assertEqual(num, rn) + + def test_fuzz_failure3(self): + v1=Variable('v1', 0, 2) + v2=Variable('v2', 0, 1) + v3=Variable('v3', 0, 2) + expr = (((((((((((((((((((0//2)//3)+v3)+0)+-4)*-2)*-2)+-1)+2)+3)+v3)+0)//8)*-3)+0)*-2)*-4)*-2)//5) + v1_val, v2_val, v3_val = v1.const_like(0), v2.const_like(0), v3.const_like(0) + num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + self.assertEqual(num, rn) + + def test_fuzz_failure4(self): + v1=Variable('v1', 0, 2) + v2=Variable('v2', 0, 3) + v3=Variable('v3', 0, 4) + expr = (((((((((((((((((((((((((((((0*-2)+0)*-1)//9)//6)//8)+v1)*-4)+v2)//4)//8)+4)*3)+v1)+v3)//8)//7)+4)+v3)*-4)+1)+v1)*3)+4)*2)//5)//2)//3)*-4) + v1_val, v2_val, v3_val = v1.const_like(2), v2.const_like(0), v3.const_like(2) + num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + self.assertEqual(num, rn) + + def test_fuzz_failure5(self): + v1=Variable('v1', 0, 1) + v2=Variable('v2', 0, 1) + v3=Variable('v3', 0, 3) + expr = ((((((((((((((0+v2)+v1)*0)+v2)//1)//7)+-2)+v2)+v1)*4)+-3)//5)+v2)+1) + v1_val, v2_val, v3_val = v1.const_like(0), v2.const_like(0), v3.const_like(0) + num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + self.assertEqual(num, rn) + + def test_fuzz_failure6(self): + v1=Variable('v1', 0, 8) + v2=Variable('v2', 0, 64) + v3=Variable('v3', 0, 128) + expr = (((((((((((((((((((((((((((((0//3)+4)+v1)//2)+-1)//1)*1)*-1)*4)//5)+v1)//6)+v1)*-1)+-4)+v2)+-2)*-3)+v3)+-4)+-2)*-1)//8)//4)*-4)+3)+v3)* + -2)+v2) + v1_val, v2_val, v3_val = v1.const_like(8), v2.const_like(3), v3.const_like(2) + num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + self.assertEqual(num, rn) + + def test_fuzz_failure7(self): + v1=Variable('v1', 0, 64) + v2=Variable('v2', 0, 5) + v3=Variable('v3', 0, 128) + expr = (((((((((((((((((((((((((((((0+v2)*-4)+0)//9)+-4)*-2)*3)*4)//9)+v3)+v1)//4)+v1)+v3)+-1)*4)//4)+v2)//7)//3)+v1)+v2)+v3)+1)*2)//4)*3)+-1)*1) + v1_val, v2_val, v3_val = v1.const_like(0), v2.const_like(2), v3.const_like(65) + num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + self.assertEqual(num, rn) + + def test_fuzz_failure8(self): + v1=Variable('v1', 0, 2) + v2=Variable('v2', 0, 8) + v3=Variable('v3', 0, 9) + expr = (((((((0+-1)+2)+v1)*-2)//3)+v1)*-4) + v1_val, v2_val, v3_val = v1.const_like(0), v2.const_like(0), v3.const_like(0) + num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + self.assertEqual(num, rn) + + def test_fuzz_failure9(self): + v1=Variable('v1', 0, 256) + v2=Variable('v2', 0, 1) + v3=Variable('v3', 0, 8) + expr = (((((((((((((((((((((((((((((0*-2)//1)+3)*-2)+-3)*-4)*1)+v1)+0)%2)%8)%9)+v2)%9)+-4)//4)+-1)*-2)+0)+v1)+v1)+3)+v1)+4)+-4)+0)*2)+-3)%6) + v1_val, v2_val, v3_val = v1.const_like(0), v2.const_like(1), v3.const_like(0) + num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + self.assertEqual(num, rn) + + def test_fuzz_failure10(self): + v1=Variable("v1", 0, 256) + v2=Variable("v2", 0, 32) + v3=Variable("v3", 0, 32) + expr = UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.MAX, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + x5:=UOp(Ops.IDIV, dtypes.int, arg=None, src=( + UOp(Ops.WHERE, dtypes.int, arg=None, src=( + UOp(Ops.CMPNE, dtypes.bool, arg=None, src=( + UOp(Ops.CMPLT, dtypes.bool, arg=None, src=( + x9:=UOp(Ops.CONST, dtypes.int, arg=9, src=()), + x10:=UOp(Ops.DEFINE_VAR, dtypes.int, arg=('v1', 0, 256), src=()),)), + x11:=UOp(Ops.CONST, dtypes.bool, arg=True, src=()),)), + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x10, + x14:=UOp(Ops.CONST, dtypes.int, arg=-4, src=()),)), + x14,)), + UOp(Ops.IDIV, dtypes.int, arg=None, src=( + x10, + x9,)),)), + x9,)), + x14,)), + x11,)), + x5, + UOp(Ops.IDIV, dtypes.int, arg=None, src=( + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.MOD, dtypes.int, arg=None, src=( + x19:=UOp(Ops.DEFINE_VAR, dtypes.int, arg=('v2', 0, 32), src=()), + UOp(Ops.CONST, dtypes.int, arg=3, src=()),)), + x19,)), + UOp(Ops.CONST, dtypes.int, arg=5, src=()),)),)), + x22:=UOp(Ops.CONST, dtypes.int, arg=-1, src=()),)), + UOp(Ops.MUL, dtypes.int, arg=None, src=( + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.ADD, dtypes.int, arg=None, src=( + UOp(Ops.MOD, dtypes.int, arg=None, src=( + UOp(Ops.MUL, dtypes.int, arg=None, src=( + x10, + UOp(Ops.CONST, dtypes.int, arg=-2, src=()),)), + UOp(Ops.CONST, dtypes.int, arg=6, src=()),)), + UOp(Ops.MOD, dtypes.int, arg=None, src=( + UOp(Ops.DEFINE_VAR, dtypes.int, arg=('v3', 0, 32), src=()), + UOp(Ops.CONST, dtypes.int, arg=1, src=()),)),)), + UOp(Ops.CONST, dtypes.int, arg=0, src=()),)), + x22,)),)), + x22,)) + v1_val, v2_val, v3_val = UOp.const(dtypes.int, 9), UOp.const(dtypes.int, 0),UOp.const(dtypes.int, 0) + num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + self.assertEqual(num, rn) diff --git a/tinygrad_repo/test/unit/test_symbolic_shapetracker.py b/tinygrad_repo/test/unit/test_symbolic_shapetracker.py new file mode 100644 index 000000000..ed065d057 --- /dev/null +++ b/tinygrad_repo/test/unit/test_symbolic_shapetracker.py @@ -0,0 +1,251 @@ +import unittest +from tinygrad.shape.shapetracker import ShapeTracker, View +from tinygrad import Variable +from tinygrad.tensor import Tensor + +class TestSymbolic(unittest.TestCase): + def assert_tuple_equal(self, x, y): + for a,b in zip(x,y): self.assertFalse(a != b) + + def test_symbolic_st(self): + x = Variable("x", 1, 100) + st = ShapeTracker.from_shape((x, 3)) + assert st.shape == (x, 3) + assert st.real_strides() == (3, 1) + + @unittest.expectedFailure + def test_real_strides_0(self): + st = ShapeTracker(views=(View(shape=(2, (Variable('start_pos', 1, 8)+1), 1, 1), strides=(8, 1, 0, 0), offset=0, mask=((0, 2), (0, Variable('start_pos', 1, 8)), (0, 1), (0, 1)), contiguous=False), View(shape=(2, (Variable('start_pos', 1, 8)+1)), strides=((Variable('start_pos', 1, 8)+1), 1), offset=0, mask=None, contiguous=True))) # noqa: E501 + self.assertEqual(st.real_strides(), (8, None)) + + @unittest.expectedFailure + def test_real_strides_1(self): + st = ShapeTracker(views=(View(shape=(3, (Variable('i', 1, 10)+2)), strides=(Variable('i', 1, 10), 1), offset=0, mask=((0, 3), (0, Variable('i', 1, 10))), contiguous=False),)) # noqa: E501 + self.assertEqual(st.real_strides(), (Variable('i', 1, 10), None)) + + @unittest.expectedFailure + def test_real_strides_2(self): + st = ShapeTracker(views=(View(shape=(3, (Variable('i', 1, 10)+Variable('j', 1, 10))), strides=(Variable('i', 1, 10), 1), offset=0, mask=((0, 3), (0, Variable('i', 1, 10))), contiguous=False),)) # noqa: E501 + self.assertEqual(st.real_strides(), (Variable('i', 1, 10), None)) + + def test_merge_view_recursion_err(self): + vm2 = View(shape=(Variable('j', 1, 10),), strides=(0,), offset=0, mask=None, contiguous=False) + vm1 = View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True) + self.assertEqual(vm2+vm1, vm1) + + def test_merge_view_recursion_err2(self): + vm2 = View(shape=(Variable('a', 1, 10).bind(4),), strides=(0,), offset=0, mask=None, contiguous=False) + # NOTE: vm1 is different from what create function would give, and this test vm2+vm1 halts + vm1 = View(shape=(Variable('a', 1, 10).bind(4),), strides=(1,), offset=0, mask=((0, Variable('a', 1, 10).bind(4)),), contiguous=False) + self.assertEqual(vm2+vm1, None) + + vm3 = View.create(shape=(Variable('a', 1, 10).bind(4),)) + self.assertEqual(vm3.shape, vm1.shape) + self.assertEqual(vm3.strides, vm1.strides) + self.assertEqual(vm2+vm3, vm2) + + def test_cat_dim0_strides(self): + i = Variable("i", 1, 5).bind(3) + j = Variable("j", 1, 5).bind(3) + k = Variable("k", 1, 5).bind(3) + t = Tensor.rand(3, 4).reshape(i, 4).cat(Tensor.rand(3, 4).reshape(j, 4), dim=0).cat(Tensor.rand(3, 4).reshape(k, 4), dim=0) + st = t.uop.st + self.assert_tuple_equal(st.shape, (i+j+k, 4)) + assert st.real_strides() == (4, 1) + t = Tensor.rand(3, 3).reshape(i, 3).cat(Tensor.rand(3, 3).reshape(i, 3), dim=0).cat(Tensor.rand(3, 3), dim=0) + st = t.uop.st + self.assert_tuple_equal(st.shape, (2*i+3, 3)) + assert st.real_strides() == (3, 1) + + def test_cat_dim1_strides(self): + i = Variable("i", 1, 5).bind(4) + j = Variable("j", 1, 5).bind(4) + k = Variable("k", 1, 5).bind(4) + t = Tensor.rand(3, 4).reshape(3, i).cat(Tensor.rand(3, 4).reshape(3, j), dim=1).cat(Tensor.rand(3, 4).reshape(3, k), dim=1) + st = t.uop.st + self.assert_tuple_equal(st.shape, (3, i+j+k)) + self.assert_tuple_equal(st.real_strides(), (i+j+k, 1)) + +class TestSymbolicVarVals(unittest.TestCase): + def assert_equal(self, x, y): self.assertFalse(x != y) + def test_var_vals_empty(self): + assert ShapeTracker.from_shape((3, 4, 5)).var_vals == {} + + def test_var_vals_shape(self): + x = Variable("x", 1, 100).bind(3) + assert ShapeTracker.from_shape((x, 3)).var_vals == {Variable("x", 1, 100): 3} + + def test_var_vals_offset(self): + x = Variable("x", 1, 100).bind(3) + st = ShapeTracker.from_shape((4, 3)).shrink(((x, x+1), (0, 3))) + self.assert_equal(st.views[-1].offset, x * 3) + assert st.var_vals == {Variable("x", 1, 100): 3} + + def test_var_vals_mask(self): + x = Variable("x", 1, 100).bind(3) + view = View.create(shape=(3,4), strides=(4,1), offset=0, mask=((0, x), (0, 4))) + st = ShapeTracker(views=(view,)) + assert st.var_vals == {Variable("x", 1, 100): 3} + + def test_var_vals_complex(self): + x = Variable("x", 1, 100).bind(3) + y = Variable("y", 1, 100).bind(4) + z = Variable("z", 1, 100).bind(5) + st = ShapeTracker.from_shape((x, 5, y)).shrink(((0, x), (z, z+1), (0, 3))) + self.assert_equal(st.views[-1].offset, y * z) + assert st.var_vals == {Variable("x", 1, 100): 3, Variable("y", 1, 100):4, Variable("z", 1, 100): 5} + + def test_shrink_reshape(self): + x = Variable("x", 1, 100).bind(3) + st = ShapeTracker.from_shape((10, 10, 10)).shrink(((x, x+3), (3, 7), (2, 5))) + st = st.reshape((3*4*3,)) + assert st.var_vals == {Variable("x", 1, 100): 3} + +class TestShapeTrackerUnbind(unittest.TestCase): + def test_view_unbind(self): + v = Variable("v", 1, 100) + bv = Variable("v", 1, 100).bind(3) + unbound_view, var_val = View.create(shape=(bv, 4)).unbind() + assert unbound_view == View.create(shape=(v, 4)) + assert var_val == {v: 3} + + def test_reshape_unbind(self): + v = Variable("v", 1, 100) + bv = Variable("v", 1, 100).bind(3) + t = Tensor.rand(3, 4).reshape(bv, 4) + unbound_st, var_val = t.uop.st.unbind() + assert unbound_st == ShapeTracker((View.create(shape=(v, 4)),)) + assert var_val == {v: 3} + + def test_shrink_unbind(self): + v = Variable("v", 1, 100) + bv = Variable("v", 1, 100).bind(2) + t = Tensor.rand(3, 4).shrink(((bv, bv+1), (0, 4))) + unbound_st, var_val = t.uop.st.unbind() + assert unbound_st == ShapeTracker((View.create(shape=(1, 4), offset=4*v),)) + assert var_val == {v: 2} + +class TestSymbolicReshapeFromContiguous(unittest.TestCase): + def test_reshape_into_symbols_simple(self): + for i in range(1, 6): + vi = Variable("i", 1, 5).bind(i) + t = Tensor.rand(i, 4).reshape(vi, 4) + assert t.shape == (vi, 4) + t = Tensor.rand(i, 6).reshape(vi, 2, 3) + assert t.shape == (vi, 2, 3) + + def test_reshape_symbols_reshape_ints(self): + for i in range(1, 6): + vi = Variable("i", 1, 5).bind(i) + t = Tensor.rand(i, 4).reshape(vi, 4) + assert t.shape == (vi, 4) + t = t.reshape(i, 4) + assert t.shape == (i, 4) + + @unittest.skip("works now") + def test_reshape_into_symbols_bad_shape(self): + vi = Variable("i", 1, 10).bind(4) + # TODO: this never actually worked, it relied on lazy + #with self.assertRaises(ValueError): + # Tensor.rand(4, 6).reshape(vi, 6).reshape(1, 77) # reshape to a different size new shape through symbolic shape + with self.assertRaises(AssertionError): + Tensor.rand(3, 4).reshape(3, (vi+1)) # reshape into non-Variable Node + + def test_two_symbol_reshape(self): + for i in range(1, 6): + for j in range(1, 6): + vi = Variable("i", 1, 5).bind(i) + vj = Variable("j", 1, 5).bind(j) + t = Tensor.rand(i, j).reshape(vi, vj) + assert t.shape == (vi, vj) + # NOTE: this is currently not allowed + # t = t.reshape(1, vi*vj) + # assert t.shape == (1, vi*vj) + t = t.reshape(vj, vi) + assert t.shape == (vj, vi) + + def test_symbolic_mask(self): + # taken from gpt2 single kvcache + # these two caused problems in gpt2 if reshape merged views + view = View(shape=(1, (Variable('start_pos', 1, 128).bind(2)+1), 16, 64), strides=(0, 0, 64, 1), offset=1024, mask=((0, 1), (Variable('start_pos', 1, 128).bind(2), (Variable('start_pos', 1, 128).bind(2)+1)), (0, 16), (0, 64)), contiguous=False) # noqa: E501 + new_shape = (1, 1, (Variable('start_pos', 1, 128).bind(2)+1), 16, 64) + assert view.reshape(new_shape) is None + + view = View(shape=(2, 1, (Variable('start_pos', 1, 128)+1), 16, 64), strides=(0, 0, 1024, 64, 1), offset=131072, mask=((1, 2), (0, 1), (0, (Variable('start_pos', 1, 128)+1)), (0, 16), (0, 64)), contiguous=False) # noqa: E501 + new_shape = (2, (Variable('start_pos', 1, 128)+1), 16, 64) + assert view.reshape(new_shape) is None + +class TestSymbolicReshapeFromNonContiguous(unittest.TestCase): + def test_reshape_from_const(self): + vi = Variable("i", 1, 5).bind(4) + t = Tensor.ones(3, 4).reshape(3, vi) + assert t.shape == (3, vi) + assert not t.uop.st.contiguous + assert len(t.uop.st.views) == 1 + + def test_reshape_not_allowed(self): + vi = Variable("i", 1, 5).bind(4) + with self.assertRaises(ValueError): + # different shape length # TODO: cases where contractions matched might be fine + Tensor.ones(3, 4, 1).reshape(3, vi) + with self.assertRaises(ValueError): + # size matched, but dimensions do not match + Tensor.ones(4, 3).reshape(3, vi) + + def test_reshape_from_padded(self): + vi = Variable("i", 1, 5).bind(4) + t = Tensor.ones(3, 4).contiguous().expand(2, 3, 4).pad(((1, 1), None, None)).shrink((None, None, (1, 3))) + st = t.uop.st + assert len(st.views) == 1 + view = st.views[0] + assert view.shape == (4, 3, 2) + t = t.reshape(vi, 3, 2) + st2 = t.uop.st + assert len(st2.views) == 1 + view2 = st2.views[0] + # check only shape changed. strides, offset, mask, contiguous remained the same + assert view2.shape == (vi, 3, 2) + assert view.strides == view2.strides == (0, 4, 1) + assert view.offset == view2.offset == 1 + assert view.mask == view2.mask == ((1, 3), (0, 3), (0, 2)) + assert not view.contiguous and not view2.contiguous + +class TestSymbolicExpand(unittest.TestCase): + def test_expand_into_symbols(self): + vi = Variable("i", 1, 5).bind(3) + vj = Variable("j", 1, 5).bind(3) + a = Tensor([[1], [2], [3]]).expand((3, vi)) + assert a.shape == (3, vi) + a = a.reshape(3, vi, 1).expand((3, vi, vj)) + assert a.shape == (3, vi, vj) + + def test_plus_expands_constant(self): + for i in range(1, 6): + vi = Variable("i", 1, 5).bind(i) + a = Tensor.rand(3, i).reshape(3, vi) + a = a + 1 + self.assertTupleEqual(a.shape, (3, vi)) + + def test_pad_then_expand_into_symbols(self): + vi = Variable("i", 1, 10).bind(3) + a = Tensor(1).unsqueeze(0).pad((0, 24)).unsqueeze(0).expand((vi, 25)) + self.assertEqual(a.shape, (vi, 25)) + self.assertEqual(a.reshape(25*vi).shape, (vi*25,)) + self.assertEqual(a.reshape(vi*25).shape, (vi*25,)) + +class TestSymbolicShrink(unittest.TestCase): + def test_shrink_symbols(self): + vi = Variable("i", 1, 5) + t = Tensor.rand(3, 5).shrink(((0, 2), (vi, vi+1))) + assert t.shape == (2, 1) + +class TestSymbolicPad(unittest.TestCase): + def test_pad(self): + v = Variable("v", 1, 100).bind(5) + t = Tensor.ones(5).reshape(v).pad(((4, 0),)).reshape(9) + assert t.shape == (9,) + st = t.uop.st + print(st) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_tar.py b/tinygrad_repo/test/unit/test_tar.py new file mode 100644 index 000000000..42f00d169 --- /dev/null +++ b/tinygrad_repo/test/unit/test_tar.py @@ -0,0 +1,141 @@ +import unittest, tarfile, io, os, pathlib, tempfile +import numpy as np +from tinygrad import Tensor +from tinygrad.nn.state import tar_extract + +class TestTarExtractFile(unittest.TestCase): + def setUp(self): + self.test_dir = tempfile.mkdtemp() + self.test_files = { + 'file1.txt': b'Hello, World!', + 'file2.bin': b'\x00\x01\x02\x03\x04', + 'empty_file.txt': b'' + } + self.tar_path = os.path.join(self.test_dir, 'test.tar') + with tarfile.open(self.tar_path, 'w') as tar: + for filename, content in self.test_files.items(): + file_path = os.path.join(self.test_dir, filename) + with open(file_path, 'wb') as f: + f.write(content) + tar.add(file_path, arcname=filename) + + # Create invalid tar file + self.invalid_tar_path = os.path.join(self.test_dir, 'invalid.tar') + with open(self.invalid_tar_path, 'wb') as f: + f.write(b'This is not a valid tar file') + + def tearDown(self): + for filename in self.test_files: + os.remove(os.path.join(self.test_dir, filename)) + os.remove(self.tar_path) + os.remove(self.invalid_tar_path) + os.rmdir(self.test_dir) + + def test_tar_extract_returns_dict(self): + result = tar_extract(self.tar_path) + self.assertIsInstance(result, dict) + + def test_tar_extract_correct_keys(self): + result = tar_extract(self.tar_path) + self.assertEqual(set(result.keys()), set(self.test_files.keys())) + + def test_tar_extract_content_size(self): + result = tar_extract(self.tar_path) + for filename, content in self.test_files.items(): + self.assertEqual(len(result[filename]), len(content)) + + def test_tar_extract_content_values(self): + result = tar_extract(self.tar_path) + for filename, content in self.test_files.items(): + np.testing.assert_array_equal(result[filename].numpy(), np.frombuffer(content, dtype=np.uint8)) + + def test_tar_extract_empty_file(self): + result = tar_extract(self.tar_path) + self.assertEqual(len(result['empty_file.txt']), 0) + + def test_tar_extract_non_existent_file(self): + with self.assertRaises(FileNotFoundError): + tar_extract('non_existent_file.tar') + + def test_tar_extract_invalid_file(self): + with self.assertRaises(tarfile.ReadError): + tar_extract(self.invalid_tar_path) + +class TestTarExtractPAX(unittest.TestCase): + tar_format = tarfile.PAX_FORMAT + max_link_len = 1000_000 + test_files = { + 'a/file1.txt': b'Hello, World!', + 'a/b/file2.bin': b'\x00\x01\x02\x03\x04', + 'empty_file.txt': b'', + '512file': b'a' * 512, + 'long_file': b'some data' * 100, + 'very' * 15 + '/' + 'very' * 15 + '_long_filename.txt': b'Hello, World!!', + 'very' * 200 + '_long_filename.txt': b'Hello, World!!!', + } + + def create_tar_tensor(self): + fobj = io.BytesIO() + test_dirs = set(os.path.dirname(k) for k in self.test_files.keys()).difference({ '' }) + with tarfile.open(fileobj=fobj, mode='w', format=self.tar_format) as tar: + for dirname in test_dirs: + dir_info = tarfile.TarInfo(name=dirname) + dir_info.type = tarfile.DIRTYPE + tar.addfile(dir_info) + + for filename, content in self.test_files.items(): + file_info = tarfile.TarInfo(name=filename) + file_info.size = len(content) + tar.addfile(file_info, io.BytesIO(content)) + + if len(filename) < self.max_link_len: + link_info = tarfile.TarInfo(name=filename + '.lnk') + link_info.type = tarfile.SYMTYPE + link_info.linkname = filename + tar.addfile(link_info) + return Tensor(fobj.getvalue()) + + def test_tar_extract_returns_dict(self): + result = tar_extract(self.create_tar_tensor()) + self.assertIsInstance(result, dict) + + def test_tar_extract_correct_keys(self): + result = tar_extract(self.create_tar_tensor()) + self.assertEqual(set(result.keys()), set(self.test_files.keys())) + + def test_tar_extract_content_size(self): + result = tar_extract(self.create_tar_tensor()) + for filename, content in self.test_files.items(): + self.assertEqual(len(result[filename]), len(content)) + + def test_tar_extract_content_values(self): + result = tar_extract(self.create_tar_tensor()) + for filename, content in self.test_files.items(): + np.testing.assert_array_equal(result[filename].numpy(), np.frombuffer(content, dtype=np.uint8)) + + def test_tar_extract_empty_file(self): + result = tar_extract(self.create_tar_tensor()) + self.assertEqual(len(result['empty_file.txt']), 0) + + def test_tar_extract_non_existent_file(self): + with self.assertRaises(FileNotFoundError): + tar_extract(Tensor(pathlib.Path('non_existent_file.tar'))) + + def test_tar_extract_invalid_file(self): + with self.assertRaises(tarfile.ReadError): + tar_extract(Tensor(b'This is not a valid tar file')) + + def test_tar_extract_invalid_file_long(self): + with self.assertRaises(tarfile.ReadError): + tar_extract(Tensor(b'This is not a valid tar file'*100)) + +class TestTarExtractUSTAR(TestTarExtractPAX): + tar_format = tarfile.USTAR_FORMAT + max_link_len = 100 + test_files = {k: v for k, v in TestTarExtractPAX.test_files.items() if len(k) < 256} + +class TestTarExtractGNU(TestTarExtractPAX): + tar_format = tarfile.GNU_FORMAT + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_tensor_io.py b/tinygrad_repo/test/unit/test_tensor_io.py new file mode 100644 index 000000000..a83925728 --- /dev/null +++ b/tinygrad_repo/test/unit/test_tensor_io.py @@ -0,0 +1,38 @@ +import unittest +from tinygrad import Tensor, dtypes +from tinygrad.nn.state import TensorIO + +class TestTensorIO(unittest.TestCase): + def test_create(self): + with self.assertRaises(ValueError): + TensorIO(Tensor(b"Hello World").reshape(1, -1)) + with self.assertRaises(ValueError): + TensorIO(Tensor([], dtype=dtypes.int64).reshape(1, -1)) + + def test_seek(self): + t = Tensor(b"Hello World!") + fobj = TensorIO(t) + self.assertEqual(fobj.tell(), 0) + self.assertEqual(fobj.seek(1), 1) + self.assertEqual(fobj.seek(-2, 2), len(t) - 2) + self.assertEqual(fobj.seek(1, 1), len(t) - 1) + self.assertEqual(fobj.seek(10, 1), len(t)) + self.assertEqual(fobj.seek(10, 2), len(t)) + self.assertEqual(fobj.seek(-10, 0), 0) + + def test_read(self): + data = b"Hello World!" + fobj = TensorIO(Tensor(data)) + self.assertEqual(fobj.read(1), data[:1]) + self.assertEqual(fobj.read(5), data[1:6]) + self.assertEqual(fobj.read(100), data[6:]) + self.assertEqual(fobj.read(100), b"") + + def test_read_nolen(self): + data = b"Hello World!" + fobj = TensorIO(Tensor(data)) + fobj.seek(2) + self.assertEqual(fobj.read(), data[2:]) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_tensor_uop_representation.py b/tinygrad_repo/test/unit/test_tensor_uop_representation.py new file mode 100644 index 000000000..59d28a434 --- /dev/null +++ b/tinygrad_repo/test/unit/test_tensor_uop_representation.py @@ -0,0 +1,104 @@ +import unittest +from tinygrad import Tensor +from tinygrad.uop.ops import UPat, Ops, UOp + +# NOTE: unlike before base for a realized tensor is always a BUFFER +realized_pattern = UPat(Ops.BUFFER) +# after realization, base tensor uops become RESHAPE(BUFFER) +buffer_view_pattern = UPat(Ops.RESHAPE, src=(UPat(Ops.BUFFER),)) +const_pattern = UPat(Ops.CONST, src=(UPat(Ops.VIEW, src=(UPat(Ops.DEVICE),),))) +def is_pattern_uop(u:UOp, pat:UPat): assert pat.match(u, {}), f"{u}\nis not\n{pat}" +def is_pattern(ten:Tensor, pat:UPat): is_pattern_uop(ten.uop, pat) + +class TestTensorMutates(unittest.TestCase): + def test_mutate_add(self): + a = Tensor([1,2,3]) + b = Tensor([4,5,6]) + ret = a+b + pa = a.uop + pb = b.uop + pr = ret.uop + ret.schedule() + self.assertIsNot(pa, a.uop) + self.assertIsNot(pb, b.uop) + self.assertIsNot(pr, ret.uop) + for t in [a,b,ret]: is_pattern_uop(t.uop.base, realized_pattern) + + def test_reshape_is_same_parent(self): + a = Tensor([1,2,3]) + b = Tensor([4,5,6]) + c = a+b + d = (a+b).reshape(3,1) + d.realize() + is_pattern_uop(d.uop.base, realized_pattern) + is_pattern_uop(c.uop.base, realized_pattern) + # NOTE: we keep movement ops on top of the buffer view + is_pattern_uop(c.uop, UPat(Ops.BUFFER)) + is_pattern_uop(d.uop, UPat(Ops.VIEW, src=(realized_pattern,))) + + def test_reshape_is_same_child(self): + a = Tensor([1,2,3]) + b = Tensor([4,5,6]) + c = a+b + d = (a+b).reshape(3,1) + c.realize() + is_pattern_uop(c.uop.base, realized_pattern) + is_pattern_uop(d.uop.base, realized_pattern) + +class TestTensorUopRepresentation(unittest.TestCase): + def test_realized(self): + a = Tensor([1.,2,3]).realize() + print(a.uop) + is_pattern_uop(a.uop.base, realized_pattern) + + def test_add_realized(self): + a = Tensor([1.,2,3]).realize() + b = Tensor([4.,5,6]).realize() + c = a+b + print(c.uop) + is_pattern(c, UPat(Ops.ADD, src=(realized_pattern, realized_pattern))) + + def test_const_pattern(self): + a = Tensor(1) + print(a.uop) + is_pattern(a, const_pattern) # const in tensor has a DEVICE and VIEW src + is_pattern(a, UPat.cvar("x")) # even cvar works! + + def test_consts_do_not_realize(self): + a = Tensor(1) + print(a.uop) + pre_realize = a.uop + a.realize() + assert a.uop is pre_realize + + def test_viewed_consts_do_not_realize(self): + a = Tensor.ones(10, 10) + print(a.uop) + a.realize() + is_pattern(a, const_pattern) + self.assertEqual(a.uop.shape, (10, 10)) + + # CONST is EXPAND -> RESHAPE -> CONST -> DEVICE + def test_consts_dont_have_buffers(self): + a = Tensor.ones(10, 10) + buffers_in_parents = [x.op for x in a.uop.toposort() if x.op is Ops.BUFFER] + self.assertEqual(len(buffers_in_parents), 0) + is_pattern(a, UPat(Ops.EXPAND, src=(UPat(Ops.RESHAPE, src=(const_pattern,)),))) + + # COPY has a copyin source and a device. + def test_copyin(self): + a = Tensor([1.,2,3]).realize() + c = a.to("TEST") # NOTE: this isn't checked + print(c.uop) + is_pattern(c, UPat(Ops.COPY, src=(realized_pattern, UPat(Ops.DEVICE)), arg=None)) + + def test_empty_buf(self): + a = Tensor.empty(3, 3) + is_pattern(a, UPat(Ops.RESHAPE, src=(UPat(Ops.BUFFER),))) + vi = UOp.variable("i", 1, 3).bind(1) + a = Tensor.empty(3, vi) + is_pattern(a, UPat(Ops.RESHAPE, src=(UPat(Ops.BUFFER),))) + self.assertEqual(a.uop.base.buffer.size, 9) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_tqdm.py b/tinygrad_repo/test/unit/test_tqdm.py new file mode 100644 index 000000000..4f9581d59 --- /dev/null +++ b/tinygrad_repo/test/unit/test_tqdm.py @@ -0,0 +1,310 @@ +import time, random, unittest, itertools +from unittest.mock import patch +from io import StringIO +from collections import namedtuple +from tqdm import tqdm +from tinygrad.helpers import tqdm as tinytqdm, trange as tinytrange +import numpy as np + +def _get_iter_per_second(raw:str) -> float: + # raw might have unit scale + if raw.endswith("k"): return float(raw[:-1])*1e3 + if raw.endswith("M"): return float(raw[:-1])*1e6 + return float(raw) + +# TODO: _get_iter_per_second in test_unit_scale might fail if lower bound is too small +NCOLS_RANGE = [80, 240] + +class TestProgressBar(unittest.TestCase): + def _compare_bars(self, bar1, bar2): + prefix1, prog1, suffix1 = bar1.split("|") + prefix2, prog2, suffix2 = bar2.split("|") + + self.assertEqual(len(bar1), len(bar2)) + self.assertEqual(prefix1, prefix2) + + def parse_timer(timer): return sum(int(x) * y for x, y in zip(timer.split(':')[::-1], (1, 60, 3600))) + + if "?" not in suffix1 and "?" not in suffix2: + # allow for few sec diff in timers (removes flakiness) + timer1, rm1 = [parse_timer(timer) for timer in suffix1.split("[")[-1].split(",")[0].split("<")] + timer2, rm2 = [parse_timer(timer) for timer in suffix2.split("[")[-1].split(",")[0].split("<")] + np.testing.assert_allclose(timer1, timer2, atol=5, rtol=1e-2) + np.testing.assert_allclose(rm1, rm2, atol=5, rtol=1e-2) + + # get suffix without timers + suffix1 = suffix1.split("[")[0] + suffix1.split(",")[1] + suffix2 = suffix2.split("[")[0] + suffix2.split(",")[1] + self.assertEqual(suffix1, suffix2) + else: + self.assertEqual(suffix1, suffix2) + + diff = sum([c1 != c2 for c1, c2 in zip(prog1, prog2)]) # allow 1 char diff to be less flaky, but it should match + assert diff <= 1, f"{diff=}\n{prog1=}\n{prog2=}" + + @patch('sys.stderr', new_callable=StringIO) + @patch('shutil.get_terminal_size') + def test_tqdm_output_iter(self, mock_terminal_size, mock_stderr): + for _ in range(10): + total, ncols = random.randint(5, 30), random.randint(*NCOLS_RANGE) + mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) + mock_stderr.truncate(0) + + # compare bars at each iteration (only when tinytqdm bar has been updated) + for n in (bar := tinytqdm(range(total), desc="Test")): + if bar.i % bar.skip != 0: continue + tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 + elapsed = n/iters_per_sec if n>0 else 0 + tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix="Test") + self._compare_bars(tinytqdm_output, tqdm_output) + + # compare final bars + tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 + elapsed = total/iters_per_sec if n>0 else 0 + tqdm_output = tqdm.format_meter(n=total, total=total, elapsed=elapsed, ncols=ncols, prefix="Test") + self._compare_bars(tinytqdm_output, tqdm_output) + + @patch('sys.stderr', new_callable=StringIO) + @patch('shutil.get_terminal_size') + def test_unit_scale(self, mock_terminal_size, mock_stderr): + for unit_scale in [True, False]: + # NOTE: numpy comparison raises TypeError if exponent > 22 + for exponent in range(1, 22, 3): + low, high = 10 ** exponent, 10 ** (exponent+1) + for _ in range(5): + total, ncols = random.randint(low, high), random.randint(*NCOLS_RANGE) + mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) + mock_stderr.truncate(0) + + # compare bars at each iteration (only when tinytqdm bar has been updated) + # setting high rate to make sure it does not skip + for n in tinytqdm(range(total), desc="Test", total=total, unit_scale=unit_scale, rate=10**9): + tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + + if n: + iters_per_sec = _get_iter_per_second(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) + elapsed = n/iters_per_sec + else: + elapsed = 0 + tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix="Test", unit_scale=unit_scale) + self._compare_bars(tinytqdm_output, tqdm_output) + if n > 3: break + + @patch('sys.stderr', new_callable=StringIO) + @patch('shutil.get_terminal_size') + def test_unit_scale_exact(self, mock_terminal_size, mock_stderr): + unit_scale = True + ncols = 80 + mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) + mock_stderr.truncate(0) + + total = 10 + with patch('time.perf_counter', side_effect=[0]+list(range(100))): # one more 0 for the init call + # compare bars at each iteration (only when tinytqdm bar has been updated) + for n in tinytqdm(range(total), desc="Test", total=total, unit_scale=unit_scale, rate=10**9): + tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + elapsed = n + tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix="Test", unit_scale=unit_scale) + self._compare_bars(tinytqdm_output, tqdm_output) + if n > 5: break + + total = 10 + k=0.001000001 + # regression test for + # E AssertionError: ' 1.00/10.0 1000it/s]' != ' 1.00/10.0 1.00kit/s]' + # E - 1.00/10.0 1000it/s] + # E ? ^ + # E + 1.00/10.0 1.00kit/s] + # E ? + ^ + with patch('time.perf_counter', side_effect=[0, *[i*k for i in range(100)]]): # one more 0 for the init call + # compare bars at each iteration (only when tinytqdm bar has been updated) + for n in tinytqdm(range(total), desc="Test", total=total, unit_scale=unit_scale, rate=10**9): + tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + elapsed = n*k + tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix="Test", unit_scale=unit_scale) + self._compare_bars(tinytqdm_output, tqdm_output) + if n > 5: break + + @patch('sys.stderr', new_callable=StringIO) + @patch('shutil.get_terminal_size') + def test_set_description(self, mock_terminal_size, mock_stderr): + for _ in range(10): + total, ncols = random.randint(5, 30), random.randint(*NCOLS_RANGE) + mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) + mock_stderr.truncate(0) + + expected_prefix = "Test" + # compare bars at each iteration (only when tinytqdm bar has been updated) + for i,n in enumerate(bar := tinytqdm(range(total), desc="Test")): + if bar.i % bar.skip != 0: continue + tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 + elapsed = n/iters_per_sec if n>0 else 0 + tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix=expected_prefix) + expected_prefix = desc = f"Test {i}" if i % 2 == 0 else "" + bar.set_description(desc) + self._compare_bars(tinytqdm_output, tqdm_output) + + # compare final bars + tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 + elapsed = total/iters_per_sec if n>0 else 0 + tqdm_output = tqdm.format_meter(n=total, total=total, elapsed=elapsed, ncols=ncols, prefix=expected_prefix) + self._compare_bars(tinytqdm_output, tqdm_output) + + @patch('sys.stderr', new_callable=StringIO) + @patch('shutil.get_terminal_size') + def test_trange_output_iter(self, mock_terminal_size, mock_stderr): + for _ in range(5): + total, ncols = random.randint(5, 30), random.randint(*NCOLS_RANGE) + mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) + mock_stderr.truncate(0) + + # compare bars at each iteration (only when tinytqdm bar has been updated) + for n in (bar := tinytrange(total, desc="Test")): + if bar.i % bar.skip != 0: continue + tiny_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + iters_per_sec = float(tiny_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 + elapsed = n/iters_per_sec if n>0 else 0 + tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix="Test") + self._compare_bars(tiny_output, tqdm_output) + + # compare final bars + tiny_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + iters_per_sec = float(tiny_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 + elapsed = total/iters_per_sec if n>0 else 0 + tqdm_output = tqdm.format_meter(n=total, total=total, elapsed=elapsed, ncols=ncols, prefix="Test") + self._compare_bars(tiny_output, tqdm_output) + + @patch('sys.stderr', new_callable=StringIO) + @patch('shutil.get_terminal_size') + def test_tqdm_output_custom(self, mock_terminal_size, mock_stderr): + for _ in range(10): + total, ncols = random.randint(10000, 1000000), random.randint(*NCOLS_RANGE) + mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) + mock_stderr.truncate(0) + + # compare bars at each iteration (only when tinytqdm bar has been updated) + bar = tinytqdm(total=total, desc="Test") + n = 0 + while n < total: + incr = (total // 100) + random.randint(0, 1000) + if n + incr > total: incr = total - n + bar.update(incr, close=n+incr==total) + n += incr + if bar.i % bar.skip != 0: continue + + tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 + elapsed = n/iters_per_sec if n>0 else 0 + tqdm_output = tqdm.format_meter(n=n, total=total, elapsed=elapsed, ncols=ncols, prefix="Test") + self._compare_bars(tinytqdm_output, tqdm_output) + + @patch('sys.stderr', new_callable=StringIO) + @patch('shutil.get_terminal_size') + def test_tqdm_output_custom_0_total(self, mock_terminal_size, mock_stderr): + for _ in range(10): + total, ncols = random.randint(10000, 100000), random.randint(*NCOLS_RANGE) + mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) + mock_stderr.truncate(0) + + # compare bars at each iteration (only when tinytqdm bar has been updated) + bar = tinytqdm(total=0, desc="Test") + n = 0 + while n < total: + incr = (total // 10) + random.randint(0, 100) + if n + incr > total: incr = total - n + bar.update(incr, close=n+incr==total) + n += incr + if bar.i % bar.skip != 0: continue + + tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) if n>0 else 0 + elapsed = n/iters_per_sec if n>0 else 0 + tqdm_output = tqdm.format_meter(n=n, total=0, elapsed=elapsed, ncols=ncols, prefix="Test") + self.assertEqual(tinytqdm_output, tqdm_output) + + @patch('sys.stderr', new_callable=StringIO) + @patch('shutil.get_terminal_size') + def test_tqdm_output_custom_nolen_total(self, mock_terminal_size, mock_stderr): + for unit_scale in [True, False]: + for _ in range(5): + gen = itertools.count(0) + ncols = random.randint(*NCOLS_RANGE) + mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) + mock_stderr.truncate(0) + + # compare bars at each iteration (only when tinytqdm bar has been updated) + # setting high rate to make sure it does not skip + for n,g in enumerate(tinytqdm(gen, desc="Test", unit_scale=unit_scale, rate=10**9)): + assert g == n + tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + if n: + iters_per_sec = _get_iter_per_second(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) + elapsed = n/iters_per_sec + else: + elapsed = 0 + tqdm_output = tqdm.format_meter(n=n, total=0, elapsed=elapsed, ncols=ncols, prefix="Test", unit_scale=unit_scale) + self.assertEqual(tinytqdm_output, tqdm_output) + if n > 5: break + + @patch('sys.stderr', new_callable=StringIO) + @patch('shutil.get_terminal_size') + def test_tqdm_write(self, mock_terminal_size, mock_stderr): + for _ in range(5): + ncols, tqdm_fp = random.randint(*NCOLS_RANGE), StringIO() + mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) + mock_stderr.truncate(0) + tqdm_fp.truncate(0) + for i in tinytqdm(range(10)): + time.sleep(0.01) + tinytqdm.write(str(i)) + tqdm.write(str(i), file=tqdm_fp) + tinytqdm_out, tqdm_out = mock_stderr.getvalue(), tqdm_fp.getvalue() + self.assertEqual(tinytqdm_out.split("\r\033[K")[-1], tqdm_out.split(f"{i-1}\n")[-1]) + self.assertEqual(tinytqdm_out, tinytqdm_out) + + @patch('sys.stderr', new_callable=StringIO) + @patch('shutil.get_terminal_size') + def test_tqdm_context_manager(self, mock_terminal_size, mock_stderr): + for _ in range(10): + total, ncols = random.randint(5, 30), random.randint(*NCOLS_RANGE) + mock_terminal_size.return_value = namedtuple(field_names='columns', typename='terminal_size')(ncols) + mock_stderr.truncate(0) + + with tinytqdm(desc="Test", total=total) as bar: + for _ in range(total): + bar.update(1) + + tinytqdm_output = mock_stderr.getvalue().split("\r")[-1].rstrip() + iters_per_sec = float(tinytqdm_output.split("it/s")[-2].split(" ")[-1]) + elapsed = total/iters_per_sec + tqdm_output = tqdm.format_meter(n=total, total=total, elapsed=elapsed, ncols=ncols, prefix="Test") + self._compare_bars(tinytqdm_output, tqdm_output) + + def test_tqdm_perf(self): + st = time.perf_counter() + for _ in tqdm(range(100)): pass + tqdm_time = time.perf_counter() - st + + st = time.perf_counter() + for _ in tinytqdm(range(100)): pass + tinytqdm_time = time.perf_counter() - st + + assert tinytqdm_time < 2 * tqdm_time + + def test_tqdm_perf_high_iter(self): + st = time.perf_counter() + for _ in tqdm(range(10^7)): pass + tqdm_time = time.perf_counter() - st + + st = time.perf_counter() + for _ in tinytqdm(range(10^7)): pass + tinytqdm_time = time.perf_counter() - st + + assert tinytqdm_time < 5 * tqdm_time + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_transcendental_helpers.py b/tinygrad_repo/test/unit/test_transcendental_helpers.py new file mode 100644 index 000000000..5a14b381d --- /dev/null +++ b/tinygrad_repo/test/unit/test_transcendental_helpers.py @@ -0,0 +1,109 @@ +import unittest, math +import numpy as np +from tinygrad import dtypes +from tinygrad.uop.ops import UOp, Ops +from tinygrad.uop.transcendental import TRANSCENDENTAL_SUPPORTED_DTYPES, payne_hanek_reduction, cody_waite_reduction +from tinygrad.uop.transcendental import frexp, rintk, xpow, xexp2, xlog2, trig_poly, pow2if +from test.helpers import eval_uop + +class TestTranscendentalFunctions(unittest.TestCase): + def test_payne_hanek_reduction(self): + # TODO: Test constant input when constant folding is fixed (or maybe test both variants) + # Load input value from a buffer to prevent constant folding + input_buf = UOp(Ops.DEFINE_GLOBAL, dtypes.double.ptr(), arg=1, src=()) + loaded_value = UOp.load(input_buf.index(UOp.const(dtypes.int, 0)), dtype=dtypes.double) + def eval_payne_hanek_reduction(v:float) -> tuple[float, int]: + return tuple(eval_uop(u, [(dtypes.float64, [v])]) for u in payne_hanek_reduction(loaded_value)) + + r, q = eval_payne_hanek_reduction(12 * math.pi + 0.1) + np.testing.assert_allclose(r, 0.1 - math.pi / 2) + np.testing.assert_equal(q, 1) + + r, q = eval_payne_hanek_reduction(12 * math.pi) + np.testing.assert_allclose(r, 0.0, atol=1e-8) + np.testing.assert_equal(q, 4) + + r, q = eval_payne_hanek_reduction(12 * math.pi - 0.1) + np.testing.assert_allclose(r, -0.1) + np.testing.assert_equal(q, 4) + + def test_cody_waite_reduction(self): + r, q = (eval_uop(u) for u in cody_waite_reduction(UOp.const(dtypes.float64, 12 * math.pi + 0.1))) + np.testing.assert_allclose(r, 0.1) + np.testing.assert_equal(q, 12) + + def test_frexp(self): + for x in (1, -1): + mantissa, exponent = (eval_uop(u) for u in frexp(UOp.const(dtypes.float64, x))) + np.testing.assert_equal(mantissa, 0.5) + np.testing.assert_equal(exponent, 1) + + for x in (2, -2): + mantissa, exponent = (eval_uop(u) for u in frexp(UOp.const(dtypes.float64, 2.0))) + np.testing.assert_equal(mantissa, 0.5) + np.testing.assert_equal(exponent, 2) + + mantissa, exponent = (eval_uop(u) for u in frexp(UOp.const(dtypes.float64, 5.0))) + np.testing.assert_equal(mantissa, 0.625) + np.testing.assert_equal(exponent, 3) + + mantissa, exponent = (eval_uop(u) for u in frexp(UOp.const(dtypes.float64, 1000.0))) + np.testing.assert_allclose(mantissa, 0.9765625) + np.testing.assert_equal(exponent, 10) + + def test_rintk(self): + np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, 0.0))), 0) + np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, 5.0))), 5) + np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, 5.5))), 6) + np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, 5.999))), 6) + np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, -5.0))), -5) + np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, -5.5))), -6) + np.testing.assert_allclose(eval_uop(rintk(UOp.const(dtypes.float, -5.999))), -6) + + def test_pow2if(self): + np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, 0), dtypes.float)), 1.0) + np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, 1), dtypes.float)), 2.0) + np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, 2), dtypes.float)), 4.0) + np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, 10), dtypes.float)), 1024.0) + np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, 63), dtypes.float)), 2**63) + np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, -1), dtypes.float)), 0.5) + np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, -2), dtypes.float)), 0.25) + np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, -10), dtypes.float)), 2**-10) + np.testing.assert_allclose(eval_uop(pow2if(UOp.const(dtypes.int, -63), dtypes.float)), 2**-63) + +class TestTranscendentalVectorizedFunctions(unittest.TestCase): + # given a scalar and vectorized input, check that the fxn outputs have the same + # scalar_dtypes, args, ops, and vcount (only for vectorized input) + + def _check_uop_vcount(self, u:tuple|UOp, vcount:int): + # check all UOps in u are vectorized with vcount + if isinstance(u, UOp): + assert u.dtype.vcount == vcount, f'expected {vcount=} but got {u.dtype.vcount=} for UOp\n{u=}' + [self._check_uop_vcount(x, vcount) for x in (u if isinstance(u, tuple) else u.src)] + + def _check_uops_match(self, u1:tuple|UOp, u2:tuple|UOp): + # check all UOps in u1, u2 have the same scalar_dtype, args, ops + if isinstance(u1, UOp) and isinstance(u2, UOp): + assert u1.dtype.scalar() == u2.dtype.scalar(), f'expected {u1.dtype.scalar()=} but got {u2.dtype.scalar()=} for UOps\n{u1=}\n{u2}' + assert u1.arg == u2.arg or (math.isnan(u1.arg) and math.isnan(u2.arg)), f'expected {u1.arg=} but got {u2.arg=} for UOps\n{u1=}\n{u2}' + assert u1.op == u2.op, f'expected {u1.op=} but got {u2.op=} for UOps\n{u1=}\n{u2}' + [self._check_uops_match(x1, x2) for x1, x2 in zip((u1 if isinstance(u1, tuple) else u1.src), (u2 if isinstance(u2, tuple) else u2.src))] + + def _test_vectorized(self, fxn, scalar_dtypes=TRANSCENDENTAL_SUPPORTED_DTYPES, vals=[-2,1.3,194], vcounts=[1,4,19]): + for scalar_dtype in scalar_dtypes: + for val in vals: + for vcount in vcounts: + in_scalar, in_vec = UOp.const(scalar_dtype, val), UOp.const(scalar_dtype.vec(vcount), val) + out_scalar, out_vec = fxn(in_scalar), fxn(in_vec) + self._check_uops_match(out_scalar, out_vec) + self._check_uop_vcount(out_vec, vcount) + + def test_xpow(self): return self._test_vectorized(lambda x: xpow(x, x)) + def test_xexp2(self): return self._test_vectorized(xexp2) + def test_xlog2(self): return self._test_vectorized(xlog2) + def test_payne_hanek_reduction(self): return self._test_vectorized(payne_hanek_reduction) + def test_cody_waite_reduction(self): return self._test_vectorized(cody_waite_reduction) + def test_trig_poly(self): return self._test_vectorized(lambda x: trig_poly(x, [0.0], [1.0])) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_uop_resolve.py b/tinygrad_repo/test/unit/test_uop_resolve.py new file mode 100644 index 000000000..83db03317 --- /dev/null +++ b/tinygrad_repo/test/unit/test_uop_resolve.py @@ -0,0 +1,125 @@ +import unittest +from tinygrad.dtype import dtypes +from tinygrad.uop.ops import UOp, resolve + +class TestUOpResolve(unittest.TestCase): + def test_simple_int(self): + u = UOp.const(dtypes.int, 4) + self.assertEqual(int(u), 4) + + def test_int_add(self): + u = UOp.const(dtypes.int, 4) + 7 + self.assertEqual(int(u), 11) + + def test_lt(self): + u = UOp.const(dtypes.int, 4) < 7 + self.assertTrue(u) + + def test_rfloordiv(self): + u = 8 // UOp.const(dtypes.int, 4) + self.assertEqual(int(u), 2) + + def test_rtruediv(self): + u = 9 / UOp.const(dtypes.float, 4) + self.assertEqual(float(u), 2.25) + + def test_leq(self): + u = UOp.const(dtypes.int, 4) <= 4 + self.assertTrue(u) + + def test_ne(self): + u = UOp.const(dtypes.int, 4) != 7 + self.assertTrue(u) + + def test_ne_f(self): + u = UOp.const(dtypes.int, 4) != 4 + self.assertFalse(u) + + def test_ngt(self): + u = UOp.const(dtypes.int, 4) > 7 + self.assertFalse(u) + + def test_ssimplify(self): + self.assertEqual((8 % UOp.const(dtypes.int, 4)).ssimplify(), 0) + self.assertEqual((8 * UOp.const(dtypes.int, 4)).ssimplify(), 32) + + def test_ambiguous_less_than(self): + u = UOp.variable("i", 1, 10) + self.assertTrue(resolve(u < 4)) + self.assertFalse(resolve(u < 4, False)) + self.assertTrue(resolve(u < 11, False)) + self.assertFalse(resolve(u < -1, False)) + self.assertFalse(resolve(u < -1, True)) + + def test_float_direct(self): + u = UOp.const(dtypes.float, 4.5) + 7 + self.assertEqual(float(u), 11.5) + + def test_var_cmp_t(self): + u = UOp.variable("i", 1, 10) < 20 + self.assertTrue(u) + + def test_var_cmp_t2(self): + u = UOp.variable("i", 1, 10)//2 < 20 + self.assertTrue(u) + + def test_var_cmp_f(self): + u = UOp.variable("i", 1, 10) < 1 + self.assertFalse(u) + + def test_var_cmp_f2(self): + u = UOp.variable("i", 1, 10) > 11 + self.assertFalse(u) + + def test_or_true(self): + u = UOp.variable("b", False, True, dtypes.bool) | True + self.assertTrue(u) + + def test_or_false(self): + with self.assertRaises(ValueError): + u = UOp.variable("b", False, True, dtypes.bool) | False + self.assertTrue(u) + + def test_and_false(self): + u = UOp.variable("b", False, True, dtypes.bool) & False + self.assertFalse(u) + + def test_max(self): + x = UOp.variable("x", 1, 10) + y = UOp.variable("y", 5, 10) + u = x.maximum(y) + self.assertTrue(u < 20) + self.assertFalse(u < 3) + + def test_x_lt_x(self): + x = UOp.variable("i", 1, 10) + self.assertFalse(x < x) + + @unittest.expectedFailure + def test_x_lt_xp1(self): + x = UOp.variable("i", 1, 10) + self.assertTrue(x < (x+1)) + + def test_and_true(self): + with self.assertRaises(ValueError): + u = UOp.variable("b", False, True, dtypes.bool) & True + self.assertFalse(u) + + @unittest.expectedFailure + def test_var_cmp_range(self): + v = UOp.variable("i", 1, 10) + u = (v > 4) | (v < 6) + self.assertTrue(u) + + def test_var_cmp_assert(self): + with self.assertRaises(ValueError): + u = UOp.variable("i", 1, 10) < 5 + self.assertFalse(u) + + def test_plus_ordering_lt(self): + i = UOp.variable("i", 1, 10) + j = UOp.variable("j", 1, 10) + self.assertFalse((i+j) < (j+i)) + +if __name__ == '__main__': + unittest.main() \ No newline at end of file diff --git a/tinygrad_repo/test/unit/test_uop_spec.py b/tinygrad_repo/test/unit/test_uop_spec.py new file mode 100644 index 000000000..5fafb6d1c --- /dev/null +++ b/tinygrad_repo/test/unit/test_uop_spec.py @@ -0,0 +1,104 @@ +from __future__ import annotations +import unittest + +from tinygrad import Tensor +from tinygrad.helpers import DEBUG +from tinygrad.uop.ops import UOp, Ops, print_uops +from tinygrad.uop.spec import type_verify, ast_spec, tensor_uop_spec +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad import dtypes +from tinygrad.shape.view import View +from tinygrad.engine.realize import get_program +from tinygrad.device import Device + +class InvalidASTException(Exception): pass +def helper_test_verify_ast(*stores:UOp): + sink = UOp(Ops.SINK, dtypes.void, stores) + if DEBUG >= 3: + for op in stores: print(op) + try: type_verify(list(sink.toposort()), ast_spec) + except RuntimeError as e: raise InvalidASTException(e.args) + program = get_program(sink, Device[Device.DEFAULT].renderer) + + if DEBUG >= 6: print_uops(program.uops) + if DEBUG >= 4: print(program.src) + +class TestUOpSpec(unittest.TestCase): + def test_tiny_add(self): + dtype = dtypes.int + buf_0 = UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), (), 0) + buf_1 = UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), (), 1) + buf_2 = UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), (), 2) + a = UOp(Ops.LOAD, dtype, (buf_1.view(ShapeTracker.from_shape((32, 1))),)) + b = UOp(Ops.LOAD, dtype, (buf_2.view(ShapeTracker.from_shape((32, 1))),)) + store = UOp(Ops.STORE, dtypes.void, (buf_0.view(ShapeTracker.from_shape((32, 1))), a+b)) + helper_test_verify_ast(store) + + def test_exactly_one_full_shape(self): + dtype = dtypes.int + bufs = [UOp(Ops.DEFINE_GLOBAL, dtype.ptr(), (), i) for i in range(6)] + a = UOp(Ops.LOAD, dtype, (bufs[2].view(ShapeTracker.from_shape((32, 1))),)) + b = UOp(Ops.LOAD, dtype, (bufs[3].view(ShapeTracker.from_shape((32, 1))),)) + st0 = UOp.store(bufs[0], ShapeTracker.from_shape((32, 1)).to_uop(), a+b) + a = UOp(Ops.LOAD, dtype, (bufs[4].view(ShapeTracker.from_shape((32, 32))),)) + b = UOp(Ops.LOAD, dtype, (bufs[5].view(ShapeTracker.from_shape((32, 32))),)) + st1 = UOp.store(bufs[1], ShapeTracker.from_shape((32, 32)).to_uop(), a+b) + with self.assertRaises(InvalidASTException): helper_test_verify_ast(st0, st1) + + def test_no_implicit_broadcasting(self): + bufs = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), i) for i in range(2)] + a = UOp(Ops.LOAD, dtypes.float, (bufs[1].view(ShapeTracker.from_shape((4, 32))),)) + b = a + UOp(Ops.REDUCE_AXIS, dtypes.float, (a,), (Ops.MAX, (1,))) + st = UOp(Ops.STORE, dtypes.void, (bufs[0].view(ShapeTracker.from_shape((4, 32))), b)) + with self.assertRaises(InvalidASTException): helper_test_verify_ast(st) + + def test_shrink_ok(self): + bufs = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), i) for i in range(2)] + a = UOp(Ops.LOAD, dtypes.float, (bufs[1].view(ShapeTracker((View((32, 32), strides=(32, 1), offset=0, mask=None, contiguous=True),))),)) + b = UOp(Ops.LOAD, dtypes.float, (bufs[1].view(ShapeTracker((View((32, 32), strides=(0, 1), offset=0, mask=None, contiguous=False),))),)) + st = UOp.store(bufs[0].view(ShapeTracker.from_shape((32, 32))), a+b) + helper_test_verify_ast(st) + + def test_reduce_store(self): + bufs = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), i) for i in range(2)] + a = UOp(Ops.LOAD, dtypes.float, (bufs[1].view(ShapeTracker.from_shape((32, 1))),)) + r = UOp(Ops.REDUCE_AXIS, dtypes.float, (a,), (Ops.ADD, (0,))) + st = UOp.store(bufs[0], ShapeTracker.from_shape((32, 1)).to_uop(), r) + with self.assertRaises(InvalidASTException): helper_test_verify_ast(st) + + def test_reduce_add_store(self): + bufs = [UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), i) for i in range(2)] + a = UOp(Ops.LOAD, dtypes.float, (bufs[1].view(ShapeTracker.from_shape((32, 1))),)) + r = UOp(Ops.REDUCE_AXIS, dtypes.float, (a,), (Ops.ADD, (0,))) + st = UOp.store(bufs[0], ShapeTracker.from_shape((32, 1)).to_uop(), r+a) + with self.assertRaises(InvalidASTException): helper_test_verify_ast(st) + + def test_buffer_uops_st(self): + a = Tensor.randn(4, 4)+2 + helper_test_verify_ast(ast:=a.schedule()[-1].ast) + store_st = [u.st for u in ast.toposort() if u.op is Ops.STORE][0] + self.assertEqual(store_st, ShapeTracker.from_shape((4, 4))) + const_st = [u.st for u in ast.toposort() if u.op is Ops.CONST][0] + self.assertEqual(const_st, ShapeTracker.from_shape((1, 1)).expand((4, 4))) + + def test_assert_swizzle(self): + buf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) + a = UOp(Ops.LOAD, dtypes.float, (buf.view(ShapeTracker.from_shape((32, 1))),)) + r = UOp(Ops.REDUCE_AXIS, dtypes.float, (a,), (Ops.ADD, (0,))) + st = UOp.store(buf, ShapeTracker.from_shape((32, 1)).to_uop(), r.view(r.st.expand((32, 1)))+a) + with self.assertRaisesRegex(InvalidASTException, "UOp verification failed"): helper_test_verify_ast(st) + + def test_const_view_always_valid(self): + buf = UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0) + a = UOp.const(dtypes.int, 0).replace(src=(UOp(Ops.VIEW, dtypes.void, (), ShapeTracker.from_shape(())),)) + st = UOp.store(buf.view(ShapeTracker.from_shape(())), a.cast(dtypes.float)) + helper_test_verify_ast(st) + + def test_assert_masked_view_in_const(self): + t = Tensor(6).uop + a = t.replace(src=(t.src[0].replace(arg=t.st.reshape((1,)).pad(((0, 1),))),)) + with self.assertRaisesRegex(RuntimeError, "UOp verification failed"): + type_verify([a], tensor_uop_spec) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_uop_symbolic.py b/tinygrad_repo/test/unit/test_uop_symbolic.py new file mode 100644 index 000000000..e0bbdad2d --- /dev/null +++ b/tinygrad_repo/test/unit/test_uop_symbolic.py @@ -0,0 +1,897 @@ +#!/usr/bin/env python +import unittest, pickle, functools +import z3 + +from tinygrad.dtype import dtypes, ConstType +from tinygrad.codegen import full_rewrite +from tinygrad.codegen.devectorizer import sym +from tinygrad.helpers import Context +from tinygrad.uop.ops import UOp, Ops, graph_rewrite, sym_infer +from tinygrad import Variable +from tinygrad.uop.spec import z3_renderer + +def render(self) -> tuple[str, ConstType, ConstType]: + # NOTE: we need STORE so the ALU op has children + glbl = UOp(Ops.DEFINE_GLOBAL, dtypes.int.ptr(), arg=0) + uops = full_rewrite(UOp(Ops.STORE, dtypes.void, (glbl.index(UOp.const(dtypes.int, 0)), self)).sink()) + rewritten_uop = [uop for uop in uops if uop.op is Ops.STORE][0].src[-1] + return rewritten_uop.render(simplify=False), rewritten_uop.vmin, rewritten_uop.vmax + +def uconst(val): return UOp.const(dtypes.int, val) +def usum(ops): return functools.reduce(lambda x,y: x+y, ops) +def uand(ops): return functools.reduce(lambda x,y: x*y, ops) + +# *** leave tests the same + +class TestSymbolicPickle(unittest.TestCase): + def _test_pickle_unpickle(self, x): self.assertEqual(x, pickle.loads(pickle.dumps(x))) + def test_pickle_variable(self): self._test_pickle_unpickle(Variable("a", 3, 8)) + def test_pickle_variable_times_2(self): self._test_pickle_unpickle(Variable("a", 3, 8)*2) + +class TestSymbolic(unittest.TestCase): + def helper_test_variable(self, v, n, m, s): + rendered, nmin, nmax = render(v) + if isinstance(s, tuple): self.assertIn(rendered, s) + else: self.assertEqual(rendered, s) + self.assertEqual(nmin, n) + self.assertEqual(nmax, m) + solver = z3.Solver() + z3_sink = graph_rewrite(v.sink(v.simplify()), z3_renderer, ctx=(solver, {})) + expr, epxr_simplified = z3_sink.src[0].arg, z3_sink.src[1].arg + self.assertEqual(solver.check(expr != epxr_simplified), z3.unsat, "simplified expression not equal to original") + + def test_cmp_simple(self): + self.helper_test_variable(Variable("a", 3, 8) < 4, 0, 1, "(a<4)") + self.helper_test_variable(Variable("a", 3, 8) >= 8, 0, 1, "((a<8)!=True)") + + def test_ge(self): + self.helper_test_variable(Variable("a", 3, 8) >= 77, 0, 0, "False") + self.helper_test_variable(Variable("a", 3, 8) >= 9, 0, 0, "False") + self.helper_test_variable(Variable("a", 3, 8) >= 8, 0, 1, "((a<8)!=True)") + self.helper_test_variable(Variable("a", 3, 8) >= 4, 0, 1, "((a<4)!=True)") + self.helper_test_variable(Variable("a", 3, 8) >= 3, 1, 1, "True") + self.helper_test_variable(Variable("a", 3, 8) >= 2, 1, 1, "True") + + def test_lt(self): + self.helper_test_variable(Variable("a", 3, 8) < 77, 1, 1, "True") + self.helper_test_variable(Variable("a", 3, 8) < 9, 1, 1, "True") + self.helper_test_variable(Variable("a", 3, 8) < 8, 0, 1, "(a<8)") + self.helper_test_variable(Variable("a", 3, 8) < 4, 0, 1, "(a<4)") + self.helper_test_variable(Variable("a", 3, 8) < 3, 0, 0, "False") + self.helper_test_variable(Variable("a", 3, 8) < 2, 0, 0, "False") + self.helper_test_variable(Variable("a", 3, 4) < Variable("b", 5, 6), 1, 1, "True") + self.helper_test_variable(Variable("a", 3, 5) < Variable("b", 5, 6), 0, 1, "(a= 12, 0, 1, "((a<3)!=True)") + self.helper_test_variable(Variable("a", 0, 5)*4 >= 13, 0, 1, "((a<4)!=True)") + + def test_div_div(self): + self.helper_test_variable((Variable("a", 0, 1800)//10)//9, 0, 20, "(a//90)") + + def test_div_const_div(self): + a = Variable("a", 0, 124) + self.helper_test_variable((a//2+1)//2, 0, 31, "((a+2)//4)") + self.helper_test_variable(((-a)//2-1)//2, -31, 0, "(((a+2)//4)*-1)") + self.helper_test_variable(((-a)//2+10)//2, -26, 5, "((((a//2)*-1)+10)//2)") + + def test_div_const_div_wrong_sign(self): + a = Variable("a", 0, 124) + self.helper_test_variable(((a-10)//2+10)//2, 2, 33, "((((a+-10)//2)+10)//2)") + + def test_div_const_div_wrong_sign_divisor(self): + a = Variable("a", 0, 124) + self.helper_test_variable(((a+10)//-2+10)//-4, -1, 14, "(((((a//2)*-1)+5)//4)*-1)") + + def test_neg_mod(self): + a = Variable("a", 0, 124) + self.helper_test_variable((-a)%4, -3, 0, "((a%4)*-1)") + self.helper_test_variable(a%-4, 0, 3, "(a%-4)") + + def test_distribute_mul(self): + self.helper_test_variable(usum([Variable("a", 0, 3), Variable("b", 0, 5)])*3, 0, 24, "((a*3)+(b*3))") + self.helper_test_variable((1+Variable("a", 0, 3))*(-2)+12, 4, 10, "((a*-2)+10)") + + def test_mod_mul_sum(self): + self.helper_test_variable(usum([Variable("b", 0, 2), Variable("a", 0, 5)*10])%9, 0, 7, ("(b+a)", "(a+b)")) + + def test_sum_0(self): + self.helper_test_variable(usum([Variable("a", 0, 7)]), 0, 7, "a") + + def test_mod_remove(self): + self.helper_test_variable(Variable("a", 0, 6)%100, 0, 6, "a") + + def test_big_mod(self): + self.helper_test_variable(Variable("a", -20, 20)%10, -9, 9, "(a%10)") + self.helper_test_variable(Variable("a", -20, 0)%10, -9, 0, "(((a*-1)%10)*-1)") + self.helper_test_variable(Variable("a", -20, 1)%10, -9, 9, "(a%10)") # TODO: tighter max + self.helper_test_variable(Variable("a", 0, 20)%10, 0, 9, "(a%10)") + self.helper_test_variable(Variable("a", -1, 20)%10, -9, 9, "(a%10)") # TODO: tighter min + + def test_ge_remove(self): + self.helper_test_variable(Variable("a", 0, 6) >= 25, 0, 0, "False") + + def test_lt_remove(self): + self.helper_test_variable(Variable("a", 0, 6) < -3, 0, 0, "False") + self.helper_test_variable(Variable("a", 0, 6) < 3, 0, 1, "(a<3)") + self.helper_test_variable(Variable("a", 0, 6) < 8, 1, 1, "True") + + def test_lt_sum_remove(self): + self.helper_test_variable(Variable("a", 0, 6) + 2 < 3, 0, 1, "(a<1)") + + def test_lt_simple_factor(self): + self.helper_test_variable((Variable("a", 0, 6)*6+Variable("b", 0, 6)*6) < 8, 0, 1, "(((a*3)+(b*3))<4)") + + def test_lt_sum_factor_rhs_partial(self): + self.helper_test_variable((Variable("a", 0, 6)*6 + Variable("b", 0, 6)*4 + Variable("c", 0, 6)*8) < 4, 0, 1, + ("((((a*3)+(b*2))+(c*4))<2)", "(((b*2)+((a*3)+(c*4)))<2)")) + + def test_lt_sum_factor_rhs_all(self): + self.helper_test_variable((Variable("a", 0, 6)*6 + Variable("b", 0, 6)*4 + Variable("c", 0, 6)*8) < 2, 0, 1, + ("((((a*3)+(b*2))+(c*4))<1)", "(((b*2)+((a*3)+(c*4)))<1)")) + + def test_and_fold(self): + self.helper_test_variable(uand([uconst(0), Variable("a", 0, 1)]), 0, 0, "0") + + def test_and_remove(self): + self.helper_test_variable(uand([uconst(1), Variable("a", 0, 1)]), 0, 1, "a") + + def test_mod_factor_negative(self): + self.helper_test_variable(usum([uconst(-29), Variable("a", 0, 10), Variable("b", 0, 10)*28]) % 28, -27, 27, "(((a+(b*28))+-29)%28)") + self.helper_test_variable(usum([uconst(-29), Variable("a", 0, 100), Variable("b", 0, 10)*28]) % 28, -27, 27, "(((a+(b*28))+-29)%28)") + + def test_sum_combine_num(self): + self.helper_test_variable(usum([uconst(29), Variable("a", 0, 10), uconst(-23)]), 6, 16, "(a+6)") + + def test_sum_num_hoisted_and_factors_cancel_out(self): + self.helper_test_variable(usum([Variable("a", 0, 1) * -4 + 1, Variable("a", 0, 1) * 4]), 1, 1, "1") + + @unittest.expectedFailure # only correct for floordiv, not truncdiv + def test_div_cancel(self): + self.helper_test_variable(usum([uconst(-40), Variable("a", 0, 10)*2, Variable("b", 0, 10)*40])//40, -1, 9, "(b+-1)") + + def test_div_cancel_correct(self): + with Context(CORRECT_DIVMOD_FOLDING=1): + self.helper_test_variable(usum([uconst(-40), Variable("a", 0, 10)*2, Variable("b", 0, 10)*40])//40, -1, 9, "(((a+(b*20))+-20)//20)") + + @unittest.expectedFailure # only correct for floordiv, not truncdiv + def test_mod_cancel(self): + self.helper_test_variable(usum([uconst(-40), Variable("a", 0, 10)*2, Variable("b", 0, 10)*40]) % 40, 0, 20, "(a*2)") + + def test_mod_cancel_correct(self): + with Context(CORRECT_DIVMOD_FOLDING=1): + self.helper_test_variable(usum([uconst(-40), Variable("a", 0, 10)*2, Variable("b", 0, 10)*40]) % 40, -38, 38, "((((a+(b*20))+-20)%20)*2)") + + def test_mul_div(self): + self.helper_test_variable((Variable("a", 0, 10)*4)//4, 0, 10, "a") + + def test_add_div(self): + # careful about the lower bounds and upper bounds + self.helper_test_variable((Variable("a", 0, 5)-2)//4, 0, 0, "0") + self.helper_test_variable((Variable("a", 0, 5)-1)//4, 0, 1, "((a+-1)//4)") + self.helper_test_variable((Variable("a", 0, 5))//4, 0, 1, "(a//4)") + self.helper_test_variable((Variable("a", 0, 5)+1)//4, 0, 1, "((a+1)//4)") + self.helper_test_variable((Variable("a", 0, 5)+2)//4, 0, 1, "((a+2)//4)") + self.helper_test_variable((Variable("a", 0, 5)+3)//4, 0, 2, "((a+3)//4)") + self.helper_test_variable((Variable("a", 0, 5)+4)//4, 1, 2, "((a//4)+1)") + self.helper_test_variable((Variable("a", 0, 5)+5)//4, 1, 2, "(((a+1)//4)+1)") + + def test_div_neg_rem(self): + self.helper_test_variable((-Variable("a", 0, 255)+256)//2, 0, 128, "((((a+1)//2)*-1)+128)") + + def test_mul_div_factor_mul(self): + self.helper_test_variable((Variable("a", 0, 10)*8)//4, 0, 20, "(a*2)") + + def test_mul_div_factor_mul_neg(self): + self.helper_test_variable((Variable("a", 0, 10)*-8+16)//4, -16, 4, "((a*-2)+4)") + + def test_mul_div_factor_div(self): + self.helper_test_variable((Variable("a", 0, 10)*4)//8, 0, 5, "(a//2)") + + def test_mul_div_factor_div_neg(self): + self.helper_test_variable((Variable("a", 0, 10)*-4+4)//8, -4, 0, "(((a*-1)+1)//2)") + + def test_mod_gcd_factor_neg(self): + self.helper_test_variable((Variable("a", 0, 10)*-4+4)%8, -4, 4, "((((a*-1)+1)%2)*4)") + + def test_mod_gcd_fold_neg(self): + self.helper_test_variable((Variable("a", 0, 10)*-8+20)%4, 0, 0, "0") + + def test_sum_div_partial_remove(self): + self.helper_test_variable(usum([Variable("idx0", 0, 127)*4, Variable("idx2", 0, 3)])//4, 0, 127, "idx0") + + def test_cdiv_const_evaluation(self): + self.helper_test_variable((Variable("a", 0, 2)-12)//8, -1, -1, "-1") + self.helper_test_variable((-Variable("a", 0, 2))//7, 0, 0, "0") + + def test_cmod_const_evaluation(self): + self.helper_test_variable((Variable("a", 1, 1)*-3)%8, -3, -3, "-3") + self.helper_test_variable((-Variable("a", 10, 10))%7, -3, -3, "-3") + + def test_div_numerator_negative(self): + self.helper_test_variable((Variable("idx", 0, 9)*-10)//11, -8, 0, "(((idx*10)//11)*-1)") + + def test_div_into_mod(self): + self.helper_test_variable((Variable("idx", 0, 16)*4)%8//4, 0, 1, "(idx%2)") + + def test_div_neg_cancel(self): + self.helper_test_variable((-Variable("idx", 0, 100)+199)//-4 + 50, 1, 26, "((idx//4)+1)") + self.helper_test_variable((-Variable("idx", 0, 100)+200)//-4 + 50, 0, 25, "((idx+3)//4)") + self.helper_test_variable((-Variable("idx", 0, 100)+201)//-4 + 50, 0, 25, "((idx+2)//4)") + self.helper_test_variable((-Variable("idx", 0, 100))//2, -50, 0, "((idx//2)*-1)") + self.helper_test_variable(Variable("idx", 0, 100)//-2, -50, 0, "((idx//2)*-1)") + + def test_sum_div_big_const(self): + gidx0 = Variable("gidx0", 0, 24) + self.helper_test_variable((gidx0+19)//20, 0, 2, "((gidx0+19)//20)") + self.helper_test_variable((gidx0+20)//20, 1, 2, "((gidx0//20)+1)") + self.helper_test_variable((gidx0+21)//20, 1, 2, "(((gidx0+1)//20)+1)") + + def test_sum_div_complex1(self): + gidx0 = Variable("gidx0", 0, 24) + gidx1 = Variable("gidx1", 0, 1) + gidx2 = Variable("gidx2", 0, 255) + lidx0 = Variable("lidx0", 0, 1) + lidx1 = Variable("lidx1", 0, 15) + lidx2 = Variable("lidx2", 0, 3) + alu0 = gidx2*640+gidx1*160+(gidx0//5)*2+lidx0*320+lidx1*10 + self.helper_test_variable((alu0+lidx2*2+1)//20, 0, 8192, + ("((((((gidx0//5)+lidx2)//5)+lidx1)//2)+(((gidx2*32)+(gidx1*8))+(lidx0*16)))", + "(((lidx1+((lidx2+(gidx0//5))//5))//2)+((gidx2*32)+((gidx1*8)+(lidx0*16))))", + "((((gidx1*8)+(gidx2*32))+(lidx0*16))+((lidx1+((lidx2+(gidx0//5))//5))//2))")) + + def test_sum_div_complex2(self): + gidx0 = Variable("gidx0", 0, 7) + lidx2 = Variable("lidx2", 0, 1) + lidx3 = Variable("lidx3", 0, 1) + self.helper_test_variable((gidx0*4+lidx2*2+1)//10, 0, 3, ("(((gidx0*2)+lidx2)//5)", "((lidx2+(gidx0*2))//5)")) + self.helper_test_variable((gidx0*4+lidx2*2+lidx3)//10, 0, 3, ("(((gidx0*2)+lidx2)//5)", "((lidx2+(gidx0*2))//5)")) + self.helper_test_variable((gidx0*2+lidx2)//10, 0, 1, "(gidx0//5)") + + def test_sum_div_complex3(self): + gidx0 = Variable("gidx0", 0, 7) + lidx2 = Variable("lidx2", 0, 12) + lidx3 = Variable("lidx3", 0, 1) + self.helper_test_variable((gidx0*4+lidx2*2+lidx3)//12, 0, 4, ("(((lidx2//2)+gidx0)//3)", "((gidx0+(lidx2//2))//3)")) + self.helper_test_variable((lidx2*2+gidx0*4+lidx3)//12, 0, 4, ("(((lidx2//2)+gidx0)//3)", "((gidx0+(lidx2//2))//3)")) + + def test_sum_mul_distribute(self): + gidx0 = Variable("gidx0", 0, 7) + lidx2 = Variable("lidx2", 0, 12) + lidx3 = Variable("lidx3", 0, 1) + self.helper_test_variable((gidx0+lidx2+lidx3)*4, 0, 80, + ("(((gidx0*4)+(lidx2*4))+(lidx3*4))","((lidx3*4)+((gidx0*4)+(lidx2*4)))")) + + @unittest.expectedFailure + def test_variable_divmod(self): + start_pos = Variable("start_pos", 0, 127) + v = start_pos + 1 + idx0 = Variable("idx0", 0, 2) + idx1 = Variable("idx1", 0, start_pos) + self.helper_test_variable((idx0*v+idx1)//v, 0, 2, "(idx0)") + self.helper_test_variable((idx0*v+idx1)%v, 0, start_pos, "idx1") + + def test_divmod_variable_denom_fold_to_const(self): + x = Variable("x", 20, 23) + y = Variable("y", 8, 10) + self.helper_test_variable(x//y, 2, 2, "2") + self.helper_test_variable(x%y, 0, 7, "(x+(y*-2))") + # ensure all 4 corners are checked + x = Variable("x", -10, 10) + y = Variable("y", -8, 9) + self.helper_test_variable(x//y, -2147483648, 2147483647, "(x//y)") + self.helper_test_variable(x%y, -2147483648, 2147483647, "(x%y)") + + def test_div_neg_all_range(self): + gidx = Variable("gidx", 0, 124) + lidx = Variable("lidx", 0, 7) + self.helper_test_variable((-gidx*8-lidx+999)//-4 + 250, 1, 250, "(((gidx*2)+(lidx//4))+1)") + self.helper_test_variable((-gidx*8-lidx+1000)//-4 + 250, 0, 250, "((gidx*2)+((lidx+3)//4))") + self.helper_test_variable((-gidx*8-lidx+1001)//-4 + 250, 0, 250, "((gidx*2)+((lidx+2)//4))") + self.helper_test_variable((-gidx*8-lidx+1002)//-4 + 250, 0, 250, "((gidx*2)+((lidx+1)//4))") + + def test_div_neg_then_neg(self): + # taken from arange opts + lidx0 = Variable("lidx0", 0, 7) + lidx1 = Variable("lidx1", 0, 7) + alu2 = -lidx0-lidx1 + self.helper_test_variable((((alu2+14)//(-32))+4), 4, 4, "4") + self.helper_test_variable(-(((alu2+14)//(-32))+4), -4, -4, "-4") + self.helper_test_variable((((alu2+134)//(-32))+4), 0, 1, "(((lidx0+lidx1)+25)//32)") + self.helper_test_variable((((alu2+142)//(-32))+4), 0, 0, "0") + self.helper_test_variable((((alu2+150)//(-32))+4), 0, 0, "0") + self.helper_test_variable((((alu2+158)//(-32))+4), 0, 0, "0") + + def test_div_mod_recombine(self): + gidx = Variable("gidx", 0, 124) + self.helper_test_variable(gidx%4+(gidx//4)*4, 0, 124, "gidx") + self.helper_test_variable((gidx//4)*4+gidx%4, 0, 124, "gidx") + + def test_div_mod_recombine_folded_mod(self): + a = Variable("a", 0, 2) + b = Variable("b", 0, 100) + self.helper_test_variable((31 * a + 1) % 30 + ((31 * a + 1) // 30) * 30, 1, 63, "((a*31)+1)") + with self.assertRaises(AssertionError): + self.helper_test_variable((31 * b + 1) % 18 + ((31 * b + 1) // 18) * 18, 1, 3101, "((b*31)+1)") + + def test_div_mod_recombine_with_gcd(self): + b = Variable("b", 0, 100) + exp = (16 * b + 2) % 18 + ((16 * b + 2) // 18) * 18 + self.helper_test_variable(exp, 2, 1602, "((b*16)+2)") + with self.assertRaises(AssertionError): + self.helper_test_variable((30 * b + 1) % 18 + ((30 * b + 1) // 18) * 18, 1, 3001, "((b*30)+1)") + + def test_arange_unrolled4(self): + gidx = Variable("gidx", 0, 2559) + unrolled_div = (gidx+2561)//4+(gidx+2562)//4+(gidx+2560)//4+(gidx+2559)//4 + self.helper_test_variable(unrolled_div, 2559, 5118, "(gidx+2559)") + + def test_arange_unrolled4_mul(self): + gidx = Variable("gidx", 0, 2559) + unrolled_div = 2*((gidx+2561)//4)+2*((gidx+2562)//4)+2*((gidx+2560)//4)+2*((gidx+2559)//4) + self.helper_test_variable(unrolled_div, 5118, 10236, "((gidx*2)+5118)") + + def test_arange_unrolled4_small(self): + gidx = Variable("gidx", 0, 3) + unrolled_div = (gidx)//4+(gidx+2)//4+(gidx+3)//4+(gidx+1)//4 + self.helper_test_variable(unrolled_div, 0, 3, "gidx") + + gidx = Variable("gidx", 0, 2) + unrolled_div = (gidx)//4+(gidx+2)//4+(gidx+3)//4+(gidx+1)//4 + self.helper_test_variable(unrolled_div, 0, 2, "gidx") + + gidx = Variable("gidx", 0, 1) + unrolled_div = (gidx)//4+(gidx+2)//4+(gidx+3)//4+(gidx+1)//4 + self.helper_test_variable(unrolled_div, 0, 1, "gidx") + + def test_arange_unrolled2(self): + gidx = Variable("gidx", 0, 2559) + unrolled_div = (gidx+2559)//2+(gidx+2560)//2+3 + self.helper_test_variable(unrolled_div, 2562, 5121, "(gidx+2562)") + + def test_arange_unrolled2_neg(self): + ridx = Variable("ridx", 0, 255) + unrolled_div = -((255-ridx)//2) - ((256-ridx)//2) + self.helper_test_variable(unrolled_div, -255, 0, "(ridx+-255)") + + def test_gated_load(self): + idx = Variable("idx", 0, 24) + self.helper_test_variable(idx//4, 0, 6, "(idx//4)") + # TODO: simplify the true branch + self.helper_test_variable((idx<4).where(idx//4, idx.const_like(-1)), -1, 6, "((idx//4) if (idx<4) else -1)") + + def test_idiv_lt(self): + idx = Variable("idx", 0, 24) + self.helper_test_variable((idx//4<3), 0, 1, "(idx<12)") + self.helper_test_variable(((idx-20)//4<-3), 0, 1, "(idx<5)") + self.helper_test_variable(((idx-10)//4<0), 0, 1, "(idx<7)") + self.helper_test_variable((idx//-4<-3), 0, 1, "(((idx//4)*-1)<-3)") + + def test_simplex_lt(self): + a = Variable("a", 0, 3) + b = Variable("b", 0, 3) + c = Variable("c", 0, 3) + d = Variable("d", -3, 3) + self.helper_test_variable((a<1).ne(True), 0, 1, "((a<1)!=True)") + self.helper_test_variable((a+b<1).ne(True), 0, 1, "(((a+b)<1)!=True)") + self.helper_test_variable((a*3+b*4<1).ne(True), 0, 1, "(((a+b)<1)!=True)") + self.helper_test_variable((a*(-3)+b*4<1).ne(True), 0, 1, "((((a*-3)+(b*4))<1)!=True)") # negative coeff, should not be simplified + self.helper_test_variable((a*3+d*4<1).ne(True), 0, 1, "((((a*3)+(d*4))<1)!=True)") # var can be negative, should not be simplified + self.helper_test_variable((a+b+c*2<1).ne(True), 0, 1, ("((((a+b)+c)<1)!=True)", "(((c+(a+b))<1)!=True)", '(((b+(a+c))<1)!=True)')) + self.helper_test_variable((a+b*2+c*4<1).ne(True), 0, 1, ("((((a+b)+c)<1)!=True)", "(((c+(a+b))<1)!=True)", '(((b+(a+c))<1)!=True)')) + + def test_where_removal(self): + cond = Variable("a", 0, 3) < 2 + u1, u0 = cond.ufix(1), cond.ufix(0) + self.helper_test_variable(cond, 0, 1, "(a<2)") + self.helper_test_variable(cond.where(u1, u0), 0, 1, "(a<2)") + self.helper_test_variable(cond.where(u1, u0).where(u1, u0), 0, 1, "(a<2)") + + def test_where_combine(self): + cond = Variable("x", 0, 3) < 2 + a = Variable("a", 0, 3) + b = Variable("b", 0, 3) + aa = cond.where(a, a.ufix(0)) + bb = cond.where(b, b.ufix(1)) + self.helper_test_variable(aa, 0, 3, "(a if (x<2) else 0)") + self.helper_test_variable(bb, 0, 3, "(b if (x<2) else 1)") + self.helper_test_variable(aa+bb, 0, 6, "((a+b) if (x<2) else 1)") + self.helper_test_variable(aa.maximum(bb), 0, 3, "(max(a, b) if (x<2) else 1)") + + # not combining because it increased total ALU + c = Variable("c", 0, 3) + cc = cond.where(c, c+1) + self.helper_test_variable(bb+cc, 0, 7, "((b if (x<2) else 1)+(c if (x<2) else (c+1)))") + + # not combining # TODO: can combine if it can further simplify? + ab = cond.where(a, b) + ba = cond.where(b, a) + self.helper_test_variable(ab+ba, 0, 6, "((a if (x<2) else b)+(b if (x<2) else a))") + + # not combining # TODO: can combine if one is identity element const + self.helper_test_variable(aa+ab, 0, 6, "((a if (x<2) else b)+(a if (x<2) else 0))") + + def test_negation_in_where(self): + cond = Variable("x", 0, 3) < 2 + a = Variable("a", 0, 3) + b = Variable("b", 0, 3) + w = cond.logical_not().where(a, b) + self.helper_test_variable(w, 0, 3, "(b if (x<2) else a)") + + def test_neg_in_comp(self): + a = Variable("a", 0, 3) + b = Variable("b", 0, 3) + self.helper_test_variable(-a<-b, False, True, "(b 2 + a = Variable("a", 0, 3) + b = Variable("b", 0, 3) + expr = cond1.where(cond2.where(a, b), b) + self.helper_test_variable(expr, 0, 3, "(a if ((s<6)&(2 (a if (s<5) else b) + self.helper_test_variable(expr, 0, 3, "(a if (s<5) else b)") + + def test_symbolic_div(self): + # from symbolic arange + a = Variable("a", 1, 10) + denominator = ((a*-2)+1) + numerator = (((((a*2)+-1)*2)+1)*a) + self.helper_test_variable(denominator, -19, -1, "((a*-2)+1)") + self.helper_test_variable(numerator, 3, 390, "(a*((a*4)+-1))") + self.helper_test_variable((numerator//denominator)<=0, 1, 1, "True") + +class TestSymbolicNumeric(unittest.TestCase): + def helper_test_numeric(self, f): + MIN, MAX = 0, 10 + # one number + for i in range(MIN, MAX): + v = graph_rewrite(f(uconst(i)), sym) + self.assertEqual(v.vmin, v.vmax) + self.assertEqual(v.vmin, f(i)) + for kmin in range(MIN, MAX): + for kmax in range(MIN, MAX): + if kmin > kmax: continue + v = f(Variable("tmp", kmin, kmax)) + values = [f(rv) for rv in range(kmin, kmax+1)] + # the min and max may not be exact + self.assertLessEqual(v.vmin, min(values)) + self.assertGreaterEqual(v.vmax, max(values)) + + def test_mod_4(self): self.helper_test_numeric(lambda x: (x%4)) + def test_div_4(self): self.helper_test_numeric(lambda x: (x//4)) + def test_plus_1_div_2(self): self.helper_test_numeric(lambda x: (x+1)//2) + def test_plus_1_mod_2(self): self.helper_test_numeric(lambda x: (x+1)%2) + def test_times_2(self): self.helper_test_numeric(lambda x: x*2) + def test_times_2_plus_3(self): self.helper_test_numeric(lambda x: x*2 + 3) + def test_times_2_plus_3_mod_4(self): self.helper_test_numeric(lambda x: (x*2 + 3)%4) + def test_times_2_plus_3_div_4(self): self.helper_test_numeric(lambda x: (x*2 + 3)//4) + def test_times_2_plus_3_div_4_mod_4(self): self.helper_test_numeric(lambda x: ((x*2 + 3)//4)%4) + +class TestSymbolicVars(unittest.TestCase): + def test_simple(self): + z = uconst(0) + a = Variable("a", 0, 10) + b = Variable("b", 0, 10) + c = Variable("c", 0, 10) + assert z.vars() == z.vars() == set() + print(a.vars()) + assert a.vars() == a.vars() == {a} + m = a * 3 + assert m.vars() == {a} + s = usum([a, b, c]) + assert s.vars() == {a, b, c} + + def test_compound(self): + a = Variable("a", 0, 10) + b = Variable("b", 0, 10) + c = Variable("c", 0, 10) + assert (a + b * c).vars() == {a, b, c} + assert (a % 3 + b // 5).vars() == {a, b} + # TODO: fix me + with self.assertRaises(AssertionError): + assert (a + b + c - a).vars() == {b, c} + + def test_dedup(self): + a = Variable("a", 0, 10) + assert (a * a).vars() == {a} + assert (a//4 + a//6).vars() == {a} + +class TestSymInfer(unittest.TestCase): + def test_sym_infer(self): + a = Variable("a", 0, 10) + b = Variable("b", 0, 10) + c = Variable("c", 0, 10) + var_vals = {a: 2, b: 3, c: 4} + assert sym_infer(5, var_vals) == 5 + assert sym_infer(4.2, var_vals) == 4.2 + assert sym_infer(a, var_vals) == 2 + assert sym_infer(b, var_vals) == 3 + assert sym_infer(a+b, var_vals) == 5 + assert sym_infer(a-b, var_vals) == -1 + assert sym_infer(a+b+c, var_vals) == 9 + assert sym_infer(a*b, var_vals) == 6 + assert sym_infer(a*b+c, var_vals) == 10 + def test_sym_infer_cdiv_cmod(self): + a = Variable("a", -1000, 1) + b = Variable("b", -1000, 1) + var_vals = {a: 1, b: -1000} + assert sym_infer(a%b, var_vals) == 1 + assert sym_infer(a//b, var_vals) == 0 + +""" +@unittest.skip("not supported on uops yet") +class TestSymbolicSymbolicOps(unittest.TestCase): + def test_node_divmod_node(self): + i = Variable("i", 1, 10) + idx0 = Variable("idx0", 0, i*3-1) + assert uconst(0) // (Variable("i", 1, 10)*128) == 0 + assert uconst(0) % (Variable("i", 1, 10)*128) == 0 + assert uconst(127) // (Variable("i", 1, 10)*128) == 0 + assert uconst(127) % (Variable("i", 1, 10)*128) == 127 + assert 127 // (Variable("i", 1, 10)*128) == 0 + assert 127 % (Variable("i", 1, 10)*128) == 127 + assert uconst(128) // (Variable("i", 1, 10)*128 + 128) == 0 + assert uconst(128) % (Variable("i", 1, 10)*128 + 128) == 128 + assert 128 // (Variable("i", 1, 10)*128 + 128) == 0 + assert 128 % (Variable("i", 1, 10)*128 + 128) == 128 + assert 0 // (Variable("i", 1, 10)*128) == 0 + assert 0 % (Variable("i", 1, 10)*128) == 0 + assert idx0 // (i*3) == 0 + assert idx0 % (i*3) == idx0 + assert i // i == 1 + assert i % i == 0 + assert 128 // uconst(4) == 32 + assert 128 % uconst(4) == 0 + assert uconst(128) // uconst(4) == 32 + assert uconst(128) % uconst(4) == 0 + + def test_mulnode_divmod_node(self): + i = Variable("i", 1, 10) + idx0 = Variable("idx0", 0, 31) + # assert (idx0*(i*4+4)) // (i+1) == (idx0*4) + # assert (idx0*(i*4+4)) % (i+1) == 0 + assert (idx0*i) % i == 0 + + def test_sumnode_divmod_sumnode(self): + i = Variable("i", 1, 10) + # idx0 = Variable("idx0", 0, 7) + # idx1 = Variable("idx1", 0, 3) + # idx2 = Variable("idx2", 0, i) + # assert (idx0*(i*4+4)+idx1*(i+1)+idx2) // (i+1) == idx0*4+idx1 + # assert (idx0*(i*4+4)+idx1*(i+1)+idx2) % (i+1) == idx2 + assert (i+1) // (i*128+128) == 0 + assert (i+1) % (i*128+128) == (i+1) + # assert (i+1+idx2) // (i+1) == 1 + # assert (i+1+idx2) % (i+1) == idx2 + # assert (idx0*(i*4+4)+i+1+idx2) // (i+1) == idx0*4+1 + # assert (idx0*(i*4+4)+i+1+idx2) % (i+1) == idx2 + # assert (i*128+128)*2 // (i*128+128) == 2 + # assert (i*128+128)*2 % (i*128+128) == 0 + + def test_sumnode_div_uconst_no_factoring(self): + gid = Variable("gid", 0, 1023) + lid = Variable("lid", 0, 3) + expr_before_div = uconst(-1019)-4*lid-gid + unfactored_expr = Node.__floordiv__(expr_before_div, uconst(-16), False) + factored_expr = Node.__floordiv__(expr_before_div, uconst(-16), True) + self.assertEqual(unfactored_expr.render(), "(((lid*4)+1019+gid)//16)") + self.assertEqual(factored_expr.render(), "(((((3+gid)//4)+2+lid)//4)+63)") + + def test_mod_node_max(self): + i = Variable("i", 1, 128) + gidx0 = Variable("gidx0", 0, i) + mod = gidx0 % 8 + assert isinstance(mod, ModNode) and mod.a == gidx0 and mod.b == 8 + mod = gidx0 % 2 + assert isinstance(mod, ModNode) and mod.a == gidx0 and mod.b == 2 + + gidx0 = Variable("gidx0", 0, i*8+7) + mod = gidx0 % 8 + assert isinstance(mod, ModNode) and mod.a == gidx0 and mod.b == 8 + mod = gidx0 % 2 + assert isinstance(mod, ModNode) and mod.a == gidx0 and mod.b == 2 + + def test_nested_variable_mod(self): + i = Variable("i", 1, 5) + idx0 = Variable("idx0", 0, i) + with self.assertRaises(AssertionError): + assert idx0 % 2 == idx0 + + def test_num_node_mul_node(self): + a = Variable("a", 1, 5) + b = uconst(2) * a + assert b == a * 2 + assert isinstance(b, MulNode) + b = uconst(1) * a + assert b == a + assert isinstance(b, Variable) + b = uconst(0) * a + assert b == 0 + assert isinstance(b, uconst) + + def test_substitute(self): + a = Variable("idx0", 1, 3) + b = a + 1 + c = b.substitute({a: uconst(1)}) + assert c == uconst(2) +""" + +class TestSymbolicRealWorld(unittest.TestCase): + def test_resnet_half(self): + gidx0 = Variable("gidx0", 0, 3) + gidx1 = Variable("gidx1", 0, 127) + gidx2 = Variable("gidx2", 0, 7) + lidx3 = Variable("lidx3", 0, 7) + lidx4 = Variable("lidx4", 0, 1) + lidx5 = Variable("lidx5", 0, 15) + + idx:UOp = ((((1+lidx5)%16)*49)+(((262145+lidx5)//16)*802816)+(gidx0*3211264)+(gidx1*784)+(gidx2*8)+(lidx4*100352)+-13151129600+lidx3) + idx = graph_rewrite(idx, sym) + #print(idx.render()) + # NOTE: this used to have 13,151,129,600 in the output which is out of int32 range. + self.assertIn(idx.render(), + ("((((((((((lidx5+1)//16)*802816)+(((lidx5+1)%16)*49))+(gidx0*3211264))+(gidx1*784))+(gidx2*8))+(lidx4*100352))+lidx3)+2207744)", + '((lidx3+((((((((lidx5+1)//16)*802816)+(((lidx5+1)%16)*49))+(gidx0*3211264))+(gidx1*784))+(gidx2*8))+(lidx4*100352)))+2207744)', + '((lidx3+((lidx4*100352)+((gidx2*8)+((gidx1*784)+((gidx0*3211264)+((((lidx5+1)//16)*802816)+(((lidx5+1)%16)*49)))))))+2207744)', + )) + +class TestBounds(unittest.TestCase): + def test_unrolled_arange(self): + # #include + # using namespace metal; + # kernel void r_2560_640_4(device int* data0, uint3 gid [[threadgroup_position_in_grid]], uint3 lid [[thread_position_in_threadgroup]]) { + # int gidx0 = gid.x; /* 2560 */ + # int alu0 = (gidx0*(-1)); + # int alu1 = max((int)((-640)),((((alu0+2559)/(-4))*(-1))+(-640))); + # int alu2 = max((int)((-640)),((((alu0+2560)/(-4))*(-1))+(-640))); + # int alu3 = max((int)((-640)),((((alu0+2561)/(-4))*(-1))+(-640))); + # int alu4 = max((int)((-640)),((((alu0+2562)/(-4))*(-1))+(-640))); + # *(data0+gidx0) = ((alu1*(-1))+(alu2*(-1))+(alu4*(-1))+(alu3*(-1))+(-1)); + # } + gidx0 = Variable("gidx0", 0, 2559) + assert gidx0.vmin == 0 and gidx0.vmax == 2559 + alu0 = gidx0 * -1 + assert alu0.vmin == -2559 and alu0.vmax == 0 + assert (alu0+2559).vmin == 0 and (alu0+2559).vmax == 2559 + assert ((alu0+2559)//-4).vmin == -639 and ((alu0+2559)//-4).vmax == 0 + assert (((alu0+2559)//-4)*(-1)).vmin == 0 and (((alu0+2559)//-4)*(-1)).vmax == 639 + +class TestFuzzFailure(unittest.TestCase): + def test_fuzz_failure1(self): + v1=Variable('v1', 0, 8) + v2=Variable('v2', 0, 2) + v3=Variable('v3', 0, 1) + expr = (((((((((((((((((((((((0//4)%2)//8)+-2)+-4)+-3)+v1)+-4)+v2)+-2)+v3)+v2)//3)%7)*1)//2)+v2)*-1)+2)+1)+0)+-3)+v3) + v1_val, v2_val, v3_val = v1.const_like(8), v2.const_like(0), v3.const_like(0) + num = expr.simplify().substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + rn = expr.substitute({v1:v1_val, v2:v2_val, v3:v3_val}).ssimplify() + assert num==rn, f"{num} != {rn}" + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_uop_vmin_vmax.py b/tinygrad_repo/test/unit/test_uop_vmin_vmax.py new file mode 100644 index 000000000..cc1ca49dd --- /dev/null +++ b/tinygrad_repo/test/unit/test_uop_vmin_vmax.py @@ -0,0 +1,322 @@ +import unittest, math +from tinygrad.uop.ops import UOp, Ops +from tinygrad.dtype import dtypes + +class TestVminVmaxProperties(unittest.TestCase): + def test_vmin_vmax_constant(self): + # vmin and vmax for a constant + uop = UOp.const(dtypes.int32, 42) + self.assertEqual(uop.vmin, 42) + self.assertEqual(uop.vmax, 42) + + def test_vmin_vmax_cmpne(self): + uop = UOp.const(dtypes.int32, 42) + def test_bool(u, x): + self.assertEqual(u.vmin, x) + self.assertEqual(u.vmax, x) + test_bool(uop != 42, False) + test_bool(uop != 43, True) + test_bool(uop != 41, True) + + def test_vmin_vmax_addition_with_variable(self): + # vmin and vmax for addition with a variable + x = UOp.variable('x', 10, 20) + uop = x + 5 + self.assertEqual(uop.vmin, 15) + self.assertEqual(uop.vmax, 25) + + def test_vmin_vmax_subtraction_with_variable(self): + x = UOp.variable('x', 10, 20) + uop = x - 5 + self.assertEqual(uop.vmin, 5) + self.assertEqual(uop.vmax, 15) + uop = 5 - x + self.assertEqual(uop.vmin, -15) + self.assertEqual(uop.vmax, -5) + + def test_vmin_vmax_and_with_variable(self): + x = UOp.variable('x', 10, 20) + uop = x & 5 + self.assertEqual(uop.vmin, 0) + self.assertEqual(uop.vmax, 5) + + # this can be improved + uop = x & 15 + self.assertEqual(uop.vmin, 0) + self.assertEqual(uop.vmax, 15) + + # this can be improved + uop = x & 32 + self.assertEqual(uop.vmin, 0) + self.assertEqual(uop.vmax, 20) + + def test_vmin_vmax_multiplication_with_variable(self): + # vmin and vmax for multiplication with a variable + x = UOp.variable('x', -3, 4) + uop = x * 2 + self.assertEqual(uop.vmin, -6) + self.assertEqual(uop.vmax, 8) + + def test_vmin_vmax_variable_inside_special(self): + uop = UOp(Ops.SPECIAL, dtypes.int, arg=('gidx0', UOp(Ops.DEFINE_VAR, dtypes.int, arg=('i', 1, 10)))) + self.assertEqual(uop.vmin, 0) + self.assertEqual(uop.vmax, 10) + + def test_vmin_vmax_multiplication_0_inf(self): + # vmin and vmax for multiplication with a variable + x = UOp.const(dtypes.float, 0.0) + y = UOp.load(UOp(Ops.DEFINE_GLOBAL, dtypes.float.ptr(), (), 0), UOp.const(dtypes.int, 0), dtype=dtypes.float) + uop = x * y + # TODO: these should be 0, but definitely should not be nan + self.assertEqual(uop.vmin, -math.inf) + self.assertEqual(uop.vmax, math.inf) + + def test_vmin_vmax_with_negative_multiplication(self): + # vmin and vmax when multiplying by a negative number + x = UOp.variable('x', 2, 5) + uop = x * -3 + self.assertEqual(uop.vmin, -15) + self.assertEqual(uop.vmax, -6) + + def test_vmin_vmax_with_negative_multiplication2(self): + # vmin and vmax when multiplying by a negative number + x = UOp.variable('x', -2, 5) + uop = x * -3 + self.assertEqual(uop.vmin, -15) + self.assertEqual(uop.vmax, 6) + + def test_vmin_vmax_nested_min_max(self): + # vmin and vmax with nested min/max operations + x = UOp.variable('x', 0, 10) + uop = x.maximum(5).minimum(8) + self.assertEqual(uop.vmin, 5) + self.assertEqual(uop.vmax, 8) + + def test_vmin_vmax_where(self): + x = UOp.variable('x', 0, 10) + y = UOp.variable('y', 1, 11) + z = UOp.variable('z', 2, 12) + uop = (x<5).where(y, z) + self.assertEqual(uop.vmin, 1) + self.assertEqual(uop.vmax, 12) + + def test_vmin_vmax_shl(self): + x = UOp.variable('x', 0, 10) << 5 + self.assertEqual(x.vmin, 0) + self.assertEqual(x.vmax, 10 << 5) + + def test_vmin_vmax_shr(self): + x = UOp.variable('x', 0, 10) >> 2 + self.assertEqual(x.vmin, 0) + self.assertEqual(x.vmax, 10 >> 2) + +class TestVminVmaxDivMod(unittest.TestCase): + def test_vmin_vmax_division_positive(self): + # vmin and vmax for division of a variable by a positive constant + x = UOp.variable('x', 10, 20) + uop = x // 2 + self.assertEqual(uop.vmin, 5) + self.assertEqual(uop.vmax, 10) + + def test_vmin_vmax_division_negative(self): + # vmin and vmax for division of a variable by a negative constant + # always positive + x = UOp.variable('x', 10, 20) + uop = x // -2 + self.assertEqual(uop.vmin, -10) + self.assertEqual(uop.vmax, -5) + uop = x // -3 + self.assertEqual(uop.vmin, -6) + self.assertEqual(uop.vmax, -3) + + # always negative + x = UOp.variable('x', -20, -10) + uop = x // -2 + self.assertEqual(uop.vmin, 5) + self.assertEqual(uop.vmax, 10) + uop = x // -3 + self.assertEqual(uop.vmin, 3) + self.assertEqual(uop.vmax, 6) + + # cross 0 + x = UOp.variable('x', -10, 10) + uop = x // -2 + self.assertEqual(uop.vmin, -5) + self.assertEqual(uop.vmax, 5) + uop = x // -3 + self.assertEqual(uop.vmin, -3) + self.assertEqual(uop.vmax, 3) + + def test_vmin_vmax_div_symbolic(self): + x = UOp.variable('x', 1, 10) + y = UOp.variable('y', 3, 5) + self.assertEqual((x//y).vmin, 0) + self.assertEqual((x//y).vmax, 3) + self.assertEqual(((-x)//y).vmin, -3) + self.assertEqual(((-x)//y).vmax, 0) + self.assertEqual((x//(-y)).vmin, -3) + self.assertEqual((x//(-y)).vmax, 0) + self.assertEqual(((-x)//(-y)).vmin, 0) + self.assertEqual(((-x)//(-y)).vmax, 3) + + self.assertEqual((100//y).vmin, 20) + self.assertEqual((100//y).vmax, 33) + self.assertEqual(((-100)//y).vmin, -33) + self.assertEqual(((-100)//y).vmax, -20) + self.assertEqual((100//(-y)).vmin, -33) + self.assertEqual((100//(-y)).vmax, -20) + self.assertEqual(((-100)//(-y)).vmin, 20) + self.assertEqual(((-100)//(-y)).vmax, 33) + + def test_vmin_vmax_mod_positive(self): + # vmin and vmax for modulo of a variable by a positive constant + positive = UOp.variable('positive', 10, 20) + uop = positive % 3 + self.assertEqual(uop.vmin, 0) + self.assertEqual(uop.vmax, 2) + + negative = UOp.variable('negative', -20, -10) + uop = negative % 3 + self.assertEqual(uop.vmin, -2) + self.assertEqual(uop.vmax, 0) + + mixed = UOp.variable('mixed', -20, 20) + uop = mixed % 3 + self.assertEqual(uop.vmin, -2) + self.assertEqual(uop.vmax, 2) + + def test_vmin_vmax_mod_negative(self): + # vmin and vmax for modulo of a variable by a negative constant + positive = UOp.variable('positive', 10, 20) + uop = positive % -3 + self.assertEqual(uop.vmin, 0) + self.assertEqual(uop.vmax, 2) + + negative = UOp.variable('negative', -20, -10) + uop = negative % -3 + self.assertEqual(uop.vmin, -2) + self.assertEqual(uop.vmax, 0) + + mixed = UOp.variable('mixed', -20, 20) + uop = mixed % -3 + self.assertEqual(uop.vmin, -2) + self.assertEqual(uop.vmax, 2) + +class TestVminVmaxVConst(unittest.TestCase): + def test_vmin_vmax_vconst_single_element(self): + # vmin and vmax for a single-element vector constant + uop = UOp.const(dtypes.int32.vec(1), (42,)) + self.assertEqual(uop.vmin, 42) + self.assertEqual(uop.vmax, 42) + + def test_vmin_vmax_vconst_multiple_elements(self): + # vmin and vmax for a multi-element vector constant + uop = UOp.const(dtypes.int32.vec(4), (10, 20, -5, 7)) + self.assertEqual(uop.vmin, -5) + self.assertEqual(uop.vmax, 20) + + def test_vmin_vmax_vconst_all_equal(self): + # vmin and vmax for a vector where all elements are equal + uop = UOp.const(dtypes.int32.vec(3), (7, 7, 7)) + self.assertEqual(uop.vmin, 7) + self.assertEqual(uop.vmax, 7) + + def test_vmin_vmax_vconst_with_negative_values(self): + # vmin and vmax for a vector constant containing negative values + uop = UOp.const(dtypes.int32.vec(4), (-10, -20, -5, -15)) + self.assertEqual(uop.vmin, -20) + self.assertEqual(uop.vmax, -5) + + def test_vmin_vmax_vconst_with_floats(self): + # vmin and vmax for a vector constant of float values + uop = UOp.const(dtypes.float32.vec(3), (1.5, -3.2, 0.0)) + self.assertEqual(uop.vmin, -3.2) + self.assertEqual(uop.vmax, 1.5) + + def test_vmin_vmax_vconst_with_bools(self): + # vmin and vmax for a vector constant of bool values + uop = UOp.const(dtypes.bool.vec(3), (True, False, False)) + self.assertIs(uop.vmin, False) + self.assertIs(uop.vmax, True) + +class TestConstFactor(unittest.TestCase): + def test_const_factor_constant(self): + # const_factor for a constant + uop = UOp.const(dtypes.int32, 42) + self.assertEqual(uop.const_factor(), 42) + + def test_const_factor_addition(self): + # const_factor for an addition of constants + uop = UOp.const(dtypes.int32, 30) + UOp.const(dtypes.int32, 12) + self.assertEqual(uop.const_factor(), 6) # GCD(30, 12) = 6 + + def test_const_factor_multiplication(self): + # const_factor for a multiplication of constants + uop = UOp.const(dtypes.int32, 5) * UOp.const(dtypes.int32, 7) + self.assertEqual(uop.const_factor(), 5) # For multiplication, it's one of the factors + + def test_const_factor_with_variable(self): + # const_factor for an expression involving a variable + x = UOp.variable('x', 10, 20) + uop = x * 3 + self.assertEqual(uop.const_factor(), 3) + + def test_const_factor_division(self): + # const_factor for an expression with division + x = UOp.variable('x', 10, 20) + uop = x // 4 + self.assertEqual(uop.const_factor(), 1) # Division reduces the const_factor to 1 + + def test_const_factor_multiplication_of_var_and_const(self): + # const_factor for multiplication of a variable and a constant + x = UOp.variable('x', 6, 18) + uop = x * 4 + self.assertEqual(uop.const_factor(), 4) # Constant factor 4 + + @unittest.skip("broken") + def test_const_factor_multiplication_of_consts_and_vars(self): + # Multiplying constants and variables + x = UOp.variable('x', 10, 20) + uop = (x * 3) * 5 + self.assertEqual(uop.const_factor(), 15) # Constant multipliers are combined (3 * 5 = 15) + +class TestDivides(unittest.TestCase): + def test_divides_constant_exact(self): + # Divides a constant by an exact divisor + uop = UOp.const(dtypes.int32, 42) + result = uop.divides(7) + self.assertIsNotNone(result) + self.assertEqual(result.const_factor(), 6) # 42 / 7 = 6 + + def test_divides_constant_inexact(self): + # Try to divide a constant by a non-exact divisor + uop = UOp.const(dtypes.int32, 42) + result = uop.divides(5) + self.assertIsNone(result) # 42 is not divisible by 5 + + @unittest.skip("broken") + def test_divides_variable_and_constant(self): + # Multiplying a variable by a constant, then dividing by the same constant + x = UOp.variable('x', 10, 20) + uop = x * 6 + result = uop.divides(6) + self.assertIsNotNone(result) + self.assertEqual(result, x) # (x * 6) / 6 = x + + def test_divides_complex_expression(self): + # Dividing a more complex expression + x = UOp.variable('x', 10, 20) + uop = (x * 6) + 18 + result = uop.divides(6) + self.assertIsNotNone(result) + self.assertEqual(result.const_factor(), 1) # (x + 3), const_factor is 1 + + def test_divides_with_inexact_factors(self): + # Multiplying by a constant but dividing by a non-exact divisor + x = UOp.variable('x', 15, 45) + uop = x * 4 + result = uop.divides(3) + self.assertIsNone(result) # Cannot divide by 3, since 4 is not divisible by 3 + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_upat_compile.py b/tinygrad_repo/test/unit/test_upat_compile.py new file mode 100644 index 000000000..1f68a8830 --- /dev/null +++ b/tinygrad_repo/test/unit/test_upat_compile.py @@ -0,0 +1,53 @@ +import unittest +from tinygrad.helpers import DEBUG +from tinygrad.dtype import dtypes +from tinygrad.uop.ops import UPat, track_rewrites, GroupOp, Ops +from tinygrad.uop.upat import _get_code, upat_compile +import dis + +@track_rewrites() +def do_compile(up): + print("\n***** COMPILE", up) + match_code = _get_code(up, False) + match = upat_compile(up, lambda **kwargs: None) + print(match_code[0]) + if DEBUG >= 2: dis.dis(match) + return match_code[0] + +class TestUPatCompile(unittest.TestCase): + def test_double(self): + up = UPat.var("x") * UPat.cvar("c0") + UPat.var("x") * UPat.cvar("c1") + do_compile(up) + + def test_single(self): + up = UPat.var("x") + UPat.var("y") + do_compile(up) + + def test_xpx(self): + up = UPat.var("x") + UPat.var("x") + do_compile(up) + + def test_xp0(self): + up = UPat.var("x") + 0 + do_compile(up) + + def test_bool(self): + up = UPat.var('x', dtype=dtypes.bool) * UPat.var('y', dtype=dtypes.bool) + do_compile(up) + + def test_single_c(self): + up = (UPat.var("x") + UPat.var("y")) * UPat.var("c") + do_compile(up) + + def test_const_folding(self): + up = UPat(GroupOp.ALU-{Ops.THREEFRY}, name="a", src=UPat((Ops.VCONST, Ops.CONST))) + do_compile(up) + + @unittest.skip("fix this") + def test_range_named(self): + # this should be one src, but this should also still work + up = UPat(Ops.CAST, dtypes.float, UPat.var("x", dtypes.bfloat16)) + do_compile(up) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/unit/test_view.py b/tinygrad_repo/test/unit/test_view.py new file mode 100644 index 000000000..720688275 --- /dev/null +++ b/tinygrad_repo/test/unit/test_view.py @@ -0,0 +1,237 @@ +#!/usr/bin/env python +import unittest +from tinygrad.shape.view import View, merge_dims +# from tinygrad.shape.shapetracker import ShapeTracker + +class TestView(unittest.TestCase): + def test_canonicalize_empty_mask(self): + v = View.create(shape=(2,2,2), strides=(4,2,1), mask=((0,2),(0,2),(0,2))) + self.assertIsNone(v.mask) + v = View.create(shape=(4,3,2), strides=(1,4,10), mask=((0,4),(0,3),(0,2))) + self.assertIsNone(v.mask) + + def test_minify_zero_strided_dims(self): + target = View.create(shape=(2,2), strides=(30,2), offset=7, mask=None) + v = View.create(shape=(2,1,2), strides=(30,0,2), offset=7, mask=None) + self.assertEqual(v.minify(), target) + v = View.create(shape=(1,2,2), strides=(0,30,2), offset=7, mask=None) + self.assertEqual(v.minify(), target) + v = View.create(shape=(2,2,1), strides=(30,2,0), offset=7, mask=None) + self.assertEqual(v.minify(), target) + v = View.create(shape=(2,1,1,2), strides=(30,0,0,2), offset=7, mask=None) + self.assertEqual(v.minify(), target) + v = View.create(shape=(1,1,2,2), strides=(0,0,30,2), offset=7, mask=None) + self.assertEqual(v.minify(), target) + v = View.create(shape=(2,2,1,1), strides=(30,2,0,0), offset=7, mask=None) + self.assertEqual(v.minify(), target) + v = View.create(shape=(1,2,2,1), strides=(0,30,2,0), offset=7, mask=None) + self.assertEqual(v.minify(), target) + v = View.create(shape=(1,2,1,2), strides=(0,30,0,2), offset=7, mask=None) + self.assertEqual(v.minify(), target) + + def test_empty_mask_contiguous(self): + v1 = View.create(shape=(2,2,2), strides=(4,2,1), mask=None) + v2 = View.create(shape=(2,2,2), strides=(4,2,1), mask=((0,2),(0,2),(0,2))) + self.assertEqual(v1.contiguous, v2.contiguous) + v1 = View.create(shape=(1,1,1,4), strides=(0,0,0,1), offset=0, mask=None) + v2 = View.create(shape=(1,1,1,4), strides=(0,0,0,1), offset=0, mask=((0,1),(0,1),(0,1),(0,4))) + self.assertEqual(v1.contiguous, v2.contiguous) + v = View.create(shape=(2,3,4), mask=((0,2),(0,3),(0,4))) + self.assertTrue(v.contiguous) + + def test_reshape_all_invalid(self): + v = View.create((4,5), mask=((0,0), (0,0))).reshape((20,)) + self.assertIsNotNone(v) + self.assertEqual(v, View.create((20,), mask=((0,0),))) + + def test_add_0(self): + v1 = View.create((2,3,4)) + v2 = View.create((2,0,4)) + self.assertEqual(v2, v1+v2) + + def test_add_0_masked(self): + v1 = View.create((2,3,4), mask=((0, 0), (0, 0), (0, 0))) + v2 = View.create((2,0,4)) + self.assertEqual(v2, v1+v2) + +class TestMergeDims(unittest.TestCase): + def test_contiguous(self): + shape = (2, 3, 4) + strides = (12, 4, 1) #=strides_for_shape(shape) + m = merge_dims(shape, strides) + self.assertEqual(m, ((24, 1, 24),)) + + def test_0_in_strides(self): + shape = (2, 3, 4) + self.assertEqual(merge_dims(shape, (0, 4, 1)), ((2, 0, 0), (12, 1, 12))) + self.assertEqual(merge_dims(shape, (0, 0, 1)), ((6, 0, 0), (4, 1, 4))) + self.assertEqual(merge_dims(shape, (3, 1, 0)), ((6, 1, 6), (4, 0, 4))) + self.assertEqual(merge_dims(shape, (0, 0, 0)), ((24, 0, 0),)) + + def test_pad(self): + # print(ShapeTracker.from_shape((1, 2)).pad(((1, 0), (0, 1))).views[-1]) + self.assertEqual(merge_dims((2, 3), (0, 1), ((1, 2), (0, 2))), ((6, 1, 3),)) + + # print(f"{ShapeTracker.from_shape((1, 1, 2)).pad(((1, 0), (1, 0), (0, 1))).views[-1]}") + self.assertEqual(merge_dims((2, 2, 3), (0, 0, 1), ((1, 2), (1, 2), (0, 2))), ((12, 1, 3),)) + + # print(f"{ShapeTracker.from_shape((1, 1, 2, 2)).pad(((1, 0), (1, 0), (0, 1), (0, 1))).views[-1]}") + self.assertEqual(merge_dims((2, 2, 3, 3), (0, 0, 2, 1), ((1, 2), (1, 2), (0, 2), (0, 2))), ((12, 2, 3), (3, 1, 3))) + + # print(f"{ShapeTracker.from_shape((2, 1, 2)).pad(((0, 0), (1, 0), (0, 1))).views[-1]}") + self.assertEqual(merge_dims((2, 2, 3), (2, 0, 1), ((0, 2), (1, 2), (0, 2))), ((2, 2, 2), (6, 1, 3))) + + def test_different_1_pad(self): + # print(f"{ShapeTracker.from_shape((2, 2, 1)).pad(((0, 0), (0, 0), (0, 1))).views[-1]}") + self.assertEqual(merge_dims((2, 2, 2), (2, 1, 0), ((0, 2), (0, 2), (0, 1))), ((4, 1, 4), (2, 0, 2))) + + # print(f"{ShapeTracker.from_shape((2, 1, 1)).pad(((0, 0), (0, 1), (0, 1))).views[-1]}") + self.assertEqual(merge_dims((2, 2, 2), (1, 0, 0), ((0, 2), (0, 2), (0, 1))), ((2, 1, 2), (4, 0, 4))) + +class TestMergeViews(unittest.TestCase): + def test_with_mask_0(self): + # from test/test_ops.py::TestOps::test_pad_reflect_mode + v0 = View(shape=(1, 1, 5, 8), strides=(0, 0, 5, 1), offset=-3, mask=((0, 1), (0, 1), (0, 5), (3, 8)), contiguous=False) + v1 = View(shape=(1, 1, 2, 2), strides=(0, 0, 8, 1), offset=3, mask=None, contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, View(shape=(1, 1, 2, 2), strides=(0, 0, 5, 1), offset=0, mask=None, contiguous=False)) + + def test_with_mask_1(self): + # from test/test_ops.py::TestOps::test_pad_reflect_mode + v0 = View(shape=(3, 3, 5, 3), strides=(27, 9, 3, 1), offset=-6, mask=((0, 3), (0, 3), (2, 4), (1, 3)), contiguous=False) + v1 = View(shape=(3, 3, 2, 2), strides=(45, 15, 3, 1), offset=7, mask=None, contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, View(shape=(3, 3, 2, 2), strides=(27, 9, 3, 1), offset=1, mask=None, contiguous=False)) + + def test_with_mask_2(self): + # from test/test_ops.py::TestOps::test_pad_reflect_mode + v0 = View(shape=(3, 3, 5, 3), strides=(27, 9, -3, 1), offset=6, mask=((0, 3), (0, 3), (0, 2), (0, 2)), contiguous=False) + v1 = View(shape=(3, 3, 2, 2), strides=(45, 15, -3, 1), offset=3, mask=None, contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, View(shape=(3, 3, 2, 2), strides=(27, 9, 3, 1), offset=3, mask=None, contiguous=False)) + + def test_with_mask_3(self): + # from test/test_ops.py::TestOps::test_pad_reflect_mode + # has a mask in the final view + v0 = View(shape=(3, 3, 4, 4), strides=(27, 9, 3, 1), offset=-5, mask=((0, 3), (0, 3), (2, 4), (0, 2)), contiguous=False) + v1 = View(shape=(3, 3, 4, 2), strides=(48, 16, 4, 1), offset=0, mask=None, contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, View(shape=(3, 3, 4, 2), strides=(27, 9, 3, 1), offset=-5, mask=((0, 3), (0, 3), (2, 4), (0, 2)), contiguous=False)) + + def test_with_mask_4(self): + # from test/test_ops.py::TestOps::test_pad_reflect_mode + # has a mask in the final view + v0 = View(shape=(3, 3, 5, 3), strides=(27, 9, -3, 1), offset=6, mask=((0, 3), (0, 3), (0, 2), (1, 3)), contiguous=False) + v1 = View(shape=(3, 3, 3, 3), strides=(45, 15, 3, 1), offset=6, mask=None, contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, View(shape=(3, 3, 3, 3), strides=(0, 0, 0, 0), offset=0, mask=((0, 0), (0, 0), (0, 0), (0, 0)), contiguous=False)) + + def test_with_mask_5(self): + # from test/test_ops.py::TestOps::test_pad_reflect_mode + # has a mask in the final view + v0 = View(shape=(1, 1, 6, 5), strides=(0, 0, 5, 1), offset=-5, mask=((0, 1), (0, 1), (1, 6), (0, 5)), contiguous=False) + v1 = View(shape=(1, 1, 6, 3), strides=(0, 0, 5, -1), offset=3, mask=None, contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, View(shape=(1, 1, 6, 3), strides=(0, 0, 5, -1), offset=-2, mask=((0, 1), (0, 1), (1, 6), (0, 3)), contiguous=False)) + + @unittest.expectedFailure # TODO: fix these + def test_merges_from_fuzzer1(self): + v0 = View(shape=(2, 4), strides=(2, 1), offset=-2, mask=((0, 2), (2, 4)), contiguous=False) + v1 = View(shape=(2, 4, 2, 2), strides=(4, 0, -2, -1), offset=3, mask=None, contiguous=False) + target = View(shape=(2, 4, 2, 2), strides=(2, 0, 0, -1), offset=1, mask=((0, 2), (0, 4), (0, 1), (0, 2)), contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, target) + + @unittest.expectedFailure # TODO: fix these + def test_merges_from_fuzzer2(self): + v0 = View(shape=(5, 10, 12), strides=(100, 1, 10), offset=-20, mask=((0, 5), (0, 10), (2, 12)), contiguous=False) + v1 = View(shape=(10, 6, 5, 2, 2), strides=(12, 2, 120, 1, 0), offset=0, mask=None, contiguous=False) + target = View(shape=(10, 6, 5, 2, 2), strides=(1, 20, 100, 10, 0), offset=-20, mask=((0, 10), (1, 6), (0, 5), (0, 2), (0, 2)), contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, target) + + @unittest.expectedFailure # TODO: fix these + def test_merges_from_fuzzer3(self): + v0 = View(shape=(8, 7, 3), strides=(1, 12, -4), offset=6, mask=((2, 6), (0, 7), (0, 3)), contiguous=False) + v1 = View(shape=(4, 2, 6, 2, 1), strides=(42, 21, 3, 1, 0), offset=4, mask=None, contiguous=False) + target = View(shape=(4, 2, 6, 2, 1), strides=(2, 1, 12, -4, 0), offset=14, mask=((1, 3), (0, 2), (0, 6), (0, 2), (0, 1)), contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, target) + + @unittest.expectedFailure # TODO: fix these + def test_merges_from_fuzzer4(self): + v0 = View(shape=(7, 21, 3), strides=(54, 3, 1), offset=-9, mask=((0, 6), (3, 21), (0, 3)), contiguous=False) + v1 = View(shape=(5, 3, 3, 7), strides=(63, 1, 3, 9), offset=63, mask=None, contiguous=False) + target = View(shape=(5, 3, 3, 7), strides=(54, 1, 3, 9), offset=45, mask=((0, 5), (0, 3), (0, 3), (1, 7)), contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, target) + + @unittest.expectedFailure # TODO: fix these + def test_merges_from_fuzzer5(self): + v0 = View(shape=(5, 1, 24), strides=(20, 0, 1), offset=-2, mask=((0, 5), (0, 1), (2, 22)), contiguous=False) + v1 = View(shape=(12, 2, 5, 2, 1), strides=(2, 1, 24, 0, 0), offset=0, mask=None, contiguous=False) + target = View(shape=(12, 2, 5, 2, 1), strides=(2, 1, 20, 0, 0), offset=-2, mask=((1, 11), (0, 2), (0, 5), (0, 2), (0, 1)), contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, target) + + def test_view_padded_area1(self): + # test_multinomial + v0 = View(shape=(2,), strides=(0,), offset=0, mask=((1, 2),), contiguous=False) + v1 = View(shape=(1,), strides=(0,), offset=0, mask=None, contiguous=True) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, View(shape=(1,), strides=(0,), offset=0, mask=((0, 0),), contiguous=False)) + + def test_view_padded_area2(self): + # test_pad_reflect_mode + v0 = View(shape=(1, 1, 10, 7), strides=(0, 0, 5, 1), offset=-15, mask=((0, 1), (0, 1), (3, 8), (0, 5)), contiguous=False) + v1 = View(shape=(0, 0, 0, 0), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=True) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, View(shape=(0, 0, 0, 0), strides=(0, 0, 0, 0), offset=0, mask=None, contiguous=True)) + + def test_view_padded_area3(self): + # test_roll + v0 = View(shape=(2, 4), strides=(0, 1), offset=4, mask=((0, 1), (0, 4)), contiguous=False) + v1 = View(shape=(1, 4), strides=(0, 1), offset=4, mask=None, contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, View(shape=(1, 4), strides=(0, 0), offset=0, mask=((0, 0), (0, 0)), contiguous=False)) + + def test_view_padded_area4(self): + # test_std_mean + v0 = View(shape=(2,), strides=(0,), offset=0, mask=((0, 1),), contiguous=False) + v1 = View(shape=(1, 1, 1), strides=(0, 0, 0), offset=1, mask=None, contiguous=False) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, View(shape=(1, 1, 1), strides=(0, 0, 0), offset=0, mask=((0, 0), (0, 0), (0, 0)), contiguous=False)) + + def test_empty_shape_view1(self): + # test_stack_slice + v0 = View(shape=(3, 5), strides=(0, 1), offset=0, mask=((0, 1), (0, 5)), contiguous=False) + v1 = View(shape=(), strides=(), offset=0, mask=None, contiguous=True) + v = v0 + v1 + self.assertIsNotNone(v) + self.assertEqual(v, View(shape=(), strides=(), offset=0, mask=None, contiguous=True)) + + def test_empty_shape_view2(self): + # test_std_mean + v0 = View(shape=(2,), strides=(0,), offset=0, mask=((1, 2),), contiguous=False) + v1 = View(shape=(), strides=(), offset=0, mask=None, contiguous=True) + v = v0 + v1 + # TODO: why is this different? + self.assertIsNone(v) + +if __name__ == '__main__': + unittest.main() diff --git a/tinygrad_repo/test/unit/test_viz.py b/tinygrad_repo/test/unit/test_viz.py new file mode 100644 index 000000000..a2fe5e801 --- /dev/null +++ b/tinygrad_repo/test/unit/test_viz.py @@ -0,0 +1,272 @@ +import unittest, decimal, json + +from tinygrad.uop.ops import UOp, UPat, Ops, PatternMatcher, TrackedPatternMatcher +from tinygrad.uop.ops import graph_rewrite, track_rewrites, TRACK_MATCH_STATS +from tinygrad.uop.symbolic import sym +from tinygrad.dtype import dtypes + +@track_rewrites(name=True) +def exec_rewrite(sink:UOp, pm_lst:list[PatternMatcher], names:None|list[str]=None) -> UOp: + for i,pm in enumerate(pm_lst): + sink = graph_rewrite(sink, TrackedPatternMatcher(pm.patterns), name=names[i] if names else None) + return sink + +# real VIZ=1 pickles these tracked values +from tinygrad.viz.serve import get_metadata +from tinygrad.uop.ops import tracked_keys, tracked_ctxs, active_rewrites, _name_cnt +def get_viz_list(): return get_metadata(tracked_keys, tracked_ctxs) + +class TestViz(unittest.TestCase): + def setUp(self): + # clear the global context + for lst in [tracked_keys, tracked_ctxs, active_rewrites, _name_cnt]: lst.clear() + self.tms = TRACK_MATCH_STATS.value + TRACK_MATCH_STATS.value = 2 + def tearDown(self): TRACK_MATCH_STATS.value = self.tms + + def test_simple(self): + a = UOp.variable("a", 0, 10) + exec_rewrite((a+0)*1, [sym]) + lst = get_viz_list() + # VIZ displays rewrites in groups of tracked functions + self.assertEqual(len(lst), 1) + # each group has a list of steps + self.assertEqual(len(lst[0]["steps"]), 1) + # each step has a list of matches + self.assertEqual(lst[0]["steps"][0]["match_count"], 2) + + def test_rewrites(self): + a = UOp.variable("a", 0, 10) + exec_rewrite(a*1, [sym]) + exec_rewrite(a*2, [sym]) + lst = get_viz_list() + self.assertEqual(len(lst), 2) + # names dedup using a counter + self.assertEqual(lst[0]["name"], "exec_rewrite n1") + self.assertEqual(lst[1]["name"], "exec_rewrite n2") + + def test_steps(self): + a = UOp.variable("a", 0, 10) + exec_rewrite(a+1, [PatternMatcher([]), PatternMatcher([])], ["x", "y"]) + steps = get_viz_list()[0]["steps"] + # steps can optionally have a name + self.assertEqual(steps[0]["name"], "x") + self.assertEqual(steps[1]["name"], "y") + + def test_rewrite_location(self): + def inner(sink): return graph_rewrite(sink, PatternMatcher([])) + @track_rewrites(name=True) + def outer(sink): return inner(sink) + outer(UOp.variable("a", 1, 10)) + lst = get_viz_list() + # step location comes from inner rewrite + fp, lineno = lst[0]["steps"][0]["loc"] + self.assertEqual(fp, inner.__code__.co_filename) + self.assertEqual(lineno, inner.__code__.co_firstlineno) + + def test_exceptions(self): + # VIZ tracks rewrites up to the error + def count_3(x:UOp): + assert x.arg <= 3 + return x.replace(arg=x.arg+1) + err_pm = PatternMatcher([(UPat.cvar("x"), count_3),]) + a = UOp.const(dtypes.int, 1) + with self.assertRaises(AssertionError): exec_rewrite(a, [err_pm]) + lst = get_viz_list() + err_step = lst[0]["steps"][0] + self.assertEqual(err_step["match_count"], 3) + + def test_default_name(self): + a = UOp.variable("a", 1, 10) + @track_rewrites() + def name_default(): return graph_rewrite(a, PatternMatcher([])) + name_default() + lst = get_viz_list() + self.assertEqual(lst[0]["name"], "name_default n1") + + # name can also be the first arg + def test_self_name(self): + @track_rewrites() + def name_is_self(s:UOp): return graph_rewrite(s, PatternMatcher([])) + name_is_self(arg:=UOp.variable("a", 1, 10)) + lst = get_viz_list() + self.assertEqual(lst[0]["name"], str(arg)) + + # name can also come from a function + def test_dyn_name_fxn(self): + @track_rewrites(name=lambda a,ret: a.render()) + def name_from_fxn(s:UOp): return graph_rewrite(s, PatternMatcher([])) + name_from_fxn(UOp.variable("a", 1, 10)+1) + lst = get_viz_list() + self.assertEqual(lst[0]["name"], "(a+1) n1") + +# VIZ displays nested graph_rewrites in a tree view + +def leaf_rewrite(x:UOp): return x.rtag(1) if x.tag is None else None +leaf = TrackedPatternMatcher([(UPat(Ops.DEFINE_VAR, name="x"), leaf_rewrite)]) + +def branch_rewrite(x:UOp, y:UOp): + if x.tag is not None: return + x2 = graph_rewrite(x, leaf, name="leaf_left") + y2 = graph_rewrite(y, leaf, name="leaf_right") + return x2 * y2 +branch = TrackedPatternMatcher([(UPat.var("x")+UPat.var("y"), branch_rewrite)]) + +def root_rewrite(root:UOp): + new_src = tuple(graph_rewrite(b, branch, name=f"branch_{i}") for i,b in enumerate(root.src)) + return root.replace(src=new_src) +root = TrackedPatternMatcher([(UPat(Ops.SINK, src=UPat(Ops.ADD), name="root"), root_rewrite),]) + +class TestVizTree(TestViz): + def assertStepEqual(self, step:dict, want:dict): + for k,v in want.items(): + self.assertEqual(step[k], v, f"failed at '{k}': {v} != {step[k]}\n{step=}") + + def test_tree_view(self): + a = UOp.variable("a",0,10) + b = UOp.variable("b",0,10) + c = UOp.variable("c",0,10) + d = UOp.variable("d",0,10) + sink = UOp.sink(a+b, c+d) + @track_rewrites() + def tree_rewrite(): return graph_rewrite(sink, root, name="root") + tree_rewrite() + lst = get_viz_list() + steps = lst[0]["steps"] + self.assertEqual(len(steps), 1+2+4) + self.assertStepEqual(steps[0], {"name":"root", "depth":0, "match_count":1}) + self.assertStepEqual(steps[1], {"name":"branch_0", "depth":1, "match_count":1}) + self.assertStepEqual(steps[2], {"name":"leaf_left", "depth":2, "match_count":1}) + self.assertStepEqual(steps[3], {"name":"leaf_right", "depth":2, "match_count":1}) + self.assertStepEqual(steps[4], {"name":"branch_1", "depth":1, "match_count":1}) + self.assertStepEqual(steps[5], {"name":"leaf_left", "depth":2, "match_count":1}) + self.assertStepEqual(steps[6], {"name":"leaf_right", "depth":2, "match_count":1}) + +import gc +from tinygrad.device import Buffer + +def bufs_allocated() -> int: + gc.collect() + return sum([isinstance(x, Buffer) for x in gc.get_objects()]) + +class TestVizGC(TestViz): + def test_gc(self): + init = bufs_allocated() + a = UOp.new_buffer("NULL", 10, dtypes.char) + a.buffer.allocate() + exec_rewrite(a, [PatternMatcher([])]) + del a + self.assertEqual(bufs_allocated()-init, 0) + lst = get_viz_list() + self.assertEqual(len(lst), 1) + + @unittest.skip("it's not generic enough to handle arbitrary UOps in arg") + def test_gc_uop_in_arg(self): + init = bufs_allocated() + a = UOp.new_buffer("NULL", 10, dtypes.char) + a.buffer.allocate() + exec_rewrite(UOp(Ops.CUSTOM, src=(a,), arg=a), [PatternMatcher([])]) + del a + self.assertEqual(bufs_allocated()-init, 0) + lst = get_viz_list() + self.assertEqual(len(lst), 1) + +# VIZ integrates with other parts of tinygrad + +from tinygrad import Tensor, Device +from tinygrad.engine.realize import get_program + +class TestVizIntegration(TestViz): + # kernelize has a custom name function in VIZ + def test_kernelize_tracing(self): + a = Tensor.empty(4, 4) + Tensor.kernelize(a+1, a+2) + lst = get_viz_list() + self.assertEqual(len(lst), 1) + self.assertEqual(lst[0]["name"], "Schedule 2 Kernels n1") + + # codegen supports rendering of code blocks + def test_codegen_tracing(self): + ast = Tensor.schedule(Tensor.empty(4)+Tensor.empty(4))[0].ast + prg = get_program(ast, Device[Device.DEFAULT].renderer) + lst = get_viz_list() + self.assertEqual(len(lst), 2) + self.assertEqual(lst[0]["name"], "Schedule 1 Kernel n1") + self.assertEqual(lst[1]["name"], prg.name) + +from tinygrad.device import ProfileDeviceEvent, ProfileRangeEvent, ProfileGraphEvent, ProfileGraphEntry +from tinygrad.viz.serve import to_perfetto + +class TextVizProfiler(unittest.TestCase): + def test_perfetto_node(self): + prof = [ProfileRangeEvent(device='NV', name='E_2', st=decimal.Decimal(1000), en=decimal.Decimal(1010), is_copy=False), + ProfileDeviceEvent(device='NV', comp_tdiff=decimal.Decimal(-1000), copy_tdiff=decimal.Decimal(-100))] + + j = json.loads(to_perfetto(prof)) + + # Device regs always first + self.assertEqual(j['traceEvents'][0]['name'], 'process_name') + self.assertEqual(j['traceEvents'][0]['ph'], 'M') + self.assertEqual(j['traceEvents'][0]['args']['name'], 'NV') + + self.assertEqual(j['traceEvents'][1]['name'], 'thread_name') + self.assertEqual(j['traceEvents'][1]['ph'], 'M') + self.assertEqual(j['traceEvents'][1]['pid'], j['traceEvents'][0]['pid']) + self.assertEqual(j['traceEvents'][1]['tid'], 0) + self.assertEqual(j['traceEvents'][1]['args']['name'], 'COMPUTE') + + self.assertEqual(j['traceEvents'][2]['name'], 'thread_name') + self.assertEqual(j['traceEvents'][2]['ph'], 'M') + self.assertEqual(j['traceEvents'][2]['pid'], j['traceEvents'][0]['pid']) + self.assertEqual(j['traceEvents'][2]['tid'], 1) + self.assertEqual(j['traceEvents'][2]['args']['name'], 'COPY') + + self.assertEqual(j['traceEvents'][3]['name'], 'E_2') + self.assertEqual(j['traceEvents'][3]['ts'], 0) + self.assertEqual(j['traceEvents'][3]['dur'], 10) + self.assertEqual(j['traceEvents'][3]['ph'], 'X') + self.assertEqual(j['traceEvents'][3]['pid'], j['traceEvents'][0]['pid']) + self.assertEqual(j['traceEvents'][3]['tid'], 0) + + def test_perfetto_copy_node(self): + prof = [ProfileRangeEvent(device='NV', name='COPYxx', st=decimal.Decimal(1000), en=decimal.Decimal(1010), is_copy=True), + ProfileDeviceEvent(device='NV', comp_tdiff=decimal.Decimal(-1000), copy_tdiff=decimal.Decimal(-100))] + + j = json.loads(to_perfetto(prof)) + + self.assertEqual(j['traceEvents'][3]['name'], 'COPYxx') + self.assertEqual(j['traceEvents'][3]['ts'], 900) # diff clock + self.assertEqual(j['traceEvents'][3]['dur'], 10) + self.assertEqual(j['traceEvents'][3]['ph'], 'X') + self.assertEqual(j['traceEvents'][3]['tid'], 1) + + def test_perfetto_graph(self): + prof = [ProfileDeviceEvent(device='NV', comp_tdiff=decimal.Decimal(-1000), copy_tdiff=decimal.Decimal(-100)), + ProfileDeviceEvent(device='NV:1', comp_tdiff=decimal.Decimal(-500), copy_tdiff=decimal.Decimal(-50)), + ProfileGraphEvent(ents=[ProfileGraphEntry(device='NV', name='E_25_4n2', st_id=0, en_id=1, is_copy=False), + ProfileGraphEntry(device='NV:1', name='NV -> NV:1', st_id=2, en_id=3, is_copy=True)], + deps=[[], [0]], + sigs=[decimal.Decimal(1000), decimal.Decimal(1002), decimal.Decimal(1004), decimal.Decimal(1008)])] + + j = json.loads(to_perfetto(prof)) + + # Device regs always first + self.assertEqual(j['traceEvents'][0]['args']['name'], 'NV') + self.assertEqual(j['traceEvents'][1]['args']['name'], 'COMPUTE') + self.assertEqual(j['traceEvents'][2]['args']['name'], 'COPY') + self.assertEqual(j['traceEvents'][3]['args']['name'], 'NV:1') + self.assertEqual(j['traceEvents'][4]['args']['name'], 'COMPUTE') + self.assertEqual(j['traceEvents'][5]['args']['name'], 'COPY') + + self.assertEqual(j['traceEvents'][6]['name'], 'E_25_4n2') + self.assertEqual(j['traceEvents'][6]['ts'], 0) + self.assertEqual(j['traceEvents'][6]['dur'], 2) + self.assertEqual(j['traceEvents'][6]['pid'], j['traceEvents'][0]['pid']) + + self.assertEqual(j['traceEvents'][7]['name'], 'NV -> NV:1') + self.assertEqual(j['traceEvents'][7]['ts'], 954) + self.assertEqual(j['traceEvents'][7]['dur'], 4) + self.assertEqual(j['traceEvents'][7]['pid'], j['traceEvents'][3]['pid']) + +if __name__ == "__main__": + unittest.main() diff --git a/tinygrad_repo/test/web/test_viz.js b/tinygrad_repo/test/web/test_viz.js new file mode 100644 index 000000000..654bf97fb --- /dev/null +++ b/tinygrad_repo/test/web/test_viz.js @@ -0,0 +1,35 @@ +const { spawn } = require("child_process"); +const puppeteer = require("puppeteer"); + +async function main() { + // ** start viz server + const proc = spawn("python", ["-u", "-c", "from tinygrad import Tensor; Tensor.arange(4).realize()"], { env: { ...process.env, VIZ:"1" }, + stdio: ["inherit", "pipe", "inherit"]}); + await new Promise(resolve => proc.stdout.on("data", r => { + if (r.includes("ready")) resolve(); + })); + + // ** run browser tests + let browser, page; + try { + browser = await puppeteer.launch({ headless: true }); + page = await browser.newPage(); + const res = await page.goto("http://localhost:8000", { waitUntil:"domcontentloaded" }); + if (res.status() !== 200) throw new Error("Failed to load page"); + const scheduleSelector = await page.waitForSelector("ul:nth-of-type(2)"); + scheduleSelector.click(); + await page.waitForSelector("rect"); + await page.waitForFunction(() => { + const nodes = document.querySelectorAll("#nodes > g").length; + const edges = document.querySelectorAll("#edges > path").length; + return nodes > 0 && edges > 0; + }); + } finally { + // ** cleanups + if (page != null) await page.close(); + if (browser != null) await browser.close(); + proc.kill(); + } +} + +main(); diff --git a/tinygrad_repo/test/web/test_webgpu.js b/tinygrad_repo/test/web/test_webgpu.js new file mode 100644 index 000000000..1c953da8a --- /dev/null +++ b/tinygrad_repo/test/web/test_webgpu.js @@ -0,0 +1,65 @@ +const puppeteer = require("puppeteer"); +const { spawn } = require("child_process"); +const res = spawn("python", ["-m", "http.server", "8000"], { shell: true }); + +async function timeout(time) { + return new Promise((resolve) => setTimeout(resolve, time)); +} + +function cleanup(err) { + console.log("cleaning up"); + res.kill(); + if (err != null) { + console.error(err); + process.exit(1); + } + process.exit(0); +} + +async function waitForText(selector, text) { + let n = 0; + let ready = false; + while (n < 30) { + const res = await (await selector.getProperty("textContent")).jsonValue(); + console.log(`waiting for text ${text} got ${res}`); + if (res == text) { + ready = true; + break; + } + await timeout(1000); + n += 1; + } + return ready; +} + +async function runTest() { + const browser = await puppeteer.launch({ + headless: false, + args: ["--enable-unsafe-webgpu"], + }); + const page = await browser.newPage(); + + page + .on("console", (message) => + console.log(`message from console ${message.text()}`), + ) + .on("pageerror", ({ message }) => + console.log(`error from page ${message}`), + ); + + const res = await page.goto("http://localhost:8000/examples/webgpu/efficientnet/index.html"); + if (res.status() !== 200) throw new Error("Failed to load page"); + + const textSelector = await page.waitForSelector("#result"); + const buttonSelector = await page.waitForSelector("input[type=button]"); + const ready = await waitForText(textSelector, "ready"); + if (!ready) throw new Error("Failed to load page"); + + await buttonSelector.evaluate((e) => e.click()); + const done = await waitForText(textSelector, "hen"); + if (!done) throw new Error("failed to get hen"); + + cleanup(null); +} + +runTest().catch((err) => cleanup(err)); diff --git a/tinygrad_repo/test_driven_development.sh b/tinygrad_repo/test_driven_development.sh new file mode 100755 index 000000000..e868497e9 --- /dev/null +++ b/tinygrad_repo/test_driven_development.sh @@ -0,0 +1,8 @@ +#!/bin/bash +python3 test/external/process_replay/reset.py +CAPTURE_PROCESS_REPLAY=1 pytest -n auto test/test_tiny.py test/test_uop_graph.py test/test_ops.py test/test_linearizer.py +while true; do + if python3 test/test_tiny.py; then + PYTHONPATH="." python3 test/external/process_replay/process_replay.py + fi +done diff --git a/tinygrad_repo/tinygrad/apps/llm.py b/tinygrad_repo/tinygrad/apps/llm.py deleted file mode 100644 index 5d79e69b9..000000000 --- a/tinygrad_repo/tinygrad/apps/llm.py +++ /dev/null @@ -1,204 +0,0 @@ -from __future__ import annotations -import sys, argparse, typing, re, itertools, unicodedata -from tinygrad import Tensor, nn, UOp, TinyJit, getenv, helpers - -def gpt2_decode_vocab(voc: dict[str, int]): # https://github.com/openai/gpt-2/blob/9b63575ef42771a015060c964af2c3da4cf7c8ab/src/encoder.py#L9 - c2b = { chr(cp): cp for cp in itertools.chain(range(ord("!"), ord("~")+1), range(ord("¡"), ord("¬")+1), range(ord("®"), ord("ÿ")+1)) } - c2b.update({ chr(256+off): cp for off, cp in enumerate(cp for cp in range(256) if chr(cp) not in c2b) }) - return { bytes(c2b[c] for c in tok): tid for tok, tid in voc.items() } - -def get_llama_re(): - def ucat_range(pre: str): return "".join(re.escape(chr(cp)) for cp in range(sys.maxunicode + 1) if unicodedata.category(chr(cp)).startswith(pre)) - r_ws, r_p_N, r_p_L = r"\t\n\x0b\x0c\r\x85" + ucat_range("Z"), ucat_range("N"), ucat_range("L") - # https://github.com/ggml-org/llama.cpp/blob/94933c8c2eeaa9a7983e3f6c08af76bd86724094/src/llama-vocab.cpp#L286 - return "(?i:'s|'t|'re|'ve|'m|'ll|'d)|" + \ - f"[^\\r\\n{r_p_N}{r_p_L}]?[{r_p_L}]+|[{r_p_N}]{{1,3}}| ?[^{r_ws}{r_p_N}{r_p_L}]+[\\r\\n]*|[{r_ws}]*[\\r\\n]+|[{r_ws}]+(?![^{r_ws}])|[{r_ws}]+" - -class SimpleTokenizer: - def __init__(self, pat: str, normal_tokens: dict[bytes, int], special_tokens: dict[str, int]): - self._normal_tokens, self._special_tokens, self._pat = normal_tokens, special_tokens, re.compile(pat) - self._tok2str = { tid: tok.encode() for tok, tid in special_tokens.items() } | { tid: tok for tok, tid in normal_tokens.items() } - self._special_re = re.compile("|".join(re.escape(tok) for tok in self._special_tokens.keys()) if special_tokens else r"(?!)") - - @staticmethod - def from_gguf_kv(kv: dict): - # https://github.com/ggml-org/llama.cpp/blob/94933c8c2eeaa9a7983e3f6c08af76bd86724094/src/llama-vocab.cpp#L1818-L1820 - if kv["tokenizer.ggml.pre"] not in ("llama3","llama-v3","llama-bpe"): raise ValueError(f"Invalid tokenizer preset '{kv['tokenizer.ggml.pre']}'") - vocab: typing.Iterable[tuple[str, int]] = ((tok, idx) for idx, tok in enumerate(kv["tokenizer.ggml.tokens"])) - normal_tokens, special_tokens = helpers.partition(vocab, lambda e: kv["tokenizer.ggml.token_type"][e[1]] == 1) - return SimpleTokenizer(get_llama_re(), gpt2_decode_vocab(dict(normal_tokens)), dict(special_tokens)) - - def encode(self, text: str): - tokens: list[int] = [] - pos = 0 - for match in self._special_re.finditer(text): - tokens.extend(self._encode_sentence(text[pos:match.start(0)]) + [self._special_tokens[text[match.start(0):match.end(0)]]]) - pos = match.end(0) - return tokens + self._encode_sentence(text[pos:]) - - def decode(self, ids: list[int]) -> str: return b''.join(self._tok2str[tid] for tid in ids).decode() - def role(self, role:str): return self.encode("<|start_header_id|>" + role + "<|end_header_id|>\n\n") - - def _encode_sentence(self, chunk: str): return [ tok for word in self._pat.findall(chunk) for tok in self._encode_word(word.encode()) ] - def _encode_word(self, word: bytes): - if (early_token:=self._normal_tokens.get(word)) is not None: return [early_token] - parts = [word[i:i+1] for i in range(len(word))] - while True: - min_tid, min_idx = 2**32, -1 - for idx, (p1, p2) in enumerate(zip(parts[:-1], parts[1:])): - tid = self._normal_tokens.get(p1 + p2, min_tid) - if tid < min_tid: min_tid, min_idx = tid, idx - if min_idx == -1: break - parts = parts[:min_idx] + [parts[min_idx] + parts[min_idx+1]] + parts[min_idx+2:] - try: return [ self._normal_tokens[p] for p in parts ] - except KeyError: raise RuntimeError("token not found") - -def apply_rope(x:Tensor, start_pos:int|UOp, base:float = 10000.0) -> Tensor: - B, H, T, Hd = x.shape - assert (Hd & 1) == 0, "RoPE requires an even head dimension" - half = Hd // 2 - angles = (Tensor.arange(T, dtype="float32") + start_pos)[:, None] * (base ** (-(Tensor.arange(half, dtype="float32") / half)))[None, :] - cos, sin = angles.cos().reshape(1, 1, T, half).cast(x.dtype), angles.sin().reshape(1, 1, T, half).cast(x.dtype) - x_pairs = x.reshape(B, H, T, half, 2) - return Tensor.stack(x_pairs[..., 0] * cos - x_pairs[..., 1] * sin, - x_pairs[..., 0] * sin + x_pairs[..., 1] * cos, dim=-1).reshape(B, H, T, Hd) - -class TransformerBlock: - def __init__(self, dim:int, hidden_dim:int, n_heads:int, n_kv_heads:int, norm_eps:float, max_context:int=0): - self.n_heads = n_heads - self.n_kv_heads = n_kv_heads - self.head_dim = dim // n_heads - self.max_context = max_context - - # --- attention projections (all linear, bias-free) ------------------ - kv_proj_out = self.head_dim * n_kv_heads # Llama-3 uses the same dim for K/V - self.attn_q = nn.Linear(dim, dim, bias=False) - self.attn_k = nn.Linear(dim, kv_proj_out, bias=False) - self.attn_v = nn.Linear(dim, kv_proj_out, bias=False) - self.attn_output = nn.Linear(dim, dim, bias=False) - - # --- RMSNorms -------------------------------------------------------- - self.attn_norm = nn.RMSNorm(dim, norm_eps) - self.ffn_norm = nn.RMSNorm(dim, norm_eps) - - # --- feed-forward ---------------------------------------------------- - self.ffn_gate = nn.Linear(dim, hidden_dim, bias=False) - self.ffn_up = nn.Linear(dim, hidden_dim, bias=False) - self.ffn_down = nn.Linear(hidden_dim, dim, bias=False) - - def _attention(self, x:Tensor, start_pos:int|UOp) -> Tensor: - x_norm = self.attn_norm(x) # (B,T,D) - q, k, v = self.attn_q(x_norm), self.attn_k(x_norm), self.attn_v(x_norm) - - B, T, _ = x.shape - q = q.reshape(B, T, self.n_heads, self.head_dim).transpose(1, 2) # (B,H,T,Hd) - k = k.reshape(B, T, self.n_kv_heads, self.head_dim).transpose(1, 2) # (B,KvH,T,Hd) - v = v.reshape(B, T, self.n_kv_heads, self.head_dim).transpose(1, 2) # (B,KvH,T,Hd) - - q = apply_rope(q, start_pos) - k = apply_rope(k, start_pos) - - # TODO: remove these kv cache realizes - if not hasattr(self, "cache_kv"): - self.cache_kv = Tensor.zeros(2, B, self.n_kv_heads, self.max_context, self.head_dim, dtype=k.dtype, device=k.device).contiguous().realize() - self.cache_kv[:, :, :, start_pos:start_pos+T, :].assign(Tensor.stack(k, v)).realize() # type: ignore - k = self.cache_kv[0, :, :, 0:start_pos+T, :] - v = self.cache_kv[1, :, :, 0:start_pos+T, :] - - # NOTE: this mask is causal_lower_right, not the causal_upper_left generated by is_casual = True - mask = Tensor.full((1, 1, T, start_pos+T), float("-inf"), dtype=x.dtype, device=x.device).triu(start_pos+1) if T > 1 else None - attn = q.scaled_dot_product_attention(k, v, attn_mask=mask, enable_gqa=True) # (B,H,T,Hd) - attn = attn.transpose(1, 2).reshape(B, T, -1) # back to (B,T,D) - attn = self.attn_output(attn) - return x + attn - - def _feed_forward(self, h: Tensor) -> Tensor: - h_norm = self.ffn_norm(h) - gated = self.ffn_gate(h_norm).silu() * self.ffn_up(h_norm) - return h + self.ffn_down(gated) - - def __call__(self, x: Tensor, start_pos: int|UOp): - return self._feed_forward(self._attention(x, start_pos)) - -class Transformer: - def __init__(self, *, num_blocks, dim, hidden_dim, n_heads, n_kv_heads, norm_eps, vocab_size, max_context): - self.blk = [TransformerBlock(dim, hidden_dim, n_heads, n_kv_heads, norm_eps, max_context) for _ in range(num_blocks)] - self.token_embd = nn.Embedding(vocab_size, dim) - self.output_norm = nn.RMSNorm(dim, norm_eps) - self.output = nn.Linear(dim, vocab_size, bias=False) - self.max_context = max_context - # JIT is used if T=1 and start_pos is a UOp. TODO: make this not needed by including T in the JIT and making start_pos always a UOp - self.forward_jit = TinyJit(self.forward) - - def forward(self, tokens:Tensor, start_pos:int|UOp) -> Tensor: - x = self.token_embd(tokens) # (B, T, D) - for block in self.blk: x = block(x, start_pos) - # TODO: add temperature - return self.output(self.output_norm(x))[:, -1, :].softmax(-1).argmax(-1, keepdim=True) - - def __call__(self, tokens:Tensor, start_pos:int|UOp=0) -> Tensor: - return (self.forward_jit if getenv("JIT", 1) and tokens.shape[1] == 1 and isinstance(start_pos, UOp) else self.forward)(tokens, start_pos) - - @staticmethod - def from_gguf(gguf:Tensor, max_context:int|None=None) -> tuple[Transformer, dict]: - # TODO: remove the need for copy to default device - kv, state_dict = nn.state.gguf_load(gguf.to(None)) - - # all state items should be float16, not float32 - state_dict = {k:v.cast('float16') for k,v in state_dict.items()} - - # some models like Llama 3.2 don't have an output.weight, they just tie to the token_embd.weight - if 'output.weight' not in state_dict: state_dict['output.weight'] = state_dict['token_embd.weight'] - - arch = kv['general.architecture'] - max_context = min(max_context, kv[f'{arch}.context_length']) if max_context is not None else kv[f'{arch}.context_length'] - model = Transformer(num_blocks=kv[f'{arch}.block_count'], dim=kv[f'{arch}.embedding_length'], hidden_dim=kv[f'{arch}.feed_forward_length'], - n_heads=kv[f'{arch}.attention.head_count'], n_kv_heads=kv[f'{arch}.attention.head_count_kv'], - norm_eps=kv[f'{arch}.attention.layer_norm_rms_epsilon'], vocab_size=len(kv['tokenizer.ggml.tokens']), max_context=max_context) - nn.state.load_state_dict(model, state_dict, verbose=False, consume=True, realize=False) # NOTE: rope_freqs.weight (32,) is unused - return model, kv - - def generate(self, tokens:list[int], start_pos=0): - v_start_pos = UOp.variable("start_pos", 1, self.max_context-1) - start_pos = 0 - t = Tensor([tokens[start_pos:]], dtype="int32") - self.forward_jit.reset() # TODO: why is this required? root cause the issue and make it not be needed - while len(tokens) < self.max_context: - t = self(t, v_start_pos.bind(start_pos) if getenv("SYM", 1) and start_pos != 0 and t.shape[-1] == 1 else start_pos) - next_id = int(t.item()) - tokens.append(next_id) - start_pos = len(tokens) - 1 - yield next_id - -models = { - "1B": "https://huggingface.co/bartowski/Llama-3.2-1B-Instruct-GGUF/resolve/main/Llama-3.2-1B-Instruct-Q6_K.gguf", - "3B": "https://huggingface.co/bartowski/Llama-3.2-3B-Instruct-GGUF/resolve/main/Llama-3.2-3B-Instruct-Q6_K.gguf", - "3B_f16": "https://huggingface.co/bartowski/Llama-3.2-3B-Instruct-GGUF/resolve/main/Llama-3.2-3B-Instruct-f16.gguf", - "8B": "https://huggingface.co/bartowski/Meta-Llama-3.1-8B-Instruct-GGUF/resolve/main/Meta-Llama-3.1-8B-Instruct-Q8_0.gguf", -} - -if __name__ == "__main__": - parser = argparse.ArgumentParser() - parser.add_argument("--size", choices=list(models.keys()), default=list(models.keys())[0], help="Model size") - parser.add_argument("--max_context", type=int, default=4096, help="Max Context Length") - args = parser.parse_args() - - # load the model - model, kv = Transformer.from_gguf(Tensor.from_url(models[args.size]), args.max_context) - - # extract some metadata - tok = SimpleTokenizer.from_gguf_kv(kv) - bos_id: int = kv['tokenizer.ggml.bos_token_id'] - eos_id: int = kv['tokenizer.ggml.eos_token_id'] - - ids: list[int] = [bos_id] - while 1: - start_pos = len(ids) - 1 - try: - ids += tok.role("user") + tok.encode(input('>>> ')) + [eos_id] + tok.role("assistant") - except EOFError: - break - for next_id in model.generate(ids, start_pos): - sys.stdout.write(tok.decode([next_id]) if next_id != eos_id else "\n\n") - sys.stdout.flush() - if next_id == eos_id: break diff --git a/tinygrad_repo/tinygrad/codegen/__init__.py b/tinygrad_repo/tinygrad/codegen/__init__.py index fb7876fe5..10ca6a223 100644 --- a/tinygrad_repo/tinygrad/codegen/__init__.py +++ b/tinygrad_repo/tinygrad/codegen/__init__.py @@ -1,7 +1,7 @@ from typing import Any, Callable import functools from dataclasses import dataclass -from tinygrad.helpers import QUANTIZE, DEVECTORIZE, TRANSCENDENTAL, RANGEIFY, POSTOPT +from tinygrad.helpers import QUANTIZE, DEVECTORIZE, TRANSCENDENTAL from tinygrad.uop.ops import PatternMatcher, graph_rewrite, UOp from tinygrad.uop.spec import type_verify from tinygrad.renderer import Renderer @@ -9,17 +9,11 @@ from tinygrad.renderer import Renderer # import all pattern matchers here from tinygrad.codegen.lowerer import pm_lowerer, get_index from tinygrad.codegen.quantize import pm_quant -from tinygrad.codegen.gpudims import pm_add_gpudims from tinygrad.uop.symbolic import sym, symbolic_simple, gep_pushing -from tinygrad.uop.decompositions import get_late_rewrite_patterns -from tinygrad.codegen.late.expander import migrate_indexing, expander, pm_pre_expander -from tinygrad.codegen.late.devectorizer import load_store_folding, load_store_indexing, devectorize, pm_reduce, \ - ReduceContext, correct_load_store, pm_render -from tinygrad.codegen.late.linearize import block_create, pm_blockend_merge, block_merge, pm_finalize, BlockContext -from tinygrad.codegen.opt import pm_get_optimization, pm_do_optimize -from tinygrad.codegen.opt.swizzler import view_left, view_right, fix_kernel_ops -from tinygrad.codegen.opt.postrange import pm_postrange_opt -from tinygrad.schedule.rangeify import pm_add_buffers_local, rangeify_codegen +from tinygrad.codegen.expander import migrate_indexing, expander +from tinygrad.codegen.devectorizer import load_store_folding, load_store_indexing, devectorize, \ + pm_reduce, ReduceContext, correct_load_store, pm_render, get_late_rewrite_patterns +from tinygrad.codegen.linearize import block_create, pm_blockend_merge, block_merge, pm_finalize, BlockContext @dataclass class RewriteStep: @@ -32,12 +26,6 @@ class RewriteStep: def apply_rewrites(sink:UOp, rewrites:list[RewriteStep]): return functools.reduce(lambda x,f: f(x), rewrites, sink) -rewrites_for_views = [ - RewriteStep(view_left, name="Main View Left"), - RewriteStep(view_right, name="Main View Right"), - RewriteStep(view_left+fix_kernel_ops, bottom_up=True, name="Finalize Kernel"), -] - rewrites_for_linearizer = [ RewriteStep(block_create, ctx=BlockContext.from_sink, name="Linearizer: Create Blocks", bottom_up=True), RewriteStep(pm_blockend_merge, name="Linearizer: Merge Blockends"), @@ -46,41 +34,25 @@ rewrites_for_linearizer = [ def get_rewrites_for_renderer(opts:Renderer, linearizer:bool=True) -> list[RewriteStep]: # cache with the values of the context vars - return _get_rewrites_for_renderer(opts, linearizer, QUANTIZE.value, DEVECTORIZE.value, TRANSCENDENTAL.value, RANGEIFY.value, POSTOPT.value) + return _get_rewrites_for_renderer(opts, linearizer, QUANTIZE.value, DEVECTORIZE.value, TRANSCENDENTAL.value) @functools.cache -def _get_rewrites_for_renderer(opts:Renderer, linearizer:bool, _QUANTIZE, _DEVECTORIZE, _TRANSCENDENTAL, _RANGEIFY, _POSTOPT) -> list[RewriteStep]: +def _get_rewrites_for_renderer(opts:Renderer, linearizer:bool, _QUANTIZE, _DEVECTORIZE, _TRANSCENDENTAL) -> list[RewriteStep]: # ** lowerer (rewrite_shapetracker_with_index) ** ret: list[RewriteStep] = [] - - # view pushing - ret.extend(rewrites_for_views) - - # this is kernel.py - if not _RANGEIFY: ret.append(RewriteStep(pm_get_optimization, ctx=lambda _: opts, name="get optimization")) - if not _POSTOPT and not _RANGEIFY: ret.append(RewriteStep(pm_do_optimize, ctx=lambda _: opts, name="optimize ast")) - if _QUANTIZE and opts.device in {"CPU", "DSP"}: ret.append(RewriteStep(pm_quant, name="quantize")) - ret.append(RewriteStep(pm_lowerer, get_index, name="lowerer", bottom_up=True)) - - if _POSTOPT or _RANGEIFY: ret.append(RewriteStep(pm_postrange_opt, ctx=lambda _: opts, name="post optimize ast")) + ret.append(RewriteStep(pm_lowerer, lambda ast: get_index(ast, opts), name="lowerer")) # ** expander (expand_rewrite) ** ret.append(RewriteStep(sym+migrate_indexing, name="initial symbolic")) # expand - ret.append(RewriteStep(sym+pm_pre_expander+expander, name="expander")) - - # add locals - ret.append(RewriteStep(pm_add_buffers_local+rangeify_codegen, name="add local buffers")) + ret.append(RewriteStep(sym+expander, name="expander")) # ** devectorizer (full_graph_rewrite) ** # remove reduce ret.append(RewriteStep(pm_reduce+gep_pushing, lambda _: ReduceContext(), name="remove_reduce")) - # add gpu dims (late). this works after devectorize, but it's faster here - ret.append(RewriteStep(pm_add_gpudims, lambda _: opts, name="add gpudims")) - # devectorize (TODO: does this need opts?) if _DEVECTORIZE >= 2: pm_devectorize = sym+load_store_folding+load_store_indexing elif _DEVECTORIZE: pm_devectorize = sym+devectorize+load_store_folding+correct_load_store+load_store_indexing @@ -93,13 +65,9 @@ def _get_rewrites_for_renderer(opts:Renderer, linearizer:bool, _QUANTIZE, _DEVEC # optional pre matcher if opts.pre_matcher is not None: ret.append(RewriteStep(opts.pre_matcher, name="pre_matcher")) - # decompositions - pm_decomp = symbolic_simple+get_late_rewrite_patterns(supported_ops, _TRANSCENDENTAL>=2) - ret.append(RewriteStep(pm_decomp, lambda _: opts.device, name="decompositions")) - # final rules for the renderer (without sym) - pm_final_rewrite = pm_decomp+pm_render+extra_matcher - ret.append(RewriteStep(pm_final_rewrite, lambda _: opts.device, name="final rewrite")) + pm_final_rewrite = symbolic_simple+get_late_rewrite_patterns(supported_ops, _TRANSCENDENTAL>=2)+pm_render+extra_matcher + ret.append(RewriteStep(pm_final_rewrite, lambda _: opts, name="final rewrite")) # return the list (with optional linearizer) return ret + (rewrites_for_linearizer if linearizer else []) diff --git a/tinygrad_repo/tinygrad/codegen/late/devectorizer.py b/tinygrad_repo/tinygrad/codegen/devectorizer.py similarity index 76% rename from tinygrad_repo/tinygrad/codegen/late/devectorizer.py rename to tinygrad_repo/tinygrad/codegen/devectorizer.py index b1b150beb..fb8eb9c22 100644 --- a/tinygrad_repo/tinygrad/codegen/late/devectorizer.py +++ b/tinygrad_repo/tinygrad/codegen/devectorizer.py @@ -1,11 +1,13 @@ -from typing import Any, cast +from typing import Any, Callable, cast import functools, operator, itertools from collections import defaultdict from dataclasses import dataclass -from tinygrad.dtype import dtypes, ImageDType, PtrDType, DType, AddrSpace +from tinygrad.device import is_dtype_supported +from tinygrad.dtype import dtypes, ImageDType, PtrDType, promo_lattice, DType from tinygrad.uop.ops import UOp, Ops, UPat, PatternMatcher, graph_rewrite, GroupOp, identity_element from tinygrad.uop.symbolic import split_uop, uop_given_valid, parse_valid, simplify_valid, sym, symbolic_flat from tinygrad.helpers import getenv, flatten, AMX, prod, partition +from tinygrad.uop.transcendental import xexp2, xlog2, xsin, xpow, TRANSCENDENTAL_SUPPORTED_DTYPES from tinygrad.renderer import Renderer # ***** image load valid simplification ***** @@ -45,10 +47,10 @@ def simplify_valid_load(buf:UOp, start_idx:UOp, valid:UOp) -> UOp|None: new_valid = functools.reduce(operator.and_, ss) if (ss:=[s for s in split_uop(valid, Ops.AND) if s not in drop_stmt]) else None return buf.index(idx, new_valid) -def delete_redundant_gates(store:UOp, buf:UOp, idx:UOp, val:UOp, store_gate:UOp, cast:UOp|None=None) -> UOp|None: +def delete_redundant_gates(buf:UOp, idx:UOp, val:UOp, store_gate:UOp, cast:UOp|None=None) -> UOp|None: if store_gate not in [gate.src[0] for gate in val.toposort() if gate.op is Ops.IF]: return None # remove the gate from the index - return UOp.store(buf.index(idx).cast(cast.dtype) if cast is not None else buf.index(idx), val, *store.src[2:]) + return UOp.store(buf.index(idx).cast(cast.dtype) if cast is not None else buf.index(idx), val) load_store_indexing = PatternMatcher([ # simplify valid @@ -59,7 +61,7 @@ load_store_indexing = PatternMatcher([ (UPat(Ops.INDEX, src=(UPat.var("buf"), UPat.var("start_idx"), UPat(Ops.CONST, arg=True))), lambda buf,start_idx: buf.index(start_idx)), # delete_redundant_gates (after expand) (UPat(Ops.STORE, src=(UPat.any(stidx:=UPat.var("buf").index(UPat.var("idx"), UPat.var("store_gate")), stidx.cast().named("cast")), - UPat.var("val")), name="store", allow_any_len=True), delete_redundant_gates), + UPat.var("val"))), delete_redundant_gates), ]) # ***** load/store grouping ***** @@ -92,7 +94,7 @@ def expand_index(buf:UOp, vec:UOp, mask:UOp|None=None): for grp in grouped_offsets: # get the index offset for this element. using [0] is okay, because they are the same lidx = midx.src[offsets[grp[0]][0]] - if len(grp) > 1: lidx = lidx.cast(ptrdtype.base.vec(len(grp)).ptr(size=ptrdtype.size, addrspace=ptrdtype.addrspace)) + if len(grp) > 1: lidx = lidx.cast(ptrdtype.base.vec(len(grp)).ptr(size=ptrdtype.size, local=ptrdtype.local)) # set the idxs of the output for i,g in enumerate(grp): for oo in offsets[g]: idxs[oo] = global_offset+i @@ -101,42 +103,91 @@ def expand_index(buf:UOp, vec:UOp, mask:UOp|None=None): global_offset += len(grp) assert None not in idxs, f"some idxs are missing {idxs}" # this base thing is for image, we want the CAT to be a normal pointer - post_cat = UOp(Ops.PTRCAT, ptrdtype.base.ptr(size=ptrdtype.size, addrspace=ptrdtype.addrspace).vec(vec.dtype.count), tuple(ret)) + post_cat = UOp(Ops.PTRCAT, ptrdtype.base.ptr(size=ptrdtype.size, local=ptrdtype.local).vec(vec.dtype.count), tuple(ret)) return post_cat.gep(tuple(cast(list[int], idxs))) -def cat_after_store(cat:UOp, data:UOp, sto:UOp): +def cat_after_store(cat:UOp, data:UOp): # TODO: this is written in many places offset = 0 - ret: list[UOp] = [] + ret = [] for s in cat.src: - ret.append(s.store(data.gep(tuple(range(offset, offset+s.dtype.count))), *sto.src[2:])) + ret.append(s.store(data.gep(tuple(range(offset, offset+s.dtype.count))))) offset += s.dtype.count - return UOp(Ops.NOOP, src=tuple(ret)) + return UOp.sink(ret[0], *ret[1:]) -def gep_on_store(gep:UOp, st:UOp, sto:UOp): +def gep_on_store(gep:UOp, st:UOp): # NOTE: we need to invert the gep here, but it may be an expanding gep # fake argsort. TODO: handle duplicates a = {} for i,x in enumerate(gep.arg): a[x] = i new_arg = tuple(x[1] for x in sorted(a.items())) - return gep.src[0].store(st.gep(new_arg), *sto.src[2:]) + return UOp(Ops.STORE, src=(gep.src[0], st.gep(new_arg))) load_store_folding = PatternMatcher([ - (UPat(Ops.INDEX, src=(UPat(Ops.VECTORIZE, src=UPat(GroupOp.Defines, name="buf")), UPat.var("vec"))), expand_index), - (UPat(Ops.INDEX, src=(UPat(Ops.VECTORIZE, src=UPat(GroupOp.Defines, name="buf")), UPat.var("vec"), + (UPat(Ops.INDEX, src=(UPat(Ops.VECTORIZE, src=UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL), name="buf")), UPat.var("vec"))), expand_index), + (UPat(Ops.INDEX, src=(UPat(Ops.VECTORIZE, src=UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL), name="buf")), UPat.var("vec"), UPat.var("mask"))), expand_index), # GEP after LOAD (UPat(Ops.LOAD, src=(UPat(Ops.GEP, name="gep"),), name="ld", allow_any_len=True), lambda gep, ld: ld.replace(dtype=ld.dtype.scalar().vec(gep.dtype.count), src=(gep.src[0],)+ld.src[1:]).gep(gep.arg)), # GEP on data of STORE - (UPat(Ops.STORE, src=(UPat(Ops.GEP, name="gep"), UPat.var("st")), allow_any_len=True, name="sto"), gep_on_store), + (UPat(Ops.STORE, src=(UPat(Ops.GEP, name="gep"), UPat.var("st"))), gep_on_store), # put PTRCAT after LOAD (UPat(Ops.LOAD, src=(UPat(Ops.PTRCAT, name="cat"),), name="ld", allow_any_len=True), lambda cat,ld: UOp(Ops.CAT, ld.dtype, tuple(ld.replace(dtype=x.dtype.base, src=(x,)+ld.src[1:]) for x in cat.src))), # put PTRCAT after STORE - (UPat(Ops.STORE, src=(UPat(Ops.PTRCAT, name="cat"), UPat(name="data")), allow_any_len=True, name="sto"), cat_after_store), + (UPat(Ops.STORE, src=(UPat(Ops.PTRCAT, name="cat"), UPat(name="data"))), cat_after_store), ]) +# ***** optional patterns ***** + +@functools.lru_cache(None) +def magicgu(vmax:int, d:int) -> tuple[int,int]: + # calculate m,s such that x//d == (x*m) >> s for all 0 <= x <= vmax, d>0; adapted from Hacker's Delight, Chapter 10 + nc = (vmax+1)//(d) * d - 1 + nbits = vmax.bit_length() + for s in range(0, 2*nbits + 1): + if 2**s > nc*(d - 1 - (2**s - 1) % d): + m = (2**s + d - 1 - (2**s - 1) % d)//d + return m, s + assert False + +def fast_idiv(ctx: Renderer|None, x: UOp, d: int) -> UOp|None: + # idiv is truncated division, but arithmetic shift is floored division, so can only do non-negative numbers! + if x.vmin<0: return None + sign = 1 if d > 0 else -1 + m,s = magicgu(vmax := min(x.vmax, dtypes.max(x.dtype)), abs(d)) + if m * vmax <= dtypes.max(x.dtype): return sign * ((x*m) >> s) + # promo_lattice needs to return an unsigned type + if ctx is not None and dtypes.is_int(next_dtype := promo_lattice[x.dtype][-1]) and is_dtype_supported(next_dtype, ctx.device): + if m * vmax <= dtypes.max(next_dtype): return sign * ((x.cast(next_dtype)*m) >> s).cast(x.dtype) + return None + +powers_of_two = {2**i:i for i in range(64)} +@functools.cache +def get_late_rewrite_patterns(ops, force_transcendental=False): + pat: list[tuple[UPat, Callable]] = [(UPat(op, dtype=TRANSCENDENTAL_SUPPORTED_DTYPES, src=(UPat.var("d"),)), f) for op,f in \ + ((Ops.EXP2, xexp2), (Ops.LOG2, xlog2), (Ops.SIN, xsin)) if op not in ops or force_transcendental] + # rewrite SQRT to xpow 0.5 + if Ops.SQRT not in ops: pat.append((UPat(Ops.SQRT, src=UPat.var("d")), lambda d: xpow(d, d.const_like(0.5)))) + # rewrite MOD to AND (which should always be supported, but not for generic in tests): x % (2**y) -> x & (2**y-1) + if Ops.AND in ops: pat += [(UPat.var("x", dtypes.ints)%UPat.cvar("c"), lambda x,c: x & (c.arg-1) if c.arg in powers_of_two else None)] + # rewrite MUL/IDIV to SHL+SHR: x*(2**y) -> shl(x,y) and x//(2**y) -> shr(x,y) + if Ops.SHL in ops: pat += [(UPat.var("x", dtypes.ints)*UPat.cvar("c"), lambda c,x: x << v if (v:=powers_of_two.get(c.arg, 0)) else None)] + if Ops.SHR in ops: + # no reason to check x<0 for uints + pat += [(UPat.var("x", dtypes.uints)//UPat.cvar("c"), lambda x,c: x >> v if (v:=powers_of_two.get(c.arg, 0)) else None)] + pat += [(UPat.var("x", dtypes.ints)//UPat.cvar("c"), lambda x,c: (x+(l.const_like(l.vmin) if (l:=(x<0)).vmin==l.vmax else l).where( + c-1, 0)) >> v if (v:=powers_of_two.get(c.arg, 0)) else None)] # (x+(x<0).where(c-1, 0)) >> v + if not getenv("DISABLE_FAST_IDIV"): + pat += [(UPat.var("x", dtypes.ints)//UPat.cvar("d"), lambda ctx, x, d: fast_idiv(ctx, x, d.arg))] + pat += [(UPat.var("x", dtypes.ints)%UPat.cvar("d"), lambda ctx, x, d: x - d*f if (f:=fast_idiv(ctx, x, d.arg)) is not None else None)] + if Ops.NEG in ops: + pat += [(UPat.var('x')*-1, lambda x: x.alu(Ops.NEG))] + if Ops.SUB in ops: pat += [(UPat.var('x')+UPat.var('y').alu(Ops.NEG), lambda x,y: x.alu(Ops.SUB, y))] + if Ops.MULACC in ops: pat += [(UPat.var('a')*UPat.var('b')+UPat.var('c'), lambda a,b,c: a.alu(Ops.MULACC, b, c))] + return PatternMatcher(pat) + # *** correct load/store *** def split_load_store(ctx:Renderer|None, ls:UOp, idx:UOp): @@ -154,8 +205,6 @@ def split_load_store(ctx:Renderer|None, ls:UOp, idx:UOp): must_divide = False elif buf.dtype.base != dtypes.float and buf.dtype.base != dtypes.half and not isinstance(buf.dtype, ImageDType): pass - elif cast(PtrDType, buf.dtype).addrspace == AddrSpace.REG: - pass elif isinstance(buf.dtype, ImageDType): lengths = [4] elif ctx is not None and ctx.supports_float4: @@ -175,15 +224,14 @@ def split_load_store(ctx:Renderer|None, ls:UOp, idx:UOp): for fold_length in lengths: if global_offset+fold_length > sz: continue lidx = buf.index(idx.src[1] + global_offset, idx.src[2] if len(idx.src) > 2 else None) - if fold_length > 1: lidx = lidx.cast(ptrdtype.base.vec(fold_length).ptr(size=ptrdtype.size, addrspace=ptrdtype.addrspace)) + if fold_length > 1: lidx = lidx.cast(ptrdtype.base.vec(fold_length).ptr(size=ptrdtype.size, local=ptrdtype.local)) if ls.op is Ops.STORE: ret.append(ls.replace(src=(lidx,ls.src[1].gep(tuple(range(global_offset, global_offset+fold_length))))+ls.src[2:])) else: ret.append(ls.replace(src=(lidx,)+ls.src[1:], dtype=ls.dtype.scalar().vec(fold_length))) global_offset += fold_length break # if it wasn't split, we return None. otherwise we CAT them - if len(ret) <= 1: return None - return UOp(Ops.CAT, ls.dtype, tuple(ret)) if ls.op is Ops.LOAD else UOp(Ops.NOOP, src=tuple(ret)) + return UOp(Ops.CAT, ls.dtype, tuple(ret)) if len(ret) > 1 else None def image_fixup(ls:UOp): # normal image load or store, with the CAST from expand_index @@ -232,21 +280,17 @@ def no_vectorized_alu(alu:UOp): alus = tuple(UOp(alu.op, alu.dtype.scalar(), tuple(s.gep(i) for s in alu.src), alu.arg) for i in range(alu.dtype.vcount)) return UOp(Ops.VECTORIZE, alu.dtype, alus) -def no_vectorized_buf(buf:UOp): - dtype = cast(PtrDType, buf.dtype) - return buf.replace(dtype=dtype.base.scalar().ptr(dtype.size*dtype.count, dtype.addrspace)).cast(dtype) - -def no_vectorized_index(buf:UOp, cast:UOp, idx:UOp): - cnt = cast.dtype.count - assert idx.dtype.count == 1, f"idx dtype must be 1 {idx.dtype}" - return buf.broadcast(cnt).index(idx.broadcast(cnt)*cnt+UOp.const(dtypes.int.vec(cnt), tuple(range(cnt)))) +def no_vectorized_acc(acc:UOp): + if acc.dtype.count == 1: return None + alus = tuple(UOp(acc.op, acc.dtype.scalar(), + tuple(s.gep(i) if j == 0 else s for j,s in enumerate(acc.src)), acc.arg+(i,)) for i in range(acc.dtype.count)) + return UOp(Ops.VECTORIZE, acc.dtype, alus) devectorize = PatternMatcher([ # no ALU on vectorized dtypes - (UPat((*GroupOp.ALU, Ops.CAST, Ops.BITCAST), name="alu"), no_vectorized_alu), + (UPat((*GroupOp.ALU, Ops.CAST, Ops.BITCAST, Ops.ASSIGN), name="alu"), no_vectorized_alu), (UPat(Ops.WMMA, name="wmma"), no_vectorized_wmma), - (UPat((Ops.DEFINE_LOCAL, Ops.DEFINE_REG), name="buf"), no_vectorized_buf), - (UPat((Ops.DEFINE_LOCAL, Ops.DEFINE_REG), name="buf").cast(name="cast").index(UPat.var("idx")), no_vectorized_index), + (UPat(Ops.DEFINE_ACC, name="acc"), no_vectorized_acc), ]) pm_render = PatternMatcher([ @@ -261,12 +305,11 @@ pm_render = PatternMatcher([ (UPat(Ops.LOAD, src=(UPat(Ops.INDEX, src=(UPat(), UPat(), UPat())).or_casted(),), allow_any_len=True, name="x"), lambda x: x.replace(src=(x.src[0], x.const_like(0))+x.src[1:]) if len(x.src) == 1 or x.src[1].op is Ops.CUSTOM else None), # gate any stores that aren't gated with ifs - (UPat(Ops.STORE, src=(UPat(src=(UPat(), UPat(), UPat(dtype=dtypes.bool)), name="idx").or_casted(), UPat()), name="store", allow_any_len=True), - lambda store,idx: UOp(Ops.STORE, dtype=store.dtype, src=store.src[:2]+(UOp(Ops.IF, src=(idx.src[2],)),)+store.src[2:]) if \ - len(store.src) <= 2 or store.src[2].op != Ops.IF else None), + (UPat(Ops.STORE, dtype=dtypes.void, src=(UPat(src=(UPat(), UPat(), UPat(dtype=dtypes.bool)), name="idx").or_casted(), UPat()), name="store"), + lambda store,idx: UOp(Ops.STORE, src=store.src+(UOp(Ops.IF, src=(idx.src[2],)),))), ]) -# *** Ops.REDUCE -> Ops.DEFINE_ACC *** +# *** Ops.REDUCE -> Ops.DEFINE_ACC+Ops.ASSIGN *** @dataclass class ReduceContext: @@ -286,16 +329,11 @@ def reduce_to_acc(ctx:ReduceContext, red:UOp): assert all(x.dtype == red.dtype for x in lst), f"horizontal reduction mismatch {lst[0].dtype} != {red.dtype}" # if we have a range if len(reduce_range) != 0: - topo = inp.toposort() - stored_ranges = flatten([x.src[2:] for x in topo if x.op is Ops.STORE]) - input_ranges = tuple([x for x in topo if x.op is Ops.RANGE and x not in reduce_range and x not in stored_ranges]) - identity = red.const(red.dtype, identity_element(red.arg, red.dtype.scalar())) - acc = UOp(Ops.DEFINE_REG, red.dtype.ptr(size=1, addrspace=AddrSpace.REG), arg=(ctx.acc_num,)).index(UOp.const(dtypes.int, 0)) - do_store = acc.store(identity, UOp(Ops.NOOP, src=input_ranges)) if len(input_ranges) else acc.store(identity) - lst = [acc.load(do_store, *reduce_range)] + lst # put acc as the first element + acc = UOp(Ops.DEFINE_ACC, red.dtype, (red.const_like(identity_element(red.arg, red.dtype.scalar())),) + tuple(reduce_range), (ctx.acc_num,)) + lst = [acc] + lst # put acc as the first element ctx.acc_num += 1 ret = functools.reduce(lambda x,y: x.alu(red.arg, y), lst) - return acc.load(acc.store(ret, *reduce_range)) if len(reduce_range) != 0 else ret + return acc.assign(ret) if len(reduce_range) != 0 else ret def no_vectorized_reduce(inp:UOp, red:UOp): if inp.dtype != red.dtype: @@ -368,7 +406,8 @@ def reduce_collapse(red:UOp): replaces[s] = UOp(Ops.DEFINE_VAR, dtype=s.dtype, arg=(f'in{len(replaces)}', s.vmin, s.vmax)) collapse_fxn = red.substitute(replaces) sink = graph_rewrite(collapse_fxn, pm_reduce_collapse, name="reduce_collapse") - if any(x.op is Ops.RANGE for x in sink.toposort()): return None + # TODO: why is REDUCE needed here and just RANGE isn't enough? + if any(x.op in {Ops.REDUCE, Ops.RANGE} for x in sink.toposort()): return None return sink.substitute({v:k for k,v in replaces.items()}) def reduce_unparented(red:UOp): diff --git a/tinygrad_repo/tinygrad/codegen/late/expander.py b/tinygrad_repo/tinygrad/codegen/expander.py similarity index 64% rename from tinygrad_repo/tinygrad/codegen/late/expander.py rename to tinygrad_repo/tinygrad/codegen/expander.py index e5944c8c2..17a5faa41 100644 --- a/tinygrad_repo/tinygrad/codegen/late/expander.py +++ b/tinygrad_repo/tinygrad/codegen/expander.py @@ -1,9 +1,8 @@ # this converts a lowerer program into a vectorized program import functools, itertools, operator -from tinygrad.dtype import dtypes, PtrDType, AddrSpace -from tinygrad.helpers import AMX, dedup, flatten, all_same, prod, partition -from tinygrad.uop.ops import UOp, Ops, UPat, PatternMatcher, GroupOp, AxisType +from tinygrad.helpers import AMX, dedup, flatten, all_same, prod +from tinygrad.uop.ops import UOp, Ops, UPat, PatternMatcher, GroupOp def _expand_arg_to_idx(args:tuple[tuple[int, int], ...], rpk:dict[int, int]) -> int: idx, mul = 0, 1 @@ -47,13 +46,11 @@ def do_expand(root:UOp): new_srcs.append(src.src[0].gep(tuple(lst))) else: # non-UNROLL input - if root.op is Ops.IF or src.op is Ops.IF: + if root.op is Ops.IF: # for the first arg of IF, just pass them through ignoring UNROLLS new_srcs.append(src) - elif (root.op is Ops.STORE and i >= 2) or (root.op in {Ops.REDUCE, Ops.BUFFERIZE} and i >= 1) or (root.op is Ops.WMMA and i >= 3): - # for any range args of STORE/REDUCE, pass them through - new_srcs.append(src) - elif root.op is Ops.INDEX and i >= 1 and not isinstance(root.dtype, PtrDType): + elif root.op is Ops.REDUCE and src.op is Ops.RANGE: + # for any range args of REDUCE, pass them through new_srcs.append(src) elif src.dtype.count > 1: # put any input dtype > 1 grouped together @@ -75,7 +72,7 @@ def do_contract(con:UOp): # CONTRACT without UNROLL repeats the element VECTORIZED if ex.op is not Ops.UNROLL: return UOp(Ops.VECTORIZE, con.dtype, con.src*con.dtype.count) # CONTRACT may remove several axes from UNROLL - assert con.dtype == dtypes.void or con.dtype.count == prod([x[1] for x in con.arg]), "dtype is wrong" + assert con.dtype.count == prod([x[1] for x in con.arg]), "dtype is wrong" idxs = [] for rpk in _choices_from_args(new_ex_args:=tuple(x for x in ex.arg if x not in con.arg)): idxs += [_expand_arg_to_idx(ex.arg, {**rpk, **lrpk}) for lrpk in _choices_from_args(con.arg)] @@ -86,9 +83,12 @@ expander = PatternMatcher([ (UPat(Ops.UNROLL, name="outer", src=(UPat(Ops.UNROLL, name="inner"),)), lambda outer, inner: UOp(Ops.UNROLL, outer.dtype, (inner.src[0],), inner.arg+outer.arg)), # do expansion - (UPat((*GroupOp.ALU, Ops.CAST, Ops.BITCAST, Ops.GEP, Ops.WMMA, Ops.LOAD, Ops.STORE, Ops.INDEX, Ops.BUFFERIZE, + (UPat((*GroupOp.ALU, Ops.CAST, Ops.BITCAST, Ops.GEP, Ops.WMMA, Ops.LOAD, Ops.STORE, Ops.INDEX, Ops.ASSIGN, Ops.VECTORIZE, Ops.IF, Ops.REDUCE), name="root", custom_early_reject=set([Ops.UNROLL])), do_expand), (UPat(Ops.CONTRACT, name="con"), do_contract), + # vectorize DEFINE_ACC + (UPat(Ops.VECTORIZE, src=UPat(Ops.DEFINE_ACC, name="acc"), name="v"), + lambda acc,v: acc.replace(dtype=v.dtype, src=(acc.src[0].broadcast(v.dtype.count),)+acc.src[1:])), # BARRIERs aren't actually expanded (UPat(Ops.BARRIER, src=(UPat(Ops.UNROLL, name="ex"),)), lambda ex: UOp(Ops.UNROLL, src=(UOp(Ops.BARRIER, src=ex.src),)*len(ex.src), arg=ex.arg)), @@ -114,49 +114,3 @@ migrate_indexing = PatternMatcher([ # create gate MUST BE BEFORE expander (UPat(Ops.STORE, name="root"), create_gate), ]) - -# **** - -def fix_reduce_unroll(x:UOp): - reduce_range, reduce_expand = partition(x.src[1:], lambda y: y.op is Ops.RANGE) - if len(reduce_expand) == 0: return None - reduce_expand = [x for x in reduce_expand if x.op is not Ops.CONST] - assert all(x.op is Ops.UNROLL for x in reduce_expand), f"not all UNROLLS in {reduce_expand}" - ret = x.src[0] - if len(contract_axis:=flatten(x.arg for x in reduce_expand)): - ret = UOp(Ops.CONTRACT, x.dtype.vec(prod(x[1] for x in contract_axis)), (ret,), tuple(contract_axis), tag=1) - # REDUCE supports both "horizontal" reduction and range reduction. the horizontal elements are taken in the nearest group - return x.replace(src=(ret,)+tuple(reduce_range)) - -def fix_store_unroll(x:UOp): - store_expand, store_range = partition(x.src[2:], lambda y: y.op is Ops.UNROLL) - if len(store_expand) == 0: return None - return UOp(Ops.CONTRACT, dtypes.void, (x.replace(src=x.src[:2]+tuple(store_range)),), tuple(flatten(x.arg for x in store_expand)), tag=1) - -def fix_group_for_reduce(x:UOp): - reduce_gfr, reduce_r = partition(x.src[1:], lambda u: u.op is Ops.RANGE and u.arg[1] == AxisType.GROUP_REDUCE) - if len(reduce_gfr) == 0: return None - - # NOTE: if there's other locals here, we need them in the buffer too - upstream_locals = [u for u in x.toposort() if u.op is Ops.RANGE and u.arg[1] == AxisType.LOCAL] - - # do only the non grouped reduces early - ret = x.replace(src=(x.src[0],)+tuple(reduce_r)) - reduce_loop = [x.replace(arg=(x.arg[0]+100, AxisType.REDUCE)) for x in reduce_gfr] - buf = ret.bufferize(*upstream_locals, *reduce_gfr, arg=(AddrSpace.LOCAL, reduce_gfr[0].arg[0])).index(*upstream_locals, *reduce_loop) - - # gate with an if on the store + do the final reduce - buf = UOp(Ops.IF, dtype=buf.dtype, src=(functools.reduce(operator.and_, [x.eq(0) for x in reduce_gfr]), buf)) - return buf.reduce(*reduce_loop, arg=x.arg) - -pm_pre_expander = PatternMatcher([ - # rewrite UPCAST/UNROLL range to something to be expanded - (UPat(Ops.RANGE, name="r"), - lambda r: UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(s:=r.vmax+1), tuple(range(s))),), ((r.arg[0],s),)) \ - if r.arg[1] in {AxisType.UNROLL, AxisType.UPCAST} else None), - # fix REDUCEs with UNROLLs - (UPat(Ops.REDUCE, name="x"), fix_reduce_unroll), - (UPat(Ops.STORE, name="x"), fix_store_unroll), - # fix group for reduce - (UPat(Ops.REDUCE, name="x"), fix_group_for_reduce), -]) diff --git a/tinygrad_repo/tinygrad/codegen/gpudims.py b/tinygrad_repo/tinygrad/codegen/gpudims.py deleted file mode 100644 index d974327ba..000000000 --- a/tinygrad_repo/tinygrad/codegen/gpudims.py +++ /dev/null @@ -1,94 +0,0 @@ -import math -from tinygrad.uop.ops import UOp, Ops, sint, PatternMatcher, UPat, KernelInfo, ssimplify, AxisType -from tinygrad.helpers import all_int, dedup -from tinygrad.dtype import dtypes -from tinygrad.shape.view import get_contraction -from tinygrad.renderer import Renderer - -def _group_dims(dims:tuple[sint, ...], max_sizes:tuple[int, ...]): - # TODO: symbolic shape - if not all_int(dims): return dims - while len(dims) > len(max_sizes) or any(d > m for d,m in zip(dims, max_sizes)): - for i,m in enumerate(max_sizes): - if i < (len(dims)-1) and dims[i] * dims[i+1] <= m: - dims = dims[:i] + (dims[i]*dims[i+1],) + dims[i+2:] - break - else: return None - return dims - -def _split_dims(dims, max_sizes): - if all(d <= m for d,m in zip(dims, max_sizes)): return dims - _dims = list(dims) + [1]*(3-len(dims)) - for i in range(len(_dims)): - while _dims[i] > max_sizes[i]: - div = next((d for d in range(2, math.ceil(math.sqrt(_dims[i])) + 1) if (_dims[i] % d) == 0), 1) - if div == 1: raise RuntimeError(f"cannot limit dim {dims=}, {max_sizes=}") - _dims[i], _dims[(i+1)%len(_dims)] = _dims[i]//div, _dims[(i+1)%len(_dims)]*div - return tuple(_dims[:2] if _dims[2] == 1 else _dims[0] if _dims[1:3] == [1,1] else _dims) - -def get_grouped_dims(prefix, dims:tuple[sint, ...], max_sizes:tuple[int, ...]|None, reverse=False) -> list[UOp]: - if reverse: dims = dims[::-1] - # try to group first: (a, b, c, d) -> (ab, c, d) - limited = (grouped if (grouped := _group_dims(dims, max_sizes)) else dims) if max_sizes is not None else dims - # check if grouping failed - if max_sizes is not None and len(limited) > len(max_sizes): raise RuntimeError(f"cannot limit dim {dims=}, {max_sizes=}") - # try to split up dims: (a,) -> (b, c) - if limited == dims: limited = _split_dims(dims, max_sizes) if max_sizes is not None else dims - ret = raw_idxs = [UOp(Ops.SPECIAL, dtypes.int, (), (f"{prefix}{i}", s)) for i,s in enumerate(limited)] - if len(limited) < len(dims): - ret = [] - if (contraction:=get_contraction(dims, limited)) is None: raise AssertionError(f"get_contraction should not be None {dims=} {limited=}") - for idx, contraction_group in zip(raw_idxs, contraction): - for c in contraction_group[:-1]: - ret.append(idx % dims[c]) - idx //= dims[c] - ret.append(idx) - elif len(limited) > len(dims): - a, b = len(limited), len(dims) - if a == 2 and b == 1: ret = [raw_idxs[0] * limited[1] + raw_idxs[1]] - if a == 3 and b == 1: ret = [raw_idxs[0] * (limited[1] * limited[2]) + raw_idxs[1] * limited[2] + raw_idxs[2]] - if a == 3 and b == 2: ret = [raw_idxs[0] * limited[1] + raw_idxs[1], raw_idxs[2]] - return ret[::-1] if reverse else ret - -def add_gpudims(ctx:Renderer, s:UOp): - if s.arg is None: return None - s_topo = list(s.toposort()) - if any(x.op is Ops.SPECIAL for x in s_topo): return None - - # get ranges - all_ranges = {x.arg[0:-1]:x for x in s_topo if x.op is Ops.RANGE} - - # extract global/local dims - global_dims = sorted(dedup([x.arg[0:-1] for x in all_ranges.values() if x.arg[-1] is AxisType.GLOBAL])) - local_dims = sorted(dedup([x.arg[0:-1] for x in all_ranges.values() if x.arg[-1] in (AxisType.LOCAL, AxisType.GROUP_REDUCE)])) - if not global_dims and not local_dims: return None - - # get global and local shape - ranges = [all_ranges[r] for r in global_dims+local_dims if r in all_ranges] - global_shape = tuple([ssimplify(r.src[0]) for r in ranges if r.arg[0:-1] in global_dims]) - local_shape = tuple([ssimplify(r.src[0]) for r in ranges if r.arg[0:-1] in local_dims]) - - # get the idxs - ki: KernelInfo = s.arg - if ki.dont_use_locals: - assert not local_dims, "can't use locals if there's no local dims" - idxs = get_grouped_dims("idx", global_shape, ctx.global_max, reverse=True) - else: - # define indexes for GPU-like execution - idxs = get_grouped_dims("gidx", global_shape, ctx.global_max, reverse=True) + get_grouped_dims("lidx", local_shape, ctx.local_max) - - # apply to multiple ranges - subs = {} - for r in s_topo: - if r.op is not Ops.RANGE: continue - try: - ii = (global_dims+local_dims).index(r.arg[0:-1]) - if r.arg[1] == AxisType.REDUCE: continue - subs[r] = idxs[ii] - except ValueError: continue - return s.substitute(subs) - -pm_add_gpudims = PatternMatcher([ - # add gpudims must be last - (UPat(Ops.SINK, name="s"), add_gpudims), -]) diff --git a/tinygrad_repo/tinygrad/codegen/late/linearize.py b/tinygrad_repo/tinygrad/codegen/linearize.py similarity index 88% rename from tinygrad_repo/tinygrad/codegen/late/linearize.py rename to tinygrad_repo/tinygrad/codegen/linearize.py index 54ff2cbfc..d205299e5 100644 --- a/tinygrad_repo/tinygrad/codegen/late/linearize.py +++ b/tinygrad_repo/tinygrad/codegen/linearize.py @@ -3,7 +3,7 @@ import heapq from collections import defaultdict from dataclasses import dataclass, replace from tinygrad.uop.ops import UOp, Ops, PatternMatcher, UPat, GroupOp -from tinygrad.helpers import dedup, all_same, flatten, BLOCK_REORDER +from tinygrad.helpers import dedup, partition, all_same, flatten, getenv # NOTE: any toposort should be valid here, unlike last time this isn't required, it's just for speed def block_reorder(lst:list[UOp]) -> list[UOp]: @@ -86,18 +86,26 @@ class BlockContext: ctx.child_count[s] += 1 this_block_ctx += ctx.last_ctx(s) - # save the block ctx. SINK never has anything - ctx.block_ctxs[u] = _sort_ctx(this_block_ctx) if u.op is not Ops.SINK else () + # save the block ctx + ctx.block_ctxs[u] = _sort_ctx(this_block_ctx) # RANGE/IF add to the next ctx # STORE/ASSIGN subtract from the next ctx if u.op in {Ops.RANGE, Ops.IF}: ctx.child_ctxs[u] = _sort_ctx(ctx.block_ctxs[u] + (u,)) - elif u.op is Ops.STORE: ctx.child_ctxs[u] = tuple([y for y in ctx.block_ctxs[u] if y not in u.src]) + elif u.op is Ops.STORE: + # ugh, deal with non-reduce locals. probably wrong + if any(x.op is Ops.DEFINE_LOCAL for x in u.src[0].toposort()): + idx_context, store_context = ctx.last_ctx(u.src[0]), ctx.last_ctx(u.src[1]) + ctx.child_ctxs[u] = tuple([y for y in store_context if y not in idx_context and y.op is Ops.RANGE]) + else: ctx.child_ctxs[u] = () + elif u.op is Ops.ASSIGN: + assert u.src[0].op is Ops.DEFINE_ACC + ctx.child_ctxs[u] = tuple([y for y in ctx.last_ctx(u.src[1]) if y not in u.src[0].src[1:]]) return ctx # ***** make blocks ***** -DONT_PLACE_IN_BLOCK = {Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL, Ops.DEFINE_REG, Ops.DEFINE_VAR, Ops.SPECIAL, Ops.CONST} +DONT_PLACE_IN_BLOCK = {Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL, Ops.DEFINE_VAR, Ops.SPECIAL, Ops.CONST} def add_blockends(base_block:UOp, new_ctx:tuple[UOp, ...], current_ctx:tuple[UOp, ...], cnt:int=1) -> UOp: ends_to_add = [z for z in new_ctx if z not in current_ctx] @@ -150,7 +158,7 @@ def make_block_bottom_up(ctx:BlockContext, x:UOp): srcs.append(add_blockends(base_block, new_ctx, current_ctx)) lst = lst[::-1] - if BLOCK_REORDER: lst = block_reorder(lst) + if getenv("BLOCK_REORDER", 1): lst = block_reorder(lst) bb = BasicBlock(tuple(lst), ctx=current_ctx, cnt=child_count, child_ctx=child_ctx) return UOp(Ops.BLOCK, src=tuple(srcs), arg=bb) @@ -207,15 +215,12 @@ def remove_blockend(x:UOp): assert all_same(parent_blocks), f"should never have two parent blocks (has {len(parent_blocks)})" parent_block = parent_blocks[0] assert len(parent_blocks) == parent_block.arg.cnt - # NOTE: DEFINE_ACC doesn't have to be handled in any special way - late_ops = list(x.arg.lst) + # range needs DEFINE_ACC to be before the range (never in DEFINE_ACC for if) + early_ops, late_ops = partition(x.arg.lst, lambda y: y.op is Ops.DEFINE_ACC and x.arg.end in y.src) # NOTE: we have to add a barrier at the start if barrier is used in the range if x.op is Ops.BLOCKEND and any(y.op is Ops.BARRIER for y in late_ops) and late_ops[-1].op is Ops.ENDRANGE: late_ops = [UOp(Ops.BARRIER)] + late_ops - # peephole opt, remove any BARRIERs next to each other - for i in range(len(late_ops)-1): - if late_ops[i].op is Ops.BARRIER and late_ops[i+1].op is Ops.BARRIER: late_ops[i+1] = UOp(Ops.NOOP) - arg = BasicBlock(parent_block.arg.lst+tuple(late_ops), tuple([y for y in x.arg.ctx if y is not x.arg.end]), cnt=x.arg.cnt) + arg = BasicBlock(tuple(early_ops)+parent_block.arg.lst+tuple(late_ops), tuple([y for y in x.arg.ctx if y is not x.arg.end]), cnt=x.arg.cnt) return UOp(Ops.BLOCK, src=tuple(y for y in x.src if y is not parent_block)+parent_block.src, arg=arg) block_merge = PatternMatcher([ @@ -227,7 +232,7 @@ block_merge = PatternMatcher([ def finalize(sink:UOp) -> UOp: if sink.op is not Ops.BLOCK or not all(x.op in DONT_PLACE_IN_BLOCK for x in sink.src): - raise RuntimeError(f"linearize failure {sink.op} {[x.op for x in sink.src if x.op not in DONT_PLACE_IN_BLOCK]}") + raise RuntimeError("linearize failure") # place the early things lst = sorted(dedup(sink.src), key=lambda x: x.tuplize) + list(sink.arg.lst) diff --git a/tinygrad_repo/tinygrad/codegen/lowerer.py b/tinygrad_repo/tinygrad/codegen/lowerer.py index 663a9b0fa..148c72398 100644 --- a/tinygrad_repo/tinygrad/codegen/lowerer.py +++ b/tinygrad_repo/tinygrad/codegen/lowerer.py @@ -1,66 +1,136 @@ # the job of the lowerer is to do indexing +import math from dataclasses import dataclass -from tinygrad.uop.ops import KernelInfo, UOp, Ops, PatternMatcher, UPat, sint_to_uop, AxisType, graph_rewrite, resolve +from typing import cast +from tinygrad.dtype import dtypes, PtrDType +from tinygrad.uop.ops import KernelInfo, UOp, Ops, PatternMatcher, UPat, sint, sint_to_uop +from tinygrad.renderer import Renderer +from tinygrad.helpers import all_int, prod, partition, flatten +from tinygrad.shape.view import get_contraction # ***** indexing ***** +def _group_dims(dims:tuple[sint, ...], max_sizes:tuple[int, ...]): + # TODO: symbolic shape + if not all_int(dims): return dims + while len(dims) > len(max_sizes) or any(d > m for d,m in zip(dims, max_sizes)): + for i,m in enumerate(max_sizes): + if i < (len(dims)-1) and dims[i] * dims[i+1] <= m: + dims = dims[:i] + (dims[i]*dims[i+1],) + dims[i+2:] + break + else: return None + return dims + +def _split_dims(dims, max_sizes): + if all(d <= m for d,m in zip(dims, max_sizes)): return dims + _dims = list(dims) + [1]*(3-len(dims)) + for i in range(len(_dims)): + while _dims[i] > max_sizes[i]: + div = next((d for d in range(2, math.ceil(math.sqrt(_dims[i])) + 1) if (_dims[i] % d) == 0), 1) + if div == 1: raise RuntimeError(f"cannot limit dim {dims=}, {max_sizes=}") + _dims[i], _dims[(i+1)%len(_dims)] = _dims[i]//div, _dims[(i+1)%len(_dims)]*div + return tuple(_dims[:2] if _dims[2] == 1 else _dims[0] if _dims[1:3] == [1,1] else _dims) + +def get_grouped_dims(prefix, dims:tuple[sint, ...], max_sizes:tuple[int, ...]|None, reverse=False) -> list[UOp]: + if reverse: dims = dims[::-1] + # try to group first: (a, b, c, d) -> (ab, c, d) + limited = (grouped if (grouped := _group_dims(dims, max_sizes)) else dims) if max_sizes is not None else dims + # check if grouping failed + if max_sizes is not None and len(limited) > len(max_sizes): raise RuntimeError(f"cannot limit dim {dims=}, {max_sizes=}") + # try to split up dims: (a,) -> (b, c) + if limited == dims: limited = _split_dims(dims, max_sizes) if max_sizes is not None else dims + ret = raw_idxs = [UOp(Ops.SPECIAL, dtypes.int, (), (f"{prefix}{i}", s)) for i,s in enumerate(limited)] + if len(limited) < len(dims): + ret = [] + if (contraction:=get_contraction(dims, limited)) is None: raise AssertionError(f"get_contraction should not be None {dims=} {limited=}") + for idx, contraction_group in zip(raw_idxs, contraction): + for c in contraction_group[:-1]: + ret.append(idx % dims[c]) + idx //= dims[c] + ret.append(idx) + elif len(limited) > len(dims): + a, b = len(limited), len(dims) + if a == 2 and b == 1: ret = [raw_idxs[0] * limited[1] + raw_idxs[1]] + if a == 3 and b == 1: ret = [raw_idxs[0] * (limited[1] * limited[2]) + raw_idxs[1] * limited[2] + raw_idxs[2]] + if a == 3 and b == 2: ret = [raw_idxs[0] * limited[1] + raw_idxs[1], raw_idxs[2]] + return ret[::-1] if reverse else ret @dataclass class IndexContext: - axis_types: tuple[AxisType, ...] idxs: list[UOp] - start: int = 0 + ridxs: list[UOp] -def shape_to_idx(s, axis_types, start=0): - return [UOp.range(sint_to_uop(s), start+i, at) for i, (s, at) in enumerate(zip(s, axis_types))] +def get_index(ast:UOp, opts:Renderer) -> IndexContext: + ki = ast.arg if isinstance(ast.arg, KernelInfo) else KernelInfo() + # NOTE: assumes the shape is + full_shape = ast.full_shape + first_upcasted = len(full_shape)-ki.upcasted + # if there's no reduce, this is first_upcasted. assumes reduces are at the end + first_reduce = min([first_upcasted]+flatten(x.axis_arg for x in ast.toposort() if x.op is Ops.REDUCE_AXIS)) + local_loads = [x for x in ast.toposort() if x.op is Ops.LOAD and x.src[0].base.op is Ops.DEFINE_LOCAL] + # NOTE: sum up the reduced axes looking across all local loads, yields the number of grouped reduces + group_for_reduces = sum([any(l.st_arg.shape[i]!=ast.src[0].st_arg.shape[i] for l in local_loads) for i in range(first_reduce,first_upcasted)]) + global_dims = first_reduce-ki.local_dims -def get_index(ast:UOp) -> IndexContext: - axis_types = ast.arg.axis_types if isinstance(ast.arg, KernelInfo) else () - if len(ast.full_shape) != len(axis_types) and ast.st is not None: - axis_types = tuple([AxisType.REDUCE if resolve(s != fs) else AxisType.LOOP for s,fs in zip(ast.shape, ast.full_shape)]) - return IndexContext(axis_types, [], 0) + if opts.has_local: + if ki.dont_use_locals: + assert ki.local_dims == 0, "can't use locals if there's no local dims" + idxs = get_grouped_dims("idx", full_shape[:global_dims], opts.global_max, reverse=True) + else: + # define indexes for GPU-like execution + idxs = get_grouped_dims("gidx", full_shape[:global_dims], opts.global_max, reverse=True) + \ + get_grouped_dims("lidx", full_shape[global_dims:first_reduce+group_for_reduces], opts.local_max) + else: + # all loops are RANGES + idxs = [UOp(Ops.RANGE, dtypes.int, (sint_to_uop(g),), i) for i,g in enumerate(full_shape[:first_reduce])] + + # reduce loops + idxs += [UOp(Ops.RANGE, dtypes.int, (sint_to_uop(g),), i) + for i,g in enumerate(full_shape[first_reduce+group_for_reduces:first_upcasted], start=first_reduce+group_for_reduces)] + + # upcast loops + for i,g in enumerate(full_shape[first_upcasted:], start=first_upcasted): + assert isinstance(g, int), "needs to be int to upcast/unroll" + idxs.append(UOp(Ops.UNROLL, dtypes.int, (UOp.const(dtypes.int.vec(g), tuple(range(g))),), ((i,g),))) + + # late indexes (group for reduce) + ridxs = idxs[:] + for a in range(first_reduce, first_reduce+group_for_reduces): + ridxs[a] = UOp(Ops.RANGE, dtypes.int, (sint_to_uop(full_shape[a]),), 1000+a) + + return IndexContext(idxs, ridxs) # ***** lowering (given index) ***** -def subblock(ctx: IndexContext, full_new_idx: list[UOp], src: UOp): - lc = IndexContext(ctx.axis_types, full_new_idx, ctx.start+1000) - ctx.start = lc.start - return graph_rewrite(src, pm_lowerer, lc, name="subblock", bottom_up=True) - def lower_reduce_axis(ctx: IndexContext, x: UOp): - new_idxs = shape_to_idx(x.src[0].shape, ctx.axis_types, ctx.start) - full_new_idx = list(ctx.idxs) - for a in x.axis_arg: full_new_idx[a] = new_idxs[a] - ret = subblock(ctx, full_new_idx, x.src[0]) - return UOp(Ops.REDUCE, x.dtype, (ret,)+tuple([full_new_idx[i] for i in x.axis_arg]), x.arg[0]) + # NOTE: always using ridxs is fine here + reduce_range, reduce_expand = partition([ctx.ridxs[i] for i in x.axis_arg], lambda y: y.op is Ops.RANGE) + assert all(x.op is Ops.UNROLL for x in reduce_expand), f"not all UNROLLS in {reduce_expand} for {x.axis_arg}" + alu_op: Ops = x.arg[0] + ret = x.src[0] + if len(contract_axis:=flatten(x.arg for x in reduce_expand)): + ret = UOp(Ops.CONTRACT, x.dtype.vec(prod(x[1] for x in contract_axis)), (ret,), tuple(contract_axis)) + # REDUCE supports both "horizontal" reduction and range reduction. the horizontal elements are taken in the nearest group + return UOp(Ops.REDUCE, x.dtype, (ret,)+tuple(reduce_range), alu_op) -def lower_store(ctx: IndexContext, x: UOp, buf: UOp): - # TODO: reenable after REDUCE_AXIS is fixed - #assert x.src[1].shape == x.src[0].shape, f"shape mismatch on store {x.src[1].shape} != {x.src[0].shape}" +def lower_load_store(ctx: IndexContext, x: UOp, buf: UOp): + idx, valid = x.st_arg.to_indexed_uops(ctx.ridxs if x.op is Ops.LOAD and buf.op is Ops.DEFINE_LOCAL else ctx.idxs) + if x.op is Ops.LOAD: + barrier = (UOp(Ops.BARRIER, dtypes.void, (x.src[1],)),) if buf.op is Ops.DEFINE_LOCAL else () + return UOp(Ops.LOAD, x.dtype, (buf.index(idx, valid),) + barrier) + # NOTE: only store the local reduceop in the threads that are actually doing the reduce + if cast(PtrDType, buf.dtype).local and x.src[1].op is Ops.REDUCE: + reduce_input = x.src[1].src[0] + store_back = reduce_input.op is Ops.LOAD and cast(PtrDType, reduce_input.src[0].dtype).local + else: store_back = False + if (not cast(PtrDType, buf.dtype).local) or store_back: + for oidx, ridx in zip(ctx.idxs, ctx.ridxs): + if oidx is not ridx: valid = valid * oidx.eq(0) + return UOp(Ops.STORE, dtypes.void, (buf.index(idx, valid), x.src[1])) - new_idxs = shape_to_idx(x.src[0].shape, ctx.axis_types, ctx.start) - idx, valid = x.st_arg.to_indexed_uops(new_idxs) - used_idxs = [x for x in UOp.sink(idx, valid).toposort() if x in new_idxs] - real_new_idxs = [] - for i in range(len(x.src[0].shape)): - if new_idxs[i] in used_idxs or len(ctx.idxs) <= i: real_new_idxs.append(new_idxs[i]) - else: real_new_idxs.append(ctx.idxs[i]) - - stored = subblock(ctx, real_new_idxs, x.src[1]) - used_ranges = [x for x in used_idxs if x.op is Ops.RANGE] - return buf.index(idx, valid).store(stored, *used_ranges) - -def fixup_wmma(ctx:IndexContext, x:UOp): - if x.tag is not None: return None - new_idxs = shape_to_idx(x.src[0].shape, ctx.axis_types, ctx.start) - full_new_idx = list(ctx.idxs) - for a in x.arg[-1]: full_new_idx[a] = new_idxs[a] - - srcs = subblock(ctx, full_new_idx, UOp.sink(*x.src)).src - - # NOTE: this assumes these are expanded. which now shouldn't change anything - new_x_arg_m2 = tuple([tuple([(full_new_idx[a].arg[0], sz) for a,sz in v]) for v in x.arg[-2]]) - new_x_arg_m1 = tuple([full_new_idx[a].arg[0] for a in x.arg[-1]]) - return x.replace(src=srcs, arg=x.arg[:-2]+(new_x_arg_m2, new_x_arg_m1), tag=1) +def lower_const(ctx:IndexContext, view:UOp, c:UOp): + if all(x.mask is None for x in view.arg.views): return c + _, valid = view.arg.to_indexed_uops(ctx.idxs) + return valid.where(c, c.const_like(0)) pm_lowerer = PatternMatcher([ # TODO: remove these hacks @@ -69,18 +139,10 @@ pm_lowerer = PatternMatcher([ # hack for old style VALID (now it's just VIEW(CONST)) (UPat(Ops.VALID, src=(UPat(Ops.VIEW, name="v"),)).where(UPat.cvar("c"), UPat(Ops.CONST, arg=0)), lambda c,v: c.replace(src=()).view(v.arg)), - # consts and loads - (UPat(Ops.VIEW, src=(UPat((Ops.CONST, Ops.DEFINE_VAR), name="c"),), name="view"), - lambda ctx,view,c: c if all(x.mask is None for x in view.arg.views) else view.arg.to_indexed_uops(ctx.idxs)[1].where(c, c.const_like(0))), - (UPat(Ops.LOAD, src=(UPat.var("buf").view(),), allow_any_len=True, name="x"), - lambda ctx,buf,x: UOp(Ops.LOAD, x.dtype, (buf.index(*x.st_arg.to_indexed_uops(ctx.idxs)),)+x.src[1:])), - # reduce/view_const (UPat(Ops.REDUCE_AXIS, name="x"), lower_reduce_axis), - (UPat(Ops.STORE, src=(UPat.var("buf").view(),), allow_any_len=True, name="x"), lower_store), - (UPat(Ops.WMMA, name="x"), fixup_wmma), - - # axis fixups for WMMA - (UPat((Ops.CONTRACT, Ops.UNROLL), name="x"), - lambda ctx,x: x.replace(tag=1, arg=tuple([(ctx.idxs[a].arg[0], sz) for a,sz in x.arg])) if x.tag is None else None), + (UPat(Ops.VIEW, src=(UPat((Ops.CONST, Ops.DEFINE_VAR), name="c"),), name="view"), lower_const), + # rewrite LOAD/STORE VIEW to LOAD/STORE with indexed + (UPat((Ops.LOAD, Ops.STORE), src=(UPat.var("buf").view(),), allow_any_len=True, name="x"), lower_load_store), + (UPat(Ops.INDEX, src=(UPat.var("b"), UPat.var("idx"), UPat.const(dtypes.bool, True))), lambda b, idx: b.index(idx)), ]) diff --git a/tinygrad_repo/tinygrad/codegen/opt/__init__.py b/tinygrad_repo/tinygrad/codegen/opt/__init__.py deleted file mode 100644 index d879a2e56..000000000 --- a/tinygrad_repo/tinygrad/codegen/opt/__init__.py +++ /dev/null @@ -1,51 +0,0 @@ -# opt opinionatedly transforms an ast into an optimized ast using either heuristics or beam search - -from tinygrad.codegen.opt.kernel import Kernel -from tinygrad.codegen.opt.heuristic import hand_coded_optimizations -from tinygrad.uop.ops import UOp, PatternMatcher, UPat, Ops, KernelInfo -from tinygrad.helpers import NOOPT, BEAM, USE_TC, getenv -from tinygrad.renderer import Renderer -from tinygrad.uop.spec import type_verify - -def get_optimized_ast(ast:UOp, renderer:Renderer) -> UOp|None: - """ - Optimize an AST based on heuristics or BEAM search. - - Args: - ast: The Ops.SINK rooted AST - renderer: The renderer used to generate the code - - Returns: - The Ops.SINK rooted AST transformed to apply the opts and with a KernelInfo in the arg. - """ - - # no shape, no opt - if ast.src[0].st is None: return None - new_arg = ast.arg - if new_arg is None: - k = Kernel(ast, opts=renderer) - if not NOOPT: - if not k.apply_tensor_cores(USE_TC.value): k.apply_opts(hand_coded_optimizations(k)) - if BEAM >= 1: - from tinygrad.codegen.opt.search import beam_search, bufs_from_lin - kb = Kernel(ast, opts=renderer) - rawbufs = bufs_from_lin(kb, allocate=False) - k = beam_search(kb, rawbufs, BEAM.value, bool(getenv("BEAM_ESTIMATE", 1))) - new_arg = KernelInfo(opts_to_apply=tuple(k.applied_opts)) - elif len(new_arg.applied_opts): return None - return Kernel(ast.replace(arg=None), opts=renderer).get_optimized_ast().replace(arg=new_arg) - -pm_get_optimization = PatternMatcher([ - (UPat(Ops.SINK, name="ast"), lambda ctx,ast: get_optimized_ast(ast, ctx)), -]) - -def apply_opt(ast:UOp, renderer:Renderer): - k = Kernel(ast, opts=renderer) - k.apply_opts(ast.arg.opts_to_apply) - ret = k.get_optimized_ast() - if __debug__: type_verify(list(ret.toposort())) - return ret - -pm_do_optimize = PatternMatcher([ - (UPat(Ops.SINK, name="ast"), lambda ctx,ast: apply_opt(ast, ctx) if ast.arg is not None and ast.arg.opts_to_apply is not None else None), -]) diff --git a/tinygrad_repo/tinygrad/codegen/opt/heuristic.py b/tinygrad_repo/tinygrad/codegen/opt/heuristic.py deleted file mode 100644 index 40b3a9d3c..000000000 --- a/tinygrad_repo/tinygrad/codegen/opt/heuristic.py +++ /dev/null @@ -1,125 +0,0 @@ -import itertools -from tinygrad.codegen.opt.kernel import Kernel, Opt, OptOps, KernelOptError, AxisType -from tinygrad.helpers import getenv, DEBUG, prod, NOLOCALS -from tinygrad.dtype import ImageDType -from tinygrad.uop.ops import Ops, resolve - -def hand_coded_optimizations(k:Kernel) -> list[Opt]: - # make a copy so it does not mutate the input - k = k.copy() - - # should use matvec - TODO: adjust/tune based on the wide vs tall/large vs small mat - MV_BLOCKSIZE, MV_THREADS_PER_ROW, MV_ROWS_PER_THREAD = getenv("MV_BLOCKSIZE", 4), getenv("MV_THREADS_PER_ROW", 8), getenv("MV_ROWS_PER_THREAD", 4) - if k.opts.has_local and getenv("MV",1) != 0 and (MV_BLOCKSIZE > 1 or MV_THREADS_PER_ROW > 1 or MV_ROWS_PER_THREAD > 1) and \ - k.reduceop is not None and k.reduceop.arg[0] is Ops.ADD and len(k.full_shape) >= 2 and k.opts.has_shared and \ - (mulop:=k.reduceop.src[0]).op is Ops.MUL and mulop.src[0].op is Ops.LOAD and mulop.src[1].op is Ops.LOAD: - st0, st1 = k.sts[k.bufs.index(mulop.src[0])], k.sts[k.bufs.index(mulop.src[1])] - strides0, strides1 = st0.real_strides(), st1.real_strides() - def has_expanded_axis(shape, strides): return any(resolve(s > 1) and not resolve(st != 0) for s,st in zip(shape,strides)) - if strides0[first_reduce:=(k.axes_of(AxisType.REDUCE)[0])] == 1 and \ - not (has_expanded_axis(st0.shape, strides0) and has_expanded_axis(st1.shape, strides1)): - for global_idx in k.axes_of(AxisType.GLOBAL): - if k.full_shape[first_reduce]%MV_THREADS_PER_ROW == 0 and k.full_shape[global_idx]%(MV_BLOCKSIZE*MV_ROWS_PER_THREAD) == 0: - if DEBUG >= 3: - print(f"MATVEC: {k.full_shape=} {first_reduce=} {strides0=} {MV_BLOCKSIZE=} {MV_THREADS_PER_ROW=} {MV_ROWS_PER_THREAD=}") - if MV_THREADS_PER_ROW > 1: k.apply_opt(Opt(OptOps.GROUP, 0, MV_THREADS_PER_ROW)) - if MV_BLOCKSIZE > 1: k.apply_opt(Opt(OptOps.LOCAL, global_idx, MV_BLOCKSIZE)) - if MV_ROWS_PER_THREAD > 1: k.apply_opt(Opt(OptOps.UPCAST, global_idx, MV_ROWS_PER_THREAD)) - return k.applied_opts - - # are we grouping? (requires local shape support) - if resolve(prod(k.output_shape[i] for i in k.upcastable_dims) <= 2048, False): - for sz in [16]: - try: - k.apply_opt(Opt(OptOps.GROUPTOP, 0, sz)) - break - except KernelOptError: pass - - # upcast float4 images - for buf_index,buf in enumerate(k.bufs): - if isinstance(buf.src[0].dtype, ImageDType): - if (unit_stride_axes_mul_4 := [i for i in k.sts[buf_index].unit_stride_axes(ignore_valid=True) if k.sts[buf_index].shape[i]%4 == 0]): - if (axis:=unit_stride_axes_mul_4[0]) in k.upcastable_dims: - k.apply_opt(Opt(OptOps.UPCAST, axis, 4)) - elif axis in k.unrollable_dims: - k.apply_opt(Opt(OptOps.UNROLL, k.unrollable_dims.index(axis), 4)) - - # no more opt if we are grouping - if k.group_for_reduces: return k.applied_opts - - # **** below this line need to be optional and benchmarked **** - - # if there are small dims with lots of valid masks, upcast them (they might be from Tensor.stack) - to_upcast: list[int] = [] - # upcast leading axes first (hack-ish for winograd; we actually want to upcast masked axes with low stride first) - for axis in k.upcastable_dims: - if k.full_shape[axis] <= 7 and any(st.axis_is_masked(axis) for st in k.sts) and \ - prod(k.full_shape[j] for j in to_upcast) * k.full_shape[axis] <= 7 * 7: - if DEBUG >= 4: print(f"upcasting masked axis : {axis}") - to_upcast.append(axis) - for axis in to_upcast[::-1]: k.apply_opt(Opt(OptOps.UPCAST, axis, 0)) - - # potentially do more upcasts of non reduce axes based on a heuristic - is_dsp = k.opts is not None and k.opts.device == "DSP" - upcasted_axis: set[int] = set() - while resolve(prod(k.output_shape[i] for i in k.upcastable_dims) >= 1024): - xb_choices = [] - # consider all upcastable axes with 3 or 4 upcast (128 on the DSP) - for axis, upcast_amount in itertools.product(k.upcastable_dims, ([128] if not len(upcasted_axis) else []) if is_dsp else [3,4]): - # if we haven't upcasted it, it mods, and buffer has stride 0 on axis while having no stride 0 in the upcasted axis already - if axis in upcasted_axis or k.full_shape[axis]%upcast_amount != 0: continue - if any(st.views[-1].strides[axis] == 0 and \ - all(x != 0 for t,x in zip(k.axis_types, st.real_strides()) if t in (AxisType.UPCAST, AxisType.UNROLL)) for st in k.sts): - xb_choices.append((sum(st.views[-1].strides[axis]>0 for st in k.sts), - sum(st.views[-1].strides[axis] for st in k.sts), axis, upcast_amount)) - if xb_choices: - xb_choices = sorted(xb_choices) - if DEBUG >= 4: print(f"more upcast axis : {xb_choices}") - k.apply_opt(Opt(OptOps.UPCAST, xb_choices[0][2], xb_choices[0][3])) - upcasted_axis.add(xb_choices[0][2]) - else: break - - # if last reduce dim is small(ish), loop unroll the reduce - # NOTE: this can fail on multireduce with mismatching dimensions, this is okay - try: - upcast_size = prod(k.full_shape[a] for a in k.axes_of(AxisType.UPCAST, AxisType.UNROLL)) - if k.unrollable_dims and (upcast_size <= 4 or not k.axes_of(AxisType.UNROLL)) and (upcast_size < 64): - if (s:=k.full_shape[k.unrollable_dims[-1]]) <= 32: - k.apply_opt(Opt(OptOps.UNROLL, len(k.unrollable_dims)-1, 0)) - # if it's small, upcast a second reduce dimension too - if k.unrollable_dims and s <= 3 and k.full_shape[k.unrollable_dims[-1]] <= 3: - k.apply_opt(Opt(OptOps.UNROLL, len(k.unrollable_dims)-1, 0)) - else: - for splits in [4]: - if k.full_shape[axis:=k.unrollable_dims[-1]]%splits == 0: - k.apply_opt(Opt(OptOps.UNROLL, len(k.unrollable_dims)-1, splits)) - break - except KernelOptError: pass - - # if nothing at all is upcasted and it's easy to, do an upcast - for splits in [4]: - # TODO: somehow this never hits a reduce - if not k.upcasted and k.upcastable_dims and k.full_shape[k.upcastable_dims[-1]] % splits == 0: - k.apply_opt(Opt(OptOps.UPCAST, k.upcastable_dims[-1], splits)) - - # **** local groups **** - - if k.opts.has_local: - if NOLOCALS: - k.apply_opt(Opt(OptOps.NOLOCALS)) - else: - # prioritize making expand axes local - local_axis_ranking = [(any(st.views[-1].strides[axis] == 0 for st in k.sts), axis) for axis in k.axes_of(AxisType.GLOBAL, AxisType.LOOP)] - to_local: list[tuple[int, int]] = [] - for _, axis in sorted(local_axis_ranking, key=lambda x: (-x[0], -x[1])): - local_size = prod(sz for _, sz in to_local) - local_sz: int|None = next((x for x in ([32] * (axis == 0) + [16,8,4,3,2]) if k.full_shape[axis] % x == 0 and local_size * x <= 128), None) - if local_sz is not None: to_local.append((axis, local_sz)) - deleted_shape = 0 - for axis, local_sz in sorted(to_local[:3]): - axis = axis - deleted_shape - will_delete_shape = local_sz == k.full_shape[axis] - k.apply_opt(Opt(OptOps.LOCAL, axis, local_sz)) - if will_delete_shape: deleted_shape += 1 - - return k.applied_opts diff --git a/tinygrad_repo/tinygrad/codegen/opt/postrange.py b/tinygrad_repo/tinygrad/codegen/opt/postrange.py deleted file mode 100644 index ab8c9186b..000000000 --- a/tinygrad_repo/tinygrad/codegen/opt/postrange.py +++ /dev/null @@ -1,18 +0,0 @@ -from dataclasses import replace -from tinygrad.uop.ops import PatternMatcher, UPat, Ops, UOp, KernelInfo -from tinygrad.helpers import colored -from tinygrad.codegen.opt.kernel import axis_colors - -def rename_sink(s:UOp): - if s.arg is not None and s.arg.name != "test": return None - - # get all ranges (sorted) - rngs = sorted([u for u in s.parents if u.op is Ops.RANGE], key=lambda x: x.arg[0:-1]) - - # add name to kernel - name = "k" + colored('_', 'BLACK').join(['']+[colored(x.src[0].render(), axis_colors[x.arg[-1]]) for x in rngs]) - return s.replace(arg=KernelInfo(name=name) if s.arg is None else replace(s.arg, name=name)) - -pm_postrange_opt = PatternMatcher([ - (UPat(Ops.SINK, name="s"), rename_sink), -]) diff --git a/tinygrad_repo/tinygrad/codegen/opt/swizzler.py b/tinygrad_repo/tinygrad/codegen/opt/swizzler.py deleted file mode 100644 index 9cc356743..000000000 --- a/tinygrad_repo/tinygrad/codegen/opt/swizzler.py +++ /dev/null @@ -1,135 +0,0 @@ -from tinygrad.uop.ops import UOp, Ops, GroupOp, PatternMatcher, UPat, graph_rewrite, resolve, sint -from tinygrad.helpers import all_same, prod, unwrap, colored -from tinygrad.shape.shapetracker import ShapeTracker -from tinygrad.shape.view import View, strides_for_shape, get_contraction_with_reduce -from tinygrad.schedule.grouper import ALWAYS_CONTIGUOUS -from tinygrad.dtype import ImageDType, dtypes - -merge_views = PatternMatcher([ - # merge adjacent views - (UPat(Ops.VIEW, src=(UPat(Ops.VIEW, name="v1"),), name="v2"), lambda v1,v2: v1.replace(arg=v1.arg+v2.arg)), - # replace MovementOps with VIEW - (UPat(GroupOp.Movement, src=(UPat.var("x"),), name="mop"), lambda mop,x: x.base.view(mop.st)), - # remove NOOP views - (UPat.var("x").view(name="view"), - lambda x,view: x if x.st is not None and x.op not in GroupOp.Defines and view.st.contiguous and view.shape == x.shape else None), - (UPat(GroupOp.All-{Ops.DEFINE_GLOBAL}).view(name="view"), - lambda view: view.const_like(0) if (mask:=view.st.views[-1].mask) is not None and any((x[1]-x[0]) == 0 for x in mask) else None), - # only unmaksed VIEW on CONST replaces the ShapeTracker - (UPat(Ops.VIEW, src=(UPat((Ops.CONST, Ops.DEFINE_VAR), name="x"),), name="view"), - lambda x,view: x.replace(src=(x.src[0].replace(arg=x.st+view.st),)) if all(v.mask is None for v in (x.st+view.st).views) else None), -]) - -def reduce_push_add_ones(src:UOp, r:UOp, view:UOp): - # contiguous, expand, and the same with ones removed - if unwrap(view.st).contiguous and len(r.shape) < len(view.shape) and \ - tuple(x for x in r.shape if resolve(x != 1)) == tuple(x for x in view.shape if resolve(x != 1)): - new_shape: list[sint] = [] - new_reduce_axis = [] - if (contraction:=get_contraction_with_reduce(view.shape, r.shape, r.arg[1])) is None: return None - for i,pairs in enumerate(contraction): - new_shape_chunk = [view.shape[p] for p in pairs] - if i in r.arg[1]: - # if this is a reduce axis, we need a 1 in the view here to put it - assert len(new_shape_chunk) > 0 - new_shape += [1]*(len(pairs)-1) + [src.shape[i]] - new_reduce_axis.append(len(new_shape)-1) - else: - # otherwise, pass through the new_shape_chunk - new_shape += new_shape_chunk - ret = r.replace(src=(src.reshape(tuple(new_shape)),), arg=(r.arg[0], tuple(new_reduce_axis))+r.arg[2:]) - assert ret.shape == view.shape, f"shape mismatch on reduce_push_add_ones, {ret.shape} != {view.shape}" - return ret - return None - -view_left = merge_views+PatternMatcher([ - # view before elementwise and buffer ops - (UPat(Ops.VIEW, src=(UPat({*GroupOp.ALU, Ops.CAST, Ops.BITCAST, Ops.BIND, Ops.STORE, Ops.VALID, Ops.SINK}, name="e"),), name="view"), - lambda e,view: e.replace(src=tuple(s.view(view.st) for s in e.src))), - # if there's ones added after reduce, put this before the reduce - (UPat(Ops.VIEW, src=(UPat(Ops.REDUCE_AXIS, src=(UPat.var("src"),), name="r"),), name="view"), reduce_push_add_ones), -]) - -view_left_through_load = PatternMatcher([ - # view before load - (UPat(Ops.VIEW, src=(UPat(Ops.LOAD, name="e"),), name="view"), - lambda e,view: e.replace(src=tuple(s.view(view.st) for s in e.src))), -]) - -def apply_swizzle(u:UOp) -> UOp: return graph_rewrite(u, view_left, name="Sub View Left") - -# change reduceop axes and input ShapeTrackers, view gets replaced with a reshape. -def swizzle_reduceop(r:UOp, src:UOp, view:UOp, fuse=False): - # contiguous and same size can push to children - # if there's a reduce child, shapes match with ones removed - if unwrap(view.st).contiguous and view.size == r.size and \ - (not (len(r.arg) == 3 and r.arg[2]) or # arg[2] = True is fuse marker - tuple((i,x) for i,x in enumerate(r.shape) if resolve(x != 1)) == tuple((i,x) for i,x in enumerate(view.shape) if resolve(x != 1))): - return None - # swizzle the input - input_st = ShapeTracker.from_shape(src.shape) - tmp = input_st.permute(tuple(i for i in range(len(input_st.shape)) if i not in r.axis_arg)+r.axis_arg) - prshape = prod(rshape:=tmp.shape[-len(r.axis_arg):]) - strides = strides_for_shape(rshape) - nv = [View.create(v.shape+rshape, tuple(x*prshape for x in v.strides)+strides, - v.offset*prshape, v.mask+tuple((0,s) for s in rshape) if v.mask is not None else None) for v in unwrap(view.st).views] - new_view = tmp + ShapeTracker(tuple(nv)) - swizzled_input = apply_swizzle(src.view(new_view)) - # create a new reduceop - new_axis = tuple(range(len(view.shape), len(view.shape) + len(r.axis_arg))) - if fuse: red = UOp(Ops.REDUCE_AXIS, r.dtype, (swizzled_input.fuse(),), (r.arg[0], new_axis, True)) - else: red = UOp(Ops.REDUCE_AXIS, r.dtype, (swizzled_input,), (r.arg[0], new_axis)) - return red.reshape(view.shape) - -def reduceop_view_right(src:UOp, v:UOp, r:UOp): - assert unwrap(v.st).contiguous and v.size == src.size, f"can't compute new axis for {src.shape} -> {r.shape}" - new_axis = [i for i,(s,u) in enumerate(zip(src.shape, r.shape)) if s != u] - return src.r(r.arg[0], tuple(new_axis)).reshape(r.shape) - -def elementwise_view_right(root:UOp): - if not (swizzles:=[x for x in root.src if x.op is Ops.VIEW and x.base.op not in ALWAYS_CONTIGUOUS]): return None - assert all_same([x.base.size for x in swizzles]), f"swizzle inputs must have the same size {swizzles}" - # place view after applying the elementwise op - new_st = ShapeTracker.from_shape(swizzles[0].base.shape) - new_src = [x.base if x.base.shape==new_st.shape else apply_swizzle(x.view(new_st)) for x in root.src] - # reshape to match downstream shapes - return root.replace(src=tuple(new_src)).reshape(root.shape) - -# push VIEW to children -view_right = merge_views+PatternMatcher([ - # push a non contiguous ShapeTracker through reduceop - (UPat(Ops.VIEW, src=(UPat(Ops.REDUCE_AXIS, src=(UPat.var("src"),), name="r"),), name="view"), swizzle_reduceop), - # apply view after reduceops - (UPat(Ops.REDUCE_AXIS, src=(UPat(Ops.VIEW, src=(UPat(GroupOp.All-ALWAYS_CONTIGUOUS, name="src"),), name="v"),), name="r"), reduceop_view_right), - # apply view after elementwise ops - (UPat(GroupOp.All-{Ops.SINK, Ops.REDUCE_AXIS}, name="root"), elementwise_view_right), - # merge axes for double reduce (invert of SPLIT_REDUCEOP=1) - (UPat(Ops.REDUCE_AXIS, src=(UPat(Ops.REDUCE_AXIS, name="r1"),), name="r2"), - lambda r1,r2: r1.replace(arg=(r1.arg[0], r2.arg[1]+r1.arg[1])) if r1.arg[0] is r2.arg[0] else None), - # remove view from sink - (UPat(Ops.VIEW, name="v").sink(name="sink"), lambda v,sink: v.src[0].sink(arg=sink.arg)), -]) - -def check_load_st(glbl:UOp, view:UOp): - if glbl.arg != 0 or (st:=unwrap(view.st)).contiguous: return - # if it has a single view and it becomes contiguous when you shrink expanded axes, it's fine - if len(st.views) == 1 and st.shrink(tuple((0,1) if st == 0 else (0,s) for s,st in zip(st.shape, st.views[0].strides))).contiguous: return - # if it has a single view and it's equal when you shrink a contig, it's fine - if len(st.views) == 1 and (mask:=st.views[0].mask) is not None and ShapeTracker.from_shape(st.shape).shrink(mask) == st.shrink(mask): return - # otherwise, it's not fine - raise RuntimeError("self operand of augmented assign must be contiguous.\nhelp: consider using .contiguous():\n" - +colored(" - a += a.T\n", "red")+colored(" + a += a.T.contiguous()", "green")) - -fix_kernel_ops = view_left_through_load+PatternMatcher([ - # add view to LOAD and STORE - (UPat(Ops.DEFINE_GLOBAL, name="g").load(), lambda g: g.view(g.st).load()), - (UPat(Ops.DEFINE_GLOBAL, name="g").store(UPat.var('x')), lambda g,x: g.view(g.st).store(x)), - # VALID - (UPat(Ops.VIEW, src=(UPat.cvar(),), name="self"), - lambda self: UOp.where(UOp(Ops.VALID, dtypes.bool, (UOp(Ops.VIEW, arg=self.st),)), self.const_like(self.base.arg), 0)), - # no ImageDType after index - (UPat(GroupOp.All-{Ops.DEFINE_GLOBAL, Ops.VIEW, Ops.INDEX}, name="x"), - lambda x: x.replace(dtype=x.dtype.base) if isinstance(x.dtype, ImageDType) else None), - # if this kernel also assigns to the loaded buffer, ensure we can index it correctly - (UPat(Ops.LOAD, src=(UPat.var("glbl").view(name="view"),)), check_load_st), -]) diff --git a/tinygrad_repo/tinygrad/codegen/opt/tc.py b/tinygrad_repo/tinygrad/codegen/opt/tc.py deleted file mode 100644 index d32266c47..000000000 --- a/tinygrad_repo/tinygrad/codegen/opt/tc.py +++ /dev/null @@ -1,136 +0,0 @@ -import math, functools -from dataclasses import dataclass -from tinygrad.dtype import DType, dtypes -from tinygrad.helpers import getenv - -@dataclass(frozen=True) -class TensorCore: # D = A * B + C, A is (M x K), B is (K x N), C and D are (M x N) - dims: tuple[int,int,int] # N, M, K - threads: int # number of threads that construct the warp - elements_per_thread: tuple[int, int, int] # elements per-thread to load/store from A/B/C - dtype_in: DType # dtype for A and B - dtype_out: DType # dtype for C and D - opts: tuple[str, ...] # ordered tuple of "ux" or "lx" specifying kernel opts to perform. "ux" upcasts dim x and "lx" localizes dim x - # (local_swizzle, upcast_swizzle, reduce_swizzle) - # l is the num axis of the locals, similar for u and upcasts, r and reduces - swizzle: tuple[tuple[tuple[str, ...], tuple[str, ...], tuple[str, ...]], tuple[tuple[str, ...], tuple[str, ...], tuple[str, ...]]] - @functools.cache # pylint: disable=method-cache-max-size-none - def _remaps(self) -> list[dict[str, str]]: - local_axes, upcast_axes, reduce_axes = len(self.get_local_axes()), len(self.get_upcast_axes()), len(self.get_reduce_axes()) - fwd_st = [f"l{i}" for i in range(local_axes)] + [f"u{i}" for i in range(upcast_axes)] + [f"r{i}" for i in range(reduce_axes)] - return [dict(zip(fwd_st, sum(s, ()))) for s in self.swizzle] - def permutes_for_shape_str(self, shape_str:list[str]) -> tuple[tuple[int, ...], tuple[int, ...]]: - ret = [[shape_str.index(remap[ss]) if ss in remap else i for i,ss in enumerate(shape_str)] for remap in self._remaps()] - return tuple(ret[0]), tuple(ret[1]) - @functools.cache # pylint: disable=method-cache-max-size-none - def base_shape_str(self) -> list[str]: - ret = [] - cnt = {'u': 0, 'l': 0} - for opt in self.opts: - ret.append(f"{opt[0]}{cnt[opt[0]]}") - cnt[opt[0]] += 1 - # assumes you do the UNROLL after the opts - return ret + [f"r{i}" for i in range(len(self.get_reduce_axes()))] - def get_reduce_axes(self): return [(i, 2) for i in range(int(math.log2(self.dims[2])))] - def get_upcast_axes(self): return [opt for opt in self.opts if opt[0] == "u"] - def get_local_axes(self): return [opt for opt in self.opts if opt[0] == "l"] - def base_upcast_axes(self): - # this is defined in the swizzle. first we use the upcast axes, then the reduce - return ([f"r{i}" for i in range(len(self.get_reduce_axes()))] + [f"u{i}" for i in range(len(self.get_upcast_axes()))])[::-1] - def __str__(self): return "_".join(["WMMA"] + list(map(str, self.dims)) + [self.dtype_in.name, self.dtype_out.name]) - def __post_init__(self): - # all axes have size 2, is the order - local_axes, upcast_axes, reduce_axes = len(self.get_local_axes()), len(self.get_upcast_axes()), len(self.get_reduce_axes()) - assert self.dims[0] * self.dims[1] == 2**(local_axes + upcast_axes), \ - f"N({self.dims[0]}) x M({self.dims[1]}) != local({2**local_axes}) x upcast({2**upcast_axes}) with opts({self.opts})" - assert 2**local_axes == self.threads, f"{self.threads} threads construct the warp but found {2**local_axes} in {self.opts}" - assert 2**upcast_axes == self.elements_per_thread[2], \ - f"{self.elements_per_thread[2]} elements from C are processed per thread but found {2**upcast_axes} in {self.opts}" - # check dims match opts - assert self.dims[0] == 2**len(gd:=[x for x in self.opts if x[1] == '0']), f"opts wrong on dims[0], {self.dims[0]} vs {gd}" - assert self.dims[1] == 2**len(gd:=[x for x in self.opts if x[1] == '1']), f"opts wrong on dims[1], {self.dims[1]} vs {gd}" - # NOTE: the K opts is implictly set by the dim - # check swizzle - assert len(self.swizzle[0]) == 3 and len(self.swizzle[1]) == 3, "swizzle has wrong part count" - assert len(self.swizzle[0][0]) == len(self.swizzle[1][0]) == local_axes, "local swizzle size is wrong" - assert len(self.swizzle[0][1]) == len(self.swizzle[1][1]) == upcast_axes, "upcast swizzle size is wrong" - assert len(self.swizzle[0][2]) == len(self.swizzle[1][2]) == reduce_axes, "reduce swizzle size is wrong" - assert all(len(s) == local_axes+upcast_axes+reduce_axes for s in self._remaps()), "remaps are the wrong size" - # check elements_per_thread - un, ln = 0, 0 - zero_stride_0 = [] - zero_stride_1 = [] - for o in self.opts: - if o[1] == '0': zero_stride_0.append(o[0] + str(un if o[0] == 'u' else ln)) - if o[1] == '1': zero_stride_1.append(o[0] + str(un if o[0] == 'u' else ln)) - if o[0] == 'u': un += 1 - if o[0] == 'l': ln += 1 - # NOTE: all the zero_stride dims can be placed in any order in the swizzle - upcasted_0 = [x for x in (self.swizzle[0][1] + self.swizzle[0][2]) if x not in zero_stride_0 and x[0] != 'l'] - upcasted_1 = [x for x in (self.swizzle[1][1] + self.swizzle[1][2]) if x not in zero_stride_1 and x[0] != 'l'] - assert 2**len(upcasted_0) == self.elements_per_thread[0], f"mismatch in elements_per_thread[0], {upcasted_0} vs {self.elements_per_thread[0]}" - assert 2**len(upcasted_1) == self.elements_per_thread[1], f"mismatch in elements_per_thread[1], {upcasted_1} vs {self.elements_per_thread[1]}" - -# ***** NVIDIA ***** - -cuda_tc_opts = ("u0","l0","l0","l1","l1","l1","u1") # shared by all shapes with M=16 N=8 - -# https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-multiply-accumulate-instructions -cuda_81616 = [TensorCore(dims=(8,16,16), threads=32, elements_per_thread=(8,4,4), dtype_in=di, dtype_out=do, opts=cuda_tc_opts, - swizzle=((('r1', 'r2', 'l2', 'l3', 'l4'), ('u1', 'r3'), ('l0', 'l1', 'u0', 'r0')), - (('r1', 'r2', 'u0', 'l0', 'l1'), ('r0', 'r3'), ('l2', 'l3', 'l4', 'u1')))) - for di,do in [(dtypes.half,dtypes.float), (dtypes.bfloat16,dtypes.float), (dtypes.half,dtypes.half)]] -cuda_8168_f16 = [TensorCore(dims=(8,16,8), threads=32, elements_per_thread=(4,2,4), dtype_in=di, dtype_out=do, opts=cuda_tc_opts, - swizzle=((('r1', 'r2', 'l2', 'l3', 'l4'), ('r0', 'u1'), ('l0', 'l1', 'u0')), - (('r1', 'r2', 'u0', 'l0', 'l1'), ('u1', 'r0'), ('l2', 'l3', 'l4')))) - for di,do in [(dtypes.half,dtypes.float), (dtypes.half,dtypes.half)]] -cuda_8168_tf32 = [TensorCore(dims=(8,16,8), threads=32, elements_per_thread=(4,2,4), dtype_in=dtypes.float, dtype_out=dtypes.float, opts=cuda_tc_opts, - swizzle=((('r0', 'r1', 'l2', 'l3', 'l4'), ('u1', 'r2'), ('l0', 'l1', 'u0')), - (('r0', 'r1', 'u0', 'l0', 'l1'), ('u1', 'r2'), ('l2', 'l3', 'l4'))))] -cuda_sm80: list[TensorCore] = cuda_81616 + cuda_8168_f16 -if getenv("ALLOW_TF32", 0): cuda_sm80 += cuda_8168_tf32 -cuda_sm75: list[TensorCore] = cuda_8168_f16 - -# ***** AMD ***** - -# https://gpuopen.com/learn/wmma_on_rdna3/ -amd_rdna3 = [TensorCore(dims=(16,16,16), threads=32, elements_per_thread=(16,16,8), dtype_in=di, dtype_out=do, - opts=("l0","l0","l0","l0","l1","u1","u1","u1"), - swizzle=((('l4', 'u0', 'u1', 'u2', 'l0'), ('r1', 'r2', 'r3'), ('l1', 'l2', 'l3', 'r0')), - (('l0', 'l1', 'l2', 'l3', 'l4'), ('r1', 'r2', 'r3'), ('u0', 'u1', 'u2', 'r0')))) - for di,do in [(dtypes.half,dtypes.float),(dtypes.half,dtypes.half),(dtypes.bfloat16,dtypes.float)]] -amd_rdna4 = [TensorCore(dims=(16,16,16), threads=32, elements_per_thread=(8,8,8), dtype_in=di, dtype_out=do, - opts=("l0","l0","l0","l0","u1","u1","u1","l1"), - swizzle=((('u0', 'u1', 'u2', 'l4', 'r2'), ('r0', 'r1', 'r3'), ('l0', 'l1', 'l2', 'l3')), - (('l0', 'l1', 'l2', 'l3', 'r2'), ('r0', 'r1', 'r3'), ('l4', 'u0', 'u1', 'u2')))) - for di,do in [(dtypes.half,dtypes.float),(dtypes.half,dtypes.half),(dtypes.bfloat16,dtypes.float),(dtypes.bfloat16,dtypes.bfloat16)]] - -# https://gpuopen.com/learn/amd-lab-notes/amd-lab-notes-matrix-cores-readme -amd_cdna = [TensorCore(dims=(16,16,16), threads=64, elements_per_thread=(4,4,4), dtype_in=di, dtype_out=do, - opts=("l0","l0","l0","l0","u1","u1","l1","l1"), - swizzle=((('u0', 'u1', 'l4', 'l5', 'r2', 'r3'), ('r0', 'r1'), ('l0', 'l1', 'l2', 'l3')), - (('l0', 'l1', 'l2', 'l3', 'r2', 'r3'), ('r0', 'r1'), ('l4', 'l5', 'u0', 'u1')))) - for di,do in [(dtypes.half,dtypes.float),(dtypes.bfloat16,dtypes.float)]] - -# ***** Apple Metal ***** - -metal = [TensorCore(dims=(8,8,8), threads=32, elements_per_thread=(2,2,2), dtype_in=di, dtype_out=do, - opts=("u0","l0","l1","l1","l0","l1"), - swizzle=((('r1', 'l1', 'l2', 'r2', 'l4'), ('r0',), ('u0', 'l0', 'l3')), - (('l0', 'r0', 'r1', 'l3', 'r2'), ('u0',), ('l1', 'l2', 'l4')))) - for di,do in [(dtypes.float,dtypes.float),(dtypes.half,dtypes.float), - (dtypes.half,dtypes.half),(dtypes.bfloat16,dtypes.float),(dtypes.bfloat16,dtypes.bfloat16)]] - -# ***** Apple AMX ***** - -amx = [TensorCore(dims=(sz,sz,1), threads=1, elements_per_thread=(sz,sz,sz*sz), dtype_in=dt, dtype_out=dt, - swizzle=(((), ('u0', 'u1', 'u2', 'u3', 'u4', 'u5', 'u6', 'u7'), ()), - ((), ('u4', 'u5', 'u6', 'u7', 'u0', 'u1', 'u2', 'u3'), ())), - opts=("u0","u0","u0","u0","u1","u1","u1","u1")) for dt,sz in [(dt, 64 // dt.itemsize) for dt in [dtypes.float]]] - -# ***** Intel **** - -intel = [TensorCore(dims=(8,8,16), threads=8, elements_per_thread=(16,16,8), dtype_in=dtypes.half, dtype_out=dtypes.float, - opts=("l0","l0","l0","u1","u1","u1"), - swizzle=((('r1', 'r2', 'r3'), ('u0', 'u1', 'u2'), ('l0', 'l1', 'l2', 'r0')), - (('l0', 'l1', 'l2'), ('r1', 'r2', 'r3'), ('u0', 'u1', 'u2', 'r0'))))] diff --git a/tinygrad_repo/tinygrad/device.py b/tinygrad_repo/tinygrad/device.py index 9a021c6a3..61fd207d4 100644 --- a/tinygrad_repo/tinygrad/device.py +++ b/tinygrad_repo/tinygrad/device.py @@ -1,10 +1,10 @@ from __future__ import annotations from dataclasses import dataclass, replace from collections import defaultdict -from typing import Any, Generic, TypeVar, Iterator -import importlib, inspect, functools, pathlib, os, platform, contextlib, sys, re, atexit, pickle, decimal -from tinygrad.helpers import CI, OSX, LRU, getenv, diskcache_get, diskcache_put, DEBUG, GlobalCounters, flat_mv, PROFILE, temp, colored, \ - Context, DISABLE_COMPILER_CACHE, ALLOW_DEVICE_USAGE, MAX_BUFFER_SIZE, cpu_events, ProfileEvent, ProfilePointEvent, dedup +from typing import Optional, Any, Generic, TypeVar, Iterator, Generator +import importlib, inspect, functools, pathlib, os, ctypes, ctypes.util, platform, contextlib, sys, re, atexit, pickle, decimal, time +from tinygrad.helpers import CI, OSX, LRU, getenv, diskcache_get, diskcache_put, DEBUG, GlobalCounters, flat_mv, from_mv, PROFILE, temp, mv_address, \ + cpu_time_execution, colored, Context, round_up, DISABLE_COMPILER_CACHE, ALLOW_DEVICE_USAGE from tinygrad.dtype import DType, ImageDType, PtrDType, dtypes, _to_np_dtype from tinygrad.renderer import Renderer @@ -18,7 +18,7 @@ class _Device: @functools.cache # this class is a singleton, pylint: disable=method-cache-max-size-none def _canonicalize(self, device:str) -> str: return re.sub(r":0$", "", (d:=device.split(":", 1)[0].upper()) + device[len(d):]) # NOTE: you can't cache canonicalize in case Device.DEFAULT changes - def canonicalize(self, device:str|None) -> str: return self._canonicalize(device if device is not None else Device.DEFAULT) + def canonicalize(self, device:Optional[str]) -> str: return self._canonicalize(device if device is not None else Device.DEFAULT) def __getitem__(self, ix:str) -> Compiled: return self.__get_canonicalized_item(self.canonicalize(ix)) @functools.cache # this class is a singleton, pylint: disable=method-cache-max-size-none def __get_canonicalized_item(self, ix:str) -> Compiled: @@ -37,8 +37,7 @@ class _Device: with contextlib.suppress(Exception): yield self[device].device @functools.cached_property def DEFAULT(self) -> str: - dev = [dev] if (dev:=getenv("DEV", "").upper()) else [] - from_env = dedup(dev + [d for d in self._devices if d not in ["DISK", "NPY"] and getenv(d) == 1]) + from_env = [d for d in self._devices if d not in ["DISK", "NPY"] and getenv(d) == 1] assert len(from_env) < 2, f"multiple devices set in env: {from_env}" if len(from_env) == 1: return from_env[0] try: @@ -51,10 +50,15 @@ atexit.register(lambda: [Device[dn].finalize() for dn in Device._opened_devices] # **************** Profile **************** +class ProfileEvent: pass + @dataclass(frozen=True) class ProfileDeviceEvent(ProfileEvent): device:str; comp_tdiff:decimal.Decimal=decimal.Decimal(0); copy_tdiff:decimal.Decimal=decimal.Decimal(0) # noqa: E702 +@dataclass(frozen=True) +class ProfileRangeEvent(ProfileEvent): device:str; name:str; st:decimal.Decimal; en:decimal.Decimal; is_copy:bool # noqa: E702 + @dataclass(frozen=True) class ProfileProgramEvent(ProfileEvent): device:str; name:str; lib:bytes|None; base:int|None # noqa: E702 @@ -64,17 +68,28 @@ class ProfileGraphEntry: device:str; name:str; st_id:int; en_id:int; is_copy:boo @dataclass(frozen=True) class ProfileGraphEvent(ProfileEvent): ents:list[ProfileGraphEntry]; deps:list[list[int]]; sigs:list[decimal.Decimal] # noqa: E702 +@dataclass +class ProfileResult: st:Optional[int]=None; en:Optional[int]=None # noqa: E702 + +@contextlib.contextmanager +def cpu_profile(name, device="CPU", is_copy=False, display=True) -> Generator[ProfileResult, None, None]: + yield (res:=ProfileResult(st:=time.perf_counter_ns())) + res.en = en = time.perf_counter_ns() + if PROFILE and display: + Compiled.profile_events += [ProfileRangeEvent(device, name, decimal.Decimal(st) / 1000, decimal.Decimal(en) / 1000, is_copy=is_copy)] + # **************** Buffer + Allocators **************** + @dataclass(frozen=True, eq=True) class BufferSpec: # TODO: move device, size, dtype here? - image: ImageDType|None = None + image: Optional[ImageDType] = None uncached: bool = False cpu_access: bool = False host: bool = False nolru: bool = False - external_ptr: int|None = None + external_ptr: Optional[int] = None class MultiBuffer: def __init__(self, device:tuple[str, ...], size:int, dtype:DType): @@ -90,9 +105,8 @@ class MultiBuffer: def __repr__(self): return f"" class Buffer: - profile_events:list[ProfileEvent] = [] - def __init__(self, device:str, size:int, dtype:DType, opaque:Any=None, options:BufferSpec|None=None, initial_value:bytes|None=None, - uop_refcount=0, base:Buffer|None=None, offset:int=0, preallocate=False): + def __init__(self, device:str, size:int, dtype:DType, opaque:Any=None, options:Optional[BufferSpec]=None, initial_value:Optional[bytes]=None, + uop_refcount=0, base:Optional[Buffer]=None, offset:int=0, preallocate=False): if isinstance(dtype, ImageDType): options = BufferSpec(image=dtype) # TODO: image hack shouldn't be here. where should it be? else: assert isinstance(dtype, DType) and not isinstance(dtype, PtrDType) self.device, self.size, self.dtype, self.options, self.offset, self.allocated_views = device, size, dtype, options, offset, 0 @@ -124,7 +138,7 @@ class Buffer: def allocate(self, opaque=None, external_ptr=None) -> Buffer: assert not self.is_initialized(), "can't allocate already allocated buffer" if DEBUG >= 7: print(f"buffer: allocate {self.nbytes} bytes on {self.device}") - if MAX_BUFFER_SIZE > 0 and self.size > MAX_BUFFER_SIZE: raise RuntimeError(f"buffer of size {self.size/1e6:.2f}M is too large") + if (mbs:=getenv("MAX_BUFFER_SIZE", 0)) > 0 and self.size > mbs: raise RuntimeError(f"buffer of size {self.size/1e6:.2f}M is too large") self.allocator:Allocator = Device[self.device].allocator if external_ptr is not None: self.options = replace(self.options, external_ptr=external_ptr) if self.options else BufferSpec(external_ptr=external_ptr) @@ -136,16 +150,12 @@ class Buffer: else: self._buf = opaque if opaque is not None else self.allocator.alloc(self.nbytes, self.options) if not self.device.startswith("DISK"): GlobalCounters.mem_used += self.nbytes - if PROFILE: - self._prof_num = num = len(Buffer.profile_events) - Buffer.profile_events.append(ProfilePointEvent(self.device, "alloc", num, {"dtype":self.dtype, "sz":self.size})) return self def deallocate(self): assert hasattr(self, '_buf'), "buffer must be allocated to deallocate" if DEBUG is not None and DEBUG >= 7: print(f"buffer: deallocate {self.nbytes} bytes on {self.device}") if self._base is None and (self.options is None or self.options.external_ptr is None): if GlobalCounters is not None and not self.device.startswith("DISK"): GlobalCounters.mem_used -= self.nbytes - if PROFILE: Buffer.profile_events.append(ProfilePointEvent(self.device, "free", self._prof_num)) self.allocator.free(self._buf, self.nbytes, self.options) elif self._base is not None: self._base.allocated_views -= 1 del self._buf @@ -164,9 +174,6 @@ class Buffer: def __repr__(self): return f"" - def as_dmaref(self) -> DMARef: - assert hasattr(self.allocator, "_as_dmaref"), f"Device {self.device} doesn't support DMA" - return self.allocator._as_dmaref(self._buf) def as_buffer(self, allow_zero_copy=False, force_zero_copy=False) -> memoryview: # zero copy with as_buffer (disabled by default due to use after free) if (force_zero_copy or allow_zero_copy) and hasattr(self.allocator, '_as_buffer') and (self.options is None or self.options.image is None): @@ -198,19 +205,6 @@ class Buffer: if self._base is not None: return Buffer(self.device, size, dtype, base=self._base, offset=self.offset+offset) return Buffer(self.device, size, dtype, base=self, offset=offset) -@dataclass(frozen=True) -class DMACPURef: - addr: int - size: int - -@dataclass(frozen=True) -class DMAFdRef: - fd: int - offset: int - size: int - -DMARef = DMACPURef|DMAFdRef - DeviceType = TypeVar('DeviceType', bound='Compiled') # TODO: size, dest, src are the same type. can we enforce this? @@ -218,12 +212,11 @@ class Allocator(Generic[DeviceType]): def __init__(self, dev:DeviceType): self.dev: DeviceType = dev self.default_buffer_spec: BufferSpec = BufferSpec() - self.supports_copy_from_disk: bool = True # overridden in LRUAllocator - def alloc(self, size:int, options:BufferSpec|None=None): + def alloc(self, size:int, options:Optional[BufferSpec]=None): assert size > 0, f"alloc size must be positive, getting {size}" return self._alloc(size, options if options is not None else self.default_buffer_spec) - def free(self, opaque, size:int, options:BufferSpec|None=None): + def free(self, opaque, size:int, options:Optional[BufferSpec]=None): self._free(opaque, options if options is not None else self.default_buffer_spec) # implemented by the runtime @@ -241,9 +234,9 @@ class LRUAllocator(Allocator, Generic[DeviceType]): It ensures that buffers are not freed until it is absolutely necessary, optimizing performance. """ def __init__(self, dev:DeviceType): - self.cache: dict[tuple[int, BufferSpec|None], Any] = defaultdict(list) + self.cache: dict[tuple[int, Optional[BufferSpec]], Any] = defaultdict(list) super().__init__(dev) - def alloc(self, size:int, options:BufferSpec|None=None): + def alloc(self, size:int, options:Optional[BufferSpec]=None): if len(c := self.cache[(size, options)]): return c.pop() try: return super().alloc(size, options) except (RuntimeError, MemoryError): @@ -253,16 +246,83 @@ class LRUAllocator(Allocator, Generic[DeviceType]): for (sz,options),opaques in self.cache.items(): for opaque in opaques: super().free(opaque, sz, options) opaques.clear() - def free(self, opaque:Any, size:int, options:BufferSpec|None=None): + def free(self, opaque:Any, size:int, options:Optional[BufferSpec]=None): if LRU and (options is None or not options.nolru): self.cache[(size, options)].append(opaque) else: super().free(opaque, size, options) +class _MallocAllocator(LRUAllocator['Compiled']): + def _alloc(self, size:int, options:BufferSpec): + # must be aligned to 0x20 for 256-bit ymm registers + # TODO: investigate if this is the cause of nondeterminism in speed + alignment = 0x1000 if size >= 0x1000 else 0x20 + return (ctypes.c_uint8 * size).from_address(options.external_ptr) if options.external_ptr else self._alloc_aligned(size, alignment) + def _alloc_aligned(self, size:int, alignment:int): + buffer = (ctypes.c_uint8 * (size + alignment))() + offset = round_up(ctypes.addressof(buffer), alignment) - ctypes.addressof(buffer) + return (ctypes.c_uint8 * size).from_buffer(buffer, offset) + def _as_buffer(self, src) -> memoryview: return flat_mv(memoryview(src)) + def _copyin(self, dest, src:memoryview): ctypes.memmove(dest, from_mv(src), len(src)) + def _copyout(self, dest:memoryview, src): ctypes.memmove(from_mv(dest), src, len(dest)) + def _offset(self, buf, size:int, offset:int): return from_mv(self._as_buffer(buf)[offset:offset+size]) + +MallocAllocator = _MallocAllocator(None) # type: ignore + +# NOTE: MAP_JIT is added to mmap module in python 3.13 +MAP_JIT = 0x0800 + +# CPUProgram is a jit/shellcode program that can be just mmapped and jumped to +class CPUProgram: + rt_lib = ctypes.CDLL(ctypes.util.find_library('System' if OSX else 'kernel32') if OSX or sys.platform == "win32" else 'libgcc_s.so.1') + + def __init__(self, name:str, lib:bytes): + if sys.platform == "win32": + PAGE_EXECUTE_READWRITE = 0x40 + MEM_COMMIT = 0x1000 + MEM_RESERVE = 0x2000 + ctypes.windll.kernel32.VirtualAlloc.restype = ctypes.c_void_p + self.mem = ctypes.windll.kernel32.VirtualAlloc(ctypes.c_void_p(0), ctypes.c_size_t(len(lib)), MEM_COMMIT | MEM_RESERVE, PAGE_EXECUTE_READWRITE) + ctypes.memmove(self.mem, lib, len(lib)) + ctypes.windll.kernel32.GetCurrentProcess.restype = ctypes.c_void_p + proc = ctypes.windll.kernel32.GetCurrentProcess() + ctypes.windll.kernel32.FlushInstructionCache(ctypes.c_void_p(proc), ctypes.c_void_p(self.mem), ctypes.c_size_t(len(lib))) + self.fxn = ctypes.CFUNCTYPE(None)(self.mem) + else: + from mmap import mmap, PROT_READ, PROT_WRITE, PROT_EXEC, MAP_ANON, MAP_PRIVATE + # On apple silicon with SPRR enabled (it always is in macos) RWX pages are unrepresentable: https://blog.svenpeter.dev/posts/m1_sprr_gxf/ + # MAP_JIT allows us to easily flip pages from RW- to R-X and vice versa. It is a noop on intel cpus. (man pthread_jit_write_protect_np) + self.mem = mmap(-1, len(lib), MAP_ANON | MAP_PRIVATE | (MAP_JIT if OSX else 0), PROT_READ | PROT_WRITE | PROT_EXEC) + + if OSX: CPUProgram.rt_lib.pthread_jit_write_protect_np(False) + self.mem.write(lib) + if OSX: CPUProgram.rt_lib.pthread_jit_write_protect_np(True) + + # __clear_cache isn't a normal libc function, but a compiler support routine found in libgcc_s for gcc and compiler-rt for clang. + # libgcc_s comes as shared library but compiler-rt is only a bunch of static library archives which we can't directly load, but fortunately + # it somehow found its way into libSystem on macos (likely because it used __builtin_clear_cache) and libgcc_s is ~always present on linux + # Using ["name"] instead of .name because otherwise name is getting mangled: https://docs.python.org/3.12/reference/expressions.html#index-5 + CPUProgram.rt_lib["__clear_cache"](ctypes.c_void_p(mv_address(self.mem)), ctypes.c_void_p(mv_address(self.mem) + len(lib))) + + self.fxn = ctypes.CFUNCTYPE(None)(mv_address(self.mem)) + + def __call__(self, *bufs, vals=(), wait=False): + args = list(bufs) + list(vals) + # NOTE: replace this by --target={host's triple}-elf in clang args once we only support macos sequoia and later. + # Apple relaxes abi requirement for stack arguments to always be at least 8 byte aligned on arm64 + # https://developer.apple.com/documentation/xcode/writing-arm64-code-for-apple-platforms + # This hack is required because clang/llvm bug doesn't allow us to just use {host's triple}+'-elf' (relocation failures) + # The bug was fixed in https://github.com/llvm/llvm-project/commit/454cc36630296262cdb6360b60f90a64a97f7f1a but was only backported to xcode 16+ + if platform.machine() == "arm64" and OSX: args = args[:8] + [ctypes.c_int64(a) if isinstance(a, int) else a for a in args[8:]] + return cpu_time_execution(lambda: self.fxn(*args), enable=wait) + + def __del__(self): + if sys.platform == 'win32': ctypes.windll.kernel32.VirtualFree(ctypes.c_void_p(self.mem), ctypes.c_size_t(0), 0x8000) #0x8000 - MEM_RELEASE + # **************** for Compiled Devices **************** class CompileError(Exception): pass class Compiler: - def __init__(self, cachekey:str|None=None): self.cachekey = None if DISABLE_COMPILER_CACHE else cachekey + def __init__(self, cachekey:Optional[str]=None): self.cachekey = None if DISABLE_COMPILER_CACHE else cachekey def compile(self, src:str) -> bytes: return src.encode() # NOTE: empty compiler is the default def compile_cached(self, src:str) -> bytes: if self.cachekey is None or (lib := diskcache_get(self.cachekey, src)) is None: @@ -275,9 +335,9 @@ class Compiler: class Compiled: profile_events:list[ProfileEvent] = [ProfileDeviceEvent("CPU")] # NOTE: CPU is the default device. - def __init__(self, device:str, allocator:Allocator, renderer:Renderer|None, compiler:Compiler|None, runtime, graph=None, group_id=None): + def __init__(self, device:str, allocator:Allocator, renderer:Optional[Renderer], compiler:Optional[Compiler], runtime, graph=None): self.device, self.allocator, self.compiler, self.runtime, self.graph = device, allocator, compiler or Compiler(), runtime, graph - self.renderer, self.group_id = renderer or Renderer(), group_id + self.renderer = renderer or Renderer() def synchronize(self): """ Synchronize all pending operations on the device. @@ -297,13 +357,13 @@ class Compiled: # override this in your device implementation # TODO: move this to each Device -def is_dtype_supported(dtype:DType, device:str|None=None) -> bool: +def is_dtype_supported(dtype:DType, device:Optional[str]=None) -> bool: if device is None: device = Device.DEFAULT if dtype == dtypes.bfloat16: if device == "METAL": return not CI if device in {"CUDA", "NV"}: return not CI and not getenv("PTX") if device in {"CPU", "LLVM"}: return not CI and platform.machine() in {"arm", "arm64", "aarch64", "x86_64", "amd64"} - return device in {"AMD", "PYTHON"} + return device == "AMD" if dtype in dtypes.fp8s: # not supported yet - in progress return False @@ -328,11 +388,11 @@ if PROFILE: for dev in devs: dev.synchronize() for dev in devs: dev._at_profile_finalize() - with open(fn:=temp("profile.pkl", append_user=True), "wb") as f: pickle.dump(cpu_events+Compiled.profile_events+Buffer.profile_events, f) + with open(fn:=temp("profile.pkl", append_user=True), "wb") as f: pickle.dump(Compiled.profile_events, f) if not getenv("SQTT", 0): from tinygrad.uop.ops import launch_viz - launch_viz(PROFILE, fn) + launch_viz("PROFILE", fn) if __name__ == "__main__": for device in ALL_DEVICES: diff --git a/tinygrad_repo/tinygrad/dtype.py b/tinygrad_repo/tinygrad/dtype.py index 2e2716c42..d7fe21aa6 100644 --- a/tinygrad_repo/tinygrad/dtype.py +++ b/tinygrad_repo/tinygrad/dtype.py @@ -1,11 +1,10 @@ from __future__ import annotations -from typing import Final, ClassVar, Callable, Literal +from typing import Final, Optional, ClassVar, Union, Callable, Literal import math, struct, ctypes, functools from dataclasses import dataclass, fields from tinygrad.helpers import getenv, prod -from enum import Enum, auto -ConstType = float|int|bool +ConstType = Union[float, int, bool] FmtStr = Literal['?', 'b', 'B', 'h', 'H', 'i', 'I', 'q', 'Q', 'e', 'f', 'd'] @@ -17,18 +16,16 @@ class DTypeMetaClass(type): DTypeMetaClass.dcache[args] = ret = super().__call__(*args) return ret -class AddrSpace(Enum): GLOBAL = auto(); LOCAL = auto(); REG = auto() # noqa: E702 - @dataclass(frozen=True, eq=False) class DType(metaclass=DTypeMetaClass): priority: int # this determines when things get upcasted itemsize: int name: str - fmt: FmtStr|None + fmt: Optional[FmtStr] count: int - _scalar: DType|None + _scalar: Optional[DType] @staticmethod - def new(priority:int, itemsize:int, name:str, fmt:FmtStr|None): return DType(priority, itemsize, name, fmt, 1, None) + def new(priority:int, itemsize:int, name:str, fmt:Optional[FmtStr]): return DType(priority, itemsize, name, fmt, 1, None) def __reduce__(self): return type(self), tuple(getattr(self, f.name) for f in fields(self)) def __repr__(self): return f"dtypes.{INVERSE_DTYPES_DICT[self.scalar().name]}"+(f".vec({self.count})" if self.count > 1 else "") def __lt__(self, o:DType): return (self.priority, self.itemsize, self.name, self.fmt, self.count) < (o.priority, o.itemsize, o.name, o.fmt, o.count) @@ -41,8 +38,8 @@ class DType(metaclass=DTypeMetaClass): assert self.count == 1, f"can't vectorize {self} with size {sz}" if sz == 1 or self == dtypes.void: return self # void doesn't vectorize, and sz=1 is scalar return DType(self.priority, self.itemsize*sz, f"{INVERSE_DTYPES_DICT[self.name]}{sz}", None, sz, self) - def ptr(self, size=-1, addrspace=AddrSpace.GLOBAL) -> PtrDType: - return PtrDType(self.priority, self.itemsize, self.name, self.fmt, self.count, None, self, addrspace, 1, size) + def ptr(self, size=-1, local=False) -> PtrDType: + return PtrDType(self.priority, self.itemsize, self.name, self.fmt, self.count, None, self, local, 1, size) def scalar(self) -> DType: return self._scalar if self._scalar is not None else self def nbytes(self): raise RuntimeError("only ptr types have nbytes") @property @@ -53,7 +50,7 @@ class DType(metaclass=DTypeMetaClass): @dataclass(frozen=True, eq=False) class PtrDType(DType): _base: DType - addrspace: AddrSpace + local: bool v: int size: int = -1 # -1 is unlimited size @property @@ -63,23 +60,22 @@ class PtrDType(DType): assert self.v == 1, f"can't vectorize ptr {self} with size {sz}" if sz == 1: return self # sz=1 is a scalar if isinstance(self, ImageDType): - return ImageDType(self.priority, self.itemsize, self.name, self.fmt, self.count, self, self._base, self.addrspace, sz, self.size, self.shape) - return type(self)(self.priority, self.itemsize, self.name, self.fmt, self.count, self, self._base, self.addrspace, sz, self.size) - def ptr(self, size=-1, addrspace=AddrSpace.GLOBAL): raise RuntimeError("can't make a pointer from a pointer") + return ImageDType(self.priority, self.itemsize, self.name, self.fmt, self.count, self, self._base, self.local, sz, self.size, self.shape) + return type(self)(self.priority, self.itemsize, self.name, self.fmt, self.count, self, self._base, self.local, sz, self.size) + def ptr(self, size=-1, local=False): raise RuntimeError("can't make a pointer from a pointer") def nbytes(self) -> int: if self.size == -1: return 0 # TODO: this should be an exception return self.size*self.itemsize @property def vcount(self): return self.v def __repr__(self): - return f"{self.base.__repr__()}.ptr({self.size}{', '+str(self.addrspace) if self.addrspace != AddrSpace.GLOBAL else ''})" + \ - (f'.vec({self.v})' if self.v != 1 else '') + return f"{self.base.__repr__()}.ptr({self.size}{', local=True' if self.local else ''})" + (f'.vec({self.v})' if self.v != 1 else '') @dataclass(frozen=True, eq=False) class ImageDType(PtrDType): shape: tuple[int, ...] = () # shape of the Image - def ptr(self, size=-1, addrspace=AddrSpace.GLOBAL) -> PtrDType: - assert addrspace == AddrSpace.GLOBAL, "images can't be local" + def ptr(self, size=-1, local=False) -> PtrDType: + assert not local, "images can't be local" return self def __repr__(self): return f"dtypes.{self.name}({self.shape})" + (f'.vec({self.v})' if self.v != 1 else '') @@ -108,16 +104,17 @@ class dtypes: if isinstance(val, tuple): assert len(val) == dtype.count, f"mismatch {val} {dtype}" return tuple(dtypes.as_const(x, dtype) for x in val) + # TODO: should truncate here return int(val) if dtypes.is_int(dtype) else float(val) if dtypes.is_float(dtype) else bool(val) @staticmethod @functools.cache def min(dtype:DType): - if dtypes.is_int(dtype): return 0 if dtypes.is_unsigned(dtype) else -2**(dtype.scalar().itemsize*8-1) + if dtypes.is_int(dtype): return 0 if dtypes.is_unsigned(dtype) else -2**(dtype.itemsize*8-1) return -float("inf") if dtypes.is_float(dtype) else False @staticmethod @functools.cache def max(dtype:DType): - if dtypes.is_int(dtype): return 2**(dtype.scalar().itemsize*8)-1+dtypes.min(dtype) + if dtypes.is_int(dtype): return 2**(dtype.itemsize*8)-1+dtypes.min(dtype) return float("inf") if dtypes.is_float(dtype) else True @staticmethod def finfo(dtype:DType) -> tuple[int, int]: @@ -152,9 +149,9 @@ class dtypes: # NOTE: these are image dtypes @staticmethod - def imageh(shp): return ImageDType(100, 2, "imageh", 'e', 1, None, dtypes.float32, AddrSpace.GLOBAL, 1, prod(shp), shp) + def imageh(shp): return ImageDType(100, 2, "imageh", 'e', 1, None, dtypes.float32, False, 1, prod(shp), shp) @staticmethod - def imagef(shp): return ImageDType(100, 4, "imagef", 'f', 1, None, dtypes.float32, AddrSpace.GLOBAL, 1, prod(shp), shp) + def imagef(shp): return ImageDType(100, 4, "imagef", 'f', 1, None, dtypes.float32, False, 1, prod(shp), shp) default_float: ClassVar[DType] = float32 default_int: ClassVar[DType] = int32 @@ -170,7 +167,7 @@ if (env_default_float := getenv("DEFAULT_FLOAT", "")): dtypes.default_float = getattr(dtypes, env_default_float.lower()) assert dtypes.is_float(dtypes.default_float), f"{env_default_float} is not a float dtype" -DTypeLike = str|DType +DTypeLike = Union[str, DType] def to_dtype(dtype:DTypeLike) -> DType: return dtype if isinstance(dtype, DType) else getattr(dtypes, dtype.lower()) # https://jax.readthedocs.io/en/latest/jep/9407-type-promotion.html @@ -192,22 +189,6 @@ def least_upper_float(dt:DType) -> DType: return dt if dtypes.is_float(dt) else DTYPES_DICT = {k: v for k, v in dtypes.__dict__.items() if isinstance(v, DType) and not k.startswith(("default", "void"))} INVERSE_DTYPES_DICT = {**{v.name:k for k,v in DTYPES_DICT.items()}, "void": "void"} -@functools.cache -def can_safe_cast(dt0:DType, dt1:DType) -> bool: - # return if dt1 preserves value of dt0 - # https://numpy.org/doc/stable/reference/generated/numpy.can_cast.html - if dt0 == dt1 or dt0 == dtypes.bool: return True - match dt1: - case dtypes.double: return dt0 in (dtypes.float, dtypes.half, dtypes.bfloat16, - dtypes.uint32, dtypes.uint16, dtypes.uint8, dtypes.int32, dtypes.int16, dtypes.int8) - case dtypes.float: return dt0 in (dtypes.half, dtypes.bfloat16, dtypes.uint16, dtypes.uint8, dtypes.int16, dtypes.int8) - case dtypes.uint64: return dt0 in (dtypes.uint32, dtypes.uint16, dtypes.uint8) - case dtypes.uint32: return dt0 in (dtypes.uint16, dtypes.uint8) - case dtypes.int64: return dt0 in (dtypes.uint32, dtypes.uint16, dtypes.uint8, dtypes.int32, dtypes.int16, dtypes.int8) - case dtypes.int32: return dt0 in (dtypes.uint16, dtypes.uint8, dtypes.int16, dtypes.int8) - case dtypes.int16: return dt0 in (dtypes.uint8, dtypes.int8) - case _: return False - def sum_acc_dtype(dt:DType): # default acc dtype for sum if dtypes.is_unsigned(dt): return least_upper_dtype(dt, dtypes.uint) @@ -215,14 +196,15 @@ def sum_acc_dtype(dt:DType): return least_upper_dtype(dt, to_dtype(getenv("SUM_DTYPE", "float32"))) def truncate_fp16(x): - try: return struct.unpack('e', struct.pack('e', float(x)))[0] + try: return struct.unpack("@e", struct.pack("@e", float(x)))[0] except OverflowError: return math.copysign(math.inf, x) -def float_to_bf16(x): - if not math.isfinite(x): return x - u = struct.unpack('I', struct.pack('f', x))[0] - u = (u + 0x7FFF + ((u >> 16) & 1)) & 0xFFFF0000 - return struct.unpack('f', struct.pack('I', u))[0] +def truncate_bf16(x): + max_bf16 = struct.unpack('f', struct.pack('I', 0x7f7f0000))[0] + if abs(x) > max_bf16: return math.copysign(math.inf, x) + f32_int = struct.unpack('I', struct.pack('f', x))[0] + bf = struct.unpack('f', struct.pack('I', f32_int & 0xFFFF0000))[0] + return bf # fp8-float conversions based on https://gitlab.com/nvidia/headers/cuda-individual/cudart/-/blob/main/cuda_fp8.hpp def float_to_fp8(x: float, dtype: DType) -> int: @@ -287,7 +269,7 @@ def fp8_to_float(x: int, dtype: DType) -> float: return float(float32_val) truncate: dict[DType, Callable] = {dtypes.bool: bool, - dtypes.float16: truncate_fp16, dtypes.bfloat16: lambda x: float_to_bf16(float(x)), + dtypes.float16: truncate_fp16, dtypes.bfloat16: truncate_bf16, **{fp8: (lambda x, dtype=fp8: fp8_to_float(float_to_fp8(x, dtype), dtype)) for fp8 in dtypes.fp8s}, dtypes.float32: lambda x: ctypes.c_float(x).value, dtypes.float64: lambda x: ctypes.c_double(x).value, dtypes.uint8: lambda x: ctypes.c_uint8(x).value, dtypes.uint16: lambda x: ctypes.c_uint16(x).value, @@ -297,22 +279,19 @@ truncate: dict[DType, Callable] = {dtypes.bool: bool, # numpy and torch dtype interop -def _to_np_dtype(dtype:DType) -> type|None: +def _to_np_dtype(dtype:DType) -> Optional[type]: import numpy as np - if dtype == dtypes.bfloat16: return np.float32 return np.dtype(dtype.fmt).type if dtype.fmt is not None else None def _from_np_dtype(npdtype:'np.dtype') -> DType: # type: ignore [name-defined] # noqa: F821 import numpy as np return dtypes.fields()[np.dtype(npdtype).name] @functools.cache -def _to_torch_dtype(dtype:DType) -> 'torch.dtype'|None: # type: ignore [name-defined] # noqa: F821 +def _to_torch_dtype(dtype:DType) -> Optional['torch.dtype']: # type: ignore [name-defined] # noqa: F821 import numpy as np, torch - if dtype == dtypes.uint64: return torch.uint64 - if dtype == dtypes.bfloat16: return torch.bfloat16 # NOTE: torch doesn't expose this mapping with a stable API try: return torch.from_numpy(np.array([], dtype=_to_np_dtype(dtype))).dtype except TypeError: return None @functools.cache def _from_torch_dtype(torchdtype:'torch.dtype') -> DType: # type: ignore [name-defined] # noqa: F821 - return {v:k for k in dtypes.all if (v:=_to_torch_dtype(k)) is not None}[torchdtype] + return {v:k for k in dtypes.all if (v:=_to_torch_dtype(k)) is not None}[torchdtype] \ No newline at end of file diff --git a/tinygrad_repo/tinygrad/engine/jit.py b/tinygrad_repo/tinygrad/engine/jit.py index 2254c606e..a093ba05b 100644 --- a/tinygrad_repo/tinygrad/engine/jit.py +++ b/tinygrad_repo/tinygrad/engine/jit.py @@ -1,7 +1,7 @@ -from typing import TypeVar, Generic, Callable, cast, Any +from typing import TypeVar, Generic, Callable, Union, cast, Optional, Any import functools, collections from tinygrad.tensor import Tensor -from tinygrad.helpers import flatten, merge_dicts, DEBUG, Context, BEAM, getenv, colored, JIT, JIT_BATCH_SIZE, dedup, partition, unwrap +from tinygrad.helpers import flatten, merge_dicts, DEBUG, Context, BEAM, getenv, colored, JIT, dedup, partition, unwrap from tinygrad.device import Buffer, Compiled, Device, MultiBuffer from tinygrad.dtype import DType from tinygrad.uop.ops import UOp, Variable, sym_infer, Ops @@ -21,45 +21,44 @@ def apply_graph_to_jit(jit_cache: list[ExecItem], input_rawbuffers: list[Buffer] # This allows the accelerator to run some batches while subsequent graphs are still being updated. graphed_jit_cache: list[ExecItem] = [] current_batch: list[ExecItem] = [] - current_batch_devs: list[Compiled] = [] + current_device: Optional[Compiled] = None def flush_batch(): - nonlocal current_batch, current_batch_devs, max_batch_size + nonlocal current_batch, current_device, max_batch_size try: - if len(current_batch_devs) == 0: raise GraphException("no device for graph") + if current_device is None: raise GraphException("no device for graph") if len(current_batch) <= 1 and not getenv("GRAPH_ONE_KERNEL"): raise GraphException("only one kernel doesn't graph") - graph_runner = current_batch_devs[0].graph(current_batch, input_rawbuffers, var_vals) + graph_runner = current_device.graph(current_batch, input_rawbuffers, var_vals) # clear jit inputs to allow their memory to be freed/reused for (j,i) in graph_runner.input_replace.keys(): graph_runner.jit_cache[j].bufs[i] = None - graphed_jit_cache.append(ExecItem(graph_runner, cast(list[Buffer|None], input_rawbuffers))) + graphed_jit_cache.append(ExecItem(graph_runner, cast(list[Optional[Buffer]], input_rawbuffers))) max_batch_size *= 2 - if DEBUG >= 2: print(f"JIT GRAPHing batch with {len(current_batch)} kernels on device {current_batch_devs[0]}") + if DEBUG >= 2: print(f"JIT GRAPHing batch with {len(current_batch)} kernels on device {current_device}") except GraphException as e: graphed_jit_cache.extend(current_batch) - if DEBUG >= 2: print(f"JIT GRAPHing failed batch with {len(current_batch)} kernels on device {current_batch_devs[0]}: {e}") + if DEBUG >= 2: print(f"JIT GRAPHing failed batch with {len(current_batch)} kernels on device {current_device}: {e}") current_batch = [] - current_batch_devs = [] + current_device = None for ji in jit_cache: match ji.prg: - case CompiledRunner(): ji_graph_dev = ji.prg.dev - case BufferXfer(): ji_graph_dev = Device[unwrap(ji.bufs[0]).device] - case BufferCopy(): ji_graph_dev = next((Device[unwrap(b).device] for b in ji.bufs if unwrap(b).device not in {"CPU", "LLVM"}), None) + case CompiledRunner(): + ji_graph_dev = ji.prg.dev + # All GraphRunners can graph CompiledRunners + can_be_graphed = ji_graph_dev.graph is not None + case BufferXfer(): + ji_graph_dev = Device[unwrap(ji.bufs[0]).device] + # All *Multi*GraphRunner support graphing BufferXfers + can_be_graphed = ji_graph_dev.graph is not None and issubclass(graph_class(ji_graph_dev), MultiGraphRunner) case ViewOp(): continue # ViewOps are just ignored - case _: ji_graph_dev = None # Everything else is not graphed and flushes existing graph if it's being constructed + case _: can_be_graphed = False # Everything else is not graphed and flushes existing graph if it's being constructed - # Check if this jit item can be graphed at all, so check if a new graph supports the current item. - can_be_graphed = ji_graph_dev is not None and ji_graph_dev.graph is not None and graph_class(ji_graph_dev).supports_exec_item([ji_graph_dev], ji) - - # Check if the current batch can be extended with this item. - can_share_graph = can_be_graphed and len(current_batch_devs) > 0 and \ - graph_class(current_batch_devs[0]).supports_exec_item(dedup(current_batch_devs + [ji_graph_dev]), ji) + is_multigraph = can_be_graphed and issubclass(graph_class(ji_graph_dev), MultiGraphRunner) + can_share_graph = can_be_graphed and (type(ji_graph_dev) is type(current_device) if is_multigraph else ji_graph_dev == current_device) can_extend_graph_batch = can_share_graph and (max_batch_size == 0 or len(current_batch) < max_batch_size) - - # Flush the current batch if any, since it can't be extended or is full. if not can_extend_graph_batch and len(current_batch) > 0: flush_batch() (current_batch if can_be_graphed else graphed_jit_cache).append(ji) - current_batch_devs = dedup(current_batch_devs + [ji_graph_dev]) if can_be_graphed else [] + current_device = ji_graph_dev if can_be_graphed else None if len(current_batch) > 0: flush_batch() return graphed_jit_cache @@ -77,7 +76,7 @@ class GraphRunner(Runner): self.jit_cache = jit_cache # NOTE: this is not used, but you have to keep these objects alive for the Graph self.input_replace:dict[tuple[int, int], int] = get_input_replace(jit_cache, input_rawbuffers) self.var_vals_replace:dict[int, list[tuple[int, int]]] = {} - self.launch_dims_replace:dict[int, tuple[int|None, int|None]] = {} + self.launch_dims_replace:dict[int, tuple[Optional[int], Optional[int]]] = {} self.launch_dims_base:dict[int, tuple[tuple[int, ...], tuple[int, ...]]] = {} def is_sym_dim(dim) -> bool: return not all(isinstance(d, (int, float)) for d in dim) @@ -131,15 +130,8 @@ class GraphRunner(Runner): return list({id(x):x for x in wait_nodes}.values()) - @staticmethod - def supports_exec_item(devs:list[Compiled], ei:ExecItem) -> bool: return isinstance(ei.prg, CompiledRunner) and len(dedup(devs)) == 1 - # a marker for your graph supporting multiple devices of the same type -class MultiGraphRunner(GraphRunner): - @staticmethod - def supports_exec_item(devs:list[Compiled], ei:ExecItem) -> bool: - # Devices must be the same type - return isinstance(ei.prg, (CompiledRunner, BufferXfer)) and len(dedup([type(Device[b.device]) for b in ei.bufs if b]+[type(d) for d in devs]))==1 +class MultiGraphRunner(GraphRunner): pass def get_out_buffers_for_ei(ei:ExecItem) -> list[Buffer]: if isinstance(ei.prg, CompiledRunner): return [cast(Buffer, ei.bufs[out]) for out in ei.prg.p.outs if out not in ei.prg.p.ins] @@ -157,7 +149,7 @@ class CapturedJit(Generic[ReturnType]): jit_cache: list[ExecItem] input_replace: dict[tuple[int, int], int] extra_view_inputs: list[tuple[int, int, str, int, DType]] - expected_names: list[int|str] + expected_names: list[Union[int, str]] expected_st_vars_dtype_device: list[tuple[ShapeTracker, tuple[Variable, ...], DType, str]] def __reduce__(self): @@ -206,7 +198,7 @@ class CapturedJit(Generic[ReturnType]): if b is not None: b.ensure_allocated() # create graph if needed if JIT < 2: - self._jit_cache = apply_graph_to_jit(self.jit_cache, input_buffers, var_vals, max_batch_size=JIT_BATCH_SIZE.value) + self._jit_cache = apply_graph_to_jit(self.jit_cache, input_buffers, var_vals, max_batch_size=getenv("JIT_BATCH_SIZE", 32)) self._input_replace = get_input_replace(self._jit_cache, input_buffers) self._first_run = False @@ -230,10 +222,10 @@ def _prepare_jit_inputs(args, kwargs): return input_buffers, var_vals, names, st_vars_dtype_device class TinyJit(Generic[ReturnType]): - def __init__(self, fxn:Callable[..., ReturnType]|None, captured:CapturedJit|None=None, prune=False, optimize=False): + def __init__(self, fxn:Optional[Callable[..., ReturnType]], captured:Optional[CapturedJit]=None, prune=False, optimize=False): assert fxn or captured, "need either a function or a CapturedJit" self.fxn = fxn - self.captured: CapturedJit|None = captured + self.captured: Optional[CapturedJit] = captured self.cnt: int = 2 if self.fxn is None else 0 self.prune = prune self.optimize = optimize diff --git a/tinygrad_repo/tinygrad/engine/memory.py b/tinygrad_repo/tinygrad/engine/memory.py index 36a4e3b0b..2c62b3f6a 100644 --- a/tinygrad_repo/tinygrad/engine/memory.py +++ b/tinygrad_repo/tinygrad/engine/memory.py @@ -23,13 +23,12 @@ def _internal_memory_planner(buffers:list[list[Buffer]], noopt_buffers=None, ign # Sort buffer operations in timeline order. Two events: buffer is allocated or buffer is freed. buffer_requests = sorted([((first_appearance[buf], True), buf) for buf in first_appearance.keys()] + \ [((last_appearance[buf] + 1, False), buf) for buf in first_appearance.keys()], key=lambda x: x[0]) - total_memory = sum(round_up(buf.nbytes, min_block_size:=0x1000) for buf in first_appearance.keys()) * 2 # *2 for fragmentation (which is about 15%) # Try to suballocate from a shared buffer managed by global_planner using TLSFAllocator. # Also track buffer replacements for buffers that do not support suballocation. buffer_replace:dict[Buffer, tuple[Buffer|None, int|None]] = {} reuse_buffers:dict[tuple, list[Buffer]] = defaultdict(list) - global_planner:dict[str, tuple[int, TLSFAllocator]] = defaultdict(lambda: (0, TLSFAllocator(total_memory, block_size=min_block_size, lv2_cnt=32))) + global_planner:dict[str, tuple[int, TLSFAllocator]] = defaultdict(lambda: (0, TLSFAllocator(1 << 44, block_size=0x1000, lv2_cnt=32))) for (_, is_open_ev), buf in buffer_requests: # Check if suballocation is possible for the given buffer and device. if hasattr(Device[buf.device].allocator, "_offset") and not isinstance(buf.dtype, ImageDType): diff --git a/tinygrad_repo/tinygrad/engine/realize.py b/tinygrad_repo/tinygrad/engine/realize.py index bcf032fcc..4473dd809 100644 --- a/tinygrad_repo/tinygrad/engine/realize.py +++ b/tinygrad_repo/tinygrad/engine/realize.py @@ -1,19 +1,20 @@ -from typing import cast, Generator, Callable -import time, pprint, random, itertools, math +from typing import Optional, cast, Generator +import time, pprint from dataclasses import dataclass, replace, field -from tinygrad.helpers import all_same, colored, DEBUG, GlobalCounters, ansilen, BEAM, NOOPT, all_int, CAPTURING, Metadata, TRACEMETA, TracingKey -from tinygrad.helpers import DEVECTORIZE, time_to_str, VALIDATE_WITH_CPU, getenv, cpu_profile, PROFILE, ProfilePointEvent, cpu_events, prod -from tinygrad.uop.ops import Ops, PatternMatcher, UOp, UPat, Variable, sym_infer, graph_rewrite, print_uops, track_rewrites, KernelInfo +from tinygrad.helpers import all_same, colored, DEBUG, GlobalCounters, ansilen, BEAM, NOOPT, all_int, CAPTURING, Metadata, TRACEMETA +from tinygrad.helpers import DEVECTORIZE, time_to_str, VALIDATE_WITH_CPU, getenv +from tinygrad.uop.ops import Ops, PatternMatcher, UOp, UPat, Variable, sym_infer, graph_rewrite, print_uops, track_rewrites from tinygrad.device import Device, Buffer from tinygrad.renderer import Renderer, ProgramSpec, Estimates from tinygrad.engine.schedule import ScheduleItem +from tinygrad.opt import get_optimized_ast from tinygrad.codegen import full_rewrite -from tinygrad.codegen.opt.kernel import Opt +from tinygrad.uop.spec import type_verify # **************** Program Creation **************** -@track_rewrites(name=lambda *args,ret,**kwargs: TracingKey(ret.name, (ret.function_name, ret.ast), ret=ret), replay=True) -def get_program(ast:UOp, renderer:Renderer|None=None, opts:list[Opt]|None=None) -> ProgramSpec: +@track_rewrites(name=lambda _ast,_renderer,ret:ret) +def get_program(ast:UOp, renderer:Renderer) -> ProgramSpec: """ Transform an AST into a ProgramSpec. May trigger BEAM search. @@ -26,18 +27,16 @@ def get_program(ast:UOp, renderer:Renderer|None=None, opts:list[Opt]|None=None) """ if getenv("VIZ"): graph_rewrite(ast, PatternMatcher([]), name="View Base AST") + modified_ast = get_optimized_ast(ast, renderer) if ast.arg is None or ast.arg.opts_to_apply is not None else ast + if __debug__: type_verify(list(modified_ast.toposort())) # linearize - if renderer is None: renderer = Device.default.renderer - if opts is not None: - assert ast.arg is None, "can't apply opts if sink has an arg" - ast = ast.replace(arg=KernelInfo(opts_to_apply=tuple(opts))) try: - uops = full_rewrite(ast, renderer) - except RuntimeError as e: + uops = full_rewrite(modified_ast, renderer) + except RuntimeError: print("***** LINEARIZE FAILURE *****") - print(e) print(f"ast = {ast}") + print(f"opts = {modified_ast.arg.applied_opts}") raise assert uops[-1].op is Ops.SINK, "last uop must be sink" @@ -45,7 +44,7 @@ def get_program(ast:UOp, renderer:Renderer|None=None, opts:list[Opt]|None=None) if DEBUG >= 6: print_uops(uops) src = renderer.render(uops) - return ProgramSpec(uops[-1].arg.name if uops[-1].arg is not None else "test", src, renderer.device, ast, uops, + return ProgramSpec(uops[-1].arg.name, src, renderer.device, ast, uops, global_size=[1,1,1] if renderer.has_local else None, local_size=[1,1,1] if renderer.has_local else None) # **************** Runners **************** @@ -55,42 +54,27 @@ class Runner: self.first_run, self.display_name, self.device, self.estimates = True, display_name, device, estimates @property def dev(self): return Device[self.device] - def exec(self, rawbufs:list[Buffer], var_vals:dict[Variable, int]|None=None) -> float|None: + def exec(self, rawbufs:list[Buffer], var_vals:Optional[dict[Variable, int]]=None) -> Optional[float]: return self(rawbufs, {} if var_vals is None else var_vals) - def __call__(self, rawbufs:list[Buffer], var_vals:dict[Variable, int], wait=False) -> float|None: + def __call__(self, rawbufs:list[Buffer], var_vals:dict[Variable, int], wait=False) -> Optional[float]: raise NotImplementedError("override this") -def optimize_local_size(_prg:Callable, global_size:list[int], rawbufs:list[Buffer]) -> list[int]: - test_rawbuffers = [Buffer(rawbufs[0].device, rawbufs[0].size, rawbufs[0].dtype).allocate(), *rawbufs[1:]] if rawbufs[0] in rawbufs[1:] else rawbufs - MAX_WORKGROUP = 1024 - local_dims = [[x for x in set([sz, 1, 2, 4, 8, 16, 32, 64, 128, 256, MAX_WORKGROUP]) if x<=sz] for sz in global_size] - local_sizes = [list(x) for x in itertools.product(*local_dims) if prod(x) <= MAX_WORKGROUP] * 2 # try each valid size twice - def try_exec(local_size): - try: - return _prg(*[x._buf for x in test_rawbuffers],global_size=[g//l if g%l == 0 else g/l for g,l in zip(global_size, local_size)], - local_size=local_size, wait=True) - except Exception: return float('inf') - ret = min([(try_exec(local_size), local_size) for local_size in random.sample(local_sizes, len(local_sizes))]) - assert not math.isinf(ret[0]), "all optimize_local_size exec failed" - return ret[1] - class CompiledRunner(Runner): - def __init__(self, p:ProgramSpec, precompiled:bytes|None=None, prg=None): + def __init__(self, p:ProgramSpec, precompiled:Optional[bytes]=None, prg=None): if DEBUG >= 4: print(p.src) self.p:ProgramSpec = p - if precompiled is not None: self.lib = precompiled - else: - with cpu_profile(TracingKey(f"compile {p.name}", (p.function_name,)), "TINY"): - self.lib = Device[p.device].compiler.compile_cached(p.src) + self.lib:bytes = precompiled if precompiled is not None else Device[p.device].compiler.compile_cached(p.src) if DEBUG >= 7: Device[p.device].compiler.disassemble(self.lib) self._prg = Device[p.device].runtime(p.function_name, self.lib) if prg is None else prg super().__init__(p.name, p.device, p.estimates) def __reduce__(self): return self.__class__, (self.p, self.lib) - def __call__(self, rawbufs:list[Buffer], var_vals:dict[Variable, int], wait=False) -> float|None: + def __call__(self, rawbufs:list[Buffer], var_vals:dict[Variable, int], wait=False) -> Optional[float]: global_size, local_size = self.p.launch_dims(var_vals) if global_size is not None and local_size is None and all_int(self.p.global_size): # type: ignore[arg-type] + # TODO: this is copied from get_program + from tinygrad.opt.search import optimize_local_size local_size = optimize_local_size(self._prg, global_size, rawbufs) global_size = [g//l if g%l == 0 else g/l for g,l in zip(global_size, local_size)] self.p = replace(self.p, global_size=global_size, local_size=local_size) @@ -115,7 +99,7 @@ class BufferCopy(Runner): super().__init__(colored(name, "yellow"), dest_device, Estimates(lds=total_sz, mem=total_sz)) def copy(self, dest, src): disk_supports_fast_copyout = src.device.startswith("DISK") and hasattr(src.allocator.dev, 'io_uring') and \ - getattr(src.allocator.dev, 'fd', None) is not None and dest.allocator.supports_copy_from_disk + getattr(src.allocator.dev, 'fd', None) is not None if src.device.startswith("DISK") and hasattr(dest.allocator, 'copy_from_disk') and disk_supports_fast_copyout and src.nbytes >= 4096: dest.allocator.copy_from_disk(dest._buf, src._buf, src.nbytes) elif src.device.startswith("DISK") and hasattr(dest.allocator, '_as_buffer'): @@ -156,13 +140,12 @@ def get_runner(device:str, ast:UOp) -> CompiledRunner: @dataclass(frozen=True) class ExecItem: prg: Runner - bufs: list[Buffer|None] - metadata: tuple[Metadata, ...]|None = None + bufs: list[Optional[Buffer]] + metadata: Optional[tuple[Metadata, ...]] = None fixedvars: dict[Variable, int] = field(default_factory=dict) - def run(self, _var_vals:dict[Variable, int]|None=None, wait=False, jit=False, do_update_stats=True) -> float|None: + def run(self, _var_vals:Optional[dict[Variable, int]]=None, wait=False, jit=False, do_update_stats=True) -> Optional[float]: var_vals = self.fixedvars if _var_vals is None else (_var_vals|self.fixedvars) bufs = [cast(Buffer, x) for x in self.bufs] if jit else [cast(Buffer, x).ensure_allocated() for x in self.bufs] - if PROFILE: cpu_events.append(ProfilePointEvent(self.prg.device, "exec", self.prg.display_name, {"metadata":self.metadata, "var_vals":var_vals})) et = self.prg(bufs, var_vals, wait=wait or DEBUG >= 2) if do_update_stats: GlobalCounters.kernel_count += 1 @@ -172,15 +155,10 @@ class ExecItem: if DEBUG >= 2: lds_est = sym_infer(self.prg.estimates.lds, var_vals) mem_est = min(mem_est, lds_est) # there can't be more memory accessed than loads/stores. remove this when symbolic is fixed - header_color = 'magenta' if jit else ('green' if self.prg.first_run else None) ptm = colored(time_to_str(et, w=9), "yellow" if et > 0.01 else None) if et is not None else "" - flops, membw, ldsbw = op_est/(et or 1e-20), mem_est/(et or 1e-20), lds_est/(et or 1e-20) - flops_str = f"{flops*1e-9:9.2f} GFLOPS" if flops < 1e14 else colored(f"{flops*1e-12:9.2f} TFLOPS", 'green') - mem_str = f"{membw*1e-9:6.1f}|{ldsbw*1e-9:<7.1f} GB/s" if membw < 1e13 else colored(f"{membw*1e-12:6.1f}|{ldsbw*1e-12:<7.1f} TB/s", 'green') - print(f"{colored(f'*** {self.prg.device[:7]:7s} {GlobalCounters.kernel_count:4d}', header_color)}"+ - f" {self.prg.display_name+' '*(44-ansilen(self.prg.display_name))} arg {len(bufs):2d} mem {GlobalCounters.mem_used/1e9:5.2f} GB"+ - ("" if et is None else f" tm {ptm}/{GlobalCounters.time_sum_s*1e3:9.2f}ms ({flops_str} {mem_str})")+ - f" {[repr(m) if TRACEMETA >= 2 else str(m) for m in self.metadata] if self.metadata else ''}") + print(f"{colored(f'*** {self.prg.device[:7]:7s} {GlobalCounters.kernel_count:4d}', 'magenta' if jit else ('green' if self.prg.first_run else None))} {self.prg.display_name+' '*(41-ansilen(self.prg.display_name))} arg {len(bufs):2d} mem {GlobalCounters.mem_used/1e9:5.2f} GB " + # noqa: E501 + (str() if et is None else f"tm {ptm}/{GlobalCounters.time_sum_s*1e3:9.2f}ms ({op_est/((et or 1e-20)*1e9):9.2f} GFLOPS {mem_est/((et or 1e-20)*1e9):6.1f}|{lds_est/((et or 1e-20)*1e9):<7.1f} GB/s)" + # noqa: E501 + f" {[repr(m) if TRACEMETA >= 2 else str(m) for m in self.metadata] if self.metadata else ''}")) self.prg.first_run = False return et @@ -210,7 +188,7 @@ def lower_schedule(schedule:list[ScheduleItem]) -> Generator[tuple[ScheduleItem, capturing: list = [] # put classes with an add method in here -def run_schedule(schedule:list[ScheduleItem], var_vals:dict[Variable, int]|None=None, do_update_stats=True): +def run_schedule(schedule:list[ScheduleItem], var_vals:Optional[dict[Variable, int]]=None, do_update_stats=True): for si, ei in lower_schedule(schedule): if len(capturing) and CAPTURING: capturing[0].add(ei) if VALIDATE_WITH_CPU and si.ast.op is Ops.SINK: diff --git a/tinygrad_repo/tinygrad/engine/schedule.py b/tinygrad_repo/tinygrad/engine/schedule.py index 1e6b5259a..9a64639bf 100644 --- a/tinygrad_repo/tinygrad/engine/schedule.py +++ b/tinygrad_repo/tinygrad/engine/schedule.py @@ -1,9 +1,9 @@ from typing import cast from dataclasses import dataclass, field from collections import deque, defaultdict -from tinygrad.uop.ops import UOp, Variable, Ops, buffers -from tinygrad.device import Device, Buffer, MultiBuffer -from tinygrad.helpers import Metadata, all_same +from tinygrad.uop.ops import UOp, Variable, Ops, UPat, PatternMatcher, graph_rewrite, buffers +from tinygrad.device import Buffer, MultiBuffer +from tinygrad.helpers import Metadata, unwrap, merge_dicts # **** ScheduleItem return type @@ -14,13 +14,32 @@ class ScheduleItem: metadata: tuple[Metadata, ...] = () fixedvars: dict[Variable, int] = field(default_factory=dict) +# **** unbind Variables + +def unbind_view(ctx:list[dict[Variable, int]], x:UOp): + st = unwrap(x.st).simplify() + if any(x.op is Ops.BIND for x in st.vars()): + st, var_vals = st.unbind() + ctx.append(var_vals) + return x.replace(arg=st) + return None + +def unbind_bind(ctx:list[dict[Variable, int]], x:UOp): + var, val = x.unbind() + ctx.append({var.replace(src=()):val}) + return var + +pm_unbind = PatternMatcher([ + (UPat(Ops.VIEW, name="x"), unbind_view), + (UPat(Ops.BIND, name="x"), unbind_bind), +]) + # **** schedule linearizer def create_schedule_with_vars(sched_sink:UOp) -> tuple[list[ScheduleItem], dict[Variable, int]]: # construct the KERNEL children graph based on assigns children: defaultdict[UOp, list[UOp]] = defaultdict(list) in_degree: dict[UOp, int] = {} - var_vals: dict[Variable, int] = {} for u in sched_sink.toposort(): if u.op is not Ops.ASSIGN: continue # anything that's not an ASSIGN doesn't write a kernel, so we can skip k = u.src[1] @@ -33,41 +52,30 @@ def create_schedule_with_vars(sched_sink:UOp) -> tuple[list[ScheduleItem], dict[ for ss in s.src: if ss.op is Ops.MSELECT: ss = ss.src[0] if ss.op is not Ops.BUFFER: - assert ss.op is Ops.ASSIGN, f"ss.op is not ASSIGN, it's {ss.op}" + assert ss.op is Ops.ASSIGN children[ss.src[1]].append(k) in_degree[k] += 1 elif s.op is Ops.BUFFER: pass # a BUFFER is already realized, nothing to do here - elif s.op is Ops.BIND: - var, val = s.unbind() - assert var not in var_vals or var_vals[var] == val, f"bind mismatch on {var}, {var_vals[var]} != {val}" - var_vals[var] = val else: raise RuntimeError(f"input to kernel must be ASSIGN or BUFFER, not {s.op}") # linearize KERNEL UOps into ScheduleItems in BFS order - - def _heuristic(k: UOp): - if k.arg.ast.op is Ops.COPY and not all_same([Device[cast(Buffer, s.buf_uop.buffer).device].group_id for s in k.src]): return 1000 - return 0 - - last_heuristic: int = 0 - queues: defaultdict[int, deque[UOp]] = defaultdict(deque) - last_queue: deque[UOp] = deque() - for k,v in in_degree.items(): - if v == 0: queues[_heuristic(k)].append(k) - + queue = deque(k for k,v in in_degree.items() if v == 0) schedule: list[ScheduleItem] = [] - while last_queue or any(queues.values()): - if not last_queue: last_heuristic, last_queue = min((it for it in queues.items() if it[1]), key=lambda x: abs(x[0]-last_heuristic)) - k = last_queue.popleft() - ast = k.arg.ast + var_vals: dict[Variable, int] = {} + while queue: + k = queue.popleft() + # unbind var_vals from the kernel + local_var_vals: list[dict[Variable, int]] = [] + ast = graph_rewrite(k.arg.ast, pm_unbind, ctx=local_var_vals, name="unbind vars") + var_vals = merge_dicts([var_vals, *local_var_vals]) # create subbuffers if needed if ast.op is Ops.BUFFER_VIEW: base = k.src[1].buf_uop.buffer assert isinstance(base, Buffer), "base can't be MultiBuffer" buffers[k.src[0]] = base.view(k.size, ast.dtype, ast.arg[1]*base.dtype.itemsize) - ubufs = tuple(s.buf_uop.buffer for s in k.src if s.op is not Ops.BIND) + ubufs = tuple(s.buf_uop.buffer for s in k.src) if any(isinstance(x, MultiBuffer) for x in ubufs): assert all(isinstance(x, MultiBuffer) for x in ubufs), "kernel must all be multibuffer" dnums = [x for x in ast.variables() if x.arg[0] == '_device_num'] @@ -78,6 +86,6 @@ def create_schedule_with_vars(sched_sink:UOp) -> tuple[list[ScheduleItem], dict[ schedule.append(ScheduleItem(ast, cast(tuple[Buffer, ...], ubufs), k.arg.metadata)) for x in children[k]: in_degree[x] -= 1 - if in_degree[x] == 0: queues[_heuristic(x)].append(x) + if in_degree[x] == 0: queue.append(x) return schedule, var_vals diff --git a/tinygrad_repo/tinygrad/frontend/onnx.py b/tinygrad_repo/tinygrad/frontend/onnx.py index 33d540860..db34a70be 100644 --- a/tinygrad_repo/tinygrad/frontend/onnx.py +++ b/tinygrad_repo/tinygrad/frontend/onnx.py @@ -1,1281 +1,7 @@ -# pylint: disable=possibly-unused-variable -from typing import Any, Sequence, cast, Literal, NamedTuple, Generator -import dataclasses, functools, io, math, types, warnings, pathlib, sys, os, struct, enum -from io import BufferedReader -from tinygrad.nn.state import TensorIO -from tinygrad.tensor import Tensor, _broadcast_shape, ReductionStr -from tinygrad.helpers import getenv, DEBUG, all_same, prod, flatten, make_tuple, argsort, is_numpy_ndarray, get_single_element, polyN -from tinygrad.dtype import DType, ConstType, dtypes, _from_np_dtype, truncate -from tinygrad.device import is_dtype_supported, Device - -# ***** protobuf definitions ****** -class WireType(enum.IntEnum): - """ - Protocol Buffer wire types for decoding fields. - Reference: https://github.com/protocolbuffers/protobuf/blob/main/python/google/protobuf/internal/wire_format.py#L24-L29 - """ - VARINT = 0; FIXED64 = 1; LENGTH_DELIMITED = 2; START_GROUP = 3; END_GROUP = 4; FIXED32 = 5 # noqa: E702 - -class AttributeType(enum.IntEnum): - """ - ONNX attribute type identifiers. - Reference: https://github.com/onnx/onnx/blob/rel-1.18.0/onnx/onnx.proto3#L128-L145 - """ - FLOAT = 1; INT = 2; STRING = 3; TENSOR = 4; GRAPH = 5; FLOATS = 6; INTS = 7; STRINGS = 8 # noqa: E702 - - def to_field_name(self) -> str: return {1: "f", 2: "i", 3: "s", 4: "t", 5: "g", 6: "floats", 7: "ints", 8: "strings"}[self.value] - -class OnnxDataType(enum.IntEnum): - """ - ONNX tensor data type identifiers. - Reference: https://github.com/onnx/onnx/blob/rel-1.18.0/onnx/onnx.proto3#L500-L544 - """ - FLOAT = 1; UINT8 = 2; INT8 = 3; UINT16 = 4; INT16 = 5; INT32 = 6; INT64 = 7; BOOL = 9; FLOAT16 = 10; DOUBLE = 11; UINT32 = 12 # noqa: E702 - UINT64 = 13; BFLOAT16 = 16 # noqa: E702 - - def to_dtype(self) -> DType: return dtypes.fields()[self.name.lower()] - -def dtype_fallback(dtype: DType, fallback_context: str) -> DType: - if is_dtype_supported(dtype): return dtype - default_dtype = dtypes.default_int if dtypes.is_int(dtype) else dtypes.default_float - warnings.warn(f"dtype {dtype} on {Device.DEFAULT} from {fallback_context} is not supported, falling back to {default_dtype}") - assert is_dtype_supported(default_dtype), f"dtype {default_dtype} must be supported on {Device.DEFAULT}" - return default_dtype - -# ***** onnx spec definitions ***** -class Domain(enum.Enum): - ONNX = "ai.onnx" - ONNX_ML = "ai.onnx.ml" - AI_ONNX_TRAINING = "ai.onnx.training" - AI_ONNX_PREVIEW_TRAINING = "ai.onnx.preview.training" - MICROSOFT_CONTRIB_OPS = "com.microsoft" - MICROSOFT_NCHWC = "com.microsoft.nchwc" - MICROSOFT_EXPERIMENTAL = "com.microsoft.experimental" - PYTORCH_ATEN = "org.pytorch.aten" - @classmethod - def from_onnx(cls, domain: str | None) -> "Domain": return cls.ONNX if domain is None or domain == "" else cls(domain) - -class OpSetId(NamedTuple): - domain: Domain - version: int - -@dataclasses.dataclass(frozen=True) -class OnnxValue: - shape: tuple[str|int, ...] - dtype: DType - is_optional: bool - is_sequence: bool - -@dataclasses.dataclass(frozen=True) -class OnnxNode: - op: str - opset_id: OpSetId - inputs: tuple[str, ...] - outputs: tuple[str, ...] - opts: dict[str, Any] - -# ***** protobuf parsing ****** -class PBBufferedReader(BufferedReader): - def __init__(self, tensor: Tensor): - assert tensor.dtype == dtypes.uint8, tensor - super().__init__(TensorIO(tensor)) - self.len = tensor.nbytes() - - def decode_varint(self) -> int: - """Reference: https://protobuf.dev/programming-guides/encoding/#varints""" - result = 0 - shift = 0 - while True: - data = self.read(1) - if data == b"": raise EOFError("decode_varint EOF") - result |= (data[0] & 0x7F) << shift - if not (data[0] & 0x80): return result - shift += 7 - if shift >= 70: raise ValueError("Varint too long") - - def read_delimited(self, use_tensor=False): - str_len = self.decode_varint() - if not use_tensor: return self.read(str_len) - raw = self.raw - assert isinstance(raw, TensorIO) - res = raw._tensor[self.tell():(self.tell()+str_len)] - self.seek(str_len, os.SEEK_CUR) - return res - def read_string(self) -> str: return self.read_delimited().decode("utf-8") - def read_bytes(self) -> Tensor: return self.read_delimited(use_tensor=True) - def read_float(self) -> float: return struct.unpack(" Tensor: return self.read_delimited(use_tensor=True) - def read_int64(self) -> int: return truncate[dtypes.int64](self.decode_varint()) - def read_packed_int64s(self) -> list[int]: - total_bytes_len = self.decode_varint() - old_pos = self.tell() - values = [] - # need copy here because packed ints are varint - while self.tell() < total_bytes_len + old_pos: values.append(self.read_int64()) - return values - - def skip_field(self, wire_type: WireType) -> None: - """Skip a field based on its wire type.""" - match wire_type: - case WireType.VARINT: self.decode_varint() - case WireType.FIXED64: self.seek(8, os.SEEK_CUR) - case WireType.FIXED32: self.seek(4, os.SEEK_CUR) - case WireType.LENGTH_DELIMITED: self.seek(self.decode_varint(), os.SEEK_CUR) - case _: raise ValueError(f"Unknown wire type: {wire_type}") - -class OnnxPBParser: - """ - ONNX protobuf parser. - Reference: https://github.com/onnx/onnx/blob/main/onnx/onnx.proto3 - """ - def __init__(self, inp: Tensor|str|pathlib.Path, load_external_data: bool=True): - self.file_path: pathlib.Path|None = None - self.load_external_data = load_external_data - if not isinstance(inp, Tensor): - self.file_path = pathlib.Path(inp) - self.tensor = Tensor(self.file_path) - else: self.tensor = inp - self.reader = PBBufferedReader(self.tensor) - - def parse(self) -> dict: - """Parses the ONNX model into a nested dictionary. """ - return self._parse_ModelProto() - - def _parse_message(self, end_pos: int) -> Generator[tuple[int, WireType], None, None]: - while self.reader.tell() < end_pos: - tag = self.reader.decode_varint() - yield tag >> 3, WireType(tag & 0x07) - - def _decode_end_pos(self) -> int: - str_len = self.reader.decode_varint() - start_pos = self.reader.tell() - return start_pos + str_len - - def _parse_ModelProto(self) -> dict: - """Entry point for parsing the ONNX model.""" - obj: dict[str, Any] = {"opset_import": []} - for fid, wire_type in self._parse_message(self.reader.len): - match fid: - case 4: obj["domain"] = self.reader.read_string() - case 5: obj["model_version"] = self.reader.read_int64() - case 7: obj["graph"] = self._parse_GraphProto() - case 8: obj["opset_import"].append(self._parse_OperatorSetIdProto()) - case _: self.reader.skip_field(wire_type) - - # update opset version - opset_imports = {Domain.from_onnx(x.get('domain')):x.get('version', 1) for x in obj["opset_import"]} - for n in obj["graph"]["node"]: - n_ = n["parsed_node"] - n["parsed_node"] = OnnxNode(n_.op, OpSetId(n_.opset_id.domain, opset_imports.get(n_.opset_id.domain, 1)), n_.inputs, n_.outputs, n_.opts) - return obj - - def _parse_GraphProto(self) -> dict: - obj: dict[str, Any] = {"node": [], "initializer": [], "input": [], "output": []} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["node"].append(self._parse_NodeProto()) - case 2: obj["name"] = self.reader.read_string() - case 5: obj["initializer"].append(self._parse_TensorProto()) - case 11: obj["input"].append(self._parse_ValueInfoProto()) - case 12: obj["output"].append(self._parse_ValueInfoProto()) - case _: self.reader.skip_field(wire_type) - return obj - - def _parse_NodeProto(self) -> dict: - obj: dict[str, Any] = {"input": [], "output": [], "attribute": [], "domain": None} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["input"].append(self.reader.read_string()) - case 2: obj["output"].append(self.reader.read_string()) - case 3: obj["name"] = self.reader.read_string() - case 4: obj["op_type"] = self.reader.read_string() - case 5: obj["attribute"].append(self._parse_AttributeProto()) - case 6: obj["doc_string"] = self.reader.read_string() - case 7: obj["domain"] = self.reader.read_string() - case _: self.reader.skip_field(wire_type) - - # parse node - attributes = {attr_dict["name"]: attr_dict[AttributeType(attr_dict["type"]).to_field_name()] for attr_dict in obj["attribute"]} - opset_id = OpSetId(Domain.from_onnx(obj.get('domain')), 1) # default version, to be updated later in _parse_ModelProto - obj["parsed_node"] = OnnxNode(obj["op_type"], opset_id, tuple(obj["input"]), tuple(obj["output"]), attributes) - return obj - - def _parse_TensorProto(self) -> dict: - obj: dict[str, Any] = {"dims": []} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["dims"].append(self.reader.read_int64()) - case 2: obj["data_type"] = self.reader.read_int64() - case 4: obj["float_data"] = self.reader.read_packed_floats() - case 5: obj["int32_data"] = self.reader.read_packed_int64s() - case 7: obj["int64_data"] = self.reader.read_packed_int64s() - case 8: obj["name"] = self.reader.read_string() - case 9: obj["raw_data"] = self.reader.read_bytes() - case 10: obj["double_data"] = self.reader.read_packed_floats() - case 11: obj["uint64_data"] = self.reader.read_packed_int64s() - case 13: obj.setdefault("external_data", []).append(self._parse_StringStringEntryProto()) - case 14: obj["data_location"] = self.reader.read_int64() - case _: self.reader.skip_field(wire_type) - - # load external data - if self.load_external_data and obj.get("data_location", 0) == 1: - if "external_data" not in obj: raise ValueError("no external_data") - location, length, offset = None, None, 0 - for kv in obj["external_data"]: - if kv["key"] == "location": location = kv["value"] - elif kv["key"] == "offset": offset = int(kv["value"]) - elif kv["key"] == "length": length = int(kv["value"]) - if location is None: raise ValueError("no location in external_data") - - if self.file_path is None: - if isinstance(self.tensor.device, str) and self.tensor.device.startswith("DISK:"): - self.file_path = pathlib.Path(self.tensor.device[5:]) - else: raise ValueError("onnx external_data needs the origin file path, try passing onnx file path to onnx_load") - ext_path = self.file_path.parent.joinpath(location) - if not ext_path.exists(): raise FileNotFoundError(f"external location not exists: {ext_path}") - - ext_tensor = Tensor(ext_path) - obj["raw_data"] = ext_tensor[offset:offset+length] if length is not None else ext_tensor[offset:] - obj["data_location"] = 0 - - # parse tensor - to_dtype = dtype_fallback(true_dtype := OnnxDataType(obj['data_type']).to_dtype(), "buffer parse") - shape = tuple(obj['dims']) - present_fields = [field for field in ['float_data', 'int32_data', 'int64_data', 'double_data', 'uint64_data', 'raw_data'] if field in obj] - assert len(present_fields) == 1, f"only 1 data field is allowed from {obj=}" - data = obj[present_fields[0]] - if not isinstance(data, Tensor): - obj["parsed_tensor"] = Tensor(data, dtype=to_dtype).reshape(shape) - return obj - assert isinstance(data, Tensor) and data.dtype == dtypes.uint8, data - data = data.bitcast(true_dtype).reshape(shape) - data = data.to(Device.DEFAULT) if true_dtype is to_dtype else data.to("cpu").cast(to_dtype).to(Device.DEFAULT) - # const folding - if shape == (): - if data.dtype == dtypes.float16 and sys.version_info < (3, 12): data = data.cast(dtypes.float32) - data = Tensor(data.item(), dtype=to_dtype).reshape(shape) - obj["parsed_tensor"] = data - return obj - - def _parse_AttributeProto(self) -> dict: - obj: dict[str, Any] = {"floats": [], "ints": [], "strings": []} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["name"] = self.reader.read_string() - case 2: obj["f"] = self.reader.read_float() - case 3: obj["i"] = self.reader.read_int64() - case 4: obj["s"] = self.reader.read_bytes().data().tobytes().decode("utf8") - case 5: obj["t"] = self._parse_TensorProto()['parsed_tensor'] - case 6: obj["g"] = OnnxRunner._from_subgraph(self._parse_GraphProto()) - case 7: obj["floats"].append(self.reader.read_float()) - case 8: obj["ints"].append(self.reader.read_int64()) - case 9: obj["strings"].append(self.reader.read_bytes().data().tobytes().decode("utf8")) - case 20: obj["type"] = self.reader.read_int64() - case _: self.reader.skip_field(wire_type) - obj["floats"], obj["ints"], obj["strings"] = tuple(obj["floats"]), tuple(obj["ints"]), tuple(obj["strings"]) - return obj - - def _parse_ValueInfoProto(self) -> dict: - obj: dict[str, Any] = {} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["name"] = self.reader.read_string() - case 2: obj["type"] = self._parse_TypeProto() - case _: self.reader.skip_field(wire_type) - - # parse type - if "type" not in obj: return {**obj, "parsed_type": None} - type_obj = obj["type"] - if is_optional := "optional_type" in type_obj: type_obj = type_obj["optional_type"]["elem_type"] - if is_sequence := "sequence_type" in type_obj: type_obj = type_obj["sequence_type"]["elem_type"] - assert "tensor_type" in type_obj, type_obj - shape_dims = type_obj['tensor_type'].get('shape', {}).get('dim', []) - obj['parsed_type'] = OnnxValue(tuple(d.get('dim_param') or d.get('dim_value') for d in shape_dims), - OnnxDataType(type_obj['tensor_type']['elem_type']).to_dtype(), is_optional, is_sequence) - return obj - - def _parse_TypeProto(self) -> dict: - obj: dict[str, Any] = {} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["tensor_type"] = self._parse_TypeProtoTensor() - case 4: obj["sequence_type"] = self._parse_TypeProtoSequence() - case 9: obj["optional_type"] = self._parse_TypeProtoOptional() - case _: self.reader.skip_field(wire_type) - return obj - - def _parse_TypeProtoTensor(self) -> dict: - obj: dict[str, Any] = {} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["elem_type"] = self.reader.read_int64() - case 2: obj["shape"] = self._parse_TensorShapeProto() - case _: self.reader.skip_field(wire_type) - return obj - - def _parse_TypeProtoSequence(self) -> dict: - obj = {} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["elem_type"] = self._parse_TypeProto() - case _: self.reader.skip_field(wire_type) - return obj - - def _parse_TypeProtoOptional(self) -> dict: - obj = {} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["elem_type"] = self._parse_TypeProto() - case _: self.reader.skip_field(wire_type) - return obj - - def _parse_TensorShapeProto(self) -> dict: - obj: dict[str, Any] = {"dim": []} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["dim"].append(self._parse_TensorShapeProtoDimension()) - case _: self.reader.skip_field(wire_type) - return obj - - def _parse_TensorShapeProtoDimension(self) -> dict: - obj: dict[str, Any] = {} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["dim_value"] = self.reader.read_int64() - case 2: obj["dim_param"] = self.reader.read_string() - case _: self.reader.skip_field(wire_type) - return obj - - def _parse_StringStringEntryProto(self) -> dict: - obj: dict[str, Any] = {} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["key"] = self.reader.read_string() - case 2: obj["value"] = self.reader.read_string() - case _: self.reader.skip_field(wire_type) - return obj - - def _parse_OperatorSetIdProto(self) -> dict: - obj: dict[str, Any] = {} - for fid, wire_type in self._parse_message(self._decode_end_pos()): - match fid: - case 1: obj["domain"] = self.reader.read_string() - case 2: obj["version"] = self.reader.read_int64() - case _: self.reader.skip_field(wire_type) - return obj - -# ***** python const ***** -required_input_python_consts: dict[str, tuple[int, ...]] = { - "Tile": (1,), "Range": (0,1,2), "Expand": (1,), "Reshape": (1,), "Squeeze": (1,), "Unsqueeze": (1,), "Trilu": (1,), "ConstantOfShape": (0,), - "CumSum": (1,), "TopK": (1,), "Pad": (1,2,3), "MaxUnpool": (2,), "Dropout": (1,2), "CenterCropPad": (1,), "OneHot": (1,), "Compress": (1,), - "ImageDecoder": (0,), "AffineGrid": (1,), "Resize": (1,2,3), "Upsample": (1,), "Split": (1,), "Slice": (1,2,3,4), - **{"Reduce"+r: (1,) for r in ("Max", "Min", "Sum", "Mean", "SumSquare", "Prod", "L1", "L2", "LogSum", "LogSumExp")}, - **{optim: (1,) for optim in ("Adam", "Adagrad", "Momentum")} -} - -cache_misses = 0 -@functools.cache -def _cached_to_python_const(t:Tensor): - if t.dtype == dtypes.uint8: return t.data().tobytes() - if 0 in t.shape: return [] - return t.tolist() - -# Tensor -> python value cache for parameters -def to_python_const(t:Any, op:str, idx:int) -> list[ConstType]|ConstType|bytes: - if idx not in required_input_python_consts.get(op, ()) or not isinstance(t, Tensor): return t - global cache_misses - ret = _cached_to_python_const(t) - if (info := _cached_to_python_const.cache_info()).misses > cache_misses and DEBUG >= 3: - print(f"Cache miss for {t}") - cache_misses = info.misses - return ret - -# ***** runner ****** -debug = int(getenv("DEBUGONNX", "0")) -limit = int(getenv("ONNXLIMIT", "-1")) -class OnnxRunner: - """ - `OnnxRunner` executes an ONNX model using Tinygrad. - - Args: - model_path: The ONNX model, provided as a file path (a string or Path object) or a Tensor. - """ - def __init__(self, model_path: Tensor | str | pathlib.Path): - model = OnnxPBParser(model_path, load_external_data=True).parse() - self._init_from_graph(model["graph"]) - - def _init_from_graph(self, graph: dict, is_subgraph: bool = False): - self.is_training = any(n['parsed_node'].opset_id.domain in {Domain.AI_ONNX_TRAINING, Domain.AI_ONNX_PREVIEW_TRAINING} for n in graph["node"]) - self.graph_name = graph["name"] if is_subgraph else "" - self.graph_values = {"": None, **{i["name"]: i["parsed_tensor"] for i in graph["initializer"]}} - self.graph_inputs = {i["name"]: i["parsed_type"] for i in graph["input"] if i["name"] not in self.graph_values} - self.graph_outputs = tuple(o["name"] for o in graph["output"]) - self.graph_nodes = tuple(n["parsed_node"] for n in graph["node"]) - - self.old_training = Tensor.training - Tensor.training = True if self.is_training else False - - self.variable_dims: dict[str, int] = {} - self.onnx_ops = onnx_ops - - @classmethod - def _from_subgraph(cls, graph: dict) -> "OnnxRunner": - subgraph = cls.__new__(cls) - subgraph._init_from_graph(graph, is_subgraph=True) - return subgraph - - def _parse_input(self, name: str, value: Any, spec: OnnxValue): - if spec.is_optional and value is None: return None - if spec.is_sequence: - if not isinstance(value, Sequence): raise RuntimeError(f"input {name} received {value}, expected a sequence type") - sequence = [Tensor(v, dtype=spec.dtype, requires_grad=self.is_training) if not isinstance(v, Tensor) else v for v in value] - if not all_same(tuple(t.shape for t in sequence)): raise RuntimeError(f"Shapes for input {name} sequence must be homogeneous") - if not all(t.dtype is spec.dtype for t in sequence): warnings.warn(f"Dtypes for input {name} sequence aren't all {spec.dtype}") - return sequence - dtype = _from_np_dtype(value.dtype) if is_numpy_ndarray(value) else spec.dtype - tensor = Tensor(value, dtype=dtype, requires_grad=self.is_training) if not isinstance(value, Tensor) else value - if tensor.dtype is not spec.dtype: warnings.warn(f"input {name} has mismatch on dtype. Expected {spec.dtype}, received {tensor.dtype}.") - for dim, (onnx_dim, user_dim_input) in enumerate(zip(spec.shape, tensor.shape, strict=True)): - if isinstance(onnx_dim, str): - onnx_dim = self.variable_dims[onnx_dim] if onnx_dim in self.variable_dims else self.variable_dims.setdefault(onnx_dim, int(user_dim_input)) - if user_dim_input != onnx_dim: raise RuntimeError(f"input {name} has mismatch on {dim=}. Expected {onnx_dim}, received {user_dim_input}.") - return tensor - - def _select_op(self, op:str, required_opset:OpSetId) -> types.FunctionType: - if op not in self.onnx_ops: raise NotImplementedError(f"{op=} is not supported") - # return default implementation if no opset_id is specified - if isinstance(impl := self.onnx_ops[op], types.FunctionType): return impl - # match domain and select implementation with latest compatible version - eligible_ops = {impl_opset.version:impl_fxn for impl_opset,impl_fxn in impl.items() - if impl_opset.domain == required_opset.domain and impl_opset.version <= required_opset.version} - if not eligible_ops: raise NotImplementedError(f"{op=} is not supported for domain {required_opset.domain} and version {required_opset.version}") - return eligible_ops[max(eligible_ops.keys())] - - def get_empty_input_data(self, device:str|None=None, dtype:DType|None=None) -> dict[str, Tensor]: - return {name:Tensor.empty(*spec.shape, device=device, dtype=dtype or spec.dtype) for name, spec in self.graph_inputs.items()} - - def to(self, device:str|None): - self.graph_values = {k: (v.to(device) if isinstance(v, Tensor) else v) for k,v in self.graph_values.items()} - self.graph_nodes = tuple(OnnxNode(n.op, n.opset_id, tuple(n.inputs), tuple(n.outputs), - {k: (v.to(device) if isinstance(v, (Tensor, OnnxRunner)) else v) for k,v in n.opts.items()}) - for n in self.graph_nodes) - return self - - def __call__(self, inputs:dict[str, Any], debug=debug): - for name, input_spec in self.graph_inputs.items(): - if name not in inputs: raise RuntimeError(f"Please provide input data for {name}") - self.graph_values[name] = self._parse_input(name, inputs[name], input_spec) - - for num, node in enumerate(self.graph_nodes): - inps = [to_python_const(self.graph_values[name], node.op, i) for i,name in enumerate(node.inputs)] - opts = node.opts - - # provide additional opts - if node.op == "Split" and 'num_outputs' not in opts: opts['num_outputs'] = len(node.outputs) - if node.op in {"Gradient", "If"}: opts['intermediate_tensors'] = self.graph_values - - if debug >= 1: print((f"[{self.graph_name}] " if self.graph_name else "") + f"{num}: op '{node.op}' opt {opts}") - if debug >= 2 and node.inputs: print("\tinputs:\n" + "\n".join(f"\t\t{x} - {i!r}" for x,i in zip(node.inputs, inps))) - ret = self._select_op(node.op, node.opset_id)(*inps, **opts) - ret = ret if isinstance(ret, tuple) else (ret,) - if debug >= 2: print("\toutputs:\n" + "\n".join(f"\t\t{x} - {o!r}" for x,o in zip(node.outputs, ret))) - - self.graph_values.update(dict(zip(node.outputs, ret[:len(node.outputs)], strict=True))) - - if num == limit: - Tensor.training = self.old_training - return {name:self.graph_values[name] for name in node.outputs} - Tensor.training = self.old_training - return {name:self.graph_values[name] for name in self.graph_outputs} - -#################### -##### ONNX OPS ##### -#################### -def get_onnx_ops() -> dict[str, types.FunctionType|dict[OpSetId, types.FunctionType]]: - # ***** helper functions ***** - def _resolve_const(x: Sequence[ConstType]|ConstType): return get_single_element(x) if isinstance(x, Sequence) else x - - def _axes(axes, noop_with_empty_axes): return axes or ([] if noop_with_empty_axes else None) - - # (padding_top, padding_left, ..., padding_bottom, padding_right, ...) -> (padding_left, padding_right, padding_top, padding_bottom, ...) - def _onnx_pads_to_tiny_pads(pads): return tuple(flatten(reversed(list(zip(pads, pads[len(pads)//2:]))))) - - AUTO_PAD_OPTIONS = Literal["NOTSET", "SAME_UPPER", "SAME_LOWER", "VALID"] - # (padding_height, padding_width) -> (padding_top, padding_left, padding_bottom, padding_right) - def _auto_pad(pads, auto_pad: AUTO_PAD_OPTIONS): - if auto_pad == "SAME_UPPER": return [pads[i]//2 for i in range(len(pads))] + [pads[i]-pads[i]//2 for i in range(len(pads))] - return [pads[i]-pads[i]//2 for i in range(len(pads))] + [pads[i]//2 for i in range(len(pads))] - - def _resolve_pool_pads(x:Tensor, p_, k_, d_, s_, auto_pad:AUTO_PAD_OPTIONS): - if auto_pad == "VALID": return [0]*(len(k_)*2) - i_, (s_,d_,p_) = x.shape[-len(k_):], (make_tuple(x, len(k_)*2) for x in (s_, d_, p_)) - if auto_pad == "NOTSET": return _onnx_pads_to_tiny_pads(p_ if len(p_)==len(k_)*2 else p_*2) - o_ = [((i - (1 if auto_pad in ("SAME_UPPER", "SAME_LOWER") else k)) // s + 1) for i,k,s in zip(i_, k_, s_)] - return _onnx_pads_to_tiny_pads(_auto_pad([(o-1)*s+k-i for o,i,k,s in zip(o_, i_, k_, s_)], auto_pad)) - - def _clamp_cast(x:Tensor, dtype:DType): return x.clamp(dtypes.min(dtype), dtypes.max(dtype)).cast(dtype) - - def _prepare_quantize(x:Tensor, scale:Tensor, zero_point:Tensor|int, axis=1, block_size=0): - if axis < 0: axis += x.ndim - # https://github.com/onnx/onnx/blob/main/onnx/reference/ops/op_quantize_linear.py#L31 - def reshape(val:Tensor): - if val.numel() == 1: return val - if block_size == 0: return val.reshape([val.shape[0] if dim == axis else 1 for dim in range(x.ndim)]) - return val.repeat_interleave(block_size, axis) - return (reshape(scale), reshape(zero_point) if isinstance(zero_point, Tensor) else zero_point) - - def _op_integer(op, inputs:list[Tensor], zero_points:list[Tensor], **opts): - adjusted_inputs = [inp.int() - zp for inp, zp in zip(inputs, zero_points)] - return op(*adjusted_inputs, **opts) - - def _qlinearop_quantized(op, inputs:list[Tensor], zero_points:list[Tensor], scales:list[Tensor], out_scale:Tensor, out_zero_point:Tensor, **opts): - # op execution is done in quantized int - out = _op_integer(op, inputs, zero_points, **opts) - assert dtypes.is_int(out.dtype), "quantized op should've done math in int" - out_quantized = (out * prod(scales) / out_scale).round() + out_zero_point - return _clamp_cast(out_quantized, out_zero_point.dtype) - - def _qlinearop_float(op, inputs:list[Tensor], zero_points:list[Tensor], scales:list[Tensor], out_scale:Tensor, out_zero_point:Tensor, **opts): - # op execution is done in float32 - dequantized_inputs = [(inp.int() - zp) * scale for inp, zp, scale in zip(inputs, zero_points, scales)] - out = op(*dequantized_inputs, **opts) - assert dtypes.is_float(out.dtype), "op should've done math in float" - out_quantized = (out / out_scale).round() + out_zero_point - return _clamp_cast(out_quantized, out_zero_point.dtype) - - def _onnx_training(input_group_size): - def __decorator(func): - def ___wrapper(R:Tensor, T:int, *inputs:Tensor, **kwargs): - R = R.detach() - groups = len(inputs) // input_group_size - ret = [func(R, T, *inps, **kwargs) for inps in (inputs[i::groups] for i in range(groups))] - return tuple(flatten(zip(*ret))) - return ___wrapper - return __decorator - - # ***** Property/Graph Ops ***** - def If(condition:Tensor, else_branch:OnnxRunner, then_branch:OnnxRunner, intermediate_tensors:dict[str, Tensor]): - def run_branch(branch:OnnxRunner): - branch.graph_values.update(intermediate_tensors) - out = branch({k:intermediate_tensors[k] for k in branch.graph_inputs.keys()}) - # dereference intermediate tensors so Buffer can be deallocated - for k in intermediate_tensors: del branch.graph_values[k] - return out - # both branch must be ran before the condition can be evaluated - else_out, then_out = run_branch(else_branch), run_branch(then_branch) - assert len(else_out) == len(then_out), f"else_out and then_out must have the same number of outputs: {len(else_out)} != {len(then_out)}" - # can use where op when output shape is the same - if all(t.shape == e.shape for t,e in zip(then_out.values(), else_out.values())): - return tuple(condition.where(t,e) for t,e in zip(then_out.values(), else_out.values())) - # otherwise, use condition to select the output in python - cond = _resolve_const(_cached_to_python_const(condition)) - return tuple(t if cond else e for t,e in zip(then_out.values(), else_out.values())) - - def Identity(x:Tensor): return x - def Constant(sparse_value:Tensor|None=None, value:Tensor|None=None, value_float:float|None=None, value_floats:list[float]|None=None, - value_int:int|None=None, value_ints:list[int]|None=None, value_string:str|None=None, value_strings:list[str]|None=None): - if value is not None: return value - if value_float is not None: return Tensor(value_float, dtype=dtypes.float32, requires_grad=False) - if value_floats is not None: return Tensor(list(value_floats), dtype=dtypes.float32, requires_grad=False) - if value_int is not None: return Tensor(value_int, dtype=dtypes.int64, requires_grad=False) - if value_ints is not None: return Tensor(list(value_ints), dtype=dtypes.int64, requires_grad=False) - if value_string is not None or value_strings is not None or sparse_value is not None: - raise NotImplementedError('Constant OP not implemented for value_string, value_strings and sparse_value') - - def Range(start:float|int|list[float|int], limit:float|int|list[float|int], delta:float|int|list[float|int]): - return Tensor.arange(start=_resolve_const(start), stop=_resolve_const(limit), step=_resolve_const(delta)) - - def ImageDecoder(encoded_stream:bytes, pixel_format="RGB"): - try: import PIL.Image - except ImportError as e: raise ImportError("Pillow must be installed for the ImageDecoder operator") from e - img = PIL.Image.open(io.BytesIO(encoded_stream)) - if pixel_format == "BGR": return Tensor(img.tobytes(), dtype=dtypes.uint8).reshape(*img.size, 3).flip(-1) - if pixel_format == "RGB": return Tensor(img.tobytes(), dtype=dtypes.uint8).reshape(*img.size, 3) - if pixel_format == "Grayscale": return Tensor(img.convert("L").tobytes(), dtype=dtypes.uint8).reshape(*img.size, 1) - raise ValueError(f"pixel_format={pixel_format!r} is not supported.") - - def EyeLike(x:Tensor, dtype:int|None=None, k:int=0): - ret = Tensor.eye(cast(int, min(x.shape)), dtype=dtype_fallback(OnnxDataType(dtype).to_dtype(), "EyeLike op") if dtype is not None else x.dtype) - return ret if x.size(0) == x.size(1) else ret.pad(tuple(None if d == ret.size(0) else (k, d-ret.shape[0]-k) for d in x.shape)) - - def OptionalHasElement(x:Tensor|None=None): return Tensor(x is not None and x.numel() > 0) - def OptionalGetElement(x:Tensor|None=None): return x if x is not None else Tensor([]) - def ConstantOfShape(shape:list[int], value:Tensor|None=None): - if value is None: value = Tensor(0, dtype=dtypes.float32) - if shape == [0]: return Tensor([], dtype=value.dtype) - return value.expand(shape) - - def Size(data:Tensor): return data.numel() - def Shape(data:Tensor, end:int|None=None, start:int=0): return Tensor(data.shape[start:end], dtype=dtypes.int64) - - # ***** Unary Ops (math) ***** - def Not(x:Tensor): return x.logical_not() - def Clip(x: Tensor, min:Tensor|None=None, max:Tensor|None=None): return x if min is None and max is None else x.clip(min, max) # noqa: A002 # pylint: disable=redefined-builtin - def IsInf(x:Tensor, detect_negative:int=1, detect_positive:int=1): return x.isinf(bool(detect_positive), bool(detect_negative)) - - # ***** Unary Ops (activation) ***** - def softmax_1(x:Tensor, axis:int=1): return x.softmax(axis) - def softmax_13(x:Tensor, axis:int=-1): return x.softmax(axis) - Softmax = {OpSetId(Domain.ONNX, 1):softmax_1, OpSetId(Domain.ONNX, 13):softmax_13} - def HardSigmoid(x:Tensor, alpha:float=0.2, beta:float=0.5): return (alpha*x + beta).clip(0, 1) - def Gelu(x:Tensor, approximate:str|None=None): return x.gelu() if approximate == "tanh" else 0.5 * x * (1 + (x/math.sqrt(2)).erf()) - def BiasGelu(x: Tensor, bias: Tensor, approximate: str | None = None) -> Tensor: return Gelu(x + bias, approximate) - def FastGelu(x:Tensor, bias:Tensor|None=None): return (x + bias).gelu() if bias is not None else x.gelu() # this is tanh approximated - def PRelu(X:Tensor, slope:Tensor): return (X > 0).where(X, X * slope) - def LeakyRelu(X:Tensor, alpha:float=0.01): return X.leaky_relu(alpha) - def ThresholdedRelu(X:Tensor, alpha:float=1.0): return (X > alpha).where(X, 0) - def LogSoftmax(x: Tensor, axis:int=-1): return x.log_softmax(axis) - def Binarizer(x:Tensor, threshold:float=0.0): return (x > threshold).float() - - # ***** Unary Ops (broadcasted) ***** - def Add(x:Tensor,y:Tensor, broadcast=None, axis=None): return x + y - def Sub(x:Tensor|int,y:Tensor): return x - y # some test has input as int - def Div(x:Tensor,y:Tensor): return x.div(y, rounding_mode='trunc' if dtypes.is_int(x.dtype) else None) - def Less(x:Tensor,y:Tensor): return x < y - def LessOrEqual(x:Tensor,y:Tensor): return x <= y - def Greater(x:Tensor,y:Tensor): return x > y - def GreaterOrEqual(x:Tensor,y:Tensor): return x >= y - def Equal(x:Tensor,y:Tensor): return x == y - def And(x:Tensor,y:Tensor): return (x==y).where(x, False) - def Or(x:Tensor,y:Tensor): return (x==y).where(x, True) - def Xor(x:Tensor,y:Tensor): return x.bool().bitwise_xor(y.bool()) - def BitwiseAnd(x:Tensor,y:Tensor): return x & y - def BitwiseOr(x:Tensor,y:Tensor): return x | y - def BitwiseXor(x:Tensor,y:Tensor): return x ^ y - def BitwiseNot(x:Tensor): return ~x - def Mod(x:Tensor,y:Tensor,fmod=0): return x - x.div(y, rounding_mode="trunc") * y if fmod else x % y - - # ***** Casting Ops ***** - # TODO: saturate - def Cast(x:Tensor, to:int, saturate:int=1): return x.cast(dtype_fallback(OnnxDataType(to).to_dtype(), "Cast op")) - def CastLike(x:Tensor, target_type:Tensor, saturate:int=1): return x.cast(target_type.dtype) - - # ***** Reduce Ops ***** - def Max(*data_0:Tensor): return functools.reduce(Tensor.maximum, data_0) - def Min(*data_0:Tensor): return functools.reduce(Tensor.minimum, data_0) - def Sum(*data_0:Tensor): return functools.reduce(Tensor.add, data_0) - def Mean(*data_0:Tensor): return Sum(*data_0) / len(data_0) - def ReduceMax(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return data.max(_axes(axes, noop_with_empty_axes), keepdim=keepdims) - def ReduceMin(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return data.min(_axes(axes, noop_with_empty_axes), keepdim=keepdims) - def ReduceSum(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return data.sum(_axes(axes, noop_with_empty_axes), keepdim=keepdims) - def ReduceMean(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return data.mean(_axes(axes, noop_with_empty_axes), keepdim=keepdims) - def ReduceSumSquare(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return ReduceSum(data.square(), axes, keepdims, noop_with_empty_axes) - def ReduceProd(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return data.prod(_axes(axes, noop_with_empty_axes), keepdim=keepdims) - def ReduceL1(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return ReduceSum(data.abs(), axes, keepdims, noop_with_empty_axes) - def ReduceL2(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return ReduceSumSquare(data, axes, keepdims, noop_with_empty_axes).sqrt() - def ReduceLogSum(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return ReduceSum(data, axes, keepdims, noop_with_empty_axes).log() - def ReduceLogSumExp(data:Tensor, axes:list[int]|None=None, keepdims:int=1, noop_with_empty_axes:int=0): - return ReduceSum(data.exp(), axes, keepdims, noop_with_empty_axes).log() - def ArgMax(x:Tensor, axis:int=0, keepdims:int=1, select_last_index:int=0): - if select_last_index: return ((x.shape[axis]-1) - x.flip(axis).argmax(axis, keepdim=keepdims)).cast(dtypes.int64) - return x.argmax(axis, keepdim=keepdims).cast(dtypes.int64) - def ArgMin(x, axis:int=0, keepdims:int=1, select_last_index:int=0): - return ArgMax(-x, axis=axis, keepdims=keepdims, select_last_index=select_last_index) - - # ***** Movement Ops ***** - def Reshape(data:Tensor, shape:list[int], allowzero:int=0): - return data.reshape([x if x != 0 else (0 if allowzero else data.shape[i]) for i,x in enumerate(shape)]) - def Flatten(x:Tensor, axis:int=1): return x.reshape(prod(x.shape[0:axis]), -1) - def Expand(x:Tensor, shape:list[int]): return x.expand(_broadcast_shape(x.shape, tuple(shape))) - def Shrink(x:Tensor, bias:float=0.0, lambd:float=0.5): return (x < -lambd)*(x+bias) + (x > lambd)*(x-bias) - def Transpose(x:Tensor, perm:list[int]|None=None): return x.permute(order=perm or list(range(x.ndim)[::-1])) - - def Squeeze(data:Tensor, axes:list[int]|None=None): - return data.squeeze() if axes is None else functools.reduce(lambda d, dim: d.squeeze(dim), sorted(axes, reverse=True), data) - def Unsqueeze(data:Tensor, axes:list[int]): return functools.reduce(lambda d, dim: d.unsqueeze(dim), sorted(axes), data) - - def Tile(x:Tensor, repeats:list[int]): return x.repeat(repeats) - def Concat(*xs:Tensor, axis:int): return Tensor.cat(*xs, dim=axis) - def Slice(data:Tensor, starts:list[int], ends:list[int], axes:list[int]|None=None, steps:list[int]|None=None): - axes = axes or list(range(data.ndim)) - steps = steps or [1]*data.ndim - slices = [slice(0,x,1) for x in data.shape] - for i, axis in enumerate(axes): slices[axis] = slice(starts[i], ends[i], steps[i]) - return data[tuple(slices)] - - def Split(data:Tensor, split:list[int]|None=None, num_outputs:int=0, axis:int=0): - sz = data.shape[axis] - if split is None: split = [sz // num_outputs + (1 if i < sz % num_outputs else 0) for i in range(num_outputs)] - return data.split(split, axis) - - def Pad(x:Tensor, pads:list[int], constant_value:ConstType|None=None, axes:list[int]|None=None, - mode:Literal["constant", "reflect", "edge", "wrap"]="constant", value=0): - value = constant_value or value - axes = axes or list(range(x.ndim)) - real_pads = [0] * (x.ndim*2) - for i,axis in enumerate(axes): real_pads[axis%x.ndim], real_pads[axis%x.ndim+x.ndim] = pads[i], pads[i+len(axes)] - return x.pad(padding=_onnx_pads_to_tiny_pads(real_pads), mode={"edge":"replicate", "wrap":"circular"}.get(mode, mode), value=value) - - def CenterCropPad(t:Tensor, shape:list[int], axes:list[int]|None=None): - shrink_arg:list[None|tuple[int,int]] = [None] * t.ndim - pad_arg:list[None|tuple[int,int]] = [None] * t.ndim - for s, x in zip(shape, axes or range(t.ndim)): - tx = t.shape[x] - if s < tx: shrink_arg[x] = (tx//2 - (s+1)//2, tx//2 + s//2) - elif s > tx: pad_arg[x] = ((s-tx)//2, (s-tx+1)//2) - return t.shrink(tuple(shrink_arg)).pad(tuple(pad_arg)) - - # ***** Processing Ops ***** - def AveragePool(X: Tensor, kernel_shape:list[int], auto_pad:AUTO_PAD_OPTIONS="NOTSET", ceil_mode:int=0, count_include_pad:int=0, - dilations:list[int]|int=1, pads:list[int]|int=0, strides:list[int]|int=1): - pool_pads = _resolve_pool_pads(X, pads, kernel_shape, dilations, strides, auto_pad) - return X.avg_pool2d(tuple(kernel_shape), strides, dilations, pool_pads, ceil_mode=ceil_mode, count_include_pad=count_include_pad) - - def MaxPool(X: Tensor, kernel_shape:list[int], auto_pad:AUTO_PAD_OPTIONS="NOTSET", ceil_mode:int=0, dilations:list[int]|int=1, pads:list[int]|int=0, - storage_order:int=0, strides:list[int]|int=1): - pool_pads = _resolve_pool_pads(X, pads, kernel_shape, dilations, strides, auto_pad) - out = X.max_pool2d(tuple(kernel_shape), strides, dilations, pool_pads, ceil_mode=ceil_mode, return_indices=True) - ret, idx = cast(tuple[Tensor, Tensor], out) - return ret, idx.transpose(-2, -1).cast(dtypes.int64) if storage_order else idx.cast(dtypes.int64) - - def Conv(X: Tensor, W: Tensor, B:Tensor|None=None, auto_pad:AUTO_PAD_OPTIONS="NOTSET", dilations:list[int]|int=1, group:int=1, - kernel_shape:list[int]|None=None, pads:list[int]|int=0, strides:list[int]|int=1): - return X.conv2d(W, B, stride=strides, groups=group, dilation=dilations, - padding=_resolve_pool_pads(X, pads, kernel_shape or W.shape[2:], dilations, strides, auto_pad)) - - def ConvTranspose(X: Tensor, W: Tensor, B:Tensor|None=None, auto_pad:AUTO_PAD_OPTIONS="NOTSET", dilations:list[int]|int=1, group:int=1, - kernel_shape:list[int]|None=None, pads:list[int]|None=None, output_shape:list[int]|None=None, output_padding:list[int]|int=0, - strides:list[int]|int=1): - input_shape_, kernel_shape_ = X.shape[2:], (kernel_shape or W.shape[2:]) - strides_, dilations_, output_padding_ = (make_tuple(x, len(input_shape_)) for x in (strides, dilations, output_padding)) - if output_shape is not None: # we pad according to output_shape - pads = _auto_pad([s_*(i-1) + op_ + ((k_-1)*d_+1) - os for s_,i,op_,k_,d_,os in - zip(strides_, input_shape_, output_padding_, kernel_shape_, dilations_, output_shape)], auto_pad) - if pads is None: # we generate pads - output_shape = output_shape or [X.shape[i+2] * strides_[i] for i in range(len(strides_))] - pads = [strides_[i]*(input_shape_[i]-1)+output_padding_[i]+((kernel_shape_[i]-1)*dilations_[i]+1)-output_shape[i] - for i in range(len(input_shape_))] - pads = _auto_pad(pads, auto_pad) if auto_pad != "NOTSET" else [0] * len(input_shape_) * 2 - pads = _onnx_pads_to_tiny_pads(pads) - return X.conv_transpose2d(W, B, group, strides_, dilations_, pads, output_padding_) - - def MaxUnpool(xT: Tensor, xI: Tensor, outshape: list[int]|None=None, kernel_shape:list[int]|None=None, pads:list[int]|int=0, - strides:list[int]|int=1): - if kernel_shape is None: kernel_shape = [] - pads_: int | tuple[int, ...] = tuple(pads) if isinstance(pads, list) else pads - return Tensor.max_unpool2d(xT, xI, tuple(kernel_shape), strides, 1, pads_, outshape if outshape is None else tuple(outshape)) - - def GlobalAveragePool(X:Tensor): return X.mean(axis=tuple(range(2, X.ndim)), keepdim=True) - def GlobalMaxPool(X:Tensor): return X.max(axis=tuple(range(2, X.ndim)), keepdim=True) - - def Gemm(A:Tensor, B:Tensor, C:Tensor|None=None, alpha:float=1.0, beta:float=1.0, transA:int=0, transB:int=0, broadcast=0): - ret = alpha * (A.transpose(transA) @ B.transpose(transB)) - if C is not None: ret = ret + beta * (C if broadcast == 0 else C.reshape([-1 if i < len(C.shape) else 1 for i in range(ret.ndim)][::-1])) - return ret - - def Einsum(*Inputs:list[Tensor], equation:str): return Tensor.einsum(equation, *Inputs) - - def CumSum(X:Tensor, axis:int|list[int], exclusive:int=0, reverse:int=0): - axis = X._resolve_dim(_resolve_const(axis)) - if reverse: X = X.flip(axis) - if exclusive: X = X.pad(tuple((1,0) if i == axis else None for i in range(X.ndim)))\ - .shrink(tuple((0,X.shape[axis]) if i == axis else None for i in range(X.ndim))) - return X.cumsum(axis).flip(axis) if reverse else X.cumsum(axis) - - def Trilu(x:Tensor, k:int|list[int]=0, upper:int=1): - k_ = _resolve_const(k) - return x.triu(k_) if upper else x.tril(k_) - - def Resize(X:Tensor, roi:list[float]|None=None, scales:list[float]|None=None, sizes:list[int]|None=None, antialias:int=0, - axes:list[int]|None=None, coordinate_transformation_mode:str='half_pixel', cubic_coeff_a:float=-0.75, exclude_outside:int=0, - extrapolation_value:float=0.0, keep_aspect_ratio_policy:str='stretch', mode:str='nearest', nearest_mode:str='round_prefer_floor'): - def _apply_transformation(input_sz, output_sz, scale_dim, mode): - index = Tensor.arange(output_sz, requires_grad=False, device=X.device) - if mode == "half_pixel": return (index + 0.5) / scale_dim - 0.5 - if mode == "align_corners": return index * (input_sz - 1) / (output_sz - 1) if output_sz != 1 else Tensor.zeros_like(index) - if mode == "asymmetric": return index / scale_dim - if mode == "pytorch_half_pixel": return ((index + 0.5) / scale_dim - 0.5) if output_sz != 1 else Tensor.zeros_like(index) - if mode == "half_pixel_symmetric": - output_dim_scaled = input_sz * scale_dim - return (input_sz / 2) * (1 - (output_sz / output_dim_scaled)) + (index + 0.5) / scale_dim - 0.5 - raise ValueError(f"invalid {coordinate_transformation_mode=}") - - if antialias: raise NotImplementedError("antialias is not implemented") - axes = axes or list(range(X.ndim)) - perm = [a for a in range(len(X.shape)) if a not in axes] + list(axes) - # we pre-permute the axes and permute back after resize - # the permute aligns X's axes to scales, sizes, and roi - X = X.permute(*perm) - - input_shape = cast(tuple[int, ...], X.shape[2:]) - if scales is not None: assert all(sc==1 for sc in scales[:-len(input_shape)]), "resizing batch_size dim or channel dim not supported" - if sizes is not None: assert tuple(sizes[:-2]) == tuple(X.shape[X.ndim-len(sizes):-2]), "resizing batch_size dim or channel dim not supported" - - scales, sizes = (None if scales is None else scales[-len(input_shape):]), (None if sizes is None else sizes[-len(input_shape):]) - if sizes is not None: - if keep_aspect_ratio_policy in ["not_larger", "not_smaller"]: - scale_fxn = min if keep_aspect_ratio_policy == "not_larger" else max - scale = scale_fxn(sz / sh for sz,sh in zip(sizes, input_shape)) - sizes, scales = [int(scale * sh + 0.5) for sh in input_shape], [scale]*len(input_shape) - else: scales = [sz / sh for sz, sh in zip(sizes, input_shape)] - else: - assert scales is not None, "either sizes or scales must be provided" - sizes = [int(sc * sh) for sc, sh in zip(scales, input_shape)] - - if all(sz == sh for sz, sh in zip(sizes, input_shape)): return X.permute(*argsort(perm)) if perm else X - - indexes = [] - for input_sz, output_sz, scale in zip(input_shape, sizes, scales): - indexes.append(_apply_transformation(input_sz, output_sz, scale, coordinate_transformation_mode)) - - if mode in ["nearest", "linear"]: indexes = [idx.clip(0, sz-1) for idx, sz in zip(indexes, input_shape)] - - if mode == "nearest": - mode_operations = { - "round_prefer_floor": lambda idx: (idx - 0.5).ceil(), - "round_prefer_ceil": lambda idx: (idx + 0.5).floor(), - "floor": lambda idx: idx.floor(), - "ceil": lambda idx: idx.ceil() - } - if nearest_mode not in mode_operations: raise ValueError(f"invalid {nearest_mode=}") - indexes = [mode_operations[nearest_mode](idx).int() for idx in indexes] - X = X[(..., *Tensor.meshgrid(*indexes))] - - if mode == "linear": - expand = list(X.shape) - for i in range(-len(sizes), 0): - reshape, index = [1] * X.ndim, indexes[i] - reshape[i] = expand[i] = sizes[i] - low, high, perc = [y.reshape(reshape).expand(expand) for y in (index.floor().int(), index.ceil().int(), index - index.floor())] - X = X.gather(i, low).lerp(X.gather(i, high), perc) - - if mode == "cubic": - A = cubic_coeff_a - - # Keys weights - # see piecewise function in: https://en.wikipedia.org/wiki/Bicubic_interpolation#Bicubic_convolution_algorithm - def W0_1(x:Tensor): return polyN(x, [A + 2, -(A + 3), 0, 1]) - def W1_2(x: Tensor): return polyN(x, [A, -5 * A, 8 * A, -4 * A]) - - expand = list(X.shape) - for i in range(-len(sizes), 0): - input_sz = cast(int, X.shape[i]) - reshape, index = [1] * X.ndim, indexes[i] - reshape[i] = expand[i] = sizes[i] - - p = index.floor().int() - ratio = index - p # in [0, 1] - - # Neighbor indices - idx0, idx1, idx2, idx3 = [p + d for d in [-1, 0, 1, 2]] - # Weights of distance from index and neighbor indices - c0, c1, c2, c3 = W1_2(ratio+1), W0_1(ratio), W0_1(-(ratio-1)), W1_2(-(ratio-2)) - - if exclude_outside: - c0 = ((idx0 >= 0) & (idx0 < input_sz)).where(c0, 0) - c1 = ((idx1 >= 0) & (idx1 < input_sz)).where(c1, 0) - c2 = ((idx2 >= 0) & (idx2 < input_sz)).where(c2, 0) - c3 = ((idx3 >= 0) & (idx3 < input_sz)).where(c3, 0) - - total = c0 + c1 + c2 + c3 - c0, c1, c2, c3 = c0 / (total + 1e-9), c1 / (total + 1e-9), c2 / (total + 1e-9), c3 / (total + 1e-9) - - # Reshape and expand - expanded_indices = [y.clip(0, input_sz - 1).reshape(reshape).expand(expand) for y in [idx0, idx1, idx2, idx3]] - expanded_coeffs = [y.reshape(reshape).expand(expand) for y in [c0, c1, c2, c3]] - - # Gather values and apply coefficients - gathered_values = [X.gather(i, idx) for idx in expanded_indices] - X = sum(v * c for v, c in zip(gathered_values, expanded_coeffs)) - return X.permute(*argsort(perm)) if perm else X - def Upsample(X, scales, mode): return Resize(X=X, scales=scales, mode=mode) # deprecated - - def TopK(X:Tensor, K:int|list[int], axis:int=-1, largest:int=1, sorted:int=1): # noqa: A002 # pylint: disable=redefined-builtin - val, idx = X.topk(_resolve_const(K), axis, bool(largest), bool(sorted)) - return val, idx.cast(dtypes.int64) - - # ***** Neural Network Ops ***** - def BatchNormalization(X:Tensor, scale:Tensor, B:Tensor, input_mean:Tensor, input_var:Tensor, epsilon:float=1e-05, momentum:float=0.9, - training_mode:int=0, spatial=1, is_test=0): - if training_mode: - x_detached = X.detach() - current_mean = x_detached.mean(axis=(0,2,3)) - y = (x_detached - current_mean.reshape(shape=[1, -1, 1, 1])) - current_var = (y*y).mean(axis=(0,2,3)) - current_invstd = current_var.add(epsilon).rsqrt() - - running_mean = input_mean * momentum + current_mean * (1 - momentum) - running_var = input_var * momentum + current_var * (1 - momentum) - - return X.batchnorm(scale, B, current_mean, current_invstd), running_mean, running_var - return X.batchnorm(scale, B, input_mean, (input_var + epsilon).rsqrt()) - def GroupNormalization(x:Tensor, scale:Tensor, bias:Tensor, num_groups:int, epsilon:float=1e-05): - x = x.reshape(x.shape[0], num_groups, -1).layernorm(eps=epsilon).reshape(x.shape) - return x * scale.reshape(1, -1, *[1] * (x.ndim-2)) + bias.reshape(1, -1, *[1] * (x.ndim-2)) - def InstanceNormalization(x:Tensor, scale:Tensor, bias:Tensor, epsilon:float=1e-05): - return GroupNormalization(x, scale, bias, num_groups=cast(int, x.shape[1]), epsilon=epsilon) - def LayerNormalization(x:Tensor, scale:Tensor, bias:Tensor, axis:int=-1, epsilon:float=1e-05, stash_type:int=1): - assert stash_type == 1, "only float32 is supported" - axes = tuple(i for i in range(axis if axis >= 0 else x.ndim + axis, x.ndim)) - mean = x.mean(axis=axes, keepdim=True) - return x.layernorm(axes, epsilon).mul(scale).add(bias), mean, (x.sub(mean)).square().mean(axis=axes, keepdim=True).add(epsilon).rsqrt() - def SkipLayerNormalization(x:Tensor, skip:Tensor, gamma:Tensor, beta:Tensor|None=None, bias:Tensor|None=None, epsilon:float=1e-12): - x = x + skip - if bias is not None: x = x + bias - ret = x.layernorm(eps=epsilon) * gamma - if beta is not None: ret = ret + beta - return ret, None, None, x - def EmbedLayerNormalization(input_ids: Tensor, segment_ids:Tensor, word_embedding:Tensor, position_embedding:Tensor, - segment_embedding:Tensor, gamma=None, beta=None, mask:Tensor|None=None, - position_ids:Tensor|None=None, epsilon=1e-12, mask_index_type=0): - # https://github.com/microsoft/onnxruntime/blob/main/docs/ContribOperators.md#com.microsoft.EmbedLayerNormalization - assert (segment_ids is None) is (segment_embedding is None) - assert mask is None and not mask_index_type, "functionality not supported yet" # TODO - input_shape = input_ids.shape - seq_length = input_shape[1] - compute_seg_emb = (segment_embedding is not None and segment_ids is not None) - vocab_size, max_position_embeddings = word_embedding.shape[0], position_embedding.shape[0] - type_vocab_size = (segment_embedding.shape[0] if compute_seg_emb else None) - - def embedding(x:Tensor, vocab_size, weight:Tensor) -> Tensor: - return x.unsqueeze(-1).expand(*x.shape, vocab_size)._one_hot_along_dim(vocab_size) @ weight - - # bert embedding layer - if position_ids is None: position_ids = Tensor.arange(seq_length, requires_grad=False).unsqueeze(0).expand(*input_shape) - wrd_embedding_res = embedding(input_ids, vocab_size, word_embedding) - pos_embedding_res = embedding(position_ids, max_position_embeddings, position_embedding) - seg_embedding_res = embedding(segment_ids, type_vocab_size, segment_embedding) if compute_seg_emb else None - - embedding_sum = wrd_embedding_res + pos_embedding_res - if seg_embedding_res is not None: embedding_sum = embedding_sum + seg_embedding_res - out = embedding_sum.layernorm(eps=epsilon) * gamma + beta - return out, None, embedding_sum - def MeanVarianceNormalization(x:Tensor, axis:list[int]|None=None): - if axis is None: axis = [0,2,3] - return (x - x.mean(axis, keepdim=True)) / (x.std(axis, keepdim=True, correction=0) + 1e-9) - - def OneHot(indices:Tensor, depth:float|int|list[int|float], values:Tensor, axis:int=-1): - # Scalar or Rank 1 tensor containing exactly one element - depth = int(_resolve_const(depth)) - indices = indices.int() - indices = (indices < 0).where(indices+depth, indices) - return indices.unsqueeze(axis)._one_hot_along_dim(depth, dim=axis).where(values[1], values[0]) - - def DepthToSpace(X:Tensor, blocksize:int, mode:str="DCR"): - return X.rearrange("b (c h1 w1) h w -> b c (h h1) (w w1)" if mode=="CRD" else "b (h1 w1 c) h w -> b c (h h1) (w w1)", h1=blocksize, w1=blocksize) - def SpaceToDepth(X:Tensor, blocksize:int): - return X.rearrange("b c (h h1) (w w1) -> b (h1 w1 c) h w", h1=blocksize, w1=blocksize) - - # Reimplemented here because you need legacy RNG for passing ONNX tests. - def dropout_7(data:Tensor, ratio:float=0.5, training_mode:bool=False, seed:int|None=None): - import numpy as np - if not training_mode: return data, data.full_like(True, dtype=dtypes.bool) - if seed is not None: - rand = Tensor(np.random.RandomState(seed).random(cast(tuple[int,...], data.shape)), requires_grad=False, dtype=data.dtype, device=data.device) - else: - rand = data.rand_like(requires_grad=False) - mask = rand >= ratio - return data * mask / (1.0 - ratio), mask - # 6 with 'is_test' needed for https://github.com/MTlab/onnx2caffe/raw/refs/heads/master/model/MobileNetV2.onnx - def dropout_6(data:Tensor, ratio:float=0.5, is_test=0): return dropout_7(data, ratio, training_mode=not is_test) - Dropout = {OpSetId(Domain.ONNX, 6):dropout_6, OpSetId(Domain.ONNX, 7):dropout_7} - - def LRN(x:Tensor, size:int, alpha:float=1e-4, beta:float=0.75, bias:float=1.0): - pooled_x = (x**2).rearrange('b c h w -> b 1 c (h w)').pad((0,0,(size-1)//2, size//2)).avg_pool2d((size, 1), 1) - return x / (pooled_x.reshape(x.shape) * alpha + bias).pow(beta) - - def NegativeLogLikelihoodLoss(x:Tensor, target:Tensor, weight:Tensor|None=None, ignore_index:int|None=None, reduction:ReductionStr="mean"): - return x.nll_loss(target, weight, ignore_index, reduction) - def SoftmaxCrossEntropyLoss(scores:Tensor, labels:Tensor, weights:Tensor|None=None, ignore_index:int|None=None, reduction:ReductionStr="mean"): - log_probs = scores.log_softmax(1) - return log_probs.nll_loss(labels, weights, ignore_index, reduction), log_probs - - def AffineGrid(theta:Tensor, size:list[int], align_corners:int=0): - N, _, *spatial_dims = size - def generate_grid(steps): - if align_corners: return Tensor.linspace(-1, 1, steps, device=theta.device) - return Tensor.linspace(-1+1/steps, 1-1/steps, steps, device=theta.device) - grids = Tensor.meshgrid(*(generate_grid(d) for d in spatial_dims)) - base_grid = Tensor.stack(*reversed(grids), Tensor.ones_like(grids[0], device=theta.device), dim=-1) - base_grid = base_grid.reshape(1, prod(spatial_dims), len(grids)+1).expand(N, -1, -1) - return (base_grid @ theta.transpose(1, 2)).reshape(N, *spatial_dims, -1) - - def attention_contrib(x:Tensor, weights:Tensor, bias:Tensor|None=None, mask_index:Tensor|None=None, past:Tensor|None=None, - attention_bias:Tensor|None=None, past_sequence_length:Tensor|None=None, do_rotary:int=0, mask_filter_value:float=-10000.0, - num_heads:int|None=None, past_present_share_buffer:int|None=None, qkv_hidden_sizes:list[int]|None=None, - rotary_embedding_dim:int|None=None, scale:float|None=None, unidirectional:int=0): - assert not do_rotary and not attention_bias, "TODO" - if qkv_hidden_sizes is None: qkv_hidden_sizes = [weights.shape[1] // 3] * 3 - qkv = x.linear(weights, bias) - q, k, v = qkv.split(qkv_hidden_sizes, dim=2) - - batch_size, seq_len, _ = x.shape - assert num_heads is not None, "num_heads must be provided" - q_head_size, k_head_size, v_head_size = (sz // num_heads for sz in qkv_hidden_sizes) - q, k, v = (x.reshape(batch_size, seq_len, num_heads, hsz).transpose(1, 2) for x, hsz in zip((q, k, v), (q_head_size, k_head_size, v_head_size))) - - present = None - if past is not None: - k, v = past[0].cat(k, dim=2), past[1].cat(v, dim=2) - present = k.stack(v) - - if scale is None: scale = 1.0 / math.sqrt(q_head_size) - attn_scores = q @ k.transpose(-1, -2) * scale - - if mask_index is not None: - assert 4 >= mask_index.ndim >= 1, f"{mask_index.ndim=}" - assert isinstance(batch_size, int), f"{batch_size=}" - if mask_index.ndim != 1: mask = mask_index.bool() - else: - if mask_index.shape[0] == batch_size: - mask = Tensor.arange(attn_scores.shape[-1], requires_grad=False, device=mask_index.device).unsqueeze(0) < mask_index.unsqueeze(1) - elif mask_index.shape[0] == 2*batch_size: - end_positions = mask_index[:batch_size] - start_positions = mask_index[batch_size:] - arange = Tensor.arange(seq_len).unsqueeze(0) - mask = (arange < end_positions.unsqueeze(1)) & (arange >= start_positions.unsqueeze(1)) - else: raise NotImplementedError("mask_index with shape (3 * batch_size + 2) is not implemented") - while mask.ndim < 4: mask = mask.unsqueeze(1) - attn_scores = mask.where(attn_scores, mask_filter_value) - - if unidirectional: - causal_mask = Tensor.ones((seq_len, seq_len), dtype=dtypes.bool).tril() - attn_scores = causal_mask.where(attn_scores, mask_filter_value) - - output = attn_scores.softmax(-1) @ v - output = output.transpose(1, 2).reshape(batch_size, seq_len, -1) - return output, present - - def attention_onnx(Q:Tensor, K:Tensor, V:Tensor, attn_mask:Tensor|None=None, past_key:Tensor|None=None, past_value:Tensor|None=None, - is_causal:int=0, kv_num_heads:int|None=None, q_num_heads:int|None=None, qk_matmul_output_mode:int=0, scale:float|None=None, - softcap:float=0.0, softmax_precision:int|None=None): - input_shape_len = Q.ndim - if input_shape_len == 3: - assert q_num_heads is not None and kv_num_heads is not None - Q = Q.reshape(Q.shape[0], q_num_heads, Q.shape[1], -1) - K = K.reshape(K.shape[0], kv_num_heads, K.shape[1], -1) - V = V.reshape(V.shape[0], kv_num_heads, V.shape[1], -1) - - if past_key is not None: K = past_key.cat(K, dim=2) - if past_value is not None: V = past_value.cat(V, dim=2) - present_key, present_value = K, V - - _q_heads, _kv_heads = q_num_heads or Q.shape[1], kv_num_heads or K.shape[1] - if _q_heads != _kv_heads: - K = K.repeat((1, _q_heads // _kv_heads, 1, 1)) - V = V.repeat((1, _q_heads // _kv_heads, 1, 1)) - - effective_scale = scale if scale is not None else 1.0 / (cast(int, Q.shape[-1]) ** 0.5) - scores = (Q @ K.transpose(-1, -2)) * effective_scale - qk_matmul_return_val = scores - - if is_causal: - causal_mask = Tensor.ones(Q.shape[-2], K.shape[-2], device=Q.device, dtype=dtypes.bool, requires_grad=False).tril(0) - scores = scores.masked_fill(causal_mask.logical_not(), -float("inf")) - - if attn_mask is not None: - mask_to_add = attn_mask.where(0, -float("inf")) if attn_mask.dtype == dtypes.bool else attn_mask - scores = scores + mask_to_add - if qk_matmul_output_mode == 1: qk_matmul_return_val = scores - - if softcap > 0.0: scores = (scores / softcap).tanh() * softcap - if qk_matmul_output_mode == 2: qk_matmul_return_val = scores - - if softmax_precision: scores = scores.cast({1: dtypes.float32, 10: dtypes.float16, 16: dtypes.bfloat16}[softmax_precision]) - qk_softmax = scores.softmax(-1).cast(Q.dtype) - if qk_matmul_output_mode == 3: qk_matmul_return_val = qk_softmax - - output = (qk_softmax @ V).cast(Q.dtype) - if input_shape_len == 3: output = output.permute(0, 2, 1, 3).reshape(Q.shape[0], Q.shape[2], -1) - return output, present_key, present_value, qk_matmul_return_val - Attention = {OpSetId(Domain.ONNX, 1): attention_onnx, OpSetId(Domain.MICROSOFT_CONTRIB_OPS, 1): attention_contrib} - - def RMSNormalization(X:Tensor, scale:Tensor, axis:int=-1, epsilon:float=1e-5): - norm = X.square().mean(axis=tuple(range(axis + X.ndim if axis < 0 else axis, X.ndim)), keepdim=True).add(epsilon).rsqrt() - return X * norm * scale - - def RotaryEmbedding(X:Tensor, cos_cache:Tensor, sin_cache:Tensor, position_ids:Tensor|None=None, interleaved:int=0, num_heads:int|None=None, - rotary_embedding_dim:int=0): - original_input_shape = X.shape - - if X.ndim == 4: X = X.permute(0, 2, 1, 3) - elif X.ndim == 3: - assert num_heads is not None, "num_heads must be provided for 3D input" - X = X.unflatten(-1, (num_heads, X.shape[-1] // num_heads)) - - head_size = cast(int, X.shape[-1]) - rot_dim = rotary_embedding_dim or head_size - x_rotate, x_pass = X[..., :rot_dim], X[..., rot_dim:] - - cos = cos_cache[position_ids] if position_ids is not None else cos_cache[:head_size] - sin = sin_cache[position_ids] if position_ids is not None else sin_cache[:head_size] - cos = cos[..., :rot_dim//2].unsqueeze(2) - sin = sin[..., :rot_dim//2].unsqueeze(2) - - x1, x2 = (x_rotate[..., ::2], x_rotate[..., 1::2]) if interleaved else x_rotate.chunk(2, dim=-1) - real = x1 * cos - x2 * sin - imag = x1 * sin + x2 * cos - x_rotated = real.stack(imag, dim=-1).flatten(start_dim=-2) if interleaved else real.cat(imag, dim=-1) - - output = x_rotated.cat(x_pass, dim=-1) - return output.flatten(start_dim=2) if len(original_input_shape) == 3 else output.permute(0, 2, 1, 3) - - # ***** Indexing Ops ***** - def ArrayFeatureExtractor(x:Tensor, indices:Tensor): return x[..., indices] - - def Gather(x:Tensor, indices:Tensor, axis:int=0): - if indices.numel() < 9: # NOTE lessor kernels for smaller indices but kernel number increases depending on size of indices - ret_shape = x.shape[:axis] + indices.shape + x.shape[axis+1:] - if indices.ndim > 1: indices = indices.flatten() - index_consts = [_cached_to_python_const(indices)] if indices.shape == () else _cached_to_python_const(indices) - index_consts = [x.shape[axis]+i if i<0 else i for i in index_consts] - args = [[(0,x) if j != axis else (i,i+1) for j, x in enumerate(x.shape)] for i in index_consts] - return x.shrink(arg=tuple(args[0])).cat(*[x.shrink(arg=tuple(arg)) for arg in args[1:]], dim=axis).reshape(ret_shape) - # NOTE faster gather, fixed number of kernels, but exceeds limited kernels for openpilot - return x[tuple([slice(None) if i != axis else indices for i in range(x.ndim)])] - def Scatter(*args, **kwargs): return ScatterElements(*args, **kwargs) # deprecated - - def GatherND(x:Tensor, indices:Tensor, batch_dims:int=0): - if batch_dims == 0: return x[tuple(i.squeeze(-1) for i in indices.split(1, -1))] - x_shape, i_shape = x.shape, indices.shape - b = math.prod(x.shape[dim] for dim in range(batch_dims)) - # NOTE: each batched dim of both input and indices are equal - x = x.reshape(b, *x.shape[batch_dims:]) - indices = indices.reshape(b, *indices.shape[batch_dims:]) - b_idx = Tensor.arange(b, device=x.device).reshape(b, *(1,)*(indices.ndim - 2)).expand(*indices.shape[:-1]) - ret = x[(b_idx,) + tuple(i.squeeze(-1) for i in indices.split(1, -1))] - return ret.reshape(*x_shape[:batch_dims], *i_shape[batch_dims:-1], *ret.shape[indices.ndim-1:]) - def ScatterND(x:Tensor, indices:Tensor, updates:Tensor, reduction:Literal["none", "add", "mul"]='none'): - assert updates.shape == indices.shape[:-1] + x.shape[cast(int, indices.shape[-1]):] - x = x.contiguous() - for index, u in zip(indices.split(1, 0), updates.split(1, 0)): - i = tuple(idx.squeeze(-1) for idx in index.squeeze(0).split(1, -1)) - u = u.squeeze(0) - if reduction == "none": x[i] = u - elif reduction == "add": x[i] += u - elif reduction == "mul": x[i] *= u - else: raise NotImplementedError("reduction doesn't support max or min") - return x - - def ScatterElements(x: Tensor, indices: Tensor, updates: Tensor, axis=0, reduction:Literal["none", "add", "mul", "min", "max"]="none"): - indices = (indices < 0).where(x.shape[axis], 0) + indices - if reduction == "none": return x.scatter(axis, indices, updates) - reduction_ = cast(Literal["sum", "prod", "amin", "amax"], {"add": "sum", "mul": "prod", "min": "amin", "max": "amax"}[reduction]) - return x.scatter_reduce(axis, indices, updates, reduction_) - def GatherElements(x:Tensor, indices:Tensor, axis:int): - indices = (indices < 0).where(x.shape[axis], 0) + indices - return x.gather(axis, indices) - - def Compress(inp:Tensor, condition:list[bool], axis:int|None=None): - if axis is None: - inp = inp.flatten() - axis = 0 - axis = inp._resolve_dim(axis) - con = Tensor([i for i,cond in enumerate(condition) if cond]) # compress in python - return inp[tuple(con if i == axis else slice(None) for i in range(inp.ndim))] - - # ***** Quantization Ops ***** - def QuantizeLinear(x:Tensor, y_scale:Tensor, y_zero_point:Tensor|int=0, axis:int=1, block_size:int=0, output_dtype:int=0, saturate=1): - if isinstance(y_zero_point, Tensor): out_dtype = y_zero_point.dtype - elif output_dtype != 0: out_dtype = dtype_fallback(OnnxDataType(output_dtype).to_dtype(), "QuantizeLinear op") - else: out_dtype = dtypes.uint8 - y_scale, y_zero_point = _prepare_quantize(x, y_scale, y_zero_point, axis, block_size) - if out_dtype == dtypes.uchar: - # this appears to work in practice, at least for uchar out_dtype. it folds with the quantize stuff - ret = _clamp_cast((x / y_scale + 0.4999999 + y_zero_point).int(), out_dtype) - else: - ret = _clamp_cast(((x / y_scale).round() + y_zero_point), out_dtype) - return ret.contiguous() - - def DynamicQuantizeLinear(x: Tensor): - # only support uint8 - qmin, qmax = dtypes.min(dtypes.uint8), dtypes.max(dtypes.uint8) - scale = (x.max().maximum(0) + ((-x).max()).maximum(0)) / (qmax - qmin) - zero_point = _clamp_cast((qmin - x.min() / scale).round(), dtypes.uint8) - y = _clamp_cast((x / scale).round() + zero_point, dtypes.uint8) - return y, scale, zero_point - - def DequantizeLinear(x:Tensor, x_scale:Tensor, x_zero_point:Tensor|int=0, axis:int=1, block_size:int=0): - x_scale, x_zero_point = _prepare_quantize(x, x_scale, x_zero_point, axis, block_size) - return ((x.int() - x_zero_point) * x_scale).cast(x_scale.dtype) - - def QLinearConv(x:Tensor, x_scale:Tensor, x_zero_point:Tensor, w:Tensor, w_scale:Tensor, w_zero_point:Tensor, y_scale:Tensor, - y_zero_point:Tensor, B:Tensor|None=None, **opts): - return _qlinearop_quantized(Conv, [x,w], [x_zero_point,w_zero_point], [x_scale,w_scale], y_scale, y_zero_point, **{"B":B, **opts}) - - def QLinearMatMul(a:Tensor, a_scale:Tensor, a_zero_point:Tensor, b:Tensor, b_scale:Tensor, b_zero_point:Tensor, y_scale:Tensor, - y_zero_point:Tensor) -> Tensor: - return _qlinearop_quantized(Tensor.matmul, [a,b], [a_zero_point,b_zero_point], [a_scale,b_scale], y_scale, y_zero_point) - - def QLinearAdd(a:Tensor, a_scale:Tensor, a_zero_point:Tensor, b:Tensor, b_scale:Tensor, b_zero_point:Tensor, c_scale:Tensor, c_zero_point:Tensor): - return _qlinearop_float(Tensor.add, [a,b], [a_zero_point,b_zero_point], [a_scale,b_scale], c_scale, c_zero_point) - - def QLinearMul(a:Tensor, a_scale:Tensor, a_zero_point:Tensor, b:Tensor, b_scale:Tensor, b_zero_point:Tensor, c_scale:Tensor, c_zero_point:Tensor): - return _qlinearop_quantized(Tensor.mul, [a,b], [a_zero_point,b_zero_point], [a_scale,b_scale], c_scale, c_zero_point) - - def QLinearGlobalAveragePool(X:Tensor, x_scale:Tensor, x_zero_point:Tensor, y_scale:Tensor, y_zero_point:Tensor, channels_last:int): - assert channels_last == 0, "TODO NHWC" - return _qlinearop_float(GlobalAveragePool, [X], [x_zero_point], [x_scale], y_scale, y_zero_point) - - def ConvInteger(x: Tensor, w: Tensor, x_zero_point:Tensor = Tensor(0), w_zero_point:Tensor = Tensor(0), B: Tensor | None = None, **opts) -> Tensor: - return _op_integer(Conv, [x,w], [x_zero_point,w_zero_point], **{"B":B, **opts}) - - def MatMulInteger(A: Tensor, B: Tensor, a_zero_point: Tensor = Tensor(0), b_zero_point: Tensor = Tensor(0)) -> Tensor: - return _op_integer(Tensor.matmul, [A,B], [a_zero_point,b_zero_point]) - - # ***** Training Ops ***** - # NOTE: onnx training ops actually don't need the state for optim, all the ops work in a functional way, but we still can reuse optim.py code - @_onnx_training(3) - def Adagrad(R:Tensor, T:int, *inputs:Tensor, decay_factor:float=0.0, epsilon:float=0.0, norm_coefficient:float=0.0): - X, G, H = (i.detach() for i in inputs) - grad = norm_coefficient * X + G - H.assign(H + grad.square()) - up = grad / (H.sqrt() + epsilon) - r = R / (1 + T * decay_factor) - X.assign(X.detach() - r * up) - return [X, H] - - @_onnx_training(4) - def Adam(R:Tensor, T:int, *inputs:Tensor, alpha:float=0.9, beta:float=0.999, epsilon:float=0.0, norm_coefficient:float=0.0, - norm_coefficient_post:float=0.0): - from tinygrad.nn.optim import Adam as TinyAdam - X, G, V, H = inputs - G, V, H = G.detach(), V.detach(), H.detach() - X.grad = norm_coefficient * X.detach() + G - opt = TinyAdam([X], b1=alpha, b2=beta, eps=epsilon) - opt.m, opt.v, opt.lr = [V], [H], R - # need no-op for m_hat and v_hat if T == 0 - if T == 0: opt.b1_t, opt.b2_t = opt.b1_t.zeros_like(), opt.b2_t.zeros_like() - else: - # `T-1` since it's applied again at the start of `_step` - opt.b1_t = Tensor([alpha**(T-1)], dtype=dtypes.float32, device=X.device, requires_grad=False) - opt.b2_t = Tensor([beta**(T-1)], dtype=dtypes.float32, device=X.device, requires_grad=False) - opt.step() - X = (1 - norm_coefficient_post) * X - return [X, V, H] - - @_onnx_training(3) - def Momentum(R:Tensor, T:int, *inputs:Tensor, alpha:float, beta:float, mode:str, norm_coefficient:float): - X, G, V = (i.detach() for i in inputs) - grad = norm_coefficient * X + G - # NOTE: this beta_adjusted term makes it so we can't use SGD for nesterov - beta_adjusted = beta if T > 0 else 1 - V.assign(alpha * V + grad * beta_adjusted) - X.assign(X - R * (V if mode == "standard" else (grad + alpha * V))) - return [X, V] - - def Gradient(*inputs:Tensor, y:str, intermediate_tensors:dict[str, Tensor], **_): - intermediate_tensors[y].backward() - return tuple([t.grad for t in inputs]) - - return { - # Tensor ops - **{op: getattr(Tensor, op.lower()) for op in ("Neg", "Reciprocal", "Pow", "Sqrt", "Sign", "Abs", "Exp", "Log", "Mish", "Sin", "Cos", "Tan", - "Asin", "Acos", "Atan", "Relu", "Sigmoid", "MatMul", "Floor", "Ceil", "IsNaN", "Softplus", "HardSwish", "Where", "Mul", "Sinh", "Cosh", - "Tanh", "Softsign", "Asinh", "Acosh", "Atanh", "Elu", "Celu", "Selu", "Round", "Erf")}, - # Implemented ops - **{name:obj for name,obj in locals().items() if isinstance(obj, types.FunctionType) and not name.startswith("_") and name[0].isupper()}, - # Version ops - **{name:obj for name,obj in locals().items() if isinstance(obj, dict)}, - } - -onnx_ops = get_onnx_ops() +# type: ignore +import sys, pathlib +sys.path.append(pathlib.Path(__file__).parent.parent.as_posix()) +try: + from extra.onnx import OnnxRunner # noqa: F401 # pylint: disable=unused-import + from extra.onnx_parser import onnx_load # noqa: F401 # pylint: disable=unused-import +except ImportError as e: raise ImportError("onnx frontend not in release\nTo fix, install tinygrad from a git checkout with pip install -e .") from e \ No newline at end of file diff --git a/tinygrad_repo/tinygrad/gradient.py b/tinygrad_repo/tinygrad/gradient.py index c538555ad..317510de1 100644 --- a/tinygrad_repo/tinygrad/gradient.py +++ b/tinygrad_repo/tinygrad/gradient.py @@ -1,5 +1,6 @@ from typing import cast import math, dataclasses +from tinygrad.dtype import dtypes, sum_acc_dtype from tinygrad.uop.ops import UOp, PatternMatcher, UPat, Ops, all_metadata from tinygrad.helpers import argsort @@ -7,7 +8,7 @@ def reduce_gradient(ctx:UOp, ret:UOp): def to_inp_shape(x): return x.reshape(x.shape+(1,)*(len(ret.src[0].shape)-len(x.shape))).expand(ret.src[0].shape) if ret.arg[0] == Ops.ADD: return (to_inp_shape(ctx),) if ret.arg[0] == Ops.MAX: - max_is_1s = ret.src[0].eq(to_inp_shape(ret)).cast(ctx.dtype) + max_is_1s = ret.src[0].ne(to_inp_shape(ret)).ne(ret.src[0].const_like(1).cast(dtypes.bool)).cast(ctx.dtype) div = to_inp_shape(max_is_1s.r(Ops.ADD, ret.arg[1])) return ((max_is_1s/div) * to_inp_shape(ctx),) if ret.arg[0] == Ops.MUL: return (to_inp_shape(ctx * ret) / ret.src[0],) @@ -22,10 +23,11 @@ pm_gradient = PatternMatcher([ (UPat(Ops.SQRT, name="ret"), lambda ctx, ret: (ctx / (ret*2),)), (UPat((Ops.CMPLT, Ops.CMPNE)), lambda: (None, None)), (UPat(Ops.ADD), lambda ctx: (ctx, ctx)), - (UPat(Ops.POW, name="ret", src=(UPat.var("b"), UPat.var("e"))), lambda ctx, ret, b, e: - (ctx * (b.eq(0)&e.eq(0)).where(e, e*b.pow(e-1)), ctx * b.eq(0).where((e<0).where(ret.const_like(-math.inf), 0), ret*b.log2()*math.log(2.0)))), - (UPat(Ops.MAX, name="ret", src=(UPat.var("x"), UPat.var("y"))), lambda ctx, ret, x, y: - ((x>y).where(ctx, (x.eq(y)).where(ctx * 0.5, 0)), (xret.src[1]).where(ctx, (ret.src[0]!=ret.src[1]).where(ctx.const_like(0), ctx * 0.5)), + (ret.src[0] T|int: return functools.reduce(operator.mul, x, 1) +def prod(x:Iterable[T]) -> Union[T,int]: return functools.reduce(operator.mul, x, 1) # NOTE: helpers is not allowed to import from anything else in tinygrad OSX = platform.system() == "Darwin" @@ -23,14 +23,14 @@ def argfix(*x): return tuple(x[0]) return x def argsort(x): return type(x)(sorted(range(len(x)), key=x.__getitem__)) # https://stackoverflow.com/questions/3382352/equivalent-of-numpy-argsort-in-basic-python -def all_same(items:tuple[T, ...]|list[T]): return all(x == items[0] for x in items) +def all_same(items:Union[tuple[T, ...], list[T]]): return all(x == items[0] for x in items) def all_int(t: Sequence[Any]) -> TypeGuard[tuple[int, ...]]: return all(isinstance(s, int) for s in t) -def colored(st, color:str|None, background=False): return f"\u001b[{10*background+60*(color.upper() == color)+30+['black', 'red', 'green', 'yellow', 'blue', 'magenta', 'cyan', 'white'].index(color.lower())}m{st}\u001b[0m" if color is not None else st # replace the termcolor library with one line # noqa: E501 +def colored(st, color:Optional[str], background=False): return f"\u001b[{10*background+60*(color.upper() == color)+30+['black', 'red', 'green', 'yellow', 'blue', 'magenta', 'cyan', 'white'].index(color.lower())}m{st}\u001b[0m" if color is not None else st # replace the termcolor library with one line # noqa: E501 def colorize_float(x: float): return colored(f"{x:7.2f}x", 'green' if x < 0.75 else 'red' if x > 1.15 else 'yellow') def time_to_str(t:float, w=8) -> str: return next((f"{t * d:{w}.2f}{pr}" for d,pr in [(1, "s "),(1e3, "ms")] if t > 10/d), f"{t * 1e6:{w}.2f}us") def ansistrip(s:str): return re.sub('\x1b\\[(K|.*?m)', '', s) def ansilen(s:str): return len(ansistrip(s)) -def make_tuple(x:int|Sequence[int], cnt:int) -> tuple[int, ...]: return (x,)*cnt if isinstance(x, int) else tuple(x) +def make_tuple(x:Union[int, Sequence[int]], cnt:int) -> tuple[int, ...]: return (x,)*cnt if isinstance(x, int) else tuple(x) def flatten(l:Iterable[Iterable[T]]): return [item for sublist in l for item in sublist] def fully_flatten(l): if hasattr(l, "__len__") and hasattr(l, "__getitem__") and not isinstance(l, str): @@ -53,7 +53,6 @@ def data64(data:Any) -> tuple[Any, Any]: return (data >> 32, data & 0xFFFFFFFF) def data64_le(data:Any) -> tuple[Any, Any]: return (data & 0xFFFFFFFF, data >> 32) # Any is sint def getbits(value: int, start: int, end: int): return (value >> start) & ((1 << (end - start + 1)) - 1) def i2u(bits: int, value: int): return value if value >= 0 else (1< bool: return str(type(x)) == "" def merge_dicts(ds:Iterable[dict[T,U]]) -> dict[T,U]: kvs = set([(k,v) for d in ds for k,v in d.items()]) assert len(kvs) == len(set(kv[0] for kv in kvs)), f"cannot merge, {kvs} contains different values for the same key" @@ -62,7 +61,7 @@ def partition(itr:Iterable[T], fxn:Callable[[T],bool]) -> tuple[list[T], list[T] ret:tuple[list[T], list[T]] = ([], []) for s in itr: (ret[0] if fxn(s) else ret[1]).append(s) return ret -def unwrap(x:T|None) -> T: +def unwrap(x:Optional[T]) -> T: assert x is not None return x def get_single_element(x:Sequence[T]) -> T: @@ -74,20 +73,7 @@ def get_child(obj, key): elif isinstance(obj, dict): obj = obj[k] else: obj = getattr(obj, k) return obj -def word_wrap(x, wrap=80): - if len(ansistrip(x)) <= wrap: return x - if len(lines:=x.splitlines()) > 1: return "\n".join(word_wrap(line, wrap) for line in lines) - i = 0 - while len(ansistrip(x[:i])) < wrap and i < len(x): i += 1 - return x[:i] + "\n" + word_wrap(x[i:], wrap) - -def suppress_finalizing(func): - def wrapper(*args, **kwargs): - try: return func(*args, **kwargs) - except (AttributeError, TypeError, ImportError): - if not getattr(sys, 'is_finalizing', lambda: True)(): raise # re-raise if not finalizing - return wrapper - +def word_wrap(x, wrap=80): return x if len(x) <= wrap or '\n' in x[0:wrap] else (x[0:wrap] + "\n" + word_wrap(x[wrap:], wrap)) def pluralize(st:str, cnt:int): return f"{cnt} {st}"+('' if cnt == 1 else 's') class LazySeq(Generic[T]): # NOTE: Mapping requires __iter__ and __len__, Sequence requires supporting __len__ and slicing in __getitem__ @@ -127,20 +113,18 @@ class ContextVar: DEBUG, IMAGE, BEAM, NOOPT = ContextVar("DEBUG", 0), ContextVar("IMAGE", 0), ContextVar("BEAM", 0), ContextVar("NOOPT", 0) JIT = ContextVar("JIT", 2 if platform.system() == 'Darwin' and ('Intel' in platform.processor() or 'i386' in platform.processor()) else 1) -JIT_BATCH_SIZE = ContextVar("JIT_BATCH_SIZE", 32) WINO, CAPTURING, TRACEMETA = ContextVar("WINO", 0), ContextVar("CAPTURING", 1), ContextVar("TRACEMETA", 1) USE_TC, TC_SELECT, TC_OPT, AMX = ContextVar("TC", 1), ContextVar("TC_SELECT", -1), ContextVar("TC_OPT", 0), ContextVar("AMX", 0) TRANSCENDENTAL, TC_SEARCH_OVER_SHAPE, NOLOCALS = ContextVar("TRANSCENDENTAL", 1), ContextVar("TC_SEARCH_OVER_SHAPE", 1), ContextVar("NOLOCALS", 0) -FUSE_ARANGE, FUSE_CONV_BW = ContextVar("FUSE_ARANGE", 1), ContextVar("FUSE_CONV_BW", 0) +FUSE_ARANGE, FUSE_CONV_BW = ContextVar("FUSE_ARANGE", 0), ContextVar("FUSE_CONV_BW", 0) SPLIT_REDUCEOP, NO_MEMORY_PLANNER, RING = ContextVar("SPLIT_REDUCEOP", 1), ContextVar("NO_MEMORY_PLANNER", 0), ContextVar("RING", 1) PICKLE_BUFFERS, PROFILE, LRU = ContextVar("PICKLE_BUFFERS", 1), ContextVar("PROFILE", getenv("VIZ")), ContextVar("LRU", 1) CACHELEVEL, IGNORE_BEAM_CACHE, DEVECTORIZE = ContextVar("CACHELEVEL", 2), ContextVar("IGNORE_BEAM_CACHE", 0), ContextVar("DEVECTORIZE", 1) -DISABLE_COMPILER_CACHE, BLOCK_REORDER = ContextVar("DISABLE_COMPILER_CACHE", 0), ContextVar("BLOCK_REORDER", 1) +DISABLE_COMPILER_CACHE = ContextVar("DISABLE_COMPILER_CACHE", 0) DONT_REALIZE_EXPAND, DONT_GROUP_REDUCES = ContextVar("DONT_REALIZE_EXPAND", 0), ContextVar("DONT_GROUP_REDUCES", 0) -QUANTIZE, VALIDATE_WITH_CPU, DISABLE_FAST_IDIV = ContextVar("QUANTIZE", 0), ContextVar("VALIDATE_WITH_CPU", 0), ContextVar("DISABLE_FAST_IDIV", 0) +QUANTIZE, VALIDATE_WITH_CPU = ContextVar("QUANTIZE", 0), ContextVar("VALIDATE_WITH_CPU", 0) CORRECT_DIVMOD_FOLDING, FUSE_OPTIM = ContextVar("CORRECT_DIVMOD_FOLDING", 0), ContextVar("FUSE_OPTIM", 0) -ALLOW_DEVICE_USAGE, MAX_BUFFER_SIZE, AMD_LLVM = ContextVar("ALLOW_DEVICE_USAGE", 1), ContextVar("MAX_BUFFER_SIZE", 0), ContextVar("AMD_LLVM", 1) -RANGEIFY, POSTOPT, FUSE_ATTENTION = ContextVar("RANGEIFY", 0), ContextVar("POSTOPT", 0), ContextVar("FUSE_ATTENTION", 0) +ALLOW_DEVICE_USAGE = ContextVar("ALLOW_DEVICE_USAGE", 1) @dataclass(frozen=True) class Metadata: @@ -192,38 +176,12 @@ class Profiling(contextlib.ContextDecorator): colored(_format_fcn(fcn).ljust(50), "yellow"), colored(f"<- {(scallers[0][1][2]/tottime)*100:3.0f}% {_format_fcn(scallers[0][0])}", "BLACK") if scallers else '') -def perf_counter_us() -> decimal.Decimal: return decimal.Decimal(time.perf_counter_ns())/1000 - -@dataclass(frozen=True) -class TracingKey: - display_name:str # display name of this trace event - keys:tuple[Any, ...]=() # optional keys to search for related traces - ret:Any=None - -class ProfileEvent: pass - -@dataclass -class ProfileRangeEvent(ProfileEvent): device:str; name:str|TracingKey; st:decimal.Decimal; en:decimal.Decimal|None=None; is_copy:bool=False # noqa: E702 - -@dataclass(frozen=True) -class ProfilePointEvent(ProfileEvent): device:str; name:str; key:Any; arg:dict=field(default_factory=dict); \ - ts:decimal.Decimal=field(default_factory=perf_counter_us) # noqa: E702 - -cpu_events:list[ProfileEvent] = [] -@contextlib.contextmanager -def cpu_profile(name:str|TracingKey, device="CPU", is_copy=False, display=True) -> Generator[ProfileRangeEvent, None, None]: - res = ProfileRangeEvent(device, name, perf_counter_us(), is_copy=is_copy) - try: yield res - finally: - res.en = perf_counter_us() - if PROFILE and display: cpu_events.append(res) - # *** universal database cache *** cache_dir: str = os.path.join(getenv("XDG_CACHE_HOME", os.path.expanduser("~/Library/Caches" if OSX else "~/.cache")), "tinygrad") CACHEDB: str = getenv("CACHEDB", os.path.abspath(os.path.join(cache_dir, "cache.db"))) -VERSION = 22 +VERSION = 20 _db_connection = None def db_connection(): global _db_connection @@ -241,7 +199,7 @@ def diskcache_clear(): drop_tables = cur.execute("SELECT 'DROP TABLE IF EXISTS ' || quote(name) || ';' FROM sqlite_master WHERE type = 'table';").fetchall() cur.executescript("\n".join([s[0] for s in drop_tables] + ["VACUUM;"])) -def diskcache_get(table:str, key:dict|str|int) -> Any: +def diskcache_get(table:str, key:Union[dict, str, int]) -> Any: if CACHELEVEL < 1: return None if isinstance(key, (str,int)): key = {"key": key} cur = db_connection().cursor() @@ -253,7 +211,7 @@ def diskcache_get(table:str, key:dict|str|int) -> Any: return None _db_tables = set() -def diskcache_put(table:str, key:dict|str|int, val:Any, prepickled=False): +def diskcache_put(table:str, key:Union[dict, str, int], val:Any, prepickled=False): if CACHELEVEL < 1: return val if isinstance(key, (str,int)): key = {"key": key} conn = db_connection() @@ -288,14 +246,14 @@ def _ensure_downloads_dir() -> pathlib.Path: return downloads_dir return pathlib.Path(cache_dir) / "downloads" -def fetch(url:str, name:pathlib.Path|str|None=None, subdir:str|None=None, gunzip:bool=False, +def fetch(url:str, name:Optional[Union[pathlib.Path, str]]=None, subdir:Optional[str]=None, gunzip:bool=False, allow_caching=not getenv("DISABLE_HTTP_CACHE")) -> pathlib.Path: if url.startswith(("/", ".")): return pathlib.Path(url) if name is not None and (isinstance(name, pathlib.Path) or '/' in name): fp = pathlib.Path(name) else: fp = _ensure_downloads_dir() / (subdir or "") / ((name or hashlib.md5(url.encode('utf-8')).hexdigest()) + (".gunzip" if gunzip else "")) if not fp.is_file() or not allow_caching: (_dir := fp.parent).mkdir(parents=True, exist_ok=True) - with urllib.request.urlopen(urllib.request.Request(url, headers={"User-Agent": "tinygrad 0.11.0"}), timeout=10) as r: + with urllib.request.urlopen(urllib.request.Request(url, headers={"User-Agent": "tinygrad 0.10.3"}), timeout=10) as r: assert r.status == 200, r.status length = int(r.headers.get('content-length', 0)) if not gunzip else None readfile = gzip.GzipFile(fileobj=r) if gunzip else r @@ -310,6 +268,11 @@ def fetch(url:str, name:pathlib.Path|str|None=None, subdir:str|None=None, gunzip # *** Exec helpers +def cpu_time_execution(cb, enable): + if enable: st = time.perf_counter() + cb() + if enable: return time.perf_counter()-st + def cpu_objdump(lib, objdump_tool='objdump'): with tempfile.NamedTemporaryFile(delete=True) as f: pathlib.Path(f.name).write_bytes(lib) @@ -326,18 +289,12 @@ def capstone_flatdump(lib: bytes): print(f"{instr.address:#08x}: {instr.mnemonic}\t{instr.op_str}") sys.stdout.flush() -def wait_cond(cb, value=True, timeout_ms=10000, msg="") -> bool: - start_time = int(time.perf_counter() * 1000) - while int(time.perf_counter() * 1000) - start_time < timeout_ms: - if (val:=cb()) == value: return val - raise TimeoutError(f"{msg}. Timed out after {timeout_ms} ms, condition not met: {val} != {value}") - # *** ctypes helpers # TODO: make this work with read only memoryviews (if possible) def from_mv(mv:memoryview, to_type:type[ctypes._SimpleCData]=ctypes.c_char) -> ctypes.Array: return ctypes.cast(ctypes.addressof(to_type.from_buffer(mv)), ctypes.POINTER(to_type * len(mv))).contents -def to_mv(ptr:int, sz:int) -> memoryview: return memoryview((ctypes.c_uint8 * sz).from_address(ptr)).cast("B") +def to_mv(ptr:int, sz:int) -> memoryview: return memoryview(ctypes.cast(ptr, ctypes.POINTER(ctypes.c_uint8 * sz)).contents).cast("B") def mv_address(mv): return ctypes.addressof(ctypes.c_char.from_buffer(mv)) def to_char_p_p(options: list[bytes], to_type=ctypes.c_char): return (ctypes.POINTER(to_type) * len(options))(*[ctypes.cast(ctypes.create_string_buffer(o), ctypes.POINTER(to_type)) for o in options]) @@ -353,7 +310,7 @@ def flat_mv(mv:memoryview): return mv if len(mv) == 0 else mv.cast("B", shape=(m class tqdm(Generic[T]): def __init__(self, iterable:Iterable[T]|None=None, desc:str='', disable:bool=False, - unit:str='it', unit_scale=False, total:int|None=None, rate:int=100): + unit:str='it', unit_scale=False, total:Optional[int]=None, rate:int=100): self.iterable, self.disable, self.unit, self.unit_scale, self.rate = iterable, disable, unit, unit_scale, rate self.st, self.i, self.n, self.skip, self.t = time.perf_counter(), -1, 0, 1, getattr(iterable, "__len__", lambda:0)() if total is None else total self.set_description(desc) diff --git a/tinygrad_repo/tinygrad/kernelize/__init__.py b/tinygrad_repo/tinygrad/kernelize/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/tinygrad_repo/tinygrad/schedule/grouper.py b/tinygrad_repo/tinygrad/kernelize/grouper.py similarity index 94% rename from tinygrad_repo/tinygrad/schedule/grouper.py rename to tinygrad_repo/tinygrad/kernelize/grouper.py index 685bc70b7..38c5a691f 100644 --- a/tinygrad_repo/tinygrad/schedule/grouper.py +++ b/tinygrad_repo/tinygrad/kernelize/grouper.py @@ -2,9 +2,8 @@ from tinygrad.uop.ops import Ops, UOp, resolve, can_pad, GroupOp, UPat, PatternM from tinygrad.helpers import all_int, prod, unwrap, dedup, DONT_REALIZE_EXPAND, DONT_GROUP_REDUCES, FUSE_CONV_BW from tinygrad.shape.shapetracker import ShapeTracker -ALWAYS_CONTIGUOUS: set[Ops] = {Ops.CONTIGUOUS, Ops.ASSIGN, Ops.COPY, Ops.BUFFER, Ops.BUFFER_VIEW, - Ops.CONST, Ops.BIND, Ops.DEVICE, Ops.MSELECT, Ops.MSTACK, Ops.DEFINE_GLOBAL, - Ops.DEFINE_LOCAL, Ops.DEFINE_REG, Ops.LOAD} +ALWAYS_CONTIGUOUS = {Ops.CONTIGUOUS, Ops.ASSIGN, Ops.COPY, Ops.BUFFER, Ops.BUFFER_VIEW, + Ops.CONST, Ops.BIND, Ops.DEVICE, Ops.MSELECT, Ops.MSTACK, Ops.GBARRIER} # **** Grouper decides which of the UOps realize @@ -26,8 +25,8 @@ def realize_before_view(ctx:dict[UOp, None], view:UOp, tr:UOp) -> None: do_realize = PatternMatcher([ # always realize SINK parents (UPat(Ops.SINK, name="s"), lambda ctx,s: ctx.update((x.base, None) for x in s.src if x.base.op not in ALWAYS_CONTIGUOUS)), - # always realize ASSIGN/CONTIGUOUS/COPY/BUFFER_VIEW - (UPat({Ops.ASSIGN, Ops.CONTIGUOUS, Ops.COPY, Ops.BUFFER_VIEW}, name="tr"), realize), + # always realize ASSIGN/CONTIGUOUS/GroupOp.Meta + (UPat({Ops.ASSIGN, Ops.CONTIGUOUS, *GroupOp.Meta}, name="tr"), realize), # realize before expand or unsafe pad ops (UPat(Ops.VIEW, src=(UPat(GroupOp.All-ALWAYS_CONTIGUOUS, name="tr"),), name="view"), realize_before_view), # realize parents of COPY, MSELECT, MSTACK diff --git a/tinygrad_repo/tinygrad/schedule/kernelize.py b/tinygrad_repo/tinygrad/kernelize/kernelize.py similarity index 62% rename from tinygrad_repo/tinygrad/schedule/kernelize.py rename to tinygrad_repo/tinygrad/kernelize/kernelize.py index b1e90bc60..d00d7de43 100644 --- a/tinygrad_repo/tinygrad/schedule/kernelize.py +++ b/tinygrad_repo/tinygrad/kernelize/kernelize.py @@ -1,13 +1,14 @@ from dataclasses import dataclass -from tinygrad.uop.ops import UOp, Ops, GroupOp, PatternMatcher, UPat, graph_rewrite, graph_rewrite_map, identity_element, resolve +from tinygrad.uop.ops import UOp, Ops, GroupOp, PatternMatcher, UPat, graph_rewrite, graph_rewrite_map, identity_element, resolve, sint from tinygrad.uop.ops import track_rewrites, _substitute from tinygrad.uop.spec import type_verify, tensor_uop_spec from tinygrad.uop.symbolic import symbolic_simple -from tinygrad.helpers import Metadata, all_int, all_same, prod, dedup, unwrap, getenv, pluralize, FUSE_ARANGE, DEBUG, SPLIT_REDUCEOP +from tinygrad.helpers import Metadata, all_int, all_same, colored, prod, dedup, unwrap, getenv, pluralize, FUSE_ARANGE, DEBUG, SPLIT_REDUCEOP from tinygrad.dtype import ImageDType -from tinygrad.schedule.multi import multi_pm -from tinygrad.schedule.grouper import group_realizes, ALWAYS_CONTIGUOUS -from tinygrad.codegen.opt.swizzler import merge_views, apply_swizzle, swizzle_reduceop +from tinygrad.kernelize.multi import multi_pm +from tinygrad.shape.shapetracker import ShapeTracker +from tinygrad.shape.view import View, strides_for_shape, get_contraction_with_reduce +from tinygrad.kernelize.grouper import group_realizes, ALWAYS_CONTIGUOUS # creation can recurse a lot import sys @@ -48,9 +49,10 @@ def copy_reorder_view(copy:UOp, view:UOp, base:UOp): if prod(view.shape) < prod(base.shape): return view.contiguous().copy_to_device(copy.device) return base.copy_to_device(copy.device).view(view.arg) -kernelize_sym = symbolic_simple+PatternMatcher([ +sym = symbolic_simple+PatternMatcher([ # UOp with size 0 is zero - (UPat(GroupOp.All-{Ops.SINK}, name="root"), lambda root: root.const_like(0) if root.base.st is not None and root.size == 0 else None), + (UPat(GroupOp.All-{Ops.SINK}, name="root"), lambda root: root.const_like(0) if root.base.st is not None and root.size == 0 \ + and not (root.base.op is Ops.CONST and root.base.arg == 0) else None), # DETACH and CONTIGUOUS_BACKWARD are NOOPs here (UPat((Ops.DETACH, Ops.CONTIGUOUS_BACKWARD), name="x"), lambda x: x.src[0]), # reduce of size 0 is the identity element @@ -119,9 +121,9 @@ def create_kernel(x:UOp, b:UOp|None=None): if b is None: b = UOp.new_buffer(x.device, x.size, x.dtype) kernel = UOp(Ops.KERNEL, src=(b,)+x.src, arg=Kernel(x.sink(), m if (m:=x.metadata) else ())) buffer = b.base if b.size == b.base.size else UOp(Ops.BUFFER_VIEW, b.dtype, (b.base,), (b.size, b.arg.views[0].offset)) - return buffer.assign(kernel).shrink(((0, prod(x.shape)),)).reshape(x.shape) + return buffer.assign(kernel).reshape(x.shape) -DONT_PLACE_IN_KERNEL = {Ops.KERNEL, Ops.ASSIGN, Ops.BUFFER, Ops.MSELECT, Ops.MSTACK, Ops.MULTI, Ops.BIND} +DONT_PLACE_IN_KERNEL = {Ops.KERNEL, Ops.ASSIGN, Ops.BUFFER, Ops.MSELECT, Ops.MSTACK, Ops.MULTI} def append_to_kernel(x:UOp): new_srcs: list[UOp] = [] metadata = x.arg.metadata @@ -135,9 +137,9 @@ def append_to_kernel(x:UOp): if (new_src:=tuple(dedup(new_srcs))) != x.src: return x.replace(src=new_src, arg=Kernel(x.arg.ast, tuple(dedup(metadata)))) create_kernels = PatternMatcher([ - # always give assign/contiguous a kernel + # always give assign/gbarrier a kernel (UPat.assign(UPat.var("b"), UPat(GroupOp.All-{Ops.KERNEL}), name="x"), create_kernel), - (UPat(Ops.CONTIGUOUS, name="x"), create_kernel), + (UPat(Ops.GBARRIER, src=(UPat.var("x"),)), create_kernel), # walk back the local graph until we reach a realized source (UPat(Ops.KERNEL, name="x"), append_to_kernel), # push RESHAPE through MSELECT @@ -147,59 +149,165 @@ create_kernels = PatternMatcher([ lambda ms: UOp(Ops.MSTACK, ms.dtype, tuple(x.src[0] for x in ms.src)).reshape(ms.src[0].arg)), ]) -# **** fix kernel AST +# **** swizzler -def unbind_view(x:UOp): - if any(x.op is Ops.BIND for x in x.arg.vars()): return x.replace(arg=x.arg.unbind()[0]) +merge_views = PatternMatcher([ + # merge adjacent views + (UPat(Ops.VIEW, src=(UPat(Ops.VIEW, name="v1"),), name="v2"), lambda v1,v2: v1.replace(arg=v1.arg+v2.arg)), + # replace MovementOps with VIEW + (UPat(GroupOp.Movement, src=(UPat.var("x"),), name="mop"), lambda mop,x: x.base.view(mop.st)), + # remove NOOP views + (UPat.var("x").view(name="view"), lambda x,view: x if x.st is not None and view.st.contiguous and view.shape == x.shape else None), + (UPat(GroupOp.All-{Ops.DEFINE_GLOBAL}).view(name="view"), + lambda view: view.const_like(0) if (mask:=view.st.views[-1].mask) is not None and any((x[1]-x[0]) == 0 for x in mask) else None), + # only unmaksed VIEW on CONST replaces the ShapeTracker + (UPat(Ops.VIEW, src=(UPat((Ops.CONST, Ops.DEFINE_VAR), name="x"),), name="view"), + lambda x,view: x.replace(src=(x.src[0].replace(arg=x.st+view.st),)) if all(v.mask is None for v in (x.st+view.st).views) else None), +]) + +def reduce_push_add_ones(src:UOp, r:UOp, view:UOp): + # contiguous, expand, and the same with ones removed + if unwrap(view.st).contiguous and len(r.shape) < len(view.shape) and \ + tuple(x for x in r.shape if resolve(x != 1)) == tuple(x for x in view.shape if resolve(x != 1)): + new_shape: list[sint] = [] + new_reduce_axis = [] + if (contraction:=get_contraction_with_reduce(view.shape, r.shape, r.arg[1])) is None: return None + for i,pairs in enumerate(contraction): + new_shape_chunk = [view.shape[p] for p in pairs] + if i in r.arg[1]: + # if this is a reduce axis, we need a 1 in the view here to put it + assert len(new_shape_chunk) > 0 + new_shape += [1]*(len(pairs)-1) + [src.shape[i]] + new_reduce_axis.append(len(new_shape)-1) + else: + # otherwise, pass through the new_shape_chunk + new_shape += new_shape_chunk + ret = r.replace(src=(src.reshape(tuple(new_shape)),), arg=(r.arg[0], tuple(new_reduce_axis))+r.arg[2:]) + assert ret.shape == view.shape, f"shape mismatch on reduce_push_add_ones, {ret.shape} != {view.shape}" + return ret return None -replace_buffers = PatternMatcher([ - # replace ASSIGN with the target BUFFER - (UPat(Ops.ASSIGN, src=(UPat((Ops.BUFFER, Ops.LOAD)), UPat(Ops.KERNEL)), name="assign", allow_any_len=True), lambda assign: assign.src[0]), - # HACK: select the 0 branch of MSTACK (the device is wrong after this, is that okay?) - (UPat(Ops.MSTACK, name="x"), lambda x: x.src[0]), +view_left = merge_views+PatternMatcher([ + # view before elementwise and buffer ops + (UPat(Ops.VIEW, src=(UPat({*GroupOp.ALU, Ops.CAST, Ops.BITCAST, Ops.BIND, Ops.LOAD, Ops.STORE, Ops.VALID}, name="e"),), name="view"), + lambda e,view: e.replace(src=tuple(s.view(view.st) for s in e.src))), + # if there's ones added after reduce, put this before the reduce + (UPat(Ops.VIEW, src=(UPat(Ops.REDUCE_AXIS, src=(UPat.var("src"),), name="r"),), name="view"), reduce_push_add_ones), +]) + +def apply_swizzle(u:UOp) -> UOp: return graph_rewrite(u, view_left, name="Sub View Left") + +# change reduceop axes and input ShapeTrackers, view gets replaced with a reshape. +def swizzle_reduceop(r:UOp, src:UOp, view:UOp, fuse=False): + # contiguous and same size can push to children + # if there's a reduce child, shapes match with ones removed + if unwrap(view.st).contiguous and view.size == r.size and \ + (not (len(r.arg) == 3 and r.arg[2]) or # arg[2] = True is fuse marker + tuple((i,x) for i,x in enumerate(r.shape) if resolve(x != 1)) == tuple((i,x) for i,x in enumerate(view.shape) if resolve(x != 1))): + return None + # swizzle the input + input_st = ShapeTracker.from_shape(src.shape) + tmp = input_st.permute(tuple(i for i in range(len(input_st.shape)) if i not in r.axis_arg)+r.axis_arg) + prshape = prod(rshape:=tmp.shape[-len(r.axis_arg):]) + strides = strides_for_shape(rshape) + nv = [View.create(v.shape+rshape, tuple(x*prshape for x in v.strides)+strides, + v.offset*prshape, v.mask+tuple((0,s) for s in rshape) if v.mask is not None else None) for v in unwrap(view.st).views] + new_view = tmp + ShapeTracker(tuple(nv)) + swizzled_input = apply_swizzle(src.view(new_view)) + # create a new reduceop + new_axis = tuple(range(len(view.shape), len(view.shape) + len(r.axis_arg))) + if fuse: red = UOp(Ops.REDUCE_AXIS, r.dtype, (swizzled_input.fuse(),), (r.arg[0], new_axis, True)) + else: red = UOp(Ops.REDUCE_AXIS, r.dtype, (swizzled_input,), (r.arg[0], new_axis)) + return red.reshape(view.shape) + +def reduceop_view_right(src:UOp, v:UOp, r:UOp): + assert unwrap(v.st).contiguous and v.size == src.size, f"can't compute new axis for {src.shape} -> {r.shape}" + new_axis = [i for i,(s,u) in enumerate(zip(src.shape, r.shape)) if s != u] + return src.r(r.arg[0], tuple(new_axis)).reshape(r.shape) + +def elementwise_view_right(root:UOp): + if not (swizzles:=[x for x in root.src if x.op is Ops.VIEW and x.base.op not in ALWAYS_CONTIGUOUS]): return None + assert all_same([x.base.size for x in swizzles]), f"swizzle inputs must have the same size {swizzles}" + # place view after applying the elementwise op + new_st = ShapeTracker.from_shape(swizzles[0].base.shape) + new_src = [x.base if x.base.shape==new_st.shape else apply_swizzle(x.view(new_st)) for x in root.src] + # reshape to match downstream shapes + return root.replace(src=tuple(new_src)).reshape(root.shape) + +# push VIEW to children +view_right = merge_views+PatternMatcher([ + # push a non contiguous ShapeTracker through reduceop + (UPat(Ops.VIEW, src=(UPat(Ops.REDUCE_AXIS, src=(UPat.var("src"),), name="r"),), name="view"), swizzle_reduceop), + # apply view after reduceops + (UPat(Ops.REDUCE_AXIS, src=(UPat(Ops.VIEW, src=(UPat(GroupOp.All-ALWAYS_CONTIGUOUS, name="src"),), name="v"),), name="r"), reduceop_view_right), + # apply view after elementwise ops + (UPat(GroupOp.All-{Ops.SINK, Ops.GBARRIER, Ops.REDUCE_AXIS}, name="root"), elementwise_view_right), + # merge axes for double reduce (invert of SPLIT_REDUCEOP=1) + (UPat(Ops.REDUCE_AXIS, src=(UPat(Ops.REDUCE_AXIS, name="r1"),), name="r2"), + lambda r1,r2: r1.replace(arg=(r1.arg[0], r2.arg[1]+r1.arg[1])) if r1.arg[0] is r2.arg[0] else None), +]) + +# **** fix kernel AST + +add_buffer_ops = PatternMatcher([ # LOAD - (UPat(Ops.BUFFER, name="x"), lambda ctx,x: UOp(Ops.DEFINE_GLOBAL, x.dtype.ptr(x.size), (), ctx.index(x)).load()), - # no SINK for meta ops - (UPat(Ops.SINK, src=(UPat(Ops.CONTIGUOUS, src=(UPat(GroupOp.Meta, name="x"),),))), lambda x:x), + (UPat(Ops.BUFFER, name="x"), lambda ctx,x: UOp.load(UOp(Ops.DEFINE_GLOBAL, x.dtype.ptr(x.size), (), ctx.index(x)).view(x.st),)), # STORE (except for meta ops) + (UPat(Ops.SINK, src=(UPat(GroupOp.Meta, name="x"),)), lambda x:x), (UPat(Ops.SINK, src=UPat(GroupOp.All-{Ops.STORE}), name="sink"), lambda ctx,sink: - UOp.sink(*[UOp.store(UOp(Ops.DEFINE_GLOBAL, (s:=x.base).dtype.ptr(ctx[i].size), (), i).view(s.st), s) for i,x in enumerate(sink.src)], - arg=sink.arg)), + UOp.sink(*[UOp.store(UOp(Ops.DEFINE_GLOBAL, (s:=x.base).dtype.ptr(ctx[i].size), (), i).view(s.st), s) for i,x in enumerate(sink.src)])), + # passthrough ASSIGN + (UPat(Ops.ASSIGN, name="x"), lambda x: x.src[1]), + # VALID + (UPat(Ops.VIEW, src=(UPat.cvar(),), name="self"), UOp.valid), +]) + +def check_load_st(glbl:UOp, view:UOp): + if glbl.arg != 0 or (st:=unwrap(view.st)).contiguous: return + # if it has a single view and it becomes contiguous when you shrink expanded axes, it's fine + if len(st.views) == 1 and st.shrink(tuple((0,1) if st == 0 else (0,s) for s,st in zip(st.shape, st.views[0].strides))).contiguous: return + # if it has a single view and it's equal when you shrink a contig, it's fine + if len(st.views) == 1 and (mask:=st.views[0].mask) is not None and ShapeTracker.from_shape(st.shape).shrink(mask) == st.shrink(mask): return + # otherwise, it's not fine + raise RuntimeError("self operand of augmented assign must be contiguous.\nhelp: consider using .contiguous():\n" + +colored(" - a += a.T\n", "red")+colored(" + a += a.T.contiguous()", "green")) + +fix_kernel_ops = PatternMatcher([ # remove CONTIGUOUS/DEVICE from kernel AST (UPat((Ops.CONTIGUOUS, Ops.MSELECT), src=(UPat.var("x"),)), lambda x: x), (UPat(Ops.VIEW, src=(UPat(Ops.DEVICE),), name="view"), lambda view: view.replace(src=())), - # passthrough ASSIGN (but let MSTACK process first) - (UPat(Ops.ASSIGN, src=(UPat(GroupOp.All-{Ops.MSTACK}), UPat()), name="x"), lambda x: x.src[1]), - # remove any BINDs from VIEWS - (UPat(Ops.VIEW, src=(UPat(), UPat((Ops.BIND, Ops.DEFINE_VAR))), allow_any_len=True, name="x"), lambda x: x.replace(src=x.src[0:1])), - # remove any BINDs from DEFINE_VARs - (UPat(Ops.BIND, name="x"), lambda x: x.src[0]), - # remove BINDs from ShapeTrackers - (UPat(Ops.VIEW, name="x"), unbind_view), + # no ImageDType after index + (UPat(GroupOp.All-{Ops.DEFINE_GLOBAL, Ops.VIEW}, name="x"), lambda x: x.replace(dtype=x.dtype.base) if isinstance(x.dtype, ImageDType) else None), + # if this kernel also assigns to the loaded buffer, ensure we can index it correctly + (UPat(Ops.LOAD, src=(UPat.var("glbl").view(name="view"),)), check_load_st), +]) + +replace_globals = PatternMatcher([ + # replace ASSIGN with the target BUFFER + (UPat(Ops.ASSIGN, src=(UPat(Ops.BUFFER), UPat(Ops.KERNEL)), name="assign", allow_any_len=True), lambda assign: assign.src[0]), + # HACK: select the 0 branch of MSTACK (the device is wrong after this, is that okay?) + (UPat(Ops.MSTACK, name="x"), lambda x: x.src[0]), ]) def fix_kernel_ast(k:UOp) -> UOp|None: if k.arg.ast.op in GroupOp.Meta or all(s.op is Ops.STORE for s in k.arg.ast.src): return None + # replace global memory ops with the BUFFER they write to + ast = graph_rewrite(k.arg.ast, replace_globals, bottom_up=True, name="replace globals") + # push views to edges + ast = graph_rewrite(graph_rewrite(ast, view_left, name="Main View Left"), view_right, name="Main View Right") # replace buffer with define_global + add load/store last bufs = [] for s in k.src: - if s.op is Ops.BIND: continue s = s.buf_uop # traverse back through MSELECT and MSTACK. HACK: 0 branch of MSTACK only while s.op in {Ops.MSELECT, Ops.MSTACK}: s = s.src[0] bufs.append(s) - # replace global memory ops with the BUFFER they write to - # NOTE: merge_views is needed to unbind the reshapes - ast = graph_rewrite(k.arg.ast, merge_views+replace_buffers, bufs, bottom_up=True, name="replace buffers") - if ast.op is Ops.SINK and not all_same([x.device for x in k.src if x.op is not Ops.BIND]): + ast = graph_rewrite(ast, view_left+add_buffer_ops+fix_kernel_ops, bufs, bottom_up=True, name="replace buffer") + if ast.op is Ops.SINK and not all_same([x.device for x in k.src]): raise RuntimeError(f"all buffers must be on the same device: {tuple(b.buf_uop.buffer for b in k.src)}") return k.replace(arg=Kernel(ast, k.arg.metadata)) -create_ast = PatternMatcher([ - (UPat(Ops.KERNEL, name="k"), fix_kernel_ast), - (UPat(Ops.DEFINE_VAR, src=(UPat(),), allow_any_len=True, name="x"), lambda x: x.replace(src=())), -]) +create_ast = PatternMatcher([(UPat(Ops.KERNEL, name="k"), fix_kernel_ast),]) # ** add metadata of KERNEL outputs @@ -236,7 +344,7 @@ pm_fuse = PatternMatcher([ def do_fusion(x:UOp): found_contiguous = {} def gate_contiguous(x): - if is_contiguous:=(x.op is Ops.CONTIGUOUS): found_contiguous[x] = x.replace(src=(UOp(Ops.VIEW, arg=x.st), UOp.unique())) + if is_contiguous:=(x.op is Ops.CONTIGUOUS): found_contiguous[x] = x.replace(src=(UOp(Ops.VIEW, arg=x.st),)) return not is_contiguous x.toposort(gate=gate_contiguous) del gate_contiguous @@ -257,6 +365,8 @@ def fuse_arange(root:UOp): for u in toposort: for s in u.src: local_children.setdefault(s, []).append(u) fuse_rep: dict[UOp, UOp] = {} + # skip if root depends on aranges with different ndims. This can be improved + if any(len(set(dims)) > 1 for dims in zip(*[r.src[0].shape for r in local_arange])): return for r in local_arange: # skip if already fused if len(r.arg) > 2: continue @@ -276,8 +386,8 @@ do_fuse = PatternMatcher([ (UPat(Ops.REDUCE_AXIS, name="root"), fuse_arange), ]) -add_contiguous = PatternMatcher([(UPat(GroupOp.All-{Ops.CONTIGUOUS, Ops.ASSIGN}, name="x"), - lambda ctx,x: x.replace(tag=1).contiguous() if x in ctx and x.tag is None else None)]) +add_gbarrier = PatternMatcher([(UPat(GroupOp.All-{Ops.GBARRIER, Ops.ASSIGN}, name="x"), + lambda ctx,x: x.replace(tag=1).gbarrier() if x in ctx and x.tag is None else None)]) # TODO: get this from the device through GrouperOpts DEVICE_MAX_BUFS = {"METAL":32, "WEBGPU":8} @@ -289,32 +399,29 @@ def limit_bufs(root:UOp): # count number of unique buffers flowing into this op bufs: set[UOp] = set() def gate_input(u:UOp): - if (is_load:=(u.op in {Ops.BUFFER, Ops.CONTIGUOUS, Ops.ASSIGN, Ops.MSTACK})): bufs.add(u) + if (is_load:=(u.op in {Ops.BUFFER, Ops.GBARRIER, Ops.ASSIGN, Ops.MSTACK})): bufs.add(u) return not is_load root.toposort(gate=gate_input) # NOTE: this -1 is for the output buffer if len(bufs)>=MAX_BUFS-1: - return root.replace(src=tuple(s if s.base in bufs else s.replace(tag=1).contiguous() for s in root.src)) + return root.replace(src=tuple(s if s.base in bufs else s.replace(tag=1).gbarrier() for s in root.src)) -def view_add_srcs(x:UOp): - if len(avars:=x.arg.vars()) and len(x.src) == 1: - return x.replace(src=x.src+tuple(avars)) - return None - -finalize_contiguous = PatternMatcher([ +finalize_gbarrier = PatternMatcher([ # if an op takes more than one input, check combined LOADs don't exceed device limits (UPat(set.union(GroupOp.Binary, GroupOp.Ternary), name="root"), limit_bufs), - # merge contiguous - (UPat(Ops.CONTIGUOUS, src=(UPat(Ops.CONTIGUOUS),), name="x"), lambda x: x.src[0]), + # merge gbarrier + (UPat((Ops.GBARRIER, Ops.CONTIGUOUS), src=(UPat(Ops.GBARRIER),), name="x"), lambda x: x.src[0]), + # add contiguous to VIEW before GBARRIER + (UPat(Ops.GBARRIER, src=(UPat(Ops.VIEW,),), name="x"), lambda x: x.src[0].contiguous().gbarrier()), + # remove gbarrier on constants without a contiguous + (UPat(Ops.GBARRIER, src=(UPat(Ops.CONST),), name="x"), lambda x: x.src[0]), # simplify views (UPat(Ops.VIEW, src=(UPat.var('x')), name="v"), lambda x,v: x.view(new_st) if (new_st:=v.arg.simplify()) != v.arg else None), - # vars to views srcs - (UPat(Ops.VIEW, name="x"), view_add_srcs), ]) remove_tags = PatternMatcher([(UPat(GroupOp.All, name="x"), lambda x: x.replace(tag=None) if x.tag is not None else None)]) -@track_rewrites(name=lambda sink,ret: f"Schedule {pluralize('Kernel',len([u for u in ret[sink].toposort() if u.op is Ops.KERNEL]))}", replay=True) +@track_rewrites(name=lambda sink,ret: f"Schedule {pluralize('Kernel',len([u for u in ret[sink].toposort() if u.op is Ops.KERNEL]))}") def get_kernelize_map(sink:UOp) -> dict[UOp, UOp]: """ Function to transform the Tensor UOp graph into a version with Ops.KERNEL @@ -327,15 +434,17 @@ def get_kernelize_map(sink:UOp) -> dict[UOp, UOp]: """ # multi + merge_views + simplify - tensor_map = graph_rewrite_map(sink, multi_pm+do_fuse+merge_views+kernelize_sym+replace_contiguous, ctx={}, name="merge_views") + tensor_map = graph_rewrite_map(sink, multi_pm+do_fuse+merge_views+sym+replace_contiguous, ctx={}, name="merge_views") # display the cleaned up tensor graph if getenv("VIZ"): graph_rewrite(tensor_map[sink], PatternMatcher([]), name="View Tensor Graph") - # insert contiguous in places determined by the realize map + # insert gbarriers in places determined by the realize map realize_map = group_realizes(tensor_map[sink]) - tensor_map = graph_rewrite_map(tensor_map[sink], add_contiguous, ctx=realize_map, bottom_up=True, input_map=tensor_map, name="add_contiguous") - tensor_map = graph_rewrite_map(tensor_map[sink], finalize_contiguous+remove_tags, input_map=tensor_map, name="finalize_contiguous") + tensor_map = graph_rewrite_map(tensor_map[sink], add_gbarrier, ctx=realize_map, bottom_up=True, input_map=tensor_map, name="insert_gbarrier") + tensor_map = graph_rewrite_map(tensor_map[sink], finalize_gbarrier+remove_tags, input_map=tensor_map, name="finalize_gbarrier") + + # TODO: move view_left/view_right here # group into kernels (this is context-free) tensor_map = graph_rewrite_map(tensor_map[sink], create_kernels, input_map=tensor_map, name="create_kernels") @@ -361,6 +470,7 @@ def get_kernelize_map(sink:UOp) -> dict[UOp, UOp]: # display the final graph sched_sink = tensor_map[sink] if getenv("VIZ"): graph_rewrite(sched_sink, PatternMatcher([]), name="View Kernel Graph") + if getenv("VIZ"): graph_rewrite(sched_sink, PatternMatcher([]), name="View Memory Graph") # verify Kernels match the spec if __debug__: type_verify(list(sched_sink.toposort()), tensor_uop_spec) diff --git a/tinygrad_repo/tinygrad/schedule/multi.py b/tinygrad_repo/tinygrad/kernelize/multi.py similarity index 88% rename from tinygrad_repo/tinygrad/schedule/multi.py rename to tinygrad_repo/tinygrad/kernelize/multi.py index 4ec0f8e12..e0d065d68 100644 --- a/tinygrad_repo/tinygrad/schedule/multi.py +++ b/tinygrad_repo/tinygrad/kernelize/multi.py @@ -2,34 +2,8 @@ from typing import cast import functools, itertools, operator from tinygrad.helpers import all_same, all_int, prod, DEBUG, RING, getenv, unwrap from tinygrad.uop.ops import Ops, UOp, sint, PatternMatcher, UPat, GroupOp, resolve -from tinygrad.device import Device # *** allreduce implementation *** -def handle_allreduce_multirank(buf:UOp, red:UOp) -> UOp|None: - if not isinstance(buf.device, tuple): return None - - # Group buffers - groups: dict[int|None, list[UOp]] = {} - for i,dev in enumerate(buf.device): - groups.setdefault(Device[dev].group_id, []).append(buf.mselect(i)) - - # Put reduce leader of each group first - reduce_leaders = set(getenv("REDUCE_LEADERS", "").split(",")) - groups = {gid: sorted(bufs, key=lambda x: (x.device not in reduce_leaders, x.device)) for gid,bufs in groups.items()} - - # Skip if only one group or if every group has only one buffer - if len(groups) <= 1 or not any(len(g) > 1 for g in groups.values()): return None - - # Reduce inside each group - inner = [UOp(Ops.MSTACK, buf.dtype, tuple(bufs)).allreduce(red.arg, (cast(str, bufs[0].device),)).mselect(0) for bufs in groups.values()] - - # Allreduce across groups - outer = UOp(Ops.MSTACK, buf.dtype, tuple(inner)).allreduce(red.arg, tuple(buf.device for buf in inner)) - - # Broadcast back to all devices in the group - gid2bid = {Device[device].group_id: i for i,device in enumerate(outer.device)} - return outer.mselect(gid2bid[Device[red.device].group_id]).copy_to_device(red.device) if not isinstance(red.device, tuple) else \ - UOp(Ops.MSTACK, buf.dtype, tuple(outer.mselect(gid2bid[Device[device].group_id]).copy_to_device(device) for device in red.device)) def handle_allreduce(buf:UOp, red:UOp) -> UOp|None: if not isinstance(buf.device, tuple): return None @@ -110,7 +84,6 @@ def mstack_early_shrink(view:UOp, ms:UOp): return ms.replace(src=tuple(ret)) replace_allreduce = PatternMatcher([ - (UPat(Ops.ALLREDUCE, src=(UPat.var("buf"), UPat()), name="red"), handle_allreduce_multirank), (UPat(Ops.ALLREDUCE, src=(UPat.var("buf"), UPat()), name="red"), handle_allreduce), # BROADCAST: explicitly expand broadcast copies and combine with MSTACK (UPat(Ops.COPY, name="c", src=(UPat(GroupOp.All-{Ops.CONST}, name="x"), UPat(Ops.DEVICE))), lambda c,x: diff --git a/tinygrad_repo/tinygrad/nn/__init__.py b/tinygrad_repo/tinygrad/nn/__init__.py index bf6dca75a..b81399501 100644 --- a/tinygrad_repo/tinygrad/nn/__init__.py +++ b/tinygrad_repo/tinygrad/nn/__init__.py @@ -10,6 +10,7 @@ class BatchNorm: """ Applies Batch Normalization over a 2D or 3D input. + - Described: https://paperswithcode.com/method/batch-normalization - Paper: https://arxiv.org/abs/1502.03167v3 See: `Tensor.batchnorm` @@ -181,6 +182,7 @@ class GroupNorm: """ Applies Group Normalization over a mini-batch of inputs. + - Described: https://paperswithcode.com/method/group-normalization - Paper: https://arxiv.org/abs/1803.08494v3 ```python exec="true" source="above" session="tensor" result="python" @@ -211,6 +213,7 @@ class InstanceNorm: """ Applies Instance Normalization over a mini-batch of inputs. + - Described: https://paperswithcode.com/method/instance-normalization - Paper: https://arxiv.org/abs/1607.08022v3 ```python exec="true" source="above" session="tensor" result="python" @@ -237,6 +240,7 @@ class LayerNorm: """ Applies Layer Normalization over a mini-batch of inputs. + - Described: https://paperswithcode.com/method/layer-normalization - Paper: https://arxiv.org/abs/1607.06450v1 ```python exec="true" source="above" session="tensor" result="python" @@ -283,6 +287,7 @@ class RMSNorm: """ Applies Root Mean Square Normalization to input. + - Described: https://paperswithcode.com/method/rmsnorm - Paper: https://arxiv.org/abs/1910.07467 ```python exec="true" source="above" session="tensor" result="python" diff --git a/tinygrad_repo/tinygrad/nn/optim.py b/tinygrad_repo/tinygrad/nn/optim.py index e93a06a90..d08fec3b8 100644 --- a/tinygrad_repo/tinygrad/nn/optim.py +++ b/tinygrad_repo/tinygrad/nn/optim.py @@ -76,32 +76,21 @@ def SGD(params: list[Tensor], lr=0.001, momentum=0.0, weight_decay=0.0, nesterov Stochastic Gradient Descent (SGD) optimizer with optional momentum and weight decay. `classic` is a boolean flag that determines whether to use the popular momentum update rule or the classic momentum update rule. - """ - return LARS(params, lr, momentum, weight_decay, 0, None, nesterov, classic=classic, pre_wd=True, tcoef=0.0, fused=fused) -# Muon applies the newton schulz algorithm on gradient. also can include momentum, nesterov, and weight decay -def Muon(params: list[Tensor], lr=0.02, momentum=0.95, weight_decay=0.0, ns_steps=5, ns_params=(3.4445, -4.775, 2.0315), - nesterov=True, fused=FUSE_OPTIM): + - Described: https://paperswithcode.com/method/sgd """ - SGD with newton-schulz iteration and post momentum weight decay. - - - Described: https://kellerjordan.github.io/posts/muon/ - - Paper: https://arxiv.org/pdf/2502.16982 - """ - assert not fused, "FUSE_OPTIM not allowed for Muon optimizer" - return LARS(params, lr, momentum, weight_decay, ns_steps, ns_params, nesterov, classic=False, pre_wd=False, tcoef=0.0, fused=fused) + return LARS(params, lr, momentum, weight_decay, nesterov, classic, tcoef=0.0, fused=fused) class LARS(Optimizer): """ Layer-wise Adaptive Rate Scaling (LARS) optimizer with optional momentum and weight decay. + - Described: https://paperswithcode.com/method/lars - Paper: https://arxiv.org/abs/1708.03888v3 """ - def __init__(self, params:list[Tensor], lr=0.001, momentum=0.9, weight_decay=1e-4, ns_steps=0, ns_params=None, - nesterov=False, classic=True, pre_wd=True, tcoef=0.001, fused=FUSE_OPTIM): + def __init__(self, params:list[Tensor], lr=0.001, momentum=0.9, weight_decay=1e-4, nesterov=False, classic=True, tcoef=0.001, fused=FUSE_OPTIM): super().__init__(params, lr, fused) - self.momentum, self.wd, self.ns_steps, self.ns_params = momentum, weight_decay, ns_steps, ns_params - self.nesterov, self.classic, self.pre_wd, self.tcoef = nesterov, classic, pre_wd, tcoef + self.momentum, self.wd, self.nesterov, self.classic, self.tcoef = momentum, weight_decay, nesterov, classic, tcoef self.b = self._new_optim_param() if self.momentum else [] def _step(self, params:list[Tensor], grads:list[Tensor]) -> tuple[list[Tensor], list[Tensor]]: @@ -112,7 +101,7 @@ class LARS(Optimizer): r2 = g.square().sum().sqrt() r:Tensor|float = (r1 > 0).where((r2 > 0).where(self.tcoef * r1 / (r2 + self.wd * r1), 1.0), 1.0) else: r = 1.0 - if self.pre_wd and self.wd > 0: g = g + self.wd * t.detach() + g = g + self.wd * t.detach() # classic momentum does post learning rate update if self.classic: g = g * r * self.lr if self.momentum: @@ -120,9 +109,6 @@ class LARS(Optimizer): # the scheduler should detect this and just insert contiguous self.b[i].assign(self.momentum * self.b[i].contiguous() + g) # NOTE: self.b[i] is zero on the first run, no if required g = (g + self.momentum * self.b[i]) if self.nesterov else self.b[i] - if self.ns_params: g = g.reshape(g.shape[0], -1).newton_schulz(self.ns_steps, self.ns_params).reshape(g.shape) - # muon does post momentum weight decay - if not self.pre_wd and self.wd > 0: t = t.detach() * (1.0 - self.wd * self.lr) # popular momentum does pre learning rate update if not self.classic: g = g * r * self.lr ret.append((t.detach() - g).cast(t.dtype)) @@ -133,6 +119,7 @@ def AdamW(params: list[Tensor], lr=0.001, b1=0.9, b2=0.999, eps=1e-8, weight_dec """ AdamW optimizer with optional weight decay. + - Described: https://paperswithcode.com/method/adamw - Paper: https://arxiv.org/abs/1711.05101v3 """ return LAMB(params, lr, b1, b2, eps, weight_decay, adam=True, fused=fused) @@ -140,6 +127,7 @@ def Adam(params: list[Tensor], lr=0.001, b1=0.9, b2=0.999, eps=1e-8, fused=FUSE_ """ Adam optimizer. + - Described: https://paperswithcode.com/method/adam - Paper: https://arxiv.org/abs/1412.6980 """ return LAMB(params, lr, b1, b2, eps, 0.0, adam=True, fused=fused) @@ -148,6 +136,7 @@ class LAMB(Optimizer): """ LAMB optimizer with optional weight decay. + - Described: https://paperswithcode.com/method/lamb - Paper: https://arxiv.org/abs/1904.00962 """ def __init__(self, params: list[Tensor], lr=0.001, b1=0.9, b2=0.999, eps=1e-6, weight_decay=0.0, adam=False, fused=FUSE_OPTIM): diff --git a/tinygrad_repo/tinygrad/nn/state.py b/tinygrad_repo/tinygrad/nn/state.py index 110da5ecd..6b56a45b6 100644 --- a/tinygrad_repo/tinygrad/nn/state.py +++ b/tinygrad_repo/tinygrad/nn/state.py @@ -1,6 +1,6 @@ import json, pathlib, zipfile, pickle, tarfile, struct, functools, io from collections import OrderedDict -from typing import Any, Callable, BinaryIO, Iterable +from typing import Union, Optional, Any, Callable, BinaryIO, Iterable from tinygrad.tensor import Tensor from tinygrad.dtype import dtypes from tinygrad.helpers import prod, argsort, DEBUG, Timing, CI, unwrap, GlobalCounters, tqdm, round_up, T @@ -35,9 +35,9 @@ safe_dtypes = {"BOOL":dtypes.bool, "I8":dtypes.int8, "U8":dtypes.uint8, "I16":dt "I64":dtypes.int64, "U64":dtypes.uint64, "F16":dtypes.float16, "BF16":dtypes.bfloat16, "F32":dtypes.float32, "F64":dtypes.float64} inverse_safe_dtypes = {v:k for k,v in safe_dtypes.items()} -def accept_filename(func: Callable[[Tensor], T]) -> Callable[[Tensor|str|pathlib.Path], T]: +def accept_filename(func: Callable[[Tensor], T]) -> Callable[[Union[Tensor, str, pathlib.Path]], T]: @functools.wraps(func) - def wrapper(fn: Tensor|str|pathlib.Path) -> T: return func(Tensor(pathlib.Path(fn)) if not isinstance(fn, Tensor) else fn) + def wrapper(fn: Union[Tensor, str, pathlib.Path]) -> T: return func(Tensor(pathlib.Path(fn)) if not isinstance(fn, Tensor) else fn) return wrapper @accept_filename @@ -48,7 +48,7 @@ def safe_load_metadata(t:Tensor) -> tuple[Tensor, int, dict[str, Any]]: data_start = int.from_bytes(t[0:8].data(), "little") + 8 return t, data_start, json.loads(t[8:data_start].data().tobytes()) -def safe_load(fn:Tensor|str|pathlib.Path) -> dict[str, Tensor]: +def safe_load(fn:Union[Tensor, str, pathlib.Path]) -> dict[str, Tensor]: """ Loads a .safetensor file, returning the `state_dict`. @@ -61,7 +61,7 @@ def safe_load(fn:Tensor|str|pathlib.Path) -> dict[str, Tensor]: return { k: data[v['data_offsets'][0]:v['data_offsets'][1]].bitcast(safe_dtypes[v['dtype']]).reshape(v['shape']) for k, v in metadata.items() if k != "__metadata__" } -def safe_save(tensors:dict[str, Tensor], fn:str, metadata:dict[str, Any]|None=None): +def safe_save(tensors:dict[str, Tensor], fn:str, metadata:Optional[dict[str, Any]]=None): """ Saves a `state_dict` to disk in a .safetensor file with optional metadata. @@ -193,8 +193,8 @@ def torch_load(t:Tensor) -> dict[str, Tensor]: state_dict = nn.state.torch_load("test.pth") ``` """ - offsets: dict[str|int, int] = {} - lens: dict[str|int, int] = {} + offsets: dict[Union[str, int], int] = {} + lens: dict[Union[str, int], int] = {} def _rebuild_tensor_v2(storage, storage_offset, size, stride, requires_grad=None, backward_hooks=None, metadata=None): #print(storage, storage_offset, size, stride, requires_grad, backward_hooks, metadata) lens[storage[2]] = storage[4] * storage[1].itemsize @@ -274,9 +274,9 @@ def ggml_data_to_tensor(t: Tensor, n: int, ggml_type: int) -> Tensor: Converts ggml tensor data to a tinygrad tensor. Supported native types: float32 (id: 0), float16 (id: 1), int8 (id: 16), int16 (id: 17), int32 (id: 18) - Supported quantized types: Q4_0 (id: 2), Q4_1 (id: 3), Q8_0 (id: 8), Q6_K (id: 14), MXFP4 (id: 39) + Supported quantized types: Q4_0 (id: 2), Q4_1 (id: 3), Q8_0 (id: 8), Q6_K (id: 14) """ - # https://github.com/ggerganov/ggml/blob/323951f1bdcdfbd5b5ff3a9a7c3770e63b1a560e/include/ggml.h#L356 + # https://github.com/ggerganov/ggml/blob/6dccc647264f5429df2624f36138f601e7ce23e5/include/ggml.h#L356 # native types if (dtype := { 0: dtypes.float32, 1: dtypes.float16, 16: dtypes.int8, 17: dtypes.int16, 18: dtypes.int32 }.get(ggml_type)) is not None: @@ -288,7 +288,7 @@ def ggml_data_to_tensor(t: Tensor, n: int, ggml_type: int) -> Tensor: return t.unsqueeze(-1).expand((*t.shape,8//b)).idiv(shift_tensor).bitwise_and(bitmask).transpose(-1, -2).flatten(-2) # map to (number of elements, number of bytes) - if (nelements_nbytes := { 2: (32, 18), 3: (32, 20), 14: (256, 210), 8: (32, 34), 39: (32, 17) }.get(ggml_type)) is not None: + if (nelements_nbytes := { 2: (32, 18), 3: (32, 20), 14: (256, 210), 8: (32, 34) }.get(ggml_type)) is not None: blocks = t[:(n//nelements_nbytes[0])*nelements_nbytes[1]].reshape((-1, nelements_nbytes[1])) if ggml_type == 2: return (q_to_uint8(blocks[:,2:], 4).bitcast(dtypes.int8) - 8) * blocks[:,:2].bitcast(dtypes.float16).cast(dtypes.float32) if ggml_type == 3: @@ -300,17 +300,6 @@ def ggml_data_to_tensor(t: Tensor, n: int, ggml_type: int) -> Tensor: scales = blocks[:,192:208].bitcast(dtypes.int8).unsqueeze(-1).expand((-1, 16, 16)).reshape((-1, 256)) d = blocks[:,-2:].bitcast(dtypes.float16).cast(dtypes.float32).expand((-1, 256)) return d * (xl.bitwise_or(xh).bitcast(dtypes.int8) - 32).flatten(-2) * scales - if ggml_type == 39: - e_int = blocks[:, 0].cast(dtypes.int32) - d = ((e_int >= 2).cast(dtypes.float32) * (e_int.cast(dtypes.float32) - 128).exp2() + - (e_int == 1).cast(dtypes.float32) * 2.0**(-127) + - (e_int == 0).cast(dtypes.float32) * 2.0**(-128)).unsqueeze(-1) - codes = q_to_uint8(blocks[:, 1:17], 4) - sign = 1.0 - codes.rshift(3).cast(dtypes.float32) * 2.0 - exp, mant = codes.rshift(1).bitwise_and(0x3).cast(dtypes.float32), codes.bitwise_and(0x1).cast(dtypes.float32) - fp4_val = sign * ((exp != 0).cast(dtypes.float32) * (1.0 + 0.5 * mant) * (exp - 1.0).exp2() + - (exp == 0).cast(dtypes.float32) * 0.5 * mant) - return (fp4_val * d).flatten(-2)[:n] raise ValueError(f"GGML type '{ggml_type}' is not supported!") @accept_filename diff --git a/tinygrad_repo/tinygrad/opt/__init__.py b/tinygrad_repo/tinygrad/opt/__init__.py new file mode 100644 index 000000000..934b9f074 --- /dev/null +++ b/tinygrad_repo/tinygrad/opt/__init__.py @@ -0,0 +1,30 @@ +# opt opinionatedly transforms an ast into an optimized ast using either heuristics or beam search + +from tinygrad.opt.kernel import Kernel +from tinygrad.opt.heuristic import hand_coded_optimizations +from tinygrad.uop.ops import UOp +from tinygrad.helpers import NOOPT, BEAM, USE_TC, getenv +from tinygrad.renderer import Renderer + +def get_optimized_ast(ast:UOp, renderer:Renderer) -> UOp: + """ + Optimize an AST based on heuristics or BEAM search. + + Args: + ast: The Ops.SINK rooted AST + renderer: The renderer used to generate the code + + Returns: + The Ops.SINK rooted AST transformed to apply the opts and with a KernelInfo in the arg. + """ + + k = Kernel(ast, opts=renderer) + if ast.arg is not None and ast.arg.opts_to_apply is not None: k.apply_opts(ast.arg.opts_to_apply) + elif not NOOPT: + if not k.apply_tensor_cores(USE_TC.value): k.apply_opts(hand_coded_optimizations(k)) + if BEAM >= 1: + from tinygrad.opt.search import beam_search, bufs_from_lin + kb = Kernel(ast, opts=renderer) + rawbufs = bufs_from_lin(kb, allocate=False) + k = beam_search(kb, rawbufs, BEAM.value, bool(getenv("BEAM_ESTIMATE", 1))) + return k.get_optimized_ast() diff --git a/tinygrad_repo/tinygrad/opt/heuristic.py b/tinygrad_repo/tinygrad/opt/heuristic.py new file mode 100644 index 000000000..86bfea7af --- /dev/null +++ b/tinygrad_repo/tinygrad/opt/heuristic.py @@ -0,0 +1,133 @@ +import itertools +from tinygrad.opt.kernel import Kernel, Opt, OptOps, KernelOptError +from tinygrad.helpers import getenv, DEBUG, all_int, prod, NOLOCALS +from tinygrad.dtype import ImageDType +from tinygrad.uop.ops import Ops, resolve + +def hand_coded_optimizations(k:Kernel) -> list[Opt]: + # make a copy so it does not mutate the input + k = k.copy() + + # should use matvec - TODO: adjust/tune based on the wide vs tall/large vs small mat + MV_BLOCKSIZE, MV_THREADS_PER_ROW, MV_ROWS_PER_THREAD = getenv("MV_BLOCKSIZE", 4), getenv("MV_THREADS_PER_ROW", 8), getenv("MV_ROWS_PER_THREAD", 4) + if k.opts.has_local and getenv("MV",1) != 0 and (MV_BLOCKSIZE > 1 or MV_THREADS_PER_ROW > 1 or MV_ROWS_PER_THREAD > 1) and \ + k.reduceop is not None and k.reduceop.arg[0] is Ops.ADD and len(k.full_shape) >= 2 and k.opts.has_shared and \ + (mulop:=k.reduceop.src[0]).op is Ops.MUL and mulop.src[0].op is Ops.LOAD and mulop.src[1].op is Ops.LOAD: + st0, st1 = k.sts[k.bufs.index(mulop.src[0])], k.sts[k.bufs.index(mulop.src[1])] + strides0, strides1 = st0.real_strides(), st1.real_strides() + def has_expanded_axis(shape, strides): return any(resolve(s > 1) and not resolve(st != 0) for s,st in zip(shape,strides)) + if strides0[k.first_reduce] == 1 and not (has_expanded_axis(st0.shape, strides0) and has_expanded_axis(st1.shape, strides1)): + for global_idx in range(k.global_dims): + if k.full_shape[k.first_reduce]%MV_THREADS_PER_ROW == 0 and k.full_shape[global_idx]%(MV_BLOCKSIZE*MV_ROWS_PER_THREAD) == 0: + if DEBUG >= 3: + print(f"MATVEC: {k.full_shape=} {k.first_reduce=} {strides0=} {MV_BLOCKSIZE=} {MV_THREADS_PER_ROW=} {MV_ROWS_PER_THREAD=}") + if MV_THREADS_PER_ROW > 1: k.apply_opt(Opt(OptOps.GROUP, 0, MV_THREADS_PER_ROW)) + if MV_BLOCKSIZE > 1: k.apply_opt(Opt(OptOps.LOCAL, global_idx, MV_BLOCKSIZE)) + if MV_ROWS_PER_THREAD > 1: k.apply_opt(Opt(OptOps.UPCAST, global_idx, MV_ROWS_PER_THREAD)) + return k.applied_opts + + if k.opts.has_local and k.opts.has_shared and all_int(k.sts[0].shape[:k.first_reduce]): + # are we grouping? (requires local shape support) + if not [x for x in k.sts[0].unit_stride_axes() if x >= k.first_upcast and k.sts[0].shape[x]%4 == 0] and \ + k.first_reduce <= 2 and k.first_reduce < k.shape_len and prod(k.sts[0].shape[:k.first_reduce]) <= 2048: + # TODO: use 1024 if it's allowed in a smarter way + for sz in ([256, 16] if prod(k.sts[0].shape[:k.first_reduce]) <= 32 else [16]): + if all(st.shape[k.first_reduce] % sz == 0 or st.shape[k.first_reduce] == 1 for st in k.sts): + try: # may fail due to excessive smem usage + k.apply_opt(Opt(OptOps.GROUPTOP, 0, sz)) + break + except KernelOptError: pass + + # upcast float4 images + for buf_index,buf in enumerate(k.bufs): + unit_stride_axes_mul_4 = [i for i in k.sts[buf_index].unit_stride_axes(ignore_valid=True) if k.sts[buf_index].shape[i]%4 == 0] + if buf.src[0].dtype.__class__ is ImageDType: + #assert len(unit_stride_axes_mul_4) >= 1, f"needs a unit stride axis in {k.bufs[buf_index]}" + if len(unit_stride_axes_mul_4) and all(x < k.first_upcast for x in unit_stride_axes_mul_4): + if unit_stride_axes_mul_4[0] < k.first_reduce: + k.apply_opt(Opt(OptOps.UPCAST, unit_stride_axes_mul_4[0], 4)) + else: + k.apply_opt(Opt(OptOps.UNROLL, unit_stride_axes_mul_4[0]-k.first_reduce, 4)) + + # no more opt if we are grouping + if k.group_for_reduces: return k.applied_opts + + # **** below this line need to be optional and benchmarked **** + + # TODO: doing extra upcasts with images doesn't work for some reason (maybe has to do with to_image_idx) + # to trigger the above bug, remove prod(k.full_shape[k.first_upcast:]) from the below + # expression and run test/test_ops.py with IMAGE=2 + # if there are small dims with lots of valid masks, upcast them (they might be from Tensor.stack) + # this can be made much smarter + to_upcast: list[int] = [] + # upcast leading axes first (hack-ish for winograd; we actually want to upcast masked axes with low stride first) + for axis in range(k.first_reduce): + # we might want to be able to split axes that are masked, or refuse to merge them in simplify_merge_adjacent + # for now skip upcasting here if there is a symbolic axis + if isinstance(k.full_shape[axis], int) and k.full_shape[axis] <= 7 and any(st.axis_is_masked(axis) for st in k.sts) and \ + prod(k.full_shape[k.first_upcast:]) * prod(k.full_shape[j] for j in to_upcast) * k.full_shape[axis] <= 7 * 7: + if DEBUG >= 4: print(f"upcasting masked axis : {axis}") + to_upcast.append(axis) + for axis in to_upcast[::-1]: k.apply_opt(Opt(OptOps.UPCAST, axis, 0)) + + # potentially do more upcasts of non reduce axes based on a heuristic + is_dsp = k.opts is not None and k.opts.device == "DSP" + upcasted_axis: set[int] = set() + while resolve(prod(k.sts[0].shape[:k.first_reduce]) >= 1024): + xb_choices = [] + # consider all the non reduce axes, and a 3 or 4 reduce. (128 on the DSP) + for axis, upcast_amount in itertools.product(range(k.first_reduce), ([128] if not len(upcasted_axis) else []) if is_dsp else [3,4]): + # if we haven't upcasted it, it's not symbolic, it mods, and buffer has stride 0 on axis while having no stride 0 in the upcasted axis already + if axis not in upcasted_axis and isinstance(k.full_shape[axis], int) and k.full_shape[axis]%upcast_amount == 0 and \ + any(st.views[-1].strides[axis] == 0 and not any(x[1] == 0 for x in k.upcasted_axis(buf_index)) for buf_index, st in enumerate(k.sts)): + xb_choices.append((sum(st.views[-1].strides[axis]>0 for st in k.sts), + sum(st.views[-1].strides[axis] for st in k.sts), axis, upcast_amount)) + if xb_choices: + xb_choices = sorted(xb_choices) + if DEBUG >= 4: print(f"float4 merging axis : {xb_choices}") + k.apply_opt(Opt(OptOps.UPCAST, xb_choices[0][2], xb_choices[0][3])) + upcasted_axis.add(xb_choices[0][2]) + else: break + + # if last dim is small(ish) and it's a reduce dim, upcast the reduce (loop unrolling). no simplify needed since it's just an upcast. + if k.first_reduce < k.first_upcast and (prod(k.full_shape[k.first_upcast:]) <= 4 or \ + not any(x!=y for x,y in zip(k.sts[0].shape[k.first_upcast:], k.full_shape[k.first_upcast:]))) and \ + (k.upcasted == 0 or prod(k.full_shape[-k.upcasted:]) < 64): + if isinstance(s:=k.full_unupcasted_shape[-1], int) and s <= 32: # NOTE: cannot loop unroll symbolic axis + k.apply_opt(Opt(OptOps.UNROLL, len(k.full_unupcasted_shape)-1-k.first_reduce, 0)) + # if it's small, upcast a second reduce dimension too + if k.first_reduce < k.first_upcast and s <= 3 and isinstance(s2:=k.full_unupcasted_shape[-1], int) and s2 <= 3: + k.apply_opt(Opt(OptOps.UNROLL, len(k.full_unupcasted_shape)-1-k.first_reduce, 0)) + else: + for splits in [4]: + if k.full_unupcasted_shape[-1]%splits == 0: + k.apply_opt(Opt(OptOps.UNROLL, len(k.full_unupcasted_shape)-1-k.first_reduce, splits)) + break + + # if nothing at all is upcasted and it's easy to, do an upcast + for splits in [4]: + if k.upcasted == 0 and k.full_unupcasted_shape and k.full_unupcasted_shape[-1] % splits == 0: + k.apply_opt(Opt(OptOps.UPCAST, len(k.full_unupcasted_shape)-1, splits)) + + # **** local groups **** + + if k.opts.has_local: + if NOLOCALS and k.local_dims == 0 and not k.group_for_reduces: + k.apply_opt(Opt(OptOps.NOLOCALS)) + else: + # prioritize making expand axes local + local_axis_ranking = [(any(k.sts[buf_index].views[-1].strides[axis] == 0 for buf_index in range(len(k.sts))), axis) \ + for axis in range(len(k.full_shape[:k.first_reduce]))] + to_local: list[tuple[int, int]] = [] + for _, axis in sorted(local_axis_ranking, key=lambda x: (-x[0], -x[1])): + local_size = prod(sz for _, sz in to_local) + local_sz: int|None = next((x for x in ([32] * (axis == 0) + [16,8,4,3,2]) if k.full_shape[axis] % x == 0 and local_size * x <= 128), None) + if local_sz is not None: to_local.append((axis, local_sz)) + deleted_shape = 0 + for axis, local_sz in sorted(to_local[:3]): + axis = axis - deleted_shape + will_delete_shape = local_sz == k.full_shape[axis] + k.apply_opt(Opt(OptOps.LOCAL, axis, local_sz)) + if will_delete_shape: deleted_shape += 1 + + return k.applied_opts diff --git a/tinygrad_repo/tinygrad/codegen/opt/kernel.py b/tinygrad_repo/tinygrad/opt/kernel.py similarity index 53% rename from tinygrad_repo/tinygrad/codegen/opt/kernel.py rename to tinygrad_repo/tinygrad/opt/kernel.py index 2d3af8d3d..581b165e9 100644 --- a/tinygrad_repo/tinygrad/codegen/opt/kernel.py +++ b/tinygrad_repo/tinygrad/opt/kernel.py @@ -2,38 +2,20 @@ from __future__ import annotations import itertools, functools, math from dataclasses import dataclass from collections import defaultdict -from typing import cast, Final, Callable, Sequence -from enum import Enum, auto +from typing import Optional, cast, Final, Callable, Sequence -from tinygrad.uop.ops import GroupOp, KernelInfo, UOp, Ops, can_pad, resolve, Variable, sint, graph_rewrite, AxisType +from tinygrad.uop.ops import GroupOp, KernelInfo, UOp, Ops, can_pad, resolve, Variable, sint, graph_rewrite, smax from tinygrad.uop.spec import type_verify, ast_spec from tinygrad.device import Device -from tinygrad.codegen.opt.tc import TensorCore -from tinygrad.renderer import Renderer +from tinygrad.renderer import Renderer, TensorCore, ProgramSpec, Opt, OptOps from tinygrad.dtype import ImageDType -from tinygrad.helpers import all_same, colored, ansilen, dedup, prod, round_up, to_function_name, unwrap, argfix, DEBUG, TC_SELECT, TC_OPT, AMX +from tinygrad.helpers import all_same, colored, ansilen, dedup, prod, round_up, all_int, to_function_name, unwrap, DEBUG, TC_SELECT, TC_OPT, AMX from tinygrad.shape.shapetracker import ShapeTracker from tinygrad.shape.view import strides_for_shape, get_contraction -from tinygrad.codegen.opt.swizzler import view_left, view_left_through_load - -class OptOps(Enum): - TC = auto(); UPCAST = auto(); UNROLL = auto(); LOCAL = auto() # noqa: E702 - GROUP = auto(); GROUPTOP = auto(); NOLOCALS = auto(); PADTO = auto(); SWAP = auto() # noqa: E702 - def __lt__(self, x:OptOps): return self.value < x.value - -@dataclass(frozen=True, order=True) -class Opt: - op: OptOps - axis: int|None = None - arg: int|tuple|None = None - def __repr__(self): return f"Opt(op={self.op}, axis={self.axis}, arg={self.arg})" - -axis_letters = {AxisType.GLOBAL: "g", AxisType.LOCAL: "l", AxisType.LOOP: "L", AxisType.UPCAST: "u", - AxisType.GROUP_REDUCE: "G", AxisType.REDUCE: "R", AxisType.UNROLL: "r"} -axis_colors = {AxisType.GLOBAL: "blue", AxisType.LOCAL: "cyan", AxisType.LOOP: "WHITE", AxisType.UPCAST: "yellow", - AxisType.GROUP_REDUCE: "green", AxisType.REDUCE: "red", AxisType.UNROLL: "magenta"} +from tinygrad.kernelize.kernelize import view_left class KernelOptError(Exception): pass + def check(cond:bool, msg:str=""): if not cond: raise KernelOptError(msg) @@ -50,7 +32,7 @@ class TensorCoreOptions: self.axes, self.axes_exist = tuple(axes), tuple(axes_exist) class Kernel: - def __init__(self, ast:UOp, opts:Renderer|None=None): + def __init__(self, ast:UOp, opts:Optional[Renderer]=None): assert ast.op is Ops.SINK, ast.op self.ast = ast @@ -58,44 +40,43 @@ class Kernel: # verify AST matches the spec if __debug__: type_verify(list(self.ast.toposort()), ast_spec) + self.reduceops = [x for x in self.ast.toposort() if x.op is Ops.REDUCE_AXIS] + self.vars: list[Variable] = self.ast.variables() # NOTE: this requires a specific order with the [::-1], this is likely a bug - self.bufs: list[UOp] = [x for x in self.ast.toposort() if x.op in GroupOp.Buffer and x.st is not None][::-1] + self.bufs: list[UOp] = [x for x in self.ast.toposort() if x.op in GroupOp.Buffer][::-1] # create new shapetrackers inside this kernel, we will permute them self.sts: list[ShapeTracker] = [x.st_arg for x in self.bufs] # add the shapetrackers for each reduce # we use this to track which axes are reduced in each reduce - self.reduceops = [x for x in self.ast.toposort() if x.op is Ops.REDUCE_AXIS] for x in self.reduceops: self.sts.append(unwrap(x.st)) self.sts.append(unwrap(x.src[0].st)) # add a shapetracker to the end to track the full shape, with 0 strides so it can merge - full_shape = ast.full_shape - self.sts.append(ShapeTracker.from_shape(full_shape, (0,)*len(full_shape))) + self.sts.append(ShapeTracker.from_shape(tuple([smax(*s) for s in zip(*[x.shape for x in self.sts])]), (0,)*self.shape_len)) + + # move all reduce axes to the end + reduce = list(enumerate(zip(self.full_shape, self.output_shape))) + permute = tuple([i for i,(s,n) in reduce if not resolve(s != n)] + [i for i,(s,n) in reduce if resolve(s != n)]) + self.reshape_and_permute(None, permute) # parameters for optimization - self.tensor_core: TensorCore|None = None - self.tensor_core_opts: TensorCoreOptions|None = None - self.use_tensor_cores: int = 0 self.applied_opts: list[Opt] = [] - self.dont_use_locals = False - self.finalized: bool = False + self.group_for_reduces: int = 0 + self.upcasted: int = 0 + self.local_dims: int = 0 + self.tensor_core: Optional[TensorCore] = None + self.tensor_core_opts: Optional[TensorCoreOptions] = None + self.use_tensor_cores: int = 0 + self.dont_use_locals: bool = False # group simplifies self.simplify_ones() self.simplify_merge_adjacent() - # axis types - global_loops = AxisType.GLOBAL if self.opts.has_local else AxisType.LOOP - self.axis_types: list[AxisType] = [AxisType.REDUCE if resolve(x!=y) else global_loops for x,y in zip(self.output_shape, self.full_shape)] - - # confirm all reduce axes are at the end - if (final_reduces := [x for x in self.axis_types if x == AxisType.REDUCE]) and final_reduces != self.axis_types[-len(final_reduces):]: - raise RuntimeError(f"reduces are not at the end of the shape {self.full_shape} -> {self.output_shape}") - def copy(self): ret = type(self).__new__(type(self)) @@ -105,109 +86,121 @@ class Kernel: # things downstream of the AST ret.reduceops, ret.vars, ret.bufs = self.reduceops, self.vars, self.bufs ret.sts = self.sts[:] - ret.axis_types = self.axis_types[:] # parameters for optimizations - ret.applied_opts, ret.dont_use_locals = self.applied_opts[:], self.dont_use_locals + ret.applied_opts, ret.group_for_reduces, ret.upcasted, ret.local_dims, ret.dont_use_locals = \ + self.applied_opts[:], self.group_for_reduces, self.upcasted, self.local_dims, self.dont_use_locals ret.tensor_core, ret.tensor_core_opts, ret.use_tensor_cores = self.tensor_core, self.tensor_core_opts, self.use_tensor_cores - ret.finalized = self.finalized return ret + @property + def membufs(self) -> list[UOp]: return dedup([x.src[0].base for x in self.bufs if x.op in {Ops.LOAD, Ops.STORE}]) + + def upcasted_axis(self, i:int) -> list[tuple[int, Optional[sint], bool]]: + upcasted_shape, upcasted_stride = self.sts[i].shape[self.first_upcast:], self.sts[i].real_strides()[self.first_upcast:] + assert all_int(upcasted_shape), f"cannot upcast a symbolic amount {upcasted_shape=}" + return list(zip(upcasted_shape, upcasted_stride, + [x!=y for x,y in zip(self.sts[0].shape[self.first_upcast:], self.full_shape[self.first_upcast:])])) + + @property + def first_reduce(self) -> int: + return [resolve(x!=y) for x,y in zip(self.sts[0].shape[:self.first_upcast]+(0,), self.full_shape[:self.first_upcast]+(1,))].index(True) + + @property + def first_upcast(self) -> int: return self.shape_len-self.upcasted + @property def reduceop(self) -> UOp|None: return self.reduceops[0] if len(self.reduceops) > 0 else None + + @property + def output_shape(self) -> tuple[sint, ...]: return self.sts[0].shape + @property def full_shape(self) -> tuple[sint, ...]: return self.sts[-1].shape @property - def output_shape(self) -> tuple[sint, ...]: return self.sts[0].shape - @property - def shape_len(self) -> int: return len(self.full_shape) + def full_unupcasted_shape(self) -> tuple[sint, ...]: return self.full_shape[:self.first_upcast] - def axes_of(self, *axis_type:AxisType) -> list[int]: return [i for i,t in enumerate(self.axis_types) if t in argfix(axis_type)] @property - def upcasted(self) -> int: return len(self.axes_of(AxisType.UPCAST, AxisType.UNROLL)) - @property - def group_for_reduces(self) -> int: return len(self.axes_of(AxisType.GROUP_REDUCE)) + def shape_len(self) -> int: return len(self.sts[0].shape) - # heuristic helpers @property - def upcastable_dims(self) -> list[int]: return [i for i in self.axes_of(AxisType.GLOBAL, AxisType.LOCAL, AxisType.LOOP) \ - if isinstance(s:=self.full_shape[i], int) and s > 1] - @property - def unrollable_dims(self) -> list[int]: return [i for i in self.axes_of(AxisType.GROUP_REDUCE, AxisType.REDUCE) \ - if isinstance(s:=self.full_shape[i], int) and s > 1] - - # ******************** colors and names ******************** + def global_dims(self) -> int: return self.first_reduce-self.local_dims + # there's eight chunks of the shape + # blue -- global dims + # cyan -- local dims (warp ones first) + # *** self.first_reduce + # green -- reduce-local dims + # red -- reduce loops + # *** self.upcasted + # purple -- reduce upcasted + # yellow -- normal upcasted dimensions def colors(self) -> list[str]: - assert len(self.axis_types) == self.shape_len, "colors size mismatch" - return [axis_colors[x] if not self.dont_use_locals or not x == AxisType.GLOBAL else "BLUE" for x in self.axis_types] + # first non local non reduce dims are global (blue) + colors = ["blue"] * self.global_dims if not self.dont_use_locals else ["BLUE"] * self.global_dims + # after global are local_dims; warp ones used in tensor cores must be closest to first_reduce (cyan) + colors += ["cyan"] * self.local_dims + # between first_reduce and first_reduce + group_for_reduces, they are late upcasted (green) + colors += ["green"] * self.group_for_reduces + # between first_reduce + group_for_reduces and upcasted, they are reduce (red) + colors += ["red"] * (self.first_upcast - (self.first_reduce + self.group_for_reduces)) + # upcasted dimensions are reduce (magenta) or normal (yellow) + colors += ["magenta" if self.full_shape[i] != self.sts[0].shape[i] else "yellow" for i in range(self.first_upcast, self.shape_len)] + assert len(colors) == self.shape_len, "colors size mismatch" + return colors - def colored_shape(self, pad:int|None=None, dense=False) -> str: + def colored_shape(self, pad:Optional[int]=None, dense=False) -> str: shape_strs = [(s if dense else f"{s:4d}") if isinstance(s, int) else s.render() for s in self.full_shape] ret = ' '.join(colored(s, color) for s,color in zip(shape_strs, self.colors())) if pad: ret += ' '*(pad-ansilen(ret)) return ret - kernel_cnt: Final[defaultdict[str, int]] = defaultdict(int) - @functools.cached_property - def name(self) -> str: - # kernel name (before late upcast) - kernel_type = "r" if self.reduceop is not None else ("C" if all(x.op is Ops.SINK or x.op in GroupOp.Buffer for x in self.ast.toposort()) else "E") - suffix = colored('_', 'BLACK').join([colored(x.render() if isinstance(x, UOp) else str(x), c) for x,c in zip(self.full_shape, self.colors())]) - name = kernel_type + (f"{len(self.ast.src)}" if len(self.ast.src) > 1 else "") + "_" + suffix - - # name the function something unique - Kernel.kernel_cnt[(function_name := to_function_name(name))] += 1 - num = f"n{Kernel.kernel_cnt[function_name]-1}" if Kernel.kernel_cnt[function_name] > 1 else "" - return name + colored(num, 'BLACK') - # ******************** base simplifiers ******************** # apply reshape and permute to all shapetrackers - def reshape(self, new_shape_fxn:Callable[[tuple[sint, ...]], Sequence[sint]]): - self.sts = [st.reshape(tuple(new_shape_fxn(st.shape))) for st in self.sts] - def permute(self, new_axes:Sequence[int]): self.sts = [st.permute(tuple(new_axes)) for st in self.sts] + def reshape_and_permute(self, new_shape_fxn:Optional[Callable[[tuple[sint, ...]], Sequence[sint]]], axis:Optional[Sequence[int]]): + def reshape(st:ShapeTracker): return st.reshape(tuple(new_shape_fxn(st.shape))) if new_shape_fxn is not None else st + def permute(st:ShapeTracker): return st.permute(tuple(axis)) if axis is not None else st + self.sts = [permute(reshape(st)) for st in self.sts] + + # drops the final dimension + def upcast(self): + check(self.full_shape[-1] != 1, "can't upcast a dimension with size 1") + self.upcasted += 1 # axis : the axis to pull from # amount : the amount to take # top : if you want to pull that amount from the top - # insert_at : place to insert the new stuff - def shift_to(self, axis:int, amount:int, new_type:AxisType, top:bool=False, insert_at:int|None=None) -> int: - if insert_at is None: insert_at = self.shape_len - self.axis_types.insert(insert_at, new_type) + # insert_before : place to insert the new stuff + def shift_to(self, axis, amount, top=False, insert_before=None): + if insert_before is None: insert_before = self.shape_len move_axis = axis if top else axis+1 - if move_axis < insert_at: insert_at += 1 - def new_shape_fxn(x): return x[0:axis] + (((amount,x[axis]//amount) if top else (x[axis]//amount,amount)) if x[axis] > 1 else (1,1)) + x[axis+1:] - new_axes = [i for i in range(insert_at) if i != move_axis]+[move_axis]+[i for i in range(insert_at, self.shape_len+1) if i != move_axis] - self.reshape(new_shape_fxn) - self.permute(new_axes) - return insert_at + if move_axis < insert_before: insert_before += 1 + self.reshape_and_permute( + lambda x: x[0:axis] + (((amount, x[axis]//amount) if top else (x[axis]//amount, amount)) if x[axis] > 1 else (1,1)) + x[axis+1:], + [i for i in range(insert_before) if i != move_axis] + [move_axis] + [i for i in range(insert_before, self.shape_len+1) if i != move_axis]) # ******************** complex simplifiers ******************** def simplify_ones(self) -> bool: # remove places where the shape is all ones - if any(all_ones:=[s==1 for s in self.full_shape]): - if hasattr(self, 'axis_types'): - self.axis_types = [x for i,x in enumerate(self.axis_types) if not all_ones[i]] - self.reshape(lambda shape: [x for i,x in enumerate(shape) if not all_ones[i]]) - return True - return False + # TODO: this should be factored in to multi shape stride + if self.shape_len == 0: return False + all_ones = [s==1 for s in self.full_shape] + self.local_dims -= sum(all_ones[self.first_reduce-self.local_dims:self.first_reduce]) + self.upcasted -= sum(all_ones[self.first_upcast:]) # TODO: no necessary since upcasted axis can't be un-upcasted + self.reshape_and_permute(lambda shape: [x for i,x in enumerate(shape) if not all_ones[i]], None) + return any(all_ones) def simplify_merge_adjacent(self): - assert not hasattr(self, 'axis_types'), "don't call this after init" if self.shape_len == 0: return shapes, strides = [x.shape for x in self.sts], [x.real_strides() for x in self.sts] - # NOTE: we can't use self.first_reduce yet - first_reduce = [resolve(x!=y) for x,y in zip(self.output_shape+(0,), self.full_shape+(1,))].index(True) # if it's an image, insert fake strides such that this fusion doesn't happen across image axes - # TODO: remove membufs - membufs = dedup([x.src[0].base for x in self.bufs if x.op in {Ops.LOAD, Ops.STORE}]) - if isinstance(membufs[0].base.dtype, ImageDType): - base_shape = membufs[0].base.dtype.shape + if isinstance(self.membufs[0].dtype, ImageDType): + base_shape = self.membufs[0].dtype.shape if shape_idx_groups := get_contraction(self.output_shape, base_shape): special_strides: tuple[sint, ...] = tuple() for i,g in enumerate(shape_idx_groups): @@ -230,7 +223,7 @@ class Kernel: si, sti, last_st = s[i], st[i], ret[-1][1] can_merge.append((sti is not None) and ((sti != 0 and last_st == si*sti) or (sti == 0 and last_st == 0))) # more can merge than this - mergeable = all(can_merge) and i != first_reduce + mergeable = all(can_merge) and i != self.first_reduce for j,(s,st) in enumerate(zip(shapes, strides)): if mergeable: rets[j][-1] = (rets[j][-1][0] * s[i], st[i]) else: rets[j].append((s[i], st[i])) @@ -238,123 +231,16 @@ class Kernel: # do the reshapes for i,x in enumerate(rets[:len(self.sts)]): self.sts[i] = self.sts[i].reshape(tuple([y[0] for y in x])) - # ******************** apply optimizations ******************** + # ******************** high level optimizers ******************** - def real_axis(self, op:OptOps, axis:int|None): - try: - if axis is None: return -1 - if op is OptOps.UNROLL: return self.unrollable_dims[axis] - if op in {OptOps.GROUP, OptOps.GROUPTOP}: return self.axes_of(AxisType.REDUCE)[axis] - check(axis < self.shape_len, f"invalid axis on {axis=} {op=} {self.shape_len=}") - return axis - except IndexError as e: raise KernelOptError from e - - def apply_opt(self, opt:Opt, append_opt:bool=True) -> int|None: - if self.finalized: raise RuntimeError("can't optimize Kernel after it's finalized") - if self.dont_use_locals: check(opt.op not in {OptOps.LOCAL, OptOps.GROUP, OptOps.GROUPTOP}, "not using locals") - - if opt.op is OptOps.TC: - check(len(self.applied_opts) == 0, "tensor core opts must be first") # TODO: things like PADTO might be fine - check(len(self.opts.tensor_cores) > 0, "must have tensor cores") - check(opt.axis is not None, "tensor core opts must have an axis") - check(opt.arg is not None and isinstance(opt.arg, tuple) and len(opt.arg) == 3, "tensor core opts must have valid arg") - check(-1 <= (tc_select:=cast(tuple, opt.arg)[0]) < len(self.opts.tensor_cores), "tensor core opts must have valid tc_select") - check(0 <= (tc_opt:=cast(tuple, opt.arg)[1]) <= 2, "tensor core opts must have valid tc_opt") - check(0 < (use_tensor_cores:=cast(tuple, opt.arg)[2]) <= 2, "use_tensor_cores value is not valid") - check(self._apply_tc_opt(use_tensor_cores, cast(int, opt.axis), tc_select, tc_opt), "no tensor core available") - self.applied_opts.append(opt) - return None - - axis = self.real_axis(opt.op, opt.axis) - - if opt.op is OptOps.SWAP: amt = self.real_axis(opt.op, cast(int, opt.arg)) # arg is an axis in the SWAPs - elif opt.arg is not None: - check(isinstance(opt.arg, int), "arg should be int") - amt = arg if (arg:=cast(int, opt.arg)) != 0 else self.full_shape[axis] - check(isinstance(amt, int) and amt != 1, f"shift/padto of {amt=}, 1 or symbolic amount is meaningless") - if opt.op is not OptOps.PADTO: - # we check both the full_shape and each shape - check(self.full_shape[axis] % amt == 0, f"no longer valid shift {self.full_shape[axis]=}, {amt=}") - for st in self.sts: check(st.shape[axis] == 1 or st.shape[axis] % amt == 0, f"no longer valid shift {st.shape[axis]=}, {amt=}") - else: amt = -1 - - if self.reduceop is not None and (opt.op in {OptOps.GROUP, OptOps.GROUPTOP} or \ - (self.group_for_reduces and opt.op not in {OptOps.NOLOCALS, OptOps.PADTO})): - acc_sz = self.reduceop.dtype.itemsize - upcast_sz = prod([self.full_shape[a] for a in self.axes_of(AxisType.UPCAST)]) - local_sz = prod([self.full_shape[a] for a in self.axes_of(AxisType.LOCAL)]) - smem_sz = amt*acc_sz*upcast_sz*local_sz - check(smem_sz <= self.opts.shared_max, f"exceeds maximum shared memory size: needs {smem_sz}, max {self.opts.shared_max}") - - new_axis = None - if opt.op is OptOps.LOCAL: # cyan - # NOTE: LLVM/CPU can use locals too, but they are treated the same as globals (still helpful for L1 cache) - # it's disabled for now since it makes BEAM slow for little gain - check(self.opts.has_local, "target does not support local") - check(self.axis_types[axis] is AxisType.GLOBAL, "local is for globals") - new_axis = self.shift_to(axis, amt, AxisType.LOCAL, insert_at=max(self.axes_of(AxisType.GLOBAL, AxisType.LOCAL))+1) - elif opt.op in {OptOps.GROUP, OptOps.GROUPTOP}: # green - check(self.opts.has_local and self.opts.has_shared, "target does not support local or shared mem") - check(self.axis_types[axis] is AxisType.REDUCE, "must be reduce axis to group") - check(not self.tensor_core, "can't group with tensor cores") - check(len(reduce_axes:=[i for r in self.reduceops for i in r.axis_arg]) == len(set(reduce_axes)), "can't group with parallel reduces") - new_axis = self.shift_to(axis, amt, AxisType.GROUP_REDUCE, top=(opt.op is OptOps.GROUPTOP), insert_at=min(self.axes_of(AxisType.REDUCE))) - elif opt.op is OptOps.UNROLL: # purple - check(self.axis_types[axis] not in (AxisType.UPCAST, AxisType.UNROLL), "can't upcasted already upcasted") - check(amt <= 32, "don't unroll more than 32") - new_axis = self.shift_to(axis, amt, AxisType.UNROLL, insert_at=None) - elif opt.op is OptOps.UPCAST: # yellow - check(axis in self.upcastable_dims, f"{axis=} not in {self.upcastable_dims=}") - # NOTE: assume the first get_local_axes() LOCAL are for TC - check(not (self.tensor_core and axis in self.axes_of(AxisType.LOCAL)[:len(self.tensor_core.get_local_axes())]), "can't upcast TC locals") - check((self.opts is not None and self.opts.device == "DSP") or amt <= 16, "don't upcast more than 16") - new_axis = self.shift_to(axis, amt, AxisType.UPCAST, - insert_at=max(self.axes_of(AxisType.GLOBAL, AxisType.LOCAL, AxisType.LOOP, AxisType.UPCAST))+1) - elif opt.op is OptOps.NOLOCALS: - check(self.opts.has_local and not self.dont_use_locals, "NOLOCALS is meaningless if target does not support local or already not using locals") - check(AxisType.LOCAL not in self.axis_types and self.group_for_reduces == 0, "can't have no locals with locals") - self.dont_use_locals = True - elif opt.op is OptOps.SWAP: - check(axis < amt, f"swap is only for axis < amt, getting {amt=}, {axis=}") - check(self.axis_types[axis]==self.axis_types[amt]==AxisType.GLOBAL, f"swap is for globals {self.axis_types[axis]=}, {self.axis_types[amt]=}") - permute = list(range(self.shape_len)) - permute[axis], permute[amt] = permute[amt], permute[axis] - self.permute(tuple(permute)) - elif opt.op is OptOps.PADTO: - check(not self.vars, "does not work with symbolic shape") - check(self.axis_types[axis] not in (AxisType.UPCAST, AxisType.UNROLL), "cannot pad upcasted") - # ok to pad SUM if all parent ALU ops have f(0) = 0 - if (r:=self.reduceop) is not None and self.axis_types[axis] in (AxisType.GROUP_REDUCE, AxisType.REDUCE): - check(r.arg[0] is Ops.ADD and can_pad(r, {}), f"cannot pad {r}") - padded = False - for i,st in enumerate(self.sts): - if (s:=st.shape[axis]) == 1: continue # reduced - check(s > amt//4, f"pad adds more than quadruple the work {st.shape[axis]=} > {amt//4=}") - if (ru := round_up(cast(int, s), amt) - s): - # pad right seems to be faster - self.sts[i] = st.pad(((0,0),) * axis + ((0,ru),) + ((0,0),) * (len(st.shape)-axis-1)) - padded = True - check(padded, "nothing was padded") - - if append_opt: self.applied_opts.append(opt) - if self.simplify_ones() and self.tensor_core_opts: - self.tensor_core_opts.fix_axes(axis) # fix up axes in TC opts if required after simplify_ones() - return new_axis - - def apply_opts(self, opts:Sequence[Opt]) -> Kernel: - for opt in opts: self.apply_opt(opt) - return self - - # **** kernel outputs, mostly tensor cores **** - - def _create_tc_opts(self, reduceop:UOp, tc:TensorCore, axis:int, opt_level:int) -> TensorCoreOptions|None: + def _create_tc_opts(self, reduceop:UOp, tc:TensorCore, axis:int, opt_level:int) -> Optional[TensorCoreOptions]: has_cast = tc.dtype_in != tc.dtype_out if has_cast and not (reduceop.src[0].op is Ops.CAST and reduceop.src[0].dtype == tc.dtype_out): return None mul_op = reduceop.src[0].src[0] if has_cast else reduceop.src[0] if mul_op.op is not Ops.MUL: return None - def buf_index(src:UOp) -> int|None: + def buf_index(src:UOp) -> Optional[int]: # TODO: apply tc even if the sources are not from LOAD if src.op is Ops.LOAD and src.dtype == tc.dtype_in: return self.bufs.index(src) try: @@ -364,11 +250,11 @@ class Kernel: if (buf0:=buf_index(mul_op.src[0])) is None or (buf1:=buf_index(mul_op.src[1])) is None: return None buf0_strides, buf1_strides = self.sts[buf0].real_strides(), self.sts[buf1].real_strides() - axis_buf0 = [(i,self.full_shape[i],buf1_strides[i]) for i in self.upcastable_dims if buf0_strides[i] == 0] - axis_buf1 = [(i,self.full_shape[i],buf0_strides[i]) for i in self.upcastable_dims if buf1_strides[i] == 0] - if not (axis_buf0 and axis_buf1 and (len(self.axes_of(AxisType.GROUP_REDUCE, AxisType.REDUCE)) == 1 or (opt_level >= 1))): return None + axis_buf0 = [(i,self.full_shape[i],buf1_strides[i]) for i,s in enumerate(buf0_strides[:self.first_reduce]) if s == 0] + axis_buf1 = [(i,self.full_shape[i],buf0_strides[i]) for i,s in enumerate(buf1_strides[:self.first_reduce]) if s == 0] + if not (axis_buf0 and axis_buf1 and ((self.shape_len-self.first_reduce) == 1 or (opt_level >= 1))): return None - axis_choices = list(itertools.product(axis_buf0, axis_buf1, self.axes_of(AxisType.GROUP_REDUCE, AxisType.REDUCE))) + axis_choices = list(itertools.product(axis_buf0, axis_buf1, range(self.first_reduce, self.shape_len))) if not (axis < len(axis_choices)): return None s0, s1, s2 = axis_choices[-(axis+1)][0][0], axis_choices[-(axis+1)][1][0], axis_choices[-(axis+1)][2] # s0 is n, s1 is m, s2 is k @@ -382,9 +268,9 @@ class Kernel: tensor_cores = self.opts.tensor_cores if tc_select == -1 else [self.opts.tensor_cores[tc_select]] for tc in tensor_cores: tensor_core_opts = [self._create_tc_opts(reduceop, tc, axis, opt_level) for reduceop in self.reduceops] - if tensor_core_opts[0] is None: continue # can only fuse reduces with the same tc options assert all_same(tensor_core_opts) + if tensor_core_opts[0] is None: continue self.tensor_core_opts = tc_opts = tensor_core_opts[0] # attempt to pad the tensor axes that require it @@ -392,14 +278,15 @@ class Kernel: for axis, dim in tc_opts.axis_pads: self.apply_opt(Opt(OptOps.PADTO, axis, dim), append_opt=False) # PADTO might fail except KernelOptError: continue # tensor core -- unroll the reduce dim (K), upcast and local the inner and outer dims (N, M) + for dim, amt in tc.get_reduce_axes(): self.apply_opt(Opt(OptOps.UNROLL, tc_opts.axes[2]-self.first_reduce, amt), append_opt=False) for opt in tc.opts: self.apply_opt(Opt({"u":OptOps.UPCAST, "l":OptOps.LOCAL}[opt[0]], tc_opts.axes[int(opt[1])], 2), append_opt=False) - for dim, amt in tc.get_reduce_axes(): self.apply_opt(Opt(OptOps.UNROLL, 0, amt), append_opt=False) # TODO: this should be the reduce, not 0 self.tensor_core = tc self.use_tensor_cores = use_tensor_cores # TC=2 will do the shape ops without the WMMA return True return False - def apply_tensor_cores(self, use_tensor_cores=1, extra_opts:list[Opt]|None=None, axis:int=0, tc_select:int|None=None, tc_opt:int|None=None) -> bool: + def apply_tensor_cores(self, use_tensor_cores=1, extra_opts:Optional[list[Opt]]=None, axis:int=0, tc_select:Optional[int]=None, + tc_opt:Optional[int]=None) -> bool: """ Attempts to apply a tensor core optimization to the kernel. If one exists and applies properly, return true, otherwise return false. Tensor cores are optimized instructions that matrix multiply-accumulate across a wave of threads: D(M, N) = A(M, K) * B(K, N) + C(M, N). @@ -408,6 +295,7 @@ class Kernel: 0: will disable any tensor core matching 1: enable tensor cores 2: apply tensor core shape but don't use UOp.WMMA + 3: emulate tensor cores with local memory extra_opts -- additional Opt's to apply after the tensor core instead of the hand-coded additional Opt's (default None) tc_select -- specifies which tensor core(s) to use for optimization (default -1) -1: iterates through all available tensor cores in order and uses the first one that matches the requirements (dims and dtypes) @@ -438,59 +326,212 @@ class Kernel: except KernelOptError: return False - # strings like ['g0', 'g1', 'l0', 'l1', 'l2', 'l3', 'l4', 'l5', 'R0', 'r0', 'r1', 'r2', 'u0', 'u1', 'u2'] - def shape_str(self) -> list[str]: - ret: list[str] = [] - cnt: dict[AxisType, int] = {} - for x in self.axis_types: - cnt[x] = (cnt[x] + 1) if x in cnt else 0 - ret.append(f"{axis_letters[x]}{cnt[x]}") - return ret - def shape_str_to_axis(self, nms:list[str]) -> tuple[int, ...]: return tuple([self.shape_str().index(x) for x in nms]) + def real_axis(self, opt:Opt): + if opt.axis is None: return -1 + if opt.op is OptOps.UNROLL: return self.first_reduce+opt.axis + if opt.op in {OptOps.GROUP, OptOps.GROUPTOP}: return self.first_reduce+self.group_for_reduces+opt.axis + return opt.axis - def get_optimized_ast(self, name_override:str|None=None) -> UOp: + def apply_opt(self, opt:Opt, append_opt:bool=True): + if self.dont_use_locals: check(opt.op not in {OptOps.LOCAL, OptOps.GROUP, OptOps.GROUPTOP}, "not using locals") + + if opt.op is OptOps.TC: + check(len(self.applied_opts) == 0, "tensor core opts must be first") # TODO: things like PADTO might be fine + check(len(self.opts.tensor_cores) > 0, "must have tensor cores") + check(opt.axis is not None, "tensor core opts must have an axis") + check(opt.arg is not None and isinstance(opt.arg, tuple) and len(opt.arg) == 3, "tensor core opts must have valid arg") + check(-1 <= (tc_select:=cast(tuple, opt.arg)[0]) < len(self.opts.tensor_cores), "tensor core opts must have valid tc_select") + check(0 <= (tc_opt:=cast(tuple, opt.arg)[1]) <= 2, "tensor core opts must have valid tc_opt") + check(0 < (use_tensor_cores:=cast(tuple, opt.arg)[2]) <= 3, "use_tensor_cores value is not valid") + check(self._apply_tc_opt(use_tensor_cores, cast(int, opt.axis), tc_select, tc_opt), "no tensor core available") + self.applied_opts.append(opt) + return + + axis = self.real_axis(opt) + check(axis < len(self.full_shape), "invalid axis") + + if opt.op is OptOps.SWAP: amt = cast(int, opt.arg) # arg is an axis in the SWAPs + elif opt.arg is not None: + check(isinstance(opt.arg, int), "arg should be int") + amt = arg if (arg:=cast(int, opt.arg)) != 0 else self.full_shape[axis] + check(isinstance(amt, int) and amt != 1, f"shift/padto of {amt=}, 1 or symbolic amount is meaningless") + if opt.op is not OptOps.PADTO: check(self.full_shape[axis] % amt == 0, f"no longer valid shift {self.full_shape[axis]=}, {amt=}") + else: amt = -1 + + if self.reduceop is not None and (opt.op in {OptOps.GROUP, OptOps.GROUPTOP} or \ + (self.group_for_reduces and opt.op not in {OptOps.NOLOCALS, OptOps.PADTO})): + acc_sz = self.reduceop.dtype.itemsize + upcast_sz = prod([a for a,b in zip(self.full_shape[self.first_upcast:], self.sts[0].shape[self.first_upcast:]) if a == b]) + local_sz = prod(self.full_shape[self.first_reduce-self.local_dims:self.first_reduce+self.group_for_reduces]) + smem_sz = amt*acc_sz*upcast_sz*local_sz + check(smem_sz <= self.opts.shared_max, f"exceeds maximum shared memory size: needs {smem_sz}, max {self.opts.shared_max}") + + if opt.op is OptOps.LOCAL: # cyan + # NOTE: LLVM/CPU can use locals too, but they are treated the same as globals (still helpful for L1 cache) + # it's disabled for now since it makes BEAM slow for little gain + check(self.opts.has_local, "target does not support local") + check(axis < self.global_dims, "local is for globals") + self.shift_to(axis, amt, insert_before=self.first_reduce) + self.local_dims += 1 + elif opt.op in {OptOps.GROUP, OptOps.GROUPTOP}: # green + check(self.opts.has_local and self.opts.has_shared, "target does not support local or shared mem") + check(self.first_reduce + self.group_for_reduces <= axis < self.first_upcast, "must be reduce axis to group") + check(not self.tensor_core, "can't group with tensor cores") + check(len(reduce_axes:=[i for r in self.reduceops for i in r.axis_arg]) == len(set(reduce_axes)), "can't group with parallel reduces") + self.shift_to(axis, amt, top=(opt.op is OptOps.GROUPTOP), insert_before=self.first_reduce + self.group_for_reduces) + self.group_for_reduces += 1 + elif opt.op is OptOps.UNROLL: # purple + check(axis < self.first_upcast, "can't upcasted already upcasted") + check(amt <= 32, "don't unroll more than 32") + # TODO: fix upcast_count to put purples before yellows. broken because of METAL tensor cores + #upcast_count = sum(x == y for x,y in zip(self.full_shape[-self.upcasted:], self.output_shape[-self.upcasted:])) if self.upcasted else 0 + #self.shift_to(axis, amt, insert_before=None if upcast_count == 0 else self.shape_len-upcast_count) + if self.full_shape[axis] == amt and axis == self.first_reduce: self.local_dims += 1 # first_reduce will ++, so offset loss in simplify_ones + if self.full_shape[axis] == amt and axis < self.first_reduce+self.group_for_reduces: self.group_for_reduces -= 1 # fully unrolling a GROUP + self.shift_to(axis, amt, insert_before=None) + self.upcast() + elif opt.op is OptOps.UPCAST: # yellow + check(axis < self.first_reduce, "upcast is for non-reduce") + check(not (self.tensor_core and self.global_dims <= axis < self.global_dims+len(self.tensor_core.get_local_axes())), "can't upcast TC locals") + check((self.opts is not None and self.opts.device == "DSP") or amt <= 16, "don't upcast more than 16") + self.shift_to(axis, amt, insert_before=None) + self.upcast() + elif opt.op is OptOps.NOLOCALS: + check(self.opts.has_local and not self.dont_use_locals, "NOLOCALS is meaningless if target does not support local or already not using locals") + check(self.local_dims == 0 and self.group_for_reduces == 0, "can't have no locals with locals") + self.dont_use_locals = True + elif opt.op is OptOps.SWAP: + check(axis < amt < self.global_dims, f"swap is only for globals with axis < amt, getting {amt=}, {axis=}, {self.global_dims=}") + permute = list(range(self.shape_len)) + permute[axis], permute[amt] = permute[amt], permute[axis] + self.reshape_and_permute(None, tuple(permute)) + elif opt.op is OptOps.PADTO: + check(not self.vars, "does not work with symbolic shape") + check(axis < self.first_upcast, "cannot pad upcasted") + # ok to pad SUM if all parent ALU ops have f(0) = 0 + if (r:=self.reduceop) is not None and self.first_reduce <= axis: check(r.arg[0] is Ops.ADD and can_pad(r, {}), f"cannot pad {r}") + padded = False + for i,st in enumerate(self.sts): + if (s:=st.shape[axis]) == 1: continue # reduced + check(s > amt//4, f"pad adds more than quadruple the work {st.shape[axis]=} > {amt//4=}") + if (ru := round_up(cast(int, s), amt) - s): + # pad right seems to be faster + self.sts[i] = st.pad(((0,0),) * axis + ((0,ru),) + ((0,0),) * (len(st.shape)-axis-1)) + padded = True + check(padded, "nothing was padded") + + if append_opt: self.applied_opts.append(opt) + if self.simplify_ones() and self.tensor_core_opts: + self.tensor_core_opts.fix_axes(axis) # fix up axes in TC opts if required after simplify_ones() + + def apply_opts(self, opts:Sequence[Opt]) -> Kernel: + for opt in opts: self.apply_opt(opt) + return self + + # **** kernel outputs **** + + kernel_cnt: Final[defaultdict[str, int]] = defaultdict(int) + @functools.cached_property + def name(self) -> str: + # kernel name (before late upcast) + kernel_type = "r" if self.reduceop is not None else ("C" if all(x.op is Ops.SINK or x.op in GroupOp.Buffer for x in self.ast.toposort()) else "E") + suffix = colored('_', 'BLACK').join([colored(x.render() if isinstance(x, UOp) else str(x), c) for x,c in zip(self.full_shape, self.colors())]) + name = kernel_type + (f"{len(self.ast.src)}" if len(self.ast.src) > 1 else "") + "_" + suffix + + # name the function something unique + Kernel.kernel_cnt[(function_name := to_function_name(name))] += 1 + num = f"n{Kernel.kernel_cnt[function_name]-1}" if Kernel.kernel_cnt[function_name] > 1 else "" + return name + colored(num, 'BLACK') + + def get_optimized_ast(self, name_override:Optional[str]=None) -> UOp: @functools.cache def fixup_ast(op:UOp) -> UOp: ret = op.replace(src=tuple(fixup_ast(x) for x in op.src)) # noqa: F821 if op.op in GroupOp.Buffer and op in self.bufs: st = self.sts[self.bufs.index(op)] - # replace the VIEW source + # NOTE: if CONST got masked after applying opts, we create a new VALID + if op.op is Ops.CONST and any(v.mask is not None for v in st.views): return op.view(st).valid() + # otherwise we just replace the VIEW source return ret.replace(src=(ret.src[0].replace(arg=st),)+ret.src[1:]) if op.op is Ops.SINK: - # NOTE: should group_for_reduces be added to the local_dims? - # TODO: arg.name should be able to be None - kernel_name = ret.arg.name if ret.arg is not None and ret.arg.name != "test" else self.name if name_override is None else name_override - return ret.replace(arg=KernelInfo(kernel_name, tuple(self.axis_types), self.dont_use_locals, tuple(self.applied_opts))) + return ret.replace(arg = KernelInfo(ret.arg.name if ret.arg is not None else self.name if name_override is None else name_override, + self.local_dims, self.upcasted, self.dont_use_locals, tuple(self.applied_opts))) if op.op is Ops.REDUCE_AXIS: reduce_idx = len(self.bufs) + self.reduceops.index(op) * 2 - changed = tuple(i for i in range(self.shape_len) if resolve(self.sts[reduce_idx].shape[i] != self.sts[reduce_idx + 1].shape[i])) - axes = tuple(i for i in self.axes_of(AxisType.REDUCE, AxisType.GROUP_REDUCE, AxisType.UNROLL) if i in changed) - if (tc := self.tensor_core) and self.use_tensor_cores == 1: - # get reduce/upcast axes for the tensor cores - tc_reduce_axes = self.shape_str_to_axis([f"r{i}" for i in range(len(tc.get_reduce_axes()))]) - base_upcast_axes = tuple([(s,2) for s in self.shape_str_to_axis(tc.base_upcast_axes())]) - tc_upcast_axes = tuple([base_upcast_axes[:int(math.log2(tc.elements_per_thread[i]))] for i in range(3)]) - # permute the srcs + def reduced_axes(start, stop): + return tuple(i for i in range(start, stop) if resolve(self.sts[reduce_idx].shape[i] != self.sts[reduce_idx + 1].shape[i])) + axes = reduced_axes(self.first_reduce + self.group_for_reduces, self.shape_len) + grouped_axes = reduced_axes(self.first_reduce, self.first_reduce + self.group_for_reduces) + + if (tc := self.tensor_core) and (self.use_tensor_cores == 1 or self.use_tensor_cores == 3): + wd, tcd = self.global_dims, self.first_upcast + def get_upcast_axes(buf): # upcast along non-zero dimensions of (tc_reduce + tc_upcast) + upcast_axes = int(math.log2(tc.elements_per_thread[buf])) + return tuple((tcd + len(tc.get_reduce_axes()) + len(tc.get_upcast_axes()) - (i+1), 2) for i in range(upcast_axes)) + def get_tc_swizzle_st(shape, local_perm, upcast_perm): + offset = (tcd - (wd + len(local_perm))) + permaxis = list(range(wd)) \ + + [wd + x + (offset if x >= len(local_perm) else 0) for x in local_perm] + list(range(wd + len(local_perm), tcd)) \ + + [wd + x + (offset if x >= len(local_perm) else 0) for x in upcast_perm] + list(range(tcd + len(upcast_perm), len(shape))) + return ShapeTracker.from_shape(shape).permute(tuple(permaxis)) + srcs = list((ret.src[0] if ret.src[0].op is not Ops.CAST else ret.src[0].src[0]).src) - for i, (src, permaxis) in enumerate(zip(srcs, tc.permutes_for_shape_str(self.shape_str()))): + for i, (src, swizzle) in enumerate(zip(srcs, tc.swizzle)): src_st = (src if src.op is Ops.LOAD else src.src[0]).st_arg - srcs[i] = src.view(ShapeTracker.from_shape(src_st.shape).permute(permaxis)) + if swizzle: srcs[i] = src.view(get_tc_swizzle_st(src_st.shape, *swizzle)) - # construct the op - wmma_arg = (str(tc), tc.dims, tc.dtype_in, tc.dtype_out, self.opts.device, tc.threads, tc_upcast_axes, tc_reduce_axes) - wmma = UOp(Ops.WMMA, dtype=tc.dtype_out.vec(tc.elements_per_thread[2]), src=( - UOp(Ops.CONTRACT, dtype=srcs[0].dtype.vec(tc.elements_per_thread[0]), src=(srcs[0],), arg=tc_upcast_axes[0]), - UOp(Ops.CONTRACT, dtype=srcs[1].dtype.vec(tc.elements_per_thread[1]), src=(srcs[1],), arg=tc_upcast_axes[1]), - UOp.const(tc.dtype_out.vec(tc.elements_per_thread[2]), 0.0)), arg=wmma_arg) - tc_uop = UOp(Ops.UNROLL, tc.dtype_out, (wmma,), arg=tc_upcast_axes[2]) + if self.use_tensor_cores == 3: # for TC=3, emulate the warp addressing with locals + local_shape = tuple(1 if st == 0 or i < wd or (i >= self.first_reduce and i < tcd) else src_st.shape[i] \ + for i,st in enumerate(src_st.real_strides())) + st = store_st = ShapeTracker.from_shape(local_shape) + local_buffer = UOp(Ops.DEFINE_LOCAL, tc.dtype_in.ptr(size=st.real_size(), local=True), (), f"temp{i}") + if swizzle: store_st = get_tc_swizzle_st(store_st.shape, *swizzle) + local_store = UOp.store(local_buffer.view(store_st), srcs[i]) + srcs[i] = UOp(Ops.LOAD, tc.dtype_in, (local_buffer.view(st), local_store)) + + tc_reduce_axes = tuple(tcd + ax for ax, _ in tc.get_reduce_axes()) + if self.use_tensor_cores == 1: # real WMMA, use CONTRACT/UNROLL to get the vectorization right + tc_upcast_axes = (get_upcast_axes(0), get_upcast_axes(1), get_upcast_axes(2)) + wmma_arg = (str(tc), tc.dims, tc.dtype_in, tc.dtype_out, self.opts.device, tc.threads, tc_upcast_axes, tc_reduce_axes) + wmma = UOp(Ops.WMMA, dtype=tc.dtype_out.vec(tc.elements_per_thread[2]), src=( + UOp(Ops.CONTRACT, dtype=srcs[0].dtype.vec(tc.elements_per_thread[0]), src=(srcs[0],), arg=tc_upcast_axes[0]), + UOp(Ops.CONTRACT, dtype=srcs[1].dtype.vec(tc.elements_per_thread[1]), src=(srcs[1],), arg=tc_upcast_axes[1]), + UOp.const(tc.dtype_out.vec(tc.elements_per_thread[2]), 0.0)), arg=wmma_arg) + tc_uop = UOp(Ops.UNROLL, tc.dtype_out, (wmma,), arg=tc_upcast_axes[2]) + + else: # for TC=3 MUL/SUM instead of WMMA + tc_uop = UOp(Ops.REDUCE_AXIS, tc.dtype_out, ((srcs[0] * srcs[1]).cast(tc.dtype_out),), (Ops.ADD, tc_reduce_axes)) - # preserve any other reduce return ret.replace(src=(tc_uop,), arg=(Ops.ADD, new_axes)) if (new_axes := tuple(i for i in axes if i not in tc_reduce_axes)) else tc_uop ret = ret.replace(arg = (op.arg[0], axes)) + if self.group_for_reduces and grouped_axes: + local_shape = (1,) * self.global_dims + self.full_shape[self.global_dims:self.global_dims+self.local_dims] + \ + tuple([self.full_shape[i] if self.sts[reduce_idx].shape[i] != self.sts[reduce_idx+1].shape[i] else 1 \ + for i in range(self.first_reduce, self.first_reduce+self.group_for_reduces)]) + \ + (1,) * (self.shape_len - self.upcasted - self.group_for_reduces - self.first_reduce) + tuple([x[0] for x in self.upcasted_axis(0)]) + st = ShapeTracker.from_shape(local_shape) + local_size = st.real_size() + local_buffer = UOp(Ops.DEFINE_LOCAL, op.dtype.ptr(local_size, local=True), (), f"temp{self.reduceops.index(op)}") + local_load = UOp(Ops.LOAD, op.dtype, (local_buffer.view(st), UOp.store(local_buffer.view(st), ret))) + grouped_reduce = UOp(Ops.REDUCE_AXIS, op.dtype, (local_load,), arg=(op.arg[0], grouped_axes)) + if op is self.reduceops[-1]: return grouped_reduce + st = ShapeTracker.from_shape(tuple([1 if i in grouped_axes else a for i,a in enumerate(local_shape)])) + return UOp(Ops.LOAD, op.dtype, (local_buffer.view(st), UOp.store(local_buffer.view(st), grouped_reduce))) + return ret - self.finalized = True fixed_ast = fixup_ast(self.ast) del fixup_ast - return graph_rewrite(fixed_ast, view_left+view_left_through_load, name="fixup optimized AST") + return graph_rewrite(fixed_ast, view_left, name="fixup optimized AST") + + # TODO: update the tests and delete these methods + + def linearize(self): + self.to_program() + return self + def to_program(self, name_override:Optional[str]=None) -> ProgramSpec: + from tinygrad.engine.realize import get_program + ret = get_program(self.get_optimized_ast(name_override), self.opts) + self.uops = ret.uops + return ret diff --git a/tinygrad_repo/tinygrad/codegen/opt/search.py b/tinygrad_repo/tinygrad/opt/search.py similarity index 82% rename from tinygrad_repo/tinygrad/codegen/opt/search.py rename to tinygrad_repo/tinygrad/opt/search.py index 0ae91a43c..27c9e5e1e 100644 --- a/tinygrad_repo/tinygrad/codegen/opt/search.py +++ b/tinygrad_repo/tinygrad/opt/search.py @@ -1,18 +1,18 @@ -from typing import cast -import functools, math, time, multiprocessing, traceback, signal, atexit +from typing import cast, Optional, Callable +import itertools, functools, random, math, time, multiprocessing, traceback, signal, atexit from collections import defaultdict from dataclasses import replace -from tinygrad.uop.ops import UOp, Ops, Variable, sym_infer, AxisType +from tinygrad.uop.ops import UOp, Ops, Variable, sym_infer from tinygrad.device import Device, Buffer, Compiler from tinygrad.helpers import prod, flatten, DEBUG, CACHELEVEL, diskcache_get, diskcache_put, getenv, Context, colored, time_to_str from tinygrad.helpers import IGNORE_BEAM_CACHE, TC_SEARCH_OVER_SHAPE from tinygrad.dtype import ImageDType, PtrDType -from tinygrad.codegen.opt.kernel import Kernel, Opt, OptOps, KernelOptError +from tinygrad.opt.kernel import Kernel, Opt, OptOps, KernelOptError from tinygrad.tensor import Tensor -from tinygrad.engine.realize import CompiledRunner, get_program +from tinygrad.engine.realize import CompiledRunner from tinygrad.renderer import ProgramSpec -actions = [Opt(op=OptOps.UPCAST, axis=axis, arg=amt) for amt in [0,2,3,4,5,7] for axis in range(8)] +actions = [Opt(op=OptOps.UPCAST, axis=axis, arg=amt) for amt in [0,2,3,4,5,7] for axis in range(6)] actions += [Opt(op=OptOps.UNROLL, axis=axis, arg=amt) for amt in [0,4,7] for axis in range(5)] actions += [Opt(op=OptOps.LOCAL, axis=axis, arg=amt) for amt in [2,3,4,8,13,16,29] for axis in range(6)] actions += [Opt(op=OptOps.GROUPTOP, axis=axis, arg=amt) for amt in [13,16,28,29,32,49,64,256] for axis in range(3)] @@ -35,8 +35,8 @@ def get_test_global_size(global_size, max_global_size, var_vals): break return test_global_size, input_size / prod(test_global_size) -def _time_program(p:ProgramSpec, lib:bytes, var_vals:dict[Variable, int], rawbufs:list[Buffer], early_stop:float|None=None, - allow_test_size:int=True, max_global_size:int|None=65536, clear_l2=False, cnt=3, name="test") -> list[float]: +def _time_program(p:ProgramSpec, lib:bytes, var_vals:dict[Variable, int], rawbufs:list[Buffer], early_stop:Optional[float]=None, + allow_test_size:int=True, max_global_size:Optional[int]=65536, clear_l2=False, cnt=3, name="test") -> list[float]: factor = 1 if allow_test_size and p.global_size is not None and max_global_size is not None: global_size, factor = get_test_global_size(p.global_size, max_global_size, var_vals) @@ -57,14 +57,14 @@ def _time_program(p:ProgramSpec, lib:bytes, var_vals:dict[Variable, int], rawbuf class TimeoutException(Exception): pass def timeout_handler(signum, frame): raise TimeoutException() -def _try_compile_linearized_w_idx(x:tuple[int,Kernel], compiler:Compiler) -> tuple[int, tuple[ProgramSpec, bytes, float]|None]: +def _try_compile_linearized_w_idx(x:tuple[int,Kernel], compiler:Compiler) -> tuple[int, Optional[tuple[ProgramSpec, bytes, float]]]: if hasattr(signal, "alarm"): signal.signal(getattr(signal, 'SIGALRM'), timeout_handler) # set timeout signal.alarm(getenv("BEAM_TIMEOUT_SEC", 10)) ret = None try: - p = get_program(x[1].copy().get_optimized_ast(name_override="test"), x[1].opts) + p = x[1].to_program(name_override="test") assert p.uops is not None, "uop list wasn't generated?" if len(p.uops) >= (uops_max:=getenv("BEAM_UOPS_MAX", 3000)) > 0: if getenv("BEAM_LOG_SURPASS_MAX"): print(f"too many uops. {len(p.uops)=}, {uops_max=}") @@ -83,7 +83,7 @@ def _try_compile_linearized_w_idx(x:tuple[int,Kernel], compiler:Compiler) -> tup # workers should not open devices and should ignore ctrl c and should not launch VIZ def _init_worker(): - Context(ALLOW_DEVICE_USAGE=0, VIZ=0, TRACK_MATCH_STATS=0).__enter__() + Context(ALLOW_DEVICE_USAGE=0, VIZ=0).__enter__() signal.signal(signal.SIGINT, signal.SIG_IGN) def _ensure_buffer_alloc(bufs:list[Buffer]) -> list[Buffer]: return [buf.ensure_allocated() if buf is not None else buf for buf in bufs] @@ -97,7 +97,7 @@ def bufs_from_lin(lin:Kernel, allocate:bool=True) -> list[Buffer]: if x.src[0].base.op is Ops.DEFINE_GLOBAL: bufsts[x.src[0].base.arg].append(x) # TODO: Nones are staying in here if buffers are optimized out! # TODO: add a test for this - rawbufs: list[Buffer|None] = [None]*(max(bufsts)+1) + rawbufs: list[Optional[Buffer]] = [None]*(max(bufsts)+1) for k,lx in bufsts.items(): buf_size = prod(dtype.shape) if isinstance(dtype:=lx[0].src[0].dtype, ImageDType) else max(y.st_arg.real_size() for y in lx) assert isinstance(dtype, (PtrDType, ImageDType)) @@ -108,9 +108,9 @@ def bufs_from_lin(lin:Kernel, allocate:bool=True) -> list[Buffer]: return cast(list[Buffer], rawbufs) # get dictionary of all possible actions -def get_kernel_actions(lin:Kernel, include_0=True, candidates:list[Opt]|None=None) -> dict[int, Kernel]: +def get_kernel_actions(lin:Kernel, include_0=True) -> dict[int, Kernel]: acted_lins, max_up, max_lcl = {0:lin} if include_0 else {}, getenv("BEAM_UPCAST_MAX", 256), getenv("BEAM_LOCAL_MAX", 1024) - kernel_actions = (actions if candidates is None else candidates).copy() + kernel_actions = actions.copy() if TC_SEARCH_OVER_SHAPE and len(lin.applied_opts) == 0: # tensor core opts must be first for i, action in enumerate(kernel_actions): @@ -121,16 +121,14 @@ def get_kernel_actions(lin:Kernel, include_0=True, candidates:list[Opt]|None=Non for i,a in enumerate(kernel_actions): if a.axis is not None and a.op is not OptOps.TC: - try: ax = lin.real_axis(a.op, a.axis) - except KernelOptError: continue - if (ax >= lin.shape_len) or (lin.full_shape[ax] == a.arg and Opt(a.op, a.axis, 0) in kernel_actions): continue + if ((ax:=lin.real_axis(a)) >= lin.shape_len) or (lin.full_shape[ax] == a.arg and Opt(a.op, ax, 0) in kernel_actions): continue lin2 = lin.copy() try: lin2.apply_opt(a) up, lcl, tc_up = 1, 1, prod(tc.dims)//tc.threads if (tc:=lin2.tensor_core) else 1 - for s,c in zip(lin2.full_shape, lin2.axis_types): - if c in (AxisType.UPCAST, AxisType.UNROLL): up *= s - elif c in (AxisType.LOCAL, AxisType.GROUP_REDUCE): lcl *= s + for s,c in zip(lin2.full_shape, lin2.colors()): + if c in {"magenta", "yellow"}: up *= s + elif c in {"cyan", "green", "white"}: lcl *= s if up//tc_up > max_up or lcl > max_lcl: if getenv("BEAM_LOG_SURPASS_MAX"): print(f"too many upcast/local. {up//tc_up=}, {max_up=}, {lcl=}, {max_lcl=}") continue @@ -180,10 +178,7 @@ def beam_search(lin:Kernel, rawbufs:list[Buffer], amt:int, allow_test_size=True, seen_libs.add(lib) try: tms = _time_program(p, lib, var_vals, rawbufs, early_stop=beam[0][1]*3 if len(beam) else 1.0, allow_test_size=allow_test_size, clear_l2=hasattr(dev, 'invalidate_caches')) - except Exception as e: - if BEAM_DEBUG: print(f"BEAM failed for opts: {acted_lins[i].applied_opts}\n{e}") - if isinstance(e, RuntimeError): continue - raise + except RuntimeError: continue # for runtime issues timed_lins.append((acted_lins[i], min(tms))) if BEAM_DEBUG > 1: print(f"{time.perf_counter() - st:7.2f}s: {i:5d} {len(cast(list, p.uops)):5d} uops {time_to_str(compile_et, w=12)} compile/{time_to_str(timed_lins[-1][1], w=12)} run {len(timed_lins):4d}/{len(acted_lins):4d} {timed_lins[-1][0].colored_shape()}") # noqa: E501 elif DEBUG >= 2: print(f"\r{time.perf_counter() - st:7.2f}s: {time_to_str(timed_lins[-1][1], w=12)} {len(timed_lins):4d}/{len(acted_lins):4d} {timed_lins[-1][0].colored_shape()}\033[K", end="") # noqa: E501 @@ -201,3 +196,15 @@ def beam_search(lin:Kernel, rawbufs:list[Buffer], amt:int, allow_test_size=True, if CACHELEVEL >= 1: diskcache_put("beam_search", key, beam[0][0].applied_opts) if BEAM_DEBUG: print(f"BEAM_SEARCH: final tm={time_to_str(beam[0][1], w=0)}, applied_opts={beam[0][0].applied_opts}") return beam[0][0] + +def optimize_local_size(_prg:Callable, global_size:list[int], rawbufs:list[Buffer]) -> list[int]: + test_rawbuffers = [Buffer(rawbufs[0].device, rawbufs[0].size, rawbufs[0].dtype).allocate(), *rawbufs[1:]] if rawbufs[0] in rawbufs[1:] else rawbufs + MAX_WORKGROUP = 1024 + local_dims = [[x for x in set([sz, 1, 2, 4, 8, 16, 32, 64, 128, 256, MAX_WORKGROUP]) if x<=sz] for sz in global_size] + local_sizes = [list(x) for x in itertools.product(*local_dims) if prod(x) <= MAX_WORKGROUP] * 2 # try each valid size twice + def try_exec(local_size): + try: return _prg(*[x._buf for x in test_rawbuffers], global_size=[g//l if g%l == 0 else g/l for g,l in zip(global_size, local_size)], local_size=local_size, wait=True) # noqa: E501 + except Exception: return float('inf') + ret = min([(try_exec(local_size), local_size) for local_size in random.sample(local_sizes, len(local_sizes))]) + assert not math.isinf(ret[0]), "all optimize_local_size exec failed" + return ret[1] diff --git a/tinygrad_repo/tinygrad/renderer/__init__.py b/tinygrad_repo/tinygrad/renderer/__init__.py index ed53f0395..d47dc47e0 100644 --- a/tinygrad_repo/tinygrad/renderer/__init__.py +++ b/tinygrad_repo/tinygrad/renderer/__init__.py @@ -1,13 +1,46 @@ from __future__ import annotations -from typing import Callable, cast, TYPE_CHECKING -import functools -from dataclasses import dataclass, field +from typing import Optional, Callable, cast +import functools, math, itertools +from enum import Enum, auto +from dataclasses import dataclass, field, replace from tinygrad.helpers import to_function_name, dedup, prod from tinygrad.uop.ops import Ops, UOp, sym_infer, sint, Variable, ssimplify, GroupOp, PatternMatcher -from tinygrad.dtype import AddrSpace, PtrDType -if TYPE_CHECKING: - from tinygrad.codegen.opt.tc import TensorCore - from tinygrad.codegen.opt.kernel import Opt +from tinygrad.dtype import DType + +class OptOps(Enum): + TC = auto(); UPCAST = auto(); UNROLL = auto(); LOCAL = auto() # noqa: E702 + GROUP = auto(); GROUPTOP = auto(); NOLOCALS = auto(); PADTO = auto(); SWAP = auto() # noqa: E702 + def __lt__(self, x:OptOps): return self.value < x.value + +@dataclass(frozen=True, order=True) +class Opt: + op: OptOps + axis: Optional[int] = None + arg: Optional[int | tuple] = None + def __repr__(self): return f"Opt(op={self.op}, axis={self.axis}, arg={self.arg})" + +@dataclass(frozen=True) +class TensorCore: # D = A * B + C, A is (M x K), B is (K x N), C and D are (M x N) + dims: tuple[int,int,int] # N, M, K + threads: int # number of threads that construct the warp + elements_per_thread: tuple[int, int, int] # elements per-thread to load/store from A/B/C + dtype_in: DType # dtype for A and B + dtype_out: DType # dtype for C and D + opts: tuple[str, ...] # ordered tuple of "ux" or "lx" specifying kernel opts to perform. "ux" upcasts dim x and "lx" localizes dim x + swizzle: tuple[Optional[tuple[tuple[int, ...], tuple[int, ...]]], Optional[tuple[tuple[int, ...], tuple[int, ...]]]] = (None, None) + def get_reduce_axes(self): return [(i, 2) for i in range(int(math.log2(self.dims[2])))] + def get_upcast_axes(self): return [opt for opt in self.opts if opt[0] == "u"] + def get_local_axes(self): return [opt for opt in self.opts if opt[0] == "l"] + def __str__(self): return "_".join(["WMMA"] + list(map(str, self.dims)) + [self.dtype_in.name, self.dtype_out.name]) + def __post_init__(self): + local_axes, upcast_axes, reduce_axes = len(self.get_local_axes()), len(self.get_upcast_axes()), len(self.get_reduce_axes()) + assert self.dims[0] * self.dims[1] == 2**(local_axes + upcast_axes), ( + f"N({self.dims[0]}) x M({self.dims[1]}) != local({2**local_axes}) x upcast({2**upcast_axes}) with opts({self.opts})") + assert 2**local_axes == self.threads, f"{self.threads} threads construct the warp but found {2**local_axes} in {self.opts}" + assert 2**upcast_axes == self.elements_per_thread[2], ( + f"{self.elements_per_thread[2]} elements from C are processed per thread but found {2**upcast_axes} in {self.opts}") + assert all(len(perm[0]) == local_axes and len(perm[1]) == reduce_axes + upcast_axes for perm in self.swizzle if perm), ( + f"swizzle perm should be of len (({local_axes})({reduce_axes + upcast_axes}))") @dataclass(frozen=True) class Estimates: @@ -23,23 +56,17 @@ class Estimates: def from_uops(uops:list[UOp], ignore_indexing=False) -> Estimates: flops: sint = 0 lds: sint = 0 - mem: dict[tuple[UOp, Ops], sint] = {} mults: sint = 1 mult_stack: list[sint] = [] dont_count: set[UOp] = set() if ignore_indexing: for u in uops: - if u.op in {Ops.LOAD, Ops.STORE} and (not isinstance(u.src[0].dtype, PtrDType) or u.src[0].dtype.addrspace != AddrSpace.REG): + if u.op in {Ops.LOAD, Ops.STORE}: dont_count = dont_count.union(u.src[0].toposort()) if len(u.src) > 2: dont_count = dont_count.union(u.src[2].toposort()) elif u.op is Ops.IF: dont_count = dont_count.union(u.src[0].toposort()) for u in uops: - if u.op in {Ops.LOAD, Ops.STORE}: - buf = u - while len(buf.src): buf = buf.src[0] - if buf.op is Ops.DEFINE_GLOBAL: # assume all DEFINE_GLOBAL memory is accessed - mem[(buf, u.op)] = cast(PtrDType, buf.dtype).size * buf.dtype.itemsize if u.op is Ops.RANGE: mult_stack.append(mults) mults *= cast(sint, u.src[0].ssimplify()) @@ -47,13 +74,11 @@ class Estimates: mults = mults.substitute({x:x.const_like(0) for x in mults.toposort() if x.op is Ops.SPECIAL}) if isinstance(mults, UOp) else mults elif u.op is Ops.ENDRANGE: mults = mult_stack.pop(-1) elif u.op is Ops.SPECIAL: mults *= u.arg[1] # NOTE: we don't push to the mult_stack here, you can't end these - elif u.op is Ops.LOAD and (not isinstance(u.src[0].dtype, PtrDType) or u.src[0].dtype.addrspace != AddrSpace.REG): - lds += u.dtype.itemsize * mults - elif u.op is Ops.STORE and (not isinstance(u.src[0].dtype, PtrDType) or u.src[0].dtype.addrspace != AddrSpace.REG): - lds += u.src[1].dtype.itemsize * mults + elif u.op is Ops.LOAD: lds += u.dtype.itemsize * mults + elif u.op is Ops.STORE: lds += u.src[1].dtype.itemsize * mults elif u.op in GroupOp.ALU and u not in dont_count: flops += (mults * (2 if u.op is Ops.MULACC else 1)) * u.dtype.count elif u.op is Ops.WMMA and u not in dont_count: flops += 2 * prod(u.arg[1]) // u.arg[5] * mults - return Estimates(flops, lds, sum(mem.values())) + return Estimates(flops, lds, lds) # TODO: properly track memory, lds is always a high estimate @dataclass class ProgramSpec: @@ -61,11 +86,11 @@ class ProgramSpec: src:str device:str ast:UOp # save the base ast (this is method cache key) - uops:list[UOp]|None=None + uops:Optional[list[UOp]]=None # filled in from uops (if we have uops) - global_size:list[int]|None=None - local_size:list[int]|None=None + global_size:Optional[list[int]]=None + local_size:Optional[list[int]]=None vars:list[Variable]=field(default_factory=list) globals:list[int]=field(default_factory=list) outs:list[int]=field(default_factory=list) @@ -90,9 +115,17 @@ class ProgramSpec: self.ins = sorted(dedup(self.ins)) self._ran_post_init = True + @functools.cached_property + def mem_estimate(self) -> sint: + # group non-local bufs by the op type (LOAD or STORE) and the buffer arg. take the max access of that buffer in bytes + # TODO: these max and min don't work on symbolic, and results are very wrong. + return sum(max(x.src[0].dtype.nbytes() for x in group) + for _, group in itertools.groupby([x for x in self.ast.toposort() if x.op in {Ops.LOAD, Ops.STORE} and x.src[0].base.op is Ops.DEFINE_GLOBAL], + key=lambda x: (x.op, x.src[0].base.arg))) + @functools.cached_property def estimates(self) -> Estimates: - return Estimates() if self.uops is None else Estimates.from_uops(self.uops, ignore_indexing=True) + return replace(Estimates() if self.uops is None else Estimates.from_uops(self.uops, ignore_indexing=True), mem=self.mem_estimate) @functools.cached_property def function_name(self) -> str: return to_function_name(self.name) @@ -114,12 +147,12 @@ class Renderer: has_local: bool = True has_shared: bool = True # NOTE: these two should be in (x,y,z) order to match the max_sizes argument in get_grouped_dims - global_max: tuple[int, ...]|None = (0x8FFFFFFF,) * (3) # TODO: Ops.SPECIAL int32 indexes right now - local_max: tuple[int, ...]|None = (0x8FFFFFFF,) * (3) # TODO: Ops.SPECIAL int32 indexes right now + global_max: Optional[tuple[int, ...]] = (0x8FFFFFFF,) * (3) # TODO: Ops.SPECIAL int32 indexes right now + local_max: Optional[tuple[int, ...]] = (0x8FFFFFFF,) * (3) # TODO: Ops.SPECIAL int32 indexes right now shared_max: int = 32768 tensor_cores: list[TensorCore] = [] - pre_matcher: PatternMatcher|None = None - extra_matcher: PatternMatcher|None = None + pre_matcher: Optional[PatternMatcher] = None + extra_matcher: Optional[PatternMatcher] = None code_for_op: dict[Ops, Callable] = {} def __reduce__(self): return self.__class__, () diff --git a/tinygrad_repo/tinygrad/renderer/cstyle.py b/tinygrad_repo/tinygrad/renderer/cstyle.py index 8a238a842..f4a9d0024 100644 --- a/tinygrad_repo/tinygrad/renderer/cstyle.py +++ b/tinygrad_repo/tinygrad/renderer/cstyle.py @@ -1,15 +1,15 @@ from typing import Literal, Callable, cast import os, math, sys from collections import defaultdict, Counter -from tinygrad.codegen.opt import tc -from tinygrad.uop.ops import GroupOp, Ops, UOp, PatternMatcher, UPat, sint_to_uop +from tinygrad.uop.ops import GroupOp, Ops, UOp, PatternMatcher, UPat from tinygrad.helpers import strip_parens, getenv, prod, dedup, AMX -from tinygrad.dtype import ImageDType, dtypes, DType, PtrDType, AddrSpace, truncate -from tinygrad.renderer import Renderer -from tinygrad.codegen.late.devectorizer import no_vectorized_alu +from tinygrad.dtype import ImageDType, dtypes, DType, PtrDType +from tinygrad.renderer import Renderer, TensorCore +from tinygrad.codegen.devectorizer import no_vectorized_alu base_rewrite = PatternMatcher([ - (UPat(Ops.DEFINE_REG, name="x"), lambda ctx,x: f"{ctx.render_dtype(x.dtype.base)} {ctx[x]}[{x.dtype.size}];"), + (UPat(Ops.DEFINE_ACC, name="x"), lambda ctx,x: ctx[x.src[0]]), + (UPat(Ops.ASSIGN, name="x"), lambda ctx,x: f"{ctx[x.src[0]]} = {ctx[x.src[1]]};"), (UPat(Ops.IF, name="x"), lambda ctx,x: f"if ({ctx[x.src[0]]}) {{"), (UPat((Ops.ENDIF, Ops.ENDRANGE)), lambda ctx: "}"), (UPat(Ops.WMMA, name="x"), lambda ctx,x: f"__{x.arg[0]}({ctx[x.src[0]]}, {ctx[x.src[1]]}, {ctx[x.src[2]]})"), @@ -25,16 +25,16 @@ base_rewrite = PatternMatcher([ (UPat(Ops.BITCAST, name="x"), lambda ctx,x: f"(*(({ctx.buffer_prefix}{ctx.render_dtype(x.dtype)}*)&{ctx[x.src[0]]}))"), (UPat(Ops.DEFINE_LOCAL, name="x"), lambda ctx,x: f"{ctx.smem_align}{ctx.smem_prefix}{ctx.render_dtype(x.dtype.base)} {ctx[x]}[{x.dtype.size}];"), (UPat(Ops.BARRIER), lambda ctx: ctx.barrier), - (UPat(Ops.PRECAST, name="x"), lambda ctx,x: ctx[x.src[0]]), - (UPat(Ops.SPECIAL, name="x"), lambda ctx,x: f"{ctx.code_for_workitem[x.arg[0][0]](x.arg[0][-1])}; /* {sint_to_uop(x.arg[1]).render()} */"), + (UPat(Ops.NOOP, name="x"), lambda ctx,x: ctx[x.src[0]]), + (UPat(Ops.SPECIAL, name="x"), lambda ctx,x: f"{ctx.code_for_workitem[x.arg[0][0]](x.arg[0][-1])}; /* {x.arg[1]} */"), # const (UPat(Ops.CONST, arg=math.inf, name="x"), lambda ctx, x: f"({ctx.render_cast(x.dtype, ctx.infinity)})"), (UPat(Ops.CONST, arg=-math.inf, name="x"), lambda ctx, x: f"({ctx.render_cast(x.dtype, f'-{ctx.infinity}')})"), (UPat(Ops.CONST, dtype=dtypes.floats, name="x"), lambda ctx,x: f"({ctx.render_cast(x.dtype, ctx.nan)})" if math.isnan(x.arg) else None), (UPat(Ops.CONST, dtype=dtypes.float, name="x"), lambda ctx,x: f"{x.arg}f"), (UPat(Ops.CONST, dtype=dtypes.int64, name="x"), lambda ctx,x: f"{x.arg}ll"), - (UPat(Ops.CONST, dtype=dtypes.uint64, name="x"), lambda ctx,x: f"{truncate[x.dtype](x.arg)}ull"), - (UPat(Ops.CONST, dtype=dtypes.uint32, name="x"), lambda ctx,x: f"{truncate[x.dtype](x.arg)}u"), + (UPat(Ops.CONST, dtype=dtypes.uint64, name="x"), lambda ctx,x: f"{x.arg}ull"), + (UPat(Ops.CONST, dtype=dtypes.uint32, name="x"), lambda ctx,x: f"{x.arg}u"), (UPat(Ops.CONST, dtype=dtypes.bool, name="x"), lambda ctx,x: "1" if x.arg else "0"), # consts are rendered to larger type and casted (UPat(Ops.CONST, (dtypes.bfloat16, dtypes.half), name="x"), lambda ctx,x: f"({ctx.render_cast(x.dtype, f'{x.arg}f')})"), @@ -47,7 +47,7 @@ base_rewrite = PatternMatcher([ lambda ctx,buf,idx: f"({ctx[buf]}+{strip_parens(ctx[idx]) if idx.arg == Ops.ADD else ctx[idx]})"), (UPat(Ops.LOAD, src=(UPat(Ops.INDEX, src=(UPat(), UPat(), UPat.var("gate"))).or_casted("bidx"), UPat.var("var")), allow_any_len=True), lambda ctx,bidx,var,gate: f"({ctx[gate]}?*{ctx[bidx]}:{ctx[var]})"), - (UPat(Ops.LOAD, src=(UPat.var('bidx'),), allow_any_len=True), lambda ctx,bidx: f"(*{ctx[bidx]})"), + (UPat(Ops.LOAD, src=(UPat.var('bidx'),), allow_any_len=True), lambda ctx,bidx: f"*{ctx[bidx]}"), (UPat(Ops.STORE, src=(UPat.var('bidx'), UPat.var("var")), allow_any_len=True), lambda ctx,bidx,var: f"*{ctx[bidx]} = {ctx[var]};"), # alu/gep # TODO: look for left-associative @@ -60,11 +60,13 @@ base_rewrite = PatternMatcher([ ]) extra_pm = PatternMatcher([ - # insert a PRECAST before BITCAST to force it to be rendered. not needed on all backends? - (UPat(Ops.BITCAST, name="x"), lambda x: UOp(Ops.BITCAST, x.dtype, (UOp(Ops.PRECAST, x.src[0].dtype, x.src),)) - if x.src[0].op not in {Ops.PRECAST, Ops.LOAD, Ops.CUSTOM} else None), + # insert a NOOP before BITCAST to force it to be rendered. not needed on all backends? + (UPat(Ops.BITCAST, name="x"), + lambda x: UOp(Ops.BITCAST, x.dtype, (UOp(Ops.NOOP, x.src[0].dtype, x.src),)) if x.src[0].op not in {Ops.NOOP, Ops.LOAD, Ops.CUSTOM} else None), + # rewrite MAX to CMPLT + WHERE (max function is annoying on many cstyle backends) + (UPat(Ops.MAX, name="m"), lambda m: (m.src[0] < m.src[1]).where(m.src[1], m.src[0])), # devectorize any bools - (UPat((*GroupOp.ALU, Ops.CAST, Ops.BITCAST, Ops.INDEX), dtype=dtypes.bool, name="alu"), no_vectorized_alu), + (UPat((*GroupOp.ALU, Ops.CAST, Ops.BITCAST, Ops.ASSIGN, Ops.INDEX), dtype=dtypes.bool, name="alu"), no_vectorized_alu), # CAST (from bool) can't be vectorized (UPat(Ops.CAST, src=(UPat(dtype=dtypes.bool),), name="alu"), no_vectorized_alu), # WHERE can't be vectorized @@ -73,10 +75,6 @@ extra_pm = PatternMatcher([ def uops_to_dtypes(uops:list[UOp]) -> list[DType]: return dedup(u.dtype for u in uops if not isinstance(u.dtype, (ImageDType, PtrDType))) -# (name, dims, dtype_in, dtype_out, device, threads, upcast_axes, reduce_axes) -def wmma_args(uops:list[UOp]): - return dedup((uop.arg[0], uop.arg[1], uop.src[0].dtype.scalar(), uop.dtype.scalar(), *(uop.arg[4:8])) for uop in uops if uop.op is Ops.WMMA) - class CStyleLanguage(Renderer): kernel_typedef: str = "void" buffer_prefix: str = "" @@ -97,12 +95,11 @@ class CStyleLanguage(Renderer): code_for_op: dict = { Ops.SQRT: lambda x,dtype: f"sqrt({x})", Ops.RECIP: lambda x,dtype: f"(1/{x})", Ops.NEG: lambda x,dtype: f"-{x}", Ops.EXP2: lambda x,dtype: f"exp2({x})", Ops.LOG2: lambda x,dtype: f"log2({x})", Ops.SIN: lambda x,dtype: f"sin({x})", - Ops.TRUNC: lambda x,dtype: f"trunc({x})", Ops.AND: lambda a,b,dtype: f"({a}&{b})", Ops.XOR: lambda a,b,dtype: f"({a}^{b})", Ops.OR: lambda a,b,dtype: f"({a}|{b})", Ops.ADD: lambda a,b,dtype: f"({a}+{b})", Ops.SUB: lambda a,b,dtype: f"({a}-{b})", Ops.MUL: lambda a,b,dtype: f"({a}*{b})", Ops.MOD: lambda a,b,dtype: f"({a}%{b})", Ops.IDIV: lambda a,b,dtype: f"({a}/{b})", Ops.CMPNE: lambda a,b,dtype: f"({a}!={b})", Ops.SHR: lambda a,b,dtype: f"({a}>>{b})", Ops.SHL: lambda a,b,dtype: f"({a}<<{b})", Ops.CMPLT: lambda a,b,dtype: f"({a}<{b})", - Ops.WHERE: lambda a,b,c,dtype: f"({a}?{b}:{c})", Ops.CMPEQ: lambda a,b,dtype: f"({a}=={b})"} + Ops.WHERE: lambda a,b,c,dtype: f"({a}?{b}:{c})" } string_rewrite = base_rewrite extra_matcher = extra_pm @@ -121,10 +118,7 @@ class CStyleLanguage(Renderer): def render_dtype(self, dt:DType, mutable=True) -> str: if isinstance(dt, ImageDType): return f"{'write_only' if mutable else 'read_only'} image2d_t" if isinstance(dt, PtrDType): - prefix = "" - if dt.addrspace == AddrSpace.LOCAL and self.smem_prefix_for_cast: prefix = self.smem_prefix - if dt.addrspace == AddrSpace.GLOBAL: prefix = self.buffer_prefix - return prefix + self.render_dtype(dt.base) + "*" + return (self.smem_prefix if dt.local and self.smem_prefix_for_cast else self.buffer_prefix) + self.render_dtype(dt.base) + "*" if dt.count > 1: return self.type_map.get(scalar:=dt.scalar(), scalar.name).replace(" ", "_") + str(dt.count) return self.type_map.get(scalar:=dt.scalar(), scalar.name) @@ -140,12 +134,11 @@ class CStyleLanguage(Renderer): c: defaultdict[str, int] = defaultdict(int) name = "test" for u in uops: - if u.op is Ops.NOOP: continue if u.op is Ops.SINK: if u.arg is not None: name = u.arg.function_name continue if u.op in (Ops.DEFINE_GLOBAL, Ops.DEFINE_VAR): - r[u] = (f"data{u.arg}_{sz}" if (sz:=cast(PtrDType, u.dtype).size) > 0 else f"data{u.arg}") if u.op is Ops.DEFINE_GLOBAL else u.arg[0] + r[u] = f"data{u.arg}" if u.op is Ops.DEFINE_GLOBAL else u.arg[0] bufs[u] = (r[u], (u.dtype, False)) continue @@ -157,11 +150,11 @@ class CStyleLanguage(Renderer): # naming prefix = None if u.op is Ops.SPECIAL: r[u] = u.arg[0] - elif u.op is Ops.RANGE: r[u] = "ridx"+'_'.join([str(x) if x >= 0 else "m"+str(-x) for x in u.arg[0:-1]]) + elif u.op is Ops.RANGE: r[u] = f"ridx{u.arg}" else: prefix = {Ops.WMMA: "wmma", Ops.DEFINE_LOCAL: "temp", Ops.CONST: "const", - Ops.CAST: "cast", Ops.BITCAST: "cast", Ops.GEP: "gep", Ops.VECTORIZE: "cast", Ops.PRECAST: "precast", - Ops.INDEX: "bidx", Ops.DEFINE_REG: "acc", Ops.LOAD: "val"}.get(u.op, "alu") + Ops.CAST: "cast", Ops.BITCAST: "cast", Ops.GEP: "gep", Ops.VECTORIZE: "cast", Ops.NOOP: "precast", + Ops.INDEX: "bidx", Ops.DEFINE_ACC: "acc", Ops.LOAD: "val"}.get(u.op, "alu") r[u] = f"{prefix}{c[prefix]}" l = cast(str, self.string_rewrite.rewrite(u, ctx=self)) @@ -169,13 +162,13 @@ class CStyleLanguage(Renderer): if u.op in {Ops.ENDIF, Ops.ENDRANGE}: depth -= 1 if (u.op is not Ops.CAST or u.dtype.vcount == 1) and (u.op in {Ops.CONST, Ops.GEP, Ops.INDEX, Ops.CUSTOMI} or \ - (u.op is Ops.LOAD and cast(PtrDType, u.src[0].dtype).addrspace == AddrSpace.REG) or \ - (u.op is Ops.CAST and isinstance(u.dtype, PtrDType)) or \ (u.op in {Ops.VECTORIZE, *(GroupOp.ALU-{Ops.WHERE}), Ops.CAST, Ops.BITCAST} and child_count[u] == 1 and not getenv("EXPAND_SSA"))): r[u] = l else: - if u.op in {Ops.RANGE, Ops.DEFINE_LOCAL, Ops.STORE, Ops.DEFINE_REG} or u.dtype == dtypes.void: pass - else: l = f"{self.render_dtype(u.dtype)} {r[u]} = {l}" + (";" if u.op is not Ops.SPECIAL else "") + if u.op in {Ops.RANGE, Ops.ASSIGN, Ops.DEFINE_LOCAL, Ops.STORE} or u.dtype == dtypes.void: + if u.op is Ops.ASSIGN: r[u] = r[u.src[0]] + else: + l = f"{self.render_dtype(u.dtype)} {r[u]} = {l}" + (";" if u.op is not Ops.SPECIAL else "") kernel.append(" "*depth + l) if prefix: c[prefix] += 1 # if it was used, increment if u.op in {Ops.IF, Ops.RANGE}: depth += 1 @@ -194,18 +187,18 @@ class ClangRenderer(CStyleLanguage): global_max = None infinity = "__builtin_inff()" nan = '__builtin_nanf("")' - if AMX: tensor_cores = tc.amx + amx_tc = [TensorCore(dims=(sz,sz,1), threads=1, elements_per_thread=(sz,sz,sz*sz), dtype_in=dt, dtype_out=dt, swizzle=(None,((),(4,5,6,7,0,1,2,3))), + opts=("u0","u0","u0","u0","u1","u1","u1","u1")) for dt,sz in [(dt, 64 // dt.itemsize) for dt in [dtypes.float]]] + if AMX: tensor_cores = amx_tc # language options buffer_suffix = " restrict" type_map = {dtypes.bool:"_Bool", dtypes.half:"__fp16"} - code_for_op = {**({k:v for k,v in CStyleLanguage.code_for_op.items() if k not in [Ops.EXP2, Ops.SIN, Ops.LOG2, Ops.TRUNC, Ops.RECIP]}), - Ops.SQRT: lambda x,dtype: f"__builtin_sqrt({x})" if dtype == dtypes.float64 else f"__builtin_sqrtf({x})", - Ops.TRUNC: lambda x,dtype: f"__builtin_trunc({x})" if dtype == dtypes.float64 else f"__builtin_truncf({x})", - Ops.FDIV: lambda a,b,dtype: f"({a}/{b})"} + code_for_op = {**({k:v for k,v in CStyleLanguage.code_for_op.items() if k not in [Ops.EXP2, Ops.SIN, Ops.LOG2]}), + Ops.SQRT: lambda x,dtype: f"__builtin_sqrt({x})" if dtype == dtypes.float64 else f"__builtin_sqrtf({x})"} # LLVM legalizes double => half cast on systems that don't support it natively (like x86 cpus without AVX512-FP16) into a compiler-rt libcall. extra_matcher = PatternMatcher([(UPat.var("x", dtypes.float64).cast(dtypes.float16), lambda x: x.cast(dtypes.float32).cast(dtypes.float16)), - (UPat((Ops.SQRT, Ops.TRUNC), name="alu"), no_vectorized_alu)]) + CStyleLanguage.extra_matcher + (UPat(Ops.SQRT, name="alu"), no_vectorized_alu),]) + CStyleLanguage.extra_matcher if sys.platform == 'win32': kernel_typedef = "__attribute__((ms_abi)) void" @@ -217,7 +210,7 @@ class ClangRenderer(CStyleLanguage): def _render_defines(self, uops) -> list[str]: prefix = [self.render_vector_prefix(dt) for dt in uops_to_dtypes(uops) if dt.count > 1] # https://github.com/corsix/amx - for name, (N, M, _), dtype_in, _, _, _, _, _ in wmma_args(uops): + for name, (N, M, _), dtype_in, _, _, _, _, _ in dedup([uop.arg for uop in uops if uop.op is Ops.WMMA]): prefix += [ '#define AMX_SET(imm5) __asm("nop\\nnop\\nnop\\n.word (0x201000+(%0<<5)+%1)" : : "i"(17), "i"(imm5) : "memory")', '#define AMX(op, gpr, btf) __asm(".word (0x201000+(%0 << 5)+0%1-((0%1>>4)*6))" : : "i"(op), "r"((unsigned long long)(gpr)+(btf)) : "memory")', @@ -268,7 +261,8 @@ class OpenCLRenderer(CStyleLanguage): class IntelRenderer(OpenCLRenderer): device, suffix, kernel_typedef = "GPU", "INTEL", "__attribute__((intel_reqd_sub_group_size(8)))\n" + "__kernel void" - tensor_cores = tc.intel + tensor_cores = [TensorCore(dims=(8,8,16), threads=8, elements_per_thread=(16,16,8), dtype_in=dtypes.half, dtype_out=dtypes.float, + opts=("l0","l0","l0","u1","u1","u1"), swizzle=(((4,5,6),(0,1,2,3,7,8,9)), ((0,1,2),(7,8,9,3,4,5,6))))] string_rewrite = PatternMatcher([ (UPat(Ops.CAST, dtype=dtypes.bfloat16, src=(UPat.var('x', dtype=dtypes.float),)), lambda ctx,x: f"intel_convert_bfloat16_as_ushort({ctx[x]})"), @@ -277,16 +271,19 @@ class IntelRenderer(OpenCLRenderer): def render_kernel(self, function_name, kernel, bufs, uops, prefix=None) -> str: prefix = [] - for name, _, dtype_in, dtype_out, _, _, _, _ in wmma_args(uops): - dt_in = ("ushort", "bf16") if dtype_in == dtypes.bfloat16 else (dtype_in.name, "f16") - prefix.append(f"""{dtype_out.name}8 __{name}({dt_in[0]}16 a, {dt_in[0]}16 b, {dtype_out.name}8 c) {{ + for arg in dedup([uop.arg for uop in uops if uop.op is Ops.WMMA]): + dt_in = ("ushort", "bf16") if arg[2] == dtypes.bfloat16 else (arg[2].name, "f16") + prefix.append(f"""{arg[3].name}8 __{arg[0]}({dt_in[0]}16 a, {dt_in[0]}16 b, {arg[3].name}8 c) {{ return intel_sub_group_{dt_in[1]}_{dt_in[1]}_matrix_mad_k16(as_int8(a), as_int8(b), c);\n}}""") return super().render_kernel(function_name, kernel, bufs, uops, prefix or None) class MetalRenderer(CStyleLanguage): device = "METAL" shared_max = 32768 - def __init__(self): self.tensor_cores = tc.metal if hasattr(os, 'uname') and os.uname().machine == "arm64" else [] + tensor_cores = [TensorCore(dims=(8,8,8), threads=32, elements_per_thread=(2,2,2), dtype_in=di, dtype_out=do, opts=("u0","l0","l1","l1","l0","l1"), + swizzle=(((6,1,2,7,4),(8,0,3,5)), ((0,5,6,3,7),(1,2,4,8)))) for di,do in [(dtypes.float,dtypes.float),(dtypes.half,dtypes.float), + (dtypes.half,dtypes.half),(dtypes.bfloat16,dtypes.float),(dtypes.bfloat16,dtypes.bfloat16)]] + def __init__(self): self.tensor_cores = MetalRenderer.tensor_cores if hasattr(os, 'uname') and os.uname().machine == "arm64" else [] # language options kernel_typedef = "kernel void" @@ -315,25 +312,37 @@ class MetalRenderer(CStyleLanguage): ]) + base_rewrite def render_kernel(self, function_name, kernel, bufs, uops, prefix=None): - prefix = ["#include ","using namespace metal;"] - for name, _, dtype_in, dtype_out, _, _, _, _ in wmma_args(uops): prefix.append( - f"""{(dstr_out:=self.render_dtype(dtype_out.vec(2)))} __{name}({(dstr_in:=self.render_dtype(dtype_in.vec(2)))} a, {dstr_in} b, {dstr_out} c){{ - simdgroup_{self.render_dtype(dtype_in)}8x8 mat_a, mat_b; simdgroup_{self.render_dtype(dtype_out)}8x8 mat_c; + prefix, wmma_args = ["#include ","using namespace metal;"], set([uop.arg for uop in uops if uop.op is Ops.WMMA]) + for arg in wmma_args: prefix.append( + f"""{(dtype_out:=self.render_dtype(arg[3].vec(2)))} __{arg[0]}({(dtype_in:=self.render_dtype(arg[2].vec(2)))} a, {dtype_in} b, {dtype_out} c){{ + simdgroup_{self.render_dtype(arg[2])}8x8 mat_a, mat_b; simdgroup_{self.render_dtype(arg[3])}8x8 mat_c; mat_a.thread_elements()[0] = a[0]; mat_b.thread_elements()[0] = b[0]; mat_c.thread_elements()[0] = c[0]; mat_a.thread_elements()[1] = a[1]; mat_b.thread_elements()[1] = b[1]; mat_c.thread_elements()[1] = c[1]; - simdgroup_multiply_accumulate(mat_c, mat_a, mat_b, mat_c);\n return {dstr_out}(mat_c.thread_elements()[0], mat_c.thread_elements()[1]);\n}}""") + simdgroup_multiply_accumulate(mat_c, mat_a, mat_b, mat_c);\n return {dtype_out}(mat_c.thread_elements()[0], mat_c.thread_elements()[1]);\n}}""") return super().render_kernel(function_name, kernel, bufs, uops, prefix) _nms = "xyzwabcdefghijkl" +cuda_tc_opts = ("u0","l0","l0","l1","l1","l1","u1") # shared by all shapes with M=16 N=8 class CUDARenderer(CStyleLanguage): device = "CUDA" global_max = (2147483647, 65535, 65535) local_max = (1024, 1024, 64) shared_max = 49152 + # https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-multiply-accumulate-instructions + tc_81616 = [TensorCore(dims=(8,16,16), threads=32, elements_per_thread=(8,4,4), dtype_in=di, dtype_out=do, opts=cuda_tc_opts, + swizzle=(((6,7,2,3,4),(0,1,9,5,10,8)), ((6,7,9,0,1),(2,3,4,10,5,8)))) for di,do in [(dtypes.half,dtypes.float), (dtypes.bfloat16,dtypes.float), + (dtypes.half,dtypes.half)]] + tc_8168_f16 = [TensorCore(dims=(8,16,8), threads=32, elements_per_thread=(4,2,4), dtype_in=di, dtype_out=do, opts=cuda_tc_opts, + swizzle=(((6,7,2,3,4),(0,1,8,5,9)), ((6,7,8,0,1),(2,3,4,9,5)))) for di,do in [(dtypes.half,dtypes.float), (dtypes.half,dtypes.half)]] + tc_8168_tf32 = [TensorCore(dims=(8,16,8), threads=32, elements_per_thread=(4,2,4), dtype_in=dtypes.float, dtype_out=dtypes.float, opts=cuda_tc_opts, + swizzle=(((5,6,2,3,4),(0,1,8,9,7)), ((5,6,8,0,1),(2,3,4,9,7))))] + tc_sm80 = tc_81616 + tc_8168_f16 + if getenv("ALLOW_TF32", 0): tc_sm80 += tc_8168_tf32 + tc_sm75 = tc_8168_f16 def __init__(self, arch:str): - self.tensor_cores, self.arch = tc.cuda_sm80 if int(arch[3:]) >= 80 else tc.cuda_sm75 if int(arch[3:]) >= 75 else [], arch + self.tensor_cores, self.arch = CUDARenderer.tc_sm80 if int(arch[3:]) >= 80 else CUDARenderer.tc_sm75 if int(arch[3:]) >= 75 else [], arch def __reduce__(self): return self.__class__, (self.arch,) # language options @@ -370,7 +379,7 @@ class CUDARenderer(CStyleLanguage): dt_map_in = { dtypes.float: "tf32", dtypes.half: "f16", dtypes.bfloat16: "bf16" } dt_map_out = { dtypes.float: "f32", dtypes.half: "f16" } - for name, (N, M, K), dtype_in, dtype_out, _, _, upcast_axes, _ in wmma_args(uops): + for name, (N, M, K), dtype_in, dtype_out, _, _, upcast_axes, _ in dedup([uop.arg for uop in uops if uop.op is Ops.WMMA]): upcast_sizes = [prod(size for _, size in upcast) for upcast in upcast_axes] wmma_dtypes = [self.render_dtype(dtype.vec(size)) for dtype, size in zip([dtype_in, dtype_in, dtype_out], upcast_sizes)] n_operands = [size*dtype.itemsize//4 for dtype, size in zip([dtype_in, dtype_in, dtype_out], upcast_sizes)] # 4 => CUDA reg size in bytes @@ -399,14 +408,27 @@ class AMDRenderer(CStyleLanguage): shared_max = 65536 # NOTE: this is only really needed on gfx12, even though gfx11 reports the same limitation global_max = (2147483647, 65535, 65535) + # https://gpuopen.com/learn/wmma_on_rdna3/ + tensor_cores = [TensorCore(dims=(16,16,16), threads=32, elements_per_thread=(16,16,8), dtype_in=di, dtype_out=do, + opts=("l0","l0","l0","l0","l1","u1","u1","u1"), swizzle=(((4,9,10,11,0),(1,2,3,5,6,7,8)), ((0,1,2,3,4),(9,10,11,5,6,7,8)))) + for di,do in [(dtypes.half,dtypes.float),(dtypes.half,dtypes.half),(dtypes.bfloat16,dtypes.float)]] + tensor_cores_rdna4 = [TensorCore(dims=(16,16,16), threads=32, elements_per_thread=(8,8,8), dtype_in=di, dtype_out=do, + opts=("l0","l0","l0","l0","u1","u1","u1","l1"), swizzle=(((9,10,11,4,7),(0,1,2,3,5,6,8)),((0,1,2,3,7),(4,9,10,11,5,6,8)))) + for di,do in [(dtypes.half,dtypes.float),(dtypes.half,dtypes.half),(dtypes.bfloat16,dtypes.float),(dtypes.bfloat16,dtypes.bfloat16)]] + # https://gpuopen.com/learn/amd-lab-notes/amd-lab-notes-matrix-cores-readme + tensor_cores_mfma = [TensorCore(dims=(16,16,16), threads=64, elements_per_thread=(4,4,4), dtype_in=di, dtype_out=do, + opts=("l0","l0","l0","l0","u1","u1","l1","l1"), swizzle=(((10,11,4,5,8,9),(0,1,2,3,6,7)),((0,1,2,3,8,9),(4,5,10,11,6,7)))) + for di,do in [(dtypes.half,dtypes.float),(dtypes.bfloat16,dtypes.float)]] @staticmethod def get_tensor_cores(arch): - return {"gfx942": tc.amd_cdna, "gfx950": tc.amd_cdna, "gfx1200": tc.amd_rdna4, "gfx1201": tc.amd_rdna4}.get(arch.split(":")[0], tc.amd_rdna3) + return {"gfx942": AMDRenderer.tensor_cores_mfma, + "gfx1200": AMDRenderer.tensor_cores_rdna4, + "gfx1201": AMDRenderer.tensor_cores_rdna4}.get(arch.split(":")[0], AMDRenderer.tensor_cores) def __init__(self, arch:str): # gfx942 => MI300, gfx1100 => RX 7900, gfx1201 => RX 9700 self.arch = arch self.tensor_cores = self.get_tensor_cores(arch) - if self.tensor_cores == tc.amd_cdna: + if self.arch.split(":")[0] == "gfx942": self.string_rewrite = PatternMatcher([ (UPat(Ops.WMMA, name="x"), lambda ctx,x: f"__{x.arg[0]}({ctx[x.src[0]]}, {ctx[x.src[1]]}, {ctx[x.src[2]]}, 0, 0, 0)")]) + base_rewrite def __reduce__(self): return self.__class__, (self.arch,) @@ -415,7 +437,7 @@ class AMDRenderer(CStyleLanguage): ockl = [(f"__ockl_get_{name}", "unsigned int", "size_t", "const") for name in ["local_id", "group_id", "local_size"]] ocml = [(f"__ocml_{name}_f{n}", f"{dt}, {dt}" if "fmax" == name else dt, dt, atr) for dt, n in [(dtype.name, dtype.itemsize * 8) for dtype in [dtypes.float, dtypes.double, dtypes.half]] - for name, atr in [("fmax", "const"), ("exp2", "pure"), ("log2", "pure"), ("sqrt", "const"), ("sin", ""), ("trunc", "")]] + for name, atr in [("fmax", "const"), ("exp2", "pure"), ("log2", "pure"), ("sqrt", "const"), ("sin", "")]] kernel_typedef = "\n".join(f'extern "C" __attribute__((device{f", {atr}" if atr else ""})) {dto} {meth}({dti});' for meth,dti,dto,atr in ockl+ocml) # https://clang.llvm.org/docs/AttributeReference.html#amdgpu-flat-work-group-size @@ -424,7 +446,6 @@ class AMDRenderer(CStyleLanguage): code_for_workitem = {"g": lambda x: f"__ockl_get_group_id({x})", "l": lambda x: f"__ockl_get_local_id({x})", "i": lambda x: f"(__ockl_get_group_id({x})*__ockl_get_local_size({x})+__ockl_get_local_id({x}))"} code_for_op = { **CStyleLanguage.code_for_op, - Ops.TRUNC: lambda x,dtype: f"__ocml_trunc_f{ {dtypes.half:16, dtypes.double:64}.get(dtype, 32)}({x})", Ops.SIN: lambda x,dtype: f"__ocml_sin_f{ {dtypes.half:16, dtypes.double:64}.get(dtype, 32)}({x})", Ops.LOG2: lambda x,dtype: f"__ocml_log2_f{ {dtypes.half:16, dtypes.double:64}.get(dtype, 32)}({x})", Ops.EXP2: lambda x,dtype: f"__ocml_exp2_f{ {dtypes.half:16, dtypes.double:64}.get(dtype, 32)}({x})", @@ -466,15 +487,15 @@ class AMDRenderer(CStyleLanguage): if any(dt.scalar() == dtypes.bfloat16 for dt in used_dtypes): prefix.append("typedef unsigned short hip_bfloat16;") prefix += [self.render_vector_prefix(dt) for dt in used_dtypes if dt.count > 1] - for name, _, dtype_in, dtype_out, _, _, _, _ in wmma_args(uops): # TODO: handle TCs f32_bf16 and bf16_bf16 w/ wrapper - if self.tensor_cores == tc.amd_cdna: - prefix.append(f"#define __{name} __builtin_amdgcn_mfma_f32_16x16x16{'f16' if dtype_in == dtypes.half else 'bf16_1k'}") + for arg in dedup([uop.arg for uop in uops if uop.op is Ops.WMMA]): # TODO: handle TCs f32_bf16 and bf16_bf16 w/ wrapper + if self.arch.split(":")[0] == "gfx942": + prefix.append(f"#define __{arg[0]} __builtin_amdgcn_mfma_f32_16x16x16{'f16' if arg[2] == dtypes.half else 'bf16_1k'}") # #define __WMMA_16_16_16_half_half __builtin_amdgcn_wmma_f16_16x16x16_f16_w32_gfx12 - elif self.tensor_cores == tc.amd_rdna4: - prefix.append(f"#define __{name} __builtin_amdgcn_wmma_{type_map[dtype_out]}_16x16x16_{type_map[dtype_in]}_w32_gfx12") - elif dtype_out == dtypes.float: - prefix.append(f"#define __{name} __builtin_amdgcn_wmma_f32_16x16x16_{'f16' if dtype_in == dtypes.half else 'bf16'}_w32") - else: prefix.append(f"static inline __attribute__((device)) half8 __{name}"+"""(half16 a, half16 b, half8 c) { + elif self.arch.split(":")[0] == "gfx1201": + prefix.append(f"#define __{arg[0]} __builtin_amdgcn_wmma_{type_map[arg[3]]}_16x16x16_{type_map[arg[2]]}_w32_gfx12") + elif arg[3] == dtypes.float: + prefix.append(f"#define __{arg[0]} __builtin_amdgcn_wmma_f32_16x16x16_{'f16' if arg[2] == dtypes.half else 'bf16'}_w32") + else: prefix.append(f"static inline __attribute__((device)) half8 __{arg[0]}"+"""(half16 a, half16 b, half8 c) { half16 c_frag = {}; half8 d; for (int n = 0; n < 8; n++) { c_frag[n*2] = c[n]; } c_frag = __builtin_amdgcn_wmma_f16_16x16x16_f16_w32(a, b, c_frag, false); for (int n = 0; n < 8; n++) { d[n] = c_frag[n*2]; } return d;\n}""") diff --git a/tinygrad_repo/tinygrad/renderer/llvmir.py b/tinygrad_repo/tinygrad/renderer/llvmir.py index 47ed182bf..d882ed7ae 100644 --- a/tinygrad_repo/tinygrad/renderer/llvmir.py +++ b/tinygrad_repo/tinygrad/renderer/llvmir.py @@ -1,8 +1,7 @@ from typing import cast import math, struct, sys -from tinygrad.codegen.opt import tc from tinygrad.renderer import Renderer -from tinygrad.renderer.cstyle import AMDRenderer +from tinygrad.renderer.cstyle import ClangRenderer, AMDRenderer from tinygrad.uop.ops import UOp, PatternMatcher, UPat, Ops, GroupOp from tinygrad.dtype import dtypes, DType, PtrDType, truncate from tinygrad.helpers import prod, AMX @@ -45,12 +44,11 @@ def render_wmma_amx(ctx, wmma: UOp) -> str: f' call void asm sideeffect "nop\\0Anop\\0Anop\\0A.word ({0x201000 + (17 << 5) + 1})", "~{{memory}}"() #0; AMX clr', # clr f' {ctx[wmma]} = load {ldt(wmma.dtype)}, ptr {ctx[wmma]}_amx2, align {wmma.dtype.itemsize}']) -def render_wmma_amd(ctx, wmma: UOp, cdna=False) -> str: - dt_map = {dtypes.half: "f16", dtypes.float: "f32", dtypes.ushort: "bf16.1k" if cdna else "bf16", dtypes.bfloat16: "bf16.1k" if cdna else "bf16"} +def render_wmma_amd(ctx, wmma: UOp, arch: str) -> str: + dt_map = {dtypes.half: "f16", dtypes.float: "f32", dtypes.bfloat16: "bf16", dtypes.ushort: "bf16"} # https://github.com/llvm/llvm-project/blob/main/clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl - if cdna: - return f" {ctx[wmma]} = call {ldt(wmma.dtype)} @llvm.amdgcn.mfma.{dt_map[wmma.src[-1].dtype.scalar()]}" + \ - f".16x16x16{dt_map[wmma.src[0].dtype.scalar()]}(" + ", ".join([f"{ldt(w.dtype)} {ctx[w]}" for w in wmma.src]) + ", i32 0, i32 0, i32 0)" + if arch.split(":")[0] == "gfx942": return f" {ctx[wmma]} = call {ldt(wmma.dtype)} @llvm.amdgcn.mfma.{dt_map[wmma.src[-1].dtype.scalar()]}" + \ + f".16x16x16{dt_map[wmma.src[0].dtype.scalar()]}(" + ", ".join([f"{ldt(w.dtype)} {ctx[w]}" for w in wmma.src]) + ", i32 0, i32 0, i32 0)" # https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll # example: %wmma0 = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16(<16 x half> %v99,<16 x half> %v100,<8 x float> %v101) return f" {ctx[wmma]} = call {ldt(wmma.dtype)} @llvm.amdgcn.wmma.{dt_map[wmma.src[-1].dtype.scalar()]}.16x16x16." + \ @@ -59,11 +57,10 @@ def render_wmma_amd(ctx, wmma: UOp, cdna=False) -> str: # llvm ops, lop[][] unsigned_lop = { Ops.ADD: "add", Ops.MUL: "mul", Ops.IDIV: "udiv", Ops.MOD: "urem", - Ops.CMPLT: "icmp ult", Ops.CMPNE: "icmp ne", Ops.CMPEQ: "icmp eq", Ops.OR: "or", Ops.AND: "and", Ops.XOR: "xor",} + Ops.CMPLT: "icmp ult", Ops.CMPNE: "icmp ne", Ops.OR: "or", Ops.AND: "and", Ops.XOR: "xor", } signed_lop = {**unsigned_lop, Ops.ADD: "add nsw", Ops.CMPLT: "icmp slt", Ops.IDIV: "sdiv", Ops.MOD: "srem"} flags = " nsz arcp contract afn" -float_lop = {Ops.ADD: "fadd"+flags, Ops.MUL: "fmul"+flags, Ops.CMPLT: f"fcmp{flags} ult", - Ops.CMPNE: f"fcmp{flags} une", Ops.CMPEQ: f"fcmp{flags} oeq", Ops.FDIV: "fdiv"+flags} +float_lop = {Ops.ADD: "fadd"+flags, Ops.MUL: "fmul"+flags, Ops.CMPLT: f"fcmp{flags} ult", Ops.CMPNE: f"fcmp{flags} une", Ops.FDIV: "fdiv"+flags} lop = {**{x:unsigned_lop for x in (dtypes.bool,)+dtypes.uints}, **{x:signed_lop for x in dtypes.sints}, **{x:float_lop for x in dtypes.floats}} base_rewrite = PatternMatcher([ @@ -92,8 +89,6 @@ base_rewrite = PatternMatcher([ # unary/binary/ternary ops (UPat(Ops.BITCAST, name="x"), lambda ctx,x: f" {ctx[x]} = bitcast {ldt(x.src[0].dtype)} {ctx[x.src[0]]} to {ldt(x.dtype)}"), (UPat(Ops.CAST, name="x"), lambda ctx,x: f" {ctx[x]} = {lcast(x.src[0].dtype, x.dtype)} {ldt(x.src[0].dtype)} {ctx[x.src[0]]} to {ldt(x.dtype)}"), - (UPat(Ops.TRUNC, name="x"), - lambda ctx,x: f" {ctx[x]} = call {ldt(x.dtype)} @llvm.trunc.{ldt(x.dtype.scalar())}({ldt(x.src[0].dtype)} {ctx[x.src[0]]})"), (UPat(GroupOp.Binary, name="x"), lambda ctx,x: f" {ctx[x]} = {lop[x.src[0].dtype.scalar()][x.op]} {ldt(x.src[0].dtype)} {ctx[x.src[0]]}, {ctx[x.src[1]]}"), (UPat(Ops.WHERE, name="x"), lambda ctx,x: @@ -101,13 +96,13 @@ base_rewrite = PatternMatcher([ # range (UPat(Ops.RANGE, name="x"), lambda ctx,x: - f" br label %loop_entry_{x.arg[0]}\nloop_entry_{x.arg[0]}:\n" - f" br label %loop_body_{x.arg[0]}\nloop_body_{x.arg[0]}:\n" - f" {ctx[x]} = phi {ldt(x.dtype)} [ 0, %loop_entry_{x.arg[0]} ], [ {ctx[x]}phi, %loop_latch_{x.arg[0]} ]"), + f" br label %loop_entry_{x.arg}\nloop_entry_{x.arg}:\n" + f" br label %loop_body_{x.arg}\nloop_body_{x.arg}:\n" + f" {ctx[x]} = phi {ldt(x.dtype)} [ 0, %loop_entry_{x.arg} ], [ {ctx[x]}phi, %loop_latch_{x.arg} ]"), (UPat(Ops.ENDRANGE, name="x"), lambda ctx,x: - f" br label %loop_latch_{x.src[0].arg[0]}\nloop_latch_{x.src[0].arg[0]}:\n" + f" br label %loop_latch_{x.src[0].arg}\nloop_latch_{x.src[0].arg}:\n" f" {ctx[x.src[0]]}phi = add i32 {ctx[x.src[0]]}, 1\n {ctx[x]} = icmp ult i32 {ctx[x.src[0]]}phi, {ctx[x.src[0].src[0]]}\n" - f" br i1 {ctx[x]}, label %loop_body_{x.src[0].arg[0]}, label %loop_exit_{x.src[0].arg[0]}\nloop_exit_{x.src[0].arg[0]}:"), + f" br i1 {ctx[x]}, label %loop_body_{x.src[0].arg}, label %loop_exit_{x.src[0].arg}\nloop_exit_{x.src[0].arg}:"), # if (UPat(Ops.IF, name="x"), lambda ctx,x: f" br i1 {ctx[x.src[0]]}, label %ifbody_{ctx[x][1:]}, label %ifskip_{ctx[x][1:]}\nifbody_{ctx[x][1:]}:"), @@ -123,10 +118,11 @@ class LLVMRenderer(Renderer): has_local = False global_max: tuple[int, ...] | None = None string_rewrite = base_rewrite + PatternMatcher([(UPat(Ops.WMMA, name="wmma"), render_wmma_amx)]) - code_for_op = {Ops.FDIV: lambda: None} - if AMX: tensor_cores = tc.amx + if AMX: tensor_cores = ClangRenderer.amx_tc extra_matcher = PatternMatcher([ + # rewrite RECIP with FDIV + (UPat(Ops.RECIP, name="x"), lambda x: UOp(Ops.FDIV, x.dtype, (x.const_like(1), x.src[0]))), # rewrite cast to bool to CMPNE 0 (UPat(Ops.CAST, dtype=dtypes.bool, name="x"), lambda x: x.src[0] != x.src[0].const_like(0)), # rewrite MAX to CMPLT + WHERE @@ -142,7 +138,7 @@ class LLVMRenderer(Renderer): def render(self, uops: list[UOp]) -> str: return "\n".join((k:=self._render_kernel(uops))[0] + (k[1], self._render_footer(uops))) def _render_footer(self, uops: list[UOp]) -> str: return 'attributes #0 = { alwaysinline nounwind "no-builtins" "no-trapping-math"="true" }' def _render_fn(self, name:str, args:list[tuple[str,DType]], kernel:list[str], prefix:list[str]|None=None) -> str: - # NOTE: CPUAllocator promises 0x20 alignment + # NOTE: MallocAllocator promises 0x20 alignment sargs = ", ".join([f"{ldt(dt)}{' noalias align 32' if isinstance(dt, PtrDType) else ''} {name}" for name,dt in args]) sprefix = "".join([f" {x}" for x in (prefix or []) + [self.abi] if x is not None]) return "\n".join([f"define{sprefix} void @{name}({sargs}) #0", "{"] + kernel + [" ret void\n}"]) @@ -153,7 +149,13 @@ class LLVMRenderer(Renderer): vc = -1 local_args: list[str] = [] + acc_to_assign: dict[UOp, UOp] = {} for u in uops: + if u.op is Ops.ASSIGN: # prealloc all assigns + vc += 1 + r[u] = r[u.src[1]] = f"%assign{vc}" + assert u.src[0] not in acc_to_assign, "can't assign to DEFINE_ACC twice" + acc_to_assign[u.src[0]] = u.src[1] if AMX and u.op is Ops.WMMA: # prealloc aux buffers as AMX can only load from memory vc += 1 r[u] = f"%wmma{vc}" @@ -163,21 +165,21 @@ class LLVMRenderer(Renderer): name = "test" for u in uops: - if u.op is Ops.NOOP: continue if u.op is Ops.SINK: if u.arg is not None: name = u.arg.function_name continue if u.op in (Ops.DEFINE_GLOBAL, Ops.DEFINE_VAR): r[u] = f"%data{u.arg}" if u.op is Ops.DEFINE_GLOBAL else f"%{u.arg[0]}" args.append((r[u], u.dtype)) - elif u.op in (Ops.DEFINE_LOCAL, Ops.DEFINE_REG): - r[u] = f"%{'local' if u.op is Ops.DEFINE_LOCAL else 'reg'}_{str(u.arg).replace('(', '').replace(')', '').replace(',', '_').replace(' ', '')}" + elif u.op == Ops.DEFINE_LOCAL: + r[u] = f"%local_{u.arg}" assert isinstance(u.dtype, PtrDType) - if self.device == "LLVM" or u.op is Ops.DEFINE_REG: - kernel.append(f" {r[u]} = alloca [{u.dtype.size} x {ldt(u.dtype.base)}]") + if self.device == "LLVM": kernel.append(f" {r[u]} = alloca [{u.dtype.size} x {ldt(u.dtype)}], align 16") else: local_args.append(f"@{r[u][1:]} = internal unnamed_addr addrspace(3) global [{u.dtype.size} x {ldt(u.dtype)}] undef, align 16") kernel.append(f" {r[u]} = addrspacecast [{u.dtype.size} x {ldt(u.dtype)}] addrspace(3)* @{r[u][1:]} to [{u.dtype.size} x {ldt(u.dtype)}]*") + elif u.op is Ops.ASSIGN: pass # assign is already handled by the first pass + elif u.op is Ops.DEFINE_ACC: r[u] = r[u.src[0]] # a define acc can be used and never be assigned to elif u.op is Ops.CONST: r[u] = lconst(u.arg, u.dtype) elif u.op is Ops.CAST and (ldt(u.dtype) == ldt(u.src[0].dtype) or isinstance(u.dtype, PtrDType)): r[u] = r[u.src[0]] # cast from signed to unsigned of the same size is a noop, or pointer cast @@ -191,33 +193,34 @@ class LLVMRenderer(Renderer): if (l:=self.string_rewrite.rewrite(u, ctx=r)) is None: raise RuntimeError(f"failed to render {u.op} with {u.dtype} srcs {[x.dtype for x in u.src]}") kernel.append(cast(str, l)) + + # generate the phi nodes for the assigns + if u.op is Ops.RANGE: + for x in acc_to_assign: + if u in x.src: # if this range is relevant for this acc + vc += 1 + kernel.append(f" %acc{vc} = phi {ldt(x.dtype)} [ {r[x]}, %loop_entry_{u.arg} ], [ {r[acc_to_assign[x]]}, %loop_latch_{u.arg} ]") + r[x] = f"%acc{vc}" return tuple(local_args), self._render_fn(name, args, kernel, prefix) barrier = 'fence syncscope("workgroup") release\ntail call void @llvm.amdgcn.s.barrier()\nfence syncscope("workgroup") acquire\n' code_for_workitem = {"g": lambda x: f"tail call i32 @llvm.amdgcn.workgroup.id.{chr(120+int(x))}()", "l": lambda x: f"tail call i32 @llvm.amdgcn.workitem.id.{chr(120+int(x))}()"} -# https://rocm.docs.amd.com/projects/llvm-project/en/latest/LLVM/llvm/html/AMDGPUUsage.html#llvm-ir-intrinsics -# llvm.log2/llvm.exp2 don't support double -llvm_intrinsics = {Ops.SQRT: "sqrt"} class AMDLLVMRenderer(LLVMRenderer): device = "AMD" has_local = True shared_max = AMDRenderer.shared_max global_max = AMDRenderer.global_max abi = "amdgpu_kernel" - code_for_op = {**LLVMRenderer.code_for_op, **{op: lambda: None for op in llvm_intrinsics}} string_rewrite = PatternMatcher([ (UPat(Ops.SPECIAL, name="x"), lambda ctx, x: f" {ctx[x]} = " + f"{ code_for_workitem[x.arg[0][0]](x.arg[0][-1])}; "), - (UPat(tuple(llvm_intrinsics), name="x"), - lambda ctx, x: f" {ctx[x]} = call {ldt(x.dtype)} @llvm.{llvm_intrinsics[x.op]}.{ldt(x.dtype.scalar())}({ldt(x.src[0].dtype)} {ctx[x.src[0]]})"), (UPat(Ops.BARRIER), lambda ctx: barrier), + (UPat(Ops.CAST, name="x", dtype=dtypes.half.vec(16), src=UPat.var("y", dtypes.half.vec(8))), lambda ctx, x, y: f" {ctx[x]} = shufflevector "\ + f"<8 x half> {ctx[y]}, <8 x half> zeroinitializer, <16 x i32> <{', '.join([f'i32 {i}, i32 {j}' for i, j in zip(range(0, 8), range(8, 16))])}>"), + (UPat(Ops.CAST, name="x", dtype=dtypes.half.vec(8), src=UPat.var("y", dtypes.half.vec(16))), lambda ctx, x, y: + f" {ctx[x]}= shufflevector <16 x half> {ctx[y]}, <16 x half> undef, <8 x i32> <{', '.join([f'i32 {x}' for x in range(0, 16, 2)])}>"), ]) + base_rewrite - extra_matcher = LLVMRenderer.extra_matcher + PatternMatcher([ - (UPat(Ops.CAST, name="x", dtype=dtypes.half.vec(16), src=UPat.var("y", dtypes.half.vec(8))), - lambda x, y: UOp(Ops.VECTORIZE, dtypes.half.vec(16), tuple(y.gep(i // 2) if i % 2 == 0 else UOp.const(dtypes.half, 0.0) for i in range(16)))), - (UPat(Ops.CAST, name="x", dtype=dtypes.half.vec(8), src=UPat.var("y", dtypes.half.vec(16))), - lambda x, y: UOp(Ops.VECTORIZE, dtypes.half.vec(8), tuple(y.gep(i * 2) for i in range(8)))), - ]) + extra_matcher = LLVMRenderer.extra_matcher def _render_footer(self, uops: list[UOp]) -> str: # TODO: this is copied from cstyle requiredMaxThreadsPerBlock = prod(u.arg[1] for u in uops if u.op is Ops.SPECIAL and u.arg[0][0] == "l") @@ -227,14 +230,7 @@ class AMDLLVMRenderer(LLVMRenderer): def __init__(self, arch:str): self.arch = arch self.tensor_cores = AMDRenderer.get_tensor_cores(arch) - self.is_cdna = arch.split(":")[0] in {"gfx942", "gfx950"} - self.string_rewrite += PatternMatcher([(UPat(Ops.WMMA, name="wmma"), lambda ctx, wmma, cdna=self.is_cdna: render_wmma_amd(ctx, wmma, cdna))]) - if self.is_cdna: - self.extra_matcher += PatternMatcher([ - (UPat(Ops.WMMA, name="x", dtype=dtypes.float.vec(4)), - lambda x: UOp(Ops.WMMA, dtypes.float.vec(4), (x.src[0].bitcast(dtypes.uint16.vec(4)), x.src[1].bitcast(dtypes.uint16.vec(4)), - x.src[2]), (*x.arg,)) if x.src[0].dtype == dtypes.bfloat16.vec(4) else None) - ]) + self.string_rewrite += PatternMatcher([(UPat(Ops.WMMA, name="wmma"), lambda ctx, wmma, arch=arch: render_wmma_amd(ctx, wmma, arch))]) if self.arch.split(":")[0] == "gfx1100": self.extra_matcher += PatternMatcher([ (UPat(Ops.WMMA, name="x", dtype=dtypes.half.vec(8)), diff --git a/tinygrad_repo/tinygrad/renderer/ptx.py b/tinygrad_repo/tinygrad/renderer/ptx.py index e5cd17026..1b15708c8 100644 --- a/tinygrad_repo/tinygrad/renderer/ptx.py +++ b/tinygrad_repo/tinygrad/renderer/ptx.py @@ -1,12 +1,11 @@ from typing import cast, Callable import struct from collections import defaultdict -from tinygrad.codegen.opt import tc from tinygrad.uop.ops import Ops, UOp, PatternMatcher, UPat, GroupOp -from tinygrad.dtype import dtypes, DType, PtrDType, AddrSpace +from tinygrad.dtype import dtypes, DType, PtrDType from tinygrad.renderer import Renderer from tinygrad.renderer.cstyle import CUDARenderer -from tinygrad.helpers import flatten, get_single_element, prod +from tinygrad.helpers import flatten, get_single_element def render_val(x, dtype): if dtypes.is_float(dtype): @@ -19,7 +18,6 @@ asm_for_op: dict[Ops, Callable] = { Ops.RECIP: lambda d,a,dt,name: f"rcp{'.approx' if dtypes.is_float(dt) else ''}.{name} {d}, {a};", Ops.EXP2: lambda d,a,dt,name: f"ex2.approx.{name} {d}, {a};", Ops.LOG2: lambda d,a,dt,name: f"lg2.approx.{name} {d}, {a};", Ops.SIN: lambda d,a,dt,name: f"sin.approx.{name} {d}, {a};", Ops.SQRT: lambda d,a,dt,name: f"sqrt.approx.{name} {d}, {a};", - Ops.TRUNC: lambda d,a,dt,name: f"cvt.rzi.{name}.{name} {d}, {a};", Ops.SHR: lambda d,a,b,dt,name: f"shr.{name} {d}, {a}, {b};", Ops.SHL: lambda d,a,b,dt,name: f"shl.b{name[1:]} {d}, {a}, {b};", Ops.ADD: lambda d,a,b,dt,name: f"{'or' if dt == dtypes.bool else 'add'}.{name} {d}, {a}, {b};", Ops.MUL: lambda d,a,b,dt,name: f"{'and' if dt == dtypes.bool else 'mul'}{'.lo' if dtypes.is_int(dt) else ''}.{name} {d}, {a}, {b};", @@ -27,19 +25,18 @@ asm_for_op: dict[Ops, Callable] = { Ops.AND: lambda d,a,b,dt, name: f"and.pred {d}, {a}, {b};" if dt == dtypes.bool else f"and.b{name[1:]} {d}, {a}, {b};", Ops.OR: lambda d,a,b,dt, name: f"or.pred {d}, {a}, {b};" if dt == dtypes.bool else f"or.b{name[1:]} {d}, {a}, {b};", Ops.IDIV: lambda d,a,b,dt,name: f"div.{name} {d}, {a}, {b};", Ops.MOD: lambda d,a,b,dt,name: f"rem.{name} {d}, {a}, {b};", - Ops.MAX: lambda d,a,b,dt,name: f"max.{name} {d}, {a}, {b};", Ops.CMPEQ: lambda d,a,b,dt,name: f"setp.eq.{name} {d}, {a}, {b};", + Ops.MAX: lambda d,a,b,dt,name: f"max.{name} {d}, {a}, {b};", Ops.CMPLT: lambda d,a,b,dt,name: f"setp.lt.{name} {d}, {a}, {b};", Ops.CMPNE: lambda d,a,b,dt,name: f"setp.ne.{name} {d}, {a}, {b};", Ops.MULACC: lambda d,a,b,c,dt,name: f"{'fma.rn' if dtypes.is_float(dt) else 'mad.lo'}.{name} {d}, {a}, {b}, {c};", Ops.WHERE: lambda d,a,b,c,dt,name: [f"@{a} mov.{name} {d}, {b};", f"@!{a} mov.{name} {d}, {c};"] if dt == dtypes.bool else \ f"selp.{'b16' if name == 'f16' else name} {d}, {b}, {c}, {a};" } -supports_half = (Ops.EXP2, Ops.ADD, Ops.MUL, Ops.MAX, Ops.CMPLT, Ops.WHERE, Ops.TRUNC) +supports_half = (Ops.EXP2, Ops.ADD, Ops.MUL, Ops.MAX, Ops.CMPLT, Ops.WHERE) doesnt_support_half: tuple[Ops, ...] = tuple(op for op in asm_for_op.keys() if op not in supports_half) ptx_matcher = PatternMatcher([ # bool CMPNE is XOR, bool CMPLT is XOR+AND (universal makes this slow, this is for renderer only) (UPat.var('x', dtype=dtypes.bool).ne(UPat.var('y')), lambda x,y: x^y), - (UPat.var('x', dtype=dtypes.bool).alu(Ops.CMPEQ, UPat.var('y')), lambda x,y: (x^y)^True), (UPat.var('x', dtype=dtypes.bool) 1 else ctx.r[var]};"), (UPat(Ops.SPECIAL, name="x"), lambda ctx,x: f"mov.u32 %{x.arg[0]}, %{'ctaid' if x.arg[0][0] == 'g' else 'tid'}.{chr(120+int(x.arg[0][-1]))};"), (UPat(Ops.DEFINE_GLOBAL, name="x"), lambda ctx, x: f"ld.param.{ctx.types[dtypes.ulong]} {ctx.r[x]}, [data{x.arg}+0];"), - (UPat((Ops.CMPLT, Ops.CMPNE, Ops.CMPEQ), name="x", allow_any_len=True, src=(UPat.var("src0"),)), + (UPat((Ops.CMPLT, Ops.CMPNE), name="x", allow_any_len=True, src=(UPat.var("src0"),)), lambda ctx, x, src0: ctx.code_for_op[x.op](ctx.r[x], *[ctx.r[v] for v in x.src], src0.dtype, ctx.types[src0.dtype])), (UPat(GroupOp.ALU, name="x"), lambda ctx, x: ctx.code_for_op[x.op](ctx.r[x], *[ctx.r[v] for v in x.src], x.dtype, ctx.types[x.dtype])), (UPat(Ops.BITCAST, name="x", src=(UPat.var("a"),), allow_any_len=True), lambda ctx, x, a: f"mov.b{ctx.types[x.dtype][1:]} {ctx.r[x]}, {ctx.r[a]};"), @@ -112,14 +108,19 @@ string_rewrite = PatternMatcher([ (UPat(Ops.LOAD, name="x", src=(UPat.var('loc'),), allow_any_len=True), lambda ctx, x, loc: f"ld.{mem_type(x)}.v{x.dtype.count}.{ctx.mem_types[x.dtype.scalar()]} {{{', '.join(ctx.r[x])}}}, [{ctx.r[loc]}+0];" \ if x.dtype.count > 1 else f"ld.{mem_type(x)}.{ctx.mem_types[x.dtype]} {ctx.r[x]}, [{ctx.r[loc]}+0];"), - (UPat(Ops.DEFINE_REG, src=()), lambda ctx: []), + (UPat(Ops.DEFINE_ACC, name="x", src=(UPat.cvar("pred", dtype=dtypes.bool),), allow_any_len=True), lambda ctx, x, pred: [ + f"setp.ne.s16 {ctx.r[pred]}, {render_val(pred.arg, pred.dtype)}, 0;", f"mov.pred {ctx.r[x]}, {ctx.r[pred]};"]), + (UPat(Ops.DEFINE_ACC, name="x", src=(UPat.cvar("pred"),), allow_any_len=True), + lambda ctx, x, pred: f"mov.b{ctx.types[x.dtype][1:]} {ctx.r[x]}, {render_val(pred.arg, x.dtype)};"), (UPat(Ops.RANGE, name="x"), lambda ctx, x: [f"mov.u32 {ctx.r[x]}, 0;", "LOOP_" + f"{ctx.r[x][1:]}:"]), + (UPat(Ops.ASSIGN, name="x", dtype=dtypes.bool), lambda ctx, x: [f"mov.pred {ctx.r[x.src[0]]}, {ctx.r[x.src[1]]};"]), + (UPat(Ops.ASSIGN, name="x"), lambda ctx, x: f"mov.b{ctx.types[x.dtype][1:]} {ctx.r[x.src[0]]}, {ctx.r[x.src[1]]};"), (UPat(Ops.ENDRANGE, name="x", src=(UPat.var("src0"),)), lambda ctx, x, src0: [ ctx.code_for_op[Ops.ADD](ctx.r[src0], ctx.r[src0], "1", dtypes.int, ctx.types[dtypes.int]), ctx.code_for_op[Ops.CMPLT](ctx.r[x], ctx.r[x.src[0]], ctx.r[src0.src[0]], dtypes.int, ctx.types[dtypes.int]), f"@{ctx.r[x]} bra LOOP_{ctx.r[src0][1:]};"]), (UPat(Ops.DEFINE_LOCAL, name="x"), - lambda ctx, x: [f".shared .align 16 .b8 local{x.arg}[{x.dtype.size*x.dtype.itemsize}];", f"mov.u64 {ctx.r[x]}, local{x.arg}[0];"]), + lambda ctx, x: [f".shared .align 16 .b8 {x.arg}[{x.dtype.size*x.dtype.itemsize}];", f"mov.u64 {ctx.r[x]}, {x.arg}[0];"]), (UPat(Ops.IF, name="x"), lambda ctx, x: f"@!{ctx.r[x.src[0]]} bra IF_{ctx.r[x.src[0]][1:]}_{ctx.uops.index(x)};"), (UPat(Ops.ENDIF, name="x"), lambda ctx, x: f"IF_{ctx.r[x.src[0].src[0]][1:]}_{ctx.uops.index(x.src[0])}:"), (UPat(Ops.WMMA, name="x"), lambda ctx, x: list(render_wmma(ctx, x))), @@ -131,12 +132,12 @@ class PTXRenderer(Renderer): device = "CUDA" suffix = "PTX" global_max, local_max, shared_max = CUDARenderer.global_max, CUDARenderer.local_max, CUDARenderer.shared_max - tc_sm80 = [x for x in tc.cuda_sm80 if x.dtype_in in [dtypes.half, dtypes.float]] + tc_sm80 = [tc for tc in CUDARenderer.tc_sm80 if tc.dtype_in in [dtypes.half, dtypes.float]] code_for_op = asm_for_op extra_matcher = ptx_matcher def __init__(self, arch:str, device="CUDA"): self.device, self.arch = device, arch - self.tensor_cores = PTXRenderer.tc_sm80 if int(arch[3:]) >= 80 else tc.cuda_sm75 if int(arch[3:]) >= 75 else [] + self.tensor_cores = PTXRenderer.tc_sm80 if int(arch[3:]) >= 80 else CUDARenderer.tc_sm75 if int(arch[3:]) >= 75 else [] def __reduce__(self): return self.__class__, (self.arch, self.device) # language options @@ -152,12 +153,11 @@ class PTXRenderer(Renderer): mem_types: dict[DType, str] = {**types, dtypes.int8: "s8", dtypes.uint8: "u8", dtypes.bool: "u8", dtypes.float16: "b16"} - def render_kernel(self, kernel, function_name, bufs, regs, uops) -> str: + def render_kernel(self, kernel, function_name, bufs, regs) -> str: def fmt(line): return line if line[0]=="$" else "\t" + line.replace(" ", "\t" if len(line.split(" ")[0]) > 7 else "\t\t", 1) kernel = '\n'.join(map(fmt, [f".reg .{reg.split('_')[-2]} %{reg}<{cnt}>;" for reg,cnt in regs] + kernel + ["ret;"])) - launch_bounds = prod(u.arg[1] for u in uops if u.op is Ops.SPECIAL and u.arg[0][0] == "l") params = ',\n\t'.join([f".param .{'u64' if dtype.__class__ == PtrDType else self.types[dtype]} {name}" for name,dtype in bufs]) - return f"{self.kernel_prefix.format(launch_bounds=launch_bounds)} {function_name} (\n\t{params}\n)\n.maxntid {launch_bounds}\n{{\n{kernel}\n}}" + return f"{self.kernel_prefix} {function_name}(\n\t{params}\n)\n{{\n{kernel}\n}}" def render(self, uops:list[UOp]) -> str: kernel:list[str] = [] @@ -170,13 +170,12 @@ class PTXRenderer(Renderer): def ssa(prefix:str, u:UOp|None=None, dtype:str|None=None) -> str: nonlocal c, r - prefix += f"_{dtype if dtype is not None else self.types[cast(UOp, u).dtype.base]}_" + prefix += f"_{dtype if dtype is not None else self.types[cast(UOp, u).dtype]}_" c[prefix] += 1 return f"%{prefix}{c[prefix]-1}" name = "test" for u in uops: - if u.op is Ops.NOOP: continue if u.op is Ops.SINK: if u.arg is not None: name = u.arg.function_name continue @@ -189,19 +188,6 @@ class PTXRenderer(Renderer): if u.op in {Ops.CAST, Ops.BITCAST} and (u.src[0].dtype == u.dtype or isinstance(u.src[0].dtype, PtrDType)): r[u] = r[u.src[0]] continue - if u.op is Ops.DEFINE_REG: - r[u] = [ssa("reg", u, self.types[u.dtype.base.scalar()]) for _ in range(cast(PtrDType, u.dtype).size)] - continue - if u.op in {Ops.INDEX, Ops.LOAD, Ops.STORE} and isinstance(u.src[0].dtype, PtrDType) and u.src[0].dtype.addrspace == AddrSpace.REG: - if u.op is Ops.INDEX: - assert u.src[1].op == Ops.CONST, f"index on REG in ptx only supported on CONST, not {u.src[1].op}" - r[u] = r[u.src[0]][u.src[1].arg] - else: - r[u] = r[u.src[0]] - if u.op is Ops.STORE: - typ = "pred" if u.src[1].dtype == dtypes.bool else ("b"+self.types[u.src[1].dtype][1:]) - kernel.append(f"mov.{typ} {self.r[u.src[0]]}, {self.r[u.src[1]]};") - continue if u.op is Ops.SPECIAL: r[u] = "%" + u.arg[0] elif u.op is Ops.DEFINE_VAR: bufs.append((u.arg[0], u.dtype)) elif u.op is Ops.LOAD: @@ -210,12 +196,12 @@ class PTXRenderer(Renderer): elif u.op is Ops.DEFINE_GLOBAL: bufs.append((f"data{u.arg}", u.dtype)) elif u.op is Ops.WMMA: # registers for packing/unpacking input and acc - self.wmma_r = [[ssa("wmma_in", dtype="b32") for _ in range(0, len(r[u.src[0]]), 4 // u.src[0].dtype.scalar().itemsize)], - [ssa("wmma_in", dtype="b32") for _ in range(0, len(r[u.src[1]]), 4 // u.src[0].dtype.scalar().itemsize)], - [ssa("wmma_acc", dtype="b32") for _ in range(0, len(r[u.src[2]]), 4 // u.dtype.scalar().itemsize)]] + self.wmma_r = [[ssa("wmma_in", dtype="b32") for _ in range(0, len(r[u.src[0]]), 4 // u.arg[2].itemsize)], + [ssa("wmma_in", dtype="b32") for _ in range(0, len(r[u.src[1]]), 4 // u.arg[2].itemsize)], + [ssa("wmma_acc", dtype="b32") for _ in range(0, len(r[u.src[2]]), 4 // u.arg[3].itemsize)]] r[u] = [ssa("wmma", dtype=self.types[u.dtype.scalar()]) for _ in range(u.dtype.count)] prefix, dtype = {Ops.CAST: ("cast", None), Ops.BITCAST: ("cast", None), Ops.ENDRANGE: ("pred", "pred"), Ops.RANGE: ("ridx", None), - Ops.DEFINE_VAR: ("dat", None), Ops.CONST: ("const", None), Ops.DEFINE_LOCAL: ("local",self.types[dtypes.ulong]), + Ops.DEFINE_ACC: ("acc", None), Ops.DEFINE_VAR: ("dat", None), Ops.CONST: ("const", None), Ops.DEFINE_LOCAL:("local",self.types[dtypes.ulong]), Ops.DEFINE_GLOBAL: ("dat", self.types[dtypes.ulong]), **{op: ("alu", None) for op in GroupOp.ALU}}.get(u.op, (None, None)) if prefix: r[u] = ssa(prefix, u, dtype) @@ -223,5 +209,6 @@ class PTXRenderer(Renderer): raise RuntimeError(f"failed to render {u.op} with {u.dtype} srcs {[x.dtype for x in u.src]}") kernel.extend([l] if isinstance(l, str) else l) - if u.op is Ops.SPECIAL: kernel = [f".reg .u32 %{u.arg[0]};"] + kernel - return self.render_kernel(kernel, name, bufs, c.items(), uops) + if u.op is Ops.ASSIGN: r[u] = r[u.src[0]] + elif u.op is Ops.SPECIAL: kernel = [f".reg .u32 %{u.arg[0]};"] + kernel + return self.render_kernel(kernel, name, bufs, c.items()) diff --git a/tinygrad_repo/tinygrad/renderer/wgsl.py b/tinygrad_repo/tinygrad/renderer/wgsl.py index 4063a23c7..3083e50d8 100644 --- a/tinygrad_repo/tinygrad/renderer/wgsl.py +++ b/tinygrad_repo/tinygrad/renderer/wgsl.py @@ -1,4 +1,4 @@ -from tinygrad.dtype import DType, PtrDType, dtypes, AddrSpace +from tinygrad.dtype import DType, PtrDType, dtypes from tinygrad.uop.ops import UOp, Ops, PatternMatcher, UPat from tinygrad.renderer.cstyle import CStyleLanguage, base_rewrite, extra_pm from tinygrad.helpers import strip_parens @@ -24,18 +24,14 @@ def packed_load(root:UOp, bidx:UOp, dtype:DType, var:UOp|None=None): val = (load.cast(dtypes.uint32) >> shift_am) & (0xFF if dtype.itemsize == 1 else 0xFFFF) return sign_extend(val, 8*dtype.itemsize).cast(dtype) if dtype in [dtypes.char, dtypes.short] else val.cast(dtype) -def is_packed(dt:DType, odt:DType|None = None) -> bool: - if odt is None: odt = dt - return dt.itemsize < 4 and dt.base != dtypes.half and (not isinstance(odt, PtrDType) or odt.addrspace != AddrSpace.REG) +def is_packed(dt:DType) -> bool: return dt.itemsize < 4 and dt.base != dtypes.half wgsl_matcher = PatternMatcher([ (UPat((Ops.CMPLT, Ops.XOR), src=(UPat(name="a", dtype=dtypes.bool), UPat.var("b")), name="c"), lambda a,b,c: a.cast(dtypes.int).alu(c.op, b.cast(dtypes.int)).cast(dtypes.bool)), - (UPat.load(UPat.var("b"), UPat.cvar("c"), name="l"), - lambda l,b,c: packed_load(l,b,l.dtype,c.cast(dtypes.uint32)) if is_packed(l.dtype, b.dtype) else None), - (UPat.load(UPat.var("b"), name='l', allow_any_len=True), lambda l,b: packed_load(l, b, l.dtype) if is_packed(l.dtype, b.dtype) else None), - (UPat.store(UPat.var("bidx"), UPat.var("var"), allow_any_len=True), - lambda bidx,var: packed_store(bidx,var) if is_packed(var.dtype, bidx.dtype) else None), + (UPat.load(UPat.var("b"), UPat.cvar("c"), name="l"),lambda l,b,c: packed_load(l,b,l.dtype,c.cast(dtypes.uint32)) if is_packed(l.dtype) else None), + (UPat.load(UPat.var("b"), name='l', allow_any_len=True), lambda l,b: packed_load(l, b, l.dtype) if is_packed(l.dtype) else None), + (UPat.store(UPat.var("bidx"), UPat.var("var"), allow_any_len=True), lambda bidx,var: packed_store(bidx,var) if is_packed(var.dtype) else None), (UPat.var("a") << UPat.var("b"),lambda a,b:(a.bitcast(dtypes.uint32)<> UPat.var("y"), lambda x,y: UOp(Ops.SHR, x.dtype, (x,y.cast(dtypes.uint))) if y.dtype != dtypes.uint else None), ]) + extra_pm @@ -59,8 +55,6 @@ class WGSLRenderer(CStyleLanguage): lambda x: f"bitcast({x.arg})" if x.arg < 0 else f"{x.arg&0xFFFFFFFF}u"), (UPat(Ops.DEFINE_LOCAL, name="x"), lambda ctx,x: f"var {ctx[x]}: array<{ctx.buf_map(x.dtype.base)},{x.dtype.size//(4//x.dtype.itemsize) if is_packed(x.dtype) else x.dtype.size}>;"), - (UPat(Ops.DEFINE_REG, name="x"), lambda ctx,x: - f"var {ctx[x]}: array<{ctx.buf_map(x.dtype)},{x.dtype.size//(4//x.dtype.itemsize) if is_packed(x.dtype) else x.dtype.size}>;"), (UPat(Ops.BITCAST, dtype=dtypes.half, name="x", src=(UPat(dtype=(dtypes.short, dtypes.ushort, dtypes.uint32),),)), lambda ctx,x: f"bitcast>({ctx[x.src[0]]})[0]"), (UPat(Ops.BITCAST, dtype=(dtypes.char, dtypes.uchar), name="x"), lambda ctx,x: f"bitcast<{ctx.type_map[x.dtype]}>({ctx[x.src[0]]}&0xFF)"), diff --git a/tinygrad_repo/tinygrad/runtime/autogen/am/navi10.py b/tinygrad_repo/tinygrad/runtime/autogen/am/navi10.py new file mode 100644 index 000000000..1960cec8c --- /dev/null +++ b/tinygrad_repo/tinygrad/runtime/autogen/am/navi10.py @@ -0,0 +1,40774 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_navi10_ENUM_HEADER = True # macro +ENUMS_GDS_PERFCOUNT_SELECT_H = True # macro +SQ_WAVE_TYPE_PS0 = 0x00000000 # macro +SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro +SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro +SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro +SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro +SQIND_WAVE_HWREGS_OFFSET = 0x00000100 # macro +SQIND_WAVE_HWREGS_SIZE = 0x00000100 # macro +SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro +SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro +SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro +SQIND_WAVE_VGPRS_SIZE = 0x00000400 # macro +SQ_GFXDEC_BEGIN = 0x0000a000 # macro +SQ_GFXDEC_END = 0x0000c000 # macro +SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro +SQDEC_BEGIN = 0x00002300 # macro +SQDEC_END = 0x000023ff # macro +SQPERFSDEC_BEGIN = 0x0000d9c0 # macro +SQPERFSDEC_END = 0x0000da40 # macro +SQPERFDDEC_BEGIN = 0x0000d1c0 # macro +SQPERFDDEC_END = 0x0000d240 # macro +SQGFXUDEC_BEGIN = 0x0000c330 # macro +SQGFXUDEC_END = 0x0000c380 # macro +SQPWRDEC_BEGIN = 0x0000f08c # macro +SQPWRDEC_END = 0x0000f094 # macro +SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro +SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro +SQ_MAX_PGM_SGPRS = 0x00000068 # macro +SQ_MAX_PGM_VGPRS = 0x00000100 # macro +SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro +SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro +SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro +SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro +SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro +SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro +SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro +SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro +SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro +SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro +SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro +INST_ID_PRIV_START = 0x80000000 # macro +INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro +INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro +INST_ID_HW_TRAP = 0xfffffff2 # macro +INST_ID_KILL_SEQ = 0xfffffff3 # macro +INST_ID_SPI_WREXEC = 0xfffffff4 # macro +INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro +SIMM16_WAITCNT_VM_CNT_START = 0x00000000 # macro +SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000004 # macro +SIMM16_WAITCNT_EXP_CNT_START = 0x00000004 # macro +SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_LGKM_CNT_START = 0x00000008 # macro +SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000004 # macro +SIMM16_WAITCNT_VM_CNT_HI_START = 0x0000000e # macro +SIMM16_WAITCNT_VM_CNT_HI_SIZE = 0x00000002 # macro +SIMM16_WAITCNT_DEPCTR_SA_SDST_START = 0x00000000 # macro +SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_VCC_START = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VM_VSRC_START = 0x00000002 # macro +SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_DEPCTR_VA_SSRC_START = 0x00000008 # macro +SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_SDST_START = 0x00000009 # macro +SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_DEPCTR_VA_VDST_START = 0x0000000c # macro +SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE = 0x00000004 # macro +SQ_EDC_FUE_CNTL_SIMD0 = 0x00000000 # macro +SQ_EDC_FUE_CNTL_SIMD1 = 0x00000001 # macro +SQ_EDC_FUE_CNTL_SIMD2 = 0x00000002 # macro +SQ_EDC_FUE_CNTL_SIMD3 = 0x00000003 # macro +SQ_EDC_FUE_CNTL_SQ = 0x00000004 # macro +SQ_EDC_FUE_CNTL_LDS = 0x00000005 # macro +SQ_EDC_FUE_CNTL_TD = 0x00000006 # macro +SQ_EDC_FUE_CNTL_TA = 0x00000007 # macro +SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro +CSDATA_TYPE_WIDTH = 0x00000002 # macro +CSDATA_ADDR_WIDTH = 0x00000007 # macro +CSDATA_DATA_WIDTH = 0x00000020 # macro +CSCNTL_TYPE_WIDTH = 0x00000002 # macro +CSCNTL_ADDR_WIDTH = 0x00000007 # macro +CSCNTL_DATA_WIDTH = 0x00000020 # macro +GSTHREADID_SIZE = 0x00000002 # macro +SEM_ECC_ERROR = 0x00000000 # macro +SEM_TRANS_ERROR = 0x00000001 # macro +SEM_RESP_FAILED = 0x00000002 # macro +SEM_RESP_PASSED = 0x00000003 # macro +IQ_QUEUE_SLEEP = 0x00000000 # macro +IQ_OFFLOAD_RETRY = 0x00000001 # macro +IQ_SCH_WAVE_MSG = 0x00000002 # macro +IQ_SEM_REARM = 0x00000003 # macro +IQ_DEQUEUE_RETRY = 0x00000004 # macro +IQ_INTR_TYPE_PQ = 0x00000000 # macro +IQ_INTR_TYPE_IB = 0x00000001 # macro +IQ_INTR_TYPE_MQD = 0x00000002 # macro +VMID_SZ = 0x00000004 # macro +CONFIG_SPACE_START = 0x00002000 # macro +CONFIG_SPACE_END = 0x00009fff # macro +CONFIG_SPACE1_START = 0x00002000 # macro +CONFIG_SPACE1_END = 0x00002bff # macro +CONFIG_SPACE2_START = 0x00003000 # macro +CONFIG_SPACE2_END = 0x00009fff # macro +UCONFIG_SPACE_START = 0x0000c000 # macro +UCONFIG_SPACE_END = 0x0000ffff # macro +PERSISTENT_SPACE_START = 0x00002c00 # macro +PERSISTENT_SPACE_END = 0x00002fff # macro +CONTEXT_SPACE_START = 0x0000a000 # macro +CONTEXT_SPACE_END = 0x0000bfff # macro +ROM_SIGNATURE = 0x0000aa55 # macro +IP_USB_PD_REVISION_ID = 0x00000000 # macro + +# values for enumeration 'GDS_PERFCOUNT_SELECT' +GDS_PERFCOUNT_SELECT__enumvalues = { + 0: 'GDS_PERF_SEL_DS_ADDR_CONFL', + 1: 'GDS_PERF_SEL_DS_BANK_CONFL', + 2: 'GDS_PERF_SEL_WBUF_FLUSH', + 3: 'GDS_PERF_SEL_WR_COMP', + 4: 'GDS_PERF_SEL_WBUF_WR', + 5: 'GDS_PERF_SEL_RBUF_HIT', + 6: 'GDS_PERF_SEL_RBUF_MISS', + 7: 'GDS_PERF_SEL_SE0_SH0_NORET', + 8: 'GDS_PERF_SEL_SE0_SH0_RET', + 9: 'GDS_PERF_SEL_SE0_SH0_ORD_CNT', + 10: 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ', + 11: 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', + 12: 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID', + 13: 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD', + 14: 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', + 15: 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP', + 16: 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP', + 17: 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP', + 18: 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP', + 19: 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP', + 20: 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP', + 21: 'GDS_PERF_SEL_SE0_SH1_NORET', + 22: 'GDS_PERF_SEL_SE0_SH1_RET', + 23: 'GDS_PERF_SEL_SE0_SH1_ORD_CNT', + 24: 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ', + 25: 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', + 26: 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID', + 27: 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD', + 28: 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', + 29: 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP', + 30: 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP', + 31: 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP', + 32: 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP', + 33: 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP', + 34: 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP', + 35: 'GDS_PERF_SEL_SE1_SH0_NORET', + 36: 'GDS_PERF_SEL_SE1_SH0_RET', + 37: 'GDS_PERF_SEL_SE1_SH0_ORD_CNT', + 38: 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ', + 39: 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', + 40: 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID', + 41: 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD', + 42: 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', + 43: 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP', + 44: 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP', + 45: 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP', + 46: 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP', + 47: 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP', + 48: 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP', + 49: 'GDS_PERF_SEL_SE1_SH1_NORET', + 50: 'GDS_PERF_SEL_SE1_SH1_RET', + 51: 'GDS_PERF_SEL_SE1_SH1_ORD_CNT', + 52: 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ', + 53: 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', + 54: 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID', + 55: 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD', + 56: 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', + 57: 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP', + 58: 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP', + 59: 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP', + 60: 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP', + 61: 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP', + 62: 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP', + 63: 'GDS_PERF_SEL_SE2_SH0_NORET', + 64: 'GDS_PERF_SEL_SE2_SH0_RET', + 65: 'GDS_PERF_SEL_SE2_SH0_ORD_CNT', + 66: 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ', + 67: 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', + 68: 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID', + 69: 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD', + 70: 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', + 71: 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP', + 72: 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP', + 73: 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP', + 74: 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP', + 75: 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP', + 76: 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP', + 77: 'GDS_PERF_SEL_SE2_SH1_NORET', + 78: 'GDS_PERF_SEL_SE2_SH1_RET', + 79: 'GDS_PERF_SEL_SE2_SH1_ORD_CNT', + 80: 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ', + 81: 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', + 82: 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID', + 83: 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD', + 84: 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', + 85: 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP', + 86: 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP', + 87: 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP', + 88: 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP', + 89: 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP', + 90: 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP', + 91: 'GDS_PERF_SEL_SE3_SH0_NORET', + 92: 'GDS_PERF_SEL_SE3_SH0_RET', + 93: 'GDS_PERF_SEL_SE3_SH0_ORD_CNT', + 94: 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ', + 95: 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', + 96: 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID', + 97: 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD', + 98: 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', + 99: 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP', + 100: 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP', + 101: 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP', + 102: 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP', + 103: 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP', + 104: 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP', + 105: 'GDS_PERF_SEL_SE3_SH1_NORET', + 106: 'GDS_PERF_SEL_SE3_SH1_RET', + 107: 'GDS_PERF_SEL_SE3_SH1_ORD_CNT', + 108: 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ', + 109: 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', + 110: 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID', + 111: 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD', + 112: 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', + 113: 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP', + 114: 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP', + 115: 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP', + 116: 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP', + 117: 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP', + 118: 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP', + 119: 'GDS_PERF_SEL_GWS_RELEASED', + 120: 'GDS_PERF_SEL_GWS_BYPASS', +} +GDS_PERF_SEL_DS_ADDR_CONFL = 0 +GDS_PERF_SEL_DS_BANK_CONFL = 1 +GDS_PERF_SEL_WBUF_FLUSH = 2 +GDS_PERF_SEL_WR_COMP = 3 +GDS_PERF_SEL_WBUF_WR = 4 +GDS_PERF_SEL_RBUF_HIT = 5 +GDS_PERF_SEL_RBUF_MISS = 6 +GDS_PERF_SEL_SE0_SH0_NORET = 7 +GDS_PERF_SEL_SE0_SH0_RET = 8 +GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9 +GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10 +GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11 +GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12 +GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13 +GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14 +GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15 +GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16 +GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17 +GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18 +GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19 +GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20 +GDS_PERF_SEL_SE0_SH1_NORET = 21 +GDS_PERF_SEL_SE0_SH1_RET = 22 +GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23 +GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24 +GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25 +GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26 +GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27 +GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28 +GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29 +GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30 +GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31 +GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32 +GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33 +GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34 +GDS_PERF_SEL_SE1_SH0_NORET = 35 +GDS_PERF_SEL_SE1_SH0_RET = 36 +GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37 +GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38 +GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39 +GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40 +GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41 +GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42 +GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43 +GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44 +GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45 +GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46 +GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47 +GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48 +GDS_PERF_SEL_SE1_SH1_NORET = 49 +GDS_PERF_SEL_SE1_SH1_RET = 50 +GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51 +GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52 +GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53 +GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54 +GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55 +GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56 +GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57 +GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58 +GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59 +GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60 +GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61 +GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62 +GDS_PERF_SEL_SE2_SH0_NORET = 63 +GDS_PERF_SEL_SE2_SH0_RET = 64 +GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65 +GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66 +GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67 +GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68 +GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69 +GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70 +GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71 +GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72 +GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73 +GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74 +GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75 +GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76 +GDS_PERF_SEL_SE2_SH1_NORET = 77 +GDS_PERF_SEL_SE2_SH1_RET = 78 +GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79 +GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80 +GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81 +GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82 +GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83 +GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84 +GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85 +GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86 +GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87 +GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88 +GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89 +GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90 +GDS_PERF_SEL_SE3_SH0_NORET = 91 +GDS_PERF_SEL_SE3_SH0_RET = 92 +GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93 +GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94 +GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95 +GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96 +GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97 +GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98 +GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99 +GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100 +GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101 +GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102 +GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103 +GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104 +GDS_PERF_SEL_SE3_SH1_NORET = 105 +GDS_PERF_SEL_SE3_SH1_RET = 106 +GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107 +GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108 +GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109 +GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110 +GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111 +GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112 +GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113 +GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114 +GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115 +GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116 +GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117 +GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118 +GDS_PERF_SEL_GWS_RELEASED = 119 +GDS_PERF_SEL_GWS_BYPASS = 120 +GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'GATCL1RequestType' +GATCL1RequestType__enumvalues = { + 0: 'GATCL1_TYPE_NORMAL', + 1: 'GATCL1_TYPE_SHOOTDOWN', + 2: 'GATCL1_TYPE_BYPASS', +} +GATCL1_TYPE_NORMAL = 0 +GATCL1_TYPE_SHOOTDOWN = 1 +GATCL1_TYPE_BYPASS = 2 +GATCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1RequestType' +UTCL1RequestType__enumvalues = { + 0: 'UTCL1_TYPE_NORMAL', + 1: 'UTCL1_TYPE_SHOOTDOWN', + 2: 'UTCL1_TYPE_BYPASS', +} +UTCL1_TYPE_NORMAL = 0 +UTCL1_TYPE_SHOOTDOWN = 1 +UTCL1_TYPE_BYPASS = 2 +UTCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1FaultType' +UTCL1FaultType__enumvalues = { + 0: 'UTCL1_XNACK_SUCCESS', + 1: 'UTCL1_XNACK_RETRY', + 2: 'UTCL1_XNACK_PRT', + 3: 'UTCL1_XNACK_NO_RETRY', +} +UTCL1_XNACK_SUCCESS = 0 +UTCL1_XNACK_RETRY = 1 +UTCL1_XNACK_PRT = 2 +UTCL1_XNACK_NO_RETRY = 3 +UTCL1FaultType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL0RequestType' +UTCL0RequestType__enumvalues = { + 0: 'UTCL0_TYPE_NORMAL', + 1: 'UTCL0_TYPE_SHOOTDOWN', + 2: 'UTCL0_TYPE_BYPASS', +} +UTCL0_TYPE_NORMAL = 0 +UTCL0_TYPE_SHOOTDOWN = 1 +UTCL0_TYPE_BYPASS = 2 +UTCL0RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL0FaultType' +UTCL0FaultType__enumvalues = { + 0: 'UTCL0_XNACK_SUCCESS', + 1: 'UTCL0_XNACK_RETRY', + 2: 'UTCL0_XNACK_PRT', + 3: 'UTCL0_XNACK_NO_RETRY', +} +UTCL0_XNACK_SUCCESS = 0 +UTCL0_XNACK_RETRY = 1 +UTCL0_XNACK_PRT = 2 +UTCL0_XNACK_NO_RETRY = 3 +UTCL0FaultType = ctypes.c_uint32 # enum + +# values for enumeration 'VMEMCMD_RETURN_ORDER' +VMEMCMD_RETURN_ORDER__enumvalues = { + 0: 'VMEMCMD_RETURN_OUT_OF_ORDER', + 1: 'VMEMCMD_RETURN_IN_ORDER', + 2: 'VMEMCMD_RETURN_IN_ORDER_READ', +} +VMEMCMD_RETURN_OUT_OF_ORDER = 0 +VMEMCMD_RETURN_IN_ORDER = 1 +VMEMCMD_RETURN_IN_ORDER_READ = 2 +VMEMCMD_RETURN_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'GL0V_CACHE_POLICIES' +GL0V_CACHE_POLICIES__enumvalues = { + 0: 'GL0V_CACHE_POLICY_MISS_LRU', + 1: 'GL0V_CACHE_POLICY_MISS_EVICT', + 2: 'GL0V_CACHE_POLICY_HIT_LRU', + 3: 'GL0V_CACHE_POLICY_HIT_EVICT', +} +GL0V_CACHE_POLICY_MISS_LRU = 0 +GL0V_CACHE_POLICY_MISS_EVICT = 1 +GL0V_CACHE_POLICY_HIT_LRU = 2 +GL0V_CACHE_POLICY_HIT_EVICT = 3 +GL0V_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL1_CACHE_POLICIES' +GL1_CACHE_POLICIES__enumvalues = { + 0: 'GL1_CACHE_POLICY_MISS_LRU', + 1: 'GL1_CACHE_POLICY_MISS_EVICT', + 2: 'GL1_CACHE_POLICY_HIT_LRU', + 3: 'GL1_CACHE_POLICY_HIT_EVICT', +} +GL1_CACHE_POLICY_MISS_LRU = 0 +GL1_CACHE_POLICY_MISS_EVICT = 1 +GL1_CACHE_POLICY_HIT_LRU = 2 +GL1_CACHE_POLICY_HIT_EVICT = 3 +GL1_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL1_CACHE_STORE_POLICIES' +GL1_CACHE_STORE_POLICIES__enumvalues = { + 0: 'GL1_CACHE_STORE_POLICY_BYPASS', +} +GL1_CACHE_STORE_POLICY_BYPASS = 0 +GL1_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_CACHE_POLICIES' +TCC_CACHE_POLICIES__enumvalues = { + 0: 'TCC_CACHE_POLICY_LRU', + 1: 'TCC_CACHE_POLICY_STREAM', +} +TCC_CACHE_POLICY_LRU = 0 +TCC_CACHE_POLICY_STREAM = 1 +TCC_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_MTYPE' +TCC_MTYPE__enumvalues = { + 0: 'MTYPE_NC', + 1: 'MTYPE_WC', + 2: 'MTYPE_CC', +} +MTYPE_NC = 0 +MTYPE_WC = 1 +MTYPE_CC = 2 +TCC_MTYPE = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_CACHE_POLICIES' +GL2_CACHE_POLICIES__enumvalues = { + 0: 'GL2_CACHE_POLICY_LRU', + 1: 'GL2_CACHE_POLICY_STREAM', + 2: 'GL2_CACHE_POLICY_NOA', + 3: 'GL2_CACHE_POLICY_BYPASS', +} +GL2_CACHE_POLICY_LRU = 0 +GL2_CACHE_POLICY_STREAM = 1 +GL2_CACHE_POLICY_NOA = 2 +GL2_CACHE_POLICY_BYPASS = 3 +GL2_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'MTYPE' +MTYPE__enumvalues = { + 0: 'MTYPE_C_RW_US', + 1: 'MTYPE_RESERVED_1', + 2: 'MTYPE_C_RO_S', + 3: 'MTYPE_UC', + 4: 'MTYPE_C_RW_S', + 5: 'MTYPE_RESERVED_5', + 6: 'MTYPE_C_RO_US', + 7: 'MTYPE_RESERVED_7', +} +MTYPE_C_RW_US = 0 +MTYPE_RESERVED_1 = 1 +MTYPE_C_RO_S = 2 +MTYPE_UC = 3 +MTYPE_C_RW_S = 4 +MTYPE_RESERVED_5 = 5 +MTYPE_C_RO_US = 6 +MTYPE_RESERVED_7 = 7 +MTYPE = ctypes.c_uint32 # enum + +# values for enumeration 'RMI_CID' +RMI_CID__enumvalues = { + 0: 'RMI_CID_CC', + 1: 'RMI_CID_FC', + 2: 'RMI_CID_CM', + 3: 'RMI_CID_DC', + 4: 'RMI_CID_Z', + 5: 'RMI_CID_S', + 6: 'RMI_CID_TILE', + 7: 'RMI_CID_ZPCPSD', +} +RMI_CID_CC = 0 +RMI_CID_FC = 1 +RMI_CID_CM = 2 +RMI_CID_DC = 3 +RMI_CID_Z = 4 +RMI_CID_S = 5 +RMI_CID_TILE = 6 +RMI_CID_ZPCPSD = 7 +RMI_CID = ctypes.c_uint32 # enum + +# values for enumeration 'WritePolicy' +WritePolicy__enumvalues = { + 0: 'CACHE_LRU_WR', + 1: 'CACHE_STREAM', + 2: 'CACHE_BYPASS', + 3: 'UNCACHED_WR', +} +CACHE_LRU_WR = 0 +CACHE_STREAM = 1 +CACHE_BYPASS = 2 +UNCACHED_WR = 3 +WritePolicy = ctypes.c_uint32 # enum + +# values for enumeration 'ReadPolicy' +ReadPolicy__enumvalues = { + 0: 'CACHE_LRU_RD', + 1: 'CACHE_NOA', + 2: 'UNCACHED_RD', + 3: 'RESERVED_RDPOLICY', +} +CACHE_LRU_RD = 0 +CACHE_NOA = 1 +UNCACHED_RD = 2 +RESERVED_RDPOLICY = 3 +ReadPolicy = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_COUNTER_MODE' +PERFMON_COUNTER_MODE__enumvalues = { + 0: 'PERFMON_COUNTER_MODE_ACCUM', + 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 2: 'PERFMON_COUNTER_MODE_MAX', + 3: 'PERFMON_COUNTER_MODE_DIRTY', + 4: 'PERFMON_COUNTER_MODE_SAMPLE', + 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 15: 'PERFMON_COUNTER_MODE_RESERVED', +} +PERFMON_COUNTER_MODE_ACCUM = 0 +PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 +PERFMON_COUNTER_MODE_MAX = 2 +PERFMON_COUNTER_MODE_DIRTY = 3 +PERFMON_COUNTER_MODE_SAMPLE = 4 +PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 +PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 +PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 +PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 +PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 +PERFMON_COUNTER_MODE_RESERVED = 15 +PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_SPM_MODE' +PERFMON_SPM_MODE__enumvalues = { + 0: 'PERFMON_SPM_MODE_OFF', + 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', + 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', + 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 5: 'PERFMON_SPM_MODE_RESERVED_5', + 6: 'PERFMON_SPM_MODE_RESERVED_6', + 7: 'PERFMON_SPM_MODE_RESERVED_7', + 8: 'PERFMON_SPM_MODE_TEST_MODE_0', + 9: 'PERFMON_SPM_MODE_TEST_MODE_1', + 10: 'PERFMON_SPM_MODE_TEST_MODE_2', +} +PERFMON_SPM_MODE_OFF = 0 +PERFMON_SPM_MODE_16BIT_CLAMP = 1 +PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 +PERFMON_SPM_MODE_32BIT_CLAMP = 3 +PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 +PERFMON_SPM_MODE_RESERVED_5 = 5 +PERFMON_SPM_MODE_RESERVED_6 = 6 +PERFMON_SPM_MODE_RESERVED_7 = 7 +PERFMON_SPM_MODE_TEST_MODE_0 = 8 +PERFMON_SPM_MODE_TEST_MODE_1 = 9 +PERFMON_SPM_MODE_TEST_MODE_2 = 10 +PERFMON_SPM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceTiling' +SurfaceTiling__enumvalues = { + 0: 'ARRAY_LINEAR', + 1: 'ARRAY_TILED', +} +ARRAY_LINEAR = 0 +ARRAY_TILED = 1 +SurfaceTiling = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceArray' +SurfaceArray__enumvalues = { + 0: 'ARRAY_1D', + 1: 'ARRAY_2D', + 2: 'ARRAY_3D', + 3: 'ARRAY_3D_SLICE', +} +ARRAY_1D = 0 +ARRAY_2D = 1 +ARRAY_3D = 2 +ARRAY_3D_SLICE = 3 +SurfaceArray = ctypes.c_uint32 # enum + +# values for enumeration 'ColorArray' +ColorArray__enumvalues = { + 0: 'ARRAY_2D_ALT_COLOR', + 1: 'ARRAY_2D_COLOR', + 3: 'ARRAY_3D_SLICE_COLOR', +} +ARRAY_2D_ALT_COLOR = 0 +ARRAY_2D_COLOR = 1 +ARRAY_3D_SLICE_COLOR = 3 +ColorArray = ctypes.c_uint32 # enum + +# values for enumeration 'DepthArray' +DepthArray__enumvalues = { + 0: 'ARRAY_2D_ALT_DEPTH', + 1: 'ARRAY_2D_DEPTH', +} +ARRAY_2D_ALT_DEPTH = 0 +ARRAY_2D_DEPTH = 1 +DepthArray = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_NUM_SIMD_PER_CU' +ENUM_NUM_SIMD_PER_CU__enumvalues = { + 2: 'NUM_SIMD_PER_CU', +} +NUM_SIMD_PER_CU = 2 +ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_ENABLE_ERROR_INJECT' +DSM_ENABLE_ERROR_INJECT__enumvalues = { + 0: 'DSM_ENABLE_ERROR_INJECT_FED_IN', + 1: 'DSM_ENABLE_ERROR_INJECT_SINGLE', + 2: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', + 3: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', +} +DSM_ENABLE_ERROR_INJECT_FED_IN = 0 +DSM_ENABLE_ERROR_INJECT_SINGLE = 1 +DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 2 +DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 3 +DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_SELECT_INJECT_DELAY' +DSM_SELECT_INJECT_DELAY__enumvalues = { + 0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY', + 1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', +} +DSM_SELECT_INJECT_DELAY_NO_DELAY = 0 +DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1 +DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_DATA_SEL' +DSM_DATA_SEL__enumvalues = { + 0: 'DSM_DATA_SEL_DISABLE', + 1: 'DSM_DATA_SEL_0', + 2: 'DSM_DATA_SEL_1', + 3: 'DSM_DATA_SEL_BOTH', +} +DSM_DATA_SEL_DISABLE = 0 +DSM_DATA_SEL_0 = 1 +DSM_DATA_SEL_1 = 2 +DSM_DATA_SEL_BOTH = 3 +DSM_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_SINGLE_WRITE' +DSM_SINGLE_WRITE__enumvalues = { + 0: 'DSM_SINGLE_WRITE_DIS', + 1: 'DSM_SINGLE_WRITE_EN', +} +DSM_SINGLE_WRITE_DIS = 0 +DSM_SINGLE_WRITE_EN = 1 +DSM_SINGLE_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'Hdp_SurfaceEndian' +Hdp_SurfaceEndian__enumvalues = { + 0: 'HDP_ENDIAN_NONE', + 1: 'HDP_ENDIAN_8IN16', + 2: 'HDP_ENDIAN_8IN32', + 3: 'HDP_ENDIAN_8IN64', +} +HDP_ENDIAN_NONE = 0 +HDP_ENDIAN_8IN16 = 1 +HDP_ENDIAN_8IN32 = 2 +HDP_ENDIAN_8IN64 = 3 +Hdp_SurfaceEndian = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_ENABLE' +CNVC_ENABLE__enumvalues = { + 0: 'CNVC_DIS', + 1: 'CNVC_EN', +} +CNVC_DIS = 0 +CNVC_EN = 1 +CNVC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_BYPASS' +CNVC_BYPASS__enumvalues = { + 0: 'CNVC_BYPASS_DISABLE', + 1: 'CNVC_BYPASS_EN', +} +CNVC_BYPASS_DISABLE = 0 +CNVC_BYPASS_EN = 1 +CNVC_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_PENDING' +CNVC_PENDING__enumvalues = { + 0: 'CNVC_NOT_PENDING', + 1: 'CNVC_YES_PENDING', +} +CNVC_NOT_PENDING = 0 +CNVC_YES_PENDING = 1 +CNVC_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'DENORM_TRUNCATE' +DENORM_TRUNCATE__enumvalues = { + 0: 'CNVC_ROUND', + 1: 'CNVC_TRUNCATE', +} +CNVC_ROUND = 0 +CNVC_TRUNCATE = 1 +DENORM_TRUNCATE = ctypes.c_uint32 # enum + +# values for enumeration 'PIX_EXPAND_MODE' +PIX_EXPAND_MODE__enumvalues = { + 0: 'PIX_DYNAMIC_EXPANSION', + 1: 'PIX_ZERO_EXPANSION', +} +PIX_DYNAMIC_EXPANSION = 0 +PIX_ZERO_EXPANSION = 1 +PIX_EXPAND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_PIXEL_FORMAT' +SURFACE_PIXEL_FORMAT__enumvalues = { + 1: 'ARGB1555', + 2: 'RGBA5551', + 3: 'RGB565', + 4: 'BGR565', + 5: 'ARGB4444', + 6: 'RGBA4444', + 8: 'ARGB8888', + 9: 'RGBA8888', + 10: 'ARGB2101010', + 11: 'RGBA1010102', + 12: 'AYCrCb8888', + 13: 'YCrCbA8888', + 14: 'ACrYCb8888', + 15: 'CrYCbA8888', + 16: 'ARGB16161616_10MSB', + 17: 'RGBA16161616_10MSB', + 18: 'ARGB16161616_10LSB', + 19: 'RGBA16161616_10LSB', + 20: 'ARGB16161616_12MSB', + 21: 'RGBA16161616_12MSB', + 22: 'ARGB16161616_12LSB', + 23: 'RGBA16161616_12LSB', + 24: 'ARGB16161616_FLOAT', + 25: 'RGBA16161616_FLOAT', + 26: 'ARGB16161616_UNORM', + 27: 'RGBA16161616_UNORM', + 28: 'ARGB16161616_SNORM', + 29: 'RGBA16161616_SNORM', + 32: 'AYCrCb16161616_10MSB', + 33: 'AYCrCb16161616_10LSB', + 34: 'YCrCbA16161616_10MSB', + 35: 'YCrCbA16161616_10LSB', + 36: 'ACrYCb16161616_10MSB', + 37: 'ACrYCb16161616_10LSB', + 38: 'CrYCbA16161616_10MSB', + 39: 'CrYCbA16161616_10LSB', + 40: 'AYCrCb16161616_12MSB', + 41: 'AYCrCb16161616_12LSB', + 42: 'YCrCbA16161616_12MSB', + 43: 'YCrCbA16161616_12LSB', + 44: 'ACrYCb16161616_12MSB', + 45: 'ACrYCb16161616_12LSB', + 46: 'CrYCbA16161616_12MSB', + 47: 'CrYCbA16161616_12LSB', + 64: 'Y8_CrCb88_420_PLANAR', + 65: 'Y8_CbCr88_420_PLANAR', + 66: 'Y10_CrCb1010_420_PLANAR', + 67: 'Y10_CbCr1010_420_PLANAR', + 68: 'Y12_CrCb1212_420_PLANAR', + 69: 'Y12_CbCr1212_420_PLANAR', + 72: 'YCrYCb8888_422_PACKED', + 73: 'YCbYCr8888_422_PACKED', + 74: 'CrYCbY8888_422_PACKED', + 75: 'CbYCrY8888_422_PACKED', + 76: 'YCrYCb10101010_422_PACKED', + 77: 'YCbYCr10101010_422_PACKED', + 78: 'CrYCbY10101010_422_PACKED', + 79: 'CbYCrY10101010_422_PACKED', + 80: 'YCrYCb12121212_422_PACKED', + 81: 'YCbYCr12121212_422_PACKED', + 82: 'CrYCbY12121212_422_PACKED', + 83: 'CbYCrY12121212_422_PACKED', + 112: 'RGB111110_FIX', + 113: 'BGR101111_FIX', + 114: 'ACrYCb2101010', + 115: 'CrYCbA1010102', + 118: 'RGB111110_FLOAT', + 119: 'BGR101111_FLOAT', + 120: 'MONO_8', + 121: 'MONO_10MSB', + 122: 'MONO_10LSB', + 123: 'MONO_12MSB', + 124: 'MONO_12LSB', + 125: 'MONO_16', +} +ARGB1555 = 1 +RGBA5551 = 2 +RGB565 = 3 +BGR565 = 4 +ARGB4444 = 5 +RGBA4444 = 6 +ARGB8888 = 8 +RGBA8888 = 9 +ARGB2101010 = 10 +RGBA1010102 = 11 +AYCrCb8888 = 12 +YCrCbA8888 = 13 +ACrYCb8888 = 14 +CrYCbA8888 = 15 +ARGB16161616_10MSB = 16 +RGBA16161616_10MSB = 17 +ARGB16161616_10LSB = 18 +RGBA16161616_10LSB = 19 +ARGB16161616_12MSB = 20 +RGBA16161616_12MSB = 21 +ARGB16161616_12LSB = 22 +RGBA16161616_12LSB = 23 +ARGB16161616_FLOAT = 24 +RGBA16161616_FLOAT = 25 +ARGB16161616_UNORM = 26 +RGBA16161616_UNORM = 27 +ARGB16161616_SNORM = 28 +RGBA16161616_SNORM = 29 +AYCrCb16161616_10MSB = 32 +AYCrCb16161616_10LSB = 33 +YCrCbA16161616_10MSB = 34 +YCrCbA16161616_10LSB = 35 +ACrYCb16161616_10MSB = 36 +ACrYCb16161616_10LSB = 37 +CrYCbA16161616_10MSB = 38 +CrYCbA16161616_10LSB = 39 +AYCrCb16161616_12MSB = 40 +AYCrCb16161616_12LSB = 41 +YCrCbA16161616_12MSB = 42 +YCrCbA16161616_12LSB = 43 +ACrYCb16161616_12MSB = 44 +ACrYCb16161616_12LSB = 45 +CrYCbA16161616_12MSB = 46 +CrYCbA16161616_12LSB = 47 +Y8_CrCb88_420_PLANAR = 64 +Y8_CbCr88_420_PLANAR = 65 +Y10_CrCb1010_420_PLANAR = 66 +Y10_CbCr1010_420_PLANAR = 67 +Y12_CrCb1212_420_PLANAR = 68 +Y12_CbCr1212_420_PLANAR = 69 +YCrYCb8888_422_PACKED = 72 +YCbYCr8888_422_PACKED = 73 +CrYCbY8888_422_PACKED = 74 +CbYCrY8888_422_PACKED = 75 +YCrYCb10101010_422_PACKED = 76 +YCbYCr10101010_422_PACKED = 77 +CrYCbY10101010_422_PACKED = 78 +CbYCrY10101010_422_PACKED = 79 +YCrYCb12121212_422_PACKED = 80 +YCbYCr12121212_422_PACKED = 81 +CrYCbY12121212_422_PACKED = 82 +CbYCrY12121212_422_PACKED = 83 +RGB111110_FIX = 112 +BGR101111_FIX = 113 +ACrYCb2101010 = 114 +CrYCbA1010102 = 115 +RGB111110_FLOAT = 118 +BGR101111_FLOAT = 119 +MONO_8 = 120 +MONO_10MSB = 121 +MONO_10LSB = 122 +MONO_12MSB = 123 +MONO_12LSB = 124 +MONO_16 = 125 +SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'XNORM' +XNORM__enumvalues = { + 0: 'XNORM_A', + 1: 'XNORM_B', +} +XNORM_A = 0 +XNORM_B = 1 +XNORM = ctypes.c_uint32 # enum + +# values for enumeration 'COLOR_KEYER_MODE' +COLOR_KEYER_MODE__enumvalues = { + 0: 'FORCE_00', + 1: 'FORCE_FF', + 2: 'RANGE_00', + 3: 'RANGE_FF', +} +FORCE_00 = 0 +FORCE_FF = 1 +RANGE_00 = 2 +RANGE_FF = 3 +COLOR_KEYER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_ENABLE' +CUR_ENABLE__enumvalues = { + 0: 'CUR_DIS', + 1: 'CUR_EN', +} +CUR_DIS = 0 +CUR_EN = 1 +CUR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_PENDING' +CUR_PENDING__enumvalues = { + 0: 'CUR_NOT_PENDING', + 1: 'CUR_YES_PENDING', +} +CUR_NOT_PENDING = 0 +CUR_YES_PENDING = 1 +CUR_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_EXPAND_MODE' +CUR_EXPAND_MODE__enumvalues = { + 0: 'CUR_DYNAMIC_EXPANSION', + 1: 'CUR_ZERO_EXPANSION', +} +CUR_DYNAMIC_EXPANSION = 0 +CUR_ZERO_EXPANSION = 1 +CUR_EXPAND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_ROM_EN' +CUR_ROM_EN__enumvalues = { + 0: 'CUR_FP_NO_ROM', + 1: 'CUR_FP_USE_ROM', +} +CUR_FP_NO_ROM = 0 +CUR_FP_USE_ROM = 1 +CUR_ROM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_MODE' +CUR_MODE__enumvalues = { + 0: 'MONO_2BIT', + 1: 'COLOR_24BIT_1BIT_AND', + 2: 'COLOR_24BIT_8BIT_ALPHA_PREMULT', + 3: 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 4: 'COLOR_64BIT_FP_PREMULT', + 5: 'COLOR_64BIT_FP_UNPREMULT', +} +MONO_2BIT = 0 +COLOR_24BIT_1BIT_AND = 1 +COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 +COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 +COLOR_64BIT_FP_PREMULT = 4 +COLOR_64BIT_FP_UNPREMULT = 5 +CUR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_INV_CLAMP' +CUR_INV_CLAMP__enumvalues = { + 0: 'CUR_CLAMP_DIS', + 1: 'CUR_CLAMP_EN', +} +CUR_CLAMP_DIS = 0 +CUR_CLAMP_EN = 1 +CUR_INV_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_COEF_FILTER_TYPE_SEL' +SCL_COEF_FILTER_TYPE_SEL__enumvalues = { + 0: 'SCL_COEF_LUMA_VERT_FILTER', + 1: 'SCL_COEF_LUMA_HORZ_FILTER', + 2: 'SCL_COEF_CHROMA_VERT_FILTER', + 3: 'SCL_COEF_CHROMA_HORZ_FILTER', + 4: 'SCL_COEF_ALPHA_VERT_FILTER', + 5: 'SCL_COEF_ALPHA_HORZ_FILTER', +} +SCL_COEF_LUMA_VERT_FILTER = 0 +SCL_COEF_LUMA_HORZ_FILTER = 1 +SCL_COEF_CHROMA_VERT_FILTER = 2 +SCL_COEF_CHROMA_HORZ_FILTER = 3 +SCL_COEF_ALPHA_VERT_FILTER = 4 +SCL_COEF_ALPHA_HORZ_FILTER = 5 +SCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSCL_MODE_SEL' +DSCL_MODE_SEL__enumvalues = { + 0: 'DSCL_MODE_SCALING_444_BYPASS', + 1: 'DSCL_MODE_SCALING_444_RGB_ENABLE', + 2: 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', + 3: 'DSCL_MODE_SCALING_YCBCR_ENABLE', + 4: 'DSCL_MODE_LUMA_SCALING_BYPASS', + 5: 'DSCL_MODE_CHROMA_SCALING_BYPASS', + 6: 'DSCL_MODE_DSCL_BYPASS', +} +DSCL_MODE_SCALING_444_BYPASS = 0 +DSCL_MODE_SCALING_444_RGB_ENABLE = 1 +DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2 +DSCL_MODE_SCALING_YCBCR_ENABLE = 3 +DSCL_MODE_LUMA_SCALING_BYPASS = 4 +DSCL_MODE_CHROMA_SCALING_BYPASS = 5 +DSCL_MODE_DSCL_BYPASS = 6 +DSCL_MODE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_AUTOCAL_MODE' +SCL_AUTOCAL_MODE__enumvalues = { + 0: 'AUTOCAL_MODE_OFF', + 1: 'AUTOCAL_MODE_AUTOSCALE', + 2: 'AUTOCAL_MODE_AUTOCENTER', + 3: 'AUTOCAL_MODE_AUTOREPLICATE', +} +AUTOCAL_MODE_OFF = 0 +AUTOCAL_MODE_AUTOSCALE = 1 +AUTOCAL_MODE_AUTOCENTER = 2 +AUTOCAL_MODE_AUTOREPLICATE = 3 +SCL_AUTOCAL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_COEF_RAM_SEL' +SCL_COEF_RAM_SEL__enumvalues = { + 0: 'SCL_COEF_RAM_SEL_0', + 1: 'SCL_COEF_RAM_SEL_1', +} +SCL_COEF_RAM_SEL_0 = 0 +SCL_COEF_RAM_SEL_1 = 1 +SCL_COEF_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_CHROMA_COEF' +SCL_CHROMA_COEF__enumvalues = { + 0: 'SCL_CHROMA_COEF_LUMA', + 1: 'SCL_CHROMA_COEF_CHROMA', +} +SCL_CHROMA_COEF_LUMA = 0 +SCL_CHROMA_COEF_CHROMA = 1 +SCL_CHROMA_COEF = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_ALPHA_COEF' +SCL_ALPHA_COEF__enumvalues = { + 0: 'SCL_ALPHA_COEF_LUMA', + 1: 'SCL_ALPHA_COEF_ALPHA', +} +SCL_ALPHA_COEF_LUMA = 0 +SCL_ALPHA_COEF_ALPHA = 1 +SCL_ALPHA_COEF = ctypes.c_uint32 # enum + +# values for enumeration 'COEF_RAM_SELECT_RD' +COEF_RAM_SELECT_RD__enumvalues = { + 0: 'COEF_RAM_SELECT_BACK', + 1: 'COEF_RAM_SELECT_CURRENT', +} +COEF_RAM_SELECT_BACK = 0 +COEF_RAM_SELECT_CURRENT = 1 +COEF_RAM_SELECT_RD = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_2TAP_HARDCODE' +SCL_2TAP_HARDCODE__enumvalues = { + 0: 'SCL_COEF_2TAP_HARDCODE_OFF', + 1: 'SCL_COEF_2TAP_HARDCODE_ON', +} +SCL_COEF_2TAP_HARDCODE_OFF = 0 +SCL_COEF_2TAP_HARDCODE_ON = 1 +SCL_2TAP_HARDCODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_SHARP_EN' +SCL_SHARP_EN__enumvalues = { + 0: 'SCL_SHARP_DISABLE', + 1: 'SCL_SHARP_ENABLE', +} +SCL_SHARP_DISABLE = 0 +SCL_SHARP_ENABLE = 1 +SCL_SHARP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_BOUNDARY' +SCL_BOUNDARY__enumvalues = { + 0: 'SCL_BOUNDARY_EDGE', + 1: 'SCL_BOUNDARY_BLACK', +} +SCL_BOUNDARY_EDGE = 0 +SCL_BOUNDARY_BLACK = 1 +SCL_BOUNDARY = ctypes.c_uint32 # enum + +# values for enumeration 'LB_INTERLEAVE_EN' +LB_INTERLEAVE_EN__enumvalues = { + 0: 'LB_INTERLEAVE_DISABLE', + 1: 'LB_INTERLEAVE_ENABLE', +} +LB_INTERLEAVE_DISABLE = 0 +LB_INTERLEAVE_ENABLE = 1 +LB_INTERLEAVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_ALPHA_EN' +LB_ALPHA_EN__enumvalues = { + 0: 'LB_ALPHA_DISABLE', + 1: 'LB_ALPHA_ENABLE', +} +LB_ALPHA_DISABLE = 0 +LB_ALPHA_ENABLE = 1 +LB_ALPHA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_BYPASS_SEL' +OBUF_BYPASS_SEL__enumvalues = { + 0: 'OBUF_BYPASS_DIS', + 1: 'OBUF_BYPASS_EN', +} +OBUF_BYPASS_DIS = 0 +OBUF_BYPASS_EN = 1 +OBUF_BYPASS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_USE_FULL_BUFFER_SEL' +OBUF_USE_FULL_BUFFER_SEL__enumvalues = { + 0: 'OBUF_RECOUT', + 1: 'OBUF_FULL', +} +OBUF_RECOUT = 0 +OBUF_FULL = 1 +OBUF_USE_FULL_BUFFER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_IS_HALF_RECOUT_WIDTH_SEL' +OBUF_IS_HALF_RECOUT_WIDTH_SEL__enumvalues = { + 0: 'OBUF_FULL_RECOUT', + 1: 'OBUF_HALF_RECOUT', +} +OBUF_FULL_RECOUT = 0 +OBUF_HALF_RECOUT = 1 +OBUF_IS_HALF_RECOUT_WIDTH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_BYPASS' +CM_BYPASS__enumvalues = { + 0: 'NON_BYPASS', + 1: 'BYPASS_EN', +} +NON_BYPASS = 0 +BYPASS_EN = 1 +CM_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'CM_EN' +CM_EN__enumvalues = { + 0: 'CM_DISABLE', + 1: 'CM_ENABLE', +} +CM_DISABLE = 0 +CM_ENABLE = 1 +CM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CM_PENDING' +CM_PENDING__enumvalues = { + 0: 'CM_NOT_PENDING', + 1: 'CM_YES_PENDING', +} +CM_NOT_PENDING = 0 +CM_YES_PENDING = 1 +CM_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'CM_DATA_SIGNED' +CM_DATA_SIGNED__enumvalues = { + 0: 'UNSIGNED', + 1: 'SIGNED', +} +UNSIGNED = 0 +SIGNED = 1 +CM_DATA_SIGNED = ctypes.c_uint32 # enum + +# values for enumeration 'CM_WRITE_BASE_ONLY' +CM_WRITE_BASE_ONLY__enumvalues = { + 0: 'WRITE_BOTH', + 1: 'WRITE_BASE_ONLY', +} +WRITE_BOTH = 0 +WRITE_BASE_ONLY = 1 +CM_WRITE_BASE_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_4_CONFIG_ENUM' +CM_LUT_4_CONFIG_ENUM__enumvalues = { + 0: 'LUT_4CFG_NO_MEMORY', + 1: 'LUT_4CFG_ROM_A', + 2: 'LUT_4CFG_ROM_B', + 3: 'LUT_4CFG_MEMORY_A', + 4: 'LUT_4CFG_MEMORY_B', +} +LUT_4CFG_NO_MEMORY = 0 +LUT_4CFG_ROM_A = 1 +LUT_4CFG_ROM_B = 2 +LUT_4CFG_MEMORY_A = 3 +LUT_4CFG_MEMORY_B = 4 +CM_LUT_4_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_2_CONFIG_ENUM' +CM_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'LUT_2CFG_NO_MEMORY', + 1: 'LUT_2CFG_MEMORY_A', + 2: 'LUT_2CFG_MEMORY_B', +} +LUT_2CFG_NO_MEMORY = 0 +LUT_2CFG_MEMORY_A = 1 +LUT_2CFG_MEMORY_B = 2 +CM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_4_MODE_ENUM' +CM_LUT_4_MODE_ENUM__enumvalues = { + 0: 'LUT_4_MODE_BYPASS', + 1: 'LUT_4_MODE_ROMA_LUT', + 2: 'LUT_4_MODE_ROMB_LUT', + 3: 'LUT_4_MODE_RAMA_LUT', + 4: 'LUT_4_MODE_RAMB_LUT', +} +LUT_4_MODE_BYPASS = 0 +LUT_4_MODE_ROMA_LUT = 1 +LUT_4_MODE_ROMB_LUT = 2 +LUT_4_MODE_RAMA_LUT = 3 +LUT_4_MODE_RAMB_LUT = 4 +CM_LUT_4_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_2_MODE_ENUM' +CM_LUT_2_MODE_ENUM__enumvalues = { + 0: 'LUT_2_MODE_BYPASS', + 1: 'LUT_2_MODE_RAMA_LUT', + 2: 'LUT_2_MODE_RAMB_LUT', +} +LUT_2_MODE_BYPASS = 0 +LUT_2_MODE_RAMA_LUT = 1 +LUT_2_MODE_RAMB_LUT = 2 +CM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_RAM_SEL' +CM_LUT_RAM_SEL__enumvalues = { + 0: 'RAMA_ACCESS', + 1: 'RAMB_ACCESS', +} +RAMA_ACCESS = 0 +RAMB_ACCESS = 1 +CM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_NUM_SEG' +CM_LUT_NUM_SEG__enumvalues = { + 0: 'SEGMENTS_1', + 1: 'SEGMENTS_2', + 2: 'SEGMENTS_4', + 3: 'SEGMENTS_8', + 4: 'SEGMENTS_16', + 5: 'SEGMENTS_32', + 6: 'SEGMENTS_64', + 7: 'SEGMENTS_128', +} +SEGMENTS_1 = 0 +SEGMENTS_2 = 1 +SEGMENTS_4 = 2 +SEGMENTS_8 = 3 +SEGMENTS_16 = 4 +SEGMENTS_32 = 5 +SEGMENTS_64 = 6 +SEGMENTS_128 = 7 +CM_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'CM_ICSC_MODE_ENUM' +CM_ICSC_MODE_ENUM__enumvalues = { + 0: 'BYPASS_ICSC', + 1: 'COEF_ICSC', + 2: 'COEF_ICSC_B', +} +BYPASS_ICSC = 0 +COEF_ICSC = 1 +COEF_ICSC_B = 2 +CM_ICSC_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMUT_REMAP_MODE_ENUM' +CM_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'BYPASS_GAMUT', + 1: 'GAMUT_COEF', + 2: 'GAMUT_COEF_B', +} +BYPASS_GAMUT = 0 +GAMUT_COEF = 1 +GAMUT_COEF_B = 2 +CM_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_COEF_FORMAT_ENUM' +CM_COEF_FORMAT_ENUM__enumvalues = { + 0: 'FIX_S2_13', + 1: 'FIX_S3_12', +} +FIX_S2_13 = 0 +FIX_S3_12 = 1 +CM_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_2_CONFIG_ENUM' +CMC_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'CMC_LUT_2CFG_NO_MEMORY', + 1: 'CMC_LUT_2CFG_MEMORY_A', + 2: 'CMC_LUT_2CFG_MEMORY_B', +} +CMC_LUT_2CFG_NO_MEMORY = 0 +CMC_LUT_2CFG_MEMORY_A = 1 +CMC_LUT_2CFG_MEMORY_B = 2 +CMC_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_2_MODE_ENUM' +CMC_LUT_2_MODE_ENUM__enumvalues = { + 0: 'CMC_LUT_2_MODE_BYPASS', + 1: 'CMC_LUT_2_MODE_RAMA_LUT', + 2: 'CMC_LUT_2_MODE_RAMB_LUT', +} +CMC_LUT_2_MODE_BYPASS = 0 +CMC_LUT_2_MODE_RAMA_LUT = 1 +CMC_LUT_2_MODE_RAMB_LUT = 2 +CMC_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_RAM_SEL' +CMC_LUT_RAM_SEL__enumvalues = { + 0: 'CMC_RAMA_ACCESS', + 1: 'CMC_RAMB_ACCESS', +} +CMC_RAMA_ACCESS = 0 +CMC_RAMB_ACCESS = 1 +CMC_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_RAM_SEL' +CMC_3DLUT_RAM_SEL__enumvalues = { + 0: 'CMC_RAM0_ACCESS', + 1: 'CMC_RAM1_ACCESS', + 2: 'CMC_RAM2_ACCESS', + 3: 'CMC_RAM3_ACCESS', +} +CMC_RAM0_ACCESS = 0 +CMC_RAM1_ACCESS = 1 +CMC_RAM2_ACCESS = 2 +CMC_RAM3_ACCESS = 3 +CMC_3DLUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_NUM_SEG' +CMC_LUT_NUM_SEG__enumvalues = { + 0: 'CMC_SEGMENTS_1', + 1: 'CMC_SEGMENTS_2', + 2: 'CMC_SEGMENTS_4', + 3: 'CMC_SEGMENTS_8', + 4: 'CMC_SEGMENTS_16', + 5: 'CMC_SEGMENTS_32', + 6: 'CMC_SEGMENTS_64', + 7: 'CMC_SEGMENTS_128', +} +CMC_SEGMENTS_1 = 0 +CMC_SEGMENTS_2 = 1 +CMC_SEGMENTS_4 = 2 +CMC_SEGMENTS_8 = 3 +CMC_SEGMENTS_16 = 4 +CMC_SEGMENTS_32 = 5 +CMC_SEGMENTS_64 = 6 +CMC_SEGMENTS_128 = 7 +CMC_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_30BIT_ENUM' +CMC_3DLUT_30BIT_ENUM__enumvalues = { + 0: 'CMC_3DLUT_36BIT', + 1: 'CMC_3DLUT_30BIT', +} +CMC_3DLUT_36BIT = 0 +CMC_3DLUT_30BIT = 1 +CMC_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_SIZE_ENUM' +CMC_3DLUT_SIZE_ENUM__enumvalues = { + 0: 'CMC_3DLUT_17CUBE', + 1: 'CMC_3DLUT_9CUBE', +} +CMC_3DLUT_17CUBE = 0 +CMC_3DLUT_9CUBE = 1 +CMC_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLK_SEL' +TEST_CLK_SEL__enumvalues = { + 0: 'TEST_CLK_SEL_0', + 1: 'TEST_CLK_SEL_1', + 2: 'TEST_CLK_SEL_2', + 3: 'TEST_CLK_SEL_3', + 4: 'TEST_CLK_SEL_4', + 5: 'TEST_CLK_SEL_5', + 6: 'TEST_CLK_SEL_6', + 7: 'TEST_CLK_SEL_7', + 8: 'TEST_CLK_SEL_8', +} +TEST_CLK_SEL_0 = 0 +TEST_CLK_SEL_1 = 1 +TEST_CLK_SEL_2 = 2 +TEST_CLK_SEL_3 = 3 +TEST_CLK_SEL_4 = 4 +TEST_CLK_SEL_5 = 5 +TEST_CLK_SEL_6 = 6 +TEST_CLK_SEL_7 = 7 +TEST_CLK_SEL_8 = 8 +TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_SRC_SEL' +CRC_SRC_SEL__enumvalues = { + 0: 'CRC_SRC_0', + 1: 'CRC_SRC_1', + 2: 'CRC_SRC_2', + 3: 'CRC_SRC_3', +} +CRC_SRC_0 = 0 +CRC_SRC_1 = 1 +CRC_SRC_2 = 2 +CRC_SRC_3 = 3 +CRC_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_IN_PIX_SEL' +CRC_IN_PIX_SEL__enumvalues = { + 0: 'CRC_IN_PIX_0', + 1: 'CRC_IN_PIX_1', + 2: 'CRC_IN_PIX_2', + 3: 'CRC_IN_PIX_3', + 4: 'CRC_IN_PIX_4', + 5: 'CRC_IN_PIX_5', + 6: 'CRC_IN_PIX_6', + 7: 'CRC_IN_PIX_7', +} +CRC_IN_PIX_0 = 0 +CRC_IN_PIX_1 = 1 +CRC_IN_PIX_2 = 2 +CRC_IN_PIX_3 = 3 +CRC_IN_PIX_4 = 4 +CRC_IN_PIX_5 = 5 +CRC_IN_PIX_6 = 6 +CRC_IN_PIX_7 = 7 +CRC_IN_PIX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_CUR_BITS_SEL' +CRC_CUR_BITS_SEL__enumvalues = { + 0: 'CRC_CUR_BITS_0', + 1: 'CRC_CUR_BITS_1', +} +CRC_CUR_BITS_0 = 0 +CRC_CUR_BITS_1 = 1 +CRC_CUR_BITS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_IN_CUR_SEL' +CRC_IN_CUR_SEL__enumvalues = { + 0: 'CRC_IN_CUR_0', + 1: 'CRC_IN_CUR_1', +} +CRC_IN_CUR_0 = 0 +CRC_IN_CUR_1 = 1 +CRC_IN_CUR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_CUR_SEL' +CRC_CUR_SEL__enumvalues = { + 0: 'CRC_CUR_0', + 1: 'CRC_CUR_1', +} +CRC_CUR_0 = 0 +CRC_CUR_1 = 1 +CRC_CUR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_STEREO_SEL' +CRC_STEREO_SEL__enumvalues = { + 0: 'CRC_STEREO_0', + 1: 'CRC_STEREO_1', + 2: 'CRC_STEREO_2', + 3: 'CRC_STEREO_3', +} +CRC_STEREO_0 = 0 +CRC_STEREO_1 = 1 +CRC_STEREO_2 = 2 +CRC_STEREO_3 = 3 +CRC_STEREO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_INTERLACE_SEL' +CRC_INTERLACE_SEL__enumvalues = { + 0: 'CRC_INTERLACE_0', + 1: 'CRC_INTERLACE_1', + 2: 'CRC_INTERLACE_2', + 3: 'CRC_INTERLACE_3', +} +CRC_INTERLACE_0 = 0 +CRC_INTERLACE_1 = 1 +CRC_INTERLACE_2 = 2 +CRC_INTERLACE_3 = 3 +CRC_INTERLACE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CVALUE_SEL' +PERFCOUNTER_CVALUE_SEL__enumvalues = { + 0: 'PERFCOUNTER_CVALUE_SEL_47_0', + 1: 'PERFCOUNTER_CVALUE_SEL_15_0', + 2: 'PERFCOUNTER_CVALUE_SEL_31_16', + 3: 'PERFCOUNTER_CVALUE_SEL_47_32', + 4: 'PERFCOUNTER_CVALUE_SEL_11_0', + 5: 'PERFCOUNTER_CVALUE_SEL_23_12', + 6: 'PERFCOUNTER_CVALUE_SEL_35_24', + 7: 'PERFCOUNTER_CVALUE_SEL_47_36', +} +PERFCOUNTER_CVALUE_SEL_47_0 = 0 +PERFCOUNTER_CVALUE_SEL_15_0 = 1 +PERFCOUNTER_CVALUE_SEL_31_16 = 2 +PERFCOUNTER_CVALUE_SEL_47_32 = 3 +PERFCOUNTER_CVALUE_SEL_11_0 = 4 +PERFCOUNTER_CVALUE_SEL_23_12 = 5 +PERFCOUNTER_CVALUE_SEL_35_24 = 6 +PERFCOUNTER_CVALUE_SEL_47_36 = 7 +PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INC_MODE' +PERFCOUNTER_INC_MODE__enumvalues = { + 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', + 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', + 2: 'PERFCOUNTER_INC_MODE_LSB', + 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', + 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', +} +PERFCOUNTER_INC_MODE_MULTI_BIT = 0 +PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 +PERFCOUNTER_INC_MODE_LSB = 2 +PERFCOUNTER_INC_MODE_POS_EDGE = 3 +PERFCOUNTER_INC_MODE_NEG_EDGE = 4 +PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' +PERFCOUNTER_HW_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', + 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', +} +PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 +PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 +PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RUNEN_MODE' +PERFCOUNTER_RUNEN_MODE__enumvalues = { + 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', +} +PERFCOUNTER_RUNEN_MODE_LEVEL = 0 +PERFCOUNTER_RUNEN_MODE_EDGE = 1 +PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' +PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { + 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', + 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', +} +PERFCOUNTER_CNTOFF_START_ENABLE = 0 +PERFCOUNTER_CNTOFF_START_DISABLE = 1 +PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RESTART_EN' +PERFCOUNTER_RESTART_EN__enumvalues = { + 0: 'PERFCOUNTER_RESTART_DISABLE', + 1: 'PERFCOUNTER_RESTART_ENABLE', +} +PERFCOUNTER_RESTART_DISABLE = 0 +PERFCOUNTER_RESTART_ENABLE = 1 +PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_EN' +PERFCOUNTER_INT_EN__enumvalues = { + 0: 'PERFCOUNTER_INT_DISABLE', + 1: 'PERFCOUNTER_INT_ENABLE', +} +PERFCOUNTER_INT_DISABLE = 0 +PERFCOUNTER_INT_ENABLE = 1 +PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_OFF_MASK' +PERFCOUNTER_OFF_MASK__enumvalues = { + 0: 'PERFCOUNTER_OFF_MASK_DISABLE', + 1: 'PERFCOUNTER_OFF_MASK_ENABLE', +} +PERFCOUNTER_OFF_MASK_DISABLE = 0 +PERFCOUNTER_OFF_MASK_ENABLE = 1 +PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_ACTIVE' +PERFCOUNTER_ACTIVE__enumvalues = { + 0: 'PERFCOUNTER_IS_IDLE', + 1: 'PERFCOUNTER_IS_ACTIVE', +} +PERFCOUNTER_IS_IDLE = 0 +PERFCOUNTER_IS_ACTIVE = 1 +PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_TYPE' +PERFCOUNTER_INT_TYPE__enumvalues = { + 0: 'PERFCOUNTER_INT_TYPE_LEVEL', + 1: 'PERFCOUNTER_INT_TYPE_PULSE', +} +PERFCOUNTER_INT_TYPE_LEVEL = 0 +PERFCOUNTER_INT_TYPE_PULSE = 1 +PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' +PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { + 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', +} +PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 +PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 +PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 +PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_STOP1_SEL' +PERFCOUNTER_HW_STOP1_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_STOP1_0', + 1: 'PERFCOUNTER_HW_STOP1_1', +} +PERFCOUNTER_HW_STOP1_0 = 0 +PERFCOUNTER_HW_STOP1_1 = 1 +PERFCOUNTER_HW_STOP1_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_STOP2_SEL' +PERFCOUNTER_HW_STOP2_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_STOP2_0', + 1: 'PERFCOUNTER_HW_STOP2_1', +} +PERFCOUNTER_HW_STOP2_0 = 0 +PERFCOUNTER_HW_STOP2_1 = 1 +PERFCOUNTER_HW_STOP2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTL_SEL' +PERFCOUNTER_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_CNTL_SEL_0', + 1: 'PERFCOUNTER_CNTL_SEL_1', + 2: 'PERFCOUNTER_CNTL_SEL_2', + 3: 'PERFCOUNTER_CNTL_SEL_3', + 4: 'PERFCOUNTER_CNTL_SEL_4', + 5: 'PERFCOUNTER_CNTL_SEL_5', + 6: 'PERFCOUNTER_CNTL_SEL_6', + 7: 'PERFCOUNTER_CNTL_SEL_7', +} +PERFCOUNTER_CNTL_SEL_0 = 0 +PERFCOUNTER_CNTL_SEL_1 = 1 +PERFCOUNTER_CNTL_SEL_2 = 2 +PERFCOUNTER_CNTL_SEL_3 = 3 +PERFCOUNTER_CNTL_SEL_4 = 4 +PERFCOUNTER_CNTL_SEL_5 = 5 +PERFCOUNTER_CNTL_SEL_6 = 6 +PERFCOUNTER_CNTL_SEL_7 = 7 +PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT0_STATE' +PERFCOUNTER_CNT0_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT0_STATE_RESET', + 1: 'PERFCOUNTER_CNT0_STATE_START', + 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT0_STATE_HW', +} +PERFCOUNTER_CNT0_STATE_RESET = 0 +PERFCOUNTER_CNT0_STATE_START = 1 +PERFCOUNTER_CNT0_STATE_FREEZE = 2 +PERFCOUNTER_CNT0_STATE_HW = 3 +PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL0' +PERFCOUNTER_STATE_SEL0__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', +} +PERFCOUNTER_STATE_SEL0_GLOBAL = 0 +PERFCOUNTER_STATE_SEL0_LOCAL = 1 +PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT1_STATE' +PERFCOUNTER_CNT1_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT1_STATE_RESET', + 1: 'PERFCOUNTER_CNT1_STATE_START', + 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT1_STATE_HW', +} +PERFCOUNTER_CNT1_STATE_RESET = 0 +PERFCOUNTER_CNT1_STATE_START = 1 +PERFCOUNTER_CNT1_STATE_FREEZE = 2 +PERFCOUNTER_CNT1_STATE_HW = 3 +PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL1' +PERFCOUNTER_STATE_SEL1__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', +} +PERFCOUNTER_STATE_SEL1_GLOBAL = 0 +PERFCOUNTER_STATE_SEL1_LOCAL = 1 +PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT2_STATE' +PERFCOUNTER_CNT2_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT2_STATE_RESET', + 1: 'PERFCOUNTER_CNT2_STATE_START', + 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT2_STATE_HW', +} +PERFCOUNTER_CNT2_STATE_RESET = 0 +PERFCOUNTER_CNT2_STATE_START = 1 +PERFCOUNTER_CNT2_STATE_FREEZE = 2 +PERFCOUNTER_CNT2_STATE_HW = 3 +PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL2' +PERFCOUNTER_STATE_SEL2__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', +} +PERFCOUNTER_STATE_SEL2_GLOBAL = 0 +PERFCOUNTER_STATE_SEL2_LOCAL = 1 +PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT3_STATE' +PERFCOUNTER_CNT3_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT3_STATE_RESET', + 1: 'PERFCOUNTER_CNT3_STATE_START', + 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT3_STATE_HW', +} +PERFCOUNTER_CNT3_STATE_RESET = 0 +PERFCOUNTER_CNT3_STATE_START = 1 +PERFCOUNTER_CNT3_STATE_FREEZE = 2 +PERFCOUNTER_CNT3_STATE_HW = 3 +PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL3' +PERFCOUNTER_STATE_SEL3__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', +} +PERFCOUNTER_STATE_SEL3_GLOBAL = 0 +PERFCOUNTER_STATE_SEL3_LOCAL = 1 +PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT4_STATE' +PERFCOUNTER_CNT4_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT4_STATE_RESET', + 1: 'PERFCOUNTER_CNT4_STATE_START', + 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT4_STATE_HW', +} +PERFCOUNTER_CNT4_STATE_RESET = 0 +PERFCOUNTER_CNT4_STATE_START = 1 +PERFCOUNTER_CNT4_STATE_FREEZE = 2 +PERFCOUNTER_CNT4_STATE_HW = 3 +PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL4' +PERFCOUNTER_STATE_SEL4__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', +} +PERFCOUNTER_STATE_SEL4_GLOBAL = 0 +PERFCOUNTER_STATE_SEL4_LOCAL = 1 +PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT5_STATE' +PERFCOUNTER_CNT5_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT5_STATE_RESET', + 1: 'PERFCOUNTER_CNT5_STATE_START', + 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT5_STATE_HW', +} +PERFCOUNTER_CNT5_STATE_RESET = 0 +PERFCOUNTER_CNT5_STATE_START = 1 +PERFCOUNTER_CNT5_STATE_FREEZE = 2 +PERFCOUNTER_CNT5_STATE_HW = 3 +PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL5' +PERFCOUNTER_STATE_SEL5__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', +} +PERFCOUNTER_STATE_SEL5_GLOBAL = 0 +PERFCOUNTER_STATE_SEL5_LOCAL = 1 +PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT6_STATE' +PERFCOUNTER_CNT6_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT6_STATE_RESET', + 1: 'PERFCOUNTER_CNT6_STATE_START', + 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT6_STATE_HW', +} +PERFCOUNTER_CNT6_STATE_RESET = 0 +PERFCOUNTER_CNT6_STATE_START = 1 +PERFCOUNTER_CNT6_STATE_FREEZE = 2 +PERFCOUNTER_CNT6_STATE_HW = 3 +PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL6' +PERFCOUNTER_STATE_SEL6__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', +} +PERFCOUNTER_STATE_SEL6_GLOBAL = 0 +PERFCOUNTER_STATE_SEL6_LOCAL = 1 +PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT7_STATE' +PERFCOUNTER_CNT7_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT7_STATE_RESET', + 1: 'PERFCOUNTER_CNT7_STATE_START', + 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT7_STATE_HW', +} +PERFCOUNTER_CNT7_STATE_RESET = 0 +PERFCOUNTER_CNT7_STATE_START = 1 +PERFCOUNTER_CNT7_STATE_FREEZE = 2 +PERFCOUNTER_CNT7_STATE_HW = 3 +PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL7' +PERFCOUNTER_STATE_SEL7__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', +} +PERFCOUNTER_STATE_SEL7_GLOBAL = 0 +PERFCOUNTER_STATE_SEL7_LOCAL = 1 +PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_STATE' +PERFMON_STATE__enumvalues = { + 0: 'PERFMON_STATE_RESET', + 1: 'PERFMON_STATE_START', + 2: 'PERFMON_STATE_FREEZE', + 3: 'PERFMON_STATE_HW', +} +PERFMON_STATE_RESET = 0 +PERFMON_STATE_START = 1 +PERFMON_STATE_FREEZE = 2 +PERFMON_STATE_HW = 3 +PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_AND_OR' +PERFMON_CNTOFF_AND_OR__enumvalues = { + 0: 'PERFMON_CNTOFF_OR', + 1: 'PERFMON_CNTOFF_AND', +} +PERFMON_CNTOFF_OR = 0 +PERFMON_CNTOFF_AND = 1 +PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_EN' +PERFMON_CNTOFF_INT_EN__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_DISABLE', + 1: 'PERFMON_CNTOFF_INT_ENABLE', +} +PERFMON_CNTOFF_INT_DISABLE = 0 +PERFMON_CNTOFF_INT_ENABLE = 1 +PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_TYPE' +PERFMON_CNTOFF_INT_TYPE__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', + 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', +} +PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 +PERFMON_CNTOFF_INT_TYPE_PULSE = 1 +PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ROTATION_ANGLE' +ROTATION_ANGLE__enumvalues = { + 0: 'ROTATE_0_DEGREES', + 1: 'ROTATE_90_DEGREES', + 2: 'ROTATE_180_DEGREES', + 3: 'ROTATE_270_DEGREES', +} +ROTATE_0_DEGREES = 0 +ROTATE_90_DEGREES = 1 +ROTATE_180_DEGREES = 2 +ROTATE_270_DEGREES = 3 +ROTATION_ANGLE = ctypes.c_uint32 # enum + +# values for enumeration 'H_MIRROR_EN' +H_MIRROR_EN__enumvalues = { + 0: 'HW_MIRRORING_DISABLE', + 1: 'HW_MIRRORING_ENABLE', +} +HW_MIRRORING_DISABLE = 0 +HW_MIRRORING_ENABLE = 1 +H_MIRROR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'NUM_PIPES' +NUM_PIPES__enumvalues = { + 0: 'ONE_PIPE', + 1: 'TWO_PIPES', + 2: 'FOUR_PIPES', + 3: 'EIGHT_PIPES', + 4: 'SIXTEEN_PIPES', + 5: 'THIRTY_TWO_PIPES', + 6: 'SIXTY_FOUR_PIPES', +} +ONE_PIPE = 0 +TWO_PIPES = 1 +FOUR_PIPES = 2 +EIGHT_PIPES = 3 +SIXTEEN_PIPES = 4 +THIRTY_TWO_PIPES = 5 +SIXTY_FOUR_PIPES = 6 +NUM_PIPES = ctypes.c_uint32 # enum + +# values for enumeration 'NUM_BANKS' +NUM_BANKS__enumvalues = { + 0: 'ONE_BANK', + 1: 'TWO_BANKS', + 2: 'FOUR_BANKS', + 3: 'EIGHT_BANKS', + 4: 'SIXTEEN_BANKS', +} +ONE_BANK = 0 +TWO_BANKS = 1 +FOUR_BANKS = 2 +EIGHT_BANKS = 3 +SIXTEEN_BANKS = 4 +NUM_BANKS = ctypes.c_uint32 # enum + +# values for enumeration 'SW_MODE' +SW_MODE__enumvalues = { + 0: 'SWIZZLE_LINEAR', + 5: 'SWIZZLE_4KB_S', + 6: 'SWIZZLE_4KB_D', + 9: 'SWIZZLE_64KB_S', + 10: 'SWIZZLE_64KB_D', + 13: 'SWIZZLE_VAR_S', + 14: 'SWIZZLE_VAR_D', + 17: 'SWIZZLE_64KB_S_T', + 18: 'SWIZZLE_64KB_D_T', + 21: 'SWIZZLE_4KB_S_X', + 22: 'SWIZZLE_4KB_D_X', + 25: 'SWIZZLE_64KB_S_X', + 26: 'SWIZZLE_64KB_D_X', + 27: 'SWIZZLE_64KB_R_X', + 29: 'SWIZZLE_VAR_S_X', + 30: 'SWIZZLE_VAR_D_X', +} +SWIZZLE_LINEAR = 0 +SWIZZLE_4KB_S = 5 +SWIZZLE_4KB_D = 6 +SWIZZLE_64KB_S = 9 +SWIZZLE_64KB_D = 10 +SWIZZLE_VAR_S = 13 +SWIZZLE_VAR_D = 14 +SWIZZLE_64KB_S_T = 17 +SWIZZLE_64KB_D_T = 18 +SWIZZLE_4KB_S_X = 21 +SWIZZLE_4KB_D_X = 22 +SWIZZLE_64KB_S_X = 25 +SWIZZLE_64KB_D_X = 26 +SWIZZLE_64KB_R_X = 27 +SWIZZLE_VAR_S_X = 29 +SWIZZLE_VAR_D_X = 30 +SW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_INTERLEAVE' +PIPE_INTERLEAVE__enumvalues = { + 0: 'PIPE_INTERLEAVE_256B', + 1: 'PIPE_INTERLEAVE_512B', + 2: 'PIPE_INTERLEAVE_1KB', +} +PIPE_INTERLEAVE_256B = 0 +PIPE_INTERLEAVE_512B = 1 +PIPE_INTERLEAVE_1KB = 2 +PIPE_INTERLEAVE = ctypes.c_uint32 # enum + +# values for enumeration 'LEGACY_PIPE_INTERLEAVE' +LEGACY_PIPE_INTERLEAVE__enumvalues = { + 0: 'LEGACY_PIPE_INTERLEAVE_256B', + 1: 'LEGACY_PIPE_INTERLEAVE_512B', +} +LEGACY_PIPE_INTERLEAVE_256B = 0 +LEGACY_PIPE_INTERLEAVE_512B = 1 +LEGACY_PIPE_INTERLEAVE = ctypes.c_uint32 # enum + +# values for enumeration 'NUM_SE' +NUM_SE__enumvalues = { + 0: 'ONE_SHADER_ENGIN', + 1: 'TWO_SHADER_ENGINS', + 2: 'FOUR_SHADER_ENGINS', + 3: 'EIGHT_SHADER_ENGINS', +} +ONE_SHADER_ENGIN = 0 +TWO_SHADER_ENGINS = 1 +FOUR_SHADER_ENGINS = 2 +EIGHT_SHADER_ENGINS = 3 +NUM_SE = ctypes.c_uint32 # enum + +# values for enumeration 'NUM_RB_PER_SE' +NUM_RB_PER_SE__enumvalues = { + 0: 'ONE_RB_PER_SE', + 1: 'TWO_RB_PER_SE', + 2: 'FOUR_RB_PER_SE', +} +ONE_RB_PER_SE = 0 +TWO_RB_PER_SE = 1 +FOUR_RB_PER_SE = 2 +NUM_RB_PER_SE = ctypes.c_uint32 # enum + +# values for enumeration 'MAX_COMPRESSED_FRAGS' +MAX_COMPRESSED_FRAGS__enumvalues = { + 0: 'ONE_FRAGMENT', + 1: 'TWO_FRAGMENTS', + 2: 'FOUR_FRAGMENTS', + 3: 'EIGHT_FRAGMENTS', +} +ONE_FRAGMENT = 0 +TWO_FRAGMENTS = 1 +FOUR_FRAGMENTS = 2 +EIGHT_FRAGMENTS = 3 +MAX_COMPRESSED_FRAGS = ctypes.c_uint32 # enum + +# values for enumeration 'DIM_TYPE' +DIM_TYPE__enumvalues = { + 0: 'DIM_TYPE_1D', + 1: 'DIM_TYPE_2D', + 2: 'DIM_TYPE_3D', + 3: 'DIM_TYPE_RESERVED', +} +DIM_TYPE_1D = 0 +DIM_TYPE_2D = 1 +DIM_TYPE_3D = 2 +DIM_TYPE_RESERVED = 3 +DIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'META_LINEAR' +META_LINEAR__enumvalues = { + 0: 'META_SURF_TILED', + 1: 'META_SURF_LINEAR', +} +META_SURF_TILED = 0 +META_SURF_LINEAR = 1 +META_LINEAR = ctypes.c_uint32 # enum + +# values for enumeration 'RB_ALIGNED' +RB_ALIGNED__enumvalues = { + 0: 'RB_UNALIGNED_META_SURF', + 1: 'RB_ALIGNED_META_SURF', +} +RB_UNALIGNED_META_SURF = 0 +RB_ALIGNED_META_SURF = 1 +RB_ALIGNED = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_ALIGNED' +PIPE_ALIGNED__enumvalues = { + 0: 'PIPE_UNALIGNED_SURF', + 1: 'PIPE_ALIGNED_SURF', +} +PIPE_UNALIGNED_SURF = 0 +PIPE_ALIGNED_SURF = 1 +PIPE_ALIGNED = ctypes.c_uint32 # enum + +# values for enumeration 'ARRAY_MODE' +ARRAY_MODE__enumvalues = { + 0: 'AM_LINEAR_GENERAL', + 1: 'AM_LINEAR_ALIGNED', + 2: 'AM_1D_TILED_THIN1', + 3: 'AM_1D_TILED_THICK', + 4: 'AM_2D_TILED_THIN1', + 5: 'AM_PRT_TILED_THIN1', + 6: 'AM_PRT_2D_TILED_THIN1', + 7: 'AM_2D_TILED_THICK', + 8: 'AM_2D_TILED_XTHICK', + 9: 'AM_PRT_TILED_THICK', + 10: 'AM_PRT_2D_TILED_THICK', + 11: 'AM_PRT_3D_TILED_THIN1', + 12: 'AM_3D_TILED_THIN1', + 13: 'AM_3D_TILED_THICK', + 14: 'AM_3D_TILED_XTHICK', + 15: 'AM_PRT_3D_TILED_THICK', +} +AM_LINEAR_GENERAL = 0 +AM_LINEAR_ALIGNED = 1 +AM_1D_TILED_THIN1 = 2 +AM_1D_TILED_THICK = 3 +AM_2D_TILED_THIN1 = 4 +AM_PRT_TILED_THIN1 = 5 +AM_PRT_2D_TILED_THIN1 = 6 +AM_2D_TILED_THICK = 7 +AM_2D_TILED_XTHICK = 8 +AM_PRT_TILED_THICK = 9 +AM_PRT_2D_TILED_THICK = 10 +AM_PRT_3D_TILED_THIN1 = 11 +AM_3D_TILED_THIN1 = 12 +AM_3D_TILED_THICK = 13 +AM_3D_TILED_XTHICK = 14 +AM_PRT_3D_TILED_THICK = 15 +ARRAY_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_CONFIG' +PIPE_CONFIG__enumvalues = { + 0: 'P2', + 4: 'P4_8x16', + 5: 'P4_16x16', + 6: 'P4_16x32', + 7: 'P4_32x32', + 8: 'P8_16x16_8x16', + 9: 'P8_16x32_8x16', + 10: 'P8_32x32_8x16', + 11: 'P8_16x32_16x16', + 12: 'P8_32x32_16x16', + 13: 'P8_32x32_16x32', + 14: 'P8_32x64_32x32', + 16: 'P16_32x32_8x16', + 17: 'P16_32x32_16x16', + 18: 'P16_ADDR_SURF', +} +P2 = 0 +P4_8x16 = 4 +P4_16x16 = 5 +P4_16x32 = 6 +P4_32x32 = 7 +P8_16x16_8x16 = 8 +P8_16x32_8x16 = 9 +P8_32x32_8x16 = 10 +P8_16x32_16x16 = 11 +P8_32x32_16x16 = 12 +P8_32x32_16x32 = 13 +P8_32x64_32x32 = 14 +P16_32x32_8x16 = 16 +P16_32x32_16x16 = 17 +P16_ADDR_SURF = 18 +PIPE_CONFIG = ctypes.c_uint32 # enum + +# values for enumeration 'MICRO_TILE_MODE_NEW' +MICRO_TILE_MODE_NEW__enumvalues = { + 0: 'DISPLAY_MICRO_TILING', + 1: 'THIN_MICRO_TILING', + 2: 'DEPTH_MICRO_TILING', + 3: 'ROTATED_MICRO_TILING', + 4: 'THICK_MICRO_TILING', +} +DISPLAY_MICRO_TILING = 0 +THIN_MICRO_TILING = 1 +DEPTH_MICRO_TILING = 2 +ROTATED_MICRO_TILING = 3 +THICK_MICRO_TILING = 4 +MICRO_TILE_MODE_NEW = ctypes.c_uint32 # enum + +# values for enumeration 'TILE_SPLIT' +TILE_SPLIT__enumvalues = { + 0: 'SURF_TILE_SPLIT_64B', + 1: 'SURF_TILE_SPLIT_128B', + 2: 'SURF_TILE_SPLIT_256B', + 3: 'SURF_TILE_SPLIT_512B', + 4: 'SURF_TILE_SPLIT_1KB', + 5: 'SURF_TILE_SPLIT_2KB', + 6: 'SURF_TILE_SPLIT_4KB', +} +SURF_TILE_SPLIT_64B = 0 +SURF_TILE_SPLIT_128B = 1 +SURF_TILE_SPLIT_256B = 2 +SURF_TILE_SPLIT_512B = 3 +SURF_TILE_SPLIT_1KB = 4 +SURF_TILE_SPLIT_2KB = 5 +SURF_TILE_SPLIT_4KB = 6 +TILE_SPLIT = ctypes.c_uint32 # enum + +# values for enumeration 'BANK_WIDTH' +BANK_WIDTH__enumvalues = { + 0: 'SURF_BANK_WIDTH_1', + 1: 'SURF_BANK_WIDTH_2', + 2: 'SURF_BANK_WIDTH_4', + 3: 'SURF_BANK_WIDTH_8', +} +SURF_BANK_WIDTH_1 = 0 +SURF_BANK_WIDTH_2 = 1 +SURF_BANK_WIDTH_4 = 2 +SURF_BANK_WIDTH_8 = 3 +BANK_WIDTH = ctypes.c_uint32 # enum + +# values for enumeration 'BANK_HEIGHT' +BANK_HEIGHT__enumvalues = { + 0: 'SURF_BANK_HEIGHT_1', + 1: 'SURF_BANK_HEIGHT_2', + 2: 'SURF_BANK_HEIGHT_4', + 3: 'SURF_BANK_HEIGHT_8', +} +SURF_BANK_HEIGHT_1 = 0 +SURF_BANK_HEIGHT_2 = 1 +SURF_BANK_HEIGHT_4 = 2 +SURF_BANK_HEIGHT_8 = 3 +BANK_HEIGHT = ctypes.c_uint32 # enum + +# values for enumeration 'MACRO_TILE_ASPECT' +MACRO_TILE_ASPECT__enumvalues = { + 0: 'SURF_MACRO_ASPECT_1', + 1: 'SURF_MACRO_ASPECT_2', + 2: 'SURF_MACRO_ASPECT_4', + 3: 'SURF_MACRO_ASPECT_8', +} +SURF_MACRO_ASPECT_1 = 0 +SURF_MACRO_ASPECT_2 = 1 +SURF_MACRO_ASPECT_4 = 2 +SURF_MACRO_ASPECT_8 = 3 +MACRO_TILE_ASPECT = ctypes.c_uint32 # enum + +# values for enumeration 'LEGACY_NUM_BANKS' +LEGACY_NUM_BANKS__enumvalues = { + 0: 'SURF_2_BANK', + 1: 'SURF_4_BANK', + 2: 'SURF_8_BANK', + 3: 'SURF_16_BANK', +} +SURF_2_BANK = 0 +SURF_4_BANK = 1 +SURF_8_BANK = 2 +SURF_16_BANK = 3 +LEGACY_NUM_BANKS = ctypes.c_uint32 # enum + +# values for enumeration 'SWATH_HEIGHT' +SWATH_HEIGHT__enumvalues = { + 0: 'SWATH_HEIGHT_1L', + 1: 'SWATH_HEIGHT_2L', + 2: 'SWATH_HEIGHT_4L', + 3: 'SWATH_HEIGHT_8L', + 4: 'SWATH_HEIGHT_16L', +} +SWATH_HEIGHT_1L = 0 +SWATH_HEIGHT_2L = 1 +SWATH_HEIGHT_4L = 2 +SWATH_HEIGHT_8L = 3 +SWATH_HEIGHT_16L = 4 +SWATH_HEIGHT = ctypes.c_uint32 # enum + +# values for enumeration 'PTE_ROW_HEIGHT_LINEAR' +PTE_ROW_HEIGHT_LINEAR__enumvalues = { + 0: 'PTE_ROW_HEIGHT_LINEAR_8L', + 1: 'PTE_ROW_HEIGHT_LINEAR_16L', + 2: 'PTE_ROW_HEIGHT_LINEAR_32L', + 3: 'PTE_ROW_HEIGHT_LINEAR_64L', + 4: 'PTE_ROW_HEIGHT_LINEAR_128L', + 5: 'PTE_ROW_HEIGHT_LINEAR_256L', + 6: 'PTE_ROW_HEIGHT_LINEAR_512L', + 7: 'PTE_ROW_HEIGHT_LINEAR_1024L', +} +PTE_ROW_HEIGHT_LINEAR_8L = 0 +PTE_ROW_HEIGHT_LINEAR_16L = 1 +PTE_ROW_HEIGHT_LINEAR_32L = 2 +PTE_ROW_HEIGHT_LINEAR_64L = 3 +PTE_ROW_HEIGHT_LINEAR_128L = 4 +PTE_ROW_HEIGHT_LINEAR_256L = 5 +PTE_ROW_HEIGHT_LINEAR_512L = 6 +PTE_ROW_HEIGHT_LINEAR_1024L = 7 +PTE_ROW_HEIGHT_LINEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CHUNK_SIZE' +CHUNK_SIZE__enumvalues = { + 0: 'CHUNK_SIZE_1KB', + 1: 'CHUNK_SIZE_2KB', + 2: 'CHUNK_SIZE_4KB', + 3: 'CHUNK_SIZE_8KB', + 4: 'CHUNK_SIZE_16KB', + 5: 'CHUNK_SIZE_32KB', + 6: 'CHUNK_SIZE_64KB', +} +CHUNK_SIZE_1KB = 0 +CHUNK_SIZE_2KB = 1 +CHUNK_SIZE_4KB = 2 +CHUNK_SIZE_8KB = 3 +CHUNK_SIZE_16KB = 4 +CHUNK_SIZE_32KB = 5 +CHUNK_SIZE_64KB = 6 +CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'MIN_CHUNK_SIZE' +MIN_CHUNK_SIZE__enumvalues = { + 0: 'NO_MIN_CHUNK_SIZE', + 1: 'MIN_CHUNK_SIZE_256B', + 2: 'MIN_CHUNK_SIZE_512B', + 3: 'MIN_CHUNK_SIZE_1024B', +} +NO_MIN_CHUNK_SIZE = 0 +MIN_CHUNK_SIZE_256B = 1 +MIN_CHUNK_SIZE_512B = 2 +MIN_CHUNK_SIZE_1024B = 3 +MIN_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'META_CHUNK_SIZE' +META_CHUNK_SIZE__enumvalues = { + 0: 'META_CHUNK_SIZE_1KB', + 1: 'META_CHUNK_SIZE_2KB', + 2: 'META_CHUNK_SIZE_4KB', + 3: 'META_CHUNK_SIZE_8KB', +} +META_CHUNK_SIZE_1KB = 0 +META_CHUNK_SIZE_2KB = 1 +META_CHUNK_SIZE_4KB = 2 +META_CHUNK_SIZE_8KB = 3 +META_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'MIN_META_CHUNK_SIZE' +MIN_META_CHUNK_SIZE__enumvalues = { + 0: 'NO_MIN_META_CHUNK_SIZE', + 1: 'MIN_META_CHUNK_SIZE_64B', + 2: 'MIN_META_CHUNK_SIZE_128B', + 3: 'MIN_META_CHUNK_SIZE_256B', +} +NO_MIN_META_CHUNK_SIZE = 0 +MIN_META_CHUNK_SIZE_64B = 1 +MIN_META_CHUNK_SIZE_128B = 2 +MIN_META_CHUNK_SIZE_256B = 3 +MIN_META_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DPTE_GROUP_SIZE' +DPTE_GROUP_SIZE__enumvalues = { + 0: 'DPTE_GROUP_SIZE_64B', + 1: 'DPTE_GROUP_SIZE_128B', + 2: 'DPTE_GROUP_SIZE_256B', + 3: 'DPTE_GROUP_SIZE_512B', + 4: 'DPTE_GROUP_SIZE_1024B', + 5: 'DPTE_GROUP_SIZE_2048B', + 6: 'DPTE_GROUP_SIZE_4096B', + 7: 'DPTE_GROUP_SIZE_8192B', +} +DPTE_GROUP_SIZE_64B = 0 +DPTE_GROUP_SIZE_128B = 1 +DPTE_GROUP_SIZE_256B = 2 +DPTE_GROUP_SIZE_512B = 3 +DPTE_GROUP_SIZE_1024B = 4 +DPTE_GROUP_SIZE_2048B = 5 +DPTE_GROUP_SIZE_4096B = 6 +DPTE_GROUP_SIZE_8192B = 7 +DPTE_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'MPTE_GROUP_SIZE' +MPTE_GROUP_SIZE__enumvalues = { + 0: 'MPTE_GROUP_SIZE_64B', + 1: 'MPTE_GROUP_SIZE_128B', + 2: 'MPTE_GROUP_SIZE_256B', + 3: 'MPTE_GROUP_SIZE_512B', + 4: 'MPTE_GROUP_SIZE_1024B', + 5: 'MPTE_GROUP_SIZE_2048B', + 6: 'MPTE_GROUP_SIZE_4096B', + 7: 'MPTE_GROUP_SIZE_8192B', +} +MPTE_GROUP_SIZE_64B = 0 +MPTE_GROUP_SIZE_128B = 1 +MPTE_GROUP_SIZE_256B = 2 +MPTE_GROUP_SIZE_512B = 3 +MPTE_GROUP_SIZE_1024B = 4 +MPTE_GROUP_SIZE_2048B = 5 +MPTE_GROUP_SIZE_4096B = 6 +MPTE_GROUP_SIZE_8192B = 7 +MPTE_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_BLANK_EN' +HUBP_BLANK_EN__enumvalues = { + 0: 'HUBP_BLANK_SW_DEASSERT', + 1: 'HUBP_BLANK_SW_ASSERT', +} +HUBP_BLANK_SW_DEASSERT = 0 +HUBP_BLANK_SW_ASSERT = 1 +HUBP_BLANK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_DISABLE' +HUBP_DISABLE__enumvalues = { + 0: 'HUBP_ENABLED', + 1: 'HUBP_DISABLED', +} +HUBP_ENABLED = 0 +HUBP_DISABLED = 1 +HUBP_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_TTU_DISABLE' +HUBP_TTU_DISABLE__enumvalues = { + 0: 'HUBP_TTU_ENABLED', + 1: 'HUBP_TTU_DISABLED', +} +HUBP_TTU_ENABLED = 0 +HUBP_TTU_DISABLED = 1 +HUBP_TTU_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_NO_OUTSTANDING_REQ' +HUBP_NO_OUTSTANDING_REQ__enumvalues = { + 0: 'OUTSTANDING_REQ', + 1: 'NO_OUTSTANDING_REQ', +} +OUTSTANDING_REQ = 0 +NO_OUTSTANDING_REQ = 1 +HUBP_NO_OUTSTANDING_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_IN_BLANK' +HUBP_IN_BLANK__enumvalues = { + 0: 'HUBP_IN_ACTIVE', + 1: 'HUBP_IN_VBLANK', +} +HUBP_IN_ACTIVE = 0 +HUBP_IN_VBLANK = 1 +HUBP_IN_BLANK = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_VTG_SEL' +HUBP_VTG_SEL__enumvalues = { + 0: 'VTG_SEL_0', + 1: 'VTG_SEL_1', + 2: 'VTG_SEL_2', + 3: 'VTG_SEL_3', + 4: 'VTG_SEL_4', + 5: 'VTG_SEL_5', +} +VTG_SEL_0 = 0 +VTG_SEL_1 = 1 +VTG_SEL_2 = 2 +VTG_SEL_3 = 3 +VTG_SEL_4 = 4 +VTG_SEL_5 = 5 +HUBP_VTG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_VREADY_AT_OR_AFTER_VSYNC' +HUBP_VREADY_AT_OR_AFTER_VSYNC__enumvalues = { + 0: 'VREADY_BEFORE_VSYNC', + 1: 'VREADY_AT_OR_AFTER_VSYNC', +} +VREADY_BEFORE_VSYNC = 0 +VREADY_AT_OR_AFTER_VSYNC = 1 +HUBP_VREADY_AT_OR_AFTER_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'VMPG_SIZE' +VMPG_SIZE__enumvalues = { + 0: 'VMPG_SIZE_4KB', + 1: 'VMPG_SIZE_64KB', +} +VMPG_SIZE_4KB = 0 +VMPG_SIZE_64KB = 1 +VMPG_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_MEASURE_WIN_MODE_DCFCLK' +HUBP_MEASURE_WIN_MODE_DCFCLK__enumvalues = { + 0: 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', + 1: 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', + 2: 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', + 3: 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', +} +HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0 +HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 1 +HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 2 +HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 3 +HUBP_MEASURE_WIN_MODE_DCFCLK = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_TMZ' +SURFACE_TMZ__enumvalues = { + 0: 'SURFACE_IS_NOT_TMZ', + 1: 'SURFACE_IS_TMZ', +} +SURFACE_IS_NOT_TMZ = 0 +SURFACE_IS_TMZ = 1 +SURFACE_TMZ = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC' +SURFACE_DCC__enumvalues = { + 0: 'SURFACE_IS_NOT_DCC', + 1: 'SURFACE_IS_DCC', +} +SURFACE_IS_NOT_DCC = 0 +SURFACE_IS_DCC = 1 +SURFACE_DCC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_64B' +SURFACE_DCC_IND_64B__enumvalues = { + 0: 'SURFACE_DCC_IS_NOT_IND_64B', + 1: 'SURFACE_DCC_IS_IND_64B', +} +SURFACE_DCC_IS_NOT_IND_64B = 0 +SURFACE_DCC_IS_IND_64B = 1 +SURFACE_DCC_IND_64B = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_TYPE' +SURFACE_FLIP_TYPE__enumvalues = { + 0: 'SURFACE_V_FLIP', + 1: 'SURFACE_I_FLIP', +} +SURFACE_V_FLIP = 0 +SURFACE_I_FLIP = 1 +SURFACE_FLIP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_MODE_FOR_STEREOSYNC' +SURFACE_FLIP_MODE_FOR_STEREOSYNC__enumvalues = { + 0: 'FLIP_ANY_FRAME', + 1: 'FLIP_LEFT_EYE', + 2: 'FLIP_RIGHT_EYE', + 3: 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', +} +FLIP_ANY_FRAME = 0 +FLIP_LEFT_EYE = 1 +FLIP_RIGHT_EYE = 2 +SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 3 +SURFACE_FLIP_MODE_FOR_STEREOSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_UPDATE_LOCK' +SURFACE_UPDATE_LOCK__enumvalues = { + 0: 'SURFACE_UPDATE_IS_UNLOCKED', + 1: 'SURFACE_UPDATE_IS_LOCKED', +} +SURFACE_UPDATE_IS_UNLOCKED = 0 +SURFACE_UPDATE_IS_LOCKED = 1 +SURFACE_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_IN_STEREOSYNC' +SURFACE_FLIP_IN_STEREOSYNC__enumvalues = { + 0: 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', + 1: 'SURFACE_FLIP_IN_STEREOSYNC_MODE', +} +SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0 +SURFACE_FLIP_IN_STEREOSYNC_MODE = 1 +SURFACE_FLIP_IN_STEREOSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_DISABLE' +SURFACE_FLIP_STEREO_SELECT_DISABLE__enumvalues = { + 0: 'SURFACE_FLIP_STEREO_SELECT_ENABLED', + 1: 'SURFACE_FLIP_STEREO_SELECT_DISABLED', +} +SURFACE_FLIP_STEREO_SELECT_ENABLED = 0 +SURFACE_FLIP_STEREO_SELECT_DISABLED = 1 +SURFACE_FLIP_STEREO_SELECT_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_POLARITY' +SURFACE_FLIP_STEREO_SELECT_POLARITY__enumvalues = { + 0: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', + 1: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', +} +SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0 +SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 1 +SURFACE_FLIP_STEREO_SELECT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_INUSE_RAED_NO_LATCH' +SURFACE_INUSE_RAED_NO_LATCH__enumvalues = { + 0: 'SURFACE_INUSE_IS_LATCHED', + 1: 'SURFACE_INUSE_IS_NOT_LATCHED', +} +SURFACE_INUSE_IS_LATCHED = 0 +SURFACE_INUSE_IS_NOT_LATCHED = 1 +SURFACE_INUSE_RAED_NO_LATCH = ctypes.c_uint32 # enum + +# values for enumeration 'INT_MASK' +INT_MASK__enumvalues = { + 0: 'INT_DISABLED', + 1: 'INT_ENABLED', +} +INT_DISABLED = 0 +INT_ENABLED = 1 +INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_INT_TYPE' +SURFACE_FLIP_INT_TYPE__enumvalues = { + 0: 'SURFACE_FLIP_INT_LEVEL', + 1: 'SURFACE_FLIP_INT_PULSE', +} +SURFACE_FLIP_INT_LEVEL = 0 +SURFACE_FLIP_INT_PULSE = 1 +SURFACE_FLIP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_AWAY_INT_TYPE' +SURFACE_FLIP_AWAY_INT_TYPE__enumvalues = { + 0: 'SURFACE_FLIP_AWAY_INT_LEVEL', + 1: 'SURFACE_FLIP_AWAY_INT_PULSE', +} +SURFACE_FLIP_AWAY_INT_LEVEL = 0 +SURFACE_FLIP_AWAY_INT_PULSE = 1 +SURFACE_FLIP_AWAY_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_VUPDATE_SKIP_NUM' +SURFACE_FLIP_VUPDATE_SKIP_NUM__enumvalues = { + 0: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', + 1: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', + 2: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', + 3: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', + 4: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', + 5: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', + 6: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', + 7: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', + 8: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', + 9: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', + 10: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', + 11: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', + 12: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', + 13: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', + 14: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', + 15: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', +} +SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0 +SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 1 +SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 2 +SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 3 +SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 4 +SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 5 +SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 6 +SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 7 +SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 8 +SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 9 +SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 10 +SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 11 +SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 12 +SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 13 +SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 14 +SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 15 +SURFACE_FLIP_VUPDATE_SKIP_NUM = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_SIZE' +DFQ_SIZE__enumvalues = { + 0: 'DFQ_SIZE_0', + 1: 'DFQ_SIZE_1', + 2: 'DFQ_SIZE_2', + 3: 'DFQ_SIZE_3', + 4: 'DFQ_SIZE_4', + 5: 'DFQ_SIZE_5', + 6: 'DFQ_SIZE_6', + 7: 'DFQ_SIZE_7', +} +DFQ_SIZE_0 = 0 +DFQ_SIZE_1 = 1 +DFQ_SIZE_2 = 2 +DFQ_SIZE_3 = 3 +DFQ_SIZE_4 = 4 +DFQ_SIZE_5 = 5 +DFQ_SIZE_6 = 6 +DFQ_SIZE_7 = 7 +DFQ_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_MIN_FREE_ENTRIES' +DFQ_MIN_FREE_ENTRIES__enumvalues = { + 0: 'DFQ_MIN_FREE_ENTRIES_0', + 1: 'DFQ_MIN_FREE_ENTRIES_1', + 2: 'DFQ_MIN_FREE_ENTRIES_2', + 3: 'DFQ_MIN_FREE_ENTRIES_3', + 4: 'DFQ_MIN_FREE_ENTRIES_4', + 5: 'DFQ_MIN_FREE_ENTRIES_5', + 6: 'DFQ_MIN_FREE_ENTRIES_6', + 7: 'DFQ_MIN_FREE_ENTRIES_7', +} +DFQ_MIN_FREE_ENTRIES_0 = 0 +DFQ_MIN_FREE_ENTRIES_1 = 1 +DFQ_MIN_FREE_ENTRIES_2 = 2 +DFQ_MIN_FREE_ENTRIES_3 = 3 +DFQ_MIN_FREE_ENTRIES_4 = 4 +DFQ_MIN_FREE_ENTRIES_5 = 5 +DFQ_MIN_FREE_ENTRIES_6 = 6 +DFQ_MIN_FREE_ENTRIES_7 = 7 +DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_NUM_ENTRIES' +DFQ_NUM_ENTRIES__enumvalues = { + 0: 'DFQ_NUM_ENTRIES_0', + 1: 'DFQ_NUM_ENTRIES_1', + 2: 'DFQ_NUM_ENTRIES_2', + 3: 'DFQ_NUM_ENTRIES_3', + 4: 'DFQ_NUM_ENTRIES_4', + 5: 'DFQ_NUM_ENTRIES_5', + 6: 'DFQ_NUM_ENTRIES_6', + 7: 'DFQ_NUM_ENTRIES_7', + 8: 'DFQ_NUM_ENTRIES_8', +} +DFQ_NUM_ENTRIES_0 = 0 +DFQ_NUM_ENTRIES_1 = 1 +DFQ_NUM_ENTRIES_2 = 2 +DFQ_NUM_ENTRIES_3 = 3 +DFQ_NUM_ENTRIES_4 = 4 +DFQ_NUM_ENTRIES_5 = 5 +DFQ_NUM_ENTRIES_6 = 6 +DFQ_NUM_ENTRIES_7 = 7 +DFQ_NUM_ENTRIES_8 = 8 +DFQ_NUM_ENTRIES = ctypes.c_uint32 # enum + +# values for enumeration 'FLIP_RATE' +FLIP_RATE__enumvalues = { + 0: 'FLIP_RATE_0', + 1: 'FLIP_RATE_1', + 2: 'FLIP_RATE_2', + 3: 'FLIP_RATE_3', + 4: 'FLIP_RATE_4', + 5: 'FLIP_RATE_5', + 6: 'FLIP_RATE_6', + 7: 'FLIP_RATE_7', +} +FLIP_RATE_0 = 0 +FLIP_RATE_1 = 1 +FLIP_RATE_2 = 2 +FLIP_RATE_3 = 3 +FLIP_RATE_4 = 4 +FLIP_RATE_5 = 5 +FLIP_RATE_6 = 6 +FLIP_RATE_7 = 7 +FLIP_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'DETILE_BUFFER_PACKER_ENABLE' +DETILE_BUFFER_PACKER_ENABLE__enumvalues = { + 0: 'DETILE_BUFFER_PACKER_IS_DISABLE', + 1: 'DETILE_BUFFER_PACKER_IS_ENABLE', +} +DETILE_BUFFER_PACKER_IS_DISABLE = 0 +DETILE_BUFFER_PACKER_IS_ENABLE = 1 +DETILE_BUFFER_PACKER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_ALPHA' +CROSSBAR_FOR_ALPHA__enumvalues = { + 0: 'ALPHA_DATA_ON_ALPHA_PORT', + 1: 'ALPHA_DATA_ON_Y_G_PORT', + 2: 'ALPHA_DATA_ON_CB_B_PORT', + 3: 'ALPHA_DATA_ON_CR_R_PORT', +} +ALPHA_DATA_ON_ALPHA_PORT = 0 +ALPHA_DATA_ON_Y_G_PORT = 1 +ALPHA_DATA_ON_CB_B_PORT = 2 +ALPHA_DATA_ON_CR_R_PORT = 3 +CROSSBAR_FOR_ALPHA = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_Y_G' +CROSSBAR_FOR_Y_G__enumvalues = { + 0: 'Y_G_DATA_ON_ALPHA_PORT', + 1: 'Y_G_DATA_ON_Y_G_PORT', + 2: 'Y_G_DATA_ON_CB_B_PORT', + 3: 'Y_G_DATA_ON_CR_R_PORT', +} +Y_G_DATA_ON_ALPHA_PORT = 0 +Y_G_DATA_ON_Y_G_PORT = 1 +Y_G_DATA_ON_CB_B_PORT = 2 +Y_G_DATA_ON_CR_R_PORT = 3 +CROSSBAR_FOR_Y_G = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_CB_B' +CROSSBAR_FOR_CB_B__enumvalues = { + 0: 'CB_B_DATA_ON_ALPHA_PORT', + 1: 'CB_B_DATA_ON_Y_G_PORT', + 2: 'CB_B_DATA_ON_CB_B_PORT', + 3: 'CB_B_DATA_ON_CR_R_PORT', +} +CB_B_DATA_ON_ALPHA_PORT = 0 +CB_B_DATA_ON_Y_G_PORT = 1 +CB_B_DATA_ON_CB_B_PORT = 2 +CB_B_DATA_ON_CR_R_PORT = 3 +CROSSBAR_FOR_CB_B = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_CR_R' +CROSSBAR_FOR_CR_R__enumvalues = { + 0: 'CR_R_DATA_ON_ALPHA_PORT', + 1: 'CR_R_DATA_ON_Y_G_PORT', + 2: 'CR_R_DATA_ON_CB_B_PORT', + 3: 'CR_R_DATA_ON_CR_R_PORT', +} +CR_R_DATA_ON_ALPHA_PORT = 0 +CR_R_DATA_ON_Y_G_PORT = 1 +CR_R_DATA_ON_CB_B_PORT = 2 +CR_R_DATA_ON_CR_R_PORT = 3 +CROSSBAR_FOR_CR_R = ctypes.c_uint32 # enum + +# values for enumeration 'DET_MEM_PWR_LIGHT_SLEEP_MODE' +DET_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'DET_MEM_POWER_LIGHT_SLEEP_MODE_1', + 2: 'DET_MEM_POWER_LIGHT_SLEEP_MODE_2', +} +DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 +DET_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE' +PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', +} +PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_ENABLE' +CURSOR_ENABLE__enumvalues = { + 0: 'CURSOR_IS_DISABLE', + 1: 'CURSOR_IS_ENABLE', +} +CURSOR_IS_DISABLE = 0 +CURSOR_IS_ENABLE = 1 +CURSOR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_2X_MAGNIFY' +CURSOR_2X_MAGNIFY__enumvalues = { + 0: 'CURSOR_2X_MAGNIFY_IS_DISABLE', + 1: 'CURSOR_2X_MAGNIFY_IS_ENABLE', +} +CURSOR_2X_MAGNIFY_IS_DISABLE = 0 +CURSOR_2X_MAGNIFY_IS_ENABLE = 1 +CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_MODE' +CURSOR_MODE__enumvalues = { + 0: 'CURSOR_MONO_2BIT', + 1: 'CURSOR_COLOR_24BIT_1BIT_AND', + 2: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', + 3: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 4: 'CURSOR_COLOR_64BIT_FP_PREMULT', + 5: 'CURSOR_COLOR_64BIT_FP_UNPREMULT', +} +CURSOR_MONO_2BIT = 0 +CURSOR_COLOR_24BIT_1BIT_AND = 1 +CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 +CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 +CURSOR_COLOR_64BIT_FP_PREMULT = 4 +CURSOR_COLOR_64BIT_FP_UNPREMULT = 5 +CURSOR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SURFACE_TMZ' +CURSOR_SURFACE_TMZ__enumvalues = { + 0: 'CURSOR_SURFACE_IS_NOT_TMZ', + 1: 'CURSOR_SURFACE_IS_TMZ', +} +CURSOR_SURFACE_IS_NOT_TMZ = 0 +CURSOR_SURFACE_IS_TMZ = 1 +CURSOR_SURFACE_TMZ = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SNOOP' +CURSOR_SNOOP__enumvalues = { + 0: 'CURSOR_IS_NOT_SNOOP', + 1: 'CURSOR_IS_SNOOP', +} +CURSOR_IS_NOT_SNOOP = 0 +CURSOR_IS_SNOOP = 1 +CURSOR_SNOOP = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SYSTEM' +CURSOR_SYSTEM__enumvalues = { + 0: 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', + 1: 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', +} +CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0 +CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 1 +CURSOR_SYSTEM = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PITCH' +CURSOR_PITCH__enumvalues = { + 0: 'CURSOR_PITCH_64_PIXELS', + 1: 'CURSOR_PITCH_128_PIXELS', + 2: 'CURSOR_PITCH_256_PIXELS', +} +CURSOR_PITCH_64_PIXELS = 0 +CURSOR_PITCH_128_PIXELS = 1 +CURSOR_PITCH_256_PIXELS = 2 +CURSOR_PITCH = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_LINES_PER_CHUNK' +CURSOR_LINES_PER_CHUNK__enumvalues = { + 0: 'CURSOR_LINE_PER_CHUNK_1', + 1: 'CURSOR_LINE_PER_CHUNK_2', + 2: 'CURSOR_LINE_PER_CHUNK_4', + 3: 'CURSOR_LINE_PER_CHUNK_8', + 4: 'CURSOR_LINE_PER_CHUNK_16', +} +CURSOR_LINE_PER_CHUNK_1 = 0 +CURSOR_LINE_PER_CHUNK_2 = 1 +CURSOR_LINE_PER_CHUNK_4 = 2 +CURSOR_LINE_PER_CHUNK_8 = 3 +CURSOR_LINE_PER_CHUNK_16 = 4 +CURSOR_LINES_PER_CHUNK = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_EN' +CURSOR_PERFMON_LATENCY_MEASURE_EN__enumvalues = { + 0: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', + 1: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', +} +CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0 +CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 1 +CURSOR_PERFMON_LATENCY_MEASURE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_SEL' +CURSOR_PERFMON_LATENCY_MEASURE_SEL__enumvalues = { + 0: 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', + 1: 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', +} +CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0 +CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 1 +CURSOR_PERFMON_LATENCY_MEASURE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_STEREO_EN' +CURSOR_STEREO_EN__enumvalues = { + 0: 'CURSOR_STEREO_IS_DISABLED', + 1: 'CURSOR_STEREO_IS_ENABLED', +} +CURSOR_STEREO_IS_DISABLED = 0 +CURSOR_STEREO_IS_ENABLED = 1 +CURSOR_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS' +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__enumvalues = { + 0: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', + 1: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', +} +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0 +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 1 +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'CROB_MEM_PWR_LIGHT_SLEEP_MODE' +CROB_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', + 2: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', +} +CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 +CROB_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UPDATED' +DMDATA_UPDATED__enumvalues = { + 0: 'DMDATA_NOT_UPDATED', + 1: 'DMDATA_WAS_UPDATED', +} +DMDATA_NOT_UPDATED = 0 +DMDATA_WAS_UPDATED = 1 +DMDATA_UPDATED = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_REPEAT' +DMDATA_REPEAT__enumvalues = { + 0: 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', + 1: 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', +} +DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0 +DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 1 +DMDATA_REPEAT = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_MODE' +DMDATA_MODE__enumvalues = { + 0: 'DMDATA_SOFTWARE_UPDATE_MODE', + 1: 'DMDATA_HARDWARE_UPDATE_MODE', +} +DMDATA_SOFTWARE_UPDATE_MODE = 0 +DMDATA_HARDWARE_UPDATE_MODE = 1 +DMDATA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_QOS_MODE' +DMDATA_QOS_MODE__enumvalues = { + 0: 'DMDATA_QOS_LEVEL_FROM_TTU', + 1: 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', +} +DMDATA_QOS_LEVEL_FROM_TTU = 0 +DMDATA_QOS_LEVEL_FROM_SOFTWARE = 1 +DMDATA_QOS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_DONE' +DMDATA_DONE__enumvalues = { + 0: 'DMDATA_NOT_SENT_TO_DIG', + 1: 'DMDATA_SENT_TO_DIG', +} +DMDATA_NOT_SENT_TO_DIG = 0 +DMDATA_SENT_TO_DIG = 1 +DMDATA_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UNDERFLOW' +DMDATA_UNDERFLOW__enumvalues = { + 0: 'DMDATA_NOT_UNDERFLOW', + 1: 'DMDATA_UNDERFLOWED', +} +DMDATA_NOT_UNDERFLOW = 0 +DMDATA_UNDERFLOWED = 1 +DMDATA_UNDERFLOW = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UNDERFLOW_CLEAR' +DMDATA_UNDERFLOW_CLEAR__enumvalues = { + 0: 'DMDATA_DONT_CLEAR', + 1: 'DMDATA_CLEAR_UNDERFLOW_STATUS', +} +DMDATA_DONT_CLEAR = 0 +DMDATA_CLEAR_UNDERFLOW_STATUS = 1 +DMDATA_UNDERFLOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_XFC_PIXEL_FORMAT_ENUM' +HUBP_XFC_PIXEL_FORMAT_ENUM__enumvalues = { + 0: 'HUBP_XFC_PIXEL_IS_32BPP', + 1: 'HUBP_XFC_PIXEL_IS_64BPP', +} +HUBP_XFC_PIXEL_IS_32BPP = 0 +HUBP_XFC_PIXEL_IS_64BPP = 1 +HUBP_XFC_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_XFC_FRAME_MODE_ENUM' +HUBP_XFC_FRAME_MODE_ENUM__enumvalues = { + 0: 'HUBP_XFC_PARTIAL_FRAME_MODE', + 1: 'HUBP_XFC_FULL_FRAME_MODE', +} +HUBP_XFC_PARTIAL_FRAME_MODE = 0 +HUBP_XFC_FULL_FRAME_MODE = 1 +HUBP_XFC_FRAME_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_XFC_CHUNK_SIZE_ENUM' +HUBP_XFC_CHUNK_SIZE_ENUM__enumvalues = { + 0: 'HUBP_XFC_CHUNK_SIZE_256B', + 1: 'HUBP_XFC_CHUNK_SIZE_512B', + 2: 'HUBP_XFC_CHUNK_SIZE_1KB', + 3: 'HUBP_XFC_CHUNK_SIZE_2KB', + 4: 'HUBP_XFC_CHUNK_SIZE_4KB', + 5: 'HUBP_XFC_CHUNK_SIZE_8KB', + 6: 'HUBP_XFC_CHUNK_SIZE_16KB', + 7: 'HUBP_XFC_CHUNK_SIZE_32KB', +} +HUBP_XFC_CHUNK_SIZE_256B = 0 +HUBP_XFC_CHUNK_SIZE_512B = 1 +HUBP_XFC_CHUNK_SIZE_1KB = 2 +HUBP_XFC_CHUNK_SIZE_2KB = 3 +HUBP_XFC_CHUNK_SIZE_4KB = 4 +HUBP_XFC_CHUNK_SIZE_8KB = 5 +HUBP_XFC_CHUNK_SIZE_16KB = 6 +HUBP_XFC_CHUNK_SIZE_32KB = 7 +HUBP_XFC_CHUNK_SIZE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MMHUBBUB_XFC_XFCMON_MODE_ENUM' +MMHUBBUB_XFC_XFCMON_MODE_ENUM__enumvalues = { + 0: 'MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT', + 1: 'MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS', + 2: 'MMHUBBUB_XFC_XFCMON_MODE_PERIODS', +} +MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT = 0 +MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS = 1 +MMHUBBUB_XFC_XFCMON_MODE_PERIODS = 2 +MMHUBBUB_XFC_XFCMON_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM' +MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM__enumvalues = { + 0: 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB', + 1: 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB', +} +MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB = 0 +MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB = 1 +MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MMHUBBUB_XFC_PIXEL_FORMAT_ENUM' +MMHUBBUB_XFC_PIXEL_FORMAT_ENUM__enumvalues = { + 0: 'MMHUBBUB_XFC_PIXEL_IS_32BPP', + 1: 'MMHUBBUB_XFC_PIXEL_IS_64BPP', +} +MMHUBBUB_XFC_PIXEL_IS_32BPP = 0 +MMHUBBUB_XFC_PIXEL_IS_64BPP = 1 +MMHUBBUB_XFC_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MMHUBBUB_XFC_FRAME_MODE_ENUM' +MMHUBBUB_XFC_FRAME_MODE_ENUM__enumvalues = { + 0: 'MMHUBBUB_XFC_PARTIAL_FRAME_MODE', + 1: 'MMHUBBUB_XFC_FULL_FRAME_MODE', +} +MMHUBBUB_XFC_PARTIAL_FRAME_MODE = 0 +MMHUBBUB_XFC_FULL_FRAME_MODE = 1 +MMHUBBUB_XFC_FRAME_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_MPC_TEST_CLK_SEL' +MPC_CFG_MPC_TEST_CLK_SEL__enumvalues = { + 0: 'MPC_CFG_MPC_TEST_CLK_SEL_0', + 1: 'MPC_CFG_MPC_TEST_CLK_SEL_1', + 2: 'MPC_CFG_MPC_TEST_CLK_SEL_2', + 3: 'MPC_CFG_MPC_TEST_CLK_SEL_3', +} +MPC_CFG_MPC_TEST_CLK_SEL_0 = 0 +MPC_CFG_MPC_TEST_CLK_SEL_1 = 1 +MPC_CFG_MPC_TEST_CLK_SEL_2 = 2 +MPC_CFG_MPC_TEST_CLK_SEL_3 = 3 +MPC_CFG_MPC_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_MODE' +MPC_CRC_CALC_MODE__enumvalues = { + 0: 'MPC_CRC_ONE_SHOT_MODE', + 1: 'MPC_CRC_CONTINUOUS_MODE', +} +MPC_CRC_ONE_SHOT_MODE = 0 +MPC_CRC_CONTINUOUS_MODE = 1 +MPC_CRC_CALC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_STEREO_MODE' +MPC_CRC_CALC_STEREO_MODE__enumvalues = { + 0: 'MPC_CRC_STEREO_MODE_LEFT', + 1: 'MPC_CRC_STEREO_MODE_RIGHT', + 2: 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', + 3: 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', +} +MPC_CRC_STEREO_MODE_LEFT = 0 +MPC_CRC_STEREO_MODE_RIGHT = 1 +MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 2 +MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 3 +MPC_CRC_CALC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_INTERLACE_MODE' +MPC_CRC_CALC_INTERLACE_MODE__enumvalues = { + 0: 'MPC_CRC_INTERLACE_MODE_TOP', + 1: 'MPC_CRC_INTERLACE_MODE_BOTTOM', + 2: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', + 3: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', +} +MPC_CRC_INTERLACE_MODE_TOP = 0 +MPC_CRC_INTERLACE_MODE_BOTTOM = 1 +MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 2 +MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 3 +MPC_CRC_CALC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_SOURCE_SELECT' +MPC_CRC_SOURCE_SELECT__enumvalues = { + 0: 'MPC_CRC_SOURCE_SEL_DPP', + 1: 'MPC_CRC_SOURCE_SEL_OPP', + 2: 'MPC_CRC_SOURCE_SEL_DWB', + 3: 'MPC_CRC_SOURCE_SEL_OTHER', +} +MPC_CRC_SOURCE_SEL_DPP = 0 +MPC_CRC_SOURCE_SEL_OPP = 1 +MPC_CRC_SOURCE_SEL_DWB = 2 +MPC_CRC_SOURCE_SEL_OTHER = 3 +MPC_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET' +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET' +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_CFG_VUPDATE_LOCK_SET' +MPC_CFG_CFG_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_VUPDATE_LOCK_SET' +MPC_CFG_ADR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_CUR_VUPDATE_LOCK_SET' +MPC_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_RATE_CONTROL_DISABLE_SET' +MPC_OUT_RATE_CONTROL_DISABLE_SET__enumvalues = { + 0: 'MPC_OUT_RATE_CONTROL_SET_ENABLE', + 1: 'MPC_OUT_RATE_CONTROL_SET_DISABLE', +} +MPC_OUT_RATE_CONTROL_SET_ENABLE = 0 +MPC_OUT_RATE_CONTROL_SET_DISABLE = 1 +MPC_OUT_RATE_CONTROL_DISABLE_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE' +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE__enumvalues = { + 0: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', + 1: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', + 2: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', + 3: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', + 4: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', + 5: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', + 6: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', + 7: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', +} +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 1 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 2 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 3 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 4 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 5 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 6 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 7 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OCSC_COEF_FORMAT' +MPC_OCSC_COEF_FORMAT__enumvalues = { + 0: 'MPC_OCSC_COEF_FORMAT_S2_13', + 1: 'MPC_OCSC_COEF_FORMAT_S3_12', +} +MPC_OCSC_COEF_FORMAT_S2_13 = 0 +MPC_OCSC_COEF_FORMAT_S3_12 = 1 +MPC_OCSC_COEF_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_CSC_MODE' +MPC_OUT_CSC_MODE__enumvalues = { + 0: 'MPC_OUT_CSC_MODE_0', + 1: 'MPC_OUT_CSC_MODE_1', + 2: 'MPC_OUT_CSC_MODE_2', + 3: 'MPC_OUT_CSC_MODE_RSV', +} +MPC_OUT_CSC_MODE_0 = 0 +MPC_OUT_CSC_MODE_1 = 1 +MPC_OUT_CSC_MODE_2 = 2 +MPC_OUT_CSC_MODE_RSV = 3 +MPC_OUT_CSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_MODE' +MPCC_CONTROL_MPCC_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_MODE_BYPASS', + 1: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', + 2: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', + 3: 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', +} +MPCC_CONTROL_MPCC_MODE_BYPASS = 0 +MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 1 +MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 2 +MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 3 +MPCC_CONTROL_MPCC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE' +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', + 1: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 2: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', + 3: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', +} +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 2 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 3 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE' +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', + 1: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', +} +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0 +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 1 +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY' +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', + 1: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', +} +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0 +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 1 +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_EN' +MPCC_SM_CONTROL_MPCC_SM_EN__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_MODE' +MPCC_SM_CONTROL_MPCC_SM_MODE__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', + 2: 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', + 4: 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', + 6: 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', +} +MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0 +MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 2 +MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 4 +MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 +MPCC_SM_CONTROL_MPCC_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT' +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT' +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL' +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', +} +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL' +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', + 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', +} +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK' +MPCC_STALL_STATUS_MPCC_STALL_INT_ACK__enumvalues = { + 0: 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE', + 1: 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE', +} +MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE = 0 +MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE = 1 +MPCC_STALL_STATUS_MPCC_STALL_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK' +MPCC_STALL_STATUS_MPCC_STALL_INT_MASK__enumvalues = { + 0: 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE', + 1: 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE', +} +MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE = 0 +MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE = 1 +MPCC_STALL_STATUS_MPCC_STALL_INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_BG_COLOR_BPC' +MPCC_BG_COLOR_BPC__enumvalues = { + 0: 'MPCC_BG_COLOR_BPC_8bit', + 1: 'MPCC_BG_COLOR_BPC_9bit', + 2: 'MPCC_BG_COLOR_BPC_10bit', + 3: 'MPCC_BG_COLOR_BPC_11bit', + 4: 'MPCC_BG_COLOR_BPC_12bit', +} +MPCC_BG_COLOR_BPC_8bit = 0 +MPCC_BG_COLOR_BPC_9bit = 1 +MPCC_BG_COLOR_BPC_10bit = 2 +MPCC_BG_COLOR_BPC_11bit = 3 +MPCC_BG_COLOR_BPC_12bit = 4 +MPCC_BG_COLOR_BPC = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE' +MPCC_CONTROL_MPCC_BOT_GAIN_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', + 1: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', +} +MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0 +MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 1 +MPCC_CONTROL_MPCC_BOT_GAIN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL' +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', + 1: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', +} +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0 +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 1 +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_MODE_MPCC_OGAM_MODE' +MPCC_OGAM_MODE_MPCC_OGAM_MODE__enumvalues = { + 0: 'MPCC_OGAM_MODE_0', + 1: 'MPCC_OGAM_MODE_1', + 2: 'MPCC_OGAM_MODE_2', + 3: 'MPCC_OGAM_MODE_RSV', +} +MPCC_OGAM_MODE_0 = 0 +MPCC_OGAM_MODE_1 = 1 +MPCC_OGAM_MODE_2 = 2 +MPCC_OGAM_MODE_RSV = 3 +MPCC_OGAM_MODE_MPCC_OGAM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_EN' +ENUM_DPG_EN__enumvalues = { + 0: 'ENUM_DPG_DISABLE', + 1: 'ENUM_DPG_ENABLE', +} +ENUM_DPG_DISABLE = 0 +ENUM_DPG_ENABLE = 1 +ENUM_DPG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_MODE' +ENUM_DPG_MODE__enumvalues = { + 0: 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', + 1: 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', + 2: 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', + 3: 'ENUM_DPG_MODE_VERTICAL_BAR', + 4: 'ENUM_DPG_MODE_HORIZONTAL_BAR', + 5: 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', + 6: 'ENUM_DPG_MODE_RGB_DUAL_RAMP', + 7: 'ENUM_DPG_MODE_RGB_XR_BIAS', +} +ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0 +ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 1 +ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 2 +ENUM_DPG_MODE_VERTICAL_BAR = 3 +ENUM_DPG_MODE_HORIZONTAL_BAR = 4 +ENUM_DPG_MODE_RGB_SINGLE_RAMP = 5 +ENUM_DPG_MODE_RGB_DUAL_RAMP = 6 +ENUM_DPG_MODE_RGB_XR_BIAS = 7 +ENUM_DPG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_DYNAMIC_RANGE' +ENUM_DPG_DYNAMIC_RANGE__enumvalues = { + 0: 'ENUM_DPG_DYNAMIC_RANGE_VESA', + 1: 'ENUM_DPG_DYNAMIC_RANGE_CEA', +} +ENUM_DPG_DYNAMIC_RANGE_VESA = 0 +ENUM_DPG_DYNAMIC_RANGE_CEA = 1 +ENUM_DPG_DYNAMIC_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_BIT_DEPTH' +ENUM_DPG_BIT_DEPTH__enumvalues = { + 0: 'ENUM_DPG_BIT_DEPTH_6BPC', + 1: 'ENUM_DPG_BIT_DEPTH_8BPC', + 2: 'ENUM_DPG_BIT_DEPTH_10BPC', + 3: 'ENUM_DPG_BIT_DEPTH_12BPC', +} +ENUM_DPG_BIT_DEPTH_6BPC = 0 +ENUM_DPG_BIT_DEPTH_8BPC = 1 +ENUM_DPG_BIT_DEPTH_10BPC = 2 +ENUM_DPG_BIT_DEPTH_12BPC = 3 +ENUM_DPG_BIT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_FIELD_POLARITY' +ENUM_DPG_FIELD_POLARITY__enumvalues = { + 0: 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', + 1: 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', +} +ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0 +ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1 +ENUM_DPG_FIELD_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' +FMT_CONTROL_PIXEL_ENCODING__enumvalues = { + 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', +} +FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 +FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 +FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 +FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 +FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' +FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', +} +FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 +FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 +FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 +FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 +FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' +FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', +} +FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 +FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 +FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { + 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', +} +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' +FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' +FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', +} +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' +FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { + 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', +} +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' +FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { + 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', +} +FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 +FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 +FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 +FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 +FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 +FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_SPATIAL_DITHER_MODE' +FMT_SPATIAL_DITHER_MODE__enumvalues = { + 0: 'FMT_SPATIAL_DITHER_MODE_0', + 1: 'FMT_SPATIAL_DITHER_MODE_1', + 2: 'FMT_SPATIAL_DITHER_MODE_2', + 3: 'FMT_SPATIAL_DITHER_MODE_3', +} +FMT_SPATIAL_DITHER_MODE_0 = 0 +FMT_SPATIAL_DITHER_MODE_1 = 1 +FMT_SPATIAL_DITHER_MODE_2 = 2 +FMT_SPATIAL_DITHER_MODE_3 = 3 +FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DYNAMIC_EXP_MODE' +FMT_DYNAMIC_EXP_MODE__enumvalues = { + 0: 'FMT_DYNAMIC_EXP_MODE_10to12', + 1: 'FMT_DYNAMIC_EXP_MODE_8to12', +} +FMT_DYNAMIC_EXP_MODE_10to12 = 0 +FMT_DYNAMIC_EXP_MODE_8to12 = 1 +FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMTMEM_PWR_FORCE_CTRL' +FMTMEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'FMTMEM_NO_FORCE_REQUEST', + 1: 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', +} +FMTMEM_NO_FORCE_REQUEST = 0 +FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 2 +FMTMEM_FORCE_SHUT_DOWN_REQUEST = 3 +FMTMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'FMTMEM_PWR_DIS_CTRL' +FMTMEM_PWR_DIS_CTRL__enumvalues = { + 0: 'FMTMEM_ENABLE_MEM_PWR_CTRL', + 1: 'FMTMEM_DISABLE_MEM_PWR_CTRL', +} +FMTMEM_ENABLE_MEM_PWR_CTRL = 0 +FMTMEM_DISABLE_MEM_PWR_CTRL = 1 +FMTMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_POWER_STATE_ENUM' +FMT_POWER_STATE_ENUM__enumvalues = { + 0: 'FMT_POWER_STATE_ENUM_ON', + 1: 'FMT_POWER_STATE_ENUM_LS', + 2: 'FMT_POWER_STATE_ENUM_DS', + 3: 'FMT_POWER_STATE_ENUM_SD', +} +FMT_POWER_STATE_ENUM_ON = 0 +FMT_POWER_STATE_ENUM_LS = 1 +FMT_POWER_STATE_ENUM_DS = 2 +FMT_POWER_STATE_ENUM_SD = 3 +FMT_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_STEREOSYNC_OVERRIDE_CONTROL' +FMT_STEREOSYNC_OVERRIDE_CONTROL__enumvalues = { + 0: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', + 1: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', +} +FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0 +FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 1 +FMT_STEREOSYNC_OVERRIDE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL' +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL__enumvalues = { + 0: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', + 1: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', + 2: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', + 3: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', +} +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 1 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 2 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 3 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_FRAME_RANDOM_ENABLE_CONTROL' +FMT_FRAME_RANDOM_ENABLE_CONTROL__enumvalues = { + 0: 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', + 1: 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', +} +FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0 +FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 1 +FMT_FRAME_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_RGB_RANDOM_ENABLE_CONTROL' +FMT_RGB_RANDOM_ENABLE_CONTROL__enumvalues = { + 0: 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', + 1: 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', +} +FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0 +FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 1 +FMT_RGB_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_FMT_PTI_FIELD_POLARITY' +ENUM_FMT_PTI_FIELD_POLARITY__enumvalues = { + 0: 'ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', + 1: 'ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', +} +ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0 +ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1 +ENUM_FMT_PTI_FIELD_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CLOCK_ENABLE_CONTROL' +OPP_PIPE_CLOCK_ENABLE_CONTROL__enumvalues = { + 0: 'OPP_PIPE_CLOCK_DISABLE', + 1: 'OPP_PIPE_CLOCK_ENABLE', +} +OPP_PIPE_CLOCK_DISABLE = 0 +OPP_PIPE_CLOCK_ENABLE = 1 +OPP_PIPE_CLOCK_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL' +OPP_PIPE_DIGTIAL_BYPASS_CONTROL__enumvalues = { + 0: 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', + 1: 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', +} +OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0 +OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 1 +OPP_PIPE_DIGTIAL_BYPASS_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_EN' +OPP_PIPE_CRC_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_DISABLE', + 1: 'OPP_PIPE_CRC_ENABLE', +} +OPP_PIPE_CRC_DISABLE = 0 +OPP_PIPE_CRC_ENABLE = 1 +OPP_PIPE_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_CONT_EN' +OPP_PIPE_CRC_CONT_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_MODE_ONE_SHOT', + 1: 'OPP_PIPE_CRC_MODE_CONTINUOUS', +} +OPP_PIPE_CRC_MODE_ONE_SHOT = 0 +OPP_PIPE_CRC_MODE_CONTINUOUS = 1 +OPP_PIPE_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_STEREO_MODE' +OPP_PIPE_CRC_STEREO_MODE__enumvalues = { + 0: 'OPP_PIPE_CRC_STEREO_MODE_LEFT', + 1: 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', + 2: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', + 3: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', +} +OPP_PIPE_CRC_STEREO_MODE_LEFT = 0 +OPP_PIPE_CRC_STEREO_MODE_RIGHT = 1 +OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 2 +OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 3 +OPP_PIPE_CRC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_STEREO_EN' +OPP_PIPE_CRC_STEREO_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', + 1: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', +} +OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0 +OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 1 +OPP_PIPE_CRC_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_INTERLACE_MODE' +OPP_PIPE_CRC_INTERLACE_MODE__enumvalues = { + 0: 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', + 1: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', + 2: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', + 3: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', +} +OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0 +OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 1 +OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 2 +OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 3 +OPP_PIPE_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_INTERLACE_EN' +OPP_PIPE_CRC_INTERLACE_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', + 1: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', +} +OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0 +OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 1 +OPP_PIPE_CRC_INTERLACE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_PIXEL_SELECT' +OPP_PIPE_CRC_PIXEL_SELECT__enumvalues = { + 0: 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', + 1: 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', + 2: 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', + 3: 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', +} +OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0 +OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 1 +OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 2 +OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 3 +OPP_PIPE_CRC_PIXEL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_SOURCE_SELECT' +OPP_PIPE_CRC_SOURCE_SELECT__enumvalues = { + 0: 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', + 1: 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', +} +OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0 +OPP_PIPE_CRC_SOURCE_SELECT_SFT = 1 +OPP_PIPE_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_ONE_SHOT_PENDING' +OPP_PIPE_CRC_ONE_SHOT_PENDING__enumvalues = { + 0: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', + 1: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', +} +OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0 +OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 1 +OPP_PIPE_CRC_ONE_SHOT_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TOP_CLOCK_GATING_CONTROL' +OPP_TOP_CLOCK_GATING_CONTROL__enumvalues = { + 0: 'OPP_TOP_CLOCK_GATING_ENABLED', + 1: 'OPP_TOP_CLOCK_GATING_DISABLED', +} +OPP_TOP_CLOCK_GATING_ENABLED = 0 +OPP_TOP_CLOCK_GATING_DISABLED = 1 +OPP_TOP_CLOCK_GATING_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TOP_CLOCK_ENABLE_STATUS' +OPP_TOP_CLOCK_ENABLE_STATUS__enumvalues = { + 0: 'OPP_TOP_CLOCK_DISABLED_STATUS', + 1: 'OPP_TOP_CLOCK_ENABLED_STATUS', +} +OPP_TOP_CLOCK_DISABLED_STATUS = 0 +OPP_TOP_CLOCK_ENABLED_STATUS = 1 +OPP_TOP_CLOCK_ENABLE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TEST_CLK_SEL_CONTROL' +OPP_TEST_CLK_SEL_CONTROL__enumvalues = { + 0: 'OPP_TEST_CLK_SEL_DISPCLK_P', + 1: 'OPP_TEST_CLK_SEL_DISPCLK_R', + 2: 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', + 3: 'OPP_TEST_CLK_SEL_RESERVED0', + 4: 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', + 5: 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', + 6: 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', + 7: 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', + 8: 'OPP_TEST_CLK_SEL_DISPCLK_OPP4', + 9: 'OPP_TEST_CLK_SEL_DISPCLK_OPP5', +} +OPP_TEST_CLK_SEL_DISPCLK_P = 0 +OPP_TEST_CLK_SEL_DISPCLK_R = 1 +OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 2 +OPP_TEST_CLK_SEL_RESERVED0 = 3 +OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 4 +OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 5 +OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 6 +OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 7 +OPP_TEST_CLK_SEL_DISPCLK_OPP4 = 8 +OPP_TEST_CLK_SEL_DISPCLK_OPP5 = 9 +OPP_TEST_CLK_SEL_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_START_POINT_CNTL' +OTG_CONTROL_OTG_START_POINT_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', + 1: 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', +} +OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0 +OTG_CONTROL_OTG_START_POINT_CNTL_DP = 1 +OTG_CONTROL_OTG_START_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL' +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', + 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', +} +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0 +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 1 +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL' +OTG_CONTROL_OTG_DISABLE_POINT_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', + 1: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 2: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED', + 3: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', +} +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED = 2 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY' +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY__enumvalues = { + 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', + 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', +} +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0 +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 1 +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE' +OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE__enumvalues = { + 0: 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE', + 1: 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE', +} +OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE = 0 +OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE = 1 +OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_SOF_PULL_EN' +OTG_CONTROL_OTG_SOF_PULL_EN__enumvalues = { + 0: 'OTG_CONTROL_OTG_SOF_PULL_EN_FALSE', + 1: 'OTG_CONTROL_OTG_SOF_PULL_EN_TRUE', +} +OTG_CONTROL_OTG_SOF_PULL_EN_FALSE = 0 +OTG_CONTROL_OTG_SOF_PULL_EN_TRUE = 1 +OTG_CONTROL_OTG_SOF_PULL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL' +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', +} +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 1 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL' +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', +} +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 1 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN' +OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE', +} +OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0 +OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE = 1 +OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC' +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', +} +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT' +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', +} +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 1 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD' +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', + 1: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', +} +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0 +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 1 +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK' +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__enumvalues = { + 0: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE', + 1: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE', +} +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0 +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 1 +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR' +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR__enumvalues = { + 0: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', + 1: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', +} +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0 +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 1 +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN' +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN__enumvalues = { + 0: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', + 1: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', +} +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0 +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 1 +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', + 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', + 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', + 8: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', + 9: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', + 10: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', + 11: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', + 12: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', + 13: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', + 14: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL', + 15: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', + 16: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', + 17: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', + 18: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', + 19: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', + 20: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', + 21: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 22: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 23: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', + 24: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', +} +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 6 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 7 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 8 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 9 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 11 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 12 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 13 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL = 14 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 15 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 17 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 18 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 19 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 20 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 23 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 24 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', + 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', + 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', +} +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 6 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 7 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', + 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', + 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', + 8: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', + 9: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', + 10: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', + 11: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', + 12: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', + 13: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', + 14: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL', + 15: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', + 16: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', + 17: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', + 18: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', + 19: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', + 20: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', + 21: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 22: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 23: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', + 24: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', +} +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 6 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 7 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 8 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 9 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 11 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 12 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 13 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL = 14 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 15 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 17 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 18 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 19 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 20 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 23 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 24 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5', +} +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4 = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5 = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', + 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', + 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', +} +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 6 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 7 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5', +} +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4 = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5 = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN' +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', +} +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR' +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', +} +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN' +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', +} +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR' +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', +} +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', + 2: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 3: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 3 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 2: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 3: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 4: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', + 5: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 6: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 7: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 8: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 9: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 10: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 11: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 12: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 13: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 14: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 15: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE', + 16: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', + 17: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', + 18: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', + 19: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 2 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 3 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 4 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 5 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 6 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 7 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 8 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 9 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 10 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 11 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 12 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 13 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 14 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE = 15 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 16 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 17 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 18 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 19 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE' +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE__enumvalues = { + 0: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', + 1: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', + 2: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', + 3: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', +} +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 1 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 2 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 3 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_MASTER_EN' +OTG_CONTROL_OTG_MASTER_EN__enumvalues = { + 0: 'OTG_CONTROL_OTG_MASTER_EN_FALSE', + 1: 'OTG_CONTROL_OTG_MASTER_EN_TRUE', +} +OTG_CONTROL_OTG_MASTER_EN_FALSE = 0 +OTG_CONTROL_OTG_MASTER_EN_TRUE = 1 +OTG_CONTROL_OTG_MASTER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN' +OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN__enumvalues = { + 0: 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE', + 1: 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE', +} +OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE = 0 +OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE = 1 +OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE' +OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE__enumvalues = { + 0: 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE', + 1: 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE', +} +OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE = 0 +OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE = 1 +OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE' +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE__enumvalues = { + 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', + 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', +} +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 1 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD' +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { + 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', + 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', + 2: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', + 3: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', +} +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 1 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 2 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY' +OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY__enumvalues = { + 0: 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE', + 1: 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE', +} +OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0 +OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 1 +OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT' +OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT__enumvalues = { + 0: 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE', + 1: 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE', +} +OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE = 0 +OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE = 1 +OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN' +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN__enumvalues = { + 0: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', + 1: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', +} +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0 +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 1 +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE' +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { + 0: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 1: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', +} +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR' +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { + 0: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 1: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', +} +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE' +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE__enumvalues = { + 0: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', + 1: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 2: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 3: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', +} +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY' +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY' +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EN' +OTG_STEREO_CONTROL_OTG_STEREO_EN__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR' +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR__enumvalues = { + 0: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', + 1: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', +} +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0 +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 1 +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL' +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { + 0: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 1: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 2: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 3: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', +} +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY' +OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY__enumvalues = { + 0: 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE', + 1: 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE', +} +OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE = 0 +OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE = 1 +OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY' +OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY__enumvalues = { + 0: 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE', + 1: 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE', +} +OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE = 0 +OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE = 1 +OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN' +OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN__enumvalues = { + 0: 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE', + 1: 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE', +} +OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE = 0 +OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE = 1 +OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN' +OTG_START_LINE_CONTROL_OTG_PREFETCH_EN__enumvalues = { + 0: 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE', + 1: 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE', +} +OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE = 0 +OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE = 1 +OTG_START_LINE_CONTROL_OTG_PREFETCH_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK' +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK__enumvalues = { + 0: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', + 1: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', +} +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0 +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 1 +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY' +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY__enumvalues = { + 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', + 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', +} +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0 +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 1 +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN' +OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN__enumvalues = { + 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE', + 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE', +} +OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0 +OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 1 +OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE' +OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE__enumvalues = { + 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0', + 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1', + 2: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2', + 3: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3', +} +OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0 +OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 1 +OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2 = 2 +OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3 = 3 +OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE' +OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE__enumvalues = { + 0: 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE', + 1: 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE', +} +OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0 +OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE = 1 +OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', +} +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME' +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME__enumvalues = { + 0: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', + 1: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', + 2: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', + 3: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', +} +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 1 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 2 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 3 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK' +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE', + 1: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE', +} +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0 +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 1 +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { + 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', + 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', + 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', +} +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 1 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 2 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE' +OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE__enumvalues = { + 0: 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE', + 1: 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG', + 2: 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL', +} +OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE = 0 +OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG = 1 +OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL = 2 +OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR' +OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR__enumvalues = { + 0: 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE', + 1: 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE', +} +OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE = 0 +OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE = 1 +OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR' +OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR__enumvalues = { + 0: 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE', + 1: 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE', +} +OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0 +OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 1 +OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR' +OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR__enumvalues = { + 0: 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE', + 1: 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE', +} +OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE = 0 +OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE = 1 +OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_EN' +OTG_CRC_CNTL_OTG_CRC_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_EN' +OTG_CRC_CNTL_OTG_CRC_CONT_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE' +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', + 1: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', + 2: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', + 3: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', +} +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 1 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 2 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 3 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE' +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', + 1: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', + 2: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 3: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', +} +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 1 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 3 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS' +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT' +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', + 1: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', + 2: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', + 3: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', + 4: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', + 5: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', + 6: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', + 7: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', +} +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 1 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 2 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 3 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 4 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 5 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 6 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 7 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT' +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', + 1: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', + 2: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', + 3: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', + 4: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', + 5: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', + 6: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', + 7: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', +} +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 1 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 2 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 3 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 4 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 5 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 6 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 7 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE' +OTG_CRC_CNTL2_OTG_CRC_DSC_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE', + 1: 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE', +} +OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE = 0 +OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE = 1 +OTG_CRC_CNTL2_OTG_CRC_DSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE' +OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE', + 1: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE', +} +OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE = 0 +OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE = 1 +OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE' +OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE', + 1: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1', + 2: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2', + 3: 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3', +} +OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE = 0 +OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1 = 1 +OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2 = 2 +OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3 = 3 +OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT' +OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT__enumvalues = { + 0: 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0', + 1: 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1', + 2: 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2', + 3: 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3', +} +OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0 = 0 +OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1 = 1 +OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2 = 2 +OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3 = 3 +OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE' +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE', + 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT', + 2: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS', + 3: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED', +} +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE = 0 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT = 1 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 2 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED = 3 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE' +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE', +} +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 1 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE' +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE', +} +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 1 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW' +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel', + 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel', + 2: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel', + 3: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel', +} +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 1 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 2 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 3 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE' +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE', +} +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 1 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE' +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE', +} +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 1 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY' +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE', +} +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 1 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY' +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE', +} +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 1 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE' +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE', +} +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 1 +OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE' +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE', +} +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 1 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR' +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE', +} +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 1 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE' +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE', +} +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 1 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT' +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME', + 1: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME', + 2: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME', + 3: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME', + 4: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME', + 5: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME', + 6: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME', + 7: 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME', +} +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 1 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 2 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 3 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 4 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 5 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 6 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 7 +OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE' +OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE', +} +OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0 +OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 1 +OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR' +OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE', +} +OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE = 0 +OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE = 1 +OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE' +OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE', +} +OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0 +OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE = 1 +OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE' +OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE', +} +OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0 +OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 1 +OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR' +OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE', +} +OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0 +OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 1 +OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE' +OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__enumvalues = { + 0: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE', + 1: 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE', +} +OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0 +OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 1 +OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE' +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE' +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', +} +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 2: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 3: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_SYNC_A_POL' +OTG_V_SYNC_A_POL__enumvalues = { + 0: 'OTG_V_SYNC_A_POL_HIGH', + 1: 'OTG_V_SYNC_A_POL_LOW', +} +OTG_V_SYNC_A_POL_HIGH = 0 +OTG_V_SYNC_A_POL_LOW = 1 +OTG_V_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_SYNC_A_POL' +OTG_H_SYNC_A_POL__enumvalues = { + 0: 'OTG_H_SYNC_A_POL_HIGH', + 1: 'OTG_H_SYNC_A_POL_LOW', +} +OTG_H_SYNC_A_POL_HIGH = 0 +OTG_H_SYNC_A_POL_LOW = 1 +OTG_H_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_HORZ_REPETITION_COUNT' +OTG_HORZ_REPETITION_COUNT__enumvalues = { + 0: 'OTG_HORZ_REPETITION_COUNT_0', + 1: 'OTG_HORZ_REPETITION_COUNT_1', + 2: 'OTG_HORZ_REPETITION_COUNT_2', + 3: 'OTG_HORZ_REPETITION_COUNT_3', + 4: 'OTG_HORZ_REPETITION_COUNT_4', + 5: 'OTG_HORZ_REPETITION_COUNT_5', + 6: 'OTG_HORZ_REPETITION_COUNT_6', + 7: 'OTG_HORZ_REPETITION_COUNT_7', + 8: 'OTG_HORZ_REPETITION_COUNT_8', + 9: 'OTG_HORZ_REPETITION_COUNT_9', + 10: 'OTG_HORZ_REPETITION_COUNT_10', + 11: 'OTG_HORZ_REPETITION_COUNT_11', + 12: 'OTG_HORZ_REPETITION_COUNT_12', + 13: 'OTG_HORZ_REPETITION_COUNT_13', + 14: 'OTG_HORZ_REPETITION_COUNT_14', + 15: 'OTG_HORZ_REPETITION_COUNT_15', +} +OTG_HORZ_REPETITION_COUNT_0 = 0 +OTG_HORZ_REPETITION_COUNT_1 = 1 +OTG_HORZ_REPETITION_COUNT_2 = 2 +OTG_HORZ_REPETITION_COUNT_3 = 3 +OTG_HORZ_REPETITION_COUNT_4 = 4 +OTG_HORZ_REPETITION_COUNT_5 = 5 +OTG_HORZ_REPETITION_COUNT_6 = 6 +OTG_HORZ_REPETITION_COUNT_7 = 7 +OTG_HORZ_REPETITION_COUNT_8 = 8 +OTG_HORZ_REPETITION_COUNT_9 = 9 +OTG_HORZ_REPETITION_COUNT_10 = 10 +OTG_HORZ_REPETITION_COUNT_11 = 11 +OTG_HORZ_REPETITION_COUNT_12 = 12 +OTG_HORZ_REPETITION_COUNT_13 = 13 +OTG_HORZ_REPETITION_COUNT_14 = 14 +OTG_HORZ_REPETITION_COUNT_15 = 15 +OTG_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_SEL' +MASTER_UPDATE_LOCK_SEL__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_SEL_0', + 1: 'MASTER_UPDATE_LOCK_SEL_1', + 2: 'MASTER_UPDATE_LOCK_SEL_2', + 3: 'MASTER_UPDATE_LOCK_SEL_3', + 4: 'MASTER_UPDATE_LOCK_SEL_4', + 5: 'MASTER_UPDATE_LOCK_SEL_5', +} +MASTER_UPDATE_LOCK_SEL_0 = 0 +MASTER_UPDATE_LOCK_SEL_1 = 1 +MASTER_UPDATE_LOCK_SEL_2 = 2 +MASTER_UPDATE_LOCK_SEL_3 = 3 +MASTER_UPDATE_LOCK_SEL_4 = 4 +MASTER_UPDATE_LOCK_SEL_5 = 5 +MASTER_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DRR_UPDATE_LOCK_SEL' +DRR_UPDATE_LOCK_SEL__enumvalues = { + 0: 'DRR_UPDATE_LOCK_SEL_0', + 1: 'DRR_UPDATE_LOCK_SEL_1', + 2: 'DRR_UPDATE_LOCK_SEL_2', + 3: 'DRR_UPDATE_LOCK_SEL_3', + 4: 'DRR_UPDATE_LOCK_SEL_4', + 5: 'DRR_UPDATE_LOCK_SEL_5', +} +DRR_UPDATE_LOCK_SEL_0 = 0 +DRR_UPDATE_LOCK_SEL_1 = 1 +DRR_UPDATE_LOCK_SEL_2 = 2 +DRR_UPDATE_LOCK_SEL_3 = 3 +DRR_UPDATE_LOCK_SEL_4 = 4 +DRR_UPDATE_LOCK_SEL_5 = 5 +DRR_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL' +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL__enumvalues = { + 0: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', + 1: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', + 2: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', + 3: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', + 4: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4', + 5: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5', +} +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 1 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 2 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 3 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4 = 4 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5 = 5 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD' +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', + 1: 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', + 2: 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', +} +MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0 +MASTER_UPDATE_LOCK_DB_FIELD_TOP = 1 +MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 2 +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL' +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', + 1: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', + 2: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', + 3: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', +} +MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 1 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 2 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 3 +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_TIMING_DIV_BY2' +OTG_H_TIMING_DIV_BY2__enumvalues = { + 0: 'OTG_H_TIMING_DIV_BY2_FALSE', + 1: 'OTG_H_TIMING_DIV_BY2_TRUE', +} +OTG_H_TIMING_DIV_BY2_FALSE = 0 +OTG_H_TIMING_DIV_BY2_TRUE = 1 +OTG_H_TIMING_DIV_BY2 = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE' +OTG_H_TIMING_DIV_BY2_UPDATE_MODE__enumvalues = { + 0: 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0', + 1: 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1', +} +OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0 = 0 +OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1 = 1 +OTG_H_TIMING_DIV_BY2_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL' +OTG_TRIGA_RISING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL' +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_FREQUENCY_SELECT' +OTG_TRIGA_FREQUENCY_SELECT__enumvalues = { + 0: 'OTG_TRIGA_FREQUENCY_SELECT_0', + 1: 'OTG_TRIGA_FREQUENCY_SELECT_1', + 2: 'OTG_TRIGA_FREQUENCY_SELECT_2', + 3: 'OTG_TRIGA_FREQUENCY_SELECT_3', +} +OTG_TRIGA_FREQUENCY_SELECT_0 = 0 +OTG_TRIGA_FREQUENCY_SELECT_1 = 1 +OTG_TRIGA_FREQUENCY_SELECT_2 = 2 +OTG_TRIGA_FREQUENCY_SELECT_3 = 3 +OTG_TRIGA_FREQUENCY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL' +OTG_TRIGB_RISING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL' +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_FREQUENCY_SELECT' +OTG_TRIGB_FREQUENCY_SELECT__enumvalues = { + 0: 'OTG_TRIGB_FREQUENCY_SELECT_0', + 1: 'OTG_TRIGB_FREQUENCY_SELECT_1', + 2: 'OTG_TRIGB_FREQUENCY_SELECT_2', + 3: 'OTG_TRIGB_FREQUENCY_SELECT_3', +} +OTG_TRIGB_FREQUENCY_SELECT_0 = 0 +OTG_TRIGB_FREQUENCY_SELECT_1 = 1 +OTG_TRIGB_FREQUENCY_SELECT_2 = 2 +OTG_TRIGB_FREQUENCY_SELECT_3 = 3 +OTG_TRIGB_FREQUENCY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_PIPE_ABORT' +OTG_PIPE_ABORT__enumvalues = { + 0: 'OTG_PIPE_ABORT_0', + 1: 'OTG_PIPE_ABORT_1', +} +OTG_PIPE_ABORT_0 = 0 +OTG_PIPE_ABORT_1 = 1 +OTG_PIPE_ABORT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_GSL_EN' +OTG_MASTER_UPDATE_LOCK_GSL_EN__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', + 1: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', +} +OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0 +OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 1 +OTG_MASTER_UPDATE_LOCK_GSL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_PTI_CONTROL_OTG_PIT_EN' +OTG_PTI_CONTROL_OTG_PIT_EN__enumvalues = { + 0: 'OTG_PTI_CONTROL_OTG_PIT_EN_FALSE', + 1: 'OTG_PTI_CONTROL_OTG_PIT_EN_TRUE', +} +OTG_PTI_CONTROL_OTG_PIT_EN_FALSE = 0 +OTG_PTI_CONTROL_OTG_PIT_EN_TRUE = 1 +OTG_PTI_CONTROL_OTG_PIT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GSL_MASTER_MODE' +OTG_GSL_MASTER_MODE__enumvalues = { + 0: 'OTG_GSL_MASTER_MODE_0', + 1: 'OTG_GSL_MASTER_MODE_1', + 2: 'OTG_GSL_MASTER_MODE_2', + 3: 'OTG_GSL_MASTER_MODE_3', +} +OTG_GSL_MASTER_MODE_0 = 0 +OTG_GSL_MASTER_MODE_1 = 1 +OTG_GSL_MASTER_MODE_2 = 2 +OTG_GSL_MASTER_MODE_3 = 3 +OTG_GSL_MASTER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DC_DMCUB_TIMER_WINDOW' +DC_DMCUB_TIMER_WINDOW__enumvalues = { + 0: 'BITS_31_0', + 1: 'BITS_32_1', + 2: 'BITS_33_2', + 3: 'BITS_34_3', + 4: 'BITS_35_4', + 5: 'BITS_36_5', + 6: 'BITS_37_6', + 7: 'BITS_38_7', +} +BITS_31_0 = 0 +BITS_32_1 = 1 +BITS_33_2 = 2 +BITS_34_3 = 3 +BITS_35_4 = 4 +BITS_36_5 = 5 +BITS_37_6 = 6 +BITS_38_7 = 7 +DC_DMCUB_TIMER_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DC_DMCUB_INT_TYPE' +DC_DMCUB_INT_TYPE__enumvalues = { + 0: 'INT_LEVEL', + 1: 'INT_PULSE', +} +INT_LEVEL = 0 +INT_PULSE = 1 +DC_DMCUB_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'INVALID_REG_ACCESS_TYPE' +INVALID_REG_ACCESS_TYPE__enumvalues = { + 0: 'REG_UNALLOCATED_ADDR_WRITE', + 1: 'REG_UNALLOCATED_ADDR_READ', + 2: 'REG_VIRTUAL_WRITE', + 3: 'REG_VIRTUAL_READ', +} +REG_UNALLOCATED_ADDR_WRITE = 0 +REG_UNALLOCATED_ADDR_READ = 1 +REG_VIRTUAL_WRITE = 2 +REG_VIRTUAL_READ = 3 +INVALID_REG_ACCESS_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_DC_GPU_TIMER_START_POSITION' +DMU_DC_GPU_TIMER_START_POSITION__enumvalues = { + 0: 'DMU_GPU_TIMER_START_0_END_27', + 1: 'DMU_GPU_TIMER_START_1_END_28', + 2: 'DMU_GPU_TIMER_START_2_END_29', + 3: 'DMU_GPU_TIMER_START_3_END_30', + 4: 'DMU_GPU_TIMER_START_4_END_31', + 5: 'DMU_GPU_TIMER_START_6_END_33', + 6: 'DMU_GPU_TIMER_START_8_END_35', + 7: 'DMU_GPU_TIMER_START_10_END_37', +} +DMU_GPU_TIMER_START_0_END_27 = 0 +DMU_GPU_TIMER_START_1_END_28 = 1 +DMU_GPU_TIMER_START_2_END_29 = 2 +DMU_GPU_TIMER_START_3_END_30 = 3 +DMU_GPU_TIMER_START_4_END_31 = 4 +DMU_GPU_TIMER_START_6_END_33 = 5 +DMU_GPU_TIMER_START_8_END_35 = 6 +DMU_GPU_TIMER_START_10_END_37 = 7 +DMU_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_DC_GPU_TIMER_READ_SELECT' +DMU_DC_GPU_TIMER_READ_SELECT__enumvalues = { + 0: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', + 1: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', + 2: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', + 3: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', + 4: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', + 5: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', + 6: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', + 7: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', + 8: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8', + 9: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9', + 10: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10', + 11: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11', + 12: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', + 13: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', + 14: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', + 15: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', + 16: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', + 17: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', + 18: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', + 19: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', + 20: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20', + 21: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21', + 22: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22', + 23: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23', + 24: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', + 25: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', + 26: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', + 27: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', + 28: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', + 29: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', + 30: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', + 31: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', + 32: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32', + 33: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33', + 34: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34', + 35: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35', + 36: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', + 37: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', + 38: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', + 39: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', + 40: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', + 41: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', + 42: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', + 43: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', + 44: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44', + 45: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45', + 46: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46', + 47: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47', + 48: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', + 49: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', + 50: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', + 51: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', + 52: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', + 53: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', + 54: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', + 55: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', + 56: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56', + 57: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57', + 58: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58', + 59: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59', + 60: 'RESERVED_60', + 61: 'RESERVED_61', + 62: 'RESERVED_62', + 63: 'RESERVED_63', + 64: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', + 65: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', + 66: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', + 67: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', + 68: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', + 69: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', + 70: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', + 71: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', + 72: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72', + 73: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73', + 74: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74', + 75: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75', + 76: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', + 77: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', + 78: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', + 79: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', + 80: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', + 81: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', + 82: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', + 83: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', + 84: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84', + 85: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85', + 86: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86', + 87: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87', + 88: 'RESERVED_88', + 89: 'RESERVED_89', + 90: 'RESERVED_90', + 91: 'RESERVED_91', +} +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 1 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 2 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 3 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 4 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 5 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 6 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 7 +DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8 = 8 +DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9 = 9 +DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10 = 10 +DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11 = 11 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 12 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 13 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 14 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 15 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 16 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 17 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 18 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 19 +DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20 = 20 +DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21 = 21 +DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22 = 22 +DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23 = 23 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 24 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 25 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 26 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 27 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 28 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 29 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 30 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 31 +DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32 = 32 +DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33 = 33 +DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34 = 34 +DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35 = 35 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 36 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 37 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 38 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 39 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 40 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 41 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 42 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 43 +DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44 = 44 +DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45 = 45 +DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46 = 46 +DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47 = 47 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 48 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 49 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 50 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 51 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 52 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 53 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 54 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 55 +DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56 = 56 +DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57 = 57 +DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58 = 58 +DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59 = 59 +RESERVED_60 = 60 +RESERVED_61 = 61 +RESERVED_62 = 62 +RESERVED_63 = 63 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 64 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 65 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 66 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 67 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 68 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 69 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 70 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 71 +DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72 = 72 +DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73 = 73 +DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74 = 74 +DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75 = 75 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 76 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 77 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 78 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 79 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 80 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 81 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 82 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 83 +DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84 = 84 +DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85 = 85 +DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86 = 86 +DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87 = 87 +RESERVED_88 = 88 +RESERVED_89 = 89 +RESERVED_90 = 90 +RESERVED_91 = 91 +DMU_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'IHC_INTERRUPT_LINE_STATUS' +IHC_INTERRUPT_LINE_STATUS__enumvalues = { + 0: 'INTERRUPT_LINE_NOT_ASSERTED', + 1: 'INTERRUPT_LINE_ASSERTED', +} +INTERRUPT_LINE_NOT_ASSERTED = 0 +INTERRUPT_LINE_ASSERTED = 1 +IHC_INTERRUPT_LINE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_CLOCK_GATING_DISABLE' +DMU_CLOCK_GATING_DISABLE__enumvalues = { + 0: 'DMU_ENABLE_CLOCK_GATING', + 1: 'DMU_DISABLE_CLOCK_GATING', +} +DMU_ENABLE_CLOCK_GATING = 0 +DMU_DISABLE_CLOCK_GATING = 1 +DMU_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_CLOCK_ON' +DMU_CLOCK_ON__enumvalues = { + 0: 'DMU_CLOCK_STATUS_ON', + 1: 'DMU_CLOCK_STATUS_OFF', +} +DMU_CLOCK_STATUS_ON = 0 +DMU_CLOCK_STATUS_OFF = 1 +DMU_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'DC_SMU_INTERRUPT_ENABLE' +DC_SMU_INTERRUPT_ENABLE__enumvalues = { + 0: 'DISABLE_THE_INTERRUPT', + 1: 'ENABLE_THE_INTERRUPT', +} +DISABLE_THE_INTERRUPT = 0 +ENABLE_THE_INTERRUPT = 1 +DC_SMU_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'STATIC_SCREEN_SMU_INTR' +STATIC_SCREEN_SMU_INTR__enumvalues = { + 0: 'STATIC_SCREEN_SMU_INTR_NOOP', + 1: 'SET_STATIC_SCREEN_SMU_INTR', +} +STATIC_SCREEN_SMU_INTR_NOOP = 0 +SET_STATIC_SCREEN_SMU_INTR = 1 +STATIC_SCREEN_SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE' +ENABLE__enumvalues = { + 0: 'DISABLE_THE_FEATURE', + 1: 'ENABLE_THE_FEATURE', +} +DISABLE_THE_FEATURE = 0 +ENABLE_THE_FEATURE = 1 +ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DS_HW_CAL_ENABLE' +DS_HW_CAL_ENABLE__enumvalues = { + 0: 'DS_HW_CAL_DIS', + 1: 'DS_HW_CAL_EN', +} +DS_HW_CAL_DIS = 0 +DS_HW_CAL_EN = 1 +DS_HW_CAL_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE_CLOCK' +ENABLE_CLOCK__enumvalues = { + 0: 'DISABLE_THE_CLOCK', + 1: 'ENABLE_THE_CLOCK', +} +DISABLE_THE_CLOCK = 0 +ENABLE_THE_CLOCK = 1 +ENABLE_CLOCK = ctypes.c_uint32 # enum + +# values for enumeration 'CLEAR_SMU_INTR' +CLEAR_SMU_INTR__enumvalues = { + 0: 'SMU_INTR_STATUS_NOOP', + 1: 'SMU_INTR_STATUS_CLEAR', +} +SMU_INTR_STATUS_NOOP = 0 +SMU_INTR_STATUS_CLEAR = 1 +CLEAR_SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'JITTER_REMOVE_DISABLE' +JITTER_REMOVE_DISABLE__enumvalues = { + 0: 'ENABLE_JITTER_REMOVAL', + 1: 'DISABLE_JITTER_REMOVAL', +} +ENABLE_JITTER_REMOVAL = 0 +DISABLE_JITTER_REMOVAL = 1 +JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DS_REF_SRC' +DS_REF_SRC__enumvalues = { + 0: 'DS_REF_IS_XTALIN', + 1: 'DS_REF_IS_EXT_GENLOCK', + 2: 'DS_REF_IS_PCIE', +} +DS_REF_IS_XTALIN = 0 +DS_REF_IS_EXT_GENLOCK = 1 +DS_REF_IS_PCIE = 2 +DS_REF_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING' +DISABLE_CLOCK_GATING__enumvalues = { + 0: 'CLOCK_GATING_ENABLED', + 1: 'CLOCK_GATING_DISABLED', +} +CLOCK_GATING_ENABLED = 0 +CLOCK_GATING_DISABLED = 1 +DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' +DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { + 0: 'CLOCK_GATING_ENABLED_IN_DCO', + 1: 'CLOCK_GATING_DISABLED_IN_DCO', +} +CLOCK_GATING_ENABLED_IN_DCO = 0 +CLOCK_GATING_DISABLED_IN_DCO = 1 +DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DEEP_COLOR_CNTL' +DCCG_DEEP_COLOR_CNTL__enumvalues = { + 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', + 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', + 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', +} +DCCG_DEEP_COLOR_DTO_DISABLE = 0 +DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 +DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 +DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 +DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'REFCLK_CLOCK_EN' +REFCLK_CLOCK_EN__enumvalues = { + 0: 'REFCLK_CLOCK_EN_XTALIN_CLK', + 1: 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', +} +REFCLK_CLOCK_EN_XTALIN_CLK = 0 +REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 1 +REFCLK_CLOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'REFCLK_SRC_SEL' +REFCLK_SRC_SEL__enumvalues = { + 0: 'REFCLK_SRC_SEL_PCIE_REFCLK', + 1: 'REFCLK_SRC_SEL_CPL_REFCLK', +} +REFCLK_SRC_SEL_PCIE_REFCLK = 0 +REFCLK_SRC_SEL_CPL_REFCLK = 1 +REFCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPREFCLK_SRC_SEL' +DPREFCLK_SRC_SEL__enumvalues = { + 0: 'DPREFCLK_SRC_SEL_CK', + 1: 'DPREFCLK_SRC_SEL_P0PLL', + 2: 'DPREFCLK_SRC_SEL_P1PLL', + 3: 'DPREFCLK_SRC_SEL_P2PLL', +} +DPREFCLK_SRC_SEL_CK = 0 +DPREFCLK_SRC_SEL_P0PLL = 1 +DPREFCLK_SRC_SEL_P1PLL = 2 +DPREFCLK_SRC_SEL_P2PLL = 3 +DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_SEL' +XTAL_REF_SEL__enumvalues = { + 0: 'XTAL_REF_SEL_1X', + 1: 'XTAL_REF_SEL_2X', +} +XTAL_REF_SEL_1X = 0 +XTAL_REF_SEL_2X = 1 +XTAL_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' +XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', + 1: 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', +} +XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 +XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 1 +XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', +} +MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ALLOW_SR_ON_TRANS_REQ' +ALLOW_SR_ON_TRANS_REQ__enumvalues = { + 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', + 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', +} +ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 +ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 +ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', +} +MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_SOURCE' +PIPE_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', + 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', +} +PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 +PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 +PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 +PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLK_DIV_SEL' +TEST_CLK_DIV_SEL__enumvalues = { + 0: 'NO_DIV', + 1: 'DIV_2', + 2: 'DIV_4', + 3: 'DIV_8', +} +NO_DIV = 0 +DIV_2 = 1 +DIV_4 = 2 +DIV_8 = 3 +TEST_CLK_DIV_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' +PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE', + 5: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF', + 6: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', +} +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 4 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 5 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 6 +PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' +PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', + 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', +} +PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 +PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 +PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DTO_DS_DISABLE' +DP_DTO_DS_DISABLE__enumvalues = { + 0: 'DP_DTO_DESPREAD_DISABLE', + 1: 'DP_DTO_DESPREAD_ENABLE', +} +DP_DTO_DESPREAD_DISABLE = 0 +DP_DTO_DESPREAD_ENABLE = 1 +DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_ADD_PIXEL' +OTG_ADD_PIXEL__enumvalues = { + 0: 'OTG_ADD_PIXEL_NOOP', + 1: 'OTG_ADD_PIXEL_FORCE', +} +OTG_ADD_PIXEL_NOOP = 0 +OTG_ADD_PIXEL_FORCE = 1 +OTG_ADD_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DROP_PIXEL' +OTG_DROP_PIXEL__enumvalues = { + 0: 'OTG_DROP_PIXEL_NOOP', + 1: 'OTG_DROP_PIXEL_FORCE', +} +OTG_DROP_PIXEL_NOOP = 0 +OTG_DROP_PIXEL_FORCE = 1 +OTG_DROP_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_FORCE_EN' +SYMCLK_FE_FORCE_EN__enumvalues = { + 0: 'SYMCLK_FE_FORCE_EN_DISABLE', + 1: 'SYMCLK_FE_FORCE_EN_ENABLE', +} +SYMCLK_FE_FORCE_EN_DISABLE = 0 +SYMCLK_FE_FORCE_EN_ENABLE = 1 +SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_FORCE_SRC' +SYMCLK_FE_FORCE_SRC__enumvalues = { + 0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA', + 1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB', + 2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC', + 3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD', + 4: 'SYMCLK_FE_FORCE_SRC_UNIPHYE', + 5: 'SYMCLK_FE_FORCE_SRC_UNIPHYF', + 6: 'SYMCLK_FE_FORCE_SRC_RESERVED', +} +SYMCLK_FE_FORCE_SRC_UNIPHYA = 0 +SYMCLK_FE_FORCE_SRC_UNIPHYB = 1 +SYMCLK_FE_FORCE_SRC_UNIPHYC = 2 +SYMCLK_FE_FORCE_SRC_UNIPHYD = 3 +SYMCLK_FE_FORCE_SRC_UNIPHYE = 4 +SYMCLK_FE_FORCE_SRC_UNIPHYF = 5 +SYMCLK_FE_FORCE_SRC_RESERVED = 6 +SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLK_COARSE_SKEW_CNTL' +DVOACLK_COARSE_SKEW_CNTL__enumvalues = { + 0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', + 1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', + 2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', + 3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', + 4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', + 5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', + 6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', + 7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', + 8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', + 9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', + 10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', + 11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', + 12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', + 13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', + 14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', + 15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', + 16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', + 17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', + 18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', + 19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', + 20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', + 21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', + 22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', + 23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', + 24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', + 25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', + 26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', + 27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', + 28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', + 29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', + 30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', +} +DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0 +DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1 +DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2 +DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3 +DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4 +DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5 +DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6 +DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7 +DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8 +DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9 +DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10 +DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11 +DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12 +DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13 +DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14 +DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15 +DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16 +DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17 +DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18 +DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19 +DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20 +DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21 +DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22 +DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23 +DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24 +DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25 +DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26 +DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27 +DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28 +DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29 +DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30 +DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLK_FINE_SKEW_CNTL' +DVOACLK_FINE_SKEW_CNTL__enumvalues = { + 0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', + 1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', + 2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', + 3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', + 4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', + 5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', + 6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', + 7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', +} +DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0 +DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1 +DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2 +DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3 +DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4 +DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5 +DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6 +DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7 +DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKD_IN_PHASE' +DVOACLKD_IN_PHASE__enumvalues = { + 0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_IN_PHASE' +DVOACLKC_IN_PHASE__enumvalues = { + 0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_MVP_IN_PHASE' +DVOACLKC_MVP_IN_PHASE__enumvalues = { + 0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE' +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = { + 0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', + 1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', +} +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0 +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1 +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' +DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', + 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', + 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', + 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', + 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4', + 5: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5', + 6: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', +} +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 1 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 2 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 3 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4 = 4 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5 = 5 +DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 6 +DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_SEL' +DCCG_AUDIO_DTO_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', + 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', +} +DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 +DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 +DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 +DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' +DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', +} +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 1 +DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' +DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { + 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', +} +DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 +DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 +DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_FREQ_RAMP_DONE' +DISPCLK_FREQ_RAMP_DONE__enumvalues = { + 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', + 1: 'DISPCLK_FREQ_RAMP_COMPLETED', +} +DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 +DISPCLK_FREQ_RAMP_COMPLETED = 1 +DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_RESET' +DCCG_FIFO_ERRDET_RESET__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', + 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', +} +DCCG_FIFO_ERRDET_RESET_NOOP = 0 +DCCG_FIFO_ERRDET_RESET_FORCE = 1 +DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_STATE' +DCCG_FIFO_ERRDET_STATE__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', + 1: 'DCCG_FIFO_ERRDET_STATE_DETECTION', +} +DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0 +DCCG_FIFO_ERRDET_STATE_DETECTION = 1 +DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' +DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', + 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', +} +DCCG_FIFO_ERRDET_OVR_DISABLE = 0 +DCCG_FIFO_ERRDET_OVR_ENABLE = 1 +DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' +DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { + 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', +} +DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 +DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 +DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' +DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { + 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', +} +DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 +DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 +DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_RUN' +DCCG_PERF_RUN__enumvalues = { + 0: 'DCCG_PERF_RUN_NOOP', + 1: 'DCCG_PERF_RUN_START', +} +DCCG_PERF_RUN_NOOP = 0 +DCCG_PERF_RUN_START = 1 +DCCG_PERF_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_VSYNC' +DCCG_PERF_MODE_VSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_VSYNC_NOOP', + 1: 'DCCG_PERF_MODE_VSYNC_START', +} +DCCG_PERF_MODE_VSYNC_NOOP = 0 +DCCG_PERF_MODE_VSYNC_START = 1 +DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_HSYNC' +DCCG_PERF_MODE_HSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_HSYNC_NOOP', + 1: 'DCCG_PERF_MODE_HSYNC_START', +} +DCCG_PERF_MODE_HSYNC_NOOP = 0 +DCCG_PERF_MODE_HSYNC_START = 1 +DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_OTG_SELECT' +DCCG_PERF_OTG_SELECT__enumvalues = { + 0: 'DCCG_PERF_SEL_OTG0', + 1: 'DCCG_PERF_SEL_OTG1', + 2: 'DCCG_PERF_SEL_OTG2', + 3: 'DCCG_PERF_SEL_OTG3', + 4: 'DCCG_PERF_SEL_OTG4', + 5: 'DCCG_PERF_SEL_OTG5', + 6: 'DCCG_PERF_SEL_RESERVED', +} +DCCG_PERF_SEL_OTG0 = 0 +DCCG_PERF_SEL_OTG1 = 1 +DCCG_PERF_SEL_OTG2 = 2 +DCCG_PERF_SEL_OTG3 = 3 +DCCG_PERF_SEL_OTG4 = 4 +DCCG_PERF_SEL_OTG5 = 5 +DCCG_PERF_SEL_RESERVED = 6 +DCCG_PERF_OTG_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_BRANCH_SOFT_RESET' +CLOCK_BRANCH_SOFT_RESET__enumvalues = { + 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', + 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', +} +CLOCK_BRANCH_SOFT_RESET_NOOP = 0 +CLOCK_BRANCH_SOFT_RESET_FORCE = 1 +CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'PLL_CFG_IF_SOFT_RESET' +PLL_CFG_IF_SOFT_RESET__enumvalues = { + 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', + 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', +} +PLL_CFG_IF_SOFT_RESET_NOOP = 0 +PLL_CFG_IF_SOFT_RESET_FORCE = 1 +PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DVO_ENABLE_RST' +DVO_ENABLE_RST__enumvalues = { + 0: 'DVO_ENABLE_RST_DISABLE', + 1: 'DVO_ENABLE_RST_ENABLE', +} +DVO_ENABLE_RST_DISABLE = 0 +DVO_ENABLE_RST_ENABLE = 1 +DVO_ENABLE_RST = ctypes.c_uint32 # enum + +# values for enumeration 'DS_JITTER_COUNT_SRC_SEL' +DS_JITTER_COUNT_SRC_SEL__enumvalues = { + 0: 'DS_JITTER_COUNT_SRC_SEL0', + 1: 'DS_JITTER_COUNT_SRC_SEL1', +} +DS_JITTER_COUNT_SRC_SEL0 = 0 +DS_JITTER_COUNT_SRC_SEL1 = 1 +DS_JITTER_COUNT_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_FIFO_ERROR' +DIO_FIFO_ERROR__enumvalues = { + 0: 'DIO_FIFO_ERROR_00', + 1: 'DIO_FIFO_ERROR_01', + 2: 'DIO_FIFO_ERROR_10', + 3: 'DIO_FIFO_ERROR_11', +} +DIO_FIFO_ERROR_00 = 0 +DIO_FIFO_ERROR_01 = 1 +DIO_FIFO_ERROR_10 = 2 +DIO_FIFO_ERROR_11 = 3 +DIO_FIFO_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'VSYNC_CNT_REFCLK_SEL' +VSYNC_CNT_REFCLK_SEL__enumvalues = { + 0: 'VSYNC_CNT_REFCLK_SEL_0', + 1: 'VSYNC_CNT_REFCLK_SEL_1', +} +VSYNC_CNT_REFCLK_SEL_0 = 0 +VSYNC_CNT_REFCLK_SEL_1 = 1 +VSYNC_CNT_REFCLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VSYNC_CNT_RESET_SEL' +VSYNC_CNT_RESET_SEL__enumvalues = { + 0: 'VSYNC_CNT_RESET_SEL_0', + 1: 'VSYNC_CNT_RESET_SEL_1', +} +VSYNC_CNT_RESET_SEL_0 = 0 +VSYNC_CNT_RESET_SEL_1 = 1 +VSYNC_CNT_RESET_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VSYNC_CNT_LATCH_MASK' +VSYNC_CNT_LATCH_MASK__enumvalues = { + 0: 'VSYNC_CNT_LATCH_MASK_0', + 1: 'VSYNC_CNT_LATCH_MASK_1', +} +VSYNC_CNT_LATCH_MASK_0 = 0 +VSYNC_CNT_LATCH_MASK_1 = 1 +VSYNC_CNT_LATCH_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_ACK' +HPD_INT_CONTROL_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_ACK_0', + 1: 'HPD_INT_CONTROL_ACK_1', +} +HPD_INT_CONTROL_ACK_0 = 0 +HPD_INT_CONTROL_ACK_1 = 1 +HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_POLARITY' +HPD_INT_CONTROL_POLARITY__enumvalues = { + 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', + 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', +} +HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 +HPD_INT_CONTROL_GEN_INT_ON_CON = 1 +HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' +HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', + 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', +} +HPD_INT_CONTROL_RX_INT_ACK_0 = 0 +HPD_INT_CONTROL_RX_INT_ACK_1 = 1 +HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSO_NUM_OF_SST_LINKS' +DP_MSO_NUM_OF_SST_LINKS__enumvalues = { + 0: 'DP_MSO_ONE_SSTLINK', + 1: 'DP_MSO_TWO_SSTLINK', + 2: 'DP_MSO_FOUR_SSTLINK', +} +DP_MSO_ONE_SSTLINK = 0 +DP_MSO_TWO_SSTLINK = 1 +DP_MSO_FOUR_SSTLINK = 2 +DP_MSO_NUM_OF_SST_LINKS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SYNC_POLARITY' +DP_SYNC_POLARITY__enumvalues = { + 0: 'DP_SYNC_POLARITY_ACTIVE_HIGH', + 1: 'DP_SYNC_POLARITY_ACTIVE_LOW', +} +DP_SYNC_POLARITY_ACTIVE_HIGH = 0 +DP_SYNC_POLARITY_ACTIVE_LOW = 1 +DP_SYNC_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_COMBINE_PIXEL_NUM' +DP_COMBINE_PIXEL_NUM__enumvalues = { + 0: 'DP_COMBINE_ONE_PIXEL', + 1: 'DP_COMBINE_TWO_PIXEL', + 2: 'DP_COMBINE_FOUR_PIXEL', +} +DP_COMBINE_ONE_PIXEL = 0 +DP_COMBINE_TWO_PIXEL = 1 +DP_COMBINE_FOUR_PIXEL = 2 +DP_COMBINE_PIXEL_NUM = ctypes.c_uint32 # enum + +# values for enumeration 'DP_LINK_TRAINING_COMPLETE' +DP_LINK_TRAINING_COMPLETE__enumvalues = { + 0: 'DP_LINK_TRAINING_NOT_COMPLETE', + 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', +} +DP_LINK_TRAINING_NOT_COMPLETE = 0 +DP_LINK_TRAINING_ALREADY_COMPLETE = 1 +DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_EMBEDDED_PANEL_MODE' +DP_EMBEDDED_PANEL_MODE__enumvalues = { + 0: 'DP_EXTERNAL_PANEL', + 1: 'DP_EMBEDDED_PANEL', +} +DP_EXTERNAL_PANEL = 0 +DP_EMBEDDED_PANEL = 1 +DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_PIXEL_ENCODING' +DP_PIXEL_ENCODING__enumvalues = { + 0: 'DP_PIXEL_ENCODING_RGB444', + 1: 'DP_PIXEL_ENCODING_YCBCR422', + 2: 'DP_PIXEL_ENCODING_YCBCR444', + 3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', + 4: 'DP_PIXEL_ENCODING_Y_ONLY', + 5: 'DP_PIXEL_ENCODING_YCBCR420', + 6: 'DP_PIXEL_ENCODING_RESERVED', +} +DP_PIXEL_ENCODING_RGB444 = 0 +DP_PIXEL_ENCODING_YCBCR422 = 1 +DP_PIXEL_ENCODING_YCBCR444 = 2 +DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3 +DP_PIXEL_ENCODING_Y_ONLY = 4 +DP_PIXEL_ENCODING_YCBCR420 = 5 +DP_PIXEL_ENCODING_RESERVED = 6 +DP_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'DP_COMPONENT_DEPTH' +DP_COMPONENT_DEPTH__enumvalues = { + 0: 'DP_COMPONENT_DEPTH_6BPC', + 1: 'DP_COMPONENT_DEPTH_8BPC', + 2: 'DP_COMPONENT_DEPTH_10BPC', + 3: 'DP_COMPONENT_DEPTH_12BPC', + 4: 'DP_COMPONENT_DEPTH_16BPC_RESERVED', + 5: 'DP_COMPONENT_DEPTH_RESERVED', +} +DP_COMPONENT_DEPTH_6BPC = 0 +DP_COMPONENT_DEPTH_8BPC = 1 +DP_COMPONENT_DEPTH_10BPC = 2 +DP_COMPONENT_DEPTH_12BPC = 3 +DP_COMPONENT_DEPTH_16BPC_RESERVED = 4 +DP_COMPONENT_DEPTH_RESERVED = 5 +DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'DP_UDI_LANES' +DP_UDI_LANES__enumvalues = { + 0: 'DP_UDI_1_LANE', + 1: 'DP_UDI_2_LANES', + 2: 'DP_UDI_LANES_RESERVED', + 3: 'DP_UDI_4_LANES', +} +DP_UDI_1_LANE = 0 +DP_UDI_2_LANES = 1 +DP_UDI_LANES_RESERVED = 2 +DP_UDI_4_LANES = 3 +DP_UDI_LANES = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DIS_DEFER' +DP_VID_STREAM_DIS_DEFER__enumvalues = { + 0: 'DP_VID_STREAM_DIS_NO_DEFER', + 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', +} +DP_VID_STREAM_DIS_NO_DEFER = 0 +DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 +DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 +DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_ACK' +DP_STEER_OVERFLOW_ACK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 +DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_MASK' +DP_STEER_OVERFLOW_MASK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_MASKED', + 1: 'DP_STEER_OVERFLOW_UNMASK', +} +DP_STEER_OVERFLOW_MASKED = 0 +DP_STEER_OVERFLOW_UNMASK = 1 +DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_TU_OVERFLOW_ACK' +DP_TU_OVERFLOW_ACK__enumvalues = { + 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 +DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' +DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { + 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', +} +DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 +DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 +DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_GEN_EN' +DP_VID_M_N_GEN_EN__enumvalues = { + 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', + 1: 'DP_VID_M_N_CALC_AUTO', +} +DP_VID_M_N_PROGRAMMED_VIA_REG = 0 +DP_VID_M_N_CALC_AUTO = 1 +DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_N_MUL' +DP_VID_N_MUL__enumvalues = { + 0: 'DP_VID_M_1X_INPUT_PIXEL_RATE', + 1: 'DP_VID_M_2X_INPUT_PIXEL_RATE', + 2: 'DP_VID_M_4X_INPUT_PIXEL_RATE', + 3: 'DP_VID_M_8X_INPUT_PIXEL_RATE', +} +DP_VID_M_1X_INPUT_PIXEL_RATE = 0 +DP_VID_M_2X_INPUT_PIXEL_RATE = 1 +DP_VID_M_4X_INPUT_PIXEL_RATE = 2 +DP_VID_M_8X_INPUT_PIXEL_RATE = 3 +DP_VID_N_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' +DP_VID_ENHANCED_FRAME_MODE__enumvalues = { + 0: 'VID_NORMAL_FRAME_MODE', + 1: 'VID_ENHANCED_MODE', +} +VID_NORMAL_FRAME_MODE = 0 +VID_ENHANCED_MODE = 1 +DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_VBID_FIELD_POL' +DP_VID_VBID_FIELD_POL__enumvalues = { + 0: 'DP_VID_VBID_FIELD_POL_NORMAL', + 1: 'DP_VID_VBID_FIELD_POL_INV', +} +DP_VID_VBID_FIELD_POL_NORMAL = 0 +DP_VID_VBID_FIELD_POL_INV = 1 +DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_ACK' +DP_VID_STREAM_DISABLE_ACK__enumvalues = { + 0: 'ID_STREAM_DISABLE_NO_ACK', + 1: 'ID_STREAM_DISABLE_ACKED', +} +ID_STREAM_DISABLE_NO_ACK = 0 +ID_STREAM_DISABLE_ACKED = 1 +DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_MASK' +DP_VID_STREAM_DISABLE_MASK__enumvalues = { + 0: 'VID_STREAM_DISABLE_MASKED', + 1: 'VID_STREAM_DISABLE_UNMASK', +} +VID_STREAM_DISABLE_MASKED = 0 +VID_STREAM_DISABLE_UNMASK = 1 +DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE0' +DPHY_ATEST_SEL_LANE0__enumvalues = { + 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE0_REG_PATTERN', +} +DPHY_ATEST_LANE0_PRBS_PATTERN = 0 +DPHY_ATEST_LANE0_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE1' +DPHY_ATEST_SEL_LANE1__enumvalues = { + 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE1_REG_PATTERN', +} +DPHY_ATEST_LANE1_PRBS_PATTERN = 0 +DPHY_ATEST_LANE1_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE2' +DPHY_ATEST_SEL_LANE2__enumvalues = { + 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE2_REG_PATTERN', +} +DPHY_ATEST_LANE2_PRBS_PATTERN = 0 +DPHY_ATEST_LANE2_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE3' +DPHY_ATEST_SEL_LANE3__enumvalues = { + 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE3_REG_PATTERN', +} +DPHY_ATEST_LANE3_PRBS_PATTERN = 0 +DPHY_ATEST_LANE3_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_BYPASS' +DPHY_BYPASS__enumvalues = { + 0: 'DPHY_8B10B_OUTPUT', + 1: 'DPHY_DBG_OUTPUT', +} +DPHY_8B10B_OUTPUT = 0 +DPHY_DBG_OUTPUT = 1 +DPHY_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SKEW_BYPASS' +DPHY_SKEW_BYPASS__enumvalues = { + 0: 'DPHY_WITH_SKEW', + 1: 'DPHY_NO_SKEW', +} +DPHY_WITH_SKEW = 0 +DPHY_NO_SKEW = 1 +DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_TRAINING_PATTERN_SEL' +DPHY_TRAINING_PATTERN_SEL__enumvalues = { + 0: 'DPHY_TRAINING_PATTERN_1', + 1: 'DPHY_TRAINING_PATTERN_2', + 2: 'DPHY_TRAINING_PATTERN_3', + 3: 'DPHY_TRAINING_PATTERN_4', +} +DPHY_TRAINING_PATTERN_1 = 0 +DPHY_TRAINING_PATTERN_2 = 1 +DPHY_TRAINING_PATTERN_3 = 2 +DPHY_TRAINING_PATTERN_4 = 3 +DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_RESET' +DPHY_8B10B_RESET__enumvalues = { + 0: 'DPHY_8B10B_NOT_RESET', + 1: 'DPHY_8B10B_RESETET', +} +DPHY_8B10B_NOT_RESET = 0 +DPHY_8B10B_RESETET = 1 +DPHY_8B10B_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_8B10B_EXT_DISP' +DP_DPHY_8B10B_EXT_DISP__enumvalues = { + 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', +} +DP_DPHY_8B10B_EXT_DISP_ZERO = 0 +DP_DPHY_8B10B_EXT_DISP_ONE = 1 +DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_CUR_DISP' +DPHY_8B10B_CUR_DISP__enumvalues = { + 0: 'DPHY_8B10B_CUR_DISP_ZERO', + 1: 'DPHY_8B10B_CUR_DISP_ONE', +} +DPHY_8B10B_CUR_DISP_ZERO = 0 +DPHY_8B10B_CUR_DISP_ONE = 1 +DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_EN' +DPHY_PRBS_EN__enumvalues = { + 0: 'DPHY_PRBS_DISABLE', + 1: 'DPHY_PRBS_ENABLE', +} +DPHY_PRBS_DISABLE = 0 +DPHY_PRBS_ENABLE = 1 +DPHY_PRBS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_SEL' +DPHY_PRBS_SEL__enumvalues = { + 0: 'DPHY_PRBS7_SELECTED', + 1: 'DPHY_PRBS23_SELECTED', + 2: 'DPHY_PRBS11_SELECTED', +} +DPHY_PRBS7_SELECTED = 0 +DPHY_PRBS23_SELECTED = 1 +DPHY_PRBS11_SELECTED = 2 +DPHY_PRBS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_FEC_ENABLE' +DPHY_FEC_ENABLE__enumvalues = { + 0: 'DPHY_FEC_DISABLED', + 1: 'DPHY_FEC_ENABLED', +} +DPHY_FEC_DISABLED = 0 +DPHY_FEC_ENABLED = 1 +DPHY_FEC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'FEC_ACTIVE_STATUS' +FEC_ACTIVE_STATUS__enumvalues = { + 0: 'DPHY_FEC_NOT_ACTIVE', + 1: 'DPHY_FEC_ACTIVE', +} +DPHY_FEC_NOT_ACTIVE = 0 +DPHY_FEC_ACTIVE = 1 +FEC_ACTIVE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_FEC_READY' +DPHY_FEC_READY__enumvalues = { + 0: 'DPHY_FEC_READY_EN', + 1: 'DPHY_FEC_READY_DIS', +} +DPHY_FEC_READY_EN = 0 +DPHY_FEC_READY_DIS = 1 +DPHY_FEC_READY = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_LOAD_BS_COUNT_START' +DPHY_LOAD_BS_COUNT_START__enumvalues = { + 0: 'DPHY_LOAD_BS_COUNT_STARTED', + 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', +} +DPHY_LOAD_BS_COUNT_STARTED = 0 +DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 +DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_EN' +DPHY_CRC_EN__enumvalues = { + 0: 'DPHY_CRC_DISABLED', + 1: 'DPHY_CRC_ENABLED', +} +DPHY_CRC_DISABLED = 0 +DPHY_CRC_ENABLED = 1 +DPHY_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_CONT_EN' +DPHY_CRC_CONT_EN__enumvalues = { + 0: 'DPHY_CRC_ONE_SHOT', + 1: 'DPHY_CRC_CONTINUOUS', +} +DPHY_CRC_ONE_SHOT = 0 +DPHY_CRC_CONTINUOUS = 1 +DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_FIELD' +DPHY_CRC_FIELD__enumvalues = { + 0: 'DPHY_CRC_START_FROM_TOP_FIELD', + 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', +} +DPHY_CRC_START_FROM_TOP_FIELD = 0 +DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 +DPHY_CRC_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_SEL' +DPHY_CRC_SEL__enumvalues = { + 0: 'DPHY_CRC_LANE0_SELECTED', + 1: 'DPHY_CRC_LANE1_SELECTED', + 2: 'DPHY_CRC_LANE2_SELECTED', + 3: 'DPHY_CRC_LANE3_SELECTED', +} +DPHY_CRC_LANE0_SELECTED = 0 +DPHY_CRC_LANE1_SELECTED = 1 +DPHY_CRC_LANE2_SELECTED = 2 +DPHY_CRC_LANE3_SELECTED = 3 +DPHY_CRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' +DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { + 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 1: 'DPHY_FAST_TRAINING_CAPABLE', +} +DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 +DPHY_FAST_TRAINING_CAPABLE = 1 +DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_COLLISION_ACK' +DP_SEC_COLLISION_ACK__enumvalues = { + 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', + 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', +} +DP_SEC_COLLISION_ACK_NO_EFFECT = 0 +DP_SEC_COLLISION_ACK_CLR_FLAG = 1 +DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_AUDIO_MUTE' +DP_SEC_AUDIO_MUTE__enumvalues = { + 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', + 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', +} +DP_SEC_AUDIO_MUTE_HW_CTRL = 0 +DP_SEC_AUDIO_MUTE_SW_CTRL = 1 +DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_TIMESTAMP_MODE' +DP_SEC_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', + 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', +} +DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 +DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 +DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_PRIORITY' +DP_SEC_ASP_PRIORITY__enumvalues = { + 0: 'DP_SEC_ASP_LOW_PRIORITY', + 1: 'DP_SEC_ASP_HIGH_PRIORITY', +} +DP_SEC_ASP_LOW_PRIORITY = 0 +DP_SEC_ASP_HIGH_PRIORITY = 1 +DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { + 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', +} +DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_UPDATE_ACT' +DP_MSE_SAT_UPDATE_ACT__enumvalues = { + 0: 'DP_MSE_SAT_UPDATE_NO_ACTION', + 1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', + 2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', +} +DP_MSE_SAT_UPDATE_NO_ACTION = 0 +DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1 +DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2 +DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_LINK_LINE' +DP_MSE_LINK_LINE__enumvalues = { + 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', + 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', + 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', + 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', +} +DP_MSE_LINK_LINE_32_MTP_LONG = 0 +DP_MSE_LINK_LINE_64_MTP_LONG = 1 +DP_MSE_LINK_LINE_128_MTP_LONG = 2 +DP_MSE_LINK_LINE_256_MTP_LONG = 3 +DP_MSE_LINK_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_BLANK_CODE' +DP_MSE_BLANK_CODE__enumvalues = { + 0: 'DP_MSE_BLANK_CODE_SF_FILLED', + 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', +} +DP_MSE_BLANK_CODE_SF_FILLED = 0 +DP_MSE_BLANK_CODE_ZERO_FILLED = 1 +DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_TIMESTAMP_MODE' +DP_MSE_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', +} +DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 +DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 +DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_ZERO_ENCODER' +DP_MSE_ZERO_ENCODER__enumvalues = { + 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', + 1: 'DP_MSE_ZERO_FE_ENCODER', +} +DP_MSE_NOT_ZERO_FE_ENCODER = 0 +DP_MSE_ZERO_FE_ENCODER = 1 +DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' +DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { + 0: 'DP_DPHY_HBR2_PASS_THROUGH', + 1: 'DP_DPHY_HBR2_PATTERN_1', + 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', + 3: 'DP_DPHY_HBR2_PATTERN_3', + 6: 'DP_DPHY_HBR2_PATTERN_2_POS', +} +DP_DPHY_HBR2_PASS_THROUGH = 0 +DP_DPHY_HBR2_PATTERN_1 = 1 +DP_DPHY_HBR2_PATTERN_2_NEG = 2 +DP_DPHY_HBR2_PATTERN_3 = 3 +DP_DPHY_HBR2_PATTERN_2_POS = 6 +DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' +DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { + 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', + 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', +} +DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 +DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 +DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SW_FAST_TRAINING_START' +DPHY_SW_FAST_TRAINING_START__enumvalues = { + 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 1: 'DPHY_SW_FAST_TRAINING_STARTED', +} +DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 +DPHY_SW_FAST_TRAINING_STARTED = 1 +DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', +} +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' +DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' +DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' +DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { + 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', + 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', +} +MSA_V_TIMING_OVERRIDE_DISABLED = 0 +MSA_V_TIMING_OVERRIDE_ENABLED = 1 +DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP0_PRIORITY' +DP_SEC_GSP0_PRIORITY__enumvalues = { + 0: 'SEC_GSP0_PRIORITY_LOW', + 1: 'SEC_GSP0_PRIORITY_HIGH', +} +SEC_GSP0_PRIORITY_LOW = 0 +SEC_GSP0_PRIORITY_HIGH = 1 +DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND' +DP_SEC_GSP_SEND__enumvalues = { + 0: 'NOT_SENT', + 1: 'FORCE_SENT', +} +NOT_SENT = 0 +FORCE_SENT = 1 +DP_SEC_GSP_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND_ANY_LINE' +DP_SEC_GSP_SEND_ANY_LINE__enumvalues = { + 0: 'SEND_AT_LINK_NUMBER', + 1: 'SEND_AT_EARLIEST_TIME', +} +SEND_AT_LINK_NUMBER = 0 +SEND_AT_EARLIEST_TIME = 1 +DP_SEC_GSP_SEND_ANY_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_LINE_REFERENCE' +DP_SEC_LINE_REFERENCE__enumvalues = { + 0: 'REFER_TO_DP_SOF', + 1: 'REFER_TO_OTG_SOF', +} +REFER_TO_DP_SOF = 0 +REFER_TO_OTG_SOF = 1 +DP_SEC_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND_PPS' +DP_SEC_GSP_SEND_PPS__enumvalues = { + 0: 'SEND_NORMAL_PACKET', + 1: 'SEND_PPS_PACKET', +} +SEND_NORMAL_PACKET = 0 +SEND_PPS_PACKET = 1 +DP_SEC_GSP_SEND_PPS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_ML_PHY_SEQ_MODE' +DP_ML_PHY_SEQ_MODE__enumvalues = { + 0: 'DP_ML_PHY_SEQ_LINE_NUM', + 1: 'DP_ML_PHY_SEQ_IMMEDIATE', +} +DP_ML_PHY_SEQ_LINE_NUM = 0 +DP_ML_PHY_SEQ_IMMEDIATE = 1 +DP_ML_PHY_SEQ_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_LINK_TRAINING_SWITCH_MODE' +DP_LINK_TRAINING_SWITCH_MODE__enumvalues = { + 0: 'DP_LINK_TRAINING_SWITCH_TO_IDLE', + 1: 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', +} +DP_LINK_TRAINING_SWITCH_TO_IDLE = 0 +DP_LINK_TRAINING_SWITCH_TO_VIDEO = 1 +DP_LINK_TRAINING_SWITCH_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DSC_MODE' +DP_DSC_MODE__enumvalues = { + 0: 'DP_DSC_DISABLE', + 1: 'DP_DSC_444_SIMPLE_422', + 2: 'DP_DSC_NATIVE_422_420', +} +DP_DSC_DISABLE = 0 +DP_DSC_444_SIMPLE_422 = 1 +DP_DSC_NATIVE_422_420 = 2 +DP_DSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_KEEPOUT_MODE' +HDMI_KEEPOUT_MODE__enumvalues = { + 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', +} +HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 +HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 +HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' +HDMI_CLOCK_CHANNEL_RATE__enumvalues = { + 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', +} +HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 +HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 +HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' +HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { + 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', + 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', +} +HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 +HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 +HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKET_GEN_VERSION' +HDMI_PACKET_GEN_VERSION__enumvalues = { + 0: 'HDMI_PACKET_GEN_VERSION_OLD', + 1: 'HDMI_PACKET_GEN_VERSION_NEW', +} +HDMI_PACKET_GEN_VERSION_OLD = 0 +HDMI_PACKET_GEN_VERSION_NEW = 1 +HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_ACK' +HDMI_ERROR_ACK__enumvalues = { + 0: 'HDMI_ERROR_ACK_INT', + 1: 'HDMI_ERROR_NOT_ACK', +} +HDMI_ERROR_ACK_INT = 0 +HDMI_ERROR_NOT_ACK = 1 +HDMI_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_MASK' +HDMI_ERROR_MASK__enumvalues = { + 0: 'HDMI_ERROR_MASK_INT', + 1: 'HDMI_ERROR_NOT_MASK', +} +HDMI_ERROR_MASK_INT = 0 +HDMI_ERROR_NOT_MASK = 1 +HDMI_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEEP_COLOR_DEPTH' +HDMI_DEEP_COLOR_DEPTH__enumvalues = { + 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', + 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 3: 'HDMI_DEEP_COLOR_DEPTH_48BPP', +} +HDMI_DEEP_COLOR_DEPTH_24BPP = 0 +HDMI_DEEP_COLOR_DEPTH_30BPP = 1 +HDMI_DEEP_COLOR_DEPTH_36BPP = 2 +HDMI_DEEP_COLOR_DEPTH_48BPP = 3 +HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_DELAY_EN' +HDMI_AUDIO_DELAY_EN__enumvalues = { + 0: 'HDMI_AUDIO_DELAY_DISABLE', + 1: 'HDMI_AUDIO_DELAY_58CLK', + 2: 'HDMI_AUDIO_DELAY_56CLK', + 3: 'HDMI_AUDIO_DELAY_RESERVED', +} +HDMI_AUDIO_DELAY_DISABLE = 0 +HDMI_AUDIO_DELAY_58CLK = 1 +HDMI_AUDIO_DELAY_56CLK = 2 +HDMI_AUDIO_DELAY_RESERVED = 3 +HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_SEND_MAX_PACKETS' +HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { + 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', +} +HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 +HDMI_SEND_MAX_AUDIO_PACKETS = 1 +HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SEND' +HDMI_ACR_SEND__enumvalues = { + 0: 'HDMI_ACR_NOT_SEND', + 1: 'HDMI_ACR_PKT_SEND', +} +HDMI_ACR_NOT_SEND = 0 +HDMI_ACR_PKT_SEND = 1 +HDMI_ACR_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_CONT' +HDMI_ACR_CONT__enumvalues = { + 0: 'HDMI_ACR_CONT_DISABLE', + 1: 'HDMI_ACR_CONT_ENABLE', +} +HDMI_ACR_CONT_DISABLE = 0 +HDMI_ACR_CONT_ENABLE = 1 +HDMI_ACR_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SELECT' +HDMI_ACR_SELECT__enumvalues = { + 0: 'HDMI_ACR_SELECT_HW', + 1: 'HDMI_ACR_SELECT_32K', + 2: 'HDMI_ACR_SELECT_44K', + 3: 'HDMI_ACR_SELECT_48K', +} +HDMI_ACR_SELECT_HW = 0 +HDMI_ACR_SELECT_32K = 1 +HDMI_ACR_SELECT_44K = 2 +HDMI_ACR_SELECT_48K = 3 +HDMI_ACR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SOURCE' +HDMI_ACR_SOURCE__enumvalues = { + 0: 'HDMI_ACR_SOURCE_HW', + 1: 'HDMI_ACR_SOURCE_SW', +} +HDMI_ACR_SOURCE_HW = 0 +HDMI_ACR_SOURCE_SW = 1 +HDMI_ACR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_N_MULTIPLE' +HDMI_ACR_N_MULTIPLE__enumvalues = { + 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', + 1: 'HDMI_ACR_1_MULTIPLE', + 2: 'HDMI_ACR_2_MULTIPLE', + 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', + 4: 'HDMI_ACR_4_MULTIPLE', + 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', + 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', + 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', +} +HDMI_ACR_0_MULTIPLE_RESERVED = 0 +HDMI_ACR_1_MULTIPLE = 1 +HDMI_ACR_2_MULTIPLE = 2 +HDMI_ACR_3_MULTIPLE_RESERVED = 3 +HDMI_ACR_4_MULTIPLE = 4 +HDMI_ACR_5_MULTIPLE_RESERVED = 5 +HDMI_ACR_6_MULTIPLE_RESERVED = 6 +HDMI_ACR_7_MULTIPLE_RESERVED = 7 +HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' +HDMI_ACR_AUDIO_PRIORITY__enumvalues = { + 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', +} +HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 +HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 +HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NULL_SEND' +HDMI_NULL_SEND__enumvalues = { + 0: 'HDMI_NULL_NOT_SEND', + 1: 'HDMI_NULL_PKT_SEND', +} +HDMI_NULL_NOT_SEND = 0 +HDMI_NULL_PKT_SEND = 1 +HDMI_NULL_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_SEND' +HDMI_GC_SEND__enumvalues = { + 0: 'HDMI_GC_NOT_SEND', + 1: 'HDMI_GC_PKT_SEND', +} +HDMI_GC_NOT_SEND = 0 +HDMI_GC_PKT_SEND = 1 +HDMI_GC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_CONT' +HDMI_GC_CONT__enumvalues = { + 0: 'HDMI_GC_CONT_DISABLE', + 1: 'HDMI_GC_CONT_ENABLE', +} +HDMI_GC_CONT_DISABLE = 0 +HDMI_GC_CONT_ENABLE = 1 +HDMI_GC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_SEND' +HDMI_ISRC_SEND__enumvalues = { + 0: 'HDMI_ISRC_NOT_SEND', + 1: 'HDMI_ISRC_PKT_SEND', +} +HDMI_ISRC_NOT_SEND = 0 +HDMI_ISRC_PKT_SEND = 1 +HDMI_ISRC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_CONT' +HDMI_ISRC_CONT__enumvalues = { + 0: 'HDMI_ISRC_CONT_DISABLE', + 1: 'HDMI_ISRC_CONT_ENABLE', +} +HDMI_ISRC_CONT_DISABLE = 0 +HDMI_ISRC_CONT_ENABLE = 1 +HDMI_ISRC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_SEND' +HDMI_AUDIO_INFO_SEND__enumvalues = { + 0: 'HDMI_AUDIO_INFO_NOT_SEND', + 1: 'HDMI_AUDIO_INFO_PKT_SEND', +} +HDMI_AUDIO_INFO_NOT_SEND = 0 +HDMI_AUDIO_INFO_PKT_SEND = 1 +HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_CONT' +HDMI_AUDIO_INFO_CONT__enumvalues = { + 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', + 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', +} +HDMI_AUDIO_INFO_CONT_DISABLE = 0 +HDMI_AUDIO_INFO_CONT_ENABLE = 1 +HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_SEND' +HDMI_MPEG_INFO_SEND__enumvalues = { + 0: 'HDMI_MPEG_INFO_NOT_SEND', + 1: 'HDMI_MPEG_INFO_PKT_SEND', +} +HDMI_MPEG_INFO_NOT_SEND = 0 +HDMI_MPEG_INFO_PKT_SEND = 1 +HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_CONT' +HDMI_MPEG_INFO_CONT__enumvalues = { + 0: 'HDMI_MPEG_INFO_CONT_DISABLE', + 1: 'HDMI_MPEG_INFO_CONT_ENABLE', +} +HDMI_MPEG_INFO_CONT_DISABLE = 0 +HDMI_MPEG_INFO_CONT_ENABLE = 1 +HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC_SEND' +HDMI_GENERIC_SEND__enumvalues = { + 0: 'HDMI_GENERIC_NOT_SEND', + 1: 'HDMI_GENERIC_PKT_SEND', +} +HDMI_GENERIC_NOT_SEND = 0 +HDMI_GENERIC_PKT_SEND = 1 +HDMI_GENERIC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC_CONT' +HDMI_GENERIC_CONT__enumvalues = { + 0: 'HDMI_GENERIC_CONT_DISABLE', + 1: 'HDMI_GENERIC_CONT_ENABLE', +} +HDMI_GENERIC_CONT_DISABLE = 0 +HDMI_GENERIC_CONT_ENABLE = 1 +HDMI_GENERIC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE_CONT' +HDMI_GC_AVMUTE_CONT__enumvalues = { + 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', + 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', +} +HDMI_GC_AVMUTE_CONT_DISABLE = 0 +HDMI_GC_AVMUTE_CONT_ENABLE = 1 +HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' +HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { + 0: 'HDMI_PACKING_PHASE_SET_BY_HW', + 1: 'HDMI_PACKING_PHASE_SET_BY_SW', +} +HDMI_PACKING_PHASE_SET_BY_HW = 0 +HDMI_PACKING_PHASE_SET_BY_SW = 1 +HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_PIXEL_ENCODING' +TMDS_PIXEL_ENCODING__enumvalues = { + 0: 'TMDS_PIXEL_ENCODING_444_OR_420', + 1: 'TMDS_PIXEL_ENCODING_422', +} +TMDS_PIXEL_ENCODING_444_OR_420 = 0 +TMDS_PIXEL_ENCODING_422 = 1 +TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_COLOR_FORMAT' +TMDS_COLOR_FORMAT__enumvalues = { + 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', + 3: 'TMDS_COLOR_FORMAT_RESERVED', +} +TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 +TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 +TMDS_COLOR_FORMAT_DUAL30BPP = 2 +TMDS_COLOR_FORMAT_RESERVED = 3 +TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' +TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { + 0: 'TMDS_STEREOSYNC_CTL0', + 1: 'TMDS_STEREOSYNC_CTL1', + 2: 'TMDS_STEREOSYNC_CTL2', + 3: 'TMDS_STEREOSYNC_CTL3', +} +TMDS_STEREOSYNC_CTL0 = 0 +TMDS_STEREOSYNC_CTL1 = 1 +TMDS_STEREOSYNC_CTL2 = 2 +TMDS_STEREOSYNC_CTL3 = 3 +TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_SEL' +TMDS_CTL0_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', +} +TMDS_CTL0_DATA_SEL0_RESERVED = 0 +TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL0_DATA_SEL2_VSYNC = 2 +TMDS_CTL0_DATA_SEL3_RESERVED = 3 +TMDS_CTL0_DATA_SEL4_HSYNC = 4 +TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 +TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 +TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_INVERT' +TMDS_CTL0_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL0_DATA_NORMAL', + 1: 'TMDS_CTL0_DATA_INVERT_EN', +} +TMDS_CTL0_DATA_NORMAL = 0 +TMDS_CTL0_DATA_INVERT_EN = 1 +TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_MODULATION' +TMDS_CTL0_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', +} +TMDS_CTL0_DATA_MODULATION_DISABLE = 0 +TMDS_CTL0_DATA_MODULATION_BIT0 = 1 +TMDS_CTL0_DATA_MODULATION_BIT1 = 2 +TMDS_CTL0_DATA_MODULATION_BIT2 = 3 +TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' +TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', +} +TMDS_CTL0_PATTERN_OUT_DISABLE = 0 +TMDS_CTL0_PATTERN_OUT_ENABLE = 1 +TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_SEL' +TMDS_CTL1_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL1_DATA_SEL0_RESERVED = 0 +TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL1_DATA_SEL2_VSYNC = 2 +TMDS_CTL1_DATA_SEL3_RESERVED = 3 +TMDS_CTL1_DATA_SEL4_HSYNC = 4 +TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_INVERT' +TMDS_CTL1_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL1_DATA_NORMAL', + 1: 'TMDS_CTL1_DATA_INVERT_EN', +} +TMDS_CTL1_DATA_NORMAL = 0 +TMDS_CTL1_DATA_INVERT_EN = 1 +TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_MODULATION' +TMDS_CTL1_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', +} +TMDS_CTL1_DATA_MODULATION_DISABLE = 0 +TMDS_CTL1_DATA_MODULATION_BIT0 = 1 +TMDS_CTL1_DATA_MODULATION_BIT1 = 2 +TMDS_CTL1_DATA_MODULATION_BIT2 = 3 +TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' +TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', +} +TMDS_CTL1_PATTERN_OUT_DISABLE = 0 +TMDS_CTL1_PATTERN_OUT_ENABLE = 1 +TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_SEL' +TMDS_CTL2_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL2_DATA_SEL0_RESERVED = 0 +TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL2_DATA_SEL2_VSYNC = 2 +TMDS_CTL2_DATA_SEL3_RESERVED = 3 +TMDS_CTL2_DATA_SEL4_HSYNC = 4 +TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_INVERT' +TMDS_CTL2_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL2_DATA_NORMAL', + 1: 'TMDS_CTL2_DATA_INVERT_EN', +} +TMDS_CTL2_DATA_NORMAL = 0 +TMDS_CTL2_DATA_INVERT_EN = 1 +TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_MODULATION' +TMDS_CTL2_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', +} +TMDS_CTL2_DATA_MODULATION_DISABLE = 0 +TMDS_CTL2_DATA_MODULATION_BIT0 = 1 +TMDS_CTL2_DATA_MODULATION_BIT1 = 2 +TMDS_CTL2_DATA_MODULATION_BIT2 = 3 +TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' +TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', +} +TMDS_CTL2_PATTERN_OUT_DISABLE = 0 +TMDS_CTL2_PATTERN_OUT_ENABLE = 1 +TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_INVERT' +TMDS_CTL3_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL3_DATA_NORMAL', + 1: 'TMDS_CTL3_DATA_INVERT_EN', +} +TMDS_CTL3_DATA_NORMAL = 0 +TMDS_CTL3_DATA_INVERT_EN = 1 +TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_MODULATION' +TMDS_CTL3_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', +} +TMDS_CTL3_DATA_MODULATION_DISABLE = 0 +TMDS_CTL3_DATA_MODULATION_BIT0 = 1 +TMDS_CTL3_DATA_MODULATION_BIT1 = 2 +TMDS_CTL3_DATA_MODULATION_BIT2 = 3 +TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' +TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', +} +TMDS_CTL3_PATTERN_OUT_DISABLE = 0 +TMDS_CTL3_PATTERN_OUT_ENABLE = 1 +TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_SEL' +TMDS_CTL3_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL3_DATA_SEL0_RESERVED = 0 +TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL3_DATA_SEL2_VSYNC = 2 +TMDS_CTL3_DATA_SEL3_RESERVED = 3 +TMDS_CTL3_DATA_SEL4_HSYNC = 4 +TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' +DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { + 0: 'DIG_FE_SOURCE_FROM_OTG0', + 1: 'DIG_FE_SOURCE_FROM_OTG1', + 2: 'DIG_FE_SOURCE_FROM_OTG2', + 3: 'DIG_FE_SOURCE_FROM_OTG3', + 4: 'DIG_FE_SOURCE_FROM_OTG4', + 5: 'DIG_FE_SOURCE_FROM_OTG5', + 6: 'DIG_FE_SOURCE_RESERVED', +} +DIG_FE_SOURCE_FROM_OTG0 = 0 +DIG_FE_SOURCE_FROM_OTG1 = 1 +DIG_FE_SOURCE_FROM_OTG2 = 2 +DIG_FE_SOURCE_FROM_OTG3 = 3 +DIG_FE_SOURCE_FROM_OTG4 = 4 +DIG_FE_SOURCE_FROM_OTG5 = 5 +DIG_FE_SOURCE_RESERVED = 6 +DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' +DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { + 0: 'DIG_FE_STEREOSYNC_FROM_OTG0', + 1: 'DIG_FE_STEREOSYNC_FROM_OTG1', + 2: 'DIG_FE_STEREOSYNC_FROM_OTG2', + 3: 'DIG_FE_STEREOSYNC_FROM_OTG3', + 4: 'DIG_FE_STEREOSYNC_FROM_OTG4', + 5: 'DIG_FE_STEREOSYNC_FROM_OTG5', + 6: 'DIG_FE_STEREOSYNC_RESERVED', +} +DIG_FE_STEREOSYNC_FROM_OTG0 = 0 +DIG_FE_STEREOSYNC_FROM_OTG1 = 1 +DIG_FE_STEREOSYNC_FROM_OTG2 = 2 +DIG_FE_STEREOSYNC_FROM_OTG3 = 3 +DIG_FE_STEREOSYNC_FROM_OTG4 = 4 +DIG_FE_STEREOSYNC_FROM_OTG5 = 5 +DIG_FE_STEREOSYNC_RESERVED = 6 +DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' +DIG_FIFO_READ_CLOCK_SRC__enumvalues = { + 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', +} +DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 +DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 +DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' +DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_ON_LINK0', + 1: 'DIG_OUTPUT_CRC_ON_LINK1', +} +DIG_OUTPUT_CRC_ON_LINK0 = 0 +DIG_OUTPUT_CRC_ON_LINK1 = 1 +DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' +DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', + 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', + 2: 'DIG_OUTPUT_CRC_FOR_VBI', + 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', +} +DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 +DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 +DIG_OUTPUT_CRC_FOR_VBI = 2 +DIG_OUTPUT_CRC_FOR_AUDIO = 3 +DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_IN_NORMAL_OPERATION', + 1: 'DIG_IN_DEBUG_MODE', +} +DIG_IN_NORMAL_OPERATION = 0 +DIG_IN_DEBUG_MODE = 1 +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { + 0: 'DIG_10BIT_TEST_PATTERN', + 1: 'DIG_ALTERNATING_TEST_PATTERN', +} +DIG_10BIT_TEST_PATTERN = 0 +DIG_ALTERNATING_TEST_PATTERN = 1 +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_NORMAL', + 1: 'DIG_TEST_PATTERN_RANDOM', +} +DIG_TEST_PATTERN_NORMAL = 0 +DIG_TEST_PATTERN_RANDOM = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_ENABLED', + 1: 'DIG_RANDOM_PATTERN_RESETED', +} +DIG_RANDOM_PATTERN_ENABLED = 0 +DIG_RANDOM_PATTERN_RESETED = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' +DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', +} +DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 +DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 +DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' +DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', +} +DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 +DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 +DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL' +DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL__enumvalues = { + 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', + 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', +} +DIG_FIFO_USE_OVERWRITE_LEVEL = 0 +DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 +DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_ERROR_ACK' +DIG_FIFO_ERROR_ACK__enumvalues = { + 0: 'DIG_FIFO_ERROR_ACK_INT', + 1: 'DIG_FIFO_ERROR_NOT_ACK', +} +DIG_FIFO_ERROR_ACK_INT = 0 +DIG_FIFO_ERROR_NOT_ACK = 1 +DIG_FIFO_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE' +DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', +} +DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 +DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 +DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX' +DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', + 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', +} +DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 +DIG_FIFO_FORCE_RECOMP_MINMAX = 1 +DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' +AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { + 0: 'AFMT_INTERRUPT_DISABLE', + 1: 'AFMT_INTERRUPT_ENABLE', +} +AFMT_INTERRUPT_DISABLE = 0 +AFMT_INTERRUPT_ENABLE = 1 +AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE' +HDMI_GC_AVMUTE__enumvalues = { + 0: 'HDMI_GC_AVMUTE_SET', + 1: 'HDMI_GC_AVMUTE_UNSET', +} +HDMI_GC_AVMUTE_SET = 0 +HDMI_GC_AVMUTE_UNSET = 1 +HDMI_GC_AVMUTE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEFAULT_PAHSE' +HDMI_DEFAULT_PAHSE__enumvalues = { + 0: 'HDMI_DEFAULT_PHASE_IS_0', + 1: 'HDMI_DEFAULT_PHASE_IS_1', +} +HDMI_DEFAULT_PHASE_IS_0 = 0 +HDMI_DEFAULT_PHASE_IS_1 = 1 +HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { + 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', +} +AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 +AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum + +# values for enumeration 'AUDIO_LAYOUT_SELECT' +AUDIO_LAYOUT_SELECT__enumvalues = { + 0: 'AUDIO_LAYOUT_0', + 1: 'AUDIO_LAYOUT_1', +} +AUDIO_LAYOUT_0 = 0 +AUDIO_LAYOUT_1 = 1 +AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' +AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { + 0: 'AFMT_AUDIO_CRC_ONESHOT', + 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', +} +AFMT_AUDIO_CRC_ONESHOT = 0 +AFMT_AUDIO_CRC_AUTO_RESTART = 1 +AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' +AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { + 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', +} +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 +AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' +AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { + 0: 'AFMT_AUDIO_CRC_CH0_SIG', + 1: 'AFMT_AUDIO_CRC_CH1_SIG', + 2: 'AFMT_AUDIO_CRC_CH2_SIG', + 3: 'AFMT_AUDIO_CRC_CH3_SIG', + 4: 'AFMT_AUDIO_CRC_CH4_SIG', + 5: 'AFMT_AUDIO_CRC_CH5_SIG', + 6: 'AFMT_AUDIO_CRC_CH6_SIG', + 7: 'AFMT_AUDIO_CRC_CH7_SIG', + 8: 'AFMT_AUDIO_CRC_RESERVED_8', + 9: 'AFMT_AUDIO_CRC_RESERVED_9', + 10: 'AFMT_AUDIO_CRC_RESERVED_10', + 11: 'AFMT_AUDIO_CRC_RESERVED_11', + 12: 'AFMT_AUDIO_CRC_RESERVED_12', + 13: 'AFMT_AUDIO_CRC_RESERVED_13', + 14: 'AFMT_AUDIO_CRC_RESERVED_14', + 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', +} +AFMT_AUDIO_CRC_CH0_SIG = 0 +AFMT_AUDIO_CRC_CH1_SIG = 1 +AFMT_AUDIO_CRC_CH2_SIG = 2 +AFMT_AUDIO_CRC_CH3_SIG = 3 +AFMT_AUDIO_CRC_CH4_SIG = 4 +AFMT_AUDIO_CRC_CH5_SIG = 5 +AFMT_AUDIO_CRC_CH6_SIG = 6 +AFMT_AUDIO_CRC_CH7_SIG = 7 +AFMT_AUDIO_CRC_RESERVED_8 = 8 +AFMT_AUDIO_CRC_RESERVED_9 = 9 +AFMT_AUDIO_CRC_RESERVED_10 = 10 +AFMT_AUDIO_CRC_RESERVED_11 = 11 +AFMT_AUDIO_CRC_RESERVED_12 = 12 +AFMT_AUDIO_CRC_RESERVED_13 = 13 +AFMT_AUDIO_CRC_RESERVED_14 = 14 +AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 +AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' +AFMT_RAMP_CONTROL0_SIGN__enumvalues = { + 0: 'AFMT_RAMP_SIGNED', + 1: 'AFMT_RAMP_UNSIGNED', +} +AFMT_RAMP_SIGNED = 0 +AFMT_RAMP_UNSIGNED = 1 +AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { + 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', +} +AFMT_AUDIO_PACKET_SENT_DISABLED = 0 +AFMT_AUDIO_PACKET_SENT_ENABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { + 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', +} +AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 +AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { + 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', +} +AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 +AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' +AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { + 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', + 6: 'AFMT_AUDIO_SRC_RESERVED', +} +AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 +AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 +AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 +AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 +AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 +AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 +AFMT_AUDIO_SRC_RESERVED = 6 +AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_MODE' +DIG_BE_CNTL_MODE__enumvalues = { + 0: 'DIG_BE_DP_SST_MODE', + 1: 'DIG_BE_RESERVED1', + 2: 'DIG_BE_TMDS_DVI_MODE', + 3: 'DIG_BE_TMDS_HDMI_MODE', + 4: 'DIG_BE_RESERVED4', + 5: 'DIG_BE_DP_MST_MODE', + 6: 'DIG_BE_RESERVED2', + 7: 'DIG_BE_RESERVED3', +} +DIG_BE_DP_SST_MODE = 0 +DIG_BE_RESERVED1 = 1 +DIG_BE_TMDS_DVI_MODE = 2 +DIG_BE_TMDS_HDMI_MODE = 3 +DIG_BE_RESERVED4 = 4 +DIG_BE_DP_MST_MODE = 5 +DIG_BE_RESERVED2 = 6 +DIG_BE_RESERVED3 = 7 +DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_HPD_SELECT' +DIG_BE_CNTL_HPD_SELECT__enumvalues = { + 0: 'DIG_BE_CNTL_HPD1', + 1: 'DIG_BE_CNTL_HPD2', + 2: 'DIG_BE_CNTL_HPD3', + 3: 'DIG_BE_CNTL_HPD4', + 4: 'DIG_BE_CNTL_HPD5', + 5: 'DIG_BE_CNTL_HPD6', + 6: 'DIG_BE_CNTL_NO_HPD', +} +DIG_BE_CNTL_HPD1 = 0 +DIG_BE_CNTL_HPD2 = 1 +DIG_BE_CNTL_HPD3 = 2 +DIG_BE_CNTL_HPD4 = 3 +DIG_BE_CNTL_HPD5 = 4 +DIG_BE_CNTL_HPD6 = 5 +DIG_BE_CNTL_NO_HPD = 6 +DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', +} +LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 +LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_SYNC_PHASE' +TMDS_SYNC_PHASE__enumvalues = { + 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', + 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', +} +TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 +TMDS_SYNC_PHASE_ON_FRAME_START = 1 +TMDS_SYNC_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' +TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { + 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', +} +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', +} +TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' +TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' +TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', +} +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', +} +TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 +TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', + 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 +TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 +TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', +} +TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 +TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' +TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', +} +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 +TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 +TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' +TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', + 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', +} +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 +TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 +TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_VBI_GSP_INDEX' +AFMT_VBI_GSP_INDEX__enumvalues = { + 0: 'AFMT_VBI_GSP0_INDEX', + 1: 'AFMT_VBI_GSP1_INDEX', + 2: 'AFMT_VBI_GSP2_INDEX', + 3: 'AFMT_VBI_GSP3_INDEX', + 4: 'AFMT_VBI_GSP4_INDEX', + 5: 'AFMT_VBI_GSP5_INDEX', + 6: 'AFMT_VBI_GSP6_INDEX', + 7: 'AFMT_VBI_GSP7_INDEX', + 8: 'AFMT_VBI_GSP8_INDEX', + 9: 'AFMT_VBI_GSP9_INDEX', + 10: 'AFMT_VBI_GSP10_INDEX', +} +AFMT_VBI_GSP0_INDEX = 0 +AFMT_VBI_GSP1_INDEX = 1 +AFMT_VBI_GSP2_INDEX = 2 +AFMT_VBI_GSP3_INDEX = 3 +AFMT_VBI_GSP4_INDEX = 4 +AFMT_VBI_GSP5_INDEX = 5 +AFMT_VBI_GSP6_INDEX = 6 +AFMT_VBI_GSP7_INDEX = 7 +AFMT_VBI_GSP8_INDEX = 8 +AFMT_VBI_GSP9_INDEX = 9 +AFMT_VBI_GSP10_INDEX = 10 +AFMT_VBI_GSP_INDEX = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_DIGITAL_BYPASS_SEL' +DIG_DIGITAL_BYPASS_SEL__enumvalues = { + 0: 'DIG_DIGITAL_BYPASS_SEL_BYPASS', + 1: 'DIG_DIGITAL_BYPASS_SEL_36BPP', + 2: 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', + 3: 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', + 4: 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', + 5: 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', + 6: 'DIG_DIGITAL_BYPASS_SEL_ALPHA', +} +DIG_DIGITAL_BYPASS_SEL_BYPASS = 0 +DIG_DIGITAL_BYPASS_SEL_36BPP = 1 +DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 2 +DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 3 +DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 4 +DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 5 +DIG_DIGITAL_BYPASS_SEL_ALPHA = 6 +DIG_DIGITAL_BYPASS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_INPUT_PIXEL_SEL' +DIG_INPUT_PIXEL_SEL__enumvalues = { + 0: 'DIG_ALL_PIXEL', + 1: 'DIG_EVEN_PIXEL_ONLY', + 2: 'DIG_ODD_PIXEL_ONLY', +} +DIG_ALL_PIXEL = 0 +DIG_EVEN_PIXEL_ONLY = 1 +DIG_ODD_PIXEL_ONLY = 2 +DIG_INPUT_PIXEL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOLBY_VISION_ENABLE' +DOLBY_VISION_ENABLE__enumvalues = { + 0: 'DOLBY_VISION_ENABLED', + 1: 'DOLBY_VISION_DISABLED', +} +DOLBY_VISION_ENABLED = 0 +DOLBY_VISION_DISABLED = 1 +DOLBY_VISION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'METADATA_HUBP_SEL' +METADATA_HUBP_SEL__enumvalues = { + 0: 'METADATA_HUBP_SEL_0', + 1: 'METADATA_HUBP_SEL_1', + 2: 'METADATA_HUBP_SEL_2', + 3: 'METADATA_HUBP_SEL_3', + 4: 'METADATA_HUBP_SEL_4', + 5: 'METADATA_HUBP_SEL_5', + 6: 'METADATA_HUBP_SEL_RESERVED', +} +METADATA_HUBP_SEL_0 = 0 +METADATA_HUBP_SEL_1 = 1 +METADATA_HUBP_SEL_2 = 2 +METADATA_HUBP_SEL_3 = 3 +METADATA_HUBP_SEL_4 = 4 +METADATA_HUBP_SEL_5 = 5 +METADATA_HUBP_SEL_RESERVED = 6 +METADATA_HUBP_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'METADATA_STREAM_TYPE_SEL' +METADATA_STREAM_TYPE_SEL__enumvalues = { + 0: 'METADATA_STREAM_DP', + 1: 'METADATA_STREAM_DVE', +} +METADATA_STREAM_DP = 0 +METADATA_STREAM_DVE = 1 +METADATA_STREAM_TYPE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_METADATA_ENABLE' +HDMI_METADATA_ENABLE__enumvalues = { + 0: 'HDMI_METADATA_NOT_SEND', + 1: 'HDMI_METADATA_PKT_SEND', +} +HDMI_METADATA_NOT_SEND = 0 +HDMI_METADATA_PKT_SEND = 1 +HDMI_METADATA_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKET_LINE_REFERENCE' +HDMI_PACKET_LINE_REFERENCE__enumvalues = { + 0: 'HDMI_PKT_LINE_REF_VSYNC', + 1: 'HDMI_PKT_LINE_REF_OTGSOF', +} +HDMI_PKT_LINE_REF_VSYNC = 0 +HDMI_PKT_LINE_REF_OTGSOF = 1 +HDMI_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_HPD_SEL' +DP_AUX_CONTROL_HPD_SEL__enumvalues = { + 0: 'DP_AUX_CONTROL_HPD1_SELECTED', + 1: 'DP_AUX_CONTROL_HPD2_SELECTED', + 2: 'DP_AUX_CONTROL_HPD3_SELECTED', + 3: 'DP_AUX_CONTROL_HPD4_SELECTED', + 4: 'DP_AUX_CONTROL_HPD5_SELECTED', + 5: 'DP_AUX_CONTROL_HPD6_SELECTED', + 6: 'DP_AUX_CONTROL_NO_HPD_SELECTED', +} +DP_AUX_CONTROL_HPD1_SELECTED = 0 +DP_AUX_CONTROL_HPD2_SELECTED = 1 +DP_AUX_CONTROL_HPD3_SELECTED = 2 +DP_AUX_CONTROL_HPD4_SELECTED = 3 +DP_AUX_CONTROL_HPD5_SELECTED = 4 +DP_AUX_CONTROL_HPD6_SELECTED = 5 +DP_AUX_CONTROL_NO_HPD_SELECTED = 6 +DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_TEST_MODE' +DP_AUX_CONTROL_TEST_MODE__enumvalues = { + 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', +} +DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 +DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 +DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' +DP_AUX_SW_CONTROL_SW_GO__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 1: 'DP_AUX_SW_CONTROL_SW__GO', +} +DP_AUX_SW_CONTROL_SW__NOT_GO = 0 +DP_AUX_SW_CONTROL_SW__GO = 1 +DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' +DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', +} +DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 +DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 +DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' +DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', +} +DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 +DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', +} +DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 +DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', +} +DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 +DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_INT_ACK' +DP_AUX_INT_ACK__enumvalues = { + 0: 'DP_AUX_INT__NOT_ACK', + 1: 'DP_AUX_INT__ACK', +} +DP_AUX_INT__NOT_ACK = 0 +DP_AUX_INT__ACK = 1 +DP_AUX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_LS_UPDATE_ACK' +DP_AUX_LS_UPDATE_ACK__enumvalues = { + 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', + 1: 'DP_AUX_INT_LS_UPDATE_ACK', +} +DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 +DP_AUX_INT_LS_UPDATE_ACK = 1 +DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { + 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', +} +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', +} +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', +} +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RX_TIMEOUT_LEN_MUL' +DP_AUX_RX_TIMEOUT_LEN_MUL__enumvalues = { + 0: 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', + 1: 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', + 2: 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', + 3: 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', +} +DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0 +DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 1 +DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 2 +DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 3 +DP_AUX_RX_TIMEOUT_LEN_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_TX_PRECHARGE_LEN_MUL' +DP_AUX_TX_PRECHARGE_LEN_MUL__enumvalues = { + 0: 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', + 1: 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', + 2: 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', + 3: 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', +} +DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0 +DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 1 +DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 2 +DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 3 +DP_AUX_TX_PRECHARGE_LEN_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { + 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', +} +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', +} +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', +} +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', +} +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', +} +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' +DP_AUX_ERR_OCCURRED_ACK__enumvalues = { + 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 1: 'DP_AUX_ERR_OCCURRED__ACK', +} +DP_AUX_ERR_OCCURRED__NOT_ACK = 0 +DP_AUX_ERR_OCCURRED__ACK = 1 +DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' +DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { + 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', + 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', +} +DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 +DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 +DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' +DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { + 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', + 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', +} +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 +DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET' +DP_AUX_RESET__enumvalues = { + 0: 'DP_AUX_RESET_DEASSERTED', + 1: 'DP_AUX_RESET_ASSERTED', +} +DP_AUX_RESET_DEASSERTED = 0 +DP_AUX_RESET_ASSERTED = 1 +DP_AUX_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET_DONE' +DP_AUX_RESET_DONE__enumvalues = { + 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', + 1: 'DP_AUX_RESET_SEQUENCE_DONE', +} +DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 +DP_AUX_RESET_SEQUENCE_DONE = 1 +DP_AUX_RESET_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_PHY_WAKE_PRIORITY' +DP_AUX_PHY_WAKE_PRIORITY__enumvalues = { + 0: 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', + 1: 'DP_AUX_PHY_WAKE_LOW_PRIORITY', +} +DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0 +DP_AUX_PHY_WAKE_LOW_PRIORITY = 1 +DP_AUX_PHY_WAKE_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_GO' +DOUT_I2C_CONTROL_GO__enumvalues = { + 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 1: 'DOUT_I2C_CONTROL_START_TRANSFER', +} +DOUT_I2C_CONTROL_STOP_TRANSFER = 0 +DOUT_I2C_CONTROL_START_TRANSFER = 1 +DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' +DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', +} +DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 +DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 +DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' +DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 1: 'DOUT_I2C_CONTROL__SEND_RESET', +} +DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 +DOUT_I2C_CONTROL__SEND_RESET = 1 +DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH' +DOUT_I2C_CONTROL_SEND_RESET_LENGTH__enumvalues = { + 0: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', + 1: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', +} +DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0 +DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 1 +DOUT_I2C_CONTROL_SEND_RESET_LENGTH = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' +DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', +} +DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 +DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 +DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' +DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', + 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', + 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', + 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', + 4: 'DOUT_I2C_CONTROL_SELECT_DDC5', + 5: 'DOUT_I2C_CONTROL_SELECT_DDC6', + 6: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', +} +DOUT_I2C_CONTROL_SELECT_DDC1 = 0 +DOUT_I2C_CONTROL_SELECT_DDC2 = 1 +DOUT_I2C_CONTROL_SELECT_DDC3 = 2 +DOUT_I2C_CONTROL_SELECT_DDC4 = 3 +DOUT_I2C_CONTROL_SELECT_DDC5 = 4 +DOUT_I2C_CONTROL_SELECT_DDC6 = 5 +DOUT_I2C_CONTROL_SELECT_DDCVGA = 6 +DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' +DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_TRANS0', + 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', +} +DOUT_I2C_CONTROL_TRANS0 = 0 +DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 +DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' +DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', +} +DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 +DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 +DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 +DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 +DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', +} +DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 +DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' +DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', +} +DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 +DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 +DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', +} +DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 +DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', +} +DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 +DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ACK' +DOUT_I2C_ACK__enumvalues = { + 0: 'DOUT_I2C_NO_ACK', + 1: 'DOUT_I2C_ACK_TO_CLEAN', +} +DOUT_I2C_NO_ACK = 0 +DOUT_I2C_ACK_TO_CLEAN = 1 +DOUT_I2C_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' +DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { + 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', +} +DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 +DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 +DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 +DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 +DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', +} +DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 +DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_EDID_DETECT_STATUS' +DOUT_I2C_DDC_EDID_DETECT_STATUS__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED', + 1: 'DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED', +} +DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED = 0 +DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED = 1 +DOUT_I2C_DDC_EDID_DETECT_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', +} +DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' +DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { + 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', +} +DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 +DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 +DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' +DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { + 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 1: 'DOUT_I2C_DATA__INDEX_WRITE', +} +DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 +DOUT_I2C_DATA__INDEX_WRITE = 1 +DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', +} +DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 +DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { + 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', +} +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_FORCE_CTRL' +DIOMEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'DIOMEM_NO_FORCE_REQUEST', + 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', +} +DIOMEM_NO_FORCE_REQUEST = 0 +DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 2 +DIOMEM_FORCE_SHUT_DOWN_REQUEST = 3 +DIOMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_FORCE_CTRL2' +DIOMEM_PWR_FORCE_CTRL2__enumvalues = { + 0: 'DIOMEM_NO_FORCE_REQ', + 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', +} +DIOMEM_NO_FORCE_REQ = 0 +DIOMEM_FORCE_LIGHT_SLEEP_REQ = 1 +DIOMEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_DIS_CTRL' +DIOMEM_PWR_DIS_CTRL__enumvalues = { + 0: 'DIOMEM_ENABLE_MEM_PWR_CTRL', + 1: 'DIOMEM_DISABLE_MEM_PWR_CTRL', +} +DIOMEM_ENABLE_MEM_PWR_CTRL = 0 +DIOMEM_DISABLE_MEM_PWR_CTRL = 1 +DIOMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_GATING_EN' +CLOCK_GATING_EN__enumvalues = { + 0: 'CLOCK_GATING_ENABLE', + 1: 'CLOCK_GATING_DISABLE', +} +CLOCK_GATING_ENABLE = 0 +CLOCK_GATING_DISABLE = 1 +CLOCK_GATING_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_SEL_CTRL' +DIOMEM_PWR_SEL_CTRL__enumvalues = { + 0: 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', + 1: 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', + 2: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', +} +DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0 +DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 1 +DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 2 +DIOMEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_SEL_CTRL2' +DIOMEM_PWR_SEL_CTRL2__enumvalues = { + 0: 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', + 1: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', +} +DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0 +DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 1 +DIOMEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'PM_ASSERT_RESET' +PM_ASSERT_RESET__enumvalues = { + 0: 'PM_ASSERT_RESET_0', + 1: 'PM_ASSERT_RESET_1', +} +PM_ASSERT_RESET_0 = 0 +PM_ASSERT_RESET_1 = 1 +PM_ASSERT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DAC_MUX_SELECT' +DAC_MUX_SELECT__enumvalues = { + 0: 'DAC_MUX_SELECT_DACA', + 1: 'DAC_MUX_SELECT_DACB', +} +DAC_MUX_SELECT_DACA = 0 +DAC_MUX_SELECT_DACB = 1 +DAC_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_MUX_SELECT' +TMDS_MUX_SELECT__enumvalues = { + 0: 'TMDS_MUX_SELECT_B', + 1: 'TMDS_MUX_SELECT_G', + 2: 'TMDS_MUX_SELECT_R', + 3: 'TMDS_MUX_SELECT_RESERVED', +} +TMDS_MUX_SELECT_B = 0 +TMDS_MUX_SELECT_G = 1 +TMDS_MUX_SELECT_R = 2 +TMDS_MUX_SELECT_RESERVED = 3 +TMDS_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SOFT_RESET' +SOFT_RESET__enumvalues = { + 0: 'SOFT_RESET_0', + 1: 'SOFT_RESET_1', +} +SOFT_RESET_0 = 0 +SOFT_RESET_1 = 1 +SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_STEREOSYNC_SEL' +GENERIC_STEREOSYNC_SEL__enumvalues = { + 0: 'GENERIC_STEREOSYNC_SEL_D1', + 1: 'GENERIC_STEREOSYNC_SEL_D2', + 2: 'GENERIC_STEREOSYNC_SEL_D3', + 3: 'GENERIC_STEREOSYNC_SEL_D4', + 4: 'GENERIC_STEREOSYNC_SEL_D5', + 5: 'GENERIC_STEREOSYNC_SEL_D6', + 6: 'GENERIC_STEREOSYNC_SEL_RESERVED', +} +GENERIC_STEREOSYNC_SEL_D1 = 0 +GENERIC_STEREOSYNC_SEL_D2 = 1 +GENERIC_STEREOSYNC_SEL_D3 = 2 +GENERIC_STEREOSYNC_SEL_D4 = 3 +GENERIC_STEREOSYNC_SEL_D5 = 4 +GENERIC_STEREOSYNC_SEL_D6 = 5 +GENERIC_STEREOSYNC_SEL_RESERVED = 6 +GENERIC_STEREOSYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE' +DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { + 0: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 1: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', +} +DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 +DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 +DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE' +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE__enumvalues = { + 0: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', + 1: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', +} +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0 +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 1 +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICA_SEL' +DCIO_DC_GENERICA_SEL__enumvalues = { + 0: 'DCIO_GENERICA_SEL_DACA_STEREOSYNC', + 1: 'DCIO_GENERICA_SEL_STEREOSYNC', + 2: 'DCIO_GENERICA_SEL_DACA_PIXCLK', + 3: 'DCIO_GENERICA_SEL_DACB_PIXCLK', + 4: 'DCIO_GENERICA_SEL_DVOA_CTL3', + 5: 'DCIO_GENERICA_SEL_P1_PLLCLK', + 6: 'DCIO_GENERICA_SEL_P2_PLLCLK', + 7: 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC', + 8: 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER', + 9: 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER', + 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', + 11: 'DCIO_GENERICA_SEL_SYNCEN', + 12: 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK', + 13: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK', + 14: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK', + 15: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2', + 16: 'DCIO_GENERICA_SEL_GENERICA_DPRX', + 17: 'DCIO_GENERICA_SEL_GENERICB_DPRX', +} +DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0 +DCIO_GENERICA_SEL_STEREOSYNC = 1 +DCIO_GENERICA_SEL_DACA_PIXCLK = 2 +DCIO_GENERICA_SEL_DACB_PIXCLK = 3 +DCIO_GENERICA_SEL_DVOA_CTL3 = 4 +DCIO_GENERICA_SEL_P1_PLLCLK = 5 +DCIO_GENERICA_SEL_P2_PLLCLK = 6 +DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 7 +DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 8 +DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 9 +DCIO_GENERICA_SEL_GENERICA_DCCG = 10 +DCIO_GENERICA_SEL_SYNCEN = 11 +DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 12 +DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 13 +DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 14 +DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15 +DCIO_GENERICA_SEL_GENERICA_DPRX = 16 +DCIO_GENERICA_SEL_GENERICB_DPRX = 17 +DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', + 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', + 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', + 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', + 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', + 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', + 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', +} +DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 +DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 +DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 +DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 +DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 +DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 +DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_CLK', +} +DCIO_UNIPHYA_FBDIV_CLK = 0 +DCIO_UNIPHYB_FBDIV_CLK = 1 +DCIO_UNIPHYC_FBDIV_CLK = 2 +DCIO_UNIPHYD_FBDIV_CLK = 3 +DCIO_UNIPHYE_FBDIV_CLK = 4 +DCIO_UNIPHYF_FBDIV_CLK = 5 +DCIO_UNIPHYG_FBDIV_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', +} +DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 +DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 +DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 +DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 +DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 +DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 +DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', +} +DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 +DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 +DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 +DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 +DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 +DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 +DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICB_SEL' +DCIO_DC_GENERICB_SEL__enumvalues = { + 0: 'DCIO_GENERICB_SEL_DACA_STEREOSYNC', + 1: 'DCIO_GENERICB_SEL_STEREOSYNC', + 2: 'DCIO_GENERICB_SEL_DACA_PIXCLK', + 3: 'DCIO_GENERICB_SEL_DACB_PIXCLK', + 4: 'DCIO_GENERICB_SEL_DVOA_CTL3', + 5: 'DCIO_GENERICB_SEL_P1_PLLCLK', + 6: 'DCIO_GENERICB_SEL_P2_PLLCLK', + 7: 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC', + 8: 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER', + 9: 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER', + 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', + 11: 'DCIO_GENERICB_SEL_SYNCEN', + 12: 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', + 13: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK', + 14: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK', + 15: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2', +} +DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0 +DCIO_GENERICB_SEL_STEREOSYNC = 1 +DCIO_GENERICB_SEL_DACA_PIXCLK = 2 +DCIO_GENERICB_SEL_DACB_PIXCLK = 3 +DCIO_GENERICB_SEL_DVOA_CTL3 = 4 +DCIO_GENERICB_SEL_P1_PLLCLK = 5 +DCIO_GENERICB_SEL_P2_PLLCLK = 6 +DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 7 +DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 8 +DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 9 +DCIO_GENERICB_SEL_GENERICB_DCCG = 10 +DCIO_GENERICB_SEL_SYNCEN = 11 +DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 12 +DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 13 +DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 14 +DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15 +DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', + 1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', + 2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', + 3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', +} +DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0 +DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1 +DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2 +DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3 +DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', +} +DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 +DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION' +DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION__enumvalues = { + 0: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS', + 1: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS', + 2: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS', + 3: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS', + 4: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS', + 5: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS', + 6: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS', + 7: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS', +} +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 1 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 2 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 3 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 4 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 5 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 6 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 7 +DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', +} +DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 +DCIO_UNIPHY_CHANNEL_INVERTED = 1 +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { + 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', + 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', +} +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', +} +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN' +DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN__enumvalues = { + 0: 'DCIO_VIP_MUX_EN_DVO', + 1: 'DCIO_VIP_MUX_EN_VIP', +} +DCIO_VIP_MUX_EN_DVO = 0 +DCIO_VIP_MUX_EN_VIP = 1 +DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN' +DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN__enumvalues = { + 0: 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', + 1: 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE', +} +DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0 +DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 1 +DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN' +DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN__enumvalues = { + 0: 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', + 1: 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE', +} +DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0 +DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 1 +DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN' +DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN__enumvalues = { + 0: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE', + 1: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE', +} +DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0 +DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 1 +DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE' +DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { + 0: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF', + 1: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON', +} +DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0 +DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 1 +DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL__enumvalues = { + 0: 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT', + 1: 'DCIO_LVTMA_SYNCEN_POL_INVERT', +} +DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0 +DCIO_LVTMA_SYNCEN_POL_INVERT = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON__enumvalues = { + 0: 'DCIO_LVTMA_DIGON_OFF', + 1: 'DCIO_LVTMA_DIGON_ON', +} +DCIO_LVTMA_DIGON_OFF = 0 +DCIO_LVTMA_DIGON_ON = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL__enumvalues = { + 0: 'DCIO_LVTMA_DIGON_POL_NON_INVERT', + 1: 'DCIO_LVTMA_DIGON_POL_INVERT', +} +DCIO_LVTMA_DIGON_POL_NON_INVERT = 0 +DCIO_LVTMA_DIGON_POL_INVERT = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON__enumvalues = { + 0: 'DCIO_LVTMA_BLON_OFF', + 1: 'DCIO_LVTMA_BLON_ON', +} +DCIO_LVTMA_BLON_OFF = 0 +DCIO_LVTMA_BLON_ON = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL__enumvalues = { + 0: 'DCIO_LVTMA_BLON_POL_NON_INVERT', + 1: 'DCIO_LVTMA_BLON_POL_INVERT', +} +DCIO_LVTMA_BLON_POL_NON_INVERT = 0 +DCIO_LVTMA_BLON_POL_INVERT = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN' +DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN__enumvalues = { + 0: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON', + 1: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE', +} +DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0 +DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 1 +DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' +DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { + 0: 'DCIO_BL_PWM_FRACTIONAL_DISABLE', + 1: 'DCIO_BL_PWM_FRACTIONAL_ENABLE', +} +DCIO_BL_PWM_FRACTIONAL_DISABLE = 0 +DCIO_BL_PWM_FRACTIONAL_ENABLE = 1 +DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_EN' +DCIO_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { + 0: 'DCIO_BL_PWM_DISABLE', + 1: 'DCIO_BL_PWM_ENABLE', +} +DCIO_BL_PWM_DISABLE = 0 +DCIO_BL_PWM_ENABLE = 1 +DCIO_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' +DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { + 0: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 1: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE', +} +DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 +DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 +DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN' +DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__enumvalues = { + 0: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL', + 1: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM', +} +DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0 +DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 1 +DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_REG_LOCK' +DCIO_BL_PWM_GRP1_REG_LOCK__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE', + 1: 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE', +} +DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 +DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 +DCIO_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START' +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 1: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', +} +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', +} +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 1: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', +} +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 1: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', +} +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL_SEL' +DCIO_GSL_SEL__enumvalues = { + 0: 'DCIO_GSL_SEL_GROUP_0', + 1: 'DCIO_GSL_SEL_GROUP_1', + 2: 'DCIO_GSL_SEL_GROUP_2', +} +DCIO_GSL_SEL_GROUP_0 = 0 +DCIO_GSL_SEL_GROUP_1 = 1 +DCIO_GSL_SEL_GROUP_2 = 2 +DCIO_GSL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' +DCIO_GENLK_CLK_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', + 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', +} +DCIO_GENLK_CLK_GSL_MASK_NO = 0 +DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 +DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 +DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' +DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', +} +DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 +DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 +DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 +DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' +DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' +DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' +DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { + 0: 'DCIO_GPU_TIMER_START_0_END_27', + 1: 'DCIO_GPU_TIMER_START_1_END_28', + 2: 'DCIO_GPU_TIMER_START_2_END_29', + 3: 'DCIO_GPU_TIMER_START_3_END_30', + 4: 'DCIO_GPU_TIMER_START_4_END_31', + 5: 'DCIO_GPU_TIMER_START_6_END_33', + 6: 'DCIO_GPU_TIMER_START_8_END_35', + 7: 'DCIO_GPU_TIMER_START_10_END_37', +} +DCIO_GPU_TIMER_START_0_END_27 = 0 +DCIO_GPU_TIMER_START_1_END_28 = 1 +DCIO_GPU_TIMER_START_2_END_29 = 2 +DCIO_GPU_TIMER_START_3_END_30 = 3 +DCIO_GPU_TIMER_START_4_END_31 = 4 +DCIO_GPU_TIMER_START_6_END_33 = 5 +DCIO_GPU_TIMER_START_8_END_35 = 6 +DCIO_GPU_TIMER_START_10_END_37 = 7 +DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { + 0: 'DCIO_TEST_CLK_SEL_DISPCLK', + 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', + 2: 'DCIO_TEST_CLK_SEL_SOCCLK', +} +DCIO_TEST_CLK_SEL_DISPCLK = 0 +DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 +DCIO_TEST_CLK_SEL_SOCCLK = 2 +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { + 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', +} +DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 +DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DIO_OTG_EXT_VSYNC_MUX' +DCIO_DIO_OTG_EXT_VSYNC_MUX__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 1: 'DCIO_EXT_VSYNC_MUX_OTG0', + 2: 'DCIO_EXT_VSYNC_MUX_OTG1', + 3: 'DCIO_EXT_VSYNC_MUX_OTG2', + 4: 'DCIO_EXT_VSYNC_MUX_OTG3', + 5: 'DCIO_EXT_VSYNC_MUX_OTG4', + 6: 'DCIO_EXT_VSYNC_MUX_OTG5', + 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', +} +DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 +DCIO_EXT_VSYNC_MUX_OTG0 = 1 +DCIO_EXT_VSYNC_MUX_OTG1 = 2 +DCIO_EXT_VSYNC_MUX_OTG2 = 3 +DCIO_EXT_VSYNC_MUX_OTG3 = 4 +DCIO_EXT_VSYNC_MUX_OTG4 = 5 +DCIO_EXT_VSYNC_MUX_OTG5 = 6 +DCIO_EXT_VSYNC_MUX_GENERICB = 7 +DCIO_DIO_OTG_EXT_VSYNC_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DIO_EXT_VSYNC_MASK' +DCIO_DIO_EXT_VSYNC_MASK__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MASK_NONE', + 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', + 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', + 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', + 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', + 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', + 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', + 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', +} +DCIO_EXT_VSYNC_MASK_NONE = 0 +DCIO_EXT_VSYNC_MASK_PIPE0 = 1 +DCIO_EXT_VSYNC_MASK_PIPE1 = 2 +DCIO_EXT_VSYNC_MASK_PIPE2 = 3 +DCIO_EXT_VSYNC_MASK_PIPE3 = 4 +DCIO_EXT_VSYNC_MASK_PIPE4 = 5 +DCIO_EXT_VSYNC_MASK_PIPE5 = 6 +DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 +DCIO_DIO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DSYNC_SOFT_RESET' +DCIO_DSYNC_SOFT_RESET__enumvalues = { + 0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT', + 1: 'DCIO_DSYNC_SOFT_RESET_ASSERT', +} +DCIO_DSYNC_SOFT_RESET_DEASSERT = 0 +DCIO_DSYNC_SOFT_RESET_ASSERT = 1 +DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DACA_SOFT_RESET' +DCIO_DACA_SOFT_RESET__enumvalues = { + 0: 'DCIO_DACA_SOFT_RESET_DEASSERT', + 1: 'DCIO_DACA_SOFT_RESET_ASSERT', +} +DCIO_DACA_SOFT_RESET_DEASSERT = 0 +DCIO_DACA_SOFT_RESET_ASSERT = 1 +DCIO_DACA_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' +DCIO_DCRXPHY_SOFT_RESET__enumvalues = { + 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', + 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', +} +DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 +DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 +DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPHY_LANE_SEL' +DCIO_DPHY_LANE_SEL__enumvalues = { + 0: 'DCIO_DPHY_LANE_SEL_LANE0', + 1: 'DCIO_DPHY_LANE_SEL_LANE1', + 2: 'DCIO_DPHY_LANE_SEL_LANE2', + 3: 'DCIO_DPHY_LANE_SEL_LANE3', +} +DCIO_DPHY_LANE_SEL_LANE0 = 0 +DCIO_DPHY_LANE_SEL_LANE1 = 1 +DCIO_DPHY_LANE_SEL_LANE2 = 2 +DCIO_DPHY_LANE_SEL_LANE3 = 3 +DCIO_DPHY_LANE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' +DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', +} +DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 +DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 +DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' +DCIO_DPCS_INTERRUPT_MASK__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_DISABLE', + 1: 'DCIO_DPCS_INTERRUPT_ENABLE', +} +DCIO_DPCS_INTERRUPT_DISABLE = 0 +DCIO_DPCS_INTERRUPT_ENABLE = 1 +DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' +DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { + 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', +} +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 2 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 3 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 4 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 5 +DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_IMPCAL_STEP_DELAY' +DCIO_IMPCAL_STEP_DELAY__enumvalues = { + 0: 'DCIO_IMPCAL_STEP_DELAY_1us', + 1: 'DCIO_IMPCAL_STEP_DELAY_2us', + 2: 'DCIO_IMPCAL_STEP_DELAY_3us', + 3: 'DCIO_IMPCAL_STEP_DELAY_4us', + 4: 'DCIO_IMPCAL_STEP_DELAY_5us', + 5: 'DCIO_IMPCAL_STEP_DELAY_6us', + 6: 'DCIO_IMPCAL_STEP_DELAY_7us', + 7: 'DCIO_IMPCAL_STEP_DELAY_8us', + 8: 'DCIO_IMPCAL_STEP_DELAY_9us', + 9: 'DCIO_IMPCAL_STEP_DELAY_10us', + 10: 'DCIO_IMPCAL_STEP_DELAY_11us', + 11: 'DCIO_IMPCAL_STEP_DELAY_12us', + 12: 'DCIO_IMPCAL_STEP_DELAY_13us', + 13: 'DCIO_IMPCAL_STEP_DELAY_14us', + 14: 'DCIO_IMPCAL_STEP_DELAY_15us', + 15: 'DCIO_IMPCAL_STEP_DELAY_16us', +} +DCIO_IMPCAL_STEP_DELAY_1us = 0 +DCIO_IMPCAL_STEP_DELAY_2us = 1 +DCIO_IMPCAL_STEP_DELAY_3us = 2 +DCIO_IMPCAL_STEP_DELAY_4us = 3 +DCIO_IMPCAL_STEP_DELAY_5us = 4 +DCIO_IMPCAL_STEP_DELAY_6us = 5 +DCIO_IMPCAL_STEP_DELAY_7us = 6 +DCIO_IMPCAL_STEP_DELAY_8us = 7 +DCIO_IMPCAL_STEP_DELAY_9us = 8 +DCIO_IMPCAL_STEP_DELAY_10us = 9 +DCIO_IMPCAL_STEP_DELAY_11us = 10 +DCIO_IMPCAL_STEP_DELAY_12us = 11 +DCIO_IMPCAL_STEP_DELAY_13us = 12 +DCIO_IMPCAL_STEP_DELAY_14us = 13 +DCIO_IMPCAL_STEP_DELAY_15us = 14 +DCIO_IMPCAL_STEP_DELAY_16us = 15 +DCIO_IMPCAL_STEP_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' +DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { + 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', +} +DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 +DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 +DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_HPD_SEL' +DCIOCHIP_HPD_SEL__enumvalues = { + 0: 'DCIOCHIP_HPD_SEL_ASYNC', + 1: 'DCIOCHIP_HPD_SEL_CLOCKED', +} +DCIOCHIP_HPD_SEL_ASYNC = 0 +DCIOCHIP_HPD_SEL_CLOCKED = 1 +DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PAD_MODE' +DCIOCHIP_PAD_MODE__enumvalues = { + 0: 'DCIOCHIP_PAD_MODE_DDC', + 1: 'DCIOCHIP_PAD_MODE_DP', +} +DCIOCHIP_PAD_MODE_DDC = 0 +DCIOCHIP_PAD_MODE_DP = 1 +DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUXSLAVE_PAD_MODE' +DCIOCHIP_AUXSLAVE_PAD_MODE__enumvalues = { + 0: 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', + 1: 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX', +} +DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0 +DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 1 +DCIOCHIP_AUXSLAVE_PAD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_INVERT' +DCIOCHIP_INVERT__enumvalues = { + 0: 'DCIOCHIP_POL_NON_INVERT', + 1: 'DCIOCHIP_POL_INVERT', +} +DCIOCHIP_POL_NON_INVERT = 0 +DCIOCHIP_POL_INVERT = 1 +DCIOCHIP_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PD_EN' +DCIOCHIP_PD_EN__enumvalues = { + 0: 'DCIOCHIP_PD_EN_NOTALLOW', + 1: 'DCIOCHIP_PD_EN_ALLOW', +} +DCIOCHIP_PD_EN_NOTALLOW = 0 +DCIOCHIP_PD_EN_ALLOW = 1 +DCIOCHIP_PD_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_MASK_EN' +DCIOCHIP_GPIO_MASK_EN__enumvalues = { + 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', +} +DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 +DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 +DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK' +DCIOCHIP_MASK__enumvalues = { + 0: 'DCIOCHIP_MASK_DISABLE', + 1: 'DCIOCHIP_MASK_ENABLE', +} +DCIOCHIP_MASK_DISABLE = 0 +DCIOCHIP_MASK_ENABLE = 1 +DCIOCHIP_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_I2C_MASK' +DCIOCHIP_GPIO_I2C_MASK__enumvalues = { + 0: 'DCIOCHIP_GPIO_I2C_MASK_DISABLE', + 1: 'DCIOCHIP_GPIO_I2C_MASK_ENABLE', +} +DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0 +DCIOCHIP_GPIO_I2C_MASK_ENABLE = 1 +DCIOCHIP_GPIO_I2C_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_I2C_DRIVE' +DCIOCHIP_GPIO_I2C_DRIVE__enumvalues = { + 0: 'DCIOCHIP_GPIO_I2C_DRIVE_LOW', + 1: 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', +} +DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0 +DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 1 +DCIOCHIP_GPIO_I2C_DRIVE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_I2C_EN' +DCIOCHIP_GPIO_I2C_EN__enumvalues = { + 0: 'DCIOCHIP_GPIO_I2C_DISABLE', + 1: 'DCIOCHIP_GPIO_I2C_ENABLE', +} +DCIOCHIP_GPIO_I2C_DISABLE = 0 +DCIOCHIP_GPIO_I2C_ENABLE = 1 +DCIOCHIP_GPIO_I2C_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK_4BIT' +DCIOCHIP_MASK_4BIT__enumvalues = { + 0: 'DCIOCHIP_MASK_4BIT_DISABLE', + 15: 'DCIOCHIP_MASK_4BIT_ENABLE', +} +DCIOCHIP_MASK_4BIT_DISABLE = 0 +DCIOCHIP_MASK_4BIT_ENABLE = 15 +DCIOCHIP_MASK_4BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_ENABLE_4BIT' +DCIOCHIP_ENABLE_4BIT__enumvalues = { + 0: 'DCIOCHIP_4BIT_DISABLE', + 15: 'DCIOCHIP_4BIT_ENABLE', +} +DCIOCHIP_4BIT_DISABLE = 0 +DCIOCHIP_4BIT_ENABLE = 15 +DCIOCHIP_ENABLE_4BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK_5BIT' +DCIOCHIP_MASK_5BIT__enumvalues = { + 0: 'DCIOCHIP_MASIK_5BIT_DISABLE', + 31: 'DCIOCHIP_MASIK_5BIT_ENABLE', +} +DCIOCHIP_MASIK_5BIT_DISABLE = 0 +DCIOCHIP_MASIK_5BIT_ENABLE = 31 +DCIOCHIP_MASK_5BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_ENABLE_5BIT' +DCIOCHIP_ENABLE_5BIT__enumvalues = { + 0: 'DCIOCHIP_5BIT_DISABLE', + 31: 'DCIOCHIP_5BIT_ENABLE', +} +DCIOCHIP_5BIT_DISABLE = 0 +DCIOCHIP_5BIT_ENABLE = 31 +DCIOCHIP_ENABLE_5BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK_2BIT' +DCIOCHIP_MASK_2BIT__enumvalues = { + 0: 'DCIOCHIP_MASK_2BIT_DISABLE', + 3: 'DCIOCHIP_MASK_2BIT_ENABLE', +} +DCIOCHIP_MASK_2BIT_DISABLE = 0 +DCIOCHIP_MASK_2BIT_ENABLE = 3 +DCIOCHIP_MASK_2BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_ENABLE_2BIT' +DCIOCHIP_ENABLE_2BIT__enumvalues = { + 0: 'DCIOCHIP_2BIT_DISABLE', + 3: 'DCIOCHIP_2BIT_ENABLE', +} +DCIOCHIP_2BIT_DISABLE = 0 +DCIOCHIP_2BIT_ENABLE = 3 +DCIOCHIP_ENABLE_2BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' +DCIOCHIP_REF_27_SRC_SEL__enumvalues = { + 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', + 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', +} +DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 +DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 +DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_DVO_VREFPON' +DCIOCHIP_DVO_VREFPON__enumvalues = { + 0: 'DCIOCHIP_DVO_VREFPON_DISABLE', + 1: 'DCIOCHIP_DVO_VREFPON_ENABLE', +} +DCIOCHIP_DVO_VREFPON_DISABLE = 0 +DCIOCHIP_DVO_VREFPON_ENABLE = 1 +DCIOCHIP_DVO_VREFPON = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_DVO_VREFSEL' +DCIOCHIP_DVO_VREFSEL__enumvalues = { + 0: 'DCIOCHIP_DVO_VREFSEL_ONCHIP', + 1: 'DCIOCHIP_DVO_VREFSEL_EXTERNAL', +} +DCIOCHIP_DVO_VREFSEL_ONCHIP = 0 +DCIOCHIP_DVO_VREFSEL_EXTERNAL = 1 +DCIOCHIP_DVO_VREFSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_SPDIF1_IMODE' +DCIOCHIP_SPDIF1_IMODE__enumvalues = { + 0: 'DCIOCHIP_SPDIF1_IMODE_OE_A', + 1: 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO', +} +DCIOCHIP_SPDIF1_IMODE_OE_A = 0 +DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 1 +DCIOCHIP_SPDIF1_IMODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' +DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { + 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', + 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', +} +DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 +DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 +DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_FALLSLEWSEL' +DCIOCHIP_I2C_FALLSLEWSEL__enumvalues = { + 0: 'DCIOCHIP_I2C_FALLSLEWSEL_00', + 1: 'DCIOCHIP_I2C_FALLSLEWSEL_01', + 2: 'DCIOCHIP_I2C_FALLSLEWSEL_10', + 3: 'DCIOCHIP_I2C_FALLSLEWSEL_11', +} +DCIOCHIP_I2C_FALLSLEWSEL_00 = 0 +DCIOCHIP_I2C_FALLSLEWSEL_01 = 1 +DCIOCHIP_I2C_FALLSLEWSEL_10 = 2 +DCIOCHIP_I2C_FALLSLEWSEL_11 = 3 +DCIOCHIP_I2C_FALLSLEWSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_SPIKESEL' +DCIOCHIP_AUX_SPIKESEL__enumvalues = { + 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', + 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', +} +DCIOCHIP_AUX_SPIKESEL_50NS = 0 +DCIOCHIP_AUX_SPIKESEL_10NS = 1 +DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL0P9' +DCIOCHIP_AUX_CSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', +} +DCIOCHIP_AUX_CSEL_DEC1P0 = 0 +DCIOCHIP_AUX_CSEL_DEC0P9 = 1 +DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL1P1' +DCIOCHIP_AUX_CSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_INC1P0', + 1: 'DCIOCHIP_AUX_CSEL_INC1P1', +} +DCIOCHIP_AUX_CSEL_INC1P0 = 0 +DCIOCHIP_AUX_CSEL_INC1P1 = 1 +DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL0P9' +DCIOCHIP_AUX_RSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', +} +DCIOCHIP_AUX_RSEL_DEC1P0 = 0 +DCIOCHIP_AUX_RSEL_DEC0P9 = 1 +DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL1P1' +DCIOCHIP_AUX_RSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_INC1P0', + 1: 'DCIOCHIP_AUX_RSEL_INC1P1', +} +DCIOCHIP_AUX_RSEL_INC1P0 = 0 +DCIOCHIP_AUX_RSEL_INC1P1 = 1 +DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_HYS_TUNE' +DCIOCHIP_AUX_HYS_TUNE__enumvalues = { + 0: 'DCIOCHIP_AUX_HYS_TUNE_0', + 1: 'DCIOCHIP_AUX_HYS_TUNE_1', + 2: 'DCIOCHIP_AUX_HYS_TUNE_2', + 3: 'DCIOCHIP_AUX_HYS_TUNE_3', +} +DCIOCHIP_AUX_HYS_TUNE_0 = 0 +DCIOCHIP_AUX_HYS_TUNE_1 = 1 +DCIOCHIP_AUX_HYS_TUNE_2 = 2 +DCIOCHIP_AUX_HYS_TUNE_3 = 3 +DCIOCHIP_AUX_HYS_TUNE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_VOD_TUNE' +DCIOCHIP_AUX_VOD_TUNE__enumvalues = { + 0: 'DCIOCHIP_AUX_VOD_TUNE_0', + 1: 'DCIOCHIP_AUX_VOD_TUNE_1', + 2: 'DCIOCHIP_AUX_VOD_TUNE_2', + 3: 'DCIOCHIP_AUX_VOD_TUNE_3', +} +DCIOCHIP_AUX_VOD_TUNE_0 = 0 +DCIOCHIP_AUX_VOD_TUNE_1 = 1 +DCIOCHIP_AUX_VOD_TUNE_2 = 2 +DCIOCHIP_AUX_VOD_TUNE_3 = 3 +DCIOCHIP_AUX_VOD_TUNE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_VPH_1V2_EN' +DCIOCHIP_I2C_VPH_1V2_EN__enumvalues = { + 0: 'DCIOCHIP_I2C_VPH_1V2_EN_0', + 1: 'DCIOCHIP_I2C_VPH_1V2_EN_1', +} +DCIOCHIP_I2C_VPH_1V2_EN_0 = 0 +DCIOCHIP_I2C_VPH_1V2_EN_1 = 1 +DCIOCHIP_I2C_VPH_1V2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_COMPSEL' +DCIOCHIP_I2C_COMPSEL__enumvalues = { + 0: 'DCIOCHIP_I2C_REC_SCHMIT', + 1: 'DCIOCHIP_I2C_REC_COMPARATOR', +} +DCIOCHIP_I2C_REC_SCHMIT = 0 +DCIOCHIP_I2C_REC_COMPARATOR = 1 +DCIOCHIP_I2C_COMPSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_ALL_PWR_OK' +DCIOCHIP_AUX_ALL_PWR_OK__enumvalues = { + 0: 'DCIOCHIP_AUX_ALL_PWR_OK_0', + 1: 'DCIOCHIP_AUX_ALL_PWR_OK_1', +} +DCIOCHIP_AUX_ALL_PWR_OK_0 = 0 +DCIOCHIP_AUX_ALL_PWR_OK_1 = 1 +DCIOCHIP_AUX_ALL_PWR_OK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_RECEIVER_SEL' +DCIOCHIP_I2C_RECEIVER_SEL__enumvalues = { + 0: 'DCIOCHIP_I2C_RECEIVER_SEL_0', + 1: 'DCIOCHIP_I2C_RECEIVER_SEL_1', + 2: 'DCIOCHIP_I2C_RECEIVER_SEL_2', + 3: 'DCIOCHIP_I2C_RECEIVER_SEL_3', +} +DCIOCHIP_I2C_RECEIVER_SEL_0 = 0 +DCIOCHIP_I2C_RECEIVER_SEL_1 = 1 +DCIOCHIP_I2C_RECEIVER_SEL_2 = 2 +DCIOCHIP_I2C_RECEIVER_SEL_3 = 3 +DCIOCHIP_I2C_RECEIVER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RECEIVER_SEL' +DCIOCHIP_AUX_RECEIVER_SEL__enumvalues = { + 0: 'DCIOCHIP_AUX_RECEIVER_SEL_0', + 1: 'DCIOCHIP_AUX_RECEIVER_SEL_1', + 2: 'DCIOCHIP_AUX_RECEIVER_SEL_2', + 3: 'DCIOCHIP_AUX_RECEIVER_SEL_3', +} +DCIOCHIP_AUX_RECEIVER_SEL_0 = 0 +DCIOCHIP_AUX_RECEIVER_SEL_1 = 1 +DCIOCHIP_AUX_RECEIVER_SEL_2 = 2 +DCIOCHIP_AUX_RECEIVER_SEL_3 = 3 +DCIOCHIP_AUX_RECEIVER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_GLOBAL_CAPABILITIES' +AZ_GLOBAL_CAPABILITIES__enumvalues = { + 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', +} +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 +AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { + 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', + 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', +} +ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 +ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' +GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { + 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', + 1: 'FLUSH_CONTROL_FLUSH_STARTED', +} +FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 +FLUSH_CONTROL_FLUSH_STARTED = 1 +GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' +GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { + 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', +} +CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 +CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 +GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_STATE_CHANGE_STATUS' +AZ_STATE_CHANGE_STATUS__enumvalues = { + 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', +} +AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 +AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 +AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' +GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { + 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', +} +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 +GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_0_SYNCHRONIZATION' +STREAM_0_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_1_SYNCHRONIZATION' +STREAM_1_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_2_SYNCHRONIZATION' +STREAM_2_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_3_SYNCHRONIZATION' +STREAM_3_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_4_SYNCHRONIZATION' +STREAM_4_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_5_SYNCHRONIZATION' +STREAM_5_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_6_SYNCHRONIZATION' +STREAM_6_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_7_SYNCHRONIZATION' +STREAM_7_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_8_SYNCHRONIZATION' +STREAM_8_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_9_SYNCHRONIZATION' +STREAM_9_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_10_SYNCHRONIZATION' +STREAM_10_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_11_SYNCHRONIZATION' +STREAM_11_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_12_SYNCHRONIZATION' +STREAM_12_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_13_SYNCHRONIZATION' +STREAM_13_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_14_SYNCHRONIZATION' +STREAM_14_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_15_SYNCHRONIZATION' +STREAM_15_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'CORB_READ_POINTER_RESET' +CORB_READ_POINTER_RESET__enumvalues = { + 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', +} +CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 +CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 +CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_CORB_SIZE' +AZ_CORB_SIZE__enumvalues = { + 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_CORB_SIZE_256ENTRIES', + 3: 'AZ_CORB_SIZE_RESERVED', +} +AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 +AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 +AZ_CORB_SIZE_256ENTRIES = 2 +AZ_CORB_SIZE_RESERVED = 3 +AZ_CORB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' +AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { + 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', + 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', +} +AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 +AZ_RIRB_WRITE_POINTER_DO_RESET = 1 +AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_SIZE' +AZ_RIRB_SIZE__enumvalues = { + 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_RIRB_SIZE_256ENTRIES', + 3: 'AZ_RIRB_SIZE_UNDEFINED', +} +AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 +AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 +AZ_RIRB_SIZE_256ENTRIES = 2 +AZ_RIRB_SIZE_UNDEFINED = 3 +AZ_RIRB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum + +# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { + 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', +} +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE' +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', + 2: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', + 3: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', + 4: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', + 5: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', + 6: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', + 7: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', + 8: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', + 9: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', + 10: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', + 11: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', + 12: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', + 13: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', + 14: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', + 15: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', +} +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 1 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 2 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 3 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 4 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 5 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 6 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 7 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 8 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 9 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 10 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 11 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 12 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 13 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 14 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 15 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL' +MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'NO_FORCE_REQUEST', + 1: 'FORCE_LIGHT_SLEEP_REQUEST', + 2: 'FORCE_DEEP_SLEEP_REQUEST', + 3: 'FORCE_SHUT_DOWN_REQUEST', +} +NO_FORCE_REQUEST = 0 +FORCE_LIGHT_SLEEP_REQUEST = 1 +FORCE_DEEP_SLEEP_REQUEST = 2 +FORCE_SHUT_DOWN_REQUEST = 3 +MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL2' +MEM_PWR_FORCE_CTRL2__enumvalues = { + 0: 'NO_FORCE_REQ', + 1: 'FORCE_LIGHT_SLEEP_REQ', +} +NO_FORCE_REQ = 0 +FORCE_LIGHT_SLEEP_REQ = 1 +MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_DIS_CTRL' +MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'ENABLE_MEM_PWR_CTRL', + 1: 'DISABLE_MEM_PWR_CTRL', +} +ENABLE_MEM_PWR_CTRL = 0 +DISABLE_MEM_PWR_CTRL = 1 +MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL' +MEM_PWR_SEL_CTRL__enumvalues = { + 0: 'DYNAMIC_SHUT_DOWN_ENABLE', + 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', + 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', +} +DYNAMIC_SHUT_DOWN_ENABLE = 0 +DYNAMIC_DEEP_SLEEP_ENABLE = 1 +DYNAMIC_LIGHT_SLEEP_ENABLE = 2 +MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL2' +MEM_PWR_SEL_CTRL2__enumvalues = { + 0: 'DYNAMIC_DEEP_SLEEP_EN', + 1: 'DYNAMIC_LIGHT_SLEEP_EN', +} +DYNAMIC_DEEP_SLEEP_EN = 0 +DYNAMIC_LIGHT_SLEEP_EN = 1 +MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { + 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', +} +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { + 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', +} +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' +AZ_LATENCY_COUNTER_CONTROL__enumvalues = { + 0: 'AZ_LATENCY_COUNTER_NO_RESET', + 1: 'AZ_LATENCY_COUNTER_RESET_DONE', +} +AZ_LATENCY_COUNTER_NO_RESET = 0 +AZ_LATENCY_COUNTER_RESET_DONE = 1 +AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', +} +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_ICH_RESET_ENUM' +DSCC_ICH_RESET_ENUM__enumvalues = { + 1: 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', + 2: 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', + 4: 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', + 8: 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', +} +DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 1 +DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 2 +DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 4 +DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 8 +DSCC_ICH_RESET_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_DSC_VERSION_MINOR_ENUM' +DSCC_DSC_VERSION_MINOR_ENUM__enumvalues = { + 1: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', + 2: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', +} +DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 1 +DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 2 +DSCC_DSC_VERSION_MINOR_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_DSC_VERSION_MAJOR_ENUM' +DSCC_DSC_VERSION_MAJOR_ENUM__enumvalues = { + 1: 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', +} +DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 1 +DSCC_DSC_VERSION_MAJOR_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_LINEBUF_DEPTH_ENUM' +DSCC_LINEBUF_DEPTH_ENUM__enumvalues = { + 8: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', + 9: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', + 10: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', + 11: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', + 12: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', + 13: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', +} +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 8 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 9 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 10 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 11 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 12 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 13 +DSCC_LINEBUF_DEPTH_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_BITS_PER_COMPONENT_ENUM' +DSCC_BITS_PER_COMPONENT_ENUM__enumvalues = { + 8: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 10: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 12: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', +} +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 +DSCC_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_ENABLE_ENUM' +DSCC_ENABLE_ENUM__enumvalues = { + 0: 'DSCC_ENABLE_ENUM_DISABLED', + 1: 'DSCC_ENABLE_ENUM_ENABLED', +} +DSCC_ENABLE_ENUM_DISABLED = 0 +DSCC_ENABLE_ENUM_ENABLED = 1 +DSCC_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_MEM_PWR_FORCE_ENUM' +DSCC_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', + 1: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', +} +DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 2 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 3 +DSCC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'POWER_STATE_ENUM' +POWER_STATE_ENUM__enumvalues = { + 0: 'POWER_STATE_ENUM_ON', + 1: 'POWER_STATE_ENUM_LS', + 2: 'POWER_STATE_ENUM_DS', + 3: 'POWER_STATE_ENUM_SD', +} +POWER_STATE_ENUM_ON = 0 +POWER_STATE_ENUM_LS = 1 +POWER_STATE_ENUM_DS = 2 +POWER_STATE_ENUM_SD = 3 +POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_MEM_PWR_DIS_ENUM' +DSCC_MEM_PWR_DIS_ENUM__enumvalues = { + 0: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', + 1: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', +} +DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0 +DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 1 +DSCC_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_ENABLE_ENUM' +DSCCIF_ENABLE_ENUM__enumvalues = { + 0: 'DSCCIF_ENABLE_ENUM_DISABLED', + 1: 'DSCCIF_ENABLE_ENUM_ENABLED', +} +DSCCIF_ENABLE_ENUM_DISABLED = 0 +DSCCIF_ENABLE_ENUM_ENABLED = 1 +DSCCIF_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM' +DSCCIF_INPUT_PIXEL_FORMAT_ENUM__enumvalues = { + 0: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', + 1: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', + 2: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', + 3: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', + 4: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', +} +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 1 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 2 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 3 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 4 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_BITS_PER_COMPONENT_ENUM' +DSCCIF_BITS_PER_COMPONENT_ENUM__enumvalues = { + 8: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 10: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 12: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', +} +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 +DSCCIF_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE_ENUM' +ENABLE_ENUM__enumvalues = { + 0: 'ENABLE_ENUM_DISABLED', + 1: 'ENABLE_ENUM_ENABLED', +} +ENABLE_ENUM_DISABLED = 0 +ENABLE_ENUM_ENABLED = 1 +ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_GATING_DISABLE_ENUM' +CLOCK_GATING_DISABLE_ENUM__enumvalues = { + 0: 'CLOCK_GATING_DISABLE_ENUM_ENABLED', + 1: 'CLOCK_GATING_DISABLE_ENUM_DISABLED', +} +CLOCK_GATING_DISABLE_ENUM_ENABLED = 0 +CLOCK_GATING_DISABLE_ENUM_DISABLED = 1 +CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLOCK_MUX_SELECT_ENUM' +TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = { + 0: 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', + 1: 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', + 2: 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', + 3: 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', + 4: 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', + 5: 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', +} +TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0 +TEST_CLOCK_MUX_SELECT_DISPCLK_G = 1 +TEST_CLOCK_MUX_SELECT_DISPCLK_R = 2 +TEST_CLOCK_MUX_SELECT_DSCCLK_P = 3 +TEST_CLOCK_MUX_SELECT_DSCCLK_G = 4 +TEST_CLOCK_MUX_SELECT_DSCCLK_R = 5 +TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WB_ENABLE_ENUM' +WB_ENABLE_ENUM__enumvalues = { + 0: 'WB_EN_DISABLE', + 1: 'WB_EN_ENABLE', +} +WB_EN_DISABLE = 0 +WB_EN_ENABLE = 1 +WB_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WB_CLK_GATE_DIS_ENUM' +WB_CLK_GATE_DIS_ENUM__enumvalues = { + 0: 'WB_CLK_GATE_ENABLE', + 1: 'WB_CLK_GATE_DISABLE', +} +WB_CLK_GATE_ENABLE = 0 +WB_CLK_GATE_DISABLE = 1 +WB_CLK_GATE_DIS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WB_MEM_PWR_DIS_ENUM' +WB_MEM_PWR_DIS_ENUM__enumvalues = { + 0: 'WB_MEM_PWR_ENABLE', + 1: 'WB_MEM_PWR_DISABLE', +} +WB_MEM_PWR_ENABLE = 0 +WB_MEM_PWR_DISABLE = 1 +WB_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WB_TEST_CLK_SEL_ENUM' +WB_TEST_CLK_SEL_ENUM__enumvalues = { + 0: 'WB_TEST_CLK_SEL_REG', + 1: 'WB_TEST_CLK_SEL_WB', + 2: 'WB_TEST_CLK_SEL_WBSCL', + 3: 'WB_TEST_CLK_SEL_PERM', +} +WB_TEST_CLK_SEL_REG = 0 +WB_TEST_CLK_SEL_WB = 1 +WB_TEST_CLK_SEL_WBSCL = 2 +WB_TEST_CLK_SEL_PERM = 3 +WB_TEST_CLK_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_LB_MEM_PWR_MODE_SEL_ENUM' +WBSCL_LB_MEM_PWR_MODE_SEL_ENUM__enumvalues = { + 0: 'WBSCL_LB_MEM_PWR_MODE_SEL_SD', + 1: 'WBSCL_LB_MEM_PWR_MODE_SEL_DS', + 2: 'WBSCL_LB_MEM_PWR_MODE_SEL_LS', + 3: 'WBSCL_LB_MEM_PWR_MODE_SEL_ON', +} +WBSCL_LB_MEM_PWR_MODE_SEL_SD = 0 +WBSCL_LB_MEM_PWR_MODE_SEL_DS = 1 +WBSCL_LB_MEM_PWR_MODE_SEL_LS = 2 +WBSCL_LB_MEM_PWR_MODE_SEL_ON = 3 +WBSCL_LB_MEM_PWR_MODE_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_LB_MEM_PWR_FORCE_ENUM' +WBSCL_LB_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'WBSCL_LB_MEM_PWR_FORCE_NO', + 1: 'WBSCL_LB_MEM_PWR_FORCE_LS', + 2: 'WBSCL_LB_MEM_PWR_FORCE_DS', + 3: 'WBSCL_LB_MEM_PWR_FORCE_SD', +} +WBSCL_LB_MEM_PWR_FORCE_NO = 0 +WBSCL_LB_MEM_PWR_FORCE_LS = 1 +WBSCL_LB_MEM_PWR_FORCE_DS = 2 +WBSCL_LB_MEM_PWR_FORCE_SD = 3 +WBSCL_LB_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_MEM_PWR_STATE_ENUM' +WBSCL_MEM_PWR_STATE_ENUM__enumvalues = { + 0: 'WBSCL_MEM_PWR_STATE_ON', + 1: 'WBSCL_MEM_PWR_STATE_LS', + 2: 'WBSCL_MEM_PWR_STATE_DS', + 3: 'WBSCL_MEM_PWR_STATE_SD', +} +WBSCL_MEM_PWR_STATE_ON = 0 +WBSCL_MEM_PWR_STATE_LS = 1 +WBSCL_MEM_PWR_STATE_DS = 2 +WBSCL_MEM_PWR_STATE_SD = 3 +WBSCL_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_LUT_MEM_PWR_STATE_ENUM' +WBSCL_LUT_MEM_PWR_STATE_ENUM__enumvalues = { + 0: 'WBSCL_LUT_MEM_PWR_STATE_ON', + 1: 'WBSCL_LUT_MEM_PWR_STATE_LS', + 2: 'WBSCL_LUT_MEM_PWR_STATE_RESERVED2', + 3: 'WBSCL_LUT_MEM_PWR_STATE_RESERVED3', +} +WBSCL_LUT_MEM_PWR_STATE_ON = 0 +WBSCL_LUT_MEM_PWR_STATE_LS = 1 +WBSCL_LUT_MEM_PWR_STATE_RESERVED2 = 2 +WBSCL_LUT_MEM_PWR_STATE_RESERVED3 = 3 +WBSCL_LUT_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WB_RAM_PW_SAVE_MODE_ENUM' +WB_RAM_PW_SAVE_MODE_ENUM__enumvalues = { + 0: 'WB_RAM_PW_SAVE_MODE_LS', + 1: 'WB_RAM_PW_SAVE_MODE_SD', +} +WB_RAM_PW_SAVE_MODE_LS = 0 +WB_RAM_PW_SAVE_MODE_SD = 1 +WB_RAM_PW_SAVE_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_OUT_BPC_ENUM' +CNV_OUT_BPC_ENUM__enumvalues = { + 0: 'CNV_OUT_BPC_8BPC', + 1: 'CNV_OUT_BPC_10BPC', +} +CNV_OUT_BPC_8BPC = 0 +CNV_OUT_BPC_10BPC = 1 +CNV_OUT_BPC_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_FRAME_CAPTURE_RATE_ENUM' +CNV_FRAME_CAPTURE_RATE_ENUM__enumvalues = { + 0: 'CNV_FRAME_CAPTURE_RATE_0', + 1: 'CNV_FRAME_CAPTURE_RATE_1', + 2: 'CNV_FRAME_CAPTURE_RATE_2', + 3: 'CNV_FRAME_CAPTURE_RATE_3', +} +CNV_FRAME_CAPTURE_RATE_0 = 0 +CNV_FRAME_CAPTURE_RATE_1 = 1 +CNV_FRAME_CAPTURE_RATE_2 = 2 +CNV_FRAME_CAPTURE_RATE_3 = 3 +CNV_FRAME_CAPTURE_RATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_WINDOW_CROP_EN_ENUM' +CNV_WINDOW_CROP_EN_ENUM__enumvalues = { + 0: 'CNV_WINDOW_CROP_DISABLE', + 1: 'CNV_WINDOW_CROP_ENABLE', +} +CNV_WINDOW_CROP_DISABLE = 0 +CNV_WINDOW_CROP_ENABLE = 1 +CNV_WINDOW_CROP_EN_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_INTERLACED_MODE_ENUM' +CNV_INTERLACED_MODE_ENUM__enumvalues = { + 0: 'CNV_INTERLACED_MODE_PROGRESSIVE', + 1: 'CNV_INTERLACED_MODE_INTERLACED', +} +CNV_INTERLACED_MODE_PROGRESSIVE = 0 +CNV_INTERLACED_MODE_INTERLACED = 1 +CNV_INTERLACED_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_EYE_SELECT' +CNV_EYE_SELECT__enumvalues = { + 0: 'STEREO_DISABLED', + 1: 'LEFT_EYE', + 2: 'RIGHT_EYE', + 3: 'BOTH_EYE', +} +STEREO_DISABLED = 0 +LEFT_EYE = 1 +RIGHT_EYE = 2 +BOTH_EYE = 3 +CNV_EYE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_STEREO_TYPE_ENUM' +CNV_STEREO_TYPE_ENUM__enumvalues = { + 0: 'CNV_STEREO_TYPE_RESERVED0', + 1: 'CNV_STEREO_TYPE_RESERVED1', + 2: 'CNV_STEREO_TYPE_RESERVED2', + 3: 'CNV_STEREO_TYPE_FRAME_SEQUENTIAL', +} +CNV_STEREO_TYPE_RESERVED0 = 0 +CNV_STEREO_TYPE_RESERVED1 = 1 +CNV_STEREO_TYPE_RESERVED2 = 2 +CNV_STEREO_TYPE_FRAME_SEQUENTIAL = 3 +CNV_STEREO_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_STEREO_POLARITY_ENUM' +CNV_STEREO_POLARITY_ENUM__enumvalues = { + 0: 'CNV_STEREO_POLARITY_LEFT', + 1: 'CNV_STEREO_POLARITY_RIGHT', +} +CNV_STEREO_POLARITY_LEFT = 0 +CNV_STEREO_POLARITY_RIGHT = 1 +CNV_STEREO_POLARITY_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_INTERLACED_FIELD_ORDER_ENUM' +CNV_INTERLACED_FIELD_ORDER_ENUM__enumvalues = { + 0: 'CNV_INTERLACED_FIELD_ORDER_TOP', + 1: 'CNV_INTERLACED_FIELD_ORDER_BOT', +} +CNV_INTERLACED_FIELD_ORDER_TOP = 0 +CNV_INTERLACED_FIELD_ORDER_BOT = 1 +CNV_INTERLACED_FIELD_ORDER_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_STEREO_SPLIT_ENUM' +CNV_STEREO_SPLIT_ENUM__enumvalues = { + 0: 'CNV_STEREO_SPLIT_DISABLE', + 1: 'CNV_STEREO_SPLIT_ENABLE', +} +CNV_STEREO_SPLIT_DISABLE = 0 +CNV_STEREO_SPLIT_ENABLE = 1 +CNV_STEREO_SPLIT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_NEW_CONTENT_ENUM' +CNV_NEW_CONTENT_ENUM__enumvalues = { + 0: 'CNV_NEW_CONTENT_NEG', + 1: 'CNV_NEW_CONTENT_POS', +} +CNV_NEW_CONTENT_NEG = 0 +CNV_NEW_CONTENT_POS = 1 +CNV_NEW_CONTENT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_FRAME_CAPTURE_EN_ENUM' +CNV_FRAME_CAPTURE_EN_ENUM__enumvalues = { + 0: 'CNV_FRAME_CAPTURE_DISABLE', + 1: 'CNV_FRAME_CAPTURE_ENABLE', +} +CNV_FRAME_CAPTURE_DISABLE = 0 +CNV_FRAME_CAPTURE_ENABLE = 1 +CNV_FRAME_CAPTURE_EN_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_UPDATE_PENDING_ENUM' +CNV_UPDATE_PENDING_ENUM__enumvalues = { + 0: 'CNV_UPDATE_PENDING_NEG', + 1: 'CNV_UPDATE_PENDING_POS', +} +CNV_UPDATE_PENDING_NEG = 0 +CNV_UPDATE_PENDING_POS = 1 +CNV_UPDATE_PENDING_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_UPDATE_LOCK_ENUM' +CNV_UPDATE_LOCK_ENUM__enumvalues = { + 0: 'CNV_UPDATE_UNLOCK', + 1: 'CNV_UPDATE_LOCK', +} +CNV_UPDATE_UNLOCK = 0 +CNV_UPDATE_LOCK = 1 +CNV_UPDATE_LOCK_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_CSC_BYPASS_ENUM' +CNV_CSC_BYPASS_ENUM__enumvalues = { + 0: 'CNV_CSC_BYPASS_NEG', + 1: 'CNV_CSC_BYPASS_POS', +} +CNV_CSC_BYPASS_NEG = 0 +CNV_CSC_BYPASS_POS = 1 +CNV_CSC_BYPASS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_TEST_CRC_EN_ENUM' +CNV_TEST_CRC_EN_ENUM__enumvalues = { + 0: 'CNV_TEST_CRC_DISABLE', + 1: 'CNV_TEST_CRC_ENABLE', +} +CNV_TEST_CRC_DISABLE = 0 +CNV_TEST_CRC_ENABLE = 1 +CNV_TEST_CRC_EN_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNV_TEST_CRC_CONT_EN_ENUM' +CNV_TEST_CRC_CONT_EN_ENUM__enumvalues = { + 0: 'CNV_TEST_CRC_CONT_DISABLE', + 1: 'CNV_TEST_CRC_CONT_ENABLE', +} +CNV_TEST_CRC_CONT_DISABLE = 0 +CNV_TEST_CRC_CONT_ENABLE = 1 +CNV_TEST_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WB_SOFT_RESET_ENUM' +WB_SOFT_RESET_ENUM__enumvalues = { + 0: 'WB_SOFT_RESET_NEG', + 1: 'WB_SOFT_RESET_POS', +} +WB_SOFT_RESET_NEG = 0 +WB_SOFT_RESET_POS = 1 +WB_SOFT_RESET_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_GMC_WARM_UP_ENABLE_ENUM' +DWB_GMC_WARM_UP_ENABLE_ENUM__enumvalues = { + 0: 'DWB_GMC_WARM_UP_DISABLE', + 1: 'DWB_GMC_WARM_UP_ENABLE', +} +DWB_GMC_WARM_UP_DISABLE = 0 +DWB_GMC_WARM_UP_ENABLE = 1 +DWB_GMC_WARM_UP_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_MODE_WARMUP_ENUM' +DWB_MODE_WARMUP_ENUM__enumvalues = { + 0: 'DWB_MODE_WARMUP_420', + 1: 'DWB_MODE_WARMUP_444', +} +DWB_MODE_WARMUP_420 = 0 +DWB_MODE_WARMUP_444 = 1 +DWB_MODE_WARMUP_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DATA_DEPTH_WARMUP_ENUM' +DWB_DATA_DEPTH_WARMUP_ENUM__enumvalues = { + 0: 'DWB_DATA_DEPTH_WARMUP_8BPC', + 1: 'DWB_DATA_DEPTH_WARMUP_10BPC', +} +DWB_DATA_DEPTH_WARMUP_8BPC = 0 +DWB_DATA_DEPTH_WARMUP_10BPC = 1 +DWB_DATA_DEPTH_WARMUP_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM' +WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM__enumvalues = { + 0: 'WBSCL_COEF_RAM_TAP_PAIR_IDX0', + 1: 'WBSCL_COEF_RAM_TAP_PAIR_IDX1', + 2: 'WBSCL_COEF_RAM_TAP_PAIR_IDX2', + 3: 'WBSCL_COEF_RAM_TAP_PAIR_IDX3', + 4: 'WBSCL_COEF_RAM_TAP_PAIR_IDX4', + 5: 'WBSCL_COEF_RAM_TAP_PAIR_IDX5', +} +WBSCL_COEF_RAM_TAP_PAIR_IDX0 = 0 +WBSCL_COEF_RAM_TAP_PAIR_IDX1 = 1 +WBSCL_COEF_RAM_TAP_PAIR_IDX2 = 2 +WBSCL_COEF_RAM_TAP_PAIR_IDX3 = 3 +WBSCL_COEF_RAM_TAP_PAIR_IDX4 = 4 +WBSCL_COEF_RAM_TAP_PAIR_IDX5 = 5 +WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_COEF_RAM_PHASE_ENUM' +WBSCL_COEF_RAM_PHASE_ENUM__enumvalues = { + 0: 'WBSCL_COEF_RAM_PHASE0', + 1: 'WBSCL_COEF_RAM_PHASE1', + 2: 'WBSCL_COEF_RAM_PHASE2', + 3: 'WBSCL_COEF_RAM_PHASE3', + 4: 'WBSCL_COEF_RAM_PHASE4', + 5: 'WBSCL_COEF_RAM_PHASE5', + 6: 'WBSCL_COEF_RAM_PHASE6', + 7: 'WBSCL_COEF_RAM_PHASE7', + 8: 'WBSCL_COEF_RAM_PHASE8', +} +WBSCL_COEF_RAM_PHASE0 = 0 +WBSCL_COEF_RAM_PHASE1 = 1 +WBSCL_COEF_RAM_PHASE2 = 2 +WBSCL_COEF_RAM_PHASE3 = 3 +WBSCL_COEF_RAM_PHASE4 = 4 +WBSCL_COEF_RAM_PHASE5 = 5 +WBSCL_COEF_RAM_PHASE6 = 6 +WBSCL_COEF_RAM_PHASE7 = 7 +WBSCL_COEF_RAM_PHASE8 = 8 +WBSCL_COEF_RAM_PHASE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_COEF_RAM_FILTER_TYPE_ENUM' +WBSCL_COEF_RAM_FILTER_TYPE_ENUM__enumvalues = { + 0: 'WBSCL_COEF_RAM_FILTER_TYPE_VL', + 1: 'WBSCL_COEF_RAM_FILTER_TYPE_VC', + 2: 'WBSCL_COEF_RAM_FILTER_TYPE_HL', + 3: 'WBSCL_COEF_RAM_FILTER_TYPE_HC', +} +WBSCL_COEF_RAM_FILTER_TYPE_VL = 0 +WBSCL_COEF_RAM_FILTER_TYPE_VC = 1 +WBSCL_COEF_RAM_FILTER_TYPE_HL = 2 +WBSCL_COEF_RAM_FILTER_TYPE_HC = 3 +WBSCL_COEF_RAM_FILTER_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_COEF_FILTER_TYPE_SEL' +WBSCL_COEF_FILTER_TYPE_SEL__enumvalues = { + 0: 'WBSCL_COEF_LUMA_VERT_FILTER', + 1: 'WBSCL_COEF_CHROMA_VERT_FILTER', + 2: 'WBSCL_COEF_LUMA_HORZ_FILTER', + 3: 'WBSCL_COEF_CHROMA_HORZ_FILTER', +} +WBSCL_COEF_LUMA_VERT_FILTER = 0 +WBSCL_COEF_CHROMA_VERT_FILTER = 1 +WBSCL_COEF_LUMA_HORZ_FILTER = 2 +WBSCL_COEF_CHROMA_HORZ_FILTER = 3 +WBSCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_MODE_SEL' +WBSCL_MODE_SEL__enumvalues = { + 0: 'WBSCL_MODE_SCALING_444_BYPASS', + 1: 'WBSCL_MODE_SCALING_444_RGB_ENABLE', + 2: 'WBSCL_MODE_SCALING_444_YCBCR_ENABLE', + 3: 'WBSCL_MODE_SCALING_YCBCR_ENABLE', +} +WBSCL_MODE_SCALING_444_BYPASS = 0 +WBSCL_MODE_SCALING_444_RGB_ENABLE = 1 +WBSCL_MODE_SCALING_444_YCBCR_ENABLE = 2 +WBSCL_MODE_SCALING_YCBCR_ENABLE = 3 +WBSCL_MODE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_PIXEL_DEPTH' +WBSCL_PIXEL_DEPTH__enumvalues = { + 0: 'PIXEL_DEPTH_8BPC', + 1: 'PIXEL_DEPTH_10BPC', +} +PIXEL_DEPTH_8BPC = 0 +PIXEL_DEPTH_10BPC = 1 +WBSCL_PIXEL_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_COEF_RAM_SEL_ENUM' +WBSCL_COEF_RAM_SEL_ENUM__enumvalues = { + 0: 'WBSCL_COEF_RAM_SEL_0', + 1: 'WBSCL_COEF_RAM_SEL_1', +} +WBSCL_COEF_RAM_SEL_0 = 0 +WBSCL_COEF_RAM_SEL_1 = 1 +WBSCL_COEF_RAM_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_COEF_RAM_RD_SEL_ENUM' +WBSCL_COEF_RAM_RD_SEL_ENUM__enumvalues = { + 0: 'WBSCL_COEF_RAM_RD_SEL_0', + 1: 'WBSCL_COEF_RAM_RD_SEL_1', +} +WBSCL_COEF_RAM_RD_SEL_0 = 0 +WBSCL_COEF_RAM_RD_SEL_1 = 1 +WBSCL_COEF_RAM_RD_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_COEF_RAM_TAP_COEF_EN_ENUM' +WBSCL_COEF_RAM_TAP_COEF_EN_ENUM__enumvalues = { + 0: 'WBSCL_COEF_RAM_TAP_COEF_DISABLE', + 1: 'WBSCL_COEF_RAM_TAP_COEF_ENABLE', +} +WBSCL_COEF_RAM_TAP_COEF_DISABLE = 0 +WBSCL_COEF_RAM_TAP_COEF_ENABLE = 1 +WBSCL_COEF_RAM_TAP_COEF_EN_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_NUM_OF_TAPS_ENUM' +WBSCL_NUM_OF_TAPS_ENUM__enumvalues = { + 0: 'WBSCL_NUM_OF_TAPS0', + 1: 'WBSCL_NUM_OF_TAPS1', + 2: 'WBSCL_NUM_OF_TAPS2', + 3: 'WBSCL_NUM_OF_TAPS3', + 4: 'WBSCL_NUM_OF_TAPS4', + 5: 'WBSCL_NUM_OF_TAPS5', + 6: 'WBSCL_NUM_OF_TAPS6', + 7: 'WBSCL_NUM_OF_TAPS7', + 8: 'WBSCL_NUM_OF_TAPS8', + 9: 'WBSCL_NUM_OF_TAPS9', + 10: 'WBSCL_NUM_OF_TAPS10', + 11: 'WBSCL_NUM_OF_TAPS11', +} +WBSCL_NUM_OF_TAPS0 = 0 +WBSCL_NUM_OF_TAPS1 = 1 +WBSCL_NUM_OF_TAPS2 = 2 +WBSCL_NUM_OF_TAPS3 = 3 +WBSCL_NUM_OF_TAPS4 = 4 +WBSCL_NUM_OF_TAPS5 = 5 +WBSCL_NUM_OF_TAPS6 = 6 +WBSCL_NUM_OF_TAPS7 = 7 +WBSCL_NUM_OF_TAPS8 = 8 +WBSCL_NUM_OF_TAPS9 = 9 +WBSCL_NUM_OF_TAPS10 = 10 +WBSCL_NUM_OF_TAPS11 = 11 +WBSCL_NUM_OF_TAPS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_STATUS_ACK_ENUM' +WBSCL_STATUS_ACK_ENUM__enumvalues = { + 0: 'WBSCL_STATUS_ACK_NCLR', + 1: 'WBSCL_STATUS_ACK_CLR', +} +WBSCL_STATUS_ACK_NCLR = 0 +WBSCL_STATUS_ACK_CLR = 1 +WBSCL_STATUS_ACK_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_STATUS_MASK_ENUM' +WBSCL_STATUS_MASK_ENUM__enumvalues = { + 0: 'WBSCL_STATUS_MASK_DISABLE', + 1: 'WBSCL_STATUS_MASK_ENABLE', +} +WBSCL_STATUS_MASK_DISABLE = 0 +WBSCL_STATUS_MASK_ENABLE = 1 +WBSCL_STATUS_MASK_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM' +WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM__enumvalues = { + 0: 'WBSCL_DATA_OVERFLOW_INT_TYPE_REG', + 1: 'WBSCL_DATA_OVERFLOW_INT_TYPE_HW', +} +WBSCL_DATA_OVERFLOW_INT_TYPE_REG = 0 +WBSCL_DATA_OVERFLOW_INT_TYPE_HW = 1 +WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_HOST_CONFLICT_INT_TYPE_ENUM' +WBSCL_HOST_CONFLICT_INT_TYPE_ENUM__enumvalues = { + 0: 'WBSCL_HOST_CONFLICT_INT_TYPE_REG', + 1: 'WBSCL_HOST_CONFLICT_INT_TYPE_HW', +} +WBSCL_HOST_CONFLICT_INT_TYPE_REG = 0 +WBSCL_HOST_CONFLICT_INT_TYPE_HW = 1 +WBSCL_HOST_CONFLICT_INT_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_TEST_CRC_EN_ENUM' +WBSCL_TEST_CRC_EN_ENUM__enumvalues = { + 0: 'WBSCL_TEST_CRC_DISABLE', + 1: 'WBSCL_TEST_CRC_ENABLE', +} +WBSCL_TEST_CRC_DISABLE = 0 +WBSCL_TEST_CRC_ENABLE = 1 +WBSCL_TEST_CRC_EN_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_TEST_CRC_CONT_EN_ENUM' +WBSCL_TEST_CRC_CONT_EN_ENUM__enumvalues = { + 0: 'WBSCL_TEST_CRC_CONT_DISABLE', + 1: 'WBSCL_TEST_CRC_CONT_ENABLE', +} +WBSCL_TEST_CRC_CONT_DISABLE = 0 +WBSCL_TEST_CRC_CONT_ENABLE = 1 +WBSCL_TEST_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_TEST_CRC_MASK_ENUM' +WBSCL_TEST_CRC_MASK_ENUM__enumvalues = { + 0: 'WBSCL_TEST_CRC_MASKED', + 1: 'WBSCL_TEST_CRC_UNMASKED', +} +WBSCL_TEST_CRC_MASKED = 0 +WBSCL_TEST_CRC_UNMASKED = 1 +WBSCL_TEST_CRC_MASK_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_BACKPRESSURE_CNT_EN_ENUM' +WBSCL_BACKPRESSURE_CNT_EN_ENUM__enumvalues = { + 0: 'WBSCL_BACKPRESSURE_CNT_DISABLE', + 1: 'WBSCL_BACKPRESSURE_CNT_ENABLE', +} +WBSCL_BACKPRESSURE_CNT_DISABLE = 0 +WBSCL_BACKPRESSURE_CNT_ENABLE = 1 +WBSCL_BACKPRESSURE_CNT_EN_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'WBSCL_OUTSIDE_PIX_STRATEGY_ENUM' +WBSCL_OUTSIDE_PIX_STRATEGY_ENUM__enumvalues = { + 0: 'WBSCL_OUTSIDE_PIX_STRATEGY_BLACK', + 1: 'WBSCL_OUTSIDE_PIX_STRATEGY_EDGE', +} +WBSCL_OUTSIDE_PIX_STRATEGY_BLACK = 0 +WBSCL_OUTSIDE_PIX_STRATEGY_EDGE = 1 +WBSCL_OUTSIDE_PIX_STRATEGY_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL' +DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL__enumvalues = { + 0: 'DPCSRX_BPHY_PCS_RX0_CLK', + 1: 'DPCSRX_BPHY_PCS_RX1_CLK', + 2: 'DPCSRX_BPHY_PCS_RX2_CLK', + 3: 'DPCSRX_BPHY_PCS_RX3_CLK', +} +DPCSRX_BPHY_PCS_RX0_CLK = 0 +DPCSRX_BPHY_PCS_RX1_CLK = 1 +DPCSRX_BPHY_PCS_RX2_CLK = 2 +DPCSRX_BPHY_PCS_RX3_CLK = 3 +DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSTX_DVI_LINK_MODE' +DPCSTX_DVI_LINK_MODE__enumvalues = { + 0: 'DPCSTX_DVI_LINK_MODE_NORMAL', + 1: 'DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER', + 2: 'DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER', +} +DPCSTX_DVI_LINK_MODE_NORMAL = 0 +DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER = 1 +DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER = 2 +DPCSTX_DVI_LINK_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET' +RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET__enumvalues = { + 0: 'RDPCS_CBUS_SOFT_RESET_DISABLE', + 1: 'RDPCS_CBUS_SOFT_RESET_ENABLE', +} +RDPCS_CBUS_SOFT_RESET_DISABLE = 0 +RDPCS_CBUS_SOFT_RESET_ENABLE = 1 +RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET' +RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET__enumvalues = { + 0: 'RDPCS_SRAM_SRAM_RESET_DISABLE', +} +RDPCS_SRAM_SRAM_RESET_DISABLE = 0 +RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN' +RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN__enumvalues = { + 0: 'RDPCS_TX_FIFO_LANE_DISABLE', + 1: 'RDPCS_TX_FIFO_LANE_ENABLE', +} +RDPCS_TX_FIFO_LANE_DISABLE = 0 +RDPCS_TX_FIFO_LANE_ENABLE = 1 +RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_FIFO_EN' +RDPCSTX_CNTL_RDPCS_TX_FIFO_EN__enumvalues = { + 0: 'RDPCS_TX_FIFO_DISABLE', + 1: 'RDPCS_TX_FIFO_ENABLE', +} +RDPCS_TX_FIFO_DISABLE = 0 +RDPCS_TX_FIFO_ENABLE = 1 +RDPCSTX_CNTL_RDPCS_TX_FIFO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET' +RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET__enumvalues = { + 0: 'RDPCS_TX_SOFT_RESET_DISABLE', + 1: 'RDPCS_TX_SOFT_RESET_ENABLE', +} +RDPCS_TX_SOFT_RESET_DISABLE = 0 +RDPCS_TX_SOFT_RESET_ENABLE = 1 +RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN' +RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN__enumvalues = { + 0: 'RDPCS_EXT_REFCLK_DISABLE', + 1: 'RDPCS_EXT_REFCLK_ENABLE', +} +RDPCS_EXT_REFCLK_DISABLE = 0 +RDPCS_EXT_REFCLK_ENABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN' +RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN__enumvalues = { + 0: 'RDPCS_EXT_REFCLK_EN_DISABLE', + 1: 'RDPCS_EXT_REFCLK_EN_ENABLE', +} +RDPCS_EXT_REFCLK_EN_DISABLE = 0 +RDPCS_EXT_REFCLK_EN_ENABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS' +RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS__enumvalues = { + 0: 'RDPCS_SYMCLK_DIV2_GATE_ENABLE', + 1: 'RDPCS_SYMCLK_DIV2_GATE_DISABLE', +} +RDPCS_SYMCLK_DIV2_GATE_ENABLE = 0 +RDPCS_SYMCLK_DIV2_GATE_DISABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN' +RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN__enumvalues = { + 0: 'RDPCS_SYMCLK_DIV2_DISABLE', + 1: 'RDPCS_SYMCLK_DIV2_ENABLE', +} +RDPCS_SYMCLK_DIV2_DISABLE = 0 +RDPCS_SYMCLK_DIV2_ENABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON' +RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON__enumvalues = { + 0: 'RDPCS_SYMCLK_DIV2_CLOCK_OFF', + 1: 'RDPCS_SYMCLK_DIV2_CLOCK_ON', +} +RDPCS_SYMCLK_DIV2_CLOCK_OFF = 0 +RDPCS_SYMCLK_DIV2_CLOCK_ON = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS' +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS__enumvalues = { + 0: 'RDPCS_SRAMCLK_GATE_ENABLE', + 1: 'RDPCS_SRAMCLK_GATE_DISABLE', +} +RDPCS_SRAMCLK_GATE_ENABLE = 0 +RDPCS_SRAMCLK_GATE_DISABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN' +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN__enumvalues = { + 0: 'RDPCS_SRAMCLK_DISABLE', + 1: 'RDPCS_SRAMCLK_ENABLE', +} +RDPCS_SRAMCLK_DISABLE = 0 +RDPCS_SRAMCLK_ENABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS' +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS__enumvalues = { + 0: 'RDPCS_SRAMCLK_NOT_BYPASS', + 1: 'RDPCS_SRAMCLK_BYPASS', +} +RDPCS_SRAMCLK_NOT_BYPASS = 0 +RDPCS_SRAMCLK_BYPASS = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON' +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON__enumvalues = { + 0: 'RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF', + 1: 'RDPCS_SYMCLK_SRAMCLK_CLOCK_ON', +} +RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF = 0 +RDPCS_SYMCLK_SRAMCLK_CLOCK_ON = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE' +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE__enumvalues = { + 0: 'RDPCS_DPALT_DISABLE_TOGGLE_ENABLE', + 1: 'RDPCS_DPALT_DISABLE_TOGGLE_DISABLE', +} +RDPCS_DPALT_DISABLE_TOGGLE_ENABLE = 0 +RDPCS_DPALT_DISABLE_TOGGLE_DISABLE = 1 +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE' +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE__enumvalues = { + 0: 'RDPCS_DPALT_4LANE_TOGGLE_2LANE', + 1: 'RDPCS_DPALT_4LANE_TOGGLE_4LANE', +} +RDPCS_DPALT_4LANE_TOGGLE_2LANE = 0 +RDPCS_DPALT_4LANE_TOGGLE_4LANE = 1 +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK' +RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK__enumvalues = { + 0: 'RDPCS_REG_FIFO_ERROR_MASK_DISABLE', + 1: 'RDPCS_REG_FIFO_ERROR_MASK_ENABLE', +} +RDPCS_REG_FIFO_ERROR_MASK_DISABLE = 0 +RDPCS_REG_FIFO_ERROR_MASK_ENABLE = 1 +RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK' +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK__enumvalues = { + 0: 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE', + 1: 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE', +} +RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0 +RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 1 +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK' +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK__enumvalues = { + 0: 'RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE', + 1: 'RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE', +} +RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0 +RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE = 1 +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK' +RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK__enumvalues = { + 0: 'RDPCS_TX_FIFO_ERROR_MASK_DISABLE', + 1: 'RDPCS_TX_FIFO_ERROR_MASK_ENABLE', +} +RDPCS_TX_FIFO_ERROR_MASK_DISABLE = 0 +RDPCS_TX_FIFO_ERROR_MASK_ENABLE = 1 +RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE' +RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE__enumvalues = { + 0: 'RDPCS_MEM_PWR_NO_FORCE', + 1: 'RDPCS_MEM_PWR_LIGHT_SLEEP', + 2: 'RDPCS_MEM_PWR_DEEP_SLEEP', + 3: 'RDPCS_MEM_PWR_SHUT_DOWN', +} +RDPCS_MEM_PWR_NO_FORCE = 0 +RDPCS_MEM_PWR_LIGHT_SLEEP = 1 +RDPCS_MEM_PWR_DEEP_SLEEP = 2 +RDPCS_MEM_PWR_SHUT_DOWN = 3 +RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE' +RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE__enumvalues = { + 0: 'RDPCS_MEM_PWR_PWR_STATE_ON', + 1: 'RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP', + 2: 'RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP', + 3: 'RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN', +} +RDPCS_MEM_PWR_PWR_STATE_ON = 0 +RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 1 +RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP = 2 +RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN = 3 +RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF' +RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF__enumvalues = { + 0: 'RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY', + 1: 'RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD', + 2: 'RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3', + 3: 'RDPCS_MEM_POWER_CTRL_POFF_FOR_SD', +} +RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY = 0 +RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD = 1 +RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3 = 2 +RDPCS_MEM_POWER_CTRL_POFF_FOR_SD = 3 +RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE' +RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE__enumvalues = { + 0: 'RDPCS_PHY_REF_RANGE_0', + 1: 'RDPCS_PHY_REF_RANGE_1', + 2: 'RDPCS_PHY_REF_RANGE_2', + 3: 'RDPCS_PHY_REF_RANGE_3', + 4: 'RDPCS_PHY_REF_RANGE_4', + 5: 'RDPCS_PHY_REF_RANGE_5', + 6: 'RDPCS_PHY_REF_RANGE_6', + 7: 'RDPCS_PHY_REF_RANGE_7', +} +RDPCS_PHY_REF_RANGE_0 = 0 +RDPCS_PHY_REF_RANGE_1 = 1 +RDPCS_PHY_REF_RANGE_2 = 2 +RDPCS_PHY_REF_RANGE_3 = 3 +RDPCS_PHY_REF_RANGE_4 = 4 +RDPCS_PHY_REF_RANGE_5 = 5 +RDPCS_PHY_REF_RANGE_6 = 6 +RDPCS_PHY_REF_RANGE_7 = 7 +RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL' +RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL__enumvalues = { + 0: 'RDPCS_PHY_CR_PARA_SEL_JTAG', + 1: 'RDPCS_PHY_CR_PARA_SEL_CR', +} +RDPCS_PHY_CR_PARA_SEL_JTAG = 0 +RDPCS_PHY_CR_PARA_SEL_CR = 1 +RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL' +RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL__enumvalues = { + 0: 'RDPCS_PHY_CR_MUX_SEL_FOR_USB', + 1: 'RDPCS_PHY_CR_MUX_SEL_FOR_DC', +} +RDPCS_PHY_CR_MUX_SEL_FOR_USB = 0 +RDPCS_PHY_CR_MUX_SEL_FOR_DC = 1 +RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE' +RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE__enumvalues = { + 0: 'RDPCS_SRAM_INIT_NOT_DONE', + 1: 'RDPCS_SRAM_INIT_DONE', +} +RDPCS_SRAM_INIT_NOT_DONE = 0 +RDPCS_SRAM_INIT_DONE = 1 +RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE' +RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE__enumvalues = { + 0: 'RDPCS_SRAM_EXT_LD_NOT_DONE', + 1: 'RDPCS_SRAM_EXT_LD_DONE', +} +RDPCS_SRAM_EXT_LD_NOT_DONE = 0 +RDPCS_SRAM_EXT_LD_DONE = 1 +RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL' +RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL__enumvalues = { + 0: 'RDPCS_PHY_DP_TX_TERM_CTRL_54', + 1: 'RDPCS_PHY_DP_TX_TERM_CTRL_52', + 2: 'RDPCS_PHY_DP_TX_TERM_CTRL_50', + 3: 'RDPCS_PHY_DP_TX_TERM_CTRL_48', + 4: 'RDPCS_PHY_DP_TX_TERM_CTRL_46', + 5: 'RDPCS_PHY_DP_TX_TERM_CTRL_44', + 6: 'RDPCS_PHY_DP_TX_TERM_CTRL_42', + 7: 'RDPCS_PHY_DP_TX_TERM_CTRL_40', +} +RDPCS_PHY_DP_TX_TERM_CTRL_54 = 0 +RDPCS_PHY_DP_TX_TERM_CTRL_52 = 1 +RDPCS_PHY_DP_TX_TERM_CTRL_50 = 2 +RDPCS_PHY_DP_TX_TERM_CTRL_48 = 3 +RDPCS_PHY_DP_TX_TERM_CTRL_46 = 4 +RDPCS_PHY_DP_TX_TERM_CTRL_44 = 5 +RDPCS_PHY_DP_TX_TERM_CTRL_42 = 6 +RDPCS_PHY_DP_TX_TERM_CTRL_40 = 7 +RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE' +RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE__enumvalues = { + 0: 'RRDPCS_PHY_DP_TX_PSTATE_POWER_UP', + 1: 'RRDPCS_PHY_DP_TX_PSTATE_HOLD', + 2: 'RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF', + 3: 'RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN', +} +RRDPCS_PHY_DP_TX_PSTATE_POWER_UP = 0 +RRDPCS_PHY_DP_TX_PSTATE_HOLD = 1 +RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF = 2 +RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN = 3 +RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE' +RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE__enumvalues = { + 0: 'RDPCS_PHY_DP_TX_RATE', + 1: 'RDPCS_PHY_DP_TX_RATE_DIV2', + 2: 'RDPCS_PHY_DP_TX_RATE_DIV4', +} +RDPCS_PHY_DP_TX_RATE = 0 +RDPCS_PHY_DP_TX_RATE_DIV2 = 1 +RDPCS_PHY_DP_TX_RATE_DIV4 = 2 +RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH' +RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH__enumvalues = { + 0: 'RDPCS_PHY_DP_TX_WIDTH_8', + 1: 'RDPCS_PHY_DP_TX_WIDTH_10', + 2: 'RDPCS_PHY_DP_TX_WIDTH_16', + 3: 'RDPCS_PHY_DP_TX_WIDTH_20', +} +RDPCS_PHY_DP_TX_WIDTH_8 = 0 +RDPCS_PHY_DP_TX_WIDTH_10 = 1 +RDPCS_PHY_DP_TX_WIDTH_16 = 2 +RDPCS_PHY_DP_TX_WIDTH_20 = 3 +RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT' +RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT__enumvalues = { + 0: 'RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT', + 1: 'RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT', +} +RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0 +RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT = 1 +RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV' +RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__enumvalues = { + 0: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1', + 1: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2', + 2: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3', + 3: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8', + 4: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16', +} +RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1 = 0 +RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2 = 1 +RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3 = 2 +RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8 = 3 +RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16 = 4 +RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV' +RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__enumvalues = { + 0: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', + 1: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', + 2: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', + 3: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', +} +RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0 +RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 1 +RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 2 +RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 3 +RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV' +RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__enumvalues = { + 0: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', + 1: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2', + 2: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4', + 3: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8', + 4: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3', + 5: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5', + 6: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6', + 7: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10', +} +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2 = 1 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4 = 2 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8 = 3 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3 = 4 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5 = 5 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6 = 6 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10 = 7 +RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_TEST_CLK_SEL' +RDPCS_TEST_CLK_SEL__enumvalues = { + 0: 'RDPCS_TEST_CLK_SEL_NONE', + 1: 'RDPCS_TEST_CLK_SEL_CFGCLK', + 2: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', + 3: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', + 4: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', + 5: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', + 6: 'RDPCS_TEST_CLK_SEL_SRAMCLK', + 7: 'RDPCS_TEST_CLK_SEL_EXT_CR_CLK', + 8: 'RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK', + 9: 'RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK', + 10: 'RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK', + 11: 'RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK', + 12: 'RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', + 13: 'RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', + 14: 'RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK', + 15: 'RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk', + 16: 'RDPCS_TEST_CLK_SEL_dtb_out0', + 17: 'RDPCS_TEST_CLK_SEL_dtb_out1', +} +RDPCS_TEST_CLK_SEL_NONE = 0 +RDPCS_TEST_CLK_SEL_CFGCLK = 1 +RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 2 +RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 3 +RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 4 +RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 5 +RDPCS_TEST_CLK_SEL_SRAMCLK = 6 +RDPCS_TEST_CLK_SEL_EXT_CR_CLK = 7 +RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK = 8 +RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK = 9 +RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK = 10 +RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK = 11 +RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 12 +RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 13 +RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK = 14 +RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk = 15 +RDPCS_TEST_CLK_SEL_dtb_out0 = 16 +RDPCS_TEST_CLK_SEL_dtb_out1 = 17 +RDPCS_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CBMode' +CBMode__enumvalues = { + 0: 'CB_DISABLE', + 1: 'CB_NORMAL', + 2: 'CB_ELIMINATE_FAST_CLEAR', + 3: 'CB_RESOLVE', + 4: 'CB_DECOMPRESS', + 5: 'CB_FMASK_DECOMPRESS', + 6: 'CB_DCC_DECOMPRESS', + 7: 'CB_RESERVED', +} +CB_DISABLE = 0 +CB_NORMAL = 1 +CB_ELIMINATE_FAST_CLEAR = 2 +CB_RESOLVE = 3 +CB_DECOMPRESS = 4 +CB_FMASK_DECOMPRESS = 5 +CB_DCC_DECOMPRESS = 6 +CB_RESERVED = 7 +CBMode = ctypes.c_uint32 # enum + +# values for enumeration 'BlendOp' +BlendOp__enumvalues = { + 0: 'BLEND_ZERO', + 1: 'BLEND_ONE', + 2: 'BLEND_SRC_COLOR', + 3: 'BLEND_ONE_MINUS_SRC_COLOR', + 4: 'BLEND_SRC_ALPHA', + 5: 'BLEND_ONE_MINUS_SRC_ALPHA', + 6: 'BLEND_DST_ALPHA', + 7: 'BLEND_ONE_MINUS_DST_ALPHA', + 8: 'BLEND_DST_COLOR', + 9: 'BLEND_ONE_MINUS_DST_COLOR', + 10: 'BLEND_SRC_ALPHA_SATURATE', + 11: 'BLEND_BOTH_SRC_ALPHA', + 12: 'BLEND_BOTH_INV_SRC_ALPHA', + 13: 'BLEND_CONSTANT_COLOR', + 14: 'BLEND_ONE_MINUS_CONSTANT_COLOR', + 15: 'BLEND_SRC1_COLOR', + 16: 'BLEND_INV_SRC1_COLOR', + 17: 'BLEND_SRC1_ALPHA', + 18: 'BLEND_INV_SRC1_ALPHA', + 19: 'BLEND_CONSTANT_ALPHA', + 20: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', +} +BLEND_ZERO = 0 +BLEND_ONE = 1 +BLEND_SRC_COLOR = 2 +BLEND_ONE_MINUS_SRC_COLOR = 3 +BLEND_SRC_ALPHA = 4 +BLEND_ONE_MINUS_SRC_ALPHA = 5 +BLEND_DST_ALPHA = 6 +BLEND_ONE_MINUS_DST_ALPHA = 7 +BLEND_DST_COLOR = 8 +BLEND_ONE_MINUS_DST_COLOR = 9 +BLEND_SRC_ALPHA_SATURATE = 10 +BLEND_BOTH_SRC_ALPHA = 11 +BLEND_BOTH_INV_SRC_ALPHA = 12 +BLEND_CONSTANT_COLOR = 13 +BLEND_ONE_MINUS_CONSTANT_COLOR = 14 +BLEND_SRC1_COLOR = 15 +BLEND_INV_SRC1_COLOR = 16 +BLEND_SRC1_ALPHA = 17 +BLEND_INV_SRC1_ALPHA = 18 +BLEND_CONSTANT_ALPHA = 19 +BLEND_ONE_MINUS_CONSTANT_ALPHA = 20 +BlendOp = ctypes.c_uint32 # enum +GL__ZERO = BLEND_ZERO # macro +GL__ONE = BLEND_ONE # macro +GL__SRC_COLOR = BLEND_SRC_COLOR # macro +GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro +GL__DST_COLOR = BLEND_DST_COLOR # macro +GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro +GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro +GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro +GL__DST_ALPHA = BLEND_DST_ALPHA # macro +GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro +GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro +GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro +GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro +GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro +GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro + +# values for enumeration 'CombFunc' +CombFunc__enumvalues = { + 0: 'COMB_DST_PLUS_SRC', + 1: 'COMB_SRC_MINUS_DST', + 2: 'COMB_MIN_DST_SRC', + 3: 'COMB_MAX_DST_SRC', + 4: 'COMB_DST_MINUS_SRC', +} +COMB_DST_PLUS_SRC = 0 +COMB_SRC_MINUS_DST = 1 +COMB_MIN_DST_SRC = 2 +COMB_MAX_DST_SRC = 3 +COMB_DST_MINUS_SRC = 4 +CombFunc = ctypes.c_uint32 # enum + +# values for enumeration 'BlendOpt' +BlendOpt__enumvalues = { + 0: 'FORCE_OPT_AUTO', + 1: 'FORCE_OPT_DISABLE', + 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', + 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', + 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', +} +FORCE_OPT_AUTO = 0 +FORCE_OPT_DISABLE = 1 +FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 +FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 +FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 +FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 +FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 +FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 +BlendOpt = ctypes.c_uint32 # enum + +# values for enumeration 'CmaskCode' +CmaskCode__enumvalues = { + 0: 'CMASK_CLR00_F0', + 1: 'CMASK_CLR00_F1', + 2: 'CMASK_CLR00_F2', + 3: 'CMASK_CLR00_FX', + 4: 'CMASK_CLR01_F0', + 5: 'CMASK_CLR01_F1', + 6: 'CMASK_CLR01_F2', + 7: 'CMASK_CLR01_FX', + 8: 'CMASK_CLR10_F0', + 9: 'CMASK_CLR10_F1', + 10: 'CMASK_CLR10_F2', + 11: 'CMASK_CLR10_FX', + 12: 'CMASK_CLR11_F0', + 13: 'CMASK_CLR11_F1', + 14: 'CMASK_CLR11_F2', + 15: 'CMASK_CLR11_FX', +} +CMASK_CLR00_F0 = 0 +CMASK_CLR00_F1 = 1 +CMASK_CLR00_F2 = 2 +CMASK_CLR00_FX = 3 +CMASK_CLR01_F0 = 4 +CMASK_CLR01_F1 = 5 +CMASK_CLR01_F2 = 6 +CMASK_CLR01_FX = 7 +CMASK_CLR10_F0 = 8 +CMASK_CLR10_F1 = 9 +CMASK_CLR10_F2 = 10 +CMASK_CLR10_FX = 11 +CMASK_CLR11_F0 = 12 +CMASK_CLR11_F1 = 13 +CMASK_CLR11_F2 = 14 +CMASK_CLR11_FX = 15 +CmaskCode = ctypes.c_uint32 # enum + +# values for enumeration 'MemArbMode' +MemArbMode__enumvalues = { + 0: 'MEM_ARB_MODE_FIXED', + 1: 'MEM_ARB_MODE_AGE', + 2: 'MEM_ARB_MODE_WEIGHT', + 3: 'MEM_ARB_MODE_BOTH', +} +MEM_ARB_MODE_FIXED = 0 +MEM_ARB_MODE_AGE = 1 +MEM_ARB_MODE_WEIGHT = 2 +MEM_ARB_MODE_BOTH = 3 +MemArbMode = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfOpFilterSel' +CBPerfOpFilterSel__enumvalues = { + 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', +} +CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 +CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 +CB_PERF_OP_FILTER_SEL_RESOLVE = 2 +CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 +CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 +CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 +CBPerfOpFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfClearFilterSel' +CBPerfClearFilterSel__enumvalues = { + 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', +} +CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 +CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 +CBPerfClearFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfSel' +CBPerfSel__enumvalues = { + 0: 'CB_PERF_SEL_NONE', + 1: 'CB_PERF_SEL_BUSY', + 2: 'CB_PERF_SEL_CORE_SCLK_VLD', + 3: 'CB_PERF_SEL_REG_SCLK0_VLD', + 4: 'CB_PERF_SEL_REG_SCLK1_VLD', + 5: 'CB_PERF_SEL_DRAWN_QUAD', + 6: 'CB_PERF_SEL_DRAWN_PIXEL', + 7: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', + 8: 'CB_PERF_SEL_DRAWN_TILE', + 9: 'CB_PERF_SEL_DB_CB_TILE_VALID_READY', + 10: 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB', + 11: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY', + 12: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB', + 13: 'CB_PERF_SEL_CM_FC_TILE_VALID_READY', + 14: 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB', + 15: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY', + 16: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB', + 17: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY', + 18: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB', + 19: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY', + 20: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB', + 21: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY', + 22: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB', + 23: 'CB_PERF_SEL_LQUAD_NO_TILE', + 24: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R', + 25: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR', + 26: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR', + 27: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR', + 28: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR', + 29: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR', + 30: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR', + 31: 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT', + 32: 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID', + 33: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK', + 34: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK', + 35: 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL', + 36: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY', + 37: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB', + 38: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY', + 39: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB', + 40: 'CB_PERF_SEL_FOP_IN_VALID_READY', + 41: 'CB_PERF_SEL_FOP_IN_VALID_READYB', + 42: 'CB_PERF_SEL_FOP_IN_VALIDB_READY', + 43: 'CB_PERF_SEL_FOP_IN_VALIDB_READYB', + 44: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY', + 45: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB', + 46: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY', + 47: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB', + 48: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY', + 49: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB', + 50: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY', + 51: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB', + 52: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY', + 53: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB', + 54: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY', + 55: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB', + 56: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY', + 57: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB', + 58: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY', + 59: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB', + 60: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY', + 61: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB', + 62: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY', + 63: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB', + 64: 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID', + 65: 'CB_PERF_SEL_CM_CACHE_HIT', + 66: 'CB_PERF_SEL_CM_CACHE_TAG_MISS', + 67: 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', + 68: 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL', + 69: 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 70: 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL', + 71: 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 72: 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL', + 73: 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL', + 74: 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL', + 75: 'CB_PERF_SEL_CM_CACHE_STALL', + 76: 'CB_PERF_SEL_CM_CACHE_FLUSH', + 77: 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED', + 78: 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED', + 79: 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED', + 80: 'CB_PERF_SEL_FC_CACHE_HIT', + 81: 'CB_PERF_SEL_FC_CACHE_TAG_MISS', + 82: 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', + 83: 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL', + 84: 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 85: 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL', + 86: 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 87: 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL', + 88: 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL', + 89: 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL', + 90: 'CB_PERF_SEL_FC_CACHE_STALL', + 91: 'CB_PERF_SEL_FC_CACHE_FLUSH', + 92: 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED', + 93: 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED', + 94: 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED', + 95: 'CB_PERF_SEL_CC_CACHE_HIT', + 96: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 97: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', + 98: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', + 99: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 100: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', + 101: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 102: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 103: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 104: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 105: 'CB_PERF_SEL_CC_CACHE_STALL', + 106: 'CB_PERF_SEL_CC_CACHE_FLUSH', + 107: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', + 108: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 109: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', + 110: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 111: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY', + 112: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB', + 113: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY', + 114: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB', + 115: 'CB_PERF_SEL_CM_MC_WRITE_REQUEST', + 116: 'CB_PERF_SEL_FC_MC_WRITE_REQUEST', + 117: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', + 118: 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT', + 119: 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT', + 120: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', + 121: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY', + 122: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB', + 123: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY', + 124: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB', + 125: 'CB_PERF_SEL_CM_MC_READ_REQUEST', + 126: 'CB_PERF_SEL_FC_MC_READ_REQUEST', + 127: 'CB_PERF_SEL_CC_MC_READ_REQUEST', + 128: 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT', + 129: 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT', + 130: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', + 131: 'CB_PERF_SEL_CM_TQ_FULL', + 132: 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL', + 133: 'CB_PERF_SEL_CM_TQ_FIFO_STUTTER_STALL', + 134: 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL', + 135: 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL', + 136: 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL', + 137: 'CB_PERF_SEL_FC_TILE_STUTTER_STALL', + 138: 'CB_PERF_SEL_FC_QUAD_STUTTER_STALL', + 139: 'CB_PERF_SEL_FC_KEYID_STUTTER_STALL', + 140: 'CB_PERF_SEL_FOP_FMASK_RAW_STALL', + 141: 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL', + 142: 'CB_PERF_SEL_CC_SF_FULL', + 143: 'CB_PERF_SEL_CC_RB_FULL', + 144: 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL', + 145: 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL', + 146: 'CB_PERF_SEL_CC_EVENFIFO_STUTTER_STALL', + 147: 'CB_PERF_SEL_CC_ODDFIFO_STUTTER_STALL', + 148: 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL', + 149: 'CB_PERF_SEL_EVENT', + 150: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 151: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 152: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 153: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 154: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 155: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 156: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 157: 'CB_PERF_SEL_CC_SURFACE_SYNC', + 158: 'CB_PERF_SEL_CMASK_READ_DATA_0xC', + 159: 'CB_PERF_SEL_CMASK_READ_DATA_0xD', + 160: 'CB_PERF_SEL_CMASK_READ_DATA_0xE', + 161: 'CB_PERF_SEL_CMASK_READ_DATA_0xF', + 162: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC', + 163: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD', + 164: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE', + 165: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF', + 166: 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', + 167: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', + 168: 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT', + 169: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE', + 170: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE', + 171: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE', + 172: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE', + 173: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE', + 174: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE', + 175: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE', + 176: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE', + 177: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE', + 178: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE', + 179: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE', + 180: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE', + 181: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE', + 182: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE', + 183: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE', + 184: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE', + 185: 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT', + 186: 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS', + 187: 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS', + 188: 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS', + 189: 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS', + 190: 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS', + 191: 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS', + 192: 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT', + 193: 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS', + 194: 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS', + 195: 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS', + 196: 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS', + 197: 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS', + 198: 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS', + 199: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0', + 200: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1', + 201: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2', + 202: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3', + 203: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4', + 204: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5', + 205: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6', + 206: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7', + 207: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0', + 208: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1', + 209: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2', + 210: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3', + 211: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4', + 212: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5', + 213: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6', + 214: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7', + 215: 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST', + 216: 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS', + 217: 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS', + 218: 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 219: 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 220: 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED', + 221: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', + 222: 'CB_PERF_SEL_DRAWN_BUSY', + 223: 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY', + 224: 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY', + 225: 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY', + 226: 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY', + 227: 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED', + 228: 'CB_PERF_SEL_FC_SEQUENCER_CLEAR', + 229: 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR', + 230: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS', + 231: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE', + 232: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 233: 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL', + 234: 'CB_PERF_SEL_FC_DOC_IS_STALLED', + 235: 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED', + 236: 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED', + 237: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS', + 238: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT', + 239: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS', + 240: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT', + 241: 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL', + 242: 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR', + 243: 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS', + 244: 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS', + 245: 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS', + 246: 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS', + 247: 'CB_PERF_SEL_FC_DCC_CACHE_HIT', + 248: 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS', + 249: 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS', + 250: 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL', + 251: 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 252: 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', + 253: 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 254: 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL', + 255: 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL', + 256: 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL', + 257: 'CB_PERF_SEL_FC_DCC_CACHE_STALL', + 258: 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', + 259: 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED', + 260: 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED', + 261: 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED', + 262: 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT', + 263: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST', + 264: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT', + 265: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST', + 266: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT', + 267: 'CB_PERF_SEL_CC_DCC_RDREQ_STALL', + 268: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN', + 269: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT', + 270: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN', + 271: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT', + 272: 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR', + 273: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1', + 274: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2', + 275: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 276: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1', + 277: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1', + 278: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2', + 279: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1', + 280: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 281: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 282: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1', + 283: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2', + 284: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2', + 285: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2', + 286: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 287: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1', + 288: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1', + 289: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2', + 290: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3', + 291: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4', + 292: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1', + 293: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2', + 294: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3', + 295: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4', + 296: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1', + 297: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2', + 298: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3', + 299: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4', + 300: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1', + 301: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2', + 302: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3', + 303: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1', + 304: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2', + 305: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3', + 306: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4', + 307: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1', + 308: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2', + 309: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3', + 310: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4', + 311: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1', + 312: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2', + 313: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3', + 314: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4', + 315: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1', + 316: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2', + 317: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3', + 318: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1', + 319: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1', + 320: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1', + 321: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1', + 322: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1', + 323: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1', + 324: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1', + 325: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1', + 326: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2', + 327: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2', + 328: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2', + 329: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2', + 330: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2', + 331: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2', + 332: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2', + 333: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1', + 334: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1', + 335: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1', + 336: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1', + 337: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2', + 338: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2', + 339: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2', + 340: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2', + 341: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 342: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2', + 343: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2', + 344: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 345: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1', + 346: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1', + 347: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1', + 348: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1', + 349: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2', + 350: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3', + 351: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4', + 352: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5', + 353: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6', + 354: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0', + 355: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1', + 356: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1', + 357: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2', + 358: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3', + 359: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4', + 360: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5', + 361: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0', + 362: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1', + 363: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1', + 364: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1', + 365: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1', + 366: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1', + 367: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1', + 368: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1', + 369: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1', + 370: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1', + 371: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2', + 372: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2', + 373: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2', + 374: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2', + 375: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2', + 376: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2', + 377: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2', + 378: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1', + 379: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2', + 380: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3', + 381: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4', + 382: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5', + 383: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6', + 384: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7', + 385: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED', + 386: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1', + 387: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1', + 388: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2', + 389: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3', + 390: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1', + 391: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2', + 392: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3', + 393: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4', + 394: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5', + 395: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1', + 396: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2', + 397: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3', + 398: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4', + 399: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5', + 400: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6', + 401: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7', + 402: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', + 403: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', + 404: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', + 405: 'CB_PERF_SEL_RBP_SPLIT_MICROTILE', + 406: 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK', + 407: 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK', + 408: 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING', + 409: 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS', + 410: 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD', + 411: 'CB_PERF_SEL_NACK_CM_READ', + 412: 'CB_PERF_SEL_NACK_CM_WRITE', + 413: 'CB_PERF_SEL_NACK_FC_READ', + 414: 'CB_PERF_SEL_NACK_FC_WRITE', + 415: 'CB_PERF_SEL_NACK_DC_READ', + 416: 'CB_PERF_SEL_NACK_DC_WRITE', + 417: 'CB_PERF_SEL_NACK_CC_READ', + 418: 'CB_PERF_SEL_NACK_CC_WRITE', + 419: 'CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN', + 420: 'CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN', + 421: 'CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN', + 422: 'CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN', + 423: 'CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', + 424: 'CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', + 425: 'CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', + 426: 'CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', + 427: 'CB_PERF_SEL_CM_MC_WRITE_ACK64B', + 428: 'CB_PERF_SEL_FC_MC_WRITE_ACK64B', + 429: 'CB_PERF_SEL_DC_MC_WRITE_ACK64B', + 430: 'CB_PERF_SEL_CC_MC_WRITE_ACK64B', + 431: 'CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS', + 432: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS', + 433: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA', + 434: 'CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT', + 435: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX', + 436: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX', + 437: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX', + 438: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX', + 439: 'CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED', + 440: 'CB_PERF_SEL_DB_CB_CONTEXT_DONE', + 441: 'CB_PERF_SEL_DB_CB_EOP_DONE', + 442: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL', + 443: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD', +} +CB_PERF_SEL_NONE = 0 +CB_PERF_SEL_BUSY = 1 +CB_PERF_SEL_CORE_SCLK_VLD = 2 +CB_PERF_SEL_REG_SCLK0_VLD = 3 +CB_PERF_SEL_REG_SCLK1_VLD = 4 +CB_PERF_SEL_DRAWN_QUAD = 5 +CB_PERF_SEL_DRAWN_PIXEL = 6 +CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 7 +CB_PERF_SEL_DRAWN_TILE = 8 +CB_PERF_SEL_DB_CB_TILE_VALID_READY = 9 +CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 10 +CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 11 +CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 12 +CB_PERF_SEL_CM_FC_TILE_VALID_READY = 13 +CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 14 +CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 15 +CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 16 +CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 17 +CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 18 +CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 19 +CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 20 +CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 21 +CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 22 +CB_PERF_SEL_LQUAD_NO_TILE = 23 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 24 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 25 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 26 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 27 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 28 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 29 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 30 +CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 31 +CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 32 +CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 33 +CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 34 +CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 35 +CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 36 +CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 37 +CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 38 +CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 39 +CB_PERF_SEL_FOP_IN_VALID_READY = 40 +CB_PERF_SEL_FOP_IN_VALID_READYB = 41 +CB_PERF_SEL_FOP_IN_VALIDB_READY = 42 +CB_PERF_SEL_FOP_IN_VALIDB_READYB = 43 +CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 44 +CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 45 +CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 46 +CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 47 +CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 48 +CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 49 +CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 50 +CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 51 +CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 52 +CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 53 +CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 54 +CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 55 +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 56 +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 57 +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 58 +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 59 +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 60 +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 61 +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 62 +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 63 +CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 64 +CB_PERF_SEL_CM_CACHE_HIT = 65 +CB_PERF_SEL_CM_CACHE_TAG_MISS = 66 +CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 67 +CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 68 +CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 69 +CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 70 +CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 71 +CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 72 +CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 73 +CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 74 +CB_PERF_SEL_CM_CACHE_STALL = 75 +CB_PERF_SEL_CM_CACHE_FLUSH = 76 +CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 77 +CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 78 +CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 79 +CB_PERF_SEL_FC_CACHE_HIT = 80 +CB_PERF_SEL_FC_CACHE_TAG_MISS = 81 +CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 82 +CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 83 +CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 84 +CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 85 +CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 86 +CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 87 +CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 88 +CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 89 +CB_PERF_SEL_FC_CACHE_STALL = 90 +CB_PERF_SEL_FC_CACHE_FLUSH = 91 +CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 92 +CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 93 +CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 94 +CB_PERF_SEL_CC_CACHE_HIT = 95 +CB_PERF_SEL_CC_CACHE_TAG_MISS = 96 +CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 97 +CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 98 +CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 99 +CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 100 +CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 101 +CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 102 +CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 103 +CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 104 +CB_PERF_SEL_CC_CACHE_STALL = 105 +CB_PERF_SEL_CC_CACHE_FLUSH = 106 +CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 107 +CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 108 +CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 109 +CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 110 +CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 111 +CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 112 +CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 113 +CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 114 +CB_PERF_SEL_CM_MC_WRITE_REQUEST = 115 +CB_PERF_SEL_FC_MC_WRITE_REQUEST = 116 +CB_PERF_SEL_CC_MC_WRITE_REQUEST = 117 +CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 118 +CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 119 +CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 120 +CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 121 +CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 122 +CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 123 +CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 124 +CB_PERF_SEL_CM_MC_READ_REQUEST = 125 +CB_PERF_SEL_FC_MC_READ_REQUEST = 126 +CB_PERF_SEL_CC_MC_READ_REQUEST = 127 +CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 128 +CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 129 +CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 130 +CB_PERF_SEL_CM_TQ_FULL = 131 +CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 132 +CB_PERF_SEL_CM_TQ_FIFO_STUTTER_STALL = 133 +CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 134 +CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 135 +CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 136 +CB_PERF_SEL_FC_TILE_STUTTER_STALL = 137 +CB_PERF_SEL_FC_QUAD_STUTTER_STALL = 138 +CB_PERF_SEL_FC_KEYID_STUTTER_STALL = 139 +CB_PERF_SEL_FOP_FMASK_RAW_STALL = 140 +CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 141 +CB_PERF_SEL_CC_SF_FULL = 142 +CB_PERF_SEL_CC_RB_FULL = 143 +CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 144 +CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 145 +CB_PERF_SEL_CC_EVENFIFO_STUTTER_STALL = 146 +CB_PERF_SEL_CC_ODDFIFO_STUTTER_STALL = 147 +CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 148 +CB_PERF_SEL_EVENT = 149 +CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 150 +CB_PERF_SEL_EVENT_CONTEXT_DONE = 151 +CB_PERF_SEL_EVENT_CACHE_FLUSH = 152 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 153 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 154 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 155 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 156 +CB_PERF_SEL_CC_SURFACE_SYNC = 157 +CB_PERF_SEL_CMASK_READ_DATA_0xC = 158 +CB_PERF_SEL_CMASK_READ_DATA_0xD = 159 +CB_PERF_SEL_CMASK_READ_DATA_0xE = 160 +CB_PERF_SEL_CMASK_READ_DATA_0xF = 161 +CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 162 +CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 163 +CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 164 +CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 165 +CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 166 +CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 167 +CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 168 +CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 169 +CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 170 +CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 171 +CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 172 +CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 173 +CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 174 +CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 175 +CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 176 +CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 177 +CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 178 +CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 179 +CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 180 +CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 181 +CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 182 +CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 183 +CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 184 +CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 185 +CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 186 +CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 187 +CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 188 +CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 189 +CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 190 +CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 191 +CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 192 +CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 193 +CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 194 +CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 195 +CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 196 +CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 197 +CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 198 +CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 199 +CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 200 +CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 201 +CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 202 +CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 203 +CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 204 +CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 205 +CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 206 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 207 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 208 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 209 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 210 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 211 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 212 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 213 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 214 +CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 215 +CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 216 +CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 217 +CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 218 +CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 219 +CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 220 +CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 221 +CB_PERF_SEL_DRAWN_BUSY = 222 +CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 223 +CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 224 +CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 225 +CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 226 +CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 227 +CB_PERF_SEL_FC_SEQUENCER_CLEAR = 228 +CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 229 +CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 230 +CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 231 +CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 232 +CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 233 +CB_PERF_SEL_FC_DOC_IS_STALLED = 234 +CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 235 +CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 236 +CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 237 +CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 238 +CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 239 +CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 240 +CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 241 +CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 242 +CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 243 +CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 244 +CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 245 +CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 246 +CB_PERF_SEL_FC_DCC_CACHE_HIT = 247 +CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 248 +CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 249 +CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 250 +CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 251 +CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 252 +CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 253 +CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 254 +CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 255 +CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 256 +CB_PERF_SEL_FC_DCC_CACHE_STALL = 257 +CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 258 +CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 259 +CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 260 +CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 261 +CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 262 +CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 263 +CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 264 +CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 265 +CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 266 +CB_PERF_SEL_CC_DCC_RDREQ_STALL = 267 +CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 268 +CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 269 +CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 270 +CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 271 +CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 272 +CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 273 +CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 274 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 275 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 276 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 277 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 278 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 279 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 280 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 281 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 282 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 283 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 284 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 285 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 286 +CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 287 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 288 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 289 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 290 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 291 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 292 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 293 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 294 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 295 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 296 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 297 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 298 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 299 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 300 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 301 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 302 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 303 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 304 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 305 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 306 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 307 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 308 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 309 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 310 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 311 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 312 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 313 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 314 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 315 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 316 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 317 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 318 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 319 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 320 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 321 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 322 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 323 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 324 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 325 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 326 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 327 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 328 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 329 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 330 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 331 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 332 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 333 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 334 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 335 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 336 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 337 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 338 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 339 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 340 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 341 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 342 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 343 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 344 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 345 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 346 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 347 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 348 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 349 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 350 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 351 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 352 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 353 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 354 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 355 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 356 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 357 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 358 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 359 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 360 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 361 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 362 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 363 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 364 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 365 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 366 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 367 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 368 +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 369 +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 370 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 371 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 372 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 373 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 374 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 375 +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 376 +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 377 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 378 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 379 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 380 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 381 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 382 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 383 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 384 +CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 385 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 386 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 387 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 388 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 389 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 390 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 391 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 392 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 393 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 394 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 395 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 396 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 397 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 398 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 399 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 400 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 401 +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 402 +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 403 +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 404 +CB_PERF_SEL_RBP_SPLIT_MICROTILE = 405 +CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 406 +CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 407 +CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 408 +CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 409 +CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 410 +CB_PERF_SEL_NACK_CM_READ = 411 +CB_PERF_SEL_NACK_CM_WRITE = 412 +CB_PERF_SEL_NACK_FC_READ = 413 +CB_PERF_SEL_NACK_FC_WRITE = 414 +CB_PERF_SEL_NACK_DC_READ = 415 +CB_PERF_SEL_NACK_DC_WRITE = 416 +CB_PERF_SEL_NACK_CC_READ = 417 +CB_PERF_SEL_NACK_CC_WRITE = 418 +CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN = 419 +CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN = 420 +CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN = 421 +CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN = 422 +CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 423 +CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 424 +CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 425 +CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 426 +CB_PERF_SEL_CM_MC_WRITE_ACK64B = 427 +CB_PERF_SEL_FC_MC_WRITE_ACK64B = 428 +CB_PERF_SEL_DC_MC_WRITE_ACK64B = 429 +CB_PERF_SEL_CC_MC_WRITE_ACK64B = 430 +CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS = 431 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS = 432 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA = 433 +CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT = 434 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX = 435 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX = 436 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX = 437 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX = 438 +CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED = 439 +CB_PERF_SEL_DB_CB_CONTEXT_DONE = 440 +CB_PERF_SEL_DB_CB_EOP_DONE = 441 +CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL = 442 +CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD = 443 +CBPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'CmaskAddr' +CmaskAddr__enumvalues = { + 0: 'CMASK_ADDR_TILED', + 1: 'CMASK_ADDR_LINEAR', + 2: 'CMASK_ADDR_COMPATIBLE', +} +CMASK_ADDR_TILED = 0 +CMASK_ADDR_LINEAR = 1 +CMASK_ADDR_COMPATIBLE = 2 +CmaskAddr = ctypes.c_uint32 # enum + +# values for enumeration 'SourceFormat' +SourceFormat__enumvalues = { + 0: 'EXPORT_4C_32BPC', + 1: 'EXPORT_4C_16BPC', + 2: 'EXPORT_2C_32BPC_GR', + 3: 'EXPORT_2C_32BPC_AR', +} +EXPORT_4C_32BPC = 0 +EXPORT_4C_16BPC = 1 +EXPORT_2C_32BPC_GR = 2 +EXPORT_2C_32BPC_AR = 3 +SourceFormat = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP_MASKS' +TC_OP_MASKS__enumvalues = { + 8: 'TC_OP_MASK_FLUSH_DENROM', + 32: 'TC_OP_MASK_64', + 64: 'TC_OP_MASK_NO_RTN', +} +TC_OP_MASK_FLUSH_DENROM = 8 +TC_OP_MASK_64 = 32 +TC_OP_MASK_NO_RTN = 64 +TC_OP_MASKS = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP' +TC_OP__enumvalues = { + 0: 'TC_OP_READ', + 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', + 2: 'TC_OP_ATOMIC_FMIN_RTN_32', + 3: 'TC_OP_ATOMIC_FMAX_RTN_32', + 4: 'TC_OP_RESERVED_FOP_RTN_32_0', + 5: 'TC_OP_RESERVED_FOP_RTN_32_1', + 6: 'TC_OP_RESERVED_FOP_RTN_32_2', + 7: 'TC_OP_ATOMIC_SWAP_RTN_32', + 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', + 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 12: 'TC_OP_PROBE_FILTER', + 13: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', + 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 15: 'TC_OP_ATOMIC_ADD_RTN_32', + 16: 'TC_OP_ATOMIC_SUB_RTN_32', + 17: 'TC_OP_ATOMIC_SMIN_RTN_32', + 18: 'TC_OP_ATOMIC_UMIN_RTN_32', + 19: 'TC_OP_ATOMIC_SMAX_RTN_32', + 20: 'TC_OP_ATOMIC_UMAX_RTN_32', + 21: 'TC_OP_ATOMIC_AND_RTN_32', + 22: 'TC_OP_ATOMIC_OR_RTN_32', + 23: 'TC_OP_ATOMIC_XOR_RTN_32', + 24: 'TC_OP_ATOMIC_INC_RTN_32', + 25: 'TC_OP_ATOMIC_DEC_RTN_32', + 26: 'TC_OP_WBINVL1_VOL', + 27: 'TC_OP_WBINVL1_SD', + 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 32: 'TC_OP_WRITE', + 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 34: 'TC_OP_ATOMIC_FMIN_RTN_64', + 35: 'TC_OP_ATOMIC_FMAX_RTN_64', + 36: 'TC_OP_RESERVED_FOP_RTN_64_0', + 37: 'TC_OP_RESERVED_FOP_RTN_64_1', + 38: 'TC_OP_RESERVED_FOP_RTN_64_2', + 39: 'TC_OP_ATOMIC_SWAP_RTN_64', + 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', + 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 44: 'TC_OP_WBINVL2_SD', + 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 47: 'TC_OP_ATOMIC_ADD_RTN_64', + 48: 'TC_OP_ATOMIC_SUB_RTN_64', + 49: 'TC_OP_ATOMIC_SMIN_RTN_64', + 50: 'TC_OP_ATOMIC_UMIN_RTN_64', + 51: 'TC_OP_ATOMIC_SMAX_RTN_64', + 52: 'TC_OP_ATOMIC_UMAX_RTN_64', + 53: 'TC_OP_ATOMIC_AND_RTN_64', + 54: 'TC_OP_ATOMIC_OR_RTN_64', + 55: 'TC_OP_ATOMIC_XOR_RTN_64', + 56: 'TC_OP_ATOMIC_INC_RTN_64', + 57: 'TC_OP_ATOMIC_DEC_RTN_64', + 58: 'TC_OP_WBL2_NC', + 59: 'TC_OP_WBL2_WC', + 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', + 64: 'TC_OP_WBINVL1', + 65: 'TC_OP_ATOMIC_FCMPSWAP_32', + 66: 'TC_OP_ATOMIC_FMIN_32', + 67: 'TC_OP_ATOMIC_FMAX_32', + 68: 'TC_OP_RESERVED_FOP_32_0', + 69: 'TC_OP_RESERVED_FOP_32_1', + 70: 'TC_OP_RESERVED_FOP_32_2', + 71: 'TC_OP_ATOMIC_SWAP_32', + 72: 'TC_OP_ATOMIC_CMPSWAP_32', + 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 76: 'TC_OP_INV_METADATA', + 77: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1', + 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 79: 'TC_OP_ATOMIC_ADD_32', + 80: 'TC_OP_ATOMIC_SUB_32', + 81: 'TC_OP_ATOMIC_SMIN_32', + 82: 'TC_OP_ATOMIC_UMIN_32', + 83: 'TC_OP_ATOMIC_SMAX_32', + 84: 'TC_OP_ATOMIC_UMAX_32', + 85: 'TC_OP_ATOMIC_AND_32', + 86: 'TC_OP_ATOMIC_OR_32', + 87: 'TC_OP_ATOMIC_XOR_32', + 88: 'TC_OP_ATOMIC_INC_32', + 89: 'TC_OP_ATOMIC_DEC_32', + 90: 'TC_OP_INVL2_NC', + 91: 'TC_OP_NOP_RTN0', + 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', + 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', + 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', + 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', + 96: 'TC_OP_WBINVL2', + 97: 'TC_OP_ATOMIC_FCMPSWAP_64', + 98: 'TC_OP_ATOMIC_FMIN_64', + 99: 'TC_OP_ATOMIC_FMAX_64', + 100: 'TC_OP_RESERVED_FOP_64_0', + 101: 'TC_OP_RESERVED_FOP_64_1', + 102: 'TC_OP_RESERVED_FOP_64_2', + 103: 'TC_OP_ATOMIC_SWAP_64', + 104: 'TC_OP_ATOMIC_CMPSWAP_64', + 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 111: 'TC_OP_ATOMIC_ADD_64', + 112: 'TC_OP_ATOMIC_SUB_64', + 113: 'TC_OP_ATOMIC_SMIN_64', + 114: 'TC_OP_ATOMIC_UMIN_64', + 115: 'TC_OP_ATOMIC_SMAX_64', + 116: 'TC_OP_ATOMIC_UMAX_64', + 117: 'TC_OP_ATOMIC_AND_64', + 118: 'TC_OP_ATOMIC_OR_64', + 119: 'TC_OP_ATOMIC_XOR_64', + 120: 'TC_OP_ATOMIC_INC_64', + 121: 'TC_OP_ATOMIC_DEC_64', + 122: 'TC_OP_WBINVL2_NC', + 123: 'TC_OP_NOP_ACK', + 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', + 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', + 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', + 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', +} +TC_OP_READ = 0 +TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 +TC_OP_ATOMIC_FMIN_RTN_32 = 2 +TC_OP_ATOMIC_FMAX_RTN_32 = 3 +TC_OP_RESERVED_FOP_RTN_32_0 = 4 +TC_OP_RESERVED_FOP_RTN_32_1 = 5 +TC_OP_RESERVED_FOP_RTN_32_2 = 6 +TC_OP_ATOMIC_SWAP_RTN_32 = 7 +TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 +TC_OP_PROBE_FILTER = 12 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 13 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 +TC_OP_ATOMIC_ADD_RTN_32 = 15 +TC_OP_ATOMIC_SUB_RTN_32 = 16 +TC_OP_ATOMIC_SMIN_RTN_32 = 17 +TC_OP_ATOMIC_UMIN_RTN_32 = 18 +TC_OP_ATOMIC_SMAX_RTN_32 = 19 +TC_OP_ATOMIC_UMAX_RTN_32 = 20 +TC_OP_ATOMIC_AND_RTN_32 = 21 +TC_OP_ATOMIC_OR_RTN_32 = 22 +TC_OP_ATOMIC_XOR_RTN_32 = 23 +TC_OP_ATOMIC_INC_RTN_32 = 24 +TC_OP_ATOMIC_DEC_RTN_32 = 25 +TC_OP_WBINVL1_VOL = 26 +TC_OP_WBINVL1_SD = 27 +TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 +TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 +TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 +TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 +TC_OP_WRITE = 32 +TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 +TC_OP_ATOMIC_FMIN_RTN_64 = 34 +TC_OP_ATOMIC_FMAX_RTN_64 = 35 +TC_OP_RESERVED_FOP_RTN_64_0 = 36 +TC_OP_RESERVED_FOP_RTN_64_1 = 37 +TC_OP_RESERVED_FOP_RTN_64_2 = 38 +TC_OP_ATOMIC_SWAP_RTN_64 = 39 +TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 +TC_OP_WBINVL2_SD = 44 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 +TC_OP_ATOMIC_ADD_RTN_64 = 47 +TC_OP_ATOMIC_SUB_RTN_64 = 48 +TC_OP_ATOMIC_SMIN_RTN_64 = 49 +TC_OP_ATOMIC_UMIN_RTN_64 = 50 +TC_OP_ATOMIC_SMAX_RTN_64 = 51 +TC_OP_ATOMIC_UMAX_RTN_64 = 52 +TC_OP_ATOMIC_AND_RTN_64 = 53 +TC_OP_ATOMIC_OR_RTN_64 = 54 +TC_OP_ATOMIC_XOR_RTN_64 = 55 +TC_OP_ATOMIC_INC_RTN_64 = 56 +TC_OP_ATOMIC_DEC_RTN_64 = 57 +TC_OP_WBL2_NC = 58 +TC_OP_WBL2_WC = 59 +TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 +TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 +TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 +TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 +TC_OP_WBINVL1 = 64 +TC_OP_ATOMIC_FCMPSWAP_32 = 65 +TC_OP_ATOMIC_FMIN_32 = 66 +TC_OP_ATOMIC_FMAX_32 = 67 +TC_OP_RESERVED_FOP_32_0 = 68 +TC_OP_RESERVED_FOP_32_1 = 69 +TC_OP_RESERVED_FOP_32_2 = 70 +TC_OP_ATOMIC_SWAP_32 = 71 +TC_OP_ATOMIC_CMPSWAP_32 = 72 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 +TC_OP_INV_METADATA = 76 +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 77 +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 +TC_OP_ATOMIC_ADD_32 = 79 +TC_OP_ATOMIC_SUB_32 = 80 +TC_OP_ATOMIC_SMIN_32 = 81 +TC_OP_ATOMIC_UMIN_32 = 82 +TC_OP_ATOMIC_SMAX_32 = 83 +TC_OP_ATOMIC_UMAX_32 = 84 +TC_OP_ATOMIC_AND_32 = 85 +TC_OP_ATOMIC_OR_32 = 86 +TC_OP_ATOMIC_XOR_32 = 87 +TC_OP_ATOMIC_INC_32 = 88 +TC_OP_ATOMIC_DEC_32 = 89 +TC_OP_INVL2_NC = 90 +TC_OP_NOP_RTN0 = 91 +TC_OP_RESERVED_NON_FLOAT_32_1 = 92 +TC_OP_RESERVED_NON_FLOAT_32_2 = 93 +TC_OP_RESERVED_NON_FLOAT_32_3 = 94 +TC_OP_RESERVED_NON_FLOAT_32_4 = 95 +TC_OP_WBINVL2 = 96 +TC_OP_ATOMIC_FCMPSWAP_64 = 97 +TC_OP_ATOMIC_FMIN_64 = 98 +TC_OP_ATOMIC_FMAX_64 = 99 +TC_OP_RESERVED_FOP_64_0 = 100 +TC_OP_RESERVED_FOP_64_1 = 101 +TC_OP_RESERVED_FOP_64_2 = 102 +TC_OP_ATOMIC_SWAP_64 = 103 +TC_OP_ATOMIC_CMPSWAP_64 = 104 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 +TC_OP_ATOMIC_ADD_64 = 111 +TC_OP_ATOMIC_SUB_64 = 112 +TC_OP_ATOMIC_SMIN_64 = 113 +TC_OP_ATOMIC_UMIN_64 = 114 +TC_OP_ATOMIC_SMAX_64 = 115 +TC_OP_ATOMIC_UMAX_64 = 116 +TC_OP_ATOMIC_AND_64 = 117 +TC_OP_ATOMIC_OR_64 = 118 +TC_OP_ATOMIC_XOR_64 = 119 +TC_OP_ATOMIC_INC_64 = 120 +TC_OP_ATOMIC_DEC_64 = 121 +TC_OP_WBINVL2_NC = 122 +TC_OP_NOP_ACK = 123 +TC_OP_RESERVED_NON_FLOAT_64_1 = 124 +TC_OP_RESERVED_NON_FLOAT_64_2 = 125 +TC_OP_RESERVED_NON_FLOAT_64_3 = 126 +TC_OP_RESERVED_NON_FLOAT_64_4 = 127 +TC_OP = ctypes.c_uint32 # enum + +# values for enumeration 'TC_NACKS' +TC_NACKS__enumvalues = { + 0: 'TC_NACK_NO_FAULT', + 1: 'TC_NACK_PAGE_FAULT', + 2: 'TC_NACK_PROTECTION_FAULT', + 3: 'TC_NACK_DATA_ERROR', +} +TC_NACK_NO_FAULT = 0 +TC_NACK_PAGE_FAULT = 1 +TC_NACK_PROTECTION_FAULT = 2 +TC_NACK_DATA_ERROR = 3 +TC_NACKS = ctypes.c_uint32 # enum + +# values for enumeration 'TC_EA_CID' +TC_EA_CID__enumvalues = { + 0: 'TC_EA_CID_RT', + 1: 'TC_EA_CID_FMASK', + 2: 'TC_EA_CID_DCC', + 3: 'TC_EA_CID_TCPMETA', + 4: 'TC_EA_CID_Z', + 5: 'TC_EA_CID_STENCIL', + 6: 'TC_EA_CID_HTILE', + 7: 'TC_EA_CID_MISC', + 8: 'TC_EA_CID_TCP', + 9: 'TC_EA_CID_SQC', + 10: 'TC_EA_CID_CPF', + 11: 'TC_EA_CID_CPG', + 12: 'TC_EA_CID_IA', + 13: 'TC_EA_CID_WD', + 14: 'TC_EA_CID_PA', + 15: 'TC_EA_CID_UTCL2_TPI', +} +TC_EA_CID_RT = 0 +TC_EA_CID_FMASK = 1 +TC_EA_CID_DCC = 2 +TC_EA_CID_TCPMETA = 3 +TC_EA_CID_Z = 4 +TC_EA_CID_STENCIL = 5 +TC_EA_CID_HTILE = 6 +TC_EA_CID_MISC = 7 +TC_EA_CID_TCP = 8 +TC_EA_CID_SQC = 9 +TC_EA_CID_CPF = 10 +TC_EA_CID_CPG = 11 +TC_EA_CID_IA = 12 +TC_EA_CID_WD = 13 +TC_EA_CID_PA = 14 +TC_EA_CID_UTCL2_TPI = 15 +TC_EA_CID = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_OP_MASKS' +GL2_OP_MASKS__enumvalues = { + 8: 'GL2_OP_MASK_FLUSH_DENROM', + 32: 'GL2_OP_MASK_64', + 64: 'GL2_OP_MASK_NO_RTN', +} +GL2_OP_MASK_FLUSH_DENROM = 8 +GL2_OP_MASK_64 = 32 +GL2_OP_MASK_NO_RTN = 64 +GL2_OP_MASKS = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_OP' +GL2_OP__enumvalues = { + 0: 'GL2_OP_READ', + 1: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', + 2: 'GL2_OP_ATOMIC_FMIN_RTN_32', + 3: 'GL2_OP_ATOMIC_FMAX_RTN_32', + 7: 'GL2_OP_ATOMIC_SWAP_RTN_32', + 8: 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', + 9: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 10: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 11: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 12: 'GL2_OP_PROBE_FILTER', + 13: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', + 14: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 15: 'GL2_OP_ATOMIC_ADD_RTN_32', + 16: 'GL2_OP_ATOMIC_SUB_RTN_32', + 17: 'GL2_OP_ATOMIC_SMIN_RTN_32', + 18: 'GL2_OP_ATOMIC_UMIN_RTN_32', + 19: 'GL2_OP_ATOMIC_SMAX_RTN_32', + 20: 'GL2_OP_ATOMIC_UMAX_RTN_32', + 21: 'GL2_OP_ATOMIC_AND_RTN_32', + 22: 'GL2_OP_ATOMIC_OR_RTN_32', + 23: 'GL2_OP_ATOMIC_XOR_RTN_32', + 24: 'GL2_OP_ATOMIC_INC_RTN_32', + 25: 'GL2_OP_ATOMIC_DEC_RTN_32', + 32: 'GL2_OP_WRITE', + 33: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', + 34: 'GL2_OP_ATOMIC_FMIN_RTN_64', + 35: 'GL2_OP_ATOMIC_FMAX_RTN_64', + 39: 'GL2_OP_ATOMIC_SWAP_RTN_64', + 40: 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', + 41: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 42: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 43: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 47: 'GL2_OP_ATOMIC_ADD_RTN_64', + 48: 'GL2_OP_ATOMIC_SUB_RTN_64', + 49: 'GL2_OP_ATOMIC_SMIN_RTN_64', + 50: 'GL2_OP_ATOMIC_UMIN_RTN_64', + 51: 'GL2_OP_ATOMIC_SMAX_RTN_64', + 52: 'GL2_OP_ATOMIC_UMAX_RTN_64', + 53: 'GL2_OP_ATOMIC_AND_RTN_64', + 54: 'GL2_OP_ATOMIC_OR_RTN_64', + 55: 'GL2_OP_ATOMIC_XOR_RTN_64', + 56: 'GL2_OP_ATOMIC_INC_RTN_64', + 57: 'GL2_OP_ATOMIC_DEC_RTN_64', + 64: 'GL2_OP_GL1_INV', + 65: 'GL2_OP_ATOMIC_FCMPSWAP_32', + 66: 'GL2_OP_ATOMIC_FMIN_32', + 67: 'GL2_OP_ATOMIC_FMAX_32', + 71: 'GL2_OP_ATOMIC_SWAP_32', + 72: 'GL2_OP_ATOMIC_CMPSWAP_32', + 73: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 74: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 75: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 79: 'GL2_OP_ATOMIC_ADD_32', + 80: 'GL2_OP_ATOMIC_SUB_32', + 81: 'GL2_OP_ATOMIC_SMIN_32', + 82: 'GL2_OP_ATOMIC_UMIN_32', + 83: 'GL2_OP_ATOMIC_SMAX_32', + 84: 'GL2_OP_ATOMIC_UMAX_32', + 85: 'GL2_OP_ATOMIC_AND_32', + 86: 'GL2_OP_ATOMIC_OR_32', + 87: 'GL2_OP_ATOMIC_XOR_32', + 88: 'GL2_OP_ATOMIC_INC_32', + 89: 'GL2_OP_ATOMIC_DEC_32', + 91: 'GL2_OP_NOP_RTN0', + 97: 'GL2_OP_ATOMIC_FCMPSWAP_64', + 98: 'GL2_OP_ATOMIC_FMIN_64', + 99: 'GL2_OP_ATOMIC_FMAX_64', + 103: 'GL2_OP_ATOMIC_SWAP_64', + 104: 'GL2_OP_ATOMIC_CMPSWAP_64', + 105: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 106: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 107: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 111: 'GL2_OP_ATOMIC_ADD_64', + 112: 'GL2_OP_ATOMIC_SUB_64', + 113: 'GL2_OP_ATOMIC_SMIN_64', + 114: 'GL2_OP_ATOMIC_UMIN_64', + 115: 'GL2_OP_ATOMIC_SMAX_64', + 116: 'GL2_OP_ATOMIC_UMAX_64', + 117: 'GL2_OP_ATOMIC_AND_64', + 118: 'GL2_OP_ATOMIC_OR_64', + 119: 'GL2_OP_ATOMIC_XOR_64', + 120: 'GL2_OP_ATOMIC_INC_64', + 121: 'GL2_OP_ATOMIC_DEC_64', + 123: 'GL2_OP_NOP_ACK', +} +GL2_OP_READ = 0 +GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 +GL2_OP_ATOMIC_FMIN_RTN_32 = 2 +GL2_OP_ATOMIC_FMAX_RTN_32 = 3 +GL2_OP_ATOMIC_SWAP_RTN_32 = 7 +GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 +GL2_OP_PROBE_FILTER = 12 +GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 13 +GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 +GL2_OP_ATOMIC_ADD_RTN_32 = 15 +GL2_OP_ATOMIC_SUB_RTN_32 = 16 +GL2_OP_ATOMIC_SMIN_RTN_32 = 17 +GL2_OP_ATOMIC_UMIN_RTN_32 = 18 +GL2_OP_ATOMIC_SMAX_RTN_32 = 19 +GL2_OP_ATOMIC_UMAX_RTN_32 = 20 +GL2_OP_ATOMIC_AND_RTN_32 = 21 +GL2_OP_ATOMIC_OR_RTN_32 = 22 +GL2_OP_ATOMIC_XOR_RTN_32 = 23 +GL2_OP_ATOMIC_INC_RTN_32 = 24 +GL2_OP_ATOMIC_DEC_RTN_32 = 25 +GL2_OP_WRITE = 32 +GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 +GL2_OP_ATOMIC_FMIN_RTN_64 = 34 +GL2_OP_ATOMIC_FMAX_RTN_64 = 35 +GL2_OP_ATOMIC_SWAP_RTN_64 = 39 +GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 40 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 +GL2_OP_ATOMIC_ADD_RTN_64 = 47 +GL2_OP_ATOMIC_SUB_RTN_64 = 48 +GL2_OP_ATOMIC_SMIN_RTN_64 = 49 +GL2_OP_ATOMIC_UMIN_RTN_64 = 50 +GL2_OP_ATOMIC_SMAX_RTN_64 = 51 +GL2_OP_ATOMIC_UMAX_RTN_64 = 52 +GL2_OP_ATOMIC_AND_RTN_64 = 53 +GL2_OP_ATOMIC_OR_RTN_64 = 54 +GL2_OP_ATOMIC_XOR_RTN_64 = 55 +GL2_OP_ATOMIC_INC_RTN_64 = 56 +GL2_OP_ATOMIC_DEC_RTN_64 = 57 +GL2_OP_GL1_INV = 64 +GL2_OP_ATOMIC_FCMPSWAP_32 = 65 +GL2_OP_ATOMIC_FMIN_32 = 66 +GL2_OP_ATOMIC_FMAX_32 = 67 +GL2_OP_ATOMIC_SWAP_32 = 71 +GL2_OP_ATOMIC_CMPSWAP_32 = 72 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 +GL2_OP_ATOMIC_ADD_32 = 79 +GL2_OP_ATOMIC_SUB_32 = 80 +GL2_OP_ATOMIC_SMIN_32 = 81 +GL2_OP_ATOMIC_UMIN_32 = 82 +GL2_OP_ATOMIC_SMAX_32 = 83 +GL2_OP_ATOMIC_UMAX_32 = 84 +GL2_OP_ATOMIC_AND_32 = 85 +GL2_OP_ATOMIC_OR_32 = 86 +GL2_OP_ATOMIC_XOR_32 = 87 +GL2_OP_ATOMIC_INC_32 = 88 +GL2_OP_ATOMIC_DEC_32 = 89 +GL2_OP_NOP_RTN0 = 91 +GL2_OP_ATOMIC_FCMPSWAP_64 = 97 +GL2_OP_ATOMIC_FMIN_64 = 98 +GL2_OP_ATOMIC_FMAX_64 = 99 +GL2_OP_ATOMIC_SWAP_64 = 103 +GL2_OP_ATOMIC_CMPSWAP_64 = 104 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 +GL2_OP_ATOMIC_ADD_64 = 111 +GL2_OP_ATOMIC_SUB_64 = 112 +GL2_OP_ATOMIC_SMIN_64 = 113 +GL2_OP_ATOMIC_UMIN_64 = 114 +GL2_OP_ATOMIC_SMAX_64 = 115 +GL2_OP_ATOMIC_UMAX_64 = 116 +GL2_OP_ATOMIC_AND_64 = 117 +GL2_OP_ATOMIC_OR_64 = 118 +GL2_OP_ATOMIC_XOR_64 = 119 +GL2_OP_ATOMIC_INC_64 = 120 +GL2_OP_ATOMIC_DEC_64 = 121 +GL2_OP_NOP_ACK = 123 +GL2_OP = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_NACKS' +GL2_NACKS__enumvalues = { + 0: 'GL2_NACK_NO_FAULT', + 1: 'GL2_NACK_PAGE_FAULT', + 2: 'GL2_NACK_PROTECTION_FAULT', + 3: 'GL2_NACK_DATA_ERROR', +} +GL2_NACK_NO_FAULT = 0 +GL2_NACK_PAGE_FAULT = 1 +GL2_NACK_PROTECTION_FAULT = 2 +GL2_NACK_DATA_ERROR = 3 +GL2_NACKS = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_EA_CID' +GL2_EA_CID__enumvalues = { + 0: 'GL2_EA_CID_CLIENT', + 1: 'GL2_EA_CID_SDMA', + 2: 'GL2_EA_CID_RLC', + 4: 'GL2_EA_CID_CP', + 5: 'GL2_EA_CID_CPDMA', + 6: 'GL2_EA_CID_UTCL2', + 7: 'GL2_EA_CID_RT', + 8: 'GL2_EA_CID_FMASK', + 9: 'GL2_EA_CID_DCC', + 10: 'GL2_EA_CID_Z_STENCIL', + 11: 'GL2_EA_CID_ZPCPSD', + 12: 'GL2_EA_CID_HTILE', + 15: 'GL2_EA_CID_TCPMETA', +} +GL2_EA_CID_CLIENT = 0 +GL2_EA_CID_SDMA = 1 +GL2_EA_CID_RLC = 2 +GL2_EA_CID_CP = 4 +GL2_EA_CID_CPDMA = 5 +GL2_EA_CID_UTCL2 = 6 +GL2_EA_CID_RT = 7 +GL2_EA_CID_FMASK = 8 +GL2_EA_CID_DCC = 9 +GL2_EA_CID_Z_STENCIL = 10 +GL2_EA_CID_ZPCPSD = 11 +GL2_EA_CID_HTILE = 12 +GL2_EA_CID_TCPMETA = 15 +GL2_EA_CID = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SAMPLE_CNTL' +SPI_SAMPLE_CNTL__enumvalues = { + 0: 'CENTROIDS_ONLY', + 1: 'CENTERS_ONLY', + 2: 'CENTROIDS_AND_CENTERS', + 3: 'UNDEF', +} +CENTROIDS_ONLY = 0 +CENTERS_ONLY = 1 +CENTROIDS_AND_CENTERS = 2 +UNDEF = 3 +SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_FOG_MODE' +SPI_FOG_MODE__enumvalues = { + 0: 'SPI_FOG_NONE', + 1: 'SPI_FOG_EXP', + 2: 'SPI_FOG_EXP2', + 3: 'SPI_FOG_LINEAR', +} +SPI_FOG_NONE = 0 +SPI_FOG_EXP = 1 +SPI_FOG_EXP2 = 2 +SPI_FOG_LINEAR = 3 +SPI_FOG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' +SPI_PNT_SPRITE_OVERRIDE__enumvalues = { + 0: 'SPI_PNT_SPRITE_SEL_0', + 1: 'SPI_PNT_SPRITE_SEL_1', + 2: 'SPI_PNT_SPRITE_SEL_S', + 3: 'SPI_PNT_SPRITE_SEL_T', + 4: 'SPI_PNT_SPRITE_SEL_NONE', +} +SPI_PNT_SPRITE_SEL_0 = 0 +SPI_PNT_SPRITE_SEL_1 = 1 +SPI_PNT_SPRITE_SEL_S = 2 +SPI_PNT_SPRITE_SEL_T = 3 +SPI_PNT_SPRITE_SEL_NONE = 4 +SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PERFCNT_SEL' +SPI_PERFCNT_SEL__enumvalues = { + 0: 'SPI_PERF_VS_WINDOW_VALID', + 1: 'SPI_PERF_VS_BUSY', + 2: 'SPI_PERF_VS_FIRST_WAVE', + 3: 'SPI_PERF_VS_LAST_WAVE', + 4: 'SPI_PERF_VS_LSHS_DEALLOC', + 5: 'SPI_PERF_VS_PC_STALL', + 6: 'SPI_PERF_VS_POS0_STALL', + 7: 'SPI_PERF_VS_POS1_STALL', + 8: 'SPI_PERF_VS_CRAWLER_STALL', + 9: 'SPI_PERF_VS_EVENT_WAVE', + 10: 'SPI_PERF_VS_WAVE', + 11: 'SPI_PERF_VS_PERS_UPD_FULL0', + 12: 'SPI_PERF_VS_PERS_UPD_FULL1', + 13: 'SPI_PERF_VS_LATE_ALLOC_FULL', + 14: 'SPI_PERF_VS_FIRST_SUBGRP', + 15: 'SPI_PERF_VS_LAST_SUBGRP', + 16: 'SPI_PERF_VS_ALLOC_CNT', + 17: 'SPI_PERF_VS_PC_ALLOC_CNT', + 18: 'SPI_PERF_VS_LATE_ALLOC_ACCUM', + 19: 'SPI_PERF_GS_WINDOW_VALID', + 20: 'SPI_PERF_GS_BUSY', + 21: 'SPI_PERF_GS_CRAWLER_STALL', + 22: 'SPI_PERF_GS_EVENT_WAVE', + 23: 'SPI_PERF_GS_WAVE', + 24: 'SPI_PERF_GS_PERS_UPD_FULL0', + 25: 'SPI_PERF_GS_PERS_UPD_FULL1', + 26: 'SPI_PERF_GS_FIRST_SUBGRP', + 27: 'SPI_PERF_GS_LAST_SUBGRP', + 28: 'SPI_PERF_GS_HS_DEALLOC', + 29: 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', + 30: 'SPI_PERF_GS_GRP_FIFO_FULL', + 31: 'SPI_PERF_HS_WINDOW_VALID', + 32: 'SPI_PERF_HS_BUSY', + 33: 'SPI_PERF_HS_CRAWLER_STALL', + 34: 'SPI_PERF_HS_FIRST_WAVE', + 35: 'SPI_PERF_HS_LAST_WAVE', + 36: 'SPI_PERF_HS_OFFCHIP_LDS_STALL', + 37: 'SPI_PERF_HS_EVENT_WAVE', + 38: 'SPI_PERF_HS_WAVE', + 39: 'SPI_PERF_HS_PERS_UPD_FULL0', + 40: 'SPI_PERF_HS_PERS_UPD_FULL1', + 41: 'SPI_PERF_CSG_WINDOW_VALID', + 42: 'SPI_PERF_CSG_BUSY', + 43: 'SPI_PERF_CSG_NUM_THREADGROUPS', + 44: 'SPI_PERF_CSG_CRAWLER_STALL', + 45: 'SPI_PERF_CSG_EVENT_WAVE', + 46: 'SPI_PERF_CSG_WAVE', + 47: 'SPI_PERF_CSN_WINDOW_VALID', + 48: 'SPI_PERF_CSN_BUSY', + 49: 'SPI_PERF_CSN_NUM_THREADGROUPS', + 50: 'SPI_PERF_CSN_CRAWLER_STALL', + 51: 'SPI_PERF_CSN_EVENT_WAVE', + 52: 'SPI_PERF_CSN_WAVE', + 53: 'SPI_PERF_PS0_WINDOW_VALID', + 54: 'SPI_PERF_PS1_WINDOW_VALID', + 55: 'SPI_PERF_PS2_WINDOW_VALID', + 56: 'SPI_PERF_PS3_WINDOW_VALID', + 57: 'SPI_PERF_PS0_BUSY', + 58: 'SPI_PERF_PS1_BUSY', + 59: 'SPI_PERF_PS2_BUSY', + 60: 'SPI_PERF_PS3_BUSY', + 61: 'SPI_PERF_PS0_ACTIVE', + 62: 'SPI_PERF_PS1_ACTIVE', + 63: 'SPI_PERF_PS2_ACTIVE', + 64: 'SPI_PERF_PS3_ACTIVE', + 65: 'SPI_PERF_PS0_DEALLOC_BIN0', + 66: 'SPI_PERF_PS1_DEALLOC_BIN0', + 67: 'SPI_PERF_PS2_DEALLOC_BIN0', + 68: 'SPI_PERF_PS3_DEALLOC_BIN0', + 69: 'SPI_PERF_PS0_FPOS_BIN1_STALL', + 70: 'SPI_PERF_PS1_FPOS_BIN1_STALL', + 71: 'SPI_PERF_PS2_FPOS_BIN1_STALL', + 72: 'SPI_PERF_PS3_FPOS_BIN1_STALL', + 73: 'SPI_PERF_PS0_EVENT_WAVE', + 74: 'SPI_PERF_PS1_EVENT_WAVE', + 75: 'SPI_PERF_PS2_EVENT_WAVE', + 76: 'SPI_PERF_PS3_EVENT_WAVE', + 77: 'SPI_PERF_PS0_WAVE', + 78: 'SPI_PERF_PS1_WAVE', + 79: 'SPI_PERF_PS2_WAVE', + 80: 'SPI_PERF_PS3_WAVE', + 81: 'SPI_PERF_PS0_OPT_WAVE', + 82: 'SPI_PERF_PS1_OPT_WAVE', + 83: 'SPI_PERF_PS2_OPT_WAVE', + 84: 'SPI_PERF_PS3_OPT_WAVE', + 85: 'SPI_PERF_PS0_PASS_BIN0', + 86: 'SPI_PERF_PS1_PASS_BIN0', + 87: 'SPI_PERF_PS2_PASS_BIN0', + 88: 'SPI_PERF_PS3_PASS_BIN0', + 89: 'SPI_PERF_PS0_PASS_BIN1', + 90: 'SPI_PERF_PS1_PASS_BIN1', + 91: 'SPI_PERF_PS2_PASS_BIN1', + 92: 'SPI_PERF_PS3_PASS_BIN1', + 93: 'SPI_PERF_PS0_FPOS_BIN2', + 94: 'SPI_PERF_PS1_FPOS_BIN2', + 95: 'SPI_PERF_PS2_FPOS_BIN2', + 96: 'SPI_PERF_PS3_FPOS_BIN2', + 97: 'SPI_PERF_PS0_PRIM_BIN0', + 98: 'SPI_PERF_PS1_PRIM_BIN0', + 99: 'SPI_PERF_PS2_PRIM_BIN0', + 100: 'SPI_PERF_PS3_PRIM_BIN0', + 101: 'SPI_PERF_PS0_PRIM_BIN1', + 102: 'SPI_PERF_PS1_PRIM_BIN1', + 103: 'SPI_PERF_PS2_PRIM_BIN1', + 104: 'SPI_PERF_PS3_PRIM_BIN1', + 105: 'SPI_PERF_PS0_CNF_BIN2', + 106: 'SPI_PERF_PS1_CNF_BIN2', + 107: 'SPI_PERF_PS2_CNF_BIN2', + 108: 'SPI_PERF_PS3_CNF_BIN2', + 109: 'SPI_PERF_PS0_CNF_BIN3', + 110: 'SPI_PERF_PS1_CNF_BIN3', + 111: 'SPI_PERF_PS2_CNF_BIN3', + 112: 'SPI_PERF_PS3_CNF_BIN3', + 113: 'SPI_PERF_PS0_CRAWLER_STALL', + 114: 'SPI_PERF_PS1_CRAWLER_STALL', + 115: 'SPI_PERF_PS2_CRAWLER_STALL', + 116: 'SPI_PERF_PS3_CRAWLER_STALL', + 117: 'SPI_PERF_PS0_LDS_RES_FULL', + 118: 'SPI_PERF_PS1_LDS_RES_FULL', + 119: 'SPI_PERF_PS2_LDS_RES_FULL', + 120: 'SPI_PERF_PS3_LDS_RES_FULL', + 121: 'SPI_PERF_PS_PERS_UPD_FULL0', + 122: 'SPI_PERF_PS_PERS_UPD_FULL1', + 123: 'SPI_PERF_PS0_POPS_WAVE_SENT', + 124: 'SPI_PERF_PS1_POPS_WAVE_SENT', + 125: 'SPI_PERF_PS2_POPS_WAVE_SENT', + 126: 'SPI_PERF_PS3_POPS_WAVE_SENT', + 127: 'SPI_PERF_PS0_POPS_WAVE_EXIT', + 128: 'SPI_PERF_PS1_POPS_WAVE_EXIT', + 129: 'SPI_PERF_PS2_POPS_WAVE_EXIT', + 130: 'SPI_PERF_PS3_POPS_WAVE_EXIT', + 131: 'SPI_PERF_LDS0_PC_VALID', + 132: 'SPI_PERF_LDS1_PC_VALID', + 133: 'SPI_PERF_RA_PIPE_REQ_BIN2', + 134: 'SPI_PERF_RA_TASK_REQ_BIN3', + 135: 'SPI_PERF_RA_WR_CTL_FULL', + 136: 'SPI_PERF_RA_REQ_NO_ALLOC', + 137: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', + 138: 'SPI_PERF_RA_REQ_NO_ALLOC_VS', + 139: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', + 140: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', + 141: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', + 142: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', + 143: 'SPI_PERF_RA_RES_STALL_PS', + 144: 'SPI_PERF_RA_RES_STALL_VS', + 145: 'SPI_PERF_RA_RES_STALL_GS', + 146: 'SPI_PERF_RA_RES_STALL_HS', + 147: 'SPI_PERF_RA_RES_STALL_CSG', + 148: 'SPI_PERF_RA_RES_STALL_CSN', + 149: 'SPI_PERF_RA_TMP_STALL_PS', + 150: 'SPI_PERF_RA_TMP_STALL_VS', + 151: 'SPI_PERF_RA_TMP_STALL_GS', + 152: 'SPI_PERF_RA_TMP_STALL_HS', + 153: 'SPI_PERF_RA_TMP_STALL_CSG', + 154: 'SPI_PERF_RA_TMP_STALL_CSN', + 155: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 156: 'SPI_PERF_RA_WAVE_SIMD_FULL_VS', + 157: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', + 158: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', + 159: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 160: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', + 161: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 162: 'SPI_PERF_RA_VGPR_SIMD_FULL_VS', + 163: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', + 164: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', + 165: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 166: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', + 167: 'SPI_PERF_RA_SGPR_SIMD_FULL_PS', + 168: 'SPI_PERF_RA_SGPR_SIMD_FULL_VS', + 169: 'SPI_PERF_RA_SGPR_SIMD_FULL_GS', + 170: 'SPI_PERF_RA_SGPR_SIMD_FULL_HS', + 171: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG', + 172: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', + 173: 'SPI_PERF_RA_LDS_CU_FULL_PS', + 174: 'SPI_PERF_RA_LDS_CU_FULL_LS', + 175: 'SPI_PERF_RA_LDS_CU_FULL_ES', + 176: 'SPI_PERF_RA_LDS_CU_FULL_CSG', + 177: 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 178: 'SPI_PERF_RA_BAR_CU_FULL_HS', + 179: 'SPI_PERF_RA_BAR_CU_FULL_CSG', + 180: 'SPI_PERF_RA_BAR_CU_FULL_CSN', + 181: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', + 182: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', + 183: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', + 184: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 185: 'SPI_PERF_RA_WVLIM_STALL_PS', + 186: 'SPI_PERF_RA_WVLIM_STALL_VS', + 187: 'SPI_PERF_RA_WVLIM_STALL_GS', + 188: 'SPI_PERF_RA_WVLIM_STALL_HS', + 189: 'SPI_PERF_RA_WVLIM_STALL_CSG', + 190: 'SPI_PERF_RA_WVLIM_STALL_CSN', + 191: 'SPI_PERF_RA_VS_LOCK', + 192: 'SPI_PERF_RA_GS_LOCK', + 193: 'SPI_PERF_RA_HS_LOCK', + 194: 'SPI_PERF_RA_CSG_LOCK', + 195: 'SPI_PERF_RA_CSN_LOCK', + 196: 'SPI_PERF_RA_RSV_UPD', + 197: 'SPI_PERF_EXP_ARB_COL_CNT', + 198: 'SPI_PERF_EXP_ARB_PAR_CNT', + 199: 'SPI_PERF_EXP_ARB_POS_CNT', + 200: 'SPI_PERF_EXP_ARB_GDS_CNT', + 201: 'SPI_PERF_NUM_PS_COL_R0_EXPORTS', + 202: 'SPI_PERF_NUM_PS_COL_R1_EXPORTS', + 203: 'SPI_PERF_NUM_VS_POS_R0_EXPORTS', + 204: 'SPI_PERF_NUM_VS_POS_R1_EXPORTS', + 205: 'SPI_PERF_NUM_VS_PARAM_R0_EXPORTS', + 206: 'SPI_PERF_NUM_VS_PARAM_R1_EXPORTS', + 207: 'SPI_PERF_NUM_VS_GDS_R0_EXPORTS', + 208: 'SPI_PERF_NUM_VS_GDS_R1_EXPORTS', + 209: 'SPI_PERF_NUM_EXPGRANT_EXPORTS', + 210: 'SPI_PERF_CLKGATE_BUSY_STALL', + 211: 'SPI_PERF_CLKGATE_ACTIVE_STALL', + 212: 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON', + 213: 'SPI_PERF_CLKGATE_CGTT_DYN_ON', + 214: 'SPI_PERF_CLKGATE_CGTT_REG_ON', + 215: 'SPI_PERF_PIX_ALLOC_PEND_CNT', + 216: 'SPI_PERF_PIX_ALLOC_SCB0_STALL', + 217: 'SPI_PERF_PIX_ALLOC_SCB1_STALL', + 218: 'SPI_PERF_PIX_ALLOC_SCB2_STALL', + 219: 'SPI_PERF_PIX_ALLOC_SCB3_STALL', + 220: 'SPI_PERF_PIX_ALLOC_DB0_STALL', + 221: 'SPI_PERF_PIX_ALLOC_DB1_STALL', + 222: 'SPI_PERF_PIX_ALLOC_DB2_STALL', + 223: 'SPI_PERF_PIX_ALLOC_DB3_STALL', + 224: 'SPI_PERF_PIX_ALLOC_DB4_STALL', + 225: 'SPI_PERF_PIX_ALLOC_DB5_STALL', + 226: 'SPI_PERF_PIX_ALLOC_DB6_STALL', + 227: 'SPI_PERF_PIX_ALLOC_DB7_STALL', + 228: 'SPI_PERF_PC_ALLOC_ACCUM', + 229: 'SPI_PERF_GS_NGG_SE_HAS_BATON', + 230: 'SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON', + 231: 'SPI_PERF_GS_NGG_SE_FORWARDED_BATON', + 232: 'SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT', + 233: 'SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT', + 234: 'SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT', + 235: 'SPI_PERF_GS_NGG_PC_FULL', + 236: 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', + 237: 'SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY', + 238: 'SPI_PERF_GSC_VTX_BUSY', + 239: 'SPI_PERF_GSC_VTX_INPUT_STARVED', + 240: 'SPI_PERF_GSC_VTX_VSR_STALL', + 241: 'SPI_PERF_GSC_VTX_VSR_FULL', + 242: 'SPI_PERF_GSC_VTX_CAC_BUSY', + 243: 'SPI_PERF_ESC_VTX_BUSY', + 244: 'SPI_PERF_ESC_VTX_INPUT_STARVED', + 245: 'SPI_PERF_ESC_VTX_VSR_STALL', + 246: 'SPI_PERF_ESC_VTX_VSR_FULL', + 247: 'SPI_PERF_ESC_VTX_CAC_BUSY', + 248: 'SPI_PERF_SWC_PS_WR', + 249: 'SPI_PERF_SWC_VS_WR', + 250: 'SPI_PERF_SWC_GS_WR', + 251: 'SPI_PERF_SWC_HS_WR', + 252: 'SPI_PERF_SWC_CSG_WR', + 253: 'SPI_PERF_SWC_CSC_WR', + 254: 'SPI_PERF_VWC_PS_WR', + 255: 'SPI_PERF_VWC_VS_WR', + 256: 'SPI_PERF_VWC_GS_WR', + 257: 'SPI_PERF_VWC_HS_WR', + 258: 'SPI_PERF_VWC_CSG_WR', + 259: 'SPI_PERF_VWC_CSC_WR', + 260: 'SPI_PERF_ES_WINDOW_VALID', + 261: 'SPI_PERF_ES_BUSY', + 262: 'SPI_PERF_ES_CRAWLER_STALL', + 263: 'SPI_PERF_ES_FIRST_WAVE', + 264: 'SPI_PERF_ES_LAST_WAVE', + 265: 'SPI_PERF_ES_LSHS_DEALLOC', + 266: 'SPI_PERF_ES_EVENT_WAVE', + 267: 'SPI_PERF_ES_WAVE', + 268: 'SPI_PERF_ES_PERS_UPD_FULL0', + 269: 'SPI_PERF_ES_PERS_UPD_FULL1', + 270: 'SPI_PERF_ES_FIRST_SUBGRP', + 271: 'SPI_PERF_ES_LAST_SUBGRP', + 272: 'SPI_PERF_LS_WINDOW_VALID', + 273: 'SPI_PERF_LS_BUSY', + 274: 'SPI_PERF_LS_CRAWLER_STALL', + 275: 'SPI_PERF_LS_FIRST_WAVE', + 276: 'SPI_PERF_LS_LAST_WAVE', + 277: 'SPI_PERF_LS_OFFCHIP_LDS_STALL', + 278: 'SPI_PERF_LS_EVENT_WAVE', + 279: 'SPI_PERF_LS_WAVE', + 280: 'SPI_PERF_LS_PERS_UPD_FULL0', + 281: 'SPI_PERF_LS_PERS_UPD_FULL1', +} +SPI_PERF_VS_WINDOW_VALID = 0 +SPI_PERF_VS_BUSY = 1 +SPI_PERF_VS_FIRST_WAVE = 2 +SPI_PERF_VS_LAST_WAVE = 3 +SPI_PERF_VS_LSHS_DEALLOC = 4 +SPI_PERF_VS_PC_STALL = 5 +SPI_PERF_VS_POS0_STALL = 6 +SPI_PERF_VS_POS1_STALL = 7 +SPI_PERF_VS_CRAWLER_STALL = 8 +SPI_PERF_VS_EVENT_WAVE = 9 +SPI_PERF_VS_WAVE = 10 +SPI_PERF_VS_PERS_UPD_FULL0 = 11 +SPI_PERF_VS_PERS_UPD_FULL1 = 12 +SPI_PERF_VS_LATE_ALLOC_FULL = 13 +SPI_PERF_VS_FIRST_SUBGRP = 14 +SPI_PERF_VS_LAST_SUBGRP = 15 +SPI_PERF_VS_ALLOC_CNT = 16 +SPI_PERF_VS_PC_ALLOC_CNT = 17 +SPI_PERF_VS_LATE_ALLOC_ACCUM = 18 +SPI_PERF_GS_WINDOW_VALID = 19 +SPI_PERF_GS_BUSY = 20 +SPI_PERF_GS_CRAWLER_STALL = 21 +SPI_PERF_GS_EVENT_WAVE = 22 +SPI_PERF_GS_WAVE = 23 +SPI_PERF_GS_PERS_UPD_FULL0 = 24 +SPI_PERF_GS_PERS_UPD_FULL1 = 25 +SPI_PERF_GS_FIRST_SUBGRP = 26 +SPI_PERF_GS_LAST_SUBGRP = 27 +SPI_PERF_GS_HS_DEALLOC = 28 +SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 29 +SPI_PERF_GS_GRP_FIFO_FULL = 30 +SPI_PERF_HS_WINDOW_VALID = 31 +SPI_PERF_HS_BUSY = 32 +SPI_PERF_HS_CRAWLER_STALL = 33 +SPI_PERF_HS_FIRST_WAVE = 34 +SPI_PERF_HS_LAST_WAVE = 35 +SPI_PERF_HS_OFFCHIP_LDS_STALL = 36 +SPI_PERF_HS_EVENT_WAVE = 37 +SPI_PERF_HS_WAVE = 38 +SPI_PERF_HS_PERS_UPD_FULL0 = 39 +SPI_PERF_HS_PERS_UPD_FULL1 = 40 +SPI_PERF_CSG_WINDOW_VALID = 41 +SPI_PERF_CSG_BUSY = 42 +SPI_PERF_CSG_NUM_THREADGROUPS = 43 +SPI_PERF_CSG_CRAWLER_STALL = 44 +SPI_PERF_CSG_EVENT_WAVE = 45 +SPI_PERF_CSG_WAVE = 46 +SPI_PERF_CSN_WINDOW_VALID = 47 +SPI_PERF_CSN_BUSY = 48 +SPI_PERF_CSN_NUM_THREADGROUPS = 49 +SPI_PERF_CSN_CRAWLER_STALL = 50 +SPI_PERF_CSN_EVENT_WAVE = 51 +SPI_PERF_CSN_WAVE = 52 +SPI_PERF_PS0_WINDOW_VALID = 53 +SPI_PERF_PS1_WINDOW_VALID = 54 +SPI_PERF_PS2_WINDOW_VALID = 55 +SPI_PERF_PS3_WINDOW_VALID = 56 +SPI_PERF_PS0_BUSY = 57 +SPI_PERF_PS1_BUSY = 58 +SPI_PERF_PS2_BUSY = 59 +SPI_PERF_PS3_BUSY = 60 +SPI_PERF_PS0_ACTIVE = 61 +SPI_PERF_PS1_ACTIVE = 62 +SPI_PERF_PS2_ACTIVE = 63 +SPI_PERF_PS3_ACTIVE = 64 +SPI_PERF_PS0_DEALLOC_BIN0 = 65 +SPI_PERF_PS1_DEALLOC_BIN0 = 66 +SPI_PERF_PS2_DEALLOC_BIN0 = 67 +SPI_PERF_PS3_DEALLOC_BIN0 = 68 +SPI_PERF_PS0_FPOS_BIN1_STALL = 69 +SPI_PERF_PS1_FPOS_BIN1_STALL = 70 +SPI_PERF_PS2_FPOS_BIN1_STALL = 71 +SPI_PERF_PS3_FPOS_BIN1_STALL = 72 +SPI_PERF_PS0_EVENT_WAVE = 73 +SPI_PERF_PS1_EVENT_WAVE = 74 +SPI_PERF_PS2_EVENT_WAVE = 75 +SPI_PERF_PS3_EVENT_WAVE = 76 +SPI_PERF_PS0_WAVE = 77 +SPI_PERF_PS1_WAVE = 78 +SPI_PERF_PS2_WAVE = 79 +SPI_PERF_PS3_WAVE = 80 +SPI_PERF_PS0_OPT_WAVE = 81 +SPI_PERF_PS1_OPT_WAVE = 82 +SPI_PERF_PS2_OPT_WAVE = 83 +SPI_PERF_PS3_OPT_WAVE = 84 +SPI_PERF_PS0_PASS_BIN0 = 85 +SPI_PERF_PS1_PASS_BIN0 = 86 +SPI_PERF_PS2_PASS_BIN0 = 87 +SPI_PERF_PS3_PASS_BIN0 = 88 +SPI_PERF_PS0_PASS_BIN1 = 89 +SPI_PERF_PS1_PASS_BIN1 = 90 +SPI_PERF_PS2_PASS_BIN1 = 91 +SPI_PERF_PS3_PASS_BIN1 = 92 +SPI_PERF_PS0_FPOS_BIN2 = 93 +SPI_PERF_PS1_FPOS_BIN2 = 94 +SPI_PERF_PS2_FPOS_BIN2 = 95 +SPI_PERF_PS3_FPOS_BIN2 = 96 +SPI_PERF_PS0_PRIM_BIN0 = 97 +SPI_PERF_PS1_PRIM_BIN0 = 98 +SPI_PERF_PS2_PRIM_BIN0 = 99 +SPI_PERF_PS3_PRIM_BIN0 = 100 +SPI_PERF_PS0_PRIM_BIN1 = 101 +SPI_PERF_PS1_PRIM_BIN1 = 102 +SPI_PERF_PS2_PRIM_BIN1 = 103 +SPI_PERF_PS3_PRIM_BIN1 = 104 +SPI_PERF_PS0_CNF_BIN2 = 105 +SPI_PERF_PS1_CNF_BIN2 = 106 +SPI_PERF_PS2_CNF_BIN2 = 107 +SPI_PERF_PS3_CNF_BIN2 = 108 +SPI_PERF_PS0_CNF_BIN3 = 109 +SPI_PERF_PS1_CNF_BIN3 = 110 +SPI_PERF_PS2_CNF_BIN3 = 111 +SPI_PERF_PS3_CNF_BIN3 = 112 +SPI_PERF_PS0_CRAWLER_STALL = 113 +SPI_PERF_PS1_CRAWLER_STALL = 114 +SPI_PERF_PS2_CRAWLER_STALL = 115 +SPI_PERF_PS3_CRAWLER_STALL = 116 +SPI_PERF_PS0_LDS_RES_FULL = 117 +SPI_PERF_PS1_LDS_RES_FULL = 118 +SPI_PERF_PS2_LDS_RES_FULL = 119 +SPI_PERF_PS3_LDS_RES_FULL = 120 +SPI_PERF_PS_PERS_UPD_FULL0 = 121 +SPI_PERF_PS_PERS_UPD_FULL1 = 122 +SPI_PERF_PS0_POPS_WAVE_SENT = 123 +SPI_PERF_PS1_POPS_WAVE_SENT = 124 +SPI_PERF_PS2_POPS_WAVE_SENT = 125 +SPI_PERF_PS3_POPS_WAVE_SENT = 126 +SPI_PERF_PS0_POPS_WAVE_EXIT = 127 +SPI_PERF_PS1_POPS_WAVE_EXIT = 128 +SPI_PERF_PS2_POPS_WAVE_EXIT = 129 +SPI_PERF_PS3_POPS_WAVE_EXIT = 130 +SPI_PERF_LDS0_PC_VALID = 131 +SPI_PERF_LDS1_PC_VALID = 132 +SPI_PERF_RA_PIPE_REQ_BIN2 = 133 +SPI_PERF_RA_TASK_REQ_BIN3 = 134 +SPI_PERF_RA_WR_CTL_FULL = 135 +SPI_PERF_RA_REQ_NO_ALLOC = 136 +SPI_PERF_RA_REQ_NO_ALLOC_PS = 137 +SPI_PERF_RA_REQ_NO_ALLOC_VS = 138 +SPI_PERF_RA_REQ_NO_ALLOC_GS = 139 +SPI_PERF_RA_REQ_NO_ALLOC_HS = 140 +SPI_PERF_RA_REQ_NO_ALLOC_CSG = 141 +SPI_PERF_RA_REQ_NO_ALLOC_CSN = 142 +SPI_PERF_RA_RES_STALL_PS = 143 +SPI_PERF_RA_RES_STALL_VS = 144 +SPI_PERF_RA_RES_STALL_GS = 145 +SPI_PERF_RA_RES_STALL_HS = 146 +SPI_PERF_RA_RES_STALL_CSG = 147 +SPI_PERF_RA_RES_STALL_CSN = 148 +SPI_PERF_RA_TMP_STALL_PS = 149 +SPI_PERF_RA_TMP_STALL_VS = 150 +SPI_PERF_RA_TMP_STALL_GS = 151 +SPI_PERF_RA_TMP_STALL_HS = 152 +SPI_PERF_RA_TMP_STALL_CSG = 153 +SPI_PERF_RA_TMP_STALL_CSN = 154 +SPI_PERF_RA_WAVE_SIMD_FULL_PS = 155 +SPI_PERF_RA_WAVE_SIMD_FULL_VS = 156 +SPI_PERF_RA_WAVE_SIMD_FULL_GS = 157 +SPI_PERF_RA_WAVE_SIMD_FULL_HS = 158 +SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 159 +SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 160 +SPI_PERF_RA_VGPR_SIMD_FULL_PS = 161 +SPI_PERF_RA_VGPR_SIMD_FULL_VS = 162 +SPI_PERF_RA_VGPR_SIMD_FULL_GS = 163 +SPI_PERF_RA_VGPR_SIMD_FULL_HS = 164 +SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 165 +SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 166 +SPI_PERF_RA_SGPR_SIMD_FULL_PS = 167 +SPI_PERF_RA_SGPR_SIMD_FULL_VS = 168 +SPI_PERF_RA_SGPR_SIMD_FULL_GS = 169 +SPI_PERF_RA_SGPR_SIMD_FULL_HS = 170 +SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 171 +SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 172 +SPI_PERF_RA_LDS_CU_FULL_PS = 173 +SPI_PERF_RA_LDS_CU_FULL_LS = 174 +SPI_PERF_RA_LDS_CU_FULL_ES = 175 +SPI_PERF_RA_LDS_CU_FULL_CSG = 176 +SPI_PERF_RA_LDS_CU_FULL_CSN = 177 +SPI_PERF_RA_BAR_CU_FULL_HS = 178 +SPI_PERF_RA_BAR_CU_FULL_CSG = 179 +SPI_PERF_RA_BAR_CU_FULL_CSN = 180 +SPI_PERF_RA_BULKY_CU_FULL_CSG = 181 +SPI_PERF_RA_BULKY_CU_FULL_CSN = 182 +SPI_PERF_RA_TGLIM_CU_FULL_CSG = 183 +SPI_PERF_RA_TGLIM_CU_FULL_CSN = 184 +SPI_PERF_RA_WVLIM_STALL_PS = 185 +SPI_PERF_RA_WVLIM_STALL_VS = 186 +SPI_PERF_RA_WVLIM_STALL_GS = 187 +SPI_PERF_RA_WVLIM_STALL_HS = 188 +SPI_PERF_RA_WVLIM_STALL_CSG = 189 +SPI_PERF_RA_WVLIM_STALL_CSN = 190 +SPI_PERF_RA_VS_LOCK = 191 +SPI_PERF_RA_GS_LOCK = 192 +SPI_PERF_RA_HS_LOCK = 193 +SPI_PERF_RA_CSG_LOCK = 194 +SPI_PERF_RA_CSN_LOCK = 195 +SPI_PERF_RA_RSV_UPD = 196 +SPI_PERF_EXP_ARB_COL_CNT = 197 +SPI_PERF_EXP_ARB_PAR_CNT = 198 +SPI_PERF_EXP_ARB_POS_CNT = 199 +SPI_PERF_EXP_ARB_GDS_CNT = 200 +SPI_PERF_NUM_PS_COL_R0_EXPORTS = 201 +SPI_PERF_NUM_PS_COL_R1_EXPORTS = 202 +SPI_PERF_NUM_VS_POS_R0_EXPORTS = 203 +SPI_PERF_NUM_VS_POS_R1_EXPORTS = 204 +SPI_PERF_NUM_VS_PARAM_R0_EXPORTS = 205 +SPI_PERF_NUM_VS_PARAM_R1_EXPORTS = 206 +SPI_PERF_NUM_VS_GDS_R0_EXPORTS = 207 +SPI_PERF_NUM_VS_GDS_R1_EXPORTS = 208 +SPI_PERF_NUM_EXPGRANT_EXPORTS = 209 +SPI_PERF_CLKGATE_BUSY_STALL = 210 +SPI_PERF_CLKGATE_ACTIVE_STALL = 211 +SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 212 +SPI_PERF_CLKGATE_CGTT_DYN_ON = 213 +SPI_PERF_CLKGATE_CGTT_REG_ON = 214 +SPI_PERF_PIX_ALLOC_PEND_CNT = 215 +SPI_PERF_PIX_ALLOC_SCB0_STALL = 216 +SPI_PERF_PIX_ALLOC_SCB1_STALL = 217 +SPI_PERF_PIX_ALLOC_SCB2_STALL = 218 +SPI_PERF_PIX_ALLOC_SCB3_STALL = 219 +SPI_PERF_PIX_ALLOC_DB0_STALL = 220 +SPI_PERF_PIX_ALLOC_DB1_STALL = 221 +SPI_PERF_PIX_ALLOC_DB2_STALL = 222 +SPI_PERF_PIX_ALLOC_DB3_STALL = 223 +SPI_PERF_PIX_ALLOC_DB4_STALL = 224 +SPI_PERF_PIX_ALLOC_DB5_STALL = 225 +SPI_PERF_PIX_ALLOC_DB6_STALL = 226 +SPI_PERF_PIX_ALLOC_DB7_STALL = 227 +SPI_PERF_PC_ALLOC_ACCUM = 228 +SPI_PERF_GS_NGG_SE_HAS_BATON = 229 +SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON = 230 +SPI_PERF_GS_NGG_SE_FORWARDED_BATON = 231 +SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT = 232 +SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT = 233 +SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT = 234 +SPI_PERF_GS_NGG_PC_FULL = 235 +SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 236 +SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY = 237 +SPI_PERF_GSC_VTX_BUSY = 238 +SPI_PERF_GSC_VTX_INPUT_STARVED = 239 +SPI_PERF_GSC_VTX_VSR_STALL = 240 +SPI_PERF_GSC_VTX_VSR_FULL = 241 +SPI_PERF_GSC_VTX_CAC_BUSY = 242 +SPI_PERF_ESC_VTX_BUSY = 243 +SPI_PERF_ESC_VTX_INPUT_STARVED = 244 +SPI_PERF_ESC_VTX_VSR_STALL = 245 +SPI_PERF_ESC_VTX_VSR_FULL = 246 +SPI_PERF_ESC_VTX_CAC_BUSY = 247 +SPI_PERF_SWC_PS_WR = 248 +SPI_PERF_SWC_VS_WR = 249 +SPI_PERF_SWC_GS_WR = 250 +SPI_PERF_SWC_HS_WR = 251 +SPI_PERF_SWC_CSG_WR = 252 +SPI_PERF_SWC_CSC_WR = 253 +SPI_PERF_VWC_PS_WR = 254 +SPI_PERF_VWC_VS_WR = 255 +SPI_PERF_VWC_GS_WR = 256 +SPI_PERF_VWC_HS_WR = 257 +SPI_PERF_VWC_CSG_WR = 258 +SPI_PERF_VWC_CSC_WR = 259 +SPI_PERF_ES_WINDOW_VALID = 260 +SPI_PERF_ES_BUSY = 261 +SPI_PERF_ES_CRAWLER_STALL = 262 +SPI_PERF_ES_FIRST_WAVE = 263 +SPI_PERF_ES_LAST_WAVE = 264 +SPI_PERF_ES_LSHS_DEALLOC = 265 +SPI_PERF_ES_EVENT_WAVE = 266 +SPI_PERF_ES_WAVE = 267 +SPI_PERF_ES_PERS_UPD_FULL0 = 268 +SPI_PERF_ES_PERS_UPD_FULL1 = 269 +SPI_PERF_ES_FIRST_SUBGRP = 270 +SPI_PERF_ES_LAST_SUBGRP = 271 +SPI_PERF_LS_WINDOW_VALID = 272 +SPI_PERF_LS_BUSY = 273 +SPI_PERF_LS_CRAWLER_STALL = 274 +SPI_PERF_LS_FIRST_WAVE = 275 +SPI_PERF_LS_LAST_WAVE = 276 +SPI_PERF_LS_OFFCHIP_LDS_STALL = 277 +SPI_PERF_LS_EVENT_WAVE = 278 +SPI_PERF_LS_WAVE = 279 +SPI_PERF_LS_PERS_UPD_FULL0 = 280 +SPI_PERF_LS_PERS_UPD_FULL1 = 281 +SPI_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_FORMAT' +SPI_SHADER_FORMAT__enumvalues = { + 0: 'SPI_SHADER_NONE', + 1: 'SPI_SHADER_1COMP', + 2: 'SPI_SHADER_2COMP', + 3: 'SPI_SHADER_4COMPRESS', + 4: 'SPI_SHADER_4COMP', +} +SPI_SHADER_NONE = 0 +SPI_SHADER_1COMP = 1 +SPI_SHADER_2COMP = 2 +SPI_SHADER_4COMPRESS = 3 +SPI_SHADER_4COMP = 4 +SPI_SHADER_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_EX_FORMAT' +SPI_SHADER_EX_FORMAT__enumvalues = { + 0: 'SPI_SHADER_ZERO', + 1: 'SPI_SHADER_32_R', + 2: 'SPI_SHADER_32_GR', + 3: 'SPI_SHADER_32_AR', + 4: 'SPI_SHADER_FP16_ABGR', + 5: 'SPI_SHADER_UNORM16_ABGR', + 6: 'SPI_SHADER_SNORM16_ABGR', + 7: 'SPI_SHADER_UINT16_ABGR', + 8: 'SPI_SHADER_SINT16_ABGR', + 9: 'SPI_SHADER_32_ABGR', +} +SPI_SHADER_ZERO = 0 +SPI_SHADER_32_R = 1 +SPI_SHADER_32_GR = 2 +SPI_SHADER_32_AR = 3 +SPI_SHADER_FP16_ABGR = 4 +SPI_SHADER_UNORM16_ABGR = 5 +SPI_SHADER_SNORM16_ABGR = 6 +SPI_SHADER_UINT16_ABGR = 7 +SPI_SHADER_SINT16_ABGR = 8 +SPI_SHADER_32_ABGR = 9 +SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_SM_MODE' +CLKGATE_SM_MODE__enumvalues = { + 0: 'ON_SEQ', + 1: 'OFF_SEQ', + 2: 'PROG_SEQ', + 3: 'READ_SEQ', + 4: 'SM_MODE_RESERVED', +} +ON_SEQ = 0 +OFF_SEQ = 1 +PROG_SEQ = 2 +READ_SEQ = 3 +SM_MODE_RESERVED = 4 +CLKGATE_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_BASE_MODE' +CLKGATE_BASE_MODE__enumvalues = { + 0: 'MULT_8', + 1: 'MULT_16', +} +MULT_8 = 0 +MULT_16 = 1 +CLKGATE_BASE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_LB_WAVES_SELECT' +SPI_LB_WAVES_SELECT__enumvalues = { + 0: 'HS_GS', + 1: 'VS_PS', + 2: 'CS_NA', + 3: 'SPI_LB_WAVES_RSVD', +} +HS_GS = 0 +VS_PS = 1 +CS_NA = 2 +SPI_LB_WAVES_RSVD = 3 +SPI_LB_WAVES_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_CLAMP' +SQ_TEX_CLAMP__enumvalues = { + 0: 'SQ_TEX_WRAP', + 1: 'SQ_TEX_MIRROR', + 2: 'SQ_TEX_CLAMP_LAST_TEXEL', + 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 4: 'SQ_TEX_CLAMP_HALF_BORDER', + 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', + 6: 'SQ_TEX_CLAMP_BORDER', + 7: 'SQ_TEX_MIRROR_ONCE_BORDER', +} +SQ_TEX_WRAP = 0 +SQ_TEX_MIRROR = 1 +SQ_TEX_CLAMP_LAST_TEXEL = 2 +SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 +SQ_TEX_CLAMP_HALF_BORDER = 4 +SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 +SQ_TEX_CLAMP_BORDER = 6 +SQ_TEX_MIRROR_ONCE_BORDER = 7 +SQ_TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_XY_FILTER' +SQ_TEX_XY_FILTER__enumvalues = { + 0: 'SQ_TEX_XY_FILTER_POINT', + 1: 'SQ_TEX_XY_FILTER_BILINEAR', + 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', + 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', +} +SQ_TEX_XY_FILTER_POINT = 0 +SQ_TEX_XY_FILTER_BILINEAR = 1 +SQ_TEX_XY_FILTER_ANISO_POINT = 2 +SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 +SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_Z_FILTER' +SQ_TEX_Z_FILTER__enumvalues = { + 0: 'SQ_TEX_Z_FILTER_NONE', + 1: 'SQ_TEX_Z_FILTER_POINT', + 2: 'SQ_TEX_Z_FILTER_LINEAR', +} +SQ_TEX_Z_FILTER_NONE = 0 +SQ_TEX_Z_FILTER_POINT = 1 +SQ_TEX_Z_FILTER_LINEAR = 2 +SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_MIP_FILTER' +SQ_TEX_MIP_FILTER__enumvalues = { + 0: 'SQ_TEX_MIP_FILTER_NONE', + 1: 'SQ_TEX_MIP_FILTER_POINT', + 2: 'SQ_TEX_MIP_FILTER_LINEAR', + 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', +} +SQ_TEX_MIP_FILTER_NONE = 0 +SQ_TEX_MIP_FILTER_POINT = 1 +SQ_TEX_MIP_FILTER_LINEAR = 2 +SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 +SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_ANISO_RATIO' +SQ_TEX_ANISO_RATIO__enumvalues = { + 0: 'SQ_TEX_ANISO_RATIO_1', + 1: 'SQ_TEX_ANISO_RATIO_2', + 2: 'SQ_TEX_ANISO_RATIO_4', + 3: 'SQ_TEX_ANISO_RATIO_8', + 4: 'SQ_TEX_ANISO_RATIO_16', +} +SQ_TEX_ANISO_RATIO_1 = 0 +SQ_TEX_ANISO_RATIO_2 = 1 +SQ_TEX_ANISO_RATIO_4 = 2 +SQ_TEX_ANISO_RATIO_8 = 3 +SQ_TEX_ANISO_RATIO_16 = 4 +SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_DEPTH_COMPARE' +SQ_TEX_DEPTH_COMPARE__enumvalues = { + 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', + 1: 'SQ_TEX_DEPTH_COMPARE_LESS', + 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', + 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', + 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', + 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', + 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', +} +SQ_TEX_DEPTH_COMPARE_NEVER = 0 +SQ_TEX_DEPTH_COMPARE_LESS = 1 +SQ_TEX_DEPTH_COMPARE_EQUAL = 2 +SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 +SQ_TEX_DEPTH_COMPARE_GREATER = 4 +SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 +SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 +SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 +SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_BORDER_COLOR' +SQ_TEX_BORDER_COLOR__enumvalues = { + 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 3: 'SQ_TEX_BORDER_COLOR_REGISTER', +} +SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 +SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 +SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 +SQ_TEX_BORDER_COLOR_REGISTER = 3 +SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_BUF_TYPE' +SQ_RSRC_BUF_TYPE__enumvalues = { + 0: 'SQ_RSRC_BUF', + 1: 'SQ_RSRC_BUF_RSVD_1', + 2: 'SQ_RSRC_BUF_RSVD_2', + 3: 'SQ_RSRC_BUF_RSVD_3', +} +SQ_RSRC_BUF = 0 +SQ_RSRC_BUF_RSVD_1 = 1 +SQ_RSRC_BUF_RSVD_2 = 2 +SQ_RSRC_BUF_RSVD_3 = 3 +SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_IMG_TYPE' +SQ_RSRC_IMG_TYPE__enumvalues = { + 0: 'SQ_RSRC_IMG_RSVD_0', + 1: 'SQ_RSRC_IMG_RSVD_1', + 2: 'SQ_RSRC_IMG_RSVD_2', + 3: 'SQ_RSRC_IMG_RSVD_3', + 4: 'SQ_RSRC_IMG_RSVD_4', + 5: 'SQ_RSRC_IMG_RSVD_5', + 6: 'SQ_RSRC_IMG_RSVD_6', + 7: 'SQ_RSRC_IMG_RSVD_7', + 8: 'SQ_RSRC_IMG_1D', + 9: 'SQ_RSRC_IMG_2D', + 10: 'SQ_RSRC_IMG_3D', + 11: 'SQ_RSRC_IMG_CUBE', + 12: 'SQ_RSRC_IMG_1D_ARRAY', + 13: 'SQ_RSRC_IMG_2D_ARRAY', + 14: 'SQ_RSRC_IMG_2D_MSAA', + 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', +} +SQ_RSRC_IMG_RSVD_0 = 0 +SQ_RSRC_IMG_RSVD_1 = 1 +SQ_RSRC_IMG_RSVD_2 = 2 +SQ_RSRC_IMG_RSVD_3 = 3 +SQ_RSRC_IMG_RSVD_4 = 4 +SQ_RSRC_IMG_RSVD_5 = 5 +SQ_RSRC_IMG_RSVD_6 = 6 +SQ_RSRC_IMG_RSVD_7 = 7 +SQ_RSRC_IMG_1D = 8 +SQ_RSRC_IMG_2D = 9 +SQ_RSRC_IMG_3D = 10 +SQ_RSRC_IMG_CUBE = 11 +SQ_RSRC_IMG_1D_ARRAY = 12 +SQ_RSRC_IMG_2D_ARRAY = 13 +SQ_RSRC_IMG_2D_MSAA = 14 +SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 +SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_FLAT_TYPE' +SQ_RSRC_FLAT_TYPE__enumvalues = { + 0: 'SQ_RSRC_FLAT_RSVD_0', + 1: 'SQ_RSRC_FLAT', + 2: 'SQ_RSRC_FLAT_RSVD_2', + 3: 'SQ_RSRC_FLAT_RSVD_3', +} +SQ_RSRC_FLAT_RSVD_0 = 0 +SQ_RSRC_FLAT = 1 +SQ_RSRC_FLAT_RSVD_2 = 2 +SQ_RSRC_FLAT_RSVD_3 = 3 +SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IMG_FILTER_TYPE' +SQ_IMG_FILTER_TYPE__enumvalues = { + 0: 'SQ_IMG_FILTER_MODE_BLEND', + 1: 'SQ_IMG_FILTER_MODE_MIN', + 2: 'SQ_IMG_FILTER_MODE_MAX', +} +SQ_IMG_FILTER_MODE_BLEND = 0 +SQ_IMG_FILTER_MODE_MIN = 1 +SQ_IMG_FILTER_MODE_MAX = 2 +SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_SEL_XYZW01' +SQ_SEL_XYZW01__enumvalues = { + 0: 'SQ_SEL_0', + 1: 'SQ_SEL_1', + 2: 'SQ_SEL_N_BC_1', + 3: 'SQ_SEL_RESERVED_1', + 4: 'SQ_SEL_X', + 5: 'SQ_SEL_Y', + 6: 'SQ_SEL_Z', + 7: 'SQ_SEL_W', +} +SQ_SEL_0 = 0 +SQ_SEL_1 = 1 +SQ_SEL_N_BC_1 = 2 +SQ_SEL_RESERVED_1 = 3 +SQ_SEL_X = 4 +SQ_SEL_Y = 5 +SQ_SEL_Z = 6 +SQ_SEL_W = 7 +SQ_SEL_XYZW01 = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_OOB_SELECT' +SQ_OOB_SELECT__enumvalues = { + 0: 'SQ_OOB_INDEX_AND_OFFSET', + 1: 'SQ_OOB_INDEX_ONLY', + 2: 'SQ_OOB_NUM_RECORDS_0', + 3: 'SQ_OOB_COMPLETE', +} +SQ_OOB_INDEX_AND_OFFSET = 0 +SQ_OOB_INDEX_ONLY = 1 +SQ_OOB_NUM_RECORDS_0 = 2 +SQ_OOB_COMPLETE = 3 +SQ_OOB_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_TYPE' +SQ_WAVE_TYPE__enumvalues = { + 0: 'SQ_WAVE_TYPE_PS', + 1: 'SQ_WAVE_TYPE_VS', + 2: 'SQ_WAVE_TYPE_GS', + 3: 'SQ_WAVE_TYPE_ES', + 4: 'SQ_WAVE_TYPE_HS', + 5: 'SQ_WAVE_TYPE_LS', + 6: 'SQ_WAVE_TYPE_CS', + 7: 'SQ_WAVE_TYPE_PS1', + 8: 'SQ_WAVE_TYPE_PS2', + 9: 'SQ_WAVE_TYPE_PS3', +} +SQ_WAVE_TYPE_PS = 0 +SQ_WAVE_TYPE_VS = 1 +SQ_WAVE_TYPE_GS = 2 +SQ_WAVE_TYPE_ES = 3 +SQ_WAVE_TYPE_HS = 4 +SQ_WAVE_TYPE_LS = 5 +SQ_WAVE_TYPE_CS = 6 +SQ_WAVE_TYPE_PS1 = 7 +SQ_WAVE_TYPE_PS2 = 8 +SQ_WAVE_TYPE_PS3 = 9 +SQ_WAVE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_PERF_SEL' +SQ_PERF_SEL__enumvalues = { + 0: 'SQ_PERF_SEL_NONE', + 1: 'SQ_PERF_SEL_ACCUM_PREV', + 2: 'SQ_PERF_SEL_CYCLES', + 3: 'SQ_PERF_SEL_BUSY_CYCLES', + 4: 'SQ_PERF_SEL_WAVES', + 5: 'SQ_PERF_SEL_WAVES_32', + 6: 'SQ_PERF_SEL_WAVES_64', + 7: 'SQ_PERF_SEL_LEVEL_WAVES', + 8: 'SQ_PERF_SEL_ITEMS', + 9: 'SQ_PERF_SEL_WAVE32_ITEMS', + 10: 'SQ_PERF_SEL_WAVE64_ITEMS', + 11: 'SQ_PERF_SEL_QUADS', + 12: 'SQ_PERF_SEL_EVENTS', + 13: 'SQ_PERF_SEL_WAVES_EQ_64', + 14: 'SQ_PERF_SEL_WAVES_LT_64', + 15: 'SQ_PERF_SEL_WAVES_LT_48', + 16: 'SQ_PERF_SEL_WAVES_LT_32', + 17: 'SQ_PERF_SEL_WAVES_LT_16', + 18: 'SQ_PERF_SEL_WAVES_RESTORED', + 19: 'SQ_PERF_SEL_WAVES_SAVED', + 20: 'SQ_PERF_SEL_MSG', + 21: 'SQ_PERF_SEL_MSG_GSCNT', + 22: 'SQ_PERF_SEL_MSG_INTERRUPT', + 23: 'SQ_PERF_SEL_Reserved_1', + 24: 'SQ_PERF_SEL_Reserved_2', + 25: 'SQ_PERF_SEL_Reserved_3', + 26: 'SQ_PERF_SEL_WAVE_CYCLES', + 27: 'SQ_PERF_SEL_WAVE_READY', + 28: 'SQ_PERF_SEL_WAIT_INST_ANY', + 29: 'SQ_PERF_SEL_WAIT_INST_VALU', + 30: 'SQ_PERF_SEL_WAIT_INST_SCA', + 31: 'SQ_PERF_SEL_WAIT_INST_LDS', + 32: 'SQ_PERF_SEL_WAIT_INST_TEX', + 33: 'SQ_PERF_SEL_WAIT_INST_FLAT', + 34: 'SQ_PERF_SEL_WAIT_INST_VMEM', + 35: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', + 36: 'SQ_PERF_SEL_WAIT_INST_BR_MSG', + 37: 'SQ_PERF_SEL_WAIT_ANY', + 38: 'SQ_PERF_SEL_WAIT_CNT_ANY', + 39: 'SQ_PERF_SEL_WAIT_CNT_VMVS', + 40: 'SQ_PERF_SEL_WAIT_CNT_LGKM', + 41: 'SQ_PERF_SEL_WAIT_CNT_EXP', + 42: 'SQ_PERF_SEL_WAIT_TTRACE', + 43: 'SQ_PERF_SEL_WAIT_IFETCH', + 44: 'SQ_PERF_SEL_WAIT_BARRIER', + 45: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', + 46: 'SQ_PERF_SEL_WAIT_SLEEP', + 47: 'SQ_PERF_SEL_WAIT_SLEEP_XNACK', + 48: 'SQ_PERF_SEL_WAIT_OTHER', + 49: 'SQ_PERF_SEL_INSTS_ALL', + 50: 'SQ_PERF_SEL_INSTS_BRANCH', + 51: 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', + 52: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', + 53: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', + 54: 'SQ_PERF_SEL_INSTS_EXP_GDS', + 55: 'SQ_PERF_SEL_INSTS_GDS', + 56: 'SQ_PERF_SEL_INSTS_EXP', + 57: 'SQ_PERF_SEL_INSTS_FLAT', + 58: 'SQ_PERF_SEL_Reserved_4', + 59: 'SQ_PERF_SEL_INSTS_LDS', + 60: 'SQ_PERF_SEL_INSTS_SALU', + 61: 'SQ_PERF_SEL_INSTS_SMEM', + 62: 'SQ_PERF_SEL_INSTS_SMEM_NORM', + 63: 'SQ_PERF_SEL_INSTS_SENDMSG', + 64: 'SQ_PERF_SEL_INSTS_VALU', + 65: 'SQ_PERF_SEL_Reserved_17', + 66: 'SQ_PERF_SEL_INSTS_VALU_TRANS32', + 67: 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', + 68: 'SQ_PERF_SEL_INSTS_TEX', + 69: 'SQ_PERF_SEL_INSTS_TEX_LOAD', + 70: 'SQ_PERF_SEL_INSTS_TEX_STORE', + 71: 'SQ_PERF_SEL_INSTS_WAVE32', + 72: 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', + 73: 'SQ_PERF_SEL_Reserved_5', + 74: 'SQ_PERF_SEL_INSTS_WAVE32_LDS', + 75: 'SQ_PERF_SEL_INSTS_WAVE32_VALU', + 76: 'SQ_PERF_SEL_Reserved_16', + 77: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', + 78: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', + 79: 'SQ_PERF_SEL_INSTS_WAVE32_TEX', + 80: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', + 81: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', + 82: 'SQ_PERF_SEL_ITEM_CYCLES_VALU', + 83: 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', + 84: 'SQ_PERF_SEL_WAVE32_INSTS', + 85: 'SQ_PERF_SEL_WAVE64_INSTS', + 86: 'SQ_PERF_SEL_Reserved_18', + 87: 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', + 88: 'SQ_PERF_SEL_WAVE64_HALF_SKIP', + 89: 'SQ_PERF_SEL_INSTS_TEX_REPLAY', + 90: 'SQ_PERF_SEL_INSTS_SMEM_REPLAY', + 91: 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY', + 92: 'SQ_PERF_SEL_INSTS_FLAT_REPLAY', + 93: 'SQ_PERF_SEL_XNACK_ALL', + 94: 'SQ_PERF_SEL_XNACK_FIRST', + 95: 'SQ_PERF_SEL_INSTS_VALU_LDS_DIRECT_RD', + 96: 'SQ_PERF_SEL_INSTS_VALU_VINTRP_OP', + 97: 'SQ_PERF_SEL_INST_LEVEL_EXP', + 98: 'SQ_PERF_SEL_INST_LEVEL_GDS', + 99: 'SQ_PERF_SEL_INST_LEVEL_LDS', + 100: 'SQ_PERF_SEL_INST_LEVEL_SMEM', + 101: 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', + 102: 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', + 103: 'SQ_PERF_SEL_IFETCH_REQS', + 104: 'SQ_PERF_SEL_IFETCH_LEVEL', + 105: 'SQ_PERF_SEL_IFETCH_XNACK', + 106: 'SQ_PERF_SEL_Reserved_6', + 107: 'SQ_PERF_SEL_Reserved_7', + 108: 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', + 109: 'SQ_PERF_SEL_VALU_SGATHER_STALL', + 110: 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', + 111: 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', + 112: 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', + 113: 'SQ_PERF_SEL_SALU_SGATHER_STALL', + 114: 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', + 115: 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', + 116: 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', + 117: 'SQ_PERF_SEL_INST_CYCLES_VALU', + 118: 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', + 119: 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', + 120: 'SQ_PERF_SEL_INST_CYCLES_VMEM', + 121: 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', + 122: 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', + 123: 'SQ_PERF_SEL_INST_CYCLES_LDS', + 124: 'SQ_PERF_SEL_INST_CYCLES_TEX', + 125: 'SQ_PERF_SEL_INST_CYCLES_FLAT', + 126: 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', + 127: 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', + 128: 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', + 129: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 130: 'SQ_PERF_SEL_Reserved_8', + 131: 'SQ_PERF_SEL_Reserved_9', + 132: 'SQ_PERF_SEL_Reserved_10', + 133: 'SQ_PERF_SEL_Reserved_11', + 134: 'SQ_PERF_SEL_Reserved_12', + 135: 'SQ_PERF_SEL_Reserved_13', + 136: 'SQ_PERF_SEL_Reserved_14', + 137: 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', + 138: 'SQ_PERF_SEL_VMEM_BUS_STALL', + 139: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', + 140: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', + 141: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', + 142: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', + 143: 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', + 144: 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', + 145: 'SQ_PERF_SEL_Reserved_15', + 146: 'SQ_PERF_SEL_SALU_PIPE_STALL', + 147: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', + 148: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_STALL', + 149: 'SQ_PERF_SEL_MSG_BUS_BUSY', + 150: 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', + 151: 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', + 152: 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', + 153: 'SQ_PERF_SEL_EXP_BUS0_BUSY', + 154: 'SQ_PERF_SEL_EXP_BUS1_BUSY', + 155: 'SQ_PERF_SEL_INST_CACHE_REQS', + 156: 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', + 157: 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VALU', + 158: 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_SALU', + 159: 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VMEM', + 160: 'SQ_PERF_SEL_USER0', + 161: 'SQ_PERF_SEL_USER1', + 162: 'SQ_PERF_SEL_USER2', + 163: 'SQ_PERF_SEL_USER3', + 164: 'SQ_PERF_SEL_USER4', + 165: 'SQ_PERF_SEL_USER5', + 166: 'SQ_PERF_SEL_USER6', + 167: 'SQ_PERF_SEL_USER7', + 168: 'SQ_PERF_SEL_USER8', + 169: 'SQ_PERF_SEL_USER9', + 170: 'SQ_PERF_SEL_USER10', + 171: 'SQ_PERF_SEL_USER11', + 172: 'SQ_PERF_SEL_USER12', + 173: 'SQ_PERF_SEL_USER13', + 174: 'SQ_PERF_SEL_USER14', + 175: 'SQ_PERF_SEL_USER15', + 176: 'SQ_PERF_SEL_USER_LEVEL0', + 177: 'SQ_PERF_SEL_USER_LEVEL1', + 178: 'SQ_PERF_SEL_USER_LEVEL2', + 179: 'SQ_PERF_SEL_USER_LEVEL3', + 180: 'SQ_PERF_SEL_USER_LEVEL4', + 181: 'SQ_PERF_SEL_USER_LEVEL5', + 182: 'SQ_PERF_SEL_USER_LEVEL6', + 183: 'SQ_PERF_SEL_USER_LEVEL7', + 184: 'SQ_PERF_SEL_USER_LEVEL8', + 185: 'SQ_PERF_SEL_USER_LEVEL9', + 186: 'SQ_PERF_SEL_USER_LEVEL10', + 187: 'SQ_PERF_SEL_USER_LEVEL11', + 188: 'SQ_PERF_SEL_USER_LEVEL12', + 189: 'SQ_PERF_SEL_USER_LEVEL13', + 190: 'SQ_PERF_SEL_USER_LEVEL14', + 191: 'SQ_PERF_SEL_USER_LEVEL15', + 192: 'SQ_PERF_SEL_VALU_RETURN_SDST', + 193: 'SQ_PERF_SEL_VMEM_SECOND_TRY_USED', + 194: 'SQ_PERF_SEL_VMEM_SECOND_TRY_STALL', + 195: 'SQ_PERF_SEL_DUMMY_END', + 255: 'SQ_PERF_SEL_DUMMY_LAST', + 256: 'SQG_PERF_SEL_UTCL0_TRANSLATION_MISS', + 257: 'SQG_PERF_SEL_UTCL0_PERMISSION_MISS', + 258: 'SQG_PERF_SEL_UTCL0_TRANSLATION_HIT', + 259: 'SQG_PERF_SEL_UTCL0_REQUEST', + 260: 'SQG_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 261: 'SQG_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 262: 'SQG_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 263: 'SQG_PERF_SEL_UTCL0_LFIFO_FULL', + 264: 'SQG_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 265: 'SQG_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 266: 'SQG_PERF_SEL_UTCL0_HIT_FIFO_FULL', + 267: 'SQG_PERF_SEL_UTCL0_UTCL1_REQ', + 268: 'SQG_PERF_SEL_TLB_SHOOTDOWN', + 269: 'SQG_PERF_SEL_TLB_SHOOTDOWN_CYCLES', + 270: 'SQG_PERF_SEL_TTRACE_REQS', + 271: 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', + 272: 'SQG_PERF_SEL_TTRACE_STALL', + 273: 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', + 274: 'SQG_PERF_SEL_DUMMY_LAST', + 275: 'SQC_PERF_SEL_POWER_VALU', + 276: 'SQC_PERF_SEL_POWER_VALU0', + 277: 'SQC_PERF_SEL_POWER_VALU1', + 278: 'SQC_PERF_SEL_POWER_VALU2', + 279: 'SQC_PERF_SEL_POWER_GPR_RD', + 280: 'SQC_PERF_SEL_POWER_GPR_WR', + 281: 'SQC_PERF_SEL_POWER_LDS_BUSY', + 282: 'SQC_PERF_SEL_POWER_ALU_BUSY', + 283: 'SQC_PERF_SEL_POWER_TEX_BUSY', + 284: 'SQC_PERF_SEL_PT_POWER_STALL', + 285: 'SQC_PERF_SEL_LDS_BANK_CONFLICT', + 286: 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', + 287: 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', + 288: 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', + 289: 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', + 290: 'SQC_PERF_SEL_LDS_IDX_ACTIVE', + 291: 'SQC_PERF_SEL_LDS_DATA_FIFO_FULL', + 292: 'SQC_PERF_SEL_LDS_CMD_FIFO_FULL', + 293: 'SQC_PERF_SEL_LDS_ADDR_STALL', + 294: 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', + 295: 'SQC_PERF_SEL_LDS_DIRECT_FIFO_FULL_STALL', + 296: 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', + 297: 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', + 298: 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', + 299: 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', + 300: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 301: 'SQC_PERF_SEL_ICACHE_REQ', + 302: 'SQC_PERF_SEL_ICACHE_HITS', + 303: 'SQC_PERF_SEL_ICACHE_MISSES', + 304: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', + 305: 'SQC_PERF_SEL_ICACHE_INVAL_INST', + 306: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 307: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 308: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 309: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', + 310: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 311: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 312: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY', + 313: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 314: 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB', + 315: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY', + 316: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 317: 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB', + 318: 'SQC_PERF_SEL_TC_REQ', + 319: 'SQC_PERF_SEL_TC_INST_REQ', + 320: 'SQC_PERF_SEL_TC_DATA_READ_REQ', + 321: 'SQC_PERF_SEL_TC_DATA_WRITE_REQ', + 322: 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ', + 323: 'SQC_PERF_SEL_TC_STALL', + 324: 'SQC_PERF_SEL_TC_STARVE', + 325: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 326: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 327: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 328: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO', + 329: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 330: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT', + 331: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO', + 332: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO', + 333: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF', + 334: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 335: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 336: 'SQC_PERF_SEL_DCACHE_REQ', + 337: 'SQC_PERF_SEL_DCACHE_HITS', + 338: 'SQC_PERF_SEL_DCACHE_MISSES', + 339: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', + 340: 'SQC_PERF_SEL_DCACHE_INVAL_INST', + 341: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 342: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 343: 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE', + 344: 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', + 345: 'SQC_PERF_SEL_DCACHE_ATOMIC', + 346: 'SQC_PERF_SEL_DCACHE_WB_INST', + 347: 'SQC_PERF_SEL_DCACHE_WB_ASYNC', + 348: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 349: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 350: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 351: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO', + 352: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 353: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 354: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT', + 355: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED', + 356: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE', + 357: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT', + 358: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH', + 359: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE', + 360: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO', + 361: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO', + 362: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF', + 363: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 364: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 365: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 366: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 367: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', + 368: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 369: 'SQC_PERF_SEL_DCACHE_REQ_TIME', + 370: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1', + 371: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2', + 372: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4', + 373: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 374: 'SQC_PERF_SEL_SQ_DCACHE_REQS', + 375: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', + 376: 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', + 377: 'SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_MISS', + 378: 'SQC_PERF_SEL_ICACHE_UTCL0_PERMISSION_MISS', + 379: 'SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_HIT', + 380: 'SQC_PERF_SEL_ICACHE_UTCL0_REQUEST', + 381: 'SQC_PERF_SEL_ICACHE_UTCL0_XNACK', + 382: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_INFLIGHT_MAX', + 383: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_LRU_INFLIGHT', + 384: 'SQC_PERF_SEL_ICACHE_UTCL0_LFIFO_FULL', + 385: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_LFIFO_NOT_RES', + 386: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 387: 'SQC_PERF_SEL_ICACHE_UTCL0_UTCL1_INFLIGHT', + 388: 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_MISSFIFO_FULL', + 389: 'SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_MISS', + 390: 'SQC_PERF_SEL_DCACHE_UTCL0_PERMISSION_MISS', + 391: 'SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_HIT', + 392: 'SQC_PERF_SEL_DCACHE_UTCL0_REQUEST', + 393: 'SQC_PERF_SEL_DCACHE_UTCL0_XNACK', + 394: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_INFLIGHT_MAX', + 395: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_LRU_INFLIGHT', + 396: 'SQC_PERF_SEL_DCACHE_UTCL0_LFIFO_FULL', + 397: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_LFIFO_NOT_RES', + 398: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 399: 'SQC_PERF_SEL_DCACHE_UTCL0_UTCL1_INFLIGHT', + 400: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_MISSFIFO_FULL', + 401: 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_MULTI_MISS', + 402: 'SQC_PERF_SEL_DCACHE_UTCL0_HIT_FIFO_FULL', + 403: 'SQC_PERF_SEL_ICACHE_UTCL0_INFLIGHT_LEVEL', + 404: 'SQC_PERF_SEL_ICACHE_UTCL0_ALL_REQ', + 405: 'SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL', + 406: 'SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ', + 407: 'SQC_PERF_SEL_DCACHE_UTCL0_INFLIGHT_LEVEL', + 408: 'SQC_PERF_SEL_DCACHE_UTCL0_ALL_REQ', + 409: 'SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL', + 410: 'SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ', + 411: 'SQC_PERF_SEL_ICACHE_GCR', + 412: 'SQC_PERF_SEL_ICACHE_GCR_HITS', + 413: 'SQC_PERF_SEL_DCACHE_GCR', + 414: 'SQC_PERF_SEL_DCACHE_GCR_HITS', + 415: 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', + 416: 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', + 417: 'SQC_PERF_SEL_DCACHE_GCR_WRITEBACK', + 418: 'SQC_PERF_SEL_DUMMY_LAST', + 448: 'SP_PERF_SEL_DUMMY_BEGIN', + 511: 'SP_PERF_SEL_DUMMY_LAST', +} +SQ_PERF_SEL_NONE = 0 +SQ_PERF_SEL_ACCUM_PREV = 1 +SQ_PERF_SEL_CYCLES = 2 +SQ_PERF_SEL_BUSY_CYCLES = 3 +SQ_PERF_SEL_WAVES = 4 +SQ_PERF_SEL_WAVES_32 = 5 +SQ_PERF_SEL_WAVES_64 = 6 +SQ_PERF_SEL_LEVEL_WAVES = 7 +SQ_PERF_SEL_ITEMS = 8 +SQ_PERF_SEL_WAVE32_ITEMS = 9 +SQ_PERF_SEL_WAVE64_ITEMS = 10 +SQ_PERF_SEL_QUADS = 11 +SQ_PERF_SEL_EVENTS = 12 +SQ_PERF_SEL_WAVES_EQ_64 = 13 +SQ_PERF_SEL_WAVES_LT_64 = 14 +SQ_PERF_SEL_WAVES_LT_48 = 15 +SQ_PERF_SEL_WAVES_LT_32 = 16 +SQ_PERF_SEL_WAVES_LT_16 = 17 +SQ_PERF_SEL_WAVES_RESTORED = 18 +SQ_PERF_SEL_WAVES_SAVED = 19 +SQ_PERF_SEL_MSG = 20 +SQ_PERF_SEL_MSG_GSCNT = 21 +SQ_PERF_SEL_MSG_INTERRUPT = 22 +SQ_PERF_SEL_Reserved_1 = 23 +SQ_PERF_SEL_Reserved_2 = 24 +SQ_PERF_SEL_Reserved_3 = 25 +SQ_PERF_SEL_WAVE_CYCLES = 26 +SQ_PERF_SEL_WAVE_READY = 27 +SQ_PERF_SEL_WAIT_INST_ANY = 28 +SQ_PERF_SEL_WAIT_INST_VALU = 29 +SQ_PERF_SEL_WAIT_INST_SCA = 30 +SQ_PERF_SEL_WAIT_INST_LDS = 31 +SQ_PERF_SEL_WAIT_INST_TEX = 32 +SQ_PERF_SEL_WAIT_INST_FLAT = 33 +SQ_PERF_SEL_WAIT_INST_VMEM = 34 +SQ_PERF_SEL_WAIT_INST_EXP_GDS = 35 +SQ_PERF_SEL_WAIT_INST_BR_MSG = 36 +SQ_PERF_SEL_WAIT_ANY = 37 +SQ_PERF_SEL_WAIT_CNT_ANY = 38 +SQ_PERF_SEL_WAIT_CNT_VMVS = 39 +SQ_PERF_SEL_WAIT_CNT_LGKM = 40 +SQ_PERF_SEL_WAIT_CNT_EXP = 41 +SQ_PERF_SEL_WAIT_TTRACE = 42 +SQ_PERF_SEL_WAIT_IFETCH = 43 +SQ_PERF_SEL_WAIT_BARRIER = 44 +SQ_PERF_SEL_WAIT_EXP_ALLOC = 45 +SQ_PERF_SEL_WAIT_SLEEP = 46 +SQ_PERF_SEL_WAIT_SLEEP_XNACK = 47 +SQ_PERF_SEL_WAIT_OTHER = 48 +SQ_PERF_SEL_INSTS_ALL = 49 +SQ_PERF_SEL_INSTS_BRANCH = 50 +SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 51 +SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 52 +SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 53 +SQ_PERF_SEL_INSTS_EXP_GDS = 54 +SQ_PERF_SEL_INSTS_GDS = 55 +SQ_PERF_SEL_INSTS_EXP = 56 +SQ_PERF_SEL_INSTS_FLAT = 57 +SQ_PERF_SEL_Reserved_4 = 58 +SQ_PERF_SEL_INSTS_LDS = 59 +SQ_PERF_SEL_INSTS_SALU = 60 +SQ_PERF_SEL_INSTS_SMEM = 61 +SQ_PERF_SEL_INSTS_SMEM_NORM = 62 +SQ_PERF_SEL_INSTS_SENDMSG = 63 +SQ_PERF_SEL_INSTS_VALU = 64 +SQ_PERF_SEL_Reserved_17 = 65 +SQ_PERF_SEL_INSTS_VALU_TRANS32 = 66 +SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 67 +SQ_PERF_SEL_INSTS_TEX = 68 +SQ_PERF_SEL_INSTS_TEX_LOAD = 69 +SQ_PERF_SEL_INSTS_TEX_STORE = 70 +SQ_PERF_SEL_INSTS_WAVE32 = 71 +SQ_PERF_SEL_INSTS_WAVE32_FLAT = 72 +SQ_PERF_SEL_Reserved_5 = 73 +SQ_PERF_SEL_INSTS_WAVE32_LDS = 74 +SQ_PERF_SEL_INSTS_WAVE32_VALU = 75 +SQ_PERF_SEL_Reserved_16 = 76 +SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 77 +SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 78 +SQ_PERF_SEL_INSTS_WAVE32_TEX = 79 +SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 80 +SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 81 +SQ_PERF_SEL_ITEM_CYCLES_VALU = 82 +SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 83 +SQ_PERF_SEL_WAVE32_INSTS = 84 +SQ_PERF_SEL_WAVE64_INSTS = 85 +SQ_PERF_SEL_Reserved_18 = 86 +SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 87 +SQ_PERF_SEL_WAVE64_HALF_SKIP = 88 +SQ_PERF_SEL_INSTS_TEX_REPLAY = 89 +SQ_PERF_SEL_INSTS_SMEM_REPLAY = 90 +SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 91 +SQ_PERF_SEL_INSTS_FLAT_REPLAY = 92 +SQ_PERF_SEL_XNACK_ALL = 93 +SQ_PERF_SEL_XNACK_FIRST = 94 +SQ_PERF_SEL_INSTS_VALU_LDS_DIRECT_RD = 95 +SQ_PERF_SEL_INSTS_VALU_VINTRP_OP = 96 +SQ_PERF_SEL_INST_LEVEL_EXP = 97 +SQ_PERF_SEL_INST_LEVEL_GDS = 98 +SQ_PERF_SEL_INST_LEVEL_LDS = 99 +SQ_PERF_SEL_INST_LEVEL_SMEM = 100 +SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 101 +SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 102 +SQ_PERF_SEL_IFETCH_REQS = 103 +SQ_PERF_SEL_IFETCH_LEVEL = 104 +SQ_PERF_SEL_IFETCH_XNACK = 105 +SQ_PERF_SEL_Reserved_6 = 106 +SQ_PERF_SEL_Reserved_7 = 107 +SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 108 +SQ_PERF_SEL_VALU_SGATHER_STALL = 109 +SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 110 +SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 111 +SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 112 +SQ_PERF_SEL_SALU_SGATHER_STALL = 113 +SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 114 +SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 115 +SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 116 +SQ_PERF_SEL_INST_CYCLES_VALU = 117 +SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 118 +SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 119 +SQ_PERF_SEL_INST_CYCLES_VMEM = 120 +SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 121 +SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 122 +SQ_PERF_SEL_INST_CYCLES_LDS = 123 +SQ_PERF_SEL_INST_CYCLES_TEX = 124 +SQ_PERF_SEL_INST_CYCLES_FLAT = 125 +SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 126 +SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 127 +SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 128 +SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 129 +SQ_PERF_SEL_Reserved_8 = 130 +SQ_PERF_SEL_Reserved_9 = 131 +SQ_PERF_SEL_Reserved_10 = 132 +SQ_PERF_SEL_Reserved_11 = 133 +SQ_PERF_SEL_Reserved_12 = 134 +SQ_PERF_SEL_Reserved_13 = 135 +SQ_PERF_SEL_Reserved_14 = 136 +SQ_PERF_SEL_VMEM_BUS_ACTIVE = 137 +SQ_PERF_SEL_VMEM_BUS_STALL = 138 +SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 139 +SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 140 +SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 141 +SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 142 +SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 143 +SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 144 +SQ_PERF_SEL_Reserved_15 = 145 +SQ_PERF_SEL_SALU_PIPE_STALL = 146 +SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 147 +SQ_PERF_SEL_SMEM_DCACHE_RETURN_STALL = 148 +SQ_PERF_SEL_MSG_BUS_BUSY = 149 +SQ_PERF_SEL_EXP_REQ_BUS_STALL = 150 +SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 151 +SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 152 +SQ_PERF_SEL_EXP_BUS0_BUSY = 153 +SQ_PERF_SEL_EXP_BUS1_BUSY = 154 +SQ_PERF_SEL_INST_CACHE_REQS = 155 +SQ_PERF_SEL_INST_CACHE_REQ_STALL = 156 +SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VALU = 157 +SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_SALU = 158 +SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VMEM = 159 +SQ_PERF_SEL_USER0 = 160 +SQ_PERF_SEL_USER1 = 161 +SQ_PERF_SEL_USER2 = 162 +SQ_PERF_SEL_USER3 = 163 +SQ_PERF_SEL_USER4 = 164 +SQ_PERF_SEL_USER5 = 165 +SQ_PERF_SEL_USER6 = 166 +SQ_PERF_SEL_USER7 = 167 +SQ_PERF_SEL_USER8 = 168 +SQ_PERF_SEL_USER9 = 169 +SQ_PERF_SEL_USER10 = 170 +SQ_PERF_SEL_USER11 = 171 +SQ_PERF_SEL_USER12 = 172 +SQ_PERF_SEL_USER13 = 173 +SQ_PERF_SEL_USER14 = 174 +SQ_PERF_SEL_USER15 = 175 +SQ_PERF_SEL_USER_LEVEL0 = 176 +SQ_PERF_SEL_USER_LEVEL1 = 177 +SQ_PERF_SEL_USER_LEVEL2 = 178 +SQ_PERF_SEL_USER_LEVEL3 = 179 +SQ_PERF_SEL_USER_LEVEL4 = 180 +SQ_PERF_SEL_USER_LEVEL5 = 181 +SQ_PERF_SEL_USER_LEVEL6 = 182 +SQ_PERF_SEL_USER_LEVEL7 = 183 +SQ_PERF_SEL_USER_LEVEL8 = 184 +SQ_PERF_SEL_USER_LEVEL9 = 185 +SQ_PERF_SEL_USER_LEVEL10 = 186 +SQ_PERF_SEL_USER_LEVEL11 = 187 +SQ_PERF_SEL_USER_LEVEL12 = 188 +SQ_PERF_SEL_USER_LEVEL13 = 189 +SQ_PERF_SEL_USER_LEVEL14 = 190 +SQ_PERF_SEL_USER_LEVEL15 = 191 +SQ_PERF_SEL_VALU_RETURN_SDST = 192 +SQ_PERF_SEL_VMEM_SECOND_TRY_USED = 193 +SQ_PERF_SEL_VMEM_SECOND_TRY_STALL = 194 +SQ_PERF_SEL_DUMMY_END = 195 +SQ_PERF_SEL_DUMMY_LAST = 255 +SQG_PERF_SEL_UTCL0_TRANSLATION_MISS = 256 +SQG_PERF_SEL_UTCL0_PERMISSION_MISS = 257 +SQG_PERF_SEL_UTCL0_TRANSLATION_HIT = 258 +SQG_PERF_SEL_UTCL0_REQUEST = 259 +SQG_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 260 +SQG_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 261 +SQG_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 262 +SQG_PERF_SEL_UTCL0_LFIFO_FULL = 263 +SQG_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 264 +SQG_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 265 +SQG_PERF_SEL_UTCL0_HIT_FIFO_FULL = 266 +SQG_PERF_SEL_UTCL0_UTCL1_REQ = 267 +SQG_PERF_SEL_TLB_SHOOTDOWN = 268 +SQG_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 269 +SQG_PERF_SEL_TTRACE_REQS = 270 +SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 271 +SQG_PERF_SEL_TTRACE_STALL = 272 +SQG_PERF_SEL_TTRACE_LOST_PACKETS = 273 +SQG_PERF_SEL_DUMMY_LAST = 274 +SQC_PERF_SEL_POWER_VALU = 275 +SQC_PERF_SEL_POWER_VALU0 = 276 +SQC_PERF_SEL_POWER_VALU1 = 277 +SQC_PERF_SEL_POWER_VALU2 = 278 +SQC_PERF_SEL_POWER_GPR_RD = 279 +SQC_PERF_SEL_POWER_GPR_WR = 280 +SQC_PERF_SEL_POWER_LDS_BUSY = 281 +SQC_PERF_SEL_POWER_ALU_BUSY = 282 +SQC_PERF_SEL_POWER_TEX_BUSY = 283 +SQC_PERF_SEL_PT_POWER_STALL = 284 +SQC_PERF_SEL_LDS_BANK_CONFLICT = 285 +SQC_PERF_SEL_LDS_ADDR_CONFLICT = 286 +SQC_PERF_SEL_LDS_UNALIGNED_STALL = 287 +SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 288 +SQC_PERF_SEL_LDS_ATOMIC_RETURN = 289 +SQC_PERF_SEL_LDS_IDX_ACTIVE = 290 +SQC_PERF_SEL_LDS_DATA_FIFO_FULL = 291 +SQC_PERF_SEL_LDS_CMD_FIFO_FULL = 292 +SQC_PERF_SEL_LDS_ADDR_STALL = 293 +SQC_PERF_SEL_LDS_ADDR_ACTIVE = 294 +SQC_PERF_SEL_LDS_DIRECT_FIFO_FULL_STALL = 295 +SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 296 +SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 297 +SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 298 +SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 299 +SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 300 +SQC_PERF_SEL_ICACHE_REQ = 301 +SQC_PERF_SEL_ICACHE_HITS = 302 +SQC_PERF_SEL_ICACHE_MISSES = 303 +SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 304 +SQC_PERF_SEL_ICACHE_INVAL_INST = 305 +SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 306 +SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 307 +SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 308 +SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 309 +SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 310 +SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 311 +SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 312 +SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 313 +SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 314 +SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 315 +SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 316 +SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 317 +SQC_PERF_SEL_TC_REQ = 318 +SQC_PERF_SEL_TC_INST_REQ = 319 +SQC_PERF_SEL_TC_DATA_READ_REQ = 320 +SQC_PERF_SEL_TC_DATA_WRITE_REQ = 321 +SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 322 +SQC_PERF_SEL_TC_STALL = 323 +SQC_PERF_SEL_TC_STARVE = 324 +SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 325 +SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 326 +SQC_PERF_SEL_ICACHE_CACHE_STALLED = 327 +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 328 +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 329 +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 330 +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 331 +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 332 +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 333 +SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 334 +SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 335 +SQC_PERF_SEL_DCACHE_REQ = 336 +SQC_PERF_SEL_DCACHE_HITS = 337 +SQC_PERF_SEL_DCACHE_MISSES = 338 +SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 339 +SQC_PERF_SEL_DCACHE_INVAL_INST = 340 +SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 341 +SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 342 +SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 343 +SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 344 +SQC_PERF_SEL_DCACHE_ATOMIC = 345 +SQC_PERF_SEL_DCACHE_WB_INST = 346 +SQC_PERF_SEL_DCACHE_WB_ASYNC = 347 +SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 348 +SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 349 +SQC_PERF_SEL_DCACHE_CACHE_STALLED = 350 +SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO = 351 +SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 352 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 353 +SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 354 +SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 355 +SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 356 +SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 357 +SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 358 +SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 359 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 360 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 361 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 362 +SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 363 +SQC_PERF_SEL_DCACHE_REQ_READ_1 = 364 +SQC_PERF_SEL_DCACHE_REQ_READ_2 = 365 +SQC_PERF_SEL_DCACHE_REQ_READ_4 = 366 +SQC_PERF_SEL_DCACHE_REQ_READ_8 = 367 +SQC_PERF_SEL_DCACHE_REQ_READ_16 = 368 +SQC_PERF_SEL_DCACHE_REQ_TIME = 369 +SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 370 +SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 371 +SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 372 +SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 373 +SQC_PERF_SEL_SQ_DCACHE_REQS = 374 +SQC_PERF_SEL_DCACHE_FLAT_REQ = 375 +SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 376 +SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_MISS = 377 +SQC_PERF_SEL_ICACHE_UTCL0_PERMISSION_MISS = 378 +SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_HIT = 379 +SQC_PERF_SEL_ICACHE_UTCL0_REQUEST = 380 +SQC_PERF_SEL_ICACHE_UTCL0_XNACK = 381 +SQC_PERF_SEL_ICACHE_UTCL0_STALL_INFLIGHT_MAX = 382 +SQC_PERF_SEL_ICACHE_UTCL0_STALL_LRU_INFLIGHT = 383 +SQC_PERF_SEL_ICACHE_UTCL0_LFIFO_FULL = 384 +SQC_PERF_SEL_ICACHE_UTCL0_STALL_LFIFO_NOT_RES = 385 +SQC_PERF_SEL_ICACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 386 +SQC_PERF_SEL_ICACHE_UTCL0_UTCL1_INFLIGHT = 387 +SQC_PERF_SEL_ICACHE_UTCL0_STALL_MISSFIFO_FULL = 388 +SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_MISS = 389 +SQC_PERF_SEL_DCACHE_UTCL0_PERMISSION_MISS = 390 +SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_HIT = 391 +SQC_PERF_SEL_DCACHE_UTCL0_REQUEST = 392 +SQC_PERF_SEL_DCACHE_UTCL0_XNACK = 393 +SQC_PERF_SEL_DCACHE_UTCL0_STALL_INFLIGHT_MAX = 394 +SQC_PERF_SEL_DCACHE_UTCL0_STALL_LRU_INFLIGHT = 395 +SQC_PERF_SEL_DCACHE_UTCL0_LFIFO_FULL = 396 +SQC_PERF_SEL_DCACHE_UTCL0_STALL_LFIFO_NOT_RES = 397 +SQC_PERF_SEL_DCACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 398 +SQC_PERF_SEL_DCACHE_UTCL0_UTCL1_INFLIGHT = 399 +SQC_PERF_SEL_DCACHE_UTCL0_STALL_MISSFIFO_FULL = 400 +SQC_PERF_SEL_DCACHE_UTCL0_STALL_MULTI_MISS = 401 +SQC_PERF_SEL_DCACHE_UTCL0_HIT_FIFO_FULL = 402 +SQC_PERF_SEL_ICACHE_UTCL0_INFLIGHT_LEVEL = 403 +SQC_PERF_SEL_ICACHE_UTCL0_ALL_REQ = 404 +SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL = 405 +SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ = 406 +SQC_PERF_SEL_DCACHE_UTCL0_INFLIGHT_LEVEL = 407 +SQC_PERF_SEL_DCACHE_UTCL0_ALL_REQ = 408 +SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL = 409 +SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ = 410 +SQC_PERF_SEL_ICACHE_GCR = 411 +SQC_PERF_SEL_ICACHE_GCR_HITS = 412 +SQC_PERF_SEL_DCACHE_GCR = 413 +SQC_PERF_SEL_DCACHE_GCR_HITS = 414 +SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 415 +SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 416 +SQC_PERF_SEL_DCACHE_GCR_WRITEBACK = 417 +SQC_PERF_SEL_DUMMY_LAST = 418 +SP_PERF_SEL_DUMMY_BEGIN = 448 +SP_PERF_SEL_DUMMY_LAST = 511 +SQ_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_CAC_POWER_SEL' +SQ_CAC_POWER_SEL__enumvalues = { + 0: 'SQ_CAC_POWER_VALU', + 1: 'SQ_CAC_POWER_VALU0', + 2: 'SQ_CAC_POWER_VALU1', + 3: 'SQ_CAC_POWER_VALU2', + 4: 'SQ_CAC_POWER_GPR_RD', + 5: 'SQ_CAC_POWER_GPR_WR', + 6: 'SQ_CAC_POWER_LDS_BUSY', + 7: 'SQ_CAC_POWER_ALU_BUSY', + 8: 'SQ_CAC_POWER_TEX_BUSY', +} +SQ_CAC_POWER_VALU = 0 +SQ_CAC_POWER_VALU0 = 1 +SQ_CAC_POWER_VALU1 = 2 +SQ_CAC_POWER_VALU2 = 3 +SQ_CAC_POWER_GPR_RD = 4 +SQ_CAC_POWER_GPR_WR = 5 +SQ_CAC_POWER_LDS_BUSY = 6 +SQ_CAC_POWER_ALU_BUSY = 7 +SQ_CAC_POWER_TEX_BUSY = 8 +SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_CMD' +SQ_IND_CMD_CMD__enumvalues = { + 0: 'SQ_IND_CMD_CMD_NULL', + 1: 'SQ_IND_CMD_CMD_SETHALT', + 2: 'SQ_IND_CMD_CMD_SAVECTX', + 3: 'SQ_IND_CMD_CMD_KILL', + 4: 'SQ_IND_CMD_CMD_DEBUG', + 5: 'SQ_IND_CMD_CMD_TRAP', + 6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO', + 7: 'SQ_IND_CMD_CMD_SETFATALHALT', + 8: 'SQ_IND_CMD_CMD_SINGLE_STEP', +} +SQ_IND_CMD_CMD_NULL = 0 +SQ_IND_CMD_CMD_SETHALT = 1 +SQ_IND_CMD_CMD_SAVECTX = 2 +SQ_IND_CMD_CMD_KILL = 3 +SQ_IND_CMD_CMD_DEBUG = 4 +SQ_IND_CMD_CMD_TRAP = 5 +SQ_IND_CMD_CMD_SET_SPI_PRIO = 6 +SQ_IND_CMD_CMD_SETFATALHALT = 7 +SQ_IND_CMD_CMD_SINGLE_STEP = 8 +SQ_IND_CMD_CMD = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_MODE' +SQ_IND_CMD_MODE__enumvalues = { + 0: 'SQ_IND_CMD_MODE_SINGLE', + 1: 'SQ_IND_CMD_MODE_BROADCAST', + 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', + 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', +} +SQ_IND_CMD_MODE_SINGLE = 0 +SQ_IND_CMD_MODE_BROADCAST = 1 +SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 +SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 +SQ_IND_CMD_MODE_BROADCAST_ME = 4 +SQ_IND_CMD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_EDC_INFO_SOURCE' +SQ_EDC_INFO_SOURCE__enumvalues = { + 0: 'SQ_EDC_INFO_SOURCE_INVALID', + 1: 'SQ_EDC_INFO_SOURCE_INST', + 2: 'SQ_EDC_INFO_SOURCE_SGPR', + 3: 'SQ_EDC_INFO_SOURCE_VGPR', + 4: 'SQ_EDC_INFO_SOURCE_LDS', + 5: 'SQ_EDC_INFO_SOURCE_GDS', + 6: 'SQ_EDC_INFO_SOURCE_TA', +} +SQ_EDC_INFO_SOURCE_INVALID = 0 +SQ_EDC_INFO_SOURCE_INST = 1 +SQ_EDC_INFO_SOURCE_SGPR = 2 +SQ_EDC_INFO_SOURCE_VGPR = 3 +SQ_EDC_INFO_SOURCE_LDS = 4 +SQ_EDC_INFO_SOURCE_GDS = 5 +SQ_EDC_INFO_SOURCE_TA = 6 +SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_ROUND_MODE' +SQ_ROUND_MODE__enumvalues = { + 0: 'SQ_ROUND_NEAREST_EVEN', + 1: 'SQ_ROUND_PLUS_INFINITY', + 2: 'SQ_ROUND_MINUS_INFINITY', + 3: 'SQ_ROUND_TO_ZERO', +} +SQ_ROUND_NEAREST_EVEN = 0 +SQ_ROUND_PLUS_INFINITY = 1 +SQ_ROUND_MINUS_INFINITY = 2 +SQ_ROUND_TO_ZERO = 3 +SQ_ROUND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INTERRUPT_WORD_ENCODING' +SQ_INTERRUPT_WORD_ENCODING__enumvalues = { + 0: 'SQ_INTERRUPT_WORD_ENCODING_AUTO', + 1: 'SQ_INTERRUPT_WORD_ENCODING_INST', + 2: 'SQ_INTERRUPT_WORD_ENCODING_ERROR', +} +SQ_INTERRUPT_WORD_ENCODING_AUTO = 0 +SQ_INTERRUPT_WORD_ENCODING_INST = 1 +SQ_INTERRUPT_WORD_ENCODING_ERROR = 2 +SQ_INTERRUPT_WORD_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IBUF_ST' +SQ_IBUF_ST__enumvalues = { + 0: 'SQ_IBUF_IB_IDLE', + 1: 'SQ_IBUF_IB_INI_WAIT_GNT', + 2: 'SQ_IBUF_IB_INI_WAIT_DRET', + 3: 'SQ_IBUF_IB_LE_4DW', + 4: 'SQ_IBUF_IB_WAIT_DRET', + 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', + 6: 'SQ_IBUF_IB_DRET', + 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', +} +SQ_IBUF_IB_IDLE = 0 +SQ_IBUF_IB_INI_WAIT_GNT = 1 +SQ_IBUF_IB_INI_WAIT_DRET = 2 +SQ_IBUF_IB_LE_4DW = 3 +SQ_IBUF_IB_WAIT_DRET = 4 +SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 +SQ_IBUF_IB_DRET = 6 +SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 +SQ_IBUF_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INST_STR_ST' +SQ_INST_STR_ST__enumvalues = { + 0: 'SQ_INST_STR_IB_WAVE_NORML', + 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 4: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0', + 5: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', + 6: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', + 7: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', +} +SQ_INST_STR_IB_WAVE_NORML = 0 +SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 +SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 +SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 +SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 4 +SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 5 +SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 6 +SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 7 +SQ_INST_STR_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_IB_ECC_ST' +SQ_WAVE_IB_ECC_ST__enumvalues = { + 0: 'SQ_WAVE_IB_ECC_CLEAN', + 1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE', + 2: 'SQ_WAVE_IB_ECC_ERR_HALT', + 3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', +} +SQ_WAVE_IB_ECC_CLEAN = 0 +SQ_WAVE_IB_ECC_ERR_CONTINUE = 1 +SQ_WAVE_IB_ECC_ERR_HALT = 2 +SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3 +SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ADDRESS_MODE' +SH_MEM_ADDRESS_MODE__enumvalues = { + 0: 'SH_MEM_ADDRESS_MODE_64', + 1: 'SH_MEM_ADDRESS_MODE_32', +} +SH_MEM_ADDRESS_MODE_64 = 0 +SH_MEM_ADDRESS_MODE_32 = 1 +SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_RETRY_MODE' +SH_MEM_RETRY_MODE__enumvalues = { + 0: 'SH_MEM_RETRY_MODE_ALL', + 1: 'SH_MEM_RETRY_MODE_WRITEATOMIC', + 2: 'SH_MEM_RETRY_MODE_NONE', +} +SH_MEM_RETRY_MODE_ALL = 0 +SH_MEM_RETRY_MODE_WRITEATOMIC = 1 +SH_MEM_RETRY_MODE_NONE = 2 +SH_MEM_RETRY_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ALIGNMENT_MODE' +SH_MEM_ALIGNMENT_MODE__enumvalues = { + 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', + 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', + 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', +} +SH_MEM_ALIGNMENT_MODE_DWORD = 0 +SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 +SH_MEM_ALIGNMENT_MODE_STRICT = 2 +SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 +SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', + 1: 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', + 2: 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', + 3: 'SQ_TT_TOKEN_MASK_COMP_SHIFT', + 4: 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', + 5: 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', + 6: 'SQ_TT_TOKEN_MASK_OTHER_SHIFT', + 7: 'SQ_TT_TOKEN_MASK_READS_SHIFT', +} +SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0 +SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 1 +SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 2 +SQ_TT_TOKEN_MASK_COMP_SHIFT = 3 +SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 4 +SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 5 +SQ_TT_TOKEN_MASK_OTHER_SHIFT = 6 +SQ_TT_TOKEN_MASK_READS_SHIFT = 7 +SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE' +SQ_TT_TOKEN_MASK_REG_INCLUDE__enumvalues = { + 1: 'SQ_TT_TOKEN_MASK_SQDEC_BIT', + 2: 'SQ_TT_TOKEN_MASK_SHDEC_BIT', + 4: 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', + 8: 'SQ_TT_TOKEN_MASK_COMP_BIT', + 16: 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', + 32: 'SQ_TT_TOKEN_MASK_CONFIG_BIT', + 64: 'SQ_TT_TOKEN_MASK_OTHER_BIT', + 128: 'SQ_TT_TOKEN_MASK_READS_BIT', +} +SQ_TT_TOKEN_MASK_SQDEC_BIT = 1 +SQ_TT_TOKEN_MASK_SHDEC_BIT = 2 +SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 4 +SQ_TT_TOKEN_MASK_COMP_BIT = 8 +SQ_TT_TOKEN_MASK_CONTEXT_BIT = 16 +SQ_TT_TOKEN_MASK_CONFIG_BIT = 32 +SQ_TT_TOKEN_MASK_OTHER_BIT = 64 +SQ_TT_TOKEN_MASK_READS_BIT = 128 +SQ_TT_TOKEN_MASK_REG_INCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', + 1: 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', + 2: 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', + 3: 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', + 4: 'SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT', + 5: 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', + 6: 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', + 7: 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', + 8: 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', + 9: 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', + 10: 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', + 11: 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', +} +SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0 +SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 1 +SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 2 +SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 3 +SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT = 4 +SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 5 +SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 6 +SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 7 +SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 8 +SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 9 +SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 10 +SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 11 +SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE' +SQ_TT_TOKEN_MASK_INST_EXCLUDE__enumvalues = { + 0: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD', + 1: 'SQ_TT_INST_EXCLUDE_EXPGNT234', +} +SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD = 0 +SQ_TT_INST_EXCLUDE_EXPGNT234 = 1 +SQ_TT_TOKEN_MASK_INST_EXCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_MODE' +SQ_TT_MODE__enumvalues = { + 0: 'SQ_TT_MODE_OFF', + 1: 'SQ_TT_MODE_ON', + 2: 'SQ_TT_MODE_GLOBAL', + 3: 'SQ_TT_MODE_DETAIL', +} +SQ_TT_MODE_OFF = 0 +SQ_TT_MODE_ON = 1 +SQ_TT_MODE_GLOBAL = 2 +SQ_TT_MODE_DETAIL = 3 +SQ_TT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_WTYPE_INCLUDE_SHIFT' +SQ_TT_WTYPE_INCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', + 1: 'SQ_TT_WTYPE_INCLUDE_VS_SHIFT', + 2: 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', + 3: 'SQ_TT_WTYPE_INCLUDE_ES_SHIFT', + 4: 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', + 5: 'SQ_TT_WTYPE_INCLUDE_LS_SHIFT', + 6: 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', +} +SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0 +SQ_TT_WTYPE_INCLUDE_VS_SHIFT = 1 +SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 2 +SQ_TT_WTYPE_INCLUDE_ES_SHIFT = 3 +SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 4 +SQ_TT_WTYPE_INCLUDE_LS_SHIFT = 5 +SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 6 +SQ_TT_WTYPE_INCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_WTYPE_INCLUDE' +SQ_TT_WTYPE_INCLUDE__enumvalues = { + 1: 'SQ_TT_WTYPE_INCLUDE_PS_BIT', + 2: 'SQ_TT_WTYPE_INCLUDE_VS_BIT', + 4: 'SQ_TT_WTYPE_INCLUDE_GS_BIT', + 8: 'SQ_TT_WTYPE_INCLUDE_ES_BIT', + 16: 'SQ_TT_WTYPE_INCLUDE_HS_BIT', + 32: 'SQ_TT_WTYPE_INCLUDE_LS_BIT', + 64: 'SQ_TT_WTYPE_INCLUDE_CS_BIT', +} +SQ_TT_WTYPE_INCLUDE_PS_BIT = 1 +SQ_TT_WTYPE_INCLUDE_VS_BIT = 2 +SQ_TT_WTYPE_INCLUDE_GS_BIT = 4 +SQ_TT_WTYPE_INCLUDE_ES_BIT = 8 +SQ_TT_WTYPE_INCLUDE_HS_BIT = 16 +SQ_TT_WTYPE_INCLUDE_LS_BIT = 32 +SQ_TT_WTYPE_INCLUDE_CS_BIT = 64 +SQ_TT_WTYPE_INCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_UTIL_TIMER' +SQ_TT_UTIL_TIMER__enumvalues = { + 0: 'SQ_TT_UTIL_TIMER_100_CLK', + 1: 'SQ_TT_UTIL_TIMER_250_CLK', +} +SQ_TT_UTIL_TIMER_100_CLK = 0 +SQ_TT_UTIL_TIMER_250_CLK = 1 +SQ_TT_UTIL_TIMER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_WAVESTART_MODE' +SQ_TT_WAVESTART_MODE__enumvalues = { + 0: 'SQ_TT_WAVESTART_MODE_SHORT', + 1: 'SQ_TT_WAVESTART_MODE_ALLOC', + 2: 'SQ_TT_WAVESTART_MODE_PBB_ID', +} +SQ_TT_WAVESTART_MODE_SHORT = 0 +SQ_TT_WAVESTART_MODE_ALLOC = 1 +SQ_TT_WAVESTART_MODE_PBB_ID = 2 +SQ_TT_WAVESTART_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_RT_FREQ' +SQ_TT_RT_FREQ__enumvalues = { + 0: 'SQ_TT_RT_FREQ_NEVER', + 1: 'SQ_TT_RT_FREQ_1024_CLK', + 2: 'SQ_TT_RT_FREQ_4096_CLK', +} +SQ_TT_RT_FREQ_NEVER = 0 +SQ_TT_RT_FREQ_1024_CLK = 1 +SQ_TT_RT_FREQ_4096_CLK = 2 +SQ_TT_RT_FREQ = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WATCH_MODES' +SQ_WATCH_MODES__enumvalues = { + 0: 'SQ_WATCH_MODE_READ', + 1: 'SQ_WATCH_MODE_NONREAD', + 2: 'SQ_WATCH_MODE_ATOMIC', + 3: 'SQ_WATCH_MODE_ALL', +} +SQ_WATCH_MODE_READ = 0 +SQ_WATCH_MODE_NONREAD = 1 +SQ_WATCH_MODE_ATOMIC = 2 +SQ_WATCH_MODE_ALL = 3 +SQ_WATCH_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_SCHED_MODES' +SQ_WAVE_SCHED_MODES__enumvalues = { + 0: 'SQ_WAVE_SCHED_MODE_NORMAL', + 1: 'SQ_WAVE_SCHED_MODE_EXPERT', + 2: 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', +} +SQ_WAVE_SCHED_MODE_NORMAL = 0 +SQ_WAVE_SCHED_MODE_EXPERT = 1 +SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 2 +SQ_WAVE_SCHED_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'CSDATA_TYPE' +CSDATA_TYPE__enumvalues = { + 0: 'CSDATA_TYPE_TG', + 1: 'CSDATA_TYPE_STATE', + 2: 'CSDATA_TYPE_EVENT', + 3: 'CSDATA_TYPE_PRIVATE', +} +CSDATA_TYPE_TG = 0 +CSDATA_TYPE_STATE = 1 +CSDATA_TYPE_EVENT = 2 +CSDATA_TYPE_PRIVATE = 3 +CSDATA_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CSCNTL_TYPE' +CSCNTL_TYPE__enumvalues = { + 0: 'CSCNTL_TYPE_TG', + 1: 'CSCNTL_TYPE_STATE', + 2: 'CSCNTL_TYPE_EVENT', + 3: 'CSCNTL_TYPE_PRIVATE', +} +CSCNTL_TYPE_TG = 0 +CSCNTL_TYPE_STATE = 1 +CSCNTL_TYPE_EVENT = 2 +CSCNTL_TYPE_PRIVATE = 3 +CSCNTL_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUT_PRIM_TYPE' +VGT_OUT_PRIM_TYPE__enumvalues = { + 0: 'VGT_OUT_POINT', + 1: 'VGT_OUT_LINE', + 2: 'VGT_OUT_TRI', + 3: 'VGT_OUT_RECT_V0', + 4: 'VGT_OUT_RECT_V1', + 5: 'VGT_OUT_RECT_V2', + 6: 'VGT_OUT_RECT_V3', + 7: 'VGT_OUT_2D_RECT', + 8: 'VGT_TE_QUAD', + 9: 'VGT_TE_PRIM_INDEX_LINE', + 10: 'VGT_TE_PRIM_INDEX_TRI', + 11: 'VGT_TE_PRIM_INDEX_QUAD', + 12: 'VGT_OUT_LINE_ADJ', + 13: 'VGT_OUT_TRI_ADJ', + 14: 'VGT_OUT_PATCH', +} +VGT_OUT_POINT = 0 +VGT_OUT_LINE = 1 +VGT_OUT_TRI = 2 +VGT_OUT_RECT_V0 = 3 +VGT_OUT_RECT_V1 = 4 +VGT_OUT_RECT_V2 = 5 +VGT_OUT_RECT_V3 = 6 +VGT_OUT_2D_RECT = 7 +VGT_TE_QUAD = 8 +VGT_TE_PRIM_INDEX_LINE = 9 +VGT_TE_PRIM_INDEX_TRI = 10 +VGT_TE_PRIM_INDEX_QUAD = 11 +VGT_OUT_LINE_ADJ = 12 +VGT_OUT_TRI_ADJ = 13 +VGT_OUT_PATCH = 14 +VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_PRIM_TYPE' +VGT_DI_PRIM_TYPE__enumvalues = { + 0: 'DI_PT_NONE', + 1: 'DI_PT_POINTLIST', + 2: 'DI_PT_LINELIST', + 3: 'DI_PT_LINESTRIP', + 4: 'DI_PT_TRILIST', + 5: 'DI_PT_TRIFAN', + 6: 'DI_PT_TRISTRIP', + 7: 'DI_PT_2D_RECTANGLE', + 8: 'DI_PT_UNUSED_1', + 9: 'DI_PT_PATCH', + 10: 'DI_PT_LINELIST_ADJ', + 11: 'DI_PT_LINESTRIP_ADJ', + 12: 'DI_PT_TRILIST_ADJ', + 13: 'DI_PT_TRISTRIP_ADJ', + 14: 'DI_PT_UNUSED_3', + 15: 'DI_PT_UNUSED_4', + 16: 'DI_PT_TRI_WITH_WFLAGS', + 17: 'DI_PT_RECTLIST', + 18: 'DI_PT_LINELOOP', + 19: 'DI_PT_QUADLIST', + 20: 'DI_PT_QUADSTRIP', + 21: 'DI_PT_POLYGON', +} +DI_PT_NONE = 0 +DI_PT_POINTLIST = 1 +DI_PT_LINELIST = 2 +DI_PT_LINESTRIP = 3 +DI_PT_TRILIST = 4 +DI_PT_TRIFAN = 5 +DI_PT_TRISTRIP = 6 +DI_PT_2D_RECTANGLE = 7 +DI_PT_UNUSED_1 = 8 +DI_PT_PATCH = 9 +DI_PT_LINELIST_ADJ = 10 +DI_PT_LINESTRIP_ADJ = 11 +DI_PT_TRILIST_ADJ = 12 +DI_PT_TRISTRIP_ADJ = 13 +DI_PT_UNUSED_3 = 14 +DI_PT_UNUSED_4 = 15 +DI_PT_TRI_WITH_WFLAGS = 16 +DI_PT_RECTLIST = 17 +DI_PT_LINELOOP = 18 +DI_PT_QUADLIST = 19 +DI_PT_QUADSTRIP = 20 +DI_PT_POLYGON = 21 +VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_SOURCE_SELECT' +VGT_DI_SOURCE_SELECT__enumvalues = { + 0: 'DI_SRC_SEL_DMA', + 1: 'DI_SRC_SEL_IMMEDIATE', + 2: 'DI_SRC_SEL_AUTO_INDEX', + 3: 'DI_SRC_SEL_RESERVED', +} +DI_SRC_SEL_DMA = 0 +DI_SRC_SEL_IMMEDIATE = 1 +DI_SRC_SEL_AUTO_INDEX = 2 +DI_SRC_SEL_RESERVED = 3 +VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_MAJOR_MODE_SELECT' +VGT_DI_MAJOR_MODE_SELECT__enumvalues = { + 0: 'DI_MAJOR_MODE_0', + 1: 'DI_MAJOR_MODE_1', +} +DI_MAJOR_MODE_0 = 0 +DI_MAJOR_MODE_1 = 1 +VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_INDEX_SIZE' +VGT_DI_INDEX_SIZE__enumvalues = { + 0: 'DI_INDEX_SIZE_16_BIT', + 1: 'DI_INDEX_SIZE_32_BIT', + 2: 'DI_INDEX_SIZE_8_BIT', +} +DI_INDEX_SIZE_16_BIT = 0 +DI_INDEX_SIZE_32_BIT = 1 +DI_INDEX_SIZE_8_BIT = 2 +VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_EVENT_TYPE' +VGT_EVENT_TYPE__enumvalues = { + 0: 'Reserved_0x00', + 1: 'SAMPLE_STREAMOUTSTATS1', + 2: 'SAMPLE_STREAMOUTSTATS2', + 3: 'SAMPLE_STREAMOUTSTATS3', + 4: 'CACHE_FLUSH_TS', + 5: 'CONTEXT_DONE', + 6: 'CACHE_FLUSH', + 7: 'CS_PARTIAL_FLUSH', + 8: 'VGT_STREAMOUT_SYNC', + 9: 'SET_FE_ID', + 10: 'VGT_STREAMOUT_RESET', + 11: 'END_OF_PIPE_INCR_DE', + 12: 'END_OF_PIPE_IB_END', + 13: 'RST_PIX_CNT', + 14: 'BREAK_BATCH', + 15: 'VS_PARTIAL_FLUSH', + 16: 'PS_PARTIAL_FLUSH', + 17: 'FLUSH_HS_OUTPUT', + 18: 'FLUSH_DFSM', + 19: 'RESET_TO_LOWEST_VGT', + 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', + 21: 'ZPASS_DONE', + 22: 'CACHE_FLUSH_AND_INV_EVENT', + 23: 'PERFCOUNTER_START', + 24: 'PERFCOUNTER_STOP', + 25: 'PIPELINESTAT_START', + 26: 'PIPELINESTAT_STOP', + 27: 'PERFCOUNTER_SAMPLE', + 28: 'FLUSH_ES_OUTPUT', + 29: 'BIN_CONF_OVERRIDE_CHECK', + 30: 'SAMPLE_PIPELINESTAT', + 31: 'SO_VGTSTREAMOUT_FLUSH', + 32: 'SAMPLE_STREAMOUTSTATS', + 33: 'RESET_VTX_CNT', + 34: 'BLOCK_CONTEXT_DONE', + 35: 'CS_CONTEXT_DONE', + 36: 'VGT_FLUSH', + 37: 'TGID_ROLLOVER', + 38: 'SQ_NON_EVENT', + 39: 'SC_SEND_DB_VPZ', + 40: 'BOTTOM_OF_PIPE_TS', + 41: 'FLUSH_SX_TS', + 42: 'DB_CACHE_FLUSH_AND_INV', + 43: 'FLUSH_AND_INV_DB_DATA_TS', + 44: 'FLUSH_AND_INV_DB_META', + 45: 'FLUSH_AND_INV_CB_DATA_TS', + 46: 'FLUSH_AND_INV_CB_META', + 47: 'CS_DONE', + 48: 'PS_DONE', + 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', + 50: 'SX_CB_RAT_ACK_REQUEST', + 51: 'THREAD_TRACE_START', + 52: 'THREAD_TRACE_STOP', + 53: 'THREAD_TRACE_MARKER', + 54: 'THREAD_TRACE_DRAW', + 55: 'THREAD_TRACE_FINISH', + 56: 'PIXEL_PIPE_STAT_CONTROL', + 57: 'PIXEL_PIPE_STAT_DUMP', + 58: 'PIXEL_PIPE_STAT_RESET', + 59: 'CONTEXT_SUSPEND', + 60: 'OFFCHIP_HS_DEALLOC', + 61: 'ENABLE_NGG_PIPELINE', + 62: 'ENABLE_LEGACY_PIPELINE', + 63: 'DRAW_DONE', +} +Reserved_0x00 = 0 +SAMPLE_STREAMOUTSTATS1 = 1 +SAMPLE_STREAMOUTSTATS2 = 2 +SAMPLE_STREAMOUTSTATS3 = 3 +CACHE_FLUSH_TS = 4 +CONTEXT_DONE = 5 +CACHE_FLUSH = 6 +CS_PARTIAL_FLUSH = 7 +VGT_STREAMOUT_SYNC = 8 +SET_FE_ID = 9 +VGT_STREAMOUT_RESET = 10 +END_OF_PIPE_INCR_DE = 11 +END_OF_PIPE_IB_END = 12 +RST_PIX_CNT = 13 +BREAK_BATCH = 14 +VS_PARTIAL_FLUSH = 15 +PS_PARTIAL_FLUSH = 16 +FLUSH_HS_OUTPUT = 17 +FLUSH_DFSM = 18 +RESET_TO_LOWEST_VGT = 19 +CACHE_FLUSH_AND_INV_TS_EVENT = 20 +ZPASS_DONE = 21 +CACHE_FLUSH_AND_INV_EVENT = 22 +PERFCOUNTER_START = 23 +PERFCOUNTER_STOP = 24 +PIPELINESTAT_START = 25 +PIPELINESTAT_STOP = 26 +PERFCOUNTER_SAMPLE = 27 +FLUSH_ES_OUTPUT = 28 +BIN_CONF_OVERRIDE_CHECK = 29 +SAMPLE_PIPELINESTAT = 30 +SO_VGTSTREAMOUT_FLUSH = 31 +SAMPLE_STREAMOUTSTATS = 32 +RESET_VTX_CNT = 33 +BLOCK_CONTEXT_DONE = 34 +CS_CONTEXT_DONE = 35 +VGT_FLUSH = 36 +TGID_ROLLOVER = 37 +SQ_NON_EVENT = 38 +SC_SEND_DB_VPZ = 39 +BOTTOM_OF_PIPE_TS = 40 +FLUSH_SX_TS = 41 +DB_CACHE_FLUSH_AND_INV = 42 +FLUSH_AND_INV_DB_DATA_TS = 43 +FLUSH_AND_INV_DB_META = 44 +FLUSH_AND_INV_CB_DATA_TS = 45 +FLUSH_AND_INV_CB_META = 46 +CS_DONE = 47 +PS_DONE = 48 +FLUSH_AND_INV_CB_PIXEL_DATA = 49 +SX_CB_RAT_ACK_REQUEST = 50 +THREAD_TRACE_START = 51 +THREAD_TRACE_STOP = 52 +THREAD_TRACE_MARKER = 53 +THREAD_TRACE_DRAW = 54 +THREAD_TRACE_FINISH = 55 +PIXEL_PIPE_STAT_CONTROL = 56 +PIXEL_PIPE_STAT_DUMP = 57 +PIXEL_PIPE_STAT_RESET = 58 +CONTEXT_SUSPEND = 59 +OFFCHIP_HS_DEALLOC = 60 +ENABLE_NGG_PIPELINE = 61 +ENABLE_LEGACY_PIPELINE = 62 +DRAW_DONE = 63 +VGT_EVENT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_SWAP_MODE' +VGT_DMA_SWAP_MODE__enumvalues = { + 0: 'VGT_DMA_SWAP_NONE', + 1: 'VGT_DMA_SWAP_16_BIT', + 2: 'VGT_DMA_SWAP_32_BIT', + 3: 'VGT_DMA_SWAP_WORD', +} +VGT_DMA_SWAP_NONE = 0 +VGT_DMA_SWAP_16_BIT = 1 +VGT_DMA_SWAP_32_BIT = 2 +VGT_DMA_SWAP_WORD = 3 +VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_INDEX_TYPE_MODE' +VGT_INDEX_TYPE_MODE__enumvalues = { + 0: 'VGT_INDEX_16', + 1: 'VGT_INDEX_32', + 2: 'VGT_INDEX_8', +} +VGT_INDEX_16 = 0 +VGT_INDEX_32 = 1 +VGT_INDEX_8 = 2 +VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_BUF_TYPE' +VGT_DMA_BUF_TYPE__enumvalues = { + 0: 'VGT_DMA_BUF_MEM', + 1: 'VGT_DMA_BUF_RING', + 2: 'VGT_DMA_BUF_SETUP', + 3: 'VGT_DMA_PTR_UPDATE', +} +VGT_DMA_BUF_MEM = 0 +VGT_DMA_BUF_RING = 1 +VGT_DMA_BUF_SETUP = 2 +VGT_DMA_PTR_UPDATE = 3 +VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUTPATH_SELECT' +VGT_OUTPATH_SELECT__enumvalues = { + 0: 'VGT_OUTPATH_VTX_REUSE', + 1: 'VGT_OUTPATH_GS_BLOCK', + 2: 'VGT_OUTPATH_HS_BLOCK', + 3: 'VGT_OUTPATH_PRIM_GEN', + 4: 'VGT_OUTPATH_TE_PRIM_GEN', + 5: 'VGT_OUTPATH_TE_GS_BLOCK', + 6: 'VGT_OUTPATH_TE_OUTPUT', +} +VGT_OUTPATH_VTX_REUSE = 0 +VGT_OUTPATH_GS_BLOCK = 1 +VGT_OUTPATH_HS_BLOCK = 2 +VGT_OUTPATH_PRIM_GEN = 3 +VGT_OUTPATH_TE_PRIM_GEN = 4 +VGT_OUTPATH_TE_GS_BLOCK = 5 +VGT_OUTPATH_TE_OUTPUT = 6 +VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GRP_PRIM_TYPE' +VGT_GRP_PRIM_TYPE__enumvalues = { + 0: 'VGT_GRP_3D_POINT', + 1: 'VGT_GRP_3D_LINE', + 2: 'VGT_GRP_3D_TRI', + 3: 'VGT_GRP_3D_RECT', + 4: 'VGT_GRP_3D_QUAD', + 5: 'VGT_GRP_2D_COPY_RECT_V0', + 6: 'VGT_GRP_2D_COPY_RECT_V1', + 7: 'VGT_GRP_2D_COPY_RECT_V2', + 8: 'VGT_GRP_2D_COPY_RECT_V3', + 9: 'VGT_GRP_2D_FILL_RECT', + 10: 'VGT_GRP_2D_LINE', + 11: 'VGT_GRP_2D_TRI', + 12: 'VGT_GRP_PRIM_INDEX_LINE', + 13: 'VGT_GRP_PRIM_INDEX_TRI', + 14: 'VGT_GRP_PRIM_INDEX_QUAD', + 15: 'VGT_GRP_3D_LINE_ADJ', + 16: 'VGT_GRP_3D_TRI_ADJ', + 17: 'VGT_GRP_3D_PATCH', + 18: 'VGT_GRP_2D_RECT', +} +VGT_GRP_3D_POINT = 0 +VGT_GRP_3D_LINE = 1 +VGT_GRP_3D_TRI = 2 +VGT_GRP_3D_RECT = 3 +VGT_GRP_3D_QUAD = 4 +VGT_GRP_2D_COPY_RECT_V0 = 5 +VGT_GRP_2D_COPY_RECT_V1 = 6 +VGT_GRP_2D_COPY_RECT_V2 = 7 +VGT_GRP_2D_COPY_RECT_V3 = 8 +VGT_GRP_2D_FILL_RECT = 9 +VGT_GRP_2D_LINE = 10 +VGT_GRP_2D_TRI = 11 +VGT_GRP_PRIM_INDEX_LINE = 12 +VGT_GRP_PRIM_INDEX_TRI = 13 +VGT_GRP_PRIM_INDEX_QUAD = 14 +VGT_GRP_3D_LINE_ADJ = 15 +VGT_GRP_3D_TRI_ADJ = 16 +VGT_GRP_3D_PATCH = 17 +VGT_GRP_2D_RECT = 18 +VGT_GRP_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GRP_PRIM_ORDER' +VGT_GRP_PRIM_ORDER__enumvalues = { + 0: 'VGT_GRP_LIST', + 1: 'VGT_GRP_STRIP', + 2: 'VGT_GRP_FAN', + 3: 'VGT_GRP_LOOP', + 4: 'VGT_GRP_POLYGON', +} +VGT_GRP_LIST = 0 +VGT_GRP_STRIP = 1 +VGT_GRP_FAN = 2 +VGT_GRP_LOOP = 3 +VGT_GRP_POLYGON = 4 +VGT_GRP_PRIM_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GROUP_CONV_SEL' +VGT_GROUP_CONV_SEL__enumvalues = { + 0: 'VGT_GRP_INDEX_16', + 1: 'VGT_GRP_INDEX_32', + 2: 'VGT_GRP_UINT_16', + 3: 'VGT_GRP_UINT_32', + 4: 'VGT_GRP_SINT_16', + 5: 'VGT_GRP_SINT_32', + 6: 'VGT_GRP_FLOAT_32', + 7: 'VGT_GRP_AUTO_PRIM', + 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', +} +VGT_GRP_INDEX_16 = 0 +VGT_GRP_INDEX_32 = 1 +VGT_GRP_UINT_16 = 2 +VGT_GRP_UINT_32 = 3 +VGT_GRP_SINT_16 = 4 +VGT_GRP_SINT_32 = 5 +VGT_GRP_FLOAT_32 = 6 +VGT_GRP_AUTO_PRIM = 7 +VGT_GRP_FIX_1_23_TO_FLOAT = 8 +VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_MODE_TYPE' +VGT_GS_MODE_TYPE__enumvalues = { + 0: 'GS_OFF', + 1: 'GS_SCENARIO_A', + 2: 'GS_SCENARIO_B', + 3: 'GS_SCENARIO_G', + 4: 'GS_SCENARIO_C', + 5: 'SPRITE_EN', +} +GS_OFF = 0 +GS_SCENARIO_A = 1 +GS_SCENARIO_B = 2 +GS_SCENARIO_G = 3 +GS_SCENARIO_C = 4 +SPRITE_EN = 5 +VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_CUT_MODE' +VGT_GS_CUT_MODE__enumvalues = { + 0: 'GS_CUT_1024', + 1: 'GS_CUT_512', + 2: 'GS_CUT_256', + 3: 'GS_CUT_128', +} +GS_CUT_1024 = 0 +GS_CUT_512 = 1 +GS_CUT_256 = 2 +GS_CUT_128 = 3 +VGT_GS_CUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_OUTPRIM_TYPE' +VGT_GS_OUTPRIM_TYPE__enumvalues = { + 0: 'POINTLIST', + 1: 'LINESTRIP', + 2: 'TRISTRIP', + 3: 'RECTLIST', +} +POINTLIST = 0 +LINESTRIP = 1 +TRISTRIP = 2 +RECTLIST = 3 +VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_CACHE_INVALID_MODE' +VGT_CACHE_INVALID_MODE__enumvalues = { + 0: 'VC_ONLY', + 1: 'TC_ONLY', + 2: 'VC_AND_TC', +} +VC_ONLY = 0 +TC_ONLY = 1 +VC_AND_TC = 2 +VGT_CACHE_INVALID_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TYPE' +VGT_TESS_TYPE__enumvalues = { + 0: 'TESS_ISOLINE', + 1: 'TESS_TRIANGLE', + 2: 'TESS_QUAD', +} +TESS_ISOLINE = 0 +TESS_TRIANGLE = 1 +TESS_QUAD = 2 +VGT_TESS_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_PARTITION' +VGT_TESS_PARTITION__enumvalues = { + 0: 'PART_INTEGER', + 1: 'PART_POW2', + 2: 'PART_FRAC_ODD', + 3: 'PART_FRAC_EVEN', +} +PART_INTEGER = 0 +PART_POW2 = 1 +PART_FRAC_ODD = 2 +PART_FRAC_EVEN = 3 +VGT_TESS_PARTITION = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TOPOLOGY' +VGT_TESS_TOPOLOGY__enumvalues = { + 0: 'OUTPUT_POINT', + 1: 'OUTPUT_LINE', + 2: 'OUTPUT_TRIANGLE_CW', + 3: 'OUTPUT_TRIANGLE_CCW', +} +OUTPUT_POINT = 0 +OUTPUT_LINE = 1 +OUTPUT_TRIANGLE_CW = 2 +OUTPUT_TRIANGLE_CCW = 3 +VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_RDREQ_POLICY' +VGT_RDREQ_POLICY__enumvalues = { + 0: 'VGT_POLICY_LRU', + 1: 'VGT_POLICY_STREAM', + 2: 'VGT_POLICY_BYPASS', +} +VGT_POLICY_LRU = 0 +VGT_POLICY_STREAM = 1 +VGT_POLICY_BYPASS = 2 +VGT_RDREQ_POLICY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DIST_MODE' +VGT_DIST_MODE__enumvalues = { + 0: 'NO_DIST', + 1: 'PATCHES', + 2: 'DONUTS', + 3: 'TRAPEZOIDS', +} +NO_DIST = 0 +PATCHES = 1 +DONUTS = 2 +TRAPEZOIDS = 3 +VGT_DIST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DETECT_ONE' +VGT_DETECT_ONE__enumvalues = { + 0: 'PRE_CLAMP_TF1', + 1: 'POST_CLAMP_TF1', + 2: 'DISABLE_TF1', +} +PRE_CLAMP_TF1 = 0 +POST_CLAMP_TF1 = 1 +DISABLE_TF1 = 2 +VGT_DETECT_ONE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DETECT_ZERO' +VGT_DETECT_ZERO__enumvalues = { + 0: 'PRE_CLAMP_TF0', + 1: 'POST_CLAMP_TF0', + 2: 'DISABLE_TF0', +} +PRE_CLAMP_TF0 = 0 +POST_CLAMP_TF0 = 1 +DISABLE_TF0 = 2 +VGT_DETECT_ZERO = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_LS_EN' +VGT_STAGES_LS_EN__enumvalues = { + 0: 'LS_STAGE_OFF', + 1: 'LS_STAGE_ON', + 2: 'CS_STAGE_ON', + 3: 'RESERVED_LS', +} +LS_STAGE_OFF = 0 +LS_STAGE_ON = 1 +CS_STAGE_ON = 2 +RESERVED_LS = 3 +VGT_STAGES_LS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_HS_EN' +VGT_STAGES_HS_EN__enumvalues = { + 0: 'HS_STAGE_OFF', + 1: 'HS_STAGE_ON', +} +HS_STAGE_OFF = 0 +HS_STAGE_ON = 1 +VGT_STAGES_HS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_ES_EN' +VGT_STAGES_ES_EN__enumvalues = { + 0: 'ES_STAGE_OFF', + 1: 'ES_STAGE_DS', + 2: 'ES_STAGE_REAL', + 3: 'RESERVED_ES', +} +ES_STAGE_OFF = 0 +ES_STAGE_DS = 1 +ES_STAGE_REAL = 2 +RESERVED_ES = 3 +VGT_STAGES_ES_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_GS_EN' +VGT_STAGES_GS_EN__enumvalues = { + 0: 'GS_STAGE_OFF', + 1: 'GS_STAGE_ON', +} +GS_STAGE_OFF = 0 +GS_STAGE_ON = 1 +VGT_STAGES_GS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_VS_EN' +VGT_STAGES_VS_EN__enumvalues = { + 0: 'VS_STAGE_REAL', + 1: 'VS_STAGE_DS', + 2: 'VS_STAGE_COPY_SHADER', + 3: 'RESERVED_VS', +} +VS_STAGE_REAL = 0 +VS_STAGE_DS = 1 +VS_STAGE_COPY_SHADER = 2 +RESERVED_VS = 3 +VGT_STAGES_VS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'GE_PERFCOUNT_SELECT' +GE_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge_assembler_busy', + 1: 'ge_assembler_stalled', + 2: 'ge_cm_reading_stalled', + 3: 'ge_cm_stalled_by_gog', + 4: 'ge_cm_stalled_by_gsfetch_done', + 5: 'ge_dma_busy', + 6: 'ge_dma_lat_bin_0', + 7: 'ge_dma_lat_bin_1', + 8: 'ge_dma_lat_bin_2', + 9: 'ge_dma_lat_bin_3', + 10: 'ge_dma_lat_bin_4', + 11: 'ge_dma_lat_bin_5', + 12: 'ge_dma_lat_bin_6', + 13: 'ge_dma_lat_bin_7', + 14: 'ge_dma_return', + 15: 'ge_dma_utcl1_consecutive_retry_event', + 16: 'ge_dma_utcl1_request_event', + 17: 'ge_dma_utcl1_retry_event', + 18: 'ge_dma_utcl1_stall_event', + 19: 'ge_dma_utcl1_stall_utcl2_event', + 20: 'ge_dma_utcl1_translation_hit_event', + 21: 'ge_dma_utcl1_translation_miss_event', + 22: 'ge_dma_utcl2_stall_on_trans', + 23: 'ge_dma_utcl2_trans_ack', + 24: 'ge_dma_utcl2_trans_xnack', + 25: 'ge_ds_cache_hits', + 26: 'ge_ds_prims', + 27: 'ge_es_done', + 28: 'ge_es_done_latency', + 29: 'ge_es_flush', + 30: 'ge_es_ring_high_water_mark', + 31: 'ge_es_thread_groups', + 32: 'ge_esthread_stalled_es_rb_full', + 33: 'ge_esthread_stalled_spi_bp', + 34: 'ge_esvert_stalled_es_tbl', + 35: 'ge_esvert_stalled_gs_event', + 36: 'ge_esvert_stalled_gs_tbl', + 37: 'ge_esvert_stalled_gsprim', + 38: 'ge_gea_dma_starved', + 39: 'ge_gog_busy', + 40: 'ge_gog_out_indx_stalled', + 41: 'ge_gog_out_prim_stalled', + 42: 'ge_gog_vs_tbl_stalled', + 43: 'ge_gs_cache_hits', + 44: 'ge_gs_counters_avail_stalled', + 45: 'ge_gs_done', + 46: 'ge_gs_done_latency', + 47: 'ge_gs_event_stall', + 48: 'ge_gs_issue_rtr_stalled', + 49: 'ge_gs_rb_space_avail_stalled', + 50: 'ge_gs_ring_high_water_mark', + 51: 'ge_gsprim_stalled_es_tbl', + 52: 'ge_gsprim_stalled_esvert', + 53: 'ge_gsprim_stalled_gs_event', + 54: 'ge_gsprim_stalled_gs_tbl', + 55: 'ge_gsthread_stalled', + 56: 'ge_hs_done', + 57: 'ge_hs_done_latency', + 58: 'ge_hs_done_se0', + 59: 'ge_hs_done_se1', + 60: 'ge_hs_done_se2_reserved', + 61: 'ge_hs_done_se3_reserved', + 62: 'ge_hs_tfm_stall', + 63: 'ge_hs_tgs_active_high_water_mark', + 64: 'ge_hs_thread_groups', + 65: 'ge_inside_tf_bin_0', + 66: 'ge_inside_tf_bin_1', + 67: 'ge_inside_tf_bin_2', + 68: 'ge_inside_tf_bin_3', + 69: 'ge_inside_tf_bin_4', + 70: 'ge_inside_tf_bin_5', + 71: 'ge_inside_tf_bin_6', + 72: 'ge_inside_tf_bin_7', + 73: 'ge_inside_tf_bin_8', + 74: 'ge_ls_done', + 75: 'ge_ls_done_latency', + 76: 'ge_null_patch', + 77: 'ge_pa_clipp_eop', + 78: 'ge_pa_clipp_is_event', + 79: 'ge_pa_clipp_new_vtx_vect', + 80: 'ge_pa_clipp_null_prim', + 81: 'ge_pa_clipp_send', + 82: 'ge_pa_clipp_send_not_event', + 83: 'ge_pa_clipp_stalled', + 84: 'ge_pa_clipp_starved_busy', + 85: 'ge_pa_clipp_starved_idle', + 86: 'ge_pa_clipp_valid_prim', + 87: 'ge_pa_clips_send', + 88: 'ge_pa_clips_stalled', + 89: 'ge_pa_clipv_send', + 90: 'ge_pa_clipv_stalled', + 91: 'ge_rbiu_di_fifo_stalled', + 92: 'ge_rbiu_di_fifo_starved', + 93: 'ge_rbiu_dr_fifo_stalled', + 94: 'ge_rbiu_dr_fifo_starved', + 95: 'ge_reused_es_indices', + 96: 'ge_reused_vs_indices', + 97: 'ge_sclk_core_vld', + 98: 'ge_sclk_gs_vld', + 99: 'ge_sclk_input_vld', + 100: 'ge_sclk_leg_gs_arb_vld', + 101: 'ge_sclk_ngg_vld', + 102: 'ge_sclk_reg_vld', + 103: 'ge_sclk_te11_vld', + 104: 'ge_sclk_vr_vld', + 105: 'ge_sclk_wd_te11_vld', + 106: 'ge_spi_esvert_eov', + 107: 'ge_spi_esvert_stalled', + 108: 'ge_spi_esvert_starved_busy', + 109: 'ge_spi_esvert_valid', + 110: 'ge_spi_eswave_is_event', + 111: 'ge_spi_eswave_send', + 112: 'ge_spi_gsprim_cont', + 113: 'ge_spi_gsprim_eov', + 114: 'ge_spi_gsprim_stalled', + 115: 'ge_spi_gsprim_starved_busy', + 116: 'ge_spi_gsprim_starved_idle', + 117: 'ge_spi_gsprim_valid', + 118: 'ge_spi_gssubgrp_is_event', + 119: 'ge_spi_gssubgrp_send', + 120: 'ge_spi_gswave_is_event', + 121: 'ge_spi_gswave_send', + 122: 'ge_spi_hsvert_eov', + 123: 'ge_spi_hsvert_stalled', + 124: 'ge_spi_hsvert_starved_busy', + 125: 'ge_spi_hsvert_valid', + 126: 'ge_spi_hswave_is_event', + 127: 'ge_spi_hswave_send', + 128: 'ge_spi_lsvert_eov', + 129: 'ge_spi_lsvert_stalled', + 130: 'ge_spi_lsvert_starved_busy', + 131: 'ge_spi_lsvert_starved_idle', + 132: 'ge_spi_lsvert_valid', + 133: 'ge_spi_lswave_is_event', + 134: 'ge_spi_lswave_send', + 135: 'ge_spi_vsvert_eov', + 136: 'ge_spi_vsvert_send', + 137: 'ge_spi_vsvert_stalled', + 138: 'ge_spi_vsvert_starved_busy', + 139: 'ge_spi_vsvert_starved_idle', + 140: 'ge_spi_vswave_is_event', + 141: 'ge_spi_vswave_send', + 142: 'ge_starved_on_hs_done', + 143: 'ge_stat_busy', + 144: 'ge_stat_combined_busy', + 145: 'ge_stat_no_dma_busy', + 146: 'ge_strmout_stalled', + 147: 'ge_te11_busy', + 148: 'ge_te11_starved', + 149: 'ge_tfreq_lat_bin_0', + 150: 'ge_tfreq_lat_bin_1', + 151: 'ge_tfreq_lat_bin_2', + 152: 'ge_tfreq_lat_bin_3', + 153: 'ge_tfreq_lat_bin_4', + 154: 'ge_tfreq_lat_bin_5', + 155: 'ge_tfreq_lat_bin_6', + 156: 'ge_tfreq_lat_bin_7', + 157: 'ge_tfreq_utcl1_consecutive_retry_event', + 158: 'ge_tfreq_utcl1_request_event', + 159: 'ge_tfreq_utcl1_retry_event', + 160: 'ge_tfreq_utcl1_stall_event', + 161: 'ge_tfreq_utcl1_stall_utcl2_event', + 162: 'ge_tfreq_utcl1_translation_hit_event', + 163: 'ge_tfreq_utcl1_translation_miss_event', + 164: 'ge_tfreq_utcl2_stall_on_trans', + 165: 'ge_tfreq_utcl2_trans_ack', + 166: 'ge_tfreq_utcl2_trans_xnack', + 167: 'ge_vs_cache_hits', + 168: 'ge_vs_done', + 169: 'ge_vs_pc_stall', + 170: 'ge_vs_table_high_water_mark', + 171: 'ge_vs_thread_groups', + 172: 'ge_vsvert_api_send', + 173: 'ge_vsvert_ds_send', + 174: 'ge_wait_for_es_done_stalled', + 175: 'ge_waveid_stalled', +} +ge_assembler_busy = 0 +ge_assembler_stalled = 1 +ge_cm_reading_stalled = 2 +ge_cm_stalled_by_gog = 3 +ge_cm_stalled_by_gsfetch_done = 4 +ge_dma_busy = 5 +ge_dma_lat_bin_0 = 6 +ge_dma_lat_bin_1 = 7 +ge_dma_lat_bin_2 = 8 +ge_dma_lat_bin_3 = 9 +ge_dma_lat_bin_4 = 10 +ge_dma_lat_bin_5 = 11 +ge_dma_lat_bin_6 = 12 +ge_dma_lat_bin_7 = 13 +ge_dma_return = 14 +ge_dma_utcl1_consecutive_retry_event = 15 +ge_dma_utcl1_request_event = 16 +ge_dma_utcl1_retry_event = 17 +ge_dma_utcl1_stall_event = 18 +ge_dma_utcl1_stall_utcl2_event = 19 +ge_dma_utcl1_translation_hit_event = 20 +ge_dma_utcl1_translation_miss_event = 21 +ge_dma_utcl2_stall_on_trans = 22 +ge_dma_utcl2_trans_ack = 23 +ge_dma_utcl2_trans_xnack = 24 +ge_ds_cache_hits = 25 +ge_ds_prims = 26 +ge_es_done = 27 +ge_es_done_latency = 28 +ge_es_flush = 29 +ge_es_ring_high_water_mark = 30 +ge_es_thread_groups = 31 +ge_esthread_stalled_es_rb_full = 32 +ge_esthread_stalled_spi_bp = 33 +ge_esvert_stalled_es_tbl = 34 +ge_esvert_stalled_gs_event = 35 +ge_esvert_stalled_gs_tbl = 36 +ge_esvert_stalled_gsprim = 37 +ge_gea_dma_starved = 38 +ge_gog_busy = 39 +ge_gog_out_indx_stalled = 40 +ge_gog_out_prim_stalled = 41 +ge_gog_vs_tbl_stalled = 42 +ge_gs_cache_hits = 43 +ge_gs_counters_avail_stalled = 44 +ge_gs_done = 45 +ge_gs_done_latency = 46 +ge_gs_event_stall = 47 +ge_gs_issue_rtr_stalled = 48 +ge_gs_rb_space_avail_stalled = 49 +ge_gs_ring_high_water_mark = 50 +ge_gsprim_stalled_es_tbl = 51 +ge_gsprim_stalled_esvert = 52 +ge_gsprim_stalled_gs_event = 53 +ge_gsprim_stalled_gs_tbl = 54 +ge_gsthread_stalled = 55 +ge_hs_done = 56 +ge_hs_done_latency = 57 +ge_hs_done_se0 = 58 +ge_hs_done_se1 = 59 +ge_hs_done_se2_reserved = 60 +ge_hs_done_se3_reserved = 61 +ge_hs_tfm_stall = 62 +ge_hs_tgs_active_high_water_mark = 63 +ge_hs_thread_groups = 64 +ge_inside_tf_bin_0 = 65 +ge_inside_tf_bin_1 = 66 +ge_inside_tf_bin_2 = 67 +ge_inside_tf_bin_3 = 68 +ge_inside_tf_bin_4 = 69 +ge_inside_tf_bin_5 = 70 +ge_inside_tf_bin_6 = 71 +ge_inside_tf_bin_7 = 72 +ge_inside_tf_bin_8 = 73 +ge_ls_done = 74 +ge_ls_done_latency = 75 +ge_null_patch = 76 +ge_pa_clipp_eop = 77 +ge_pa_clipp_is_event = 78 +ge_pa_clipp_new_vtx_vect = 79 +ge_pa_clipp_null_prim = 80 +ge_pa_clipp_send = 81 +ge_pa_clipp_send_not_event = 82 +ge_pa_clipp_stalled = 83 +ge_pa_clipp_starved_busy = 84 +ge_pa_clipp_starved_idle = 85 +ge_pa_clipp_valid_prim = 86 +ge_pa_clips_send = 87 +ge_pa_clips_stalled = 88 +ge_pa_clipv_send = 89 +ge_pa_clipv_stalled = 90 +ge_rbiu_di_fifo_stalled = 91 +ge_rbiu_di_fifo_starved = 92 +ge_rbiu_dr_fifo_stalled = 93 +ge_rbiu_dr_fifo_starved = 94 +ge_reused_es_indices = 95 +ge_reused_vs_indices = 96 +ge_sclk_core_vld = 97 +ge_sclk_gs_vld = 98 +ge_sclk_input_vld = 99 +ge_sclk_leg_gs_arb_vld = 100 +ge_sclk_ngg_vld = 101 +ge_sclk_reg_vld = 102 +ge_sclk_te11_vld = 103 +ge_sclk_vr_vld = 104 +ge_sclk_wd_te11_vld = 105 +ge_spi_esvert_eov = 106 +ge_spi_esvert_stalled = 107 +ge_spi_esvert_starved_busy = 108 +ge_spi_esvert_valid = 109 +ge_spi_eswave_is_event = 110 +ge_spi_eswave_send = 111 +ge_spi_gsprim_cont = 112 +ge_spi_gsprim_eov = 113 +ge_spi_gsprim_stalled = 114 +ge_spi_gsprim_starved_busy = 115 +ge_spi_gsprim_starved_idle = 116 +ge_spi_gsprim_valid = 117 +ge_spi_gssubgrp_is_event = 118 +ge_spi_gssubgrp_send = 119 +ge_spi_gswave_is_event = 120 +ge_spi_gswave_send = 121 +ge_spi_hsvert_eov = 122 +ge_spi_hsvert_stalled = 123 +ge_spi_hsvert_starved_busy = 124 +ge_spi_hsvert_valid = 125 +ge_spi_hswave_is_event = 126 +ge_spi_hswave_send = 127 +ge_spi_lsvert_eov = 128 +ge_spi_lsvert_stalled = 129 +ge_spi_lsvert_starved_busy = 130 +ge_spi_lsvert_starved_idle = 131 +ge_spi_lsvert_valid = 132 +ge_spi_lswave_is_event = 133 +ge_spi_lswave_send = 134 +ge_spi_vsvert_eov = 135 +ge_spi_vsvert_send = 136 +ge_spi_vsvert_stalled = 137 +ge_spi_vsvert_starved_busy = 138 +ge_spi_vsvert_starved_idle = 139 +ge_spi_vswave_is_event = 140 +ge_spi_vswave_send = 141 +ge_starved_on_hs_done = 142 +ge_stat_busy = 143 +ge_stat_combined_busy = 144 +ge_stat_no_dma_busy = 145 +ge_strmout_stalled = 146 +ge_te11_busy = 147 +ge_te11_starved = 148 +ge_tfreq_lat_bin_0 = 149 +ge_tfreq_lat_bin_1 = 150 +ge_tfreq_lat_bin_2 = 151 +ge_tfreq_lat_bin_3 = 152 +ge_tfreq_lat_bin_4 = 153 +ge_tfreq_lat_bin_5 = 154 +ge_tfreq_lat_bin_6 = 155 +ge_tfreq_lat_bin_7 = 156 +ge_tfreq_utcl1_consecutive_retry_event = 157 +ge_tfreq_utcl1_request_event = 158 +ge_tfreq_utcl1_retry_event = 159 +ge_tfreq_utcl1_stall_event = 160 +ge_tfreq_utcl1_stall_utcl2_event = 161 +ge_tfreq_utcl1_translation_hit_event = 162 +ge_tfreq_utcl1_translation_miss_event = 163 +ge_tfreq_utcl2_stall_on_trans = 164 +ge_tfreq_utcl2_trans_ack = 165 +ge_tfreq_utcl2_trans_xnack = 166 +ge_vs_cache_hits = 167 +ge_vs_done = 168 +ge_vs_pc_stall = 169 +ge_vs_table_high_water_mark = 170 +ge_vs_thread_groups = 171 +ge_vsvert_api_send = 172 +ge_vsvert_ds_send = 173 +ge_wait_for_es_done_stalled = 174 +ge_waveid_stalled = 175 +GE_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_TYPE' +WD_IA_DRAW_TYPE__enumvalues = { + 0: 'WD_IA_DRAW_TYPE_DI_MM0', + 1: 'WD_IA_DRAW_TYPE_REG_XFER', + 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', + 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 4: 'WD_IA_DRAW_TYPE_MIN_INDX', + 5: 'WD_IA_DRAW_TYPE_MAX_INDX', + 6: 'WD_IA_DRAW_TYPE_INDX_OFF', + 7: 'WD_IA_DRAW_TYPE_IMM_DATA', +} +WD_IA_DRAW_TYPE_DI_MM0 = 0 +WD_IA_DRAW_TYPE_REG_XFER = 1 +WD_IA_DRAW_TYPE_EVENT_INIT = 2 +WD_IA_DRAW_TYPE_EVENT_ADDR = 3 +WD_IA_DRAW_TYPE_MIN_INDX = 4 +WD_IA_DRAW_TYPE_MAX_INDX = 5 +WD_IA_DRAW_TYPE_INDX_OFF = 6 +WD_IA_DRAW_TYPE_IMM_DATA = 7 +WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_REG_XFER' +WD_IA_DRAW_REG_XFER__enumvalues = { + 0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', + 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', + 2: 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', + 3: 'WD_IA_DRAW_REG_XFER_GE_CNTL', +} +WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0 +WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 +WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 2 +WD_IA_DRAW_REG_XFER_GE_CNTL = 3 +WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_SOURCE' +WD_IA_DRAW_SOURCE__enumvalues = { + 0: 'WD_IA_DRAW_SOURCE_DMA', + 1: 'WD_IA_DRAW_SOURCE_IMMD', + 2: 'WD_IA_DRAW_SOURCE_AUTO', + 3: 'WD_IA_DRAW_SOURCE_OPAQ', +} +WD_IA_DRAW_SOURCE_DMA = 0 +WD_IA_DRAW_SOURCE_IMMD = 1 +WD_IA_DRAW_SOURCE_AUTO = 2 +WD_IA_DRAW_SOURCE_OPAQ = 3 +WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'GB_EDC_DED_MODE' +GB_EDC_DED_MODE__enumvalues = { + 0: 'GB_EDC_DED_MODE_LOG', + 1: 'GB_EDC_DED_MODE_HALT', + 2: 'GB_EDC_DED_MODE_INT_HALT', +} +GB_EDC_DED_MODE_LOG = 0 +GB_EDC_DED_MODE_HALT = 1 +GB_EDC_DED_MODE_INT_HALT = 2 +GB_EDC_DED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CHA_PERF_SEL' +CHA_PERF_SEL__enumvalues = { + 0: 'CHA_PERF_SEL_BUSY', + 1: 'CHA_PERF_SEL_STALL_CHC0', + 2: 'CHA_PERF_SEL_STALL_CHC1', + 3: 'CHA_PERF_SEL_STALL_CHC2', + 4: 'CHA_PERF_SEL_STALL_CHC3', + 5: 'CHA_PERF_SEL_STALL_CHC4', + 6: 'CHA_PERF_SEL_REQUEST_CHC0', + 7: 'CHA_PERF_SEL_REQUEST_CHC1', + 8: 'CHA_PERF_SEL_REQUEST_CHC2', + 9: 'CHA_PERF_SEL_REQUEST_CHC3', + 10: 'CHA_PERF_SEL_REQUEST_CHC4', + 11: 'CHA_PERF_SEL_REQUEST_CHC5', + 12: 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', + 13: 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', + 14: 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', + 15: 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', + 16: 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', + 17: 'CHA_PERF_SEL_IO_32B_WDS_CHC0', + 18: 'CHA_PERF_SEL_IO_32B_WDS_CHC1', + 19: 'CHA_PERF_SEL_IO_32B_WDS_CHC2', + 20: 'CHA_PERF_SEL_IO_32B_WDS_CHC3', + 21: 'CHA_PERF_SEL_IO_32B_WDS_CHC4', + 22: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', + 23: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', + 24: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', + 25: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', + 26: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', + 27: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', + 28: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', + 29: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', + 30: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', + 31: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', + 32: 'CHA_PERF_SEL_ARB_REQUESTS', + 33: 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', + 34: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', + 35: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', + 36: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', + 37: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', + 38: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', + 39: 'CHA_PERF_SEL_CYCLE', +} +CHA_PERF_SEL_BUSY = 0 +CHA_PERF_SEL_STALL_CHC0 = 1 +CHA_PERF_SEL_STALL_CHC1 = 2 +CHA_PERF_SEL_STALL_CHC2 = 3 +CHA_PERF_SEL_STALL_CHC3 = 4 +CHA_PERF_SEL_STALL_CHC4 = 5 +CHA_PERF_SEL_REQUEST_CHC0 = 6 +CHA_PERF_SEL_REQUEST_CHC1 = 7 +CHA_PERF_SEL_REQUEST_CHC2 = 8 +CHA_PERF_SEL_REQUEST_CHC3 = 9 +CHA_PERF_SEL_REQUEST_CHC4 = 10 +CHA_PERF_SEL_REQUEST_CHC5 = 11 +CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 12 +CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 13 +CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 14 +CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 15 +CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 16 +CHA_PERF_SEL_IO_32B_WDS_CHC0 = 17 +CHA_PERF_SEL_IO_32B_WDS_CHC1 = 18 +CHA_PERF_SEL_IO_32B_WDS_CHC2 = 19 +CHA_PERF_SEL_IO_32B_WDS_CHC3 = 20 +CHA_PERF_SEL_IO_32B_WDS_CHC4 = 21 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 22 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 23 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 24 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 25 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 26 +CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 27 +CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 28 +CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 29 +CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 30 +CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 31 +CHA_PERF_SEL_ARB_REQUESTS = 32 +CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 33 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 34 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 35 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 36 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 37 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 38 +CHA_PERF_SEL_CYCLE = 39 +CHA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CHC_PERF_SEL' +CHC_PERF_SEL__enumvalues = { + 0: 'CHC_PERF_SEL_GATE_EN1', + 1: 'CHC_PERF_SEL_GATE_EN2', + 2: 'CHC_PERF_SEL_CORE_REG_SCLK_VLD', + 3: 'CHC_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES', + 4: 'CHC_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES', + 5: 'CHC_PERF_SEL_CYCLE', + 6: 'CHC_PERF_SEL_REQ', +} +CHC_PERF_SEL_GATE_EN1 = 0 +CHC_PERF_SEL_GATE_EN2 = 1 +CHC_PERF_SEL_CORE_REG_SCLK_VLD = 2 +CHC_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES = 3 +CHC_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES = 4 +CHC_PERF_SEL_CYCLE = 5 +CHC_PERF_SEL_REQ = 6 +CHC_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CHCG_PERF_SEL' +CHCG_PERF_SEL__enumvalues = { + 0: 'CHCG_PERF_SEL_GATE_EN1', + 1: 'CHCG_PERF_SEL_GATE_EN2', + 2: 'CHCG_PERF_SEL_CORE_REG_SCLK_VLD', + 3: 'CHCG_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES', + 4: 'CHCG_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES', + 5: 'CHCG_PERF_SEL_CYCLE', + 6: 'CHCG_PERF_SEL_REQ', +} +CHCG_PERF_SEL_GATE_EN1 = 0 +CHCG_PERF_SEL_GATE_EN2 = 1 +CHCG_PERF_SEL_CORE_REG_SCLK_VLD = 2 +CHCG_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES = 3 +CHCG_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES = 4 +CHCG_PERF_SEL_CYCLE = 5 +CHCG_PERF_SEL_REQ = 6 +CHCG_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1A_PERF_SEL' +GL1A_PERF_SEL__enumvalues = { + 0: 'GL1A_PERF_SEL_BUSY', + 1: 'GL1A_PERF_SEL_STALL_GL1C0', + 2: 'GL1A_PERF_SEL_STALL_GL1C1', + 3: 'GL1A_PERF_SEL_STALL_GL1C2', + 4: 'GL1A_PERF_SEL_STALL_GL1C3', + 5: 'GL1A_PERF_SEL_STALL_GL1C4', + 6: 'GL1A_PERF_SEL_REQUEST_GL1C0', + 7: 'GL1A_PERF_SEL_REQUEST_GL1C1', + 8: 'GL1A_PERF_SEL_REQUEST_GL1C2', + 9: 'GL1A_PERF_SEL_REQUEST_GL1C3', + 10: 'GL1A_PERF_SEL_REQUEST_GL1C4', + 11: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C0', + 12: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C1', + 13: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C2', + 14: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C3', + 15: 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C4', + 16: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C0', + 17: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C1', + 18: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C2', + 19: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C3', + 20: 'GL1A_PERF_SEL_IO_32B_WDS_GL1C4', + 21: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0', + 22: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1', + 23: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2', + 24: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3', + 25: 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4', + 26: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0', + 27: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1', + 28: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2', + 29: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3', + 30: 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4', + 31: 'GL1A_PERF_SEL_ARB_REQUESTS', + 32: 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', + 33: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', + 34: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', + 35: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', + 36: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', + 37: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4', + 38: 'GL1A_PERF_SEL_CYCLE', +} +GL1A_PERF_SEL_BUSY = 0 +GL1A_PERF_SEL_STALL_GL1C0 = 1 +GL1A_PERF_SEL_STALL_GL1C1 = 2 +GL1A_PERF_SEL_STALL_GL1C2 = 3 +GL1A_PERF_SEL_STALL_GL1C3 = 4 +GL1A_PERF_SEL_STALL_GL1C4 = 5 +GL1A_PERF_SEL_REQUEST_GL1C0 = 6 +GL1A_PERF_SEL_REQUEST_GL1C1 = 7 +GL1A_PERF_SEL_REQUEST_GL1C2 = 8 +GL1A_PERF_SEL_REQUEST_GL1C3 = 9 +GL1A_PERF_SEL_REQUEST_GL1C4 = 10 +GL1A_PERF_SEL_MEM_32B_WDS_GL1C0 = 11 +GL1A_PERF_SEL_MEM_32B_WDS_GL1C1 = 12 +GL1A_PERF_SEL_MEM_32B_WDS_GL1C2 = 13 +GL1A_PERF_SEL_MEM_32B_WDS_GL1C3 = 14 +GL1A_PERF_SEL_MEM_32B_WDS_GL1C4 = 15 +GL1A_PERF_SEL_IO_32B_WDS_GL1C0 = 16 +GL1A_PERF_SEL_IO_32B_WDS_GL1C1 = 17 +GL1A_PERF_SEL_IO_32B_WDS_GL1C2 = 18 +GL1A_PERF_SEL_IO_32B_WDS_GL1C3 = 19 +GL1A_PERF_SEL_IO_32B_WDS_GL1C4 = 20 +GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0 = 21 +GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1 = 22 +GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2 = 23 +GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3 = 24 +GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4 = 25 +GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0 = 26 +GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1 = 27 +GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2 = 28 +GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3 = 29 +GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4 = 30 +GL1A_PERF_SEL_ARB_REQUESTS = 31 +GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 32 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 33 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 34 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 35 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 36 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4 = 37 +GL1A_PERF_SEL_CYCLE = 38 +GL1A_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1C_PERF_SEL' +GL1C_PERF_SEL__enumvalues = { + 0: 'GL1C_PERF_SEL_GATE_EN1', + 1: 'GL1C_PERF_SEL_GATE_EN2', + 2: 'GL1C_PERF_SEL_CORE_REG_SCLK_VLD', + 3: 'GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES', + 4: 'GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES', + 5: 'GL1C_PERF_SEL_CYCLE', + 6: 'GL1C_PERF_SEL_REQ', +} +GL1C_PERF_SEL_GATE_EN1 = 0 +GL1C_PERF_SEL_GATE_EN2 = 1 +GL1C_PERF_SEL_CORE_REG_SCLK_VLD = 2 +GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES = 3 +GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES = 4 +GL1C_PERF_SEL_CYCLE = 5 +GL1C_PERF_SEL_REQ = 6 +GL1C_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1CG_PERF_SEL' +GL1CG_PERF_SEL__enumvalues = { + 0: 'GL1CG_PERF_SEL_GATE_EN1', + 1: 'GL1CG_PERF_SEL_GATE_EN2', + 2: 'GL1CG_PERF_SEL_CORE_REG_SCLK_VLD', + 3: 'GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES', + 4: 'GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES', + 5: 'GL1CG_PERF_SEL_CYCLE', + 6: 'GL1CG_PERF_SEL_REQ', +} +GL1CG_PERF_SEL_GATE_EN1 = 0 +GL1CG_PERF_SEL_GATE_EN2 = 1 +GL1CG_PERF_SEL_CORE_REG_SCLK_VLD = 2 +GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES = 3 +GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES = 4 +GL1CG_PERF_SEL_CYCLE = 5 +GL1CG_PERF_SEL_REQ = 6 +GL1CG_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TA_TC_REQ_MODES' +TA_TC_REQ_MODES__enumvalues = { + 0: 'TA_TC_REQ_MODE_BORDER', + 1: 'TA_TC_REQ_MODE_TEX2', + 2: 'TA_TC_REQ_MODE_TEX1', + 3: 'TA_TC_REQ_MODE_TEX0', + 4: 'TA_TC_REQ_MODE_NORMAL', + 5: 'TA_TC_REQ_MODE_DWORD', + 6: 'TA_TC_REQ_MODE_BYTE', + 7: 'TA_TC_REQ_MODE_BYTE_NV', +} +TA_TC_REQ_MODE_BORDER = 0 +TA_TC_REQ_MODE_TEX2 = 1 +TA_TC_REQ_MODE_TEX1 = 2 +TA_TC_REQ_MODE_TEX0 = 3 +TA_TC_REQ_MODE_NORMAL = 4 +TA_TC_REQ_MODE_DWORD = 5 +TA_TC_REQ_MODE_BYTE = 6 +TA_TC_REQ_MODE_BYTE_NV = 7 +TA_TC_REQ_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TA_TC_ADDR_MODES' +TA_TC_ADDR_MODES__enumvalues = { + 0: 'TA_TC_ADDR_MODE_DEFAULT', + 1: 'TA_TC_ADDR_MODE_COMP0', + 2: 'TA_TC_ADDR_MODE_COMP1', + 3: 'TA_TC_ADDR_MODE_COMP2', + 4: 'TA_TC_ADDR_MODE_COMP3', + 5: 'TA_TC_ADDR_MODE_UNALIGNED', + 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', +} +TA_TC_ADDR_MODE_DEFAULT = 0 +TA_TC_ADDR_MODE_COMP0 = 1 +TA_TC_ADDR_MODE_COMP1 = 2 +TA_TC_ADDR_MODE_COMP2 = 3 +TA_TC_ADDR_MODE_COMP3 = 4 +TA_TC_ADDR_MODE_UNALIGNED = 5 +TA_TC_ADDR_MODE_BORDER_COLOR = 6 +TA_TC_ADDR_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TA_PERFCOUNT_SEL' +TA_PERFCOUNT_SEL__enumvalues = { + 0: 'TA_PERF_SEL_NULL', + 1: 'TA_PERF_SEL_sh_fifo_busy', + 2: 'TA_PERF_SEL_sh_fifo_cmd_busy', + 3: 'TA_PERF_SEL_sh_fifo_addr_busy', + 4: 'TA_PERF_SEL_sh_fifo_data_busy', + 5: 'TA_PERF_SEL_sh_fifo_data_sfifo_busy', + 6: 'TA_PERF_SEL_sh_fifo_data_tfifo_busy', + 7: 'TA_PERF_SEL_gradient_busy', + 8: 'TA_PERF_SEL_gradient_fifo_busy', + 9: 'TA_PERF_SEL_lod_busy', + 10: 'TA_PERF_SEL_lod_fifo_busy', + 11: 'TA_PERF_SEL_addresser_busy', + 12: 'TA_PERF_SEL_addresser_fifo_busy', + 13: 'TA_PERF_SEL_aligner_busy', + 14: 'TA_PERF_SEL_write_path_busy', + 15: 'TA_PERF_SEL_ta_busy', + 16: 'TA_PERF_SEL_sq_ta_cmd_cycles', + 17: 'TA_PERF_SEL_sp_ta_addr_cycles', + 18: 'TA_PERF_SEL_sp_ta_data_cycles', + 19: 'TA_PERF_SEL_ta_fa_data_state_cycles', + 20: 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles', + 21: 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles', + 22: 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles', + 23: 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles', + 24: 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles', + 25: 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles', + 26: 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles', + 27: 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles', + 28: 'TA_PERF_SEL_ta_sh_fifo_starved', + 29: 'TA_PERF_SEL_RESERVED_29', + 30: 'TA_PERF_SEL_sh_fifo_addr_cycles', + 31: 'TA_PERF_SEL_sh_fifo_data_cycles', + 32: 'TA_PERF_SEL_total_wavefronts', + 33: 'TA_PERF_SEL_gradient_cycles', + 34: 'TA_PERF_SEL_walker_cycles', + 35: 'TA_PERF_SEL_aligner_cycles', + 36: 'TA_PERF_SEL_image_wavefronts', + 37: 'TA_PERF_SEL_image_read_wavefronts', + 38: 'TA_PERF_SEL_image_write_wavefronts', + 39: 'TA_PERF_SEL_image_atomic_wavefronts', + 40: 'TA_PERF_SEL_image_total_cycles', + 41: 'TA_PERF_SEL_RESERVED_41', + 42: 'TA_PERF_SEL_RESERVED_42', + 43: 'TA_PERF_SEL_RESERVED_43', + 44: 'TA_PERF_SEL_buffer_wavefronts', + 45: 'TA_PERF_SEL_buffer_read_wavefronts', + 46: 'TA_PERF_SEL_buffer_write_wavefronts', + 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', + 48: 'TA_PERF_SEL_buffer_coalescable_wavefronts', + 49: 'TA_PERF_SEL_buffer_total_cycles', + 50: 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles', + 51: 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles', + 52: 'TA_PERF_SEL_buffer_coalesced_read_cycles', + 53: 'TA_PERF_SEL_buffer_coalesced_write_cycles', + 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 56: 'TA_PERF_SEL_data_stalled_by_tc_cycles', + 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 58: 'TA_PERF_SEL_addresser_stalled_cycles', + 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 60: 'TA_PERF_SEL_aniso_stalled_cycles', + 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 62: 'TA_PERF_SEL_deriv_stalled_cycles', + 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 64: 'TA_PERF_SEL_color_1_cycle_pixels', + 65: 'TA_PERF_SEL_color_2_cycle_pixels', + 66: 'TA_PERF_SEL_color_3_cycle_pixels', + 67: 'TA_PERF_SEL_color_4_cycle_pixels', + 68: 'TA_PERF_SEL_mip_1_cycle_pixels', + 69: 'TA_PERF_SEL_mip_2_cycle_pixels', + 70: 'TA_PERF_SEL_vol_1_cycle_pixels', + 71: 'TA_PERF_SEL_vol_2_cycle_pixels', + 72: 'TA_PERF_SEL_bilin_point_1_cycle_pixels', + 73: 'TA_PERF_SEL_mipmap_lod_0_samples', + 74: 'TA_PERF_SEL_mipmap_lod_1_samples', + 75: 'TA_PERF_SEL_mipmap_lod_2_samples', + 76: 'TA_PERF_SEL_mipmap_lod_3_samples', + 77: 'TA_PERF_SEL_mipmap_lod_4_samples', + 78: 'TA_PERF_SEL_mipmap_lod_5_samples', + 79: 'TA_PERF_SEL_mipmap_lod_6_samples', + 80: 'TA_PERF_SEL_mipmap_lod_7_samples', + 81: 'TA_PERF_SEL_mipmap_lod_8_samples', + 82: 'TA_PERF_SEL_mipmap_lod_9_samples', + 83: 'TA_PERF_SEL_mipmap_lod_10_samples', + 84: 'TA_PERF_SEL_mipmap_lod_11_samples', + 85: 'TA_PERF_SEL_mipmap_lod_12_samples', + 86: 'TA_PERF_SEL_mipmap_lod_13_samples', + 87: 'TA_PERF_SEL_mipmap_lod_14_samples', + 88: 'TA_PERF_SEL_mipmap_invalid_samples', + 89: 'TA_PERF_SEL_aniso_1_cycle_quads', + 90: 'TA_PERF_SEL_aniso_2_cycle_quads', + 91: 'TA_PERF_SEL_aniso_4_cycle_quads', + 92: 'TA_PERF_SEL_aniso_6_cycle_quads', + 93: 'TA_PERF_SEL_aniso_8_cycle_quads', + 94: 'TA_PERF_SEL_aniso_10_cycle_quads', + 95: 'TA_PERF_SEL_aniso_12_cycle_quads', + 96: 'TA_PERF_SEL_aniso_14_cycle_quads', + 97: 'TA_PERF_SEL_aniso_16_cycle_quads', + 98: 'TA_PERF_SEL_write_path_input_cycles', + 99: 'TA_PERF_SEL_write_path_output_cycles', + 100: 'TA_PERF_SEL_flat_wavefronts', + 101: 'TA_PERF_SEL_flat_read_wavefronts', + 102: 'TA_PERF_SEL_flat_write_wavefronts', + 103: 'TA_PERF_SEL_flat_atomic_wavefronts', + 104: 'TA_PERF_SEL_flat_coalesceable_wavefronts', + 105: 'TA_PERF_SEL_reg_sclk_vld', + 106: 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en', + 107: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en', + 108: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en', + 109: 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en', + 110: 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', + 111: 'TA_PERF_SEL_xnack_on_phase0', + 112: 'TA_PERF_SEL_xnack_on_phase1', + 113: 'TA_PERF_SEL_xnack_on_phase2', + 114: 'TA_PERF_SEL_xnack_on_phase3', + 115: 'TA_PERF_SEL_first_xnack_on_phase0', + 116: 'TA_PERF_SEL_first_xnack_on_phase1', + 117: 'TA_PERF_SEL_first_xnack_on_phase2', + 118: 'TA_PERF_SEL_first_xnack_on_phase3', +} +TA_PERF_SEL_NULL = 0 +TA_PERF_SEL_sh_fifo_busy = 1 +TA_PERF_SEL_sh_fifo_cmd_busy = 2 +TA_PERF_SEL_sh_fifo_addr_busy = 3 +TA_PERF_SEL_sh_fifo_data_busy = 4 +TA_PERF_SEL_sh_fifo_data_sfifo_busy = 5 +TA_PERF_SEL_sh_fifo_data_tfifo_busy = 6 +TA_PERF_SEL_gradient_busy = 7 +TA_PERF_SEL_gradient_fifo_busy = 8 +TA_PERF_SEL_lod_busy = 9 +TA_PERF_SEL_lod_fifo_busy = 10 +TA_PERF_SEL_addresser_busy = 11 +TA_PERF_SEL_addresser_fifo_busy = 12 +TA_PERF_SEL_aligner_busy = 13 +TA_PERF_SEL_write_path_busy = 14 +TA_PERF_SEL_ta_busy = 15 +TA_PERF_SEL_sq_ta_cmd_cycles = 16 +TA_PERF_SEL_sp_ta_addr_cycles = 17 +TA_PERF_SEL_sp_ta_data_cycles = 18 +TA_PERF_SEL_ta_fa_data_state_cycles = 19 +TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 20 +TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 21 +TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 22 +TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 23 +TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 24 +TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 25 +TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 26 +TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 27 +TA_PERF_SEL_ta_sh_fifo_starved = 28 +TA_PERF_SEL_RESERVED_29 = 29 +TA_PERF_SEL_sh_fifo_addr_cycles = 30 +TA_PERF_SEL_sh_fifo_data_cycles = 31 +TA_PERF_SEL_total_wavefronts = 32 +TA_PERF_SEL_gradient_cycles = 33 +TA_PERF_SEL_walker_cycles = 34 +TA_PERF_SEL_aligner_cycles = 35 +TA_PERF_SEL_image_wavefronts = 36 +TA_PERF_SEL_image_read_wavefronts = 37 +TA_PERF_SEL_image_write_wavefronts = 38 +TA_PERF_SEL_image_atomic_wavefronts = 39 +TA_PERF_SEL_image_total_cycles = 40 +TA_PERF_SEL_RESERVED_41 = 41 +TA_PERF_SEL_RESERVED_42 = 42 +TA_PERF_SEL_RESERVED_43 = 43 +TA_PERF_SEL_buffer_wavefronts = 44 +TA_PERF_SEL_buffer_read_wavefronts = 45 +TA_PERF_SEL_buffer_write_wavefronts = 46 +TA_PERF_SEL_buffer_atomic_wavefronts = 47 +TA_PERF_SEL_buffer_coalescable_wavefronts = 48 +TA_PERF_SEL_buffer_total_cycles = 49 +TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 50 +TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 51 +TA_PERF_SEL_buffer_coalesced_read_cycles = 52 +TA_PERF_SEL_buffer_coalesced_write_cycles = 53 +TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 +TA_PERF_SEL_addr_stalled_by_td_cycles = 55 +TA_PERF_SEL_data_stalled_by_tc_cycles = 56 +TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 +TA_PERF_SEL_addresser_stalled_cycles = 58 +TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 +TA_PERF_SEL_aniso_stalled_cycles = 60 +TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 +TA_PERF_SEL_deriv_stalled_cycles = 62 +TA_PERF_SEL_aniso_gt1_cycle_quads = 63 +TA_PERF_SEL_color_1_cycle_pixels = 64 +TA_PERF_SEL_color_2_cycle_pixels = 65 +TA_PERF_SEL_color_3_cycle_pixels = 66 +TA_PERF_SEL_color_4_cycle_pixels = 67 +TA_PERF_SEL_mip_1_cycle_pixels = 68 +TA_PERF_SEL_mip_2_cycle_pixels = 69 +TA_PERF_SEL_vol_1_cycle_pixels = 70 +TA_PERF_SEL_vol_2_cycle_pixels = 71 +TA_PERF_SEL_bilin_point_1_cycle_pixels = 72 +TA_PERF_SEL_mipmap_lod_0_samples = 73 +TA_PERF_SEL_mipmap_lod_1_samples = 74 +TA_PERF_SEL_mipmap_lod_2_samples = 75 +TA_PERF_SEL_mipmap_lod_3_samples = 76 +TA_PERF_SEL_mipmap_lod_4_samples = 77 +TA_PERF_SEL_mipmap_lod_5_samples = 78 +TA_PERF_SEL_mipmap_lod_6_samples = 79 +TA_PERF_SEL_mipmap_lod_7_samples = 80 +TA_PERF_SEL_mipmap_lod_8_samples = 81 +TA_PERF_SEL_mipmap_lod_9_samples = 82 +TA_PERF_SEL_mipmap_lod_10_samples = 83 +TA_PERF_SEL_mipmap_lod_11_samples = 84 +TA_PERF_SEL_mipmap_lod_12_samples = 85 +TA_PERF_SEL_mipmap_lod_13_samples = 86 +TA_PERF_SEL_mipmap_lod_14_samples = 87 +TA_PERF_SEL_mipmap_invalid_samples = 88 +TA_PERF_SEL_aniso_1_cycle_quads = 89 +TA_PERF_SEL_aniso_2_cycle_quads = 90 +TA_PERF_SEL_aniso_4_cycle_quads = 91 +TA_PERF_SEL_aniso_6_cycle_quads = 92 +TA_PERF_SEL_aniso_8_cycle_quads = 93 +TA_PERF_SEL_aniso_10_cycle_quads = 94 +TA_PERF_SEL_aniso_12_cycle_quads = 95 +TA_PERF_SEL_aniso_14_cycle_quads = 96 +TA_PERF_SEL_aniso_16_cycle_quads = 97 +TA_PERF_SEL_write_path_input_cycles = 98 +TA_PERF_SEL_write_path_output_cycles = 99 +TA_PERF_SEL_flat_wavefronts = 100 +TA_PERF_SEL_flat_read_wavefronts = 101 +TA_PERF_SEL_flat_write_wavefronts = 102 +TA_PERF_SEL_flat_atomic_wavefronts = 103 +TA_PERF_SEL_flat_coalesceable_wavefronts = 104 +TA_PERF_SEL_reg_sclk_vld = 105 +TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 106 +TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 107 +TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 108 +TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 109 +TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 110 +TA_PERF_SEL_xnack_on_phase0 = 111 +TA_PERF_SEL_xnack_on_phase1 = 112 +TA_PERF_SEL_xnack_on_phase2 = 113 +TA_PERF_SEL_xnack_on_phase3 = 114 +TA_PERF_SEL_first_xnack_on_phase0 = 115 +TA_PERF_SEL_first_xnack_on_phase1 = 116 +TA_PERF_SEL_first_xnack_on_phase2 = 117 +TA_PERF_SEL_first_xnack_on_phase3 = 118 +TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TD_PERFCOUNT_SEL' +TD_PERFCOUNT_SEL__enumvalues = { + 0: 'TD_PERF_SEL_none', + 1: 'TD_PERF_SEL_td_busy', + 2: 'TD_PERF_SEL_input_busy', + 3: 'TD_PERF_SEL_sampler_lerp_busy', + 4: 'TD_PERF_SEL_sampler_out_busy', + 5: 'TD_PERF_SEL_nofilter_busy', + 6: 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', + 7: 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', + 8: 'TD_PERF_SEL_RESERVED_8', + 9: 'TD_PERF_SEL_core_state_rams_read', + 10: 'TD_PERF_SEL_weight_data_rams_read', + 11: 'TD_PERF_SEL_reference_data_rams_read', + 12: 'TD_PERF_SEL_tc_td_data_fifo_full', + 13: 'TD_PERF_SEL_tc_td_ram_fifo_full', + 14: 'TD_PERF_SEL_input_state_fifo_full', + 15: 'TD_PERF_SEL_ta_data_stall', + 16: 'TD_PERF_SEL_tc_data_stall', + 17: 'TD_PERF_SEL_tc_ram_stall', + 18: 'TD_PERF_SEL_lds_stall', + 19: 'TD_PERF_SEL_sampler_pkr_full', + 20: 'TD_PERF_SEL_nofilter_pkr_full', + 21: 'TD_PERF_SEL_RESERVED_21', + 22: 'TD_PERF_SEL_gather4_wavefront', + 23: 'TD_PERF_SEL_gather4h_wavefront', + 24: 'TD_PERF_SEL_gather4h_packed_wavefront', + 25: 'TD_PERF_SEL_gather8h_packed_wavefront', + 26: 'TD_PERF_SEL_sample_c_wavefront', + 27: 'TD_PERF_SEL_load_wavefront', + 28: 'TD_PERF_SEL_store_wavefront', + 29: 'TD_PERF_SEL_ldfptr_wavefront', + 30: 'TD_PERF_SEL_write_ack_wavefront', + 31: 'TD_PERF_SEL_d16_en_wavefront', + 32: 'TD_PERF_SEL_bypassLerp_wavefront', + 33: 'TD_PERF_SEL_min_max_filter_wavefront', + 34: 'TD_PERF_SEL_one_comp_wavefront', + 35: 'TD_PERF_SEL_two_comp_wavefront', + 36: 'TD_PERF_SEL_three_comp_wavefront', + 37: 'TD_PERF_SEL_four_comp_wavefront', + 38: 'TD_PERF_SEL_user_defined_border', + 39: 'TD_PERF_SEL_white_border', + 40: 'TD_PERF_SEL_opaque_black_border', + 41: 'TD_PERF_SEL_lod_warn_from_ta', + 42: 'TD_PERF_SEL_wavefront_dest_is_lds', + 43: 'TD_PERF_SEL_td_cycling_of_nofilter_instr', + 44: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr', + 45: 'TD_PERF_SEL_out_of_order_instr', + 46: 'TD_PERF_SEL_total_num_instr', + 47: 'TD_PERF_SEL_mixmode_instruction', + 48: 'TD_PERF_SEL_mixmode_resource', + 49: 'TD_PERF_SEL_status_packet', + 50: 'TD_PERF_SEL_address_cmd_poison', + 51: 'TD_PERF_SEL_data_poison', + 52: 'TD_PERF_SEL_done_scoreboard_not_empty', + 53: 'TD_PERF_SEL_done_scoreboard_is_full', + 54: 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', + 55: 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', + 56: 'TD_PERF_SEL_nofilter_formatters_turned_off', + 57: 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', + 58: 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', +} +TD_PERF_SEL_none = 0 +TD_PERF_SEL_td_busy = 1 +TD_PERF_SEL_input_busy = 2 +TD_PERF_SEL_sampler_lerp_busy = 3 +TD_PERF_SEL_sampler_out_busy = 4 +TD_PERF_SEL_nofilter_busy = 5 +TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 6 +TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 7 +TD_PERF_SEL_RESERVED_8 = 8 +TD_PERF_SEL_core_state_rams_read = 9 +TD_PERF_SEL_weight_data_rams_read = 10 +TD_PERF_SEL_reference_data_rams_read = 11 +TD_PERF_SEL_tc_td_data_fifo_full = 12 +TD_PERF_SEL_tc_td_ram_fifo_full = 13 +TD_PERF_SEL_input_state_fifo_full = 14 +TD_PERF_SEL_ta_data_stall = 15 +TD_PERF_SEL_tc_data_stall = 16 +TD_PERF_SEL_tc_ram_stall = 17 +TD_PERF_SEL_lds_stall = 18 +TD_PERF_SEL_sampler_pkr_full = 19 +TD_PERF_SEL_nofilter_pkr_full = 20 +TD_PERF_SEL_RESERVED_21 = 21 +TD_PERF_SEL_gather4_wavefront = 22 +TD_PERF_SEL_gather4h_wavefront = 23 +TD_PERF_SEL_gather4h_packed_wavefront = 24 +TD_PERF_SEL_gather8h_packed_wavefront = 25 +TD_PERF_SEL_sample_c_wavefront = 26 +TD_PERF_SEL_load_wavefront = 27 +TD_PERF_SEL_store_wavefront = 28 +TD_PERF_SEL_ldfptr_wavefront = 29 +TD_PERF_SEL_write_ack_wavefront = 30 +TD_PERF_SEL_d16_en_wavefront = 31 +TD_PERF_SEL_bypassLerp_wavefront = 32 +TD_PERF_SEL_min_max_filter_wavefront = 33 +TD_PERF_SEL_one_comp_wavefront = 34 +TD_PERF_SEL_two_comp_wavefront = 35 +TD_PERF_SEL_three_comp_wavefront = 36 +TD_PERF_SEL_four_comp_wavefront = 37 +TD_PERF_SEL_user_defined_border = 38 +TD_PERF_SEL_white_border = 39 +TD_PERF_SEL_opaque_black_border = 40 +TD_PERF_SEL_lod_warn_from_ta = 41 +TD_PERF_SEL_wavefront_dest_is_lds = 42 +TD_PERF_SEL_td_cycling_of_nofilter_instr = 43 +TD_PERF_SEL_tc_cycling_of_nofilter_instr = 44 +TD_PERF_SEL_out_of_order_instr = 45 +TD_PERF_SEL_total_num_instr = 46 +TD_PERF_SEL_mixmode_instruction = 47 +TD_PERF_SEL_mixmode_resource = 48 +TD_PERF_SEL_status_packet = 49 +TD_PERF_SEL_address_cmd_poison = 50 +TD_PERF_SEL_data_poison = 51 +TD_PERF_SEL_done_scoreboard_not_empty = 52 +TD_PERF_SEL_done_scoreboard_is_full = 53 +TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 54 +TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 55 +TD_PERF_SEL_nofilter_formatters_turned_off = 56 +TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 57 +TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 58 +TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_PERFCOUNT_SELECT' +TCP_PERFCOUNT_SELECT__enumvalues = { + 0: 'TCP_PERF_SEL_GATE_EN1', + 1: 'TCP_PERF_SEL_GATE_EN2', + 2: 'TCP_PERF_SEL_CORE_REG_SCLK_VLD', + 3: 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES', + 4: 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES', + 5: 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES', + 6: 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES', + 7: 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', + 8: 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES', + 9: 'TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES', + 10: 'TCP_PERF_SEL_LOD_STALL_CYCLES', + 11: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES', + 12: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', + 13: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES', + 14: 'TCP_PERF_SEL_ALLOC_STALL_CYCLES', + 15: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', + 16: 'TCP_PERF_SEL_LFIFO_STALL_CYCLES', + 17: 'TCP_PERF_SEL_RFIFO_STALL_CYCLES', + 18: 'TCP_PERF_SEL_TCR_RDRET_STALL', + 19: 'TCP_PERF_SEL_WRITE_CONFLICT_STALL', + 20: 'TCP_PERF_SEL_HOLE_READ_STALL', + 21: 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES', + 22: 'TCP_PERF_SEL_PENDING_STALL_CYCLES', + 23: 'TCP_PERF_SEL_READFIFO_STALL_CYCLES', + 24: 'TCP_PERF_SEL_POWER_STALL', + 25: 'TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL', + 26: 'TCP_PERF_SEL_TC_TA_XNACK_STALL', + 27: 'TCP_PERF_SEL_TA_TCP_STATE_READ', + 28: 'TCP_PERF_SEL_TOTAL_ACCESSES', + 29: 'TCP_PERF_SEL_TOTAL_READ', + 30: 'TCP_PERF_SEL_TOTAL_NON_READ', + 31: 'TCP_PERF_SEL_TOTAL_WRITE', + 32: 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ', + 33: 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ', + 34: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ', + 35: 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE', + 36: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE', + 37: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET', + 38: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET', + 39: 'TCP_PERF_SEL_TOTAL_WBINVL1', + 40: 'TCP_PERF_SEL_CP_TCP_INVALIDATE', + 41: 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES', + 42: 'TCP_PERF_SEL_SHOOTDOWN', + 43: 'TCP_PERF_SEL_UTCL0_REQUEST', + 44: 'TCP_PERF_SEL_UTCL0_TRANSLATION_MISS', + 45: 'TCP_PERF_SEL_UTCL0_TRANSLATION_HIT', + 46: 'TCP_PERF_SEL_UTCL0_PERMISSION_MISS', + 47: 'TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 48: 'TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 49: 'TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS', + 50: 'TCP_PERF_SEL_UTCL0_LFIFO_FULL', + 51: 'TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 52: 'TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 53: 'TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT', + 54: 'TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT', + 55: 'TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 56: 'TCP_PERF_SEL_TOTAL_CACHE_ACCESSES', + 57: 'TCP_PERF_SEL_TAGRAM0_REQ', + 58: 'TCP_PERF_SEL_TAGRAM1_REQ', + 59: 'TCP_PERF_SEL_TAGRAM2_REQ', + 60: 'TCP_PERF_SEL_TAGRAM3_REQ', + 61: 'TCP_PERF_SEL_TCP_LATENCY', + 62: 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY', + 63: 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', + 64: 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY', + 65: 'TCP_PERF_SEL_TCC_READ_REQ', + 66: 'TCP_PERF_SEL_TCC_WRITE_REQ', + 67: 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ', + 68: 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ', + 69: 'TCP_PERF_SEL_TCC_LRU_REQ', + 70: 'TCP_PERF_SEL_TCC_STREAM_REQ', + 71: 'TCP_PERF_SEL_TCC_NC_READ_REQ', + 72: 'TCP_PERF_SEL_TCC_NC_WRITE_REQ', + 73: 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ', + 74: 'TCP_PERF_SEL_TCC_UC_READ_REQ', + 75: 'TCP_PERF_SEL_TCC_UC_WRITE_REQ', + 76: 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ', + 77: 'TCP_PERF_SEL_TCC_CC_READ_REQ', + 78: 'TCP_PERF_SEL_TCC_CC_WRITE_REQ', + 79: 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', + 80: 'TCP_PERF_SEL_TCC_DCC_REQ', + 81: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', + 82: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', + 83: 'TCP_PERF_SEL_GL1_REQ_READ', + 84: 'TCP_PERF_SEL_GL1_REQ_READ_LATENCY', + 85: 'TCP_PERF_SEL_GL1_REQ_WRITE', + 86: 'TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY', + 87: 'TCP_PERF_SEL_REQ_MISS_TAGRAM0', + 88: 'TCP_PERF_SEL_REQ_MISS_TAGRAM1', + 89: 'TCP_PERF_SEL_REQ_MISS_TAGRAM2', + 90: 'TCP_PERF_SEL_REQ_MISS_TAGRAM3', + 91: 'TCP_PERF_SEL_TA_REQ', + 92: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', + 93: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', + 94: 'TCP_PERF_SEL_TA_REQ_READ', + 95: 'TCP_PERF_SEL_TA_REQ_WRITE', + 96: 'TCP_PERF_SEL_TA_REQ_STATE_READ', +} +TCP_PERF_SEL_GATE_EN1 = 0 +TCP_PERF_SEL_GATE_EN2 = 1 +TCP_PERF_SEL_CORE_REG_SCLK_VLD = 2 +TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 3 +TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 4 +TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 5 +TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 6 +TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 7 +TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 8 +TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES = 9 +TCP_PERF_SEL_LOD_STALL_CYCLES = 10 +TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 11 +TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 12 +TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 13 +TCP_PERF_SEL_ALLOC_STALL_CYCLES = 14 +TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 15 +TCP_PERF_SEL_LFIFO_STALL_CYCLES = 16 +TCP_PERF_SEL_RFIFO_STALL_CYCLES = 17 +TCP_PERF_SEL_TCR_RDRET_STALL = 18 +TCP_PERF_SEL_WRITE_CONFLICT_STALL = 19 +TCP_PERF_SEL_HOLE_READ_STALL = 20 +TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 21 +TCP_PERF_SEL_PENDING_STALL_CYCLES = 22 +TCP_PERF_SEL_READFIFO_STALL_CYCLES = 23 +TCP_PERF_SEL_POWER_STALL = 24 +TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL = 25 +TCP_PERF_SEL_TC_TA_XNACK_STALL = 26 +TCP_PERF_SEL_TA_TCP_STATE_READ = 27 +TCP_PERF_SEL_TOTAL_ACCESSES = 28 +TCP_PERF_SEL_TOTAL_READ = 29 +TCP_PERF_SEL_TOTAL_NON_READ = 30 +TCP_PERF_SEL_TOTAL_WRITE = 31 +TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 32 +TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 33 +TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 34 +TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 35 +TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 36 +TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 37 +TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 38 +TCP_PERF_SEL_TOTAL_WBINVL1 = 39 +TCP_PERF_SEL_CP_TCP_INVALIDATE = 40 +TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 41 +TCP_PERF_SEL_SHOOTDOWN = 42 +TCP_PERF_SEL_UTCL0_REQUEST = 43 +TCP_PERF_SEL_UTCL0_TRANSLATION_MISS = 44 +TCP_PERF_SEL_UTCL0_TRANSLATION_HIT = 45 +TCP_PERF_SEL_UTCL0_PERMISSION_MISS = 46 +TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 47 +TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 48 +TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS = 49 +TCP_PERF_SEL_UTCL0_LFIFO_FULL = 50 +TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 51 +TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS = 52 +TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 53 +TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT = 54 +TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 55 +TCP_PERF_SEL_TOTAL_CACHE_ACCESSES = 56 +TCP_PERF_SEL_TAGRAM0_REQ = 57 +TCP_PERF_SEL_TAGRAM1_REQ = 58 +TCP_PERF_SEL_TAGRAM2_REQ = 59 +TCP_PERF_SEL_TAGRAM3_REQ = 60 +TCP_PERF_SEL_TCP_LATENCY = 61 +TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 62 +TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 63 +TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 64 +TCP_PERF_SEL_TCC_READ_REQ = 65 +TCP_PERF_SEL_TCC_WRITE_REQ = 66 +TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 67 +TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 68 +TCP_PERF_SEL_TCC_LRU_REQ = 69 +TCP_PERF_SEL_TCC_STREAM_REQ = 70 +TCP_PERF_SEL_TCC_NC_READ_REQ = 71 +TCP_PERF_SEL_TCC_NC_WRITE_REQ = 72 +TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 73 +TCP_PERF_SEL_TCC_UC_READ_REQ = 74 +TCP_PERF_SEL_TCC_UC_WRITE_REQ = 75 +TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 76 +TCP_PERF_SEL_TCC_CC_READ_REQ = 77 +TCP_PERF_SEL_TCC_CC_WRITE_REQ = 78 +TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 79 +TCP_PERF_SEL_TCC_DCC_REQ = 80 +TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 81 +TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 82 +TCP_PERF_SEL_GL1_REQ_READ = 83 +TCP_PERF_SEL_GL1_REQ_READ_LATENCY = 84 +TCP_PERF_SEL_GL1_REQ_WRITE = 85 +TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY = 86 +TCP_PERF_SEL_REQ_MISS_TAGRAM0 = 87 +TCP_PERF_SEL_REQ_MISS_TAGRAM1 = 88 +TCP_PERF_SEL_REQ_MISS_TAGRAM2 = 89 +TCP_PERF_SEL_REQ_MISS_TAGRAM3 = 90 +TCP_PERF_SEL_TA_REQ = 91 +TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 92 +TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 93 +TCP_PERF_SEL_TA_REQ_READ = 94 +TCP_PERF_SEL_TA_REQ_WRITE = 95 +TCP_PERF_SEL_TA_REQ_STATE_READ = 96 +TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_POLICIES' +TCP_CACHE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_POLICY_MISS_LRU', + 1: 'TCP_CACHE_POLICY_MISS_EVICT', + 2: 'TCP_CACHE_POLICY_HIT_LRU', + 3: 'TCP_CACHE_POLICY_HIT_EVICT', +} +TCP_CACHE_POLICY_MISS_LRU = 0 +TCP_CACHE_POLICY_MISS_EVICT = 1 +TCP_CACHE_POLICY_HIT_LRU = 2 +TCP_CACHE_POLICY_HIT_EVICT = 3 +TCP_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_STORE_POLICIES' +TCP_CACHE_STORE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', + 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', +} +TCP_CACHE_STORE_POLICY_WT_LRU = 0 +TCP_CACHE_STORE_POLICY_WT_EVICT = 1 +TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_WATCH_MODES' +TCP_WATCH_MODES__enumvalues = { + 0: 'TCP_WATCH_MODE_READ', + 1: 'TCP_WATCH_MODE_NONREAD', + 2: 'TCP_WATCH_MODE_ATOMIC', + 3: 'TCP_WATCH_MODE_ALL', +} +TCP_WATCH_MODE_READ = 0 +TCP_WATCH_MODE_NONREAD = 1 +TCP_WATCH_MODE_ATOMIC = 2 +TCP_WATCH_MODE_ALL = 3 +TCP_WATCH_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_DATA_SEL' +TCP_DSM_DATA_SEL__enumvalues = { + 0: 'TCP_DSM_DISABLE', + 1: 'TCP_DSM_SEL0', + 2: 'TCP_DSM_SEL1', + 3: 'TCP_DSM_SEL_BOTH', +} +TCP_DSM_DISABLE = 0 +TCP_DSM_SEL0 = 1 +TCP_DSM_SEL1 = 2 +TCP_DSM_SEL_BOTH = 3 +TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_SINGLE_WRITE' +TCP_DSM_SINGLE_WRITE__enumvalues = { + 0: 'TCP_DSM_SINGLE_WRITE_DIS', + 1: 'TCP_DSM_SINGLE_WRITE_EN', +} +TCP_DSM_SINGLE_WRITE_DIS = 0 +TCP_DSM_SINGLE_WRITE_EN = 1 +TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_INJECT_SEL' +TCP_DSM_INJECT_SEL__enumvalues = { + 0: 'TCP_DSM_INJECT_SEL0', + 1: 'TCP_DSM_INJECT_SEL1', + 2: 'TCP_DSM_INJECT_SEL2', + 3: 'TCP_DSM_INJECT_SEL3', +} +TCP_DSM_INJECT_SEL0 = 0 +TCP_DSM_INJECT_SEL1 = 1 +TCP_DSM_INJECT_SEL2 = 2 +TCP_DSM_INJECT_SEL3 = 3 +TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_OPCODE_TYPE' +TCP_OPCODE_TYPE__enumvalues = { + 0: 'TCP_OPCODE_READ', + 1: 'TCP_OPCODE_WRITE', + 2: 'TCP_OPCODE_ATOMIC', + 3: 'TCP_OPCODE_WBINVL1', + 4: 'TCP_OPCODE_ATOMIC_CMPSWAP', + 5: 'TCP_OPCODE_GATHERH', +} +TCP_OPCODE_READ = 0 +TCP_OPCODE_WRITE = 1 +TCP_OPCODE_ATOMIC = 2 +TCP_OPCODE_WBINVL1 = 3 +TCP_OPCODE_ATOMIC_CMPSWAP = 4 +TCP_OPCODE_GATHERH = 5 +TCP_OPCODE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'GL2C_PERF_SEL' +GL2C_PERF_SEL__enumvalues = { + 0: 'GL2C_PERF_SEL_NONE', + 1: 'GL2C_PERF_SEL_CYCLE', + 2: 'GL2C_PERF_SEL_BUSY', + 3: 'GL2C_PERF_SEL_REQ', + 4: 'GL2C_PERF_SEL_VOL_REQ', + 5: 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', + 6: 'GL2C_PERF_SEL_READ', + 7: 'GL2C_PERF_SEL_WRITE', + 8: 'GL2C_PERF_SEL_ATOMIC', + 9: 'GL2C_PERF_SEL_NOP_ACK', + 10: 'GL2C_PERF_SEL_NOP_RTN0', + 11: 'GL2C_PERF_SEL_PROBE', + 12: 'GL2C_PERF_SEL_PROBE_ALL', + 13: 'GL2C_PERF_SEL_INTERNAL_PROBE', + 14: 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', + 15: 'GL2C_PERF_SEL_METADATA_READ_REQ', + 16: 'GL2C_PERF_SEL_CLIENT0_REQ', + 17: 'GL2C_PERF_SEL_CLIENT1_REQ', + 18: 'GL2C_PERF_SEL_CLIENT2_REQ', + 19: 'GL2C_PERF_SEL_CLIENT3_REQ', + 20: 'GL2C_PERF_SEL_CLIENT4_REQ', + 21: 'GL2C_PERF_SEL_CLIENT5_REQ', + 22: 'GL2C_PERF_SEL_CLIENT6_REQ', + 23: 'GL2C_PERF_SEL_CLIENT7_REQ', + 24: 'GL2C_PERF_SEL_C_RW_S_REQ', + 25: 'GL2C_PERF_SEL_C_RW_US_REQ', + 26: 'GL2C_PERF_SEL_C_RO_S_REQ', + 27: 'GL2C_PERF_SEL_C_RO_US_REQ', + 28: 'GL2C_PERF_SEL_UC_REQ', + 29: 'GL2C_PERF_SEL_LRU_REQ', + 30: 'GL2C_PERF_SEL_STREAM_REQ', + 31: 'GL2C_PERF_SEL_BYPASS_REQ', + 32: 'GL2C_PERF_SEL_NOA_REQ', + 33: 'GL2C_PERF_SEL_SHARED_REQ', + 34: 'GL2C_PERF_SEL_HIT', + 35: 'GL2C_PERF_SEL_MISS', + 36: 'GL2C_PERF_SEL_FULL_HIT', + 37: 'GL2C_PERF_SEL_PARTIAL_32B_HIT', + 38: 'GL2C_PERF_SEL_PARTIAL_64B_HIT', + 39: 'GL2C_PERF_SEL_PARTIAL_96B_HIT', + 40: 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', + 41: 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', + 42: 'GL2C_PERF_SEL_UNCACHED_WRITE', + 43: 'GL2C_PERF_SEL_WRITEBACK', + 44: 'GL2C_PERF_SEL_NORMAL_WRITEBACK', + 45: 'GL2C_PERF_SEL_EVICT', + 46: 'GL2C_PERF_SEL_NORMAL_EVICT', + 47: 'GL2C_PERF_SEL_PROBE_EVICT', + 48: 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', + 49: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO', + 50: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP', + 51: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', + 52: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', + 53: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', + 54: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', + 55: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', + 56: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', + 57: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', + 58: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', + 59: 'GL2C_PERF_SEL_READ_32_REQ', + 60: 'GL2C_PERF_SEL_READ_64_REQ', + 61: 'GL2C_PERF_SEL_READ_128_REQ', + 62: 'GL2C_PERF_SEL_WRITE_32_REQ', + 63: 'GL2C_PERF_SEL_WRITE_64_REQ', + 64: 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', + 65: 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', + 66: 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', + 67: 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', + 68: 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', + 69: 'GL2C_PERF_SEL_MC_WRREQ', + 70: 'GL2C_PERF_SEL_EA_WRREQ_64B', + 71: 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', + 72: 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', + 73: 'GL2C_PERF_SEL_MC_WRREQ_STALL', + 74: 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', + 75: 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', + 76: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', + 77: 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', + 78: 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', + 79: 'GL2C_PERF_SEL_EA_ATOMIC', + 80: 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', + 81: 'GL2C_PERF_SEL_MC_RDREQ', + 82: 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', + 83: 'GL2C_PERF_SEL_EA_RDREQ_32B', + 84: 'GL2C_PERF_SEL_EA_RDREQ_64B', + 85: 'GL2C_PERF_SEL_EA_RDREQ_96B', + 86: 'GL2C_PERF_SEL_EA_RDREQ_128B', + 87: 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', + 88: 'GL2C_PERF_SEL_EA_RD_MDC_32B', + 89: 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', + 90: 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', + 91: 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', + 92: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', + 93: 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', + 94: 'GL2C_PERF_SEL_EA_RDREQ_DRAM', + 95: 'GL2C_PERF_SEL_EA_WRREQ_DRAM', + 96: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', + 97: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', + 98: 'GL2C_PERF_SEL_ONION_READ', + 99: 'GL2C_PERF_SEL_ONION_WRITE', + 100: 'GL2C_PERF_SEL_IO_READ', + 101: 'GL2C_PERF_SEL_IO_WRITE', + 102: 'GL2C_PERF_SEL_GARLIC_READ', + 103: 'GL2C_PERF_SEL_GARLIC_WRITE', + 104: 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', + 105: 'GL2C_PERF_SEL_SRC_FIFO_FULL', + 106: 'GL2C_PERF_SEL_TAG_STALL', + 107: 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 108: 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 109: 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 110: 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 111: 'GL2C_PERF_SEL_TAG_PROBE_STALL', + 112: 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', + 113: 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', + 114: 'GL2C_PERF_SEL_TAG_READ_DST_STALL', + 115: 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', + 116: 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 117: 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 118: 'GL2C_PERF_SEL_BUBBLE', + 119: 'GL2C_PERF_SEL_IB_REQ', + 120: 'GL2C_PERF_SEL_IB_STALL', + 121: 'GL2C_PERF_SEL_IB_TAG_STALL', + 122: 'GL2C_PERF_SEL_IB_CM_STALL', + 123: 'GL2C_PERF_SEL_RETURN_ACK', + 124: 'GL2C_PERF_SEL_RETURN_DATA', + 125: 'GL2C_PERF_SEL_EA_RDRET_NACK', + 126: 'GL2C_PERF_SEL_EA_WRRET_NACK', + 127: 'GL2C_PERF_SEL_GL2A_LEVEL', + 128: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', + 129: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', + 130: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 131: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', + 132: 'GL2C_PERF_SEL_GCR_INV', + 133: 'GL2C_PERF_SEL_GCR_WB', + 134: 'GL2C_PERF_SEL_GCR_DISCARD', + 135: 'GL2C_PERF_SEL_GCR_RANGE', + 136: 'GL2C_PERF_SEL_GCR_ALL', + 137: 'GL2C_PERF_SEL_GCR_VOL', + 138: 'GL2C_PERF_SEL_GCR_UNSHARED', + 139: 'GL2C_PERF_SEL_GCR_MDC_INV', + 140: 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', + 141: 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', + 142: 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', + 143: 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', + 144: 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', + 145: 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', + 146: 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', + 147: 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', + 148: 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', + 149: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', + 150: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', + 151: 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', + 152: 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', + 153: 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', + 154: 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', + 155: 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', + 156: 'GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT', + 157: 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', + 158: 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', + 159: 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', + 160: 'GL2C_PERF_SEL_GCR_WBINVL2_START', + 161: 'GL2C_PERF_SEL_MDC_INV_METADATA', + 162: 'GL2C_PERF_SEL_MDC_REQ', + 163: 'GL2C_PERF_SEL_MDC_LEVEL', + 164: 'GL2C_PERF_SEL_MDC_TAG_HIT', + 165: 'GL2C_PERF_SEL_MDC_SECTOR_HIT', + 166: 'GL2C_PERF_SEL_MDC_SECTOR_MISS', + 167: 'GL2C_PERF_SEL_MDC_TAG_STALL', + 168: 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', + 169: 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', + 170: 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', + 171: 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', + 172: 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', + 173: 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', + 174: 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', + 175: 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', + 176: 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', + 177: 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', + 178: 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', + 179: 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', + 180: 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', + 181: 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', + 182: 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', + 183: 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', + 184: 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', + 185: 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', + 186: 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', + 187: 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', + 188: 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', + 189: 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', + 190: 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', + 191: 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', + 192: 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', + 193: 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', + 194: 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', + 195: 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', + 196: 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', + 197: 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', + 198: 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', + 199: 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', + 200: 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', + 201: 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', + 202: 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', + 203: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', + 204: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', + 205: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', + 206: 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', + 207: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', + 208: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', + 209: 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', + 210: 'GL2C_PERF_SEL_CM_COMP_READ_REQ', + 211: 'GL2C_PERF_SEL_CM_READ_BACK_REQ', + 212: 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', + 213: 'GL2C_PERF_SEL_CM_WR_ACK_REQ', + 214: 'GL2C_PERF_SEL_CM_NO_ACK_REQ', + 215: 'GL2C_PERF_SEL_CM_NOOP_REQ', + 216: 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', + 217: 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', + 218: 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', + 219: 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', + 220: 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', + 221: 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', + 222: 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', + 223: 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', + 224: 'GL2C_PERF_SEL_CM_RVF_FULL', + 225: 'GL2C_PERF_SEL_CM_SDR_FULL', + 226: 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', + 227: 'GL2C_PERF_SEL_CM_DCC_STALL', +} +GL2C_PERF_SEL_NONE = 0 +GL2C_PERF_SEL_CYCLE = 1 +GL2C_PERF_SEL_BUSY = 2 +GL2C_PERF_SEL_REQ = 3 +GL2C_PERF_SEL_VOL_REQ = 4 +GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 5 +GL2C_PERF_SEL_READ = 6 +GL2C_PERF_SEL_WRITE = 7 +GL2C_PERF_SEL_ATOMIC = 8 +GL2C_PERF_SEL_NOP_ACK = 9 +GL2C_PERF_SEL_NOP_RTN0 = 10 +GL2C_PERF_SEL_PROBE = 11 +GL2C_PERF_SEL_PROBE_ALL = 12 +GL2C_PERF_SEL_INTERNAL_PROBE = 13 +GL2C_PERF_SEL_COMPRESSED_READ_REQ = 14 +GL2C_PERF_SEL_METADATA_READ_REQ = 15 +GL2C_PERF_SEL_CLIENT0_REQ = 16 +GL2C_PERF_SEL_CLIENT1_REQ = 17 +GL2C_PERF_SEL_CLIENT2_REQ = 18 +GL2C_PERF_SEL_CLIENT3_REQ = 19 +GL2C_PERF_SEL_CLIENT4_REQ = 20 +GL2C_PERF_SEL_CLIENT5_REQ = 21 +GL2C_PERF_SEL_CLIENT6_REQ = 22 +GL2C_PERF_SEL_CLIENT7_REQ = 23 +GL2C_PERF_SEL_C_RW_S_REQ = 24 +GL2C_PERF_SEL_C_RW_US_REQ = 25 +GL2C_PERF_SEL_C_RO_S_REQ = 26 +GL2C_PERF_SEL_C_RO_US_REQ = 27 +GL2C_PERF_SEL_UC_REQ = 28 +GL2C_PERF_SEL_LRU_REQ = 29 +GL2C_PERF_SEL_STREAM_REQ = 30 +GL2C_PERF_SEL_BYPASS_REQ = 31 +GL2C_PERF_SEL_NOA_REQ = 32 +GL2C_PERF_SEL_SHARED_REQ = 33 +GL2C_PERF_SEL_HIT = 34 +GL2C_PERF_SEL_MISS = 35 +GL2C_PERF_SEL_FULL_HIT = 36 +GL2C_PERF_SEL_PARTIAL_32B_HIT = 37 +GL2C_PERF_SEL_PARTIAL_64B_HIT = 38 +GL2C_PERF_SEL_PARTIAL_96B_HIT = 39 +GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 40 +GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 41 +GL2C_PERF_SEL_UNCACHED_WRITE = 42 +GL2C_PERF_SEL_WRITEBACK = 43 +GL2C_PERF_SEL_NORMAL_WRITEBACK = 44 +GL2C_PERF_SEL_EVICT = 45 +GL2C_PERF_SEL_NORMAL_EVICT = 46 +GL2C_PERF_SEL_PROBE_EVICT = 47 +GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 48 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO = 49 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP = 50 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 51 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 52 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 53 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 54 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 55 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 56 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 57 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 58 +GL2C_PERF_SEL_READ_32_REQ = 59 +GL2C_PERF_SEL_READ_64_REQ = 60 +GL2C_PERF_SEL_READ_128_REQ = 61 +GL2C_PERF_SEL_WRITE_32_REQ = 62 +GL2C_PERF_SEL_WRITE_64_REQ = 63 +GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 64 +GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 65 +GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 66 +GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 67 +GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 68 +GL2C_PERF_SEL_MC_WRREQ = 69 +GL2C_PERF_SEL_EA_WRREQ_64B = 70 +GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 71 +GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 72 +GL2C_PERF_SEL_MC_WRREQ_STALL = 73 +GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 74 +GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 75 +GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 76 +GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 77 +GL2C_PERF_SEL_MC_WRREQ_LEVEL = 78 +GL2C_PERF_SEL_EA_ATOMIC = 79 +GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 80 +GL2C_PERF_SEL_MC_RDREQ = 81 +GL2C_PERF_SEL_EA_RDREQ_SPLIT = 82 +GL2C_PERF_SEL_EA_RDREQ_32B = 83 +GL2C_PERF_SEL_EA_RDREQ_64B = 84 +GL2C_PERF_SEL_EA_RDREQ_96B = 85 +GL2C_PERF_SEL_EA_RDREQ_128B = 86 +GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 87 +GL2C_PERF_SEL_EA_RD_MDC_32B = 88 +GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 89 +GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 90 +GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 91 +GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 92 +GL2C_PERF_SEL_MC_RDREQ_LEVEL = 93 +GL2C_PERF_SEL_EA_RDREQ_DRAM = 94 +GL2C_PERF_SEL_EA_WRREQ_DRAM = 95 +GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 96 +GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 97 +GL2C_PERF_SEL_ONION_READ = 98 +GL2C_PERF_SEL_ONION_WRITE = 99 +GL2C_PERF_SEL_IO_READ = 100 +GL2C_PERF_SEL_IO_WRITE = 101 +GL2C_PERF_SEL_GARLIC_READ = 102 +GL2C_PERF_SEL_GARLIC_WRITE = 103 +GL2C_PERF_SEL_LATENCY_FIFO_FULL = 104 +GL2C_PERF_SEL_SRC_FIFO_FULL = 105 +GL2C_PERF_SEL_TAG_STALL = 106 +GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 107 +GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 108 +GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 109 +GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 110 +GL2C_PERF_SEL_TAG_PROBE_STALL = 111 +GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 112 +GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 113 +GL2C_PERF_SEL_TAG_READ_DST_STALL = 114 +GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 115 +GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 116 +GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 117 +GL2C_PERF_SEL_BUBBLE = 118 +GL2C_PERF_SEL_IB_REQ = 119 +GL2C_PERF_SEL_IB_STALL = 120 +GL2C_PERF_SEL_IB_TAG_STALL = 121 +GL2C_PERF_SEL_IB_CM_STALL = 122 +GL2C_PERF_SEL_RETURN_ACK = 123 +GL2C_PERF_SEL_RETURN_DATA = 124 +GL2C_PERF_SEL_EA_RDRET_NACK = 125 +GL2C_PERF_SEL_EA_WRRET_NACK = 126 +GL2C_PERF_SEL_GL2A_LEVEL = 127 +GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 128 +GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 129 +GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 130 +GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 131 +GL2C_PERF_SEL_GCR_INV = 132 +GL2C_PERF_SEL_GCR_WB = 133 +GL2C_PERF_SEL_GCR_DISCARD = 134 +GL2C_PERF_SEL_GCR_RANGE = 135 +GL2C_PERF_SEL_GCR_ALL = 136 +GL2C_PERF_SEL_GCR_VOL = 137 +GL2C_PERF_SEL_GCR_UNSHARED = 138 +GL2C_PERF_SEL_GCR_MDC_INV = 139 +GL2C_PERF_SEL_GCR_GL2_INV_ALL = 140 +GL2C_PERF_SEL_GCR_GL2_WB_ALL = 141 +GL2C_PERF_SEL_GCR_MDC_INV_ALL = 142 +GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 143 +GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 144 +GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 145 +GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 146 +GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 147 +GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 148 +GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 149 +GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 150 +GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 151 +GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 152 +GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 153 +GL2C_PERF_SEL_GCR_INVL2_VOL_START = 154 +GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 155 +GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT = 156 +GL2C_PERF_SEL_GCR_WBL2_VOL_START = 157 +GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 158 +GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 159 +GL2C_PERF_SEL_GCR_WBINVL2_START = 160 +GL2C_PERF_SEL_MDC_INV_METADATA = 161 +GL2C_PERF_SEL_MDC_REQ = 162 +GL2C_PERF_SEL_MDC_LEVEL = 163 +GL2C_PERF_SEL_MDC_TAG_HIT = 164 +GL2C_PERF_SEL_MDC_SECTOR_HIT = 165 +GL2C_PERF_SEL_MDC_SECTOR_MISS = 166 +GL2C_PERF_SEL_MDC_TAG_STALL = 167 +GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 168 +GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 169 +GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 170 +GL2C_PERF_SEL_CM_CHANNEL0_REQ = 171 +GL2C_PERF_SEL_CM_CHANNEL1_REQ = 172 +GL2C_PERF_SEL_CM_CHANNEL2_REQ = 173 +GL2C_PERF_SEL_CM_CHANNEL3_REQ = 174 +GL2C_PERF_SEL_CM_CHANNEL4_REQ = 175 +GL2C_PERF_SEL_CM_CHANNEL5_REQ = 176 +GL2C_PERF_SEL_CM_CHANNEL6_REQ = 177 +GL2C_PERF_SEL_CM_CHANNEL7_REQ = 178 +GL2C_PERF_SEL_CM_CHANNEL8_REQ = 179 +GL2C_PERF_SEL_CM_CHANNEL9_REQ = 180 +GL2C_PERF_SEL_CM_CHANNEL10_REQ = 181 +GL2C_PERF_SEL_CM_CHANNEL11_REQ = 182 +GL2C_PERF_SEL_CM_CHANNEL12_REQ = 183 +GL2C_PERF_SEL_CM_CHANNEL13_REQ = 184 +GL2C_PERF_SEL_CM_CHANNEL14_REQ = 185 +GL2C_PERF_SEL_CM_CHANNEL15_REQ = 186 +GL2C_PERF_SEL_CM_CHANNEL16_REQ = 187 +GL2C_PERF_SEL_CM_CHANNEL17_REQ = 188 +GL2C_PERF_SEL_CM_CHANNEL18_REQ = 189 +GL2C_PERF_SEL_CM_CHANNEL19_REQ = 190 +GL2C_PERF_SEL_CM_CHANNEL20_REQ = 191 +GL2C_PERF_SEL_CM_CHANNEL21_REQ = 192 +GL2C_PERF_SEL_CM_CHANNEL22_REQ = 193 +GL2C_PERF_SEL_CM_CHANNEL23_REQ = 194 +GL2C_PERF_SEL_CM_CHANNEL24_REQ = 195 +GL2C_PERF_SEL_CM_CHANNEL25_REQ = 196 +GL2C_PERF_SEL_CM_CHANNEL26_REQ = 197 +GL2C_PERF_SEL_CM_CHANNEL27_REQ = 198 +GL2C_PERF_SEL_CM_CHANNEL28_REQ = 199 +GL2C_PERF_SEL_CM_CHANNEL29_REQ = 200 +GL2C_PERF_SEL_CM_CHANNEL30_REQ = 201 +GL2C_PERF_SEL_CM_CHANNEL31_REQ = 202 +GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 203 +GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 204 +GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 205 +GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 206 +GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 207 +GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 208 +GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 209 +GL2C_PERF_SEL_CM_COMP_READ_REQ = 210 +GL2C_PERF_SEL_CM_READ_BACK_REQ = 211 +GL2C_PERF_SEL_CM_METADATA_WR_REQ = 212 +GL2C_PERF_SEL_CM_WR_ACK_REQ = 213 +GL2C_PERF_SEL_CM_NO_ACK_REQ = 214 +GL2C_PERF_SEL_CM_NOOP_REQ = 215 +GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 216 +GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 217 +GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 218 +GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 219 +GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 220 +GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 221 +GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 222 +GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 223 +GL2C_PERF_SEL_CM_RVF_FULL = 224 +GL2C_PERF_SEL_CM_SDR_FULL = 225 +GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 226 +GL2C_PERF_SEL_CM_DCC_STALL = 227 +GL2C_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL2A_PERF_SEL' +GL2A_PERF_SEL__enumvalues = { + 0: 'GL2A_PERF_SEL_NONE', + 1: 'GL2A_PERF_SEL_CYCLE', + 2: 'GL2A_PERF_SEL_BUSY', + 3: 'GL2A_PERF_SEL_REQ_GL2C0', + 4: 'GL2A_PERF_SEL_REQ_GL2C1', + 5: 'GL2A_PERF_SEL_REQ_GL2C2', + 6: 'GL2A_PERF_SEL_REQ_GL2C3', + 7: 'GL2A_PERF_SEL_REQ_GL2C4', + 8: 'GL2A_PERF_SEL_REQ_GL2C5', + 9: 'GL2A_PERF_SEL_REQ_GL2C6', + 10: 'GL2A_PERF_SEL_REQ_GL2C7', + 11: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', + 12: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', + 13: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', + 14: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', + 15: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', + 16: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', + 17: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', + 18: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', + 19: 'GL2A_PERF_SEL_REQ_BURST_GL2C0', + 20: 'GL2A_PERF_SEL_REQ_BURST_GL2C1', + 21: 'GL2A_PERF_SEL_REQ_BURST_GL2C2', + 22: 'GL2A_PERF_SEL_REQ_BURST_GL2C3', + 23: 'GL2A_PERF_SEL_REQ_BURST_GL2C4', + 24: 'GL2A_PERF_SEL_REQ_BURST_GL2C5', + 25: 'GL2A_PERF_SEL_REQ_BURST_GL2C6', + 26: 'GL2A_PERF_SEL_REQ_BURST_GL2C7', + 27: 'GL2A_PERF_SEL_REQ_STALL_GL2C0', + 28: 'GL2A_PERF_SEL_REQ_STALL_GL2C1', + 29: 'GL2A_PERF_SEL_REQ_STALL_GL2C2', + 30: 'GL2A_PERF_SEL_REQ_STALL_GL2C3', + 31: 'GL2A_PERF_SEL_REQ_STALL_GL2C4', + 32: 'GL2A_PERF_SEL_REQ_STALL_GL2C5', + 33: 'GL2A_PERF_SEL_REQ_STALL_GL2C6', + 34: 'GL2A_PERF_SEL_REQ_STALL_GL2C7', + 35: 'GL2A_PERF_SEL_RTN_STALL_GL2C0', + 36: 'GL2A_PERF_SEL_RTN_STALL_GL2C1', + 37: 'GL2A_PERF_SEL_RTN_STALL_GL2C2', + 38: 'GL2A_PERF_SEL_RTN_STALL_GL2C3', + 39: 'GL2A_PERF_SEL_RTN_STALL_GL2C4', + 40: 'GL2A_PERF_SEL_RTN_STALL_GL2C5', + 41: 'GL2A_PERF_SEL_RTN_STALL_GL2C6', + 42: 'GL2A_PERF_SEL_RTN_STALL_GL2C7', + 43: 'GL2A_PERF_SEL_RTN_CLIENT0', + 44: 'GL2A_PERF_SEL_RTN_CLIENT1', + 45: 'GL2A_PERF_SEL_RTN_CLIENT2', + 46: 'GL2A_PERF_SEL_RTN_CLIENT3', + 47: 'GL2A_PERF_SEL_RTN_CLIENT4', + 48: 'GL2A_PERF_SEL_RTN_CLIENT5', + 49: 'GL2A_PERF_SEL_RTN_CLIENT6', + 50: 'GL2A_PERF_SEL_RTN_CLIENT7', + 51: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', + 52: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', + 53: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', + 54: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', + 55: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', + 56: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', + 57: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', + 58: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', +} +GL2A_PERF_SEL_NONE = 0 +GL2A_PERF_SEL_CYCLE = 1 +GL2A_PERF_SEL_BUSY = 2 +GL2A_PERF_SEL_REQ_GL2C0 = 3 +GL2A_PERF_SEL_REQ_GL2C1 = 4 +GL2A_PERF_SEL_REQ_GL2C2 = 5 +GL2A_PERF_SEL_REQ_GL2C3 = 6 +GL2A_PERF_SEL_REQ_GL2C4 = 7 +GL2A_PERF_SEL_REQ_GL2C5 = 8 +GL2A_PERF_SEL_REQ_GL2C6 = 9 +GL2A_PERF_SEL_REQ_GL2C7 = 10 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 11 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 12 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 13 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 14 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 15 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 16 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 17 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 18 +GL2A_PERF_SEL_REQ_BURST_GL2C0 = 19 +GL2A_PERF_SEL_REQ_BURST_GL2C1 = 20 +GL2A_PERF_SEL_REQ_BURST_GL2C2 = 21 +GL2A_PERF_SEL_REQ_BURST_GL2C3 = 22 +GL2A_PERF_SEL_REQ_BURST_GL2C4 = 23 +GL2A_PERF_SEL_REQ_BURST_GL2C5 = 24 +GL2A_PERF_SEL_REQ_BURST_GL2C6 = 25 +GL2A_PERF_SEL_REQ_BURST_GL2C7 = 26 +GL2A_PERF_SEL_REQ_STALL_GL2C0 = 27 +GL2A_PERF_SEL_REQ_STALL_GL2C1 = 28 +GL2A_PERF_SEL_REQ_STALL_GL2C2 = 29 +GL2A_PERF_SEL_REQ_STALL_GL2C3 = 30 +GL2A_PERF_SEL_REQ_STALL_GL2C4 = 31 +GL2A_PERF_SEL_REQ_STALL_GL2C5 = 32 +GL2A_PERF_SEL_REQ_STALL_GL2C6 = 33 +GL2A_PERF_SEL_REQ_STALL_GL2C7 = 34 +GL2A_PERF_SEL_RTN_STALL_GL2C0 = 35 +GL2A_PERF_SEL_RTN_STALL_GL2C1 = 36 +GL2A_PERF_SEL_RTN_STALL_GL2C2 = 37 +GL2A_PERF_SEL_RTN_STALL_GL2C3 = 38 +GL2A_PERF_SEL_RTN_STALL_GL2C4 = 39 +GL2A_PERF_SEL_RTN_STALL_GL2C5 = 40 +GL2A_PERF_SEL_RTN_STALL_GL2C6 = 41 +GL2A_PERF_SEL_RTN_STALL_GL2C7 = 42 +GL2A_PERF_SEL_RTN_CLIENT0 = 43 +GL2A_PERF_SEL_RTN_CLIENT1 = 44 +GL2A_PERF_SEL_RTN_CLIENT2 = 45 +GL2A_PERF_SEL_RTN_CLIENT3 = 46 +GL2A_PERF_SEL_RTN_CLIENT4 = 47 +GL2A_PERF_SEL_RTN_CLIENT5 = 48 +GL2A_PERF_SEL_RTN_CLIENT6 = 49 +GL2A_PERF_SEL_RTN_CLIENT7 = 50 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 51 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 52 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 53 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 54 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 55 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 56 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 57 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 58 +GL2A_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_PERF_SEL' +GRBM_PERF_SEL__enumvalues = { + 0: 'GRBM_PERF_SEL_COUNT', + 1: 'GRBM_PERF_SEL_USER_DEFINED', + 2: 'GRBM_PERF_SEL_GUI_ACTIVE', + 3: 'GRBM_PERF_SEL_CP_BUSY', + 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', + 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', + 6: 'GRBM_PERF_SEL_CB_BUSY', + 7: 'GRBM_PERF_SEL_DB_BUSY', + 8: 'GRBM_PERF_SEL_PA_BUSY', + 9: 'GRBM_PERF_SEL_SC_BUSY', + 10: 'GRBM_PERF_SEL_RESERVED_6', + 11: 'GRBM_PERF_SEL_SPI_BUSY', + 12: 'GRBM_PERF_SEL_SX_BUSY', + 13: 'GRBM_PERF_SEL_TA_BUSY', + 14: 'GRBM_PERF_SEL_CB_CLEAN', + 15: 'GRBM_PERF_SEL_DB_CLEAN', + 16: 'GRBM_PERF_SEL_RESERVED_5', + 17: 'GRBM_PERF_SEL_RESERVED_9', + 18: 'GRBM_PERF_SEL_RESERVED_4', + 19: 'GRBM_PERF_SEL_RESERVED_3', + 20: 'GRBM_PERF_SEL_RESERVED_2', + 21: 'GRBM_PERF_SEL_RESERVED_1', + 22: 'GRBM_PERF_SEL_RESERVED_0', + 23: 'GRBM_PERF_SEL_RESERVED_8', + 24: 'GRBM_PERF_SEL_RESERVED_7', + 25: 'GRBM_PERF_SEL_GDS_BUSY', + 26: 'GRBM_PERF_SEL_BCI_BUSY', + 27: 'GRBM_PERF_SEL_RLC_BUSY', + 28: 'GRBM_PERF_SEL_TCP_BUSY', + 29: 'GRBM_PERF_SEL_CPG_BUSY', + 30: 'GRBM_PERF_SEL_CPC_BUSY', + 31: 'GRBM_PERF_SEL_CPF_BUSY', + 32: 'GRBM_PERF_SEL_GE_BUSY', + 33: 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', + 34: 'GRBM_PERF_SEL_UTCL2_BUSY', + 35: 'GRBM_PERF_SEL_EA_BUSY', + 36: 'GRBM_PERF_SEL_RMI_BUSY', + 37: 'GRBM_PERF_SEL_CPAXI_BUSY', + 39: 'GRBM_PERF_SEL_UTCL1_BUSY', + 40: 'GRBM_PERF_SEL_GL2CC_BUSY', + 41: 'GRBM_PERF_SEL_SDMA_BUSY', + 42: 'GRBM_PERF_SEL_CH_BUSY', + 43: 'GRBM_PERF_SEL_PH_BUSY', + 44: 'GRBM_PERF_SEL_PMM_BUSY', + 45: 'GRBM_PERF_SEL_GUS_BUSY', + 46: 'GRBM_PERF_SEL_GL1CC_BUSY', +} +GRBM_PERF_SEL_COUNT = 0 +GRBM_PERF_SEL_USER_DEFINED = 1 +GRBM_PERF_SEL_GUI_ACTIVE = 2 +GRBM_PERF_SEL_CP_BUSY = 3 +GRBM_PERF_SEL_CP_COHER_BUSY = 4 +GRBM_PERF_SEL_CP_DMA_BUSY = 5 +GRBM_PERF_SEL_CB_BUSY = 6 +GRBM_PERF_SEL_DB_BUSY = 7 +GRBM_PERF_SEL_PA_BUSY = 8 +GRBM_PERF_SEL_SC_BUSY = 9 +GRBM_PERF_SEL_RESERVED_6 = 10 +GRBM_PERF_SEL_SPI_BUSY = 11 +GRBM_PERF_SEL_SX_BUSY = 12 +GRBM_PERF_SEL_TA_BUSY = 13 +GRBM_PERF_SEL_CB_CLEAN = 14 +GRBM_PERF_SEL_DB_CLEAN = 15 +GRBM_PERF_SEL_RESERVED_5 = 16 +GRBM_PERF_SEL_RESERVED_9 = 17 +GRBM_PERF_SEL_RESERVED_4 = 18 +GRBM_PERF_SEL_RESERVED_3 = 19 +GRBM_PERF_SEL_RESERVED_2 = 20 +GRBM_PERF_SEL_RESERVED_1 = 21 +GRBM_PERF_SEL_RESERVED_0 = 22 +GRBM_PERF_SEL_RESERVED_8 = 23 +GRBM_PERF_SEL_RESERVED_7 = 24 +GRBM_PERF_SEL_GDS_BUSY = 25 +GRBM_PERF_SEL_BCI_BUSY = 26 +GRBM_PERF_SEL_RLC_BUSY = 27 +GRBM_PERF_SEL_TCP_BUSY = 28 +GRBM_PERF_SEL_CPG_BUSY = 29 +GRBM_PERF_SEL_CPC_BUSY = 30 +GRBM_PERF_SEL_CPF_BUSY = 31 +GRBM_PERF_SEL_GE_BUSY = 32 +GRBM_PERF_SEL_GE_NO_DMA_BUSY = 33 +GRBM_PERF_SEL_UTCL2_BUSY = 34 +GRBM_PERF_SEL_EA_BUSY = 35 +GRBM_PERF_SEL_RMI_BUSY = 36 +GRBM_PERF_SEL_CPAXI_BUSY = 37 +GRBM_PERF_SEL_UTCL1_BUSY = 39 +GRBM_PERF_SEL_GL2CC_BUSY = 40 +GRBM_PERF_SEL_SDMA_BUSY = 41 +GRBM_PERF_SEL_CH_BUSY = 42 +GRBM_PERF_SEL_PH_BUSY = 43 +GRBM_PERF_SEL_PMM_BUSY = 44 +GRBM_PERF_SEL_GUS_BUSY = 45 +GRBM_PERF_SEL_GL1CC_BUSY = 46 +GRBM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE0_PERF_SEL' +GRBM_SE0_PERF_SEL__enumvalues = { + 0: 'GRBM_SE0_PERF_SEL_COUNT', + 1: 'GRBM_SE0_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE0_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE0_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE0_PERF_SEL_SC_BUSY', + 5: 'GRBM_SE0_PERF_SEL_RESERVED_1', + 6: 'GRBM_SE0_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE0_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE0_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE0_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE0_PERF_SEL_DB_CLEAN', + 11: 'GRBM_SE0_PERF_SEL_RESERVED_0', + 12: 'GRBM_SE0_PERF_SEL_PA_BUSY', + 13: 'GRBM_SE0_PERF_SEL_RESERVED_2', + 14: 'GRBM_SE0_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE0_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE0_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', +} +GRBM_SE0_PERF_SEL_COUNT = 0 +GRBM_SE0_PERF_SEL_USER_DEFINED = 1 +GRBM_SE0_PERF_SEL_CB_BUSY = 2 +GRBM_SE0_PERF_SEL_DB_BUSY = 3 +GRBM_SE0_PERF_SEL_SC_BUSY = 4 +GRBM_SE0_PERF_SEL_RESERVED_1 = 5 +GRBM_SE0_PERF_SEL_SPI_BUSY = 6 +GRBM_SE0_PERF_SEL_SX_BUSY = 7 +GRBM_SE0_PERF_SEL_TA_BUSY = 8 +GRBM_SE0_PERF_SEL_CB_CLEAN = 9 +GRBM_SE0_PERF_SEL_DB_CLEAN = 10 +GRBM_SE0_PERF_SEL_RESERVED_0 = 11 +GRBM_SE0_PERF_SEL_PA_BUSY = 12 +GRBM_SE0_PERF_SEL_RESERVED_2 = 13 +GRBM_SE0_PERF_SEL_BCI_BUSY = 14 +GRBM_SE0_PERF_SEL_RMI_BUSY = 15 +GRBM_SE0_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE0_PERF_SEL_TCP_BUSY = 17 +GRBM_SE0_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE1_PERF_SEL' +GRBM_SE1_PERF_SEL__enumvalues = { + 0: 'GRBM_SE1_PERF_SEL_COUNT', + 1: 'GRBM_SE1_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE1_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE1_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE1_PERF_SEL_SC_BUSY', + 5: 'GRBM_SE1_PERF_SEL_RESERVED_1', + 6: 'GRBM_SE1_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE1_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE1_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE1_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE1_PERF_SEL_DB_CLEAN', + 11: 'GRBM_SE1_PERF_SEL_RESERVED_0', + 12: 'GRBM_SE1_PERF_SEL_PA_BUSY', + 13: 'GRBM_SE1_PERF_SEL_RESERVED_2', + 14: 'GRBM_SE1_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE1_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE1_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', +} +GRBM_SE1_PERF_SEL_COUNT = 0 +GRBM_SE1_PERF_SEL_USER_DEFINED = 1 +GRBM_SE1_PERF_SEL_CB_BUSY = 2 +GRBM_SE1_PERF_SEL_DB_BUSY = 3 +GRBM_SE1_PERF_SEL_SC_BUSY = 4 +GRBM_SE1_PERF_SEL_RESERVED_1 = 5 +GRBM_SE1_PERF_SEL_SPI_BUSY = 6 +GRBM_SE1_PERF_SEL_SX_BUSY = 7 +GRBM_SE1_PERF_SEL_TA_BUSY = 8 +GRBM_SE1_PERF_SEL_CB_CLEAN = 9 +GRBM_SE1_PERF_SEL_DB_CLEAN = 10 +GRBM_SE1_PERF_SEL_RESERVED_0 = 11 +GRBM_SE1_PERF_SEL_PA_BUSY = 12 +GRBM_SE1_PERF_SEL_RESERVED_2 = 13 +GRBM_SE1_PERF_SEL_BCI_BUSY = 14 +GRBM_SE1_PERF_SEL_RMI_BUSY = 15 +GRBM_SE1_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE1_PERF_SEL_TCP_BUSY = 17 +GRBM_SE1_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE2_PERF_SEL' +GRBM_SE2_PERF_SEL__enumvalues = { + 0: 'GRBM_SE2_PERF_SEL_COUNT', + 1: 'GRBM_SE2_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE2_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE2_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE2_PERF_SEL_SC_BUSY', + 5: 'GRBM_SE2_PERF_SEL_RESERVED_1', + 6: 'GRBM_SE2_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE2_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE2_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE2_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE2_PERF_SEL_DB_CLEAN', + 11: 'GRBM_SE2_PERF_SEL_RESERVED_0', + 12: 'GRBM_SE2_PERF_SEL_PA_BUSY', + 13: 'GRBM_SE2_PERF_SEL_RESERVED_2', + 14: 'GRBM_SE2_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE2_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE2_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', +} +GRBM_SE2_PERF_SEL_COUNT = 0 +GRBM_SE2_PERF_SEL_USER_DEFINED = 1 +GRBM_SE2_PERF_SEL_CB_BUSY = 2 +GRBM_SE2_PERF_SEL_DB_BUSY = 3 +GRBM_SE2_PERF_SEL_SC_BUSY = 4 +GRBM_SE2_PERF_SEL_RESERVED_1 = 5 +GRBM_SE2_PERF_SEL_SPI_BUSY = 6 +GRBM_SE2_PERF_SEL_SX_BUSY = 7 +GRBM_SE2_PERF_SEL_TA_BUSY = 8 +GRBM_SE2_PERF_SEL_CB_CLEAN = 9 +GRBM_SE2_PERF_SEL_DB_CLEAN = 10 +GRBM_SE2_PERF_SEL_RESERVED_0 = 11 +GRBM_SE2_PERF_SEL_PA_BUSY = 12 +GRBM_SE2_PERF_SEL_RESERVED_2 = 13 +GRBM_SE2_PERF_SEL_BCI_BUSY = 14 +GRBM_SE2_PERF_SEL_RMI_BUSY = 15 +GRBM_SE2_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE2_PERF_SEL_TCP_BUSY = 17 +GRBM_SE2_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE3_PERF_SEL' +GRBM_SE3_PERF_SEL__enumvalues = { + 0: 'GRBM_SE3_PERF_SEL_COUNT', + 1: 'GRBM_SE3_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE3_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE3_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE3_PERF_SEL_SC_BUSY', + 5: 'GRBM_SE3_PERF_SEL_RESERVED_1', + 6: 'GRBM_SE3_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE3_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE3_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE3_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE3_PERF_SEL_DB_CLEAN', + 11: 'GRBM_SE3_PERF_SEL_RESERVED_0', + 12: 'GRBM_SE3_PERF_SEL_PA_BUSY', + 13: 'GRBM_SE3_PERF_SEL_RESERVED_2', + 14: 'GRBM_SE3_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE3_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE3_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', +} +GRBM_SE3_PERF_SEL_COUNT = 0 +GRBM_SE3_PERF_SEL_USER_DEFINED = 1 +GRBM_SE3_PERF_SEL_CB_BUSY = 2 +GRBM_SE3_PERF_SEL_DB_BUSY = 3 +GRBM_SE3_PERF_SEL_SC_BUSY = 4 +GRBM_SE3_PERF_SEL_RESERVED_1 = 5 +GRBM_SE3_PERF_SEL_SPI_BUSY = 6 +GRBM_SE3_PERF_SEL_SX_BUSY = 7 +GRBM_SE3_PERF_SEL_TA_BUSY = 8 +GRBM_SE3_PERF_SEL_CB_CLEAN = 9 +GRBM_SE3_PERF_SEL_DB_CLEAN = 10 +GRBM_SE3_PERF_SEL_RESERVED_0 = 11 +GRBM_SE3_PERF_SEL_PA_BUSY = 12 +GRBM_SE3_PERF_SEL_RESERVED_2 = 13 +GRBM_SE3_PERF_SEL_BCI_BUSY = 14 +GRBM_SE3_PERF_SEL_RMI_BUSY = 15 +GRBM_SE3_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE3_PERF_SEL_TCP_BUSY = 17 +GRBM_SE3_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_RING_ID' +CP_RING_ID__enumvalues = { + 0: 'RINGID0', + 1: 'RINGID1', + 2: 'RINGID2', + 3: 'RINGID3', +} +RINGID0 = 0 +RINGID1 = 1 +RINGID2 = 2 +RINGID3 = 3 +CP_RING_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PIPE_ID' +CP_PIPE_ID__enumvalues = { + 0: 'PIPE_ID0', + 1: 'PIPE_ID1', + 2: 'PIPE_ID2', + 3: 'PIPE_ID3', +} +PIPE_ID0 = 0 +PIPE_ID1 = 1 +PIPE_ID2 = 2 +PIPE_ID3 = 3 +CP_PIPE_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ME_ID' +CP_ME_ID__enumvalues = { + 0: 'ME_ID0', + 1: 'ME_ID1', + 2: 'ME_ID2', + 3: 'ME_ID3', +} +ME_ID0 = 0 +ME_ID1 = 1 +ME_ID2 = 2 +ME_ID3 = 3 +CP_ME_ID = ctypes.c_uint32 # enum + +# values for enumeration 'SPM_PERFMON_STATE' +SPM_PERFMON_STATE__enumvalues = { + 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'STRM_PERFMON_STATE_START_COUNTING', + 2: 'STRM_PERFMON_STATE_STOP_COUNTING', + 3: 'STRM_PERFMON_STATE_RESERVED_3', + 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 +STRM_PERFMON_STATE_START_COUNTING = 1 +STRM_PERFMON_STATE_STOP_COUNTING = 2 +STRM_PERFMON_STATE_RESERVED_3 = 3 +STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +SPM_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_STATE' +CP_PERFMON_STATE__enumvalues = { + 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'CP_PERFMON_STATE_START_COUNTING', + 2: 'CP_PERFMON_STATE_STOP_COUNTING', + 3: 'CP_PERFMON_STATE_RESERVED_3', + 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +CP_PERFMON_STATE_DISABLE_AND_RESET = 0 +CP_PERFMON_STATE_START_COUNTING = 1 +CP_PERFMON_STATE_STOP_COUNTING = 2 +CP_PERFMON_STATE_RESERVED_3 = 3 +CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +CP_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_ENABLE_MODE' +CP_PERFMON_ENABLE_MODE__enumvalues = { + 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', + 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', +} +CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 +CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 +CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_PERFCOUNT_SEL' +CPG_PERFCOUNT_SEL__enumvalues = { + 0: 'CPG_PERF_SEL_ALWAYS_COUNT', + 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 2: 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR', + 3: 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL', + 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', + 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', + 8: 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 30: 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS', + 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 34: 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 35: 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', + 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 40: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU', + 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 49: 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 50: 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', + 51: 'CPG_PERF_SEL_CPG_STAT_BUSY', + 52: 'CPG_PERF_SEL_CPG_STAT_IDLE', + 53: 'CPG_PERF_SEL_CPG_STAT_STALL', + 54: 'CPG_PERF_SEL_CPG_TCIU_BUSY', + 55: 'CPG_PERF_SEL_CPG_TCIU_IDLE', + 56: 'CPF_PERF_SEL_CPG_TCIU_STALL', + 57: 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', + 58: 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', + 59: 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', + 60: 'CPG_PERF_SEL_CPG_GCRIU_BUSY', + 61: 'CPG_PERF_SEL_CPG_GCRIU_IDLE', + 62: 'CPG_PERF_SEL_CPG_GCRIU_STALL', + 63: 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 64: 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', + 65: 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', + 66: 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', + 67: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', + 68: 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', + 69: 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', + 70: 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', + 71: 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', + 72: 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', + 73: 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', + 74: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', + 75: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', + 76: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', + 77: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', +} +CPG_PERF_SEL_ALWAYS_COUNT = 0 +CPG_PERF_SEL_RBIU_FIFO_FULL = 1 +CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 2 +CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 3 +CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 +CPG_PERF_SEL_ME_PARSER_BUSY = 5 +CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 +CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 +CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 8 +CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 +CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 +CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 +CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 +CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 +CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 +CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 +CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 +CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 +CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 +CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 +CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 +CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 +CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 +CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 +CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 +CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 30 +CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 +CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 +CPG_PERF_SEL_REGISTER_CLK_VALID = 33 +CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 34 +CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 35 +CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 +CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 +CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 +CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 40 +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 +CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 +CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 +CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 +CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 49 +CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 50 +CPG_PERF_SEL_CPG_STAT_BUSY = 51 +CPG_PERF_SEL_CPG_STAT_IDLE = 52 +CPG_PERF_SEL_CPG_STAT_STALL = 53 +CPG_PERF_SEL_CPG_TCIU_BUSY = 54 +CPG_PERF_SEL_CPG_TCIU_IDLE = 55 +CPF_PERF_SEL_CPG_TCIU_STALL = 56 +CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 57 +CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 58 +CPG_PERF_SEL_CPG_UTCL2IU_STALL = 59 +CPG_PERF_SEL_CPG_GCRIU_BUSY = 60 +CPG_PERF_SEL_CPG_GCRIU_IDLE = 61 +CPG_PERF_SEL_CPG_GCRIU_STALL = 62 +CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 63 +CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 64 +CPG_PERF_SEL_CPG_UTCL2IU_XACK = 65 +CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 66 +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 67 +CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 68 +CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 69 +CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 70 +CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 71 +CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 72 +CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 73 +CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 74 +CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 75 +CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 76 +CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 77 +CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_PERFCOUNT_SEL' +CPF_PERFCOUNT_SEL__enumvalues = { + 0: 'CPF_PERF_SEL_ALWAYS_COUNT', + 1: 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE', + 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE', + 8: 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS', + 9: 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR', + 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 15: 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SEND', + 16: 'CPF_PERF_SEL_GUS_READ_REQUEST_SEND', + 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 19: 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', + 20: 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', + 21: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 22: 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 23: 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', + 24: 'CPF_PERF_SEL_CPF_STAT_BUSY', + 25: 'CPF_PERF_SEL_CPF_STAT_IDLE', + 26: 'CPF_PERF_SEL_CPF_STAT_STALL', + 27: 'CPF_PERF_SEL_CPF_TCIU_BUSY', + 28: 'CPF_PERF_SEL_CPF_TCIU_IDLE', + 29: 'CPF_PERF_SEL_CPF_TCIU_STALL', + 30: 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', + 31: 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', + 32: 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', + 33: 'CPF_PERF_SEL_CPF_GCRIU_BUSY', + 34: 'CPF_PERF_SEL_CPF_GCRIU_IDLE', + 35: 'CPF_PERF_SEL_CPF_GCRIU_STALL', + 36: 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 37: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', + 38: 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', + 39: 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', +} +CPF_PERF_SEL_ALWAYS_COUNT = 0 +CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 1 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 +CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 7 +CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 8 +CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 9 +CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 +CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 +CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 +CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 +CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 +CPF_PERF_SEL_GUS_WRITE_REQUEST_SEND = 15 +CPF_PERF_SEL_GUS_READ_REQUEST_SEND = 16 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 +CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 19 +CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 20 +CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 21 +CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 22 +CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 23 +CPF_PERF_SEL_CPF_STAT_BUSY = 24 +CPF_PERF_SEL_CPF_STAT_IDLE = 25 +CPF_PERF_SEL_CPF_STAT_STALL = 26 +CPF_PERF_SEL_CPF_TCIU_BUSY = 27 +CPF_PERF_SEL_CPF_TCIU_IDLE = 28 +CPF_PERF_SEL_CPF_TCIU_STALL = 29 +CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 30 +CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 31 +CPF_PERF_SEL_CPF_UTCL2IU_STALL = 32 +CPF_PERF_SEL_CPF_GCRIU_BUSY = 33 +CPF_PERF_SEL_CPF_GCRIU_IDLE = 34 +CPF_PERF_SEL_CPF_GCRIU_STALL = 35 +CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 36 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 37 +CPF_PERF_SEL_CPF_UTCL2IU_XACK = 38 +CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 39 +CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPC_PERFCOUNT_SEL' +CPC_PERFCOUNT_SEL__enumvalues = { + 0: 'CPC_PERF_SEL_ALWAYS_COUNT', + 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 3: 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE', + 4: 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE', + 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', + 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', + 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', + 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', + 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 25: 'CPC_PERF_SEL_CPC_STAT_BUSY', + 26: 'CPC_PERF_SEL_CPC_STAT_IDLE', + 27: 'CPC_PERF_SEL_CPC_STAT_STALL', + 28: 'CPC_PERF_SEL_CPC_TCIU_BUSY', + 29: 'CPC_PERF_SEL_CPC_TCIU_IDLE', + 30: 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', + 31: 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', + 32: 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', + 33: 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', + 34: 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', + 35: 'CPC_PERF_SEL_CPC_GCRIU_BUSY', + 36: 'CPC_PERF_SEL_CPC_GCRIU_IDLE', + 37: 'CPC_PERF_SEL_CPC_GCRIU_STALL', + 38: 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 39: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', + 40: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', + 41: 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', + 42: 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', + 43: 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', + 44: 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', +} +CPC_PERF_SEL_ALWAYS_COUNT = 0 +CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 +CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 +CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 3 +CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 4 +CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 9 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 10 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 +CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 17 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 18 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 +CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 +CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 +CPC_PERF_SEL_CPC_STAT_BUSY = 25 +CPC_PERF_SEL_CPC_STAT_IDLE = 26 +CPC_PERF_SEL_CPC_STAT_STALL = 27 +CPC_PERF_SEL_CPC_TCIU_BUSY = 28 +CPC_PERF_SEL_CPC_TCIU_IDLE = 29 +CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 30 +CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 31 +CPC_PERF_SEL_CPC_UTCL2IU_STALL = 32 +CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 33 +CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 34 +CPC_PERF_SEL_CPC_GCRIU_BUSY = 35 +CPC_PERF_SEL_CPC_GCRIU_IDLE = 36 +CPC_PERF_SEL_CPC_GCRIU_STALL = 37 +CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 38 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 39 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 40 +CPC_PERF_SEL_CPC_UTCL2IU_XACK = 41 +CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 42 +CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 43 +CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 44 +CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ALPHA_TAG_RAM_SEL' +CP_ALPHA_TAG_RAM_SEL__enumvalues = { + 0: 'CPG_TAG_RAM', + 1: 'CPC_TAG_RAM', + 2: 'CPF_TAG_RAM', + 3: 'RSV_TAG_RAM', +} +CPG_TAG_RAM = 0 +CPC_TAG_RAM = 1 +CPF_TAG_RAM = 2 +RSV_TAG_RAM = 3 +CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_PERFCOUNTWINDOW_SEL' +CPF_PERFCOUNTWINDOW_SEL__enumvalues = { + 0: 'CPF_PERFWINDOW_SEL_CSF', + 1: 'CPF_PERFWINDOW_SEL_HQD1', + 2: 'CPF_PERFWINDOW_SEL_HQD2', + 3: 'CPF_PERFWINDOW_SEL_RDMA', + 4: 'CPF_PERFWINDOW_SEL_RWPP', +} +CPF_PERFWINDOW_SEL_CSF = 0 +CPF_PERFWINDOW_SEL_HQD1 = 1 +CPF_PERFWINDOW_SEL_HQD2 = 2 +CPF_PERFWINDOW_SEL_RDMA = 3 +CPF_PERFWINDOW_SEL_RWPP = 4 +CPF_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_PERFCOUNTWINDOW_SEL' +CPG_PERFCOUNTWINDOW_SEL__enumvalues = { + 0: 'CPG_PERFWINDOW_SEL_PFP', + 1: 'CPG_PERFWINDOW_SEL_ME', + 2: 'CPG_PERFWINDOW_SEL_CE', + 3: 'CPG_PERFWINDOW_SEL_MES', + 4: 'CPG_PERFWINDOW_SEL_MEC1', + 5: 'CPG_PERFWINDOW_SEL_MEC2', + 6: 'CPG_PERFWINDOW_SEL_DFY', + 7: 'CPG_PERFWINDOW_SEL_DMA', + 8: 'CPG_PERFWINDOW_SEL_SHADOW', + 9: 'CPG_PERFWINDOW_SEL_RB', + 10: 'CPG_PERFWINDOW_SEL_CEDMA', + 11: 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', + 12: 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', + 13: 'CPG_PERFWINDOW_SEL_PQ1', + 14: 'CPG_PERFWINDOW_SEL_PQ2', + 15: 'CPG_PERFWINDOW_SEL_PQ3', + 16: 'CPG_PERFWINDOW_SEL_MEMWR', + 17: 'CPG_PERFWINDOW_SEL_MEMRD', + 18: 'CPG_PERFWINDOW_SEL_VGT0', + 19: 'CPG_PERFWINDOW_SEL_VGT1', + 20: 'CPG_PERFWINDOW_SEL_APPEND', + 21: 'CPG_PERFWINDOW_SEL_QURD', + 22: 'CPG_PERFWINDOW_SEL_DDID', + 23: 'CPG_PERFWINDOW_SEL_SR', + 24: 'CPG_PERFWINDOW_SEL_QU_EOP', + 25: 'CPG_PERFWINDOW_SEL_QU_STRM', + 26: 'CPG_PERFWINDOW_SEL_QU_PIPE', + 27: 'CPG_PERFWINDOW_SEL_RESERVED1', + 28: 'CPG_PERFWINDOW_SEL_CPC_IC', + 29: 'CPG_PERFWINDOW_SEL_RESERVED2', + 30: 'CPG_PERFWINDOW_SEL_CPG_IC', +} +CPG_PERFWINDOW_SEL_PFP = 0 +CPG_PERFWINDOW_SEL_ME = 1 +CPG_PERFWINDOW_SEL_CE = 2 +CPG_PERFWINDOW_SEL_MES = 3 +CPG_PERFWINDOW_SEL_MEC1 = 4 +CPG_PERFWINDOW_SEL_MEC2 = 5 +CPG_PERFWINDOW_SEL_DFY = 6 +CPG_PERFWINDOW_SEL_DMA = 7 +CPG_PERFWINDOW_SEL_SHADOW = 8 +CPG_PERFWINDOW_SEL_RB = 9 +CPG_PERFWINDOW_SEL_CEDMA = 10 +CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 11 +CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 12 +CPG_PERFWINDOW_SEL_PQ1 = 13 +CPG_PERFWINDOW_SEL_PQ2 = 14 +CPG_PERFWINDOW_SEL_PQ3 = 15 +CPG_PERFWINDOW_SEL_MEMWR = 16 +CPG_PERFWINDOW_SEL_MEMRD = 17 +CPG_PERFWINDOW_SEL_VGT0 = 18 +CPG_PERFWINDOW_SEL_VGT1 = 19 +CPG_PERFWINDOW_SEL_APPEND = 20 +CPG_PERFWINDOW_SEL_QURD = 21 +CPG_PERFWINDOW_SEL_DDID = 22 +CPG_PERFWINDOW_SEL_SR = 23 +CPG_PERFWINDOW_SEL_QU_EOP = 24 +CPG_PERFWINDOW_SEL_QU_STRM = 25 +CPG_PERFWINDOW_SEL_QU_PIPE = 26 +CPG_PERFWINDOW_SEL_RESERVED1 = 27 +CPG_PERFWINDOW_SEL_CPC_IC = 28 +CPG_PERFWINDOW_SEL_RESERVED2 = 29 +CPG_PERFWINDOW_SEL_CPG_IC = 30 +CPG_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_LATENCY_STATS_SEL' +CPF_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPF_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPF_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPF_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPF_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPF_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPF_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPF_LATENCY_STATS_SEL_READ_MAX', + 7: 'CPF_LATENCY_STATS_SEL_READ_MIN', + 8: 'CPF_LATENCY_STATS_SEL_READ_LAST', + 9: 'CPF_LATENCY_STATS_SEL_INVAL_MAX', + 10: 'CPF_LATENCY_STATS_SEL_INVAL_MIN', + 11: 'CPF_LATENCY_STATS_SEL_INVAL_LAST', +} +CPF_LATENCY_STATS_SEL_XACK_MAX = 0 +CPF_LATENCY_STATS_SEL_XACK_MIN = 1 +CPF_LATENCY_STATS_SEL_XACK_LAST = 2 +CPF_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPF_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPF_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPF_LATENCY_STATS_SEL_READ_MAX = 6 +CPF_LATENCY_STATS_SEL_READ_MIN = 7 +CPF_LATENCY_STATS_SEL_READ_LAST = 8 +CPF_LATENCY_STATS_SEL_INVAL_MAX = 9 +CPF_LATENCY_STATS_SEL_INVAL_MIN = 10 +CPF_LATENCY_STATS_SEL_INVAL_LAST = 11 +CPF_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_LATENCY_STATS_SEL' +CPG_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPG_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPG_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPG_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPG_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPG_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPG_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPG_LATENCY_STATS_SEL_WRITE_MAX', + 7: 'CPG_LATENCY_STATS_SEL_WRITE_MIN', + 8: 'CPG_LATENCY_STATS_SEL_WRITE_LAST', + 9: 'CPG_LATENCY_STATS_SEL_READ_MAX', + 10: 'CPG_LATENCY_STATS_SEL_READ_MIN', + 11: 'CPG_LATENCY_STATS_SEL_READ_LAST', + 12: 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', + 13: 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', + 14: 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', + 15: 'CPG_LATENCY_STATS_SEL_INVAL_MAX', + 16: 'CPG_LATENCY_STATS_SEL_INVAL_MIN', + 17: 'CPG_LATENCY_STATS_SEL_INVAL_LAST', +} +CPG_LATENCY_STATS_SEL_XACK_MAX = 0 +CPG_LATENCY_STATS_SEL_XACK_MIN = 1 +CPG_LATENCY_STATS_SEL_XACK_LAST = 2 +CPG_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPG_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPG_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPG_LATENCY_STATS_SEL_WRITE_MAX = 6 +CPG_LATENCY_STATS_SEL_WRITE_MIN = 7 +CPG_LATENCY_STATS_SEL_WRITE_LAST = 8 +CPG_LATENCY_STATS_SEL_READ_MAX = 9 +CPG_LATENCY_STATS_SEL_READ_MIN = 10 +CPG_LATENCY_STATS_SEL_READ_LAST = 11 +CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 12 +CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 13 +CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 14 +CPG_LATENCY_STATS_SEL_INVAL_MAX = 15 +CPG_LATENCY_STATS_SEL_INVAL_MIN = 16 +CPG_LATENCY_STATS_SEL_INVAL_LAST = 17 +CPG_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPC_LATENCY_STATS_SEL' +CPC_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPC_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPC_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPC_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPC_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPC_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPC_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPC_LATENCY_STATS_SEL_INVAL_MAX', + 7: 'CPC_LATENCY_STATS_SEL_INVAL_MIN', + 8: 'CPC_LATENCY_STATS_SEL_INVAL_LAST', +} +CPC_LATENCY_STATS_SEL_XACK_MAX = 0 +CPC_LATENCY_STATS_SEL_XACK_MIN = 1 +CPC_LATENCY_STATS_SEL_XACK_LAST = 2 +CPC_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPC_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPC_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPC_LATENCY_STATS_SEL_INVAL_MAX = 6 +CPC_LATENCY_STATS_SEL_INVAL_MIN = 7 +CPC_LATENCY_STATS_SEL_INVAL_LAST = 8 +CPC_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_MODE' +CP_DDID_CNTL_MODE__enumvalues = { + 0: 'STALL', + 1: 'OVERRUN', +} +STALL = 0 +OVERRUN = 1 +CP_DDID_CNTL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_SIZE' +CP_DDID_CNTL_SIZE__enumvalues = { + 0: 'SIZE_8K', + 1: 'SIZE_16K', +} +SIZE_8K = 0 +SIZE_16K = 1 +CP_DDID_CNTL_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_VMID_SEL' +CP_DDID_CNTL_VMID_SEL__enumvalues = { + 0: 'DDID_VMID_PIPE', + 1: 'DDID_VMID_CNTL', +} +DDID_VMID_PIPE = 0 +DDID_VMID_CNTL = 1 +CP_DDID_CNTL_VMID_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SX_BLEND_OPT' +SX_BLEND_OPT__enumvalues = { + 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', +} +BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 +BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 +BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 +BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 +BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 +BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 +BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 +BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 +SX_BLEND_OPT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_OPT_COMB_FCN' +SX_OPT_COMB_FCN__enumvalues = { + 0: 'OPT_COMB_NONE', + 1: 'OPT_COMB_ADD', + 2: 'OPT_COMB_SUBTRACT', + 3: 'OPT_COMB_MIN', + 4: 'OPT_COMB_MAX', + 5: 'OPT_COMB_REVSUBTRACT', + 6: 'OPT_COMB_BLEND_DISABLED', + 7: 'OPT_COMB_SAFE_ADD', +} +OPT_COMB_NONE = 0 +OPT_COMB_ADD = 1 +OPT_COMB_SUBTRACT = 2 +OPT_COMB_MIN = 3 +OPT_COMB_MAX = 4 +OPT_COMB_REVSUBTRACT = 5 +OPT_COMB_BLEND_DISABLED = 6 +OPT_COMB_SAFE_ADD = 7 +SX_OPT_COMB_FCN = ctypes.c_uint32 # enum + +# values for enumeration 'SX_DOWNCONVERT_FORMAT' +SX_DOWNCONVERT_FORMAT__enumvalues = { + 0: 'SX_RT_EXPORT_NO_CONVERSION', + 1: 'SX_RT_EXPORT_32_R', + 2: 'SX_RT_EXPORT_32_A', + 3: 'SX_RT_EXPORT_10_11_11', + 4: 'SX_RT_EXPORT_2_10_10_10', + 5: 'SX_RT_EXPORT_8_8_8_8', + 6: 'SX_RT_EXPORT_5_6_5', + 7: 'SX_RT_EXPORT_1_5_5_5', + 8: 'SX_RT_EXPORT_4_4_4_4', + 9: 'SX_RT_EXPORT_16_16_GR', + 10: 'SX_RT_EXPORT_16_16_AR', +} +SX_RT_EXPORT_NO_CONVERSION = 0 +SX_RT_EXPORT_32_R = 1 +SX_RT_EXPORT_32_A = 2 +SX_RT_EXPORT_10_11_11 = 3 +SX_RT_EXPORT_2_10_10_10 = 4 +SX_RT_EXPORT_8_8_8_8 = 5 +SX_RT_EXPORT_5_6_5 = 6 +SX_RT_EXPORT_1_5_5_5 = 7 +SX_RT_EXPORT_4_4_4_4 = 8 +SX_RT_EXPORT_16_16_GR = 9 +SX_RT_EXPORT_16_16_AR = 10 +SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_PERFCOUNTER_VALS' +SX_PERFCOUNTER_VALS__enumvalues = { + 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', + 1: 'SX_PERF_SEL_PA_REQ', + 2: 'SX_PERF_SEL_PA_POS', + 3: 'SX_PERF_SEL_CLOCK', + 4: 'SX_PERF_SEL_GATE_EN1', + 5: 'SX_PERF_SEL_GATE_EN2', + 6: 'SX_PERF_SEL_GATE_EN3', + 7: 'SX_PERF_SEL_GATE_EN4', + 8: 'SX_PERF_SEL_SH_POS_STARVE', + 9: 'SX_PERF_SEL_SH_COLOR_STARVE', + 10: 'SX_PERF_SEL_SH_POS_STALL', + 11: 'SX_PERF_SEL_SH_COLOR_STALL', + 12: 'SX_PERF_SEL_DB0_PIXELS', + 13: 'SX_PERF_SEL_DB0_HALF_QUADS', + 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', + 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', + 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', + 17: 'SX_PERF_SEL_DB1_PIXELS', + 18: 'SX_PERF_SEL_DB1_HALF_QUADS', + 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', + 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', + 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', + 22: 'SX_PERF_SEL_DB2_PIXELS', + 23: 'SX_PERF_SEL_DB2_HALF_QUADS', + 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', + 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', + 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', + 27: 'SX_PERF_SEL_DB3_PIXELS', + 28: 'SX_PERF_SEL_DB3_HALF_QUADS', + 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', + 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', + 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', + 32: 'SX_PERF_SEL_COL_BUSY', + 33: 'SX_PERF_SEL_POS_BUSY', + 34: 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', + 35: 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS', + 36: 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST', + 37: 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC', + 38: 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS', + 39: 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS', + 40: 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS', + 41: 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST', + 42: 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC', + 43: 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS', + 44: 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS', + 45: 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS', + 46: 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST', + 47: 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC', + 48: 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS', + 49: 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS', + 50: 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS', + 51: 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST', + 52: 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC', + 53: 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS', + 54: 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS', + 55: 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS', + 56: 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST', + 57: 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC', + 58: 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS', + 59: 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS', + 60: 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS', + 61: 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST', + 62: 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC', + 63: 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS', + 64: 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS', + 65: 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS', + 66: 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST', + 67: 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC', + 68: 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS', + 69: 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS', + 70: 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS', + 71: 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST', + 72: 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC', + 73: 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', + 74: 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS', + 75: 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', + 76: 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS', + 77: 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST', + 78: 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC', + 79: 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS', + 80: 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS', + 81: 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS', + 82: 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST', + 83: 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC', + 84: 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS', + 85: 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS', + 86: 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS', + 87: 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST', + 88: 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC', + 89: 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS', + 90: 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS', + 91: 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS', + 92: 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST', + 93: 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC', + 94: 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS', + 95: 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS', + 96: 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS', + 97: 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST', + 98: 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC', + 99: 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS', + 100: 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS', + 101: 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS', + 102: 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST', + 103: 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC', + 104: 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS', + 105: 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS', + 106: 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS', + 107: 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST', + 108: 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC', + 109: 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS', + 110: 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS', + 111: 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS', + 112: 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST', + 113: 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC', + 114: 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', + 115: 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS', + 116: 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', + 117: 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS', + 118: 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST', + 119: 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC', + 120: 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS', + 121: 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS', + 122: 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS', + 123: 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST', + 124: 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC', + 125: 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS', + 126: 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS', + 127: 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS', + 128: 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST', + 129: 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC', + 130: 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS', + 131: 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS', + 132: 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS', + 133: 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST', + 134: 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC', + 135: 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS', + 136: 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS', + 137: 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS', + 138: 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST', + 139: 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC', + 140: 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS', + 141: 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS', + 142: 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS', + 143: 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST', + 144: 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC', + 145: 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS', + 146: 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS', + 147: 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS', + 148: 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST', + 149: 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC', + 150: 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS', + 151: 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS', + 152: 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS', + 153: 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST', + 154: 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC', + 155: 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', + 156: 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS', + 157: 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', + 158: 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS', + 159: 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST', + 160: 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC', + 161: 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS', + 162: 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS', + 163: 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS', + 164: 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST', + 165: 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC', + 166: 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS', + 167: 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS', + 168: 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS', + 169: 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST', + 170: 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC', + 171: 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS', + 172: 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS', + 173: 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS', + 174: 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST', + 175: 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC', + 176: 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS', + 177: 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS', + 178: 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS', + 179: 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST', + 180: 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC', + 181: 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS', + 182: 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS', + 183: 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS', + 184: 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST', + 185: 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC', + 186: 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS', + 187: 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS', + 188: 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS', + 189: 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST', + 190: 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC', + 191: 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS', + 192: 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS', + 193: 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS', + 194: 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST', + 195: 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC', + 196: 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', + 197: 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS', + 198: 'SX_PERF_SEL_PA_REQ_LATENCY', + 199: 'SX_PERF_SEL_POS_SCBD_STALL', + 200: 'SX_PERF_SEL_COL_SCBD_STALL', + 201: 'SX_PERF_SEL_CLOCK_DROP_STALL', + 202: 'SX_PERF_SEL_GATE_EN5', + 203: 'SX_PERF_SEL_GATE_EN6', + 204: 'SX_PERF_SEL_DB0_SIZE', + 205: 'SX_PERF_SEL_DB1_SIZE', + 206: 'SX_PERF_SEL_DB2_SIZE', + 207: 'SX_PERF_SEL_DB3_SIZE', + 208: 'SX_PERF_SEL_SPLITMODE', + 209: 'SX_PERF_SEL_COL_SCBD0_STALL', + 210: 'SX_PERF_SEL_COL_SCBD1_STALL', + 211: 'SX_PERF_SEL_IDX_STALL_CYCLES', + 212: 'SX_PERF_SEL_IDX_IDLE_CYCLES', + 213: 'SX_PERF_SEL_IDX_REQ', + 214: 'SX_PERF_SEL_IDX_RET', + 215: 'SX_PERF_SEL_IDX_REQ_LATENCY', + 216: 'SX_PERF_SEL_IDX_SCBD_STALL', + 217: 'SX_PERF_SEL_GATE_EN7', + 218: 'SX_PERF_SEL_GATE_EN8', + 219: 'SX_PERF_SEL_SH_IDX_STARVE', + 220: 'SX_PERF_SEL_IDX_BUSY', +} +SX_PERF_SEL_PA_IDLE_CYCLES = 0 +SX_PERF_SEL_PA_REQ = 1 +SX_PERF_SEL_PA_POS = 2 +SX_PERF_SEL_CLOCK = 3 +SX_PERF_SEL_GATE_EN1 = 4 +SX_PERF_SEL_GATE_EN2 = 5 +SX_PERF_SEL_GATE_EN3 = 6 +SX_PERF_SEL_GATE_EN4 = 7 +SX_PERF_SEL_SH_POS_STARVE = 8 +SX_PERF_SEL_SH_COLOR_STARVE = 9 +SX_PERF_SEL_SH_POS_STALL = 10 +SX_PERF_SEL_SH_COLOR_STALL = 11 +SX_PERF_SEL_DB0_PIXELS = 12 +SX_PERF_SEL_DB0_HALF_QUADS = 13 +SX_PERF_SEL_DB0_PIXEL_STALL = 14 +SX_PERF_SEL_DB0_PIXEL_IDLE = 15 +SX_PERF_SEL_DB0_PRED_PIXELS = 16 +SX_PERF_SEL_DB1_PIXELS = 17 +SX_PERF_SEL_DB1_HALF_QUADS = 18 +SX_PERF_SEL_DB1_PIXEL_STALL = 19 +SX_PERF_SEL_DB1_PIXEL_IDLE = 20 +SX_PERF_SEL_DB1_PRED_PIXELS = 21 +SX_PERF_SEL_DB2_PIXELS = 22 +SX_PERF_SEL_DB2_HALF_QUADS = 23 +SX_PERF_SEL_DB2_PIXEL_STALL = 24 +SX_PERF_SEL_DB2_PIXEL_IDLE = 25 +SX_PERF_SEL_DB2_PRED_PIXELS = 26 +SX_PERF_SEL_DB3_PIXELS = 27 +SX_PERF_SEL_DB3_HALF_QUADS = 28 +SX_PERF_SEL_DB3_PIXEL_STALL = 29 +SX_PERF_SEL_DB3_PIXEL_IDLE = 30 +SX_PERF_SEL_DB3_PRED_PIXELS = 31 +SX_PERF_SEL_COL_BUSY = 32 +SX_PERF_SEL_POS_BUSY = 33 +SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 34 +SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 35 +SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 36 +SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 37 +SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 38 +SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 39 +SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 40 +SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 41 +SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 42 +SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 43 +SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 44 +SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 45 +SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 46 +SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 47 +SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 48 +SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 49 +SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 50 +SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 51 +SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 52 +SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 53 +SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 54 +SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 55 +SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 56 +SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 57 +SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 58 +SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 59 +SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 60 +SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 61 +SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 62 +SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 63 +SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 64 +SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 65 +SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 66 +SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 67 +SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 68 +SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 69 +SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 70 +SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 71 +SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 72 +SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 73 +SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 74 +SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 75 +SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 76 +SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 77 +SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 78 +SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 79 +SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 80 +SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 81 +SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 82 +SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 83 +SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 84 +SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 85 +SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 86 +SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 87 +SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 88 +SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 89 +SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 90 +SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 91 +SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 92 +SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 93 +SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 94 +SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 95 +SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 96 +SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 97 +SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 98 +SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 99 +SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 100 +SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 101 +SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 102 +SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 103 +SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 104 +SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 105 +SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 106 +SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 107 +SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 108 +SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 109 +SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 110 +SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 111 +SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 112 +SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 113 +SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 114 +SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 115 +SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 116 +SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 117 +SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 118 +SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 119 +SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 120 +SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 121 +SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 122 +SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 123 +SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 124 +SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 125 +SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 126 +SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 127 +SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 128 +SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 129 +SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 130 +SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 131 +SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 132 +SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 133 +SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 134 +SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 135 +SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 136 +SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 137 +SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 138 +SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 139 +SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 140 +SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 141 +SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 142 +SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 143 +SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 144 +SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 145 +SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 146 +SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 147 +SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 148 +SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 149 +SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 150 +SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 151 +SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 152 +SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 153 +SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 154 +SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 155 +SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 156 +SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 157 +SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 158 +SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 159 +SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 160 +SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 161 +SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 162 +SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 163 +SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 164 +SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 165 +SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 166 +SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 167 +SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 168 +SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 169 +SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 170 +SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 171 +SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 172 +SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 173 +SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 174 +SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 175 +SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 176 +SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 177 +SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 178 +SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 179 +SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 180 +SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 181 +SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 182 +SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 183 +SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 184 +SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 185 +SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 186 +SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 187 +SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 188 +SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 189 +SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 190 +SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 191 +SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 192 +SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 193 +SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 194 +SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 195 +SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 196 +SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 197 +SX_PERF_SEL_PA_REQ_LATENCY = 198 +SX_PERF_SEL_POS_SCBD_STALL = 199 +SX_PERF_SEL_COL_SCBD_STALL = 200 +SX_PERF_SEL_CLOCK_DROP_STALL = 201 +SX_PERF_SEL_GATE_EN5 = 202 +SX_PERF_SEL_GATE_EN6 = 203 +SX_PERF_SEL_DB0_SIZE = 204 +SX_PERF_SEL_DB1_SIZE = 205 +SX_PERF_SEL_DB2_SIZE = 206 +SX_PERF_SEL_DB3_SIZE = 207 +SX_PERF_SEL_SPLITMODE = 208 +SX_PERF_SEL_COL_SCBD0_STALL = 209 +SX_PERF_SEL_COL_SCBD1_STALL = 210 +SX_PERF_SEL_IDX_STALL_CYCLES = 211 +SX_PERF_SEL_IDX_IDLE_CYCLES = 212 +SX_PERF_SEL_IDX_REQ = 213 +SX_PERF_SEL_IDX_RET = 214 +SX_PERF_SEL_IDX_REQ_LATENCY = 215 +SX_PERF_SEL_IDX_SCBD_STALL = 216 +SX_PERF_SEL_GATE_EN7 = 217 +SX_PERF_SEL_GATE_EN8 = 218 +SX_PERF_SEL_SH_IDX_STARVE = 219 +SX_PERF_SEL_IDX_BUSY = 220 +SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum + +# values for enumeration 'ForceControl' +ForceControl__enumvalues = { + 0: 'FORCE_OFF', + 1: 'FORCE_ENABLE', + 2: 'FORCE_DISABLE', + 3: 'FORCE_RESERVED', +} +FORCE_OFF = 0 +FORCE_ENABLE = 1 +FORCE_DISABLE = 2 +FORCE_RESERVED = 3 +ForceControl = ctypes.c_uint32 # enum + +# values for enumeration 'ZSamplePosition' +ZSamplePosition__enumvalues = { + 0: 'Z_SAMPLE_CENTER', + 1: 'Z_SAMPLE_CENTROID', +} +Z_SAMPLE_CENTER = 0 +Z_SAMPLE_CENTROID = 1 +ZSamplePosition = ctypes.c_uint32 # enum + +# values for enumeration 'ZOrder' +ZOrder__enumvalues = { + 0: 'LATE_Z', + 1: 'EARLY_Z_THEN_LATE_Z', + 2: 'RE_Z', + 3: 'EARLY_Z_THEN_RE_Z', +} +LATE_Z = 0 +EARLY_Z_THEN_LATE_Z = 1 +RE_Z = 2 +EARLY_Z_THEN_RE_Z = 3 +ZOrder = ctypes.c_uint32 # enum + +# values for enumeration 'ZpassControl' +ZpassControl__enumvalues = { + 0: 'ZPASS_DISABLE', + 1: 'ZPASS_SAMPLES', + 2: 'ZPASS_PIXELS', +} +ZPASS_DISABLE = 0 +ZPASS_SAMPLES = 1 +ZPASS_PIXELS = 2 +ZpassControl = ctypes.c_uint32 # enum + +# values for enumeration 'ZModeForce' +ZModeForce__enumvalues = { + 0: 'NO_FORCE', + 1: 'FORCE_EARLY_Z', + 2: 'FORCE_LATE_Z', + 3: 'FORCE_RE_Z', +} +NO_FORCE = 0 +FORCE_EARLY_Z = 1 +FORCE_LATE_Z = 2 +FORCE_RE_Z = 3 +ZModeForce = ctypes.c_uint32 # enum + +# values for enumeration 'ZLimitSumm' +ZLimitSumm__enumvalues = { + 0: 'FORCE_SUMM_OFF', + 1: 'FORCE_SUMM_MINZ', + 2: 'FORCE_SUMM_MAXZ', + 3: 'FORCE_SUMM_BOTH', +} +FORCE_SUMM_OFF = 0 +FORCE_SUMM_MINZ = 1 +FORCE_SUMM_MAXZ = 2 +FORCE_SUMM_BOTH = 3 +ZLimitSumm = ctypes.c_uint32 # enum + +# values for enumeration 'CompareFrag' +CompareFrag__enumvalues = { + 0: 'FRAG_NEVER', + 1: 'FRAG_LESS', + 2: 'FRAG_EQUAL', + 3: 'FRAG_LEQUAL', + 4: 'FRAG_GREATER', + 5: 'FRAG_NOTEQUAL', + 6: 'FRAG_GEQUAL', + 7: 'FRAG_ALWAYS', +} +FRAG_NEVER = 0 +FRAG_LESS = 1 +FRAG_EQUAL = 2 +FRAG_LEQUAL = 3 +FRAG_GREATER = 4 +FRAG_NOTEQUAL = 5 +FRAG_GEQUAL = 6 +FRAG_ALWAYS = 7 +CompareFrag = ctypes.c_uint32 # enum + +# values for enumeration 'StencilOp' +StencilOp__enumvalues = { + 0: 'STENCIL_KEEP', + 1: 'STENCIL_ZERO', + 2: 'STENCIL_ONES', + 3: 'STENCIL_REPLACE_TEST', + 4: 'STENCIL_REPLACE_OP', + 5: 'STENCIL_ADD_CLAMP', + 6: 'STENCIL_SUB_CLAMP', + 7: 'STENCIL_INVERT', + 8: 'STENCIL_ADD_WRAP', + 9: 'STENCIL_SUB_WRAP', + 10: 'STENCIL_AND', + 11: 'STENCIL_OR', + 12: 'STENCIL_XOR', + 13: 'STENCIL_NAND', + 14: 'STENCIL_NOR', + 15: 'STENCIL_XNOR', +} +STENCIL_KEEP = 0 +STENCIL_ZERO = 1 +STENCIL_ONES = 2 +STENCIL_REPLACE_TEST = 3 +STENCIL_REPLACE_OP = 4 +STENCIL_ADD_CLAMP = 5 +STENCIL_SUB_CLAMP = 6 +STENCIL_INVERT = 7 +STENCIL_ADD_WRAP = 8 +STENCIL_SUB_WRAP = 9 +STENCIL_AND = 10 +STENCIL_OR = 11 +STENCIL_XOR = 12 +STENCIL_NAND = 13 +STENCIL_NOR = 14 +STENCIL_XNOR = 15 +StencilOp = ctypes.c_uint32 # enum + +# values for enumeration 'ConservativeZExport' +ConservativeZExport__enumvalues = { + 0: 'EXPORT_ANY_Z', + 1: 'EXPORT_LESS_THAN_Z', + 2: 'EXPORT_GREATER_THAN_Z', + 3: 'EXPORT_RESERVED', +} +EXPORT_ANY_Z = 0 +EXPORT_LESS_THAN_Z = 1 +EXPORT_GREATER_THAN_Z = 2 +EXPORT_RESERVED = 3 +ConservativeZExport = ctypes.c_uint32 # enum + +# values for enumeration 'DbPSLControl' +DbPSLControl__enumvalues = { + 0: 'PSLC_AUTO', + 1: 'PSLC_ON_HANG_ONLY', + 2: 'PSLC_ASAP', + 3: 'PSLC_COUNTDOWN', +} +PSLC_AUTO = 0 +PSLC_ON_HANG_ONLY = 1 +PSLC_ASAP = 2 +PSLC_COUNTDOWN = 3 +DbPSLControl = ctypes.c_uint32 # enum + +# values for enumeration 'DbPRTFaultBehavior' +DbPRTFaultBehavior__enumvalues = { + 0: 'FAULT_ZERO', + 1: 'FAULT_ONE', + 2: 'FAULT_FAIL', + 3: 'FAULT_PASS', +} +FAULT_ZERO = 0 +FAULT_ONE = 1 +FAULT_FAIL = 2 +FAULT_PASS = 3 +DbPRTFaultBehavior = ctypes.c_uint32 # enum + +# values for enumeration 'PerfCounter_Vals' +PerfCounter_Vals__enumvalues = { + 0: 'DB_PERF_SEL_SC_DB_tile_sends', + 1: 'DB_PERF_SEL_SC_DB_tile_busy', + 2: 'DB_PERF_SEL_SC_DB_tile_stalls', + 3: 'DB_PERF_SEL_SC_DB_tile_events', + 4: 'DB_PERF_SEL_SC_DB_tile_tiles', + 5: 'DB_PERF_SEL_SC_DB_tile_covered', + 6: 'DB_PERF_SEL_hiz_tc_read_starved', + 7: 'DB_PERF_SEL_hiz_tc_write_stall', + 8: 'DB_PERF_SEL_hiz_tile_culled', + 9: 'DB_PERF_SEL_his_tile_culled', + 10: 'DB_PERF_SEL_DB_SC_tile_sends', + 11: 'DB_PERF_SEL_DB_SC_tile_busy', + 12: 'DB_PERF_SEL_DB_SC_tile_stalls', + 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 14: 'DB_PERF_SEL_DB_SC_tile_tiles', + 15: 'DB_PERF_SEL_DB_SC_tile_culled', + 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', + 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 23: 'DB_PERF_SEL_SC_DB_quad_sends', + 24: 'DB_PERF_SEL_SC_DB_quad_busy', + 25: 'DB_PERF_SEL_SC_DB_quad_squads', + 26: 'DB_PERF_SEL_SC_DB_quad_tiles', + 27: 'DB_PERF_SEL_SC_DB_quad_pixels', + 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 29: 'DB_PERF_SEL_DB_SC_quad_sends', + 30: 'DB_PERF_SEL_DB_SC_quad_busy', + 31: 'DB_PERF_SEL_DB_SC_quad_stalls', + 32: 'DB_PERF_SEL_DB_SC_quad_tiles', + 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', + 34: 'DB_PERF_SEL_DB_CB_tile_sends', + 35: 'DB_PERF_SEL_DB_CB_tile_busy', + 36: 'DB_PERF_SEL_DB_CB_tile_stalls', + 37: 'DB_PERF_SEL_SX_DB_quad_sends', + 38: 'DB_PERF_SEL_SX_DB_quad_busy', + 39: 'DB_PERF_SEL_SX_DB_quad_stalls', + 40: 'DB_PERF_SEL_SX_DB_quad_quads', + 41: 'DB_PERF_SEL_SX_DB_quad_pixels', + 42: 'DB_PERF_SEL_SX_DB_quad_exports', + 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', + 44: 'DB_PERF_SEL_DB_CB_lquad_sends', + 45: 'DB_PERF_SEL_DB_CB_lquad_busy', + 46: 'DB_PERF_SEL_DB_CB_lquad_stalls', + 47: 'DB_PERF_SEL_DB_CB_lquad_quads', + 48: 'DB_PERF_SEL_tile_rd_sends', + 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 50: 'DB_PERF_SEL_quad_rd_sends', + 51: 'DB_PERF_SEL_quad_rd_busy', + 52: 'DB_PERF_SEL_quad_rd_mi_stall', + 53: 'DB_PERF_SEL_quad_rd_rw_collision', + 54: 'DB_PERF_SEL_quad_rd_tag_stall', + 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', + 56: 'DB_PERF_SEL_quad_rd_panic', + 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 58: 'DB_PERF_SEL_quad_rdret_sends', + 59: 'DB_PERF_SEL_quad_rdret_busy', + 60: 'DB_PERF_SEL_tile_wr_sends', + 61: 'DB_PERF_SEL_tile_wr_acks', + 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 63: 'DB_PERF_SEL_quad_wr_sends', + 64: 'DB_PERF_SEL_quad_wr_busy', + 65: 'DB_PERF_SEL_quad_wr_mi_stall', + 66: 'DB_PERF_SEL_quad_wr_coherency_stall', + 67: 'DB_PERF_SEL_quad_wr_acks', + 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 69: 'DB_PERF_SEL_Tile_Cache_misses', + 70: 'DB_PERF_SEL_Tile_Cache_hits', + 71: 'DB_PERF_SEL_Tile_Cache_flushes', + 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', + 73: 'DB_PERF_SEL_Tile_Cache_starves', + 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 75: 'DB_PERF_SEL_tcp_dispatcher_reads', + 76: 'DB_PERF_SEL_tcp_prefetcher_reads', + 77: 'DB_PERF_SEL_tcp_preloader_reads', + 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', + 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', + 80: 'DB_PERF_SEL_tcp_preloader_flushes', + 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', + 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 95: 'DB_PERF_SEL_Stencil_Cache_misses', + 96: 'DB_PERF_SEL_Stencil_Cache_hits', + 97: 'DB_PERF_SEL_Stencil_Cache_flushes', + 98: 'DB_PERF_SEL_Stencil_Cache_starves', + 99: 'DB_PERF_SEL_Stencil_Cache_frees', + 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', + 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', + 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', + 108: 'DB_PERF_SEL_Z_Cache_frees', + 109: 'DB_PERF_SEL_Plane_Cache_misses', + 110: 'DB_PERF_SEL_Plane_Cache_hits', + 111: 'DB_PERF_SEL_Plane_Cache_flushes', + 112: 'DB_PERF_SEL_Plane_Cache_starves', + 113: 'DB_PERF_SEL_Plane_Cache_frees', + 114: 'DB_PERF_SEL_flush_expanded_stencil', + 115: 'DB_PERF_SEL_flush_compressed_stencil', + 116: 'DB_PERF_SEL_flush_single_stencil', + 117: 'DB_PERF_SEL_planes_flushed', + 118: 'DB_PERF_SEL_flush_1plane', + 119: 'DB_PERF_SEL_flush_2plane', + 120: 'DB_PERF_SEL_flush_3plane', + 121: 'DB_PERF_SEL_flush_4plane', + 122: 'DB_PERF_SEL_flush_5plane', + 123: 'DB_PERF_SEL_flush_6plane', + 124: 'DB_PERF_SEL_flush_7plane', + 125: 'DB_PERF_SEL_flush_8plane', + 126: 'DB_PERF_SEL_flush_9plane', + 127: 'DB_PERF_SEL_flush_10plane', + 128: 'DB_PERF_SEL_flush_11plane', + 129: 'DB_PERF_SEL_flush_12plane', + 130: 'DB_PERF_SEL_flush_13plane', + 131: 'DB_PERF_SEL_flush_14plane', + 132: 'DB_PERF_SEL_flush_15plane', + 133: 'DB_PERF_SEL_flush_16plane', + 134: 'DB_PERF_SEL_flush_expanded_z', + 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 137: 'DB_PERF_SEL_dk_tile_sends', + 138: 'DB_PERF_SEL_dk_tile_busy', + 139: 'DB_PERF_SEL_dk_tile_quad_starves', + 140: 'DB_PERF_SEL_dk_tile_stalls', + 141: 'DB_PERF_SEL_dk_squad_sends', + 142: 'DB_PERF_SEL_dk_squad_busy', + 143: 'DB_PERF_SEL_dk_squad_stalls', + 144: 'DB_PERF_SEL_Op_Pipe_Busy', + 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 146: 'DB_PERF_SEL_qc_busy', + 147: 'DB_PERF_SEL_qc_xfc', + 148: 'DB_PERF_SEL_qc_conflicts', + 149: 'DB_PERF_SEL_qc_full_stall', + 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', + 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', + 153: 'DB_PERF_SEL_tl_busy', + 154: 'DB_PERF_SEL_tl_dtc_read_starved', + 155: 'DB_PERF_SEL_tl_z_fetch_stall', + 156: 'DB_PERF_SEL_tl_stencil_stall', + 157: 'DB_PERF_SEL_tl_z_decompress_stall', + 158: 'DB_PERF_SEL_tl_stencil_locked_stall', + 159: 'DB_PERF_SEL_tl_events', + 160: 'DB_PERF_SEL_tl_summarize_squads', + 161: 'DB_PERF_SEL_tl_flush_expand_squads', + 162: 'DB_PERF_SEL_tl_expand_squads', + 163: 'DB_PERF_SEL_tl_preZ_squads', + 164: 'DB_PERF_SEL_tl_postZ_squads', + 165: 'DB_PERF_SEL_tl_preZ_noop_squads', + 166: 'DB_PERF_SEL_tl_postZ_noop_squads', + 167: 'DB_PERF_SEL_tl_tile_ops', + 168: 'DB_PERF_SEL_tl_in_xfc', + 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 170: 'DB_PERF_SEL_tl_in_fast_z_stall', + 171: 'DB_PERF_SEL_tl_out_xfc', + 172: 'DB_PERF_SEL_tl_out_squads', + 173: 'DB_PERF_SEL_zf_plane_multicycle', + 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', + 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', + 180: 'DB_PERF_SEL_ts_tc_update_stall', + 181: 'DB_PERF_SEL_sc_kick_start', + 182: 'DB_PERF_SEL_sc_kick_end', + 183: 'DB_PERF_SEL_clock_reg_active', + 184: 'DB_PERF_SEL_clock_main_active', + 185: 'DB_PERF_SEL_clock_mem_export_active', + 186: 'DB_PERF_SEL_esr_ps_out_busy', + 187: 'DB_PERF_SEL_esr_ps_lqf_busy', + 188: 'DB_PERF_SEL_esr_ps_lqf_stall', + 189: 'DB_PERF_SEL_etr_out_send', + 190: 'DB_PERF_SEL_etr_out_busy', + 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 192: 'DB_PERF_SEL_etr_out_cb_tile_stall', + 193: 'DB_PERF_SEL_etr_out_esr_stall', + 194: 'DB_PERF_SEL_esr_ps_sqq_busy', + 195: 'DB_PERF_SEL_esr_ps_sqq_stall', + 196: 'DB_PERF_SEL_esr_eot_fwd_busy', + 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 198: 'DB_PERF_SEL_esr_eot_fwd_forward', + 199: 'DB_PERF_SEL_esr_sqq_zi_busy', + 200: 'DB_PERF_SEL_esr_sqq_zi_stall', + 201: 'DB_PERF_SEL_postzl_sq_pt_busy', + 202: 'DB_PERF_SEL_postzl_sq_pt_stall', + 203: 'DB_PERF_SEL_postzl_se_busy', + 204: 'DB_PERF_SEL_postzl_se_stall', + 205: 'DB_PERF_SEL_postzl_partial_launch', + 206: 'DB_PERF_SEL_postzl_full_launch', + 207: 'DB_PERF_SEL_postzl_partial_waiting', + 208: 'DB_PERF_SEL_postzl_tile_mem_stall', + 209: 'DB_PERF_SEL_postzl_tile_init_stall', + 210: 'DB_PERF_SEL_prezl_tile_mem_stall', + 211: 'DB_PERF_SEL_prezl_tile_init_stall', + 212: 'DB_PERF_SEL_dtt_sm_clash_stall', + 213: 'DB_PERF_SEL_dtt_sm_slot_stall', + 214: 'DB_PERF_SEL_dtt_sm_miss_stall', + 215: 'DB_PERF_SEL_mi_rdreq_busy', + 216: 'DB_PERF_SEL_mi_rdreq_stall', + 217: 'DB_PERF_SEL_mi_wrreq_busy', + 218: 'DB_PERF_SEL_mi_wrreq_stall', + 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 220: 'DB_PERF_SEL_dkg_tile_rate_tile', + 221: 'DB_PERF_SEL_prezl_src_in_sends', + 222: 'DB_PERF_SEL_prezl_src_in_stall', + 223: 'DB_PERF_SEL_prezl_src_in_squads', + 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', + 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 227: 'DB_PERF_SEL_prezl_src_out_stall', + 228: 'DB_PERF_SEL_postzl_src_in_sends', + 229: 'DB_PERF_SEL_postzl_src_in_stall', + 230: 'DB_PERF_SEL_postzl_src_in_squads', + 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', + 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 234: 'DB_PERF_SEL_postzl_src_out_stall', + 235: 'DB_PERF_SEL_esr_ps_src_in_sends', + 236: 'DB_PERF_SEL_esr_ps_src_in_stall', + 237: 'DB_PERF_SEL_esr_ps_src_in_squads', + 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 242: 'DB_PERF_SEL_esr_ps_src_out_stall', + 243: 'DB_PERF_SEL_depth_bounds_tile_culled', + 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 246: 'DB_PERF_SEL_flush_compressed', + 247: 'DB_PERF_SEL_flush_plane_le4', + 248: 'DB_PERF_SEL_tiles_z_fully_summarized', + 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', + 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', + 256: 'DB_PERF_SEL_di_dt_stall', + 257: 'DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke', + 258: 'DB_PERF_SEL_DB_SC_s_tile_rate', + 259: 'DB_PERF_SEL_DB_SC_c_tile_rate', + 260: 'DB_PERF_SEL_DB_SC_z_tile_rate', + 261: 'Spare_261', + 262: 'DB_PERF_SEL_DB_CB_lquad_export_quads', + 263: 'DB_PERF_SEL_DB_CB_lquad_double_format', + 264: 'DB_PERF_SEL_DB_CB_lquad_fast_format', + 265: 'DB_PERF_SEL_DB_CB_lquad_slow_format', + 266: 'DB_PERF_SEL_CB_DB_rdreq_sends', + 267: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 268: 'DB_PERF_SEL_CB_DB_wrreq_sends', + 269: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 270: 'DB_PERF_SEL_DB_CB_rdret_ack', + 271: 'DB_PERF_SEL_DB_CB_rdret_nack', + 272: 'DB_PERF_SEL_DB_CB_wrret_ack', + 273: 'DB_PERF_SEL_DB_CB_wrret_nack', + 274: 'DB_PERF_SEL_DFSM_Stall_opmode_change', + 275: 'DB_PERF_SEL_DFSM_Stall_cam_fifo', + 276: 'DB_PERF_SEL_DFSM_Stall_bypass_fifo', + 277: 'DB_PERF_SEL_DFSM_Stall_retained_tile_fifo', + 278: 'DB_PERF_SEL_DFSM_Stall_control_fifo', + 279: 'DB_PERF_SEL_DFSM_Stall_overflow_counter', + 280: 'DB_PERF_SEL_DFSM_Stall_pops_stall_overflow', + 281: 'DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush', + 282: 'DB_PERF_SEL_DFSM_Stall_middle_output', + 283: 'DB_PERF_SEL_DFSM_Stall_stalling_general', + 284: 'Spare_285', + 285: 'Spare_286', + 286: 'DB_PERF_SEL_DFSM_prez_killed_squad', + 287: 'DB_PERF_SEL_DFSM_squads_in', + 288: 'DB_PERF_SEL_DFSM_full_cleared_squads_out', + 289: 'DB_PERF_SEL_DFSM_quads_in', + 290: 'DB_PERF_SEL_DFSM_fully_cleared_quads_out', + 291: 'DB_PERF_SEL_DFSM_lit_pixels_in', + 292: 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out', + 293: 'DB_PERF_SEL_DFSM_lit_samples_in', + 294: 'DB_PERF_SEL_DFSM_lit_samples_out', + 295: 'DB_PERF_SEL_DFSM_evicted_tiles_above_watermark', + 296: 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream', + 297: 'DB_PERF_SEL_DFSM_stalled_by_downstream', + 298: 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark', + 299: 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow', + 300: 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO', + 301: 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark', + 302: 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', + 303: 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', + 304: 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', + 305: 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', + 306: 'DB_PERF_SEL_unmapped_z_tile_culled', + 307: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', + 308: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', + 309: 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', + 310: 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', + 311: 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', + 312: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', + 313: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', + 314: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', + 315: 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', + 316: 'DB_PERF_SEL_DB_CB_context_dones', + 317: 'DB_PERF_SEL_DB_CB_eop_dones', + 318: 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', + 319: 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', + 320: 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', + 321: 'DB_PERF_SEL_SC_DB_tile_backface', + 322: 'DB_PERF_SEL_SC_DB_quad_quads', + 323: 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', + 324: 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', + 325: 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', + 326: 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', + 327: 'DB_PERF_SEL_DFSM_Flush_flushabit', + 328: 'DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo', + 329: 'DB_PERF_SEL_DFSM_Flush_flushabit_passthrough', + 330: 'DB_PERF_SEL_DFSM_Flush_flushabit_forceflush', + 331: 'DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull', + 332: 'DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark', + 333: 'DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling', + 334: 'DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark', + 335: 'DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark', + 336: 'DB_PERF_SEL_DFSM_Flush_flushall', + 337: 'DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush', + 338: 'DB_PERF_SEL_DFSM_Flush_flushall_opmodechange', + 339: 'DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange', + 340: 'DB_PERF_SEL_DFSM_Flush_flushall_watchdog', + 341: 'DB_PERF_SEL_DB_SC_quad_double_quad', + 342: 'DB_PERF_SEL_SX_DB_quad_export_quads', + 343: 'DB_PERF_SEL_SX_DB_quad_double_format', + 344: 'DB_PERF_SEL_SX_DB_quad_fast_format', + 345: 'DB_PERF_SEL_SX_DB_quad_slow_format', +} +DB_PERF_SEL_SC_DB_tile_sends = 0 +DB_PERF_SEL_SC_DB_tile_busy = 1 +DB_PERF_SEL_SC_DB_tile_stalls = 2 +DB_PERF_SEL_SC_DB_tile_events = 3 +DB_PERF_SEL_SC_DB_tile_tiles = 4 +DB_PERF_SEL_SC_DB_tile_covered = 5 +DB_PERF_SEL_hiz_tc_read_starved = 6 +DB_PERF_SEL_hiz_tc_write_stall = 7 +DB_PERF_SEL_hiz_tile_culled = 8 +DB_PERF_SEL_his_tile_culled = 9 +DB_PERF_SEL_DB_SC_tile_sends = 10 +DB_PERF_SEL_DB_SC_tile_busy = 11 +DB_PERF_SEL_DB_SC_tile_stalls = 12 +DB_PERF_SEL_DB_SC_tile_df_stalls = 13 +DB_PERF_SEL_DB_SC_tile_tiles = 14 +DB_PERF_SEL_DB_SC_tile_culled = 15 +DB_PERF_SEL_DB_SC_tile_hier_kill = 16 +DB_PERF_SEL_DB_SC_tile_fast_ops = 17 +DB_PERF_SEL_DB_SC_tile_no_ops = 18 +DB_PERF_SEL_DB_SC_tile_tile_rate = 19 +DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 +DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 +DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 +DB_PERF_SEL_SC_DB_quad_sends = 23 +DB_PERF_SEL_SC_DB_quad_busy = 24 +DB_PERF_SEL_SC_DB_quad_squads = 25 +DB_PERF_SEL_SC_DB_quad_tiles = 26 +DB_PERF_SEL_SC_DB_quad_pixels = 27 +DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 +DB_PERF_SEL_DB_SC_quad_sends = 29 +DB_PERF_SEL_DB_SC_quad_busy = 30 +DB_PERF_SEL_DB_SC_quad_stalls = 31 +DB_PERF_SEL_DB_SC_quad_tiles = 32 +DB_PERF_SEL_DB_SC_quad_lit_quad = 33 +DB_PERF_SEL_DB_CB_tile_sends = 34 +DB_PERF_SEL_DB_CB_tile_busy = 35 +DB_PERF_SEL_DB_CB_tile_stalls = 36 +DB_PERF_SEL_SX_DB_quad_sends = 37 +DB_PERF_SEL_SX_DB_quad_busy = 38 +DB_PERF_SEL_SX_DB_quad_stalls = 39 +DB_PERF_SEL_SX_DB_quad_quads = 40 +DB_PERF_SEL_SX_DB_quad_pixels = 41 +DB_PERF_SEL_SX_DB_quad_exports = 42 +DB_PERF_SEL_SH_quads_outstanding_sum = 43 +DB_PERF_SEL_DB_CB_lquad_sends = 44 +DB_PERF_SEL_DB_CB_lquad_busy = 45 +DB_PERF_SEL_DB_CB_lquad_stalls = 46 +DB_PERF_SEL_DB_CB_lquad_quads = 47 +DB_PERF_SEL_tile_rd_sends = 48 +DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 +DB_PERF_SEL_quad_rd_sends = 50 +DB_PERF_SEL_quad_rd_busy = 51 +DB_PERF_SEL_quad_rd_mi_stall = 52 +DB_PERF_SEL_quad_rd_rw_collision = 53 +DB_PERF_SEL_quad_rd_tag_stall = 54 +DB_PERF_SEL_quad_rd_32byte_reqs = 55 +DB_PERF_SEL_quad_rd_panic = 56 +DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 +DB_PERF_SEL_quad_rdret_sends = 58 +DB_PERF_SEL_quad_rdret_busy = 59 +DB_PERF_SEL_tile_wr_sends = 60 +DB_PERF_SEL_tile_wr_acks = 61 +DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 +DB_PERF_SEL_quad_wr_sends = 63 +DB_PERF_SEL_quad_wr_busy = 64 +DB_PERF_SEL_quad_wr_mi_stall = 65 +DB_PERF_SEL_quad_wr_coherency_stall = 66 +DB_PERF_SEL_quad_wr_acks = 67 +DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 +DB_PERF_SEL_Tile_Cache_misses = 69 +DB_PERF_SEL_Tile_Cache_hits = 70 +DB_PERF_SEL_Tile_Cache_flushes = 71 +DB_PERF_SEL_Tile_Cache_surface_stall = 72 +DB_PERF_SEL_Tile_Cache_starves = 73 +DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 +DB_PERF_SEL_tcp_dispatcher_reads = 75 +DB_PERF_SEL_tcp_prefetcher_reads = 76 +DB_PERF_SEL_tcp_preloader_reads = 77 +DB_PERF_SEL_tcp_dispatcher_flushes = 78 +DB_PERF_SEL_tcp_prefetcher_flushes = 79 +DB_PERF_SEL_tcp_preloader_flushes = 80 +DB_PERF_SEL_Depth_Tile_Cache_sends = 81 +DB_PERF_SEL_Depth_Tile_Cache_busy = 82 +DB_PERF_SEL_Depth_Tile_Cache_starves = 83 +DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 +DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 +DB_PERF_SEL_Depth_Tile_Cache_misses = 86 +DB_PERF_SEL_Depth_Tile_Cache_hits = 87 +DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 +DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 +DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 +DB_PERF_SEL_Depth_Tile_Cache_event = 91 +DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 +DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 +DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 +DB_PERF_SEL_Stencil_Cache_misses = 95 +DB_PERF_SEL_Stencil_Cache_hits = 96 +DB_PERF_SEL_Stencil_Cache_flushes = 97 +DB_PERF_SEL_Stencil_Cache_starves = 98 +DB_PERF_SEL_Stencil_Cache_frees = 99 +DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 +DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 +DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 +DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 +DB_PERF_SEL_Z_Cache_pmask_misses = 104 +DB_PERF_SEL_Z_Cache_pmask_hits = 105 +DB_PERF_SEL_Z_Cache_pmask_flushes = 106 +DB_PERF_SEL_Z_Cache_pmask_starves = 107 +DB_PERF_SEL_Z_Cache_frees = 108 +DB_PERF_SEL_Plane_Cache_misses = 109 +DB_PERF_SEL_Plane_Cache_hits = 110 +DB_PERF_SEL_Plane_Cache_flushes = 111 +DB_PERF_SEL_Plane_Cache_starves = 112 +DB_PERF_SEL_Plane_Cache_frees = 113 +DB_PERF_SEL_flush_expanded_stencil = 114 +DB_PERF_SEL_flush_compressed_stencil = 115 +DB_PERF_SEL_flush_single_stencil = 116 +DB_PERF_SEL_planes_flushed = 117 +DB_PERF_SEL_flush_1plane = 118 +DB_PERF_SEL_flush_2plane = 119 +DB_PERF_SEL_flush_3plane = 120 +DB_PERF_SEL_flush_4plane = 121 +DB_PERF_SEL_flush_5plane = 122 +DB_PERF_SEL_flush_6plane = 123 +DB_PERF_SEL_flush_7plane = 124 +DB_PERF_SEL_flush_8plane = 125 +DB_PERF_SEL_flush_9plane = 126 +DB_PERF_SEL_flush_10plane = 127 +DB_PERF_SEL_flush_11plane = 128 +DB_PERF_SEL_flush_12plane = 129 +DB_PERF_SEL_flush_13plane = 130 +DB_PERF_SEL_flush_14plane = 131 +DB_PERF_SEL_flush_15plane = 132 +DB_PERF_SEL_flush_16plane = 133 +DB_PERF_SEL_flush_expanded_z = 134 +DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 +DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 +DB_PERF_SEL_dk_tile_sends = 137 +DB_PERF_SEL_dk_tile_busy = 138 +DB_PERF_SEL_dk_tile_quad_starves = 139 +DB_PERF_SEL_dk_tile_stalls = 140 +DB_PERF_SEL_dk_squad_sends = 141 +DB_PERF_SEL_dk_squad_busy = 142 +DB_PERF_SEL_dk_squad_stalls = 143 +DB_PERF_SEL_Op_Pipe_Busy = 144 +DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 +DB_PERF_SEL_qc_busy = 146 +DB_PERF_SEL_qc_xfc = 147 +DB_PERF_SEL_qc_conflicts = 148 +DB_PERF_SEL_qc_full_stall = 149 +DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 +DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 +DB_PERF_SEL_tsc_insert_summarize_stall = 152 +DB_PERF_SEL_tl_busy = 153 +DB_PERF_SEL_tl_dtc_read_starved = 154 +DB_PERF_SEL_tl_z_fetch_stall = 155 +DB_PERF_SEL_tl_stencil_stall = 156 +DB_PERF_SEL_tl_z_decompress_stall = 157 +DB_PERF_SEL_tl_stencil_locked_stall = 158 +DB_PERF_SEL_tl_events = 159 +DB_PERF_SEL_tl_summarize_squads = 160 +DB_PERF_SEL_tl_flush_expand_squads = 161 +DB_PERF_SEL_tl_expand_squads = 162 +DB_PERF_SEL_tl_preZ_squads = 163 +DB_PERF_SEL_tl_postZ_squads = 164 +DB_PERF_SEL_tl_preZ_noop_squads = 165 +DB_PERF_SEL_tl_postZ_noop_squads = 166 +DB_PERF_SEL_tl_tile_ops = 167 +DB_PERF_SEL_tl_in_xfc = 168 +DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 +DB_PERF_SEL_tl_in_fast_z_stall = 170 +DB_PERF_SEL_tl_out_xfc = 171 +DB_PERF_SEL_tl_out_squads = 172 +DB_PERF_SEL_zf_plane_multicycle = 173 +DB_PERF_SEL_PostZ_Samples_passing_Z = 174 +DB_PERF_SEL_PostZ_Samples_failing_Z = 175 +DB_PERF_SEL_PostZ_Samples_failing_S = 176 +DB_PERF_SEL_PreZ_Samples_passing_Z = 177 +DB_PERF_SEL_PreZ_Samples_failing_Z = 178 +DB_PERF_SEL_PreZ_Samples_failing_S = 179 +DB_PERF_SEL_ts_tc_update_stall = 180 +DB_PERF_SEL_sc_kick_start = 181 +DB_PERF_SEL_sc_kick_end = 182 +DB_PERF_SEL_clock_reg_active = 183 +DB_PERF_SEL_clock_main_active = 184 +DB_PERF_SEL_clock_mem_export_active = 185 +DB_PERF_SEL_esr_ps_out_busy = 186 +DB_PERF_SEL_esr_ps_lqf_busy = 187 +DB_PERF_SEL_esr_ps_lqf_stall = 188 +DB_PERF_SEL_etr_out_send = 189 +DB_PERF_SEL_etr_out_busy = 190 +DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 +DB_PERF_SEL_etr_out_cb_tile_stall = 192 +DB_PERF_SEL_etr_out_esr_stall = 193 +DB_PERF_SEL_esr_ps_sqq_busy = 194 +DB_PERF_SEL_esr_ps_sqq_stall = 195 +DB_PERF_SEL_esr_eot_fwd_busy = 196 +DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 +DB_PERF_SEL_esr_eot_fwd_forward = 198 +DB_PERF_SEL_esr_sqq_zi_busy = 199 +DB_PERF_SEL_esr_sqq_zi_stall = 200 +DB_PERF_SEL_postzl_sq_pt_busy = 201 +DB_PERF_SEL_postzl_sq_pt_stall = 202 +DB_PERF_SEL_postzl_se_busy = 203 +DB_PERF_SEL_postzl_se_stall = 204 +DB_PERF_SEL_postzl_partial_launch = 205 +DB_PERF_SEL_postzl_full_launch = 206 +DB_PERF_SEL_postzl_partial_waiting = 207 +DB_PERF_SEL_postzl_tile_mem_stall = 208 +DB_PERF_SEL_postzl_tile_init_stall = 209 +DB_PERF_SEL_prezl_tile_mem_stall = 210 +DB_PERF_SEL_prezl_tile_init_stall = 211 +DB_PERF_SEL_dtt_sm_clash_stall = 212 +DB_PERF_SEL_dtt_sm_slot_stall = 213 +DB_PERF_SEL_dtt_sm_miss_stall = 214 +DB_PERF_SEL_mi_rdreq_busy = 215 +DB_PERF_SEL_mi_rdreq_stall = 216 +DB_PERF_SEL_mi_wrreq_busy = 217 +DB_PERF_SEL_mi_wrreq_stall = 218 +DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 +DB_PERF_SEL_dkg_tile_rate_tile = 220 +DB_PERF_SEL_prezl_src_in_sends = 221 +DB_PERF_SEL_prezl_src_in_stall = 222 +DB_PERF_SEL_prezl_src_in_squads = 223 +DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 +DB_PERF_SEL_prezl_src_in_tile_rate = 225 +DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 +DB_PERF_SEL_prezl_src_out_stall = 227 +DB_PERF_SEL_postzl_src_in_sends = 228 +DB_PERF_SEL_postzl_src_in_stall = 229 +DB_PERF_SEL_postzl_src_in_squads = 230 +DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 +DB_PERF_SEL_postzl_src_in_tile_rate = 232 +DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 +DB_PERF_SEL_postzl_src_out_stall = 234 +DB_PERF_SEL_esr_ps_src_in_sends = 235 +DB_PERF_SEL_esr_ps_src_in_stall = 236 +DB_PERF_SEL_esr_ps_src_in_squads = 237 +DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 +DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 +DB_PERF_SEL_esr_ps_src_out_stall = 242 +DB_PERF_SEL_depth_bounds_tile_culled = 243 +DB_PERF_SEL_PreZ_Samples_failing_DB = 244 +DB_PERF_SEL_PostZ_Samples_failing_DB = 245 +DB_PERF_SEL_flush_compressed = 246 +DB_PERF_SEL_flush_plane_le4 = 247 +DB_PERF_SEL_tiles_z_fully_summarized = 248 +DB_PERF_SEL_tiles_stencil_fully_summarized = 249 +DB_PERF_SEL_tiles_z_clear_on_expclear = 250 +DB_PERF_SEL_tiles_s_clear_on_expclear = 251 +DB_PERF_SEL_tiles_decomp_on_expclear = 252 +DB_PERF_SEL_tiles_compressed_to_decompressed = 253 +DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 +DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 +DB_PERF_SEL_di_dt_stall = 256 +DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke = 257 +DB_PERF_SEL_DB_SC_s_tile_rate = 258 +DB_PERF_SEL_DB_SC_c_tile_rate = 259 +DB_PERF_SEL_DB_SC_z_tile_rate = 260 +Spare_261 = 261 +DB_PERF_SEL_DB_CB_lquad_export_quads = 262 +DB_PERF_SEL_DB_CB_lquad_double_format = 263 +DB_PERF_SEL_DB_CB_lquad_fast_format = 264 +DB_PERF_SEL_DB_CB_lquad_slow_format = 265 +DB_PERF_SEL_CB_DB_rdreq_sends = 266 +DB_PERF_SEL_CB_DB_rdreq_prt_sends = 267 +DB_PERF_SEL_CB_DB_wrreq_sends = 268 +DB_PERF_SEL_CB_DB_wrreq_prt_sends = 269 +DB_PERF_SEL_DB_CB_rdret_ack = 270 +DB_PERF_SEL_DB_CB_rdret_nack = 271 +DB_PERF_SEL_DB_CB_wrret_ack = 272 +DB_PERF_SEL_DB_CB_wrret_nack = 273 +DB_PERF_SEL_DFSM_Stall_opmode_change = 274 +DB_PERF_SEL_DFSM_Stall_cam_fifo = 275 +DB_PERF_SEL_DFSM_Stall_bypass_fifo = 276 +DB_PERF_SEL_DFSM_Stall_retained_tile_fifo = 277 +DB_PERF_SEL_DFSM_Stall_control_fifo = 278 +DB_PERF_SEL_DFSM_Stall_overflow_counter = 279 +DB_PERF_SEL_DFSM_Stall_pops_stall_overflow = 280 +DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush = 281 +DB_PERF_SEL_DFSM_Stall_middle_output = 282 +DB_PERF_SEL_DFSM_Stall_stalling_general = 283 +Spare_285 = 284 +Spare_286 = 285 +DB_PERF_SEL_DFSM_prez_killed_squad = 286 +DB_PERF_SEL_DFSM_squads_in = 287 +DB_PERF_SEL_DFSM_full_cleared_squads_out = 288 +DB_PERF_SEL_DFSM_quads_in = 289 +DB_PERF_SEL_DFSM_fully_cleared_quads_out = 290 +DB_PERF_SEL_DFSM_lit_pixels_in = 291 +DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 292 +DB_PERF_SEL_DFSM_lit_samples_in = 293 +DB_PERF_SEL_DFSM_lit_samples_out = 294 +DB_PERF_SEL_DFSM_evicted_tiles_above_watermark = 295 +DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 296 +DB_PERF_SEL_DFSM_stalled_by_downstream = 297 +DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 298 +DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 299 +DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 300 +DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 301 +DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 302 +DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 303 +DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 304 +DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 305 +DB_PERF_SEL_unmapped_z_tile_culled = 306 +DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 307 +DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 308 +DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 309 +DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 310 +DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 311 +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 312 +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 313 +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 314 +DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 315 +DB_PERF_SEL_DB_CB_context_dones = 316 +DB_PERF_SEL_DB_CB_eop_dones = 317 +DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 318 +DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 319 +DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 320 +DB_PERF_SEL_SC_DB_tile_backface = 321 +DB_PERF_SEL_SC_DB_quad_quads = 322 +DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 323 +DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 324 +DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 325 +DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 326 +DB_PERF_SEL_DFSM_Flush_flushabit = 327 +DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo = 328 +DB_PERF_SEL_DFSM_Flush_flushabit_passthrough = 329 +DB_PERF_SEL_DFSM_Flush_flushabit_forceflush = 330 +DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull = 331 +DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark = 332 +DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling = 333 +DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark = 334 +DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark = 335 +DB_PERF_SEL_DFSM_Flush_flushall = 336 +DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush = 337 +DB_PERF_SEL_DFSM_Flush_flushall_opmodechange = 338 +DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange = 339 +DB_PERF_SEL_DFSM_Flush_flushall_watchdog = 340 +DB_PERF_SEL_DB_SC_quad_double_quad = 341 +DB_PERF_SEL_SX_DB_quad_export_quads = 342 +DB_PERF_SEL_SX_DB_quad_double_format = 343 +DB_PERF_SEL_SX_DB_quad_fast_format = 344 +DB_PERF_SEL_SX_DB_quad_slow_format = 345 +PerfCounter_Vals = ctypes.c_uint32 # enum + +# values for enumeration 'RingCounterControl' +RingCounterControl__enumvalues = { + 0: 'COUNTER_RING_SPLIT', + 1: 'COUNTER_RING_0', + 2: 'COUNTER_RING_1', +} +COUNTER_RING_SPLIT = 0 +COUNTER_RING_0 = 1 +COUNTER_RING_1 = 2 +RingCounterControl = ctypes.c_uint32 # enum + +# values for enumeration 'DbMemArbWatermarks' +DbMemArbWatermarks__enumvalues = { + 0: 'TRANSFERRED_64_BYTES', + 1: 'TRANSFERRED_128_BYTES', + 2: 'TRANSFERRED_256_BYTES', + 3: 'TRANSFERRED_512_BYTES', + 4: 'TRANSFERRED_1024_BYTES', + 5: 'TRANSFERRED_2048_BYTES', + 6: 'TRANSFERRED_4096_BYTES', + 7: 'TRANSFERRED_8192_BYTES', +} +TRANSFERRED_64_BYTES = 0 +TRANSFERRED_128_BYTES = 1 +TRANSFERRED_256_BYTES = 2 +TRANSFERRED_512_BYTES = 3 +TRANSFERRED_1024_BYTES = 4 +TRANSFERRED_2048_BYTES = 5 +TRANSFERRED_4096_BYTES = 6 +TRANSFERRED_8192_BYTES = 7 +DbMemArbWatermarks = ctypes.c_uint32 # enum + +# values for enumeration 'DFSMFlushEvents' +DFSMFlushEvents__enumvalues = { + 0: 'DB_FLUSH_AND_INV_DB_DATA_TS', + 1: 'DB_FLUSH_AND_INV_DB_META', + 2: 'DB_CACHE_FLUSH', + 3: 'DB_CACHE_FLUSH_TS', + 4: 'DB_CACHE_FLUSH_AND_INV_EVENT', + 5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', + 6: 'DB_VPORT_CHANGED_EVENT', + 7: 'DB_CONTEXT_DONE_EVENT', + 8: 'DB_BREAK_BATCH_EVENT', + 9: 'DB_PSINVOKE_CHANGE_EVENT', + 10: 'DB_CONTEXT_SUSPEND_EVENT', +} +DB_FLUSH_AND_INV_DB_DATA_TS = 0 +DB_FLUSH_AND_INV_DB_META = 1 +DB_CACHE_FLUSH = 2 +DB_CACHE_FLUSH_TS = 3 +DB_CACHE_FLUSH_AND_INV_EVENT = 4 +DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5 +DB_VPORT_CHANGED_EVENT = 6 +DB_CONTEXT_DONE_EVENT = 7 +DB_BREAK_BATCH_EVENT = 8 +DB_PSINVOKE_CHANGE_EVENT = 9 +DB_CONTEXT_SUSPEND_EVENT = 10 +DFSMFlushEvents = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeCounterId' +PixelPipeCounterId__enumvalues = { + 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', + 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', + 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', + 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', + 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', + 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', +} +PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 +PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 +PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 +PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 +PixelPipeCounterId = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeStride' +PixelPipeStride__enumvalues = { + 0: 'PIXEL_PIPE_STRIDE_32_BITS', + 1: 'PIXEL_PIPE_STRIDE_64_BITS', + 2: 'PIXEL_PIPE_STRIDE_128_BITS', + 3: 'PIXEL_PIPE_STRIDE_256_BITS', +} +PIXEL_PIPE_STRIDE_32_BITS = 0 +PIXEL_PIPE_STRIDE_64_BITS = 1 +PIXEL_PIPE_STRIDE_128_BITS = 2 +PIXEL_PIPE_STRIDE_256_BITS = 3 +PixelPipeStride = ctypes.c_uint32 # enum + +# values for enumeration 'FullTileWaveBreak' +FullTileWaveBreak__enumvalues = { + 0: 'FULL_TILE_WAVE_BREAK_NBC_ONLY', + 1: 'FULL_TILE_WAVE_BREAK_BOTH', + 2: 'FULL_TILE_WAVE_BREAK_NONE', + 3: 'FULL_TILE_WAVE_BREAK_BC_ONLY', +} +FULL_TILE_WAVE_BREAK_NBC_ONLY = 0 +FULL_TILE_WAVE_BREAK_BOTH = 1 +FULL_TILE_WAVE_BREAK_NONE = 2 +FULL_TILE_WAVE_BREAK_BC_ONLY = 3 +FullTileWaveBreak = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_BORDER_COLOR_TYPE' +TEX_BORDER_COLOR_TYPE__enumvalues = { + 0: 'TEX_BorderColor_TransparentBlack', + 1: 'TEX_BorderColor_OpaqueBlack', + 2: 'TEX_BorderColor_OpaqueWhite', + 3: 'TEX_BorderColor_Register', +} +TEX_BorderColor_TransparentBlack = 0 +TEX_BorderColor_OpaqueBlack = 1 +TEX_BorderColor_OpaqueWhite = 2 +TEX_BorderColor_Register = 3 +TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_BC_SWIZZLE' +TEX_BC_SWIZZLE__enumvalues = { + 0: 'TEX_BC_Swizzle_XYZW', + 1: 'TEX_BC_Swizzle_XWYZ', + 2: 'TEX_BC_Swizzle_WZYX', + 3: 'TEX_BC_Swizzle_WXYZ', + 4: 'TEX_BC_Swizzle_ZYXW', + 5: 'TEX_BC_Swizzle_YXWZ', +} +TEX_BC_Swizzle_XYZW = 0 +TEX_BC_Swizzle_XWYZ = 1 +TEX_BC_Swizzle_WZYX = 2 +TEX_BC_Swizzle_WXYZ = 3 +TEX_BC_Swizzle_ZYXW = 4 +TEX_BC_Swizzle_YXWZ = 5 +TEX_BC_SWIZZLE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CHROMA_KEY' +TEX_CHROMA_KEY__enumvalues = { + 0: 'TEX_ChromaKey_Disabled', + 1: 'TEX_ChromaKey_Kill', + 2: 'TEX_ChromaKey_Blend', + 3: 'TEX_ChromaKey_RESERVED_3', +} +TEX_ChromaKey_Disabled = 0 +TEX_ChromaKey_Kill = 1 +TEX_ChromaKey_Blend = 2 +TEX_ChromaKey_RESERVED_3 = 3 +TEX_CHROMA_KEY = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CLAMP' +TEX_CLAMP__enumvalues = { + 0: 'TEX_Clamp_Repeat', + 1: 'TEX_Clamp_Mirror', + 2: 'TEX_Clamp_ClampToLast', + 3: 'TEX_Clamp_MirrorOnceToLast', + 4: 'TEX_Clamp_ClampHalfToBorder', + 5: 'TEX_Clamp_MirrorOnceHalfToBorder', + 6: 'TEX_Clamp_ClampToBorder', + 7: 'TEX_Clamp_MirrorOnceToBorder', +} +TEX_Clamp_Repeat = 0 +TEX_Clamp_Mirror = 1 +TEX_Clamp_ClampToLast = 2 +TEX_Clamp_MirrorOnceToLast = 3 +TEX_Clamp_ClampHalfToBorder = 4 +TEX_Clamp_MirrorOnceHalfToBorder = 5 +TEX_Clamp_ClampToBorder = 6 +TEX_Clamp_MirrorOnceToBorder = 7 +TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_COORD_TYPE' +TEX_COORD_TYPE__enumvalues = { + 0: 'TEX_CoordType_Unnormalized', + 1: 'TEX_CoordType_Normalized', +} +TEX_CoordType_Unnormalized = 0 +TEX_CoordType_Normalized = 1 +TEX_COORD_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' +TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { + 0: 'TEX_DepthCompareFunction_Never', + 1: 'TEX_DepthCompareFunction_Less', + 2: 'TEX_DepthCompareFunction_Equal', + 3: 'TEX_DepthCompareFunction_LessEqual', + 4: 'TEX_DepthCompareFunction_Greater', + 5: 'TEX_DepthCompareFunction_NotEqual', + 6: 'TEX_DepthCompareFunction_GreaterEqual', + 7: 'TEX_DepthCompareFunction_Always', +} +TEX_DepthCompareFunction_Never = 0 +TEX_DepthCompareFunction_Less = 1 +TEX_DepthCompareFunction_Equal = 2 +TEX_DepthCompareFunction_LessEqual = 3 +TEX_DepthCompareFunction_Greater = 4 +TEX_DepthCompareFunction_NotEqual = 5 +TEX_DepthCompareFunction_GreaterEqual = 6 +TEX_DepthCompareFunction_Always = 7 +TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_DIM' +TEX_DIM__enumvalues = { + 0: 'TEX_Dim_1D', + 1: 'TEX_Dim_2D', + 2: 'TEX_Dim_3D', + 3: 'TEX_Dim_CubeMap', + 4: 'TEX_Dim_1DArray', + 5: 'TEX_Dim_2DArray', + 6: 'TEX_Dim_2D_MSAA', + 7: 'TEX_Dim_2DArray_MSAA', +} +TEX_Dim_1D = 0 +TEX_Dim_2D = 1 +TEX_Dim_3D = 2 +TEX_Dim_CubeMap = 3 +TEX_Dim_1DArray = 4 +TEX_Dim_2DArray = 5 +TEX_Dim_2D_MSAA = 6 +TEX_Dim_2DArray_MSAA = 7 +TEX_DIM = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_FORMAT_COMP' +TEX_FORMAT_COMP__enumvalues = { + 0: 'TEX_FormatComp_Unsigned', + 1: 'TEX_FormatComp_Signed', + 2: 'TEX_FormatComp_UnsignedBiased', + 3: 'TEX_FormatComp_RESERVED_3', +} +TEX_FormatComp_Unsigned = 0 +TEX_FormatComp_Signed = 1 +TEX_FormatComp_UnsignedBiased = 2 +TEX_FormatComp_RESERVED_3 = 3 +TEX_FORMAT_COMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MAX_ANISO_RATIO' +TEX_MAX_ANISO_RATIO__enumvalues = { + 0: 'TEX_MaxAnisoRatio_1to1', + 1: 'TEX_MaxAnisoRatio_2to1', + 2: 'TEX_MaxAnisoRatio_4to1', + 3: 'TEX_MaxAnisoRatio_8to1', + 4: 'TEX_MaxAnisoRatio_16to1', + 5: 'TEX_MaxAnisoRatio_RESERVED_5', + 6: 'TEX_MaxAnisoRatio_RESERVED_6', + 7: 'TEX_MaxAnisoRatio_RESERVED_7', +} +TEX_MaxAnisoRatio_1to1 = 0 +TEX_MaxAnisoRatio_2to1 = 1 +TEX_MaxAnisoRatio_4to1 = 2 +TEX_MaxAnisoRatio_8to1 = 3 +TEX_MaxAnisoRatio_16to1 = 4 +TEX_MaxAnisoRatio_RESERVED_5 = 5 +TEX_MaxAnisoRatio_RESERVED_6 = 6 +TEX_MaxAnisoRatio_RESERVED_7 = 7 +TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MIP_FILTER' +TEX_MIP_FILTER__enumvalues = { + 0: 'TEX_MipFilter_None', + 1: 'TEX_MipFilter_Point', + 2: 'TEX_MipFilter_Linear', + 3: 'TEX_MipFilter_Point_Aniso_Adj', +} +TEX_MipFilter_None = 0 +TEX_MipFilter_Point = 1 +TEX_MipFilter_Linear = 2 +TEX_MipFilter_Point_Aniso_Adj = 3 +TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_REQUEST_SIZE' +TEX_REQUEST_SIZE__enumvalues = { + 0: 'TEX_RequestSize_32B', + 1: 'TEX_RequestSize_64B', + 2: 'TEX_RequestSize_128B', + 3: 'TEX_RequestSize_2X64B', +} +TEX_RequestSize_32B = 0 +TEX_RequestSize_64B = 1 +TEX_RequestSize_128B = 2 +TEX_RequestSize_2X64B = 3 +TEX_REQUEST_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_SAMPLER_TYPE' +TEX_SAMPLER_TYPE__enumvalues = { + 0: 'TEX_SamplerType_Invalid', + 1: 'TEX_SamplerType_Valid', +} +TEX_SamplerType_Invalid = 0 +TEX_SamplerType_Valid = 1 +TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_XY_FILTER' +TEX_XY_FILTER__enumvalues = { + 0: 'TEX_XYFilter_Point', + 1: 'TEX_XYFilter_Linear', + 2: 'TEX_XYFilter_AnisoPoint', + 3: 'TEX_XYFilter_AnisoLinear', +} +TEX_XYFilter_Point = 0 +TEX_XYFilter_Linear = 1 +TEX_XYFilter_AnisoPoint = 2 +TEX_XYFilter_AnisoLinear = 3 +TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_Z_FILTER' +TEX_Z_FILTER__enumvalues = { + 0: 'TEX_ZFilter_None', + 1: 'TEX_ZFilter_Point', + 2: 'TEX_ZFilter_Linear', + 3: 'TEX_ZFilter_RESERVED_3', +} +TEX_ZFilter_None = 0 +TEX_ZFilter_Point = 1 +TEX_ZFilter_Linear = 2 +TEX_ZFilter_RESERVED_3 = 3 +TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'VTX_CLAMP' +VTX_CLAMP__enumvalues = { + 0: 'VTX_Clamp_ClampToZero', + 1: 'VTX_Clamp_ClampToNAN', +} +VTX_Clamp_ClampToZero = 0 +VTX_Clamp_ClampToNAN = 1 +VTX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'VTX_FETCH_TYPE' +VTX_FETCH_TYPE__enumvalues = { + 0: 'VTX_FetchType_VertexData', + 1: 'VTX_FetchType_InstanceData', + 2: 'VTX_FetchType_NoIndexOffset', + 3: 'VTX_FetchType_RESERVED_3', +} +VTX_FetchType_VertexData = 0 +VTX_FetchType_InstanceData = 1 +VTX_FetchType_NoIndexOffset = 2 +VTX_FetchType_RESERVED_3 = 3 +VTX_FETCH_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VTX_FORMAT_COMP_ALL' +VTX_FORMAT_COMP_ALL__enumvalues = { + 0: 'VTX_FormatCompAll_Unsigned', + 1: 'VTX_FormatCompAll_Signed', +} +VTX_FormatCompAll_Unsigned = 0 +VTX_FormatCompAll_Signed = 1 +VTX_FORMAT_COMP_ALL = ctypes.c_uint32 # enum + +# values for enumeration 'VTX_MEM_REQUEST_SIZE' +VTX_MEM_REQUEST_SIZE__enumvalues = { + 0: 'VTX_MemRequestSize_32B', + 1: 'VTX_MemRequestSize_64B', +} +VTX_MemRequestSize_32B = 0 +VTX_MemRequestSize_64B = 1 +VTX_MEM_REQUEST_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_DATA_FORMAT' +TVX_DATA_FORMAT__enumvalues = { + 0: 'TVX_FMT_INVALID', + 1: 'TVX_FMT_8', + 2: 'TVX_FMT_4_4', + 3: 'TVX_FMT_3_3_2', + 4: 'TVX_FMT_RESERVED_4', + 5: 'TVX_FMT_16', + 6: 'TVX_FMT_16_FLOAT', + 7: 'TVX_FMT_8_8', + 8: 'TVX_FMT_5_6_5', + 9: 'TVX_FMT_6_5_5', + 10: 'TVX_FMT_1_5_5_5', + 11: 'TVX_FMT_4_4_4_4', + 12: 'TVX_FMT_5_5_5_1', + 13: 'TVX_FMT_32', + 14: 'TVX_FMT_32_FLOAT', + 15: 'TVX_FMT_16_16', + 16: 'TVX_FMT_16_16_FLOAT', + 17: 'TVX_FMT_8_24', + 18: 'TVX_FMT_8_24_FLOAT', + 19: 'TVX_FMT_24_8', + 20: 'TVX_FMT_24_8_FLOAT', + 21: 'TVX_FMT_10_11_11', + 22: 'TVX_FMT_10_11_11_FLOAT', + 23: 'TVX_FMT_11_11_10', + 24: 'TVX_FMT_11_11_10_FLOAT', + 25: 'TVX_FMT_2_10_10_10', + 26: 'TVX_FMT_8_8_8_8', + 27: 'TVX_FMT_10_10_10_2', + 28: 'TVX_FMT_X24_8_32_FLOAT', + 29: 'TVX_FMT_32_32', + 30: 'TVX_FMT_32_32_FLOAT', + 31: 'TVX_FMT_16_16_16_16', + 32: 'TVX_FMT_16_16_16_16_FLOAT', + 33: 'TVX_FMT_RESERVED_33', + 34: 'TVX_FMT_32_32_32_32', + 35: 'TVX_FMT_32_32_32_32_FLOAT', + 36: 'TVX_FMT_RESERVED_36', + 37: 'TVX_FMT_1', + 38: 'TVX_FMT_1_REVERSED', + 39: 'TVX_FMT_GB_GR', + 40: 'TVX_FMT_BG_RG', + 41: 'TVX_FMT_32_AS_8', + 42: 'TVX_FMT_32_AS_8_8', + 43: 'TVX_FMT_5_9_9_9_SHAREDEXP', + 44: 'TVX_FMT_8_8_8', + 45: 'TVX_FMT_16_16_16', + 46: 'TVX_FMT_16_16_16_FLOAT', + 47: 'TVX_FMT_32_32_32', + 48: 'TVX_FMT_32_32_32_FLOAT', + 49: 'TVX_FMT_BC1', + 50: 'TVX_FMT_BC2', + 51: 'TVX_FMT_BC3', + 52: 'TVX_FMT_BC4', + 53: 'TVX_FMT_BC5', + 54: 'TVX_FMT_APC0', + 55: 'TVX_FMT_APC1', + 56: 'TVX_FMT_APC2', + 57: 'TVX_FMT_APC3', + 58: 'TVX_FMT_APC4', + 59: 'TVX_FMT_APC5', + 60: 'TVX_FMT_APC6', + 61: 'TVX_FMT_APC7', + 62: 'TVX_FMT_CTX1', + 63: 'TVX_FMT_RESERVED_63', +} +TVX_FMT_INVALID = 0 +TVX_FMT_8 = 1 +TVX_FMT_4_4 = 2 +TVX_FMT_3_3_2 = 3 +TVX_FMT_RESERVED_4 = 4 +TVX_FMT_16 = 5 +TVX_FMT_16_FLOAT = 6 +TVX_FMT_8_8 = 7 +TVX_FMT_5_6_5 = 8 +TVX_FMT_6_5_5 = 9 +TVX_FMT_1_5_5_5 = 10 +TVX_FMT_4_4_4_4 = 11 +TVX_FMT_5_5_5_1 = 12 +TVX_FMT_32 = 13 +TVX_FMT_32_FLOAT = 14 +TVX_FMT_16_16 = 15 +TVX_FMT_16_16_FLOAT = 16 +TVX_FMT_8_24 = 17 +TVX_FMT_8_24_FLOAT = 18 +TVX_FMT_24_8 = 19 +TVX_FMT_24_8_FLOAT = 20 +TVX_FMT_10_11_11 = 21 +TVX_FMT_10_11_11_FLOAT = 22 +TVX_FMT_11_11_10 = 23 +TVX_FMT_11_11_10_FLOAT = 24 +TVX_FMT_2_10_10_10 = 25 +TVX_FMT_8_8_8_8 = 26 +TVX_FMT_10_10_10_2 = 27 +TVX_FMT_X24_8_32_FLOAT = 28 +TVX_FMT_32_32 = 29 +TVX_FMT_32_32_FLOAT = 30 +TVX_FMT_16_16_16_16 = 31 +TVX_FMT_16_16_16_16_FLOAT = 32 +TVX_FMT_RESERVED_33 = 33 +TVX_FMT_32_32_32_32 = 34 +TVX_FMT_32_32_32_32_FLOAT = 35 +TVX_FMT_RESERVED_36 = 36 +TVX_FMT_1 = 37 +TVX_FMT_1_REVERSED = 38 +TVX_FMT_GB_GR = 39 +TVX_FMT_BG_RG = 40 +TVX_FMT_32_AS_8 = 41 +TVX_FMT_32_AS_8_8 = 42 +TVX_FMT_5_9_9_9_SHAREDEXP = 43 +TVX_FMT_8_8_8 = 44 +TVX_FMT_16_16_16 = 45 +TVX_FMT_16_16_16_FLOAT = 46 +TVX_FMT_32_32_32 = 47 +TVX_FMT_32_32_32_FLOAT = 48 +TVX_FMT_BC1 = 49 +TVX_FMT_BC2 = 50 +TVX_FMT_BC3 = 51 +TVX_FMT_BC4 = 52 +TVX_FMT_BC5 = 53 +TVX_FMT_APC0 = 54 +TVX_FMT_APC1 = 55 +TVX_FMT_APC2 = 56 +TVX_FMT_APC3 = 57 +TVX_FMT_APC4 = 58 +TVX_FMT_APC5 = 59 +TVX_FMT_APC6 = 60 +TVX_FMT_APC7 = 61 +TVX_FMT_CTX1 = 62 +TVX_FMT_RESERVED_63 = 63 +TVX_DATA_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_DST_SEL' +TVX_DST_SEL__enumvalues = { + 0: 'TVX_DstSel_X', + 1: 'TVX_DstSel_Y', + 2: 'TVX_DstSel_Z', + 3: 'TVX_DstSel_W', + 4: 'TVX_DstSel_0f', + 5: 'TVX_DstSel_1f', + 6: 'TVX_DstSel_RESERVED_6', + 7: 'TVX_DstSel_Mask', +} +TVX_DstSel_X = 0 +TVX_DstSel_Y = 1 +TVX_DstSel_Z = 2 +TVX_DstSel_W = 3 +TVX_DstSel_0f = 4 +TVX_DstSel_1f = 5 +TVX_DstSel_RESERVED_6 = 6 +TVX_DstSel_Mask = 7 +TVX_DST_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_ENDIAN_SWAP' +TVX_ENDIAN_SWAP__enumvalues = { + 0: 'TVX_EndianSwap_None', + 1: 'TVX_EndianSwap_8in16', + 2: 'TVX_EndianSwap_8in32', + 3: 'TVX_EndianSwap_8in64', +} +TVX_EndianSwap_None = 0 +TVX_EndianSwap_8in16 = 1 +TVX_EndianSwap_8in32 = 2 +TVX_EndianSwap_8in64 = 3 +TVX_ENDIAN_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_INST' +TVX_INST__enumvalues = { + 0: 'TVX_Inst_NormalVertexFetch', + 1: 'TVX_Inst_SemanticVertexFetch', + 2: 'TVX_Inst_RESERVED_2', + 3: 'TVX_Inst_LD', + 4: 'TVX_Inst_GetTextureResInfo', + 5: 'TVX_Inst_GetNumberOfSamples', + 6: 'TVX_Inst_GetLOD', + 7: 'TVX_Inst_GetGradientsH', + 8: 'TVX_Inst_GetGradientsV', + 9: 'TVX_Inst_SetTextureOffsets', + 10: 'TVX_Inst_KeepGradients', + 11: 'TVX_Inst_SetGradientsH', + 12: 'TVX_Inst_SetGradientsV', + 13: 'TVX_Inst_Pass', + 14: 'TVX_Inst_GetBufferResInfo', + 15: 'TVX_Inst_RESERVED_15', + 16: 'TVX_Inst_Sample', + 17: 'TVX_Inst_Sample_L', + 18: 'TVX_Inst_Sample_LB', + 19: 'TVX_Inst_Sample_LZ', + 20: 'TVX_Inst_Sample_G', + 21: 'TVX_Inst_Gather4', + 22: 'TVX_Inst_Sample_G_LB', + 23: 'TVX_Inst_Gather4_O', + 24: 'TVX_Inst_Sample_C', + 25: 'TVX_Inst_Sample_C_L', + 26: 'TVX_Inst_Sample_C_LB', + 27: 'TVX_Inst_Sample_C_LZ', + 28: 'TVX_Inst_Sample_C_G', + 29: 'TVX_Inst_Gather4_C', + 30: 'TVX_Inst_Sample_C_G_LB', + 31: 'TVX_Inst_Gather4_C_O', +} +TVX_Inst_NormalVertexFetch = 0 +TVX_Inst_SemanticVertexFetch = 1 +TVX_Inst_RESERVED_2 = 2 +TVX_Inst_LD = 3 +TVX_Inst_GetTextureResInfo = 4 +TVX_Inst_GetNumberOfSamples = 5 +TVX_Inst_GetLOD = 6 +TVX_Inst_GetGradientsH = 7 +TVX_Inst_GetGradientsV = 8 +TVX_Inst_SetTextureOffsets = 9 +TVX_Inst_KeepGradients = 10 +TVX_Inst_SetGradientsH = 11 +TVX_Inst_SetGradientsV = 12 +TVX_Inst_Pass = 13 +TVX_Inst_GetBufferResInfo = 14 +TVX_Inst_RESERVED_15 = 15 +TVX_Inst_Sample = 16 +TVX_Inst_Sample_L = 17 +TVX_Inst_Sample_LB = 18 +TVX_Inst_Sample_LZ = 19 +TVX_Inst_Sample_G = 20 +TVX_Inst_Gather4 = 21 +TVX_Inst_Sample_G_LB = 22 +TVX_Inst_Gather4_O = 23 +TVX_Inst_Sample_C = 24 +TVX_Inst_Sample_C_L = 25 +TVX_Inst_Sample_C_LB = 26 +TVX_Inst_Sample_C_LZ = 27 +TVX_Inst_Sample_C_G = 28 +TVX_Inst_Gather4_C = 29 +TVX_Inst_Sample_C_G_LB = 30 +TVX_Inst_Gather4_C_O = 31 +TVX_INST = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_NUM_FORMAT_ALL' +TVX_NUM_FORMAT_ALL__enumvalues = { + 0: 'TVX_NumFormatAll_Norm', + 1: 'TVX_NumFormatAll_Int', + 2: 'TVX_NumFormatAll_Scaled', + 3: 'TVX_NumFormatAll_RESERVED_3', +} +TVX_NumFormatAll_Norm = 0 +TVX_NumFormatAll_Int = 1 +TVX_NumFormatAll_Scaled = 2 +TVX_NumFormatAll_RESERVED_3 = 3 +TVX_NUM_FORMAT_ALL = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_SRC_SEL' +TVX_SRC_SEL__enumvalues = { + 0: 'TVX_SrcSel_X', + 1: 'TVX_SrcSel_Y', + 2: 'TVX_SrcSel_Z', + 3: 'TVX_SrcSel_W', + 4: 'TVX_SrcSel_0f', + 5: 'TVX_SrcSel_1f', +} +TVX_SrcSel_X = 0 +TVX_SrcSel_Y = 1 +TVX_SrcSel_Z = 2 +TVX_SrcSel_W = 3 +TVX_SrcSel_0f = 4 +TVX_SrcSel_1f = 5 +TVX_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_SRF_MODE_ALL' +TVX_SRF_MODE_ALL__enumvalues = { + 0: 'TVX_SRFModeAll_ZCMO', + 1: 'TVX_SRFModeAll_NZ', +} +TVX_SRFModeAll_ZCMO = 0 +TVX_SRFModeAll_NZ = 1 +TVX_SRF_MODE_ALL = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_TYPE' +TVX_TYPE__enumvalues = { + 0: 'TVX_Type_InvalidTextureResource', + 1: 'TVX_Type_InvalidVertexBuffer', + 2: 'TVX_Type_ValidTextureResource', + 3: 'TVX_Type_ValidVertexBuffer', +} +TVX_Type_InvalidTextureResource = 0 +TVX_Type_InvalidVertexBuffer = 1 +TVX_Type_ValidTextureResource = 2 +TVX_Type_ValidVertexBuffer = 3 +TVX_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PH_PERFCNT_SEL' +PH_PERFCNT_SEL__enumvalues = { + 0: 'PH_SC0_SRPS_WINDOW_VALID', + 1: 'PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 2: 'PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES', + 3: 'PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 4: 'PH_SC0_ARB_STALLED_FROM_BELOW', + 5: 'PH_SC0_ARB_STARVED_FROM_ABOVE', + 6: 'PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 7: 'PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 8: 'PH_SC0_ARB_BUSY', + 9: 'PH_SC0_ARB_PA_BUSY_SOP', + 10: 'PH_SC0_ARB_EOP_POP_SYNC_POP', + 11: 'PH_SC0_ARB_EVENT_SYNC_POP', + 12: 'PH_SC0_PS_ENG_MULTICYCLE_BUBBLE', + 13: 'PH_SC0_EOP_SYNC_WINDOW', + 14: 'PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', + 15: 'PH_SC0_BUSY_CNT_NOT_ZERO', + 16: 'PH_SC0_SEND', + 17: 'PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 18: 'PH_SC0_CREDIT_AT_MAX', + 19: 'PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', + 20: 'PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 21: 'PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', + 22: 'PH_SC0_GFX_PIPE0_TO_1_TRANSITION', + 23: 'PH_SC0_GFX_PIPE1_TO_0_TRANSITION', + 24: 'PH_SC0_PA0_DATA_FIFO_RD', + 25: 'PH_SC0_PA0_DATA_FIFO_WE', + 26: 'PH_SC0_PA0_FIFO_EMPTY', + 27: 'PH_SC0_PA0_FIFO_FULL', + 28: 'PH_SC0_PA0_NULL_WE', + 29: 'PH_SC0_PA0_EVENT_WE', + 30: 'PH_SC0_PA0_FPOV_WE', + 31: 'PH_SC0_PA0_LPOV_WE', + 32: 'PH_SC0_PA0_EOP_WE', + 33: 'PH_SC0_PA0_DATA_FIFO_EOP_RD', + 34: 'PH_SC0_PA0_EOPG_WE', + 35: 'PH_SC0_PA0_DEALLOC_4_0_RD', + 36: 'PH_SC0_PA1_DATA_FIFO_RD', + 37: 'PH_SC0_PA1_DATA_FIFO_WE', + 38: 'PH_SC0_PA1_FIFO_EMPTY', + 39: 'PH_SC0_PA1_FIFO_FULL', + 40: 'PH_SC0_PA1_NULL_WE', + 41: 'PH_SC0_PA1_EVENT_WE', + 42: 'PH_SC0_PA1_FPOV_WE', + 43: 'PH_SC0_PA1_LPOV_WE', + 44: 'PH_SC0_PA1_EOP_WE', + 45: 'PH_SC0_PA1_DATA_FIFO_EOP_RD', + 46: 'PH_SC0_PA1_EOPG_WE', + 47: 'PH_SC0_PA1_DEALLOC_4_0_RD', + 48: 'PH_SC0_PA2_DATA_FIFO_RD', + 49: 'PH_SC0_PA2_DATA_FIFO_WE', + 50: 'PH_SC0_PA2_FIFO_EMPTY', + 51: 'PH_SC0_PA2_FIFO_FULL', + 52: 'PH_SC0_PA2_NULL_WE', + 53: 'PH_SC0_PA2_EVENT_WE', + 54: 'PH_SC0_PA2_FPOV_WE', + 55: 'PH_SC0_PA2_LPOV_WE', + 56: 'PH_SC0_PA2_EOP_WE', + 57: 'PH_SC0_PA2_DATA_FIFO_EOP_RD', + 58: 'PH_SC0_PA2_EOPG_WE', + 59: 'PH_SC0_PA2_DEALLOC_4_0_RD', + 60: 'PH_SC0_PA3_DATA_FIFO_RD', + 61: 'PH_SC0_PA3_DATA_FIFO_WE', + 62: 'PH_SC0_PA3_FIFO_EMPTY', + 63: 'PH_SC0_PA3_FIFO_FULL', + 64: 'PH_SC0_PA3_NULL_WE', + 65: 'PH_SC0_PA3_EVENT_WE', + 66: 'PH_SC0_PA3_FPOV_WE', + 67: 'PH_SC0_PA3_LPOV_WE', + 68: 'PH_SC0_PA3_EOP_WE', + 69: 'PH_SC0_PA3_DATA_FIFO_EOP_RD', + 70: 'PH_SC0_PA3_EOPG_WE', + 71: 'PH_SC0_PA3_DEALLOC_4_0_RD', + 72: 'PH_SC0_PA4_DATA_FIFO_RD', + 73: 'PH_SC0_PA4_DATA_FIFO_WE', + 74: 'PH_SC0_PA4_FIFO_EMPTY', + 75: 'PH_SC0_PA4_FIFO_FULL', + 76: 'PH_SC0_PA4_NULL_WE', + 77: 'PH_SC0_PA4_EVENT_WE', + 78: 'PH_SC0_PA4_FPOV_WE', + 79: 'PH_SC0_PA4_LPOV_WE', + 80: 'PH_SC0_PA4_EOP_WE', + 81: 'PH_SC0_PA4_DATA_FIFO_EOP_RD', + 82: 'PH_SC0_PA4_EOPG_WE', + 83: 'PH_SC0_PA4_DEALLOC_4_0_RD', + 84: 'PH_SC0_PA5_DATA_FIFO_RD', + 85: 'PH_SC0_PA5_DATA_FIFO_WE', + 86: 'PH_SC0_PA5_FIFO_EMPTY', + 87: 'PH_SC0_PA5_FIFO_FULL', + 88: 'PH_SC0_PA5_NULL_WE', + 89: 'PH_SC0_PA5_EVENT_WE', + 90: 'PH_SC0_PA5_FPOV_WE', + 91: 'PH_SC0_PA5_LPOV_WE', + 92: 'PH_SC0_PA5_EOP_WE', + 93: 'PH_SC0_PA5_DATA_FIFO_EOP_RD', + 94: 'PH_SC0_PA5_EOPG_WE', + 95: 'PH_SC0_PA5_DEALLOC_4_0_RD', + 96: 'PH_SC0_PA6_DATA_FIFO_RD', + 97: 'PH_SC0_PA6_DATA_FIFO_WE', + 98: 'PH_SC0_PA6_FIFO_EMPTY', + 99: 'PH_SC0_PA6_FIFO_FULL', + 100: 'PH_SC0_PA6_NULL_WE', + 101: 'PH_SC0_PA6_EVENT_WE', + 102: 'PH_SC0_PA6_FPOV_WE', + 103: 'PH_SC0_PA6_LPOV_WE', + 104: 'PH_SC0_PA6_EOP_WE', + 105: 'PH_SC0_PA6_DATA_FIFO_EOP_RD', + 106: 'PH_SC0_PA6_EOPG_WE', + 107: 'PH_SC0_PA6_DEALLOC_4_0_RD', + 108: 'PH_SC0_PA7_DATA_FIFO_RD', + 109: 'PH_SC0_PA7_DATA_FIFO_WE', + 110: 'PH_SC0_PA7_FIFO_EMPTY', + 111: 'PH_SC0_PA7_FIFO_FULL', + 112: 'PH_SC0_PA7_NULL_WE', + 113: 'PH_SC0_PA7_EVENT_WE', + 114: 'PH_SC0_PA7_FPOV_WE', + 115: 'PH_SC0_PA7_LPOV_WE', + 116: 'PH_SC0_PA7_EOP_WE', + 117: 'PH_SC0_PA7_DATA_FIFO_EOP_RD', + 118: 'PH_SC0_PA7_EOPG_WE', + 119: 'PH_SC0_PA7_DEALLOC_4_0_RD', + 120: 'PH_SC1_SRPS_WINDOW_VALID', + 121: 'PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 122: 'PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES', + 123: 'PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 124: 'PH_SC1_ARB_STALLED_FROM_BELOW', + 125: 'PH_SC1_ARB_STARVED_FROM_ABOVE', + 126: 'PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 127: 'PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 128: 'PH_SC1_ARB_BUSY', + 129: 'PH_SC1_ARB_PA_BUSY_SOP', + 130: 'PH_SC1_ARB_EOP_POP_SYNC_POP', + 131: 'PH_SC1_ARB_EVENT_SYNC_POP', + 132: 'PH_SC1_PS_ENG_MULTICYCLE_BUBBLE', + 133: 'PH_SC1_EOP_SYNC_WINDOW', + 134: 'PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', + 135: 'PH_SC1_BUSY_CNT_NOT_ZERO', + 136: 'PH_SC1_SEND', + 137: 'PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 138: 'PH_SC1_CREDIT_AT_MAX', + 139: 'PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', + 140: 'PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 141: 'PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 142: 'PH_SC1_GFX_PIPE0_TO_1_TRANSITION', + 143: 'PH_SC1_GFX_PIPE1_TO_0_TRANSITION', + 144: 'PH_SC1_PA0_DATA_FIFO_RD', + 145: 'PH_SC1_PA0_DATA_FIFO_WE', + 146: 'PH_SC1_PA0_FIFO_EMPTY', + 147: 'PH_SC1_PA0_FIFO_FULL', + 148: 'PH_SC1_PA0_NULL_WE', + 149: 'PH_SC1_PA0_EVENT_WE', + 150: 'PH_SC1_PA0_FPOV_WE', + 151: 'PH_SC1_PA0_LPOV_WE', + 152: 'PH_SC1_PA0_EOP_WE', + 153: 'PH_SC1_PA0_DATA_FIFO_EOP_RD', + 154: 'PH_SC1_PA0_EOPG_WE', + 155: 'PH_SC1_PA0_DEALLOC_4_0_RD', + 156: 'PH_SC1_PA1_DATA_FIFO_RD', + 157: 'PH_SC1_PA1_DATA_FIFO_WE', + 158: 'PH_SC1_PA1_FIFO_EMPTY', + 159: 'PH_SC1_PA1_FIFO_FULL', + 160: 'PH_SC1_PA1_NULL_WE', + 161: 'PH_SC1_PA1_EVENT_WE', + 162: 'PH_SC1_PA1_FPOV_WE', + 163: 'PH_SC1_PA1_LPOV_WE', + 164: 'PH_SC1_PA1_EOP_WE', + 165: 'PH_SC1_PA1_DATA_FIFO_EOP_RD', + 166: 'PH_SC1_PA1_EOPG_WE', + 167: 'PH_SC1_PA1_DEALLOC_4_0_RD', + 168: 'PH_SC1_PA2_DATA_FIFO_RD', + 169: 'PH_SC1_PA2_DATA_FIFO_WE', + 170: 'PH_SC1_PA2_FIFO_EMPTY', + 171: 'PH_SC1_PA2_FIFO_FULL', + 172: 'PH_SC1_PA2_NULL_WE', + 173: 'PH_SC1_PA2_EVENT_WE', + 174: 'PH_SC1_PA2_FPOV_WE', + 175: 'PH_SC1_PA2_LPOV_WE', + 176: 'PH_SC1_PA2_EOP_WE', + 177: 'PH_SC1_PA2_DATA_FIFO_EOP_RD', + 178: 'PH_SC1_PA2_EOPG_WE', + 179: 'PH_SC1_PA2_DEALLOC_4_0_RD', + 180: 'PH_SC1_PA3_DATA_FIFO_RD', + 181: 'PH_SC1_PA3_DATA_FIFO_WE', + 182: 'PH_SC1_PA3_FIFO_EMPTY', + 183: 'PH_SC1_PA3_FIFO_FULL', + 184: 'PH_SC1_PA3_NULL_WE', + 185: 'PH_SC1_PA3_EVENT_WE', + 186: 'PH_SC1_PA3_FPOV_WE', + 187: 'PH_SC1_PA3_LPOV_WE', + 188: 'PH_SC1_PA3_EOP_WE', + 189: 'PH_SC1_PA3_DATA_FIFO_EOP_RD', + 190: 'PH_SC1_PA3_EOPG_WE', + 191: 'PH_SC1_PA3_DEALLOC_4_0_RD', + 192: 'PH_SC1_PA4_DATA_FIFO_RD', + 193: 'PH_SC1_PA4_DATA_FIFO_WE', + 194: 'PH_SC1_PA4_FIFO_EMPTY', + 195: 'PH_SC1_PA4_FIFO_FULL', + 196: 'PH_SC1_PA4_NULL_WE', + 197: 'PH_SC1_PA4_EVENT_WE', + 198: 'PH_SC1_PA4_FPOV_WE', + 199: 'PH_SC1_PA4_LPOV_WE', + 200: 'PH_SC1_PA4_EOP_WE', + 201: 'PH_SC1_PA4_DATA_FIFO_EOP_RD', + 202: 'PH_SC1_PA4_EOPG_WE', + 203: 'PH_SC1_PA4_DEALLOC_4_0_RD', + 204: 'PH_SC1_PA5_DATA_FIFO_RD', + 205: 'PH_SC1_PA5_DATA_FIFO_WE', + 206: 'PH_SC1_PA5_FIFO_EMPTY', + 207: 'PH_SC1_PA5_FIFO_FULL', + 208: 'PH_SC1_PA5_NULL_WE', + 209: 'PH_SC1_PA5_EVENT_WE', + 210: 'PH_SC1_PA5_FPOV_WE', + 211: 'PH_SC1_PA5_LPOV_WE', + 212: 'PH_SC1_PA5_EOP_WE', + 213: 'PH_SC1_PA5_DATA_FIFO_EOP_RD', + 214: 'PH_SC1_PA5_EOPG_WE', + 215: 'PH_SC1_PA5_DEALLOC_4_0_RD', + 216: 'PH_SC1_PA6_DATA_FIFO_RD', + 217: 'PH_SC1_PA6_DATA_FIFO_WE', + 218: 'PH_SC1_PA6_FIFO_EMPTY', + 219: 'PH_SC1_PA6_FIFO_FULL', + 220: 'PH_SC1_PA6_NULL_WE', + 221: 'PH_SC1_PA6_EVENT_WE', + 222: 'PH_SC1_PA6_FPOV_WE', + 223: 'PH_SC1_PA6_LPOV_WE', + 224: 'PH_SC1_PA6_EOP_WE', + 225: 'PH_SC1_PA6_DATA_FIFO_EOP_RD', + 226: 'PH_SC1_PA6_EOPG_WE', + 227: 'PH_SC1_PA6_DEALLOC_4_0_RD', + 228: 'PH_SC1_PA7_DATA_FIFO_RD', + 229: 'PH_SC1_PA7_DATA_FIFO_WE', + 230: 'PH_SC1_PA7_FIFO_EMPTY', + 231: 'PH_SC1_PA7_FIFO_FULL', + 232: 'PH_SC1_PA7_NULL_WE', + 233: 'PH_SC1_PA7_EVENT_WE', + 234: 'PH_SC1_PA7_FPOV_WE', + 235: 'PH_SC1_PA7_LPOV_WE', + 236: 'PH_SC1_PA7_EOP_WE', + 237: 'PH_SC1_PA7_DATA_FIFO_EOP_RD', + 238: 'PH_SC1_PA7_EOPG_WE', + 239: 'PH_SC1_PA7_DEALLOC_4_0_RD', + 240: 'PH_SC2_SRPS_WINDOW_VALID', + 241: 'PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 242: 'PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES', + 243: 'PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 244: 'PH_SC2_ARB_STALLED_FROM_BELOW', + 245: 'PH_SC2_ARB_STARVED_FROM_ABOVE', + 246: 'PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 247: 'PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 248: 'PH_SC2_ARB_BUSY', + 249: 'PH_SC2_ARB_PA_BUSY_SOP', + 250: 'PH_SC2_ARB_EOP_POP_SYNC_POP', + 251: 'PH_SC2_ARB_EVENT_SYNC_POP', + 252: 'PH_SC2_PS_ENG_MULTICYCLE_BUBBLE', + 253: 'PH_SC2_EOP_SYNC_WINDOW', + 254: 'PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', + 255: 'PH_SC2_BUSY_CNT_NOT_ZERO', + 256: 'PH_SC2_SEND', + 257: 'PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 258: 'PH_SC2_CREDIT_AT_MAX', + 259: 'PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', + 260: 'PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 261: 'PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 262: 'PH_SC2_GFX_PIPE0_TO_1_TRANSITION', + 263: 'PH_SC2_GFX_PIPE1_TO_0_TRANSITION', + 264: 'PH_SC2_PA0_DATA_FIFO_RD', + 265: 'PH_SC2_PA0_DATA_FIFO_WE', + 266: 'PH_SC2_PA0_FIFO_EMPTY', + 267: 'PH_SC2_PA0_FIFO_FULL', + 268: 'PH_SC2_PA0_NULL_WE', + 269: 'PH_SC2_PA0_EVENT_WE', + 270: 'PH_SC2_PA0_FPOV_WE', + 271: 'PH_SC2_PA0_LPOV_WE', + 272: 'PH_SC2_PA0_EOP_WE', + 273: 'PH_SC2_PA0_DATA_FIFO_EOP_RD', + 274: 'PH_SC2_PA0_EOPG_WE', + 275: 'PH_SC2_PA0_DEALLOC_4_0_RD', + 276: 'PH_SC2_PA1_DATA_FIFO_RD', + 277: 'PH_SC2_PA1_DATA_FIFO_WE', + 278: 'PH_SC2_PA1_FIFO_EMPTY', + 279: 'PH_SC2_PA1_FIFO_FULL', + 280: 'PH_SC2_PA1_NULL_WE', + 281: 'PH_SC2_PA1_EVENT_WE', + 282: 'PH_SC2_PA1_FPOV_WE', + 283: 'PH_SC2_PA1_LPOV_WE', + 284: 'PH_SC2_PA1_EOP_WE', + 285: 'PH_SC2_PA1_DATA_FIFO_EOP_RD', + 286: 'PH_SC2_PA1_EOPG_WE', + 287: 'PH_SC2_PA1_DEALLOC_4_0_RD', + 288: 'PH_SC2_PA2_DATA_FIFO_RD', + 289: 'PH_SC2_PA2_DATA_FIFO_WE', + 290: 'PH_SC2_PA2_FIFO_EMPTY', + 291: 'PH_SC2_PA2_FIFO_FULL', + 292: 'PH_SC2_PA2_NULL_WE', + 293: 'PH_SC2_PA2_EVENT_WE', + 294: 'PH_SC2_PA2_FPOV_WE', + 295: 'PH_SC2_PA2_LPOV_WE', + 296: 'PH_SC2_PA2_EOP_WE', + 297: 'PH_SC2_PA2_DATA_FIFO_EOP_RD', + 298: 'PH_SC2_PA2_EOPG_WE', + 299: 'PH_SC2_PA2_DEALLOC_4_0_RD', + 300: 'PH_SC2_PA3_DATA_FIFO_RD', + 301: 'PH_SC2_PA3_DATA_FIFO_WE', + 302: 'PH_SC2_PA3_FIFO_EMPTY', + 303: 'PH_SC2_PA3_FIFO_FULL', + 304: 'PH_SC2_PA3_NULL_WE', + 305: 'PH_SC2_PA3_EVENT_WE', + 306: 'PH_SC2_PA3_FPOV_WE', + 307: 'PH_SC2_PA3_LPOV_WE', + 308: 'PH_SC2_PA3_EOP_WE', + 309: 'PH_SC2_PA3_DATA_FIFO_EOP_RD', + 310: 'PH_SC2_PA3_EOPG_WE', + 311: 'PH_SC2_PA3_DEALLOC_4_0_RD', + 312: 'PH_SC2_PA4_DATA_FIFO_RD', + 313: 'PH_SC2_PA4_DATA_FIFO_WE', + 314: 'PH_SC2_PA4_FIFO_EMPTY', + 315: 'PH_SC2_PA4_FIFO_FULL', + 316: 'PH_SC2_PA4_NULL_WE', + 317: 'PH_SC2_PA4_EVENT_WE', + 318: 'PH_SC2_PA4_FPOV_WE', + 319: 'PH_SC2_PA4_LPOV_WE', + 320: 'PH_SC2_PA4_EOP_WE', + 321: 'PH_SC2_PA4_DATA_FIFO_EOP_RD', + 322: 'PH_SC2_PA4_EOPG_WE', + 323: 'PH_SC2_PA4_DEALLOC_4_0_RD', + 324: 'PH_SC2_PA5_DATA_FIFO_RD', + 325: 'PH_SC2_PA5_DATA_FIFO_WE', + 326: 'PH_SC2_PA5_FIFO_EMPTY', + 327: 'PH_SC2_PA5_FIFO_FULL', + 328: 'PH_SC2_PA5_NULL_WE', + 329: 'PH_SC2_PA5_EVENT_WE', + 330: 'PH_SC2_PA5_FPOV_WE', + 331: 'PH_SC2_PA5_LPOV_WE', + 332: 'PH_SC2_PA5_EOP_WE', + 333: 'PH_SC2_PA5_DATA_FIFO_EOP_RD', + 334: 'PH_SC2_PA5_EOPG_WE', + 335: 'PH_SC2_PA5_DEALLOC_4_0_RD', + 336: 'PH_SC2_PA6_DATA_FIFO_RD', + 337: 'PH_SC2_PA6_DATA_FIFO_WE', + 338: 'PH_SC2_PA6_FIFO_EMPTY', + 339: 'PH_SC2_PA6_FIFO_FULL', + 340: 'PH_SC2_PA6_NULL_WE', + 341: 'PH_SC2_PA6_EVENT_WE', + 342: 'PH_SC2_PA6_FPOV_WE', + 343: 'PH_SC2_PA6_LPOV_WE', + 344: 'PH_SC2_PA6_EOP_WE', + 345: 'PH_SC2_PA6_DATA_FIFO_EOP_RD', + 346: 'PH_SC2_PA6_EOPG_WE', + 347: 'PH_SC2_PA6_DEALLOC_4_0_RD', + 348: 'PH_SC2_PA7_DATA_FIFO_RD', + 349: 'PH_SC2_PA7_DATA_FIFO_WE', + 350: 'PH_SC2_PA7_FIFO_EMPTY', + 351: 'PH_SC2_PA7_FIFO_FULL', + 352: 'PH_SC2_PA7_NULL_WE', + 353: 'PH_SC2_PA7_EVENT_WE', + 354: 'PH_SC2_PA7_FPOV_WE', + 355: 'PH_SC2_PA7_LPOV_WE', + 356: 'PH_SC2_PA7_EOP_WE', + 357: 'PH_SC2_PA7_DATA_FIFO_EOP_RD', + 358: 'PH_SC2_PA7_EOPG_WE', + 359: 'PH_SC2_PA7_DEALLOC_4_0_RD', + 360: 'PH_SC3_SRPS_WINDOW_VALID', + 361: 'PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 362: 'PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES', + 363: 'PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 364: 'PH_SC3_ARB_STALLED_FROM_BELOW', + 365: 'PH_SC3_ARB_STARVED_FROM_ABOVE', + 366: 'PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 367: 'PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 368: 'PH_SC3_ARB_BUSY', + 369: 'PH_SC3_ARB_PA_BUSY_SOP', + 370: 'PH_SC3_ARB_EOP_POP_SYNC_POP', + 371: 'PH_SC3_ARB_EVENT_SYNC_POP', + 372: 'PH_SC3_PS_ENG_MULTICYCLE_BUBBLE', + 373: 'PH_SC3_EOP_SYNC_WINDOW', + 374: 'PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', + 375: 'PH_SC3_BUSY_CNT_NOT_ZERO', + 376: 'PH_SC3_SEND', + 377: 'PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 378: 'PH_SC3_CREDIT_AT_MAX', + 379: 'PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', + 380: 'PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 381: 'PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 382: 'PH_SC3_GFX_PIPE0_TO_1_TRANSITION', + 383: 'PH_SC3_GFX_PIPE1_TO_0_TRANSITION', + 384: 'PH_SC3_PA0_DATA_FIFO_RD', + 385: 'PH_SC3_PA0_DATA_FIFO_WE', + 386: 'PH_SC3_PA0_FIFO_EMPTY', + 387: 'PH_SC3_PA0_FIFO_FULL', + 388: 'PH_SC3_PA0_NULL_WE', + 389: 'PH_SC3_PA0_EVENT_WE', + 390: 'PH_SC3_PA0_FPOV_WE', + 391: 'PH_SC3_PA0_LPOV_WE', + 392: 'PH_SC3_PA0_EOP_WE', + 393: 'PH_SC3_PA0_DATA_FIFO_EOP_RD', + 394: 'PH_SC3_PA0_EOPG_WE', + 395: 'PH_SC3_PA0_DEALLOC_4_0_RD', + 396: 'PH_SC3_PA1_DATA_FIFO_RD', + 397: 'PH_SC3_PA1_DATA_FIFO_WE', + 398: 'PH_SC3_PA1_FIFO_EMPTY', + 399: 'PH_SC3_PA1_FIFO_FULL', + 400: 'PH_SC3_PA1_NULL_WE', + 401: 'PH_SC3_PA1_EVENT_WE', + 402: 'PH_SC3_PA1_FPOV_WE', + 403: 'PH_SC3_PA1_LPOV_WE', + 404: 'PH_SC3_PA1_EOP_WE', + 405: 'PH_SC3_PA1_DATA_FIFO_EOP_RD', + 406: 'PH_SC3_PA1_EOPG_WE', + 407: 'PH_SC3_PA1_DEALLOC_4_0_RD', + 408: 'PH_SC3_PA2_DATA_FIFO_RD', + 409: 'PH_SC3_PA2_DATA_FIFO_WE', + 410: 'PH_SC3_PA2_FIFO_EMPTY', + 411: 'PH_SC3_PA2_FIFO_FULL', + 412: 'PH_SC3_PA2_NULL_WE', + 413: 'PH_SC3_PA2_EVENT_WE', + 414: 'PH_SC3_PA2_FPOV_WE', + 415: 'PH_SC3_PA2_LPOV_WE', + 416: 'PH_SC3_PA2_EOP_WE', + 417: 'PH_SC3_PA2_DATA_FIFO_EOP_RD', + 418: 'PH_SC3_PA2_EOPG_WE', + 419: 'PH_SC3_PA2_DEALLOC_4_0_RD', + 420: 'PH_SC3_PA3_DATA_FIFO_RD', + 421: 'PH_SC3_PA3_DATA_FIFO_WE', + 422: 'PH_SC3_PA3_FIFO_EMPTY', + 423: 'PH_SC3_PA3_FIFO_FULL', + 424: 'PH_SC3_PA3_NULL_WE', + 425: 'PH_SC3_PA3_EVENT_WE', + 426: 'PH_SC3_PA3_FPOV_WE', + 427: 'PH_SC3_PA3_LPOV_WE', + 428: 'PH_SC3_PA3_EOP_WE', + 429: 'PH_SC3_PA3_DATA_FIFO_EOP_RD', + 430: 'PH_SC3_PA3_EOPG_WE', + 431: 'PH_SC3_PA3_DEALLOC_4_0_RD', + 432: 'PH_SC3_PA4_DATA_FIFO_RD', + 433: 'PH_SC3_PA4_DATA_FIFO_WE', + 434: 'PH_SC3_PA4_FIFO_EMPTY', + 435: 'PH_SC3_PA4_FIFO_FULL', + 436: 'PH_SC3_PA4_NULL_WE', + 437: 'PH_SC3_PA4_EVENT_WE', + 438: 'PH_SC3_PA4_FPOV_WE', + 439: 'PH_SC3_PA4_LPOV_WE', + 440: 'PH_SC3_PA4_EOP_WE', + 441: 'PH_SC3_PA4_DATA_FIFO_EOP_RD', + 442: 'PH_SC3_PA4_EOPG_WE', + 443: 'PH_SC3_PA4_DEALLOC_4_0_RD', + 444: 'PH_SC3_PA5_DATA_FIFO_RD', + 445: 'PH_SC3_PA5_DATA_FIFO_WE', + 446: 'PH_SC3_PA5_FIFO_EMPTY', + 447: 'PH_SC3_PA5_FIFO_FULL', + 448: 'PH_SC3_PA5_NULL_WE', + 449: 'PH_SC3_PA5_EVENT_WE', + 450: 'PH_SC3_PA5_FPOV_WE', + 451: 'PH_SC3_PA5_LPOV_WE', + 452: 'PH_SC3_PA5_EOP_WE', + 453: 'PH_SC3_PA5_DATA_FIFO_EOP_RD', + 454: 'PH_SC3_PA5_EOPG_WE', + 455: 'PH_SC3_PA5_DEALLOC_4_0_RD', + 456: 'PH_SC3_PA6_DATA_FIFO_RD', + 457: 'PH_SC3_PA6_DATA_FIFO_WE', + 458: 'PH_SC3_PA6_FIFO_EMPTY', + 459: 'PH_SC3_PA6_FIFO_FULL', + 460: 'PH_SC3_PA6_NULL_WE', + 461: 'PH_SC3_PA6_EVENT_WE', + 462: 'PH_SC3_PA6_FPOV_WE', + 463: 'PH_SC3_PA6_LPOV_WE', + 464: 'PH_SC3_PA6_EOP_WE', + 465: 'PH_SC3_PA6_DATA_FIFO_EOP_RD', + 466: 'PH_SC3_PA6_EOPG_WE', + 467: 'PH_SC3_PA6_DEALLOC_4_0_RD', + 468: 'PH_SC3_PA7_DATA_FIFO_RD', + 469: 'PH_SC3_PA7_DATA_FIFO_WE', + 470: 'PH_SC3_PA7_FIFO_EMPTY', + 471: 'PH_SC3_PA7_FIFO_FULL', + 472: 'PH_SC3_PA7_NULL_WE', + 473: 'PH_SC3_PA7_EVENT_WE', + 474: 'PH_SC3_PA7_FPOV_WE', + 475: 'PH_SC3_PA7_LPOV_WE', + 476: 'PH_SC3_PA7_EOP_WE', + 477: 'PH_SC3_PA7_DATA_FIFO_EOP_RD', + 478: 'PH_SC3_PA7_EOPG_WE', + 479: 'PH_SC3_PA7_DEALLOC_4_0_RD', + 480: 'PH_SC4_SRPS_WINDOW_VALID', + 481: 'PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 482: 'PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES', + 483: 'PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 484: 'PH_SC4_ARB_STALLED_FROM_BELOW', + 485: 'PH_SC4_ARB_STARVED_FROM_ABOVE', + 486: 'PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 487: 'PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 488: 'PH_SC4_ARB_BUSY', + 489: 'PH_SC4_ARB_PA_BUSY_SOP', + 490: 'PH_SC4_ARB_EOP_POP_SYNC_POP', + 491: 'PH_SC4_ARB_EVENT_SYNC_POP', + 492: 'PH_SC4_PS_ENG_MULTICYCLE_BUBBLE', + 493: 'PH_SC4_EOP_SYNC_WINDOW', + 494: 'PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', + 495: 'PH_SC4_BUSY_CNT_NOT_ZERO', + 496: 'PH_SC4_SEND', + 497: 'PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 498: 'PH_SC4_CREDIT_AT_MAX', + 499: 'PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', + 500: 'PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 501: 'PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 502: 'PH_SC4_GFX_PIPE0_TO_1_TRANSITION', + 503: 'PH_SC4_GFX_PIPE1_TO_0_TRANSITION', + 504: 'PH_SC4_PA0_DATA_FIFO_RD', + 505: 'PH_SC4_PA0_DATA_FIFO_WE', + 506: 'PH_SC4_PA0_FIFO_EMPTY', + 507: 'PH_SC4_PA0_FIFO_FULL', + 508: 'PH_SC4_PA0_NULL_WE', + 509: 'PH_SC4_PA0_EVENT_WE', + 510: 'PH_SC4_PA0_FPOV_WE', + 511: 'PH_SC4_PA0_LPOV_WE', + 512: 'PH_SC4_PA0_EOP_WE', + 513: 'PH_SC4_PA0_DATA_FIFO_EOP_RD', + 514: 'PH_SC4_PA0_EOPG_WE', + 515: 'PH_SC4_PA0_DEALLOC_4_0_RD', + 516: 'PH_SC4_PA1_DATA_FIFO_RD', + 517: 'PH_SC4_PA1_DATA_FIFO_WE', + 518: 'PH_SC4_PA1_FIFO_EMPTY', + 519: 'PH_SC4_PA1_FIFO_FULL', + 520: 'PH_SC4_PA1_NULL_WE', + 521: 'PH_SC4_PA1_EVENT_WE', + 522: 'PH_SC4_PA1_FPOV_WE', + 523: 'PH_SC4_PA1_LPOV_WE', + 524: 'PH_SC4_PA1_EOP_WE', + 525: 'PH_SC4_PA1_DATA_FIFO_EOP_RD', + 526: 'PH_SC4_PA1_EOPG_WE', + 527: 'PH_SC4_PA1_DEALLOC_4_0_RD', + 528: 'PH_SC4_PA2_DATA_FIFO_RD', + 529: 'PH_SC4_PA2_DATA_FIFO_WE', + 530: 'PH_SC4_PA2_FIFO_EMPTY', + 531: 'PH_SC4_PA2_FIFO_FULL', + 532: 'PH_SC4_PA2_NULL_WE', + 533: 'PH_SC4_PA2_EVENT_WE', + 534: 'PH_SC4_PA2_FPOV_WE', + 535: 'PH_SC4_PA2_LPOV_WE', + 536: 'PH_SC4_PA2_EOP_WE', + 537: 'PH_SC4_PA2_DATA_FIFO_EOP_RD', + 538: 'PH_SC4_PA2_EOPG_WE', + 539: 'PH_SC4_PA2_DEALLOC_4_0_RD', + 540: 'PH_SC4_PA3_DATA_FIFO_RD', + 541: 'PH_SC4_PA3_DATA_FIFO_WE', + 542: 'PH_SC4_PA3_FIFO_EMPTY', + 543: 'PH_SC4_PA3_FIFO_FULL', + 544: 'PH_SC4_PA3_NULL_WE', + 545: 'PH_SC4_PA3_EVENT_WE', + 546: 'PH_SC4_PA3_FPOV_WE', + 547: 'PH_SC4_PA3_LPOV_WE', + 548: 'PH_SC4_PA3_EOP_WE', + 549: 'PH_SC4_PA3_DATA_FIFO_EOP_RD', + 550: 'PH_SC4_PA3_EOPG_WE', + 551: 'PH_SC4_PA3_DEALLOC_4_0_RD', + 552: 'PH_SC4_PA4_DATA_FIFO_RD', + 553: 'PH_SC4_PA4_DATA_FIFO_WE', + 554: 'PH_SC4_PA4_FIFO_EMPTY', + 555: 'PH_SC4_PA4_FIFO_FULL', + 556: 'PH_SC4_PA4_NULL_WE', + 557: 'PH_SC4_PA4_EVENT_WE', + 558: 'PH_SC4_PA4_FPOV_WE', + 559: 'PH_SC4_PA4_LPOV_WE', + 560: 'PH_SC4_PA4_EOP_WE', + 561: 'PH_SC4_PA4_DATA_FIFO_EOP_RD', + 562: 'PH_SC4_PA4_EOPG_WE', + 563: 'PH_SC4_PA4_DEALLOC_4_0_RD', + 564: 'PH_SC4_PA5_DATA_FIFO_RD', + 565: 'PH_SC4_PA5_DATA_FIFO_WE', + 566: 'PH_SC4_PA5_FIFO_EMPTY', + 567: 'PH_SC4_PA5_FIFO_FULL', + 568: 'PH_SC4_PA5_NULL_WE', + 569: 'PH_SC4_PA5_EVENT_WE', + 570: 'PH_SC4_PA5_FPOV_WE', + 571: 'PH_SC4_PA5_LPOV_WE', + 572: 'PH_SC4_PA5_EOP_WE', + 573: 'PH_SC4_PA5_DATA_FIFO_EOP_RD', + 574: 'PH_SC4_PA5_EOPG_WE', + 575: 'PH_SC4_PA5_DEALLOC_4_0_RD', + 576: 'PH_SC4_PA6_DATA_FIFO_RD', + 577: 'PH_SC4_PA6_DATA_FIFO_WE', + 578: 'PH_SC4_PA6_FIFO_EMPTY', + 579: 'PH_SC4_PA6_FIFO_FULL', + 580: 'PH_SC4_PA6_NULL_WE', + 581: 'PH_SC4_PA6_EVENT_WE', + 582: 'PH_SC4_PA6_FPOV_WE', + 583: 'PH_SC4_PA6_LPOV_WE', + 584: 'PH_SC4_PA6_EOP_WE', + 585: 'PH_SC4_PA6_DATA_FIFO_EOP_RD', + 586: 'PH_SC4_PA6_EOPG_WE', + 587: 'PH_SC4_PA6_DEALLOC_4_0_RD', + 588: 'PH_SC4_PA7_DATA_FIFO_RD', + 589: 'PH_SC4_PA7_DATA_FIFO_WE', + 590: 'PH_SC4_PA7_FIFO_EMPTY', + 591: 'PH_SC4_PA7_FIFO_FULL', + 592: 'PH_SC4_PA7_NULL_WE', + 593: 'PH_SC4_PA7_EVENT_WE', + 594: 'PH_SC4_PA7_FPOV_WE', + 595: 'PH_SC4_PA7_LPOV_WE', + 596: 'PH_SC4_PA7_EOP_WE', + 597: 'PH_SC4_PA7_DATA_FIFO_EOP_RD', + 598: 'PH_SC4_PA7_EOPG_WE', + 599: 'PH_SC4_PA7_DEALLOC_4_0_RD', + 600: 'PH_SC5_SRPS_WINDOW_VALID', + 601: 'PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 602: 'PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES', + 603: 'PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 604: 'PH_SC5_ARB_STALLED_FROM_BELOW', + 605: 'PH_SC5_ARB_STARVED_FROM_ABOVE', + 606: 'PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 607: 'PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 608: 'PH_SC5_ARB_BUSY', + 609: 'PH_SC5_ARB_PA_BUSY_SOP', + 610: 'PH_SC5_ARB_EOP_POP_SYNC_POP', + 611: 'PH_SC5_ARB_EVENT_SYNC_POP', + 612: 'PH_SC5_PS_ENG_MULTICYCLE_BUBBLE', + 613: 'PH_SC5_EOP_SYNC_WINDOW', + 614: 'PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', + 615: 'PH_SC5_BUSY_CNT_NOT_ZERO', + 616: 'PH_SC5_SEND', + 617: 'PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 618: 'PH_SC5_CREDIT_AT_MAX', + 619: 'PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', + 620: 'PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 621: 'PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 622: 'PH_SC5_GFX_PIPE0_TO_1_TRANSITION', + 623: 'PH_SC5_GFX_PIPE1_TO_0_TRANSITION', + 624: 'PH_SC5_PA0_DATA_FIFO_RD', + 625: 'PH_SC5_PA0_DATA_FIFO_WE', + 626: 'PH_SC5_PA0_FIFO_EMPTY', + 627: 'PH_SC5_PA0_FIFO_FULL', + 628: 'PH_SC5_PA0_NULL_WE', + 629: 'PH_SC5_PA0_EVENT_WE', + 630: 'PH_SC5_PA0_FPOV_WE', + 631: 'PH_SC5_PA0_LPOV_WE', + 632: 'PH_SC5_PA0_EOP_WE', + 633: 'PH_SC5_PA0_DATA_FIFO_EOP_RD', + 634: 'PH_SC5_PA0_EOPG_WE', + 635: 'PH_SC5_PA0_DEALLOC_4_0_RD', + 636: 'PH_SC5_PA1_DATA_FIFO_RD', + 637: 'PH_SC5_PA1_DATA_FIFO_WE', + 638: 'PH_SC5_PA1_FIFO_EMPTY', + 639: 'PH_SC5_PA1_FIFO_FULL', + 640: 'PH_SC5_PA1_NULL_WE', + 641: 'PH_SC5_PA1_EVENT_WE', + 642: 'PH_SC5_PA1_FPOV_WE', + 643: 'PH_SC5_PA1_LPOV_WE', + 644: 'PH_SC5_PA1_EOP_WE', + 645: 'PH_SC5_PA1_DATA_FIFO_EOP_RD', + 646: 'PH_SC5_PA1_EOPG_WE', + 647: 'PH_SC5_PA1_DEALLOC_4_0_RD', + 648: 'PH_SC5_PA2_DATA_FIFO_RD', + 649: 'PH_SC5_PA2_DATA_FIFO_WE', + 650: 'PH_SC5_PA2_FIFO_EMPTY', + 651: 'PH_SC5_PA2_FIFO_FULL', + 652: 'PH_SC5_PA2_NULL_WE', + 653: 'PH_SC5_PA2_EVENT_WE', + 654: 'PH_SC5_PA2_FPOV_WE', + 655: 'PH_SC5_PA2_LPOV_WE', + 656: 'PH_SC5_PA2_EOP_WE', + 657: 'PH_SC5_PA2_DATA_FIFO_EOP_RD', + 658: 'PH_SC5_PA2_EOPG_WE', + 659: 'PH_SC5_PA2_DEALLOC_4_0_RD', + 660: 'PH_SC5_PA3_DATA_FIFO_RD', + 661: 'PH_SC5_PA3_DATA_FIFO_WE', + 662: 'PH_SC5_PA3_FIFO_EMPTY', + 663: 'PH_SC5_PA3_FIFO_FULL', + 664: 'PH_SC5_PA3_NULL_WE', + 665: 'PH_SC5_PA3_EVENT_WE', + 666: 'PH_SC5_PA3_FPOV_WE', + 667: 'PH_SC5_PA3_LPOV_WE', + 668: 'PH_SC5_PA3_EOP_WE', + 669: 'PH_SC5_PA3_DATA_FIFO_EOP_RD', + 670: 'PH_SC5_PA3_EOPG_WE', + 671: 'PH_SC5_PA3_DEALLOC_4_0_RD', + 672: 'PH_SC5_PA4_DATA_FIFO_RD', + 673: 'PH_SC5_PA4_DATA_FIFO_WE', + 674: 'PH_SC5_PA4_FIFO_EMPTY', + 675: 'PH_SC5_PA4_FIFO_FULL', + 676: 'PH_SC5_PA4_NULL_WE', + 677: 'PH_SC5_PA4_EVENT_WE', + 678: 'PH_SC5_PA4_FPOV_WE', + 679: 'PH_SC5_PA4_LPOV_WE', + 680: 'PH_SC5_PA4_EOP_WE', + 681: 'PH_SC5_PA4_DATA_FIFO_EOP_RD', + 682: 'PH_SC5_PA4_EOPG_WE', + 683: 'PH_SC5_PA4_DEALLOC_4_0_RD', + 684: 'PH_SC5_PA5_DATA_FIFO_RD', + 685: 'PH_SC5_PA5_DATA_FIFO_WE', + 686: 'PH_SC5_PA5_FIFO_EMPTY', + 687: 'PH_SC5_PA5_FIFO_FULL', + 688: 'PH_SC5_PA5_NULL_WE', + 689: 'PH_SC5_PA5_EVENT_WE', + 690: 'PH_SC5_PA5_FPOV_WE', + 691: 'PH_SC5_PA5_LPOV_WE', + 692: 'PH_SC5_PA5_EOP_WE', + 693: 'PH_SC5_PA5_DATA_FIFO_EOP_RD', + 694: 'PH_SC5_PA5_EOPG_WE', + 695: 'PH_SC5_PA5_DEALLOC_4_0_RD', + 696: 'PH_SC5_PA6_DATA_FIFO_RD', + 697: 'PH_SC5_PA6_DATA_FIFO_WE', + 698: 'PH_SC5_PA6_FIFO_EMPTY', + 699: 'PH_SC5_PA6_FIFO_FULL', + 700: 'PH_SC5_PA6_NULL_WE', + 701: 'PH_SC5_PA6_EVENT_WE', + 702: 'PH_SC5_PA6_FPOV_WE', + 703: 'PH_SC5_PA6_LPOV_WE', + 704: 'PH_SC5_PA6_EOP_WE', + 705: 'PH_SC5_PA6_DATA_FIFO_EOP_RD', + 706: 'PH_SC5_PA6_EOPG_WE', + 707: 'PH_SC5_PA6_DEALLOC_4_0_RD', + 708: 'PH_SC5_PA7_DATA_FIFO_RD', + 709: 'PH_SC5_PA7_DATA_FIFO_WE', + 710: 'PH_SC5_PA7_FIFO_EMPTY', + 711: 'PH_SC5_PA7_FIFO_FULL', + 712: 'PH_SC5_PA7_NULL_WE', + 713: 'PH_SC5_PA7_EVENT_WE', + 714: 'PH_SC5_PA7_FPOV_WE', + 715: 'PH_SC5_PA7_LPOV_WE', + 716: 'PH_SC5_PA7_EOP_WE', + 717: 'PH_SC5_PA7_DATA_FIFO_EOP_RD', + 718: 'PH_SC5_PA7_EOPG_WE', + 719: 'PH_SC5_PA7_DEALLOC_4_0_RD', + 720: 'PH_SC6_SRPS_WINDOW_VALID', + 721: 'PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 722: 'PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES', + 723: 'PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 724: 'PH_SC6_ARB_STALLED_FROM_BELOW', + 725: 'PH_SC6_ARB_STARVED_FROM_ABOVE', + 726: 'PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 727: 'PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 728: 'PH_SC6_ARB_BUSY', + 729: 'PH_SC6_ARB_PA_BUSY_SOP', + 730: 'PH_SC6_ARB_EOP_POP_SYNC_POP', + 731: 'PH_SC6_ARB_EVENT_SYNC_POP', + 732: 'PH_SC6_PS_ENG_MULTICYCLE_BUBBLE', + 733: 'PH_SC6_EOP_SYNC_WINDOW', + 734: 'PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', + 735: 'PH_SC6_BUSY_CNT_NOT_ZERO', + 736: 'PH_SC6_SEND', + 737: 'PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 738: 'PH_SC6_CREDIT_AT_MAX', + 739: 'PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', + 740: 'PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 741: 'PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 742: 'PH_SC6_GFX_PIPE0_TO_1_TRANSITION', + 743: 'PH_SC6_GFX_PIPE1_TO_0_TRANSITION', + 744: 'PH_SC6_PA0_DATA_FIFO_RD', + 745: 'PH_SC6_PA0_DATA_FIFO_WE', + 746: 'PH_SC6_PA0_FIFO_EMPTY', + 747: 'PH_SC6_PA0_FIFO_FULL', + 748: 'PH_SC6_PA0_NULL_WE', + 749: 'PH_SC6_PA0_EVENT_WE', + 750: 'PH_SC6_PA0_FPOV_WE', + 751: 'PH_SC6_PA0_LPOV_WE', + 752: 'PH_SC6_PA0_EOP_WE', + 753: 'PH_SC6_PA0_DATA_FIFO_EOP_RD', + 754: 'PH_SC6_PA0_EOPG_WE', + 755: 'PH_SC6_PA0_DEALLOC_4_0_RD', + 756: 'PH_SC6_PA1_DATA_FIFO_RD', + 757: 'PH_SC6_PA1_DATA_FIFO_WE', + 758: 'PH_SC6_PA1_FIFO_EMPTY', + 759: 'PH_SC6_PA1_FIFO_FULL', + 760: 'PH_SC6_PA1_NULL_WE', + 761: 'PH_SC6_PA1_EVENT_WE', + 762: 'PH_SC6_PA1_FPOV_WE', + 763: 'PH_SC6_PA1_LPOV_WE', + 764: 'PH_SC6_PA1_EOP_WE', + 765: 'PH_SC6_PA1_DATA_FIFO_EOP_RD', + 766: 'PH_SC6_PA1_EOPG_WE', + 767: 'PH_SC6_PA1_DEALLOC_4_0_RD', + 768: 'PH_SC6_PA2_DATA_FIFO_RD', + 769: 'PH_SC6_PA2_DATA_FIFO_WE', + 770: 'PH_SC6_PA2_FIFO_EMPTY', + 771: 'PH_SC6_PA2_FIFO_FULL', + 772: 'PH_SC6_PA2_NULL_WE', + 773: 'PH_SC6_PA2_EVENT_WE', + 774: 'PH_SC6_PA2_FPOV_WE', + 775: 'PH_SC6_PA2_LPOV_WE', + 776: 'PH_SC6_PA2_EOP_WE', + 777: 'PH_SC6_PA2_DATA_FIFO_EOP_RD', + 778: 'PH_SC6_PA2_EOPG_WE', + 779: 'PH_SC6_PA2_DEALLOC_4_0_RD', + 780: 'PH_SC6_PA3_DATA_FIFO_RD', + 781: 'PH_SC6_PA3_DATA_FIFO_WE', + 782: 'PH_SC6_PA3_FIFO_EMPTY', + 783: 'PH_SC6_PA3_FIFO_FULL', + 784: 'PH_SC6_PA3_NULL_WE', + 785: 'PH_SC6_PA3_EVENT_WE', + 786: 'PH_SC6_PA3_FPOV_WE', + 787: 'PH_SC6_PA3_LPOV_WE', + 788: 'PH_SC6_PA3_EOP_WE', + 789: 'PH_SC6_PA3_DATA_FIFO_EOP_RD', + 790: 'PH_SC6_PA3_EOPG_WE', + 791: 'PH_SC6_PA3_DEALLOC_4_0_RD', + 792: 'PH_SC6_PA4_DATA_FIFO_RD', + 793: 'PH_SC6_PA4_DATA_FIFO_WE', + 794: 'PH_SC6_PA4_FIFO_EMPTY', + 795: 'PH_SC6_PA4_FIFO_FULL', + 796: 'PH_SC6_PA4_NULL_WE', + 797: 'PH_SC6_PA4_EVENT_WE', + 798: 'PH_SC6_PA4_FPOV_WE', + 799: 'PH_SC6_PA4_LPOV_WE', + 800: 'PH_SC6_PA4_EOP_WE', + 801: 'PH_SC6_PA4_DATA_FIFO_EOP_RD', + 802: 'PH_SC6_PA4_EOPG_WE', + 803: 'PH_SC6_PA4_DEALLOC_4_0_RD', + 804: 'PH_SC6_PA5_DATA_FIFO_RD', + 805: 'PH_SC6_PA5_DATA_FIFO_WE', + 806: 'PH_SC6_PA5_FIFO_EMPTY', + 807: 'PH_SC6_PA5_FIFO_FULL', + 808: 'PH_SC6_PA5_NULL_WE', + 809: 'PH_SC6_PA5_EVENT_WE', + 810: 'PH_SC6_PA5_FPOV_WE', + 811: 'PH_SC6_PA5_LPOV_WE', + 812: 'PH_SC6_PA5_EOP_WE', + 813: 'PH_SC6_PA5_DATA_FIFO_EOP_RD', + 814: 'PH_SC6_PA5_EOPG_WE', + 815: 'PH_SC6_PA5_DEALLOC_4_0_RD', + 816: 'PH_SC6_PA6_DATA_FIFO_RD', + 817: 'PH_SC6_PA6_DATA_FIFO_WE', + 818: 'PH_SC6_PA6_FIFO_EMPTY', + 819: 'PH_SC6_PA6_FIFO_FULL', + 820: 'PH_SC6_PA6_NULL_WE', + 821: 'PH_SC6_PA6_EVENT_WE', + 822: 'PH_SC6_PA6_FPOV_WE', + 823: 'PH_SC6_PA6_LPOV_WE', + 824: 'PH_SC6_PA6_EOP_WE', + 825: 'PH_SC6_PA6_DATA_FIFO_EOP_RD', + 826: 'PH_SC6_PA6_EOPG_WE', + 827: 'PH_SC6_PA6_DEALLOC_4_0_RD', + 828: 'PH_SC6_PA7_DATA_FIFO_RD', + 829: 'PH_SC6_PA7_DATA_FIFO_WE', + 830: 'PH_SC6_PA7_FIFO_EMPTY', + 831: 'PH_SC6_PA7_FIFO_FULL', + 832: 'PH_SC6_PA7_NULL_WE', + 833: 'PH_SC6_PA7_EVENT_WE', + 834: 'PH_SC6_PA7_FPOV_WE', + 835: 'PH_SC6_PA7_LPOV_WE', + 836: 'PH_SC6_PA7_EOP_WE', + 837: 'PH_SC6_PA7_DATA_FIFO_EOP_RD', + 838: 'PH_SC6_PA7_EOPG_WE', + 839: 'PH_SC6_PA7_DEALLOC_4_0_RD', + 840: 'PH_SC7_SRPS_WINDOW_VALID', + 841: 'PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 842: 'PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES', + 843: 'PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 844: 'PH_SC7_ARB_STALLED_FROM_BELOW', + 845: 'PH_SC7_ARB_STARVED_FROM_ABOVE', + 846: 'PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 847: 'PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 848: 'PH_SC7_ARB_BUSY', + 849: 'PH_SC7_ARB_PA_BUSY_SOP', + 850: 'PH_SC7_ARB_EOP_POP_SYNC_POP', + 851: 'PH_SC7_ARB_EVENT_SYNC_POP', + 852: 'PH_SC7_PS_ENG_MULTICYCLE_BUBBLE', + 853: 'PH_SC7_EOP_SYNC_WINDOW', + 854: 'PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', + 855: 'PH_SC7_BUSY_CNT_NOT_ZERO', + 856: 'PH_SC7_SEND', + 857: 'PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 858: 'PH_SC7_CREDIT_AT_MAX', + 859: 'PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', + 860: 'PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 861: 'PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 862: 'PH_SC7_GFX_PIPE0_TO_1_TRANSITION', + 863: 'PH_SC7_GFX_PIPE1_TO_0_TRANSITION', + 864: 'PH_SC7_PA0_DATA_FIFO_RD', + 865: 'PH_SC7_PA0_DATA_FIFO_WE', + 866: 'PH_SC7_PA0_FIFO_EMPTY', + 867: 'PH_SC7_PA0_FIFO_FULL', + 868: 'PH_SC7_PA0_NULL_WE', + 869: 'PH_SC7_PA0_EVENT_WE', + 870: 'PH_SC7_PA0_FPOV_WE', + 871: 'PH_SC7_PA0_LPOV_WE', + 872: 'PH_SC7_PA0_EOP_WE', + 873: 'PH_SC7_PA0_DATA_FIFO_EOP_RD', + 874: 'PH_SC7_PA0_EOPG_WE', + 875: 'PH_SC7_PA0_DEALLOC_4_0_RD', + 876: 'PH_SC7_PA1_DATA_FIFO_RD', + 877: 'PH_SC7_PA1_DATA_FIFO_WE', + 878: 'PH_SC7_PA1_FIFO_EMPTY', + 879: 'PH_SC7_PA1_FIFO_FULL', + 880: 'PH_SC7_PA1_NULL_WE', + 881: 'PH_SC7_PA1_EVENT_WE', + 882: 'PH_SC7_PA1_FPOV_WE', + 883: 'PH_SC7_PA1_LPOV_WE', + 884: 'PH_SC7_PA1_EOP_WE', + 885: 'PH_SC7_PA1_DATA_FIFO_EOP_RD', + 886: 'PH_SC7_PA1_EOPG_WE', + 887: 'PH_SC7_PA1_DEALLOC_4_0_RD', + 888: 'PH_SC7_PA2_DATA_FIFO_RD', + 889: 'PH_SC7_PA2_DATA_FIFO_WE', + 890: 'PH_SC7_PA2_FIFO_EMPTY', + 891: 'PH_SC7_PA2_FIFO_FULL', + 892: 'PH_SC7_PA2_NULL_WE', + 893: 'PH_SC7_PA2_EVENT_WE', + 894: 'PH_SC7_PA2_FPOV_WE', + 895: 'PH_SC7_PA2_LPOV_WE', + 896: 'PH_SC7_PA2_EOP_WE', + 897: 'PH_SC7_PA2_DATA_FIFO_EOP_RD', + 898: 'PH_SC7_PA2_EOPG_WE', + 899: 'PH_SC7_PA2_DEALLOC_4_0_RD', + 900: 'PH_SC7_PA3_DATA_FIFO_RD', + 901: 'PH_SC7_PA3_DATA_FIFO_WE', + 902: 'PH_SC7_PA3_FIFO_EMPTY', + 903: 'PH_SC7_PA3_FIFO_FULL', + 904: 'PH_SC7_PA3_NULL_WE', + 905: 'PH_SC7_PA3_EVENT_WE', + 906: 'PH_SC7_PA3_FPOV_WE', + 907: 'PH_SC7_PA3_LPOV_WE', + 908: 'PH_SC7_PA3_EOP_WE', + 909: 'PH_SC7_PA3_DATA_FIFO_EOP_RD', + 910: 'PH_SC7_PA3_EOPG_WE', + 911: 'PH_SC7_PA3_DEALLOC_4_0_RD', + 912: 'PH_SC7_PA4_DATA_FIFO_RD', + 913: 'PH_SC7_PA4_DATA_FIFO_WE', + 914: 'PH_SC7_PA4_FIFO_EMPTY', + 915: 'PH_SC7_PA4_FIFO_FULL', + 916: 'PH_SC7_PA4_NULL_WE', + 917: 'PH_SC7_PA4_EVENT_WE', + 918: 'PH_SC7_PA4_FPOV_WE', + 919: 'PH_SC7_PA4_LPOV_WE', + 920: 'PH_SC7_PA4_EOP_WE', + 921: 'PH_SC7_PA4_DATA_FIFO_EOP_RD', + 922: 'PH_SC7_PA4_EOPG_WE', + 923: 'PH_SC7_PA4_DEALLOC_4_0_RD', + 924: 'PH_SC7_PA5_DATA_FIFO_RD', + 925: 'PH_SC7_PA5_DATA_FIFO_WE', + 926: 'PH_SC7_PA5_FIFO_EMPTY', + 927: 'PH_SC7_PA5_FIFO_FULL', + 928: 'PH_SC7_PA5_NULL_WE', + 929: 'PH_SC7_PA5_EVENT_WE', + 930: 'PH_SC7_PA5_FPOV_WE', + 931: 'PH_SC7_PA5_LPOV_WE', + 932: 'PH_SC7_PA5_EOP_WE', + 933: 'PH_SC7_PA5_DATA_FIFO_EOP_RD', + 934: 'PH_SC7_PA5_EOPG_WE', + 935: 'PH_SC7_PA5_DEALLOC_4_0_RD', + 936: 'PH_SC7_PA6_DATA_FIFO_RD', + 937: 'PH_SC7_PA6_DATA_FIFO_WE', + 938: 'PH_SC7_PA6_FIFO_EMPTY', + 939: 'PH_SC7_PA6_FIFO_FULL', + 940: 'PH_SC7_PA6_NULL_WE', + 941: 'PH_SC7_PA6_EVENT_WE', + 942: 'PH_SC7_PA6_FPOV_WE', + 943: 'PH_SC7_PA6_LPOV_WE', + 944: 'PH_SC7_PA6_EOP_WE', + 945: 'PH_SC7_PA6_DATA_FIFO_EOP_RD', + 946: 'PH_SC7_PA6_EOPG_WE', + 947: 'PH_SC7_PA6_DEALLOC_4_0_RD', + 948: 'PH_SC7_PA7_DATA_FIFO_RD', + 949: 'PH_SC7_PA7_DATA_FIFO_WE', + 950: 'PH_SC7_PA7_FIFO_EMPTY', + 951: 'PH_SC7_PA7_FIFO_FULL', + 952: 'PH_SC7_PA7_NULL_WE', + 953: 'PH_SC7_PA7_EVENT_WE', + 954: 'PH_SC7_PA7_FPOV_WE', + 955: 'PH_SC7_PA7_LPOV_WE', + 956: 'PH_SC7_PA7_EOP_WE', + 957: 'PH_SC7_PA7_DATA_FIFO_EOP_RD', + 958: 'PH_SC7_PA7_EOPG_WE', + 959: 'PH_SC7_PA7_DEALLOC_4_0_RD', +} +PH_SC0_SRPS_WINDOW_VALID = 0 +PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 1 +PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 2 +PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 3 +PH_SC0_ARB_STALLED_FROM_BELOW = 4 +PH_SC0_ARB_STARVED_FROM_ABOVE = 5 +PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 6 +PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 7 +PH_SC0_ARB_BUSY = 8 +PH_SC0_ARB_PA_BUSY_SOP = 9 +PH_SC0_ARB_EOP_POP_SYNC_POP = 10 +PH_SC0_ARB_EVENT_SYNC_POP = 11 +PH_SC0_PS_ENG_MULTICYCLE_BUBBLE = 12 +PH_SC0_EOP_SYNC_WINDOW = 13 +PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 14 +PH_SC0_BUSY_CNT_NOT_ZERO = 15 +PH_SC0_SEND = 16 +PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 17 +PH_SC0_CREDIT_AT_MAX = 18 +PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 19 +PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 20 +PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 21 +PH_SC0_GFX_PIPE0_TO_1_TRANSITION = 22 +PH_SC0_GFX_PIPE1_TO_0_TRANSITION = 23 +PH_SC0_PA0_DATA_FIFO_RD = 24 +PH_SC0_PA0_DATA_FIFO_WE = 25 +PH_SC0_PA0_FIFO_EMPTY = 26 +PH_SC0_PA0_FIFO_FULL = 27 +PH_SC0_PA0_NULL_WE = 28 +PH_SC0_PA0_EVENT_WE = 29 +PH_SC0_PA0_FPOV_WE = 30 +PH_SC0_PA0_LPOV_WE = 31 +PH_SC0_PA0_EOP_WE = 32 +PH_SC0_PA0_DATA_FIFO_EOP_RD = 33 +PH_SC0_PA0_EOPG_WE = 34 +PH_SC0_PA0_DEALLOC_4_0_RD = 35 +PH_SC0_PA1_DATA_FIFO_RD = 36 +PH_SC0_PA1_DATA_FIFO_WE = 37 +PH_SC0_PA1_FIFO_EMPTY = 38 +PH_SC0_PA1_FIFO_FULL = 39 +PH_SC0_PA1_NULL_WE = 40 +PH_SC0_PA1_EVENT_WE = 41 +PH_SC0_PA1_FPOV_WE = 42 +PH_SC0_PA1_LPOV_WE = 43 +PH_SC0_PA1_EOP_WE = 44 +PH_SC0_PA1_DATA_FIFO_EOP_RD = 45 +PH_SC0_PA1_EOPG_WE = 46 +PH_SC0_PA1_DEALLOC_4_0_RD = 47 +PH_SC0_PA2_DATA_FIFO_RD = 48 +PH_SC0_PA2_DATA_FIFO_WE = 49 +PH_SC0_PA2_FIFO_EMPTY = 50 +PH_SC0_PA2_FIFO_FULL = 51 +PH_SC0_PA2_NULL_WE = 52 +PH_SC0_PA2_EVENT_WE = 53 +PH_SC0_PA2_FPOV_WE = 54 +PH_SC0_PA2_LPOV_WE = 55 +PH_SC0_PA2_EOP_WE = 56 +PH_SC0_PA2_DATA_FIFO_EOP_RD = 57 +PH_SC0_PA2_EOPG_WE = 58 +PH_SC0_PA2_DEALLOC_4_0_RD = 59 +PH_SC0_PA3_DATA_FIFO_RD = 60 +PH_SC0_PA3_DATA_FIFO_WE = 61 +PH_SC0_PA3_FIFO_EMPTY = 62 +PH_SC0_PA3_FIFO_FULL = 63 +PH_SC0_PA3_NULL_WE = 64 +PH_SC0_PA3_EVENT_WE = 65 +PH_SC0_PA3_FPOV_WE = 66 +PH_SC0_PA3_LPOV_WE = 67 +PH_SC0_PA3_EOP_WE = 68 +PH_SC0_PA3_DATA_FIFO_EOP_RD = 69 +PH_SC0_PA3_EOPG_WE = 70 +PH_SC0_PA3_DEALLOC_4_0_RD = 71 +PH_SC0_PA4_DATA_FIFO_RD = 72 +PH_SC0_PA4_DATA_FIFO_WE = 73 +PH_SC0_PA4_FIFO_EMPTY = 74 +PH_SC0_PA4_FIFO_FULL = 75 +PH_SC0_PA4_NULL_WE = 76 +PH_SC0_PA4_EVENT_WE = 77 +PH_SC0_PA4_FPOV_WE = 78 +PH_SC0_PA4_LPOV_WE = 79 +PH_SC0_PA4_EOP_WE = 80 +PH_SC0_PA4_DATA_FIFO_EOP_RD = 81 +PH_SC0_PA4_EOPG_WE = 82 +PH_SC0_PA4_DEALLOC_4_0_RD = 83 +PH_SC0_PA5_DATA_FIFO_RD = 84 +PH_SC0_PA5_DATA_FIFO_WE = 85 +PH_SC0_PA5_FIFO_EMPTY = 86 +PH_SC0_PA5_FIFO_FULL = 87 +PH_SC0_PA5_NULL_WE = 88 +PH_SC0_PA5_EVENT_WE = 89 +PH_SC0_PA5_FPOV_WE = 90 +PH_SC0_PA5_LPOV_WE = 91 +PH_SC0_PA5_EOP_WE = 92 +PH_SC0_PA5_DATA_FIFO_EOP_RD = 93 +PH_SC0_PA5_EOPG_WE = 94 +PH_SC0_PA5_DEALLOC_4_0_RD = 95 +PH_SC0_PA6_DATA_FIFO_RD = 96 +PH_SC0_PA6_DATA_FIFO_WE = 97 +PH_SC0_PA6_FIFO_EMPTY = 98 +PH_SC0_PA6_FIFO_FULL = 99 +PH_SC0_PA6_NULL_WE = 100 +PH_SC0_PA6_EVENT_WE = 101 +PH_SC0_PA6_FPOV_WE = 102 +PH_SC0_PA6_LPOV_WE = 103 +PH_SC0_PA6_EOP_WE = 104 +PH_SC0_PA6_DATA_FIFO_EOP_RD = 105 +PH_SC0_PA6_EOPG_WE = 106 +PH_SC0_PA6_DEALLOC_4_0_RD = 107 +PH_SC0_PA7_DATA_FIFO_RD = 108 +PH_SC0_PA7_DATA_FIFO_WE = 109 +PH_SC0_PA7_FIFO_EMPTY = 110 +PH_SC0_PA7_FIFO_FULL = 111 +PH_SC0_PA7_NULL_WE = 112 +PH_SC0_PA7_EVENT_WE = 113 +PH_SC0_PA7_FPOV_WE = 114 +PH_SC0_PA7_LPOV_WE = 115 +PH_SC0_PA7_EOP_WE = 116 +PH_SC0_PA7_DATA_FIFO_EOP_RD = 117 +PH_SC0_PA7_EOPG_WE = 118 +PH_SC0_PA7_DEALLOC_4_0_RD = 119 +PH_SC1_SRPS_WINDOW_VALID = 120 +PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 121 +PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 122 +PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 123 +PH_SC1_ARB_STALLED_FROM_BELOW = 124 +PH_SC1_ARB_STARVED_FROM_ABOVE = 125 +PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 126 +PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 127 +PH_SC1_ARB_BUSY = 128 +PH_SC1_ARB_PA_BUSY_SOP = 129 +PH_SC1_ARB_EOP_POP_SYNC_POP = 130 +PH_SC1_ARB_EVENT_SYNC_POP = 131 +PH_SC1_PS_ENG_MULTICYCLE_BUBBLE = 132 +PH_SC1_EOP_SYNC_WINDOW = 133 +PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 134 +PH_SC1_BUSY_CNT_NOT_ZERO = 135 +PH_SC1_SEND = 136 +PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 137 +PH_SC1_CREDIT_AT_MAX = 138 +PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 139 +PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 140 +PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 141 +PH_SC1_GFX_PIPE0_TO_1_TRANSITION = 142 +PH_SC1_GFX_PIPE1_TO_0_TRANSITION = 143 +PH_SC1_PA0_DATA_FIFO_RD = 144 +PH_SC1_PA0_DATA_FIFO_WE = 145 +PH_SC1_PA0_FIFO_EMPTY = 146 +PH_SC1_PA0_FIFO_FULL = 147 +PH_SC1_PA0_NULL_WE = 148 +PH_SC1_PA0_EVENT_WE = 149 +PH_SC1_PA0_FPOV_WE = 150 +PH_SC1_PA0_LPOV_WE = 151 +PH_SC1_PA0_EOP_WE = 152 +PH_SC1_PA0_DATA_FIFO_EOP_RD = 153 +PH_SC1_PA0_EOPG_WE = 154 +PH_SC1_PA0_DEALLOC_4_0_RD = 155 +PH_SC1_PA1_DATA_FIFO_RD = 156 +PH_SC1_PA1_DATA_FIFO_WE = 157 +PH_SC1_PA1_FIFO_EMPTY = 158 +PH_SC1_PA1_FIFO_FULL = 159 +PH_SC1_PA1_NULL_WE = 160 +PH_SC1_PA1_EVENT_WE = 161 +PH_SC1_PA1_FPOV_WE = 162 +PH_SC1_PA1_LPOV_WE = 163 +PH_SC1_PA1_EOP_WE = 164 +PH_SC1_PA1_DATA_FIFO_EOP_RD = 165 +PH_SC1_PA1_EOPG_WE = 166 +PH_SC1_PA1_DEALLOC_4_0_RD = 167 +PH_SC1_PA2_DATA_FIFO_RD = 168 +PH_SC1_PA2_DATA_FIFO_WE = 169 +PH_SC1_PA2_FIFO_EMPTY = 170 +PH_SC1_PA2_FIFO_FULL = 171 +PH_SC1_PA2_NULL_WE = 172 +PH_SC1_PA2_EVENT_WE = 173 +PH_SC1_PA2_FPOV_WE = 174 +PH_SC1_PA2_LPOV_WE = 175 +PH_SC1_PA2_EOP_WE = 176 +PH_SC1_PA2_DATA_FIFO_EOP_RD = 177 +PH_SC1_PA2_EOPG_WE = 178 +PH_SC1_PA2_DEALLOC_4_0_RD = 179 +PH_SC1_PA3_DATA_FIFO_RD = 180 +PH_SC1_PA3_DATA_FIFO_WE = 181 +PH_SC1_PA3_FIFO_EMPTY = 182 +PH_SC1_PA3_FIFO_FULL = 183 +PH_SC1_PA3_NULL_WE = 184 +PH_SC1_PA3_EVENT_WE = 185 +PH_SC1_PA3_FPOV_WE = 186 +PH_SC1_PA3_LPOV_WE = 187 +PH_SC1_PA3_EOP_WE = 188 +PH_SC1_PA3_DATA_FIFO_EOP_RD = 189 +PH_SC1_PA3_EOPG_WE = 190 +PH_SC1_PA3_DEALLOC_4_0_RD = 191 +PH_SC1_PA4_DATA_FIFO_RD = 192 +PH_SC1_PA4_DATA_FIFO_WE = 193 +PH_SC1_PA4_FIFO_EMPTY = 194 +PH_SC1_PA4_FIFO_FULL = 195 +PH_SC1_PA4_NULL_WE = 196 +PH_SC1_PA4_EVENT_WE = 197 +PH_SC1_PA4_FPOV_WE = 198 +PH_SC1_PA4_LPOV_WE = 199 +PH_SC1_PA4_EOP_WE = 200 +PH_SC1_PA4_DATA_FIFO_EOP_RD = 201 +PH_SC1_PA4_EOPG_WE = 202 +PH_SC1_PA4_DEALLOC_4_0_RD = 203 +PH_SC1_PA5_DATA_FIFO_RD = 204 +PH_SC1_PA5_DATA_FIFO_WE = 205 +PH_SC1_PA5_FIFO_EMPTY = 206 +PH_SC1_PA5_FIFO_FULL = 207 +PH_SC1_PA5_NULL_WE = 208 +PH_SC1_PA5_EVENT_WE = 209 +PH_SC1_PA5_FPOV_WE = 210 +PH_SC1_PA5_LPOV_WE = 211 +PH_SC1_PA5_EOP_WE = 212 +PH_SC1_PA5_DATA_FIFO_EOP_RD = 213 +PH_SC1_PA5_EOPG_WE = 214 +PH_SC1_PA5_DEALLOC_4_0_RD = 215 +PH_SC1_PA6_DATA_FIFO_RD = 216 +PH_SC1_PA6_DATA_FIFO_WE = 217 +PH_SC1_PA6_FIFO_EMPTY = 218 +PH_SC1_PA6_FIFO_FULL = 219 +PH_SC1_PA6_NULL_WE = 220 +PH_SC1_PA6_EVENT_WE = 221 +PH_SC1_PA6_FPOV_WE = 222 +PH_SC1_PA6_LPOV_WE = 223 +PH_SC1_PA6_EOP_WE = 224 +PH_SC1_PA6_DATA_FIFO_EOP_RD = 225 +PH_SC1_PA6_EOPG_WE = 226 +PH_SC1_PA6_DEALLOC_4_0_RD = 227 +PH_SC1_PA7_DATA_FIFO_RD = 228 +PH_SC1_PA7_DATA_FIFO_WE = 229 +PH_SC1_PA7_FIFO_EMPTY = 230 +PH_SC1_PA7_FIFO_FULL = 231 +PH_SC1_PA7_NULL_WE = 232 +PH_SC1_PA7_EVENT_WE = 233 +PH_SC1_PA7_FPOV_WE = 234 +PH_SC1_PA7_LPOV_WE = 235 +PH_SC1_PA7_EOP_WE = 236 +PH_SC1_PA7_DATA_FIFO_EOP_RD = 237 +PH_SC1_PA7_EOPG_WE = 238 +PH_SC1_PA7_DEALLOC_4_0_RD = 239 +PH_SC2_SRPS_WINDOW_VALID = 240 +PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 241 +PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 242 +PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 243 +PH_SC2_ARB_STALLED_FROM_BELOW = 244 +PH_SC2_ARB_STARVED_FROM_ABOVE = 245 +PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 246 +PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 247 +PH_SC2_ARB_BUSY = 248 +PH_SC2_ARB_PA_BUSY_SOP = 249 +PH_SC2_ARB_EOP_POP_SYNC_POP = 250 +PH_SC2_ARB_EVENT_SYNC_POP = 251 +PH_SC2_PS_ENG_MULTICYCLE_BUBBLE = 252 +PH_SC2_EOP_SYNC_WINDOW = 253 +PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 254 +PH_SC2_BUSY_CNT_NOT_ZERO = 255 +PH_SC2_SEND = 256 +PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 257 +PH_SC2_CREDIT_AT_MAX = 258 +PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 259 +PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 260 +PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 261 +PH_SC2_GFX_PIPE0_TO_1_TRANSITION = 262 +PH_SC2_GFX_PIPE1_TO_0_TRANSITION = 263 +PH_SC2_PA0_DATA_FIFO_RD = 264 +PH_SC2_PA0_DATA_FIFO_WE = 265 +PH_SC2_PA0_FIFO_EMPTY = 266 +PH_SC2_PA0_FIFO_FULL = 267 +PH_SC2_PA0_NULL_WE = 268 +PH_SC2_PA0_EVENT_WE = 269 +PH_SC2_PA0_FPOV_WE = 270 +PH_SC2_PA0_LPOV_WE = 271 +PH_SC2_PA0_EOP_WE = 272 +PH_SC2_PA0_DATA_FIFO_EOP_RD = 273 +PH_SC2_PA0_EOPG_WE = 274 +PH_SC2_PA0_DEALLOC_4_0_RD = 275 +PH_SC2_PA1_DATA_FIFO_RD = 276 +PH_SC2_PA1_DATA_FIFO_WE = 277 +PH_SC2_PA1_FIFO_EMPTY = 278 +PH_SC2_PA1_FIFO_FULL = 279 +PH_SC2_PA1_NULL_WE = 280 +PH_SC2_PA1_EVENT_WE = 281 +PH_SC2_PA1_FPOV_WE = 282 +PH_SC2_PA1_LPOV_WE = 283 +PH_SC2_PA1_EOP_WE = 284 +PH_SC2_PA1_DATA_FIFO_EOP_RD = 285 +PH_SC2_PA1_EOPG_WE = 286 +PH_SC2_PA1_DEALLOC_4_0_RD = 287 +PH_SC2_PA2_DATA_FIFO_RD = 288 +PH_SC2_PA2_DATA_FIFO_WE = 289 +PH_SC2_PA2_FIFO_EMPTY = 290 +PH_SC2_PA2_FIFO_FULL = 291 +PH_SC2_PA2_NULL_WE = 292 +PH_SC2_PA2_EVENT_WE = 293 +PH_SC2_PA2_FPOV_WE = 294 +PH_SC2_PA2_LPOV_WE = 295 +PH_SC2_PA2_EOP_WE = 296 +PH_SC2_PA2_DATA_FIFO_EOP_RD = 297 +PH_SC2_PA2_EOPG_WE = 298 +PH_SC2_PA2_DEALLOC_4_0_RD = 299 +PH_SC2_PA3_DATA_FIFO_RD = 300 +PH_SC2_PA3_DATA_FIFO_WE = 301 +PH_SC2_PA3_FIFO_EMPTY = 302 +PH_SC2_PA3_FIFO_FULL = 303 +PH_SC2_PA3_NULL_WE = 304 +PH_SC2_PA3_EVENT_WE = 305 +PH_SC2_PA3_FPOV_WE = 306 +PH_SC2_PA3_LPOV_WE = 307 +PH_SC2_PA3_EOP_WE = 308 +PH_SC2_PA3_DATA_FIFO_EOP_RD = 309 +PH_SC2_PA3_EOPG_WE = 310 +PH_SC2_PA3_DEALLOC_4_0_RD = 311 +PH_SC2_PA4_DATA_FIFO_RD = 312 +PH_SC2_PA4_DATA_FIFO_WE = 313 +PH_SC2_PA4_FIFO_EMPTY = 314 +PH_SC2_PA4_FIFO_FULL = 315 +PH_SC2_PA4_NULL_WE = 316 +PH_SC2_PA4_EVENT_WE = 317 +PH_SC2_PA4_FPOV_WE = 318 +PH_SC2_PA4_LPOV_WE = 319 +PH_SC2_PA4_EOP_WE = 320 +PH_SC2_PA4_DATA_FIFO_EOP_RD = 321 +PH_SC2_PA4_EOPG_WE = 322 +PH_SC2_PA4_DEALLOC_4_0_RD = 323 +PH_SC2_PA5_DATA_FIFO_RD = 324 +PH_SC2_PA5_DATA_FIFO_WE = 325 +PH_SC2_PA5_FIFO_EMPTY = 326 +PH_SC2_PA5_FIFO_FULL = 327 +PH_SC2_PA5_NULL_WE = 328 +PH_SC2_PA5_EVENT_WE = 329 +PH_SC2_PA5_FPOV_WE = 330 +PH_SC2_PA5_LPOV_WE = 331 +PH_SC2_PA5_EOP_WE = 332 +PH_SC2_PA5_DATA_FIFO_EOP_RD = 333 +PH_SC2_PA5_EOPG_WE = 334 +PH_SC2_PA5_DEALLOC_4_0_RD = 335 +PH_SC2_PA6_DATA_FIFO_RD = 336 +PH_SC2_PA6_DATA_FIFO_WE = 337 +PH_SC2_PA6_FIFO_EMPTY = 338 +PH_SC2_PA6_FIFO_FULL = 339 +PH_SC2_PA6_NULL_WE = 340 +PH_SC2_PA6_EVENT_WE = 341 +PH_SC2_PA6_FPOV_WE = 342 +PH_SC2_PA6_LPOV_WE = 343 +PH_SC2_PA6_EOP_WE = 344 +PH_SC2_PA6_DATA_FIFO_EOP_RD = 345 +PH_SC2_PA6_EOPG_WE = 346 +PH_SC2_PA6_DEALLOC_4_0_RD = 347 +PH_SC2_PA7_DATA_FIFO_RD = 348 +PH_SC2_PA7_DATA_FIFO_WE = 349 +PH_SC2_PA7_FIFO_EMPTY = 350 +PH_SC2_PA7_FIFO_FULL = 351 +PH_SC2_PA7_NULL_WE = 352 +PH_SC2_PA7_EVENT_WE = 353 +PH_SC2_PA7_FPOV_WE = 354 +PH_SC2_PA7_LPOV_WE = 355 +PH_SC2_PA7_EOP_WE = 356 +PH_SC2_PA7_DATA_FIFO_EOP_RD = 357 +PH_SC2_PA7_EOPG_WE = 358 +PH_SC2_PA7_DEALLOC_4_0_RD = 359 +PH_SC3_SRPS_WINDOW_VALID = 360 +PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 361 +PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 362 +PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 363 +PH_SC3_ARB_STALLED_FROM_BELOW = 364 +PH_SC3_ARB_STARVED_FROM_ABOVE = 365 +PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 366 +PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 367 +PH_SC3_ARB_BUSY = 368 +PH_SC3_ARB_PA_BUSY_SOP = 369 +PH_SC3_ARB_EOP_POP_SYNC_POP = 370 +PH_SC3_ARB_EVENT_SYNC_POP = 371 +PH_SC3_PS_ENG_MULTICYCLE_BUBBLE = 372 +PH_SC3_EOP_SYNC_WINDOW = 373 +PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 374 +PH_SC3_BUSY_CNT_NOT_ZERO = 375 +PH_SC3_SEND = 376 +PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 377 +PH_SC3_CREDIT_AT_MAX = 378 +PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 379 +PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 380 +PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 381 +PH_SC3_GFX_PIPE0_TO_1_TRANSITION = 382 +PH_SC3_GFX_PIPE1_TO_0_TRANSITION = 383 +PH_SC3_PA0_DATA_FIFO_RD = 384 +PH_SC3_PA0_DATA_FIFO_WE = 385 +PH_SC3_PA0_FIFO_EMPTY = 386 +PH_SC3_PA0_FIFO_FULL = 387 +PH_SC3_PA0_NULL_WE = 388 +PH_SC3_PA0_EVENT_WE = 389 +PH_SC3_PA0_FPOV_WE = 390 +PH_SC3_PA0_LPOV_WE = 391 +PH_SC3_PA0_EOP_WE = 392 +PH_SC3_PA0_DATA_FIFO_EOP_RD = 393 +PH_SC3_PA0_EOPG_WE = 394 +PH_SC3_PA0_DEALLOC_4_0_RD = 395 +PH_SC3_PA1_DATA_FIFO_RD = 396 +PH_SC3_PA1_DATA_FIFO_WE = 397 +PH_SC3_PA1_FIFO_EMPTY = 398 +PH_SC3_PA1_FIFO_FULL = 399 +PH_SC3_PA1_NULL_WE = 400 +PH_SC3_PA1_EVENT_WE = 401 +PH_SC3_PA1_FPOV_WE = 402 +PH_SC3_PA1_LPOV_WE = 403 +PH_SC3_PA1_EOP_WE = 404 +PH_SC3_PA1_DATA_FIFO_EOP_RD = 405 +PH_SC3_PA1_EOPG_WE = 406 +PH_SC3_PA1_DEALLOC_4_0_RD = 407 +PH_SC3_PA2_DATA_FIFO_RD = 408 +PH_SC3_PA2_DATA_FIFO_WE = 409 +PH_SC3_PA2_FIFO_EMPTY = 410 +PH_SC3_PA2_FIFO_FULL = 411 +PH_SC3_PA2_NULL_WE = 412 +PH_SC3_PA2_EVENT_WE = 413 +PH_SC3_PA2_FPOV_WE = 414 +PH_SC3_PA2_LPOV_WE = 415 +PH_SC3_PA2_EOP_WE = 416 +PH_SC3_PA2_DATA_FIFO_EOP_RD = 417 +PH_SC3_PA2_EOPG_WE = 418 +PH_SC3_PA2_DEALLOC_4_0_RD = 419 +PH_SC3_PA3_DATA_FIFO_RD = 420 +PH_SC3_PA3_DATA_FIFO_WE = 421 +PH_SC3_PA3_FIFO_EMPTY = 422 +PH_SC3_PA3_FIFO_FULL = 423 +PH_SC3_PA3_NULL_WE = 424 +PH_SC3_PA3_EVENT_WE = 425 +PH_SC3_PA3_FPOV_WE = 426 +PH_SC3_PA3_LPOV_WE = 427 +PH_SC3_PA3_EOP_WE = 428 +PH_SC3_PA3_DATA_FIFO_EOP_RD = 429 +PH_SC3_PA3_EOPG_WE = 430 +PH_SC3_PA3_DEALLOC_4_0_RD = 431 +PH_SC3_PA4_DATA_FIFO_RD = 432 +PH_SC3_PA4_DATA_FIFO_WE = 433 +PH_SC3_PA4_FIFO_EMPTY = 434 +PH_SC3_PA4_FIFO_FULL = 435 +PH_SC3_PA4_NULL_WE = 436 +PH_SC3_PA4_EVENT_WE = 437 +PH_SC3_PA4_FPOV_WE = 438 +PH_SC3_PA4_LPOV_WE = 439 +PH_SC3_PA4_EOP_WE = 440 +PH_SC3_PA4_DATA_FIFO_EOP_RD = 441 +PH_SC3_PA4_EOPG_WE = 442 +PH_SC3_PA4_DEALLOC_4_0_RD = 443 +PH_SC3_PA5_DATA_FIFO_RD = 444 +PH_SC3_PA5_DATA_FIFO_WE = 445 +PH_SC3_PA5_FIFO_EMPTY = 446 +PH_SC3_PA5_FIFO_FULL = 447 +PH_SC3_PA5_NULL_WE = 448 +PH_SC3_PA5_EVENT_WE = 449 +PH_SC3_PA5_FPOV_WE = 450 +PH_SC3_PA5_LPOV_WE = 451 +PH_SC3_PA5_EOP_WE = 452 +PH_SC3_PA5_DATA_FIFO_EOP_RD = 453 +PH_SC3_PA5_EOPG_WE = 454 +PH_SC3_PA5_DEALLOC_4_0_RD = 455 +PH_SC3_PA6_DATA_FIFO_RD = 456 +PH_SC3_PA6_DATA_FIFO_WE = 457 +PH_SC3_PA6_FIFO_EMPTY = 458 +PH_SC3_PA6_FIFO_FULL = 459 +PH_SC3_PA6_NULL_WE = 460 +PH_SC3_PA6_EVENT_WE = 461 +PH_SC3_PA6_FPOV_WE = 462 +PH_SC3_PA6_LPOV_WE = 463 +PH_SC3_PA6_EOP_WE = 464 +PH_SC3_PA6_DATA_FIFO_EOP_RD = 465 +PH_SC3_PA6_EOPG_WE = 466 +PH_SC3_PA6_DEALLOC_4_0_RD = 467 +PH_SC3_PA7_DATA_FIFO_RD = 468 +PH_SC3_PA7_DATA_FIFO_WE = 469 +PH_SC3_PA7_FIFO_EMPTY = 470 +PH_SC3_PA7_FIFO_FULL = 471 +PH_SC3_PA7_NULL_WE = 472 +PH_SC3_PA7_EVENT_WE = 473 +PH_SC3_PA7_FPOV_WE = 474 +PH_SC3_PA7_LPOV_WE = 475 +PH_SC3_PA7_EOP_WE = 476 +PH_SC3_PA7_DATA_FIFO_EOP_RD = 477 +PH_SC3_PA7_EOPG_WE = 478 +PH_SC3_PA7_DEALLOC_4_0_RD = 479 +PH_SC4_SRPS_WINDOW_VALID = 480 +PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 481 +PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 482 +PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 483 +PH_SC4_ARB_STALLED_FROM_BELOW = 484 +PH_SC4_ARB_STARVED_FROM_ABOVE = 485 +PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 486 +PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 487 +PH_SC4_ARB_BUSY = 488 +PH_SC4_ARB_PA_BUSY_SOP = 489 +PH_SC4_ARB_EOP_POP_SYNC_POP = 490 +PH_SC4_ARB_EVENT_SYNC_POP = 491 +PH_SC4_PS_ENG_MULTICYCLE_BUBBLE = 492 +PH_SC4_EOP_SYNC_WINDOW = 493 +PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 494 +PH_SC4_BUSY_CNT_NOT_ZERO = 495 +PH_SC4_SEND = 496 +PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 497 +PH_SC4_CREDIT_AT_MAX = 498 +PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 499 +PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 500 +PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 501 +PH_SC4_GFX_PIPE0_TO_1_TRANSITION = 502 +PH_SC4_GFX_PIPE1_TO_0_TRANSITION = 503 +PH_SC4_PA0_DATA_FIFO_RD = 504 +PH_SC4_PA0_DATA_FIFO_WE = 505 +PH_SC4_PA0_FIFO_EMPTY = 506 +PH_SC4_PA0_FIFO_FULL = 507 +PH_SC4_PA0_NULL_WE = 508 +PH_SC4_PA0_EVENT_WE = 509 +PH_SC4_PA0_FPOV_WE = 510 +PH_SC4_PA0_LPOV_WE = 511 +PH_SC4_PA0_EOP_WE = 512 +PH_SC4_PA0_DATA_FIFO_EOP_RD = 513 +PH_SC4_PA0_EOPG_WE = 514 +PH_SC4_PA0_DEALLOC_4_0_RD = 515 +PH_SC4_PA1_DATA_FIFO_RD = 516 +PH_SC4_PA1_DATA_FIFO_WE = 517 +PH_SC4_PA1_FIFO_EMPTY = 518 +PH_SC4_PA1_FIFO_FULL = 519 +PH_SC4_PA1_NULL_WE = 520 +PH_SC4_PA1_EVENT_WE = 521 +PH_SC4_PA1_FPOV_WE = 522 +PH_SC4_PA1_LPOV_WE = 523 +PH_SC4_PA1_EOP_WE = 524 +PH_SC4_PA1_DATA_FIFO_EOP_RD = 525 +PH_SC4_PA1_EOPG_WE = 526 +PH_SC4_PA1_DEALLOC_4_0_RD = 527 +PH_SC4_PA2_DATA_FIFO_RD = 528 +PH_SC4_PA2_DATA_FIFO_WE = 529 +PH_SC4_PA2_FIFO_EMPTY = 530 +PH_SC4_PA2_FIFO_FULL = 531 +PH_SC4_PA2_NULL_WE = 532 +PH_SC4_PA2_EVENT_WE = 533 +PH_SC4_PA2_FPOV_WE = 534 +PH_SC4_PA2_LPOV_WE = 535 +PH_SC4_PA2_EOP_WE = 536 +PH_SC4_PA2_DATA_FIFO_EOP_RD = 537 +PH_SC4_PA2_EOPG_WE = 538 +PH_SC4_PA2_DEALLOC_4_0_RD = 539 +PH_SC4_PA3_DATA_FIFO_RD = 540 +PH_SC4_PA3_DATA_FIFO_WE = 541 +PH_SC4_PA3_FIFO_EMPTY = 542 +PH_SC4_PA3_FIFO_FULL = 543 +PH_SC4_PA3_NULL_WE = 544 +PH_SC4_PA3_EVENT_WE = 545 +PH_SC4_PA3_FPOV_WE = 546 +PH_SC4_PA3_LPOV_WE = 547 +PH_SC4_PA3_EOP_WE = 548 +PH_SC4_PA3_DATA_FIFO_EOP_RD = 549 +PH_SC4_PA3_EOPG_WE = 550 +PH_SC4_PA3_DEALLOC_4_0_RD = 551 +PH_SC4_PA4_DATA_FIFO_RD = 552 +PH_SC4_PA4_DATA_FIFO_WE = 553 +PH_SC4_PA4_FIFO_EMPTY = 554 +PH_SC4_PA4_FIFO_FULL = 555 +PH_SC4_PA4_NULL_WE = 556 +PH_SC4_PA4_EVENT_WE = 557 +PH_SC4_PA4_FPOV_WE = 558 +PH_SC4_PA4_LPOV_WE = 559 +PH_SC4_PA4_EOP_WE = 560 +PH_SC4_PA4_DATA_FIFO_EOP_RD = 561 +PH_SC4_PA4_EOPG_WE = 562 +PH_SC4_PA4_DEALLOC_4_0_RD = 563 +PH_SC4_PA5_DATA_FIFO_RD = 564 +PH_SC4_PA5_DATA_FIFO_WE = 565 +PH_SC4_PA5_FIFO_EMPTY = 566 +PH_SC4_PA5_FIFO_FULL = 567 +PH_SC4_PA5_NULL_WE = 568 +PH_SC4_PA5_EVENT_WE = 569 +PH_SC4_PA5_FPOV_WE = 570 +PH_SC4_PA5_LPOV_WE = 571 +PH_SC4_PA5_EOP_WE = 572 +PH_SC4_PA5_DATA_FIFO_EOP_RD = 573 +PH_SC4_PA5_EOPG_WE = 574 +PH_SC4_PA5_DEALLOC_4_0_RD = 575 +PH_SC4_PA6_DATA_FIFO_RD = 576 +PH_SC4_PA6_DATA_FIFO_WE = 577 +PH_SC4_PA6_FIFO_EMPTY = 578 +PH_SC4_PA6_FIFO_FULL = 579 +PH_SC4_PA6_NULL_WE = 580 +PH_SC4_PA6_EVENT_WE = 581 +PH_SC4_PA6_FPOV_WE = 582 +PH_SC4_PA6_LPOV_WE = 583 +PH_SC4_PA6_EOP_WE = 584 +PH_SC4_PA6_DATA_FIFO_EOP_RD = 585 +PH_SC4_PA6_EOPG_WE = 586 +PH_SC4_PA6_DEALLOC_4_0_RD = 587 +PH_SC4_PA7_DATA_FIFO_RD = 588 +PH_SC4_PA7_DATA_FIFO_WE = 589 +PH_SC4_PA7_FIFO_EMPTY = 590 +PH_SC4_PA7_FIFO_FULL = 591 +PH_SC4_PA7_NULL_WE = 592 +PH_SC4_PA7_EVENT_WE = 593 +PH_SC4_PA7_FPOV_WE = 594 +PH_SC4_PA7_LPOV_WE = 595 +PH_SC4_PA7_EOP_WE = 596 +PH_SC4_PA7_DATA_FIFO_EOP_RD = 597 +PH_SC4_PA7_EOPG_WE = 598 +PH_SC4_PA7_DEALLOC_4_0_RD = 599 +PH_SC5_SRPS_WINDOW_VALID = 600 +PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 601 +PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 602 +PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 603 +PH_SC5_ARB_STALLED_FROM_BELOW = 604 +PH_SC5_ARB_STARVED_FROM_ABOVE = 605 +PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 606 +PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 607 +PH_SC5_ARB_BUSY = 608 +PH_SC5_ARB_PA_BUSY_SOP = 609 +PH_SC5_ARB_EOP_POP_SYNC_POP = 610 +PH_SC5_ARB_EVENT_SYNC_POP = 611 +PH_SC5_PS_ENG_MULTICYCLE_BUBBLE = 612 +PH_SC5_EOP_SYNC_WINDOW = 613 +PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 614 +PH_SC5_BUSY_CNT_NOT_ZERO = 615 +PH_SC5_SEND = 616 +PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 617 +PH_SC5_CREDIT_AT_MAX = 618 +PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 619 +PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 620 +PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 621 +PH_SC5_GFX_PIPE0_TO_1_TRANSITION = 622 +PH_SC5_GFX_PIPE1_TO_0_TRANSITION = 623 +PH_SC5_PA0_DATA_FIFO_RD = 624 +PH_SC5_PA0_DATA_FIFO_WE = 625 +PH_SC5_PA0_FIFO_EMPTY = 626 +PH_SC5_PA0_FIFO_FULL = 627 +PH_SC5_PA0_NULL_WE = 628 +PH_SC5_PA0_EVENT_WE = 629 +PH_SC5_PA0_FPOV_WE = 630 +PH_SC5_PA0_LPOV_WE = 631 +PH_SC5_PA0_EOP_WE = 632 +PH_SC5_PA0_DATA_FIFO_EOP_RD = 633 +PH_SC5_PA0_EOPG_WE = 634 +PH_SC5_PA0_DEALLOC_4_0_RD = 635 +PH_SC5_PA1_DATA_FIFO_RD = 636 +PH_SC5_PA1_DATA_FIFO_WE = 637 +PH_SC5_PA1_FIFO_EMPTY = 638 +PH_SC5_PA1_FIFO_FULL = 639 +PH_SC5_PA1_NULL_WE = 640 +PH_SC5_PA1_EVENT_WE = 641 +PH_SC5_PA1_FPOV_WE = 642 +PH_SC5_PA1_LPOV_WE = 643 +PH_SC5_PA1_EOP_WE = 644 +PH_SC5_PA1_DATA_FIFO_EOP_RD = 645 +PH_SC5_PA1_EOPG_WE = 646 +PH_SC5_PA1_DEALLOC_4_0_RD = 647 +PH_SC5_PA2_DATA_FIFO_RD = 648 +PH_SC5_PA2_DATA_FIFO_WE = 649 +PH_SC5_PA2_FIFO_EMPTY = 650 +PH_SC5_PA2_FIFO_FULL = 651 +PH_SC5_PA2_NULL_WE = 652 +PH_SC5_PA2_EVENT_WE = 653 +PH_SC5_PA2_FPOV_WE = 654 +PH_SC5_PA2_LPOV_WE = 655 +PH_SC5_PA2_EOP_WE = 656 +PH_SC5_PA2_DATA_FIFO_EOP_RD = 657 +PH_SC5_PA2_EOPG_WE = 658 +PH_SC5_PA2_DEALLOC_4_0_RD = 659 +PH_SC5_PA3_DATA_FIFO_RD = 660 +PH_SC5_PA3_DATA_FIFO_WE = 661 +PH_SC5_PA3_FIFO_EMPTY = 662 +PH_SC5_PA3_FIFO_FULL = 663 +PH_SC5_PA3_NULL_WE = 664 +PH_SC5_PA3_EVENT_WE = 665 +PH_SC5_PA3_FPOV_WE = 666 +PH_SC5_PA3_LPOV_WE = 667 +PH_SC5_PA3_EOP_WE = 668 +PH_SC5_PA3_DATA_FIFO_EOP_RD = 669 +PH_SC5_PA3_EOPG_WE = 670 +PH_SC5_PA3_DEALLOC_4_0_RD = 671 +PH_SC5_PA4_DATA_FIFO_RD = 672 +PH_SC5_PA4_DATA_FIFO_WE = 673 +PH_SC5_PA4_FIFO_EMPTY = 674 +PH_SC5_PA4_FIFO_FULL = 675 +PH_SC5_PA4_NULL_WE = 676 +PH_SC5_PA4_EVENT_WE = 677 +PH_SC5_PA4_FPOV_WE = 678 +PH_SC5_PA4_LPOV_WE = 679 +PH_SC5_PA4_EOP_WE = 680 +PH_SC5_PA4_DATA_FIFO_EOP_RD = 681 +PH_SC5_PA4_EOPG_WE = 682 +PH_SC5_PA4_DEALLOC_4_0_RD = 683 +PH_SC5_PA5_DATA_FIFO_RD = 684 +PH_SC5_PA5_DATA_FIFO_WE = 685 +PH_SC5_PA5_FIFO_EMPTY = 686 +PH_SC5_PA5_FIFO_FULL = 687 +PH_SC5_PA5_NULL_WE = 688 +PH_SC5_PA5_EVENT_WE = 689 +PH_SC5_PA5_FPOV_WE = 690 +PH_SC5_PA5_LPOV_WE = 691 +PH_SC5_PA5_EOP_WE = 692 +PH_SC5_PA5_DATA_FIFO_EOP_RD = 693 +PH_SC5_PA5_EOPG_WE = 694 +PH_SC5_PA5_DEALLOC_4_0_RD = 695 +PH_SC5_PA6_DATA_FIFO_RD = 696 +PH_SC5_PA6_DATA_FIFO_WE = 697 +PH_SC5_PA6_FIFO_EMPTY = 698 +PH_SC5_PA6_FIFO_FULL = 699 +PH_SC5_PA6_NULL_WE = 700 +PH_SC5_PA6_EVENT_WE = 701 +PH_SC5_PA6_FPOV_WE = 702 +PH_SC5_PA6_LPOV_WE = 703 +PH_SC5_PA6_EOP_WE = 704 +PH_SC5_PA6_DATA_FIFO_EOP_RD = 705 +PH_SC5_PA6_EOPG_WE = 706 +PH_SC5_PA6_DEALLOC_4_0_RD = 707 +PH_SC5_PA7_DATA_FIFO_RD = 708 +PH_SC5_PA7_DATA_FIFO_WE = 709 +PH_SC5_PA7_FIFO_EMPTY = 710 +PH_SC5_PA7_FIFO_FULL = 711 +PH_SC5_PA7_NULL_WE = 712 +PH_SC5_PA7_EVENT_WE = 713 +PH_SC5_PA7_FPOV_WE = 714 +PH_SC5_PA7_LPOV_WE = 715 +PH_SC5_PA7_EOP_WE = 716 +PH_SC5_PA7_DATA_FIFO_EOP_RD = 717 +PH_SC5_PA7_EOPG_WE = 718 +PH_SC5_PA7_DEALLOC_4_0_RD = 719 +PH_SC6_SRPS_WINDOW_VALID = 720 +PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 721 +PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 722 +PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 723 +PH_SC6_ARB_STALLED_FROM_BELOW = 724 +PH_SC6_ARB_STARVED_FROM_ABOVE = 725 +PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 726 +PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 727 +PH_SC6_ARB_BUSY = 728 +PH_SC6_ARB_PA_BUSY_SOP = 729 +PH_SC6_ARB_EOP_POP_SYNC_POP = 730 +PH_SC6_ARB_EVENT_SYNC_POP = 731 +PH_SC6_PS_ENG_MULTICYCLE_BUBBLE = 732 +PH_SC6_EOP_SYNC_WINDOW = 733 +PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 734 +PH_SC6_BUSY_CNT_NOT_ZERO = 735 +PH_SC6_SEND = 736 +PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 737 +PH_SC6_CREDIT_AT_MAX = 738 +PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 739 +PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 740 +PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 741 +PH_SC6_GFX_PIPE0_TO_1_TRANSITION = 742 +PH_SC6_GFX_PIPE1_TO_0_TRANSITION = 743 +PH_SC6_PA0_DATA_FIFO_RD = 744 +PH_SC6_PA0_DATA_FIFO_WE = 745 +PH_SC6_PA0_FIFO_EMPTY = 746 +PH_SC6_PA0_FIFO_FULL = 747 +PH_SC6_PA0_NULL_WE = 748 +PH_SC6_PA0_EVENT_WE = 749 +PH_SC6_PA0_FPOV_WE = 750 +PH_SC6_PA0_LPOV_WE = 751 +PH_SC6_PA0_EOP_WE = 752 +PH_SC6_PA0_DATA_FIFO_EOP_RD = 753 +PH_SC6_PA0_EOPG_WE = 754 +PH_SC6_PA0_DEALLOC_4_0_RD = 755 +PH_SC6_PA1_DATA_FIFO_RD = 756 +PH_SC6_PA1_DATA_FIFO_WE = 757 +PH_SC6_PA1_FIFO_EMPTY = 758 +PH_SC6_PA1_FIFO_FULL = 759 +PH_SC6_PA1_NULL_WE = 760 +PH_SC6_PA1_EVENT_WE = 761 +PH_SC6_PA1_FPOV_WE = 762 +PH_SC6_PA1_LPOV_WE = 763 +PH_SC6_PA1_EOP_WE = 764 +PH_SC6_PA1_DATA_FIFO_EOP_RD = 765 +PH_SC6_PA1_EOPG_WE = 766 +PH_SC6_PA1_DEALLOC_4_0_RD = 767 +PH_SC6_PA2_DATA_FIFO_RD = 768 +PH_SC6_PA2_DATA_FIFO_WE = 769 +PH_SC6_PA2_FIFO_EMPTY = 770 +PH_SC6_PA2_FIFO_FULL = 771 +PH_SC6_PA2_NULL_WE = 772 +PH_SC6_PA2_EVENT_WE = 773 +PH_SC6_PA2_FPOV_WE = 774 +PH_SC6_PA2_LPOV_WE = 775 +PH_SC6_PA2_EOP_WE = 776 +PH_SC6_PA2_DATA_FIFO_EOP_RD = 777 +PH_SC6_PA2_EOPG_WE = 778 +PH_SC6_PA2_DEALLOC_4_0_RD = 779 +PH_SC6_PA3_DATA_FIFO_RD = 780 +PH_SC6_PA3_DATA_FIFO_WE = 781 +PH_SC6_PA3_FIFO_EMPTY = 782 +PH_SC6_PA3_FIFO_FULL = 783 +PH_SC6_PA3_NULL_WE = 784 +PH_SC6_PA3_EVENT_WE = 785 +PH_SC6_PA3_FPOV_WE = 786 +PH_SC6_PA3_LPOV_WE = 787 +PH_SC6_PA3_EOP_WE = 788 +PH_SC6_PA3_DATA_FIFO_EOP_RD = 789 +PH_SC6_PA3_EOPG_WE = 790 +PH_SC6_PA3_DEALLOC_4_0_RD = 791 +PH_SC6_PA4_DATA_FIFO_RD = 792 +PH_SC6_PA4_DATA_FIFO_WE = 793 +PH_SC6_PA4_FIFO_EMPTY = 794 +PH_SC6_PA4_FIFO_FULL = 795 +PH_SC6_PA4_NULL_WE = 796 +PH_SC6_PA4_EVENT_WE = 797 +PH_SC6_PA4_FPOV_WE = 798 +PH_SC6_PA4_LPOV_WE = 799 +PH_SC6_PA4_EOP_WE = 800 +PH_SC6_PA4_DATA_FIFO_EOP_RD = 801 +PH_SC6_PA4_EOPG_WE = 802 +PH_SC6_PA4_DEALLOC_4_0_RD = 803 +PH_SC6_PA5_DATA_FIFO_RD = 804 +PH_SC6_PA5_DATA_FIFO_WE = 805 +PH_SC6_PA5_FIFO_EMPTY = 806 +PH_SC6_PA5_FIFO_FULL = 807 +PH_SC6_PA5_NULL_WE = 808 +PH_SC6_PA5_EVENT_WE = 809 +PH_SC6_PA5_FPOV_WE = 810 +PH_SC6_PA5_LPOV_WE = 811 +PH_SC6_PA5_EOP_WE = 812 +PH_SC6_PA5_DATA_FIFO_EOP_RD = 813 +PH_SC6_PA5_EOPG_WE = 814 +PH_SC6_PA5_DEALLOC_4_0_RD = 815 +PH_SC6_PA6_DATA_FIFO_RD = 816 +PH_SC6_PA6_DATA_FIFO_WE = 817 +PH_SC6_PA6_FIFO_EMPTY = 818 +PH_SC6_PA6_FIFO_FULL = 819 +PH_SC6_PA6_NULL_WE = 820 +PH_SC6_PA6_EVENT_WE = 821 +PH_SC6_PA6_FPOV_WE = 822 +PH_SC6_PA6_LPOV_WE = 823 +PH_SC6_PA6_EOP_WE = 824 +PH_SC6_PA6_DATA_FIFO_EOP_RD = 825 +PH_SC6_PA6_EOPG_WE = 826 +PH_SC6_PA6_DEALLOC_4_0_RD = 827 +PH_SC6_PA7_DATA_FIFO_RD = 828 +PH_SC6_PA7_DATA_FIFO_WE = 829 +PH_SC6_PA7_FIFO_EMPTY = 830 +PH_SC6_PA7_FIFO_FULL = 831 +PH_SC6_PA7_NULL_WE = 832 +PH_SC6_PA7_EVENT_WE = 833 +PH_SC6_PA7_FPOV_WE = 834 +PH_SC6_PA7_LPOV_WE = 835 +PH_SC6_PA7_EOP_WE = 836 +PH_SC6_PA7_DATA_FIFO_EOP_RD = 837 +PH_SC6_PA7_EOPG_WE = 838 +PH_SC6_PA7_DEALLOC_4_0_RD = 839 +PH_SC7_SRPS_WINDOW_VALID = 840 +PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 841 +PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 842 +PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 843 +PH_SC7_ARB_STALLED_FROM_BELOW = 844 +PH_SC7_ARB_STARVED_FROM_ABOVE = 845 +PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 846 +PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 847 +PH_SC7_ARB_BUSY = 848 +PH_SC7_ARB_PA_BUSY_SOP = 849 +PH_SC7_ARB_EOP_POP_SYNC_POP = 850 +PH_SC7_ARB_EVENT_SYNC_POP = 851 +PH_SC7_PS_ENG_MULTICYCLE_BUBBLE = 852 +PH_SC7_EOP_SYNC_WINDOW = 853 +PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 854 +PH_SC7_BUSY_CNT_NOT_ZERO = 855 +PH_SC7_SEND = 856 +PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 857 +PH_SC7_CREDIT_AT_MAX = 858 +PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 859 +PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 860 +PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 861 +PH_SC7_GFX_PIPE0_TO_1_TRANSITION = 862 +PH_SC7_GFX_PIPE1_TO_0_TRANSITION = 863 +PH_SC7_PA0_DATA_FIFO_RD = 864 +PH_SC7_PA0_DATA_FIFO_WE = 865 +PH_SC7_PA0_FIFO_EMPTY = 866 +PH_SC7_PA0_FIFO_FULL = 867 +PH_SC7_PA0_NULL_WE = 868 +PH_SC7_PA0_EVENT_WE = 869 +PH_SC7_PA0_FPOV_WE = 870 +PH_SC7_PA0_LPOV_WE = 871 +PH_SC7_PA0_EOP_WE = 872 +PH_SC7_PA0_DATA_FIFO_EOP_RD = 873 +PH_SC7_PA0_EOPG_WE = 874 +PH_SC7_PA0_DEALLOC_4_0_RD = 875 +PH_SC7_PA1_DATA_FIFO_RD = 876 +PH_SC7_PA1_DATA_FIFO_WE = 877 +PH_SC7_PA1_FIFO_EMPTY = 878 +PH_SC7_PA1_FIFO_FULL = 879 +PH_SC7_PA1_NULL_WE = 880 +PH_SC7_PA1_EVENT_WE = 881 +PH_SC7_PA1_FPOV_WE = 882 +PH_SC7_PA1_LPOV_WE = 883 +PH_SC7_PA1_EOP_WE = 884 +PH_SC7_PA1_DATA_FIFO_EOP_RD = 885 +PH_SC7_PA1_EOPG_WE = 886 +PH_SC7_PA1_DEALLOC_4_0_RD = 887 +PH_SC7_PA2_DATA_FIFO_RD = 888 +PH_SC7_PA2_DATA_FIFO_WE = 889 +PH_SC7_PA2_FIFO_EMPTY = 890 +PH_SC7_PA2_FIFO_FULL = 891 +PH_SC7_PA2_NULL_WE = 892 +PH_SC7_PA2_EVENT_WE = 893 +PH_SC7_PA2_FPOV_WE = 894 +PH_SC7_PA2_LPOV_WE = 895 +PH_SC7_PA2_EOP_WE = 896 +PH_SC7_PA2_DATA_FIFO_EOP_RD = 897 +PH_SC7_PA2_EOPG_WE = 898 +PH_SC7_PA2_DEALLOC_4_0_RD = 899 +PH_SC7_PA3_DATA_FIFO_RD = 900 +PH_SC7_PA3_DATA_FIFO_WE = 901 +PH_SC7_PA3_FIFO_EMPTY = 902 +PH_SC7_PA3_FIFO_FULL = 903 +PH_SC7_PA3_NULL_WE = 904 +PH_SC7_PA3_EVENT_WE = 905 +PH_SC7_PA3_FPOV_WE = 906 +PH_SC7_PA3_LPOV_WE = 907 +PH_SC7_PA3_EOP_WE = 908 +PH_SC7_PA3_DATA_FIFO_EOP_RD = 909 +PH_SC7_PA3_EOPG_WE = 910 +PH_SC7_PA3_DEALLOC_4_0_RD = 911 +PH_SC7_PA4_DATA_FIFO_RD = 912 +PH_SC7_PA4_DATA_FIFO_WE = 913 +PH_SC7_PA4_FIFO_EMPTY = 914 +PH_SC7_PA4_FIFO_FULL = 915 +PH_SC7_PA4_NULL_WE = 916 +PH_SC7_PA4_EVENT_WE = 917 +PH_SC7_PA4_FPOV_WE = 918 +PH_SC7_PA4_LPOV_WE = 919 +PH_SC7_PA4_EOP_WE = 920 +PH_SC7_PA4_DATA_FIFO_EOP_RD = 921 +PH_SC7_PA4_EOPG_WE = 922 +PH_SC7_PA4_DEALLOC_4_0_RD = 923 +PH_SC7_PA5_DATA_FIFO_RD = 924 +PH_SC7_PA5_DATA_FIFO_WE = 925 +PH_SC7_PA5_FIFO_EMPTY = 926 +PH_SC7_PA5_FIFO_FULL = 927 +PH_SC7_PA5_NULL_WE = 928 +PH_SC7_PA5_EVENT_WE = 929 +PH_SC7_PA5_FPOV_WE = 930 +PH_SC7_PA5_LPOV_WE = 931 +PH_SC7_PA5_EOP_WE = 932 +PH_SC7_PA5_DATA_FIFO_EOP_RD = 933 +PH_SC7_PA5_EOPG_WE = 934 +PH_SC7_PA5_DEALLOC_4_0_RD = 935 +PH_SC7_PA6_DATA_FIFO_RD = 936 +PH_SC7_PA6_DATA_FIFO_WE = 937 +PH_SC7_PA6_FIFO_EMPTY = 938 +PH_SC7_PA6_FIFO_FULL = 939 +PH_SC7_PA6_NULL_WE = 940 +PH_SC7_PA6_EVENT_WE = 941 +PH_SC7_PA6_FPOV_WE = 942 +PH_SC7_PA6_LPOV_WE = 943 +PH_SC7_PA6_EOP_WE = 944 +PH_SC7_PA6_DATA_FIFO_EOP_RD = 945 +PH_SC7_PA6_EOPG_WE = 946 +PH_SC7_PA6_DEALLOC_4_0_RD = 947 +PH_SC7_PA7_DATA_FIFO_RD = 948 +PH_SC7_PA7_DATA_FIFO_WE = 949 +PH_SC7_PA7_FIFO_EMPTY = 950 +PH_SC7_PA7_FIFO_FULL = 951 +PH_SC7_PA7_NULL_WE = 952 +PH_SC7_PA7_EVENT_WE = 953 +PH_SC7_PA7_FPOV_WE = 954 +PH_SC7_PA7_LPOV_WE = 955 +PH_SC7_PA7_EOP_WE = 956 +PH_SC7_PA7_DATA_FIFO_EOP_RD = 957 +PH_SC7_PA7_EOPG_WE = 958 +PH_SC7_PA7_DEALLOC_4_0_RD = 959 +PH_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SU_PERFCNT_SEL' +SU_PERFCNT_SEL__enumvalues = { + 0: 'PERF_PAPC_PASX_REQ', + 1: 'PERF_PAPC_PASX_DISABLE_PIPE', + 2: 'PERF_PAPC_PASX_FIRST_VECTOR', + 3: 'PERF_PAPC_PASX_SECOND_VECTOR', + 4: 'PERF_PAPC_PASX_FIRST_DEAD', + 5: 'PERF_PAPC_PASX_SECOND_DEAD', + 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 8: 'PERF_PAPC_PA_INPUT_PRIM', + 9: 'PERF_PAPC_PA_INPUT_NULL_PRIM', + 10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG', + 11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', + 12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET', + 13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', + 14: 'PERF_PAPC_CLPR_CULL_PRIM', + 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', + 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', + 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', + 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', + 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', + 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', + 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', + 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 39: 'PERF_PAPC_CLSM_NULL_PRIM', + 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', + 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', + 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', + 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', + 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', + 49: 'PERF_PAPC_SU_INPUT_PRIM', + 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', + 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 61: 'PERF_PAPC_SU_OUTPUT_PRIM', + 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', + 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', + 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 77: 'PERF_PAPC_PASX_REQ_IDLE', + 78: 'PERF_PAPC_PASX_REQ_BUSY', + 79: 'PERF_PAPC_PASX_REQ_STALLED', + 80: 'PERF_PAPC_PASX_REC_IDLE', + 81: 'PERF_PAPC_PASX_REC_BUSY', + 82: 'PERF_PAPC_PASX_REC_STARVED_SX', + 83: 'PERF_PAPC_PASX_REC_STALLED', + 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 86: 'PERF_PAPC_CCGSM_IDLE', + 87: 'PERF_PAPC_CCGSM_BUSY', + 88: 'PERF_PAPC_CCGSM_STALLED', + 89: 'PERF_PAPC_CLPRIM_IDLE', + 90: 'PERF_PAPC_CLPRIM_BUSY', + 91: 'PERF_PAPC_CLPRIM_STALLED', + 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 93: 'PERF_PAPC_CLIPSM_IDLE', + 94: 'PERF_PAPC_CLIPSM_BUSY', + 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', + 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 100: 'PERF_PAPC_CLIPGA_IDLE', + 101: 'PERF_PAPC_CLIPGA_BUSY', + 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 103: 'PERF_PAPC_CLIPGA_STALLED', + 104: 'PERF_PAPC_CLIP_IDLE', + 105: 'PERF_PAPC_CLIP_BUSY', + 106: 'PERF_PAPC_SU_IDLE', + 107: 'PERF_PAPC_SU_BUSY', + 108: 'PERF_PAPC_SU_STARVED_CLIP', + 109: 'PERF_PAPC_SU_STALLED_SC', + 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', + 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', + 112: 'PERF_PAPC_PA_REG_SCLK_VLD', + 113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', + 114: 'PERF_PAPC_PASX_SE0_REQ', + 115: 'PERF_PAPC_PASX_SE1_REQ', + 116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', + 117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', + 118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', + 119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', + 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', + 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', + 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', + 129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', + 130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', + 131: 'PERF_PAPC_SU_SE0_STALLED_SC', + 132: 'PERF_PAPC_SU_SE1_STALLED_SC', + 133: 'PERF_PAPC_SU_SE01_STALLED_SC', + 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 135: 'PERF_PAPC_SU_CULLED_PRIM', + 136: 'PERF_PAPC_SU_OUTPUT_EOPG', + 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', + 144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', + 145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', + 146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', + 147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', + 148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', + 149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', + 150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', + 151: 'PERF_PAPC_SU_SE2_STALLED_SC', + 152: 'PERF_PAPC_SU_SE3_STALLED_SC', + 153: 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', + 154: 'PERF_SMALL_PRIM_CULL_PRIM_1X1', + 155: 'PERF_SMALL_PRIM_CULL_PRIM_2X1', + 156: 'PERF_SMALL_PRIM_CULL_PRIM_1X2', + 157: 'PERF_SMALL_PRIM_CULL_PRIM_2X2', + 158: 'PERF_SMALL_PRIM_CULL_PRIM_3X1', + 159: 'PERF_SMALL_PRIM_CULL_PRIM_1X3', + 160: 'PERF_SMALL_PRIM_CULL_PRIM_3X2', + 161: 'PERF_SMALL_PRIM_CULL_PRIM_2X3', + 162: 'PERF_SMALL_PRIM_CULL_PRIM_NX1', + 163: 'PERF_SMALL_PRIM_CULL_PRIM_1XN', + 164: 'PERF_SMALL_PRIM_CULL_PRIM_NX2', + 165: 'PERF_SMALL_PRIM_CULL_PRIM_2XN', + 166: 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', + 167: 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', + 168: 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', + 169: 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', + 170: 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', + 171: 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', + 172: 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', + 173: 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', + 174: 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', + 175: 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', + 176: 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', + 177: 'PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1', + 178: 'PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT', + 179: 'PERF_UTC_SIDEBAND_DRIVER_BUSY', + 180: 'PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1', + 181: 'PERF_UTC_INDEX_DRIVER_STALLING_CLIENT', + 182: 'PERF_UTC_INDEX_DRIVER_BUSY', + 183: 'PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1', + 184: 'PERF_UTC_POSITION_DRIVER_STALLING_CLIENT', + 185: 'PERF_UTC_POSITION_DRIVER_BUSY', + 186: 'PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1', + 187: 'PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER', + 188: 'PERF_UTC_SIDEBAND_RECEIVER_BUSY', + 189: 'PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1', + 190: 'PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER', + 191: 'PERF_UTC_INDEX_RECEIVER_BUSY', + 192: 'PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1', + 193: 'PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER', + 194: 'PERF_UTC_POSITION_RECEIVER_BUSY', + 195: 'PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE', + 196: 'PERF_TCIF_STALLING_CLIENT_NO_CREDITS', + 197: 'PERF_TCIF_BUSY', + 198: 'PERF_TCIF_SIDEBAND_RDREQ', + 199: 'PERF_TCIF_INDEX_RDREQ', + 200: 'PERF_TCIF_POSITION_RDREQ', + 201: 'PERF_SIDEBAND_WAITING_ON_UTCL1', + 202: 'PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY', + 203: 'PERF_WRITING_TO_SIDEBAND_MEMORY', + 204: 'PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD', + 205: 'PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD', + 206: 'PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD', + 207: 'PERF_SIDEBAND_WAITING_ON_RETURNED_DATA', + 208: 'PERF_SIDEBAND_POP_BIT_FIFO_FULL', + 209: 'PERF_SIDEBAND_FIFO_VMID_FIFO_FULL', + 210: 'PERF_SIDEBAND_INVALID_REFETCH', + 211: 'PERF_SIDEBAND_QUALIFIED_BUSY', + 212: 'PERF_SIDEBAND_QUALIFIED_STARVED', + 213: 'PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_', + 214: 'PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_', + 215: 'PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_', + 216: 'PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_', + 217: 'PERF_INDEX_REQUEST_WAITING_ON_TOKENS', + 218: 'PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO', + 219: 'PERF_INDEX_REQUEST_QUALIFIED_BUSY', + 220: 'PERF_INDEX_REQUEST_QUALIFIED_STARVED', + 221: 'PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE', + 222: 'PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO', + 223: 'PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE', + 224: 'PERF_INDEX_RECEIVE_QUALIFIED_BUSY', + 225: 'PERF_INDEX_RECEIVE_QUALIFIED_STARVED', + 226: 'PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE', + 227: 'PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE', + 228: 'PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE', + 229: 'PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE', + 230: 'PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE', + 231: 'PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE', + 232: 'PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE', + 233: 'PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE', + 234: 'PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE', + 235: 'PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE', + 236: 'PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE', + 237: 'PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE', + 238: 'PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE', + 239: 'PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE', + 240: 'PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE', + 241: 'PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE', + 242: 'PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE', + 243: 'PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', + 244: 'PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', + 245: 'PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO', + 246: 'PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO', + 247: 'PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO', + 248: 'PERF_POS_REQ_STALLED_BY_NO_TOKENS', + 249: 'PERF_POS_REQ_STARVED_BY_NO_PRIM', + 250: 'PERF_POS_REQ_STALLED_BY_UTCL1', + 251: 'PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE', + 252: 'PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', + 253: 'PERF_POS_REQ_QUALIFIED_BUSY', + 254: 'PERF_POS_REQ_QUALIFIED_STARVED', + 255: 'PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM', + 256: 'PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM', + 257: 'PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM', + 258: 'PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM', + 259: 'PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO', + 260: 'PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO', + 261: 'PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE', + 262: 'PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE', + 263: 'PERF_POS_RET_QUALIFIED_BUSY', + 264: 'PERF_POS_RET_QUALIFIED_STARVED', + 265: 'PERF_POS_RET_1_CACHELINE_POSITION_USED', + 266: 'PERF_POS_RET_2_CACHELINE_POSITION_USED', + 267: 'PERF_POS_RET_3_CACHELINE_POSITION_USED', + 268: 'PERF_POS_RET_4_CACHELINE_POSITION_USED', + 269: 'PERF_TC_INDEX_LATENCY_BIN0', + 270: 'PERF_TC_INDEX_LATENCY_BIN1', + 271: 'PERF_TC_INDEX_LATENCY_BIN2', + 272: 'PERF_TC_INDEX_LATENCY_BIN3', + 273: 'PERF_TC_INDEX_LATENCY_BIN4', + 274: 'PERF_TC_INDEX_LATENCY_BIN5', + 275: 'PERF_TC_INDEX_LATENCY_BIN6', + 276: 'PERF_TC_INDEX_LATENCY_BIN7', + 277: 'PERF_TC_INDEX_LATENCY_BIN8', + 278: 'PERF_TC_INDEX_LATENCY_BIN9', + 279: 'PERF_TC_INDEX_LATENCY_BIN10', + 280: 'PERF_TC_INDEX_LATENCY_BIN11', + 281: 'PERF_TC_INDEX_LATENCY_BIN12', + 282: 'PERF_TC_INDEX_LATENCY_BIN13', + 283: 'PERF_TC_INDEX_LATENCY_BIN14', + 284: 'PERF_TC_INDEX_LATENCY_BIN15', + 285: 'PERF_TC_POSITION_LATENCY_BIN0', + 286: 'PERF_TC_POSITION_LATENCY_BIN1', + 287: 'PERF_TC_POSITION_LATENCY_BIN2', + 288: 'PERF_TC_POSITION_LATENCY_BIN3', + 289: 'PERF_TC_POSITION_LATENCY_BIN4', + 290: 'PERF_TC_POSITION_LATENCY_BIN5', + 291: 'PERF_TC_POSITION_LATENCY_BIN6', + 292: 'PERF_TC_POSITION_LATENCY_BIN7', + 293: 'PERF_TC_POSITION_LATENCY_BIN8', + 294: 'PERF_TC_POSITION_LATENCY_BIN9', + 295: 'PERF_TC_POSITION_LATENCY_BIN10', + 296: 'PERF_TC_POSITION_LATENCY_BIN11', + 297: 'PERF_TC_POSITION_LATENCY_BIN12', + 298: 'PERF_TC_POSITION_LATENCY_BIN13', + 299: 'PERF_TC_POSITION_LATENCY_BIN14', + 300: 'PERF_TC_POSITION_LATENCY_BIN15', + 301: 'PERF_TC_STREAM0_DATA_AVAILABLE', + 302: 'PERF_TC_STREAM1_DATA_AVAILABLE', + 303: 'PERF_TC_STREAM2_DATA_AVAILABLE', + 304: 'PERF_PAWD_DEALLOC_FIFO_IS_FULL', + 305: 'PERF_PAWD_DEALLOC_WAITING_TO_BE_READ', + 306: 'PERF_SHOOTDOWN_WAIT_ON_UTCL1', + 307: 'PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND', + 308: 'PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX', + 309: 'PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION', + 310: 'PERF_SHOOTDOWN_WAIT_ALL_CLEAN', + 311: 'PERF_SHOOTDOWN_WAIT_DEASSERT', + 312: 'PERF_UTCL1_TRANSLATION_MISS_CLIENT0', + 313: 'PERF_UTCL1_TRANSLATION_MISS_CLIENT1', + 314: 'PERF_UTCL1_TRANSLATION_MISS_CLIENT2', + 315: 'PERF_UTCL1_PERMISSION_MISS_CLIENT0', + 316: 'PERF_UTCL1_PERMISSION_MISS_CLIENT1', + 317: 'PERF_UTCL1_PERMISSION_MISS_CLIENT2', + 318: 'PERF_UTCL1_TRANSLATION_HIT_CLIENT0', + 319: 'PERF_UTCL1_TRANSLATION_HIT_CLIENT1', + 320: 'PERF_UTCL1_TRANSLATION_HIT_CLIENT2', + 321: 'PERF_UTCL1_REQUEST_CLIENT0', + 322: 'PERF_UTCL1_REQUEST_CLIENT1', + 323: 'PERF_UTCL1_REQUEST_CLIENT2', + 324: 'PERF_UTCL1_STALL_MISSFIFO_FULL', + 325: 'PERF_UTCL1_STALL_INFLIGHT_MAX', + 326: 'PERF_UTCL1_STALL_LRU_INFLIGHT', + 327: 'PERF_UTCL1_STALL_MULTI_MISS', + 328: 'PERF_UTCL1_LFIFO_FULL', + 329: 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0', + 330: 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1', + 331: 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2', + 332: 'PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 333: 'PERF_UTCL1_UTCL2_REQ', + 334: 'PERF_UTCL1_UTCL2_RET', + 335: 'PERF_UTCL1_UTCL2_INFLIGHT', + 336: 'PERF_CLIENT_UTCL1_INFLIGHT', + 337: 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', + 338: 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', + 339: 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', + 340: 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', + 341: 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', + 342: 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', + 343: 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', + 344: 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', + 345: 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', + 346: 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', + 347: 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', + 348: 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', + 349: 'PERF_PA_VERTEX_FIFO_FULL', + 350: 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', + 351: 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', + 352: 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', + 355: 'ENGG_CSB_MACHINE_IS_STARVED', + 356: 'ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', + 357: 'ENGG_CSB_MACHINE_STALLED_BY_SPI', + 358: 'ENGG_CSB_GE_INPUT_FIFO_FULL', + 359: 'ENGG_CSB_SPI_INPUT_FIFO_FULL', + 360: 'ENGG_CSB_OBJECTID_INPUT_FIFO_FULL', + 361: 'ENGG_CSB_PRIM_COUNT_EQ0', + 362: 'ENGG_CSB_GE_SENDING_SUBGROUP', + 363: 'ENGG_CSB_DELAY_BIN00', + 364: 'ENGG_CSB_DELAY_BIN01', + 365: 'ENGG_CSB_DELAY_BIN02', + 366: 'ENGG_CSB_DELAY_BIN03', + 367: 'ENGG_CSB_DELAY_BIN04', + 368: 'ENGG_CSB_DELAY_BIN05', + 369: 'ENGG_CSB_DELAY_BIN06', + 370: 'ENGG_CSB_DELAY_BIN07', + 371: 'ENGG_CSB_DELAY_BIN08', + 372: 'ENGG_CSB_DELAY_BIN09', + 373: 'ENGG_CSB_DELAY_BIN10', + 374: 'ENGG_CSB_DELAY_BIN11', + 375: 'ENGG_CSB_DELAY_BIN12', + 376: 'ENGG_CSB_DELAY_BIN13', + 377: 'ENGG_CSB_DELAY_BIN14', + 378: 'ENGG_CSB_DELAY_BIN15', + 379: 'ENGG_CSB_SPI_DELAY_BIN00', + 380: 'ENGG_CSB_SPI_DELAY_BIN01', + 381: 'ENGG_CSB_SPI_DELAY_BIN02', + 382: 'ENGG_CSB_SPI_DELAY_BIN03', + 383: 'ENGG_CSB_SPI_DELAY_BIN04', + 384: 'ENGG_CSB_SPI_DELAY_BIN05', + 385: 'ENGG_CSB_SPI_DELAY_BIN06', + 386: 'ENGG_CSB_SPI_DELAY_BIN07', + 387: 'ENGG_CSB_SPI_DELAY_BIN08', + 388: 'ENGG_CSB_SPI_DELAY_BIN09', + 389: 'ENGG_CSB_SPI_DELAY_BIN10', + 390: 'ENGG_CSB_SPI_DELAY_BIN11', + 391: 'ENGG_CSB_SPI_DELAY_BIN12', + 392: 'ENGG_CSB_SPI_DELAY_BIN13', + 393: 'ENGG_CSB_SPI_DELAY_BIN14', + 394: 'ENGG_CSB_SPI_DELAY_BIN15', + 395: 'ENGG_INDEX_REQ_STARVED', + 396: 'ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 397: 'ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 398: 'ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', + 399: 'ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', + 400: 'ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', + 401: 'ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', + 402: 'ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', + 403: 'ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', + 404: 'ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', + 405: 'ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', + 406: 'ENGG_INDEX_RET_SXRX_READING_EVENT', + 407: 'ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', + 408: 'ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', + 409: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', + 410: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', + 411: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', + 412: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', + 413: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS', + 414: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS', + 415: 'ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS', + 416: 'ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', + 417: 'ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', + 418: 'ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', + 419: 'ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', + 420: 'ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', + 421: 'ENGG_INDEX_PRIM_IF_QUALIFIED_BUSY', + 422: 'ENGG_INDEX_PRIM_IF_QUALIFIED_STARVED', + 423: 'ENGG_INDEX_PRIM_IF_REUSE_0_NEW_VERTS_THIS_PRIM', + 424: 'ENGG_INDEX_PRIM_IF_REUSE_1_NEW_VERTS_THIS_PRIM', + 425: 'ENGG_INDEX_PRIM_IF_REUSE_2_NEW_VERTS_THIS_PRIM', + 426: 'ENGG_INDEX_PRIM_IF_REUSE_3_NEW_VERTS_THIS_PRIM', + 427: 'ENGG_POS_REQ_STARVED', + 428: 'ENGG_POS_REQ_STALLED_BY_FULL_CLIPV_FIFO', +} +PERF_PAPC_PASX_REQ = 0 +PERF_PAPC_PASX_DISABLE_PIPE = 1 +PERF_PAPC_PASX_FIRST_VECTOR = 2 +PERF_PAPC_PASX_SECOND_VECTOR = 3 +PERF_PAPC_PASX_FIRST_DEAD = 4 +PERF_PAPC_PASX_SECOND_DEAD = 5 +PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 +PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 +PERF_PAPC_PA_INPUT_PRIM = 8 +PERF_PAPC_PA_INPUT_NULL_PRIM = 9 +PERF_PAPC_PA_INPUT_EVENT_FLAG = 10 +PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11 +PERF_PAPC_PA_INPUT_END_OF_PACKET = 12 +PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13 +PERF_PAPC_CLPR_CULL_PRIM = 14 +PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 +PERF_PAPC_CLPR_VV_CULL_PRIM = 16 +PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 +PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 +PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 +PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 +PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 +PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 +PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 +PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30 +PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 +PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 +PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 +PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 +PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 +PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 +PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37 +PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 +PERF_PAPC_CLSM_NULL_PRIM = 39 +PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 +PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 +PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 +PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 +PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 +PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 +PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 +PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47 +PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 +PERF_PAPC_SU_INPUT_PRIM = 49 +PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 +PERF_PAPC_SU_INPUT_NULL_PRIM = 51 +PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 +PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 +PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 +PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 +PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 +PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 +PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 +PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 +PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 +PERF_PAPC_SU_OUTPUT_PRIM = 61 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 +PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 +PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 +PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 +PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 +PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 +PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 +PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 +PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 +PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 +PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 +PERF_PAPC_PASX_REQ_IDLE = 77 +PERF_PAPC_PASX_REQ_BUSY = 78 +PERF_PAPC_PASX_REQ_STALLED = 79 +PERF_PAPC_PASX_REC_IDLE = 80 +PERF_PAPC_PASX_REC_BUSY = 81 +PERF_PAPC_PASX_REC_STARVED_SX = 82 +PERF_PAPC_PASX_REC_STALLED = 83 +PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 +PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 +PERF_PAPC_CCGSM_IDLE = 86 +PERF_PAPC_CCGSM_BUSY = 87 +PERF_PAPC_CCGSM_STALLED = 88 +PERF_PAPC_CLPRIM_IDLE = 89 +PERF_PAPC_CLPRIM_BUSY = 90 +PERF_PAPC_CLPRIM_STALLED = 91 +PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 +PERF_PAPC_CLIPSM_IDLE = 93 +PERF_PAPC_CLIPSM_BUSY = 94 +PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 +PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 +PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 +PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 +PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 +PERF_PAPC_CLIPGA_IDLE = 100 +PERF_PAPC_CLIPGA_BUSY = 101 +PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 +PERF_PAPC_CLIPGA_STALLED = 103 +PERF_PAPC_CLIP_IDLE = 104 +PERF_PAPC_CLIP_BUSY = 105 +PERF_PAPC_SU_IDLE = 106 +PERF_PAPC_SU_BUSY = 107 +PERF_PAPC_SU_STARVED_CLIP = 108 +PERF_PAPC_SU_STALLED_SC = 109 +PERF_PAPC_CL_DYN_SCLK_VLD = 110 +PERF_PAPC_SU_DYN_SCLK_VLD = 111 +PERF_PAPC_PA_REG_SCLK_VLD = 112 +PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113 +PERF_PAPC_PASX_SE0_REQ = 114 +PERF_PAPC_PASX_SE1_REQ = 115 +PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116 +PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117 +PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118 +PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119 +PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 +PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 +PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122 +PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 +PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 +PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125 +PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 +PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 +PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128 +PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129 +PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130 +PERF_PAPC_SU_SE0_STALLED_SC = 131 +PERF_PAPC_SU_SE1_STALLED_SC = 132 +PERF_PAPC_SU_SE01_STALLED_SC = 133 +PERF_PAPC_CLSM_CLIPPING_PRIM = 134 +PERF_PAPC_SU_CULLED_PRIM = 135 +PERF_PAPC_SU_OUTPUT_EOPG = 136 +PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 +PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 +PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 +PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 +PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 +PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 +PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143 +PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144 +PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145 +PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146 +PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147 +PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148 +PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149 +PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150 +PERF_PAPC_SU_SE2_STALLED_SC = 151 +PERF_PAPC_SU_SE3_STALLED_SC = 152 +PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 153 +PERF_SMALL_PRIM_CULL_PRIM_1X1 = 154 +PERF_SMALL_PRIM_CULL_PRIM_2X1 = 155 +PERF_SMALL_PRIM_CULL_PRIM_1X2 = 156 +PERF_SMALL_PRIM_CULL_PRIM_2X2 = 157 +PERF_SMALL_PRIM_CULL_PRIM_3X1 = 158 +PERF_SMALL_PRIM_CULL_PRIM_1X3 = 159 +PERF_SMALL_PRIM_CULL_PRIM_3X2 = 160 +PERF_SMALL_PRIM_CULL_PRIM_2X3 = 161 +PERF_SMALL_PRIM_CULL_PRIM_NX1 = 162 +PERF_SMALL_PRIM_CULL_PRIM_1XN = 163 +PERF_SMALL_PRIM_CULL_PRIM_NX2 = 164 +PERF_SMALL_PRIM_CULL_PRIM_2XN = 165 +PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 166 +PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 167 +PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 168 +PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 169 +PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 170 +PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 171 +PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 172 +PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 173 +PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 174 +PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 175 +PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 176 +PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1 = 177 +PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT = 178 +PERF_UTC_SIDEBAND_DRIVER_BUSY = 179 +PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1 = 180 +PERF_UTC_INDEX_DRIVER_STALLING_CLIENT = 181 +PERF_UTC_INDEX_DRIVER_BUSY = 182 +PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1 = 183 +PERF_UTC_POSITION_DRIVER_STALLING_CLIENT = 184 +PERF_UTC_POSITION_DRIVER_BUSY = 185 +PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1 = 186 +PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER = 187 +PERF_UTC_SIDEBAND_RECEIVER_BUSY = 188 +PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1 = 189 +PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER = 190 +PERF_UTC_INDEX_RECEIVER_BUSY = 191 +PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1 = 192 +PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER = 193 +PERF_UTC_POSITION_RECEIVER_BUSY = 194 +PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE = 195 +PERF_TCIF_STALLING_CLIENT_NO_CREDITS = 196 +PERF_TCIF_BUSY = 197 +PERF_TCIF_SIDEBAND_RDREQ = 198 +PERF_TCIF_INDEX_RDREQ = 199 +PERF_TCIF_POSITION_RDREQ = 200 +PERF_SIDEBAND_WAITING_ON_UTCL1 = 201 +PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY = 202 +PERF_WRITING_TO_SIDEBAND_MEMORY = 203 +PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD = 204 +PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD = 205 +PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD = 206 +PERF_SIDEBAND_WAITING_ON_RETURNED_DATA = 207 +PERF_SIDEBAND_POP_BIT_FIFO_FULL = 208 +PERF_SIDEBAND_FIFO_VMID_FIFO_FULL = 209 +PERF_SIDEBAND_INVALID_REFETCH = 210 +PERF_SIDEBAND_QUALIFIED_BUSY = 211 +PERF_SIDEBAND_QUALIFIED_STARVED = 212 +PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_ = 213 +PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_ = 214 +PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_ = 215 +PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_ = 216 +PERF_INDEX_REQUEST_WAITING_ON_TOKENS = 217 +PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO = 218 +PERF_INDEX_REQUEST_QUALIFIED_BUSY = 219 +PERF_INDEX_REQUEST_QUALIFIED_STARVED = 220 +PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE = 221 +PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO = 222 +PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE = 223 +PERF_INDEX_RECEIVE_QUALIFIED_BUSY = 224 +PERF_INDEX_RECEIVE_QUALIFIED_STARVED = 225 +PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE = 226 +PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE = 227 +PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE = 228 +PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE = 229 +PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE = 230 +PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE = 231 +PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE = 232 +PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE = 233 +PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE = 234 +PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE = 235 +PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE = 236 +PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE = 237 +PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE = 238 +PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE = 239 +PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE = 240 +PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE = 241 +PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE = 242 +PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 243 +PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 244 +PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO = 245 +PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO = 246 +PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO = 247 +PERF_POS_REQ_STALLED_BY_NO_TOKENS = 248 +PERF_POS_REQ_STARVED_BY_NO_PRIM = 249 +PERF_POS_REQ_STALLED_BY_UTCL1 = 250 +PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE = 251 +PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 252 +PERF_POS_REQ_QUALIFIED_BUSY = 253 +PERF_POS_REQ_QUALIFIED_STARVED = 254 +PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM = 255 +PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM = 256 +PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM = 257 +PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM = 258 +PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO = 259 +PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO = 260 +PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE = 261 +PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE = 262 +PERF_POS_RET_QUALIFIED_BUSY = 263 +PERF_POS_RET_QUALIFIED_STARVED = 264 +PERF_POS_RET_1_CACHELINE_POSITION_USED = 265 +PERF_POS_RET_2_CACHELINE_POSITION_USED = 266 +PERF_POS_RET_3_CACHELINE_POSITION_USED = 267 +PERF_POS_RET_4_CACHELINE_POSITION_USED = 268 +PERF_TC_INDEX_LATENCY_BIN0 = 269 +PERF_TC_INDEX_LATENCY_BIN1 = 270 +PERF_TC_INDEX_LATENCY_BIN2 = 271 +PERF_TC_INDEX_LATENCY_BIN3 = 272 +PERF_TC_INDEX_LATENCY_BIN4 = 273 +PERF_TC_INDEX_LATENCY_BIN5 = 274 +PERF_TC_INDEX_LATENCY_BIN6 = 275 +PERF_TC_INDEX_LATENCY_BIN7 = 276 +PERF_TC_INDEX_LATENCY_BIN8 = 277 +PERF_TC_INDEX_LATENCY_BIN9 = 278 +PERF_TC_INDEX_LATENCY_BIN10 = 279 +PERF_TC_INDEX_LATENCY_BIN11 = 280 +PERF_TC_INDEX_LATENCY_BIN12 = 281 +PERF_TC_INDEX_LATENCY_BIN13 = 282 +PERF_TC_INDEX_LATENCY_BIN14 = 283 +PERF_TC_INDEX_LATENCY_BIN15 = 284 +PERF_TC_POSITION_LATENCY_BIN0 = 285 +PERF_TC_POSITION_LATENCY_BIN1 = 286 +PERF_TC_POSITION_LATENCY_BIN2 = 287 +PERF_TC_POSITION_LATENCY_BIN3 = 288 +PERF_TC_POSITION_LATENCY_BIN4 = 289 +PERF_TC_POSITION_LATENCY_BIN5 = 290 +PERF_TC_POSITION_LATENCY_BIN6 = 291 +PERF_TC_POSITION_LATENCY_BIN7 = 292 +PERF_TC_POSITION_LATENCY_BIN8 = 293 +PERF_TC_POSITION_LATENCY_BIN9 = 294 +PERF_TC_POSITION_LATENCY_BIN10 = 295 +PERF_TC_POSITION_LATENCY_BIN11 = 296 +PERF_TC_POSITION_LATENCY_BIN12 = 297 +PERF_TC_POSITION_LATENCY_BIN13 = 298 +PERF_TC_POSITION_LATENCY_BIN14 = 299 +PERF_TC_POSITION_LATENCY_BIN15 = 300 +PERF_TC_STREAM0_DATA_AVAILABLE = 301 +PERF_TC_STREAM1_DATA_AVAILABLE = 302 +PERF_TC_STREAM2_DATA_AVAILABLE = 303 +PERF_PAWD_DEALLOC_FIFO_IS_FULL = 304 +PERF_PAWD_DEALLOC_WAITING_TO_BE_READ = 305 +PERF_SHOOTDOWN_WAIT_ON_UTCL1 = 306 +PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND = 307 +PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX = 308 +PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION = 309 +PERF_SHOOTDOWN_WAIT_ALL_CLEAN = 310 +PERF_SHOOTDOWN_WAIT_DEASSERT = 311 +PERF_UTCL1_TRANSLATION_MISS_CLIENT0 = 312 +PERF_UTCL1_TRANSLATION_MISS_CLIENT1 = 313 +PERF_UTCL1_TRANSLATION_MISS_CLIENT2 = 314 +PERF_UTCL1_PERMISSION_MISS_CLIENT0 = 315 +PERF_UTCL1_PERMISSION_MISS_CLIENT1 = 316 +PERF_UTCL1_PERMISSION_MISS_CLIENT2 = 317 +PERF_UTCL1_TRANSLATION_HIT_CLIENT0 = 318 +PERF_UTCL1_TRANSLATION_HIT_CLIENT1 = 319 +PERF_UTCL1_TRANSLATION_HIT_CLIENT2 = 320 +PERF_UTCL1_REQUEST_CLIENT0 = 321 +PERF_UTCL1_REQUEST_CLIENT1 = 322 +PERF_UTCL1_REQUEST_CLIENT2 = 323 +PERF_UTCL1_STALL_MISSFIFO_FULL = 324 +PERF_UTCL1_STALL_INFLIGHT_MAX = 325 +PERF_UTCL1_STALL_LRU_INFLIGHT = 326 +PERF_UTCL1_STALL_MULTI_MISS = 327 +PERF_UTCL1_LFIFO_FULL = 328 +PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0 = 329 +PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1 = 330 +PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2 = 331 +PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 332 +PERF_UTCL1_UTCL2_REQ = 333 +PERF_UTCL1_UTCL2_RET = 334 +PERF_UTCL1_UTCL2_INFLIGHT = 335 +PERF_CLIENT_UTCL1_INFLIGHT = 336 +PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 337 +PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 338 +PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 339 +PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 340 +PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 341 +PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 342 +PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 343 +PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 344 +PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 345 +PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 346 +PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 347 +PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 348 +PERF_PA_VERTEX_FIFO_FULL = 349 +PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 350 +PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 351 +PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 352 +ENGG_CSB_MACHINE_IS_STARVED = 355 +ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 356 +ENGG_CSB_MACHINE_STALLED_BY_SPI = 357 +ENGG_CSB_GE_INPUT_FIFO_FULL = 358 +ENGG_CSB_SPI_INPUT_FIFO_FULL = 359 +ENGG_CSB_OBJECTID_INPUT_FIFO_FULL = 360 +ENGG_CSB_PRIM_COUNT_EQ0 = 361 +ENGG_CSB_GE_SENDING_SUBGROUP = 362 +ENGG_CSB_DELAY_BIN00 = 363 +ENGG_CSB_DELAY_BIN01 = 364 +ENGG_CSB_DELAY_BIN02 = 365 +ENGG_CSB_DELAY_BIN03 = 366 +ENGG_CSB_DELAY_BIN04 = 367 +ENGG_CSB_DELAY_BIN05 = 368 +ENGG_CSB_DELAY_BIN06 = 369 +ENGG_CSB_DELAY_BIN07 = 370 +ENGG_CSB_DELAY_BIN08 = 371 +ENGG_CSB_DELAY_BIN09 = 372 +ENGG_CSB_DELAY_BIN10 = 373 +ENGG_CSB_DELAY_BIN11 = 374 +ENGG_CSB_DELAY_BIN12 = 375 +ENGG_CSB_DELAY_BIN13 = 376 +ENGG_CSB_DELAY_BIN14 = 377 +ENGG_CSB_DELAY_BIN15 = 378 +ENGG_CSB_SPI_DELAY_BIN00 = 379 +ENGG_CSB_SPI_DELAY_BIN01 = 380 +ENGG_CSB_SPI_DELAY_BIN02 = 381 +ENGG_CSB_SPI_DELAY_BIN03 = 382 +ENGG_CSB_SPI_DELAY_BIN04 = 383 +ENGG_CSB_SPI_DELAY_BIN05 = 384 +ENGG_CSB_SPI_DELAY_BIN06 = 385 +ENGG_CSB_SPI_DELAY_BIN07 = 386 +ENGG_CSB_SPI_DELAY_BIN08 = 387 +ENGG_CSB_SPI_DELAY_BIN09 = 388 +ENGG_CSB_SPI_DELAY_BIN10 = 389 +ENGG_CSB_SPI_DELAY_BIN11 = 390 +ENGG_CSB_SPI_DELAY_BIN12 = 391 +ENGG_CSB_SPI_DELAY_BIN13 = 392 +ENGG_CSB_SPI_DELAY_BIN14 = 393 +ENGG_CSB_SPI_DELAY_BIN15 = 394 +ENGG_INDEX_REQ_STARVED = 395 +ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 396 +ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 397 +ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 398 +ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 399 +ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 400 +ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 401 +ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 402 +ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 403 +ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 404 +ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 405 +ENGG_INDEX_RET_SXRX_READING_EVENT = 406 +ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 407 +ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 408 +ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 409 +ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 410 +ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 411 +ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 412 +ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS = 413 +ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS = 414 +ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS = 415 +ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 416 +ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 417 +ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 418 +ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 419 +ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 420 +ENGG_INDEX_PRIM_IF_QUALIFIED_BUSY = 421 +ENGG_INDEX_PRIM_IF_QUALIFIED_STARVED = 422 +ENGG_INDEX_PRIM_IF_REUSE_0_NEW_VERTS_THIS_PRIM = 423 +ENGG_INDEX_PRIM_IF_REUSE_1_NEW_VERTS_THIS_PRIM = 424 +ENGG_INDEX_PRIM_IF_REUSE_2_NEW_VERTS_THIS_PRIM = 425 +ENGG_INDEX_PRIM_IF_REUSE_3_NEW_VERTS_THIS_PRIM = 426 +ENGG_POS_REQ_STARVED = 427 +ENGG_POS_REQ_STALLED_BY_FULL_CLIPV_FIFO = 428 +SU_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SC_PERFCNT_SEL' +SC_PERFCNT_SEL__enumvalues = { + 0: 'SC_SRPS_WINDOW_VALID', + 1: 'SC_PSSW_WINDOW_VALID', + 2: 'SC_TPQZ_WINDOW_VALID', + 3: 'SC_QZQP_WINDOW_VALID', + 4: 'SC_TRPK_WINDOW_VALID', + 5: 'SC_SRPS_WINDOW_VALID_BUSY', + 6: 'SC_PSSW_WINDOW_VALID_BUSY', + 7: 'SC_TPQZ_WINDOW_VALID_BUSY', + 8: 'SC_QZQP_WINDOW_VALID_BUSY', + 9: 'SC_TRPK_WINDOW_VALID_BUSY', + 10: 'SC_STARVED_BY_PA', + 11: 'SC_STALLED_BY_PRIMFIFO', + 12: 'SC_STALLED_BY_DB_TILE', + 13: 'SC_STARVED_BY_DB_TILE', + 14: 'SC_STALLED_BY_TILEORDERFIFO', + 15: 'SC_STALLED_BY_TILEFIFO', + 16: 'SC_STALLED_BY_DB_QUAD', + 17: 'SC_STARVED_BY_DB_QUAD', + 18: 'SC_STALLED_BY_QUADFIFO', + 19: 'SC_STALLED_BY_BCI', + 20: 'SC_STALLED_BY_SPI', + 21: 'SC_SCISSOR_DISCARD', + 22: 'SC_BB_DISCARD', + 23: 'SC_SUPERTILE_COUNT', + 24: 'SC_SUPERTILE_PER_PRIM_H0', + 25: 'SC_SUPERTILE_PER_PRIM_H1', + 26: 'SC_SUPERTILE_PER_PRIM_H2', + 27: 'SC_SUPERTILE_PER_PRIM_H3', + 28: 'SC_SUPERTILE_PER_PRIM_H4', + 29: 'SC_SUPERTILE_PER_PRIM_H5', + 30: 'SC_SUPERTILE_PER_PRIM_H6', + 31: 'SC_SUPERTILE_PER_PRIM_H7', + 32: 'SC_SUPERTILE_PER_PRIM_H8', + 33: 'SC_SUPERTILE_PER_PRIM_H9', + 34: 'SC_SUPERTILE_PER_PRIM_H10', + 35: 'SC_SUPERTILE_PER_PRIM_H11', + 36: 'SC_SUPERTILE_PER_PRIM_H12', + 37: 'SC_SUPERTILE_PER_PRIM_H13', + 38: 'SC_SUPERTILE_PER_PRIM_H14', + 39: 'SC_SUPERTILE_PER_PRIM_H15', + 40: 'SC_SUPERTILE_PER_PRIM_H16', + 41: 'SC_TILE_PER_PRIM_H0', + 42: 'SC_TILE_PER_PRIM_H1', + 43: 'SC_TILE_PER_PRIM_H2', + 44: 'SC_TILE_PER_PRIM_H3', + 45: 'SC_TILE_PER_PRIM_H4', + 46: 'SC_TILE_PER_PRIM_H5', + 47: 'SC_TILE_PER_PRIM_H6', + 48: 'SC_TILE_PER_PRIM_H7', + 49: 'SC_TILE_PER_PRIM_H8', + 50: 'SC_TILE_PER_PRIM_H9', + 51: 'SC_TILE_PER_PRIM_H10', + 52: 'SC_TILE_PER_PRIM_H11', + 53: 'SC_TILE_PER_PRIM_H12', + 54: 'SC_TILE_PER_PRIM_H13', + 55: 'SC_TILE_PER_PRIM_H14', + 56: 'SC_TILE_PER_PRIM_H15', + 57: 'SC_TILE_PER_PRIM_H16', + 58: 'SC_TILE_PER_SUPERTILE_H0', + 59: 'SC_TILE_PER_SUPERTILE_H1', + 60: 'SC_TILE_PER_SUPERTILE_H2', + 61: 'SC_TILE_PER_SUPERTILE_H3', + 62: 'SC_TILE_PER_SUPERTILE_H4', + 63: 'SC_TILE_PER_SUPERTILE_H5', + 64: 'SC_TILE_PER_SUPERTILE_H6', + 65: 'SC_TILE_PER_SUPERTILE_H7', + 66: 'SC_TILE_PER_SUPERTILE_H8', + 67: 'SC_TILE_PER_SUPERTILE_H9', + 68: 'SC_TILE_PER_SUPERTILE_H10', + 69: 'SC_TILE_PER_SUPERTILE_H11', + 70: 'SC_TILE_PER_SUPERTILE_H12', + 71: 'SC_TILE_PER_SUPERTILE_H13', + 72: 'SC_TILE_PER_SUPERTILE_H14', + 73: 'SC_TILE_PER_SUPERTILE_H15', + 74: 'SC_TILE_PER_SUPERTILE_H16', + 75: 'SC_TILE_PICKED_H1', + 76: 'SC_TILE_PICKED_H2', + 77: 'SC_TILE_PICKED_H3', + 78: 'SC_TILE_PICKED_H4', + 79: 'SC_QZ0_TILE_COUNT', + 80: 'SC_QZ1_TILE_COUNT', + 81: 'SC_QZ2_TILE_COUNT', + 82: 'SC_QZ3_TILE_COUNT', + 83: 'SC_QZ0_TILE_COVERED_COUNT', + 84: 'SC_QZ1_TILE_COVERED_COUNT', + 85: 'SC_QZ2_TILE_COVERED_COUNT', + 86: 'SC_QZ3_TILE_COVERED_COUNT', + 87: 'SC_QZ0_TILE_NOT_COVERED_COUNT', + 88: 'SC_QZ1_TILE_NOT_COVERED_COUNT', + 89: 'SC_QZ2_TILE_NOT_COVERED_COUNT', + 90: 'SC_QZ3_TILE_NOT_COVERED_COUNT', + 91: 'SC_QZ0_QUAD_PER_TILE_H0', + 92: 'SC_QZ0_QUAD_PER_TILE_H1', + 93: 'SC_QZ0_QUAD_PER_TILE_H2', + 94: 'SC_QZ0_QUAD_PER_TILE_H3', + 95: 'SC_QZ0_QUAD_PER_TILE_H4', + 96: 'SC_QZ0_QUAD_PER_TILE_H5', + 97: 'SC_QZ0_QUAD_PER_TILE_H6', + 98: 'SC_QZ0_QUAD_PER_TILE_H7', + 99: 'SC_QZ0_QUAD_PER_TILE_H8', + 100: 'SC_QZ0_QUAD_PER_TILE_H9', + 101: 'SC_QZ0_QUAD_PER_TILE_H10', + 102: 'SC_QZ0_QUAD_PER_TILE_H11', + 103: 'SC_QZ0_QUAD_PER_TILE_H12', + 104: 'SC_QZ0_QUAD_PER_TILE_H13', + 105: 'SC_QZ0_QUAD_PER_TILE_H14', + 106: 'SC_QZ0_QUAD_PER_TILE_H15', + 107: 'SC_QZ0_QUAD_PER_TILE_H16', + 108: 'SC_QZ1_QUAD_PER_TILE_H0', + 109: 'SC_QZ1_QUAD_PER_TILE_H1', + 110: 'SC_QZ1_QUAD_PER_TILE_H2', + 111: 'SC_QZ1_QUAD_PER_TILE_H3', + 112: 'SC_QZ1_QUAD_PER_TILE_H4', + 113: 'SC_QZ1_QUAD_PER_TILE_H5', + 114: 'SC_QZ1_QUAD_PER_TILE_H6', + 115: 'SC_QZ1_QUAD_PER_TILE_H7', + 116: 'SC_QZ1_QUAD_PER_TILE_H8', + 117: 'SC_QZ1_QUAD_PER_TILE_H9', + 118: 'SC_QZ1_QUAD_PER_TILE_H10', + 119: 'SC_QZ1_QUAD_PER_TILE_H11', + 120: 'SC_QZ1_QUAD_PER_TILE_H12', + 121: 'SC_QZ1_QUAD_PER_TILE_H13', + 122: 'SC_QZ1_QUAD_PER_TILE_H14', + 123: 'SC_QZ1_QUAD_PER_TILE_H15', + 124: 'SC_QZ1_QUAD_PER_TILE_H16', + 125: 'SC_QZ2_QUAD_PER_TILE_H0', + 126: 'SC_QZ2_QUAD_PER_TILE_H1', + 127: 'SC_QZ2_QUAD_PER_TILE_H2', + 128: 'SC_QZ2_QUAD_PER_TILE_H3', + 129: 'SC_QZ2_QUAD_PER_TILE_H4', + 130: 'SC_QZ2_QUAD_PER_TILE_H5', + 131: 'SC_QZ2_QUAD_PER_TILE_H6', + 132: 'SC_QZ2_QUAD_PER_TILE_H7', + 133: 'SC_QZ2_QUAD_PER_TILE_H8', + 134: 'SC_QZ2_QUAD_PER_TILE_H9', + 135: 'SC_QZ2_QUAD_PER_TILE_H10', + 136: 'SC_QZ2_QUAD_PER_TILE_H11', + 137: 'SC_QZ2_QUAD_PER_TILE_H12', + 138: 'SC_QZ2_QUAD_PER_TILE_H13', + 139: 'SC_QZ2_QUAD_PER_TILE_H14', + 140: 'SC_QZ2_QUAD_PER_TILE_H15', + 141: 'SC_QZ2_QUAD_PER_TILE_H16', + 142: 'SC_QZ3_QUAD_PER_TILE_H0', + 143: 'SC_QZ3_QUAD_PER_TILE_H1', + 144: 'SC_QZ3_QUAD_PER_TILE_H2', + 145: 'SC_QZ3_QUAD_PER_TILE_H3', + 146: 'SC_QZ3_QUAD_PER_TILE_H4', + 147: 'SC_QZ3_QUAD_PER_TILE_H5', + 148: 'SC_QZ3_QUAD_PER_TILE_H6', + 149: 'SC_QZ3_QUAD_PER_TILE_H7', + 150: 'SC_QZ3_QUAD_PER_TILE_H8', + 151: 'SC_QZ3_QUAD_PER_TILE_H9', + 152: 'SC_QZ3_QUAD_PER_TILE_H10', + 153: 'SC_QZ3_QUAD_PER_TILE_H11', + 154: 'SC_QZ3_QUAD_PER_TILE_H12', + 155: 'SC_QZ3_QUAD_PER_TILE_H13', + 156: 'SC_QZ3_QUAD_PER_TILE_H14', + 157: 'SC_QZ3_QUAD_PER_TILE_H15', + 158: 'SC_QZ3_QUAD_PER_TILE_H16', + 159: 'SC_QZ0_QUAD_COUNT', + 160: 'SC_QZ1_QUAD_COUNT', + 161: 'SC_QZ2_QUAD_COUNT', + 162: 'SC_QZ3_QUAD_COUNT', + 163: 'SC_P0_HIZ_TILE_COUNT', + 164: 'SC_P1_HIZ_TILE_COUNT', + 165: 'SC_P2_HIZ_TILE_COUNT', + 166: 'SC_P3_HIZ_TILE_COUNT', + 167: 'SC_P0_HIZ_QUAD_PER_TILE_H0', + 168: 'SC_P0_HIZ_QUAD_PER_TILE_H1', + 169: 'SC_P0_HIZ_QUAD_PER_TILE_H2', + 170: 'SC_P0_HIZ_QUAD_PER_TILE_H3', + 171: 'SC_P0_HIZ_QUAD_PER_TILE_H4', + 172: 'SC_P0_HIZ_QUAD_PER_TILE_H5', + 173: 'SC_P0_HIZ_QUAD_PER_TILE_H6', + 174: 'SC_P0_HIZ_QUAD_PER_TILE_H7', + 175: 'SC_P0_HIZ_QUAD_PER_TILE_H8', + 176: 'SC_P0_HIZ_QUAD_PER_TILE_H9', + 177: 'SC_P0_HIZ_QUAD_PER_TILE_H10', + 178: 'SC_P0_HIZ_QUAD_PER_TILE_H11', + 179: 'SC_P0_HIZ_QUAD_PER_TILE_H12', + 180: 'SC_P0_HIZ_QUAD_PER_TILE_H13', + 181: 'SC_P0_HIZ_QUAD_PER_TILE_H14', + 182: 'SC_P0_HIZ_QUAD_PER_TILE_H15', + 183: 'SC_P0_HIZ_QUAD_PER_TILE_H16', + 184: 'SC_P1_HIZ_QUAD_PER_TILE_H0', + 185: 'SC_P1_HIZ_QUAD_PER_TILE_H1', + 186: 'SC_P1_HIZ_QUAD_PER_TILE_H2', + 187: 'SC_P1_HIZ_QUAD_PER_TILE_H3', + 188: 'SC_P1_HIZ_QUAD_PER_TILE_H4', + 189: 'SC_P1_HIZ_QUAD_PER_TILE_H5', + 190: 'SC_P1_HIZ_QUAD_PER_TILE_H6', + 191: 'SC_P1_HIZ_QUAD_PER_TILE_H7', + 192: 'SC_P1_HIZ_QUAD_PER_TILE_H8', + 193: 'SC_P1_HIZ_QUAD_PER_TILE_H9', + 194: 'SC_P1_HIZ_QUAD_PER_TILE_H10', + 195: 'SC_P1_HIZ_QUAD_PER_TILE_H11', + 196: 'SC_P1_HIZ_QUAD_PER_TILE_H12', + 197: 'SC_P1_HIZ_QUAD_PER_TILE_H13', + 198: 'SC_P1_HIZ_QUAD_PER_TILE_H14', + 199: 'SC_P1_HIZ_QUAD_PER_TILE_H15', + 200: 'SC_P1_HIZ_QUAD_PER_TILE_H16', + 201: 'SC_P2_HIZ_QUAD_PER_TILE_H0', + 202: 'SC_P2_HIZ_QUAD_PER_TILE_H1', + 203: 'SC_P2_HIZ_QUAD_PER_TILE_H2', + 204: 'SC_P2_HIZ_QUAD_PER_TILE_H3', + 205: 'SC_P2_HIZ_QUAD_PER_TILE_H4', + 206: 'SC_P2_HIZ_QUAD_PER_TILE_H5', + 207: 'SC_P2_HIZ_QUAD_PER_TILE_H6', + 208: 'SC_P2_HIZ_QUAD_PER_TILE_H7', + 209: 'SC_P2_HIZ_QUAD_PER_TILE_H8', + 210: 'SC_P2_HIZ_QUAD_PER_TILE_H9', + 211: 'SC_P2_HIZ_QUAD_PER_TILE_H10', + 212: 'SC_P2_HIZ_QUAD_PER_TILE_H11', + 213: 'SC_P2_HIZ_QUAD_PER_TILE_H12', + 214: 'SC_P2_HIZ_QUAD_PER_TILE_H13', + 215: 'SC_P2_HIZ_QUAD_PER_TILE_H14', + 216: 'SC_P2_HIZ_QUAD_PER_TILE_H15', + 217: 'SC_P2_HIZ_QUAD_PER_TILE_H16', + 218: 'SC_P3_HIZ_QUAD_PER_TILE_H0', + 219: 'SC_P3_HIZ_QUAD_PER_TILE_H1', + 220: 'SC_P3_HIZ_QUAD_PER_TILE_H2', + 221: 'SC_P3_HIZ_QUAD_PER_TILE_H3', + 222: 'SC_P3_HIZ_QUAD_PER_TILE_H4', + 223: 'SC_P3_HIZ_QUAD_PER_TILE_H5', + 224: 'SC_P3_HIZ_QUAD_PER_TILE_H6', + 225: 'SC_P3_HIZ_QUAD_PER_TILE_H7', + 226: 'SC_P3_HIZ_QUAD_PER_TILE_H8', + 227: 'SC_P3_HIZ_QUAD_PER_TILE_H9', + 228: 'SC_P3_HIZ_QUAD_PER_TILE_H10', + 229: 'SC_P3_HIZ_QUAD_PER_TILE_H11', + 230: 'SC_P3_HIZ_QUAD_PER_TILE_H12', + 231: 'SC_P3_HIZ_QUAD_PER_TILE_H13', + 232: 'SC_P3_HIZ_QUAD_PER_TILE_H14', + 233: 'SC_P3_HIZ_QUAD_PER_TILE_H15', + 234: 'SC_P3_HIZ_QUAD_PER_TILE_H16', + 235: 'SC_P0_HIZ_QUAD_COUNT', + 236: 'SC_P1_HIZ_QUAD_COUNT', + 237: 'SC_P2_HIZ_QUAD_COUNT', + 238: 'SC_P3_HIZ_QUAD_COUNT', + 239: 'SC_P0_DETAIL_QUAD_COUNT', + 240: 'SC_P1_DETAIL_QUAD_COUNT', + 241: 'SC_P2_DETAIL_QUAD_COUNT', + 242: 'SC_P3_DETAIL_QUAD_COUNT', + 243: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', + 244: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', + 245: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', + 246: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', + 247: 'SC_P1_DETAIL_QUAD_WITH_1_PIX', + 248: 'SC_P1_DETAIL_QUAD_WITH_2_PIX', + 249: 'SC_P1_DETAIL_QUAD_WITH_3_PIX', + 250: 'SC_P1_DETAIL_QUAD_WITH_4_PIX', + 251: 'SC_P2_DETAIL_QUAD_WITH_1_PIX', + 252: 'SC_P2_DETAIL_QUAD_WITH_2_PIX', + 253: 'SC_P2_DETAIL_QUAD_WITH_3_PIX', + 254: 'SC_P2_DETAIL_QUAD_WITH_4_PIX', + 255: 'SC_P3_DETAIL_QUAD_WITH_1_PIX', + 256: 'SC_P3_DETAIL_QUAD_WITH_2_PIX', + 257: 'SC_P3_DETAIL_QUAD_WITH_3_PIX', + 258: 'SC_P3_DETAIL_QUAD_WITH_4_PIX', + 259: 'SC_EARLYZ_QUAD_COUNT', + 260: 'SC_EARLYZ_QUAD_WITH_1_PIX', + 261: 'SC_EARLYZ_QUAD_WITH_2_PIX', + 262: 'SC_EARLYZ_QUAD_WITH_3_PIX', + 263: 'SC_EARLYZ_QUAD_WITH_4_PIX', + 264: 'SC_PKR_QUAD_PER_ROW_H1', + 265: 'SC_PKR_QUAD_PER_ROW_H2', + 266: 'SC_PKR_4X2_QUAD_SPLIT', + 267: 'SC_PKR_4X2_FILL_QUAD', + 268: 'SC_PKR_END_OF_VECTOR', + 269: 'SC_PKR_CONTROL_XFER', + 270: 'SC_PKR_DBHANG_FORCE_EOV', + 271: 'SC_REG_SCLK_BUSY', + 272: 'SC_GRP0_DYN_SCLK_BUSY', + 273: 'SC_GRP1_DYN_SCLK_BUSY', + 274: 'SC_GRP2_DYN_SCLK_BUSY', + 275: 'SC_GRP3_DYN_SCLK_BUSY', + 276: 'SC_GRP4_DYN_SCLK_BUSY', + 277: 'SC_PA0_SC_DATA_FIFO_RD', + 278: 'SC_PA0_SC_DATA_FIFO_WE', + 279: 'SC_PA1_SC_DATA_FIFO_RD', + 280: 'SC_PA1_SC_DATA_FIFO_WE', + 281: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 282: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', + 283: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 284: 'SC_PS_ARB_STALLED_FROM_BELOW', + 285: 'SC_PS_ARB_STARVED_FROM_ABOVE', + 286: 'SC_PS_ARB_SC_BUSY', + 287: 'SC_PS_ARB_PA_SC_BUSY', + 288: 'SC_PA2_SC_DATA_FIFO_RD', + 289: 'SC_PA2_SC_DATA_FIFO_WE', + 290: 'SC_PA3_SC_DATA_FIFO_RD', + 291: 'SC_PA3_SC_DATA_FIFO_WE', + 292: 'SC_PA_SC_DEALLOC_0_0_WE', + 293: 'SC_PA_SC_DEALLOC_0_1_WE', + 294: 'SC_PA_SC_DEALLOC_1_0_WE', + 295: 'SC_PA_SC_DEALLOC_1_1_WE', + 296: 'SC_PA_SC_DEALLOC_2_0_WE', + 297: 'SC_PA_SC_DEALLOC_2_1_WE', + 298: 'SC_PA_SC_DEALLOC_3_0_WE', + 299: 'SC_PA_SC_DEALLOC_3_1_WE', + 300: 'SC_PA0_SC_EOP_WE', + 301: 'SC_PA0_SC_EOPG_WE', + 302: 'SC_PA0_SC_EVENT_WE', + 303: 'SC_PA1_SC_EOP_WE', + 304: 'SC_PA1_SC_EOPG_WE', + 305: 'SC_PA1_SC_EVENT_WE', + 306: 'SC_PA2_SC_EOP_WE', + 307: 'SC_PA2_SC_EOPG_WE', + 308: 'SC_PA2_SC_EVENT_WE', + 309: 'SC_PA3_SC_EOP_WE', + 310: 'SC_PA3_SC_EOPG_WE', + 311: 'SC_PA3_SC_EVENT_WE', + 312: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', + 313: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', + 314: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', + 315: 'SC_PS_ARB_EOP_POP_SYNC_POP', + 316: 'SC_PS_ARB_EVENT_SYNC_POP', + 317: 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', + 318: 'SC_PA0_SC_FPOV_WE', + 319: 'SC_PA1_SC_FPOV_WE', + 320: 'SC_PA2_SC_FPOV_WE', + 321: 'SC_PA3_SC_FPOV_WE', + 322: 'SC_PA0_SC_LPOV_WE', + 323: 'SC_PA1_SC_LPOV_WE', + 324: 'SC_PA2_SC_LPOV_WE', + 325: 'SC_PA3_SC_LPOV_WE', + 326: 'SC_SC_SPI_DEALLOC_0_0', + 327: 'SC_SC_SPI_DEALLOC_0_1', + 328: 'SC_SC_SPI_DEALLOC_0_2', + 329: 'SC_SC_SPI_DEALLOC_1_0', + 330: 'SC_SC_SPI_DEALLOC_1_1', + 331: 'SC_SC_SPI_DEALLOC_1_2', + 332: 'SC_SC_SPI_DEALLOC_2_0', + 333: 'SC_SC_SPI_DEALLOC_2_1', + 334: 'SC_SC_SPI_DEALLOC_2_2', + 335: 'SC_SC_SPI_DEALLOC_3_0', + 336: 'SC_SC_SPI_DEALLOC_3_1', + 337: 'SC_SC_SPI_DEALLOC_3_2', + 338: 'SC_SC_SPI_FPOV_0', + 339: 'SC_SC_SPI_FPOV_1', + 340: 'SC_SC_SPI_FPOV_2', + 341: 'SC_SC_SPI_FPOV_3', + 342: 'SC_SC_SPI_EVENT', + 343: 'SC_PS_TS_EVENT_FIFO_PUSH', + 344: 'SC_PS_TS_EVENT_FIFO_POP', + 345: 'SC_PS_CTX_DONE_FIFO_PUSH', + 346: 'SC_PS_CTX_DONE_FIFO_POP', + 347: 'SC_MULTICYCLE_BUBBLE_FREEZE', + 348: 'SC_EOP_SYNC_WINDOW', + 349: 'SC_PA0_SC_NULL_WE', + 350: 'SC_PA0_SC_NULL_DEALLOC_WE', + 351: 'SC_PA0_SC_DATA_FIFO_EOPG_RD', + 352: 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 353: 'SC_PA0_SC_DEALLOC_0_RD', + 354: 'SC_PA0_SC_DEALLOC_1_RD', + 355: 'SC_PA1_SC_DATA_FIFO_EOPG_RD', + 356: 'SC_PA1_SC_DATA_FIFO_EOP_RD', + 357: 'SC_PA1_SC_DEALLOC_0_RD', + 358: 'SC_PA1_SC_DEALLOC_1_RD', + 359: 'SC_PA1_SC_NULL_WE', + 360: 'SC_PA1_SC_NULL_DEALLOC_WE', + 361: 'SC_PA2_SC_DATA_FIFO_EOPG_RD', + 362: 'SC_PA2_SC_DATA_FIFO_EOP_RD', + 363: 'SC_PA2_SC_DEALLOC_0_RD', + 364: 'SC_PA2_SC_DEALLOC_1_RD', + 365: 'SC_PA2_SC_NULL_WE', + 366: 'SC_PA2_SC_NULL_DEALLOC_WE', + 367: 'SC_PA3_SC_DATA_FIFO_EOPG_RD', + 368: 'SC_PA3_SC_DATA_FIFO_EOP_RD', + 369: 'SC_PA3_SC_DEALLOC_0_RD', + 370: 'SC_PA3_SC_DEALLOC_1_RD', + 371: 'SC_PA3_SC_NULL_WE', + 372: 'SC_PA3_SC_NULL_DEALLOC_WE', + 373: 'SC_PS_PA0_SC_FIFO_EMPTY', + 374: 'SC_PS_PA0_SC_FIFO_FULL', + 375: 'SC_RESERVED_0', + 376: 'SC_PS_PA1_SC_FIFO_EMPTY', + 377: 'SC_PS_PA1_SC_FIFO_FULL', + 378: 'SC_RESERVED_1', + 379: 'SC_PS_PA2_SC_FIFO_EMPTY', + 380: 'SC_PS_PA2_SC_FIFO_FULL', + 381: 'SC_RESERVED_2', + 382: 'SC_PS_PA3_SC_FIFO_EMPTY', + 383: 'SC_PS_PA3_SC_FIFO_FULL', + 384: 'SC_RESERVED_3', + 385: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', + 386: 'SC_BUSY_CNT_NOT_ZERO', + 387: 'SC_BM_BUSY', + 388: 'SC_BACKEND_BUSY', + 389: 'SC_SCF_SCB_INTERFACE_BUSY', + 390: 'SC_SCB_BUSY', + 391: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 392: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 393: 'SC_PBB_BIN_HIST_NUM_PRIMS', + 394: 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 395: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 396: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 397: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 398: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 399: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 400: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 401: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 402: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 403: 'SC_PBB_BUSY', + 404: 'SC_PBB_BUSY_AND_NO_SENDS', + 405: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 406: 'SC_PBB_NUM_BINS', + 407: 'SC_PBB_END_OF_BIN', + 408: 'SC_PBB_END_OF_BATCH', + 409: 'SC_PBB_PRIMBIN_PROCESSED', + 410: 'SC_PBB_PRIM_ADDED_TO_BATCH', + 411: 'SC_PBB_NONBINNED_PRIM', + 412: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', + 413: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 414: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 415: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 416: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 417: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 418: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 419: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 420: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 421: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 422: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 423: 'SC_POPS_INTRA_WAVE_OVERLAPS', + 424: 'SC_POPS_FORCE_EOV', + 425: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', + 426: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', + 427: 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', + 428: 'SC_FULL_FULL_QUAD', + 429: 'SC_FULL_HALF_QUAD', + 430: 'SC_FULL_QTR_QUAD', + 431: 'SC_HALF_FULL_QUAD', + 432: 'SC_HALF_HALF_QUAD', + 433: 'SC_HALF_QTR_QUAD', + 434: 'SC_QTR_FULL_QUAD', + 435: 'SC_QTR_HALF_QUAD', + 436: 'SC_QTR_QTR_QUAD', + 437: 'SC_GRP5_DYN_SCLK_BUSY', + 438: 'SC_GRP6_DYN_SCLK_BUSY', + 439: 'SC_GRP7_DYN_SCLK_BUSY', + 440: 'SC_GRP8_DYN_SCLK_BUSY', + 441: 'SC_GRP9_DYN_SCLK_BUSY', + 442: 'SC_PS_TO_BE_SCLK_GATE_STALL', + 443: 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', + 444: 'SC_PK_BUSY', + 445: 'SC_PK_MAX_DEALLOC_FORCE_EOV', + 446: 'SC_PK_DEALLOC_WAVE_BREAK', + 447: 'SC_SPI_SEND', + 448: 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 449: 'SC_SPI_CREDIT_AT_MAX', + 450: 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', + 451: 'SC_BCI_SEND', + 452: 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 453: 'SC_BCI_CREDIT_AT_MAX', + 454: 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', + 455: 'SC_SPIBC_FULL_FREEZE', + 456: 'SC_PW_BM_PASS_EMPTY_PRIM', + 457: 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', + 458: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', + 459: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', + 460: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', + 461: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', + 462: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', + 463: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', + 464: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', + 465: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', + 466: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', + 467: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', + 468: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', + 469: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', + 470: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', + 471: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', + 472: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', + 473: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', + 474: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', + 475: 'SC_DB0_TILE_INTERFACE_BUSY', + 476: 'SC_DB0_TILE_INTERFACE_SEND', + 477: 'SC_DB0_TILE_INTERFACE_SEND_EVENT', + 478: 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 479: 'SC_DB0_TILE_INTERFACE_SEND_SOP', + 480: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 481: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', + 482: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 483: 'SC_DB1_TILE_INTERFACE_BUSY', + 484: 'SC_DB1_TILE_INTERFACE_SEND', + 485: 'SC_DB1_TILE_INTERFACE_SEND_EVENT', + 486: 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 487: 'SC_DB1_TILE_INTERFACE_SEND_SOP', + 488: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 489: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', + 490: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 491: 'SC_BACKEND_PRIM_FIFO_FULL', + 492: 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', + 493: 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', + 494: 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', + 495: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', + 496: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', + 497: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', + 498: 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', + 499: 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', + 500: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', +} +SC_SRPS_WINDOW_VALID = 0 +SC_PSSW_WINDOW_VALID = 1 +SC_TPQZ_WINDOW_VALID = 2 +SC_QZQP_WINDOW_VALID = 3 +SC_TRPK_WINDOW_VALID = 4 +SC_SRPS_WINDOW_VALID_BUSY = 5 +SC_PSSW_WINDOW_VALID_BUSY = 6 +SC_TPQZ_WINDOW_VALID_BUSY = 7 +SC_QZQP_WINDOW_VALID_BUSY = 8 +SC_TRPK_WINDOW_VALID_BUSY = 9 +SC_STARVED_BY_PA = 10 +SC_STALLED_BY_PRIMFIFO = 11 +SC_STALLED_BY_DB_TILE = 12 +SC_STARVED_BY_DB_TILE = 13 +SC_STALLED_BY_TILEORDERFIFO = 14 +SC_STALLED_BY_TILEFIFO = 15 +SC_STALLED_BY_DB_QUAD = 16 +SC_STARVED_BY_DB_QUAD = 17 +SC_STALLED_BY_QUADFIFO = 18 +SC_STALLED_BY_BCI = 19 +SC_STALLED_BY_SPI = 20 +SC_SCISSOR_DISCARD = 21 +SC_BB_DISCARD = 22 +SC_SUPERTILE_COUNT = 23 +SC_SUPERTILE_PER_PRIM_H0 = 24 +SC_SUPERTILE_PER_PRIM_H1 = 25 +SC_SUPERTILE_PER_PRIM_H2 = 26 +SC_SUPERTILE_PER_PRIM_H3 = 27 +SC_SUPERTILE_PER_PRIM_H4 = 28 +SC_SUPERTILE_PER_PRIM_H5 = 29 +SC_SUPERTILE_PER_PRIM_H6 = 30 +SC_SUPERTILE_PER_PRIM_H7 = 31 +SC_SUPERTILE_PER_PRIM_H8 = 32 +SC_SUPERTILE_PER_PRIM_H9 = 33 +SC_SUPERTILE_PER_PRIM_H10 = 34 +SC_SUPERTILE_PER_PRIM_H11 = 35 +SC_SUPERTILE_PER_PRIM_H12 = 36 +SC_SUPERTILE_PER_PRIM_H13 = 37 +SC_SUPERTILE_PER_PRIM_H14 = 38 +SC_SUPERTILE_PER_PRIM_H15 = 39 +SC_SUPERTILE_PER_PRIM_H16 = 40 +SC_TILE_PER_PRIM_H0 = 41 +SC_TILE_PER_PRIM_H1 = 42 +SC_TILE_PER_PRIM_H2 = 43 +SC_TILE_PER_PRIM_H3 = 44 +SC_TILE_PER_PRIM_H4 = 45 +SC_TILE_PER_PRIM_H5 = 46 +SC_TILE_PER_PRIM_H6 = 47 +SC_TILE_PER_PRIM_H7 = 48 +SC_TILE_PER_PRIM_H8 = 49 +SC_TILE_PER_PRIM_H9 = 50 +SC_TILE_PER_PRIM_H10 = 51 +SC_TILE_PER_PRIM_H11 = 52 +SC_TILE_PER_PRIM_H12 = 53 +SC_TILE_PER_PRIM_H13 = 54 +SC_TILE_PER_PRIM_H14 = 55 +SC_TILE_PER_PRIM_H15 = 56 +SC_TILE_PER_PRIM_H16 = 57 +SC_TILE_PER_SUPERTILE_H0 = 58 +SC_TILE_PER_SUPERTILE_H1 = 59 +SC_TILE_PER_SUPERTILE_H2 = 60 +SC_TILE_PER_SUPERTILE_H3 = 61 +SC_TILE_PER_SUPERTILE_H4 = 62 +SC_TILE_PER_SUPERTILE_H5 = 63 +SC_TILE_PER_SUPERTILE_H6 = 64 +SC_TILE_PER_SUPERTILE_H7 = 65 +SC_TILE_PER_SUPERTILE_H8 = 66 +SC_TILE_PER_SUPERTILE_H9 = 67 +SC_TILE_PER_SUPERTILE_H10 = 68 +SC_TILE_PER_SUPERTILE_H11 = 69 +SC_TILE_PER_SUPERTILE_H12 = 70 +SC_TILE_PER_SUPERTILE_H13 = 71 +SC_TILE_PER_SUPERTILE_H14 = 72 +SC_TILE_PER_SUPERTILE_H15 = 73 +SC_TILE_PER_SUPERTILE_H16 = 74 +SC_TILE_PICKED_H1 = 75 +SC_TILE_PICKED_H2 = 76 +SC_TILE_PICKED_H3 = 77 +SC_TILE_PICKED_H4 = 78 +SC_QZ0_TILE_COUNT = 79 +SC_QZ1_TILE_COUNT = 80 +SC_QZ2_TILE_COUNT = 81 +SC_QZ3_TILE_COUNT = 82 +SC_QZ0_TILE_COVERED_COUNT = 83 +SC_QZ1_TILE_COVERED_COUNT = 84 +SC_QZ2_TILE_COVERED_COUNT = 85 +SC_QZ3_TILE_COVERED_COUNT = 86 +SC_QZ0_TILE_NOT_COVERED_COUNT = 87 +SC_QZ1_TILE_NOT_COVERED_COUNT = 88 +SC_QZ2_TILE_NOT_COVERED_COUNT = 89 +SC_QZ3_TILE_NOT_COVERED_COUNT = 90 +SC_QZ0_QUAD_PER_TILE_H0 = 91 +SC_QZ0_QUAD_PER_TILE_H1 = 92 +SC_QZ0_QUAD_PER_TILE_H2 = 93 +SC_QZ0_QUAD_PER_TILE_H3 = 94 +SC_QZ0_QUAD_PER_TILE_H4 = 95 +SC_QZ0_QUAD_PER_TILE_H5 = 96 +SC_QZ0_QUAD_PER_TILE_H6 = 97 +SC_QZ0_QUAD_PER_TILE_H7 = 98 +SC_QZ0_QUAD_PER_TILE_H8 = 99 +SC_QZ0_QUAD_PER_TILE_H9 = 100 +SC_QZ0_QUAD_PER_TILE_H10 = 101 +SC_QZ0_QUAD_PER_TILE_H11 = 102 +SC_QZ0_QUAD_PER_TILE_H12 = 103 +SC_QZ0_QUAD_PER_TILE_H13 = 104 +SC_QZ0_QUAD_PER_TILE_H14 = 105 +SC_QZ0_QUAD_PER_TILE_H15 = 106 +SC_QZ0_QUAD_PER_TILE_H16 = 107 +SC_QZ1_QUAD_PER_TILE_H0 = 108 +SC_QZ1_QUAD_PER_TILE_H1 = 109 +SC_QZ1_QUAD_PER_TILE_H2 = 110 +SC_QZ1_QUAD_PER_TILE_H3 = 111 +SC_QZ1_QUAD_PER_TILE_H4 = 112 +SC_QZ1_QUAD_PER_TILE_H5 = 113 +SC_QZ1_QUAD_PER_TILE_H6 = 114 +SC_QZ1_QUAD_PER_TILE_H7 = 115 +SC_QZ1_QUAD_PER_TILE_H8 = 116 +SC_QZ1_QUAD_PER_TILE_H9 = 117 +SC_QZ1_QUAD_PER_TILE_H10 = 118 +SC_QZ1_QUAD_PER_TILE_H11 = 119 +SC_QZ1_QUAD_PER_TILE_H12 = 120 +SC_QZ1_QUAD_PER_TILE_H13 = 121 +SC_QZ1_QUAD_PER_TILE_H14 = 122 +SC_QZ1_QUAD_PER_TILE_H15 = 123 +SC_QZ1_QUAD_PER_TILE_H16 = 124 +SC_QZ2_QUAD_PER_TILE_H0 = 125 +SC_QZ2_QUAD_PER_TILE_H1 = 126 +SC_QZ2_QUAD_PER_TILE_H2 = 127 +SC_QZ2_QUAD_PER_TILE_H3 = 128 +SC_QZ2_QUAD_PER_TILE_H4 = 129 +SC_QZ2_QUAD_PER_TILE_H5 = 130 +SC_QZ2_QUAD_PER_TILE_H6 = 131 +SC_QZ2_QUAD_PER_TILE_H7 = 132 +SC_QZ2_QUAD_PER_TILE_H8 = 133 +SC_QZ2_QUAD_PER_TILE_H9 = 134 +SC_QZ2_QUAD_PER_TILE_H10 = 135 +SC_QZ2_QUAD_PER_TILE_H11 = 136 +SC_QZ2_QUAD_PER_TILE_H12 = 137 +SC_QZ2_QUAD_PER_TILE_H13 = 138 +SC_QZ2_QUAD_PER_TILE_H14 = 139 +SC_QZ2_QUAD_PER_TILE_H15 = 140 +SC_QZ2_QUAD_PER_TILE_H16 = 141 +SC_QZ3_QUAD_PER_TILE_H0 = 142 +SC_QZ3_QUAD_PER_TILE_H1 = 143 +SC_QZ3_QUAD_PER_TILE_H2 = 144 +SC_QZ3_QUAD_PER_TILE_H3 = 145 +SC_QZ3_QUAD_PER_TILE_H4 = 146 +SC_QZ3_QUAD_PER_TILE_H5 = 147 +SC_QZ3_QUAD_PER_TILE_H6 = 148 +SC_QZ3_QUAD_PER_TILE_H7 = 149 +SC_QZ3_QUAD_PER_TILE_H8 = 150 +SC_QZ3_QUAD_PER_TILE_H9 = 151 +SC_QZ3_QUAD_PER_TILE_H10 = 152 +SC_QZ3_QUAD_PER_TILE_H11 = 153 +SC_QZ3_QUAD_PER_TILE_H12 = 154 +SC_QZ3_QUAD_PER_TILE_H13 = 155 +SC_QZ3_QUAD_PER_TILE_H14 = 156 +SC_QZ3_QUAD_PER_TILE_H15 = 157 +SC_QZ3_QUAD_PER_TILE_H16 = 158 +SC_QZ0_QUAD_COUNT = 159 +SC_QZ1_QUAD_COUNT = 160 +SC_QZ2_QUAD_COUNT = 161 +SC_QZ3_QUAD_COUNT = 162 +SC_P0_HIZ_TILE_COUNT = 163 +SC_P1_HIZ_TILE_COUNT = 164 +SC_P2_HIZ_TILE_COUNT = 165 +SC_P3_HIZ_TILE_COUNT = 166 +SC_P0_HIZ_QUAD_PER_TILE_H0 = 167 +SC_P0_HIZ_QUAD_PER_TILE_H1 = 168 +SC_P0_HIZ_QUAD_PER_TILE_H2 = 169 +SC_P0_HIZ_QUAD_PER_TILE_H3 = 170 +SC_P0_HIZ_QUAD_PER_TILE_H4 = 171 +SC_P0_HIZ_QUAD_PER_TILE_H5 = 172 +SC_P0_HIZ_QUAD_PER_TILE_H6 = 173 +SC_P0_HIZ_QUAD_PER_TILE_H7 = 174 +SC_P0_HIZ_QUAD_PER_TILE_H8 = 175 +SC_P0_HIZ_QUAD_PER_TILE_H9 = 176 +SC_P0_HIZ_QUAD_PER_TILE_H10 = 177 +SC_P0_HIZ_QUAD_PER_TILE_H11 = 178 +SC_P0_HIZ_QUAD_PER_TILE_H12 = 179 +SC_P0_HIZ_QUAD_PER_TILE_H13 = 180 +SC_P0_HIZ_QUAD_PER_TILE_H14 = 181 +SC_P0_HIZ_QUAD_PER_TILE_H15 = 182 +SC_P0_HIZ_QUAD_PER_TILE_H16 = 183 +SC_P1_HIZ_QUAD_PER_TILE_H0 = 184 +SC_P1_HIZ_QUAD_PER_TILE_H1 = 185 +SC_P1_HIZ_QUAD_PER_TILE_H2 = 186 +SC_P1_HIZ_QUAD_PER_TILE_H3 = 187 +SC_P1_HIZ_QUAD_PER_TILE_H4 = 188 +SC_P1_HIZ_QUAD_PER_TILE_H5 = 189 +SC_P1_HIZ_QUAD_PER_TILE_H6 = 190 +SC_P1_HIZ_QUAD_PER_TILE_H7 = 191 +SC_P1_HIZ_QUAD_PER_TILE_H8 = 192 +SC_P1_HIZ_QUAD_PER_TILE_H9 = 193 +SC_P1_HIZ_QUAD_PER_TILE_H10 = 194 +SC_P1_HIZ_QUAD_PER_TILE_H11 = 195 +SC_P1_HIZ_QUAD_PER_TILE_H12 = 196 +SC_P1_HIZ_QUAD_PER_TILE_H13 = 197 +SC_P1_HIZ_QUAD_PER_TILE_H14 = 198 +SC_P1_HIZ_QUAD_PER_TILE_H15 = 199 +SC_P1_HIZ_QUAD_PER_TILE_H16 = 200 +SC_P2_HIZ_QUAD_PER_TILE_H0 = 201 +SC_P2_HIZ_QUAD_PER_TILE_H1 = 202 +SC_P2_HIZ_QUAD_PER_TILE_H2 = 203 +SC_P2_HIZ_QUAD_PER_TILE_H3 = 204 +SC_P2_HIZ_QUAD_PER_TILE_H4 = 205 +SC_P2_HIZ_QUAD_PER_TILE_H5 = 206 +SC_P2_HIZ_QUAD_PER_TILE_H6 = 207 +SC_P2_HIZ_QUAD_PER_TILE_H7 = 208 +SC_P2_HIZ_QUAD_PER_TILE_H8 = 209 +SC_P2_HIZ_QUAD_PER_TILE_H9 = 210 +SC_P2_HIZ_QUAD_PER_TILE_H10 = 211 +SC_P2_HIZ_QUAD_PER_TILE_H11 = 212 +SC_P2_HIZ_QUAD_PER_TILE_H12 = 213 +SC_P2_HIZ_QUAD_PER_TILE_H13 = 214 +SC_P2_HIZ_QUAD_PER_TILE_H14 = 215 +SC_P2_HIZ_QUAD_PER_TILE_H15 = 216 +SC_P2_HIZ_QUAD_PER_TILE_H16 = 217 +SC_P3_HIZ_QUAD_PER_TILE_H0 = 218 +SC_P3_HIZ_QUAD_PER_TILE_H1 = 219 +SC_P3_HIZ_QUAD_PER_TILE_H2 = 220 +SC_P3_HIZ_QUAD_PER_TILE_H3 = 221 +SC_P3_HIZ_QUAD_PER_TILE_H4 = 222 +SC_P3_HIZ_QUAD_PER_TILE_H5 = 223 +SC_P3_HIZ_QUAD_PER_TILE_H6 = 224 +SC_P3_HIZ_QUAD_PER_TILE_H7 = 225 +SC_P3_HIZ_QUAD_PER_TILE_H8 = 226 +SC_P3_HIZ_QUAD_PER_TILE_H9 = 227 +SC_P3_HIZ_QUAD_PER_TILE_H10 = 228 +SC_P3_HIZ_QUAD_PER_TILE_H11 = 229 +SC_P3_HIZ_QUAD_PER_TILE_H12 = 230 +SC_P3_HIZ_QUAD_PER_TILE_H13 = 231 +SC_P3_HIZ_QUAD_PER_TILE_H14 = 232 +SC_P3_HIZ_QUAD_PER_TILE_H15 = 233 +SC_P3_HIZ_QUAD_PER_TILE_H16 = 234 +SC_P0_HIZ_QUAD_COUNT = 235 +SC_P1_HIZ_QUAD_COUNT = 236 +SC_P2_HIZ_QUAD_COUNT = 237 +SC_P3_HIZ_QUAD_COUNT = 238 +SC_P0_DETAIL_QUAD_COUNT = 239 +SC_P1_DETAIL_QUAD_COUNT = 240 +SC_P2_DETAIL_QUAD_COUNT = 241 +SC_P3_DETAIL_QUAD_COUNT = 242 +SC_P0_DETAIL_QUAD_WITH_1_PIX = 243 +SC_P0_DETAIL_QUAD_WITH_2_PIX = 244 +SC_P0_DETAIL_QUAD_WITH_3_PIX = 245 +SC_P0_DETAIL_QUAD_WITH_4_PIX = 246 +SC_P1_DETAIL_QUAD_WITH_1_PIX = 247 +SC_P1_DETAIL_QUAD_WITH_2_PIX = 248 +SC_P1_DETAIL_QUAD_WITH_3_PIX = 249 +SC_P1_DETAIL_QUAD_WITH_4_PIX = 250 +SC_P2_DETAIL_QUAD_WITH_1_PIX = 251 +SC_P2_DETAIL_QUAD_WITH_2_PIX = 252 +SC_P2_DETAIL_QUAD_WITH_3_PIX = 253 +SC_P2_DETAIL_QUAD_WITH_4_PIX = 254 +SC_P3_DETAIL_QUAD_WITH_1_PIX = 255 +SC_P3_DETAIL_QUAD_WITH_2_PIX = 256 +SC_P3_DETAIL_QUAD_WITH_3_PIX = 257 +SC_P3_DETAIL_QUAD_WITH_4_PIX = 258 +SC_EARLYZ_QUAD_COUNT = 259 +SC_EARLYZ_QUAD_WITH_1_PIX = 260 +SC_EARLYZ_QUAD_WITH_2_PIX = 261 +SC_EARLYZ_QUAD_WITH_3_PIX = 262 +SC_EARLYZ_QUAD_WITH_4_PIX = 263 +SC_PKR_QUAD_PER_ROW_H1 = 264 +SC_PKR_QUAD_PER_ROW_H2 = 265 +SC_PKR_4X2_QUAD_SPLIT = 266 +SC_PKR_4X2_FILL_QUAD = 267 +SC_PKR_END_OF_VECTOR = 268 +SC_PKR_CONTROL_XFER = 269 +SC_PKR_DBHANG_FORCE_EOV = 270 +SC_REG_SCLK_BUSY = 271 +SC_GRP0_DYN_SCLK_BUSY = 272 +SC_GRP1_DYN_SCLK_BUSY = 273 +SC_GRP2_DYN_SCLK_BUSY = 274 +SC_GRP3_DYN_SCLK_BUSY = 275 +SC_GRP4_DYN_SCLK_BUSY = 276 +SC_PA0_SC_DATA_FIFO_RD = 277 +SC_PA0_SC_DATA_FIFO_WE = 278 +SC_PA1_SC_DATA_FIFO_RD = 279 +SC_PA1_SC_DATA_FIFO_WE = 280 +SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 281 +SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 282 +SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 283 +SC_PS_ARB_STALLED_FROM_BELOW = 284 +SC_PS_ARB_STARVED_FROM_ABOVE = 285 +SC_PS_ARB_SC_BUSY = 286 +SC_PS_ARB_PA_SC_BUSY = 287 +SC_PA2_SC_DATA_FIFO_RD = 288 +SC_PA2_SC_DATA_FIFO_WE = 289 +SC_PA3_SC_DATA_FIFO_RD = 290 +SC_PA3_SC_DATA_FIFO_WE = 291 +SC_PA_SC_DEALLOC_0_0_WE = 292 +SC_PA_SC_DEALLOC_0_1_WE = 293 +SC_PA_SC_DEALLOC_1_0_WE = 294 +SC_PA_SC_DEALLOC_1_1_WE = 295 +SC_PA_SC_DEALLOC_2_0_WE = 296 +SC_PA_SC_DEALLOC_2_1_WE = 297 +SC_PA_SC_DEALLOC_3_0_WE = 298 +SC_PA_SC_DEALLOC_3_1_WE = 299 +SC_PA0_SC_EOP_WE = 300 +SC_PA0_SC_EOPG_WE = 301 +SC_PA0_SC_EVENT_WE = 302 +SC_PA1_SC_EOP_WE = 303 +SC_PA1_SC_EOPG_WE = 304 +SC_PA1_SC_EVENT_WE = 305 +SC_PA2_SC_EOP_WE = 306 +SC_PA2_SC_EOPG_WE = 307 +SC_PA2_SC_EVENT_WE = 308 +SC_PA3_SC_EOP_WE = 309 +SC_PA3_SC_EOPG_WE = 310 +SC_PA3_SC_EVENT_WE = 311 +SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 312 +SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 313 +SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 314 +SC_PS_ARB_EOP_POP_SYNC_POP = 315 +SC_PS_ARB_EVENT_SYNC_POP = 316 +SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 317 +SC_PA0_SC_FPOV_WE = 318 +SC_PA1_SC_FPOV_WE = 319 +SC_PA2_SC_FPOV_WE = 320 +SC_PA3_SC_FPOV_WE = 321 +SC_PA0_SC_LPOV_WE = 322 +SC_PA1_SC_LPOV_WE = 323 +SC_PA2_SC_LPOV_WE = 324 +SC_PA3_SC_LPOV_WE = 325 +SC_SC_SPI_DEALLOC_0_0 = 326 +SC_SC_SPI_DEALLOC_0_1 = 327 +SC_SC_SPI_DEALLOC_0_2 = 328 +SC_SC_SPI_DEALLOC_1_0 = 329 +SC_SC_SPI_DEALLOC_1_1 = 330 +SC_SC_SPI_DEALLOC_1_2 = 331 +SC_SC_SPI_DEALLOC_2_0 = 332 +SC_SC_SPI_DEALLOC_2_1 = 333 +SC_SC_SPI_DEALLOC_2_2 = 334 +SC_SC_SPI_DEALLOC_3_0 = 335 +SC_SC_SPI_DEALLOC_3_1 = 336 +SC_SC_SPI_DEALLOC_3_2 = 337 +SC_SC_SPI_FPOV_0 = 338 +SC_SC_SPI_FPOV_1 = 339 +SC_SC_SPI_FPOV_2 = 340 +SC_SC_SPI_FPOV_3 = 341 +SC_SC_SPI_EVENT = 342 +SC_PS_TS_EVENT_FIFO_PUSH = 343 +SC_PS_TS_EVENT_FIFO_POP = 344 +SC_PS_CTX_DONE_FIFO_PUSH = 345 +SC_PS_CTX_DONE_FIFO_POP = 346 +SC_MULTICYCLE_BUBBLE_FREEZE = 347 +SC_EOP_SYNC_WINDOW = 348 +SC_PA0_SC_NULL_WE = 349 +SC_PA0_SC_NULL_DEALLOC_WE = 350 +SC_PA0_SC_DATA_FIFO_EOPG_RD = 351 +SC_PA0_SC_DATA_FIFO_EOP_RD = 352 +SC_PA0_SC_DEALLOC_0_RD = 353 +SC_PA0_SC_DEALLOC_1_RD = 354 +SC_PA1_SC_DATA_FIFO_EOPG_RD = 355 +SC_PA1_SC_DATA_FIFO_EOP_RD = 356 +SC_PA1_SC_DEALLOC_0_RD = 357 +SC_PA1_SC_DEALLOC_1_RD = 358 +SC_PA1_SC_NULL_WE = 359 +SC_PA1_SC_NULL_DEALLOC_WE = 360 +SC_PA2_SC_DATA_FIFO_EOPG_RD = 361 +SC_PA2_SC_DATA_FIFO_EOP_RD = 362 +SC_PA2_SC_DEALLOC_0_RD = 363 +SC_PA2_SC_DEALLOC_1_RD = 364 +SC_PA2_SC_NULL_WE = 365 +SC_PA2_SC_NULL_DEALLOC_WE = 366 +SC_PA3_SC_DATA_FIFO_EOPG_RD = 367 +SC_PA3_SC_DATA_FIFO_EOP_RD = 368 +SC_PA3_SC_DEALLOC_0_RD = 369 +SC_PA3_SC_DEALLOC_1_RD = 370 +SC_PA3_SC_NULL_WE = 371 +SC_PA3_SC_NULL_DEALLOC_WE = 372 +SC_PS_PA0_SC_FIFO_EMPTY = 373 +SC_PS_PA0_SC_FIFO_FULL = 374 +SC_RESERVED_0 = 375 +SC_PS_PA1_SC_FIFO_EMPTY = 376 +SC_PS_PA1_SC_FIFO_FULL = 377 +SC_RESERVED_1 = 378 +SC_PS_PA2_SC_FIFO_EMPTY = 379 +SC_PS_PA2_SC_FIFO_FULL = 380 +SC_RESERVED_2 = 381 +SC_PS_PA3_SC_FIFO_EMPTY = 382 +SC_PS_PA3_SC_FIFO_FULL = 383 +SC_RESERVED_3 = 384 +SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 385 +SC_BUSY_CNT_NOT_ZERO = 386 +SC_BM_BUSY = 387 +SC_BACKEND_BUSY = 388 +SC_SCF_SCB_INTERFACE_BUSY = 389 +SC_SCB_BUSY = 390 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 391 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 392 +SC_PBB_BIN_HIST_NUM_PRIMS = 393 +SC_PBB_BATCH_HIST_NUM_PRIMS = 394 +SC_PBB_BIN_HIST_NUM_CONTEXTS = 395 +SC_PBB_BATCH_HIST_NUM_CONTEXTS = 396 +SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 397 +SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 398 +SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 399 +SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 400 +SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 401 +SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 402 +SC_PBB_BUSY = 403 +SC_PBB_BUSY_AND_NO_SENDS = 404 +SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 405 +SC_PBB_NUM_BINS = 406 +SC_PBB_END_OF_BIN = 407 +SC_PBB_END_OF_BATCH = 408 +SC_PBB_PRIMBIN_PROCESSED = 409 +SC_PBB_PRIM_ADDED_TO_BATCH = 410 +SC_PBB_NONBINNED_PRIM = 411 +SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 412 +SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 413 +SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 414 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 415 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 416 +SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 417 +SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 418 +SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 419 +SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 420 +SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 421 +SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 422 +SC_POPS_INTRA_WAVE_OVERLAPS = 423 +SC_POPS_FORCE_EOV = 424 +SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 425 +SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 426 +SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 427 +SC_FULL_FULL_QUAD = 428 +SC_FULL_HALF_QUAD = 429 +SC_FULL_QTR_QUAD = 430 +SC_HALF_FULL_QUAD = 431 +SC_HALF_HALF_QUAD = 432 +SC_HALF_QTR_QUAD = 433 +SC_QTR_FULL_QUAD = 434 +SC_QTR_HALF_QUAD = 435 +SC_QTR_QTR_QUAD = 436 +SC_GRP5_DYN_SCLK_BUSY = 437 +SC_GRP6_DYN_SCLK_BUSY = 438 +SC_GRP7_DYN_SCLK_BUSY = 439 +SC_GRP8_DYN_SCLK_BUSY = 440 +SC_GRP9_DYN_SCLK_BUSY = 441 +SC_PS_TO_BE_SCLK_GATE_STALL = 442 +SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 443 +SC_PK_BUSY = 444 +SC_PK_MAX_DEALLOC_FORCE_EOV = 445 +SC_PK_DEALLOC_WAVE_BREAK = 446 +SC_SPI_SEND = 447 +SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 448 +SC_SPI_CREDIT_AT_MAX = 449 +SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 450 +SC_BCI_SEND = 451 +SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 452 +SC_BCI_CREDIT_AT_MAX = 453 +SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 454 +SC_SPIBC_FULL_FREEZE = 455 +SC_PW_BM_PASS_EMPTY_PRIM = 456 +SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 457 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 458 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 459 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 460 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 461 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 462 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 463 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 464 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 465 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 466 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 467 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 468 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 469 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 470 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 471 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 472 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 473 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 474 +SC_DB0_TILE_INTERFACE_BUSY = 475 +SC_DB0_TILE_INTERFACE_SEND = 476 +SC_DB0_TILE_INTERFACE_SEND_EVENT = 477 +SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 478 +SC_DB0_TILE_INTERFACE_SEND_SOP = 479 +SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 480 +SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 481 +SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 482 +SC_DB1_TILE_INTERFACE_BUSY = 483 +SC_DB1_TILE_INTERFACE_SEND = 484 +SC_DB1_TILE_INTERFACE_SEND_EVENT = 485 +SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 486 +SC_DB1_TILE_INTERFACE_SEND_SOP = 487 +SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 488 +SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 489 +SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 490 +SC_BACKEND_PRIM_FIFO_FULL = 491 +SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 492 +SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 493 +SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 494 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 495 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 496 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 497 +SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 498 +SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 499 +SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 500 +SC_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SePairXsel' +SePairXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 +SePairXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SePairYsel' +SePairYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 +SePairYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SePairMap' +SePairMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', + 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', + 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', + 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', +} +RASTER_CONFIG_SE_PAIR_MAP_0 = 0 +RASTER_CONFIG_SE_PAIR_MAP_1 = 1 +RASTER_CONFIG_SE_PAIR_MAP_2 = 2 +RASTER_CONFIG_SE_PAIR_MAP_3 = 3 +SePairMap = ctypes.c_uint32 # enum + +# values for enumeration 'SeXsel' +SeXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 +SeXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeYsel' +SeYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 +SeYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeMap' +SeMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_MAP_0', + 1: 'RASTER_CONFIG_SE_MAP_1', + 2: 'RASTER_CONFIG_SE_MAP_2', + 3: 'RASTER_CONFIG_SE_MAP_3', +} +RASTER_CONFIG_SE_MAP_0 = 0 +RASTER_CONFIG_SE_MAP_1 = 1 +RASTER_CONFIG_SE_MAP_2 = 2 +RASTER_CONFIG_SE_MAP_3 = 3 +SeMap = ctypes.c_uint32 # enum + +# values for enumeration 'ScXsel' +ScXsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 +ScXsel = ctypes.c_uint32 # enum + +# values for enumeration 'ScYsel' +ScYsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 +ScYsel = ctypes.c_uint32 # enum + +# values for enumeration 'ScMap' +ScMap__enumvalues = { + 0: 'RASTER_CONFIG_SC_MAP_0', + 1: 'RASTER_CONFIG_SC_MAP_1', + 2: 'RASTER_CONFIG_SC_MAP_2', + 3: 'RASTER_CONFIG_SC_MAP_3', +} +RASTER_CONFIG_SC_MAP_0 = 0 +RASTER_CONFIG_SC_MAP_1 = 1 +RASTER_CONFIG_SC_MAP_2 = 2 +RASTER_CONFIG_SC_MAP_3 = 3 +ScMap = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel2' +PkrXsel2__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL2_0', + 1: 'RASTER_CONFIG_PKR_XSEL2_1', + 2: 'RASTER_CONFIG_PKR_XSEL2_2', + 3: 'RASTER_CONFIG_PKR_XSEL2_3', +} +RASTER_CONFIG_PKR_XSEL2_0 = 0 +RASTER_CONFIG_PKR_XSEL2_1 = 1 +RASTER_CONFIG_PKR_XSEL2_2 = 2 +RASTER_CONFIG_PKR_XSEL2_3 = 3 +PkrXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel' +PkrXsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL_0', + 1: 'RASTER_CONFIG_PKR_XSEL_1', + 2: 'RASTER_CONFIG_PKR_XSEL_2', + 3: 'RASTER_CONFIG_PKR_XSEL_3', +} +RASTER_CONFIG_PKR_XSEL_0 = 0 +RASTER_CONFIG_PKR_XSEL_1 = 1 +RASTER_CONFIG_PKR_XSEL_2 = 2 +RASTER_CONFIG_PKR_XSEL_3 = 3 +PkrXsel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrYsel' +PkrYsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_YSEL_0', + 1: 'RASTER_CONFIG_PKR_YSEL_1', + 2: 'RASTER_CONFIG_PKR_YSEL_2', + 3: 'RASTER_CONFIG_PKR_YSEL_3', +} +RASTER_CONFIG_PKR_YSEL_0 = 0 +RASTER_CONFIG_PKR_YSEL_1 = 1 +RASTER_CONFIG_PKR_YSEL_2 = 2 +RASTER_CONFIG_PKR_YSEL_3 = 3 +PkrYsel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrMap' +PkrMap__enumvalues = { + 0: 'RASTER_CONFIG_PKR_MAP_0', + 1: 'RASTER_CONFIG_PKR_MAP_1', + 2: 'RASTER_CONFIG_PKR_MAP_2', + 3: 'RASTER_CONFIG_PKR_MAP_3', +} +RASTER_CONFIG_PKR_MAP_0 = 0 +RASTER_CONFIG_PKR_MAP_1 = 1 +RASTER_CONFIG_PKR_MAP_2 = 2 +RASTER_CONFIG_PKR_MAP_3 = 3 +PkrMap = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel' +RbXsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL_0', + 1: 'RASTER_CONFIG_RB_XSEL_1', +} +RASTER_CONFIG_RB_XSEL_0 = 0 +RASTER_CONFIG_RB_XSEL_1 = 1 +RbXsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbYsel' +RbYsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_YSEL_0', + 1: 'RASTER_CONFIG_RB_YSEL_1', +} +RASTER_CONFIG_RB_YSEL_0 = 0 +RASTER_CONFIG_RB_YSEL_1 = 1 +RbYsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel2' +RbXsel2__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL2_0', + 1: 'RASTER_CONFIG_RB_XSEL2_1', + 2: 'RASTER_CONFIG_RB_XSEL2_2', + 3: 'RASTER_CONFIG_RB_XSEL2_3', +} +RASTER_CONFIG_RB_XSEL2_0 = 0 +RASTER_CONFIG_RB_XSEL2_1 = 1 +RASTER_CONFIG_RB_XSEL2_2 = 2 +RASTER_CONFIG_RB_XSEL2_3 = 3 +RbXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'RbMap' +RbMap__enumvalues = { + 0: 'RASTER_CONFIG_RB_MAP_0', + 1: 'RASTER_CONFIG_RB_MAP_1', + 2: 'RASTER_CONFIG_RB_MAP_2', + 3: 'RASTER_CONFIG_RB_MAP_3', +} +RASTER_CONFIG_RB_MAP_0 = 0 +RASTER_CONFIG_RB_MAP_1 = 1 +RASTER_CONFIG_RB_MAP_2 = 2 +RASTER_CONFIG_RB_MAP_3 = 3 +RbMap = ctypes.c_uint32 # enum + +# values for enumeration 'BinningMode' +BinningMode__enumvalues = { + 0: 'BINNING_ALLOWED', + 1: 'FORCE_BINNING_ON', + 2: 'DISABLE_BINNING_USE_NEW_SC', + 3: 'DISABLE_BINNING_USE_LEGACY_SC', +} +BINNING_ALLOWED = 0 +FORCE_BINNING_ON = 1 +DISABLE_BINNING_USE_NEW_SC = 2 +DISABLE_BINNING_USE_LEGACY_SC = 3 +BinningMode = ctypes.c_uint32 # enum + +# values for enumeration 'BinSizeExtend' +BinSizeExtend__enumvalues = { + 0: 'BIN_SIZE_32_PIXELS', + 1: 'BIN_SIZE_64_PIXELS', + 2: 'BIN_SIZE_128_PIXELS', + 3: 'BIN_SIZE_256_PIXELS', + 4: 'BIN_SIZE_512_PIXELS', +} +BIN_SIZE_32_PIXELS = 0 +BIN_SIZE_64_PIXELS = 1 +BIN_SIZE_128_PIXELS = 2 +BIN_SIZE_256_PIXELS = 3 +BIN_SIZE_512_PIXELS = 4 +BinSizeExtend = ctypes.c_uint32 # enum + +# values for enumeration 'BinMapMode' +BinMapMode__enumvalues = { + 0: 'BIN_MAP_MODE_NONE', + 1: 'BIN_MAP_MODE_RTA_INDEX', + 2: 'BIN_MAP_MODE_POPS', +} +BIN_MAP_MODE_NONE = 0 +BIN_MAP_MODE_RTA_INDEX = 1 +BIN_MAP_MODE_POPS = 2 +BinMapMode = ctypes.c_uint32 # enum + +# values for enumeration 'BinEventCntl' +BinEventCntl__enumvalues = { + 0: 'BINNER_BREAK_BATCH', + 1: 'BINNER_PIPELINE', + 2: 'BINNER_DROP', + 3: 'BINNER_DROP_ASSERT', +} +BINNER_BREAK_BATCH = 0 +BINNER_PIPELINE = 1 +BINNER_DROP = 2 +BINNER_DROP_ASSERT = 3 +BinEventCntl = ctypes.c_uint32 # enum + +# values for enumeration 'CovToShaderSel' +CovToShaderSel__enumvalues = { + 0: 'INPUT_COVERAGE', + 1: 'INPUT_INNER_COVERAGE', + 2: 'INPUT_DEPTH_COVERAGE', + 3: 'RAW', +} +INPUT_COVERAGE = 0 +INPUT_INNER_COVERAGE = 1 +INPUT_DEPTH_COVERAGE = 2 +RAW = 3 +CovToShaderSel = ctypes.c_uint32 # enum + +# values for enumeration 'ScUncertaintyRegionMode' +ScUncertaintyRegionMode__enumvalues = { + 0: 'SC_HALF_LSB', + 1: 'SC_LSB_ONE_SIDED', + 2: 'SC_LSB_TWO_SIDED', +} +SC_HALF_LSB = 0 +SC_LSB_ONE_SIDED = 1 +SC_LSB_TWO_SIDED = 2 +ScUncertaintyRegionMode = ctypes.c_uint32 # enum + +# values for enumeration 'RMIPerfSel' +RMIPerfSel__enumvalues = { + 0: 'RMI_PERF_SEL_NONE', + 1: 'RMI_PERF_SEL_BUSY', + 2: 'RMI_PERF_SEL_REG_CLK_VLD', + 3: 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', + 4: 'RMI_PERF_SEL_DYN_CLK_RB_VLD', + 5: 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', + 6: 'RMI_PERF_SEL_PERF_WINDOW', + 7: 'RMI_PERF_SEL_EVENT_SEND', + 8: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0', + 9: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1', + 10: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2', + 11: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3', + 12: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4', + 13: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5', + 14: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6', + 15: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7', + 16: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8', + 17: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9', + 18: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10', + 19: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11', + 20: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12', + 21: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13', + 22: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14', + 23: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15', + 24: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL', + 25: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0', + 26: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1', + 27: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2', + 28: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3', + 29: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4', + 30: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5', + 31: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6', + 32: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7', + 33: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8', + 34: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9', + 35: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10', + 36: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11', + 37: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12', + 38: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13', + 39: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14', + 40: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15', + 41: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL', + 42: 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS', + 43: 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS', + 44: 'RMI_PERF_SEL_UTCL1_TRANSLATION_HIT', + 45: 'RMI_PERF_SEL_UTCL1_REQUEST', + 46: 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 47: 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 48: 'RMI_PERF_SEL_UTCL1_LFIFO_FULL', + 49: 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 50: 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 51: 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 52: 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL', + 53: 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS', + 54: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', + 55: 'RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY', + 56: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', + 57: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', + 58: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', + 59: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', + 60: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', + 61: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', + 62: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', + 63: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', + 64: 'RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID', + 65: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', + 66: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', + 67: 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', + 68: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', + 69: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', + 70: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', + 71: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', + 72: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', + 73: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', + 74: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', + 75: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', + 76: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', + 77: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', + 78: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', + 79: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', + 80: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', + 81: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', + 82: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', + 83: 'RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY', + 84: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', + 85: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', + 86: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', + 87: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', + 88: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', + 89: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', + 90: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', + 91: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', + 92: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', + 93: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', + 94: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', + 95: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', + 96: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', + 97: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', + 98: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', + 99: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', + 100: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', + 101: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', + 102: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', + 103: 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', + 104: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', + 105: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', + 106: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', + 107: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', + 108: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', + 109: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', + 110: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', + 111: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', + 112: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', + 113: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', + 114: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', + 115: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', + 116: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', + 117: 'RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX', + 118: 'RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY', + 119: 'RMI_PERF_SEL_RB_RMI_WR_IDLE', + 120: 'RMI_PERF_SEL_RB_RMI_WR_STARVE', + 121: 'RMI_PERF_SEL_RB_RMI_WR_STALL', + 122: 'RMI_PERF_SEL_RB_RMI_WR_BUSY', + 123: 'RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY', + 124: 'RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX', + 125: 'RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY', + 126: 'RMI_PERF_SEL_RB_RMI_RD_IDLE', + 127: 'RMI_PERF_SEL_RB_RMI_RD_STARVE', + 128: 'RMI_PERF_SEL_RB_RMI_RD_STALL', + 129: 'RMI_PERF_SEL_RB_RMI_RD_BUSY', + 130: 'RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY', + 131: 'RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID', + 132: 'RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID', + 133: 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', + 134: 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', + 135: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', + 136: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', + 137: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', + 138: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', + 139: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', + 140: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', + 141: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', + 142: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', + 143: 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', + 144: 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', + 145: 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', + 146: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', + 147: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', + 148: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', + 149: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', + 150: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', + 151: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', + 152: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', + 153: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', + 154: 'RMI_PERF_SEL_RMI_TC_STALL_RDREQ', + 155: 'RMI_PERF_SEL_RMI_TC_STALL_WRREQ', + 156: 'RMI_PERF_SEL_RMI_TC_STALL_ALLREQ', + 157: 'RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND', + 158: 'RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND', + 159: 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', + 160: 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', + 161: 'RMI_PERF_SEL_UTCL1_BUSY', + 162: 'RMI_PERF_SEL_RMI_UTC_REQ', + 163: 'RMI_PERF_SEL_RMI_UTC_BUSY', + 164: 'RMI_PERF_SEL_UTCL1_UTCL2_REQ', + 165: 'RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2', + 166: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY', + 167: 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT', + 168: 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT', + 169: 'RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS', + 170: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT', + 171: 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED', + 172: 'RMI_PERF_SEL_LAT_FIFO_NUM_USED', + 173: 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ', + 174: 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ', + 175: 'RMI_PERF_SEL_XNACK_FIFO_FULL', + 176: 'RMI_PERF_SEL_XNACK_FIFO_BUSY', + 177: 'RMI_PERF_SEL_LAT_FIFO_FULL', + 178: 'RMI_PERF_SEL_SKID_FIFO_DEPTH', + 179: 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', + 180: 'RMI_PERF_SEL_PRT_FIFO_NUM_USED', + 181: 'RMI_PERF_SEL_PRT_FIFO_REQ', + 182: 'RMI_PERF_SEL_PRT_FIFO_BUSY', + 183: 'RMI_PERF_SEL_TCIW_REQ', + 184: 'RMI_PERF_SEL_TCIW_BUSY', + 185: 'RMI_PERF_SEL_SKID_FIFO_REQ', + 186: 'RMI_PERF_SEL_SKID_FIFO_BUSY', + 187: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0', + 188: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1', + 189: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2', + 190: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3', + 191: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR', + 192: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR', + 193: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB', + 194: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB', + 195: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', + 196: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', + 197: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', + 198: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', + 199: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR', + 200: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR', + 201: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB', + 202: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB', + 203: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR', + 204: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR', + 205: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB', + 206: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB', + 207: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR', + 208: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR', + 209: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB', + 210: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB', + 211: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR', + 212: 'RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC', + 213: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR', + 214: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB', + 215: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB', + 216: 'RMI_PERF_SEL_UTC_POP_RTS_RTR', + 217: 'RMI_PERF_SEL_UTC_POP_RTSB_RTR', + 218: 'RMI_PERF_SEL_UTC_POP_RTS_RTRB', + 219: 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', + 220: 'RMI_PERF_SEL_POP_XNACK_RTS_RTR', + 221: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR', + 222: 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB', + 223: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB', + 224: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR', + 225: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR', + 226: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', + 227: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB', + 228: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR', + 229: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR', + 230: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB', + 231: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB', + 232: 'RMI_PERF_SEL_SKID_FIFO_IN_RTS', + 233: 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB', + 234: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS', + 235: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', + 236: 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR', + 237: 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR', + 238: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR', + 239: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR', + 240: 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR', + 241: 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR', + 242: 'RMI_PERF_SEL_REORDER_FIFO_REQ', + 243: 'RMI_PERF_SEL_REORDER_FIFO_BUSY', + 244: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', + 245: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', + 246: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', + 247: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', + 248: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', + 249: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', + 250: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', + 251: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', + 252: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', + 253: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0', + 254: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1', + 255: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2', + 256: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3', +} +RMI_PERF_SEL_NONE = 0 +RMI_PERF_SEL_BUSY = 1 +RMI_PERF_SEL_REG_CLK_VLD = 2 +RMI_PERF_SEL_DYN_CLK_CMN_VLD = 3 +RMI_PERF_SEL_DYN_CLK_RB_VLD = 4 +RMI_PERF_SEL_DYN_CLK_PERF_VLD = 5 +RMI_PERF_SEL_PERF_WINDOW = 6 +RMI_PERF_SEL_EVENT_SEND = 7 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 8 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 9 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 10 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 11 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 12 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 13 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 14 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 15 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 16 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 17 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 18 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 19 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 20 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 21 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 22 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 23 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 24 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 25 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 26 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 27 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 28 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 29 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 30 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 31 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 32 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 33 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 34 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 35 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 36 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 37 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 38 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 39 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 40 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 41 +RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 42 +RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 43 +RMI_PERF_SEL_UTCL1_TRANSLATION_HIT = 44 +RMI_PERF_SEL_UTCL1_REQUEST = 45 +RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 46 +RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 47 +RMI_PERF_SEL_UTCL1_LFIFO_FULL = 48 +RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 49 +RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 50 +RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 51 +RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 52 +RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 53 +RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 54 +RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY = 55 +RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 56 +RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 57 +RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 58 +RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 59 +RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 60 +RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 61 +RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 62 +RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 63 +RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID = 64 +RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 65 +RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 66 +RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 67 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 68 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 69 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 70 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 71 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 72 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 73 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 74 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 75 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 76 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 77 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 78 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 79 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 80 +RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 81 +RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 82 +RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY = 83 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 84 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 85 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 86 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 87 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 88 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 89 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 90 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 91 +RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 92 +RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 93 +RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 94 +RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 95 +RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 96 +RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 97 +RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 98 +RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 99 +RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 100 +RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 101 +RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 102 +RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 103 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 104 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 105 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 106 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 107 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 108 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 109 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 110 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 111 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 112 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 113 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 114 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 115 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 116 +RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX = 117 +RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY = 118 +RMI_PERF_SEL_RB_RMI_WR_IDLE = 119 +RMI_PERF_SEL_RB_RMI_WR_STARVE = 120 +RMI_PERF_SEL_RB_RMI_WR_STALL = 121 +RMI_PERF_SEL_RB_RMI_WR_BUSY = 122 +RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY = 123 +RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX = 124 +RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY = 125 +RMI_PERF_SEL_RB_RMI_RD_IDLE = 126 +RMI_PERF_SEL_RB_RMI_RD_STARVE = 127 +RMI_PERF_SEL_RB_RMI_RD_STALL = 128 +RMI_PERF_SEL_RB_RMI_RD_BUSY = 129 +RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY = 130 +RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID = 131 +RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID = 132 +RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 133 +RMI_PERF_SEL_RMI_TC_REQ_BUSY = 134 +RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 135 +RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 136 +RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 137 +RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 138 +RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 139 +RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 140 +RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 141 +RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 142 +RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 143 +RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 144 +RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 145 +RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 146 +RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 147 +RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 148 +RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 149 +RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 150 +RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 151 +RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 152 +RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 153 +RMI_PERF_SEL_RMI_TC_STALL_RDREQ = 154 +RMI_PERF_SEL_RMI_TC_STALL_WRREQ = 155 +RMI_PERF_SEL_RMI_TC_STALL_ALLREQ = 156 +RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND = 157 +RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND = 158 +RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 159 +RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 160 +RMI_PERF_SEL_UTCL1_BUSY = 161 +RMI_PERF_SEL_RMI_UTC_REQ = 162 +RMI_PERF_SEL_RMI_UTC_BUSY = 163 +RMI_PERF_SEL_UTCL1_UTCL2_REQ = 164 +RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2 = 165 +RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 166 +RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 167 +RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 168 +RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS = 169 +RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 170 +RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 171 +RMI_PERF_SEL_LAT_FIFO_NUM_USED = 172 +RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 173 +RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 174 +RMI_PERF_SEL_XNACK_FIFO_FULL = 175 +RMI_PERF_SEL_XNACK_FIFO_BUSY = 176 +RMI_PERF_SEL_LAT_FIFO_FULL = 177 +RMI_PERF_SEL_SKID_FIFO_DEPTH = 178 +RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 179 +RMI_PERF_SEL_PRT_FIFO_NUM_USED = 180 +RMI_PERF_SEL_PRT_FIFO_REQ = 181 +RMI_PERF_SEL_PRT_FIFO_BUSY = 182 +RMI_PERF_SEL_TCIW_REQ = 183 +RMI_PERF_SEL_TCIW_BUSY = 184 +RMI_PERF_SEL_SKID_FIFO_REQ = 185 +RMI_PERF_SEL_SKID_FIFO_BUSY = 186 +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 187 +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 188 +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 189 +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 190 +RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 191 +RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 192 +RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 193 +RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 194 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 195 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 196 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 197 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 198 +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 199 +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 200 +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 201 +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 202 +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 203 +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 204 +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 205 +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 206 +RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 207 +RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 208 +RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 209 +RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 210 +RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 211 +RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC = 212 +RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 213 +RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 214 +RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 215 +RMI_PERF_SEL_UTC_POP_RTS_RTR = 216 +RMI_PERF_SEL_UTC_POP_RTSB_RTR = 217 +RMI_PERF_SEL_UTC_POP_RTS_RTRB = 218 +RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 219 +RMI_PERF_SEL_POP_XNACK_RTS_RTR = 220 +RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 221 +RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 222 +RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 223 +RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 224 +RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 225 +RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 226 +RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 227 +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 228 +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 229 +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 230 +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 231 +RMI_PERF_SEL_SKID_FIFO_IN_RTS = 232 +RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 233 +RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 234 +RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 235 +RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 236 +RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 237 +RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 238 +RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 239 +RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 240 +RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 241 +RMI_PERF_SEL_REORDER_FIFO_REQ = 242 +RMI_PERF_SEL_REORDER_FIFO_BUSY = 243 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 244 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 245 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 246 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 247 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 248 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 249 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 250 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 251 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 252 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 253 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 254 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 255 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 256 +RMIPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'GCRPerfSel' +GCRPerfSel__enumvalues = { + 0: 'GCR_PERF_SEL_NONE', + 1: 'GCR_PERF_SEL_SDMA0_ALL_REQ', + 2: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', + 3: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', + 4: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', + 5: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', + 6: 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', + 7: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', + 8: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', + 9: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', + 10: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', + 11: 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', + 12: 'GCR_PERF_SEL_SDMA0_METADATA_REQ', + 13: 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', + 14: 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', + 15: 'GCR_PERF_SEL_SDMA0_TCP_REQ', + 16: 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', + 17: 'GCR_PERF_SEL_SDMA1_ALL_REQ', + 18: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', + 19: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', + 20: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', + 21: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', + 22: 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', + 23: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', + 24: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', + 25: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', + 26: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', + 27: 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', + 28: 'GCR_PERF_SEL_SDMA1_METADATA_REQ', + 29: 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', + 30: 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', + 31: 'GCR_PERF_SEL_SDMA1_TCP_REQ', + 32: 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', + 33: 'GCR_PERF_SEL_CPG_ALL_REQ', + 34: 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', + 35: 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', + 36: 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', + 37: 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', + 38: 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', + 39: 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', + 40: 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', + 41: 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', + 42: 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', + 43: 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', + 44: 'GCR_PERF_SEL_CPG_METADATA_REQ', + 45: 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', + 46: 'GCR_PERF_SEL_CPG_SQC_INST_REQ', + 47: 'GCR_PERF_SEL_CPG_TCP_REQ', + 48: 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', + 49: 'GCR_PERF_SEL_CPC_ALL_REQ', + 50: 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', + 51: 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', + 52: 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', + 53: 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', + 54: 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', + 55: 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', + 56: 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', + 57: 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', + 58: 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', + 59: 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', + 60: 'GCR_PERF_SEL_CPC_METADATA_REQ', + 61: 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', + 62: 'GCR_PERF_SEL_CPC_SQC_INST_REQ', + 63: 'GCR_PERF_SEL_CPC_TCP_REQ', + 64: 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', + 65: 'GCR_PERF_SEL_CPF_ALL_REQ', + 66: 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', + 67: 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', + 68: 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', + 69: 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', + 70: 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', + 71: 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', + 72: 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', + 73: 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', + 74: 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', + 75: 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', + 76: 'GCR_PERF_SEL_CPF_METADATA_REQ', + 77: 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', + 78: 'GCR_PERF_SEL_CPF_SQC_INST_REQ', + 79: 'GCR_PERF_SEL_CPF_TCP_REQ', + 80: 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', + 81: 'GCR_PERF_SEL_VIRT_REQ', + 82: 'GCR_PERF_SEL_PHY_REQ', + 83: 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', + 84: 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', + 85: 'GCR_PERF_SEL_ALL_REQ', + 86: 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', + 87: 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', + 88: 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', + 89: 'GCR_PERF_SEL_UTCL2_REQ', + 90: 'GCR_PERF_SEL_UTCL2_RET', + 91: 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', + 92: 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', + 93: 'GCR_PERF_SEL_UTCL2_FILTERED_RET', +} +GCR_PERF_SEL_NONE = 0 +GCR_PERF_SEL_SDMA0_ALL_REQ = 1 +GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 2 +GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 3 +GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 4 +GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 5 +GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 6 +GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 7 +GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 8 +GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 9 +GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 10 +GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 11 +GCR_PERF_SEL_SDMA0_METADATA_REQ = 12 +GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 13 +GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 14 +GCR_PERF_SEL_SDMA0_TCP_REQ = 15 +GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 16 +GCR_PERF_SEL_SDMA1_ALL_REQ = 17 +GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 18 +GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 19 +GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 20 +GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 21 +GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 22 +GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 23 +GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 24 +GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 25 +GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 26 +GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 27 +GCR_PERF_SEL_SDMA1_METADATA_REQ = 28 +GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 29 +GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 30 +GCR_PERF_SEL_SDMA1_TCP_REQ = 31 +GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 32 +GCR_PERF_SEL_CPG_ALL_REQ = 33 +GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 34 +GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 35 +GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 36 +GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 37 +GCR_PERF_SEL_CPG_GL2_ALL_REQ = 38 +GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 39 +GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 40 +GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 41 +GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 42 +GCR_PERF_SEL_CPG_GL1_ALL_REQ = 43 +GCR_PERF_SEL_CPG_METADATA_REQ = 44 +GCR_PERF_SEL_CPG_SQC_DATA_REQ = 45 +GCR_PERF_SEL_CPG_SQC_INST_REQ = 46 +GCR_PERF_SEL_CPG_TCP_REQ = 47 +GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 48 +GCR_PERF_SEL_CPC_ALL_REQ = 49 +GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 50 +GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 51 +GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 52 +GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 53 +GCR_PERF_SEL_CPC_GL2_ALL_REQ = 54 +GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 55 +GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 56 +GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 57 +GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 58 +GCR_PERF_SEL_CPC_GL1_ALL_REQ = 59 +GCR_PERF_SEL_CPC_METADATA_REQ = 60 +GCR_PERF_SEL_CPC_SQC_DATA_REQ = 61 +GCR_PERF_SEL_CPC_SQC_INST_REQ = 62 +GCR_PERF_SEL_CPC_TCP_REQ = 63 +GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 64 +GCR_PERF_SEL_CPF_ALL_REQ = 65 +GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 66 +GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 67 +GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 68 +GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 69 +GCR_PERF_SEL_CPF_GL2_ALL_REQ = 70 +GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 71 +GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 72 +GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 73 +GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 74 +GCR_PERF_SEL_CPF_GL1_ALL_REQ = 75 +GCR_PERF_SEL_CPF_METADATA_REQ = 76 +GCR_PERF_SEL_CPF_SQC_DATA_REQ = 77 +GCR_PERF_SEL_CPF_SQC_INST_REQ = 78 +GCR_PERF_SEL_CPF_TCP_REQ = 79 +GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 80 +GCR_PERF_SEL_VIRT_REQ = 81 +GCR_PERF_SEL_PHY_REQ = 82 +GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 83 +GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 84 +GCR_PERF_SEL_ALL_REQ = 85 +GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 86 +GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 87 +GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 88 +GCR_PERF_SEL_UTCL2_REQ = 89 +GCR_PERF_SEL_UTCL2_RET = 90 +GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 91 +GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 92 +GCR_PERF_SEL_UTCL2_FILTERED_RET = 93 +GCRPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1PerfSel' +UTCL1PerfSel__enumvalues = { + 0: 'UTCL1_PERF_SEL_NONE', + 1: 'UTCL1_PERF_SEL_REQS', + 2: 'UTCL1_PERF_SEL_HITS', + 3: 'UTCL1_PERF_SEL_MISSES', + 4: 'UTCL1_PERF_SEL_BYPASS_REQS', + 5: 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', + 6: 'UTCL1_PERF_SEL_NUM_SMALLK_PAGES', + 7: 'UTCL1_PERF_SEL_NUM_BIGK_PAGES', + 8: 'UTCL1_PERF_SEL_TOTAL_UTCL2_REQS', + 9: 'UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM', + 10: 'UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS', + 11: 'UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL', + 12: 'UTCL1_PERF_SEL_STALL_MH_CAM_FULL', + 13: 'UTCL1_PERF_SEL_NONRANGE_INV_REQS', + 14: 'UTCL1_PERF_SEL_RANGE_INV_REQS', +} +UTCL1_PERF_SEL_NONE = 0 +UTCL1_PERF_SEL_REQS = 1 +UTCL1_PERF_SEL_HITS = 2 +UTCL1_PERF_SEL_MISSES = 3 +UTCL1_PERF_SEL_BYPASS_REQS = 4 +UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 5 +UTCL1_PERF_SEL_NUM_SMALLK_PAGES = 6 +UTCL1_PERF_SEL_NUM_BIGK_PAGES = 7 +UTCL1_PERF_SEL_TOTAL_UTCL2_REQS = 8 +UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM = 9 +UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS = 10 +UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL = 11 +UTCL1_PERF_SEL_STALL_MH_CAM_FULL = 12 +UTCL1_PERF_SEL_NONRANGE_INV_REQS = 13 +UTCL1_PERF_SEL_RANGE_INV_REQS = 14 +UTCL1PerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'SDMA_PERF_SEL' +SDMA_PERF_SEL__enumvalues = { + 0: 'SDMA_PERF_SEL_CYCLE', + 1: 'SDMA_PERF_SEL_IDLE', + 2: 'SDMA_PERF_SEL_REG_IDLE', + 3: 'SDMA_PERF_SEL_RB_EMPTY', + 4: 'SDMA_PERF_SEL_RB_FULL', + 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', + 8: 'SDMA_PERF_SEL_RB_RPTR_WB', + 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', + 10: 'SDMA_PERF_SEL_RB_CMD_FULL', + 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', + 12: 'SDMA_PERF_SEL_IB_CMD_FULL', + 13: 'SDMA_PERF_SEL_EX_IDLE', + 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', + 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'SDMA_PERF_SEL_MC_WR_IDLE', + 17: 'SDMA_PERF_SEL_MC_WR_COUNT', + 18: 'SDMA_PERF_SEL_MC_RD_IDLE', + 19: 'SDMA_PERF_SEL_MC_RD_COUNT', + 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', + 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 24: 'SDMA_PERF_SEL_SEM_IDLE', + 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', + 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', + 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', + 30: 'SDMA_PERF_SEL_INT_IDLE', + 31: 'SDMA_PERF_SEL_INT_REQ_STALL', + 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', + 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', + 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', + 35: 'SDMA_PERF_SEL_NUM_PACKET', + 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 38: 'SDMA_PERF_SEL_CE_WR_IDLE', + 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', + 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', + 42: 'SDMA_PERF_SEL_CE_IN_IDLE', + 43: 'SDMA_PERF_SEL_CE_DST_IDLE', + 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', + 49: 'SDMA_PERF_SEL_CE_INFO_FULL', + 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', + 51: 'SDMA_PERF_SEL_CE_RD_STALL', + 52: 'SDMA_PERF_SEL_CE_WR_STALL', + 53: 'SDMA_PERF_SEL_GFX_SELECT', + 54: 'SDMA_PERF_SEL_RLC0_SELECT', + 55: 'SDMA_PERF_SEL_RLC1_SELECT', + 56: 'SDMA_PERF_SEL_PAGE_SELECT', + 57: 'SDMA_PERF_SEL_CTX_CHANGE', + 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', + 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 60: 'SDMA_PERF_SEL_DOORBELL', + 61: 'SDMA_PERF_SEL_RD_BA_RTR', + 62: 'SDMA_PERF_SEL_WR_BA_RTR', + 63: 'SDMA_PERF_SEL_F32_L1_WR_VLD', + 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', + 65: 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', + 66: 'SDMA_PERF_SEL_SDMA_CPF_INVACK', + 67: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', + 68: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', + 69: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', + 70: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', + 71: 'SDMA_PERF_SEL_UTCL2_RET_XNACK', + 72: 'SDMA_PERF_SEL_UTCL2_RET_ACK', + 73: 'SDMA_PERF_SEL_UTCL2_FREE', + 74: 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', + 75: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 76: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', + 77: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 78: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', + 79: 'SDMA_PERF_SEL_GPUVM_INVREQ_HIGH', + 80: 'SDMA_PERF_SEL_GPUVM_INVREQ_LOW', + 81: 'SDMA_PERF_SEL_L1_WRL2_IDLE', + 82: 'SDMA_PERF_SEL_L1_RDL2_IDLE', + 83: 'SDMA_PERF_SEL_L1_WRMC_IDLE', + 84: 'SDMA_PERF_SEL_L1_RDMC_IDLE', + 85: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', + 86: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', + 87: 'SDMA_PERF_SEL_META_L2_REQ_SEND', + 88: 'SDMA_PERF_SEL_L2_META_RET_VLD', + 89: 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', + 90: 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', + 91: 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', + 92: 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', + 93: 'SDMA_PERF_SEL_META_REQ_SEND', + 94: 'SDMA_PERF_SEL_META_RTN_VLD', + 95: 'SDMA_PERF_SEL_TLBI_SEND', + 96: 'SDMA_PERF_SEL_TLBI_RTN', + 97: 'SDMA_PERF_SEL_GCR_SEND', + 98: 'SDMA_PERF_SEL_GCR_RTN', + 99: 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER', + 100: 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER', +} +SDMA_PERF_SEL_CYCLE = 0 +SDMA_PERF_SEL_IDLE = 1 +SDMA_PERF_SEL_REG_IDLE = 2 +SDMA_PERF_SEL_RB_EMPTY = 3 +SDMA_PERF_SEL_RB_FULL = 4 +SDMA_PERF_SEL_RB_WPTR_WRAP = 5 +SDMA_PERF_SEL_RB_RPTR_WRAP = 6 +SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 +SDMA_PERF_SEL_RB_RPTR_WB = 8 +SDMA_PERF_SEL_RB_CMD_IDLE = 9 +SDMA_PERF_SEL_RB_CMD_FULL = 10 +SDMA_PERF_SEL_IB_CMD_IDLE = 11 +SDMA_PERF_SEL_IB_CMD_FULL = 12 +SDMA_PERF_SEL_EX_IDLE = 13 +SDMA_PERF_SEL_SRBM_REG_SEND = 14 +SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +SDMA_PERF_SEL_MC_WR_IDLE = 16 +SDMA_PERF_SEL_MC_WR_COUNT = 17 +SDMA_PERF_SEL_MC_RD_IDLE = 18 +SDMA_PERF_SEL_MC_RD_COUNT = 19 +SDMA_PERF_SEL_MC_RD_RET_STALL = 20 +SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 +SDMA_PERF_SEL_SEM_IDLE = 24 +SDMA_PERF_SEL_SEM_REQ_STALL = 25 +SDMA_PERF_SEL_SEM_REQ_COUNT = 26 +SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 +SDMA_PERF_SEL_SEM_RESP_FAIL = 28 +SDMA_PERF_SEL_SEM_RESP_PASS = 29 +SDMA_PERF_SEL_INT_IDLE = 30 +SDMA_PERF_SEL_INT_REQ_STALL = 31 +SDMA_PERF_SEL_INT_REQ_COUNT = 32 +SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 +SDMA_PERF_SEL_INT_RESP_RETRY = 34 +SDMA_PERF_SEL_NUM_PACKET = 35 +SDMA_PERF_SEL_CE_WREQ_IDLE = 37 +SDMA_PERF_SEL_CE_WR_IDLE = 38 +SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 +SDMA_PERF_SEL_CE_RREQ_IDLE = 40 +SDMA_PERF_SEL_CE_OUT_IDLE = 41 +SDMA_PERF_SEL_CE_IN_IDLE = 42 +SDMA_PERF_SEL_CE_DST_IDLE = 43 +SDMA_PERF_SEL_CE_AFIFO_FULL = 46 +SDMA_PERF_SEL_CE_INFO_FULL = 49 +SDMA_PERF_SEL_CE_INFO1_FULL = 50 +SDMA_PERF_SEL_CE_RD_STALL = 51 +SDMA_PERF_SEL_CE_WR_STALL = 52 +SDMA_PERF_SEL_GFX_SELECT = 53 +SDMA_PERF_SEL_RLC0_SELECT = 54 +SDMA_PERF_SEL_RLC1_SELECT = 55 +SDMA_PERF_SEL_PAGE_SELECT = 56 +SDMA_PERF_SEL_CTX_CHANGE = 57 +SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 +SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 +SDMA_PERF_SEL_DOORBELL = 60 +SDMA_PERF_SEL_RD_BA_RTR = 61 +SDMA_PERF_SEL_WR_BA_RTR = 62 +SDMA_PERF_SEL_F32_L1_WR_VLD = 63 +SDMA_PERF_SEL_CE_L1_WR_VLD = 64 +SDMA_PERF_SEL_CPF_SDMA_INVREQ = 65 +SDMA_PERF_SEL_SDMA_CPF_INVACK = 66 +SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 67 +SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 68 +SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 69 +SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 70 +SDMA_PERF_SEL_UTCL2_RET_XNACK = 71 +SDMA_PERF_SEL_UTCL2_RET_ACK = 72 +SDMA_PERF_SEL_UTCL2_FREE = 73 +SDMA_PERF_SEL_SDMA_UTCL2_SEND = 74 +SDMA_PERF_SEL_DMA_L1_WR_SEND = 75 +SDMA_PERF_SEL_DMA_L1_RD_SEND = 76 +SDMA_PERF_SEL_DMA_MC_WR_SEND = 77 +SDMA_PERF_SEL_DMA_MC_RD_SEND = 78 +SDMA_PERF_SEL_GPUVM_INVREQ_HIGH = 79 +SDMA_PERF_SEL_GPUVM_INVREQ_LOW = 80 +SDMA_PERF_SEL_L1_WRL2_IDLE = 81 +SDMA_PERF_SEL_L1_RDL2_IDLE = 82 +SDMA_PERF_SEL_L1_WRMC_IDLE = 83 +SDMA_PERF_SEL_L1_RDMC_IDLE = 84 +SDMA_PERF_SEL_L1_WR_INV_IDLE = 85 +SDMA_PERF_SEL_L1_RD_INV_IDLE = 86 +SDMA_PERF_SEL_META_L2_REQ_SEND = 87 +SDMA_PERF_SEL_L2_META_RET_VLD = 88 +SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 89 +SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 90 +SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 91 +SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 92 +SDMA_PERF_SEL_META_REQ_SEND = 93 +SDMA_PERF_SEL_META_RTN_VLD = 94 +SDMA_PERF_SEL_TLBI_SEND = 95 +SDMA_PERF_SEL_TLBI_RTN = 96 +SDMA_PERF_SEL_GCR_SEND = 97 +SDMA_PERF_SEL_GCR_RTN = 98 +SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 99 +SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 100 +SDMA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'NUM_PIPES_BC_ENUM' +NUM_PIPES_BC_ENUM__enumvalues = { + 0: 'ADDR_NUM_PIPES_BC_P8', + 1: 'ADDR_NUM_PIPES_BC_P16', +} +ADDR_NUM_PIPES_BC_P8 = 0 +ADDR_NUM_PIPES_BC_P16 = 1 +NUM_PIPES_BC_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'NUM_BANKS_BC_ENUM' +NUM_BANKS_BC_ENUM__enumvalues = { + 0: 'ADDR_NUM_BANKS_BC_BANKS_1', + 1: 'ADDR_NUM_BANKS_BC_BANKS_2', + 2: 'ADDR_NUM_BANKS_BC_BANKS_4', + 3: 'ADDR_NUM_BANKS_BC_BANKS_8', + 4: 'ADDR_NUM_BANKS_BC_BANKS_16', +} +ADDR_NUM_BANKS_BC_BANKS_1 = 0 +ADDR_NUM_BANKS_BC_BANKS_2 = 1 +ADDR_NUM_BANKS_BC_BANKS_4 = 2 +ADDR_NUM_BANKS_BC_BANKS_8 = 3 +ADDR_NUM_BANKS_BC_BANKS_16 = 4 +NUM_BANKS_BC_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'SWIZZLE_TYPE_ENUM' +SWIZZLE_TYPE_ENUM__enumvalues = { + 0: 'SW_Z', + 1: 'SW_S', + 2: 'SW_D', + 3: 'SW_R', + 4: 'SW_L', +} +SW_Z = 0 +SW_S = 1 +SW_D = 2 +SW_R = 3 +SW_L = 4 +SWIZZLE_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'TC_MICRO_TILE_MODE' +TC_MICRO_TILE_MODE__enumvalues = { + 0: 'MICRO_TILE_MODE_LINEAR', + 1: 'MICRO_TILE_MODE_RENDER_TARGET', + 2: 'MICRO_TILE_MODE_STD_2D', + 3: 'MICRO_TILE_MODE_STD_3D', + 4: 'MICRO_TILE_MODE_DISPLAY_2D', + 5: 'MICRO_TILE_MODE_DISPLAY_3D', + 6: 'MICRO_TILE_MODE_Z', +} +MICRO_TILE_MODE_LINEAR = 0 +MICRO_TILE_MODE_RENDER_TARGET = 1 +MICRO_TILE_MODE_STD_2D = 2 +MICRO_TILE_MODE_STD_3D = 3 +MICRO_TILE_MODE_DISPLAY_2D = 4 +MICRO_TILE_MODE_DISPLAY_3D = 5 +MICRO_TILE_MODE_Z = 6 +TC_MICRO_TILE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SWIZZLE_MODE_ENUM' +SWIZZLE_MODE_ENUM__enumvalues = { + 0: 'SW_LINEAR', + 1: 'SW_256B_S', + 2: 'SW_256B_D', + 3: 'SW_256B_R', + 4: 'SW_4KB_Z', + 5: 'SW_4KB_S', + 6: 'SW_4KB_D', + 7: 'SW_4KB_R', + 8: 'SW_64KB_Z', + 9: 'SW_64KB_S', + 10: 'SW_64KB_D', + 11: 'SW_64KB_R', + 12: 'SW_VAR_Z', + 13: 'SW_VAR_S', + 14: 'SW_VAR_D', + 15: 'SW_VAR_R', + 16: 'SW_64KB_Z_T', + 17: 'SW_64KB_S_T', + 18: 'SW_64KB_D_T', + 19: 'SW_64KB_R_T', + 20: 'SW_4KB_Z_X', + 21: 'SW_4KB_S_X', + 22: 'SW_4KB_D_X', + 23: 'SW_4KB_R_X', + 24: 'SW_64KB_Z_X', + 25: 'SW_64KB_S_X', + 26: 'SW_64KB_D_X', + 27: 'SW_64KB_R_X', + 28: 'SW_VAR_Z_X', + 29: 'SW_VAR_S_X', + 30: 'SW_VAR_D_X', + 31: 'SW_VAR_R_X', +} +SW_LINEAR = 0 +SW_256B_S = 1 +SW_256B_D = 2 +SW_256B_R = 3 +SW_4KB_Z = 4 +SW_4KB_S = 5 +SW_4KB_D = 6 +SW_4KB_R = 7 +SW_64KB_Z = 8 +SW_64KB_S = 9 +SW_64KB_D = 10 +SW_64KB_R = 11 +SW_VAR_Z = 12 +SW_VAR_S = 13 +SW_VAR_D = 14 +SW_VAR_R = 15 +SW_64KB_Z_T = 16 +SW_64KB_S_T = 17 +SW_64KB_D_T = 18 +SW_64KB_R_T = 19 +SW_4KB_Z_X = 20 +SW_4KB_S_X = 21 +SW_4KB_D_X = 22 +SW_4KB_R_X = 23 +SW_64KB_Z_X = 24 +SW_64KB_S_X = 25 +SW_64KB_D_X = 26 +SW_64KB_R_X = 27 +SW_VAR_Z_X = 28 +SW_VAR_S_X = 29 +SW_VAR_D_X = 30 +SW_VAR_R_X = 31 +SWIZZLE_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceEndian' +SurfaceEndian__enumvalues = { + 0: 'ENDIAN_NONE', + 1: 'ENDIAN_8IN16', + 2: 'ENDIAN_8IN32', + 3: 'ENDIAN_8IN64', +} +ENDIAN_NONE = 0 +ENDIAN_8IN16 = 1 +ENDIAN_8IN32 = 2 +ENDIAN_8IN64 = 3 +SurfaceEndian = ctypes.c_uint32 # enum + +# values for enumeration 'ArrayMode' +ArrayMode__enumvalues = { + 0: 'ARRAY_LINEAR_GENERAL', + 1: 'ARRAY_LINEAR_ALIGNED', + 2: 'ARRAY_1D_TILED_THIN1', + 3: 'ARRAY_1D_TILED_THICK', + 4: 'ARRAY_2D_TILED_THIN1', + 5: 'ARRAY_PRT_TILED_THIN1', + 6: 'ARRAY_PRT_2D_TILED_THIN1', + 7: 'ARRAY_2D_TILED_THICK', + 8: 'ARRAY_2D_TILED_XTHICK', + 9: 'ARRAY_PRT_TILED_THICK', + 10: 'ARRAY_PRT_2D_TILED_THICK', + 11: 'ARRAY_PRT_3D_TILED_THIN1', + 12: 'ARRAY_3D_TILED_THIN1', + 13: 'ARRAY_3D_TILED_THICK', + 14: 'ARRAY_3D_TILED_XTHICK', + 15: 'ARRAY_PRT_3D_TILED_THICK', +} +ARRAY_LINEAR_GENERAL = 0 +ARRAY_LINEAR_ALIGNED = 1 +ARRAY_1D_TILED_THIN1 = 2 +ARRAY_1D_TILED_THICK = 3 +ARRAY_2D_TILED_THIN1 = 4 +ARRAY_PRT_TILED_THIN1 = 5 +ARRAY_PRT_2D_TILED_THIN1 = 6 +ARRAY_2D_TILED_THICK = 7 +ARRAY_2D_TILED_XTHICK = 8 +ARRAY_PRT_TILED_THICK = 9 +ARRAY_PRT_2D_TILED_THICK = 10 +ARRAY_PRT_3D_TILED_THIN1 = 11 +ARRAY_3D_TILED_THIN1 = 12 +ARRAY_3D_TILED_THICK = 13 +ARRAY_3D_TILED_XTHICK = 14 +ARRAY_PRT_3D_TILED_THICK = 15 +ArrayMode = ctypes.c_uint32 # enum + +# values for enumeration 'NumPipes' +NumPipes__enumvalues = { + 0: 'ADDR_CONFIG_1_PIPE', + 1: 'ADDR_CONFIG_2_PIPE', + 2: 'ADDR_CONFIG_4_PIPE', + 3: 'ADDR_CONFIG_8_PIPE', + 4: 'ADDR_CONFIG_16_PIPE', + 5: 'ADDR_CONFIG_32_PIPE', + 6: 'ADDR_CONFIG_64_PIPE', +} +ADDR_CONFIG_1_PIPE = 0 +ADDR_CONFIG_2_PIPE = 1 +ADDR_CONFIG_4_PIPE = 2 +ADDR_CONFIG_8_PIPE = 3 +ADDR_CONFIG_16_PIPE = 4 +ADDR_CONFIG_32_PIPE = 5 +ADDR_CONFIG_64_PIPE = 6 +NumPipes = ctypes.c_uint32 # enum + +# values for enumeration 'NumBanksConfig' +NumBanksConfig__enumvalues = { + 0: 'ADDR_CONFIG_1_BANK', + 1: 'ADDR_CONFIG_2_BANK', + 2: 'ADDR_CONFIG_4_BANK', + 3: 'ADDR_CONFIG_8_BANK', + 4: 'ADDR_CONFIG_16_BANK', +} +ADDR_CONFIG_1_BANK = 0 +ADDR_CONFIG_2_BANK = 1 +ADDR_CONFIG_4_BANK = 2 +ADDR_CONFIG_8_BANK = 3 +ADDR_CONFIG_16_BANK = 4 +NumBanksConfig = ctypes.c_uint32 # enum + +# values for enumeration 'PipeInterleaveSize' +PipeInterleaveSize__enumvalues = { + 0: 'ADDR_CONFIG_PIPE_INTERLEAVE_256B', + 1: 'ADDR_CONFIG_PIPE_INTERLEAVE_512B', + 2: 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB', + 3: 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB', +} +ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0 +ADDR_CONFIG_PIPE_INTERLEAVE_512B = 1 +ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 2 +ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 3 +PipeInterleaveSize = ctypes.c_uint32 # enum + +# values for enumeration 'BankInterleaveSize' +BankInterleaveSize__enumvalues = { + 0: 'ADDR_CONFIG_BANK_INTERLEAVE_1', + 1: 'ADDR_CONFIG_BANK_INTERLEAVE_2', + 2: 'ADDR_CONFIG_BANK_INTERLEAVE_4', + 3: 'ADDR_CONFIG_BANK_INTERLEAVE_8', +} +ADDR_CONFIG_BANK_INTERLEAVE_1 = 0 +ADDR_CONFIG_BANK_INTERLEAVE_2 = 1 +ADDR_CONFIG_BANK_INTERLEAVE_4 = 2 +ADDR_CONFIG_BANK_INTERLEAVE_8 = 3 +BankInterleaveSize = ctypes.c_uint32 # enum + +# values for enumeration 'NumShaderEngines' +NumShaderEngines__enumvalues = { + 0: 'ADDR_CONFIG_1_SHADER_ENGINE', + 1: 'ADDR_CONFIG_2_SHADER_ENGINE', + 2: 'ADDR_CONFIG_4_SHADER_ENGINE', + 3: 'ADDR_CONFIG_8_SHADER_ENGINE', +} +ADDR_CONFIG_1_SHADER_ENGINE = 0 +ADDR_CONFIG_2_SHADER_ENGINE = 1 +ADDR_CONFIG_4_SHADER_ENGINE = 2 +ADDR_CONFIG_8_SHADER_ENGINE = 3 +NumShaderEngines = ctypes.c_uint32 # enum + +# values for enumeration 'NumRbPerShaderEngine' +NumRbPerShaderEngine__enumvalues = { + 0: 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE', + 1: 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE', + 2: 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE', +} +ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0 +ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 1 +ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 2 +NumRbPerShaderEngine = ctypes.c_uint32 # enum + +# values for enumeration 'NumGPUs' +NumGPUs__enumvalues = { + 0: 'ADDR_CONFIG_1_GPU', + 1: 'ADDR_CONFIG_2_GPU', + 2: 'ADDR_CONFIG_4_GPU', + 3: 'ADDR_CONFIG_8_GPU', +} +ADDR_CONFIG_1_GPU = 0 +ADDR_CONFIG_2_GPU = 1 +ADDR_CONFIG_4_GPU = 2 +ADDR_CONFIG_8_GPU = 3 +NumGPUs = ctypes.c_uint32 # enum + +# values for enumeration 'NumMaxCompressedFragments' +NumMaxCompressedFragments__enumvalues = { + 0: 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', + 1: 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', + 2: 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', + 3: 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', +} +ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0 +ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 1 +ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 2 +ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 3 +NumMaxCompressedFragments = ctypes.c_uint32 # enum + +# values for enumeration 'ShaderEngineTileSize' +ShaderEngineTileSize__enumvalues = { + 0: 'ADDR_CONFIG_SE_TILE_16', + 1: 'ADDR_CONFIG_SE_TILE_32', +} +ADDR_CONFIG_SE_TILE_16 = 0 +ADDR_CONFIG_SE_TILE_32 = 1 +ShaderEngineTileSize = ctypes.c_uint32 # enum + +# values for enumeration 'MultiGPUTileSize' +MultiGPUTileSize__enumvalues = { + 0: 'ADDR_CONFIG_GPU_TILE_16', + 1: 'ADDR_CONFIG_GPU_TILE_32', + 2: 'ADDR_CONFIG_GPU_TILE_64', + 3: 'ADDR_CONFIG_GPU_TILE_128', +} +ADDR_CONFIG_GPU_TILE_16 = 0 +ADDR_CONFIG_GPU_TILE_32 = 1 +ADDR_CONFIG_GPU_TILE_64 = 2 +ADDR_CONFIG_GPU_TILE_128 = 3 +MultiGPUTileSize = ctypes.c_uint32 # enum + +# values for enumeration 'RowSize' +RowSize__enumvalues = { + 0: 'ADDR_CONFIG_1KB_ROW', + 1: 'ADDR_CONFIG_2KB_ROW', + 2: 'ADDR_CONFIG_4KB_ROW', +} +ADDR_CONFIG_1KB_ROW = 0 +ADDR_CONFIG_2KB_ROW = 1 +ADDR_CONFIG_4KB_ROW = 2 +RowSize = ctypes.c_uint32 # enum + +# values for enumeration 'NumLowerPipes' +NumLowerPipes__enumvalues = { + 0: 'ADDR_CONFIG_1_LOWER_PIPES', + 1: 'ADDR_CONFIG_2_LOWER_PIPES', +} +ADDR_CONFIG_1_LOWER_PIPES = 0 +ADDR_CONFIG_2_LOWER_PIPES = 1 +NumLowerPipes = ctypes.c_uint32 # enum + +# values for enumeration 'ColorTransform' +ColorTransform__enumvalues = { + 0: 'DCC_CT_AUTO', + 1: 'DCC_CT_NONE', + 2: 'ABGR_TO_A_BG_G_RB', + 3: 'BGRA_TO_BG_G_RB_A', +} +DCC_CT_AUTO = 0 +DCC_CT_NONE = 1 +ABGR_TO_A_BG_G_RB = 2 +BGRA_TO_BG_G_RB_A = 3 +ColorTransform = ctypes.c_uint32 # enum + +# values for enumeration 'CompareRef' +CompareRef__enumvalues = { + 0: 'REF_NEVER', + 1: 'REF_LESS', + 2: 'REF_EQUAL', + 3: 'REF_LEQUAL', + 4: 'REF_GREATER', + 5: 'REF_NOTEQUAL', + 6: 'REF_GEQUAL', + 7: 'REF_ALWAYS', +} +REF_NEVER = 0 +REF_LESS = 1 +REF_EQUAL = 2 +REF_LEQUAL = 3 +REF_GREATER = 4 +REF_NOTEQUAL = 5 +REF_GEQUAL = 6 +REF_ALWAYS = 7 +CompareRef = ctypes.c_uint32 # enum + +# values for enumeration 'ReadSize' +ReadSize__enumvalues = { + 0: 'READ_256_BITS', + 1: 'READ_512_BITS', +} +READ_256_BITS = 0 +READ_512_BITS = 1 +ReadSize = ctypes.c_uint32 # enum + +# values for enumeration 'DepthFormat' +DepthFormat__enumvalues = { + 0: 'DEPTH_INVALID', + 1: 'DEPTH_16', + 2: 'DEPTH_X8_24', + 3: 'DEPTH_8_24', + 4: 'DEPTH_X8_24_FLOAT', + 5: 'DEPTH_8_24_FLOAT', + 6: 'DEPTH_32_FLOAT', + 7: 'DEPTH_X24_8_32_FLOAT', +} +DEPTH_INVALID = 0 +DEPTH_16 = 1 +DEPTH_X8_24 = 2 +DEPTH_8_24 = 3 +DEPTH_X8_24_FLOAT = 4 +DEPTH_8_24_FLOAT = 5 +DEPTH_32_FLOAT = 6 +DEPTH_X24_8_32_FLOAT = 7 +DepthFormat = ctypes.c_uint32 # enum + +# values for enumeration 'ZFormat' +ZFormat__enumvalues = { + 0: 'Z_INVALID', + 1: 'Z_16', + 2: 'Z_24', + 3: 'Z_32_FLOAT', +} +Z_INVALID = 0 +Z_16 = 1 +Z_24 = 2 +Z_32_FLOAT = 3 +ZFormat = ctypes.c_uint32 # enum + +# values for enumeration 'StencilFormat' +StencilFormat__enumvalues = { + 0: 'STENCIL_INVALID', + 1: 'STENCIL_8', +} +STENCIL_INVALID = 0 +STENCIL_8 = 1 +StencilFormat = ctypes.c_uint32 # enum + +# values for enumeration 'CmaskMode' +CmaskMode__enumvalues = { + 0: 'CMASK_CLEAR_NONE', + 1: 'CMASK_CLEAR_ONE', + 2: 'CMASK_CLEAR_ALL', + 3: 'CMASK_ANY_EXPANDED', + 4: 'CMASK_ALPHA0_FRAG1', + 5: 'CMASK_ALPHA0_FRAG2', + 6: 'CMASK_ALPHA0_FRAG4', + 7: 'CMASK_ALPHA0_FRAGS', + 8: 'CMASK_ALPHA1_FRAG1', + 9: 'CMASK_ALPHA1_FRAG2', + 10: 'CMASK_ALPHA1_FRAG4', + 11: 'CMASK_ALPHA1_FRAGS', + 12: 'CMASK_ALPHAX_FRAG1', + 13: 'CMASK_ALPHAX_FRAG2', + 14: 'CMASK_ALPHAX_FRAG4', + 15: 'CMASK_ALPHAX_FRAGS', +} +CMASK_CLEAR_NONE = 0 +CMASK_CLEAR_ONE = 1 +CMASK_CLEAR_ALL = 2 +CMASK_ANY_EXPANDED = 3 +CMASK_ALPHA0_FRAG1 = 4 +CMASK_ALPHA0_FRAG2 = 5 +CMASK_ALPHA0_FRAG4 = 6 +CMASK_ALPHA0_FRAGS = 7 +CMASK_ALPHA1_FRAG1 = 8 +CMASK_ALPHA1_FRAG2 = 9 +CMASK_ALPHA1_FRAG4 = 10 +CMASK_ALPHA1_FRAGS = 11 +CMASK_ALPHAX_FRAG1 = 12 +CMASK_ALPHAX_FRAG2 = 13 +CMASK_ALPHAX_FRAG4 = 14 +CMASK_ALPHAX_FRAGS = 15 +CmaskMode = ctypes.c_uint32 # enum + +# values for enumeration 'QuadExportFormat' +QuadExportFormat__enumvalues = { + 0: 'EXPORT_UNUSED', + 1: 'EXPORT_32_R', + 2: 'EXPORT_32_GR', + 3: 'EXPORT_32_AR', + 4: 'EXPORT_FP16_ABGR', + 5: 'EXPORT_UNSIGNED16_ABGR', + 6: 'EXPORT_SIGNED16_ABGR', + 7: 'EXPORT_32_ABGR', + 8: 'EXPORT_32BPP_8PIX', + 9: 'EXPORT_16_16_UNSIGNED_8PIX', + 10: 'EXPORT_16_16_SIGNED_8PIX', + 11: 'EXPORT_16_16_FLOAT_8PIX', +} +EXPORT_UNUSED = 0 +EXPORT_32_R = 1 +EXPORT_32_GR = 2 +EXPORT_32_AR = 3 +EXPORT_FP16_ABGR = 4 +EXPORT_UNSIGNED16_ABGR = 5 +EXPORT_SIGNED16_ABGR = 6 +EXPORT_32_ABGR = 7 +EXPORT_32BPP_8PIX = 8 +EXPORT_16_16_UNSIGNED_8PIX = 9 +EXPORT_16_16_SIGNED_8PIX = 10 +EXPORT_16_16_FLOAT_8PIX = 11 +QuadExportFormat = ctypes.c_uint32 # enum + +# values for enumeration 'QuadExportFormatOld' +QuadExportFormatOld__enumvalues = { + 0: 'EXPORT_4P_32BPC_ABGR', + 1: 'EXPORT_4P_16BPC_ABGR', + 2: 'EXPORT_4P_32BPC_GR', + 3: 'EXPORT_4P_32BPC_AR', + 4: 'EXPORT_2P_32BPC_ABGR', + 5: 'EXPORT_8P_32BPC_R', +} +EXPORT_4P_32BPC_ABGR = 0 +EXPORT_4P_16BPC_ABGR = 1 +EXPORT_4P_32BPC_GR = 2 +EXPORT_4P_32BPC_AR = 3 +EXPORT_2P_32BPC_ABGR = 4 +EXPORT_8P_32BPC_R = 5 +QuadExportFormatOld = ctypes.c_uint32 # enum + +# values for enumeration 'ColorFormat' +ColorFormat__enumvalues = { + 0: 'COLOR_INVALID', + 1: 'COLOR_8', + 2: 'COLOR_16', + 3: 'COLOR_8_8', + 4: 'COLOR_32', + 5: 'COLOR_16_16', + 6: 'COLOR_10_11_11', + 7: 'COLOR_11_11_10', + 8: 'COLOR_10_10_10_2', + 9: 'COLOR_2_10_10_10', + 10: 'COLOR_8_8_8_8', + 11: 'COLOR_32_32', + 12: 'COLOR_16_16_16_16', + 13: 'COLOR_RESERVED_13', + 14: 'COLOR_32_32_32_32', + 15: 'COLOR_RESERVED_15', + 16: 'COLOR_5_6_5', + 17: 'COLOR_1_5_5_5', + 18: 'COLOR_5_5_5_1', + 19: 'COLOR_4_4_4_4', + 20: 'COLOR_8_24', + 21: 'COLOR_24_8', + 22: 'COLOR_X24_8_32_FLOAT', + 23: 'COLOR_RESERVED_23', + 24: 'COLOR_RESERVED_24', + 25: 'COLOR_RESERVED_25', + 26: 'COLOR_RESERVED_26', + 27: 'COLOR_RESERVED_27', + 28: 'COLOR_RESERVED_28', + 29: 'COLOR_RESERVED_29', + 30: 'COLOR_RESERVED_30', + 31: 'COLOR_2_10_10_10_6E4', +} +COLOR_INVALID = 0 +COLOR_8 = 1 +COLOR_16 = 2 +COLOR_8_8 = 3 +COLOR_32 = 4 +COLOR_16_16 = 5 +COLOR_10_11_11 = 6 +COLOR_11_11_10 = 7 +COLOR_10_10_10_2 = 8 +COLOR_2_10_10_10 = 9 +COLOR_8_8_8_8 = 10 +COLOR_32_32 = 11 +COLOR_16_16_16_16 = 12 +COLOR_RESERVED_13 = 13 +COLOR_32_32_32_32 = 14 +COLOR_RESERVED_15 = 15 +COLOR_5_6_5 = 16 +COLOR_1_5_5_5 = 17 +COLOR_5_5_5_1 = 18 +COLOR_4_4_4_4 = 19 +COLOR_8_24 = 20 +COLOR_24_8 = 21 +COLOR_X24_8_32_FLOAT = 22 +COLOR_RESERVED_23 = 23 +COLOR_RESERVED_24 = 24 +COLOR_RESERVED_25 = 25 +COLOR_RESERVED_26 = 26 +COLOR_RESERVED_27 = 27 +COLOR_RESERVED_28 = 28 +COLOR_RESERVED_29 = 29 +COLOR_RESERVED_30 = 30 +COLOR_2_10_10_10_6E4 = 31 +ColorFormat = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceFormat' +SurfaceFormat__enumvalues = { + 0: 'FMT_INVALID', + 1: 'FMT_8', + 2: 'FMT_16', + 3: 'FMT_8_8', + 4: 'FMT_32', + 5: 'FMT_16_16', + 6: 'FMT_10_11_11', + 7: 'FMT_11_11_10', + 8: 'FMT_10_10_10_2', + 9: 'FMT_2_10_10_10', + 10: 'FMT_8_8_8_8', + 11: 'FMT_32_32', + 12: 'FMT_16_16_16_16', + 13: 'FMT_32_32_32', + 14: 'FMT_32_32_32_32', + 15: 'FMT_RESERVED_4', + 16: 'FMT_5_6_5', + 17: 'FMT_1_5_5_5', + 18: 'FMT_5_5_5_1', + 19: 'FMT_4_4_4_4', + 20: 'FMT_8_24', + 21: 'FMT_24_8', + 22: 'FMT_X24_8_32_FLOAT', + 23: 'FMT_RESERVED_33', + 24: 'FMT_11_11_10_FLOAT', + 25: 'FMT_16_FLOAT', + 26: 'FMT_32_FLOAT', + 27: 'FMT_16_16_FLOAT', + 28: 'FMT_8_24_FLOAT', + 29: 'FMT_24_8_FLOAT', + 30: 'FMT_32_32_FLOAT', + 31: 'FMT_10_11_11_FLOAT', + 32: 'FMT_16_16_16_16_FLOAT', + 33: 'FMT_3_3_2', + 34: 'FMT_6_5_5', + 35: 'FMT_32_32_32_32_FLOAT', + 36: 'FMT_RESERVED_36', + 37: 'FMT_1', + 38: 'FMT_1_REVERSED', + 39: 'FMT_GB_GR', + 40: 'FMT_BG_RG', + 41: 'FMT_32_AS_8', + 42: 'FMT_32_AS_8_8', + 43: 'FMT_5_9_9_9_SHAREDEXP', + 44: 'FMT_8_8_8', + 45: 'FMT_16_16_16', + 46: 'FMT_16_16_16_FLOAT', + 47: 'FMT_4_4', + 48: 'FMT_32_32_32_FLOAT', + 49: 'FMT_BC1', + 50: 'FMT_BC2', + 51: 'FMT_BC3', + 52: 'FMT_BC4', + 53: 'FMT_BC5', + 54: 'FMT_BC6', + 55: 'FMT_BC7', + 56: 'FMT_32_AS_32_32_32_32', + 57: 'FMT_APC3', + 58: 'FMT_APC4', + 59: 'FMT_APC5', + 60: 'FMT_APC6', + 61: 'FMT_APC7', + 62: 'FMT_CTX1', + 63: 'FMT_RESERVED_63', +} +FMT_INVALID = 0 +FMT_8 = 1 +FMT_16 = 2 +FMT_8_8 = 3 +FMT_32 = 4 +FMT_16_16 = 5 +FMT_10_11_11 = 6 +FMT_11_11_10 = 7 +FMT_10_10_10_2 = 8 +FMT_2_10_10_10 = 9 +FMT_8_8_8_8 = 10 +FMT_32_32 = 11 +FMT_16_16_16_16 = 12 +FMT_32_32_32 = 13 +FMT_32_32_32_32 = 14 +FMT_RESERVED_4 = 15 +FMT_5_6_5 = 16 +FMT_1_5_5_5 = 17 +FMT_5_5_5_1 = 18 +FMT_4_4_4_4 = 19 +FMT_8_24 = 20 +FMT_24_8 = 21 +FMT_X24_8_32_FLOAT = 22 +FMT_RESERVED_33 = 23 +FMT_11_11_10_FLOAT = 24 +FMT_16_FLOAT = 25 +FMT_32_FLOAT = 26 +FMT_16_16_FLOAT = 27 +FMT_8_24_FLOAT = 28 +FMT_24_8_FLOAT = 29 +FMT_32_32_FLOAT = 30 +FMT_10_11_11_FLOAT = 31 +FMT_16_16_16_16_FLOAT = 32 +FMT_3_3_2 = 33 +FMT_6_5_5 = 34 +FMT_32_32_32_32_FLOAT = 35 +FMT_RESERVED_36 = 36 +FMT_1 = 37 +FMT_1_REVERSED = 38 +FMT_GB_GR = 39 +FMT_BG_RG = 40 +FMT_32_AS_8 = 41 +FMT_32_AS_8_8 = 42 +FMT_5_9_9_9_SHAREDEXP = 43 +FMT_8_8_8 = 44 +FMT_16_16_16 = 45 +FMT_16_16_16_FLOAT = 46 +FMT_4_4 = 47 +FMT_32_32_32_FLOAT = 48 +FMT_BC1 = 49 +FMT_BC2 = 50 +FMT_BC3 = 51 +FMT_BC4 = 52 +FMT_BC5 = 53 +FMT_BC6 = 54 +FMT_BC7 = 55 +FMT_32_AS_32_32_32_32 = 56 +FMT_APC3 = 57 +FMT_APC4 = 58 +FMT_APC5 = 59 +FMT_APC6 = 60 +FMT_APC7 = 61 +FMT_CTX1 = 62 +FMT_RESERVED_63 = 63 +SurfaceFormat = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT_FMASK' +IMG_NUM_FORMAT_FMASK__enumvalues = { + 0: 'IMG_NUM_FORMAT_FMASK_8_2_1', + 1: 'IMG_NUM_FORMAT_FMASK_8_4_1', + 2: 'IMG_NUM_FORMAT_FMASK_8_8_1', + 3: 'IMG_NUM_FORMAT_FMASK_8_2_2', + 4: 'IMG_NUM_FORMAT_FMASK_8_4_2', + 5: 'IMG_NUM_FORMAT_FMASK_8_4_4', + 6: 'IMG_NUM_FORMAT_FMASK_16_16_1', + 7: 'IMG_NUM_FORMAT_FMASK_16_8_2', + 8: 'IMG_NUM_FORMAT_FMASK_32_16_2', + 9: 'IMG_NUM_FORMAT_FMASK_32_8_4', + 10: 'IMG_NUM_FORMAT_FMASK_32_8_8', + 11: 'IMG_NUM_FORMAT_FMASK_64_16_4', + 12: 'IMG_NUM_FORMAT_FMASK_64_16_8', + 13: 'IMG_NUM_FORMAT_FMASK_RESERVED_13', + 14: 'IMG_NUM_FORMAT_FMASK_RESERVED_14', + 15: 'IMG_NUM_FORMAT_FMASK_RESERVED_15', +} +IMG_NUM_FORMAT_FMASK_8_2_1 = 0 +IMG_NUM_FORMAT_FMASK_8_4_1 = 1 +IMG_NUM_FORMAT_FMASK_8_8_1 = 2 +IMG_NUM_FORMAT_FMASK_8_2_2 = 3 +IMG_NUM_FORMAT_FMASK_8_4_2 = 4 +IMG_NUM_FORMAT_FMASK_8_4_4 = 5 +IMG_NUM_FORMAT_FMASK_16_16_1 = 6 +IMG_NUM_FORMAT_FMASK_16_8_2 = 7 +IMG_NUM_FORMAT_FMASK_32_16_2 = 8 +IMG_NUM_FORMAT_FMASK_32_8_4 = 9 +IMG_NUM_FORMAT_FMASK_32_8_8 = 10 +IMG_NUM_FORMAT_FMASK_64_16_4 = 11 +IMG_NUM_FORMAT_FMASK_64_16_8 = 12 +IMG_NUM_FORMAT_FMASK_RESERVED_13 = 13 +IMG_NUM_FORMAT_FMASK_RESERVED_14 = 14 +IMG_NUM_FORMAT_FMASK_RESERVED_15 = 15 +IMG_NUM_FORMAT_FMASK = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT_N_IN_16' +IMG_NUM_FORMAT_N_IN_16__enumvalues = { + 0: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0', + 1: 'IMG_NUM_FORMAT_N_IN_16_UNORM_10', + 2: 'IMG_NUM_FORMAT_N_IN_16_UNORM_9', + 3: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3', + 4: 'IMG_NUM_FORMAT_N_IN_16_UINT_10', + 5: 'IMG_NUM_FORMAT_N_IN_16_UINT_9', + 6: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6', + 7: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10', + 8: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9', + 9: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9', + 10: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10', + 11: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11', + 12: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12', + 13: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13', + 14: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14', + 15: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15', +} +IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0 +IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 1 +IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 2 +IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 3 +IMG_NUM_FORMAT_N_IN_16_UINT_10 = 4 +IMG_NUM_FORMAT_N_IN_16_UINT_9 = 5 +IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 6 +IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 7 +IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 8 +IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 9 +IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 10 +IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 11 +IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 12 +IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 13 +IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 14 +IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 15 +IMG_NUM_FORMAT_N_IN_16 = ctypes.c_uint32 # enum + +# values for enumeration 'TileType' +TileType__enumvalues = { + 0: 'ARRAY_COLOR_TILE', + 1: 'ARRAY_DEPTH_TILE', +} +ARRAY_COLOR_TILE = 0 +ARRAY_DEPTH_TILE = 1 +TileType = ctypes.c_uint32 # enum + +# values for enumeration 'NonDispTilingOrder' +NonDispTilingOrder__enumvalues = { + 0: 'ADDR_SURF_MICRO_TILING_DISPLAY', + 1: 'ADDR_SURF_MICRO_TILING_NON_DISPLAY', +} +ADDR_SURF_MICRO_TILING_DISPLAY = 0 +ADDR_SURF_MICRO_TILING_NON_DISPLAY = 1 +NonDispTilingOrder = ctypes.c_uint32 # enum + +# values for enumeration 'MicroTileMode' +MicroTileMode__enumvalues = { + 0: 'ADDR_SURF_DISPLAY_MICRO_TILING', + 1: 'ADDR_SURF_THIN_MICRO_TILING', + 2: 'ADDR_SURF_DEPTH_MICRO_TILING', + 3: 'ADDR_SURF_ROTATED_MICRO_TILING', + 4: 'ADDR_SURF_THICK_MICRO_TILING', +} +ADDR_SURF_DISPLAY_MICRO_TILING = 0 +ADDR_SURF_THIN_MICRO_TILING = 1 +ADDR_SURF_DEPTH_MICRO_TILING = 2 +ADDR_SURF_ROTATED_MICRO_TILING = 3 +ADDR_SURF_THICK_MICRO_TILING = 4 +MicroTileMode = ctypes.c_uint32 # enum + +# values for enumeration 'TileSplit' +TileSplit__enumvalues = { + 0: 'ADDR_SURF_TILE_SPLIT_64B', + 1: 'ADDR_SURF_TILE_SPLIT_128B', + 2: 'ADDR_SURF_TILE_SPLIT_256B', + 3: 'ADDR_SURF_TILE_SPLIT_512B', + 4: 'ADDR_SURF_TILE_SPLIT_1KB', + 5: 'ADDR_SURF_TILE_SPLIT_2KB', + 6: 'ADDR_SURF_TILE_SPLIT_4KB', +} +ADDR_SURF_TILE_SPLIT_64B = 0 +ADDR_SURF_TILE_SPLIT_128B = 1 +ADDR_SURF_TILE_SPLIT_256B = 2 +ADDR_SURF_TILE_SPLIT_512B = 3 +ADDR_SURF_TILE_SPLIT_1KB = 4 +ADDR_SURF_TILE_SPLIT_2KB = 5 +ADDR_SURF_TILE_SPLIT_4KB = 6 +TileSplit = ctypes.c_uint32 # enum + +# values for enumeration 'SampleSplit' +SampleSplit__enumvalues = { + 0: 'ADDR_SURF_SAMPLE_SPLIT_1', + 1: 'ADDR_SURF_SAMPLE_SPLIT_2', + 2: 'ADDR_SURF_SAMPLE_SPLIT_4', + 3: 'ADDR_SURF_SAMPLE_SPLIT_8', +} +ADDR_SURF_SAMPLE_SPLIT_1 = 0 +ADDR_SURF_SAMPLE_SPLIT_2 = 1 +ADDR_SURF_SAMPLE_SPLIT_4 = 2 +ADDR_SURF_SAMPLE_SPLIT_8 = 3 +SampleSplit = ctypes.c_uint32 # enum + +# values for enumeration 'PipeConfig' +PipeConfig__enumvalues = { + 0: 'ADDR_SURF_P2', + 1: 'ADDR_SURF_P2_RESERVED0', + 2: 'ADDR_SURF_P2_RESERVED1', + 3: 'ADDR_SURF_P2_RESERVED2', + 4: 'ADDR_SURF_P4_8x16', + 5: 'ADDR_SURF_P4_16x16', + 6: 'ADDR_SURF_P4_16x32', + 7: 'ADDR_SURF_P4_32x32', + 8: 'ADDR_SURF_P8_16x16_8x16', + 9: 'ADDR_SURF_P8_16x32_8x16', + 10: 'ADDR_SURF_P8_32x32_8x16', + 11: 'ADDR_SURF_P8_16x32_16x16', + 12: 'ADDR_SURF_P8_32x32_16x16', + 13: 'ADDR_SURF_P8_32x32_16x32', + 14: 'ADDR_SURF_P8_32x64_32x32', + 15: 'ADDR_SURF_P8_RESERVED0', + 16: 'ADDR_SURF_P16_32x32_8x16', + 17: 'ADDR_SURF_P16_32x32_16x16', + 18: 'ADDR_SURF_P16', +} +ADDR_SURF_P2 = 0 +ADDR_SURF_P2_RESERVED0 = 1 +ADDR_SURF_P2_RESERVED1 = 2 +ADDR_SURF_P2_RESERVED2 = 3 +ADDR_SURF_P4_8x16 = 4 +ADDR_SURF_P4_16x16 = 5 +ADDR_SURF_P4_16x32 = 6 +ADDR_SURF_P4_32x32 = 7 +ADDR_SURF_P8_16x16_8x16 = 8 +ADDR_SURF_P8_16x32_8x16 = 9 +ADDR_SURF_P8_32x32_8x16 = 10 +ADDR_SURF_P8_16x32_16x16 = 11 +ADDR_SURF_P8_32x32_16x16 = 12 +ADDR_SURF_P8_32x32_16x32 = 13 +ADDR_SURF_P8_32x64_32x32 = 14 +ADDR_SURF_P8_RESERVED0 = 15 +ADDR_SURF_P16_32x32_8x16 = 16 +ADDR_SURF_P16_32x32_16x16 = 17 +ADDR_SURF_P16 = 18 +PipeConfig = ctypes.c_uint32 # enum + +# values for enumeration 'SeEnable' +SeEnable__enumvalues = { + 0: 'ADDR_CONFIG_DISABLE_SE', + 1: 'ADDR_CONFIG_ENABLE_SE', +} +ADDR_CONFIG_DISABLE_SE = 0 +ADDR_CONFIG_ENABLE_SE = 1 +SeEnable = ctypes.c_uint32 # enum + +# values for enumeration 'NumBanks' +NumBanks__enumvalues = { + 0: 'ADDR_SURF_2_BANK', + 1: 'ADDR_SURF_4_BANK', + 2: 'ADDR_SURF_8_BANK', + 3: 'ADDR_SURF_16_BANK', +} +ADDR_SURF_2_BANK = 0 +ADDR_SURF_4_BANK = 1 +ADDR_SURF_8_BANK = 2 +ADDR_SURF_16_BANK = 3 +NumBanks = ctypes.c_uint32 # enum + +# values for enumeration 'BankWidth' +BankWidth__enumvalues = { + 0: 'ADDR_SURF_BANK_WIDTH_1', + 1: 'ADDR_SURF_BANK_WIDTH_2', + 2: 'ADDR_SURF_BANK_WIDTH_4', + 3: 'ADDR_SURF_BANK_WIDTH_8', +} +ADDR_SURF_BANK_WIDTH_1 = 0 +ADDR_SURF_BANK_WIDTH_2 = 1 +ADDR_SURF_BANK_WIDTH_4 = 2 +ADDR_SURF_BANK_WIDTH_8 = 3 +BankWidth = ctypes.c_uint32 # enum + +# values for enumeration 'BankHeight' +BankHeight__enumvalues = { + 0: 'ADDR_SURF_BANK_HEIGHT_1', + 1: 'ADDR_SURF_BANK_HEIGHT_2', + 2: 'ADDR_SURF_BANK_HEIGHT_4', + 3: 'ADDR_SURF_BANK_HEIGHT_8', +} +ADDR_SURF_BANK_HEIGHT_1 = 0 +ADDR_SURF_BANK_HEIGHT_2 = 1 +ADDR_SURF_BANK_HEIGHT_4 = 2 +ADDR_SURF_BANK_HEIGHT_8 = 3 +BankHeight = ctypes.c_uint32 # enum + +# values for enumeration 'BankWidthHeight' +BankWidthHeight__enumvalues = { + 0: 'ADDR_SURF_BANK_WH_1', + 1: 'ADDR_SURF_BANK_WH_2', + 2: 'ADDR_SURF_BANK_WH_4', + 3: 'ADDR_SURF_BANK_WH_8', +} +ADDR_SURF_BANK_WH_1 = 0 +ADDR_SURF_BANK_WH_2 = 1 +ADDR_SURF_BANK_WH_4 = 2 +ADDR_SURF_BANK_WH_8 = 3 +BankWidthHeight = ctypes.c_uint32 # enum + +# values for enumeration 'MacroTileAspect' +MacroTileAspect__enumvalues = { + 0: 'ADDR_SURF_MACRO_ASPECT_1', + 1: 'ADDR_SURF_MACRO_ASPECT_2', + 2: 'ADDR_SURF_MACRO_ASPECT_4', + 3: 'ADDR_SURF_MACRO_ASPECT_8', +} +ADDR_SURF_MACRO_ASPECT_1 = 0 +ADDR_SURF_MACRO_ASPECT_2 = 1 +ADDR_SURF_MACRO_ASPECT_4 = 2 +ADDR_SURF_MACRO_ASPECT_8 = 3 +MacroTileAspect = ctypes.c_uint32 # enum + +# values for enumeration 'PipeTiling' +PipeTiling__enumvalues = { + 0: 'CONFIG_1_PIPE', + 1: 'CONFIG_2_PIPE', + 2: 'CONFIG_4_PIPE', + 3: 'CONFIG_8_PIPE', +} +CONFIG_1_PIPE = 0 +CONFIG_2_PIPE = 1 +CONFIG_4_PIPE = 2 +CONFIG_8_PIPE = 3 +PipeTiling = ctypes.c_uint32 # enum + +# values for enumeration 'BankTiling' +BankTiling__enumvalues = { + 0: 'CONFIG_4_BANK', + 1: 'CONFIG_8_BANK', +} +CONFIG_4_BANK = 0 +CONFIG_8_BANK = 1 +BankTiling = ctypes.c_uint32 # enum + +# values for enumeration 'GroupInterleave' +GroupInterleave__enumvalues = { + 0: 'CONFIG_256B_GROUP', + 1: 'CONFIG_512B_GROUP', +} +CONFIG_256B_GROUP = 0 +CONFIG_512B_GROUP = 1 +GroupInterleave = ctypes.c_uint32 # enum + +# values for enumeration 'RowTiling' +RowTiling__enumvalues = { + 0: 'CONFIG_1KB_ROW', + 1: 'CONFIG_2KB_ROW', + 2: 'CONFIG_4KB_ROW', + 3: 'CONFIG_8KB_ROW', + 4: 'CONFIG_1KB_ROW_OPT', + 5: 'CONFIG_2KB_ROW_OPT', + 6: 'CONFIG_4KB_ROW_OPT', + 7: 'CONFIG_8KB_ROW_OPT', +} +CONFIG_1KB_ROW = 0 +CONFIG_2KB_ROW = 1 +CONFIG_4KB_ROW = 2 +CONFIG_8KB_ROW = 3 +CONFIG_1KB_ROW_OPT = 4 +CONFIG_2KB_ROW_OPT = 5 +CONFIG_4KB_ROW_OPT = 6 +CONFIG_8KB_ROW_OPT = 7 +RowTiling = ctypes.c_uint32 # enum + +# values for enumeration 'BankSwapBytes' +BankSwapBytes__enumvalues = { + 0: 'CONFIG_128B_SWAPS', + 1: 'CONFIG_256B_SWAPS', + 2: 'CONFIG_512B_SWAPS', + 3: 'CONFIG_1KB_SWAPS', +} +CONFIG_128B_SWAPS = 0 +CONFIG_256B_SWAPS = 1 +CONFIG_512B_SWAPS = 2 +CONFIG_1KB_SWAPS = 3 +BankSwapBytes = ctypes.c_uint32 # enum + +# values for enumeration 'SampleSplitBytes' +SampleSplitBytes__enumvalues = { + 0: 'CONFIG_1KB_SPLIT', + 1: 'CONFIG_2KB_SPLIT', + 2: 'CONFIG_4KB_SPLIT', + 3: 'CONFIG_8KB_SPLIT', +} +CONFIG_1KB_SPLIT = 0 +CONFIG_2KB_SPLIT = 1 +CONFIG_4KB_SPLIT = 2 +CONFIG_8KB_SPLIT = 3 +SampleSplitBytes = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceNumber' +SurfaceNumber__enumvalues = { + 0: 'NUMBER_UNORM', + 1: 'NUMBER_SNORM', + 2: 'NUMBER_USCALED', + 3: 'NUMBER_SSCALED', + 4: 'NUMBER_UINT', + 5: 'NUMBER_SINT', + 6: 'NUMBER_SRGB', + 7: 'NUMBER_FLOAT', +} +NUMBER_UNORM = 0 +NUMBER_SNORM = 1 +NUMBER_USCALED = 2 +NUMBER_SSCALED = 3 +NUMBER_UINT = 4 +NUMBER_SINT = 5 +NUMBER_SRGB = 6 +NUMBER_FLOAT = 7 +SurfaceNumber = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceSwap' +SurfaceSwap__enumvalues = { + 0: 'SWAP_STD', + 1: 'SWAP_ALT', + 2: 'SWAP_STD_REV', + 3: 'SWAP_ALT_REV', +} +SWAP_STD = 0 +SWAP_ALT = 1 +SWAP_STD_REV = 2 +SWAP_ALT_REV = 3 +SurfaceSwap = ctypes.c_uint32 # enum + +# values for enumeration 'RoundMode' +RoundMode__enumvalues = { + 0: 'ROUND_BY_HALF', + 1: 'ROUND_TRUNCATE', +} +ROUND_BY_HALF = 0 +ROUND_TRUNCATE = 1 +RoundMode = ctypes.c_uint32 # enum + +# values for enumeration 'BUF_FMT' +BUF_FMT__enumvalues = { + 0: 'BUF_FMT_INVALID', + 1: 'BUF_FMT_8_UNORM', + 2: 'BUF_FMT_8_SNORM', + 3: 'BUF_FMT_8_USCALED', + 4: 'BUF_FMT_8_SSCALED', + 5: 'BUF_FMT_8_UINT', + 6: 'BUF_FMT_8_SINT', + 7: 'BUF_FMT_16_UNORM', + 8: 'BUF_FMT_16_SNORM', + 9: 'BUF_FMT_16_USCALED', + 10: 'BUF_FMT_16_SSCALED', + 11: 'BUF_FMT_16_UINT', + 12: 'BUF_FMT_16_SINT', + 13: 'BUF_FMT_16_FLOAT', + 14: 'BUF_FMT_8_8_UNORM', + 15: 'BUF_FMT_8_8_SNORM', + 16: 'BUF_FMT_8_8_USCALED', + 17: 'BUF_FMT_8_8_SSCALED', + 18: 'BUF_FMT_8_8_UINT', + 19: 'BUF_FMT_8_8_SINT', + 20: 'BUF_FMT_32_UINT', + 21: 'BUF_FMT_32_SINT', + 22: 'BUF_FMT_32_FLOAT', + 23: 'BUF_FMT_16_16_UNORM', + 24: 'BUF_FMT_16_16_SNORM', + 25: 'BUF_FMT_16_16_USCALED', + 26: 'BUF_FMT_16_16_SSCALED', + 27: 'BUF_FMT_16_16_UINT', + 28: 'BUF_FMT_16_16_SINT', + 29: 'BUF_FMT_16_16_FLOAT', + 30: 'BUF_FMT_10_11_11_UNORM', + 31: 'BUF_FMT_10_11_11_SNORM', + 32: 'BUF_FMT_10_11_11_USCALED', + 33: 'BUF_FMT_10_11_11_SSCALED', + 34: 'BUF_FMT_10_11_11_UINT', + 35: 'BUF_FMT_10_11_11_SINT', + 36: 'BUF_FMT_10_11_11_FLOAT', + 37: 'BUF_FMT_11_11_10_UNORM', + 38: 'BUF_FMT_11_11_10_SNORM', + 39: 'BUF_FMT_11_11_10_USCALED', + 40: 'BUF_FMT_11_11_10_SSCALED', + 41: 'BUF_FMT_11_11_10_UINT', + 42: 'BUF_FMT_11_11_10_SINT', + 43: 'BUF_FMT_11_11_10_FLOAT', + 44: 'BUF_FMT_10_10_10_2_UNORM', + 45: 'BUF_FMT_10_10_10_2_SNORM', + 46: 'BUF_FMT_10_10_10_2_USCALED', + 47: 'BUF_FMT_10_10_10_2_SSCALED', + 48: 'BUF_FMT_10_10_10_2_UINT', + 49: 'BUF_FMT_10_10_10_2_SINT', + 50: 'BUF_FMT_2_10_10_10_UNORM', + 51: 'BUF_FMT_2_10_10_10_SNORM', + 52: 'BUF_FMT_2_10_10_10_USCALED', + 53: 'BUF_FMT_2_10_10_10_SSCALED', + 54: 'BUF_FMT_2_10_10_10_UINT', + 55: 'BUF_FMT_2_10_10_10_SINT', + 56: 'BUF_FMT_8_8_8_8_UNORM', + 57: 'BUF_FMT_8_8_8_8_SNORM', + 58: 'BUF_FMT_8_8_8_8_USCALED', + 59: 'BUF_FMT_8_8_8_8_SSCALED', + 60: 'BUF_FMT_8_8_8_8_UINT', + 61: 'BUF_FMT_8_8_8_8_SINT', + 62: 'BUF_FMT_32_32_UINT', + 63: 'BUF_FMT_32_32_SINT', + 64: 'BUF_FMT_32_32_FLOAT', + 65: 'BUF_FMT_16_16_16_16_UNORM', + 66: 'BUF_FMT_16_16_16_16_SNORM', + 67: 'BUF_FMT_16_16_16_16_USCALED', + 68: 'BUF_FMT_16_16_16_16_SSCALED', + 69: 'BUF_FMT_16_16_16_16_UINT', + 70: 'BUF_FMT_16_16_16_16_SINT', + 71: 'BUF_FMT_16_16_16_16_FLOAT', + 72: 'BUF_FMT_32_32_32_UINT', + 73: 'BUF_FMT_32_32_32_SINT', + 74: 'BUF_FMT_32_32_32_FLOAT', + 75: 'BUF_FMT_32_32_32_32_UINT', + 76: 'BUF_FMT_32_32_32_32_SINT', + 77: 'BUF_FMT_32_32_32_32_FLOAT', + 78: 'BUF_FMT_RESERVED_78', + 79: 'BUF_FMT_RESERVED_79', + 80: 'BUF_FMT_RESERVED_80', + 81: 'BUF_FMT_RESERVED_81', + 82: 'BUF_FMT_RESERVED_82', + 83: 'BUF_FMT_RESERVED_83', + 84: 'BUF_FMT_RESERVED_84', + 85: 'BUF_FMT_RESERVED_85', + 86: 'BUF_FMT_RESERVED_86', + 87: 'BUF_FMT_RESERVED_87', + 88: 'BUF_FMT_RESERVED_88', + 89: 'BUF_FMT_RESERVED_89', + 90: 'BUF_FMT_RESERVED_90', + 91: 'BUF_FMT_RESERVED_91', + 92: 'BUF_FMT_RESERVED_92', + 93: 'BUF_FMT_RESERVED_93', + 94: 'BUF_FMT_RESERVED_94', + 95: 'BUF_FMT_RESERVED_95', + 96: 'BUF_FMT_RESERVED_96', + 97: 'BUF_FMT_RESERVED_97', + 98: 'BUF_FMT_RESERVED_98', + 99: 'BUF_FMT_RESERVED_99', + 100: 'BUF_FMT_RESERVED_100', + 101: 'BUF_FMT_RESERVED_101', + 102: 'BUF_FMT_RESERVED_102', + 103: 'BUF_FMT_RESERVED_103', + 104: 'BUF_FMT_RESERVED_104', + 105: 'BUF_FMT_RESERVED_105', + 106: 'BUF_FMT_RESERVED_106', + 107: 'BUF_FMT_RESERVED_107', + 108: 'BUF_FMT_RESERVED_108', + 109: 'BUF_FMT_RESERVED_109', + 110: 'BUF_FMT_RESERVED_110', + 111: 'BUF_FMT_RESERVED_111', + 112: 'BUF_FMT_RESERVED_112', + 113: 'BUF_FMT_RESERVED_113', + 114: 'BUF_FMT_RESERVED_114', + 115: 'BUF_FMT_RESERVED_115', + 116: 'BUF_FMT_RESERVED_116', + 117: 'BUF_FMT_RESERVED_117', + 118: 'BUF_FMT_RESERVED_118', + 119: 'BUF_FMT_RESERVED_119', + 120: 'BUF_FMT_RESERVED_120', + 121: 'BUF_FMT_RESERVED_121', + 122: 'BUF_FMT_RESERVED_122', + 123: 'BUF_FMT_RESERVED_123', + 124: 'BUF_FMT_RESERVED_124', + 125: 'BUF_FMT_RESERVED_125', + 126: 'BUF_FMT_RESERVED_126', + 127: 'BUF_FMT_RESERVED_127', +} +BUF_FMT_INVALID = 0 +BUF_FMT_8_UNORM = 1 +BUF_FMT_8_SNORM = 2 +BUF_FMT_8_USCALED = 3 +BUF_FMT_8_SSCALED = 4 +BUF_FMT_8_UINT = 5 +BUF_FMT_8_SINT = 6 +BUF_FMT_16_UNORM = 7 +BUF_FMT_16_SNORM = 8 +BUF_FMT_16_USCALED = 9 +BUF_FMT_16_SSCALED = 10 +BUF_FMT_16_UINT = 11 +BUF_FMT_16_SINT = 12 +BUF_FMT_16_FLOAT = 13 +BUF_FMT_8_8_UNORM = 14 +BUF_FMT_8_8_SNORM = 15 +BUF_FMT_8_8_USCALED = 16 +BUF_FMT_8_8_SSCALED = 17 +BUF_FMT_8_8_UINT = 18 +BUF_FMT_8_8_SINT = 19 +BUF_FMT_32_UINT = 20 +BUF_FMT_32_SINT = 21 +BUF_FMT_32_FLOAT = 22 +BUF_FMT_16_16_UNORM = 23 +BUF_FMT_16_16_SNORM = 24 +BUF_FMT_16_16_USCALED = 25 +BUF_FMT_16_16_SSCALED = 26 +BUF_FMT_16_16_UINT = 27 +BUF_FMT_16_16_SINT = 28 +BUF_FMT_16_16_FLOAT = 29 +BUF_FMT_10_11_11_UNORM = 30 +BUF_FMT_10_11_11_SNORM = 31 +BUF_FMT_10_11_11_USCALED = 32 +BUF_FMT_10_11_11_SSCALED = 33 +BUF_FMT_10_11_11_UINT = 34 +BUF_FMT_10_11_11_SINT = 35 +BUF_FMT_10_11_11_FLOAT = 36 +BUF_FMT_11_11_10_UNORM = 37 +BUF_FMT_11_11_10_SNORM = 38 +BUF_FMT_11_11_10_USCALED = 39 +BUF_FMT_11_11_10_SSCALED = 40 +BUF_FMT_11_11_10_UINT = 41 +BUF_FMT_11_11_10_SINT = 42 +BUF_FMT_11_11_10_FLOAT = 43 +BUF_FMT_10_10_10_2_UNORM = 44 +BUF_FMT_10_10_10_2_SNORM = 45 +BUF_FMT_10_10_10_2_USCALED = 46 +BUF_FMT_10_10_10_2_SSCALED = 47 +BUF_FMT_10_10_10_2_UINT = 48 +BUF_FMT_10_10_10_2_SINT = 49 +BUF_FMT_2_10_10_10_UNORM = 50 +BUF_FMT_2_10_10_10_SNORM = 51 +BUF_FMT_2_10_10_10_USCALED = 52 +BUF_FMT_2_10_10_10_SSCALED = 53 +BUF_FMT_2_10_10_10_UINT = 54 +BUF_FMT_2_10_10_10_SINT = 55 +BUF_FMT_8_8_8_8_UNORM = 56 +BUF_FMT_8_8_8_8_SNORM = 57 +BUF_FMT_8_8_8_8_USCALED = 58 +BUF_FMT_8_8_8_8_SSCALED = 59 +BUF_FMT_8_8_8_8_UINT = 60 +BUF_FMT_8_8_8_8_SINT = 61 +BUF_FMT_32_32_UINT = 62 +BUF_FMT_32_32_SINT = 63 +BUF_FMT_32_32_FLOAT = 64 +BUF_FMT_16_16_16_16_UNORM = 65 +BUF_FMT_16_16_16_16_SNORM = 66 +BUF_FMT_16_16_16_16_USCALED = 67 +BUF_FMT_16_16_16_16_SSCALED = 68 +BUF_FMT_16_16_16_16_UINT = 69 +BUF_FMT_16_16_16_16_SINT = 70 +BUF_FMT_16_16_16_16_FLOAT = 71 +BUF_FMT_32_32_32_UINT = 72 +BUF_FMT_32_32_32_SINT = 73 +BUF_FMT_32_32_32_FLOAT = 74 +BUF_FMT_32_32_32_32_UINT = 75 +BUF_FMT_32_32_32_32_SINT = 76 +BUF_FMT_32_32_32_32_FLOAT = 77 +BUF_FMT_RESERVED_78 = 78 +BUF_FMT_RESERVED_79 = 79 +BUF_FMT_RESERVED_80 = 80 +BUF_FMT_RESERVED_81 = 81 +BUF_FMT_RESERVED_82 = 82 +BUF_FMT_RESERVED_83 = 83 +BUF_FMT_RESERVED_84 = 84 +BUF_FMT_RESERVED_85 = 85 +BUF_FMT_RESERVED_86 = 86 +BUF_FMT_RESERVED_87 = 87 +BUF_FMT_RESERVED_88 = 88 +BUF_FMT_RESERVED_89 = 89 +BUF_FMT_RESERVED_90 = 90 +BUF_FMT_RESERVED_91 = 91 +BUF_FMT_RESERVED_92 = 92 +BUF_FMT_RESERVED_93 = 93 +BUF_FMT_RESERVED_94 = 94 +BUF_FMT_RESERVED_95 = 95 +BUF_FMT_RESERVED_96 = 96 +BUF_FMT_RESERVED_97 = 97 +BUF_FMT_RESERVED_98 = 98 +BUF_FMT_RESERVED_99 = 99 +BUF_FMT_RESERVED_100 = 100 +BUF_FMT_RESERVED_101 = 101 +BUF_FMT_RESERVED_102 = 102 +BUF_FMT_RESERVED_103 = 103 +BUF_FMT_RESERVED_104 = 104 +BUF_FMT_RESERVED_105 = 105 +BUF_FMT_RESERVED_106 = 106 +BUF_FMT_RESERVED_107 = 107 +BUF_FMT_RESERVED_108 = 108 +BUF_FMT_RESERVED_109 = 109 +BUF_FMT_RESERVED_110 = 110 +BUF_FMT_RESERVED_111 = 111 +BUF_FMT_RESERVED_112 = 112 +BUF_FMT_RESERVED_113 = 113 +BUF_FMT_RESERVED_114 = 114 +BUF_FMT_RESERVED_115 = 115 +BUF_FMT_RESERVED_116 = 116 +BUF_FMT_RESERVED_117 = 117 +BUF_FMT_RESERVED_118 = 118 +BUF_FMT_RESERVED_119 = 119 +BUF_FMT_RESERVED_120 = 120 +BUF_FMT_RESERVED_121 = 121 +BUF_FMT_RESERVED_122 = 122 +BUF_FMT_RESERVED_123 = 123 +BUF_FMT_RESERVED_124 = 124 +BUF_FMT_RESERVED_125 = 125 +BUF_FMT_RESERVED_126 = 126 +BUF_FMT_RESERVED_127 = 127 +BUF_FMT = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_FMT' +IMG_FMT__enumvalues = { + 0: 'IMG_FMT_INVALID', + 1: 'IMG_FMT_8_UNORM', + 2: 'IMG_FMT_8_SNORM', + 3: 'IMG_FMT_8_USCALED', + 4: 'IMG_FMT_8_SSCALED', + 5: 'IMG_FMT_8_UINT', + 6: 'IMG_FMT_8_SINT', + 7: 'IMG_FMT_16_UNORM', + 8: 'IMG_FMT_16_SNORM', + 9: 'IMG_FMT_16_USCALED', + 10: 'IMG_FMT_16_SSCALED', + 11: 'IMG_FMT_16_UINT', + 12: 'IMG_FMT_16_SINT', + 13: 'IMG_FMT_16_FLOAT', + 14: 'IMG_FMT_8_8_UNORM', + 15: 'IMG_FMT_8_8_SNORM', + 16: 'IMG_FMT_8_8_USCALED', + 17: 'IMG_FMT_8_8_SSCALED', + 18: 'IMG_FMT_8_8_UINT', + 19: 'IMG_FMT_8_8_SINT', + 20: 'IMG_FMT_32_UINT', + 21: 'IMG_FMT_32_SINT', + 22: 'IMG_FMT_32_FLOAT', + 23: 'IMG_FMT_16_16_UNORM', + 24: 'IMG_FMT_16_16_SNORM', + 25: 'IMG_FMT_16_16_USCALED', + 26: 'IMG_FMT_16_16_SSCALED', + 27: 'IMG_FMT_16_16_UINT', + 28: 'IMG_FMT_16_16_SINT', + 29: 'IMG_FMT_16_16_FLOAT', + 30: 'IMG_FMT_10_11_11_UNORM', + 31: 'IMG_FMT_10_11_11_SNORM', + 32: 'IMG_FMT_10_11_11_USCALED', + 33: 'IMG_FMT_10_11_11_SSCALED', + 34: 'IMG_FMT_10_11_11_UINT', + 35: 'IMG_FMT_10_11_11_SINT', + 36: 'IMG_FMT_10_11_11_FLOAT', + 37: 'IMG_FMT_11_11_10_UNORM', + 38: 'IMG_FMT_11_11_10_SNORM', + 39: 'IMG_FMT_11_11_10_USCALED', + 40: 'IMG_FMT_11_11_10_SSCALED', + 41: 'IMG_FMT_11_11_10_UINT', + 42: 'IMG_FMT_11_11_10_SINT', + 43: 'IMG_FMT_11_11_10_FLOAT', + 44: 'IMG_FMT_10_10_10_2_UNORM', + 45: 'IMG_FMT_10_10_10_2_SNORM', + 46: 'IMG_FMT_10_10_10_2_USCALED', + 47: 'IMG_FMT_10_10_10_2_SSCALED', + 48: 'IMG_FMT_10_10_10_2_UINT', + 49: 'IMG_FMT_10_10_10_2_SINT', + 50: 'IMG_FMT_2_10_10_10_UNORM', + 51: 'IMG_FMT_2_10_10_10_SNORM', + 52: 'IMG_FMT_2_10_10_10_USCALED', + 53: 'IMG_FMT_2_10_10_10_SSCALED', + 54: 'IMG_FMT_2_10_10_10_UINT', + 55: 'IMG_FMT_2_10_10_10_SINT', + 56: 'IMG_FMT_8_8_8_8_UNORM', + 57: 'IMG_FMT_8_8_8_8_SNORM', + 58: 'IMG_FMT_8_8_8_8_USCALED', + 59: 'IMG_FMT_8_8_8_8_SSCALED', + 60: 'IMG_FMT_8_8_8_8_UINT', + 61: 'IMG_FMT_8_8_8_8_SINT', + 62: 'IMG_FMT_32_32_UINT', + 63: 'IMG_FMT_32_32_SINT', + 64: 'IMG_FMT_32_32_FLOAT', + 65: 'IMG_FMT_16_16_16_16_UNORM', + 66: 'IMG_FMT_16_16_16_16_SNORM', + 67: 'IMG_FMT_16_16_16_16_USCALED', + 68: 'IMG_FMT_16_16_16_16_SSCALED', + 69: 'IMG_FMT_16_16_16_16_UINT', + 70: 'IMG_FMT_16_16_16_16_SINT', + 71: 'IMG_FMT_16_16_16_16_FLOAT', + 72: 'IMG_FMT_32_32_32_UINT', + 73: 'IMG_FMT_32_32_32_SINT', + 74: 'IMG_FMT_32_32_32_FLOAT', + 75: 'IMG_FMT_32_32_32_32_UINT', + 76: 'IMG_FMT_32_32_32_32_SINT', + 77: 'IMG_FMT_32_32_32_32_FLOAT', + 78: 'IMG_FMT_RESERVED_78', + 79: 'IMG_FMT_RESERVED_79', + 80: 'IMG_FMT_RESERVED_80', + 81: 'IMG_FMT_RESERVED_81', + 82: 'IMG_FMT_RESERVED_82', + 83: 'IMG_FMT_RESERVED_83', + 84: 'IMG_FMT_RESERVED_84', + 85: 'IMG_FMT_RESERVED_85', + 86: 'IMG_FMT_RESERVED_86', + 87: 'IMG_FMT_RESERVED_87', + 88: 'IMG_FMT_RESERVED_88', + 89: 'IMG_FMT_RESERVED_89', + 90: 'IMG_FMT_RESERVED_90', + 91: 'IMG_FMT_RESERVED_91', + 92: 'IMG_FMT_RESERVED_92', + 93: 'IMG_FMT_RESERVED_93', + 94: 'IMG_FMT_RESERVED_94', + 95: 'IMG_FMT_RESERVED_95', + 96: 'IMG_FMT_RESERVED_96', + 97: 'IMG_FMT_RESERVED_97', + 98: 'IMG_FMT_RESERVED_98', + 99: 'IMG_FMT_RESERVED_99', + 100: 'IMG_FMT_RESERVED_100', + 101: 'IMG_FMT_RESERVED_101', + 102: 'IMG_FMT_RESERVED_102', + 103: 'IMG_FMT_RESERVED_103', + 104: 'IMG_FMT_RESERVED_104', + 105: 'IMG_FMT_RESERVED_105', + 106: 'IMG_FMT_RESERVED_106', + 107: 'IMG_FMT_RESERVED_107', + 108: 'IMG_FMT_RESERVED_108', + 109: 'IMG_FMT_RESERVED_109', + 110: 'IMG_FMT_RESERVED_110', + 111: 'IMG_FMT_RESERVED_111', + 112: 'IMG_FMT_RESERVED_112', + 113: 'IMG_FMT_RESERVED_113', + 114: 'IMG_FMT_RESERVED_114', + 115: 'IMG_FMT_RESERVED_115', + 116: 'IMG_FMT_RESERVED_116', + 117: 'IMG_FMT_RESERVED_117', + 118: 'IMG_FMT_RESERVED_118', + 119: 'IMG_FMT_RESERVED_119', + 120: 'IMG_FMT_RESERVED_120', + 121: 'IMG_FMT_RESERVED_121', + 122: 'IMG_FMT_RESERVED_122', + 123: 'IMG_FMT_RESERVED_123', + 124: 'IMG_FMT_RESERVED_124', + 125: 'IMG_FMT_RESERVED_125', + 126: 'IMG_FMT_RESERVED_126', + 127: 'IMG_FMT_RESERVED_127', + 128: 'IMG_FMT_8_SRGB', + 129: 'IMG_FMT_8_8_SRGB', + 130: 'IMG_FMT_8_8_8_8_SRGB', + 131: 'IMG_FMT_6E4_FLOAT', + 132: 'IMG_FMT_5_9_9_9_FLOAT', + 133: 'IMG_FMT_5_6_5_UNORM', + 134: 'IMG_FMT_1_5_5_5_UNORM', + 135: 'IMG_FMT_5_5_5_1_UNORM', + 136: 'IMG_FMT_4_4_4_4_UNORM', + 137: 'IMG_FMT_4_4_UNORM', + 138: 'IMG_FMT_1_UNORM', + 139: 'IMG_FMT_1_REVERSED_UNORM', + 140: 'IMG_FMT_32_FLOAT_CLAMP', + 141: 'IMG_FMT_8_24_UNORM', + 142: 'IMG_FMT_8_24_UINT', + 143: 'IMG_FMT_24_8_UNORM', + 144: 'IMG_FMT_24_8_UINT', + 145: 'IMG_FMT_X24_8_32_UINT', + 146: 'IMG_FMT_X24_8_32_FLOAT', + 147: 'IMG_FMT_GB_GR_UNORM', + 148: 'IMG_FMT_GB_GR_SNORM', + 149: 'IMG_FMT_GB_GR_UINT', + 150: 'IMG_FMT_GB_GR_SRGB', + 151: 'IMG_FMT_BG_RG_UNORM', + 152: 'IMG_FMT_BG_RG_SNORM', + 153: 'IMG_FMT_BG_RG_UINT', + 154: 'IMG_FMT_BG_RG_SRGB', + 155: 'IMG_FMT_RESERVED_155', + 156: 'IMG_FMT_FMASK8_S2_F1', + 157: 'IMG_FMT_FMASK8_S4_F1', + 158: 'IMG_FMT_FMASK8_S8_F1', + 159: 'IMG_FMT_FMASK8_S2_F2', + 160: 'IMG_FMT_FMASK8_S4_F2', + 161: 'IMG_FMT_FMASK8_S4_F4', + 162: 'IMG_FMT_FMASK16_S16_F1', + 163: 'IMG_FMT_FMASK16_S8_F2', + 164: 'IMG_FMT_FMASK32_S16_F2', + 165: 'IMG_FMT_FMASK32_S8_F4', + 166: 'IMG_FMT_FMASK32_S8_F8', + 167: 'IMG_FMT_FMASK64_S16_F4', + 168: 'IMG_FMT_FMASK64_S16_F8', + 169: 'IMG_FMT_BC1_UNORM', + 170: 'IMG_FMT_BC1_SRGB', + 171: 'IMG_FMT_BC2_UNORM', + 172: 'IMG_FMT_BC2_SRGB', + 173: 'IMG_FMT_BC3_UNORM', + 174: 'IMG_FMT_BC3_SRGB', + 175: 'IMG_FMT_BC4_UNORM', + 176: 'IMG_FMT_BC4_SNORM', + 177: 'IMG_FMT_BC5_UNORM', + 178: 'IMG_FMT_BC5_SNORM', + 179: 'IMG_FMT_BC6_UFLOAT', + 180: 'IMG_FMT_BC6_SFLOAT', + 181: 'IMG_FMT_BC7_UNORM', + 182: 'IMG_FMT_BC7_SRGB', + 265: 'IMG_FMT_MM_8_UNORM', + 266: 'IMG_FMT_MM_8_UINT', + 267: 'IMG_FMT_MM_8_8_UNORM', + 268: 'IMG_FMT_MM_8_8_UINT', + 269: 'IMG_FMT_MM_8_8_8_8_UNORM', + 270: 'IMG_FMT_MM_8_8_8_8_UINT', + 271: 'IMG_FMT_MM_VYUY8_UNORM', + 272: 'IMG_FMT_MM_VYUY8_UINT', + 273: 'IMG_FMT_MM_10_11_11_UNORM', + 274: 'IMG_FMT_MM_10_11_11_UINT', + 275: 'IMG_FMT_MM_2_10_10_10_UNORM', + 276: 'IMG_FMT_MM_2_10_10_10_UINT', + 277: 'IMG_FMT_MM_16_16_16_16_UNORM', + 278: 'IMG_FMT_MM_16_16_16_16_UINT', + 279: 'IMG_FMT_MM_10_IN_16_UNORM', + 280: 'IMG_FMT_MM_10_IN_16_UINT', + 281: 'IMG_FMT_MM_10_IN_16_16_UNORM', + 282: 'IMG_FMT_MM_10_IN_16_16_UINT', + 283: 'IMG_FMT_MM_10_IN_16_16_16_16_UNORM', + 284: 'IMG_FMT_MM_10_IN_16_16_16_16_UINT', + 285: 'IMG_FMT_RESERVED_285', + 286: 'IMG_FMT_RESERVED_286', + 287: 'IMG_FMT_RESERVED_287', + 288: 'IMG_FMT_RESERVED_288', + 289: 'IMG_FMT_RESERVED_289', + 290: 'IMG_FMT_RESERVED_290', + 291: 'IMG_FMT_RESERVED_291', + 292: 'IMG_FMT_RESERVED_292', + 293: 'IMG_FMT_RESERVED_293', + 294: 'IMG_FMT_RESERVED_294', + 295: 'IMG_FMT_RESERVED_295', + 296: 'IMG_FMT_RESERVED_296', + 297: 'IMG_FMT_RESERVED_297', + 298: 'IMG_FMT_RESERVED_298', + 299: 'IMG_FMT_RESERVED_299', + 300: 'IMG_FMT_RESERVED_300', + 301: 'IMG_FMT_RESERVED_301', + 302: 'IMG_FMT_RESERVED_302', + 303: 'IMG_FMT_RESERVED_303', + 304: 'IMG_FMT_RESERVED_304', + 305: 'IMG_FMT_RESERVED_305', + 306: 'IMG_FMT_RESERVED_306', + 307: 'IMG_FMT_RESERVED_307', + 308: 'IMG_FMT_RESERVED_308', + 309: 'IMG_FMT_RESERVED_309', + 310: 'IMG_FMT_RESERVED_310', + 311: 'IMG_FMT_RESERVED_311', + 312: 'IMG_FMT_RESERVED_312', + 313: 'IMG_FMT_RESERVED_313', + 314: 'IMG_FMT_RESERVED_314', + 315: 'IMG_FMT_RESERVED_315', + 316: 'IMG_FMT_RESERVED_316', + 317: 'IMG_FMT_RESERVED_317', + 318: 'IMG_FMT_RESERVED_318', + 319: 'IMG_FMT_RESERVED_319', + 320: 'IMG_FMT_RESERVED_320', + 321: 'IMG_FMT_RESERVED_321', + 322: 'IMG_FMT_RESERVED_322', + 323: 'IMG_FMT_RESERVED_323', + 324: 'IMG_FMT_RESERVED_324', + 325: 'IMG_FMT_RESERVED_325', + 326: 'IMG_FMT_RESERVED_326', + 327: 'IMG_FMT_RESERVED_327', + 328: 'IMG_FMT_RESERVED_328', + 329: 'IMG_FMT_RESERVED_329', + 330: 'IMG_FMT_RESERVED_330', + 331: 'IMG_FMT_RESERVED_331', + 332: 'IMG_FMT_RESERVED_332', + 333: 'IMG_FMT_RESERVED_333', + 334: 'IMG_FMT_RESERVED_334', + 335: 'IMG_FMT_RESERVED_335', + 336: 'IMG_FMT_RESERVED_336', + 337: 'IMG_FMT_RESERVED_337', + 338: 'IMG_FMT_RESERVED_338', + 339: 'IMG_FMT_RESERVED_339', + 340: 'IMG_FMT_RESERVED_340', + 341: 'IMG_FMT_RESERVED_341', + 342: 'IMG_FMT_RESERVED_342', + 343: 'IMG_FMT_RESERVED_343', + 344: 'IMG_FMT_RESERVED_344', + 345: 'IMG_FMT_RESERVED_345', + 346: 'IMG_FMT_RESERVED_346', + 347: 'IMG_FMT_RESERVED_347', + 348: 'IMG_FMT_RESERVED_348', + 349: 'IMG_FMT_RESERVED_349', + 350: 'IMG_FMT_RESERVED_350', + 351: 'IMG_FMT_RESERVED_351', + 352: 'IMG_FMT_RESERVED_352', + 353: 'IMG_FMT_RESERVED_353', + 354: 'IMG_FMT_RESERVED_354', + 355: 'IMG_FMT_RESERVED_355', + 356: 'IMG_FMT_RESERVED_356', + 357: 'IMG_FMT_RESERVED_357', + 358: 'IMG_FMT_RESERVED_358', + 359: 'IMG_FMT_RESERVED_359', + 360: 'IMG_FMT_RESERVED_360', + 361: 'IMG_FMT_RESERVED_361', + 362: 'IMG_FMT_RESERVED_362', + 363: 'IMG_FMT_RESERVED_363', + 364: 'IMG_FMT_RESERVED_364', + 365: 'IMG_FMT_RESERVED_365', + 366: 'IMG_FMT_RESERVED_366', + 367: 'IMG_FMT_RESERVED_367', + 368: 'IMG_FMT_RESERVED_368', + 369: 'IMG_FMT_RESERVED_369', + 370: 'IMG_FMT_RESERVED_370', + 371: 'IMG_FMT_RESERVED_371', + 372: 'IMG_FMT_RESERVED_372', + 373: 'IMG_FMT_RESERVED_373', + 374: 'IMG_FMT_RESERVED_374', + 375: 'IMG_FMT_RESERVED_375', + 376: 'IMG_FMT_RESERVED_376', + 377: 'IMG_FMT_RESERVED_377', + 378: 'IMG_FMT_RESERVED_378', + 379: 'IMG_FMT_RESERVED_379', + 380: 'IMG_FMT_RESERVED_380', + 381: 'IMG_FMT_RESERVED_381', + 382: 'IMG_FMT_RESERVED_382', + 383: 'IMG_FMT_RESERVED_383', + 384: 'IMG_FMT_RESERVED_384', + 385: 'IMG_FMT_RESERVED_385', + 386: 'IMG_FMT_RESERVED_386', + 387: 'IMG_FMT_RESERVED_387', + 388: 'IMG_FMT_RESERVED_388', + 389: 'IMG_FMT_RESERVED_389', + 390: 'IMG_FMT_RESERVED_390', + 391: 'IMG_FMT_RESERVED_391', + 392: 'IMG_FMT_RESERVED_392', + 393: 'IMG_FMT_RESERVED_393', + 394: 'IMG_FMT_RESERVED_394', + 395: 'IMG_FMT_RESERVED_395', + 396: 'IMG_FMT_RESERVED_396', + 397: 'IMG_FMT_RESERVED_397', + 398: 'IMG_FMT_RESERVED_398', + 399: 'IMG_FMT_RESERVED_399', + 400: 'IMG_FMT_RESERVED_400', + 401: 'IMG_FMT_RESERVED_401', + 402: 'IMG_FMT_RESERVED_402', + 403: 'IMG_FMT_RESERVED_403', + 404: 'IMG_FMT_RESERVED_404', + 405: 'IMG_FMT_RESERVED_405', + 406: 'IMG_FMT_RESERVED_406', + 407: 'IMG_FMT_RESERVED_407', + 408: 'IMG_FMT_RESERVED_408', + 409: 'IMG_FMT_RESERVED_409', + 410: 'IMG_FMT_RESERVED_410', + 411: 'IMG_FMT_RESERVED_411', + 412: 'IMG_FMT_RESERVED_412', + 413: 'IMG_FMT_RESERVED_413', + 414: 'IMG_FMT_RESERVED_414', + 415: 'IMG_FMT_RESERVED_415', + 416: 'IMG_FMT_RESERVED_416', + 417: 'IMG_FMT_RESERVED_417', + 418: 'IMG_FMT_RESERVED_418', + 419: 'IMG_FMT_RESERVED_419', + 420: 'IMG_FMT_RESERVED_420', + 421: 'IMG_FMT_RESERVED_421', + 422: 'IMG_FMT_RESERVED_422', + 423: 'IMG_FMT_RESERVED_423', + 424: 'IMG_FMT_RESERVED_424', + 425: 'IMG_FMT_RESERVED_425', + 426: 'IMG_FMT_RESERVED_426', + 427: 'IMG_FMT_RESERVED_427', + 428: 'IMG_FMT_RESERVED_428', + 429: 'IMG_FMT_RESERVED_429', + 430: 'IMG_FMT_RESERVED_430', + 431: 'IMG_FMT_RESERVED_431', + 432: 'IMG_FMT_RESERVED_432', + 433: 'IMG_FMT_RESERVED_433', + 434: 'IMG_FMT_RESERVED_434', + 435: 'IMG_FMT_RESERVED_435', + 436: 'IMG_FMT_RESERVED_436', + 437: 'IMG_FMT_RESERVED_437', + 438: 'IMG_FMT_RESERVED_438', + 439: 'IMG_FMT_RESERVED_439', + 440: 'IMG_FMT_RESERVED_440', + 441: 'IMG_FMT_RESERVED_441', + 442: 'IMG_FMT_RESERVED_442', + 443: 'IMG_FMT_RESERVED_443', + 444: 'IMG_FMT_RESERVED_444', + 445: 'IMG_FMT_RESERVED_445', + 446: 'IMG_FMT_RESERVED_446', + 447: 'IMG_FMT_RESERVED_447', + 448: 'IMG_FMT_RESERVED_448', + 449: 'IMG_FMT_RESERVED_449', + 450: 'IMG_FMT_RESERVED_450', + 451: 'IMG_FMT_RESERVED_451', + 452: 'IMG_FMT_RESERVED_452', + 453: 'IMG_FMT_RESERVED_453', + 454: 'IMG_FMT_RESERVED_454', + 455: 'IMG_FMT_RESERVED_455', + 456: 'IMG_FMT_RESERVED_456', + 457: 'IMG_FMT_RESERVED_457', + 458: 'IMG_FMT_RESERVED_458', + 459: 'IMG_FMT_RESERVED_459', + 460: 'IMG_FMT_RESERVED_460', + 461: 'IMG_FMT_RESERVED_461', + 462: 'IMG_FMT_RESERVED_462', + 463: 'IMG_FMT_RESERVED_463', + 464: 'IMG_FMT_RESERVED_464', + 465: 'IMG_FMT_RESERVED_465', + 466: 'IMG_FMT_RESERVED_466', + 467: 'IMG_FMT_RESERVED_467', + 468: 'IMG_FMT_RESERVED_468', + 469: 'IMG_FMT_RESERVED_469', + 470: 'IMG_FMT_RESERVED_470', + 471: 'IMG_FMT_RESERVED_471', + 472: 'IMG_FMT_RESERVED_472', + 473: 'IMG_FMT_RESERVED_473', + 474: 'IMG_FMT_RESERVED_474', + 475: 'IMG_FMT_RESERVED_475', + 476: 'IMG_FMT_RESERVED_476', + 477: 'IMG_FMT_RESERVED_477', + 478: 'IMG_FMT_RESERVED_478', + 479: 'IMG_FMT_RESERVED_479', + 480: 'IMG_FMT_RESERVED_480', + 481: 'IMG_FMT_RESERVED_481', + 482: 'IMG_FMT_RESERVED_482', + 483: 'IMG_FMT_RESERVED_483', + 484: 'IMG_FMT_RESERVED_484', + 485: 'IMG_FMT_RESERVED_485', + 486: 'IMG_FMT_RESERVED_486', + 487: 'IMG_FMT_RESERVED_487', + 488: 'IMG_FMT_RESERVED_488', + 489: 'IMG_FMT_RESERVED_489', + 490: 'IMG_FMT_RESERVED_490', + 491: 'IMG_FMT_RESERVED_491', + 492: 'IMG_FMT_RESERVED_492', + 493: 'IMG_FMT_RESERVED_493', + 494: 'IMG_FMT_RESERVED_494', + 495: 'IMG_FMT_RESERVED_495', + 496: 'IMG_FMT_RESERVED_496', + 497: 'IMG_FMT_RESERVED_497', + 498: 'IMG_FMT_RESERVED_498', + 499: 'IMG_FMT_RESERVED_499', + 500: 'IMG_FMT_RESERVED_500', + 501: 'IMG_FMT_RESERVED_501', + 502: 'IMG_FMT_RESERVED_502', + 503: 'IMG_FMT_RESERVED_503', + 504: 'IMG_FMT_RESERVED_504', + 505: 'IMG_FMT_RESERVED_505', + 506: 'IMG_FMT_RESERVED_506', + 507: 'IMG_FMT_RESERVED_507', + 508: 'IMG_FMT_RESERVED_508', + 509: 'IMG_FMT_RESERVED_509', + 510: 'IMG_FMT_RESERVED_510', + 511: 'IMG_FMT_RESERVED_511', +} +IMG_FMT_INVALID = 0 +IMG_FMT_8_UNORM = 1 +IMG_FMT_8_SNORM = 2 +IMG_FMT_8_USCALED = 3 +IMG_FMT_8_SSCALED = 4 +IMG_FMT_8_UINT = 5 +IMG_FMT_8_SINT = 6 +IMG_FMT_16_UNORM = 7 +IMG_FMT_16_SNORM = 8 +IMG_FMT_16_USCALED = 9 +IMG_FMT_16_SSCALED = 10 +IMG_FMT_16_UINT = 11 +IMG_FMT_16_SINT = 12 +IMG_FMT_16_FLOAT = 13 +IMG_FMT_8_8_UNORM = 14 +IMG_FMT_8_8_SNORM = 15 +IMG_FMT_8_8_USCALED = 16 +IMG_FMT_8_8_SSCALED = 17 +IMG_FMT_8_8_UINT = 18 +IMG_FMT_8_8_SINT = 19 +IMG_FMT_32_UINT = 20 +IMG_FMT_32_SINT = 21 +IMG_FMT_32_FLOAT = 22 +IMG_FMT_16_16_UNORM = 23 +IMG_FMT_16_16_SNORM = 24 +IMG_FMT_16_16_USCALED = 25 +IMG_FMT_16_16_SSCALED = 26 +IMG_FMT_16_16_UINT = 27 +IMG_FMT_16_16_SINT = 28 +IMG_FMT_16_16_FLOAT = 29 +IMG_FMT_10_11_11_UNORM = 30 +IMG_FMT_10_11_11_SNORM = 31 +IMG_FMT_10_11_11_USCALED = 32 +IMG_FMT_10_11_11_SSCALED = 33 +IMG_FMT_10_11_11_UINT = 34 +IMG_FMT_10_11_11_SINT = 35 +IMG_FMT_10_11_11_FLOAT = 36 +IMG_FMT_11_11_10_UNORM = 37 +IMG_FMT_11_11_10_SNORM = 38 +IMG_FMT_11_11_10_USCALED = 39 +IMG_FMT_11_11_10_SSCALED = 40 +IMG_FMT_11_11_10_UINT = 41 +IMG_FMT_11_11_10_SINT = 42 +IMG_FMT_11_11_10_FLOAT = 43 +IMG_FMT_10_10_10_2_UNORM = 44 +IMG_FMT_10_10_10_2_SNORM = 45 +IMG_FMT_10_10_10_2_USCALED = 46 +IMG_FMT_10_10_10_2_SSCALED = 47 +IMG_FMT_10_10_10_2_UINT = 48 +IMG_FMT_10_10_10_2_SINT = 49 +IMG_FMT_2_10_10_10_UNORM = 50 +IMG_FMT_2_10_10_10_SNORM = 51 +IMG_FMT_2_10_10_10_USCALED = 52 +IMG_FMT_2_10_10_10_SSCALED = 53 +IMG_FMT_2_10_10_10_UINT = 54 +IMG_FMT_2_10_10_10_SINT = 55 +IMG_FMT_8_8_8_8_UNORM = 56 +IMG_FMT_8_8_8_8_SNORM = 57 +IMG_FMT_8_8_8_8_USCALED = 58 +IMG_FMT_8_8_8_8_SSCALED = 59 +IMG_FMT_8_8_8_8_UINT = 60 +IMG_FMT_8_8_8_8_SINT = 61 +IMG_FMT_32_32_UINT = 62 +IMG_FMT_32_32_SINT = 63 +IMG_FMT_32_32_FLOAT = 64 +IMG_FMT_16_16_16_16_UNORM = 65 +IMG_FMT_16_16_16_16_SNORM = 66 +IMG_FMT_16_16_16_16_USCALED = 67 +IMG_FMT_16_16_16_16_SSCALED = 68 +IMG_FMT_16_16_16_16_UINT = 69 +IMG_FMT_16_16_16_16_SINT = 70 +IMG_FMT_16_16_16_16_FLOAT = 71 +IMG_FMT_32_32_32_UINT = 72 +IMG_FMT_32_32_32_SINT = 73 +IMG_FMT_32_32_32_FLOAT = 74 +IMG_FMT_32_32_32_32_UINT = 75 +IMG_FMT_32_32_32_32_SINT = 76 +IMG_FMT_32_32_32_32_FLOAT = 77 +IMG_FMT_RESERVED_78 = 78 +IMG_FMT_RESERVED_79 = 79 +IMG_FMT_RESERVED_80 = 80 +IMG_FMT_RESERVED_81 = 81 +IMG_FMT_RESERVED_82 = 82 +IMG_FMT_RESERVED_83 = 83 +IMG_FMT_RESERVED_84 = 84 +IMG_FMT_RESERVED_85 = 85 +IMG_FMT_RESERVED_86 = 86 +IMG_FMT_RESERVED_87 = 87 +IMG_FMT_RESERVED_88 = 88 +IMG_FMT_RESERVED_89 = 89 +IMG_FMT_RESERVED_90 = 90 +IMG_FMT_RESERVED_91 = 91 +IMG_FMT_RESERVED_92 = 92 +IMG_FMT_RESERVED_93 = 93 +IMG_FMT_RESERVED_94 = 94 +IMG_FMT_RESERVED_95 = 95 +IMG_FMT_RESERVED_96 = 96 +IMG_FMT_RESERVED_97 = 97 +IMG_FMT_RESERVED_98 = 98 +IMG_FMT_RESERVED_99 = 99 +IMG_FMT_RESERVED_100 = 100 +IMG_FMT_RESERVED_101 = 101 +IMG_FMT_RESERVED_102 = 102 +IMG_FMT_RESERVED_103 = 103 +IMG_FMT_RESERVED_104 = 104 +IMG_FMT_RESERVED_105 = 105 +IMG_FMT_RESERVED_106 = 106 +IMG_FMT_RESERVED_107 = 107 +IMG_FMT_RESERVED_108 = 108 +IMG_FMT_RESERVED_109 = 109 +IMG_FMT_RESERVED_110 = 110 +IMG_FMT_RESERVED_111 = 111 +IMG_FMT_RESERVED_112 = 112 +IMG_FMT_RESERVED_113 = 113 +IMG_FMT_RESERVED_114 = 114 +IMG_FMT_RESERVED_115 = 115 +IMG_FMT_RESERVED_116 = 116 +IMG_FMT_RESERVED_117 = 117 +IMG_FMT_RESERVED_118 = 118 +IMG_FMT_RESERVED_119 = 119 +IMG_FMT_RESERVED_120 = 120 +IMG_FMT_RESERVED_121 = 121 +IMG_FMT_RESERVED_122 = 122 +IMG_FMT_RESERVED_123 = 123 +IMG_FMT_RESERVED_124 = 124 +IMG_FMT_RESERVED_125 = 125 +IMG_FMT_RESERVED_126 = 126 +IMG_FMT_RESERVED_127 = 127 +IMG_FMT_8_SRGB = 128 +IMG_FMT_8_8_SRGB = 129 +IMG_FMT_8_8_8_8_SRGB = 130 +IMG_FMT_6E4_FLOAT = 131 +IMG_FMT_5_9_9_9_FLOAT = 132 +IMG_FMT_5_6_5_UNORM = 133 +IMG_FMT_1_5_5_5_UNORM = 134 +IMG_FMT_5_5_5_1_UNORM = 135 +IMG_FMT_4_4_4_4_UNORM = 136 +IMG_FMT_4_4_UNORM = 137 +IMG_FMT_1_UNORM = 138 +IMG_FMT_1_REVERSED_UNORM = 139 +IMG_FMT_32_FLOAT_CLAMP = 140 +IMG_FMT_8_24_UNORM = 141 +IMG_FMT_8_24_UINT = 142 +IMG_FMT_24_8_UNORM = 143 +IMG_FMT_24_8_UINT = 144 +IMG_FMT_X24_8_32_UINT = 145 +IMG_FMT_X24_8_32_FLOAT = 146 +IMG_FMT_GB_GR_UNORM = 147 +IMG_FMT_GB_GR_SNORM = 148 +IMG_FMT_GB_GR_UINT = 149 +IMG_FMT_GB_GR_SRGB = 150 +IMG_FMT_BG_RG_UNORM = 151 +IMG_FMT_BG_RG_SNORM = 152 +IMG_FMT_BG_RG_UINT = 153 +IMG_FMT_BG_RG_SRGB = 154 +IMG_FMT_RESERVED_155 = 155 +IMG_FMT_FMASK8_S2_F1 = 156 +IMG_FMT_FMASK8_S4_F1 = 157 +IMG_FMT_FMASK8_S8_F1 = 158 +IMG_FMT_FMASK8_S2_F2 = 159 +IMG_FMT_FMASK8_S4_F2 = 160 +IMG_FMT_FMASK8_S4_F4 = 161 +IMG_FMT_FMASK16_S16_F1 = 162 +IMG_FMT_FMASK16_S8_F2 = 163 +IMG_FMT_FMASK32_S16_F2 = 164 +IMG_FMT_FMASK32_S8_F4 = 165 +IMG_FMT_FMASK32_S8_F8 = 166 +IMG_FMT_FMASK64_S16_F4 = 167 +IMG_FMT_FMASK64_S16_F8 = 168 +IMG_FMT_BC1_UNORM = 169 +IMG_FMT_BC1_SRGB = 170 +IMG_FMT_BC2_UNORM = 171 +IMG_FMT_BC2_SRGB = 172 +IMG_FMT_BC3_UNORM = 173 +IMG_FMT_BC3_SRGB = 174 +IMG_FMT_BC4_UNORM = 175 +IMG_FMT_BC4_SNORM = 176 +IMG_FMT_BC5_UNORM = 177 +IMG_FMT_BC5_SNORM = 178 +IMG_FMT_BC6_UFLOAT = 179 +IMG_FMT_BC6_SFLOAT = 180 +IMG_FMT_BC7_UNORM = 181 +IMG_FMT_BC7_SRGB = 182 +IMG_FMT_MM_8_UNORM = 265 +IMG_FMT_MM_8_UINT = 266 +IMG_FMT_MM_8_8_UNORM = 267 +IMG_FMT_MM_8_8_UINT = 268 +IMG_FMT_MM_8_8_8_8_UNORM = 269 +IMG_FMT_MM_8_8_8_8_UINT = 270 +IMG_FMT_MM_VYUY8_UNORM = 271 +IMG_FMT_MM_VYUY8_UINT = 272 +IMG_FMT_MM_10_11_11_UNORM = 273 +IMG_FMT_MM_10_11_11_UINT = 274 +IMG_FMT_MM_2_10_10_10_UNORM = 275 +IMG_FMT_MM_2_10_10_10_UINT = 276 +IMG_FMT_MM_16_16_16_16_UNORM = 277 +IMG_FMT_MM_16_16_16_16_UINT = 278 +IMG_FMT_MM_10_IN_16_UNORM = 279 +IMG_FMT_MM_10_IN_16_UINT = 280 +IMG_FMT_MM_10_IN_16_16_UNORM = 281 +IMG_FMT_MM_10_IN_16_16_UINT = 282 +IMG_FMT_MM_10_IN_16_16_16_16_UNORM = 283 +IMG_FMT_MM_10_IN_16_16_16_16_UINT = 284 +IMG_FMT_RESERVED_285 = 285 +IMG_FMT_RESERVED_286 = 286 +IMG_FMT_RESERVED_287 = 287 +IMG_FMT_RESERVED_288 = 288 +IMG_FMT_RESERVED_289 = 289 +IMG_FMT_RESERVED_290 = 290 +IMG_FMT_RESERVED_291 = 291 +IMG_FMT_RESERVED_292 = 292 +IMG_FMT_RESERVED_293 = 293 +IMG_FMT_RESERVED_294 = 294 +IMG_FMT_RESERVED_295 = 295 +IMG_FMT_RESERVED_296 = 296 +IMG_FMT_RESERVED_297 = 297 +IMG_FMT_RESERVED_298 = 298 +IMG_FMT_RESERVED_299 = 299 +IMG_FMT_RESERVED_300 = 300 +IMG_FMT_RESERVED_301 = 301 +IMG_FMT_RESERVED_302 = 302 +IMG_FMT_RESERVED_303 = 303 +IMG_FMT_RESERVED_304 = 304 +IMG_FMT_RESERVED_305 = 305 +IMG_FMT_RESERVED_306 = 306 +IMG_FMT_RESERVED_307 = 307 +IMG_FMT_RESERVED_308 = 308 +IMG_FMT_RESERVED_309 = 309 +IMG_FMT_RESERVED_310 = 310 +IMG_FMT_RESERVED_311 = 311 +IMG_FMT_RESERVED_312 = 312 +IMG_FMT_RESERVED_313 = 313 +IMG_FMT_RESERVED_314 = 314 +IMG_FMT_RESERVED_315 = 315 +IMG_FMT_RESERVED_316 = 316 +IMG_FMT_RESERVED_317 = 317 +IMG_FMT_RESERVED_318 = 318 +IMG_FMT_RESERVED_319 = 319 +IMG_FMT_RESERVED_320 = 320 +IMG_FMT_RESERVED_321 = 321 +IMG_FMT_RESERVED_322 = 322 +IMG_FMT_RESERVED_323 = 323 +IMG_FMT_RESERVED_324 = 324 +IMG_FMT_RESERVED_325 = 325 +IMG_FMT_RESERVED_326 = 326 +IMG_FMT_RESERVED_327 = 327 +IMG_FMT_RESERVED_328 = 328 +IMG_FMT_RESERVED_329 = 329 +IMG_FMT_RESERVED_330 = 330 +IMG_FMT_RESERVED_331 = 331 +IMG_FMT_RESERVED_332 = 332 +IMG_FMT_RESERVED_333 = 333 +IMG_FMT_RESERVED_334 = 334 +IMG_FMT_RESERVED_335 = 335 +IMG_FMT_RESERVED_336 = 336 +IMG_FMT_RESERVED_337 = 337 +IMG_FMT_RESERVED_338 = 338 +IMG_FMT_RESERVED_339 = 339 +IMG_FMT_RESERVED_340 = 340 +IMG_FMT_RESERVED_341 = 341 +IMG_FMT_RESERVED_342 = 342 +IMG_FMT_RESERVED_343 = 343 +IMG_FMT_RESERVED_344 = 344 +IMG_FMT_RESERVED_345 = 345 +IMG_FMT_RESERVED_346 = 346 +IMG_FMT_RESERVED_347 = 347 +IMG_FMT_RESERVED_348 = 348 +IMG_FMT_RESERVED_349 = 349 +IMG_FMT_RESERVED_350 = 350 +IMG_FMT_RESERVED_351 = 351 +IMG_FMT_RESERVED_352 = 352 +IMG_FMT_RESERVED_353 = 353 +IMG_FMT_RESERVED_354 = 354 +IMG_FMT_RESERVED_355 = 355 +IMG_FMT_RESERVED_356 = 356 +IMG_FMT_RESERVED_357 = 357 +IMG_FMT_RESERVED_358 = 358 +IMG_FMT_RESERVED_359 = 359 +IMG_FMT_RESERVED_360 = 360 +IMG_FMT_RESERVED_361 = 361 +IMG_FMT_RESERVED_362 = 362 +IMG_FMT_RESERVED_363 = 363 +IMG_FMT_RESERVED_364 = 364 +IMG_FMT_RESERVED_365 = 365 +IMG_FMT_RESERVED_366 = 366 +IMG_FMT_RESERVED_367 = 367 +IMG_FMT_RESERVED_368 = 368 +IMG_FMT_RESERVED_369 = 369 +IMG_FMT_RESERVED_370 = 370 +IMG_FMT_RESERVED_371 = 371 +IMG_FMT_RESERVED_372 = 372 +IMG_FMT_RESERVED_373 = 373 +IMG_FMT_RESERVED_374 = 374 +IMG_FMT_RESERVED_375 = 375 +IMG_FMT_RESERVED_376 = 376 +IMG_FMT_RESERVED_377 = 377 +IMG_FMT_RESERVED_378 = 378 +IMG_FMT_RESERVED_379 = 379 +IMG_FMT_RESERVED_380 = 380 +IMG_FMT_RESERVED_381 = 381 +IMG_FMT_RESERVED_382 = 382 +IMG_FMT_RESERVED_383 = 383 +IMG_FMT_RESERVED_384 = 384 +IMG_FMT_RESERVED_385 = 385 +IMG_FMT_RESERVED_386 = 386 +IMG_FMT_RESERVED_387 = 387 +IMG_FMT_RESERVED_388 = 388 +IMG_FMT_RESERVED_389 = 389 +IMG_FMT_RESERVED_390 = 390 +IMG_FMT_RESERVED_391 = 391 +IMG_FMT_RESERVED_392 = 392 +IMG_FMT_RESERVED_393 = 393 +IMG_FMT_RESERVED_394 = 394 +IMG_FMT_RESERVED_395 = 395 +IMG_FMT_RESERVED_396 = 396 +IMG_FMT_RESERVED_397 = 397 +IMG_FMT_RESERVED_398 = 398 +IMG_FMT_RESERVED_399 = 399 +IMG_FMT_RESERVED_400 = 400 +IMG_FMT_RESERVED_401 = 401 +IMG_FMT_RESERVED_402 = 402 +IMG_FMT_RESERVED_403 = 403 +IMG_FMT_RESERVED_404 = 404 +IMG_FMT_RESERVED_405 = 405 +IMG_FMT_RESERVED_406 = 406 +IMG_FMT_RESERVED_407 = 407 +IMG_FMT_RESERVED_408 = 408 +IMG_FMT_RESERVED_409 = 409 +IMG_FMT_RESERVED_410 = 410 +IMG_FMT_RESERVED_411 = 411 +IMG_FMT_RESERVED_412 = 412 +IMG_FMT_RESERVED_413 = 413 +IMG_FMT_RESERVED_414 = 414 +IMG_FMT_RESERVED_415 = 415 +IMG_FMT_RESERVED_416 = 416 +IMG_FMT_RESERVED_417 = 417 +IMG_FMT_RESERVED_418 = 418 +IMG_FMT_RESERVED_419 = 419 +IMG_FMT_RESERVED_420 = 420 +IMG_FMT_RESERVED_421 = 421 +IMG_FMT_RESERVED_422 = 422 +IMG_FMT_RESERVED_423 = 423 +IMG_FMT_RESERVED_424 = 424 +IMG_FMT_RESERVED_425 = 425 +IMG_FMT_RESERVED_426 = 426 +IMG_FMT_RESERVED_427 = 427 +IMG_FMT_RESERVED_428 = 428 +IMG_FMT_RESERVED_429 = 429 +IMG_FMT_RESERVED_430 = 430 +IMG_FMT_RESERVED_431 = 431 +IMG_FMT_RESERVED_432 = 432 +IMG_FMT_RESERVED_433 = 433 +IMG_FMT_RESERVED_434 = 434 +IMG_FMT_RESERVED_435 = 435 +IMG_FMT_RESERVED_436 = 436 +IMG_FMT_RESERVED_437 = 437 +IMG_FMT_RESERVED_438 = 438 +IMG_FMT_RESERVED_439 = 439 +IMG_FMT_RESERVED_440 = 440 +IMG_FMT_RESERVED_441 = 441 +IMG_FMT_RESERVED_442 = 442 +IMG_FMT_RESERVED_443 = 443 +IMG_FMT_RESERVED_444 = 444 +IMG_FMT_RESERVED_445 = 445 +IMG_FMT_RESERVED_446 = 446 +IMG_FMT_RESERVED_447 = 447 +IMG_FMT_RESERVED_448 = 448 +IMG_FMT_RESERVED_449 = 449 +IMG_FMT_RESERVED_450 = 450 +IMG_FMT_RESERVED_451 = 451 +IMG_FMT_RESERVED_452 = 452 +IMG_FMT_RESERVED_453 = 453 +IMG_FMT_RESERVED_454 = 454 +IMG_FMT_RESERVED_455 = 455 +IMG_FMT_RESERVED_456 = 456 +IMG_FMT_RESERVED_457 = 457 +IMG_FMT_RESERVED_458 = 458 +IMG_FMT_RESERVED_459 = 459 +IMG_FMT_RESERVED_460 = 460 +IMG_FMT_RESERVED_461 = 461 +IMG_FMT_RESERVED_462 = 462 +IMG_FMT_RESERVED_463 = 463 +IMG_FMT_RESERVED_464 = 464 +IMG_FMT_RESERVED_465 = 465 +IMG_FMT_RESERVED_466 = 466 +IMG_FMT_RESERVED_467 = 467 +IMG_FMT_RESERVED_468 = 468 +IMG_FMT_RESERVED_469 = 469 +IMG_FMT_RESERVED_470 = 470 +IMG_FMT_RESERVED_471 = 471 +IMG_FMT_RESERVED_472 = 472 +IMG_FMT_RESERVED_473 = 473 +IMG_FMT_RESERVED_474 = 474 +IMG_FMT_RESERVED_475 = 475 +IMG_FMT_RESERVED_476 = 476 +IMG_FMT_RESERVED_477 = 477 +IMG_FMT_RESERVED_478 = 478 +IMG_FMT_RESERVED_479 = 479 +IMG_FMT_RESERVED_480 = 480 +IMG_FMT_RESERVED_481 = 481 +IMG_FMT_RESERVED_482 = 482 +IMG_FMT_RESERVED_483 = 483 +IMG_FMT_RESERVED_484 = 484 +IMG_FMT_RESERVED_485 = 485 +IMG_FMT_RESERVED_486 = 486 +IMG_FMT_RESERVED_487 = 487 +IMG_FMT_RESERVED_488 = 488 +IMG_FMT_RESERVED_489 = 489 +IMG_FMT_RESERVED_490 = 490 +IMG_FMT_RESERVED_491 = 491 +IMG_FMT_RESERVED_492 = 492 +IMG_FMT_RESERVED_493 = 493 +IMG_FMT_RESERVED_494 = 494 +IMG_FMT_RESERVED_495 = 495 +IMG_FMT_RESERVED_496 = 496 +IMG_FMT_RESERVED_497 = 497 +IMG_FMT_RESERVED_498 = 498 +IMG_FMT_RESERVED_499 = 499 +IMG_FMT_RESERVED_500 = 500 +IMG_FMT_RESERVED_501 = 501 +IMG_FMT_RESERVED_502 = 502 +IMG_FMT_RESERVED_503 = 503 +IMG_FMT_RESERVED_504 = 504 +IMG_FMT_RESERVED_505 = 505 +IMG_FMT_RESERVED_506 = 506 +IMG_FMT_RESERVED_507 = 507 +IMG_FMT_RESERVED_508 = 508 +IMG_FMT_RESERVED_509 = 509 +IMG_FMT_RESERVED_510 = 510 +IMG_FMT_RESERVED_511 = 511 +IMG_FMT = ctypes.c_uint32 # enum + +# values for enumeration 'BUF_DATA_FORMAT' +BUF_DATA_FORMAT__enumvalues = { + 0: 'BUF_DATA_FORMAT_INVALID', + 1: 'BUF_DATA_FORMAT_8', + 2: 'BUF_DATA_FORMAT_16', + 3: 'BUF_DATA_FORMAT_8_8', + 4: 'BUF_DATA_FORMAT_32', + 5: 'BUF_DATA_FORMAT_16_16', + 6: 'BUF_DATA_FORMAT_10_11_11', + 7: 'BUF_DATA_FORMAT_11_11_10', + 8: 'BUF_DATA_FORMAT_10_10_10_2', + 9: 'BUF_DATA_FORMAT_2_10_10_10', + 10: 'BUF_DATA_FORMAT_8_8_8_8', + 11: 'BUF_DATA_FORMAT_32_32', + 12: 'BUF_DATA_FORMAT_16_16_16_16', + 13: 'BUF_DATA_FORMAT_32_32_32', + 14: 'BUF_DATA_FORMAT_32_32_32_32', + 15: 'BUF_DATA_FORMAT_RESERVED_15', +} +BUF_DATA_FORMAT_INVALID = 0 +BUF_DATA_FORMAT_8 = 1 +BUF_DATA_FORMAT_16 = 2 +BUF_DATA_FORMAT_8_8 = 3 +BUF_DATA_FORMAT_32 = 4 +BUF_DATA_FORMAT_16_16 = 5 +BUF_DATA_FORMAT_10_11_11 = 6 +BUF_DATA_FORMAT_11_11_10 = 7 +BUF_DATA_FORMAT_10_10_10_2 = 8 +BUF_DATA_FORMAT_2_10_10_10 = 9 +BUF_DATA_FORMAT_8_8_8_8 = 10 +BUF_DATA_FORMAT_32_32 = 11 +BUF_DATA_FORMAT_16_16_16_16 = 12 +BUF_DATA_FORMAT_32_32_32 = 13 +BUF_DATA_FORMAT_32_32_32_32 = 14 +BUF_DATA_FORMAT_RESERVED_15 = 15 +BUF_DATA_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_DATA_FORMAT' +IMG_DATA_FORMAT__enumvalues = { + 0: 'IMG_DATA_FORMAT_INVALID', + 1: 'IMG_DATA_FORMAT_8', + 2: 'IMG_DATA_FORMAT_16', + 3: 'IMG_DATA_FORMAT_8_8', + 4: 'IMG_DATA_FORMAT_32', + 5: 'IMG_DATA_FORMAT_16_16', + 6: 'IMG_DATA_FORMAT_10_11_11', + 7: 'IMG_DATA_FORMAT_11_11_10', + 8: 'IMG_DATA_FORMAT_10_10_10_2', + 9: 'IMG_DATA_FORMAT_2_10_10_10', + 10: 'IMG_DATA_FORMAT_8_8_8_8', + 11: 'IMG_DATA_FORMAT_32_32', + 12: 'IMG_DATA_FORMAT_16_16_16_16', + 13: 'IMG_DATA_FORMAT_32_32_32', + 14: 'IMG_DATA_FORMAT_32_32_32_32', + 15: 'IMG_DATA_FORMAT_RESERVED_15', + 16: 'IMG_DATA_FORMAT_5_6_5', + 17: 'IMG_DATA_FORMAT_1_5_5_5', + 18: 'IMG_DATA_FORMAT_5_5_5_1', + 19: 'IMG_DATA_FORMAT_4_4_4_4', + 20: 'IMG_DATA_FORMAT_8_24', + 21: 'IMG_DATA_FORMAT_24_8', + 22: 'IMG_DATA_FORMAT_X24_8_32', + 23: 'IMG_DATA_FORMAT_RESERVED_23', + 24: 'IMG_DATA_FORMAT_RESERVED_24', + 25: 'IMG_DATA_FORMAT_RESERVED_25', + 26: 'IMG_DATA_FORMAT_RESERVED_26', + 27: 'IMG_DATA_FORMAT_RESERVED_27', + 28: 'IMG_DATA_FORMAT_RESERVED_28', + 29: 'IMG_DATA_FORMAT_RESERVED_29', + 30: 'IMG_DATA_FORMAT_RESERVED_30', + 31: 'IMG_DATA_FORMAT_6E4', + 32: 'IMG_DATA_FORMAT_GB_GR', + 33: 'IMG_DATA_FORMAT_BG_RG', + 34: 'IMG_DATA_FORMAT_5_9_9_9', + 35: 'IMG_DATA_FORMAT_BC1', + 36: 'IMG_DATA_FORMAT_BC2', + 37: 'IMG_DATA_FORMAT_BC3', + 38: 'IMG_DATA_FORMAT_BC4', + 39: 'IMG_DATA_FORMAT_BC5', + 40: 'IMG_DATA_FORMAT_BC6', + 41: 'IMG_DATA_FORMAT_BC7', + 42: 'IMG_DATA_FORMAT_RESERVED_42', + 43: 'IMG_DATA_FORMAT_RESERVED_43', + 44: 'IMG_DATA_FORMAT_FMASK8_S2_F1', + 45: 'IMG_DATA_FORMAT_FMASK8_S4_F1', + 46: 'IMG_DATA_FORMAT_FMASK8_S8_F1', + 47: 'IMG_DATA_FORMAT_FMASK8_S2_F2', + 48: 'IMG_DATA_FORMAT_FMASK8_S4_F2', + 49: 'IMG_DATA_FORMAT_FMASK8_S4_F4', + 50: 'IMG_DATA_FORMAT_FMASK16_S16_F1', + 51: 'IMG_DATA_FORMAT_FMASK16_S8_F2', + 52: 'IMG_DATA_FORMAT_FMASK32_S16_F2', + 53: 'IMG_DATA_FORMAT_FMASK32_S8_F4', + 54: 'IMG_DATA_FORMAT_FMASK32_S8_F8', + 55: 'IMG_DATA_FORMAT_FMASK64_S16_F4', + 56: 'IMG_DATA_FORMAT_FMASK64_S16_F8', + 57: 'IMG_DATA_FORMAT_4_4', + 58: 'IMG_DATA_FORMAT_6_5_5', + 59: 'IMG_DATA_FORMAT_1', + 60: 'IMG_DATA_FORMAT_1_REVERSED', + 61: 'IMG_DATA_FORMAT_RESERVED_61', + 62: 'IMG_DATA_FORMAT_RESERVED_62', + 63: 'IMG_DATA_FORMAT_32_AS_32_32_32_32', + 75: 'IMG_DATA_FORMAT_RESERVED_75', + 76: 'IMG_DATA_FORMAT_MM_8', + 77: 'IMG_DATA_FORMAT_MM_8_8', + 78: 'IMG_DATA_FORMAT_MM_8_8_8_8', + 79: 'IMG_DATA_FORMAT_MM_VYUY8', + 80: 'IMG_DATA_FORMAT_MM_10_11_11', + 81: 'IMG_DATA_FORMAT_MM_2_10_10_10', + 82: 'IMG_DATA_FORMAT_MM_16_16_16_16', + 83: 'IMG_DATA_FORMAT_MM_10_IN_16', + 84: 'IMG_DATA_FORMAT_MM_10_IN_16_16', + 85: 'IMG_DATA_FORMAT_MM_10_IN_16_16_16_16', + 86: 'IMG_DATA_FORMAT_RESERVED_86', + 87: 'IMG_DATA_FORMAT_RESERVED_87', + 88: 'IMG_DATA_FORMAT_RESERVED_88', + 89: 'IMG_DATA_FORMAT_RESERVED_89', + 90: 'IMG_DATA_FORMAT_RESERVED_90', + 91: 'IMG_DATA_FORMAT_RESERVED_91', + 92: 'IMG_DATA_FORMAT_RESERVED_92', + 93: 'IMG_DATA_FORMAT_RESERVED_93', + 94: 'IMG_DATA_FORMAT_RESERVED_94', + 95: 'IMG_DATA_FORMAT_RESERVED_95', + 96: 'IMG_DATA_FORMAT_RESERVED_96', + 97: 'IMG_DATA_FORMAT_RESERVED_97', + 98: 'IMG_DATA_FORMAT_RESERVED_98', + 99: 'IMG_DATA_FORMAT_RESERVED_99', + 100: 'IMG_DATA_FORMAT_RESERVED_100', + 101: 'IMG_DATA_FORMAT_RESERVED_101', + 102: 'IMG_DATA_FORMAT_RESERVED_102', + 103: 'IMG_DATA_FORMAT_RESERVED_103', + 104: 'IMG_DATA_FORMAT_RESERVED_104', + 105: 'IMG_DATA_FORMAT_RESERVED_105', + 106: 'IMG_DATA_FORMAT_RESERVED_106', + 107: 'IMG_DATA_FORMAT_RESERVED_107', + 108: 'IMG_DATA_FORMAT_RESERVED_108', + 109: 'IMG_DATA_FORMAT_RESERVED_109', + 110: 'IMG_DATA_FORMAT_RESERVED_110', + 111: 'IMG_DATA_FORMAT_RESERVED_111', + 112: 'IMG_DATA_FORMAT_RESERVED_112', + 113: 'IMG_DATA_FORMAT_RESERVED_113', + 114: 'IMG_DATA_FORMAT_RESERVED_114', + 115: 'IMG_DATA_FORMAT_RESERVED_115', + 116: 'IMG_DATA_FORMAT_RESERVED_116', + 117: 'IMG_DATA_FORMAT_RESERVED_117', + 118: 'IMG_DATA_FORMAT_RESERVED_118', + 119: 'IMG_DATA_FORMAT_RESERVED_119', + 120: 'IMG_DATA_FORMAT_RESERVED_120', + 121: 'IMG_DATA_FORMAT_RESERVED_121', + 122: 'IMG_DATA_FORMAT_RESERVED_122', + 123: 'IMG_DATA_FORMAT_RESERVED_123', + 124: 'IMG_DATA_FORMAT_RESERVED_124', + 125: 'IMG_DATA_FORMAT_RESERVED_125', + 126: 'IMG_DATA_FORMAT_RESERVED_126', + 127: 'IMG_DATA_FORMAT_RESERVED_127', +} +IMG_DATA_FORMAT_INVALID = 0 +IMG_DATA_FORMAT_8 = 1 +IMG_DATA_FORMAT_16 = 2 +IMG_DATA_FORMAT_8_8 = 3 +IMG_DATA_FORMAT_32 = 4 +IMG_DATA_FORMAT_16_16 = 5 +IMG_DATA_FORMAT_10_11_11 = 6 +IMG_DATA_FORMAT_11_11_10 = 7 +IMG_DATA_FORMAT_10_10_10_2 = 8 +IMG_DATA_FORMAT_2_10_10_10 = 9 +IMG_DATA_FORMAT_8_8_8_8 = 10 +IMG_DATA_FORMAT_32_32 = 11 +IMG_DATA_FORMAT_16_16_16_16 = 12 +IMG_DATA_FORMAT_32_32_32 = 13 +IMG_DATA_FORMAT_32_32_32_32 = 14 +IMG_DATA_FORMAT_RESERVED_15 = 15 +IMG_DATA_FORMAT_5_6_5 = 16 +IMG_DATA_FORMAT_1_5_5_5 = 17 +IMG_DATA_FORMAT_5_5_5_1 = 18 +IMG_DATA_FORMAT_4_4_4_4 = 19 +IMG_DATA_FORMAT_8_24 = 20 +IMG_DATA_FORMAT_24_8 = 21 +IMG_DATA_FORMAT_X24_8_32 = 22 +IMG_DATA_FORMAT_RESERVED_23 = 23 +IMG_DATA_FORMAT_RESERVED_24 = 24 +IMG_DATA_FORMAT_RESERVED_25 = 25 +IMG_DATA_FORMAT_RESERVED_26 = 26 +IMG_DATA_FORMAT_RESERVED_27 = 27 +IMG_DATA_FORMAT_RESERVED_28 = 28 +IMG_DATA_FORMAT_RESERVED_29 = 29 +IMG_DATA_FORMAT_RESERVED_30 = 30 +IMG_DATA_FORMAT_6E4 = 31 +IMG_DATA_FORMAT_GB_GR = 32 +IMG_DATA_FORMAT_BG_RG = 33 +IMG_DATA_FORMAT_5_9_9_9 = 34 +IMG_DATA_FORMAT_BC1 = 35 +IMG_DATA_FORMAT_BC2 = 36 +IMG_DATA_FORMAT_BC3 = 37 +IMG_DATA_FORMAT_BC4 = 38 +IMG_DATA_FORMAT_BC5 = 39 +IMG_DATA_FORMAT_BC6 = 40 +IMG_DATA_FORMAT_BC7 = 41 +IMG_DATA_FORMAT_RESERVED_42 = 42 +IMG_DATA_FORMAT_RESERVED_43 = 43 +IMG_DATA_FORMAT_FMASK8_S2_F1 = 44 +IMG_DATA_FORMAT_FMASK8_S4_F1 = 45 +IMG_DATA_FORMAT_FMASK8_S8_F1 = 46 +IMG_DATA_FORMAT_FMASK8_S2_F2 = 47 +IMG_DATA_FORMAT_FMASK8_S4_F2 = 48 +IMG_DATA_FORMAT_FMASK8_S4_F4 = 49 +IMG_DATA_FORMAT_FMASK16_S16_F1 = 50 +IMG_DATA_FORMAT_FMASK16_S8_F2 = 51 +IMG_DATA_FORMAT_FMASK32_S16_F2 = 52 +IMG_DATA_FORMAT_FMASK32_S8_F4 = 53 +IMG_DATA_FORMAT_FMASK32_S8_F8 = 54 +IMG_DATA_FORMAT_FMASK64_S16_F4 = 55 +IMG_DATA_FORMAT_FMASK64_S16_F8 = 56 +IMG_DATA_FORMAT_4_4 = 57 +IMG_DATA_FORMAT_6_5_5 = 58 +IMG_DATA_FORMAT_1 = 59 +IMG_DATA_FORMAT_1_REVERSED = 60 +IMG_DATA_FORMAT_RESERVED_61 = 61 +IMG_DATA_FORMAT_RESERVED_62 = 62 +IMG_DATA_FORMAT_32_AS_32_32_32_32 = 63 +IMG_DATA_FORMAT_RESERVED_75 = 75 +IMG_DATA_FORMAT_MM_8 = 76 +IMG_DATA_FORMAT_MM_8_8 = 77 +IMG_DATA_FORMAT_MM_8_8_8_8 = 78 +IMG_DATA_FORMAT_MM_VYUY8 = 79 +IMG_DATA_FORMAT_MM_10_11_11 = 80 +IMG_DATA_FORMAT_MM_2_10_10_10 = 81 +IMG_DATA_FORMAT_MM_16_16_16_16 = 82 +IMG_DATA_FORMAT_MM_10_IN_16 = 83 +IMG_DATA_FORMAT_MM_10_IN_16_16 = 84 +IMG_DATA_FORMAT_MM_10_IN_16_16_16_16 = 85 +IMG_DATA_FORMAT_RESERVED_86 = 86 +IMG_DATA_FORMAT_RESERVED_87 = 87 +IMG_DATA_FORMAT_RESERVED_88 = 88 +IMG_DATA_FORMAT_RESERVED_89 = 89 +IMG_DATA_FORMAT_RESERVED_90 = 90 +IMG_DATA_FORMAT_RESERVED_91 = 91 +IMG_DATA_FORMAT_RESERVED_92 = 92 +IMG_DATA_FORMAT_RESERVED_93 = 93 +IMG_DATA_FORMAT_RESERVED_94 = 94 +IMG_DATA_FORMAT_RESERVED_95 = 95 +IMG_DATA_FORMAT_RESERVED_96 = 96 +IMG_DATA_FORMAT_RESERVED_97 = 97 +IMG_DATA_FORMAT_RESERVED_98 = 98 +IMG_DATA_FORMAT_RESERVED_99 = 99 +IMG_DATA_FORMAT_RESERVED_100 = 100 +IMG_DATA_FORMAT_RESERVED_101 = 101 +IMG_DATA_FORMAT_RESERVED_102 = 102 +IMG_DATA_FORMAT_RESERVED_103 = 103 +IMG_DATA_FORMAT_RESERVED_104 = 104 +IMG_DATA_FORMAT_RESERVED_105 = 105 +IMG_DATA_FORMAT_RESERVED_106 = 106 +IMG_DATA_FORMAT_RESERVED_107 = 107 +IMG_DATA_FORMAT_RESERVED_108 = 108 +IMG_DATA_FORMAT_RESERVED_109 = 109 +IMG_DATA_FORMAT_RESERVED_110 = 110 +IMG_DATA_FORMAT_RESERVED_111 = 111 +IMG_DATA_FORMAT_RESERVED_112 = 112 +IMG_DATA_FORMAT_RESERVED_113 = 113 +IMG_DATA_FORMAT_RESERVED_114 = 114 +IMG_DATA_FORMAT_RESERVED_115 = 115 +IMG_DATA_FORMAT_RESERVED_116 = 116 +IMG_DATA_FORMAT_RESERVED_117 = 117 +IMG_DATA_FORMAT_RESERVED_118 = 118 +IMG_DATA_FORMAT_RESERVED_119 = 119 +IMG_DATA_FORMAT_RESERVED_120 = 120 +IMG_DATA_FORMAT_RESERVED_121 = 121 +IMG_DATA_FORMAT_RESERVED_122 = 122 +IMG_DATA_FORMAT_RESERVED_123 = 123 +IMG_DATA_FORMAT_RESERVED_124 = 124 +IMG_DATA_FORMAT_RESERVED_125 = 125 +IMG_DATA_FORMAT_RESERVED_126 = 126 +IMG_DATA_FORMAT_RESERVED_127 = 127 +IMG_DATA_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'BUF_NUM_FORMAT' +BUF_NUM_FORMAT__enumvalues = { + 0: 'BUF_NUM_FORMAT_UNORM', + 1: 'BUF_NUM_FORMAT_SNORM', + 2: 'BUF_NUM_FORMAT_USCALED', + 3: 'BUF_NUM_FORMAT_SSCALED', + 4: 'BUF_NUM_FORMAT_UINT', + 5: 'BUF_NUM_FORMAT_SINT', + 6: 'BUF_NUM_FORMAT_SNORM_NZ', + 7: 'BUF_NUM_FORMAT_FLOAT', +} +BUF_NUM_FORMAT_UNORM = 0 +BUF_NUM_FORMAT_SNORM = 1 +BUF_NUM_FORMAT_USCALED = 2 +BUF_NUM_FORMAT_SSCALED = 3 +BUF_NUM_FORMAT_UINT = 4 +BUF_NUM_FORMAT_SINT = 5 +BUF_NUM_FORMAT_SNORM_NZ = 6 +BUF_NUM_FORMAT_FLOAT = 7 +BUF_NUM_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT' +IMG_NUM_FORMAT__enumvalues = { + 0: 'IMG_NUM_FORMAT_UNORM', + 1: 'IMG_NUM_FORMAT_SNORM', + 2: 'IMG_NUM_FORMAT_USCALED', + 3: 'IMG_NUM_FORMAT_SSCALED', + 4: 'IMG_NUM_FORMAT_UINT', + 5: 'IMG_NUM_FORMAT_SINT', + 6: 'IMG_NUM_FORMAT_SNORM_NZ', + 7: 'IMG_NUM_FORMAT_FLOAT', + 8: 'IMG_NUM_FORMAT_RESERVED_8', + 9: 'IMG_NUM_FORMAT_SRGB', + 10: 'IMG_NUM_FORMAT_UBNORM', + 11: 'IMG_NUM_FORMAT_UBNORM_NZ', + 12: 'IMG_NUM_FORMAT_UBINT', + 13: 'IMG_NUM_FORMAT_UBSCALED', + 14: 'IMG_NUM_FORMAT_RESERVED_14', + 15: 'IMG_NUM_FORMAT_RESERVED_15', +} +IMG_NUM_FORMAT_UNORM = 0 +IMG_NUM_FORMAT_SNORM = 1 +IMG_NUM_FORMAT_USCALED = 2 +IMG_NUM_FORMAT_SSCALED = 3 +IMG_NUM_FORMAT_UINT = 4 +IMG_NUM_FORMAT_SINT = 5 +IMG_NUM_FORMAT_SNORM_NZ = 6 +IMG_NUM_FORMAT_FLOAT = 7 +IMG_NUM_FORMAT_RESERVED_8 = 8 +IMG_NUM_FORMAT_SRGB = 9 +IMG_NUM_FORMAT_UBNORM = 10 +IMG_NUM_FORMAT_UBNORM_NZ = 11 +IMG_NUM_FORMAT_UBINT = 12 +IMG_NUM_FORMAT_UBSCALED = 13 +IMG_NUM_FORMAT_RESERVED_14 = 14 +IMG_NUM_FORMAT_RESERVED_15 = 15 +IMG_NUM_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'IH_PERF_SEL' +IH_PERF_SEL__enumvalues = { + 0: 'IH_PERF_SEL_CYCLE', + 1: 'IH_PERF_SEL_IDLE', + 2: 'IH_PERF_SEL_INPUT_IDLE', + 3: 'IH_PERF_SEL_BUFFER_IDLE', + 4: 'IH_PERF_SEL_RB0_FULL', + 5: 'IH_PERF_SEL_RB0_OVERFLOW', + 6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', + 7: 'IH_PERF_SEL_RB0_WPTR_WRAP', + 8: 'IH_PERF_SEL_RB0_RPTR_WRAP', + 9: 'IH_PERF_SEL_MC_WR_IDLE', + 10: 'IH_PERF_SEL_MC_WR_COUNT', + 11: 'IH_PERF_SEL_MC_WR_STALL', + 12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', + 13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL', + 14: 'IH_PERF_SEL_BIF_LINE0_RISING', + 15: 'IH_PERF_SEL_BIF_LINE0_FALLING', + 16: 'IH_PERF_SEL_RB1_FULL', + 17: 'IH_PERF_SEL_RB1_OVERFLOW', + 18: 'IH_PERF_SEL_COOKIE_REC_ERROR', + 19: 'IH_PERF_SEL_RB1_WPTR_WRAP', + 20: 'IH_PERF_SEL_RB1_RPTR_WRAP', + 21: 'IH_PERF_SEL_RB2_FULL', + 22: 'IH_PERF_SEL_RB2_OVERFLOW', + 23: 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', + 24: 'IH_PERF_SEL_RB2_WPTR_WRAP', + 25: 'IH_PERF_SEL_RB2_RPTR_WRAP', + 26: 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', + 27: 'IH_PERF_SEL_SELF_IV_VALID', + 28: 'IH_PERF_SEL_BUFFER_FIFO_FULL', + 29: 'IH_PERF_SEL_RB0_FULL_VF0', + 30: 'IH_PERF_SEL_RB0_FULL_VF1', + 31: 'IH_PERF_SEL_RB0_FULL_VF2', + 32: 'IH_PERF_SEL_RB0_FULL_VF3', + 33: 'IH_PERF_SEL_RB0_FULL_VF4', + 34: 'IH_PERF_SEL_RB0_FULL_VF5', + 35: 'IH_PERF_SEL_RB0_FULL_VF6', + 36: 'IH_PERF_SEL_RB0_FULL_VF7', + 37: 'IH_PERF_SEL_RB0_FULL_VF8', + 38: 'IH_PERF_SEL_RB0_FULL_VF9', + 39: 'IH_PERF_SEL_RB0_FULL_VF10', + 40: 'IH_PERF_SEL_RB0_FULL_VF11', + 41: 'IH_PERF_SEL_RB0_FULL_VF12', + 42: 'IH_PERF_SEL_RB0_FULL_VF13', + 43: 'IH_PERF_SEL_RB0_FULL_VF14', + 44: 'IH_PERF_SEL_RB0_FULL_VF15', + 45: 'IH_PERF_SEL_RB0_FULL_VF16', + 46: 'IH_PERF_SEL_RB0_FULL_VF17', + 47: 'IH_PERF_SEL_RB0_FULL_VF18', + 48: 'IH_PERF_SEL_RB0_FULL_VF19', + 49: 'IH_PERF_SEL_RB0_FULL_VF20', + 50: 'IH_PERF_SEL_RB0_FULL_VF21', + 51: 'IH_PERF_SEL_RB0_FULL_VF22', + 52: 'IH_PERF_SEL_RB0_FULL_VF23', + 53: 'IH_PERF_SEL_RB0_FULL_VF24', + 54: 'IH_PERF_SEL_RB0_FULL_VF25', + 55: 'IH_PERF_SEL_RB0_FULL_VF26', + 56: 'IH_PERF_SEL_RB0_FULL_VF27', + 57: 'IH_PERF_SEL_RB0_FULL_VF28', + 58: 'IH_PERF_SEL_RB0_FULL_VF29', + 59: 'IH_PERF_SEL_RB0_FULL_VF30', + 60: 'IH_PERF_SEL_RB0_OVERFLOW_VF0', + 61: 'IH_PERF_SEL_RB0_OVERFLOW_VF1', + 62: 'IH_PERF_SEL_RB0_OVERFLOW_VF2', + 63: 'IH_PERF_SEL_RB0_OVERFLOW_VF3', + 64: 'IH_PERF_SEL_RB0_OVERFLOW_VF4', + 65: 'IH_PERF_SEL_RB0_OVERFLOW_VF5', + 66: 'IH_PERF_SEL_RB0_OVERFLOW_VF6', + 67: 'IH_PERF_SEL_RB0_OVERFLOW_VF7', + 68: 'IH_PERF_SEL_RB0_OVERFLOW_VF8', + 69: 'IH_PERF_SEL_RB0_OVERFLOW_VF9', + 70: 'IH_PERF_SEL_RB0_OVERFLOW_VF10', + 71: 'IH_PERF_SEL_RB0_OVERFLOW_VF11', + 72: 'IH_PERF_SEL_RB0_OVERFLOW_VF12', + 73: 'IH_PERF_SEL_RB0_OVERFLOW_VF13', + 74: 'IH_PERF_SEL_RB0_OVERFLOW_VF14', + 75: 'IH_PERF_SEL_RB0_OVERFLOW_VF15', + 76: 'IH_PERF_SEL_RB0_OVERFLOW_VF16', + 77: 'IH_PERF_SEL_RB0_OVERFLOW_VF17', + 78: 'IH_PERF_SEL_RB0_OVERFLOW_VF18', + 79: 'IH_PERF_SEL_RB0_OVERFLOW_VF19', + 80: 'IH_PERF_SEL_RB0_OVERFLOW_VF20', + 81: 'IH_PERF_SEL_RB0_OVERFLOW_VF21', + 82: 'IH_PERF_SEL_RB0_OVERFLOW_VF22', + 83: 'IH_PERF_SEL_RB0_OVERFLOW_VF23', + 84: 'IH_PERF_SEL_RB0_OVERFLOW_VF24', + 85: 'IH_PERF_SEL_RB0_OVERFLOW_VF25', + 86: 'IH_PERF_SEL_RB0_OVERFLOW_VF26', + 87: 'IH_PERF_SEL_RB0_OVERFLOW_VF27', + 88: 'IH_PERF_SEL_RB0_OVERFLOW_VF28', + 89: 'IH_PERF_SEL_RB0_OVERFLOW_VF29', + 90: 'IH_PERF_SEL_RB0_OVERFLOW_VF30', + 91: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', + 92: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', + 93: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', + 94: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', + 95: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', + 96: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', + 97: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', + 98: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', + 99: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', + 100: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', + 101: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', + 102: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', + 103: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', + 104: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', + 105: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', + 106: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', + 107: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16', + 108: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17', + 109: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18', + 110: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19', + 111: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20', + 112: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21', + 113: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22', + 114: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23', + 115: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24', + 116: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25', + 117: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26', + 118: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27', + 119: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28', + 120: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29', + 121: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30', + 122: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', + 123: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', + 124: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', + 125: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', + 126: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', + 127: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', + 128: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', + 129: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', + 130: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', + 131: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', + 132: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', + 133: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', + 134: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', + 135: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', + 136: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', + 137: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', + 138: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF16', + 139: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF17', + 140: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF18', + 141: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF19', + 142: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF20', + 143: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF21', + 144: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF22', + 145: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF23', + 146: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF24', + 147: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF25', + 148: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF26', + 149: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF27', + 150: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF28', + 151: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF29', + 152: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF30', + 153: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', + 154: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', + 155: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', + 156: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', + 157: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', + 158: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', + 159: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', + 160: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', + 161: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', + 162: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', + 163: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', + 164: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', + 165: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', + 166: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', + 167: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', + 168: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', + 169: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF16', + 170: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF17', + 171: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF18', + 172: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF19', + 173: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF20', + 174: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF21', + 175: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF22', + 176: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF23', + 177: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF24', + 178: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF25', + 179: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF26', + 180: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF27', + 181: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF28', + 182: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF29', + 183: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF30', + 184: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', + 185: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', + 186: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', + 187: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', + 188: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', + 189: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', + 190: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', + 191: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', + 192: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', + 193: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', + 194: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', + 195: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', + 196: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', + 197: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', + 198: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', + 199: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', + 200: 'IH_PERF_SEL_BIF_LINE0_RISING_VF16', + 201: 'IH_PERF_SEL_BIF_LINE0_RISING_VF17', + 202: 'IH_PERF_SEL_BIF_LINE0_RISING_VF18', + 203: 'IH_PERF_SEL_BIF_LINE0_RISING_VF19', + 204: 'IH_PERF_SEL_BIF_LINE0_RISING_VF20', + 205: 'IH_PERF_SEL_BIF_LINE0_RISING_VF21', + 206: 'IH_PERF_SEL_BIF_LINE0_RISING_VF22', + 207: 'IH_PERF_SEL_BIF_LINE0_RISING_VF23', + 208: 'IH_PERF_SEL_BIF_LINE0_RISING_VF24', + 209: 'IH_PERF_SEL_BIF_LINE0_RISING_VF25', + 210: 'IH_PERF_SEL_BIF_LINE0_RISING_VF26', + 211: 'IH_PERF_SEL_BIF_LINE0_RISING_VF27', + 212: 'IH_PERF_SEL_BIF_LINE0_RISING_VF28', + 213: 'IH_PERF_SEL_BIF_LINE0_RISING_VF29', + 214: 'IH_PERF_SEL_BIF_LINE0_RISING_VF30', + 215: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', + 216: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', + 217: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', + 218: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', + 219: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', + 220: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', + 221: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', + 222: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', + 223: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', + 224: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', + 225: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', + 226: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', + 227: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', + 228: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', + 229: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', + 230: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', + 231: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF16', + 232: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF17', + 233: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF18', + 234: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF19', + 235: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF20', + 236: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF21', + 237: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF22', + 238: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF23', + 239: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF24', + 240: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF25', + 241: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF26', + 242: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF27', + 243: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF28', + 244: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF29', + 245: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF30', + 246: 'IH_PERF_SEL_CLIENT0_INT', + 247: 'IH_PERF_SEL_CLIENT1_INT', + 248: 'IH_PERF_SEL_CLIENT2_INT', + 249: 'IH_PERF_SEL_CLIENT3_INT', + 250: 'IH_PERF_SEL_CLIENT4_INT', + 251: 'IH_PERF_SEL_CLIENT5_INT', + 252: 'IH_PERF_SEL_CLIENT6_INT', + 253: 'IH_PERF_SEL_CLIENT7_INT', + 254: 'IH_PERF_SEL_CLIENT8_INT', + 255: 'IH_PERF_SEL_CLIENT9_INT', + 256: 'IH_PERF_SEL_CLIENT10_INT', + 257: 'IH_PERF_SEL_CLIENT11_INT', + 258: 'IH_PERF_SEL_CLIENT12_INT', + 259: 'IH_PERF_SEL_CLIENT13_INT', + 260: 'IH_PERF_SEL_CLIENT14_INT', + 261: 'IH_PERF_SEL_CLIENT15_INT', + 262: 'IH_PERF_SEL_CLIENT16_INT', + 263: 'IH_PERF_SEL_CLIENT17_INT', + 264: 'IH_PERF_SEL_CLIENT18_INT', + 265: 'IH_PERF_SEL_CLIENT19_INT', + 266: 'IH_PERF_SEL_CLIENT20_INT', + 267: 'IH_PERF_SEL_CLIENT21_INT', + 268: 'IH_PERF_SEL_CLIENT22_INT', + 269: 'IH_PERF_SEL_CLIENT23_INT', + 270: 'IH_PERF_SEL_CLIENT24_INT', + 271: 'IH_PERF_SEL_CLIENT25_INT', + 272: 'IH_PERF_SEL_CLIENT26_INT', + 273: 'IH_PERF_SEL_CLIENT27_INT', + 274: 'IH_PERF_SEL_CLIENT28_INT', + 275: 'IH_PERF_SEL_CLIENT29_INT', + 276: 'IH_PERF_SEL_CLIENT30_INT', + 277: 'IH_PERF_SEL_CLIENT31_INT', + 278: 'IH_PERF_SEL_RB1_FULL_VF0', + 279: 'IH_PERF_SEL_RB1_FULL_VF1', + 280: 'IH_PERF_SEL_RB1_FULL_VF2', + 281: 'IH_PERF_SEL_RB1_FULL_VF3', + 282: 'IH_PERF_SEL_RB1_FULL_VF4', + 283: 'IH_PERF_SEL_RB1_FULL_VF5', + 284: 'IH_PERF_SEL_RB1_FULL_VF6', + 285: 'IH_PERF_SEL_RB1_FULL_VF7', + 286: 'IH_PERF_SEL_RB1_FULL_VF8', + 287: 'IH_PERF_SEL_RB1_FULL_VF9', + 288: 'IH_PERF_SEL_RB1_FULL_VF10', + 289: 'IH_PERF_SEL_RB1_FULL_VF11', + 290: 'IH_PERF_SEL_RB1_FULL_VF12', + 291: 'IH_PERF_SEL_RB1_FULL_VF13', + 292: 'IH_PERF_SEL_RB1_FULL_VF14', + 293: 'IH_PERF_SEL_RB1_FULL_VF15', + 294: 'IH_PERF_SEL_RB1_FULL_VF16', + 295: 'IH_PERF_SEL_RB1_FULL_VF17', + 296: 'IH_PERF_SEL_RB1_FULL_VF18', + 297: 'IH_PERF_SEL_RB1_FULL_VF19', + 298: 'IH_PERF_SEL_RB1_FULL_VF20', + 299: 'IH_PERF_SEL_RB1_FULL_VF21', + 300: 'IH_PERF_SEL_RB1_FULL_VF22', + 301: 'IH_PERF_SEL_RB1_FULL_VF23', + 302: 'IH_PERF_SEL_RB1_FULL_VF24', + 303: 'IH_PERF_SEL_RB1_FULL_VF25', + 304: 'IH_PERF_SEL_RB1_FULL_VF26', + 305: 'IH_PERF_SEL_RB1_FULL_VF27', + 306: 'IH_PERF_SEL_RB1_FULL_VF28', + 307: 'IH_PERF_SEL_RB1_FULL_VF29', + 308: 'IH_PERF_SEL_RB1_FULL_VF30', + 309: 'IH_PERF_SEL_RB1_OVERFLOW_VF0', + 310: 'IH_PERF_SEL_RB1_OVERFLOW_VF1', + 311: 'IH_PERF_SEL_RB1_OVERFLOW_VF2', + 312: 'IH_PERF_SEL_RB1_OVERFLOW_VF3', + 313: 'IH_PERF_SEL_RB1_OVERFLOW_VF4', + 314: 'IH_PERF_SEL_RB1_OVERFLOW_VF5', + 315: 'IH_PERF_SEL_RB1_OVERFLOW_VF6', + 316: 'IH_PERF_SEL_RB1_OVERFLOW_VF7', + 317: 'IH_PERF_SEL_RB1_OVERFLOW_VF8', + 318: 'IH_PERF_SEL_RB1_OVERFLOW_VF9', + 319: 'IH_PERF_SEL_RB1_OVERFLOW_VF10', + 320: 'IH_PERF_SEL_RB1_OVERFLOW_VF11', + 321: 'IH_PERF_SEL_RB1_OVERFLOW_VF12', + 322: 'IH_PERF_SEL_RB1_OVERFLOW_VF13', + 323: 'IH_PERF_SEL_RB1_OVERFLOW_VF14', + 324: 'IH_PERF_SEL_RB1_OVERFLOW_VF15', + 325: 'IH_PERF_SEL_RB1_OVERFLOW_VF16', + 326: 'IH_PERF_SEL_RB1_OVERFLOW_VF17', + 327: 'IH_PERF_SEL_RB1_OVERFLOW_VF18', + 328: 'IH_PERF_SEL_RB1_OVERFLOW_VF19', + 329: 'IH_PERF_SEL_RB1_OVERFLOW_VF20', + 330: 'IH_PERF_SEL_RB1_OVERFLOW_VF21', + 331: 'IH_PERF_SEL_RB1_OVERFLOW_VF22', + 332: 'IH_PERF_SEL_RB1_OVERFLOW_VF23', + 333: 'IH_PERF_SEL_RB1_OVERFLOW_VF24', + 334: 'IH_PERF_SEL_RB1_OVERFLOW_VF25', + 335: 'IH_PERF_SEL_RB1_OVERFLOW_VF26', + 336: 'IH_PERF_SEL_RB1_OVERFLOW_VF27', + 337: 'IH_PERF_SEL_RB1_OVERFLOW_VF28', + 338: 'IH_PERF_SEL_RB1_OVERFLOW_VF29', + 339: 'IH_PERF_SEL_RB1_OVERFLOW_VF30', + 340: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', + 341: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', + 342: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', + 343: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', + 344: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', + 345: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', + 346: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', + 347: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', + 348: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', + 349: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', + 350: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', + 351: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', + 352: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', + 353: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', + 354: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', + 355: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', + 356: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF16', + 357: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF17', + 358: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF18', + 359: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF19', + 360: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF20', + 361: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF21', + 362: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF22', + 363: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF23', + 364: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF24', + 365: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF25', + 366: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF26', + 367: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF27', + 368: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF28', + 369: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF29', + 370: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF30', + 371: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', + 372: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', + 373: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', + 374: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', + 375: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', + 376: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', + 377: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', + 378: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', + 379: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', + 380: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', + 381: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', + 382: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', + 383: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', + 384: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', + 385: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', + 386: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', + 387: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF16', + 388: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF17', + 389: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF18', + 390: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF19', + 391: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF20', + 392: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF21', + 393: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF22', + 394: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF23', + 395: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF24', + 396: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF25', + 397: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF26', + 398: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF27', + 399: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF28', + 400: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF29', + 401: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF30', + 402: 'IH_PERF_SEL_RB2_FULL_VF0', + 403: 'IH_PERF_SEL_RB2_FULL_VF1', + 404: 'IH_PERF_SEL_RB2_FULL_VF2', + 405: 'IH_PERF_SEL_RB2_FULL_VF3', + 406: 'IH_PERF_SEL_RB2_FULL_VF4', + 407: 'IH_PERF_SEL_RB2_FULL_VF5', + 408: 'IH_PERF_SEL_RB2_FULL_VF6', + 409: 'IH_PERF_SEL_RB2_FULL_VF7', + 410: 'IH_PERF_SEL_RB2_FULL_VF8', + 411: 'IH_PERF_SEL_RB2_FULL_VF9', + 412: 'IH_PERF_SEL_RB2_FULL_VF10', + 413: 'IH_PERF_SEL_RB2_FULL_VF11', + 414: 'IH_PERF_SEL_RB2_FULL_VF12', + 415: 'IH_PERF_SEL_RB2_FULL_VF13', + 416: 'IH_PERF_SEL_RB2_FULL_VF14', + 417: 'IH_PERF_SEL_RB2_FULL_VF15', + 418: 'IH_PERF_SEL_RB2_FULL_VF16', + 419: 'IH_PERF_SEL_RB2_FULL_VF17', + 420: 'IH_PERF_SEL_RB2_FULL_VF18', + 421: 'IH_PERF_SEL_RB2_FULL_VF19', + 422: 'IH_PERF_SEL_RB2_FULL_VF20', + 423: 'IH_PERF_SEL_RB2_FULL_VF21', + 424: 'IH_PERF_SEL_RB2_FULL_VF22', + 425: 'IH_PERF_SEL_RB2_FULL_VF23', + 426: 'IH_PERF_SEL_RB2_FULL_VF24', + 427: 'IH_PERF_SEL_RB2_FULL_VF25', + 428: 'IH_PERF_SEL_RB2_FULL_VF26', + 429: 'IH_PERF_SEL_RB2_FULL_VF27', + 430: 'IH_PERF_SEL_RB2_FULL_VF28', + 431: 'IH_PERF_SEL_RB2_FULL_VF29', + 432: 'IH_PERF_SEL_RB2_FULL_VF30', + 433: 'IH_PERF_SEL_RB2_OVERFLOW_VF0', + 434: 'IH_PERF_SEL_RB2_OVERFLOW_VF1', + 435: 'IH_PERF_SEL_RB2_OVERFLOW_VF2', + 436: 'IH_PERF_SEL_RB2_OVERFLOW_VF3', + 437: 'IH_PERF_SEL_RB2_OVERFLOW_VF4', + 438: 'IH_PERF_SEL_RB2_OVERFLOW_VF5', + 439: 'IH_PERF_SEL_RB2_OVERFLOW_VF6', + 440: 'IH_PERF_SEL_RB2_OVERFLOW_VF7', + 441: 'IH_PERF_SEL_RB2_OVERFLOW_VF8', + 442: 'IH_PERF_SEL_RB2_OVERFLOW_VF9', + 443: 'IH_PERF_SEL_RB2_OVERFLOW_VF10', + 444: 'IH_PERF_SEL_RB2_OVERFLOW_VF11', + 445: 'IH_PERF_SEL_RB2_OVERFLOW_VF12', + 446: 'IH_PERF_SEL_RB2_OVERFLOW_VF13', + 447: 'IH_PERF_SEL_RB2_OVERFLOW_VF14', + 448: 'IH_PERF_SEL_RB2_OVERFLOW_VF15', + 449: 'IH_PERF_SEL_RB2_OVERFLOW_VF16', + 450: 'IH_PERF_SEL_RB2_OVERFLOW_VF17', + 451: 'IH_PERF_SEL_RB2_OVERFLOW_VF18', + 452: 'IH_PERF_SEL_RB2_OVERFLOW_VF19', + 453: 'IH_PERF_SEL_RB2_OVERFLOW_VF20', + 454: 'IH_PERF_SEL_RB2_OVERFLOW_VF21', + 455: 'IH_PERF_SEL_RB2_OVERFLOW_VF22', + 456: 'IH_PERF_SEL_RB2_OVERFLOW_VF23', + 457: 'IH_PERF_SEL_RB2_OVERFLOW_VF24', + 458: 'IH_PERF_SEL_RB2_OVERFLOW_VF25', + 459: 'IH_PERF_SEL_RB2_OVERFLOW_VF26', + 460: 'IH_PERF_SEL_RB2_OVERFLOW_VF27', + 461: 'IH_PERF_SEL_RB2_OVERFLOW_VF28', + 462: 'IH_PERF_SEL_RB2_OVERFLOW_VF29', + 463: 'IH_PERF_SEL_RB2_OVERFLOW_VF30', + 464: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', + 465: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', + 466: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', + 467: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', + 468: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', + 469: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', + 470: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', + 471: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', + 472: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', + 473: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', + 474: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', + 475: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', + 476: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', + 477: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', + 478: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', + 479: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', + 480: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF16', + 481: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF17', + 482: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF18', + 483: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF19', + 484: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF20', + 485: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF21', + 486: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF22', + 487: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF23', + 488: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF24', + 489: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF25', + 490: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF26', + 491: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF27', + 492: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF28', + 493: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF29', + 494: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF30', + 495: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', + 496: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', + 497: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', + 498: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', + 499: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', + 500: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', + 501: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', + 502: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', + 503: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', + 504: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', + 505: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', + 506: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', + 507: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', + 508: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', + 509: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', + 510: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', + 511: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF16', + 512: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF17', + 513: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF18', + 514: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF19', + 515: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF20', + 516: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF21', + 517: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF22', + 518: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF23', + 519: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF24', + 520: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF25', + 521: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF26', + 522: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF27', + 523: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF28', + 524: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF29', + 525: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF30', + 526: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', + 527: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', + 528: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', + 529: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', + 530: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', + 531: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', + 532: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', + 533: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', + 534: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', + 535: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', + 536: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', + 537: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', + 538: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', + 539: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', + 540: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', + 541: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', + 542: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', + 543: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16', + 544: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17', + 545: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18', + 546: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19', + 547: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20', + 548: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21', + 549: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22', + 550: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23', + 551: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24', + 552: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25', + 553: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26', + 554: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27', + 555: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28', + 556: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29', + 557: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30', + 558: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', + 559: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', + 560: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', + 561: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', + 562: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', + 563: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', + 564: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', + 565: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', + 566: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', + 567: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', + 568: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', + 569: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', + 570: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', + 571: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', + 572: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', + 573: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', + 574: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', + 575: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16', + 576: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17', + 577: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18', + 578: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19', + 579: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20', + 580: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21', + 581: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22', + 582: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23', + 583: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24', + 584: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25', + 585: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26', + 586: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27', + 587: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28', + 588: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29', + 589: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30', + 590: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', + 591: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', + 592: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', + 593: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', + 594: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', + 595: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', + 596: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', + 597: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', + 598: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', + 599: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', + 600: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', + 601: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', + 602: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', + 603: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', + 604: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', + 605: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', + 606: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', + 607: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16', + 608: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17', + 609: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18', + 610: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19', + 611: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20', + 612: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21', + 613: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22', + 614: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23', + 615: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24', + 616: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25', + 617: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26', + 618: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27', + 619: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28', + 620: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29', + 621: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30', + 622: 'IH_PERF_SEL_RB0_LOAD_RPTR', + 623: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', + 624: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', + 625: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', + 626: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', + 627: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', + 628: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', + 629: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', + 630: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', + 631: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', + 632: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', + 633: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', + 634: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', + 635: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', + 636: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', + 637: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', + 638: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', + 639: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF16', + 640: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF17', + 641: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF18', + 642: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF19', + 643: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF20', + 644: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF21', + 645: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF22', + 646: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF23', + 647: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF24', + 648: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF25', + 649: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF26', + 650: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF27', + 651: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF28', + 652: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF29', + 653: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF30', + 654: 'IH_PERF_SEL_RB1_LOAD_RPTR', + 655: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', + 656: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', + 657: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', + 658: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', + 659: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', + 660: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', + 661: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', + 662: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', + 663: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', + 664: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', + 665: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', + 666: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', + 667: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', + 668: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', + 669: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', + 670: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', + 671: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF16', + 672: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF17', + 673: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF18', + 674: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF19', + 675: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF20', + 676: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF21', + 677: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF22', + 678: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF23', + 679: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF24', + 680: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF25', + 681: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF26', + 682: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF27', + 683: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF28', + 684: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF29', + 685: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF30', + 686: 'IH_PERF_SEL_RB2_LOAD_RPTR', + 687: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', + 688: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', + 689: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', + 690: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', + 691: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', + 692: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', + 693: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', + 694: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', + 695: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', + 696: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', + 697: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', + 698: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', + 699: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', + 700: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', + 701: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', + 702: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', + 703: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF16', + 704: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF17', + 705: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF18', + 706: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF19', + 707: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF20', + 708: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF21', + 709: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF22', + 710: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF23', + 711: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF24', + 712: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF25', + 713: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF26', + 714: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF27', + 715: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF28', + 716: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF29', + 717: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF30', +} +IH_PERF_SEL_CYCLE = 0 +IH_PERF_SEL_IDLE = 1 +IH_PERF_SEL_INPUT_IDLE = 2 +IH_PERF_SEL_BUFFER_IDLE = 3 +IH_PERF_SEL_RB0_FULL = 4 +IH_PERF_SEL_RB0_OVERFLOW = 5 +IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6 +IH_PERF_SEL_RB0_WPTR_WRAP = 7 +IH_PERF_SEL_RB0_RPTR_WRAP = 8 +IH_PERF_SEL_MC_WR_IDLE = 9 +IH_PERF_SEL_MC_WR_COUNT = 10 +IH_PERF_SEL_MC_WR_STALL = 11 +IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12 +IH_PERF_SEL_MC_WR_CLEAN_STALL = 13 +IH_PERF_SEL_BIF_LINE0_RISING = 14 +IH_PERF_SEL_BIF_LINE0_FALLING = 15 +IH_PERF_SEL_RB1_FULL = 16 +IH_PERF_SEL_RB1_OVERFLOW = 17 +IH_PERF_SEL_COOKIE_REC_ERROR = 18 +IH_PERF_SEL_RB1_WPTR_WRAP = 19 +IH_PERF_SEL_RB1_RPTR_WRAP = 20 +IH_PERF_SEL_RB2_FULL = 21 +IH_PERF_SEL_RB2_OVERFLOW = 22 +IH_PERF_SEL_CLIENT_CREDIT_ERROR = 23 +IH_PERF_SEL_RB2_WPTR_WRAP = 24 +IH_PERF_SEL_RB2_RPTR_WRAP = 25 +IH_PERF_SEL_STORM_CLIENT_INT_DROP = 26 +IH_PERF_SEL_SELF_IV_VALID = 27 +IH_PERF_SEL_BUFFER_FIFO_FULL = 28 +IH_PERF_SEL_RB0_FULL_VF0 = 29 +IH_PERF_SEL_RB0_FULL_VF1 = 30 +IH_PERF_SEL_RB0_FULL_VF2 = 31 +IH_PERF_SEL_RB0_FULL_VF3 = 32 +IH_PERF_SEL_RB0_FULL_VF4 = 33 +IH_PERF_SEL_RB0_FULL_VF5 = 34 +IH_PERF_SEL_RB0_FULL_VF6 = 35 +IH_PERF_SEL_RB0_FULL_VF7 = 36 +IH_PERF_SEL_RB0_FULL_VF8 = 37 +IH_PERF_SEL_RB0_FULL_VF9 = 38 +IH_PERF_SEL_RB0_FULL_VF10 = 39 +IH_PERF_SEL_RB0_FULL_VF11 = 40 +IH_PERF_SEL_RB0_FULL_VF12 = 41 +IH_PERF_SEL_RB0_FULL_VF13 = 42 +IH_PERF_SEL_RB0_FULL_VF14 = 43 +IH_PERF_SEL_RB0_FULL_VF15 = 44 +IH_PERF_SEL_RB0_FULL_VF16 = 45 +IH_PERF_SEL_RB0_FULL_VF17 = 46 +IH_PERF_SEL_RB0_FULL_VF18 = 47 +IH_PERF_SEL_RB0_FULL_VF19 = 48 +IH_PERF_SEL_RB0_FULL_VF20 = 49 +IH_PERF_SEL_RB0_FULL_VF21 = 50 +IH_PERF_SEL_RB0_FULL_VF22 = 51 +IH_PERF_SEL_RB0_FULL_VF23 = 52 +IH_PERF_SEL_RB0_FULL_VF24 = 53 +IH_PERF_SEL_RB0_FULL_VF25 = 54 +IH_PERF_SEL_RB0_FULL_VF26 = 55 +IH_PERF_SEL_RB0_FULL_VF27 = 56 +IH_PERF_SEL_RB0_FULL_VF28 = 57 +IH_PERF_SEL_RB0_FULL_VF29 = 58 +IH_PERF_SEL_RB0_FULL_VF30 = 59 +IH_PERF_SEL_RB0_OVERFLOW_VF0 = 60 +IH_PERF_SEL_RB0_OVERFLOW_VF1 = 61 +IH_PERF_SEL_RB0_OVERFLOW_VF2 = 62 +IH_PERF_SEL_RB0_OVERFLOW_VF3 = 63 +IH_PERF_SEL_RB0_OVERFLOW_VF4 = 64 +IH_PERF_SEL_RB0_OVERFLOW_VF5 = 65 +IH_PERF_SEL_RB0_OVERFLOW_VF6 = 66 +IH_PERF_SEL_RB0_OVERFLOW_VF7 = 67 +IH_PERF_SEL_RB0_OVERFLOW_VF8 = 68 +IH_PERF_SEL_RB0_OVERFLOW_VF9 = 69 +IH_PERF_SEL_RB0_OVERFLOW_VF10 = 70 +IH_PERF_SEL_RB0_OVERFLOW_VF11 = 71 +IH_PERF_SEL_RB0_OVERFLOW_VF12 = 72 +IH_PERF_SEL_RB0_OVERFLOW_VF13 = 73 +IH_PERF_SEL_RB0_OVERFLOW_VF14 = 74 +IH_PERF_SEL_RB0_OVERFLOW_VF15 = 75 +IH_PERF_SEL_RB0_OVERFLOW_VF16 = 76 +IH_PERF_SEL_RB0_OVERFLOW_VF17 = 77 +IH_PERF_SEL_RB0_OVERFLOW_VF18 = 78 +IH_PERF_SEL_RB0_OVERFLOW_VF19 = 79 +IH_PERF_SEL_RB0_OVERFLOW_VF20 = 80 +IH_PERF_SEL_RB0_OVERFLOW_VF21 = 81 +IH_PERF_SEL_RB0_OVERFLOW_VF22 = 82 +IH_PERF_SEL_RB0_OVERFLOW_VF23 = 83 +IH_PERF_SEL_RB0_OVERFLOW_VF24 = 84 +IH_PERF_SEL_RB0_OVERFLOW_VF25 = 85 +IH_PERF_SEL_RB0_OVERFLOW_VF26 = 86 +IH_PERF_SEL_RB0_OVERFLOW_VF27 = 87 +IH_PERF_SEL_RB0_OVERFLOW_VF28 = 88 +IH_PERF_SEL_RB0_OVERFLOW_VF29 = 89 +IH_PERF_SEL_RB0_OVERFLOW_VF30 = 90 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 91 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 92 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 93 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 94 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 95 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 96 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 97 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 98 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 99 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 100 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 101 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 102 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 103 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 104 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 105 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 106 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16 = 107 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17 = 108 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18 = 109 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19 = 110 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20 = 111 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21 = 112 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22 = 113 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23 = 114 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24 = 115 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25 = 116 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26 = 117 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27 = 118 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28 = 119 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29 = 120 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30 = 121 +IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 122 +IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 123 +IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 124 +IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 125 +IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 126 +IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 127 +IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 128 +IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 129 +IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 130 +IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 131 +IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 132 +IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 133 +IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 134 +IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 135 +IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 136 +IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 137 +IH_PERF_SEL_RB0_WPTR_WRAP_VF16 = 138 +IH_PERF_SEL_RB0_WPTR_WRAP_VF17 = 139 +IH_PERF_SEL_RB0_WPTR_WRAP_VF18 = 140 +IH_PERF_SEL_RB0_WPTR_WRAP_VF19 = 141 +IH_PERF_SEL_RB0_WPTR_WRAP_VF20 = 142 +IH_PERF_SEL_RB0_WPTR_WRAP_VF21 = 143 +IH_PERF_SEL_RB0_WPTR_WRAP_VF22 = 144 +IH_PERF_SEL_RB0_WPTR_WRAP_VF23 = 145 +IH_PERF_SEL_RB0_WPTR_WRAP_VF24 = 146 +IH_PERF_SEL_RB0_WPTR_WRAP_VF25 = 147 +IH_PERF_SEL_RB0_WPTR_WRAP_VF26 = 148 +IH_PERF_SEL_RB0_WPTR_WRAP_VF27 = 149 +IH_PERF_SEL_RB0_WPTR_WRAP_VF28 = 150 +IH_PERF_SEL_RB0_WPTR_WRAP_VF29 = 151 +IH_PERF_SEL_RB0_WPTR_WRAP_VF30 = 152 +IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 153 +IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 154 +IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 155 +IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 156 +IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 157 +IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 158 +IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 159 +IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 160 +IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 161 +IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 162 +IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 163 +IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 164 +IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 165 +IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 166 +IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 167 +IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 168 +IH_PERF_SEL_RB0_RPTR_WRAP_VF16 = 169 +IH_PERF_SEL_RB0_RPTR_WRAP_VF17 = 170 +IH_PERF_SEL_RB0_RPTR_WRAP_VF18 = 171 +IH_PERF_SEL_RB0_RPTR_WRAP_VF19 = 172 +IH_PERF_SEL_RB0_RPTR_WRAP_VF20 = 173 +IH_PERF_SEL_RB0_RPTR_WRAP_VF21 = 174 +IH_PERF_SEL_RB0_RPTR_WRAP_VF22 = 175 +IH_PERF_SEL_RB0_RPTR_WRAP_VF23 = 176 +IH_PERF_SEL_RB0_RPTR_WRAP_VF24 = 177 +IH_PERF_SEL_RB0_RPTR_WRAP_VF25 = 178 +IH_PERF_SEL_RB0_RPTR_WRAP_VF26 = 179 +IH_PERF_SEL_RB0_RPTR_WRAP_VF27 = 180 +IH_PERF_SEL_RB0_RPTR_WRAP_VF28 = 181 +IH_PERF_SEL_RB0_RPTR_WRAP_VF29 = 182 +IH_PERF_SEL_RB0_RPTR_WRAP_VF30 = 183 +IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 184 +IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 185 +IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 186 +IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 187 +IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 188 +IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 189 +IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 190 +IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 191 +IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 192 +IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 193 +IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 194 +IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 195 +IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 196 +IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 197 +IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 198 +IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 199 +IH_PERF_SEL_BIF_LINE0_RISING_VF16 = 200 +IH_PERF_SEL_BIF_LINE0_RISING_VF17 = 201 +IH_PERF_SEL_BIF_LINE0_RISING_VF18 = 202 +IH_PERF_SEL_BIF_LINE0_RISING_VF19 = 203 +IH_PERF_SEL_BIF_LINE0_RISING_VF20 = 204 +IH_PERF_SEL_BIF_LINE0_RISING_VF21 = 205 +IH_PERF_SEL_BIF_LINE0_RISING_VF22 = 206 +IH_PERF_SEL_BIF_LINE0_RISING_VF23 = 207 +IH_PERF_SEL_BIF_LINE0_RISING_VF24 = 208 +IH_PERF_SEL_BIF_LINE0_RISING_VF25 = 209 +IH_PERF_SEL_BIF_LINE0_RISING_VF26 = 210 +IH_PERF_SEL_BIF_LINE0_RISING_VF27 = 211 +IH_PERF_SEL_BIF_LINE0_RISING_VF28 = 212 +IH_PERF_SEL_BIF_LINE0_RISING_VF29 = 213 +IH_PERF_SEL_BIF_LINE0_RISING_VF30 = 214 +IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 215 +IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 216 +IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 217 +IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 218 +IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 219 +IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 220 +IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 221 +IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 222 +IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 223 +IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 224 +IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 225 +IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 226 +IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 227 +IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 228 +IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 229 +IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 230 +IH_PERF_SEL_BIF_LINE0_FALLING_VF16 = 231 +IH_PERF_SEL_BIF_LINE0_FALLING_VF17 = 232 +IH_PERF_SEL_BIF_LINE0_FALLING_VF18 = 233 +IH_PERF_SEL_BIF_LINE0_FALLING_VF19 = 234 +IH_PERF_SEL_BIF_LINE0_FALLING_VF20 = 235 +IH_PERF_SEL_BIF_LINE0_FALLING_VF21 = 236 +IH_PERF_SEL_BIF_LINE0_FALLING_VF22 = 237 +IH_PERF_SEL_BIF_LINE0_FALLING_VF23 = 238 +IH_PERF_SEL_BIF_LINE0_FALLING_VF24 = 239 +IH_PERF_SEL_BIF_LINE0_FALLING_VF25 = 240 +IH_PERF_SEL_BIF_LINE0_FALLING_VF26 = 241 +IH_PERF_SEL_BIF_LINE0_FALLING_VF27 = 242 +IH_PERF_SEL_BIF_LINE0_FALLING_VF28 = 243 +IH_PERF_SEL_BIF_LINE0_FALLING_VF29 = 244 +IH_PERF_SEL_BIF_LINE0_FALLING_VF30 = 245 +IH_PERF_SEL_CLIENT0_INT = 246 +IH_PERF_SEL_CLIENT1_INT = 247 +IH_PERF_SEL_CLIENT2_INT = 248 +IH_PERF_SEL_CLIENT3_INT = 249 +IH_PERF_SEL_CLIENT4_INT = 250 +IH_PERF_SEL_CLIENT5_INT = 251 +IH_PERF_SEL_CLIENT6_INT = 252 +IH_PERF_SEL_CLIENT7_INT = 253 +IH_PERF_SEL_CLIENT8_INT = 254 +IH_PERF_SEL_CLIENT9_INT = 255 +IH_PERF_SEL_CLIENT10_INT = 256 +IH_PERF_SEL_CLIENT11_INT = 257 +IH_PERF_SEL_CLIENT12_INT = 258 +IH_PERF_SEL_CLIENT13_INT = 259 +IH_PERF_SEL_CLIENT14_INT = 260 +IH_PERF_SEL_CLIENT15_INT = 261 +IH_PERF_SEL_CLIENT16_INT = 262 +IH_PERF_SEL_CLIENT17_INT = 263 +IH_PERF_SEL_CLIENT18_INT = 264 +IH_PERF_SEL_CLIENT19_INT = 265 +IH_PERF_SEL_CLIENT20_INT = 266 +IH_PERF_SEL_CLIENT21_INT = 267 +IH_PERF_SEL_CLIENT22_INT = 268 +IH_PERF_SEL_CLIENT23_INT = 269 +IH_PERF_SEL_CLIENT24_INT = 270 +IH_PERF_SEL_CLIENT25_INT = 271 +IH_PERF_SEL_CLIENT26_INT = 272 +IH_PERF_SEL_CLIENT27_INT = 273 +IH_PERF_SEL_CLIENT28_INT = 274 +IH_PERF_SEL_CLIENT29_INT = 275 +IH_PERF_SEL_CLIENT30_INT = 276 +IH_PERF_SEL_CLIENT31_INT = 277 +IH_PERF_SEL_RB1_FULL_VF0 = 278 +IH_PERF_SEL_RB1_FULL_VF1 = 279 +IH_PERF_SEL_RB1_FULL_VF2 = 280 +IH_PERF_SEL_RB1_FULL_VF3 = 281 +IH_PERF_SEL_RB1_FULL_VF4 = 282 +IH_PERF_SEL_RB1_FULL_VF5 = 283 +IH_PERF_SEL_RB1_FULL_VF6 = 284 +IH_PERF_SEL_RB1_FULL_VF7 = 285 +IH_PERF_SEL_RB1_FULL_VF8 = 286 +IH_PERF_SEL_RB1_FULL_VF9 = 287 +IH_PERF_SEL_RB1_FULL_VF10 = 288 +IH_PERF_SEL_RB1_FULL_VF11 = 289 +IH_PERF_SEL_RB1_FULL_VF12 = 290 +IH_PERF_SEL_RB1_FULL_VF13 = 291 +IH_PERF_SEL_RB1_FULL_VF14 = 292 +IH_PERF_SEL_RB1_FULL_VF15 = 293 +IH_PERF_SEL_RB1_FULL_VF16 = 294 +IH_PERF_SEL_RB1_FULL_VF17 = 295 +IH_PERF_SEL_RB1_FULL_VF18 = 296 +IH_PERF_SEL_RB1_FULL_VF19 = 297 +IH_PERF_SEL_RB1_FULL_VF20 = 298 +IH_PERF_SEL_RB1_FULL_VF21 = 299 +IH_PERF_SEL_RB1_FULL_VF22 = 300 +IH_PERF_SEL_RB1_FULL_VF23 = 301 +IH_PERF_SEL_RB1_FULL_VF24 = 302 +IH_PERF_SEL_RB1_FULL_VF25 = 303 +IH_PERF_SEL_RB1_FULL_VF26 = 304 +IH_PERF_SEL_RB1_FULL_VF27 = 305 +IH_PERF_SEL_RB1_FULL_VF28 = 306 +IH_PERF_SEL_RB1_FULL_VF29 = 307 +IH_PERF_SEL_RB1_FULL_VF30 = 308 +IH_PERF_SEL_RB1_OVERFLOW_VF0 = 309 +IH_PERF_SEL_RB1_OVERFLOW_VF1 = 310 +IH_PERF_SEL_RB1_OVERFLOW_VF2 = 311 +IH_PERF_SEL_RB1_OVERFLOW_VF3 = 312 +IH_PERF_SEL_RB1_OVERFLOW_VF4 = 313 +IH_PERF_SEL_RB1_OVERFLOW_VF5 = 314 +IH_PERF_SEL_RB1_OVERFLOW_VF6 = 315 +IH_PERF_SEL_RB1_OVERFLOW_VF7 = 316 +IH_PERF_SEL_RB1_OVERFLOW_VF8 = 317 +IH_PERF_SEL_RB1_OVERFLOW_VF9 = 318 +IH_PERF_SEL_RB1_OVERFLOW_VF10 = 319 +IH_PERF_SEL_RB1_OVERFLOW_VF11 = 320 +IH_PERF_SEL_RB1_OVERFLOW_VF12 = 321 +IH_PERF_SEL_RB1_OVERFLOW_VF13 = 322 +IH_PERF_SEL_RB1_OVERFLOW_VF14 = 323 +IH_PERF_SEL_RB1_OVERFLOW_VF15 = 324 +IH_PERF_SEL_RB1_OVERFLOW_VF16 = 325 +IH_PERF_SEL_RB1_OVERFLOW_VF17 = 326 +IH_PERF_SEL_RB1_OVERFLOW_VF18 = 327 +IH_PERF_SEL_RB1_OVERFLOW_VF19 = 328 +IH_PERF_SEL_RB1_OVERFLOW_VF20 = 329 +IH_PERF_SEL_RB1_OVERFLOW_VF21 = 330 +IH_PERF_SEL_RB1_OVERFLOW_VF22 = 331 +IH_PERF_SEL_RB1_OVERFLOW_VF23 = 332 +IH_PERF_SEL_RB1_OVERFLOW_VF24 = 333 +IH_PERF_SEL_RB1_OVERFLOW_VF25 = 334 +IH_PERF_SEL_RB1_OVERFLOW_VF26 = 335 +IH_PERF_SEL_RB1_OVERFLOW_VF27 = 336 +IH_PERF_SEL_RB1_OVERFLOW_VF28 = 337 +IH_PERF_SEL_RB1_OVERFLOW_VF29 = 338 +IH_PERF_SEL_RB1_OVERFLOW_VF30 = 339 +IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 340 +IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 341 +IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 342 +IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 343 +IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 344 +IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 345 +IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 346 +IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 347 +IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 348 +IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 349 +IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 350 +IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 351 +IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 352 +IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 353 +IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 354 +IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 355 +IH_PERF_SEL_RB1_WPTR_WRAP_VF16 = 356 +IH_PERF_SEL_RB1_WPTR_WRAP_VF17 = 357 +IH_PERF_SEL_RB1_WPTR_WRAP_VF18 = 358 +IH_PERF_SEL_RB1_WPTR_WRAP_VF19 = 359 +IH_PERF_SEL_RB1_WPTR_WRAP_VF20 = 360 +IH_PERF_SEL_RB1_WPTR_WRAP_VF21 = 361 +IH_PERF_SEL_RB1_WPTR_WRAP_VF22 = 362 +IH_PERF_SEL_RB1_WPTR_WRAP_VF23 = 363 +IH_PERF_SEL_RB1_WPTR_WRAP_VF24 = 364 +IH_PERF_SEL_RB1_WPTR_WRAP_VF25 = 365 +IH_PERF_SEL_RB1_WPTR_WRAP_VF26 = 366 +IH_PERF_SEL_RB1_WPTR_WRAP_VF27 = 367 +IH_PERF_SEL_RB1_WPTR_WRAP_VF28 = 368 +IH_PERF_SEL_RB1_WPTR_WRAP_VF29 = 369 +IH_PERF_SEL_RB1_WPTR_WRAP_VF30 = 370 +IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 371 +IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 372 +IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 373 +IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 374 +IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 375 +IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 376 +IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 377 +IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 378 +IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 379 +IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 380 +IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 381 +IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 382 +IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 383 +IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 384 +IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 385 +IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 386 +IH_PERF_SEL_RB1_RPTR_WRAP_VF16 = 387 +IH_PERF_SEL_RB1_RPTR_WRAP_VF17 = 388 +IH_PERF_SEL_RB1_RPTR_WRAP_VF18 = 389 +IH_PERF_SEL_RB1_RPTR_WRAP_VF19 = 390 +IH_PERF_SEL_RB1_RPTR_WRAP_VF20 = 391 +IH_PERF_SEL_RB1_RPTR_WRAP_VF21 = 392 +IH_PERF_SEL_RB1_RPTR_WRAP_VF22 = 393 +IH_PERF_SEL_RB1_RPTR_WRAP_VF23 = 394 +IH_PERF_SEL_RB1_RPTR_WRAP_VF24 = 395 +IH_PERF_SEL_RB1_RPTR_WRAP_VF25 = 396 +IH_PERF_SEL_RB1_RPTR_WRAP_VF26 = 397 +IH_PERF_SEL_RB1_RPTR_WRAP_VF27 = 398 +IH_PERF_SEL_RB1_RPTR_WRAP_VF28 = 399 +IH_PERF_SEL_RB1_RPTR_WRAP_VF29 = 400 +IH_PERF_SEL_RB1_RPTR_WRAP_VF30 = 401 +IH_PERF_SEL_RB2_FULL_VF0 = 402 +IH_PERF_SEL_RB2_FULL_VF1 = 403 +IH_PERF_SEL_RB2_FULL_VF2 = 404 +IH_PERF_SEL_RB2_FULL_VF3 = 405 +IH_PERF_SEL_RB2_FULL_VF4 = 406 +IH_PERF_SEL_RB2_FULL_VF5 = 407 +IH_PERF_SEL_RB2_FULL_VF6 = 408 +IH_PERF_SEL_RB2_FULL_VF7 = 409 +IH_PERF_SEL_RB2_FULL_VF8 = 410 +IH_PERF_SEL_RB2_FULL_VF9 = 411 +IH_PERF_SEL_RB2_FULL_VF10 = 412 +IH_PERF_SEL_RB2_FULL_VF11 = 413 +IH_PERF_SEL_RB2_FULL_VF12 = 414 +IH_PERF_SEL_RB2_FULL_VF13 = 415 +IH_PERF_SEL_RB2_FULL_VF14 = 416 +IH_PERF_SEL_RB2_FULL_VF15 = 417 +IH_PERF_SEL_RB2_FULL_VF16 = 418 +IH_PERF_SEL_RB2_FULL_VF17 = 419 +IH_PERF_SEL_RB2_FULL_VF18 = 420 +IH_PERF_SEL_RB2_FULL_VF19 = 421 +IH_PERF_SEL_RB2_FULL_VF20 = 422 +IH_PERF_SEL_RB2_FULL_VF21 = 423 +IH_PERF_SEL_RB2_FULL_VF22 = 424 +IH_PERF_SEL_RB2_FULL_VF23 = 425 +IH_PERF_SEL_RB2_FULL_VF24 = 426 +IH_PERF_SEL_RB2_FULL_VF25 = 427 +IH_PERF_SEL_RB2_FULL_VF26 = 428 +IH_PERF_SEL_RB2_FULL_VF27 = 429 +IH_PERF_SEL_RB2_FULL_VF28 = 430 +IH_PERF_SEL_RB2_FULL_VF29 = 431 +IH_PERF_SEL_RB2_FULL_VF30 = 432 +IH_PERF_SEL_RB2_OVERFLOW_VF0 = 433 +IH_PERF_SEL_RB2_OVERFLOW_VF1 = 434 +IH_PERF_SEL_RB2_OVERFLOW_VF2 = 435 +IH_PERF_SEL_RB2_OVERFLOW_VF3 = 436 +IH_PERF_SEL_RB2_OVERFLOW_VF4 = 437 +IH_PERF_SEL_RB2_OVERFLOW_VF5 = 438 +IH_PERF_SEL_RB2_OVERFLOW_VF6 = 439 +IH_PERF_SEL_RB2_OVERFLOW_VF7 = 440 +IH_PERF_SEL_RB2_OVERFLOW_VF8 = 441 +IH_PERF_SEL_RB2_OVERFLOW_VF9 = 442 +IH_PERF_SEL_RB2_OVERFLOW_VF10 = 443 +IH_PERF_SEL_RB2_OVERFLOW_VF11 = 444 +IH_PERF_SEL_RB2_OVERFLOW_VF12 = 445 +IH_PERF_SEL_RB2_OVERFLOW_VF13 = 446 +IH_PERF_SEL_RB2_OVERFLOW_VF14 = 447 +IH_PERF_SEL_RB2_OVERFLOW_VF15 = 448 +IH_PERF_SEL_RB2_OVERFLOW_VF16 = 449 +IH_PERF_SEL_RB2_OVERFLOW_VF17 = 450 +IH_PERF_SEL_RB2_OVERFLOW_VF18 = 451 +IH_PERF_SEL_RB2_OVERFLOW_VF19 = 452 +IH_PERF_SEL_RB2_OVERFLOW_VF20 = 453 +IH_PERF_SEL_RB2_OVERFLOW_VF21 = 454 +IH_PERF_SEL_RB2_OVERFLOW_VF22 = 455 +IH_PERF_SEL_RB2_OVERFLOW_VF23 = 456 +IH_PERF_SEL_RB2_OVERFLOW_VF24 = 457 +IH_PERF_SEL_RB2_OVERFLOW_VF25 = 458 +IH_PERF_SEL_RB2_OVERFLOW_VF26 = 459 +IH_PERF_SEL_RB2_OVERFLOW_VF27 = 460 +IH_PERF_SEL_RB2_OVERFLOW_VF28 = 461 +IH_PERF_SEL_RB2_OVERFLOW_VF29 = 462 +IH_PERF_SEL_RB2_OVERFLOW_VF30 = 463 +IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 464 +IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 465 +IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 466 +IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 467 +IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 468 +IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 469 +IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 470 +IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 471 +IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 472 +IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 473 +IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 474 +IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 475 +IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 476 +IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 477 +IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 478 +IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 479 +IH_PERF_SEL_RB2_WPTR_WRAP_VF16 = 480 +IH_PERF_SEL_RB2_WPTR_WRAP_VF17 = 481 +IH_PERF_SEL_RB2_WPTR_WRAP_VF18 = 482 +IH_PERF_SEL_RB2_WPTR_WRAP_VF19 = 483 +IH_PERF_SEL_RB2_WPTR_WRAP_VF20 = 484 +IH_PERF_SEL_RB2_WPTR_WRAP_VF21 = 485 +IH_PERF_SEL_RB2_WPTR_WRAP_VF22 = 486 +IH_PERF_SEL_RB2_WPTR_WRAP_VF23 = 487 +IH_PERF_SEL_RB2_WPTR_WRAP_VF24 = 488 +IH_PERF_SEL_RB2_WPTR_WRAP_VF25 = 489 +IH_PERF_SEL_RB2_WPTR_WRAP_VF26 = 490 +IH_PERF_SEL_RB2_WPTR_WRAP_VF27 = 491 +IH_PERF_SEL_RB2_WPTR_WRAP_VF28 = 492 +IH_PERF_SEL_RB2_WPTR_WRAP_VF29 = 493 +IH_PERF_SEL_RB2_WPTR_WRAP_VF30 = 494 +IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 495 +IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 496 +IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 497 +IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 498 +IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 499 +IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 500 +IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 501 +IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 502 +IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 503 +IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 504 +IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 505 +IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 506 +IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 507 +IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 508 +IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 509 +IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 510 +IH_PERF_SEL_RB2_RPTR_WRAP_VF16 = 511 +IH_PERF_SEL_RB2_RPTR_WRAP_VF17 = 512 +IH_PERF_SEL_RB2_RPTR_WRAP_VF18 = 513 +IH_PERF_SEL_RB2_RPTR_WRAP_VF19 = 514 +IH_PERF_SEL_RB2_RPTR_WRAP_VF20 = 515 +IH_PERF_SEL_RB2_RPTR_WRAP_VF21 = 516 +IH_PERF_SEL_RB2_RPTR_WRAP_VF22 = 517 +IH_PERF_SEL_RB2_RPTR_WRAP_VF23 = 518 +IH_PERF_SEL_RB2_RPTR_WRAP_VF24 = 519 +IH_PERF_SEL_RB2_RPTR_WRAP_VF25 = 520 +IH_PERF_SEL_RB2_RPTR_WRAP_VF26 = 521 +IH_PERF_SEL_RB2_RPTR_WRAP_VF27 = 522 +IH_PERF_SEL_RB2_RPTR_WRAP_VF28 = 523 +IH_PERF_SEL_RB2_RPTR_WRAP_VF29 = 524 +IH_PERF_SEL_RB2_RPTR_WRAP_VF30 = 525 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 526 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 527 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 528 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 529 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 530 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 531 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 532 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 533 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 534 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 535 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 536 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 537 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 538 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 539 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 540 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 541 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 542 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16 = 543 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17 = 544 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18 = 545 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19 = 546 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20 = 547 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21 = 548 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22 = 549 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23 = 550 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24 = 551 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25 = 552 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26 = 553 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27 = 554 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28 = 555 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29 = 556 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30 = 557 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 558 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 559 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 560 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 561 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 562 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 563 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 564 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 565 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 566 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 567 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 568 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 569 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 570 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 571 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 572 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 573 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 574 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16 = 575 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17 = 576 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18 = 577 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19 = 578 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20 = 579 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21 = 580 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22 = 581 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23 = 582 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24 = 583 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25 = 584 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26 = 585 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27 = 586 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28 = 587 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29 = 588 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30 = 589 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 590 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 591 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 592 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 593 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 594 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 595 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 596 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 597 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 598 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 599 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 600 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 601 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 602 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 603 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 604 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 605 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 606 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16 = 607 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17 = 608 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18 = 609 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19 = 610 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20 = 611 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21 = 612 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22 = 613 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23 = 614 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24 = 615 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25 = 616 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26 = 617 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27 = 618 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28 = 619 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29 = 620 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30 = 621 +IH_PERF_SEL_RB0_LOAD_RPTR = 622 +IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 623 +IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 624 +IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 625 +IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 626 +IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 627 +IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 628 +IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 629 +IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 630 +IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 631 +IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 632 +IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 633 +IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 634 +IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 635 +IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 636 +IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 637 +IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 638 +IH_PERF_SEL_RB0_LOAD_RPTR_VF16 = 639 +IH_PERF_SEL_RB0_LOAD_RPTR_VF17 = 640 +IH_PERF_SEL_RB0_LOAD_RPTR_VF18 = 641 +IH_PERF_SEL_RB0_LOAD_RPTR_VF19 = 642 +IH_PERF_SEL_RB0_LOAD_RPTR_VF20 = 643 +IH_PERF_SEL_RB0_LOAD_RPTR_VF21 = 644 +IH_PERF_SEL_RB0_LOAD_RPTR_VF22 = 645 +IH_PERF_SEL_RB0_LOAD_RPTR_VF23 = 646 +IH_PERF_SEL_RB0_LOAD_RPTR_VF24 = 647 +IH_PERF_SEL_RB0_LOAD_RPTR_VF25 = 648 +IH_PERF_SEL_RB0_LOAD_RPTR_VF26 = 649 +IH_PERF_SEL_RB0_LOAD_RPTR_VF27 = 650 +IH_PERF_SEL_RB0_LOAD_RPTR_VF28 = 651 +IH_PERF_SEL_RB0_LOAD_RPTR_VF29 = 652 +IH_PERF_SEL_RB0_LOAD_RPTR_VF30 = 653 +IH_PERF_SEL_RB1_LOAD_RPTR = 654 +IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 655 +IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 656 +IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 657 +IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 658 +IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 659 +IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 660 +IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 661 +IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 662 +IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 663 +IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 664 +IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 665 +IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 666 +IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 667 +IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 668 +IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 669 +IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 670 +IH_PERF_SEL_RB1_LOAD_RPTR_VF16 = 671 +IH_PERF_SEL_RB1_LOAD_RPTR_VF17 = 672 +IH_PERF_SEL_RB1_LOAD_RPTR_VF18 = 673 +IH_PERF_SEL_RB1_LOAD_RPTR_VF19 = 674 +IH_PERF_SEL_RB1_LOAD_RPTR_VF20 = 675 +IH_PERF_SEL_RB1_LOAD_RPTR_VF21 = 676 +IH_PERF_SEL_RB1_LOAD_RPTR_VF22 = 677 +IH_PERF_SEL_RB1_LOAD_RPTR_VF23 = 678 +IH_PERF_SEL_RB1_LOAD_RPTR_VF24 = 679 +IH_PERF_SEL_RB1_LOAD_RPTR_VF25 = 680 +IH_PERF_SEL_RB1_LOAD_RPTR_VF26 = 681 +IH_PERF_SEL_RB1_LOAD_RPTR_VF27 = 682 +IH_PERF_SEL_RB1_LOAD_RPTR_VF28 = 683 +IH_PERF_SEL_RB1_LOAD_RPTR_VF29 = 684 +IH_PERF_SEL_RB1_LOAD_RPTR_VF30 = 685 +IH_PERF_SEL_RB2_LOAD_RPTR = 686 +IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 687 +IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 688 +IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 689 +IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 690 +IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 691 +IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 692 +IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 693 +IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 694 +IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 695 +IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 696 +IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 697 +IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 698 +IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 699 +IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 700 +IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 701 +IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 702 +IH_PERF_SEL_RB2_LOAD_RPTR_VF16 = 703 +IH_PERF_SEL_RB2_LOAD_RPTR_VF17 = 704 +IH_PERF_SEL_RB2_LOAD_RPTR_VF18 = 705 +IH_PERF_SEL_RB2_LOAD_RPTR_VF19 = 706 +IH_PERF_SEL_RB2_LOAD_RPTR_VF20 = 707 +IH_PERF_SEL_RB2_LOAD_RPTR_VF21 = 708 +IH_PERF_SEL_RB2_LOAD_RPTR_VF22 = 709 +IH_PERF_SEL_RB2_LOAD_RPTR_VF23 = 710 +IH_PERF_SEL_RB2_LOAD_RPTR_VF24 = 711 +IH_PERF_SEL_RB2_LOAD_RPTR_VF25 = 712 +IH_PERF_SEL_RB2_LOAD_RPTR_VF26 = 713 +IH_PERF_SEL_RB2_LOAD_RPTR_VF27 = 714 +IH_PERF_SEL_RB2_LOAD_RPTR_VF28 = 715 +IH_PERF_SEL_RB2_LOAD_RPTR_VF29 = 716 +IH_PERF_SEL_RB2_LOAD_RPTR_VF30 = 717 +IH_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'IH_CLIENT_TYPE' +IH_CLIENT_TYPE__enumvalues = { + 0: 'IH_GFX_VMID_CLIENT', + 1: 'IH_MM_VMID_CLIENT', + 2: 'IH_MULTI_VMID_CLIENT', + 3: 'IH_CLIENT_TYPE_RESERVED', +} +IH_GFX_VMID_CLIENT = 0 +IH_MM_VMID_CLIENT = 1 +IH_MULTI_VMID_CLIENT = 2 +IH_CLIENT_TYPE_RESERVED = 3 +IH_CLIENT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'IH_RING_ID' +IH_RING_ID__enumvalues = { + 0: 'IH_RING_ID_INTERRUPT', + 1: 'IH_RING_ID_REQUEST', + 2: 'IH_RING_ID_TRANSLATION', + 3: 'IH_RING_ID_RESERVED', +} +IH_RING_ID_INTERRUPT = 0 +IH_RING_ID_REQUEST = 1 +IH_RING_ID_TRANSLATION = 2 +IH_RING_ID_RESERVED = 3 +IH_RING_ID = ctypes.c_uint32 # enum + +# values for enumeration 'IH_VF_RB_SELECT' +IH_VF_RB_SELECT__enumvalues = { + 0: 'IH_VF_RB_SELECT_CLIENT_FCN_ID', + 1: 'IH_VF_RB_SELECT_IH_FCN_ID', + 2: 'IH_VF_RB_SELECT_PF', + 3: 'IH_VF_RB_SELECT_RESERVED', +} +IH_VF_RB_SELECT_CLIENT_FCN_ID = 0 +IH_VF_RB_SELECT_IH_FCN_ID = 1 +IH_VF_RB_SELECT_PF = 2 +IH_VF_RB_SELECT_RESERVED = 3 +IH_VF_RB_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'IH_INTERFACE_TYPE' +IH_INTERFACE_TYPE__enumvalues = { + 0: 'IH_LEGACY_INTERFACE', + 1: 'IH_REGISTER_WRITE_INTERFACE', +} +IH_LEGACY_INTERFACE = 0 +IH_REGISTER_WRITE_INTERFACE = 1 +IH_INTERFACE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SEM_PERF_SEL' +SEM_PERF_SEL__enumvalues = { + 0: 'SEM_PERF_SEL_CYCLE', + 1: 'SEM_PERF_SEL_IDLE', + 2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', + 3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', + 4: 'SEM_PERF_SEL_UVD_REQ_SIGNAL', + 5: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', + 6: 'SEM_PERF_SEL_ACP_REQ_SIGNAL', + 7: 'SEM_PERF_SEL_ISP_REQ_SIGNAL', + 8: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', + 9: 'SEM_PERF_SEL_VP8_REQ_SIGNAL', + 10: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', + 11: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', + 12: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', + 13: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', + 14: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', + 15: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', + 16: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', + 17: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', + 18: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', + 19: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', + 20: 'SEM_PERF_SEL_SDMA0_REQ_WAIT', + 21: 'SEM_PERF_SEL_SDMA1_REQ_WAIT', + 22: 'SEM_PERF_SEL_UVD_REQ_WAIT', + 23: 'SEM_PERF_SEL_VCE0_REQ_WAIT', + 24: 'SEM_PERF_SEL_ACP_REQ_WAIT', + 25: 'SEM_PERF_SEL_ISP_REQ_WAIT', + 26: 'SEM_PERF_SEL_VCE1_REQ_WAIT', + 27: 'SEM_PERF_SEL_VP8_REQ_WAIT', + 28: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', + 29: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', + 30: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', + 31: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', + 32: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', + 33: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', + 34: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', + 35: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', + 36: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', + 37: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', + 38: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', + 39: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', + 40: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', + 41: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', + 42: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', + 43: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', + 44: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', + 45: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', + 46: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', + 47: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', + 48: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', + 49: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', + 50: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', + 51: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', + 52: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', + 53: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', + 54: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', + 55: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', + 56: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', + 57: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', + 58: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', + 59: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', + 60: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', + 61: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', + 62: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', + 63: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', + 64: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', + 65: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', + 66: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', + 67: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', + 68: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', + 69: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', + 70: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', + 71: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', + 72: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', + 73: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', + 74: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', + 75: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', + 76: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', + 77: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', + 78: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', + 79: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', + 80: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', + 81: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', + 82: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', + 83: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', + 84: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', + 85: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', + 86: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', + 87: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', + 88: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', + 89: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', + 90: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', + 91: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', + 92: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', + 93: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', + 94: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', + 95: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', + 96: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', + 97: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', + 98: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', + 99: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', + 100: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', + 101: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', + 102: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', + 103: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', + 104: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', + 105: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', + 106: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', + 107: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', + 108: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', + 109: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', + 110: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', + 111: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', + 112: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', + 113: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', + 114: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', + 115: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', + 116: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', + 117: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', + 118: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', + 119: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', + 120: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', + 121: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', + 122: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', + 123: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', + 124: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', + 125: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', + 126: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', + 127: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', + 128: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', + 129: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', + 130: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', + 131: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', + 132: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', + 133: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', + 134: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', + 135: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', + 136: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', + 137: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', + 138: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', + 139: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', + 140: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', + 141: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', + 142: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', + 143: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', + 144: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', + 145: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', + 146: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', + 147: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', + 148: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', + 149: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', + 150: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', + 151: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', + 152: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', + 153: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', + 154: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', + 155: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', + 156: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', + 157: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', + 158: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', + 159: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', + 160: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', + 161: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', + 162: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', + 163: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', + 164: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', + 165: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', + 166: 'SEM_PERF_SEL_MC_RD_REQ', + 167: 'SEM_PERF_SEL_MC_RD_RET', + 168: 'SEM_PERF_SEL_MC_WR_REQ', + 169: 'SEM_PERF_SEL_MC_WR_RET', + 170: 'SEM_PERF_SEL_ATC_REQ', + 171: 'SEM_PERF_SEL_ATC_RET', + 172: 'SEM_PERF_SEL_ATC_XNACK', + 173: 'SEM_PERF_SEL_ATC_INVALIDATION', + 174: 'SEM_PERF_SEL_ATC_VM_INVALIDATION', +} +SEM_PERF_SEL_CYCLE = 0 +SEM_PERF_SEL_IDLE = 1 +SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2 +SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3 +SEM_PERF_SEL_UVD_REQ_SIGNAL = 4 +SEM_PERF_SEL_VCE0_REQ_SIGNAL = 5 +SEM_PERF_SEL_ACP_REQ_SIGNAL = 6 +SEM_PERF_SEL_ISP_REQ_SIGNAL = 7 +SEM_PERF_SEL_VCE1_REQ_SIGNAL = 8 +SEM_PERF_SEL_VP8_REQ_SIGNAL = 9 +SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 10 +SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 11 +SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 12 +SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 13 +SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 14 +SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 15 +SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 16 +SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 17 +SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 18 +SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 19 +SEM_PERF_SEL_SDMA0_REQ_WAIT = 20 +SEM_PERF_SEL_SDMA1_REQ_WAIT = 21 +SEM_PERF_SEL_UVD_REQ_WAIT = 22 +SEM_PERF_SEL_VCE0_REQ_WAIT = 23 +SEM_PERF_SEL_ACP_REQ_WAIT = 24 +SEM_PERF_SEL_ISP_REQ_WAIT = 25 +SEM_PERF_SEL_VCE1_REQ_WAIT = 26 +SEM_PERF_SEL_VP8_REQ_WAIT = 27 +SEM_PERF_SEL_CPG_E0_REQ_WAIT = 28 +SEM_PERF_SEL_CPG_E1_REQ_WAIT = 29 +SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 30 +SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 31 +SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 32 +SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 33 +SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 34 +SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 35 +SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 36 +SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 37 +SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 38 +SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 39 +SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 40 +SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 41 +SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 42 +SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 43 +SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 44 +SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 45 +SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 46 +SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 47 +SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 48 +SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 49 +SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 50 +SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 51 +SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 52 +SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 53 +SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 54 +SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 55 +SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 56 +SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 57 +SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 58 +SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 59 +SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 60 +SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 61 +SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 62 +SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 63 +SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 64 +SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 65 +SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 66 +SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 67 +SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 68 +SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 69 +SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 70 +SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 71 +SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 72 +SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 73 +SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 74 +SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 75 +SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 76 +SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 77 +SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 78 +SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 79 +SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 80 +SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 81 +SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 82 +SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 83 +SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 84 +SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 85 +SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 86 +SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 87 +SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 88 +SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 89 +SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 90 +SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 91 +SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 92 +SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 93 +SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 94 +SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 95 +SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 96 +SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 97 +SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 98 +SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 99 +SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 100 +SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 101 +SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 102 +SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 103 +SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 104 +SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 105 +SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 106 +SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 107 +SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 108 +SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 109 +SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 110 +SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 111 +SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 112 +SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 113 +SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 114 +SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 115 +SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 116 +SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 117 +SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 118 +SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 119 +SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 120 +SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 121 +SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 122 +SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 123 +SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 124 +SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 125 +SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 126 +SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 127 +SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 128 +SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 129 +SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 130 +SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 131 +SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 132 +SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 133 +SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 134 +SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 135 +SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 136 +SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 137 +SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 138 +SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 139 +SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 140 +SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 141 +SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 142 +SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 143 +SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 144 +SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 145 +SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 146 +SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 147 +SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 148 +SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 149 +SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 150 +SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 151 +SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 152 +SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 153 +SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 154 +SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 155 +SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 156 +SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 157 +SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 158 +SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 159 +SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 160 +SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 161 +SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 162 +SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 163 +SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 164 +SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 165 +SEM_PERF_SEL_MC_RD_REQ = 166 +SEM_PERF_SEL_MC_RD_RET = 167 +SEM_PERF_SEL_MC_WR_REQ = 168 +SEM_PERF_SEL_MC_WR_RET = 169 +SEM_PERF_SEL_ATC_REQ = 170 +SEM_PERF_SEL_ATC_RET = 171 +SEM_PERF_SEL_ATC_XNACK = 172 +SEM_PERF_SEL_ATC_INVALIDATION = 173 +SEM_PERF_SEL_ATC_VM_INVALIDATION = 174 +SEM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'EFC_SURFACE_PIXEL_FORMAT' +EFC_SURFACE_PIXEL_FORMAT__enumvalues = { + 1: 'EFC_ARGB1555', + 2: 'EFC_RGBA5551', + 3: 'EFC_RGB565', + 4: 'EFC_BGR565', + 5: 'EFC_ARGB4444', + 6: 'EFC_RGBA4444', + 8: 'EFC_ARGB8888', + 9: 'EFC_RGBA8888', + 10: 'EFC_ARGB2101010', + 11: 'EFC_RGBA1010102', + 12: 'EFC_AYCrCb8888', + 13: 'EFC_YCrCbA8888', + 14: 'EFC_ACrYCb8888', + 15: 'EFC_CrYCbA8888', + 16: 'EFC_ARGB16161616_10MSB', + 17: 'EFC_RGBA16161616_10MSB', + 18: 'EFC_ARGB16161616_10LSB', + 19: 'EFC_RGBA16161616_10LSB', + 20: 'EFC_ARGB16161616_12MSB', + 21: 'EFC_RGBA16161616_12MSB', + 22: 'EFC_ARGB16161616_12LSB', + 23: 'EFC_RGBA16161616_12LSB', + 24: 'EFC_ARGB16161616_FLOAT', + 25: 'EFC_RGBA16161616_FLOAT', + 26: 'EFC_ARGB16161616_UNORM', + 27: 'EFC_RGBA16161616_UNORM', + 28: 'EFC_ARGB16161616_SNORM', + 29: 'EFC_RGBA16161616_SNORM', + 32: 'EFC_AYCrCb16161616_10MSB', + 33: 'EFC_AYCrCb16161616_10LSB', + 34: 'EFC_YCrCbA16161616_10MSB', + 35: 'EFC_YCrCbA16161616_10LSB', + 36: 'EFC_ACrYCb16161616_10MSB', + 37: 'EFC_ACrYCb16161616_10LSB', + 38: 'EFC_CrYCbA16161616_10MSB', + 39: 'EFC_CrYCbA16161616_10LSB', + 40: 'EFC_AYCrCb16161616_12MSB', + 41: 'EFC_AYCrCb16161616_12LSB', + 42: 'EFC_YCrCbA16161616_12MSB', + 43: 'EFC_YCrCbA16161616_12LSB', + 44: 'EFC_ACrYCb16161616_12MSB', + 45: 'EFC_ACrYCb16161616_12LSB', + 46: 'EFC_CrYCbA16161616_12MSB', + 47: 'EFC_CrYCbA16161616_12LSB', + 64: 'EFC_Y8_CrCb88_420_PLANAR', + 65: 'EFC_Y8_CbCr88_420_PLANAR', + 66: 'EFC_Y10_CrCb1010_420_PLANAR', + 67: 'EFC_Y10_CbCr1010_420_PLANAR', + 68: 'EFC_Y12_CrCb1212_420_PLANAR', + 69: 'EFC_Y12_CbCr1212_420_PLANAR', + 72: 'EFC_YCrYCb8888_422_PACKED', + 73: 'EFC_YCbYCr8888_422_PACKED', + 74: 'EFC_CrYCbY8888_422_PACKED', + 75: 'EFC_CbYCrY8888_422_PACKED', + 76: 'EFC_YCrYCb10101010_422_PACKED', + 77: 'EFC_YCbYCr10101010_422_PACKED', + 78: 'EFC_CrYCbY10101010_422_PACKED', + 79: 'EFC_CbYCrY10101010_422_PACKED', + 80: 'EFC_YCrYCb12121212_422_PACKED', + 81: 'EFC_YCbYCr12121212_422_PACKED', + 82: 'EFC_CrYCbY12121212_422_PACKED', + 83: 'EFC_CbYCrY12121212_422_PACKED', + 112: 'EFC_RGB111110_FIX', + 113: 'EFC_BGR101111_FIX', + 114: 'EFC_ACrYCb2101010', + 115: 'EFC_CrYCbA1010102', + 118: 'EFC_RGB111110_FLOAT', + 119: 'EFC_BGR101111_FLOAT', + 120: 'EFC_MONO_8', + 121: 'EFC_MONO_10MSB', + 122: 'EFC_MONO_10LSB', + 123: 'EFC_MONO_12MSB', + 124: 'EFC_MONO_12LSB', + 125: 'EFC_MONO_16', +} +EFC_ARGB1555 = 1 +EFC_RGBA5551 = 2 +EFC_RGB565 = 3 +EFC_BGR565 = 4 +EFC_ARGB4444 = 5 +EFC_RGBA4444 = 6 +EFC_ARGB8888 = 8 +EFC_RGBA8888 = 9 +EFC_ARGB2101010 = 10 +EFC_RGBA1010102 = 11 +EFC_AYCrCb8888 = 12 +EFC_YCrCbA8888 = 13 +EFC_ACrYCb8888 = 14 +EFC_CrYCbA8888 = 15 +EFC_ARGB16161616_10MSB = 16 +EFC_RGBA16161616_10MSB = 17 +EFC_ARGB16161616_10LSB = 18 +EFC_RGBA16161616_10LSB = 19 +EFC_ARGB16161616_12MSB = 20 +EFC_RGBA16161616_12MSB = 21 +EFC_ARGB16161616_12LSB = 22 +EFC_RGBA16161616_12LSB = 23 +EFC_ARGB16161616_FLOAT = 24 +EFC_RGBA16161616_FLOAT = 25 +EFC_ARGB16161616_UNORM = 26 +EFC_RGBA16161616_UNORM = 27 +EFC_ARGB16161616_SNORM = 28 +EFC_RGBA16161616_SNORM = 29 +EFC_AYCrCb16161616_10MSB = 32 +EFC_AYCrCb16161616_10LSB = 33 +EFC_YCrCbA16161616_10MSB = 34 +EFC_YCrCbA16161616_10LSB = 35 +EFC_ACrYCb16161616_10MSB = 36 +EFC_ACrYCb16161616_10LSB = 37 +EFC_CrYCbA16161616_10MSB = 38 +EFC_CrYCbA16161616_10LSB = 39 +EFC_AYCrCb16161616_12MSB = 40 +EFC_AYCrCb16161616_12LSB = 41 +EFC_YCrCbA16161616_12MSB = 42 +EFC_YCrCbA16161616_12LSB = 43 +EFC_ACrYCb16161616_12MSB = 44 +EFC_ACrYCb16161616_12LSB = 45 +EFC_CrYCbA16161616_12MSB = 46 +EFC_CrYCbA16161616_12LSB = 47 +EFC_Y8_CrCb88_420_PLANAR = 64 +EFC_Y8_CbCr88_420_PLANAR = 65 +EFC_Y10_CrCb1010_420_PLANAR = 66 +EFC_Y10_CbCr1010_420_PLANAR = 67 +EFC_Y12_CrCb1212_420_PLANAR = 68 +EFC_Y12_CbCr1212_420_PLANAR = 69 +EFC_YCrYCb8888_422_PACKED = 72 +EFC_YCbYCr8888_422_PACKED = 73 +EFC_CrYCbY8888_422_PACKED = 74 +EFC_CbYCrY8888_422_PACKED = 75 +EFC_YCrYCb10101010_422_PACKED = 76 +EFC_YCbYCr10101010_422_PACKED = 77 +EFC_CrYCbY10101010_422_PACKED = 78 +EFC_CbYCrY10101010_422_PACKED = 79 +EFC_YCrYCb12121212_422_PACKED = 80 +EFC_YCbYCr12121212_422_PACKED = 81 +EFC_CrYCbY12121212_422_PACKED = 82 +EFC_CbYCrY12121212_422_PACKED = 83 +EFC_RGB111110_FIX = 112 +EFC_BGR101111_FIX = 113 +EFC_ACrYCb2101010 = 114 +EFC_CrYCbA1010102 = 115 +EFC_RGB111110_FLOAT = 118 +EFC_BGR101111_FLOAT = 119 +EFC_MONO_8 = 120 +EFC_MONO_10MSB = 121 +EFC_MONO_10LSB = 122 +EFC_MONO_12MSB = 123 +EFC_MONO_12LSB = 124 +EFC_MONO_16 = 125 +EFC_SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'UVDFirmwareCommand' +UVDFirmwareCommand__enumvalues = { + 0: 'UVDFC_FENCE', + 1: 'UVDFC_TRAP', + 2: 'UVDFC_DECODED_ADDR', + 3: 'UVDFC_MBLOCK_ADDR', + 4: 'UVDFC_ITBUF_ADDR', + 5: 'UVDFC_DISPLAY_ADDR', + 6: 'UVDFC_EOD', + 7: 'UVDFC_DISPLAY_PITCH', + 8: 'UVDFC_DISPLAY_TILING', + 9: 'UVDFC_BITSTREAM_ADDR', + 10: 'UVDFC_BITSTREAM_SIZE', +} +UVDFC_FENCE = 0 +UVDFC_TRAP = 1 +UVDFC_DECODED_ADDR = 2 +UVDFC_MBLOCK_ADDR = 3 +UVDFC_ITBUF_ADDR = 4 +UVDFC_DISPLAY_ADDR = 5 +UVDFC_EOD = 6 +UVDFC_DISPLAY_PITCH = 7 +UVDFC_DISPLAY_TILING = 8 +UVDFC_BITSTREAM_ADDR = 9 +UVDFC_BITSTREAM_SIZE = 10 +UVDFirmwareCommand = ctypes.c_uint32 # enum +__all__ = \ + ['ABGR_TO_A_BG_G_RB', 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', + 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ACrYCb16161616_10LSB', + 'ACrYCb16161616_10MSB', 'ACrYCb16161616_12LSB', + 'ACrYCb16161616_12MSB', 'ACrYCb2101010', 'ACrYCb8888', + 'ADDR_CONFIG_16_BANK', 'ADDR_CONFIG_16_PIPE', + 'ADDR_CONFIG_1KB_ROW', 'ADDR_CONFIG_1_BANK', 'ADDR_CONFIG_1_GPU', + 'ADDR_CONFIG_1_LOWER_PIPES', + 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_1_PIPE', + 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE', + 'ADDR_CONFIG_1_SHADER_ENGINE', 'ADDR_CONFIG_2KB_ROW', + 'ADDR_CONFIG_2_BANK', 'ADDR_CONFIG_2_GPU', + 'ADDR_CONFIG_2_LOWER_PIPES', + 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_2_PIPE', + 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE', + 'ADDR_CONFIG_2_SHADER_ENGINE', 'ADDR_CONFIG_32_PIPE', + 'ADDR_CONFIG_4KB_ROW', 'ADDR_CONFIG_4_BANK', 'ADDR_CONFIG_4_GPU', + 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_4_PIPE', + 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE', + 'ADDR_CONFIG_4_SHADER_ENGINE', 'ADDR_CONFIG_64_PIPE', + 'ADDR_CONFIG_8_BANK', 'ADDR_CONFIG_8_GPU', + 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_8_PIPE', + 'ADDR_CONFIG_8_SHADER_ENGINE', 'ADDR_CONFIG_BANK_INTERLEAVE_1', + 'ADDR_CONFIG_BANK_INTERLEAVE_2', 'ADDR_CONFIG_BANK_INTERLEAVE_4', + 'ADDR_CONFIG_BANK_INTERLEAVE_8', 'ADDR_CONFIG_DISABLE_SE', + 'ADDR_CONFIG_ENABLE_SE', 'ADDR_CONFIG_GPU_TILE_128', + 'ADDR_CONFIG_GPU_TILE_16', 'ADDR_CONFIG_GPU_TILE_32', + 'ADDR_CONFIG_GPU_TILE_64', 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB', + 'ADDR_CONFIG_PIPE_INTERLEAVE_256B', + 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB', + 'ADDR_CONFIG_PIPE_INTERLEAVE_512B', 'ADDR_CONFIG_SE_TILE_16', + 'ADDR_CONFIG_SE_TILE_32', 'ADDR_NUM_BANKS_BC_BANKS_1', + 'ADDR_NUM_BANKS_BC_BANKS_16', 'ADDR_NUM_BANKS_BC_BANKS_2', + 'ADDR_NUM_BANKS_BC_BANKS_4', 'ADDR_NUM_BANKS_BC_BANKS_8', + 'ADDR_NUM_PIPES_BC_P16', 'ADDR_NUM_PIPES_BC_P8', + 'ADDR_SURF_16_BANK', 'ADDR_SURF_2_BANK', 'ADDR_SURF_4_BANK', + 'ADDR_SURF_8_BANK', 'ADDR_SURF_BANK_HEIGHT_1', + 'ADDR_SURF_BANK_HEIGHT_2', 'ADDR_SURF_BANK_HEIGHT_4', + 'ADDR_SURF_BANK_HEIGHT_8', 'ADDR_SURF_BANK_WH_1', + 'ADDR_SURF_BANK_WH_2', 'ADDR_SURF_BANK_WH_4', + 'ADDR_SURF_BANK_WH_8', 'ADDR_SURF_BANK_WIDTH_1', + 'ADDR_SURF_BANK_WIDTH_2', 'ADDR_SURF_BANK_WIDTH_4', + 'ADDR_SURF_BANK_WIDTH_8', 'ADDR_SURF_DEPTH_MICRO_TILING', + 'ADDR_SURF_DISPLAY_MICRO_TILING', 'ADDR_SURF_MACRO_ASPECT_1', + 'ADDR_SURF_MACRO_ASPECT_2', 'ADDR_SURF_MACRO_ASPECT_4', + 'ADDR_SURF_MACRO_ASPECT_8', 'ADDR_SURF_MICRO_TILING_DISPLAY', + 'ADDR_SURF_MICRO_TILING_NON_DISPLAY', 'ADDR_SURF_P16', + 'ADDR_SURF_P16_32x32_16x16', 'ADDR_SURF_P16_32x32_8x16', + 'ADDR_SURF_P2', 'ADDR_SURF_P2_RESERVED0', + 'ADDR_SURF_P2_RESERVED1', 'ADDR_SURF_P2_RESERVED2', + 'ADDR_SURF_P4_16x16', 'ADDR_SURF_P4_16x32', 'ADDR_SURF_P4_32x32', + 'ADDR_SURF_P4_8x16', 'ADDR_SURF_P8_16x16_8x16', + 'ADDR_SURF_P8_16x32_16x16', 'ADDR_SURF_P8_16x32_8x16', + 'ADDR_SURF_P8_32x32_16x16', 'ADDR_SURF_P8_32x32_16x32', + 'ADDR_SURF_P8_32x32_8x16', 'ADDR_SURF_P8_32x64_32x32', + 'ADDR_SURF_P8_RESERVED0', 'ADDR_SURF_ROTATED_MICRO_TILING', + 'ADDR_SURF_SAMPLE_SPLIT_1', 'ADDR_SURF_SAMPLE_SPLIT_2', + 'ADDR_SURF_SAMPLE_SPLIT_4', 'ADDR_SURF_SAMPLE_SPLIT_8', + 'ADDR_SURF_THICK_MICRO_TILING', 'ADDR_SURF_THIN_MICRO_TILING', + 'ADDR_SURF_TILE_SPLIT_128B', 'ADDR_SURF_TILE_SPLIT_1KB', + 'ADDR_SURF_TILE_SPLIT_256B', 'ADDR_SURF_TILE_SPLIT_2KB', + 'ADDR_SURF_TILE_SPLIT_4KB', 'ADDR_SURF_TILE_SPLIT_512B', + 'ADDR_SURF_TILE_SPLIT_64B', 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', + 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', + 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', + 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', + 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', + 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', + 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', + 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', + 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', + 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', + 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', + 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', + 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', + 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', + 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', + 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', 'AFMT_AUDIO_SRC_RESERVED', + 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', + 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', + 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', + 'AFMT_INTERRUPT_STATUS_CHG_MASK', + 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', + 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', + 'AFMT_VBI_GSP0_INDEX', 'AFMT_VBI_GSP10_INDEX', + 'AFMT_VBI_GSP1_INDEX', 'AFMT_VBI_GSP2_INDEX', + 'AFMT_VBI_GSP3_INDEX', 'AFMT_VBI_GSP4_INDEX', + 'AFMT_VBI_GSP5_INDEX', 'AFMT_VBI_GSP6_INDEX', + 'AFMT_VBI_GSP7_INDEX', 'AFMT_VBI_GSP8_INDEX', + 'AFMT_VBI_GSP9_INDEX', 'AFMT_VBI_GSP_INDEX', + 'ALLOW_SR_ON_TRANS_REQ', 'ALLOW_SR_ON_TRANS_REQ_DISABLE', + 'ALLOW_SR_ON_TRANS_REQ_ENABLE', 'ALPHA_DATA_ON_ALPHA_PORT', + 'ALPHA_DATA_ON_CB_B_PORT', 'ALPHA_DATA_ON_CR_R_PORT', + 'ALPHA_DATA_ON_Y_G_PORT', 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'AM_1D_TILED_THICK', + 'AM_1D_TILED_THIN1', 'AM_2D_TILED_THICK', 'AM_2D_TILED_THIN1', + 'AM_2D_TILED_XTHICK', 'AM_3D_TILED_THICK', 'AM_3D_TILED_THIN1', + 'AM_3D_TILED_XTHICK', 'AM_LINEAR_ALIGNED', 'AM_LINEAR_GENERAL', + 'AM_PRT_2D_TILED_THICK', 'AM_PRT_2D_TILED_THIN1', + 'AM_PRT_3D_TILED_THICK', 'AM_PRT_3D_TILED_THIN1', + 'AM_PRT_TILED_THICK', 'AM_PRT_TILED_THIN1', 'ARGB1555', + 'ARGB16161616_10LSB', 'ARGB16161616_10MSB', 'ARGB16161616_12LSB', + 'ARGB16161616_12MSB', 'ARGB16161616_FLOAT', 'ARGB16161616_SNORM', + 'ARGB16161616_UNORM', 'ARGB2101010', 'ARGB4444', 'ARGB8888', + 'ARRAY_1D', 'ARRAY_1D_TILED_THICK', 'ARRAY_1D_TILED_THIN1', + 'ARRAY_2D', 'ARRAY_2D_ALT_COLOR', 'ARRAY_2D_ALT_DEPTH', + 'ARRAY_2D_COLOR', 'ARRAY_2D_DEPTH', 'ARRAY_2D_TILED_THICK', + 'ARRAY_2D_TILED_THIN1', 'ARRAY_2D_TILED_XTHICK', 'ARRAY_3D', + 'ARRAY_3D_SLICE', 'ARRAY_3D_SLICE_COLOR', 'ARRAY_3D_TILED_THICK', + 'ARRAY_3D_TILED_THIN1', 'ARRAY_3D_TILED_XTHICK', + 'ARRAY_COLOR_TILE', 'ARRAY_DEPTH_TILE', 'ARRAY_LINEAR', + 'ARRAY_LINEAR_ALIGNED', 'ARRAY_LINEAR_GENERAL', 'ARRAY_MODE', + 'ARRAY_PRT_2D_TILED_THICK', 'ARRAY_PRT_2D_TILED_THIN1', + 'ARRAY_PRT_3D_TILED_THICK', 'ARRAY_PRT_3D_TILED_THIN1', + 'ARRAY_PRT_TILED_THICK', 'ARRAY_PRT_TILED_THIN1', 'ARRAY_TILED', + 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT', + 'AUTOCAL_MODE_AUTOCENTER', 'AUTOCAL_MODE_AUTOREPLICATE', + 'AUTOCAL_MODE_AUTOSCALE', 'AUTOCAL_MODE_OFF', + 'AYCrCb16161616_10LSB', 'AYCrCb16161616_10MSB', + 'AYCrCb16161616_12LSB', 'AYCrCb16161616_12MSB', 'AYCrCb8888', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', + 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', + 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', + 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', + 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', + 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', + 'AZ_RIRB_WRITE_POINTER_DO_RESET', + 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', + 'AZ_STATE_CHANGE_STATUS', + 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'ArrayMode', + 'BANK_HEIGHT', 'BANK_WIDTH', 'BGR101111_FIX', 'BGR101111_FLOAT', + 'BGR565', 'BGRA_TO_BG_G_RB_A', 'BINNER_BREAK_BATCH', + 'BINNER_DROP', 'BINNER_DROP_ASSERT', 'BINNER_PIPELINE', + 'BINNING_ALLOWED', 'BIN_CONF_OVERRIDE_CHECK', 'BIN_MAP_MODE_NONE', + 'BIN_MAP_MODE_POPS', 'BIN_MAP_MODE_RTA_INDEX', + 'BIN_SIZE_128_PIXELS', 'BIN_SIZE_256_PIXELS', + 'BIN_SIZE_32_PIXELS', 'BIN_SIZE_512_PIXELS', 'BIN_SIZE_64_PIXELS', + 'BITS_31_0', 'BITS_32_1', 'BITS_33_2', 'BITS_34_3', 'BITS_35_4', + 'BITS_36_5', 'BITS_37_6', 'BITS_38_7', 'BLEND_BOTH_INV_SRC_ALPHA', + 'BLEND_BOTH_SRC_ALPHA', 'BLEND_CONSTANT_ALPHA', + 'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', + 'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', + 'BLEND_ONE_MINUS_CONSTANT_ALPHA', + 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', + 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', + 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', + 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', + 'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLOCK_CONTEXT_DONE', 'BOTH_EYE', + 'BOTTOM_OF_PIPE_TS', 'BREAK_BATCH', 'BUF_DATA_FORMAT', + 'BUF_DATA_FORMAT_10_10_10_2', 'BUF_DATA_FORMAT_10_11_11', + 'BUF_DATA_FORMAT_11_11_10', 'BUF_DATA_FORMAT_16', + 'BUF_DATA_FORMAT_16_16', 'BUF_DATA_FORMAT_16_16_16_16', + 'BUF_DATA_FORMAT_2_10_10_10', 'BUF_DATA_FORMAT_32', + 'BUF_DATA_FORMAT_32_32', 'BUF_DATA_FORMAT_32_32_32', + 'BUF_DATA_FORMAT_32_32_32_32', 'BUF_DATA_FORMAT_8', + 'BUF_DATA_FORMAT_8_8', 'BUF_DATA_FORMAT_8_8_8_8', + 'BUF_DATA_FORMAT_INVALID', 'BUF_DATA_FORMAT_RESERVED_15', + 'BUF_FMT', 'BUF_FMT_10_10_10_2_SINT', 'BUF_FMT_10_10_10_2_SNORM', + 'BUF_FMT_10_10_10_2_SSCALED', 'BUF_FMT_10_10_10_2_UINT', + 'BUF_FMT_10_10_10_2_UNORM', 'BUF_FMT_10_10_10_2_USCALED', + 'BUF_FMT_10_11_11_FLOAT', 'BUF_FMT_10_11_11_SINT', + 'BUF_FMT_10_11_11_SNORM', 'BUF_FMT_10_11_11_SSCALED', + 'BUF_FMT_10_11_11_UINT', 'BUF_FMT_10_11_11_UNORM', + 'BUF_FMT_10_11_11_USCALED', 'BUF_FMT_11_11_10_FLOAT', + 'BUF_FMT_11_11_10_SINT', 'BUF_FMT_11_11_10_SNORM', + 'BUF_FMT_11_11_10_SSCALED', 'BUF_FMT_11_11_10_UINT', + 'BUF_FMT_11_11_10_UNORM', 'BUF_FMT_11_11_10_USCALED', + 'BUF_FMT_16_16_16_16_FLOAT', 'BUF_FMT_16_16_16_16_SINT', + 'BUF_FMT_16_16_16_16_SNORM', 'BUF_FMT_16_16_16_16_SSCALED', + 'BUF_FMT_16_16_16_16_UINT', 'BUF_FMT_16_16_16_16_UNORM', + 'BUF_FMT_16_16_16_16_USCALED', 'BUF_FMT_16_16_FLOAT', + 'BUF_FMT_16_16_SINT', 'BUF_FMT_16_16_SNORM', + 'BUF_FMT_16_16_SSCALED', 'BUF_FMT_16_16_UINT', + 'BUF_FMT_16_16_UNORM', 'BUF_FMT_16_16_USCALED', + 'BUF_FMT_16_FLOAT', 'BUF_FMT_16_SINT', 'BUF_FMT_16_SNORM', + 'BUF_FMT_16_SSCALED', 'BUF_FMT_16_UINT', 'BUF_FMT_16_UNORM', + 'BUF_FMT_16_USCALED', 'BUF_FMT_2_10_10_10_SINT', + 'BUF_FMT_2_10_10_10_SNORM', 'BUF_FMT_2_10_10_10_SSCALED', + 'BUF_FMT_2_10_10_10_UINT', 'BUF_FMT_2_10_10_10_UNORM', + 'BUF_FMT_2_10_10_10_USCALED', 'BUF_FMT_32_32_32_32_FLOAT', + 'BUF_FMT_32_32_32_32_SINT', 'BUF_FMT_32_32_32_32_UINT', + 'BUF_FMT_32_32_32_FLOAT', 'BUF_FMT_32_32_32_SINT', + 'BUF_FMT_32_32_32_UINT', 'BUF_FMT_32_32_FLOAT', + 'BUF_FMT_32_32_SINT', 'BUF_FMT_32_32_UINT', 'BUF_FMT_32_FLOAT', + 'BUF_FMT_32_SINT', 'BUF_FMT_32_UINT', 'BUF_FMT_8_8_8_8_SINT', + 'BUF_FMT_8_8_8_8_SNORM', 'BUF_FMT_8_8_8_8_SSCALED', + 'BUF_FMT_8_8_8_8_UINT', 'BUF_FMT_8_8_8_8_UNORM', + 'BUF_FMT_8_8_8_8_USCALED', 'BUF_FMT_8_8_SINT', + 'BUF_FMT_8_8_SNORM', 'BUF_FMT_8_8_SSCALED', 'BUF_FMT_8_8_UINT', + 'BUF_FMT_8_8_UNORM', 'BUF_FMT_8_8_USCALED', 'BUF_FMT_8_SINT', + 'BUF_FMT_8_SNORM', 'BUF_FMT_8_SSCALED', 'BUF_FMT_8_UINT', + 'BUF_FMT_8_UNORM', 'BUF_FMT_8_USCALED', 'BUF_FMT_INVALID', + 'BUF_FMT_RESERVED_100', 'BUF_FMT_RESERVED_101', + 'BUF_FMT_RESERVED_102', 'BUF_FMT_RESERVED_103', + 'BUF_FMT_RESERVED_104', 'BUF_FMT_RESERVED_105', + 'BUF_FMT_RESERVED_106', 'BUF_FMT_RESERVED_107', + 'BUF_FMT_RESERVED_108', 'BUF_FMT_RESERVED_109', + 'BUF_FMT_RESERVED_110', 'BUF_FMT_RESERVED_111', + 'BUF_FMT_RESERVED_112', 'BUF_FMT_RESERVED_113', + 'BUF_FMT_RESERVED_114', 'BUF_FMT_RESERVED_115', + 'BUF_FMT_RESERVED_116', 'BUF_FMT_RESERVED_117', + 'BUF_FMT_RESERVED_118', 'BUF_FMT_RESERVED_119', + 'BUF_FMT_RESERVED_120', 'BUF_FMT_RESERVED_121', + 'BUF_FMT_RESERVED_122', 'BUF_FMT_RESERVED_123', + 'BUF_FMT_RESERVED_124', 'BUF_FMT_RESERVED_125', + 'BUF_FMT_RESERVED_126', 'BUF_FMT_RESERVED_127', + 'BUF_FMT_RESERVED_78', 'BUF_FMT_RESERVED_79', + 'BUF_FMT_RESERVED_80', 'BUF_FMT_RESERVED_81', + 'BUF_FMT_RESERVED_82', 'BUF_FMT_RESERVED_83', + 'BUF_FMT_RESERVED_84', 'BUF_FMT_RESERVED_85', + 'BUF_FMT_RESERVED_86', 'BUF_FMT_RESERVED_87', + 'BUF_FMT_RESERVED_88', 'BUF_FMT_RESERVED_89', + 'BUF_FMT_RESERVED_90', 'BUF_FMT_RESERVED_91', + 'BUF_FMT_RESERVED_92', 'BUF_FMT_RESERVED_93', + 'BUF_FMT_RESERVED_94', 'BUF_FMT_RESERVED_95', + 'BUF_FMT_RESERVED_96', 'BUF_FMT_RESERVED_97', + 'BUF_FMT_RESERVED_98', 'BUF_FMT_RESERVED_99', 'BUF_NUM_FORMAT', + 'BUF_NUM_FORMAT_FLOAT', 'BUF_NUM_FORMAT_SINT', + 'BUF_NUM_FORMAT_SNORM', 'BUF_NUM_FORMAT_SNORM_NZ', + 'BUF_NUM_FORMAT_SSCALED', 'BUF_NUM_FORMAT_UINT', + 'BUF_NUM_FORMAT_UNORM', 'BUF_NUM_FORMAT_USCALED', 'BYPASS_EN', + 'BYPASS_GAMUT', 'BYPASS_ICSC', 'BankHeight', 'BankInterleaveSize', + 'BankSwapBytes', 'BankTiling', 'BankWidth', 'BankWidthHeight', + 'BinEventCntl', 'BinMapMode', 'BinSizeExtend', 'BinningMode', + 'BlendOp', 'BlendOpt', 'CACHE_BYPASS', 'CACHE_FLUSH', + 'CACHE_FLUSH_AND_INV_EVENT', 'CACHE_FLUSH_AND_INV_TS_EVENT', + 'CACHE_FLUSH_TS', 'CACHE_LRU_RD', 'CACHE_LRU_WR', 'CACHE_NOA', + 'CACHE_STREAM', 'CBMode', 'CBPerfClearFilterSel', + 'CBPerfOpFilterSel', 'CBPerfSel', 'CB_B_DATA_ON_ALPHA_PORT', + 'CB_B_DATA_ON_CB_B_PORT', 'CB_B_DATA_ON_CR_R_PORT', + 'CB_B_DATA_ON_Y_G_PORT', 'CB_DCC_DECOMPRESS', 'CB_DECOMPRESS', + 'CB_DISABLE', 'CB_ELIMINATE_FAST_CLEAR', 'CB_FMASK_DECOMPRESS', + 'CB_NORMAL', 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', + 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', + 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL', + 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', 'CB_PERF_SEL_BUSY', + 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY', + 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB', + 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY', + 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB', + 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY', + 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB', + 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY', + 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB', + 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY', + 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD', + 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID', + 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_CC_CACHE_FLUSH', 'CB_PERF_SEL_CC_CACHE_HIT', + 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', + 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7', + 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN', + 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT', + 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN', + 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED', + 'CB_PERF_SEL_CC_DCC_RDREQ_STALL', + 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL', + 'CB_PERF_SEL_CC_EVENFIFO_STUTTER_STALL', + 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY', + 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB', + 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY', + 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB', + 'CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN', + 'CB_PERF_SEL_CC_MC_READ_REQUEST', + 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_MC_WRITE_ACK64B', + 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', + 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL', + 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL', + 'CB_PERF_SEL_CC_ODDFIFO_STUTTER_STALL', + 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY', + 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB', + 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY', + 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB', + 'CB_PERF_SEL_CC_RB_FULL', 'CB_PERF_SEL_CC_SF_FULL', + 'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CMASK_READ_DATA_0xC', + 'CB_PERF_SEL_CMASK_READ_DATA_0xD', + 'CB_PERF_SEL_CMASK_READ_DATA_0xE', + 'CB_PERF_SEL_CMASK_READ_DATA_0xF', + 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC', + 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD', + 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE', + 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF', + 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY', + 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_CM_CACHE_FLUSH', 'CB_PERF_SEL_CM_CACHE_HIT', + 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CM_CACHE_STALL', + 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_CM_CACHE_TAG_MISS', + 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY', + 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB', + 'CB_PERF_SEL_CM_FC_TILE_VALID_READY', + 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB', + 'CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN', + 'CB_PERF_SEL_CM_MC_READ_REQUEST', + 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CM_MC_WRITE_ACK64B', + 'CB_PERF_SEL_CM_MC_WRITE_REQUEST', + 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CM_TQ_FIFO_STUTTER_STALL', + 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL', + 'CB_PERF_SEL_CM_TQ_FULL', 'CB_PERF_SEL_CORE_SCLK_VLD', + 'CB_PERF_SEL_DB_CB_CONTEXT_DONE', 'CB_PERF_SEL_DB_CB_EOP_DONE', + 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY', + 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB', + 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY', + 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB', + 'CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT', + 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY', + 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB', + 'CB_PERF_SEL_DB_CB_TILE_VALID_READY', + 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB', + 'CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN', + 'CB_PERF_SEL_DC_MC_WRITE_ACK64B', 'CB_PERF_SEL_DRAWN_BUSY', + 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', + 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE', + 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT', + 'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS', + 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', + 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY', + 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_FC_CACHE_FLUSH', 'CB_PERF_SEL_FC_CACHE_HIT', + 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_FC_CACHE_STALL', + 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_FC_CACHE_TAG_MISS', + 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY', + 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB', + 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY', + 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB', + 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY', + 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB', + 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY', + 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB', + 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', 'CB_PERF_SEL_FC_DCC_CACHE_HIT', + 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS', + 'CB_PERF_SEL_FC_DCC_CACHE_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS', + 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR', + 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT', + 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS', + 'CB_PERF_SEL_FC_DOC_IS_STALLED', + 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED', + 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED', + 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR', + 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS', + 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS', + 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS', + 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT', + 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS', + 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL', + 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS', + 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL', + 'CB_PERF_SEL_FC_KEYID_STUTTER_STALL', + 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST', + 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST', + 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN', + 'CB_PERF_SEL_FC_MC_READ_REQUEST', + 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_MC_WRITE_ACK64B', + 'CB_PERF_SEL_FC_MC_WRITE_REQUEST', + 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED', + 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL', + 'CB_PERF_SEL_FC_QUAD_STUTTER_STALL', + 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL', + 'CB_PERF_SEL_FC_SEQUENCER_CLEAR', + 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR', + 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE', + 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS', + 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL', + 'CB_PERF_SEL_FC_TILE_STUTTER_STALL', + 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL', + 'CB_PERF_SEL_FOP_FMASK_RAW_STALL', + 'CB_PERF_SEL_FOP_IN_VALIDB_READY', + 'CB_PERF_SEL_FOP_IN_VALIDB_READYB', + 'CB_PERF_SEL_FOP_IN_VALID_READY', + 'CB_PERF_SEL_FOP_IN_VALID_READYB', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR', + 'CB_PERF_SEL_LQUAD_NO_TILE', + 'CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED', + 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY', + 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB', + 'CB_PERF_SEL_NACK_CC_READ', 'CB_PERF_SEL_NACK_CC_WRITE', + 'CB_PERF_SEL_NACK_CM_READ', 'CB_PERF_SEL_NACK_CM_WRITE', + 'CB_PERF_SEL_NACK_DC_READ', 'CB_PERF_SEL_NACK_DC_WRITE', + 'CB_PERF_SEL_NACK_FC_READ', 'CB_PERF_SEL_NACK_FC_WRITE', + 'CB_PERF_SEL_NONE', 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT', + 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS', + 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS', + 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS', + 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST', + 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED', + 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID', + 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL', + 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT', + 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK', + 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7', + 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT', + 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7', + 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', + 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', + 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', + 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD', + 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS', + 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK', + 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING', + 'CB_PERF_SEL_RBP_SPLIT_MICROTILE', + 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK', + 'CB_PERF_SEL_REG_SCLK0_VLD', 'CB_PERF_SEL_REG_SCLK1_VLD', + 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY', + 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', 'CB_RESERVED', + 'CB_RESOLVE', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', + 'CHA_PERF_SEL', 'CHA_PERF_SEL_ARB_REQUESTS', 'CHA_PERF_SEL_BUSY', + 'CHA_PERF_SEL_CYCLE', 'CHA_PERF_SEL_IO_32B_WDS_CHC0', + 'CHA_PERF_SEL_IO_32B_WDS_CHC1', 'CHA_PERF_SEL_IO_32B_WDS_CHC2', + 'CHA_PERF_SEL_IO_32B_WDS_CHC3', 'CHA_PERF_SEL_IO_32B_WDS_CHC4', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', 'CHA_PERF_SEL_REQUEST_CHC0', + 'CHA_PERF_SEL_REQUEST_CHC1', 'CHA_PERF_SEL_REQUEST_CHC2', + 'CHA_PERF_SEL_REQUEST_CHC3', 'CHA_PERF_SEL_REQUEST_CHC4', + 'CHA_PERF_SEL_REQUEST_CHC5', 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', + 'CHA_PERF_SEL_STALL_CHC0', 'CHA_PERF_SEL_STALL_CHC1', + 'CHA_PERF_SEL_STALL_CHC2', 'CHA_PERF_SEL_STALL_CHC3', + 'CHA_PERF_SEL_STALL_CHC4', 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', 'CHCG_PERF_SEL', + 'CHCG_PERF_SEL_CORE_REG_SCLK_VLD', 'CHCG_PERF_SEL_CYCLE', + 'CHCG_PERF_SEL_GATE_EN1', 'CHCG_PERF_SEL_GATE_EN2', + 'CHCG_PERF_SEL_REQ', 'CHCG_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES', + 'CHCG_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES', 'CHC_PERF_SEL', + 'CHC_PERF_SEL_CORE_REG_SCLK_VLD', 'CHC_PERF_SEL_CYCLE', + 'CHC_PERF_SEL_GATE_EN1', 'CHC_PERF_SEL_GATE_EN2', + 'CHC_PERF_SEL_REQ', 'CHC_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES', + 'CHC_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES', 'CHUNK_SIZE', + 'CHUNK_SIZE_16KB', 'CHUNK_SIZE_1KB', 'CHUNK_SIZE_2KB', + 'CHUNK_SIZE_32KB', 'CHUNK_SIZE_4KB', 'CHUNK_SIZE_64KB', + 'CHUNK_SIZE_8KB', 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', + 'CLKGATE_SM_MODE', 'CLOCK_BRANCH_SOFT_RESET', + 'CLOCK_BRANCH_SOFT_RESET_FORCE', 'CLOCK_BRANCH_SOFT_RESET_NOOP', + 'CLOCK_GATING_DISABLE', 'CLOCK_GATING_DISABLED', + 'CLOCK_GATING_DISABLED_IN_DCO', 'CLOCK_GATING_DISABLE_ENUM', + 'CLOCK_GATING_DISABLE_ENUM_DISABLED', + 'CLOCK_GATING_DISABLE_ENUM_ENABLED', 'CLOCK_GATING_EN', + 'CLOCK_GATING_ENABLE', 'CLOCK_GATING_ENABLED', + 'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_ADDR_COMPATIBLE', + 'CMASK_ADDR_LINEAR', 'CMASK_ADDR_TILED', 'CMASK_ALPHA0_FRAG1', + 'CMASK_ALPHA0_FRAG2', 'CMASK_ALPHA0_FRAG4', 'CMASK_ALPHA0_FRAGS', + 'CMASK_ALPHA1_FRAG1', 'CMASK_ALPHA1_FRAG2', 'CMASK_ALPHA1_FRAG4', + 'CMASK_ALPHA1_FRAGS', 'CMASK_ALPHAX_FRAG1', 'CMASK_ALPHAX_FRAG2', + 'CMASK_ALPHAX_FRAG4', 'CMASK_ALPHAX_FRAGS', 'CMASK_ANY_EXPANDED', + 'CMASK_CLEAR_ALL', 'CMASK_CLEAR_NONE', 'CMASK_CLEAR_ONE', + 'CMASK_CLR00_F0', 'CMASK_CLR00_F1', 'CMASK_CLR00_F2', + 'CMASK_CLR00_FX', 'CMASK_CLR01_F0', 'CMASK_CLR01_F1', + 'CMASK_CLR01_F2', 'CMASK_CLR01_FX', 'CMASK_CLR10_F0', + 'CMASK_CLR10_F1', 'CMASK_CLR10_F2', 'CMASK_CLR10_FX', + 'CMASK_CLR11_F0', 'CMASK_CLR11_F1', 'CMASK_CLR11_F2', + 'CMASK_CLR11_FX', 'CMC_3DLUT_17CUBE', 'CMC_3DLUT_30BIT', + 'CMC_3DLUT_30BIT_ENUM', 'CMC_3DLUT_36BIT', 'CMC_3DLUT_9CUBE', + 'CMC_3DLUT_RAM_SEL', 'CMC_3DLUT_SIZE_ENUM', + 'CMC_LUT_2CFG_MEMORY_A', 'CMC_LUT_2CFG_MEMORY_B', + 'CMC_LUT_2CFG_NO_MEMORY', 'CMC_LUT_2_CONFIG_ENUM', + 'CMC_LUT_2_MODE_BYPASS', 'CMC_LUT_2_MODE_ENUM', + 'CMC_LUT_2_MODE_RAMA_LUT', 'CMC_LUT_2_MODE_RAMB_LUT', + 'CMC_LUT_NUM_SEG', 'CMC_LUT_RAM_SEL', 'CMC_RAM0_ACCESS', + 'CMC_RAM1_ACCESS', 'CMC_RAM2_ACCESS', 'CMC_RAM3_ACCESS', + 'CMC_RAMA_ACCESS', 'CMC_RAMB_ACCESS', 'CMC_SEGMENTS_1', + 'CMC_SEGMENTS_128', 'CMC_SEGMENTS_16', 'CMC_SEGMENTS_2', + 'CMC_SEGMENTS_32', 'CMC_SEGMENTS_4', 'CMC_SEGMENTS_64', + 'CMC_SEGMENTS_8', 'CM_BYPASS', 'CM_COEF_FORMAT_ENUM', + 'CM_DATA_SIGNED', 'CM_DISABLE', 'CM_EN', 'CM_ENABLE', + 'CM_GAMUT_REMAP_MODE_ENUM', 'CM_ICSC_MODE_ENUM', + 'CM_LUT_2_CONFIG_ENUM', 'CM_LUT_2_MODE_ENUM', + 'CM_LUT_4_CONFIG_ENUM', 'CM_LUT_4_MODE_ENUM', 'CM_LUT_NUM_SEG', + 'CM_LUT_RAM_SEL', 'CM_NOT_PENDING', 'CM_PENDING', + 'CM_WRITE_BASE_ONLY', 'CM_YES_PENDING', 'CNVC_BYPASS', + 'CNVC_BYPASS_DISABLE', 'CNVC_BYPASS_EN', 'CNVC_DIS', 'CNVC_EN', + 'CNVC_ENABLE', 'CNVC_NOT_PENDING', 'CNVC_PENDING', 'CNVC_ROUND', + 'CNVC_TRUNCATE', 'CNVC_YES_PENDING', 'CNV_CSC_BYPASS_ENUM', + 'CNV_CSC_BYPASS_NEG', 'CNV_CSC_BYPASS_POS', 'CNV_EYE_SELECT', + 'CNV_FRAME_CAPTURE_DISABLE', 'CNV_FRAME_CAPTURE_ENABLE', + 'CNV_FRAME_CAPTURE_EN_ENUM', 'CNV_FRAME_CAPTURE_RATE_0', + 'CNV_FRAME_CAPTURE_RATE_1', 'CNV_FRAME_CAPTURE_RATE_2', + 'CNV_FRAME_CAPTURE_RATE_3', 'CNV_FRAME_CAPTURE_RATE_ENUM', + 'CNV_INTERLACED_FIELD_ORDER_BOT', + 'CNV_INTERLACED_FIELD_ORDER_ENUM', + 'CNV_INTERLACED_FIELD_ORDER_TOP', 'CNV_INTERLACED_MODE_ENUM', + 'CNV_INTERLACED_MODE_INTERLACED', + 'CNV_INTERLACED_MODE_PROGRESSIVE', 'CNV_NEW_CONTENT_ENUM', + 'CNV_NEW_CONTENT_NEG', 'CNV_NEW_CONTENT_POS', 'CNV_OUT_BPC_10BPC', + 'CNV_OUT_BPC_8BPC', 'CNV_OUT_BPC_ENUM', + 'CNV_STEREO_POLARITY_ENUM', 'CNV_STEREO_POLARITY_LEFT', + 'CNV_STEREO_POLARITY_RIGHT', 'CNV_STEREO_SPLIT_DISABLE', + 'CNV_STEREO_SPLIT_ENABLE', 'CNV_STEREO_SPLIT_ENUM', + 'CNV_STEREO_TYPE_ENUM', 'CNV_STEREO_TYPE_FRAME_SEQUENTIAL', + 'CNV_STEREO_TYPE_RESERVED0', 'CNV_STEREO_TYPE_RESERVED1', + 'CNV_STEREO_TYPE_RESERVED2', 'CNV_TEST_CRC_CONT_DISABLE', + 'CNV_TEST_CRC_CONT_ENABLE', 'CNV_TEST_CRC_CONT_EN_ENUM', + 'CNV_TEST_CRC_DISABLE', 'CNV_TEST_CRC_ENABLE', + 'CNV_TEST_CRC_EN_ENUM', 'CNV_UPDATE_LOCK', 'CNV_UPDATE_LOCK_ENUM', + 'CNV_UPDATE_PENDING_ENUM', 'CNV_UPDATE_PENDING_NEG', + 'CNV_UPDATE_PENDING_POS', 'CNV_UPDATE_UNLOCK', + 'CNV_WINDOW_CROP_DISABLE', 'CNV_WINDOW_CROP_ENABLE', + 'CNV_WINDOW_CROP_EN_ENUM', 'COEF_ICSC', 'COEF_ICSC_B', + 'COEF_RAM_SELECT_BACK', 'COEF_RAM_SELECT_CURRENT', + 'COEF_RAM_SELECT_RD', 'COLOR_10_10_10_2', 'COLOR_10_11_11', + 'COLOR_11_11_10', 'COLOR_16', 'COLOR_16_16', 'COLOR_16_16_16_16', + 'COLOR_1_5_5_5', 'COLOR_24BIT_1BIT_AND', + 'COLOR_24BIT_8BIT_ALPHA_PREMULT', + 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', 'COLOR_24_8', + 'COLOR_2_10_10_10', 'COLOR_2_10_10_10_6E4', 'COLOR_32', + 'COLOR_32_32', 'COLOR_32_32_32_32', 'COLOR_4_4_4_4', + 'COLOR_5_5_5_1', 'COLOR_5_6_5', 'COLOR_64BIT_FP_PREMULT', + 'COLOR_64BIT_FP_UNPREMULT', 'COLOR_8', 'COLOR_8_24', 'COLOR_8_8', + 'COLOR_8_8_8_8', 'COLOR_INVALID', 'COLOR_KEYER_MODE', + 'COLOR_RESERVED_13', 'COLOR_RESERVED_15', 'COLOR_RESERVED_23', + 'COLOR_RESERVED_24', 'COLOR_RESERVED_25', 'COLOR_RESERVED_26', + 'COLOR_RESERVED_27', 'COLOR_RESERVED_28', 'COLOR_RESERVED_29', + 'COLOR_RESERVED_30', 'COLOR_X24_8_32_FLOAT', 'COMB_DST_MINUS_SRC', + 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', 'COMB_MIN_DST_SRC', + 'COMB_SRC_MINUS_DST', 'CONFIG_128B_SWAPS', 'CONFIG_1KB_ROW', + 'CONFIG_1KB_ROW_OPT', 'CONFIG_1KB_SPLIT', 'CONFIG_1KB_SWAPS', + 'CONFIG_1_PIPE', 'CONFIG_256B_GROUP', 'CONFIG_256B_SWAPS', + 'CONFIG_2KB_ROW', 'CONFIG_2KB_ROW_OPT', 'CONFIG_2KB_SPLIT', + 'CONFIG_2_PIPE', 'CONFIG_4KB_ROW', 'CONFIG_4KB_ROW_OPT', + 'CONFIG_4KB_SPLIT', 'CONFIG_4_BANK', 'CONFIG_4_PIPE', + 'CONFIG_512B_GROUP', 'CONFIG_512B_SWAPS', 'CONFIG_8KB_ROW', + 'CONFIG_8KB_ROW_OPT', 'CONFIG_8KB_SPLIT', 'CONFIG_8_BANK', + 'CONFIG_8_PIPE', 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', + 'CONFIG_SPACE2_END', 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', + 'CONFIG_SPACE_START', 'CONTEXT_DONE', 'CONTEXT_SPACE_END', + 'CONTEXT_SPACE_START', 'CONTEXT_SUSPEND', + 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', + 'CORB_READ_POINTER_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', + 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_LATENCY_STATS_SEL', + 'CPC_LATENCY_STATS_SEL_INVAL_LAST', + 'CPC_LATENCY_STATS_SEL_INVAL_MAX', + 'CPC_LATENCY_STATS_SEL_INVAL_MIN', + 'CPC_LATENCY_STATS_SEL_XACK_LAST', + 'CPC_LATENCY_STATS_SEL_XACK_MAX', + 'CPC_LATENCY_STATS_SEL_XACK_MIN', + 'CPC_LATENCY_STATS_SEL_XNACK_LAST', + 'CPC_LATENCY_STATS_SEL_XNACK_MAX', + 'CPC_LATENCY_STATS_SEL_XNACK_MIN', 'CPC_PERFCOUNT_SEL', + 'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_CPC_GCRIU_BUSY', + 'CPC_PERF_SEL_CPC_GCRIU_IDLE', 'CPC_PERF_SEL_CPC_GCRIU_STALL', + 'CPC_PERF_SEL_CPC_STAT_BUSY', 'CPC_PERF_SEL_CPC_STAT_IDLE', + 'CPC_PERF_SEL_CPC_STAT_STALL', 'CPC_PERF_SEL_CPC_TCIU_BUSY', + 'CPC_PERF_SEL_CPC_TCIU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', + 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', + 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', + 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', + 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', + 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', + 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', + 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE', + 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE', + 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', + 'CPF_LATENCY_STATS_SEL', 'CPF_LATENCY_STATS_SEL_INVAL_LAST', + 'CPF_LATENCY_STATS_SEL_INVAL_MAX', + 'CPF_LATENCY_STATS_SEL_INVAL_MIN', + 'CPF_LATENCY_STATS_SEL_READ_LAST', + 'CPF_LATENCY_STATS_SEL_READ_MAX', + 'CPF_LATENCY_STATS_SEL_READ_MIN', + 'CPF_LATENCY_STATS_SEL_XACK_LAST', + 'CPF_LATENCY_STATS_SEL_XACK_MAX', + 'CPF_LATENCY_STATS_SEL_XACK_MIN', + 'CPF_LATENCY_STATS_SEL_XNACK_LAST', + 'CPF_LATENCY_STATS_SEL_XNACK_MAX', + 'CPF_LATENCY_STATS_SEL_XNACK_MIN', 'CPF_PERFCOUNTWINDOW_SEL', + 'CPF_PERFCOUNT_SEL', 'CPF_PERFWINDOW_SEL_CSF', + 'CPF_PERFWINDOW_SEL_HQD1', 'CPF_PERFWINDOW_SEL_HQD2', + 'CPF_PERFWINDOW_SEL_RDMA', 'CPF_PERFWINDOW_SEL_RWPP', + 'CPF_PERF_SEL_ALWAYS_COUNT', + 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', + 'CPF_PERF_SEL_CPF_GCRIU_BUSY', 'CPF_PERF_SEL_CPF_GCRIU_IDLE', + 'CPF_PERF_SEL_CPF_GCRIU_STALL', 'CPF_PERF_SEL_CPF_STAT_BUSY', + 'CPF_PERF_SEL_CPF_STAT_IDLE', 'CPF_PERF_SEL_CPF_STAT_STALL', + 'CPF_PERF_SEL_CPF_TCIU_BUSY', 'CPF_PERF_SEL_CPF_TCIU_IDLE', + 'CPF_PERF_SEL_CPF_TCIU_STALL', 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', + 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', + 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', + 'CPF_PERF_SEL_CPG_TCIU_STALL', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR', + 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', + 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 'CPF_PERF_SEL_GUS_READ_REQUEST_SEND', + 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SEND', + 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS', + 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE', + 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPF_TAG_RAM', + 'CPG_LATENCY_STATS_SEL', 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', + 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', + 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', + 'CPG_LATENCY_STATS_SEL_INVAL_LAST', + 'CPG_LATENCY_STATS_SEL_INVAL_MAX', + 'CPG_LATENCY_STATS_SEL_INVAL_MIN', + 'CPG_LATENCY_STATS_SEL_READ_LAST', + 'CPG_LATENCY_STATS_SEL_READ_MAX', + 'CPG_LATENCY_STATS_SEL_READ_MIN', + 'CPG_LATENCY_STATS_SEL_WRITE_LAST', + 'CPG_LATENCY_STATS_SEL_WRITE_MAX', + 'CPG_LATENCY_STATS_SEL_WRITE_MIN', + 'CPG_LATENCY_STATS_SEL_XACK_LAST', + 'CPG_LATENCY_STATS_SEL_XACK_MAX', + 'CPG_LATENCY_STATS_SEL_XACK_MIN', + 'CPG_LATENCY_STATS_SEL_XNACK_LAST', + 'CPG_LATENCY_STATS_SEL_XNACK_MAX', + 'CPG_LATENCY_STATS_SEL_XNACK_MIN', 'CPG_PERFCOUNTWINDOW_SEL', + 'CPG_PERFCOUNT_SEL', 'CPG_PERFWINDOW_SEL_APPEND', + 'CPG_PERFWINDOW_SEL_CE', 'CPG_PERFWINDOW_SEL_CEDMA', + 'CPG_PERFWINDOW_SEL_CPC_IC', 'CPG_PERFWINDOW_SEL_CPG_IC', + 'CPG_PERFWINDOW_SEL_DDID', 'CPG_PERFWINDOW_SEL_DFY', + 'CPG_PERFWINDOW_SEL_DMA', 'CPG_PERFWINDOW_SEL_ME', + 'CPG_PERFWINDOW_SEL_MEC1', 'CPG_PERFWINDOW_SEL_MEC2', + 'CPG_PERFWINDOW_SEL_MEMRD', 'CPG_PERFWINDOW_SEL_MEMWR', + 'CPG_PERFWINDOW_SEL_MES', 'CPG_PERFWINDOW_SEL_PFP', + 'CPG_PERFWINDOW_SEL_PQ1', 'CPG_PERFWINDOW_SEL_PQ2', + 'CPG_PERFWINDOW_SEL_PQ3', 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', + 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', 'CPG_PERFWINDOW_SEL_QURD', + 'CPG_PERFWINDOW_SEL_QU_EOP', 'CPG_PERFWINDOW_SEL_QU_PIPE', + 'CPG_PERFWINDOW_SEL_QU_STRM', 'CPG_PERFWINDOW_SEL_RB', + 'CPG_PERFWINDOW_SEL_RESERVED1', 'CPG_PERFWINDOW_SEL_RESERVED2', + 'CPG_PERFWINDOW_SEL_SHADOW', 'CPG_PERFWINDOW_SEL_SR', + 'CPG_PERFWINDOW_SEL_VGT0', 'CPG_PERFWINDOW_SEL_VGT1', + 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', 'CPG_PERF_SEL_ALWAYS_COUNT', + 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', + 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU', + 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CPG_GCRIU_BUSY', + 'CPG_PERF_SEL_CPG_GCRIU_IDLE', 'CPG_PERF_SEL_CPG_GCRIU_STALL', + 'CPG_PERF_SEL_CPG_STAT_BUSY', 'CPG_PERF_SEL_CPG_STAT_IDLE', + 'CPG_PERF_SEL_CPG_STAT_STALL', 'CPG_PERF_SEL_CPG_TCIU_BUSY', + 'CPG_PERF_SEL_CPG_TCIU_IDLE', 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', + 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', + 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', + 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR', + 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL', + 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', + 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', 'CPG_PERF_SEL_ME_PARSER_BUSY', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', + 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS', + 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', + 'CP_ALPHA_TAG_RAM_SEL', 'CP_DDID_CNTL_MODE', 'CP_DDID_CNTL_SIZE', + 'CP_DDID_CNTL_VMID_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE', + 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', + 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', + 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', + 'CRC_CUR_0', 'CRC_CUR_1', 'CRC_CUR_BITS_0', 'CRC_CUR_BITS_1', + 'CRC_CUR_BITS_SEL', 'CRC_CUR_SEL', 'CRC_INTERLACE_0', + 'CRC_INTERLACE_1', 'CRC_INTERLACE_2', 'CRC_INTERLACE_3', + 'CRC_INTERLACE_SEL', 'CRC_IN_CUR_0', 'CRC_IN_CUR_1', + 'CRC_IN_CUR_SEL', 'CRC_IN_PIX_0', 'CRC_IN_PIX_1', 'CRC_IN_PIX_2', + 'CRC_IN_PIX_3', 'CRC_IN_PIX_4', 'CRC_IN_PIX_5', 'CRC_IN_PIX_6', + 'CRC_IN_PIX_7', 'CRC_IN_PIX_SEL', 'CRC_SRC_0', 'CRC_SRC_1', + 'CRC_SRC_2', 'CRC_SRC_3', 'CRC_SRC_SEL', 'CRC_STEREO_0', + 'CRC_STEREO_1', 'CRC_STEREO_2', 'CRC_STEREO_3', 'CRC_STEREO_SEL', + 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', + 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'CROB_MEM_PWR_LIGHT_SLEEP_MODE', 'CROSSBAR_FOR_ALPHA', + 'CROSSBAR_FOR_CB_B', 'CROSSBAR_FOR_CR_R', 'CROSSBAR_FOR_Y_G', + 'CR_R_DATA_ON_ALPHA_PORT', 'CR_R_DATA_ON_CB_B_PORT', + 'CR_R_DATA_ON_CR_R_PORT', 'CR_R_DATA_ON_Y_G_PORT', + 'CSCNTL_ADDR_WIDTH', 'CSCNTL_DATA_WIDTH', 'CSCNTL_TYPE', + 'CSCNTL_TYPE_EVENT', 'CSCNTL_TYPE_PRIVATE', 'CSCNTL_TYPE_STATE', + 'CSCNTL_TYPE_TG', 'CSCNTL_TYPE_WIDTH', 'CSDATA_ADDR_WIDTH', + 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT', + 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG', + 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_NA', + 'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CURSOR_2X_MAGNIFY', + 'CURSOR_2X_MAGNIFY_IS_DISABLE', 'CURSOR_2X_MAGNIFY_IS_ENABLE', + 'CURSOR_COLOR_24BIT_1BIT_AND', + 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', + 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 'CURSOR_COLOR_64BIT_FP_PREMULT', + 'CURSOR_COLOR_64BIT_FP_UNPREMULT', 'CURSOR_ENABLE', + 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', + 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', 'CURSOR_IS_DISABLE', + 'CURSOR_IS_ENABLE', 'CURSOR_IS_NOT_SNOOP', 'CURSOR_IS_SNOOP', + 'CURSOR_LINES_PER_CHUNK', 'CURSOR_LINE_PER_CHUNK_1', + 'CURSOR_LINE_PER_CHUNK_16', 'CURSOR_LINE_PER_CHUNK_2', + 'CURSOR_LINE_PER_CHUNK_4', 'CURSOR_LINE_PER_CHUNK_8', + 'CURSOR_MODE', 'CURSOR_MONO_2BIT', + 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', + 'CURSOR_PERFMON_LATENCY_MEASURE_EN', + 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', + 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', + 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', + 'CURSOR_PERFMON_LATENCY_MEASURE_SEL', 'CURSOR_PITCH', + 'CURSOR_PITCH_128_PIXELS', 'CURSOR_PITCH_256_PIXELS', + 'CURSOR_PITCH_64_PIXELS', 'CURSOR_SNOOP', 'CURSOR_STEREO_EN', + 'CURSOR_STEREO_IS_DISABLED', 'CURSOR_STEREO_IS_ENABLED', + 'CURSOR_SURFACE_IS_NOT_TMZ', 'CURSOR_SURFACE_IS_TMZ', + 'CURSOR_SURFACE_TMZ', 'CURSOR_SYSTEM', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', + 'CUR_CLAMP_DIS', 'CUR_CLAMP_EN', 'CUR_DIS', + 'CUR_DYNAMIC_EXPANSION', 'CUR_EN', 'CUR_ENABLE', + 'CUR_EXPAND_MODE', 'CUR_FP_NO_ROM', 'CUR_FP_USE_ROM', + 'CUR_INV_CLAMP', 'CUR_MODE', 'CUR_NOT_PENDING', 'CUR_PENDING', + 'CUR_ROM_EN', 'CUR_YES_PENDING', 'CUR_ZERO_EXPANSION', + 'CbYCrY10101010_422_PACKED', 'CbYCrY12121212_422_PACKED', + 'CbYCrY8888_422_PACKED', 'CmaskAddr', 'CmaskCode', 'CmaskMode', + 'ColorArray', 'ColorFormat', 'ColorTransform', 'CombFunc', + 'CompareFrag', 'CompareRef', 'ConservativeZExport', + 'CovToShaderSel', 'CrYCbA1010102', 'CrYCbA16161616_10LSB', + 'CrYCbA16161616_10MSB', 'CrYCbA16161616_12LSB', + 'CrYCbA16161616_12MSB', 'CrYCbA8888', 'CrYCbY10101010_422_PACKED', + 'CrYCbY12121212_422_PACKED', 'CrYCbY8888_422_PACKED', + 'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA', 'DAC_MUX_SELECT_DACB', + 'DB_BREAK_BATCH_EVENT', 'DB_CACHE_FLUSH', + 'DB_CACHE_FLUSH_AND_INV', 'DB_CACHE_FLUSH_AND_INV_EVENT', + 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', 'DB_CACHE_FLUSH_TS', + 'DB_CONTEXT_DONE_EVENT', 'DB_CONTEXT_SUSPEND_EVENT', + 'DB_FLUSH_AND_INV_DB_DATA_TS', 'DB_FLUSH_AND_INV_DB_META', + 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 'DB_PERF_SEL_CB_DB_rdreq_sends', + 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 'DB_PERF_SEL_CB_DB_wrreq_sends', + 'DB_PERF_SEL_DB_CB_context_dones', 'DB_PERF_SEL_DB_CB_eop_dones', + 'DB_PERF_SEL_DB_CB_lquad_busy', + 'DB_PERF_SEL_DB_CB_lquad_double_format', + 'DB_PERF_SEL_DB_CB_lquad_export_quads', + 'DB_PERF_SEL_DB_CB_lquad_fast_format', + 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', + 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', + 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', + 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', + 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', + 'DB_PERF_SEL_DB_CB_lquad_quads', 'DB_PERF_SEL_DB_CB_lquad_sends', + 'DB_PERF_SEL_DB_CB_lquad_slow_format', + 'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack', + 'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy', + 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', + 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', + 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', + 'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls', + 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', + 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', + 'DB_PERF_SEL_DB_SC_c_tile_rate', 'DB_PERF_SEL_DB_SC_quad_busy', + 'DB_PERF_SEL_DB_SC_quad_double_quad', + 'DB_PERF_SEL_DB_SC_quad_lit_quad', + 'DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke', + 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', + 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', + 'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls', + 'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_s_tile_rate', + 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', + 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', + 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 'DB_PERF_SEL_DB_SC_tile_stalls', + 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DB_SC_z_tile_rate', + 'DB_PERF_SEL_DFSM_Flush_flushabit', + 'DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo', + 'DB_PERF_SEL_DFSM_Flush_flushabit_forceflush', + 'DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull', + 'DB_PERF_SEL_DFSM_Flush_flushabit_passthrough', + 'DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark', + 'DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling', + 'DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark', + 'DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark', + 'DB_PERF_SEL_DFSM_Flush_flushall', + 'DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush', + 'DB_PERF_SEL_DFSM_Flush_flushall_opmodechange', + 'DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange', + 'DB_PERF_SEL_DFSM_Flush_flushall_watchdog', + 'DB_PERF_SEL_DFSM_Stall_bypass_fifo', + 'DB_PERF_SEL_DFSM_Stall_cam_fifo', + 'DB_PERF_SEL_DFSM_Stall_control_fifo', + 'DB_PERF_SEL_DFSM_Stall_middle_output', + 'DB_PERF_SEL_DFSM_Stall_opmode_change', + 'DB_PERF_SEL_DFSM_Stall_overflow_counter', + 'DB_PERF_SEL_DFSM_Stall_pops_stall_overflow', + 'DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush', + 'DB_PERF_SEL_DFSM_Stall_retained_tile_fifo', + 'DB_PERF_SEL_DFSM_Stall_stalling_general', + 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream', + 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO', + 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow', + 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark', + 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark', + 'DB_PERF_SEL_DFSM_evicted_tiles_above_watermark', + 'DB_PERF_SEL_DFSM_full_cleared_squads_out', + 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out', + 'DB_PERF_SEL_DFSM_fully_cleared_quads_out', + 'DB_PERF_SEL_DFSM_lit_pixels_in', + 'DB_PERF_SEL_DFSM_lit_samples_in', + 'DB_PERF_SEL_DFSM_lit_samples_out', + 'DB_PERF_SEL_DFSM_prez_killed_squad', 'DB_PERF_SEL_DFSM_quads_in', + 'DB_PERF_SEL_DFSM_squads_in', + 'DB_PERF_SEL_DFSM_stalled_by_downstream', + 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 'DB_PERF_SEL_Depth_Tile_Cache_event', + 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', + 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 'DB_PERF_SEL_Plane_Cache_flushes', + 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', + 'DB_PERF_SEL_Plane_Cache_misses', + 'DB_PERF_SEL_Plane_Cache_starves', + 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 'DB_PERF_SEL_PostZ_Samples_failing_S', + 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 'DB_PERF_SEL_PreZ_Samples_failing_S', + 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 'DB_PERF_SEL_SC_DB_quad_busy', + 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_quads', + 'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads', + 'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_tile_backface', + 'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered', + 'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends', + 'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles', + 'DB_PERF_SEL_SH_quads_outstanding_sum', + 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', + 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', + 'DB_PERF_SEL_SX_DB_quad_busy', + 'DB_PERF_SEL_SX_DB_quad_double_format', + 'DB_PERF_SEL_SX_DB_quad_export_quads', + 'DB_PERF_SEL_SX_DB_quad_exports', + 'DB_PERF_SEL_SX_DB_quad_fast_format', + 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', + 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', + 'DB_PERF_SEL_SX_DB_quad_sends', + 'DB_PERF_SEL_SX_DB_quad_slow_format', + 'DB_PERF_SEL_SX_DB_quad_stalls', + 'DB_PERF_SEL_Stencil_Cache_flushes', + 'DB_PERF_SEL_Stencil_Cache_frees', + 'DB_PERF_SEL_Stencil_Cache_hits', + 'DB_PERF_SEL_Stencil_Cache_misses', + 'DB_PERF_SEL_Stencil_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', + 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_surface_stall', + 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 'DB_PERF_SEL_Z_Cache_pmask_hits', + 'DB_PERF_SEL_Z_Cache_pmask_misses', + 'DB_PERF_SEL_Z_Cache_pmask_starves', + 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 'DB_PERF_SEL_clock_main_active', + 'DB_PERF_SEL_clock_mem_export_active', + 'DB_PERF_SEL_clock_reg_active', + 'DB_PERF_SEL_depth_bounds_tile_culled', 'DB_PERF_SEL_di_dt_stall', + 'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends', + 'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy', + 'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends', + 'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile', + 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', + 'DB_PERF_SEL_dtt_sm_slot_stall', + 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', + 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', + 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_sqq_busy', + 'DB_PERF_SEL_esr_ps_sqq_stall', 'DB_PERF_SEL_esr_ps_src_in_sends', + 'DB_PERF_SEL_esr_ps_src_in_squads', + 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_stall', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_sqq_zi_busy', + 'DB_PERF_SEL_esr_sqq_zi_stall', 'DB_PERF_SEL_etr_out_busy', + 'DB_PERF_SEL_etr_out_cb_tile_stall', + 'DB_PERF_SEL_etr_out_esr_stall', + 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', + 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', + 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', + 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', + 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', + 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', + 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', + 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', + 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', + 'DB_PERF_SEL_flush_compressed_stencil', + 'DB_PERF_SEL_flush_expanded_stencil', + 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', + 'DB_PERF_SEL_flush_single_stencil', 'DB_PERF_SEL_his_tile_culled', + 'DB_PERF_SEL_hiz_tc_read_starved', + 'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_hiz_tile_culled', + 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', + 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', + 'DB_PERF_SEL_planes_flushed', 'DB_PERF_SEL_postzl_full_launch', + 'DB_PERF_SEL_postzl_partial_launch', + 'DB_PERF_SEL_postzl_partial_waiting', + 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', + 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', + 'DB_PERF_SEL_postzl_src_in_sends', + 'DB_PERF_SEL_postzl_src_in_squads', + 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 'DB_PERF_SEL_postzl_src_in_stall', + 'DB_PERF_SEL_postzl_src_in_tile_rate', + 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_postzl_src_out_stall', + 'DB_PERF_SEL_postzl_tile_init_stall', + 'DB_PERF_SEL_postzl_tile_mem_stall', + 'DB_PERF_SEL_prezl_src_in_sends', + 'DB_PERF_SEL_prezl_src_in_squads', + 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 'DB_PERF_SEL_prezl_src_in_stall', + 'DB_PERF_SEL_prezl_src_in_tile_rate', + 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_prezl_src_out_stall', + 'DB_PERF_SEL_prezl_tile_init_stall', + 'DB_PERF_SEL_prezl_tile_mem_stall', 'DB_PERF_SEL_qc_busy', + 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', + 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', + 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', + 'DB_PERF_SEL_quad_rd_mi_stall', 'DB_PERF_SEL_quad_rd_panic', + 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', + 'DB_PERF_SEL_quad_rd_tag_stall', 'DB_PERF_SEL_quad_rdret_busy', + 'DB_PERF_SEL_quad_rdret_sends', 'DB_PERF_SEL_quad_wr_acks', + 'DB_PERF_SEL_quad_wr_busy', 'DB_PERF_SEL_quad_wr_coherency_stall', + 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', + 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', + 'DB_PERF_SEL_tcp_dispatcher_flushes', + 'DB_PERF_SEL_tcp_dispatcher_reads', + 'DB_PERF_SEL_tcp_prefetcher_flushes', + 'DB_PERF_SEL_tcp_prefetcher_reads', + 'DB_PERF_SEL_tcp_preloader_flushes', + 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', + 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', + 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 'DB_PERF_SEL_tiles_decomp_on_expclear', + 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', + 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', + 'DB_PERF_SEL_tl_expand_squads', + 'DB_PERF_SEL_tl_flush_expand_squads', + 'DB_PERF_SEL_tl_in_fast_z_stall', + 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', + 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', + 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', + 'DB_PERF_SEL_tl_preZ_squads', + 'DB_PERF_SEL_tl_stencil_locked_stall', + 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', + 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', + 'DB_PERF_SEL_tl_z_fetch_stall', 'DB_PERF_SEL_ts_tc_update_stall', + 'DB_PERF_SEL_tsc_insert_summarize_stall', + 'DB_PERF_SEL_unmapped_z_tile_culled', + 'DB_PERF_SEL_zf_plane_multicycle', 'DB_PSINVOKE_CHANGE_EVENT', + 'DB_VPORT_CHANGED_EVENT', 'DCCG_AUDIO_DTO0_SOURCE_SEL', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', + 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', 'DCCG_AUDIO_DTO_SEL', + 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', + 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 'DCCG_AUDIO_DTO_USE_512FBR_DTO', + 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DEEP_COLOR_CNTL', + 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', + 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', + 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', + 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', + 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', + 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_MODE_HSYNC', + 'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START', + 'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP', + 'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_OTG_SELECT', + 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', + 'DCCG_PERF_SEL_OTG0', 'DCCG_PERF_SEL_OTG1', 'DCCG_PERF_SEL_OTG2', + 'DCCG_PERF_SEL_OTG3', 'DCCG_PERF_SEL_OTG4', 'DCCG_PERF_SEL_OTG5', + 'DCCG_PERF_SEL_RESERVED', 'DCC_CT_AUTO', 'DCC_CT_NONE', + 'DCIOCHIP_2BIT_DISABLE', 'DCIOCHIP_2BIT_ENABLE', + 'DCIOCHIP_4BIT_DISABLE', 'DCIOCHIP_4BIT_ENABLE', + 'DCIOCHIP_5BIT_DISABLE', 'DCIOCHIP_5BIT_ENABLE', + 'DCIOCHIP_AUXSLAVE_PAD_MODE', 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX', + 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', 'DCIOCHIP_AUX_ALL_PWR_OK', + 'DCIOCHIP_AUX_ALL_PWR_OK_0', 'DCIOCHIP_AUX_ALL_PWR_OK_1', + 'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1', + 'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0', + 'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1', + 'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_HYS_TUNE', + 'DCIOCHIP_AUX_HYS_TUNE_0', 'DCIOCHIP_AUX_HYS_TUNE_1', + 'DCIOCHIP_AUX_HYS_TUNE_2', 'DCIOCHIP_AUX_HYS_TUNE_3', + 'DCIOCHIP_AUX_RECEIVER_SEL', 'DCIOCHIP_AUX_RECEIVER_SEL_0', + 'DCIOCHIP_AUX_RECEIVER_SEL_1', 'DCIOCHIP_AUX_RECEIVER_SEL_2', + 'DCIOCHIP_AUX_RECEIVER_SEL_3', 'DCIOCHIP_AUX_RSEL0P9', + 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', + 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', + 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', + 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', + 'DCIOCHIP_AUX_VOD_TUNE', 'DCIOCHIP_AUX_VOD_TUNE_0', + 'DCIOCHIP_AUX_VOD_TUNE_1', 'DCIOCHIP_AUX_VOD_TUNE_2', + 'DCIOCHIP_AUX_VOD_TUNE_3', 'DCIOCHIP_DVO_VREFPON', + 'DCIOCHIP_DVO_VREFPON_DISABLE', 'DCIOCHIP_DVO_VREFPON_ENABLE', + 'DCIOCHIP_DVO_VREFSEL', 'DCIOCHIP_DVO_VREFSEL_EXTERNAL', + 'DCIOCHIP_DVO_VREFSEL_ONCHIP', 'DCIOCHIP_ENABLE_2BIT', + 'DCIOCHIP_ENABLE_4BIT', 'DCIOCHIP_ENABLE_5BIT', + 'DCIOCHIP_GPIO_I2C_DISABLE', 'DCIOCHIP_GPIO_I2C_DRIVE', + 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', 'DCIOCHIP_GPIO_I2C_DRIVE_LOW', + 'DCIOCHIP_GPIO_I2C_EN', 'DCIOCHIP_GPIO_I2C_ENABLE', + 'DCIOCHIP_GPIO_I2C_MASK', 'DCIOCHIP_GPIO_I2C_MASK_DISABLE', + 'DCIOCHIP_GPIO_I2C_MASK_ENABLE', 'DCIOCHIP_GPIO_MASK_EN', + 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', + 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', + 'DCIOCHIP_I2C_COMPSEL', 'DCIOCHIP_I2C_FALLSLEWSEL', + 'DCIOCHIP_I2C_FALLSLEWSEL_00', 'DCIOCHIP_I2C_FALLSLEWSEL_01', + 'DCIOCHIP_I2C_FALLSLEWSEL_10', 'DCIOCHIP_I2C_FALLSLEWSEL_11', + 'DCIOCHIP_I2C_RECEIVER_SEL', 'DCIOCHIP_I2C_RECEIVER_SEL_0', + 'DCIOCHIP_I2C_RECEIVER_SEL_1', 'DCIOCHIP_I2C_RECEIVER_SEL_2', + 'DCIOCHIP_I2C_RECEIVER_SEL_3', 'DCIOCHIP_I2C_REC_COMPARATOR', + 'DCIOCHIP_I2C_REC_SCHMIT', 'DCIOCHIP_I2C_VPH_1V2_EN', + 'DCIOCHIP_I2C_VPH_1V2_EN_0', 'DCIOCHIP_I2C_VPH_1V2_EN_1', + 'DCIOCHIP_INVERT', 'DCIOCHIP_MASIK_5BIT_DISABLE', + 'DCIOCHIP_MASIK_5BIT_ENABLE', 'DCIOCHIP_MASK', + 'DCIOCHIP_MASK_2BIT', 'DCIOCHIP_MASK_2BIT_DISABLE', + 'DCIOCHIP_MASK_2BIT_ENABLE', 'DCIOCHIP_MASK_4BIT', + 'DCIOCHIP_MASK_4BIT_DISABLE', 'DCIOCHIP_MASK_4BIT_ENABLE', + 'DCIOCHIP_MASK_5BIT', 'DCIOCHIP_MASK_DISABLE', + 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', + 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', + 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', + 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', + 'DCIOCHIP_REF_27_SRC_SEL', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', 'DCIOCHIP_SPDIF1_IMODE', + 'DCIOCHIP_SPDIF1_IMODE_OE_A', 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO', + 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN', + 'DCIO_BL_PWM_CNTL_BL_PWM_EN', + 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', 'DCIO_BL_PWM_DISABLE', + 'DCIO_BL_PWM_ENABLE', 'DCIO_BL_PWM_FRACTIONAL_DISABLE', + 'DCIO_BL_PWM_FRACTIONAL_ENABLE', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', + 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', + 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', + 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', + 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', + 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 'DCIO_BL_PWM_GRP1_REG_LOCK', 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE', + 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE', + 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START', + 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', + 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL', + 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM', + 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', + 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', 'DCIO_DACA_SOFT_RESET', + 'DCIO_DACA_SOFT_RESET_ASSERT', 'DCIO_DACA_SOFT_RESET_DEASSERT', + 'DCIO_DCRXPHY_SOFT_RESET', 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', + 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', + 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN', + 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN', + 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN', 'DCIO_DC_GENERICA_SEL', + 'DCIO_DC_GENERICB_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', + 'DCIO_DC_GPU_TIMER_READ_SELECT', + 'DCIO_DC_GPU_TIMER_START_POSITION', + 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', + 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL', + 'DCIO_DIO_EXT_VSYNC_MASK', 'DCIO_DIO_OTG_EXT_VSYNC_MUX', + 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', + 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', + 'DCIO_DPCS_INTERRUPT_TYPE', + 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', 'DCIO_DPHY_LANE_SEL', + 'DCIO_DPHY_LANE_SEL_LANE0', 'DCIO_DPHY_LANE_SEL_LANE1', + 'DCIO_DPHY_LANE_SEL_LANE2', 'DCIO_DPHY_LANE_SEL_LANE3', + 'DCIO_DSYNC_SOFT_RESET', 'DCIO_DSYNC_SOFT_RESET_ASSERT', + 'DCIO_DSYNC_SOFT_RESET_DEASSERT', + 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE', + 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', 'DCIO_EXT_VSYNC_MASK_NONE', + 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', 'DCIO_EXT_VSYNC_MASK_PIPE0', + 'DCIO_EXT_VSYNC_MASK_PIPE1', 'DCIO_EXT_VSYNC_MASK_PIPE2', + 'DCIO_EXT_VSYNC_MASK_PIPE3', 'DCIO_EXT_VSYNC_MASK_PIPE4', + 'DCIO_EXT_VSYNC_MASK_PIPE5', 'DCIO_EXT_VSYNC_MUX_GENERICB', + 'DCIO_EXT_VSYNC_MUX_OTG0', 'DCIO_EXT_VSYNC_MUX_OTG1', + 'DCIO_EXT_VSYNC_MUX_OTG2', 'DCIO_EXT_VSYNC_MUX_OTG3', + 'DCIO_EXT_VSYNC_MUX_OTG4', 'DCIO_EXT_VSYNC_MUX_OTG5', + 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER', + 'DCIO_GENERICA_SEL_DACA_PIXCLK', + 'DCIO_GENERICA_SEL_DACA_STEREOSYNC', + 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER', + 'DCIO_GENERICA_SEL_DACB_PIXCLK', 'DCIO_GENERICA_SEL_DVOA_CTL3', + 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC', + 'DCIO_GENERICA_SEL_GENERICA_DCCG', + 'DCIO_GENERICA_SEL_GENERICA_DPRX', + 'DCIO_GENERICA_SEL_GENERICB_DPRX', 'DCIO_GENERICA_SEL_P1_PLLCLK', + 'DCIO_GENERICA_SEL_P2_PLLCLK', 'DCIO_GENERICA_SEL_STEREOSYNC', + 'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK', + 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2', + 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK', + 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK', + 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER', + 'DCIO_GENERICB_SEL_DACA_PIXCLK', + 'DCIO_GENERICB_SEL_DACA_STEREOSYNC', + 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER', + 'DCIO_GENERICB_SEL_DACB_PIXCLK', 'DCIO_GENERICB_SEL_DVOA_CTL3', + 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC', + 'DCIO_GENERICB_SEL_GENERICB_DCCG', 'DCIO_GENERICB_SEL_P1_PLLCLK', + 'DCIO_GENERICB_SEL_P2_PLLCLK', 'DCIO_GENERICB_SEL_STEREOSYNC', + 'DCIO_GENERICB_SEL_SYNCEN', 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK', + 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2', + 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK', + 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', 'DCIO_GENLK_CLK_GSL_MASK', + 'DCIO_GENLK_CLK_GSL_MASK_NO', 'DCIO_GENLK_CLK_GSL_MASK_STEREO', + 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', + 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', + 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', + 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', + 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', + 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', + 'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', + 'DCIO_GSL_SEL_GROUP_2', 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', + 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', + 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', 'DCIO_IMPCAL_STEP_DELAY', + 'DCIO_IMPCAL_STEP_DELAY_10us', 'DCIO_IMPCAL_STEP_DELAY_11us', + 'DCIO_IMPCAL_STEP_DELAY_12us', 'DCIO_IMPCAL_STEP_DELAY_13us', + 'DCIO_IMPCAL_STEP_DELAY_14us', 'DCIO_IMPCAL_STEP_DELAY_15us', + 'DCIO_IMPCAL_STEP_DELAY_16us', 'DCIO_IMPCAL_STEP_DELAY_1us', + 'DCIO_IMPCAL_STEP_DELAY_2us', 'DCIO_IMPCAL_STEP_DELAY_3us', + 'DCIO_IMPCAL_STEP_DELAY_4us', 'DCIO_IMPCAL_STEP_DELAY_5us', + 'DCIO_IMPCAL_STEP_DELAY_6us', 'DCIO_IMPCAL_STEP_DELAY_7us', + 'DCIO_IMPCAL_STEP_DELAY_8us', 'DCIO_IMPCAL_STEP_DELAY_9us', + 'DCIO_LVTMA_BLON_OFF', 'DCIO_LVTMA_BLON_ON', + 'DCIO_LVTMA_BLON_POL_INVERT', 'DCIO_LVTMA_BLON_POL_NON_INVERT', + 'DCIO_LVTMA_DIGON_OFF', 'DCIO_LVTMA_DIGON_ON', + 'DCIO_LVTMA_DIGON_POL_INVERT', 'DCIO_LVTMA_DIGON_POL_NON_INVERT', + 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL', + 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE', + 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN', + 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE', + 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE', + 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF', + 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON', + 'DCIO_LVTMA_SYNCEN_POL_INVERT', + 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT', + 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON', + 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE', + 'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO', + 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', + 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', + 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SOCCLK', + 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', + 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', + 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', + 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', + 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', + 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', + 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', + 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', + 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', + 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', + 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', + 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS', + 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE', + 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', 'DCIO_VIP_MUX_EN_DVO', + 'DCIO_VIP_MUX_EN_VIP', 'DC_DMCUB_INT_TYPE', + 'DC_DMCUB_TIMER_WINDOW', 'DC_MEM_GLOBAL_PWR_REQ_DIS', + 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 'DC_SMU_INTERRUPT_ENABLE', 'DDID_VMID_CNTL', 'DDID_VMID_PIPE', + 'DENORM_TRUNCATE', 'DEPTH_16', 'DEPTH_32_FLOAT', 'DEPTH_8_24', + 'DEPTH_8_24_FLOAT', 'DEPTH_INVALID', 'DEPTH_MICRO_TILING', + 'DEPTH_X24_8_32_FLOAT', 'DEPTH_X8_24', 'DEPTH_X8_24_FLOAT', + 'DETILE_BUFFER_PACKER_ENABLE', 'DETILE_BUFFER_PACKER_IS_DISABLE', + 'DETILE_BUFFER_PACKER_IS_ENABLE', + 'DET_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'DET_MEM_POWER_LIGHT_SLEEP_MODE_2', + 'DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'DET_MEM_PWR_LIGHT_SLEEP_MODE', 'DFQ_MIN_FREE_ENTRIES', + 'DFQ_MIN_FREE_ENTRIES_0', 'DFQ_MIN_FREE_ENTRIES_1', + 'DFQ_MIN_FREE_ENTRIES_2', 'DFQ_MIN_FREE_ENTRIES_3', + 'DFQ_MIN_FREE_ENTRIES_4', 'DFQ_MIN_FREE_ENTRIES_5', + 'DFQ_MIN_FREE_ENTRIES_6', 'DFQ_MIN_FREE_ENTRIES_7', + 'DFQ_NUM_ENTRIES', 'DFQ_NUM_ENTRIES_0', 'DFQ_NUM_ENTRIES_1', + 'DFQ_NUM_ENTRIES_2', 'DFQ_NUM_ENTRIES_3', 'DFQ_NUM_ENTRIES_4', + 'DFQ_NUM_ENTRIES_5', 'DFQ_NUM_ENTRIES_6', 'DFQ_NUM_ENTRIES_7', + 'DFQ_NUM_ENTRIES_8', 'DFQ_SIZE', 'DFQ_SIZE_0', 'DFQ_SIZE_1', + 'DFQ_SIZE_2', 'DFQ_SIZE_3', 'DFQ_SIZE_4', 'DFQ_SIZE_5', + 'DFQ_SIZE_6', 'DFQ_SIZE_7', 'DFSMFlushEvents', + 'DIG_10BIT_TEST_PATTERN', 'DIG_ALL_PIXEL', + 'DIG_ALTERNATING_TEST_PATTERN', 'DIG_BE_CNTL_HPD1', + 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', 'DIG_BE_CNTL_HPD4', + 'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD6', 'DIG_BE_CNTL_HPD_SELECT', + 'DIG_BE_CNTL_MODE', 'DIG_BE_CNTL_NO_HPD', 'DIG_BE_DP_MST_MODE', + 'DIG_BE_DP_SST_MODE', 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', + 'DIG_BE_RESERVED3', 'DIG_BE_RESERVED4', 'DIG_BE_TMDS_DVI_MODE', + 'DIG_BE_TMDS_HDMI_MODE', 'DIG_DIGITAL_BYPASS_SEL', + 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', + 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', + 'DIG_DIGITAL_BYPASS_SEL_36BPP', + 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', + 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', + 'DIG_DIGITAL_BYPASS_SEL_ALPHA', 'DIG_DIGITAL_BYPASS_SEL_BYPASS', + 'DIG_EVEN_PIXEL_ONLY', 'DIG_FE_CNTL_SOURCE_SELECT', + 'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_OTG0', + 'DIG_FE_SOURCE_FROM_OTG1', 'DIG_FE_SOURCE_FROM_OTG2', + 'DIG_FE_SOURCE_FROM_OTG3', 'DIG_FE_SOURCE_FROM_OTG4', + 'DIG_FE_SOURCE_FROM_OTG5', 'DIG_FE_SOURCE_RESERVED', + 'DIG_FE_STEREOSYNC_FROM_OTG0', 'DIG_FE_STEREOSYNC_FROM_OTG1', + 'DIG_FE_STEREOSYNC_FROM_OTG2', 'DIG_FE_STEREOSYNC_FROM_OTG3', + 'DIG_FE_STEREOSYNC_FROM_OTG4', 'DIG_FE_STEREOSYNC_FROM_OTG5', + 'DIG_FE_STEREOSYNC_RESERVED', 'DIG_FIFO_ERROR_ACK', + 'DIG_FIFO_ERROR_ACK_INT', 'DIG_FIFO_ERROR_NOT_ACK', + 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', + 'DIG_FIFO_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_READ_CLOCK_SRC', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', + 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL', + 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', 'DIG_FIFO_USE_OVERWRITE_LEVEL', + 'DIG_INPUT_PIXEL_SEL', 'DIG_IN_DEBUG_MODE', + 'DIG_IN_NORMAL_OPERATION', 'DIG_ODD_PIXEL_ONLY', + 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', 'DIG_OUTPUT_CRC_DATA_SEL', + 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', 'DIG_OUTPUT_CRC_FOR_AUDIO', + 'DIG_OUTPUT_CRC_FOR_FULLFRAME', 'DIG_OUTPUT_CRC_FOR_VBI', + 'DIG_OUTPUT_CRC_ON_LINK0', 'DIG_OUTPUT_CRC_ON_LINK1', + 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', + 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', + 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DIM_TYPE', 'DIM_TYPE_1D', + 'DIM_TYPE_2D', 'DIM_TYPE_3D', 'DIM_TYPE_RESERVED', + 'DIOMEM_DISABLE_MEM_PWR_CTRL', 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', + 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', + 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', + 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', + 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', 'DIOMEM_ENABLE_MEM_PWR_CTRL', + 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', + 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', + 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', 'DIOMEM_NO_FORCE_REQ', + 'DIOMEM_NO_FORCE_REQUEST', 'DIOMEM_PWR_DIS_CTRL', + 'DIOMEM_PWR_FORCE_CTRL', 'DIOMEM_PWR_FORCE_CTRL2', + 'DIOMEM_PWR_SEL_CTRL', 'DIOMEM_PWR_SEL_CTRL2', 'DIO_FIFO_ERROR', + 'DIO_FIFO_ERROR_00', 'DIO_FIFO_ERROR_01', 'DIO_FIFO_ERROR_10', + 'DIO_FIFO_ERROR_11', + 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE', + 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', + 'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC', + 'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO', + 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', 'DISABLE_TF0', + 'DISABLE_TF1', 'DISABLE_THE_CLOCK', 'DISABLE_THE_FEATURE', + 'DISABLE_THE_INTERRUPT', 'DISPCLK_CHG_FWD_CORR_DISABLE', + 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', + 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', + 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DISPLAY_MICRO_TILING', 'DIV_2', + 'DIV_4', 'DIV_8', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', + 'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1', + 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ', + 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', + 'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON', + 'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', + 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', + 'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_TRI_WITH_WFLAGS', + 'DI_PT_UNUSED_1', 'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4', + 'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', + 'DI_SRC_SEL_RESERVED', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', + 'DMDATA_CLEAR_UNDERFLOW_STATUS', 'DMDATA_DONE', + 'DMDATA_DONT_CLEAR', 'DMDATA_HARDWARE_UPDATE_MODE', 'DMDATA_MODE', + 'DMDATA_NOT_SENT_TO_DIG', 'DMDATA_NOT_UNDERFLOW', + 'DMDATA_NOT_UPDATED', 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', + 'DMDATA_QOS_LEVEL_FROM_TTU', 'DMDATA_QOS_MODE', 'DMDATA_REPEAT', + 'DMDATA_SENT_TO_DIG', 'DMDATA_SOFTWARE_UPDATE_MODE', + 'DMDATA_UNDERFLOW', 'DMDATA_UNDERFLOWED', + 'DMDATA_UNDERFLOW_CLEAR', 'DMDATA_UPDATED', + 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', + 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', 'DMDATA_WAS_UPDATED', + 'DMU_CLOCK_GATING_DISABLE', 'DMU_CLOCK_ON', + 'DMU_CLOCK_STATUS_OFF', 'DMU_CLOCK_STATUS_ON', + 'DMU_DC_GPU_TIMER_READ_SELECT', 'DMU_DC_GPU_TIMER_START_POSITION', + 'DMU_DISABLE_CLOCK_GATING', 'DMU_ENABLE_CLOCK_GATING', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75', + 'DMU_GPU_TIMER_START_0_END_27', 'DMU_GPU_TIMER_START_10_END_37', + 'DMU_GPU_TIMER_START_1_END_28', 'DMU_GPU_TIMER_START_2_END_29', + 'DMU_GPU_TIMER_START_3_END_30', 'DMU_GPU_TIMER_START_4_END_31', + 'DMU_GPU_TIMER_START_6_END_33', 'DMU_GPU_TIMER_START_8_END_35', + 'DOLBY_VISION_DISABLED', 'DOLBY_VISION_ENABLE', + 'DOLBY_VISION_ENABLED', 'DONUTS', 'DOUT_I2C_ACK', + 'DOUT_I2C_ACK_TO_CLEAN', + 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_ABORT_XFER', + 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', + 'DOUT_I2C_CONTROL_DDC_SELECT', 'DOUT_I2C_CONTROL_GO', + 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', + 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', + 'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDC6', + 'DOUT_I2C_CONTROL_SELECT_DDCVGA', 'DOUT_I2C_CONTROL_SEND_RESET', + 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH', + 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', + 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', + 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', + 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 'DOUT_I2C_CONTROL__SEND_RESET', + 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', + 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', + 'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE', + 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 'DOUT_I2C_DDC_EDID_DETECT_STATUS', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', + 'DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', + 'DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', + 'DOUT_I2C_DDC_SPEED_THRESHOLD', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', + 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', + 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', + 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DPCSRX_BPHY_PCS_RX0_CLK', + 'DPCSRX_BPHY_PCS_RX1_CLK', 'DPCSRX_BPHY_PCS_RX2_CLK', + 'DPCSRX_BPHY_PCS_RX3_CLK', + 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL', 'DPCSTX_DVI_LINK_MODE', + 'DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER', + 'DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER', + 'DPCSTX_DVI_LINK_MODE_NORMAL', 'DPHY_8B10B_CUR_DISP', + 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', + 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', + 'DPHY_8B10B_RESETET', 'DPHY_ATEST_LANE0_PRBS_PATTERN', + 'DPHY_ATEST_LANE0_REG_PATTERN', 'DPHY_ATEST_LANE1_PRBS_PATTERN', + 'DPHY_ATEST_LANE1_REG_PATTERN', 'DPHY_ATEST_LANE2_PRBS_PATTERN', + 'DPHY_ATEST_LANE2_REG_PATTERN', 'DPHY_ATEST_LANE3_PRBS_PATTERN', + 'DPHY_ATEST_LANE3_REG_PATTERN', 'DPHY_ATEST_SEL_LANE0', + 'DPHY_ATEST_SEL_LANE1', 'DPHY_ATEST_SEL_LANE2', + 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', 'DPHY_CRC_CONTINUOUS', + 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', 'DPHY_CRC_EN', + 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', 'DPHY_CRC_LANE0_SELECTED', + 'DPHY_CRC_LANE1_SELECTED', 'DPHY_CRC_LANE2_SELECTED', + 'DPHY_CRC_LANE3_SELECTED', 'DPHY_CRC_MST_PHASE_ERROR_ACK', + 'DPHY_CRC_MST_PHASE_ERROR_ACKED', + 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', + 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', + 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', + 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 'DPHY_FEC_ACTIVE', 'DPHY_FEC_DISABLED', 'DPHY_FEC_ENABLE', + 'DPHY_FEC_ENABLED', 'DPHY_FEC_NOT_ACTIVE', 'DPHY_FEC_READY', + 'DPHY_FEC_READY_DIS', 'DPHY_FEC_READY_EN', + 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', + 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', + 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', + 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', + 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', + 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SKEW_BYPASS', + 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', + 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', + 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', + 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', + 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', + 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', + 'DPTE_GROUP_SIZE', 'DPTE_GROUP_SIZE_1024B', + 'DPTE_GROUP_SIZE_128B', 'DPTE_GROUP_SIZE_2048B', + 'DPTE_GROUP_SIZE_256B', 'DPTE_GROUP_SIZE_4096B', + 'DPTE_GROUP_SIZE_512B', 'DPTE_GROUP_SIZE_64B', + 'DPTE_GROUP_SIZE_8192B', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', + 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', + 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', + 'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD6_SELECTED', + 'DP_AUX_CONTROL_HPD_SEL', 'DP_AUX_CONTROL_NO_HPD_SELECTED', + 'DP_AUX_CONTROL_TEST_MODE', 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 'DP_AUX_CONTROL_TEST_MODE_ENABLE', + 'DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', + 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', + 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', + 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', + 'DP_AUX_INT__NOT_ACK', 'DP_AUX_LS_UPDATE_ACK', + 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', 'DP_AUX_PHY_WAKE_LOW_PRIORITY', + 'DP_AUX_PHY_WAKE_PRIORITY', 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', + 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', + 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', + 'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_RX_TIMEOUT_LEN_MUL', + 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', + 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', + 'DP_AUX_SW_CONTROL_LS_READ_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', + 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 'DP_AUX_TX_PRECHARGE_LEN_MUL', 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', + 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', + 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', 'DP_COMBINE_FOUR_PIXEL', + 'DP_COMBINE_ONE_PIXEL', 'DP_COMBINE_PIXEL_NUM', + 'DP_COMBINE_TWO_PIXEL', 'DP_COMPONENT_DEPTH', + 'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC', + 'DP_COMPONENT_DEPTH_16BPC_RESERVED', 'DP_COMPONENT_DEPTH_6BPC', + 'DP_COMPONENT_DEPTH_8BPC', 'DP_COMPONENT_DEPTH_RESERVED', + 'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE', + 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', + 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', + 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', + 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', + 'DP_DSC_444_SIMPLE_422', 'DP_DSC_DISABLE', 'DP_DSC_MODE', + 'DP_DSC_NATIVE_422_420', 'DP_DTO_DESPREAD_DISABLE', + 'DP_DTO_DESPREAD_ENABLE', 'DP_DTO_DS_DISABLE', + 'DP_EMBEDDED_PANEL', 'DP_EMBEDDED_PANEL_MODE', + 'DP_EXTERNAL_PANEL', 'DP_LINK_TRAINING_ALREADY_COMPLETE', + 'DP_LINK_TRAINING_COMPLETE', 'DP_LINK_TRAINING_NOT_COMPLETE', + 'DP_LINK_TRAINING_SWITCH_MODE', 'DP_LINK_TRAINING_SWITCH_TO_IDLE', + 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', 'DP_ML_PHY_SEQ_IMMEDIATE', + 'DP_ML_PHY_SEQ_LINE_NUM', 'DP_ML_PHY_SEQ_MODE', + 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', + 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', + 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', + 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', + 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', + 'DP_MSE_SAT_UPDATE_ACT', 'DP_MSE_SAT_UPDATE_NO_ACTION', + 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', + 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', + 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', + 'DP_MSO_FOUR_SSTLINK', 'DP_MSO_NUM_OF_SST_LINKS', + 'DP_MSO_ONE_SSTLINK', 'DP_MSO_TWO_SSTLINK', 'DP_PIXEL_ENCODING', + 'DP_PIXEL_ENCODING_RESERVED', 'DP_PIXEL_ENCODING_RGB444', + 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', 'DP_PIXEL_ENCODING_YCBCR420', + 'DP_PIXEL_ENCODING_YCBCR422', 'DP_PIXEL_ENCODING_YCBCR444', + 'DP_PIXEL_ENCODING_Y_ONLY', 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', + 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', + 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', + 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', + 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', + 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', + 'DP_SEC_GSP_SEND', 'DP_SEC_GSP_SEND_ANY_LINE', + 'DP_SEC_GSP_SEND_PPS', 'DP_SEC_LINE_REFERENCE', + 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE', + 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_STEER_OVERFLOW_ACK', + 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', + 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', + 'DP_SYNC_POLARITY', 'DP_SYNC_POLARITY_ACTIVE_HIGH', + 'DP_SYNC_POLARITY_ACTIVE_LOW', 'DP_TU_OVERFLOW_ACK', + 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', + 'DP_UDI_4_LANES', 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', + 'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_M_1X_INPUT_PIXEL_RATE', + 'DP_VID_M_2X_INPUT_PIXEL_RATE', 'DP_VID_M_4X_INPUT_PIXEL_RATE', + 'DP_VID_M_8X_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO', + 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', + 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', + 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_N_MUL', + 'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK', + 'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', + 'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV', + 'DP_VID_VBID_FIELD_POL_NORMAL', 'DRAW_DONE', + 'DRR_UPDATE_LOCK_SEL', 'DRR_UPDATE_LOCK_SEL_0', + 'DRR_UPDATE_LOCK_SEL_1', 'DRR_UPDATE_LOCK_SEL_2', + 'DRR_UPDATE_LOCK_SEL_3', 'DRR_UPDATE_LOCK_SEL_4', + 'DRR_UPDATE_LOCK_SEL_5', 'DSCCIF_BITS_PER_COMPONENT_ENUM', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 'DSCCIF_ENABLE_ENUM', 'DSCCIF_ENABLE_ENUM_DISABLED', + 'DSCCIF_ENABLE_ENUM_ENABLED', 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', + 'DSCC_BITS_PER_COMPONENT_ENUM', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 'DSCC_DSC_VERSION_MAJOR_ENUM', + 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', + 'DSCC_DSC_VERSION_MINOR_ENUM', + 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', + 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', + 'DSCC_ENABLE_ENUM', 'DSCC_ENABLE_ENUM_DISABLED', + 'DSCC_ENABLE_ENUM_ENABLED', 'DSCC_ICH_RESET_ENUM', + 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', 'DSCC_LINEBUF_DEPTH_ENUM', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', + 'DSCC_MEM_PWR_DIS_ENUM', 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', + 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', 'DSCC_MEM_PWR_FORCE_ENUM', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', + 'DSCL_MODE_CHROMA_SCALING_BYPASS', 'DSCL_MODE_DSCL_BYPASS', + 'DSCL_MODE_LUMA_SCALING_BYPASS', 'DSCL_MODE_SCALING_444_BYPASS', + 'DSCL_MODE_SCALING_444_RGB_ENABLE', + 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', + 'DSCL_MODE_SCALING_YCBCR_ENABLE', 'DSCL_MODE_SEL', 'DSM_DATA_SEL', + 'DSM_DATA_SEL_0', 'DSM_DATA_SEL_1', 'DSM_DATA_SEL_BOTH', + 'DSM_DATA_SEL_DISABLE', 'DSM_ENABLE_ERROR_INJECT', + 'DSM_ENABLE_ERROR_INJECT_FED_IN', + 'DSM_ENABLE_ERROR_INJECT_SINGLE', + 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', + 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', + 'DSM_SELECT_INJECT_DELAY', 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', + 'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DSM_SINGLE_WRITE', + 'DSM_SINGLE_WRITE_DIS', 'DSM_SINGLE_WRITE_EN', 'DS_HW_CAL_DIS', + 'DS_HW_CAL_EN', 'DS_HW_CAL_ENABLE', 'DS_JITTER_COUNT_SRC_SEL', + 'DS_JITTER_COUNT_SRC_SEL0', 'DS_JITTER_COUNT_SRC_SEL1', + 'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', + 'DS_REF_SRC', 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_IN_PHASE', 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', + 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE', + 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', + 'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', + 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST', + 'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE', + 'DWB_DATA_DEPTH_WARMUP_10BPC', 'DWB_DATA_DEPTH_WARMUP_8BPC', + 'DWB_DATA_DEPTH_WARMUP_ENUM', 'DWB_GMC_WARM_UP_DISABLE', + 'DWB_GMC_WARM_UP_ENABLE', 'DWB_GMC_WARM_UP_ENABLE_ENUM', + 'DWB_MODE_WARMUP_420', 'DWB_MODE_WARMUP_444', + 'DWB_MODE_WARMUP_ENUM', 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE', + 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', + 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', + 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', + 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', + 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', + 'DbPRTFaultBehavior', 'DbPSLControl', 'DepthArray', 'DepthFormat', + 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', + 'EFC_ACrYCb16161616_10LSB', 'EFC_ACrYCb16161616_10MSB', + 'EFC_ACrYCb16161616_12LSB', 'EFC_ACrYCb16161616_12MSB', + 'EFC_ACrYCb2101010', 'EFC_ACrYCb8888', 'EFC_ARGB1555', + 'EFC_ARGB16161616_10LSB', 'EFC_ARGB16161616_10MSB', + 'EFC_ARGB16161616_12LSB', 'EFC_ARGB16161616_12MSB', + 'EFC_ARGB16161616_FLOAT', 'EFC_ARGB16161616_SNORM', + 'EFC_ARGB16161616_UNORM', 'EFC_ARGB2101010', 'EFC_ARGB4444', + 'EFC_ARGB8888', 'EFC_AYCrCb16161616_10LSB', + 'EFC_AYCrCb16161616_10MSB', 'EFC_AYCrCb16161616_12LSB', + 'EFC_AYCrCb16161616_12MSB', 'EFC_AYCrCb8888', 'EFC_BGR101111_FIX', + 'EFC_BGR101111_FLOAT', 'EFC_BGR565', + 'EFC_CbYCrY10101010_422_PACKED', 'EFC_CbYCrY12121212_422_PACKED', + 'EFC_CbYCrY8888_422_PACKED', 'EFC_CrYCbA1010102', + 'EFC_CrYCbA16161616_10LSB', 'EFC_CrYCbA16161616_10MSB', + 'EFC_CrYCbA16161616_12LSB', 'EFC_CrYCbA16161616_12MSB', + 'EFC_CrYCbA8888', 'EFC_CrYCbY10101010_422_PACKED', + 'EFC_CrYCbY12121212_422_PACKED', 'EFC_CrYCbY8888_422_PACKED', + 'EFC_MONO_10LSB', 'EFC_MONO_10MSB', 'EFC_MONO_12LSB', + 'EFC_MONO_12MSB', 'EFC_MONO_16', 'EFC_MONO_8', + 'EFC_RGB111110_FIX', 'EFC_RGB111110_FLOAT', 'EFC_RGB565', + 'EFC_RGBA1010102', 'EFC_RGBA16161616_10LSB', + 'EFC_RGBA16161616_10MSB', 'EFC_RGBA16161616_12LSB', + 'EFC_RGBA16161616_12MSB', 'EFC_RGBA16161616_FLOAT', + 'EFC_RGBA16161616_SNORM', 'EFC_RGBA16161616_UNORM', + 'EFC_RGBA4444', 'EFC_RGBA5551', 'EFC_RGBA8888', + 'EFC_SURFACE_PIXEL_FORMAT', 'EFC_Y10_CbCr1010_420_PLANAR', + 'EFC_Y10_CrCb1010_420_PLANAR', 'EFC_Y12_CbCr1212_420_PLANAR', + 'EFC_Y12_CrCb1212_420_PLANAR', 'EFC_Y8_CbCr88_420_PLANAR', + 'EFC_Y8_CrCb88_420_PLANAR', 'EFC_YCbYCr10101010_422_PACKED', + 'EFC_YCbYCr12121212_422_PACKED', 'EFC_YCbYCr8888_422_PACKED', + 'EFC_YCrCbA16161616_10LSB', 'EFC_YCrCbA16161616_10MSB', + 'EFC_YCrCbA16161616_12LSB', 'EFC_YCrCbA16161616_12MSB', + 'EFC_YCrCbA8888', 'EFC_YCrYCb10101010_422_PACKED', + 'EFC_YCrYCb12121212_422_PACKED', 'EFC_YCrYCb8888_422_PACKED', + 'EIGHT_BANKS', 'EIGHT_FRAGMENTS', 'EIGHT_PIPES', + 'EIGHT_SHADER_ENGINS', 'ENABLE', 'ENABLE_CLOCK', 'ENABLE_ENUM', + 'ENABLE_ENUM_DISABLED', 'ENABLE_ENUM_ENABLED', + 'ENABLE_JITTER_REMOVAL', 'ENABLE_LEGACY_PIPELINE', + 'ENABLE_MEM_PWR_CTRL', 'ENABLE_NGG_PIPELINE', 'ENABLE_THE_CLOCK', + 'ENABLE_THE_FEATURE', 'ENABLE_THE_INTERRUPT', 'ENDIAN_8IN16', + 'ENDIAN_8IN32', 'ENDIAN_8IN64', 'ENDIAN_NONE', + 'END_OF_PIPE_IB_END', 'END_OF_PIPE_INCR_DE', + 'ENGG_CSB_DELAY_BIN00', 'ENGG_CSB_DELAY_BIN01', + 'ENGG_CSB_DELAY_BIN02', 'ENGG_CSB_DELAY_BIN03', + 'ENGG_CSB_DELAY_BIN04', 'ENGG_CSB_DELAY_BIN05', + 'ENGG_CSB_DELAY_BIN06', 'ENGG_CSB_DELAY_BIN07', + 'ENGG_CSB_DELAY_BIN08', 'ENGG_CSB_DELAY_BIN09', + 'ENGG_CSB_DELAY_BIN10', 'ENGG_CSB_DELAY_BIN11', + 'ENGG_CSB_DELAY_BIN12', 'ENGG_CSB_DELAY_BIN13', + 'ENGG_CSB_DELAY_BIN14', 'ENGG_CSB_DELAY_BIN15', + 'ENGG_CSB_GE_INPUT_FIFO_FULL', 'ENGG_CSB_GE_SENDING_SUBGROUP', + 'ENGG_CSB_MACHINE_IS_STARVED', + 'ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', + 'ENGG_CSB_MACHINE_STALLED_BY_SPI', + 'ENGG_CSB_OBJECTID_INPUT_FIFO_FULL', 'ENGG_CSB_PRIM_COUNT_EQ0', + 'ENGG_CSB_SPI_DELAY_BIN00', 'ENGG_CSB_SPI_DELAY_BIN01', + 'ENGG_CSB_SPI_DELAY_BIN02', 'ENGG_CSB_SPI_DELAY_BIN03', + 'ENGG_CSB_SPI_DELAY_BIN04', 'ENGG_CSB_SPI_DELAY_BIN05', + 'ENGG_CSB_SPI_DELAY_BIN06', 'ENGG_CSB_SPI_DELAY_BIN07', + 'ENGG_CSB_SPI_DELAY_BIN08', 'ENGG_CSB_SPI_DELAY_BIN09', + 'ENGG_CSB_SPI_DELAY_BIN10', 'ENGG_CSB_SPI_DELAY_BIN11', + 'ENGG_CSB_SPI_DELAY_BIN12', 'ENGG_CSB_SPI_DELAY_BIN13', + 'ENGG_CSB_SPI_DELAY_BIN14', 'ENGG_CSB_SPI_DELAY_BIN15', + 'ENGG_CSB_SPI_INPUT_FIFO_FULL', + 'ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', + 'ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', + 'ENGG_INDEX_PRIM_IF_QUALIFIED_BUSY', + 'ENGG_INDEX_PRIM_IF_QUALIFIED_STARVED', + 'ENGG_INDEX_PRIM_IF_REUSE_0_NEW_VERTS_THIS_PRIM', + 'ENGG_INDEX_PRIM_IF_REUSE_1_NEW_VERTS_THIS_PRIM', + 'ENGG_INDEX_PRIM_IF_REUSE_2_NEW_VERTS_THIS_PRIM', + 'ENGG_INDEX_PRIM_IF_REUSE_3_NEW_VERTS_THIS_PRIM', + 'ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', + 'ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', + 'ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', + 'ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 'ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 'ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', 'ENGG_INDEX_REQ_STARVED', + 'ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', + 'ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', + 'ENGG_INDEX_RET_SXRX_READING_EVENT', + 'ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', + 'ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', + 'ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', + 'ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', + 'ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', + 'ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS', + 'ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS', + 'ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS', + 'ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', + 'ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', + 'ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', + 'ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', + 'ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', + 'ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', + 'ENGG_POS_REQ_STALLED_BY_FULL_CLIPV_FIFO', 'ENGG_POS_REQ_STARVED', + 'ENUMS_GDS_PERFCOUNT_SELECT_H', 'ENUM_DPG_BIT_DEPTH', + 'ENUM_DPG_BIT_DEPTH_10BPC', 'ENUM_DPG_BIT_DEPTH_12BPC', + 'ENUM_DPG_BIT_DEPTH_6BPC', 'ENUM_DPG_BIT_DEPTH_8BPC', + 'ENUM_DPG_DISABLE', 'ENUM_DPG_DYNAMIC_RANGE', + 'ENUM_DPG_DYNAMIC_RANGE_CEA', 'ENUM_DPG_DYNAMIC_RANGE_VESA', + 'ENUM_DPG_EN', 'ENUM_DPG_ENABLE', 'ENUM_DPG_FIELD_POLARITY', + 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', + 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', 'ENUM_DPG_MODE', + 'ENUM_DPG_MODE_HORIZONTAL_BAR', 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', + 'ENUM_DPG_MODE_RGB_DUAL_RAMP', 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', + 'ENUM_DPG_MODE_RGB_XR_BIAS', 'ENUM_DPG_MODE_VERTICAL_BAR', + 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', + 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', + 'ENUM_FMT_PTI_FIELD_POLARITY', + 'ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', + 'ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', + 'ENUM_NUM_SIMD_PER_CU', 'ES_STAGE_DS', 'ES_STAGE_OFF', + 'ES_STAGE_REAL', 'EXPORT_16_16_FLOAT_8PIX', + 'EXPORT_16_16_SIGNED_8PIX', 'EXPORT_16_16_UNSIGNED_8PIX', + 'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR', + 'EXPORT_2P_32BPC_ABGR', 'EXPORT_32BPP_8PIX', 'EXPORT_32_ABGR', + 'EXPORT_32_AR', 'EXPORT_32_GR', 'EXPORT_32_R', 'EXPORT_4C_16BPC', + 'EXPORT_4C_32BPC', 'EXPORT_4P_16BPC_ABGR', 'EXPORT_4P_32BPC_ABGR', + 'EXPORT_4P_32BPC_AR', 'EXPORT_4P_32BPC_GR', 'EXPORT_8P_32BPC_R', + 'EXPORT_ANY_Z', 'EXPORT_FP16_ABGR', 'EXPORT_GREATER_THAN_Z', + 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'EXPORT_SIGNED16_ABGR', + 'EXPORT_UNSIGNED16_ABGR', 'EXPORT_UNUSED', 'FAULT_FAIL', + 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', 'FEC_ACTIVE_STATUS', + 'FIX_S2_13', 'FIX_S3_12', 'FLIP_ANY_FRAME', 'FLIP_LEFT_EYE', + 'FLIP_RATE', 'FLIP_RATE_0', 'FLIP_RATE_1', 'FLIP_RATE_2', + 'FLIP_RATE_3', 'FLIP_RATE_4', 'FLIP_RATE_5', 'FLIP_RATE_6', + 'FLIP_RATE_7', 'FLIP_RIGHT_EYE', 'FLUSH_AND_INV_CB_DATA_TS', + 'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA', + 'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META', + 'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED', + 'FLUSH_DFSM', 'FLUSH_ES_OUTPUT', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', + 'FMTMEM_DISABLE_MEM_PWR_CTRL', 'FMTMEM_ENABLE_MEM_PWR_CTRL', + 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', + 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', + 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', 'FMTMEM_NO_FORCE_REQUEST', + 'FMTMEM_PWR_DIS_CTRL', 'FMTMEM_PWR_FORCE_CTRL', 'FMT_1', + 'FMT_10_10_10_2', 'FMT_10_11_11', 'FMT_10_11_11_FLOAT', + 'FMT_11_11_10', 'FMT_11_11_10_FLOAT', 'FMT_16', 'FMT_16_16', + 'FMT_16_16_16', 'FMT_16_16_16_16', 'FMT_16_16_16_16_FLOAT', + 'FMT_16_16_16_FLOAT', 'FMT_16_16_FLOAT', 'FMT_16_FLOAT', + 'FMT_1_5_5_5', 'FMT_1_REVERSED', 'FMT_24_8', 'FMT_24_8_FLOAT', + 'FMT_2_10_10_10', 'FMT_32', 'FMT_32_32', 'FMT_32_32_32', + 'FMT_32_32_32_32', 'FMT_32_32_32_32_FLOAT', 'FMT_32_32_32_FLOAT', + 'FMT_32_32_FLOAT', 'FMT_32_AS_32_32_32_32', 'FMT_32_AS_8', + 'FMT_32_AS_8_8', 'FMT_32_FLOAT', 'FMT_3_3_2', 'FMT_4_4', + 'FMT_4_4_4_4', 'FMT_5_5_5_1', 'FMT_5_6_5', + 'FMT_5_9_9_9_SHAREDEXP', 'FMT_6_5_5', 'FMT_8', 'FMT_8_24', + 'FMT_8_24_FLOAT', 'FMT_8_8', 'FMT_8_8_8', 'FMT_8_8_8_8', + 'FMT_APC3', 'FMT_APC4', 'FMT_APC5', 'FMT_APC6', 'FMT_APC7', + 'FMT_BC1', 'FMT_BC2', 'FMT_BC3', 'FMT_BC4', 'FMT_BC5', 'FMT_BC6', + 'FMT_BC7', 'FMT_BG_RG', 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 'FMT_CLAMP_CNTL_COLOR_FORMAT', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', + 'FMT_CONTROL_PIXEL_ENCODING', + 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', + 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 'FMT_CONTROL_SUBSAMPLING_MODE', + 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', + 'FMT_CONTROL_SUBSAMPLING_ORDER', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', 'FMT_CTX1', + 'FMT_DYNAMIC_EXP_MODE', 'FMT_DYNAMIC_EXP_MODE_10to12', + 'FMT_DYNAMIC_EXP_MODE_8to12', 'FMT_FRAME_RANDOM_ENABLE_CONTROL', + 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', + 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', 'FMT_GB_GR', 'FMT_INVALID', + 'FMT_POWER_STATE_ENUM', 'FMT_POWER_STATE_ENUM_DS', + 'FMT_POWER_STATE_ENUM_LS', 'FMT_POWER_STATE_ENUM_ON', + 'FMT_POWER_STATE_ENUM_SD', 'FMT_RESERVED_33', 'FMT_RESERVED_36', + 'FMT_RESERVED_4', 'FMT_RESERVED_63', + 'FMT_RGB_RANDOM_ENABLE_CONTROL', + 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', + 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', + 'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0', + 'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2', + 'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVERRIDE_CONTROL', + 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', + 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', + 'FMT_X24_8_32_FLOAT', 'FORCE_00', 'FORCE_BINNING_ON', + 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', 'FORCE_EARLY_Z', + 'FORCE_ENABLE', 'FORCE_FF', 'FORCE_LATE_Z', + 'FORCE_LIGHT_SLEEP_REQ', 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', + 'FORCE_OPT_AUTO', 'FORCE_OPT_DISABLE', + 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', + 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', + 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', + 'FOUR_BANKS', 'FOUR_FRAGMENTS', 'FOUR_PIPES', 'FOUR_RB_PER_SE', + 'FOUR_SHADER_ENGINS', 'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL', + 'FRAG_GREATER', 'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER', + 'FRAG_NOTEQUAL', 'FULL_TILE_WAVE_BREAK_BC_ONLY', + 'FULL_TILE_WAVE_BREAK_BOTH', 'FULL_TILE_WAVE_BREAK_NBC_ONLY', + 'FULL_TILE_WAVE_BREAK_NONE', 'ForceControl', 'FullTileWaveBreak', + 'GAMUT_COEF', 'GAMUT_COEF_B', 'GATCL1RequestType', + 'GATCL1_TYPE_BYPASS', 'GATCL1_TYPE_NORMAL', + 'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE', + 'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT', + 'GB_EDC_DED_MODE_LOG', 'GCRPerfSel', 'GCR_PERF_SEL_ALL_REQ', + 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CPC_ALL_REQ', 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPC_METADATA_REQ', + 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', 'GCR_PERF_SEL_CPC_SQC_INST_REQ', + 'GCR_PERF_SEL_CPC_TCP_REQ', + 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_CPF_ALL_REQ', 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPF_METADATA_REQ', + 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', 'GCR_PERF_SEL_CPF_SQC_INST_REQ', + 'GCR_PERF_SEL_CPF_TCP_REQ', + 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_CPG_ALL_REQ', 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPG_METADATA_REQ', + 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', 'GCR_PERF_SEL_CPG_SQC_INST_REQ', + 'GCR_PERF_SEL_CPG_TCP_REQ', + 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', 'GCR_PERF_SEL_NONE', + 'GCR_PERF_SEL_PHY_REQ', 'GCR_PERF_SEL_SDMA0_ALL_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', + 'GCR_PERF_SEL_SDMA0_METADATA_REQ', + 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', + 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA0_TCP_REQ', + 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_SDMA1_ALL_REQ', 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', + 'GCR_PERF_SEL_SDMA1_METADATA_REQ', + 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', + 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA1_TCP_REQ', + 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', + 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', + 'GCR_PERF_SEL_UTCL2_FILTERED_RET', + 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', + 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', + 'GCR_PERF_SEL_UTCL2_REQ', 'GCR_PERF_SEL_UTCL2_RET', + 'GCR_PERF_SEL_VIRT_REQ', 'GDS_PERFCOUNT_SELECT', + 'GDS_PERF_SEL_DS_ADDR_CONFL', 'GDS_PERF_SEL_DS_BANK_CONFL', + 'GDS_PERF_SEL_GWS_BYPASS', 'GDS_PERF_SEL_GWS_RELEASED', + 'GDS_PERF_SEL_RBUF_HIT', 'GDS_PERF_SEL_RBUF_MISS', + 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ', + 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH0_NORET', + 'GDS_PERF_SEL_SE0_SH0_ORD_CNT', + 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH0_RET', + 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ', + 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH1_NORET', + 'GDS_PERF_SEL_SE0_SH1_ORD_CNT', + 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH1_RET', + 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ', + 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH0_NORET', + 'GDS_PERF_SEL_SE1_SH0_ORD_CNT', + 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH0_RET', + 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ', + 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH1_NORET', + 'GDS_PERF_SEL_SE1_SH1_ORD_CNT', + 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH1_RET', + 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ', + 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH0_NORET', + 'GDS_PERF_SEL_SE2_SH0_ORD_CNT', + 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH0_RET', + 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ', + 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH1_NORET', + 'GDS_PERF_SEL_SE2_SH1_ORD_CNT', + 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH1_RET', + 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ', + 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH0_NORET', + 'GDS_PERF_SEL_SE3_SH0_ORD_CNT', + 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH0_RET', + 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ', + 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH1_NORET', + 'GDS_PERF_SEL_SE3_SH1_ORD_CNT', + 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH1_RET', + 'GDS_PERF_SEL_WBUF_FLUSH', 'GDS_PERF_SEL_WBUF_WR', + 'GDS_PERF_SEL_WR_COMP', 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', + 'GENERIC_STEREOSYNC_SEL', 'GENERIC_STEREOSYNC_SEL_D1', + 'GENERIC_STEREOSYNC_SEL_D2', 'GENERIC_STEREOSYNC_SEL_D3', + 'GENERIC_STEREOSYNC_SEL_D4', 'GENERIC_STEREOSYNC_SEL_D5', + 'GENERIC_STEREOSYNC_SEL_D6', 'GENERIC_STEREOSYNC_SEL_RESERVED', + 'GE_PERFCOUNT_SELECT', 'GL0V_CACHE_POLICIES', + 'GL0V_CACHE_POLICY_HIT_EVICT', 'GL0V_CACHE_POLICY_HIT_LRU', + 'GL0V_CACHE_POLICY_MISS_EVICT', 'GL0V_CACHE_POLICY_MISS_LRU', + 'GL1A_PERF_SEL', 'GL1A_PERF_SEL_ARB_REQUESTS', + 'GL1A_PERF_SEL_BUSY', 'GL1A_PERF_SEL_CYCLE', + 'GL1A_PERF_SEL_IO_32B_WDS_GL1C0', + 'GL1A_PERF_SEL_IO_32B_WDS_GL1C1', + 'GL1A_PERF_SEL_IO_32B_WDS_GL1C2', + 'GL1A_PERF_SEL_IO_32B_WDS_GL1C3', + 'GL1A_PERF_SEL_IO_32B_WDS_GL1C4', + 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0', + 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1', + 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2', + 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3', + 'GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4', + 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C0', + 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C1', + 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C2', + 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C3', + 'GL1A_PERF_SEL_MEM_32B_WDS_GL1C4', + 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0', + 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1', + 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2', + 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3', + 'GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4', + 'GL1A_PERF_SEL_REQUEST_GL1C0', 'GL1A_PERF_SEL_REQUEST_GL1C1', + 'GL1A_PERF_SEL_REQUEST_GL1C2', 'GL1A_PERF_SEL_REQUEST_GL1C3', + 'GL1A_PERF_SEL_REQUEST_GL1C4', 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', + 'GL1A_PERF_SEL_STALL_GL1C0', 'GL1A_PERF_SEL_STALL_GL1C1', + 'GL1A_PERF_SEL_STALL_GL1C2', 'GL1A_PERF_SEL_STALL_GL1C3', + 'GL1A_PERF_SEL_STALL_GL1C4', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4', 'GL1CG_PERF_SEL', + 'GL1CG_PERF_SEL_CORE_REG_SCLK_VLD', 'GL1CG_PERF_SEL_CYCLE', + 'GL1CG_PERF_SEL_GATE_EN1', 'GL1CG_PERF_SEL_GATE_EN2', + 'GL1CG_PERF_SEL_REQ', 'GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES', + 'GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES', 'GL1C_PERF_SEL', + 'GL1C_PERF_SEL_CORE_REG_SCLK_VLD', 'GL1C_PERF_SEL_CYCLE', + 'GL1C_PERF_SEL_GATE_EN1', 'GL1C_PERF_SEL_GATE_EN2', + 'GL1C_PERF_SEL_REQ', 'GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES', + 'GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES', 'GL1_CACHE_POLICIES', + 'GL1_CACHE_POLICY_HIT_EVICT', 'GL1_CACHE_POLICY_HIT_LRU', + 'GL1_CACHE_POLICY_MISS_EVICT', 'GL1_CACHE_POLICY_MISS_LRU', + 'GL1_CACHE_STORE_POLICIES', 'GL1_CACHE_STORE_POLICY_BYPASS', + 'GL2A_PERF_SEL', 'GL2A_PERF_SEL_BUSY', 'GL2A_PERF_SEL_CYCLE', + 'GL2A_PERF_SEL_NONE', 'GL2A_PERF_SEL_REQ_BURST_GL2C0', + 'GL2A_PERF_SEL_REQ_BURST_GL2C1', 'GL2A_PERF_SEL_REQ_BURST_GL2C2', + 'GL2A_PERF_SEL_REQ_BURST_GL2C3', 'GL2A_PERF_SEL_REQ_BURST_GL2C4', + 'GL2A_PERF_SEL_REQ_BURST_GL2C5', 'GL2A_PERF_SEL_REQ_BURST_GL2C6', + 'GL2A_PERF_SEL_REQ_BURST_GL2C7', 'GL2A_PERF_SEL_REQ_GL2C0', + 'GL2A_PERF_SEL_REQ_GL2C1', 'GL2A_PERF_SEL_REQ_GL2C2', + 'GL2A_PERF_SEL_REQ_GL2C3', 'GL2A_PERF_SEL_REQ_GL2C4', + 'GL2A_PERF_SEL_REQ_GL2C5', 'GL2A_PERF_SEL_REQ_GL2C6', + 'GL2A_PERF_SEL_REQ_GL2C7', 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', + 'GL2A_PERF_SEL_REQ_STALL_GL2C0', 'GL2A_PERF_SEL_REQ_STALL_GL2C1', + 'GL2A_PERF_SEL_REQ_STALL_GL2C2', 'GL2A_PERF_SEL_REQ_STALL_GL2C3', + 'GL2A_PERF_SEL_REQ_STALL_GL2C4', 'GL2A_PERF_SEL_REQ_STALL_GL2C5', + 'GL2A_PERF_SEL_REQ_STALL_GL2C6', 'GL2A_PERF_SEL_REQ_STALL_GL2C7', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', + 'GL2A_PERF_SEL_RTN_CLIENT0', 'GL2A_PERF_SEL_RTN_CLIENT1', + 'GL2A_PERF_SEL_RTN_CLIENT2', 'GL2A_PERF_SEL_RTN_CLIENT3', + 'GL2A_PERF_SEL_RTN_CLIENT4', 'GL2A_PERF_SEL_RTN_CLIENT5', + 'GL2A_PERF_SEL_RTN_CLIENT6', 'GL2A_PERF_SEL_RTN_CLIENT7', + 'GL2A_PERF_SEL_RTN_STALL_GL2C0', 'GL2A_PERF_SEL_RTN_STALL_GL2C1', + 'GL2A_PERF_SEL_RTN_STALL_GL2C2', 'GL2A_PERF_SEL_RTN_STALL_GL2C3', + 'GL2A_PERF_SEL_RTN_STALL_GL2C4', 'GL2A_PERF_SEL_RTN_STALL_GL2C5', + 'GL2A_PERF_SEL_RTN_STALL_GL2C6', 'GL2A_PERF_SEL_RTN_STALL_GL2C7', + 'GL2C_PERF_SEL', 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', + 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', + 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', + 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', + 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', + 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', + 'GL2C_PERF_SEL_ATOMIC', 'GL2C_PERF_SEL_BUBBLE', + 'GL2C_PERF_SEL_BUSY', 'GL2C_PERF_SEL_BYPASS_REQ', + 'GL2C_PERF_SEL_CLIENT0_REQ', 'GL2C_PERF_SEL_CLIENT1_REQ', + 'GL2C_PERF_SEL_CLIENT2_REQ', 'GL2C_PERF_SEL_CLIENT3_REQ', + 'GL2C_PERF_SEL_CLIENT4_REQ', 'GL2C_PERF_SEL_CLIENT5_REQ', + 'GL2C_PERF_SEL_CLIENT6_REQ', 'GL2C_PERF_SEL_CLIENT7_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', + 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', + 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', + 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', + 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', + 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', + 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', + 'GL2C_PERF_SEL_CM_COMP_READ_REQ', + 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', + 'GL2C_PERF_SEL_CM_DCC_STALL', 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', + 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', + 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', 'GL2C_PERF_SEL_CM_NOOP_REQ', + 'GL2C_PERF_SEL_CM_NO_ACK_REQ', 'GL2C_PERF_SEL_CM_READ_BACK_REQ', + 'GL2C_PERF_SEL_CM_RVF_FULL', 'GL2C_PERF_SEL_CM_SDR_FULL', + 'GL2C_PERF_SEL_CM_WR_ACK_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', 'GL2C_PERF_SEL_CYCLE', + 'GL2C_PERF_SEL_C_RO_S_REQ', 'GL2C_PERF_SEL_C_RO_US_REQ', + 'GL2C_PERF_SEL_C_RW_S_REQ', 'GL2C_PERF_SEL_C_RW_US_REQ', + 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'GL2C_PERF_SEL_EA_ATOMIC', + 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', 'GL2C_PERF_SEL_EA_RDREQ_128B', + 'GL2C_PERF_SEL_EA_RDREQ_32B', 'GL2C_PERF_SEL_EA_RDREQ_64B', + 'GL2C_PERF_SEL_EA_RDREQ_96B', 'GL2C_PERF_SEL_EA_RDREQ_DRAM', + 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', + 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', 'GL2C_PERF_SEL_EA_RDRET_NACK', + 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', + 'GL2C_PERF_SEL_EA_RD_MDC_32B', 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', + 'GL2C_PERF_SEL_EA_WRREQ_64B', 'GL2C_PERF_SEL_EA_WRREQ_DRAM', + 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', + 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', + 'GL2C_PERF_SEL_EA_WRRET_NACK', 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', + 'GL2C_PERF_SEL_EVICT', 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', + 'GL2C_PERF_SEL_FULL_HIT', 'GL2C_PERF_SEL_GARLIC_READ', + 'GL2C_PERF_SEL_GARLIC_WRITE', 'GL2C_PERF_SEL_GCR_ALL', + 'GL2C_PERF_SEL_GCR_DISCARD', 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', + 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', + 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', + 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', 'GL2C_PERF_SEL_GCR_INV', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', 'GL2C_PERF_SEL_GCR_MDC_INV', + 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', + 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', 'GL2C_PERF_SEL_GCR_RANGE', + 'GL2C_PERF_SEL_GCR_UNSHARED', 'GL2C_PERF_SEL_GCR_VOL', + 'GL2C_PERF_SEL_GCR_WB', 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', + 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', + 'GL2C_PERF_SEL_GCR_WBINVL2_START', + 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', + 'GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT', + 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', 'GL2C_PERF_SEL_GL2A_LEVEL', + 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', 'GL2C_PERF_SEL_HIT', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO', + 'GL2C_PERF_SEL_IB_CM_STALL', 'GL2C_PERF_SEL_IB_REQ', + 'GL2C_PERF_SEL_IB_STALL', 'GL2C_PERF_SEL_IB_TAG_STALL', + 'GL2C_PERF_SEL_INTERNAL_PROBE', 'GL2C_PERF_SEL_IO_READ', + 'GL2C_PERF_SEL_IO_WRITE', 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', + 'GL2C_PERF_SEL_LRU_REQ', 'GL2C_PERF_SEL_MC_RDREQ', + 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ', + 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ_STALL', + 'GL2C_PERF_SEL_MDC_INV_METADATA', 'GL2C_PERF_SEL_MDC_LEVEL', + 'GL2C_PERF_SEL_MDC_REQ', 'GL2C_PERF_SEL_MDC_SECTOR_HIT', + 'GL2C_PERF_SEL_MDC_SECTOR_MISS', + 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_MDC_TAG_HIT', + 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', + 'GL2C_PERF_SEL_MDC_TAG_STALL', + 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', + 'GL2C_PERF_SEL_METADATA_READ_REQ', 'GL2C_PERF_SEL_MISS', + 'GL2C_PERF_SEL_NOA_REQ', 'GL2C_PERF_SEL_NONE', + 'GL2C_PERF_SEL_NOP_ACK', 'GL2C_PERF_SEL_NOP_RTN0', + 'GL2C_PERF_SEL_NORMAL_EVICT', 'GL2C_PERF_SEL_NORMAL_WRITEBACK', + 'GL2C_PERF_SEL_ONION_READ', 'GL2C_PERF_SEL_ONION_WRITE', + 'GL2C_PERF_SEL_PARTIAL_32B_HIT', 'GL2C_PERF_SEL_PARTIAL_64B_HIT', + 'GL2C_PERF_SEL_PARTIAL_96B_HIT', 'GL2C_PERF_SEL_PROBE', + 'GL2C_PERF_SEL_PROBE_ALL', 'GL2C_PERF_SEL_PROBE_EVICT', + 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', + 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', + 'GL2C_PERF_SEL_READ', 'GL2C_PERF_SEL_READ_128_REQ', + 'GL2C_PERF_SEL_READ_32_REQ', 'GL2C_PERF_SEL_READ_64_REQ', + 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', 'GL2C_PERF_SEL_REQ', + 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', 'GL2C_PERF_SEL_RETURN_ACK', + 'GL2C_PERF_SEL_RETURN_DATA', 'GL2C_PERF_SEL_SHARED_REQ', + 'GL2C_PERF_SEL_SRC_FIFO_FULL', 'GL2C_PERF_SEL_STREAM_REQ', + 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', + 'GL2C_PERF_SEL_TAG_PROBE_STALL', + 'GL2C_PERF_SEL_TAG_READ_DST_STALL', 'GL2C_PERF_SEL_TAG_STALL', + 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'GL2C_PERF_SEL_UC_REQ', + 'GL2C_PERF_SEL_UNCACHED_WRITE', 'GL2C_PERF_SEL_VOL_REQ', + 'GL2C_PERF_SEL_WRITE', 'GL2C_PERF_SEL_WRITEBACK', + 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 'GL2C_PERF_SEL_WRITE_32_REQ', 'GL2C_PERF_SEL_WRITE_64_REQ', + 'GL2_CACHE_POLICIES', 'GL2_CACHE_POLICY_BYPASS', + 'GL2_CACHE_POLICY_LRU', 'GL2_CACHE_POLICY_NOA', + 'GL2_CACHE_POLICY_STREAM', 'GL2_EA_CID', 'GL2_EA_CID_CLIENT', + 'GL2_EA_CID_CP', 'GL2_EA_CID_CPDMA', 'GL2_EA_CID_DCC', + 'GL2_EA_CID_FMASK', 'GL2_EA_CID_HTILE', 'GL2_EA_CID_RLC', + 'GL2_EA_CID_RT', 'GL2_EA_CID_SDMA', 'GL2_EA_CID_TCPMETA', + 'GL2_EA_CID_UTCL2', 'GL2_EA_CID_ZPCPSD', 'GL2_EA_CID_Z_STENCIL', + 'GL2_NACKS', 'GL2_NACK_DATA_ERROR', 'GL2_NACK_NO_FAULT', + 'GL2_NACK_PAGE_FAULT', 'GL2_NACK_PROTECTION_FAULT', 'GL2_OP', + 'GL2_OP_ATOMIC_ADD_32', 'GL2_OP_ATOMIC_ADD_64', + 'GL2_OP_ATOMIC_ADD_RTN_32', 'GL2_OP_ATOMIC_ADD_RTN_64', + 'GL2_OP_ATOMIC_AND_32', 'GL2_OP_ATOMIC_AND_64', + 'GL2_OP_ATOMIC_AND_RTN_32', 'GL2_OP_ATOMIC_AND_RTN_64', + 'GL2_OP_ATOMIC_CMPSWAP_32', 'GL2_OP_ATOMIC_CMPSWAP_64', + 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', + 'GL2_OP_ATOMIC_DEC_32', 'GL2_OP_ATOMIC_DEC_64', + 'GL2_OP_ATOMIC_DEC_RTN_32', 'GL2_OP_ATOMIC_DEC_RTN_64', + 'GL2_OP_ATOMIC_FCMPSWAP_32', 'GL2_OP_ATOMIC_FCMPSWAP_64', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', + 'GL2_OP_ATOMIC_FMAX_32', 'GL2_OP_ATOMIC_FMAX_64', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FMAX_RTN_32', 'GL2_OP_ATOMIC_FMAX_RTN_64', + 'GL2_OP_ATOMIC_FMIN_32', 'GL2_OP_ATOMIC_FMIN_64', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FMIN_RTN_32', 'GL2_OP_ATOMIC_FMIN_RTN_64', + 'GL2_OP_ATOMIC_INC_32', 'GL2_OP_ATOMIC_INC_64', + 'GL2_OP_ATOMIC_INC_RTN_32', 'GL2_OP_ATOMIC_INC_RTN_64', + 'GL2_OP_ATOMIC_OR_32', 'GL2_OP_ATOMIC_OR_64', + 'GL2_OP_ATOMIC_OR_RTN_32', 'GL2_OP_ATOMIC_OR_RTN_64', + 'GL2_OP_ATOMIC_SMAX_32', 'GL2_OP_ATOMIC_SMAX_64', + 'GL2_OP_ATOMIC_SMAX_RTN_32', 'GL2_OP_ATOMIC_SMAX_RTN_64', + 'GL2_OP_ATOMIC_SMIN_32', 'GL2_OP_ATOMIC_SMIN_64', + 'GL2_OP_ATOMIC_SMIN_RTN_32', 'GL2_OP_ATOMIC_SMIN_RTN_64', + 'GL2_OP_ATOMIC_SUB_32', 'GL2_OP_ATOMIC_SUB_64', + 'GL2_OP_ATOMIC_SUB_RTN_32', 'GL2_OP_ATOMIC_SUB_RTN_64', + 'GL2_OP_ATOMIC_SWAP_32', 'GL2_OP_ATOMIC_SWAP_64', + 'GL2_OP_ATOMIC_SWAP_RTN_32', 'GL2_OP_ATOMIC_SWAP_RTN_64', + 'GL2_OP_ATOMIC_UMAX_32', 'GL2_OP_ATOMIC_UMAX_64', + 'GL2_OP_ATOMIC_UMAX_RTN_32', 'GL2_OP_ATOMIC_UMAX_RTN_64', + 'GL2_OP_ATOMIC_UMIN_32', 'GL2_OP_ATOMIC_UMIN_64', + 'GL2_OP_ATOMIC_UMIN_RTN_32', 'GL2_OP_ATOMIC_UMIN_RTN_64', + 'GL2_OP_ATOMIC_XOR_32', 'GL2_OP_ATOMIC_XOR_64', + 'GL2_OP_ATOMIC_XOR_RTN_32', 'GL2_OP_ATOMIC_XOR_RTN_64', + 'GL2_OP_GL1_INV', 'GL2_OP_MASKS', 'GL2_OP_MASK_64', + 'GL2_OP_MASK_FLUSH_DENROM', 'GL2_OP_MASK_NO_RTN', + 'GL2_OP_NOP_ACK', 'GL2_OP_NOP_RTN0', 'GL2_OP_PROBE_FILTER', + 'GL2_OP_READ', 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', + 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', 'GL2_OP_WRITE', + 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', + 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', + 'GLOBAL_STATUS_FLUSH_STATUS', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', + 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', + 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', + 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', + 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', + 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', + 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_BCI_BUSY', + 'GRBM_PERF_SEL_CB_BUSY', 'GRBM_PERF_SEL_CB_CLEAN', + 'GRBM_PERF_SEL_CH_BUSY', 'GRBM_PERF_SEL_COUNT', + 'GRBM_PERF_SEL_CPAXI_BUSY', 'GRBM_PERF_SEL_CPC_BUSY', + 'GRBM_PERF_SEL_CPF_BUSY', 'GRBM_PERF_SEL_CPG_BUSY', + 'GRBM_PERF_SEL_CP_BUSY', 'GRBM_PERF_SEL_CP_COHER_BUSY', + 'GRBM_PERF_SEL_CP_DMA_BUSY', 'GRBM_PERF_SEL_DB_BUSY', + 'GRBM_PERF_SEL_DB_CLEAN', 'GRBM_PERF_SEL_EA_BUSY', + 'GRBM_PERF_SEL_GDS_BUSY', 'GRBM_PERF_SEL_GE_BUSY', + 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', 'GRBM_PERF_SEL_GL1CC_BUSY', + 'GRBM_PERF_SEL_GL2CC_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE', + 'GRBM_PERF_SEL_GUS_BUSY', 'GRBM_PERF_SEL_PA_BUSY', + 'GRBM_PERF_SEL_PH_BUSY', 'GRBM_PERF_SEL_PMM_BUSY', + 'GRBM_PERF_SEL_RESERVED_0', 'GRBM_PERF_SEL_RESERVED_1', + 'GRBM_PERF_SEL_RESERVED_2', 'GRBM_PERF_SEL_RESERVED_3', + 'GRBM_PERF_SEL_RESERVED_4', 'GRBM_PERF_SEL_RESERVED_5', + 'GRBM_PERF_SEL_RESERVED_6', 'GRBM_PERF_SEL_RESERVED_7', + 'GRBM_PERF_SEL_RESERVED_8', 'GRBM_PERF_SEL_RESERVED_9', + 'GRBM_PERF_SEL_RLC_BUSY', 'GRBM_PERF_SEL_RMI_BUSY', + 'GRBM_PERF_SEL_SC_BUSY', 'GRBM_PERF_SEL_SDMA_BUSY', + 'GRBM_PERF_SEL_SPI_BUSY', 'GRBM_PERF_SEL_SX_BUSY', + 'GRBM_PERF_SEL_TA_BUSY', 'GRBM_PERF_SEL_TCP_BUSY', + 'GRBM_PERF_SEL_USER_DEFINED', 'GRBM_PERF_SEL_UTCL1_BUSY', + 'GRBM_PERF_SEL_UTCL2_BUSY', 'GRBM_SE0_PERF_SEL', + 'GRBM_SE0_PERF_SEL_BCI_BUSY', 'GRBM_SE0_PERF_SEL_CB_BUSY', + 'GRBM_SE0_PERF_SEL_CB_CLEAN', 'GRBM_SE0_PERF_SEL_COUNT', + 'GRBM_SE0_PERF_SEL_DB_BUSY', 'GRBM_SE0_PERF_SEL_DB_CLEAN', + 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', 'GRBM_SE0_PERF_SEL_PA_BUSY', + 'GRBM_SE0_PERF_SEL_RESERVED_0', 'GRBM_SE0_PERF_SEL_RESERVED_1', + 'GRBM_SE0_PERF_SEL_RESERVED_2', 'GRBM_SE0_PERF_SEL_RMI_BUSY', + 'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY', + 'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY', + 'GRBM_SE0_PERF_SEL_TCP_BUSY', 'GRBM_SE0_PERF_SEL_USER_DEFINED', + 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', 'GRBM_SE1_PERF_SEL', + 'GRBM_SE1_PERF_SEL_BCI_BUSY', 'GRBM_SE1_PERF_SEL_CB_BUSY', + 'GRBM_SE1_PERF_SEL_CB_CLEAN', 'GRBM_SE1_PERF_SEL_COUNT', + 'GRBM_SE1_PERF_SEL_DB_BUSY', 'GRBM_SE1_PERF_SEL_DB_CLEAN', + 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', 'GRBM_SE1_PERF_SEL_PA_BUSY', + 'GRBM_SE1_PERF_SEL_RESERVED_0', 'GRBM_SE1_PERF_SEL_RESERVED_1', + 'GRBM_SE1_PERF_SEL_RESERVED_2', 'GRBM_SE1_PERF_SEL_RMI_BUSY', + 'GRBM_SE1_PERF_SEL_SC_BUSY', 'GRBM_SE1_PERF_SEL_SPI_BUSY', + 'GRBM_SE1_PERF_SEL_SX_BUSY', 'GRBM_SE1_PERF_SEL_TA_BUSY', + 'GRBM_SE1_PERF_SEL_TCP_BUSY', 'GRBM_SE1_PERF_SEL_USER_DEFINED', + 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', 'GRBM_SE2_PERF_SEL', + 'GRBM_SE2_PERF_SEL_BCI_BUSY', 'GRBM_SE2_PERF_SEL_CB_BUSY', + 'GRBM_SE2_PERF_SEL_CB_CLEAN', 'GRBM_SE2_PERF_SEL_COUNT', + 'GRBM_SE2_PERF_SEL_DB_BUSY', 'GRBM_SE2_PERF_SEL_DB_CLEAN', + 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', 'GRBM_SE2_PERF_SEL_PA_BUSY', + 'GRBM_SE2_PERF_SEL_RESERVED_0', 'GRBM_SE2_PERF_SEL_RESERVED_1', + 'GRBM_SE2_PERF_SEL_RESERVED_2', 'GRBM_SE2_PERF_SEL_RMI_BUSY', + 'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY', + 'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY', + 'GRBM_SE2_PERF_SEL_TCP_BUSY', 'GRBM_SE2_PERF_SEL_USER_DEFINED', + 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', 'GRBM_SE3_PERF_SEL', + 'GRBM_SE3_PERF_SEL_BCI_BUSY', 'GRBM_SE3_PERF_SEL_CB_BUSY', + 'GRBM_SE3_PERF_SEL_CB_CLEAN', 'GRBM_SE3_PERF_SEL_COUNT', + 'GRBM_SE3_PERF_SEL_DB_BUSY', 'GRBM_SE3_PERF_SEL_DB_CLEAN', + 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', 'GRBM_SE3_PERF_SEL_PA_BUSY', + 'GRBM_SE3_PERF_SEL_RESERVED_0', 'GRBM_SE3_PERF_SEL_RESERVED_1', + 'GRBM_SE3_PERF_SEL_RESERVED_2', 'GRBM_SE3_PERF_SEL_RMI_BUSY', + 'GRBM_SE3_PERF_SEL_SC_BUSY', 'GRBM_SE3_PERF_SEL_SPI_BUSY', + 'GRBM_SE3_PERF_SEL_SX_BUSY', 'GRBM_SE3_PERF_SEL_TA_BUSY', + 'GRBM_SE3_PERF_SEL_TCP_BUSY', 'GRBM_SE3_PERF_SEL_USER_DEFINED', + 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', 'GSTHREADID_SIZE', 'GS_CUT_1024', + 'GS_CUT_128', 'GS_CUT_256', 'GS_CUT_512', 'GS_OFF', + 'GS_SCENARIO_A', 'GS_SCENARIO_B', 'GS_SCENARIO_C', + 'GS_SCENARIO_G', 'GS_STAGE_OFF', 'GS_STAGE_ON', 'GroupInterleave', + 'HDMI_ACR_0_MULTIPLE_RESERVED', 'HDMI_ACR_1_MULTIPLE', + 'HDMI_ACR_2_MULTIPLE', 'HDMI_ACR_3_MULTIPLE_RESERVED', + 'HDMI_ACR_4_MULTIPLE', 'HDMI_ACR_5_MULTIPLE_RESERVED', + 'HDMI_ACR_6_MULTIPLE_RESERVED', 'HDMI_ACR_7_MULTIPLE_RESERVED', + 'HDMI_ACR_AUDIO_PRIORITY', 'HDMI_ACR_CONT', + 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', + 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', + 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', + 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', + 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', + 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', + 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', + 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', + 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', + 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', + 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', + 'HDMI_AUDIO_INFO_SEND', + 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', + 'HDMI_AUDIO_SEND_MAX_PACKETS', + 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DEEP_COLOR_DEPTH', + 'HDMI_DEEP_COLOR_DEPTH_24BPP', 'HDMI_DEEP_COLOR_DEPTH_30BPP', + 'HDMI_DEEP_COLOR_DEPTH_36BPP', 'HDMI_DEEP_COLOR_DEPTH_48BPP', + 'HDMI_DEFAULT_PAHSE', 'HDMI_DEFAULT_PHASE_IS_0', + 'HDMI_DEFAULT_PHASE_IS_1', 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', + 'HDMI_ERROR_MASK', 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', + 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', + 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_GC_AVMUTE', + 'HDMI_GC_AVMUTE_CONT', 'HDMI_GC_AVMUTE_CONT_DISABLE', + 'HDMI_GC_AVMUTE_CONT_ENABLE', 'HDMI_GC_AVMUTE_SET', + 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', 'HDMI_GC_CONT_DISABLE', + 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', 'HDMI_GC_PKT_SEND', + 'HDMI_GC_SEND', 'HDMI_GENERIC_CONT', 'HDMI_GENERIC_CONT_DISABLE', + 'HDMI_GENERIC_CONT_ENABLE', 'HDMI_GENERIC_NOT_SEND', + 'HDMI_GENERIC_PKT_SEND', 'HDMI_GENERIC_SEND', 'HDMI_ISRC_CONT', + 'HDMI_ISRC_CONT_DISABLE', 'HDMI_ISRC_CONT_ENABLE', + 'HDMI_ISRC_NOT_SEND', 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', + 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', + 'HDMI_METADATA_ENABLE', 'HDMI_METADATA_NOT_SEND', + 'HDMI_METADATA_PKT_SEND', 'HDMI_MPEG_INFO_CONT', + 'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE', + 'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND', + 'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', + 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', + 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', + 'HDMI_PACKET_LINE_REFERENCE', 'HDMI_PACKING_PHASE_OVERRIDE', + 'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW', + 'HDMI_PKT_LINE_REF_OTGSOF', 'HDMI_PKT_LINE_REF_VSYNC', + 'HDMI_SEND_MAX_AUDIO_PACKETS', 'HDP_ENDIAN_8IN16', + 'HDP_ENDIAN_8IN32', 'HDP_ENDIAN_8IN64', 'HDP_ENDIAN_NONE', + 'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0', + 'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON', + 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', + 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', + 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HS_GS', 'HS_STAGE_OFF', + 'HS_STAGE_ON', 'HUBP_BLANK_EN', 'HUBP_BLANK_SW_ASSERT', + 'HUBP_BLANK_SW_DEASSERT', 'HUBP_DISABLE', 'HUBP_DISABLED', + 'HUBP_ENABLED', 'HUBP_IN_ACTIVE', 'HUBP_IN_BLANK', + 'HUBP_IN_VBLANK', 'HUBP_MEASURE_WIN_MODE_DCFCLK', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', 'HUBP_NO_OUTSTANDING_REQ', + 'HUBP_TTU_DISABLE', 'HUBP_TTU_DISABLED', 'HUBP_TTU_ENABLED', + 'HUBP_VREADY_AT_OR_AFTER_VSYNC', 'HUBP_VTG_SEL', + 'HUBP_XFC_CHUNK_SIZE_16KB', 'HUBP_XFC_CHUNK_SIZE_1KB', + 'HUBP_XFC_CHUNK_SIZE_256B', 'HUBP_XFC_CHUNK_SIZE_2KB', + 'HUBP_XFC_CHUNK_SIZE_32KB', 'HUBP_XFC_CHUNK_SIZE_4KB', + 'HUBP_XFC_CHUNK_SIZE_512B', 'HUBP_XFC_CHUNK_SIZE_8KB', + 'HUBP_XFC_CHUNK_SIZE_ENUM', 'HUBP_XFC_FRAME_MODE_ENUM', + 'HUBP_XFC_FULL_FRAME_MODE', 'HUBP_XFC_PARTIAL_FRAME_MODE', + 'HUBP_XFC_PIXEL_FORMAT_ENUM', 'HUBP_XFC_PIXEL_IS_32BPP', + 'HUBP_XFC_PIXEL_IS_64BPP', 'HW_MIRRORING_DISABLE', + 'HW_MIRRORING_ENABLE', 'H_MIRROR_EN', 'Hdp_SurfaceEndian', + 'ID_STREAM_DISABLE_ACKED', 'ID_STREAM_DISABLE_NO_ACK', + 'IHC_INTERRUPT_LINE_STATUS', 'IH_CLIENT_TYPE', + 'IH_CLIENT_TYPE_RESERVED', 'IH_GFX_VMID_CLIENT', + 'IH_INTERFACE_TYPE', 'IH_LEGACY_INTERFACE', 'IH_MM_VMID_CLIENT', + 'IH_MULTI_VMID_CLIENT', 'IH_PERF_SEL', + 'IH_PERF_SEL_BIF_LINE0_FALLING', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF16', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF17', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF18', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF19', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF20', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF21', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF22', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF23', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF24', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF25', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF26', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF27', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF28', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF29', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF30', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', + 'IH_PERF_SEL_BIF_LINE0_RISING', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF16', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF17', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF18', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF19', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF20', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF21', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF22', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF23', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF24', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF25', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF26', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF27', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF28', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF29', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF30', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', + 'IH_PERF_SEL_BUFFER_FIFO_FULL', 'IH_PERF_SEL_BUFFER_IDLE', + 'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT', + 'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT', + 'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT', + 'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT', + 'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT', + 'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT', + 'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT', + 'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT', + 'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT', + 'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT', + 'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT', + 'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT', + 'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT', + 'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT', + 'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT', + 'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT', + 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', 'IH_PERF_SEL_COOKIE_REC_ERROR', + 'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE', + 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', + 'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT', + 'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL', + 'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB0_FULL_VF0', + 'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10', + 'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12', + 'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14', + 'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF16', + 'IH_PERF_SEL_RB0_FULL_VF17', 'IH_PERF_SEL_RB0_FULL_VF18', + 'IH_PERF_SEL_RB0_FULL_VF19', 'IH_PERF_SEL_RB0_FULL_VF2', + 'IH_PERF_SEL_RB0_FULL_VF20', 'IH_PERF_SEL_RB0_FULL_VF21', + 'IH_PERF_SEL_RB0_FULL_VF22', 'IH_PERF_SEL_RB0_FULL_VF23', + 'IH_PERF_SEL_RB0_FULL_VF24', 'IH_PERF_SEL_RB0_FULL_VF25', + 'IH_PERF_SEL_RB0_FULL_VF26', 'IH_PERF_SEL_RB0_FULL_VF27', + 'IH_PERF_SEL_RB0_FULL_VF28', 'IH_PERF_SEL_RB0_FULL_VF29', + 'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF30', + 'IH_PERF_SEL_RB0_FULL_VF4', 'IH_PERF_SEL_RB0_FULL_VF5', + 'IH_PERF_SEL_RB0_FULL_VF6', 'IH_PERF_SEL_RB0_FULL_VF7', + 'IH_PERF_SEL_RB0_FULL_VF8', 'IH_PERF_SEL_RB0_FULL_VF9', + 'IH_PERF_SEL_RB0_LOAD_RPTR', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF16', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF17', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF18', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF19', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF20', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF21', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF22', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF23', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF24', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF25', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF26', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF27', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF28', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF29', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF30', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB0_OVERFLOW', + 'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1', + 'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11', + 'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13', + 'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15', + 'IH_PERF_SEL_RB0_OVERFLOW_VF16', 'IH_PERF_SEL_RB0_OVERFLOW_VF17', + 'IH_PERF_SEL_RB0_OVERFLOW_VF18', 'IH_PERF_SEL_RB0_OVERFLOW_VF19', + 'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF20', + 'IH_PERF_SEL_RB0_OVERFLOW_VF21', 'IH_PERF_SEL_RB0_OVERFLOW_VF22', + 'IH_PERF_SEL_RB0_OVERFLOW_VF23', 'IH_PERF_SEL_RB0_OVERFLOW_VF24', + 'IH_PERF_SEL_RB0_OVERFLOW_VF25', 'IH_PERF_SEL_RB0_OVERFLOW_VF26', + 'IH_PERF_SEL_RB0_OVERFLOW_VF27', 'IH_PERF_SEL_RB0_OVERFLOW_VF28', + 'IH_PERF_SEL_RB0_OVERFLOW_VF29', 'IH_PERF_SEL_RB0_OVERFLOW_VF3', + 'IH_PERF_SEL_RB0_OVERFLOW_VF30', 'IH_PERF_SEL_RB0_OVERFLOW_VF4', + 'IH_PERF_SEL_RB0_OVERFLOW_VF5', 'IH_PERF_SEL_RB0_OVERFLOW_VF6', + 'IH_PERF_SEL_RB0_OVERFLOW_VF7', 'IH_PERF_SEL_RB0_OVERFLOW_VF8', + 'IH_PERF_SEL_RB0_OVERFLOW_VF9', 'IH_PERF_SEL_RB0_RPTR_WRAP', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF16', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF17', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF18', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF19', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF20', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF21', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF22', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF23', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF24', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF25', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF26', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF27', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF28', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF29', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF30', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF16', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF17', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF18', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF19', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF20', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF21', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF22', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF23', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF24', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF25', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF26', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF27', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF28', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF29', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF30', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB1_FULL_VF0', + 'IH_PERF_SEL_RB1_FULL_VF1', 'IH_PERF_SEL_RB1_FULL_VF10', + 'IH_PERF_SEL_RB1_FULL_VF11', 'IH_PERF_SEL_RB1_FULL_VF12', + 'IH_PERF_SEL_RB1_FULL_VF13', 'IH_PERF_SEL_RB1_FULL_VF14', + 'IH_PERF_SEL_RB1_FULL_VF15', 'IH_PERF_SEL_RB1_FULL_VF16', + 'IH_PERF_SEL_RB1_FULL_VF17', 'IH_PERF_SEL_RB1_FULL_VF18', + 'IH_PERF_SEL_RB1_FULL_VF19', 'IH_PERF_SEL_RB1_FULL_VF2', + 'IH_PERF_SEL_RB1_FULL_VF20', 'IH_PERF_SEL_RB1_FULL_VF21', + 'IH_PERF_SEL_RB1_FULL_VF22', 'IH_PERF_SEL_RB1_FULL_VF23', + 'IH_PERF_SEL_RB1_FULL_VF24', 'IH_PERF_SEL_RB1_FULL_VF25', + 'IH_PERF_SEL_RB1_FULL_VF26', 'IH_PERF_SEL_RB1_FULL_VF27', + 'IH_PERF_SEL_RB1_FULL_VF28', 'IH_PERF_SEL_RB1_FULL_VF29', + 'IH_PERF_SEL_RB1_FULL_VF3', 'IH_PERF_SEL_RB1_FULL_VF30', + 'IH_PERF_SEL_RB1_FULL_VF4', 'IH_PERF_SEL_RB1_FULL_VF5', + 'IH_PERF_SEL_RB1_FULL_VF6', 'IH_PERF_SEL_RB1_FULL_VF7', + 'IH_PERF_SEL_RB1_FULL_VF8', 'IH_PERF_SEL_RB1_FULL_VF9', + 'IH_PERF_SEL_RB1_LOAD_RPTR', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF16', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF17', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF18', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF19', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF20', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF21', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF22', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF23', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF24', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF25', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF26', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF27', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF28', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF29', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF30', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB1_OVERFLOW', + 'IH_PERF_SEL_RB1_OVERFLOW_VF0', 'IH_PERF_SEL_RB1_OVERFLOW_VF1', + 'IH_PERF_SEL_RB1_OVERFLOW_VF10', 'IH_PERF_SEL_RB1_OVERFLOW_VF11', + 'IH_PERF_SEL_RB1_OVERFLOW_VF12', 'IH_PERF_SEL_RB1_OVERFLOW_VF13', + 'IH_PERF_SEL_RB1_OVERFLOW_VF14', 'IH_PERF_SEL_RB1_OVERFLOW_VF15', + 'IH_PERF_SEL_RB1_OVERFLOW_VF16', 'IH_PERF_SEL_RB1_OVERFLOW_VF17', + 'IH_PERF_SEL_RB1_OVERFLOW_VF18', 'IH_PERF_SEL_RB1_OVERFLOW_VF19', + 'IH_PERF_SEL_RB1_OVERFLOW_VF2', 'IH_PERF_SEL_RB1_OVERFLOW_VF20', + 'IH_PERF_SEL_RB1_OVERFLOW_VF21', 'IH_PERF_SEL_RB1_OVERFLOW_VF22', + 'IH_PERF_SEL_RB1_OVERFLOW_VF23', 'IH_PERF_SEL_RB1_OVERFLOW_VF24', + 'IH_PERF_SEL_RB1_OVERFLOW_VF25', 'IH_PERF_SEL_RB1_OVERFLOW_VF26', + 'IH_PERF_SEL_RB1_OVERFLOW_VF27', 'IH_PERF_SEL_RB1_OVERFLOW_VF28', + 'IH_PERF_SEL_RB1_OVERFLOW_VF29', 'IH_PERF_SEL_RB1_OVERFLOW_VF3', + 'IH_PERF_SEL_RB1_OVERFLOW_VF30', 'IH_PERF_SEL_RB1_OVERFLOW_VF4', + 'IH_PERF_SEL_RB1_OVERFLOW_VF5', 'IH_PERF_SEL_RB1_OVERFLOW_VF6', + 'IH_PERF_SEL_RB1_OVERFLOW_VF7', 'IH_PERF_SEL_RB1_OVERFLOW_VF8', + 'IH_PERF_SEL_RB1_OVERFLOW_VF9', 'IH_PERF_SEL_RB1_RPTR_WRAP', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF16', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF17', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF18', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF19', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF20', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF21', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF22', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF23', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF24', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF25', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF26', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF27', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF28', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF29', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF30', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF16', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF17', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF18', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF19', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF20', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF21', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF22', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF23', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF24', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF25', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF26', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF27', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF28', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF29', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF30', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB2_FULL_VF0', + 'IH_PERF_SEL_RB2_FULL_VF1', 'IH_PERF_SEL_RB2_FULL_VF10', + 'IH_PERF_SEL_RB2_FULL_VF11', 'IH_PERF_SEL_RB2_FULL_VF12', + 'IH_PERF_SEL_RB2_FULL_VF13', 'IH_PERF_SEL_RB2_FULL_VF14', + 'IH_PERF_SEL_RB2_FULL_VF15', 'IH_PERF_SEL_RB2_FULL_VF16', + 'IH_PERF_SEL_RB2_FULL_VF17', 'IH_PERF_SEL_RB2_FULL_VF18', + 'IH_PERF_SEL_RB2_FULL_VF19', 'IH_PERF_SEL_RB2_FULL_VF2', + 'IH_PERF_SEL_RB2_FULL_VF20', 'IH_PERF_SEL_RB2_FULL_VF21', + 'IH_PERF_SEL_RB2_FULL_VF22', 'IH_PERF_SEL_RB2_FULL_VF23', + 'IH_PERF_SEL_RB2_FULL_VF24', 'IH_PERF_SEL_RB2_FULL_VF25', + 'IH_PERF_SEL_RB2_FULL_VF26', 'IH_PERF_SEL_RB2_FULL_VF27', + 'IH_PERF_SEL_RB2_FULL_VF28', 'IH_PERF_SEL_RB2_FULL_VF29', + 'IH_PERF_SEL_RB2_FULL_VF3', 'IH_PERF_SEL_RB2_FULL_VF30', + 'IH_PERF_SEL_RB2_FULL_VF4', 'IH_PERF_SEL_RB2_FULL_VF5', + 'IH_PERF_SEL_RB2_FULL_VF6', 'IH_PERF_SEL_RB2_FULL_VF7', + 'IH_PERF_SEL_RB2_FULL_VF8', 'IH_PERF_SEL_RB2_FULL_VF9', + 'IH_PERF_SEL_RB2_LOAD_RPTR', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF16', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF17', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF18', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF19', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF20', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF21', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF22', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF23', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF24', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF25', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF26', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF27', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF28', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF29', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF30', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB2_OVERFLOW', + 'IH_PERF_SEL_RB2_OVERFLOW_VF0', 'IH_PERF_SEL_RB2_OVERFLOW_VF1', + 'IH_PERF_SEL_RB2_OVERFLOW_VF10', 'IH_PERF_SEL_RB2_OVERFLOW_VF11', + 'IH_PERF_SEL_RB2_OVERFLOW_VF12', 'IH_PERF_SEL_RB2_OVERFLOW_VF13', + 'IH_PERF_SEL_RB2_OVERFLOW_VF14', 'IH_PERF_SEL_RB2_OVERFLOW_VF15', + 'IH_PERF_SEL_RB2_OVERFLOW_VF16', 'IH_PERF_SEL_RB2_OVERFLOW_VF17', + 'IH_PERF_SEL_RB2_OVERFLOW_VF18', 'IH_PERF_SEL_RB2_OVERFLOW_VF19', + 'IH_PERF_SEL_RB2_OVERFLOW_VF2', 'IH_PERF_SEL_RB2_OVERFLOW_VF20', + 'IH_PERF_SEL_RB2_OVERFLOW_VF21', 'IH_PERF_SEL_RB2_OVERFLOW_VF22', + 'IH_PERF_SEL_RB2_OVERFLOW_VF23', 'IH_PERF_SEL_RB2_OVERFLOW_VF24', + 'IH_PERF_SEL_RB2_OVERFLOW_VF25', 'IH_PERF_SEL_RB2_OVERFLOW_VF26', + 'IH_PERF_SEL_RB2_OVERFLOW_VF27', 'IH_PERF_SEL_RB2_OVERFLOW_VF28', + 'IH_PERF_SEL_RB2_OVERFLOW_VF29', 'IH_PERF_SEL_RB2_OVERFLOW_VF3', + 'IH_PERF_SEL_RB2_OVERFLOW_VF30', 'IH_PERF_SEL_RB2_OVERFLOW_VF4', + 'IH_PERF_SEL_RB2_OVERFLOW_VF5', 'IH_PERF_SEL_RB2_OVERFLOW_VF6', + 'IH_PERF_SEL_RB2_OVERFLOW_VF7', 'IH_PERF_SEL_RB2_OVERFLOW_VF8', + 'IH_PERF_SEL_RB2_OVERFLOW_VF9', 'IH_PERF_SEL_RB2_RPTR_WRAP', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF16', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF17', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF18', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF19', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF20', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF21', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF22', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF23', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF24', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF25', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF26', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF27', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF28', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF29', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF30', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF16', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF17', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF18', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF19', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF20', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF21', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF22', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF23', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF24', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF25', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF26', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF27', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF28', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF29', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF30', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IH_PERF_SEL_SELF_IV_VALID', + 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', + 'IH_REGISTER_WRITE_INTERFACE', 'IH_RING_ID', + 'IH_RING_ID_INTERRUPT', 'IH_RING_ID_REQUEST', + 'IH_RING_ID_RESERVED', 'IH_RING_ID_TRANSLATION', + 'IH_VF_RB_SELECT', 'IH_VF_RB_SELECT_CLIENT_FCN_ID', + 'IH_VF_RB_SELECT_IH_FCN_ID', 'IH_VF_RB_SELECT_PF', + 'IH_VF_RB_SELECT_RESERVED', 'IMG_DATA_FORMAT', + 'IMG_DATA_FORMAT_1', 'IMG_DATA_FORMAT_10_10_10_2', + 'IMG_DATA_FORMAT_10_11_11', 'IMG_DATA_FORMAT_11_11_10', + 'IMG_DATA_FORMAT_16', 'IMG_DATA_FORMAT_16_16', + 'IMG_DATA_FORMAT_16_16_16_16', 'IMG_DATA_FORMAT_1_5_5_5', + 'IMG_DATA_FORMAT_1_REVERSED', 'IMG_DATA_FORMAT_24_8', + 'IMG_DATA_FORMAT_2_10_10_10', 'IMG_DATA_FORMAT_32', + 'IMG_DATA_FORMAT_32_32', 'IMG_DATA_FORMAT_32_32_32', + 'IMG_DATA_FORMAT_32_32_32_32', + 'IMG_DATA_FORMAT_32_AS_32_32_32_32', 'IMG_DATA_FORMAT_4_4', + 'IMG_DATA_FORMAT_4_4_4_4', 'IMG_DATA_FORMAT_5_5_5_1', + 'IMG_DATA_FORMAT_5_6_5', 'IMG_DATA_FORMAT_5_9_9_9', + 'IMG_DATA_FORMAT_6E4', 'IMG_DATA_FORMAT_6_5_5', + 'IMG_DATA_FORMAT_8', 'IMG_DATA_FORMAT_8_24', + 'IMG_DATA_FORMAT_8_8', 'IMG_DATA_FORMAT_8_8_8_8', + 'IMG_DATA_FORMAT_BC1', 'IMG_DATA_FORMAT_BC2', + 'IMG_DATA_FORMAT_BC3', 'IMG_DATA_FORMAT_BC4', + 'IMG_DATA_FORMAT_BC5', 'IMG_DATA_FORMAT_BC6', + 'IMG_DATA_FORMAT_BC7', 'IMG_DATA_FORMAT_BG_RG', + 'IMG_DATA_FORMAT_FMASK16_S16_F1', 'IMG_DATA_FORMAT_FMASK16_S8_F2', + 'IMG_DATA_FORMAT_FMASK32_S16_F2', 'IMG_DATA_FORMAT_FMASK32_S8_F4', + 'IMG_DATA_FORMAT_FMASK32_S8_F8', 'IMG_DATA_FORMAT_FMASK64_S16_F4', + 'IMG_DATA_FORMAT_FMASK64_S16_F8', 'IMG_DATA_FORMAT_FMASK8_S2_F1', + 'IMG_DATA_FORMAT_FMASK8_S2_F2', 'IMG_DATA_FORMAT_FMASK8_S4_F1', + 'IMG_DATA_FORMAT_FMASK8_S4_F2', 'IMG_DATA_FORMAT_FMASK8_S4_F4', + 'IMG_DATA_FORMAT_FMASK8_S8_F1', 'IMG_DATA_FORMAT_GB_GR', + 'IMG_DATA_FORMAT_INVALID', 'IMG_DATA_FORMAT_MM_10_11_11', + 'IMG_DATA_FORMAT_MM_10_IN_16', 'IMG_DATA_FORMAT_MM_10_IN_16_16', + 'IMG_DATA_FORMAT_MM_10_IN_16_16_16_16', + 'IMG_DATA_FORMAT_MM_16_16_16_16', 'IMG_DATA_FORMAT_MM_2_10_10_10', + 'IMG_DATA_FORMAT_MM_8', 'IMG_DATA_FORMAT_MM_8_8', + 'IMG_DATA_FORMAT_MM_8_8_8_8', 'IMG_DATA_FORMAT_MM_VYUY8', + 'IMG_DATA_FORMAT_RESERVED_100', 'IMG_DATA_FORMAT_RESERVED_101', + 'IMG_DATA_FORMAT_RESERVED_102', 'IMG_DATA_FORMAT_RESERVED_103', + 'IMG_DATA_FORMAT_RESERVED_104', 'IMG_DATA_FORMAT_RESERVED_105', + 'IMG_DATA_FORMAT_RESERVED_106', 'IMG_DATA_FORMAT_RESERVED_107', + 'IMG_DATA_FORMAT_RESERVED_108', 'IMG_DATA_FORMAT_RESERVED_109', + 'IMG_DATA_FORMAT_RESERVED_110', 'IMG_DATA_FORMAT_RESERVED_111', + 'IMG_DATA_FORMAT_RESERVED_112', 'IMG_DATA_FORMAT_RESERVED_113', + 'IMG_DATA_FORMAT_RESERVED_114', 'IMG_DATA_FORMAT_RESERVED_115', + 'IMG_DATA_FORMAT_RESERVED_116', 'IMG_DATA_FORMAT_RESERVED_117', + 'IMG_DATA_FORMAT_RESERVED_118', 'IMG_DATA_FORMAT_RESERVED_119', + 'IMG_DATA_FORMAT_RESERVED_120', 'IMG_DATA_FORMAT_RESERVED_121', + 'IMG_DATA_FORMAT_RESERVED_122', 'IMG_DATA_FORMAT_RESERVED_123', + 'IMG_DATA_FORMAT_RESERVED_124', 'IMG_DATA_FORMAT_RESERVED_125', + 'IMG_DATA_FORMAT_RESERVED_126', 'IMG_DATA_FORMAT_RESERVED_127', + 'IMG_DATA_FORMAT_RESERVED_15', 'IMG_DATA_FORMAT_RESERVED_23', + 'IMG_DATA_FORMAT_RESERVED_24', 'IMG_DATA_FORMAT_RESERVED_25', + 'IMG_DATA_FORMAT_RESERVED_26', 'IMG_DATA_FORMAT_RESERVED_27', + 'IMG_DATA_FORMAT_RESERVED_28', 'IMG_DATA_FORMAT_RESERVED_29', + 'IMG_DATA_FORMAT_RESERVED_30', 'IMG_DATA_FORMAT_RESERVED_42', + 'IMG_DATA_FORMAT_RESERVED_43', 'IMG_DATA_FORMAT_RESERVED_61', + 'IMG_DATA_FORMAT_RESERVED_62', 'IMG_DATA_FORMAT_RESERVED_75', + 'IMG_DATA_FORMAT_RESERVED_86', 'IMG_DATA_FORMAT_RESERVED_87', + 'IMG_DATA_FORMAT_RESERVED_88', 'IMG_DATA_FORMAT_RESERVED_89', + 'IMG_DATA_FORMAT_RESERVED_90', 'IMG_DATA_FORMAT_RESERVED_91', + 'IMG_DATA_FORMAT_RESERVED_92', 'IMG_DATA_FORMAT_RESERVED_93', + 'IMG_DATA_FORMAT_RESERVED_94', 'IMG_DATA_FORMAT_RESERVED_95', + 'IMG_DATA_FORMAT_RESERVED_96', 'IMG_DATA_FORMAT_RESERVED_97', + 'IMG_DATA_FORMAT_RESERVED_98', 'IMG_DATA_FORMAT_RESERVED_99', + 'IMG_DATA_FORMAT_X24_8_32', 'IMG_FMT', 'IMG_FMT_10_10_10_2_SINT', + 'IMG_FMT_10_10_10_2_SNORM', 'IMG_FMT_10_10_10_2_SSCALED', + 'IMG_FMT_10_10_10_2_UINT', 'IMG_FMT_10_10_10_2_UNORM', + 'IMG_FMT_10_10_10_2_USCALED', 'IMG_FMT_10_11_11_FLOAT', + 'IMG_FMT_10_11_11_SINT', 'IMG_FMT_10_11_11_SNORM', + 'IMG_FMT_10_11_11_SSCALED', 'IMG_FMT_10_11_11_UINT', + 'IMG_FMT_10_11_11_UNORM', 'IMG_FMT_10_11_11_USCALED', + 'IMG_FMT_11_11_10_FLOAT', 'IMG_FMT_11_11_10_SINT', + 'IMG_FMT_11_11_10_SNORM', 'IMG_FMT_11_11_10_SSCALED', + 'IMG_FMT_11_11_10_UINT', 'IMG_FMT_11_11_10_UNORM', + 'IMG_FMT_11_11_10_USCALED', 'IMG_FMT_16_16_16_16_FLOAT', + 'IMG_FMT_16_16_16_16_SINT', 'IMG_FMT_16_16_16_16_SNORM', + 'IMG_FMT_16_16_16_16_SSCALED', 'IMG_FMT_16_16_16_16_UINT', + 'IMG_FMT_16_16_16_16_UNORM', 'IMG_FMT_16_16_16_16_USCALED', + 'IMG_FMT_16_16_FLOAT', 'IMG_FMT_16_16_SINT', + 'IMG_FMT_16_16_SNORM', 'IMG_FMT_16_16_SSCALED', + 'IMG_FMT_16_16_UINT', 'IMG_FMT_16_16_UNORM', + 'IMG_FMT_16_16_USCALED', 'IMG_FMT_16_FLOAT', 'IMG_FMT_16_SINT', + 'IMG_FMT_16_SNORM', 'IMG_FMT_16_SSCALED', 'IMG_FMT_16_UINT', + 'IMG_FMT_16_UNORM', 'IMG_FMT_16_USCALED', 'IMG_FMT_1_5_5_5_UNORM', + 'IMG_FMT_1_REVERSED_UNORM', 'IMG_FMT_1_UNORM', + 'IMG_FMT_24_8_UINT', 'IMG_FMT_24_8_UNORM', + 'IMG_FMT_2_10_10_10_SINT', 'IMG_FMT_2_10_10_10_SNORM', + 'IMG_FMT_2_10_10_10_SSCALED', 'IMG_FMT_2_10_10_10_UINT', + 'IMG_FMT_2_10_10_10_UNORM', 'IMG_FMT_2_10_10_10_USCALED', + 'IMG_FMT_32_32_32_32_FLOAT', 'IMG_FMT_32_32_32_32_SINT', + 'IMG_FMT_32_32_32_32_UINT', 'IMG_FMT_32_32_32_FLOAT', + 'IMG_FMT_32_32_32_SINT', 'IMG_FMT_32_32_32_UINT', + 'IMG_FMT_32_32_FLOAT', 'IMG_FMT_32_32_SINT', 'IMG_FMT_32_32_UINT', + 'IMG_FMT_32_FLOAT', 'IMG_FMT_32_FLOAT_CLAMP', 'IMG_FMT_32_SINT', + 'IMG_FMT_32_UINT', 'IMG_FMT_4_4_4_4_UNORM', 'IMG_FMT_4_4_UNORM', + 'IMG_FMT_5_5_5_1_UNORM', 'IMG_FMT_5_6_5_UNORM', + 'IMG_FMT_5_9_9_9_FLOAT', 'IMG_FMT_6E4_FLOAT', 'IMG_FMT_8_24_UINT', + 'IMG_FMT_8_24_UNORM', 'IMG_FMT_8_8_8_8_SINT', + 'IMG_FMT_8_8_8_8_SNORM', 'IMG_FMT_8_8_8_8_SRGB', + 'IMG_FMT_8_8_8_8_SSCALED', 'IMG_FMT_8_8_8_8_UINT', + 'IMG_FMT_8_8_8_8_UNORM', 'IMG_FMT_8_8_8_8_USCALED', + 'IMG_FMT_8_8_SINT', 'IMG_FMT_8_8_SNORM', 'IMG_FMT_8_8_SRGB', + 'IMG_FMT_8_8_SSCALED', 'IMG_FMT_8_8_UINT', 'IMG_FMT_8_8_UNORM', + 'IMG_FMT_8_8_USCALED', 'IMG_FMT_8_SINT', 'IMG_FMT_8_SNORM', + 'IMG_FMT_8_SRGB', 'IMG_FMT_8_SSCALED', 'IMG_FMT_8_UINT', + 'IMG_FMT_8_UNORM', 'IMG_FMT_8_USCALED', 'IMG_FMT_BC1_SRGB', + 'IMG_FMT_BC1_UNORM', 'IMG_FMT_BC2_SRGB', 'IMG_FMT_BC2_UNORM', + 'IMG_FMT_BC3_SRGB', 'IMG_FMT_BC3_UNORM', 'IMG_FMT_BC4_SNORM', + 'IMG_FMT_BC4_UNORM', 'IMG_FMT_BC5_SNORM', 'IMG_FMT_BC5_UNORM', + 'IMG_FMT_BC6_SFLOAT', 'IMG_FMT_BC6_UFLOAT', 'IMG_FMT_BC7_SRGB', + 'IMG_FMT_BC7_UNORM', 'IMG_FMT_BG_RG_SNORM', 'IMG_FMT_BG_RG_SRGB', + 'IMG_FMT_BG_RG_UINT', 'IMG_FMT_BG_RG_UNORM', + 'IMG_FMT_FMASK16_S16_F1', 'IMG_FMT_FMASK16_S8_F2', + 'IMG_FMT_FMASK32_S16_F2', 'IMG_FMT_FMASK32_S8_F4', + 'IMG_FMT_FMASK32_S8_F8', 'IMG_FMT_FMASK64_S16_F4', + 'IMG_FMT_FMASK64_S16_F8', 'IMG_FMT_FMASK8_S2_F1', + 'IMG_FMT_FMASK8_S2_F2', 'IMG_FMT_FMASK8_S4_F1', + 'IMG_FMT_FMASK8_S4_F2', 'IMG_FMT_FMASK8_S4_F4', + 'IMG_FMT_FMASK8_S8_F1', 'IMG_FMT_GB_GR_SNORM', + 'IMG_FMT_GB_GR_SRGB', 'IMG_FMT_GB_GR_UINT', 'IMG_FMT_GB_GR_UNORM', + 'IMG_FMT_INVALID', 'IMG_FMT_MM_10_11_11_UINT', + 'IMG_FMT_MM_10_11_11_UNORM', 'IMG_FMT_MM_10_IN_16_16_16_16_UINT', + 'IMG_FMT_MM_10_IN_16_16_16_16_UNORM', + 'IMG_FMT_MM_10_IN_16_16_UINT', 'IMG_FMT_MM_10_IN_16_16_UNORM', + 'IMG_FMT_MM_10_IN_16_UINT', 'IMG_FMT_MM_10_IN_16_UNORM', + 'IMG_FMT_MM_16_16_16_16_UINT', 'IMG_FMT_MM_16_16_16_16_UNORM', + 'IMG_FMT_MM_2_10_10_10_UINT', 'IMG_FMT_MM_2_10_10_10_UNORM', + 'IMG_FMT_MM_8_8_8_8_UINT', 'IMG_FMT_MM_8_8_8_8_UNORM', + 'IMG_FMT_MM_8_8_UINT', 'IMG_FMT_MM_8_8_UNORM', + 'IMG_FMT_MM_8_UINT', 'IMG_FMT_MM_8_UNORM', + 'IMG_FMT_MM_VYUY8_UINT', 'IMG_FMT_MM_VYUY8_UNORM', + 'IMG_FMT_RESERVED_100', 'IMG_FMT_RESERVED_101', + 'IMG_FMT_RESERVED_102', 'IMG_FMT_RESERVED_103', + 'IMG_FMT_RESERVED_104', 'IMG_FMT_RESERVED_105', + 'IMG_FMT_RESERVED_106', 'IMG_FMT_RESERVED_107', + 'IMG_FMT_RESERVED_108', 'IMG_FMT_RESERVED_109', + 'IMG_FMT_RESERVED_110', 'IMG_FMT_RESERVED_111', + 'IMG_FMT_RESERVED_112', 'IMG_FMT_RESERVED_113', + 'IMG_FMT_RESERVED_114', 'IMG_FMT_RESERVED_115', + 'IMG_FMT_RESERVED_116', 'IMG_FMT_RESERVED_117', + 'IMG_FMT_RESERVED_118', 'IMG_FMT_RESERVED_119', + 'IMG_FMT_RESERVED_120', 'IMG_FMT_RESERVED_121', + 'IMG_FMT_RESERVED_122', 'IMG_FMT_RESERVED_123', + 'IMG_FMT_RESERVED_124', 'IMG_FMT_RESERVED_125', + 'IMG_FMT_RESERVED_126', 'IMG_FMT_RESERVED_127', + 'IMG_FMT_RESERVED_155', 'IMG_FMT_RESERVED_285', + 'IMG_FMT_RESERVED_286', 'IMG_FMT_RESERVED_287', + 'IMG_FMT_RESERVED_288', 'IMG_FMT_RESERVED_289', + 'IMG_FMT_RESERVED_290', 'IMG_FMT_RESERVED_291', + 'IMG_FMT_RESERVED_292', 'IMG_FMT_RESERVED_293', + 'IMG_FMT_RESERVED_294', 'IMG_FMT_RESERVED_295', + 'IMG_FMT_RESERVED_296', 'IMG_FMT_RESERVED_297', + 'IMG_FMT_RESERVED_298', 'IMG_FMT_RESERVED_299', + 'IMG_FMT_RESERVED_300', 'IMG_FMT_RESERVED_301', + 'IMG_FMT_RESERVED_302', 'IMG_FMT_RESERVED_303', + 'IMG_FMT_RESERVED_304', 'IMG_FMT_RESERVED_305', + 'IMG_FMT_RESERVED_306', 'IMG_FMT_RESERVED_307', + 'IMG_FMT_RESERVED_308', 'IMG_FMT_RESERVED_309', + 'IMG_FMT_RESERVED_310', 'IMG_FMT_RESERVED_311', + 'IMG_FMT_RESERVED_312', 'IMG_FMT_RESERVED_313', + 'IMG_FMT_RESERVED_314', 'IMG_FMT_RESERVED_315', + 'IMG_FMT_RESERVED_316', 'IMG_FMT_RESERVED_317', + 'IMG_FMT_RESERVED_318', 'IMG_FMT_RESERVED_319', + 'IMG_FMT_RESERVED_320', 'IMG_FMT_RESERVED_321', + 'IMG_FMT_RESERVED_322', 'IMG_FMT_RESERVED_323', + 'IMG_FMT_RESERVED_324', 'IMG_FMT_RESERVED_325', + 'IMG_FMT_RESERVED_326', 'IMG_FMT_RESERVED_327', + 'IMG_FMT_RESERVED_328', 'IMG_FMT_RESERVED_329', + 'IMG_FMT_RESERVED_330', 'IMG_FMT_RESERVED_331', + 'IMG_FMT_RESERVED_332', 'IMG_FMT_RESERVED_333', + 'IMG_FMT_RESERVED_334', 'IMG_FMT_RESERVED_335', + 'IMG_FMT_RESERVED_336', 'IMG_FMT_RESERVED_337', + 'IMG_FMT_RESERVED_338', 'IMG_FMT_RESERVED_339', + 'IMG_FMT_RESERVED_340', 'IMG_FMT_RESERVED_341', + 'IMG_FMT_RESERVED_342', 'IMG_FMT_RESERVED_343', + 'IMG_FMT_RESERVED_344', 'IMG_FMT_RESERVED_345', + 'IMG_FMT_RESERVED_346', 'IMG_FMT_RESERVED_347', + 'IMG_FMT_RESERVED_348', 'IMG_FMT_RESERVED_349', + 'IMG_FMT_RESERVED_350', 'IMG_FMT_RESERVED_351', + 'IMG_FMT_RESERVED_352', 'IMG_FMT_RESERVED_353', + 'IMG_FMT_RESERVED_354', 'IMG_FMT_RESERVED_355', + 'IMG_FMT_RESERVED_356', 'IMG_FMT_RESERVED_357', + 'IMG_FMT_RESERVED_358', 'IMG_FMT_RESERVED_359', + 'IMG_FMT_RESERVED_360', 'IMG_FMT_RESERVED_361', + 'IMG_FMT_RESERVED_362', 'IMG_FMT_RESERVED_363', + 'IMG_FMT_RESERVED_364', 'IMG_FMT_RESERVED_365', + 'IMG_FMT_RESERVED_366', 'IMG_FMT_RESERVED_367', + 'IMG_FMT_RESERVED_368', 'IMG_FMT_RESERVED_369', + 'IMG_FMT_RESERVED_370', 'IMG_FMT_RESERVED_371', + 'IMG_FMT_RESERVED_372', 'IMG_FMT_RESERVED_373', + 'IMG_FMT_RESERVED_374', 'IMG_FMT_RESERVED_375', + 'IMG_FMT_RESERVED_376', 'IMG_FMT_RESERVED_377', + 'IMG_FMT_RESERVED_378', 'IMG_FMT_RESERVED_379', + 'IMG_FMT_RESERVED_380', 'IMG_FMT_RESERVED_381', + 'IMG_FMT_RESERVED_382', 'IMG_FMT_RESERVED_383', + 'IMG_FMT_RESERVED_384', 'IMG_FMT_RESERVED_385', + 'IMG_FMT_RESERVED_386', 'IMG_FMT_RESERVED_387', + 'IMG_FMT_RESERVED_388', 'IMG_FMT_RESERVED_389', + 'IMG_FMT_RESERVED_390', 'IMG_FMT_RESERVED_391', + 'IMG_FMT_RESERVED_392', 'IMG_FMT_RESERVED_393', + 'IMG_FMT_RESERVED_394', 'IMG_FMT_RESERVED_395', + 'IMG_FMT_RESERVED_396', 'IMG_FMT_RESERVED_397', + 'IMG_FMT_RESERVED_398', 'IMG_FMT_RESERVED_399', + 'IMG_FMT_RESERVED_400', 'IMG_FMT_RESERVED_401', + 'IMG_FMT_RESERVED_402', 'IMG_FMT_RESERVED_403', + 'IMG_FMT_RESERVED_404', 'IMG_FMT_RESERVED_405', + 'IMG_FMT_RESERVED_406', 'IMG_FMT_RESERVED_407', + 'IMG_FMT_RESERVED_408', 'IMG_FMT_RESERVED_409', + 'IMG_FMT_RESERVED_410', 'IMG_FMT_RESERVED_411', + 'IMG_FMT_RESERVED_412', 'IMG_FMT_RESERVED_413', + 'IMG_FMT_RESERVED_414', 'IMG_FMT_RESERVED_415', + 'IMG_FMT_RESERVED_416', 'IMG_FMT_RESERVED_417', + 'IMG_FMT_RESERVED_418', 'IMG_FMT_RESERVED_419', + 'IMG_FMT_RESERVED_420', 'IMG_FMT_RESERVED_421', + 'IMG_FMT_RESERVED_422', 'IMG_FMT_RESERVED_423', + 'IMG_FMT_RESERVED_424', 'IMG_FMT_RESERVED_425', + 'IMG_FMT_RESERVED_426', 'IMG_FMT_RESERVED_427', + 'IMG_FMT_RESERVED_428', 'IMG_FMT_RESERVED_429', + 'IMG_FMT_RESERVED_430', 'IMG_FMT_RESERVED_431', + 'IMG_FMT_RESERVED_432', 'IMG_FMT_RESERVED_433', + 'IMG_FMT_RESERVED_434', 'IMG_FMT_RESERVED_435', + 'IMG_FMT_RESERVED_436', 'IMG_FMT_RESERVED_437', + 'IMG_FMT_RESERVED_438', 'IMG_FMT_RESERVED_439', + 'IMG_FMT_RESERVED_440', 'IMG_FMT_RESERVED_441', + 'IMG_FMT_RESERVED_442', 'IMG_FMT_RESERVED_443', + 'IMG_FMT_RESERVED_444', 'IMG_FMT_RESERVED_445', + 'IMG_FMT_RESERVED_446', 'IMG_FMT_RESERVED_447', + 'IMG_FMT_RESERVED_448', 'IMG_FMT_RESERVED_449', + 'IMG_FMT_RESERVED_450', 'IMG_FMT_RESERVED_451', + 'IMG_FMT_RESERVED_452', 'IMG_FMT_RESERVED_453', + 'IMG_FMT_RESERVED_454', 'IMG_FMT_RESERVED_455', + 'IMG_FMT_RESERVED_456', 'IMG_FMT_RESERVED_457', + 'IMG_FMT_RESERVED_458', 'IMG_FMT_RESERVED_459', + 'IMG_FMT_RESERVED_460', 'IMG_FMT_RESERVED_461', + 'IMG_FMT_RESERVED_462', 'IMG_FMT_RESERVED_463', + 'IMG_FMT_RESERVED_464', 'IMG_FMT_RESERVED_465', + 'IMG_FMT_RESERVED_466', 'IMG_FMT_RESERVED_467', + 'IMG_FMT_RESERVED_468', 'IMG_FMT_RESERVED_469', + 'IMG_FMT_RESERVED_470', 'IMG_FMT_RESERVED_471', + 'IMG_FMT_RESERVED_472', 'IMG_FMT_RESERVED_473', + 'IMG_FMT_RESERVED_474', 'IMG_FMT_RESERVED_475', + 'IMG_FMT_RESERVED_476', 'IMG_FMT_RESERVED_477', + 'IMG_FMT_RESERVED_478', 'IMG_FMT_RESERVED_479', + 'IMG_FMT_RESERVED_480', 'IMG_FMT_RESERVED_481', + 'IMG_FMT_RESERVED_482', 'IMG_FMT_RESERVED_483', + 'IMG_FMT_RESERVED_484', 'IMG_FMT_RESERVED_485', + 'IMG_FMT_RESERVED_486', 'IMG_FMT_RESERVED_487', + 'IMG_FMT_RESERVED_488', 'IMG_FMT_RESERVED_489', + 'IMG_FMT_RESERVED_490', 'IMG_FMT_RESERVED_491', + 'IMG_FMT_RESERVED_492', 'IMG_FMT_RESERVED_493', + 'IMG_FMT_RESERVED_494', 'IMG_FMT_RESERVED_495', + 'IMG_FMT_RESERVED_496', 'IMG_FMT_RESERVED_497', + 'IMG_FMT_RESERVED_498', 'IMG_FMT_RESERVED_499', + 'IMG_FMT_RESERVED_500', 'IMG_FMT_RESERVED_501', + 'IMG_FMT_RESERVED_502', 'IMG_FMT_RESERVED_503', + 'IMG_FMT_RESERVED_504', 'IMG_FMT_RESERVED_505', + 'IMG_FMT_RESERVED_506', 'IMG_FMT_RESERVED_507', + 'IMG_FMT_RESERVED_508', 'IMG_FMT_RESERVED_509', + 'IMG_FMT_RESERVED_510', 'IMG_FMT_RESERVED_511', + 'IMG_FMT_RESERVED_78', 'IMG_FMT_RESERVED_79', + 'IMG_FMT_RESERVED_80', 'IMG_FMT_RESERVED_81', + 'IMG_FMT_RESERVED_82', 'IMG_FMT_RESERVED_83', + 'IMG_FMT_RESERVED_84', 'IMG_FMT_RESERVED_85', + 'IMG_FMT_RESERVED_86', 'IMG_FMT_RESERVED_87', + 'IMG_FMT_RESERVED_88', 'IMG_FMT_RESERVED_89', + 'IMG_FMT_RESERVED_90', 'IMG_FMT_RESERVED_91', + 'IMG_FMT_RESERVED_92', 'IMG_FMT_RESERVED_93', + 'IMG_FMT_RESERVED_94', 'IMG_FMT_RESERVED_95', + 'IMG_FMT_RESERVED_96', 'IMG_FMT_RESERVED_97', + 'IMG_FMT_RESERVED_98', 'IMG_FMT_RESERVED_99', + 'IMG_FMT_X24_8_32_FLOAT', 'IMG_FMT_X24_8_32_UINT', + 'IMG_NUM_FORMAT', 'IMG_NUM_FORMAT_FLOAT', 'IMG_NUM_FORMAT_FMASK', + 'IMG_NUM_FORMAT_FMASK_16_16_1', 'IMG_NUM_FORMAT_FMASK_16_8_2', + 'IMG_NUM_FORMAT_FMASK_32_16_2', 'IMG_NUM_FORMAT_FMASK_32_8_4', + 'IMG_NUM_FORMAT_FMASK_32_8_8', 'IMG_NUM_FORMAT_FMASK_64_16_4', + 'IMG_NUM_FORMAT_FMASK_64_16_8', 'IMG_NUM_FORMAT_FMASK_8_2_1', + 'IMG_NUM_FORMAT_FMASK_8_2_2', 'IMG_NUM_FORMAT_FMASK_8_4_1', + 'IMG_NUM_FORMAT_FMASK_8_4_2', 'IMG_NUM_FORMAT_FMASK_8_4_4', + 'IMG_NUM_FORMAT_FMASK_8_8_1', 'IMG_NUM_FORMAT_FMASK_RESERVED_13', + 'IMG_NUM_FORMAT_FMASK_RESERVED_14', + 'IMG_NUM_FORMAT_FMASK_RESERVED_15', 'IMG_NUM_FORMAT_N_IN_16', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9', + 'IMG_NUM_FORMAT_N_IN_16_UINT_10', 'IMG_NUM_FORMAT_N_IN_16_UINT_9', + 'IMG_NUM_FORMAT_N_IN_16_UNORM_10', + 'IMG_NUM_FORMAT_N_IN_16_UNORM_9', + 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10', + 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9', + 'IMG_NUM_FORMAT_RESERVED_14', 'IMG_NUM_FORMAT_RESERVED_15', + 'IMG_NUM_FORMAT_RESERVED_8', 'IMG_NUM_FORMAT_SINT', + 'IMG_NUM_FORMAT_SNORM', 'IMG_NUM_FORMAT_SNORM_NZ', + 'IMG_NUM_FORMAT_SRGB', 'IMG_NUM_FORMAT_SSCALED', + 'IMG_NUM_FORMAT_UBINT', 'IMG_NUM_FORMAT_UBNORM', + 'IMG_NUM_FORMAT_UBNORM_NZ', 'IMG_NUM_FORMAT_UBSCALED', + 'IMG_NUM_FORMAT_UINT', 'IMG_NUM_FORMAT_UNORM', + 'IMG_NUM_FORMAT_USCALED', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_INNER_COVERAGE', + 'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG', + 'INST_ID_HW_TRAP', 'INST_ID_KILL_SEQ', 'INST_ID_PRIV_START', + 'INST_ID_SPI_WREXEC', 'INST_ID_TTRACE_NEW_PC_MSG', + 'INTERRUPT_LINE_ASSERTED', 'INTERRUPT_LINE_NOT_ASSERTED', + 'INT_DISABLED', 'INT_ENABLED', 'INT_LEVEL', 'INT_MASK', + 'INT_PULSE', 'INVALID_REG_ACCESS_TYPE', 'IP_USB_PD_REVISION_ID', + 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', + 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', + 'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'JITTER_REMOVE_DISABLE', + 'LATE_Z', 'LB_ALPHA_DISABLE', 'LB_ALPHA_EN', 'LB_ALPHA_ENABLE', + 'LB_INTERLEAVE_DISABLE', 'LB_INTERLEAVE_EN', + 'LB_INTERLEAVE_ENABLE', 'LEFT_EYE', 'LEGACY_NUM_BANKS', + 'LEGACY_PIPE_INTERLEAVE', 'LEGACY_PIPE_INTERLEAVE_256B', + 'LEGACY_PIPE_INTERLEAVE_512B', 'LINESTRIP', 'LS_STAGE_OFF', + 'LS_STAGE_ON', 'LUT_2CFG_MEMORY_A', 'LUT_2CFG_MEMORY_B', + 'LUT_2CFG_NO_MEMORY', 'LUT_2_MODE_BYPASS', 'LUT_2_MODE_RAMA_LUT', + 'LUT_2_MODE_RAMB_LUT', 'LUT_4CFG_MEMORY_A', 'LUT_4CFG_MEMORY_B', + 'LUT_4CFG_NO_MEMORY', 'LUT_4CFG_ROM_A', 'LUT_4CFG_ROM_B', + 'LUT_4_MODE_BYPASS', 'LUT_4_MODE_RAMA_LUT', 'LUT_4_MODE_RAMB_LUT', + 'LUT_4_MODE_ROMA_LUT', 'LUT_4_MODE_ROMB_LUT', + 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', + 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', 'MACRO_TILE_ASPECT', + 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', + 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', + 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', + 'MASTER_UPDATE_LOCK_SEL', 'MASTER_UPDATE_LOCK_SEL_0', + 'MASTER_UPDATE_LOCK_SEL_1', 'MASTER_UPDATE_LOCK_SEL_2', + 'MASTER_UPDATE_LOCK_SEL_3', 'MASTER_UPDATE_LOCK_SEL_4', + 'MASTER_UPDATE_LOCK_SEL_5', + 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK', + 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE', + 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', + 'MAX_COMPRESSED_FRAGS', 'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH', + 'MEM_ARB_MODE_FIXED', 'MEM_ARB_MODE_WEIGHT', 'MEM_PWR_DIS_CTRL', + 'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2', 'MEM_PWR_SEL_CTRL', + 'MEM_PWR_SEL_CTRL2', 'METADATA_HUBP_SEL', 'METADATA_HUBP_SEL_0', + 'METADATA_HUBP_SEL_1', 'METADATA_HUBP_SEL_2', + 'METADATA_HUBP_SEL_3', 'METADATA_HUBP_SEL_4', + 'METADATA_HUBP_SEL_5', 'METADATA_HUBP_SEL_RESERVED', + 'METADATA_STREAM_DP', 'METADATA_STREAM_DVE', + 'METADATA_STREAM_TYPE_SEL', 'META_CHUNK_SIZE', + 'META_CHUNK_SIZE_1KB', 'META_CHUNK_SIZE_2KB', + 'META_CHUNK_SIZE_4KB', 'META_CHUNK_SIZE_8KB', 'META_LINEAR', + 'META_SURF_LINEAR', 'META_SURF_TILED', 'ME_ID0', 'ME_ID1', + 'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', + 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', + 'MICRO_TILE_MODE_DISPLAY_2D', 'MICRO_TILE_MODE_DISPLAY_3D', + 'MICRO_TILE_MODE_LINEAR', 'MICRO_TILE_MODE_NEW', + 'MICRO_TILE_MODE_RENDER_TARGET', 'MICRO_TILE_MODE_STD_2D', + 'MICRO_TILE_MODE_STD_3D', 'MICRO_TILE_MODE_Z', + 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', + 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MIN_CHUNK_SIZE', + 'MIN_CHUNK_SIZE_1024B', 'MIN_CHUNK_SIZE_256B', + 'MIN_CHUNK_SIZE_512B', 'MIN_META_CHUNK_SIZE', + 'MIN_META_CHUNK_SIZE_128B', 'MIN_META_CHUNK_SIZE_256B', + 'MIN_META_CHUNK_SIZE_64B', 'MMHUBBUB_XFC_FRAME_MODE_ENUM', + 'MMHUBBUB_XFC_FULL_FRAME_MODE', 'MMHUBBUB_XFC_PARTIAL_FRAME_MODE', + 'MMHUBBUB_XFC_PIXEL_FORMAT_ENUM', 'MMHUBBUB_XFC_PIXEL_IS_32BPP', + 'MMHUBBUB_XFC_PIXEL_IS_64BPP', + 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM', + 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB', + 'MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB', + 'MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS', + 'MMHUBBUB_XFC_XFCMON_MODE_ENUM', + 'MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT', + 'MMHUBBUB_XFC_XFCMON_MODE_PERIODS', 'MONO_10LSB', 'MONO_10MSB', + 'MONO_12LSB', 'MONO_12MSB', 'MONO_16', 'MONO_2BIT', 'MONO_8', + 'MPCC_BG_COLOR_BPC', 'MPCC_BG_COLOR_BPC_10bit', + 'MPCC_BG_COLOR_BPC_11bit', 'MPCC_BG_COLOR_BPC_12bit', + 'MPCC_BG_COLOR_BPC_8bit', 'MPCC_BG_COLOR_BPC_9bit', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', 'MPCC_CONTROL_MPCC_MODE', + 'MPCC_CONTROL_MPCC_MODE_BYPASS', + 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', + 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', + 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', + 'MPCC_OGAM_MODE_0', 'MPCC_OGAM_MODE_1', 'MPCC_OGAM_MODE_2', + 'MPCC_OGAM_MODE_MPCC_OGAM_MODE', 'MPCC_OGAM_MODE_RSV', + 'MPCC_SM_CONTROL_MPCC_SM_EN', 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_MODE', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', + 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK', + 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE', + 'MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE', + 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK', + 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE', + 'MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', 'MPC_CFG_MPC_TEST_CLK_SEL', + 'MPC_CFG_MPC_TEST_CLK_SEL_0', 'MPC_CFG_MPC_TEST_CLK_SEL_1', + 'MPC_CFG_MPC_TEST_CLK_SEL_2', 'MPC_CFG_MPC_TEST_CLK_SEL_3', + 'MPC_CRC_CALC_INTERLACE_MODE', 'MPC_CRC_CALC_MODE', + 'MPC_CRC_CALC_STEREO_MODE', 'MPC_CRC_CONTINUOUS_MODE', + 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', + 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', + 'MPC_CRC_INTERLACE_MODE_BOTTOM', 'MPC_CRC_INTERLACE_MODE_TOP', + 'MPC_CRC_ONE_SHOT_MODE', 'MPC_CRC_SOURCE_SELECT', + 'MPC_CRC_SOURCE_SEL_DPP', 'MPC_CRC_SOURCE_SEL_DWB', + 'MPC_CRC_SOURCE_SEL_OPP', 'MPC_CRC_SOURCE_SEL_OTHER', + 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', + 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', + 'MPC_CRC_STEREO_MODE_LEFT', 'MPC_CRC_STEREO_MODE_RIGHT', + 'MPC_OCSC_COEF_FORMAT', 'MPC_OCSC_COEF_FORMAT_S2_13', + 'MPC_OCSC_COEF_FORMAT_S3_12', 'MPC_OUT_CSC_MODE', + 'MPC_OUT_CSC_MODE_0', 'MPC_OUT_CSC_MODE_1', 'MPC_OUT_CSC_MODE_2', + 'MPC_OUT_CSC_MODE_RSV', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', + 'MPC_OUT_RATE_CONTROL_DISABLE_SET', + 'MPC_OUT_RATE_CONTROL_SET_DISABLE', + 'MPC_OUT_RATE_CONTROL_SET_ENABLE', 'MPTE_GROUP_SIZE', + 'MPTE_GROUP_SIZE_1024B', 'MPTE_GROUP_SIZE_128B', + 'MPTE_GROUP_SIZE_2048B', 'MPTE_GROUP_SIZE_256B', + 'MPTE_GROUP_SIZE_4096B', 'MPTE_GROUP_SIZE_512B', + 'MPTE_GROUP_SIZE_64B', 'MPTE_GROUP_SIZE_8192B', + 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', + 'MTYPE', 'MTYPE_CC', 'MTYPE_C_RO_S', 'MTYPE_C_RO_US', + 'MTYPE_C_RW_S', 'MTYPE_C_RW_US', 'MTYPE_NC', 'MTYPE_RESERVED_1', + 'MTYPE_RESERVED_5', 'MTYPE_RESERVED_7', 'MTYPE_UC', 'MTYPE_WC', + 'MULT_16', 'MULT_8', 'MacroTileAspect', 'MemArbMode', + 'MicroTileMode', 'MultiGPUTileSize', 'NON_BYPASS', 'NOT_SENT', + 'NO_DIST', 'NO_DIV', 'NO_FORCE', 'NO_FORCE_REQ', + 'NO_FORCE_REQUEST', 'NO_MIN_CHUNK_SIZE', 'NO_MIN_META_CHUNK_SIZE', + 'NO_OUTSTANDING_REQ', 'NUMBER_FLOAT', 'NUMBER_SINT', + 'NUMBER_SNORM', 'NUMBER_SRGB', 'NUMBER_SSCALED', 'NUMBER_UINT', + 'NUMBER_UNORM', 'NUMBER_USCALED', 'NUM_BANKS', + 'NUM_BANKS_BC_ENUM', 'NUM_PIPES', 'NUM_PIPES_BC_ENUM', + 'NUM_RB_PER_SE', 'NUM_SE', 'NUM_SIMD_PER_CU', + 'NonDispTilingOrder', 'NumBanks', 'NumBanksConfig', 'NumGPUs', + 'NumLowerPipes', 'NumMaxCompressedFragments', 'NumPipes', + 'NumRbPerShaderEngine', 'NumShaderEngines', 'OBUF_BYPASS_DIS', + 'OBUF_BYPASS_EN', 'OBUF_BYPASS_SEL', 'OBUF_FULL', + 'OBUF_FULL_RECOUT', 'OBUF_HALF_RECOUT', + 'OBUF_IS_HALF_RECOUT_WIDTH_SEL', 'OBUF_RECOUT', + 'OBUF_USE_FULL_BUFFER_SEL', 'OFFCHIP_HS_DEALLOC', 'OFF_SEQ', + 'ONE_BANK', 'ONE_FRAGMENT', 'ONE_PIPE', 'ONE_RB_PER_SE', + 'ONE_SHADER_ENGIN', 'ON_SEQ', 'OPP_PIPE_CLOCK_DISABLE', + 'OPP_PIPE_CLOCK_ENABLE', 'OPP_PIPE_CLOCK_ENABLE_CONTROL', + 'OPP_PIPE_CRC_CONT_EN', 'OPP_PIPE_CRC_DISABLE', 'OPP_PIPE_CRC_EN', + 'OPP_PIPE_CRC_ENABLE', 'OPP_PIPE_CRC_INTERLACE_EN', + 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', + 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', + 'OPP_PIPE_CRC_INTERLACE_MODE', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', + 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', 'OPP_PIPE_CRC_MODE_CONTINUOUS', + 'OPP_PIPE_CRC_MODE_ONE_SHOT', 'OPP_PIPE_CRC_ONE_SHOT_PENDING', + 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', + 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', + 'OPP_PIPE_CRC_PIXEL_SELECT', + 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', + 'OPP_PIPE_CRC_SOURCE_SELECT', 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', + 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', 'OPP_PIPE_CRC_STEREO_EN', + 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', + 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', + 'OPP_PIPE_CRC_STEREO_MODE', + 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', + 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', + 'OPP_PIPE_CRC_STEREO_MODE_LEFT', 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', + 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL', + 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', + 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', 'OPP_TEST_CLK_SEL_CONTROL', + 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', + 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', + 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', 'OPP_TEST_CLK_SEL_DISPCLK_OPP4', + 'OPP_TEST_CLK_SEL_DISPCLK_OPP5', 'OPP_TEST_CLK_SEL_DISPCLK_P', + 'OPP_TEST_CLK_SEL_DISPCLK_R', 'OPP_TEST_CLK_SEL_RESERVED0', + 'OPP_TOP_CLOCK_DISABLED_STATUS', 'OPP_TOP_CLOCK_ENABLED_STATUS', + 'OPP_TOP_CLOCK_ENABLE_STATUS', 'OPP_TOP_CLOCK_GATING_CONTROL', + 'OPP_TOP_CLOCK_GATING_DISABLED', 'OPP_TOP_CLOCK_GATING_ENABLED', + 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX', + 'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT', + 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', + 'OTG_ADD_PIXEL', 'OTG_ADD_PIXEL_FORCE', 'OTG_ADD_PIXEL_NOOP', + 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN', + 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE', + 'OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE', + 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE', + 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE', + 'OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED', + 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE', + 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE', + 'OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', + 'OTG_CONTROL_OTG_MASTER_EN', 'OTG_CONTROL_OTG_MASTER_EN_FALSE', + 'OTG_CONTROL_OTG_MASTER_EN_TRUE', 'OTG_CONTROL_OTG_SOF_PULL_EN', + 'OTG_CONTROL_OTG_SOF_PULL_EN_FALSE', + 'OTG_CONTROL_OTG_SOF_PULL_EN_TRUE', + 'OTG_CONTROL_OTG_START_POINT_CNTL', + 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', + 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3', + 'OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE', + 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE', + 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE', + 'OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_EN', + 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', 'OTG_CRC_CNTL_OTG_CRC_EN', + 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', + 'OTG_DROP_PIXEL', 'OTG_DROP_PIXEL_FORCE', 'OTG_DROP_PIXEL_NOOP', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE', + 'OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE', + 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR', + 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE', + 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE', + 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE', + 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE', + 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE', + 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE', + 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE', + 'OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE', + 'OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE', + 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR', + 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE', + 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE', + 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE', + 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE', + 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE', + 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE', + 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE', + 'OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE', + 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT', + 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE', + 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE', + 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY', + 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE', + 'OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5', + 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD', + 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL', + 'OTG_GSL_MASTER_MODE', 'OTG_GSL_MASTER_MODE_0', + 'OTG_GSL_MASTER_MODE_1', 'OTG_GSL_MASTER_MODE_2', + 'OTG_GSL_MASTER_MODE_3', 'OTG_HORZ_REPETITION_COUNT', + 'OTG_HORZ_REPETITION_COUNT_0', 'OTG_HORZ_REPETITION_COUNT_1', + 'OTG_HORZ_REPETITION_COUNT_10', 'OTG_HORZ_REPETITION_COUNT_11', + 'OTG_HORZ_REPETITION_COUNT_12', 'OTG_HORZ_REPETITION_COUNT_13', + 'OTG_HORZ_REPETITION_COUNT_14', 'OTG_HORZ_REPETITION_COUNT_15', + 'OTG_HORZ_REPETITION_COUNT_2', 'OTG_HORZ_REPETITION_COUNT_3', + 'OTG_HORZ_REPETITION_COUNT_4', 'OTG_HORZ_REPETITION_COUNT_5', + 'OTG_HORZ_REPETITION_COUNT_6', 'OTG_HORZ_REPETITION_COUNT_7', + 'OTG_HORZ_REPETITION_COUNT_8', 'OTG_HORZ_REPETITION_COUNT_9', + 'OTG_H_SYNC_A_POL', 'OTG_H_SYNC_A_POL_HIGH', + 'OTG_H_SYNC_A_POL_LOW', 'OTG_H_TIMING_DIV_BY2', + 'OTG_H_TIMING_DIV_BY2_FALSE', 'OTG_H_TIMING_DIV_BY2_TRUE', + 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE', + 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0', + 'OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', + 'OTG_MASTER_UPDATE_LOCK_GSL_EN', + 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', + 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', + 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE', + 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG', + 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE', + 'OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL', + 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR', + 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE', + 'OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE', + 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR', + 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE', + 'OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE', 'OTG_PIPE_ABORT', + 'OTG_PIPE_ABORT_0', 'OTG_PIPE_ABORT_1', + 'OTG_PTI_CONTROL_OTG_PIT_EN', 'OTG_PTI_CONTROL_OTG_PIT_EN_FALSE', + 'OTG_PTI_CONTROL_OTG_PIT_EN_TRUE', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', + 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY', + 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE', + 'OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE', + 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN', + 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE', + 'OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE', + 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN', + 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE', + 'OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE', + 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY', + 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE', + 'OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGA_FREQUENCY_SELECT', 'OTG_TRIGA_FREQUENCY_SELECT_0', + 'OTG_TRIGA_FREQUENCY_SELECT_1', 'OTG_TRIGA_FREQUENCY_SELECT_2', + 'OTG_TRIGA_FREQUENCY_SELECT_3', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGB_FREQUENCY_SELECT', 'OTG_TRIGB_FREQUENCY_SELECT_0', + 'OTG_TRIGB_FREQUENCY_SELECT_1', 'OTG_TRIGB_FREQUENCY_SELECT_2', + 'OTG_TRIGB_FREQUENCY_SELECT_3', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', + 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE', + 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE', + 'OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', + 'OTG_V_SYNC_A_POL', 'OTG_V_SYNC_A_POL_HIGH', + 'OTG_V_SYNC_A_POL_LOW', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', + 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN', + 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE', + 'OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE', + 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR', + 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE', + 'OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE', + 'OUTPUT_LINE', 'OUTPUT_POINT', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OUTSTANDING_REQ', + 'OVERRUN', 'P16_32x32_16x16', 'P16_32x32_8x16', 'P16_ADDR_SURF', + 'P2', 'P4_16x16', 'P4_16x32', 'P4_32x32', 'P4_8x16', + 'P8_16x16_8x16', 'P8_16x32_16x16', 'P8_16x32_8x16', + 'P8_32x32_16x16', 'P8_32x32_16x32', 'P8_32x32_8x16', + 'P8_32x64_32x32', 'PART_FRAC_EVEN', 'PART_FRAC_ODD', + 'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PERFCOUNTER_ACTIVE', + 'PERFCOUNTER_CNT0_STATE', 'PERFCOUNTER_CNT0_STATE_FREEZE', + 'PERFCOUNTER_CNT0_STATE_HW', 'PERFCOUNTER_CNT0_STATE_RESET', + 'PERFCOUNTER_CNT0_STATE_START', 'PERFCOUNTER_CNT1_STATE', + 'PERFCOUNTER_CNT1_STATE_FREEZE', 'PERFCOUNTER_CNT1_STATE_HW', + 'PERFCOUNTER_CNT1_STATE_RESET', 'PERFCOUNTER_CNT1_STATE_START', + 'PERFCOUNTER_CNT2_STATE', 'PERFCOUNTER_CNT2_STATE_FREEZE', + 'PERFCOUNTER_CNT2_STATE_HW', 'PERFCOUNTER_CNT2_STATE_RESET', + 'PERFCOUNTER_CNT2_STATE_START', 'PERFCOUNTER_CNT3_STATE', + 'PERFCOUNTER_CNT3_STATE_FREEZE', 'PERFCOUNTER_CNT3_STATE_HW', + 'PERFCOUNTER_CNT3_STATE_RESET', 'PERFCOUNTER_CNT3_STATE_START', + 'PERFCOUNTER_CNT4_STATE', 'PERFCOUNTER_CNT4_STATE_FREEZE', + 'PERFCOUNTER_CNT4_STATE_HW', 'PERFCOUNTER_CNT4_STATE_RESET', + 'PERFCOUNTER_CNT4_STATE_START', 'PERFCOUNTER_CNT5_STATE', + 'PERFCOUNTER_CNT5_STATE_FREEZE', 'PERFCOUNTER_CNT5_STATE_HW', + 'PERFCOUNTER_CNT5_STATE_RESET', 'PERFCOUNTER_CNT5_STATE_START', + 'PERFCOUNTER_CNT6_STATE', 'PERFCOUNTER_CNT6_STATE_FREEZE', + 'PERFCOUNTER_CNT6_STATE_HW', 'PERFCOUNTER_CNT6_STATE_RESET', + 'PERFCOUNTER_CNT6_STATE_START', 'PERFCOUNTER_CNT7_STATE', + 'PERFCOUNTER_CNT7_STATE_FREEZE', 'PERFCOUNTER_CNT7_STATE_HW', + 'PERFCOUNTER_CNT7_STATE_RESET', 'PERFCOUNTER_CNT7_STATE_START', + 'PERFCOUNTER_CNTL_SEL', 'PERFCOUNTER_CNTL_SEL_0', + 'PERFCOUNTER_CNTL_SEL_1', 'PERFCOUNTER_CNTL_SEL_2', + 'PERFCOUNTER_CNTL_SEL_3', 'PERFCOUNTER_CNTL_SEL_4', + 'PERFCOUNTER_CNTL_SEL_5', 'PERFCOUNTER_CNTL_SEL_6', + 'PERFCOUNTER_CNTL_SEL_7', 'PERFCOUNTER_CNTOFF_START_DIS', + 'PERFCOUNTER_CNTOFF_START_DISABLE', + 'PERFCOUNTER_CNTOFF_START_ENABLE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', + 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', + 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', + 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', + 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', + 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', + 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_HW_STOP1_0', + 'PERFCOUNTER_HW_STOP1_1', 'PERFCOUNTER_HW_STOP1_SEL', + 'PERFCOUNTER_HW_STOP2_0', 'PERFCOUNTER_HW_STOP2_1', + 'PERFCOUNTER_HW_STOP2_SEL', 'PERFCOUNTER_INC_MODE', + 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', + 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', + 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', + 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', + 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', + 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', + 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', + 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', + 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', + 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', + 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', + 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', + 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', + 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', + 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', + 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', + 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', + 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', + 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', + 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', + 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', + 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', + 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', + 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', + 'PERFMON_COUNTER_MODE_ACCUM', + 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 'PERFMON_COUNTER_MODE_DIRTY', + 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', + 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', + 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', + 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', + 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', + 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', + 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', + 'PERFMON_STATE_START', 'PERF_CLIENT_UTCL1_INFLIGHT', + 'PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE', + 'PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE', + 'PERF_INDEX_RECEIVE_QUALIFIED_BUSY', + 'PERF_INDEX_RECEIVE_QUALIFIED_STARVED', + 'PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO', + 'PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE', + 'PERF_INDEX_REQUEST_QUALIFIED_BUSY', + 'PERF_INDEX_REQUEST_QUALIFIED_STARVED', + 'PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO', + 'PERF_INDEX_REQUEST_WAITING_ON_TOKENS', 'PERF_PAPC_CCGSM_BUSY', + 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', + 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', + 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', + 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', + 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', + 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', + 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', + 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', + 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', + 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE', + 'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR', + 'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE', + 'PERF_PAPC_PASX_REC_STALLED', + 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', + 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', + 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', + 'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', + 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ', + 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD', + 'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 'PERF_PAPC_PA_INPUT_END_OF_PACKET', + 'PERF_PAPC_PA_INPUT_EVENT_FLAG', + 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', + 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM', + 'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM', + 'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', + 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', + 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', + 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE01_STALLED_SC', + 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE0_STALLED_SC', + 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE1_STALLED_SC', + 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE2_STALLED_SC', + 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', + 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 'PERF_PAWD_DEALLOC_FIFO_IS_FULL', + 'PERF_PAWD_DEALLOC_WAITING_TO_BE_READ', + 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', + 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', + 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', + 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', + 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', + 'PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', + 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', + 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', + 'PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', + 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', + 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', + 'PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', + 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND', + 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND', + 'PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED', + 'PERF_PA_VERTEX_FIFO_FULL', + 'PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', + 'PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE', + 'PERF_POS_REQ_QUALIFIED_BUSY', 'PERF_POS_REQ_QUALIFIED_STARVED', + 'PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM', + 'PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM', + 'PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM', + 'PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM', + 'PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', + 'PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', + 'PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO', + 'PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO', + 'PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO', + 'PERF_POS_REQ_STALLED_BY_NO_TOKENS', + 'PERF_POS_REQ_STALLED_BY_UTCL1', + 'PERF_POS_REQ_STARVED_BY_NO_PRIM', + 'PERF_POS_RET_1_CACHELINE_POSITION_USED', + 'PERF_POS_RET_2_CACHELINE_POSITION_USED', + 'PERF_POS_RET_3_CACHELINE_POSITION_USED', + 'PERF_POS_RET_4_CACHELINE_POSITION_USED', + 'PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE', + 'PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO', + 'PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO', + 'PERF_POS_RET_QUALIFIED_BUSY', 'PERF_POS_RET_QUALIFIED_STARVED', + 'PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE', + 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SHOOTDOWN_WAIT_ALL_CLEAN', 'PERF_SHOOTDOWN_WAIT_DEASSERT', + 'PERF_SHOOTDOWN_WAIT_ON_UTCL1', + 'PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX', + 'PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION', + 'PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND', + 'PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_', + 'PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_', + 'PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_', + 'PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_', + 'PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD', + 'PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD', + 'PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD', + 'PERF_SIDEBAND_FIFO_VMID_FIFO_FULL', + 'PERF_SIDEBAND_INVALID_REFETCH', + 'PERF_SIDEBAND_POP_BIT_FIFO_FULL', 'PERF_SIDEBAND_QUALIFIED_BUSY', + 'PERF_SIDEBAND_QUALIFIED_STARVED', + 'PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY', + 'PERF_SIDEBAND_WAITING_ON_RETURNED_DATA', + 'PERF_SIDEBAND_WAITING_ON_UTCL1', 'PERF_SMALL_PRIM_CULL_PRIM_1X1', + 'PERF_SMALL_PRIM_CULL_PRIM_1X2', 'PERF_SMALL_PRIM_CULL_PRIM_1X3', + 'PERF_SMALL_PRIM_CULL_PRIM_1XN', 'PERF_SMALL_PRIM_CULL_PRIM_2X1', + 'PERF_SMALL_PRIM_CULL_PRIM_2X2', 'PERF_SMALL_PRIM_CULL_PRIM_2X3', + 'PERF_SMALL_PRIM_CULL_PRIM_2XN', 'PERF_SMALL_PRIM_CULL_PRIM_3X1', + 'PERF_SMALL_PRIM_CULL_PRIM_3X2', + 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', + 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', + 'PERF_SMALL_PRIM_CULL_PRIM_NX1', 'PERF_SMALL_PRIM_CULL_PRIM_NX2', + 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', + 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', 'PERF_TCIF_BUSY', + 'PERF_TCIF_INDEX_RDREQ', 'PERF_TCIF_POSITION_RDREQ', + 'PERF_TCIF_SIDEBAND_RDREQ', + 'PERF_TCIF_STALLING_CLIENT_NO_CREDITS', + 'PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE', + 'PERF_TC_INDEX_LATENCY_BIN0', 'PERF_TC_INDEX_LATENCY_BIN1', + 'PERF_TC_INDEX_LATENCY_BIN10', 'PERF_TC_INDEX_LATENCY_BIN11', + 'PERF_TC_INDEX_LATENCY_BIN12', 'PERF_TC_INDEX_LATENCY_BIN13', + 'PERF_TC_INDEX_LATENCY_BIN14', 'PERF_TC_INDEX_LATENCY_BIN15', + 'PERF_TC_INDEX_LATENCY_BIN2', 'PERF_TC_INDEX_LATENCY_BIN3', + 'PERF_TC_INDEX_LATENCY_BIN4', 'PERF_TC_INDEX_LATENCY_BIN5', + 'PERF_TC_INDEX_LATENCY_BIN6', 'PERF_TC_INDEX_LATENCY_BIN7', + 'PERF_TC_INDEX_LATENCY_BIN8', 'PERF_TC_INDEX_LATENCY_BIN9', + 'PERF_TC_POSITION_LATENCY_BIN0', 'PERF_TC_POSITION_LATENCY_BIN1', + 'PERF_TC_POSITION_LATENCY_BIN10', + 'PERF_TC_POSITION_LATENCY_BIN11', + 'PERF_TC_POSITION_LATENCY_BIN12', + 'PERF_TC_POSITION_LATENCY_BIN13', + 'PERF_TC_POSITION_LATENCY_BIN14', + 'PERF_TC_POSITION_LATENCY_BIN15', 'PERF_TC_POSITION_LATENCY_BIN2', + 'PERF_TC_POSITION_LATENCY_BIN3', 'PERF_TC_POSITION_LATENCY_BIN4', + 'PERF_TC_POSITION_LATENCY_BIN5', 'PERF_TC_POSITION_LATENCY_BIN6', + 'PERF_TC_POSITION_LATENCY_BIN7', 'PERF_TC_POSITION_LATENCY_BIN8', + 'PERF_TC_POSITION_LATENCY_BIN9', 'PERF_TC_STREAM0_DATA_AVAILABLE', + 'PERF_TC_STREAM1_DATA_AVAILABLE', + 'PERF_TC_STREAM2_DATA_AVAILABLE', 'PERF_UTCL1_LFIFO_FULL', + 'PERF_UTCL1_PERMISSION_MISS_CLIENT0', + 'PERF_UTCL1_PERMISSION_MISS_CLIENT1', + 'PERF_UTCL1_PERMISSION_MISS_CLIENT2', + 'PERF_UTCL1_REQUEST_CLIENT0', 'PERF_UTCL1_REQUEST_CLIENT1', + 'PERF_UTCL1_REQUEST_CLIENT2', 'PERF_UTCL1_STALL_INFLIGHT_MAX', + 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0', + 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1', + 'PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2', + 'PERF_UTCL1_STALL_LRU_INFLIGHT', 'PERF_UTCL1_STALL_MISSFIFO_FULL', + 'PERF_UTCL1_STALL_MULTI_MISS', + 'PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 'PERF_UTCL1_TRANSLATION_HIT_CLIENT0', + 'PERF_UTCL1_TRANSLATION_HIT_CLIENT1', + 'PERF_UTCL1_TRANSLATION_HIT_CLIENT2', + 'PERF_UTCL1_TRANSLATION_MISS_CLIENT0', + 'PERF_UTCL1_TRANSLATION_MISS_CLIENT1', + 'PERF_UTCL1_TRANSLATION_MISS_CLIENT2', + 'PERF_UTCL1_UTCL2_INFLIGHT', 'PERF_UTCL1_UTCL2_REQ', + 'PERF_UTCL1_UTCL2_RET', 'PERF_UTC_INDEX_DRIVER_BUSY', + 'PERF_UTC_INDEX_DRIVER_STALLING_CLIENT', + 'PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1', + 'PERF_UTC_INDEX_RECEIVER_BUSY', + 'PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER', + 'PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1', + 'PERF_UTC_POSITION_DRIVER_BUSY', + 'PERF_UTC_POSITION_DRIVER_STALLING_CLIENT', + 'PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1', + 'PERF_UTC_POSITION_RECEIVER_BUSY', + 'PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER', + 'PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1', + 'PERF_UTC_SIDEBAND_DRIVER_BUSY', + 'PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT', + 'PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1', + 'PERF_UTC_SIDEBAND_RECEIVER_BUSY', + 'PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER', + 'PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1', + 'PERF_WRITING_TO_SIDEBAND_MEMORY', 'PERSISTENT_SPACE_END', + 'PERSISTENT_SPACE_START', 'PH_PERFCNT_SEL', 'PH_SC0_ARB_BUSY', + 'PH_SC0_ARB_EOP_POP_SYNC_POP', 'PH_SC0_ARB_EVENT_SYNC_POP', + 'PH_SC0_ARB_PA_BUSY_SOP', 'PH_SC0_ARB_STALLED_FROM_BELOW', + 'PH_SC0_ARB_STARVED_FROM_ABOVE', + 'PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC0_BUSY_CNT_NOT_ZERO', + 'PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC0_CREDIT_AT_MAX', + 'PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_SC0_EOP_SYNC_WINDOW', 'PH_SC0_GFX_PIPE0_TO_1_TRANSITION', + 'PH_SC0_GFX_PIPE1_TO_0_TRANSITION', + 'PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', + 'PH_SC0_PA0_DATA_FIFO_EOP_RD', 'PH_SC0_PA0_DATA_FIFO_RD', + 'PH_SC0_PA0_DATA_FIFO_WE', 'PH_SC0_PA0_DEALLOC_4_0_RD', + 'PH_SC0_PA0_EOPG_WE', 'PH_SC0_PA0_EOP_WE', 'PH_SC0_PA0_EVENT_WE', + 'PH_SC0_PA0_FIFO_EMPTY', 'PH_SC0_PA0_FIFO_FULL', + 'PH_SC0_PA0_FPOV_WE', 'PH_SC0_PA0_LPOV_WE', 'PH_SC0_PA0_NULL_WE', + 'PH_SC0_PA1_DATA_FIFO_EOP_RD', 'PH_SC0_PA1_DATA_FIFO_RD', + 'PH_SC0_PA1_DATA_FIFO_WE', 'PH_SC0_PA1_DEALLOC_4_0_RD', + 'PH_SC0_PA1_EOPG_WE', 'PH_SC0_PA1_EOP_WE', 'PH_SC0_PA1_EVENT_WE', + 'PH_SC0_PA1_FIFO_EMPTY', 'PH_SC0_PA1_FIFO_FULL', + 'PH_SC0_PA1_FPOV_WE', 'PH_SC0_PA1_LPOV_WE', 'PH_SC0_PA1_NULL_WE', + 'PH_SC0_PA2_DATA_FIFO_EOP_RD', 'PH_SC0_PA2_DATA_FIFO_RD', + 'PH_SC0_PA2_DATA_FIFO_WE', 'PH_SC0_PA2_DEALLOC_4_0_RD', + 'PH_SC0_PA2_EOPG_WE', 'PH_SC0_PA2_EOP_WE', 'PH_SC0_PA2_EVENT_WE', + 'PH_SC0_PA2_FIFO_EMPTY', 'PH_SC0_PA2_FIFO_FULL', + 'PH_SC0_PA2_FPOV_WE', 'PH_SC0_PA2_LPOV_WE', 'PH_SC0_PA2_NULL_WE', + 'PH_SC0_PA3_DATA_FIFO_EOP_RD', 'PH_SC0_PA3_DATA_FIFO_RD', + 'PH_SC0_PA3_DATA_FIFO_WE', 'PH_SC0_PA3_DEALLOC_4_0_RD', + 'PH_SC0_PA3_EOPG_WE', 'PH_SC0_PA3_EOP_WE', 'PH_SC0_PA3_EVENT_WE', + 'PH_SC0_PA3_FIFO_EMPTY', 'PH_SC0_PA3_FIFO_FULL', + 'PH_SC0_PA3_FPOV_WE', 'PH_SC0_PA3_LPOV_WE', 'PH_SC0_PA3_NULL_WE', + 'PH_SC0_PA4_DATA_FIFO_EOP_RD', 'PH_SC0_PA4_DATA_FIFO_RD', + 'PH_SC0_PA4_DATA_FIFO_WE', 'PH_SC0_PA4_DEALLOC_4_0_RD', + 'PH_SC0_PA4_EOPG_WE', 'PH_SC0_PA4_EOP_WE', 'PH_SC0_PA4_EVENT_WE', + 'PH_SC0_PA4_FIFO_EMPTY', 'PH_SC0_PA4_FIFO_FULL', + 'PH_SC0_PA4_FPOV_WE', 'PH_SC0_PA4_LPOV_WE', 'PH_SC0_PA4_NULL_WE', + 'PH_SC0_PA5_DATA_FIFO_EOP_RD', 'PH_SC0_PA5_DATA_FIFO_RD', + 'PH_SC0_PA5_DATA_FIFO_WE', 'PH_SC0_PA5_DEALLOC_4_0_RD', + 'PH_SC0_PA5_EOPG_WE', 'PH_SC0_PA5_EOP_WE', 'PH_SC0_PA5_EVENT_WE', + 'PH_SC0_PA5_FIFO_EMPTY', 'PH_SC0_PA5_FIFO_FULL', + 'PH_SC0_PA5_FPOV_WE', 'PH_SC0_PA5_LPOV_WE', 'PH_SC0_PA5_NULL_WE', + 'PH_SC0_PA6_DATA_FIFO_EOP_RD', 'PH_SC0_PA6_DATA_FIFO_RD', + 'PH_SC0_PA6_DATA_FIFO_WE', 'PH_SC0_PA6_DEALLOC_4_0_RD', + 'PH_SC0_PA6_EOPG_WE', 'PH_SC0_PA6_EOP_WE', 'PH_SC0_PA6_EVENT_WE', + 'PH_SC0_PA6_FIFO_EMPTY', 'PH_SC0_PA6_FIFO_FULL', + 'PH_SC0_PA6_FPOV_WE', 'PH_SC0_PA6_LPOV_WE', 'PH_SC0_PA6_NULL_WE', + 'PH_SC0_PA7_DATA_FIFO_EOP_RD', 'PH_SC0_PA7_DATA_FIFO_RD', + 'PH_SC0_PA7_DATA_FIFO_WE', 'PH_SC0_PA7_DEALLOC_4_0_RD', + 'PH_SC0_PA7_EOPG_WE', 'PH_SC0_PA7_EOP_WE', 'PH_SC0_PA7_EVENT_WE', + 'PH_SC0_PA7_FIFO_EMPTY', 'PH_SC0_PA7_FIFO_FULL', + 'PH_SC0_PA7_FPOV_WE', 'PH_SC0_PA7_LPOV_WE', 'PH_SC0_PA7_NULL_WE', + 'PH_SC0_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC0_SEND', + 'PH_SC0_SRPS_WINDOW_VALID', 'PH_SC1_ARB_BUSY', + 'PH_SC1_ARB_EOP_POP_SYNC_POP', 'PH_SC1_ARB_EVENT_SYNC_POP', + 'PH_SC1_ARB_PA_BUSY_SOP', 'PH_SC1_ARB_STALLED_FROM_BELOW', + 'PH_SC1_ARB_STARVED_FROM_ABOVE', + 'PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC1_BUSY_CNT_NOT_ZERO', + 'PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC1_CREDIT_AT_MAX', + 'PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_SC1_EOP_SYNC_WINDOW', 'PH_SC1_GFX_PIPE0_TO_1_TRANSITION', + 'PH_SC1_GFX_PIPE1_TO_0_TRANSITION', + 'PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_SC1_PA0_DATA_FIFO_EOP_RD', 'PH_SC1_PA0_DATA_FIFO_RD', + 'PH_SC1_PA0_DATA_FIFO_WE', 'PH_SC1_PA0_DEALLOC_4_0_RD', + 'PH_SC1_PA0_EOPG_WE', 'PH_SC1_PA0_EOP_WE', 'PH_SC1_PA0_EVENT_WE', + 'PH_SC1_PA0_FIFO_EMPTY', 'PH_SC1_PA0_FIFO_FULL', + 'PH_SC1_PA0_FPOV_WE', 'PH_SC1_PA0_LPOV_WE', 'PH_SC1_PA0_NULL_WE', + 'PH_SC1_PA1_DATA_FIFO_EOP_RD', 'PH_SC1_PA1_DATA_FIFO_RD', + 'PH_SC1_PA1_DATA_FIFO_WE', 'PH_SC1_PA1_DEALLOC_4_0_RD', + 'PH_SC1_PA1_EOPG_WE', 'PH_SC1_PA1_EOP_WE', 'PH_SC1_PA1_EVENT_WE', + 'PH_SC1_PA1_FIFO_EMPTY', 'PH_SC1_PA1_FIFO_FULL', + 'PH_SC1_PA1_FPOV_WE', 'PH_SC1_PA1_LPOV_WE', 'PH_SC1_PA1_NULL_WE', + 'PH_SC1_PA2_DATA_FIFO_EOP_RD', 'PH_SC1_PA2_DATA_FIFO_RD', + 'PH_SC1_PA2_DATA_FIFO_WE', 'PH_SC1_PA2_DEALLOC_4_0_RD', + 'PH_SC1_PA2_EOPG_WE', 'PH_SC1_PA2_EOP_WE', 'PH_SC1_PA2_EVENT_WE', + 'PH_SC1_PA2_FIFO_EMPTY', 'PH_SC1_PA2_FIFO_FULL', + 'PH_SC1_PA2_FPOV_WE', 'PH_SC1_PA2_LPOV_WE', 'PH_SC1_PA2_NULL_WE', + 'PH_SC1_PA3_DATA_FIFO_EOP_RD', 'PH_SC1_PA3_DATA_FIFO_RD', + 'PH_SC1_PA3_DATA_FIFO_WE', 'PH_SC1_PA3_DEALLOC_4_0_RD', + 'PH_SC1_PA3_EOPG_WE', 'PH_SC1_PA3_EOP_WE', 'PH_SC1_PA3_EVENT_WE', + 'PH_SC1_PA3_FIFO_EMPTY', 'PH_SC1_PA3_FIFO_FULL', + 'PH_SC1_PA3_FPOV_WE', 'PH_SC1_PA3_LPOV_WE', 'PH_SC1_PA3_NULL_WE', + 'PH_SC1_PA4_DATA_FIFO_EOP_RD', 'PH_SC1_PA4_DATA_FIFO_RD', + 'PH_SC1_PA4_DATA_FIFO_WE', 'PH_SC1_PA4_DEALLOC_4_0_RD', + 'PH_SC1_PA4_EOPG_WE', 'PH_SC1_PA4_EOP_WE', 'PH_SC1_PA4_EVENT_WE', + 'PH_SC1_PA4_FIFO_EMPTY', 'PH_SC1_PA4_FIFO_FULL', + 'PH_SC1_PA4_FPOV_WE', 'PH_SC1_PA4_LPOV_WE', 'PH_SC1_PA4_NULL_WE', + 'PH_SC1_PA5_DATA_FIFO_EOP_RD', 'PH_SC1_PA5_DATA_FIFO_RD', + 'PH_SC1_PA5_DATA_FIFO_WE', 'PH_SC1_PA5_DEALLOC_4_0_RD', + 'PH_SC1_PA5_EOPG_WE', 'PH_SC1_PA5_EOP_WE', 'PH_SC1_PA5_EVENT_WE', + 'PH_SC1_PA5_FIFO_EMPTY', 'PH_SC1_PA5_FIFO_FULL', + 'PH_SC1_PA5_FPOV_WE', 'PH_SC1_PA5_LPOV_WE', 'PH_SC1_PA5_NULL_WE', + 'PH_SC1_PA6_DATA_FIFO_EOP_RD', 'PH_SC1_PA6_DATA_FIFO_RD', + 'PH_SC1_PA6_DATA_FIFO_WE', 'PH_SC1_PA6_DEALLOC_4_0_RD', + 'PH_SC1_PA6_EOPG_WE', 'PH_SC1_PA6_EOP_WE', 'PH_SC1_PA6_EVENT_WE', + 'PH_SC1_PA6_FIFO_EMPTY', 'PH_SC1_PA6_FIFO_FULL', + 'PH_SC1_PA6_FPOV_WE', 'PH_SC1_PA6_LPOV_WE', 'PH_SC1_PA6_NULL_WE', + 'PH_SC1_PA7_DATA_FIFO_EOP_RD', 'PH_SC1_PA7_DATA_FIFO_RD', + 'PH_SC1_PA7_DATA_FIFO_WE', 'PH_SC1_PA7_DEALLOC_4_0_RD', + 'PH_SC1_PA7_EOPG_WE', 'PH_SC1_PA7_EOP_WE', 'PH_SC1_PA7_EVENT_WE', + 'PH_SC1_PA7_FIFO_EMPTY', 'PH_SC1_PA7_FIFO_FULL', + 'PH_SC1_PA7_FPOV_WE', 'PH_SC1_PA7_LPOV_WE', 'PH_SC1_PA7_NULL_WE', + 'PH_SC1_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC1_SEND', + 'PH_SC1_SRPS_WINDOW_VALID', 'PH_SC2_ARB_BUSY', + 'PH_SC2_ARB_EOP_POP_SYNC_POP', 'PH_SC2_ARB_EVENT_SYNC_POP', + 'PH_SC2_ARB_PA_BUSY_SOP', 'PH_SC2_ARB_STALLED_FROM_BELOW', + 'PH_SC2_ARB_STARVED_FROM_ABOVE', + 'PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC2_BUSY_CNT_NOT_ZERO', + 'PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC2_CREDIT_AT_MAX', + 'PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_SC2_EOP_SYNC_WINDOW', 'PH_SC2_GFX_PIPE0_TO_1_TRANSITION', + 'PH_SC2_GFX_PIPE1_TO_0_TRANSITION', + 'PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_SC2_PA0_DATA_FIFO_EOP_RD', 'PH_SC2_PA0_DATA_FIFO_RD', + 'PH_SC2_PA0_DATA_FIFO_WE', 'PH_SC2_PA0_DEALLOC_4_0_RD', + 'PH_SC2_PA0_EOPG_WE', 'PH_SC2_PA0_EOP_WE', 'PH_SC2_PA0_EVENT_WE', + 'PH_SC2_PA0_FIFO_EMPTY', 'PH_SC2_PA0_FIFO_FULL', + 'PH_SC2_PA0_FPOV_WE', 'PH_SC2_PA0_LPOV_WE', 'PH_SC2_PA0_NULL_WE', + 'PH_SC2_PA1_DATA_FIFO_EOP_RD', 'PH_SC2_PA1_DATA_FIFO_RD', + 'PH_SC2_PA1_DATA_FIFO_WE', 'PH_SC2_PA1_DEALLOC_4_0_RD', + 'PH_SC2_PA1_EOPG_WE', 'PH_SC2_PA1_EOP_WE', 'PH_SC2_PA1_EVENT_WE', + 'PH_SC2_PA1_FIFO_EMPTY', 'PH_SC2_PA1_FIFO_FULL', + 'PH_SC2_PA1_FPOV_WE', 'PH_SC2_PA1_LPOV_WE', 'PH_SC2_PA1_NULL_WE', + 'PH_SC2_PA2_DATA_FIFO_EOP_RD', 'PH_SC2_PA2_DATA_FIFO_RD', + 'PH_SC2_PA2_DATA_FIFO_WE', 'PH_SC2_PA2_DEALLOC_4_0_RD', + 'PH_SC2_PA2_EOPG_WE', 'PH_SC2_PA2_EOP_WE', 'PH_SC2_PA2_EVENT_WE', + 'PH_SC2_PA2_FIFO_EMPTY', 'PH_SC2_PA2_FIFO_FULL', + 'PH_SC2_PA2_FPOV_WE', 'PH_SC2_PA2_LPOV_WE', 'PH_SC2_PA2_NULL_WE', + 'PH_SC2_PA3_DATA_FIFO_EOP_RD', 'PH_SC2_PA3_DATA_FIFO_RD', + 'PH_SC2_PA3_DATA_FIFO_WE', 'PH_SC2_PA3_DEALLOC_4_0_RD', + 'PH_SC2_PA3_EOPG_WE', 'PH_SC2_PA3_EOP_WE', 'PH_SC2_PA3_EVENT_WE', + 'PH_SC2_PA3_FIFO_EMPTY', 'PH_SC2_PA3_FIFO_FULL', + 'PH_SC2_PA3_FPOV_WE', 'PH_SC2_PA3_LPOV_WE', 'PH_SC2_PA3_NULL_WE', + 'PH_SC2_PA4_DATA_FIFO_EOP_RD', 'PH_SC2_PA4_DATA_FIFO_RD', + 'PH_SC2_PA4_DATA_FIFO_WE', 'PH_SC2_PA4_DEALLOC_4_0_RD', + 'PH_SC2_PA4_EOPG_WE', 'PH_SC2_PA4_EOP_WE', 'PH_SC2_PA4_EVENT_WE', + 'PH_SC2_PA4_FIFO_EMPTY', 'PH_SC2_PA4_FIFO_FULL', + 'PH_SC2_PA4_FPOV_WE', 'PH_SC2_PA4_LPOV_WE', 'PH_SC2_PA4_NULL_WE', + 'PH_SC2_PA5_DATA_FIFO_EOP_RD', 'PH_SC2_PA5_DATA_FIFO_RD', + 'PH_SC2_PA5_DATA_FIFO_WE', 'PH_SC2_PA5_DEALLOC_4_0_RD', + 'PH_SC2_PA5_EOPG_WE', 'PH_SC2_PA5_EOP_WE', 'PH_SC2_PA5_EVENT_WE', + 'PH_SC2_PA5_FIFO_EMPTY', 'PH_SC2_PA5_FIFO_FULL', + 'PH_SC2_PA5_FPOV_WE', 'PH_SC2_PA5_LPOV_WE', 'PH_SC2_PA5_NULL_WE', + 'PH_SC2_PA6_DATA_FIFO_EOP_RD', 'PH_SC2_PA6_DATA_FIFO_RD', + 'PH_SC2_PA6_DATA_FIFO_WE', 'PH_SC2_PA6_DEALLOC_4_0_RD', + 'PH_SC2_PA6_EOPG_WE', 'PH_SC2_PA6_EOP_WE', 'PH_SC2_PA6_EVENT_WE', + 'PH_SC2_PA6_FIFO_EMPTY', 'PH_SC2_PA6_FIFO_FULL', + 'PH_SC2_PA6_FPOV_WE', 'PH_SC2_PA6_LPOV_WE', 'PH_SC2_PA6_NULL_WE', + 'PH_SC2_PA7_DATA_FIFO_EOP_RD', 'PH_SC2_PA7_DATA_FIFO_RD', + 'PH_SC2_PA7_DATA_FIFO_WE', 'PH_SC2_PA7_DEALLOC_4_0_RD', + 'PH_SC2_PA7_EOPG_WE', 'PH_SC2_PA7_EOP_WE', 'PH_SC2_PA7_EVENT_WE', + 'PH_SC2_PA7_FIFO_EMPTY', 'PH_SC2_PA7_FIFO_FULL', + 'PH_SC2_PA7_FPOV_WE', 'PH_SC2_PA7_LPOV_WE', 'PH_SC2_PA7_NULL_WE', + 'PH_SC2_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC2_SEND', + 'PH_SC2_SRPS_WINDOW_VALID', 'PH_SC3_ARB_BUSY', + 'PH_SC3_ARB_EOP_POP_SYNC_POP', 'PH_SC3_ARB_EVENT_SYNC_POP', + 'PH_SC3_ARB_PA_BUSY_SOP', 'PH_SC3_ARB_STALLED_FROM_BELOW', + 'PH_SC3_ARB_STARVED_FROM_ABOVE', + 'PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC3_BUSY_CNT_NOT_ZERO', + 'PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC3_CREDIT_AT_MAX', + 'PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_SC3_EOP_SYNC_WINDOW', 'PH_SC3_GFX_PIPE0_TO_1_TRANSITION', + 'PH_SC3_GFX_PIPE1_TO_0_TRANSITION', + 'PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_SC3_PA0_DATA_FIFO_EOP_RD', 'PH_SC3_PA0_DATA_FIFO_RD', + 'PH_SC3_PA0_DATA_FIFO_WE', 'PH_SC3_PA0_DEALLOC_4_0_RD', + 'PH_SC3_PA0_EOPG_WE', 'PH_SC3_PA0_EOP_WE', 'PH_SC3_PA0_EVENT_WE', + 'PH_SC3_PA0_FIFO_EMPTY', 'PH_SC3_PA0_FIFO_FULL', + 'PH_SC3_PA0_FPOV_WE', 'PH_SC3_PA0_LPOV_WE', 'PH_SC3_PA0_NULL_WE', + 'PH_SC3_PA1_DATA_FIFO_EOP_RD', 'PH_SC3_PA1_DATA_FIFO_RD', + 'PH_SC3_PA1_DATA_FIFO_WE', 'PH_SC3_PA1_DEALLOC_4_0_RD', + 'PH_SC3_PA1_EOPG_WE', 'PH_SC3_PA1_EOP_WE', 'PH_SC3_PA1_EVENT_WE', + 'PH_SC3_PA1_FIFO_EMPTY', 'PH_SC3_PA1_FIFO_FULL', + 'PH_SC3_PA1_FPOV_WE', 'PH_SC3_PA1_LPOV_WE', 'PH_SC3_PA1_NULL_WE', + 'PH_SC3_PA2_DATA_FIFO_EOP_RD', 'PH_SC3_PA2_DATA_FIFO_RD', + 'PH_SC3_PA2_DATA_FIFO_WE', 'PH_SC3_PA2_DEALLOC_4_0_RD', + 'PH_SC3_PA2_EOPG_WE', 'PH_SC3_PA2_EOP_WE', 'PH_SC3_PA2_EVENT_WE', + 'PH_SC3_PA2_FIFO_EMPTY', 'PH_SC3_PA2_FIFO_FULL', + 'PH_SC3_PA2_FPOV_WE', 'PH_SC3_PA2_LPOV_WE', 'PH_SC3_PA2_NULL_WE', + 'PH_SC3_PA3_DATA_FIFO_EOP_RD', 'PH_SC3_PA3_DATA_FIFO_RD', + 'PH_SC3_PA3_DATA_FIFO_WE', 'PH_SC3_PA3_DEALLOC_4_0_RD', + 'PH_SC3_PA3_EOPG_WE', 'PH_SC3_PA3_EOP_WE', 'PH_SC3_PA3_EVENT_WE', + 'PH_SC3_PA3_FIFO_EMPTY', 'PH_SC3_PA3_FIFO_FULL', + 'PH_SC3_PA3_FPOV_WE', 'PH_SC3_PA3_LPOV_WE', 'PH_SC3_PA3_NULL_WE', + 'PH_SC3_PA4_DATA_FIFO_EOP_RD', 'PH_SC3_PA4_DATA_FIFO_RD', + 'PH_SC3_PA4_DATA_FIFO_WE', 'PH_SC3_PA4_DEALLOC_4_0_RD', + 'PH_SC3_PA4_EOPG_WE', 'PH_SC3_PA4_EOP_WE', 'PH_SC3_PA4_EVENT_WE', + 'PH_SC3_PA4_FIFO_EMPTY', 'PH_SC3_PA4_FIFO_FULL', + 'PH_SC3_PA4_FPOV_WE', 'PH_SC3_PA4_LPOV_WE', 'PH_SC3_PA4_NULL_WE', + 'PH_SC3_PA5_DATA_FIFO_EOP_RD', 'PH_SC3_PA5_DATA_FIFO_RD', + 'PH_SC3_PA5_DATA_FIFO_WE', 'PH_SC3_PA5_DEALLOC_4_0_RD', + 'PH_SC3_PA5_EOPG_WE', 'PH_SC3_PA5_EOP_WE', 'PH_SC3_PA5_EVENT_WE', + 'PH_SC3_PA5_FIFO_EMPTY', 'PH_SC3_PA5_FIFO_FULL', + 'PH_SC3_PA5_FPOV_WE', 'PH_SC3_PA5_LPOV_WE', 'PH_SC3_PA5_NULL_WE', + 'PH_SC3_PA6_DATA_FIFO_EOP_RD', 'PH_SC3_PA6_DATA_FIFO_RD', + 'PH_SC3_PA6_DATA_FIFO_WE', 'PH_SC3_PA6_DEALLOC_4_0_RD', + 'PH_SC3_PA6_EOPG_WE', 'PH_SC3_PA6_EOP_WE', 'PH_SC3_PA6_EVENT_WE', + 'PH_SC3_PA6_FIFO_EMPTY', 'PH_SC3_PA6_FIFO_FULL', + 'PH_SC3_PA6_FPOV_WE', 'PH_SC3_PA6_LPOV_WE', 'PH_SC3_PA6_NULL_WE', + 'PH_SC3_PA7_DATA_FIFO_EOP_RD', 'PH_SC3_PA7_DATA_FIFO_RD', + 'PH_SC3_PA7_DATA_FIFO_WE', 'PH_SC3_PA7_DEALLOC_4_0_RD', + 'PH_SC3_PA7_EOPG_WE', 'PH_SC3_PA7_EOP_WE', 'PH_SC3_PA7_EVENT_WE', + 'PH_SC3_PA7_FIFO_EMPTY', 'PH_SC3_PA7_FIFO_FULL', + 'PH_SC3_PA7_FPOV_WE', 'PH_SC3_PA7_LPOV_WE', 'PH_SC3_PA7_NULL_WE', + 'PH_SC3_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC3_SEND', + 'PH_SC3_SRPS_WINDOW_VALID', 'PH_SC4_ARB_BUSY', + 'PH_SC4_ARB_EOP_POP_SYNC_POP', 'PH_SC4_ARB_EVENT_SYNC_POP', + 'PH_SC4_ARB_PA_BUSY_SOP', 'PH_SC4_ARB_STALLED_FROM_BELOW', + 'PH_SC4_ARB_STARVED_FROM_ABOVE', + 'PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC4_BUSY_CNT_NOT_ZERO', + 'PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC4_CREDIT_AT_MAX', + 'PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_SC4_EOP_SYNC_WINDOW', 'PH_SC4_GFX_PIPE0_TO_1_TRANSITION', + 'PH_SC4_GFX_PIPE1_TO_0_TRANSITION', + 'PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_SC4_PA0_DATA_FIFO_EOP_RD', 'PH_SC4_PA0_DATA_FIFO_RD', + 'PH_SC4_PA0_DATA_FIFO_WE', 'PH_SC4_PA0_DEALLOC_4_0_RD', + 'PH_SC4_PA0_EOPG_WE', 'PH_SC4_PA0_EOP_WE', 'PH_SC4_PA0_EVENT_WE', + 'PH_SC4_PA0_FIFO_EMPTY', 'PH_SC4_PA0_FIFO_FULL', + 'PH_SC4_PA0_FPOV_WE', 'PH_SC4_PA0_LPOV_WE', 'PH_SC4_PA0_NULL_WE', + 'PH_SC4_PA1_DATA_FIFO_EOP_RD', 'PH_SC4_PA1_DATA_FIFO_RD', + 'PH_SC4_PA1_DATA_FIFO_WE', 'PH_SC4_PA1_DEALLOC_4_0_RD', + 'PH_SC4_PA1_EOPG_WE', 'PH_SC4_PA1_EOP_WE', 'PH_SC4_PA1_EVENT_WE', + 'PH_SC4_PA1_FIFO_EMPTY', 'PH_SC4_PA1_FIFO_FULL', + 'PH_SC4_PA1_FPOV_WE', 'PH_SC4_PA1_LPOV_WE', 'PH_SC4_PA1_NULL_WE', + 'PH_SC4_PA2_DATA_FIFO_EOP_RD', 'PH_SC4_PA2_DATA_FIFO_RD', + 'PH_SC4_PA2_DATA_FIFO_WE', 'PH_SC4_PA2_DEALLOC_4_0_RD', + 'PH_SC4_PA2_EOPG_WE', 'PH_SC4_PA2_EOP_WE', 'PH_SC4_PA2_EVENT_WE', + 'PH_SC4_PA2_FIFO_EMPTY', 'PH_SC4_PA2_FIFO_FULL', + 'PH_SC4_PA2_FPOV_WE', 'PH_SC4_PA2_LPOV_WE', 'PH_SC4_PA2_NULL_WE', + 'PH_SC4_PA3_DATA_FIFO_EOP_RD', 'PH_SC4_PA3_DATA_FIFO_RD', + 'PH_SC4_PA3_DATA_FIFO_WE', 'PH_SC4_PA3_DEALLOC_4_0_RD', + 'PH_SC4_PA3_EOPG_WE', 'PH_SC4_PA3_EOP_WE', 'PH_SC4_PA3_EVENT_WE', + 'PH_SC4_PA3_FIFO_EMPTY', 'PH_SC4_PA3_FIFO_FULL', + 'PH_SC4_PA3_FPOV_WE', 'PH_SC4_PA3_LPOV_WE', 'PH_SC4_PA3_NULL_WE', + 'PH_SC4_PA4_DATA_FIFO_EOP_RD', 'PH_SC4_PA4_DATA_FIFO_RD', + 'PH_SC4_PA4_DATA_FIFO_WE', 'PH_SC4_PA4_DEALLOC_4_0_RD', + 'PH_SC4_PA4_EOPG_WE', 'PH_SC4_PA4_EOP_WE', 'PH_SC4_PA4_EVENT_WE', + 'PH_SC4_PA4_FIFO_EMPTY', 'PH_SC4_PA4_FIFO_FULL', + 'PH_SC4_PA4_FPOV_WE', 'PH_SC4_PA4_LPOV_WE', 'PH_SC4_PA4_NULL_WE', + 'PH_SC4_PA5_DATA_FIFO_EOP_RD', 'PH_SC4_PA5_DATA_FIFO_RD', + 'PH_SC4_PA5_DATA_FIFO_WE', 'PH_SC4_PA5_DEALLOC_4_0_RD', + 'PH_SC4_PA5_EOPG_WE', 'PH_SC4_PA5_EOP_WE', 'PH_SC4_PA5_EVENT_WE', + 'PH_SC4_PA5_FIFO_EMPTY', 'PH_SC4_PA5_FIFO_FULL', + 'PH_SC4_PA5_FPOV_WE', 'PH_SC4_PA5_LPOV_WE', 'PH_SC4_PA5_NULL_WE', + 'PH_SC4_PA6_DATA_FIFO_EOP_RD', 'PH_SC4_PA6_DATA_FIFO_RD', + 'PH_SC4_PA6_DATA_FIFO_WE', 'PH_SC4_PA6_DEALLOC_4_0_RD', + 'PH_SC4_PA6_EOPG_WE', 'PH_SC4_PA6_EOP_WE', 'PH_SC4_PA6_EVENT_WE', + 'PH_SC4_PA6_FIFO_EMPTY', 'PH_SC4_PA6_FIFO_FULL', + 'PH_SC4_PA6_FPOV_WE', 'PH_SC4_PA6_LPOV_WE', 'PH_SC4_PA6_NULL_WE', + 'PH_SC4_PA7_DATA_FIFO_EOP_RD', 'PH_SC4_PA7_DATA_FIFO_RD', + 'PH_SC4_PA7_DATA_FIFO_WE', 'PH_SC4_PA7_DEALLOC_4_0_RD', + 'PH_SC4_PA7_EOPG_WE', 'PH_SC4_PA7_EOP_WE', 'PH_SC4_PA7_EVENT_WE', + 'PH_SC4_PA7_FIFO_EMPTY', 'PH_SC4_PA7_FIFO_FULL', + 'PH_SC4_PA7_FPOV_WE', 'PH_SC4_PA7_LPOV_WE', 'PH_SC4_PA7_NULL_WE', + 'PH_SC4_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC4_SEND', + 'PH_SC4_SRPS_WINDOW_VALID', 'PH_SC5_ARB_BUSY', + 'PH_SC5_ARB_EOP_POP_SYNC_POP', 'PH_SC5_ARB_EVENT_SYNC_POP', + 'PH_SC5_ARB_PA_BUSY_SOP', 'PH_SC5_ARB_STALLED_FROM_BELOW', + 'PH_SC5_ARB_STARVED_FROM_ABOVE', + 'PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC5_BUSY_CNT_NOT_ZERO', + 'PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC5_CREDIT_AT_MAX', + 'PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_SC5_EOP_SYNC_WINDOW', 'PH_SC5_GFX_PIPE0_TO_1_TRANSITION', + 'PH_SC5_GFX_PIPE1_TO_0_TRANSITION', + 'PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_SC5_PA0_DATA_FIFO_EOP_RD', 'PH_SC5_PA0_DATA_FIFO_RD', + 'PH_SC5_PA0_DATA_FIFO_WE', 'PH_SC5_PA0_DEALLOC_4_0_RD', + 'PH_SC5_PA0_EOPG_WE', 'PH_SC5_PA0_EOP_WE', 'PH_SC5_PA0_EVENT_WE', + 'PH_SC5_PA0_FIFO_EMPTY', 'PH_SC5_PA0_FIFO_FULL', + 'PH_SC5_PA0_FPOV_WE', 'PH_SC5_PA0_LPOV_WE', 'PH_SC5_PA0_NULL_WE', + 'PH_SC5_PA1_DATA_FIFO_EOP_RD', 'PH_SC5_PA1_DATA_FIFO_RD', + 'PH_SC5_PA1_DATA_FIFO_WE', 'PH_SC5_PA1_DEALLOC_4_0_RD', + 'PH_SC5_PA1_EOPG_WE', 'PH_SC5_PA1_EOP_WE', 'PH_SC5_PA1_EVENT_WE', + 'PH_SC5_PA1_FIFO_EMPTY', 'PH_SC5_PA1_FIFO_FULL', + 'PH_SC5_PA1_FPOV_WE', 'PH_SC5_PA1_LPOV_WE', 'PH_SC5_PA1_NULL_WE', + 'PH_SC5_PA2_DATA_FIFO_EOP_RD', 'PH_SC5_PA2_DATA_FIFO_RD', + 'PH_SC5_PA2_DATA_FIFO_WE', 'PH_SC5_PA2_DEALLOC_4_0_RD', + 'PH_SC5_PA2_EOPG_WE', 'PH_SC5_PA2_EOP_WE', 'PH_SC5_PA2_EVENT_WE', + 'PH_SC5_PA2_FIFO_EMPTY', 'PH_SC5_PA2_FIFO_FULL', + 'PH_SC5_PA2_FPOV_WE', 'PH_SC5_PA2_LPOV_WE', 'PH_SC5_PA2_NULL_WE', + 'PH_SC5_PA3_DATA_FIFO_EOP_RD', 'PH_SC5_PA3_DATA_FIFO_RD', + 'PH_SC5_PA3_DATA_FIFO_WE', 'PH_SC5_PA3_DEALLOC_4_0_RD', + 'PH_SC5_PA3_EOPG_WE', 'PH_SC5_PA3_EOP_WE', 'PH_SC5_PA3_EVENT_WE', + 'PH_SC5_PA3_FIFO_EMPTY', 'PH_SC5_PA3_FIFO_FULL', + 'PH_SC5_PA3_FPOV_WE', 'PH_SC5_PA3_LPOV_WE', 'PH_SC5_PA3_NULL_WE', + 'PH_SC5_PA4_DATA_FIFO_EOP_RD', 'PH_SC5_PA4_DATA_FIFO_RD', + 'PH_SC5_PA4_DATA_FIFO_WE', 'PH_SC5_PA4_DEALLOC_4_0_RD', + 'PH_SC5_PA4_EOPG_WE', 'PH_SC5_PA4_EOP_WE', 'PH_SC5_PA4_EVENT_WE', + 'PH_SC5_PA4_FIFO_EMPTY', 'PH_SC5_PA4_FIFO_FULL', + 'PH_SC5_PA4_FPOV_WE', 'PH_SC5_PA4_LPOV_WE', 'PH_SC5_PA4_NULL_WE', + 'PH_SC5_PA5_DATA_FIFO_EOP_RD', 'PH_SC5_PA5_DATA_FIFO_RD', + 'PH_SC5_PA5_DATA_FIFO_WE', 'PH_SC5_PA5_DEALLOC_4_0_RD', + 'PH_SC5_PA5_EOPG_WE', 'PH_SC5_PA5_EOP_WE', 'PH_SC5_PA5_EVENT_WE', + 'PH_SC5_PA5_FIFO_EMPTY', 'PH_SC5_PA5_FIFO_FULL', + 'PH_SC5_PA5_FPOV_WE', 'PH_SC5_PA5_LPOV_WE', 'PH_SC5_PA5_NULL_WE', + 'PH_SC5_PA6_DATA_FIFO_EOP_RD', 'PH_SC5_PA6_DATA_FIFO_RD', + 'PH_SC5_PA6_DATA_FIFO_WE', 'PH_SC5_PA6_DEALLOC_4_0_RD', + 'PH_SC5_PA6_EOPG_WE', 'PH_SC5_PA6_EOP_WE', 'PH_SC5_PA6_EVENT_WE', + 'PH_SC5_PA6_FIFO_EMPTY', 'PH_SC5_PA6_FIFO_FULL', + 'PH_SC5_PA6_FPOV_WE', 'PH_SC5_PA6_LPOV_WE', 'PH_SC5_PA6_NULL_WE', + 'PH_SC5_PA7_DATA_FIFO_EOP_RD', 'PH_SC5_PA7_DATA_FIFO_RD', + 'PH_SC5_PA7_DATA_FIFO_WE', 'PH_SC5_PA7_DEALLOC_4_0_RD', + 'PH_SC5_PA7_EOPG_WE', 'PH_SC5_PA7_EOP_WE', 'PH_SC5_PA7_EVENT_WE', + 'PH_SC5_PA7_FIFO_EMPTY', 'PH_SC5_PA7_FIFO_FULL', + 'PH_SC5_PA7_FPOV_WE', 'PH_SC5_PA7_LPOV_WE', 'PH_SC5_PA7_NULL_WE', + 'PH_SC5_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC5_SEND', + 'PH_SC5_SRPS_WINDOW_VALID', 'PH_SC6_ARB_BUSY', + 'PH_SC6_ARB_EOP_POP_SYNC_POP', 'PH_SC6_ARB_EVENT_SYNC_POP', + 'PH_SC6_ARB_PA_BUSY_SOP', 'PH_SC6_ARB_STALLED_FROM_BELOW', + 'PH_SC6_ARB_STARVED_FROM_ABOVE', + 'PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC6_BUSY_CNT_NOT_ZERO', + 'PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC6_CREDIT_AT_MAX', + 'PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_SC6_EOP_SYNC_WINDOW', 'PH_SC6_GFX_PIPE0_TO_1_TRANSITION', + 'PH_SC6_GFX_PIPE1_TO_0_TRANSITION', + 'PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_SC6_PA0_DATA_FIFO_EOP_RD', 'PH_SC6_PA0_DATA_FIFO_RD', + 'PH_SC6_PA0_DATA_FIFO_WE', 'PH_SC6_PA0_DEALLOC_4_0_RD', + 'PH_SC6_PA0_EOPG_WE', 'PH_SC6_PA0_EOP_WE', 'PH_SC6_PA0_EVENT_WE', + 'PH_SC6_PA0_FIFO_EMPTY', 'PH_SC6_PA0_FIFO_FULL', + 'PH_SC6_PA0_FPOV_WE', 'PH_SC6_PA0_LPOV_WE', 'PH_SC6_PA0_NULL_WE', + 'PH_SC6_PA1_DATA_FIFO_EOP_RD', 'PH_SC6_PA1_DATA_FIFO_RD', + 'PH_SC6_PA1_DATA_FIFO_WE', 'PH_SC6_PA1_DEALLOC_4_0_RD', + 'PH_SC6_PA1_EOPG_WE', 'PH_SC6_PA1_EOP_WE', 'PH_SC6_PA1_EVENT_WE', + 'PH_SC6_PA1_FIFO_EMPTY', 'PH_SC6_PA1_FIFO_FULL', + 'PH_SC6_PA1_FPOV_WE', 'PH_SC6_PA1_LPOV_WE', 'PH_SC6_PA1_NULL_WE', + 'PH_SC6_PA2_DATA_FIFO_EOP_RD', 'PH_SC6_PA2_DATA_FIFO_RD', + 'PH_SC6_PA2_DATA_FIFO_WE', 'PH_SC6_PA2_DEALLOC_4_0_RD', + 'PH_SC6_PA2_EOPG_WE', 'PH_SC6_PA2_EOP_WE', 'PH_SC6_PA2_EVENT_WE', + 'PH_SC6_PA2_FIFO_EMPTY', 'PH_SC6_PA2_FIFO_FULL', + 'PH_SC6_PA2_FPOV_WE', 'PH_SC6_PA2_LPOV_WE', 'PH_SC6_PA2_NULL_WE', + 'PH_SC6_PA3_DATA_FIFO_EOP_RD', 'PH_SC6_PA3_DATA_FIFO_RD', + 'PH_SC6_PA3_DATA_FIFO_WE', 'PH_SC6_PA3_DEALLOC_4_0_RD', + 'PH_SC6_PA3_EOPG_WE', 'PH_SC6_PA3_EOP_WE', 'PH_SC6_PA3_EVENT_WE', + 'PH_SC6_PA3_FIFO_EMPTY', 'PH_SC6_PA3_FIFO_FULL', + 'PH_SC6_PA3_FPOV_WE', 'PH_SC6_PA3_LPOV_WE', 'PH_SC6_PA3_NULL_WE', + 'PH_SC6_PA4_DATA_FIFO_EOP_RD', 'PH_SC6_PA4_DATA_FIFO_RD', + 'PH_SC6_PA4_DATA_FIFO_WE', 'PH_SC6_PA4_DEALLOC_4_0_RD', + 'PH_SC6_PA4_EOPG_WE', 'PH_SC6_PA4_EOP_WE', 'PH_SC6_PA4_EVENT_WE', + 'PH_SC6_PA4_FIFO_EMPTY', 'PH_SC6_PA4_FIFO_FULL', + 'PH_SC6_PA4_FPOV_WE', 'PH_SC6_PA4_LPOV_WE', 'PH_SC6_PA4_NULL_WE', + 'PH_SC6_PA5_DATA_FIFO_EOP_RD', 'PH_SC6_PA5_DATA_FIFO_RD', + 'PH_SC6_PA5_DATA_FIFO_WE', 'PH_SC6_PA5_DEALLOC_4_0_RD', + 'PH_SC6_PA5_EOPG_WE', 'PH_SC6_PA5_EOP_WE', 'PH_SC6_PA5_EVENT_WE', + 'PH_SC6_PA5_FIFO_EMPTY', 'PH_SC6_PA5_FIFO_FULL', + 'PH_SC6_PA5_FPOV_WE', 'PH_SC6_PA5_LPOV_WE', 'PH_SC6_PA5_NULL_WE', + 'PH_SC6_PA6_DATA_FIFO_EOP_RD', 'PH_SC6_PA6_DATA_FIFO_RD', + 'PH_SC6_PA6_DATA_FIFO_WE', 'PH_SC6_PA6_DEALLOC_4_0_RD', + 'PH_SC6_PA6_EOPG_WE', 'PH_SC6_PA6_EOP_WE', 'PH_SC6_PA6_EVENT_WE', + 'PH_SC6_PA6_FIFO_EMPTY', 'PH_SC6_PA6_FIFO_FULL', + 'PH_SC6_PA6_FPOV_WE', 'PH_SC6_PA6_LPOV_WE', 'PH_SC6_PA6_NULL_WE', + 'PH_SC6_PA7_DATA_FIFO_EOP_RD', 'PH_SC6_PA7_DATA_FIFO_RD', + 'PH_SC6_PA7_DATA_FIFO_WE', 'PH_SC6_PA7_DEALLOC_4_0_RD', + 'PH_SC6_PA7_EOPG_WE', 'PH_SC6_PA7_EOP_WE', 'PH_SC6_PA7_EVENT_WE', + 'PH_SC6_PA7_FIFO_EMPTY', 'PH_SC6_PA7_FIFO_FULL', + 'PH_SC6_PA7_FPOV_WE', 'PH_SC6_PA7_LPOV_WE', 'PH_SC6_PA7_NULL_WE', + 'PH_SC6_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC6_SEND', + 'PH_SC6_SRPS_WINDOW_VALID', 'PH_SC7_ARB_BUSY', + 'PH_SC7_ARB_EOP_POP_SYNC_POP', 'PH_SC7_ARB_EVENT_SYNC_POP', + 'PH_SC7_ARB_PA_BUSY_SOP', 'PH_SC7_ARB_STALLED_FROM_BELOW', + 'PH_SC7_ARB_STARVED_FROM_ABOVE', + 'PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES', 'PH_SC7_BUSY_CNT_NOT_ZERO', + 'PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', 'PH_SC7_CREDIT_AT_MAX', + 'PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_SC7_EOP_SYNC_WINDOW', 'PH_SC7_GFX_PIPE0_TO_1_TRANSITION', + 'PH_SC7_GFX_PIPE1_TO_0_TRANSITION', + 'PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_SC7_PA0_DATA_FIFO_EOP_RD', 'PH_SC7_PA0_DATA_FIFO_RD', + 'PH_SC7_PA0_DATA_FIFO_WE', 'PH_SC7_PA0_DEALLOC_4_0_RD', + 'PH_SC7_PA0_EOPG_WE', 'PH_SC7_PA0_EOP_WE', 'PH_SC7_PA0_EVENT_WE', + 'PH_SC7_PA0_FIFO_EMPTY', 'PH_SC7_PA0_FIFO_FULL', + 'PH_SC7_PA0_FPOV_WE', 'PH_SC7_PA0_LPOV_WE', 'PH_SC7_PA0_NULL_WE', + 'PH_SC7_PA1_DATA_FIFO_EOP_RD', 'PH_SC7_PA1_DATA_FIFO_RD', + 'PH_SC7_PA1_DATA_FIFO_WE', 'PH_SC7_PA1_DEALLOC_4_0_RD', + 'PH_SC7_PA1_EOPG_WE', 'PH_SC7_PA1_EOP_WE', 'PH_SC7_PA1_EVENT_WE', + 'PH_SC7_PA1_FIFO_EMPTY', 'PH_SC7_PA1_FIFO_FULL', + 'PH_SC7_PA1_FPOV_WE', 'PH_SC7_PA1_LPOV_WE', 'PH_SC7_PA1_NULL_WE', + 'PH_SC7_PA2_DATA_FIFO_EOP_RD', 'PH_SC7_PA2_DATA_FIFO_RD', + 'PH_SC7_PA2_DATA_FIFO_WE', 'PH_SC7_PA2_DEALLOC_4_0_RD', + 'PH_SC7_PA2_EOPG_WE', 'PH_SC7_PA2_EOP_WE', 'PH_SC7_PA2_EVENT_WE', + 'PH_SC7_PA2_FIFO_EMPTY', 'PH_SC7_PA2_FIFO_FULL', + 'PH_SC7_PA2_FPOV_WE', 'PH_SC7_PA2_LPOV_WE', 'PH_SC7_PA2_NULL_WE', + 'PH_SC7_PA3_DATA_FIFO_EOP_RD', 'PH_SC7_PA3_DATA_FIFO_RD', + 'PH_SC7_PA3_DATA_FIFO_WE', 'PH_SC7_PA3_DEALLOC_4_0_RD', + 'PH_SC7_PA3_EOPG_WE', 'PH_SC7_PA3_EOP_WE', 'PH_SC7_PA3_EVENT_WE', + 'PH_SC7_PA3_FIFO_EMPTY', 'PH_SC7_PA3_FIFO_FULL', + 'PH_SC7_PA3_FPOV_WE', 'PH_SC7_PA3_LPOV_WE', 'PH_SC7_PA3_NULL_WE', + 'PH_SC7_PA4_DATA_FIFO_EOP_RD', 'PH_SC7_PA4_DATA_FIFO_RD', + 'PH_SC7_PA4_DATA_FIFO_WE', 'PH_SC7_PA4_DEALLOC_4_0_RD', + 'PH_SC7_PA4_EOPG_WE', 'PH_SC7_PA4_EOP_WE', 'PH_SC7_PA4_EVENT_WE', + 'PH_SC7_PA4_FIFO_EMPTY', 'PH_SC7_PA4_FIFO_FULL', + 'PH_SC7_PA4_FPOV_WE', 'PH_SC7_PA4_LPOV_WE', 'PH_SC7_PA4_NULL_WE', + 'PH_SC7_PA5_DATA_FIFO_EOP_RD', 'PH_SC7_PA5_DATA_FIFO_RD', + 'PH_SC7_PA5_DATA_FIFO_WE', 'PH_SC7_PA5_DEALLOC_4_0_RD', + 'PH_SC7_PA5_EOPG_WE', 'PH_SC7_PA5_EOP_WE', 'PH_SC7_PA5_EVENT_WE', + 'PH_SC7_PA5_FIFO_EMPTY', 'PH_SC7_PA5_FIFO_FULL', + 'PH_SC7_PA5_FPOV_WE', 'PH_SC7_PA5_LPOV_WE', 'PH_SC7_PA5_NULL_WE', + 'PH_SC7_PA6_DATA_FIFO_EOP_RD', 'PH_SC7_PA6_DATA_FIFO_RD', + 'PH_SC7_PA6_DATA_FIFO_WE', 'PH_SC7_PA6_DEALLOC_4_0_RD', + 'PH_SC7_PA6_EOPG_WE', 'PH_SC7_PA6_EOP_WE', 'PH_SC7_PA6_EVENT_WE', + 'PH_SC7_PA6_FIFO_EMPTY', 'PH_SC7_PA6_FIFO_FULL', + 'PH_SC7_PA6_FPOV_WE', 'PH_SC7_PA6_LPOV_WE', 'PH_SC7_PA6_NULL_WE', + 'PH_SC7_PA7_DATA_FIFO_EOP_RD', 'PH_SC7_PA7_DATA_FIFO_RD', + 'PH_SC7_PA7_DATA_FIFO_WE', 'PH_SC7_PA7_DEALLOC_4_0_RD', + 'PH_SC7_PA7_EOPG_WE', 'PH_SC7_PA7_EOP_WE', 'PH_SC7_PA7_EVENT_WE', + 'PH_SC7_PA7_FIFO_EMPTY', 'PH_SC7_PA7_FIFO_FULL', + 'PH_SC7_PA7_FPOV_WE', 'PH_SC7_PA7_LPOV_WE', 'PH_SC7_PA7_NULL_WE', + 'PH_SC7_PS_ENG_MULTICYCLE_BUBBLE', 'PH_SC7_SEND', + 'PH_SC7_SRPS_WINDOW_VALID', 'PIPELINESTAT_START', + 'PIPELINESTAT_STOP', 'PIPE_ALIGNED', 'PIPE_ALIGNED_SURF', + 'PIPE_CONFIG', 'PIPE_ID0', 'PIPE_ID1', 'PIPE_ID2', 'PIPE_ID3', + 'PIPE_INTERLEAVE', 'PIPE_INTERLEAVE_1KB', 'PIPE_INTERLEAVE_256B', + 'PIPE_INTERLEAVE_512B', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF', + 'PIPE_PIXEL_RATE_PLL_SOURCE', + 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', + 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', + 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIPE_UNALIGNED_SURF', + 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE', 'PIXEL_DEPTH_10BPC', + 'PIXEL_DEPTH_8BPC', 'PIXEL_PIPE_OCCLUSION_COUNT_0', + 'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2', + 'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', + 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', + 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', + 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', + 'PIX_DYNAMIC_EXPANSION', 'PIX_EXPAND_MODE', 'PIX_ZERO_EXPANSION', + 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', + 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET', + 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST', + 'POST_CLAMP_TF0', 'POST_CLAMP_TF1', 'POWER_STATE_ENUM', + 'POWER_STATE_ENUM_DS', 'POWER_STATE_ENUM_LS', + 'POWER_STATE_ENUM_ON', 'POWER_STATE_ENUM_SD', 'PRE_CLAMP_TF0', + 'PRE_CLAMP_TF1', 'PROG_SEQ', 'PSLC_ASAP', 'PSLC_AUTO', + 'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PS_DONE', + 'PS_PARTIAL_FLUSH', 'PTE_ROW_HEIGHT_LINEAR', + 'PTE_ROW_HEIGHT_LINEAR_1024L', 'PTE_ROW_HEIGHT_LINEAR_128L', + 'PTE_ROW_HEIGHT_LINEAR_16L', 'PTE_ROW_HEIGHT_LINEAR_256L', + 'PTE_ROW_HEIGHT_LINEAR_32L', 'PTE_ROW_HEIGHT_LINEAR_512L', + 'PTE_ROW_HEIGHT_LINEAR_64L', 'PTE_ROW_HEIGHT_LINEAR_8L', + 'PerfCounter_Vals', 'PipeConfig', 'PipeInterleaveSize', + 'PipeTiling', 'PixelPipeCounterId', 'PixelPipeStride', 'PkrMap', + 'PkrXsel', 'PkrXsel2', 'PkrYsel', 'QuadExportFormat', + 'QuadExportFormatOld', 'RAMA_ACCESS', 'RAMB_ACCESS', 'RANGE_00', + 'RANGE_FF', 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', + 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', + 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', + 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', + 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', + 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', + 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', + 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', + 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', + 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', + 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', + 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', + 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', + 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', + 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', + 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', + 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', + 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', + 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', + 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', + 'RASTER_CONFIG_SE_PAIR_MAP_3', + 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', 'RB_ALIGNED', + 'RB_ALIGNED_META_SURF', 'RB_UNALIGNED_META_SURF', + 'RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN', + 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS', + 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON', + 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN', + 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS', + 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON', + 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN', + 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS', + 'RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN', + 'RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET', + 'RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET', + 'RDPCSTX_CNTL_RDPCS_TX_FIFO_EN', + 'RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN', + 'RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET', + 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE', + 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK', + 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE', + 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK', + 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK', + 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK', + 'RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF', + 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL', + 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL', + 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE', + 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE', + 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE', + 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV', + 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV', + 'RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', + 'RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL', + 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT', + 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE', + 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH', + 'RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE', + 'RDPCS_CBUS_SOFT_RESET_DISABLE', 'RDPCS_CBUS_SOFT_RESET_ENABLE', + 'RDPCS_DPALT_4LANE_TOGGLE_2LANE', + 'RDPCS_DPALT_4LANE_TOGGLE_4LANE', + 'RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE', + 'RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE', + 'RDPCS_DPALT_DISABLE_TOGGLE_DISABLE', + 'RDPCS_DPALT_DISABLE_TOGGLE_ENABLE', + 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE', + 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE', + 'RDPCS_EXT_REFCLK_DISABLE', 'RDPCS_EXT_REFCLK_ENABLE', + 'RDPCS_EXT_REFCLK_EN_DISABLE', 'RDPCS_EXT_REFCLK_EN_ENABLE', + 'RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY', + 'RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3', + 'RDPCS_MEM_POWER_CTRL_POFF_FOR_SD', + 'RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD', + 'RDPCS_MEM_PWR_DEEP_SLEEP', 'RDPCS_MEM_PWR_LIGHT_SLEEP', + 'RDPCS_MEM_PWR_NO_FORCE', 'RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP', + 'RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP', + 'RDPCS_MEM_PWR_PWR_STATE_ON', 'RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN', + 'RDPCS_MEM_PWR_SHUT_DOWN', 'RDPCS_PHY_CR_MUX_SEL_FOR_DC', + 'RDPCS_PHY_CR_MUX_SEL_FOR_USB', 'RDPCS_PHY_CR_PARA_SEL_CR', + 'RDPCS_PHY_CR_PARA_SEL_JTAG', 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8', + 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1', + 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16', + 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2', + 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3', + 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8', + 'RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT', + 'RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT', 'RDPCS_PHY_DP_TX_RATE', + 'RDPCS_PHY_DP_TX_RATE_DIV2', 'RDPCS_PHY_DP_TX_RATE_DIV4', + 'RDPCS_PHY_DP_TX_TERM_CTRL_40', 'RDPCS_PHY_DP_TX_TERM_CTRL_42', + 'RDPCS_PHY_DP_TX_TERM_CTRL_44', 'RDPCS_PHY_DP_TX_TERM_CTRL_46', + 'RDPCS_PHY_DP_TX_TERM_CTRL_48', 'RDPCS_PHY_DP_TX_TERM_CTRL_50', + 'RDPCS_PHY_DP_TX_TERM_CTRL_52', 'RDPCS_PHY_DP_TX_TERM_CTRL_54', + 'RDPCS_PHY_DP_TX_WIDTH_10', 'RDPCS_PHY_DP_TX_WIDTH_16', + 'RDPCS_PHY_DP_TX_WIDTH_20', 'RDPCS_PHY_DP_TX_WIDTH_8', + 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', + 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', + 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', + 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', + 'RDPCS_PHY_REF_RANGE_0', 'RDPCS_PHY_REF_RANGE_1', + 'RDPCS_PHY_REF_RANGE_2', 'RDPCS_PHY_REF_RANGE_3', + 'RDPCS_PHY_REF_RANGE_4', 'RDPCS_PHY_REF_RANGE_5', + 'RDPCS_PHY_REF_RANGE_6', 'RDPCS_PHY_REF_RANGE_7', + 'RDPCS_REG_FIFO_ERROR_MASK_DISABLE', + 'RDPCS_REG_FIFO_ERROR_MASK_ENABLE', 'RDPCS_SRAMCLK_BYPASS', + 'RDPCS_SRAMCLK_DISABLE', 'RDPCS_SRAMCLK_ENABLE', + 'RDPCS_SRAMCLK_GATE_DISABLE', 'RDPCS_SRAMCLK_GATE_ENABLE', + 'RDPCS_SRAMCLK_NOT_BYPASS', 'RDPCS_SRAM_EXT_LD_DONE', + 'RDPCS_SRAM_EXT_LD_NOT_DONE', 'RDPCS_SRAM_INIT_DONE', + 'RDPCS_SRAM_INIT_NOT_DONE', 'RDPCS_SRAM_SRAM_RESET_DISABLE', + 'RDPCS_SYMCLK_DIV2_CLOCK_OFF', 'RDPCS_SYMCLK_DIV2_CLOCK_ON', + 'RDPCS_SYMCLK_DIV2_DISABLE', 'RDPCS_SYMCLK_DIV2_ENABLE', + 'RDPCS_SYMCLK_DIV2_GATE_DISABLE', 'RDPCS_SYMCLK_DIV2_GATE_ENABLE', + 'RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF', 'RDPCS_SYMCLK_SRAMCLK_CLOCK_ON', + 'RDPCS_TEST_CLK_SEL', 'RDPCS_TEST_CLK_SEL_CFGCLK', + 'RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', + 'RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK', + 'RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK', + 'RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK', + 'RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK', + 'RDPCS_TEST_CLK_SEL_EXT_CR_CLK', + 'RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', + 'RDPCS_TEST_CLK_SEL_NONE', 'RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK', + 'RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk', 'RDPCS_TEST_CLK_SEL_SRAMCLK', + 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', + 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', + 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', + 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', + 'RDPCS_TEST_CLK_SEL_dtb_out0', 'RDPCS_TEST_CLK_SEL_dtb_out1', + 'RDPCS_TX_FIFO_DISABLE', 'RDPCS_TX_FIFO_ENABLE', + 'RDPCS_TX_FIFO_ERROR_MASK_DISABLE', + 'RDPCS_TX_FIFO_ERROR_MASK_ENABLE', 'RDPCS_TX_FIFO_LANE_DISABLE', + 'RDPCS_TX_FIFO_LANE_ENABLE', 'RDPCS_TX_SOFT_RESET_DISABLE', + 'RDPCS_TX_SOFT_RESET_ENABLE', + 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE', + 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE', 'READ_256_BITS', + 'READ_512_BITS', 'READ_SEQ', 'RECTLIST', 'REFCLK_CLOCK_EN', + 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', 'REFCLK_CLOCK_EN_XTALIN_CLK', + 'REFCLK_SRC_SEL', 'REFCLK_SRC_SEL_CPL_REFCLK', + 'REFCLK_SRC_SEL_PCIE_REFCLK', 'REFER_TO_DP_SOF', + 'REFER_TO_OTG_SOF', 'REF_ALWAYS', 'REF_EQUAL', 'REF_GEQUAL', + 'REF_GREATER', 'REF_LEQUAL', 'REF_LESS', 'REF_NEVER', + 'REF_NOTEQUAL', 'REG_UNALLOCATED_ADDR_READ', + 'REG_UNALLOCATED_ADDR_WRITE', 'REG_VIRTUAL_READ', + 'REG_VIRTUAL_WRITE', 'RESERVED_60', 'RESERVED_61', 'RESERVED_62', + 'RESERVED_63', 'RESERVED_88', 'RESERVED_89', 'RESERVED_90', + 'RESERVED_91', 'RESERVED_ES', 'RESERVED_LS', 'RESERVED_RDPOLICY', + 'RESERVED_VS', 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RE_Z', + 'RGB111110_FIX', 'RGB111110_FLOAT', 'RGB565', 'RGBA1010102', + 'RGBA16161616_10LSB', 'RGBA16161616_10MSB', 'RGBA16161616_12LSB', + 'RGBA16161616_12MSB', 'RGBA16161616_FLOAT', 'RGBA16161616_SNORM', + 'RGBA16161616_UNORM', 'RGBA4444', 'RGBA5551', 'RGBA8888', + 'RIGHT_EYE', 'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC', + 'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z', + 'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_BUSY', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', + 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0', + 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1', + 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2', + 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3', + 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', + 'RMI_PERF_SEL_DYN_CLK_RB_VLD', 'RMI_PERF_SEL_EVENT_SEND', + 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ', + 'RMI_PERF_SEL_LAT_FIFO_FULL', + 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ', + 'RMI_PERF_SEL_LAT_FIFO_NUM_USED', + 'RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC', + 'RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2', 'RMI_PERF_SEL_NONE', + 'RMI_PERF_SEL_PERF_WINDOW', 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR', + 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB', + 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR', + 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB', + 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR', + 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB', + 'RMI_PERF_SEL_POP_XNACK_RTS_RTR', + 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB', + 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR', + 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB', + 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR', + 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB', + 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT', + 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT', + 'RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS', + 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT', + 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY', + 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR', + 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB', + 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR', + 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB', + 'RMI_PERF_SEL_PRT_FIFO_BUSY', 'RMI_PERF_SEL_PRT_FIFO_NUM_USED', + 'RMI_PERF_SEL_PRT_FIFO_REQ', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', + 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', + 'RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY', + 'RMI_PERF_SEL_RB_RMI_RD_BUSY', + 'RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY', + 'RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX', 'RMI_PERF_SEL_RB_RMI_RD_IDLE', + 'RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY', + 'RMI_PERF_SEL_RB_RMI_RD_STALL', 'RMI_PERF_SEL_RB_RMI_RD_STARVE', + 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', + 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', + 'RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY', + 'RMI_PERF_SEL_RB_RMI_WR_BUSY', + 'RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY', + 'RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX', 'RMI_PERF_SEL_RB_RMI_WR_IDLE', + 'RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY', + 'RMI_PERF_SEL_RB_RMI_WR_STALL', 'RMI_PERF_SEL_RB_RMI_WR_STARVE', + 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR', + 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB', + 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR', + 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB', + 'RMI_PERF_SEL_REG_CLK_VLD', 'RMI_PERF_SEL_REORDER_FIFO_BUSY', + 'RMI_PERF_SEL_REORDER_FIFO_REQ', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', + 'RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID', + 'RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID', + 'RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND', + 'RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND', + 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', + 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', + 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', + 'RMI_PERF_SEL_RMI_TC_STALL_ALLREQ', + 'RMI_PERF_SEL_RMI_TC_STALL_RDREQ', + 'RMI_PERF_SEL_RMI_TC_STALL_WRREQ', + 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', + 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', + 'RMI_PERF_SEL_RMI_UTC_BUSY', 'RMI_PERF_SEL_RMI_UTC_REQ', + 'RMI_PERF_SEL_SKID_FIFO_BUSY', 'RMI_PERF_SEL_SKID_FIFO_DEPTH', + 'RMI_PERF_SEL_SKID_FIFO_IN_RTS', 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB', + 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS', + 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', 'RMI_PERF_SEL_SKID_FIFO_REQ', + 'RMI_PERF_SEL_TCIW_BUSY', 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', + 'RMI_PERF_SEL_TCIW_REQ', + 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', + 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', + 'RMI_PERF_SEL_UTCL1_BUSY', 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL', + 'RMI_PERF_SEL_UTCL1_LFIFO_FULL', + 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS', + 'RMI_PERF_SEL_UTCL1_REQUEST', + 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS', + 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 'RMI_PERF_SEL_UTCL1_TRANSLATION_HIT', + 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS', + 'RMI_PERF_SEL_UTCL1_UTCL2_REQ', 'RMI_PERF_SEL_UTC_POP_RTSB_RTR', + 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', 'RMI_PERF_SEL_UTC_POP_RTS_RTR', + 'RMI_PERF_SEL_UTC_POP_RTS_RTRB', + 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR', + 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB', + 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR', + 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB', + 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB', + 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB', + 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR', + 'RMI_PERF_SEL_XNACK_FIFO_BUSY', 'RMI_PERF_SEL_XNACK_FIFO_FULL', + 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED', + 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR', + 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB', + 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR', + 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', 'ROM_SIGNATURE', + 'ROTATED_MICRO_TILING', 'ROTATE_0_DEGREES', 'ROTATE_180_DEGREES', + 'ROTATE_270_DEGREES', 'ROTATE_90_DEGREES', 'ROTATION_ANGLE', + 'ROUND_BY_HALF', 'ROUND_TRUNCATE', 'RRDPCS_PHY_DP_TX_PSTATE_HOLD', + 'RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF', + 'RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN', + 'RRDPCS_PHY_DP_TX_PSTATE_POWER_UP', 'RST_PIX_CNT', 'RSV_TAG_RAM', + 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', 'ReadPolicy', 'ReadSize', + 'Reserved_0x00', 'RingCounterControl', 'RoundMode', 'RowSize', + 'RowTiling', 'SAMPLE_PIPELINESTAT', 'SAMPLE_STREAMOUTSTATS', + 'SAMPLE_STREAMOUTSTATS1', 'SAMPLE_STREAMOUTSTATS2', + 'SAMPLE_STREAMOUTSTATS3', 'SCL_2TAP_HARDCODE', 'SCL_ALPHA_COEF', + 'SCL_ALPHA_COEF_ALPHA', 'SCL_ALPHA_COEF_LUMA', 'SCL_AUTOCAL_MODE', + 'SCL_BOUNDARY', 'SCL_BOUNDARY_BLACK', 'SCL_BOUNDARY_EDGE', + 'SCL_CHROMA_COEF', 'SCL_CHROMA_COEF_CHROMA', + 'SCL_CHROMA_COEF_LUMA', 'SCL_COEF_2TAP_HARDCODE_OFF', + 'SCL_COEF_2TAP_HARDCODE_ON', 'SCL_COEF_ALPHA_HORZ_FILTER', + 'SCL_COEF_ALPHA_VERT_FILTER', 'SCL_COEF_CHROMA_HORZ_FILTER', + 'SCL_COEF_CHROMA_VERT_FILTER', 'SCL_COEF_FILTER_TYPE_SEL', + 'SCL_COEF_LUMA_HORZ_FILTER', 'SCL_COEF_LUMA_VERT_FILTER', + 'SCL_COEF_RAM_SEL', 'SCL_COEF_RAM_SEL_0', 'SCL_COEF_RAM_SEL_1', + 'SCL_SHARP_DISABLE', 'SCL_SHARP_EN', 'SCL_SHARP_ENABLE', + 'SC_BACKEND_BUSY', 'SC_BACKEND_PRIM_FIFO_FULL', 'SC_BB_DISCARD', + 'SC_BCI_CREDIT_AT_MAX', 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', + 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_BCI_SEND', + 'SC_BM_BUSY', 'SC_BUSY_CNT_NOT_ZERO', + 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'SC_DB0_TILE_INTERFACE_BUSY', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'SC_DB0_TILE_INTERFACE_SEND', 'SC_DB0_TILE_INTERFACE_SEND_EVENT', + 'SC_DB0_TILE_INTERFACE_SEND_SOP', + 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 'SC_DB1_TILE_INTERFACE_BUSY', + 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', + 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'SC_DB1_TILE_INTERFACE_SEND', 'SC_DB1_TILE_INTERFACE_SEND_EVENT', + 'SC_DB1_TILE_INTERFACE_SEND_SOP', + 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX', + 'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX', + 'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_EOP_SYNC_WINDOW', + 'SC_FULL_FULL_QUAD', 'SC_FULL_HALF_QUAD', 'SC_FULL_QTR_QUAD', + 'SC_GRP0_DYN_SCLK_BUSY', 'SC_GRP1_DYN_SCLK_BUSY', + 'SC_GRP2_DYN_SCLK_BUSY', 'SC_GRP3_DYN_SCLK_BUSY', + 'SC_GRP4_DYN_SCLK_BUSY', 'SC_GRP5_DYN_SCLK_BUSY', + 'SC_GRP6_DYN_SCLK_BUSY', 'SC_GRP7_DYN_SCLK_BUSY', + 'SC_GRP8_DYN_SCLK_BUSY', 'SC_GRP9_DYN_SCLK_BUSY', + 'SC_HALF_FULL_QUAD', 'SC_HALF_HALF_QUAD', 'SC_HALF_LSB', + 'SC_HALF_QTR_QUAD', 'SC_LSB_ONE_SIDED', 'SC_LSB_TWO_SIDED', + 'SC_MULTICYCLE_BUBBLE_FREEZE', 'SC_P0_DETAIL_QUAD_COUNT', + 'SC_P0_DETAIL_QUAD_WITH_1_PIX', 'SC_P0_DETAIL_QUAD_WITH_2_PIX', + 'SC_P0_DETAIL_QUAD_WITH_3_PIX', 'SC_P0_DETAIL_QUAD_WITH_4_PIX', + 'SC_P0_HIZ_QUAD_COUNT', 'SC_P0_HIZ_QUAD_PER_TILE_H0', + 'SC_P0_HIZ_QUAD_PER_TILE_H1', 'SC_P0_HIZ_QUAD_PER_TILE_H10', + 'SC_P0_HIZ_QUAD_PER_TILE_H11', 'SC_P0_HIZ_QUAD_PER_TILE_H12', + 'SC_P0_HIZ_QUAD_PER_TILE_H13', 'SC_P0_HIZ_QUAD_PER_TILE_H14', + 'SC_P0_HIZ_QUAD_PER_TILE_H15', 'SC_P0_HIZ_QUAD_PER_TILE_H16', + 'SC_P0_HIZ_QUAD_PER_TILE_H2', 'SC_P0_HIZ_QUAD_PER_TILE_H3', + 'SC_P0_HIZ_QUAD_PER_TILE_H4', 'SC_P0_HIZ_QUAD_PER_TILE_H5', + 'SC_P0_HIZ_QUAD_PER_TILE_H6', 'SC_P0_HIZ_QUAD_PER_TILE_H7', + 'SC_P0_HIZ_QUAD_PER_TILE_H8', 'SC_P0_HIZ_QUAD_PER_TILE_H9', + 'SC_P0_HIZ_TILE_COUNT', 'SC_P1_DETAIL_QUAD_COUNT', + 'SC_P1_DETAIL_QUAD_WITH_1_PIX', 'SC_P1_DETAIL_QUAD_WITH_2_PIX', + 'SC_P1_DETAIL_QUAD_WITH_3_PIX', 'SC_P1_DETAIL_QUAD_WITH_4_PIX', + 'SC_P1_HIZ_QUAD_COUNT', 'SC_P1_HIZ_QUAD_PER_TILE_H0', + 'SC_P1_HIZ_QUAD_PER_TILE_H1', 'SC_P1_HIZ_QUAD_PER_TILE_H10', + 'SC_P1_HIZ_QUAD_PER_TILE_H11', 'SC_P1_HIZ_QUAD_PER_TILE_H12', + 'SC_P1_HIZ_QUAD_PER_TILE_H13', 'SC_P1_HIZ_QUAD_PER_TILE_H14', + 'SC_P1_HIZ_QUAD_PER_TILE_H15', 'SC_P1_HIZ_QUAD_PER_TILE_H16', + 'SC_P1_HIZ_QUAD_PER_TILE_H2', 'SC_P1_HIZ_QUAD_PER_TILE_H3', + 'SC_P1_HIZ_QUAD_PER_TILE_H4', 'SC_P1_HIZ_QUAD_PER_TILE_H5', + 'SC_P1_HIZ_QUAD_PER_TILE_H6', 'SC_P1_HIZ_QUAD_PER_TILE_H7', + 'SC_P1_HIZ_QUAD_PER_TILE_H8', 'SC_P1_HIZ_QUAD_PER_TILE_H9', + 'SC_P1_HIZ_TILE_COUNT', 'SC_P2_DETAIL_QUAD_COUNT', + 'SC_P2_DETAIL_QUAD_WITH_1_PIX', 'SC_P2_DETAIL_QUAD_WITH_2_PIX', + 'SC_P2_DETAIL_QUAD_WITH_3_PIX', 'SC_P2_DETAIL_QUAD_WITH_4_PIX', + 'SC_P2_HIZ_QUAD_COUNT', 'SC_P2_HIZ_QUAD_PER_TILE_H0', + 'SC_P2_HIZ_QUAD_PER_TILE_H1', 'SC_P2_HIZ_QUAD_PER_TILE_H10', + 'SC_P2_HIZ_QUAD_PER_TILE_H11', 'SC_P2_HIZ_QUAD_PER_TILE_H12', + 'SC_P2_HIZ_QUAD_PER_TILE_H13', 'SC_P2_HIZ_QUAD_PER_TILE_H14', + 'SC_P2_HIZ_QUAD_PER_TILE_H15', 'SC_P2_HIZ_QUAD_PER_TILE_H16', + 'SC_P2_HIZ_QUAD_PER_TILE_H2', 'SC_P2_HIZ_QUAD_PER_TILE_H3', + 'SC_P2_HIZ_QUAD_PER_TILE_H4', 'SC_P2_HIZ_QUAD_PER_TILE_H5', + 'SC_P2_HIZ_QUAD_PER_TILE_H6', 'SC_P2_HIZ_QUAD_PER_TILE_H7', + 'SC_P2_HIZ_QUAD_PER_TILE_H8', 'SC_P2_HIZ_QUAD_PER_TILE_H9', + 'SC_P2_HIZ_TILE_COUNT', 'SC_P3_DETAIL_QUAD_COUNT', + 'SC_P3_DETAIL_QUAD_WITH_1_PIX', 'SC_P3_DETAIL_QUAD_WITH_2_PIX', + 'SC_P3_DETAIL_QUAD_WITH_3_PIX', 'SC_P3_DETAIL_QUAD_WITH_4_PIX', + 'SC_P3_HIZ_QUAD_COUNT', 'SC_P3_HIZ_QUAD_PER_TILE_H0', + 'SC_P3_HIZ_QUAD_PER_TILE_H1', 'SC_P3_HIZ_QUAD_PER_TILE_H10', + 'SC_P3_HIZ_QUAD_PER_TILE_H11', 'SC_P3_HIZ_QUAD_PER_TILE_H12', + 'SC_P3_HIZ_QUAD_PER_TILE_H13', 'SC_P3_HIZ_QUAD_PER_TILE_H14', + 'SC_P3_HIZ_QUAD_PER_TILE_H15', 'SC_P3_HIZ_QUAD_PER_TILE_H16', + 'SC_P3_HIZ_QUAD_PER_TILE_H2', 'SC_P3_HIZ_QUAD_PER_TILE_H3', + 'SC_P3_HIZ_QUAD_PER_TILE_H4', 'SC_P3_HIZ_QUAD_PER_TILE_H5', + 'SC_P3_HIZ_QUAD_PER_TILE_H6', 'SC_P3_HIZ_QUAD_PER_TILE_H7', + 'SC_P3_HIZ_QUAD_PER_TILE_H8', 'SC_P3_HIZ_QUAD_PER_TILE_H9', + 'SC_P3_HIZ_TILE_COUNT', 'SC_PA0_SC_DATA_FIFO_EOPG_RD', + 'SC_PA0_SC_DATA_FIFO_EOP_RD', 'SC_PA0_SC_DATA_FIFO_RD', + 'SC_PA0_SC_DATA_FIFO_WE', 'SC_PA0_SC_DEALLOC_0_RD', + 'SC_PA0_SC_DEALLOC_1_RD', 'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE', + 'SC_PA0_SC_EVENT_WE', 'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE', + 'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE', + 'SC_PA1_SC_DATA_FIFO_EOPG_RD', 'SC_PA1_SC_DATA_FIFO_EOP_RD', + 'SC_PA1_SC_DATA_FIFO_RD', 'SC_PA1_SC_DATA_FIFO_WE', + 'SC_PA1_SC_DEALLOC_0_RD', 'SC_PA1_SC_DEALLOC_1_RD', + 'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', 'SC_PA1_SC_EVENT_WE', + 'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE', + 'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE', + 'SC_PA2_SC_DATA_FIFO_EOPG_RD', 'SC_PA2_SC_DATA_FIFO_EOP_RD', + 'SC_PA2_SC_DATA_FIFO_RD', 'SC_PA2_SC_DATA_FIFO_WE', + 'SC_PA2_SC_DEALLOC_0_RD', 'SC_PA2_SC_DEALLOC_1_RD', + 'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', 'SC_PA2_SC_EVENT_WE', + 'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE', + 'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE', + 'SC_PA3_SC_DATA_FIFO_EOPG_RD', 'SC_PA3_SC_DATA_FIFO_EOP_RD', + 'SC_PA3_SC_DATA_FIFO_RD', 'SC_PA3_SC_DATA_FIFO_WE', + 'SC_PA3_SC_DEALLOC_0_RD', 'SC_PA3_SC_DEALLOC_1_RD', + 'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', 'SC_PA3_SC_EVENT_WE', + 'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE', + 'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE', + 'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE', + 'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE', + 'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE', + 'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE', + 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', + 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', + 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', + 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', + 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', + 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', + 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', + 'SC_PBB_BUSY_AND_NO_SENDS', 'SC_PBB_END_OF_BATCH', + 'SC_PBB_END_OF_BIN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', + 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', + 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', + 'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT', + 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', + 'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', + 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', + 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', + 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', 'SC_PK_BUSY', + 'SC_PK_DEALLOC_WAVE_BREAK', 'SC_PK_MAX_DEALLOC_FORCE_EOV', + 'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS', + 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', + 'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP', + 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', + 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', + 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', + 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', + 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', + 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', + 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_PA0_SC_FIFO_EMPTY', + 'SC_PS_PA0_SC_FIFO_FULL', 'SC_PS_PA1_SC_FIFO_EMPTY', + 'SC_PS_PA1_SC_FIFO_FULL', 'SC_PS_PA2_SC_FIFO_EMPTY', + 'SC_PS_PA2_SC_FIFO_FULL', 'SC_PS_PA3_SC_FIFO_EMPTY', + 'SC_PS_PA3_SC_FIFO_FULL', 'SC_PS_TO_BE_SCLK_GATE_STALL', + 'SC_PS_TS_EVENT_FIFO_POP', 'SC_PS_TS_EVENT_FIFO_PUSH', + 'SC_PW_BM_PASS_EMPTY_PRIM', 'SC_QTR_FULL_QUAD', + 'SC_QTR_HALF_QUAD', 'SC_QTR_QTR_QUAD', 'SC_QZ0_QUAD_COUNT', + 'SC_QZ0_QUAD_PER_TILE_H0', 'SC_QZ0_QUAD_PER_TILE_H1', + 'SC_QZ0_QUAD_PER_TILE_H10', 'SC_QZ0_QUAD_PER_TILE_H11', + 'SC_QZ0_QUAD_PER_TILE_H12', 'SC_QZ0_QUAD_PER_TILE_H13', + 'SC_QZ0_QUAD_PER_TILE_H14', 'SC_QZ0_QUAD_PER_TILE_H15', + 'SC_QZ0_QUAD_PER_TILE_H16', 'SC_QZ0_QUAD_PER_TILE_H2', + 'SC_QZ0_QUAD_PER_TILE_H3', 'SC_QZ0_QUAD_PER_TILE_H4', + 'SC_QZ0_QUAD_PER_TILE_H5', 'SC_QZ0_QUAD_PER_TILE_H6', + 'SC_QZ0_QUAD_PER_TILE_H7', 'SC_QZ0_QUAD_PER_TILE_H8', + 'SC_QZ0_QUAD_PER_TILE_H9', 'SC_QZ0_TILE_COUNT', + 'SC_QZ0_TILE_COVERED_COUNT', 'SC_QZ0_TILE_NOT_COVERED_COUNT', + 'SC_QZ1_QUAD_COUNT', 'SC_QZ1_QUAD_PER_TILE_H0', + 'SC_QZ1_QUAD_PER_TILE_H1', 'SC_QZ1_QUAD_PER_TILE_H10', + 'SC_QZ1_QUAD_PER_TILE_H11', 'SC_QZ1_QUAD_PER_TILE_H12', + 'SC_QZ1_QUAD_PER_TILE_H13', 'SC_QZ1_QUAD_PER_TILE_H14', + 'SC_QZ1_QUAD_PER_TILE_H15', 'SC_QZ1_QUAD_PER_TILE_H16', + 'SC_QZ1_QUAD_PER_TILE_H2', 'SC_QZ1_QUAD_PER_TILE_H3', + 'SC_QZ1_QUAD_PER_TILE_H4', 'SC_QZ1_QUAD_PER_TILE_H5', + 'SC_QZ1_QUAD_PER_TILE_H6', 'SC_QZ1_QUAD_PER_TILE_H7', + 'SC_QZ1_QUAD_PER_TILE_H8', 'SC_QZ1_QUAD_PER_TILE_H9', + 'SC_QZ1_TILE_COUNT', 'SC_QZ1_TILE_COVERED_COUNT', + 'SC_QZ1_TILE_NOT_COVERED_COUNT', 'SC_QZ2_QUAD_COUNT', + 'SC_QZ2_QUAD_PER_TILE_H0', 'SC_QZ2_QUAD_PER_TILE_H1', + 'SC_QZ2_QUAD_PER_TILE_H10', 'SC_QZ2_QUAD_PER_TILE_H11', + 'SC_QZ2_QUAD_PER_TILE_H12', 'SC_QZ2_QUAD_PER_TILE_H13', + 'SC_QZ2_QUAD_PER_TILE_H14', 'SC_QZ2_QUAD_PER_TILE_H15', + 'SC_QZ2_QUAD_PER_TILE_H16', 'SC_QZ2_QUAD_PER_TILE_H2', + 'SC_QZ2_QUAD_PER_TILE_H3', 'SC_QZ2_QUAD_PER_TILE_H4', + 'SC_QZ2_QUAD_PER_TILE_H5', 'SC_QZ2_QUAD_PER_TILE_H6', + 'SC_QZ2_QUAD_PER_TILE_H7', 'SC_QZ2_QUAD_PER_TILE_H8', + 'SC_QZ2_QUAD_PER_TILE_H9', 'SC_QZ2_TILE_COUNT', + 'SC_QZ2_TILE_COVERED_COUNT', 'SC_QZ2_TILE_NOT_COVERED_COUNT', + 'SC_QZ3_QUAD_COUNT', 'SC_QZ3_QUAD_PER_TILE_H0', + 'SC_QZ3_QUAD_PER_TILE_H1', 'SC_QZ3_QUAD_PER_TILE_H10', + 'SC_QZ3_QUAD_PER_TILE_H11', 'SC_QZ3_QUAD_PER_TILE_H12', + 'SC_QZ3_QUAD_PER_TILE_H13', 'SC_QZ3_QUAD_PER_TILE_H14', + 'SC_QZ3_QUAD_PER_TILE_H15', 'SC_QZ3_QUAD_PER_TILE_H16', + 'SC_QZ3_QUAD_PER_TILE_H2', 'SC_QZ3_QUAD_PER_TILE_H3', + 'SC_QZ3_QUAD_PER_TILE_H4', 'SC_QZ3_QUAD_PER_TILE_H5', + 'SC_QZ3_QUAD_PER_TILE_H6', 'SC_QZ3_QUAD_PER_TILE_H7', + 'SC_QZ3_QUAD_PER_TILE_H8', 'SC_QZ3_QUAD_PER_TILE_H9', + 'SC_QZ3_TILE_COUNT', 'SC_QZ3_TILE_COVERED_COUNT', + 'SC_QZ3_TILE_NOT_COVERED_COUNT', 'SC_QZQP_WINDOW_VALID', + 'SC_QZQP_WINDOW_VALID_BUSY', 'SC_REG_SCLK_BUSY', 'SC_RESERVED_0', + 'SC_RESERVED_1', 'SC_RESERVED_2', 'SC_RESERVED_3', 'SC_SCB_BUSY', + 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', + 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', 'SC_SC_SPI_DEALLOC_0_0', + 'SC_SC_SPI_DEALLOC_0_1', 'SC_SC_SPI_DEALLOC_0_2', + 'SC_SC_SPI_DEALLOC_1_0', 'SC_SC_SPI_DEALLOC_1_1', + 'SC_SC_SPI_DEALLOC_1_2', 'SC_SC_SPI_DEALLOC_2_0', + 'SC_SC_SPI_DEALLOC_2_1', 'SC_SC_SPI_DEALLOC_2_2', + 'SC_SC_SPI_DEALLOC_3_0', 'SC_SC_SPI_DEALLOC_3_1', + 'SC_SC_SPI_DEALLOC_3_2', 'SC_SC_SPI_EVENT', 'SC_SC_SPI_FPOV_0', + 'SC_SC_SPI_FPOV_1', 'SC_SC_SPI_FPOV_2', 'SC_SC_SPI_FPOV_3', + 'SC_SEND_DB_VPZ', 'SC_SPIBC_FULL_FREEZE', 'SC_SPI_CREDIT_AT_MAX', + 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', + 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_SPI_SEND', + 'SC_SRPS_WINDOW_VALID', 'SC_SRPS_WINDOW_VALID_BUSY', + 'SC_STALLED_BY_BCI', 'SC_STALLED_BY_DB_QUAD', + 'SC_STALLED_BY_DB_TILE', 'SC_STALLED_BY_PRIMFIFO', + 'SC_STALLED_BY_QUADFIFO', 'SC_STALLED_BY_SPI', + 'SC_STALLED_BY_TILEFIFO', 'SC_STALLED_BY_TILEORDERFIFO', + 'SC_STARVED_BY_DB_QUAD', 'SC_STARVED_BY_DB_TILE', + 'SC_STARVED_BY_PA', 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 'SC_SUPERTILE_COUNT', + 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', + 'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1', + 'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11', + 'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13', + 'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15', + 'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2', + 'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4', + 'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6', + 'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8', + 'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0', + 'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10', + 'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12', + 'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14', + 'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16', + 'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3', + 'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5', + 'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7', + 'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9', + 'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1', + 'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11', + 'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13', + 'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15', + 'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2', + 'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4', + 'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6', + 'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8', + 'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1', + 'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', 'SC_TILE_PICKED_H4', + 'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY', + 'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY', + 'SDMA_PERF_SEL', 'SDMA_PERF_SEL_CE_AFIFO_FULL', + 'SDMA_PERF_SEL_CE_DST_IDLE', 'SDMA_PERF_SEL_CE_INFO1_FULL', + 'SDMA_PERF_SEL_CE_INFO_FULL', 'SDMA_PERF_SEL_CE_IN_IDLE', + 'SDMA_PERF_SEL_CE_L1_WR_VLD', 'SDMA_PERF_SEL_CE_OUT_IDLE', + 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', + 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', 'SDMA_PERF_SEL_CTX_CHANGE', + 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', + 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE', + 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'SDMA_PERF_SEL_F32_L1_WR_VLD', 'SDMA_PERF_SEL_GCR_RTN', + 'SDMA_PERF_SEL_GCR_SEND', 'SDMA_PERF_SEL_GFX_SELECT', + 'SDMA_PERF_SEL_GPUVM_INVREQ_HIGH', + 'SDMA_PERF_SEL_GPUVM_INVREQ_LOW', 'SDMA_PERF_SEL_IB_CMD_FULL', + 'SDMA_PERF_SEL_IB_CMD_IDLE', 'SDMA_PERF_SEL_IDLE', + 'SDMA_PERF_SEL_INT_IDLE', 'SDMA_PERF_SEL_INT_REQ_COUNT', + 'SDMA_PERF_SEL_INT_REQ_STALL', 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', + 'SDMA_PERF_SEL_INT_RESP_RETRY', 'SDMA_PERF_SEL_L1_RDL2_IDLE', + 'SDMA_PERF_SEL_L1_RDMC_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_IDLE', + 'SDMA_PERF_SEL_L1_WRL2_IDLE', 'SDMA_PERF_SEL_L1_WRMC_IDLE', + 'SDMA_PERF_SEL_L1_WR_INV_IDLE', 'SDMA_PERF_SEL_L2_META_RET_VLD', + 'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE', + 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', + 'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_META_L2_REQ_SEND', + 'SDMA_PERF_SEL_META_REQ_SEND', 'SDMA_PERF_SEL_META_RTN_VLD', + 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER', + 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT', + 'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE', + 'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL', + 'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE', + 'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT', + 'SDMA_PERF_SEL_SDMA_CPF_INVACK', + 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', + 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', + 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', + 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', + 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', 'SDMA_PERF_SEL_SEM_IDLE', + 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', + 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', + 'SDMA_PERF_SEL_TLBI_RTN', 'SDMA_PERF_SEL_TLBI_SEND', + 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER', + 'SDMA_PERF_SEL_UTCL2_FREE', 'SDMA_PERF_SEL_UTCL2_RET_ACK', + 'SDMA_PERF_SEL_UTCL2_RET_XNACK', + 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', + 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', + 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', + 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', 'SDMA_PERF_SEL_WR_BA_RTR', + 'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', 'SEGMENTS_1', + 'SEGMENTS_128', 'SEGMENTS_16', 'SEGMENTS_2', 'SEGMENTS_32', + 'SEGMENTS_4', 'SEGMENTS_64', 'SEGMENTS_8', 'SEM_ECC_ERROR', + 'SEM_PERF_SEL', 'SEM_PERF_SEL_ACP_REQ_SIGNAL', + 'SEM_PERF_SEL_ACP_REQ_WAIT', 'SEM_PERF_SEL_ATC_INVALIDATION', + 'SEM_PERF_SEL_ATC_REQ', 'SEM_PERF_SEL_ATC_RET', + 'SEM_PERF_SEL_ATC_VM_INVALIDATION', 'SEM_PERF_SEL_ATC_XNACK', + 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', + 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', + 'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE', + 'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT', + 'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET', + 'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET', + 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT', + 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT', + 'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT', + 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT', + 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT', + 'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT', + 'SEM_RESP_FAILED', 'SEM_RESP_PASSED', 'SEM_TRANS_ERROR', + 'SEND_AT_EARLIEST_TIME', 'SEND_AT_LINK_NUMBER', + 'SEND_NORMAL_PACKET', 'SEND_PPS_PACKET', 'SET_FE_ID', + 'SET_STATIC_SCREEN_SMU_INTR', 'SH_MEM_ADDRESS_MODE', + 'SH_MEM_ADDRESS_MODE_32', 'SH_MEM_ADDRESS_MODE_64', + 'SH_MEM_ALIGNMENT_MODE', 'SH_MEM_ALIGNMENT_MODE_DWORD', + 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', + 'SH_MEM_RETRY_MODE', 'SH_MEM_RETRY_MODE_ALL', + 'SH_MEM_RETRY_MODE_NONE', 'SH_MEM_RETRY_MODE_WRITEATOMIC', + 'SIGNED', 'SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_SA_SDST_START', + 'SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_SDST_START', + 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_START', + 'SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_VCC_START', + 'SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_VDST_START', + 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_START', + 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', + 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', + 'SIMM16_WAITCNT_VM_CNT_HI_SIZE', 'SIMM16_WAITCNT_VM_CNT_HI_START', + 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', + 'SIXTEEN_BANKS', 'SIXTEEN_PIPES', 'SIXTY_FOUR_PIPES', 'SIZE_16K', + 'SIZE_8K', 'SMU_INTR_STATUS_CLEAR', 'SMU_INTR_STATUS_NOOP', + 'SM_MODE_RESERVED', 'SOFT_RESET', 'SOFT_RESET_0', 'SOFT_RESET_1', + 'SO_VGTSTREAMOUT_FLUSH', 'SPI_FOG_EXP', 'SPI_FOG_EXP2', + 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', 'SPI_FOG_NONE', + 'SPI_LB_WAVES_RSVD', 'SPI_LB_WAVES_SELECT', 'SPI_PERFCNT_SEL', + 'SPI_PERF_CLKGATE_ACTIVE_STALL', 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON', + 'SPI_PERF_CLKGATE_BUSY_STALL', 'SPI_PERF_CLKGATE_CGTT_DYN_ON', + 'SPI_PERF_CLKGATE_CGTT_REG_ON', 'SPI_PERF_CSG_BUSY', + 'SPI_PERF_CSG_CRAWLER_STALL', 'SPI_PERF_CSG_EVENT_WAVE', + 'SPI_PERF_CSG_NUM_THREADGROUPS', 'SPI_PERF_CSG_WAVE', + 'SPI_PERF_CSG_WINDOW_VALID', 'SPI_PERF_CSN_BUSY', + 'SPI_PERF_CSN_CRAWLER_STALL', 'SPI_PERF_CSN_EVENT_WAVE', + 'SPI_PERF_CSN_NUM_THREADGROUPS', 'SPI_PERF_CSN_WAVE', + 'SPI_PERF_CSN_WINDOW_VALID', 'SPI_PERF_ESC_VTX_BUSY', + 'SPI_PERF_ESC_VTX_CAC_BUSY', 'SPI_PERF_ESC_VTX_INPUT_STARVED', + 'SPI_PERF_ESC_VTX_VSR_FULL', 'SPI_PERF_ESC_VTX_VSR_STALL', + 'SPI_PERF_ES_BUSY', 'SPI_PERF_ES_CRAWLER_STALL', + 'SPI_PERF_ES_EVENT_WAVE', 'SPI_PERF_ES_FIRST_SUBGRP', + 'SPI_PERF_ES_FIRST_WAVE', 'SPI_PERF_ES_LAST_SUBGRP', + 'SPI_PERF_ES_LAST_WAVE', 'SPI_PERF_ES_LSHS_DEALLOC', + 'SPI_PERF_ES_PERS_UPD_FULL0', 'SPI_PERF_ES_PERS_UPD_FULL1', + 'SPI_PERF_ES_WAVE', 'SPI_PERF_ES_WINDOW_VALID', + 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', + 'SPI_PERF_EXP_ARB_PAR_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', + 'SPI_PERF_GSC_VTX_BUSY', 'SPI_PERF_GSC_VTX_CAC_BUSY', + 'SPI_PERF_GSC_VTX_INPUT_STARVED', 'SPI_PERF_GSC_VTX_VSR_FULL', + 'SPI_PERF_GSC_VTX_VSR_STALL', 'SPI_PERF_GS_BUSY', + 'SPI_PERF_GS_CRAWLER_STALL', 'SPI_PERF_GS_EVENT_WAVE', + 'SPI_PERF_GS_FIRST_SUBGRP', 'SPI_PERF_GS_GRP_FIFO_FULL', + 'SPI_PERF_GS_HS_DEALLOC', 'SPI_PERF_GS_LAST_SUBGRP', + 'SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY', 'SPI_PERF_GS_NGG_PC_FULL', + 'SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT', + 'SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT', + 'SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON', + 'SPI_PERF_GS_NGG_SE_FORWARDED_BATON', + 'SPI_PERF_GS_NGG_SE_HAS_BATON', + 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', + 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', + 'SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT', + 'SPI_PERF_GS_PERS_UPD_FULL0', 'SPI_PERF_GS_PERS_UPD_FULL1', + 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID', + 'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL', + 'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE', + 'SPI_PERF_HS_LAST_WAVE', 'SPI_PERF_HS_OFFCHIP_LDS_STALL', + 'SPI_PERF_HS_PERS_UPD_FULL0', 'SPI_PERF_HS_PERS_UPD_FULL1', + 'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WINDOW_VALID', + 'SPI_PERF_LDS0_PC_VALID', 'SPI_PERF_LDS1_PC_VALID', + 'SPI_PERF_LS_BUSY', 'SPI_PERF_LS_CRAWLER_STALL', + 'SPI_PERF_LS_EVENT_WAVE', 'SPI_PERF_LS_FIRST_WAVE', + 'SPI_PERF_LS_LAST_WAVE', 'SPI_PERF_LS_OFFCHIP_LDS_STALL', + 'SPI_PERF_LS_PERS_UPD_FULL0', 'SPI_PERF_LS_PERS_UPD_FULL1', + 'SPI_PERF_LS_WAVE', 'SPI_PERF_LS_WINDOW_VALID', + 'SPI_PERF_NUM_EXPGRANT_EXPORTS', 'SPI_PERF_NUM_PS_COL_R0_EXPORTS', + 'SPI_PERF_NUM_PS_COL_R1_EXPORTS', + 'SPI_PERF_NUM_VS_GDS_R0_EXPORTS', + 'SPI_PERF_NUM_VS_GDS_R1_EXPORTS', + 'SPI_PERF_NUM_VS_PARAM_R0_EXPORTS', + 'SPI_PERF_NUM_VS_PARAM_R1_EXPORTS', + 'SPI_PERF_NUM_VS_POS_R0_EXPORTS', + 'SPI_PERF_NUM_VS_POS_R1_EXPORTS', 'SPI_PERF_PC_ALLOC_ACCUM', + 'SPI_PERF_PIX_ALLOC_DB0_STALL', 'SPI_PERF_PIX_ALLOC_DB1_STALL', + 'SPI_PERF_PIX_ALLOC_DB2_STALL', 'SPI_PERF_PIX_ALLOC_DB3_STALL', + 'SPI_PERF_PIX_ALLOC_DB4_STALL', 'SPI_PERF_PIX_ALLOC_DB5_STALL', + 'SPI_PERF_PIX_ALLOC_DB6_STALL', 'SPI_PERF_PIX_ALLOC_DB7_STALL', + 'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PIX_ALLOC_SCB0_STALL', + 'SPI_PERF_PIX_ALLOC_SCB1_STALL', 'SPI_PERF_PIX_ALLOC_SCB2_STALL', + 'SPI_PERF_PIX_ALLOC_SCB3_STALL', 'SPI_PERF_PS0_ACTIVE', + 'SPI_PERF_PS0_BUSY', 'SPI_PERF_PS0_CNF_BIN2', + 'SPI_PERF_PS0_CNF_BIN3', 'SPI_PERF_PS0_CRAWLER_STALL', + 'SPI_PERF_PS0_DEALLOC_BIN0', 'SPI_PERF_PS0_EVENT_WAVE', + 'SPI_PERF_PS0_FPOS_BIN1_STALL', 'SPI_PERF_PS0_FPOS_BIN2', + 'SPI_PERF_PS0_LDS_RES_FULL', 'SPI_PERF_PS0_OPT_WAVE', + 'SPI_PERF_PS0_PASS_BIN0', 'SPI_PERF_PS0_PASS_BIN1', + 'SPI_PERF_PS0_POPS_WAVE_EXIT', 'SPI_PERF_PS0_POPS_WAVE_SENT', + 'SPI_PERF_PS0_PRIM_BIN0', 'SPI_PERF_PS0_PRIM_BIN1', + 'SPI_PERF_PS0_WAVE', 'SPI_PERF_PS0_WINDOW_VALID', + 'SPI_PERF_PS1_ACTIVE', 'SPI_PERF_PS1_BUSY', + 'SPI_PERF_PS1_CNF_BIN2', 'SPI_PERF_PS1_CNF_BIN3', + 'SPI_PERF_PS1_CRAWLER_STALL', 'SPI_PERF_PS1_DEALLOC_BIN0', + 'SPI_PERF_PS1_EVENT_WAVE', 'SPI_PERF_PS1_FPOS_BIN1_STALL', + 'SPI_PERF_PS1_FPOS_BIN2', 'SPI_PERF_PS1_LDS_RES_FULL', + 'SPI_PERF_PS1_OPT_WAVE', 'SPI_PERF_PS1_PASS_BIN0', + 'SPI_PERF_PS1_PASS_BIN1', 'SPI_PERF_PS1_POPS_WAVE_EXIT', + 'SPI_PERF_PS1_POPS_WAVE_SENT', 'SPI_PERF_PS1_PRIM_BIN0', + 'SPI_PERF_PS1_PRIM_BIN1', 'SPI_PERF_PS1_WAVE', + 'SPI_PERF_PS1_WINDOW_VALID', 'SPI_PERF_PS2_ACTIVE', + 'SPI_PERF_PS2_BUSY', 'SPI_PERF_PS2_CNF_BIN2', + 'SPI_PERF_PS2_CNF_BIN3', 'SPI_PERF_PS2_CRAWLER_STALL', + 'SPI_PERF_PS2_DEALLOC_BIN0', 'SPI_PERF_PS2_EVENT_WAVE', + 'SPI_PERF_PS2_FPOS_BIN1_STALL', 'SPI_PERF_PS2_FPOS_BIN2', + 'SPI_PERF_PS2_LDS_RES_FULL', 'SPI_PERF_PS2_OPT_WAVE', + 'SPI_PERF_PS2_PASS_BIN0', 'SPI_PERF_PS2_PASS_BIN1', + 'SPI_PERF_PS2_POPS_WAVE_EXIT', 'SPI_PERF_PS2_POPS_WAVE_SENT', + 'SPI_PERF_PS2_PRIM_BIN0', 'SPI_PERF_PS2_PRIM_BIN1', + 'SPI_PERF_PS2_WAVE', 'SPI_PERF_PS2_WINDOW_VALID', + 'SPI_PERF_PS3_ACTIVE', 'SPI_PERF_PS3_BUSY', + 'SPI_PERF_PS3_CNF_BIN2', 'SPI_PERF_PS3_CNF_BIN3', + 'SPI_PERF_PS3_CRAWLER_STALL', 'SPI_PERF_PS3_DEALLOC_BIN0', + 'SPI_PERF_PS3_EVENT_WAVE', 'SPI_PERF_PS3_FPOS_BIN1_STALL', + 'SPI_PERF_PS3_FPOS_BIN2', 'SPI_PERF_PS3_LDS_RES_FULL', + 'SPI_PERF_PS3_OPT_WAVE', 'SPI_PERF_PS3_PASS_BIN0', + 'SPI_PERF_PS3_PASS_BIN1', 'SPI_PERF_PS3_POPS_WAVE_EXIT', + 'SPI_PERF_PS3_POPS_WAVE_SENT', 'SPI_PERF_PS3_PRIM_BIN0', + 'SPI_PERF_PS3_PRIM_BIN1', 'SPI_PERF_PS3_WAVE', + 'SPI_PERF_PS3_WINDOW_VALID', 'SPI_PERF_PS_PERS_UPD_FULL0', + 'SPI_PERF_PS_PERS_UPD_FULL1', 'SPI_PERF_RA_BAR_CU_FULL_CSG', + 'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_HS', + 'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN', + 'SPI_PERF_RA_CSG_LOCK', 'SPI_PERF_RA_CSN_LOCK', + 'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK', + 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 'SPI_PERF_RA_LDS_CU_FULL_ES', 'SPI_PERF_RA_LDS_CU_FULL_LS', + 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_PIPE_REQ_BIN2', + 'SPI_PERF_RA_REQ_NO_ALLOC', 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', + 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', 'SPI_PERF_RA_REQ_NO_ALLOC_GS', + 'SPI_PERF_RA_REQ_NO_ALLOC_HS', 'SPI_PERF_RA_REQ_NO_ALLOC_PS', + 'SPI_PERF_RA_REQ_NO_ALLOC_VS', 'SPI_PERF_RA_RES_STALL_CSG', + 'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_GS', + 'SPI_PERF_RA_RES_STALL_HS', 'SPI_PERF_RA_RES_STALL_PS', + 'SPI_PERF_RA_RES_STALL_VS', 'SPI_PERF_RA_RSV_UPD', + 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG', + 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_SGPR_SIMD_FULL_GS', + 'SPI_PERF_RA_SGPR_SIMD_FULL_HS', 'SPI_PERF_RA_SGPR_SIMD_FULL_PS', + 'SPI_PERF_RA_SGPR_SIMD_FULL_VS', 'SPI_PERF_RA_TASK_REQ_BIN3', + 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', + 'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS', + 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_TMP_STALL_VS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_VS', 'SPI_PERF_RA_VS_LOCK', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_VS', 'SPI_PERF_RA_WR_CTL_FULL', + 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', + 'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS', + 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_RA_WVLIM_STALL_VS', + 'SPI_PERF_SWC_CSC_WR', 'SPI_PERF_SWC_CSG_WR', + 'SPI_PERF_SWC_GS_WR', 'SPI_PERF_SWC_HS_WR', 'SPI_PERF_SWC_PS_WR', + 'SPI_PERF_SWC_VS_WR', 'SPI_PERF_VS_ALLOC_CNT', 'SPI_PERF_VS_BUSY', + 'SPI_PERF_VS_CRAWLER_STALL', 'SPI_PERF_VS_EVENT_WAVE', + 'SPI_PERF_VS_FIRST_SUBGRP', 'SPI_PERF_VS_FIRST_WAVE', + 'SPI_PERF_VS_LAST_SUBGRP', 'SPI_PERF_VS_LAST_WAVE', + 'SPI_PERF_VS_LATE_ALLOC_ACCUM', 'SPI_PERF_VS_LATE_ALLOC_FULL', + 'SPI_PERF_VS_LSHS_DEALLOC', 'SPI_PERF_VS_PC_ALLOC_CNT', + 'SPI_PERF_VS_PC_STALL', 'SPI_PERF_VS_PERS_UPD_FULL0', + 'SPI_PERF_VS_PERS_UPD_FULL1', 'SPI_PERF_VS_POS0_STALL', + 'SPI_PERF_VS_POS1_STALL', 'SPI_PERF_VS_WAVE', + 'SPI_PERF_VS_WINDOW_VALID', 'SPI_PERF_VWC_CSC_WR', + 'SPI_PERF_VWC_CSG_WR', 'SPI_PERF_VWC_GS_WR', 'SPI_PERF_VWC_HS_WR', + 'SPI_PERF_VWC_PS_WR', 'SPI_PERF_VWC_VS_WR', + 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', + 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', + 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', 'SPI_SAMPLE_CNTL', + 'SPI_SHADER_1COMP', 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', + 'SPI_SHADER_32_AR', 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', + 'SPI_SHADER_4COMP', 'SPI_SHADER_4COMPRESS', + 'SPI_SHADER_EX_FORMAT', 'SPI_SHADER_FORMAT', + 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', + 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', + 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', + 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', + 'SP_PERF_SEL_DUMMY_BEGIN', 'SP_PERF_SEL_DUMMY_LAST', + 'SQC_PERF_SEL_DCACHE_ATOMIC', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED', + 'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GCR', + 'SQC_PERF_SEL_DCACHE_GCR_HITS', + 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', + 'SQC_PERF_SEL_DCACHE_GCR_WRITEBACK', 'SQC_PERF_SEL_DCACHE_HITS', + 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB', + 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY', + 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_MISSES', + 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', + 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', 'SQC_PERF_SEL_DCACHE_REQ', + 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 'SQC_PERF_SEL_DCACHE_REQ_READ_8', 'SQC_PERF_SEL_DCACHE_REQ_TIME', + 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1', + 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2', + 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4', + 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DCACHE_UTCL0_ALL_REQ', + 'SQC_PERF_SEL_DCACHE_UTCL0_HIT_FIFO_FULL', + 'SQC_PERF_SEL_DCACHE_UTCL0_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DCACHE_UTCL0_LFIFO_FULL', + 'SQC_PERF_SEL_DCACHE_UTCL0_PERMISSION_MISS', + 'SQC_PERF_SEL_DCACHE_UTCL0_REQUEST', + 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_LFIFO_NOT_RES', + 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_LRU_INFLIGHT', + 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_MISSFIFO_FULL', + 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_MULTI_MISS', + 'SQC_PERF_SEL_DCACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 'SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_HIT', + 'SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_MISS', + 'SQC_PERF_SEL_DCACHE_UTCL0_UTCL1_INFLIGHT', + 'SQC_PERF_SEL_DCACHE_UTCL0_XNACK', + 'SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ', + 'SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DCACHE_WB_ASYNC', 'SQC_PERF_SEL_DCACHE_WB_INST', + 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE', + 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', 'SQC_PERF_SEL_DUMMY_LAST', + 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF', + 'SQC_PERF_SEL_ICACHE_GCR', 'SQC_PERF_SEL_ICACHE_GCR_HITS', + 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_ICACHE_HITS', + 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB', + 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY', + 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', + 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_ICACHE_REQ', + 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_ICACHE_UTCL0_ALL_REQ', + 'SQC_PERF_SEL_ICACHE_UTCL0_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_ICACHE_UTCL0_LFIFO_FULL', + 'SQC_PERF_SEL_ICACHE_UTCL0_PERMISSION_MISS', + 'SQC_PERF_SEL_ICACHE_UTCL0_REQUEST', + 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_LFIFO_NOT_RES', + 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_LRU_INFLIGHT', + 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_MISSFIFO_FULL', + 'SQC_PERF_SEL_ICACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 'SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_HIT', + 'SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_MISS', + 'SQC_PERF_SEL_ICACHE_UTCL0_UTCL1_INFLIGHT', + 'SQC_PERF_SEL_ICACHE_UTCL0_XNACK', + 'SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ', + 'SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', + 'SQC_PERF_SEL_LDS_ADDR_STALL', 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', + 'SQC_PERF_SEL_LDS_BANK_CONFLICT', + 'SQC_PERF_SEL_LDS_CMD_FIFO_FULL', + 'SQC_PERF_SEL_LDS_DATA_FIFO_FULL', + 'SQC_PERF_SEL_LDS_DIRECT_FIFO_FULL_STALL', + 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', 'SQC_PERF_SEL_LDS_IDX_ACTIVE', + 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', + 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', + 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', + 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', + 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', 'SQC_PERF_SEL_POWER_ALU_BUSY', + 'SQC_PERF_SEL_POWER_GPR_RD', 'SQC_PERF_SEL_POWER_GPR_WR', + 'SQC_PERF_SEL_POWER_LDS_BUSY', 'SQC_PERF_SEL_POWER_TEX_BUSY', + 'SQC_PERF_SEL_POWER_VALU', 'SQC_PERF_SEL_POWER_VALU0', + 'SQC_PERF_SEL_POWER_VALU1', 'SQC_PERF_SEL_POWER_VALU2', + 'SQC_PERF_SEL_PT_POWER_STALL', 'SQC_PERF_SEL_SQ_DCACHE_REQS', + 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ', + 'SQC_PERF_SEL_TC_DATA_READ_REQ', 'SQC_PERF_SEL_TC_DATA_WRITE_REQ', + 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', + 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', + 'SQC_PERF_SEL_TC_STARVE', 'SQDEC_BEGIN', 'SQDEC_END', + 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', 'SQG_PERF_SEL_DUMMY_LAST', + 'SQG_PERF_SEL_TLB_SHOOTDOWN', 'SQG_PERF_SEL_TLB_SHOOTDOWN_CYCLES', + 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', + 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', 'SQG_PERF_SEL_TTRACE_REQS', + 'SQG_PERF_SEL_TTRACE_STALL', 'SQG_PERF_SEL_UTCL0_HIT_FIFO_FULL', + 'SQG_PERF_SEL_UTCL0_LFIFO_FULL', + 'SQG_PERF_SEL_UTCL0_PERMISSION_MISS', + 'SQG_PERF_SEL_UTCL0_REQUEST', + 'SQG_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 'SQG_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 'SQG_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 'SQG_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 'SQG_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 'SQG_PERF_SEL_UTCL0_TRANSLATION_HIT', + 'SQG_PERF_SEL_UTCL0_TRANSLATION_MISS', + 'SQG_PERF_SEL_UTCL0_UTCL1_REQ', 'SQIND_GLOBAL_REGS_OFFSET', + 'SQIND_GLOBAL_REGS_SIZE', 'SQIND_LOCAL_REGS_OFFSET', + 'SQIND_LOCAL_REGS_SIZE', 'SQIND_WAVE_HWREGS_OFFSET', + 'SQIND_WAVE_HWREGS_SIZE', 'SQIND_WAVE_SGPRS_OFFSET', + 'SQIND_WAVE_SGPRS_SIZE', 'SQIND_WAVE_VGPRS_OFFSET', + 'SQIND_WAVE_VGPRS_SIZE', 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', + 'SQPERFSDEC_BEGIN', 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', + 'SQPWRDEC_END', 'SQ_CAC_POWER_ALU_BUSY', 'SQ_CAC_POWER_GPR_RD', + 'SQ_CAC_POWER_GPR_WR', 'SQ_CAC_POWER_LDS_BUSY', + 'SQ_CAC_POWER_SEL', 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', + 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', + 'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN', + 'SQ_EDC_FUE_CNTL_LDS', 'SQ_EDC_FUE_CNTL_SIMD0', + 'SQ_EDC_FUE_CNTL_SIMD1', 'SQ_EDC_FUE_CNTL_SIMD2', + 'SQ_EDC_FUE_CNTL_SIMD3', 'SQ_EDC_FUE_CNTL_SQ', + 'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', 'SQ_EDC_FUE_CNTL_TD', + 'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS', + 'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID', + 'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR', + 'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR', + 'SQ_EX_MODE_EXCP_ADDR_WATCH0', 'SQ_EX_MODE_EXCP_DIV0', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT', + 'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0', + 'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL', + 'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW', + 'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE', + 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', + 'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET', + 'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE', + 'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT', + 'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', + 'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX', + 'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', + 'SQ_IND_CMD_CMD_DEBUG', 'SQ_IND_CMD_CMD_KILL', + 'SQ_IND_CMD_CMD_NULL', 'SQ_IND_CMD_CMD_SAVECTX', + 'SQ_IND_CMD_CMD_SETFATALHALT', 'SQ_IND_CMD_CMD_SETHALT', + 'SQ_IND_CMD_CMD_SET_SPI_PRIO', 'SQ_IND_CMD_CMD_SINGLE_STEP', + 'SQ_IND_CMD_CMD_TRAP', 'SQ_IND_CMD_MODE', + 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', + 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', + 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', + 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', + 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0', + 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', 'SQ_INST_STR_ST', + 'SQ_INTERRUPT_WORD_ENCODING', 'SQ_INTERRUPT_WORD_ENCODING_AUTO', + 'SQ_INTERRUPT_WORD_ENCODING_ERROR', + 'SQ_INTERRUPT_WORD_ENCODING_INST', 'SQ_MAX_PGM_SGPRS', + 'SQ_MAX_PGM_VGPRS', 'SQ_NON_EVENT', 'SQ_OOB_COMPLETE', + 'SQ_OOB_INDEX_AND_OFFSET', 'SQ_OOB_INDEX_ONLY', + 'SQ_OOB_NUM_RECORDS_0', 'SQ_OOB_SELECT', 'SQ_PERF_SEL', + 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_BUSY_CYCLES', + 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', + 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', + 'SQ_PERF_SEL_EXP_BUS0_BUSY', 'SQ_PERF_SEL_EXP_BUS1_BUSY', + 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', + 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_REQS', + 'SQ_PERF_SEL_IFETCH_XNACK', 'SQ_PERF_SEL_INSTS_ALL', + 'SQ_PERF_SEL_INSTS_BRANCH', 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', + 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', + 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', 'SQ_PERF_SEL_INSTS_EXP', + 'SQ_PERF_SEL_INSTS_EXP_GDS', 'SQ_PERF_SEL_INSTS_FLAT', + 'SQ_PERF_SEL_INSTS_FLAT_REPLAY', 'SQ_PERF_SEL_INSTS_GDS', + 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_SALU', + 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', + 'SQ_PERF_SEL_INSTS_SMEM_NORM', + 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY', + 'SQ_PERF_SEL_INSTS_SMEM_REPLAY', 'SQ_PERF_SEL_INSTS_TEX', + 'SQ_PERF_SEL_INSTS_TEX_LOAD', 'SQ_PERF_SEL_INSTS_TEX_REPLAY', + 'SQ_PERF_SEL_INSTS_TEX_STORE', 'SQ_PERF_SEL_INSTS_VALU', + 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', + 'SQ_PERF_SEL_INSTS_VALU_LDS_DIRECT_RD', + 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INSTS_VALU_TRANS32', + 'SQ_PERF_SEL_INSTS_VALU_VINTRP_OP', 'SQ_PERF_SEL_INSTS_WAVE32', + 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', 'SQ_PERF_SEL_INSTS_WAVE32_LDS', + 'SQ_PERF_SEL_INSTS_WAVE32_TEX', + 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', + 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', + 'SQ_PERF_SEL_INSTS_WAVE32_VALU', + 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', + 'SQ_PERF_SEL_INST_CACHE_REQS', 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', + 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', 'SQ_PERF_SEL_INST_CYCLES_FLAT', + 'SQ_PERF_SEL_INST_CYCLES_LDS', 'SQ_PERF_SEL_INST_CYCLES_TEX', + 'SQ_PERF_SEL_INST_CYCLES_VALU', + 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', + 'SQ_PERF_SEL_INST_CYCLES_VMEM', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', + 'SQ_PERF_SEL_INST_LEVEL_EXP', 'SQ_PERF_SEL_INST_LEVEL_GDS', + 'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM', + 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', + 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', 'SQ_PERF_SEL_ITEMS', + 'SQ_PERF_SEL_ITEM_CYCLES_VALU', + 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_LEVEL_WAVES', + 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_SALU', + 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VALU', + 'SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VMEM', 'SQ_PERF_SEL_MSG', + 'SQ_PERF_SEL_MSG_BUS_BUSY', 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', + 'SQ_PERF_SEL_MSG_GSCNT', 'SQ_PERF_SEL_MSG_INTERRUPT', + 'SQ_PERF_SEL_NONE', 'SQ_PERF_SEL_QUADS', 'SQ_PERF_SEL_Reserved_1', + 'SQ_PERF_SEL_Reserved_10', 'SQ_PERF_SEL_Reserved_11', + 'SQ_PERF_SEL_Reserved_12', 'SQ_PERF_SEL_Reserved_13', + 'SQ_PERF_SEL_Reserved_14', 'SQ_PERF_SEL_Reserved_15', + 'SQ_PERF_SEL_Reserved_16', 'SQ_PERF_SEL_Reserved_17', + 'SQ_PERF_SEL_Reserved_18', 'SQ_PERF_SEL_Reserved_2', + 'SQ_PERF_SEL_Reserved_3', 'SQ_PERF_SEL_Reserved_4', + 'SQ_PERF_SEL_Reserved_5', 'SQ_PERF_SEL_Reserved_6', + 'SQ_PERF_SEL_Reserved_7', 'SQ_PERF_SEL_Reserved_8', + 'SQ_PERF_SEL_Reserved_9', 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', + 'SQ_PERF_SEL_SALU_PIPE_STALL', 'SQ_PERF_SEL_SALU_SGATHER_STALL', + 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', + 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', + 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_STALL', 'SQ_PERF_SEL_USER0', + 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', + 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', + 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', + 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', + 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', + 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', + 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', + 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', + 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', + 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', + 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', + 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', + 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', + 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', + 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', + 'SQ_PERF_SEL_VALU_RETURN_SDST', + 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', + 'SQ_PERF_SEL_VALU_SGATHER_STALL', + 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', + 'SQ_PERF_SEL_VMEM_BUS_STALL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_SECOND_TRY_STALL', + 'SQ_PERF_SEL_VMEM_SECOND_TRY_USED', + 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', + 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', 'SQ_PERF_SEL_WAIT_ANY', + 'SQ_PERF_SEL_WAIT_BARRIER', 'SQ_PERF_SEL_WAIT_CNT_ANY', + 'SQ_PERF_SEL_WAIT_CNT_EXP', 'SQ_PERF_SEL_WAIT_CNT_LGKM', + 'SQ_PERF_SEL_WAIT_CNT_VMVS', 'SQ_PERF_SEL_WAIT_EXP_ALLOC', + 'SQ_PERF_SEL_WAIT_IFETCH', 'SQ_PERF_SEL_WAIT_INST_ANY', + 'SQ_PERF_SEL_WAIT_INST_BR_MSG', 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', + 'SQ_PERF_SEL_WAIT_INST_FLAT', 'SQ_PERF_SEL_WAIT_INST_LDS', + 'SQ_PERF_SEL_WAIT_INST_SCA', 'SQ_PERF_SEL_WAIT_INST_TEX', + 'SQ_PERF_SEL_WAIT_INST_VALU', 'SQ_PERF_SEL_WAIT_INST_VMEM', + 'SQ_PERF_SEL_WAIT_OTHER', 'SQ_PERF_SEL_WAIT_SLEEP', + 'SQ_PERF_SEL_WAIT_SLEEP_XNACK', 'SQ_PERF_SEL_WAIT_TTRACE', + 'SQ_PERF_SEL_WAVE32_INSTS', 'SQ_PERF_SEL_WAVE32_ITEMS', + 'SQ_PERF_SEL_WAVE64_HALF_SKIP', 'SQ_PERF_SEL_WAVE64_INSTS', + 'SQ_PERF_SEL_WAVE64_ITEMS', 'SQ_PERF_SEL_WAVES', + 'SQ_PERF_SEL_WAVES_32', 'SQ_PERF_SEL_WAVES_64', + 'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_LT_16', + 'SQ_PERF_SEL_WAVES_LT_32', 'SQ_PERF_SEL_WAVES_LT_48', + 'SQ_PERF_SEL_WAVES_LT_64', 'SQ_PERF_SEL_WAVES_RESTORED', + 'SQ_PERF_SEL_WAVES_SAVED', 'SQ_PERF_SEL_WAVE_CYCLES', + 'SQ_PERF_SEL_WAVE_READY', 'SQ_PERF_SEL_XNACK_ALL', + 'SQ_PERF_SEL_XNACK_FIRST', 'SQ_ROUND_MINUS_INFINITY', + 'SQ_ROUND_MODE', 'SQ_ROUND_NEAREST_EVEN', + 'SQ_ROUND_PLUS_INFINITY', 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', + 'SQ_RSRC_BUF_RSVD_1', 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', + 'SQ_RSRC_BUF_TYPE', 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', + 'SQ_RSRC_FLAT_RSVD_2', 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', + 'SQ_RSRC_IMG_1D', 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', + 'SQ_RSRC_IMG_2D_ARRAY', 'SQ_RSRC_IMG_2D_MSAA', + 'SQ_RSRC_IMG_2D_MSAA_ARRAY', 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', + 'SQ_RSRC_IMG_RSVD_0', 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', + 'SQ_RSRC_IMG_RSVD_3', 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', + 'SQ_RSRC_IMG_RSVD_6', 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', + 'SQ_SEL_0', 'SQ_SEL_1', 'SQ_SEL_N_BC_1', 'SQ_SEL_RESERVED_1', + 'SQ_SEL_W', 'SQ_SEL_X', 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', + 'SQ_TEX_ANISO_RATIO', 'SQ_TEX_ANISO_RATIO_1', + 'SQ_TEX_ANISO_RATIO_16', 'SQ_TEX_ANISO_RATIO_2', + 'SQ_TEX_ANISO_RATIO_4', 'SQ_TEX_ANISO_RATIO_8', + 'SQ_TEX_BORDER_COLOR', 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', + 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', + 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 'SQ_TEX_DEPTH_COMPARE_GREATER', + 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', + 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', + 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', + 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', + 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', + 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', + 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', + 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', + 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', + 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', + 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', + 'SQ_TT_INST_EXCLUDE_EXPGNT234', + 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD', 'SQ_TT_MODE', + 'SQ_TT_MODE_DETAIL', 'SQ_TT_MODE_GLOBAL', 'SQ_TT_MODE_OFF', + 'SQ_TT_MODE_ON', 'SQ_TT_RT_FREQ', 'SQ_TT_RT_FREQ_1024_CLK', + 'SQ_TT_RT_FREQ_4096_CLK', 'SQ_TT_RT_FREQ_NEVER', + 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', 'SQ_TT_TOKEN_MASK_COMP_BIT', + 'SQ_TT_TOKEN_MASK_COMP_SHIFT', 'SQ_TT_TOKEN_MASK_CONFIG_BIT', + 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', + 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', + 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', 'SQ_TT_TOKEN_MASK_INST_EXCLUDE', + 'SQ_TT_TOKEN_MASK_OTHER_BIT', 'SQ_TT_TOKEN_MASK_OTHER_SHIFT', + 'SQ_TT_TOKEN_MASK_READS_BIT', 'SQ_TT_TOKEN_MASK_READS_SHIFT', + 'SQ_TT_TOKEN_MASK_REG_INCLUDE', + 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT', + 'SQ_TT_TOKEN_MASK_SHDEC_BIT', 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', + 'SQ_TT_TOKEN_MASK_SQDEC_BIT', 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', + 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT', 'SQ_TT_UTIL_TIMER', + 'SQ_TT_UTIL_TIMER_100_CLK', 'SQ_TT_UTIL_TIMER_250_CLK', + 'SQ_TT_WAVESTART_MODE', 'SQ_TT_WAVESTART_MODE_ALLOC', + 'SQ_TT_WAVESTART_MODE_PBB_ID', 'SQ_TT_WAVESTART_MODE_SHORT', + 'SQ_TT_WTYPE_INCLUDE', 'SQ_TT_WTYPE_INCLUDE_CS_BIT', + 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_ES_BIT', + 'SQ_TT_WTYPE_INCLUDE_ES_SHIFT', 'SQ_TT_WTYPE_INCLUDE_GS_BIT', + 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_HS_BIT', + 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_LS_BIT', + 'SQ_TT_WTYPE_INCLUDE_LS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_PS_BIT', + 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_SHIFT', + 'SQ_TT_WTYPE_INCLUDE_VS_BIT', 'SQ_TT_WTYPE_INCLUDE_VS_SHIFT', + 'SQ_WATCH_MODES', 'SQ_WATCH_MODE_ALL', 'SQ_WATCH_MODE_ATOMIC', + 'SQ_WATCH_MODE_NONREAD', 'SQ_WATCH_MODE_READ', + 'SQ_WAVE_IB_ECC_CLEAN', 'SQ_WAVE_IB_ECC_ERR_CONTINUE', + 'SQ_WAVE_IB_ECC_ERR_HALT', 'SQ_WAVE_IB_ECC_ST', + 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', 'SQ_WAVE_SCHED_MODES', + 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', 'SQ_WAVE_SCHED_MODE_EXPERT', + 'SQ_WAVE_SCHED_MODE_NORMAL', 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', + 'SQ_WAVE_TYPE_ES', 'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS', + 'SQ_WAVE_TYPE_LS', 'SQ_WAVE_TYPE_PS', 'SQ_WAVE_TYPE_PS0', + 'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_PS2', 'SQ_WAVE_TYPE_PS3', + 'SQ_WAVE_TYPE_VS', 'STALL', 'STATIC_SCREEN_SMU_INTR', + 'STATIC_SCREEN_SMU_INTR_NOOP', 'STENCIL_8', 'STENCIL_ADD_CLAMP', + 'STENCIL_ADD_WRAP', 'STENCIL_AND', 'STENCIL_INVALID', + 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', + 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', + 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', + 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', 'STEREO_DISABLED', + 'STREAM_0_SYNCHRONIZATION', + 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_10_SYNCHRONIZATION', + 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION', + 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION', + 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION', + 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION', + 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION', + 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_1_SYNCHRONIZATION', + 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_2_SYNCHRONIZATION', + 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_3_SYNCHRONIZATION', + 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_4_SYNCHRONIZATION', + 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_5_SYNCHRONIZATION', + 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_6_SYNCHRONIZATION', + 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION', + 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION', + 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION', + 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'STRM_PERFMON_STATE_RESERVED_3', + 'STRM_PERFMON_STATE_START_COUNTING', + 'STRM_PERFMON_STATE_STOP_COUNTING', 'SURFACE_DCC', + 'SURFACE_DCC_IND_64B', 'SURFACE_DCC_IS_IND_64B', + 'SURFACE_DCC_IS_NOT_IND_64B', 'SURFACE_FLIP_AWAY_INT_LEVEL', + 'SURFACE_FLIP_AWAY_INT_PULSE', 'SURFACE_FLIP_AWAY_INT_TYPE', + 'SURFACE_FLIP_INT_LEVEL', 'SURFACE_FLIP_INT_PULSE', + 'SURFACE_FLIP_INT_TYPE', 'SURFACE_FLIP_IN_STEREOSYNC', + 'SURFACE_FLIP_IN_STEREOSYNC_MODE', + 'SURFACE_FLIP_MODE_FOR_STEREOSYNC', + 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', + 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', + 'SURFACE_FLIP_STEREO_SELECT_DISABLE', + 'SURFACE_FLIP_STEREO_SELECT_DISABLED', + 'SURFACE_FLIP_STEREO_SELECT_ENABLED', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', + 'SURFACE_FLIP_TYPE', 'SURFACE_FLIP_VUPDATE_SKIP_NUM', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', 'SURFACE_INUSE_IS_LATCHED', + 'SURFACE_INUSE_IS_NOT_LATCHED', 'SURFACE_INUSE_RAED_NO_LATCH', + 'SURFACE_IS_DCC', 'SURFACE_IS_NOT_DCC', 'SURFACE_IS_NOT_TMZ', + 'SURFACE_IS_TMZ', 'SURFACE_I_FLIP', 'SURFACE_PIXEL_FORMAT', + 'SURFACE_TMZ', 'SURFACE_UPDATE_IS_LOCKED', + 'SURFACE_UPDATE_IS_UNLOCKED', 'SURFACE_UPDATE_LOCK', + 'SURFACE_V_FLIP', 'SURF_16_BANK', 'SURF_2_BANK', 'SURF_4_BANK', + 'SURF_8_BANK', 'SURF_BANK_HEIGHT_1', 'SURF_BANK_HEIGHT_2', + 'SURF_BANK_HEIGHT_4', 'SURF_BANK_HEIGHT_8', 'SURF_BANK_WIDTH_1', + 'SURF_BANK_WIDTH_2', 'SURF_BANK_WIDTH_4', 'SURF_BANK_WIDTH_8', + 'SURF_MACRO_ASPECT_1', 'SURF_MACRO_ASPECT_2', + 'SURF_MACRO_ASPECT_4', 'SURF_MACRO_ASPECT_8', + 'SURF_TILE_SPLIT_128B', 'SURF_TILE_SPLIT_1KB', + 'SURF_TILE_SPLIT_256B', 'SURF_TILE_SPLIT_2KB', + 'SURF_TILE_SPLIT_4KB', 'SURF_TILE_SPLIT_512B', + 'SURF_TILE_SPLIT_64B', 'SU_PERFCNT_SEL', 'SWAP_ALT', + 'SWAP_ALT_REV', 'SWAP_STD', 'SWAP_STD_REV', 'SWATH_HEIGHT', + 'SWATH_HEIGHT_16L', 'SWATH_HEIGHT_1L', 'SWATH_HEIGHT_2L', + 'SWATH_HEIGHT_4L', 'SWATH_HEIGHT_8L', 'SWIZZLE_4KB_D', + 'SWIZZLE_4KB_D_X', 'SWIZZLE_4KB_S', 'SWIZZLE_4KB_S_X', + 'SWIZZLE_64KB_D', 'SWIZZLE_64KB_D_T', 'SWIZZLE_64KB_D_X', + 'SWIZZLE_64KB_R_X', 'SWIZZLE_64KB_S', 'SWIZZLE_64KB_S_T', + 'SWIZZLE_64KB_S_X', 'SWIZZLE_LINEAR', 'SWIZZLE_MODE_ENUM', + 'SWIZZLE_TYPE_ENUM', 'SWIZZLE_VAR_D', 'SWIZZLE_VAR_D_X', + 'SWIZZLE_VAR_S', 'SWIZZLE_VAR_S_X', 'SW_256B_D', 'SW_256B_R', + 'SW_256B_S', 'SW_4KB_D', 'SW_4KB_D_X', 'SW_4KB_R', 'SW_4KB_R_X', + 'SW_4KB_S', 'SW_4KB_S_X', 'SW_4KB_Z', 'SW_4KB_Z_X', 'SW_64KB_D', + 'SW_64KB_D_T', 'SW_64KB_D_X', 'SW_64KB_R', 'SW_64KB_R_T', + 'SW_64KB_R_X', 'SW_64KB_S', 'SW_64KB_S_T', 'SW_64KB_S_X', + 'SW_64KB_Z', 'SW_64KB_Z_T', 'SW_64KB_Z_X', 'SW_D', 'SW_L', + 'SW_LINEAR', 'SW_MODE', 'SW_R', 'SW_S', 'SW_VAR_D', 'SW_VAR_D_X', + 'SW_VAR_R', 'SW_VAR_R_X', 'SW_VAR_S', 'SW_VAR_S_X', 'SW_VAR_Z', + 'SW_VAR_Z_X', 'SW_Z', 'SX_BLEND_OPT', 'SX_CB_RAT_ACK_REQUEST', + 'SX_DOWNCONVERT_FORMAT', 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', + 'SX_PERF_SEL_CLOCK', 'SX_PERF_SEL_CLOCK_DROP_STALL', + 'SX_PERF_SEL_COL_BUSY', 'SX_PERF_SEL_COL_SCBD0_STALL', + 'SX_PERF_SEL_COL_SCBD1_STALL', 'SX_PERF_SEL_COL_SCBD_STALL', + 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB0_HALF_QUADS', + 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', + 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', + 'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB0_SIZE', + 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB1_HALF_QUADS', + 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', + 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', + 'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB1_SIZE', + 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB2_HALF_QUADS', + 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', + 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', + 'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB2_SIZE', + 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB3_HALF_QUADS', + 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', + 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', + 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_DB3_SIZE', + 'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2', + 'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4', + 'SX_PERF_SEL_GATE_EN5', 'SX_PERF_SEL_GATE_EN6', + 'SX_PERF_SEL_GATE_EN7', 'SX_PERF_SEL_GATE_EN8', + 'SX_PERF_SEL_IDX_BUSY', 'SX_PERF_SEL_IDX_IDLE_CYCLES', + 'SX_PERF_SEL_IDX_REQ', 'SX_PERF_SEL_IDX_REQ_LATENCY', + 'SX_PERF_SEL_IDX_RET', 'SX_PERF_SEL_IDX_SCBD_STALL', + 'SX_PERF_SEL_IDX_STALL_CYCLES', 'SX_PERF_SEL_PA_IDLE_CYCLES', + 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_REQ', + 'SX_PERF_SEL_PA_REQ_LATENCY', 'SX_PERF_SEL_POS_BUSY', + 'SX_PERF_SEL_POS_SCBD_STALL', 'SX_PERF_SEL_SH_COLOR_STALL', + 'SX_PERF_SEL_SH_COLOR_STARVE', 'SX_PERF_SEL_SH_IDX_STARVE', + 'SX_PERF_SEL_SH_POS_STALL', 'SX_PERF_SEL_SH_POS_STARVE', + 'SX_PERF_SEL_SPLITMODE', 'SX_RT_EXPORT_10_11_11', + 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', + 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', + 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', + 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', + 'SX_RT_EXPORT_NO_CONVERSION', 'SYMCLK_FE_FORCE_EN', + 'SYMCLK_FE_FORCE_EN_DISABLE', 'SYMCLK_FE_FORCE_EN_ENABLE', + 'SYMCLK_FE_FORCE_SRC', 'SYMCLK_FE_FORCE_SRC_RESERVED', + 'SYMCLK_FE_FORCE_SRC_UNIPHYA', 'SYMCLK_FE_FORCE_SRC_UNIPHYB', + 'SYMCLK_FE_FORCE_SRC_UNIPHYC', 'SYMCLK_FE_FORCE_SRC_UNIPHYD', + 'SYMCLK_FE_FORCE_SRC_UNIPHYE', 'SYMCLK_FE_FORCE_SRC_UNIPHYF', + 'SampleSplit', 'SampleSplitBytes', 'ScMap', + 'ScUncertaintyRegionMode', 'ScXsel', 'ScYsel', 'SeEnable', + 'SeMap', 'SePairMap', 'SePairXsel', 'SePairYsel', 'SeXsel', + 'SeYsel', 'ShaderEngineTileSize', 'SourceFormat', 'Spare_261', + 'Spare_285', 'Spare_286', 'StencilFormat', 'StencilOp', + 'SurfaceArray', 'SurfaceEndian', 'SurfaceFormat', 'SurfaceNumber', + 'SurfaceSwap', 'SurfaceTiling', 'TA_PERFCOUNT_SEL', + 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_RESERVED_29', + 'TA_PERF_SEL_RESERVED_41', 'TA_PERF_SEL_RESERVED_42', + 'TA_PERF_SEL_RESERVED_43', + 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', + 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 'TA_PERF_SEL_addresser_stalled_cycles', + 'TA_PERF_SEL_aligner_busy', 'TA_PERF_SEL_aligner_cycles', + 'TA_PERF_SEL_aniso_10_cycle_quads', + 'TA_PERF_SEL_aniso_12_cycle_quads', + 'TA_PERF_SEL_aniso_14_cycle_quads', + 'TA_PERF_SEL_aniso_16_cycle_quads', + 'TA_PERF_SEL_aniso_1_cycle_quads', + 'TA_PERF_SEL_aniso_2_cycle_quads', + 'TA_PERF_SEL_aniso_4_cycle_quads', + 'TA_PERF_SEL_aniso_6_cycle_quads', + 'TA_PERF_SEL_aniso_8_cycle_quads', + 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 'TA_PERF_SEL_aniso_stalled_cycles', + 'TA_PERF_SEL_bilin_point_1_cycle_pixels', + 'TA_PERF_SEL_buffer_atomic_wavefronts', + 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles', + 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles', + 'TA_PERF_SEL_buffer_coalescable_wavefronts', + 'TA_PERF_SEL_buffer_coalesced_read_cycles', + 'TA_PERF_SEL_buffer_coalesced_write_cycles', + 'TA_PERF_SEL_buffer_read_wavefronts', + 'TA_PERF_SEL_buffer_total_cycles', + 'TA_PERF_SEL_buffer_wavefronts', + 'TA_PERF_SEL_buffer_write_wavefronts', + 'TA_PERF_SEL_color_1_cycle_pixels', + 'TA_PERF_SEL_color_2_cycle_pixels', + 'TA_PERF_SEL_color_3_cycle_pixels', + 'TA_PERF_SEL_color_4_cycle_pixels', + 'TA_PERF_SEL_data_stalled_by_tc_cycles', + 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 'TA_PERF_SEL_deriv_stalled_cycles', + 'TA_PERF_SEL_first_xnack_on_phase0', + 'TA_PERF_SEL_first_xnack_on_phase1', + 'TA_PERF_SEL_first_xnack_on_phase2', + 'TA_PERF_SEL_first_xnack_on_phase3', + 'TA_PERF_SEL_flat_atomic_wavefronts', + 'TA_PERF_SEL_flat_coalesceable_wavefronts', + 'TA_PERF_SEL_flat_read_wavefronts', 'TA_PERF_SEL_flat_wavefronts', + 'TA_PERF_SEL_flat_write_wavefronts', 'TA_PERF_SEL_gradient_busy', + 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', + 'TA_PERF_SEL_image_atomic_wavefronts', + 'TA_PERF_SEL_image_read_wavefronts', + 'TA_PERF_SEL_image_total_cycles', 'TA_PERF_SEL_image_wavefronts', + 'TA_PERF_SEL_image_write_wavefronts', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', 'TA_PERF_SEL_lod_busy', + 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_pixels', + 'TA_PERF_SEL_mip_2_cycle_pixels', + 'TA_PERF_SEL_mipmap_invalid_samples', + 'TA_PERF_SEL_mipmap_lod_0_samples', + 'TA_PERF_SEL_mipmap_lod_10_samples', + 'TA_PERF_SEL_mipmap_lod_11_samples', + 'TA_PERF_SEL_mipmap_lod_12_samples', + 'TA_PERF_SEL_mipmap_lod_13_samples', + 'TA_PERF_SEL_mipmap_lod_14_samples', + 'TA_PERF_SEL_mipmap_lod_1_samples', + 'TA_PERF_SEL_mipmap_lod_2_samples', + 'TA_PERF_SEL_mipmap_lod_3_samples', + 'TA_PERF_SEL_mipmap_lod_4_samples', + 'TA_PERF_SEL_mipmap_lod_5_samples', + 'TA_PERF_SEL_mipmap_lod_6_samples', + 'TA_PERF_SEL_mipmap_lod_7_samples', + 'TA_PERF_SEL_mipmap_lod_8_samples', + 'TA_PERF_SEL_mipmap_lod_9_samples', 'TA_PERF_SEL_reg_sclk_vld', + 'TA_PERF_SEL_sh_fifo_addr_busy', + 'TA_PERF_SEL_sh_fifo_addr_cycles', + 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles', + 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles', + 'TA_PERF_SEL_sh_fifo_busy', 'TA_PERF_SEL_sh_fifo_cmd_busy', + 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles', + 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles', + 'TA_PERF_SEL_sh_fifo_data_busy', + 'TA_PERF_SEL_sh_fifo_data_cycles', + 'TA_PERF_SEL_sh_fifo_data_sfifo_busy', + 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles', + 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles', + 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles', + 'TA_PERF_SEL_sh_fifo_data_tfifo_busy', + 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles', + 'TA_PERF_SEL_sp_ta_addr_cycles', 'TA_PERF_SEL_sp_ta_data_cycles', + 'TA_PERF_SEL_sq_ta_cmd_cycles', 'TA_PERF_SEL_ta_busy', + 'TA_PERF_SEL_ta_fa_data_state_cycles', + 'TA_PERF_SEL_ta_sh_fifo_starved', 'TA_PERF_SEL_total_wavefronts', + 'TA_PERF_SEL_vol_1_cycle_pixels', + 'TA_PERF_SEL_vol_2_cycle_pixels', 'TA_PERF_SEL_walker_cycles', + 'TA_PERF_SEL_write_path_busy', + 'TA_PERF_SEL_write_path_input_cycles', + 'TA_PERF_SEL_write_path_output_cycles', + 'TA_PERF_SEL_xnack_on_phase0', 'TA_PERF_SEL_xnack_on_phase1', + 'TA_PERF_SEL_xnack_on_phase2', 'TA_PERF_SEL_xnack_on_phase3', + 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', + 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', + 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', + 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', + 'TA_TC_REQ_MODES', 'TA_TC_REQ_MODE_BORDER', 'TA_TC_REQ_MODE_BYTE', + 'TA_TC_REQ_MODE_BYTE_NV', 'TA_TC_REQ_MODE_DWORD', + 'TA_TC_REQ_MODE_NORMAL', 'TA_TC_REQ_MODE_TEX0', + 'TA_TC_REQ_MODE_TEX1', 'TA_TC_REQ_MODE_TEX2', + 'TCC_CACHE_POLICIES', 'TCC_CACHE_POLICY_LRU', + 'TCC_CACHE_POLICY_STREAM', 'TCC_MTYPE', 'TCP_CACHE_POLICIES', + 'TCP_CACHE_POLICY_HIT_EVICT', 'TCP_CACHE_POLICY_HIT_LRU', + 'TCP_CACHE_POLICY_MISS_EVICT', 'TCP_CACHE_POLICY_MISS_LRU', + 'TCP_CACHE_STORE_POLICIES', 'TCP_CACHE_STORE_POLICY_WT_EVICT', + 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL', + 'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0', + 'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2', + 'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1', + 'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE', + 'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN', + 'TCP_OPCODE_ATOMIC', 'TCP_OPCODE_ATOMIC_CMPSWAP', + 'TCP_OPCODE_GATHERH', 'TCP_OPCODE_READ', 'TCP_OPCODE_TYPE', + 'TCP_OPCODE_WBINVL1', 'TCP_OPCODE_WRITE', 'TCP_PERFCOUNT_SELECT', + 'TCP_PERF_SEL_ALLOC_STALL_CYCLES', + 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES', + 'TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT', + 'TCP_PERF_SEL_CORE_REG_SCLK_VLD', + 'TCP_PERF_SEL_CP_TCP_INVALIDATE', 'TCP_PERF_SEL_GATE_EN1', + 'TCP_PERF_SEL_GATE_EN2', + 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', + 'TCP_PERF_SEL_GL1_REQ_READ', 'TCP_PERF_SEL_GL1_REQ_READ_LATENCY', + 'TCP_PERF_SEL_GL1_REQ_WRITE', + 'TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY', + 'TCP_PERF_SEL_HOLE_READ_STALL', 'TCP_PERF_SEL_LFIFO_STALL_CYCLES', + 'TCP_PERF_SEL_LOD_STALL_CYCLES', + 'TCP_PERF_SEL_PENDING_STALL_CYCLES', 'TCP_PERF_SEL_POWER_STALL', + 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES', + 'TCP_PERF_SEL_READFIFO_STALL_CYCLES', + 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES', + 'TCP_PERF_SEL_REQ_MISS_TAGRAM0', 'TCP_PERF_SEL_REQ_MISS_TAGRAM1', + 'TCP_PERF_SEL_REQ_MISS_TAGRAM2', 'TCP_PERF_SEL_REQ_MISS_TAGRAM3', + 'TCP_PERF_SEL_RFIFO_STALL_CYCLES', 'TCP_PERF_SEL_SHOOTDOWN', + 'TCP_PERF_SEL_TAGRAM0_REQ', 'TCP_PERF_SEL_TAGRAM1_REQ', + 'TCP_PERF_SEL_TAGRAM2_REQ', 'TCP_PERF_SEL_TAGRAM3_REQ', + 'TCP_PERF_SEL_TA_REQ', 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', 'TCP_PERF_SEL_TA_REQ_READ', + 'TCP_PERF_SEL_TA_REQ_STATE_READ', 'TCP_PERF_SEL_TA_REQ_WRITE', + 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES', + 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES', + 'TCP_PERF_SEL_TA_TCP_STATE_READ', + 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ', + 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ', + 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_CC_READ_REQ', + 'TCP_PERF_SEL_TCC_CC_WRITE_REQ', 'TCP_PERF_SEL_TCC_DCC_REQ', + 'TCP_PERF_SEL_TCC_LRU_REQ', 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ', + 'TCP_PERF_SEL_TCC_NC_READ_REQ', 'TCP_PERF_SEL_TCC_NC_WRITE_REQ', + 'TCP_PERF_SEL_TCC_READ_REQ', 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY', + 'TCP_PERF_SEL_TCC_STREAM_REQ', 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ', + 'TCP_PERF_SEL_TCC_UC_READ_REQ', 'TCP_PERF_SEL_TCC_UC_WRITE_REQ', + 'TCP_PERF_SEL_TCC_WRITE_REQ', + 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY', + 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', 'TCP_PERF_SEL_TCP_LATENCY', + 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES', + 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES', + 'TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES', + 'TCP_PERF_SEL_TCR_RDRET_STALL', + 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES', + 'TCP_PERF_SEL_TC_TA_XNACK_STALL', + 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', 'TCP_PERF_SEL_TOTAL_ACCESSES', + 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET', + 'TCP_PERF_SEL_TOTAL_CACHE_ACCESSES', + 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ', + 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ', + 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE', + 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ', + 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE', + 'TCP_PERF_SEL_TOTAL_NON_READ', 'TCP_PERF_SEL_TOTAL_READ', + 'TCP_PERF_SEL_TOTAL_WBINVL1', 'TCP_PERF_SEL_TOTAL_WRITE', + 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES', + 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', + 'TCP_PERF_SEL_UTCL0_LFIFO_FULL', + 'TCP_PERF_SEL_UTCL0_PERMISSION_MISS', + 'TCP_PERF_SEL_UTCL0_REQUEST', + 'TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL', + 'TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 'TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 'TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 'TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 'TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS', + 'TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 'TCP_PERF_SEL_UTCL0_TRANSLATION_HIT', + 'TCP_PERF_SEL_UTCL0_TRANSLATION_MISS', + 'TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT', + 'TCP_PERF_SEL_WRITE_CONFLICT_STALL', + 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', 'TCP_WATCH_MODES', + 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', + 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', 'TC_EA_CID', + 'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', + 'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', + 'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', + 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', + 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', + 'TC_MICRO_TILE_MODE', 'TC_NACKS', 'TC_NACK_DATA_ERROR', + 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', + 'TC_NACK_PROTECTION_FAULT', 'TC_ONLY', 'TC_OP', + 'TC_OP_ATOMIC_ADD_32', 'TC_OP_ATOMIC_ADD_64', + 'TC_OP_ATOMIC_ADD_RTN_32', 'TC_OP_ATOMIC_ADD_RTN_64', + 'TC_OP_ATOMIC_AND_32', 'TC_OP_ATOMIC_AND_64', + 'TC_OP_ATOMIC_AND_RTN_32', 'TC_OP_ATOMIC_AND_RTN_64', + 'TC_OP_ATOMIC_CMPSWAP_32', 'TC_OP_ATOMIC_CMPSWAP_64', + 'TC_OP_ATOMIC_CMPSWAP_RTN_32', 'TC_OP_ATOMIC_CMPSWAP_RTN_64', + 'TC_OP_ATOMIC_DEC_32', 'TC_OP_ATOMIC_DEC_64', + 'TC_OP_ATOMIC_DEC_RTN_32', 'TC_OP_ATOMIC_DEC_RTN_64', + 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', + 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', + 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', + 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', + 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', + 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', + 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', + 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', + 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', + 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', + 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', + 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', + 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', + 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', + 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', + 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', + 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', + 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', + 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', + 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', + 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', + 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', + 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', + 'TC_OP_READ', 'TC_OP_RESERVED_FOP_32_0', + 'TC_OP_RESERVED_FOP_32_1', 'TC_OP_RESERVED_FOP_32_2', + 'TC_OP_RESERVED_FOP_64_0', 'TC_OP_RESERVED_FOP_64_1', + 'TC_OP_RESERVED_FOP_64_2', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_1', + 'TC_OP_RESERVED_FOP_RTN_32_2', 'TC_OP_RESERVED_FOP_RTN_64_0', + 'TC_OP_RESERVED_FOP_RTN_64_1', 'TC_OP_RESERVED_FOP_RTN_64_2', + 'TC_OP_RESERVED_NON_FLOAT_32_1', 'TC_OP_RESERVED_NON_FLOAT_32_2', + 'TC_OP_RESERVED_NON_FLOAT_32_3', 'TC_OP_RESERVED_NON_FLOAT_32_4', + 'TC_OP_RESERVED_NON_FLOAT_64_1', 'TC_OP_RESERVED_NON_FLOAT_64_2', + 'TC_OP_RESERVED_NON_FLOAT_64_3', 'TC_OP_RESERVED_NON_FLOAT_64_4', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', + 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', + 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', + 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', + 'TD_PERF_SEL_RESERVED_21', 'TD_PERF_SEL_RESERVED_8', + 'TD_PERF_SEL_address_cmd_poison', + 'TD_PERF_SEL_bypassLerp_wavefront', + 'TD_PERF_SEL_core_state_rams_read', + 'TD_PERF_SEL_d16_en_wavefront', 'TD_PERF_SEL_data_poison', + 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', + 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', + 'TD_PERF_SEL_done_scoreboard_is_full', + 'TD_PERF_SEL_done_scoreboard_not_empty', + 'TD_PERF_SEL_four_comp_wavefront', + 'TD_PERF_SEL_gather4_wavefront', + 'TD_PERF_SEL_gather4h_packed_wavefront', + 'TD_PERF_SEL_gather4h_wavefront', + 'TD_PERF_SEL_gather8h_packed_wavefront', 'TD_PERF_SEL_input_busy', + 'TD_PERF_SEL_input_state_fifo_full', + 'TD_PERF_SEL_ldfptr_wavefront', 'TD_PERF_SEL_lds_stall', + 'TD_PERF_SEL_load_wavefront', 'TD_PERF_SEL_lod_warn_from_ta', + 'TD_PERF_SEL_min_max_filter_wavefront', + 'TD_PERF_SEL_mixmode_instruction', 'TD_PERF_SEL_mixmode_resource', + 'TD_PERF_SEL_nofilter_busy', + 'TD_PERF_SEL_nofilter_formatters_turned_off', + 'TD_PERF_SEL_nofilter_pkr_full', + 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', + 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', + 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', + 'TD_PERF_SEL_none', 'TD_PERF_SEL_one_comp_wavefront', + 'TD_PERF_SEL_opaque_black_border', + 'TD_PERF_SEL_out_of_order_instr', + 'TD_PERF_SEL_reference_data_rams_read', + 'TD_PERF_SEL_sample_c_wavefront', 'TD_PERF_SEL_sampler_lerp_busy', + 'TD_PERF_SEL_sampler_out_busy', 'TD_PERF_SEL_sampler_pkr_full', + 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', + 'TD_PERF_SEL_status_packet', 'TD_PERF_SEL_store_wavefront', + 'TD_PERF_SEL_ta_data_stall', + 'TD_PERF_SEL_tc_cycling_of_nofilter_instr', + 'TD_PERF_SEL_tc_data_stall', 'TD_PERF_SEL_tc_ram_stall', + 'TD_PERF_SEL_tc_td_data_fifo_full', + 'TD_PERF_SEL_tc_td_ram_fifo_full', 'TD_PERF_SEL_td_busy', + 'TD_PERF_SEL_td_cycling_of_nofilter_instr', + 'TD_PERF_SEL_three_comp_wavefront', 'TD_PERF_SEL_total_num_instr', + 'TD_PERF_SEL_two_comp_wavefront', + 'TD_PERF_SEL_user_defined_border', + 'TD_PERF_SEL_wavefront_dest_is_lds', + 'TD_PERF_SEL_weight_data_rams_read', 'TD_PERF_SEL_white_border', + 'TD_PERF_SEL_write_ack_wavefront', 'TESS_ISOLINE', 'TESS_QUAD', + 'TESS_TRIANGLE', 'TEST_CLK_DIV_SEL', 'TEST_CLK_SEL', + 'TEST_CLK_SEL_0', 'TEST_CLK_SEL_1', 'TEST_CLK_SEL_2', + 'TEST_CLK_SEL_3', 'TEST_CLK_SEL_4', 'TEST_CLK_SEL_5', + 'TEST_CLK_SEL_6', 'TEST_CLK_SEL_7', 'TEST_CLK_SEL_8', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', 'TEST_CLOCK_MUX_SELECT_ENUM', + 'TEX_BC_SWIZZLE', 'TEX_BC_Swizzle_WXYZ', 'TEX_BC_Swizzle_WZYX', + 'TEX_BC_Swizzle_XWYZ', 'TEX_BC_Swizzle_XYZW', + 'TEX_BC_Swizzle_YXWZ', 'TEX_BC_Swizzle_ZYXW', + 'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack', + 'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register', + 'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP', + 'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', + 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', + 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', + 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', + 'TEX_Clamp_MirrorOnceHalfToBorder', + 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', + 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', + 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', + 'TEX_DIM', 'TEX_DepthCompareFunction_Always', + 'TEX_DepthCompareFunction_Equal', + 'TEX_DepthCompareFunction_Greater', + 'TEX_DepthCompareFunction_GreaterEqual', + 'TEX_DepthCompareFunction_Less', + 'TEX_DepthCompareFunction_LessEqual', + 'TEX_DepthCompareFunction_Never', + 'TEX_DepthCompareFunction_NotEqual', 'TEX_Dim_1D', + 'TEX_Dim_1DArray', 'TEX_Dim_2D', 'TEX_Dim_2DArray', + 'TEX_Dim_2DArray_MSAA', 'TEX_Dim_2D_MSAA', 'TEX_Dim_3D', + 'TEX_Dim_CubeMap', 'TEX_FORMAT_COMP', 'TEX_FormatComp_RESERVED_3', + 'TEX_FormatComp_Signed', 'TEX_FormatComp_Unsigned', + 'TEX_FormatComp_UnsignedBiased', 'TEX_MAX_ANISO_RATIO', + 'TEX_MIP_FILTER', 'TEX_MaxAnisoRatio_16to1', + 'TEX_MaxAnisoRatio_1to1', 'TEX_MaxAnisoRatio_2to1', + 'TEX_MaxAnisoRatio_4to1', 'TEX_MaxAnisoRatio_8to1', + 'TEX_MaxAnisoRatio_RESERVED_5', 'TEX_MaxAnisoRatio_RESERVED_6', + 'TEX_MaxAnisoRatio_RESERVED_7', 'TEX_MipFilter_Linear', + 'TEX_MipFilter_None', 'TEX_MipFilter_Point', + 'TEX_MipFilter_Point_Aniso_Adj', 'TEX_REQUEST_SIZE', + 'TEX_RequestSize_128B', 'TEX_RequestSize_2X64B', + 'TEX_RequestSize_32B', 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', + 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', + 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', + 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', + 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', + 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', + 'THICK_MICRO_TILING', 'THIN_MICRO_TILING', 'THIRTY_TWO_PIPES', + 'THREAD_TRACE_DRAW', 'THREAD_TRACE_FINISH', 'THREAD_TRACE_MARKER', + 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TILE_SPLIT', + 'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP', + 'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', + 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', + 'TMDS_CTL0_DATA_MODULATION_BIT1', + 'TMDS_CTL0_DATA_MODULATION_BIT2', + 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', + 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', + 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', + 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', + 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', + 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', + 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', + 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', + 'TMDS_CTL1_DATA_MODULATION_BIT0', + 'TMDS_CTL1_DATA_MODULATION_BIT1', + 'TMDS_CTL1_DATA_MODULATION_BIT2', + 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', + 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', + 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', + 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', + 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', + 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', + 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', + 'TMDS_CTL2_DATA_MODULATION_BIT0', + 'TMDS_CTL2_DATA_MODULATION_BIT1', + 'TMDS_CTL2_DATA_MODULATION_BIT2', + 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', + 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', + 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', + 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', + 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', + 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', + 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', + 'TMDS_CTL3_DATA_MODULATION_BIT0', + 'TMDS_CTL3_DATA_MODULATION_BIT1', + 'TMDS_CTL3_DATA_MODULATION_BIT2', + 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', + 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', + 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', + 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', + 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', + 'TMDS_CTL3_PATTERN_OUT_ENABLE', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_MUX_SELECT', + 'TMDS_MUX_SELECT_B', 'TMDS_MUX_SELECT_G', 'TMDS_MUX_SELECT_R', + 'TMDS_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', + 'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422', + 'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', + 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', + 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', + 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', + 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', + 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', + 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', + 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', + 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', + 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', + 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', + 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', + 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', + 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', + 'TRISTRIP', 'TVX_DATA_FORMAT', 'TVX_DST_SEL', 'TVX_DstSel_0f', + 'TVX_DstSel_1f', 'TVX_DstSel_Mask', 'TVX_DstSel_RESERVED_6', + 'TVX_DstSel_W', 'TVX_DstSel_X', 'TVX_DstSel_Y', 'TVX_DstSel_Z', + 'TVX_ENDIAN_SWAP', 'TVX_EndianSwap_8in16', 'TVX_EndianSwap_8in32', + 'TVX_EndianSwap_8in64', 'TVX_EndianSwap_None', 'TVX_FMT_1', + 'TVX_FMT_10_10_10_2', 'TVX_FMT_10_11_11', + 'TVX_FMT_10_11_11_FLOAT', 'TVX_FMT_11_11_10', + 'TVX_FMT_11_11_10_FLOAT', 'TVX_FMT_16', 'TVX_FMT_16_16', + 'TVX_FMT_16_16_16', 'TVX_FMT_16_16_16_16', + 'TVX_FMT_16_16_16_16_FLOAT', 'TVX_FMT_16_16_16_FLOAT', + 'TVX_FMT_16_16_FLOAT', 'TVX_FMT_16_FLOAT', 'TVX_FMT_1_5_5_5', + 'TVX_FMT_1_REVERSED', 'TVX_FMT_24_8', 'TVX_FMT_24_8_FLOAT', + 'TVX_FMT_2_10_10_10', 'TVX_FMT_32', 'TVX_FMT_32_32', + 'TVX_FMT_32_32_32', 'TVX_FMT_32_32_32_32', + 'TVX_FMT_32_32_32_32_FLOAT', 'TVX_FMT_32_32_32_FLOAT', + 'TVX_FMT_32_32_FLOAT', 'TVX_FMT_32_AS_8', 'TVX_FMT_32_AS_8_8', + 'TVX_FMT_32_FLOAT', 'TVX_FMT_3_3_2', 'TVX_FMT_4_4', + 'TVX_FMT_4_4_4_4', 'TVX_FMT_5_5_5_1', 'TVX_FMT_5_6_5', + 'TVX_FMT_5_9_9_9_SHAREDEXP', 'TVX_FMT_6_5_5', 'TVX_FMT_8', + 'TVX_FMT_8_24', 'TVX_FMT_8_24_FLOAT', 'TVX_FMT_8_8', + 'TVX_FMT_8_8_8', 'TVX_FMT_8_8_8_8', 'TVX_FMT_APC0', + 'TVX_FMT_APC1', 'TVX_FMT_APC2', 'TVX_FMT_APC3', 'TVX_FMT_APC4', + 'TVX_FMT_APC5', 'TVX_FMT_APC6', 'TVX_FMT_APC7', 'TVX_FMT_BC1', + 'TVX_FMT_BC2', 'TVX_FMT_BC3', 'TVX_FMT_BC4', 'TVX_FMT_BC5', + 'TVX_FMT_BG_RG', 'TVX_FMT_CTX1', 'TVX_FMT_GB_GR', + 'TVX_FMT_INVALID', 'TVX_FMT_RESERVED_33', 'TVX_FMT_RESERVED_36', + 'TVX_FMT_RESERVED_4', 'TVX_FMT_RESERVED_63', + 'TVX_FMT_X24_8_32_FLOAT', 'TVX_INST', 'TVX_Inst_Gather4', + 'TVX_Inst_Gather4_C', 'TVX_Inst_Gather4_C_O', + 'TVX_Inst_Gather4_O', 'TVX_Inst_GetBufferResInfo', + 'TVX_Inst_GetGradientsH', 'TVX_Inst_GetGradientsV', + 'TVX_Inst_GetLOD', 'TVX_Inst_GetNumberOfSamples', + 'TVX_Inst_GetTextureResInfo', 'TVX_Inst_KeepGradients', + 'TVX_Inst_LD', 'TVX_Inst_NormalVertexFetch', 'TVX_Inst_Pass', + 'TVX_Inst_RESERVED_15', 'TVX_Inst_RESERVED_2', 'TVX_Inst_Sample', + 'TVX_Inst_Sample_C', 'TVX_Inst_Sample_C_G', + 'TVX_Inst_Sample_C_G_LB', 'TVX_Inst_Sample_C_L', + 'TVX_Inst_Sample_C_LB', 'TVX_Inst_Sample_C_LZ', + 'TVX_Inst_Sample_G', 'TVX_Inst_Sample_G_LB', 'TVX_Inst_Sample_L', + 'TVX_Inst_Sample_LB', 'TVX_Inst_Sample_LZ', + 'TVX_Inst_SemanticVertexFetch', 'TVX_Inst_SetGradientsH', + 'TVX_Inst_SetGradientsV', 'TVX_Inst_SetTextureOffsets', + 'TVX_NUM_FORMAT_ALL', 'TVX_NumFormatAll_Int', + 'TVX_NumFormatAll_Norm', 'TVX_NumFormatAll_RESERVED_3', + 'TVX_NumFormatAll_Scaled', 'TVX_SRC_SEL', 'TVX_SRFModeAll_NZ', + 'TVX_SRFModeAll_ZCMO', 'TVX_SRF_MODE_ALL', 'TVX_SrcSel_0f', + 'TVX_SrcSel_1f', 'TVX_SrcSel_W', 'TVX_SrcSel_X', 'TVX_SrcSel_Y', + 'TVX_SrcSel_Z', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', + 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', + 'TVX_Type_ValidVertexBuffer', 'TWO_BANKS', 'TWO_FRAGMENTS', + 'TWO_PIPES', 'TWO_RB_PER_SE', 'TWO_SHADER_ENGINS', 'TileSplit', + 'TileType', 'UCONFIG_SPACE_END', 'UCONFIG_SPACE_START', + 'UNCACHED_RD', 'UNCACHED_WR', 'UNDEF', 'UNSIGNED', + 'UTCL0FaultType', 'UTCL0RequestType', 'UTCL0_TYPE_BYPASS', + 'UTCL0_TYPE_NORMAL', 'UTCL0_TYPE_SHOOTDOWN', + 'UTCL0_XNACK_NO_RETRY', 'UTCL0_XNACK_PRT', 'UTCL0_XNACK_RETRY', + 'UTCL0_XNACK_SUCCESS', 'UTCL1FaultType', 'UTCL1PerfSel', + 'UTCL1RequestType', 'UTCL1_PERF_SEL_BYPASS_REQS', + 'UTCL1_PERF_SEL_HITS', 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', + 'UTCL1_PERF_SEL_MISSES', 'UTCL1_PERF_SEL_NONE', + 'UTCL1_PERF_SEL_NONRANGE_INV_REQS', + 'UTCL1_PERF_SEL_NUM_BIGK_PAGES', + 'UTCL1_PERF_SEL_NUM_SMALLK_PAGES', + 'UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM', + 'UTCL1_PERF_SEL_RANGE_INV_REQS', 'UTCL1_PERF_SEL_REQS', + 'UTCL1_PERF_SEL_STALL_MH_CAM_FULL', + 'UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL', + 'UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS', + 'UTCL1_PERF_SEL_TOTAL_UTCL2_REQS', 'UTCL1_TYPE_BYPASS', + 'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN', + 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY', + 'UTCL1_XNACK_SUCCESS', 'UVDFC_BITSTREAM_ADDR', + 'UVDFC_BITSTREAM_SIZE', 'UVDFC_DECODED_ADDR', + 'UVDFC_DISPLAY_ADDR', 'UVDFC_DISPLAY_PITCH', + 'UVDFC_DISPLAY_TILING', 'UVDFC_EOD', 'UVDFC_FENCE', + 'UVDFC_ITBUF_ADDR', 'UVDFC_MBLOCK_ADDR', 'UVDFC_TRAP', + 'UVDFirmwareCommand', 'VC_AND_TC', 'VC_ONLY', + 'VGT_CACHE_INVALID_MODE', 'VGT_DETECT_ONE', 'VGT_DETECT_ZERO', + 'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE', 'VGT_DI_MAJOR_MODE_SELECT', + 'VGT_DI_PRIM_TYPE', 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', + 'VGT_DMA_BUF_RING', 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', + 'VGT_DMA_PTR_UPDATE', 'VGT_DMA_SWAP_16_BIT', + 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', 'VGT_DMA_SWAP_NONE', + 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', 'VGT_FLUSH', + 'VGT_GROUP_CONV_SEL', 'VGT_GRP_2D_COPY_RECT_V0', + 'VGT_GRP_2D_COPY_RECT_V1', 'VGT_GRP_2D_COPY_RECT_V2', + 'VGT_GRP_2D_COPY_RECT_V3', 'VGT_GRP_2D_FILL_RECT', + 'VGT_GRP_2D_LINE', 'VGT_GRP_2D_RECT', 'VGT_GRP_2D_TRI', + 'VGT_GRP_3D_LINE', 'VGT_GRP_3D_LINE_ADJ', 'VGT_GRP_3D_PATCH', + 'VGT_GRP_3D_POINT', 'VGT_GRP_3D_QUAD', 'VGT_GRP_3D_RECT', + 'VGT_GRP_3D_TRI', 'VGT_GRP_3D_TRI_ADJ', 'VGT_GRP_AUTO_PRIM', + 'VGT_GRP_FAN', 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', + 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_LIST', + 'VGT_GRP_LOOP', 'VGT_GRP_POLYGON', 'VGT_GRP_PRIM_INDEX_LINE', + 'VGT_GRP_PRIM_INDEX_QUAD', 'VGT_GRP_PRIM_INDEX_TRI', + 'VGT_GRP_PRIM_ORDER', 'VGT_GRP_PRIM_TYPE', 'VGT_GRP_SINT_16', + 'VGT_GRP_SINT_32', 'VGT_GRP_STRIP', 'VGT_GRP_UINT_16', + 'VGT_GRP_UINT_32', 'VGT_GS_CUT_MODE', 'VGT_GS_MODE_TYPE', + 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', 'VGT_INDEX_32', + 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', 'VGT_OUTPATH_GS_BLOCK', + 'VGT_OUTPATH_HS_BLOCK', 'VGT_OUTPATH_PRIM_GEN', + 'VGT_OUTPATH_SELECT', 'VGT_OUTPATH_TE_GS_BLOCK', + 'VGT_OUTPATH_TE_OUTPUT', 'VGT_OUTPATH_TE_PRIM_GEN', + 'VGT_OUTPATH_VTX_REUSE', 'VGT_OUT_2D_RECT', 'VGT_OUT_LINE', + 'VGT_OUT_LINE_ADJ', 'VGT_OUT_PATCH', 'VGT_OUT_POINT', + 'VGT_OUT_PRIM_TYPE', 'VGT_OUT_RECT_V0', 'VGT_OUT_RECT_V1', + 'VGT_OUT_RECT_V2', 'VGT_OUT_RECT_V3', 'VGT_OUT_TRI', + 'VGT_OUT_TRI_ADJ', 'VGT_POLICY_BYPASS', 'VGT_POLICY_LRU', + 'VGT_POLICY_STREAM', 'VGT_RDREQ_POLICY', 'VGT_STAGES_ES_EN', + 'VGT_STAGES_GS_EN', 'VGT_STAGES_HS_EN', 'VGT_STAGES_LS_EN', + 'VGT_STAGES_VS_EN', 'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC', + 'VGT_TESS_PARTITION', 'VGT_TESS_TOPOLOGY', 'VGT_TESS_TYPE', + 'VGT_TE_PRIM_INDEX_LINE', 'VGT_TE_PRIM_INDEX_QUAD', + 'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD', 'VID_ENHANCED_MODE', + 'VID_NORMAL_FRAME_MODE', 'VID_STREAM_DISABLE_MASKED', + 'VID_STREAM_DISABLE_UNMASK', 'VMEMCMD_RETURN_IN_ORDER', + 'VMEMCMD_RETURN_IN_ORDER_READ', 'VMEMCMD_RETURN_ORDER', + 'VMEMCMD_RETURN_OUT_OF_ORDER', 'VMID_SZ', 'VMPG_SIZE', + 'VMPG_SIZE_4KB', 'VMPG_SIZE_64KB', 'VREADY_AT_OR_AFTER_VSYNC', + 'VREADY_BEFORE_VSYNC', 'VSYNC_CNT_LATCH_MASK', + 'VSYNC_CNT_LATCH_MASK_0', 'VSYNC_CNT_LATCH_MASK_1', + 'VSYNC_CNT_REFCLK_SEL', 'VSYNC_CNT_REFCLK_SEL_0', + 'VSYNC_CNT_REFCLK_SEL_1', 'VSYNC_CNT_RESET_SEL', + 'VSYNC_CNT_RESET_SEL_0', 'VSYNC_CNT_RESET_SEL_1', + 'VS_PARTIAL_FLUSH', 'VS_PS', 'VS_STAGE_COPY_SHADER', + 'VS_STAGE_DS', 'VS_STAGE_REAL', 'VTG_SEL_0', 'VTG_SEL_1', + 'VTG_SEL_2', 'VTG_SEL_3', 'VTG_SEL_4', 'VTG_SEL_5', 'VTX_CLAMP', + 'VTX_Clamp_ClampToNAN', 'VTX_Clamp_ClampToZero', 'VTX_FETCH_TYPE', + 'VTX_FORMAT_COMP_ALL', 'VTX_FetchType_InstanceData', + 'VTX_FetchType_NoIndexOffset', 'VTX_FetchType_RESERVED_3', + 'VTX_FetchType_VertexData', 'VTX_FormatCompAll_Signed', + 'VTX_FormatCompAll_Unsigned', 'VTX_MEM_REQUEST_SIZE', + 'VTX_MemRequestSize_32B', 'VTX_MemRequestSize_64B', + 'WBSCL_BACKPRESSURE_CNT_DISABLE', 'WBSCL_BACKPRESSURE_CNT_ENABLE', + 'WBSCL_BACKPRESSURE_CNT_EN_ENUM', 'WBSCL_COEF_CHROMA_HORZ_FILTER', + 'WBSCL_COEF_CHROMA_VERT_FILTER', 'WBSCL_COEF_FILTER_TYPE_SEL', + 'WBSCL_COEF_LUMA_HORZ_FILTER', 'WBSCL_COEF_LUMA_VERT_FILTER', + 'WBSCL_COEF_RAM_FILTER_TYPE_ENUM', + 'WBSCL_COEF_RAM_FILTER_TYPE_HC', 'WBSCL_COEF_RAM_FILTER_TYPE_HL', + 'WBSCL_COEF_RAM_FILTER_TYPE_VC', 'WBSCL_COEF_RAM_FILTER_TYPE_VL', + 'WBSCL_COEF_RAM_PHASE0', 'WBSCL_COEF_RAM_PHASE1', + 'WBSCL_COEF_RAM_PHASE2', 'WBSCL_COEF_RAM_PHASE3', + 'WBSCL_COEF_RAM_PHASE4', 'WBSCL_COEF_RAM_PHASE5', + 'WBSCL_COEF_RAM_PHASE6', 'WBSCL_COEF_RAM_PHASE7', + 'WBSCL_COEF_RAM_PHASE8', 'WBSCL_COEF_RAM_PHASE_ENUM', + 'WBSCL_COEF_RAM_RD_SEL_0', 'WBSCL_COEF_RAM_RD_SEL_1', + 'WBSCL_COEF_RAM_RD_SEL_ENUM', 'WBSCL_COEF_RAM_SEL_0', + 'WBSCL_COEF_RAM_SEL_1', 'WBSCL_COEF_RAM_SEL_ENUM', + 'WBSCL_COEF_RAM_TAP_COEF_DISABLE', + 'WBSCL_COEF_RAM_TAP_COEF_ENABLE', + 'WBSCL_COEF_RAM_TAP_COEF_EN_ENUM', 'WBSCL_COEF_RAM_TAP_PAIR_IDX0', + 'WBSCL_COEF_RAM_TAP_PAIR_IDX1', 'WBSCL_COEF_RAM_TAP_PAIR_IDX2', + 'WBSCL_COEF_RAM_TAP_PAIR_IDX3', 'WBSCL_COEF_RAM_TAP_PAIR_IDX4', + 'WBSCL_COEF_RAM_TAP_PAIR_IDX5', + 'WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM', + 'WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM', + 'WBSCL_DATA_OVERFLOW_INT_TYPE_HW', + 'WBSCL_DATA_OVERFLOW_INT_TYPE_REG', + 'WBSCL_HOST_CONFLICT_INT_TYPE_ENUM', + 'WBSCL_HOST_CONFLICT_INT_TYPE_HW', + 'WBSCL_HOST_CONFLICT_INT_TYPE_REG', 'WBSCL_LB_MEM_PWR_FORCE_DS', + 'WBSCL_LB_MEM_PWR_FORCE_ENUM', 'WBSCL_LB_MEM_PWR_FORCE_LS', + 'WBSCL_LB_MEM_PWR_FORCE_NO', 'WBSCL_LB_MEM_PWR_FORCE_SD', + 'WBSCL_LB_MEM_PWR_MODE_SEL_DS', 'WBSCL_LB_MEM_PWR_MODE_SEL_ENUM', + 'WBSCL_LB_MEM_PWR_MODE_SEL_LS', 'WBSCL_LB_MEM_PWR_MODE_SEL_ON', + 'WBSCL_LB_MEM_PWR_MODE_SEL_SD', 'WBSCL_LUT_MEM_PWR_STATE_ENUM', + 'WBSCL_LUT_MEM_PWR_STATE_LS', 'WBSCL_LUT_MEM_PWR_STATE_ON', + 'WBSCL_LUT_MEM_PWR_STATE_RESERVED2', + 'WBSCL_LUT_MEM_PWR_STATE_RESERVED3', 'WBSCL_MEM_PWR_STATE_DS', + 'WBSCL_MEM_PWR_STATE_ENUM', 'WBSCL_MEM_PWR_STATE_LS', + 'WBSCL_MEM_PWR_STATE_ON', 'WBSCL_MEM_PWR_STATE_SD', + 'WBSCL_MODE_SCALING_444_BYPASS', + 'WBSCL_MODE_SCALING_444_RGB_ENABLE', + 'WBSCL_MODE_SCALING_444_YCBCR_ENABLE', + 'WBSCL_MODE_SCALING_YCBCR_ENABLE', 'WBSCL_MODE_SEL', + 'WBSCL_NUM_OF_TAPS0', 'WBSCL_NUM_OF_TAPS1', 'WBSCL_NUM_OF_TAPS10', + 'WBSCL_NUM_OF_TAPS11', 'WBSCL_NUM_OF_TAPS2', 'WBSCL_NUM_OF_TAPS3', + 'WBSCL_NUM_OF_TAPS4', 'WBSCL_NUM_OF_TAPS5', 'WBSCL_NUM_OF_TAPS6', + 'WBSCL_NUM_OF_TAPS7', 'WBSCL_NUM_OF_TAPS8', 'WBSCL_NUM_OF_TAPS9', + 'WBSCL_NUM_OF_TAPS_ENUM', 'WBSCL_OUTSIDE_PIX_STRATEGY_BLACK', + 'WBSCL_OUTSIDE_PIX_STRATEGY_EDGE', + 'WBSCL_OUTSIDE_PIX_STRATEGY_ENUM', 'WBSCL_PIXEL_DEPTH', + 'WBSCL_STATUS_ACK_CLR', 'WBSCL_STATUS_ACK_ENUM', + 'WBSCL_STATUS_ACK_NCLR', 'WBSCL_STATUS_MASK_DISABLE', + 'WBSCL_STATUS_MASK_ENABLE', 'WBSCL_STATUS_MASK_ENUM', + 'WBSCL_TEST_CRC_CONT_DISABLE', 'WBSCL_TEST_CRC_CONT_ENABLE', + 'WBSCL_TEST_CRC_CONT_EN_ENUM', 'WBSCL_TEST_CRC_DISABLE', + 'WBSCL_TEST_CRC_ENABLE', 'WBSCL_TEST_CRC_EN_ENUM', + 'WBSCL_TEST_CRC_MASKED', 'WBSCL_TEST_CRC_MASK_ENUM', + 'WBSCL_TEST_CRC_UNMASKED', 'WB_CLK_GATE_DISABLE', + 'WB_CLK_GATE_DIS_ENUM', 'WB_CLK_GATE_ENABLE', 'WB_ENABLE_ENUM', + 'WB_EN_DISABLE', 'WB_EN_ENABLE', 'WB_MEM_PWR_DISABLE', + 'WB_MEM_PWR_DIS_ENUM', 'WB_MEM_PWR_ENABLE', + 'WB_RAM_PW_SAVE_MODE_ENUM', 'WB_RAM_PW_SAVE_MODE_LS', + 'WB_RAM_PW_SAVE_MODE_SD', 'WB_SOFT_RESET_ENUM', + 'WB_SOFT_RESET_NEG', 'WB_SOFT_RESET_POS', 'WB_TEST_CLK_SEL_ENUM', + 'WB_TEST_CLK_SEL_PERM', 'WB_TEST_CLK_SEL_REG', + 'WB_TEST_CLK_SEL_WB', 'WB_TEST_CLK_SEL_WBSCL', + 'WD_IA_DRAW_REG_XFER', 'WD_IA_DRAW_REG_XFER_GE_CNTL', + 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', + 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', + 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', + 'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO', + 'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD', + 'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE', + 'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA', + 'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX', + 'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER', + 'WRITE_BASE_ONLY', 'WRITE_BOTH', 'WritePolicy', 'XNORM', + 'XNORM_A', 'XNORM_B', 'XTAL_REF_CLOCK_SOURCE_SEL', + 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', + 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', + 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'Y10_CbCr1010_420_PLANAR', + 'Y10_CrCb1010_420_PLANAR', 'Y12_CbCr1212_420_PLANAR', + 'Y12_CrCb1212_420_PLANAR', 'Y8_CbCr88_420_PLANAR', + 'Y8_CrCb88_420_PLANAR', 'YCbYCr10101010_422_PACKED', + 'YCbYCr12121212_422_PACKED', 'YCbYCr8888_422_PACKED', + 'YCrCbA16161616_10LSB', 'YCrCbA16161616_10MSB', + 'YCrCbA16161616_12LSB', 'YCrCbA16161616_12MSB', 'YCrCbA8888', + 'YCrYCb10101010_422_PACKED', 'YCrYCb12121212_422_PACKED', + 'YCrYCb8888_422_PACKED', 'Y_G_DATA_ON_ALPHA_PORT', + 'Y_G_DATA_ON_CB_B_PORT', 'Y_G_DATA_ON_CR_R_PORT', + 'Y_G_DATA_ON_Y_G_PORT', 'ZFormat', 'ZLimitSumm', 'ZModeForce', + 'ZOrder', 'ZPASS_DISABLE', 'ZPASS_DONE', 'ZPASS_PIXELS', + 'ZPASS_SAMPLES', 'ZSamplePosition', 'Z_16', 'Z_24', 'Z_32_FLOAT', + 'Z_INVALID', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID', + 'ZpassControl', '_navi10_ENUM_HEADER', 'ge_assembler_busy', + 'ge_assembler_stalled', 'ge_cm_reading_stalled', + 'ge_cm_stalled_by_gog', 'ge_cm_stalled_by_gsfetch_done', + 'ge_dma_busy', 'ge_dma_lat_bin_0', 'ge_dma_lat_bin_1', + 'ge_dma_lat_bin_2', 'ge_dma_lat_bin_3', 'ge_dma_lat_bin_4', + 'ge_dma_lat_bin_5', 'ge_dma_lat_bin_6', 'ge_dma_lat_bin_7', + 'ge_dma_return', 'ge_dma_utcl1_consecutive_retry_event', + 'ge_dma_utcl1_request_event', 'ge_dma_utcl1_retry_event', + 'ge_dma_utcl1_stall_event', 'ge_dma_utcl1_stall_utcl2_event', + 'ge_dma_utcl1_translation_hit_event', + 'ge_dma_utcl1_translation_miss_event', + 'ge_dma_utcl2_stall_on_trans', 'ge_dma_utcl2_trans_ack', + 'ge_dma_utcl2_trans_xnack', 'ge_ds_cache_hits', 'ge_ds_prims', + 'ge_es_done', 'ge_es_done_latency', 'ge_es_flush', + 'ge_es_ring_high_water_mark', 'ge_es_thread_groups', + 'ge_esthread_stalled_es_rb_full', 'ge_esthread_stalled_spi_bp', + 'ge_esvert_stalled_es_tbl', 'ge_esvert_stalled_gs_event', + 'ge_esvert_stalled_gs_tbl', 'ge_esvert_stalled_gsprim', + 'ge_gea_dma_starved', 'ge_gog_busy', 'ge_gog_out_indx_stalled', + 'ge_gog_out_prim_stalled', 'ge_gog_vs_tbl_stalled', + 'ge_gs_cache_hits', 'ge_gs_counters_avail_stalled', 'ge_gs_done', + 'ge_gs_done_latency', 'ge_gs_event_stall', + 'ge_gs_issue_rtr_stalled', 'ge_gs_rb_space_avail_stalled', + 'ge_gs_ring_high_water_mark', 'ge_gsprim_stalled_es_tbl', + 'ge_gsprim_stalled_esvert', 'ge_gsprim_stalled_gs_event', + 'ge_gsprim_stalled_gs_tbl', 'ge_gsthread_stalled', 'ge_hs_done', + 'ge_hs_done_latency', 'ge_hs_done_se0', 'ge_hs_done_se1', + 'ge_hs_done_se2_reserved', 'ge_hs_done_se3_reserved', + 'ge_hs_tfm_stall', 'ge_hs_tgs_active_high_water_mark', + 'ge_hs_thread_groups', 'ge_inside_tf_bin_0', 'ge_inside_tf_bin_1', + 'ge_inside_tf_bin_2', 'ge_inside_tf_bin_3', 'ge_inside_tf_bin_4', + 'ge_inside_tf_bin_5', 'ge_inside_tf_bin_6', 'ge_inside_tf_bin_7', + 'ge_inside_tf_bin_8', 'ge_ls_done', 'ge_ls_done_latency', + 'ge_null_patch', 'ge_pa_clipp_eop', 'ge_pa_clipp_is_event', + 'ge_pa_clipp_new_vtx_vect', 'ge_pa_clipp_null_prim', + 'ge_pa_clipp_send', 'ge_pa_clipp_send_not_event', + 'ge_pa_clipp_stalled', 'ge_pa_clipp_starved_busy', + 'ge_pa_clipp_starved_idle', 'ge_pa_clipp_valid_prim', + 'ge_pa_clips_send', 'ge_pa_clips_stalled', 'ge_pa_clipv_send', + 'ge_pa_clipv_stalled', 'ge_rbiu_di_fifo_stalled', + 'ge_rbiu_di_fifo_starved', 'ge_rbiu_dr_fifo_stalled', + 'ge_rbiu_dr_fifo_starved', 'ge_reused_es_indices', + 'ge_reused_vs_indices', 'ge_sclk_core_vld', 'ge_sclk_gs_vld', + 'ge_sclk_input_vld', 'ge_sclk_leg_gs_arb_vld', 'ge_sclk_ngg_vld', + 'ge_sclk_reg_vld', 'ge_sclk_te11_vld', 'ge_sclk_vr_vld', + 'ge_sclk_wd_te11_vld', 'ge_spi_esvert_eov', + 'ge_spi_esvert_stalled', 'ge_spi_esvert_starved_busy', + 'ge_spi_esvert_valid', 'ge_spi_eswave_is_event', + 'ge_spi_eswave_send', 'ge_spi_gsprim_cont', 'ge_spi_gsprim_eov', + 'ge_spi_gsprim_stalled', 'ge_spi_gsprim_starved_busy', + 'ge_spi_gsprim_starved_idle', 'ge_spi_gsprim_valid', + 'ge_spi_gssubgrp_is_event', 'ge_spi_gssubgrp_send', + 'ge_spi_gswave_is_event', 'ge_spi_gswave_send', + 'ge_spi_hsvert_eov', 'ge_spi_hsvert_stalled', + 'ge_spi_hsvert_starved_busy', 'ge_spi_hsvert_valid', + 'ge_spi_hswave_is_event', 'ge_spi_hswave_send', + 'ge_spi_lsvert_eov', 'ge_spi_lsvert_stalled', + 'ge_spi_lsvert_starved_busy', 'ge_spi_lsvert_starved_idle', + 'ge_spi_lsvert_valid', 'ge_spi_lswave_is_event', + 'ge_spi_lswave_send', 'ge_spi_vsvert_eov', 'ge_spi_vsvert_send', + 'ge_spi_vsvert_stalled', 'ge_spi_vsvert_starved_busy', + 'ge_spi_vsvert_starved_idle', 'ge_spi_vswave_is_event', + 'ge_spi_vswave_send', 'ge_starved_on_hs_done', 'ge_stat_busy', + 'ge_stat_combined_busy', 'ge_stat_no_dma_busy', + 'ge_strmout_stalled', 'ge_te11_busy', 'ge_te11_starved', + 'ge_tfreq_lat_bin_0', 'ge_tfreq_lat_bin_1', 'ge_tfreq_lat_bin_2', + 'ge_tfreq_lat_bin_3', 'ge_tfreq_lat_bin_4', 'ge_tfreq_lat_bin_5', + 'ge_tfreq_lat_bin_6', 'ge_tfreq_lat_bin_7', + 'ge_tfreq_utcl1_consecutive_retry_event', + 'ge_tfreq_utcl1_request_event', 'ge_tfreq_utcl1_retry_event', + 'ge_tfreq_utcl1_stall_event', 'ge_tfreq_utcl1_stall_utcl2_event', + 'ge_tfreq_utcl1_translation_hit_event', + 'ge_tfreq_utcl1_translation_miss_event', + 'ge_tfreq_utcl2_stall_on_trans', 'ge_tfreq_utcl2_trans_ack', + 'ge_tfreq_utcl2_trans_xnack', 'ge_vs_cache_hits', 'ge_vs_done', + 'ge_vs_pc_stall', 'ge_vs_table_high_water_mark', + 'ge_vs_thread_groups', 'ge_vsvert_api_send', 'ge_vsvert_ds_send', + 'ge_wait_for_es_done_stalled', 'ge_waveid_stalled'] diff --git a/tinygrad_repo/tinygrad/runtime/autogen/am/soc21.py b/tinygrad_repo/tinygrad/runtime/autogen/am/soc21.py new file mode 100644 index 000000000..34a95940d --- /dev/null +++ b/tinygrad_repo/tinygrad/runtime/autogen/am/soc21.py @@ -0,0 +1,39083 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_soc21_ENUM_HEADER = True # macro +SQ_WAVE_TYPE_PS0 = 0x00000000 # macro +SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro +SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro +SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro +SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro +SQIND_WAVE_HWREGS_OFFSET = 0x00000100 # macro +SQIND_WAVE_HWREGS_SIZE = 0x00000100 # macro +SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro +SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro +SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro +SQIND_WAVE_VGPRS_SIZE = 0x00000400 # macro +SQ_GFXDEC_BEGIN = 0x0000a000 # macro +SQ_GFXDEC_END = 0x0000c000 # macro +SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro +SQDEC_BEGIN = 0x00002300 # macro +SQDEC_END = 0x000023ff # macro +SQPERFSDEC_BEGIN = 0x0000d9c0 # macro +SQPERFSDEC_END = 0x0000da40 # macro +SQPERFDDEC_BEGIN = 0x0000d1c0 # macro +SQPERFDDEC_END = 0x0000d240 # macro +SQGFXUDEC_BEGIN = 0x0000c330 # macro +SQGFXUDEC_END = 0x0000c380 # macro +SQPWRDEC_BEGIN = 0x0000f08c # macro +SQPWRDEC_END = 0x0000f094 # macro +SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro +SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro +SQ_MAX_PGM_SGPRS = 0x00000068 # macro +SQ_MAX_PGM_VGPRS = 0x00000100 # macro +SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro +SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro +SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro +SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro +SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro +SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro +SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro +SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro +SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro +SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro +SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro +INST_ID_PRIV_START = 0x80000000 # macro +INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro +INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro +INST_ID_HW_TRAP = 0xfffffff2 # macro +INST_ID_KILL_SEQ = 0xfffffff3 # macro +INST_ID_SPI_WREXEC = 0xfffffff4 # macro +INST_ID_HW_TRAP_GET_TBA = 0xfffffff5 # macro +INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro +SIMM16_WAITCNT_EXP_CNT_START = 0x00000000 # macro +SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_LGKM_CNT_START = 0x00000004 # macro +SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000006 # macro +SIMM16_WAITCNT_VM_CNT_START = 0x0000000a # macro +SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000006 # macro +SIMM16_WAITCNT_DEPCTR_SA_SDST_START = 0x00000000 # macro +SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_VCC_START = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VM_VSRC_START = 0x00000002 # macro +SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START = 0x00000006 # macro +SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_SSRC_START = 0x00000007 # macro +SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_SDST_START = 0x00000008 # macro +SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_DEPCTR_VA_VDST_START = 0x0000000b # macro +SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE = 0x00000005 # macro +SIMM16_WAIT_EVENT_EXP_RDY_START = 0x00000000 # macro +SIMM16_WAIT_EVENT_EXP_RDY_SIZE = 0x00000001 # macro +SQ_WAVE_IB_DEP_SA_SDST_SIZE = 0x00000004 # macro +SQ_WAVE_IB_DEP_SA_EXEC_SIZE = 0x00000002 # macro +SQ_WAVE_IB_DEP_SA_M0_SIZE = 0x00000001 # macro +SQ_WAVE_IB_DEP_VM_VSRC_SIZE = 0x00000004 # macro +SQ_WAVE_IB_DEP_HOLD_CNT_SIZE = 0x00000001 # macro +SQ_WAVE_IB_DEP_VA_SSRC_SIZE = 0x00000003 # macro +SQ_WAVE_IB_DEP_VA_SDST_SIZE = 0x00000004 # macro +SQ_WAVE_IB_DEP_VA_VCC_SIZE = 0x00000003 # macro +SQ_WAVE_IB_DEP_VA_EXEC_SIZE = 0x00000002 # macro +SQ_WAVE_IB_DEP_VA_VDST_SIZE = 0x00000005 # macro +SQ_WAVE_IB_DEP_LDS_DIR_SIZE = 0x00000003 # macro +SQ_EDC_FUE_CNTL_SIMD0 = 0x00000000 # macro +SQ_EDC_FUE_CNTL_SIMD1 = 0x00000001 # macro +SQ_EDC_FUE_CNTL_SIMD2 = 0x00000002 # macro +SQ_EDC_FUE_CNTL_SIMD3 = 0x00000003 # macro +SQ_EDC_FUE_CNTL_SQ = 0x00000004 # macro +SQ_EDC_FUE_CNTL_LDS = 0x00000005 # macro +SQ_EDC_FUE_CNTL_TD = 0x00000006 # macro +SQ_EDC_FUE_CNTL_TA = 0x00000007 # macro +SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro +CSDATA_TYPE_WIDTH = 0x00000002 # macro +CSDATA_ADDR_WIDTH = 0x00000007 # macro +CSDATA_DATA_WIDTH = 0x00000020 # macro +CSCNTL_TYPE_WIDTH = 0x00000002 # macro +CSCNTL_ADDR_WIDTH = 0x00000007 # macro +CSCNTL_DATA_WIDTH = 0x00000020 # macro +GSTHREADID_SIZE = 0x00000002 # macro +GB_TILING_CONFIG_TABLE_SIZE = 0x00000020 # macro +GB_TILING_CONFIG_MACROTABLE_SIZE = 0x00000010 # macro +SEM_ECC_ERROR = 0x00000000 # macro +SEM_TRANS_ERROR = 0x00000001 # macro +SEM_RESP_FAILED = 0x00000002 # macro +SEM_RESP_PASSED = 0x00000003 # macro +IQ_QUEUE_SLEEP = 0x00000000 # macro +IQ_OFFLOAD_RETRY = 0x00000001 # macro +IQ_SCH_WAVE_MSG = 0x00000002 # macro +IQ_SEM_REARM = 0x00000003 # macro +IQ_DEQUEUE_RETRY = 0x00000004 # macro +IQ_INTR_TYPE_PQ = 0x00000000 # macro +IQ_INTR_TYPE_IB = 0x00000001 # macro +IQ_INTR_TYPE_MQD = 0x00000002 # macro +VMID_SZ = 0x00000004 # macro +SRCID_RLC = 0x00000000 # macro +SRCID_RLCV = 0x00000006 # macro +SRCID_SECURE_CP = 0x00000007 # macro +SRCID_NONSECURE_CP = 0x00000001 # macro +SRCID_SECURE_CP_RCIU = 0x00000007 # macro +SRCID_NONSECURE_CP_RCIU = 0x00000001 # macro +CONFIG_SPACE_START = 0x00002000 # macro +CONFIG_SPACE_END = 0x00009fff # macro +CONFIG_SPACE1_START = 0x00002000 # macro +CONFIG_SPACE1_END = 0x00002bff # macro +CONFIG_SPACE2_START = 0x00003000 # macro +CONFIG_SPACE2_END = 0x00009fff # macro +UCONFIG_SPACE_START = 0x0000c000 # macro +UCONFIG_SPACE_END = 0x0000ffff # macro +PERSISTENT_SPACE_START = 0x00002c00 # macro +PERSISTENT_SPACE_END = 0x00002fff # macro +CONTEXT_SPACE_START = 0x0000a000 # macro +CONTEXT_SPACE_END = 0x0000a3ff # macro +ROM_SIGNATURE = 0x0000aa55 # macro + +# values for enumeration 'DSM_DATA_SEL' +DSM_DATA_SEL__enumvalues = { + 0: 'DSM_DATA_SEL_DISABLE', + 1: 'DSM_DATA_SEL_0', + 2: 'DSM_DATA_SEL_1', + 3: 'DSM_DATA_SEL_BOTH', +} +DSM_DATA_SEL_DISABLE = 0 +DSM_DATA_SEL_0 = 1 +DSM_DATA_SEL_1 = 2 +DSM_DATA_SEL_BOTH = 3 +DSM_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_ENABLE_ERROR_INJECT' +DSM_ENABLE_ERROR_INJECT__enumvalues = { + 0: 'DSM_ENABLE_ERROR_INJECT_FED_IN', + 1: 'DSM_ENABLE_ERROR_INJECT_SINGLE', + 2: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', + 3: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', +} +DSM_ENABLE_ERROR_INJECT_FED_IN = 0 +DSM_ENABLE_ERROR_INJECT_SINGLE = 1 +DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 2 +DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 3 +DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_SELECT_INJECT_DELAY' +DSM_SELECT_INJECT_DELAY__enumvalues = { + 0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY', + 1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', +} +DSM_SELECT_INJECT_DELAY_NO_DELAY = 0 +DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1 +DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_SINGLE_WRITE' +DSM_SINGLE_WRITE__enumvalues = { + 0: 'DSM_SINGLE_WRITE_DIS', + 1: 'DSM_SINGLE_WRITE_EN', +} +DSM_SINGLE_WRITE_DIS = 0 +DSM_SINGLE_WRITE_EN = 1 +DSM_SINGLE_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_NUM_SIMD_PER_CU' +ENUM_NUM_SIMD_PER_CU__enumvalues = { + 2: 'NUM_SIMD_PER_CU', +} +NUM_SIMD_PER_CU = 2 +ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum + +# values for enumeration 'GATCL1RequestType' +GATCL1RequestType__enumvalues = { + 0: 'GATCL1_TYPE_NORMAL', + 1: 'GATCL1_TYPE_SHOOTDOWN', + 2: 'GATCL1_TYPE_BYPASS', +} +GATCL1_TYPE_NORMAL = 0 +GATCL1_TYPE_SHOOTDOWN = 1 +GATCL1_TYPE_BYPASS = 2 +GATCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'GL0V_CACHE_POLICIES' +GL0V_CACHE_POLICIES__enumvalues = { + 0: 'GL0V_CACHE_POLICY_MISS_LRU', + 1: 'GL0V_CACHE_POLICY_MISS_EVICT', + 2: 'GL0V_CACHE_POLICY_HIT_LRU', + 3: 'GL0V_CACHE_POLICY_HIT_EVICT', +} +GL0V_CACHE_POLICY_MISS_LRU = 0 +GL0V_CACHE_POLICY_MISS_EVICT = 1 +GL0V_CACHE_POLICY_HIT_LRU = 2 +GL0V_CACHE_POLICY_HIT_EVICT = 3 +GL0V_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL1_CACHE_POLICIES' +GL1_CACHE_POLICIES__enumvalues = { + 0: 'GL1_CACHE_POLICY_MISS_LRU', + 1: 'GL1_CACHE_POLICY_MISS_EVICT', + 2: 'GL1_CACHE_POLICY_HIT_LRU', + 3: 'GL1_CACHE_POLICY_HIT_EVICT', +} +GL1_CACHE_POLICY_MISS_LRU = 0 +GL1_CACHE_POLICY_MISS_EVICT = 1 +GL1_CACHE_POLICY_HIT_LRU = 2 +GL1_CACHE_POLICY_HIT_EVICT = 3 +GL1_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL1_CACHE_STORE_POLICIES' +GL1_CACHE_STORE_POLICIES__enumvalues = { + 0: 'GL1_CACHE_STORE_POLICY_BYPASS', +} +GL1_CACHE_STORE_POLICY_BYPASS = 0 +GL1_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_CACHE_POLICIES' +GL2_CACHE_POLICIES__enumvalues = { + 0: 'GL2_CACHE_POLICY_LRU', + 1: 'GL2_CACHE_POLICY_STREAM', + 2: 'GL2_CACHE_POLICY_NOA', + 3: 'GL2_CACHE_POLICY_BYPASS', +} +GL2_CACHE_POLICY_LRU = 0 +GL2_CACHE_POLICY_STREAM = 1 +GL2_CACHE_POLICY_NOA = 2 +GL2_CACHE_POLICY_BYPASS = 3 +GL2_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'Hdp_SurfaceEndian' +Hdp_SurfaceEndian__enumvalues = { + 0: 'HDP_ENDIAN_NONE', + 1: 'HDP_ENDIAN_8IN16', + 2: 'HDP_ENDIAN_8IN32', + 3: 'HDP_ENDIAN_8IN64', +} +HDP_ENDIAN_NONE = 0 +HDP_ENDIAN_8IN16 = 1 +HDP_ENDIAN_8IN32 = 2 +HDP_ENDIAN_8IN64 = 3 +Hdp_SurfaceEndian = ctypes.c_uint32 # enum + +# values for enumeration 'MTYPE' +MTYPE__enumvalues = { + 0: 'MTYPE_C_RW_US', + 1: 'MTYPE_RESERVED_1', + 2: 'MTYPE_C_RO_S', + 3: 'MTYPE_UC', + 4: 'MTYPE_C_RW_S', + 5: 'MTYPE_RESERVED_5', + 6: 'MTYPE_C_RO_US', + 7: 'MTYPE_RESERVED_7', +} +MTYPE_C_RW_US = 0 +MTYPE_RESERVED_1 = 1 +MTYPE_C_RO_S = 2 +MTYPE_UC = 3 +MTYPE_C_RW_S = 4 +MTYPE_RESERVED_5 = 5 +MTYPE_C_RO_US = 6 +MTYPE_RESERVED_7 = 7 +MTYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_COUNTER_MODE' +PERFMON_COUNTER_MODE__enumvalues = { + 0: 'PERFMON_COUNTER_MODE_ACCUM', + 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 2: 'PERFMON_COUNTER_MODE_MAX', + 3: 'PERFMON_COUNTER_MODE_DIRTY', + 4: 'PERFMON_COUNTER_MODE_SAMPLE', + 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 15: 'PERFMON_COUNTER_MODE_RESERVED', +} +PERFMON_COUNTER_MODE_ACCUM = 0 +PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 +PERFMON_COUNTER_MODE_MAX = 2 +PERFMON_COUNTER_MODE_DIRTY = 3 +PERFMON_COUNTER_MODE_SAMPLE = 4 +PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 +PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 +PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 +PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 +PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 +PERFMON_COUNTER_MODE_RESERVED = 15 +PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_SPM_MODE' +PERFMON_SPM_MODE__enumvalues = { + 0: 'PERFMON_SPM_MODE_OFF', + 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', + 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', + 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 5: 'PERFMON_SPM_MODE_RESERVED_5', + 6: 'PERFMON_SPM_MODE_RESERVED_6', + 7: 'PERFMON_SPM_MODE_RESERVED_7', + 8: 'PERFMON_SPM_MODE_TEST_MODE_0', + 9: 'PERFMON_SPM_MODE_TEST_MODE_1', + 10: 'PERFMON_SPM_MODE_TEST_MODE_2', +} +PERFMON_SPM_MODE_OFF = 0 +PERFMON_SPM_MODE_16BIT_CLAMP = 1 +PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 +PERFMON_SPM_MODE_32BIT_CLAMP = 3 +PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 +PERFMON_SPM_MODE_RESERVED_5 = 5 +PERFMON_SPM_MODE_RESERVED_6 = 6 +PERFMON_SPM_MODE_RESERVED_7 = 7 +PERFMON_SPM_MODE_TEST_MODE_0 = 8 +PERFMON_SPM_MODE_TEST_MODE_1 = 9 +PERFMON_SPM_MODE_TEST_MODE_2 = 10 +PERFMON_SPM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'RMI_CID' +RMI_CID__enumvalues = { + 0: 'RMI_CID_CC', + 1: 'RMI_CID_FC', + 2: 'RMI_CID_CM', + 3: 'RMI_CID_DC', + 4: 'RMI_CID_Z', + 5: 'RMI_CID_S', + 6: 'RMI_CID_TILE', + 7: 'RMI_CID_ZPCPSD', +} +RMI_CID_CC = 0 +RMI_CID_FC = 1 +RMI_CID_CM = 2 +RMI_CID_DC = 3 +RMI_CID_Z = 4 +RMI_CID_S = 5 +RMI_CID_TILE = 6 +RMI_CID_ZPCPSD = 7 +RMI_CID = ctypes.c_uint32 # enum + +# values for enumeration 'ReadPolicy' +ReadPolicy__enumvalues = { + 0: 'CACHE_LRU_RD', + 1: 'CACHE_STREAM_RD', + 2: 'CACHE_NOA', + 3: 'RESERVED_RDPOLICY', +} +CACHE_LRU_RD = 0 +CACHE_STREAM_RD = 1 +CACHE_NOA = 2 +RESERVED_RDPOLICY = 3 +ReadPolicy = ctypes.c_uint32 # enum + +# values for enumeration 'SDMA_PERFMON_SEL' +SDMA_PERFMON_SEL__enumvalues = { + 0: 'SDMA_PERFMON_SEL_CYCLE', + 1: 'SDMA_PERFMON_SEL_IDLE', + 2: 'SDMA_PERFMON_SEL_REG_IDLE', + 3: 'SDMA_PERFMON_SEL_RB_EMPTY', + 4: 'SDMA_PERFMON_SEL_RB_FULL', + 5: 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', + 6: 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', + 7: 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', + 8: 'SDMA_PERFMON_SEL_RB_RPTR_WB', + 9: 'SDMA_PERFMON_SEL_RB_CMD_IDLE', + 10: 'SDMA_PERFMON_SEL_RB_CMD_FULL', + 11: 'SDMA_PERFMON_SEL_IB_CMD_IDLE', + 12: 'SDMA_PERFMON_SEL_IB_CMD_FULL', + 13: 'SDMA_PERFMON_SEL_EX_IDLE', + 14: 'SDMA_PERFMON_SEL_SRBM_REG_SEND', + 15: 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'SDMA_PERFMON_SEL_WR_BA_RTR', + 17: 'SDMA_PERFMON_SEL_MC_WR_IDLE', + 18: 'SDMA_PERFMON_SEL_MC_WR_COUNT', + 19: 'SDMA_PERFMON_SEL_RD_BA_RTR', + 20: 'SDMA_PERFMON_SEL_MC_RD_IDLE', + 21: 'SDMA_PERFMON_SEL_MC_RD_COUNT', + 22: 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', + 23: 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', + 26: 'SDMA_PERFMON_SEL_SEM_IDLE', + 27: 'SDMA_PERFMON_SEL_SEM_REQ_STALL', + 28: 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', + 29: 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', + 30: 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', + 31: 'SDMA_PERFMON_SEL_SEM_RESP_PASS', + 32: 'SDMA_PERFMON_SEL_INT_IDLE', + 33: 'SDMA_PERFMON_SEL_INT_REQ_STALL', + 34: 'SDMA_PERFMON_SEL_INT_REQ_COUNT', + 35: 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', + 36: 'SDMA_PERFMON_SEL_INT_RESP_RETRY', + 37: 'SDMA_PERFMON_SEL_NUM_PACKET', + 39: 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', + 40: 'SDMA_PERFMON_SEL_CE_WR_IDLE', + 41: 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', + 42: 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', + 43: 'SDMA_PERFMON_SEL_CE_OUT_IDLE', + 44: 'SDMA_PERFMON_SEL_CE_IN_IDLE', + 45: 'SDMA_PERFMON_SEL_CE_DST_IDLE', + 48: 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', + 51: 'SDMA_PERFMON_SEL_CE_INFO_FULL', + 52: 'SDMA_PERFMON_SEL_CE_INFO1_FULL', + 53: 'SDMA_PERFMON_SEL_CE_RD_STALL', + 54: 'SDMA_PERFMON_SEL_CE_WR_STALL', + 55: 'SDMA_PERFMON_SEL_GFX_SELECT', + 56: 'SDMA_PERFMON_SEL_RLC0_SELECT', + 57: 'SDMA_PERFMON_SEL_RLC1_SELECT', + 58: 'SDMA_PERFMON_SEL_PAGE_SELECT', + 59: 'SDMA_PERFMON_SEL_CTX_CHANGE', + 60: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', + 61: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', + 62: 'SDMA_PERFMON_SEL_DOORBELL', + 63: 'SDMA_PERFMON_SEL_F32_L1_WR_VLD', + 64: 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', + 65: 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', + 66: 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', + 67: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', + 68: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', + 69: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', + 70: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', + 71: 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', + 72: 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', + 73: 'SDMA_PERFMON_SEL_UTCL2_FREE', + 74: 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', + 75: 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', + 76: 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', + 77: 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', + 78: 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', + 79: 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', + 80: 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', + 81: 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', + 82: 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', + 83: 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', + 84: 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', + 85: 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', + 86: 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', + 87: 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', + 88: 'SDMA_PERFMON_SEL_L2_META_RET_VLD', + 89: 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', + 90: 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', + 91: 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', + 92: 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', + 93: 'SDMA_PERFMON_SEL_META_REQ_SEND', + 94: 'SDMA_PERFMON_SEL_META_RTN_VLD', + 95: 'SDMA_PERFMON_SEL_TLBI_SEND', + 96: 'SDMA_PERFMON_SEL_TLBI_RTN', + 97: 'SDMA_PERFMON_SEL_GCR_SEND', + 98: 'SDMA_PERFMON_SEL_GCR_RTN', + 99: 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', + 100: 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', +} +SDMA_PERFMON_SEL_CYCLE = 0 +SDMA_PERFMON_SEL_IDLE = 1 +SDMA_PERFMON_SEL_REG_IDLE = 2 +SDMA_PERFMON_SEL_RB_EMPTY = 3 +SDMA_PERFMON_SEL_RB_FULL = 4 +SDMA_PERFMON_SEL_RB_WPTR_WRAP = 5 +SDMA_PERFMON_SEL_RB_RPTR_WRAP = 6 +SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 7 +SDMA_PERFMON_SEL_RB_RPTR_WB = 8 +SDMA_PERFMON_SEL_RB_CMD_IDLE = 9 +SDMA_PERFMON_SEL_RB_CMD_FULL = 10 +SDMA_PERFMON_SEL_IB_CMD_IDLE = 11 +SDMA_PERFMON_SEL_IB_CMD_FULL = 12 +SDMA_PERFMON_SEL_EX_IDLE = 13 +SDMA_PERFMON_SEL_SRBM_REG_SEND = 14 +SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +SDMA_PERFMON_SEL_WR_BA_RTR = 16 +SDMA_PERFMON_SEL_MC_WR_IDLE = 17 +SDMA_PERFMON_SEL_MC_WR_COUNT = 18 +SDMA_PERFMON_SEL_RD_BA_RTR = 19 +SDMA_PERFMON_SEL_MC_RD_IDLE = 20 +SDMA_PERFMON_SEL_MC_RD_COUNT = 21 +SDMA_PERFMON_SEL_MC_RD_RET_STALL = 22 +SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 23 +SDMA_PERFMON_SEL_SEM_IDLE = 26 +SDMA_PERFMON_SEL_SEM_REQ_STALL = 27 +SDMA_PERFMON_SEL_SEM_REQ_COUNT = 28 +SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 29 +SDMA_PERFMON_SEL_SEM_RESP_FAIL = 30 +SDMA_PERFMON_SEL_SEM_RESP_PASS = 31 +SDMA_PERFMON_SEL_INT_IDLE = 32 +SDMA_PERFMON_SEL_INT_REQ_STALL = 33 +SDMA_PERFMON_SEL_INT_REQ_COUNT = 34 +SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 35 +SDMA_PERFMON_SEL_INT_RESP_RETRY = 36 +SDMA_PERFMON_SEL_NUM_PACKET = 37 +SDMA_PERFMON_SEL_CE_WREQ_IDLE = 39 +SDMA_PERFMON_SEL_CE_WR_IDLE = 40 +SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 41 +SDMA_PERFMON_SEL_CE_RREQ_IDLE = 42 +SDMA_PERFMON_SEL_CE_OUT_IDLE = 43 +SDMA_PERFMON_SEL_CE_IN_IDLE = 44 +SDMA_PERFMON_SEL_CE_DST_IDLE = 45 +SDMA_PERFMON_SEL_CE_AFIFO_FULL = 48 +SDMA_PERFMON_SEL_CE_INFO_FULL = 51 +SDMA_PERFMON_SEL_CE_INFO1_FULL = 52 +SDMA_PERFMON_SEL_CE_RD_STALL = 53 +SDMA_PERFMON_SEL_CE_WR_STALL = 54 +SDMA_PERFMON_SEL_GFX_SELECT = 55 +SDMA_PERFMON_SEL_RLC0_SELECT = 56 +SDMA_PERFMON_SEL_RLC1_SELECT = 57 +SDMA_PERFMON_SEL_PAGE_SELECT = 58 +SDMA_PERFMON_SEL_CTX_CHANGE = 59 +SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 60 +SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 61 +SDMA_PERFMON_SEL_DOORBELL = 62 +SDMA_PERFMON_SEL_F32_L1_WR_VLD = 63 +SDMA_PERFMON_SEL_CE_L1_WR_VLD = 64 +SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 65 +SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 66 +SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 67 +SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 68 +SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 69 +SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 70 +SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 71 +SDMA_PERFMON_SEL_UTCL2_RET_ACK = 72 +SDMA_PERFMON_SEL_UTCL2_FREE = 73 +SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 74 +SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 75 +SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 76 +SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 77 +SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 78 +SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 79 +SDMA_PERFMON_SEL_GPUVM_INV_LOW = 80 +SDMA_PERFMON_SEL_L1_WRL2_IDLE = 81 +SDMA_PERFMON_SEL_L1_RDL2_IDLE = 82 +SDMA_PERFMON_SEL_L1_WRMC_IDLE = 83 +SDMA_PERFMON_SEL_L1_RDMC_IDLE = 84 +SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 85 +SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 86 +SDMA_PERFMON_SEL_META_L2_REQ_SEND = 87 +SDMA_PERFMON_SEL_L2_META_RET_VLD = 88 +SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 89 +SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 90 +SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 91 +SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 92 +SDMA_PERFMON_SEL_META_REQ_SEND = 93 +SDMA_PERFMON_SEL_META_RTN_VLD = 94 +SDMA_PERFMON_SEL_TLBI_SEND = 95 +SDMA_PERFMON_SEL_TLBI_RTN = 96 +SDMA_PERFMON_SEL_GCR_SEND = 97 +SDMA_PERFMON_SEL_GCR_RTN = 98 +SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 99 +SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 100 +SDMA_PERFMON_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SDMA_PERF_SEL' +SDMA_PERF_SEL__enumvalues = { + 0: 'SDMA_PERF_SEL_CYCLE', + 1: 'SDMA_PERF_SEL_IDLE', + 2: 'SDMA_PERF_SEL_REG_IDLE', + 3: 'SDMA_PERF_SEL_RB_EMPTY', + 4: 'SDMA_PERF_SEL_RB_FULL', + 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', + 8: 'SDMA_PERF_SEL_RB_RPTR_WB', + 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', + 10: 'SDMA_PERF_SEL_RB_CMD_FULL', + 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', + 12: 'SDMA_PERF_SEL_IB_CMD_FULL', + 13: 'SDMA_PERF_SEL_EX_IDLE', + 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', + 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'SDMA_PERF_SEL_MC_WR_IDLE', + 17: 'SDMA_PERF_SEL_MC_WR_COUNT', + 18: 'SDMA_PERF_SEL_MC_RD_IDLE', + 19: 'SDMA_PERF_SEL_MC_RD_COUNT', + 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', + 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 24: 'SDMA_PERF_SEL_SEM_IDLE', + 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', + 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', + 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', + 30: 'SDMA_PERF_SEL_INT_IDLE', + 31: 'SDMA_PERF_SEL_INT_REQ_STALL', + 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', + 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', + 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', + 35: 'SDMA_PERF_SEL_NUM_PACKET', + 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 38: 'SDMA_PERF_SEL_CE_WR_IDLE', + 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', + 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', + 42: 'SDMA_PERF_SEL_CE_IN_IDLE', + 43: 'SDMA_PERF_SEL_CE_DST_IDLE', + 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', + 49: 'SDMA_PERF_SEL_CE_INFO_FULL', + 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', + 51: 'SDMA_PERF_SEL_CE_RD_STALL', + 52: 'SDMA_PERF_SEL_CE_WR_STALL', + 53: 'SDMA_PERF_SEL_GFX_SELECT', + 54: 'SDMA_PERF_SEL_RLC0_SELECT', + 55: 'SDMA_PERF_SEL_RLC1_SELECT', + 56: 'SDMA_PERF_SEL_PAGE_SELECT', + 57: 'SDMA_PERF_SEL_CTX_CHANGE', + 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', + 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 60: 'SDMA_PERF_SEL_DOORBELL', + 61: 'SDMA_PERF_SEL_RD_BA_RTR', + 62: 'SDMA_PERF_SEL_WR_BA_RTR', + 63: 'SDMA_PERF_SEL_F32_L1_WR_VLD', + 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', + 65: 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', + 66: 'SDMA_PERF_SEL_SDMA_CPF_INVACK', + 67: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', + 68: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', + 69: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', + 70: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', + 71: 'SDMA_PERF_SEL_UTCL2_RET_XNACK', + 72: 'SDMA_PERF_SEL_UTCL2_RET_ACK', + 73: 'SDMA_PERF_SEL_UTCL2_FREE', + 74: 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', + 75: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 76: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', + 77: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 78: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', + 79: 'SDMA_PERF_SEL_GPUVM_INV_HIGH', + 80: 'SDMA_PERF_SEL_GPUVM_INV_LOW', + 81: 'SDMA_PERF_SEL_L1_WRL2_IDLE', + 82: 'SDMA_PERF_SEL_L1_RDL2_IDLE', + 83: 'SDMA_PERF_SEL_L1_WRMC_IDLE', + 84: 'SDMA_PERF_SEL_L1_RDMC_IDLE', + 85: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', + 86: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', + 87: 'SDMA_PERF_SEL_META_L2_REQ_SEND', + 88: 'SDMA_PERF_SEL_L2_META_RET_VLD', + 89: 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', + 90: 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', + 91: 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', + 92: 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', + 93: 'SDMA_PERF_SEL_META_REQ_SEND', + 94: 'SDMA_PERF_SEL_META_RTN_VLD', + 95: 'SDMA_PERF_SEL_TLBI_SEND', + 96: 'SDMA_PERF_SEL_TLBI_RTN', + 97: 'SDMA_PERF_SEL_GCR_SEND', + 98: 'SDMA_PERF_SEL_GCR_RTN', + 99: 'SDMA_PERF_SEL_CGCG_FENCE', + 100: 'SDMA_PERF_SEL_CE_CH_WR_REQ', + 101: 'SDMA_PERF_SEL_CE_CH_WR_RET', + 102: 'SDMA_PERF_SEL_F32_CH_WR_REQ', + 103: 'SDMA_PERF_SEL_F32_CH_WR_RET', + 104: 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ', + 105: 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET', + 106: 'SDMA_PERF_SEL_RB_CH_RD_REQ', + 107: 'SDMA_PERF_SEL_RB_CH_RD_RET', + 108: 'SDMA_PERF_SEL_IB_CH_RD_REQ', + 109: 'SDMA_PERF_SEL_IB_CH_RD_RET', + 110: 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', + 111: 'SDMA_PERF_SEL_WPTR_CH_RD_RET', + 112: 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', + 113: 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', + 114: 'SDMA_PERF_SEL_CMD_OP_MATCH', + 115: 'SDMA_PERF_SEL_CMD_OP_START', + 116: 'SDMA_PERF_SEL_CMD_OP_END', + 117: 'SDMA_PERF_SEL_CE_BUSY', + 118: 'SDMA_PERF_SEL_CE_BUSY_START', + 119: 'SDMA_PERF_SEL_CE_BUSY_END', + 120: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 121: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 122: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 123: 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', + 124: 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', + 125: 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', + 126: 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', +} +SDMA_PERF_SEL_CYCLE = 0 +SDMA_PERF_SEL_IDLE = 1 +SDMA_PERF_SEL_REG_IDLE = 2 +SDMA_PERF_SEL_RB_EMPTY = 3 +SDMA_PERF_SEL_RB_FULL = 4 +SDMA_PERF_SEL_RB_WPTR_WRAP = 5 +SDMA_PERF_SEL_RB_RPTR_WRAP = 6 +SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 +SDMA_PERF_SEL_RB_RPTR_WB = 8 +SDMA_PERF_SEL_RB_CMD_IDLE = 9 +SDMA_PERF_SEL_RB_CMD_FULL = 10 +SDMA_PERF_SEL_IB_CMD_IDLE = 11 +SDMA_PERF_SEL_IB_CMD_FULL = 12 +SDMA_PERF_SEL_EX_IDLE = 13 +SDMA_PERF_SEL_SRBM_REG_SEND = 14 +SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +SDMA_PERF_SEL_MC_WR_IDLE = 16 +SDMA_PERF_SEL_MC_WR_COUNT = 17 +SDMA_PERF_SEL_MC_RD_IDLE = 18 +SDMA_PERF_SEL_MC_RD_COUNT = 19 +SDMA_PERF_SEL_MC_RD_RET_STALL = 20 +SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 +SDMA_PERF_SEL_SEM_IDLE = 24 +SDMA_PERF_SEL_SEM_REQ_STALL = 25 +SDMA_PERF_SEL_SEM_REQ_COUNT = 26 +SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 +SDMA_PERF_SEL_SEM_RESP_FAIL = 28 +SDMA_PERF_SEL_SEM_RESP_PASS = 29 +SDMA_PERF_SEL_INT_IDLE = 30 +SDMA_PERF_SEL_INT_REQ_STALL = 31 +SDMA_PERF_SEL_INT_REQ_COUNT = 32 +SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 +SDMA_PERF_SEL_INT_RESP_RETRY = 34 +SDMA_PERF_SEL_NUM_PACKET = 35 +SDMA_PERF_SEL_CE_WREQ_IDLE = 37 +SDMA_PERF_SEL_CE_WR_IDLE = 38 +SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 +SDMA_PERF_SEL_CE_RREQ_IDLE = 40 +SDMA_PERF_SEL_CE_OUT_IDLE = 41 +SDMA_PERF_SEL_CE_IN_IDLE = 42 +SDMA_PERF_SEL_CE_DST_IDLE = 43 +SDMA_PERF_SEL_CE_AFIFO_FULL = 46 +SDMA_PERF_SEL_CE_INFO_FULL = 49 +SDMA_PERF_SEL_CE_INFO1_FULL = 50 +SDMA_PERF_SEL_CE_RD_STALL = 51 +SDMA_PERF_SEL_CE_WR_STALL = 52 +SDMA_PERF_SEL_GFX_SELECT = 53 +SDMA_PERF_SEL_RLC0_SELECT = 54 +SDMA_PERF_SEL_RLC1_SELECT = 55 +SDMA_PERF_SEL_PAGE_SELECT = 56 +SDMA_PERF_SEL_CTX_CHANGE = 57 +SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 +SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 +SDMA_PERF_SEL_DOORBELL = 60 +SDMA_PERF_SEL_RD_BA_RTR = 61 +SDMA_PERF_SEL_WR_BA_RTR = 62 +SDMA_PERF_SEL_F32_L1_WR_VLD = 63 +SDMA_PERF_SEL_CE_L1_WR_VLD = 64 +SDMA_PERF_SEL_CPF_SDMA_INVREQ = 65 +SDMA_PERF_SEL_SDMA_CPF_INVACK = 66 +SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 67 +SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 68 +SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 69 +SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 70 +SDMA_PERF_SEL_UTCL2_RET_XNACK = 71 +SDMA_PERF_SEL_UTCL2_RET_ACK = 72 +SDMA_PERF_SEL_UTCL2_FREE = 73 +SDMA_PERF_SEL_SDMA_UTCL2_SEND = 74 +SDMA_PERF_SEL_DMA_L1_WR_SEND = 75 +SDMA_PERF_SEL_DMA_L1_RD_SEND = 76 +SDMA_PERF_SEL_DMA_MC_WR_SEND = 77 +SDMA_PERF_SEL_DMA_MC_RD_SEND = 78 +SDMA_PERF_SEL_GPUVM_INV_HIGH = 79 +SDMA_PERF_SEL_GPUVM_INV_LOW = 80 +SDMA_PERF_SEL_L1_WRL2_IDLE = 81 +SDMA_PERF_SEL_L1_RDL2_IDLE = 82 +SDMA_PERF_SEL_L1_WRMC_IDLE = 83 +SDMA_PERF_SEL_L1_RDMC_IDLE = 84 +SDMA_PERF_SEL_L1_WR_INV_IDLE = 85 +SDMA_PERF_SEL_L1_RD_INV_IDLE = 86 +SDMA_PERF_SEL_META_L2_REQ_SEND = 87 +SDMA_PERF_SEL_L2_META_RET_VLD = 88 +SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 89 +SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 90 +SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 91 +SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 92 +SDMA_PERF_SEL_META_REQ_SEND = 93 +SDMA_PERF_SEL_META_RTN_VLD = 94 +SDMA_PERF_SEL_TLBI_SEND = 95 +SDMA_PERF_SEL_TLBI_RTN = 96 +SDMA_PERF_SEL_GCR_SEND = 97 +SDMA_PERF_SEL_GCR_RTN = 98 +SDMA_PERF_SEL_CGCG_FENCE = 99 +SDMA_PERF_SEL_CE_CH_WR_REQ = 100 +SDMA_PERF_SEL_CE_CH_WR_RET = 101 +SDMA_PERF_SEL_F32_CH_WR_REQ = 102 +SDMA_PERF_SEL_F32_CH_WR_RET = 103 +SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ = 104 +SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET = 105 +SDMA_PERF_SEL_RB_CH_RD_REQ = 106 +SDMA_PERF_SEL_RB_CH_RD_RET = 107 +SDMA_PERF_SEL_IB_CH_RD_REQ = 108 +SDMA_PERF_SEL_IB_CH_RD_RET = 109 +SDMA_PERF_SEL_WPTR_CH_RD_REQ = 110 +SDMA_PERF_SEL_WPTR_CH_RD_RET = 111 +SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 112 +SDMA_PERF_SEL_UTCL1_UTCL2_RET = 113 +SDMA_PERF_SEL_CMD_OP_MATCH = 114 +SDMA_PERF_SEL_CMD_OP_START = 115 +SDMA_PERF_SEL_CMD_OP_END = 116 +SDMA_PERF_SEL_CE_BUSY = 117 +SDMA_PERF_SEL_CE_BUSY_START = 118 +SDMA_PERF_SEL_CE_BUSY_END = 119 +SDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 120 +SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 121 +SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 122 +SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 123 +SDMA_PERF_SEL_CH_CE_WRRET_VALID = 124 +SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 125 +SDMA_PERF_SEL_CH_CE_RDRET_VALID = 126 +SDMA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_CACHE_POLICIES' +TCC_CACHE_POLICIES__enumvalues = { + 0: 'TCC_CACHE_POLICY_LRU', + 1: 'TCC_CACHE_POLICY_STREAM', +} +TCC_CACHE_POLICY_LRU = 0 +TCC_CACHE_POLICY_STREAM = 1 +TCC_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_MTYPE' +TCC_MTYPE__enumvalues = { + 0: 'MTYPE_NC', + 1: 'MTYPE_WC', + 2: 'MTYPE_CC', +} +MTYPE_NC = 0 +MTYPE_WC = 1 +MTYPE_CC = 2 +TCC_MTYPE = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL0FaultType' +UTCL0FaultType__enumvalues = { + 0: 'UTCL0_XNACK_SUCCESS', + 1: 'UTCL0_XNACK_RETRY', + 2: 'UTCL0_XNACK_PRT', + 3: 'UTCL0_XNACK_NO_RETRY', +} +UTCL0_XNACK_SUCCESS = 0 +UTCL0_XNACK_RETRY = 1 +UTCL0_XNACK_PRT = 2 +UTCL0_XNACK_NO_RETRY = 3 +UTCL0FaultType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL0RequestType' +UTCL0RequestType__enumvalues = { + 0: 'UTCL0_TYPE_NORMAL', + 1: 'UTCL0_TYPE_SHOOTDOWN', + 2: 'UTCL0_TYPE_BYPASS', +} +UTCL0_TYPE_NORMAL = 0 +UTCL0_TYPE_SHOOTDOWN = 1 +UTCL0_TYPE_BYPASS = 2 +UTCL0RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1FaultType' +UTCL1FaultType__enumvalues = { + 0: 'UTCL1_XNACK_SUCCESS', + 1: 'UTCL1_XNACK_RETRY', + 2: 'UTCL1_XNACK_PRT', + 3: 'UTCL1_XNACK_NO_RETRY', +} +UTCL1_XNACK_SUCCESS = 0 +UTCL1_XNACK_RETRY = 1 +UTCL1_XNACK_PRT = 2 +UTCL1_XNACK_NO_RETRY = 3 +UTCL1FaultType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1RequestType' +UTCL1RequestType__enumvalues = { + 0: 'UTCL1_TYPE_NORMAL', + 1: 'UTCL1_TYPE_SHOOTDOWN', + 2: 'UTCL1_TYPE_BYPASS', +} +UTCL1_TYPE_NORMAL = 0 +UTCL1_TYPE_SHOOTDOWN = 1 +UTCL1_TYPE_BYPASS = 2 +UTCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'VMEMCMD_RETURN_ORDER' +VMEMCMD_RETURN_ORDER__enumvalues = { + 0: 'VMEMCMD_RETURN_OUT_OF_ORDER', + 1: 'VMEMCMD_RETURN_IN_ORDER', + 2: 'VMEMCMD_RETURN_IN_ORDER_READ', +} +VMEMCMD_RETURN_OUT_OF_ORDER = 0 +VMEMCMD_RETURN_IN_ORDER = 1 +VMEMCMD_RETURN_IN_ORDER_READ = 2 +VMEMCMD_RETURN_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'WritePolicy' +WritePolicy__enumvalues = { + 0: 'CACHE_LRU_WR', + 1: 'CACHE_STREAM', + 2: 'CACHE_NOA_WR', + 3: 'CACHE_BYPASS', +} +CACHE_LRU_WR = 0 +CACHE_STREAM = 1 +CACHE_NOA_WR = 2 +CACHE_BYPASS = 3 +WritePolicy = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_BYPASS' +CNVC_BYPASS__enumvalues = { + 0: 'CNVC_BYPASS_DISABLE', + 1: 'CNVC_BYPASS_EN', +} +CNVC_BYPASS_DISABLE = 0 +CNVC_BYPASS_EN = 1 +CNVC_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_COEF_FORMAT_ENUM' +CNVC_COEF_FORMAT_ENUM__enumvalues = { + 0: 'CNVC_FIX_S2_13', + 1: 'CNVC_FIX_S3_12', +} +CNVC_FIX_S2_13 = 0 +CNVC_FIX_S3_12 = 1 +CNVC_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_ENABLE' +CNVC_ENABLE__enumvalues = { + 0: 'CNVC_DIS', + 1: 'CNVC_EN', +} +CNVC_DIS = 0 +CNVC_EN = 1 +CNVC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_PENDING' +CNVC_PENDING__enumvalues = { + 0: 'CNVC_NOT_PENDING', + 1: 'CNVC_YES_PENDING', +} +CNVC_NOT_PENDING = 0 +CNVC_YES_PENDING = 1 +CNVC_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'COLOR_KEYER_MODE' +COLOR_KEYER_MODE__enumvalues = { + 0: 'FORCE_00', + 1: 'FORCE_FF', + 2: 'RANGE_00', + 3: 'RANGE_FF', +} +FORCE_00 = 0 +FORCE_FF = 1 +RANGE_00 = 2 +RANGE_FF = 3 +COLOR_KEYER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DENORM_TRUNCATE' +DENORM_TRUNCATE__enumvalues = { + 0: 'CNVC_ROUND', + 1: 'CNVC_TRUNCATE', +} +CNVC_ROUND = 0 +CNVC_TRUNCATE = 1 +DENORM_TRUNCATE = ctypes.c_uint32 # enum + +# values for enumeration 'FORMAT_CROSSBAR' +FORMAT_CROSSBAR__enumvalues = { + 0: 'FORMAT_CROSSBAR_R', + 1: 'FORMAT_CROSSBAR_G', + 2: 'FORMAT_CROSSBAR_B', +} +FORMAT_CROSSBAR_R = 0 +FORMAT_CROSSBAR_G = 1 +FORMAT_CROSSBAR_B = 2 +FORMAT_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'PIX_EXPAND_MODE' +PIX_EXPAND_MODE__enumvalues = { + 0: 'PIX_DYNAMIC_EXPANSION', + 1: 'PIX_ZERO_EXPANSION', +} +PIX_DYNAMIC_EXPANSION = 0 +PIX_ZERO_EXPANSION = 1 +PIX_EXPAND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PRE_CSC_MODE_ENUM' +PRE_CSC_MODE_ENUM__enumvalues = { + 0: 'PRE_CSC_BYPASS', + 1: 'PRE_CSC_SET_A', + 2: 'PRE_CSC_SET_B', +} +PRE_CSC_BYPASS = 0 +PRE_CSC_SET_A = 1 +PRE_CSC_SET_B = 2 +PRE_CSC_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'PRE_DEGAM_MODE' +PRE_DEGAM_MODE__enumvalues = { + 0: 'PRE_DEGAM_BYPASS', + 1: 'PRE_DEGAM_ENABLE', +} +PRE_DEGAM_BYPASS = 0 +PRE_DEGAM_ENABLE = 1 +PRE_DEGAM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PRE_DEGAM_SELECT' +PRE_DEGAM_SELECT__enumvalues = { + 0: 'PRE_DEGAM_SRGB', + 1: 'PRE_DEGAM_GAMMA_22', + 2: 'PRE_DEGAM_GAMMA_24', + 3: 'PRE_DEGAM_GAMMA_26', + 4: 'PRE_DEGAM_BT2020', + 5: 'PRE_DEGAM_BT2100PQ', + 6: 'PRE_DEGAM_BT2100HLG', +} +PRE_DEGAM_SRGB = 0 +PRE_DEGAM_GAMMA_22 = 1 +PRE_DEGAM_GAMMA_24 = 2 +PRE_DEGAM_GAMMA_26 = 3 +PRE_DEGAM_BT2020 = 4 +PRE_DEGAM_BT2100PQ = 5 +PRE_DEGAM_BT2100HLG = 6 +PRE_DEGAM_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_PIXEL_FORMAT' +SURFACE_PIXEL_FORMAT__enumvalues = { + 1: 'ARGB1555', + 2: 'RGBA5551', + 3: 'RGB565', + 4: 'BGR565', + 5: 'ARGB4444', + 6: 'RGBA4444', + 8: 'ARGB8888', + 9: 'RGBA8888', + 10: 'ARGB2101010', + 11: 'RGBA1010102', + 12: 'AYCrCb8888', + 13: 'YCrCbA8888', + 14: 'ACrYCb8888', + 15: 'CrYCbA8888', + 16: 'ARGB16161616_10MSB', + 17: 'RGBA16161616_10MSB', + 18: 'ARGB16161616_10LSB', + 19: 'RGBA16161616_10LSB', + 20: 'ARGB16161616_12MSB', + 21: 'RGBA16161616_12MSB', + 22: 'ARGB16161616_12LSB', + 23: 'RGBA16161616_12LSB', + 24: 'ARGB16161616_FLOAT', + 25: 'RGBA16161616_FLOAT', + 26: 'ARGB16161616_UNORM', + 27: 'RGBA16161616_UNORM', + 28: 'ARGB16161616_SNORM', + 29: 'RGBA16161616_SNORM', + 32: 'AYCrCb16161616_10MSB', + 33: 'AYCrCb16161616_10LSB', + 34: 'YCrCbA16161616_10MSB', + 35: 'YCrCbA16161616_10LSB', + 36: 'ACrYCb16161616_10MSB', + 37: 'ACrYCb16161616_10LSB', + 38: 'CrYCbA16161616_10MSB', + 39: 'CrYCbA16161616_10LSB', + 40: 'AYCrCb16161616_12MSB', + 41: 'AYCrCb16161616_12LSB', + 42: 'YCrCbA16161616_12MSB', + 43: 'YCrCbA16161616_12LSB', + 44: 'ACrYCb16161616_12MSB', + 45: 'ACrYCb16161616_12LSB', + 46: 'CrYCbA16161616_12MSB', + 47: 'CrYCbA16161616_12LSB', + 64: 'Y8_CrCb88_420_PLANAR', + 65: 'Y8_CbCr88_420_PLANAR', + 66: 'Y10_CrCb1010_420_PLANAR', + 67: 'Y10_CbCr1010_420_PLANAR', + 68: 'Y12_CrCb1212_420_PLANAR', + 69: 'Y12_CbCr1212_420_PLANAR', + 72: 'YCrYCb8888_422_PACKED', + 73: 'YCbYCr8888_422_PACKED', + 74: 'CrYCbY8888_422_PACKED', + 75: 'CbYCrY8888_422_PACKED', + 76: 'YCrYCb10101010_422_PACKED', + 77: 'YCbYCr10101010_422_PACKED', + 78: 'CrYCbY10101010_422_PACKED', + 79: 'CbYCrY10101010_422_PACKED', + 80: 'YCrYCb12121212_422_PACKED', + 81: 'YCbYCr12121212_422_PACKED', + 82: 'CrYCbY12121212_422_PACKED', + 83: 'CbYCrY12121212_422_PACKED', + 112: 'RGB111110_FIX', + 113: 'BGR101111_FIX', + 114: 'ACrYCb2101010', + 115: 'CrYCbA1010102', + 116: 'RGBE', + 118: 'RGB111110_FLOAT', + 119: 'BGR101111_FLOAT', + 120: 'MONO_8', + 121: 'MONO_10MSB', + 122: 'MONO_10LSB', + 123: 'MONO_12MSB', + 124: 'MONO_12LSB', + 125: 'MONO_16', +} +ARGB1555 = 1 +RGBA5551 = 2 +RGB565 = 3 +BGR565 = 4 +ARGB4444 = 5 +RGBA4444 = 6 +ARGB8888 = 8 +RGBA8888 = 9 +ARGB2101010 = 10 +RGBA1010102 = 11 +AYCrCb8888 = 12 +YCrCbA8888 = 13 +ACrYCb8888 = 14 +CrYCbA8888 = 15 +ARGB16161616_10MSB = 16 +RGBA16161616_10MSB = 17 +ARGB16161616_10LSB = 18 +RGBA16161616_10LSB = 19 +ARGB16161616_12MSB = 20 +RGBA16161616_12MSB = 21 +ARGB16161616_12LSB = 22 +RGBA16161616_12LSB = 23 +ARGB16161616_FLOAT = 24 +RGBA16161616_FLOAT = 25 +ARGB16161616_UNORM = 26 +RGBA16161616_UNORM = 27 +ARGB16161616_SNORM = 28 +RGBA16161616_SNORM = 29 +AYCrCb16161616_10MSB = 32 +AYCrCb16161616_10LSB = 33 +YCrCbA16161616_10MSB = 34 +YCrCbA16161616_10LSB = 35 +ACrYCb16161616_10MSB = 36 +ACrYCb16161616_10LSB = 37 +CrYCbA16161616_10MSB = 38 +CrYCbA16161616_10LSB = 39 +AYCrCb16161616_12MSB = 40 +AYCrCb16161616_12LSB = 41 +YCrCbA16161616_12MSB = 42 +YCrCbA16161616_12LSB = 43 +ACrYCb16161616_12MSB = 44 +ACrYCb16161616_12LSB = 45 +CrYCbA16161616_12MSB = 46 +CrYCbA16161616_12LSB = 47 +Y8_CrCb88_420_PLANAR = 64 +Y8_CbCr88_420_PLANAR = 65 +Y10_CrCb1010_420_PLANAR = 66 +Y10_CbCr1010_420_PLANAR = 67 +Y12_CrCb1212_420_PLANAR = 68 +Y12_CbCr1212_420_PLANAR = 69 +YCrYCb8888_422_PACKED = 72 +YCbYCr8888_422_PACKED = 73 +CrYCbY8888_422_PACKED = 74 +CbYCrY8888_422_PACKED = 75 +YCrYCb10101010_422_PACKED = 76 +YCbYCr10101010_422_PACKED = 77 +CrYCbY10101010_422_PACKED = 78 +CbYCrY10101010_422_PACKED = 79 +YCrYCb12121212_422_PACKED = 80 +YCbYCr12121212_422_PACKED = 81 +CrYCbY12121212_422_PACKED = 82 +CbYCrY12121212_422_PACKED = 83 +RGB111110_FIX = 112 +BGR101111_FIX = 113 +ACrYCb2101010 = 114 +CrYCbA1010102 = 115 +RGBE = 116 +RGB111110_FLOAT = 118 +BGR101111_FLOAT = 119 +MONO_8 = 120 +MONO_10MSB = 121 +MONO_10LSB = 122 +MONO_12MSB = 123 +MONO_12LSB = 124 +MONO_16 = 125 +SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'XNORM' +XNORM__enumvalues = { + 0: 'XNORM_A', + 1: 'XNORM_B', +} +XNORM_A = 0 +XNORM_B = 1 +XNORM = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_ENABLE' +CUR_ENABLE__enumvalues = { + 0: 'CUR_DIS', + 1: 'CUR_EN', +} +CUR_DIS = 0 +CUR_EN = 1 +CUR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_EXPAND_MODE' +CUR_EXPAND_MODE__enumvalues = { + 0: 'CUR_DYNAMIC_EXPANSION', + 1: 'CUR_ZERO_EXPANSION', +} +CUR_DYNAMIC_EXPANSION = 0 +CUR_ZERO_EXPANSION = 1 +CUR_EXPAND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_INV_CLAMP' +CUR_INV_CLAMP__enumvalues = { + 0: 'CUR_CLAMP_DIS', + 1: 'CUR_CLAMP_EN', +} +CUR_CLAMP_DIS = 0 +CUR_CLAMP_EN = 1 +CUR_INV_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_MODE' +CUR_MODE__enumvalues = { + 0: 'MONO_2BIT', + 1: 'COLOR_24BIT_1BIT_AND', + 2: 'COLOR_24BIT_8BIT_ALPHA_PREMULT', + 3: 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 4: 'COLOR_64BIT_FP_PREMULT', + 5: 'COLOR_64BIT_FP_UNPREMULT', +} +MONO_2BIT = 0 +COLOR_24BIT_1BIT_AND = 1 +COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 +COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 +COLOR_64BIT_FP_PREMULT = 4 +COLOR_64BIT_FP_UNPREMULT = 5 +CUR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_PENDING' +CUR_PENDING__enumvalues = { + 0: 'CUR_NOT_PENDING', + 1: 'CUR_YES_PENDING', +} +CUR_NOT_PENDING = 0 +CUR_YES_PENDING = 1 +CUR_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_ROM_EN' +CUR_ROM_EN__enumvalues = { + 0: 'CUR_FP_NO_ROM', + 1: 'CUR_FP_USE_ROM', +} +CUR_FP_NO_ROM = 0 +CUR_FP_USE_ROM = 1 +CUR_ROM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'COEF_RAM_SELECT_RD' +COEF_RAM_SELECT_RD__enumvalues = { + 0: 'COEF_RAM_SELECT_BACK', + 1: 'COEF_RAM_SELECT_CURRENT', +} +COEF_RAM_SELECT_BACK = 0 +COEF_RAM_SELECT_CURRENT = 1 +COEF_RAM_SELECT_RD = ctypes.c_uint32 # enum + +# values for enumeration 'DSCL_MODE_SEL' +DSCL_MODE_SEL__enumvalues = { + 0: 'DSCL_MODE_SCALING_444_BYPASS', + 1: 'DSCL_MODE_SCALING_444_RGB_ENABLE', + 2: 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', + 3: 'DSCL_MODE_SCALING_YCBCR_ENABLE', + 4: 'DSCL_MODE_LUMA_SCALING_BYPASS', + 5: 'DSCL_MODE_CHROMA_SCALING_BYPASS', + 6: 'DSCL_MODE_DSCL_BYPASS', +} +DSCL_MODE_SCALING_444_BYPASS = 0 +DSCL_MODE_SCALING_444_RGB_ENABLE = 1 +DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2 +DSCL_MODE_SCALING_YCBCR_ENABLE = 3 +DSCL_MODE_LUMA_SCALING_BYPASS = 4 +DSCL_MODE_CHROMA_SCALING_BYPASS = 5 +DSCL_MODE_DSCL_BYPASS = 6 +DSCL_MODE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'LB_ALPHA_EN' +LB_ALPHA_EN__enumvalues = { + 0: 'LB_ALPHA_DISABLE', + 1: 'LB_ALPHA_ENABLE', +} +LB_ALPHA_DISABLE = 0 +LB_ALPHA_ENABLE = 1 +LB_ALPHA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_INTERLEAVE_EN' +LB_INTERLEAVE_EN__enumvalues = { + 0: 'LB_INTERLEAVE_DISABLE', + 1: 'LB_INTERLEAVE_ENABLE', +} +LB_INTERLEAVE_DISABLE = 0 +LB_INTERLEAVE_ENABLE = 1 +LB_INTERLEAVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MEMORY_CONFIG' +LB_MEMORY_CONFIG__enumvalues = { + 0: 'LB_MEMORY_CONFIG_0', + 1: 'LB_MEMORY_CONFIG_1', + 2: 'LB_MEMORY_CONFIG_2', + 3: 'LB_MEMORY_CONFIG_3', +} +LB_MEMORY_CONFIG_0 = 0 +LB_MEMORY_CONFIG_1 = 1 +LB_MEMORY_CONFIG_2 = 2 +LB_MEMORY_CONFIG_3 = 3 +LB_MEMORY_CONFIG = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_BYPASS_SEL' +OBUF_BYPASS_SEL__enumvalues = { + 0: 'OBUF_BYPASS_DIS', + 1: 'OBUF_BYPASS_EN', +} +OBUF_BYPASS_DIS = 0 +OBUF_BYPASS_EN = 1 +OBUF_BYPASS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_IS_HALF_RECOUT_WIDTH_SEL' +OBUF_IS_HALF_RECOUT_WIDTH_SEL__enumvalues = { + 0: 'OBUF_FULL_RECOUT', + 1: 'OBUF_HALF_RECOUT', +} +OBUF_FULL_RECOUT = 0 +OBUF_HALF_RECOUT = 1 +OBUF_IS_HALF_RECOUT_WIDTH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_USE_FULL_BUFFER_SEL' +OBUF_USE_FULL_BUFFER_SEL__enumvalues = { + 0: 'OBUF_RECOUT', + 1: 'OBUF_FULL', +} +OBUF_RECOUT = 0 +OBUF_FULL = 1 +OBUF_USE_FULL_BUFFER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_2TAP_HARDCODE' +SCL_2TAP_HARDCODE__enumvalues = { + 0: 'SCL_COEF_2TAP_HARDCODE_OFF', + 1: 'SCL_COEF_2TAP_HARDCODE_ON', +} +SCL_COEF_2TAP_HARDCODE_OFF = 0 +SCL_COEF_2TAP_HARDCODE_ON = 1 +SCL_2TAP_HARDCODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_ALPHA_COEF' +SCL_ALPHA_COEF__enumvalues = { + 0: 'SCL_ALPHA_COEF_FIRST', + 1: 'SCL_ALPHA_COEF_SECOND', +} +SCL_ALPHA_COEF_FIRST = 0 +SCL_ALPHA_COEF_SECOND = 1 +SCL_ALPHA_COEF = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_AUTOCAL_MODE' +SCL_AUTOCAL_MODE__enumvalues = { + 0: 'AUTOCAL_MODE_OFF', + 1: 'AUTOCAL_MODE_AUTOSCALE', + 2: 'AUTOCAL_MODE_AUTOCENTER', + 3: 'AUTOCAL_MODE_AUTOREPLICATE', +} +AUTOCAL_MODE_OFF = 0 +AUTOCAL_MODE_AUTOSCALE = 1 +AUTOCAL_MODE_AUTOCENTER = 2 +AUTOCAL_MODE_AUTOREPLICATE = 3 +SCL_AUTOCAL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_BOUNDARY' +SCL_BOUNDARY__enumvalues = { + 0: 'SCL_BOUNDARY_EDGE', + 1: 'SCL_BOUNDARY_BLACK', +} +SCL_BOUNDARY_EDGE = 0 +SCL_BOUNDARY_BLACK = 1 +SCL_BOUNDARY = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_CHROMA_COEF' +SCL_CHROMA_COEF__enumvalues = { + 0: 'SCL_CHROMA_COEF_FIRST', + 1: 'SCL_CHROMA_COEF_SECOND', +} +SCL_CHROMA_COEF_FIRST = 0 +SCL_CHROMA_COEF_SECOND = 1 +SCL_CHROMA_COEF = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_COEF_FILTER_TYPE_SEL' +SCL_COEF_FILTER_TYPE_SEL__enumvalues = { + 0: 'SCL_COEF_LUMA_VERT_FILTER', + 1: 'SCL_COEF_LUMA_HORZ_FILTER', + 2: 'SCL_COEF_CHROMA_VERT_FILTER', + 3: 'SCL_COEF_CHROMA_HORZ_FILTER', +} +SCL_COEF_LUMA_VERT_FILTER = 0 +SCL_COEF_LUMA_HORZ_FILTER = 1 +SCL_COEF_CHROMA_VERT_FILTER = 2 +SCL_COEF_CHROMA_HORZ_FILTER = 3 +SCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_COEF_RAM_SEL' +SCL_COEF_RAM_SEL__enumvalues = { + 0: 'SCL_COEF_RAM_SEL_0', + 1: 'SCL_COEF_RAM_SEL_1', +} +SCL_COEF_RAM_SEL_0 = 0 +SCL_COEF_RAM_SEL_1 = 1 +SCL_COEF_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_SHARP_EN' +SCL_SHARP_EN__enumvalues = { + 0: 'SCL_SHARP_DISABLE', + 1: 'SCL_SHARP_ENABLE', +} +SCL_SHARP_DISABLE = 0 +SCL_SHARP_ENABLE = 1 +SCL_SHARP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_30BIT_ENUM' +CMC_3DLUT_30BIT_ENUM__enumvalues = { + 0: 'CMC_3DLUT_36BIT', + 1: 'CMC_3DLUT_30BIT', +} +CMC_3DLUT_36BIT = 0 +CMC_3DLUT_30BIT = 1 +CMC_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_RAM_SEL' +CMC_3DLUT_RAM_SEL__enumvalues = { + 0: 'CMC_RAM0_ACCESS', + 1: 'CMC_RAM1_ACCESS', + 2: 'CMC_RAM2_ACCESS', + 3: 'CMC_RAM3_ACCESS', +} +CMC_RAM0_ACCESS = 0 +CMC_RAM1_ACCESS = 1 +CMC_RAM2_ACCESS = 2 +CMC_RAM3_ACCESS = 3 +CMC_3DLUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_SIZE_ENUM' +CMC_3DLUT_SIZE_ENUM__enumvalues = { + 0: 'CMC_3DLUT_17CUBE', + 1: 'CMC_3DLUT_9CUBE', +} +CMC_3DLUT_17CUBE = 0 +CMC_3DLUT_9CUBE = 1 +CMC_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_2_CONFIG_ENUM' +CMC_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'CMC_LUT_2CFG_NO_MEMORY', + 1: 'CMC_LUT_2CFG_MEMORY_A', + 2: 'CMC_LUT_2CFG_MEMORY_B', +} +CMC_LUT_2CFG_NO_MEMORY = 0 +CMC_LUT_2CFG_MEMORY_A = 1 +CMC_LUT_2CFG_MEMORY_B = 2 +CMC_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_2_MODE_ENUM' +CMC_LUT_2_MODE_ENUM__enumvalues = { + 0: 'CMC_LUT_2_MODE_BYPASS', + 1: 'CMC_LUT_2_MODE_RAMA_LUT', + 2: 'CMC_LUT_2_MODE_RAMB_LUT', +} +CMC_LUT_2_MODE_BYPASS = 0 +CMC_LUT_2_MODE_RAMA_LUT = 1 +CMC_LUT_2_MODE_RAMB_LUT = 2 +CMC_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_NUM_SEG' +CMC_LUT_NUM_SEG__enumvalues = { + 0: 'CMC_SEGMENTS_1', + 1: 'CMC_SEGMENTS_2', + 2: 'CMC_SEGMENTS_4', + 3: 'CMC_SEGMENTS_8', + 4: 'CMC_SEGMENTS_16', + 5: 'CMC_SEGMENTS_32', + 6: 'CMC_SEGMENTS_64', + 7: 'CMC_SEGMENTS_128', +} +CMC_SEGMENTS_1 = 0 +CMC_SEGMENTS_2 = 1 +CMC_SEGMENTS_4 = 2 +CMC_SEGMENTS_8 = 3 +CMC_SEGMENTS_16 = 4 +CMC_SEGMENTS_32 = 5 +CMC_SEGMENTS_64 = 6 +CMC_SEGMENTS_128 = 7 +CMC_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_RAM_SEL' +CMC_LUT_RAM_SEL__enumvalues = { + 0: 'CMC_RAMA_ACCESS', + 1: 'CMC_RAMB_ACCESS', +} +CMC_RAMA_ACCESS = 0 +CMC_RAMB_ACCESS = 1 +CMC_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_BYPASS' +CM_BYPASS__enumvalues = { + 0: 'NON_BYPASS', + 1: 'BYPASS_EN', +} +NON_BYPASS = 0 +BYPASS_EN = 1 +CM_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'CM_COEF_FORMAT_ENUM' +CM_COEF_FORMAT_ENUM__enumvalues = { + 0: 'FIX_S2_13', + 1: 'FIX_S3_12', +} +FIX_S2_13 = 0 +FIX_S3_12 = 1 +CM_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_DATA_SIGNED' +CM_DATA_SIGNED__enumvalues = { + 0: 'UNSIGNED', + 1: 'SIGNED', +} +UNSIGNED = 0 +SIGNED = 1 +CM_DATA_SIGNED = ctypes.c_uint32 # enum + +# values for enumeration 'CM_EN' +CM_EN__enumvalues = { + 0: 'CM_DISABLE', + 1: 'CM_ENABLE', +} +CM_DISABLE = 0 +CM_ENABLE = 1 +CM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMMA_LUT_MODE_ENUM' +CM_GAMMA_LUT_MODE_ENUM__enumvalues = { + 0: 'BYPASS', + 1: 'RESERVED_1', + 2: 'RAM_LUT', + 3: 'RESERVED_3', +} +BYPASS = 0 +RESERVED_1 = 1 +RAM_LUT = 2 +RESERVED_3 = 3 +CM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMMA_LUT_PWL_DISABLE_ENUM' +CM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { + 0: 'ENABLE_PWL', + 1: 'DISABLE_PWL', +} +ENABLE_PWL = 0 +DISABLE_PWL = 1 +CM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMMA_LUT_SEL_ENUM' +CM_GAMMA_LUT_SEL_ENUM__enumvalues = { + 0: 'RAMA', + 1: 'RAMB', +} +RAMA = 0 +RAMB = 1 +CM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMUT_REMAP_MODE_ENUM' +CM_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'BYPASS_GAMUT', + 1: 'GAMUT_COEF', + 2: 'GAMUT_COEF_B', +} +BYPASS_GAMUT = 0 +GAMUT_COEF = 1 +GAMUT_COEF_B = 2 +CM_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_2_CONFIG_ENUM' +CM_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'LUT_2CFG_NO_MEMORY', + 1: 'LUT_2CFG_MEMORY_A', + 2: 'LUT_2CFG_MEMORY_B', +} +LUT_2CFG_NO_MEMORY = 0 +LUT_2CFG_MEMORY_A = 1 +LUT_2CFG_MEMORY_B = 2 +CM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_2_MODE_ENUM' +CM_LUT_2_MODE_ENUM__enumvalues = { + 0: 'LUT_2_MODE_BYPASS', + 1: 'LUT_2_MODE_RAMA_LUT', + 2: 'LUT_2_MODE_RAMB_LUT', +} +LUT_2_MODE_BYPASS = 0 +LUT_2_MODE_RAMA_LUT = 1 +LUT_2_MODE_RAMB_LUT = 2 +CM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_4_CONFIG_ENUM' +CM_LUT_4_CONFIG_ENUM__enumvalues = { + 0: 'LUT_4CFG_NO_MEMORY', + 1: 'LUT_4CFG_ROM_A', + 2: 'LUT_4CFG_ROM_B', + 3: 'LUT_4CFG_MEMORY_A', + 4: 'LUT_4CFG_MEMORY_B', +} +LUT_4CFG_NO_MEMORY = 0 +LUT_4CFG_ROM_A = 1 +LUT_4CFG_ROM_B = 2 +LUT_4CFG_MEMORY_A = 3 +LUT_4CFG_MEMORY_B = 4 +CM_LUT_4_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_4_MODE_ENUM' +CM_LUT_4_MODE_ENUM__enumvalues = { + 0: 'LUT_4_MODE_BYPASS', + 1: 'LUT_4_MODE_ROMA_LUT', + 2: 'LUT_4_MODE_ROMB_LUT', + 3: 'LUT_4_MODE_RAMA_LUT', + 4: 'LUT_4_MODE_RAMB_LUT', +} +LUT_4_MODE_BYPASS = 0 +LUT_4_MODE_ROMA_LUT = 1 +LUT_4_MODE_ROMB_LUT = 2 +LUT_4_MODE_RAMA_LUT = 3 +LUT_4_MODE_RAMB_LUT = 4 +CM_LUT_4_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_CONFIG_MODE' +CM_LUT_CONFIG_MODE__enumvalues = { + 0: 'DIFFERENT_RGB', + 1: 'ALL_USE_R', +} +DIFFERENT_RGB = 0 +ALL_USE_R = 1 +CM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_NUM_SEG' +CM_LUT_NUM_SEG__enumvalues = { + 0: 'SEGMENTS_1', + 1: 'SEGMENTS_2', + 2: 'SEGMENTS_4', + 3: 'SEGMENTS_8', + 4: 'SEGMENTS_16', + 5: 'SEGMENTS_32', + 6: 'SEGMENTS_64', + 7: 'SEGMENTS_128', +} +SEGMENTS_1 = 0 +SEGMENTS_2 = 1 +SEGMENTS_4 = 2 +SEGMENTS_8 = 3 +SEGMENTS_16 = 4 +SEGMENTS_32 = 5 +SEGMENTS_64 = 6 +SEGMENTS_128 = 7 +CM_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_RAM_SEL' +CM_LUT_RAM_SEL__enumvalues = { + 0: 'RAMA_ACCESS', + 1: 'RAMB_ACCESS', +} +RAMA_ACCESS = 0 +RAMB_ACCESS = 1 +CM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_READ_COLOR_SEL' +CM_LUT_READ_COLOR_SEL__enumvalues = { + 0: 'BLUE_LUT', + 1: 'GREEN_LUT', + 2: 'RED_LUT', +} +BLUE_LUT = 0 +GREEN_LUT = 1 +RED_LUT = 2 +CM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_READ_DBG' +CM_LUT_READ_DBG__enumvalues = { + 0: 'DISABLE_DEBUG', + 1: 'ENABLE_DEBUG', +} +DISABLE_DEBUG = 0 +ENABLE_DEBUG = 1 +CM_LUT_READ_DBG = ctypes.c_uint32 # enum + +# values for enumeration 'CM_PENDING' +CM_PENDING__enumvalues = { + 0: 'CM_NOT_PENDING', + 1: 'CM_YES_PENDING', +} +CM_NOT_PENDING = 0 +CM_YES_PENDING = 1 +CM_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'CM_POST_CSC_MODE_ENUM' +CM_POST_CSC_MODE_ENUM__enumvalues = { + 0: 'BYPASS_POST_CSC', + 1: 'COEF_POST_CSC', + 2: 'COEF_POST_CSC_B', +} +BYPASS_POST_CSC = 0 +COEF_POST_CSC = 1 +COEF_POST_CSC_B = 2 +CM_POST_CSC_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_WRITE_BASE_ONLY' +CM_WRITE_BASE_ONLY__enumvalues = { + 0: 'WRITE_BOTH', + 1: 'WRITE_BASE_ONLY', +} +WRITE_BOTH = 0 +WRITE_BASE_ONLY = 1 +CM_WRITE_BASE_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_CUR_SEL' +CRC_CUR_SEL__enumvalues = { + 0: 'CRC_CUR_0', + 1: 'CRC_CUR_1', +} +CRC_CUR_0 = 0 +CRC_CUR_1 = 1 +CRC_CUR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_INTERLACE_SEL' +CRC_INTERLACE_SEL__enumvalues = { + 0: 'CRC_INTERLACE_0', + 1: 'CRC_INTERLACE_1', + 2: 'CRC_INTERLACE_2', + 3: 'CRC_INTERLACE_3', +} +CRC_INTERLACE_0 = 0 +CRC_INTERLACE_1 = 1 +CRC_INTERLACE_2 = 2 +CRC_INTERLACE_3 = 3 +CRC_INTERLACE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_IN_CUR_SEL' +CRC_IN_CUR_SEL__enumvalues = { + 0: 'CRC_IN_CUR_0', + 1: 'CRC_IN_CUR_1', + 2: 'CRC_IN_CUR_2', + 3: 'CRC_IN_CUR_3', +} +CRC_IN_CUR_0 = 0 +CRC_IN_CUR_1 = 1 +CRC_IN_CUR_2 = 2 +CRC_IN_CUR_3 = 3 +CRC_IN_CUR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_IN_PIX_SEL' +CRC_IN_PIX_SEL__enumvalues = { + 0: 'CRC_IN_PIX_0', + 1: 'CRC_IN_PIX_1', + 2: 'CRC_IN_PIX_2', + 3: 'CRC_IN_PIX_3', + 4: 'CRC_IN_PIX_4', + 5: 'CRC_IN_PIX_5', + 6: 'CRC_IN_PIX_6', + 7: 'CRC_IN_PIX_7', +} +CRC_IN_PIX_0 = 0 +CRC_IN_PIX_1 = 1 +CRC_IN_PIX_2 = 2 +CRC_IN_PIX_3 = 3 +CRC_IN_PIX_4 = 4 +CRC_IN_PIX_5 = 5 +CRC_IN_PIX_6 = 6 +CRC_IN_PIX_7 = 7 +CRC_IN_PIX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_SRC_SEL' +CRC_SRC_SEL__enumvalues = { + 0: 'CRC_SRC_0', + 1: 'CRC_SRC_1', + 2: 'CRC_SRC_2', + 3: 'CRC_SRC_3', +} +CRC_SRC_0 = 0 +CRC_SRC_1 = 1 +CRC_SRC_2 = 2 +CRC_SRC_3 = 3 +CRC_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_STEREO_SEL' +CRC_STEREO_SEL__enumvalues = { + 0: 'CRC_STEREO_0', + 1: 'CRC_STEREO_1', + 2: 'CRC_STEREO_2', + 3: 'CRC_STEREO_3', +} +CRC_STEREO_0 = 0 +CRC_STEREO_1 = 1 +CRC_STEREO_2 = 2 +CRC_STEREO_3 = 3 +CRC_STEREO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLK_SEL' +TEST_CLK_SEL__enumvalues = { + 0: 'TEST_CLK_SEL_0', + 1: 'TEST_CLK_SEL_1', + 2: 'TEST_CLK_SEL_2', + 3: 'TEST_CLK_SEL_3', + 4: 'TEST_CLK_SEL_4', + 5: 'TEST_CLK_SEL_5', + 6: 'TEST_CLK_SEL_6', + 7: 'TEST_CLK_SEL_7', +} +TEST_CLK_SEL_0 = 0 +TEST_CLK_SEL_1 = 1 +TEST_CLK_SEL_2 = 2 +TEST_CLK_SEL_3 = 3 +TEST_CLK_SEL_4 = 4 +TEST_CLK_SEL_5 = 5 +TEST_CLK_SEL_6 = 6 +TEST_CLK_SEL_7 = 7 +TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_ACTIVE' +PERFCOUNTER_ACTIVE__enumvalues = { + 0: 'PERFCOUNTER_IS_IDLE', + 1: 'PERFCOUNTER_IS_ACTIVE', +} +PERFCOUNTER_IS_IDLE = 0 +PERFCOUNTER_IS_ACTIVE = 1 +PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT0_STATE' +PERFCOUNTER_CNT0_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT0_STATE_RESET', + 1: 'PERFCOUNTER_CNT0_STATE_START', + 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT0_STATE_HW', +} +PERFCOUNTER_CNT0_STATE_RESET = 0 +PERFCOUNTER_CNT0_STATE_START = 1 +PERFCOUNTER_CNT0_STATE_FREEZE = 2 +PERFCOUNTER_CNT0_STATE_HW = 3 +PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT1_STATE' +PERFCOUNTER_CNT1_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT1_STATE_RESET', + 1: 'PERFCOUNTER_CNT1_STATE_START', + 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT1_STATE_HW', +} +PERFCOUNTER_CNT1_STATE_RESET = 0 +PERFCOUNTER_CNT1_STATE_START = 1 +PERFCOUNTER_CNT1_STATE_FREEZE = 2 +PERFCOUNTER_CNT1_STATE_HW = 3 +PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT2_STATE' +PERFCOUNTER_CNT2_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT2_STATE_RESET', + 1: 'PERFCOUNTER_CNT2_STATE_START', + 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT2_STATE_HW', +} +PERFCOUNTER_CNT2_STATE_RESET = 0 +PERFCOUNTER_CNT2_STATE_START = 1 +PERFCOUNTER_CNT2_STATE_FREEZE = 2 +PERFCOUNTER_CNT2_STATE_HW = 3 +PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT3_STATE' +PERFCOUNTER_CNT3_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT3_STATE_RESET', + 1: 'PERFCOUNTER_CNT3_STATE_START', + 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT3_STATE_HW', +} +PERFCOUNTER_CNT3_STATE_RESET = 0 +PERFCOUNTER_CNT3_STATE_START = 1 +PERFCOUNTER_CNT3_STATE_FREEZE = 2 +PERFCOUNTER_CNT3_STATE_HW = 3 +PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT4_STATE' +PERFCOUNTER_CNT4_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT4_STATE_RESET', + 1: 'PERFCOUNTER_CNT4_STATE_START', + 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT4_STATE_HW', +} +PERFCOUNTER_CNT4_STATE_RESET = 0 +PERFCOUNTER_CNT4_STATE_START = 1 +PERFCOUNTER_CNT4_STATE_FREEZE = 2 +PERFCOUNTER_CNT4_STATE_HW = 3 +PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT5_STATE' +PERFCOUNTER_CNT5_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT5_STATE_RESET', + 1: 'PERFCOUNTER_CNT5_STATE_START', + 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT5_STATE_HW', +} +PERFCOUNTER_CNT5_STATE_RESET = 0 +PERFCOUNTER_CNT5_STATE_START = 1 +PERFCOUNTER_CNT5_STATE_FREEZE = 2 +PERFCOUNTER_CNT5_STATE_HW = 3 +PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT6_STATE' +PERFCOUNTER_CNT6_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT6_STATE_RESET', + 1: 'PERFCOUNTER_CNT6_STATE_START', + 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT6_STATE_HW', +} +PERFCOUNTER_CNT6_STATE_RESET = 0 +PERFCOUNTER_CNT6_STATE_START = 1 +PERFCOUNTER_CNT6_STATE_FREEZE = 2 +PERFCOUNTER_CNT6_STATE_HW = 3 +PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT7_STATE' +PERFCOUNTER_CNT7_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT7_STATE_RESET', + 1: 'PERFCOUNTER_CNT7_STATE_START', + 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT7_STATE_HW', +} +PERFCOUNTER_CNT7_STATE_RESET = 0 +PERFCOUNTER_CNT7_STATE_START = 1 +PERFCOUNTER_CNT7_STATE_FREEZE = 2 +PERFCOUNTER_CNT7_STATE_HW = 3 +PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTL_SEL' +PERFCOUNTER_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_CNTL_SEL_0', + 1: 'PERFCOUNTER_CNTL_SEL_1', + 2: 'PERFCOUNTER_CNTL_SEL_2', + 3: 'PERFCOUNTER_CNTL_SEL_3', + 4: 'PERFCOUNTER_CNTL_SEL_4', + 5: 'PERFCOUNTER_CNTL_SEL_5', + 6: 'PERFCOUNTER_CNTL_SEL_6', + 7: 'PERFCOUNTER_CNTL_SEL_7', +} +PERFCOUNTER_CNTL_SEL_0 = 0 +PERFCOUNTER_CNTL_SEL_1 = 1 +PERFCOUNTER_CNTL_SEL_2 = 2 +PERFCOUNTER_CNTL_SEL_3 = 3 +PERFCOUNTER_CNTL_SEL_4 = 4 +PERFCOUNTER_CNTL_SEL_5 = 5 +PERFCOUNTER_CNTL_SEL_6 = 6 +PERFCOUNTER_CNTL_SEL_7 = 7 +PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' +PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { + 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', + 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', +} +PERFCOUNTER_CNTOFF_START_ENABLE = 0 +PERFCOUNTER_CNTOFF_START_DISABLE = 1 +PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' +PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { + 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', +} +PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 +PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 +PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 +PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CVALUE_SEL' +PERFCOUNTER_CVALUE_SEL__enumvalues = { + 0: 'PERFCOUNTER_CVALUE_SEL_47_0', + 1: 'PERFCOUNTER_CVALUE_SEL_15_0', + 2: 'PERFCOUNTER_CVALUE_SEL_31_16', + 3: 'PERFCOUNTER_CVALUE_SEL_47_32', + 4: 'PERFCOUNTER_CVALUE_SEL_11_0', + 5: 'PERFCOUNTER_CVALUE_SEL_23_12', + 6: 'PERFCOUNTER_CVALUE_SEL_35_24', + 7: 'PERFCOUNTER_CVALUE_SEL_47_36', +} +PERFCOUNTER_CVALUE_SEL_47_0 = 0 +PERFCOUNTER_CVALUE_SEL_15_0 = 1 +PERFCOUNTER_CVALUE_SEL_31_16 = 2 +PERFCOUNTER_CVALUE_SEL_47_32 = 3 +PERFCOUNTER_CVALUE_SEL_11_0 = 4 +PERFCOUNTER_CVALUE_SEL_23_12 = 5 +PERFCOUNTER_CVALUE_SEL_35_24 = 6 +PERFCOUNTER_CVALUE_SEL_47_36 = 7 +PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' +PERFCOUNTER_HW_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', + 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', +} +PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 +PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 +PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_STOP1_SEL' +PERFCOUNTER_HW_STOP1_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_STOP1_0', + 1: 'PERFCOUNTER_HW_STOP1_1', +} +PERFCOUNTER_HW_STOP1_0 = 0 +PERFCOUNTER_HW_STOP1_1 = 1 +PERFCOUNTER_HW_STOP1_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_STOP2_SEL' +PERFCOUNTER_HW_STOP2_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_STOP2_0', + 1: 'PERFCOUNTER_HW_STOP2_1', +} +PERFCOUNTER_HW_STOP2_0 = 0 +PERFCOUNTER_HW_STOP2_1 = 1 +PERFCOUNTER_HW_STOP2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INC_MODE' +PERFCOUNTER_INC_MODE__enumvalues = { + 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', + 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', + 2: 'PERFCOUNTER_INC_MODE_LSB', + 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', + 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', +} +PERFCOUNTER_INC_MODE_MULTI_BIT = 0 +PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 +PERFCOUNTER_INC_MODE_LSB = 2 +PERFCOUNTER_INC_MODE_POS_EDGE = 3 +PERFCOUNTER_INC_MODE_NEG_EDGE = 4 +PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_EN' +PERFCOUNTER_INT_EN__enumvalues = { + 0: 'PERFCOUNTER_INT_DISABLE', + 1: 'PERFCOUNTER_INT_ENABLE', +} +PERFCOUNTER_INT_DISABLE = 0 +PERFCOUNTER_INT_ENABLE = 1 +PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_TYPE' +PERFCOUNTER_INT_TYPE__enumvalues = { + 0: 'PERFCOUNTER_INT_TYPE_LEVEL', + 1: 'PERFCOUNTER_INT_TYPE_PULSE', +} +PERFCOUNTER_INT_TYPE_LEVEL = 0 +PERFCOUNTER_INT_TYPE_PULSE = 1 +PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_OFF_MASK' +PERFCOUNTER_OFF_MASK__enumvalues = { + 0: 'PERFCOUNTER_OFF_MASK_DISABLE', + 1: 'PERFCOUNTER_OFF_MASK_ENABLE', +} +PERFCOUNTER_OFF_MASK_DISABLE = 0 +PERFCOUNTER_OFF_MASK_ENABLE = 1 +PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RESTART_EN' +PERFCOUNTER_RESTART_EN__enumvalues = { + 0: 'PERFCOUNTER_RESTART_DISABLE', + 1: 'PERFCOUNTER_RESTART_ENABLE', +} +PERFCOUNTER_RESTART_DISABLE = 0 +PERFCOUNTER_RESTART_ENABLE = 1 +PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RUNEN_MODE' +PERFCOUNTER_RUNEN_MODE__enumvalues = { + 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', +} +PERFCOUNTER_RUNEN_MODE_LEVEL = 0 +PERFCOUNTER_RUNEN_MODE_EDGE = 1 +PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL0' +PERFCOUNTER_STATE_SEL0__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', +} +PERFCOUNTER_STATE_SEL0_GLOBAL = 0 +PERFCOUNTER_STATE_SEL0_LOCAL = 1 +PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL1' +PERFCOUNTER_STATE_SEL1__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', +} +PERFCOUNTER_STATE_SEL1_GLOBAL = 0 +PERFCOUNTER_STATE_SEL1_LOCAL = 1 +PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL2' +PERFCOUNTER_STATE_SEL2__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', +} +PERFCOUNTER_STATE_SEL2_GLOBAL = 0 +PERFCOUNTER_STATE_SEL2_LOCAL = 1 +PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL3' +PERFCOUNTER_STATE_SEL3__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', +} +PERFCOUNTER_STATE_SEL3_GLOBAL = 0 +PERFCOUNTER_STATE_SEL3_LOCAL = 1 +PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL4' +PERFCOUNTER_STATE_SEL4__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', +} +PERFCOUNTER_STATE_SEL4_GLOBAL = 0 +PERFCOUNTER_STATE_SEL4_LOCAL = 1 +PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL5' +PERFCOUNTER_STATE_SEL5__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', +} +PERFCOUNTER_STATE_SEL5_GLOBAL = 0 +PERFCOUNTER_STATE_SEL5_LOCAL = 1 +PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL6' +PERFCOUNTER_STATE_SEL6__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', +} +PERFCOUNTER_STATE_SEL6_GLOBAL = 0 +PERFCOUNTER_STATE_SEL6_LOCAL = 1 +PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL7' +PERFCOUNTER_STATE_SEL7__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', +} +PERFCOUNTER_STATE_SEL7_GLOBAL = 0 +PERFCOUNTER_STATE_SEL7_LOCAL = 1 +PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_AND_OR' +PERFMON_CNTOFF_AND_OR__enumvalues = { + 0: 'PERFMON_CNTOFF_OR', + 1: 'PERFMON_CNTOFF_AND', +} +PERFMON_CNTOFF_OR = 0 +PERFMON_CNTOFF_AND = 1 +PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_EN' +PERFMON_CNTOFF_INT_EN__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_DISABLE', + 1: 'PERFMON_CNTOFF_INT_ENABLE', +} +PERFMON_CNTOFF_INT_DISABLE = 0 +PERFMON_CNTOFF_INT_ENABLE = 1 +PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_TYPE' +PERFMON_CNTOFF_INT_TYPE__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', + 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', +} +PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 +PERFMON_CNTOFF_INT_TYPE_PULSE = 1 +PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_STATE' +PERFMON_STATE__enumvalues = { + 0: 'PERFMON_STATE_RESET', + 1: 'PERFMON_STATE_START', + 2: 'PERFMON_STATE_FREEZE', + 3: 'PERFMON_STATE_HW', +} +PERFMON_STATE_RESET = 0 +PERFMON_STATE_START = 1 +PERFMON_STATE_FREEZE = 2 +PERFMON_STATE_HW = 3 +PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'BIGK_FRAGMENT_SIZE' +BIGK_FRAGMENT_SIZE__enumvalues = { + 0: 'VM_PG_SIZE_4KB', + 1: 'VM_PG_SIZE_8KB', + 2: 'VM_PG_SIZE_16KB', + 3: 'VM_PG_SIZE_32KB', + 4: 'VM_PG_SIZE_64KB', + 5: 'VM_PG_SIZE_128KB', + 6: 'VM_PG_SIZE_256KB', + 7: 'VM_PG_SIZE_512KB', + 8: 'VM_PG_SIZE_1024KB', + 9: 'VM_PG_SIZE_2048KB', +} +VM_PG_SIZE_4KB = 0 +VM_PG_SIZE_8KB = 1 +VM_PG_SIZE_16KB = 2 +VM_PG_SIZE_32KB = 3 +VM_PG_SIZE_64KB = 4 +VM_PG_SIZE_128KB = 5 +VM_PG_SIZE_256KB = 6 +VM_PG_SIZE_512KB = 7 +VM_PG_SIZE_1024KB = 8 +VM_PG_SIZE_2048KB = 9 +BIGK_FRAGMENT_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'CHUNK_SIZE' +CHUNK_SIZE__enumvalues = { + 0: 'CHUNK_SIZE_1KB', + 1: 'CHUNK_SIZE_2KB', + 2: 'CHUNK_SIZE_4KB', + 3: 'CHUNK_SIZE_8KB', + 4: 'CHUNK_SIZE_16KB', + 5: 'CHUNK_SIZE_32KB', + 6: 'CHUNK_SIZE_64KB', +} +CHUNK_SIZE_1KB = 0 +CHUNK_SIZE_2KB = 1 +CHUNK_SIZE_4KB = 2 +CHUNK_SIZE_8KB = 3 +CHUNK_SIZE_16KB = 4 +CHUNK_SIZE_32KB = 5 +CHUNK_SIZE_64KB = 6 +CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'COMPAT_LEVEL' +COMPAT_LEVEL__enumvalues = { + 0: 'ADDR_GEN_ZERO', + 1: 'ADDR_GEN_ONE', + 2: 'ADDR_GEN_TWO', + 3: 'ADDR_RESERVED', +} +ADDR_GEN_ZERO = 0 +ADDR_GEN_ONE = 1 +ADDR_GEN_TWO = 2 +ADDR_RESERVED = 3 +COMPAT_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPTE_GROUP_SIZE' +DPTE_GROUP_SIZE__enumvalues = { + 0: 'DPTE_GROUP_SIZE_64B', + 1: 'DPTE_GROUP_SIZE_128B', + 2: 'DPTE_GROUP_SIZE_256B', + 3: 'DPTE_GROUP_SIZE_512B', + 4: 'DPTE_GROUP_SIZE_1024B', + 5: 'DPTE_GROUP_SIZE_2048B', +} +DPTE_GROUP_SIZE_64B = 0 +DPTE_GROUP_SIZE_128B = 1 +DPTE_GROUP_SIZE_256B = 2 +DPTE_GROUP_SIZE_512B = 3 +DPTE_GROUP_SIZE_1024B = 4 +DPTE_GROUP_SIZE_2048B = 5 +DPTE_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'FORCE_ONE_ROW_FOR_FRAME' +FORCE_ONE_ROW_FOR_FRAME__enumvalues = { + 0: 'FORCE_ONE_ROW_FOR_FRAME_0', + 1: 'FORCE_ONE_ROW_FOR_FRAME_1', +} +FORCE_ONE_ROW_FOR_FRAME_0 = 0 +FORCE_ONE_ROW_FOR_FRAME_1 = 1 +FORCE_ONE_ROW_FOR_FRAME = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_BLANK_EN' +HUBP_BLANK_EN__enumvalues = { + 0: 'HUBP_BLANK_SW_DEASSERT', + 1: 'HUBP_BLANK_SW_ASSERT', +} +HUBP_BLANK_SW_DEASSERT = 0 +HUBP_BLANK_SW_ASSERT = 1 +HUBP_BLANK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_IN_BLANK' +HUBP_IN_BLANK__enumvalues = { + 0: 'HUBP_IN_ACTIVE', + 1: 'HUBP_IN_VBLANK', +} +HUBP_IN_ACTIVE = 0 +HUBP_IN_VBLANK = 1 +HUBP_IN_BLANK = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_MEASURE_WIN_MODE_DCFCLK' +HUBP_MEASURE_WIN_MODE_DCFCLK__enumvalues = { + 0: 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', + 1: 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', + 2: 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', + 3: 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', +} +HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0 +HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 1 +HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 2 +HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 3 +HUBP_MEASURE_WIN_MODE_DCFCLK = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_NO_OUTSTANDING_REQ' +HUBP_NO_OUTSTANDING_REQ__enumvalues = { + 0: 'OUTSTANDING_REQ', + 1: 'NO_OUTSTANDING_REQ', +} +OUTSTANDING_REQ = 0 +NO_OUTSTANDING_REQ = 1 +HUBP_NO_OUTSTANDING_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_SOFT_RESET' +HUBP_SOFT_RESET__enumvalues = { + 0: 'HUBP_SOFT_RESET_ON', + 1: 'HUBP_SOFT_RESET_OFF', +} +HUBP_SOFT_RESET_ON = 0 +HUBP_SOFT_RESET_OFF = 1 +HUBP_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_TTU_DISABLE' +HUBP_TTU_DISABLE__enumvalues = { + 0: 'HUBP_TTU_ENABLED', + 1: 'HUBP_TTU_DISABLED', +} +HUBP_TTU_ENABLED = 0 +HUBP_TTU_DISABLED = 1 +HUBP_TTU_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_VREADY_AT_OR_AFTER_VSYNC' +HUBP_VREADY_AT_OR_AFTER_VSYNC__enumvalues = { + 0: 'VREADY_BEFORE_VSYNC', + 1: 'VREADY_AT_OR_AFTER_VSYNC', +} +VREADY_BEFORE_VSYNC = 0 +VREADY_AT_OR_AFTER_VSYNC = 1 +HUBP_VREADY_AT_OR_AFTER_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_VTG_SEL' +HUBP_VTG_SEL__enumvalues = { + 0: 'VTG_SEL_0', + 1: 'VTG_SEL_1', + 2: 'VTG_SEL_2', + 3: 'VTG_SEL_3', + 4: 'VTG_SEL_4', + 5: 'VTG_SEL_5', +} +VTG_SEL_0 = 0 +VTG_SEL_1 = 1 +VTG_SEL_2 = 2 +VTG_SEL_3 = 3 +VTG_SEL_4 = 4 +VTG_SEL_5 = 5 +HUBP_VTG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'H_MIRROR_EN' +H_MIRROR_EN__enumvalues = { + 0: 'HW_MIRRORING_DISABLE', + 1: 'HW_MIRRORING_ENABLE', +} +HW_MIRRORING_DISABLE = 0 +HW_MIRRORING_ENABLE = 1 +H_MIRROR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LEGACY_PIPE_INTERLEAVE' +LEGACY_PIPE_INTERLEAVE__enumvalues = { + 0: 'LEGACY_PIPE_INTERLEAVE_256B', + 1: 'LEGACY_PIPE_INTERLEAVE_512B', +} +LEGACY_PIPE_INTERLEAVE_256B = 0 +LEGACY_PIPE_INTERLEAVE_512B = 1 +LEGACY_PIPE_INTERLEAVE = ctypes.c_uint32 # enum + +# values for enumeration 'META_CHUNK_SIZE' +META_CHUNK_SIZE__enumvalues = { + 0: 'META_CHUNK_SIZE_1KB', + 1: 'META_CHUNK_SIZE_2KB', + 2: 'META_CHUNK_SIZE_4KB', + 3: 'META_CHUNK_SIZE_8KB', +} +META_CHUNK_SIZE_1KB = 0 +META_CHUNK_SIZE_2KB = 1 +META_CHUNK_SIZE_4KB = 2 +META_CHUNK_SIZE_8KB = 3 +META_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'META_LINEAR' +META_LINEAR__enumvalues = { + 0: 'META_SURF_TILED', + 1: 'META_SURF_LINEAR', +} +META_SURF_TILED = 0 +META_SURF_LINEAR = 1 +META_LINEAR = ctypes.c_uint32 # enum + +# values for enumeration 'MIN_CHUNK_SIZE' +MIN_CHUNK_SIZE__enumvalues = { + 0: 'NO_MIN_CHUNK_SIZE', + 1: 'MIN_CHUNK_SIZE_256B', + 2: 'MIN_CHUNK_SIZE_512B', + 3: 'MIN_CHUNK_SIZE_1024B', +} +NO_MIN_CHUNK_SIZE = 0 +MIN_CHUNK_SIZE_256B = 1 +MIN_CHUNK_SIZE_512B = 2 +MIN_CHUNK_SIZE_1024B = 3 +MIN_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'MIN_META_CHUNK_SIZE' +MIN_META_CHUNK_SIZE__enumvalues = { + 0: 'NO_MIN_META_CHUNK_SIZE', + 1: 'MIN_META_CHUNK_SIZE_64B', + 2: 'MIN_META_CHUNK_SIZE_128B', + 3: 'MIN_META_CHUNK_SIZE_256B', +} +NO_MIN_META_CHUNK_SIZE = 0 +MIN_META_CHUNK_SIZE_64B = 1 +MIN_META_CHUNK_SIZE_128B = 2 +MIN_META_CHUNK_SIZE_256B = 3 +MIN_META_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_ALIGNED' +PIPE_ALIGNED__enumvalues = { + 0: 'PIPE_UNALIGNED_SURF', + 1: 'PIPE_ALIGNED_SURF', +} +PIPE_UNALIGNED_SURF = 0 +PIPE_ALIGNED_SURF = 1 +PIPE_ALIGNED = ctypes.c_uint32 # enum + +# values for enumeration 'PTE_BUFFER_MODE' +PTE_BUFFER_MODE__enumvalues = { + 0: 'PTE_BUFFER_MODE_0', + 1: 'PTE_BUFFER_MODE_1', +} +PTE_BUFFER_MODE_0 = 0 +PTE_BUFFER_MODE_1 = 1 +PTE_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PTE_ROW_HEIGHT_LINEAR' +PTE_ROW_HEIGHT_LINEAR__enumvalues = { + 0: 'PTE_ROW_HEIGHT_LINEAR_8L', + 1: 'PTE_ROW_HEIGHT_LINEAR_16L', + 2: 'PTE_ROW_HEIGHT_LINEAR_32L', + 3: 'PTE_ROW_HEIGHT_LINEAR_64L', + 4: 'PTE_ROW_HEIGHT_LINEAR_128L', + 5: 'PTE_ROW_HEIGHT_LINEAR_256L', + 6: 'PTE_ROW_HEIGHT_LINEAR_512L', + 7: 'PTE_ROW_HEIGHT_LINEAR_1024L', +} +PTE_ROW_HEIGHT_LINEAR_8L = 0 +PTE_ROW_HEIGHT_LINEAR_16L = 1 +PTE_ROW_HEIGHT_LINEAR_32L = 2 +PTE_ROW_HEIGHT_LINEAR_64L = 3 +PTE_ROW_HEIGHT_LINEAR_128L = 4 +PTE_ROW_HEIGHT_LINEAR_256L = 5 +PTE_ROW_HEIGHT_LINEAR_512L = 6 +PTE_ROW_HEIGHT_LINEAR_1024L = 7 +PTE_ROW_HEIGHT_LINEAR = ctypes.c_uint32 # enum + +# values for enumeration 'ROTATION_ANGLE' +ROTATION_ANGLE__enumvalues = { + 0: 'ROTATE_0_DEGREES', + 1: 'ROTATE_90_DEGREES', + 2: 'ROTATE_180_DEGREES', + 3: 'ROTATE_270_DEGREES', +} +ROTATE_0_DEGREES = 0 +ROTATE_90_DEGREES = 1 +ROTATE_180_DEGREES = 2 +ROTATE_270_DEGREES = 3 +ROTATION_ANGLE = ctypes.c_uint32 # enum + +# values for enumeration 'SWATH_HEIGHT' +SWATH_HEIGHT__enumvalues = { + 0: 'SWATH_HEIGHT_1L', + 1: 'SWATH_HEIGHT_2L', + 2: 'SWATH_HEIGHT_4L', + 3: 'SWATH_HEIGHT_8L', + 4: 'SWATH_HEIGHT_16L', +} +SWATH_HEIGHT_1L = 0 +SWATH_HEIGHT_2L = 1 +SWATH_HEIGHT_4L = 2 +SWATH_HEIGHT_8L = 3 +SWATH_HEIGHT_16L = 4 +SWATH_HEIGHT = ctypes.c_uint32 # enum + +# values for enumeration 'USE_MALL_FOR_CURSOR' +USE_MALL_FOR_CURSOR__enumvalues = { + 0: 'USE_MALL_FOR_CURSOR_0', + 1: 'USE_MALL_FOR_CURSOR_1', +} +USE_MALL_FOR_CURSOR_0 = 0 +USE_MALL_FOR_CURSOR_1 = 1 +USE_MALL_FOR_CURSOR = ctypes.c_uint32 # enum + +# values for enumeration 'USE_MALL_FOR_PSTATE_CHANGE' +USE_MALL_FOR_PSTATE_CHANGE__enumvalues = { + 0: 'USE_MALL_FOR_PSTATE_CHANGE_0', + 1: 'USE_MALL_FOR_PSTATE_CHANGE_1', +} +USE_MALL_FOR_PSTATE_CHANGE_0 = 0 +USE_MALL_FOR_PSTATE_CHANGE_1 = 1 +USE_MALL_FOR_PSTATE_CHANGE = ctypes.c_uint32 # enum + +# values for enumeration 'USE_MALL_FOR_STATIC_SCREEN' +USE_MALL_FOR_STATIC_SCREEN__enumvalues = { + 0: 'USE_MALL_FOR_STATIC_SCREEN_0', + 1: 'USE_MALL_FOR_STATIC_SCREEN_1', +} +USE_MALL_FOR_STATIC_SCREEN_0 = 0 +USE_MALL_FOR_STATIC_SCREEN_1 = 1 +USE_MALL_FOR_STATIC_SCREEN = ctypes.c_uint32 # enum + +# values for enumeration 'VMPG_SIZE' +VMPG_SIZE__enumvalues = { + 0: 'VMPG_SIZE_4KB', + 1: 'VMPG_SIZE_64KB', +} +VMPG_SIZE_4KB = 0 +VMPG_SIZE_64KB = 1 +VMPG_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'VM_GROUP_SIZE' +VM_GROUP_SIZE__enumvalues = { + 0: 'VM_GROUP_SIZE_64B', + 1: 'VM_GROUP_SIZE_128B', + 2: 'VM_GROUP_SIZE_256B', + 3: 'VM_GROUP_SIZE_512B', + 4: 'VM_GROUP_SIZE_1024B', + 5: 'VM_GROUP_SIZE_2048B', +} +VM_GROUP_SIZE_64B = 0 +VM_GROUP_SIZE_128B = 1 +VM_GROUP_SIZE_256B = 2 +VM_GROUP_SIZE_512B = 3 +VM_GROUP_SIZE_1024B = 4 +VM_GROUP_SIZE_2048B = 5 +VM_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_MIN_FREE_ENTRIES' +DFQ_MIN_FREE_ENTRIES__enumvalues = { + 0: 'DFQ_MIN_FREE_ENTRIES_0', + 1: 'DFQ_MIN_FREE_ENTRIES_1', + 2: 'DFQ_MIN_FREE_ENTRIES_2', + 3: 'DFQ_MIN_FREE_ENTRIES_3', + 4: 'DFQ_MIN_FREE_ENTRIES_4', + 5: 'DFQ_MIN_FREE_ENTRIES_5', + 6: 'DFQ_MIN_FREE_ENTRIES_6', + 7: 'DFQ_MIN_FREE_ENTRIES_7', +} +DFQ_MIN_FREE_ENTRIES_0 = 0 +DFQ_MIN_FREE_ENTRIES_1 = 1 +DFQ_MIN_FREE_ENTRIES_2 = 2 +DFQ_MIN_FREE_ENTRIES_3 = 3 +DFQ_MIN_FREE_ENTRIES_4 = 4 +DFQ_MIN_FREE_ENTRIES_5 = 5 +DFQ_MIN_FREE_ENTRIES_6 = 6 +DFQ_MIN_FREE_ENTRIES_7 = 7 +DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_NUM_ENTRIES' +DFQ_NUM_ENTRIES__enumvalues = { + 0: 'DFQ_NUM_ENTRIES_0', + 1: 'DFQ_NUM_ENTRIES_1', + 2: 'DFQ_NUM_ENTRIES_2', + 3: 'DFQ_NUM_ENTRIES_3', + 4: 'DFQ_NUM_ENTRIES_4', + 5: 'DFQ_NUM_ENTRIES_5', + 6: 'DFQ_NUM_ENTRIES_6', + 7: 'DFQ_NUM_ENTRIES_7', + 8: 'DFQ_NUM_ENTRIES_8', +} +DFQ_NUM_ENTRIES_0 = 0 +DFQ_NUM_ENTRIES_1 = 1 +DFQ_NUM_ENTRIES_2 = 2 +DFQ_NUM_ENTRIES_3 = 3 +DFQ_NUM_ENTRIES_4 = 4 +DFQ_NUM_ENTRIES_5 = 5 +DFQ_NUM_ENTRIES_6 = 6 +DFQ_NUM_ENTRIES_7 = 7 +DFQ_NUM_ENTRIES_8 = 8 +DFQ_NUM_ENTRIES = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_SIZE' +DFQ_SIZE__enumvalues = { + 0: 'DFQ_SIZE_0', + 1: 'DFQ_SIZE_1', + 2: 'DFQ_SIZE_2', + 3: 'DFQ_SIZE_3', + 4: 'DFQ_SIZE_4', + 5: 'DFQ_SIZE_5', + 6: 'DFQ_SIZE_6', + 7: 'DFQ_SIZE_7', +} +DFQ_SIZE_0 = 0 +DFQ_SIZE_1 = 1 +DFQ_SIZE_2 = 2 +DFQ_SIZE_3 = 3 +DFQ_SIZE_4 = 4 +DFQ_SIZE_5 = 5 +DFQ_SIZE_6 = 6 +DFQ_SIZE_7 = 7 +DFQ_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_VM_DONE' +DMDATA_VM_DONE__enumvalues = { + 0: 'DMDATA_VM_IS_NOT_DONE', + 1: 'DMDATA_VM_IS_DONE', +} +DMDATA_VM_IS_NOT_DONE = 0 +DMDATA_VM_IS_DONE = 1 +DMDATA_VM_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'EXPANSION_MODE' +EXPANSION_MODE__enumvalues = { + 0: 'EXPANSION_MODE_ZERO', + 1: 'EXPANSION_MODE_CONSERVATIVE', + 2: 'EXPANSION_MODE_OPTIMAL', +} +EXPANSION_MODE_ZERO = 0 +EXPANSION_MODE_CONSERVATIVE = 1 +EXPANSION_MODE_OPTIMAL = 2 +EXPANSION_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FLIP_RATE' +FLIP_RATE__enumvalues = { + 0: 'FLIP_RATE_0', + 1: 'FLIP_RATE_1', + 2: 'FLIP_RATE_2', + 3: 'FLIP_RATE_3', + 4: 'FLIP_RATE_4', + 5: 'FLIP_RATE_5', + 6: 'FLIP_RATE_6', + 7: 'FLIP_RATE_7', +} +FLIP_RATE_0 = 0 +FLIP_RATE_1 = 1 +FLIP_RATE_2 = 2 +FLIP_RATE_3 = 3 +FLIP_RATE_4 = 4 +FLIP_RATE_5 = 5 +FLIP_RATE_6 = 6 +FLIP_RATE_7 = 7 +FLIP_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'INT_MASK' +INT_MASK__enumvalues = { + 0: 'INT_DISABLED', + 1: 'INT_ENABLED', +} +INT_DISABLED = 0 +INT_ENABLED = 1 +INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_IN_FLUSH_URGENT' +PIPE_IN_FLUSH_URGENT__enumvalues = { + 0: 'PIPE_IN_FLUSH_URGENT_ENABLE', + 1: 'PIPE_IN_FLUSH_URGENT_DISABLE', +} +PIPE_IN_FLUSH_URGENT_ENABLE = 0 +PIPE_IN_FLUSH_URGENT_DISABLE = 1 +PIPE_IN_FLUSH_URGENT = ctypes.c_uint32 # enum + +# values for enumeration 'PRQ_MRQ_FLUSH_URGENT' +PRQ_MRQ_FLUSH_URGENT__enumvalues = { + 0: 'PRQ_MRQ_FLUSH_URGENT_ENABLE', + 1: 'PRQ_MRQ_FLUSH_URGENT_DISABLE', +} +PRQ_MRQ_FLUSH_URGENT_ENABLE = 0 +PRQ_MRQ_FLUSH_URGENT_DISABLE = 1 +PRQ_MRQ_FLUSH_URGENT = ctypes.c_uint32 # enum + +# values for enumeration 'ROW_TTU_MODE' +ROW_TTU_MODE__enumvalues = { + 0: 'END_OF_ROW_MODE', + 1: 'WATERMARK_MODE', +} +END_OF_ROW_MODE = 0 +WATERMARK_MODE = 1 +ROW_TTU_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC' +SURFACE_DCC__enumvalues = { + 0: 'SURFACE_IS_NOT_DCC', + 1: 'SURFACE_IS_DCC', +} +SURFACE_IS_NOT_DCC = 0 +SURFACE_IS_DCC = 1 +SURFACE_DCC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_128B' +SURFACE_DCC_IND_128B__enumvalues = { + 0: 'SURFACE_DCC_IS_NOT_IND_128B', + 1: 'SURFACE_DCC_IS_IND_128B', +} +SURFACE_DCC_IS_NOT_IND_128B = 0 +SURFACE_DCC_IS_IND_128B = 1 +SURFACE_DCC_IND_128B = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_64B' +SURFACE_DCC_IND_64B__enumvalues = { + 0: 'SURFACE_DCC_IS_NOT_IND_64B', + 1: 'SURFACE_DCC_IS_IND_64B', +} +SURFACE_DCC_IS_NOT_IND_64B = 0 +SURFACE_DCC_IS_IND_64B = 1 +SURFACE_DCC_IND_64B = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_BLK' +SURFACE_DCC_IND_BLK__enumvalues = { + 0: 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', + 1: 'SURFACE_DCC_BLOCK_IS_IND_64B', + 2: 'SURFACE_DCC_BLOCK_IS_IND_128B', + 3: 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', +} +SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0 +SURFACE_DCC_BLOCK_IS_IND_64B = 1 +SURFACE_DCC_BLOCK_IS_IND_128B = 2 +SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 3 +SURFACE_DCC_IND_BLK = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_AWAY_INT_TYPE' +SURFACE_FLIP_AWAY_INT_TYPE__enumvalues = { + 0: 'SURFACE_FLIP_AWAY_INT_LEVEL', + 1: 'SURFACE_FLIP_AWAY_INT_PULSE', +} +SURFACE_FLIP_AWAY_INT_LEVEL = 0 +SURFACE_FLIP_AWAY_INT_PULSE = 1 +SURFACE_FLIP_AWAY_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_EXEC_DEBUG_MODE' +SURFACE_FLIP_EXEC_DEBUG_MODE__enumvalues = { + 0: 'SURFACE_FLIP_EXEC_NORMAL_MODE', + 1: 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', +} +SURFACE_FLIP_EXEC_NORMAL_MODE = 0 +SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 1 +SURFACE_FLIP_EXEC_DEBUG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_INT_TYPE' +SURFACE_FLIP_INT_TYPE__enumvalues = { + 0: 'SURFACE_FLIP_INT_LEVEL', + 1: 'SURFACE_FLIP_INT_PULSE', +} +SURFACE_FLIP_INT_LEVEL = 0 +SURFACE_FLIP_INT_PULSE = 1 +SURFACE_FLIP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_IN_STEREOSYNC' +SURFACE_FLIP_IN_STEREOSYNC__enumvalues = { + 0: 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', + 1: 'SURFACE_FLIP_IN_STEREOSYNC_MODE', +} +SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0 +SURFACE_FLIP_IN_STEREOSYNC_MODE = 1 +SURFACE_FLIP_IN_STEREOSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_MODE_FOR_STEREOSYNC' +SURFACE_FLIP_MODE_FOR_STEREOSYNC__enumvalues = { + 0: 'FLIP_ANY_FRAME', + 1: 'FLIP_LEFT_EYE', + 2: 'FLIP_RIGHT_EYE', + 3: 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', +} +FLIP_ANY_FRAME = 0 +FLIP_LEFT_EYE = 1 +FLIP_RIGHT_EYE = 2 +SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 3 +SURFACE_FLIP_MODE_FOR_STEREOSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_DISABLE' +SURFACE_FLIP_STEREO_SELECT_DISABLE__enumvalues = { + 0: 'SURFACE_FLIP_STEREO_SELECT_ENABLED', + 1: 'SURFACE_FLIP_STEREO_SELECT_DISABLED', +} +SURFACE_FLIP_STEREO_SELECT_ENABLED = 0 +SURFACE_FLIP_STEREO_SELECT_DISABLED = 1 +SURFACE_FLIP_STEREO_SELECT_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_POLARITY' +SURFACE_FLIP_STEREO_SELECT_POLARITY__enumvalues = { + 0: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', + 1: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', +} +SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0 +SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 1 +SURFACE_FLIP_STEREO_SELECT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_TYPE' +SURFACE_FLIP_TYPE__enumvalues = { + 0: 'SURFACE_V_FLIP', + 1: 'SURFACE_I_FLIP', +} +SURFACE_V_FLIP = 0 +SURFACE_I_FLIP = 1 +SURFACE_FLIP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_VUPDATE_SKIP_NUM' +SURFACE_FLIP_VUPDATE_SKIP_NUM__enumvalues = { + 0: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', + 1: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', + 2: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', + 3: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', + 4: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', + 5: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', + 6: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', + 7: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', + 8: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', + 9: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', + 10: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', + 11: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', + 12: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', + 13: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', + 14: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', + 15: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', +} +SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0 +SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 1 +SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 2 +SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 3 +SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 4 +SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 5 +SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 6 +SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 7 +SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 8 +SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 9 +SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 10 +SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 11 +SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 12 +SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 13 +SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 14 +SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 15 +SURFACE_FLIP_VUPDATE_SKIP_NUM = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_INUSE_RAED_NO_LATCH' +SURFACE_INUSE_RAED_NO_LATCH__enumvalues = { + 0: 'SURFACE_INUSE_IS_LATCHED', + 1: 'SURFACE_INUSE_IS_NOT_LATCHED', +} +SURFACE_INUSE_IS_LATCHED = 0 +SURFACE_INUSE_IS_NOT_LATCHED = 1 +SURFACE_INUSE_RAED_NO_LATCH = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_TMZ' +SURFACE_TMZ__enumvalues = { + 0: 'SURFACE_IS_NOT_TMZ', + 1: 'SURFACE_IS_TMZ', +} +SURFACE_IS_NOT_TMZ = 0 +SURFACE_IS_TMZ = 1 +SURFACE_TMZ = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_UPDATE_LOCK' +SURFACE_UPDATE_LOCK__enumvalues = { + 0: 'SURFACE_UPDATE_IS_UNLOCKED', + 1: 'SURFACE_UPDATE_IS_LOCKED', +} +SURFACE_UPDATE_IS_UNLOCKED = 0 +SURFACE_UPDATE_IS_LOCKED = 1 +SURFACE_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_ALPHA' +CROSSBAR_FOR_ALPHA__enumvalues = { + 0: 'ALPHA_DATA_ONTO_ALPHA_PORT', + 1: 'Y_G_DATA_ONTO_ALPHA_PORT', + 2: 'CB_B_DATA_ONTO_ALPHA_PORT', + 3: 'CR_R_DATA_ONTO_ALPHA_PORT', +} +ALPHA_DATA_ONTO_ALPHA_PORT = 0 +Y_G_DATA_ONTO_ALPHA_PORT = 1 +CB_B_DATA_ONTO_ALPHA_PORT = 2 +CR_R_DATA_ONTO_ALPHA_PORT = 3 +CROSSBAR_FOR_ALPHA = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_CB_B' +CROSSBAR_FOR_CB_B__enumvalues = { + 0: 'ALPHA_DATA_ONTO_CB_B_PORT', + 1: 'Y_G_DATA_ONTO_CB_B_PORT', + 2: 'CB_B_DATA_ONTO_CB_B_PORT', + 3: 'CR_R_DATA_ONTO_CB_B_PORT', +} +ALPHA_DATA_ONTO_CB_B_PORT = 0 +Y_G_DATA_ONTO_CB_B_PORT = 1 +CB_B_DATA_ONTO_CB_B_PORT = 2 +CR_R_DATA_ONTO_CB_B_PORT = 3 +CROSSBAR_FOR_CB_B = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_CR_R' +CROSSBAR_FOR_CR_R__enumvalues = { + 0: 'ALPHA_DATA_ONTO_CR_R_PORT', + 1: 'Y_G_DATA_ONTO_CR_R_PORT', + 2: 'CB_B_DATA_ONTO_CR_R_PORT', + 3: 'CR_R_DATA_ONTO_CR_R_PORT', +} +ALPHA_DATA_ONTO_CR_R_PORT = 0 +Y_G_DATA_ONTO_CR_R_PORT = 1 +CB_B_DATA_ONTO_CR_R_PORT = 2 +CR_R_DATA_ONTO_CR_R_PORT = 3 +CROSSBAR_FOR_CR_R = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_Y_G' +CROSSBAR_FOR_Y_G__enumvalues = { + 0: 'ALPHA_DATA_ONTO_Y_G_PORT', + 1: 'Y_G_DATA_ONTO_Y_G_PORT', + 2: 'CB_B_DATA_ONTO_Y_G_PORT', + 3: 'CR_R_DATA_ONTO_Y_G_PORT', +} +ALPHA_DATA_ONTO_Y_G_PORT = 0 +Y_G_DATA_ONTO_Y_G_PORT = 1 +CB_B_DATA_ONTO_Y_G_PORT = 2 +CR_R_DATA_ONTO_Y_G_PORT = 3 +CROSSBAR_FOR_Y_G = ctypes.c_uint32 # enum + +# values for enumeration 'DETILE_BUFFER_PACKER_ENABLE' +DETILE_BUFFER_PACKER_ENABLE__enumvalues = { + 0: 'DETILE_BUFFER_PACKER_IS_DISABLE', + 1: 'DETILE_BUFFER_PACKER_IS_ENABLE', +} +DETILE_BUFFER_PACKER_IS_DISABLE = 0 +DETILE_BUFFER_PACKER_IS_ENABLE = 1 +DETILE_BUFFER_PACKER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_DIS_MODE' +MEM_PWR_DIS_MODE__enumvalues = { + 0: 'MEM_POWER_DIS_MODE_ENABLE', + 1: 'MEM_POWER_DIS_MODE_DISABLE', +} +MEM_POWER_DIS_MODE_ENABLE = 0 +MEM_POWER_DIS_MODE_DISABLE = 1 +MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_MODE' +MEM_PWR_FORCE_MODE__enumvalues = { + 0: 'MEM_POWER_FORCE_MODE_OFF', + 1: 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', + 2: 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', + 3: 'MEM_POWER_FORCE_MODE_SHUT_DOWN', +} +MEM_POWER_FORCE_MODE_OFF = 0 +MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 1 +MEM_POWER_FORCE_MODE_DEEP_SLEEP = 2 +MEM_POWER_FORCE_MODE_SHUT_DOWN = 3 +MEM_PWR_FORCE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_STATUS' +MEM_PWR_STATUS__enumvalues = { + 0: 'MEM_POWER_STATUS_ON', + 1: 'MEM_POWER_STATUS_LIGHT_SLEEP', + 2: 'MEM_POWER_STATUS_DEEP_SLEEP', + 3: 'MEM_POWER_STATUS_SHUT_DOWN', +} +MEM_POWER_STATUS_ON = 0 +MEM_POWER_STATUS_LIGHT_SLEEP = 1 +MEM_POWER_STATUS_DEEP_SLEEP = 2 +MEM_POWER_STATUS_SHUT_DOWN = 3 +MEM_PWR_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_INT_MASK_MODE' +PIPE_INT_MASK_MODE__enumvalues = { + 0: 'PIPE_INT_MASK_MODE_DISABLE', + 1: 'PIPE_INT_MASK_MODE_ENABLE', +} +PIPE_INT_MASK_MODE_DISABLE = 0 +PIPE_INT_MASK_MODE_ENABLE = 1 +PIPE_INT_MASK_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_INT_TYPE_MODE' +PIPE_INT_TYPE_MODE__enumvalues = { + 0: 'PIPE_INT_TYPE_MODE_DISABLE', + 1: 'PIPE_INT_TYPE_MODE_ENABLE', +} +PIPE_INT_TYPE_MODE_DISABLE = 0 +PIPE_INT_TYPE_MODE_ENABLE = 1 +PIPE_INT_TYPE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE' +PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', +} +PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CROB_MEM_PWR_LIGHT_SLEEP_MODE' +CROB_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', + 2: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', +} +CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 +CROB_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_2X_MAGNIFY' +CURSOR_2X_MAGNIFY__enumvalues = { + 0: 'CURSOR_2X_MAGNIFY_IS_DISABLE', + 1: 'CURSOR_2X_MAGNIFY_IS_ENABLE', +} +CURSOR_2X_MAGNIFY_IS_DISABLE = 0 +CURSOR_2X_MAGNIFY_IS_ENABLE = 1 +CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_ENABLE' +CURSOR_ENABLE__enumvalues = { + 0: 'CURSOR_IS_DISABLE', + 1: 'CURSOR_IS_ENABLE', +} +CURSOR_IS_DISABLE = 0 +CURSOR_IS_ENABLE = 1 +CURSOR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_LINES_PER_CHUNK' +CURSOR_LINES_PER_CHUNK__enumvalues = { + 0: 'CURSOR_LINE_PER_CHUNK_1', + 1: 'CURSOR_LINE_PER_CHUNK_2', + 2: 'CURSOR_LINE_PER_CHUNK_4', + 3: 'CURSOR_LINE_PER_CHUNK_8', + 4: 'CURSOR_LINE_PER_CHUNK_16', +} +CURSOR_LINE_PER_CHUNK_1 = 0 +CURSOR_LINE_PER_CHUNK_2 = 1 +CURSOR_LINE_PER_CHUNK_4 = 2 +CURSOR_LINE_PER_CHUNK_8 = 3 +CURSOR_LINE_PER_CHUNK_16 = 4 +CURSOR_LINES_PER_CHUNK = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_MODE' +CURSOR_MODE__enumvalues = { + 0: 'CURSOR_MONO_2BIT', + 1: 'CURSOR_COLOR_24BIT_1BIT_AND', + 2: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', + 3: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 4: 'CURSOR_COLOR_64BIT_FP_PREMULT', + 5: 'CURSOR_COLOR_64BIT_FP_UNPREMULT', +} +CURSOR_MONO_2BIT = 0 +CURSOR_COLOR_24BIT_1BIT_AND = 1 +CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 +CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 +CURSOR_COLOR_64BIT_FP_PREMULT = 4 +CURSOR_COLOR_64BIT_FP_UNPREMULT = 5 +CURSOR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_EN' +CURSOR_PERFMON_LATENCY_MEASURE_EN__enumvalues = { + 0: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', + 1: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', +} +CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0 +CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 1 +CURSOR_PERFMON_LATENCY_MEASURE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_SEL' +CURSOR_PERFMON_LATENCY_MEASURE_SEL__enumvalues = { + 0: 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', + 1: 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', +} +CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0 +CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 1 +CURSOR_PERFMON_LATENCY_MEASURE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PITCH' +CURSOR_PITCH__enumvalues = { + 0: 'CURSOR_PITCH_64_PIXELS', + 1: 'CURSOR_PITCH_128_PIXELS', + 2: 'CURSOR_PITCH_256_PIXELS', +} +CURSOR_PITCH_64_PIXELS = 0 +CURSOR_PITCH_128_PIXELS = 1 +CURSOR_PITCH_256_PIXELS = 2 +CURSOR_PITCH = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_REQ_MODE' +CURSOR_REQ_MODE__enumvalues = { + 0: 'CURSOR_REQUEST_NORMALLY', + 1: 'CURSOR_REQUEST_EARLY', +} +CURSOR_REQUEST_NORMALLY = 0 +CURSOR_REQUEST_EARLY = 1 +CURSOR_REQ_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SNOOP' +CURSOR_SNOOP__enumvalues = { + 0: 'CURSOR_IS_NOT_SNOOP', + 1: 'CURSOR_IS_SNOOP', +} +CURSOR_IS_NOT_SNOOP = 0 +CURSOR_IS_SNOOP = 1 +CURSOR_SNOOP = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_STEREO_EN' +CURSOR_STEREO_EN__enumvalues = { + 0: 'CURSOR_STEREO_IS_DISABLED', + 1: 'CURSOR_STEREO_IS_ENABLED', +} +CURSOR_STEREO_IS_DISABLED = 0 +CURSOR_STEREO_IS_ENABLED = 1 +CURSOR_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SURFACE_TMZ' +CURSOR_SURFACE_TMZ__enumvalues = { + 0: 'CURSOR_SURFACE_IS_NOT_TMZ', + 1: 'CURSOR_SURFACE_IS_TMZ', +} +CURSOR_SURFACE_IS_NOT_TMZ = 0 +CURSOR_SURFACE_IS_TMZ = 1 +CURSOR_SURFACE_TMZ = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SYSTEM' +CURSOR_SYSTEM__enumvalues = { + 0: 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', + 1: 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', +} +CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0 +CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 1 +CURSOR_SYSTEM = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS' +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__enumvalues = { + 0: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', + 1: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', +} +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0 +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 1 +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_DONE' +DMDATA_DONE__enumvalues = { + 0: 'DMDATA_NOT_SENT_TO_DIG', + 1: 'DMDATA_SENT_TO_DIG', +} +DMDATA_NOT_SENT_TO_DIG = 0 +DMDATA_SENT_TO_DIG = 1 +DMDATA_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_MODE' +DMDATA_MODE__enumvalues = { + 0: 'DMDATA_SOFTWARE_UPDATE_MODE', + 1: 'DMDATA_HARDWARE_UPDATE_MODE', +} +DMDATA_SOFTWARE_UPDATE_MODE = 0 +DMDATA_HARDWARE_UPDATE_MODE = 1 +DMDATA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_QOS_MODE' +DMDATA_QOS_MODE__enumvalues = { + 0: 'DMDATA_QOS_LEVEL_FROM_TTU', + 1: 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', +} +DMDATA_QOS_LEVEL_FROM_TTU = 0 +DMDATA_QOS_LEVEL_FROM_SOFTWARE = 1 +DMDATA_QOS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_REPEAT' +DMDATA_REPEAT__enumvalues = { + 0: 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', + 1: 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', +} +DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0 +DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 1 +DMDATA_REPEAT = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UNDERFLOW' +DMDATA_UNDERFLOW__enumvalues = { + 0: 'DMDATA_NOT_UNDERFLOW', + 1: 'DMDATA_UNDERFLOWED', +} +DMDATA_NOT_UNDERFLOW = 0 +DMDATA_UNDERFLOWED = 1 +DMDATA_UNDERFLOW = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UNDERFLOW_CLEAR' +DMDATA_UNDERFLOW_CLEAR__enumvalues = { + 0: 'DMDATA_DONT_CLEAR', + 1: 'DMDATA_CLEAR_UNDERFLOW_STATUS', +} +DMDATA_DONT_CLEAR = 0 +DMDATA_CLEAR_UNDERFLOW_STATUS = 1 +DMDATA_UNDERFLOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UPDATED' +DMDATA_UPDATED__enumvalues = { + 0: 'DMDATA_NOT_UPDATED', + 1: 'DMDATA_WAS_UPDATED', +} +DMDATA_NOT_UPDATED = 0 +DMDATA_WAS_UPDATED = 1 +DMDATA_UPDATED = ctypes.c_uint32 # enum + +# values for enumeration 'RESPONSE_STATUS' +RESPONSE_STATUS__enumvalues = { + 0: 'OKAY', + 1: 'EXOKAY', + 2: 'SLVERR', + 3: 'DECERR', + 4: 'EARLY', + 5: 'OKAY_NODATA', + 6: 'PROTVIOL', + 7: 'TRANSERR', + 8: 'CMPTO', + 12: 'CRS', +} +OKAY = 0 +EXOKAY = 1 +SLVERR = 2 +DECERR = 3 +EARLY = 4 +OKAY_NODATA = 5 +PROTVIOL = 6 +TRANSERR = 7 +CMPTO = 8 +CRS = 12 +RESPONSE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE' +DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', + 2: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', +} +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 +DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCHUBBUB_MEM_PWR_DIS_MODE' +DCHUBBUB_MEM_PWR_DIS_MODE__enumvalues = { + 0: 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', + 1: 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', +} +DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0 +DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 1 +DCHUBBUB_MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCHUBBUB_MEM_PWR_MODE' +DCHUBBUB_MEM_PWR_MODE__enumvalues = { + 0: 'DCHUBBUB_MEM_POWER_MODE_OFF', + 1: 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', + 2: 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', + 3: 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', +} +DCHUBBUB_MEM_POWER_MODE_OFF = 0 +DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 1 +DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 2 +DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 3 +DCHUBBUB_MEM_PWR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET' +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET' +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_VUPDATE_LOCK_SET' +MPC_CFG_ADR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_CFG_VUPDATE_LOCK_SET' +MPC_CFG_CFG_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_CUR_VUPDATE_LOCK_SET' +MPC_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_MPC_TEST_CLK_SEL' +MPC_CFG_MPC_TEST_CLK_SEL__enumvalues = { + 0: 'MPC_CFG_MPC_TEST_CLK_SEL_0', + 1: 'MPC_CFG_MPC_TEST_CLK_SEL_1', + 2: 'MPC_CFG_MPC_TEST_CLK_SEL_2', + 3: 'MPC_CFG_MPC_TEST_CLK_SEL_3', +} +MPC_CFG_MPC_TEST_CLK_SEL_0 = 0 +MPC_CFG_MPC_TEST_CLK_SEL_1 = 1 +MPC_CFG_MPC_TEST_CLK_SEL_2 = 2 +MPC_CFG_MPC_TEST_CLK_SEL_3 = 3 +MPC_CFG_MPC_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN' +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', +} +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_INTERLACE_MODE' +MPC_CRC_CALC_INTERLACE_MODE__enumvalues = { + 0: 'MPC_CRC_INTERLACE_MODE_TOP', + 1: 'MPC_CRC_INTERLACE_MODE_BOTTOM', + 2: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', + 3: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', +} +MPC_CRC_INTERLACE_MODE_TOP = 0 +MPC_CRC_INTERLACE_MODE_BOTTOM = 1 +MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 2 +MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 3 +MPC_CRC_CALC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_MODE' +MPC_CRC_CALC_MODE__enumvalues = { + 0: 'MPC_CRC_ONE_SHOT_MODE', + 1: 'MPC_CRC_CONTINUOUS_MODE', +} +MPC_CRC_ONE_SHOT_MODE = 0 +MPC_CRC_CONTINUOUS_MODE = 1 +MPC_CRC_CALC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_STEREO_MODE' +MPC_CRC_CALC_STEREO_MODE__enumvalues = { + 0: 'MPC_CRC_STEREO_MODE_LEFT', + 1: 'MPC_CRC_STEREO_MODE_RIGHT', + 2: 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', + 3: 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', +} +MPC_CRC_STEREO_MODE_LEFT = 0 +MPC_CRC_STEREO_MODE_RIGHT = 1 +MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 2 +MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 3 +MPC_CRC_CALC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_SOURCE_SELECT' +MPC_CRC_SOURCE_SELECT__enumvalues = { + 0: 'MPC_CRC_SOURCE_SEL_DPP', + 1: 'MPC_CRC_SOURCE_SEL_OPP', + 2: 'MPC_CRC_SOURCE_SEL_DWB', + 3: 'MPC_CRC_SOURCE_SEL_OTHER', +} +MPC_CRC_SOURCE_SEL_DPP = 0 +MPC_CRC_SOURCE_SEL_OPP = 1 +MPC_CRC_SOURCE_SEL_DWB = 2 +MPC_CRC_SOURCE_SEL_OTHER = 3 +MPC_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_DEBUG_BUS1_DATA_SELECT' +MPC_DEBUG_BUS1_DATA_SELECT__enumvalues = { + 0: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG', + 1: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT', + 2: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1', + 3: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV', +} +MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG = 0 +MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT = 1 +MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1 = 2 +MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV = 3 +MPC_DEBUG_BUS1_DATA_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_DEBUG_BUS2_DATA_SELECT' +MPC_DEBUG_BUS2_DATA_SELECT__enumvalues = { + 0: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC', + 1: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT', + 2: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM', + 3: 'MPC_DEBUG_BUS2_DATA_SELECT_RES', +} +MPC_DEBUG_BUS2_DATA_SELECT_MPCC = 0 +MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT = 1 +MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM = 2 +MPC_DEBUG_BUS2_DATA_SELECT_RES = 3 +MPC_DEBUG_BUS2_DATA_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT' +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT__enumvalues = { + 0: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID', + 1: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID', + 2: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID', + 3: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID', + 4: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA', + 5: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA', + 6: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1', + 7: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID', +} +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID = 0 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID = 1 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID = 2 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID = 3 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA = 4 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA = 5 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1 = 6 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID = 7 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_DEBUG_BUS_MPCC_BYTE_SELECT' +MPC_DEBUG_BUS_MPCC_BYTE_SELECT__enumvalues = { + 0: 'MPC_DEBUG_BUS_MPCC_BYTE0', + 1: 'MPC_DEBUG_BUS_MPCC_BYTE1', + 2: 'MPC_DEBUG_BUS_MPCC_BYTE2', + 3: 'MPC_DEBUG_BUS_MPCC_BYTE3', +} +MPC_DEBUG_BUS_MPCC_BYTE0 = 0 +MPC_DEBUG_BUS_MPCC_BYTE1 = 1 +MPC_DEBUG_BUS_MPCC_BYTE2 = 2 +MPC_DEBUG_BUS_MPCC_BYTE3 = 3 +MPC_DEBUG_BUS_MPCC_BYTE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OCSC_COEF_FORMAT' +MPC_OCSC_COEF_FORMAT__enumvalues = { + 0: 'MPC_OCSC_COEF_FORMAT_S2_13', + 1: 'MPC_OCSC_COEF_FORMAT_S3_12', +} +MPC_OCSC_COEF_FORMAT_S2_13 = 0 +MPC_OCSC_COEF_FORMAT_S3_12 = 1 +MPC_OCSC_COEF_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN' +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', +} +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_CSC_MODE' +MPC_OUT_CSC_MODE__enumvalues = { + 0: 'MPC_OUT_CSC_MODE_0', + 1: 'MPC_OUT_CSC_MODE_1', + 2: 'MPC_OUT_CSC_MODE_2', + 3: 'MPC_OUT_CSC_MODE_RSV', +} +MPC_OUT_CSC_MODE_0 = 0 +MPC_OUT_CSC_MODE_1 = 1 +MPC_OUT_CSC_MODE_2 = 2 +MPC_OUT_CSC_MODE_RSV = 3 +MPC_OUT_CSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE' +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE__enumvalues = { + 0: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', + 1: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', + 2: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', + 3: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', + 4: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', + 5: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', + 6: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', + 7: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', +} +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 1 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 2 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 3 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 4 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 5 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 6 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 7 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_RATE_CONTROL_DISABLE_SET' +MPC_OUT_RATE_CONTROL_DISABLE_SET__enumvalues = { + 0: 'MPC_OUT_RATE_CONTROL_SET_ENABLE', + 1: 'MPC_OUT_RATE_CONTROL_SET_DISABLE', +} +MPC_OUT_RATE_CONTROL_SET_ENABLE = 0 +MPC_OUT_RATE_CONTROL_SET_DISABLE = 1 +MPC_OUT_RATE_CONTROL_DISABLE_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_BG_COLOR_BPC' +MPCC_BG_COLOR_BPC__enumvalues = { + 0: 'MPCC_BG_COLOR_BPC_8bit', + 1: 'MPCC_BG_COLOR_BPC_9bit', + 2: 'MPCC_BG_COLOR_BPC_10bit', + 3: 'MPCC_BG_COLOR_BPC_11bit', + 4: 'MPCC_BG_COLOR_BPC_12bit', +} +MPCC_BG_COLOR_BPC_8bit = 0 +MPCC_BG_COLOR_BPC_9bit = 1 +MPCC_BG_COLOR_BPC_10bit = 2 +MPCC_BG_COLOR_BPC_11bit = 3 +MPCC_BG_COLOR_BPC_12bit = 4 +MPCC_BG_COLOR_BPC = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY' +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', + 1: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', +} +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0 +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 1 +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE' +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', + 1: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 2: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', + 3: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', +} +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 2 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 3 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE' +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', + 1: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', +} +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0 +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 1 +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE' +MPCC_CONTROL_MPCC_BOT_GAIN_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', + 1: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', +} +MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0 +MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 1 +MPCC_CONTROL_MPCC_BOT_GAIN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_MODE' +MPCC_CONTROL_MPCC_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_MODE_BYPASS', + 1: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', + 2: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', + 3: 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', +} +MPCC_CONTROL_MPCC_MODE_BYPASS = 0 +MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 1 +MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 2 +MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 3 +MPCC_CONTROL_MPCC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_EN' +MPCC_SM_CONTROL_MPCC_SM_EN__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT' +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL' +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', +} +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL' +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', + 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', +} +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT' +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_MODE' +MPCC_SM_CONTROL_MPCC_SM_MODE__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', + 2: 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', + 4: 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', + 6: 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', +} +MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0 +MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 2 +MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 4 +MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 +MPCC_SM_CONTROL_MPCC_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN' +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE', +} +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM' +MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { + 0: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', + 1: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', +} +MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 +MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 +MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_GAMUT_REMAP_MODE_ENUM' +MPCC_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'MPCC_GAMUT_REMAP_MODE_0', + 1: 'MPCC_GAMUT_REMAP_MODE_1', + 2: 'MPCC_GAMUT_REMAP_MODE_2', + 3: 'MPCC_GAMUT_REMAP_MODE_RSV', +} +MPCC_GAMUT_REMAP_MODE_0 = 0 +MPCC_GAMUT_REMAP_MODE_1 = 1 +MPCC_GAMUT_REMAP_MODE_2 = 2 +MPCC_GAMUT_REMAP_MODE_RSV = 3 +MPCC_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_2_CONFIG_ENUM' +MPCC_OGAM_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', + 1: 'MPCC_OGAM_LUT_2CFG_MEMORY_A', + 2: 'MPCC_OGAM_LUT_2CFG_MEMORY_B', +} +MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0 +MPCC_OGAM_LUT_2CFG_MEMORY_A = 1 +MPCC_OGAM_LUT_2CFG_MEMORY_B = 2 +MPCC_OGAM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_CONFIG_MODE' +MPCC_OGAM_LUT_CONFIG_MODE__enumvalues = { + 0: 'MPCC_OGAM_DIFFERENT_RGB', + 1: 'MPCC_OGAM_ALL_USE_R', +} +MPCC_OGAM_DIFFERENT_RGB = 0 +MPCC_OGAM_ALL_USE_R = 1 +MPCC_OGAM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM' +MPCC_OGAM_LUT_PWL_DISABLE_ENUM__enumvalues = { + 0: 'MPCC_OGAM_ENABLE_PWL', + 1: 'MPCC_OGAM_DISABLE_PWL', +} +MPCC_OGAM_ENABLE_PWL = 0 +MPCC_OGAM_DISABLE_PWL = 1 +MPCC_OGAM_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL' +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', + 1: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', +} +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0 +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 1 +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_RAM_SEL' +MPCC_OGAM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_OGAM_RAMA_ACCESS', + 1: 'MPCC_OGAM_RAMB_ACCESS', +} +MPCC_OGAM_RAMA_ACCESS = 0 +MPCC_OGAM_RAMB_ACCESS = 1 +MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_READ_COLOR_SEL' +MPCC_OGAM_LUT_READ_COLOR_SEL__enumvalues = { + 0: 'MPCC_OGAM_BLUE_LUT', + 1: 'MPCC_OGAM_GREEN_LUT', + 2: 'MPCC_OGAM_RED_LUT', +} +MPCC_OGAM_BLUE_LUT = 0 +MPCC_OGAM_GREEN_LUT = 1 +MPCC_OGAM_RED_LUT = 2 +MPCC_OGAM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_READ_DBG' +MPCC_OGAM_LUT_READ_DBG__enumvalues = { + 0: 'MPCC_OGAM_DISABLE_DEBUG', + 1: 'MPCC_OGAM_ENABLE_DEBUG', +} +MPCC_OGAM_DISABLE_DEBUG = 0 +MPCC_OGAM_ENABLE_DEBUG = 1 +MPCC_OGAM_LUT_READ_DBG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_SEL_ENUM' +MPCC_OGAM_LUT_SEL_ENUM__enumvalues = { + 0: 'MPCC_OGAM_RAMA', + 1: 'MPCC_OGAM_RAMB', +} +MPCC_OGAM_RAMA = 0 +MPCC_OGAM_RAMB = 1 +MPCC_OGAM_LUT_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM' +MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM__enumvalues = { + 0: 'MPCC_OGAM_MODE_0', + 1: 'MPCC_OGAM_MODE_RSV1', + 2: 'MPCC_OGAM_MODE_2', + 3: 'MPCC_OGAM_MODE_RSV', +} +MPCC_OGAM_MODE_0 = 0 +MPCC_OGAM_MODE_RSV1 = 1 +MPCC_OGAM_MODE_2 = 2 +MPCC_OGAM_MODE_RSV = 3 +MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_NUM_SEG' +MPCC_OGAM_NUM_SEG__enumvalues = { + 0: 'MPCC_OGAM_SEGMENTS_1', + 1: 'MPCC_OGAM_SEGMENTS_2', + 2: 'MPCC_OGAM_SEGMENTS_4', + 3: 'MPCC_OGAM_SEGMENTS_8', + 4: 'MPCC_OGAM_SEGMENTS_16', + 5: 'MPCC_OGAM_SEGMENTS_32', + 6: 'MPCC_OGAM_SEGMENTS_64', + 7: 'MPCC_OGAM_SEGMENTS_128', +} +MPCC_OGAM_SEGMENTS_1 = 0 +MPCC_OGAM_SEGMENTS_2 = 1 +MPCC_OGAM_SEGMENTS_4 = 2 +MPCC_OGAM_SEGMENTS_8 = 3 +MPCC_OGAM_SEGMENTS_16 = 4 +MPCC_OGAM_SEGMENTS_32 = 5 +MPCC_OGAM_SEGMENTS_64 = 6 +MPCC_OGAM_SEGMENTS_128 = 7 +MPCC_OGAM_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN' +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', +} +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_3DLUT_30BIT_ENUM' +MPCC_MCM_3DLUT_30BIT_ENUM__enumvalues = { + 0: 'MPCC_MCM_3DLUT_36BIT', + 1: 'MPCC_MCM_3DLUT_30BIT', +} +MPCC_MCM_3DLUT_36BIT = 0 +MPCC_MCM_3DLUT_30BIT = 1 +MPCC_MCM_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_3DLUT_RAM_SEL' +MPCC_MCM_3DLUT_RAM_SEL__enumvalues = { + 0: 'MPCC_MCM_RAM0_ACCESS', + 1: 'MPCC_MCM_RAM1_ACCESS', + 2: 'MPCC_MCM_RAM2_ACCESS', + 3: 'MPCC_MCM_RAM3_ACCESS', +} +MPCC_MCM_RAM0_ACCESS = 0 +MPCC_MCM_RAM1_ACCESS = 1 +MPCC_MCM_RAM2_ACCESS = 2 +MPCC_MCM_RAM3_ACCESS = 3 +MPCC_MCM_3DLUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_3DLUT_SIZE_ENUM' +MPCC_MCM_3DLUT_SIZE_ENUM__enumvalues = { + 0: 'MPCC_MCM_3DLUT_17CUBE', + 1: 'MPCC_MCM_3DLUT_9CUBE', +} +MPCC_MCM_3DLUT_17CUBE = 0 +MPCC_MCM_3DLUT_9CUBE = 1 +MPCC_MCM_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMMA_LUT_MODE_ENUM' +MPCC_MCM_GAMMA_LUT_MODE_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMMA_LUT_BYPASS', + 1: 'MPCC_MCM_GAMMA_LUT_RESERVED_1', + 2: 'MPCC_MCM_GAMMA_LUT_RAM_LUT', + 3: 'MPCC_MCM_GAMMA_LUT_RESERVED_3', +} +MPCC_MCM_GAMMA_LUT_BYPASS = 0 +MPCC_MCM_GAMMA_LUT_RESERVED_1 = 1 +MPCC_MCM_GAMMA_LUT_RAM_LUT = 2 +MPCC_MCM_GAMMA_LUT_RESERVED_3 = 3 +MPCC_MCM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM' +MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', + 1: 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', +} +MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0 +MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 1 +MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMMA_LUT_SEL_ENUM' +MPCC_MCM_GAMMA_LUT_SEL_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMMA_LUT_RAMA', + 1: 'MPCC_MCM_GAMMA_LUT_RAMB', +} +MPCC_MCM_GAMMA_LUT_RAMA = 0 +MPCC_MCM_GAMMA_LUT_RAMB = 1 +MPCC_MCM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_2_MODE_ENUM' +MPCC_MCM_LUT_2_MODE_ENUM__enumvalues = { + 0: 'MPCC_MCM_LUT_2_MODE_BYPASS', + 1: 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', + 2: 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', +} +MPCC_MCM_LUT_2_MODE_BYPASS = 0 +MPCC_MCM_LUT_2_MODE_RAMA_LUT = 1 +MPCC_MCM_LUT_2_MODE_RAMB_LUT = 2 +MPCC_MCM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_CONFIG_MODE' +MPCC_MCM_LUT_CONFIG_MODE__enumvalues = { + 0: 'MPCC_MCM_LUT_DIFFERENT_RGB', + 1: 'MPCC_MCM_LUT_ALL_USE_R', +} +MPCC_MCM_LUT_DIFFERENT_RGB = 0 +MPCC_MCM_LUT_ALL_USE_R = 1 +MPCC_MCM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_NUM_SEG' +MPCC_MCM_LUT_NUM_SEG__enumvalues = { + 0: 'MPCC_MCM_LUT_SEGMENTS_1', + 1: 'MPCC_MCM_LUT_SEGMENTS_2', + 2: 'MPCC_MCM_LUT_SEGMENTS_4', + 3: 'MPCC_MCM_LUT_SEGMENTS_8', + 4: 'MPCC_MCM_LUT_SEGMENTS_16', + 5: 'MPCC_MCM_LUT_SEGMENTS_32', + 6: 'MPCC_MCM_LUT_SEGMENTS_64', + 7: 'MPCC_MCM_LUT_SEGMENTS_128', +} +MPCC_MCM_LUT_SEGMENTS_1 = 0 +MPCC_MCM_LUT_SEGMENTS_2 = 1 +MPCC_MCM_LUT_SEGMENTS_4 = 2 +MPCC_MCM_LUT_SEGMENTS_8 = 3 +MPCC_MCM_LUT_SEGMENTS_16 = 4 +MPCC_MCM_LUT_SEGMENTS_32 = 5 +MPCC_MCM_LUT_SEGMENTS_64 = 6 +MPCC_MCM_LUT_SEGMENTS_128 = 7 +MPCC_MCM_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_RAM_SEL' +MPCC_MCM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_MCM_LUT_RAMA_ACCESS', + 1: 'MPCC_MCM_LUT_RAMB_ACCESS', +} +MPCC_MCM_LUT_RAMA_ACCESS = 0 +MPCC_MCM_LUT_RAMB_ACCESS = 1 +MPCC_MCM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_READ_COLOR_SEL' +MPCC_MCM_LUT_READ_COLOR_SEL__enumvalues = { + 0: 'MPCC_MCM_LUT_BLUE_LUT', + 1: 'MPCC_MCM_LUT_GREEN_LUT', + 2: 'MPCC_MCM_LUT_RED_LUT', +} +MPCC_MCM_LUT_BLUE_LUT = 0 +MPCC_MCM_LUT_GREEN_LUT = 1 +MPCC_MCM_LUT_RED_LUT = 2 +MPCC_MCM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_READ_DBG' +MPCC_MCM_LUT_READ_DBG__enumvalues = { + 0: 'MPCC_MCM_LUT_DISABLE_DEBUG', + 1: 'MPCC_MCM_LUT_ENABLE_DEBUG', +} +MPCC_MCM_LUT_DISABLE_DEBUG = 0 +MPCC_MCM_LUT_ENABLE_DEBUG = 1 +MPCC_MCM_LUT_READ_DBG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_MEM_PWR_FORCE_ENUM' +MPCC_MCM_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'MPCC_MCM_MEM_PWR_FORCE_DIS', + 1: 'MPCC_MCM_MEM_PWR_FORCE_LS', + 2: 'MPCC_MCM_MEM_PWR_FORCE_DS', + 3: 'MPCC_MCM_MEM_PWR_FORCE_SD', +} +MPCC_MCM_MEM_PWR_FORCE_DIS = 0 +MPCC_MCM_MEM_PWR_FORCE_LS = 1 +MPCC_MCM_MEM_PWR_FORCE_DS = 2 +MPCC_MCM_MEM_PWR_FORCE_SD = 3 +MPCC_MCM_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_MEM_PWR_STATE_ENUM' +MPCC_MCM_MEM_PWR_STATE_ENUM__enumvalues = { + 0: 'MPCC_MCM_MEM_PWR_STATE_ON', + 1: 'MPCC_MCM_MEM_PWR_STATE_LS', + 2: 'MPCC_MCM_MEM_PWR_STATE_DS', + 3: 'MPCC_MCM_MEM_PWR_STATE_SD', +} +MPCC_MCM_MEM_PWR_STATE_ON = 0 +MPCC_MCM_MEM_PWR_STATE_LS = 1 +MPCC_MCM_MEM_PWR_STATE_DS = 2 +MPCC_MCM_MEM_PWR_STATE_SD = 3 +MPCC_MCM_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_BIT_DEPTH' +ENUM_DPG_BIT_DEPTH__enumvalues = { + 0: 'ENUM_DPG_BIT_DEPTH_6BPC', + 1: 'ENUM_DPG_BIT_DEPTH_8BPC', + 2: 'ENUM_DPG_BIT_DEPTH_10BPC', + 3: 'ENUM_DPG_BIT_DEPTH_12BPC', +} +ENUM_DPG_BIT_DEPTH_6BPC = 0 +ENUM_DPG_BIT_DEPTH_8BPC = 1 +ENUM_DPG_BIT_DEPTH_10BPC = 2 +ENUM_DPG_BIT_DEPTH_12BPC = 3 +ENUM_DPG_BIT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_DYNAMIC_RANGE' +ENUM_DPG_DYNAMIC_RANGE__enumvalues = { + 0: 'ENUM_DPG_DYNAMIC_RANGE_VESA', + 1: 'ENUM_DPG_DYNAMIC_RANGE_CEA', +} +ENUM_DPG_DYNAMIC_RANGE_VESA = 0 +ENUM_DPG_DYNAMIC_RANGE_CEA = 1 +ENUM_DPG_DYNAMIC_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_EN' +ENUM_DPG_EN__enumvalues = { + 0: 'ENUM_DPG_DISABLE', + 1: 'ENUM_DPG_ENABLE', +} +ENUM_DPG_DISABLE = 0 +ENUM_DPG_ENABLE = 1 +ENUM_DPG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_FIELD_POLARITY' +ENUM_DPG_FIELD_POLARITY__enumvalues = { + 0: 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', + 1: 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', +} +ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0 +ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1 +ENUM_DPG_FIELD_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_MODE' +ENUM_DPG_MODE__enumvalues = { + 0: 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', + 1: 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', + 2: 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', + 3: 'ENUM_DPG_MODE_VERTICAL_BAR', + 4: 'ENUM_DPG_MODE_HORIZONTAL_BAR', + 5: 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', + 6: 'ENUM_DPG_MODE_RGB_DUAL_RAMP', + 7: 'ENUM_DPG_MODE_RGB_XR_BIAS', +} +ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0 +ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 1 +ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 2 +ENUM_DPG_MODE_VERTICAL_BAR = 3 +ENUM_DPG_MODE_HORIZONTAL_BAR = 4 +ENUM_DPG_MODE_RGB_SINGLE_RAMP = 5 +ENUM_DPG_MODE_RGB_DUAL_RAMP = 6 +ENUM_DPG_MODE_RGB_XR_BIAS = 7 +ENUM_DPG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMTMEM_PWR_DIS_CTRL' +FMTMEM_PWR_DIS_CTRL__enumvalues = { + 0: 'FMTMEM_ENABLE_MEM_PWR_CTRL', + 1: 'FMTMEM_DISABLE_MEM_PWR_CTRL', +} +FMTMEM_ENABLE_MEM_PWR_CTRL = 0 +FMTMEM_DISABLE_MEM_PWR_CTRL = 1 +FMTMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'FMTMEM_PWR_FORCE_CTRL' +FMTMEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'FMTMEM_NO_FORCE_REQUEST', + 1: 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', +} +FMTMEM_NO_FORCE_REQUEST = 0 +FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 2 +FMTMEM_FORCE_SHUT_DOWN_REQUEST = 3 +FMTMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' +FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' +FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', +} +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' +FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' +FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { + 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', +} +FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 +FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 +FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 +FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 +FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 +FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { + 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', +} +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' +FMT_CONTROL_PIXEL_ENCODING__enumvalues = { + 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', +} +FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 +FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 +FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 +FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 +FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' +FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', +} +FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 +FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 +FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 +FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 +FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' +FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', +} +FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 +FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 +FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT' +FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = { + 0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', + 1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', + 2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', + 3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', +} +FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0 +FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1 +FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2 +FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3 +FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DYNAMIC_EXP_MODE' +FMT_DYNAMIC_EXP_MODE__enumvalues = { + 0: 'FMT_DYNAMIC_EXP_MODE_10to12', + 1: 'FMT_DYNAMIC_EXP_MODE_8to12', +} +FMT_DYNAMIC_EXP_MODE_10to12 = 0 +FMT_DYNAMIC_EXP_MODE_8to12 = 1 +FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_FRAME_RANDOM_ENABLE_CONTROL' +FMT_FRAME_RANDOM_ENABLE_CONTROL__enumvalues = { + 0: 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', + 1: 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', +} +FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0 +FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 1 +FMT_FRAME_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_POWER_STATE_ENUM' +FMT_POWER_STATE_ENUM__enumvalues = { + 0: 'FMT_POWER_STATE_ENUM_ON', + 1: 'FMT_POWER_STATE_ENUM_LS', + 2: 'FMT_POWER_STATE_ENUM_DS', + 3: 'FMT_POWER_STATE_ENUM_SD', +} +FMT_POWER_STATE_ENUM_ON = 0 +FMT_POWER_STATE_ENUM_LS = 1 +FMT_POWER_STATE_ENUM_DS = 2 +FMT_POWER_STATE_ENUM_SD = 3 +FMT_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_RGB_RANDOM_ENABLE_CONTROL' +FMT_RGB_RANDOM_ENABLE_CONTROL__enumvalues = { + 0: 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', + 1: 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', +} +FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0 +FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 1 +FMT_RGB_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL' +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL__enumvalues = { + 0: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', + 1: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', + 2: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', + 3: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', +} +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 1 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 2 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 3 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_SPATIAL_DITHER_MODE' +FMT_SPATIAL_DITHER_MODE__enumvalues = { + 0: 'FMT_SPATIAL_DITHER_MODE_0', + 1: 'FMT_SPATIAL_DITHER_MODE_1', + 2: 'FMT_SPATIAL_DITHER_MODE_2', + 3: 'FMT_SPATIAL_DITHER_MODE_3', +} +FMT_SPATIAL_DITHER_MODE_0 = 0 +FMT_SPATIAL_DITHER_MODE_1 = 1 +FMT_SPATIAL_DITHER_MODE_2 = 2 +FMT_SPATIAL_DITHER_MODE_3 = 3 +FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_STEREOSYNC_OVERRIDE_CONTROL' +FMT_STEREOSYNC_OVERRIDE_CONTROL__enumvalues = { + 0: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', + 1: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', +} +FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0 +FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 1 +FMT_STEREOSYNC_OVERRIDE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { + 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', +} +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum + +# values for enumeration 'OPPBUF_DISPLAY_SEGMENTATION' +OPPBUF_DISPLAY_SEGMENTATION__enumvalues = { + 0: 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', + 1: 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', + 2: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', + 3: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', + 4: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', +} +OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0 +OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1 +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2 +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3 +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4 +OPPBUF_DISPLAY_SEGMENTATION = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CLOCK_ENABLE_CONTROL' +OPP_PIPE_CLOCK_ENABLE_CONTROL__enumvalues = { + 0: 'OPP_PIPE_CLOCK_DISABLE', + 1: 'OPP_PIPE_CLOCK_ENABLE', +} +OPP_PIPE_CLOCK_DISABLE = 0 +OPP_PIPE_CLOCK_ENABLE = 1 +OPP_PIPE_CLOCK_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL' +OPP_PIPE_DIGTIAL_BYPASS_CONTROL__enumvalues = { + 0: 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', + 1: 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', +} +OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0 +OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 1 +OPP_PIPE_DIGTIAL_BYPASS_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_CONT_EN' +OPP_PIPE_CRC_CONT_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_MODE_ONE_SHOT', + 1: 'OPP_PIPE_CRC_MODE_CONTINUOUS', +} +OPP_PIPE_CRC_MODE_ONE_SHOT = 0 +OPP_PIPE_CRC_MODE_CONTINUOUS = 1 +OPP_PIPE_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_EN' +OPP_PIPE_CRC_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_DISABLE', + 1: 'OPP_PIPE_CRC_ENABLE', +} +OPP_PIPE_CRC_DISABLE = 0 +OPP_PIPE_CRC_ENABLE = 1 +OPP_PIPE_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_INTERLACE_EN' +OPP_PIPE_CRC_INTERLACE_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', + 1: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', +} +OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0 +OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 1 +OPP_PIPE_CRC_INTERLACE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_INTERLACE_MODE' +OPP_PIPE_CRC_INTERLACE_MODE__enumvalues = { + 0: 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', + 1: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', + 2: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', + 3: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', +} +OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0 +OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 1 +OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 2 +OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 3 +OPP_PIPE_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_ONE_SHOT_PENDING' +OPP_PIPE_CRC_ONE_SHOT_PENDING__enumvalues = { + 0: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', + 1: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', +} +OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0 +OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 1 +OPP_PIPE_CRC_ONE_SHOT_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_PIXEL_SELECT' +OPP_PIPE_CRC_PIXEL_SELECT__enumvalues = { + 0: 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', + 1: 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', + 2: 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', + 3: 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', +} +OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0 +OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 1 +OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 2 +OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 3 +OPP_PIPE_CRC_PIXEL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_SOURCE_SELECT' +OPP_PIPE_CRC_SOURCE_SELECT__enumvalues = { + 0: 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', + 1: 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', +} +OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0 +OPP_PIPE_CRC_SOURCE_SELECT_SFT = 1 +OPP_PIPE_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_STEREO_EN' +OPP_PIPE_CRC_STEREO_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', + 1: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', +} +OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0 +OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 1 +OPP_PIPE_CRC_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_STEREO_MODE' +OPP_PIPE_CRC_STEREO_MODE__enumvalues = { + 0: 'OPP_PIPE_CRC_STEREO_MODE_LEFT', + 1: 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', + 2: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', + 3: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', +} +OPP_PIPE_CRC_STEREO_MODE_LEFT = 0 +OPP_PIPE_CRC_STEREO_MODE_RIGHT = 1 +OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 2 +OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 3 +OPP_PIPE_CRC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_ABM_DEBUG_BUS_SELECT_CONTROL' +OPP_ABM_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_ABM0', + 1: 'DEBUG_BUS_SELECT_ABM1', + 2: 'DEBUG_BUS_SELECT_ABM2', + 3: 'DEBUG_BUS_SELECT_ABM3', + 4: 'DEBUG_BUS_SELECT_ABM_RESERVED0', + 5: 'DEBUG_BUS_SELECT_ABM_RESERVED1', +} +DEBUG_BUS_SELECT_ABM0 = 0 +DEBUG_BUS_SELECT_ABM1 = 1 +DEBUG_BUS_SELECT_ABM2 = 2 +DEBUG_BUS_SELECT_ABM3 = 3 +DEBUG_BUS_SELECT_ABM_RESERVED0 = 4 +DEBUG_BUS_SELECT_ABM_RESERVED1 = 5 +OPP_ABM_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_DPG_DEBUG_BUS_SELECT_CONTROL' +OPP_DPG_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_DPG0', + 1: 'DEBUG_BUS_SELECT_DPG1', + 2: 'DEBUG_BUS_SELECT_DPG2', + 3: 'DEBUG_BUS_SELECT_DPG3', + 4: 'DEBUG_BUS_SELECT_DPG_RESERVED0', + 5: 'DEBUG_BUS_SELECT_DPG_RESERVED1', +} +DEBUG_BUS_SELECT_DPG0 = 0 +DEBUG_BUS_SELECT_DPG1 = 1 +DEBUG_BUS_SELECT_DPG2 = 2 +DEBUG_BUS_SELECT_DPG3 = 3 +DEBUG_BUS_SELECT_DPG_RESERVED0 = 4 +DEBUG_BUS_SELECT_DPG_RESERVED1 = 5 +OPP_DPG_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_FMT_DEBUG_BUS_SELECT_CONTROL' +OPP_FMT_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_FMT0', + 1: 'DEBUG_BUS_SELECT_FMT1', + 2: 'DEBUG_BUS_SELECT_FMT2', + 3: 'DEBUG_BUS_SELECT_FMT3', + 4: 'DEBUG_BUS_SELECT_FMT_RESERVED0', + 5: 'DEBUG_BUS_SELECT_FMT_RESERVED1', +} +DEBUG_BUS_SELECT_FMT0 = 0 +DEBUG_BUS_SELECT_FMT1 = 1 +DEBUG_BUS_SELECT_FMT2 = 2 +DEBUG_BUS_SELECT_FMT3 = 3 +DEBUG_BUS_SELECT_FMT_RESERVED0 = 4 +DEBUG_BUS_SELECT_FMT_RESERVED1 = 5 +OPP_FMT_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL' +OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_OPPBUF0', + 1: 'DEBUG_BUS_SELECT_OPPBUF1', + 2: 'DEBUG_BUS_SELECT_OPPBUF2', + 3: 'DEBUG_BUS_SELECT_OPPBUF3', + 4: 'DEBUG_BUS_SELECT_OPPBUF_RESERVED0', + 5: 'DEBUG_BUS_SELECT_OPPBUF_RESERVED1', +} +DEBUG_BUS_SELECT_OPPBUF0 = 0 +DEBUG_BUS_SELECT_OPPBUF1 = 1 +DEBUG_BUS_SELECT_OPPBUF2 = 2 +DEBUG_BUS_SELECT_OPPBUF3 = 3 +DEBUG_BUS_SELECT_OPPBUF_RESERVED0 = 4 +DEBUG_BUS_SELECT_OPPBUF_RESERVED1 = 5 +OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL' +OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_OPP_PIPE0', + 1: 'DEBUG_BUS_SELECT_OPP_PIPE1', + 2: 'DEBUG_BUS_SELECT_OPP_PIPE2', + 3: 'DEBUG_BUS_SELECT_OPP_PIPE3', + 4: 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0', + 5: 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1', +} +DEBUG_BUS_SELECT_OPP_PIPE0 = 0 +DEBUG_BUS_SELECT_OPP_PIPE1 = 1 +DEBUG_BUS_SELECT_OPP_PIPE2 = 2 +DEBUG_BUS_SELECT_OPP_PIPE3 = 3 +DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0 = 4 +DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1 = 5 +OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TEST_CLK_SEL_CONTROL' +OPP_TEST_CLK_SEL_CONTROL__enumvalues = { + 0: 'OPP_TEST_CLK_SEL_DISPCLK_P', + 1: 'OPP_TEST_CLK_SEL_DISPCLK_R', + 2: 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', + 3: 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', + 4: 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', + 5: 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', + 6: 'OPP_TEST_CLK_SEL_RESERVED0', + 7: 'OPP_TEST_CLK_SEL_RESERVED1', + 8: 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', + 9: 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', + 10: 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', + 11: 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', + 12: 'OPP_TEST_CLK_SEL_RESERVED2', + 13: 'OPP_TEST_CLK_SEL_RESERVED3', +} +OPP_TEST_CLK_SEL_DISPCLK_P = 0 +OPP_TEST_CLK_SEL_DISPCLK_R = 1 +OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 2 +OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 3 +OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 4 +OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 5 +OPP_TEST_CLK_SEL_RESERVED0 = 6 +OPP_TEST_CLK_SEL_RESERVED1 = 7 +OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 8 +OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 9 +OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 10 +OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 11 +OPP_TEST_CLK_SEL_RESERVED2 = 12 +OPP_TEST_CLK_SEL_RESERVED3 = 13 +OPP_TEST_CLK_SEL_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TOP_CLOCK_ENABLE_STATUS' +OPP_TOP_CLOCK_ENABLE_STATUS__enumvalues = { + 0: 'OPP_TOP_CLOCK_DISABLED_STATUS', + 1: 'OPP_TOP_CLOCK_ENABLED_STATUS', +} +OPP_TOP_CLOCK_DISABLED_STATUS = 0 +OPP_TOP_CLOCK_ENABLED_STATUS = 1 +OPP_TOP_CLOCK_ENABLE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TOP_CLOCK_GATING_CONTROL' +OPP_TOP_CLOCK_GATING_CONTROL__enumvalues = { + 0: 'OPP_TOP_CLOCK_GATING_ENABLED', + 1: 'OPP_TOP_CLOCK_GATING_DISABLED', +} +OPP_TOP_CLOCK_GATING_ENABLED = 0 +OPP_TOP_CLOCK_GATING_DISABLED = 1 +OPP_TOP_CLOCK_GATING_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DSCRM_EN' +ENUM_DSCRM_EN__enumvalues = { + 0: 'ENUM_DSCRM_DISABLE', + 1: 'ENUM_DSCRM_ENABLE', +} +ENUM_DSCRM_DISABLE = 0 +ENUM_DSCRM_ENABLE = 1 +ENUM_DSCRM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', +} +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_SEL' +MASTER_UPDATE_LOCK_SEL__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_SEL_0', + 1: 'MASTER_UPDATE_LOCK_SEL_1', + 2: 'MASTER_UPDATE_LOCK_SEL_2', + 3: 'MASTER_UPDATE_LOCK_SEL_3', + 4: 'MASTER_UPDATE_LOCK_SEL_RESERVED4', + 5: 'MASTER_UPDATE_LOCK_SEL_RESERVED5', +} +MASTER_UPDATE_LOCK_SEL_0 = 0 +MASTER_UPDATE_LOCK_SEL_1 = 1 +MASTER_UPDATE_LOCK_SEL_2 = 2 +MASTER_UPDATE_LOCK_SEL_3 = 3 +MASTER_UPDATE_LOCK_SEL_RESERVED4 = 4 +MASTER_UPDATE_LOCK_SEL_RESERVED5 = 5 +MASTER_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { + 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', + 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', + 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', +} +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 1 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 2 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 2: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 3: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL' +OTG_CONTROL_OTG_DISABLE_POINT_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', + 1: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 2: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', + 3: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', +} +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 2 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL' +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', + 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', +} +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0 +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 1 +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY' +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY__enumvalues = { + 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', + 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', +} +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0 +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 1 +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_MASTER_EN' +OTG_CONTROL_OTG_MASTER_EN__enumvalues = { + 0: 'OTG_CONTROL_OTG_MASTER_EN_FALSE', + 1: 'OTG_CONTROL_OTG_MASTER_EN_TRUE', +} +OTG_CONTROL_OTG_MASTER_EN_FALSE = 0 +OTG_CONTROL_OTG_MASTER_EN_TRUE = 1 +OTG_CONTROL_OTG_MASTER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_OUT_MUX' +OTG_CONTROL_OTG_OUT_MUX__enumvalues = { + 0: 'OTG_CONTROL_OTG_OUT_MUX_0', + 1: 'OTG_CONTROL_OTG_OUT_MUX_1', + 2: 'OTG_CONTROL_OTG_OUT_MUX_2', +} +OTG_CONTROL_OTG_OUT_MUX_0 = 0 +OTG_CONTROL_OTG_OUT_MUX_1 = 1 +OTG_CONTROL_OTG_OUT_MUX_2 = 2 +OTG_CONTROL_OTG_OUT_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_START_POINT_CNTL' +OTG_CONTROL_OTG_START_POINT_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', + 1: 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', +} +OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0 +OTG_CONTROL_OTG_START_POINT_CNTL_DP = 1 +OTG_CONTROL_OTG_START_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN' +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN__enumvalues = { + 0: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', + 1: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', +} +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0 +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 1 +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC1_EN' +OTG_CRC_CNTL_OTG_CRC1_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC1_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_EN' +OTG_CRC_CNTL_OTG_CRC_CONT_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE' +OTG_CRC_CNTL_OTG_CRC_CONT_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', + 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', +} +OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0 +OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 1 +OTG_CRC_CNTL_OTG_CRC_CONT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_EN' +OTG_CRC_CNTL_OTG_CRC_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE' +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', + 1: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', + 2: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 3: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', +} +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 1 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 3 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE' +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', + 1: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', + 2: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', + 3: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', +} +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 1 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 2 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 3 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS' +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT' +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', + 1: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', + 2: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', + 3: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', + 4: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', + 5: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', + 6: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', + 7: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', +} +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 1 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 2 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 3 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 4 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 5 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 6 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 7 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT' +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', + 1: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', + 2: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', + 3: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', + 4: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', + 5: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', + 6: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', + 7: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', +} +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 1 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 2 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 3 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 4 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 5 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 6 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 7 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DIG_UPDATE_VCOUNT_MODE' +OTG_DIG_UPDATE_VCOUNT_MODE__enumvalues = { + 0: 'OTG_DIG_UPDATE_VCOUNT_0', + 1: 'OTG_DIG_UPDATE_VCOUNT_1', +} +OTG_DIG_UPDATE_VCOUNT_0 = 0 +OTG_DIG_UPDATE_VCOUNT_1 = 1 +OTG_DIG_UPDATE_VCOUNT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE' +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE__enumvalues = { + 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', + 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', + 2: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', + 3: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', +} +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 1 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 2 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 3 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY' +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY__enumvalues = { + 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', + 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', +} +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0 +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 1 +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME' +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME__enumvalues = { + 0: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', + 1: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', + 2: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', + 3: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', +} +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 1 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 2 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 3 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN' +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN__enumvalues = { + 0: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', + 1: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', +} +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0 +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 1 +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 2: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 3: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 4: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', + 5: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 6: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 7: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 8: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 9: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 10: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 11: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 12: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 13: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 14: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 15: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', + 16: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', + 17: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', + 18: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', + 19: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 2 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 3 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 4 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 5 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 6 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 7 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 8 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 9 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 10 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 11 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 12 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 13 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 14 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 15 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 16 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 17 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 18 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 19 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', + 2: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 3: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 3 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL' +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL__enumvalues = { + 0: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', + 1: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', + 2: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', + 3: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', + 4: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', + 5: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', +} +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 1 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 2 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 3 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 4 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 5 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL' +OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL__enumvalues = { + 0: 'DIG_UPDATE_EYE_SEL_BOTH', + 1: 'DIG_UPDATE_EYE_SEL_LEFT', + 2: 'DIG_UPDATE_EYE_SEL_RIGHT', +} +DIG_UPDATE_EYE_SEL_BOTH = 0 +DIG_UPDATE_EYE_SEL_LEFT = 1 +DIG_UPDATE_EYE_SEL_RIGHT = 2 +OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL' +OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL__enumvalues = { + 0: 'DIG_UPDATE_FIELD_SEL_BOTH', + 1: 'DIG_UPDATE_FIELD_SEL_TOP', + 2: 'DIG_UPDATE_FIELD_SEL_BOTTOM', + 3: 'DIG_UPDATE_FIELD_SEL_RESERVED', +} +DIG_UPDATE_FIELD_SEL_BOTH = 0 +DIG_UPDATE_FIELD_SEL_TOP = 1 +DIG_UPDATE_FIELD_SEL_BOTTOM = 2 +DIG_UPDATE_FIELD_SEL_RESERVED = 3 +OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD' +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', + 1: 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', + 2: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', + 3: 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', +} +MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0 +MASTER_UPDATE_LOCK_DB_FIELD_TOP = 1 +MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 2 +MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 3 +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL' +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', + 1: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', + 2: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', + 3: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', +} +MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 1 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 2 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 3 +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_UPDATE_LOCK_EN' +OTG_GLOBAL_UPDATE_LOCK_EN__enumvalues = { + 0: 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', + 1: 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', +} +OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0 +OTG_GLOBAL_UPDATE_LOCK_ENABLE = 1 +OTG_GLOBAL_UPDATE_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GSL_MASTER_MODE' +OTG_GSL_MASTER_MODE__enumvalues = { + 0: 'OTG_GSL_MASTER_MODE_0', + 1: 'OTG_GSL_MASTER_MODE_1', + 2: 'OTG_GSL_MASTER_MODE_2', + 3: 'OTG_GSL_MASTER_MODE_3', +} +OTG_GSL_MASTER_MODE_0 = 0 +OTG_GSL_MASTER_MODE_1 = 1 +OTG_GSL_MASTER_MODE_2 = 2 +OTG_GSL_MASTER_MODE_3 = 3 +OTG_GSL_MASTER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_HORZ_REPETITION_COUNT' +OTG_HORZ_REPETITION_COUNT__enumvalues = { + 0: 'OTG_HORZ_REPETITION_COUNT_0', + 1: 'OTG_HORZ_REPETITION_COUNT_1', + 2: 'OTG_HORZ_REPETITION_COUNT_2', + 3: 'OTG_HORZ_REPETITION_COUNT_3', + 4: 'OTG_HORZ_REPETITION_COUNT_4', + 5: 'OTG_HORZ_REPETITION_COUNT_5', + 6: 'OTG_HORZ_REPETITION_COUNT_6', + 7: 'OTG_HORZ_REPETITION_COUNT_7', + 8: 'OTG_HORZ_REPETITION_COUNT_8', + 9: 'OTG_HORZ_REPETITION_COUNT_9', + 10: 'OTG_HORZ_REPETITION_COUNT_10', + 11: 'OTG_HORZ_REPETITION_COUNT_11', + 12: 'OTG_HORZ_REPETITION_COUNT_12', + 13: 'OTG_HORZ_REPETITION_COUNT_13', + 14: 'OTG_HORZ_REPETITION_COUNT_14', + 15: 'OTG_HORZ_REPETITION_COUNT_15', +} +OTG_HORZ_REPETITION_COUNT_0 = 0 +OTG_HORZ_REPETITION_COUNT_1 = 1 +OTG_HORZ_REPETITION_COUNT_2 = 2 +OTG_HORZ_REPETITION_COUNT_3 = 3 +OTG_HORZ_REPETITION_COUNT_4 = 4 +OTG_HORZ_REPETITION_COUNT_5 = 5 +OTG_HORZ_REPETITION_COUNT_6 = 6 +OTG_HORZ_REPETITION_COUNT_7 = 7 +OTG_HORZ_REPETITION_COUNT_8 = 8 +OTG_HORZ_REPETITION_COUNT_9 = 9 +OTG_HORZ_REPETITION_COUNT_10 = 10 +OTG_HORZ_REPETITION_COUNT_11 = 11 +OTG_HORZ_REPETITION_COUNT_12 = 12 +OTG_HORZ_REPETITION_COUNT_13 = 13 +OTG_HORZ_REPETITION_COUNT_14 = 14 +OTG_HORZ_REPETITION_COUNT_15 = 15 +OTG_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_SYNC_A_POL' +OTG_H_SYNC_A_POL__enumvalues = { + 0: 'OTG_H_SYNC_A_POL_HIGH', + 1: 'OTG_H_SYNC_A_POL_LOW', +} +OTG_H_SYNC_A_POL_HIGH = 0 +OTG_H_SYNC_A_POL_LOW = 1 +OTG_H_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_TIMING_DIV_MODE' +OTG_H_TIMING_DIV_MODE__enumvalues = { + 0: 'OTG_H_TIMING_DIV_MODE_NO_DIV', + 1: 'OTG_H_TIMING_DIV_MODE_DIV_BY2', + 2: 'OTG_H_TIMING_DIV_MODE_RESERVED', + 3: 'OTG_H_TIMING_DIV_MODE_DIV_BY4', +} +OTG_H_TIMING_DIV_MODE_NO_DIV = 0 +OTG_H_TIMING_DIV_MODE_DIV_BY2 = 1 +OTG_H_TIMING_DIV_MODE_RESERVED = 2 +OTG_H_TIMING_DIV_MODE_DIV_BY4 = 3 +OTG_H_TIMING_DIV_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_TIMING_DIV_MODE_MANUAL' +OTG_H_TIMING_DIV_MODE_MANUAL__enumvalues = { + 0: 'OTG_H_TIMING_DIV_MODE_AUTO', + 1: 'OTG_H_TIMING_DIV_MODE_NOAUTO', +} +OTG_H_TIMING_DIV_MODE_AUTO = 0 +OTG_H_TIMING_DIV_MODE_NOAUTO = 1 +OTG_H_TIMING_DIV_MODE_MANUAL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE' +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE__enumvalues = { + 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', + 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', +} +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 1 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD' +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { + 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', + 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', + 2: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', + 3: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', +} +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 1 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 2 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE' +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { + 0: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 1: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', +} +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_DB_EN' +OTG_MASTER_UPDATE_LOCK_DB_EN__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_DISABLE', + 1: 'OTG_MASTER_UPDATE_LOCK_ENABLE', +} +OTG_MASTER_UPDATE_LOCK_DISABLE = 0 +OTG_MASTER_UPDATE_LOCK_ENABLE = 1 +OTG_MASTER_UPDATE_LOCK_DB_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_GSL_EN' +OTG_MASTER_UPDATE_LOCK_GSL_EN__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', + 1: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', +} +OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0 +OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 1 +OTG_MASTER_UPDATE_LOCK_GSL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE' +OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', + 1: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', +} +OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0 +OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 1 +OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL' +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { + 0: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 1: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 2: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 3: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', +} +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR' +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR__enumvalues = { + 0: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', + 1: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', +} +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0 +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 1 +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE' +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE' +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', +} +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL' +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', +} +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0 +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 1 +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EN' +OTG_STEREO_CONTROL_OTG_STEREO_EN__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY' +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY' +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE' +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE__enumvalues = { + 0: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', + 1: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', + 2: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', + 3: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', +} +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 1 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 2 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 3 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR' +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', +} +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', + 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', + 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', +} +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 6 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 7 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN' +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', +} +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', +} +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', + 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', + 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', + 8: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', + 9: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', + 10: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', + 11: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', + 12: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', + 13: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', + 14: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', + 15: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', + 16: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', + 17: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', + 18: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', + 19: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', + 20: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', + 21: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 22: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 23: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', + 24: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', +} +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 6 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 7 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 8 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 9 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 11 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 12 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 13 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 14 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 15 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 17 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 18 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 19 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 20 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 23 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 24 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL' +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_FREQUENCY_SELECT' +OTG_TRIGA_FREQUENCY_SELECT__enumvalues = { + 0: 'OTG_TRIGA_FREQUENCY_SELECT_0', + 1: 'OTG_TRIGA_FREQUENCY_SELECT_1', + 2: 'OTG_TRIGA_FREQUENCY_SELECT_2', + 3: 'OTG_TRIGA_FREQUENCY_SELECT_3', +} +OTG_TRIGA_FREQUENCY_SELECT_0 = 0 +OTG_TRIGA_FREQUENCY_SELECT_1 = 1 +OTG_TRIGA_FREQUENCY_SELECT_2 = 2 +OTG_TRIGA_FREQUENCY_SELECT_3 = 3 +OTG_TRIGA_FREQUENCY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL' +OTG_TRIGA_RISING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR' +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', +} +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', + 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', + 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', +} +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 6 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 7 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN' +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', +} +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', +} +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', + 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', + 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', + 8: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', + 9: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', + 10: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', + 11: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', + 12: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', + 13: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', + 14: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', + 15: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', + 16: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', + 17: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', + 18: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', + 19: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', + 20: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', + 21: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 22: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 23: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', + 24: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', +} +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 6 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 7 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 8 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 9 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 11 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 12 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 13 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 14 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 15 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 17 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 18 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 19 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 20 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 23 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 24 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL' +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_FREQUENCY_SELECT' +OTG_TRIGB_FREQUENCY_SELECT__enumvalues = { + 0: 'OTG_TRIGB_FREQUENCY_SELECT_0', + 1: 'OTG_TRIGB_FREQUENCY_SELECT_1', + 2: 'OTG_TRIGB_FREQUENCY_SELECT_2', + 3: 'OTG_TRIGB_FREQUENCY_SELECT_3', +} +OTG_TRIGB_FREQUENCY_SELECT_0 = 0 +OTG_TRIGB_FREQUENCY_SELECT_1 = 1 +OTG_TRIGB_FREQUENCY_SELECT_2 = 2 +OTG_TRIGB_FREQUENCY_SELECT_3 = 3 +OTG_TRIGB_FREQUENCY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL' +OTG_TRIGB_RISING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK' +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK__enumvalues = { + 0: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', + 1: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', +} +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0 +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 1 +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE' +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE__enumvalues = { + 0: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', + 1: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 2: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 3: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', +} +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR' +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { + 0: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 1: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', +} +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR' +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR__enumvalues = { + 0: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', + 1: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', +} +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0 +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 1 +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VUPDATE_BLOCK_DISABLE' +OTG_VUPDATE_BLOCK_DISABLE__enumvalues = { + 0: 'OTG_VUPDATE_BLOCK_DISABLE_OFF', + 1: 'OTG_VUPDATE_BLOCK_DISABLE_ON', +} +OTG_VUPDATE_BLOCK_DISABLE_OFF = 0 +OTG_VUPDATE_BLOCK_DISABLE_ON = 1 +OTG_VUPDATE_BLOCK_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_SYNC_A_POL' +OTG_V_SYNC_A_POL__enumvalues = { + 0: 'OTG_V_SYNC_A_POL_HIGH', + 1: 'OTG_V_SYNC_A_POL_LOW', +} +OTG_V_SYNC_A_POL_HIGH = 0 +OTG_V_SYNC_A_POL_LOW = 1 +OTG_V_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_SYNC_MODE' +OTG_V_SYNC_MODE__enumvalues = { + 0: 'OTG_V_SYNC_MODE_HSYNC', + 1: 'OTG_V_SYNC_MODE_HBLANK', +} +OTG_V_SYNC_MODE_HSYNC = 0 +OTG_V_SYNC_MODE_HBLANK = 1 +OTG_V_SYNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD' +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', + 1: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', +} +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0 +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 1 +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT' +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', +} +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 1 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC' +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', +} +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL' +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', +} +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 1 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL' +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', +} +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 1 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK' +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__enumvalues = { + 0: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', + 1: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', +} +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0 +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 1 +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL' +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL__enumvalues = { + 0: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', + 1: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', + 2: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', + 3: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', + 4: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', + 5: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', +} +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 1 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 2 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 3 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 4 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 5 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DC_DMCUB_INT_TYPE' +DC_DMCUB_INT_TYPE__enumvalues = { + 0: 'INT_LEVEL', + 1: 'INT_PULSE', +} +INT_LEVEL = 0 +INT_PULSE = 1 +DC_DMCUB_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DC_DMCUB_TIMER_WINDOW' +DC_DMCUB_TIMER_WINDOW__enumvalues = { + 0: 'BITS_31_0', + 1: 'BITS_32_1', + 2: 'BITS_33_2', + 3: 'BITS_34_3', + 4: 'BITS_35_4', + 5: 'BITS_36_5', + 6: 'BITS_37_6', + 7: 'BITS_38_7', +} +BITS_31_0 = 0 +BITS_32_1 = 1 +BITS_33_2 = 2 +BITS_34_3 = 3 +BITS_35_4 = 4 +BITS_36_5 = 5 +BITS_37_6 = 6 +BITS_38_7 = 7 +DC_DMCUB_TIMER_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'INVALID_REG_ACCESS_TYPE' +INVALID_REG_ACCESS_TYPE__enumvalues = { + 0: 'REG_UNALLOCATED_ADDR_WRITE', + 1: 'REG_UNALLOCATED_ADDR_READ', + 2: 'REG_VIRTUAL_WRITE', + 3: 'REG_VIRTUAL_READ', + 4: 'REG_SECURE_VIOLATE_WRITE', + 5: 'REG_SECURE_VIOLATE_READ', +} +REG_UNALLOCATED_ADDR_WRITE = 0 +REG_UNALLOCATED_ADDR_READ = 1 +REG_VIRTUAL_WRITE = 2 +REG_VIRTUAL_READ = 3 +REG_SECURE_VIOLATE_WRITE = 4 +REG_SECURE_VIOLATE_READ = 5 +INVALID_REG_ACCESS_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_DC_GPU_TIMER_READ_SELECT' +DMU_DC_GPU_TIMER_READ_SELECT__enumvalues = { + 0: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', + 1: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', + 2: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', + 3: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', + 4: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', + 5: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', + 6: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', + 7: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', + 8: 'RESERVED_8', + 9: 'RESERVED_9', + 10: 'RESERVED_10', + 11: 'RESERVED_11', + 12: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', + 13: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', + 14: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', + 15: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', + 16: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', + 17: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', + 18: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', + 19: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', + 20: 'RESERVED_20', + 21: 'RESERVED_21', + 22: 'RESERVED_22', + 23: 'RESERVED_23', + 24: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', + 25: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', + 26: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', + 27: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', + 28: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', + 29: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', + 30: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', + 31: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', + 32: 'RESERVED_32', + 33: 'RESERVED_33', + 34: 'RESERVED_34', + 35: 'RESERVED_35', + 36: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', + 37: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', + 38: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', + 39: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', + 40: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', + 41: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', + 42: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', + 43: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', + 44: 'RESERVED_44', + 45: 'RESERVED_45', + 46: 'RESERVED_46', + 47: 'RESERVED_47', + 48: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', + 49: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', + 50: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', + 51: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', + 52: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', + 53: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', + 54: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', + 55: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', + 56: 'RESERVED_56', + 57: 'RESERVED_57', + 58: 'RESERVED_58', + 59: 'RESERVED_59', + 60: 'RESERVED_60', + 61: 'RESERVED_61', + 62: 'RESERVED_62', + 63: 'RESERVED_63', + 64: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', + 65: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', + 66: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', + 67: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', + 68: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', + 69: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', + 70: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', + 71: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', + 72: 'RESERVED_72', + 73: 'RESERVED_73', + 74: 'RESERVED_74', + 75: 'RESERVED_75', + 76: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', + 77: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', + 78: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', + 79: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', + 80: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', + 81: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', + 82: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', + 83: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', + 84: 'RESERVED_84', + 85: 'RESERVED_85', + 86: 'RESERVED_86', + 87: 'RESERVED_87', + 88: 'RESERVED_88', + 89: 'RESERVED_89', + 90: 'RESERVED_90', + 91: 'RESERVED_91', +} +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 1 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 2 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 3 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 4 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 5 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 6 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 7 +RESERVED_8 = 8 +RESERVED_9 = 9 +RESERVED_10 = 10 +RESERVED_11 = 11 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 12 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 13 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 14 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 15 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 16 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 17 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 18 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 19 +RESERVED_20 = 20 +RESERVED_21 = 21 +RESERVED_22 = 22 +RESERVED_23 = 23 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 24 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 25 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 26 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 27 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 28 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 29 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 30 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 31 +RESERVED_32 = 32 +RESERVED_33 = 33 +RESERVED_34 = 34 +RESERVED_35 = 35 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 36 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 37 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 38 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 39 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 40 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 41 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 42 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 43 +RESERVED_44 = 44 +RESERVED_45 = 45 +RESERVED_46 = 46 +RESERVED_47 = 47 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 48 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 49 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 50 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 51 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 52 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 53 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 54 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 55 +RESERVED_56 = 56 +RESERVED_57 = 57 +RESERVED_58 = 58 +RESERVED_59 = 59 +RESERVED_60 = 60 +RESERVED_61 = 61 +RESERVED_62 = 62 +RESERVED_63 = 63 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 64 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 65 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 66 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 67 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 68 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 69 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 70 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 71 +RESERVED_72 = 72 +RESERVED_73 = 73 +RESERVED_74 = 74 +RESERVED_75 = 75 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 76 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 77 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 78 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 79 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 80 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 81 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 82 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 83 +RESERVED_84 = 84 +RESERVED_85 = 85 +RESERVED_86 = 86 +RESERVED_87 = 87 +RESERVED_88 = 88 +RESERVED_89 = 89 +RESERVED_90 = 90 +RESERVED_91 = 91 +DMU_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_DC_GPU_TIMER_START_POSITION' +DMU_DC_GPU_TIMER_START_POSITION__enumvalues = { + 0: 'DMU_GPU_TIMER_START_0_END_27', + 1: 'DMU_GPU_TIMER_START_1_END_28', + 2: 'DMU_GPU_TIMER_START_2_END_29', + 3: 'DMU_GPU_TIMER_START_3_END_30', + 4: 'DMU_GPU_TIMER_START_4_END_31', + 5: 'DMU_GPU_TIMER_START_6_END_33', + 6: 'DMU_GPU_TIMER_START_8_END_35', + 7: 'DMU_GPU_TIMER_START_10_END_37', +} +DMU_GPU_TIMER_START_0_END_27 = 0 +DMU_GPU_TIMER_START_1_END_28 = 1 +DMU_GPU_TIMER_START_2_END_29 = 2 +DMU_GPU_TIMER_START_3_END_30 = 3 +DMU_GPU_TIMER_START_4_END_31 = 4 +DMU_GPU_TIMER_START_6_END_33 = 5 +DMU_GPU_TIMER_START_8_END_35 = 6 +DMU_GPU_TIMER_START_10_END_37 = 7 +DMU_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'IHC_INTERRUPT_DEST' +IHC_INTERRUPT_DEST__enumvalues = { + 0: 'INTERRUPT_SENT_TO_IH', + 1: 'INTERRUPT_SENT_TO_DMCUB', +} +INTERRUPT_SENT_TO_IH = 0 +INTERRUPT_SENT_TO_DMCUB = 1 +IHC_INTERRUPT_DEST = ctypes.c_uint32 # enum + +# values for enumeration 'IHC_INTERRUPT_LINE_STATUS' +IHC_INTERRUPT_LINE_STATUS__enumvalues = { + 0: 'INTERRUPT_LINE_NOT_ASSERTED', + 1: 'INTERRUPT_LINE_ASSERTED', +} +INTERRUPT_LINE_NOT_ASSERTED = 0 +INTERRUPT_LINE_ASSERTED = 1 +IHC_INTERRUPT_LINE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DC_SMU_INTERRUPT_ENABLE' +DC_SMU_INTERRUPT_ENABLE__enumvalues = { + 0: 'DISABLE_THE_INTERRUPT', + 1: 'ENABLE_THE_INTERRUPT', +} +DISABLE_THE_INTERRUPT = 0 +ENABLE_THE_INTERRUPT = 1 +DC_SMU_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_CLOCK_ON' +DMU_CLOCK_ON__enumvalues = { + 0: 'DMU_CLOCK_STATUS_ON', + 1: 'DMU_CLOCK_STATUS_OFF', +} +DMU_CLOCK_STATUS_ON = 0 +DMU_CLOCK_STATUS_OFF = 1 +DMU_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'SMU_INTR' +SMU_INTR__enumvalues = { + 0: 'SMU_MSG_INTR_NOOP', + 1: 'SET_SMU_MSG_INTR', +} +SMU_MSG_INTR_NOOP = 0 +SET_SMU_MSG_INTR = 1 +SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'ALLOW_SR_ON_TRANS_REQ' +ALLOW_SR_ON_TRANS_REQ__enumvalues = { + 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', + 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', +} +ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 +ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 +ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'AMCLOCK_ENABLE' +AMCLOCK_ENABLE__enumvalues = { + 0: 'ENABLE_AMCLK0', + 1: 'ENABLE_AMCLK1', +} +ENABLE_AMCLK0 = 0 +ENABLE_AMCLK1 = 1 +AMCLOCK_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CLEAR_SMU_INTR' +CLEAR_SMU_INTR__enumvalues = { + 0: 'SMU_INTR_STATUS_NOOP', + 1: 'SMU_INTR_STATUS_CLEAR', +} +SMU_INTR_STATUS_NOOP = 0 +SMU_INTR_STATUS_CLEAR = 1 +CLEAR_SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_BRANCH_SOFT_RESET' +CLOCK_BRANCH_SOFT_RESET__enumvalues = { + 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', + 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', +} +CLOCK_BRANCH_SOFT_RESET_NOOP = 0 +CLOCK_BRANCH_SOFT_RESET_FORCE = 1 +CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' +DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', + 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', + 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', + 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', + 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', +} +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 1 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 2 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 3 +DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 4 +DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' +DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', +} +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 1 +DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_SEL' +DCCG_AUDIO_DTO_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', + 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', + 3: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK', +} +DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 +DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 +DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 +DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK = 3 +DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' +DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { + 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', +} +DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 +DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 +DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DBG_BLOCK_SEL' +DCCG_DBG_BLOCK_SEL__enumvalues = { + 0: 'DCCG_DBG_BLOCK_SEL_DCCG', + 1: 'DCCG_DBG_BLOCK_SEL_PMON', + 2: 'DCCG_DBG_BLOCK_SEL_PMON2', +} +DCCG_DBG_BLOCK_SEL_DCCG = 0 +DCCG_DBG_BLOCK_SEL_PMON = 1 +DCCG_DBG_BLOCK_SEL_PMON2 = 2 +DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DBG_EN' +DCCG_DBG_EN__enumvalues = { + 0: 'DCCG_DBG_EN_DISABLE', + 1: 'DCCG_DBG_EN_ENABLE', +} +DCCG_DBG_EN_DISABLE = 0 +DCCG_DBG_EN_ENABLE = 1 +DCCG_DBG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DEEP_COLOR_CNTL' +DCCG_DEEP_COLOR_CNTL__enumvalues = { + 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', + 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', + 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', +} +DCCG_DEEP_COLOR_DTO_DISABLE = 0 +DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 +DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 +DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 +DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' +DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', + 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', +} +DCCG_FIFO_ERRDET_OVR_DISABLE = 0 +DCCG_FIFO_ERRDET_OVR_ENABLE = 1 +DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_RESET' +DCCG_FIFO_ERRDET_RESET__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', + 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', +} +DCCG_FIFO_ERRDET_RESET_NOOP = 0 +DCCG_FIFO_ERRDET_RESET_FORCE = 1 +DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_STATE' +DCCG_FIFO_ERRDET_STATE__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', + 1: 'DCCG_FIFO_ERRDET_STATE_DETECTION', +} +DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0 +DCCG_FIFO_ERRDET_STATE_DETECTION = 1 +DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_HSYNC' +DCCG_PERF_MODE_HSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_HSYNC_NOOP', + 1: 'DCCG_PERF_MODE_HSYNC_START', +} +DCCG_PERF_MODE_HSYNC_NOOP = 0 +DCCG_PERF_MODE_HSYNC_START = 1 +DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_VSYNC' +DCCG_PERF_MODE_VSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_VSYNC_NOOP', + 1: 'DCCG_PERF_MODE_VSYNC_START', +} +DCCG_PERF_MODE_VSYNC_NOOP = 0 +DCCG_PERF_MODE_VSYNC_START = 1 +DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_OTG_SELECT' +DCCG_PERF_OTG_SELECT__enumvalues = { + 0: 'DCCG_PERF_SEL_OTG0', + 1: 'DCCG_PERF_SEL_OTG1', + 2: 'DCCG_PERF_SEL_OTG2', + 3: 'DCCG_PERF_SEL_OTG3', + 4: 'DCCG_PERF_SEL_RESERVED', +} +DCCG_PERF_SEL_OTG0 = 0 +DCCG_PERF_SEL_OTG1 = 1 +DCCG_PERF_SEL_OTG2 = 2 +DCCG_PERF_SEL_OTG3 = 3 +DCCG_PERF_SEL_RESERVED = 4 +DCCG_PERF_OTG_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_RUN' +DCCG_PERF_RUN__enumvalues = { + 0: 'DCCG_PERF_RUN_NOOP', + 1: 'DCCG_PERF_RUN_START', +} +DCCG_PERF_RUN_NOOP = 0 +DCCG_PERF_RUN_START = 1 +DCCG_PERF_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' +DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { + 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', +} +DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 +DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 +DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_FIFO_ERROR' +DIO_FIFO_ERROR__enumvalues = { + 0: 'DIO_FIFO_ERROR_00', + 1: 'DIO_FIFO_ERROR_01', + 2: 'DIO_FIFO_ERROR_10', + 3: 'DIO_FIFO_ERROR_11', +} +DIO_FIFO_ERROR_00 = 0 +DIO_FIFO_ERROR_01 = 1 +DIO_FIFO_ERROR_10 = 2 +DIO_FIFO_ERROR_11 = 3 +DIO_FIFO_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING' +DISABLE_CLOCK_GATING__enumvalues = { + 0: 'CLOCK_GATING_ENABLED', + 1: 'CLOCK_GATING_DISABLED', +} +CLOCK_GATING_ENABLED = 0 +CLOCK_GATING_DISABLED = 1 +DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' +DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { + 0: 'CLOCK_GATING_ENABLED_IN_DCO', + 1: 'CLOCK_GATING_DISABLED_IN_DCO', +} +CLOCK_GATING_ENABLED_IN_DCO = 0 +CLOCK_GATING_DISABLED_IN_DCO = 1 +DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' +DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { + 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', +} +DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 +DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 +DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_FREQ_RAMP_DONE' +DISPCLK_FREQ_RAMP_DONE__enumvalues = { + 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', + 1: 'DISPCLK_FREQ_RAMP_COMPLETED', +} +DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 +DISPCLK_FREQ_RAMP_COMPLETED = 1 +DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DPREFCLK_SRC_SEL' +DPREFCLK_SRC_SEL__enumvalues = { + 0: 'DPREFCLK_SRC_SEL_CK', + 1: 'DPREFCLK_SRC_SEL_P0PLL', + 2: 'DPREFCLK_SRC_SEL_P1PLL', + 3: 'DPREFCLK_SRC_SEL_P2PLL', +} +DPREFCLK_SRC_SEL_CK = 0 +DPREFCLK_SRC_SEL_P0PLL = 1 +DPREFCLK_SRC_SEL_P1PLL = 2 +DPREFCLK_SRC_SEL_P2PLL = 3 +DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DTO_DS_DISABLE' +DP_DTO_DS_DISABLE__enumvalues = { + 0: 'DP_DTO_DESPREAD_DISABLE', + 1: 'DP_DTO_DESPREAD_ENABLE', +} +DP_DTO_DESPREAD_DISABLE = 0 +DP_DTO_DESPREAD_ENABLE = 1 +DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DS_HW_CAL_ENABLE' +DS_HW_CAL_ENABLE__enumvalues = { + 0: 'DS_HW_CAL_DIS', + 1: 'DS_HW_CAL_EN', +} +DS_HW_CAL_DIS = 0 +DS_HW_CAL_EN = 1 +DS_HW_CAL_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DS_JITTER_COUNT_SRC_SEL' +DS_JITTER_COUNT_SRC_SEL__enumvalues = { + 0: 'DS_JITTER_COUNT_SRC_SEL0', + 1: 'DS_JITTER_COUNT_SRC_SEL1', +} +DS_JITTER_COUNT_SRC_SEL0 = 0 +DS_JITTER_COUNT_SRC_SEL1 = 1 +DS_JITTER_COUNT_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DS_REF_SRC' +DS_REF_SRC__enumvalues = { + 0: 'DS_REF_IS_XTALIN', + 1: 'DS_REF_IS_EXT_GENLOCK', + 2: 'DS_REF_IS_PCIE', +} +DS_REF_IS_XTALIN = 0 +DS_REF_IS_EXT_GENLOCK = 1 +DS_REF_IS_PCIE = 2 +DS_REF_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_IN_PHASE' +DVOACLKC_IN_PHASE__enumvalues = { + 0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_MVP_IN_PHASE' +DVOACLKC_MVP_IN_PHASE__enumvalues = { + 0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE' +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = { + 0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', + 1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', +} +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0 +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1 +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKD_IN_PHASE' +DVOACLKD_IN_PHASE__enumvalues = { + 0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLK_COARSE_SKEW_CNTL' +DVOACLK_COARSE_SKEW_CNTL__enumvalues = { + 0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', + 1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', + 2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', + 3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', + 4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', + 5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', + 6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', + 7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', + 8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', + 9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', + 10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', + 11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', + 12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', + 13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', + 14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', + 15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', + 16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', + 17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', + 18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', + 19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', + 20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', + 21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', + 22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', + 23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', + 24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', + 25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', + 26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', + 27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', + 28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', + 29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', + 30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', +} +DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0 +DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1 +DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2 +DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3 +DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4 +DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5 +DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6 +DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7 +DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8 +DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9 +DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10 +DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11 +DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12 +DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13 +DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14 +DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15 +DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16 +DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17 +DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18 +DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19 +DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20 +DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21 +DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22 +DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23 +DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24 +DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25 +DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26 +DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27 +DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28 +DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29 +DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30 +DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLK_FINE_SKEW_CNTL' +DVOACLK_FINE_SKEW_CNTL__enumvalues = { + 0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', + 1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', + 2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', + 3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', + 4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', + 5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', + 6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', + 7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', +} +DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0 +DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1 +DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2 +DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3 +DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4 +DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5 +DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6 +DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7 +DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DVO_ENABLE_RST' +DVO_ENABLE_RST__enumvalues = { + 0: 'DVO_ENABLE_RST_DISABLE', + 1: 'DVO_ENABLE_RST_ENABLE', +} +DVO_ENABLE_RST_DISABLE = 0 +DVO_ENABLE_RST_ENABLE = 1 +DVO_ENABLE_RST = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE' +ENABLE__enumvalues = { + 0: 'DISABLE_THE_FEATURE', + 1: 'ENABLE_THE_FEATURE', +} +DISABLE_THE_FEATURE = 0 +ENABLE_THE_FEATURE = 1 +ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE_CLOCK' +ENABLE_CLOCK__enumvalues = { + 0: 'ENABLE_THE_REFCLK', + 1: 'ENABLE_THE_FUNC_CLOCK', +} +ENABLE_THE_REFCLK = 0 +ENABLE_THE_FUNC_CLOCK = 1 +ENABLE_CLOCK = ctypes.c_uint32 # enum + +# values for enumeration 'FORCE_DISABLE_CLOCK' +FORCE_DISABLE_CLOCK__enumvalues = { + 0: 'NOT_FORCE_THE_CLOCK_DISABLED', + 1: 'FORCE_THE_CLOCK_DISABLED', +} +NOT_FORCE_THE_CLOCK_DISABLED = 0 +FORCE_THE_CLOCK_DISABLED = 1 +FORCE_DISABLE_CLOCK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMICHARCLK_SRC_SEL' +HDMICHARCLK_SRC_SEL__enumvalues = { + 0: 'HDMICHARCLK_SRC_SEL_UNIPHYA', + 1: 'HDMICHARCLK_SRC_SEL_UNIPHYB', + 2: 'HDMICHARCLK_SRC_SEL_UNIPHYC', + 3: 'HDMICHARCLK_SRC_SEL_UNIPHYD', + 4: 'HDMICHARCLK_SRC_SEL_UNIPHYE', + 5: 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', +} +HDMICHARCLK_SRC_SEL_UNIPHYA = 0 +HDMICHARCLK_SRC_SEL_UNIPHYB = 1 +HDMICHARCLK_SRC_SEL_UNIPHYC = 2 +HDMICHARCLK_SRC_SEL_UNIPHYD = 3 +HDMICHARCLK_SRC_SEL_UNIPHYE = 4 +HDMICHARCLK_SRC_SEL_SRC_RESERVED = 5 +HDMICHARCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMISTREAMCLK_DTO_FORCE_DIS' +HDMISTREAMCLK_DTO_FORCE_DIS__enumvalues = { + 0: 'DTO_FORCE_NO_BYPASS', + 1: 'DTO_FORCE_BYPASS', +} +DTO_FORCE_NO_BYPASS = 0 +DTO_FORCE_BYPASS = 1 +HDMISTREAMCLK_DTO_FORCE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'HDMISTREAMCLK_SRC_SEL' +HDMISTREAMCLK_SRC_SEL__enumvalues = { + 0: 'SEL_REFCLK0', + 1: 'SEL_DTBCLK0', + 2: 'SEL_DTBCLK1', +} +SEL_REFCLK0 = 0 +SEL_DTBCLK0 = 1 +SEL_DTBCLK1 = 2 +HDMISTREAMCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'JITTER_REMOVE_DISABLE' +JITTER_REMOVE_DISABLE__enumvalues = { + 0: 'ENABLE_JITTER_REMOVAL', + 1: 'DISABLE_JITTER_REMOVAL', +} +ENABLE_JITTER_REMOVAL = 0 +DISABLE_JITTER_REMOVAL = 1 +JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', +} +MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', +} +MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_ADD_PIXEL' +OTG_ADD_PIXEL__enumvalues = { + 0: 'OTG_ADD_PIXEL_NOOP', + 1: 'OTG_ADD_PIXEL_FORCE', +} +OTG_ADD_PIXEL_NOOP = 0 +OTG_ADD_PIXEL_FORCE = 1 +OTG_ADD_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DROP_PIXEL' +OTG_DROP_PIXEL__enumvalues = { + 0: 'OTG_DROP_PIXEL_NOOP', + 1: 'OTG_DROP_PIXEL_FORCE', +} +OTG_DROP_PIXEL_NOOP = 0 +OTG_DROP_PIXEL_FORCE = 1 +OTG_DROP_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'PHYSYMCLK_FORCE_EN' +PHYSYMCLK_FORCE_EN__enumvalues = { + 0: 'PHYSYMCLK_FORCE_EN_DISABLE', + 1: 'PHYSYMCLK_FORCE_EN_ENABLE', +} +PHYSYMCLK_FORCE_EN_DISABLE = 0 +PHYSYMCLK_FORCE_EN_ENABLE = 1 +PHYSYMCLK_FORCE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PHYSYMCLK_FORCE_SRC_SEL' +PHYSYMCLK_FORCE_SRC_SEL__enumvalues = { + 0: 'PHYSYMCLK_FORCE_SRC_SYMCLK', + 1: 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', + 2: 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', +} +PHYSYMCLK_FORCE_SRC_SYMCLK = 0 +PHYSYMCLK_FORCE_SRC_PHYD18CLK = 1 +PHYSYMCLK_FORCE_SRC_PHYD32CLK = 2 +PHYSYMCLK_FORCE_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' +PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', +} +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 4 +PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' +PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', + 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', +} +PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 +PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 +PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_SOURCE' +PIPE_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', + 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', +} +PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 +PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 +PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 +PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PLL_CFG_IF_SOFT_RESET' +PLL_CFG_IF_SOFT_RESET__enumvalues = { + 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', + 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', +} +PLL_CFG_IF_SOFT_RESET_NOOP = 0 +PLL_CFG_IF_SOFT_RESET_FORCE = 1 +PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_FORCE_EN' +SYMCLK_FE_FORCE_EN__enumvalues = { + 0: 'SYMCLK_FE_FORCE_EN_DISABLE', + 1: 'SYMCLK_FE_FORCE_EN_ENABLE', +} +SYMCLK_FE_FORCE_EN_DISABLE = 0 +SYMCLK_FE_FORCE_EN_ENABLE = 1 +SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_FORCE_SRC' +SYMCLK_FE_FORCE_SRC__enumvalues = { + 0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA', + 1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB', + 2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC', + 3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD', + 4: 'SYMCLK_FE_FORCE_SRC_RESERVED', +} +SYMCLK_FE_FORCE_SRC_UNIPHYA = 0 +SYMCLK_FE_FORCE_SRC_UNIPHYB = 1 +SYMCLK_FE_FORCE_SRC_UNIPHYC = 2 +SYMCLK_FE_FORCE_SRC_UNIPHYD = 3 +SYMCLK_FE_FORCE_SRC_RESERVED = 4 +SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLK_DIV_SEL' +TEST_CLK_DIV_SEL__enumvalues = { + 0: 'NO_DIV', + 1: 'DIV_2', + 2: 'DIV_4', + 3: 'DIV_8', +} +NO_DIV = 0 +DIV_2 = 1 +DIV_4 = 2 +DIV_8 = 3 +TEST_CLK_DIV_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VSYNC_CNT_LATCH_MASK' +VSYNC_CNT_LATCH_MASK__enumvalues = { + 0: 'VSYNC_CNT_LATCH_MASK_0', + 1: 'VSYNC_CNT_LATCH_MASK_1', +} +VSYNC_CNT_LATCH_MASK_0 = 0 +VSYNC_CNT_LATCH_MASK_1 = 1 +VSYNC_CNT_LATCH_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'VSYNC_CNT_RESET_SEL' +VSYNC_CNT_RESET_SEL__enumvalues = { + 0: 'VSYNC_CNT_RESET_SEL_0', + 1: 'VSYNC_CNT_RESET_SEL_1', +} +VSYNC_CNT_RESET_SEL_0 = 0 +VSYNC_CNT_RESET_SEL_1 = 1 +VSYNC_CNT_RESET_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' +XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', + 1: 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', +} +XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 +XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 1 +XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_SEL' +XTAL_REF_SEL__enumvalues = { + 0: 'XTAL_REF_SEL_1X', + 1: 'XTAL_REF_SEL_2X', +} +XTAL_REF_SEL_1X = 0 +XTAL_REF_SEL_2X = 1 +XTAL_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_ACK' +HPD_INT_CONTROL_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_ACK_0', + 1: 'HPD_INT_CONTROL_ACK_1', +} +HPD_INT_CONTROL_ACK_0 = 0 +HPD_INT_CONTROL_ACK_1 = 1 +HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_POLARITY' +HPD_INT_CONTROL_POLARITY__enumvalues = { + 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', + 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', +} +HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 +HPD_INT_CONTROL_GEN_INT_ON_CON = 1 +HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' +HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', + 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', +} +HPD_INT_CONTROL_RX_INT_ACK_0 = 0 +HPD_INT_CONTROL_RX_INT_ACK_1 = 1 +HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_CUR_DISP' +DPHY_8B10B_CUR_DISP__enumvalues = { + 0: 'DPHY_8B10B_CUR_DISP_ZERO', + 1: 'DPHY_8B10B_CUR_DISP_ONE', +} +DPHY_8B10B_CUR_DISP_ZERO = 0 +DPHY_8B10B_CUR_DISP_ONE = 1 +DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_RESET' +DPHY_8B10B_RESET__enumvalues = { + 0: 'DPHY_8B10B_NOT_RESET', + 1: 'DPHY_8B10B_RESETET', +} +DPHY_8B10B_NOT_RESET = 0 +DPHY_8B10B_RESETET = 1 +DPHY_8B10B_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_EN' +DPHY_ALT_SCRAMBLER_RESET_EN__enumvalues = { + 0: 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', + 1: 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', +} +DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0 +DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 1 +DPHY_ALT_SCRAMBLER_RESET_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_SEL' +DPHY_ALT_SCRAMBLER_RESET_SEL__enumvalues = { + 0: 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', + 1: 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', +} +DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0 +DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 1 +DPHY_ALT_SCRAMBLER_RESET_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE0' +DPHY_ATEST_SEL_LANE0__enumvalues = { + 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE0_REG_PATTERN', +} +DPHY_ATEST_LANE0_PRBS_PATTERN = 0 +DPHY_ATEST_LANE0_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE1' +DPHY_ATEST_SEL_LANE1__enumvalues = { + 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE1_REG_PATTERN', +} +DPHY_ATEST_LANE1_PRBS_PATTERN = 0 +DPHY_ATEST_LANE1_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE2' +DPHY_ATEST_SEL_LANE2__enumvalues = { + 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE2_REG_PATTERN', +} +DPHY_ATEST_LANE2_PRBS_PATTERN = 0 +DPHY_ATEST_LANE2_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE3' +DPHY_ATEST_SEL_LANE3__enumvalues = { + 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE3_REG_PATTERN', +} +DPHY_ATEST_LANE3_PRBS_PATTERN = 0 +DPHY_ATEST_LANE3_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_BYPASS' +DPHY_BYPASS__enumvalues = { + 0: 'DPHY_8B10B_OUTPUT', + 1: 'DPHY_DBG_OUTPUT', +} +DPHY_8B10B_OUTPUT = 0 +DPHY_DBG_OUTPUT = 1 +DPHY_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_CONT_EN' +DPHY_CRC_CONT_EN__enumvalues = { + 0: 'DPHY_CRC_ONE_SHOT', + 1: 'DPHY_CRC_CONTINUOUS', +} +DPHY_CRC_ONE_SHOT = 0 +DPHY_CRC_CONTINUOUS = 1 +DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_EN' +DPHY_CRC_EN__enumvalues = { + 0: 'DPHY_CRC_DISABLED', + 1: 'DPHY_CRC_ENABLED', +} +DPHY_CRC_DISABLED = 0 +DPHY_CRC_ENABLED = 1 +DPHY_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_FIELD' +DPHY_CRC_FIELD__enumvalues = { + 0: 'DPHY_CRC_START_FROM_TOP_FIELD', + 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', +} +DPHY_CRC_START_FROM_TOP_FIELD = 0 +DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 +DPHY_CRC_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' +DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { + 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', + 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', +} +DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 +DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 +DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_SEL' +DPHY_CRC_SEL__enumvalues = { + 0: 'DPHY_CRC_LANE0_SELECTED', + 1: 'DPHY_CRC_LANE1_SELECTED', + 2: 'DPHY_CRC_LANE2_SELECTED', + 3: 'DPHY_CRC_LANE3_SELECTED', +} +DPHY_CRC_LANE0_SELECTED = 0 +DPHY_CRC_LANE1_SELECTED = 1 +DPHY_CRC_LANE2_SELECTED = 2 +DPHY_CRC_LANE3_SELECTED = 3 +DPHY_CRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_FEC_ENABLE' +DPHY_FEC_ENABLE__enumvalues = { + 0: 'DPHY_FEC_DISABLED', + 1: 'DPHY_FEC_ENABLED', +} +DPHY_FEC_DISABLED = 0 +DPHY_FEC_ENABLED = 1 +DPHY_FEC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_FEC_READY' +DPHY_FEC_READY__enumvalues = { + 0: 'DPHY_FEC_READY_EN', + 1: 'DPHY_FEC_READY_DIS', +} +DPHY_FEC_READY_EN = 0 +DPHY_FEC_READY_DIS = 1 +DPHY_FEC_READY = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_LOAD_BS_COUNT_START' +DPHY_LOAD_BS_COUNT_START__enumvalues = { + 0: 'DPHY_LOAD_BS_COUNT_STARTED', + 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', +} +DPHY_LOAD_BS_COUNT_STARTED = 0 +DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 +DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_EN' +DPHY_PRBS_EN__enumvalues = { + 0: 'DPHY_PRBS_DISABLE', + 1: 'DPHY_PRBS_ENABLE', +} +DPHY_PRBS_DISABLE = 0 +DPHY_PRBS_ENABLE = 1 +DPHY_PRBS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_SEL' +DPHY_PRBS_SEL__enumvalues = { + 0: 'DPHY_PRBS7_SELECTED', + 1: 'DPHY_PRBS23_SELECTED', + 2: 'DPHY_PRBS11_SELECTED', +} +DPHY_PRBS7_SELECTED = 0 +DPHY_PRBS23_SELECTED = 1 +DPHY_PRBS11_SELECTED = 2 +DPHY_PRBS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' +DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { + 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 1: 'DPHY_FAST_TRAINING_CAPABLE', +} +DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 +DPHY_FAST_TRAINING_CAPABLE = 1 +DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_ADVANCE' +DPHY_SCRAMBLER_ADVANCE__enumvalues = { + 0: 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', + 1: 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', +} +DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0 +DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 1 +DPHY_SCRAMBLER_ADVANCE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_DIS' +DPHY_SCRAMBLER_DIS__enumvalues = { + 0: 'DPHY_SCR_ENABLED', + 1: 'DPHY_SCR_DISABLED', +} +DPHY_SCR_ENABLED = 0 +DPHY_SCR_DISABLED = 1 +DPHY_SCRAMBLER_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_KCODE' +DPHY_SCRAMBLER_KCODE__enumvalues = { + 0: 'DPHY_SCRAMBLER_KCODE_DISABLED', + 1: 'DPHY_SCRAMBLER_KCODE_ENABLED', +} +DPHY_SCRAMBLER_KCODE_DISABLED = 0 +DPHY_SCRAMBLER_KCODE_ENABLED = 1 +DPHY_SCRAMBLER_KCODE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_SEL' +DPHY_SCRAMBLER_SEL__enumvalues = { + 0: 'DPHY_SCRAMBLER_SEL_LANE_DATA', + 1: 'DPHY_SCRAMBLER_SEL_DBG_DATA', +} +DPHY_SCRAMBLER_SEL_LANE_DATA = 0 +DPHY_SCRAMBLER_SEL_DBG_DATA = 1 +DPHY_SCRAMBLER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SKEW_BYPASS' +DPHY_SKEW_BYPASS__enumvalues = { + 0: 'DPHY_WITH_SKEW', + 1: 'DPHY_NO_SKEW', +} +DPHY_WITH_SKEW = 0 +DPHY_NO_SKEW = 1 +DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM' +DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM__enumvalues = { + 0: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', + 1: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', +} +DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0 +DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 1 +DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SW_FAST_TRAINING_START' +DPHY_SW_FAST_TRAINING_START__enumvalues = { + 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 1: 'DPHY_SW_FAST_TRAINING_STARTED', +} +DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 +DPHY_SW_FAST_TRAINING_STARTED = 1 +DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_TRAINING_PATTERN_SEL' +DPHY_TRAINING_PATTERN_SEL__enumvalues = { + 0: 'DPHY_TRAINING_PATTERN_1', + 1: 'DPHY_TRAINING_PATTERN_2', + 2: 'DPHY_TRAINING_PATTERN_3', + 3: 'DPHY_TRAINING_PATTERN_4', +} +DPHY_TRAINING_PATTERN_1 = 0 +DPHY_TRAINING_PATTERN_2 = 1 +DPHY_TRAINING_PATTERN_3 = 2 +DPHY_TRAINING_PATTERN_4 = 3 +DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_COMPONENT_DEPTH' +DP_COMPONENT_DEPTH__enumvalues = { + 0: 'DP_COMPONENT_DEPTH_6BPC', + 1: 'DP_COMPONENT_DEPTH_8BPC', + 2: 'DP_COMPONENT_DEPTH_10BPC', + 3: 'DP_COMPONENT_DEPTH_12BPC', + 4: 'DP_COMPONENT_DEPTH_16BPC', +} +DP_COMPONENT_DEPTH_6BPC = 0 +DP_COMPONENT_DEPTH_8BPC = 1 +DP_COMPONENT_DEPTH_10BPC = 2 +DP_COMPONENT_DEPTH_12BPC = 3 +DP_COMPONENT_DEPTH_16BPC = 4 +DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'DP_CP_ENCRYPTION_TYPE' +DP_CP_ENCRYPTION_TYPE__enumvalues = { + 0: 'DP_CP_ENCRYPTION_TYPE_0', + 1: 'DP_CP_ENCRYPTION_TYPE_1', +} +DP_CP_ENCRYPTION_TYPE_0 = 0 +DP_CP_ENCRYPTION_TYPE_1 = 1 +DP_CP_ENCRYPTION_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_8B10B_EXT_DISP' +DP_DPHY_8B10B_EXT_DISP__enumvalues = { + 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', +} +DP_DPHY_8B10B_EXT_DISP_ZERO = 0 +DP_DPHY_8B10B_EXT_DISP_ONE = 1 +DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' +DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' +DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', +} +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' +DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { + 0: 'DP_DPHY_HBR2_PASS_THROUGH', + 1: 'DP_DPHY_HBR2_PATTERN_1', + 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', + 3: 'DP_DPHY_HBR2_PATTERN_3', + 6: 'DP_DPHY_HBR2_PATTERN_2_POS', +} +DP_DPHY_HBR2_PASS_THROUGH = 0 +DP_DPHY_HBR2_PATTERN_1 = 1 +DP_DPHY_HBR2_PATTERN_2_NEG = 2 +DP_DPHY_HBR2_PATTERN_3 = 3 +DP_DPHY_HBR2_PATTERN_2_POS = 6 +DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DSC_MODE' +DP_DSC_MODE__enumvalues = { + 0: 'DP_DSC_DISABLE', + 1: 'DP_DSC_444_SIMPLE_422', + 2: 'DP_DSC_NATIVE_422_420', +} +DP_DSC_DISABLE = 0 +DP_DSC_444_SIMPLE_422 = 1 +DP_DSC_NATIVE_422_420 = 2 +DP_DSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_EMBEDDED_PANEL_MODE' +DP_EMBEDDED_PANEL_MODE__enumvalues = { + 0: 'DP_EXTERNAL_PANEL', + 1: 'DP_EMBEDDED_PANEL', +} +DP_EXTERNAL_PANEL = 0 +DP_EMBEDDED_PANEL = 1 +DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_LINK_TRAINING_COMPLETE' +DP_LINK_TRAINING_COMPLETE__enumvalues = { + 0: 'DP_LINK_TRAINING_NOT_COMPLETE', + 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', +} +DP_LINK_TRAINING_NOT_COMPLETE = 0 +DP_LINK_TRAINING_ALREADY_COMPLETE = 1 +DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_LINK_TRAINING_SWITCH_MODE' +DP_LINK_TRAINING_SWITCH_MODE__enumvalues = { + 0: 'DP_LINK_TRAINING_SWITCH_TO_IDLE', + 1: 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', +} +DP_LINK_TRAINING_SWITCH_TO_IDLE = 0 +DP_LINK_TRAINING_SWITCH_TO_VIDEO = 1 +DP_LINK_TRAINING_SWITCH_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_ML_PHY_SEQ_MODE' +DP_ML_PHY_SEQ_MODE__enumvalues = { + 0: 'DP_ML_PHY_SEQ_LINE_NUM', + 1: 'DP_ML_PHY_SEQ_IMMEDIATE', +} +DP_ML_PHY_SEQ_LINE_NUM = 0 +DP_ML_PHY_SEQ_IMMEDIATE = 1 +DP_ML_PHY_SEQ_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' +DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { + 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', + 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', +} +MSA_V_TIMING_OVERRIDE_DISABLED = 0 +MSA_V_TIMING_OVERRIDE_ENABLED = 1 +DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_BLANK_CODE' +DP_MSE_BLANK_CODE__enumvalues = { + 0: 'DP_MSE_BLANK_CODE_SF_FILLED', + 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', +} +DP_MSE_BLANK_CODE_SF_FILLED = 0 +DP_MSE_BLANK_CODE_ZERO_FILLED = 1 +DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_LINK_LINE' +DP_MSE_LINK_LINE__enumvalues = { + 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', + 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', + 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', + 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', +} +DP_MSE_LINK_LINE_32_MTP_LONG = 0 +DP_MSE_LINK_LINE_64_MTP_LONG = 1 +DP_MSE_LINK_LINE_128_MTP_LONG = 2 +DP_MSE_LINK_LINE_256_MTP_LONG = 3 +DP_MSE_LINK_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT0' +DP_MSE_SAT_ENCRYPT0__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT0_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT0_ENABLED', +} +DP_MSE_SAT_ENCRYPT0_DISABLED = 0 +DP_MSE_SAT_ENCRYPT0_ENABLED = 1 +DP_MSE_SAT_ENCRYPT0 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT1' +DP_MSE_SAT_ENCRYPT1__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT1_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT1_ENABLED', +} +DP_MSE_SAT_ENCRYPT1_DISABLED = 0 +DP_MSE_SAT_ENCRYPT1_ENABLED = 1 +DP_MSE_SAT_ENCRYPT1 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT2' +DP_MSE_SAT_ENCRYPT2__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT2_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT2_ENABLED', +} +DP_MSE_SAT_ENCRYPT2_DISABLED = 0 +DP_MSE_SAT_ENCRYPT2_ENABLED = 1 +DP_MSE_SAT_ENCRYPT2 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT3' +DP_MSE_SAT_ENCRYPT3__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT3_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT3_ENABLED', +} +DP_MSE_SAT_ENCRYPT3_DISABLED = 0 +DP_MSE_SAT_ENCRYPT3_ENABLED = 1 +DP_MSE_SAT_ENCRYPT3 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT4' +DP_MSE_SAT_ENCRYPT4__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT4_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT4_ENABLED', +} +DP_MSE_SAT_ENCRYPT4_DISABLED = 0 +DP_MSE_SAT_ENCRYPT4_ENABLED = 1 +DP_MSE_SAT_ENCRYPT4 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT5' +DP_MSE_SAT_ENCRYPT5__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT5_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT5_ENABLED', +} +DP_MSE_SAT_ENCRYPT5_DISABLED = 0 +DP_MSE_SAT_ENCRYPT5_ENABLED = 1 +DP_MSE_SAT_ENCRYPT5 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_UPDATE_ACT' +DP_MSE_SAT_UPDATE_ACT__enumvalues = { + 0: 'DP_MSE_SAT_UPDATE_NO_ACTION', + 1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', + 2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', +} +DP_MSE_SAT_UPDATE_NO_ACTION = 0 +DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1 +DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2 +DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_TIMESTAMP_MODE' +DP_MSE_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', +} +DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 +DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 +DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_ZERO_ENCODER' +DP_MSE_ZERO_ENCODER__enumvalues = { + 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', + 1: 'DP_MSE_ZERO_FE_ENCODER', +} +DP_MSE_NOT_ZERO_FE_ENCODER = 0 +DP_MSE_ZERO_FE_ENCODER = 1 +DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSO_NUM_OF_SST_LINKS' +DP_MSO_NUM_OF_SST_LINKS__enumvalues = { + 0: 'DP_MSO_ONE_SSTLINK', + 1: 'DP_MSO_TWO_SSTLINK', + 2: 'DP_MSO_FOUR_SSTLINK', +} +DP_MSO_ONE_SSTLINK = 0 +DP_MSO_TWO_SSTLINK = 1 +DP_MSO_FOUR_SSTLINK = 2 +DP_MSO_NUM_OF_SST_LINKS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_PIXEL_ENCODING' +DP_PIXEL_ENCODING__enumvalues = { + 0: 'DP_PIXEL_ENCODING_RGB444', + 1: 'DP_PIXEL_ENCODING_YCBCR422', + 2: 'DP_PIXEL_ENCODING_YCBCR444', + 3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', + 4: 'DP_PIXEL_ENCODING_Y_ONLY', + 5: 'DP_PIXEL_ENCODING_YCBCR420', +} +DP_PIXEL_ENCODING_RGB444 = 0 +DP_PIXEL_ENCODING_YCBCR422 = 1 +DP_PIXEL_ENCODING_YCBCR444 = 2 +DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3 +DP_PIXEL_ENCODING_Y_ONLY = 4 +DP_PIXEL_ENCODING_YCBCR420 = 5 +DP_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'DP_PIXEL_PER_CYCLE_PROCESSING_NUM' +DP_PIXEL_PER_CYCLE_PROCESSING_NUM__enumvalues = { + 0: 'DP_ONE_PIXEL_PER_CYCLE', + 1: 'DP_TWO_PIXEL_PER_CYCLE', +} +DP_ONE_PIXEL_PER_CYCLE = 0 +DP_TWO_PIXEL_PER_CYCLE = 1 +DP_PIXEL_PER_CYCLE_PROCESSING_NUM = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { + 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', +} +DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_PRIORITY' +DP_SEC_ASP_PRIORITY__enumvalues = { + 0: 'DP_SEC_ASP_LOW_PRIORITY', + 1: 'DP_SEC_ASP_HIGH_PRIORITY', +} +DP_SEC_ASP_LOW_PRIORITY = 0 +DP_SEC_ASP_HIGH_PRIORITY = 1 +DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_AUDIO_MUTE' +DP_SEC_AUDIO_MUTE__enumvalues = { + 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', + 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', +} +DP_SEC_AUDIO_MUTE_HW_CTRL = 0 +DP_SEC_AUDIO_MUTE_SW_CTRL = 1 +DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_COLLISION_ACK' +DP_SEC_COLLISION_ACK__enumvalues = { + 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', + 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', +} +DP_SEC_COLLISION_ACK_NO_EFFECT = 0 +DP_SEC_COLLISION_ACK_CLR_FLAG = 1 +DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP0_PRIORITY' +DP_SEC_GSP0_PRIORITY__enumvalues = { + 0: 'SEC_GSP0_PRIORITY_LOW', + 1: 'SEC_GSP0_PRIORITY_HIGH', +} +SEC_GSP0_PRIORITY_LOW = 0 +SEC_GSP0_PRIORITY_HIGH = 1 +DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND' +DP_SEC_GSP_SEND__enumvalues = { + 0: 'NOT_SENT', + 1: 'FORCE_SENT', +} +NOT_SENT = 0 +FORCE_SENT = 1 +DP_SEC_GSP_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND_ANY_LINE' +DP_SEC_GSP_SEND_ANY_LINE__enumvalues = { + 0: 'SEND_AT_LINK_NUMBER', + 1: 'SEND_AT_EARLIEST_TIME', +} +SEND_AT_LINK_NUMBER = 0 +SEND_AT_EARLIEST_TIME = 1 +DP_SEC_GSP_SEND_ANY_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND_PPS' +DP_SEC_GSP_SEND_PPS__enumvalues = { + 0: 'SEND_NORMAL_PACKET', + 1: 'SEND_PPS_PACKET', +} +SEND_NORMAL_PACKET = 0 +SEND_PPS_PACKET = 1 +DP_SEC_GSP_SEND_PPS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_LINE_REFERENCE' +DP_SEC_LINE_REFERENCE__enumvalues = { + 0: 'REFER_TO_DP_SOF', + 1: 'REFER_TO_OTG_SOF', +} +REFER_TO_DP_SOF = 0 +REFER_TO_OTG_SOF = 1 +DP_SEC_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_TIMESTAMP_MODE' +DP_SEC_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', + 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', +} +DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 +DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 +DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_ACK' +DP_STEER_OVERFLOW_ACK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 +DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_MASK' +DP_STEER_OVERFLOW_MASK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_MASKED', + 1: 'DP_STEER_OVERFLOW_UNMASK', +} +DP_STEER_OVERFLOW_MASKED = 0 +DP_STEER_OVERFLOW_UNMASK = 1 +DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SYNC_POLARITY' +DP_SYNC_POLARITY__enumvalues = { + 0: 'DP_SYNC_POLARITY_ACTIVE_HIGH', + 1: 'DP_SYNC_POLARITY_ACTIVE_LOW', +} +DP_SYNC_POLARITY_ACTIVE_HIGH = 0 +DP_SYNC_POLARITY_ACTIVE_LOW = 1 +DP_SYNC_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_TU_OVERFLOW_ACK' +DP_TU_OVERFLOW_ACK__enumvalues = { + 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 +DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_UDI_LANES' +DP_UDI_LANES__enumvalues = { + 0: 'DP_UDI_1_LANE', + 1: 'DP_UDI_2_LANES', + 2: 'DP_UDI_LANES_RESERVED', + 3: 'DP_UDI_4_LANES', +} +DP_UDI_1_LANE = 0 +DP_UDI_2_LANES = 1 +DP_UDI_LANES_RESERVED = 2 +DP_UDI_4_LANES = 3 +DP_UDI_LANES = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' +DP_VID_ENHANCED_FRAME_MODE__enumvalues = { + 0: 'VID_NORMAL_FRAME_MODE', + 1: 'VID_ENHANCED_MODE', +} +VID_NORMAL_FRAME_MODE = 0 +VID_ENHANCED_MODE = 1 +DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' +DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { + 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', +} +DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 +DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 +DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_GEN_EN' +DP_VID_M_N_GEN_EN__enumvalues = { + 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', + 1: 'DP_VID_M_N_CALC_AUTO', +} +DP_VID_M_N_PROGRAMMED_VIA_REG = 0 +DP_VID_M_N_CALC_AUTO = 1 +DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_N_MUL' +DP_VID_N_MUL__enumvalues = { + 0: 'DP_VID_M_1X_INPUT_PIXEL_RATE', + 1: 'DP_VID_M_2X_INPUT_PIXEL_RATE', + 2: 'DP_VID_M_4X_INPUT_PIXEL_RATE', + 3: 'DP_VID_M_8X_INPUT_PIXEL_RATE', +} +DP_VID_M_1X_INPUT_PIXEL_RATE = 0 +DP_VID_M_2X_INPUT_PIXEL_RATE = 1 +DP_VID_M_4X_INPUT_PIXEL_RATE = 2 +DP_VID_M_8X_INPUT_PIXEL_RATE = 3 +DP_VID_N_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_ACK' +DP_VID_STREAM_DISABLE_ACK__enumvalues = { + 0: 'ID_STREAM_DISABLE_NO_ACK', + 1: 'ID_STREAM_DISABLE_ACKED', +} +ID_STREAM_DISABLE_NO_ACK = 0 +ID_STREAM_DISABLE_ACKED = 1 +DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_MASK' +DP_VID_STREAM_DISABLE_MASK__enumvalues = { + 0: 'VID_STREAM_DISABLE_MASKED', + 1: 'VID_STREAM_DISABLE_UNMASK', +} +VID_STREAM_DISABLE_MASKED = 0 +VID_STREAM_DISABLE_UNMASK = 1 +DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DIS_DEFER' +DP_VID_STREAM_DIS_DEFER__enumvalues = { + 0: 'DP_VID_STREAM_DIS_NO_DEFER', + 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', +} +DP_VID_STREAM_DIS_NO_DEFER = 0 +DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 +DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 +DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_VBID_FIELD_POL' +DP_VID_VBID_FIELD_POL__enumvalues = { + 0: 'DP_VID_VBID_FIELD_POL_NORMAL', + 1: 'DP_VID_VBID_FIELD_POL_INV', +} +DP_VID_VBID_FIELD_POL_NORMAL = 0 +DP_VID_VBID_FIELD_POL_INV = 1 +DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum + +# values for enumeration 'FEC_ACTIVE_STATUS' +FEC_ACTIVE_STATUS__enumvalues = { + 0: 'DPHY_FEC_NOT_ACTIVE', + 1: 'DPHY_FEC_ACTIVE', +} +DPHY_FEC_NOT_ACTIVE = 0 +DPHY_FEC_ACTIVE = 1 +FEC_ACTIVE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_HPD_SELECT' +DIG_BE_CNTL_HPD_SELECT__enumvalues = { + 0: 'DIG_BE_CNTL_HPD1', + 1: 'DIG_BE_CNTL_HPD2', + 2: 'DIG_BE_CNTL_HPD3', + 3: 'DIG_BE_CNTL_HPD4', + 4: 'DIG_BE_CNTL_HPD5', + 5: 'DIG_BE_CNTL_NO_HPD', +} +DIG_BE_CNTL_HPD1 = 0 +DIG_BE_CNTL_HPD2 = 1 +DIG_BE_CNTL_HPD3 = 2 +DIG_BE_CNTL_HPD4 = 3 +DIG_BE_CNTL_HPD5 = 4 +DIG_BE_CNTL_NO_HPD = 5 +DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_MODE' +DIG_BE_CNTL_MODE__enumvalues = { + 0: 'DIG_BE_DP_SST_MODE', + 1: 'DIG_BE_RESERVED1', + 2: 'DIG_BE_TMDS_DVI_MODE', + 3: 'DIG_BE_TMDS_HDMI_MODE', + 4: 'DIG_BE_RESERVED4', + 5: 'DIG_BE_DP_MST_MODE', + 6: 'DIG_BE_RESERVED2', + 7: 'DIG_BE_RESERVED3', +} +DIG_BE_DP_SST_MODE = 0 +DIG_BE_RESERVED1 = 1 +DIG_BE_TMDS_DVI_MODE = 2 +DIG_BE_TMDS_HDMI_MODE = 3 +DIG_BE_RESERVED4 = 4 +DIG_BE_DP_MST_MODE = 5 +DIG_BE_RESERVED2 = 6 +DIG_BE_RESERVED3 = 7 +DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_DIGITAL_BYPASS_ENABLE' +DIG_DIGITAL_BYPASS_ENABLE__enumvalues = { + 0: 'DIG_DIGITAL_BYPASS_OFF', + 1: 'DIG_DIGITAL_BYPASS_ON', +} +DIG_DIGITAL_BYPASS_OFF = 0 +DIG_DIGITAL_BYPASS_ON = 1 +DIG_DIGITAL_BYPASS_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_DIGITAL_BYPASS_SEL' +DIG_DIGITAL_BYPASS_SEL__enumvalues = { + 0: 'DIG_DIGITAL_BYPASS_SEL_BYPASS', + 1: 'DIG_DIGITAL_BYPASS_SEL_36BPP', + 2: 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', + 3: 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', + 4: 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', + 5: 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', + 6: 'DIG_DIGITAL_BYPASS_SEL_ALPHA', +} +DIG_DIGITAL_BYPASS_SEL_BYPASS = 0 +DIG_DIGITAL_BYPASS_SEL_36BPP = 1 +DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 2 +DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 3 +DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 4 +DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 5 +DIG_DIGITAL_BYPASS_SEL_ALPHA = 6 +DIG_DIGITAL_BYPASS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' +DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { + 0: 'DIG_FE_SOURCE_FROM_OTG0', + 1: 'DIG_FE_SOURCE_FROM_OTG1', + 2: 'DIG_FE_SOURCE_FROM_OTG2', + 3: 'DIG_FE_SOURCE_FROM_OTG3', + 4: 'DIG_FE_SOURCE_RESERVED', +} +DIG_FE_SOURCE_FROM_OTG0 = 0 +DIG_FE_SOURCE_FROM_OTG1 = 1 +DIG_FE_SOURCE_FROM_OTG2 = 2 +DIG_FE_SOURCE_FROM_OTG3 = 3 +DIG_FE_SOURCE_RESERVED = 4 +DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' +DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { + 0: 'DIG_FE_STEREOSYNC_FROM_OTG0', + 1: 'DIG_FE_STEREOSYNC_FROM_OTG1', + 2: 'DIG_FE_STEREOSYNC_FROM_OTG2', + 3: 'DIG_FE_STEREOSYNC_FROM_OTG3', + 4: 'DIG_FE_STEREOSYNC_RESERVED', +} +DIG_FE_STEREOSYNC_FROM_OTG0 = 0 +DIG_FE_STEREOSYNC_FROM_OTG1 = 1 +DIG_FE_STEREOSYNC_FROM_OTG2 = 2 +DIG_FE_STEREOSYNC_FROM_OTG3 = 3 +DIG_FE_STEREOSYNC_RESERVED = 4 +DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX' +DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', + 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', +} +DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 +DIG_FIFO_FORCE_RECOMP_MINMAX = 1 +DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL' +DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL__enumvalues = { + 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', + 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', +} +DIG_FIFO_USE_OVERWRITE_LEVEL = 0 +DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 +DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_FORCE_RECAL_AVERAGE' +DIG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', +} +DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 +DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 +DIG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_OUTPUT_PROCESSING_MODE' +DIG_FIFO_OUTPUT_PROCESSING_MODE__enumvalues = { + 0: 'DIG_FIFO_1_PIX_PER_CYCLE', + 1: 'DIG_FIFO_2_PIX_PER_CYCLE', +} +DIG_FIFO_1_PIX_PER_CYCLE = 0 +DIG_FIFO_2_PIX_PER_CYCLE = 1 +DIG_FIFO_OUTPUT_PROCESSING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR' +DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { + 0: 'DIG_FIFO_NO_ERROR_OCCURRED', + 1: 'DIG_FIFO_UNDERFLOW_OCCURRED', + 2: 'DIG_FIFO_OVERFLOW_OCCURRED', +} +DIG_FIFO_NO_ERROR_OCCURRED = 0 +DIG_FIFO_UNDERFLOW_OCCURRED = 1 +DIG_FIFO_OVERFLOW_OCCURRED = 2 +DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' +DIG_FIFO_READ_CLOCK_SRC__enumvalues = { + 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', +} +DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 +DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 +DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_INPUT_PIXEL_SEL' +DIG_INPUT_PIXEL_SEL__enumvalues = { + 0: 'DIG_ALL_PIXEL', + 1: 'DIG_EVEN_PIXEL_ONLY', + 2: 'DIG_ODD_PIXEL_ONLY', +} +DIG_ALL_PIXEL = 0 +DIG_EVEN_PIXEL_ONLY = 1 +DIG_ODD_PIXEL_ONLY = 2 +DIG_INPUT_PIXEL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' +DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_ON_LINK0', + 1: 'DIG_OUTPUT_CRC_ON_LINK1', +} +DIG_OUTPUT_CRC_ON_LINK0 = 0 +DIG_OUTPUT_CRC_ON_LINK1 = 1 +DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' +DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', + 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', + 2: 'DIG_OUTPUT_CRC_FOR_VBI', + 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', +} +DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 +DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 +DIG_OUTPUT_CRC_FOR_VBI = 2 +DIG_OUTPUT_CRC_FOR_AUDIO = 3 +DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' +DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', +} +DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 +DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 +DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_SL_PIXEL_GROUPING' +DIG_SL_PIXEL_GROUPING__enumvalues = { + 0: 'DIG_SINGLETON_PIXELS', + 1: 'DIG_PAIR_PIXELS', +} +DIG_SINGLETON_PIXELS = 0 +DIG_PAIR_PIXELS = 1 +DIG_SL_PIXEL_GROUPING = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' +DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', +} +DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 +DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 +DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { + 0: 'DIG_10BIT_TEST_PATTERN', + 1: 'DIG_ALTERNATING_TEST_PATTERN', +} +DIG_10BIT_TEST_PATTERN = 0 +DIG_ALTERNATING_TEST_PATTERN = 1 +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_NORMAL', + 1: 'DIG_TEST_PATTERN_RANDOM', +} +DIG_TEST_PATTERN_NORMAL = 0 +DIG_TEST_PATTERN_RANDOM = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_ENABLED', + 1: 'DIG_RANDOM_PATTERN_RESETED', +} +DIG_RANDOM_PATTERN_ENABLED = 0 +DIG_RANDOM_PATTERN_RESETED = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_IN_NORMAL_OPERATION', + 1: 'DIG_IN_DEBUG_MODE', +} +DIG_IN_NORMAL_OPERATION = 0 +DIG_IN_DEBUG_MODE = 1 +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOLBY_VISION_ENABLE' +DOLBY_VISION_ENABLE__enumvalues = { + 0: 'DOLBY_VISION_DISABLED', + 1: 'DOLBY_VISION_ENABLED', +} +DOLBY_VISION_DISABLED = 0 +DOLBY_VISION_ENABLED = 1 +DOLBY_VISION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACP_SEND' +HDMI_ACP_SEND__enumvalues = { + 0: 'HDMI_ACP_NOT_SEND', + 1: 'HDMI_ACP_PKT_SEND', +} +HDMI_ACP_NOT_SEND = 0 +HDMI_ACP_PKT_SEND = 1 +HDMI_ACP_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' +HDMI_ACR_AUDIO_PRIORITY__enumvalues = { + 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', +} +HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 +HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 +HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_CONT' +HDMI_ACR_CONT__enumvalues = { + 0: 'HDMI_ACR_CONT_DISABLE', + 1: 'HDMI_ACR_CONT_ENABLE', +} +HDMI_ACR_CONT_DISABLE = 0 +HDMI_ACR_CONT_ENABLE = 1 +HDMI_ACR_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_N_MULTIPLE' +HDMI_ACR_N_MULTIPLE__enumvalues = { + 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', + 1: 'HDMI_ACR_1_MULTIPLE', + 2: 'HDMI_ACR_2_MULTIPLE', + 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', + 4: 'HDMI_ACR_4_MULTIPLE', + 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', + 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', + 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', +} +HDMI_ACR_0_MULTIPLE_RESERVED = 0 +HDMI_ACR_1_MULTIPLE = 1 +HDMI_ACR_2_MULTIPLE = 2 +HDMI_ACR_3_MULTIPLE_RESERVED = 3 +HDMI_ACR_4_MULTIPLE = 4 +HDMI_ACR_5_MULTIPLE_RESERVED = 5 +HDMI_ACR_6_MULTIPLE_RESERVED = 6 +HDMI_ACR_7_MULTIPLE_RESERVED = 7 +HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SELECT' +HDMI_ACR_SELECT__enumvalues = { + 0: 'HDMI_ACR_SELECT_HW', + 1: 'HDMI_ACR_SELECT_32K', + 2: 'HDMI_ACR_SELECT_44K', + 3: 'HDMI_ACR_SELECT_48K', +} +HDMI_ACR_SELECT_HW = 0 +HDMI_ACR_SELECT_32K = 1 +HDMI_ACR_SELECT_44K = 2 +HDMI_ACR_SELECT_48K = 3 +HDMI_ACR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SEND' +HDMI_ACR_SEND__enumvalues = { + 0: 'HDMI_ACR_NOT_SEND', + 1: 'HDMI_ACR_PKT_SEND', +} +HDMI_ACR_NOT_SEND = 0 +HDMI_ACR_PKT_SEND = 1 +HDMI_ACR_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SOURCE' +HDMI_ACR_SOURCE__enumvalues = { + 0: 'HDMI_ACR_SOURCE_HW', + 1: 'HDMI_ACR_SOURCE_SW', +} +HDMI_ACR_SOURCE_HW = 0 +HDMI_ACR_SOURCE_SW = 1 +HDMI_ACR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_DELAY_EN' +HDMI_AUDIO_DELAY_EN__enumvalues = { + 0: 'HDMI_AUDIO_DELAY_DISABLE', + 1: 'HDMI_AUDIO_DELAY_58CLK', + 2: 'HDMI_AUDIO_DELAY_56CLK', + 3: 'HDMI_AUDIO_DELAY_RESERVED', +} +HDMI_AUDIO_DELAY_DISABLE = 0 +HDMI_AUDIO_DELAY_58CLK = 1 +HDMI_AUDIO_DELAY_56CLK = 2 +HDMI_AUDIO_DELAY_RESERVED = 3 +HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_CONT' +HDMI_AUDIO_INFO_CONT__enumvalues = { + 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', + 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', +} +HDMI_AUDIO_INFO_CONT_DISABLE = 0 +HDMI_AUDIO_INFO_CONT_ENABLE = 1 +HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_SEND' +HDMI_AUDIO_INFO_SEND__enumvalues = { + 0: 'HDMI_AUDIO_INFO_NOT_SEND', + 1: 'HDMI_AUDIO_INFO_PKT_SEND', +} +HDMI_AUDIO_INFO_NOT_SEND = 0 +HDMI_AUDIO_INFO_PKT_SEND = 1 +HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' +HDMI_CLOCK_CHANNEL_RATE__enumvalues = { + 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', +} +HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 +HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 +HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DATA_SCRAMBLE_EN' +HDMI_DATA_SCRAMBLE_EN__enumvalues = { + 0: 'HDMI_DATA_SCRAMBLE_DISABLE', + 1: 'HDMI_DATA_SCRAMBLE_ENABLE', +} +HDMI_DATA_SCRAMBLE_DISABLE = 0 +HDMI_DATA_SCRAMBLE_ENABLE = 1 +HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEEP_COLOR_DEPTH' +HDMI_DEEP_COLOR_DEPTH__enumvalues = { + 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', + 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 3: 'HDMI_DEEP_COLOR_DEPTH_48BPP', +} +HDMI_DEEP_COLOR_DEPTH_24BPP = 0 +HDMI_DEEP_COLOR_DEPTH_30BPP = 1 +HDMI_DEEP_COLOR_DEPTH_36BPP = 2 +HDMI_DEEP_COLOR_DEPTH_48BPP = 3 +HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEFAULT_PAHSE' +HDMI_DEFAULT_PAHSE__enumvalues = { + 0: 'HDMI_DEFAULT_PHASE_IS_0', + 1: 'HDMI_DEFAULT_PHASE_IS_1', +} +HDMI_DEFAULT_PHASE_IS_0 = 0 +HDMI_DEFAULT_PHASE_IS_1 = 1 +HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_ACK' +HDMI_ERROR_ACK__enumvalues = { + 0: 'HDMI_ERROR_ACK_INT', + 1: 'HDMI_ERROR_NOT_ACK', +} +HDMI_ERROR_ACK_INT = 0 +HDMI_ERROR_NOT_ACK = 1 +HDMI_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_MASK' +HDMI_ERROR_MASK__enumvalues = { + 0: 'HDMI_ERROR_MASK_INT', + 1: 'HDMI_ERROR_NOT_MASK', +} +HDMI_ERROR_MASK_INT = 0 +HDMI_ERROR_NOT_MASK = 1 +HDMI_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE' +HDMI_GC_AVMUTE__enumvalues = { + 0: 'HDMI_GC_AVMUTE_SET', + 1: 'HDMI_GC_AVMUTE_UNSET', +} +HDMI_GC_AVMUTE_SET = 0 +HDMI_GC_AVMUTE_UNSET = 1 +HDMI_GC_AVMUTE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE_CONT' +HDMI_GC_AVMUTE_CONT__enumvalues = { + 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', + 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', +} +HDMI_GC_AVMUTE_CONT_DISABLE = 0 +HDMI_GC_AVMUTE_CONT_ENABLE = 1 +HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_CONT' +HDMI_GC_CONT__enumvalues = { + 0: 'HDMI_GC_CONT_DISABLE', + 1: 'HDMI_GC_CONT_ENABLE', +} +HDMI_GC_CONT_DISABLE = 0 +HDMI_GC_CONT_ENABLE = 1 +HDMI_GC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_SEND' +HDMI_GC_SEND__enumvalues = { + 0: 'HDMI_GC_NOT_SEND', + 1: 'HDMI_GC_PKT_SEND', +} +HDMI_GC_NOT_SEND = 0 +HDMI_GC_PKT_SEND = 1 +HDMI_GC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC_CONT' +HDMI_GENERIC_CONT__enumvalues = { + 0: 'HDMI_GENERIC_CONT_DISABLE', + 1: 'HDMI_GENERIC_CONT_ENABLE', +} +HDMI_GENERIC_CONT_DISABLE = 0 +HDMI_GENERIC_CONT_ENABLE = 1 +HDMI_GENERIC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC_SEND' +HDMI_GENERIC_SEND__enumvalues = { + 0: 'HDMI_GENERIC_NOT_SEND', + 1: 'HDMI_GENERIC_PKT_SEND', +} +HDMI_GENERIC_NOT_SEND = 0 +HDMI_GENERIC_PKT_SEND = 1 +HDMI_GENERIC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_CONT' +HDMI_ISRC_CONT__enumvalues = { + 0: 'HDMI_ISRC_CONT_DISABLE', + 1: 'HDMI_ISRC_CONT_ENABLE', +} +HDMI_ISRC_CONT_DISABLE = 0 +HDMI_ISRC_CONT_ENABLE = 1 +HDMI_ISRC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_SEND' +HDMI_ISRC_SEND__enumvalues = { + 0: 'HDMI_ISRC_NOT_SEND', + 1: 'HDMI_ISRC_PKT_SEND', +} +HDMI_ISRC_NOT_SEND = 0 +HDMI_ISRC_PKT_SEND = 1 +HDMI_ISRC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_KEEPOUT_MODE' +HDMI_KEEPOUT_MODE__enumvalues = { + 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', +} +HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 +HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 +HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_METADATA_ENABLE' +HDMI_METADATA_ENABLE__enumvalues = { + 0: 'HDMI_METADATA_NOT_SEND', + 1: 'HDMI_METADATA_PKT_SEND', +} +HDMI_METADATA_NOT_SEND = 0 +HDMI_METADATA_PKT_SEND = 1 +HDMI_METADATA_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_CONT' +HDMI_MPEG_INFO_CONT__enumvalues = { + 0: 'HDMI_MPEG_INFO_CONT_DISABLE', + 1: 'HDMI_MPEG_INFO_CONT_ENABLE', +} +HDMI_MPEG_INFO_CONT_DISABLE = 0 +HDMI_MPEG_INFO_CONT_ENABLE = 1 +HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_SEND' +HDMI_MPEG_INFO_SEND__enumvalues = { + 0: 'HDMI_MPEG_INFO_NOT_SEND', + 1: 'HDMI_MPEG_INFO_PKT_SEND', +} +HDMI_MPEG_INFO_NOT_SEND = 0 +HDMI_MPEG_INFO_PKT_SEND = 1 +HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' +HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { + 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', + 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', +} +HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 +HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 +HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NULL_SEND' +HDMI_NULL_SEND__enumvalues = { + 0: 'HDMI_NULL_NOT_SEND', + 1: 'HDMI_NULL_PKT_SEND', +} +HDMI_NULL_NOT_SEND = 0 +HDMI_NULL_PKT_SEND = 1 +HDMI_NULL_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKET_GEN_VERSION' +HDMI_PACKET_GEN_VERSION__enumvalues = { + 0: 'HDMI_PACKET_GEN_VERSION_OLD', + 1: 'HDMI_PACKET_GEN_VERSION_NEW', +} +HDMI_PACKET_GEN_VERSION_OLD = 0 +HDMI_PACKET_GEN_VERSION_NEW = 1 +HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKET_LINE_REFERENCE' +HDMI_PACKET_LINE_REFERENCE__enumvalues = { + 0: 'HDMI_PKT_LINE_REF_VSYNC', + 1: 'HDMI_PKT_LINE_REF_OTGSOF', +} +HDMI_PKT_LINE_REF_VSYNC = 0 +HDMI_PKT_LINE_REF_OTGSOF = 1 +HDMI_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' +HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { + 0: 'HDMI_PACKING_PHASE_SET_BY_HW', + 1: 'HDMI_PACKING_PHASE_SET_BY_SW', +} +HDMI_PACKING_PHASE_SET_BY_HW = 0 +HDMI_PACKING_PHASE_SET_BY_SW = 1 +HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', +} +LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 +LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_COLOR_FORMAT' +TMDS_COLOR_FORMAT__enumvalues = { + 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', + 3: 'TMDS_COLOR_FORMAT_RESERVED', +} +TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 +TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 +TMDS_COLOR_FORMAT_DUAL30BPP = 2 +TMDS_COLOR_FORMAT_RESERVED = 3 +TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_INVERT' +TMDS_CTL0_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL0_DATA_NORMAL', + 1: 'TMDS_CTL0_DATA_INVERT_EN', +} +TMDS_CTL0_DATA_NORMAL = 0 +TMDS_CTL0_DATA_INVERT_EN = 1 +TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_MODULATION' +TMDS_CTL0_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', +} +TMDS_CTL0_DATA_MODULATION_DISABLE = 0 +TMDS_CTL0_DATA_MODULATION_BIT0 = 1 +TMDS_CTL0_DATA_MODULATION_BIT1 = 2 +TMDS_CTL0_DATA_MODULATION_BIT2 = 3 +TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_SEL' +TMDS_CTL0_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', +} +TMDS_CTL0_DATA_SEL0_RESERVED = 0 +TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL0_DATA_SEL2_VSYNC = 2 +TMDS_CTL0_DATA_SEL3_RESERVED = 3 +TMDS_CTL0_DATA_SEL4_HSYNC = 4 +TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 +TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 +TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' +TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', +} +TMDS_CTL0_PATTERN_OUT_DISABLE = 0 +TMDS_CTL0_PATTERN_OUT_ENABLE = 1 +TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_INVERT' +TMDS_CTL1_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL1_DATA_NORMAL', + 1: 'TMDS_CTL1_DATA_INVERT_EN', +} +TMDS_CTL1_DATA_NORMAL = 0 +TMDS_CTL1_DATA_INVERT_EN = 1 +TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_MODULATION' +TMDS_CTL1_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', +} +TMDS_CTL1_DATA_MODULATION_DISABLE = 0 +TMDS_CTL1_DATA_MODULATION_BIT0 = 1 +TMDS_CTL1_DATA_MODULATION_BIT1 = 2 +TMDS_CTL1_DATA_MODULATION_BIT2 = 3 +TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_SEL' +TMDS_CTL1_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL1_DATA_SEL0_RESERVED = 0 +TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL1_DATA_SEL2_VSYNC = 2 +TMDS_CTL1_DATA_SEL3_RESERVED = 3 +TMDS_CTL1_DATA_SEL4_HSYNC = 4 +TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' +TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', +} +TMDS_CTL1_PATTERN_OUT_DISABLE = 0 +TMDS_CTL1_PATTERN_OUT_ENABLE = 1 +TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_INVERT' +TMDS_CTL2_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL2_DATA_NORMAL', + 1: 'TMDS_CTL2_DATA_INVERT_EN', +} +TMDS_CTL2_DATA_NORMAL = 0 +TMDS_CTL2_DATA_INVERT_EN = 1 +TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_MODULATION' +TMDS_CTL2_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', +} +TMDS_CTL2_DATA_MODULATION_DISABLE = 0 +TMDS_CTL2_DATA_MODULATION_BIT0 = 1 +TMDS_CTL2_DATA_MODULATION_BIT1 = 2 +TMDS_CTL2_DATA_MODULATION_BIT2 = 3 +TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_SEL' +TMDS_CTL2_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL2_DATA_SEL0_RESERVED = 0 +TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL2_DATA_SEL2_VSYNC = 2 +TMDS_CTL2_DATA_SEL3_RESERVED = 3 +TMDS_CTL2_DATA_SEL4_HSYNC = 4 +TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' +TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', +} +TMDS_CTL2_PATTERN_OUT_DISABLE = 0 +TMDS_CTL2_PATTERN_OUT_ENABLE = 1 +TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_INVERT' +TMDS_CTL3_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL3_DATA_NORMAL', + 1: 'TMDS_CTL3_DATA_INVERT_EN', +} +TMDS_CTL3_DATA_NORMAL = 0 +TMDS_CTL3_DATA_INVERT_EN = 1 +TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_MODULATION' +TMDS_CTL3_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', +} +TMDS_CTL3_DATA_MODULATION_DISABLE = 0 +TMDS_CTL3_DATA_MODULATION_BIT0 = 1 +TMDS_CTL3_DATA_MODULATION_BIT1 = 2 +TMDS_CTL3_DATA_MODULATION_BIT2 = 3 +TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_SEL' +TMDS_CTL3_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL3_DATA_SEL0_RESERVED = 0 +TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL3_DATA_SEL2_VSYNC = 2 +TMDS_CTL3_DATA_SEL3_RESERVED = 3 +TMDS_CTL3_DATA_SEL4_HSYNC = 4 +TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' +TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', +} +TMDS_CTL3_PATTERN_OUT_DISABLE = 0 +TMDS_CTL3_PATTERN_OUT_ENABLE = 1 +TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' +TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { + 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', +} +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_PIXEL_ENCODING' +TMDS_PIXEL_ENCODING__enumvalues = { + 0: 'TMDS_PIXEL_ENCODING_444_OR_420', + 1: 'TMDS_PIXEL_ENCODING_422', +} +TMDS_PIXEL_ENCODING_444_OR_420 = 0 +TMDS_PIXEL_ENCODING_422 = 1 +TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' +TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', +} +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 +TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 +TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' +TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', + 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', +} +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 +TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 +TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' +TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { + 0: 'TMDS_STEREOSYNC_CTL0', + 1: 'TMDS_STEREOSYNC_CTL1', + 2: 'TMDS_STEREOSYNC_CTL2', + 3: 'TMDS_STEREOSYNC_CTL3', +} +TMDS_STEREOSYNC_CTL0 = 0 +TMDS_STEREOSYNC_CTL1 = 1 +TMDS_STEREOSYNC_CTL2 = 2 +TMDS_STEREOSYNC_CTL3 = 3 +TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_SYNC_PHASE' +TMDS_SYNC_PHASE__enumvalues = { + 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', + 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', +} +TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 +TMDS_SYNC_PHASE_ON_FRAME_START = 1 +TMDS_SYNC_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' +TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' +TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', +} +TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 +TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', +} +TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', +} +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', +} +TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 +TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 +TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', + 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 +TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' +DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', +} +DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 +DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', +} +DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 +DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', +} +DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 +DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_STATUS' +DP_AUX_ARB_STATUS__enumvalues = { + 0: 'DP_AUX_IDLE', + 1: 'DP_AUX_IN_USE_LS', + 2: 'DP_AUX_IN_USE_GTC', + 3: 'DP_AUX_IN_USE_SW', + 4: 'DP_AUX_IN_USE_PHYWAKE', +} +DP_AUX_IDLE = 0 +DP_AUX_IN_USE_LS = 1 +DP_AUX_IN_USE_GTC = 2 +DP_AUX_IN_USE_SW = 3 +DP_AUX_IN_USE_PHYWAKE = 4 +DP_AUX_ARB_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_HPD_SEL' +DP_AUX_CONTROL_HPD_SEL__enumvalues = { + 0: 'DP_AUX_CONTROL_HPD1_SELECTED', + 1: 'DP_AUX_CONTROL_HPD2_SELECTED', + 2: 'DP_AUX_CONTROL_HPD3_SELECTED', + 3: 'DP_AUX_CONTROL_HPD4_SELECTED', + 4: 'DP_AUX_CONTROL_HPD5_SELECTED', + 5: 'DP_AUX_CONTROL_NO_HPD_SELECTED', +} +DP_AUX_CONTROL_HPD1_SELECTED = 0 +DP_AUX_CONTROL_HPD2_SELECTED = 1 +DP_AUX_CONTROL_HPD3_SELECTED = 2 +DP_AUX_CONTROL_HPD4_SELECTED = 3 +DP_AUX_CONTROL_HPD5_SELECTED = 4 +DP_AUX_CONTROL_NO_HPD_SELECTED = 5 +DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_TEST_MODE' +DP_AUX_CONTROL_TEST_MODE__enumvalues = { + 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', +} +DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 +DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 +DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' +DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { + 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', + 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', +} +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 +DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', +} +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', +} +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { + 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', +} +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { + 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', +} +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' +DP_AUX_ERR_OCCURRED_ACK__enumvalues = { + 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 1: 'DP_AUX_ERR_OCCURRED__ACK', +} +DP_AUX_ERR_OCCURRED__NOT_ACK = 0 +DP_AUX_ERR_OCCURRED__ACK = 1 +DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', +} +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', +} +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', +} +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', +} +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_INT_ACK' +DP_AUX_INT_ACK__enumvalues = { + 0: 'DP_AUX_INT__NOT_ACK', + 1: 'DP_AUX_INT__ACK', +} +DP_AUX_INT__NOT_ACK = 0 +DP_AUX_INT__ACK = 1 +DP_AUX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_LS_UPDATE_ACK' +DP_AUX_LS_UPDATE_ACK__enumvalues = { + 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', + 1: 'DP_AUX_INT_LS_UPDATE_ACK', +} +DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 +DP_AUX_INT_LS_UPDATE_ACK = 1 +DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_PHY_WAKE_PRIORITY' +DP_AUX_PHY_WAKE_PRIORITY__enumvalues = { + 0: 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', + 1: 'DP_AUX_PHY_WAKE_LOW_PRIORITY', +} +DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0 +DP_AUX_PHY_WAKE_LOW_PRIORITY = 1 +DP_AUX_PHY_WAKE_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' +DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { + 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', + 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', +} +DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 +DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 +DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET' +DP_AUX_RESET__enumvalues = { + 0: 'DP_AUX_RESET_DEASSERTED', + 1: 'DP_AUX_RESET_ASSERTED', +} +DP_AUX_RESET_DEASSERTED = 0 +DP_AUX_RESET_ASSERTED = 1 +DP_AUX_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET_DONE' +DP_AUX_RESET_DONE__enumvalues = { + 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', + 1: 'DP_AUX_RESET_SEQUENCE_DONE', +} +DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 +DP_AUX_RESET_SEQUENCE_DONE = 1 +DP_AUX_RESET_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RX_TIMEOUT_LEN_MUL' +DP_AUX_RX_TIMEOUT_LEN_MUL__enumvalues = { + 0: 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', + 1: 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', + 2: 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', + 3: 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', +} +DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0 +DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 1 +DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 2 +DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 3 +DP_AUX_RX_TIMEOUT_LEN_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' +DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', +} +DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 +DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 +DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' +DP_AUX_SW_CONTROL_SW_GO__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 1: 'DP_AUX_SW_CONTROL_SW__GO', +} +DP_AUX_SW_CONTROL_SW__NOT_GO = 0 +DP_AUX_SW_CONTROL_SW__GO = 1 +DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_TX_PRECHARGE_LEN_MUL' +DP_AUX_TX_PRECHARGE_LEN_MUL__enumvalues = { + 0: 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', + 1: 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', + 2: 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', + 3: 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', +} +DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0 +DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 1 +DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 2 +DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 3 +DP_AUX_TX_PRECHARGE_LEN_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ACK' +DOUT_I2C_ACK__enumvalues = { + 0: 'DOUT_I2C_NO_ACK', + 1: 'DOUT_I2C_ACK_TO_CLEAN', +} +DOUT_I2C_NO_ACK = 0 +DOUT_I2C_ACK_TO_CLEAN = 1 +DOUT_I2C_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' +DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', +} +DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 +DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 +DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', +} +DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 +DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', +} +DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 +DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' +DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', +} +DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 +DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 +DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 +DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 +DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', +} +DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 +DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL' +DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG', + 1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', +} +DOUT_I2C_CONTROL_NORMAL_DEBUG = 0 +DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1 +DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' +DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', + 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', + 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', + 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', + 4: 'DOUT_I2C_CONTROL_SELECT_DDC5', + 5: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', +} +DOUT_I2C_CONTROL_SELECT_DDC1 = 0 +DOUT_I2C_CONTROL_SELECT_DDC2 = 1 +DOUT_I2C_CONTROL_SELECT_DDC3 = 2 +DOUT_I2C_CONTROL_SELECT_DDC4 = 3 +DOUT_I2C_CONTROL_SELECT_DDC5 = 4 +DOUT_I2C_CONTROL_SELECT_DDCVGA = 5 +DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_GO' +DOUT_I2C_CONTROL_GO__enumvalues = { + 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 1: 'DOUT_I2C_CONTROL_START_TRANSFER', +} +DOUT_I2C_CONTROL_STOP_TRANSFER = 0 +DOUT_I2C_CONTROL_START_TRANSFER = 1 +DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' +DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 1: 'DOUT_I2C_CONTROL__SEND_RESET', +} +DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 +DOUT_I2C_CONTROL__SEND_RESET = 1 +DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH' +DOUT_I2C_CONTROL_SEND_RESET_LENGTH__enumvalues = { + 0: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', + 1: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', +} +DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0 +DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 1 +DOUT_I2C_CONTROL_SEND_RESET_LENGTH = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' +DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', +} +DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 +DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 +DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' +DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', +} +DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 +DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 +DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' +DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_TRANS0', + 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', +} +DOUT_I2C_CONTROL_TRANS0 = 0 +DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 +DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' +DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { + 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 1: 'DOUT_I2C_DATA__INDEX_WRITE', +} +DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 +DOUT_I2C_DATA__INDEX_WRITE = 1 +DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', +} +DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', +} +DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 +DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' +DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { + 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', +} +DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 +DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 +DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 +DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 +DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', +} +DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 +DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { + 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', +} +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' +DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { + 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', +} +DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 +DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 +DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_GATING_EN' +CLOCK_GATING_EN__enumvalues = { + 0: 'CLOCK_GATING_ENABLE', + 1: 'CLOCK_GATING_DISABLE', +} +CLOCK_GATING_ENABLE = 0 +CLOCK_GATING_DISABLE = 1 +CLOCK_GATING_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DAC_MUX_SELECT' +DAC_MUX_SELECT__enumvalues = { + 0: 'DAC_MUX_SELECT_DACA', + 1: 'DAC_MUX_SELECT_DACB', +} +DAC_MUX_SELECT_DACA = 0 +DAC_MUX_SELECT_DACB = 1 +DAC_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_DIS_CTRL' +DIOMEM_PWR_DIS_CTRL__enumvalues = { + 0: 'DIOMEM_ENABLE_MEM_PWR_CTRL', + 1: 'DIOMEM_DISABLE_MEM_PWR_CTRL', +} +DIOMEM_ENABLE_MEM_PWR_CTRL = 0 +DIOMEM_DISABLE_MEM_PWR_CTRL = 1 +DIOMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_FORCE_CTRL' +DIOMEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'DIOMEM_NO_FORCE_REQUEST', + 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', +} +DIOMEM_NO_FORCE_REQUEST = 0 +DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 2 +DIOMEM_FORCE_SHUT_DOWN_REQUEST = 3 +DIOMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_FORCE_CTRL2' +DIOMEM_PWR_FORCE_CTRL2__enumvalues = { + 0: 'DIOMEM_NO_FORCE_REQ', + 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', +} +DIOMEM_NO_FORCE_REQ = 0 +DIOMEM_FORCE_LIGHT_SLEEP_REQ = 1 +DIOMEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_SEL_CTRL' +DIOMEM_PWR_SEL_CTRL__enumvalues = { + 0: 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', + 1: 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', + 2: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', +} +DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0 +DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 1 +DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 2 +DIOMEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_SEL_CTRL2' +DIOMEM_PWR_SEL_CTRL2__enumvalues = { + 0: 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', + 1: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', +} +DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0 +DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 1 +DIOMEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_DBG_BLOCK_SEL' +DIO_DBG_BLOCK_SEL__enumvalues = { + 0: 'DIO_DBG_BLOCK_SEL_DIO', + 11: 'DIO_DBG_BLOCK_SEL_DIGFE_A', + 12: 'DIO_DBG_BLOCK_SEL_DIGFE_B', + 13: 'DIO_DBG_BLOCK_SEL_DIGFE_C', + 14: 'DIO_DBG_BLOCK_SEL_DIGFE_D', + 15: 'DIO_DBG_BLOCK_SEL_DIGFE_E', + 18: 'DIO_DBG_BLOCK_SEL_DIGA', + 19: 'DIO_DBG_BLOCK_SEL_DIGB', + 20: 'DIO_DBG_BLOCK_SEL_DIGC', + 21: 'DIO_DBG_BLOCK_SEL_DIGD', + 22: 'DIO_DBG_BLOCK_SEL_DIGE', + 25: 'DIO_DBG_BLOCK_SEL_DPFE_A', + 26: 'DIO_DBG_BLOCK_SEL_DPFE_B', + 27: 'DIO_DBG_BLOCK_SEL_DPFE_C', + 28: 'DIO_DBG_BLOCK_SEL_DPFE_D', + 29: 'DIO_DBG_BLOCK_SEL_DPFE_E', + 32: 'DIO_DBG_BLOCK_SEL_DPA', + 33: 'DIO_DBG_BLOCK_SEL_DPB', + 34: 'DIO_DBG_BLOCK_SEL_DPC', + 35: 'DIO_DBG_BLOCK_SEL_DPD', + 36: 'DIO_DBG_BLOCK_SEL_DPE', + 39: 'DIO_DBG_BLOCK_SEL_AUX0', + 40: 'DIO_DBG_BLOCK_SEL_AUX1', + 41: 'DIO_DBG_BLOCK_SEL_AUX2', + 42: 'DIO_DBG_BLOCK_SEL_AUX3', + 43: 'DIO_DBG_BLOCK_SEL_AUX4', + 45: 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', + 46: 'DIO_DBG_BLOCK_SEL_RESERVED', +} +DIO_DBG_BLOCK_SEL_DIO = 0 +DIO_DBG_BLOCK_SEL_DIGFE_A = 11 +DIO_DBG_BLOCK_SEL_DIGFE_B = 12 +DIO_DBG_BLOCK_SEL_DIGFE_C = 13 +DIO_DBG_BLOCK_SEL_DIGFE_D = 14 +DIO_DBG_BLOCK_SEL_DIGFE_E = 15 +DIO_DBG_BLOCK_SEL_DIGA = 18 +DIO_DBG_BLOCK_SEL_DIGB = 19 +DIO_DBG_BLOCK_SEL_DIGC = 20 +DIO_DBG_BLOCK_SEL_DIGD = 21 +DIO_DBG_BLOCK_SEL_DIGE = 22 +DIO_DBG_BLOCK_SEL_DPFE_A = 25 +DIO_DBG_BLOCK_SEL_DPFE_B = 26 +DIO_DBG_BLOCK_SEL_DPFE_C = 27 +DIO_DBG_BLOCK_SEL_DPFE_D = 28 +DIO_DBG_BLOCK_SEL_DPFE_E = 29 +DIO_DBG_BLOCK_SEL_DPA = 32 +DIO_DBG_BLOCK_SEL_DPB = 33 +DIO_DBG_BLOCK_SEL_DPC = 34 +DIO_DBG_BLOCK_SEL_DPD = 35 +DIO_DBG_BLOCK_SEL_DPE = 36 +DIO_DBG_BLOCK_SEL_AUX0 = 39 +DIO_DBG_BLOCK_SEL_AUX1 = 40 +DIO_DBG_BLOCK_SEL_AUX2 = 41 +DIO_DBG_BLOCK_SEL_AUX3 = 42 +DIO_DBG_BLOCK_SEL_AUX4 = 43 +DIO_DBG_BLOCK_SEL_PERFMON_DIO = 45 +DIO_DBG_BLOCK_SEL_RESERVED = 46 +DIO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE' +DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { + 0: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 1: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', +} +DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 +DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 +DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE' +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE__enumvalues = { + 0: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', + 1: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', +} +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0 +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 1 +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DIO_DCN_ACTIVE_STATUS' +ENUM_DIO_DCN_ACTIVE_STATUS__enumvalues = { + 0: 'ENUM_DCN_NOT_ACTIVE', + 1: 'ENUM_DCN_ACTIVE', +} +ENUM_DCN_NOT_ACTIVE = 0 +ENUM_DCN_ACTIVE = 1 +ENUM_DIO_DCN_ACTIVE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_STEREOSYNC_SEL' +GENERIC_STEREOSYNC_SEL__enumvalues = { + 0: 'GENERIC_STEREOSYNC_SEL_D1', + 1: 'GENERIC_STEREOSYNC_SEL_D2', + 2: 'GENERIC_STEREOSYNC_SEL_D3', + 3: 'GENERIC_STEREOSYNC_SEL_D4', + 4: 'GENERIC_STEREOSYNC_SEL_RESERVED', +} +GENERIC_STEREOSYNC_SEL_D1 = 0 +GENERIC_STEREOSYNC_SEL_D2 = 1 +GENERIC_STEREOSYNC_SEL_D3 = 2 +GENERIC_STEREOSYNC_SEL_D4 = 3 +GENERIC_STEREOSYNC_SEL_RESERVED = 4 +GENERIC_STEREOSYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PM_ASSERT_RESET' +PM_ASSERT_RESET__enumvalues = { + 0: 'PM_ASSERT_RESET_0', + 1: 'PM_ASSERT_RESET_1', +} +PM_ASSERT_RESET_0 = 0 +PM_ASSERT_RESET_1 = 1 +PM_ASSERT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'SOFT_RESET' +SOFT_RESET__enumvalues = { + 0: 'SOFT_RESET_0', + 1: 'SOFT_RESET_1', +} +SOFT_RESET_0 = 0 +SOFT_RESET_1 = 1 +SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_MUX_SELECT' +TMDS_MUX_SELECT__enumvalues = { + 0: 'TMDS_MUX_SELECT_B', + 1: 'TMDS_MUX_SELECT_G', + 2: 'TMDS_MUX_SELECT_R', + 3: 'TMDS_MUX_SELECT_RESERVED', +} +TMDS_MUX_SELECT_B = 0 +TMDS_MUX_SELECT_G = 1 +TMDS_MUX_SELECT_R = 2 +TMDS_MUX_SELECT_RESERVED = 3 +TMDS_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DME_MEM_POWER_STATE_ENUM' +DME_MEM_POWER_STATE_ENUM__enumvalues = { + 0: 'DME_MEM_POWER_STATE_ENUM_ON', + 1: 'DME_MEM_POWER_STATE_ENUM_LS', + 2: 'DME_MEM_POWER_STATE_ENUM_DS', + 3: 'DME_MEM_POWER_STATE_ENUM_SD', +} +DME_MEM_POWER_STATE_ENUM_ON = 0 +DME_MEM_POWER_STATE_ENUM_LS = 1 +DME_MEM_POWER_STATE_ENUM_DS = 2 +DME_MEM_POWER_STATE_ENUM_SD = 3 +DME_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DME_MEM_PWR_DIS_CTRL' +DME_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'DME_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'DME_MEM_DISABLE_MEM_PWR_CTRL', +} +DME_MEM_ENABLE_MEM_PWR_CTRL = 0 +DME_MEM_DISABLE_MEM_PWR_CTRL = 1 +DME_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DME_MEM_PWR_FORCE_CTRL' +DME_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'DME_MEM_NO_FORCE_REQUEST', + 1: 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', +} +DME_MEM_NO_FORCE_REQUEST = 0 +DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 +DME_MEM_FORCE_SHUT_DOWN_REQUEST = 3 +DME_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'METADATA_HUBP_SEL' +METADATA_HUBP_SEL__enumvalues = { + 0: 'METADATA_HUBP_SEL_0', + 1: 'METADATA_HUBP_SEL_1', + 2: 'METADATA_HUBP_SEL_2', + 3: 'METADATA_HUBP_SEL_3', + 4: 'METADATA_HUBP_SEL_RESERVED', +} +METADATA_HUBP_SEL_0 = 0 +METADATA_HUBP_SEL_1 = 1 +METADATA_HUBP_SEL_2 = 2 +METADATA_HUBP_SEL_3 = 3 +METADATA_HUBP_SEL_RESERVED = 4 +METADATA_HUBP_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'METADATA_STREAM_TYPE_SEL' +METADATA_STREAM_TYPE_SEL__enumvalues = { + 0: 'METADATA_STREAM_DP', + 1: 'METADATA_STREAM_DVE', +} +METADATA_STREAM_DP = 0 +METADATA_STREAM_DVE = 1 +METADATA_STREAM_TYPE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VPG_MEM_PWR_DIS_CTRL' +VPG_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'VPG_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'VPG_MEM_DISABLE_MEM_PWR_CTRL', +} +VPG_MEM_ENABLE_MEM_PWR_CTRL = 0 +VPG_MEM_DISABLE_MEM_PWR_CTRL = 1 +VPG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'VPG_MEM_PWR_FORCE_CTRL' +VPG_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'VPG_MEM_NO_FORCE_REQ', + 1: 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', +} +VPG_MEM_NO_FORCE_REQ = 0 +VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 1 +VPG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_ACP_TYPE' +AFMT_ACP_TYPE__enumvalues = { + 0: 'ACP_TYPE_GENERIC_AUDIO', + 1: 'ACP_TYPE_ICE60958_AUDIO', + 2: 'ACP_TYPE_DVD_AUDIO', + 3: 'ACP_TYPE_SUPER_AUDIO_CD', +} +ACP_TYPE_GENERIC_AUDIO = 0 +ACP_TYPE_ICE60958_AUDIO = 1 +ACP_TYPE_DVD_AUDIO = 2 +ACP_TYPE_SUPER_AUDIO_CD = 3 +AFMT_ACP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' +AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { + 0: 'AFMT_AUDIO_CRC_CH0_SIG', + 1: 'AFMT_AUDIO_CRC_CH1_SIG', + 2: 'AFMT_AUDIO_CRC_CH2_SIG', + 3: 'AFMT_AUDIO_CRC_CH3_SIG', + 4: 'AFMT_AUDIO_CRC_CH4_SIG', + 5: 'AFMT_AUDIO_CRC_CH5_SIG', + 6: 'AFMT_AUDIO_CRC_CH6_SIG', + 7: 'AFMT_AUDIO_CRC_CH7_SIG', + 8: 'AFMT_AUDIO_CRC_RESERVED_8', + 9: 'AFMT_AUDIO_CRC_RESERVED_9', + 10: 'AFMT_AUDIO_CRC_RESERVED_10', + 11: 'AFMT_AUDIO_CRC_RESERVED_11', + 12: 'AFMT_AUDIO_CRC_RESERVED_12', + 13: 'AFMT_AUDIO_CRC_RESERVED_13', + 14: 'AFMT_AUDIO_CRC_RESERVED_14', + 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', +} +AFMT_AUDIO_CRC_CH0_SIG = 0 +AFMT_AUDIO_CRC_CH1_SIG = 1 +AFMT_AUDIO_CRC_CH2_SIG = 2 +AFMT_AUDIO_CRC_CH3_SIG = 3 +AFMT_AUDIO_CRC_CH4_SIG = 4 +AFMT_AUDIO_CRC_CH5_SIG = 5 +AFMT_AUDIO_CRC_CH6_SIG = 6 +AFMT_AUDIO_CRC_CH7_SIG = 7 +AFMT_AUDIO_CRC_RESERVED_8 = 8 +AFMT_AUDIO_CRC_RESERVED_9 = 9 +AFMT_AUDIO_CRC_RESERVED_10 = 10 +AFMT_AUDIO_CRC_RESERVED_11 = 11 +AFMT_AUDIO_CRC_RESERVED_12 = 12 +AFMT_AUDIO_CRC_RESERVED_13 = 13 +AFMT_AUDIO_CRC_RESERVED_14 = 14 +AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 +AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' +AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { + 0: 'AFMT_AUDIO_CRC_ONESHOT', + 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', +} +AFMT_AUDIO_CRC_ONESHOT = 0 +AFMT_AUDIO_CRC_AUTO_RESTART = 1 +AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' +AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { + 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', +} +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 +AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { + 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', +} +AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 +AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { + 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', +} +AFMT_AUDIO_PACKET_SENT_DISABLED = 0 +AFMT_AUDIO_PACKET_SENT_ENABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { + 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', +} +AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 +AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' +AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { + 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', +} +AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 +AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 +AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 +AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 +AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 +AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 +AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS' +AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { + 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', +} +HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 +HDMI_SEND_MAX_AUDIO_PACKETS = 1 +AFMT_HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { + 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', +} +AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 +AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' +AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { + 0: 'AFMT_INTERRUPT_DISABLE', + 1: 'AFMT_INTERRUPT_ENABLE', +} +AFMT_INTERRUPT_DISABLE = 0 +AFMT_INTERRUPT_ENABLE = 1 +AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_MEM_PWR_DIS_CTRL' +AFMT_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', +} +AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0 +AFMT_MEM_DISABLE_MEM_PWR_CTRL = 1 +AFMT_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_MEM_PWR_FORCE_CTRL' +AFMT_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'AFMT_MEM_NO_FORCE_REQUEST', + 1: 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', +} +AFMT_MEM_NO_FORCE_REQUEST = 0 +AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 +AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 3 +AFMT_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' +AFMT_RAMP_CONTROL0_SIGN__enumvalues = { + 0: 'AFMT_RAMP_SIGNED', + 1: 'AFMT_RAMP_UNSIGNED', +} +AFMT_RAMP_SIGNED = 0 +AFMT_RAMP_UNSIGNED = 1 +AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE' +AFMT_VBI_PACKET_CONTROL_ACP_SOURCE__enumvalues = { + 0: 'AFMT_ACP_SOURCE_FROM_AZALIA', + 1: 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', +} +AFMT_ACP_SOURCE_FROM_AZALIA = 0 +AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 1 +AFMT_VBI_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AUDIO_LAYOUT_SELECT' +AUDIO_LAYOUT_SELECT__enumvalues = { + 0: 'AUDIO_LAYOUT_0', + 1: 'AUDIO_LAYOUT_1', +} +AUDIO_LAYOUT_0 = 0 +AUDIO_LAYOUT_1 = 1 +AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HPO_TOP_CLOCK_GATING_DISABLE' +HPO_TOP_CLOCK_GATING_DISABLE__enumvalues = { + 0: 'HPO_TOP_CLOCK_GATING_EN', + 1: 'HPO_TOP_CLOCK_GATING_DIS', +} +HPO_TOP_CLOCK_GATING_EN = 0 +HPO_TOP_CLOCK_GATING_DIS = 1 +HPO_TOP_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HPO_TOP_TEST_CLK_SEL' +HPO_TOP_TEST_CLK_SEL__enumvalues = { + 0: 'HPO_TOP_PERMANENT_DISPCLK', + 1: 'HPO_TOP_REGISTER_GATED_DISPCLK', + 2: 'HPO_TOP_PERMANENT_SOCCLK', + 3: 'HPO_TOP_TEST_CLOCK_RESERVED', + 4: 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', + 5: 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', + 6: 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', + 7: 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', + 8: 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', + 9: 'HPO_TOP_PERMANENT_HDMICHARCLK0', + 10: 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', + 11: 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', +} +HPO_TOP_PERMANENT_DISPCLK = 0 +HPO_TOP_REGISTER_GATED_DISPCLK = 1 +HPO_TOP_PERMANENT_SOCCLK = 2 +HPO_TOP_TEST_CLOCK_RESERVED = 3 +HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 4 +HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 5 +HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 6 +HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 7 +HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 8 +HPO_TOP_PERMANENT_HDMICHARCLK0 = 9 +HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 10 +HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 11 +HPO_TOP_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET' +DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET__enumvalues = { + 0: 'DP_STREAM_MAPPER_LINK0', + 1: 'DP_STREAM_MAPPER_LINK1', + 2: 'DP_STREAM_MAPPER_RESERVED', +} +DP_STREAM_MAPPER_LINK0 = 0 +DP_STREAM_MAPPER_LINK1 = 1 +DP_STREAM_MAPPER_RESERVED = 2 +DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_DB_DISABLE_CONTROL' +HDMI_STREAM_ENC_DB_DISABLE_CONTROL__enumvalues = { + 0: 'HDMI_STREAM_ENC_DB_ENABLE', + 1: 'HDMI_STREAM_ENC_DB_DISABLE', +} +HDMI_STREAM_ENC_DB_ENABLE = 0 +HDMI_STREAM_ENC_DB_DISABLE = 1 +HDMI_STREAM_ENC_DB_DISABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_DSC_MODE' +HDMI_STREAM_ENC_DSC_MODE__enumvalues = { + 0: 'STREAM_DSC_DISABLE', + 1: 'STREAM_DSC_444_RGB', + 2: 'STREAM_DSC_NATIVE_422_420', +} +STREAM_DSC_DISABLE = 0 +STREAM_DSC_444_RGB = 1 +STREAM_DSC_NATIVE_422_420 = 2 +HDMI_STREAM_ENC_DSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_ENABLE_CONTROL' +HDMI_STREAM_ENC_ENABLE_CONTROL__enumvalues = { + 0: 'HDMI_STREAM_ENC_DISABLE', + 1: 'HDMI_STREAM_ENC_ENABLE', +} +HDMI_STREAM_ENC_DISABLE = 0 +HDMI_STREAM_ENC_ENABLE = 1 +HDMI_STREAM_ENC_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_ODM_COMBINE_MODE' +HDMI_STREAM_ENC_ODM_COMBINE_MODE__enumvalues = { + 0: 'STREAM_ODM_COMBINE_1_SEGMENT', + 1: 'STREAM_ODM_COMBINE_2_SEGMENT', + 2: 'STREAM_ODM_COMBINE_RESERVED', + 3: 'STREAM_ODM_COMBINE_4_SEGMENT', +} +STREAM_ODM_COMBINE_1_SEGMENT = 0 +STREAM_ODM_COMBINE_2_SEGMENT = 1 +STREAM_ODM_COMBINE_RESERVED = 2 +STREAM_ODM_COMBINE_4_SEGMENT = 3 +HDMI_STREAM_ENC_ODM_COMBINE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR' +HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { + 0: 'HDMI_STREAM_ENC_NO_ERROR_OCCURRED', + 1: 'HDMI_STREAM_ENC_UNDERFLOW_OCCURRED', + 2: 'HDMI_STREAM_ENC_OVERFLOW_OCCURRED', +} +HDMI_STREAM_ENC_NO_ERROR_OCCURRED = 0 +HDMI_STREAM_ENC_UNDERFLOW_OCCURRED = 1 +HDMI_STREAM_ENC_OVERFLOW_OCCURRED = 2 +HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT' +HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = { + 0: 'HDMI_STREAM_ENC_HARDWARE', + 1: 'HDMI_STREAM_ENC_PROGRAMMABLE', +} +HDMI_STREAM_ENC_HARDWARE = 0 +HDMI_STREAM_ENC_PROGRAMMABLE = 1 +HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_PIXEL_ENCODING' +HDMI_STREAM_ENC_PIXEL_ENCODING__enumvalues = { + 0: 'STREAM_PIXEL_ENCODING_444_RGB', + 1: 'STREAM_PIXEL_ENCODING_422', + 2: 'STREAM_PIXEL_ENCODING_420', +} +STREAM_PIXEL_ENCODING_444_RGB = 0 +STREAM_PIXEL_ENCODING_422 = 1 +STREAM_PIXEL_ENCODING_420 = 2 +HDMI_STREAM_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_READ_CLOCK_CONTROL' +HDMI_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = { + 0: 'HDMI_STREAM_ENC_DCCG', + 1: 'HDMI_STREAM_ENC_DISPLAY_PIPE', +} +HDMI_STREAM_ENC_DCCG = 0 +HDMI_STREAM_ENC_DISPLAY_PIPE = 1 +HDMI_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_RESET_CONTROL' +HDMI_STREAM_ENC_RESET_CONTROL__enumvalues = { + 0: 'HDMI_STREAM_ENC_NOT_RESET', + 1: 'HDMI_STREAM_ENC_RESET', +} +HDMI_STREAM_ENC_NOT_RESET = 0 +HDMI_STREAM_ENC_RESET = 1 +HDMI_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_STREAM_ACTIVE' +HDMI_STREAM_ENC_STREAM_ACTIVE__enumvalues = { + 0: 'HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', + 1: 'HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE', +} +HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0 +HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1 +HDMI_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'BORROWBUFFER_MEM_POWER_STATE_ENUM' +BORROWBUFFER_MEM_POWER_STATE_ENUM__enumvalues = { + 0: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_ON', + 1: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_LS', + 2: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_DS', + 3: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_SD', +} +BORROWBUFFER_MEM_POWER_STATE_ENUM_ON = 0 +BORROWBUFFER_MEM_POWER_STATE_ENUM_LS = 1 +BORROWBUFFER_MEM_POWER_STATE_ENUM_DS = 2 +BORROWBUFFER_MEM_POWER_STATE_ENUM_SD = 3 +BORROWBUFFER_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_BORROW_MODE' +HDMI_BORROW_MODE__enumvalues = { + 0: 'TB_BORROW_MODE_NONE', + 1: 'TB_BORROW_MODE_ACTIVE', + 2: 'TB_BORROW_MODE_BLANK', + 3: 'TB_BORROW_MODE_RESERVED', +} +TB_BORROW_MODE_NONE = 0 +TB_BORROW_MODE_ACTIVE = 1 +TB_BORROW_MODE_BLANK = 2 +TB_BORROW_MODE_RESERVED = 3 +HDMI_BORROW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACP_SEND' +HDMI_TB_ENC_ACP_SEND__enumvalues = { + 0: 'TB_ACP_NOT_SEND', + 1: 'TB_ACP_PKT_SEND', +} +TB_ACP_NOT_SEND = 0 +TB_ACP_PKT_SEND = 1 +HDMI_TB_ENC_ACP_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_AUDIO_PRIORITY' +HDMI_TB_ENC_ACR_AUDIO_PRIORITY__enumvalues = { + 0: 'TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 1: 'TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', +} +TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 +TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 +HDMI_TB_ENC_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_CONT' +HDMI_TB_ENC_ACR_CONT__enumvalues = { + 0: 'TB_ACR_CONT_DISABLE', + 1: 'TB_ACR_CONT_ENABLE', +} +TB_ACR_CONT_DISABLE = 0 +TB_ACR_CONT_ENABLE = 1 +HDMI_TB_ENC_ACR_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_N_MULTIPLE' +HDMI_TB_ENC_ACR_N_MULTIPLE__enumvalues = { + 0: 'TB_ACR_0_MULTIPLE_RESERVED', + 1: 'TB_ACR_1_MULTIPLE', + 2: 'TB_ACR_2_MULTIPLE', + 3: 'TB_ACR_3_MULTIPLE_RESERVED', + 4: 'TB_ACR_4_MULTIPLE', + 5: 'TB_ACR_5_MULTIPLE_RESERVED', + 6: 'TB_ACR_6_MULTIPLE_RESERVED', + 7: 'TB_ACR_7_MULTIPLE_RESERVED', +} +TB_ACR_0_MULTIPLE_RESERVED = 0 +TB_ACR_1_MULTIPLE = 1 +TB_ACR_2_MULTIPLE = 2 +TB_ACR_3_MULTIPLE_RESERVED = 3 +TB_ACR_4_MULTIPLE = 4 +TB_ACR_5_MULTIPLE_RESERVED = 5 +TB_ACR_6_MULTIPLE_RESERVED = 6 +TB_ACR_7_MULTIPLE_RESERVED = 7 +HDMI_TB_ENC_ACR_N_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_SELECT' +HDMI_TB_ENC_ACR_SELECT__enumvalues = { + 0: 'TB_ACR_SELECT_HW', + 1: 'TB_ACR_SELECT_32K', + 2: 'TB_ACR_SELECT_44K', + 3: 'TB_ACR_SELECT_48K', +} +TB_ACR_SELECT_HW = 0 +TB_ACR_SELECT_32K = 1 +TB_ACR_SELECT_44K = 2 +TB_ACR_SELECT_48K = 3 +HDMI_TB_ENC_ACR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_SEND' +HDMI_TB_ENC_ACR_SEND__enumvalues = { + 0: 'TB_ACR_NOT_SEND', + 1: 'TB_ACR_PKT_SEND', +} +TB_ACR_NOT_SEND = 0 +TB_ACR_PKT_SEND = 1 +HDMI_TB_ENC_ACR_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_SOURCE' +HDMI_TB_ENC_ACR_SOURCE__enumvalues = { + 0: 'TB_ACR_SOURCE_HW', + 1: 'TB_ACR_SOURCE_SW', +} +TB_ACR_SOURCE_HW = 0 +TB_ACR_SOURCE_SW = 1 +HDMI_TB_ENC_ACR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_AUDIO_INFO_CONT' +HDMI_TB_ENC_AUDIO_INFO_CONT__enumvalues = { + 0: 'TB_AUDIO_INFO_CONT_DISABLE', + 1: 'TB_AUDIO_INFO_CONT_ENABLE', +} +TB_AUDIO_INFO_CONT_DISABLE = 0 +TB_AUDIO_INFO_CONT_ENABLE = 1 +HDMI_TB_ENC_AUDIO_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_AUDIO_INFO_SEND' +HDMI_TB_ENC_AUDIO_INFO_SEND__enumvalues = { + 0: 'TB_AUDIO_INFO_NOT_SEND', + 1: 'TB_AUDIO_INFO_PKT_SEND', +} +TB_AUDIO_INFO_NOT_SEND = 0 +TB_AUDIO_INFO_PKT_SEND = 1 +HDMI_TB_ENC_AUDIO_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_CRC_SRC_SEL' +HDMI_TB_ENC_CRC_SRC_SEL__enumvalues = { + 0: 'TB_CRC_TB_ENC_INPUT', + 1: 'TB_CRC_DSC_PACKER', + 2: 'TB_CRC_DEEP_COLOR_PACKER', + 3: 'TB_CRC_ENCRYPTOR_INPUT', +} +TB_CRC_TB_ENC_INPUT = 0 +TB_CRC_DSC_PACKER = 1 +TB_CRC_DEEP_COLOR_PACKER = 2 +TB_CRC_ENCRYPTOR_INPUT = 3 +HDMI_TB_ENC_CRC_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_CRC_TYPE' +HDMI_TB_ENC_CRC_TYPE__enumvalues = { + 0: 'TB_CRC_ALL_TRIBYTES', + 1: 'TB_CRC_ACTIVE_TRIBYTES', + 2: 'TB_CRC_DATAISLAND_TRIBYTES', + 3: 'TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES', +} +TB_CRC_ALL_TRIBYTES = 0 +TB_CRC_ACTIVE_TRIBYTES = 1 +TB_CRC_DATAISLAND_TRIBYTES = 2 +TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES = 3 +HDMI_TB_ENC_CRC_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_DEEP_COLOR_DEPTH' +HDMI_TB_ENC_DEEP_COLOR_DEPTH__enumvalues = { + 0: 'TB_DEEP_COLOR_DEPTH_24BPP', + 1: 'TB_DEEP_COLOR_DEPTH_30BPP', + 2: 'TB_DEEP_COLOR_DEPTH_36BPP', + 3: 'TB_DEEP_COLOR_DEPTH_RESERVED', +} +TB_DEEP_COLOR_DEPTH_24BPP = 0 +TB_DEEP_COLOR_DEPTH_30BPP = 1 +TB_DEEP_COLOR_DEPTH_36BPP = 2 +TB_DEEP_COLOR_DEPTH_RESERVED = 3 +HDMI_TB_ENC_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_DEFAULT_PAHSE' +HDMI_TB_ENC_DEFAULT_PAHSE__enumvalues = { + 0: 'TB_DEFAULT_PHASE_IS_0', + 1: 'TB_DEFAULT_PHASE_IS_1', +} +TB_DEFAULT_PHASE_IS_0 = 0 +TB_DEFAULT_PHASE_IS_1 = 1 +HDMI_TB_ENC_DEFAULT_PAHSE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_DSC_MODE' +HDMI_TB_ENC_DSC_MODE__enumvalues = { + 0: 'TB_DSC_DISABLE', + 1: 'TB_DSC_444_RGB', + 2: 'TB_DSC_NATIVE_422_420', +} +TB_DSC_DISABLE = 0 +TB_DSC_444_RGB = 1 +TB_DSC_NATIVE_422_420 = 2 +HDMI_TB_ENC_DSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ENABLE' +HDMI_TB_ENC_ENABLE__enumvalues = { + 0: 'TB_DISABLE', + 1: 'TB_ENABLE', +} +TB_DISABLE = 0 +TB_ENABLE = 1 +HDMI_TB_ENC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GC_AVMUTE' +HDMI_TB_ENC_GC_AVMUTE__enumvalues = { + 0: 'TB_GC_AVMUTE_SET', + 1: 'TB_GC_AVMUTE_UNSET', +} +TB_GC_AVMUTE_SET = 0 +TB_GC_AVMUTE_UNSET = 1 +HDMI_TB_ENC_GC_AVMUTE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GC_AVMUTE_CONT' +HDMI_TB_ENC_GC_AVMUTE_CONT__enumvalues = { + 0: 'TB_GC_AVMUTE_CONT_DISABLE', + 1: 'TB_GC_AVMUTE_CONT_ENABLE', +} +TB_GC_AVMUTE_CONT_DISABLE = 0 +TB_GC_AVMUTE_CONT_ENABLE = 1 +HDMI_TB_ENC_GC_AVMUTE_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GC_CONT' +HDMI_TB_ENC_GC_CONT__enumvalues = { + 0: 'TB_GC_CONT_DISABLE', + 1: 'TB_GC_CONT_ENABLE', +} +TB_GC_CONT_DISABLE = 0 +TB_GC_CONT_ENABLE = 1 +HDMI_TB_ENC_GC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GC_SEND' +HDMI_TB_ENC_GC_SEND__enumvalues = { + 0: 'TB_GC_NOT_SEND', + 1: 'TB_GC_PKT_SEND', +} +TB_GC_NOT_SEND = 0 +TB_GC_PKT_SEND = 1 +HDMI_TB_ENC_GC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GENERIC_CONT' +HDMI_TB_ENC_GENERIC_CONT__enumvalues = { + 0: 'TB_GENERIC_CONT_DISABLE', + 1: 'TB_GENERIC_CONT_ENABLE', +} +TB_GENERIC_CONT_DISABLE = 0 +TB_GENERIC_CONT_ENABLE = 1 +HDMI_TB_ENC_GENERIC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GENERIC_LOCK_EN' +HDMI_TB_ENC_GENERIC_LOCK_EN__enumvalues = { + 0: 'HDMI_TB_ENC_GENERIC_LOCK_DISABLE', + 1: 'HDMI_TB_ENC_GENERIC_LOCK_ENABLE', +} +HDMI_TB_ENC_GENERIC_LOCK_DISABLE = 0 +HDMI_TB_ENC_GENERIC_LOCK_ENABLE = 1 +HDMI_TB_ENC_GENERIC_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GENERIC_SEND' +HDMI_TB_ENC_GENERIC_SEND__enumvalues = { + 0: 'TB_GENERIC_NOT_SEND', + 1: 'TB_GENERIC_PKT_SEND', +} +TB_GENERIC_NOT_SEND = 0 +TB_GENERIC_PKT_SEND = 1 +HDMI_TB_ENC_GENERIC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ISRC_CONT' +HDMI_TB_ENC_ISRC_CONT__enumvalues = { + 0: 'TB_ISRC_CONT_DISABLE', + 1: 'TB_ISRC_CONT_ENABLE', +} +TB_ISRC_CONT_DISABLE = 0 +TB_ISRC_CONT_ENABLE = 1 +HDMI_TB_ENC_ISRC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ISRC_SEND' +HDMI_TB_ENC_ISRC_SEND__enumvalues = { + 0: 'TB_ISRC_NOT_SEND', + 1: 'TB_ISRC_PKT_SEND', +} +TB_ISRC_NOT_SEND = 0 +TB_ISRC_PKT_SEND = 1 +HDMI_TB_ENC_ISRC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_METADATA_ENABLE' +HDMI_TB_ENC_METADATA_ENABLE__enumvalues = { + 0: 'TB_METADATA_NOT_SEND', + 1: 'TB_METADATA_PKT_SEND', +} +TB_METADATA_NOT_SEND = 0 +TB_METADATA_PKT_SEND = 1 +HDMI_TB_ENC_METADATA_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_PACKET_LINE_REFERENCE' +HDMI_TB_ENC_PACKET_LINE_REFERENCE__enumvalues = { + 0: 'TB_PKT_LINE_REF_END_OF_ACTIVE', + 1: 'TB_PKT_LINE_REF_OTGSOF', +} +TB_PKT_LINE_REF_END_OF_ACTIVE = 0 +TB_PKT_LINE_REF_OTGSOF = 1 +HDMI_TB_ENC_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_PIXEL_ENCODING' +HDMI_TB_ENC_PIXEL_ENCODING__enumvalues = { + 0: 'TB_PIXEL_ENCODING_444_RGB', + 1: 'TB_PIXEL_ENCODING_422', + 2: 'TB_PIXEL_ENCODING_420', +} +TB_PIXEL_ENCODING_444_RGB = 0 +TB_PIXEL_ENCODING_422 = 1 +TB_PIXEL_ENCODING_420 = 2 +HDMI_TB_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_RESET' +HDMI_TB_ENC_RESET__enumvalues = { + 0: 'TB_NOT_RESET', + 1: 'TB_RESET', +} +TB_NOT_RESET = 0 +TB_RESET = 1 +HDMI_TB_ENC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_SYNC_PHASE' +HDMI_TB_ENC_SYNC_PHASE__enumvalues = { + 0: 'TB_NOT_SYNC_PHASE_ON_FRAME_START', + 1: 'TB_SYNC_PHASE_ON_FRAME_START', +} +TB_NOT_SYNC_PHASE_ON_FRAME_START = 0 +TB_SYNC_PHASE_ON_FRAME_START = 1 +HDMI_TB_ENC_SYNC_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'INPUT_FIFO_ERROR_TYPE' +INPUT_FIFO_ERROR_TYPE__enumvalues = { + 0: 'TB_NO_ERROR_OCCURRED', + 1: 'TB_OVERFLOW_OCCURRED', +} +TB_NO_ERROR_OCCURRED = 0 +TB_OVERFLOW_OCCURRED = 1 +INPUT_FIFO_ERROR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR' +DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { + 0: 'DP_STREAM_ENC_NO_ERROR_OCCURRED', + 1: 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', + 2: 'DP_STREAM_ENC_OVERFLOW_OCCURRED', +} +DP_STREAM_ENC_NO_ERROR_OCCURRED = 0 +DP_STREAM_ENC_UNDERFLOW_OCCURRED = 1 +DP_STREAM_ENC_OVERFLOW_OCCURRED = 2 +DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT' +DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = { + 0: 'DP_STREAM_ENC_HARDWARE', + 1: 'DP_STREAM_ENC_PROGRAMMABLE', +} +DP_STREAM_ENC_HARDWARE = 0 +DP_STREAM_ENC_PROGRAMMABLE = 1 +DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_READ_CLOCK_CONTROL' +DP_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = { + 0: 'DP_STREAM_ENC_DCCG', + 1: 'DP_STREAM_ENC_DISPLAY_PIPE', +} +DP_STREAM_ENC_DCCG = 0 +DP_STREAM_ENC_DISPLAY_PIPE = 1 +DP_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_RESET_CONTROL' +DP_STREAM_ENC_RESET_CONTROL__enumvalues = { + 0: 'DP_STREAM_ENC_NOT_RESET', + 1: 'DP_STREAM_ENC_RESET', +} +DP_STREAM_ENC_NOT_RESET = 0 +DP_STREAM_ENC_RESET = 1 +DP_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_STREAM_ACTIVE' +DP_STREAM_ENC_STREAM_ACTIVE__enumvalues = { + 0: 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', + 1: 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', +} +DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0 +DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1 +DP_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_AUDIO_MUTE' +ENUM_DP_SYM32_ENC_AUDIO_MUTE__enumvalues = { + 0: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', + 1: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', +} +DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0 +DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 1 +ENUM_DP_SYM32_ENC_AUDIO_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE' +ENUM_DP_SYM32_ENC_CONTINUOUS_MODE__enumvalues = { + 0: 'DP_SYM32_ENC_ONE_SHOT_MODE', + 1: 'DP_SYM32_ENC_CONTINUOUS_MODE', +} +DP_SYM32_ENC_ONE_SHOT_MODE = 0 +DP_SYM32_ENC_CONTINUOUS_MODE = 1 +ENUM_DP_SYM32_ENC_CONTINUOUS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_CRC_VALID' +ENUM_DP_SYM32_ENC_CRC_VALID__enumvalues = { + 0: 'DP_SYM32_ENC_CRC_NOT_VALID', + 1: 'DP_SYM32_ENC_CRC_VALID', +} +DP_SYM32_ENC_CRC_NOT_VALID = 0 +DP_SYM32_ENC_CRC_VALID = 1 +ENUM_DP_SYM32_ENC_CRC_VALID = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH' +ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH__enumvalues = { + 0: 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', + 1: 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', + 2: 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', + 3: 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', +} +DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0 +DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 1 +DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 2 +DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 3 +ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_ENABLE' +ENUM_DP_SYM32_ENC_ENABLE__enumvalues = { + 0: 'DP_SYM32_ENC_DISABLE', + 1: 'DP_SYM32_ENC_ENABLE', +} +DP_SYM32_ENC_DISABLE = 0 +DP_SYM32_ENC_ENABLE = 1 +ENUM_DP_SYM32_ENC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED' +ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', + 1: 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', +} +DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0 +DP_SYM32_ENC_GSP_DEADLINE_MISSED = 1 +ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION' +ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', + 1: 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', +} +DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0 +DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 1 +ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE' +ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', + 1: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', + 2: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', + 3: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', +} +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0 +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 1 +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 2 +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 3 +ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING' +ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', + 1: 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', +} +DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0 +DP_SYM32_ENC_GSP_TRIGGER_PENDING = 1 +ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM' +ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', + 1: 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', +} +DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0 +DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 1 +DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 2 +DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 3 +ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS' +ENUM_DP_SYM32_ENC_OVERFLOW_STATUS__enumvalues = { + 0: 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', + 1: 'DP_SYM32_ENC_OVERFLOW_OCCURRED', +} +DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0 +DP_SYM32_ENC_OVERFLOW_OCCURRED = 1 +ENUM_DP_SYM32_ENC_OVERFLOW_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_PENDING' +ENUM_DP_SYM32_ENC_PENDING__enumvalues = { + 0: 'DP_SYM32_ENC_NOT_PENDING', + 1: 'DP_SYM32_ENC_PENDING', +} +DP_SYM32_ENC_NOT_PENDING = 0 +DP_SYM32_ENC_PENDING = 1 +ENUM_DP_SYM32_ENC_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING' +ENUM_DP_SYM32_ENC_PIXEL_ENCODING__enumvalues = { + 0: 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', + 1: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', + 2: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', + 3: 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', +} +DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0 +DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 1 +DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 2 +DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 3 +ENUM_DP_SYM32_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE' +ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE__enumvalues = { + 0: 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', + 1: 'DP_SYM32_ENC_COMPRESSED_FORMAT', +} +DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0 +DP_SYM32_ENC_COMPRESSED_FORMAT = 1 +ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM' +ENUM_DP_SYM32_ENC_POWER_STATE_ENUM__enumvalues = { + 0: 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', + 1: 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', + 2: 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', + 3: 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', +} +DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0 +DP_SYM32_ENC_POWER_STATE_ENUM_LS = 1 +DP_SYM32_ENC_POWER_STATE_ENUM_DS = 2 +DP_SYM32_ENC_POWER_STATE_ENUM_SD = 3 +ENUM_DP_SYM32_ENC_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_RESET' +ENUM_DP_SYM32_ENC_RESET__enumvalues = { + 0: 'DP_SYM32_ENC_NOT_RESET', + 1: 'DP_SYM32_ENC_RESET', +} +DP_SYM32_ENC_NOT_RESET = 0 +DP_SYM32_ENC_RESET = 1 +ENUM_DP_SYM32_ENC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_SDP_PRIORITY' +ENUM_DP_SYM32_ENC_SDP_PRIORITY__enumvalues = { + 0: 'DP_SYM32_ENC_SDP_LOW_PRIORITY', + 1: 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', +} +DP_SYM32_ENC_SDP_LOW_PRIORITY = 0 +DP_SYM32_ENC_SDP_HIGH_PRIORITY = 1 +ENUM_DP_SYM32_ENC_SDP_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_SOF_REFERENCE' +ENUM_DP_SYM32_ENC_SOF_REFERENCE__enumvalues = { + 0: 'DP_SYM32_ENC_DP_SOF', + 1: 'DP_SYM32_ENC_OTG_SOF', +} +DP_SYM32_ENC_DP_SOF = 0 +DP_SYM32_ENC_OTG_SOF = 1 +ENUM_DP_SYM32_ENC_SOF_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER' +ENUM_DP_SYM32_ENC_VID_STREAM_DEFER__enumvalues = { + 0: 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', + 1: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', + 2: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', +} +DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0 +DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 1 +DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 2 +ENUM_DP_SYM32_ENC_VID_STREAM_DEFER = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT' +ENUM_DP_DPHY_SYM32_CRC_END_EVENT__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_END_LLCP', + 1: 'DP_DPHY_SYM32_CRC_END_PS_ONLY', + 2: 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', + 3: 'DP_DPHY_SYM32_CRC_END_PS_ANY', +} +DP_DPHY_SYM32_CRC_END_LLCP = 0 +DP_DPHY_SYM32_CRC_END_PS_ONLY = 1 +DP_DPHY_SYM32_CRC_END_PS_LT_SR = 2 +DP_DPHY_SYM32_CRC_END_PS_ANY = 3 +ENUM_DP_DPHY_SYM32_CRC_END_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT' +ENUM_DP_DPHY_SYM32_CRC_START_EVENT__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_START_LLCP', + 1: 'DP_DPHY_SYM32_CRC_START_PS_ONLY', + 2: 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', + 3: 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', + 4: 'DP_DPHY_SYM32_CRC_START_TP_START', +} +DP_DPHY_SYM32_CRC_START_LLCP = 0 +DP_DPHY_SYM32_CRC_START_PS_ONLY = 1 +DP_DPHY_SYM32_CRC_START_PS_LT_SR = 2 +DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 3 +DP_DPHY_SYM32_CRC_START_TP_START = 4 +ENUM_DP_DPHY_SYM32_CRC_START_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE' +ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', + 1: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', + 2: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', +} +DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0 +DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 1 +DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 2 +ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS' +ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_USE_END_EVENT', + 1: 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', +} +DP_DPHY_SYM32_CRC_USE_END_EVENT = 0 +DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 1 +ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_ENABLE' +ENUM_DP_DPHY_SYM32_ENABLE__enumvalues = { + 0: 'DP_DPHY_SYM32_DISABLE', + 1: 'DP_DPHY_SYM32_ENABLE', +} +DP_DPHY_SYM32_DISABLE = 0 +DP_DPHY_SYM32_ENABLE = 1 +ENUM_DP_DPHY_SYM32_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE' +ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE__enumvalues = { + 0: 'DP_DPHY_SYM32_ENCRYPT_TYPE0', + 1: 'DP_DPHY_SYM32_ENCRYPT_TYPE1', +} +DP_DPHY_SYM32_ENCRYPT_TYPE0 = 0 +DP_DPHY_SYM32_ENCRYPT_TYPE1 = 1 +ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_MODE' +ENUM_DP_DPHY_SYM32_MODE__enumvalues = { + 0: 'DP_DPHY_SYM32_LT_TPS1', + 1: 'DP_DPHY_SYM32_LT_TPS2', + 2: 'DP_DPHY_SYM32_ACTIVE', + 3: 'DP_DPHY_SYM32_TEST', +} +DP_DPHY_SYM32_LT_TPS1 = 0 +DP_DPHY_SYM32_LT_TPS2 = 1 +DP_DPHY_SYM32_ACTIVE = 2 +DP_DPHY_SYM32_TEST = 3 +ENUM_DP_DPHY_SYM32_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_NUM_LANES' +ENUM_DP_DPHY_SYM32_NUM_LANES__enumvalues = { + 0: 'DP_DPHY_SYM32_1LANE', + 1: 'DP_DPHY_SYM32_2LANE', + 2: 'DP_DPHY_SYM32_RESERVED', + 3: 'DP_DPHY_SYM32_4LANE', +} +DP_DPHY_SYM32_1LANE = 0 +DP_DPHY_SYM32_2LANE = 1 +DP_DPHY_SYM32_RESERVED = 2 +DP_DPHY_SYM32_4LANE = 3 +ENUM_DP_DPHY_SYM32_NUM_LANES = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING' +ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING__enumvalues = { + 0: 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', + 1: 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', +} +DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0 +DP_DPHY_SYM32_RATE_UPDATE_PENDING = 1 +ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET' +ENUM_DP_DPHY_SYM32_RESET__enumvalues = { + 0: 'DP_DPHY_SYM32_NOT_RESET', + 1: 'DP_DPHY_SYM32_RESET', +} +DP_DPHY_SYM32_NOT_RESET = 0 +DP_DPHY_SYM32_RESET = 1 +ENUM_DP_DPHY_SYM32_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET_STATUS' +ENUM_DP_DPHY_SYM32_RESET_STATUS__enumvalues = { + 0: 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', + 1: 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', +} +DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0 +DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 1 +ENUM_DP_DPHY_SYM32_RESET_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE' +ENUM_DP_DPHY_SYM32_SAT_UPDATE__enumvalues = { + 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE', + 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', + 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', +} +DP_DPHY_SYM32_SAT_NO_UPDATE = 0 +DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 1 +DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 2 +ENUM_DP_DPHY_SYM32_SAT_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING' +ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING__enumvalues = { + 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', + 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', + 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', +} +DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0 +DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 1 +DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 2 +ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_STATUS' +ENUM_DP_DPHY_SYM32_STATUS__enumvalues = { + 0: 'DP_DPHY_SYM32_STATUS_IDLE', + 1: 'DP_DPHY_SYM32_STATUS_ENABLED', +} +DP_DPHY_SYM32_STATUS_IDLE = 0 +DP_DPHY_SYM32_STATUS_ENABLED = 1 +ENUM_DP_DPHY_SYM32_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE' +ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE__enumvalues = { + 0: 'DP_DPHY_SYM32_STREAM_OVR_NONE', + 1: 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', + 2: 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', +} +DP_DPHY_SYM32_STREAM_OVR_NONE = 0 +DP_DPHY_SYM32_STREAM_OVR_REPLACE = 1 +DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 2 +ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE' +ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE__enumvalues = { + 0: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', + 1: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', +} +DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0 +DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 1 +ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL' +ENUM_DP_DPHY_SYM32_TP_PRBS_SEL__enumvalues = { + 0: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', + 1: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', + 2: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', + 3: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', + 4: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', + 5: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', +} +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 1 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 2 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 3 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 4 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 5 +ENUM_DP_DPHY_SYM32_TP_PRBS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_SELECT' +ENUM_DP_DPHY_SYM32_TP_SELECT__enumvalues = { + 0: 'DP_DPHY_SYM32_TP_SELECT_TPS1', + 1: 'DP_DPHY_SYM32_TP_SELECT_TPS2', + 2: 'DP_DPHY_SYM32_TP_SELECT_PRBS', + 3: 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', + 4: 'DP_DPHY_SYM32_TP_SELECT_SQUARE', +} +DP_DPHY_SYM32_TP_SELECT_TPS1 = 0 +DP_DPHY_SYM32_TP_SELECT_TPS2 = 1 +DP_DPHY_SYM32_TP_SELECT_PRBS = 2 +DP_DPHY_SYM32_TP_SELECT_CUSTOM = 3 +DP_DPHY_SYM32_TP_SELECT_SQUARE = 4 +ENUM_DP_DPHY_SYM32_TP_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'APG_AUDIO_CRC_CONTROL_CH_SEL' +APG_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { + 0: 'APG_AUDIO_CRC_CH0_SIG', + 1: 'APG_AUDIO_CRC_CH1_SIG', + 2: 'APG_AUDIO_CRC_CH2_SIG', + 3: 'APG_AUDIO_CRC_CH3_SIG', + 4: 'APG_AUDIO_CRC_CH4_SIG', + 5: 'APG_AUDIO_CRC_CH5_SIG', + 6: 'APG_AUDIO_CRC_CH6_SIG', + 7: 'APG_AUDIO_CRC_CH7_SIG', + 8: 'APG_AUDIO_CRC_RESERVED_8', + 9: 'APG_AUDIO_CRC_RESERVED_9', + 10: 'APG_AUDIO_CRC_RESERVED_10', + 11: 'APG_AUDIO_CRC_RESERVED_11', + 12: 'APG_AUDIO_CRC_RESERVED_12', + 13: 'APG_AUDIO_CRC_RESERVED_13', + 14: 'APG_AUDIO_CRC_RESERVED_14', + 15: 'APG_AUDIO_CRC_RESERVED_15', +} +APG_AUDIO_CRC_CH0_SIG = 0 +APG_AUDIO_CRC_CH1_SIG = 1 +APG_AUDIO_CRC_CH2_SIG = 2 +APG_AUDIO_CRC_CH3_SIG = 3 +APG_AUDIO_CRC_CH4_SIG = 4 +APG_AUDIO_CRC_CH5_SIG = 5 +APG_AUDIO_CRC_CH6_SIG = 6 +APG_AUDIO_CRC_CH7_SIG = 7 +APG_AUDIO_CRC_RESERVED_8 = 8 +APG_AUDIO_CRC_RESERVED_9 = 9 +APG_AUDIO_CRC_RESERVED_10 = 10 +APG_AUDIO_CRC_RESERVED_11 = 11 +APG_AUDIO_CRC_RESERVED_12 = 12 +APG_AUDIO_CRC_RESERVED_13 = 13 +APG_AUDIO_CRC_RESERVED_14 = 14 +APG_AUDIO_CRC_RESERVED_15 = 15 +APG_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_AUDIO_CRC_CONTROL_CONT' +APG_AUDIO_CRC_CONTROL_CONT__enumvalues = { + 0: 'APG_AUDIO_CRC_ONESHOT', + 1: 'APG_AUDIO_CRC_CONTINUOUS', +} +APG_AUDIO_CRC_ONESHOT = 0 +APG_AUDIO_CRC_CONTINUOUS = 1 +APG_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_ACP_TYPE' +APG_DBG_ACP_TYPE__enumvalues = { + 0: 'APG_ACP_TYPE_GENERIC_AUDIO', + 1: 'APG_ACP_TYPE_ICE60958_AUDIO', + 2: 'APG_ACP_TYPE_DVD_AUDIO', + 3: 'APG_ACP_TYPE_SUPER_AUDIO_CD', +} +APG_ACP_TYPE_GENERIC_AUDIO = 0 +APG_ACP_TYPE_ICE60958_AUDIO = 1 +APG_ACP_TYPE_DVD_AUDIO = 2 +APG_ACP_TYPE_SUPER_AUDIO_CD = 3 +APG_DBG_ACP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_AUDIO_DTO_BASE' +APG_DBG_AUDIO_DTO_BASE__enumvalues = { + 0: 'BASE_RATE_48KHZ', + 1: 'BASE_RATE_44P1KHZ', +} +BASE_RATE_48KHZ = 0 +BASE_RATE_44P1KHZ = 1 +APG_DBG_AUDIO_DTO_BASE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_AUDIO_DTO_DIV' +APG_DBG_AUDIO_DTO_DIV__enumvalues = { + 0: 'DIVISOR_BY1', + 1: 'DIVISOR_BY2_RESERVED', + 2: 'DIVISOR_BY3', + 3: 'DIVISOR_BY4_RESERVED', + 4: 'DIVISOR_BY5_RESERVED', + 5: 'DIVISOR_BY6_RESERVED', + 6: 'DIVISOR_BY7_RESERVED', + 7: 'DIVISOR_BY8_RESERVED', +} +DIVISOR_BY1 = 0 +DIVISOR_BY2_RESERVED = 1 +DIVISOR_BY3 = 2 +DIVISOR_BY4_RESERVED = 3 +DIVISOR_BY5_RESERVED = 4 +DIVISOR_BY6_RESERVED = 5 +DIVISOR_BY7_RESERVED = 6 +DIVISOR_BY8_RESERVED = 7 +APG_DBG_AUDIO_DTO_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_AUDIO_DTO_MULTI' +APG_DBG_AUDIO_DTO_MULTI__enumvalues = { + 0: 'MULTIPLE_BY1', + 1: 'MULTIPLE_BY2', + 2: 'MULTIPLE_BY3_RESERVED', + 3: 'MULTIPLE_BY4', + 4: 'MULTIPLE_RESERVED', +} +MULTIPLE_BY1 = 0 +MULTIPLE_BY2 = 1 +MULTIPLE_BY3_RESERVED = 2 +MULTIPLE_BY4 = 3 +MULTIPLE_RESERVED = 4 +APG_DBG_AUDIO_DTO_MULTI = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_MUX_SEL' +APG_DBG_MUX_SEL__enumvalues = { + 0: 'APG_FUNCTIONAL_MODE', + 1: 'APG_DEBUG_AUDIO_MODE', +} +APG_FUNCTIONAL_MODE = 0 +APG_DEBUG_AUDIO_MODE = 1 +APG_DBG_MUX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE' +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { + 0: 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', + 1: 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', +} +APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0 +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_MEM_POWER_STATE' +APG_MEM_POWER_STATE__enumvalues = { + 0: 'APG_MEM_POWER_STATE_ON', + 1: 'APG_MEM_POWER_STATE_LS', + 2: 'APG_MEM_POWER_STATE_DS', + 3: 'APG_MEM_POWER_STATE_SD', +} +APG_MEM_POWER_STATE_ON = 0 +APG_MEM_POWER_STATE_LS = 1 +APG_MEM_POWER_STATE_DS = 2 +APG_MEM_POWER_STATE_SD = 3 +APG_MEM_POWER_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_MEM_PWR_DIS_CTRL' +APG_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'APG_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'APG_MEM_DISABLE_MEM_PWR_CTRL', +} +APG_MEM_ENABLE_MEM_PWR_CTRL = 0 +APG_MEM_DISABLE_MEM_PWR_CTRL = 1 +APG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_MEM_PWR_FORCE_CTRL' +APG_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'APG_MEM_NO_FORCE_REQUEST', + 1: 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', +} +APG_MEM_NO_FORCE_REQUEST = 0 +APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 +APG_MEM_FORCE_SHUT_DOWN_REQUEST = 3 +APG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_PACKET_CONTROL_ACP_SOURCE' +APG_PACKET_CONTROL_ACP_SOURCE__enumvalues = { + 0: 'APG_ACP_SOURCE_NO_OVERRIDE', + 1: 'APG_ACP_OVERRIDE', +} +APG_ACP_SOURCE_NO_OVERRIDE = 0 +APG_ACP_OVERRIDE = 1 +APG_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE' +APG_PACKET_CONTROL_AUDIO_INFO_SOURCE__enumvalues = { + 0: 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', + 1: 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', +} +APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0 +APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 1 +APG_PACKET_CONTROL_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_RAMP_CONTROL_SIGN' +APG_RAMP_CONTROL_SIGN__enumvalues = { + 0: 'APG_RAMP_SIGNED', + 1: 'APG_RAMP_UNSIGNED', +} +APG_RAMP_SIGNED = 0 +APG_RAMP_UNSIGNED = 1 +APG_RAMP_CONTROL_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', +} +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { + 0: 'DCIO_TEST_CLK_SEL_DISPCLK', + 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', + 2: 'DCIO_TEST_CLK_SEL_SOCCLK', +} +DCIO_TEST_CLK_SEL_DISPCLK = 0 +DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 +DCIO_TEST_CLK_SEL_SOCCLK = 2 +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { + 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', +} +DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 +DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL' +DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = { + 0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', + 1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', + 2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', + 3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', + 4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', + 5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', + 6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', + 7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', +} +DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0 +DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1 +DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2 +DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3 +DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4 +DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5 +DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6 +DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7 +DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL' +DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = { + 0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', + 1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', + 2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', + 3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', +} +DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0 +DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1 +DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2 +DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 3 +DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' +DCIO_DCRXPHY_SOFT_RESET__enumvalues = { + 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', + 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', +} +DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 +DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 +DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICA_SEL' +DCIO_DC_GENERICA_SEL__enumvalues = { + 1: 'DCIO_GENERICA_SEL_STEREOSYNC', + 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', + 11: 'DCIO_GENERICA_SEL_SYNCEN', +} +DCIO_GENERICA_SEL_STEREOSYNC = 1 +DCIO_GENERICA_SEL_GENERICA_DCCG = 10 +DCIO_GENERICA_SEL_SYNCEN = 11 +DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICB_SEL' +DCIO_DC_GENERICB_SEL__enumvalues = { + 1: 'DCIO_GENERICB_SEL_STEREOSYNC', + 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', + 11: 'DCIO_GENERICB_SEL_SYNCEN', +} +DCIO_GENERICB_SEL_STEREOSYNC = 1 +DCIO_GENERICB_SEL_GENERICB_DCCG = 10 +DCIO_GENERICB_SEL_SYNCEN = 11 +DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', +} +DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 +DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 +DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 +DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 +DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 +DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 +DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_CLK', +} +DCIO_UNIPHYA_FBDIV_CLK = 0 +DCIO_UNIPHYB_FBDIV_CLK = 1 +DCIO_UNIPHYC_FBDIV_CLK = 2 +DCIO_UNIPHYD_FBDIV_CLK = 3 +DCIO_UNIPHYE_FBDIV_CLK = 4 +DCIO_UNIPHYF_FBDIV_CLK = 5 +DCIO_UNIPHYG_FBDIV_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', +} +DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 +DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 +DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 +DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 +DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 +DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 +DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', + 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', + 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', + 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', + 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', + 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', + 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', +} +DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 +DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 +DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 +DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 +DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 +DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 +DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE' +DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = { + 0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', + 1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', +} +DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0 +DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1 +DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' +DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { + 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', +} +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 2 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 3 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 4 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 5 +DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' +DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { + 0: 'DCIO_GPU_TIMER_START_0_END_27', + 1: 'DCIO_GPU_TIMER_START_1_END_28', + 2: 'DCIO_GPU_TIMER_START_2_END_29', + 3: 'DCIO_GPU_TIMER_START_3_END_30', + 4: 'DCIO_GPU_TIMER_START_4_END_31', + 5: 'DCIO_GPU_TIMER_START_6_END_33', + 6: 'DCIO_GPU_TIMER_START_8_END_35', + 7: 'DCIO_GPU_TIMER_START_10_END_37', +} +DCIO_GPU_TIMER_START_0_END_27 = 0 +DCIO_GPU_TIMER_START_1_END_28 = 1 +DCIO_GPU_TIMER_START_2_END_29 = 2 +DCIO_GPU_TIMER_START_3_END_30 = 3 +DCIO_GPU_TIMER_START_4_END_31 = 4 +DCIO_GPU_TIMER_START_6_END_33 = 5 +DCIO_GPU_TIMER_START_8_END_35 = 6 +DCIO_GPU_TIMER_START_10_END_37 = 7 +DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', +} +DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 +DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', + 1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', + 2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', + 3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', +} +DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0 +DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1 +DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2 +DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3 +DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DIO_EXT_VSYNC_MASK' +DCIO_DIO_EXT_VSYNC_MASK__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MASK_NONE', + 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', + 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', + 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', + 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', + 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', + 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', + 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', +} +DCIO_EXT_VSYNC_MASK_NONE = 0 +DCIO_EXT_VSYNC_MASK_PIPE0 = 1 +DCIO_EXT_VSYNC_MASK_PIPE1 = 2 +DCIO_EXT_VSYNC_MASK_PIPE2 = 3 +DCIO_EXT_VSYNC_MASK_PIPE3 = 4 +DCIO_EXT_VSYNC_MASK_PIPE4 = 5 +DCIO_EXT_VSYNC_MASK_PIPE5 = 6 +DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 +DCIO_DIO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DIO_OTG_EXT_VSYNC_MUX' +DCIO_DIO_OTG_EXT_VSYNC_MUX__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 1: 'DCIO_EXT_VSYNC_MUX_OTG0', + 2: 'DCIO_EXT_VSYNC_MUX_OTG1', + 3: 'DCIO_EXT_VSYNC_MUX_OTG2', + 4: 'DCIO_EXT_VSYNC_MUX_OTG3', + 5: 'DCIO_EXT_VSYNC_MUX_OTG4', + 6: 'DCIO_EXT_VSYNC_MUX_OTG5', + 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', +} +DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 +DCIO_EXT_VSYNC_MUX_OTG0 = 1 +DCIO_EXT_VSYNC_MUX_OTG1 = 2 +DCIO_EXT_VSYNC_MUX_OTG2 = 3 +DCIO_EXT_VSYNC_MUX_OTG3 = 4 +DCIO_EXT_VSYNC_MUX_OTG4 = 5 +DCIO_EXT_VSYNC_MUX_OTG5 = 6 +DCIO_EXT_VSYNC_MUX_GENERICB = 7 +DCIO_DIO_OTG_EXT_VSYNC_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' +DCIO_DPCS_INTERRUPT_MASK__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_DISABLE', + 1: 'DCIO_DPCS_INTERRUPT_ENABLE', +} +DCIO_DPCS_INTERRUPT_DISABLE = 0 +DCIO_DPCS_INTERRUPT_ENABLE = 1 +DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' +DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', +} +DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 +DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 +DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DSYNC_SOFT_RESET' +DCIO_DSYNC_SOFT_RESET__enumvalues = { + 0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT', + 1: 'DCIO_DSYNC_SOFT_RESET_ASSERT', +} +DCIO_DSYNC_SOFT_RESET_DEASSERT = 0 +DCIO_DSYNC_SOFT_RESET_ASSERT = 1 +DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' +DCIO_GENLK_CLK_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', + 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', +} +DCIO_GENLK_CLK_GSL_MASK_NO = 0 +DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 +DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 +DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' +DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', +} +DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 +DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 +DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 +DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL_SEL' +DCIO_GSL_SEL__enumvalues = { + 0: 'DCIO_GSL_SEL_GROUP_0', + 1: 'DCIO_GSL_SEL_GROUP_1', + 2: 'DCIO_GSL_SEL_GROUP_2', +} +DCIO_GSL_SEL_GROUP_0 = 0 +DCIO_GSL_SEL_GROUP_1 = 1 +DCIO_GSL_SEL_GROUP_2 = 2 +DCIO_GSL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_PHY_HPO_ENC_SRC_SEL' +DCIO_PHY_HPO_ENC_SRC_SEL__enumvalues = { + 0: 'HPO_SRC0', + 1: 'HPO_SRC_RESERVED', +} +HPO_SRC0 = 0 +HPO_SRC_RESERVED = 1 +DCIO_PHY_HPO_ENC_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' +DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' +DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', +} +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' +DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { + 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', +} +DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 +DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 +DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', +} +DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 +DCIO_UNIPHY_CHANNEL_INVERTED = 1 +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { + 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', + 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', +} +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_ALL_PWR_OK' +DCIOCHIP_AUX_ALL_PWR_OK__enumvalues = { + 0: 'DCIOCHIP_AUX_ALL_PWR_OK_0', + 1: 'DCIOCHIP_AUX_ALL_PWR_OK_1', +} +DCIOCHIP_AUX_ALL_PWR_OK_0 = 0 +DCIOCHIP_AUX_ALL_PWR_OK_1 = 1 +DCIOCHIP_AUX_ALL_PWR_OK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL0P9' +DCIOCHIP_AUX_CSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', +} +DCIOCHIP_AUX_CSEL_DEC1P0 = 0 +DCIOCHIP_AUX_CSEL_DEC0P9 = 1 +DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL1P1' +DCIOCHIP_AUX_CSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_INC1P0', + 1: 'DCIOCHIP_AUX_CSEL_INC1P1', +} +DCIOCHIP_AUX_CSEL_INC1P0 = 0 +DCIOCHIP_AUX_CSEL_INC1P1 = 1 +DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' +DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { + 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', + 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', +} +DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 +DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 +DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_HYS_TUNE' +DCIOCHIP_AUX_HYS_TUNE__enumvalues = { + 0: 'DCIOCHIP_AUX_HYS_TUNE_0', + 1: 'DCIOCHIP_AUX_HYS_TUNE_1', + 2: 'DCIOCHIP_AUX_HYS_TUNE_2', + 3: 'DCIOCHIP_AUX_HYS_TUNE_3', +} +DCIOCHIP_AUX_HYS_TUNE_0 = 0 +DCIOCHIP_AUX_HYS_TUNE_1 = 1 +DCIOCHIP_AUX_HYS_TUNE_2 = 2 +DCIOCHIP_AUX_HYS_TUNE_3 = 3 +DCIOCHIP_AUX_HYS_TUNE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RECEIVER_SEL' +DCIOCHIP_AUX_RECEIVER_SEL__enumvalues = { + 0: 'DCIOCHIP_AUX_RECEIVER_SEL_0', + 1: 'DCIOCHIP_AUX_RECEIVER_SEL_1', + 2: 'DCIOCHIP_AUX_RECEIVER_SEL_2', + 3: 'DCIOCHIP_AUX_RECEIVER_SEL_3', +} +DCIOCHIP_AUX_RECEIVER_SEL_0 = 0 +DCIOCHIP_AUX_RECEIVER_SEL_1 = 1 +DCIOCHIP_AUX_RECEIVER_SEL_2 = 2 +DCIOCHIP_AUX_RECEIVER_SEL_3 = 3 +DCIOCHIP_AUX_RECEIVER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL0P9' +DCIOCHIP_AUX_RSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', +} +DCIOCHIP_AUX_RSEL_DEC1P0 = 0 +DCIOCHIP_AUX_RSEL_DEC0P9 = 1 +DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL1P1' +DCIOCHIP_AUX_RSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_INC1P0', + 1: 'DCIOCHIP_AUX_RSEL_INC1P1', +} +DCIOCHIP_AUX_RSEL_INC1P0 = 0 +DCIOCHIP_AUX_RSEL_INC1P1 = 1 +DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_SPIKESEL' +DCIOCHIP_AUX_SPIKESEL__enumvalues = { + 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', + 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', +} +DCIOCHIP_AUX_SPIKESEL_50NS = 0 +DCIOCHIP_AUX_SPIKESEL_10NS = 1 +DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_VOD_TUNE' +DCIOCHIP_AUX_VOD_TUNE__enumvalues = { + 0: 'DCIOCHIP_AUX_VOD_TUNE_0', + 1: 'DCIOCHIP_AUX_VOD_TUNE_1', + 2: 'DCIOCHIP_AUX_VOD_TUNE_2', + 3: 'DCIOCHIP_AUX_VOD_TUNE_3', +} +DCIOCHIP_AUX_VOD_TUNE_0 = 0 +DCIOCHIP_AUX_VOD_TUNE_1 = 1 +DCIOCHIP_AUX_VOD_TUNE_2 = 2 +DCIOCHIP_AUX_VOD_TUNE_3 = 3 +DCIOCHIP_AUX_VOD_TUNE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_MASK_EN' +DCIOCHIP_GPIO_MASK_EN__enumvalues = { + 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', +} +DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 +DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 +DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_HPD_SEL' +DCIOCHIP_HPD_SEL__enumvalues = { + 0: 'DCIOCHIP_HPD_SEL_ASYNC', + 1: 'DCIOCHIP_HPD_SEL_CLOCKED', +} +DCIOCHIP_HPD_SEL_ASYNC = 0 +DCIOCHIP_HPD_SEL_CLOCKED = 1 +DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_COMPSEL' +DCIOCHIP_I2C_COMPSEL__enumvalues = { + 0: 'DCIOCHIP_I2C_REC_SCHMIT', + 1: 'DCIOCHIP_I2C_REC_COMPARATOR', +} +DCIOCHIP_I2C_REC_SCHMIT = 0 +DCIOCHIP_I2C_REC_COMPARATOR = 1 +DCIOCHIP_I2C_COMPSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_FALLSLEWSEL' +DCIOCHIP_I2C_FALLSLEWSEL__enumvalues = { + 0: 'DCIOCHIP_I2C_FALLSLEWSEL_00', + 1: 'DCIOCHIP_I2C_FALLSLEWSEL_01', + 2: 'DCIOCHIP_I2C_FALLSLEWSEL_10', + 3: 'DCIOCHIP_I2C_FALLSLEWSEL_11', +} +DCIOCHIP_I2C_FALLSLEWSEL_00 = 0 +DCIOCHIP_I2C_FALLSLEWSEL_01 = 1 +DCIOCHIP_I2C_FALLSLEWSEL_10 = 2 +DCIOCHIP_I2C_FALLSLEWSEL_11 = 3 +DCIOCHIP_I2C_FALLSLEWSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_RECEIVER_SEL' +DCIOCHIP_I2C_RECEIVER_SEL__enumvalues = { + 0: 'DCIOCHIP_I2C_RECEIVER_SEL_0', + 1: 'DCIOCHIP_I2C_RECEIVER_SEL_1', + 2: 'DCIOCHIP_I2C_RECEIVER_SEL_2', + 3: 'DCIOCHIP_I2C_RECEIVER_SEL_3', +} +DCIOCHIP_I2C_RECEIVER_SEL_0 = 0 +DCIOCHIP_I2C_RECEIVER_SEL_1 = 1 +DCIOCHIP_I2C_RECEIVER_SEL_2 = 2 +DCIOCHIP_I2C_RECEIVER_SEL_3 = 3 +DCIOCHIP_I2C_RECEIVER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_VPH_1V2_EN' +DCIOCHIP_I2C_VPH_1V2_EN__enumvalues = { + 0: 'DCIOCHIP_I2C_VPH_1V2_EN_0', + 1: 'DCIOCHIP_I2C_VPH_1V2_EN_1', +} +DCIOCHIP_I2C_VPH_1V2_EN_0 = 0 +DCIOCHIP_I2C_VPH_1V2_EN_1 = 1 +DCIOCHIP_I2C_VPH_1V2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_INVERT' +DCIOCHIP_INVERT__enumvalues = { + 0: 'DCIOCHIP_POL_NON_INVERT', + 1: 'DCIOCHIP_POL_INVERT', +} +DCIOCHIP_POL_NON_INVERT = 0 +DCIOCHIP_POL_INVERT = 1 +DCIOCHIP_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK' +DCIOCHIP_MASK__enumvalues = { + 0: 'DCIOCHIP_MASK_DISABLE', + 1: 'DCIOCHIP_MASK_ENABLE', +} +DCIOCHIP_MASK_DISABLE = 0 +DCIOCHIP_MASK_ENABLE = 1 +DCIOCHIP_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PAD_MODE' +DCIOCHIP_PAD_MODE__enumvalues = { + 0: 'DCIOCHIP_PAD_MODE_DDC', + 1: 'DCIOCHIP_PAD_MODE_DP', +} +DCIOCHIP_PAD_MODE_DDC = 0 +DCIOCHIP_PAD_MODE_DP = 1 +DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PD_EN' +DCIOCHIP_PD_EN__enumvalues = { + 0: 'DCIOCHIP_PD_EN_NOTALLOW', + 1: 'DCIOCHIP_PD_EN_ALLOW', +} +DCIOCHIP_PD_EN_NOTALLOW = 0 +DCIOCHIP_PD_EN_ALLOW = 1 +DCIOCHIP_PD_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' +DCIOCHIP_REF_27_SRC_SEL__enumvalues = { + 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', + 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', +} +DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 +DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 +DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { + 0: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 1: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', +} +PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 +PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN' +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', + 1: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', +} +PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0 +PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 1 +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT' +PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = { + 0: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', + 1: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', + 2: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', + 3: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', +} +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0 +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1 +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2 +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3 +PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN' +PWRSEQ_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_DISABLE', + 1: 'PWRSEQ_BL_PWM_ENABLE', +} +PWRSEQ_BL_PWM_DISABLE = 0 +PWRSEQ_BL_PWM_ENABLE = 1 +PWRSEQ_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' +PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', + 1: 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', +} +PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0 +PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 1 +PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 1: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', +} +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 1: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', +} +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_REG_LOCK' +PWRSEQ_BL_PWM_GRP1_REG_LOCK__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', + 1: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', +} +PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 +PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 +PWRSEQ_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START' +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 1: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', +} +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_GPIO_MASK_EN' +PWRSEQ_GPIO_MASK_EN__enumvalues = { + 0: 'PWRSEQ_GPIO_MASK_EN_HARDWARE', + 1: 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', +} +PWRSEQ_GPIO_MASK_EN_HARDWARE = 0 +PWRSEQ_GPIO_MASK_EN_SOFTWARE = 1 +PWRSEQ_GPIO_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON__enumvalues = { + 0: 'PWRSEQ_PANEL_BLON_OFF', + 1: 'PWRSEQ_PANEL_BLON_ON', +} +PWRSEQ_PANEL_BLON_OFF = 0 +PWRSEQ_PANEL_BLON_ON = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL__enumvalues = { + 0: 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', + 1: 'PWRSEQ_PANEL_BLON_POL_INVERT', +} +PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0 +PWRSEQ_PANEL_BLON_POL_INVERT = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON__enumvalues = { + 0: 'PWRSEQ_PANEL_DIGON_OFF', + 1: 'PWRSEQ_PANEL_DIGON_ON', +} +PWRSEQ_PANEL_DIGON_OFF = 0 +PWRSEQ_PANEL_DIGON_ON = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL__enumvalues = { + 0: 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', + 1: 'PWRSEQ_PANEL_DIGON_POL_INVERT', +} +PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0 +PWRSEQ_PANEL_DIGON_POL_INVERT = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL__enumvalues = { + 0: 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', + 1: 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', +} +PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0 +PWRSEQ_PANEL_SYNCEN_POL_INVERT = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE' +PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { + 0: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', + 1: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', +} +PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0 +PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN' +PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN__enumvalues = { + 0: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', + 1: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', +} +PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0 +PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 1 +PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_CORB_SIZE' +AZ_CORB_SIZE__enumvalues = { + 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_CORB_SIZE_256ENTRIES', + 3: 'AZ_CORB_SIZE_RESERVED', +} +AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 +AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 +AZ_CORB_SIZE_256ENTRIES = 2 +AZ_CORB_SIZE_RESERVED = 3 +AZ_CORB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_GLOBAL_CAPABILITIES' +AZ_GLOBAL_CAPABILITIES__enumvalues = { + 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', +} +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 +AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_SIZE' +AZ_RIRB_SIZE__enumvalues = { + 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_RIRB_SIZE_256ENTRIES', + 3: 'AZ_RIRB_SIZE_UNDEFINED', +} +AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 +AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 +AZ_RIRB_SIZE_256ENTRIES = 2 +AZ_RIRB_SIZE_UNDEFINED = 3 +AZ_RIRB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' +AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { + 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', + 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', +} +AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 +AZ_RIRB_WRITE_POINTER_DO_RESET = 1 +AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_STATE_CHANGE_STATUS' +AZ_STATE_CHANGE_STATUS__enumvalues = { + 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', +} +AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 +AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 +AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'CORB_READ_POINTER_RESET' +CORB_READ_POINTER_RESET__enumvalues = { + 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', +} +CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 +CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 +CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { + 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', +} +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { + 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', + 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', +} +ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 +ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' +GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { + 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', +} +CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 +CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 +GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' +GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { + 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', + 1: 'FLUSH_CONTROL_FLUSH_STARTED', +} +FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 +FLUSH_CONTROL_FLUSH_STARTED = 1 +GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' +GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { + 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', +} +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 +GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_0_SYNCHRONIZATION' +STREAM_0_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_10_SYNCHRONIZATION' +STREAM_10_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_11_SYNCHRONIZATION' +STREAM_11_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_12_SYNCHRONIZATION' +STREAM_12_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_13_SYNCHRONIZATION' +STREAM_13_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_14_SYNCHRONIZATION' +STREAM_14_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_15_SYNCHRONIZATION' +STREAM_15_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_1_SYNCHRONIZATION' +STREAM_1_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_2_SYNCHRONIZATION' +STREAM_2_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_3_SYNCHRONIZATION' +STREAM_3_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_4_SYNCHRONIZATION' +STREAM_4_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_5_SYNCHRONIZATION' +STREAM_5_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_6_SYNCHRONIZATION' +STREAM_6_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_7_SYNCHRONIZATION' +STREAM_7_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_8_SYNCHRONIZATION' +STREAM_8_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_9_SYNCHRONIZATION' +STREAM_9_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE' +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', + 2: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', + 3: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', + 4: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', + 5: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', + 6: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', + 7: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', + 8: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', + 9: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', + 10: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', + 11: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', + 12: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', + 13: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', + 14: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', + 15: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', +} +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 1 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 2 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 3 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 4 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 5 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 6 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 7 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 8 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 9 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 10 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 11 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 12 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 13 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 14 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 15 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { + 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', +} +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_DIS_CTRL' +MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'ENABLE_MEM_PWR_CTRL', + 1: 'DISABLE_MEM_PWR_CTRL', +} +ENABLE_MEM_PWR_CTRL = 0 +DISABLE_MEM_PWR_CTRL = 1 +MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL' +MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'NO_FORCE_REQUEST', + 1: 'FORCE_LIGHT_SLEEP_REQUEST', + 2: 'FORCE_DEEP_SLEEP_REQUEST', + 3: 'FORCE_SHUT_DOWN_REQUEST', +} +NO_FORCE_REQUEST = 0 +FORCE_LIGHT_SLEEP_REQUEST = 1 +FORCE_DEEP_SLEEP_REQUEST = 2 +FORCE_SHUT_DOWN_REQUEST = 3 +MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL2' +MEM_PWR_FORCE_CTRL2__enumvalues = { + 0: 'NO_FORCE_REQ', + 1: 'FORCE_LIGHT_SLEEP_REQ', +} +NO_FORCE_REQ = 0 +FORCE_LIGHT_SLEEP_REQ = 1 +MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL' +MEM_PWR_SEL_CTRL__enumvalues = { + 0: 'DYNAMIC_SHUT_DOWN_ENABLE', + 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', + 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', +} +DYNAMIC_SHUT_DOWN_ENABLE = 0 +DYNAMIC_DEEP_SLEEP_ENABLE = 1 +DYNAMIC_LIGHT_SLEEP_ENABLE = 2 +MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL2' +MEM_PWR_SEL_CTRL2__enumvalues = { + 0: 'DYNAMIC_DEEP_SLEEP_EN', + 1: 'DYNAMIC_LIGHT_SLEEP_EN', +} +DYNAMIC_DEEP_SLEEP_EN = 0 +DYNAMIC_LIGHT_SLEEP_EN = 1 +MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { + 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', +} +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' +AZ_LATENCY_COUNTER_CONTROL__enumvalues = { + 0: 'AZ_LATENCY_COUNTER_NO_RESET', + 1: 'AZ_LATENCY_COUNTER_RESET_DONE', +} +AZ_LATENCY_COUNTER_NO_RESET = 0 +AZ_LATENCY_COUNTER_RESET_DONE = 1 +AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', +} +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_BITS_PER_COMPONENT_ENUM' +DSCC_BITS_PER_COMPONENT_ENUM__enumvalues = { + 8: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 10: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 12: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', +} +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 +DSCC_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_DSC_VERSION_MAJOR_ENUM' +DSCC_DSC_VERSION_MAJOR_ENUM__enumvalues = { + 1: 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', +} +DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 1 +DSCC_DSC_VERSION_MAJOR_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_DSC_VERSION_MINOR_ENUM' +DSCC_DSC_VERSION_MINOR_ENUM__enumvalues = { + 1: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', + 2: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', +} +DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 1 +DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 2 +DSCC_DSC_VERSION_MINOR_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_ENABLE_ENUM' +DSCC_ENABLE_ENUM__enumvalues = { + 0: 'DSCC_ENABLE_ENUM_DISABLED', + 1: 'DSCC_ENABLE_ENUM_ENABLED', +} +DSCC_ENABLE_ENUM_DISABLED = 0 +DSCC_ENABLE_ENUM_ENABLED = 1 +DSCC_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_ICH_RESET_ENUM' +DSCC_ICH_RESET_ENUM__enumvalues = { + 1: 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', + 2: 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', + 4: 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', + 8: 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', +} +DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 1 +DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 2 +DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 4 +DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 8 +DSCC_ICH_RESET_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_LINEBUF_DEPTH_ENUM' +DSCC_LINEBUF_DEPTH_ENUM__enumvalues = { + 8: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', + 9: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', + 10: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', + 11: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', + 12: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', + 13: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', +} +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 8 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 9 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 10 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 11 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 12 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 13 +DSCC_LINEBUF_DEPTH_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_MEM_PWR_DIS_ENUM' +DSCC_MEM_PWR_DIS_ENUM__enumvalues = { + 0: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', + 1: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', +} +DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0 +DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 1 +DSCC_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_MEM_PWR_FORCE_ENUM' +DSCC_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', + 1: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', +} +DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 2 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 3 +DSCC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'POWER_STATE_ENUM' +POWER_STATE_ENUM__enumvalues = { + 0: 'POWER_STATE_ENUM_ON', + 1: 'POWER_STATE_ENUM_LS', + 2: 'POWER_STATE_ENUM_DS', + 3: 'POWER_STATE_ENUM_SD', +} +POWER_STATE_ENUM_ON = 0 +POWER_STATE_ENUM_LS = 1 +POWER_STATE_ENUM_DS = 2 +POWER_STATE_ENUM_SD = 3 +POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_BITS_PER_COMPONENT_ENUM' +DSCCIF_BITS_PER_COMPONENT_ENUM__enumvalues = { + 8: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 10: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 12: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', +} +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 +DSCCIF_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_ENABLE_ENUM' +DSCCIF_ENABLE_ENUM__enumvalues = { + 0: 'DSCCIF_ENABLE_ENUM_DISABLED', + 1: 'DSCCIF_ENABLE_ENUM_ENABLED', +} +DSCCIF_ENABLE_ENUM_DISABLED = 0 +DSCCIF_ENABLE_ENUM_ENABLED = 1 +DSCCIF_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM' +DSCCIF_INPUT_PIXEL_FORMAT_ENUM__enumvalues = { + 0: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', + 1: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', + 2: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', + 3: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', + 4: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', +} +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 1 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 2 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 3 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 4 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_GATING_DISABLE_ENUM' +CLOCK_GATING_DISABLE_ENUM__enumvalues = { + 0: 'CLOCK_GATING_DISABLE_ENUM_ENABLED', + 1: 'CLOCK_GATING_DISABLE_ENUM_DISABLED', +} +CLOCK_GATING_DISABLE_ENUM_ENABLED = 0 +CLOCK_GATING_DISABLE_ENUM_DISABLED = 1 +CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE_ENUM' +ENABLE_ENUM__enumvalues = { + 0: 'ENABLE_ENUM_DISABLED', + 1: 'ENABLE_ENUM_ENABLED', +} +ENABLE_ENUM_DISABLED = 0 +ENABLE_ENUM_ENABLED = 1 +ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLOCK_MUX_SELECT_ENUM' +TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = { + 0: 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', + 1: 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', + 2: 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', + 3: 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', + 4: 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', + 5: 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', +} +TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0 +TEST_CLOCK_MUX_SELECT_DISPCLK_G = 1 +TEST_CLOCK_MUX_SELECT_DISPCLK_R = 2 +TEST_CLOCK_MUX_SELECT_DSCCLK_P = 3 +TEST_CLOCK_MUX_SELECT_DSCCLK_G = 4 +TEST_CLOCK_MUX_SELECT_DSCCLK_R = 5 +TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_CRC_CONT_EN_ENUM' +DWB_CRC_CONT_EN_ENUM__enumvalues = { + 0: 'DWB_CRC_CONT_EN_ONE_SHOT', + 1: 'DWB_CRC_CONT_EN_CONT', +} +DWB_CRC_CONT_EN_ONE_SHOT = 0 +DWB_CRC_CONT_EN_CONT = 1 +DWB_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_CRC_SRC_SEL_ENUM' +DWB_CRC_SRC_SEL_ENUM__enumvalues = { + 0: 'DWB_CRC_SRC_SEL_DWB_IN', + 1: 'DWB_CRC_SRC_SEL_OGAM_OUT', + 2: 'DWB_CRC_SRC_SEL_DWB_OUT', +} +DWB_CRC_SRC_SEL_DWB_IN = 0 +DWB_CRC_SRC_SEL_OGAM_OUT = 1 +DWB_CRC_SRC_SEL_DWB_OUT = 2 +DWB_CRC_SRC_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM' +DWB_DATA_OVERFLOW_INT_TYPE_ENUM__enumvalues = { + 0: 'DWB_DATA_OVERFLOW_INT_TYPE_0', + 1: 'DWB_DATA_OVERFLOW_INT_TYPE_1', +} +DWB_DATA_OVERFLOW_INT_TYPE_0 = 0 +DWB_DATA_OVERFLOW_INT_TYPE_1 = 1 +DWB_DATA_OVERFLOW_INT_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DATA_OVERFLOW_TYPE_ENUM' +DWB_DATA_OVERFLOW_TYPE_ENUM__enumvalues = { + 0: 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', + 1: 'DWB_DATA_OVERFLOW_TYPE_BUFFER', + 2: 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', + 3: 'DWB_DATA_OVERFLOW_TYPE_VREADY', +} +DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0 +DWB_DATA_OVERFLOW_TYPE_BUFFER = 1 +DWB_DATA_OVERFLOW_TYPE_VUPDATE = 2 +DWB_DATA_OVERFLOW_TYPE_VREADY = 3 +DWB_DATA_OVERFLOW_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DEBUG_SEL_ENUM' +DWB_DEBUG_SEL_ENUM__enumvalues = { + 0: 'DWB_DEBUG_SEL_FC', + 1: 'DWB_DEBUG_SEL_RESERVED', + 2: 'DWB_DEBUG_SEL_DWBCP', + 3: 'DWB_DEBUG_SEL_PERFMON', +} +DWB_DEBUG_SEL_FC = 0 +DWB_DEBUG_SEL_RESERVED = 1 +DWB_DEBUG_SEL_DWBCP = 2 +DWB_DEBUG_SEL_PERFMON = 3 +DWB_DEBUG_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_MEM_PWR_FORCE_ENUM' +DWB_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DWB_MEM_PWR_FORCE_DIS', + 1: 'DWB_MEM_PWR_FORCE_LS', + 2: 'DWB_MEM_PWR_FORCE_DS', + 3: 'DWB_MEM_PWR_FORCE_SD', +} +DWB_MEM_PWR_FORCE_DIS = 0 +DWB_MEM_PWR_FORCE_LS = 1 +DWB_MEM_PWR_FORCE_DS = 2 +DWB_MEM_PWR_FORCE_SD = 3 +DWB_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_MEM_PWR_STATE_ENUM' +DWB_MEM_PWR_STATE_ENUM__enumvalues = { + 0: 'DWB_MEM_PWR_STATE_ON', + 1: 'DWB_MEM_PWR_STATE_LS', + 2: 'DWB_MEM_PWR_STATE_DS', + 3: 'DWB_MEM_PWR_STATE_SD', +} +DWB_MEM_PWR_STATE_ON = 0 +DWB_MEM_PWR_STATE_LS = 1 +DWB_MEM_PWR_STATE_DS = 2 +DWB_MEM_PWR_STATE_SD = 3 +DWB_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_TEST_CLK_SEL_ENUM' +DWB_TEST_CLK_SEL_ENUM__enumvalues = { + 0: 'DWB_TEST_CLK_SEL_R', + 1: 'DWB_TEST_CLK_SEL_G', + 2: 'DWB_TEST_CLK_SEL_P', +} +DWB_TEST_CLK_SEL_R = 0 +DWB_TEST_CLK_SEL_G = 1 +DWB_TEST_CLK_SEL_P = 2 +DWB_TEST_CLK_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FC_EYE_SELECTION_ENUM' +FC_EYE_SELECTION_ENUM__enumvalues = { + 0: 'FC_EYE_SELECTION_STEREO_DIS', + 1: 'FC_EYE_SELECTION_LEFT_EYE', + 2: 'FC_EYE_SELECTION_RIGHT_EYE', +} +FC_EYE_SELECTION_STEREO_DIS = 0 +FC_EYE_SELECTION_LEFT_EYE = 1 +FC_EYE_SELECTION_RIGHT_EYE = 2 +FC_EYE_SELECTION_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FC_FRAME_CAPTURE_RATE_ENUM' +FC_FRAME_CAPTURE_RATE_ENUM__enumvalues = { + 0: 'FC_FRAME_CAPTURE_RATE_FULL', + 1: 'FC_FRAME_CAPTURE_RATE_HALF', + 2: 'FC_FRAME_CAPTURE_RATE_THIRD', + 3: 'FC_FRAME_CAPTURE_RATE_QUARTER', +} +FC_FRAME_CAPTURE_RATE_FULL = 0 +FC_FRAME_CAPTURE_RATE_HALF = 1 +FC_FRAME_CAPTURE_RATE_THIRD = 2 +FC_FRAME_CAPTURE_RATE_QUARTER = 3 +FC_FRAME_CAPTURE_RATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FC_STEREO_EYE_POLARITY_ENUM' +FC_STEREO_EYE_POLARITY_ENUM__enumvalues = { + 0: 'FC_STEREO_EYE_POLARITY_LEFT', + 1: 'FC_STEREO_EYE_POLARITY_RIGHT', +} +FC_STEREO_EYE_POLARITY_LEFT = 0 +FC_STEREO_EYE_POLARITY_RIGHT = 1 +FC_STEREO_EYE_POLARITY_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM' +DWB_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { + 0: 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', + 1: 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', +} +DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 +DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 +DWB_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_GAMUT_REMAP_MODE_ENUM' +DWB_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'DWB_GAMUT_REMAP_MODE_BYPASS', + 1: 'DWB_GAMUT_REMAP_MODE_COEF_A', + 2: 'DWB_GAMUT_REMAP_MODE_COEF_B', + 3: 'DWB_GAMUT_REMAP_MODE_RESERVED', +} +DWB_GAMUT_REMAP_MODE_BYPASS = 0 +DWB_GAMUT_REMAP_MODE_COEF_A = 1 +DWB_GAMUT_REMAP_MODE_COEF_B = 2 +DWB_GAMUT_REMAP_MODE_RESERVED = 3 +DWB_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_LUT_NUM_SEG' +DWB_LUT_NUM_SEG__enumvalues = { + 0: 'DWB_SEGMENTS_1', + 1: 'DWB_SEGMENTS_2', + 2: 'DWB_SEGMENTS_4', + 3: 'DWB_SEGMENTS_8', + 4: 'DWB_SEGMENTS_16', + 5: 'DWB_SEGMENTS_32', + 6: 'DWB_SEGMENTS_64', + 7: 'DWB_SEGMENTS_128', +} +DWB_SEGMENTS_1 = 0 +DWB_SEGMENTS_2 = 1 +DWB_SEGMENTS_4 = 2 +DWB_SEGMENTS_8 = 3 +DWB_SEGMENTS_16 = 4 +DWB_SEGMENTS_32 = 5 +DWB_SEGMENTS_64 = 6 +DWB_SEGMENTS_128 = 7 +DWB_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_CONFIG_MODE_ENUM' +DWB_OGAM_LUT_CONFIG_MODE_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', + 1: 'DWB_OGAM_LUT_CONFIG_MODE_SAME', +} +DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0 +DWB_OGAM_LUT_CONFIG_MODE_SAME = 1 +DWB_OGAM_LUT_CONFIG_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_HOST_SEL_ENUM' +DWB_OGAM_LUT_HOST_SEL_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_HOST_SEL_RAMA', + 1: 'DWB_OGAM_LUT_HOST_SEL_RAMB', +} +DWB_OGAM_LUT_HOST_SEL_RAMA = 0 +DWB_OGAM_LUT_HOST_SEL_RAMB = 1 +DWB_OGAM_LUT_HOST_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM' +DWB_OGAM_LUT_READ_COLOR_SEL_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_READ_COLOR_SEL_B', + 1: 'DWB_OGAM_LUT_READ_COLOR_SEL_G', + 2: 'DWB_OGAM_LUT_READ_COLOR_SEL_R', + 3: 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', +} +DWB_OGAM_LUT_READ_COLOR_SEL_B = 0 +DWB_OGAM_LUT_READ_COLOR_SEL_G = 1 +DWB_OGAM_LUT_READ_COLOR_SEL_R = 2 +DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 3 +DWB_OGAM_LUT_READ_COLOR_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_READ_DBG_ENUM' +DWB_OGAM_LUT_READ_DBG_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_READ_DBG_DISABLE', + 1: 'DWB_OGAM_LUT_READ_DBG_ENABLE', +} +DWB_OGAM_LUT_READ_DBG_DISABLE = 0 +DWB_OGAM_LUT_READ_DBG_ENABLE = 1 +DWB_OGAM_LUT_READ_DBG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_MODE_ENUM' +DWB_OGAM_MODE_ENUM__enumvalues = { + 0: 'DWB_OGAM_MODE_BYPASS', + 1: 'DWB_OGAM_MODE_RESERVED', + 2: 'DWB_OGAM_MODE_RAM_LUT_ENABLED', +} +DWB_OGAM_MODE_BYPASS = 0 +DWB_OGAM_MODE_RESERVED = 1 +DWB_OGAM_MODE_RAM_LUT_ENABLED = 2 +DWB_OGAM_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_PWL_DISABLE_ENUM' +DWB_OGAM_PWL_DISABLE_ENUM__enumvalues = { + 0: 'DWB_OGAM_PWL_DISABLE_FALSE', + 1: 'DWB_OGAM_PWL_DISABLE_TRUE', +} +DWB_OGAM_PWL_DISABLE_FALSE = 0 +DWB_OGAM_PWL_DISABLE_TRUE = 1 +DWB_OGAM_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_SELECT_ENUM' +DWB_OGAM_SELECT_ENUM__enumvalues = { + 0: 'DWB_OGAM_SELECT_A', + 1: 'DWB_OGAM_SELECT_B', +} +DWB_OGAM_SELECT_A = 0 +DWB_OGAM_SELECT_B = 1 +DWB_OGAM_SELECT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN' +RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN__enumvalues = { + 0: 'RDPCSPIPE_EXT_PCLK_EN_DISABLE', + 1: 'RDPCSPIPE_EXT_PCLK_EN_ENABLE', +} +RDPCSPIPE_EXT_PCLK_EN_DISABLE = 0 +RDPCSPIPE_EXT_PCLK_EN_ENABLE = 1 +RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN' +RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN__enumvalues = { + 0: 'RDPCSPIPE_APBCLK_DISABLE', + 1: 'RDPCSPIPE_APBCLK_ENABLE', +} +RDPCSPIPE_APBCLK_DISABLE = 0 +RDPCSPIPE_APBCLK_ENABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON' +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON__enumvalues = { + 0: 'RDPCS_PIPE_CLK_CLOCK_OFF', + 1: 'RDPCS_PIPE_CLK_CLOCK_ON', +} +RDPCS_PIPE_CLK_CLOCK_OFF = 0 +RDPCS_PIPE_CLK_CLOCK_ON = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN' +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN__enumvalues = { + 0: 'RDPCS_PIPE_CLK_DISABLE', + 1: 'RDPCS_PIPE_CLK_ENABLE', +} +RDPCS_PIPE_CLK_DISABLE = 0 +RDPCS_PIPE_CLK_ENABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS' +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS__enumvalues = { + 0: 'RDPCS_PIPE_CLK_GATE_ENABLE', + 1: 'RDPCS_PIPE_CLK_GATE_DISABLE', +} +RDPCS_PIPE_CLK_GATE_ENABLE = 0 +RDPCS_PIPE_CLK_GATE_DISABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON' +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON__enumvalues = { + 0: 'RDPCS_PIPE_PHYD32CLK_CLOCK_OFF', + 1: 'RDPCS_PIPE_PHYD32CLK_CLOCK_ON', +} +RDPCS_PIPE_PHYD32CLK_CLOCK_OFF = 0 +RDPCS_PIPE_PHYD32CLK_CLOCK_ON = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON' +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON__enumvalues = { + 0: 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF', + 1: 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON', +} +RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF = 0 +RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN' +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN__enumvalues = { + 0: 'RDPCSPIPE_SRAMCLK_DISABLE', + 1: 'RDPCSPIPE_SRAMCLK_ENABLE', +} +RDPCSPIPE_SRAMCLK_DISABLE = 0 +RDPCSPIPE_SRAMCLK_ENABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS' +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS__enumvalues = { + 0: 'RDPCSPIPE_SRAMCLK_GATE_ENABLE', + 1: 'RDPCSPIPE_SRAMCLK_GATE_DISABLE', +} +RDPCSPIPE_SRAMCLK_GATE_ENABLE = 0 +RDPCSPIPE_SRAMCLK_GATE_DISABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS' +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS__enumvalues = { + 0: 'RDPCSPIPE_SRAMCLK_NOT_PASS', + 1: 'RDPCSPIPE_SRAMCLK_PASS', +} +RDPCSPIPE_SRAMCLK_NOT_PASS = 0 +RDPCSPIPE_SRAMCLK_PASS = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN' +RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN__enumvalues = { + 0: 'RDPCS_PIPE_FIFO_DISABLE', + 1: 'RDPCS_PIPE_FIFO_ENABLE', +} +RDPCS_PIPE_FIFO_DISABLE = 0 +RDPCS_PIPE_FIFO_ENABLE = 1 +RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN' +RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN__enumvalues = { + 0: 'RDPCS_PIPE_FIFO_LANE_DISABLE', + 1: 'RDPCS_PIPE_FIFO_LANE_ENABLE', +} +RDPCS_PIPE_FIFO_LANE_DISABLE = 0 +RDPCS_PIPE_FIFO_LANE_ENABLE = 1 +RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET' +RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET__enumvalues = { + 0: 'RDPCS_PIPE_SOFT_RESET_DISABLE', + 1: 'RDPCS_PIPE_SOFT_RESET_ENABLE', +} +RDPCS_PIPE_SOFT_RESET_DISABLE = 0 +RDPCS_PIPE_SOFT_RESET_ENABLE = 1 +RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET' +RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET__enumvalues = { + 0: 'RDPCSPIPE_SRAM_SRAM_RESET_DISABLE', + 1: 'RDPCSPIPE_SRAM_SRAM_RESET_ENABLE', +} +RDPCSPIPE_SRAM_SRAM_RESET_DISABLE = 0 +RDPCSPIPE_SRAM_SRAM_RESET_ENABLE = 1 +RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK' +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK__enumvalues = { + 0: 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE', + 1: 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE', +} +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE = 0 +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE = 1 +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_DBG_OCLA_SEL' +RDPCSPIPE_DBG_OCLA_SEL__enumvalues = { + 0: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0', + 1: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8', + 2: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16', + 3: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24', + 4: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32', + 5: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40', + 6: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48', + 7: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56', +} +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0 = 0 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8 = 1 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16 = 2 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24 = 3 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32 = 4 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40 = 5 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48 = 6 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56 = 7 +RDPCSPIPE_DBG_OCLA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_ENC_TYPE' +RDPCSPIPE_ENC_TYPE__enumvalues = { + 0: 'HDMI_TMDS_OR_DP_8B10B', + 1: 'HDMI_FRL', + 2: 'DP_128B132B', +} +HDMI_TMDS_OR_DP_8B10B = 0 +HDMI_FRL = 1 +DP_128B132B = 2 +RDPCSPIPE_ENC_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_FIFO_EMPTY' +RDPCSPIPE_FIFO_EMPTY__enumvalues = { + 0: 'RDPCSPIPE_FIFO_NOT_EMPTY', + 1: 'RDPCSPIPE_FIFO_IS_EMPTY', +} +RDPCSPIPE_FIFO_NOT_EMPTY = 0 +RDPCSPIPE_FIFO_IS_EMPTY = 1 +RDPCSPIPE_FIFO_EMPTY = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_FIFO_FULL' +RDPCSPIPE_FIFO_FULL__enumvalues = { + 0: 'RDPCSPIPE_FIFO_NOT_FULL', + 1: 'RDPCSPIPE_FIFO_IS_FULL', +} +RDPCSPIPE_FIFO_NOT_FULL = 0 +RDPCSPIPE_FIFO_IS_FULL = 1 +RDPCSPIPE_FIFO_FULL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK__enumvalues = { + 0: 'RDPCSPIPE_APB_PSLVERR_MASK_DISABLE', + 1: 'RDPCSPIPE_APB_PSLVERR_MASK_ENABLE', +} +RDPCSPIPE_APB_PSLVERR_MASK_DISABLE = 0 +RDPCSPIPE_APB_PSLVERR_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE__enumvalues = { + 0: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE', + 1: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE', +} +RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE = 0 +RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK__enumvalues = { + 0: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE', + 1: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE', +} +RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0 +RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE__enumvalues = { + 0: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE', + 1: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE', +} +RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE = 0 +RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK__enumvalues = { + 0: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE', + 1: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE', +} +RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0 +RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK__enumvalues = { + 0: 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE', + 1: 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE', +} +RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE = 0 +RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK__enumvalues = { + 0: 'RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE', + 1: 'RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE', +} +RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE = 0 +RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK' +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK__enumvalues = { + 0: 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE', + 1: 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE', +} +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE = 0 +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE = 1 +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PACK_MODE' +RDPCSPIPE_PACK_MODE__enumvalues = { + 0: 'TIGHT_PACK', + 1: 'LOOSE_PACK', +} +TIGHT_PACK = 0 +LOOSE_PACK = 1 +RDPCSPIPE_PACK_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL' +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL__enumvalues = { + 0: 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB', + 1: 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC', +} +RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB = 0 +RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC = 1 +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL' +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL__enumvalues = { + 0: 'RDPCSPIPE_PHY_CR_PARA_SEL_JTAG', + 1: 'RDPCSPIPE_PHY_CR_PARA_SEL_CR', +} +RDPCSPIPE_PHY_CR_PARA_SEL_JTAG = 0 +RDPCSPIPE_PHY_CR_PARA_SEL_CR = 1 +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE' +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE__enumvalues = { + 0: 'RDPCSPIPE_PHY_REF_RANGE_0', + 1: 'RDPCSPIPE_PHY_REF_RANGE_1', + 2: 'RDPCSPIPE_PHY_REF_RANGE_2', + 3: 'RDPCSPIPE_PHY_REF_RANGE_3', + 4: 'RDPCSPIPE_PHY_REF_RANGE_4', + 5: 'RDPCSPIPE_PHY_REF_RANGE_5', + 6: 'RDPCSPIPE_PHY_REF_RANGE_6', + 7: 'RDPCSPIPE_PHY_REF_RANGE_7', +} +RDPCSPIPE_PHY_REF_RANGE_0 = 0 +RDPCSPIPE_PHY_REF_RANGE_1 = 1 +RDPCSPIPE_PHY_REF_RANGE_2 = 2 +RDPCSPIPE_PHY_REF_RANGE_3 = 3 +RDPCSPIPE_PHY_REF_RANGE_4 = 4 +RDPCSPIPE_PHY_REF_RANGE_5 = 5 +RDPCSPIPE_PHY_REF_RANGE_6 = 6 +RDPCSPIPE_PHY_REF_RANGE_7 = 7 +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE' +RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE__enumvalues = { + 0: 'RDPCSPIPE_SRAM_EXT_LD_NOT_DONE', + 1: 'RDPCSPIPE_SRAM_EXT_LD_DONE', +} +RDPCSPIPE_SRAM_EXT_LD_NOT_DONE = 0 +RDPCSPIPE_SRAM_EXT_LD_DONE = 1 +RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE' +RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE__enumvalues = { + 0: 'RDPCSPIPE_SRAM_INIT_NOT_DONE', + 1: 'RDPCSPIPE_SRAM_INIT_DONE', +} +RDPCSPIPE_SRAM_INIT_NOT_DONE = 0 +RDPCSPIPE_SRAM_INIT_DONE = 1 +RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV' +RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1', + 1: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2', + 2: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3', + 3: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8', + 4: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16', +} +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1 = 0 +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2 = 1 +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3 = 2 +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8 = 3 +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16 = 4 +RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV' +RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__enumvalues = { + 0: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', + 1: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', + 2: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', + 3: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', +} +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0 +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 1 +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 2 +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 3 +RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV' +RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV', + 1: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2', + 2: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4', + 3: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8', + 4: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3', + 5: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5', + 6: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6', + 7: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10', +} +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV = 0 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2 = 1 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4 = 2 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8 = 3 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3 = 4 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5 = 5 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6 = 6 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10 = 7 +RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL' +RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54', + 1: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52', + 2: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50', + 3: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48', + 4: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46', + 5: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44', + 6: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42', + 7: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40', +} +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54 = 0 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52 = 1 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50 = 2 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48 = 3 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46 = 4 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44 = 5 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42 = 6 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40 = 7 +RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT' +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT', + 1: 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT', +} +RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0 +RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT = 1 +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE' +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_TX_RATE', + 1: 'RDPCSPIPE_PHY_DP_TX_RATE_DIV2', + 2: 'RDPCSPIPE_PHY_DP_TX_RATE_DIV4', +} +RDPCSPIPE_PHY_DP_TX_RATE = 0 +RDPCSPIPE_PHY_DP_TX_RATE_DIV2 = 1 +RDPCSPIPE_PHY_DP_TX_RATE_DIV4 = 2 +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH' +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_TX_WIDTH_8', + 1: 'RDPCSPIPE_PHY_DP_TX_WIDTH_10', + 2: 'RDPCSPIPE_PHY_DP_TX_WIDTH_16', + 3: 'RDPCSPIPE_PHY_DP_TX_WIDTH_20', +} +RDPCSPIPE_PHY_DP_TX_WIDTH_8 = 0 +RDPCSPIPE_PHY_DP_TX_WIDTH_10 = 1 +RDPCSPIPE_PHY_DP_TX_WIDTH_16 = 2 +RDPCSPIPE_PHY_DP_TX_WIDTH_20 = 3 +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE' +RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE__enumvalues = { + 0: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP', + 1: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD', + 2: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF', + 3: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN', +} +RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP = 0 +RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD = 1 +RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF = 2 +RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN = 3 +RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_IF_WIDTH' +RDPCSPIPE_PHY_IF_WIDTH__enumvalues = { + 0: 'PHY_IF_WIDTH_10BIT', + 1: 'PHY_IF_WIDTH_20BIT', + 2: 'PHY_IF_WIDTH_40BIT', + 3: 'PHY_IF_WIDTH_80BIT', +} +PHY_IF_WIDTH_10BIT = 0 +PHY_IF_WIDTH_20BIT = 1 +PHY_IF_WIDTH_40BIT = 2 +PHY_IF_WIDTH_80BIT = 3 +RDPCSPIPE_PHY_IF_WIDTH = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_RATE' +RDPCSPIPE_PHY_RATE__enumvalues = { + 0: 'PHY_DP_RATE_1P62', + 1: 'PHY_DP_RATE_2P7', + 2: 'PHY_DP_RATE_5P4', + 3: 'PHY_DP_RATE_8P1', + 4: 'PHY_DP_RATE_2P16', + 5: 'PHY_DP_RATE_2P43', + 6: 'PHY_DP_RATE_3P24', + 7: 'PHY_DP_RATE_4P32', + 8: 'PHY_DP_RATE_10P', + 9: 'PHY_DP_RATE_13P5', + 10: 'PHY_DP_RATE_20P', + 15: 'PHY_CUSTOM_RATE', +} +PHY_DP_RATE_1P62 = 0 +PHY_DP_RATE_2P7 = 1 +PHY_DP_RATE_5P4 = 2 +PHY_DP_RATE_8P1 = 3 +PHY_DP_RATE_2P16 = 4 +PHY_DP_RATE_2P43 = 5 +PHY_DP_RATE_3P24 = 6 +PHY_DP_RATE_4P32 = 7 +PHY_DP_RATE_10P = 8 +PHY_DP_RATE_13P5 = 9 +PHY_DP_RATE_20P = 10 +PHY_CUSTOM_RATE = 15 +RDPCSPIPE_PHY_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_REF_ALT_CLK_EN' +RDPCSPIPE_PHY_REF_ALT_CLK_EN__enumvalues = { + 0: 'RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE', + 1: 'RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE', +} +RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE = 0 +RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE = 1 +RDPCSPIPE_PHY_REF_ALT_CLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_TEST_CLK_SEL' +RDPCSPIPE_TEST_CLK_SEL__enumvalues = { + 0: 'RDPCSPIPE_TEST_CLK_SEL_NONE', + 1: 'RDPCSPIPE_TEST_CLK_SEL_CFGCLK', + 2: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', + 3: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', + 4: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', + 5: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', + 6: 'RDPCSPIPE_TEST_CLK_SEL_SRAMCLK', + 7: 'RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK', + 8: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK', + 9: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK', + 10: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK', + 11: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK', + 12: 'RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', + 13: 'RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', + 14: 'RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK', + 15: 'RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk', + 16: 'RDPCSPIPE_TEST_CLK_SEL_dtb_out0', + 17: 'RDPCSPIPE_TEST_CLK_SEL_dtb_out1', +} +RDPCSPIPE_TEST_CLK_SEL_NONE = 0 +RDPCSPIPE_TEST_CLK_SEL_CFGCLK = 1 +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 2 +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 3 +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 4 +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 5 +RDPCSPIPE_TEST_CLK_SEL_SRAMCLK = 6 +RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK = 7 +RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK = 8 +RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK = 9 +RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK = 10 +RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK = 11 +RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 12 +RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 13 +RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK = 14 +RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk = 15 +RDPCSPIPE_TEST_CLK_SEL_dtb_out0 = 16 +RDPCSPIPE_TEST_CLK_SEL_dtb_out1 = 17 +RDPCSPIPE_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB' +RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB__enumvalues = { + 0: 'RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE', + 1: 'RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE', +} +RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE = 0 +RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE = 1 +RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE' +RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE__enumvalues = { + 0: 'RDPCSPIPE_MEM_PWR_NO_FORCE', + 1: 'RDPCSPIPE_MEM_PWR_LIGHT_SLEEP', + 2: 'RDPCSPIPE_MEM_PWR_DEEP_SLEEP', + 3: 'RDPCSPIPE_MEM_PWR_SHUT_DOWN', +} +RDPCSPIPE_MEM_PWR_NO_FORCE = 0 +RDPCSPIPE_MEM_PWR_LIGHT_SLEEP = 1 +RDPCSPIPE_MEM_PWR_DEEP_SLEEP = 2 +RDPCSPIPE_MEM_PWR_SHUT_DOWN = 3 +RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE' +RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE__enumvalues = { + 0: 'RDPCSPIPE_MEM_PWR_PWR_STATE_ON', + 1: 'RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP', + 2: 'RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP', + 3: 'RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN', +} +RDPCSPIPE_MEM_PWR_PWR_STATE_ON = 0 +RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 1 +RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP = 2 +RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN = 3 +RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK' +RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK__enumvalues = { + 0: 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE', + 1: 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE', +} +RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE = 0 +RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE = 1 +RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK = ctypes.c_uint32 # enum + +# values for enumeration 'GDS_PERFCOUNT_SELECT' +GDS_PERFCOUNT_SELECT__enumvalues = { + 0: 'GDS_PERF_SEL_WR_COMP', + 1: 'GDS_PERF_SEL_WBUF_WR', + 2: 'GDS_PERF_SEL_SE0_NORET', + 3: 'GDS_PERF_SEL_SE0_RET', + 4: 'GDS_PERF_SEL_SE0_ORD_CNT', + 5: 'GDS_PERF_SEL_SE0_2COMP_REQ', + 6: 'GDS_PERF_SEL_SE0_ORD_WAVE_VALID', + 7: 'GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD', + 8: 'GDS_PERF_SEL_SE0_GDS_WR_OP', + 9: 'GDS_PERF_SEL_SE0_GDS_RD_OP', + 10: 'GDS_PERF_SEL_SE0_GDS_ATOM_OP', + 11: 'GDS_PERF_SEL_SE0_GDS_REL_OP', + 12: 'GDS_PERF_SEL_SE0_GDS_CMPXCH_OP', + 13: 'GDS_PERF_SEL_SE0_GDS_BYTE_OP', + 14: 'GDS_PERF_SEL_SE0_GDS_SHORT_OP', + 15: 'GDS_PERF_SEL_SE1_NORET', + 16: 'GDS_PERF_SEL_SE1_RET', + 17: 'GDS_PERF_SEL_SE1_ORD_CNT', + 18: 'GDS_PERF_SEL_SE1_2COMP_REQ', + 19: 'GDS_PERF_SEL_SE1_ORD_WAVE_VALID', + 20: 'GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD', + 21: 'GDS_PERF_SEL_SE1_GDS_WR_OP', + 22: 'GDS_PERF_SEL_SE1_GDS_RD_OP', + 23: 'GDS_PERF_SEL_SE1_GDS_ATOM_OP', + 24: 'GDS_PERF_SEL_SE1_GDS_REL_OP', + 25: 'GDS_PERF_SEL_SE1_GDS_CMPXCH_OP', + 26: 'GDS_PERF_SEL_SE1_GDS_BYTE_OP', + 27: 'GDS_PERF_SEL_SE1_GDS_SHORT_OP', + 28: 'GDS_PERF_SEL_SE2_NORET', + 29: 'GDS_PERF_SEL_SE2_RET', + 30: 'GDS_PERF_SEL_SE2_ORD_CNT', + 31: 'GDS_PERF_SEL_SE2_2COMP_REQ', + 32: 'GDS_PERF_SEL_SE2_ORD_WAVE_VALID', + 33: 'GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD', + 34: 'GDS_PERF_SEL_SE2_GDS_WR_OP', + 35: 'GDS_PERF_SEL_SE2_GDS_RD_OP', + 36: 'GDS_PERF_SEL_SE2_GDS_ATOM_OP', + 37: 'GDS_PERF_SEL_SE2_GDS_REL_OP', + 38: 'GDS_PERF_SEL_SE2_GDS_CMPXCH_OP', + 39: 'GDS_PERF_SEL_SE2_GDS_BYTE_OP', + 40: 'GDS_PERF_SEL_SE2_GDS_SHORT_OP', + 41: 'GDS_PERF_SEL_SE3_NORET', + 42: 'GDS_PERF_SEL_SE3_RET', + 43: 'GDS_PERF_SEL_SE3_ORD_CNT', + 44: 'GDS_PERF_SEL_SE3_2COMP_REQ', + 45: 'GDS_PERF_SEL_SE3_ORD_WAVE_VALID', + 46: 'GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD', + 47: 'GDS_PERF_SEL_SE3_GDS_WR_OP', + 48: 'GDS_PERF_SEL_SE3_GDS_RD_OP', + 49: 'GDS_PERF_SEL_SE3_GDS_ATOM_OP', + 50: 'GDS_PERF_SEL_SE3_GDS_REL_OP', + 51: 'GDS_PERF_SEL_SE3_GDS_CMPXCH_OP', + 52: 'GDS_PERF_SEL_SE3_GDS_BYTE_OP', + 53: 'GDS_PERF_SEL_SE3_GDS_SHORT_OP', + 54: 'GDS_PERF_SEL_SE4_NORET', + 55: 'GDS_PERF_SEL_SE4_RET', + 56: 'GDS_PERF_SEL_SE4_ORD_CNT', + 57: 'GDS_PERF_SEL_SE4_2COMP_REQ', + 58: 'GDS_PERF_SEL_SE4_ORD_WAVE_VALID', + 59: 'GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD', + 60: 'GDS_PERF_SEL_SE4_GDS_WR_OP', + 61: 'GDS_PERF_SEL_SE4_GDS_RD_OP', + 62: 'GDS_PERF_SEL_SE4_GDS_ATOM_OP', + 63: 'GDS_PERF_SEL_SE4_GDS_REL_OP', + 64: 'GDS_PERF_SEL_SE4_GDS_CMPXCH_OP', + 65: 'GDS_PERF_SEL_SE4_GDS_BYTE_OP', + 66: 'GDS_PERF_SEL_SE4_GDS_SHORT_OP', + 67: 'GDS_PERF_SEL_SE5_NORET', + 68: 'GDS_PERF_SEL_SE5_RET', + 69: 'GDS_PERF_SEL_SE5_ORD_CNT', + 70: 'GDS_PERF_SEL_SE5_2COMP_REQ', + 71: 'GDS_PERF_SEL_SE5_ORD_WAVE_VALID', + 72: 'GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD', + 73: 'GDS_PERF_SEL_SE5_GDS_WR_OP', + 74: 'GDS_PERF_SEL_SE5_GDS_RD_OP', + 75: 'GDS_PERF_SEL_SE5_GDS_ATOM_OP', + 76: 'GDS_PERF_SEL_SE5_GDS_REL_OP', + 77: 'GDS_PERF_SEL_SE5_GDS_CMPXCH_OP', + 78: 'GDS_PERF_SEL_SE5_GDS_BYTE_OP', + 79: 'GDS_PERF_SEL_SE5_GDS_SHORT_OP', + 80: 'GDS_PERF_SEL_SE6_NORET', + 81: 'GDS_PERF_SEL_SE6_RET', + 82: 'GDS_PERF_SEL_SE6_ORD_CNT', + 83: 'GDS_PERF_SEL_SE6_2COMP_REQ', + 84: 'GDS_PERF_SEL_SE6_ORD_WAVE_VALID', + 85: 'GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD', + 86: 'GDS_PERF_SEL_SE6_GDS_WR_OP', + 87: 'GDS_PERF_SEL_SE6_GDS_RD_OP', + 88: 'GDS_PERF_SEL_SE6_GDS_ATOM_OP', + 89: 'GDS_PERF_SEL_SE6_GDS_REL_OP', + 90: 'GDS_PERF_SEL_SE6_GDS_CMPXCH_OP', + 91: 'GDS_PERF_SEL_SE6_GDS_BYTE_OP', + 92: 'GDS_PERF_SEL_SE6_GDS_SHORT_OP', + 93: 'GDS_PERF_SEL_SE7_NORET', + 94: 'GDS_PERF_SEL_SE7_RET', + 95: 'GDS_PERF_SEL_SE7_ORD_CNT', + 96: 'GDS_PERF_SEL_SE7_2COMP_REQ', + 97: 'GDS_PERF_SEL_SE7_ORD_WAVE_VALID', + 98: 'GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD', + 99: 'GDS_PERF_SEL_SE7_GDS_WR_OP', + 100: 'GDS_PERF_SEL_SE7_GDS_RD_OP', + 101: 'GDS_PERF_SEL_SE7_GDS_ATOM_OP', + 102: 'GDS_PERF_SEL_SE7_GDS_REL_OP', + 103: 'GDS_PERF_SEL_SE7_GDS_CMPXCH_OP', + 104: 'GDS_PERF_SEL_SE7_GDS_BYTE_OP', + 105: 'GDS_PERF_SEL_SE7_GDS_SHORT_OP', + 106: 'GDS_PERF_SEL_GWS_RELEASED', + 107: 'GDS_PERF_SEL_GWS_BYPASS', +} +GDS_PERF_SEL_WR_COMP = 0 +GDS_PERF_SEL_WBUF_WR = 1 +GDS_PERF_SEL_SE0_NORET = 2 +GDS_PERF_SEL_SE0_RET = 3 +GDS_PERF_SEL_SE0_ORD_CNT = 4 +GDS_PERF_SEL_SE0_2COMP_REQ = 5 +GDS_PERF_SEL_SE0_ORD_WAVE_VALID = 6 +GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD = 7 +GDS_PERF_SEL_SE0_GDS_WR_OP = 8 +GDS_PERF_SEL_SE0_GDS_RD_OP = 9 +GDS_PERF_SEL_SE0_GDS_ATOM_OP = 10 +GDS_PERF_SEL_SE0_GDS_REL_OP = 11 +GDS_PERF_SEL_SE0_GDS_CMPXCH_OP = 12 +GDS_PERF_SEL_SE0_GDS_BYTE_OP = 13 +GDS_PERF_SEL_SE0_GDS_SHORT_OP = 14 +GDS_PERF_SEL_SE1_NORET = 15 +GDS_PERF_SEL_SE1_RET = 16 +GDS_PERF_SEL_SE1_ORD_CNT = 17 +GDS_PERF_SEL_SE1_2COMP_REQ = 18 +GDS_PERF_SEL_SE1_ORD_WAVE_VALID = 19 +GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD = 20 +GDS_PERF_SEL_SE1_GDS_WR_OP = 21 +GDS_PERF_SEL_SE1_GDS_RD_OP = 22 +GDS_PERF_SEL_SE1_GDS_ATOM_OP = 23 +GDS_PERF_SEL_SE1_GDS_REL_OP = 24 +GDS_PERF_SEL_SE1_GDS_CMPXCH_OP = 25 +GDS_PERF_SEL_SE1_GDS_BYTE_OP = 26 +GDS_PERF_SEL_SE1_GDS_SHORT_OP = 27 +GDS_PERF_SEL_SE2_NORET = 28 +GDS_PERF_SEL_SE2_RET = 29 +GDS_PERF_SEL_SE2_ORD_CNT = 30 +GDS_PERF_SEL_SE2_2COMP_REQ = 31 +GDS_PERF_SEL_SE2_ORD_WAVE_VALID = 32 +GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD = 33 +GDS_PERF_SEL_SE2_GDS_WR_OP = 34 +GDS_PERF_SEL_SE2_GDS_RD_OP = 35 +GDS_PERF_SEL_SE2_GDS_ATOM_OP = 36 +GDS_PERF_SEL_SE2_GDS_REL_OP = 37 +GDS_PERF_SEL_SE2_GDS_CMPXCH_OP = 38 +GDS_PERF_SEL_SE2_GDS_BYTE_OP = 39 +GDS_PERF_SEL_SE2_GDS_SHORT_OP = 40 +GDS_PERF_SEL_SE3_NORET = 41 +GDS_PERF_SEL_SE3_RET = 42 +GDS_PERF_SEL_SE3_ORD_CNT = 43 +GDS_PERF_SEL_SE3_2COMP_REQ = 44 +GDS_PERF_SEL_SE3_ORD_WAVE_VALID = 45 +GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD = 46 +GDS_PERF_SEL_SE3_GDS_WR_OP = 47 +GDS_PERF_SEL_SE3_GDS_RD_OP = 48 +GDS_PERF_SEL_SE3_GDS_ATOM_OP = 49 +GDS_PERF_SEL_SE3_GDS_REL_OP = 50 +GDS_PERF_SEL_SE3_GDS_CMPXCH_OP = 51 +GDS_PERF_SEL_SE3_GDS_BYTE_OP = 52 +GDS_PERF_SEL_SE3_GDS_SHORT_OP = 53 +GDS_PERF_SEL_SE4_NORET = 54 +GDS_PERF_SEL_SE4_RET = 55 +GDS_PERF_SEL_SE4_ORD_CNT = 56 +GDS_PERF_SEL_SE4_2COMP_REQ = 57 +GDS_PERF_SEL_SE4_ORD_WAVE_VALID = 58 +GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD = 59 +GDS_PERF_SEL_SE4_GDS_WR_OP = 60 +GDS_PERF_SEL_SE4_GDS_RD_OP = 61 +GDS_PERF_SEL_SE4_GDS_ATOM_OP = 62 +GDS_PERF_SEL_SE4_GDS_REL_OP = 63 +GDS_PERF_SEL_SE4_GDS_CMPXCH_OP = 64 +GDS_PERF_SEL_SE4_GDS_BYTE_OP = 65 +GDS_PERF_SEL_SE4_GDS_SHORT_OP = 66 +GDS_PERF_SEL_SE5_NORET = 67 +GDS_PERF_SEL_SE5_RET = 68 +GDS_PERF_SEL_SE5_ORD_CNT = 69 +GDS_PERF_SEL_SE5_2COMP_REQ = 70 +GDS_PERF_SEL_SE5_ORD_WAVE_VALID = 71 +GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD = 72 +GDS_PERF_SEL_SE5_GDS_WR_OP = 73 +GDS_PERF_SEL_SE5_GDS_RD_OP = 74 +GDS_PERF_SEL_SE5_GDS_ATOM_OP = 75 +GDS_PERF_SEL_SE5_GDS_REL_OP = 76 +GDS_PERF_SEL_SE5_GDS_CMPXCH_OP = 77 +GDS_PERF_SEL_SE5_GDS_BYTE_OP = 78 +GDS_PERF_SEL_SE5_GDS_SHORT_OP = 79 +GDS_PERF_SEL_SE6_NORET = 80 +GDS_PERF_SEL_SE6_RET = 81 +GDS_PERF_SEL_SE6_ORD_CNT = 82 +GDS_PERF_SEL_SE6_2COMP_REQ = 83 +GDS_PERF_SEL_SE6_ORD_WAVE_VALID = 84 +GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD = 85 +GDS_PERF_SEL_SE6_GDS_WR_OP = 86 +GDS_PERF_SEL_SE6_GDS_RD_OP = 87 +GDS_PERF_SEL_SE6_GDS_ATOM_OP = 88 +GDS_PERF_SEL_SE6_GDS_REL_OP = 89 +GDS_PERF_SEL_SE6_GDS_CMPXCH_OP = 90 +GDS_PERF_SEL_SE6_GDS_BYTE_OP = 91 +GDS_PERF_SEL_SE6_GDS_SHORT_OP = 92 +GDS_PERF_SEL_SE7_NORET = 93 +GDS_PERF_SEL_SE7_RET = 94 +GDS_PERF_SEL_SE7_ORD_CNT = 95 +GDS_PERF_SEL_SE7_2COMP_REQ = 96 +GDS_PERF_SEL_SE7_ORD_WAVE_VALID = 97 +GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD = 98 +GDS_PERF_SEL_SE7_GDS_WR_OP = 99 +GDS_PERF_SEL_SE7_GDS_RD_OP = 100 +GDS_PERF_SEL_SE7_GDS_ATOM_OP = 101 +GDS_PERF_SEL_SE7_GDS_REL_OP = 102 +GDS_PERF_SEL_SE7_GDS_CMPXCH_OP = 103 +GDS_PERF_SEL_SE7_GDS_BYTE_OP = 104 +GDS_PERF_SEL_SE7_GDS_SHORT_OP = 105 +GDS_PERF_SEL_GWS_RELEASED = 106 +GDS_PERF_SEL_GWS_BYPASS = 107 +GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'BlendOp' +BlendOp__enumvalues = { + 0: 'BLEND_ZERO', + 1: 'BLEND_ONE', + 2: 'BLEND_SRC_COLOR', + 3: 'BLEND_ONE_MINUS_SRC_COLOR', + 4: 'BLEND_SRC_ALPHA', + 5: 'BLEND_ONE_MINUS_SRC_ALPHA', + 6: 'BLEND_DST_ALPHA', + 7: 'BLEND_ONE_MINUS_DST_ALPHA', + 8: 'BLEND_DST_COLOR', + 9: 'BLEND_ONE_MINUS_DST_COLOR', + 10: 'BLEND_SRC_ALPHA_SATURATE', + 11: 'BLEND_CONSTANT_COLOR', + 12: 'BLEND_ONE_MINUS_CONSTANT_COLOR', + 13: 'BLEND_SRC1_COLOR', + 14: 'BLEND_INV_SRC1_COLOR', + 15: 'BLEND_SRC1_ALPHA', + 16: 'BLEND_INV_SRC1_ALPHA', + 17: 'BLEND_CONSTANT_ALPHA', + 18: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', +} +BLEND_ZERO = 0 +BLEND_ONE = 1 +BLEND_SRC_COLOR = 2 +BLEND_ONE_MINUS_SRC_COLOR = 3 +BLEND_SRC_ALPHA = 4 +BLEND_ONE_MINUS_SRC_ALPHA = 5 +BLEND_DST_ALPHA = 6 +BLEND_ONE_MINUS_DST_ALPHA = 7 +BLEND_DST_COLOR = 8 +BLEND_ONE_MINUS_DST_COLOR = 9 +BLEND_SRC_ALPHA_SATURATE = 10 +BLEND_CONSTANT_COLOR = 11 +BLEND_ONE_MINUS_CONSTANT_COLOR = 12 +BLEND_SRC1_COLOR = 13 +BLEND_INV_SRC1_COLOR = 14 +BLEND_SRC1_ALPHA = 15 +BLEND_INV_SRC1_ALPHA = 16 +BLEND_CONSTANT_ALPHA = 17 +BLEND_ONE_MINUS_CONSTANT_ALPHA = 18 +BlendOp = ctypes.c_uint32 # enum +GL__ZERO = BLEND_ZERO # macro +GL__ONE = BLEND_ONE # macro +GL__SRC_COLOR = BLEND_SRC_COLOR # macro +GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro +GL__DST_COLOR = BLEND_DST_COLOR # macro +GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro +GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro +GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro +GL__DST_ALPHA = BLEND_DST_ALPHA # macro +GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro +GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro +GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro +GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro +GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro +GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro + +# values for enumeration 'BlendOpt' +BlendOpt__enumvalues = { + 0: 'FORCE_OPT_AUTO', + 1: 'FORCE_OPT_DISABLE', + 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', + 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', + 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', +} +FORCE_OPT_AUTO = 0 +FORCE_OPT_DISABLE = 1 +FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 +FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 +FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 +FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 +FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 +FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 +BlendOpt = ctypes.c_uint32 # enum + +# values for enumeration 'CBMode' +CBMode__enumvalues = { + 0: 'CB_DISABLE', + 1: 'CB_NORMAL', + 2: 'CB_ELIMINATE_FAST_CLEAR', + 3: 'CB_DCC_DECOMPRESS', + 4: 'CB_RESERVED', +} +CB_DISABLE = 0 +CB_NORMAL = 1 +CB_ELIMINATE_FAST_CLEAR = 2 +CB_DCC_DECOMPRESS = 3 +CB_RESERVED = 4 +CBMode = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfClearFilterSel' +CBPerfClearFilterSel__enumvalues = { + 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', +} +CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 +CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 +CBPerfClearFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfOpFilterSel' +CBPerfOpFilterSel__enumvalues = { + 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', +} +CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 +CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 +CB_PERF_OP_FILTER_SEL_RESOLVE = 2 +CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 +CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 +CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 +CBPerfOpFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfSel' +CBPerfSel__enumvalues = { + 0: 'CB_PERF_SEL_NONE', + 1: 'CB_PERF_SEL_DRAWN_PIXEL', + 2: 'CB_PERF_SEL_DRAWN_QUAD', + 3: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', + 4: 'CB_PERF_SEL_DRAWN_TILE', + 5: 'CB_PERF_SEL_FILTER_DRAWN_PIXEL', + 6: 'CB_PERF_SEL_FILTER_DRAWN_QUAD', + 7: 'CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT', + 8: 'CB_PERF_SEL_FILTER_DRAWN_TILE', + 9: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN', + 10: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT', + 11: 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN', + 12: 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT', + 13: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', + 14: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', + 15: 'CB_PERF_SEL_CC_MC_READ_REQUEST', + 16: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', + 17: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', + 18: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', + 19: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', + 20: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', + 21: 'CB_PERF_SEL_RESERVED_21', + 22: 'CB_PERF_SEL_RESERVED_22', + 23: 'CB_PERF_SEL_RESERVED_23', + 24: 'CB_PERF_SEL_RESERVED_24', + 25: 'CB_PERF_SEL_RESERVED_25', + 26: 'CB_PERF_SEL_RESERVED_26', + 27: 'CB_PERF_SEL_RESERVED_27', + 28: 'CB_PERF_SEL_RESERVED_28', + 29: 'CB_PERF_SEL_RESERVED_29', + 30: 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY', + 31: 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB', + 32: 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY', + 33: 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB', + 34: 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY', + 35: 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB', + 36: 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY', + 37: 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB', + 38: 'CB_PERF_SEL_RESERVED_38', + 39: 'CB_PERF_SEL_RESERVED_39', + 40: 'CB_PERF_SEL_RESERVED_40', + 41: 'CB_PERF_SEL_RESERVED_41', + 42: 'CB_PERF_SEL_RESERVED_42', + 43: 'CB_PERF_SEL_RESERVED_43', + 44: 'CB_PERF_SEL_RESERVED_44', + 45: 'CB_PERF_SEL_RESERVED_45', + 46: 'CB_PERF_SEL_RESERVED_46', + 47: 'CB_PERF_SEL_RESERVED_47', + 48: 'CB_PERF_SEL_RESERVED_48', + 49: 'CB_PERF_SEL_RESERVED_49', + 50: 'CB_PERF_SEL_STATIC_CLOCK_EN', + 51: 'CB_PERF_SEL_PERFMON_CLOCK_EN', + 52: 'CB_PERF_SEL_BLEND_CLOCK_EN', + 53: 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', + 54: 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', + 55: 'CB_PERF_SEL_GRBM_CLOCK_EN', + 56: 'CB_PERF_SEL_MEMARB_CLOCK_EN', + 57: 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', + 58: 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', + 59: 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', + 60: 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', + 61: 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', + 62: 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', + 63: 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', + 64: 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', + 65: 'CB_PERF_SEL_RESERVED_65', + 66: 'CB_PERF_SEL_RESERVED_66', + 67: 'CB_PERF_SEL_RESERVED_67', + 68: 'CB_PERF_SEL_RESERVED_68', + 69: 'CB_PERF_SEL_RESERVED_69', + 70: 'CB_PERF_SEL_RESERVED_70', + 71: 'CB_PERF_SEL_RESERVED_71', + 72: 'CB_PERF_SEL_RESERVED_72', + 73: 'CB_PERF_SEL_RESERVED_73', + 74: 'CB_PERF_SEL_RESERVED_74', + 75: 'CB_PERF_SEL_RESERVED_75', + 76: 'CB_PERF_SEL_RESERVED_76', + 77: 'CB_PERF_SEL_RESERVED_77', + 78: 'CB_PERF_SEL_RESERVED_78', + 79: 'CB_PERF_SEL_RESERVED_79', + 80: 'CB_PERF_SEL_RESERVED_80', + 81: 'CB_PERF_SEL_RESERVED_81', + 82: 'CB_PERF_SEL_RESERVED_82', + 83: 'CB_PERF_SEL_RESERVED_83', + 84: 'CB_PERF_SEL_RESERVED_84', + 85: 'CB_PERF_SEL_RESERVED_85', + 86: 'CB_PERF_SEL_RESERVED_86', + 87: 'CB_PERF_SEL_RESERVED_87', + 88: 'CB_PERF_SEL_RESERVED_88', + 89: 'CB_PERF_SEL_RESERVED_89', + 90: 'CB_PERF_SEL_RESERVED_90', + 91: 'CB_PERF_SEL_RESERVED_91', + 92: 'CB_PERF_SEL_RESERVED_92', + 93: 'CB_PERF_SEL_RESERVED_93', + 94: 'CB_PERF_SEL_RESERVED_94', + 95: 'CB_PERF_SEL_RESERVED_95', + 96: 'CB_PERF_SEL_RESERVED_96', + 97: 'CB_PERF_SEL_RESERVED_97', + 98: 'CB_PERF_SEL_RESERVED_98', + 99: 'CB_PERF_SEL_RESERVED_99', + 100: 'CB_PERF_SEL_CC_TAG_HIT', + 101: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 102: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', + 103: 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', + 104: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', + 105: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 106: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', + 107: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 108: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 109: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 110: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 111: 'CB_PERF_SEL_CC_CACHE_STALL', + 112: 'CB_PERF_SEL_CC_CACHE_FLUSH', + 113: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', + 114: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 115: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 116: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', + 117: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 118: 'CB_PERF_SEL_RESERVED_118', + 119: 'CB_PERF_SEL_RESERVED_119', + 120: 'CB_PERF_SEL_RESERVED_120', + 121: 'CB_PERF_SEL_RESERVED_121', + 122: 'CB_PERF_SEL_RESERVED_122', + 123: 'CB_PERF_SEL_RESERVED_123', + 124: 'CB_PERF_SEL_RESERVED_124', + 125: 'CB_PERF_SEL_RESERVED_125', + 126: 'CB_PERF_SEL_RESERVED_126', + 127: 'CB_PERF_SEL_RESERVED_127', + 128: 'CB_PERF_SEL_RESERVED_128', + 129: 'CB_PERF_SEL_RESERVED_129', + 130: 'CB_PERF_SEL_RESERVED_130', + 131: 'CB_PERF_SEL_RESERVED_131', + 132: 'CB_PERF_SEL_RESERVED_132', + 133: 'CB_PERF_SEL_RESERVED_133', + 134: 'CB_PERF_SEL_RESERVED_134', + 135: 'CB_PERF_SEL_RESERVED_135', + 136: 'CB_PERF_SEL_RESERVED_136', + 137: 'CB_PERF_SEL_RESERVED_137', + 138: 'CB_PERF_SEL_RESERVED_138', + 139: 'CB_PERF_SEL_RESERVED_139', + 140: 'CB_PERF_SEL_RESERVED_140', + 141: 'CB_PERF_SEL_RESERVED_141', + 142: 'CB_PERF_SEL_RESERVED_142', + 143: 'CB_PERF_SEL_RESERVED_143', + 144: 'CB_PERF_SEL_RESERVED_144', + 145: 'CB_PERF_SEL_RESERVED_145', + 146: 'CB_PERF_SEL_RESERVED_146', + 147: 'CB_PERF_SEL_RESERVED_147', + 148: 'CB_PERF_SEL_RESERVED_148', + 149: 'CB_PERF_SEL_RESERVED_149', + 150: 'CB_PERF_SEL_DCC_CACHE_PERF_HIT', + 151: 'CB_PERF_SEL_DCC_CACHE_TAG_MISS', + 152: 'CB_PERF_SEL_DCC_CACHE_SECTOR_MISS', + 153: 'CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL', + 154: 'CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 155: 'CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', + 156: 'CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 157: 'CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL', + 158: 'CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL', + 159: 'CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL', + 160: 'CB_PERF_SEL_DCC_CACHE_STALL', + 161: 'CB_PERF_SEL_DCC_CACHE_FLUSH', + 162: 'CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED', + 163: 'CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED', + 164: 'CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED', + 165: 'CB_PERF_SEL_RESERVED_165', + 166: 'CB_PERF_SEL_RESERVED_166', + 167: 'CB_PERF_SEL_RESERVED_167', + 168: 'CB_PERF_SEL_RESERVED_168', + 169: 'CB_PERF_SEL_RESERVED_169', + 170: 'CB_PERF_SEL_RESERVED_170', + 171: 'CB_PERF_SEL_RESERVED_171', + 172: 'CB_PERF_SEL_RESERVED_172', + 173: 'CB_PERF_SEL_RESERVED_173', + 174: 'CB_PERF_SEL_RESERVED_174', + 175: 'CB_PERF_SEL_RESERVED_175', + 176: 'CB_PERF_SEL_RESERVED_176', + 177: 'CB_PERF_SEL_RESERVED_177', + 178: 'CB_PERF_SEL_RESERVED_178', + 179: 'CB_PERF_SEL_RESERVED_179', + 180: 'CB_PERF_SEL_RESERVED_180', + 181: 'CB_PERF_SEL_RESERVED_181', + 182: 'CB_PERF_SEL_RESERVED_182', + 183: 'CB_PERF_SEL_RESERVED_183', + 184: 'CB_PERF_SEL_RESERVED_184', + 185: 'CB_PERF_SEL_RESERVED_185', + 186: 'CB_PERF_SEL_RESERVED_186', + 187: 'CB_PERF_SEL_RESERVED_187', + 188: 'CB_PERF_SEL_RESERVED_188', + 189: 'CB_PERF_SEL_RESERVED_189', + 190: 'CB_PERF_SEL_RESERVED_190', + 191: 'CB_PERF_SEL_RESERVED_191', + 192: 'CB_PERF_SEL_RESERVED_192', + 193: 'CB_PERF_SEL_RESERVED_193', + 194: 'CB_PERF_SEL_RESERVED_194', + 195: 'CB_PERF_SEL_RESERVED_195', + 196: 'CB_PERF_SEL_RESERVED_196', + 197: 'CB_PERF_SEL_RESERVED_197', + 198: 'CB_PERF_SEL_RESERVED_198', + 199: 'CB_PERF_SEL_RESERVED_199', + 200: 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 201: 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 202: 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', + 203: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', + 204: 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', + 205: 'CB_PERF_SEL_RESERVED_205', + 206: 'CB_PERF_SEL_RESERVED_206', + 207: 'CB_PERF_SEL_RESERVED_207', + 208: 'CB_PERF_SEL_RESERVED_208', + 209: 'CB_PERF_SEL_RESERVED_209', + 210: 'CB_PERF_SEL_RESERVED_210', + 211: 'CB_PERF_SEL_RESERVED_211', + 212: 'CB_PERF_SEL_RESERVED_212', + 213: 'CB_PERF_SEL_RESERVED_213', + 214: 'CB_PERF_SEL_RESERVED_214', + 215: 'CB_PERF_SEL_RESERVED_215', + 216: 'CB_PERF_SEL_RESERVED_216', + 217: 'CB_PERF_SEL_RESERVED_217', + 218: 'CB_PERF_SEL_RESERVED_218', + 219: 'CB_PERF_SEL_RESERVED_219', + 220: 'CB_PERF_SEL_RESERVED_220', + 221: 'CB_PERF_SEL_RESERVED_221', + 222: 'CB_PERF_SEL_RESERVED_222', + 223: 'CB_PERF_SEL_RESERVED_223', + 224: 'CB_PERF_SEL_RESERVED_224', + 225: 'CB_PERF_SEL_RESERVED_225', + 226: 'CB_PERF_SEL_RESERVED_226', + 227: 'CB_PERF_SEL_RESERVED_227', + 228: 'CB_PERF_SEL_RESERVED_228', + 229: 'CB_PERF_SEL_RESERVED_229', + 230: 'CB_PERF_SEL_RESERVED_230', + 231: 'CB_PERF_SEL_RESERVED_231', + 232: 'CB_PERF_SEL_RESERVED_232', + 233: 'CB_PERF_SEL_RESERVED_233', + 234: 'CB_PERF_SEL_RESERVED_234', + 235: 'CB_PERF_SEL_RESERVED_235', + 236: 'CB_PERF_SEL_RESERVED_236', + 237: 'CB_PERF_SEL_RESERVED_237', + 238: 'CB_PERF_SEL_RESERVED_238', + 239: 'CB_PERF_SEL_RESERVED_239', + 240: 'CB_PERF_SEL_RESERVED_240', + 241: 'CB_PERF_SEL_RESERVED_241', + 242: 'CB_PERF_SEL_RESERVED_242', + 243: 'CB_PERF_SEL_RESERVED_243', + 244: 'CB_PERF_SEL_RESERVED_244', + 245: 'CB_PERF_SEL_RESERVED_245', + 246: 'CB_PERF_SEL_RESERVED_246', + 247: 'CB_PERF_SEL_RESERVED_247', + 248: 'CB_PERF_SEL_RESERVED_248', + 249: 'CB_PERF_SEL_RESERVED_249', + 250: 'CB_PERF_SEL_EVENT', + 251: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 252: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 253: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 254: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 255: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 256: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 257: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 258: 'CB_PERF_SEL_CC_SURFACE_SYNC', + 259: 'CB_PERF_SEL_RESERVED_259', + 260: 'CB_PERF_SEL_RESERVED_260', + 261: 'CB_PERF_SEL_RESERVED_261', + 262: 'CB_PERF_SEL_RESERVED_262', + 263: 'CB_PERF_SEL_RESERVED_263', + 264: 'CB_PERF_SEL_RESERVED_264', + 265: 'CB_PERF_SEL_RESERVED_265', + 266: 'CB_PERF_SEL_RESERVED_266', + 267: 'CB_PERF_SEL_RESERVED_267', + 268: 'CB_PERF_SEL_RESERVED_268', + 269: 'CB_PERF_SEL_RESERVED_269', + 270: 'CB_PERF_SEL_RESERVED_270', + 271: 'CB_PERF_SEL_RESERVED_271', + 272: 'CB_PERF_SEL_RESERVED_272', + 273: 'CB_PERF_SEL_RESERVED_273', + 274: 'CB_PERF_SEL_RESERVED_274', + 275: 'CB_PERF_SEL_RESERVED_275', + 276: 'CB_PERF_SEL_RESERVED_276', + 277: 'CB_PERF_SEL_RESERVED_277', + 278: 'CB_PERF_SEL_RESERVED_278', + 279: 'CB_PERF_SEL_RESERVED_279', + 280: 'CB_PERF_SEL_RESERVED_280', + 281: 'CB_PERF_SEL_RESERVED_281', + 282: 'CB_PERF_SEL_RESERVED_282', + 283: 'CB_PERF_SEL_RESERVED_283', + 284: 'CB_PERF_SEL_RESERVED_284', + 285: 'CB_PERF_SEL_RESERVED_285', + 286: 'CB_PERF_SEL_RESERVED_286', + 287: 'CB_PERF_SEL_RESERVED_287', + 288: 'CB_PERF_SEL_RESERVED_288', + 289: 'CB_PERF_SEL_RESERVED_289', + 290: 'CB_PERF_SEL_RESERVED_290', + 291: 'CB_PERF_SEL_RESERVED_291', + 292: 'CB_PERF_SEL_RESERVED_292', + 293: 'CB_PERF_SEL_RESERVED_293', + 294: 'CB_PERF_SEL_RESERVED_294', + 295: 'CB_PERF_SEL_RESERVED_295', + 296: 'CB_PERF_SEL_RESERVED_296', + 297: 'CB_PERF_SEL_RESERVED_297', + 298: 'CB_PERF_SEL_RESERVED_298', + 299: 'CB_PERF_SEL_RESERVED_299', + 300: 'CB_PERF_SEL_NACK_CC_READ', + 301: 'CB_PERF_SEL_NACK_CC_WRITE', + 302: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', + 303: 'CB_PERF_SEL_RESERVED_303', + 304: 'CB_PERF_SEL_RESERVED_304', + 305: 'CB_PERF_SEL_RESERVED_305', + 306: 'CB_PERF_SEL_RESERVED_306', + 307: 'CB_PERF_SEL_RESERVED_307', + 308: 'CB_PERF_SEL_RESERVED_308', + 309: 'CB_PERF_SEL_RESERVED_309', + 310: 'CB_PERF_SEL_RESERVED_310', + 311: 'CB_PERF_SEL_RESERVED_311', + 312: 'CB_PERF_SEL_RESERVED_312', + 313: 'CB_PERF_SEL_RESERVED_313', + 314: 'CB_PERF_SEL_RESERVED_314', + 315: 'CB_PERF_SEL_RESERVED_315', + 316: 'CB_PERF_SEL_RESERVED_316', + 317: 'CB_PERF_SEL_RESERVED_317', + 318: 'CB_PERF_SEL_RESERVED_318', + 319: 'CB_PERF_SEL_RESERVED_319', + 320: 'CB_PERF_SEL_RESERVED_320', + 321: 'CB_PERF_SEL_RESERVED_321', + 322: 'CB_PERF_SEL_RESERVED_322', + 323: 'CB_PERF_SEL_RESERVED_323', + 324: 'CB_PERF_SEL_RESERVED_324', + 325: 'CB_PERF_SEL_RESERVED_325', + 326: 'CB_PERF_SEL_RESERVED_326', + 327: 'CB_PERF_SEL_RESERVED_327', + 328: 'CB_PERF_SEL_RESERVED_328', + 329: 'CB_PERF_SEL_RESERVED_329', + 330: 'CB_PERF_SEL_RESERVED_330', + 331: 'CB_PERF_SEL_RESERVED_331', + 332: 'CB_PERF_SEL_RESERVED_332', + 333: 'CB_PERF_SEL_RESERVED_333', + 334: 'CB_PERF_SEL_RESERVED_334', + 335: 'CB_PERF_SEL_RESERVED_335', + 336: 'CB_PERF_SEL_RESERVED_336', + 337: 'CB_PERF_SEL_RESERVED_337', + 338: 'CB_PERF_SEL_RESERVED_338', + 339: 'CB_PERF_SEL_RESERVED_339', + 340: 'CB_PERF_SEL_RESERVED_340', + 341: 'CB_PERF_SEL_RESERVED_341', + 342: 'CB_PERF_SEL_RESERVED_342', + 343: 'CB_PERF_SEL_RESERVED_343', + 344: 'CB_PERF_SEL_RESERVED_344', + 345: 'CB_PERF_SEL_RESERVED_345', + 346: 'CB_PERF_SEL_RESERVED_346', + 347: 'CB_PERF_SEL_RESERVED_347', + 348: 'CB_PERF_SEL_RESERVED_348', + 349: 'CB_PERF_SEL_RESERVED_349', + 350: 'CB_PERF_SEL_RESERVED_350', + 351: 'CB_PERF_SEL_RESERVED_351', + 352: 'CB_PERF_SEL_RESERVED_352', + 353: 'CB_PERF_SEL_RESERVED_353', + 354: 'CB_PERF_SEL_RESERVED_354', + 355: 'CB_PERF_SEL_RESERVED_355', + 356: 'CB_PERF_SEL_RESERVED_356', + 357: 'CB_PERF_SEL_RESERVED_357', + 358: 'CB_PERF_SEL_RESERVED_358', + 359: 'CB_PERF_SEL_RESERVED_359', + 360: 'CB_PERF_SEL_RESERVED_360', + 361: 'CB_PERF_SEL_RESERVED_361', + 362: 'CB_PERF_SEL_RESERVED_362', + 363: 'CB_PERF_SEL_RESERVED_363', + 364: 'CB_PERF_SEL_RESERVED_364', + 365: 'CB_PERF_SEL_RESERVED_365', + 366: 'CB_PERF_SEL_RESERVED_366', + 367: 'CB_PERF_SEL_RESERVED_367', + 368: 'CB_PERF_SEL_RESERVED_368', + 369: 'CB_PERF_SEL_RESERVED_369', + 370: 'CB_PERF_SEL_RESERVED_370', + 371: 'CB_PERF_SEL_RESERVED_371', + 372: 'CB_PERF_SEL_RESERVED_372', + 373: 'CB_PERF_SEL_RESERVED_373', + 374: 'CB_PERF_SEL_RESERVED_374', + 375: 'CB_PERF_SEL_RESERVED_375', + 376: 'CB_PERF_SEL_RESERVED_376', + 377: 'CB_PERF_SEL_RESERVED_377', + 378: 'CB_PERF_SEL_RESERVED_378', + 379: 'CB_PERF_SEL_RESERVED_379', + 380: 'CB_PERF_SEL_RESERVED_380', + 381: 'CB_PERF_SEL_RESERVED_381', + 382: 'CB_PERF_SEL_RESERVED_382', + 383: 'CB_PERF_SEL_RESERVED_383', + 384: 'CB_PERF_SEL_RESERVED_384', + 385: 'CB_PERF_SEL_RESERVED_385', + 386: 'CB_PERF_SEL_RESERVED_386', + 387: 'CB_PERF_SEL_RESERVED_387', + 388: 'CB_PERF_SEL_RESERVED_388', + 389: 'CB_PERF_SEL_RESERVED_389', + 390: 'CB_PERF_SEL_RESERVED_390', + 391: 'CB_PERF_SEL_RESERVED_391', + 392: 'CB_PERF_SEL_RESERVED_392', + 393: 'CB_PERF_SEL_RESERVED_393', + 394: 'CB_PERF_SEL_RESERVED_394', + 395: 'CB_PERF_SEL_RESERVED_395', + 396: 'CB_PERF_SEL_RESERVED_396', + 397: 'CB_PERF_SEL_RESERVED_397', + 398: 'CB_PERF_SEL_RESERVED_398', + 399: 'CB_PERF_SEL_RESERVED_399', + 400: 'CB_PERF_SEL_RESERVED_400', + 401: 'CB_PERF_SEL_RESERVED_401', + 402: 'CB_PERF_SEL_RESERVED_402', + 403: 'CB_PERF_SEL_RESERVED_403', + 404: 'CB_PERF_SEL_RESERVED_404', + 405: 'CB_PERF_SEL_RESERVED_405', + 406: 'CB_PERF_SEL_RESERVED_406', + 407: 'CB_PERF_SEL_RESERVED_407', + 408: 'CB_PERF_SEL_RESERVED_408', + 409: 'CB_PERF_SEL_RESERVED_409', + 410: 'CB_PERF_SEL_RESERVED_410', + 411: 'CB_PERF_SEL_RESERVED_411', + 412: 'CB_PERF_SEL_RESERVED_412', + 413: 'CB_PERF_SEL_RESERVED_413', + 414: 'CB_PERF_SEL_RESERVED_414', + 415: 'CB_PERF_SEL_RESERVED_415', + 416: 'CB_PERF_SEL_RESERVED_416', + 417: 'CB_PERF_SEL_RESERVED_417', + 418: 'CB_PERF_SEL_RESERVED_418', + 419: 'CB_PERF_SEL_RESERVED_419', + 420: 'CB_PERF_SEL_RESERVED_420', + 421: 'CB_PERF_SEL_RESERVED_421', + 422: 'CB_PERF_SEL_RESERVED_422', + 423: 'CB_PERF_SEL_RESERVED_423', + 424: 'CB_PERF_SEL_RESERVED_424', + 425: 'CB_PERF_SEL_RESERVED_425', + 426: 'CB_PERF_SEL_RESERVED_426', + 427: 'CB_PERF_SEL_RESERVED_427', + 428: 'CB_PERF_SEL_RESERVED_428', + 429: 'CB_PERF_SEL_RESERVED_429', + 430: 'CB_PERF_SEL_RESERVED_430', + 431: 'CB_PERF_SEL_RESERVED_431', + 432: 'CB_PERF_SEL_RESERVED_432', + 433: 'CB_PERF_SEL_RESERVED_433', + 434: 'CB_PERF_SEL_RESERVED_434', + 435: 'CB_PERF_SEL_RESERVED_435', + 436: 'CB_PERF_SEL_RESERVED_436', + 437: 'CB_PERF_SEL_RESERVED_437', + 438: 'CB_PERF_SEL_RESERVED_438', + 439: 'CB_PERF_SEL_RESERVED_439', + 440: 'CB_PERF_SEL_RESERVED_440', + 441: 'CB_PERF_SEL_RESERVED_441', + 442: 'CB_PERF_SEL_RESERVED_442', + 443: 'CB_PERF_SEL_RESERVED_443', + 444: 'CB_PERF_SEL_RESERVED_444', + 445: 'CB_PERF_SEL_RESERVED_445', + 446: 'CB_PERF_SEL_RESERVED_446', + 447: 'CB_PERF_SEL_RESERVED_447', + 448: 'CB_PERF_SEL_RESERVED_448', + 449: 'CB_PERF_SEL_RESERVED_449', + 450: 'CB_PERF_SEL_RESERVED_450', + 451: 'CB_PERF_SEL_RESERVED_451', + 452: 'CB_PERF_SEL_RESERVED_452', + 453: 'CB_PERF_SEL_RESERVED_453', + 454: 'CB_PERF_SEL_RESERVED_454', + 455: 'CB_PERF_SEL_RESERVED_455', + 456: 'CB_PERF_SEL_RESERVED_456', + 457: 'CB_PERF_SEL_RESERVED_457', + 458: 'CB_PERF_SEL_RESERVED_458', + 459: 'CB_PERF_SEL_RESERVED_459', + 460: 'CB_PERF_SEL_RESERVED_460', + 461: 'CB_PERF_SEL_RESERVED_461', + 462: 'CB_PERF_SEL_RESERVED_462', + 463: 'CB_PERF_SEL_RESERVED_463', + 464: 'CB_PERF_SEL_RESERVED_464', + 465: 'CB_PERF_SEL_RESERVED_465', +} +CB_PERF_SEL_NONE = 0 +CB_PERF_SEL_DRAWN_PIXEL = 1 +CB_PERF_SEL_DRAWN_QUAD = 2 +CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 3 +CB_PERF_SEL_DRAWN_TILE = 4 +CB_PERF_SEL_FILTER_DRAWN_PIXEL = 5 +CB_PERF_SEL_FILTER_DRAWN_QUAD = 6 +CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT = 7 +CB_PERF_SEL_FILTER_DRAWN_TILE = 8 +CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN = 9 +CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT = 10 +CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN = 11 +CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT = 12 +CB_PERF_SEL_CC_MC_WRITE_REQUEST = 13 +CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 14 +CB_PERF_SEL_CC_MC_READ_REQUEST = 15 +CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 16 +CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 17 +CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 18 +CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 19 +CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 20 +CB_PERF_SEL_RESERVED_21 = 21 +CB_PERF_SEL_RESERVED_22 = 22 +CB_PERF_SEL_RESERVED_23 = 23 +CB_PERF_SEL_RESERVED_24 = 24 +CB_PERF_SEL_RESERVED_25 = 25 +CB_PERF_SEL_RESERVED_26 = 26 +CB_PERF_SEL_RESERVED_27 = 27 +CB_PERF_SEL_RESERVED_28 = 28 +CB_PERF_SEL_RESERVED_29 = 29 +CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY = 30 +CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB = 31 +CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY = 32 +CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB = 33 +CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY = 34 +CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB = 35 +CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY = 36 +CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB = 37 +CB_PERF_SEL_RESERVED_38 = 38 +CB_PERF_SEL_RESERVED_39 = 39 +CB_PERF_SEL_RESERVED_40 = 40 +CB_PERF_SEL_RESERVED_41 = 41 +CB_PERF_SEL_RESERVED_42 = 42 +CB_PERF_SEL_RESERVED_43 = 43 +CB_PERF_SEL_RESERVED_44 = 44 +CB_PERF_SEL_RESERVED_45 = 45 +CB_PERF_SEL_RESERVED_46 = 46 +CB_PERF_SEL_RESERVED_47 = 47 +CB_PERF_SEL_RESERVED_48 = 48 +CB_PERF_SEL_RESERVED_49 = 49 +CB_PERF_SEL_STATIC_CLOCK_EN = 50 +CB_PERF_SEL_PERFMON_CLOCK_EN = 51 +CB_PERF_SEL_BLEND_CLOCK_EN = 52 +CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 53 +CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 54 +CB_PERF_SEL_GRBM_CLOCK_EN = 55 +CB_PERF_SEL_MEMARB_CLOCK_EN = 56 +CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 57 +CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 58 +CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 59 +CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 60 +CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 61 +CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 62 +CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 63 +CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 64 +CB_PERF_SEL_RESERVED_65 = 65 +CB_PERF_SEL_RESERVED_66 = 66 +CB_PERF_SEL_RESERVED_67 = 67 +CB_PERF_SEL_RESERVED_68 = 68 +CB_PERF_SEL_RESERVED_69 = 69 +CB_PERF_SEL_RESERVED_70 = 70 +CB_PERF_SEL_RESERVED_71 = 71 +CB_PERF_SEL_RESERVED_72 = 72 +CB_PERF_SEL_RESERVED_73 = 73 +CB_PERF_SEL_RESERVED_74 = 74 +CB_PERF_SEL_RESERVED_75 = 75 +CB_PERF_SEL_RESERVED_76 = 76 +CB_PERF_SEL_RESERVED_77 = 77 +CB_PERF_SEL_RESERVED_78 = 78 +CB_PERF_SEL_RESERVED_79 = 79 +CB_PERF_SEL_RESERVED_80 = 80 +CB_PERF_SEL_RESERVED_81 = 81 +CB_PERF_SEL_RESERVED_82 = 82 +CB_PERF_SEL_RESERVED_83 = 83 +CB_PERF_SEL_RESERVED_84 = 84 +CB_PERF_SEL_RESERVED_85 = 85 +CB_PERF_SEL_RESERVED_86 = 86 +CB_PERF_SEL_RESERVED_87 = 87 +CB_PERF_SEL_RESERVED_88 = 88 +CB_PERF_SEL_RESERVED_89 = 89 +CB_PERF_SEL_RESERVED_90 = 90 +CB_PERF_SEL_RESERVED_91 = 91 +CB_PERF_SEL_RESERVED_92 = 92 +CB_PERF_SEL_RESERVED_93 = 93 +CB_PERF_SEL_RESERVED_94 = 94 +CB_PERF_SEL_RESERVED_95 = 95 +CB_PERF_SEL_RESERVED_96 = 96 +CB_PERF_SEL_RESERVED_97 = 97 +CB_PERF_SEL_RESERVED_98 = 98 +CB_PERF_SEL_RESERVED_99 = 99 +CB_PERF_SEL_CC_TAG_HIT = 100 +CB_PERF_SEL_CC_CACHE_TAG_MISS = 101 +CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 102 +CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 103 +CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 104 +CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 105 +CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 106 +CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 107 +CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 108 +CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 109 +CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 110 +CB_PERF_SEL_CC_CACHE_STALL = 111 +CB_PERF_SEL_CC_CACHE_FLUSH = 112 +CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 113 +CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 114 +CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 115 +CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 116 +CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 117 +CB_PERF_SEL_RESERVED_118 = 118 +CB_PERF_SEL_RESERVED_119 = 119 +CB_PERF_SEL_RESERVED_120 = 120 +CB_PERF_SEL_RESERVED_121 = 121 +CB_PERF_SEL_RESERVED_122 = 122 +CB_PERF_SEL_RESERVED_123 = 123 +CB_PERF_SEL_RESERVED_124 = 124 +CB_PERF_SEL_RESERVED_125 = 125 +CB_PERF_SEL_RESERVED_126 = 126 +CB_PERF_SEL_RESERVED_127 = 127 +CB_PERF_SEL_RESERVED_128 = 128 +CB_PERF_SEL_RESERVED_129 = 129 +CB_PERF_SEL_RESERVED_130 = 130 +CB_PERF_SEL_RESERVED_131 = 131 +CB_PERF_SEL_RESERVED_132 = 132 +CB_PERF_SEL_RESERVED_133 = 133 +CB_PERF_SEL_RESERVED_134 = 134 +CB_PERF_SEL_RESERVED_135 = 135 +CB_PERF_SEL_RESERVED_136 = 136 +CB_PERF_SEL_RESERVED_137 = 137 +CB_PERF_SEL_RESERVED_138 = 138 +CB_PERF_SEL_RESERVED_139 = 139 +CB_PERF_SEL_RESERVED_140 = 140 +CB_PERF_SEL_RESERVED_141 = 141 +CB_PERF_SEL_RESERVED_142 = 142 +CB_PERF_SEL_RESERVED_143 = 143 +CB_PERF_SEL_RESERVED_144 = 144 +CB_PERF_SEL_RESERVED_145 = 145 +CB_PERF_SEL_RESERVED_146 = 146 +CB_PERF_SEL_RESERVED_147 = 147 +CB_PERF_SEL_RESERVED_148 = 148 +CB_PERF_SEL_RESERVED_149 = 149 +CB_PERF_SEL_DCC_CACHE_PERF_HIT = 150 +CB_PERF_SEL_DCC_CACHE_TAG_MISS = 151 +CB_PERF_SEL_DCC_CACHE_SECTOR_MISS = 152 +CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL = 153 +CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 154 +CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 155 +CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 156 +CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL = 157 +CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL = 158 +CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL = 159 +CB_PERF_SEL_DCC_CACHE_STALL = 160 +CB_PERF_SEL_DCC_CACHE_FLUSH = 161 +CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED = 162 +CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 163 +CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED = 164 +CB_PERF_SEL_RESERVED_165 = 165 +CB_PERF_SEL_RESERVED_166 = 166 +CB_PERF_SEL_RESERVED_167 = 167 +CB_PERF_SEL_RESERVED_168 = 168 +CB_PERF_SEL_RESERVED_169 = 169 +CB_PERF_SEL_RESERVED_170 = 170 +CB_PERF_SEL_RESERVED_171 = 171 +CB_PERF_SEL_RESERVED_172 = 172 +CB_PERF_SEL_RESERVED_173 = 173 +CB_PERF_SEL_RESERVED_174 = 174 +CB_PERF_SEL_RESERVED_175 = 175 +CB_PERF_SEL_RESERVED_176 = 176 +CB_PERF_SEL_RESERVED_177 = 177 +CB_PERF_SEL_RESERVED_178 = 178 +CB_PERF_SEL_RESERVED_179 = 179 +CB_PERF_SEL_RESERVED_180 = 180 +CB_PERF_SEL_RESERVED_181 = 181 +CB_PERF_SEL_RESERVED_182 = 182 +CB_PERF_SEL_RESERVED_183 = 183 +CB_PERF_SEL_RESERVED_184 = 184 +CB_PERF_SEL_RESERVED_185 = 185 +CB_PERF_SEL_RESERVED_186 = 186 +CB_PERF_SEL_RESERVED_187 = 187 +CB_PERF_SEL_RESERVED_188 = 188 +CB_PERF_SEL_RESERVED_189 = 189 +CB_PERF_SEL_RESERVED_190 = 190 +CB_PERF_SEL_RESERVED_191 = 191 +CB_PERF_SEL_RESERVED_192 = 192 +CB_PERF_SEL_RESERVED_193 = 193 +CB_PERF_SEL_RESERVED_194 = 194 +CB_PERF_SEL_RESERVED_195 = 195 +CB_PERF_SEL_RESERVED_196 = 196 +CB_PERF_SEL_RESERVED_197 = 197 +CB_PERF_SEL_RESERVED_198 = 198 +CB_PERF_SEL_RESERVED_199 = 199 +CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 200 +CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 201 +CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 202 +CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 203 +CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 204 +CB_PERF_SEL_RESERVED_205 = 205 +CB_PERF_SEL_RESERVED_206 = 206 +CB_PERF_SEL_RESERVED_207 = 207 +CB_PERF_SEL_RESERVED_208 = 208 +CB_PERF_SEL_RESERVED_209 = 209 +CB_PERF_SEL_RESERVED_210 = 210 +CB_PERF_SEL_RESERVED_211 = 211 +CB_PERF_SEL_RESERVED_212 = 212 +CB_PERF_SEL_RESERVED_213 = 213 +CB_PERF_SEL_RESERVED_214 = 214 +CB_PERF_SEL_RESERVED_215 = 215 +CB_PERF_SEL_RESERVED_216 = 216 +CB_PERF_SEL_RESERVED_217 = 217 +CB_PERF_SEL_RESERVED_218 = 218 +CB_PERF_SEL_RESERVED_219 = 219 +CB_PERF_SEL_RESERVED_220 = 220 +CB_PERF_SEL_RESERVED_221 = 221 +CB_PERF_SEL_RESERVED_222 = 222 +CB_PERF_SEL_RESERVED_223 = 223 +CB_PERF_SEL_RESERVED_224 = 224 +CB_PERF_SEL_RESERVED_225 = 225 +CB_PERF_SEL_RESERVED_226 = 226 +CB_PERF_SEL_RESERVED_227 = 227 +CB_PERF_SEL_RESERVED_228 = 228 +CB_PERF_SEL_RESERVED_229 = 229 +CB_PERF_SEL_RESERVED_230 = 230 +CB_PERF_SEL_RESERVED_231 = 231 +CB_PERF_SEL_RESERVED_232 = 232 +CB_PERF_SEL_RESERVED_233 = 233 +CB_PERF_SEL_RESERVED_234 = 234 +CB_PERF_SEL_RESERVED_235 = 235 +CB_PERF_SEL_RESERVED_236 = 236 +CB_PERF_SEL_RESERVED_237 = 237 +CB_PERF_SEL_RESERVED_238 = 238 +CB_PERF_SEL_RESERVED_239 = 239 +CB_PERF_SEL_RESERVED_240 = 240 +CB_PERF_SEL_RESERVED_241 = 241 +CB_PERF_SEL_RESERVED_242 = 242 +CB_PERF_SEL_RESERVED_243 = 243 +CB_PERF_SEL_RESERVED_244 = 244 +CB_PERF_SEL_RESERVED_245 = 245 +CB_PERF_SEL_RESERVED_246 = 246 +CB_PERF_SEL_RESERVED_247 = 247 +CB_PERF_SEL_RESERVED_248 = 248 +CB_PERF_SEL_RESERVED_249 = 249 +CB_PERF_SEL_EVENT = 250 +CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 251 +CB_PERF_SEL_EVENT_CONTEXT_DONE = 252 +CB_PERF_SEL_EVENT_CACHE_FLUSH = 253 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 254 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 255 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 256 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 257 +CB_PERF_SEL_CC_SURFACE_SYNC = 258 +CB_PERF_SEL_RESERVED_259 = 259 +CB_PERF_SEL_RESERVED_260 = 260 +CB_PERF_SEL_RESERVED_261 = 261 +CB_PERF_SEL_RESERVED_262 = 262 +CB_PERF_SEL_RESERVED_263 = 263 +CB_PERF_SEL_RESERVED_264 = 264 +CB_PERF_SEL_RESERVED_265 = 265 +CB_PERF_SEL_RESERVED_266 = 266 +CB_PERF_SEL_RESERVED_267 = 267 +CB_PERF_SEL_RESERVED_268 = 268 +CB_PERF_SEL_RESERVED_269 = 269 +CB_PERF_SEL_RESERVED_270 = 270 +CB_PERF_SEL_RESERVED_271 = 271 +CB_PERF_SEL_RESERVED_272 = 272 +CB_PERF_SEL_RESERVED_273 = 273 +CB_PERF_SEL_RESERVED_274 = 274 +CB_PERF_SEL_RESERVED_275 = 275 +CB_PERF_SEL_RESERVED_276 = 276 +CB_PERF_SEL_RESERVED_277 = 277 +CB_PERF_SEL_RESERVED_278 = 278 +CB_PERF_SEL_RESERVED_279 = 279 +CB_PERF_SEL_RESERVED_280 = 280 +CB_PERF_SEL_RESERVED_281 = 281 +CB_PERF_SEL_RESERVED_282 = 282 +CB_PERF_SEL_RESERVED_283 = 283 +CB_PERF_SEL_RESERVED_284 = 284 +CB_PERF_SEL_RESERVED_285 = 285 +CB_PERF_SEL_RESERVED_286 = 286 +CB_PERF_SEL_RESERVED_287 = 287 +CB_PERF_SEL_RESERVED_288 = 288 +CB_PERF_SEL_RESERVED_289 = 289 +CB_PERF_SEL_RESERVED_290 = 290 +CB_PERF_SEL_RESERVED_291 = 291 +CB_PERF_SEL_RESERVED_292 = 292 +CB_PERF_SEL_RESERVED_293 = 293 +CB_PERF_SEL_RESERVED_294 = 294 +CB_PERF_SEL_RESERVED_295 = 295 +CB_PERF_SEL_RESERVED_296 = 296 +CB_PERF_SEL_RESERVED_297 = 297 +CB_PERF_SEL_RESERVED_298 = 298 +CB_PERF_SEL_RESERVED_299 = 299 +CB_PERF_SEL_NACK_CC_READ = 300 +CB_PERF_SEL_NACK_CC_WRITE = 301 +CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 302 +CB_PERF_SEL_RESERVED_303 = 303 +CB_PERF_SEL_RESERVED_304 = 304 +CB_PERF_SEL_RESERVED_305 = 305 +CB_PERF_SEL_RESERVED_306 = 306 +CB_PERF_SEL_RESERVED_307 = 307 +CB_PERF_SEL_RESERVED_308 = 308 +CB_PERF_SEL_RESERVED_309 = 309 +CB_PERF_SEL_RESERVED_310 = 310 +CB_PERF_SEL_RESERVED_311 = 311 +CB_PERF_SEL_RESERVED_312 = 312 +CB_PERF_SEL_RESERVED_313 = 313 +CB_PERF_SEL_RESERVED_314 = 314 +CB_PERF_SEL_RESERVED_315 = 315 +CB_PERF_SEL_RESERVED_316 = 316 +CB_PERF_SEL_RESERVED_317 = 317 +CB_PERF_SEL_RESERVED_318 = 318 +CB_PERF_SEL_RESERVED_319 = 319 +CB_PERF_SEL_RESERVED_320 = 320 +CB_PERF_SEL_RESERVED_321 = 321 +CB_PERF_SEL_RESERVED_322 = 322 +CB_PERF_SEL_RESERVED_323 = 323 +CB_PERF_SEL_RESERVED_324 = 324 +CB_PERF_SEL_RESERVED_325 = 325 +CB_PERF_SEL_RESERVED_326 = 326 +CB_PERF_SEL_RESERVED_327 = 327 +CB_PERF_SEL_RESERVED_328 = 328 +CB_PERF_SEL_RESERVED_329 = 329 +CB_PERF_SEL_RESERVED_330 = 330 +CB_PERF_SEL_RESERVED_331 = 331 +CB_PERF_SEL_RESERVED_332 = 332 +CB_PERF_SEL_RESERVED_333 = 333 +CB_PERF_SEL_RESERVED_334 = 334 +CB_PERF_SEL_RESERVED_335 = 335 +CB_PERF_SEL_RESERVED_336 = 336 +CB_PERF_SEL_RESERVED_337 = 337 +CB_PERF_SEL_RESERVED_338 = 338 +CB_PERF_SEL_RESERVED_339 = 339 +CB_PERF_SEL_RESERVED_340 = 340 +CB_PERF_SEL_RESERVED_341 = 341 +CB_PERF_SEL_RESERVED_342 = 342 +CB_PERF_SEL_RESERVED_343 = 343 +CB_PERF_SEL_RESERVED_344 = 344 +CB_PERF_SEL_RESERVED_345 = 345 +CB_PERF_SEL_RESERVED_346 = 346 +CB_PERF_SEL_RESERVED_347 = 347 +CB_PERF_SEL_RESERVED_348 = 348 +CB_PERF_SEL_RESERVED_349 = 349 +CB_PERF_SEL_RESERVED_350 = 350 +CB_PERF_SEL_RESERVED_351 = 351 +CB_PERF_SEL_RESERVED_352 = 352 +CB_PERF_SEL_RESERVED_353 = 353 +CB_PERF_SEL_RESERVED_354 = 354 +CB_PERF_SEL_RESERVED_355 = 355 +CB_PERF_SEL_RESERVED_356 = 356 +CB_PERF_SEL_RESERVED_357 = 357 +CB_PERF_SEL_RESERVED_358 = 358 +CB_PERF_SEL_RESERVED_359 = 359 +CB_PERF_SEL_RESERVED_360 = 360 +CB_PERF_SEL_RESERVED_361 = 361 +CB_PERF_SEL_RESERVED_362 = 362 +CB_PERF_SEL_RESERVED_363 = 363 +CB_PERF_SEL_RESERVED_364 = 364 +CB_PERF_SEL_RESERVED_365 = 365 +CB_PERF_SEL_RESERVED_366 = 366 +CB_PERF_SEL_RESERVED_367 = 367 +CB_PERF_SEL_RESERVED_368 = 368 +CB_PERF_SEL_RESERVED_369 = 369 +CB_PERF_SEL_RESERVED_370 = 370 +CB_PERF_SEL_RESERVED_371 = 371 +CB_PERF_SEL_RESERVED_372 = 372 +CB_PERF_SEL_RESERVED_373 = 373 +CB_PERF_SEL_RESERVED_374 = 374 +CB_PERF_SEL_RESERVED_375 = 375 +CB_PERF_SEL_RESERVED_376 = 376 +CB_PERF_SEL_RESERVED_377 = 377 +CB_PERF_SEL_RESERVED_378 = 378 +CB_PERF_SEL_RESERVED_379 = 379 +CB_PERF_SEL_RESERVED_380 = 380 +CB_PERF_SEL_RESERVED_381 = 381 +CB_PERF_SEL_RESERVED_382 = 382 +CB_PERF_SEL_RESERVED_383 = 383 +CB_PERF_SEL_RESERVED_384 = 384 +CB_PERF_SEL_RESERVED_385 = 385 +CB_PERF_SEL_RESERVED_386 = 386 +CB_PERF_SEL_RESERVED_387 = 387 +CB_PERF_SEL_RESERVED_388 = 388 +CB_PERF_SEL_RESERVED_389 = 389 +CB_PERF_SEL_RESERVED_390 = 390 +CB_PERF_SEL_RESERVED_391 = 391 +CB_PERF_SEL_RESERVED_392 = 392 +CB_PERF_SEL_RESERVED_393 = 393 +CB_PERF_SEL_RESERVED_394 = 394 +CB_PERF_SEL_RESERVED_395 = 395 +CB_PERF_SEL_RESERVED_396 = 396 +CB_PERF_SEL_RESERVED_397 = 397 +CB_PERF_SEL_RESERVED_398 = 398 +CB_PERF_SEL_RESERVED_399 = 399 +CB_PERF_SEL_RESERVED_400 = 400 +CB_PERF_SEL_RESERVED_401 = 401 +CB_PERF_SEL_RESERVED_402 = 402 +CB_PERF_SEL_RESERVED_403 = 403 +CB_PERF_SEL_RESERVED_404 = 404 +CB_PERF_SEL_RESERVED_405 = 405 +CB_PERF_SEL_RESERVED_406 = 406 +CB_PERF_SEL_RESERVED_407 = 407 +CB_PERF_SEL_RESERVED_408 = 408 +CB_PERF_SEL_RESERVED_409 = 409 +CB_PERF_SEL_RESERVED_410 = 410 +CB_PERF_SEL_RESERVED_411 = 411 +CB_PERF_SEL_RESERVED_412 = 412 +CB_PERF_SEL_RESERVED_413 = 413 +CB_PERF_SEL_RESERVED_414 = 414 +CB_PERF_SEL_RESERVED_415 = 415 +CB_PERF_SEL_RESERVED_416 = 416 +CB_PERF_SEL_RESERVED_417 = 417 +CB_PERF_SEL_RESERVED_418 = 418 +CB_PERF_SEL_RESERVED_419 = 419 +CB_PERF_SEL_RESERVED_420 = 420 +CB_PERF_SEL_RESERVED_421 = 421 +CB_PERF_SEL_RESERVED_422 = 422 +CB_PERF_SEL_RESERVED_423 = 423 +CB_PERF_SEL_RESERVED_424 = 424 +CB_PERF_SEL_RESERVED_425 = 425 +CB_PERF_SEL_RESERVED_426 = 426 +CB_PERF_SEL_RESERVED_427 = 427 +CB_PERF_SEL_RESERVED_428 = 428 +CB_PERF_SEL_RESERVED_429 = 429 +CB_PERF_SEL_RESERVED_430 = 430 +CB_PERF_SEL_RESERVED_431 = 431 +CB_PERF_SEL_RESERVED_432 = 432 +CB_PERF_SEL_RESERVED_433 = 433 +CB_PERF_SEL_RESERVED_434 = 434 +CB_PERF_SEL_RESERVED_435 = 435 +CB_PERF_SEL_RESERVED_436 = 436 +CB_PERF_SEL_RESERVED_437 = 437 +CB_PERF_SEL_RESERVED_438 = 438 +CB_PERF_SEL_RESERVED_439 = 439 +CB_PERF_SEL_RESERVED_440 = 440 +CB_PERF_SEL_RESERVED_441 = 441 +CB_PERF_SEL_RESERVED_442 = 442 +CB_PERF_SEL_RESERVED_443 = 443 +CB_PERF_SEL_RESERVED_444 = 444 +CB_PERF_SEL_RESERVED_445 = 445 +CB_PERF_SEL_RESERVED_446 = 446 +CB_PERF_SEL_RESERVED_447 = 447 +CB_PERF_SEL_RESERVED_448 = 448 +CB_PERF_SEL_RESERVED_449 = 449 +CB_PERF_SEL_RESERVED_450 = 450 +CB_PERF_SEL_RESERVED_451 = 451 +CB_PERF_SEL_RESERVED_452 = 452 +CB_PERF_SEL_RESERVED_453 = 453 +CB_PERF_SEL_RESERVED_454 = 454 +CB_PERF_SEL_RESERVED_455 = 455 +CB_PERF_SEL_RESERVED_456 = 456 +CB_PERF_SEL_RESERVED_457 = 457 +CB_PERF_SEL_RESERVED_458 = 458 +CB_PERF_SEL_RESERVED_459 = 459 +CB_PERF_SEL_RESERVED_460 = 460 +CB_PERF_SEL_RESERVED_461 = 461 +CB_PERF_SEL_RESERVED_462 = 462 +CB_PERF_SEL_RESERVED_463 = 463 +CB_PERF_SEL_RESERVED_464 = 464 +CB_PERF_SEL_RESERVED_465 = 465 +CBPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBRamList' +CBRamList__enumvalues = { + 0: 'CB_DCG_CCC_CAS_TAG_ARRAY', + 1: 'CB_DCG_CCC_CAS_FRAG_PTR', + 2: 'CB_DCG_CCC_CAS_COLOR_PTR', + 3: 'CB_DCG_CCC_CAS_SURF_PARAM', + 4: 'CB_DCG_CCC_CAS_KEYID', + 5: 'CB_DCG_BACKEND_RDLAT_FIFO', + 6: 'CB_DCG_FRONTEND_RDLAT_FIFO', + 7: 'CB_DCG_SRC_FIFO', + 8: 'CB_DCG_COLOR_STORE', + 9: 'CB_DCG_COLOR_STORE_DIRTY_BYTE', + 10: 'CB_DCG_FMASK_CACHE_STORE', + 11: 'CB_DCG_READ_SKID_FIFO', + 12: 'CB_DCG_QUAD_PTR_FIFO', + 13: 'CB_DCG_OUTPUT_FIFO', + 14: 'CB_DCG_DCC_CACHE', + 15: 'CB_DCG_DCC_DIRTY_BITS', + 16: 'CB_DCG_QBLOCK_ALLOC', +} +CB_DCG_CCC_CAS_TAG_ARRAY = 0 +CB_DCG_CCC_CAS_FRAG_PTR = 1 +CB_DCG_CCC_CAS_COLOR_PTR = 2 +CB_DCG_CCC_CAS_SURF_PARAM = 3 +CB_DCG_CCC_CAS_KEYID = 4 +CB_DCG_BACKEND_RDLAT_FIFO = 5 +CB_DCG_FRONTEND_RDLAT_FIFO = 6 +CB_DCG_SRC_FIFO = 7 +CB_DCG_COLOR_STORE = 8 +CB_DCG_COLOR_STORE_DIRTY_BYTE = 9 +CB_DCG_FMASK_CACHE_STORE = 10 +CB_DCG_READ_SKID_FIFO = 11 +CB_DCG_QUAD_PTR_FIFO = 12 +CB_DCG_OUTPUT_FIFO = 13 +CB_DCG_DCC_CACHE = 14 +CB_DCG_DCC_DIRTY_BITS = 15 +CB_DCG_QBLOCK_ALLOC = 16 +CBRamList = ctypes.c_uint32 # enum + +# values for enumeration 'CmaskCode' +CmaskCode__enumvalues = { + 0: 'CMASK_CLR00_F0', + 1: 'CMASK_CLR00_F1', + 2: 'CMASK_CLR00_F2', + 3: 'CMASK_CLR00_FX', + 4: 'CMASK_CLR01_F0', + 5: 'CMASK_CLR01_F1', + 6: 'CMASK_CLR01_F2', + 7: 'CMASK_CLR01_FX', + 8: 'CMASK_CLR10_F0', + 9: 'CMASK_CLR10_F1', + 10: 'CMASK_CLR10_F2', + 11: 'CMASK_CLR10_FX', + 12: 'CMASK_CLR11_F0', + 13: 'CMASK_CLR11_F1', + 14: 'CMASK_CLR11_F2', + 15: 'CMASK_CLR11_FX', +} +CMASK_CLR00_F0 = 0 +CMASK_CLR00_F1 = 1 +CMASK_CLR00_F2 = 2 +CMASK_CLR00_FX = 3 +CMASK_CLR01_F0 = 4 +CMASK_CLR01_F1 = 5 +CMASK_CLR01_F2 = 6 +CMASK_CLR01_FX = 7 +CMASK_CLR10_F0 = 8 +CMASK_CLR10_F1 = 9 +CMASK_CLR10_F2 = 10 +CMASK_CLR10_FX = 11 +CMASK_CLR11_F0 = 12 +CMASK_CLR11_F1 = 13 +CMASK_CLR11_F2 = 14 +CMASK_CLR11_FX = 15 +CmaskCode = ctypes.c_uint32 # enum + +# values for enumeration 'CombFunc' +CombFunc__enumvalues = { + 0: 'COMB_DST_PLUS_SRC', + 1: 'COMB_SRC_MINUS_DST', + 2: 'COMB_MIN_DST_SRC', + 3: 'COMB_MAX_DST_SRC', + 4: 'COMB_DST_MINUS_SRC', +} +COMB_DST_PLUS_SRC = 0 +COMB_SRC_MINUS_DST = 1 +COMB_MIN_DST_SRC = 2 +COMB_MAX_DST_SRC = 3 +COMB_DST_MINUS_SRC = 4 +CombFunc = ctypes.c_uint32 # enum + +# values for enumeration 'MemArbMode' +MemArbMode__enumvalues = { + 0: 'MEM_ARB_MODE_FIXED', + 1: 'MEM_ARB_MODE_AGE', + 2: 'MEM_ARB_MODE_WEIGHT', + 3: 'MEM_ARB_MODE_BOTH', +} +MEM_ARB_MODE_FIXED = 0 +MEM_ARB_MODE_AGE = 1 +MEM_ARB_MODE_WEIGHT = 2 +MEM_ARB_MODE_BOTH = 3 +MemArbMode = ctypes.c_uint32 # enum + +# values for enumeration 'SourceFormat' +SourceFormat__enumvalues = { + 0: 'EXPORT_4C_32BPC', + 1: 'EXPORT_4C_16BPC', + 2: 'EXPORT_2C_32BPC_GR', + 3: 'EXPORT_2C_32BPC_AR', +} +EXPORT_4C_32BPC = 0 +EXPORT_4C_16BPC = 1 +EXPORT_2C_32BPC_GR = 2 +EXPORT_2C_32BPC_AR = 3 +SourceFormat = ctypes.c_uint32 # enum + +# values for enumeration 'BinEventCntl' +BinEventCntl__enumvalues = { + 0: 'BINNER_BREAK_BATCH', + 1: 'BINNER_PIPELINE', + 2: 'BINNER_DROP', + 3: 'BINNER_PIPELINE_BREAK', +} +BINNER_BREAK_BATCH = 0 +BINNER_PIPELINE = 1 +BINNER_DROP = 2 +BINNER_PIPELINE_BREAK = 3 +BinEventCntl = ctypes.c_uint32 # enum + +# values for enumeration 'BinMapMode' +BinMapMode__enumvalues = { + 0: 'BIN_MAP_MODE_NONE', + 1: 'BIN_MAP_MODE_RTA_INDEX', + 2: 'BIN_MAP_MODE_POPS', +} +BIN_MAP_MODE_NONE = 0 +BIN_MAP_MODE_RTA_INDEX = 1 +BIN_MAP_MODE_POPS = 2 +BinMapMode = ctypes.c_uint32 # enum + +# values for enumeration 'BinSizeExtend' +BinSizeExtend__enumvalues = { + 0: 'BIN_SIZE_32_PIXELS', + 1: 'BIN_SIZE_64_PIXELS', + 2: 'BIN_SIZE_128_PIXELS', + 3: 'BIN_SIZE_256_PIXELS', + 4: 'BIN_SIZE_512_PIXELS', +} +BIN_SIZE_32_PIXELS = 0 +BIN_SIZE_64_PIXELS = 1 +BIN_SIZE_128_PIXELS = 2 +BIN_SIZE_256_PIXELS = 3 +BIN_SIZE_512_PIXELS = 4 +BinSizeExtend = ctypes.c_uint32 # enum + +# values for enumeration 'BinningMode' +BinningMode__enumvalues = { + 0: 'BINNING_ALLOWED', + 1: 'FORCE_BINNING_ON', + 2: 'DISABLE_BINNING_USE_NEW_SC', + 3: 'DISABLE_BINNING_USE_LEGACY_SC', +} +BINNING_ALLOWED = 0 +FORCE_BINNING_ON = 1 +DISABLE_BINNING_USE_NEW_SC = 2 +DISABLE_BINNING_USE_LEGACY_SC = 3 +BinningMode = ctypes.c_uint32 # enum + +# values for enumeration 'CovToShaderSel' +CovToShaderSel__enumvalues = { + 0: 'INPUT_COVERAGE', + 1: 'INPUT_INNER_COVERAGE', + 2: 'INPUT_DEPTH_COVERAGE', + 3: 'RAW', +} +INPUT_COVERAGE = 0 +INPUT_INNER_COVERAGE = 1 +INPUT_DEPTH_COVERAGE = 2 +RAW = 3 +CovToShaderSel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrMap' +PkrMap__enumvalues = { + 0: 'RASTER_CONFIG_PKR_MAP_0', + 1: 'RASTER_CONFIG_PKR_MAP_1', + 2: 'RASTER_CONFIG_PKR_MAP_2', + 3: 'RASTER_CONFIG_PKR_MAP_3', +} +RASTER_CONFIG_PKR_MAP_0 = 0 +RASTER_CONFIG_PKR_MAP_1 = 1 +RASTER_CONFIG_PKR_MAP_2 = 2 +RASTER_CONFIG_PKR_MAP_3 = 3 +PkrMap = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel' +PkrXsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL_0', + 1: 'RASTER_CONFIG_PKR_XSEL_1', + 2: 'RASTER_CONFIG_PKR_XSEL_2', + 3: 'RASTER_CONFIG_PKR_XSEL_3', +} +RASTER_CONFIG_PKR_XSEL_0 = 0 +RASTER_CONFIG_PKR_XSEL_1 = 1 +RASTER_CONFIG_PKR_XSEL_2 = 2 +RASTER_CONFIG_PKR_XSEL_3 = 3 +PkrXsel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel2' +PkrXsel2__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL2_0', + 1: 'RASTER_CONFIG_PKR_XSEL2_1', + 2: 'RASTER_CONFIG_PKR_XSEL2_2', + 3: 'RASTER_CONFIG_PKR_XSEL2_3', +} +RASTER_CONFIG_PKR_XSEL2_0 = 0 +RASTER_CONFIG_PKR_XSEL2_1 = 1 +RASTER_CONFIG_PKR_XSEL2_2 = 2 +RASTER_CONFIG_PKR_XSEL2_3 = 3 +PkrXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'PkrYsel' +PkrYsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_YSEL_0', + 1: 'RASTER_CONFIG_PKR_YSEL_1', + 2: 'RASTER_CONFIG_PKR_YSEL_2', + 3: 'RASTER_CONFIG_PKR_YSEL_3', +} +RASTER_CONFIG_PKR_YSEL_0 = 0 +RASTER_CONFIG_PKR_YSEL_1 = 1 +RASTER_CONFIG_PKR_YSEL_2 = 2 +RASTER_CONFIG_PKR_YSEL_3 = 3 +PkrYsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbMap' +RbMap__enumvalues = { + 0: 'RASTER_CONFIG_RB_MAP_0', + 1: 'RASTER_CONFIG_RB_MAP_1', + 2: 'RASTER_CONFIG_RB_MAP_2', + 3: 'RASTER_CONFIG_RB_MAP_3', +} +RASTER_CONFIG_RB_MAP_0 = 0 +RASTER_CONFIG_RB_MAP_1 = 1 +RASTER_CONFIG_RB_MAP_2 = 2 +RASTER_CONFIG_RB_MAP_3 = 3 +RbMap = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel' +RbXsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL_0', + 1: 'RASTER_CONFIG_RB_XSEL_1', +} +RASTER_CONFIG_RB_XSEL_0 = 0 +RASTER_CONFIG_RB_XSEL_1 = 1 +RbXsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel2' +RbXsel2__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL2_0', + 1: 'RASTER_CONFIG_RB_XSEL2_1', + 2: 'RASTER_CONFIG_RB_XSEL2_2', + 3: 'RASTER_CONFIG_RB_XSEL2_3', +} +RASTER_CONFIG_RB_XSEL2_0 = 0 +RASTER_CONFIG_RB_XSEL2_1 = 1 +RASTER_CONFIG_RB_XSEL2_2 = 2 +RASTER_CONFIG_RB_XSEL2_3 = 3 +RbXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'RbYsel' +RbYsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_YSEL_0', + 1: 'RASTER_CONFIG_RB_YSEL_1', +} +RASTER_CONFIG_RB_YSEL_0 = 0 +RASTER_CONFIG_RB_YSEL_1 = 1 +RbYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SC_PERFCNT_SEL' +SC_PERFCNT_SEL__enumvalues = { + 0: 'SC_SRPS_WINDOW_VALID', + 1: 'SC_PSSW_WINDOW_VALID', + 2: 'SC_TPQZ_WINDOW_VALID', + 3: 'SC_QZQP_WINDOW_VALID', + 4: 'SC_TRPK_WINDOW_VALID', + 5: 'SC_SRPS_WINDOW_VALID_BUSY', + 6: 'SC_PSSW_WINDOW_VALID_BUSY', + 7: 'SC_TPQZ_WINDOW_VALID_BUSY', + 8: 'SC_QZQP_WINDOW_VALID_BUSY', + 9: 'SC_TRPK_WINDOW_VALID_BUSY', + 10: 'SC_STARVED_BY_PA', + 11: 'SC_STALLED_BY_PRIMFIFO', + 12: 'SC_STALLED_BY_DB_TILE', + 13: 'SC_STARVED_BY_DB_TILE', + 14: 'SC_STALLED_BY_TILEORDERFIFO', + 15: 'SC_STALLED_BY_TILEFIFO', + 16: 'SC_STALLED_BY_DB_QUAD', + 17: 'SC_STARVED_BY_DB_QUAD', + 18: 'SC_STALLED_BY_QUADFIFO', + 19: 'SC_STALLED_BY_BCI', + 20: 'SC_STALLED_BY_SPI', + 21: 'SC_SCISSOR_DISCARD', + 22: 'SC_BB_DISCARD', + 23: 'SC_SUPERTILE_COUNT', + 24: 'SC_SUPERTILE_PER_PRIM_H0', + 25: 'SC_SUPERTILE_PER_PRIM_H1', + 26: 'SC_SUPERTILE_PER_PRIM_H2', + 27: 'SC_SUPERTILE_PER_PRIM_H3', + 28: 'SC_SUPERTILE_PER_PRIM_H4', + 29: 'SC_SUPERTILE_PER_PRIM_H5', + 30: 'SC_SUPERTILE_PER_PRIM_H6', + 31: 'SC_SUPERTILE_PER_PRIM_H7', + 32: 'SC_SUPERTILE_PER_PRIM_H8', + 33: 'SC_SUPERTILE_PER_PRIM_H9', + 34: 'SC_SUPERTILE_PER_PRIM_H10', + 35: 'SC_SUPERTILE_PER_PRIM_H11', + 36: 'SC_SUPERTILE_PER_PRIM_H12', + 37: 'SC_SUPERTILE_PER_PRIM_H13', + 38: 'SC_SUPERTILE_PER_PRIM_H14', + 39: 'SC_SUPERTILE_PER_PRIM_H15', + 40: 'SC_SUPERTILE_PER_PRIM_H16', + 41: 'SC_TILE_PER_PRIM_H0', + 42: 'SC_TILE_PER_PRIM_H1', + 43: 'SC_TILE_PER_PRIM_H2', + 44: 'SC_TILE_PER_PRIM_H3', + 45: 'SC_TILE_PER_PRIM_H4', + 46: 'SC_TILE_PER_PRIM_H5', + 47: 'SC_TILE_PER_PRIM_H6', + 48: 'SC_TILE_PER_PRIM_H7', + 49: 'SC_TILE_PER_PRIM_H8', + 50: 'SC_TILE_PER_PRIM_H9', + 51: 'SC_TILE_PER_PRIM_H10', + 52: 'SC_TILE_PER_PRIM_H11', + 53: 'SC_TILE_PER_PRIM_H12', + 54: 'SC_TILE_PER_PRIM_H13', + 55: 'SC_TILE_PER_PRIM_H14', + 56: 'SC_TILE_PER_PRIM_H15', + 57: 'SC_TILE_PER_PRIM_H16', + 58: 'SC_TILE_PER_SUPERTILE_H0', + 59: 'SC_TILE_PER_SUPERTILE_H1', + 60: 'SC_TILE_PER_SUPERTILE_H2', + 61: 'SC_TILE_PER_SUPERTILE_H3', + 62: 'SC_TILE_PER_SUPERTILE_H4', + 63: 'SC_TILE_PER_SUPERTILE_H5', + 64: 'SC_TILE_PER_SUPERTILE_H6', + 65: 'SC_TILE_PER_SUPERTILE_H7', + 66: 'SC_TILE_PER_SUPERTILE_H8', + 67: 'SC_TILE_PER_SUPERTILE_H9', + 68: 'SC_TILE_PER_SUPERTILE_H10', + 69: 'SC_TILE_PER_SUPERTILE_H11', + 70: 'SC_TILE_PER_SUPERTILE_H12', + 71: 'SC_TILE_PER_SUPERTILE_H13', + 72: 'SC_TILE_PER_SUPERTILE_H14', + 73: 'SC_TILE_PER_SUPERTILE_H15', + 74: 'SC_TILE_PER_SUPERTILE_H16', + 75: 'SC_TILE_PICKED_H1', + 76: 'SC_TILE_PICKED_H2', + 77: 'SC_TILE_PICKED_H3', + 78: 'SC_TILE_PICKED_H4', + 79: 'SC_QZ0_TILE_COUNT', + 80: 'SC_QZ1_TILE_COUNT', + 81: 'SC_QZ2_TILE_COUNT', + 82: 'SC_QZ3_TILE_COUNT', + 83: 'SC_QZ0_TILE_COVERED_COUNT', + 84: 'SC_QZ1_TILE_COVERED_COUNT', + 85: 'SC_QZ2_TILE_COVERED_COUNT', + 86: 'SC_QZ3_TILE_COVERED_COUNT', + 87: 'SC_QZ0_TILE_NOT_COVERED_COUNT', + 88: 'SC_QZ1_TILE_NOT_COVERED_COUNT', + 89: 'SC_QZ2_TILE_NOT_COVERED_COUNT', + 90: 'SC_QZ3_TILE_NOT_COVERED_COUNT', + 91: 'SC_QZ0_QUAD_PER_TILE_H0', + 92: 'SC_QZ0_QUAD_PER_TILE_H1', + 93: 'SC_QZ0_QUAD_PER_TILE_H2', + 94: 'SC_QZ0_QUAD_PER_TILE_H3', + 95: 'SC_QZ0_QUAD_PER_TILE_H4', + 96: 'SC_QZ0_QUAD_PER_TILE_H5', + 97: 'SC_QZ0_QUAD_PER_TILE_H6', + 98: 'SC_QZ0_QUAD_PER_TILE_H7', + 99: 'SC_QZ0_QUAD_PER_TILE_H8', + 100: 'SC_QZ0_QUAD_PER_TILE_H9', + 101: 'SC_QZ0_QUAD_PER_TILE_H10', + 102: 'SC_QZ0_QUAD_PER_TILE_H11', + 103: 'SC_QZ0_QUAD_PER_TILE_H12', + 104: 'SC_QZ0_QUAD_PER_TILE_H13', + 105: 'SC_QZ0_QUAD_PER_TILE_H14', + 106: 'SC_QZ0_QUAD_PER_TILE_H15', + 107: 'SC_QZ0_QUAD_PER_TILE_H16', + 108: 'SC_QZ1_QUAD_PER_TILE_H0', + 109: 'SC_QZ1_QUAD_PER_TILE_H1', + 110: 'SC_QZ1_QUAD_PER_TILE_H2', + 111: 'SC_QZ1_QUAD_PER_TILE_H3', + 112: 'SC_QZ1_QUAD_PER_TILE_H4', + 113: 'SC_QZ1_QUAD_PER_TILE_H5', + 114: 'SC_QZ1_QUAD_PER_TILE_H6', + 115: 'SC_QZ1_QUAD_PER_TILE_H7', + 116: 'SC_QZ1_QUAD_PER_TILE_H8', + 117: 'SC_QZ1_QUAD_PER_TILE_H9', + 118: 'SC_QZ1_QUAD_PER_TILE_H10', + 119: 'SC_QZ1_QUAD_PER_TILE_H11', + 120: 'SC_QZ1_QUAD_PER_TILE_H12', + 121: 'SC_QZ1_QUAD_PER_TILE_H13', + 122: 'SC_QZ1_QUAD_PER_TILE_H14', + 123: 'SC_QZ1_QUAD_PER_TILE_H15', + 124: 'SC_QZ1_QUAD_PER_TILE_H16', + 125: 'SC_QZ2_QUAD_PER_TILE_H0', + 126: 'SC_QZ2_QUAD_PER_TILE_H1', + 127: 'SC_QZ2_QUAD_PER_TILE_H2', + 128: 'SC_QZ2_QUAD_PER_TILE_H3', + 129: 'SC_QZ2_QUAD_PER_TILE_H4', + 130: 'SC_QZ2_QUAD_PER_TILE_H5', + 131: 'SC_QZ2_QUAD_PER_TILE_H6', + 132: 'SC_QZ2_QUAD_PER_TILE_H7', + 133: 'SC_QZ2_QUAD_PER_TILE_H8', + 134: 'SC_QZ2_QUAD_PER_TILE_H9', + 135: 'SC_QZ2_QUAD_PER_TILE_H10', + 136: 'SC_QZ2_QUAD_PER_TILE_H11', + 137: 'SC_QZ2_QUAD_PER_TILE_H12', + 138: 'SC_QZ2_QUAD_PER_TILE_H13', + 139: 'SC_QZ2_QUAD_PER_TILE_H14', + 140: 'SC_QZ2_QUAD_PER_TILE_H15', + 141: 'SC_QZ2_QUAD_PER_TILE_H16', + 142: 'SC_QZ3_QUAD_PER_TILE_H0', + 143: 'SC_QZ3_QUAD_PER_TILE_H1', + 144: 'SC_QZ3_QUAD_PER_TILE_H2', + 145: 'SC_QZ3_QUAD_PER_TILE_H3', + 146: 'SC_QZ3_QUAD_PER_TILE_H4', + 147: 'SC_QZ3_QUAD_PER_TILE_H5', + 148: 'SC_QZ3_QUAD_PER_TILE_H6', + 149: 'SC_QZ3_QUAD_PER_TILE_H7', + 150: 'SC_QZ3_QUAD_PER_TILE_H8', + 151: 'SC_QZ3_QUAD_PER_TILE_H9', + 152: 'SC_QZ3_QUAD_PER_TILE_H10', + 153: 'SC_QZ3_QUAD_PER_TILE_H11', + 154: 'SC_QZ3_QUAD_PER_TILE_H12', + 155: 'SC_QZ3_QUAD_PER_TILE_H13', + 156: 'SC_QZ3_QUAD_PER_TILE_H14', + 157: 'SC_QZ3_QUAD_PER_TILE_H15', + 158: 'SC_QZ3_QUAD_PER_TILE_H16', + 159: 'SC_QZ0_QUAD_COUNT', + 160: 'SC_QZ1_QUAD_COUNT', + 161: 'SC_QZ2_QUAD_COUNT', + 162: 'SC_QZ3_QUAD_COUNT', + 163: 'SC_P0_HIZ_TILE_COUNT', + 164: 'SC_P1_HIZ_TILE_COUNT', + 165: 'SC_P2_HIZ_TILE_COUNT', + 166: 'SC_P3_HIZ_TILE_COUNT', + 167: 'SC_P0_HIZ_QUAD_PER_TILE_H0', + 168: 'SC_P0_HIZ_QUAD_PER_TILE_H1', + 169: 'SC_P0_HIZ_QUAD_PER_TILE_H2', + 170: 'SC_P0_HIZ_QUAD_PER_TILE_H3', + 171: 'SC_P0_HIZ_QUAD_PER_TILE_H4', + 172: 'SC_P0_HIZ_QUAD_PER_TILE_H5', + 173: 'SC_P0_HIZ_QUAD_PER_TILE_H6', + 174: 'SC_P0_HIZ_QUAD_PER_TILE_H7', + 175: 'SC_P0_HIZ_QUAD_PER_TILE_H8', + 176: 'SC_P0_HIZ_QUAD_PER_TILE_H9', + 177: 'SC_P0_HIZ_QUAD_PER_TILE_H10', + 178: 'SC_P0_HIZ_QUAD_PER_TILE_H11', + 179: 'SC_P0_HIZ_QUAD_PER_TILE_H12', + 180: 'SC_P0_HIZ_QUAD_PER_TILE_H13', + 181: 'SC_P0_HIZ_QUAD_PER_TILE_H14', + 182: 'SC_P0_HIZ_QUAD_PER_TILE_H15', + 183: 'SC_P0_HIZ_QUAD_PER_TILE_H16', + 184: 'SC_P1_HIZ_QUAD_PER_TILE_H0', + 185: 'SC_P1_HIZ_QUAD_PER_TILE_H1', + 186: 'SC_P1_HIZ_QUAD_PER_TILE_H2', + 187: 'SC_P1_HIZ_QUAD_PER_TILE_H3', + 188: 'SC_P1_HIZ_QUAD_PER_TILE_H4', + 189: 'SC_P1_HIZ_QUAD_PER_TILE_H5', + 190: 'SC_P1_HIZ_QUAD_PER_TILE_H6', + 191: 'SC_P1_HIZ_QUAD_PER_TILE_H7', + 192: 'SC_P1_HIZ_QUAD_PER_TILE_H8', + 193: 'SC_P1_HIZ_QUAD_PER_TILE_H9', + 194: 'SC_P1_HIZ_QUAD_PER_TILE_H10', + 195: 'SC_P1_HIZ_QUAD_PER_TILE_H11', + 196: 'SC_P1_HIZ_QUAD_PER_TILE_H12', + 197: 'SC_P1_HIZ_QUAD_PER_TILE_H13', + 198: 'SC_P1_HIZ_QUAD_PER_TILE_H14', + 199: 'SC_P1_HIZ_QUAD_PER_TILE_H15', + 200: 'SC_P1_HIZ_QUAD_PER_TILE_H16', + 201: 'SC_P2_HIZ_QUAD_PER_TILE_H0', + 202: 'SC_P2_HIZ_QUAD_PER_TILE_H1', + 203: 'SC_P2_HIZ_QUAD_PER_TILE_H2', + 204: 'SC_P2_HIZ_QUAD_PER_TILE_H3', + 205: 'SC_P2_HIZ_QUAD_PER_TILE_H4', + 206: 'SC_P2_HIZ_QUAD_PER_TILE_H5', + 207: 'SC_P2_HIZ_QUAD_PER_TILE_H6', + 208: 'SC_P2_HIZ_QUAD_PER_TILE_H7', + 209: 'SC_P2_HIZ_QUAD_PER_TILE_H8', + 210: 'SC_P2_HIZ_QUAD_PER_TILE_H9', + 211: 'SC_P2_HIZ_QUAD_PER_TILE_H10', + 212: 'SC_P2_HIZ_QUAD_PER_TILE_H11', + 213: 'SC_P2_HIZ_QUAD_PER_TILE_H12', + 214: 'SC_P2_HIZ_QUAD_PER_TILE_H13', + 215: 'SC_P2_HIZ_QUAD_PER_TILE_H14', + 216: 'SC_P2_HIZ_QUAD_PER_TILE_H15', + 217: 'SC_P2_HIZ_QUAD_PER_TILE_H16', + 218: 'SC_P3_HIZ_QUAD_PER_TILE_H0', + 219: 'SC_P3_HIZ_QUAD_PER_TILE_H1', + 220: 'SC_P3_HIZ_QUAD_PER_TILE_H2', + 221: 'SC_P3_HIZ_QUAD_PER_TILE_H3', + 222: 'SC_P3_HIZ_QUAD_PER_TILE_H4', + 223: 'SC_P3_HIZ_QUAD_PER_TILE_H5', + 224: 'SC_P3_HIZ_QUAD_PER_TILE_H6', + 225: 'SC_P3_HIZ_QUAD_PER_TILE_H7', + 226: 'SC_P3_HIZ_QUAD_PER_TILE_H8', + 227: 'SC_P3_HIZ_QUAD_PER_TILE_H9', + 228: 'SC_P3_HIZ_QUAD_PER_TILE_H10', + 229: 'SC_P3_HIZ_QUAD_PER_TILE_H11', + 230: 'SC_P3_HIZ_QUAD_PER_TILE_H12', + 231: 'SC_P3_HIZ_QUAD_PER_TILE_H13', + 232: 'SC_P3_HIZ_QUAD_PER_TILE_H14', + 233: 'SC_P3_HIZ_QUAD_PER_TILE_H15', + 234: 'SC_P3_HIZ_QUAD_PER_TILE_H16', + 235: 'SC_P0_HIZ_QUAD_COUNT', + 236: 'SC_P1_HIZ_QUAD_COUNT', + 237: 'SC_P2_HIZ_QUAD_COUNT', + 238: 'SC_P3_HIZ_QUAD_COUNT', + 239: 'SC_P0_DETAIL_QUAD_COUNT', + 240: 'SC_P1_DETAIL_QUAD_COUNT', + 241: 'SC_P2_DETAIL_QUAD_COUNT', + 242: 'SC_P3_DETAIL_QUAD_COUNT', + 243: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', + 244: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', + 245: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', + 246: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', + 247: 'SC_P1_DETAIL_QUAD_WITH_1_PIX', + 248: 'SC_P1_DETAIL_QUAD_WITH_2_PIX', + 249: 'SC_P1_DETAIL_QUAD_WITH_3_PIX', + 250: 'SC_P1_DETAIL_QUAD_WITH_4_PIX', + 251: 'SC_P2_DETAIL_QUAD_WITH_1_PIX', + 252: 'SC_P2_DETAIL_QUAD_WITH_2_PIX', + 253: 'SC_P2_DETAIL_QUAD_WITH_3_PIX', + 254: 'SC_P2_DETAIL_QUAD_WITH_4_PIX', + 255: 'SC_P3_DETAIL_QUAD_WITH_1_PIX', + 256: 'SC_P3_DETAIL_QUAD_WITH_2_PIX', + 257: 'SC_P3_DETAIL_QUAD_WITH_3_PIX', + 258: 'SC_P3_DETAIL_QUAD_WITH_4_PIX', + 259: 'SC_EARLYZ_QUAD_COUNT', + 260: 'SC_EARLYZ_QUAD_WITH_1_PIX', + 261: 'SC_EARLYZ_QUAD_WITH_2_PIX', + 262: 'SC_EARLYZ_QUAD_WITH_3_PIX', + 263: 'SC_EARLYZ_QUAD_WITH_4_PIX', + 264: 'SC_PKR_QUAD_PER_ROW_H1', + 265: 'SC_PKR_QUAD_PER_ROW_H2', + 266: 'SC_PKR_4X2_QUAD_SPLIT', + 267: 'SC_PKR_4X2_FILL_QUAD', + 268: 'SC_PKR_END_OF_VECTOR', + 269: 'SC_PKR_CONTROL_XFER', + 270: 'SC_PKR_DBHANG_FORCE_EOV', + 271: 'SC_REG_SCLK_BUSY', + 272: 'SC_GRP0_DYN_SCLK_BUSY', + 273: 'SC_GRP1_DYN_SCLK_BUSY', + 274: 'SC_GRP2_DYN_SCLK_BUSY', + 275: 'SC_GRP3_DYN_SCLK_BUSY', + 276: 'SC_GRP4_DYN_SCLK_BUSY', + 277: 'SC_PA0_SC_DATA_FIFO_RD', + 278: 'SC_PA0_SC_DATA_FIFO_WE', + 279: 'SC_PA1_SC_DATA_FIFO_RD', + 280: 'SC_PA1_SC_DATA_FIFO_WE', + 281: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 282: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', + 283: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 284: 'SC_PS_ARB_STALLED_FROM_BELOW', + 285: 'SC_PS_ARB_STARVED_FROM_ABOVE', + 286: 'SC_PS_ARB_SC_BUSY', + 287: 'SC_PS_ARB_PA_SC_BUSY', + 288: 'SC_PA2_SC_DATA_FIFO_RD', + 289: 'SC_PA2_SC_DATA_FIFO_WE', + 290: 'SC_PA3_SC_DATA_FIFO_RD', + 291: 'SC_PA3_SC_DATA_FIFO_WE', + 292: 'SC_PA_SC_DEALLOC_0_0_WE', + 293: 'SC_PA_SC_DEALLOC_0_1_WE', + 294: 'SC_PA_SC_DEALLOC_1_0_WE', + 295: 'SC_PA_SC_DEALLOC_1_1_WE', + 296: 'SC_PA_SC_DEALLOC_2_0_WE', + 297: 'SC_PA_SC_DEALLOC_2_1_WE', + 298: 'SC_PA_SC_DEALLOC_3_0_WE', + 299: 'SC_PA_SC_DEALLOC_3_1_WE', + 300: 'SC_PA0_SC_EOP_WE', + 301: 'SC_PA0_SC_EOPG_WE', + 302: 'SC_PA0_SC_EVENT_WE', + 303: 'SC_PA1_SC_EOP_WE', + 304: 'SC_PA1_SC_EOPG_WE', + 305: 'SC_PA1_SC_EVENT_WE', + 306: 'SC_PA2_SC_EOP_WE', + 307: 'SC_PA2_SC_EOPG_WE', + 308: 'SC_PA2_SC_EVENT_WE', + 309: 'SC_PA3_SC_EOP_WE', + 310: 'SC_PA3_SC_EOPG_WE', + 311: 'SC_PA3_SC_EVENT_WE', + 312: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', + 313: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', + 314: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', + 315: 'SC_PS_ARB_EOP_POP_SYNC_POP', + 316: 'SC_PS_ARB_EVENT_SYNC_POP', + 317: 'SC_PS_ENG_MULTICYCLE_BUBBLE', + 318: 'SC_PA0_SC_FPOV_WE', + 319: 'SC_PA1_SC_FPOV_WE', + 320: 'SC_PA2_SC_FPOV_WE', + 321: 'SC_PA3_SC_FPOV_WE', + 322: 'SC_PA0_SC_LPOV_WE', + 323: 'SC_PA1_SC_LPOV_WE', + 324: 'SC_PA2_SC_LPOV_WE', + 325: 'SC_PA3_SC_LPOV_WE', + 326: 'SC_SPI_DEALLOC_0_0', + 327: 'SC_SPI_DEALLOC_0_1', + 328: 'SC_SPI_DEALLOC_0_2', + 329: 'SC_SPI_DEALLOC_1_0', + 330: 'SC_SPI_DEALLOC_1_1', + 331: 'SC_SPI_DEALLOC_1_2', + 332: 'SC_SPI_DEALLOC_2_0', + 333: 'SC_SPI_DEALLOC_2_1', + 334: 'SC_SPI_DEALLOC_2_2', + 335: 'SC_SPI_DEALLOC_3_0', + 336: 'SC_SPI_DEALLOC_3_1', + 337: 'SC_SPI_DEALLOC_3_2', + 338: 'SC_SPI_FPOV_0', + 339: 'SC_SPI_FPOV_1', + 340: 'SC_SPI_FPOV_2', + 341: 'SC_SPI_FPOV_3', + 342: 'SC_SPI_EVENT', + 343: 'SC_PS_TS_EVENT_FIFO_PUSH', + 344: 'SC_PS_TS_EVENT_FIFO_POP', + 345: 'SC_PS_CTX_DONE_FIFO_PUSH', + 346: 'SC_PS_CTX_DONE_FIFO_POP', + 347: 'SC_MULTICYCLE_BUBBLE_FREEZE', + 348: 'SC_EOP_SYNC_WINDOW', + 349: 'SC_PA0_SC_NULL_WE', + 350: 'SC_PA0_SC_NULL_DEALLOC_WE', + 351: 'SC_PA0_SC_DATA_FIFO_EOPG_RD', + 352: 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 353: 'SC_PA0_SC_DEALLOC_0_RD', + 354: 'SC_PA0_SC_DEALLOC_1_RD', + 355: 'SC_PA1_SC_DATA_FIFO_EOPG_RD', + 356: 'SC_PA1_SC_DATA_FIFO_EOP_RD', + 357: 'SC_PA1_SC_DEALLOC_0_RD', + 358: 'SC_PA1_SC_DEALLOC_1_RD', + 359: 'SC_PA1_SC_NULL_WE', + 360: 'SC_PA1_SC_NULL_DEALLOC_WE', + 361: 'SC_PA2_SC_DATA_FIFO_EOPG_RD', + 362: 'SC_PA2_SC_DATA_FIFO_EOP_RD', + 363: 'SC_PA2_SC_DEALLOC_0_RD', + 364: 'SC_PA2_SC_DEALLOC_1_RD', + 365: 'SC_PA2_SC_NULL_WE', + 366: 'SC_PA2_SC_NULL_DEALLOC_WE', + 367: 'SC_PA3_SC_DATA_FIFO_EOPG_RD', + 368: 'SC_PA3_SC_DATA_FIFO_EOP_RD', + 369: 'SC_PA3_SC_DEALLOC_0_RD', + 370: 'SC_PA3_SC_DEALLOC_1_RD', + 371: 'SC_PA3_SC_NULL_WE', + 372: 'SC_PA3_SC_NULL_DEALLOC_WE', + 373: 'SC_PS_PA0_SC_FIFO_EMPTY', + 374: 'SC_PS_PA0_SC_FIFO_FULL', + 375: 'SC_RESERVED_0', + 376: 'SC_PS_PA1_SC_FIFO_EMPTY', + 377: 'SC_PS_PA1_SC_FIFO_FULL', + 378: 'SC_RESERVED_1', + 379: 'SC_PS_PA2_SC_FIFO_EMPTY', + 380: 'SC_PS_PA2_SC_FIFO_FULL', + 381: 'SC_RESERVED_2', + 382: 'SC_PS_PA3_SC_FIFO_EMPTY', + 383: 'SC_PS_PA3_SC_FIFO_FULL', + 384: 'SC_RESERVED_3', + 385: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', + 386: 'SC_BUSY_CNT_NOT_ZERO', + 387: 'SC_BM_BUSY', + 388: 'SC_BACKEND_BUSY', + 389: 'SC_SCF_SCB_INTERFACE_BUSY', + 390: 'SC_SCB_BUSY', + 391: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 392: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 393: 'SC_PBB_BIN_HIST_NUM_PRIMS', + 394: 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 395: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 396: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 397: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 398: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 399: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 400: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 401: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 402: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 403: 'SC_PBB_BUSY', + 404: 'SC_PBB_BUSY_AND_NO_SENDS', + 405: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 406: 'SC_PBB_NUM_BINS', + 407: 'SC_PBB_END_OF_BIN', + 408: 'SC_PBB_END_OF_BATCH', + 409: 'SC_PBB_PRIMBIN_PROCESSED', + 410: 'SC_PBB_PRIM_ADDED_TO_BATCH', + 411: 'SC_PBB_NONBINNED_PRIM', + 412: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', + 413: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 414: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 415: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 416: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 417: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 418: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 419: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 420: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 421: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 422: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 423: 'SC_POPS_INTRA_WAVE_OVERLAPS', + 424: 'SC_POPS_FORCE_EOV', + 425: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', + 426: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', + 427: 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', + 428: 'SC_FULL_FULL_QUAD', + 429: 'SC_FULL_HALF_QUAD', + 430: 'SC_FULL_QTR_QUAD', + 431: 'SC_HALF_FULL_QUAD', + 432: 'SC_HALF_HALF_QUAD', + 433: 'SC_HALF_QTR_QUAD', + 434: 'SC_QTR_FULL_QUAD', + 435: 'SC_QTR_HALF_QUAD', + 436: 'SC_QTR_QTR_QUAD', + 437: 'SC_GRP5_DYN_SCLK_BUSY', + 438: 'SC_GRP6_DYN_SCLK_BUSY', + 439: 'SC_GRP7_DYN_SCLK_BUSY', + 440: 'SC_GRP8_DYN_SCLK_BUSY', + 441: 'SC_GRP9_DYN_SCLK_BUSY', + 442: 'SC_PS_TO_BE_SCLK_GATE_STALL', + 443: 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', + 444: 'SC_PK_BUSY', + 445: 'SC_PK_MAX_DEALLOC_FORCE_EOV', + 446: 'SC_PK_DEALLOC_WAVE_BREAK', + 447: 'SC_SPI_SEND', + 448: 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 449: 'SC_SPI_CREDIT_AT_MAX', + 450: 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', + 451: 'SC_BCI_SEND', + 452: 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 453: 'SC_BCI_CREDIT_AT_MAX', + 454: 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', + 455: 'SC_SPIBC_FULL_FREEZE', + 456: 'SC_PW_BM_PASS_EMPTY_PRIM', + 457: 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', + 458: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', + 459: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', + 460: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', + 461: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', + 462: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', + 463: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', + 464: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', + 465: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', + 466: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', + 467: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', + 468: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', + 469: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', + 470: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', + 471: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', + 472: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', + 473: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', + 474: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', + 475: 'SC_DB0_TILE_INTERFACE_BUSY', + 476: 'SC_DB0_TILE_INTERFACE_SEND', + 477: 'SC_DB0_TILE_INTERFACE_SEND_EVENT', + 478: 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 479: 'SC_DB0_TILE_INTERFACE_SEND_SOP', + 480: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 481: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', + 482: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 483: 'SC_DB1_TILE_INTERFACE_BUSY', + 484: 'SC_DB1_TILE_INTERFACE_SEND', + 485: 'SC_DB1_TILE_INTERFACE_SEND_EVENT', + 486: 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 487: 'SC_DB1_TILE_INTERFACE_SEND_SOP', + 488: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 489: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', + 490: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 491: 'SC_BACKEND_PRIM_FIFO_FULL', + 492: 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', + 493: 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', + 494: 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', + 495: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', + 496: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', + 497: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', + 498: 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', + 499: 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', + 500: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', + 501: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', + 502: 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', + 503: 'SC_STALLED_BY_DB0_TILEFIFO', + 504: 'SC_DB0_QUAD_INTF_SEND', + 505: 'SC_DB0_QUAD_INTF_BUSY', + 506: 'SC_DB0_QUAD_INTF_STALLED_BY_DB', + 507: 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', + 508: 'SC_DB0_QUAD_INTF_IDLE', + 509: 'SC_DB1_QUAD_INTF_SEND', + 510: 'SC_STALLED_BY_DB1_TILEFIFO', + 511: 'SC_DB1_QUAD_INTF_BUSY', + 512: 'SC_DB1_QUAD_INTF_STALLED_BY_DB', + 513: 'SC_DB1_QUAD_INTF_CREDIT_AT_MAX', + 514: 'SC_DB1_QUAD_INTF_IDLE', + 515: 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', + 516: 'SC_PKR_WAVE_BREAK_FULL_TILE', + 517: 'SC_FSR_WALKED', + 518: 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', + 519: 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', + 520: 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', + 521: 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 522: 'SC_DB0_TILE_MASK_FIFO_FULL', + 523: 'SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL', + 524: 'SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 525: 'SC_DB1_TILE_MASK_FIFO_FULL', + 526: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', + 527: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', + 528: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', + 529: 'SC_PS_PM_PFF_PW_FULL', + 530: 'SC_PS_PM_ZFF_PW_FULL', + 531: 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', + 532: 'SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H', + 533: 'SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 534: 'SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 535: 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', + 536: 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', + 537: 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', + 538: 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', + 539: 'SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H', + 540: 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', + 541: 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 542: 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', + 543: 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 544: 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', + 545: 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', + 546: 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', + 547: 'SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H', + 548: 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', + 549: 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', + 550: 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', + 551: 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', + 552: 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', + 553: 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', + 554: 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', + 555: 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', + 556: 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', + 557: 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', + 558: 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', + 559: 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', + 560: 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', + 561: 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', + 562: 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', + 563: 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', + 564: 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', + 565: 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', + 566: 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', + 567: 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', + 568: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE', + 569: 'SC_PBB_RESERVED', + 570: 'SC_BM_BE0_STALLED', + 571: 'SC_BM_BE1_STALLED', + 572: 'SC_BM_BE2_STALLED', + 573: 'SC_BM_BE3_STALLED', + 574: 'SC_BM_MULTI_ACCUM_1_BE_STALLED', + 575: 'SC_BM_MULTI_ACCUM_2_BE_STALLED', + 576: 'SC_BM_MULTI_ACCUM_3_BE_STALLED', + 577: 'SC_BM_MULTI_ACCUM_4_BE_STALLED', +} +SC_SRPS_WINDOW_VALID = 0 +SC_PSSW_WINDOW_VALID = 1 +SC_TPQZ_WINDOW_VALID = 2 +SC_QZQP_WINDOW_VALID = 3 +SC_TRPK_WINDOW_VALID = 4 +SC_SRPS_WINDOW_VALID_BUSY = 5 +SC_PSSW_WINDOW_VALID_BUSY = 6 +SC_TPQZ_WINDOW_VALID_BUSY = 7 +SC_QZQP_WINDOW_VALID_BUSY = 8 +SC_TRPK_WINDOW_VALID_BUSY = 9 +SC_STARVED_BY_PA = 10 +SC_STALLED_BY_PRIMFIFO = 11 +SC_STALLED_BY_DB_TILE = 12 +SC_STARVED_BY_DB_TILE = 13 +SC_STALLED_BY_TILEORDERFIFO = 14 +SC_STALLED_BY_TILEFIFO = 15 +SC_STALLED_BY_DB_QUAD = 16 +SC_STARVED_BY_DB_QUAD = 17 +SC_STALLED_BY_QUADFIFO = 18 +SC_STALLED_BY_BCI = 19 +SC_STALLED_BY_SPI = 20 +SC_SCISSOR_DISCARD = 21 +SC_BB_DISCARD = 22 +SC_SUPERTILE_COUNT = 23 +SC_SUPERTILE_PER_PRIM_H0 = 24 +SC_SUPERTILE_PER_PRIM_H1 = 25 +SC_SUPERTILE_PER_PRIM_H2 = 26 +SC_SUPERTILE_PER_PRIM_H3 = 27 +SC_SUPERTILE_PER_PRIM_H4 = 28 +SC_SUPERTILE_PER_PRIM_H5 = 29 +SC_SUPERTILE_PER_PRIM_H6 = 30 +SC_SUPERTILE_PER_PRIM_H7 = 31 +SC_SUPERTILE_PER_PRIM_H8 = 32 +SC_SUPERTILE_PER_PRIM_H9 = 33 +SC_SUPERTILE_PER_PRIM_H10 = 34 +SC_SUPERTILE_PER_PRIM_H11 = 35 +SC_SUPERTILE_PER_PRIM_H12 = 36 +SC_SUPERTILE_PER_PRIM_H13 = 37 +SC_SUPERTILE_PER_PRIM_H14 = 38 +SC_SUPERTILE_PER_PRIM_H15 = 39 +SC_SUPERTILE_PER_PRIM_H16 = 40 +SC_TILE_PER_PRIM_H0 = 41 +SC_TILE_PER_PRIM_H1 = 42 +SC_TILE_PER_PRIM_H2 = 43 +SC_TILE_PER_PRIM_H3 = 44 +SC_TILE_PER_PRIM_H4 = 45 +SC_TILE_PER_PRIM_H5 = 46 +SC_TILE_PER_PRIM_H6 = 47 +SC_TILE_PER_PRIM_H7 = 48 +SC_TILE_PER_PRIM_H8 = 49 +SC_TILE_PER_PRIM_H9 = 50 +SC_TILE_PER_PRIM_H10 = 51 +SC_TILE_PER_PRIM_H11 = 52 +SC_TILE_PER_PRIM_H12 = 53 +SC_TILE_PER_PRIM_H13 = 54 +SC_TILE_PER_PRIM_H14 = 55 +SC_TILE_PER_PRIM_H15 = 56 +SC_TILE_PER_PRIM_H16 = 57 +SC_TILE_PER_SUPERTILE_H0 = 58 +SC_TILE_PER_SUPERTILE_H1 = 59 +SC_TILE_PER_SUPERTILE_H2 = 60 +SC_TILE_PER_SUPERTILE_H3 = 61 +SC_TILE_PER_SUPERTILE_H4 = 62 +SC_TILE_PER_SUPERTILE_H5 = 63 +SC_TILE_PER_SUPERTILE_H6 = 64 +SC_TILE_PER_SUPERTILE_H7 = 65 +SC_TILE_PER_SUPERTILE_H8 = 66 +SC_TILE_PER_SUPERTILE_H9 = 67 +SC_TILE_PER_SUPERTILE_H10 = 68 +SC_TILE_PER_SUPERTILE_H11 = 69 +SC_TILE_PER_SUPERTILE_H12 = 70 +SC_TILE_PER_SUPERTILE_H13 = 71 +SC_TILE_PER_SUPERTILE_H14 = 72 +SC_TILE_PER_SUPERTILE_H15 = 73 +SC_TILE_PER_SUPERTILE_H16 = 74 +SC_TILE_PICKED_H1 = 75 +SC_TILE_PICKED_H2 = 76 +SC_TILE_PICKED_H3 = 77 +SC_TILE_PICKED_H4 = 78 +SC_QZ0_TILE_COUNT = 79 +SC_QZ1_TILE_COUNT = 80 +SC_QZ2_TILE_COUNT = 81 +SC_QZ3_TILE_COUNT = 82 +SC_QZ0_TILE_COVERED_COUNT = 83 +SC_QZ1_TILE_COVERED_COUNT = 84 +SC_QZ2_TILE_COVERED_COUNT = 85 +SC_QZ3_TILE_COVERED_COUNT = 86 +SC_QZ0_TILE_NOT_COVERED_COUNT = 87 +SC_QZ1_TILE_NOT_COVERED_COUNT = 88 +SC_QZ2_TILE_NOT_COVERED_COUNT = 89 +SC_QZ3_TILE_NOT_COVERED_COUNT = 90 +SC_QZ0_QUAD_PER_TILE_H0 = 91 +SC_QZ0_QUAD_PER_TILE_H1 = 92 +SC_QZ0_QUAD_PER_TILE_H2 = 93 +SC_QZ0_QUAD_PER_TILE_H3 = 94 +SC_QZ0_QUAD_PER_TILE_H4 = 95 +SC_QZ0_QUAD_PER_TILE_H5 = 96 +SC_QZ0_QUAD_PER_TILE_H6 = 97 +SC_QZ0_QUAD_PER_TILE_H7 = 98 +SC_QZ0_QUAD_PER_TILE_H8 = 99 +SC_QZ0_QUAD_PER_TILE_H9 = 100 +SC_QZ0_QUAD_PER_TILE_H10 = 101 +SC_QZ0_QUAD_PER_TILE_H11 = 102 +SC_QZ0_QUAD_PER_TILE_H12 = 103 +SC_QZ0_QUAD_PER_TILE_H13 = 104 +SC_QZ0_QUAD_PER_TILE_H14 = 105 +SC_QZ0_QUAD_PER_TILE_H15 = 106 +SC_QZ0_QUAD_PER_TILE_H16 = 107 +SC_QZ1_QUAD_PER_TILE_H0 = 108 +SC_QZ1_QUAD_PER_TILE_H1 = 109 +SC_QZ1_QUAD_PER_TILE_H2 = 110 +SC_QZ1_QUAD_PER_TILE_H3 = 111 +SC_QZ1_QUAD_PER_TILE_H4 = 112 +SC_QZ1_QUAD_PER_TILE_H5 = 113 +SC_QZ1_QUAD_PER_TILE_H6 = 114 +SC_QZ1_QUAD_PER_TILE_H7 = 115 +SC_QZ1_QUAD_PER_TILE_H8 = 116 +SC_QZ1_QUAD_PER_TILE_H9 = 117 +SC_QZ1_QUAD_PER_TILE_H10 = 118 +SC_QZ1_QUAD_PER_TILE_H11 = 119 +SC_QZ1_QUAD_PER_TILE_H12 = 120 +SC_QZ1_QUAD_PER_TILE_H13 = 121 +SC_QZ1_QUAD_PER_TILE_H14 = 122 +SC_QZ1_QUAD_PER_TILE_H15 = 123 +SC_QZ1_QUAD_PER_TILE_H16 = 124 +SC_QZ2_QUAD_PER_TILE_H0 = 125 +SC_QZ2_QUAD_PER_TILE_H1 = 126 +SC_QZ2_QUAD_PER_TILE_H2 = 127 +SC_QZ2_QUAD_PER_TILE_H3 = 128 +SC_QZ2_QUAD_PER_TILE_H4 = 129 +SC_QZ2_QUAD_PER_TILE_H5 = 130 +SC_QZ2_QUAD_PER_TILE_H6 = 131 +SC_QZ2_QUAD_PER_TILE_H7 = 132 +SC_QZ2_QUAD_PER_TILE_H8 = 133 +SC_QZ2_QUAD_PER_TILE_H9 = 134 +SC_QZ2_QUAD_PER_TILE_H10 = 135 +SC_QZ2_QUAD_PER_TILE_H11 = 136 +SC_QZ2_QUAD_PER_TILE_H12 = 137 +SC_QZ2_QUAD_PER_TILE_H13 = 138 +SC_QZ2_QUAD_PER_TILE_H14 = 139 +SC_QZ2_QUAD_PER_TILE_H15 = 140 +SC_QZ2_QUAD_PER_TILE_H16 = 141 +SC_QZ3_QUAD_PER_TILE_H0 = 142 +SC_QZ3_QUAD_PER_TILE_H1 = 143 +SC_QZ3_QUAD_PER_TILE_H2 = 144 +SC_QZ3_QUAD_PER_TILE_H3 = 145 +SC_QZ3_QUAD_PER_TILE_H4 = 146 +SC_QZ3_QUAD_PER_TILE_H5 = 147 +SC_QZ3_QUAD_PER_TILE_H6 = 148 +SC_QZ3_QUAD_PER_TILE_H7 = 149 +SC_QZ3_QUAD_PER_TILE_H8 = 150 +SC_QZ3_QUAD_PER_TILE_H9 = 151 +SC_QZ3_QUAD_PER_TILE_H10 = 152 +SC_QZ3_QUAD_PER_TILE_H11 = 153 +SC_QZ3_QUAD_PER_TILE_H12 = 154 +SC_QZ3_QUAD_PER_TILE_H13 = 155 +SC_QZ3_QUAD_PER_TILE_H14 = 156 +SC_QZ3_QUAD_PER_TILE_H15 = 157 +SC_QZ3_QUAD_PER_TILE_H16 = 158 +SC_QZ0_QUAD_COUNT = 159 +SC_QZ1_QUAD_COUNT = 160 +SC_QZ2_QUAD_COUNT = 161 +SC_QZ3_QUAD_COUNT = 162 +SC_P0_HIZ_TILE_COUNT = 163 +SC_P1_HIZ_TILE_COUNT = 164 +SC_P2_HIZ_TILE_COUNT = 165 +SC_P3_HIZ_TILE_COUNT = 166 +SC_P0_HIZ_QUAD_PER_TILE_H0 = 167 +SC_P0_HIZ_QUAD_PER_TILE_H1 = 168 +SC_P0_HIZ_QUAD_PER_TILE_H2 = 169 +SC_P0_HIZ_QUAD_PER_TILE_H3 = 170 +SC_P0_HIZ_QUAD_PER_TILE_H4 = 171 +SC_P0_HIZ_QUAD_PER_TILE_H5 = 172 +SC_P0_HIZ_QUAD_PER_TILE_H6 = 173 +SC_P0_HIZ_QUAD_PER_TILE_H7 = 174 +SC_P0_HIZ_QUAD_PER_TILE_H8 = 175 +SC_P0_HIZ_QUAD_PER_TILE_H9 = 176 +SC_P0_HIZ_QUAD_PER_TILE_H10 = 177 +SC_P0_HIZ_QUAD_PER_TILE_H11 = 178 +SC_P0_HIZ_QUAD_PER_TILE_H12 = 179 +SC_P0_HIZ_QUAD_PER_TILE_H13 = 180 +SC_P0_HIZ_QUAD_PER_TILE_H14 = 181 +SC_P0_HIZ_QUAD_PER_TILE_H15 = 182 +SC_P0_HIZ_QUAD_PER_TILE_H16 = 183 +SC_P1_HIZ_QUAD_PER_TILE_H0 = 184 +SC_P1_HIZ_QUAD_PER_TILE_H1 = 185 +SC_P1_HIZ_QUAD_PER_TILE_H2 = 186 +SC_P1_HIZ_QUAD_PER_TILE_H3 = 187 +SC_P1_HIZ_QUAD_PER_TILE_H4 = 188 +SC_P1_HIZ_QUAD_PER_TILE_H5 = 189 +SC_P1_HIZ_QUAD_PER_TILE_H6 = 190 +SC_P1_HIZ_QUAD_PER_TILE_H7 = 191 +SC_P1_HIZ_QUAD_PER_TILE_H8 = 192 +SC_P1_HIZ_QUAD_PER_TILE_H9 = 193 +SC_P1_HIZ_QUAD_PER_TILE_H10 = 194 +SC_P1_HIZ_QUAD_PER_TILE_H11 = 195 +SC_P1_HIZ_QUAD_PER_TILE_H12 = 196 +SC_P1_HIZ_QUAD_PER_TILE_H13 = 197 +SC_P1_HIZ_QUAD_PER_TILE_H14 = 198 +SC_P1_HIZ_QUAD_PER_TILE_H15 = 199 +SC_P1_HIZ_QUAD_PER_TILE_H16 = 200 +SC_P2_HIZ_QUAD_PER_TILE_H0 = 201 +SC_P2_HIZ_QUAD_PER_TILE_H1 = 202 +SC_P2_HIZ_QUAD_PER_TILE_H2 = 203 +SC_P2_HIZ_QUAD_PER_TILE_H3 = 204 +SC_P2_HIZ_QUAD_PER_TILE_H4 = 205 +SC_P2_HIZ_QUAD_PER_TILE_H5 = 206 +SC_P2_HIZ_QUAD_PER_TILE_H6 = 207 +SC_P2_HIZ_QUAD_PER_TILE_H7 = 208 +SC_P2_HIZ_QUAD_PER_TILE_H8 = 209 +SC_P2_HIZ_QUAD_PER_TILE_H9 = 210 +SC_P2_HIZ_QUAD_PER_TILE_H10 = 211 +SC_P2_HIZ_QUAD_PER_TILE_H11 = 212 +SC_P2_HIZ_QUAD_PER_TILE_H12 = 213 +SC_P2_HIZ_QUAD_PER_TILE_H13 = 214 +SC_P2_HIZ_QUAD_PER_TILE_H14 = 215 +SC_P2_HIZ_QUAD_PER_TILE_H15 = 216 +SC_P2_HIZ_QUAD_PER_TILE_H16 = 217 +SC_P3_HIZ_QUAD_PER_TILE_H0 = 218 +SC_P3_HIZ_QUAD_PER_TILE_H1 = 219 +SC_P3_HIZ_QUAD_PER_TILE_H2 = 220 +SC_P3_HIZ_QUAD_PER_TILE_H3 = 221 +SC_P3_HIZ_QUAD_PER_TILE_H4 = 222 +SC_P3_HIZ_QUAD_PER_TILE_H5 = 223 +SC_P3_HIZ_QUAD_PER_TILE_H6 = 224 +SC_P3_HIZ_QUAD_PER_TILE_H7 = 225 +SC_P3_HIZ_QUAD_PER_TILE_H8 = 226 +SC_P3_HIZ_QUAD_PER_TILE_H9 = 227 +SC_P3_HIZ_QUAD_PER_TILE_H10 = 228 +SC_P3_HIZ_QUAD_PER_TILE_H11 = 229 +SC_P3_HIZ_QUAD_PER_TILE_H12 = 230 +SC_P3_HIZ_QUAD_PER_TILE_H13 = 231 +SC_P3_HIZ_QUAD_PER_TILE_H14 = 232 +SC_P3_HIZ_QUAD_PER_TILE_H15 = 233 +SC_P3_HIZ_QUAD_PER_TILE_H16 = 234 +SC_P0_HIZ_QUAD_COUNT = 235 +SC_P1_HIZ_QUAD_COUNT = 236 +SC_P2_HIZ_QUAD_COUNT = 237 +SC_P3_HIZ_QUAD_COUNT = 238 +SC_P0_DETAIL_QUAD_COUNT = 239 +SC_P1_DETAIL_QUAD_COUNT = 240 +SC_P2_DETAIL_QUAD_COUNT = 241 +SC_P3_DETAIL_QUAD_COUNT = 242 +SC_P0_DETAIL_QUAD_WITH_1_PIX = 243 +SC_P0_DETAIL_QUAD_WITH_2_PIX = 244 +SC_P0_DETAIL_QUAD_WITH_3_PIX = 245 +SC_P0_DETAIL_QUAD_WITH_4_PIX = 246 +SC_P1_DETAIL_QUAD_WITH_1_PIX = 247 +SC_P1_DETAIL_QUAD_WITH_2_PIX = 248 +SC_P1_DETAIL_QUAD_WITH_3_PIX = 249 +SC_P1_DETAIL_QUAD_WITH_4_PIX = 250 +SC_P2_DETAIL_QUAD_WITH_1_PIX = 251 +SC_P2_DETAIL_QUAD_WITH_2_PIX = 252 +SC_P2_DETAIL_QUAD_WITH_3_PIX = 253 +SC_P2_DETAIL_QUAD_WITH_4_PIX = 254 +SC_P3_DETAIL_QUAD_WITH_1_PIX = 255 +SC_P3_DETAIL_QUAD_WITH_2_PIX = 256 +SC_P3_DETAIL_QUAD_WITH_3_PIX = 257 +SC_P3_DETAIL_QUAD_WITH_4_PIX = 258 +SC_EARLYZ_QUAD_COUNT = 259 +SC_EARLYZ_QUAD_WITH_1_PIX = 260 +SC_EARLYZ_QUAD_WITH_2_PIX = 261 +SC_EARLYZ_QUAD_WITH_3_PIX = 262 +SC_EARLYZ_QUAD_WITH_4_PIX = 263 +SC_PKR_QUAD_PER_ROW_H1 = 264 +SC_PKR_QUAD_PER_ROW_H2 = 265 +SC_PKR_4X2_QUAD_SPLIT = 266 +SC_PKR_4X2_FILL_QUAD = 267 +SC_PKR_END_OF_VECTOR = 268 +SC_PKR_CONTROL_XFER = 269 +SC_PKR_DBHANG_FORCE_EOV = 270 +SC_REG_SCLK_BUSY = 271 +SC_GRP0_DYN_SCLK_BUSY = 272 +SC_GRP1_DYN_SCLK_BUSY = 273 +SC_GRP2_DYN_SCLK_BUSY = 274 +SC_GRP3_DYN_SCLK_BUSY = 275 +SC_GRP4_DYN_SCLK_BUSY = 276 +SC_PA0_SC_DATA_FIFO_RD = 277 +SC_PA0_SC_DATA_FIFO_WE = 278 +SC_PA1_SC_DATA_FIFO_RD = 279 +SC_PA1_SC_DATA_FIFO_WE = 280 +SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 281 +SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 282 +SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 283 +SC_PS_ARB_STALLED_FROM_BELOW = 284 +SC_PS_ARB_STARVED_FROM_ABOVE = 285 +SC_PS_ARB_SC_BUSY = 286 +SC_PS_ARB_PA_SC_BUSY = 287 +SC_PA2_SC_DATA_FIFO_RD = 288 +SC_PA2_SC_DATA_FIFO_WE = 289 +SC_PA3_SC_DATA_FIFO_RD = 290 +SC_PA3_SC_DATA_FIFO_WE = 291 +SC_PA_SC_DEALLOC_0_0_WE = 292 +SC_PA_SC_DEALLOC_0_1_WE = 293 +SC_PA_SC_DEALLOC_1_0_WE = 294 +SC_PA_SC_DEALLOC_1_1_WE = 295 +SC_PA_SC_DEALLOC_2_0_WE = 296 +SC_PA_SC_DEALLOC_2_1_WE = 297 +SC_PA_SC_DEALLOC_3_0_WE = 298 +SC_PA_SC_DEALLOC_3_1_WE = 299 +SC_PA0_SC_EOP_WE = 300 +SC_PA0_SC_EOPG_WE = 301 +SC_PA0_SC_EVENT_WE = 302 +SC_PA1_SC_EOP_WE = 303 +SC_PA1_SC_EOPG_WE = 304 +SC_PA1_SC_EVENT_WE = 305 +SC_PA2_SC_EOP_WE = 306 +SC_PA2_SC_EOPG_WE = 307 +SC_PA2_SC_EVENT_WE = 308 +SC_PA3_SC_EOP_WE = 309 +SC_PA3_SC_EOPG_WE = 310 +SC_PA3_SC_EVENT_WE = 311 +SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 312 +SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 313 +SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 314 +SC_PS_ARB_EOP_POP_SYNC_POP = 315 +SC_PS_ARB_EVENT_SYNC_POP = 316 +SC_PS_ENG_MULTICYCLE_BUBBLE = 317 +SC_PA0_SC_FPOV_WE = 318 +SC_PA1_SC_FPOV_WE = 319 +SC_PA2_SC_FPOV_WE = 320 +SC_PA3_SC_FPOV_WE = 321 +SC_PA0_SC_LPOV_WE = 322 +SC_PA1_SC_LPOV_WE = 323 +SC_PA2_SC_LPOV_WE = 324 +SC_PA3_SC_LPOV_WE = 325 +SC_SPI_DEALLOC_0_0 = 326 +SC_SPI_DEALLOC_0_1 = 327 +SC_SPI_DEALLOC_0_2 = 328 +SC_SPI_DEALLOC_1_0 = 329 +SC_SPI_DEALLOC_1_1 = 330 +SC_SPI_DEALLOC_1_2 = 331 +SC_SPI_DEALLOC_2_0 = 332 +SC_SPI_DEALLOC_2_1 = 333 +SC_SPI_DEALLOC_2_2 = 334 +SC_SPI_DEALLOC_3_0 = 335 +SC_SPI_DEALLOC_3_1 = 336 +SC_SPI_DEALLOC_3_2 = 337 +SC_SPI_FPOV_0 = 338 +SC_SPI_FPOV_1 = 339 +SC_SPI_FPOV_2 = 340 +SC_SPI_FPOV_3 = 341 +SC_SPI_EVENT = 342 +SC_PS_TS_EVENT_FIFO_PUSH = 343 +SC_PS_TS_EVENT_FIFO_POP = 344 +SC_PS_CTX_DONE_FIFO_PUSH = 345 +SC_PS_CTX_DONE_FIFO_POP = 346 +SC_MULTICYCLE_BUBBLE_FREEZE = 347 +SC_EOP_SYNC_WINDOW = 348 +SC_PA0_SC_NULL_WE = 349 +SC_PA0_SC_NULL_DEALLOC_WE = 350 +SC_PA0_SC_DATA_FIFO_EOPG_RD = 351 +SC_PA0_SC_DATA_FIFO_EOP_RD = 352 +SC_PA0_SC_DEALLOC_0_RD = 353 +SC_PA0_SC_DEALLOC_1_RD = 354 +SC_PA1_SC_DATA_FIFO_EOPG_RD = 355 +SC_PA1_SC_DATA_FIFO_EOP_RD = 356 +SC_PA1_SC_DEALLOC_0_RD = 357 +SC_PA1_SC_DEALLOC_1_RD = 358 +SC_PA1_SC_NULL_WE = 359 +SC_PA1_SC_NULL_DEALLOC_WE = 360 +SC_PA2_SC_DATA_FIFO_EOPG_RD = 361 +SC_PA2_SC_DATA_FIFO_EOP_RD = 362 +SC_PA2_SC_DEALLOC_0_RD = 363 +SC_PA2_SC_DEALLOC_1_RD = 364 +SC_PA2_SC_NULL_WE = 365 +SC_PA2_SC_NULL_DEALLOC_WE = 366 +SC_PA3_SC_DATA_FIFO_EOPG_RD = 367 +SC_PA3_SC_DATA_FIFO_EOP_RD = 368 +SC_PA3_SC_DEALLOC_0_RD = 369 +SC_PA3_SC_DEALLOC_1_RD = 370 +SC_PA3_SC_NULL_WE = 371 +SC_PA3_SC_NULL_DEALLOC_WE = 372 +SC_PS_PA0_SC_FIFO_EMPTY = 373 +SC_PS_PA0_SC_FIFO_FULL = 374 +SC_RESERVED_0 = 375 +SC_PS_PA1_SC_FIFO_EMPTY = 376 +SC_PS_PA1_SC_FIFO_FULL = 377 +SC_RESERVED_1 = 378 +SC_PS_PA2_SC_FIFO_EMPTY = 379 +SC_PS_PA2_SC_FIFO_FULL = 380 +SC_RESERVED_2 = 381 +SC_PS_PA3_SC_FIFO_EMPTY = 382 +SC_PS_PA3_SC_FIFO_FULL = 383 +SC_RESERVED_3 = 384 +SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 385 +SC_BUSY_CNT_NOT_ZERO = 386 +SC_BM_BUSY = 387 +SC_BACKEND_BUSY = 388 +SC_SCF_SCB_INTERFACE_BUSY = 389 +SC_SCB_BUSY = 390 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 391 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 392 +SC_PBB_BIN_HIST_NUM_PRIMS = 393 +SC_PBB_BATCH_HIST_NUM_PRIMS = 394 +SC_PBB_BIN_HIST_NUM_CONTEXTS = 395 +SC_PBB_BATCH_HIST_NUM_CONTEXTS = 396 +SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 397 +SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 398 +SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 399 +SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 400 +SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 401 +SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 402 +SC_PBB_BUSY = 403 +SC_PBB_BUSY_AND_NO_SENDS = 404 +SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 405 +SC_PBB_NUM_BINS = 406 +SC_PBB_END_OF_BIN = 407 +SC_PBB_END_OF_BATCH = 408 +SC_PBB_PRIMBIN_PROCESSED = 409 +SC_PBB_PRIM_ADDED_TO_BATCH = 410 +SC_PBB_NONBINNED_PRIM = 411 +SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 412 +SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 413 +SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 414 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 415 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 416 +SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 417 +SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 418 +SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 419 +SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 420 +SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 421 +SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 422 +SC_POPS_INTRA_WAVE_OVERLAPS = 423 +SC_POPS_FORCE_EOV = 424 +SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 425 +SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 426 +SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 427 +SC_FULL_FULL_QUAD = 428 +SC_FULL_HALF_QUAD = 429 +SC_FULL_QTR_QUAD = 430 +SC_HALF_FULL_QUAD = 431 +SC_HALF_HALF_QUAD = 432 +SC_HALF_QTR_QUAD = 433 +SC_QTR_FULL_QUAD = 434 +SC_QTR_HALF_QUAD = 435 +SC_QTR_QTR_QUAD = 436 +SC_GRP5_DYN_SCLK_BUSY = 437 +SC_GRP6_DYN_SCLK_BUSY = 438 +SC_GRP7_DYN_SCLK_BUSY = 439 +SC_GRP8_DYN_SCLK_BUSY = 440 +SC_GRP9_DYN_SCLK_BUSY = 441 +SC_PS_TO_BE_SCLK_GATE_STALL = 442 +SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 443 +SC_PK_BUSY = 444 +SC_PK_MAX_DEALLOC_FORCE_EOV = 445 +SC_PK_DEALLOC_WAVE_BREAK = 446 +SC_SPI_SEND = 447 +SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 448 +SC_SPI_CREDIT_AT_MAX = 449 +SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 450 +SC_BCI_SEND = 451 +SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 452 +SC_BCI_CREDIT_AT_MAX = 453 +SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 454 +SC_SPIBC_FULL_FREEZE = 455 +SC_PW_BM_PASS_EMPTY_PRIM = 456 +SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 457 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 458 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 459 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 460 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 461 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 462 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 463 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 464 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 465 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 466 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 467 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 468 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 469 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 470 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 471 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 472 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 473 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 474 +SC_DB0_TILE_INTERFACE_BUSY = 475 +SC_DB0_TILE_INTERFACE_SEND = 476 +SC_DB0_TILE_INTERFACE_SEND_EVENT = 477 +SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 478 +SC_DB0_TILE_INTERFACE_SEND_SOP = 479 +SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 480 +SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 481 +SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 482 +SC_DB1_TILE_INTERFACE_BUSY = 483 +SC_DB1_TILE_INTERFACE_SEND = 484 +SC_DB1_TILE_INTERFACE_SEND_EVENT = 485 +SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 486 +SC_DB1_TILE_INTERFACE_SEND_SOP = 487 +SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 488 +SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 489 +SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 490 +SC_BACKEND_PRIM_FIFO_FULL = 491 +SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 492 +SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 493 +SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 494 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 495 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 496 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 497 +SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 498 +SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 499 +SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 500 +SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 501 +SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 502 +SC_STALLED_BY_DB0_TILEFIFO = 503 +SC_DB0_QUAD_INTF_SEND = 504 +SC_DB0_QUAD_INTF_BUSY = 505 +SC_DB0_QUAD_INTF_STALLED_BY_DB = 506 +SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 507 +SC_DB0_QUAD_INTF_IDLE = 508 +SC_DB1_QUAD_INTF_SEND = 509 +SC_STALLED_BY_DB1_TILEFIFO = 510 +SC_DB1_QUAD_INTF_BUSY = 511 +SC_DB1_QUAD_INTF_STALLED_BY_DB = 512 +SC_DB1_QUAD_INTF_CREDIT_AT_MAX = 513 +SC_DB1_QUAD_INTF_IDLE = 514 +SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 515 +SC_PKR_WAVE_BREAK_FULL_TILE = 516 +SC_FSR_WALKED = 517 +SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 518 +SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 519 +SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 520 +SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 521 +SC_DB0_TILE_MASK_FIFO_FULL = 522 +SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL = 523 +SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 524 +SC_DB1_TILE_MASK_FIFO_FULL = 525 +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 526 +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 527 +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 528 +SC_PS_PM_PFF_PW_FULL = 529 +SC_PS_PM_ZFF_PW_FULL = 530 +SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 531 +SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H = 532 +SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 533 +SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 534 +SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 535 +SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 536 +SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 537 +SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 538 +SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H = 539 +SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 540 +SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 541 +SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 542 +SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 543 +SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 544 +SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 545 +SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 546 +SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H = 547 +SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 548 +SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 549 +SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 550 +SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 551 +SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 552 +SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 553 +SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 554 +SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 555 +SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 556 +SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 557 +SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 558 +SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 559 +SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 560 +SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 561 +SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 562 +SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 563 +SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 564 +SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 565 +SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 566 +SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 567 +SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE = 568 +SC_PBB_RESERVED = 569 +SC_BM_BE0_STALLED = 570 +SC_BM_BE1_STALLED = 571 +SC_BM_BE2_STALLED = 572 +SC_BM_BE3_STALLED = 573 +SC_BM_MULTI_ACCUM_1_BE_STALLED = 574 +SC_BM_MULTI_ACCUM_2_BE_STALLED = 575 +SC_BM_MULTI_ACCUM_3_BE_STALLED = 576 +SC_BM_MULTI_ACCUM_4_BE_STALLED = 577 +SC_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ScMap' +ScMap__enumvalues = { + 0: 'RASTER_CONFIG_SC_MAP_0', + 1: 'RASTER_CONFIG_SC_MAP_1', + 2: 'RASTER_CONFIG_SC_MAP_2', + 3: 'RASTER_CONFIG_SC_MAP_3', +} +RASTER_CONFIG_SC_MAP_0 = 0 +RASTER_CONFIG_SC_MAP_1 = 1 +RASTER_CONFIG_SC_MAP_2 = 2 +RASTER_CONFIG_SC_MAP_3 = 3 +ScMap = ctypes.c_uint32 # enum + +# values for enumeration 'ScUncertaintyRegionMode' +ScUncertaintyRegionMode__enumvalues = { + 0: 'SC_HALF_LSB', + 1: 'SC_LSB_ONE_SIDED', + 2: 'SC_LSB_TWO_SIDED', +} +SC_HALF_LSB = 0 +SC_LSB_ONE_SIDED = 1 +SC_LSB_TWO_SIDED = 2 +ScUncertaintyRegionMode = ctypes.c_uint32 # enum + +# values for enumeration 'ScUncertaintyRegionMult' +ScUncertaintyRegionMult__enumvalues = { + 0: 'SC_UR_1X', + 1: 'SC_UR_2X', + 2: 'SC_UR_4X', + 3: 'SC_UR_8X', +} +SC_UR_1X = 0 +SC_UR_2X = 1 +SC_UR_4X = 2 +SC_UR_8X = 3 +ScUncertaintyRegionMult = ctypes.c_uint32 # enum + +# values for enumeration 'ScXsel' +ScXsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 +ScXsel = ctypes.c_uint32 # enum + +# values for enumeration 'ScYsel' +ScYsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 +ScYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeMap' +SeMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_MAP_0', + 1: 'RASTER_CONFIG_SE_MAP_1', + 2: 'RASTER_CONFIG_SE_MAP_2', + 3: 'RASTER_CONFIG_SE_MAP_3', +} +RASTER_CONFIG_SE_MAP_0 = 0 +RASTER_CONFIG_SE_MAP_1 = 1 +RASTER_CONFIG_SE_MAP_2 = 2 +RASTER_CONFIG_SE_MAP_3 = 3 +SeMap = ctypes.c_uint32 # enum + +# values for enumeration 'SePairMap' +SePairMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', + 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', + 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', + 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', +} +RASTER_CONFIG_SE_PAIR_MAP_0 = 0 +RASTER_CONFIG_SE_PAIR_MAP_1 = 1 +RASTER_CONFIG_SE_PAIR_MAP_2 = 2 +RASTER_CONFIG_SE_PAIR_MAP_3 = 3 +SePairMap = ctypes.c_uint32 # enum + +# values for enumeration 'SePairXsel' +SePairXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 +SePairXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SePairYsel' +SePairYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 +SePairYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeXsel' +SeXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 +SeXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeYsel' +SeYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 +SeYsel = ctypes.c_uint32 # enum + +# values for enumeration 'VRSCombinerModeSC' +VRSCombinerModeSC__enumvalues = { + 0: 'SC_VRS_COMB_MODE_PASSTHRU', + 1: 'SC_VRS_COMB_MODE_OVERRIDE', + 2: 'SC_VRS_COMB_MODE_MIN', + 3: 'SC_VRS_COMB_MODE_MAX', + 4: 'SC_VRS_COMB_MODE_SATURATE', +} +SC_VRS_COMB_MODE_PASSTHRU = 0 +SC_VRS_COMB_MODE_OVERRIDE = 1 +SC_VRS_COMB_MODE_MIN = 2 +SC_VRS_COMB_MODE_MAX = 3 +SC_VRS_COMB_MODE_SATURATE = 4 +VRSCombinerModeSC = ctypes.c_uint32 # enum + +# values for enumeration 'VRSrate' +VRSrate__enumvalues = { + 0: 'VRS_SHADING_RATE_1X1', + 1: 'VRS_SHADING_RATE_1X2', + 2: 'VRS_SHADING_RATE_UNDEFINED0', + 3: 'VRS_SHADING_RATE_UNDEFINED1', + 4: 'VRS_SHADING_RATE_2X1', + 5: 'VRS_SHADING_RATE_2X2', + 6: 'VRS_SHADING_RATE_2X4', + 7: 'VRS_SHADING_RATE_UNDEFINED2', + 8: 'VRS_SHADING_RATE_UNDEFINED3', + 9: 'VRS_SHADING_RATE_4X2', + 10: 'VRS_SHADING_RATE_4X4', + 11: 'VRS_SHADING_RATE_UNDEFINED4', + 12: 'VRS_SHADING_RATE_16X_SSAA', + 13: 'VRS_SHADING_RATE_8X_SSAA', + 14: 'VRS_SHADING_RATE_4X_SSAA', + 15: 'VRS_SHADING_RATE_2X_SSAA', +} +VRS_SHADING_RATE_1X1 = 0 +VRS_SHADING_RATE_1X2 = 1 +VRS_SHADING_RATE_UNDEFINED0 = 2 +VRS_SHADING_RATE_UNDEFINED1 = 3 +VRS_SHADING_RATE_2X1 = 4 +VRS_SHADING_RATE_2X2 = 5 +VRS_SHADING_RATE_2X4 = 6 +VRS_SHADING_RATE_UNDEFINED2 = 7 +VRS_SHADING_RATE_UNDEFINED3 = 8 +VRS_SHADING_RATE_4X2 = 9 +VRS_SHADING_RATE_4X4 = 10 +VRS_SHADING_RATE_UNDEFINED4 = 11 +VRS_SHADING_RATE_16X_SSAA = 12 +VRS_SHADING_RATE_8X_SSAA = 13 +VRS_SHADING_RATE_4X_SSAA = 14 +VRS_SHADING_RATE_2X_SSAA = 15 +VRSrate = ctypes.c_uint32 # enum + +# values for enumeration 'TC_EA_CID' +TC_EA_CID__enumvalues = { + 0: 'TC_EA_CID_RT', + 1: 'TC_EA_CID_FMASK', + 2: 'TC_EA_CID_DCC', + 3: 'TC_EA_CID_TCPMETA', + 4: 'TC_EA_CID_Z', + 5: 'TC_EA_CID_STENCIL', + 6: 'TC_EA_CID_HTILE', + 7: 'TC_EA_CID_MISC', + 8: 'TC_EA_CID_TCP', + 9: 'TC_EA_CID_SQC', + 10: 'TC_EA_CID_CPF', + 11: 'TC_EA_CID_CPG', + 12: 'TC_EA_CID_IA', + 13: 'TC_EA_CID_WD', + 14: 'TC_EA_CID_PA', + 15: 'TC_EA_CID_UTCL2_TPI', +} +TC_EA_CID_RT = 0 +TC_EA_CID_FMASK = 1 +TC_EA_CID_DCC = 2 +TC_EA_CID_TCPMETA = 3 +TC_EA_CID_Z = 4 +TC_EA_CID_STENCIL = 5 +TC_EA_CID_HTILE = 6 +TC_EA_CID_MISC = 7 +TC_EA_CID_TCP = 8 +TC_EA_CID_SQC = 9 +TC_EA_CID_CPF = 10 +TC_EA_CID_CPG = 11 +TC_EA_CID_IA = 12 +TC_EA_CID_WD = 13 +TC_EA_CID_PA = 14 +TC_EA_CID_UTCL2_TPI = 15 +TC_EA_CID = ctypes.c_uint32 # enum + +# values for enumeration 'TC_NACKS' +TC_NACKS__enumvalues = { + 0: 'TC_NACK_NO_FAULT', + 1: 'TC_NACK_PAGE_FAULT', + 2: 'TC_NACK_PROTECTION_FAULT', + 3: 'TC_NACK_DATA_ERROR', +} +TC_NACK_NO_FAULT = 0 +TC_NACK_PAGE_FAULT = 1 +TC_NACK_PROTECTION_FAULT = 2 +TC_NACK_DATA_ERROR = 3 +TC_NACKS = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP' +TC_OP__enumvalues = { + 0: 'TC_OP_READ', + 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', + 2: 'TC_OP_ATOMIC_FMIN_RTN_32', + 3: 'TC_OP_ATOMIC_FMAX_RTN_32', + 4: 'TC_OP_RESERVED_FOP_RTN_32_0', + 5: 'TC_OP_RESERVED_FADD_RTN_32', + 6: 'TC_OP_RESERVED_FOP_RTN_32_2', + 7: 'TC_OP_ATOMIC_SWAP_RTN_32', + 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', + 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 12: 'TC_OP_PROBE_FILTER', + 13: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 15: 'TC_OP_ATOMIC_ADD_RTN_32', + 16: 'TC_OP_ATOMIC_SUB_RTN_32', + 17: 'TC_OP_ATOMIC_SMIN_RTN_32', + 18: 'TC_OP_ATOMIC_UMIN_RTN_32', + 19: 'TC_OP_ATOMIC_SMAX_RTN_32', + 20: 'TC_OP_ATOMIC_UMAX_RTN_32', + 21: 'TC_OP_ATOMIC_AND_RTN_32', + 22: 'TC_OP_ATOMIC_OR_RTN_32', + 23: 'TC_OP_ATOMIC_XOR_RTN_32', + 24: 'TC_OP_ATOMIC_INC_RTN_32', + 25: 'TC_OP_ATOMIC_DEC_RTN_32', + 26: 'TC_OP_WBINVL1_VOL', + 27: 'TC_OP_WBINVL1_SD', + 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 32: 'TC_OP_WRITE', + 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 34: 'TC_OP_ATOMIC_FMIN_RTN_64', + 35: 'TC_OP_ATOMIC_FMAX_RTN_64', + 36: 'TC_OP_RESERVED_FOP_RTN_64_0', + 37: 'TC_OP_RESERVED_FOP_RTN_64_1', + 38: 'TC_OP_RESERVED_FOP_RTN_64_2', + 39: 'TC_OP_ATOMIC_SWAP_RTN_64', + 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', + 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 44: 'TC_OP_WBINVL2_SD', + 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 47: 'TC_OP_ATOMIC_ADD_RTN_64', + 48: 'TC_OP_ATOMIC_SUB_RTN_64', + 49: 'TC_OP_ATOMIC_SMIN_RTN_64', + 50: 'TC_OP_ATOMIC_UMIN_RTN_64', + 51: 'TC_OP_ATOMIC_SMAX_RTN_64', + 52: 'TC_OP_ATOMIC_UMAX_RTN_64', + 53: 'TC_OP_ATOMIC_AND_RTN_64', + 54: 'TC_OP_ATOMIC_OR_RTN_64', + 55: 'TC_OP_ATOMIC_XOR_RTN_64', + 56: 'TC_OP_ATOMIC_INC_RTN_64', + 57: 'TC_OP_ATOMIC_DEC_RTN_64', + 58: 'TC_OP_WBL2_NC', + 59: 'TC_OP_WBL2_WC', + 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', + 64: 'TC_OP_WBINVL1', + 65: 'TC_OP_ATOMIC_FCMPSWAP_32', + 66: 'TC_OP_ATOMIC_FMIN_32', + 67: 'TC_OP_ATOMIC_FMAX_32', + 68: 'TC_OP_RESERVED_FOP_32_0', + 69: 'TC_OP_RESERVED_FADD_32', + 70: 'TC_OP_RESERVED_FOP_32_2', + 71: 'TC_OP_ATOMIC_SWAP_32', + 72: 'TC_OP_ATOMIC_CMPSWAP_32', + 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 76: 'TC_OP_INV_METADATA', + 77: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 79: 'TC_OP_ATOMIC_ADD_32', + 80: 'TC_OP_ATOMIC_SUB_32', + 81: 'TC_OP_ATOMIC_SMIN_32', + 82: 'TC_OP_ATOMIC_UMIN_32', + 83: 'TC_OP_ATOMIC_SMAX_32', + 84: 'TC_OP_ATOMIC_UMAX_32', + 85: 'TC_OP_ATOMIC_AND_32', + 86: 'TC_OP_ATOMIC_OR_32', + 87: 'TC_OP_ATOMIC_XOR_32', + 88: 'TC_OP_ATOMIC_INC_32', + 89: 'TC_OP_ATOMIC_DEC_32', + 90: 'TC_OP_INVL2_NC', + 91: 'TC_OP_NOP_RTN0', + 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', + 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', + 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', + 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', + 96: 'TC_OP_WBINVL2', + 97: 'TC_OP_ATOMIC_FCMPSWAP_64', + 98: 'TC_OP_ATOMIC_FMIN_64', + 99: 'TC_OP_ATOMIC_FMAX_64', + 100: 'TC_OP_RESERVED_FOP_64_0', + 101: 'TC_OP_RESERVED_FOP_64_1', + 102: 'TC_OP_RESERVED_FOP_64_2', + 103: 'TC_OP_ATOMIC_SWAP_64', + 104: 'TC_OP_ATOMIC_CMPSWAP_64', + 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 111: 'TC_OP_ATOMIC_ADD_64', + 112: 'TC_OP_ATOMIC_SUB_64', + 113: 'TC_OP_ATOMIC_SMIN_64', + 114: 'TC_OP_ATOMIC_UMIN_64', + 115: 'TC_OP_ATOMIC_SMAX_64', + 116: 'TC_OP_ATOMIC_UMAX_64', + 117: 'TC_OP_ATOMIC_AND_64', + 118: 'TC_OP_ATOMIC_OR_64', + 119: 'TC_OP_ATOMIC_XOR_64', + 120: 'TC_OP_ATOMIC_INC_64', + 121: 'TC_OP_ATOMIC_DEC_64', + 122: 'TC_OP_WBINVL2_NC', + 123: 'TC_OP_NOP_ACK', + 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', + 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', + 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', + 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', +} +TC_OP_READ = 0 +TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 +TC_OP_ATOMIC_FMIN_RTN_32 = 2 +TC_OP_ATOMIC_FMAX_RTN_32 = 3 +TC_OP_RESERVED_FOP_RTN_32_0 = 4 +TC_OP_RESERVED_FADD_RTN_32 = 5 +TC_OP_RESERVED_FOP_RTN_32_2 = 6 +TC_OP_ATOMIC_SWAP_RTN_32 = 7 +TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 +TC_OP_PROBE_FILTER = 12 +TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 +TC_OP_ATOMIC_ADD_RTN_32 = 15 +TC_OP_ATOMIC_SUB_RTN_32 = 16 +TC_OP_ATOMIC_SMIN_RTN_32 = 17 +TC_OP_ATOMIC_UMIN_RTN_32 = 18 +TC_OP_ATOMIC_SMAX_RTN_32 = 19 +TC_OP_ATOMIC_UMAX_RTN_32 = 20 +TC_OP_ATOMIC_AND_RTN_32 = 21 +TC_OP_ATOMIC_OR_RTN_32 = 22 +TC_OP_ATOMIC_XOR_RTN_32 = 23 +TC_OP_ATOMIC_INC_RTN_32 = 24 +TC_OP_ATOMIC_DEC_RTN_32 = 25 +TC_OP_WBINVL1_VOL = 26 +TC_OP_WBINVL1_SD = 27 +TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 +TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 +TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 +TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 +TC_OP_WRITE = 32 +TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 +TC_OP_ATOMIC_FMIN_RTN_64 = 34 +TC_OP_ATOMIC_FMAX_RTN_64 = 35 +TC_OP_RESERVED_FOP_RTN_64_0 = 36 +TC_OP_RESERVED_FOP_RTN_64_1 = 37 +TC_OP_RESERVED_FOP_RTN_64_2 = 38 +TC_OP_ATOMIC_SWAP_RTN_64 = 39 +TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 +TC_OP_WBINVL2_SD = 44 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 +TC_OP_ATOMIC_ADD_RTN_64 = 47 +TC_OP_ATOMIC_SUB_RTN_64 = 48 +TC_OP_ATOMIC_SMIN_RTN_64 = 49 +TC_OP_ATOMIC_UMIN_RTN_64 = 50 +TC_OP_ATOMIC_SMAX_RTN_64 = 51 +TC_OP_ATOMIC_UMAX_RTN_64 = 52 +TC_OP_ATOMIC_AND_RTN_64 = 53 +TC_OP_ATOMIC_OR_RTN_64 = 54 +TC_OP_ATOMIC_XOR_RTN_64 = 55 +TC_OP_ATOMIC_INC_RTN_64 = 56 +TC_OP_ATOMIC_DEC_RTN_64 = 57 +TC_OP_WBL2_NC = 58 +TC_OP_WBL2_WC = 59 +TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 +TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 +TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 +TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 +TC_OP_WBINVL1 = 64 +TC_OP_ATOMIC_FCMPSWAP_32 = 65 +TC_OP_ATOMIC_FMIN_32 = 66 +TC_OP_ATOMIC_FMAX_32 = 67 +TC_OP_RESERVED_FOP_32_0 = 68 +TC_OP_RESERVED_FADD_32 = 69 +TC_OP_RESERVED_FOP_32_2 = 70 +TC_OP_ATOMIC_SWAP_32 = 71 +TC_OP_ATOMIC_CMPSWAP_32 = 72 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 +TC_OP_INV_METADATA = 76 +TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 +TC_OP_ATOMIC_ADD_32 = 79 +TC_OP_ATOMIC_SUB_32 = 80 +TC_OP_ATOMIC_SMIN_32 = 81 +TC_OP_ATOMIC_UMIN_32 = 82 +TC_OP_ATOMIC_SMAX_32 = 83 +TC_OP_ATOMIC_UMAX_32 = 84 +TC_OP_ATOMIC_AND_32 = 85 +TC_OP_ATOMIC_OR_32 = 86 +TC_OP_ATOMIC_XOR_32 = 87 +TC_OP_ATOMIC_INC_32 = 88 +TC_OP_ATOMIC_DEC_32 = 89 +TC_OP_INVL2_NC = 90 +TC_OP_NOP_RTN0 = 91 +TC_OP_RESERVED_NON_FLOAT_32_1 = 92 +TC_OP_RESERVED_NON_FLOAT_32_2 = 93 +TC_OP_RESERVED_NON_FLOAT_32_3 = 94 +TC_OP_RESERVED_NON_FLOAT_32_4 = 95 +TC_OP_WBINVL2 = 96 +TC_OP_ATOMIC_FCMPSWAP_64 = 97 +TC_OP_ATOMIC_FMIN_64 = 98 +TC_OP_ATOMIC_FMAX_64 = 99 +TC_OP_RESERVED_FOP_64_0 = 100 +TC_OP_RESERVED_FOP_64_1 = 101 +TC_OP_RESERVED_FOP_64_2 = 102 +TC_OP_ATOMIC_SWAP_64 = 103 +TC_OP_ATOMIC_CMPSWAP_64 = 104 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 +TC_OP_ATOMIC_ADD_64 = 111 +TC_OP_ATOMIC_SUB_64 = 112 +TC_OP_ATOMIC_SMIN_64 = 113 +TC_OP_ATOMIC_UMIN_64 = 114 +TC_OP_ATOMIC_SMAX_64 = 115 +TC_OP_ATOMIC_UMAX_64 = 116 +TC_OP_ATOMIC_AND_64 = 117 +TC_OP_ATOMIC_OR_64 = 118 +TC_OP_ATOMIC_XOR_64 = 119 +TC_OP_ATOMIC_INC_64 = 120 +TC_OP_ATOMIC_DEC_64 = 121 +TC_OP_WBINVL2_NC = 122 +TC_OP_NOP_ACK = 123 +TC_OP_RESERVED_NON_FLOAT_64_1 = 124 +TC_OP_RESERVED_NON_FLOAT_64_2 = 125 +TC_OP_RESERVED_NON_FLOAT_64_3 = 126 +TC_OP_RESERVED_NON_FLOAT_64_4 = 127 +TC_OP = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP_MASKS' +TC_OP_MASKS__enumvalues = { + 8: 'TC_OP_MASK_FLUSH_DENROM', + 32: 'TC_OP_MASK_64', + 64: 'TC_OP_MASK_NO_RTN', +} +TC_OP_MASK_FLUSH_DENROM = 8 +TC_OP_MASK_64 = 32 +TC_OP_MASK_NO_RTN = 64 +TC_OP_MASKS = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_EA_CID' +GL2_EA_CID__enumvalues = { + 0: 'GL2_EA_CID_CLIENT', + 1: 'GL2_EA_CID_SDMA', + 2: 'GL2_EA_CID_RLC', + 3: 'GL2_EA_CID_SQC', + 4: 'GL2_EA_CID_CP', + 5: 'GL2_EA_CID_CPDMA', + 6: 'GL2_EA_CID_UTCL2', + 7: 'GL2_EA_CID_RT', + 8: 'GL2_EA_CID_FMASK', + 9: 'GL2_EA_CID_DCC', + 10: 'GL2_EA_CID_Z_STENCIL', + 11: 'GL2_EA_CID_ZPCPSD', + 12: 'GL2_EA_CID_HTILE', + 13: 'GL2_EA_CID_MES', + 15: 'GL2_EA_CID_TCPMETA', +} +GL2_EA_CID_CLIENT = 0 +GL2_EA_CID_SDMA = 1 +GL2_EA_CID_RLC = 2 +GL2_EA_CID_SQC = 3 +GL2_EA_CID_CP = 4 +GL2_EA_CID_CPDMA = 5 +GL2_EA_CID_UTCL2 = 6 +GL2_EA_CID_RT = 7 +GL2_EA_CID_FMASK = 8 +GL2_EA_CID_DCC = 9 +GL2_EA_CID_Z_STENCIL = 10 +GL2_EA_CID_ZPCPSD = 11 +GL2_EA_CID_HTILE = 12 +GL2_EA_CID_MES = 13 +GL2_EA_CID_TCPMETA = 15 +GL2_EA_CID = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_NACKS' +GL2_NACKS__enumvalues = { + 0: 'GL2_NACK_NO_FAULT', + 1: 'GL2_NACK_PAGE_FAULT', + 2: 'GL2_NACK_PROTECTION_FAULT', + 3: 'GL2_NACK_DATA_ERROR', +} +GL2_NACK_NO_FAULT = 0 +GL2_NACK_PAGE_FAULT = 1 +GL2_NACK_PROTECTION_FAULT = 2 +GL2_NACK_DATA_ERROR = 3 +GL2_NACKS = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_OP' +GL2_OP__enumvalues = { + 0: 'GL2_OP_READ', + 1: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', + 2: 'GL2_OP_ATOMIC_FMIN_RTN_32', + 3: 'GL2_OP_ATOMIC_FMAX_RTN_32', + 7: 'GL2_OP_ATOMIC_SWAP_RTN_32', + 8: 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', + 9: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 10: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 11: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 12: 'GL2_OP_PROBE_FILTER', + 13: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 14: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 15: 'GL2_OP_ATOMIC_ADD_RTN_32', + 16: 'GL2_OP_ATOMIC_SUB_RTN_32', + 17: 'GL2_OP_ATOMIC_SMIN_RTN_32', + 18: 'GL2_OP_ATOMIC_UMIN_RTN_32', + 19: 'GL2_OP_ATOMIC_SMAX_RTN_32', + 20: 'GL2_OP_ATOMIC_UMAX_RTN_32', + 21: 'GL2_OP_ATOMIC_AND_RTN_32', + 22: 'GL2_OP_ATOMIC_OR_RTN_32', + 23: 'GL2_OP_ATOMIC_XOR_RTN_32', + 24: 'GL2_OP_ATOMIC_INC_RTN_32', + 25: 'GL2_OP_ATOMIC_DEC_RTN_32', + 26: 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', + 32: 'GL2_OP_WRITE', + 33: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', + 34: 'GL2_OP_ATOMIC_FMIN_RTN_64', + 35: 'GL2_OP_ATOMIC_FMAX_RTN_64', + 39: 'GL2_OP_ATOMIC_SWAP_RTN_64', + 40: 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', + 41: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 42: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 43: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 47: 'GL2_OP_ATOMIC_ADD_RTN_64', + 48: 'GL2_OP_ATOMIC_SUB_RTN_64', + 49: 'GL2_OP_ATOMIC_SMIN_RTN_64', + 50: 'GL2_OP_ATOMIC_UMIN_RTN_64', + 51: 'GL2_OP_ATOMIC_SMAX_RTN_64', + 52: 'GL2_OP_ATOMIC_UMAX_RTN_64', + 53: 'GL2_OP_ATOMIC_AND_RTN_64', + 54: 'GL2_OP_ATOMIC_OR_RTN_64', + 55: 'GL2_OP_ATOMIC_XOR_RTN_64', + 56: 'GL2_OP_ATOMIC_INC_RTN_64', + 57: 'GL2_OP_ATOMIC_DEC_RTN_64', + 64: 'GL2_OP_GL1_INV', + 65: 'GL2_OP_ATOMIC_FCMPSWAP_32', + 66: 'GL2_OP_ATOMIC_FMIN_32', + 67: 'GL2_OP_ATOMIC_FMAX_32', + 71: 'GL2_OP_ATOMIC_SWAP_32', + 72: 'GL2_OP_ATOMIC_CMPSWAP_32', + 73: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 74: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 75: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 76: 'GL2_OP_ATOMIC_UMIN_8', + 77: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 79: 'GL2_OP_ATOMIC_ADD_32', + 80: 'GL2_OP_ATOMIC_SUB_32', + 81: 'GL2_OP_ATOMIC_SMIN_32', + 82: 'GL2_OP_ATOMIC_UMIN_32', + 83: 'GL2_OP_ATOMIC_SMAX_32', + 84: 'GL2_OP_ATOMIC_UMAX_32', + 85: 'GL2_OP_ATOMIC_AND_32', + 86: 'GL2_OP_ATOMIC_OR_32', + 87: 'GL2_OP_ATOMIC_XOR_32', + 88: 'GL2_OP_ATOMIC_INC_32', + 89: 'GL2_OP_ATOMIC_DEC_32', + 91: 'GL2_OP_NOP_RTN0', + 97: 'GL2_OP_ATOMIC_FCMPSWAP_64', + 98: 'GL2_OP_ATOMIC_FMIN_64', + 99: 'GL2_OP_ATOMIC_FMAX_64', + 103: 'GL2_OP_ATOMIC_SWAP_64', + 104: 'GL2_OP_ATOMIC_CMPSWAP_64', + 105: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 106: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 107: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 111: 'GL2_OP_ATOMIC_ADD_64', + 112: 'GL2_OP_ATOMIC_SUB_64', + 113: 'GL2_OP_ATOMIC_SMIN_64', + 114: 'GL2_OP_ATOMIC_UMIN_64', + 115: 'GL2_OP_ATOMIC_SMAX_64', + 116: 'GL2_OP_ATOMIC_UMAX_64', + 117: 'GL2_OP_ATOMIC_AND_64', + 118: 'GL2_OP_ATOMIC_OR_64', + 119: 'GL2_OP_ATOMIC_XOR_64', + 120: 'GL2_OP_ATOMIC_INC_64', + 121: 'GL2_OP_ATOMIC_DEC_64', + 122: 'GL2_OP_ATOMIC_UMAX_8', + 123: 'GL2_OP_NOP_ACK', +} +GL2_OP_READ = 0 +GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 +GL2_OP_ATOMIC_FMIN_RTN_32 = 2 +GL2_OP_ATOMIC_FMAX_RTN_32 = 3 +GL2_OP_ATOMIC_SWAP_RTN_32 = 7 +GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 +GL2_OP_PROBE_FILTER = 12 +GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 +GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 +GL2_OP_ATOMIC_ADD_RTN_32 = 15 +GL2_OP_ATOMIC_SUB_RTN_32 = 16 +GL2_OP_ATOMIC_SMIN_RTN_32 = 17 +GL2_OP_ATOMIC_UMIN_RTN_32 = 18 +GL2_OP_ATOMIC_SMAX_RTN_32 = 19 +GL2_OP_ATOMIC_UMAX_RTN_32 = 20 +GL2_OP_ATOMIC_AND_RTN_32 = 21 +GL2_OP_ATOMIC_OR_RTN_32 = 22 +GL2_OP_ATOMIC_XOR_RTN_32 = 23 +GL2_OP_ATOMIC_INC_RTN_32 = 24 +GL2_OP_ATOMIC_DEC_RTN_32 = 25 +GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 26 +GL2_OP_WRITE = 32 +GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 +GL2_OP_ATOMIC_FMIN_RTN_64 = 34 +GL2_OP_ATOMIC_FMAX_RTN_64 = 35 +GL2_OP_ATOMIC_SWAP_RTN_64 = 39 +GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 40 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 +GL2_OP_ATOMIC_ADD_RTN_64 = 47 +GL2_OP_ATOMIC_SUB_RTN_64 = 48 +GL2_OP_ATOMIC_SMIN_RTN_64 = 49 +GL2_OP_ATOMIC_UMIN_RTN_64 = 50 +GL2_OP_ATOMIC_SMAX_RTN_64 = 51 +GL2_OP_ATOMIC_UMAX_RTN_64 = 52 +GL2_OP_ATOMIC_AND_RTN_64 = 53 +GL2_OP_ATOMIC_OR_RTN_64 = 54 +GL2_OP_ATOMIC_XOR_RTN_64 = 55 +GL2_OP_ATOMIC_INC_RTN_64 = 56 +GL2_OP_ATOMIC_DEC_RTN_64 = 57 +GL2_OP_GL1_INV = 64 +GL2_OP_ATOMIC_FCMPSWAP_32 = 65 +GL2_OP_ATOMIC_FMIN_32 = 66 +GL2_OP_ATOMIC_FMAX_32 = 67 +GL2_OP_ATOMIC_SWAP_32 = 71 +GL2_OP_ATOMIC_CMPSWAP_32 = 72 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 +GL2_OP_ATOMIC_UMIN_8 = 76 +GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 +GL2_OP_ATOMIC_ADD_32 = 79 +GL2_OP_ATOMIC_SUB_32 = 80 +GL2_OP_ATOMIC_SMIN_32 = 81 +GL2_OP_ATOMIC_UMIN_32 = 82 +GL2_OP_ATOMIC_SMAX_32 = 83 +GL2_OP_ATOMIC_UMAX_32 = 84 +GL2_OP_ATOMIC_AND_32 = 85 +GL2_OP_ATOMIC_OR_32 = 86 +GL2_OP_ATOMIC_XOR_32 = 87 +GL2_OP_ATOMIC_INC_32 = 88 +GL2_OP_ATOMIC_DEC_32 = 89 +GL2_OP_NOP_RTN0 = 91 +GL2_OP_ATOMIC_FCMPSWAP_64 = 97 +GL2_OP_ATOMIC_FMIN_64 = 98 +GL2_OP_ATOMIC_FMAX_64 = 99 +GL2_OP_ATOMIC_SWAP_64 = 103 +GL2_OP_ATOMIC_CMPSWAP_64 = 104 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 +GL2_OP_ATOMIC_ADD_64 = 111 +GL2_OP_ATOMIC_SUB_64 = 112 +GL2_OP_ATOMIC_SMIN_64 = 113 +GL2_OP_ATOMIC_UMIN_64 = 114 +GL2_OP_ATOMIC_SMAX_64 = 115 +GL2_OP_ATOMIC_UMAX_64 = 116 +GL2_OP_ATOMIC_AND_64 = 117 +GL2_OP_ATOMIC_OR_64 = 118 +GL2_OP_ATOMIC_XOR_64 = 119 +GL2_OP_ATOMIC_INC_64 = 120 +GL2_OP_ATOMIC_DEC_64 = 121 +GL2_OP_ATOMIC_UMAX_8 = 122 +GL2_OP_NOP_ACK = 123 +GL2_OP = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_OP_MASKS' +GL2_OP_MASKS__enumvalues = { + 8: 'GL2_OP_MASK_FLUSH_DENROM', + 32: 'GL2_OP_MASK_64', + 64: 'GL2_OP_MASK_NO_RTN', +} +GL2_OP_MASK_FLUSH_DENROM = 8 +GL2_OP_MASK_64 = 32 +GL2_OP_MASK_NO_RTN = 64 +GL2_OP_MASKS = ctypes.c_uint32 # enum + +# values for enumeration 'RLC_DOORBELL_MODE' +RLC_DOORBELL_MODE__enumvalues = { + 0: 'RLC_DOORBELL_MODE_DISABLE', + 1: 'RLC_DOORBELL_MODE_ENABLE', + 2: 'RLC_DOORBELL_MODE_ENABLE_PF', + 3: 'RLC_DOORBELL_MODE_ENABLE_PF_VF', +} +RLC_DOORBELL_MODE_DISABLE = 0 +RLC_DOORBELL_MODE_ENABLE = 1 +RLC_DOORBELL_MODE_ENABLE_PF = 2 +RLC_DOORBELL_MODE_ENABLE_PF_VF = 3 +RLC_DOORBELL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'RLC_PERFCOUNTER_SEL' +RLC_PERFCOUNTER_SEL__enumvalues = { + 0: 'RLC_PERF_SEL_POWER_FEATURE_0', + 1: 'RLC_PERF_SEL_POWER_FEATURE_1', + 2: 'RLC_PERF_SEL_CP_INTERRUPT', + 3: 'RLC_PERF_SEL_GRBM_INTERRUPT', + 4: 'RLC_PERF_SEL_SPM_INTERRUPT', + 5: 'RLC_PERF_SEL_IH_INTERRUPT', + 6: 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', +} +RLC_PERF_SEL_POWER_FEATURE_0 = 0 +RLC_PERF_SEL_POWER_FEATURE_1 = 1 +RLC_PERF_SEL_CP_INTERRUPT = 2 +RLC_PERF_SEL_GRBM_INTERRUPT = 3 +RLC_PERF_SEL_SPM_INTERRUPT = 4 +RLC_PERF_SEL_IH_INTERRUPT = 5 +RLC_PERF_SEL_SERDES_COMMAND_WRITE = 6 +RLC_PERFCOUNTER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RLC_PERFMON_STATE' +RLC_PERFMON_STATE__enumvalues = { + 0: 'RLC_PERFMON_STATE_RESET', + 1: 'RLC_PERFMON_STATE_ENABLE', + 2: 'RLC_PERFMON_STATE_DISABLE', + 3: 'RLC_PERFMON_STATE_RESERVED_3', + 4: 'RLC_PERFMON_STATE_RESERVED_4', + 5: 'RLC_PERFMON_STATE_RESERVED_5', + 6: 'RLC_PERFMON_STATE_RESERVED_6', + 7: 'RLC_PERFMON_STATE_ROLLOVER', +} +RLC_PERFMON_STATE_RESET = 0 +RLC_PERFMON_STATE_ENABLE = 1 +RLC_PERFMON_STATE_DISABLE = 2 +RLC_PERFMON_STATE_RESERVED_3 = 3 +RLC_PERFMON_STATE_RESERVED_4 = 4 +RLC_PERFMON_STATE_RESERVED_5 = 5 +RLC_PERFMON_STATE_RESERVED_6 = 6 +RLC_PERFMON_STATE_ROLLOVER = 7 +RLC_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'RSPM_CMD' +RSPM_CMD__enumvalues = { + 0: 'RSPM_CMD_INVALID', + 1: 'RSPM_CMD_IDLE', + 2: 'RSPM_CMD_CALIBRATE', + 3: 'RSPM_CMD_SPM_RESET', + 4: 'RSPM_CMD_SPM_START', + 5: 'RSPM_CMD_SPM_STOP', + 6: 'RSPM_CMD_PERF_RESET', + 7: 'RSPM_CMD_PERF_SAMPLE', + 8: 'RSPM_CMD_PROF_START', + 9: 'RSPM_CMD_PROF_STOP', + 10: 'RSPM_CMD_FORCE_SAMPLE', +} +RSPM_CMD_INVALID = 0 +RSPM_CMD_IDLE = 1 +RSPM_CMD_CALIBRATE = 2 +RSPM_CMD_SPM_RESET = 3 +RSPM_CMD_SPM_START = 4 +RSPM_CMD_SPM_STOP = 5 +RSPM_CMD_PERF_RESET = 6 +RSPM_CMD_PERF_SAMPLE = 7 +RSPM_CMD_PROF_START = 8 +RSPM_CMD_PROF_STOP = 9 +RSPM_CMD_FORCE_SAMPLE = 10 +RSPM_CMD = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_BASE_MODE' +CLKGATE_BASE_MODE__enumvalues = { + 0: 'MULT_8', + 1: 'MULT_16', +} +MULT_8 = 0 +MULT_16 = 1 +CLKGATE_BASE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_SM_MODE' +CLKGATE_SM_MODE__enumvalues = { + 0: 'ON_SEQ', + 1: 'OFF_SEQ', + 2: 'PROG_SEQ', + 3: 'READ_SEQ', + 4: 'SM_MODE_RESERVED', +} +ON_SEQ = 0 +OFF_SEQ = 1 +PROG_SEQ = 2 +READ_SEQ = 3 +SM_MODE_RESERVED = 4 +CLKGATE_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_FOG_MODE' +SPI_FOG_MODE__enumvalues = { + 0: 'SPI_FOG_NONE', + 1: 'SPI_FOG_EXP', + 2: 'SPI_FOG_EXP2', + 3: 'SPI_FOG_LINEAR', +} +SPI_FOG_NONE = 0 +SPI_FOG_EXP = 1 +SPI_FOG_EXP2 = 2 +SPI_FOG_LINEAR = 3 +SPI_FOG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_LB_WAVES_SELECT' +SPI_LB_WAVES_SELECT__enumvalues = { + 0: 'HS_GS', + 1: 'PS', + 2: 'CS_NA', + 3: 'SPI_LB_WAVES_RSVD', +} +HS_GS = 0 +PS = 1 +CS_NA = 2 +SPI_LB_WAVES_RSVD = 3 +SPI_LB_WAVES_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PERFCNT_SEL' +SPI_PERFCNT_SEL__enumvalues = { + 1: 'SPI_PERF_GS_WINDOW_VALID', + 2: 'SPI_PERF_GS_BUSY', + 3: 'SPI_PERF_GS_CRAWLER_STALL', + 4: 'SPI_PERF_GS_EVENT_WAVE', + 5: 'SPI_PERF_GS_WAVE', + 6: 'SPI_PERF_GS_PERS_UPD_FULL0', + 7: 'SPI_PERF_GS_PERS_UPD_FULL1', + 8: 'SPI_PERF_GS_FIRST_SUBGRP', + 9: 'SPI_PERF_GS_HS_DEALLOC', + 10: 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', + 11: 'SPI_PERF_GS_POS0_STALL', + 12: 'SPI_PERF_GS_POS1_STALL', + 13: 'SPI_PERF_GS_INDX0_STALL', + 14: 'SPI_PERF_GS_INDX1_STALL', + 15: 'SPI_PERF_GS_PWS_STALL', + 21: 'SPI_PERF_HS_WINDOW_VALID', + 22: 'SPI_PERF_HS_BUSY', + 23: 'SPI_PERF_HS_CRAWLER_STALL', + 24: 'SPI_PERF_HS_FIRST_WAVE', + 25: 'SPI_PERF_HS_OFFCHIP_LDS_STALL', + 26: 'SPI_PERF_HS_EVENT_WAVE', + 27: 'SPI_PERF_HS_WAVE', + 28: 'SPI_PERF_HS_PERS_UPD_FULL0', + 29: 'SPI_PERF_HS_PERS_UPD_FULL1', + 30: 'SPI_PERF_HS_PWS_STALL', + 37: 'SPI_PERF_CSGN_WINDOW_VALID', + 38: 'SPI_PERF_CSGN_BUSY', + 39: 'SPI_PERF_CSGN_NUM_THREADGROUPS', + 40: 'SPI_PERF_CSGN_CRAWLER_STALL', + 41: 'SPI_PERF_CSGN_EVENT_WAVE', + 42: 'SPI_PERF_CSGN_WAVE', + 43: 'SPI_PERF_CSGN_PWS_STALL', + 44: 'SPI_PERF_CSN_WINDOW_VALID', + 45: 'SPI_PERF_CSN_BUSY', + 46: 'SPI_PERF_CSN_NUM_THREADGROUPS', + 47: 'SPI_PERF_CSN_CRAWLER_STALL', + 48: 'SPI_PERF_CSN_EVENT_WAVE', + 49: 'SPI_PERF_CSN_WAVE', + 53: 'SPI_PERF_PS0_WINDOW_VALID', + 54: 'SPI_PERF_PS1_WINDOW_VALID', + 55: 'SPI_PERF_PS2_WINDOW_VALID', + 56: 'SPI_PERF_PS3_WINDOW_VALID', + 57: 'SPI_PERF_PS0_BUSY', + 58: 'SPI_PERF_PS1_BUSY', + 59: 'SPI_PERF_PS2_BUSY', + 60: 'SPI_PERF_PS3_BUSY', + 61: 'SPI_PERF_PS0_ACTIVE', + 62: 'SPI_PERF_PS1_ACTIVE', + 63: 'SPI_PERF_PS2_ACTIVE', + 64: 'SPI_PERF_PS3_ACTIVE', + 65: 'SPI_PERF_PS0_DEALLOC', + 66: 'SPI_PERF_PS1_DEALLOC', + 67: 'SPI_PERF_PS2_DEALLOC', + 68: 'SPI_PERF_PS3_DEALLOC', + 69: 'SPI_PERF_PS0_EVENT_WAVE', + 70: 'SPI_PERF_PS1_EVENT_WAVE', + 71: 'SPI_PERF_PS2_EVENT_WAVE', + 72: 'SPI_PERF_PS3_EVENT_WAVE', + 73: 'SPI_PERF_PS0_WAVE', + 74: 'SPI_PERF_PS1_WAVE', + 75: 'SPI_PERF_PS2_WAVE', + 76: 'SPI_PERF_PS3_WAVE', + 77: 'SPI_PERF_PS0_OPT_WAVE', + 78: 'SPI_PERF_PS1_OPT_WAVE', + 79: 'SPI_PERF_PS2_OPT_WAVE', + 80: 'SPI_PERF_PS3_OPT_WAVE', + 81: 'SPI_PERF_PS0_PRIM_BIN0', + 82: 'SPI_PERF_PS1_PRIM_BIN0', + 83: 'SPI_PERF_PS2_PRIM_BIN0', + 84: 'SPI_PERF_PS3_PRIM_BIN0', + 85: 'SPI_PERF_PS0_PRIM_BIN1', + 86: 'SPI_PERF_PS1_PRIM_BIN1', + 87: 'SPI_PERF_PS2_PRIM_BIN1', + 88: 'SPI_PERF_PS3_PRIM_BIN1', + 89: 'SPI_PERF_PS0_CRAWLER_STALL', + 90: 'SPI_PERF_PS1_CRAWLER_STALL', + 91: 'SPI_PERF_PS2_CRAWLER_STALL', + 92: 'SPI_PERF_PS3_CRAWLER_STALL', + 93: 'SPI_PERF_PS_PERS_UPD_FULL0', + 94: 'SPI_PERF_PS_PERS_UPD_FULL1', + 95: 'SPI_PERF_PS0_2_WAVE_GROUPS', + 96: 'SPI_PERF_PS1_2_WAVE_GROUPS', + 97: 'SPI_PERF_PS2_2_WAVE_GROUPS', + 98: 'SPI_PERF_PS3_2_WAVE_GROUPS', + 99: 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', + 100: 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', + 101: 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', + 102: 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', + 103: 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', + 104: 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', + 105: 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', + 106: 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', + 107: 'SPI_PERF_PS_PWS_STALL', + 141: 'SPI_PERF_RA_PIPE_REQ_BIN2', + 142: 'SPI_PERF_RA_TASK_REQ_BIN3', + 143: 'SPI_PERF_RA_WR_CTL_FULL', + 144: 'SPI_PERF_RA_REQ_NO_ALLOC', + 145: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', + 146: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', + 147: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', + 148: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', + 149: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', + 150: 'SPI_PERF_RA_RES_STALL_PS', + 151: 'SPI_PERF_RA_RES_STALL_GS', + 152: 'SPI_PERF_RA_RES_STALL_HS', + 153: 'SPI_PERF_RA_RES_STALL_CSG', + 154: 'SPI_PERF_RA_RES_STALL_CSN', + 155: 'SPI_PERF_RA_TMP_STALL_PS', + 156: 'SPI_PERF_RA_TMP_STALL_GS', + 157: 'SPI_PERF_RA_TMP_STALL_HS', + 158: 'SPI_PERF_RA_TMP_STALL_CSG', + 159: 'SPI_PERF_RA_TMP_STALL_CSN', + 160: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 161: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', + 162: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', + 163: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 164: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', + 165: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 166: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', + 167: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', + 168: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 169: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', + 170: 'SPI_PERF_RA_LDS_CU_FULL_PS', + 171: 'SPI_PERF_RA_LDS_CU_FULL_HS', + 172: 'SPI_PERF_RA_LDS_CU_FULL_GS', + 173: 'SPI_PERF_RA_LDS_CU_FULL_CSG', + 174: 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 175: 'SPI_PERF_RA_BAR_CU_FULL_HS', + 176: 'SPI_PERF_RA_BAR_CU_FULL_CSG', + 177: 'SPI_PERF_RA_BAR_CU_FULL_CSN', + 178: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', + 179: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', + 180: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', + 181: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 182: 'SPI_PERF_RA_WVLIM_STALL_PS', + 183: 'SPI_PERF_RA_WVLIM_STALL_GS', + 184: 'SPI_PERF_RA_WVLIM_STALL_HS', + 185: 'SPI_PERF_RA_WVLIM_STALL_CSG', + 186: 'SPI_PERF_RA_WVLIM_STALL_CSN', + 187: 'SPI_PERF_RA_GS_LOCK', + 188: 'SPI_PERF_RA_HS_LOCK', + 189: 'SPI_PERF_RA_CSG_LOCK', + 190: 'SPI_PERF_RA_CSN_LOCK', + 191: 'SPI_PERF_RA_RSV_UPD', + 192: 'SPI_PERF_RA_PRE_ALLOC_STALL', + 193: 'SPI_PERF_RA_GFX_UNDER_TUNNEL', + 194: 'SPI_PERF_RA_CSC_UNDER_TUNNEL', + 195: 'SPI_PERF_RA_WVALLOC_STALL', + 196: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', + 197: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', + 198: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', + 199: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', + 200: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', + 201: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', + 202: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', + 203: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', + 204: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', + 205: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', + 206: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', + 207: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', + 208: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', + 209: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', + 210: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', + 211: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', + 212: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', + 213: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', + 214: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', + 215: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', + 216: 'SPI_PERF_EXP_ARB_COL_CNT', + 217: 'SPI_PERF_EXP_ARB_POS_CNT', + 218: 'SPI_PERF_EXP_ARB_GDS_CNT', + 219: 'SPI_PERF_EXP_ARB_IDX_CNT', + 220: 'SPI_PERF_EXP_WITH_CONFLICT', + 221: 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', + 222: 'SPI_PERF_GS_EXP_DONE', + 223: 'SPI_PERF_PS_EXP_DONE', + 224: 'SPI_PERF_PS_EXP_ARB_CONFLICT', + 225: 'SPI_PERF_PS_EXP_ALLOC', + 226: 'SPI_PERF_PS0_WAVEID_STARVED', + 227: 'SPI_PERF_PS1_WAVEID_STARVED', + 228: 'SPI_PERF_PS2_WAVEID_STARVED', + 229: 'SPI_PERF_PS3_WAVEID_STARVED', + 230: 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', + 231: 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', + 232: 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', + 233: 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', + 234: 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', + 235: 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', + 236: 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', + 237: 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', + 238: 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', + 239: 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', + 240: 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', + 241: 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', + 242: 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', + 243: 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', + 244: 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', + 245: 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', + 246: 'SPI_PERF_NUM_EXPGRANT_EXPORTS', + 253: 'SPI_PERF_PIX_ALLOC_PEND_CNT', + 254: 'SPI_PERF_EXPORT_SCB0_STALL', + 255: 'SPI_PERF_EXPORT_SCB1_STALL', + 256: 'SPI_PERF_EXPORT_SCB2_STALL', + 257: 'SPI_PERF_EXPORT_SCB3_STALL', + 258: 'SPI_PERF_EXPORT_DB0_STALL', + 259: 'SPI_PERF_EXPORT_DB1_STALL', + 260: 'SPI_PERF_EXPORT_DB2_STALL', + 261: 'SPI_PERF_EXPORT_DB3_STALL', + 262: 'SPI_PERF_EXPORT_DB4_STALL', + 263: 'SPI_PERF_EXPORT_DB5_STALL', + 264: 'SPI_PERF_EXPORT_DB6_STALL', + 265: 'SPI_PERF_EXPORT_DB7_STALL', + 266: 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', + 267: 'SPI_PERF_GS_NGG_STALL_MSG_VAL', + 268: 'SPI_PERF_SWC_PS_WR', + 269: 'SPI_PERF_SWC_GS_WR', + 270: 'SPI_PERF_SWC_HS_WR', + 271: 'SPI_PERF_SWC_CSGN_WR', + 272: 'SPI_PERF_SWC_CSN_WR', + 273: 'SPI_PERF_VWC_PS_WR', + 274: 'SPI_PERF_VWC_ES_WR', + 275: 'SPI_PERF_VWC_GS_WR', + 276: 'SPI_PERF_VWC_LS_WR', + 277: 'SPI_PERF_VWC_HS_WR', + 278: 'SPI_PERF_VWC_CSGN_WR', + 279: 'SPI_PERF_VWC_CSN_WR', + 280: 'SPI_PERF_EXP_THROT_UPSTEP', + 281: 'SPI_PERF_EXP_THROT_DOWNSTEP', + 282: 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', + 283: 'SPI_PERF_BUSY', +} +SPI_PERF_GS_WINDOW_VALID = 1 +SPI_PERF_GS_BUSY = 2 +SPI_PERF_GS_CRAWLER_STALL = 3 +SPI_PERF_GS_EVENT_WAVE = 4 +SPI_PERF_GS_WAVE = 5 +SPI_PERF_GS_PERS_UPD_FULL0 = 6 +SPI_PERF_GS_PERS_UPD_FULL1 = 7 +SPI_PERF_GS_FIRST_SUBGRP = 8 +SPI_PERF_GS_HS_DEALLOC = 9 +SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 10 +SPI_PERF_GS_POS0_STALL = 11 +SPI_PERF_GS_POS1_STALL = 12 +SPI_PERF_GS_INDX0_STALL = 13 +SPI_PERF_GS_INDX1_STALL = 14 +SPI_PERF_GS_PWS_STALL = 15 +SPI_PERF_HS_WINDOW_VALID = 21 +SPI_PERF_HS_BUSY = 22 +SPI_PERF_HS_CRAWLER_STALL = 23 +SPI_PERF_HS_FIRST_WAVE = 24 +SPI_PERF_HS_OFFCHIP_LDS_STALL = 25 +SPI_PERF_HS_EVENT_WAVE = 26 +SPI_PERF_HS_WAVE = 27 +SPI_PERF_HS_PERS_UPD_FULL0 = 28 +SPI_PERF_HS_PERS_UPD_FULL1 = 29 +SPI_PERF_HS_PWS_STALL = 30 +SPI_PERF_CSGN_WINDOW_VALID = 37 +SPI_PERF_CSGN_BUSY = 38 +SPI_PERF_CSGN_NUM_THREADGROUPS = 39 +SPI_PERF_CSGN_CRAWLER_STALL = 40 +SPI_PERF_CSGN_EVENT_WAVE = 41 +SPI_PERF_CSGN_WAVE = 42 +SPI_PERF_CSGN_PWS_STALL = 43 +SPI_PERF_CSN_WINDOW_VALID = 44 +SPI_PERF_CSN_BUSY = 45 +SPI_PERF_CSN_NUM_THREADGROUPS = 46 +SPI_PERF_CSN_CRAWLER_STALL = 47 +SPI_PERF_CSN_EVENT_WAVE = 48 +SPI_PERF_CSN_WAVE = 49 +SPI_PERF_PS0_WINDOW_VALID = 53 +SPI_PERF_PS1_WINDOW_VALID = 54 +SPI_PERF_PS2_WINDOW_VALID = 55 +SPI_PERF_PS3_WINDOW_VALID = 56 +SPI_PERF_PS0_BUSY = 57 +SPI_PERF_PS1_BUSY = 58 +SPI_PERF_PS2_BUSY = 59 +SPI_PERF_PS3_BUSY = 60 +SPI_PERF_PS0_ACTIVE = 61 +SPI_PERF_PS1_ACTIVE = 62 +SPI_PERF_PS2_ACTIVE = 63 +SPI_PERF_PS3_ACTIVE = 64 +SPI_PERF_PS0_DEALLOC = 65 +SPI_PERF_PS1_DEALLOC = 66 +SPI_PERF_PS2_DEALLOC = 67 +SPI_PERF_PS3_DEALLOC = 68 +SPI_PERF_PS0_EVENT_WAVE = 69 +SPI_PERF_PS1_EVENT_WAVE = 70 +SPI_PERF_PS2_EVENT_WAVE = 71 +SPI_PERF_PS3_EVENT_WAVE = 72 +SPI_PERF_PS0_WAVE = 73 +SPI_PERF_PS1_WAVE = 74 +SPI_PERF_PS2_WAVE = 75 +SPI_PERF_PS3_WAVE = 76 +SPI_PERF_PS0_OPT_WAVE = 77 +SPI_PERF_PS1_OPT_WAVE = 78 +SPI_PERF_PS2_OPT_WAVE = 79 +SPI_PERF_PS3_OPT_WAVE = 80 +SPI_PERF_PS0_PRIM_BIN0 = 81 +SPI_PERF_PS1_PRIM_BIN0 = 82 +SPI_PERF_PS2_PRIM_BIN0 = 83 +SPI_PERF_PS3_PRIM_BIN0 = 84 +SPI_PERF_PS0_PRIM_BIN1 = 85 +SPI_PERF_PS1_PRIM_BIN1 = 86 +SPI_PERF_PS2_PRIM_BIN1 = 87 +SPI_PERF_PS3_PRIM_BIN1 = 88 +SPI_PERF_PS0_CRAWLER_STALL = 89 +SPI_PERF_PS1_CRAWLER_STALL = 90 +SPI_PERF_PS2_CRAWLER_STALL = 91 +SPI_PERF_PS3_CRAWLER_STALL = 92 +SPI_PERF_PS_PERS_UPD_FULL0 = 93 +SPI_PERF_PS_PERS_UPD_FULL1 = 94 +SPI_PERF_PS0_2_WAVE_GROUPS = 95 +SPI_PERF_PS1_2_WAVE_GROUPS = 96 +SPI_PERF_PS2_2_WAVE_GROUPS = 97 +SPI_PERF_PS3_2_WAVE_GROUPS = 98 +SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 99 +SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 100 +SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 101 +SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 102 +SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 103 +SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 104 +SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 105 +SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 106 +SPI_PERF_PS_PWS_STALL = 107 +SPI_PERF_RA_PIPE_REQ_BIN2 = 141 +SPI_PERF_RA_TASK_REQ_BIN3 = 142 +SPI_PERF_RA_WR_CTL_FULL = 143 +SPI_PERF_RA_REQ_NO_ALLOC = 144 +SPI_PERF_RA_REQ_NO_ALLOC_PS = 145 +SPI_PERF_RA_REQ_NO_ALLOC_GS = 146 +SPI_PERF_RA_REQ_NO_ALLOC_HS = 147 +SPI_PERF_RA_REQ_NO_ALLOC_CSG = 148 +SPI_PERF_RA_REQ_NO_ALLOC_CSN = 149 +SPI_PERF_RA_RES_STALL_PS = 150 +SPI_PERF_RA_RES_STALL_GS = 151 +SPI_PERF_RA_RES_STALL_HS = 152 +SPI_PERF_RA_RES_STALL_CSG = 153 +SPI_PERF_RA_RES_STALL_CSN = 154 +SPI_PERF_RA_TMP_STALL_PS = 155 +SPI_PERF_RA_TMP_STALL_GS = 156 +SPI_PERF_RA_TMP_STALL_HS = 157 +SPI_PERF_RA_TMP_STALL_CSG = 158 +SPI_PERF_RA_TMP_STALL_CSN = 159 +SPI_PERF_RA_WAVE_SIMD_FULL_PS = 160 +SPI_PERF_RA_WAVE_SIMD_FULL_GS = 161 +SPI_PERF_RA_WAVE_SIMD_FULL_HS = 162 +SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 163 +SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 164 +SPI_PERF_RA_VGPR_SIMD_FULL_PS = 165 +SPI_PERF_RA_VGPR_SIMD_FULL_GS = 166 +SPI_PERF_RA_VGPR_SIMD_FULL_HS = 167 +SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 168 +SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 169 +SPI_PERF_RA_LDS_CU_FULL_PS = 170 +SPI_PERF_RA_LDS_CU_FULL_HS = 171 +SPI_PERF_RA_LDS_CU_FULL_GS = 172 +SPI_PERF_RA_LDS_CU_FULL_CSG = 173 +SPI_PERF_RA_LDS_CU_FULL_CSN = 174 +SPI_PERF_RA_BAR_CU_FULL_HS = 175 +SPI_PERF_RA_BAR_CU_FULL_CSG = 176 +SPI_PERF_RA_BAR_CU_FULL_CSN = 177 +SPI_PERF_RA_BULKY_CU_FULL_CSG = 178 +SPI_PERF_RA_BULKY_CU_FULL_CSN = 179 +SPI_PERF_RA_TGLIM_CU_FULL_CSG = 180 +SPI_PERF_RA_TGLIM_CU_FULL_CSN = 181 +SPI_PERF_RA_WVLIM_STALL_PS = 182 +SPI_PERF_RA_WVLIM_STALL_GS = 183 +SPI_PERF_RA_WVLIM_STALL_HS = 184 +SPI_PERF_RA_WVLIM_STALL_CSG = 185 +SPI_PERF_RA_WVLIM_STALL_CSN = 186 +SPI_PERF_RA_GS_LOCK = 187 +SPI_PERF_RA_HS_LOCK = 188 +SPI_PERF_RA_CSG_LOCK = 189 +SPI_PERF_RA_CSN_LOCK = 190 +SPI_PERF_RA_RSV_UPD = 191 +SPI_PERF_RA_PRE_ALLOC_STALL = 192 +SPI_PERF_RA_GFX_UNDER_TUNNEL = 193 +SPI_PERF_RA_CSC_UNDER_TUNNEL = 194 +SPI_PERF_RA_WVALLOC_STALL = 195 +SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 196 +SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 197 +SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 198 +SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 199 +SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 200 +SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 201 +SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 202 +SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 203 +SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 204 +SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 205 +SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 206 +SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 207 +SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 208 +SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 209 +SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 210 +SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 211 +SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 212 +SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 213 +SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 214 +SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 215 +SPI_PERF_EXP_ARB_COL_CNT = 216 +SPI_PERF_EXP_ARB_POS_CNT = 217 +SPI_PERF_EXP_ARB_GDS_CNT = 218 +SPI_PERF_EXP_ARB_IDX_CNT = 219 +SPI_PERF_EXP_WITH_CONFLICT = 220 +SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 221 +SPI_PERF_GS_EXP_DONE = 222 +SPI_PERF_PS_EXP_DONE = 223 +SPI_PERF_PS_EXP_ARB_CONFLICT = 224 +SPI_PERF_PS_EXP_ALLOC = 225 +SPI_PERF_PS0_WAVEID_STARVED = 226 +SPI_PERF_PS1_WAVEID_STARVED = 227 +SPI_PERF_PS2_WAVEID_STARVED = 228 +SPI_PERF_PS3_WAVEID_STARVED = 229 +SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 230 +SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 231 +SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 232 +SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 233 +SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 234 +SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 235 +SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 236 +SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 237 +SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 238 +SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 239 +SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 240 +SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 241 +SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 242 +SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 243 +SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 244 +SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 245 +SPI_PERF_NUM_EXPGRANT_EXPORTS = 246 +SPI_PERF_PIX_ALLOC_PEND_CNT = 253 +SPI_PERF_EXPORT_SCB0_STALL = 254 +SPI_PERF_EXPORT_SCB1_STALL = 255 +SPI_PERF_EXPORT_SCB2_STALL = 256 +SPI_PERF_EXPORT_SCB3_STALL = 257 +SPI_PERF_EXPORT_DB0_STALL = 258 +SPI_PERF_EXPORT_DB1_STALL = 259 +SPI_PERF_EXPORT_DB2_STALL = 260 +SPI_PERF_EXPORT_DB3_STALL = 261 +SPI_PERF_EXPORT_DB4_STALL = 262 +SPI_PERF_EXPORT_DB5_STALL = 263 +SPI_PERF_EXPORT_DB6_STALL = 264 +SPI_PERF_EXPORT_DB7_STALL = 265 +SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 266 +SPI_PERF_GS_NGG_STALL_MSG_VAL = 267 +SPI_PERF_SWC_PS_WR = 268 +SPI_PERF_SWC_GS_WR = 269 +SPI_PERF_SWC_HS_WR = 270 +SPI_PERF_SWC_CSGN_WR = 271 +SPI_PERF_SWC_CSN_WR = 272 +SPI_PERF_VWC_PS_WR = 273 +SPI_PERF_VWC_ES_WR = 274 +SPI_PERF_VWC_GS_WR = 275 +SPI_PERF_VWC_LS_WR = 276 +SPI_PERF_VWC_HS_WR = 277 +SPI_PERF_VWC_CSGN_WR = 278 +SPI_PERF_VWC_CSN_WR = 279 +SPI_PERF_EXP_THROT_UPSTEP = 280 +SPI_PERF_EXP_THROT_DOWNSTEP = 281 +SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 282 +SPI_PERF_BUSY = 283 +SPI_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' +SPI_PNT_SPRITE_OVERRIDE__enumvalues = { + 0: 'SPI_PNT_SPRITE_SEL_0', + 1: 'SPI_PNT_SPRITE_SEL_1', + 2: 'SPI_PNT_SPRITE_SEL_S', + 3: 'SPI_PNT_SPRITE_SEL_T', + 4: 'SPI_PNT_SPRITE_SEL_NONE', +} +SPI_PNT_SPRITE_SEL_0 = 0 +SPI_PNT_SPRITE_SEL_1 = 1 +SPI_PNT_SPRITE_SEL_S = 2 +SPI_PNT_SPRITE_SEL_T = 3 +SPI_PNT_SPRITE_SEL_NONE = 4 +SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PS_LDS_GROUP_SIZE' +SPI_PS_LDS_GROUP_SIZE__enumvalues = { + 0: 'SPI_PS_LDS_GROUP_1', + 1: 'SPI_PS_LDS_GROUP_2', + 2: 'SPI_PS_LDS_GROUP_4', +} +SPI_PS_LDS_GROUP_1 = 0 +SPI_PS_LDS_GROUP_2 = 1 +SPI_PS_LDS_GROUP_4 = 2 +SPI_PS_LDS_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SAMPLE_CNTL' +SPI_SAMPLE_CNTL__enumvalues = { + 0: 'CENTROIDS_ONLY', + 1: 'CENTERS_ONLY', + 2: 'CENTROIDS_AND_CENTERS', + 3: 'UNDEF', +} +CENTROIDS_ONLY = 0 +CENTERS_ONLY = 1 +CENTROIDS_AND_CENTERS = 2 +UNDEF = 3 +SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_EX_FORMAT' +SPI_SHADER_EX_FORMAT__enumvalues = { + 0: 'SPI_SHADER_ZERO', + 1: 'SPI_SHADER_32_R', + 2: 'SPI_SHADER_32_GR', + 3: 'SPI_SHADER_32_AR', + 4: 'SPI_SHADER_FP16_ABGR', + 5: 'SPI_SHADER_UNORM16_ABGR', + 6: 'SPI_SHADER_SNORM16_ABGR', + 7: 'SPI_SHADER_UINT16_ABGR', + 8: 'SPI_SHADER_SINT16_ABGR', + 9: 'SPI_SHADER_32_ABGR', +} +SPI_SHADER_ZERO = 0 +SPI_SHADER_32_R = 1 +SPI_SHADER_32_GR = 2 +SPI_SHADER_32_AR = 3 +SPI_SHADER_FP16_ABGR = 4 +SPI_SHADER_UNORM16_ABGR = 5 +SPI_SHADER_SNORM16_ABGR = 6 +SPI_SHADER_UINT16_ABGR = 7 +SPI_SHADER_SINT16_ABGR = 8 +SPI_SHADER_32_ABGR = 9 +SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_FORMAT' +SPI_SHADER_FORMAT__enumvalues = { + 0: 'SPI_SHADER_NONE', + 1: 'SPI_SHADER_1COMP', + 2: 'SPI_SHADER_2COMP', + 3: 'SPI_SHADER_4COMPRESS', + 4: 'SPI_SHADER_4COMP', +} +SPI_SHADER_NONE = 0 +SPI_SHADER_1COMP = 1 +SPI_SHADER_2COMP = 2 +SPI_SHADER_4COMPRESS = 3 +SPI_SHADER_4COMP = 4 +SPI_SHADER_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ADDRESS_MODE' +SH_MEM_ADDRESS_MODE__enumvalues = { + 0: 'SH_MEM_ADDRESS_MODE_64', + 1: 'SH_MEM_ADDRESS_MODE_32', +} +SH_MEM_ADDRESS_MODE_64 = 0 +SH_MEM_ADDRESS_MODE_32 = 1 +SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ALIGNMENT_MODE' +SH_MEM_ALIGNMENT_MODE__enumvalues = { + 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', + 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', + 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', +} +SH_MEM_ALIGNMENT_MODE_DWORD = 0 +SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 +SH_MEM_ALIGNMENT_MODE_STRICT = 2 +SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 +SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQG_PERF_SEL' +SQG_PERF_SEL__enumvalues = { + 0: 'SQG_PERF_SEL_NONE', + 1: 'SQG_PERF_SEL_MSG_BUS_BUSY', + 2: 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', + 3: 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', + 4: 'SQG_PERF_SEL_EXP_BUS0_BUSY', + 5: 'SQG_PERF_SEL_EXP_BUS1_BUSY', + 6: 'SQG_PERF_SEL_TTRACE_REQS', + 7: 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', + 8: 'SQG_PERF_SEL_TTRACE_STALL', + 9: 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', + 10: 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', + 11: 'SQG_PERF_SEL_EVENTS', + 12: 'SQG_PERF_SEL_WAVES_RESTORED', + 13: 'SQG_PERF_SEL_WAVES_SAVED', + 14: 'SQG_PERF_SEL_ACCUM_PREV', + 15: 'SQG_PERF_SEL_CYCLES', + 16: 'SQG_PERF_SEL_BUSY_CYCLES', + 17: 'SQG_PERF_SEL_WAVE_CYCLES', + 18: 'SQG_PERF_SEL_MSG', + 19: 'SQG_PERF_SEL_MSG_INTERRUPT', + 20: 'SQG_PERF_SEL_WAVES', + 21: 'SQG_PERF_SEL_WAVES_32', + 22: 'SQG_PERF_SEL_WAVES_64', + 23: 'SQG_PERF_SEL_LEVEL_WAVES', + 24: 'SQG_PERF_SEL_ITEMS', + 25: 'SQG_PERF_SEL_WAVE32_ITEMS', + 26: 'SQG_PERF_SEL_WAVE64_ITEMS', + 27: 'SQG_PERF_SEL_PS_QUADS', + 28: 'SQG_PERF_SEL_WAVES_EQ_64', + 29: 'SQG_PERF_SEL_WAVES_EQ_32', + 30: 'SQG_PERF_SEL_WAVES_LT_64', + 31: 'SQG_PERF_SEL_WAVES_LT_48', + 32: 'SQG_PERF_SEL_WAVES_LT_32', + 33: 'SQG_PERF_SEL_WAVES_LT_16', + 34: 'SQG_PERF_SEL_DUMMY_LAST', +} +SQG_PERF_SEL_NONE = 0 +SQG_PERF_SEL_MSG_BUS_BUSY = 1 +SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 2 +SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 3 +SQG_PERF_SEL_EXP_BUS0_BUSY = 4 +SQG_PERF_SEL_EXP_BUS1_BUSY = 5 +SQG_PERF_SEL_TTRACE_REQS = 6 +SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 7 +SQG_PERF_SEL_TTRACE_STALL = 8 +SQG_PERF_SEL_TTRACE_LOST_PACKETS = 9 +SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 10 +SQG_PERF_SEL_EVENTS = 11 +SQG_PERF_SEL_WAVES_RESTORED = 12 +SQG_PERF_SEL_WAVES_SAVED = 13 +SQG_PERF_SEL_ACCUM_PREV = 14 +SQG_PERF_SEL_CYCLES = 15 +SQG_PERF_SEL_BUSY_CYCLES = 16 +SQG_PERF_SEL_WAVE_CYCLES = 17 +SQG_PERF_SEL_MSG = 18 +SQG_PERF_SEL_MSG_INTERRUPT = 19 +SQG_PERF_SEL_WAVES = 20 +SQG_PERF_SEL_WAVES_32 = 21 +SQG_PERF_SEL_WAVES_64 = 22 +SQG_PERF_SEL_LEVEL_WAVES = 23 +SQG_PERF_SEL_ITEMS = 24 +SQG_PERF_SEL_WAVE32_ITEMS = 25 +SQG_PERF_SEL_WAVE64_ITEMS = 26 +SQG_PERF_SEL_PS_QUADS = 27 +SQG_PERF_SEL_WAVES_EQ_64 = 28 +SQG_PERF_SEL_WAVES_EQ_32 = 29 +SQG_PERF_SEL_WAVES_LT_64 = 30 +SQG_PERF_SEL_WAVES_LT_48 = 31 +SQG_PERF_SEL_WAVES_LT_32 = 32 +SQG_PERF_SEL_WAVES_LT_16 = 33 +SQG_PERF_SEL_DUMMY_LAST = 34 +SQG_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_CAC_POWER_SEL' +SQ_CAC_POWER_SEL__enumvalues = { + 0: 'SQ_CAC_POWER_VALU', + 1: 'SQ_CAC_POWER_VALU0', + 2: 'SQ_CAC_POWER_VALU1', + 3: 'SQ_CAC_POWER_VALU2', + 4: 'SQ_CAC_POWER_GPR_RD', + 5: 'SQ_CAC_POWER_GPR_WR', + 6: 'SQ_CAC_POWER_LDS_BUSY', + 7: 'SQ_CAC_POWER_ALU_BUSY', + 8: 'SQ_CAC_POWER_TEX_BUSY', +} +SQ_CAC_POWER_VALU = 0 +SQ_CAC_POWER_VALU0 = 1 +SQ_CAC_POWER_VALU1 = 2 +SQ_CAC_POWER_VALU2 = 3 +SQ_CAC_POWER_GPR_RD = 4 +SQ_CAC_POWER_GPR_WR = 5 +SQ_CAC_POWER_LDS_BUSY = 6 +SQ_CAC_POWER_ALU_BUSY = 7 +SQ_CAC_POWER_TEX_BUSY = 8 +SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_EDC_INFO_SOURCE' +SQ_EDC_INFO_SOURCE__enumvalues = { + 0: 'SQ_EDC_INFO_SOURCE_INVALID', + 1: 'SQ_EDC_INFO_SOURCE_INST', + 2: 'SQ_EDC_INFO_SOURCE_SGPR', + 3: 'SQ_EDC_INFO_SOURCE_VGPR', + 4: 'SQ_EDC_INFO_SOURCE_LDS', + 5: 'SQ_EDC_INFO_SOURCE_GDS', + 6: 'SQ_EDC_INFO_SOURCE_TA', +} +SQ_EDC_INFO_SOURCE_INVALID = 0 +SQ_EDC_INFO_SOURCE_INST = 1 +SQ_EDC_INFO_SOURCE_SGPR = 2 +SQ_EDC_INFO_SOURCE_VGPR = 3 +SQ_EDC_INFO_SOURCE_LDS = 4 +SQ_EDC_INFO_SOURCE_GDS = 5 +SQ_EDC_INFO_SOURCE_TA = 6 +SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IBUF_ST' +SQ_IBUF_ST__enumvalues = { + 0: 'SQ_IBUF_IB_IDLE', + 1: 'SQ_IBUF_IB_INI_WAIT_GNT', + 2: 'SQ_IBUF_IB_INI_WAIT_DRET', + 3: 'SQ_IBUF_IB_LE_4DW', + 4: 'SQ_IBUF_IB_WAIT_DRET', + 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', + 6: 'SQ_IBUF_IB_DRET', + 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', +} +SQ_IBUF_IB_IDLE = 0 +SQ_IBUF_IB_INI_WAIT_GNT = 1 +SQ_IBUF_IB_INI_WAIT_DRET = 2 +SQ_IBUF_IB_LE_4DW = 3 +SQ_IBUF_IB_WAIT_DRET = 4 +SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 +SQ_IBUF_IB_DRET = 6 +SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 +SQ_IBUF_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IMG_FILTER_TYPE' +SQ_IMG_FILTER_TYPE__enumvalues = { + 0: 'SQ_IMG_FILTER_MODE_BLEND', + 1: 'SQ_IMG_FILTER_MODE_MIN', + 2: 'SQ_IMG_FILTER_MODE_MAX', +} +SQ_IMG_FILTER_MODE_BLEND = 0 +SQ_IMG_FILTER_MODE_MIN = 1 +SQ_IMG_FILTER_MODE_MAX = 2 +SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_CMD' +SQ_IND_CMD_CMD__enumvalues = { + 0: 'SQ_IND_CMD_CMD_NULL', + 1: 'SQ_IND_CMD_CMD_SETHALT', + 2: 'SQ_IND_CMD_CMD_SAVECTX', + 3: 'SQ_IND_CMD_CMD_KILL', + 4: 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', + 5: 'SQ_IND_CMD_CMD_TRAP', + 6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO', + 7: 'SQ_IND_CMD_CMD_SETFATALHALT', + 8: 'SQ_IND_CMD_CMD_SINGLE_STEP', +} +SQ_IND_CMD_CMD_NULL = 0 +SQ_IND_CMD_CMD_SETHALT = 1 +SQ_IND_CMD_CMD_SAVECTX = 2 +SQ_IND_CMD_CMD_KILL = 3 +SQ_IND_CMD_CMD_TRAP_AFTER_INST = 4 +SQ_IND_CMD_CMD_TRAP = 5 +SQ_IND_CMD_CMD_SET_SPI_PRIO = 6 +SQ_IND_CMD_CMD_SETFATALHALT = 7 +SQ_IND_CMD_CMD_SINGLE_STEP = 8 +SQ_IND_CMD_CMD = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_MODE' +SQ_IND_CMD_MODE__enumvalues = { + 0: 'SQ_IND_CMD_MODE_SINGLE', + 1: 'SQ_IND_CMD_MODE_BROADCAST', + 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', + 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', +} +SQ_IND_CMD_MODE_SINGLE = 0 +SQ_IND_CMD_MODE_BROADCAST = 1 +SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 +SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 +SQ_IND_CMD_MODE_BROADCAST_ME = 4 +SQ_IND_CMD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INST_STR_ST' +SQ_INST_STR_ST__enumvalues = { + 0: 'SQ_INST_STR_IB_WAVE_NORML', + 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 4: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', + 5: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', +} +SQ_INST_STR_IB_WAVE_NORML = 0 +SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 +SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 +SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 +SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 4 +SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 5 +SQ_INST_STR_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INST_TYPE' +SQ_INST_TYPE__enumvalues = { + 0: 'SQ_INST_TYPE_VALU', + 1: 'SQ_INST_TYPE_SCALAR', + 2: 'SQ_INST_TYPE_TEX', + 3: 'SQ_INST_TYPE_LDS', + 4: 'SQ_INST_TYPE_LDS_DIRECT', + 5: 'SQ_INST_TYPE_EXP', + 6: 'SQ_INST_TYPE_MSG', + 7: 'SQ_INST_TYPE_BARRIER', + 8: 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', + 9: 'SQ_INST_TYPE_BRANCH_TAKEN', + 10: 'SQ_INST_TYPE_JUMP', + 11: 'SQ_INST_TYPE_OTHER', + 12: 'SQ_INST_TYPE_NONE', +} +SQ_INST_TYPE_VALU = 0 +SQ_INST_TYPE_SCALAR = 1 +SQ_INST_TYPE_TEX = 2 +SQ_INST_TYPE_LDS = 3 +SQ_INST_TYPE_LDS_DIRECT = 4 +SQ_INST_TYPE_EXP = 5 +SQ_INST_TYPE_MSG = 6 +SQ_INST_TYPE_BARRIER = 7 +SQ_INST_TYPE_BRANCH_NOT_TAKEN = 8 +SQ_INST_TYPE_BRANCH_TAKEN = 9 +SQ_INST_TYPE_JUMP = 10 +SQ_INST_TYPE_OTHER = 11 +SQ_INST_TYPE_NONE = 12 +SQ_INST_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_LLC_CTL' +SQ_LLC_CTL__enumvalues = { + 0: 'SQ_LLC_0', + 1: 'SQ_LLC_1', + 2: 'SQ_LLC_RSVD_2', + 3: 'SQ_LLC_BYPASS', +} +SQ_LLC_0 = 0 +SQ_LLC_1 = 1 +SQ_LLC_RSVD_2 = 2 +SQ_LLC_BYPASS = 3 +SQ_LLC_CTL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_NO_INST_ISSUE' +SQ_NO_INST_ISSUE__enumvalues = { + 0: 'SQ_NO_INST_ISSUE_NO_INSTS', + 1: 'SQ_NO_INST_ISSUE_ALU_DEP', + 2: 'SQ_NO_INST_ISSUE_S_WAITCNT', + 3: 'SQ_NO_INST_ISSUE_NO_ARB_WIN', + 4: 'SQ_NO_INST_ISSUE_SLEEP_WAIT', + 5: 'SQ_NO_INST_ISSUE_BARRIER_WAIT', + 6: 'SQ_NO_INST_ISSUE_OTHER', +} +SQ_NO_INST_ISSUE_NO_INSTS = 0 +SQ_NO_INST_ISSUE_ALU_DEP = 1 +SQ_NO_INST_ISSUE_S_WAITCNT = 2 +SQ_NO_INST_ISSUE_NO_ARB_WIN = 3 +SQ_NO_INST_ISSUE_SLEEP_WAIT = 4 +SQ_NO_INST_ISSUE_BARRIER_WAIT = 5 +SQ_NO_INST_ISSUE_OTHER = 6 +SQ_NO_INST_ISSUE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_OOB_SELECT' +SQ_OOB_SELECT__enumvalues = { + 0: 'SQ_OOB_INDEX_AND_OFFSET', + 1: 'SQ_OOB_INDEX_ONLY', + 2: 'SQ_OOB_NUM_RECORDS_0', + 3: 'SQ_OOB_COMPLETE', +} +SQ_OOB_INDEX_AND_OFFSET = 0 +SQ_OOB_INDEX_ONLY = 1 +SQ_OOB_NUM_RECORDS_0 = 2 +SQ_OOB_COMPLETE = 3 +SQ_OOB_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_PERF_SEL' +SQ_PERF_SEL__enumvalues = { + 0: 'SQ_PERF_SEL_NONE', + 1: 'SQ_PERF_SEL_ACCUM_PREV', + 2: 'SQ_PERF_SEL_CYCLES', + 3: 'SQ_PERF_SEL_BUSY_CYCLES', + 4: 'SQ_PERF_SEL_WAVES', + 5: 'SQ_PERF_SEL_WAVES_32', + 6: 'SQ_PERF_SEL_WAVES_64', + 7: 'SQ_PERF_SEL_LEVEL_WAVES', + 8: 'SQ_PERF_SEL_ITEMS', + 9: 'SQ_PERF_SEL_WAVE32_ITEMS', + 10: 'SQ_PERF_SEL_WAVE64_ITEMS', + 11: 'SQ_PERF_SEL_PS_QUADS', + 12: 'SQ_PERF_SEL_EVENTS', + 13: 'SQ_PERF_SEL_WAVES_EQ_32', + 14: 'SQ_PERF_SEL_WAVES_EQ_64', + 15: 'SQ_PERF_SEL_WAVES_LT_64', + 16: 'SQ_PERF_SEL_WAVES_LT_48', + 17: 'SQ_PERF_SEL_WAVES_LT_32', + 18: 'SQ_PERF_SEL_WAVES_LT_16', + 19: 'SQ_PERF_SEL_WAVES_RESTORED', + 20: 'SQ_PERF_SEL_WAVES_SAVED', + 21: 'SQ_PERF_SEL_MSG', + 22: 'SQ_PERF_SEL_MSG_INTERRUPT', + 23: 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', + 24: 'SQ_PERF_SEL_WAVE_CYCLES', + 25: 'SQ_PERF_SEL_WAVE_READY', + 26: 'SQ_PERF_SEL_WAIT_INST_ANY', + 27: 'SQ_PERF_SEL_WAIT_INST_VALU', + 28: 'SQ_PERF_SEL_WAIT_INST_SCA', + 29: 'SQ_PERF_SEL_WAIT_INST_LDS', + 30: 'SQ_PERF_SEL_WAIT_INST_TEX', + 31: 'SQ_PERF_SEL_WAIT_INST_FLAT', + 32: 'SQ_PERF_SEL_WAIT_INST_VMEM', + 33: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', + 34: 'SQ_PERF_SEL_WAIT_INST_BR_MSG', + 35: 'SQ_PERF_SEL_WAIT_ANY', + 36: 'SQ_PERF_SEL_WAIT_CNT_ANY', + 37: 'SQ_PERF_SEL_WAIT_CNT_VMVS', + 38: 'SQ_PERF_SEL_WAIT_CNT_LGKM', + 39: 'SQ_PERF_SEL_WAIT_CNT_EXP', + 40: 'SQ_PERF_SEL_WAIT_TTRACE', + 41: 'SQ_PERF_SEL_WAIT_IFETCH', + 42: 'SQ_PERF_SEL_WAIT_BARRIER', + 43: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', + 44: 'SQ_PERF_SEL_WAIT_SLEEP', + 45: 'SQ_PERF_SEL_WAIT_DELAY_ALU', + 46: 'SQ_PERF_SEL_WAIT_DEPCTR', + 47: 'SQ_PERF_SEL_WAIT_OTHER', + 48: 'SQ_PERF_SEL_INSTS_ALL', + 49: 'SQ_PERF_SEL_INSTS_BRANCH', + 50: 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', + 51: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', + 52: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', + 53: 'SQ_PERF_SEL_INSTS_EXP_GDS', + 54: 'SQ_PERF_SEL_INSTS_GDS', + 55: 'SQ_PERF_SEL_INSTS_EXP', + 56: 'SQ_PERF_SEL_INSTS_FLAT', + 57: 'SQ_PERF_SEL_INSTS_LDS', + 58: 'SQ_PERF_SEL_INSTS_SALU', + 59: 'SQ_PERF_SEL_INSTS_SMEM', + 60: 'SQ_PERF_SEL_INSTS_SMEM_NORM', + 61: 'SQ_PERF_SEL_INSTS_SENDMSG', + 62: 'SQ_PERF_SEL_INSTS_VALU', + 63: 'SQ_PERF_SEL_INSTS_VALU_TRANS32', + 64: 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', + 65: 'SQ_PERF_SEL_INSTS_TEX', + 66: 'SQ_PERF_SEL_INSTS_TEX_LOAD', + 67: 'SQ_PERF_SEL_INSTS_TEX_STORE', + 68: 'SQ_PERF_SEL_INSTS_DELAY_ALU', + 69: 'SQ_PERF_SEL_INSTS_INTERNAL', + 70: 'SQ_PERF_SEL_INSTS_WAVE32', + 71: 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', + 72: 'SQ_PERF_SEL_INSTS_WAVE32_LDS', + 73: 'SQ_PERF_SEL_INSTS_WAVE32_VALU', + 74: 'SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS', + 75: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', + 76: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', + 77: 'SQ_PERF_SEL_INSTS_WAVE32_TEX', + 78: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', + 79: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', + 80: 'SQ_PERF_SEL_ITEM_CYCLES_VALU', + 81: 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', + 82: 'SQ_PERF_SEL_WAVE32_INSTS', + 83: 'SQ_PERF_SEL_WAVE64_INSTS', + 84: 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', + 85: 'SQ_PERF_SEL_WAVE64_HALF_SKIP', + 86: 'SQ_PERF_SEL_INST_LEVEL_EXP', + 87: 'SQ_PERF_SEL_INST_LEVEL_GDS', + 88: 'SQ_PERF_SEL_INST_LEVEL_LDS', + 89: 'SQ_PERF_SEL_INST_LEVEL_SMEM', + 90: 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', + 91: 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', + 92: 'SQ_PERF_SEL_IFETCH_REQS', + 93: 'SQ_PERF_SEL_IFETCH_LEVEL', + 94: 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', + 95: 'SQ_PERF_SEL_VALU_SGATHER_STALL', + 96: 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', + 97: 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', + 98: 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', + 99: 'SQ_PERF_SEL_SALU_SGATHER_STALL', + 100: 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', + 101: 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', + 102: 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', + 103: 'SQ_PERF_SEL_INST_CYCLES_VALU', + 104: 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', + 105: 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', + 106: 'SQ_PERF_SEL_INST_CYCLES_VMEM', + 107: 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', + 108: 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', + 109: 'SQ_PERF_SEL_INST_CYCLES_LDS', + 110: 'SQ_PERF_SEL_INST_CYCLES_TEX', + 111: 'SQ_PERF_SEL_INST_CYCLES_FLAT', + 112: 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', + 113: 'SQ_PERF_SEL_INST_CYCLES_EXP', + 114: 'SQ_PERF_SEL_INST_CYCLES_GDS', + 115: 'SQ_PERF_SEL_VALU_STARVE', + 116: 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', + 117: 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', + 118: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 119: 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', + 120: 'SQ_PERF_SEL_VMEM_BUS_STALL', + 121: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', + 122: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', + 123: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', + 124: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', + 125: 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', + 126: 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', + 127: 'SQ_PERF_SEL_SALU_PIPE_STALL', + 128: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', + 129: 'SQ_PERF_SEL_MSG_BUS_BUSY', + 130: 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', + 131: 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', + 132: 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', + 133: 'SQ_PERF_SEL_EXP_BUS0_BUSY', + 134: 'SQ_PERF_SEL_EXP_BUS1_BUSY', + 135: 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', + 136: 'SQ_PERF_SEL_USER0', + 137: 'SQ_PERF_SEL_USER1', + 138: 'SQ_PERF_SEL_USER2', + 139: 'SQ_PERF_SEL_USER3', + 140: 'SQ_PERF_SEL_USER4', + 141: 'SQ_PERF_SEL_USER5', + 142: 'SQ_PERF_SEL_USER6', + 143: 'SQ_PERF_SEL_USER7', + 144: 'SQ_PERF_SEL_USER8', + 145: 'SQ_PERF_SEL_USER9', + 146: 'SQ_PERF_SEL_USER10', + 147: 'SQ_PERF_SEL_USER11', + 148: 'SQ_PERF_SEL_USER12', + 149: 'SQ_PERF_SEL_USER13', + 150: 'SQ_PERF_SEL_USER14', + 151: 'SQ_PERF_SEL_USER15', + 152: 'SQ_PERF_SEL_USER_LEVEL0', + 153: 'SQ_PERF_SEL_USER_LEVEL1', + 154: 'SQ_PERF_SEL_USER_LEVEL2', + 155: 'SQ_PERF_SEL_USER_LEVEL3', + 156: 'SQ_PERF_SEL_USER_LEVEL4', + 157: 'SQ_PERF_SEL_USER_LEVEL5', + 158: 'SQ_PERF_SEL_USER_LEVEL6', + 159: 'SQ_PERF_SEL_USER_LEVEL7', + 160: 'SQ_PERF_SEL_USER_LEVEL8', + 161: 'SQ_PERF_SEL_USER_LEVEL9', + 162: 'SQ_PERF_SEL_USER_LEVEL10', + 163: 'SQ_PERF_SEL_USER_LEVEL11', + 164: 'SQ_PERF_SEL_USER_LEVEL12', + 165: 'SQ_PERF_SEL_USER_LEVEL13', + 166: 'SQ_PERF_SEL_USER_LEVEL14', + 167: 'SQ_PERF_SEL_USER_LEVEL15', + 168: 'SQ_PERF_SEL_VALU_RETURN_SDST', + 169: 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', + 170: 'SQ_PERF_SEL_INSTS_VALU_TRANS', + 171: 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', + 172: 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', + 173: 'SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD', + 174: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', + 175: 'SQ_PERF_SEL_INSTS_VALU_VINTERP', + 176: 'SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP', + 177: 'SQ_PERF_SEL_OVERFLOW_PREV', + 178: 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', + 179: 'SQ_PERF_SEL_INSTS_VALU_1_PASS', + 180: 'SQ_PERF_SEL_INSTS_VALU_2_PASS', + 181: 'SQ_PERF_SEL_INSTS_VALU_4_PASS', + 182: 'SQ_PERF_SEL_INSTS_VALU_DP', + 183: 'SQ_PERF_SEL_SP_CONST_CYCLES', + 184: 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', + 185: 'SQ_PERF_SEL_ITEMS_VALU', + 186: 'SQ_PERF_SEL_ITEMS_MAX_VALU', + 187: 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', + 188: 'SQ_PERF_SEL_DUMMY_END', + 255: 'SQ_PERF_SEL_DUMMY_LAST', + 256: 'SQC_PERF_SEL_LDS_BANK_CONFLICT', + 257: 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', + 258: 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', + 259: 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', + 260: 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', + 261: 'SQC_PERF_SEL_LDS_IDX_ACTIVE', + 262: 'SQC_PERF_SEL_LDS_ADDR_STALL', + 263: 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', + 264: 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', + 265: 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', + 266: 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', + 267: 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', + 268: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 269: 'SQC_PERF_SEL_ICACHE_REQ', + 270: 'SQC_PERF_SEL_ICACHE_HITS', + 271: 'SQC_PERF_SEL_ICACHE_MISSES', + 272: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', + 273: 'SQC_PERF_SEL_ICACHE_INVAL_INST', + 274: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 275: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 276: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 277: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', + 278: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 279: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 280: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 281: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 282: 'SQC_PERF_SEL_TC_REQ', + 283: 'SQC_PERF_SEL_TC_INST_REQ', + 284: 'SQC_PERF_SEL_TC_DATA_READ_REQ', + 285: 'SQC_PERF_SEL_TC_STALL', + 286: 'SQC_PERF_SEL_TC_STARVE', + 287: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 288: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 289: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 290: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 291: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 292: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 293: 'SQC_PERF_SEL_DCACHE_REQ', + 294: 'SQC_PERF_SEL_DCACHE_HITS', + 295: 'SQC_PERF_SEL_DCACHE_MISSES', + 296: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', + 297: 'SQC_PERF_SEL_DCACHE_INVAL_INST', + 298: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 299: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 300: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 301: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 302: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 303: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 304: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 305: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 306: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 307: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 308: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 309: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', + 310: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 311: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 312: 'SQC_PERF_SEL_SQ_DCACHE_REQS', + 313: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', + 314: 'SQC_PERF_SEL_TD_VGPR_BUSY', + 315: 'SQC_PERF_SEL_LDS_VGPR_BUSY', + 316: 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', + 317: 'SQC_PERF_SEL_ICACHE_GCR', + 318: 'SQC_PERF_SEL_ICACHE_GCR_HITS', + 319: 'SQC_PERF_SEL_DCACHE_GCR', + 320: 'SQC_PERF_SEL_DCACHE_GCR_HITS', + 321: 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', + 322: 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', + 323: 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', + 324: 'SQC_PERF_SEL_DUMMY_LAST', + 448: 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', + 449: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', + 450: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', + 451: 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', + 452: 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', + 453: 'SP_PERF_SEL_SRC_CACHE_HIT_B0', + 454: 'SP_PERF_SEL_SRC_CACHE_HIT_B1', + 455: 'SP_PERF_SEL_SRC_CACHE_HIT_B2', + 456: 'SP_PERF_SEL_SRC_CACHE_HIT_B3', + 457: 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', + 458: 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', + 459: 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', + 460: 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', + 461: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', + 462: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', + 463: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', + 464: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', + 465: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', + 466: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', + 467: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', + 468: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', + 469: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', + 470: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', + 471: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', + 472: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', + 473: 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', + 474: 'SP_PERF_SEL_VALU_OPERAND', + 475: 'SP_PERF_SEL_VALU_VGPR_OPERAND', + 476: 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', + 477: 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', + 478: 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', + 479: 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', + 480: 'SP_PERF_SEL_VALU_STALL', + 481: 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', + 482: 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', + 483: 'SP_PERF_SEL_VALU_STALL_VDST_FWD', + 484: 'SP_PERF_SEL_VALU_STALL_SDST_FWD', + 485: 'SP_PERF_SEL_VALU_STALL_DST_STALL', + 486: 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', + 487: 'SP_PERF_SEL_VGPR_VMEM_RD', + 488: 'SP_PERF_SEL_VGPR_EXP_RD', + 489: 'SP_PERF_SEL_VGPR_SPI_WR', + 490: 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', + 491: 'SP_PERF_SEL_VGPR_WR', + 492: 'SP_PERF_SEL_VGPR_RD', + 493: 'SP_PERF_SEL_DUMMY_LAST', + 511: 'SQ_PERF_SEL_NONE2', +} +SQ_PERF_SEL_NONE = 0 +SQ_PERF_SEL_ACCUM_PREV = 1 +SQ_PERF_SEL_CYCLES = 2 +SQ_PERF_SEL_BUSY_CYCLES = 3 +SQ_PERF_SEL_WAVES = 4 +SQ_PERF_SEL_WAVES_32 = 5 +SQ_PERF_SEL_WAVES_64 = 6 +SQ_PERF_SEL_LEVEL_WAVES = 7 +SQ_PERF_SEL_ITEMS = 8 +SQ_PERF_SEL_WAVE32_ITEMS = 9 +SQ_PERF_SEL_WAVE64_ITEMS = 10 +SQ_PERF_SEL_PS_QUADS = 11 +SQ_PERF_SEL_EVENTS = 12 +SQ_PERF_SEL_WAVES_EQ_32 = 13 +SQ_PERF_SEL_WAVES_EQ_64 = 14 +SQ_PERF_SEL_WAVES_LT_64 = 15 +SQ_PERF_SEL_WAVES_LT_48 = 16 +SQ_PERF_SEL_WAVES_LT_32 = 17 +SQ_PERF_SEL_WAVES_LT_16 = 18 +SQ_PERF_SEL_WAVES_RESTORED = 19 +SQ_PERF_SEL_WAVES_SAVED = 20 +SQ_PERF_SEL_MSG = 21 +SQ_PERF_SEL_MSG_INTERRUPT = 22 +SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 23 +SQ_PERF_SEL_WAVE_CYCLES = 24 +SQ_PERF_SEL_WAVE_READY = 25 +SQ_PERF_SEL_WAIT_INST_ANY = 26 +SQ_PERF_SEL_WAIT_INST_VALU = 27 +SQ_PERF_SEL_WAIT_INST_SCA = 28 +SQ_PERF_SEL_WAIT_INST_LDS = 29 +SQ_PERF_SEL_WAIT_INST_TEX = 30 +SQ_PERF_SEL_WAIT_INST_FLAT = 31 +SQ_PERF_SEL_WAIT_INST_VMEM = 32 +SQ_PERF_SEL_WAIT_INST_EXP_GDS = 33 +SQ_PERF_SEL_WAIT_INST_BR_MSG = 34 +SQ_PERF_SEL_WAIT_ANY = 35 +SQ_PERF_SEL_WAIT_CNT_ANY = 36 +SQ_PERF_SEL_WAIT_CNT_VMVS = 37 +SQ_PERF_SEL_WAIT_CNT_LGKM = 38 +SQ_PERF_SEL_WAIT_CNT_EXP = 39 +SQ_PERF_SEL_WAIT_TTRACE = 40 +SQ_PERF_SEL_WAIT_IFETCH = 41 +SQ_PERF_SEL_WAIT_BARRIER = 42 +SQ_PERF_SEL_WAIT_EXP_ALLOC = 43 +SQ_PERF_SEL_WAIT_SLEEP = 44 +SQ_PERF_SEL_WAIT_DELAY_ALU = 45 +SQ_PERF_SEL_WAIT_DEPCTR = 46 +SQ_PERF_SEL_WAIT_OTHER = 47 +SQ_PERF_SEL_INSTS_ALL = 48 +SQ_PERF_SEL_INSTS_BRANCH = 49 +SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 50 +SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 51 +SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 52 +SQ_PERF_SEL_INSTS_EXP_GDS = 53 +SQ_PERF_SEL_INSTS_GDS = 54 +SQ_PERF_SEL_INSTS_EXP = 55 +SQ_PERF_SEL_INSTS_FLAT = 56 +SQ_PERF_SEL_INSTS_LDS = 57 +SQ_PERF_SEL_INSTS_SALU = 58 +SQ_PERF_SEL_INSTS_SMEM = 59 +SQ_PERF_SEL_INSTS_SMEM_NORM = 60 +SQ_PERF_SEL_INSTS_SENDMSG = 61 +SQ_PERF_SEL_INSTS_VALU = 62 +SQ_PERF_SEL_INSTS_VALU_TRANS32 = 63 +SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 64 +SQ_PERF_SEL_INSTS_TEX = 65 +SQ_PERF_SEL_INSTS_TEX_LOAD = 66 +SQ_PERF_SEL_INSTS_TEX_STORE = 67 +SQ_PERF_SEL_INSTS_DELAY_ALU = 68 +SQ_PERF_SEL_INSTS_INTERNAL = 69 +SQ_PERF_SEL_INSTS_WAVE32 = 70 +SQ_PERF_SEL_INSTS_WAVE32_FLAT = 71 +SQ_PERF_SEL_INSTS_WAVE32_LDS = 72 +SQ_PERF_SEL_INSTS_WAVE32_VALU = 73 +SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS = 74 +SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 75 +SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 76 +SQ_PERF_SEL_INSTS_WAVE32_TEX = 77 +SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 78 +SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 79 +SQ_PERF_SEL_ITEM_CYCLES_VALU = 80 +SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 81 +SQ_PERF_SEL_WAVE32_INSTS = 82 +SQ_PERF_SEL_WAVE64_INSTS = 83 +SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 84 +SQ_PERF_SEL_WAVE64_HALF_SKIP = 85 +SQ_PERF_SEL_INST_LEVEL_EXP = 86 +SQ_PERF_SEL_INST_LEVEL_GDS = 87 +SQ_PERF_SEL_INST_LEVEL_LDS = 88 +SQ_PERF_SEL_INST_LEVEL_SMEM = 89 +SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 90 +SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 91 +SQ_PERF_SEL_IFETCH_REQS = 92 +SQ_PERF_SEL_IFETCH_LEVEL = 93 +SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 94 +SQ_PERF_SEL_VALU_SGATHER_STALL = 95 +SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 96 +SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 97 +SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 98 +SQ_PERF_SEL_SALU_SGATHER_STALL = 99 +SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 100 +SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 101 +SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 102 +SQ_PERF_SEL_INST_CYCLES_VALU = 103 +SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 104 +SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 105 +SQ_PERF_SEL_INST_CYCLES_VMEM = 106 +SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 107 +SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 108 +SQ_PERF_SEL_INST_CYCLES_LDS = 109 +SQ_PERF_SEL_INST_CYCLES_TEX = 110 +SQ_PERF_SEL_INST_CYCLES_FLAT = 111 +SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 112 +SQ_PERF_SEL_INST_CYCLES_EXP = 113 +SQ_PERF_SEL_INST_CYCLES_GDS = 114 +SQ_PERF_SEL_VALU_STARVE = 115 +SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 116 +SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 117 +SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 118 +SQ_PERF_SEL_VMEM_BUS_ACTIVE = 119 +SQ_PERF_SEL_VMEM_BUS_STALL = 120 +SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 121 +SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 122 +SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 123 +SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 124 +SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 125 +SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 126 +SQ_PERF_SEL_SALU_PIPE_STALL = 127 +SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 128 +SQ_PERF_SEL_MSG_BUS_BUSY = 129 +SQ_PERF_SEL_EXP_REQ_BUS_STALL = 130 +SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 131 +SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 132 +SQ_PERF_SEL_EXP_BUS0_BUSY = 133 +SQ_PERF_SEL_EXP_BUS1_BUSY = 134 +SQ_PERF_SEL_INST_CACHE_REQ_STALL = 135 +SQ_PERF_SEL_USER0 = 136 +SQ_PERF_SEL_USER1 = 137 +SQ_PERF_SEL_USER2 = 138 +SQ_PERF_SEL_USER3 = 139 +SQ_PERF_SEL_USER4 = 140 +SQ_PERF_SEL_USER5 = 141 +SQ_PERF_SEL_USER6 = 142 +SQ_PERF_SEL_USER7 = 143 +SQ_PERF_SEL_USER8 = 144 +SQ_PERF_SEL_USER9 = 145 +SQ_PERF_SEL_USER10 = 146 +SQ_PERF_SEL_USER11 = 147 +SQ_PERF_SEL_USER12 = 148 +SQ_PERF_SEL_USER13 = 149 +SQ_PERF_SEL_USER14 = 150 +SQ_PERF_SEL_USER15 = 151 +SQ_PERF_SEL_USER_LEVEL0 = 152 +SQ_PERF_SEL_USER_LEVEL1 = 153 +SQ_PERF_SEL_USER_LEVEL2 = 154 +SQ_PERF_SEL_USER_LEVEL3 = 155 +SQ_PERF_SEL_USER_LEVEL4 = 156 +SQ_PERF_SEL_USER_LEVEL5 = 157 +SQ_PERF_SEL_USER_LEVEL6 = 158 +SQ_PERF_SEL_USER_LEVEL7 = 159 +SQ_PERF_SEL_USER_LEVEL8 = 160 +SQ_PERF_SEL_USER_LEVEL9 = 161 +SQ_PERF_SEL_USER_LEVEL10 = 162 +SQ_PERF_SEL_USER_LEVEL11 = 163 +SQ_PERF_SEL_USER_LEVEL12 = 164 +SQ_PERF_SEL_USER_LEVEL13 = 165 +SQ_PERF_SEL_USER_LEVEL14 = 166 +SQ_PERF_SEL_USER_LEVEL15 = 167 +SQ_PERF_SEL_VALU_RETURN_SDST = 168 +SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 169 +SQ_PERF_SEL_INSTS_VALU_TRANS = 170 +SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 171 +SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 172 +SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD = 173 +SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 174 +SQ_PERF_SEL_INSTS_VALU_VINTERP = 175 +SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP = 176 +SQ_PERF_SEL_OVERFLOW_PREV = 177 +SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 178 +SQ_PERF_SEL_INSTS_VALU_1_PASS = 179 +SQ_PERF_SEL_INSTS_VALU_2_PASS = 180 +SQ_PERF_SEL_INSTS_VALU_4_PASS = 181 +SQ_PERF_SEL_INSTS_VALU_DP = 182 +SQ_PERF_SEL_SP_CONST_CYCLES = 183 +SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 184 +SQ_PERF_SEL_ITEMS_VALU = 185 +SQ_PERF_SEL_ITEMS_MAX_VALU = 186 +SQ_PERF_SEL_ITEM_CYCLES_VMEM = 187 +SQ_PERF_SEL_DUMMY_END = 188 +SQ_PERF_SEL_DUMMY_LAST = 255 +SQC_PERF_SEL_LDS_BANK_CONFLICT = 256 +SQC_PERF_SEL_LDS_ADDR_CONFLICT = 257 +SQC_PERF_SEL_LDS_UNALIGNED_STALL = 258 +SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 259 +SQC_PERF_SEL_LDS_ATOMIC_RETURN = 260 +SQC_PERF_SEL_LDS_IDX_ACTIVE = 261 +SQC_PERF_SEL_LDS_ADDR_STALL = 262 +SQC_PERF_SEL_LDS_ADDR_ACTIVE = 263 +SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 264 +SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 265 +SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 266 +SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 267 +SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 268 +SQC_PERF_SEL_ICACHE_REQ = 269 +SQC_PERF_SEL_ICACHE_HITS = 270 +SQC_PERF_SEL_ICACHE_MISSES = 271 +SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 272 +SQC_PERF_SEL_ICACHE_INVAL_INST = 273 +SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 274 +SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 275 +SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 276 +SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 277 +SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 278 +SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 279 +SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 280 +SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 281 +SQC_PERF_SEL_TC_REQ = 282 +SQC_PERF_SEL_TC_INST_REQ = 283 +SQC_PERF_SEL_TC_DATA_READ_REQ = 284 +SQC_PERF_SEL_TC_STALL = 285 +SQC_PERF_SEL_TC_STARVE = 286 +SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 287 +SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 288 +SQC_PERF_SEL_ICACHE_CACHE_STALLED = 289 +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 290 +SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 291 +SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 292 +SQC_PERF_SEL_DCACHE_REQ = 293 +SQC_PERF_SEL_DCACHE_HITS = 294 +SQC_PERF_SEL_DCACHE_MISSES = 295 +SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 296 +SQC_PERF_SEL_DCACHE_INVAL_INST = 297 +SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 298 +SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 299 +SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 300 +SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 301 +SQC_PERF_SEL_DCACHE_CACHE_STALLED = 302 +SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 303 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 304 +SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 305 +SQC_PERF_SEL_DCACHE_REQ_READ_1 = 306 +SQC_PERF_SEL_DCACHE_REQ_READ_2 = 307 +SQC_PERF_SEL_DCACHE_REQ_READ_4 = 308 +SQC_PERF_SEL_DCACHE_REQ_READ_8 = 309 +SQC_PERF_SEL_DCACHE_REQ_READ_16 = 310 +SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 311 +SQC_PERF_SEL_SQ_DCACHE_REQS = 312 +SQC_PERF_SEL_DCACHE_FLAT_REQ = 313 +SQC_PERF_SEL_TD_VGPR_BUSY = 314 +SQC_PERF_SEL_LDS_VGPR_BUSY = 315 +SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 316 +SQC_PERF_SEL_ICACHE_GCR = 317 +SQC_PERF_SEL_ICACHE_GCR_HITS = 318 +SQC_PERF_SEL_DCACHE_GCR = 319 +SQC_PERF_SEL_DCACHE_GCR_HITS = 320 +SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 321 +SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 322 +SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 323 +SQC_PERF_SEL_DUMMY_LAST = 324 +SP_PERF_SEL_DST_BUF_ALLOC_STALL = 448 +SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 449 +SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 450 +SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 451 +SP_PERF_SEL_DST_BUF_ODD_DIRTY = 452 +SP_PERF_SEL_SRC_CACHE_HIT_B0 = 453 +SP_PERF_SEL_SRC_CACHE_HIT_B1 = 454 +SP_PERF_SEL_SRC_CACHE_HIT_B2 = 455 +SP_PERF_SEL_SRC_CACHE_HIT_B3 = 456 +SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 457 +SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 458 +SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 459 +SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 460 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 461 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 462 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 463 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 464 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 465 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 466 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 467 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 468 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 469 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 470 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 471 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 472 +SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 473 +SP_PERF_SEL_VALU_OPERAND = 474 +SP_PERF_SEL_VALU_VGPR_OPERAND = 475 +SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 476 +SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 477 +SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 478 +SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 479 +SP_PERF_SEL_VALU_STALL = 480 +SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 481 +SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 482 +SP_PERF_SEL_VALU_STALL_VDST_FWD = 483 +SP_PERF_SEL_VALU_STALL_SDST_FWD = 484 +SP_PERF_SEL_VALU_STALL_DST_STALL = 485 +SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 486 +SP_PERF_SEL_VGPR_VMEM_RD = 487 +SP_PERF_SEL_VGPR_EXP_RD = 488 +SP_PERF_SEL_VGPR_SPI_WR = 489 +SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 490 +SP_PERF_SEL_VGPR_WR = 491 +SP_PERF_SEL_VGPR_RD = 492 +SP_PERF_SEL_DUMMY_LAST = 493 +SQ_PERF_SEL_NONE2 = 511 +SQ_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_ROUND_MODE' +SQ_ROUND_MODE__enumvalues = { + 0: 'SQ_ROUND_NEAREST_EVEN', + 1: 'SQ_ROUND_PLUS_INFINITY', + 2: 'SQ_ROUND_MINUS_INFINITY', + 3: 'SQ_ROUND_TO_ZERO', +} +SQ_ROUND_NEAREST_EVEN = 0 +SQ_ROUND_PLUS_INFINITY = 1 +SQ_ROUND_MINUS_INFINITY = 2 +SQ_ROUND_TO_ZERO = 3 +SQ_ROUND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_BUF_TYPE' +SQ_RSRC_BUF_TYPE__enumvalues = { + 0: 'SQ_RSRC_BUF', + 1: 'SQ_RSRC_BUF_RSVD_1', + 2: 'SQ_RSRC_BUF_RSVD_2', + 3: 'SQ_RSRC_BUF_RSVD_3', +} +SQ_RSRC_BUF = 0 +SQ_RSRC_BUF_RSVD_1 = 1 +SQ_RSRC_BUF_RSVD_2 = 2 +SQ_RSRC_BUF_RSVD_3 = 3 +SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_FLAT_TYPE' +SQ_RSRC_FLAT_TYPE__enumvalues = { + 0: 'SQ_RSRC_FLAT_RSVD_0', + 1: 'SQ_RSRC_FLAT', + 2: 'SQ_RSRC_FLAT_RSVD_2', + 3: 'SQ_RSRC_FLAT_RSVD_3', +} +SQ_RSRC_FLAT_RSVD_0 = 0 +SQ_RSRC_FLAT = 1 +SQ_RSRC_FLAT_RSVD_2 = 2 +SQ_RSRC_FLAT_RSVD_3 = 3 +SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_IMG_TYPE' +SQ_RSRC_IMG_TYPE__enumvalues = { + 0: 'SQ_RSRC_IMG_RSVD_0', + 1: 'SQ_RSRC_IMG_RSVD_1', + 2: 'SQ_RSRC_IMG_RSVD_2', + 3: 'SQ_RSRC_IMG_RSVD_3', + 4: 'SQ_RSRC_IMG_RSVD_4', + 5: 'SQ_RSRC_IMG_RSVD_5', + 6: 'SQ_RSRC_IMG_RSVD_6', + 7: 'SQ_RSRC_IMG_RSVD_7', + 8: 'SQ_RSRC_IMG_1D', + 9: 'SQ_RSRC_IMG_2D', + 10: 'SQ_RSRC_IMG_3D', + 11: 'SQ_RSRC_IMG_CUBE', + 12: 'SQ_RSRC_IMG_1D_ARRAY', + 13: 'SQ_RSRC_IMG_2D_ARRAY', + 14: 'SQ_RSRC_IMG_2D_MSAA', + 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', +} +SQ_RSRC_IMG_RSVD_0 = 0 +SQ_RSRC_IMG_RSVD_1 = 1 +SQ_RSRC_IMG_RSVD_2 = 2 +SQ_RSRC_IMG_RSVD_3 = 3 +SQ_RSRC_IMG_RSVD_4 = 4 +SQ_RSRC_IMG_RSVD_5 = 5 +SQ_RSRC_IMG_RSVD_6 = 6 +SQ_RSRC_IMG_RSVD_7 = 7 +SQ_RSRC_IMG_1D = 8 +SQ_RSRC_IMG_2D = 9 +SQ_RSRC_IMG_3D = 10 +SQ_RSRC_IMG_CUBE = 11 +SQ_RSRC_IMG_1D_ARRAY = 12 +SQ_RSRC_IMG_2D_ARRAY = 13 +SQ_RSRC_IMG_2D_MSAA = 14 +SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 +SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_SEL_XYZW01' +SQ_SEL_XYZW01__enumvalues = { + 0: 'SQ_SEL_0', + 1: 'SQ_SEL_1', + 2: 'SQ_SEL_N_BC_1', + 3: 'SQ_SEL_RESERVED_1', + 4: 'SQ_SEL_X', + 5: 'SQ_SEL_Y', + 6: 'SQ_SEL_Z', + 7: 'SQ_SEL_W', +} +SQ_SEL_0 = 0 +SQ_SEL_1 = 1 +SQ_SEL_N_BC_1 = 2 +SQ_SEL_RESERVED_1 = 3 +SQ_SEL_X = 4 +SQ_SEL_Y = 5 +SQ_SEL_Z = 6 +SQ_SEL_W = 7 +SQ_SEL_XYZW01 = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_ANISO_RATIO' +SQ_TEX_ANISO_RATIO__enumvalues = { + 0: 'SQ_TEX_ANISO_RATIO_1', + 1: 'SQ_TEX_ANISO_RATIO_2', + 2: 'SQ_TEX_ANISO_RATIO_4', + 3: 'SQ_TEX_ANISO_RATIO_8', + 4: 'SQ_TEX_ANISO_RATIO_16', +} +SQ_TEX_ANISO_RATIO_1 = 0 +SQ_TEX_ANISO_RATIO_2 = 1 +SQ_TEX_ANISO_RATIO_4 = 2 +SQ_TEX_ANISO_RATIO_8 = 3 +SQ_TEX_ANISO_RATIO_16 = 4 +SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_BORDER_COLOR' +SQ_TEX_BORDER_COLOR__enumvalues = { + 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 3: 'SQ_TEX_BORDER_COLOR_REGISTER', +} +SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 +SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 +SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 +SQ_TEX_BORDER_COLOR_REGISTER = 3 +SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_CLAMP' +SQ_TEX_CLAMP__enumvalues = { + 0: 'SQ_TEX_WRAP', + 1: 'SQ_TEX_MIRROR', + 2: 'SQ_TEX_CLAMP_LAST_TEXEL', + 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 4: 'SQ_TEX_CLAMP_HALF_BORDER', + 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', + 6: 'SQ_TEX_CLAMP_BORDER', + 7: 'SQ_TEX_MIRROR_ONCE_BORDER', +} +SQ_TEX_WRAP = 0 +SQ_TEX_MIRROR = 1 +SQ_TEX_CLAMP_LAST_TEXEL = 2 +SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 +SQ_TEX_CLAMP_HALF_BORDER = 4 +SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 +SQ_TEX_CLAMP_BORDER = 6 +SQ_TEX_MIRROR_ONCE_BORDER = 7 +SQ_TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_DEPTH_COMPARE' +SQ_TEX_DEPTH_COMPARE__enumvalues = { + 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', + 1: 'SQ_TEX_DEPTH_COMPARE_LESS', + 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', + 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', + 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', + 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', + 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', +} +SQ_TEX_DEPTH_COMPARE_NEVER = 0 +SQ_TEX_DEPTH_COMPARE_LESS = 1 +SQ_TEX_DEPTH_COMPARE_EQUAL = 2 +SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 +SQ_TEX_DEPTH_COMPARE_GREATER = 4 +SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 +SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 +SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 +SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_MIP_FILTER' +SQ_TEX_MIP_FILTER__enumvalues = { + 0: 'SQ_TEX_MIP_FILTER_NONE', + 1: 'SQ_TEX_MIP_FILTER_POINT', + 2: 'SQ_TEX_MIP_FILTER_LINEAR', + 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', +} +SQ_TEX_MIP_FILTER_NONE = 0 +SQ_TEX_MIP_FILTER_POINT = 1 +SQ_TEX_MIP_FILTER_LINEAR = 2 +SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 +SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_XY_FILTER' +SQ_TEX_XY_FILTER__enumvalues = { + 0: 'SQ_TEX_XY_FILTER_POINT', + 1: 'SQ_TEX_XY_FILTER_BILINEAR', + 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', + 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', +} +SQ_TEX_XY_FILTER_POINT = 0 +SQ_TEX_XY_FILTER_BILINEAR = 1 +SQ_TEX_XY_FILTER_ANISO_POINT = 2 +SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 +SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_Z_FILTER' +SQ_TEX_Z_FILTER__enumvalues = { + 0: 'SQ_TEX_Z_FILTER_NONE', + 1: 'SQ_TEX_Z_FILTER_POINT', + 2: 'SQ_TEX_Z_FILTER_LINEAR', +} +SQ_TEX_Z_FILTER_NONE = 0 +SQ_TEX_Z_FILTER_POINT = 1 +SQ_TEX_Z_FILTER_LINEAR = 2 +SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_MODE' +SQ_TT_MODE__enumvalues = { + 0: 'SQ_TT_MODE_OFF', + 1: 'SQ_TT_MODE_ON', + 2: 'SQ_TT_MODE_GLOBAL', + 3: 'SQ_TT_MODE_DETAIL', +} +SQ_TT_MODE_OFF = 0 +SQ_TT_MODE_ON = 1 +SQ_TT_MODE_GLOBAL = 2 +SQ_TT_MODE_DETAIL = 3 +SQ_TT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_RT_FREQ' +SQ_TT_RT_FREQ__enumvalues = { + 0: 'SQ_TT_RT_FREQ_NEVER', + 1: 'SQ_TT_RT_FREQ_1024_CLK', + 2: 'SQ_TT_RT_FREQ_4096_CLK', +} +SQ_TT_RT_FREQ_NEVER = 0 +SQ_TT_RT_FREQ_1024_CLK = 1 +SQ_TT_RT_FREQ_4096_CLK = 2 +SQ_TT_RT_FREQ = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE' +SQ_TT_TOKEN_MASK_INST_EXCLUDE__enumvalues = { + 1: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT', + 2: 'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT', +} +SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT = 1 +SQ_TT_INST_EXCLUDE_EXPGNT234_BIT = 2 +SQ_TT_TOKEN_MASK_INST_EXCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT', + 1: 'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT', +} +SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT = 0 +SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT = 1 +SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_EXCLUDE' +SQ_TT_TOKEN_MASK_REG_EXCLUDE__enumvalues = { + 1: 'SQ_TT_REG_EXCLUDE_USER_DATA_BIT', + 2: 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT', + 4: 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT', +} +SQ_TT_REG_EXCLUDE_USER_DATA_BIT = 1 +SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT = 2 +SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT = 4 +SQ_TT_TOKEN_MASK_REG_EXCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT', + 1: 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT', + 2: 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT', +} +SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT = 0 +SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT = 1 +SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT = 2 +SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE' +SQ_TT_TOKEN_MASK_REG_INCLUDE__enumvalues = { + 1: 'SQ_TT_TOKEN_MASK_SQDEC_BIT', + 2: 'SQ_TT_TOKEN_MASK_SHDEC_BIT', + 4: 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', + 8: 'SQ_TT_TOKEN_MASK_COMP_BIT', + 16: 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', + 32: 'SQ_TT_TOKEN_MASK_CONFIG_BIT', + 64: 'SQ_TT_TOKEN_MASK_ALL_BIT', + 128: 'SQ_TT_TOKEN_MASK_RSVD_BIT', +} +SQ_TT_TOKEN_MASK_SQDEC_BIT = 1 +SQ_TT_TOKEN_MASK_SHDEC_BIT = 2 +SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 4 +SQ_TT_TOKEN_MASK_COMP_BIT = 8 +SQ_TT_TOKEN_MASK_CONTEXT_BIT = 16 +SQ_TT_TOKEN_MASK_CONFIG_BIT = 32 +SQ_TT_TOKEN_MASK_ALL_BIT = 64 +SQ_TT_TOKEN_MASK_RSVD_BIT = 128 +SQ_TT_TOKEN_MASK_REG_INCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', + 1: 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', + 2: 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', + 3: 'SQ_TT_TOKEN_MASK_COMP_SHIFT', + 4: 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', + 5: 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', + 6: 'SQ_TT_TOKEN_MASK_ALL_SHIFT', + 7: 'SQ_TT_TOKEN_MASK_RSVD_SHIFT', +} +SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0 +SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 1 +SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 2 +SQ_TT_TOKEN_MASK_COMP_SHIFT = 3 +SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 4 +SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 5 +SQ_TT_TOKEN_MASK_ALL_SHIFT = 6 +SQ_TT_TOKEN_MASK_RSVD_SHIFT = 7 +SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', + 1: 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', + 2: 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', + 3: 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', + 4: 'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT', + 5: 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', + 6: 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', + 7: 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', + 8: 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', + 9: 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', + 10: 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', + 11: 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', +} +SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0 +SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 1 +SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 2 +SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 3 +SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT = 4 +SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 5 +SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 6 +SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 7 +SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 8 +SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 9 +SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 10 +SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 11 +SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_UTIL_TIMER' +SQ_TT_UTIL_TIMER__enumvalues = { + 0: 'SQ_TT_UTIL_TIMER_100_CLK', + 1: 'SQ_TT_UTIL_TIMER_250_CLK', +} +SQ_TT_UTIL_TIMER_100_CLK = 0 +SQ_TT_UTIL_TIMER_250_CLK = 1 +SQ_TT_UTIL_TIMER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_WAVESTART_MODE' +SQ_TT_WAVESTART_MODE__enumvalues = { + 0: 'SQ_TT_WAVESTART_MODE_SHORT', + 1: 'SQ_TT_WAVESTART_MODE_ALLOC', + 2: 'SQ_TT_WAVESTART_MODE_PBB_ID', +} +SQ_TT_WAVESTART_MODE_SHORT = 0 +SQ_TT_WAVESTART_MODE_ALLOC = 1 +SQ_TT_WAVESTART_MODE_PBB_ID = 2 +SQ_TT_WAVESTART_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_WTYPE_INCLUDE' +SQ_TT_WTYPE_INCLUDE__enumvalues = { + 1: 'SQ_TT_WTYPE_INCLUDE_PS_BIT', + 2: 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT', + 4: 'SQ_TT_WTYPE_INCLUDE_GS_BIT', + 8: 'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT', + 16: 'SQ_TT_WTYPE_INCLUDE_HS_BIT', + 32: 'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT', + 64: 'SQ_TT_WTYPE_INCLUDE_CS_BIT', +} +SQ_TT_WTYPE_INCLUDE_PS_BIT = 1 +SQ_TT_WTYPE_INCLUDE_RSVD0_BIT = 2 +SQ_TT_WTYPE_INCLUDE_GS_BIT = 4 +SQ_TT_WTYPE_INCLUDE_RSVD1_BIT = 8 +SQ_TT_WTYPE_INCLUDE_HS_BIT = 16 +SQ_TT_WTYPE_INCLUDE_RSVD2_BIT = 32 +SQ_TT_WTYPE_INCLUDE_CS_BIT = 64 +SQ_TT_WTYPE_INCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_WTYPE_INCLUDE_SHIFT' +SQ_TT_WTYPE_INCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', + 1: 'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT', + 2: 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', + 3: 'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT', + 4: 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', + 5: 'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT', + 6: 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', +} +SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0 +SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT = 1 +SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 2 +SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT = 3 +SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 4 +SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT = 5 +SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 6 +SQ_TT_WTYPE_INCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WATCH_MODES' +SQ_WATCH_MODES__enumvalues = { + 0: 'SQ_WATCH_MODE_READ', + 1: 'SQ_WATCH_MODE_NONREAD', + 2: 'SQ_WATCH_MODE_ATOMIC', + 3: 'SQ_WATCH_MODE_ALL', +} +SQ_WATCH_MODE_READ = 0 +SQ_WATCH_MODE_NONREAD = 1 +SQ_WATCH_MODE_ATOMIC = 2 +SQ_WATCH_MODE_ALL = 3 +SQ_WATCH_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_FWD_PROG_INTERVAL' +SQ_WAVE_FWD_PROG_INTERVAL__enumvalues = { + 0: 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', + 1: 'SQ_WAVE_FWD_PROG_INTERVAL_256', + 2: 'SQ_WAVE_FWD_PROG_INTERVAL_1024', + 3: 'SQ_WAVE_FWD_PROG_INTERVAL_4096', +} +SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0 +SQ_WAVE_FWD_PROG_INTERVAL_256 = 1 +SQ_WAVE_FWD_PROG_INTERVAL_1024 = 2 +SQ_WAVE_FWD_PROG_INTERVAL_4096 = 3 +SQ_WAVE_FWD_PROG_INTERVAL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_IB_ECC_ST' +SQ_WAVE_IB_ECC_ST__enumvalues = { + 0: 'SQ_WAVE_IB_ECC_CLEAN', + 1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE', + 2: 'SQ_WAVE_IB_ECC_ERR_HALT', + 3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', +} +SQ_WAVE_IB_ECC_CLEAN = 0 +SQ_WAVE_IB_ECC_ERR_CONTINUE = 1 +SQ_WAVE_IB_ECC_ERR_HALT = 2 +SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3 +SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_SCHED_MODES' +SQ_WAVE_SCHED_MODES__enumvalues = { + 0: 'SQ_WAVE_SCHED_MODE_NORMAL', + 1: 'SQ_WAVE_SCHED_MODE_EXPERT', + 2: 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', +} +SQ_WAVE_SCHED_MODE_NORMAL = 0 +SQ_WAVE_SCHED_MODE_EXPERT = 1 +SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 2 +SQ_WAVE_SCHED_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_TYPE' +SQ_WAVE_TYPE__enumvalues = { + 0: 'SQ_WAVE_TYPE_PS', + 1: 'SQ_WAVE_TYPE_RSVD0', + 2: 'SQ_WAVE_TYPE_GS', + 3: 'SQ_WAVE_TYPE_RSVD1', + 4: 'SQ_WAVE_TYPE_HS', + 5: 'SQ_WAVE_TYPE_RSVD2', + 6: 'SQ_WAVE_TYPE_CS', + 7: 'SQ_WAVE_TYPE_PS1', + 8: 'SQ_WAVE_TYPE_PS2', + 9: 'SQ_WAVE_TYPE_PS3', +} +SQ_WAVE_TYPE_PS = 0 +SQ_WAVE_TYPE_RSVD0 = 1 +SQ_WAVE_TYPE_GS = 2 +SQ_WAVE_TYPE_RSVD1 = 3 +SQ_WAVE_TYPE_HS = 4 +SQ_WAVE_TYPE_RSVD2 = 5 +SQ_WAVE_TYPE_CS = 6 +SQ_WAVE_TYPE_PS1 = 7 +SQ_WAVE_TYPE_PS2 = 8 +SQ_WAVE_TYPE_PS3 = 9 +SQ_WAVE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CSCNTL_TYPE' +CSCNTL_TYPE__enumvalues = { + 0: 'CSCNTL_TYPE_TG', + 1: 'CSCNTL_TYPE_STATE', + 2: 'CSCNTL_TYPE_EVENT', + 3: 'CSCNTL_TYPE_PRIVATE', +} +CSCNTL_TYPE_TG = 0 +CSCNTL_TYPE_STATE = 1 +CSCNTL_TYPE_EVENT = 2 +CSCNTL_TYPE_PRIVATE = 3 +CSCNTL_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CSDATA_TYPE' +CSDATA_TYPE__enumvalues = { + 0: 'CSDATA_TYPE_TG', + 1: 'CSDATA_TYPE_STATE', + 2: 'CSDATA_TYPE_EVENT', + 3: 'CSDATA_TYPE_PRIVATE', +} +CSDATA_TYPE_TG = 0 +CSDATA_TYPE_STATE = 1 +CSDATA_TYPE_EVENT = 2 +CSDATA_TYPE_PRIVATE = 3 +CSDATA_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'GE1_PERFCOUNT_SELECT' +GE1_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge1_assembler_busy', + 1: 'ge1_assembler_stalled', + 2: 'ge1_dma_busy', + 3: 'ge1_dma_lat_bin_0', + 4: 'ge1_dma_lat_bin_1', + 5: 'ge1_dma_lat_bin_2', + 6: 'ge1_dma_lat_bin_3', + 7: 'ge1_dma_lat_bin_4', + 8: 'ge1_dma_lat_bin_5', + 9: 'ge1_dma_lat_bin_6', + 10: 'ge1_dma_lat_bin_7', + 11: 'ge1_dma_return_cl0', + 12: 'ge1_dma_return_cl1', + 13: 'ge1_dma_utcl1_consecutive_retry_event', + 14: 'ge1_dma_utcl1_request_event', + 15: 'ge1_dma_utcl1_retry_event', + 16: 'ge1_dma_utcl1_stall_event', + 17: 'ge1_dma_utcl1_stall_utcl2_event', + 18: 'ge1_dma_utcl1_translation_hit_event', + 19: 'ge1_dma_utcl1_translation_miss_event', + 20: 'ge1_assembler_dma_starved', + 21: 'ge1_rbiu_di_fifo_stalled_p0', + 22: 'ge1_rbiu_di_fifo_starved_p0', + 23: 'ge1_rbiu_dr_fifo_stalled_p0', + 24: 'ge1_rbiu_dr_fifo_starved_p0', + 25: 'ge1_sclk_reg_vld', + 26: 'ge1_stat_busy', + 27: 'ge1_stat_no_dma_busy', + 28: 'ge1_pipe0_to_pipe1', + 29: 'ge1_pipe1_to_pipe0', + 30: 'ge1_dma_return_size_cl0', + 31: 'ge1_dma_return_size_cl1', + 32: 'ge1_small_draws_one_instance', + 33: 'ge1_sclk_input_vld', + 34: 'ge1_prim_group_limit_hit', + 35: 'ge1_unopt_multi_instance_draws', + 36: 'ge1_rbiu_di_fifo_stalled_p1', + 37: 'ge1_rbiu_di_fifo_starved_p1', + 38: 'ge1_rbiu_dr_fifo_stalled_p1', + 39: 'ge1_rbiu_dr_fifo_starved_p1', +} +ge1_assembler_busy = 0 +ge1_assembler_stalled = 1 +ge1_dma_busy = 2 +ge1_dma_lat_bin_0 = 3 +ge1_dma_lat_bin_1 = 4 +ge1_dma_lat_bin_2 = 5 +ge1_dma_lat_bin_3 = 6 +ge1_dma_lat_bin_4 = 7 +ge1_dma_lat_bin_5 = 8 +ge1_dma_lat_bin_6 = 9 +ge1_dma_lat_bin_7 = 10 +ge1_dma_return_cl0 = 11 +ge1_dma_return_cl1 = 12 +ge1_dma_utcl1_consecutive_retry_event = 13 +ge1_dma_utcl1_request_event = 14 +ge1_dma_utcl1_retry_event = 15 +ge1_dma_utcl1_stall_event = 16 +ge1_dma_utcl1_stall_utcl2_event = 17 +ge1_dma_utcl1_translation_hit_event = 18 +ge1_dma_utcl1_translation_miss_event = 19 +ge1_assembler_dma_starved = 20 +ge1_rbiu_di_fifo_stalled_p0 = 21 +ge1_rbiu_di_fifo_starved_p0 = 22 +ge1_rbiu_dr_fifo_stalled_p0 = 23 +ge1_rbiu_dr_fifo_starved_p0 = 24 +ge1_sclk_reg_vld = 25 +ge1_stat_busy = 26 +ge1_stat_no_dma_busy = 27 +ge1_pipe0_to_pipe1 = 28 +ge1_pipe1_to_pipe0 = 29 +ge1_dma_return_size_cl0 = 30 +ge1_dma_return_size_cl1 = 31 +ge1_small_draws_one_instance = 32 +ge1_sclk_input_vld = 33 +ge1_prim_group_limit_hit = 34 +ge1_unopt_multi_instance_draws = 35 +ge1_rbiu_di_fifo_stalled_p1 = 36 +ge1_rbiu_di_fifo_starved_p1 = 37 +ge1_rbiu_dr_fifo_stalled_p1 = 38 +ge1_rbiu_dr_fifo_starved_p1 = 39 +GE1_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'GE2_DIST_PERFCOUNT_SELECT' +GE2_DIST_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge_dist_hs_done', + 1: 'ge_dist_hs_done_latency_se0', + 2: 'ge_dist_hs_done_latency_se1', + 3: 'ge_dist_hs_done_latency_se2', + 4: 'ge_dist_hs_done_latency_se3', + 5: 'ge_dist_hs_done_latency_se4', + 6: 'ge_dist_hs_done_latency_se5', + 7: 'ge_dist_hs_done_latency_se6', + 8: 'ge_dist_hs_done_latency_se7', + 9: 'ge_dist_inside_tf_bin_0', + 10: 'ge_dist_inside_tf_bin_1', + 11: 'ge_dist_inside_tf_bin_2', + 12: 'ge_dist_inside_tf_bin_3', + 13: 'ge_dist_inside_tf_bin_4', + 14: 'ge_dist_inside_tf_bin_5', + 15: 'ge_dist_inside_tf_bin_6', + 16: 'ge_dist_inside_tf_bin_7', + 17: 'ge_dist_inside_tf_bin_8', + 18: 'ge_dist_null_patch', + 19: 'ge_dist_sclk_core_vld', + 20: 'ge_dist_sclk_wd_te11_vld', + 21: 'ge_dist_tfreq_lat_bin_0', + 22: 'ge_dist_tfreq_lat_bin_1', + 23: 'ge_dist_tfreq_lat_bin_2', + 24: 'ge_dist_tfreq_lat_bin_3', + 25: 'ge_dist_tfreq_lat_bin_4', + 26: 'ge_dist_tfreq_lat_bin_5', + 27: 'ge_dist_tfreq_lat_bin_6', + 28: 'ge_dist_tfreq_lat_bin_7', + 29: 'ge_dist_tfreq_utcl1_consecutive_retry_event', + 30: 'ge_dist_tfreq_utcl1_request_event', + 31: 'ge_dist_tfreq_utcl1_retry_event', + 32: 'ge_dist_tfreq_utcl1_stall_event', + 33: 'ge_dist_tfreq_utcl1_stall_utcl2_event', + 34: 'ge_dist_tfreq_utcl1_translation_hit_event', + 35: 'ge_dist_tfreq_utcl1_translation_miss_event', + 36: 'ge_dist_vs_pc_stall', + 37: 'ge_dist_pc_feorder_fifo_full', + 38: 'ge_dist_pc_ge_manager_busy', + 39: 'ge_dist_pc_req_stall_se0', + 40: 'ge_dist_pc_req_stall_se1', + 41: 'ge_dist_pc_req_stall_se2', + 42: 'ge_dist_pc_req_stall_se3', + 43: 'ge_dist_pc_req_stall_se4', + 44: 'ge_dist_pc_req_stall_se5', + 45: 'ge_dist_pc_req_stall_se6', + 46: 'ge_dist_pc_req_stall_se7', + 47: 'ge_dist_pc_space_zero', + 48: 'ge_dist_sclk_input_vld', + 49: 'ge_dist_reserved', + 50: 'ge_dist_wd_te11_busy', + 51: 'ge_dist_te11_starved', + 52: 'ge_dist_switch_mode_stall', + 53: 'ge_all_tf_eq', + 54: 'ge_all_tf2', + 55: 'ge_all_tf3', + 56: 'ge_all_tf4', + 57: 'ge_all_tf5', + 58: 'ge_all_tf6', + 59: 'ge_se0_te11_starved_on_hs_done', + 60: 'ge_se1_te11_starved_on_hs_done', + 61: 'ge_se2_te11_starved_on_hs_done', + 62: 'ge_se3_te11_starved_on_hs_done', + 63: 'ge_se4_te11_starved_on_hs_done', + 64: 'ge_se5_te11_starved_on_hs_done', + 65: 'ge_se6_te11_starved_on_hs_done', + 66: 'ge_se7_te11_starved_on_hs_done', + 67: 'ge_dist_op_fifo_full_starve', + 68: 'ge_dist_hs_done_se0', + 69: 'ge_dist_hs_done_se1', + 70: 'ge_dist_hs_done_se2', + 71: 'ge_dist_hs_done_se3', + 72: 'ge_dist_hs_done_se4', + 73: 'ge_dist_hs_done_se5', + 74: 'ge_dist_hs_done_se6', + 75: 'ge_dist_hs_done_se7', + 76: 'ge_dist_hs_done_latency', + 77: 'ge_dist_distributer_busy', + 78: 'ge_tf_ret_data_stalling_hs_done', + 79: 'ge_num_of_no_dist_patches', + 80: 'ge_num_of_donut_dist_patches', + 81: 'ge_num_of_patch_dist_patches', + 82: 'ge_num_of_se_switches_due_to_patch_accum', + 83: 'ge_num_of_se_switches_due_to_donut', + 84: 'ge_num_of_se_switches_due_to_trap', + 85: 'ge_num_of_hs_alloc_events', + 86: 'ge_agm_gcr_req', + 87: 'ge_agm_gcr_tag_stall', + 88: 'ge_agm_gcr_crd_stall', + 89: 'ge_agm_gcr_stall', + 90: 'ge_agm_gcr_latency', + 91: 'ge_distclk_vld', +} +ge_dist_hs_done = 0 +ge_dist_hs_done_latency_se0 = 1 +ge_dist_hs_done_latency_se1 = 2 +ge_dist_hs_done_latency_se2 = 3 +ge_dist_hs_done_latency_se3 = 4 +ge_dist_hs_done_latency_se4 = 5 +ge_dist_hs_done_latency_se5 = 6 +ge_dist_hs_done_latency_se6 = 7 +ge_dist_hs_done_latency_se7 = 8 +ge_dist_inside_tf_bin_0 = 9 +ge_dist_inside_tf_bin_1 = 10 +ge_dist_inside_tf_bin_2 = 11 +ge_dist_inside_tf_bin_3 = 12 +ge_dist_inside_tf_bin_4 = 13 +ge_dist_inside_tf_bin_5 = 14 +ge_dist_inside_tf_bin_6 = 15 +ge_dist_inside_tf_bin_7 = 16 +ge_dist_inside_tf_bin_8 = 17 +ge_dist_null_patch = 18 +ge_dist_sclk_core_vld = 19 +ge_dist_sclk_wd_te11_vld = 20 +ge_dist_tfreq_lat_bin_0 = 21 +ge_dist_tfreq_lat_bin_1 = 22 +ge_dist_tfreq_lat_bin_2 = 23 +ge_dist_tfreq_lat_bin_3 = 24 +ge_dist_tfreq_lat_bin_4 = 25 +ge_dist_tfreq_lat_bin_5 = 26 +ge_dist_tfreq_lat_bin_6 = 27 +ge_dist_tfreq_lat_bin_7 = 28 +ge_dist_tfreq_utcl1_consecutive_retry_event = 29 +ge_dist_tfreq_utcl1_request_event = 30 +ge_dist_tfreq_utcl1_retry_event = 31 +ge_dist_tfreq_utcl1_stall_event = 32 +ge_dist_tfreq_utcl1_stall_utcl2_event = 33 +ge_dist_tfreq_utcl1_translation_hit_event = 34 +ge_dist_tfreq_utcl1_translation_miss_event = 35 +ge_dist_vs_pc_stall = 36 +ge_dist_pc_feorder_fifo_full = 37 +ge_dist_pc_ge_manager_busy = 38 +ge_dist_pc_req_stall_se0 = 39 +ge_dist_pc_req_stall_se1 = 40 +ge_dist_pc_req_stall_se2 = 41 +ge_dist_pc_req_stall_se3 = 42 +ge_dist_pc_req_stall_se4 = 43 +ge_dist_pc_req_stall_se5 = 44 +ge_dist_pc_req_stall_se6 = 45 +ge_dist_pc_req_stall_se7 = 46 +ge_dist_pc_space_zero = 47 +ge_dist_sclk_input_vld = 48 +ge_dist_reserved = 49 +ge_dist_wd_te11_busy = 50 +ge_dist_te11_starved = 51 +ge_dist_switch_mode_stall = 52 +ge_all_tf_eq = 53 +ge_all_tf2 = 54 +ge_all_tf3 = 55 +ge_all_tf4 = 56 +ge_all_tf5 = 57 +ge_all_tf6 = 58 +ge_se0_te11_starved_on_hs_done = 59 +ge_se1_te11_starved_on_hs_done = 60 +ge_se2_te11_starved_on_hs_done = 61 +ge_se3_te11_starved_on_hs_done = 62 +ge_se4_te11_starved_on_hs_done = 63 +ge_se5_te11_starved_on_hs_done = 64 +ge_se6_te11_starved_on_hs_done = 65 +ge_se7_te11_starved_on_hs_done = 66 +ge_dist_op_fifo_full_starve = 67 +ge_dist_hs_done_se0 = 68 +ge_dist_hs_done_se1 = 69 +ge_dist_hs_done_se2 = 70 +ge_dist_hs_done_se3 = 71 +ge_dist_hs_done_se4 = 72 +ge_dist_hs_done_se5 = 73 +ge_dist_hs_done_se6 = 74 +ge_dist_hs_done_se7 = 75 +ge_dist_hs_done_latency = 76 +ge_dist_distributer_busy = 77 +ge_tf_ret_data_stalling_hs_done = 78 +ge_num_of_no_dist_patches = 79 +ge_num_of_donut_dist_patches = 80 +ge_num_of_patch_dist_patches = 81 +ge_num_of_se_switches_due_to_patch_accum = 82 +ge_num_of_se_switches_due_to_donut = 83 +ge_num_of_se_switches_due_to_trap = 84 +ge_num_of_hs_alloc_events = 85 +ge_agm_gcr_req = 86 +ge_agm_gcr_tag_stall = 87 +ge_agm_gcr_crd_stall = 88 +ge_agm_gcr_stall = 89 +ge_agm_gcr_latency = 90 +ge_distclk_vld = 91 +GE2_DIST_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'GE2_SE_PERFCOUNT_SELECT' +GE2_SE_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge_se_ds_prims', + 1: 'ge_se_es_thread_groups', + 2: 'ge_se_esvert_stalled_gsprim', + 3: 'ge_se_hs_tfm_stall', + 4: 'ge_se_hs_tgs_active_high_water_mark', + 5: 'ge_se_hs_thread_groups', + 6: 'ge_se_reused_es_indices', + 7: 'ge_se_sclk_ngg_vld', + 8: 'ge_se_sclk_te11_vld', + 9: 'ge_se_spi_esvert_eov', + 10: 'ge_se_spi_esvert_stalled', + 11: 'ge_se_spi_esvert_starved_busy', + 12: 'ge_se_spi_esvert_valid', + 13: 'ge_se_spi_gsprim_cont', + 14: 'ge_se_spi_gsprim_eov', + 15: 'ge_se_spi_gsprim_stalled', + 16: 'ge_se_spi_gsprim_starved_busy', + 17: 'ge_se_spi_gsprim_valid', + 18: 'ge_se_spi_gssubgrp_is_event', + 19: 'ge_se_spi_gssubgrp_send', + 20: 'ge_se_spi_hsvert_eov', + 21: 'ge_se_spi_hsvert_stalled', + 22: 'ge_se_spi_hsvert_starved_busy', + 23: 'ge_se_spi_hsvert_valid', + 24: 'ge_se_spi_hswave_is_event', + 25: 'ge_se_spi_hswave_send', + 26: 'ge_se_spi_lsvert_eov', + 27: 'ge_se_spi_lsvert_stalled', + 28: 'ge_se_spi_lsvert_starved_busy', + 29: 'ge_se_spi_lsvert_valid', + 30: 'ge_se_spi_hsvert_fifo_full_stall', + 31: 'ge_se_spi_tgrp_fifo_stall', + 32: 'ge_spi_hsgrp_spi_stall', + 33: 'ge_se_spi_gssubgrp_event_window_active', + 34: 'ge_se_hs_input_stall', + 35: 'ge_se_sending_vert_or_prim', + 36: 'ge_se_sclk_input_vld', + 37: 'ge_spi_lswave_fifo_full_stall', + 38: 'ge_spi_hswave_fifo_full_stall', + 39: 'ge_hs_tif_stall', + 40: 'ge_csb_spi_bp', + 41: 'ge_ngg_starving_for_pc_grant', + 42: 'ge_pa0_csb_eop', + 43: 'ge_pa1_csb_eop', + 44: 'ge_ngg_starved_idle', + 45: 'ge_gsprim_send', + 46: 'ge_esvert_send', + 47: 'ge_ngg_starved_after_work', + 48: 'ge_ngg_subgrp_fifo_stall', + 49: 'ge_ngg_ord_id_req_stall', + 50: 'ge_ngg_indx_bus_stall', + 51: 'ge_hs_stall_tfmm_fifo_full', + 52: 'ge_gs_issue_rtr_stalled', + 53: 'ge_gsprim_stalled_esvert', + 54: 'ge_gsthread_stalled', + 55: 'ge_te11_stall_prim_funnel', + 56: 'ge_te11_stall_vert_funnel', + 57: 'ge_ngg_attr_grp_alloc', + 58: 'ge_ngg_attr_discard_alloc', + 59: 'ge_ngg_pc_space_not_avail', + 60: 'ge_ngg_agm_req_stall', + 61: 'ge_ngg_spi_esvert_partial_eov', + 62: 'ge_ngg_spi_gsprim_partial_eov', + 63: 'ge_spi_gsgrp_valid', + 64: 'ge_ngg_attr_grp_latency', + 65: 'ge_ngg_reuse_prim_limit_hit', + 66: 'ge_ngg_reuse_vert_limit_hit', + 67: 'ge_te11_con_stall', + 68: 'ge_te11_compactor_starved', + 69: 'ge_ngg_stall_tess_off_tess_on', + 70: 'ge_ngg_stall_tess_on_tess_off', +} +ge_se_ds_prims = 0 +ge_se_es_thread_groups = 1 +ge_se_esvert_stalled_gsprim = 2 +ge_se_hs_tfm_stall = 3 +ge_se_hs_tgs_active_high_water_mark = 4 +ge_se_hs_thread_groups = 5 +ge_se_reused_es_indices = 6 +ge_se_sclk_ngg_vld = 7 +ge_se_sclk_te11_vld = 8 +ge_se_spi_esvert_eov = 9 +ge_se_spi_esvert_stalled = 10 +ge_se_spi_esvert_starved_busy = 11 +ge_se_spi_esvert_valid = 12 +ge_se_spi_gsprim_cont = 13 +ge_se_spi_gsprim_eov = 14 +ge_se_spi_gsprim_stalled = 15 +ge_se_spi_gsprim_starved_busy = 16 +ge_se_spi_gsprim_valid = 17 +ge_se_spi_gssubgrp_is_event = 18 +ge_se_spi_gssubgrp_send = 19 +ge_se_spi_hsvert_eov = 20 +ge_se_spi_hsvert_stalled = 21 +ge_se_spi_hsvert_starved_busy = 22 +ge_se_spi_hsvert_valid = 23 +ge_se_spi_hswave_is_event = 24 +ge_se_spi_hswave_send = 25 +ge_se_spi_lsvert_eov = 26 +ge_se_spi_lsvert_stalled = 27 +ge_se_spi_lsvert_starved_busy = 28 +ge_se_spi_lsvert_valid = 29 +ge_se_spi_hsvert_fifo_full_stall = 30 +ge_se_spi_tgrp_fifo_stall = 31 +ge_spi_hsgrp_spi_stall = 32 +ge_se_spi_gssubgrp_event_window_active = 33 +ge_se_hs_input_stall = 34 +ge_se_sending_vert_or_prim = 35 +ge_se_sclk_input_vld = 36 +ge_spi_lswave_fifo_full_stall = 37 +ge_spi_hswave_fifo_full_stall = 38 +ge_hs_tif_stall = 39 +ge_csb_spi_bp = 40 +ge_ngg_starving_for_pc_grant = 41 +ge_pa0_csb_eop = 42 +ge_pa1_csb_eop = 43 +ge_ngg_starved_idle = 44 +ge_gsprim_send = 45 +ge_esvert_send = 46 +ge_ngg_starved_after_work = 47 +ge_ngg_subgrp_fifo_stall = 48 +ge_ngg_ord_id_req_stall = 49 +ge_ngg_indx_bus_stall = 50 +ge_hs_stall_tfmm_fifo_full = 51 +ge_gs_issue_rtr_stalled = 52 +ge_gsprim_stalled_esvert = 53 +ge_gsthread_stalled = 54 +ge_te11_stall_prim_funnel = 55 +ge_te11_stall_vert_funnel = 56 +ge_ngg_attr_grp_alloc = 57 +ge_ngg_attr_discard_alloc = 58 +ge_ngg_pc_space_not_avail = 59 +ge_ngg_agm_req_stall = 60 +ge_ngg_spi_esvert_partial_eov = 61 +ge_ngg_spi_gsprim_partial_eov = 62 +ge_spi_gsgrp_valid = 63 +ge_ngg_attr_grp_latency = 64 +ge_ngg_reuse_prim_limit_hit = 65 +ge_ngg_reuse_vert_limit_hit = 66 +ge_te11_con_stall = 67 +ge_te11_compactor_starved = 68 +ge_ngg_stall_tess_off_tess_on = 69 +ge_ngg_stall_tess_on_tess_off = 70 +GE2_SE_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DETECT_ONE' +VGT_DETECT_ONE__enumvalues = { + 0: 'ENABLE_TF1_OPT', + 1: 'DISABLE_TF1_OPT', +} +ENABLE_TF1_OPT = 0 +DISABLE_TF1_OPT = 1 +VGT_DETECT_ONE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DETECT_ZERO' +VGT_DETECT_ZERO__enumvalues = { + 0: 'ENABLE_TF0_OPT', + 1: 'DISABLE_TF0_OPT', +} +ENABLE_TF0_OPT = 0 +DISABLE_TF0_OPT = 1 +VGT_DETECT_ZERO = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DIST_MODE' +VGT_DIST_MODE__enumvalues = { + 0: 'NO_DIST', + 1: 'PATCHES', + 2: 'DONUTS', + 3: 'TRAPEZOIDS', +} +NO_DIST = 0 +PATCHES = 1 +DONUTS = 2 +TRAPEZOIDS = 3 +VGT_DIST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_INDEX_SIZE' +VGT_DI_INDEX_SIZE__enumvalues = { + 0: 'DI_INDEX_SIZE_16_BIT', + 1: 'DI_INDEX_SIZE_32_BIT', + 2: 'DI_INDEX_SIZE_8_BIT', +} +DI_INDEX_SIZE_16_BIT = 0 +DI_INDEX_SIZE_32_BIT = 1 +DI_INDEX_SIZE_8_BIT = 2 +VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_MAJOR_MODE_SELECT' +VGT_DI_MAJOR_MODE_SELECT__enumvalues = { + 0: 'DI_MAJOR_MODE_0', + 1: 'DI_MAJOR_MODE_1', +} +DI_MAJOR_MODE_0 = 0 +DI_MAJOR_MODE_1 = 1 +VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_PRIM_TYPE' +VGT_DI_PRIM_TYPE__enumvalues = { + 0: 'DI_PT_NONE', + 1: 'DI_PT_POINTLIST', + 2: 'DI_PT_LINELIST', + 3: 'DI_PT_LINESTRIP', + 4: 'DI_PT_TRILIST', + 5: 'DI_PT_TRIFAN', + 6: 'DI_PT_TRISTRIP', + 7: 'DI_PT_2D_RECTANGLE', + 8: 'DI_PT_UNUSED_1', + 9: 'DI_PT_PATCH', + 10: 'DI_PT_LINELIST_ADJ', + 11: 'DI_PT_LINESTRIP_ADJ', + 12: 'DI_PT_TRILIST_ADJ', + 13: 'DI_PT_TRISTRIP_ADJ', + 14: 'DI_PT_UNUSED_3', + 15: 'DI_PT_UNUSED_4', + 16: 'DI_PT_UNUSED_5', + 17: 'DI_PT_RECTLIST', + 18: 'DI_PT_LINELOOP', + 19: 'DI_PT_QUADLIST', + 20: 'DI_PT_QUADSTRIP', + 21: 'DI_PT_POLYGON', +} +DI_PT_NONE = 0 +DI_PT_POINTLIST = 1 +DI_PT_LINELIST = 2 +DI_PT_LINESTRIP = 3 +DI_PT_TRILIST = 4 +DI_PT_TRIFAN = 5 +DI_PT_TRISTRIP = 6 +DI_PT_2D_RECTANGLE = 7 +DI_PT_UNUSED_1 = 8 +DI_PT_PATCH = 9 +DI_PT_LINELIST_ADJ = 10 +DI_PT_LINESTRIP_ADJ = 11 +DI_PT_TRILIST_ADJ = 12 +DI_PT_TRISTRIP_ADJ = 13 +DI_PT_UNUSED_3 = 14 +DI_PT_UNUSED_4 = 15 +DI_PT_UNUSED_5 = 16 +DI_PT_RECTLIST = 17 +DI_PT_LINELOOP = 18 +DI_PT_QUADLIST = 19 +DI_PT_QUADSTRIP = 20 +DI_PT_POLYGON = 21 +VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_SOURCE_SELECT' +VGT_DI_SOURCE_SELECT__enumvalues = { + 0: 'DI_SRC_SEL_DMA', + 1: 'DI_SRC_SEL_IMMEDIATE', + 2: 'DI_SRC_SEL_AUTO_INDEX', + 3: 'DI_SRC_SEL_RESERVED', +} +DI_SRC_SEL_DMA = 0 +DI_SRC_SEL_IMMEDIATE = 1 +DI_SRC_SEL_AUTO_INDEX = 2 +DI_SRC_SEL_RESERVED = 3 +VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_BUF_TYPE' +VGT_DMA_BUF_TYPE__enumvalues = { + 0: 'VGT_DMA_BUF_MEM', + 1: 'VGT_DMA_BUF_RING', + 2: 'VGT_DMA_BUF_SETUP', + 3: 'VGT_DMA_PTR_UPDATE', +} +VGT_DMA_BUF_MEM = 0 +VGT_DMA_BUF_RING = 1 +VGT_DMA_BUF_SETUP = 2 +VGT_DMA_PTR_UPDATE = 3 +VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_SWAP_MODE' +VGT_DMA_SWAP_MODE__enumvalues = { + 0: 'VGT_DMA_SWAP_NONE', + 1: 'VGT_DMA_SWAP_16_BIT', + 2: 'VGT_DMA_SWAP_32_BIT', + 3: 'VGT_DMA_SWAP_WORD', +} +VGT_DMA_SWAP_NONE = 0 +VGT_DMA_SWAP_16_BIT = 1 +VGT_DMA_SWAP_32_BIT = 2 +VGT_DMA_SWAP_WORD = 3 +VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_EVENT_TYPE' +VGT_EVENT_TYPE__enumvalues = { + 0: 'Reserved_0x00', + 1: 'SAMPLE_STREAMOUTSTATS1', + 2: 'SAMPLE_STREAMOUTSTATS2', + 3: 'SAMPLE_STREAMOUTSTATS3', + 4: 'CACHE_FLUSH_TS', + 5: 'CONTEXT_DONE', + 6: 'CACHE_FLUSH', + 7: 'CS_PARTIAL_FLUSH', + 8: 'VGT_STREAMOUT_SYNC', + 9: 'Reserved_0x09', + 10: 'VGT_STREAMOUT_RESET', + 11: 'END_OF_PIPE_INCR_DE', + 12: 'END_OF_PIPE_IB_END', + 13: 'RST_PIX_CNT', + 14: 'BREAK_BATCH', + 15: 'VS_PARTIAL_FLUSH', + 16: 'PS_PARTIAL_FLUSH', + 17: 'FLUSH_HS_OUTPUT', + 18: 'FLUSH_DFSM', + 19: 'RESET_TO_LOWEST_VGT', + 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', + 21: 'WAIT_SYNC', + 22: 'CACHE_FLUSH_AND_INV_EVENT', + 23: 'PERFCOUNTER_START', + 24: 'PERFCOUNTER_STOP', + 25: 'PIPELINESTAT_START', + 26: 'PIPELINESTAT_STOP', + 27: 'PERFCOUNTER_SAMPLE', + 28: 'FLUSH_ES_OUTPUT', + 29: 'BIN_CONF_OVERRIDE_CHECK', + 30: 'SAMPLE_PIPELINESTAT', + 31: 'SO_VGTSTREAMOUT_FLUSH', + 32: 'SAMPLE_STREAMOUTSTATS', + 33: 'RESET_VTX_CNT', + 34: 'BLOCK_CONTEXT_DONE', + 35: 'CS_CONTEXT_DONE', + 36: 'VGT_FLUSH', + 37: 'TGID_ROLLOVER', + 38: 'SQ_NON_EVENT', + 39: 'SC_SEND_DB_VPZ', + 40: 'BOTTOM_OF_PIPE_TS', + 41: 'FLUSH_SX_TS', + 42: 'DB_CACHE_FLUSH_AND_INV', + 43: 'FLUSH_AND_INV_DB_DATA_TS', + 44: 'FLUSH_AND_INV_DB_META', + 45: 'FLUSH_AND_INV_CB_DATA_TS', + 46: 'FLUSH_AND_INV_CB_META', + 47: 'CS_DONE', + 48: 'PS_DONE', + 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', + 50: 'SX_CB_RAT_ACK_REQUEST', + 51: 'THREAD_TRACE_START', + 52: 'THREAD_TRACE_STOP', + 53: 'THREAD_TRACE_MARKER', + 54: 'THREAD_TRACE_DRAW', + 55: 'THREAD_TRACE_FINISH', + 56: 'PIXEL_PIPE_STAT_CONTROL', + 57: 'PIXEL_PIPE_STAT_DUMP', + 58: 'PIXEL_PIPE_STAT_RESET', + 59: 'CONTEXT_SUSPEND', + 60: 'OFFCHIP_HS_DEALLOC', + 61: 'ENABLE_NGG_PIPELINE', + 62: 'ENABLE_LEGACY_PIPELINE', + 63: 'DRAW_DONE', +} +Reserved_0x00 = 0 +SAMPLE_STREAMOUTSTATS1 = 1 +SAMPLE_STREAMOUTSTATS2 = 2 +SAMPLE_STREAMOUTSTATS3 = 3 +CACHE_FLUSH_TS = 4 +CONTEXT_DONE = 5 +CACHE_FLUSH = 6 +CS_PARTIAL_FLUSH = 7 +VGT_STREAMOUT_SYNC = 8 +Reserved_0x09 = 9 +VGT_STREAMOUT_RESET = 10 +END_OF_PIPE_INCR_DE = 11 +END_OF_PIPE_IB_END = 12 +RST_PIX_CNT = 13 +BREAK_BATCH = 14 +VS_PARTIAL_FLUSH = 15 +PS_PARTIAL_FLUSH = 16 +FLUSH_HS_OUTPUT = 17 +FLUSH_DFSM = 18 +RESET_TO_LOWEST_VGT = 19 +CACHE_FLUSH_AND_INV_TS_EVENT = 20 +WAIT_SYNC = 21 +CACHE_FLUSH_AND_INV_EVENT = 22 +PERFCOUNTER_START = 23 +PERFCOUNTER_STOP = 24 +PIPELINESTAT_START = 25 +PIPELINESTAT_STOP = 26 +PERFCOUNTER_SAMPLE = 27 +FLUSH_ES_OUTPUT = 28 +BIN_CONF_OVERRIDE_CHECK = 29 +SAMPLE_PIPELINESTAT = 30 +SO_VGTSTREAMOUT_FLUSH = 31 +SAMPLE_STREAMOUTSTATS = 32 +RESET_VTX_CNT = 33 +BLOCK_CONTEXT_DONE = 34 +CS_CONTEXT_DONE = 35 +VGT_FLUSH = 36 +TGID_ROLLOVER = 37 +SQ_NON_EVENT = 38 +SC_SEND_DB_VPZ = 39 +BOTTOM_OF_PIPE_TS = 40 +FLUSH_SX_TS = 41 +DB_CACHE_FLUSH_AND_INV = 42 +FLUSH_AND_INV_DB_DATA_TS = 43 +FLUSH_AND_INV_DB_META = 44 +FLUSH_AND_INV_CB_DATA_TS = 45 +FLUSH_AND_INV_CB_META = 46 +CS_DONE = 47 +PS_DONE = 48 +FLUSH_AND_INV_CB_PIXEL_DATA = 49 +SX_CB_RAT_ACK_REQUEST = 50 +THREAD_TRACE_START = 51 +THREAD_TRACE_STOP = 52 +THREAD_TRACE_MARKER = 53 +THREAD_TRACE_DRAW = 54 +THREAD_TRACE_FINISH = 55 +PIXEL_PIPE_STAT_CONTROL = 56 +PIXEL_PIPE_STAT_DUMP = 57 +PIXEL_PIPE_STAT_RESET = 58 +CONTEXT_SUSPEND = 59 +OFFCHIP_HS_DEALLOC = 60 +ENABLE_NGG_PIPELINE = 61 +ENABLE_LEGACY_PIPELINE = 62 +DRAW_DONE = 63 +VGT_EVENT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GROUP_CONV_SEL' +VGT_GROUP_CONV_SEL__enumvalues = { + 0: 'VGT_GRP_INDEX_16', + 1: 'VGT_GRP_INDEX_32', + 2: 'VGT_GRP_UINT_16', + 3: 'VGT_GRP_UINT_32', + 4: 'VGT_GRP_SINT_16', + 5: 'VGT_GRP_SINT_32', + 6: 'VGT_GRP_FLOAT_32', + 7: 'VGT_GRP_AUTO_PRIM', + 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', +} +VGT_GRP_INDEX_16 = 0 +VGT_GRP_INDEX_32 = 1 +VGT_GRP_UINT_16 = 2 +VGT_GRP_UINT_32 = 3 +VGT_GRP_SINT_16 = 4 +VGT_GRP_SINT_32 = 5 +VGT_GRP_FLOAT_32 = 6 +VGT_GRP_AUTO_PRIM = 7 +VGT_GRP_FIX_1_23_TO_FLOAT = 8 +VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_MODE_TYPE' +VGT_GS_MODE_TYPE__enumvalues = { + 0: 'GS_OFF', + 1: 'GS_SCENARIO_A', + 2: 'GS_SCENARIO_B', + 3: 'GS_SCENARIO_G', + 4: 'GS_SCENARIO_C', + 5: 'SPRITE_EN', +} +GS_OFF = 0 +GS_SCENARIO_A = 1 +GS_SCENARIO_B = 2 +GS_SCENARIO_G = 3 +GS_SCENARIO_C = 4 +SPRITE_EN = 5 +VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_OUTPRIM_TYPE' +VGT_GS_OUTPRIM_TYPE__enumvalues = { + 0: 'POINTLIST', + 1: 'LINESTRIP', + 2: 'TRISTRIP', + 3: 'RECT_2D', + 4: 'RECTLIST', +} +POINTLIST = 0 +LINESTRIP = 1 +TRISTRIP = 2 +RECT_2D = 3 +RECTLIST = 4 +VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_INDEX_TYPE_MODE' +VGT_INDEX_TYPE_MODE__enumvalues = { + 0: 'VGT_INDEX_16', + 1: 'VGT_INDEX_32', + 2: 'VGT_INDEX_8', +} +VGT_INDEX_16 = 0 +VGT_INDEX_32 = 1 +VGT_INDEX_8 = 2 +VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUTPATH_SELECT' +VGT_OUTPATH_SELECT__enumvalues = { + 0: 'VGT_OUTPATH_VTX_REUSE', + 1: 'VGT_OUTPATH_GS_BLOCK', + 2: 'VGT_OUTPATH_HS_BLOCK', + 3: 'VGT_OUTPATH_PRIM_GEN', + 4: 'VGT_OUTPATH_TE_PRIM_GEN', + 5: 'VGT_OUTPATH_TE_GS_BLOCK', + 6: 'VGT_OUTPATH_TE_OUTPUT', +} +VGT_OUTPATH_VTX_REUSE = 0 +VGT_OUTPATH_GS_BLOCK = 1 +VGT_OUTPATH_HS_BLOCK = 2 +VGT_OUTPATH_PRIM_GEN = 3 +VGT_OUTPATH_TE_PRIM_GEN = 4 +VGT_OUTPATH_TE_GS_BLOCK = 5 +VGT_OUTPATH_TE_OUTPUT = 6 +VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUT_PRIM_TYPE' +VGT_OUT_PRIM_TYPE__enumvalues = { + 0: 'VGT_OUT_POINT', + 1: 'VGT_OUT_LINE', + 2: 'VGT_OUT_TRI', + 3: 'VGT_OUT_RECT_V0', + 4: 'VGT_OUT_RECT_V1', + 5: 'VGT_OUT_RECT_V2', + 6: 'VGT_OUT_RECT_V3', + 7: 'VGT_OUT_2D_RECT', + 8: 'VGT_TE_QUAD', + 9: 'VGT_TE_PRIM_INDEX_LINE', + 10: 'VGT_TE_PRIM_INDEX_TRI', + 11: 'VGT_TE_PRIM_INDEX_QUAD', + 12: 'VGT_OUT_LINE_ADJ', + 13: 'VGT_OUT_TRI_ADJ', + 14: 'VGT_OUT_PATCH', +} +VGT_OUT_POINT = 0 +VGT_OUT_LINE = 1 +VGT_OUT_TRI = 2 +VGT_OUT_RECT_V0 = 3 +VGT_OUT_RECT_V1 = 4 +VGT_OUT_RECT_V2 = 5 +VGT_OUT_RECT_V3 = 6 +VGT_OUT_2D_RECT = 7 +VGT_TE_QUAD = 8 +VGT_TE_PRIM_INDEX_LINE = 9 +VGT_TE_PRIM_INDEX_TRI = 10 +VGT_TE_PRIM_INDEX_QUAD = 11 +VGT_OUT_LINE_ADJ = 12 +VGT_OUT_TRI_ADJ = 13 +VGT_OUT_PATCH = 14 +VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_RDREQ_POLICY' +VGT_RDREQ_POLICY__enumvalues = { + 0: 'VGT_POLICY_LRU', + 1: 'VGT_POLICY_STREAM', + 2: 'VGT_POLICY_BYPASS', +} +VGT_POLICY_LRU = 0 +VGT_POLICY_STREAM = 1 +VGT_POLICY_BYPASS = 2 +VGT_RDREQ_POLICY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_ES_EN' +VGT_STAGES_ES_EN__enumvalues = { + 0: 'ES_STAGE_OFF', + 1: 'ES_STAGE_DS', + 2: 'ES_STAGE_REAL', + 3: 'RESERVED_ES', +} +ES_STAGE_OFF = 0 +ES_STAGE_DS = 1 +ES_STAGE_REAL = 2 +RESERVED_ES = 3 +VGT_STAGES_ES_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_GS_EN' +VGT_STAGES_GS_EN__enumvalues = { + 0: 'GS_STAGE_OFF', + 1: 'GS_STAGE_ON', +} +GS_STAGE_OFF = 0 +GS_STAGE_ON = 1 +VGT_STAGES_GS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_HS_EN' +VGT_STAGES_HS_EN__enumvalues = { + 0: 'HS_STAGE_OFF', + 1: 'HS_STAGE_ON', +} +HS_STAGE_OFF = 0 +HS_STAGE_ON = 1 +VGT_STAGES_HS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_LS_EN' +VGT_STAGES_LS_EN__enumvalues = { + 0: 'LS_STAGE_OFF', + 1: 'LS_STAGE_ON', + 2: 'CS_STAGE_ON', + 3: 'RESERVED_LS', +} +LS_STAGE_OFF = 0 +LS_STAGE_ON = 1 +CS_STAGE_ON = 2 +RESERVED_LS = 3 +VGT_STAGES_LS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_VS_EN' +VGT_STAGES_VS_EN__enumvalues = { + 0: 'VS_STAGE_REAL', + 1: 'VS_STAGE_DS', + 2: 'VS_STAGE_COPY_SHADER', + 3: 'RESERVED_VS', +} +VS_STAGE_REAL = 0 +VS_STAGE_DS = 1 +VS_STAGE_COPY_SHADER = 2 +RESERVED_VS = 3 +VGT_STAGES_VS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_PARTITION' +VGT_TESS_PARTITION__enumvalues = { + 0: 'PART_INTEGER', + 1: 'PART_POW2', + 2: 'PART_FRAC_ODD', + 3: 'PART_FRAC_EVEN', +} +PART_INTEGER = 0 +PART_POW2 = 1 +PART_FRAC_ODD = 2 +PART_FRAC_EVEN = 3 +VGT_TESS_PARTITION = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TOPOLOGY' +VGT_TESS_TOPOLOGY__enumvalues = { + 0: 'OUTPUT_POINT', + 1: 'OUTPUT_LINE', + 2: 'OUTPUT_TRIANGLE_CW', + 3: 'OUTPUT_TRIANGLE_CCW', +} +OUTPUT_POINT = 0 +OUTPUT_LINE = 1 +OUTPUT_TRIANGLE_CW = 2 +OUTPUT_TRIANGLE_CCW = 3 +VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TYPE' +VGT_TESS_TYPE__enumvalues = { + 0: 'TESS_ISOLINE', + 1: 'TESS_TRIANGLE', + 2: 'TESS_QUAD', +} +TESS_ISOLINE = 0 +TESS_TRIANGLE = 1 +TESS_QUAD = 2 +VGT_TESS_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_REG_XFER' +WD_IA_DRAW_REG_XFER__enumvalues = { + 0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', + 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', + 2: 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', + 3: 'WD_IA_DRAW_REG_XFER_GE_CNTL', + 4: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', + 5: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', + 6: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', + 7: 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', + 8: 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', +} +WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0 +WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 +WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 2 +WD_IA_DRAW_REG_XFER_GE_CNTL = 3 +WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 4 +WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 5 +WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 6 +WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 7 +WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 8 +WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_SOURCE' +WD_IA_DRAW_SOURCE__enumvalues = { + 0: 'WD_IA_DRAW_SOURCE_DMA', + 1: 'WD_IA_DRAW_SOURCE_IMMD', + 2: 'WD_IA_DRAW_SOURCE_AUTO', + 3: 'WD_IA_DRAW_SOURCE_OPAQ', +} +WD_IA_DRAW_SOURCE_DMA = 0 +WD_IA_DRAW_SOURCE_IMMD = 1 +WD_IA_DRAW_SOURCE_AUTO = 2 +WD_IA_DRAW_SOURCE_OPAQ = 3 +WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_TYPE' +WD_IA_DRAW_TYPE__enumvalues = { + 0: 'WD_IA_DRAW_TYPE_DI_MM0', + 1: 'WD_IA_DRAW_TYPE_REG_XFER', + 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', + 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 4: 'WD_IA_DRAW_TYPE_MIN_INDX', + 5: 'WD_IA_DRAW_TYPE_MAX_INDX', + 6: 'WD_IA_DRAW_TYPE_INDX_OFF', + 7: 'WD_IA_DRAW_TYPE_IMM_DATA', +} +WD_IA_DRAW_TYPE_DI_MM0 = 0 +WD_IA_DRAW_TYPE_REG_XFER = 1 +WD_IA_DRAW_TYPE_EVENT_INIT = 2 +WD_IA_DRAW_TYPE_EVENT_ADDR = 3 +WD_IA_DRAW_TYPE_MIN_INDX = 4 +WD_IA_DRAW_TYPE_MAX_INDX = 5 +WD_IA_DRAW_TYPE_INDX_OFF = 6 +WD_IA_DRAW_TYPE_IMM_DATA = 7 +WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'GB_EDC_DED_MODE' +GB_EDC_DED_MODE__enumvalues = { + 0: 'GB_EDC_DED_MODE_LOG', + 1: 'GB_EDC_DED_MODE_HALT', + 2: 'GB_EDC_DED_MODE_INT_HALT', +} +GB_EDC_DED_MODE_LOG = 0 +GB_EDC_DED_MODE_HALT = 1 +GB_EDC_DED_MODE_INT_HALT = 2 +GB_EDC_DED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CHA_PERF_SEL' +CHA_PERF_SEL__enumvalues = { + 0: 'CHA_PERF_SEL_BUSY', + 1: 'CHA_PERF_SEL_STALL_CHC0', + 2: 'CHA_PERF_SEL_STALL_CHC1', + 3: 'CHA_PERF_SEL_STALL_CHC2', + 4: 'CHA_PERF_SEL_STALL_CHC3', + 5: 'CHA_PERF_SEL_STALL_CHC4', + 6: 'CHA_PERF_SEL_STALL_CHC5', + 7: 'CHA_PERF_SEL_REQUEST_CHC0', + 8: 'CHA_PERF_SEL_REQUEST_CHC1', + 9: 'CHA_PERF_SEL_REQUEST_CHC2', + 10: 'CHA_PERF_SEL_REQUEST_CHC3', + 11: 'CHA_PERF_SEL_REQUEST_CHC4', + 12: 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', + 13: 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', + 14: 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', + 15: 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', + 16: 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', + 17: 'CHA_PERF_SEL_IO_32B_WDS_CHC0', + 18: 'CHA_PERF_SEL_IO_32B_WDS_CHC1', + 19: 'CHA_PERF_SEL_IO_32B_WDS_CHC2', + 20: 'CHA_PERF_SEL_IO_32B_WDS_CHC3', + 21: 'CHA_PERF_SEL_IO_32B_WDS_CHC4', + 22: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', + 23: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', + 24: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', + 25: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', + 26: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', + 27: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', + 28: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', + 29: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', + 30: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', + 31: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', + 32: 'CHA_PERF_SEL_ARB_REQUESTS', + 33: 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', + 34: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', + 35: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', + 36: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', + 37: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', + 38: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', + 39: 'CHA_PERF_SEL_CYCLE', +} +CHA_PERF_SEL_BUSY = 0 +CHA_PERF_SEL_STALL_CHC0 = 1 +CHA_PERF_SEL_STALL_CHC1 = 2 +CHA_PERF_SEL_STALL_CHC2 = 3 +CHA_PERF_SEL_STALL_CHC3 = 4 +CHA_PERF_SEL_STALL_CHC4 = 5 +CHA_PERF_SEL_STALL_CHC5 = 6 +CHA_PERF_SEL_REQUEST_CHC0 = 7 +CHA_PERF_SEL_REQUEST_CHC1 = 8 +CHA_PERF_SEL_REQUEST_CHC2 = 9 +CHA_PERF_SEL_REQUEST_CHC3 = 10 +CHA_PERF_SEL_REQUEST_CHC4 = 11 +CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 12 +CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 13 +CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 14 +CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 15 +CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 16 +CHA_PERF_SEL_IO_32B_WDS_CHC0 = 17 +CHA_PERF_SEL_IO_32B_WDS_CHC1 = 18 +CHA_PERF_SEL_IO_32B_WDS_CHC2 = 19 +CHA_PERF_SEL_IO_32B_WDS_CHC3 = 20 +CHA_PERF_SEL_IO_32B_WDS_CHC4 = 21 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 22 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 23 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 24 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 25 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 26 +CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 27 +CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 28 +CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 29 +CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 30 +CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 31 +CHA_PERF_SEL_ARB_REQUESTS = 32 +CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 33 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 34 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 35 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 36 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 37 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 38 +CHA_PERF_SEL_CYCLE = 39 +CHA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CHCG_PERF_SEL' +CHCG_PERF_SEL__enumvalues = { + 0: 'CHCG_PERF_SEL_CYCLE', + 1: 'CHCG_PERF_SEL_BUSY', + 2: 'CHCG_PERF_SEL_STARVE', + 3: 'CHCG_PERF_SEL_ARB_RET_LEVEL', + 4: 'CHCG_PERF_SEL_GL2_REQ_READ_LATENCY', + 5: 'CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY', + 6: 'CHCG_PERF_SEL_REQ', + 7: 'CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET', + 8: 'CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 9: 'CHCG_PERF_SEL_REQ_NOP_ACK', + 10: 'CHCG_PERF_SEL_REQ_NOP_RTN0', + 11: 'CHCG_PERF_SEL_REQ_READ', + 12: 'CHCG_PERF_SEL_REQ_READ_128B', + 13: 'CHCG_PERF_SEL_REQ_READ_32B', + 14: 'CHCG_PERF_SEL_REQ_READ_64B', + 15: 'CHCG_PERF_SEL_REQ_WRITE', + 16: 'CHCG_PERF_SEL_REQ_WRITE_32B', + 17: 'CHCG_PERF_SEL_REQ_WRITE_64B', + 18: 'CHCG_PERF_SEL_STALL_GUS_GL1', + 19: 'CHCG_PERF_SEL_STALL_BUFFER_FULL', + 20: 'CHCG_PERF_SEL_REQ_CLIENT0', + 21: 'CHCG_PERF_SEL_REQ_CLIENT1', + 22: 'CHCG_PERF_SEL_REQ_CLIENT2', + 23: 'CHCG_PERF_SEL_REQ_CLIENT3', + 24: 'CHCG_PERF_SEL_REQ_CLIENT4', + 25: 'CHCG_PERF_SEL_REQ_CLIENT5', + 26: 'CHCG_PERF_SEL_REQ_CLIENT6', + 27: 'CHCG_PERF_SEL_REQ_CLIENT7', + 28: 'CHCG_PERF_SEL_REQ_CLIENT8', + 29: 'CHCG_PERF_SEL_REQ_CLIENT9', + 30: 'CHCG_PERF_SEL_REQ_CLIENT10', + 31: 'CHCG_PERF_SEL_REQ_CLIENT11', + 32: 'CHCG_PERF_SEL_REQ_CLIENT12', + 33: 'CHCG_PERF_SEL_REQ_CLIENT13', + 34: 'CHCG_PERF_SEL_REQ_CLIENT14', + 35: 'CHCG_PERF_SEL_REQ_CLIENT15', + 36: 'CHCG_PERF_SEL_REQ_CLIENT16', + 37: 'CHCG_PERF_SEL_REQ_CLIENT17', + 38: 'CHCG_PERF_SEL_REQ_CLIENT18', + 39: 'CHCG_PERF_SEL_REQ_CLIENT19', + 40: 'CHCG_PERF_SEL_REQ_CLIENT20', + 41: 'CHCG_PERF_SEL_REQ_CLIENT21', + 42: 'CHCG_PERF_SEL_REQ_CLIENT22', + 43: 'CHCG_PERF_SEL_REQ_CLIENT23', +} +CHCG_PERF_SEL_CYCLE = 0 +CHCG_PERF_SEL_BUSY = 1 +CHCG_PERF_SEL_STARVE = 2 +CHCG_PERF_SEL_ARB_RET_LEVEL = 3 +CHCG_PERF_SEL_GL2_REQ_READ_LATENCY = 4 +CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 +CHCG_PERF_SEL_REQ = 6 +CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 +CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 +CHCG_PERF_SEL_REQ_NOP_ACK = 9 +CHCG_PERF_SEL_REQ_NOP_RTN0 = 10 +CHCG_PERF_SEL_REQ_READ = 11 +CHCG_PERF_SEL_REQ_READ_128B = 12 +CHCG_PERF_SEL_REQ_READ_32B = 13 +CHCG_PERF_SEL_REQ_READ_64B = 14 +CHCG_PERF_SEL_REQ_WRITE = 15 +CHCG_PERF_SEL_REQ_WRITE_32B = 16 +CHCG_PERF_SEL_REQ_WRITE_64B = 17 +CHCG_PERF_SEL_STALL_GUS_GL1 = 18 +CHCG_PERF_SEL_STALL_BUFFER_FULL = 19 +CHCG_PERF_SEL_REQ_CLIENT0 = 20 +CHCG_PERF_SEL_REQ_CLIENT1 = 21 +CHCG_PERF_SEL_REQ_CLIENT2 = 22 +CHCG_PERF_SEL_REQ_CLIENT3 = 23 +CHCG_PERF_SEL_REQ_CLIENT4 = 24 +CHCG_PERF_SEL_REQ_CLIENT5 = 25 +CHCG_PERF_SEL_REQ_CLIENT6 = 26 +CHCG_PERF_SEL_REQ_CLIENT7 = 27 +CHCG_PERF_SEL_REQ_CLIENT8 = 28 +CHCG_PERF_SEL_REQ_CLIENT9 = 29 +CHCG_PERF_SEL_REQ_CLIENT10 = 30 +CHCG_PERF_SEL_REQ_CLIENT11 = 31 +CHCG_PERF_SEL_REQ_CLIENT12 = 32 +CHCG_PERF_SEL_REQ_CLIENT13 = 33 +CHCG_PERF_SEL_REQ_CLIENT14 = 34 +CHCG_PERF_SEL_REQ_CLIENT15 = 35 +CHCG_PERF_SEL_REQ_CLIENT16 = 36 +CHCG_PERF_SEL_REQ_CLIENT17 = 37 +CHCG_PERF_SEL_REQ_CLIENT18 = 38 +CHCG_PERF_SEL_REQ_CLIENT19 = 39 +CHCG_PERF_SEL_REQ_CLIENT20 = 40 +CHCG_PERF_SEL_REQ_CLIENT21 = 41 +CHCG_PERF_SEL_REQ_CLIENT22 = 42 +CHCG_PERF_SEL_REQ_CLIENT23 = 43 +CHCG_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CHC_PERF_SEL' +CHC_PERF_SEL__enumvalues = { + 0: 'CHC_PERF_SEL_CYCLE', + 1: 'CHC_PERF_SEL_BUSY', + 2: 'CHC_PERF_SEL_STARVE', + 3: 'CHC_PERF_SEL_ARB_RET_LEVEL', + 4: 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', + 5: 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', + 6: 'CHC_PERF_SEL_REQ', + 7: 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', + 8: 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 9: 'CHC_PERF_SEL_REQ_NOP_ACK', + 10: 'CHC_PERF_SEL_REQ_NOP_RTN0', + 11: 'CHC_PERF_SEL_REQ_READ', + 12: 'CHC_PERF_SEL_REQ_READ_128B', + 13: 'CHC_PERF_SEL_REQ_READ_32B', + 14: 'CHC_PERF_SEL_REQ_READ_64B', + 15: 'CHC_PERF_SEL_REQ_WRITE', + 16: 'CHC_PERF_SEL_REQ_WRITE_32B', + 17: 'CHC_PERF_SEL_REQ_WRITE_64B', + 18: 'CHC_PERF_SEL_STALL_GL2_GL1', + 19: 'CHC_PERF_SEL_STALL_BUFFER_FULL', + 20: 'CHC_PERF_SEL_REQ_CLIENT0', + 21: 'CHC_PERF_SEL_REQ_CLIENT1', + 22: 'CHC_PERF_SEL_REQ_CLIENT2', + 23: 'CHC_PERF_SEL_REQ_CLIENT3', + 24: 'CHC_PERF_SEL_REQ_CLIENT4', + 25: 'CHC_PERF_SEL_REQ_CLIENT5', + 26: 'CHC_PERF_SEL_REQ_CLIENT6', + 27: 'CHC_PERF_SEL_REQ_CLIENT7', + 28: 'CHC_PERF_SEL_REQ_CLIENT8', + 29: 'CHC_PERF_SEL_REQ_CLIENT9', + 30: 'CHC_PERF_SEL_REQ_CLIENT10', + 31: 'CHC_PERF_SEL_REQ_CLIENT11', + 32: 'CHC_PERF_SEL_REQ_CLIENT12', + 33: 'CHC_PERF_SEL_REQ_CLIENT13', + 34: 'CHC_PERF_SEL_REQ_CLIENT14', + 35: 'CHC_PERF_SEL_REQ_CLIENT15', + 36: 'CHC_PERF_SEL_REQ_CLIENT16', + 37: 'CHC_PERF_SEL_REQ_CLIENT17', + 38: 'CHC_PERF_SEL_REQ_CLIENT18', + 39: 'CHC_PERF_SEL_REQ_CLIENT19', + 40: 'CHC_PERF_SEL_REQ_CLIENT20', + 41: 'CHC_PERF_SEL_REQ_CLIENT21', + 42: 'CHC_PERF_SEL_REQ_CLIENT22', + 43: 'CHC_PERF_SEL_REQ_CLIENT23', +} +CHC_PERF_SEL_CYCLE = 0 +CHC_PERF_SEL_BUSY = 1 +CHC_PERF_SEL_STARVE = 2 +CHC_PERF_SEL_ARB_RET_LEVEL = 3 +CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 4 +CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 +CHC_PERF_SEL_REQ = 6 +CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 +CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 +CHC_PERF_SEL_REQ_NOP_ACK = 9 +CHC_PERF_SEL_REQ_NOP_RTN0 = 10 +CHC_PERF_SEL_REQ_READ = 11 +CHC_PERF_SEL_REQ_READ_128B = 12 +CHC_PERF_SEL_REQ_READ_32B = 13 +CHC_PERF_SEL_REQ_READ_64B = 14 +CHC_PERF_SEL_REQ_WRITE = 15 +CHC_PERF_SEL_REQ_WRITE_32B = 16 +CHC_PERF_SEL_REQ_WRITE_64B = 17 +CHC_PERF_SEL_STALL_GL2_GL1 = 18 +CHC_PERF_SEL_STALL_BUFFER_FULL = 19 +CHC_PERF_SEL_REQ_CLIENT0 = 20 +CHC_PERF_SEL_REQ_CLIENT1 = 21 +CHC_PERF_SEL_REQ_CLIENT2 = 22 +CHC_PERF_SEL_REQ_CLIENT3 = 23 +CHC_PERF_SEL_REQ_CLIENT4 = 24 +CHC_PERF_SEL_REQ_CLIENT5 = 25 +CHC_PERF_SEL_REQ_CLIENT6 = 26 +CHC_PERF_SEL_REQ_CLIENT7 = 27 +CHC_PERF_SEL_REQ_CLIENT8 = 28 +CHC_PERF_SEL_REQ_CLIENT9 = 29 +CHC_PERF_SEL_REQ_CLIENT10 = 30 +CHC_PERF_SEL_REQ_CLIENT11 = 31 +CHC_PERF_SEL_REQ_CLIENT12 = 32 +CHC_PERF_SEL_REQ_CLIENT13 = 33 +CHC_PERF_SEL_REQ_CLIENT14 = 34 +CHC_PERF_SEL_REQ_CLIENT15 = 35 +CHC_PERF_SEL_REQ_CLIENT16 = 36 +CHC_PERF_SEL_REQ_CLIENT17 = 37 +CHC_PERF_SEL_REQ_CLIENT18 = 38 +CHC_PERF_SEL_REQ_CLIENT19 = 39 +CHC_PERF_SEL_REQ_CLIENT20 = 40 +CHC_PERF_SEL_REQ_CLIENT21 = 41 +CHC_PERF_SEL_REQ_CLIENT22 = 42 +CHC_PERF_SEL_REQ_CLIENT23 = 43 +CHC_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1A_PERF_SEL' +GL1A_PERF_SEL__enumvalues = { + 0: 'GL1A_PERF_SEL_BUSY', + 1: 'GL1A_PERF_SEL_STALL_GL1C0', + 2: 'GL1A_PERF_SEL_STALL_GL1C1', + 3: 'GL1A_PERF_SEL_STALL_GL1C2', + 4: 'GL1A_PERF_SEL_STALL_GL1C3', + 5: 'GL1A_PERF_SEL_REQUEST_GL1C0', + 6: 'GL1A_PERF_SEL_REQUEST_GL1C1', + 7: 'GL1A_PERF_SEL_REQUEST_GL1C2', + 8: 'GL1A_PERF_SEL_REQUEST_GL1C3', + 9: 'GL1A_PERF_SEL_WDS_32B_GL1C0', + 10: 'GL1A_PERF_SEL_WDS_32B_GL1C1', + 11: 'GL1A_PERF_SEL_WDS_32B_GL1C2', + 12: 'GL1A_PERF_SEL_WDS_32B_GL1C3', + 13: 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', + 14: 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', + 15: 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', + 16: 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', + 17: 'GL1A_PERF_SEL_ARB_REQUESTS', + 18: 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', + 19: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', + 20: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', + 21: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', + 22: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', + 23: 'GL1A_PERF_SEL_CYCLE', +} +GL1A_PERF_SEL_BUSY = 0 +GL1A_PERF_SEL_STALL_GL1C0 = 1 +GL1A_PERF_SEL_STALL_GL1C1 = 2 +GL1A_PERF_SEL_STALL_GL1C2 = 3 +GL1A_PERF_SEL_STALL_GL1C3 = 4 +GL1A_PERF_SEL_REQUEST_GL1C0 = 5 +GL1A_PERF_SEL_REQUEST_GL1C1 = 6 +GL1A_PERF_SEL_REQUEST_GL1C2 = 7 +GL1A_PERF_SEL_REQUEST_GL1C3 = 8 +GL1A_PERF_SEL_WDS_32B_GL1C0 = 9 +GL1A_PERF_SEL_WDS_32B_GL1C1 = 10 +GL1A_PERF_SEL_WDS_32B_GL1C2 = 11 +GL1A_PERF_SEL_WDS_32B_GL1C3 = 12 +GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 13 +GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 14 +GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 15 +GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 16 +GL1A_PERF_SEL_ARB_REQUESTS = 17 +GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 18 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 19 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 20 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 21 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 22 +GL1A_PERF_SEL_CYCLE = 23 +GL1A_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1C_PERF_SEL' +GL1C_PERF_SEL__enumvalues = { + 0: 'GL1C_PERF_SEL_CYCLE', + 1: 'GL1C_PERF_SEL_BUSY', + 2: 'GL1C_PERF_SEL_STARVE', + 3: 'GL1C_PERF_SEL_ARB_RET_LEVEL', + 4: 'GL1C_PERF_SEL_GL2_REQ_READ', + 5: 'GL1C_PERF_SEL_GL2_REQ_READ_128B', + 6: 'GL1C_PERF_SEL_GL2_REQ_READ_32B', + 7: 'GL1C_PERF_SEL_GL2_REQ_READ_64B', + 8: 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', + 9: 'GL1C_PERF_SEL_GL2_REQ_WRITE', + 10: 'GL1C_PERF_SEL_GL2_REQ_WRITE_32B', + 11: 'GL1C_PERF_SEL_GL2_REQ_WRITE_64B', + 12: 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', + 13: 'GL1C_PERF_SEL_GL2_REQ_PREFETCH', + 14: 'GL1C_PERF_SEL_REQ', + 15: 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', + 16: 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 17: 'GL1C_PERF_SEL_REQ_SHADER_INV', + 18: 'GL1C_PERF_SEL_REQ_MISS', + 19: 'GL1C_PERF_SEL_REQ_NOP_ACK', + 20: 'GL1C_PERF_SEL_REQ_NOP_RTN0', + 21: 'GL1C_PERF_SEL_REQ_READ', + 22: 'GL1C_PERF_SEL_REQ_READ_128B', + 23: 'GL1C_PERF_SEL_REQ_READ_32B', + 24: 'GL1C_PERF_SEL_REQ_READ_64B', + 25: 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT', + 26: 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU', + 27: 'GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT', + 28: 'GL1C_PERF_SEL_REQ_WRITE', + 29: 'GL1C_PERF_SEL_REQ_WRITE_32B', + 30: 'GL1C_PERF_SEL_REQ_WRITE_64B', + 31: 'GL1C_PERF_SEL_STALL_GL2_GL1', + 32: 'GL1C_PERF_SEL_STALL_LFIFO_FULL', + 33: 'GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC', + 34: 'GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE', + 35: 'GL1C_PERF_SEL_STALL_GCR_INV', + 36: 'GL1C_PERF_SEL_STALL_VM', + 37: 'GL1C_PERF_SEL_REQ_CLIENT0', + 38: 'GL1C_PERF_SEL_REQ_CLIENT1', + 39: 'GL1C_PERF_SEL_REQ_CLIENT2', + 40: 'GL1C_PERF_SEL_REQ_CLIENT3', + 41: 'GL1C_PERF_SEL_REQ_CLIENT4', + 42: 'GL1C_PERF_SEL_REQ_CLIENT5', + 43: 'GL1C_PERF_SEL_REQ_CLIENT6', + 44: 'GL1C_PERF_SEL_REQ_CLIENT7', + 45: 'GL1C_PERF_SEL_REQ_CLIENT8', + 46: 'GL1C_PERF_SEL_REQ_CLIENT9', + 47: 'GL1C_PERF_SEL_REQ_CLIENT10', + 48: 'GL1C_PERF_SEL_REQ_CLIENT11', + 49: 'GL1C_PERF_SEL_REQ_CLIENT12', + 50: 'GL1C_PERF_SEL_REQ_CLIENT13', + 51: 'GL1C_PERF_SEL_REQ_CLIENT14', + 52: 'GL1C_PERF_SEL_REQ_CLIENT15', + 53: 'GL1C_PERF_SEL_REQ_CLIENT16', + 54: 'GL1C_PERF_SEL_REQ_CLIENT17', + 55: 'GL1C_PERF_SEL_REQ_CLIENT18', + 56: 'GL1C_PERF_SEL_REQ_CLIENT19', + 57: 'GL1C_PERF_SEL_REQ_CLIENT20', + 58: 'GL1C_PERF_SEL_REQ_CLIENT21', + 59: 'GL1C_PERF_SEL_REQ_CLIENT22', + 60: 'GL1C_PERF_SEL_REQ_CLIENT23', + 61: 'GL1C_PERF_SEL_REQ_CLIENT24', + 62: 'GL1C_PERF_SEL_REQ_CLIENT25', + 63: 'GL1C_PERF_SEL_REQ_CLIENT26', + 64: 'GL1C_PERF_SEL_REQ_CLIENT27', + 65: 'GL1C_PERF_SEL_UTCL0_REQUEST', + 66: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', + 67: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', + 68: 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', + 69: 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', + 70: 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', + 71: 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 72: 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 73: 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 74: 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 75: 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', + 76: 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 77: 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', + 78: 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', + 79: 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', + 80: 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', + 81: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', + 82: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', + 83: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', +} +GL1C_PERF_SEL_CYCLE = 0 +GL1C_PERF_SEL_BUSY = 1 +GL1C_PERF_SEL_STARVE = 2 +GL1C_PERF_SEL_ARB_RET_LEVEL = 3 +GL1C_PERF_SEL_GL2_REQ_READ = 4 +GL1C_PERF_SEL_GL2_REQ_READ_128B = 5 +GL1C_PERF_SEL_GL2_REQ_READ_32B = 6 +GL1C_PERF_SEL_GL2_REQ_READ_64B = 7 +GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 8 +GL1C_PERF_SEL_GL2_REQ_WRITE = 9 +GL1C_PERF_SEL_GL2_REQ_WRITE_32B = 10 +GL1C_PERF_SEL_GL2_REQ_WRITE_64B = 11 +GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 12 +GL1C_PERF_SEL_GL2_REQ_PREFETCH = 13 +GL1C_PERF_SEL_REQ = 14 +GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 15 +GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 16 +GL1C_PERF_SEL_REQ_SHADER_INV = 17 +GL1C_PERF_SEL_REQ_MISS = 18 +GL1C_PERF_SEL_REQ_NOP_ACK = 19 +GL1C_PERF_SEL_REQ_NOP_RTN0 = 20 +GL1C_PERF_SEL_REQ_READ = 21 +GL1C_PERF_SEL_REQ_READ_128B = 22 +GL1C_PERF_SEL_REQ_READ_32B = 23 +GL1C_PERF_SEL_REQ_READ_64B = 24 +GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT = 25 +GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU = 26 +GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT = 27 +GL1C_PERF_SEL_REQ_WRITE = 28 +GL1C_PERF_SEL_REQ_WRITE_32B = 29 +GL1C_PERF_SEL_REQ_WRITE_64B = 30 +GL1C_PERF_SEL_STALL_GL2_GL1 = 31 +GL1C_PERF_SEL_STALL_LFIFO_FULL = 32 +GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC = 33 +GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE = 34 +GL1C_PERF_SEL_STALL_GCR_INV = 35 +GL1C_PERF_SEL_STALL_VM = 36 +GL1C_PERF_SEL_REQ_CLIENT0 = 37 +GL1C_PERF_SEL_REQ_CLIENT1 = 38 +GL1C_PERF_SEL_REQ_CLIENT2 = 39 +GL1C_PERF_SEL_REQ_CLIENT3 = 40 +GL1C_PERF_SEL_REQ_CLIENT4 = 41 +GL1C_PERF_SEL_REQ_CLIENT5 = 42 +GL1C_PERF_SEL_REQ_CLIENT6 = 43 +GL1C_PERF_SEL_REQ_CLIENT7 = 44 +GL1C_PERF_SEL_REQ_CLIENT8 = 45 +GL1C_PERF_SEL_REQ_CLIENT9 = 46 +GL1C_PERF_SEL_REQ_CLIENT10 = 47 +GL1C_PERF_SEL_REQ_CLIENT11 = 48 +GL1C_PERF_SEL_REQ_CLIENT12 = 49 +GL1C_PERF_SEL_REQ_CLIENT13 = 50 +GL1C_PERF_SEL_REQ_CLIENT14 = 51 +GL1C_PERF_SEL_REQ_CLIENT15 = 52 +GL1C_PERF_SEL_REQ_CLIENT16 = 53 +GL1C_PERF_SEL_REQ_CLIENT17 = 54 +GL1C_PERF_SEL_REQ_CLIENT18 = 55 +GL1C_PERF_SEL_REQ_CLIENT19 = 56 +GL1C_PERF_SEL_REQ_CLIENT20 = 57 +GL1C_PERF_SEL_REQ_CLIENT21 = 58 +GL1C_PERF_SEL_REQ_CLIENT22 = 59 +GL1C_PERF_SEL_REQ_CLIENT23 = 60 +GL1C_PERF_SEL_REQ_CLIENT24 = 61 +GL1C_PERF_SEL_REQ_CLIENT25 = 62 +GL1C_PERF_SEL_REQ_CLIENT26 = 63 +GL1C_PERF_SEL_REQ_CLIENT27 = 64 +GL1C_PERF_SEL_UTCL0_REQUEST = 65 +GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 66 +GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 67 +GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 68 +GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 69 +GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 70 +GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 71 +GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 72 +GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 73 +GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 74 +GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 75 +GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 76 +GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 77 +GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 78 +GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 79 +GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 80 +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 81 +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 82 +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 83 +GL1C_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1H_REQ_PERF_SEL' +GL1H_REQ_PERF_SEL__enumvalues = { + 0: 'GL1H_REQ_PERF_SEL_BUSY', + 1: 'GL1H_REQ_PERF_SEL_STALL_GL1_0', + 2: 'GL1H_REQ_PERF_SEL_STALL_GL1_1', + 3: 'GL1H_REQ_PERF_SEL_REQUEST_GL1_0', + 4: 'GL1H_REQ_PERF_SEL_REQUEST_GL1_1', + 5: 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_0', + 6: 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_1', + 7: 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0', + 8: 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1', + 9: 'GL1H_REQ_PERF_SEL_ARB_REQUESTS', + 10: 'GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL', + 11: 'GL1H_REQ_PERF_SEL_CYCLE', +} +GL1H_REQ_PERF_SEL_BUSY = 0 +GL1H_REQ_PERF_SEL_STALL_GL1_0 = 1 +GL1H_REQ_PERF_SEL_STALL_GL1_1 = 2 +GL1H_REQ_PERF_SEL_REQUEST_GL1_0 = 3 +GL1H_REQ_PERF_SEL_REQUEST_GL1_1 = 4 +GL1H_REQ_PERF_SEL_WDS_32B_GL1_0 = 5 +GL1H_REQ_PERF_SEL_WDS_32B_GL1_1 = 6 +GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0 = 7 +GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1 = 8 +GL1H_REQ_PERF_SEL_ARB_REQUESTS = 9 +GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL = 10 +GL1H_REQ_PERF_SEL_CYCLE = 11 +GL1H_REQ_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TA_PERFCOUNT_SEL' +TA_PERFCOUNT_SEL__enumvalues = { + 0: 'TA_PERF_SEL_NULL', + 1: 'TA_PERF_SEL_image_sampler_has_offset_instructions', + 2: 'TA_PERF_SEL_image_sampler_has_bias_instructions', + 3: 'TA_PERF_SEL_image_sampler_has_reference_instructions', + 4: 'TA_PERF_SEL_image_sampler_has_ds_instructions', + 5: 'TA_PERF_SEL_image_sampler_has_dt_instructions', + 6: 'TA_PERF_SEL_image_sampler_has_dr_instructions', + 7: 'TA_PERF_SEL_gradient_busy', + 8: 'TA_PERF_SEL_gradient_fifo_busy', + 9: 'TA_PERF_SEL_lod_busy', + 10: 'TA_PERF_SEL_lod_fifo_busy', + 11: 'TA_PERF_SEL_addresser_busy', + 12: 'TA_PERF_SEL_addresser_fifo_busy', + 13: 'TA_PERF_SEL_aligner_busy', + 14: 'TA_PERF_SEL_write_path_busy', + 15: 'TA_PERF_SEL_ta_busy', + 16: 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', + 17: 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', + 18: 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', + 19: 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', + 20: 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', + 21: 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', + 22: 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', + 23: 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', + 24: 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', + 25: 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', + 26: 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', + 27: 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', + 28: 'TA_PERF_SEL_image_sampler_has_t_instructions', + 29: 'TA_PERF_SEL_image_sampler_has_r_instructions', + 30: 'TA_PERF_SEL_image_sampler_has_q_instructions', + 32: 'TA_PERF_SEL_total_wavefronts', + 33: 'TA_PERF_SEL_gradient_cycles', + 34: 'TA_PERF_SEL_walker_cycles', + 35: 'TA_PERF_SEL_aligner_cycles', + 36: 'TA_PERF_SEL_image_wavefronts', + 37: 'TA_PERF_SEL_image_read_wavefronts', + 38: 'TA_PERF_SEL_image_store_wavefronts', + 39: 'TA_PERF_SEL_image_atomic_wavefronts', + 40: 'TA_PERF_SEL_image_sampler_total_cycles', + 41: 'TA_PERF_SEL_image_nosampler_total_cycles', + 42: 'TA_PERF_SEL_flat_total_cycles', + 43: 'TA_PERF_SEL_bvh_total_cycles', + 44: 'TA_PERF_SEL_buffer_wavefronts', + 45: 'TA_PERF_SEL_buffer_load_wavefronts', + 46: 'TA_PERF_SEL_buffer_store_wavefronts', + 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', + 49: 'TA_PERF_SEL_buffer_total_cycles', + 50: 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', + 51: 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', + 52: 'TA_PERF_SEL_buffer_has_index_instructions', + 53: 'TA_PERF_SEL_buffer_has_offset_instructions', + 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 56: 'TA_PERF_SEL_image_sampler_wavefronts', + 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 58: 'TA_PERF_SEL_addresser_stalled_cycles', + 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 60: 'TA_PERF_SEL_aniso_stalled_cycles', + 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 62: 'TA_PERF_SEL_deriv_stalled_cycles', + 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 64: 'TA_PERF_SEL_color_1_cycle_quads', + 65: 'TA_PERF_SEL_color_2_cycle_quads', + 66: 'TA_PERF_SEL_color_3_cycle_quads', + 68: 'TA_PERF_SEL_mip_1_cycle_quads', + 69: 'TA_PERF_SEL_mip_2_cycle_quads', + 70: 'TA_PERF_SEL_vol_1_cycle_quads', + 71: 'TA_PERF_SEL_vol_2_cycle_quads', + 72: 'TA_PERF_SEL_sampler_op_quads', + 73: 'TA_PERF_SEL_mipmap_lod_0_samples', + 74: 'TA_PERF_SEL_mipmap_lod_1_samples', + 75: 'TA_PERF_SEL_mipmap_lod_2_samples', + 76: 'TA_PERF_SEL_mipmap_lod_3_samples', + 77: 'TA_PERF_SEL_mipmap_lod_4_samples', + 78: 'TA_PERF_SEL_mipmap_lod_5_samples', + 79: 'TA_PERF_SEL_mipmap_lod_6_samples', + 80: 'TA_PERF_SEL_mipmap_lod_7_samples', + 81: 'TA_PERF_SEL_mipmap_lod_8_samples', + 82: 'TA_PERF_SEL_mipmap_lod_9_samples', + 83: 'TA_PERF_SEL_mipmap_lod_10_samples', + 84: 'TA_PERF_SEL_mipmap_lod_11_samples', + 85: 'TA_PERF_SEL_mipmap_lod_12_samples', + 86: 'TA_PERF_SEL_mipmap_lod_13_samples', + 87: 'TA_PERF_SEL_mipmap_lod_14_samples', + 88: 'TA_PERF_SEL_mipmap_invalid_samples', + 89: 'TA_PERF_SEL_aniso_1_cycle_quads', + 90: 'TA_PERF_SEL_aniso_2_cycle_quads', + 91: 'TA_PERF_SEL_aniso_4_cycle_quads', + 92: 'TA_PERF_SEL_aniso_6_cycle_quads', + 93: 'TA_PERF_SEL_aniso_8_cycle_quads', + 94: 'TA_PERF_SEL_aniso_10_cycle_quads', + 95: 'TA_PERF_SEL_aniso_12_cycle_quads', + 96: 'TA_PERF_SEL_aniso_14_cycle_quads', + 97: 'TA_PERF_SEL_aniso_16_cycle_quads', + 98: 'TA_PERF_SEL_store_write_data_input_cycles', + 99: 'TA_PERF_SEL_store_write_data_output_cycles', + 100: 'TA_PERF_SEL_flat_wavefronts', + 101: 'TA_PERF_SEL_flat_load_wavefronts', + 102: 'TA_PERF_SEL_flat_store_wavefronts', + 103: 'TA_PERF_SEL_flat_atomic_wavefronts', + 104: 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', + 105: 'TA_PERF_SEL_register_clk_valid_cycles', + 106: 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', + 107: 'TA_PERF_SEL_harvestable_clk_enabled_cycles', + 108: 'TA_PERF_SEL_harvestable_register_clk_enabled_cycles', + 109: 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', + 110: 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', + 114: 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', + 115: 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', + 116: 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', + 117: 'TA_PERF_SEL_store_has_x_instructions', + 118: 'TA_PERF_SEL_store_has_y_instructions', + 119: 'TA_PERF_SEL_store_has_z_instructions', + 120: 'TA_PERF_SEL_store_has_w_instructions', + 121: 'TA_PERF_SEL_image_nosampler_has_t_instructions', + 122: 'TA_PERF_SEL_image_nosampler_has_r_instructions', + 123: 'TA_PERF_SEL_image_nosampler_has_q_instructions', + 124: 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', + 125: 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', + 126: 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', + 127: 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', + 128: 'TA_PERF_SEL_in_busy', + 129: 'TA_PERF_SEL_in_fifos_busy', + 130: 'TA_PERF_SEL_in_cfifo_busy', + 131: 'TA_PERF_SEL_in_qfifo_busy', + 132: 'TA_PERF_SEL_in_wfifo_busy', + 133: 'TA_PERF_SEL_in_rfifo_busy', + 134: 'TA_PERF_SEL_bf_busy', + 135: 'TA_PERF_SEL_ns_busy', + 136: 'TA_PERF_SEL_smp_busy_ns_idle', + 137: 'TA_PERF_SEL_smp_idle_ns_busy', + 144: 'TA_PERF_SEL_vmemcmd_cycles', + 145: 'TA_PERF_SEL_vmemreq_cycles', + 146: 'TA_PERF_SEL_in_waiting_on_req_cycles', + 150: 'TA_PERF_SEL_in_addr_cycles', + 151: 'TA_PERF_SEL_in_data_cycles', + 154: 'TA_PERF_SEL_latency_ram_weights_written_cycles', + 155: 'TA_PERF_SEL_latency_ram_ws_required_quads', + 156: 'TA_PERF_SEL_latency_ram_whv_required_quads', + 157: 'TA_PERF_SEL_latency_ram_ws_required_instructions', + 158: 'TA_PERF_SEL_latency_ram_whv_required_instructions', + 159: 'TA_PERF_SEL_latency_ram_ref_required_instructions', + 160: 'TA_PERF_SEL_point_sampled_quads', + 162: 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', + 163: 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', + 164: 'TA_PERF_SEL_atomic_write_data_input_cycles', + 165: 'TA_PERF_SEL_atomic_write_data_output_cycles', + 173: 'TA_PERF_SEL_num_unlit_nodes_ta_opt', + 174: 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', + 175: 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', + 176: 'TA_PERF_SEL_num_of_bvh_valid_first_tri', + 177: 'TA_PERF_SEL_num_of_bvh_valid_second_tri', + 178: 'TA_PERF_SEL_num_of_bvh_valid_third_tri', + 179: 'TA_PERF_SEL_num_of_bvh_valid_fourth_tri', + 180: 'TA_PERF_SEL_num_of_bvh_valid_fp16_box', + 181: 'TA_PERF_SEL_num_of_bvh_valid_fp32_box', + 182: 'TA_PERF_SEL_num_of_bvh_invalidated_first_tri', + 183: 'TA_PERF_SEL_num_of_bvh_invalidated_second_tri', + 184: 'TA_PERF_SEL_num_of_bvh_invalidated_third_tri', + 185: 'TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri', + 186: 'TA_PERF_SEL_num_of_bvh_invalidated_fp16_box', + 187: 'TA_PERF_SEL_num_of_bvh_invalidated_fp32_box', + 188: 'TA_PERF_SEL_image_bvh_8_input_vgpr_instructions', + 189: 'TA_PERF_SEL_image_bvh_9_input_vgpr_instructions', + 190: 'TA_PERF_SEL_image_bvh_11_input_vgpr_instructions', + 191: 'TA_PERF_SEL_image_bvh_12_input_vgpr_instructions', + 192: 'TA_PERF_SEL_image_sampler_1_op_burst', + 193: 'TA_PERF_SEL_image_sampler_2to3_op_burst', + 194: 'TA_PERF_SEL_image_sampler_4to7_op_burst', + 195: 'TA_PERF_SEL_image_sampler_ge8_op_burst', + 196: 'TA_PERF_SEL_image_linked_1_op_burst', + 197: 'TA_PERF_SEL_image_linked_2to3_op_burst', + 198: 'TA_PERF_SEL_image_linked_4to7_op_burst', + 199: 'TA_PERF_SEL_image_linked_ge8_op_burst', + 200: 'TA_PERF_SEL_image_bvh_1_op_burst', + 201: 'TA_PERF_SEL_image_bvh_2to3_op_burst', + 202: 'TA_PERF_SEL_image_bvh_4to7_op_burst', + 203: 'TA_PERF_SEL_image_bvh_ge8_op_burst', + 204: 'TA_PERF_SEL_image_nosampler_1_op_burst', + 205: 'TA_PERF_SEL_image_nosampler_2to3_op_burst', + 206: 'TA_PERF_SEL_image_nosampler_4to31_op_burst', + 207: 'TA_PERF_SEL_image_nosampler_ge32_op_burst', + 208: 'TA_PERF_SEL_buffer_flat_1_op_burst', + 209: 'TA_PERF_SEL_buffer_flat_2to3_op_burst', + 210: 'TA_PERF_SEL_buffer_flat_4to31_op_burst', + 211: 'TA_PERF_SEL_buffer_flat_ge32_op_burst', + 212: 'TA_PERF_SEL_write_1_op_burst', + 213: 'TA_PERF_SEL_write_2to3_op_burst', + 214: 'TA_PERF_SEL_write_4to31_op_burst', + 215: 'TA_PERF_SEL_write_ge32_op_burst', + 216: 'TA_PERF_SEL_ibubble_1_cycle_burst', + 217: 'TA_PERF_SEL_ibubble_2to3_cycle_burst', + 218: 'TA_PERF_SEL_ibubble_4to15_cycle_burst', + 219: 'TA_PERF_SEL_ibubble_16to31_cycle_burst', + 220: 'TA_PERF_SEL_ibubble_32to63_cycle_burst', + 221: 'TA_PERF_SEL_ibubble_ge64_cycle_burst', + 224: 'TA_PERF_SEL_sampler_clk_valid_cycles', + 225: 'TA_PERF_SEL_nonsampler_clk_valid_cycles', + 226: 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', + 227: 'TA_PERF_SEL_write_data_clk_valid_cycles', + 228: 'TA_PERF_SEL_gradient_clk_valid_cycles', + 229: 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', + 230: 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', + 231: 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', + 232: 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', + 233: 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', + 234: 'TA_PERF_SEL_aligner_clk_valid_cycles', + 235: 'TA_PERF_SEL_tcreq_clk_valid_cycles', +} +TA_PERF_SEL_NULL = 0 +TA_PERF_SEL_image_sampler_has_offset_instructions = 1 +TA_PERF_SEL_image_sampler_has_bias_instructions = 2 +TA_PERF_SEL_image_sampler_has_reference_instructions = 3 +TA_PERF_SEL_image_sampler_has_ds_instructions = 4 +TA_PERF_SEL_image_sampler_has_dt_instructions = 5 +TA_PERF_SEL_image_sampler_has_dr_instructions = 6 +TA_PERF_SEL_gradient_busy = 7 +TA_PERF_SEL_gradient_fifo_busy = 8 +TA_PERF_SEL_lod_busy = 9 +TA_PERF_SEL_lod_fifo_busy = 10 +TA_PERF_SEL_addresser_busy = 11 +TA_PERF_SEL_addresser_fifo_busy = 12 +TA_PERF_SEL_aligner_busy = 13 +TA_PERF_SEL_write_path_busy = 14 +TA_PERF_SEL_ta_busy = 15 +TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 16 +TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 17 +TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 18 +TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 19 +TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 20 +TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 21 +TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 22 +TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 23 +TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 24 +TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 25 +TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 26 +TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 27 +TA_PERF_SEL_image_sampler_has_t_instructions = 28 +TA_PERF_SEL_image_sampler_has_r_instructions = 29 +TA_PERF_SEL_image_sampler_has_q_instructions = 30 +TA_PERF_SEL_total_wavefronts = 32 +TA_PERF_SEL_gradient_cycles = 33 +TA_PERF_SEL_walker_cycles = 34 +TA_PERF_SEL_aligner_cycles = 35 +TA_PERF_SEL_image_wavefronts = 36 +TA_PERF_SEL_image_read_wavefronts = 37 +TA_PERF_SEL_image_store_wavefronts = 38 +TA_PERF_SEL_image_atomic_wavefronts = 39 +TA_PERF_SEL_image_sampler_total_cycles = 40 +TA_PERF_SEL_image_nosampler_total_cycles = 41 +TA_PERF_SEL_flat_total_cycles = 42 +TA_PERF_SEL_bvh_total_cycles = 43 +TA_PERF_SEL_buffer_wavefronts = 44 +TA_PERF_SEL_buffer_load_wavefronts = 45 +TA_PERF_SEL_buffer_store_wavefronts = 46 +TA_PERF_SEL_buffer_atomic_wavefronts = 47 +TA_PERF_SEL_buffer_total_cycles = 49 +TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 50 +TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 51 +TA_PERF_SEL_buffer_has_index_instructions = 52 +TA_PERF_SEL_buffer_has_offset_instructions = 53 +TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 +TA_PERF_SEL_addr_stalled_by_td_cycles = 55 +TA_PERF_SEL_image_sampler_wavefronts = 56 +TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 +TA_PERF_SEL_addresser_stalled_cycles = 58 +TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 +TA_PERF_SEL_aniso_stalled_cycles = 60 +TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 +TA_PERF_SEL_deriv_stalled_cycles = 62 +TA_PERF_SEL_aniso_gt1_cycle_quads = 63 +TA_PERF_SEL_color_1_cycle_quads = 64 +TA_PERF_SEL_color_2_cycle_quads = 65 +TA_PERF_SEL_color_3_cycle_quads = 66 +TA_PERF_SEL_mip_1_cycle_quads = 68 +TA_PERF_SEL_mip_2_cycle_quads = 69 +TA_PERF_SEL_vol_1_cycle_quads = 70 +TA_PERF_SEL_vol_2_cycle_quads = 71 +TA_PERF_SEL_sampler_op_quads = 72 +TA_PERF_SEL_mipmap_lod_0_samples = 73 +TA_PERF_SEL_mipmap_lod_1_samples = 74 +TA_PERF_SEL_mipmap_lod_2_samples = 75 +TA_PERF_SEL_mipmap_lod_3_samples = 76 +TA_PERF_SEL_mipmap_lod_4_samples = 77 +TA_PERF_SEL_mipmap_lod_5_samples = 78 +TA_PERF_SEL_mipmap_lod_6_samples = 79 +TA_PERF_SEL_mipmap_lod_7_samples = 80 +TA_PERF_SEL_mipmap_lod_8_samples = 81 +TA_PERF_SEL_mipmap_lod_9_samples = 82 +TA_PERF_SEL_mipmap_lod_10_samples = 83 +TA_PERF_SEL_mipmap_lod_11_samples = 84 +TA_PERF_SEL_mipmap_lod_12_samples = 85 +TA_PERF_SEL_mipmap_lod_13_samples = 86 +TA_PERF_SEL_mipmap_lod_14_samples = 87 +TA_PERF_SEL_mipmap_invalid_samples = 88 +TA_PERF_SEL_aniso_1_cycle_quads = 89 +TA_PERF_SEL_aniso_2_cycle_quads = 90 +TA_PERF_SEL_aniso_4_cycle_quads = 91 +TA_PERF_SEL_aniso_6_cycle_quads = 92 +TA_PERF_SEL_aniso_8_cycle_quads = 93 +TA_PERF_SEL_aniso_10_cycle_quads = 94 +TA_PERF_SEL_aniso_12_cycle_quads = 95 +TA_PERF_SEL_aniso_14_cycle_quads = 96 +TA_PERF_SEL_aniso_16_cycle_quads = 97 +TA_PERF_SEL_store_write_data_input_cycles = 98 +TA_PERF_SEL_store_write_data_output_cycles = 99 +TA_PERF_SEL_flat_wavefronts = 100 +TA_PERF_SEL_flat_load_wavefronts = 101 +TA_PERF_SEL_flat_store_wavefronts = 102 +TA_PERF_SEL_flat_atomic_wavefronts = 103 +TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 104 +TA_PERF_SEL_register_clk_valid_cycles = 105 +TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 106 +TA_PERF_SEL_harvestable_clk_enabled_cycles = 107 +TA_PERF_SEL_harvestable_register_clk_enabled_cycles = 108 +TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 109 +TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 110 +TA_PERF_SEL_store_2_write_data_vgpr_instructions = 114 +TA_PERF_SEL_store_3_write_data_vgpr_instructions = 115 +TA_PERF_SEL_store_4_write_data_vgpr_instructions = 116 +TA_PERF_SEL_store_has_x_instructions = 117 +TA_PERF_SEL_store_has_y_instructions = 118 +TA_PERF_SEL_store_has_z_instructions = 119 +TA_PERF_SEL_store_has_w_instructions = 120 +TA_PERF_SEL_image_nosampler_has_t_instructions = 121 +TA_PERF_SEL_image_nosampler_has_r_instructions = 122 +TA_PERF_SEL_image_nosampler_has_q_instructions = 123 +TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 124 +TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 125 +TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 126 +TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 127 +TA_PERF_SEL_in_busy = 128 +TA_PERF_SEL_in_fifos_busy = 129 +TA_PERF_SEL_in_cfifo_busy = 130 +TA_PERF_SEL_in_qfifo_busy = 131 +TA_PERF_SEL_in_wfifo_busy = 132 +TA_PERF_SEL_in_rfifo_busy = 133 +TA_PERF_SEL_bf_busy = 134 +TA_PERF_SEL_ns_busy = 135 +TA_PERF_SEL_smp_busy_ns_idle = 136 +TA_PERF_SEL_smp_idle_ns_busy = 137 +TA_PERF_SEL_vmemcmd_cycles = 144 +TA_PERF_SEL_vmemreq_cycles = 145 +TA_PERF_SEL_in_waiting_on_req_cycles = 146 +TA_PERF_SEL_in_addr_cycles = 150 +TA_PERF_SEL_in_data_cycles = 151 +TA_PERF_SEL_latency_ram_weights_written_cycles = 154 +TA_PERF_SEL_latency_ram_ws_required_quads = 155 +TA_PERF_SEL_latency_ram_whv_required_quads = 156 +TA_PERF_SEL_latency_ram_ws_required_instructions = 157 +TA_PERF_SEL_latency_ram_whv_required_instructions = 158 +TA_PERF_SEL_latency_ram_ref_required_instructions = 159 +TA_PERF_SEL_point_sampled_quads = 160 +TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 162 +TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 163 +TA_PERF_SEL_atomic_write_data_input_cycles = 164 +TA_PERF_SEL_atomic_write_data_output_cycles = 165 +TA_PERF_SEL_num_unlit_nodes_ta_opt = 173 +TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 174 +TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 175 +TA_PERF_SEL_num_of_bvh_valid_first_tri = 176 +TA_PERF_SEL_num_of_bvh_valid_second_tri = 177 +TA_PERF_SEL_num_of_bvh_valid_third_tri = 178 +TA_PERF_SEL_num_of_bvh_valid_fourth_tri = 179 +TA_PERF_SEL_num_of_bvh_valid_fp16_box = 180 +TA_PERF_SEL_num_of_bvh_valid_fp32_box = 181 +TA_PERF_SEL_num_of_bvh_invalidated_first_tri = 182 +TA_PERF_SEL_num_of_bvh_invalidated_second_tri = 183 +TA_PERF_SEL_num_of_bvh_invalidated_third_tri = 184 +TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri = 185 +TA_PERF_SEL_num_of_bvh_invalidated_fp16_box = 186 +TA_PERF_SEL_num_of_bvh_invalidated_fp32_box = 187 +TA_PERF_SEL_image_bvh_8_input_vgpr_instructions = 188 +TA_PERF_SEL_image_bvh_9_input_vgpr_instructions = 189 +TA_PERF_SEL_image_bvh_11_input_vgpr_instructions = 190 +TA_PERF_SEL_image_bvh_12_input_vgpr_instructions = 191 +TA_PERF_SEL_image_sampler_1_op_burst = 192 +TA_PERF_SEL_image_sampler_2to3_op_burst = 193 +TA_PERF_SEL_image_sampler_4to7_op_burst = 194 +TA_PERF_SEL_image_sampler_ge8_op_burst = 195 +TA_PERF_SEL_image_linked_1_op_burst = 196 +TA_PERF_SEL_image_linked_2to3_op_burst = 197 +TA_PERF_SEL_image_linked_4to7_op_burst = 198 +TA_PERF_SEL_image_linked_ge8_op_burst = 199 +TA_PERF_SEL_image_bvh_1_op_burst = 200 +TA_PERF_SEL_image_bvh_2to3_op_burst = 201 +TA_PERF_SEL_image_bvh_4to7_op_burst = 202 +TA_PERF_SEL_image_bvh_ge8_op_burst = 203 +TA_PERF_SEL_image_nosampler_1_op_burst = 204 +TA_PERF_SEL_image_nosampler_2to3_op_burst = 205 +TA_PERF_SEL_image_nosampler_4to31_op_burst = 206 +TA_PERF_SEL_image_nosampler_ge32_op_burst = 207 +TA_PERF_SEL_buffer_flat_1_op_burst = 208 +TA_PERF_SEL_buffer_flat_2to3_op_burst = 209 +TA_PERF_SEL_buffer_flat_4to31_op_burst = 210 +TA_PERF_SEL_buffer_flat_ge32_op_burst = 211 +TA_PERF_SEL_write_1_op_burst = 212 +TA_PERF_SEL_write_2to3_op_burst = 213 +TA_PERF_SEL_write_4to31_op_burst = 214 +TA_PERF_SEL_write_ge32_op_burst = 215 +TA_PERF_SEL_ibubble_1_cycle_burst = 216 +TA_PERF_SEL_ibubble_2to3_cycle_burst = 217 +TA_PERF_SEL_ibubble_4to15_cycle_burst = 218 +TA_PERF_SEL_ibubble_16to31_cycle_burst = 219 +TA_PERF_SEL_ibubble_32to63_cycle_burst = 220 +TA_PERF_SEL_ibubble_ge64_cycle_burst = 221 +TA_PERF_SEL_sampler_clk_valid_cycles = 224 +TA_PERF_SEL_nonsampler_clk_valid_cycles = 225 +TA_PERF_SEL_buffer_flat_clk_valid_cycles = 226 +TA_PERF_SEL_write_data_clk_valid_cycles = 227 +TA_PERF_SEL_gradient_clk_valid_cycles = 228 +TA_PERF_SEL_lod_aniso_clk_valid_cycles = 229 +TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 230 +TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 231 +TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 232 +TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 233 +TA_PERF_SEL_aligner_clk_valid_cycles = 234 +TA_PERF_SEL_tcreq_clk_valid_cycles = 235 +TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_BC_SWIZZLE' +TEX_BC_SWIZZLE__enumvalues = { + 0: 'TEX_BC_Swizzle_XYZW', + 1: 'TEX_BC_Swizzle_XWYZ', + 2: 'TEX_BC_Swizzle_WZYX', + 3: 'TEX_BC_Swizzle_WXYZ', + 4: 'TEX_BC_Swizzle_ZYXW', + 5: 'TEX_BC_Swizzle_YXWZ', +} +TEX_BC_Swizzle_XYZW = 0 +TEX_BC_Swizzle_XWYZ = 1 +TEX_BC_Swizzle_WZYX = 2 +TEX_BC_Swizzle_WXYZ = 3 +TEX_BC_Swizzle_ZYXW = 4 +TEX_BC_Swizzle_YXWZ = 5 +TEX_BC_SWIZZLE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_BORDER_COLOR_TYPE' +TEX_BORDER_COLOR_TYPE__enumvalues = { + 0: 'TEX_BorderColor_TransparentBlack', + 1: 'TEX_BorderColor_OpaqueBlack', + 2: 'TEX_BorderColor_OpaqueWhite', + 3: 'TEX_BorderColor_Register', +} +TEX_BorderColor_TransparentBlack = 0 +TEX_BorderColor_OpaqueBlack = 1 +TEX_BorderColor_OpaqueWhite = 2 +TEX_BorderColor_Register = 3 +TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CHROMA_KEY' +TEX_CHROMA_KEY__enumvalues = { + 0: 'TEX_ChromaKey_Disabled', + 1: 'TEX_ChromaKey_Kill', + 2: 'TEX_ChromaKey_Blend', + 3: 'TEX_ChromaKey_RESERVED_3', +} +TEX_ChromaKey_Disabled = 0 +TEX_ChromaKey_Kill = 1 +TEX_ChromaKey_Blend = 2 +TEX_ChromaKey_RESERVED_3 = 3 +TEX_CHROMA_KEY = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CLAMP' +TEX_CLAMP__enumvalues = { + 0: 'TEX_Clamp_Repeat', + 1: 'TEX_Clamp_Mirror', + 2: 'TEX_Clamp_ClampToLast', + 3: 'TEX_Clamp_MirrorOnceToLast', + 4: 'TEX_Clamp_ClampHalfToBorder', + 5: 'TEX_Clamp_MirrorOnceHalfToBorder', + 6: 'TEX_Clamp_ClampToBorder', + 7: 'TEX_Clamp_MirrorOnceToBorder', +} +TEX_Clamp_Repeat = 0 +TEX_Clamp_Mirror = 1 +TEX_Clamp_ClampToLast = 2 +TEX_Clamp_MirrorOnceToLast = 3 +TEX_Clamp_ClampHalfToBorder = 4 +TEX_Clamp_MirrorOnceHalfToBorder = 5 +TEX_Clamp_ClampToBorder = 6 +TEX_Clamp_MirrorOnceToBorder = 7 +TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_COORD_TYPE' +TEX_COORD_TYPE__enumvalues = { + 0: 'TEX_CoordType_Unnormalized', + 1: 'TEX_CoordType_Normalized', +} +TEX_CoordType_Unnormalized = 0 +TEX_CoordType_Normalized = 1 +TEX_COORD_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' +TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { + 0: 'TEX_DepthCompareFunction_Never', + 1: 'TEX_DepthCompareFunction_Less', + 2: 'TEX_DepthCompareFunction_Equal', + 3: 'TEX_DepthCompareFunction_LessEqual', + 4: 'TEX_DepthCompareFunction_Greater', + 5: 'TEX_DepthCompareFunction_NotEqual', + 6: 'TEX_DepthCompareFunction_GreaterEqual', + 7: 'TEX_DepthCompareFunction_Always', +} +TEX_DepthCompareFunction_Never = 0 +TEX_DepthCompareFunction_Less = 1 +TEX_DepthCompareFunction_Equal = 2 +TEX_DepthCompareFunction_LessEqual = 3 +TEX_DepthCompareFunction_Greater = 4 +TEX_DepthCompareFunction_NotEqual = 5 +TEX_DepthCompareFunction_GreaterEqual = 6 +TEX_DepthCompareFunction_Always = 7 +TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_FORMAT_COMP' +TEX_FORMAT_COMP__enumvalues = { + 0: 'TEX_FormatComp_Unsigned', + 1: 'TEX_FormatComp_Signed', + 2: 'TEX_FormatComp_UnsignedBiased', + 3: 'TEX_FormatComp_RESERVED_3', +} +TEX_FormatComp_Unsigned = 0 +TEX_FormatComp_Signed = 1 +TEX_FormatComp_UnsignedBiased = 2 +TEX_FormatComp_RESERVED_3 = 3 +TEX_FORMAT_COMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MAX_ANISO_RATIO' +TEX_MAX_ANISO_RATIO__enumvalues = { + 0: 'TEX_MaxAnisoRatio_1to1', + 1: 'TEX_MaxAnisoRatio_2to1', + 2: 'TEX_MaxAnisoRatio_4to1', + 3: 'TEX_MaxAnisoRatio_8to1', + 4: 'TEX_MaxAnisoRatio_16to1', + 5: 'TEX_MaxAnisoRatio_RESERVED_5', + 6: 'TEX_MaxAnisoRatio_RESERVED_6', + 7: 'TEX_MaxAnisoRatio_RESERVED_7', +} +TEX_MaxAnisoRatio_1to1 = 0 +TEX_MaxAnisoRatio_2to1 = 1 +TEX_MaxAnisoRatio_4to1 = 2 +TEX_MaxAnisoRatio_8to1 = 3 +TEX_MaxAnisoRatio_16to1 = 4 +TEX_MaxAnisoRatio_RESERVED_5 = 5 +TEX_MaxAnisoRatio_RESERVED_6 = 6 +TEX_MaxAnisoRatio_RESERVED_7 = 7 +TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MIP_FILTER' +TEX_MIP_FILTER__enumvalues = { + 0: 'TEX_MipFilter_None', + 1: 'TEX_MipFilter_Point', + 2: 'TEX_MipFilter_Linear', + 3: 'TEX_MipFilter_Point_Aniso_Adj', +} +TEX_MipFilter_None = 0 +TEX_MipFilter_Point = 1 +TEX_MipFilter_Linear = 2 +TEX_MipFilter_Point_Aniso_Adj = 3 +TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_REQUEST_SIZE' +TEX_REQUEST_SIZE__enumvalues = { + 0: 'TEX_RequestSize_32B', + 1: 'TEX_RequestSize_64B', + 2: 'TEX_RequestSize_128B', + 3: 'TEX_RequestSize_2X64B', +} +TEX_RequestSize_32B = 0 +TEX_RequestSize_64B = 1 +TEX_RequestSize_128B = 2 +TEX_RequestSize_2X64B = 3 +TEX_REQUEST_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_SAMPLER_TYPE' +TEX_SAMPLER_TYPE__enumvalues = { + 0: 'TEX_SamplerType_Invalid', + 1: 'TEX_SamplerType_Valid', +} +TEX_SamplerType_Invalid = 0 +TEX_SamplerType_Valid = 1 +TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_XY_FILTER' +TEX_XY_FILTER__enumvalues = { + 0: 'TEX_XYFilter_Point', + 1: 'TEX_XYFilter_Linear', + 2: 'TEX_XYFilter_AnisoPoint', + 3: 'TEX_XYFilter_AnisoLinear', +} +TEX_XYFilter_Point = 0 +TEX_XYFilter_Linear = 1 +TEX_XYFilter_AnisoPoint = 2 +TEX_XYFilter_AnisoLinear = 3 +TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_Z_FILTER' +TEX_Z_FILTER__enumvalues = { + 0: 'TEX_ZFilter_None', + 1: 'TEX_ZFilter_Point', + 2: 'TEX_ZFilter_Linear', + 3: 'TEX_ZFilter_RESERVED_3', +} +TEX_ZFilter_None = 0 +TEX_ZFilter_Point = 1 +TEX_ZFilter_Linear = 2 +TEX_ZFilter_RESERVED_3 = 3 +TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_TYPE' +TVX_TYPE__enumvalues = { + 0: 'TVX_Type_InvalidTextureResource', + 1: 'TVX_Type_InvalidVertexBuffer', + 2: 'TVX_Type_ValidTextureResource', + 3: 'TVX_Type_ValidVertexBuffer', +} +TVX_Type_InvalidTextureResource = 0 +TVX_Type_InvalidVertexBuffer = 1 +TVX_Type_ValidTextureResource = 2 +TVX_Type_ValidVertexBuffer = 3 +TVX_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TA_TC_ADDR_MODES' +TA_TC_ADDR_MODES__enumvalues = { + 0: 'TA_TC_ADDR_MODE_DEFAULT', + 1: 'TA_TC_ADDR_MODE_COMP0', + 2: 'TA_TC_ADDR_MODE_COMP1', + 3: 'TA_TC_ADDR_MODE_COMP2', + 4: 'TA_TC_ADDR_MODE_COMP3', + 5: 'TA_TC_ADDR_MODE_UNALIGNED', + 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', +} +TA_TC_ADDR_MODE_DEFAULT = 0 +TA_TC_ADDR_MODE_COMP0 = 1 +TA_TC_ADDR_MODE_COMP1 = 2 +TA_TC_ADDR_MODE_COMP2 = 3 +TA_TC_ADDR_MODE_COMP3 = 4 +TA_TC_ADDR_MODE_UNALIGNED = 5 +TA_TC_ADDR_MODE_BORDER_COLOR = 6 +TA_TC_ADDR_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TA_TC_REQ_MODES' +TA_TC_REQ_MODES__enumvalues = { + 0: 'TA_TC_REQ_MODE_BORDER', + 1: 'TA_TC_REQ_MODE_TEX2', + 2: 'TA_TC_REQ_MODE_TEX1', + 3: 'TA_TC_REQ_MODE_TEX0', + 4: 'TA_TC_REQ_MODE_NORMAL', + 5: 'TA_TC_REQ_MODE_DWORD', + 6: 'TA_TC_REQ_MODE_BYTE', + 7: 'TA_TC_REQ_MODE_BYTE_NV', +} +TA_TC_REQ_MODE_BORDER = 0 +TA_TC_REQ_MODE_TEX2 = 1 +TA_TC_REQ_MODE_TEX1 = 2 +TA_TC_REQ_MODE_TEX0 = 3 +TA_TC_REQ_MODE_NORMAL = 4 +TA_TC_REQ_MODE_DWORD = 5 +TA_TC_REQ_MODE_BYTE = 6 +TA_TC_REQ_MODE_BYTE_NV = 7 +TA_TC_REQ_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_POLICIES' +TCP_CACHE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_POLICY_MISS_LRU', + 1: 'TCP_CACHE_POLICY_MISS_EVICT', + 2: 'TCP_CACHE_POLICY_HIT_LRU', + 3: 'TCP_CACHE_POLICY_HIT_EVICT', +} +TCP_CACHE_POLICY_MISS_LRU = 0 +TCP_CACHE_POLICY_MISS_EVICT = 1 +TCP_CACHE_POLICY_HIT_LRU = 2 +TCP_CACHE_POLICY_HIT_EVICT = 3 +TCP_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_STORE_POLICIES' +TCP_CACHE_STORE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', + 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', +} +TCP_CACHE_STORE_POLICY_WT_LRU = 0 +TCP_CACHE_STORE_POLICY_WT_EVICT = 1 +TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_DATA_SEL' +TCP_DSM_DATA_SEL__enumvalues = { + 0: 'TCP_DSM_DISABLE', + 1: 'TCP_DSM_SEL0', + 2: 'TCP_DSM_SEL1', + 3: 'TCP_DSM_SEL_BOTH', +} +TCP_DSM_DISABLE = 0 +TCP_DSM_SEL0 = 1 +TCP_DSM_SEL1 = 2 +TCP_DSM_SEL_BOTH = 3 +TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_INJECT_SEL' +TCP_DSM_INJECT_SEL__enumvalues = { + 0: 'TCP_DSM_INJECT_SEL0', + 1: 'TCP_DSM_INJECT_SEL1', + 2: 'TCP_DSM_INJECT_SEL2', + 3: 'TCP_DSM_INJECT_SEL3', +} +TCP_DSM_INJECT_SEL0 = 0 +TCP_DSM_INJECT_SEL1 = 1 +TCP_DSM_INJECT_SEL2 = 2 +TCP_DSM_INJECT_SEL3 = 3 +TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_SINGLE_WRITE' +TCP_DSM_SINGLE_WRITE__enumvalues = { + 0: 'TCP_DSM_SINGLE_WRITE_DIS', + 1: 'TCP_DSM_SINGLE_WRITE_EN', +} +TCP_DSM_SINGLE_WRITE_DIS = 0 +TCP_DSM_SINGLE_WRITE_EN = 1 +TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_OPCODE_TYPE' +TCP_OPCODE_TYPE__enumvalues = { + 0: 'TCP_OPCODE_READ', + 1: 'TCP_OPCODE_WRITE', + 2: 'TCP_OPCODE_ATOMIC', + 3: 'TCP_OPCODE_INV', + 4: 'TCP_OPCODE_ATOMIC_CMPSWAP', + 5: 'TCP_OPCODE_SAMPLER', + 6: 'TCP_OPCODE_LOAD', + 7: 'TCP_OPCODE_GATHERH', +} +TCP_OPCODE_READ = 0 +TCP_OPCODE_WRITE = 1 +TCP_OPCODE_ATOMIC = 2 +TCP_OPCODE_INV = 3 +TCP_OPCODE_ATOMIC_CMPSWAP = 4 +TCP_OPCODE_SAMPLER = 5 +TCP_OPCODE_LOAD = 6 +TCP_OPCODE_GATHERH = 7 +TCP_OPCODE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_PERFCOUNT_SELECT' +TCP_PERFCOUNT_SELECT__enumvalues = { + 0: 'TCP_PERF_SEL_GATE_EN1', + 1: 'TCP_PERF_SEL_GATE_EN2', + 2: 'TCP_PERF_SEL_TA_REQ', + 3: 'TCP_PERF_SEL_TA_REQ_STATE_READ', + 4: 'TCP_PERF_SEL_TA_REQ_READ', + 5: 'TCP_PERF_SEL_TA_REQ_WRITE', + 6: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', + 7: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', + 8: 'TCP_PERF_SEL_TA_REQ_GL0_INV', + 9: 'TCP_PERF_SEL_REQ', + 10: 'TCP_PERF_SEL_REQ_READ', + 11: 'TCP_PERF_SEL_REQ_READ_HIT_EVICT', + 12: 'TCP_PERF_SEL_REQ_READ_HIT_LRU', + 13: 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', + 14: 'TCP_PERF_SEL_REQ_WRITE', + 15: 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', + 16: 'TCP_PERF_SEL_REQ_WRITE_MISS_LRU', + 17: 'TCP_PERF_SEL_REQ_NON_READ', + 18: 'TCP_PERF_SEL_REQ_MISS', + 19: 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', + 20: 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', + 21: 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', + 22: 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', + 23: 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', + 24: 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', + 25: 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', + 26: 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', + 27: 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', + 28: 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', + 29: 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', + 30: 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', + 31: 'TCP_PERF_SEL_GL1_REQ_READ', + 32: 'TCP_PERF_SEL_GL1_REQ_READ_128B', + 33: 'TCP_PERF_SEL_GL1_REQ_READ_64B', + 34: 'TCP_PERF_SEL_GL1_REQ_WRITE', + 35: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', + 36: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', + 37: 'TCP_PERF_SEL_GL1_READ_LATENCY', + 38: 'TCP_PERF_SEL_GL1_WRITE_LATENCY', + 39: 'TCP_PERF_SEL_TCP_LATENCY', + 40: 'TCP_PERF_SEL_TCP_TA_REQ_STALL', + 41: 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', + 42: 'TCP_PERF_SEL_DATA_FIFO_STALL', + 43: 'TCP_PERF_SEL_LOD_STALL', + 44: 'TCP_PERF_SEL_POWER_STALL', + 45: 'TCP_PERF_SEL_ALLOC_STALL', + 46: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', + 47: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', + 48: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', + 49: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', + 50: 'TCP_PERF_SEL_LFIFO_STALL', + 51: 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', + 52: 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', + 53: 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', + 54: 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', + 55: 'TCP_PERF_SEL_GL1_PENDING_STALL', + 56: 'TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL', + 57: 'TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL', + 58: 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', + 59: 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', + 60: 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', + 61: 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', + 62: 'TCP_PERF_SEL_TD_TCP_STALL', +} +TCP_PERF_SEL_GATE_EN1 = 0 +TCP_PERF_SEL_GATE_EN2 = 1 +TCP_PERF_SEL_TA_REQ = 2 +TCP_PERF_SEL_TA_REQ_STATE_READ = 3 +TCP_PERF_SEL_TA_REQ_READ = 4 +TCP_PERF_SEL_TA_REQ_WRITE = 5 +TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 6 +TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 7 +TCP_PERF_SEL_TA_REQ_GL0_INV = 8 +TCP_PERF_SEL_REQ = 9 +TCP_PERF_SEL_REQ_READ = 10 +TCP_PERF_SEL_REQ_READ_HIT_EVICT = 11 +TCP_PERF_SEL_REQ_READ_HIT_LRU = 12 +TCP_PERF_SEL_REQ_READ_MISS_EVICT = 13 +TCP_PERF_SEL_REQ_WRITE = 14 +TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 15 +TCP_PERF_SEL_REQ_WRITE_MISS_LRU = 16 +TCP_PERF_SEL_REQ_NON_READ = 17 +TCP_PERF_SEL_REQ_MISS = 18 +TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 19 +TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 20 +TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 21 +TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 22 +TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 23 +TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 24 +TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 25 +TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 26 +TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 27 +TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 28 +TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 29 +TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 30 +TCP_PERF_SEL_GL1_REQ_READ = 31 +TCP_PERF_SEL_GL1_REQ_READ_128B = 32 +TCP_PERF_SEL_GL1_REQ_READ_64B = 33 +TCP_PERF_SEL_GL1_REQ_WRITE = 34 +TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 35 +TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 36 +TCP_PERF_SEL_GL1_READ_LATENCY = 37 +TCP_PERF_SEL_GL1_WRITE_LATENCY = 38 +TCP_PERF_SEL_TCP_LATENCY = 39 +TCP_PERF_SEL_TCP_TA_REQ_STALL = 40 +TCP_PERF_SEL_TA_TCP_REQ_STARVE = 41 +TCP_PERF_SEL_DATA_FIFO_STALL = 42 +TCP_PERF_SEL_LOD_STALL = 43 +TCP_PERF_SEL_POWER_STALL = 44 +TCP_PERF_SEL_ALLOC_STALL = 45 +TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 46 +TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 47 +TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 48 +TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 49 +TCP_PERF_SEL_LFIFO_STALL = 50 +TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 51 +TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 52 +TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 53 +TCP_PERF_SEL_GL1_GRANT_READ_STALL = 54 +TCP_PERF_SEL_GL1_PENDING_STALL = 55 +TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL = 56 +TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL = 57 +TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 58 +TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 59 +TCP_PERF_SEL_READ_DATACONFLICT_STALL = 60 +TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 61 +TCP_PERF_SEL_TD_TCP_STALL = 62 +TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_WATCH_MODES' +TCP_WATCH_MODES__enumvalues = { + 0: 'TCP_WATCH_MODE_READ', + 1: 'TCP_WATCH_MODE_NONREAD', + 2: 'TCP_WATCH_MODE_ATOMIC', + 3: 'TCP_WATCH_MODE_ALL', +} +TCP_WATCH_MODE_READ = 0 +TCP_WATCH_MODE_NONREAD = 1 +TCP_WATCH_MODE_ATOMIC = 2 +TCP_WATCH_MODE_ALL = 3 +TCP_WATCH_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TD_PERFCOUNT_SEL' +TD_PERFCOUNT_SEL__enumvalues = { + 0: 'TD_PERF_SEL_none', + 1: 'TD_PERF_SEL_td_busy', + 2: 'TD_PERF_SEL_input_busy', + 3: 'TD_PERF_SEL_sampler_lerp_busy', + 4: 'TD_PERF_SEL_sampler_out_busy', + 5: 'TD_PERF_SEL_nofilter_busy', + 6: 'TD_PERF_SEL_ray_tracing_bvh4_busy', + 7: 'TD_PERF_SEL_sampler_core_sclk_en', + 8: 'TD_PERF_SEL_sampler_preformatter_sclk_en', + 9: 'TD_PERF_SEL_sampler_bilerp_sclk_en', + 10: 'TD_PERF_SEL_sampler_bypass_sclk_en', + 11: 'TD_PERF_SEL_sampler_minmax_sclk_en', + 12: 'TD_PERF_SEL_sampler_accum_sclk_en', + 13: 'TD_PERF_SEL_sampler_format_flt_sclk_en', + 14: 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', + 15: 'TD_PERF_SEL_sampler_out_sclk_en', + 16: 'TD_PERF_SEL_nofilter_sclk_en', + 17: 'TD_PERF_SEL_nofilter_d32_sclk_en', + 18: 'TD_PERF_SEL_nofilter_d16_sclk_en', + 22: 'TD_PERF_SEL_ray_tracing_bvh4_sclk_en', + 23: 'TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en', + 24: 'TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en', + 25: 'TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en', + 26: 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', + 27: 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', + 28: 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', + 29: 'TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off', + 30: 'TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off', + 31: 'TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off', + 32: 'TD_PERF_SEL_core_state_ram_max_cnt', + 33: 'TD_PERF_SEL_core_state_rams_read', + 34: 'TD_PERF_SEL_weight_data_rams_read', + 35: 'TD_PERF_SEL_reference_data_rams_read', + 36: 'TD_PERF_SEL_tc_td_ram_fifo_full', + 37: 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', + 38: 'TD_PERF_SEL_tc_td_data_fifo_full', + 39: 'TD_PERF_SEL_input_state_fifo_full', + 40: 'TD_PERF_SEL_ta_data_stall', + 41: 'TD_PERF_SEL_tc_data_stall', + 42: 'TD_PERF_SEL_tc_ram_stall', + 43: 'TD_PERF_SEL_lds_stall', + 44: 'TD_PERF_SEL_sampler_pkr_full', + 45: 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', + 46: 'TD_PERF_SEL_nofilter_pkr_full', + 47: 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', + 48: 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full', + 49: 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb', + 50: 'TD_PERF_SEL_gather4_instr', + 51: 'TD_PERF_SEL_gather4h_instr', + 54: 'TD_PERF_SEL_sample_instr', + 55: 'TD_PERF_SEL_sample_c_instr', + 56: 'TD_PERF_SEL_load_instr', + 57: 'TD_PERF_SEL_ldfptr_instr', + 58: 'TD_PERF_SEL_write_ack_instr', + 59: 'TD_PERF_SEL_d16_en_instr', + 60: 'TD_PERF_SEL_bypassLerp_instr', + 61: 'TD_PERF_SEL_min_max_filter_instr', + 62: 'TD_PERF_SEL_one_comp_return_instr', + 63: 'TD_PERF_SEL_two_comp_return_instr', + 64: 'TD_PERF_SEL_three_comp_return_instr', + 65: 'TD_PERF_SEL_four_comp_return_instr', + 66: 'TD_PERF_SEL_user_defined_border', + 67: 'TD_PERF_SEL_white_border', + 68: 'TD_PERF_SEL_opaque_black_border', + 69: 'TD_PERF_SEL_lod_warn_from_ta', + 70: 'TD_PERF_SEL_instruction_dest_is_lds', + 71: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', + 72: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', + 73: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', + 74: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', + 75: 'TD_PERF_SEL_out_of_order_instr', + 76: 'TD_PERF_SEL_total_num_instr', + 77: 'TD_PERF_SEL_total_num_instr_with_perf_wdw', + 78: 'TD_PERF_SEL_total_num_sampler_instr', + 79: 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', + 80: 'TD_PERF_SEL_total_num_nofilter_instr', + 81: 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', + 82: 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr', + 83: 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw', + 84: 'TD_PERF_SEL_mixmode_instr', + 85: 'TD_PERF_SEL_mixmode_resource', + 86: 'TD_PERF_SEL_status_packet', + 87: 'TD_PERF_SEL_address_cmd_poison', + 88: 'TD_PERF_SEL_data_poison', + 89: 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', + 90: 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', + 91: 'TD_PERF_SEL_done_scoreboard_not_empty', + 92: 'TD_PERF_SEL_done_scoreboard_is_full', + 93: 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', + 94: 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', + 95: 'TD_PERF_SEL_nofilter_formatters_turned_on', + 96: 'TD_PERF_SEL_nofilter_insert_extra_comps', + 97: 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', + 98: 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', + 99: 'TD_PERF_SEL_msaa_load_instr', + 100: 'TD_PERF_SEL_blend_prt_with_prt_default_0', + 101: 'TD_PERF_SEL_blend_prt_with_prt_default_1', + 102: 'TD_PERF_SEL_resmap_instr', + 103: 'TD_PERF_SEL_prt_ack_instr', + 104: 'TD_PERF_SEL_resmap_with_volume_filtering', + 105: 'TD_PERF_SEL_resmap_with_aniso_filtering', + 106: 'TD_PERF_SEL_resmap_with_no_more_filtering', + 107: 'TD_PERF_SEL_resmap_with_cubemap_corner', + 108: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0', + 109: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1', + 110: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2', + 111: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4', + 112: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8', + 113: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16', + 114: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31', + 115: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32', + 116: 'TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node', + 117: 'TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node', + 118: 'TD_PERF_SEL_ray_tracing_bvh4_tri_node', + 119: 'TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node', + 120: 'TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node', + 121: 'TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node', + 122: 'TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node', + 123: 'TD_PERF_SEL_ray_tracing_bvh4_box_sort_en', + 124: 'TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero', + 125: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx', + 126: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx', + 127: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan', + 128: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_misses', + 129: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses', + 130: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers', + 131: 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', + 132: 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', + 133: 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', + 134: 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', + 135: 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', + 136: 'TD_PERF_SEL_burst_bin_sampler_1', + 137: 'TD_PERF_SEL_burst_bin_sampler_2to8', + 138: 'TD_PERF_SEL_burst_bin_sampler_9to16', + 139: 'TD_PERF_SEL_burst_bin_sampler_gt16', + 140: 'TD_PERF_SEL_burst_bin_gather_1', + 141: 'TD_PERF_SEL_burst_bin_gather_2to8', + 142: 'TD_PERF_SEL_burst_bin_gather_9to16', + 143: 'TD_PERF_SEL_burst_bin_gather_gt16', + 144: 'TD_PERF_SEL_burst_bin_nofilter_1', + 145: 'TD_PERF_SEL_burst_bin_nofilter_2to4', + 146: 'TD_PERF_SEL_burst_bin_nofilter_5to7', + 147: 'TD_PERF_SEL_burst_bin_nofilter_8to16', + 148: 'TD_PERF_SEL_burst_bin_nofilter_gt16', + 149: 'TD_PERF_SEL_burst_bin_bvh4_1', + 150: 'TD_PERF_SEL_burst_bin_bvh4_2to8', + 151: 'TD_PERF_SEL_burst_bin_bvh4_9to16', + 152: 'TD_PERF_SEL_burst_bin_bvh4_gt16', + 153: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_1', + 154: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4', + 155: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7', + 156: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16', + 157: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16', + 158: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1', + 159: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8', + 160: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16', + 161: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16', + 162: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1', + 163: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8', + 164: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16', + 165: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16', + 166: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1', + 167: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8', + 168: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16', + 169: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16', + 170: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', + 171: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', + 172: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', + 173: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', + 174: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', + 175: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', + 176: 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', + 177: 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', + 178: 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', + 179: 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', + 180: 'TD_PERF_SEL_preempting_nofilter_max_cnt', + 181: 'TD_PERF_SEL_sampler_lerp0_active', + 182: 'TD_PERF_SEL_sampler_lerp1_active', + 183: 'TD_PERF_SEL_sampler_lerp2_active', + 184: 'TD_PERF_SEL_sampler_lerp3_active', + 185: 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', + 186: 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', + 187: 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', + 188: 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', + 189: 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', + 190: 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', + 191: 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', + 192: 'TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt', +} +TD_PERF_SEL_none = 0 +TD_PERF_SEL_td_busy = 1 +TD_PERF_SEL_input_busy = 2 +TD_PERF_SEL_sampler_lerp_busy = 3 +TD_PERF_SEL_sampler_out_busy = 4 +TD_PERF_SEL_nofilter_busy = 5 +TD_PERF_SEL_ray_tracing_bvh4_busy = 6 +TD_PERF_SEL_sampler_core_sclk_en = 7 +TD_PERF_SEL_sampler_preformatter_sclk_en = 8 +TD_PERF_SEL_sampler_bilerp_sclk_en = 9 +TD_PERF_SEL_sampler_bypass_sclk_en = 10 +TD_PERF_SEL_sampler_minmax_sclk_en = 11 +TD_PERF_SEL_sampler_accum_sclk_en = 12 +TD_PERF_SEL_sampler_format_flt_sclk_en = 13 +TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 14 +TD_PERF_SEL_sampler_out_sclk_en = 15 +TD_PERF_SEL_nofilter_sclk_en = 16 +TD_PERF_SEL_nofilter_d32_sclk_en = 17 +TD_PERF_SEL_nofilter_d16_sclk_en = 18 +TD_PERF_SEL_ray_tracing_bvh4_sclk_en = 22 +TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en = 23 +TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en = 24 +TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en = 25 +TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 26 +TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 27 +TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 28 +TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off = 29 +TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off = 30 +TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off = 31 +TD_PERF_SEL_core_state_ram_max_cnt = 32 +TD_PERF_SEL_core_state_rams_read = 33 +TD_PERF_SEL_weight_data_rams_read = 34 +TD_PERF_SEL_reference_data_rams_read = 35 +TD_PERF_SEL_tc_td_ram_fifo_full = 36 +TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 37 +TD_PERF_SEL_tc_td_data_fifo_full = 38 +TD_PERF_SEL_input_state_fifo_full = 39 +TD_PERF_SEL_ta_data_stall = 40 +TD_PERF_SEL_tc_data_stall = 41 +TD_PERF_SEL_tc_ram_stall = 42 +TD_PERF_SEL_lds_stall = 43 +TD_PERF_SEL_sampler_pkr_full = 44 +TD_PERF_SEL_sampler_pkr_full_due_to_arb = 45 +TD_PERF_SEL_nofilter_pkr_full = 46 +TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 47 +TD_PERF_SEL_ray_tracing_bvh4_pkr_full = 48 +TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb = 49 +TD_PERF_SEL_gather4_instr = 50 +TD_PERF_SEL_gather4h_instr = 51 +TD_PERF_SEL_sample_instr = 54 +TD_PERF_SEL_sample_c_instr = 55 +TD_PERF_SEL_load_instr = 56 +TD_PERF_SEL_ldfptr_instr = 57 +TD_PERF_SEL_write_ack_instr = 58 +TD_PERF_SEL_d16_en_instr = 59 +TD_PERF_SEL_bypassLerp_instr = 60 +TD_PERF_SEL_min_max_filter_instr = 61 +TD_PERF_SEL_one_comp_return_instr = 62 +TD_PERF_SEL_two_comp_return_instr = 63 +TD_PERF_SEL_three_comp_return_instr = 64 +TD_PERF_SEL_four_comp_return_instr = 65 +TD_PERF_SEL_user_defined_border = 66 +TD_PERF_SEL_white_border = 67 +TD_PERF_SEL_opaque_black_border = 68 +TD_PERF_SEL_lod_warn_from_ta = 69 +TD_PERF_SEL_instruction_dest_is_lds = 70 +TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 71 +TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 72 +TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 73 +TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 74 +TD_PERF_SEL_out_of_order_instr = 75 +TD_PERF_SEL_total_num_instr = 76 +TD_PERF_SEL_total_num_instr_with_perf_wdw = 77 +TD_PERF_SEL_total_num_sampler_instr = 78 +TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 79 +TD_PERF_SEL_total_num_nofilter_instr = 80 +TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 81 +TD_PERF_SEL_total_num_ray_tracing_bvh4_instr = 82 +TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw = 83 +TD_PERF_SEL_mixmode_instr = 84 +TD_PERF_SEL_mixmode_resource = 85 +TD_PERF_SEL_status_packet = 86 +TD_PERF_SEL_address_cmd_poison = 87 +TD_PERF_SEL_data_poison = 88 +TD_PERF_SEL_done_scoreboard_max_stored_cnt = 89 +TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 90 +TD_PERF_SEL_done_scoreboard_not_empty = 91 +TD_PERF_SEL_done_scoreboard_is_full = 92 +TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 93 +TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 94 +TD_PERF_SEL_nofilter_formatters_turned_on = 95 +TD_PERF_SEL_nofilter_insert_extra_comps = 96 +TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 97 +TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 98 +TD_PERF_SEL_msaa_load_instr = 99 +TD_PERF_SEL_blend_prt_with_prt_default_0 = 100 +TD_PERF_SEL_blend_prt_with_prt_default_1 = 101 +TD_PERF_SEL_resmap_instr = 102 +TD_PERF_SEL_prt_ack_instr = 103 +TD_PERF_SEL_resmap_with_volume_filtering = 104 +TD_PERF_SEL_resmap_with_aniso_filtering = 105 +TD_PERF_SEL_resmap_with_no_more_filtering = 106 +TD_PERF_SEL_resmap_with_cubemap_corner = 107 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0 = 108 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1 = 109 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2 = 110 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4 = 111 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8 = 112 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16 = 113 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31 = 114 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32 = 115 +TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node = 116 +TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node = 117 +TD_PERF_SEL_ray_tracing_bvh4_tri_node = 118 +TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node = 119 +TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node = 120 +TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node = 121 +TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node = 122 +TD_PERF_SEL_ray_tracing_bvh4_box_sort_en = 123 +TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero = 124 +TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx = 125 +TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx = 126 +TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan = 127 +TD_PERF_SEL_ray_tracing_bvh4_num_box_misses = 128 +TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses = 129 +TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers = 130 +TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 131 +TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 132 +TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 133 +TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 134 +TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 135 +TD_PERF_SEL_burst_bin_sampler_1 = 136 +TD_PERF_SEL_burst_bin_sampler_2to8 = 137 +TD_PERF_SEL_burst_bin_sampler_9to16 = 138 +TD_PERF_SEL_burst_bin_sampler_gt16 = 139 +TD_PERF_SEL_burst_bin_gather_1 = 140 +TD_PERF_SEL_burst_bin_gather_2to8 = 141 +TD_PERF_SEL_burst_bin_gather_9to16 = 142 +TD_PERF_SEL_burst_bin_gather_gt16 = 143 +TD_PERF_SEL_burst_bin_nofilter_1 = 144 +TD_PERF_SEL_burst_bin_nofilter_2to4 = 145 +TD_PERF_SEL_burst_bin_nofilter_5to7 = 146 +TD_PERF_SEL_burst_bin_nofilter_8to16 = 147 +TD_PERF_SEL_burst_bin_nofilter_gt16 = 148 +TD_PERF_SEL_burst_bin_bvh4_1 = 149 +TD_PERF_SEL_burst_bin_bvh4_2to8 = 150 +TD_PERF_SEL_burst_bin_bvh4_9to16 = 151 +TD_PERF_SEL_burst_bin_bvh4_gt16 = 152 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_1 = 153 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4 = 154 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7 = 155 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16 = 156 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16 = 157 +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1 = 158 +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8 = 159 +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16 = 160 +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16 = 161 +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1 = 162 +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8 = 163 +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16 = 164 +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16 = 165 +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1 = 166 +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8 = 167 +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16 = 168 +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16 = 169 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 170 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 171 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 172 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 173 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 174 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 175 +TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 176 +TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 177 +TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 178 +TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 179 +TD_PERF_SEL_preempting_nofilter_max_cnt = 180 +TD_PERF_SEL_sampler_lerp0_active = 181 +TD_PERF_SEL_sampler_lerp1_active = 182 +TD_PERF_SEL_sampler_lerp2_active = 183 +TD_PERF_SEL_sampler_lerp3_active = 184 +TD_PERF_SEL_nofilter_total_num_comps_to_lds = 185 +TD_PERF_SEL_nofilter_byte_cycling_4cycles = 186 +TD_PERF_SEL_nofilter_byte_cycling_8cycles = 187 +TD_PERF_SEL_nofilter_byte_cycling_16cycles = 188 +TD_PERF_SEL_nofilter_dword_cycling_2cycles = 189 +TD_PERF_SEL_nofilter_dword_cycling_4cycles = 190 +TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 191 +TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt = 192 +TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL2A_PERF_SEL' +GL2A_PERF_SEL__enumvalues = { + 0: 'GL2A_PERF_SEL_NONE', + 1: 'GL2A_PERF_SEL_CYCLE', + 2: 'GL2A_PERF_SEL_BUSY', + 3: 'GL2A_PERF_SEL_REQ_GL2C0', + 4: 'GL2A_PERF_SEL_REQ_GL2C1', + 5: 'GL2A_PERF_SEL_REQ_GL2C2', + 6: 'GL2A_PERF_SEL_REQ_GL2C3', + 7: 'GL2A_PERF_SEL_REQ_GL2C4', + 8: 'GL2A_PERF_SEL_REQ_GL2C5', + 9: 'GL2A_PERF_SEL_REQ_GL2C6', + 10: 'GL2A_PERF_SEL_REQ_GL2C7', + 11: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', + 12: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', + 13: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', + 14: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', + 15: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', + 16: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', + 17: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', + 18: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', + 19: 'GL2A_PERF_SEL_REQ_BURST_GL2C0', + 20: 'GL2A_PERF_SEL_REQ_BURST_GL2C1', + 21: 'GL2A_PERF_SEL_REQ_BURST_GL2C2', + 22: 'GL2A_PERF_SEL_REQ_BURST_GL2C3', + 23: 'GL2A_PERF_SEL_REQ_BURST_GL2C4', + 24: 'GL2A_PERF_SEL_REQ_BURST_GL2C5', + 25: 'GL2A_PERF_SEL_REQ_BURST_GL2C6', + 26: 'GL2A_PERF_SEL_REQ_BURST_GL2C7', + 27: 'GL2A_PERF_SEL_REQ_STALL_GL2C0', + 28: 'GL2A_PERF_SEL_REQ_STALL_GL2C1', + 29: 'GL2A_PERF_SEL_REQ_STALL_GL2C2', + 30: 'GL2A_PERF_SEL_REQ_STALL_GL2C3', + 31: 'GL2A_PERF_SEL_REQ_STALL_GL2C4', + 32: 'GL2A_PERF_SEL_REQ_STALL_GL2C5', + 33: 'GL2A_PERF_SEL_REQ_STALL_GL2C6', + 34: 'GL2A_PERF_SEL_REQ_STALL_GL2C7', + 35: 'GL2A_PERF_SEL_RTN_STALL_GL2C0', + 36: 'GL2A_PERF_SEL_RTN_STALL_GL2C1', + 37: 'GL2A_PERF_SEL_RTN_STALL_GL2C2', + 38: 'GL2A_PERF_SEL_RTN_STALL_GL2C3', + 39: 'GL2A_PERF_SEL_RTN_STALL_GL2C4', + 40: 'GL2A_PERF_SEL_RTN_STALL_GL2C5', + 41: 'GL2A_PERF_SEL_RTN_STALL_GL2C6', + 42: 'GL2A_PERF_SEL_RTN_STALL_GL2C7', + 43: 'GL2A_PERF_SEL_RTN_CLIENT0', + 44: 'GL2A_PERF_SEL_RTN_CLIENT1', + 45: 'GL2A_PERF_SEL_RTN_CLIENT2', + 46: 'GL2A_PERF_SEL_RTN_CLIENT3', + 47: 'GL2A_PERF_SEL_RTN_CLIENT4', + 48: 'GL2A_PERF_SEL_RTN_CLIENT5', + 49: 'GL2A_PERF_SEL_RTN_CLIENT6', + 50: 'GL2A_PERF_SEL_RTN_CLIENT7', + 51: 'GL2A_PERF_SEL_RTN_CLIENT8', + 52: 'GL2A_PERF_SEL_RTN_CLIENT9', + 53: 'GL2A_PERF_SEL_RTN_CLIENT10', + 54: 'GL2A_PERF_SEL_RTN_CLIENT11', + 55: 'GL2A_PERF_SEL_RTN_CLIENT12', + 56: 'GL2A_PERF_SEL_RTN_CLIENT13', + 57: 'GL2A_PERF_SEL_RTN_CLIENT14', + 58: 'GL2A_PERF_SEL_RTN_CLIENT15', + 59: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', + 60: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', + 61: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', + 62: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', + 63: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', + 64: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', + 65: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', + 66: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', + 67: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', + 68: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', + 69: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', + 70: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', + 71: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', + 72: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', + 73: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', + 74: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', + 75: 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', + 76: 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', + 77: 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', + 78: 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', + 79: 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', + 80: 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', + 81: 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', + 82: 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', + 83: 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', + 84: 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', + 85: 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', + 86: 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', + 87: 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', + 88: 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', + 89: 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', + 90: 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', + 91: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', + 92: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', + 93: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', + 94: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', + 95: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', + 96: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', + 97: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', + 98: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', + 99: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', + 100: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', + 101: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', + 103: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', + 104: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', + 105: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', + 106: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', + 107: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', +} +GL2A_PERF_SEL_NONE = 0 +GL2A_PERF_SEL_CYCLE = 1 +GL2A_PERF_SEL_BUSY = 2 +GL2A_PERF_SEL_REQ_GL2C0 = 3 +GL2A_PERF_SEL_REQ_GL2C1 = 4 +GL2A_PERF_SEL_REQ_GL2C2 = 5 +GL2A_PERF_SEL_REQ_GL2C3 = 6 +GL2A_PERF_SEL_REQ_GL2C4 = 7 +GL2A_PERF_SEL_REQ_GL2C5 = 8 +GL2A_PERF_SEL_REQ_GL2C6 = 9 +GL2A_PERF_SEL_REQ_GL2C7 = 10 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 11 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 12 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 13 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 14 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 15 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 16 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 17 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 18 +GL2A_PERF_SEL_REQ_BURST_GL2C0 = 19 +GL2A_PERF_SEL_REQ_BURST_GL2C1 = 20 +GL2A_PERF_SEL_REQ_BURST_GL2C2 = 21 +GL2A_PERF_SEL_REQ_BURST_GL2C3 = 22 +GL2A_PERF_SEL_REQ_BURST_GL2C4 = 23 +GL2A_PERF_SEL_REQ_BURST_GL2C5 = 24 +GL2A_PERF_SEL_REQ_BURST_GL2C6 = 25 +GL2A_PERF_SEL_REQ_BURST_GL2C7 = 26 +GL2A_PERF_SEL_REQ_STALL_GL2C0 = 27 +GL2A_PERF_SEL_REQ_STALL_GL2C1 = 28 +GL2A_PERF_SEL_REQ_STALL_GL2C2 = 29 +GL2A_PERF_SEL_REQ_STALL_GL2C3 = 30 +GL2A_PERF_SEL_REQ_STALL_GL2C4 = 31 +GL2A_PERF_SEL_REQ_STALL_GL2C5 = 32 +GL2A_PERF_SEL_REQ_STALL_GL2C6 = 33 +GL2A_PERF_SEL_REQ_STALL_GL2C7 = 34 +GL2A_PERF_SEL_RTN_STALL_GL2C0 = 35 +GL2A_PERF_SEL_RTN_STALL_GL2C1 = 36 +GL2A_PERF_SEL_RTN_STALL_GL2C2 = 37 +GL2A_PERF_SEL_RTN_STALL_GL2C3 = 38 +GL2A_PERF_SEL_RTN_STALL_GL2C4 = 39 +GL2A_PERF_SEL_RTN_STALL_GL2C5 = 40 +GL2A_PERF_SEL_RTN_STALL_GL2C6 = 41 +GL2A_PERF_SEL_RTN_STALL_GL2C7 = 42 +GL2A_PERF_SEL_RTN_CLIENT0 = 43 +GL2A_PERF_SEL_RTN_CLIENT1 = 44 +GL2A_PERF_SEL_RTN_CLIENT2 = 45 +GL2A_PERF_SEL_RTN_CLIENT3 = 46 +GL2A_PERF_SEL_RTN_CLIENT4 = 47 +GL2A_PERF_SEL_RTN_CLIENT5 = 48 +GL2A_PERF_SEL_RTN_CLIENT6 = 49 +GL2A_PERF_SEL_RTN_CLIENT7 = 50 +GL2A_PERF_SEL_RTN_CLIENT8 = 51 +GL2A_PERF_SEL_RTN_CLIENT9 = 52 +GL2A_PERF_SEL_RTN_CLIENT10 = 53 +GL2A_PERF_SEL_RTN_CLIENT11 = 54 +GL2A_PERF_SEL_RTN_CLIENT12 = 55 +GL2A_PERF_SEL_RTN_CLIENT13 = 56 +GL2A_PERF_SEL_RTN_CLIENT14 = 57 +GL2A_PERF_SEL_RTN_CLIENT15 = 58 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 59 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 60 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 61 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 62 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 63 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 64 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 65 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 66 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 67 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 68 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 69 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 70 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 71 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 72 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 73 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 74 +GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 75 +GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 76 +GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 77 +GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 78 +GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 79 +GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 80 +GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 81 +GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 82 +GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 83 +GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 84 +GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 85 +GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 86 +GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 87 +GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 88 +GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 89 +GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 90 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 91 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 92 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 93 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 94 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 95 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 96 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 97 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 98 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 99 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 100 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 101 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 103 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 104 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 105 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 106 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 107 +GL2A_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL2C_PERF_SEL' +GL2C_PERF_SEL__enumvalues = { + 0: 'GL2C_PERF_SEL_NONE', + 1: 'GL2C_PERF_SEL_CYCLE', + 2: 'GL2C_PERF_SEL_BUSY', + 3: 'GL2C_PERF_SEL_REQ', + 4: 'GL2C_PERF_SEL_VOL_REQ', + 5: 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', + 6: 'GL2C_PERF_SEL_READ', + 7: 'GL2C_PERF_SEL_WRITE', + 8: 'GL2C_PERF_SEL_ATOMIC', + 9: 'GL2C_PERF_SEL_NOP_ACK', + 10: 'GL2C_PERF_SEL_NOP_RTN0', + 11: 'GL2C_PERF_SEL_PROBE', + 12: 'GL2C_PERF_SEL_PROBE_ALL', + 13: 'GL2C_PERF_SEL_INTERNAL_PROBE', + 14: 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', + 15: 'GL2C_PERF_SEL_METADATA_READ_REQ', + 16: 'GL2C_PERF_SEL_CLIENT0_REQ', + 17: 'GL2C_PERF_SEL_CLIENT1_REQ', + 18: 'GL2C_PERF_SEL_CLIENT2_REQ', + 19: 'GL2C_PERF_SEL_CLIENT3_REQ', + 20: 'GL2C_PERF_SEL_CLIENT4_REQ', + 21: 'GL2C_PERF_SEL_CLIENT5_REQ', + 22: 'GL2C_PERF_SEL_CLIENT6_REQ', + 23: 'GL2C_PERF_SEL_CLIENT7_REQ', + 24: 'GL2C_PERF_SEL_CLIENT8_REQ', + 25: 'GL2C_PERF_SEL_CLIENT9_REQ', + 26: 'GL2C_PERF_SEL_CLIENT10_REQ', + 27: 'GL2C_PERF_SEL_CLIENT11_REQ', + 28: 'GL2C_PERF_SEL_CLIENT12_REQ', + 29: 'GL2C_PERF_SEL_CLIENT13_REQ', + 30: 'GL2C_PERF_SEL_CLIENT14_REQ', + 31: 'GL2C_PERF_SEL_CLIENT15_REQ', + 32: 'GL2C_PERF_SEL_C_RW_S_REQ', + 33: 'GL2C_PERF_SEL_C_RW_US_REQ', + 34: 'GL2C_PERF_SEL_C_RO_S_REQ', + 35: 'GL2C_PERF_SEL_C_RO_US_REQ', + 36: 'GL2C_PERF_SEL_UC_REQ', + 37: 'GL2C_PERF_SEL_LRU_REQ', + 38: 'GL2C_PERF_SEL_STREAM_REQ', + 39: 'GL2C_PERF_SEL_BYPASS_REQ', + 40: 'GL2C_PERF_SEL_NOA_REQ', + 41: 'GL2C_PERF_SEL_SHARED_REQ', + 42: 'GL2C_PERF_SEL_HIT', + 43: 'GL2C_PERF_SEL_MISS', + 44: 'GL2C_PERF_SEL_FULL_HIT', + 45: 'GL2C_PERF_SEL_PARTIAL_32B_HIT', + 46: 'GL2C_PERF_SEL_PARTIAL_64B_HIT', + 47: 'GL2C_PERF_SEL_PARTIAL_96B_HIT', + 48: 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', + 49: 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', + 50: 'GL2C_PERF_SEL_UNCACHED_WRITE', + 51: 'GL2C_PERF_SEL_WRITEBACK', + 52: 'GL2C_PERF_SEL_NORMAL_WRITEBACK', + 53: 'GL2C_PERF_SEL_EVICT', + 54: 'GL2C_PERF_SEL_NORMAL_EVICT', + 55: 'GL2C_PERF_SEL_PROBE_EVICT', + 56: 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', + 57: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', + 58: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', + 59: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', + 60: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', + 61: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', + 62: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', + 63: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', + 64: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', + 65: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', + 66: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', + 67: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', + 68: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', + 69: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', + 70: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', + 71: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', + 72: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', + 73: 'GL2C_PERF_SEL_READ_32_REQ', + 74: 'GL2C_PERF_SEL_READ_64_REQ', + 75: 'GL2C_PERF_SEL_READ_128_REQ', + 76: 'GL2C_PERF_SEL_WRITE_32_REQ', + 77: 'GL2C_PERF_SEL_WRITE_64_REQ', + 78: 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', + 79: 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', + 80: 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', + 81: 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', + 82: 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', + 83: 'GL2C_PERF_SEL_MC_WRREQ', + 84: 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', + 85: 'GL2C_PERF_SEL_EA_WRREQ_64B', + 86: 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', + 87: 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', + 88: 'GL2C_PERF_SEL_MC_WRREQ_STALL', + 89: 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', + 90: 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', + 91: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', + 92: 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', + 93: 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', + 94: 'GL2C_PERF_SEL_EA_ATOMIC', + 95: 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', + 96: 'GL2C_PERF_SEL_MC_RDREQ', + 97: 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', + 98: 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', + 99: 'GL2C_PERF_SEL_EA_RDREQ_32B', + 100: 'GL2C_PERF_SEL_EA_RDREQ_64B', + 101: 'GL2C_PERF_SEL_EA_RDREQ_96B', + 102: 'GL2C_PERF_SEL_EA_RDREQ_128B', + 103: 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', + 104: 'GL2C_PERF_SEL_EA_RD_MDC_32B', + 105: 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', + 106: 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', + 107: 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', + 108: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', + 109: 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', + 110: 'GL2C_PERF_SEL_EA_RDREQ_DRAM', + 111: 'GL2C_PERF_SEL_EA_WRREQ_DRAM', + 112: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', + 113: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', + 114: 'GL2C_PERF_SEL_ONION_READ', + 115: 'GL2C_PERF_SEL_ONION_WRITE', + 116: 'GL2C_PERF_SEL_IO_READ', + 117: 'GL2C_PERF_SEL_IO_WRITE', + 118: 'GL2C_PERF_SEL_GARLIC_READ', + 119: 'GL2C_PERF_SEL_GARLIC_WRITE', + 120: 'GL2C_PERF_SEL_EA_OUTSTANDING', + 121: 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', + 122: 'GL2C_PERF_SEL_SRC_FIFO_FULL', + 123: 'GL2C_PERF_SEL_TAG_STALL', + 124: 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 125: 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 126: 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 127: 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 128: 'GL2C_PERF_SEL_TAG_PROBE_STALL', + 129: 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', + 130: 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', + 131: 'GL2C_PERF_SEL_TAG_READ_DST_STALL', + 132: 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', + 133: 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 134: 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 135: 'GL2C_PERF_SEL_BUBBLE', + 136: 'GL2C_PERF_SEL_IB_REQ', + 137: 'GL2C_PERF_SEL_IB_STALL', + 138: 'GL2C_PERF_SEL_IB_TAG_STALL', + 139: 'GL2C_PERF_SEL_IB_CM_STALL', + 140: 'GL2C_PERF_SEL_RETURN_ACK', + 141: 'GL2C_PERF_SEL_RETURN_DATA', + 142: 'GL2C_PERF_SEL_EA_RDRET_NACK', + 143: 'GL2C_PERF_SEL_EA_WRRET_NACK', + 144: 'GL2C_PERF_SEL_GL2A_LEVEL', + 145: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', + 146: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', + 147: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 148: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', + 149: 'GL2C_PERF_SEL_GCR_INV', + 150: 'GL2C_PERF_SEL_GCR_WB', + 151: 'GL2C_PERF_SEL_GCR_DISCARD', + 152: 'GL2C_PERF_SEL_GCR_RANGE', + 153: 'GL2C_PERF_SEL_GCR_ALL', + 154: 'GL2C_PERF_SEL_GCR_VOL', + 155: 'GL2C_PERF_SEL_GCR_UNSHARED', + 156: 'GL2C_PERF_SEL_GCR_MDC_INV', + 157: 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', + 158: 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', + 159: 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', + 160: 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', + 161: 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', + 162: 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', + 163: 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', + 164: 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', + 165: 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', + 166: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', + 167: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', + 168: 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', + 169: 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', + 170: 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', + 171: 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', + 172: 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', + 173: 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', + 174: 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', + 175: 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', + 176: 'GL2C_PERF_SEL_GCR_WBINVL2_START', + 177: 'GL2C_PERF_SEL_MDC_INV_METADATA', + 178: 'GL2C_PERF_SEL_MDC_REQ', + 179: 'GL2C_PERF_SEL_MDC_LEVEL', + 180: 'GL2C_PERF_SEL_MDC_TAG_HIT', + 181: 'GL2C_PERF_SEL_MDC_SECTOR_HIT', + 182: 'GL2C_PERF_SEL_MDC_SECTOR_MISS', + 183: 'GL2C_PERF_SEL_MDC_TAG_STALL', + 184: 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', + 185: 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', + 186: 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', + 187: 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', + 188: 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', + 189: 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', + 190: 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', + 191: 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', + 192: 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', + 193: 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', + 194: 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', + 195: 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', + 196: 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', + 197: 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', + 198: 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', + 199: 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', + 200: 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', + 201: 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', + 202: 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', + 203: 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', + 204: 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', + 205: 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', + 206: 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', + 207: 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', + 208: 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', + 209: 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', + 210: 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', + 211: 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', + 212: 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', + 213: 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', + 214: 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', + 215: 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', + 216: 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', + 217: 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', + 218: 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', + 219: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', + 220: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', + 221: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', + 222: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ', + 223: 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', + 224: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', + 225: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', + 226: 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', + 227: 'GL2C_PERF_SEL_CM_COMP_READ_REQ', + 228: 'GL2C_PERF_SEL_CM_READ_BACK_REQ', + 229: 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', + 230: 'GL2C_PERF_SEL_CM_WR_ACK_REQ', + 231: 'GL2C_PERF_SEL_CM_NO_ACK_REQ', + 232: 'GL2C_PERF_SEL_CM_NOOP_REQ', + 233: 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', + 234: 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', + 235: 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', + 236: 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', + 237: 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', + 238: 'GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ', + 239: 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', + 240: 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', + 241: 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', + 242: 'GL2C_PERF_SEL_CM_RVF_FULL', + 243: 'GL2C_PERF_SEL_CM_SDR_FULL', + 244: 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', + 245: 'GL2C_PERF_SEL_CM_DCC_STALL', + 246: 'GL2C_PERF_SEL_CM_DCC_IN_XFC', + 247: 'GL2C_PERF_SEL_CM_DCC_OUT_XFC', + 248: 'GL2C_PERF_SEL_CM_DCC_OUT_1x1', + 249: 'GL2C_PERF_SEL_CM_DCC_OUT_1x2', + 250: 'GL2C_PERF_SEL_CM_DCC_OUT_2x1', + 251: 'GL2C_PERF_SEL_CM_DCC_OUT_2x2', + 252: 'GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP', + 253: 'GL2C_PERF_SEL_CM_DCC_OUT_CONST', + 254: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', + 255: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', + 256: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', + 257: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', +} +GL2C_PERF_SEL_NONE = 0 +GL2C_PERF_SEL_CYCLE = 1 +GL2C_PERF_SEL_BUSY = 2 +GL2C_PERF_SEL_REQ = 3 +GL2C_PERF_SEL_VOL_REQ = 4 +GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 5 +GL2C_PERF_SEL_READ = 6 +GL2C_PERF_SEL_WRITE = 7 +GL2C_PERF_SEL_ATOMIC = 8 +GL2C_PERF_SEL_NOP_ACK = 9 +GL2C_PERF_SEL_NOP_RTN0 = 10 +GL2C_PERF_SEL_PROBE = 11 +GL2C_PERF_SEL_PROBE_ALL = 12 +GL2C_PERF_SEL_INTERNAL_PROBE = 13 +GL2C_PERF_SEL_COMPRESSED_READ_REQ = 14 +GL2C_PERF_SEL_METADATA_READ_REQ = 15 +GL2C_PERF_SEL_CLIENT0_REQ = 16 +GL2C_PERF_SEL_CLIENT1_REQ = 17 +GL2C_PERF_SEL_CLIENT2_REQ = 18 +GL2C_PERF_SEL_CLIENT3_REQ = 19 +GL2C_PERF_SEL_CLIENT4_REQ = 20 +GL2C_PERF_SEL_CLIENT5_REQ = 21 +GL2C_PERF_SEL_CLIENT6_REQ = 22 +GL2C_PERF_SEL_CLIENT7_REQ = 23 +GL2C_PERF_SEL_CLIENT8_REQ = 24 +GL2C_PERF_SEL_CLIENT9_REQ = 25 +GL2C_PERF_SEL_CLIENT10_REQ = 26 +GL2C_PERF_SEL_CLIENT11_REQ = 27 +GL2C_PERF_SEL_CLIENT12_REQ = 28 +GL2C_PERF_SEL_CLIENT13_REQ = 29 +GL2C_PERF_SEL_CLIENT14_REQ = 30 +GL2C_PERF_SEL_CLIENT15_REQ = 31 +GL2C_PERF_SEL_C_RW_S_REQ = 32 +GL2C_PERF_SEL_C_RW_US_REQ = 33 +GL2C_PERF_SEL_C_RO_S_REQ = 34 +GL2C_PERF_SEL_C_RO_US_REQ = 35 +GL2C_PERF_SEL_UC_REQ = 36 +GL2C_PERF_SEL_LRU_REQ = 37 +GL2C_PERF_SEL_STREAM_REQ = 38 +GL2C_PERF_SEL_BYPASS_REQ = 39 +GL2C_PERF_SEL_NOA_REQ = 40 +GL2C_PERF_SEL_SHARED_REQ = 41 +GL2C_PERF_SEL_HIT = 42 +GL2C_PERF_SEL_MISS = 43 +GL2C_PERF_SEL_FULL_HIT = 44 +GL2C_PERF_SEL_PARTIAL_32B_HIT = 45 +GL2C_PERF_SEL_PARTIAL_64B_HIT = 46 +GL2C_PERF_SEL_PARTIAL_96B_HIT = 47 +GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 48 +GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 49 +GL2C_PERF_SEL_UNCACHED_WRITE = 50 +GL2C_PERF_SEL_WRITEBACK = 51 +GL2C_PERF_SEL_NORMAL_WRITEBACK = 52 +GL2C_PERF_SEL_EVICT = 53 +GL2C_PERF_SEL_NORMAL_EVICT = 54 +GL2C_PERF_SEL_PROBE_EVICT = 55 +GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 56 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 57 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 58 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 59 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 60 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 61 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 62 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 63 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 64 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 65 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 66 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 67 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 68 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 69 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 70 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 71 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 72 +GL2C_PERF_SEL_READ_32_REQ = 73 +GL2C_PERF_SEL_READ_64_REQ = 74 +GL2C_PERF_SEL_READ_128_REQ = 75 +GL2C_PERF_SEL_WRITE_32_REQ = 76 +GL2C_PERF_SEL_WRITE_64_REQ = 77 +GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 78 +GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 79 +GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 80 +GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 81 +GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 82 +GL2C_PERF_SEL_MC_WRREQ = 83 +GL2C_PERF_SEL_EA_WRREQ_SNOOP = 84 +GL2C_PERF_SEL_EA_WRREQ_64B = 85 +GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 86 +GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 87 +GL2C_PERF_SEL_MC_WRREQ_STALL = 88 +GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 89 +GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 90 +GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 91 +GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 92 +GL2C_PERF_SEL_MC_WRREQ_LEVEL = 93 +GL2C_PERF_SEL_EA_ATOMIC = 94 +GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 95 +GL2C_PERF_SEL_MC_RDREQ = 96 +GL2C_PERF_SEL_EA_RDREQ_SNOOP = 97 +GL2C_PERF_SEL_EA_RDREQ_SPLIT = 98 +GL2C_PERF_SEL_EA_RDREQ_32B = 99 +GL2C_PERF_SEL_EA_RDREQ_64B = 100 +GL2C_PERF_SEL_EA_RDREQ_96B = 101 +GL2C_PERF_SEL_EA_RDREQ_128B = 102 +GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 103 +GL2C_PERF_SEL_EA_RD_MDC_32B = 104 +GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 105 +GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 106 +GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 107 +GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 108 +GL2C_PERF_SEL_MC_RDREQ_LEVEL = 109 +GL2C_PERF_SEL_EA_RDREQ_DRAM = 110 +GL2C_PERF_SEL_EA_WRREQ_DRAM = 111 +GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 112 +GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 113 +GL2C_PERF_SEL_ONION_READ = 114 +GL2C_PERF_SEL_ONION_WRITE = 115 +GL2C_PERF_SEL_IO_READ = 116 +GL2C_PERF_SEL_IO_WRITE = 117 +GL2C_PERF_SEL_GARLIC_READ = 118 +GL2C_PERF_SEL_GARLIC_WRITE = 119 +GL2C_PERF_SEL_EA_OUTSTANDING = 120 +GL2C_PERF_SEL_LATENCY_FIFO_FULL = 121 +GL2C_PERF_SEL_SRC_FIFO_FULL = 122 +GL2C_PERF_SEL_TAG_STALL = 123 +GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 124 +GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 125 +GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 126 +GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 127 +GL2C_PERF_SEL_TAG_PROBE_STALL = 128 +GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 129 +GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 130 +GL2C_PERF_SEL_TAG_READ_DST_STALL = 131 +GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 132 +GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 133 +GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 134 +GL2C_PERF_SEL_BUBBLE = 135 +GL2C_PERF_SEL_IB_REQ = 136 +GL2C_PERF_SEL_IB_STALL = 137 +GL2C_PERF_SEL_IB_TAG_STALL = 138 +GL2C_PERF_SEL_IB_CM_STALL = 139 +GL2C_PERF_SEL_RETURN_ACK = 140 +GL2C_PERF_SEL_RETURN_DATA = 141 +GL2C_PERF_SEL_EA_RDRET_NACK = 142 +GL2C_PERF_SEL_EA_WRRET_NACK = 143 +GL2C_PERF_SEL_GL2A_LEVEL = 144 +GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 145 +GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 146 +GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 147 +GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 148 +GL2C_PERF_SEL_GCR_INV = 149 +GL2C_PERF_SEL_GCR_WB = 150 +GL2C_PERF_SEL_GCR_DISCARD = 151 +GL2C_PERF_SEL_GCR_RANGE = 152 +GL2C_PERF_SEL_GCR_ALL = 153 +GL2C_PERF_SEL_GCR_VOL = 154 +GL2C_PERF_SEL_GCR_UNSHARED = 155 +GL2C_PERF_SEL_GCR_MDC_INV = 156 +GL2C_PERF_SEL_GCR_GL2_INV_ALL = 157 +GL2C_PERF_SEL_GCR_GL2_WB_ALL = 158 +GL2C_PERF_SEL_GCR_MDC_INV_ALL = 159 +GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 160 +GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 161 +GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 162 +GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 163 +GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 164 +GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 165 +GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 166 +GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 167 +GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 168 +GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 169 +GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 170 +GL2C_PERF_SEL_GCR_INVL2_VOL_START = 171 +GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 172 +GL2C_PERF_SEL_GCR_WBL2_VOL_START = 173 +GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 174 +GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 175 +GL2C_PERF_SEL_GCR_WBINVL2_START = 176 +GL2C_PERF_SEL_MDC_INV_METADATA = 177 +GL2C_PERF_SEL_MDC_REQ = 178 +GL2C_PERF_SEL_MDC_LEVEL = 179 +GL2C_PERF_SEL_MDC_TAG_HIT = 180 +GL2C_PERF_SEL_MDC_SECTOR_HIT = 181 +GL2C_PERF_SEL_MDC_SECTOR_MISS = 182 +GL2C_PERF_SEL_MDC_TAG_STALL = 183 +GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 184 +GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 185 +GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 186 +GL2C_PERF_SEL_CM_CHANNEL0_REQ = 187 +GL2C_PERF_SEL_CM_CHANNEL1_REQ = 188 +GL2C_PERF_SEL_CM_CHANNEL2_REQ = 189 +GL2C_PERF_SEL_CM_CHANNEL3_REQ = 190 +GL2C_PERF_SEL_CM_CHANNEL4_REQ = 191 +GL2C_PERF_SEL_CM_CHANNEL5_REQ = 192 +GL2C_PERF_SEL_CM_CHANNEL6_REQ = 193 +GL2C_PERF_SEL_CM_CHANNEL7_REQ = 194 +GL2C_PERF_SEL_CM_CHANNEL8_REQ = 195 +GL2C_PERF_SEL_CM_CHANNEL9_REQ = 196 +GL2C_PERF_SEL_CM_CHANNEL10_REQ = 197 +GL2C_PERF_SEL_CM_CHANNEL11_REQ = 198 +GL2C_PERF_SEL_CM_CHANNEL12_REQ = 199 +GL2C_PERF_SEL_CM_CHANNEL13_REQ = 200 +GL2C_PERF_SEL_CM_CHANNEL14_REQ = 201 +GL2C_PERF_SEL_CM_CHANNEL15_REQ = 202 +GL2C_PERF_SEL_CM_CHANNEL16_REQ = 203 +GL2C_PERF_SEL_CM_CHANNEL17_REQ = 204 +GL2C_PERF_SEL_CM_CHANNEL18_REQ = 205 +GL2C_PERF_SEL_CM_CHANNEL19_REQ = 206 +GL2C_PERF_SEL_CM_CHANNEL20_REQ = 207 +GL2C_PERF_SEL_CM_CHANNEL21_REQ = 208 +GL2C_PERF_SEL_CM_CHANNEL22_REQ = 209 +GL2C_PERF_SEL_CM_CHANNEL23_REQ = 210 +GL2C_PERF_SEL_CM_CHANNEL24_REQ = 211 +GL2C_PERF_SEL_CM_CHANNEL25_REQ = 212 +GL2C_PERF_SEL_CM_CHANNEL26_REQ = 213 +GL2C_PERF_SEL_CM_CHANNEL27_REQ = 214 +GL2C_PERF_SEL_CM_CHANNEL28_REQ = 215 +GL2C_PERF_SEL_CM_CHANNEL29_REQ = 216 +GL2C_PERF_SEL_CM_CHANNEL30_REQ = 217 +GL2C_PERF_SEL_CM_CHANNEL31_REQ = 218 +GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 219 +GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 220 +GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 221 +GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ = 222 +GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 223 +GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 224 +GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 225 +GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 226 +GL2C_PERF_SEL_CM_COMP_READ_REQ = 227 +GL2C_PERF_SEL_CM_READ_BACK_REQ = 228 +GL2C_PERF_SEL_CM_METADATA_WR_REQ = 229 +GL2C_PERF_SEL_CM_WR_ACK_REQ = 230 +GL2C_PERF_SEL_CM_NO_ACK_REQ = 231 +GL2C_PERF_SEL_CM_NOOP_REQ = 232 +GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 233 +GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 234 +GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 235 +GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 236 +GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 237 +GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ = 238 +GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 239 +GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 240 +GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 241 +GL2C_PERF_SEL_CM_RVF_FULL = 242 +GL2C_PERF_SEL_CM_SDR_FULL = 243 +GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 244 +GL2C_PERF_SEL_CM_DCC_STALL = 245 +GL2C_PERF_SEL_CM_DCC_IN_XFC = 246 +GL2C_PERF_SEL_CM_DCC_OUT_XFC = 247 +GL2C_PERF_SEL_CM_DCC_OUT_1x1 = 248 +GL2C_PERF_SEL_CM_DCC_OUT_1x2 = 249 +GL2C_PERF_SEL_CM_DCC_OUT_2x1 = 250 +GL2C_PERF_SEL_CM_DCC_OUT_2x2 = 251 +GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP = 252 +GL2C_PERF_SEL_CM_DCC_OUT_CONST = 253 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 254 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 255 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 256 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 257 +GL2C_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_PERF_SEL' +GRBM_PERF_SEL__enumvalues = { + 0: 'GRBM_PERF_SEL_COUNT', + 1: 'GRBM_PERF_SEL_USER_DEFINED', + 2: 'GRBM_PERF_SEL_GUI_ACTIVE', + 3: 'GRBM_PERF_SEL_CP_BUSY', + 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', + 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', + 6: 'GRBM_PERF_SEL_CB_BUSY', + 7: 'GRBM_PERF_SEL_DB_BUSY', + 8: 'GRBM_PERF_SEL_PA_BUSY', + 9: 'GRBM_PERF_SEL_SC_BUSY', + 11: 'GRBM_PERF_SEL_SPI_BUSY', + 12: 'GRBM_PERF_SEL_SX_BUSY', + 13: 'GRBM_PERF_SEL_TA_BUSY', + 14: 'GRBM_PERF_SEL_CB_CLEAN', + 15: 'GRBM_PERF_SEL_DB_CLEAN', + 25: 'GRBM_PERF_SEL_GDS_BUSY', + 26: 'GRBM_PERF_SEL_BCI_BUSY', + 27: 'GRBM_PERF_SEL_RLC_BUSY', + 28: 'GRBM_PERF_SEL_TCP_BUSY', + 29: 'GRBM_PERF_SEL_CPG_BUSY', + 30: 'GRBM_PERF_SEL_CPC_BUSY', + 31: 'GRBM_PERF_SEL_CPF_BUSY', + 32: 'GRBM_PERF_SEL_GE_BUSY', + 33: 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', + 34: 'GRBM_PERF_SEL_UTCL2_BUSY', + 35: 'GRBM_PERF_SEL_EA_BUSY', + 36: 'GRBM_PERF_SEL_RMI_BUSY', + 37: 'GRBM_PERF_SEL_CPAXI_BUSY', + 39: 'GRBM_PERF_SEL_UTCL1_BUSY', + 40: 'GRBM_PERF_SEL_GL2CC_BUSY', + 41: 'GRBM_PERF_SEL_SDMA_BUSY', + 42: 'GRBM_PERF_SEL_CH_BUSY', + 43: 'GRBM_PERF_SEL_PH_BUSY', + 44: 'GRBM_PERF_SEL_PMM_BUSY', + 45: 'GRBM_PERF_SEL_GUS_BUSY', + 46: 'GRBM_PERF_SEL_GL1CC_BUSY', + 47: 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', + 48: 'GRBM_PERF_SEL_GL1H_BUSY', + 49: 'GRBM_PERF_SEL_PC_BUSY', +} +GRBM_PERF_SEL_COUNT = 0 +GRBM_PERF_SEL_USER_DEFINED = 1 +GRBM_PERF_SEL_GUI_ACTIVE = 2 +GRBM_PERF_SEL_CP_BUSY = 3 +GRBM_PERF_SEL_CP_COHER_BUSY = 4 +GRBM_PERF_SEL_CP_DMA_BUSY = 5 +GRBM_PERF_SEL_CB_BUSY = 6 +GRBM_PERF_SEL_DB_BUSY = 7 +GRBM_PERF_SEL_PA_BUSY = 8 +GRBM_PERF_SEL_SC_BUSY = 9 +GRBM_PERF_SEL_SPI_BUSY = 11 +GRBM_PERF_SEL_SX_BUSY = 12 +GRBM_PERF_SEL_TA_BUSY = 13 +GRBM_PERF_SEL_CB_CLEAN = 14 +GRBM_PERF_SEL_DB_CLEAN = 15 +GRBM_PERF_SEL_GDS_BUSY = 25 +GRBM_PERF_SEL_BCI_BUSY = 26 +GRBM_PERF_SEL_RLC_BUSY = 27 +GRBM_PERF_SEL_TCP_BUSY = 28 +GRBM_PERF_SEL_CPG_BUSY = 29 +GRBM_PERF_SEL_CPC_BUSY = 30 +GRBM_PERF_SEL_CPF_BUSY = 31 +GRBM_PERF_SEL_GE_BUSY = 32 +GRBM_PERF_SEL_GE_NO_DMA_BUSY = 33 +GRBM_PERF_SEL_UTCL2_BUSY = 34 +GRBM_PERF_SEL_EA_BUSY = 35 +GRBM_PERF_SEL_RMI_BUSY = 36 +GRBM_PERF_SEL_CPAXI_BUSY = 37 +GRBM_PERF_SEL_UTCL1_BUSY = 39 +GRBM_PERF_SEL_GL2CC_BUSY = 40 +GRBM_PERF_SEL_SDMA_BUSY = 41 +GRBM_PERF_SEL_CH_BUSY = 42 +GRBM_PERF_SEL_PH_BUSY = 43 +GRBM_PERF_SEL_PMM_BUSY = 44 +GRBM_PERF_SEL_GUS_BUSY = 45 +GRBM_PERF_SEL_GL1CC_BUSY = 46 +GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 47 +GRBM_PERF_SEL_GL1H_BUSY = 48 +GRBM_PERF_SEL_PC_BUSY = 49 +GRBM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE0_PERF_SEL' +GRBM_SE0_PERF_SEL__enumvalues = { + 0: 'GRBM_SE0_PERF_SEL_COUNT', + 1: 'GRBM_SE0_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE0_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE0_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE0_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE0_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE0_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE0_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE0_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE0_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE0_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE0_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE0_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE0_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE0_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE0_PERF_SEL_PC_BUSY', +} +GRBM_SE0_PERF_SEL_COUNT = 0 +GRBM_SE0_PERF_SEL_USER_DEFINED = 1 +GRBM_SE0_PERF_SEL_CB_BUSY = 2 +GRBM_SE0_PERF_SEL_DB_BUSY = 3 +GRBM_SE0_PERF_SEL_SC_BUSY = 4 +GRBM_SE0_PERF_SEL_SPI_BUSY = 6 +GRBM_SE0_PERF_SEL_SX_BUSY = 7 +GRBM_SE0_PERF_SEL_TA_BUSY = 8 +GRBM_SE0_PERF_SEL_CB_CLEAN = 9 +GRBM_SE0_PERF_SEL_DB_CLEAN = 10 +GRBM_SE0_PERF_SEL_PA_BUSY = 12 +GRBM_SE0_PERF_SEL_BCI_BUSY = 14 +GRBM_SE0_PERF_SEL_RMI_BUSY = 15 +GRBM_SE0_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE0_PERF_SEL_TCP_BUSY = 17 +GRBM_SE0_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE0_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE0_PERF_SEL_PC_BUSY = 20 +GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE1_PERF_SEL' +GRBM_SE1_PERF_SEL__enumvalues = { + 0: 'GRBM_SE1_PERF_SEL_COUNT', + 1: 'GRBM_SE1_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE1_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE1_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE1_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE1_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE1_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE1_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE1_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE1_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE1_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE1_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE1_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE1_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE1_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE1_PERF_SEL_PC_BUSY', +} +GRBM_SE1_PERF_SEL_COUNT = 0 +GRBM_SE1_PERF_SEL_USER_DEFINED = 1 +GRBM_SE1_PERF_SEL_CB_BUSY = 2 +GRBM_SE1_PERF_SEL_DB_BUSY = 3 +GRBM_SE1_PERF_SEL_SC_BUSY = 4 +GRBM_SE1_PERF_SEL_SPI_BUSY = 6 +GRBM_SE1_PERF_SEL_SX_BUSY = 7 +GRBM_SE1_PERF_SEL_TA_BUSY = 8 +GRBM_SE1_PERF_SEL_CB_CLEAN = 9 +GRBM_SE1_PERF_SEL_DB_CLEAN = 10 +GRBM_SE1_PERF_SEL_PA_BUSY = 12 +GRBM_SE1_PERF_SEL_BCI_BUSY = 14 +GRBM_SE1_PERF_SEL_RMI_BUSY = 15 +GRBM_SE1_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE1_PERF_SEL_TCP_BUSY = 17 +GRBM_SE1_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE1_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE1_PERF_SEL_PC_BUSY = 20 +GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE2_PERF_SEL' +GRBM_SE2_PERF_SEL__enumvalues = { + 0: 'GRBM_SE2_PERF_SEL_COUNT', + 1: 'GRBM_SE2_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE2_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE2_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE2_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE2_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE2_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE2_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE2_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE2_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE2_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE2_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE2_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE2_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE2_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE2_PERF_SEL_PC_BUSY', +} +GRBM_SE2_PERF_SEL_COUNT = 0 +GRBM_SE2_PERF_SEL_USER_DEFINED = 1 +GRBM_SE2_PERF_SEL_CB_BUSY = 2 +GRBM_SE2_PERF_SEL_DB_BUSY = 3 +GRBM_SE2_PERF_SEL_SC_BUSY = 4 +GRBM_SE2_PERF_SEL_SPI_BUSY = 6 +GRBM_SE2_PERF_SEL_SX_BUSY = 7 +GRBM_SE2_PERF_SEL_TA_BUSY = 8 +GRBM_SE2_PERF_SEL_CB_CLEAN = 9 +GRBM_SE2_PERF_SEL_DB_CLEAN = 10 +GRBM_SE2_PERF_SEL_PA_BUSY = 12 +GRBM_SE2_PERF_SEL_BCI_BUSY = 14 +GRBM_SE2_PERF_SEL_RMI_BUSY = 15 +GRBM_SE2_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE2_PERF_SEL_TCP_BUSY = 17 +GRBM_SE2_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE2_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE2_PERF_SEL_PC_BUSY = 20 +GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE3_PERF_SEL' +GRBM_SE3_PERF_SEL__enumvalues = { + 0: 'GRBM_SE3_PERF_SEL_COUNT', + 1: 'GRBM_SE3_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE3_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE3_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE3_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE3_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE3_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE3_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE3_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE3_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE3_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE3_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE3_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE3_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE3_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE3_PERF_SEL_PC_BUSY', +} +GRBM_SE3_PERF_SEL_COUNT = 0 +GRBM_SE3_PERF_SEL_USER_DEFINED = 1 +GRBM_SE3_PERF_SEL_CB_BUSY = 2 +GRBM_SE3_PERF_SEL_DB_BUSY = 3 +GRBM_SE3_PERF_SEL_SC_BUSY = 4 +GRBM_SE3_PERF_SEL_SPI_BUSY = 6 +GRBM_SE3_PERF_SEL_SX_BUSY = 7 +GRBM_SE3_PERF_SEL_TA_BUSY = 8 +GRBM_SE3_PERF_SEL_CB_CLEAN = 9 +GRBM_SE3_PERF_SEL_DB_CLEAN = 10 +GRBM_SE3_PERF_SEL_PA_BUSY = 12 +GRBM_SE3_PERF_SEL_BCI_BUSY = 14 +GRBM_SE3_PERF_SEL_RMI_BUSY = 15 +GRBM_SE3_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE3_PERF_SEL_TCP_BUSY = 17 +GRBM_SE3_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE3_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE3_PERF_SEL_PC_BUSY = 20 +GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE4_PERF_SEL' +GRBM_SE4_PERF_SEL__enumvalues = { + 0: 'GRBM_SE4_PERF_SEL_COUNT', + 1: 'GRBM_SE4_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE4_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE4_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE4_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE4_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE4_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE4_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE4_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE4_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE4_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE4_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE4_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE4_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE4_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE4_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE4_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE4_PERF_SEL_PC_BUSY', +} +GRBM_SE4_PERF_SEL_COUNT = 0 +GRBM_SE4_PERF_SEL_USER_DEFINED = 1 +GRBM_SE4_PERF_SEL_CB_BUSY = 2 +GRBM_SE4_PERF_SEL_DB_BUSY = 3 +GRBM_SE4_PERF_SEL_SC_BUSY = 4 +GRBM_SE4_PERF_SEL_SPI_BUSY = 6 +GRBM_SE4_PERF_SEL_SX_BUSY = 7 +GRBM_SE4_PERF_SEL_TA_BUSY = 8 +GRBM_SE4_PERF_SEL_CB_CLEAN = 9 +GRBM_SE4_PERF_SEL_DB_CLEAN = 10 +GRBM_SE4_PERF_SEL_PA_BUSY = 12 +GRBM_SE4_PERF_SEL_BCI_BUSY = 14 +GRBM_SE4_PERF_SEL_RMI_BUSY = 15 +GRBM_SE4_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE4_PERF_SEL_TCP_BUSY = 17 +GRBM_SE4_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE4_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE4_PERF_SEL_PC_BUSY = 20 +GRBM_SE4_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE5_PERF_SEL' +GRBM_SE5_PERF_SEL__enumvalues = { + 0: 'GRBM_SE5_PERF_SEL_COUNT', + 1: 'GRBM_SE5_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE5_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE5_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE5_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE5_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE5_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE5_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE5_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE5_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE5_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE5_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE5_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE5_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE5_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE5_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE5_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE5_PERF_SEL_PC_BUSY', +} +GRBM_SE5_PERF_SEL_COUNT = 0 +GRBM_SE5_PERF_SEL_USER_DEFINED = 1 +GRBM_SE5_PERF_SEL_CB_BUSY = 2 +GRBM_SE5_PERF_SEL_DB_BUSY = 3 +GRBM_SE5_PERF_SEL_SC_BUSY = 4 +GRBM_SE5_PERF_SEL_SPI_BUSY = 6 +GRBM_SE5_PERF_SEL_SX_BUSY = 7 +GRBM_SE5_PERF_SEL_TA_BUSY = 8 +GRBM_SE5_PERF_SEL_CB_CLEAN = 9 +GRBM_SE5_PERF_SEL_DB_CLEAN = 10 +GRBM_SE5_PERF_SEL_PA_BUSY = 12 +GRBM_SE5_PERF_SEL_BCI_BUSY = 14 +GRBM_SE5_PERF_SEL_RMI_BUSY = 15 +GRBM_SE5_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE5_PERF_SEL_TCP_BUSY = 17 +GRBM_SE5_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE5_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE5_PERF_SEL_PC_BUSY = 20 +GRBM_SE5_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE6_PERF_SEL' +GRBM_SE6_PERF_SEL__enumvalues = { + 0: 'GRBM_SE6_PERF_SEL_COUNT', + 1: 'GRBM_SE6_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE6_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE6_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE6_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE6_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE6_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE6_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE6_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE6_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE6_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE6_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE6_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE6_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE6_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE6_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE6_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE6_PERF_SEL_PC_BUSY', +} +GRBM_SE6_PERF_SEL_COUNT = 0 +GRBM_SE6_PERF_SEL_USER_DEFINED = 1 +GRBM_SE6_PERF_SEL_CB_BUSY = 2 +GRBM_SE6_PERF_SEL_DB_BUSY = 3 +GRBM_SE6_PERF_SEL_SC_BUSY = 4 +GRBM_SE6_PERF_SEL_SPI_BUSY = 6 +GRBM_SE6_PERF_SEL_SX_BUSY = 7 +GRBM_SE6_PERF_SEL_TA_BUSY = 8 +GRBM_SE6_PERF_SEL_CB_CLEAN = 9 +GRBM_SE6_PERF_SEL_DB_CLEAN = 10 +GRBM_SE6_PERF_SEL_PA_BUSY = 12 +GRBM_SE6_PERF_SEL_BCI_BUSY = 14 +GRBM_SE6_PERF_SEL_RMI_BUSY = 15 +GRBM_SE6_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE6_PERF_SEL_TCP_BUSY = 17 +GRBM_SE6_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE6_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE6_PERF_SEL_PC_BUSY = 20 +GRBM_SE6_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE7_PERF_SEL' +GRBM_SE7_PERF_SEL__enumvalues = { + 0: 'GRBM_SE7_PERF_SEL_COUNT', + 1: 'GRBM_SE7_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE7_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE7_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE7_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE7_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE7_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE7_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE7_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE7_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE7_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE7_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE7_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE7_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE7_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE7_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE7_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE7_PERF_SEL_PC_BUSY', +} +GRBM_SE7_PERF_SEL_COUNT = 0 +GRBM_SE7_PERF_SEL_USER_DEFINED = 1 +GRBM_SE7_PERF_SEL_CB_BUSY = 2 +GRBM_SE7_PERF_SEL_DB_BUSY = 3 +GRBM_SE7_PERF_SEL_SC_BUSY = 4 +GRBM_SE7_PERF_SEL_SPI_BUSY = 6 +GRBM_SE7_PERF_SEL_SX_BUSY = 7 +GRBM_SE7_PERF_SEL_TA_BUSY = 8 +GRBM_SE7_PERF_SEL_CB_CLEAN = 9 +GRBM_SE7_PERF_SEL_DB_CLEAN = 10 +GRBM_SE7_PERF_SEL_PA_BUSY = 12 +GRBM_SE7_PERF_SEL_BCI_BUSY = 14 +GRBM_SE7_PERF_SEL_RMI_BUSY = 15 +GRBM_SE7_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE7_PERF_SEL_TCP_BUSY = 17 +GRBM_SE7_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE7_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE7_PERF_SEL_PC_BUSY = 20 +GRBM_SE7_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_COMPAT_LEVEL' +PIPE_COMPAT_LEVEL__enumvalues = { + 0: 'GEN_ZERO', + 1: 'GEN_ONE', + 2: 'GEN_TWO', + 3: 'GEN_RESERVED', +} +GEN_ZERO = 0 +GEN_ONE = 1 +GEN_TWO = 2 +GEN_RESERVED = 3 +PIPE_COMPAT_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPC_LATENCY_STATS_SEL' +CPC_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPC_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPC_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPC_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPC_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPC_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPC_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPC_LATENCY_STATS_SEL_INVAL_MAX', + 7: 'CPC_LATENCY_STATS_SEL_INVAL_MIN', + 8: 'CPC_LATENCY_STATS_SEL_INVAL_LAST', +} +CPC_LATENCY_STATS_SEL_XACK_MAX = 0 +CPC_LATENCY_STATS_SEL_XACK_MIN = 1 +CPC_LATENCY_STATS_SEL_XACK_LAST = 2 +CPC_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPC_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPC_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPC_LATENCY_STATS_SEL_INVAL_MAX = 6 +CPC_LATENCY_STATS_SEL_INVAL_MIN = 7 +CPC_LATENCY_STATS_SEL_INVAL_LAST = 8 +CPC_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPC_PERFCOUNT_SEL' +CPC_PERFCOUNT_SEL__enumvalues = { + 0: 'CPC_PERF_SEL_ALWAYS_COUNT', + 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', + 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', + 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', + 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', + 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 25: 'CPC_PERF_SEL_CPC_STAT_BUSY', + 26: 'CPC_PERF_SEL_CPC_STAT_IDLE', + 27: 'CPC_PERF_SEL_CPC_STAT_STALL', + 28: 'CPC_PERF_SEL_CPC_TCIU_BUSY', + 29: 'CPC_PERF_SEL_CPC_TCIU_IDLE', + 30: 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', + 31: 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', + 32: 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', + 33: 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', + 34: 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', + 35: 'CPC_PERF_SEL_CPC_GCRIU_BUSY', + 36: 'CPC_PERF_SEL_CPC_GCRIU_IDLE', + 37: 'CPC_PERF_SEL_CPC_GCRIU_STALL', + 38: 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 39: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', + 40: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', + 41: 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', + 42: 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', + 43: 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', + 44: 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', + 45: 'CPC_PERF_SEL_MES_THREAD0', + 46: 'CPC_PERF_SEL_MES_THREAD1', +} +CPC_PERF_SEL_ALWAYS_COUNT = 0 +CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 +CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 +CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 9 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 10 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 +CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 17 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 18 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 +CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 +CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 +CPC_PERF_SEL_CPC_STAT_BUSY = 25 +CPC_PERF_SEL_CPC_STAT_IDLE = 26 +CPC_PERF_SEL_CPC_STAT_STALL = 27 +CPC_PERF_SEL_CPC_TCIU_BUSY = 28 +CPC_PERF_SEL_CPC_TCIU_IDLE = 29 +CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 30 +CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 31 +CPC_PERF_SEL_CPC_UTCL2IU_STALL = 32 +CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 33 +CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 34 +CPC_PERF_SEL_CPC_GCRIU_BUSY = 35 +CPC_PERF_SEL_CPC_GCRIU_IDLE = 36 +CPC_PERF_SEL_CPC_GCRIU_STALL = 37 +CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 38 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 39 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 40 +CPC_PERF_SEL_CPC_UTCL2IU_XACK = 41 +CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 42 +CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 43 +CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 44 +CPC_PERF_SEL_MES_THREAD0 = 45 +CPC_PERF_SEL_MES_THREAD1 = 46 +CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_LATENCY_STATS_SEL' +CPF_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPF_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPF_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPF_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPF_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPF_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPF_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPF_LATENCY_STATS_SEL_READ_MAX', + 7: 'CPF_LATENCY_STATS_SEL_READ_MIN', + 8: 'CPF_LATENCY_STATS_SEL_READ_LAST', + 9: 'CPF_LATENCY_STATS_SEL_INVAL_MAX', + 10: 'CPF_LATENCY_STATS_SEL_INVAL_MIN', + 11: 'CPF_LATENCY_STATS_SEL_INVAL_LAST', +} +CPF_LATENCY_STATS_SEL_XACK_MAX = 0 +CPF_LATENCY_STATS_SEL_XACK_MIN = 1 +CPF_LATENCY_STATS_SEL_XACK_LAST = 2 +CPF_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPF_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPF_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPF_LATENCY_STATS_SEL_READ_MAX = 6 +CPF_LATENCY_STATS_SEL_READ_MIN = 7 +CPF_LATENCY_STATS_SEL_READ_LAST = 8 +CPF_LATENCY_STATS_SEL_INVAL_MAX = 9 +CPF_LATENCY_STATS_SEL_INVAL_MIN = 10 +CPF_LATENCY_STATS_SEL_INVAL_LAST = 11 +CPF_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_PERFCOUNTWINDOW_SEL' +CPF_PERFCOUNTWINDOW_SEL__enumvalues = { + 0: 'CPF_PERFWINDOW_SEL_CSF', + 1: 'CPF_PERFWINDOW_SEL_HQD1', + 2: 'CPF_PERFWINDOW_SEL_HQD2', + 3: 'CPF_PERFWINDOW_SEL_RDMA', + 4: 'CPF_PERFWINDOW_SEL_RWPP', +} +CPF_PERFWINDOW_SEL_CSF = 0 +CPF_PERFWINDOW_SEL_HQD1 = 1 +CPF_PERFWINDOW_SEL_HQD2 = 2 +CPF_PERFWINDOW_SEL_RDMA = 3 +CPF_PERFWINDOW_SEL_RWPP = 4 +CPF_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_PERFCOUNT_SEL' +CPF_PERFCOUNT_SEL__enumvalues = { + 0: 'CPF_PERF_SEL_ALWAYS_COUNT', + 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', + 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 15: 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 16: 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', + 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 19: 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', + 20: 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', + 21: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 22: 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 23: 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', + 24: 'CPF_PERF_SEL_CPF_STAT_BUSY', + 25: 'CPF_PERF_SEL_CPF_STAT_IDLE', + 26: 'CPF_PERF_SEL_CPF_STAT_STALL', + 27: 'CPF_PERF_SEL_CPF_TCIU_BUSY', + 28: 'CPF_PERF_SEL_CPF_TCIU_IDLE', + 29: 'CPF_PERF_SEL_CPF_TCIU_STALL', + 30: 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', + 31: 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', + 32: 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', + 33: 'CPF_PERF_SEL_CPF_GCRIU_BUSY', + 34: 'CPF_PERF_SEL_CPF_GCRIU_IDLE', + 35: 'CPF_PERF_SEL_CPF_GCRIU_STALL', + 36: 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 37: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', + 38: 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', + 39: 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', + 40: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', + 41: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', + 42: 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', + 43: 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', +} +CPF_PERF_SEL_ALWAYS_COUNT = 0 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 7 +CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 +CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 +CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 +CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 +CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 +CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 15 +CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 16 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 +CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 19 +CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 20 +CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 21 +CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 22 +CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 23 +CPF_PERF_SEL_CPF_STAT_BUSY = 24 +CPF_PERF_SEL_CPF_STAT_IDLE = 25 +CPF_PERF_SEL_CPF_STAT_STALL = 26 +CPF_PERF_SEL_CPF_TCIU_BUSY = 27 +CPF_PERF_SEL_CPF_TCIU_IDLE = 28 +CPF_PERF_SEL_CPF_TCIU_STALL = 29 +CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 30 +CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 31 +CPF_PERF_SEL_CPF_UTCL2IU_STALL = 32 +CPF_PERF_SEL_CPF_GCRIU_BUSY = 33 +CPF_PERF_SEL_CPF_GCRIU_IDLE = 34 +CPF_PERF_SEL_CPF_GCRIU_STALL = 35 +CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 36 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 37 +CPF_PERF_SEL_CPF_UTCL2IU_XACK = 38 +CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 39 +CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 40 +CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 41 +CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 42 +CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 43 +CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_SCRATCH_REG_ATOMIC_OP' +CPF_SCRATCH_REG_ATOMIC_OP__enumvalues = { + 0: 'CPF_SCRATCH_REG_ATOMIC_ADD', + 1: 'CPF_SCRATCH_REG_ATOMIC_SUB', + 2: 'CPF_SCRATCH_REG_ATOMIC_OR', + 3: 'CPF_SCRATCH_REG_ATOMIC_AND', + 4: 'CPF_SCRATCH_REG_ATOMIC_NOT', + 5: 'CPF_SCRATCH_REG_ATOMIC_MIN', + 6: 'CPF_SCRATCH_REG_ATOMIC_MAX', + 7: 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', +} +CPF_SCRATCH_REG_ATOMIC_ADD = 0 +CPF_SCRATCH_REG_ATOMIC_SUB = 1 +CPF_SCRATCH_REG_ATOMIC_OR = 2 +CPF_SCRATCH_REG_ATOMIC_AND = 3 +CPF_SCRATCH_REG_ATOMIC_NOT = 4 +CPF_SCRATCH_REG_ATOMIC_MIN = 5 +CPF_SCRATCH_REG_ATOMIC_MAX = 6 +CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 7 +CPF_SCRATCH_REG_ATOMIC_OP = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_LATENCY_STATS_SEL' +CPG_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPG_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPG_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPG_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPG_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPG_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPG_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPG_LATENCY_STATS_SEL_WRITE_MAX', + 7: 'CPG_LATENCY_STATS_SEL_WRITE_MIN', + 8: 'CPG_LATENCY_STATS_SEL_WRITE_LAST', + 9: 'CPG_LATENCY_STATS_SEL_READ_MAX', + 10: 'CPG_LATENCY_STATS_SEL_READ_MIN', + 11: 'CPG_LATENCY_STATS_SEL_READ_LAST', + 12: 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', + 13: 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', + 14: 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', + 15: 'CPG_LATENCY_STATS_SEL_INVAL_MAX', + 16: 'CPG_LATENCY_STATS_SEL_INVAL_MIN', + 17: 'CPG_LATENCY_STATS_SEL_INVAL_LAST', +} +CPG_LATENCY_STATS_SEL_XACK_MAX = 0 +CPG_LATENCY_STATS_SEL_XACK_MIN = 1 +CPG_LATENCY_STATS_SEL_XACK_LAST = 2 +CPG_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPG_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPG_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPG_LATENCY_STATS_SEL_WRITE_MAX = 6 +CPG_LATENCY_STATS_SEL_WRITE_MIN = 7 +CPG_LATENCY_STATS_SEL_WRITE_LAST = 8 +CPG_LATENCY_STATS_SEL_READ_MAX = 9 +CPG_LATENCY_STATS_SEL_READ_MIN = 10 +CPG_LATENCY_STATS_SEL_READ_LAST = 11 +CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 12 +CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 13 +CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 14 +CPG_LATENCY_STATS_SEL_INVAL_MAX = 15 +CPG_LATENCY_STATS_SEL_INVAL_MIN = 16 +CPG_LATENCY_STATS_SEL_INVAL_LAST = 17 +CPG_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_PERFCOUNTWINDOW_SEL' +CPG_PERFCOUNTWINDOW_SEL__enumvalues = { + 0: 'CPG_PERFWINDOW_SEL_PFP', + 1: 'CPG_PERFWINDOW_SEL_ME', + 2: 'CPG_PERFWINDOW_SEL_CE', + 3: 'CPG_PERFWINDOW_SEL_MES', + 4: 'CPG_PERFWINDOW_SEL_MEC1', + 5: 'CPG_PERFWINDOW_SEL_MEC2', + 6: 'CPG_PERFWINDOW_SEL_DFY', + 7: 'CPG_PERFWINDOW_SEL_DMA', + 8: 'CPG_PERFWINDOW_SEL_SHADOW', + 9: 'CPG_PERFWINDOW_SEL_RB', + 10: 'CPG_PERFWINDOW_SEL_CEDMA', + 11: 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', + 12: 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', + 13: 'CPG_PERFWINDOW_SEL_PQ1', + 14: 'CPG_PERFWINDOW_SEL_PQ2', + 15: 'CPG_PERFWINDOW_SEL_PQ3', + 16: 'CPG_PERFWINDOW_SEL_MEMWR', + 17: 'CPG_PERFWINDOW_SEL_MEMRD', + 18: 'CPG_PERFWINDOW_SEL_VGT0', + 19: 'CPG_PERFWINDOW_SEL_VGT1', + 20: 'CPG_PERFWINDOW_SEL_APPEND', + 21: 'CPG_PERFWINDOW_SEL_QURD', + 22: 'CPG_PERFWINDOW_SEL_DDID', + 23: 'CPG_PERFWINDOW_SEL_SR', + 24: 'CPG_PERFWINDOW_SEL_QU_EOP', + 25: 'CPG_PERFWINDOW_SEL_QU_STRM', + 26: 'CPG_PERFWINDOW_SEL_QU_PIPE', + 27: 'CPG_PERFWINDOW_SEL_RESERVED1', + 28: 'CPG_PERFWINDOW_SEL_CPC_IC', + 29: 'CPG_PERFWINDOW_SEL_RESERVED2', + 30: 'CPG_PERFWINDOW_SEL_CPG_IC', +} +CPG_PERFWINDOW_SEL_PFP = 0 +CPG_PERFWINDOW_SEL_ME = 1 +CPG_PERFWINDOW_SEL_CE = 2 +CPG_PERFWINDOW_SEL_MES = 3 +CPG_PERFWINDOW_SEL_MEC1 = 4 +CPG_PERFWINDOW_SEL_MEC2 = 5 +CPG_PERFWINDOW_SEL_DFY = 6 +CPG_PERFWINDOW_SEL_DMA = 7 +CPG_PERFWINDOW_SEL_SHADOW = 8 +CPG_PERFWINDOW_SEL_RB = 9 +CPG_PERFWINDOW_SEL_CEDMA = 10 +CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 11 +CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 12 +CPG_PERFWINDOW_SEL_PQ1 = 13 +CPG_PERFWINDOW_SEL_PQ2 = 14 +CPG_PERFWINDOW_SEL_PQ3 = 15 +CPG_PERFWINDOW_SEL_MEMWR = 16 +CPG_PERFWINDOW_SEL_MEMRD = 17 +CPG_PERFWINDOW_SEL_VGT0 = 18 +CPG_PERFWINDOW_SEL_VGT1 = 19 +CPG_PERFWINDOW_SEL_APPEND = 20 +CPG_PERFWINDOW_SEL_QURD = 21 +CPG_PERFWINDOW_SEL_DDID = 22 +CPG_PERFWINDOW_SEL_SR = 23 +CPG_PERFWINDOW_SEL_QU_EOP = 24 +CPG_PERFWINDOW_SEL_QU_STRM = 25 +CPG_PERFWINDOW_SEL_QU_PIPE = 26 +CPG_PERFWINDOW_SEL_RESERVED1 = 27 +CPG_PERFWINDOW_SEL_CPC_IC = 28 +CPG_PERFWINDOW_SEL_RESERVED2 = 29 +CPG_PERFWINDOW_SEL_CPG_IC = 30 +CPG_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_PERFCOUNT_SEL' +CPG_PERFCOUNT_SEL__enumvalues = { + 0: 'CPG_PERF_SEL_ALWAYS_COUNT', + 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', + 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', + 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 34: 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 35: 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', + 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 49: 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 50: 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', + 51: 'CPG_PERF_SEL_CPG_STAT_BUSY', + 52: 'CPG_PERF_SEL_CPG_STAT_IDLE', + 53: 'CPG_PERF_SEL_CPG_STAT_STALL', + 54: 'CPG_PERF_SEL_CPG_TCIU_BUSY', + 55: 'CPG_PERF_SEL_CPG_TCIU_IDLE', + 56: 'CPG_PERF_SEL_CPG_TCIU_STALL', + 57: 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', + 58: 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', + 59: 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', + 60: 'CPG_PERF_SEL_CPG_GCRIU_BUSY', + 61: 'CPG_PERF_SEL_CPG_GCRIU_IDLE', + 62: 'CPG_PERF_SEL_CPG_GCRIU_STALL', + 63: 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 64: 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', + 65: 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', + 66: 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', + 67: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', + 68: 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', + 69: 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', + 70: 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', + 71: 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', + 72: 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', + 73: 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', + 74: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', + 75: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', + 76: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', + 77: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', + 78: 'CPG_PERF_SEL_DMA_BUSY', + 79: 'CPG_PERF_SEL_DMA_STARVED', + 80: 'CPG_PERF_SEL_DMA_STALLED', + 81: 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', + 82: 'CPG_PERF_SEL_PFP_PWS_STALLED0', + 83: 'CPG_PERF_SEL_ME_PWS_STALLED0', + 84: 'CPG_PERF_SEL_PFP_PWS_STALLED1', + 85: 'CPG_PERF_SEL_ME_PWS_STALLED1', +} +CPG_PERF_SEL_ALWAYS_COUNT = 0 +CPG_PERF_SEL_RBIU_FIFO_FULL = 1 +CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 +CPG_PERF_SEL_ME_PARSER_BUSY = 5 +CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 +CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 +CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 +CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 +CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 +CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 +CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 +CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 +CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 +CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 +CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 +CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 +CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 +CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 +CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 +CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 +CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 +CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 +CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 +CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 +CPG_PERF_SEL_REGISTER_CLK_VALID = 33 +CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 34 +CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 35 +CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 +CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 +CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 +CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 +CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 +CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 +CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 +CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 49 +CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 50 +CPG_PERF_SEL_CPG_STAT_BUSY = 51 +CPG_PERF_SEL_CPG_STAT_IDLE = 52 +CPG_PERF_SEL_CPG_STAT_STALL = 53 +CPG_PERF_SEL_CPG_TCIU_BUSY = 54 +CPG_PERF_SEL_CPG_TCIU_IDLE = 55 +CPG_PERF_SEL_CPG_TCIU_STALL = 56 +CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 57 +CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 58 +CPG_PERF_SEL_CPG_UTCL2IU_STALL = 59 +CPG_PERF_SEL_CPG_GCRIU_BUSY = 60 +CPG_PERF_SEL_CPG_GCRIU_IDLE = 61 +CPG_PERF_SEL_CPG_GCRIU_STALL = 62 +CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 63 +CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 64 +CPG_PERF_SEL_CPG_UTCL2IU_XACK = 65 +CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 66 +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 67 +CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 68 +CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 69 +CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 70 +CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 71 +CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 72 +CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 73 +CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 74 +CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 75 +CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 76 +CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 77 +CPG_PERF_SEL_DMA_BUSY = 78 +CPG_PERF_SEL_DMA_STARVED = 79 +CPG_PERF_SEL_DMA_STALLED = 80 +CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 81 +CPG_PERF_SEL_PFP_PWS_STALLED0 = 82 +CPG_PERF_SEL_ME_PWS_STALLED0 = 83 +CPG_PERF_SEL_PFP_PWS_STALLED1 = 84 +CPG_PERF_SEL_ME_PWS_STALLED1 = 85 +CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ALPHA_TAG_RAM_SEL' +CP_ALPHA_TAG_RAM_SEL__enumvalues = { + 0: 'CPG_TAG_RAM', + 1: 'CPC_TAG_RAM', + 2: 'CPF_TAG_RAM', + 3: 'RSV_TAG_RAM', +} +CPG_TAG_RAM = 0 +CPC_TAG_RAM = 1 +CPF_TAG_RAM = 2 +RSV_TAG_RAM = 3 +CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_MODE' +CP_DDID_CNTL_MODE__enumvalues = { + 0: 'STALL', + 1: 'OVERRUN', +} +STALL = 0 +OVERRUN = 1 +CP_DDID_CNTL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_SIZE' +CP_DDID_CNTL_SIZE__enumvalues = { + 0: 'SIZE_8K', + 1: 'SIZE_16K', +} +SIZE_8K = 0 +SIZE_16K = 1 +CP_DDID_CNTL_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_VMID_SEL' +CP_DDID_CNTL_VMID_SEL__enumvalues = { + 0: 'DDID_VMID_PIPE', + 1: 'DDID_VMID_CNTL', +} +DDID_VMID_PIPE = 0 +DDID_VMID_CNTL = 1 +CP_DDID_CNTL_VMID_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ME_ID' +CP_ME_ID__enumvalues = { + 0: 'ME_ID0', + 1: 'ME_ID1', + 2: 'ME_ID2', + 3: 'ME_ID3', +} +ME_ID0 = 0 +ME_ID1 = 1 +ME_ID2 = 2 +ME_ID3 = 3 +CP_ME_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_ENABLE_MODE' +CP_PERFMON_ENABLE_MODE__enumvalues = { + 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', + 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', +} +CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 +CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 +CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_STATE' +CP_PERFMON_STATE__enumvalues = { + 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'CP_PERFMON_STATE_START_COUNTING', + 2: 'CP_PERFMON_STATE_STOP_COUNTING', + 3: 'CP_PERFMON_STATE_RESERVED_3', + 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +CP_PERFMON_STATE_DISABLE_AND_RESET = 0 +CP_PERFMON_STATE_START_COUNTING = 1 +CP_PERFMON_STATE_STOP_COUNTING = 2 +CP_PERFMON_STATE_RESERVED_3 = 3 +CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +CP_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PIPE_ID' +CP_PIPE_ID__enumvalues = { + 0: 'PIPE_ID0', + 1: 'PIPE_ID1', + 2: 'PIPE_ID2', + 3: 'PIPE_ID3', +} +PIPE_ID0 = 0 +PIPE_ID1 = 1 +PIPE_ID2 = 2 +PIPE_ID3 = 3 +CP_PIPE_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_RING_ID' +CP_RING_ID__enumvalues = { + 0: 'RINGID0', + 1: 'RINGID1', + 2: 'RINGID2', + 3: 'RINGID3', +} +RINGID0 = 0 +RINGID1 = 1 +RINGID2 = 2 +RINGID3 = 3 +CP_RING_ID = ctypes.c_uint32 # enum + +# values for enumeration 'SPM_PERFMON_STATE' +SPM_PERFMON_STATE__enumvalues = { + 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'STRM_PERFMON_STATE_START_COUNTING', + 2: 'STRM_PERFMON_STATE_STOP_COUNTING', + 3: 'STRM_PERFMON_STATE_RESERVED_3', + 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 +STRM_PERFMON_STATE_START_COUNTING = 1 +STRM_PERFMON_STATE_STOP_COUNTING = 2 +STRM_PERFMON_STATE_RESERVED_3 = 3 +STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +SPM_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'SX_BLEND_OPT' +SX_BLEND_OPT__enumvalues = { + 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', +} +BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 +BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 +BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 +BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 +BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 +BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 +BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 +BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 +SX_BLEND_OPT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_DOWNCONVERT_FORMAT' +SX_DOWNCONVERT_FORMAT__enumvalues = { + 0: 'SX_RT_EXPORT_NO_CONVERSION', + 1: 'SX_RT_EXPORT_32_R', + 2: 'SX_RT_EXPORT_32_A', + 3: 'SX_RT_EXPORT_10_11_11', + 4: 'SX_RT_EXPORT_2_10_10_10', + 5: 'SX_RT_EXPORT_8_8_8_8', + 6: 'SX_RT_EXPORT_5_6_5', + 7: 'SX_RT_EXPORT_1_5_5_5', + 8: 'SX_RT_EXPORT_4_4_4_4', + 9: 'SX_RT_EXPORT_16_16_GR', + 10: 'SX_RT_EXPORT_16_16_AR', + 11: 'SX_RT_EXPORT_9_9_9_E5', + 12: 'SX_RT_EXPORT_2_10_10_10_7E3', + 13: 'SX_RT_EXPORT_2_10_10_10_6E4', +} +SX_RT_EXPORT_NO_CONVERSION = 0 +SX_RT_EXPORT_32_R = 1 +SX_RT_EXPORT_32_A = 2 +SX_RT_EXPORT_10_11_11 = 3 +SX_RT_EXPORT_2_10_10_10 = 4 +SX_RT_EXPORT_8_8_8_8 = 5 +SX_RT_EXPORT_5_6_5 = 6 +SX_RT_EXPORT_1_5_5_5 = 7 +SX_RT_EXPORT_4_4_4_4 = 8 +SX_RT_EXPORT_16_16_GR = 9 +SX_RT_EXPORT_16_16_AR = 10 +SX_RT_EXPORT_9_9_9_E5 = 11 +SX_RT_EXPORT_2_10_10_10_7E3 = 12 +SX_RT_EXPORT_2_10_10_10_6E4 = 13 +SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_OPT_COMB_FCN' +SX_OPT_COMB_FCN__enumvalues = { + 0: 'OPT_COMB_NONE', + 1: 'OPT_COMB_ADD', + 2: 'OPT_COMB_SUBTRACT', + 3: 'OPT_COMB_MIN', + 4: 'OPT_COMB_MAX', + 5: 'OPT_COMB_REVSUBTRACT', + 6: 'OPT_COMB_BLEND_DISABLED', + 7: 'OPT_COMB_SAFE_ADD', +} +OPT_COMB_NONE = 0 +OPT_COMB_ADD = 1 +OPT_COMB_SUBTRACT = 2 +OPT_COMB_MIN = 3 +OPT_COMB_MAX = 4 +OPT_COMB_REVSUBTRACT = 5 +OPT_COMB_BLEND_DISABLED = 6 +OPT_COMB_SAFE_ADD = 7 +SX_OPT_COMB_FCN = ctypes.c_uint32 # enum + +# values for enumeration 'SX_PERFCOUNTER_VALS' +SX_PERFCOUNTER_VALS__enumvalues = { + 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', + 1: 'SX_PERF_SEL_PA_REQ', + 2: 'SX_PERF_SEL_PA_POS', + 3: 'SX_PERF_SEL_CLOCK', + 4: 'SX_PERF_SEL_GATE_EN1', + 5: 'SX_PERF_SEL_GATE_EN2', + 6: 'SX_PERF_SEL_GATE_EN3', + 7: 'SX_PERF_SEL_GATE_EN4', + 8: 'SX_PERF_SEL_SH_POS_STARVE', + 9: 'SX_PERF_SEL_SH_COLOR_STARVE', + 10: 'SX_PERF_SEL_SH_POS_STALL', + 11: 'SX_PERF_SEL_SH_COLOR_STALL', + 12: 'SX_PERF_SEL_DB0_PIXELS', + 13: 'SX_PERF_SEL_DB0_HALF_QUADS', + 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', + 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', + 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', + 17: 'SX_PERF_SEL_DB1_PIXELS', + 18: 'SX_PERF_SEL_DB1_HALF_QUADS', + 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', + 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', + 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', + 22: 'SX_PERF_SEL_DB2_PIXELS', + 23: 'SX_PERF_SEL_DB2_HALF_QUADS', + 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', + 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', + 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', + 27: 'SX_PERF_SEL_DB3_PIXELS', + 28: 'SX_PERF_SEL_DB3_HALF_QUADS', + 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', + 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', + 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', + 32: 'SX_PERF_SEL_COL_BUSY', + 33: 'SX_PERF_SEL_POS_BUSY', + 34: 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', + 35: 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', + 36: 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', + 37: 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', + 38: 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', + 39: 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', + 40: 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', + 41: 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', + 42: 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', + 43: 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', + 44: 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', + 45: 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', + 46: 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', + 47: 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', + 48: 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', + 49: 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', + 50: 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', + 51: 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', + 52: 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', + 53: 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', + 54: 'SX_PERF_SEL_PA_REQ_LATENCY', + 55: 'SX_PERF_SEL_POS_SCBD_STALL', + 56: 'SX_PERF_SEL_CLOCK_DROP_STALL', + 57: 'SX_PERF_SEL_GATE_EN5', + 58: 'SX_PERF_SEL_GATE_EN6', + 59: 'SX_PERF_SEL_DB0_SIZE', + 60: 'SX_PERF_SEL_DB1_SIZE', + 61: 'SX_PERF_SEL_DB2_SIZE', + 62: 'SX_PERF_SEL_DB3_SIZE', + 63: 'SX_PERF_SEL_IDX_STALL_CYCLES', + 64: 'SX_PERF_SEL_IDX_IDLE_CYCLES', + 65: 'SX_PERF_SEL_IDX_REQ', + 66: 'SX_PERF_SEL_IDX_RET', + 67: 'SX_PERF_SEL_IDX_REQ_LATENCY', + 68: 'SX_PERF_SEL_IDX_SCBD_STALL', + 69: 'SX_PERF_SEL_GATE_EN7', + 70: 'SX_PERF_SEL_GATE_EN8', + 71: 'SX_PERF_SEL_SH_IDX_STARVE', + 72: 'SX_PERF_SEL_IDX_BUSY', + 73: 'SX_PERF_SEL_PA_POS_BANK_CONF', + 74: 'SX_PERF_SEL_DB0_END_OF_WAVE', + 75: 'SX_PERF_SEL_DB0_4X2_DISCARD', + 76: 'SX_PERF_SEL_DB1_END_OF_WAVE', + 77: 'SX_PERF_SEL_DB1_4X2_DISCARD', + 78: 'SX_PERF_SEL_DB2_END_OF_WAVE', + 79: 'SX_PERF_SEL_DB2_4X2_DISCARD', + 80: 'SX_PERF_SEL_DB3_END_OF_WAVE', + 81: 'SX_PERF_SEL_DB3_4X2_DISCARD', +} +SX_PERF_SEL_PA_IDLE_CYCLES = 0 +SX_PERF_SEL_PA_REQ = 1 +SX_PERF_SEL_PA_POS = 2 +SX_PERF_SEL_CLOCK = 3 +SX_PERF_SEL_GATE_EN1 = 4 +SX_PERF_SEL_GATE_EN2 = 5 +SX_PERF_SEL_GATE_EN3 = 6 +SX_PERF_SEL_GATE_EN4 = 7 +SX_PERF_SEL_SH_POS_STARVE = 8 +SX_PERF_SEL_SH_COLOR_STARVE = 9 +SX_PERF_SEL_SH_POS_STALL = 10 +SX_PERF_SEL_SH_COLOR_STALL = 11 +SX_PERF_SEL_DB0_PIXELS = 12 +SX_PERF_SEL_DB0_HALF_QUADS = 13 +SX_PERF_SEL_DB0_PIXEL_STALL = 14 +SX_PERF_SEL_DB0_PIXEL_IDLE = 15 +SX_PERF_SEL_DB0_PRED_PIXELS = 16 +SX_PERF_SEL_DB1_PIXELS = 17 +SX_PERF_SEL_DB1_HALF_QUADS = 18 +SX_PERF_SEL_DB1_PIXEL_STALL = 19 +SX_PERF_SEL_DB1_PIXEL_IDLE = 20 +SX_PERF_SEL_DB1_PRED_PIXELS = 21 +SX_PERF_SEL_DB2_PIXELS = 22 +SX_PERF_SEL_DB2_HALF_QUADS = 23 +SX_PERF_SEL_DB2_PIXEL_STALL = 24 +SX_PERF_SEL_DB2_PIXEL_IDLE = 25 +SX_PERF_SEL_DB2_PRED_PIXELS = 26 +SX_PERF_SEL_DB3_PIXELS = 27 +SX_PERF_SEL_DB3_HALF_QUADS = 28 +SX_PERF_SEL_DB3_PIXEL_STALL = 29 +SX_PERF_SEL_DB3_PIXEL_IDLE = 30 +SX_PERF_SEL_DB3_PRED_PIXELS = 31 +SX_PERF_SEL_COL_BUSY = 32 +SX_PERF_SEL_POS_BUSY = 33 +SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 34 +SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 35 +SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 36 +SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 37 +SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 38 +SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 39 +SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 40 +SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 41 +SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 42 +SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 43 +SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 44 +SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 45 +SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 46 +SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 47 +SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 48 +SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 49 +SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 50 +SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 51 +SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 52 +SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 53 +SX_PERF_SEL_PA_REQ_LATENCY = 54 +SX_PERF_SEL_POS_SCBD_STALL = 55 +SX_PERF_SEL_CLOCK_DROP_STALL = 56 +SX_PERF_SEL_GATE_EN5 = 57 +SX_PERF_SEL_GATE_EN6 = 58 +SX_PERF_SEL_DB0_SIZE = 59 +SX_PERF_SEL_DB1_SIZE = 60 +SX_PERF_SEL_DB2_SIZE = 61 +SX_PERF_SEL_DB3_SIZE = 62 +SX_PERF_SEL_IDX_STALL_CYCLES = 63 +SX_PERF_SEL_IDX_IDLE_CYCLES = 64 +SX_PERF_SEL_IDX_REQ = 65 +SX_PERF_SEL_IDX_RET = 66 +SX_PERF_SEL_IDX_REQ_LATENCY = 67 +SX_PERF_SEL_IDX_SCBD_STALL = 68 +SX_PERF_SEL_GATE_EN7 = 69 +SX_PERF_SEL_GATE_EN8 = 70 +SX_PERF_SEL_SH_IDX_STARVE = 71 +SX_PERF_SEL_IDX_BUSY = 72 +SX_PERF_SEL_PA_POS_BANK_CONF = 73 +SX_PERF_SEL_DB0_END_OF_WAVE = 74 +SX_PERF_SEL_DB0_4X2_DISCARD = 75 +SX_PERF_SEL_DB1_END_OF_WAVE = 76 +SX_PERF_SEL_DB1_4X2_DISCARD = 77 +SX_PERF_SEL_DB2_END_OF_WAVE = 78 +SX_PERF_SEL_DB2_4X2_DISCARD = 79 +SX_PERF_SEL_DB3_END_OF_WAVE = 80 +SX_PERF_SEL_DB3_4X2_DISCARD = 81 +SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum + +# values for enumeration 'CompareFrag' +CompareFrag__enumvalues = { + 0: 'FRAG_NEVER', + 1: 'FRAG_LESS', + 2: 'FRAG_EQUAL', + 3: 'FRAG_LEQUAL', + 4: 'FRAG_GREATER', + 5: 'FRAG_NOTEQUAL', + 6: 'FRAG_GEQUAL', + 7: 'FRAG_ALWAYS', +} +FRAG_NEVER = 0 +FRAG_LESS = 1 +FRAG_EQUAL = 2 +FRAG_LEQUAL = 3 +FRAG_GREATER = 4 +FRAG_NOTEQUAL = 5 +FRAG_GEQUAL = 6 +FRAG_ALWAYS = 7 +CompareFrag = ctypes.c_uint32 # enum + +# values for enumeration 'ConservativeZExport' +ConservativeZExport__enumvalues = { + 0: 'EXPORT_ANY_Z', + 1: 'EXPORT_LESS_THAN_Z', + 2: 'EXPORT_GREATER_THAN_Z', + 3: 'EXPORT_RESERVED', +} +EXPORT_ANY_Z = 0 +EXPORT_LESS_THAN_Z = 1 +EXPORT_GREATER_THAN_Z = 2 +EXPORT_RESERVED = 3 +ConservativeZExport = ctypes.c_uint32 # enum + +# values for enumeration 'DFSMFlushEvents' +DFSMFlushEvents__enumvalues = { + 0: 'DB_FLUSH_AND_INV_DB_DATA_TS', + 1: 'DB_FLUSH_AND_INV_DB_META', + 2: 'DB_CACHE_FLUSH', + 3: 'DB_CACHE_FLUSH_TS', + 4: 'DB_CACHE_FLUSH_AND_INV_EVENT', + 5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', + 6: 'DB_VPORT_CHANGED_EVENT', + 7: 'DB_CONTEXT_DONE_EVENT', + 8: 'DB_BREAK_BATCH_EVENT', + 9: 'DB_INVOKE_CHANGE_EVENT', + 10: 'DB_CONTEXT_SUSPEND_EVENT', +} +DB_FLUSH_AND_INV_DB_DATA_TS = 0 +DB_FLUSH_AND_INV_DB_META = 1 +DB_CACHE_FLUSH = 2 +DB_CACHE_FLUSH_TS = 3 +DB_CACHE_FLUSH_AND_INV_EVENT = 4 +DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5 +DB_VPORT_CHANGED_EVENT = 6 +DB_CONTEXT_DONE_EVENT = 7 +DB_BREAK_BATCH_EVENT = 8 +DB_INVOKE_CHANGE_EVENT = 9 +DB_CONTEXT_SUSPEND_EVENT = 10 +DFSMFlushEvents = ctypes.c_uint32 # enum + +# values for enumeration 'DbMemArbWatermarks' +DbMemArbWatermarks__enumvalues = { + 0: 'TRANSFERRED_64_BYTES', + 1: 'TRANSFERRED_128_BYTES', + 2: 'TRANSFERRED_256_BYTES', + 3: 'TRANSFERRED_512_BYTES', + 4: 'TRANSFERRED_1024_BYTES', + 5: 'TRANSFERRED_2048_BYTES', + 6: 'TRANSFERRED_4096_BYTES', + 7: 'TRANSFERRED_8192_BYTES', +} +TRANSFERRED_64_BYTES = 0 +TRANSFERRED_128_BYTES = 1 +TRANSFERRED_256_BYTES = 2 +TRANSFERRED_512_BYTES = 3 +TRANSFERRED_1024_BYTES = 4 +TRANSFERRED_2048_BYTES = 5 +TRANSFERRED_4096_BYTES = 6 +TRANSFERRED_8192_BYTES = 7 +DbMemArbWatermarks = ctypes.c_uint32 # enum + +# values for enumeration 'DbPRTFaultBehavior' +DbPRTFaultBehavior__enumvalues = { + 0: 'FAULT_ZERO', + 1: 'FAULT_ONE', + 2: 'FAULT_FAIL', + 3: 'FAULT_PASS', +} +FAULT_ZERO = 0 +FAULT_ONE = 1 +FAULT_FAIL = 2 +FAULT_PASS = 3 +DbPRTFaultBehavior = ctypes.c_uint32 # enum + +# values for enumeration 'DbPSLControl' +DbPSLControl__enumvalues = { + 0: 'PSLC_AUTO', + 1: 'PSLC_ON_HANG_ONLY', + 2: 'PSLC_ASAP', + 3: 'PSLC_COUNTDOWN', +} +PSLC_AUTO = 0 +PSLC_ON_HANG_ONLY = 1 +PSLC_ASAP = 2 +PSLC_COUNTDOWN = 3 +DbPSLControl = ctypes.c_uint32 # enum + +# values for enumeration 'ForceControl' +ForceControl__enumvalues = { + 0: 'FORCE_OFF', + 1: 'FORCE_ENABLE', + 2: 'FORCE_DISABLE', + 3: 'FORCE_RESERVED', +} +FORCE_OFF = 0 +FORCE_ENABLE = 1 +FORCE_DISABLE = 2 +FORCE_RESERVED = 3 +ForceControl = ctypes.c_uint32 # enum + +# values for enumeration 'OreoMode' +OreoMode__enumvalues = { + 0: 'OMODE_BLEND', + 1: 'OMODE_O_THEN_B', + 2: 'OMODE_P_THEN_O_THEN_B', + 3: 'OMODE_RESERVED_3', +} +OMODE_BLEND = 0 +OMODE_O_THEN_B = 1 +OMODE_P_THEN_O_THEN_B = 2 +OMODE_RESERVED_3 = 3 +OreoMode = ctypes.c_uint32 # enum + +# values for enumeration 'PerfCounter_Vals' +PerfCounter_Vals__enumvalues = { + 0: 'DB_PERF_SEL_SC_DB_tile_sends', + 1: 'DB_PERF_SEL_SC_DB_tile_busy', + 2: 'DB_PERF_SEL_SC_DB_tile_stalls', + 3: 'DB_PERF_SEL_SC_DB_tile_events', + 4: 'DB_PERF_SEL_SC_DB_tile_tiles', + 5: 'DB_PERF_SEL_SC_DB_tile_covered', + 6: 'DB_PERF_SEL_hiz_tc_read_starved', + 7: 'DB_PERF_SEL_hiz_tc_write_stall', + 8: 'DB_PERF_SEL_hiz_tile_culled', + 9: 'DB_PERF_SEL_his_tile_culled', + 10: 'DB_PERF_SEL_DB_SC_tile_sends', + 11: 'DB_PERF_SEL_DB_SC_tile_busy', + 12: 'DB_PERF_SEL_DB_SC_tile_stalls', + 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 14: 'DB_PERF_SEL_DB_SC_tile_tiles', + 15: 'DB_PERF_SEL_DB_SC_tile_culled', + 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', + 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 23: 'DB_PERF_SEL_SC_DB_quad_sends', + 24: 'DB_PERF_SEL_SC_DB_quad_busy', + 25: 'DB_PERF_SEL_SC_DB_quad_squads', + 26: 'DB_PERF_SEL_SC_DB_quad_tiles', + 27: 'DB_PERF_SEL_SC_DB_quad_pixels', + 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 29: 'DB_PERF_SEL_DB_SC_quad_sends', + 30: 'DB_PERF_SEL_DB_SC_quad_busy', + 31: 'DB_PERF_SEL_DB_SC_quad_stalls', + 32: 'DB_PERF_SEL_DB_SC_quad_tiles', + 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', + 34: 'DB_PERF_SEL_DB_CB_tile_sends', + 35: 'DB_PERF_SEL_DB_CB_tile_busy', + 36: 'DB_PERF_SEL_DB_CB_tile_stalls', + 37: 'DB_PERF_SEL_SX_DB_quad_sends', + 38: 'DB_PERF_SEL_SX_DB_quad_busy', + 39: 'DB_PERF_SEL_SX_DB_quad_stalls', + 40: 'DB_PERF_SEL_SX_DB_quad_quads', + 41: 'DB_PERF_SEL_SX_DB_quad_pixels', + 42: 'DB_PERF_SEL_SX_DB_quad_exports', + 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', + 44: 'DB_PERF_SEL_DB_CB_lquad_sends', + 45: 'DB_PERF_SEL_DB_CB_lquad_busy', + 46: 'DB_PERF_SEL_DB_CB_lquad_stalls', + 47: 'DB_PERF_SEL_DB_CB_lquad_quads', + 48: 'DB_PERF_SEL_tile_rd_sends', + 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 50: 'DB_PERF_SEL_quad_rd_sends', + 51: 'DB_PERF_SEL_quad_rd_busy', + 52: 'DB_PERF_SEL_quad_rd_mi_stall', + 53: 'DB_PERF_SEL_quad_rd_rw_collision', + 54: 'DB_PERF_SEL_quad_rd_tag_stall', + 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', + 56: 'DB_PERF_SEL_quad_rd_panic', + 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 58: 'DB_PERF_SEL_quad_rdret_sends', + 59: 'DB_PERF_SEL_quad_rdret_busy', + 60: 'DB_PERF_SEL_tile_wr_sends', + 61: 'DB_PERF_SEL_tile_wr_acks', + 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 63: 'DB_PERF_SEL_quad_wr_sends', + 64: 'DB_PERF_SEL_quad_wr_busy', + 65: 'DB_PERF_SEL_quad_wr_mi_stall', + 66: 'DB_PERF_SEL_quad_wr_coherency_stall', + 67: 'DB_PERF_SEL_quad_wr_acks', + 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 69: 'DB_PERF_SEL_Tile_Cache_misses', + 70: 'DB_PERF_SEL_Tile_Cache_hits', + 71: 'DB_PERF_SEL_Tile_Cache_flushes', + 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', + 73: 'DB_PERF_SEL_Tile_Cache_starves', + 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 75: 'DB_PERF_SEL_tcp_dispatcher_reads', + 76: 'DB_PERF_SEL_tcp_prefetcher_reads', + 77: 'DB_PERF_SEL_tcp_preloader_reads', + 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', + 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', + 80: 'DB_PERF_SEL_tcp_preloader_flushes', + 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', + 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 95: 'DB_PERF_SEL_Stencil_Cache_misses', + 96: 'DB_PERF_SEL_Stencil_Cache_hits', + 97: 'DB_PERF_SEL_Stencil_Cache_flushes', + 98: 'DB_PERF_SEL_Stencil_Cache_starves', + 99: 'DB_PERF_SEL_Stencil_Cache_frees', + 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', + 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', + 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', + 108: 'DB_PERF_SEL_Z_Cache_frees', + 109: 'DB_PERF_SEL_Plane_Cache_misses', + 110: 'DB_PERF_SEL_Plane_Cache_hits', + 111: 'DB_PERF_SEL_Plane_Cache_flushes', + 112: 'DB_PERF_SEL_Plane_Cache_starves', + 113: 'DB_PERF_SEL_Plane_Cache_frees', + 114: 'DB_PERF_SEL_flush_expanded_stencil', + 115: 'DB_PERF_SEL_flush_compressed_stencil', + 116: 'DB_PERF_SEL_flush_single_stencil', + 117: 'DB_PERF_SEL_planes_flushed', + 118: 'DB_PERF_SEL_flush_1plane', + 119: 'DB_PERF_SEL_flush_2plane', + 120: 'DB_PERF_SEL_flush_3plane', + 121: 'DB_PERF_SEL_flush_4plane', + 122: 'DB_PERF_SEL_flush_5plane', + 123: 'DB_PERF_SEL_flush_6plane', + 124: 'DB_PERF_SEL_flush_7plane', + 125: 'DB_PERF_SEL_flush_8plane', + 126: 'DB_PERF_SEL_flush_9plane', + 127: 'DB_PERF_SEL_flush_10plane', + 128: 'DB_PERF_SEL_flush_11plane', + 129: 'DB_PERF_SEL_flush_12plane', + 130: 'DB_PERF_SEL_flush_13plane', + 131: 'DB_PERF_SEL_flush_14plane', + 132: 'DB_PERF_SEL_flush_15plane', + 133: 'DB_PERF_SEL_flush_16plane', + 134: 'DB_PERF_SEL_flush_expanded_z', + 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 137: 'DB_PERF_SEL_dk_tile_sends', + 138: 'DB_PERF_SEL_dk_tile_busy', + 139: 'DB_PERF_SEL_dk_tile_quad_starves', + 140: 'DB_PERF_SEL_dk_tile_stalls', + 141: 'DB_PERF_SEL_dk_squad_sends', + 142: 'DB_PERF_SEL_dk_squad_busy', + 143: 'DB_PERF_SEL_dk_squad_stalls', + 144: 'DB_PERF_SEL_Op_Pipe_Busy', + 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 146: 'DB_PERF_SEL_qc_busy', + 147: 'DB_PERF_SEL_qc_xfc', + 148: 'DB_PERF_SEL_qc_conflicts', + 149: 'DB_PERF_SEL_qc_full_stall', + 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', + 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', + 153: 'DB_PERF_SEL_tl_busy', + 154: 'DB_PERF_SEL_tl_dtc_read_starved', + 155: 'DB_PERF_SEL_tl_z_fetch_stall', + 156: 'DB_PERF_SEL_tl_stencil_stall', + 157: 'DB_PERF_SEL_tl_z_decompress_stall', + 158: 'DB_PERF_SEL_tl_stencil_locked_stall', + 159: 'DB_PERF_SEL_tl_events', + 160: 'DB_PERF_SEL_tl_summarize_squads', + 161: 'DB_PERF_SEL_tl_flush_expand_squads', + 162: 'DB_PERF_SEL_tl_expand_squads', + 163: 'DB_PERF_SEL_tl_preZ_squads', + 164: 'DB_PERF_SEL_tl_postZ_squads', + 165: 'DB_PERF_SEL_tl_preZ_noop_squads', + 166: 'DB_PERF_SEL_tl_postZ_noop_squads', + 167: 'DB_PERF_SEL_tl_tile_ops', + 168: 'DB_PERF_SEL_tl_in_xfc', + 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 170: 'DB_PERF_SEL_tl_in_fast_z_stall', + 171: 'DB_PERF_SEL_tl_out_xfc', + 172: 'DB_PERF_SEL_tl_out_squads', + 173: 'DB_PERF_SEL_zf_plane_multicycle', + 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', + 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', + 180: 'DB_PERF_SEL_ts_tc_update_stall', + 181: 'DB_PERF_SEL_sc_kick_start', + 182: 'DB_PERF_SEL_sc_kick_end', + 183: 'DB_PERF_SEL_clock_reg_active', + 184: 'DB_PERF_SEL_clock_main_active', + 185: 'DB_PERF_SEL_clock_mem_export_active', + 186: 'DB_PERF_SEL_esr_ps_out_busy', + 187: 'DB_PERF_SEL_esr_ps_lqf_busy', + 188: 'DB_PERF_SEL_esr_ps_lqf_stall', + 189: 'DB_PERF_SEL_etr_out_send', + 190: 'DB_PERF_SEL_etr_out_busy', + 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 192: 'DB_PERF_SEL_etr_out_cb_tile_stall', + 193: 'DB_PERF_SEL_etr_out_esr_stall', + 194: 'DB_PERF_SEL_esr_ps_vic_busy', + 195: 'DB_PERF_SEL_esr_ps_vic_stall', + 196: 'DB_PERF_SEL_esr_eot_fwd_busy', + 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 198: 'DB_PERF_SEL_esr_eot_fwd_forward', + 199: 'DB_PERF_SEL_esr_sqq_zi_busy', + 200: 'DB_PERF_SEL_esr_sqq_zi_stall', + 201: 'DB_PERF_SEL_postzl_sq_pt_busy', + 202: 'DB_PERF_SEL_postzl_sq_pt_stall', + 203: 'DB_PERF_SEL_postzl_se_busy', + 204: 'DB_PERF_SEL_postzl_se_stall', + 205: 'DB_PERF_SEL_postzl_partial_launch', + 206: 'DB_PERF_SEL_postzl_full_launch', + 207: 'DB_PERF_SEL_postzl_partial_waiting', + 208: 'DB_PERF_SEL_postzl_tile_mem_stall', + 209: 'DB_PERF_SEL_postzl_tile_init_stall', + 210: 'DB_PERF_SEL_prezl_tile_mem_stall', + 211: 'DB_PERF_SEL_prezl_tile_init_stall', + 212: 'DB_PERF_SEL_dtt_sm_clash_stall', + 213: 'DB_PERF_SEL_dtt_sm_slot_stall', + 214: 'DB_PERF_SEL_dtt_sm_miss_stall', + 215: 'DB_PERF_SEL_mi_rdreq_busy', + 216: 'DB_PERF_SEL_mi_rdreq_stall', + 217: 'DB_PERF_SEL_mi_wrreq_busy', + 218: 'DB_PERF_SEL_mi_wrreq_stall', + 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 220: 'DB_PERF_SEL_dkg_tile_rate_tile', + 221: 'DB_PERF_SEL_prezl_src_in_sends', + 222: 'DB_PERF_SEL_prezl_src_in_stall', + 223: 'DB_PERF_SEL_prezl_src_in_squads', + 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', + 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 227: 'DB_PERF_SEL_prezl_src_out_stall', + 228: 'DB_PERF_SEL_postzl_src_in_sends', + 229: 'DB_PERF_SEL_postzl_src_in_stall', + 230: 'DB_PERF_SEL_postzl_src_in_squads', + 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', + 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 234: 'DB_PERF_SEL_postzl_src_out_stall', + 235: 'DB_PERF_SEL_esr_ps_src_in_sends', + 236: 'DB_PERF_SEL_esr_ps_src_in_stall', + 237: 'DB_PERF_SEL_esr_ps_src_in_squads', + 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 242: 'DB_PERF_SEL_esr_ps_src_out_stall', + 243: 'DB_PERF_SEL_depth_bounds_tile_culled', + 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 246: 'DB_PERF_SEL_flush_compressed', + 247: 'DB_PERF_SEL_flush_plane_le4', + 248: 'DB_PERF_SEL_tiles_z_fully_summarized', + 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', + 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', + 256: 'DB_PERF_SEL_di_dt_stall', + 257: 'Spare_257', + 258: 'DB_PERF_SEL_DB_SC_s_tile_rate', + 259: 'DB_PERF_SEL_DB_SC_c_tile_rate', + 260: 'DB_PERF_SEL_DB_SC_z_tile_rate', + 261: 'DB_PERF_SEL_DB_CB_lquad_export_quads', + 262: 'DB_PERF_SEL_DB_CB_lquad_double_format', + 263: 'DB_PERF_SEL_DB_CB_lquad_fast_format', + 264: 'DB_PERF_SEL_DB_CB_lquad_slow_format', + 265: 'DB_PERF_SEL_CB_DB_rdreq_sends', + 266: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 267: 'DB_PERF_SEL_CB_DB_wrreq_sends', + 268: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 269: 'DB_PERF_SEL_DB_CB_rdret_ack', + 270: 'DB_PERF_SEL_DB_CB_rdret_nack', + 271: 'DB_PERF_SEL_DB_CB_wrret_ack', + 272: 'DB_PERF_SEL_DB_CB_wrret_nack', + 273: 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', + 274: 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', + 275: 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', + 276: 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', + 277: 'DB_PERF_SEL_unmapped_z_tile_culled', + 278: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', + 279: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', + 280: 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', + 281: 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', + 282: 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', + 283: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', + 284: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', + 285: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', + 286: 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', + 287: 'DB_PERF_SEL_DB_CB_context_dones', + 288: 'DB_PERF_SEL_DB_CB_eop_dones', + 289: 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', + 290: 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', + 291: 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', + 292: 'DB_PERF_SEL_SC_DB_tile_backface', + 293: 'DB_PERF_SEL_SC_DB_quad_quads', + 294: 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', + 295: 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', + 296: 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', + 297: 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', + 298: 'DB_PERF_SEL_DB_SC_quad_double_quad', + 299: 'DB_PERF_SEL_SX_DB_quad_export_quads', + 300: 'DB_PERF_SEL_SX_DB_quad_double_format', + 301: 'DB_PERF_SEL_SX_DB_quad_fast_format', + 302: 'DB_PERF_SEL_SX_DB_quad_slow_format', + 303: 'DB_PERF_SEL_quad_rd_sends_unc', + 304: 'DB_PERF_SEL_quad_rd_mi_stall_unc', + 305: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', + 306: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', + 307: 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', + 308: 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', + 309: 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', + 310: 'DB_PERF_SEL_noz_waiting_for_postz_done', + 311: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1', + 312: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1', + 313: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2', + 314: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2', + 315: 'DB_PERF_SEL_RMI_rd_tile_32byte_req', + 316: 'DB_PERF_SEL_RMI_rd_z_32byte_req', + 317: 'DB_PERF_SEL_RMI_rd_s_32byte_req', + 318: 'DB_PERF_SEL_RMI_wr_tile_32byte_req', + 319: 'DB_PERF_SEL_RMI_wr_z_32byte_req', + 320: 'DB_PERF_SEL_RMI_wr_s_32byte_req', + 321: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', + 322: 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', + 323: 'DB_PERF_SEL_RMI_rd_z_32byte_ret', + 324: 'DB_PERF_SEL_RMI_rd_s_32byte_ret', + 325: 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', + 326: 'DB_PERF_SEL_RMI_wr_z_32byte_ack', + 327: 'DB_PERF_SEL_RMI_wr_s_32byte_ack', + 328: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', + 329: 'DB_PERF_SEL_esr_vic_sqq_busy', + 330: 'DB_PERF_SEL_esr_vic_sqq_stall', + 331: 'DB_PERF_SEL_esr_psi_vic_tile_rate', + 332: 'DB_PERF_SEL_esr_vic_footprint_match_2x2', + 333: 'DB_PERF_SEL_esr_vic_footprint_match_2x1', + 334: 'DB_PERF_SEL_esr_vic_footprint_match_1x2', + 335: 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', + 336: 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', + 337: 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', + 338: 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', + 339: 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', + 340: 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', + 341: 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', + 342: 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', + 343: 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', + 344: 'DB_PERF_SEL_ts_events_pws_enable', + 345: 'DB_PERF_SEL_ps_events_pws_enable', + 346: 'DB_PERF_SEL_cs_events_pws_enable', + 347: 'DB_PERF_SEL_DB_SC_quad_noz_tiles', + 348: 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', +} +DB_PERF_SEL_SC_DB_tile_sends = 0 +DB_PERF_SEL_SC_DB_tile_busy = 1 +DB_PERF_SEL_SC_DB_tile_stalls = 2 +DB_PERF_SEL_SC_DB_tile_events = 3 +DB_PERF_SEL_SC_DB_tile_tiles = 4 +DB_PERF_SEL_SC_DB_tile_covered = 5 +DB_PERF_SEL_hiz_tc_read_starved = 6 +DB_PERF_SEL_hiz_tc_write_stall = 7 +DB_PERF_SEL_hiz_tile_culled = 8 +DB_PERF_SEL_his_tile_culled = 9 +DB_PERF_SEL_DB_SC_tile_sends = 10 +DB_PERF_SEL_DB_SC_tile_busy = 11 +DB_PERF_SEL_DB_SC_tile_stalls = 12 +DB_PERF_SEL_DB_SC_tile_df_stalls = 13 +DB_PERF_SEL_DB_SC_tile_tiles = 14 +DB_PERF_SEL_DB_SC_tile_culled = 15 +DB_PERF_SEL_DB_SC_tile_hier_kill = 16 +DB_PERF_SEL_DB_SC_tile_fast_ops = 17 +DB_PERF_SEL_DB_SC_tile_no_ops = 18 +DB_PERF_SEL_DB_SC_tile_tile_rate = 19 +DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 +DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 +DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 +DB_PERF_SEL_SC_DB_quad_sends = 23 +DB_PERF_SEL_SC_DB_quad_busy = 24 +DB_PERF_SEL_SC_DB_quad_squads = 25 +DB_PERF_SEL_SC_DB_quad_tiles = 26 +DB_PERF_SEL_SC_DB_quad_pixels = 27 +DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 +DB_PERF_SEL_DB_SC_quad_sends = 29 +DB_PERF_SEL_DB_SC_quad_busy = 30 +DB_PERF_SEL_DB_SC_quad_stalls = 31 +DB_PERF_SEL_DB_SC_quad_tiles = 32 +DB_PERF_SEL_DB_SC_quad_lit_quad = 33 +DB_PERF_SEL_DB_CB_tile_sends = 34 +DB_PERF_SEL_DB_CB_tile_busy = 35 +DB_PERF_SEL_DB_CB_tile_stalls = 36 +DB_PERF_SEL_SX_DB_quad_sends = 37 +DB_PERF_SEL_SX_DB_quad_busy = 38 +DB_PERF_SEL_SX_DB_quad_stalls = 39 +DB_PERF_SEL_SX_DB_quad_quads = 40 +DB_PERF_SEL_SX_DB_quad_pixels = 41 +DB_PERF_SEL_SX_DB_quad_exports = 42 +DB_PERF_SEL_SH_quads_outstanding_sum = 43 +DB_PERF_SEL_DB_CB_lquad_sends = 44 +DB_PERF_SEL_DB_CB_lquad_busy = 45 +DB_PERF_SEL_DB_CB_lquad_stalls = 46 +DB_PERF_SEL_DB_CB_lquad_quads = 47 +DB_PERF_SEL_tile_rd_sends = 48 +DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 +DB_PERF_SEL_quad_rd_sends = 50 +DB_PERF_SEL_quad_rd_busy = 51 +DB_PERF_SEL_quad_rd_mi_stall = 52 +DB_PERF_SEL_quad_rd_rw_collision = 53 +DB_PERF_SEL_quad_rd_tag_stall = 54 +DB_PERF_SEL_quad_rd_32byte_reqs = 55 +DB_PERF_SEL_quad_rd_panic = 56 +DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 +DB_PERF_SEL_quad_rdret_sends = 58 +DB_PERF_SEL_quad_rdret_busy = 59 +DB_PERF_SEL_tile_wr_sends = 60 +DB_PERF_SEL_tile_wr_acks = 61 +DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 +DB_PERF_SEL_quad_wr_sends = 63 +DB_PERF_SEL_quad_wr_busy = 64 +DB_PERF_SEL_quad_wr_mi_stall = 65 +DB_PERF_SEL_quad_wr_coherency_stall = 66 +DB_PERF_SEL_quad_wr_acks = 67 +DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 +DB_PERF_SEL_Tile_Cache_misses = 69 +DB_PERF_SEL_Tile_Cache_hits = 70 +DB_PERF_SEL_Tile_Cache_flushes = 71 +DB_PERF_SEL_Tile_Cache_surface_stall = 72 +DB_PERF_SEL_Tile_Cache_starves = 73 +DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 +DB_PERF_SEL_tcp_dispatcher_reads = 75 +DB_PERF_SEL_tcp_prefetcher_reads = 76 +DB_PERF_SEL_tcp_preloader_reads = 77 +DB_PERF_SEL_tcp_dispatcher_flushes = 78 +DB_PERF_SEL_tcp_prefetcher_flushes = 79 +DB_PERF_SEL_tcp_preloader_flushes = 80 +DB_PERF_SEL_Depth_Tile_Cache_sends = 81 +DB_PERF_SEL_Depth_Tile_Cache_busy = 82 +DB_PERF_SEL_Depth_Tile_Cache_starves = 83 +DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 +DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 +DB_PERF_SEL_Depth_Tile_Cache_misses = 86 +DB_PERF_SEL_Depth_Tile_Cache_hits = 87 +DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 +DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 +DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 +DB_PERF_SEL_Depth_Tile_Cache_event = 91 +DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 +DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 +DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 +DB_PERF_SEL_Stencil_Cache_misses = 95 +DB_PERF_SEL_Stencil_Cache_hits = 96 +DB_PERF_SEL_Stencil_Cache_flushes = 97 +DB_PERF_SEL_Stencil_Cache_starves = 98 +DB_PERF_SEL_Stencil_Cache_frees = 99 +DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 +DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 +DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 +DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 +DB_PERF_SEL_Z_Cache_pmask_misses = 104 +DB_PERF_SEL_Z_Cache_pmask_hits = 105 +DB_PERF_SEL_Z_Cache_pmask_flushes = 106 +DB_PERF_SEL_Z_Cache_pmask_starves = 107 +DB_PERF_SEL_Z_Cache_frees = 108 +DB_PERF_SEL_Plane_Cache_misses = 109 +DB_PERF_SEL_Plane_Cache_hits = 110 +DB_PERF_SEL_Plane_Cache_flushes = 111 +DB_PERF_SEL_Plane_Cache_starves = 112 +DB_PERF_SEL_Plane_Cache_frees = 113 +DB_PERF_SEL_flush_expanded_stencil = 114 +DB_PERF_SEL_flush_compressed_stencil = 115 +DB_PERF_SEL_flush_single_stencil = 116 +DB_PERF_SEL_planes_flushed = 117 +DB_PERF_SEL_flush_1plane = 118 +DB_PERF_SEL_flush_2plane = 119 +DB_PERF_SEL_flush_3plane = 120 +DB_PERF_SEL_flush_4plane = 121 +DB_PERF_SEL_flush_5plane = 122 +DB_PERF_SEL_flush_6plane = 123 +DB_PERF_SEL_flush_7plane = 124 +DB_PERF_SEL_flush_8plane = 125 +DB_PERF_SEL_flush_9plane = 126 +DB_PERF_SEL_flush_10plane = 127 +DB_PERF_SEL_flush_11plane = 128 +DB_PERF_SEL_flush_12plane = 129 +DB_PERF_SEL_flush_13plane = 130 +DB_PERF_SEL_flush_14plane = 131 +DB_PERF_SEL_flush_15plane = 132 +DB_PERF_SEL_flush_16plane = 133 +DB_PERF_SEL_flush_expanded_z = 134 +DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 +DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 +DB_PERF_SEL_dk_tile_sends = 137 +DB_PERF_SEL_dk_tile_busy = 138 +DB_PERF_SEL_dk_tile_quad_starves = 139 +DB_PERF_SEL_dk_tile_stalls = 140 +DB_PERF_SEL_dk_squad_sends = 141 +DB_PERF_SEL_dk_squad_busy = 142 +DB_PERF_SEL_dk_squad_stalls = 143 +DB_PERF_SEL_Op_Pipe_Busy = 144 +DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 +DB_PERF_SEL_qc_busy = 146 +DB_PERF_SEL_qc_xfc = 147 +DB_PERF_SEL_qc_conflicts = 148 +DB_PERF_SEL_qc_full_stall = 149 +DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 +DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 +DB_PERF_SEL_tsc_insert_summarize_stall = 152 +DB_PERF_SEL_tl_busy = 153 +DB_PERF_SEL_tl_dtc_read_starved = 154 +DB_PERF_SEL_tl_z_fetch_stall = 155 +DB_PERF_SEL_tl_stencil_stall = 156 +DB_PERF_SEL_tl_z_decompress_stall = 157 +DB_PERF_SEL_tl_stencil_locked_stall = 158 +DB_PERF_SEL_tl_events = 159 +DB_PERF_SEL_tl_summarize_squads = 160 +DB_PERF_SEL_tl_flush_expand_squads = 161 +DB_PERF_SEL_tl_expand_squads = 162 +DB_PERF_SEL_tl_preZ_squads = 163 +DB_PERF_SEL_tl_postZ_squads = 164 +DB_PERF_SEL_tl_preZ_noop_squads = 165 +DB_PERF_SEL_tl_postZ_noop_squads = 166 +DB_PERF_SEL_tl_tile_ops = 167 +DB_PERF_SEL_tl_in_xfc = 168 +DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 +DB_PERF_SEL_tl_in_fast_z_stall = 170 +DB_PERF_SEL_tl_out_xfc = 171 +DB_PERF_SEL_tl_out_squads = 172 +DB_PERF_SEL_zf_plane_multicycle = 173 +DB_PERF_SEL_PostZ_Samples_passing_Z = 174 +DB_PERF_SEL_PostZ_Samples_failing_Z = 175 +DB_PERF_SEL_PostZ_Samples_failing_S = 176 +DB_PERF_SEL_PreZ_Samples_passing_Z = 177 +DB_PERF_SEL_PreZ_Samples_failing_Z = 178 +DB_PERF_SEL_PreZ_Samples_failing_S = 179 +DB_PERF_SEL_ts_tc_update_stall = 180 +DB_PERF_SEL_sc_kick_start = 181 +DB_PERF_SEL_sc_kick_end = 182 +DB_PERF_SEL_clock_reg_active = 183 +DB_PERF_SEL_clock_main_active = 184 +DB_PERF_SEL_clock_mem_export_active = 185 +DB_PERF_SEL_esr_ps_out_busy = 186 +DB_PERF_SEL_esr_ps_lqf_busy = 187 +DB_PERF_SEL_esr_ps_lqf_stall = 188 +DB_PERF_SEL_etr_out_send = 189 +DB_PERF_SEL_etr_out_busy = 190 +DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 +DB_PERF_SEL_etr_out_cb_tile_stall = 192 +DB_PERF_SEL_etr_out_esr_stall = 193 +DB_PERF_SEL_esr_ps_vic_busy = 194 +DB_PERF_SEL_esr_ps_vic_stall = 195 +DB_PERF_SEL_esr_eot_fwd_busy = 196 +DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 +DB_PERF_SEL_esr_eot_fwd_forward = 198 +DB_PERF_SEL_esr_sqq_zi_busy = 199 +DB_PERF_SEL_esr_sqq_zi_stall = 200 +DB_PERF_SEL_postzl_sq_pt_busy = 201 +DB_PERF_SEL_postzl_sq_pt_stall = 202 +DB_PERF_SEL_postzl_se_busy = 203 +DB_PERF_SEL_postzl_se_stall = 204 +DB_PERF_SEL_postzl_partial_launch = 205 +DB_PERF_SEL_postzl_full_launch = 206 +DB_PERF_SEL_postzl_partial_waiting = 207 +DB_PERF_SEL_postzl_tile_mem_stall = 208 +DB_PERF_SEL_postzl_tile_init_stall = 209 +DB_PERF_SEL_prezl_tile_mem_stall = 210 +DB_PERF_SEL_prezl_tile_init_stall = 211 +DB_PERF_SEL_dtt_sm_clash_stall = 212 +DB_PERF_SEL_dtt_sm_slot_stall = 213 +DB_PERF_SEL_dtt_sm_miss_stall = 214 +DB_PERF_SEL_mi_rdreq_busy = 215 +DB_PERF_SEL_mi_rdreq_stall = 216 +DB_PERF_SEL_mi_wrreq_busy = 217 +DB_PERF_SEL_mi_wrreq_stall = 218 +DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 +DB_PERF_SEL_dkg_tile_rate_tile = 220 +DB_PERF_SEL_prezl_src_in_sends = 221 +DB_PERF_SEL_prezl_src_in_stall = 222 +DB_PERF_SEL_prezl_src_in_squads = 223 +DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 +DB_PERF_SEL_prezl_src_in_tile_rate = 225 +DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 +DB_PERF_SEL_prezl_src_out_stall = 227 +DB_PERF_SEL_postzl_src_in_sends = 228 +DB_PERF_SEL_postzl_src_in_stall = 229 +DB_PERF_SEL_postzl_src_in_squads = 230 +DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 +DB_PERF_SEL_postzl_src_in_tile_rate = 232 +DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 +DB_PERF_SEL_postzl_src_out_stall = 234 +DB_PERF_SEL_esr_ps_src_in_sends = 235 +DB_PERF_SEL_esr_ps_src_in_stall = 236 +DB_PERF_SEL_esr_ps_src_in_squads = 237 +DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 +DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 +DB_PERF_SEL_esr_ps_src_out_stall = 242 +DB_PERF_SEL_depth_bounds_tile_culled = 243 +DB_PERF_SEL_PreZ_Samples_failing_DB = 244 +DB_PERF_SEL_PostZ_Samples_failing_DB = 245 +DB_PERF_SEL_flush_compressed = 246 +DB_PERF_SEL_flush_plane_le4 = 247 +DB_PERF_SEL_tiles_z_fully_summarized = 248 +DB_PERF_SEL_tiles_stencil_fully_summarized = 249 +DB_PERF_SEL_tiles_z_clear_on_expclear = 250 +DB_PERF_SEL_tiles_s_clear_on_expclear = 251 +DB_PERF_SEL_tiles_decomp_on_expclear = 252 +DB_PERF_SEL_tiles_compressed_to_decompressed = 253 +DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 +DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 +DB_PERF_SEL_di_dt_stall = 256 +Spare_257 = 257 +DB_PERF_SEL_DB_SC_s_tile_rate = 258 +DB_PERF_SEL_DB_SC_c_tile_rate = 259 +DB_PERF_SEL_DB_SC_z_tile_rate = 260 +DB_PERF_SEL_DB_CB_lquad_export_quads = 261 +DB_PERF_SEL_DB_CB_lquad_double_format = 262 +DB_PERF_SEL_DB_CB_lquad_fast_format = 263 +DB_PERF_SEL_DB_CB_lquad_slow_format = 264 +DB_PERF_SEL_CB_DB_rdreq_sends = 265 +DB_PERF_SEL_CB_DB_rdreq_prt_sends = 266 +DB_PERF_SEL_CB_DB_wrreq_sends = 267 +DB_PERF_SEL_CB_DB_wrreq_prt_sends = 268 +DB_PERF_SEL_DB_CB_rdret_ack = 269 +DB_PERF_SEL_DB_CB_rdret_nack = 270 +DB_PERF_SEL_DB_CB_wrret_ack = 271 +DB_PERF_SEL_DB_CB_wrret_nack = 272 +DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 273 +DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 274 +DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 275 +DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 276 +DB_PERF_SEL_unmapped_z_tile_culled = 277 +DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 278 +DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 279 +DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 280 +DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 281 +DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 282 +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 283 +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 284 +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 285 +DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 286 +DB_PERF_SEL_DB_CB_context_dones = 287 +DB_PERF_SEL_DB_CB_eop_dones = 288 +DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 289 +DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 290 +DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 291 +DB_PERF_SEL_SC_DB_tile_backface = 292 +DB_PERF_SEL_SC_DB_quad_quads = 293 +DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 294 +DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 295 +DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 296 +DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 297 +DB_PERF_SEL_DB_SC_quad_double_quad = 298 +DB_PERF_SEL_SX_DB_quad_export_quads = 299 +DB_PERF_SEL_SX_DB_quad_double_format = 300 +DB_PERF_SEL_SX_DB_quad_fast_format = 301 +DB_PERF_SEL_SX_DB_quad_slow_format = 302 +DB_PERF_SEL_quad_rd_sends_unc = 303 +DB_PERF_SEL_quad_rd_mi_stall_unc = 304 +DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 305 +DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 306 +DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 307 +DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 308 +DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 309 +DB_PERF_SEL_noz_waiting_for_postz_done = 310 +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1 = 311 +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1 = 312 +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2 = 313 +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2 = 314 +DB_PERF_SEL_RMI_rd_tile_32byte_req = 315 +DB_PERF_SEL_RMI_rd_z_32byte_req = 316 +DB_PERF_SEL_RMI_rd_s_32byte_req = 317 +DB_PERF_SEL_RMI_wr_tile_32byte_req = 318 +DB_PERF_SEL_RMI_wr_z_32byte_req = 319 +DB_PERF_SEL_RMI_wr_s_32byte_req = 320 +DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 321 +DB_PERF_SEL_RMI_rd_tile_32byte_ret = 322 +DB_PERF_SEL_RMI_rd_z_32byte_ret = 323 +DB_PERF_SEL_RMI_rd_s_32byte_ret = 324 +DB_PERF_SEL_RMI_wr_tile_32byte_ack = 325 +DB_PERF_SEL_RMI_wr_z_32byte_ack = 326 +DB_PERF_SEL_RMI_wr_s_32byte_ack = 327 +DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 328 +DB_PERF_SEL_esr_vic_sqq_busy = 329 +DB_PERF_SEL_esr_vic_sqq_stall = 330 +DB_PERF_SEL_esr_psi_vic_tile_rate = 331 +DB_PERF_SEL_esr_vic_footprint_match_2x2 = 332 +DB_PERF_SEL_esr_vic_footprint_match_2x1 = 333 +DB_PERF_SEL_esr_vic_footprint_match_1x2 = 334 +DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 335 +DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 336 +DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 337 +DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 338 +DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 339 +DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 340 +DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 341 +DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 342 +DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 343 +DB_PERF_SEL_ts_events_pws_enable = 344 +DB_PERF_SEL_ps_events_pws_enable = 345 +DB_PERF_SEL_cs_events_pws_enable = 346 +DB_PERF_SEL_DB_SC_quad_noz_tiles = 347 +DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 348 +PerfCounter_Vals = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeCounterId' +PixelPipeCounterId__enumvalues = { + 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', + 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', + 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', + 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', + 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', + 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', +} +PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 +PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 +PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 +PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 +PixelPipeCounterId = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeStride' +PixelPipeStride__enumvalues = { + 0: 'PIXEL_PIPE_STRIDE_32_BITS', + 1: 'PIXEL_PIPE_STRIDE_64_BITS', + 2: 'PIXEL_PIPE_STRIDE_128_BITS', + 3: 'PIXEL_PIPE_STRIDE_256_BITS', +} +PIXEL_PIPE_STRIDE_32_BITS = 0 +PIXEL_PIPE_STRIDE_64_BITS = 1 +PIXEL_PIPE_STRIDE_128_BITS = 2 +PIXEL_PIPE_STRIDE_256_BITS = 3 +PixelPipeStride = ctypes.c_uint32 # enum + +# values for enumeration 'RingCounterControl' +RingCounterControl__enumvalues = { + 0: 'COUNTER_RING_SPLIT', + 1: 'COUNTER_RING_0', + 2: 'COUNTER_RING_1', +} +COUNTER_RING_SPLIT = 0 +COUNTER_RING_0 = 1 +COUNTER_RING_1 = 2 +RingCounterControl = ctypes.c_uint32 # enum + +# values for enumeration 'StencilOp' +StencilOp__enumvalues = { + 0: 'STENCIL_KEEP', + 1: 'STENCIL_ZERO', + 2: 'STENCIL_ONES', + 3: 'STENCIL_REPLACE_TEST', + 4: 'STENCIL_REPLACE_OP', + 5: 'STENCIL_ADD_CLAMP', + 6: 'STENCIL_SUB_CLAMP', + 7: 'STENCIL_INVERT', + 8: 'STENCIL_ADD_WRAP', + 9: 'STENCIL_SUB_WRAP', + 10: 'STENCIL_AND', + 11: 'STENCIL_OR', + 12: 'STENCIL_XOR', + 13: 'STENCIL_NAND', + 14: 'STENCIL_NOR', + 15: 'STENCIL_XNOR', +} +STENCIL_KEEP = 0 +STENCIL_ZERO = 1 +STENCIL_ONES = 2 +STENCIL_REPLACE_TEST = 3 +STENCIL_REPLACE_OP = 4 +STENCIL_ADD_CLAMP = 5 +STENCIL_SUB_CLAMP = 6 +STENCIL_INVERT = 7 +STENCIL_ADD_WRAP = 8 +STENCIL_SUB_WRAP = 9 +STENCIL_AND = 10 +STENCIL_OR = 11 +STENCIL_XOR = 12 +STENCIL_NAND = 13 +STENCIL_NOR = 14 +STENCIL_XNOR = 15 +StencilOp = ctypes.c_uint32 # enum + +# values for enumeration 'ZLimitSumm' +ZLimitSumm__enumvalues = { + 0: 'FORCE_SUMM_OFF', + 1: 'FORCE_SUMM_MINZ', + 2: 'FORCE_SUMM_MAXZ', + 3: 'FORCE_SUMM_BOTH', +} +FORCE_SUMM_OFF = 0 +FORCE_SUMM_MINZ = 1 +FORCE_SUMM_MAXZ = 2 +FORCE_SUMM_BOTH = 3 +ZLimitSumm = ctypes.c_uint32 # enum + +# values for enumeration 'ZModeForce' +ZModeForce__enumvalues = { + 0: 'NO_FORCE', + 1: 'FORCE_EARLY_Z', + 2: 'FORCE_LATE_Z', + 3: 'FORCE_RE_Z', +} +NO_FORCE = 0 +FORCE_EARLY_Z = 1 +FORCE_LATE_Z = 2 +FORCE_RE_Z = 3 +ZModeForce = ctypes.c_uint32 # enum + +# values for enumeration 'ZOrder' +ZOrder__enumvalues = { + 0: 'LATE_Z', + 1: 'EARLY_Z_THEN_LATE_Z', + 2: 'RE_Z', + 3: 'EARLY_Z_THEN_RE_Z', +} +LATE_Z = 0 +EARLY_Z_THEN_LATE_Z = 1 +RE_Z = 2 +EARLY_Z_THEN_RE_Z = 3 +ZOrder = ctypes.c_uint32 # enum + +# values for enumeration 'ZSamplePosition' +ZSamplePosition__enumvalues = { + 0: 'Z_SAMPLE_CENTER', + 1: 'Z_SAMPLE_CENTROID', +} +Z_SAMPLE_CENTER = 0 +Z_SAMPLE_CENTROID = 1 +ZSamplePosition = ctypes.c_uint32 # enum + +# values for enumeration 'ZpassControl' +ZpassControl__enumvalues = { + 0: 'ZPASS_DISABLE', + 1: 'ZPASS_SAMPLES', + 2: 'ZPASS_PIXELS', +} +ZPASS_DISABLE = 0 +ZPASS_SAMPLES = 1 +ZPASS_PIXELS = 2 +ZpassControl = ctypes.c_uint32 # enum + +# values for enumeration 'SU_PERFCNT_SEL' +SU_PERFCNT_SEL__enumvalues = { + 0: 'PERF_PAPC_PASX_REQ', + 1: 'PERF_PAPC_PASX_DISABLE_PIPE', + 2: 'PERF_PAPC_PASX_FIRST_VECTOR', + 3: 'PERF_PAPC_PASX_SECOND_VECTOR', + 4: 'PERF_PAPC_PASX_FIRST_DEAD', + 5: 'PERF_PAPC_PASX_SECOND_DEAD', + 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 8: 'PERF_PAPC_PA_INPUT_PRIM', + 9: 'PERF_PAPC_PA_INPUT_NULL_PRIM', + 10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG', + 11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', + 12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET', + 13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', + 14: 'PERF_PAPC_CLPR_CULL_PRIM', + 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', + 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', + 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', + 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', + 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', + 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', + 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', + 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 39: 'PERF_PAPC_CLSM_NULL_PRIM', + 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', + 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', + 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', + 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', + 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', + 49: 'PERF_PAPC_SU_INPUT_PRIM', + 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', + 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 61: 'PERF_PAPC_SU_OUTPUT_PRIM', + 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', + 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', + 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 77: 'PERF_PAPC_PASX_REQ_IDLE', + 78: 'PERF_PAPC_PASX_REQ_BUSY', + 79: 'PERF_PAPC_PASX_REQ_STALLED', + 80: 'PERF_PAPC_PASX_REC_IDLE', + 81: 'PERF_PAPC_PASX_REC_BUSY', + 82: 'PERF_PAPC_PASX_REC_STARVED_SX', + 83: 'PERF_PAPC_PASX_REC_STALLED', + 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 86: 'PERF_PAPC_CCGSM_IDLE', + 87: 'PERF_PAPC_CCGSM_BUSY', + 88: 'PERF_PAPC_CCGSM_STALLED', + 89: 'PERF_PAPC_CLPRIM_IDLE', + 90: 'PERF_PAPC_CLPRIM_BUSY', + 91: 'PERF_PAPC_CLPRIM_STALLED', + 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 93: 'PERF_PAPC_CLIPSM_IDLE', + 94: 'PERF_PAPC_CLIPSM_BUSY', + 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', + 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 100: 'PERF_PAPC_CLIPGA_IDLE', + 101: 'PERF_PAPC_CLIPGA_BUSY', + 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 103: 'PERF_PAPC_CLIPGA_STALLED', + 104: 'PERF_PAPC_CLIP_IDLE', + 105: 'PERF_PAPC_CLIP_BUSY', + 106: 'PERF_PAPC_SU_IDLE', + 107: 'PERF_PAPC_SU_BUSY', + 108: 'PERF_PAPC_SU_STARVED_CLIP', + 109: 'PERF_PAPC_SU_STALLED_SC', + 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', + 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', + 112: 'PERF_PAPC_PA_REG_SCLK_VLD', + 113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', + 114: 'PERF_PAPC_PASX_SE0_REQ', + 115: 'PERF_PAPC_PASX_SE1_REQ', + 116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', + 117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', + 118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', + 119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', + 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', + 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', + 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', + 129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', + 130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', + 131: 'PERF_PAPC_SU_SE0_STALLED_SC', + 132: 'PERF_PAPC_SU_SE1_STALLED_SC', + 133: 'PERF_PAPC_SU_SE01_STALLED_SC', + 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 135: 'PERF_PAPC_SU_CULLED_PRIM', + 136: 'PERF_PAPC_SU_OUTPUT_EOPG', + 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', + 144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', + 145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', + 146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', + 147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', + 148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', + 149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', + 150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', + 151: 'PERF_PAPC_SU_SE2_STALLED_SC', + 152: 'PERF_PAPC_SU_SE3_STALLED_SC', + 153: 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', + 154: 'PERF_SMALL_PRIM_CULL_PRIM_1X1', + 155: 'PERF_SMALL_PRIM_CULL_PRIM_2X1', + 156: 'PERF_SMALL_PRIM_CULL_PRIM_1X2', + 157: 'PERF_SMALL_PRIM_CULL_PRIM_2X2', + 158: 'PERF_SMALL_PRIM_CULL_PRIM_3X1', + 159: 'PERF_SMALL_PRIM_CULL_PRIM_1X3', + 160: 'PERF_SMALL_PRIM_CULL_PRIM_3X2', + 161: 'PERF_SMALL_PRIM_CULL_PRIM_2X3', + 162: 'PERF_SMALL_PRIM_CULL_PRIM_NX1', + 163: 'PERF_SMALL_PRIM_CULL_PRIM_1XN', + 164: 'PERF_SMALL_PRIM_CULL_PRIM_NX2', + 165: 'PERF_SMALL_PRIM_CULL_PRIM_2XN', + 166: 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', + 167: 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', + 168: 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', + 170: 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', + 171: 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', + 172: 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', + 173: 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', + 174: 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', + 175: 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', + 176: 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', + 177: 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', + 179: 'PERF_PA_VERTEX_FIFO_FULL', + 180: 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', + 182: 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', + 183: 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', + 185: 'PERF_PA_PIPE0_SWITCHED_GEN', + 186: 'PERF_PA_PIPE1_SWITCHED_GEN', + 188: 'PERF_ENGG_CSB_MACHINE_IS_STARVED', + 189: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', + 190: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', + 191: 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', + 192: 'PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL', + 193: 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', + 194: 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', + 195: 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', + 196: 'PERF_ENGG_CSB_NULL_SUBGROUP', + 197: 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', + 198: 'PERF_ENGG_CSB_GE_MEMORY_FULL', + 199: 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', + 200: 'PERF_ENGG_CSB_SPI_MEMORY_FULL', + 201: 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', + 202: 'PERF_ENGG_CSB_DELAY_BIN00', + 203: 'PERF_ENGG_CSB_DELAY_BIN01', + 204: 'PERF_ENGG_CSB_DELAY_BIN02', + 205: 'PERF_ENGG_CSB_DELAY_BIN03', + 206: 'PERF_ENGG_CSB_DELAY_BIN04', + 207: 'PERF_ENGG_CSB_DELAY_BIN05', + 208: 'PERF_ENGG_CSB_DELAY_BIN06', + 209: 'PERF_ENGG_CSB_DELAY_BIN07', + 210: 'PERF_ENGG_CSB_DELAY_BIN08', + 211: 'PERF_ENGG_CSB_DELAY_BIN09', + 212: 'PERF_ENGG_CSB_DELAY_BIN10', + 213: 'PERF_ENGG_CSB_DELAY_BIN11', + 214: 'PERF_ENGG_CSB_DELAY_BIN12', + 215: 'PERF_ENGG_CSB_DELAY_BIN13', + 216: 'PERF_ENGG_CSB_DELAY_BIN14', + 217: 'PERF_ENGG_CSB_DELAY_BIN15', + 218: 'PERF_ENGG_CSB_SPI_DELAY_BIN00', + 219: 'PERF_ENGG_CSB_SPI_DELAY_BIN01', + 220: 'PERF_ENGG_CSB_SPI_DELAY_BIN02', + 221: 'PERF_ENGG_CSB_SPI_DELAY_BIN03', + 222: 'PERF_ENGG_CSB_SPI_DELAY_BIN04', + 223: 'PERF_ENGG_CSB_SPI_DELAY_BIN05', + 224: 'PERF_ENGG_CSB_SPI_DELAY_BIN06', + 225: 'PERF_ENGG_CSB_SPI_DELAY_BIN07', + 226: 'PERF_ENGG_CSB_SPI_DELAY_BIN08', + 227: 'PERF_ENGG_CSB_SPI_DELAY_BIN09', + 228: 'PERF_ENGG_CSB_SPI_DELAY_BIN10', + 229: 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', + 230: 'PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM', + 231: 'PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM', + 232: 'PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM', + 233: 'PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM', + 234: 'PERF_ENGG_INDEX_REQ_STARVED', + 235: 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 236: 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 237: 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', + 238: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', + 239: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', + 240: 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', + 241: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', + 242: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', + 243: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', + 244: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', + 245: 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', + 246: 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', + 247: 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', + 248: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', + 249: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', + 250: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', + 251: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', + 252: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', + 253: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', + 254: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', + 255: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', + 256: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', + 257: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', + 258: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS', + 259: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS', + 260: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS', + 261: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS', + 262: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS', + 263: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', + 264: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', + 265: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', + 266: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', + 267: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', + 268: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', + 269: 'PERF_ENGG_POS_REQ_STARVED', + 270: 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', + 271: 'PERF_ENGG_BUSY', + 272: 'PERF_CLIPSM_CULL_PRIMS_CNT', + 273: 'PERF_PH_SEND_1_SC', + 274: 'PERF_PH_SEND_2_SC', + 275: 'PERF_PH_SEND_3_SC', + 276: 'PERF_PH_SEND_4_SC', + 277: 'PERF_OUTPUT_PRIM_1_SC', + 278: 'PERF_OUTPUT_PRIM_2_SC', + 279: 'PERF_OUTPUT_PRIM_3_SC', + 280: 'PERF_OUTPUT_PRIM_4_SC', +} +PERF_PAPC_PASX_REQ = 0 +PERF_PAPC_PASX_DISABLE_PIPE = 1 +PERF_PAPC_PASX_FIRST_VECTOR = 2 +PERF_PAPC_PASX_SECOND_VECTOR = 3 +PERF_PAPC_PASX_FIRST_DEAD = 4 +PERF_PAPC_PASX_SECOND_DEAD = 5 +PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 +PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 +PERF_PAPC_PA_INPUT_PRIM = 8 +PERF_PAPC_PA_INPUT_NULL_PRIM = 9 +PERF_PAPC_PA_INPUT_EVENT_FLAG = 10 +PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11 +PERF_PAPC_PA_INPUT_END_OF_PACKET = 12 +PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13 +PERF_PAPC_CLPR_CULL_PRIM = 14 +PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 +PERF_PAPC_CLPR_VV_CULL_PRIM = 16 +PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 +PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 +PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 +PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 +PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 +PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 +PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 +PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30 +PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 +PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 +PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 +PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 +PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 +PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 +PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37 +PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 +PERF_PAPC_CLSM_NULL_PRIM = 39 +PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 +PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 +PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 +PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 +PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 +PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 +PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 +PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47 +PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 +PERF_PAPC_SU_INPUT_PRIM = 49 +PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 +PERF_PAPC_SU_INPUT_NULL_PRIM = 51 +PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 +PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 +PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 +PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 +PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 +PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 +PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 +PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 +PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 +PERF_PAPC_SU_OUTPUT_PRIM = 61 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 +PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 +PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 +PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 +PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 +PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 +PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 +PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 +PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 +PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 +PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 +PERF_PAPC_PASX_REQ_IDLE = 77 +PERF_PAPC_PASX_REQ_BUSY = 78 +PERF_PAPC_PASX_REQ_STALLED = 79 +PERF_PAPC_PASX_REC_IDLE = 80 +PERF_PAPC_PASX_REC_BUSY = 81 +PERF_PAPC_PASX_REC_STARVED_SX = 82 +PERF_PAPC_PASX_REC_STALLED = 83 +PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 +PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 +PERF_PAPC_CCGSM_IDLE = 86 +PERF_PAPC_CCGSM_BUSY = 87 +PERF_PAPC_CCGSM_STALLED = 88 +PERF_PAPC_CLPRIM_IDLE = 89 +PERF_PAPC_CLPRIM_BUSY = 90 +PERF_PAPC_CLPRIM_STALLED = 91 +PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 +PERF_PAPC_CLIPSM_IDLE = 93 +PERF_PAPC_CLIPSM_BUSY = 94 +PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 +PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 +PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 +PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 +PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 +PERF_PAPC_CLIPGA_IDLE = 100 +PERF_PAPC_CLIPGA_BUSY = 101 +PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 +PERF_PAPC_CLIPGA_STALLED = 103 +PERF_PAPC_CLIP_IDLE = 104 +PERF_PAPC_CLIP_BUSY = 105 +PERF_PAPC_SU_IDLE = 106 +PERF_PAPC_SU_BUSY = 107 +PERF_PAPC_SU_STARVED_CLIP = 108 +PERF_PAPC_SU_STALLED_SC = 109 +PERF_PAPC_CL_DYN_SCLK_VLD = 110 +PERF_PAPC_SU_DYN_SCLK_VLD = 111 +PERF_PAPC_PA_REG_SCLK_VLD = 112 +PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113 +PERF_PAPC_PASX_SE0_REQ = 114 +PERF_PAPC_PASX_SE1_REQ = 115 +PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116 +PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117 +PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118 +PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119 +PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 +PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 +PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122 +PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 +PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 +PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125 +PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 +PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 +PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128 +PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129 +PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130 +PERF_PAPC_SU_SE0_STALLED_SC = 131 +PERF_PAPC_SU_SE1_STALLED_SC = 132 +PERF_PAPC_SU_SE01_STALLED_SC = 133 +PERF_PAPC_CLSM_CLIPPING_PRIM = 134 +PERF_PAPC_SU_CULLED_PRIM = 135 +PERF_PAPC_SU_OUTPUT_EOPG = 136 +PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 +PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 +PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 +PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 +PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 +PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 +PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143 +PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144 +PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145 +PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146 +PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147 +PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148 +PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149 +PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150 +PERF_PAPC_SU_SE2_STALLED_SC = 151 +PERF_PAPC_SU_SE3_STALLED_SC = 152 +PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 153 +PERF_SMALL_PRIM_CULL_PRIM_1X1 = 154 +PERF_SMALL_PRIM_CULL_PRIM_2X1 = 155 +PERF_SMALL_PRIM_CULL_PRIM_1X2 = 156 +PERF_SMALL_PRIM_CULL_PRIM_2X2 = 157 +PERF_SMALL_PRIM_CULL_PRIM_3X1 = 158 +PERF_SMALL_PRIM_CULL_PRIM_1X3 = 159 +PERF_SMALL_PRIM_CULL_PRIM_3X2 = 160 +PERF_SMALL_PRIM_CULL_PRIM_2X3 = 161 +PERF_SMALL_PRIM_CULL_PRIM_NX1 = 162 +PERF_SMALL_PRIM_CULL_PRIM_1XN = 163 +PERF_SMALL_PRIM_CULL_PRIM_NX2 = 164 +PERF_SMALL_PRIM_CULL_PRIM_2XN = 165 +PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 166 +PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 167 +PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 168 +PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 170 +PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 171 +PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 172 +PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 173 +PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 174 +PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 175 +PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 176 +PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 177 +PERF_PA_VERTEX_FIFO_FULL = 179 +PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 180 +PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 182 +PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 183 +PERF_PA_PIPE0_SWITCHED_GEN = 185 +PERF_PA_PIPE1_SWITCHED_GEN = 186 +PERF_ENGG_CSB_MACHINE_IS_STARVED = 188 +PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 189 +PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 190 +PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 191 +PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL = 192 +PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 193 +PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 194 +PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 195 +PERF_ENGG_CSB_NULL_SUBGROUP = 196 +PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 197 +PERF_ENGG_CSB_GE_MEMORY_FULL = 198 +PERF_ENGG_CSB_GE_MEMORY_EMPTY = 199 +PERF_ENGG_CSB_SPI_MEMORY_FULL = 200 +PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 201 +PERF_ENGG_CSB_DELAY_BIN00 = 202 +PERF_ENGG_CSB_DELAY_BIN01 = 203 +PERF_ENGG_CSB_DELAY_BIN02 = 204 +PERF_ENGG_CSB_DELAY_BIN03 = 205 +PERF_ENGG_CSB_DELAY_BIN04 = 206 +PERF_ENGG_CSB_DELAY_BIN05 = 207 +PERF_ENGG_CSB_DELAY_BIN06 = 208 +PERF_ENGG_CSB_DELAY_BIN07 = 209 +PERF_ENGG_CSB_DELAY_BIN08 = 210 +PERF_ENGG_CSB_DELAY_BIN09 = 211 +PERF_ENGG_CSB_DELAY_BIN10 = 212 +PERF_ENGG_CSB_DELAY_BIN11 = 213 +PERF_ENGG_CSB_DELAY_BIN12 = 214 +PERF_ENGG_CSB_DELAY_BIN13 = 215 +PERF_ENGG_CSB_DELAY_BIN14 = 216 +PERF_ENGG_CSB_DELAY_BIN15 = 217 +PERF_ENGG_CSB_SPI_DELAY_BIN00 = 218 +PERF_ENGG_CSB_SPI_DELAY_BIN01 = 219 +PERF_ENGG_CSB_SPI_DELAY_BIN02 = 220 +PERF_ENGG_CSB_SPI_DELAY_BIN03 = 221 +PERF_ENGG_CSB_SPI_DELAY_BIN04 = 222 +PERF_ENGG_CSB_SPI_DELAY_BIN05 = 223 +PERF_ENGG_CSB_SPI_DELAY_BIN06 = 224 +PERF_ENGG_CSB_SPI_DELAY_BIN07 = 225 +PERF_ENGG_CSB_SPI_DELAY_BIN08 = 226 +PERF_ENGG_CSB_SPI_DELAY_BIN09 = 227 +PERF_ENGG_CSB_SPI_DELAY_BIN10 = 228 +PERF_ENGG_INDEX_REQ_NULL_REQUEST = 229 +PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM = 230 +PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM = 231 +PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM = 232 +PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM = 233 +PERF_ENGG_INDEX_REQ_STARVED = 234 +PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 235 +PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 236 +PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 237 +PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 238 +PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 239 +PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 240 +PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 241 +PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 242 +PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 243 +PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 244 +PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 245 +PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 246 +PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 247 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 248 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 249 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 250 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 251 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 252 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 253 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 254 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 255 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 256 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 257 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS = 258 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS = 259 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS = 260 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS = 261 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS = 262 +PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 263 +PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 264 +PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 265 +PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 266 +PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 267 +PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 268 +PERF_ENGG_POS_REQ_STARVED = 269 +PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 270 +PERF_ENGG_BUSY = 271 +PERF_CLIPSM_CULL_PRIMS_CNT = 272 +PERF_PH_SEND_1_SC = 273 +PERF_PH_SEND_2_SC = 274 +PERF_PH_SEND_3_SC = 275 +PERF_PH_SEND_4_SC = 276 +PERF_OUTPUT_PRIM_1_SC = 277 +PERF_OUTPUT_PRIM_2_SC = 278 +PERF_OUTPUT_PRIM_3_SC = 279 +PERF_OUTPUT_PRIM_4_SC = 280 +SU_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PH_PERFCNT_SEL' +PH_PERFCNT_SEL__enumvalues = { + 0: 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', + 1: 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 2: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', + 3: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 4: 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', + 5: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', + 6: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 7: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 8: 'PH_PERF_SEL_SC0_ARB_BUSY', + 9: 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', + 10: 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', + 11: 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', + 12: 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', + 13: 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', + 14: 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', + 15: 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', + 16: 'PH_PERF_SEL_SC0_SEND', + 17: 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 18: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', + 19: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', + 20: 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', + 21: 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', + 22: 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', + 23: 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 24: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', + 25: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', + 26: 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', + 27: 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', + 28: 'PH_PERF_SEL_SC0_PA0_NULL_WE', + 29: 'PH_PERF_SEL_SC0_PA0_EVENT_WE', + 30: 'PH_PERF_SEL_SC0_PA0_FPOV_WE', + 31: 'PH_PERF_SEL_SC0_PA0_LPOV_WE', + 32: 'PH_PERF_SEL_SC0_PA0_EOP_WE', + 33: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', + 34: 'PH_PERF_SEL_SC0_PA0_EOPG_WE', + 35: 'PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD', + 36: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', + 37: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', + 38: 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', + 39: 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', + 40: 'PH_PERF_SEL_SC0_PA1_NULL_WE', + 41: 'PH_PERF_SEL_SC0_PA1_EVENT_WE', + 42: 'PH_PERF_SEL_SC0_PA1_FPOV_WE', + 43: 'PH_PERF_SEL_SC0_PA1_LPOV_WE', + 44: 'PH_PERF_SEL_SC0_PA1_EOP_WE', + 45: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', + 46: 'PH_PERF_SEL_SC0_PA1_EOPG_WE', + 47: 'PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD', + 48: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', + 49: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', + 50: 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', + 51: 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', + 52: 'PH_PERF_SEL_SC0_PA2_NULL_WE', + 53: 'PH_PERF_SEL_SC0_PA2_EVENT_WE', + 54: 'PH_PERF_SEL_SC0_PA2_FPOV_WE', + 55: 'PH_PERF_SEL_SC0_PA2_LPOV_WE', + 56: 'PH_PERF_SEL_SC0_PA2_EOP_WE', + 57: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', + 58: 'PH_PERF_SEL_SC0_PA2_EOPG_WE', + 59: 'PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD', + 60: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', + 61: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', + 62: 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', + 63: 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', + 64: 'PH_PERF_SEL_SC0_PA3_NULL_WE', + 65: 'PH_PERF_SEL_SC0_PA3_EVENT_WE', + 66: 'PH_PERF_SEL_SC0_PA3_FPOV_WE', + 67: 'PH_PERF_SEL_SC0_PA3_LPOV_WE', + 68: 'PH_PERF_SEL_SC0_PA3_EOP_WE', + 69: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', + 70: 'PH_PERF_SEL_SC0_PA3_EOPG_WE', + 71: 'PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD', + 72: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', + 73: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', + 74: 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', + 75: 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', + 76: 'PH_PERF_SEL_SC0_PA4_NULL_WE', + 77: 'PH_PERF_SEL_SC0_PA4_EVENT_WE', + 78: 'PH_PERF_SEL_SC0_PA4_FPOV_WE', + 79: 'PH_PERF_SEL_SC0_PA4_LPOV_WE', + 80: 'PH_PERF_SEL_SC0_PA4_EOP_WE', + 81: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', + 82: 'PH_PERF_SEL_SC0_PA4_EOPG_WE', + 83: 'PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD', + 84: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', + 85: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', + 86: 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', + 87: 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', + 88: 'PH_PERF_SEL_SC0_PA5_NULL_WE', + 89: 'PH_PERF_SEL_SC0_PA5_EVENT_WE', + 90: 'PH_PERF_SEL_SC0_PA5_FPOV_WE', + 91: 'PH_PERF_SEL_SC0_PA5_LPOV_WE', + 92: 'PH_PERF_SEL_SC0_PA5_EOP_WE', + 93: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', + 94: 'PH_PERF_SEL_SC0_PA5_EOPG_WE', + 95: 'PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD', + 96: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', + 97: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', + 98: 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', + 99: 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', + 100: 'PH_PERF_SEL_SC0_PA6_NULL_WE', + 101: 'PH_PERF_SEL_SC0_PA6_EVENT_WE', + 102: 'PH_PERF_SEL_SC0_PA6_FPOV_WE', + 103: 'PH_PERF_SEL_SC0_PA6_LPOV_WE', + 104: 'PH_PERF_SEL_SC0_PA6_EOP_WE', + 105: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', + 106: 'PH_PERF_SEL_SC0_PA6_EOPG_WE', + 107: 'PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD', + 108: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', + 109: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', + 110: 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', + 111: 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', + 112: 'PH_PERF_SEL_SC0_PA7_NULL_WE', + 113: 'PH_PERF_SEL_SC0_PA7_EVENT_WE', + 114: 'PH_PERF_SEL_SC0_PA7_FPOV_WE', + 115: 'PH_PERF_SEL_SC0_PA7_LPOV_WE', + 116: 'PH_PERF_SEL_SC0_PA7_EOP_WE', + 117: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', + 118: 'PH_PERF_SEL_SC0_PA7_EOPG_WE', + 119: 'PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD', + 120: 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', + 121: 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 122: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', + 123: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 124: 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', + 125: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', + 126: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 127: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 128: 'PH_PERF_SEL_SC1_ARB_BUSY', + 129: 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', + 130: 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', + 131: 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', + 132: 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', + 133: 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', + 134: 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', + 135: 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', + 136: 'PH_PERF_SEL_SC1_SEND', + 137: 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 138: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', + 139: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', + 140: 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', + 141: 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', + 142: 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 143: 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 144: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', + 145: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', + 146: 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', + 147: 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', + 148: 'PH_PERF_SEL_SC1_PA0_NULL_WE', + 149: 'PH_PERF_SEL_SC1_PA0_EVENT_WE', + 150: 'PH_PERF_SEL_SC1_PA0_FPOV_WE', + 151: 'PH_PERF_SEL_SC1_PA0_LPOV_WE', + 152: 'PH_PERF_SEL_SC1_PA0_EOP_WE', + 153: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', + 154: 'PH_PERF_SEL_SC1_PA0_EOPG_WE', + 155: 'PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD', + 156: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', + 157: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', + 158: 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', + 159: 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', + 160: 'PH_PERF_SEL_SC1_PA1_NULL_WE', + 161: 'PH_PERF_SEL_SC1_PA1_EVENT_WE', + 162: 'PH_PERF_SEL_SC1_PA1_FPOV_WE', + 163: 'PH_PERF_SEL_SC1_PA1_LPOV_WE', + 164: 'PH_PERF_SEL_SC1_PA1_EOP_WE', + 165: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', + 166: 'PH_PERF_SEL_SC1_PA1_EOPG_WE', + 167: 'PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD', + 168: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', + 169: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', + 170: 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', + 171: 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', + 172: 'PH_PERF_SEL_SC1_PA2_NULL_WE', + 173: 'PH_PERF_SEL_SC1_PA2_EVENT_WE', + 174: 'PH_PERF_SEL_SC1_PA2_FPOV_WE', + 175: 'PH_PERF_SEL_SC1_PA2_LPOV_WE', + 176: 'PH_PERF_SEL_SC1_PA2_EOP_WE', + 177: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', + 178: 'PH_PERF_SEL_SC1_PA2_EOPG_WE', + 179: 'PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD', + 180: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', + 181: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', + 182: 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', + 183: 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', + 184: 'PH_PERF_SEL_SC1_PA3_NULL_WE', + 185: 'PH_PERF_SEL_SC1_PA3_EVENT_WE', + 186: 'PH_PERF_SEL_SC1_PA3_FPOV_WE', + 187: 'PH_PERF_SEL_SC1_PA3_LPOV_WE', + 188: 'PH_PERF_SEL_SC1_PA3_EOP_WE', + 189: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', + 190: 'PH_PERF_SEL_SC1_PA3_EOPG_WE', + 191: 'PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD', + 192: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', + 193: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', + 194: 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', + 195: 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', + 196: 'PH_PERF_SEL_SC1_PA4_NULL_WE', + 197: 'PH_PERF_SEL_SC1_PA4_EVENT_WE', + 198: 'PH_PERF_SEL_SC1_PA4_FPOV_WE', + 199: 'PH_PERF_SEL_SC1_PA4_LPOV_WE', + 200: 'PH_PERF_SEL_SC1_PA4_EOP_WE', + 201: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', + 202: 'PH_PERF_SEL_SC1_PA4_EOPG_WE', + 203: 'PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD', + 204: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', + 205: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', + 206: 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', + 207: 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', + 208: 'PH_PERF_SEL_SC1_PA5_NULL_WE', + 209: 'PH_PERF_SEL_SC1_PA5_EVENT_WE', + 210: 'PH_PERF_SEL_SC1_PA5_FPOV_WE', + 211: 'PH_PERF_SEL_SC1_PA5_LPOV_WE', + 212: 'PH_PERF_SEL_SC1_PA5_EOP_WE', + 213: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', + 214: 'PH_PERF_SEL_SC1_PA5_EOPG_WE', + 215: 'PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD', + 216: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', + 217: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', + 218: 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', + 219: 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', + 220: 'PH_PERF_SEL_SC1_PA6_NULL_WE', + 221: 'PH_PERF_SEL_SC1_PA6_EVENT_WE', + 222: 'PH_PERF_SEL_SC1_PA6_FPOV_WE', + 223: 'PH_PERF_SEL_SC1_PA6_LPOV_WE', + 224: 'PH_PERF_SEL_SC1_PA6_EOP_WE', + 225: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', + 226: 'PH_PERF_SEL_SC1_PA6_EOPG_WE', + 227: 'PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD', + 228: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', + 229: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', + 230: 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', + 231: 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', + 232: 'PH_PERF_SEL_SC1_PA7_NULL_WE', + 233: 'PH_PERF_SEL_SC1_PA7_EVENT_WE', + 234: 'PH_PERF_SEL_SC1_PA7_FPOV_WE', + 235: 'PH_PERF_SEL_SC1_PA7_LPOV_WE', + 236: 'PH_PERF_SEL_SC1_PA7_EOP_WE', + 237: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', + 238: 'PH_PERF_SEL_SC1_PA7_EOPG_WE', + 239: 'PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD', + 240: 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', + 241: 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 242: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', + 243: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 244: 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', + 245: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', + 246: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 247: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 248: 'PH_PERF_SEL_SC2_ARB_BUSY', + 249: 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', + 250: 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', + 251: 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', + 252: 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', + 253: 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', + 254: 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', + 255: 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', + 256: 'PH_PERF_SEL_SC2_SEND', + 257: 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 258: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', + 259: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', + 260: 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', + 261: 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', + 262: 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 263: 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 264: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', + 265: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', + 266: 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', + 267: 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', + 268: 'PH_PERF_SEL_SC2_PA0_NULL_WE', + 269: 'PH_PERF_SEL_SC2_PA0_EVENT_WE', + 270: 'PH_PERF_SEL_SC2_PA0_FPOV_WE', + 271: 'PH_PERF_SEL_SC2_PA0_LPOV_WE', + 272: 'PH_PERF_SEL_SC2_PA0_EOP_WE', + 273: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', + 274: 'PH_PERF_SEL_SC2_PA0_EOPG_WE', + 275: 'PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD', + 276: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', + 277: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', + 278: 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', + 279: 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', + 280: 'PH_PERF_SEL_SC2_PA1_NULL_WE', + 281: 'PH_PERF_SEL_SC2_PA1_EVENT_WE', + 282: 'PH_PERF_SEL_SC2_PA1_FPOV_WE', + 283: 'PH_PERF_SEL_SC2_PA1_LPOV_WE', + 284: 'PH_PERF_SEL_SC2_PA1_EOP_WE', + 285: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', + 286: 'PH_PERF_SEL_SC2_PA1_EOPG_WE', + 287: 'PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD', + 288: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', + 289: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', + 290: 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', + 291: 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', + 292: 'PH_PERF_SEL_SC2_PA2_NULL_WE', + 293: 'PH_PERF_SEL_SC2_PA2_EVENT_WE', + 294: 'PH_PERF_SEL_SC2_PA2_FPOV_WE', + 295: 'PH_PERF_SEL_SC2_PA2_LPOV_WE', + 296: 'PH_PERF_SEL_SC2_PA2_EOP_WE', + 297: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', + 298: 'PH_PERF_SEL_SC2_PA2_EOPG_WE', + 299: 'PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD', + 300: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', + 301: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', + 302: 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', + 303: 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', + 304: 'PH_PERF_SEL_SC2_PA3_NULL_WE', + 305: 'PH_PERF_SEL_SC2_PA3_EVENT_WE', + 306: 'PH_PERF_SEL_SC2_PA3_FPOV_WE', + 307: 'PH_PERF_SEL_SC2_PA3_LPOV_WE', + 308: 'PH_PERF_SEL_SC2_PA3_EOP_WE', + 309: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', + 310: 'PH_PERF_SEL_SC2_PA3_EOPG_WE', + 311: 'PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD', + 312: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', + 313: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', + 314: 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', + 315: 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', + 316: 'PH_PERF_SEL_SC2_PA4_NULL_WE', + 317: 'PH_PERF_SEL_SC2_PA4_EVENT_WE', + 318: 'PH_PERF_SEL_SC2_PA4_FPOV_WE', + 319: 'PH_PERF_SEL_SC2_PA4_LPOV_WE', + 320: 'PH_PERF_SEL_SC2_PA4_EOP_WE', + 321: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', + 322: 'PH_PERF_SEL_SC2_PA4_EOPG_WE', + 323: 'PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD', + 324: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', + 325: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', + 326: 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', + 327: 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', + 328: 'PH_PERF_SEL_SC2_PA5_NULL_WE', + 329: 'PH_PERF_SEL_SC2_PA5_EVENT_WE', + 330: 'PH_PERF_SEL_SC2_PA5_FPOV_WE', + 331: 'PH_PERF_SEL_SC2_PA5_LPOV_WE', + 332: 'PH_PERF_SEL_SC2_PA5_EOP_WE', + 333: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', + 334: 'PH_PERF_SEL_SC2_PA5_EOPG_WE', + 335: 'PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD', + 336: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', + 337: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', + 338: 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', + 339: 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', + 340: 'PH_PERF_SEL_SC2_PA6_NULL_WE', + 341: 'PH_PERF_SEL_SC2_PA6_EVENT_WE', + 342: 'PH_PERF_SEL_SC2_PA6_FPOV_WE', + 343: 'PH_PERF_SEL_SC2_PA6_LPOV_WE', + 344: 'PH_PERF_SEL_SC2_PA6_EOP_WE', + 345: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', + 346: 'PH_PERF_SEL_SC2_PA6_EOPG_WE', + 347: 'PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD', + 348: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', + 349: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', + 350: 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', + 351: 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', + 352: 'PH_PERF_SEL_SC2_PA7_NULL_WE', + 353: 'PH_PERF_SEL_SC2_PA7_EVENT_WE', + 354: 'PH_PERF_SEL_SC2_PA7_FPOV_WE', + 355: 'PH_PERF_SEL_SC2_PA7_LPOV_WE', + 356: 'PH_PERF_SEL_SC2_PA7_EOP_WE', + 357: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', + 358: 'PH_PERF_SEL_SC2_PA7_EOPG_WE', + 359: 'PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD', + 360: 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', + 361: 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 362: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', + 363: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 364: 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', + 365: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', + 366: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 367: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 368: 'PH_PERF_SEL_SC3_ARB_BUSY', + 369: 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', + 370: 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', + 371: 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', + 372: 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', + 373: 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', + 374: 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', + 375: 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', + 376: 'PH_PERF_SEL_SC3_SEND', + 377: 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 378: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', + 379: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', + 380: 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', + 381: 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', + 382: 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 383: 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 384: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', + 385: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', + 386: 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', + 387: 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', + 388: 'PH_PERF_SEL_SC3_PA0_NULL_WE', + 389: 'PH_PERF_SEL_SC3_PA0_EVENT_WE', + 390: 'PH_PERF_SEL_SC3_PA0_FPOV_WE', + 391: 'PH_PERF_SEL_SC3_PA0_LPOV_WE', + 392: 'PH_PERF_SEL_SC3_PA0_EOP_WE', + 393: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', + 394: 'PH_PERF_SEL_SC3_PA0_EOPG_WE', + 395: 'PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD', + 396: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', + 397: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', + 398: 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', + 399: 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', + 400: 'PH_PERF_SEL_SC3_PA1_NULL_WE', + 401: 'PH_PERF_SEL_SC3_PA1_EVENT_WE', + 402: 'PH_PERF_SEL_SC3_PA1_FPOV_WE', + 403: 'PH_PERF_SEL_SC3_PA1_LPOV_WE', + 404: 'PH_PERF_SEL_SC3_PA1_EOP_WE', + 405: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', + 406: 'PH_PERF_SEL_SC3_PA1_EOPG_WE', + 407: 'PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD', + 408: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', + 409: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', + 410: 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', + 411: 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', + 412: 'PH_PERF_SEL_SC3_PA2_NULL_WE', + 413: 'PH_PERF_SEL_SC3_PA2_EVENT_WE', + 414: 'PH_PERF_SEL_SC3_PA2_FPOV_WE', + 415: 'PH_PERF_SEL_SC3_PA2_LPOV_WE', + 416: 'PH_PERF_SEL_SC3_PA2_EOP_WE', + 417: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', + 418: 'PH_PERF_SEL_SC3_PA2_EOPG_WE', + 419: 'PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD', + 420: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', + 421: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', + 422: 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', + 423: 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', + 424: 'PH_PERF_SEL_SC3_PA3_NULL_WE', + 425: 'PH_PERF_SEL_SC3_PA3_EVENT_WE', + 426: 'PH_PERF_SEL_SC3_PA3_FPOV_WE', + 427: 'PH_PERF_SEL_SC3_PA3_LPOV_WE', + 428: 'PH_PERF_SEL_SC3_PA3_EOP_WE', + 429: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', + 430: 'PH_PERF_SEL_SC3_PA3_EOPG_WE', + 431: 'PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD', + 432: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', + 433: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', + 434: 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', + 435: 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', + 436: 'PH_PERF_SEL_SC3_PA4_NULL_WE', + 437: 'PH_PERF_SEL_SC3_PA4_EVENT_WE', + 438: 'PH_PERF_SEL_SC3_PA4_FPOV_WE', + 439: 'PH_PERF_SEL_SC3_PA4_LPOV_WE', + 440: 'PH_PERF_SEL_SC3_PA4_EOP_WE', + 441: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', + 442: 'PH_PERF_SEL_SC3_PA4_EOPG_WE', + 443: 'PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD', + 444: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', + 445: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', + 446: 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', + 447: 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', + 448: 'PH_PERF_SEL_SC3_PA5_NULL_WE', + 449: 'PH_PERF_SEL_SC3_PA5_EVENT_WE', + 450: 'PH_PERF_SEL_SC3_PA5_FPOV_WE', + 451: 'PH_PERF_SEL_SC3_PA5_LPOV_WE', + 452: 'PH_PERF_SEL_SC3_PA5_EOP_WE', + 453: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', + 454: 'PH_PERF_SEL_SC3_PA5_EOPG_WE', + 455: 'PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD', + 456: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', + 457: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', + 458: 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', + 459: 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', + 460: 'PH_PERF_SEL_SC3_PA6_NULL_WE', + 461: 'PH_PERF_SEL_SC3_PA6_EVENT_WE', + 462: 'PH_PERF_SEL_SC3_PA6_FPOV_WE', + 463: 'PH_PERF_SEL_SC3_PA6_LPOV_WE', + 464: 'PH_PERF_SEL_SC3_PA6_EOP_WE', + 465: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', + 466: 'PH_PERF_SEL_SC3_PA6_EOPG_WE', + 467: 'PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD', + 468: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', + 469: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', + 470: 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', + 471: 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', + 472: 'PH_PERF_SEL_SC3_PA7_NULL_WE', + 473: 'PH_PERF_SEL_SC3_PA7_EVENT_WE', + 474: 'PH_PERF_SEL_SC3_PA7_FPOV_WE', + 475: 'PH_PERF_SEL_SC3_PA7_LPOV_WE', + 476: 'PH_PERF_SEL_SC3_PA7_EOP_WE', + 477: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', + 478: 'PH_PERF_SEL_SC3_PA7_EOPG_WE', + 479: 'PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD', + 480: 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', + 481: 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 482: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', + 483: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 484: 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', + 485: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', + 486: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 487: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 488: 'PH_PERF_SEL_SC4_ARB_BUSY', + 489: 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', + 490: 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', + 491: 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', + 492: 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', + 493: 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', + 494: 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', + 495: 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', + 496: 'PH_PERF_SEL_SC4_SEND', + 497: 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 498: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', + 499: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', + 500: 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', + 501: 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', + 502: 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 503: 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 504: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', + 505: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', + 506: 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', + 507: 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', + 508: 'PH_PERF_SEL_SC4_PA0_NULL_WE', + 509: 'PH_PERF_SEL_SC4_PA0_EVENT_WE', + 510: 'PH_PERF_SEL_SC4_PA0_FPOV_WE', + 511: 'PH_PERF_SEL_SC4_PA0_LPOV_WE', + 512: 'PH_PERF_SEL_SC4_PA0_EOP_WE', + 513: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', + 514: 'PH_PERF_SEL_SC4_PA0_EOPG_WE', + 515: 'PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD', + 516: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', + 517: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', + 518: 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', + 519: 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', + 520: 'PH_PERF_SEL_SC4_PA1_NULL_WE', + 521: 'PH_PERF_SEL_SC4_PA1_EVENT_WE', + 522: 'PH_PERF_SEL_SC4_PA1_FPOV_WE', + 523: 'PH_PERF_SEL_SC4_PA1_LPOV_WE', + 524: 'PH_PERF_SEL_SC4_PA1_EOP_WE', + 525: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', + 526: 'PH_PERF_SEL_SC4_PA1_EOPG_WE', + 527: 'PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD', + 528: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', + 529: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', + 530: 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', + 531: 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', + 532: 'PH_PERF_SEL_SC4_PA2_NULL_WE', + 533: 'PH_PERF_SEL_SC4_PA2_EVENT_WE', + 534: 'PH_PERF_SEL_SC4_PA2_FPOV_WE', + 535: 'PH_PERF_SEL_SC4_PA2_LPOV_WE', + 536: 'PH_PERF_SEL_SC4_PA2_EOP_WE', + 537: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', + 538: 'PH_PERF_SEL_SC4_PA2_EOPG_WE', + 539: 'PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD', + 540: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', + 541: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', + 542: 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', + 543: 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', + 544: 'PH_PERF_SEL_SC4_PA3_NULL_WE', + 545: 'PH_PERF_SEL_SC4_PA3_EVENT_WE', + 546: 'PH_PERF_SEL_SC4_PA3_FPOV_WE', + 547: 'PH_PERF_SEL_SC4_PA3_LPOV_WE', + 548: 'PH_PERF_SEL_SC4_PA3_EOP_WE', + 549: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', + 550: 'PH_PERF_SEL_SC4_PA3_EOPG_WE', + 551: 'PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD', + 552: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', + 553: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', + 554: 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', + 555: 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', + 556: 'PH_PERF_SEL_SC4_PA4_NULL_WE', + 557: 'PH_PERF_SEL_SC4_PA4_EVENT_WE', + 558: 'PH_PERF_SEL_SC4_PA4_FPOV_WE', + 559: 'PH_PERF_SEL_SC4_PA4_LPOV_WE', + 560: 'PH_PERF_SEL_SC4_PA4_EOP_WE', + 561: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', + 562: 'PH_PERF_SEL_SC4_PA4_EOPG_WE', + 563: 'PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD', + 564: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', + 565: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', + 566: 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', + 567: 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', + 568: 'PH_PERF_SEL_SC4_PA5_NULL_WE', + 569: 'PH_PERF_SEL_SC4_PA5_EVENT_WE', + 570: 'PH_PERF_SEL_SC4_PA5_FPOV_WE', + 571: 'PH_PERF_SEL_SC4_PA5_LPOV_WE', + 572: 'PH_PERF_SEL_SC4_PA5_EOP_WE', + 573: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', + 574: 'PH_PERF_SEL_SC4_PA5_EOPG_WE', + 575: 'PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD', + 576: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', + 577: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', + 578: 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', + 579: 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', + 580: 'PH_PERF_SEL_SC4_PA6_NULL_WE', + 581: 'PH_PERF_SEL_SC4_PA6_EVENT_WE', + 582: 'PH_PERF_SEL_SC4_PA6_FPOV_WE', + 583: 'PH_PERF_SEL_SC4_PA6_LPOV_WE', + 584: 'PH_PERF_SEL_SC4_PA6_EOP_WE', + 585: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', + 586: 'PH_PERF_SEL_SC4_PA6_EOPG_WE', + 587: 'PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD', + 588: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', + 589: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', + 590: 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', + 591: 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', + 592: 'PH_PERF_SEL_SC4_PA7_NULL_WE', + 593: 'PH_PERF_SEL_SC4_PA7_EVENT_WE', + 594: 'PH_PERF_SEL_SC4_PA7_FPOV_WE', + 595: 'PH_PERF_SEL_SC4_PA7_LPOV_WE', + 596: 'PH_PERF_SEL_SC4_PA7_EOP_WE', + 597: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', + 598: 'PH_PERF_SEL_SC4_PA7_EOPG_WE', + 599: 'PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD', + 600: 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', + 601: 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 602: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', + 603: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 604: 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', + 605: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', + 606: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 607: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 608: 'PH_PERF_SEL_SC5_ARB_BUSY', + 609: 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', + 610: 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', + 611: 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', + 612: 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', + 613: 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', + 614: 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', + 615: 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', + 616: 'PH_PERF_SEL_SC5_SEND', + 617: 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 618: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', + 619: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', + 620: 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', + 621: 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', + 622: 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 623: 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 624: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', + 625: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', + 626: 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', + 627: 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', + 628: 'PH_PERF_SEL_SC5_PA0_NULL_WE', + 629: 'PH_PERF_SEL_SC5_PA0_EVENT_WE', + 630: 'PH_PERF_SEL_SC5_PA0_FPOV_WE', + 631: 'PH_PERF_SEL_SC5_PA0_LPOV_WE', + 632: 'PH_PERF_SEL_SC5_PA0_EOP_WE', + 633: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', + 634: 'PH_PERF_SEL_SC5_PA0_EOPG_WE', + 635: 'PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD', + 636: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', + 637: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', + 638: 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', + 639: 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', + 640: 'PH_PERF_SEL_SC5_PA1_NULL_WE', + 641: 'PH_PERF_SEL_SC5_PA1_EVENT_WE', + 642: 'PH_PERF_SEL_SC5_PA1_FPOV_WE', + 643: 'PH_PERF_SEL_SC5_PA1_LPOV_WE', + 644: 'PH_PERF_SEL_SC5_PA1_EOP_WE', + 645: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', + 646: 'PH_PERF_SEL_SC5_PA1_EOPG_WE', + 647: 'PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD', + 648: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', + 649: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', + 650: 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', + 651: 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', + 652: 'PH_PERF_SEL_SC5_PA2_NULL_WE', + 653: 'PH_PERF_SEL_SC5_PA2_EVENT_WE', + 654: 'PH_PERF_SEL_SC5_PA2_FPOV_WE', + 655: 'PH_PERF_SEL_SC5_PA2_LPOV_WE', + 656: 'PH_PERF_SEL_SC5_PA2_EOP_WE', + 657: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', + 658: 'PH_PERF_SEL_SC5_PA2_EOPG_WE', + 659: 'PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD', + 660: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', + 661: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', + 662: 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', + 663: 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', + 664: 'PH_PERF_SEL_SC5_PA3_NULL_WE', + 665: 'PH_PERF_SEL_SC5_PA3_EVENT_WE', + 666: 'PH_PERF_SEL_SC5_PA3_FPOV_WE', + 667: 'PH_PERF_SEL_SC5_PA3_LPOV_WE', + 668: 'PH_PERF_SEL_SC5_PA3_EOP_WE', + 669: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', + 670: 'PH_PERF_SEL_SC5_PA3_EOPG_WE', + 671: 'PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD', + 672: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', + 673: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', + 674: 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', + 675: 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', + 676: 'PH_PERF_SEL_SC5_PA4_NULL_WE', + 677: 'PH_PERF_SEL_SC5_PA4_EVENT_WE', + 678: 'PH_PERF_SEL_SC5_PA4_FPOV_WE', + 679: 'PH_PERF_SEL_SC5_PA4_LPOV_WE', + 680: 'PH_PERF_SEL_SC5_PA4_EOP_WE', + 681: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', + 682: 'PH_PERF_SEL_SC5_PA4_EOPG_WE', + 683: 'PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD', + 684: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', + 685: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', + 686: 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', + 687: 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', + 688: 'PH_PERF_SEL_SC5_PA5_NULL_WE', + 689: 'PH_PERF_SEL_SC5_PA5_EVENT_WE', + 690: 'PH_PERF_SEL_SC5_PA5_FPOV_WE', + 691: 'PH_PERF_SEL_SC5_PA5_LPOV_WE', + 692: 'PH_PERF_SEL_SC5_PA5_EOP_WE', + 693: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', + 694: 'PH_PERF_SEL_SC5_PA5_EOPG_WE', + 695: 'PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD', + 696: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', + 697: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', + 698: 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', + 699: 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', + 700: 'PH_PERF_SEL_SC5_PA6_NULL_WE', + 701: 'PH_PERF_SEL_SC5_PA6_EVENT_WE', + 702: 'PH_PERF_SEL_SC5_PA6_FPOV_WE', + 703: 'PH_PERF_SEL_SC5_PA6_LPOV_WE', + 704: 'PH_PERF_SEL_SC5_PA6_EOP_WE', + 705: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', + 706: 'PH_PERF_SEL_SC5_PA6_EOPG_WE', + 707: 'PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD', + 708: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', + 709: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', + 710: 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', + 711: 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', + 712: 'PH_PERF_SEL_SC5_PA7_NULL_WE', + 713: 'PH_PERF_SEL_SC5_PA7_EVENT_WE', + 714: 'PH_PERF_SEL_SC5_PA7_FPOV_WE', + 715: 'PH_PERF_SEL_SC5_PA7_LPOV_WE', + 716: 'PH_PERF_SEL_SC5_PA7_EOP_WE', + 717: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', + 718: 'PH_PERF_SEL_SC5_PA7_EOPG_WE', + 719: 'PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD', + 720: 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', + 721: 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 722: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', + 723: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 724: 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', + 725: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', + 726: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 727: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 728: 'PH_PERF_SEL_SC6_ARB_BUSY', + 729: 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', + 730: 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', + 731: 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', + 732: 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', + 733: 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', + 734: 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', + 735: 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', + 736: 'PH_PERF_SEL_SC6_SEND', + 737: 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 738: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', + 739: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', + 740: 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', + 741: 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', + 742: 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 743: 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 744: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', + 745: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', + 746: 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', + 747: 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', + 748: 'PH_PERF_SEL_SC6_PA0_NULL_WE', + 749: 'PH_PERF_SEL_SC6_PA0_EVENT_WE', + 750: 'PH_PERF_SEL_SC6_PA0_FPOV_WE', + 751: 'PH_PERF_SEL_SC6_PA0_LPOV_WE', + 752: 'PH_PERF_SEL_SC6_PA0_EOP_WE', + 753: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', + 754: 'PH_PERF_SEL_SC6_PA0_EOPG_WE', + 755: 'PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD', + 756: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', + 757: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', + 758: 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', + 759: 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', + 760: 'PH_PERF_SEL_SC6_PA1_NULL_WE', + 761: 'PH_PERF_SEL_SC6_PA1_EVENT_WE', + 762: 'PH_PERF_SEL_SC6_PA1_FPOV_WE', + 763: 'PH_PERF_SEL_SC6_PA1_LPOV_WE', + 764: 'PH_PERF_SEL_SC6_PA1_EOP_WE', + 765: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', + 766: 'PH_PERF_SEL_SC6_PA1_EOPG_WE', + 767: 'PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD', + 768: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', + 769: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', + 770: 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', + 771: 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', + 772: 'PH_PERF_SEL_SC6_PA2_NULL_WE', + 773: 'PH_PERF_SEL_SC6_PA2_EVENT_WE', + 774: 'PH_PERF_SEL_SC6_PA2_FPOV_WE', + 775: 'PH_PERF_SEL_SC6_PA2_LPOV_WE', + 776: 'PH_PERF_SEL_SC6_PA2_EOP_WE', + 777: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', + 778: 'PH_PERF_SEL_SC6_PA2_EOPG_WE', + 779: 'PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD', + 780: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', + 781: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', + 782: 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', + 783: 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', + 784: 'PH_PERF_SEL_SC6_PA3_NULL_WE', + 785: 'PH_PERF_SEL_SC6_PA3_EVENT_WE', + 786: 'PH_PERF_SEL_SC6_PA3_FPOV_WE', + 787: 'PH_PERF_SEL_SC6_PA3_LPOV_WE', + 788: 'PH_PERF_SEL_SC6_PA3_EOP_WE', + 789: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', + 790: 'PH_PERF_SEL_SC6_PA3_EOPG_WE', + 791: 'PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD', + 792: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', + 793: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', + 794: 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', + 795: 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', + 796: 'PH_PERF_SEL_SC6_PA4_NULL_WE', + 797: 'PH_PERF_SEL_SC6_PA4_EVENT_WE', + 798: 'PH_PERF_SEL_SC6_PA4_FPOV_WE', + 799: 'PH_PERF_SEL_SC6_PA4_LPOV_WE', + 800: 'PH_PERF_SEL_SC6_PA4_EOP_WE', + 801: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', + 802: 'PH_PERF_SEL_SC6_PA4_EOPG_WE', + 803: 'PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD', + 804: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', + 805: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', + 806: 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', + 807: 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', + 808: 'PH_PERF_SEL_SC6_PA5_NULL_WE', + 809: 'PH_PERF_SEL_SC6_PA5_EVENT_WE', + 810: 'PH_PERF_SEL_SC6_PA5_FPOV_WE', + 811: 'PH_PERF_SEL_SC6_PA5_LPOV_WE', + 812: 'PH_PERF_SEL_SC6_PA5_EOP_WE', + 813: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', + 814: 'PH_PERF_SEL_SC6_PA5_EOPG_WE', + 815: 'PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD', + 816: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', + 817: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', + 818: 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', + 819: 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', + 820: 'PH_PERF_SEL_SC6_PA6_NULL_WE', + 821: 'PH_PERF_SEL_SC6_PA6_EVENT_WE', + 822: 'PH_PERF_SEL_SC6_PA6_FPOV_WE', + 823: 'PH_PERF_SEL_SC6_PA6_LPOV_WE', + 824: 'PH_PERF_SEL_SC6_PA6_EOP_WE', + 825: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', + 826: 'PH_PERF_SEL_SC6_PA6_EOPG_WE', + 827: 'PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD', + 828: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', + 829: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', + 830: 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', + 831: 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', + 832: 'PH_PERF_SEL_SC6_PA7_NULL_WE', + 833: 'PH_PERF_SEL_SC6_PA7_EVENT_WE', + 834: 'PH_PERF_SEL_SC6_PA7_FPOV_WE', + 835: 'PH_PERF_SEL_SC6_PA7_LPOV_WE', + 836: 'PH_PERF_SEL_SC6_PA7_EOP_WE', + 837: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', + 838: 'PH_PERF_SEL_SC6_PA7_EOPG_WE', + 839: 'PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD', + 840: 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', + 841: 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 842: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', + 843: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 844: 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', + 845: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', + 846: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 847: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 848: 'PH_PERF_SEL_SC7_ARB_BUSY', + 849: 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', + 850: 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', + 851: 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', + 852: 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', + 853: 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', + 854: 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', + 855: 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', + 856: 'PH_PERF_SEL_SC7_SEND', + 857: 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 858: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', + 859: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', + 860: 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', + 861: 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', + 862: 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 863: 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 864: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', + 865: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', + 866: 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', + 867: 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', + 868: 'PH_PERF_SEL_SC7_PA0_NULL_WE', + 869: 'PH_PERF_SEL_SC7_PA0_EVENT_WE', + 870: 'PH_PERF_SEL_SC7_PA0_FPOV_WE', + 871: 'PH_PERF_SEL_SC7_PA0_LPOV_WE', + 872: 'PH_PERF_SEL_SC7_PA0_EOP_WE', + 873: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', + 874: 'PH_PERF_SEL_SC7_PA0_EOPG_WE', + 875: 'PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD', + 876: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', + 877: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', + 878: 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', + 879: 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', + 880: 'PH_PERF_SEL_SC7_PA1_NULL_WE', + 881: 'PH_PERF_SEL_SC7_PA1_EVENT_WE', + 882: 'PH_PERF_SEL_SC7_PA1_FPOV_WE', + 883: 'PH_PERF_SEL_SC7_PA1_LPOV_WE', + 884: 'PH_PERF_SEL_SC7_PA1_EOP_WE', + 885: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', + 886: 'PH_PERF_SEL_SC7_PA1_EOPG_WE', + 887: 'PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD', + 888: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', + 889: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', + 890: 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', + 891: 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', + 892: 'PH_PERF_SEL_SC7_PA2_NULL_WE', + 893: 'PH_PERF_SEL_SC7_PA2_EVENT_WE', + 894: 'PH_PERF_SEL_SC7_PA2_FPOV_WE', + 895: 'PH_PERF_SEL_SC7_PA2_LPOV_WE', + 896: 'PH_PERF_SEL_SC7_PA2_EOP_WE', + 897: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', + 898: 'PH_PERF_SEL_SC7_PA2_EOPG_WE', + 899: 'PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD', + 900: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', + 901: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', + 902: 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', + 903: 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', + 904: 'PH_PERF_SEL_SC7_PA3_NULL_WE', + 905: 'PH_PERF_SEL_SC7_PA3_EVENT_WE', + 906: 'PH_PERF_SEL_SC7_PA3_FPOV_WE', + 907: 'PH_PERF_SEL_SC7_PA3_LPOV_WE', + 908: 'PH_PERF_SEL_SC7_PA3_EOP_WE', + 909: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', + 910: 'PH_PERF_SEL_SC7_PA3_EOPG_WE', + 911: 'PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD', + 912: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', + 913: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', + 914: 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', + 915: 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', + 916: 'PH_PERF_SEL_SC7_PA4_NULL_WE', + 917: 'PH_PERF_SEL_SC7_PA4_EVENT_WE', + 918: 'PH_PERF_SEL_SC7_PA4_FPOV_WE', + 919: 'PH_PERF_SEL_SC7_PA4_LPOV_WE', + 920: 'PH_PERF_SEL_SC7_PA4_EOP_WE', + 921: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', + 922: 'PH_PERF_SEL_SC7_PA4_EOPG_WE', + 923: 'PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD', + 924: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', + 925: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', + 926: 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', + 927: 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', + 928: 'PH_PERF_SEL_SC7_PA5_NULL_WE', + 929: 'PH_PERF_SEL_SC7_PA5_EVENT_WE', + 930: 'PH_PERF_SEL_SC7_PA5_FPOV_WE', + 931: 'PH_PERF_SEL_SC7_PA5_LPOV_WE', + 932: 'PH_PERF_SEL_SC7_PA5_EOP_WE', + 933: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', + 934: 'PH_PERF_SEL_SC7_PA5_EOPG_WE', + 935: 'PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD', + 936: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', + 937: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', + 938: 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', + 939: 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', + 940: 'PH_PERF_SEL_SC7_PA6_NULL_WE', + 941: 'PH_PERF_SEL_SC7_PA6_EVENT_WE', + 942: 'PH_PERF_SEL_SC7_PA6_FPOV_WE', + 943: 'PH_PERF_SEL_SC7_PA6_LPOV_WE', + 944: 'PH_PERF_SEL_SC7_PA6_EOP_WE', + 945: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', + 946: 'PH_PERF_SEL_SC7_PA6_EOPG_WE', + 947: 'PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD', + 948: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', + 949: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', + 950: 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', + 951: 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', + 952: 'PH_PERF_SEL_SC7_PA7_NULL_WE', + 953: 'PH_PERF_SEL_SC7_PA7_EVENT_WE', + 954: 'PH_PERF_SEL_SC7_PA7_FPOV_WE', + 955: 'PH_PERF_SEL_SC7_PA7_LPOV_WE', + 956: 'PH_PERF_SEL_SC7_PA7_EOP_WE', + 957: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', + 958: 'PH_PERF_SEL_SC7_PA7_EOPG_WE', + 959: 'PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD', + 960: 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', + 961: 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', + 962: 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', + 963: 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', + 964: 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', + 965: 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', + 966: 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', + 967: 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', + 968: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', + 969: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', + 970: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', + 971: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', + 972: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', + 973: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', + 974: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', + 975: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', + 976: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 977: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 978: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 979: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 980: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 981: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 982: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 983: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 984: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 985: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 986: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 987: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 988: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 989: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 990: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 991: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 992: 'PH_PERF_SC0_FIFO_STATUS_0', + 993: 'PH_PERF_SC0_FIFO_STATUS_1', + 994: 'PH_PERF_SC0_FIFO_STATUS_2', + 995: 'PH_PERF_SC0_FIFO_STATUS_3', + 996: 'PH_PERF_SC1_FIFO_STATUS_0', + 997: 'PH_PERF_SC1_FIFO_STATUS_1', + 998: 'PH_PERF_SC1_FIFO_STATUS_2', + 999: 'PH_PERF_SC1_FIFO_STATUS_3', + 1000: 'PH_PERF_SC2_FIFO_STATUS_0', + 1001: 'PH_PERF_SC2_FIFO_STATUS_1', + 1002: 'PH_PERF_SC2_FIFO_STATUS_2', + 1003: 'PH_PERF_SC2_FIFO_STATUS_3', + 1004: 'PH_PERF_SC3_FIFO_STATUS_0', + 1005: 'PH_PERF_SC3_FIFO_STATUS_1', + 1006: 'PH_PERF_SC3_FIFO_STATUS_2', + 1007: 'PH_PERF_SC3_FIFO_STATUS_3', + 1008: 'PH_PERF_SC4_FIFO_STATUS_0', + 1009: 'PH_PERF_SC4_FIFO_STATUS_1', + 1010: 'PH_PERF_SC4_FIFO_STATUS_2', + 1011: 'PH_PERF_SC4_FIFO_STATUS_3', + 1012: 'PH_PERF_SC5_FIFO_STATUS_0', + 1013: 'PH_PERF_SC5_FIFO_STATUS_1', + 1014: 'PH_PERF_SC5_FIFO_STATUS_2', + 1015: 'PH_PERF_SC5_FIFO_STATUS_3', + 1016: 'PH_PERF_SC6_FIFO_STATUS_0', + 1017: 'PH_PERF_SC6_FIFO_STATUS_1', + 1018: 'PH_PERF_SC6_FIFO_STATUS_2', + 1019: 'PH_PERF_SC6_FIFO_STATUS_3', + 1020: 'PH_PERF_SC7_FIFO_STATUS_0', + 1021: 'PH_PERF_SC7_FIFO_STATUS_1', + 1022: 'PH_PERF_SC7_FIFO_STATUS_2', + 1023: 'PH_PERF_SC7_FIFO_STATUS_3', +} +PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0 +PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 1 +PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 2 +PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 3 +PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 4 +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 5 +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 6 +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 7 +PH_PERF_SEL_SC0_ARB_BUSY = 8 +PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 9 +PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 10 +PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 11 +PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 12 +PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 13 +PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 14 +PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 15 +PH_PERF_SEL_SC0_SEND = 16 +PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 17 +PH_PERF_SEL_SC0_CREDIT_AT_MAX = 18 +PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 19 +PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 20 +PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 21 +PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 22 +PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 23 +PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 24 +PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 25 +PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 26 +PH_PERF_SEL_SC0_PA0_FIFO_FULL = 27 +PH_PERF_SEL_SC0_PA0_NULL_WE = 28 +PH_PERF_SEL_SC0_PA0_EVENT_WE = 29 +PH_PERF_SEL_SC0_PA0_FPOV_WE = 30 +PH_PERF_SEL_SC0_PA0_LPOV_WE = 31 +PH_PERF_SEL_SC0_PA0_EOP_WE = 32 +PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 33 +PH_PERF_SEL_SC0_PA0_EOPG_WE = 34 +PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD = 35 +PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 36 +PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 37 +PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 38 +PH_PERF_SEL_SC0_PA1_FIFO_FULL = 39 +PH_PERF_SEL_SC0_PA1_NULL_WE = 40 +PH_PERF_SEL_SC0_PA1_EVENT_WE = 41 +PH_PERF_SEL_SC0_PA1_FPOV_WE = 42 +PH_PERF_SEL_SC0_PA1_LPOV_WE = 43 +PH_PERF_SEL_SC0_PA1_EOP_WE = 44 +PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 45 +PH_PERF_SEL_SC0_PA1_EOPG_WE = 46 +PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD = 47 +PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 48 +PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 49 +PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 50 +PH_PERF_SEL_SC0_PA2_FIFO_FULL = 51 +PH_PERF_SEL_SC0_PA2_NULL_WE = 52 +PH_PERF_SEL_SC0_PA2_EVENT_WE = 53 +PH_PERF_SEL_SC0_PA2_FPOV_WE = 54 +PH_PERF_SEL_SC0_PA2_LPOV_WE = 55 +PH_PERF_SEL_SC0_PA2_EOP_WE = 56 +PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 57 +PH_PERF_SEL_SC0_PA2_EOPG_WE = 58 +PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD = 59 +PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 60 +PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 61 +PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 62 +PH_PERF_SEL_SC0_PA3_FIFO_FULL = 63 +PH_PERF_SEL_SC0_PA3_NULL_WE = 64 +PH_PERF_SEL_SC0_PA3_EVENT_WE = 65 +PH_PERF_SEL_SC0_PA3_FPOV_WE = 66 +PH_PERF_SEL_SC0_PA3_LPOV_WE = 67 +PH_PERF_SEL_SC0_PA3_EOP_WE = 68 +PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 69 +PH_PERF_SEL_SC0_PA3_EOPG_WE = 70 +PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD = 71 +PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 72 +PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 73 +PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 74 +PH_PERF_SEL_SC0_PA4_FIFO_FULL = 75 +PH_PERF_SEL_SC0_PA4_NULL_WE = 76 +PH_PERF_SEL_SC0_PA4_EVENT_WE = 77 +PH_PERF_SEL_SC0_PA4_FPOV_WE = 78 +PH_PERF_SEL_SC0_PA4_LPOV_WE = 79 +PH_PERF_SEL_SC0_PA4_EOP_WE = 80 +PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 81 +PH_PERF_SEL_SC0_PA4_EOPG_WE = 82 +PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD = 83 +PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 84 +PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 85 +PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 86 +PH_PERF_SEL_SC0_PA5_FIFO_FULL = 87 +PH_PERF_SEL_SC0_PA5_NULL_WE = 88 +PH_PERF_SEL_SC0_PA5_EVENT_WE = 89 +PH_PERF_SEL_SC0_PA5_FPOV_WE = 90 +PH_PERF_SEL_SC0_PA5_LPOV_WE = 91 +PH_PERF_SEL_SC0_PA5_EOP_WE = 92 +PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 93 +PH_PERF_SEL_SC0_PA5_EOPG_WE = 94 +PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD = 95 +PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 96 +PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 97 +PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 98 +PH_PERF_SEL_SC0_PA6_FIFO_FULL = 99 +PH_PERF_SEL_SC0_PA6_NULL_WE = 100 +PH_PERF_SEL_SC0_PA6_EVENT_WE = 101 +PH_PERF_SEL_SC0_PA6_FPOV_WE = 102 +PH_PERF_SEL_SC0_PA6_LPOV_WE = 103 +PH_PERF_SEL_SC0_PA6_EOP_WE = 104 +PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 105 +PH_PERF_SEL_SC0_PA6_EOPG_WE = 106 +PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD = 107 +PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 108 +PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 109 +PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 110 +PH_PERF_SEL_SC0_PA7_FIFO_FULL = 111 +PH_PERF_SEL_SC0_PA7_NULL_WE = 112 +PH_PERF_SEL_SC0_PA7_EVENT_WE = 113 +PH_PERF_SEL_SC0_PA7_FPOV_WE = 114 +PH_PERF_SEL_SC0_PA7_LPOV_WE = 115 +PH_PERF_SEL_SC0_PA7_EOP_WE = 116 +PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 117 +PH_PERF_SEL_SC0_PA7_EOPG_WE = 118 +PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD = 119 +PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 120 +PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 121 +PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 122 +PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 123 +PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 124 +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 125 +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 126 +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 127 +PH_PERF_SEL_SC1_ARB_BUSY = 128 +PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 129 +PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 130 +PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 131 +PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 132 +PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 133 +PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 134 +PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 135 +PH_PERF_SEL_SC1_SEND = 136 +PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 137 +PH_PERF_SEL_SC1_CREDIT_AT_MAX = 138 +PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 139 +PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 140 +PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 141 +PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 142 +PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 143 +PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 144 +PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 145 +PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 146 +PH_PERF_SEL_SC1_PA0_FIFO_FULL = 147 +PH_PERF_SEL_SC1_PA0_NULL_WE = 148 +PH_PERF_SEL_SC1_PA0_EVENT_WE = 149 +PH_PERF_SEL_SC1_PA0_FPOV_WE = 150 +PH_PERF_SEL_SC1_PA0_LPOV_WE = 151 +PH_PERF_SEL_SC1_PA0_EOP_WE = 152 +PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 153 +PH_PERF_SEL_SC1_PA0_EOPG_WE = 154 +PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD = 155 +PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 156 +PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 157 +PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 158 +PH_PERF_SEL_SC1_PA1_FIFO_FULL = 159 +PH_PERF_SEL_SC1_PA1_NULL_WE = 160 +PH_PERF_SEL_SC1_PA1_EVENT_WE = 161 +PH_PERF_SEL_SC1_PA1_FPOV_WE = 162 +PH_PERF_SEL_SC1_PA1_LPOV_WE = 163 +PH_PERF_SEL_SC1_PA1_EOP_WE = 164 +PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 165 +PH_PERF_SEL_SC1_PA1_EOPG_WE = 166 +PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD = 167 +PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 168 +PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 169 +PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 170 +PH_PERF_SEL_SC1_PA2_FIFO_FULL = 171 +PH_PERF_SEL_SC1_PA2_NULL_WE = 172 +PH_PERF_SEL_SC1_PA2_EVENT_WE = 173 +PH_PERF_SEL_SC1_PA2_FPOV_WE = 174 +PH_PERF_SEL_SC1_PA2_LPOV_WE = 175 +PH_PERF_SEL_SC1_PA2_EOP_WE = 176 +PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 177 +PH_PERF_SEL_SC1_PA2_EOPG_WE = 178 +PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD = 179 +PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 180 +PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 181 +PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 182 +PH_PERF_SEL_SC1_PA3_FIFO_FULL = 183 +PH_PERF_SEL_SC1_PA3_NULL_WE = 184 +PH_PERF_SEL_SC1_PA3_EVENT_WE = 185 +PH_PERF_SEL_SC1_PA3_FPOV_WE = 186 +PH_PERF_SEL_SC1_PA3_LPOV_WE = 187 +PH_PERF_SEL_SC1_PA3_EOP_WE = 188 +PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 189 +PH_PERF_SEL_SC1_PA3_EOPG_WE = 190 +PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD = 191 +PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 192 +PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 193 +PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 194 +PH_PERF_SEL_SC1_PA4_FIFO_FULL = 195 +PH_PERF_SEL_SC1_PA4_NULL_WE = 196 +PH_PERF_SEL_SC1_PA4_EVENT_WE = 197 +PH_PERF_SEL_SC1_PA4_FPOV_WE = 198 +PH_PERF_SEL_SC1_PA4_LPOV_WE = 199 +PH_PERF_SEL_SC1_PA4_EOP_WE = 200 +PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 201 +PH_PERF_SEL_SC1_PA4_EOPG_WE = 202 +PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD = 203 +PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 204 +PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 205 +PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 206 +PH_PERF_SEL_SC1_PA5_FIFO_FULL = 207 +PH_PERF_SEL_SC1_PA5_NULL_WE = 208 +PH_PERF_SEL_SC1_PA5_EVENT_WE = 209 +PH_PERF_SEL_SC1_PA5_FPOV_WE = 210 +PH_PERF_SEL_SC1_PA5_LPOV_WE = 211 +PH_PERF_SEL_SC1_PA5_EOP_WE = 212 +PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 213 +PH_PERF_SEL_SC1_PA5_EOPG_WE = 214 +PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD = 215 +PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 216 +PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 217 +PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 218 +PH_PERF_SEL_SC1_PA6_FIFO_FULL = 219 +PH_PERF_SEL_SC1_PA6_NULL_WE = 220 +PH_PERF_SEL_SC1_PA6_EVENT_WE = 221 +PH_PERF_SEL_SC1_PA6_FPOV_WE = 222 +PH_PERF_SEL_SC1_PA6_LPOV_WE = 223 +PH_PERF_SEL_SC1_PA6_EOP_WE = 224 +PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 225 +PH_PERF_SEL_SC1_PA6_EOPG_WE = 226 +PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD = 227 +PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 228 +PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 229 +PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 230 +PH_PERF_SEL_SC1_PA7_FIFO_FULL = 231 +PH_PERF_SEL_SC1_PA7_NULL_WE = 232 +PH_PERF_SEL_SC1_PA7_EVENT_WE = 233 +PH_PERF_SEL_SC1_PA7_FPOV_WE = 234 +PH_PERF_SEL_SC1_PA7_LPOV_WE = 235 +PH_PERF_SEL_SC1_PA7_EOP_WE = 236 +PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 237 +PH_PERF_SEL_SC1_PA7_EOPG_WE = 238 +PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD = 239 +PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 240 +PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 241 +PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 242 +PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 243 +PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 244 +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 245 +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 246 +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 247 +PH_PERF_SEL_SC2_ARB_BUSY = 248 +PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 249 +PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 250 +PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 251 +PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 252 +PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 253 +PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 254 +PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 255 +PH_PERF_SEL_SC2_SEND = 256 +PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 257 +PH_PERF_SEL_SC2_CREDIT_AT_MAX = 258 +PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 259 +PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 260 +PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 261 +PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 262 +PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 263 +PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 264 +PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 265 +PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 266 +PH_PERF_SEL_SC2_PA0_FIFO_FULL = 267 +PH_PERF_SEL_SC2_PA0_NULL_WE = 268 +PH_PERF_SEL_SC2_PA0_EVENT_WE = 269 +PH_PERF_SEL_SC2_PA0_FPOV_WE = 270 +PH_PERF_SEL_SC2_PA0_LPOV_WE = 271 +PH_PERF_SEL_SC2_PA0_EOP_WE = 272 +PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 273 +PH_PERF_SEL_SC2_PA0_EOPG_WE = 274 +PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD = 275 +PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 276 +PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 277 +PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 278 +PH_PERF_SEL_SC2_PA1_FIFO_FULL = 279 +PH_PERF_SEL_SC2_PA1_NULL_WE = 280 +PH_PERF_SEL_SC2_PA1_EVENT_WE = 281 +PH_PERF_SEL_SC2_PA1_FPOV_WE = 282 +PH_PERF_SEL_SC2_PA1_LPOV_WE = 283 +PH_PERF_SEL_SC2_PA1_EOP_WE = 284 +PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 285 +PH_PERF_SEL_SC2_PA1_EOPG_WE = 286 +PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD = 287 +PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 288 +PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 289 +PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 290 +PH_PERF_SEL_SC2_PA2_FIFO_FULL = 291 +PH_PERF_SEL_SC2_PA2_NULL_WE = 292 +PH_PERF_SEL_SC2_PA2_EVENT_WE = 293 +PH_PERF_SEL_SC2_PA2_FPOV_WE = 294 +PH_PERF_SEL_SC2_PA2_LPOV_WE = 295 +PH_PERF_SEL_SC2_PA2_EOP_WE = 296 +PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 297 +PH_PERF_SEL_SC2_PA2_EOPG_WE = 298 +PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD = 299 +PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 300 +PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 301 +PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 302 +PH_PERF_SEL_SC2_PA3_FIFO_FULL = 303 +PH_PERF_SEL_SC2_PA3_NULL_WE = 304 +PH_PERF_SEL_SC2_PA3_EVENT_WE = 305 +PH_PERF_SEL_SC2_PA3_FPOV_WE = 306 +PH_PERF_SEL_SC2_PA3_LPOV_WE = 307 +PH_PERF_SEL_SC2_PA3_EOP_WE = 308 +PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 309 +PH_PERF_SEL_SC2_PA3_EOPG_WE = 310 +PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD = 311 +PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 312 +PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 313 +PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 314 +PH_PERF_SEL_SC2_PA4_FIFO_FULL = 315 +PH_PERF_SEL_SC2_PA4_NULL_WE = 316 +PH_PERF_SEL_SC2_PA4_EVENT_WE = 317 +PH_PERF_SEL_SC2_PA4_FPOV_WE = 318 +PH_PERF_SEL_SC2_PA4_LPOV_WE = 319 +PH_PERF_SEL_SC2_PA4_EOP_WE = 320 +PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 321 +PH_PERF_SEL_SC2_PA4_EOPG_WE = 322 +PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD = 323 +PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 324 +PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 325 +PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 326 +PH_PERF_SEL_SC2_PA5_FIFO_FULL = 327 +PH_PERF_SEL_SC2_PA5_NULL_WE = 328 +PH_PERF_SEL_SC2_PA5_EVENT_WE = 329 +PH_PERF_SEL_SC2_PA5_FPOV_WE = 330 +PH_PERF_SEL_SC2_PA5_LPOV_WE = 331 +PH_PERF_SEL_SC2_PA5_EOP_WE = 332 +PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 333 +PH_PERF_SEL_SC2_PA5_EOPG_WE = 334 +PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD = 335 +PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 336 +PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 337 +PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 338 +PH_PERF_SEL_SC2_PA6_FIFO_FULL = 339 +PH_PERF_SEL_SC2_PA6_NULL_WE = 340 +PH_PERF_SEL_SC2_PA6_EVENT_WE = 341 +PH_PERF_SEL_SC2_PA6_FPOV_WE = 342 +PH_PERF_SEL_SC2_PA6_LPOV_WE = 343 +PH_PERF_SEL_SC2_PA6_EOP_WE = 344 +PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 345 +PH_PERF_SEL_SC2_PA6_EOPG_WE = 346 +PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD = 347 +PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 348 +PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 349 +PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 350 +PH_PERF_SEL_SC2_PA7_FIFO_FULL = 351 +PH_PERF_SEL_SC2_PA7_NULL_WE = 352 +PH_PERF_SEL_SC2_PA7_EVENT_WE = 353 +PH_PERF_SEL_SC2_PA7_FPOV_WE = 354 +PH_PERF_SEL_SC2_PA7_LPOV_WE = 355 +PH_PERF_SEL_SC2_PA7_EOP_WE = 356 +PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 357 +PH_PERF_SEL_SC2_PA7_EOPG_WE = 358 +PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD = 359 +PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 360 +PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 361 +PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 362 +PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 363 +PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 364 +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 365 +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 366 +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 367 +PH_PERF_SEL_SC3_ARB_BUSY = 368 +PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 369 +PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 370 +PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 371 +PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 372 +PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 373 +PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 374 +PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 375 +PH_PERF_SEL_SC3_SEND = 376 +PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 377 +PH_PERF_SEL_SC3_CREDIT_AT_MAX = 378 +PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 379 +PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 380 +PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 381 +PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 382 +PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 383 +PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 384 +PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 385 +PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 386 +PH_PERF_SEL_SC3_PA0_FIFO_FULL = 387 +PH_PERF_SEL_SC3_PA0_NULL_WE = 388 +PH_PERF_SEL_SC3_PA0_EVENT_WE = 389 +PH_PERF_SEL_SC3_PA0_FPOV_WE = 390 +PH_PERF_SEL_SC3_PA0_LPOV_WE = 391 +PH_PERF_SEL_SC3_PA0_EOP_WE = 392 +PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 393 +PH_PERF_SEL_SC3_PA0_EOPG_WE = 394 +PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD = 395 +PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 396 +PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 397 +PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 398 +PH_PERF_SEL_SC3_PA1_FIFO_FULL = 399 +PH_PERF_SEL_SC3_PA1_NULL_WE = 400 +PH_PERF_SEL_SC3_PA1_EVENT_WE = 401 +PH_PERF_SEL_SC3_PA1_FPOV_WE = 402 +PH_PERF_SEL_SC3_PA1_LPOV_WE = 403 +PH_PERF_SEL_SC3_PA1_EOP_WE = 404 +PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 405 +PH_PERF_SEL_SC3_PA1_EOPG_WE = 406 +PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD = 407 +PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 408 +PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 409 +PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 410 +PH_PERF_SEL_SC3_PA2_FIFO_FULL = 411 +PH_PERF_SEL_SC3_PA2_NULL_WE = 412 +PH_PERF_SEL_SC3_PA2_EVENT_WE = 413 +PH_PERF_SEL_SC3_PA2_FPOV_WE = 414 +PH_PERF_SEL_SC3_PA2_LPOV_WE = 415 +PH_PERF_SEL_SC3_PA2_EOP_WE = 416 +PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 417 +PH_PERF_SEL_SC3_PA2_EOPG_WE = 418 +PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD = 419 +PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 420 +PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 421 +PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 422 +PH_PERF_SEL_SC3_PA3_FIFO_FULL = 423 +PH_PERF_SEL_SC3_PA3_NULL_WE = 424 +PH_PERF_SEL_SC3_PA3_EVENT_WE = 425 +PH_PERF_SEL_SC3_PA3_FPOV_WE = 426 +PH_PERF_SEL_SC3_PA3_LPOV_WE = 427 +PH_PERF_SEL_SC3_PA3_EOP_WE = 428 +PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 429 +PH_PERF_SEL_SC3_PA3_EOPG_WE = 430 +PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD = 431 +PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 432 +PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 433 +PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 434 +PH_PERF_SEL_SC3_PA4_FIFO_FULL = 435 +PH_PERF_SEL_SC3_PA4_NULL_WE = 436 +PH_PERF_SEL_SC3_PA4_EVENT_WE = 437 +PH_PERF_SEL_SC3_PA4_FPOV_WE = 438 +PH_PERF_SEL_SC3_PA4_LPOV_WE = 439 +PH_PERF_SEL_SC3_PA4_EOP_WE = 440 +PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 441 +PH_PERF_SEL_SC3_PA4_EOPG_WE = 442 +PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD = 443 +PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 444 +PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 445 +PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 446 +PH_PERF_SEL_SC3_PA5_FIFO_FULL = 447 +PH_PERF_SEL_SC3_PA5_NULL_WE = 448 +PH_PERF_SEL_SC3_PA5_EVENT_WE = 449 +PH_PERF_SEL_SC3_PA5_FPOV_WE = 450 +PH_PERF_SEL_SC3_PA5_LPOV_WE = 451 +PH_PERF_SEL_SC3_PA5_EOP_WE = 452 +PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 453 +PH_PERF_SEL_SC3_PA5_EOPG_WE = 454 +PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD = 455 +PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 456 +PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 457 +PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 458 +PH_PERF_SEL_SC3_PA6_FIFO_FULL = 459 +PH_PERF_SEL_SC3_PA6_NULL_WE = 460 +PH_PERF_SEL_SC3_PA6_EVENT_WE = 461 +PH_PERF_SEL_SC3_PA6_FPOV_WE = 462 +PH_PERF_SEL_SC3_PA6_LPOV_WE = 463 +PH_PERF_SEL_SC3_PA6_EOP_WE = 464 +PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 465 +PH_PERF_SEL_SC3_PA6_EOPG_WE = 466 +PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD = 467 +PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 468 +PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 469 +PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 470 +PH_PERF_SEL_SC3_PA7_FIFO_FULL = 471 +PH_PERF_SEL_SC3_PA7_NULL_WE = 472 +PH_PERF_SEL_SC3_PA7_EVENT_WE = 473 +PH_PERF_SEL_SC3_PA7_FPOV_WE = 474 +PH_PERF_SEL_SC3_PA7_LPOV_WE = 475 +PH_PERF_SEL_SC3_PA7_EOP_WE = 476 +PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 477 +PH_PERF_SEL_SC3_PA7_EOPG_WE = 478 +PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD = 479 +PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 480 +PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 481 +PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 482 +PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 483 +PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 484 +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 485 +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 486 +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 487 +PH_PERF_SEL_SC4_ARB_BUSY = 488 +PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 489 +PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 490 +PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 491 +PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 492 +PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 493 +PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 494 +PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 495 +PH_PERF_SEL_SC4_SEND = 496 +PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 497 +PH_PERF_SEL_SC4_CREDIT_AT_MAX = 498 +PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 499 +PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 500 +PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 501 +PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 502 +PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 503 +PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 504 +PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 505 +PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 506 +PH_PERF_SEL_SC4_PA0_FIFO_FULL = 507 +PH_PERF_SEL_SC4_PA0_NULL_WE = 508 +PH_PERF_SEL_SC4_PA0_EVENT_WE = 509 +PH_PERF_SEL_SC4_PA0_FPOV_WE = 510 +PH_PERF_SEL_SC4_PA0_LPOV_WE = 511 +PH_PERF_SEL_SC4_PA0_EOP_WE = 512 +PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 513 +PH_PERF_SEL_SC4_PA0_EOPG_WE = 514 +PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD = 515 +PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 516 +PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 517 +PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 518 +PH_PERF_SEL_SC4_PA1_FIFO_FULL = 519 +PH_PERF_SEL_SC4_PA1_NULL_WE = 520 +PH_PERF_SEL_SC4_PA1_EVENT_WE = 521 +PH_PERF_SEL_SC4_PA1_FPOV_WE = 522 +PH_PERF_SEL_SC4_PA1_LPOV_WE = 523 +PH_PERF_SEL_SC4_PA1_EOP_WE = 524 +PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 525 +PH_PERF_SEL_SC4_PA1_EOPG_WE = 526 +PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD = 527 +PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 528 +PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 529 +PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 530 +PH_PERF_SEL_SC4_PA2_FIFO_FULL = 531 +PH_PERF_SEL_SC4_PA2_NULL_WE = 532 +PH_PERF_SEL_SC4_PA2_EVENT_WE = 533 +PH_PERF_SEL_SC4_PA2_FPOV_WE = 534 +PH_PERF_SEL_SC4_PA2_LPOV_WE = 535 +PH_PERF_SEL_SC4_PA2_EOP_WE = 536 +PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 537 +PH_PERF_SEL_SC4_PA2_EOPG_WE = 538 +PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD = 539 +PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 540 +PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 541 +PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 542 +PH_PERF_SEL_SC4_PA3_FIFO_FULL = 543 +PH_PERF_SEL_SC4_PA3_NULL_WE = 544 +PH_PERF_SEL_SC4_PA3_EVENT_WE = 545 +PH_PERF_SEL_SC4_PA3_FPOV_WE = 546 +PH_PERF_SEL_SC4_PA3_LPOV_WE = 547 +PH_PERF_SEL_SC4_PA3_EOP_WE = 548 +PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 549 +PH_PERF_SEL_SC4_PA3_EOPG_WE = 550 +PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD = 551 +PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 552 +PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 553 +PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 554 +PH_PERF_SEL_SC4_PA4_FIFO_FULL = 555 +PH_PERF_SEL_SC4_PA4_NULL_WE = 556 +PH_PERF_SEL_SC4_PA4_EVENT_WE = 557 +PH_PERF_SEL_SC4_PA4_FPOV_WE = 558 +PH_PERF_SEL_SC4_PA4_LPOV_WE = 559 +PH_PERF_SEL_SC4_PA4_EOP_WE = 560 +PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 561 +PH_PERF_SEL_SC4_PA4_EOPG_WE = 562 +PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD = 563 +PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 564 +PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 565 +PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 566 +PH_PERF_SEL_SC4_PA5_FIFO_FULL = 567 +PH_PERF_SEL_SC4_PA5_NULL_WE = 568 +PH_PERF_SEL_SC4_PA5_EVENT_WE = 569 +PH_PERF_SEL_SC4_PA5_FPOV_WE = 570 +PH_PERF_SEL_SC4_PA5_LPOV_WE = 571 +PH_PERF_SEL_SC4_PA5_EOP_WE = 572 +PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 573 +PH_PERF_SEL_SC4_PA5_EOPG_WE = 574 +PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD = 575 +PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 576 +PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 577 +PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 578 +PH_PERF_SEL_SC4_PA6_FIFO_FULL = 579 +PH_PERF_SEL_SC4_PA6_NULL_WE = 580 +PH_PERF_SEL_SC4_PA6_EVENT_WE = 581 +PH_PERF_SEL_SC4_PA6_FPOV_WE = 582 +PH_PERF_SEL_SC4_PA6_LPOV_WE = 583 +PH_PERF_SEL_SC4_PA6_EOP_WE = 584 +PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 585 +PH_PERF_SEL_SC4_PA6_EOPG_WE = 586 +PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD = 587 +PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 588 +PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 589 +PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 590 +PH_PERF_SEL_SC4_PA7_FIFO_FULL = 591 +PH_PERF_SEL_SC4_PA7_NULL_WE = 592 +PH_PERF_SEL_SC4_PA7_EVENT_WE = 593 +PH_PERF_SEL_SC4_PA7_FPOV_WE = 594 +PH_PERF_SEL_SC4_PA7_LPOV_WE = 595 +PH_PERF_SEL_SC4_PA7_EOP_WE = 596 +PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 597 +PH_PERF_SEL_SC4_PA7_EOPG_WE = 598 +PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD = 599 +PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 600 +PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 601 +PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 602 +PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 603 +PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 604 +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 605 +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 606 +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 607 +PH_PERF_SEL_SC5_ARB_BUSY = 608 +PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 609 +PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 610 +PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 611 +PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 612 +PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 613 +PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 614 +PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 615 +PH_PERF_SEL_SC5_SEND = 616 +PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 617 +PH_PERF_SEL_SC5_CREDIT_AT_MAX = 618 +PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 619 +PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 620 +PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 621 +PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 622 +PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 623 +PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 624 +PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 625 +PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 626 +PH_PERF_SEL_SC5_PA0_FIFO_FULL = 627 +PH_PERF_SEL_SC5_PA0_NULL_WE = 628 +PH_PERF_SEL_SC5_PA0_EVENT_WE = 629 +PH_PERF_SEL_SC5_PA0_FPOV_WE = 630 +PH_PERF_SEL_SC5_PA0_LPOV_WE = 631 +PH_PERF_SEL_SC5_PA0_EOP_WE = 632 +PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 633 +PH_PERF_SEL_SC5_PA0_EOPG_WE = 634 +PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD = 635 +PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 636 +PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 637 +PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 638 +PH_PERF_SEL_SC5_PA1_FIFO_FULL = 639 +PH_PERF_SEL_SC5_PA1_NULL_WE = 640 +PH_PERF_SEL_SC5_PA1_EVENT_WE = 641 +PH_PERF_SEL_SC5_PA1_FPOV_WE = 642 +PH_PERF_SEL_SC5_PA1_LPOV_WE = 643 +PH_PERF_SEL_SC5_PA1_EOP_WE = 644 +PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 645 +PH_PERF_SEL_SC5_PA1_EOPG_WE = 646 +PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD = 647 +PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 648 +PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 649 +PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 650 +PH_PERF_SEL_SC5_PA2_FIFO_FULL = 651 +PH_PERF_SEL_SC5_PA2_NULL_WE = 652 +PH_PERF_SEL_SC5_PA2_EVENT_WE = 653 +PH_PERF_SEL_SC5_PA2_FPOV_WE = 654 +PH_PERF_SEL_SC5_PA2_LPOV_WE = 655 +PH_PERF_SEL_SC5_PA2_EOP_WE = 656 +PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 657 +PH_PERF_SEL_SC5_PA2_EOPG_WE = 658 +PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD = 659 +PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 660 +PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 661 +PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 662 +PH_PERF_SEL_SC5_PA3_FIFO_FULL = 663 +PH_PERF_SEL_SC5_PA3_NULL_WE = 664 +PH_PERF_SEL_SC5_PA3_EVENT_WE = 665 +PH_PERF_SEL_SC5_PA3_FPOV_WE = 666 +PH_PERF_SEL_SC5_PA3_LPOV_WE = 667 +PH_PERF_SEL_SC5_PA3_EOP_WE = 668 +PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 669 +PH_PERF_SEL_SC5_PA3_EOPG_WE = 670 +PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD = 671 +PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 672 +PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 673 +PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 674 +PH_PERF_SEL_SC5_PA4_FIFO_FULL = 675 +PH_PERF_SEL_SC5_PA4_NULL_WE = 676 +PH_PERF_SEL_SC5_PA4_EVENT_WE = 677 +PH_PERF_SEL_SC5_PA4_FPOV_WE = 678 +PH_PERF_SEL_SC5_PA4_LPOV_WE = 679 +PH_PERF_SEL_SC5_PA4_EOP_WE = 680 +PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 681 +PH_PERF_SEL_SC5_PA4_EOPG_WE = 682 +PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD = 683 +PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 684 +PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 685 +PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 686 +PH_PERF_SEL_SC5_PA5_FIFO_FULL = 687 +PH_PERF_SEL_SC5_PA5_NULL_WE = 688 +PH_PERF_SEL_SC5_PA5_EVENT_WE = 689 +PH_PERF_SEL_SC5_PA5_FPOV_WE = 690 +PH_PERF_SEL_SC5_PA5_LPOV_WE = 691 +PH_PERF_SEL_SC5_PA5_EOP_WE = 692 +PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 693 +PH_PERF_SEL_SC5_PA5_EOPG_WE = 694 +PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD = 695 +PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 696 +PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 697 +PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 698 +PH_PERF_SEL_SC5_PA6_FIFO_FULL = 699 +PH_PERF_SEL_SC5_PA6_NULL_WE = 700 +PH_PERF_SEL_SC5_PA6_EVENT_WE = 701 +PH_PERF_SEL_SC5_PA6_FPOV_WE = 702 +PH_PERF_SEL_SC5_PA6_LPOV_WE = 703 +PH_PERF_SEL_SC5_PA6_EOP_WE = 704 +PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 705 +PH_PERF_SEL_SC5_PA6_EOPG_WE = 706 +PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD = 707 +PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 708 +PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 709 +PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 710 +PH_PERF_SEL_SC5_PA7_FIFO_FULL = 711 +PH_PERF_SEL_SC5_PA7_NULL_WE = 712 +PH_PERF_SEL_SC5_PA7_EVENT_WE = 713 +PH_PERF_SEL_SC5_PA7_FPOV_WE = 714 +PH_PERF_SEL_SC5_PA7_LPOV_WE = 715 +PH_PERF_SEL_SC5_PA7_EOP_WE = 716 +PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 717 +PH_PERF_SEL_SC5_PA7_EOPG_WE = 718 +PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD = 719 +PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 720 +PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 721 +PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 722 +PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 723 +PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 724 +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 725 +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 726 +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 727 +PH_PERF_SEL_SC6_ARB_BUSY = 728 +PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 729 +PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 730 +PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 731 +PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 732 +PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 733 +PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 734 +PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 735 +PH_PERF_SEL_SC6_SEND = 736 +PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 737 +PH_PERF_SEL_SC6_CREDIT_AT_MAX = 738 +PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 739 +PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 740 +PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 741 +PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 742 +PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 743 +PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 744 +PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 745 +PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 746 +PH_PERF_SEL_SC6_PA0_FIFO_FULL = 747 +PH_PERF_SEL_SC6_PA0_NULL_WE = 748 +PH_PERF_SEL_SC6_PA0_EVENT_WE = 749 +PH_PERF_SEL_SC6_PA0_FPOV_WE = 750 +PH_PERF_SEL_SC6_PA0_LPOV_WE = 751 +PH_PERF_SEL_SC6_PA0_EOP_WE = 752 +PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 753 +PH_PERF_SEL_SC6_PA0_EOPG_WE = 754 +PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD = 755 +PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 756 +PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 757 +PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 758 +PH_PERF_SEL_SC6_PA1_FIFO_FULL = 759 +PH_PERF_SEL_SC6_PA1_NULL_WE = 760 +PH_PERF_SEL_SC6_PA1_EVENT_WE = 761 +PH_PERF_SEL_SC6_PA1_FPOV_WE = 762 +PH_PERF_SEL_SC6_PA1_LPOV_WE = 763 +PH_PERF_SEL_SC6_PA1_EOP_WE = 764 +PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 765 +PH_PERF_SEL_SC6_PA1_EOPG_WE = 766 +PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD = 767 +PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 768 +PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 769 +PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 770 +PH_PERF_SEL_SC6_PA2_FIFO_FULL = 771 +PH_PERF_SEL_SC6_PA2_NULL_WE = 772 +PH_PERF_SEL_SC6_PA2_EVENT_WE = 773 +PH_PERF_SEL_SC6_PA2_FPOV_WE = 774 +PH_PERF_SEL_SC6_PA2_LPOV_WE = 775 +PH_PERF_SEL_SC6_PA2_EOP_WE = 776 +PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 777 +PH_PERF_SEL_SC6_PA2_EOPG_WE = 778 +PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD = 779 +PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 780 +PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 781 +PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 782 +PH_PERF_SEL_SC6_PA3_FIFO_FULL = 783 +PH_PERF_SEL_SC6_PA3_NULL_WE = 784 +PH_PERF_SEL_SC6_PA3_EVENT_WE = 785 +PH_PERF_SEL_SC6_PA3_FPOV_WE = 786 +PH_PERF_SEL_SC6_PA3_LPOV_WE = 787 +PH_PERF_SEL_SC6_PA3_EOP_WE = 788 +PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 789 +PH_PERF_SEL_SC6_PA3_EOPG_WE = 790 +PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD = 791 +PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 792 +PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 793 +PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 794 +PH_PERF_SEL_SC6_PA4_FIFO_FULL = 795 +PH_PERF_SEL_SC6_PA4_NULL_WE = 796 +PH_PERF_SEL_SC6_PA4_EVENT_WE = 797 +PH_PERF_SEL_SC6_PA4_FPOV_WE = 798 +PH_PERF_SEL_SC6_PA4_LPOV_WE = 799 +PH_PERF_SEL_SC6_PA4_EOP_WE = 800 +PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 801 +PH_PERF_SEL_SC6_PA4_EOPG_WE = 802 +PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD = 803 +PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 804 +PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 805 +PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 806 +PH_PERF_SEL_SC6_PA5_FIFO_FULL = 807 +PH_PERF_SEL_SC6_PA5_NULL_WE = 808 +PH_PERF_SEL_SC6_PA5_EVENT_WE = 809 +PH_PERF_SEL_SC6_PA5_FPOV_WE = 810 +PH_PERF_SEL_SC6_PA5_LPOV_WE = 811 +PH_PERF_SEL_SC6_PA5_EOP_WE = 812 +PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 813 +PH_PERF_SEL_SC6_PA5_EOPG_WE = 814 +PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD = 815 +PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 816 +PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 817 +PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 818 +PH_PERF_SEL_SC6_PA6_FIFO_FULL = 819 +PH_PERF_SEL_SC6_PA6_NULL_WE = 820 +PH_PERF_SEL_SC6_PA6_EVENT_WE = 821 +PH_PERF_SEL_SC6_PA6_FPOV_WE = 822 +PH_PERF_SEL_SC6_PA6_LPOV_WE = 823 +PH_PERF_SEL_SC6_PA6_EOP_WE = 824 +PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 825 +PH_PERF_SEL_SC6_PA6_EOPG_WE = 826 +PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD = 827 +PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 828 +PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 829 +PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 830 +PH_PERF_SEL_SC6_PA7_FIFO_FULL = 831 +PH_PERF_SEL_SC6_PA7_NULL_WE = 832 +PH_PERF_SEL_SC6_PA7_EVENT_WE = 833 +PH_PERF_SEL_SC6_PA7_FPOV_WE = 834 +PH_PERF_SEL_SC6_PA7_LPOV_WE = 835 +PH_PERF_SEL_SC6_PA7_EOP_WE = 836 +PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 837 +PH_PERF_SEL_SC6_PA7_EOPG_WE = 838 +PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD = 839 +PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 840 +PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 841 +PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 842 +PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 843 +PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 844 +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 845 +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 846 +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 847 +PH_PERF_SEL_SC7_ARB_BUSY = 848 +PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 849 +PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 850 +PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 851 +PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 852 +PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 853 +PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 854 +PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 855 +PH_PERF_SEL_SC7_SEND = 856 +PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 857 +PH_PERF_SEL_SC7_CREDIT_AT_MAX = 858 +PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 859 +PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 860 +PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 861 +PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 862 +PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 863 +PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 864 +PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 865 +PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 866 +PH_PERF_SEL_SC7_PA0_FIFO_FULL = 867 +PH_PERF_SEL_SC7_PA0_NULL_WE = 868 +PH_PERF_SEL_SC7_PA0_EVENT_WE = 869 +PH_PERF_SEL_SC7_PA0_FPOV_WE = 870 +PH_PERF_SEL_SC7_PA0_LPOV_WE = 871 +PH_PERF_SEL_SC7_PA0_EOP_WE = 872 +PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 873 +PH_PERF_SEL_SC7_PA0_EOPG_WE = 874 +PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD = 875 +PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 876 +PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 877 +PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 878 +PH_PERF_SEL_SC7_PA1_FIFO_FULL = 879 +PH_PERF_SEL_SC7_PA1_NULL_WE = 880 +PH_PERF_SEL_SC7_PA1_EVENT_WE = 881 +PH_PERF_SEL_SC7_PA1_FPOV_WE = 882 +PH_PERF_SEL_SC7_PA1_LPOV_WE = 883 +PH_PERF_SEL_SC7_PA1_EOP_WE = 884 +PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 885 +PH_PERF_SEL_SC7_PA1_EOPG_WE = 886 +PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD = 887 +PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 888 +PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 889 +PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 890 +PH_PERF_SEL_SC7_PA2_FIFO_FULL = 891 +PH_PERF_SEL_SC7_PA2_NULL_WE = 892 +PH_PERF_SEL_SC7_PA2_EVENT_WE = 893 +PH_PERF_SEL_SC7_PA2_FPOV_WE = 894 +PH_PERF_SEL_SC7_PA2_LPOV_WE = 895 +PH_PERF_SEL_SC7_PA2_EOP_WE = 896 +PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 897 +PH_PERF_SEL_SC7_PA2_EOPG_WE = 898 +PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD = 899 +PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 900 +PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 901 +PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 902 +PH_PERF_SEL_SC7_PA3_FIFO_FULL = 903 +PH_PERF_SEL_SC7_PA3_NULL_WE = 904 +PH_PERF_SEL_SC7_PA3_EVENT_WE = 905 +PH_PERF_SEL_SC7_PA3_FPOV_WE = 906 +PH_PERF_SEL_SC7_PA3_LPOV_WE = 907 +PH_PERF_SEL_SC7_PA3_EOP_WE = 908 +PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 909 +PH_PERF_SEL_SC7_PA3_EOPG_WE = 910 +PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD = 911 +PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 912 +PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 913 +PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 914 +PH_PERF_SEL_SC7_PA4_FIFO_FULL = 915 +PH_PERF_SEL_SC7_PA4_NULL_WE = 916 +PH_PERF_SEL_SC7_PA4_EVENT_WE = 917 +PH_PERF_SEL_SC7_PA4_FPOV_WE = 918 +PH_PERF_SEL_SC7_PA4_LPOV_WE = 919 +PH_PERF_SEL_SC7_PA4_EOP_WE = 920 +PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 921 +PH_PERF_SEL_SC7_PA4_EOPG_WE = 922 +PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD = 923 +PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 924 +PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 925 +PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 926 +PH_PERF_SEL_SC7_PA5_FIFO_FULL = 927 +PH_PERF_SEL_SC7_PA5_NULL_WE = 928 +PH_PERF_SEL_SC7_PA5_EVENT_WE = 929 +PH_PERF_SEL_SC7_PA5_FPOV_WE = 930 +PH_PERF_SEL_SC7_PA5_LPOV_WE = 931 +PH_PERF_SEL_SC7_PA5_EOP_WE = 932 +PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 933 +PH_PERF_SEL_SC7_PA5_EOPG_WE = 934 +PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD = 935 +PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 936 +PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 937 +PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 938 +PH_PERF_SEL_SC7_PA6_FIFO_FULL = 939 +PH_PERF_SEL_SC7_PA6_NULL_WE = 940 +PH_PERF_SEL_SC7_PA6_EVENT_WE = 941 +PH_PERF_SEL_SC7_PA6_FPOV_WE = 942 +PH_PERF_SEL_SC7_PA6_LPOV_WE = 943 +PH_PERF_SEL_SC7_PA6_EOP_WE = 944 +PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 945 +PH_PERF_SEL_SC7_PA6_EOPG_WE = 946 +PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD = 947 +PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 948 +PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 949 +PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 950 +PH_PERF_SEL_SC7_PA7_FIFO_FULL = 951 +PH_PERF_SEL_SC7_PA7_NULL_WE = 952 +PH_PERF_SEL_SC7_PA7_EVENT_WE = 953 +PH_PERF_SEL_SC7_PA7_FPOV_WE = 954 +PH_PERF_SEL_SC7_PA7_LPOV_WE = 955 +PH_PERF_SEL_SC7_PA7_EOP_WE = 956 +PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 957 +PH_PERF_SEL_SC7_PA7_EOPG_WE = 958 +PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD = 959 +PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 960 +PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 961 +PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 962 +PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 963 +PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 964 +PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 965 +PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 966 +PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 967 +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 968 +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 969 +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 970 +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 971 +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 972 +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 973 +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 974 +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 975 +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 976 +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 977 +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 978 +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 979 +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 980 +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 981 +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 982 +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 983 +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 984 +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 985 +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 986 +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 987 +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 988 +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 989 +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 990 +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 991 +PH_PERF_SC0_FIFO_STATUS_0 = 992 +PH_PERF_SC0_FIFO_STATUS_1 = 993 +PH_PERF_SC0_FIFO_STATUS_2 = 994 +PH_PERF_SC0_FIFO_STATUS_3 = 995 +PH_PERF_SC1_FIFO_STATUS_0 = 996 +PH_PERF_SC1_FIFO_STATUS_1 = 997 +PH_PERF_SC1_FIFO_STATUS_2 = 998 +PH_PERF_SC1_FIFO_STATUS_3 = 999 +PH_PERF_SC2_FIFO_STATUS_0 = 1000 +PH_PERF_SC2_FIFO_STATUS_1 = 1001 +PH_PERF_SC2_FIFO_STATUS_2 = 1002 +PH_PERF_SC2_FIFO_STATUS_3 = 1003 +PH_PERF_SC3_FIFO_STATUS_0 = 1004 +PH_PERF_SC3_FIFO_STATUS_1 = 1005 +PH_PERF_SC3_FIFO_STATUS_2 = 1006 +PH_PERF_SC3_FIFO_STATUS_3 = 1007 +PH_PERF_SC4_FIFO_STATUS_0 = 1008 +PH_PERF_SC4_FIFO_STATUS_1 = 1009 +PH_PERF_SC4_FIFO_STATUS_2 = 1010 +PH_PERF_SC4_FIFO_STATUS_3 = 1011 +PH_PERF_SC5_FIFO_STATUS_0 = 1012 +PH_PERF_SC5_FIFO_STATUS_1 = 1013 +PH_PERF_SC5_FIFO_STATUS_2 = 1014 +PH_PERF_SC5_FIFO_STATUS_3 = 1015 +PH_PERF_SC6_FIFO_STATUS_0 = 1016 +PH_PERF_SC6_FIFO_STATUS_1 = 1017 +PH_PERF_SC6_FIFO_STATUS_2 = 1018 +PH_PERF_SC6_FIFO_STATUS_3 = 1019 +PH_PERF_SC7_FIFO_STATUS_0 = 1020 +PH_PERF_SC7_FIFO_STATUS_1 = 1021 +PH_PERF_SC7_FIFO_STATUS_2 = 1022 +PH_PERF_SC7_FIFO_STATUS_3 = 1023 +PH_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PhSPIstatusMode' +PhSPIstatusMode__enumvalues = { + 0: 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', + 1: 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', + 2: 'PH_SPI_MODE_DISABLED', +} +PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0 +PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 1 +PH_SPI_MODE_DISABLED = 2 +PhSPIstatusMode = ctypes.c_uint32 # enum + +# values for enumeration 'RMIPerfSel' +RMIPerfSel__enumvalues = { + 0: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', + 1: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', +} +RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0 +RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 1 +RMIPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'GCRPerfSel' +GCRPerfSel__enumvalues = { + 0: 'GCR_PERF_SEL_NONE', + 1: 'GCR_PERF_SEL_SDMA0_ALL_REQ', + 2: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', + 3: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', + 4: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', + 5: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', + 6: 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', + 7: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', + 8: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', + 9: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', + 10: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', + 11: 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', + 12: 'GCR_PERF_SEL_SDMA0_METADATA_REQ', + 13: 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', + 14: 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', + 15: 'GCR_PERF_SEL_SDMA0_TCP_REQ', + 16: 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', + 17: 'GCR_PERF_SEL_SDMA1_ALL_REQ', + 18: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', + 19: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', + 20: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', + 21: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', + 22: 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', + 23: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', + 24: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', + 25: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', + 26: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', + 27: 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', + 28: 'GCR_PERF_SEL_SDMA1_METADATA_REQ', + 29: 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', + 30: 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', + 31: 'GCR_PERF_SEL_SDMA1_TCP_REQ', + 32: 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', + 33: 'GCR_PERF_SEL_CPC_ALL_REQ', + 34: 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', + 35: 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', + 36: 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', + 37: 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', + 38: 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', + 39: 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', + 40: 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', + 41: 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', + 42: 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', + 43: 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', + 44: 'GCR_PERF_SEL_CPC_METADATA_REQ', + 45: 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', + 46: 'GCR_PERF_SEL_CPC_SQC_INST_REQ', + 47: 'GCR_PERF_SEL_CPC_TCP_REQ', + 48: 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', + 49: 'GCR_PERF_SEL_CPG_ALL_REQ', + 50: 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', + 51: 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', + 52: 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', + 53: 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', + 54: 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', + 55: 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', + 56: 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', + 57: 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', + 58: 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', + 59: 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', + 60: 'GCR_PERF_SEL_CPG_METADATA_REQ', + 61: 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', + 62: 'GCR_PERF_SEL_CPG_SQC_INST_REQ', + 63: 'GCR_PERF_SEL_CPG_TCP_REQ', + 64: 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', + 65: 'GCR_PERF_SEL_CPF_ALL_REQ', + 66: 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', + 67: 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', + 68: 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', + 69: 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', + 70: 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', + 71: 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', + 72: 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', + 73: 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', + 74: 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', + 75: 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', + 76: 'GCR_PERF_SEL_CPF_METADATA_REQ', + 77: 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', + 78: 'GCR_PERF_SEL_CPF_SQC_INST_REQ', + 79: 'GCR_PERF_SEL_CPF_TCP_REQ', + 80: 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', + 81: 'GCR_PERF_SEL_VIRT_REQ', + 82: 'GCR_PERF_SEL_PHY_REQ', + 83: 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', + 84: 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', + 85: 'GCR_PERF_SEL_ALL_REQ', + 86: 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', + 87: 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', + 88: 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', + 89: 'GCR_PERF_SEL_UTCL2_REQ', + 90: 'GCR_PERF_SEL_UTCL2_RET', + 91: 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', + 92: 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', + 93: 'GCR_PERF_SEL_UTCL2_FILTERED_RET', + 94: 'GCR_PERF_SEL_RLC_ALL_REQ', + 95: 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', + 96: 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', + 97: 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', + 98: 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', + 99: 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', + 100: 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', + 101: 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', + 102: 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', + 103: 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', + 104: 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', + 105: 'GCR_PERF_SEL_RLC_METADATA_REQ', + 106: 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', + 107: 'GCR_PERF_SEL_RLC_SQC_INST_REQ', + 108: 'GCR_PERF_SEL_RLC_TCP_REQ', + 109: 'GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ', + 110: 'GCR_PERF_SEL_PM_ALL_REQ', + 111: 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', + 112: 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', + 113: 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', + 114: 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', + 115: 'GCR_PERF_SEL_PM_GL2_ALL_REQ', + 116: 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', + 117: 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', + 118: 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', + 119: 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', + 120: 'GCR_PERF_SEL_PM_GL1_ALL_REQ', + 121: 'GCR_PERF_SEL_PM_METADATA_REQ', + 122: 'GCR_PERF_SEL_PM_SQC_DATA_REQ', + 123: 'GCR_PERF_SEL_PM_SQC_INST_REQ', + 124: 'GCR_PERF_SEL_PM_TCP_REQ', + 125: 'GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ', + 126: 'GCR_PERF_SEL_PIO_ALL_REQ', + 127: 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', + 128: 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', + 129: 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', + 130: 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', + 131: 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', + 132: 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', + 133: 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', + 134: 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', + 135: 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', + 136: 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', + 137: 'GCR_PERF_SEL_PIO_METADATA_REQ', + 138: 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', + 139: 'GCR_PERF_SEL_PIO_SQC_INST_REQ', + 140: 'GCR_PERF_SEL_PIO_TCP_REQ', + 141: 'GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ', +} +GCR_PERF_SEL_NONE = 0 +GCR_PERF_SEL_SDMA0_ALL_REQ = 1 +GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 2 +GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 3 +GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 4 +GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 5 +GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 6 +GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 7 +GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 8 +GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 9 +GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 10 +GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 11 +GCR_PERF_SEL_SDMA0_METADATA_REQ = 12 +GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 13 +GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 14 +GCR_PERF_SEL_SDMA0_TCP_REQ = 15 +GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 16 +GCR_PERF_SEL_SDMA1_ALL_REQ = 17 +GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 18 +GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 19 +GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 20 +GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 21 +GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 22 +GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 23 +GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 24 +GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 25 +GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 26 +GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 27 +GCR_PERF_SEL_SDMA1_METADATA_REQ = 28 +GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 29 +GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 30 +GCR_PERF_SEL_SDMA1_TCP_REQ = 31 +GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 32 +GCR_PERF_SEL_CPC_ALL_REQ = 33 +GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 34 +GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 35 +GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 36 +GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 37 +GCR_PERF_SEL_CPC_GL2_ALL_REQ = 38 +GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 39 +GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 40 +GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 41 +GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 42 +GCR_PERF_SEL_CPC_GL1_ALL_REQ = 43 +GCR_PERF_SEL_CPC_METADATA_REQ = 44 +GCR_PERF_SEL_CPC_SQC_DATA_REQ = 45 +GCR_PERF_SEL_CPC_SQC_INST_REQ = 46 +GCR_PERF_SEL_CPC_TCP_REQ = 47 +GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 48 +GCR_PERF_SEL_CPG_ALL_REQ = 49 +GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 50 +GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 51 +GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 52 +GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 53 +GCR_PERF_SEL_CPG_GL2_ALL_REQ = 54 +GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 55 +GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 56 +GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 57 +GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 58 +GCR_PERF_SEL_CPG_GL1_ALL_REQ = 59 +GCR_PERF_SEL_CPG_METADATA_REQ = 60 +GCR_PERF_SEL_CPG_SQC_DATA_REQ = 61 +GCR_PERF_SEL_CPG_SQC_INST_REQ = 62 +GCR_PERF_SEL_CPG_TCP_REQ = 63 +GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 64 +GCR_PERF_SEL_CPF_ALL_REQ = 65 +GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 66 +GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 67 +GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 68 +GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 69 +GCR_PERF_SEL_CPF_GL2_ALL_REQ = 70 +GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 71 +GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 72 +GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 73 +GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 74 +GCR_PERF_SEL_CPF_GL1_ALL_REQ = 75 +GCR_PERF_SEL_CPF_METADATA_REQ = 76 +GCR_PERF_SEL_CPF_SQC_DATA_REQ = 77 +GCR_PERF_SEL_CPF_SQC_INST_REQ = 78 +GCR_PERF_SEL_CPF_TCP_REQ = 79 +GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 80 +GCR_PERF_SEL_VIRT_REQ = 81 +GCR_PERF_SEL_PHY_REQ = 82 +GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 83 +GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 84 +GCR_PERF_SEL_ALL_REQ = 85 +GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 86 +GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 87 +GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 88 +GCR_PERF_SEL_UTCL2_REQ = 89 +GCR_PERF_SEL_UTCL2_RET = 90 +GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 91 +GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 92 +GCR_PERF_SEL_UTCL2_FILTERED_RET = 93 +GCR_PERF_SEL_RLC_ALL_REQ = 94 +GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 95 +GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 96 +GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 97 +GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 98 +GCR_PERF_SEL_RLC_GL2_ALL_REQ = 99 +GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 100 +GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 101 +GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 102 +GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 103 +GCR_PERF_SEL_RLC_GL1_ALL_REQ = 104 +GCR_PERF_SEL_RLC_METADATA_REQ = 105 +GCR_PERF_SEL_RLC_SQC_DATA_REQ = 106 +GCR_PERF_SEL_RLC_SQC_INST_REQ = 107 +GCR_PERF_SEL_RLC_TCP_REQ = 108 +GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ = 109 +GCR_PERF_SEL_PM_ALL_REQ = 110 +GCR_PERF_SEL_PM_GL2_RANGE_REQ = 111 +GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 112 +GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 113 +GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 114 +GCR_PERF_SEL_PM_GL2_ALL_REQ = 115 +GCR_PERF_SEL_PM_GL1_RANGE_REQ = 116 +GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 117 +GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 118 +GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 119 +GCR_PERF_SEL_PM_GL1_ALL_REQ = 120 +GCR_PERF_SEL_PM_METADATA_REQ = 121 +GCR_PERF_SEL_PM_SQC_DATA_REQ = 122 +GCR_PERF_SEL_PM_SQC_INST_REQ = 123 +GCR_PERF_SEL_PM_TCP_REQ = 124 +GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ = 125 +GCR_PERF_SEL_PIO_ALL_REQ = 126 +GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 127 +GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 128 +GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 129 +GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 130 +GCR_PERF_SEL_PIO_GL2_ALL_REQ = 131 +GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 132 +GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 133 +GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 134 +GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 135 +GCR_PERF_SEL_PIO_GL1_ALL_REQ = 136 +GCR_PERF_SEL_PIO_METADATA_REQ = 137 +GCR_PERF_SEL_PIO_SQC_DATA_REQ = 138 +GCR_PERF_SEL_PIO_SQC_INST_REQ = 139 +GCR_PERF_SEL_PIO_TCP_REQ = 140 +GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ = 141 +GCRPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1PerfSel' +UTCL1PerfSel__enumvalues = { + 0: 'UTCL1_PERF_SEL_NONE', + 1: 'UTCL1_PERF_SEL_REQS', + 2: 'UTCL1_PERF_SEL_HITS', + 3: 'UTCL1_PERF_SEL_MISSES', + 4: 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', + 5: 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', + 6: 'UTCL1_PERF_SEL_UTCL2_REQS', + 7: 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', + 8: 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', + 9: 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', + 10: 'UTCL1_PERF_SEL_STALL_MH_FULL', + 11: 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', + 12: 'UTCL1_PERF_SEL_UTCL2_RET_CNT', + 13: 'UTCL1_PERF_SEL_RTNS', + 14: 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', + 15: 'UTCL1_PERF_SEL_BYPASS_REQS', + 16: 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', + 17: 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', + 18: 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', + 19: 'UTCL1_PERF_SEL_CP_INVREQS', + 20: 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', + 21: 'UTCL1_PERF_SEL_RANGE_INVREQS', + 22: 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', +} +UTCL1_PERF_SEL_NONE = 0 +UTCL1_PERF_SEL_REQS = 1 +UTCL1_PERF_SEL_HITS = 2 +UTCL1_PERF_SEL_MISSES = 3 +UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 4 +UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 5 +UTCL1_PERF_SEL_UTCL2_REQS = 6 +UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 7 +UTCL1_PERF_SEL_UTCL2_RET_FAULT = 8 +UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 9 +UTCL1_PERF_SEL_STALL_MH_FULL = 10 +UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 11 +UTCL1_PERF_SEL_UTCL2_RET_CNT = 12 +UTCL1_PERF_SEL_RTNS = 13 +UTCL1_PERF_SEL_XLAT_REQ_BUSY = 14 +UTCL1_PERF_SEL_BYPASS_REQS = 15 +UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 16 +UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 17 +UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 18 +UTCL1_PERF_SEL_CP_INVREQS = 19 +UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 20 +UTCL1_PERF_SEL_RANGE_INVREQS = 21 +UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 22 +UTCL1PerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'IH_CLIENT_TYPE' +IH_CLIENT_TYPE__enumvalues = { + 0: 'IH_GFX_VMID_CLIENT', + 1: 'IH_MM_VMID_CLIENT', + 2: 'IH_MULTI_VMID_CLIENT', + 3: 'IH_CLIENT_TYPE_RESERVED', +} +IH_GFX_VMID_CLIENT = 0 +IH_MM_VMID_CLIENT = 1 +IH_MULTI_VMID_CLIENT = 2 +IH_CLIENT_TYPE_RESERVED = 3 +IH_CLIENT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'IH_INTERFACE_TYPE' +IH_INTERFACE_TYPE__enumvalues = { + 0: 'IH_LEGACY_INTERFACE', + 1: 'IH_REGISTER_WRITE_INTERFACE', +} +IH_LEGACY_INTERFACE = 0 +IH_REGISTER_WRITE_INTERFACE = 1 +IH_INTERFACE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'IH_PERF_SEL' +IH_PERF_SEL__enumvalues = { + 0: 'IH_PERF_SEL_CYCLE', + 1: 'IH_PERF_SEL_IDLE', + 2: 'IH_PERF_SEL_INPUT_IDLE', + 3: 'IH_PERF_SEL_BUFFER_IDLE', + 4: 'IH_PERF_SEL_RB0_FULL', + 5: 'IH_PERF_SEL_RB0_OVERFLOW', + 6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', + 7: 'IH_PERF_SEL_RB0_WPTR_WRAP', + 8: 'IH_PERF_SEL_RB0_RPTR_WRAP', + 9: 'IH_PERF_SEL_MC_WR_IDLE', + 10: 'IH_PERF_SEL_MC_WR_COUNT', + 11: 'IH_PERF_SEL_MC_WR_STALL', + 12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', + 13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL', + 14: 'IH_PERF_SEL_BIF_LINE0_RISING', + 15: 'IH_PERF_SEL_BIF_LINE0_FALLING', + 16: 'IH_PERF_SEL_RB1_FULL', + 17: 'IH_PERF_SEL_RB1_OVERFLOW', + 18: 'IH_PERF_SEL_COOKIE_REC_ERROR', + 19: 'IH_PERF_SEL_RB1_WPTR_WRAP', + 20: 'IH_PERF_SEL_RB1_RPTR_WRAP', + 21: 'IH_PERF_SEL_RB2_FULL', + 22: 'IH_PERF_SEL_RB2_OVERFLOW', + 23: 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', + 24: 'IH_PERF_SEL_RB2_WPTR_WRAP', + 25: 'IH_PERF_SEL_RB2_RPTR_WRAP', + 26: 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', + 27: 'IH_PERF_SEL_SELF_IV_VALID', + 28: 'IH_PERF_SEL_BUFFER_FIFO_FULL', + 29: 'IH_PERF_SEL_RB0_FULL_VF0', + 30: 'IH_PERF_SEL_RB0_FULL_VF1', + 31: 'IH_PERF_SEL_RB0_FULL_VF2', + 32: 'IH_PERF_SEL_RB0_FULL_VF3', + 33: 'IH_PERF_SEL_RB0_FULL_VF4', + 34: 'IH_PERF_SEL_RB0_FULL_VF5', + 35: 'IH_PERF_SEL_RB0_FULL_VF6', + 36: 'IH_PERF_SEL_RB0_FULL_VF7', + 37: 'IH_PERF_SEL_RB0_FULL_VF8', + 38: 'IH_PERF_SEL_RB0_FULL_VF9', + 39: 'IH_PERF_SEL_RB0_FULL_VF10', + 40: 'IH_PERF_SEL_RB0_FULL_VF11', + 41: 'IH_PERF_SEL_RB0_FULL_VF12', + 42: 'IH_PERF_SEL_RB0_FULL_VF13', + 43: 'IH_PERF_SEL_RB0_FULL_VF14', + 44: 'IH_PERF_SEL_RB0_FULL_VF15', + 45: 'IH_PERF_SEL_RB0_OVERFLOW_VF0', + 46: 'IH_PERF_SEL_RB0_OVERFLOW_VF1', + 47: 'IH_PERF_SEL_RB0_OVERFLOW_VF2', + 48: 'IH_PERF_SEL_RB0_OVERFLOW_VF3', + 49: 'IH_PERF_SEL_RB0_OVERFLOW_VF4', + 50: 'IH_PERF_SEL_RB0_OVERFLOW_VF5', + 51: 'IH_PERF_SEL_RB0_OVERFLOW_VF6', + 52: 'IH_PERF_SEL_RB0_OVERFLOW_VF7', + 53: 'IH_PERF_SEL_RB0_OVERFLOW_VF8', + 54: 'IH_PERF_SEL_RB0_OVERFLOW_VF9', + 55: 'IH_PERF_SEL_RB0_OVERFLOW_VF10', + 56: 'IH_PERF_SEL_RB0_OVERFLOW_VF11', + 57: 'IH_PERF_SEL_RB0_OVERFLOW_VF12', + 58: 'IH_PERF_SEL_RB0_OVERFLOW_VF13', + 59: 'IH_PERF_SEL_RB0_OVERFLOW_VF14', + 60: 'IH_PERF_SEL_RB0_OVERFLOW_VF15', + 61: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', + 62: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', + 63: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', + 64: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', + 65: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', + 66: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', + 67: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', + 68: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', + 69: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', + 70: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', + 71: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', + 72: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', + 73: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', + 74: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', + 75: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', + 76: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', + 77: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', + 78: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', + 79: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', + 80: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', + 81: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', + 82: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', + 83: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', + 84: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', + 85: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', + 86: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', + 87: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', + 88: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', + 89: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', + 90: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', + 91: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', + 92: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', + 93: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', + 94: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', + 95: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', + 96: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', + 97: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', + 98: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', + 99: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', + 100: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', + 101: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', + 102: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', + 103: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', + 104: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', + 105: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', + 106: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', + 107: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', + 108: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', + 109: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', + 110: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', + 111: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', + 112: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', + 113: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', + 114: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', + 115: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', + 116: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', + 117: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', + 118: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', + 119: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', + 120: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', + 121: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', + 122: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', + 123: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', + 124: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', + 125: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', + 126: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', + 127: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', + 128: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', + 129: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', + 130: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', + 131: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', + 132: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', + 133: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', + 134: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', + 135: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', + 136: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', + 137: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', + 138: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', + 139: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', + 140: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', + 141: 'IH_PERF_SEL_CLIENT0_INT', + 142: 'IH_PERF_SEL_CLIENT1_INT', + 143: 'IH_PERF_SEL_CLIENT2_INT', + 144: 'IH_PERF_SEL_CLIENT3_INT', + 145: 'IH_PERF_SEL_CLIENT4_INT', + 146: 'IH_PERF_SEL_CLIENT5_INT', + 147: 'IH_PERF_SEL_CLIENT6_INT', + 148: 'IH_PERF_SEL_CLIENT7_INT', + 149: 'IH_PERF_SEL_CLIENT8_INT', + 150: 'IH_PERF_SEL_CLIENT9_INT', + 151: 'IH_PERF_SEL_CLIENT10_INT', + 152: 'IH_PERF_SEL_CLIENT11_INT', + 153: 'IH_PERF_SEL_CLIENT12_INT', + 154: 'IH_PERF_SEL_CLIENT13_INT', + 155: 'IH_PERF_SEL_CLIENT14_INT', + 156: 'IH_PERF_SEL_CLIENT15_INT', + 157: 'IH_PERF_SEL_CLIENT16_INT', + 158: 'IH_PERF_SEL_CLIENT17_INT', + 159: 'IH_PERF_SEL_CLIENT18_INT', + 160: 'IH_PERF_SEL_CLIENT19_INT', + 161: 'IH_PERF_SEL_CLIENT20_INT', + 162: 'IH_PERF_SEL_CLIENT21_INT', + 163: 'IH_PERF_SEL_CLIENT22_INT', + 164: 'IH_PERF_SEL_CLIENT23_INT', + 165: 'IH_PERF_SEL_CLIENT24_INT', + 166: 'IH_PERF_SEL_CLIENT25_INT', + 167: 'IH_PERF_SEL_CLIENT26_INT', + 168: 'IH_PERF_SEL_CLIENT27_INT', + 169: 'IH_PERF_SEL_CLIENT28_INT', + 170: 'IH_PERF_SEL_CLIENT29_INT', + 171: 'IH_PERF_SEL_CLIENT30_INT', + 172: 'IH_PERF_SEL_CLIENT31_INT', + 173: 'IH_PERF_SEL_RB1_FULL_VF0', + 174: 'IH_PERF_SEL_RB1_FULL_VF1', + 175: 'IH_PERF_SEL_RB1_FULL_VF2', + 176: 'IH_PERF_SEL_RB1_FULL_VF3', + 177: 'IH_PERF_SEL_RB1_FULL_VF4', + 178: 'IH_PERF_SEL_RB1_FULL_VF5', + 179: 'IH_PERF_SEL_RB1_FULL_VF6', + 180: 'IH_PERF_SEL_RB1_FULL_VF7', + 181: 'IH_PERF_SEL_RB1_FULL_VF8', + 182: 'IH_PERF_SEL_RB1_FULL_VF9', + 183: 'IH_PERF_SEL_RB1_FULL_VF10', + 184: 'IH_PERF_SEL_RB1_FULL_VF11', + 185: 'IH_PERF_SEL_RB1_FULL_VF12', + 186: 'IH_PERF_SEL_RB1_FULL_VF13', + 187: 'IH_PERF_SEL_RB1_FULL_VF14', + 188: 'IH_PERF_SEL_RB1_FULL_VF15', + 189: 'IH_PERF_SEL_RB1_OVERFLOW_VF0', + 190: 'IH_PERF_SEL_RB1_OVERFLOW_VF1', + 191: 'IH_PERF_SEL_RB1_OVERFLOW_VF2', + 192: 'IH_PERF_SEL_RB1_OVERFLOW_VF3', + 193: 'IH_PERF_SEL_RB1_OVERFLOW_VF4', + 194: 'IH_PERF_SEL_RB1_OVERFLOW_VF5', + 195: 'IH_PERF_SEL_RB1_OVERFLOW_VF6', + 196: 'IH_PERF_SEL_RB1_OVERFLOW_VF7', + 197: 'IH_PERF_SEL_RB1_OVERFLOW_VF8', + 198: 'IH_PERF_SEL_RB1_OVERFLOW_VF9', + 199: 'IH_PERF_SEL_RB1_OVERFLOW_VF10', + 200: 'IH_PERF_SEL_RB1_OVERFLOW_VF11', + 201: 'IH_PERF_SEL_RB1_OVERFLOW_VF12', + 202: 'IH_PERF_SEL_RB1_OVERFLOW_VF13', + 203: 'IH_PERF_SEL_RB1_OVERFLOW_VF14', + 204: 'IH_PERF_SEL_RB1_OVERFLOW_VF15', + 205: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', + 206: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', + 207: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', + 208: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', + 209: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', + 210: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', + 211: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', + 212: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', + 213: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', + 214: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', + 215: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', + 216: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', + 217: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', + 218: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', + 219: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', + 220: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', + 221: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', + 222: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', + 223: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', + 224: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', + 225: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', + 226: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', + 227: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', + 228: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', + 229: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', + 230: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', + 231: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', + 232: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', + 233: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', + 234: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', + 235: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', + 236: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', + 237: 'IH_PERF_SEL_RB2_FULL_VF0', + 238: 'IH_PERF_SEL_RB2_FULL_VF1', + 239: 'IH_PERF_SEL_RB2_FULL_VF2', + 240: 'IH_PERF_SEL_RB2_FULL_VF3', + 241: 'IH_PERF_SEL_RB2_FULL_VF4', + 242: 'IH_PERF_SEL_RB2_FULL_VF5', + 243: 'IH_PERF_SEL_RB2_FULL_VF6', + 244: 'IH_PERF_SEL_RB2_FULL_VF7', + 245: 'IH_PERF_SEL_RB2_FULL_VF8', + 246: 'IH_PERF_SEL_RB2_FULL_VF9', + 247: 'IH_PERF_SEL_RB2_FULL_VF10', + 248: 'IH_PERF_SEL_RB2_FULL_VF11', + 249: 'IH_PERF_SEL_RB2_FULL_VF12', + 250: 'IH_PERF_SEL_RB2_FULL_VF13', + 251: 'IH_PERF_SEL_RB2_FULL_VF14', + 252: 'IH_PERF_SEL_RB2_FULL_VF15', + 253: 'IH_PERF_SEL_RB2_OVERFLOW_VF0', + 254: 'IH_PERF_SEL_RB2_OVERFLOW_VF1', + 255: 'IH_PERF_SEL_RB2_OVERFLOW_VF2', + 256: 'IH_PERF_SEL_RB2_OVERFLOW_VF3', + 257: 'IH_PERF_SEL_RB2_OVERFLOW_VF4', + 258: 'IH_PERF_SEL_RB2_OVERFLOW_VF5', + 259: 'IH_PERF_SEL_RB2_OVERFLOW_VF6', + 260: 'IH_PERF_SEL_RB2_OVERFLOW_VF7', + 261: 'IH_PERF_SEL_RB2_OVERFLOW_VF8', + 262: 'IH_PERF_SEL_RB2_OVERFLOW_VF9', + 263: 'IH_PERF_SEL_RB2_OVERFLOW_VF10', + 264: 'IH_PERF_SEL_RB2_OVERFLOW_VF11', + 265: 'IH_PERF_SEL_RB2_OVERFLOW_VF12', + 266: 'IH_PERF_SEL_RB2_OVERFLOW_VF13', + 267: 'IH_PERF_SEL_RB2_OVERFLOW_VF14', + 268: 'IH_PERF_SEL_RB2_OVERFLOW_VF15', + 269: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', + 270: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', + 271: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', + 272: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', + 273: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', + 274: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', + 275: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', + 276: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', + 277: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', + 278: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', + 279: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', + 280: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', + 281: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', + 282: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', + 283: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', + 284: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', + 285: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', + 286: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', + 287: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', + 288: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', + 289: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', + 290: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', + 291: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', + 292: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', + 293: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', + 294: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', + 295: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', + 296: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', + 297: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', + 298: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', + 299: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', + 300: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', + 301: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', + 302: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', + 303: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', + 304: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', + 305: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', + 306: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', + 307: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', + 308: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', + 309: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', + 310: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', + 311: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', + 312: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', + 313: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', + 314: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', + 315: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', + 316: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', + 317: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', + 318: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', + 319: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', + 320: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', + 321: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', + 322: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', + 323: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', + 324: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', + 325: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', + 326: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', + 327: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', + 328: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', + 329: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', + 330: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', + 331: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', + 332: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', + 333: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', + 334: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', + 335: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', + 336: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', + 337: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', + 338: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', + 339: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', + 340: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', + 341: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', + 342: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', + 343: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', + 344: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', + 345: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', + 346: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', + 347: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', + 348: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', + 349: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', + 350: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', + 351: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', + 352: 'IH_PERF_SEL_RB0_LOAD_RPTR', + 353: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', + 354: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', + 355: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', + 356: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', + 357: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', + 358: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', + 359: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', + 360: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', + 361: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', + 362: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', + 363: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', + 364: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', + 365: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', + 366: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', + 367: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', + 368: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', + 369: 'IH_PERF_SEL_RB1_LOAD_RPTR', + 370: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', + 371: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', + 372: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', + 373: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', + 374: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', + 375: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', + 376: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', + 377: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', + 378: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', + 379: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', + 380: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', + 381: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', + 382: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', + 383: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', + 384: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', + 385: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', + 386: 'IH_PERF_SEL_RB2_LOAD_RPTR', + 387: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', + 388: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', + 389: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', + 390: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', + 391: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', + 392: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', + 393: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', + 394: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', + 395: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', + 396: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', + 397: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', + 398: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', + 399: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', + 400: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', + 401: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', + 402: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', +} +IH_PERF_SEL_CYCLE = 0 +IH_PERF_SEL_IDLE = 1 +IH_PERF_SEL_INPUT_IDLE = 2 +IH_PERF_SEL_BUFFER_IDLE = 3 +IH_PERF_SEL_RB0_FULL = 4 +IH_PERF_SEL_RB0_OVERFLOW = 5 +IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6 +IH_PERF_SEL_RB0_WPTR_WRAP = 7 +IH_PERF_SEL_RB0_RPTR_WRAP = 8 +IH_PERF_SEL_MC_WR_IDLE = 9 +IH_PERF_SEL_MC_WR_COUNT = 10 +IH_PERF_SEL_MC_WR_STALL = 11 +IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12 +IH_PERF_SEL_MC_WR_CLEAN_STALL = 13 +IH_PERF_SEL_BIF_LINE0_RISING = 14 +IH_PERF_SEL_BIF_LINE0_FALLING = 15 +IH_PERF_SEL_RB1_FULL = 16 +IH_PERF_SEL_RB1_OVERFLOW = 17 +IH_PERF_SEL_COOKIE_REC_ERROR = 18 +IH_PERF_SEL_RB1_WPTR_WRAP = 19 +IH_PERF_SEL_RB1_RPTR_WRAP = 20 +IH_PERF_SEL_RB2_FULL = 21 +IH_PERF_SEL_RB2_OVERFLOW = 22 +IH_PERF_SEL_CLIENT_CREDIT_ERROR = 23 +IH_PERF_SEL_RB2_WPTR_WRAP = 24 +IH_PERF_SEL_RB2_RPTR_WRAP = 25 +IH_PERF_SEL_STORM_CLIENT_INT_DROP = 26 +IH_PERF_SEL_SELF_IV_VALID = 27 +IH_PERF_SEL_BUFFER_FIFO_FULL = 28 +IH_PERF_SEL_RB0_FULL_VF0 = 29 +IH_PERF_SEL_RB0_FULL_VF1 = 30 +IH_PERF_SEL_RB0_FULL_VF2 = 31 +IH_PERF_SEL_RB0_FULL_VF3 = 32 +IH_PERF_SEL_RB0_FULL_VF4 = 33 +IH_PERF_SEL_RB0_FULL_VF5 = 34 +IH_PERF_SEL_RB0_FULL_VF6 = 35 +IH_PERF_SEL_RB0_FULL_VF7 = 36 +IH_PERF_SEL_RB0_FULL_VF8 = 37 +IH_PERF_SEL_RB0_FULL_VF9 = 38 +IH_PERF_SEL_RB0_FULL_VF10 = 39 +IH_PERF_SEL_RB0_FULL_VF11 = 40 +IH_PERF_SEL_RB0_FULL_VF12 = 41 +IH_PERF_SEL_RB0_FULL_VF13 = 42 +IH_PERF_SEL_RB0_FULL_VF14 = 43 +IH_PERF_SEL_RB0_FULL_VF15 = 44 +IH_PERF_SEL_RB0_OVERFLOW_VF0 = 45 +IH_PERF_SEL_RB0_OVERFLOW_VF1 = 46 +IH_PERF_SEL_RB0_OVERFLOW_VF2 = 47 +IH_PERF_SEL_RB0_OVERFLOW_VF3 = 48 +IH_PERF_SEL_RB0_OVERFLOW_VF4 = 49 +IH_PERF_SEL_RB0_OVERFLOW_VF5 = 50 +IH_PERF_SEL_RB0_OVERFLOW_VF6 = 51 +IH_PERF_SEL_RB0_OVERFLOW_VF7 = 52 +IH_PERF_SEL_RB0_OVERFLOW_VF8 = 53 +IH_PERF_SEL_RB0_OVERFLOW_VF9 = 54 +IH_PERF_SEL_RB0_OVERFLOW_VF10 = 55 +IH_PERF_SEL_RB0_OVERFLOW_VF11 = 56 +IH_PERF_SEL_RB0_OVERFLOW_VF12 = 57 +IH_PERF_SEL_RB0_OVERFLOW_VF13 = 58 +IH_PERF_SEL_RB0_OVERFLOW_VF14 = 59 +IH_PERF_SEL_RB0_OVERFLOW_VF15 = 60 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 61 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 62 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 63 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 64 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 65 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 66 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 67 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 68 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 69 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 70 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 71 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 72 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 73 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 74 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 75 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 76 +IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 77 +IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 78 +IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 79 +IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 80 +IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 81 +IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 82 +IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 83 +IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 84 +IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 85 +IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 86 +IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 87 +IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 88 +IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 89 +IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 90 +IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 91 +IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 92 +IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 93 +IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 94 +IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 95 +IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 96 +IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 97 +IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 98 +IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 99 +IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 100 +IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 101 +IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 102 +IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 103 +IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 104 +IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 105 +IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 106 +IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 107 +IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 108 +IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 109 +IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 110 +IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 111 +IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 112 +IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 113 +IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 114 +IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 115 +IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 116 +IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 117 +IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 118 +IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 119 +IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 120 +IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 121 +IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 122 +IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 123 +IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 124 +IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 125 +IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 126 +IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 127 +IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 128 +IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 129 +IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 130 +IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 131 +IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 132 +IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 133 +IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 134 +IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 135 +IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 136 +IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 137 +IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 138 +IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 139 +IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 140 +IH_PERF_SEL_CLIENT0_INT = 141 +IH_PERF_SEL_CLIENT1_INT = 142 +IH_PERF_SEL_CLIENT2_INT = 143 +IH_PERF_SEL_CLIENT3_INT = 144 +IH_PERF_SEL_CLIENT4_INT = 145 +IH_PERF_SEL_CLIENT5_INT = 146 +IH_PERF_SEL_CLIENT6_INT = 147 +IH_PERF_SEL_CLIENT7_INT = 148 +IH_PERF_SEL_CLIENT8_INT = 149 +IH_PERF_SEL_CLIENT9_INT = 150 +IH_PERF_SEL_CLIENT10_INT = 151 +IH_PERF_SEL_CLIENT11_INT = 152 +IH_PERF_SEL_CLIENT12_INT = 153 +IH_PERF_SEL_CLIENT13_INT = 154 +IH_PERF_SEL_CLIENT14_INT = 155 +IH_PERF_SEL_CLIENT15_INT = 156 +IH_PERF_SEL_CLIENT16_INT = 157 +IH_PERF_SEL_CLIENT17_INT = 158 +IH_PERF_SEL_CLIENT18_INT = 159 +IH_PERF_SEL_CLIENT19_INT = 160 +IH_PERF_SEL_CLIENT20_INT = 161 +IH_PERF_SEL_CLIENT21_INT = 162 +IH_PERF_SEL_CLIENT22_INT = 163 +IH_PERF_SEL_CLIENT23_INT = 164 +IH_PERF_SEL_CLIENT24_INT = 165 +IH_PERF_SEL_CLIENT25_INT = 166 +IH_PERF_SEL_CLIENT26_INT = 167 +IH_PERF_SEL_CLIENT27_INT = 168 +IH_PERF_SEL_CLIENT28_INT = 169 +IH_PERF_SEL_CLIENT29_INT = 170 +IH_PERF_SEL_CLIENT30_INT = 171 +IH_PERF_SEL_CLIENT31_INT = 172 +IH_PERF_SEL_RB1_FULL_VF0 = 173 +IH_PERF_SEL_RB1_FULL_VF1 = 174 +IH_PERF_SEL_RB1_FULL_VF2 = 175 +IH_PERF_SEL_RB1_FULL_VF3 = 176 +IH_PERF_SEL_RB1_FULL_VF4 = 177 +IH_PERF_SEL_RB1_FULL_VF5 = 178 +IH_PERF_SEL_RB1_FULL_VF6 = 179 +IH_PERF_SEL_RB1_FULL_VF7 = 180 +IH_PERF_SEL_RB1_FULL_VF8 = 181 +IH_PERF_SEL_RB1_FULL_VF9 = 182 +IH_PERF_SEL_RB1_FULL_VF10 = 183 +IH_PERF_SEL_RB1_FULL_VF11 = 184 +IH_PERF_SEL_RB1_FULL_VF12 = 185 +IH_PERF_SEL_RB1_FULL_VF13 = 186 +IH_PERF_SEL_RB1_FULL_VF14 = 187 +IH_PERF_SEL_RB1_FULL_VF15 = 188 +IH_PERF_SEL_RB1_OVERFLOW_VF0 = 189 +IH_PERF_SEL_RB1_OVERFLOW_VF1 = 190 +IH_PERF_SEL_RB1_OVERFLOW_VF2 = 191 +IH_PERF_SEL_RB1_OVERFLOW_VF3 = 192 +IH_PERF_SEL_RB1_OVERFLOW_VF4 = 193 +IH_PERF_SEL_RB1_OVERFLOW_VF5 = 194 +IH_PERF_SEL_RB1_OVERFLOW_VF6 = 195 +IH_PERF_SEL_RB1_OVERFLOW_VF7 = 196 +IH_PERF_SEL_RB1_OVERFLOW_VF8 = 197 +IH_PERF_SEL_RB1_OVERFLOW_VF9 = 198 +IH_PERF_SEL_RB1_OVERFLOW_VF10 = 199 +IH_PERF_SEL_RB1_OVERFLOW_VF11 = 200 +IH_PERF_SEL_RB1_OVERFLOW_VF12 = 201 +IH_PERF_SEL_RB1_OVERFLOW_VF13 = 202 +IH_PERF_SEL_RB1_OVERFLOW_VF14 = 203 +IH_PERF_SEL_RB1_OVERFLOW_VF15 = 204 +IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 205 +IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 206 +IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 207 +IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 208 +IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 209 +IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 210 +IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 211 +IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 212 +IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 213 +IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 214 +IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 215 +IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 216 +IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 217 +IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 218 +IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 219 +IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 220 +IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 221 +IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 222 +IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 223 +IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 224 +IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 225 +IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 226 +IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 227 +IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 228 +IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 229 +IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 230 +IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 231 +IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 232 +IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 233 +IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 234 +IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 235 +IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 236 +IH_PERF_SEL_RB2_FULL_VF0 = 237 +IH_PERF_SEL_RB2_FULL_VF1 = 238 +IH_PERF_SEL_RB2_FULL_VF2 = 239 +IH_PERF_SEL_RB2_FULL_VF3 = 240 +IH_PERF_SEL_RB2_FULL_VF4 = 241 +IH_PERF_SEL_RB2_FULL_VF5 = 242 +IH_PERF_SEL_RB2_FULL_VF6 = 243 +IH_PERF_SEL_RB2_FULL_VF7 = 244 +IH_PERF_SEL_RB2_FULL_VF8 = 245 +IH_PERF_SEL_RB2_FULL_VF9 = 246 +IH_PERF_SEL_RB2_FULL_VF10 = 247 +IH_PERF_SEL_RB2_FULL_VF11 = 248 +IH_PERF_SEL_RB2_FULL_VF12 = 249 +IH_PERF_SEL_RB2_FULL_VF13 = 250 +IH_PERF_SEL_RB2_FULL_VF14 = 251 +IH_PERF_SEL_RB2_FULL_VF15 = 252 +IH_PERF_SEL_RB2_OVERFLOW_VF0 = 253 +IH_PERF_SEL_RB2_OVERFLOW_VF1 = 254 +IH_PERF_SEL_RB2_OVERFLOW_VF2 = 255 +IH_PERF_SEL_RB2_OVERFLOW_VF3 = 256 +IH_PERF_SEL_RB2_OVERFLOW_VF4 = 257 +IH_PERF_SEL_RB2_OVERFLOW_VF5 = 258 +IH_PERF_SEL_RB2_OVERFLOW_VF6 = 259 +IH_PERF_SEL_RB2_OVERFLOW_VF7 = 260 +IH_PERF_SEL_RB2_OVERFLOW_VF8 = 261 +IH_PERF_SEL_RB2_OVERFLOW_VF9 = 262 +IH_PERF_SEL_RB2_OVERFLOW_VF10 = 263 +IH_PERF_SEL_RB2_OVERFLOW_VF11 = 264 +IH_PERF_SEL_RB2_OVERFLOW_VF12 = 265 +IH_PERF_SEL_RB2_OVERFLOW_VF13 = 266 +IH_PERF_SEL_RB2_OVERFLOW_VF14 = 267 +IH_PERF_SEL_RB2_OVERFLOW_VF15 = 268 +IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 269 +IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 270 +IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 271 +IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 272 +IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 273 +IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 274 +IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 275 +IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 276 +IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 277 +IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 278 +IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 279 +IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 280 +IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 281 +IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 282 +IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 283 +IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 284 +IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 285 +IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 286 +IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 287 +IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 288 +IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 289 +IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 290 +IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 291 +IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 292 +IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 293 +IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 294 +IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 295 +IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 296 +IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 297 +IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 298 +IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 299 +IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 300 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 301 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 302 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 303 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 304 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 305 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 306 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 307 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 308 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 309 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 310 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 311 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 312 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 313 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 314 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 315 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 316 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 317 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 318 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 319 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 320 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 321 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 322 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 323 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 324 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 325 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 326 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 327 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 328 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 329 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 330 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 331 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 332 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 333 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 334 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 335 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 336 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 337 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 338 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 339 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 340 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 341 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 342 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 343 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 344 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 345 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 346 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 347 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 348 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 349 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 350 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 351 +IH_PERF_SEL_RB0_LOAD_RPTR = 352 +IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 353 +IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 354 +IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 355 +IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 356 +IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 357 +IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 358 +IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 359 +IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 360 +IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 361 +IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 362 +IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 363 +IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 364 +IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 365 +IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 366 +IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 367 +IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 368 +IH_PERF_SEL_RB1_LOAD_RPTR = 369 +IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 370 +IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 371 +IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 372 +IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 373 +IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 374 +IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 375 +IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 376 +IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 377 +IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 378 +IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 379 +IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 380 +IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 381 +IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 382 +IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 383 +IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 384 +IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 385 +IH_PERF_SEL_RB2_LOAD_RPTR = 386 +IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 387 +IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 388 +IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 389 +IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 390 +IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 391 +IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 392 +IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 393 +IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 394 +IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 395 +IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 396 +IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 397 +IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 398 +IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 399 +IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 400 +IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 401 +IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 402 +IH_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'IH_RING_ID' +IH_RING_ID__enumvalues = { + 0: 'IH_RING_ID_INTERRUPT', + 1: 'IH_RING_ID_REQUEST', + 2: 'IH_RING_ID_TRANSLATION', + 3: 'IH_RING_ID_RESERVED', +} +IH_RING_ID_INTERRUPT = 0 +IH_RING_ID_REQUEST = 1 +IH_RING_ID_TRANSLATION = 2 +IH_RING_ID_RESERVED = 3 +IH_RING_ID = ctypes.c_uint32 # enum + +# values for enumeration 'IH_VF_RB_SELECT' +IH_VF_RB_SELECT__enumvalues = { + 0: 'IH_VF_RB_SELECT_CLIENT_FCN_ID', + 1: 'IH_VF_RB_SELECT_IH_FCN_ID', + 2: 'IH_VF_RB_SELECT_PF', + 3: 'IH_VF_RB_SELECT_RESERVED', +} +IH_VF_RB_SELECT_CLIENT_FCN_ID = 0 +IH_VF_RB_SELECT_IH_FCN_ID = 1 +IH_VF_RB_SELECT_PF = 2 +IH_VF_RB_SELECT_RESERVED = 3 +IH_VF_RB_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SEM_PERF_SEL' +SEM_PERF_SEL__enumvalues = { + 0: 'SEM_PERF_SEL_CYCLE', + 1: 'SEM_PERF_SEL_IDLE', + 2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', + 3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', + 4: 'SEM_PERF_SEL_SDMA2_REQ_SIGNAL', + 5: 'SEM_PERF_SEL_SDMA3_REQ_SIGNAL', + 6: 'SEM_PERF_SEL_UVD_REQ_SIGNAL', + 7: 'SEM_PERF_SEL_UVD1_REQ_SIGNAL', + 8: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', + 9: 'SEM_PERF_SEL_ACP_REQ_SIGNAL', + 10: 'SEM_PERF_SEL_ISP_REQ_SIGNAL', + 11: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', + 12: 'SEM_PERF_SEL_VP8_REQ_SIGNAL', + 13: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', + 14: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', + 15: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', + 16: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', + 17: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', + 18: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', + 19: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', + 20: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', + 21: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', + 22: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', + 23: 'SEM_PERF_SEL_SDMA0_REQ_WAIT', + 24: 'SEM_PERF_SEL_SDMA1_REQ_WAIT', + 25: 'SEM_PERF_SEL_SDMA2_REQ_WAIT', + 26: 'SEM_PERF_SEL_SDMA3_REQ_WAIT', + 27: 'SEM_PERF_SEL_UVD_REQ_WAIT', + 28: 'SEM_PERF_SEL_UVD1_REQ_WAIT', + 29: 'SEM_PERF_SEL_VCE0_REQ_WAIT', + 30: 'SEM_PERF_SEL_ACP_REQ_WAIT', + 31: 'SEM_PERF_SEL_ISP_REQ_WAIT', + 32: 'SEM_PERF_SEL_VCE1_REQ_WAIT', + 33: 'SEM_PERF_SEL_VP8_REQ_WAIT', + 34: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', + 35: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', + 36: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', + 37: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', + 38: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', + 39: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', + 40: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', + 41: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', + 42: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', + 43: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', + 44: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', + 45: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', + 46: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', + 47: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', + 48: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', + 49: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', + 50: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', + 51: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', + 52: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', + 53: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', + 54: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', + 55: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', + 56: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', + 57: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', + 58: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', + 59: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', + 60: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', + 61: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', + 62: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', + 63: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', + 64: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', + 65: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', + 66: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', + 67: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', + 68: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', + 69: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', + 70: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', + 71: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', + 72: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', + 73: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', + 74: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', + 75: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', + 76: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', + 77: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', + 78: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', + 79: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', + 80: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', + 81: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', + 82: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', + 83: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', + 84: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', + 85: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', + 86: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', + 87: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', + 88: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', + 89: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', + 90: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', + 91: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', + 92: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', + 93: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', + 94: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', + 95: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', + 96: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', + 97: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', + 98: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', + 99: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', + 100: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', + 101: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', + 102: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', + 103: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', + 104: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', + 105: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', + 106: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', + 107: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', + 108: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', + 109: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', + 110: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', + 111: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', + 112: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', + 113: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', + 114: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', + 115: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', + 116: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', + 117: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', + 118: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', + 119: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', + 120: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', + 121: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', + 122: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', + 123: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', + 124: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', + 125: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', + 126: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', + 127: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', + 128: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', + 129: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', + 130: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', + 131: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', + 132: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', + 133: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', + 134: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', + 135: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', + 136: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', + 137: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', + 138: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', + 139: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', + 140: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', + 141: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', + 142: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', + 143: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', + 144: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', + 145: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', + 146: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', + 147: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', + 148: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', + 149: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', + 150: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', + 151: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', + 152: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', + 153: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', + 154: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', + 155: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', + 156: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', + 157: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', + 158: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', + 159: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', + 160: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', + 161: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', + 162: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', + 163: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', + 164: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', + 165: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', + 166: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', + 167: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', + 168: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', + 169: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', + 170: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', + 171: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', + 172: 'SEM_PERF_SEL_MC_RD_REQ', + 173: 'SEM_PERF_SEL_MC_RD_RET', + 174: 'SEM_PERF_SEL_MC_WR_REQ', + 175: 'SEM_PERF_SEL_MC_WR_RET', + 176: 'SEM_PERF_SEL_ATC_REQ', + 177: 'SEM_PERF_SEL_ATC_RET', + 178: 'SEM_PERF_SEL_ATC_XNACK', + 179: 'SEM_PERF_SEL_ATC_INVALIDATION', + 180: 'SEM_PERF_SEL_ATC_VM_INVALIDATION', +} +SEM_PERF_SEL_CYCLE = 0 +SEM_PERF_SEL_IDLE = 1 +SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2 +SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3 +SEM_PERF_SEL_SDMA2_REQ_SIGNAL = 4 +SEM_PERF_SEL_SDMA3_REQ_SIGNAL = 5 +SEM_PERF_SEL_UVD_REQ_SIGNAL = 6 +SEM_PERF_SEL_UVD1_REQ_SIGNAL = 7 +SEM_PERF_SEL_VCE0_REQ_SIGNAL = 8 +SEM_PERF_SEL_ACP_REQ_SIGNAL = 9 +SEM_PERF_SEL_ISP_REQ_SIGNAL = 10 +SEM_PERF_SEL_VCE1_REQ_SIGNAL = 11 +SEM_PERF_SEL_VP8_REQ_SIGNAL = 12 +SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 13 +SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 14 +SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 15 +SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 16 +SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 17 +SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 18 +SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 19 +SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 20 +SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 21 +SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 22 +SEM_PERF_SEL_SDMA0_REQ_WAIT = 23 +SEM_PERF_SEL_SDMA1_REQ_WAIT = 24 +SEM_PERF_SEL_SDMA2_REQ_WAIT = 25 +SEM_PERF_SEL_SDMA3_REQ_WAIT = 26 +SEM_PERF_SEL_UVD_REQ_WAIT = 27 +SEM_PERF_SEL_UVD1_REQ_WAIT = 28 +SEM_PERF_SEL_VCE0_REQ_WAIT = 29 +SEM_PERF_SEL_ACP_REQ_WAIT = 30 +SEM_PERF_SEL_ISP_REQ_WAIT = 31 +SEM_PERF_SEL_VCE1_REQ_WAIT = 32 +SEM_PERF_SEL_VP8_REQ_WAIT = 33 +SEM_PERF_SEL_CPG_E0_REQ_WAIT = 34 +SEM_PERF_SEL_CPG_E1_REQ_WAIT = 35 +SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 36 +SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 37 +SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 38 +SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 39 +SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 40 +SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 41 +SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 42 +SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 43 +SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 44 +SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 45 +SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 46 +SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 47 +SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 48 +SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 49 +SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 50 +SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 51 +SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 52 +SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 53 +SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 54 +SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 55 +SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 56 +SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 57 +SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 58 +SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 59 +SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 60 +SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 61 +SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 62 +SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 63 +SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 64 +SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 65 +SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 66 +SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 67 +SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 68 +SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 69 +SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 70 +SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 71 +SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 72 +SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 73 +SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 74 +SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 75 +SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 76 +SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 77 +SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 78 +SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 79 +SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 80 +SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 81 +SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 82 +SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 83 +SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 84 +SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 85 +SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 86 +SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 87 +SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 88 +SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 89 +SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 90 +SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 91 +SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 92 +SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 93 +SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 94 +SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 95 +SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 96 +SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 97 +SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 98 +SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 99 +SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 100 +SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 101 +SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 102 +SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 103 +SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 104 +SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 105 +SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 106 +SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 107 +SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 108 +SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 109 +SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 110 +SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 111 +SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 112 +SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 113 +SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 114 +SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 115 +SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 116 +SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 117 +SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 118 +SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 119 +SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 120 +SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 121 +SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 122 +SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 123 +SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 124 +SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 125 +SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 126 +SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 127 +SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 128 +SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 129 +SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 130 +SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 131 +SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 132 +SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 133 +SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 134 +SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 135 +SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 136 +SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 137 +SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 138 +SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 139 +SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 140 +SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 141 +SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 142 +SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 143 +SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 144 +SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 145 +SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 146 +SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 147 +SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 148 +SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 149 +SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 150 +SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 151 +SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 152 +SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 153 +SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 154 +SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 155 +SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 156 +SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 157 +SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 158 +SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 159 +SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 160 +SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 161 +SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 162 +SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 163 +SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 164 +SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 165 +SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 166 +SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 167 +SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 168 +SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 169 +SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 170 +SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 171 +SEM_PERF_SEL_MC_RD_REQ = 172 +SEM_PERF_SEL_MC_RD_RET = 173 +SEM_PERF_SEL_MC_WR_REQ = 174 +SEM_PERF_SEL_MC_WR_RET = 175 +SEM_PERF_SEL_ATC_REQ = 176 +SEM_PERF_SEL_ATC_RET = 177 +SEM_PERF_SEL_ATC_XNACK = 178 +SEM_PERF_SEL_ATC_INVALIDATION = 179 +SEM_PERF_SEL_ATC_VM_INVALIDATION = 180 +SEM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'LSDMA_PERF_SEL' +LSDMA_PERF_SEL__enumvalues = { + 0: 'LSDMA_PERF_SEL_CYCLE', + 1: 'LSDMA_PERF_SEL_IDLE', + 2: 'LSDMA_PERF_SEL_REG_IDLE', + 3: 'LSDMA_PERF_SEL_RB_EMPTY', + 4: 'LSDMA_PERF_SEL_RB_FULL', + 5: 'LSDMA_PERF_SEL_RB_WPTR_WRAP', + 6: 'LSDMA_PERF_SEL_RB_RPTR_WRAP', + 7: 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', + 8: 'LSDMA_PERF_SEL_RB_RPTR_WB', + 9: 'LSDMA_PERF_SEL_RB_CMD_IDLE', + 10: 'LSDMA_PERF_SEL_RB_CMD_FULL', + 11: 'LSDMA_PERF_SEL_IB_CMD_IDLE', + 12: 'LSDMA_PERF_SEL_IB_CMD_FULL', + 13: 'LSDMA_PERF_SEL_EX_IDLE', + 14: 'LSDMA_PERF_SEL_SRBM_REG_SEND', + 15: 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'LSDMA_PERF_SEL_MC_WR_IDLE', + 17: 'LSDMA_PERF_SEL_MC_WR_COUNT', + 18: 'LSDMA_PERF_SEL_MC_RD_IDLE', + 19: 'LSDMA_PERF_SEL_MC_RD_COUNT', + 20: 'LSDMA_PERF_SEL_MC_RD_RET_STALL', + 21: 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 24: 'LSDMA_PERF_SEL_SEM_IDLE', + 25: 'LSDMA_PERF_SEL_SEM_REQ_STALL', + 26: 'LSDMA_PERF_SEL_SEM_REQ_COUNT', + 27: 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 28: 'LSDMA_PERF_SEL_SEM_RESP_FAIL', + 29: 'LSDMA_PERF_SEL_SEM_RESP_PASS', + 30: 'LSDMA_PERF_SEL_INT_IDLE', + 31: 'LSDMA_PERF_SEL_INT_REQ_STALL', + 32: 'LSDMA_PERF_SEL_INT_REQ_COUNT', + 33: 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', + 34: 'LSDMA_PERF_SEL_INT_RESP_RETRY', + 35: 'LSDMA_PERF_SEL_NUM_PACKET', + 37: 'LSDMA_PERF_SEL_CE_WREQ_IDLE', + 38: 'LSDMA_PERF_SEL_CE_WR_IDLE', + 39: 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', + 40: 'LSDMA_PERF_SEL_CE_RREQ_IDLE', + 41: 'LSDMA_PERF_SEL_CE_OUT_IDLE', + 42: 'LSDMA_PERF_SEL_CE_IN_IDLE', + 43: 'LSDMA_PERF_SEL_CE_DST_IDLE', + 46: 'LSDMA_PERF_SEL_CE_AFIFO_FULL', + 49: 'LSDMA_PERF_SEL_CE_INFO_FULL', + 50: 'LSDMA_PERF_SEL_CE_INFO1_FULL', + 51: 'LSDMA_PERF_SEL_CE_RD_STALL', + 52: 'LSDMA_PERF_SEL_CE_WR_STALL', + 53: 'LSDMA_PERF_SEL_GFX_SELECT', + 54: 'LSDMA_PERF_SEL_RLC0_SELECT', + 55: 'LSDMA_PERF_SEL_RLC1_SELECT', + 56: 'LSDMA_PERF_SEL_PAGE_SELECT', + 57: 'LSDMA_PERF_SEL_CTX_CHANGE', + 58: 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', + 59: 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 60: 'LSDMA_PERF_SEL_DOORBELL', + 61: 'LSDMA_PERF_SEL_RD_BA_RTR', + 62: 'LSDMA_PERF_SEL_WR_BA_RTR', + 63: 'LSDMA_PERF_SEL_F32_L1_WR_VLD', + 64: 'LSDMA_PERF_SEL_CE_L1_WR_VLD', + 65: 'LSDMA_PERF_SEL_CE_L1_STALL', + 66: 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', + 67: 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', + 68: 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', + 69: 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', + 70: 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', + 71: 'LSDMA_PERF_SEL_ATCL2_RET_ACK', + 72: 'LSDMA_PERF_SEL_ATCL2_FREE', + 73: 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', + 74: 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', + 75: 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', + 76: 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', + 77: 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', + 78: 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', + 79: 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', + 80: 'LSDMA_PERF_SEL_L1_WRL2_IDLE', + 81: 'LSDMA_PERF_SEL_L1_RDL2_IDLE', + 82: 'LSDMA_PERF_SEL_L1_WRMC_IDLE', + 83: 'LSDMA_PERF_SEL_L1_RDMC_IDLE', + 84: 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', + 85: 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', + 86: 'LSDMA_PERF_SEL_L1_WR_INV_EN', + 87: 'LSDMA_PERF_SEL_L1_RD_INV_EN', + 88: 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', + 89: 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', + 90: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', + 91: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', + 92: 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', + 93: 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', + 94: 'LSDMA_PERF_SEL_L1_INV_MIDDLE', + 95: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', + 96: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', + 97: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', + 98: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', + 99: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', + 100: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', + 101: 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', + 102: 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', + 103: 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', + 104: 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', + 105: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', + 106: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', + 107: 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', + 108: 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', + 109: 'LSDMA_PERF_SEL_CMD_OP_MATCH', + 110: 'LSDMA_PERF_SEL_CMD_OP_START', + 111: 'LSDMA_PERF_SEL_CMD_OP_END', + 112: 'LSDMA_PERF_SEL_CE_BUSY', + 113: 'LSDMA_PERF_SEL_CE_BUSY_START', + 114: 'LSDMA_PERF_SEL_CE_BUSY_END', + 115: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 116: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 117: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 118: 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', + 119: 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', + 120: 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', + 121: 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', + 122: 'LSDMA_PERF_SEL_DRAM_ECC', + 123: 'LSDMA_PERF_SEL_NACK_GEN_ERR', +} +LSDMA_PERF_SEL_CYCLE = 0 +LSDMA_PERF_SEL_IDLE = 1 +LSDMA_PERF_SEL_REG_IDLE = 2 +LSDMA_PERF_SEL_RB_EMPTY = 3 +LSDMA_PERF_SEL_RB_FULL = 4 +LSDMA_PERF_SEL_RB_WPTR_WRAP = 5 +LSDMA_PERF_SEL_RB_RPTR_WRAP = 6 +LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 +LSDMA_PERF_SEL_RB_RPTR_WB = 8 +LSDMA_PERF_SEL_RB_CMD_IDLE = 9 +LSDMA_PERF_SEL_RB_CMD_FULL = 10 +LSDMA_PERF_SEL_IB_CMD_IDLE = 11 +LSDMA_PERF_SEL_IB_CMD_FULL = 12 +LSDMA_PERF_SEL_EX_IDLE = 13 +LSDMA_PERF_SEL_SRBM_REG_SEND = 14 +LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +LSDMA_PERF_SEL_MC_WR_IDLE = 16 +LSDMA_PERF_SEL_MC_WR_COUNT = 17 +LSDMA_PERF_SEL_MC_RD_IDLE = 18 +LSDMA_PERF_SEL_MC_RD_COUNT = 19 +LSDMA_PERF_SEL_MC_RD_RET_STALL = 20 +LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 +LSDMA_PERF_SEL_SEM_IDLE = 24 +LSDMA_PERF_SEL_SEM_REQ_STALL = 25 +LSDMA_PERF_SEL_SEM_REQ_COUNT = 26 +LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 +LSDMA_PERF_SEL_SEM_RESP_FAIL = 28 +LSDMA_PERF_SEL_SEM_RESP_PASS = 29 +LSDMA_PERF_SEL_INT_IDLE = 30 +LSDMA_PERF_SEL_INT_REQ_STALL = 31 +LSDMA_PERF_SEL_INT_REQ_COUNT = 32 +LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 +LSDMA_PERF_SEL_INT_RESP_RETRY = 34 +LSDMA_PERF_SEL_NUM_PACKET = 35 +LSDMA_PERF_SEL_CE_WREQ_IDLE = 37 +LSDMA_PERF_SEL_CE_WR_IDLE = 38 +LSDMA_PERF_SEL_CE_SPLIT_IDLE = 39 +LSDMA_PERF_SEL_CE_RREQ_IDLE = 40 +LSDMA_PERF_SEL_CE_OUT_IDLE = 41 +LSDMA_PERF_SEL_CE_IN_IDLE = 42 +LSDMA_PERF_SEL_CE_DST_IDLE = 43 +LSDMA_PERF_SEL_CE_AFIFO_FULL = 46 +LSDMA_PERF_SEL_CE_INFO_FULL = 49 +LSDMA_PERF_SEL_CE_INFO1_FULL = 50 +LSDMA_PERF_SEL_CE_RD_STALL = 51 +LSDMA_PERF_SEL_CE_WR_STALL = 52 +LSDMA_PERF_SEL_GFX_SELECT = 53 +LSDMA_PERF_SEL_RLC0_SELECT = 54 +LSDMA_PERF_SEL_RLC1_SELECT = 55 +LSDMA_PERF_SEL_PAGE_SELECT = 56 +LSDMA_PERF_SEL_CTX_CHANGE = 57 +LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 +LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 +LSDMA_PERF_SEL_DOORBELL = 60 +LSDMA_PERF_SEL_RD_BA_RTR = 61 +LSDMA_PERF_SEL_WR_BA_RTR = 62 +LSDMA_PERF_SEL_F32_L1_WR_VLD = 63 +LSDMA_PERF_SEL_CE_L1_WR_VLD = 64 +LSDMA_PERF_SEL_CE_L1_STALL = 65 +LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66 +LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67 +LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68 +LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69 +LSDMA_PERF_SEL_ATCL2_RET_XNACK = 70 +LSDMA_PERF_SEL_ATCL2_RET_ACK = 71 +LSDMA_PERF_SEL_ATCL2_FREE = 72 +LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 73 +LSDMA_PERF_SEL_DMA_L1_WR_SEND = 74 +LSDMA_PERF_SEL_DMA_L1_RD_SEND = 75 +LSDMA_PERF_SEL_DMA_MC_WR_SEND = 76 +LSDMA_PERF_SEL_DMA_MC_RD_SEND = 77 +LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78 +LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79 +LSDMA_PERF_SEL_L1_WRL2_IDLE = 80 +LSDMA_PERF_SEL_L1_RDL2_IDLE = 81 +LSDMA_PERF_SEL_L1_WRMC_IDLE = 82 +LSDMA_PERF_SEL_L1_RDMC_IDLE = 83 +LSDMA_PERF_SEL_L1_WR_INV_IDLE = 84 +LSDMA_PERF_SEL_L1_RD_INV_IDLE = 85 +LSDMA_PERF_SEL_L1_WR_INV_EN = 86 +LSDMA_PERF_SEL_L1_RD_INV_EN = 87 +LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88 +LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89 +LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90 +LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91 +LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92 +LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93 +LSDMA_PERF_SEL_L1_INV_MIDDLE = 94 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 95 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 96 +LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 97 +LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 98 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 99 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 100 +LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 101 +LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 102 +LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 103 +LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 104 +LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 105 +LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 106 +LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 107 +LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 108 +LSDMA_PERF_SEL_CMD_OP_MATCH = 109 +LSDMA_PERF_SEL_CMD_OP_START = 110 +LSDMA_PERF_SEL_CMD_OP_END = 111 +LSDMA_PERF_SEL_CE_BUSY = 112 +LSDMA_PERF_SEL_CE_BUSY_START = 113 +LSDMA_PERF_SEL_CE_BUSY_END = 114 +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 115 +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 116 +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 117 +LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 118 +LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 119 +LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 120 +LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 121 +LSDMA_PERF_SEL_DRAM_ECC = 122 +LSDMA_PERF_SEL_NACK_GEN_ERR = 123 +LSDMA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'EFC_SURFACE_PIXEL_FORMAT' +EFC_SURFACE_PIXEL_FORMAT__enumvalues = { + 1: 'EFC_ARGB1555', + 2: 'EFC_RGBA5551', + 3: 'EFC_RGB565', + 4: 'EFC_BGR565', + 5: 'EFC_ARGB4444', + 6: 'EFC_RGBA4444', + 8: 'EFC_ARGB8888', + 9: 'EFC_RGBA8888', + 10: 'EFC_ARGB2101010', + 11: 'EFC_RGBA1010102', + 12: 'EFC_AYCrCb8888', + 13: 'EFC_YCrCbA8888', + 14: 'EFC_ACrYCb8888', + 15: 'EFC_CrYCbA8888', + 16: 'EFC_ARGB16161616_10MSB', + 17: 'EFC_RGBA16161616_10MSB', + 18: 'EFC_ARGB16161616_10LSB', + 19: 'EFC_RGBA16161616_10LSB', + 20: 'EFC_ARGB16161616_12MSB', + 21: 'EFC_RGBA16161616_12MSB', + 22: 'EFC_ARGB16161616_12LSB', + 23: 'EFC_RGBA16161616_12LSB', + 24: 'EFC_ARGB16161616_FLOAT', + 25: 'EFC_RGBA16161616_FLOAT', + 26: 'EFC_ARGB16161616_UNORM', + 27: 'EFC_RGBA16161616_UNORM', + 28: 'EFC_ARGB16161616_SNORM', + 29: 'EFC_RGBA16161616_SNORM', + 32: 'EFC_AYCrCb16161616_10MSB', + 33: 'EFC_AYCrCb16161616_10LSB', + 34: 'EFC_YCrCbA16161616_10MSB', + 35: 'EFC_YCrCbA16161616_10LSB', + 36: 'EFC_ACrYCb16161616_10MSB', + 37: 'EFC_ACrYCb16161616_10LSB', + 38: 'EFC_CrYCbA16161616_10MSB', + 39: 'EFC_CrYCbA16161616_10LSB', + 40: 'EFC_AYCrCb16161616_12MSB', + 41: 'EFC_AYCrCb16161616_12LSB', + 42: 'EFC_YCrCbA16161616_12MSB', + 43: 'EFC_YCrCbA16161616_12LSB', + 44: 'EFC_ACrYCb16161616_12MSB', + 45: 'EFC_ACrYCb16161616_12LSB', + 46: 'EFC_CrYCbA16161616_12MSB', + 47: 'EFC_CrYCbA16161616_12LSB', + 64: 'EFC_Y8_CrCb88_420_PLANAR', + 65: 'EFC_Y8_CbCr88_420_PLANAR', + 66: 'EFC_Y10_CrCb1010_420_PLANAR', + 67: 'EFC_Y10_CbCr1010_420_PLANAR', + 68: 'EFC_Y12_CrCb1212_420_PLANAR', + 69: 'EFC_Y12_CbCr1212_420_PLANAR', + 72: 'EFC_YCrYCb8888_422_PACKED', + 73: 'EFC_YCbYCr8888_422_PACKED', + 74: 'EFC_CrYCbY8888_422_PACKED', + 75: 'EFC_CbYCrY8888_422_PACKED', + 76: 'EFC_YCrYCb10101010_422_PACKED', + 77: 'EFC_YCbYCr10101010_422_PACKED', + 78: 'EFC_CrYCbY10101010_422_PACKED', + 79: 'EFC_CbYCrY10101010_422_PACKED', + 80: 'EFC_YCrYCb12121212_422_PACKED', + 81: 'EFC_YCbYCr12121212_422_PACKED', + 82: 'EFC_CrYCbY12121212_422_PACKED', + 83: 'EFC_CbYCrY12121212_422_PACKED', + 112: 'EFC_RGB111110_FIX', + 113: 'EFC_BGR101111_FIX', + 114: 'EFC_ACrYCb2101010', + 115: 'EFC_CrYCbA1010102', + 118: 'EFC_RGB111110_FLOAT', + 119: 'EFC_BGR101111_FLOAT', + 120: 'EFC_MONO_8', + 121: 'EFC_MONO_10MSB', + 122: 'EFC_MONO_10LSB', + 123: 'EFC_MONO_12MSB', + 124: 'EFC_MONO_12LSB', + 125: 'EFC_MONO_16', +} +EFC_ARGB1555 = 1 +EFC_RGBA5551 = 2 +EFC_RGB565 = 3 +EFC_BGR565 = 4 +EFC_ARGB4444 = 5 +EFC_RGBA4444 = 6 +EFC_ARGB8888 = 8 +EFC_RGBA8888 = 9 +EFC_ARGB2101010 = 10 +EFC_RGBA1010102 = 11 +EFC_AYCrCb8888 = 12 +EFC_YCrCbA8888 = 13 +EFC_ACrYCb8888 = 14 +EFC_CrYCbA8888 = 15 +EFC_ARGB16161616_10MSB = 16 +EFC_RGBA16161616_10MSB = 17 +EFC_ARGB16161616_10LSB = 18 +EFC_RGBA16161616_10LSB = 19 +EFC_ARGB16161616_12MSB = 20 +EFC_RGBA16161616_12MSB = 21 +EFC_ARGB16161616_12LSB = 22 +EFC_RGBA16161616_12LSB = 23 +EFC_ARGB16161616_FLOAT = 24 +EFC_RGBA16161616_FLOAT = 25 +EFC_ARGB16161616_UNORM = 26 +EFC_RGBA16161616_UNORM = 27 +EFC_ARGB16161616_SNORM = 28 +EFC_RGBA16161616_SNORM = 29 +EFC_AYCrCb16161616_10MSB = 32 +EFC_AYCrCb16161616_10LSB = 33 +EFC_YCrCbA16161616_10MSB = 34 +EFC_YCrCbA16161616_10LSB = 35 +EFC_ACrYCb16161616_10MSB = 36 +EFC_ACrYCb16161616_10LSB = 37 +EFC_CrYCbA16161616_10MSB = 38 +EFC_CrYCbA16161616_10LSB = 39 +EFC_AYCrCb16161616_12MSB = 40 +EFC_AYCrCb16161616_12LSB = 41 +EFC_YCrCbA16161616_12MSB = 42 +EFC_YCrCbA16161616_12LSB = 43 +EFC_ACrYCb16161616_12MSB = 44 +EFC_ACrYCb16161616_12LSB = 45 +EFC_CrYCbA16161616_12MSB = 46 +EFC_CrYCbA16161616_12LSB = 47 +EFC_Y8_CrCb88_420_PLANAR = 64 +EFC_Y8_CbCr88_420_PLANAR = 65 +EFC_Y10_CrCb1010_420_PLANAR = 66 +EFC_Y10_CbCr1010_420_PLANAR = 67 +EFC_Y12_CrCb1212_420_PLANAR = 68 +EFC_Y12_CbCr1212_420_PLANAR = 69 +EFC_YCrYCb8888_422_PACKED = 72 +EFC_YCbYCr8888_422_PACKED = 73 +EFC_CrYCbY8888_422_PACKED = 74 +EFC_CbYCrY8888_422_PACKED = 75 +EFC_YCrYCb10101010_422_PACKED = 76 +EFC_YCbYCr10101010_422_PACKED = 77 +EFC_CrYCbY10101010_422_PACKED = 78 +EFC_CbYCrY10101010_422_PACKED = 79 +EFC_YCrYCb12121212_422_PACKED = 80 +EFC_YCbYCr12121212_422_PACKED = 81 +EFC_CrYCbY12121212_422_PACKED = 82 +EFC_CbYCrY12121212_422_PACKED = 83 +EFC_RGB111110_FIX = 112 +EFC_BGR101111_FIX = 113 +EFC_ACrYCb2101010 = 114 +EFC_CrYCbA1010102 = 115 +EFC_RGB111110_FLOAT = 118 +EFC_BGR101111_FLOAT = 119 +EFC_MONO_8 = 120 +EFC_MONO_10MSB = 121 +EFC_MONO_10LSB = 122 +EFC_MONO_12MSB = 123 +EFC_MONO_12LSB = 124 +EFC_MONO_16 = 125 +EFC_SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum +__all__ = \ + ['ACCEPT_UNSOLICITED_RESPONSE_ENABLE', + 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ACP_TYPE_DVD_AUDIO', + 'ACP_TYPE_GENERIC_AUDIO', 'ACP_TYPE_ICE60958_AUDIO', + 'ACP_TYPE_SUPER_AUDIO_CD', 'ACrYCb16161616_10LSB', + 'ACrYCb16161616_10MSB', 'ACrYCb16161616_12LSB', + 'ACrYCb16161616_12MSB', 'ACrYCb2101010', 'ACrYCb8888', + 'ADDR_GEN_ONE', 'ADDR_GEN_TWO', 'ADDR_GEN_ZERO', 'ADDR_RESERVED', + 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', + 'AFMT_ACP_SOURCE_FROM_AZALIA', 'AFMT_ACP_TYPE', + 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', + 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', + 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', + 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', + 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', + 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', + 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', + 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', + 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', + 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', + 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', + 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', + 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', + 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', + 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', + 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', + 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS', + 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', + 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', + 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', + 'AFMT_INTERRUPT_STATUS_CHG_MASK', 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', + 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', + 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', + 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', 'AFMT_MEM_NO_FORCE_REQUEST', + 'AFMT_MEM_PWR_DIS_CTRL', 'AFMT_MEM_PWR_FORCE_CTRL', + 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', + 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', + 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE', 'ALLOW_SR_ON_TRANS_REQ', + 'ALLOW_SR_ON_TRANS_REQ_DISABLE', 'ALLOW_SR_ON_TRANS_REQ_ENABLE', + 'ALL_USE_R', 'ALPHA_DATA_ONTO_ALPHA_PORT', + 'ALPHA_DATA_ONTO_CB_B_PORT', 'ALPHA_DATA_ONTO_CR_R_PORT', + 'ALPHA_DATA_ONTO_Y_G_PORT', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'AMCLOCK_ENABLE', + 'APG_ACP_OVERRIDE', 'APG_ACP_SOURCE_NO_OVERRIDE', + 'APG_ACP_TYPE_DVD_AUDIO', 'APG_ACP_TYPE_GENERIC_AUDIO', + 'APG_ACP_TYPE_ICE60958_AUDIO', 'APG_ACP_TYPE_SUPER_AUDIO_CD', + 'APG_AUDIO_CRC_CH0_SIG', 'APG_AUDIO_CRC_CH1_SIG', + 'APG_AUDIO_CRC_CH2_SIG', 'APG_AUDIO_CRC_CH3_SIG', + 'APG_AUDIO_CRC_CH4_SIG', 'APG_AUDIO_CRC_CH5_SIG', + 'APG_AUDIO_CRC_CH6_SIG', 'APG_AUDIO_CRC_CH7_SIG', + 'APG_AUDIO_CRC_CONTINUOUS', 'APG_AUDIO_CRC_CONTROL_CH_SEL', + 'APG_AUDIO_CRC_CONTROL_CONT', 'APG_AUDIO_CRC_ONESHOT', + 'APG_AUDIO_CRC_RESERVED_10', 'APG_AUDIO_CRC_RESERVED_11', + 'APG_AUDIO_CRC_RESERVED_12', 'APG_AUDIO_CRC_RESERVED_13', + 'APG_AUDIO_CRC_RESERVED_14', 'APG_AUDIO_CRC_RESERVED_15', + 'APG_AUDIO_CRC_RESERVED_8', 'APG_AUDIO_CRC_RESERVED_9', + 'APG_DBG_ACP_TYPE', 'APG_DBG_AUDIO_DTO_BASE', + 'APG_DBG_AUDIO_DTO_DIV', 'APG_DBG_AUDIO_DTO_MULTI', + 'APG_DBG_MUX_SEL', 'APG_DEBUG_AUDIO_MODE', + 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', + 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE', + 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', + 'APG_FUNCTIONAL_MODE', 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', + 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', + 'APG_MEM_DISABLE_MEM_PWR_CTRL', 'APG_MEM_ENABLE_MEM_PWR_CTRL', + 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', + 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', 'APG_MEM_NO_FORCE_REQUEST', + 'APG_MEM_POWER_STATE', 'APG_MEM_POWER_STATE_DS', + 'APG_MEM_POWER_STATE_LS', 'APG_MEM_POWER_STATE_ON', + 'APG_MEM_POWER_STATE_SD', 'APG_MEM_PWR_DIS_CTRL', + 'APG_MEM_PWR_FORCE_CTRL', 'APG_PACKET_CONTROL_ACP_SOURCE', + 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE', 'APG_RAMP_CONTROL_SIGN', + 'APG_RAMP_SIGNED', 'APG_RAMP_UNSIGNED', 'ARGB1555', + 'ARGB16161616_10LSB', 'ARGB16161616_10MSB', 'ARGB16161616_12LSB', + 'ARGB16161616_12MSB', 'ARGB16161616_FLOAT', 'ARGB16161616_SNORM', + 'ARGB16161616_UNORM', 'ARGB2101010', 'ARGB4444', 'ARGB8888', + 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT', + 'AUTOCAL_MODE_AUTOCENTER', 'AUTOCAL_MODE_AUTOREPLICATE', + 'AUTOCAL_MODE_AUTOSCALE', 'AUTOCAL_MODE_OFF', + 'AYCrCb16161616_10LSB', 'AYCrCb16161616_10MSB', + 'AYCrCb16161616_12LSB', 'AYCrCb16161616_12MSB', 'AYCrCb8888', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', + 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', + 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', + 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', + 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', + 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', + 'AZ_RIRB_WRITE_POINTER_DO_RESET', + 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', + 'AZ_STATE_CHANGE_STATUS', + 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'BASE_RATE_44P1KHZ', + 'BASE_RATE_48KHZ', 'BGR101111_FIX', 'BGR101111_FLOAT', 'BGR565', + 'BIGK_FRAGMENT_SIZE', 'BINNER_BREAK_BATCH', 'BINNER_DROP', + 'BINNER_PIPELINE', 'BINNER_PIPELINE_BREAK', 'BINNING_ALLOWED', + 'BIN_CONF_OVERRIDE_CHECK', 'BIN_MAP_MODE_NONE', + 'BIN_MAP_MODE_POPS', 'BIN_MAP_MODE_RTA_INDEX', + 'BIN_SIZE_128_PIXELS', 'BIN_SIZE_256_PIXELS', + 'BIN_SIZE_32_PIXELS', 'BIN_SIZE_512_PIXELS', 'BIN_SIZE_64_PIXELS', + 'BITS_31_0', 'BITS_32_1', 'BITS_33_2', 'BITS_34_3', 'BITS_35_4', + 'BITS_36_5', 'BITS_37_6', 'BITS_38_7', 'BLEND_CONSTANT_ALPHA', + 'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', + 'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', + 'BLEND_ONE_MINUS_CONSTANT_ALPHA', + 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', + 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', + 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', + 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', + 'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLOCK_CONTEXT_DONE', 'BLUE_LUT', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM_DS', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM_LS', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM_ON', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM_SD', 'BOTTOM_OF_PIPE_TS', + 'BREAK_BATCH', 'BYPASS', 'BYPASS_EN', 'BYPASS_GAMUT', + 'BYPASS_POST_CSC', 'BinEventCntl', 'BinMapMode', 'BinSizeExtend', + 'BinningMode', 'BlendOp', 'BlendOpt', 'CACHE_BYPASS', + 'CACHE_FLUSH', 'CACHE_FLUSH_AND_INV_EVENT', + 'CACHE_FLUSH_AND_INV_TS_EVENT', 'CACHE_FLUSH_TS', 'CACHE_LRU_RD', + 'CACHE_LRU_WR', 'CACHE_NOA', 'CACHE_NOA_WR', 'CACHE_STREAM', + 'CACHE_STREAM_RD', 'CBMode', 'CBPerfClearFilterSel', + 'CBPerfOpFilterSel', 'CBPerfSel', 'CBRamList', + 'CB_B_DATA_ONTO_ALPHA_PORT', 'CB_B_DATA_ONTO_CB_B_PORT', + 'CB_B_DATA_ONTO_CR_R_PORT', 'CB_B_DATA_ONTO_Y_G_PORT', + 'CB_DCC_DECOMPRESS', 'CB_DCG_BACKEND_RDLAT_FIFO', + 'CB_DCG_CCC_CAS_COLOR_PTR', 'CB_DCG_CCC_CAS_FRAG_PTR', + 'CB_DCG_CCC_CAS_KEYID', 'CB_DCG_CCC_CAS_SURF_PARAM', + 'CB_DCG_CCC_CAS_TAG_ARRAY', 'CB_DCG_COLOR_STORE', + 'CB_DCG_COLOR_STORE_DIRTY_BYTE', 'CB_DCG_DCC_CACHE', + 'CB_DCG_DCC_DIRTY_BITS', 'CB_DCG_FMASK_CACHE_STORE', + 'CB_DCG_FRONTEND_RDLAT_FIFO', 'CB_DCG_OUTPUT_FIFO', + 'CB_DCG_QBLOCK_ALLOC', 'CB_DCG_QUAD_PTR_FIFO', + 'CB_DCG_READ_SKID_FIFO', 'CB_DCG_SRC_FIFO', 'CB_DISABLE', + 'CB_ELIMINATE_FAST_CLEAR', 'CB_NORMAL', + 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', + 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', + 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', + 'CB_PERF_SEL_BLEND_CLOCK_EN', + 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', + 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', + 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', + 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY', + 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB', + 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY', + 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB', + 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY', + 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB', + 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY', + 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB', + 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_CC_CACHE_FLUSH', + 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', + 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', + 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN', + 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT', + 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN', + 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT', + 'CB_PERF_SEL_CC_MC_READ_REQUEST', + 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', + 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CC_TAG_HIT', + 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', + 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', + 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', + 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', + 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', + 'CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_DCC_CACHE_FLUSH', + 'CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_DCC_CACHE_PERF_HIT', + 'CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_DCC_CACHE_SECTOR_MISS', + 'CB_PERF_SEL_DCC_CACHE_STALL', + 'CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_DCC_CACHE_TAG_MISS', + 'CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', + 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE', + 'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', + 'CB_PERF_SEL_FILTER_DRAWN_PIXEL', 'CB_PERF_SEL_FILTER_DRAWN_QUAD', + 'CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT', + 'CB_PERF_SEL_FILTER_DRAWN_TILE', + 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', + 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', + 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', + 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', + 'CB_PERF_SEL_GRBM_CLOCK_EN', 'CB_PERF_SEL_MEMARB_CLOCK_EN', + 'CB_PERF_SEL_NACK_CC_READ', 'CB_PERF_SEL_NACK_CC_WRITE', + 'CB_PERF_SEL_NONE', 'CB_PERF_SEL_PERFMON_CLOCK_EN', + 'CB_PERF_SEL_RESERVED_118', 'CB_PERF_SEL_RESERVED_119', + 'CB_PERF_SEL_RESERVED_120', 'CB_PERF_SEL_RESERVED_121', + 'CB_PERF_SEL_RESERVED_122', 'CB_PERF_SEL_RESERVED_123', + 'CB_PERF_SEL_RESERVED_124', 'CB_PERF_SEL_RESERVED_125', + 'CB_PERF_SEL_RESERVED_126', 'CB_PERF_SEL_RESERVED_127', + 'CB_PERF_SEL_RESERVED_128', 'CB_PERF_SEL_RESERVED_129', + 'CB_PERF_SEL_RESERVED_130', 'CB_PERF_SEL_RESERVED_131', + 'CB_PERF_SEL_RESERVED_132', 'CB_PERF_SEL_RESERVED_133', + 'CB_PERF_SEL_RESERVED_134', 'CB_PERF_SEL_RESERVED_135', + 'CB_PERF_SEL_RESERVED_136', 'CB_PERF_SEL_RESERVED_137', + 'CB_PERF_SEL_RESERVED_138', 'CB_PERF_SEL_RESERVED_139', + 'CB_PERF_SEL_RESERVED_140', 'CB_PERF_SEL_RESERVED_141', + 'CB_PERF_SEL_RESERVED_142', 'CB_PERF_SEL_RESERVED_143', + 'CB_PERF_SEL_RESERVED_144', 'CB_PERF_SEL_RESERVED_145', + 'CB_PERF_SEL_RESERVED_146', 'CB_PERF_SEL_RESERVED_147', + 'CB_PERF_SEL_RESERVED_148', 'CB_PERF_SEL_RESERVED_149', + 'CB_PERF_SEL_RESERVED_165', 'CB_PERF_SEL_RESERVED_166', + 'CB_PERF_SEL_RESERVED_167', 'CB_PERF_SEL_RESERVED_168', + 'CB_PERF_SEL_RESERVED_169', 'CB_PERF_SEL_RESERVED_170', + 'CB_PERF_SEL_RESERVED_171', 'CB_PERF_SEL_RESERVED_172', + 'CB_PERF_SEL_RESERVED_173', 'CB_PERF_SEL_RESERVED_174', + 'CB_PERF_SEL_RESERVED_175', 'CB_PERF_SEL_RESERVED_176', + 'CB_PERF_SEL_RESERVED_177', 'CB_PERF_SEL_RESERVED_178', + 'CB_PERF_SEL_RESERVED_179', 'CB_PERF_SEL_RESERVED_180', + 'CB_PERF_SEL_RESERVED_181', 'CB_PERF_SEL_RESERVED_182', + 'CB_PERF_SEL_RESERVED_183', 'CB_PERF_SEL_RESERVED_184', + 'CB_PERF_SEL_RESERVED_185', 'CB_PERF_SEL_RESERVED_186', + 'CB_PERF_SEL_RESERVED_187', 'CB_PERF_SEL_RESERVED_188', + 'CB_PERF_SEL_RESERVED_189', 'CB_PERF_SEL_RESERVED_190', + 'CB_PERF_SEL_RESERVED_191', 'CB_PERF_SEL_RESERVED_192', + 'CB_PERF_SEL_RESERVED_193', 'CB_PERF_SEL_RESERVED_194', + 'CB_PERF_SEL_RESERVED_195', 'CB_PERF_SEL_RESERVED_196', + 'CB_PERF_SEL_RESERVED_197', 'CB_PERF_SEL_RESERVED_198', + 'CB_PERF_SEL_RESERVED_199', 'CB_PERF_SEL_RESERVED_205', + 'CB_PERF_SEL_RESERVED_206', 'CB_PERF_SEL_RESERVED_207', + 'CB_PERF_SEL_RESERVED_208', 'CB_PERF_SEL_RESERVED_209', + 'CB_PERF_SEL_RESERVED_21', 'CB_PERF_SEL_RESERVED_210', + 'CB_PERF_SEL_RESERVED_211', 'CB_PERF_SEL_RESERVED_212', + 'CB_PERF_SEL_RESERVED_213', 'CB_PERF_SEL_RESERVED_214', + 'CB_PERF_SEL_RESERVED_215', 'CB_PERF_SEL_RESERVED_216', + 'CB_PERF_SEL_RESERVED_217', 'CB_PERF_SEL_RESERVED_218', + 'CB_PERF_SEL_RESERVED_219', 'CB_PERF_SEL_RESERVED_22', + 'CB_PERF_SEL_RESERVED_220', 'CB_PERF_SEL_RESERVED_221', + 'CB_PERF_SEL_RESERVED_222', 'CB_PERF_SEL_RESERVED_223', + 'CB_PERF_SEL_RESERVED_224', 'CB_PERF_SEL_RESERVED_225', + 'CB_PERF_SEL_RESERVED_226', 'CB_PERF_SEL_RESERVED_227', + 'CB_PERF_SEL_RESERVED_228', 'CB_PERF_SEL_RESERVED_229', + 'CB_PERF_SEL_RESERVED_23', 'CB_PERF_SEL_RESERVED_230', + 'CB_PERF_SEL_RESERVED_231', 'CB_PERF_SEL_RESERVED_232', + 'CB_PERF_SEL_RESERVED_233', 'CB_PERF_SEL_RESERVED_234', + 'CB_PERF_SEL_RESERVED_235', 'CB_PERF_SEL_RESERVED_236', + 'CB_PERF_SEL_RESERVED_237', 'CB_PERF_SEL_RESERVED_238', + 'CB_PERF_SEL_RESERVED_239', 'CB_PERF_SEL_RESERVED_24', + 'CB_PERF_SEL_RESERVED_240', 'CB_PERF_SEL_RESERVED_241', + 'CB_PERF_SEL_RESERVED_242', 'CB_PERF_SEL_RESERVED_243', + 'CB_PERF_SEL_RESERVED_244', 'CB_PERF_SEL_RESERVED_245', + 'CB_PERF_SEL_RESERVED_246', 'CB_PERF_SEL_RESERVED_247', + 'CB_PERF_SEL_RESERVED_248', 'CB_PERF_SEL_RESERVED_249', + 'CB_PERF_SEL_RESERVED_25', 'CB_PERF_SEL_RESERVED_259', + 'CB_PERF_SEL_RESERVED_26', 'CB_PERF_SEL_RESERVED_260', + 'CB_PERF_SEL_RESERVED_261', 'CB_PERF_SEL_RESERVED_262', + 'CB_PERF_SEL_RESERVED_263', 'CB_PERF_SEL_RESERVED_264', + 'CB_PERF_SEL_RESERVED_265', 'CB_PERF_SEL_RESERVED_266', + 'CB_PERF_SEL_RESERVED_267', 'CB_PERF_SEL_RESERVED_268', + 'CB_PERF_SEL_RESERVED_269', 'CB_PERF_SEL_RESERVED_27', + 'CB_PERF_SEL_RESERVED_270', 'CB_PERF_SEL_RESERVED_271', + 'CB_PERF_SEL_RESERVED_272', 'CB_PERF_SEL_RESERVED_273', + 'CB_PERF_SEL_RESERVED_274', 'CB_PERF_SEL_RESERVED_275', + 'CB_PERF_SEL_RESERVED_276', 'CB_PERF_SEL_RESERVED_277', + 'CB_PERF_SEL_RESERVED_278', 'CB_PERF_SEL_RESERVED_279', + 'CB_PERF_SEL_RESERVED_28', 'CB_PERF_SEL_RESERVED_280', + 'CB_PERF_SEL_RESERVED_281', 'CB_PERF_SEL_RESERVED_282', + 'CB_PERF_SEL_RESERVED_283', 'CB_PERF_SEL_RESERVED_284', + 'CB_PERF_SEL_RESERVED_285', 'CB_PERF_SEL_RESERVED_286', + 'CB_PERF_SEL_RESERVED_287', 'CB_PERF_SEL_RESERVED_288', + 'CB_PERF_SEL_RESERVED_289', 'CB_PERF_SEL_RESERVED_29', + 'CB_PERF_SEL_RESERVED_290', 'CB_PERF_SEL_RESERVED_291', + 'CB_PERF_SEL_RESERVED_292', 'CB_PERF_SEL_RESERVED_293', + 'CB_PERF_SEL_RESERVED_294', 'CB_PERF_SEL_RESERVED_295', + 'CB_PERF_SEL_RESERVED_296', 'CB_PERF_SEL_RESERVED_297', + 'CB_PERF_SEL_RESERVED_298', 'CB_PERF_SEL_RESERVED_299', + 'CB_PERF_SEL_RESERVED_303', 'CB_PERF_SEL_RESERVED_304', + 'CB_PERF_SEL_RESERVED_305', 'CB_PERF_SEL_RESERVED_306', + 'CB_PERF_SEL_RESERVED_307', 'CB_PERF_SEL_RESERVED_308', + 'CB_PERF_SEL_RESERVED_309', 'CB_PERF_SEL_RESERVED_310', + 'CB_PERF_SEL_RESERVED_311', 'CB_PERF_SEL_RESERVED_312', + 'CB_PERF_SEL_RESERVED_313', 'CB_PERF_SEL_RESERVED_314', + 'CB_PERF_SEL_RESERVED_315', 'CB_PERF_SEL_RESERVED_316', + 'CB_PERF_SEL_RESERVED_317', 'CB_PERF_SEL_RESERVED_318', + 'CB_PERF_SEL_RESERVED_319', 'CB_PERF_SEL_RESERVED_320', + 'CB_PERF_SEL_RESERVED_321', 'CB_PERF_SEL_RESERVED_322', + 'CB_PERF_SEL_RESERVED_323', 'CB_PERF_SEL_RESERVED_324', + 'CB_PERF_SEL_RESERVED_325', 'CB_PERF_SEL_RESERVED_326', + 'CB_PERF_SEL_RESERVED_327', 'CB_PERF_SEL_RESERVED_328', + 'CB_PERF_SEL_RESERVED_329', 'CB_PERF_SEL_RESERVED_330', + 'CB_PERF_SEL_RESERVED_331', 'CB_PERF_SEL_RESERVED_332', + 'CB_PERF_SEL_RESERVED_333', 'CB_PERF_SEL_RESERVED_334', + 'CB_PERF_SEL_RESERVED_335', 'CB_PERF_SEL_RESERVED_336', + 'CB_PERF_SEL_RESERVED_337', 'CB_PERF_SEL_RESERVED_338', + 'CB_PERF_SEL_RESERVED_339', 'CB_PERF_SEL_RESERVED_340', + 'CB_PERF_SEL_RESERVED_341', 'CB_PERF_SEL_RESERVED_342', + 'CB_PERF_SEL_RESERVED_343', 'CB_PERF_SEL_RESERVED_344', + 'CB_PERF_SEL_RESERVED_345', 'CB_PERF_SEL_RESERVED_346', + 'CB_PERF_SEL_RESERVED_347', 'CB_PERF_SEL_RESERVED_348', + 'CB_PERF_SEL_RESERVED_349', 'CB_PERF_SEL_RESERVED_350', + 'CB_PERF_SEL_RESERVED_351', 'CB_PERF_SEL_RESERVED_352', + 'CB_PERF_SEL_RESERVED_353', 'CB_PERF_SEL_RESERVED_354', + 'CB_PERF_SEL_RESERVED_355', 'CB_PERF_SEL_RESERVED_356', + 'CB_PERF_SEL_RESERVED_357', 'CB_PERF_SEL_RESERVED_358', + 'CB_PERF_SEL_RESERVED_359', 'CB_PERF_SEL_RESERVED_360', + 'CB_PERF_SEL_RESERVED_361', 'CB_PERF_SEL_RESERVED_362', + 'CB_PERF_SEL_RESERVED_363', 'CB_PERF_SEL_RESERVED_364', + 'CB_PERF_SEL_RESERVED_365', 'CB_PERF_SEL_RESERVED_366', + 'CB_PERF_SEL_RESERVED_367', 'CB_PERF_SEL_RESERVED_368', + 'CB_PERF_SEL_RESERVED_369', 'CB_PERF_SEL_RESERVED_370', + 'CB_PERF_SEL_RESERVED_371', 'CB_PERF_SEL_RESERVED_372', + 'CB_PERF_SEL_RESERVED_373', 'CB_PERF_SEL_RESERVED_374', + 'CB_PERF_SEL_RESERVED_375', 'CB_PERF_SEL_RESERVED_376', + 'CB_PERF_SEL_RESERVED_377', 'CB_PERF_SEL_RESERVED_378', + 'CB_PERF_SEL_RESERVED_379', 'CB_PERF_SEL_RESERVED_38', + 'CB_PERF_SEL_RESERVED_380', 'CB_PERF_SEL_RESERVED_381', + 'CB_PERF_SEL_RESERVED_382', 'CB_PERF_SEL_RESERVED_383', + 'CB_PERF_SEL_RESERVED_384', 'CB_PERF_SEL_RESERVED_385', + 'CB_PERF_SEL_RESERVED_386', 'CB_PERF_SEL_RESERVED_387', + 'CB_PERF_SEL_RESERVED_388', 'CB_PERF_SEL_RESERVED_389', + 'CB_PERF_SEL_RESERVED_39', 'CB_PERF_SEL_RESERVED_390', + 'CB_PERF_SEL_RESERVED_391', 'CB_PERF_SEL_RESERVED_392', + 'CB_PERF_SEL_RESERVED_393', 'CB_PERF_SEL_RESERVED_394', + 'CB_PERF_SEL_RESERVED_395', 'CB_PERF_SEL_RESERVED_396', + 'CB_PERF_SEL_RESERVED_397', 'CB_PERF_SEL_RESERVED_398', + 'CB_PERF_SEL_RESERVED_399', 'CB_PERF_SEL_RESERVED_40', + 'CB_PERF_SEL_RESERVED_400', 'CB_PERF_SEL_RESERVED_401', + 'CB_PERF_SEL_RESERVED_402', 'CB_PERF_SEL_RESERVED_403', + 'CB_PERF_SEL_RESERVED_404', 'CB_PERF_SEL_RESERVED_405', + 'CB_PERF_SEL_RESERVED_406', 'CB_PERF_SEL_RESERVED_407', + 'CB_PERF_SEL_RESERVED_408', 'CB_PERF_SEL_RESERVED_409', + 'CB_PERF_SEL_RESERVED_41', 'CB_PERF_SEL_RESERVED_410', + 'CB_PERF_SEL_RESERVED_411', 'CB_PERF_SEL_RESERVED_412', + 'CB_PERF_SEL_RESERVED_413', 'CB_PERF_SEL_RESERVED_414', + 'CB_PERF_SEL_RESERVED_415', 'CB_PERF_SEL_RESERVED_416', + 'CB_PERF_SEL_RESERVED_417', 'CB_PERF_SEL_RESERVED_418', + 'CB_PERF_SEL_RESERVED_419', 'CB_PERF_SEL_RESERVED_42', + 'CB_PERF_SEL_RESERVED_420', 'CB_PERF_SEL_RESERVED_421', + 'CB_PERF_SEL_RESERVED_422', 'CB_PERF_SEL_RESERVED_423', + 'CB_PERF_SEL_RESERVED_424', 'CB_PERF_SEL_RESERVED_425', + 'CB_PERF_SEL_RESERVED_426', 'CB_PERF_SEL_RESERVED_427', + 'CB_PERF_SEL_RESERVED_428', 'CB_PERF_SEL_RESERVED_429', + 'CB_PERF_SEL_RESERVED_43', 'CB_PERF_SEL_RESERVED_430', + 'CB_PERF_SEL_RESERVED_431', 'CB_PERF_SEL_RESERVED_432', + 'CB_PERF_SEL_RESERVED_433', 'CB_PERF_SEL_RESERVED_434', + 'CB_PERF_SEL_RESERVED_435', 'CB_PERF_SEL_RESERVED_436', + 'CB_PERF_SEL_RESERVED_437', 'CB_PERF_SEL_RESERVED_438', + 'CB_PERF_SEL_RESERVED_439', 'CB_PERF_SEL_RESERVED_44', + 'CB_PERF_SEL_RESERVED_440', 'CB_PERF_SEL_RESERVED_441', + 'CB_PERF_SEL_RESERVED_442', 'CB_PERF_SEL_RESERVED_443', + 'CB_PERF_SEL_RESERVED_444', 'CB_PERF_SEL_RESERVED_445', + 'CB_PERF_SEL_RESERVED_446', 'CB_PERF_SEL_RESERVED_447', + 'CB_PERF_SEL_RESERVED_448', 'CB_PERF_SEL_RESERVED_449', + 'CB_PERF_SEL_RESERVED_45', 'CB_PERF_SEL_RESERVED_450', + 'CB_PERF_SEL_RESERVED_451', 'CB_PERF_SEL_RESERVED_452', + 'CB_PERF_SEL_RESERVED_453', 'CB_PERF_SEL_RESERVED_454', + 'CB_PERF_SEL_RESERVED_455', 'CB_PERF_SEL_RESERVED_456', + 'CB_PERF_SEL_RESERVED_457', 'CB_PERF_SEL_RESERVED_458', + 'CB_PERF_SEL_RESERVED_459', 'CB_PERF_SEL_RESERVED_46', + 'CB_PERF_SEL_RESERVED_460', 'CB_PERF_SEL_RESERVED_461', + 'CB_PERF_SEL_RESERVED_462', 'CB_PERF_SEL_RESERVED_463', + 'CB_PERF_SEL_RESERVED_464', 'CB_PERF_SEL_RESERVED_465', + 'CB_PERF_SEL_RESERVED_47', 'CB_PERF_SEL_RESERVED_48', + 'CB_PERF_SEL_RESERVED_49', 'CB_PERF_SEL_RESERVED_65', + 'CB_PERF_SEL_RESERVED_66', 'CB_PERF_SEL_RESERVED_67', + 'CB_PERF_SEL_RESERVED_68', 'CB_PERF_SEL_RESERVED_69', + 'CB_PERF_SEL_RESERVED_70', 'CB_PERF_SEL_RESERVED_71', + 'CB_PERF_SEL_RESERVED_72', 'CB_PERF_SEL_RESERVED_73', + 'CB_PERF_SEL_RESERVED_74', 'CB_PERF_SEL_RESERVED_75', + 'CB_PERF_SEL_RESERVED_76', 'CB_PERF_SEL_RESERVED_77', + 'CB_PERF_SEL_RESERVED_78', 'CB_PERF_SEL_RESERVED_79', + 'CB_PERF_SEL_RESERVED_80', 'CB_PERF_SEL_RESERVED_81', + 'CB_PERF_SEL_RESERVED_82', 'CB_PERF_SEL_RESERVED_83', + 'CB_PERF_SEL_RESERVED_84', 'CB_PERF_SEL_RESERVED_85', + 'CB_PERF_SEL_RESERVED_86', 'CB_PERF_SEL_RESERVED_87', + 'CB_PERF_SEL_RESERVED_88', 'CB_PERF_SEL_RESERVED_89', + 'CB_PERF_SEL_RESERVED_90', 'CB_PERF_SEL_RESERVED_91', + 'CB_PERF_SEL_RESERVED_92', 'CB_PERF_SEL_RESERVED_93', + 'CB_PERF_SEL_RESERVED_94', 'CB_PERF_SEL_RESERVED_95', + 'CB_PERF_SEL_RESERVED_96', 'CB_PERF_SEL_RESERVED_97', + 'CB_PERF_SEL_RESERVED_98', 'CB_PERF_SEL_RESERVED_99', + 'CB_PERF_SEL_STATIC_CLOCK_EN', 'CB_RESERVED', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', + 'CHA_PERF_SEL', 'CHA_PERF_SEL_ARB_REQUESTS', 'CHA_PERF_SEL_BUSY', + 'CHA_PERF_SEL_CYCLE', 'CHA_PERF_SEL_IO_32B_WDS_CHC0', + 'CHA_PERF_SEL_IO_32B_WDS_CHC1', 'CHA_PERF_SEL_IO_32B_WDS_CHC2', + 'CHA_PERF_SEL_IO_32B_WDS_CHC3', 'CHA_PERF_SEL_IO_32B_WDS_CHC4', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', 'CHA_PERF_SEL_REQUEST_CHC0', + 'CHA_PERF_SEL_REQUEST_CHC1', 'CHA_PERF_SEL_REQUEST_CHC2', + 'CHA_PERF_SEL_REQUEST_CHC3', 'CHA_PERF_SEL_REQUEST_CHC4', + 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', 'CHA_PERF_SEL_STALL_CHC0', + 'CHA_PERF_SEL_STALL_CHC1', 'CHA_PERF_SEL_STALL_CHC2', + 'CHA_PERF_SEL_STALL_CHC3', 'CHA_PERF_SEL_STALL_CHC4', + 'CHA_PERF_SEL_STALL_CHC5', 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', 'CHCG_PERF_SEL', + 'CHCG_PERF_SEL_ARB_RET_LEVEL', 'CHCG_PERF_SEL_BUSY', + 'CHCG_PERF_SEL_CYCLE', 'CHCG_PERF_SEL_GL2_REQ_READ_LATENCY', + 'CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHCG_PERF_SEL_REQ', + 'CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 'CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHCG_PERF_SEL_REQ_CLIENT0', + 'CHCG_PERF_SEL_REQ_CLIENT1', 'CHCG_PERF_SEL_REQ_CLIENT10', + 'CHCG_PERF_SEL_REQ_CLIENT11', 'CHCG_PERF_SEL_REQ_CLIENT12', + 'CHCG_PERF_SEL_REQ_CLIENT13', 'CHCG_PERF_SEL_REQ_CLIENT14', + 'CHCG_PERF_SEL_REQ_CLIENT15', 'CHCG_PERF_SEL_REQ_CLIENT16', + 'CHCG_PERF_SEL_REQ_CLIENT17', 'CHCG_PERF_SEL_REQ_CLIENT18', + 'CHCG_PERF_SEL_REQ_CLIENT19', 'CHCG_PERF_SEL_REQ_CLIENT2', + 'CHCG_PERF_SEL_REQ_CLIENT20', 'CHCG_PERF_SEL_REQ_CLIENT21', + 'CHCG_PERF_SEL_REQ_CLIENT22', 'CHCG_PERF_SEL_REQ_CLIENT23', + 'CHCG_PERF_SEL_REQ_CLIENT3', 'CHCG_PERF_SEL_REQ_CLIENT4', + 'CHCG_PERF_SEL_REQ_CLIENT5', 'CHCG_PERF_SEL_REQ_CLIENT6', + 'CHCG_PERF_SEL_REQ_CLIENT7', 'CHCG_PERF_SEL_REQ_CLIENT8', + 'CHCG_PERF_SEL_REQ_CLIENT9', 'CHCG_PERF_SEL_REQ_NOP_ACK', + 'CHCG_PERF_SEL_REQ_NOP_RTN0', 'CHCG_PERF_SEL_REQ_READ', + 'CHCG_PERF_SEL_REQ_READ_128B', 'CHCG_PERF_SEL_REQ_READ_32B', + 'CHCG_PERF_SEL_REQ_READ_64B', 'CHCG_PERF_SEL_REQ_WRITE', + 'CHCG_PERF_SEL_REQ_WRITE_32B', 'CHCG_PERF_SEL_REQ_WRITE_64B', + 'CHCG_PERF_SEL_STALL_BUFFER_FULL', 'CHCG_PERF_SEL_STALL_GUS_GL1', + 'CHCG_PERF_SEL_STARVE', 'CHC_PERF_SEL', + 'CHC_PERF_SEL_ARB_RET_LEVEL', 'CHC_PERF_SEL_BUSY', + 'CHC_PERF_SEL_CYCLE', 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', + 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHC_PERF_SEL_REQ', + 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHC_PERF_SEL_REQ_CLIENT0', + 'CHC_PERF_SEL_REQ_CLIENT1', 'CHC_PERF_SEL_REQ_CLIENT10', + 'CHC_PERF_SEL_REQ_CLIENT11', 'CHC_PERF_SEL_REQ_CLIENT12', + 'CHC_PERF_SEL_REQ_CLIENT13', 'CHC_PERF_SEL_REQ_CLIENT14', + 'CHC_PERF_SEL_REQ_CLIENT15', 'CHC_PERF_SEL_REQ_CLIENT16', + 'CHC_PERF_SEL_REQ_CLIENT17', 'CHC_PERF_SEL_REQ_CLIENT18', + 'CHC_PERF_SEL_REQ_CLIENT19', 'CHC_PERF_SEL_REQ_CLIENT2', + 'CHC_PERF_SEL_REQ_CLIENT20', 'CHC_PERF_SEL_REQ_CLIENT21', + 'CHC_PERF_SEL_REQ_CLIENT22', 'CHC_PERF_SEL_REQ_CLIENT23', + 'CHC_PERF_SEL_REQ_CLIENT3', 'CHC_PERF_SEL_REQ_CLIENT4', + 'CHC_PERF_SEL_REQ_CLIENT5', 'CHC_PERF_SEL_REQ_CLIENT6', + 'CHC_PERF_SEL_REQ_CLIENT7', 'CHC_PERF_SEL_REQ_CLIENT8', + 'CHC_PERF_SEL_REQ_CLIENT9', 'CHC_PERF_SEL_REQ_NOP_ACK', + 'CHC_PERF_SEL_REQ_NOP_RTN0', 'CHC_PERF_SEL_REQ_READ', + 'CHC_PERF_SEL_REQ_READ_128B', 'CHC_PERF_SEL_REQ_READ_32B', + 'CHC_PERF_SEL_REQ_READ_64B', 'CHC_PERF_SEL_REQ_WRITE', + 'CHC_PERF_SEL_REQ_WRITE_32B', 'CHC_PERF_SEL_REQ_WRITE_64B', + 'CHC_PERF_SEL_STALL_BUFFER_FULL', 'CHC_PERF_SEL_STALL_GL2_GL1', + 'CHC_PERF_SEL_STARVE', 'CHUNK_SIZE', 'CHUNK_SIZE_16KB', + 'CHUNK_SIZE_1KB', 'CHUNK_SIZE_2KB', 'CHUNK_SIZE_32KB', + 'CHUNK_SIZE_4KB', 'CHUNK_SIZE_64KB', 'CHUNK_SIZE_8KB', + 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', 'CLKGATE_SM_MODE', + 'CLOCK_BRANCH_SOFT_RESET', 'CLOCK_BRANCH_SOFT_RESET_FORCE', + 'CLOCK_BRANCH_SOFT_RESET_NOOP', 'CLOCK_GATING_DISABLE', + 'CLOCK_GATING_DISABLED', 'CLOCK_GATING_DISABLED_IN_DCO', + 'CLOCK_GATING_DISABLE_ENUM', 'CLOCK_GATING_DISABLE_ENUM_DISABLED', + 'CLOCK_GATING_DISABLE_ENUM_ENABLED', 'CLOCK_GATING_EN', + 'CLOCK_GATING_ENABLE', 'CLOCK_GATING_ENABLED', + 'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_CLR00_F0', 'CMASK_CLR00_F1', + 'CMASK_CLR00_F2', 'CMASK_CLR00_FX', 'CMASK_CLR01_F0', + 'CMASK_CLR01_F1', 'CMASK_CLR01_F2', 'CMASK_CLR01_FX', + 'CMASK_CLR10_F0', 'CMASK_CLR10_F1', 'CMASK_CLR10_F2', + 'CMASK_CLR10_FX', 'CMASK_CLR11_F0', 'CMASK_CLR11_F1', + 'CMASK_CLR11_F2', 'CMASK_CLR11_FX', 'CMC_3DLUT_17CUBE', + 'CMC_3DLUT_30BIT', 'CMC_3DLUT_30BIT_ENUM', 'CMC_3DLUT_36BIT', + 'CMC_3DLUT_9CUBE', 'CMC_3DLUT_RAM_SEL', 'CMC_3DLUT_SIZE_ENUM', + 'CMC_LUT_2CFG_MEMORY_A', 'CMC_LUT_2CFG_MEMORY_B', + 'CMC_LUT_2CFG_NO_MEMORY', 'CMC_LUT_2_CONFIG_ENUM', + 'CMC_LUT_2_MODE_BYPASS', 'CMC_LUT_2_MODE_ENUM', + 'CMC_LUT_2_MODE_RAMA_LUT', 'CMC_LUT_2_MODE_RAMB_LUT', + 'CMC_LUT_NUM_SEG', 'CMC_LUT_RAM_SEL', 'CMC_RAM0_ACCESS', + 'CMC_RAM1_ACCESS', 'CMC_RAM2_ACCESS', 'CMC_RAM3_ACCESS', + 'CMC_RAMA_ACCESS', 'CMC_RAMB_ACCESS', 'CMC_SEGMENTS_1', + 'CMC_SEGMENTS_128', 'CMC_SEGMENTS_16', 'CMC_SEGMENTS_2', + 'CMC_SEGMENTS_32', 'CMC_SEGMENTS_4', 'CMC_SEGMENTS_64', + 'CMC_SEGMENTS_8', 'CMPTO', 'CM_BYPASS', 'CM_COEF_FORMAT_ENUM', + 'CM_DATA_SIGNED', 'CM_DISABLE', 'CM_EN', 'CM_ENABLE', + 'CM_GAMMA_LUT_MODE_ENUM', 'CM_GAMMA_LUT_PWL_DISABLE_ENUM', + 'CM_GAMMA_LUT_SEL_ENUM', 'CM_GAMUT_REMAP_MODE_ENUM', + 'CM_LUT_2_CONFIG_ENUM', 'CM_LUT_2_MODE_ENUM', + 'CM_LUT_4_CONFIG_ENUM', 'CM_LUT_4_MODE_ENUM', + 'CM_LUT_CONFIG_MODE', 'CM_LUT_NUM_SEG', 'CM_LUT_RAM_SEL', + 'CM_LUT_READ_COLOR_SEL', 'CM_LUT_READ_DBG', 'CM_NOT_PENDING', + 'CM_PENDING', 'CM_POST_CSC_MODE_ENUM', 'CM_WRITE_BASE_ONLY', + 'CM_YES_PENDING', 'CNVC_BYPASS', 'CNVC_BYPASS_DISABLE', + 'CNVC_BYPASS_EN', 'CNVC_COEF_FORMAT_ENUM', 'CNVC_DIS', 'CNVC_EN', + 'CNVC_ENABLE', 'CNVC_FIX_S2_13', 'CNVC_FIX_S3_12', + 'CNVC_NOT_PENDING', 'CNVC_PENDING', 'CNVC_ROUND', 'CNVC_TRUNCATE', + 'CNVC_YES_PENDING', 'COEF_POST_CSC', 'COEF_POST_CSC_B', + 'COEF_RAM_SELECT_BACK', 'COEF_RAM_SELECT_CURRENT', + 'COEF_RAM_SELECT_RD', 'COLOR_24BIT_1BIT_AND', + 'COLOR_24BIT_8BIT_ALPHA_PREMULT', + 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', 'COLOR_64BIT_FP_PREMULT', + 'COLOR_64BIT_FP_UNPREMULT', 'COLOR_KEYER_MODE', + 'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', + 'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST', 'COMPAT_LEVEL', + 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END', + 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START', + 'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START', + 'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', + 'CORB_READ_POINTER_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', + 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_LATENCY_STATS_SEL', + 'CPC_LATENCY_STATS_SEL_INVAL_LAST', + 'CPC_LATENCY_STATS_SEL_INVAL_MAX', + 'CPC_LATENCY_STATS_SEL_INVAL_MIN', + 'CPC_LATENCY_STATS_SEL_XACK_LAST', + 'CPC_LATENCY_STATS_SEL_XACK_MAX', + 'CPC_LATENCY_STATS_SEL_XACK_MIN', + 'CPC_LATENCY_STATS_SEL_XNACK_LAST', + 'CPC_LATENCY_STATS_SEL_XNACK_MAX', + 'CPC_LATENCY_STATS_SEL_XNACK_MIN', 'CPC_PERFCOUNT_SEL', + 'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_CPC_GCRIU_BUSY', + 'CPC_PERF_SEL_CPC_GCRIU_IDLE', 'CPC_PERF_SEL_CPC_GCRIU_STALL', + 'CPC_PERF_SEL_CPC_STAT_BUSY', 'CPC_PERF_SEL_CPC_STAT_IDLE', + 'CPC_PERF_SEL_CPC_STAT_STALL', 'CPC_PERF_SEL_CPC_TCIU_BUSY', + 'CPC_PERF_SEL_CPC_TCIU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', + 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', + 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', + 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', + 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', + 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', + 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', 'CPC_PERF_SEL_MES_THREAD0', + 'CPC_PERF_SEL_MES_THREAD1', + 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', + 'CPF_LATENCY_STATS_SEL', 'CPF_LATENCY_STATS_SEL_INVAL_LAST', + 'CPF_LATENCY_STATS_SEL_INVAL_MAX', + 'CPF_LATENCY_STATS_SEL_INVAL_MIN', + 'CPF_LATENCY_STATS_SEL_READ_LAST', + 'CPF_LATENCY_STATS_SEL_READ_MAX', + 'CPF_LATENCY_STATS_SEL_READ_MIN', + 'CPF_LATENCY_STATS_SEL_XACK_LAST', + 'CPF_LATENCY_STATS_SEL_XACK_MAX', + 'CPF_LATENCY_STATS_SEL_XACK_MIN', + 'CPF_LATENCY_STATS_SEL_XNACK_LAST', + 'CPF_LATENCY_STATS_SEL_XNACK_MAX', + 'CPF_LATENCY_STATS_SEL_XNACK_MIN', 'CPF_PERFCOUNTWINDOW_SEL', + 'CPF_PERFCOUNT_SEL', 'CPF_PERFWINDOW_SEL_CSF', + 'CPF_PERFWINDOW_SEL_HQD1', 'CPF_PERFWINDOW_SEL_HQD2', + 'CPF_PERFWINDOW_SEL_RDMA', 'CPF_PERFWINDOW_SEL_RWPP', + 'CPF_PERF_SEL_ALWAYS_COUNT', + 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', + 'CPF_PERF_SEL_CPF_GCRIU_BUSY', 'CPF_PERF_SEL_CPF_GCRIU_IDLE', + 'CPF_PERF_SEL_CPF_GCRIU_STALL', 'CPF_PERF_SEL_CPF_STAT_BUSY', + 'CPF_PERF_SEL_CPF_STAT_IDLE', 'CPF_PERF_SEL_CPF_STAT_STALL', + 'CPF_PERF_SEL_CPF_TCIU_BUSY', 'CPF_PERF_SEL_CPF_TCIU_IDLE', + 'CPF_PERF_SEL_CPF_TCIU_STALL', 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', + 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', + 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', + 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', + 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', + 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', + 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', + 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', + 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', + 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 'CPF_SCRATCH_REG_ATOMIC_ADD', 'CPF_SCRATCH_REG_ATOMIC_AND', + 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', 'CPF_SCRATCH_REG_ATOMIC_MAX', + 'CPF_SCRATCH_REG_ATOMIC_MIN', 'CPF_SCRATCH_REG_ATOMIC_NOT', + 'CPF_SCRATCH_REG_ATOMIC_OP', 'CPF_SCRATCH_REG_ATOMIC_OR', + 'CPF_SCRATCH_REG_ATOMIC_SUB', 'CPF_TAG_RAM', + 'CPG_LATENCY_STATS_SEL', 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', + 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', + 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', + 'CPG_LATENCY_STATS_SEL_INVAL_LAST', + 'CPG_LATENCY_STATS_SEL_INVAL_MAX', + 'CPG_LATENCY_STATS_SEL_INVAL_MIN', + 'CPG_LATENCY_STATS_SEL_READ_LAST', + 'CPG_LATENCY_STATS_SEL_READ_MAX', + 'CPG_LATENCY_STATS_SEL_READ_MIN', + 'CPG_LATENCY_STATS_SEL_WRITE_LAST', + 'CPG_LATENCY_STATS_SEL_WRITE_MAX', + 'CPG_LATENCY_STATS_SEL_WRITE_MIN', + 'CPG_LATENCY_STATS_SEL_XACK_LAST', + 'CPG_LATENCY_STATS_SEL_XACK_MAX', + 'CPG_LATENCY_STATS_SEL_XACK_MIN', + 'CPG_LATENCY_STATS_SEL_XNACK_LAST', + 'CPG_LATENCY_STATS_SEL_XNACK_MAX', + 'CPG_LATENCY_STATS_SEL_XNACK_MIN', 'CPG_PERFCOUNTWINDOW_SEL', + 'CPG_PERFCOUNT_SEL', 'CPG_PERFWINDOW_SEL_APPEND', + 'CPG_PERFWINDOW_SEL_CE', 'CPG_PERFWINDOW_SEL_CEDMA', + 'CPG_PERFWINDOW_SEL_CPC_IC', 'CPG_PERFWINDOW_SEL_CPG_IC', + 'CPG_PERFWINDOW_SEL_DDID', 'CPG_PERFWINDOW_SEL_DFY', + 'CPG_PERFWINDOW_SEL_DMA', 'CPG_PERFWINDOW_SEL_ME', + 'CPG_PERFWINDOW_SEL_MEC1', 'CPG_PERFWINDOW_SEL_MEC2', + 'CPG_PERFWINDOW_SEL_MEMRD', 'CPG_PERFWINDOW_SEL_MEMWR', + 'CPG_PERFWINDOW_SEL_MES', 'CPG_PERFWINDOW_SEL_PFP', + 'CPG_PERFWINDOW_SEL_PQ1', 'CPG_PERFWINDOW_SEL_PQ2', + 'CPG_PERFWINDOW_SEL_PQ3', 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', + 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', 'CPG_PERFWINDOW_SEL_QURD', + 'CPG_PERFWINDOW_SEL_QU_EOP', 'CPG_PERFWINDOW_SEL_QU_PIPE', + 'CPG_PERFWINDOW_SEL_QU_STRM', 'CPG_PERFWINDOW_SEL_RB', + 'CPG_PERFWINDOW_SEL_RESERVED1', 'CPG_PERFWINDOW_SEL_RESERVED2', + 'CPG_PERFWINDOW_SEL_SHADOW', 'CPG_PERFWINDOW_SEL_SR', + 'CPG_PERFWINDOW_SEL_VGT0', 'CPG_PERFWINDOW_SEL_VGT1', + 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', 'CPG_PERF_SEL_ALWAYS_COUNT', + 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', + 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CPG_GCRIU_BUSY', + 'CPG_PERF_SEL_CPG_GCRIU_IDLE', 'CPG_PERF_SEL_CPG_GCRIU_STALL', + 'CPG_PERF_SEL_CPG_STAT_BUSY', 'CPG_PERF_SEL_CPG_STAT_IDLE', + 'CPG_PERF_SEL_CPG_STAT_STALL', 'CPG_PERF_SEL_CPG_TCIU_BUSY', + 'CPG_PERF_SEL_CPG_TCIU_IDLE', 'CPG_PERF_SEL_CPG_TCIU_STALL', + 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', + 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', + 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', + 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_DMA_BUSY', + 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', + 'CPG_PERF_SEL_DMA_STALLED', 'CPG_PERF_SEL_DMA_STARVED', + 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', + 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', 'CPG_PERF_SEL_ME_PARSER_BUSY', + 'CPG_PERF_SEL_ME_PWS_STALLED0', 'CPG_PERF_SEL_ME_PWS_STALLED1', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', + 'CPG_PERF_SEL_PFP_PWS_STALLED0', 'CPG_PERF_SEL_PFP_PWS_STALLED1', + 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', + 'CP_ALPHA_TAG_RAM_SEL', 'CP_DDID_CNTL_MODE', 'CP_DDID_CNTL_SIZE', + 'CP_DDID_CNTL_VMID_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE', + 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', + 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', + 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', + 'CRC_CUR_0', 'CRC_CUR_1', 'CRC_CUR_SEL', 'CRC_INTERLACE_0', + 'CRC_INTERLACE_1', 'CRC_INTERLACE_2', 'CRC_INTERLACE_3', + 'CRC_INTERLACE_SEL', 'CRC_IN_CUR_0', 'CRC_IN_CUR_1', + 'CRC_IN_CUR_2', 'CRC_IN_CUR_3', 'CRC_IN_CUR_SEL', 'CRC_IN_PIX_0', + 'CRC_IN_PIX_1', 'CRC_IN_PIX_2', 'CRC_IN_PIX_3', 'CRC_IN_PIX_4', + 'CRC_IN_PIX_5', 'CRC_IN_PIX_6', 'CRC_IN_PIX_7', 'CRC_IN_PIX_SEL', + 'CRC_SRC_0', 'CRC_SRC_1', 'CRC_SRC_2', 'CRC_SRC_3', 'CRC_SRC_SEL', + 'CRC_STEREO_0', 'CRC_STEREO_1', 'CRC_STEREO_2', 'CRC_STEREO_3', + 'CRC_STEREO_SEL', 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', + 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'CROB_MEM_PWR_LIGHT_SLEEP_MODE', 'CROSSBAR_FOR_ALPHA', + 'CROSSBAR_FOR_CB_B', 'CROSSBAR_FOR_CR_R', 'CROSSBAR_FOR_Y_G', + 'CRS', 'CR_R_DATA_ONTO_ALPHA_PORT', 'CR_R_DATA_ONTO_CB_B_PORT', + 'CR_R_DATA_ONTO_CR_R_PORT', 'CR_R_DATA_ONTO_Y_G_PORT', + 'CSCNTL_ADDR_WIDTH', 'CSCNTL_DATA_WIDTH', 'CSCNTL_TYPE', + 'CSCNTL_TYPE_EVENT', 'CSCNTL_TYPE_PRIVATE', 'CSCNTL_TYPE_STATE', + 'CSCNTL_TYPE_TG', 'CSCNTL_TYPE_WIDTH', 'CSDATA_ADDR_WIDTH', + 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT', + 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG', + 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_NA', + 'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CURSOR_2X_MAGNIFY', + 'CURSOR_2X_MAGNIFY_IS_DISABLE', 'CURSOR_2X_MAGNIFY_IS_ENABLE', + 'CURSOR_COLOR_24BIT_1BIT_AND', + 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', + 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 'CURSOR_COLOR_64BIT_FP_PREMULT', + 'CURSOR_COLOR_64BIT_FP_UNPREMULT', 'CURSOR_ENABLE', + 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', + 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', 'CURSOR_IS_DISABLE', + 'CURSOR_IS_ENABLE', 'CURSOR_IS_NOT_SNOOP', 'CURSOR_IS_SNOOP', + 'CURSOR_LINES_PER_CHUNK', 'CURSOR_LINE_PER_CHUNK_1', + 'CURSOR_LINE_PER_CHUNK_16', 'CURSOR_LINE_PER_CHUNK_2', + 'CURSOR_LINE_PER_CHUNK_4', 'CURSOR_LINE_PER_CHUNK_8', + 'CURSOR_MODE', 'CURSOR_MONO_2BIT', + 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', + 'CURSOR_PERFMON_LATENCY_MEASURE_EN', + 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', + 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', + 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', + 'CURSOR_PERFMON_LATENCY_MEASURE_SEL', 'CURSOR_PITCH', + 'CURSOR_PITCH_128_PIXELS', 'CURSOR_PITCH_256_PIXELS', + 'CURSOR_PITCH_64_PIXELS', 'CURSOR_REQUEST_EARLY', + 'CURSOR_REQUEST_NORMALLY', 'CURSOR_REQ_MODE', 'CURSOR_SNOOP', + 'CURSOR_STEREO_EN', 'CURSOR_STEREO_IS_DISABLED', + 'CURSOR_STEREO_IS_ENABLED', 'CURSOR_SURFACE_IS_NOT_TMZ', + 'CURSOR_SURFACE_IS_TMZ', 'CURSOR_SURFACE_TMZ', 'CURSOR_SYSTEM', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', + 'CUR_CLAMP_DIS', 'CUR_CLAMP_EN', 'CUR_DIS', + 'CUR_DYNAMIC_EXPANSION', 'CUR_EN', 'CUR_ENABLE', + 'CUR_EXPAND_MODE', 'CUR_FP_NO_ROM', 'CUR_FP_USE_ROM', + 'CUR_INV_CLAMP', 'CUR_MODE', 'CUR_NOT_PENDING', 'CUR_PENDING', + 'CUR_ROM_EN', 'CUR_YES_PENDING', 'CUR_ZERO_EXPANSION', + 'CbYCrY10101010_422_PACKED', 'CbYCrY12121212_422_PACKED', + 'CbYCrY8888_422_PACKED', 'CmaskCode', 'CombFunc', 'CompareFrag', + 'ConservativeZExport', 'CovToShaderSel', 'CrYCbA1010102', + 'CrYCbA16161616_10LSB', 'CrYCbA16161616_10MSB', + 'CrYCbA16161616_12LSB', 'CrYCbA16161616_12MSB', 'CrYCbA8888', + 'CrYCbY10101010_422_PACKED', 'CrYCbY12121212_422_PACKED', + 'CrYCbY8888_422_PACKED', 'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA', + 'DAC_MUX_SELECT_DACB', 'DB_BREAK_BATCH_EVENT', 'DB_CACHE_FLUSH', + 'DB_CACHE_FLUSH_AND_INV', 'DB_CACHE_FLUSH_AND_INV_EVENT', + 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', 'DB_CACHE_FLUSH_TS', + 'DB_CONTEXT_DONE_EVENT', 'DB_CONTEXT_SUSPEND_EVENT', + 'DB_FLUSH_AND_INV_DB_DATA_TS', 'DB_FLUSH_AND_INV_DB_META', + 'DB_INVOKE_CHANGE_EVENT', 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 'DB_PERF_SEL_CB_DB_rdreq_sends', + 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 'DB_PERF_SEL_CB_DB_wrreq_sends', + 'DB_PERF_SEL_DB_CB_context_dones', 'DB_PERF_SEL_DB_CB_eop_dones', + 'DB_PERF_SEL_DB_CB_lquad_busy', + 'DB_PERF_SEL_DB_CB_lquad_double_format', + 'DB_PERF_SEL_DB_CB_lquad_export_quads', + 'DB_PERF_SEL_DB_CB_lquad_fast_format', + 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', + 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', + 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', + 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', + 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', + 'DB_PERF_SEL_DB_CB_lquad_quads', + 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1', + 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2', + 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1', + 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2', + 'DB_PERF_SEL_DB_CB_lquad_sends', + 'DB_PERF_SEL_DB_CB_lquad_slow_format', + 'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack', + 'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy', + 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', + 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', + 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', + 'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls', + 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', + 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', + 'DB_PERF_SEL_DB_SC_c_tile_rate', 'DB_PERF_SEL_DB_SC_quad_busy', + 'DB_PERF_SEL_DB_SC_quad_double_quad', + 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', + 'DB_PERF_SEL_DB_SC_quad_lit_quad', + 'DB_PERF_SEL_DB_SC_quad_noz_tiles', + 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', + 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', + 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', + 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', + 'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls', + 'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_s_tile_rate', + 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', + 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', + 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 'DB_PERF_SEL_DB_SC_tile_stalls', + 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DB_SC_z_tile_rate', + 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 'DB_PERF_SEL_Depth_Tile_Cache_event', + 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', + 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', + 'DB_PERF_SEL_Plane_Cache_flushes', + 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', + 'DB_PERF_SEL_Plane_Cache_misses', + 'DB_PERF_SEL_Plane_Cache_starves', + 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 'DB_PERF_SEL_PostZ_Samples_failing_S', + 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 'DB_PERF_SEL_PreZ_Samples_failing_S', + 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 'DB_PERF_SEL_RMI_rd_s_32byte_req', + 'DB_PERF_SEL_RMI_rd_s_32byte_ret', + 'DB_PERF_SEL_RMI_rd_tile_32byte_req', + 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', + 'DB_PERF_SEL_RMI_rd_z_32byte_req', + 'DB_PERF_SEL_RMI_rd_z_32byte_ret', + 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', + 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', + 'DB_PERF_SEL_RMI_wr_s_32byte_ack', + 'DB_PERF_SEL_RMI_wr_s_32byte_req', + 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', + 'DB_PERF_SEL_RMI_wr_tile_32byte_req', + 'DB_PERF_SEL_RMI_wr_z_32byte_ack', + 'DB_PERF_SEL_RMI_wr_z_32byte_req', 'DB_PERF_SEL_SC_DB_quad_busy', + 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_quads', + 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', + 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', + 'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads', + 'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_tile_backface', + 'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered', + 'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends', + 'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles', + 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', + 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', + 'DB_PERF_SEL_SH_quads_outstanding_sum', + 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', + 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', + 'DB_PERF_SEL_SX_DB_quad_busy', + 'DB_PERF_SEL_SX_DB_quad_double_format', + 'DB_PERF_SEL_SX_DB_quad_export_quads', + 'DB_PERF_SEL_SX_DB_quad_exports', + 'DB_PERF_SEL_SX_DB_quad_fast_format', + 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', + 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', + 'DB_PERF_SEL_SX_DB_quad_sends', + 'DB_PERF_SEL_SX_DB_quad_slow_format', + 'DB_PERF_SEL_SX_DB_quad_stalls', + 'DB_PERF_SEL_Stencil_Cache_flushes', + 'DB_PERF_SEL_Stencil_Cache_frees', + 'DB_PERF_SEL_Stencil_Cache_hits', + 'DB_PERF_SEL_Stencil_Cache_misses', + 'DB_PERF_SEL_Stencil_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', + 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_surface_stall', + 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 'DB_PERF_SEL_Z_Cache_pmask_hits', + 'DB_PERF_SEL_Z_Cache_pmask_misses', + 'DB_PERF_SEL_Z_Cache_pmask_starves', + 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 'DB_PERF_SEL_clock_main_active', + 'DB_PERF_SEL_clock_mem_export_active', + 'DB_PERF_SEL_clock_reg_active', + 'DB_PERF_SEL_cs_events_pws_enable', + 'DB_PERF_SEL_depth_bounds_tile_culled', 'DB_PERF_SEL_di_dt_stall', + 'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends', + 'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy', + 'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends', + 'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile', + 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', + 'DB_PERF_SEL_dtt_sm_slot_stall', + 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', + 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', + 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_src_in_sends', + 'DB_PERF_SEL_esr_ps_src_in_squads', + 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_stall', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_ps_vic_busy', + 'DB_PERF_SEL_esr_ps_vic_stall', + 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', + 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', + 'DB_PERF_SEL_esr_psi_vic_tile_rate', + 'DB_PERF_SEL_esr_sqq_zi_busy', 'DB_PERF_SEL_esr_sqq_zi_stall', + 'DB_PERF_SEL_esr_vic_footprint_match_1x2', + 'DB_PERF_SEL_esr_vic_footprint_match_2x1', + 'DB_PERF_SEL_esr_vic_footprint_match_2x2', + 'DB_PERF_SEL_esr_vic_sqq_busy', 'DB_PERF_SEL_esr_vic_sqq_stall', + 'DB_PERF_SEL_etr_out_busy', 'DB_PERF_SEL_etr_out_cb_tile_stall', + 'DB_PERF_SEL_etr_out_esr_stall', + 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', + 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', + 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', + 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', + 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', + 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', + 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', + 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', + 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', + 'DB_PERF_SEL_flush_compressed_stencil', + 'DB_PERF_SEL_flush_expanded_stencil', + 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', + 'DB_PERF_SEL_flush_single_stencil', + 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', + 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', + 'DB_PERF_SEL_his_tile_culled', 'DB_PERF_SEL_hiz_tc_read_starved', + 'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_hiz_tile_culled', + 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', + 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', + 'DB_PERF_SEL_noz_waiting_for_postz_done', + 'DB_PERF_SEL_planes_flushed', + 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', + 'DB_PERF_SEL_postzl_full_launch', + 'DB_PERF_SEL_postzl_partial_launch', + 'DB_PERF_SEL_postzl_partial_waiting', + 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', + 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', + 'DB_PERF_SEL_postzl_src_in_sends', + 'DB_PERF_SEL_postzl_src_in_squads', + 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 'DB_PERF_SEL_postzl_src_in_stall', + 'DB_PERF_SEL_postzl_src_in_tile_rate', + 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_postzl_src_out_stall', + 'DB_PERF_SEL_postzl_tile_init_stall', + 'DB_PERF_SEL_postzl_tile_mem_stall', + 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', + 'DB_PERF_SEL_prezl_src_in_sends', + 'DB_PERF_SEL_prezl_src_in_squads', + 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 'DB_PERF_SEL_prezl_src_in_stall', + 'DB_PERF_SEL_prezl_src_in_tile_rate', + 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_prezl_src_out_stall', + 'DB_PERF_SEL_prezl_tile_init_stall', + 'DB_PERF_SEL_prezl_tile_mem_stall', + 'DB_PERF_SEL_ps_events_pws_enable', 'DB_PERF_SEL_qc_busy', + 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', + 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', + 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', + 'DB_PERF_SEL_quad_rd_mi_stall', + 'DB_PERF_SEL_quad_rd_mi_stall_unc', 'DB_PERF_SEL_quad_rd_panic', + 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', + 'DB_PERF_SEL_quad_rd_sends_unc', 'DB_PERF_SEL_quad_rd_tag_stall', + 'DB_PERF_SEL_quad_rdret_busy', 'DB_PERF_SEL_quad_rdret_sends', + 'DB_PERF_SEL_quad_wr_acks', 'DB_PERF_SEL_quad_wr_busy', + 'DB_PERF_SEL_quad_wr_coherency_stall', + 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', + 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', + 'DB_PERF_SEL_tcp_dispatcher_flushes', + 'DB_PERF_SEL_tcp_dispatcher_reads', + 'DB_PERF_SEL_tcp_prefetcher_flushes', + 'DB_PERF_SEL_tcp_prefetcher_reads', + 'DB_PERF_SEL_tcp_preloader_flushes', + 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', + 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', + 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 'DB_PERF_SEL_tiles_decomp_on_expclear', + 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', + 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', + 'DB_PERF_SEL_tl_expand_squads', + 'DB_PERF_SEL_tl_flush_expand_squads', + 'DB_PERF_SEL_tl_in_fast_z_stall', + 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', + 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', + 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', + 'DB_PERF_SEL_tl_preZ_squads', + 'DB_PERF_SEL_tl_stencil_locked_stall', + 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', + 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', + 'DB_PERF_SEL_tl_z_fetch_stall', + 'DB_PERF_SEL_ts_events_pws_enable', + 'DB_PERF_SEL_ts_tc_update_stall', + 'DB_PERF_SEL_tsc_insert_summarize_stall', + 'DB_PERF_SEL_unmapped_z_tile_culled', + 'DB_PERF_SEL_zf_plane_multicycle', 'DB_VPORT_CHANGED_EVENT', + 'DCCG_AUDIO_DTO0_SOURCE_SEL', 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', + 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', 'DCCG_AUDIO_DTO_SEL', + 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK', + 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', + 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 'DCCG_AUDIO_DTO_USE_512FBR_DTO', + 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL', + 'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON', + 'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE', + 'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL', + 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', + 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', + 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', + 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', + 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', + 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_MODE_HSYNC', + 'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START', + 'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP', + 'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_OTG_SELECT', + 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', + 'DCCG_PERF_SEL_OTG0', 'DCCG_PERF_SEL_OTG1', 'DCCG_PERF_SEL_OTG2', + 'DCCG_PERF_SEL_OTG3', 'DCCG_PERF_SEL_RESERVED', + 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', + 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE', + 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', + 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', + 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', + 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', + 'DCHUBBUB_MEM_POWER_MODE_OFF', + 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', 'DCHUBBUB_MEM_PWR_DIS_MODE', + 'DCHUBBUB_MEM_PWR_MODE', 'DCIOCHIP_AUX_ALL_PWR_OK', + 'DCIOCHIP_AUX_ALL_PWR_OK_0', 'DCIOCHIP_AUX_ALL_PWR_OK_1', + 'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1', + 'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0', + 'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1', + 'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_HYS_TUNE', + 'DCIOCHIP_AUX_HYS_TUNE_0', 'DCIOCHIP_AUX_HYS_TUNE_1', + 'DCIOCHIP_AUX_HYS_TUNE_2', 'DCIOCHIP_AUX_HYS_TUNE_3', + 'DCIOCHIP_AUX_RECEIVER_SEL', 'DCIOCHIP_AUX_RECEIVER_SEL_0', + 'DCIOCHIP_AUX_RECEIVER_SEL_1', 'DCIOCHIP_AUX_RECEIVER_SEL_2', + 'DCIOCHIP_AUX_RECEIVER_SEL_3', 'DCIOCHIP_AUX_RSEL0P9', + 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', + 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', + 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', + 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', + 'DCIOCHIP_AUX_VOD_TUNE', 'DCIOCHIP_AUX_VOD_TUNE_0', + 'DCIOCHIP_AUX_VOD_TUNE_1', 'DCIOCHIP_AUX_VOD_TUNE_2', + 'DCIOCHIP_AUX_VOD_TUNE_3', 'DCIOCHIP_GPIO_MASK_EN', + 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', + 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', + 'DCIOCHIP_I2C_COMPSEL', 'DCIOCHIP_I2C_FALLSLEWSEL', + 'DCIOCHIP_I2C_FALLSLEWSEL_00', 'DCIOCHIP_I2C_FALLSLEWSEL_01', + 'DCIOCHIP_I2C_FALLSLEWSEL_10', 'DCIOCHIP_I2C_FALLSLEWSEL_11', + 'DCIOCHIP_I2C_RECEIVER_SEL', 'DCIOCHIP_I2C_RECEIVER_SEL_0', + 'DCIOCHIP_I2C_RECEIVER_SEL_1', 'DCIOCHIP_I2C_RECEIVER_SEL_2', + 'DCIOCHIP_I2C_RECEIVER_SEL_3', 'DCIOCHIP_I2C_REC_COMPARATOR', + 'DCIOCHIP_I2C_REC_SCHMIT', 'DCIOCHIP_I2C_VPH_1V2_EN', + 'DCIOCHIP_I2C_VPH_1V2_EN_0', 'DCIOCHIP_I2C_VPH_1V2_EN_1', + 'DCIOCHIP_INVERT', 'DCIOCHIP_MASK', 'DCIOCHIP_MASK_DISABLE', + 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', + 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', + 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', + 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', + 'DCIOCHIP_REF_27_SRC_SEL', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', + 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', + 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', + 'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', + 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', + 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', + 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', + 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', + 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', + 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL', + 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', + 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', + 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', 'DCIO_DCRXPHY_SOFT_RESET', + 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', + 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', 'DCIO_DC_GENERICA_SEL', + 'DCIO_DC_GENERICB_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', + 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE', + 'DCIO_DC_GPU_TIMER_READ_SELECT', + 'DCIO_DC_GPU_TIMER_START_POSITION', + 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', + 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL', + 'DCIO_DIO_EXT_VSYNC_MASK', 'DCIO_DIO_OTG_EXT_VSYNC_MUX', + 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', + 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', + 'DCIO_DPCS_INTERRUPT_TYPE', + 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', + 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', + 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_DSYNC_SOFT_RESET', + 'DCIO_DSYNC_SOFT_RESET_ASSERT', 'DCIO_DSYNC_SOFT_RESET_DEASSERT', + 'DCIO_EXT_VSYNC_MASK_NONE', 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', + 'DCIO_EXT_VSYNC_MASK_PIPE0', 'DCIO_EXT_VSYNC_MASK_PIPE1', + 'DCIO_EXT_VSYNC_MASK_PIPE2', 'DCIO_EXT_VSYNC_MASK_PIPE3', + 'DCIO_EXT_VSYNC_MASK_PIPE4', 'DCIO_EXT_VSYNC_MASK_PIPE5', + 'DCIO_EXT_VSYNC_MUX_GENERICB', 'DCIO_EXT_VSYNC_MUX_OTG0', + 'DCIO_EXT_VSYNC_MUX_OTG1', 'DCIO_EXT_VSYNC_MUX_OTG2', + 'DCIO_EXT_VSYNC_MUX_OTG3', 'DCIO_EXT_VSYNC_MUX_OTG4', + 'DCIO_EXT_VSYNC_MUX_OTG5', 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 'DCIO_GENERICA_SEL_GENERICA_DCCG', 'DCIO_GENERICA_SEL_STEREOSYNC', + 'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICB_SEL_GENERICB_DCCG', + 'DCIO_GENERICB_SEL_STEREOSYNC', 'DCIO_GENERICB_SEL_SYNCEN', + 'DCIO_GENLK_CLK_GSL_MASK', 'DCIO_GENLK_CLK_GSL_MASK_NO', + 'DCIO_GENLK_CLK_GSL_MASK_STEREO', + 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', + 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', + 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', + 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', + 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', + 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', + 'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', + 'DCIO_GSL_SEL_GROUP_2', 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', + 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', + 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', 'DCIO_PHY_HPO_ENC_SRC_SEL', + 'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO', + 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', + 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', + 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SOCCLK', + 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', + 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', + 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', + 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', + 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', + 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', + 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', + 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', + 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', + 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', + 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', 'DC_DMCUB_INT_TYPE', + 'DC_DMCUB_TIMER_WINDOW', 'DC_MEM_GLOBAL_PWR_REQ_DIS', + 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 'DC_SMU_INTERRUPT_ENABLE', 'DDID_VMID_CNTL', 'DDID_VMID_PIPE', + 'DEBUG_BUS_SELECT_ABM0', 'DEBUG_BUS_SELECT_ABM1', + 'DEBUG_BUS_SELECT_ABM2', 'DEBUG_BUS_SELECT_ABM3', + 'DEBUG_BUS_SELECT_ABM_RESERVED0', + 'DEBUG_BUS_SELECT_ABM_RESERVED1', 'DEBUG_BUS_SELECT_DPG0', + 'DEBUG_BUS_SELECT_DPG1', 'DEBUG_BUS_SELECT_DPG2', + 'DEBUG_BUS_SELECT_DPG3', 'DEBUG_BUS_SELECT_DPG_RESERVED0', + 'DEBUG_BUS_SELECT_DPG_RESERVED1', 'DEBUG_BUS_SELECT_FMT0', + 'DEBUG_BUS_SELECT_FMT1', 'DEBUG_BUS_SELECT_FMT2', + 'DEBUG_BUS_SELECT_FMT3', 'DEBUG_BUS_SELECT_FMT_RESERVED0', + 'DEBUG_BUS_SELECT_FMT_RESERVED1', 'DEBUG_BUS_SELECT_OPPBUF0', + 'DEBUG_BUS_SELECT_OPPBUF1', 'DEBUG_BUS_SELECT_OPPBUF2', + 'DEBUG_BUS_SELECT_OPPBUF3', 'DEBUG_BUS_SELECT_OPPBUF_RESERVED0', + 'DEBUG_BUS_SELECT_OPPBUF_RESERVED1', 'DEBUG_BUS_SELECT_OPP_PIPE0', + 'DEBUG_BUS_SELECT_OPP_PIPE1', 'DEBUG_BUS_SELECT_OPP_PIPE2', + 'DEBUG_BUS_SELECT_OPP_PIPE3', + 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0', + 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1', 'DECERR', + 'DENORM_TRUNCATE', 'DETILE_BUFFER_PACKER_ENABLE', + 'DETILE_BUFFER_PACKER_IS_DISABLE', + 'DETILE_BUFFER_PACKER_IS_ENABLE', 'DFQ_MIN_FREE_ENTRIES', + 'DFQ_MIN_FREE_ENTRIES_0', 'DFQ_MIN_FREE_ENTRIES_1', + 'DFQ_MIN_FREE_ENTRIES_2', 'DFQ_MIN_FREE_ENTRIES_3', + 'DFQ_MIN_FREE_ENTRIES_4', 'DFQ_MIN_FREE_ENTRIES_5', + 'DFQ_MIN_FREE_ENTRIES_6', 'DFQ_MIN_FREE_ENTRIES_7', + 'DFQ_NUM_ENTRIES', 'DFQ_NUM_ENTRIES_0', 'DFQ_NUM_ENTRIES_1', + 'DFQ_NUM_ENTRIES_2', 'DFQ_NUM_ENTRIES_3', 'DFQ_NUM_ENTRIES_4', + 'DFQ_NUM_ENTRIES_5', 'DFQ_NUM_ENTRIES_6', 'DFQ_NUM_ENTRIES_7', + 'DFQ_NUM_ENTRIES_8', 'DFQ_SIZE', 'DFQ_SIZE_0', 'DFQ_SIZE_1', + 'DFQ_SIZE_2', 'DFQ_SIZE_3', 'DFQ_SIZE_4', 'DFQ_SIZE_5', + 'DFQ_SIZE_6', 'DFQ_SIZE_7', 'DFSMFlushEvents', 'DIFFERENT_RGB', + 'DIG_10BIT_TEST_PATTERN', 'DIG_ALL_PIXEL', + 'DIG_ALTERNATING_TEST_PATTERN', 'DIG_BE_CNTL_HPD1', + 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', 'DIG_BE_CNTL_HPD4', + 'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD_SELECT', 'DIG_BE_CNTL_MODE', + 'DIG_BE_CNTL_NO_HPD', 'DIG_BE_DP_MST_MODE', 'DIG_BE_DP_SST_MODE', + 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', 'DIG_BE_RESERVED3', + 'DIG_BE_RESERVED4', 'DIG_BE_TMDS_DVI_MODE', + 'DIG_BE_TMDS_HDMI_MODE', 'DIG_DIGITAL_BYPASS_ENABLE', + 'DIG_DIGITAL_BYPASS_OFF', 'DIG_DIGITAL_BYPASS_ON', + 'DIG_DIGITAL_BYPASS_SEL', 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', + 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', + 'DIG_DIGITAL_BYPASS_SEL_36BPP', + 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', + 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', + 'DIG_DIGITAL_BYPASS_SEL_ALPHA', 'DIG_DIGITAL_BYPASS_SEL_BYPASS', + 'DIG_EVEN_PIXEL_ONLY', 'DIG_FE_CNTL_SOURCE_SELECT', + 'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_OTG0', + 'DIG_FE_SOURCE_FROM_OTG1', 'DIG_FE_SOURCE_FROM_OTG2', + 'DIG_FE_SOURCE_FROM_OTG3', 'DIG_FE_SOURCE_RESERVED', + 'DIG_FE_STEREOSYNC_FROM_OTG0', 'DIG_FE_STEREOSYNC_FROM_OTG1', + 'DIG_FE_STEREOSYNC_FROM_OTG2', 'DIG_FE_STEREOSYNC_FROM_OTG3', + 'DIG_FE_STEREOSYNC_RESERVED', 'DIG_FIFO_1_PIX_PER_CYCLE', + 'DIG_FIFO_2_PIX_PER_CYCLE', 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL', + 'DIG_FIFO_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', + 'DIG_FIFO_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_NO_ERROR_OCCURRED', + 'DIG_FIFO_OUTPUT_PROCESSING_MODE', 'DIG_FIFO_OVERFLOW_OCCURRED', + 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR', 'DIG_FIFO_READ_CLOCK_SRC', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', + 'DIG_FIFO_UNDERFLOW_OCCURRED', 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', + 'DIG_FIFO_USE_OVERWRITE_LEVEL', 'DIG_INPUT_PIXEL_SEL', + 'DIG_IN_DEBUG_MODE', 'DIG_IN_NORMAL_OPERATION', + 'DIG_ODD_PIXEL_ONLY', 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', + 'DIG_OUTPUT_CRC_DATA_SEL', 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', + 'DIG_OUTPUT_CRC_FOR_AUDIO', 'DIG_OUTPUT_CRC_FOR_FULLFRAME', + 'DIG_OUTPUT_CRC_FOR_VBI', 'DIG_OUTPUT_CRC_ON_LINK0', + 'DIG_OUTPUT_CRC_ON_LINK1', 'DIG_PAIR_PIXELS', + 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', 'DIG_SINGLETON_PIXELS', + 'DIG_SL_PIXEL_GROUPING', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', + 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', + 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DIG_UPDATE_EYE_SEL_BOTH', + 'DIG_UPDATE_EYE_SEL_LEFT', 'DIG_UPDATE_EYE_SEL_RIGHT', + 'DIG_UPDATE_FIELD_SEL_BOTH', 'DIG_UPDATE_FIELD_SEL_BOTTOM', + 'DIG_UPDATE_FIELD_SEL_RESERVED', 'DIG_UPDATE_FIELD_SEL_TOP', + 'DIOMEM_DISABLE_MEM_PWR_CTRL', 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', + 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', + 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', + 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', + 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', 'DIOMEM_ENABLE_MEM_PWR_CTRL', + 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', + 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', + 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', 'DIOMEM_NO_FORCE_REQ', + 'DIOMEM_NO_FORCE_REQUEST', 'DIOMEM_PWR_DIS_CTRL', + 'DIOMEM_PWR_FORCE_CTRL', 'DIOMEM_PWR_FORCE_CTRL2', + 'DIOMEM_PWR_SEL_CTRL', 'DIOMEM_PWR_SEL_CTRL2', + 'DIO_DBG_BLOCK_SEL', 'DIO_DBG_BLOCK_SEL_AUX0', + 'DIO_DBG_BLOCK_SEL_AUX1', 'DIO_DBG_BLOCK_SEL_AUX2', + 'DIO_DBG_BLOCK_SEL_AUX3', 'DIO_DBG_BLOCK_SEL_AUX4', + 'DIO_DBG_BLOCK_SEL_DIGA', 'DIO_DBG_BLOCK_SEL_DIGB', + 'DIO_DBG_BLOCK_SEL_DIGC', 'DIO_DBG_BLOCK_SEL_DIGD', + 'DIO_DBG_BLOCK_SEL_DIGE', 'DIO_DBG_BLOCK_SEL_DIGFE_A', + 'DIO_DBG_BLOCK_SEL_DIGFE_B', 'DIO_DBG_BLOCK_SEL_DIGFE_C', + 'DIO_DBG_BLOCK_SEL_DIGFE_D', 'DIO_DBG_BLOCK_SEL_DIGFE_E', + 'DIO_DBG_BLOCK_SEL_DIO', 'DIO_DBG_BLOCK_SEL_DPA', + 'DIO_DBG_BLOCK_SEL_DPB', 'DIO_DBG_BLOCK_SEL_DPC', + 'DIO_DBG_BLOCK_SEL_DPD', 'DIO_DBG_BLOCK_SEL_DPE', + 'DIO_DBG_BLOCK_SEL_DPFE_A', 'DIO_DBG_BLOCK_SEL_DPFE_B', + 'DIO_DBG_BLOCK_SEL_DPFE_C', 'DIO_DBG_BLOCK_SEL_DPFE_D', + 'DIO_DBG_BLOCK_SEL_DPFE_E', 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', + 'DIO_DBG_BLOCK_SEL_RESERVED', 'DIO_FIFO_ERROR', + 'DIO_FIFO_ERROR_00', 'DIO_FIFO_ERROR_01', 'DIO_FIFO_ERROR_10', + 'DIO_FIFO_ERROR_11', + 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE', + 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', + 'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC', + 'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO', + 'DISABLE_DEBUG', 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', + 'DISABLE_PWL', 'DISABLE_TF0_OPT', 'DISABLE_TF1_OPT', + 'DISABLE_THE_FEATURE', 'DISABLE_THE_INTERRUPT', + 'DISPCLK_CHG_FWD_CORR_DISABLE', + 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', + 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', + 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DIVISOR_BY1', + 'DIVISOR_BY2_RESERVED', 'DIVISOR_BY3', 'DIVISOR_BY4_RESERVED', + 'DIVISOR_BY5_RESERVED', 'DIVISOR_BY6_RESERVED', + 'DIVISOR_BY7_RESERVED', 'DIVISOR_BY8_RESERVED', 'DIV_2', 'DIV_4', + 'DIV_8', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', + 'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1', + 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ', + 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', + 'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON', + 'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', + 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', + 'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_UNUSED_1', + 'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4', 'DI_PT_UNUSED_5', + 'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', + 'DI_SRC_SEL_RESERVED', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', + 'DMDATA_CLEAR_UNDERFLOW_STATUS', 'DMDATA_DONE', + 'DMDATA_DONT_CLEAR', 'DMDATA_HARDWARE_UPDATE_MODE', 'DMDATA_MODE', + 'DMDATA_NOT_SENT_TO_DIG', 'DMDATA_NOT_UNDERFLOW', + 'DMDATA_NOT_UPDATED', 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', + 'DMDATA_QOS_LEVEL_FROM_TTU', 'DMDATA_QOS_MODE', 'DMDATA_REPEAT', + 'DMDATA_SENT_TO_DIG', 'DMDATA_SOFTWARE_UPDATE_MODE', + 'DMDATA_UNDERFLOW', 'DMDATA_UNDERFLOWED', + 'DMDATA_UNDERFLOW_CLEAR', 'DMDATA_UPDATED', + 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', + 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', 'DMDATA_VM_DONE', + 'DMDATA_VM_IS_DONE', 'DMDATA_VM_IS_NOT_DONE', + 'DMDATA_WAS_UPDATED', 'DME_MEM_DISABLE_MEM_PWR_CTRL', + 'DME_MEM_ENABLE_MEM_PWR_CTRL', 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', + 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', 'DME_MEM_NO_FORCE_REQUEST', + 'DME_MEM_POWER_STATE_ENUM', 'DME_MEM_POWER_STATE_ENUM_DS', + 'DME_MEM_POWER_STATE_ENUM_LS', 'DME_MEM_POWER_STATE_ENUM_ON', + 'DME_MEM_POWER_STATE_ENUM_SD', 'DME_MEM_PWR_DIS_CTRL', + 'DME_MEM_PWR_FORCE_CTRL', 'DMU_CLOCK_ON', 'DMU_CLOCK_STATUS_OFF', + 'DMU_CLOCK_STATUS_ON', 'DMU_DC_GPU_TIMER_READ_SELECT', + 'DMU_DC_GPU_TIMER_START_POSITION', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', + 'DMU_GPU_TIMER_START_0_END_27', 'DMU_GPU_TIMER_START_10_END_37', + 'DMU_GPU_TIMER_START_1_END_28', 'DMU_GPU_TIMER_START_2_END_29', + 'DMU_GPU_TIMER_START_3_END_30', 'DMU_GPU_TIMER_START_4_END_31', + 'DMU_GPU_TIMER_START_6_END_33', 'DMU_GPU_TIMER_START_8_END_35', + 'DOLBY_VISION_DISABLED', 'DOLBY_VISION_ENABLE', + 'DOLBY_VISION_ENABLED', 'DONUTS', 'DOUT_I2C_ACK', + 'DOUT_I2C_ACK_TO_CLEAN', + 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_ABORT_XFER', + 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', + 'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT', + 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO', + 'DOUT_I2C_CONTROL_NORMAL_DEBUG', + 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', + 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', + 'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDCVGA', + 'DOUT_I2C_CONTROL_SEND_RESET', + 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH', + 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', + 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', + 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', + 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 'DOUT_I2C_CONTROL__SEND_RESET', + 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', + 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', + 'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE', + 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', + 'DOUT_I2C_DDC_SPEED_THRESHOLD', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', + 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', + 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', + 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DPHY_8B10B_CUR_DISP', + 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', + 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', + 'DPHY_8B10B_RESETET', + 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', + 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', + 'DPHY_ALT_SCRAMBLER_RESET_EN', 'DPHY_ALT_SCRAMBLER_RESET_SEL', + 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', + 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', + 'DPHY_ATEST_LANE0_PRBS_PATTERN', 'DPHY_ATEST_LANE0_REG_PATTERN', + 'DPHY_ATEST_LANE1_PRBS_PATTERN', 'DPHY_ATEST_LANE1_REG_PATTERN', + 'DPHY_ATEST_LANE2_PRBS_PATTERN', 'DPHY_ATEST_LANE2_REG_PATTERN', + 'DPHY_ATEST_LANE3_PRBS_PATTERN', 'DPHY_ATEST_LANE3_REG_PATTERN', + 'DPHY_ATEST_SEL_LANE0', 'DPHY_ATEST_SEL_LANE1', + 'DPHY_ATEST_SEL_LANE2', 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', + 'DPHY_CRC_CONTINUOUS', 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', + 'DPHY_CRC_EN', 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', + 'DPHY_CRC_LANE0_SELECTED', 'DPHY_CRC_LANE1_SELECTED', + 'DPHY_CRC_LANE2_SELECTED', 'DPHY_CRC_LANE3_SELECTED', + 'DPHY_CRC_MST_PHASE_ERROR_ACK', 'DPHY_CRC_MST_PHASE_ERROR_ACKED', + 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', + 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', + 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', + 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', + 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 'DPHY_FEC_ACTIVE', 'DPHY_FEC_DISABLED', 'DPHY_FEC_ENABLE', + 'DPHY_FEC_ENABLED', 'DPHY_FEC_NOT_ACTIVE', 'DPHY_FEC_READY', + 'DPHY_FEC_READY_DIS', 'DPHY_FEC_READY_EN', + 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', + 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', + 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', + 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', + 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', + 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SCRAMBLER_ADVANCE', + 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', + 'DPHY_SCRAMBLER_DIS', 'DPHY_SCRAMBLER_KCODE', + 'DPHY_SCRAMBLER_KCODE_DISABLED', 'DPHY_SCRAMBLER_KCODE_ENABLED', + 'DPHY_SCRAMBLER_SEL', 'DPHY_SCRAMBLER_SEL_DBG_DATA', + 'DPHY_SCRAMBLER_SEL_LANE_DATA', 'DPHY_SCR_DISABLED', + 'DPHY_SCR_ENABLED', 'DPHY_SKEW_BYPASS', + 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM', + 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', + 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', + 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', + 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', + 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', + 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', + 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', + 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', + 'DPTE_GROUP_SIZE', 'DPTE_GROUP_SIZE_1024B', + 'DPTE_GROUP_SIZE_128B', 'DPTE_GROUP_SIZE_2048B', + 'DPTE_GROUP_SIZE_256B', 'DPTE_GROUP_SIZE_512B', + 'DPTE_GROUP_SIZE_64B', 'DP_128B132B', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', 'DP_AUX_ARB_STATUS', + 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', + 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', + 'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD_SEL', + 'DP_AUX_CONTROL_NO_HPD_SELECTED', 'DP_AUX_CONTROL_TEST_MODE', + 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 'DP_AUX_CONTROL_TEST_MODE_ENABLE', + 'DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', + 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', + 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 'DP_AUX_IDLE', 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', + 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', + 'DP_AUX_INT__NOT_ACK', 'DP_AUX_IN_USE_GTC', 'DP_AUX_IN_USE_LS', + 'DP_AUX_IN_USE_PHYWAKE', 'DP_AUX_IN_USE_SW', + 'DP_AUX_LS_UPDATE_ACK', 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', + 'DP_AUX_PHY_WAKE_LOW_PRIORITY', 'DP_AUX_PHY_WAKE_PRIORITY', + 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', + 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', + 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', + 'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_RX_TIMEOUT_LEN_MUL', + 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', + 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', + 'DP_AUX_SW_CONTROL_LS_READ_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', + 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 'DP_AUX_TX_PRECHARGE_LEN_MUL', 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', + 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', + 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', 'DP_COMPONENT_DEPTH', + 'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC', + 'DP_COMPONENT_DEPTH_16BPC', 'DP_COMPONENT_DEPTH_6BPC', + 'DP_COMPONENT_DEPTH_8BPC', 'DP_CP_ENCRYPTION_TYPE', + 'DP_CP_ENCRYPTION_TYPE_0', 'DP_CP_ENCRYPTION_TYPE_1', + 'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE', + 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', + 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', + 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', + 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', + 'DP_DPHY_SYM32_1LANE', 'DP_DPHY_SYM32_2LANE', + 'DP_DPHY_SYM32_4LANE', 'DP_DPHY_SYM32_ACTIVE', + 'DP_DPHY_SYM32_CRC_END_LLCP', 'DP_DPHY_SYM32_CRC_END_PS_ANY', + 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', 'DP_DPHY_SYM32_CRC_END_PS_ONLY', + 'DP_DPHY_SYM32_CRC_START_LLCP', + 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', + 'DP_DPHY_SYM32_CRC_START_PS_ONLY', + 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', + 'DP_DPHY_SYM32_CRC_START_TP_START', + 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', + 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', + 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', + 'DP_DPHY_SYM32_CRC_USE_END_EVENT', + 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', 'DP_DPHY_SYM32_DISABLE', + 'DP_DPHY_SYM32_ENABLE', 'DP_DPHY_SYM32_ENCRYPT_TYPE0', + 'DP_DPHY_SYM32_ENCRYPT_TYPE1', 'DP_DPHY_SYM32_LT_TPS1', + 'DP_DPHY_SYM32_LT_TPS2', 'DP_DPHY_SYM32_NOT_RESET', + 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', + 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', 'DP_DPHY_SYM32_RESERVED', + 'DP_DPHY_SYM32_RESET', 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', + 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', + 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', + 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', + 'DP_DPHY_SYM32_SAT_NO_UPDATE', + 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', + 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', + 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', + 'DP_DPHY_SYM32_STATUS_ENABLED', 'DP_DPHY_SYM32_STATUS_IDLE', + 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', + 'DP_DPHY_SYM32_STREAM_OVR_NONE', + 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', + 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', + 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', 'DP_DPHY_SYM32_TEST', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', + 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', 'DP_DPHY_SYM32_TP_SELECT_PRBS', + 'DP_DPHY_SYM32_TP_SELECT_SQUARE', 'DP_DPHY_SYM32_TP_SELECT_TPS1', + 'DP_DPHY_SYM32_TP_SELECT_TPS2', 'DP_DSC_444_SIMPLE_422', + 'DP_DSC_DISABLE', 'DP_DSC_MODE', 'DP_DSC_NATIVE_422_420', + 'DP_DTO_DESPREAD_DISABLE', 'DP_DTO_DESPREAD_ENABLE', + 'DP_DTO_DS_DISABLE', 'DP_EMBEDDED_PANEL', + 'DP_EMBEDDED_PANEL_MODE', 'DP_EXTERNAL_PANEL', + 'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE', + 'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_LINK_TRAINING_SWITCH_MODE', + 'DP_LINK_TRAINING_SWITCH_TO_IDLE', + 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', 'DP_ML_PHY_SEQ_IMMEDIATE', + 'DP_ML_PHY_SEQ_LINE_NUM', 'DP_ML_PHY_SEQ_MODE', + 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', + 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', + 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', + 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', + 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', + 'DP_MSE_SAT_ENCRYPT0', 'DP_MSE_SAT_ENCRYPT0_DISABLED', + 'DP_MSE_SAT_ENCRYPT0_ENABLED', 'DP_MSE_SAT_ENCRYPT1', + 'DP_MSE_SAT_ENCRYPT1_DISABLED', 'DP_MSE_SAT_ENCRYPT1_ENABLED', + 'DP_MSE_SAT_ENCRYPT2', 'DP_MSE_SAT_ENCRYPT2_DISABLED', + 'DP_MSE_SAT_ENCRYPT2_ENABLED', 'DP_MSE_SAT_ENCRYPT3', + 'DP_MSE_SAT_ENCRYPT3_DISABLED', 'DP_MSE_SAT_ENCRYPT3_ENABLED', + 'DP_MSE_SAT_ENCRYPT4', 'DP_MSE_SAT_ENCRYPT4_DISABLED', + 'DP_MSE_SAT_ENCRYPT4_ENABLED', 'DP_MSE_SAT_ENCRYPT5', + 'DP_MSE_SAT_ENCRYPT5_DISABLED', 'DP_MSE_SAT_ENCRYPT5_ENABLED', + 'DP_MSE_SAT_UPDATE_ACT', 'DP_MSE_SAT_UPDATE_NO_ACTION', + 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', + 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', + 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', + 'DP_MSO_FOUR_SSTLINK', 'DP_MSO_NUM_OF_SST_LINKS', + 'DP_MSO_ONE_SSTLINK', 'DP_MSO_TWO_SSTLINK', + 'DP_ONE_PIXEL_PER_CYCLE', 'DP_PIXEL_ENCODING', + 'DP_PIXEL_ENCODING_RGB444', 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', + 'DP_PIXEL_ENCODING_YCBCR420', 'DP_PIXEL_ENCODING_YCBCR422', + 'DP_PIXEL_ENCODING_YCBCR444', 'DP_PIXEL_ENCODING_Y_ONLY', + 'DP_PIXEL_PER_CYCLE_PROCESSING_NUM', + 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', + 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', + 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', + 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', + 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', + 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', + 'DP_SEC_GSP_SEND', 'DP_SEC_GSP_SEND_ANY_LINE', + 'DP_SEC_GSP_SEND_PPS', 'DP_SEC_LINE_REFERENCE', + 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE', + 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_STEER_OVERFLOW_ACK', + 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', + 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', + 'DP_STREAM_ENC_DCCG', 'DP_STREAM_ENC_DISPLAY_PIPE', + 'DP_STREAM_ENC_HARDWARE', 'DP_STREAM_ENC_NOT_RESET', + 'DP_STREAM_ENC_NO_ERROR_OCCURRED', + 'DP_STREAM_ENC_OVERFLOW_OCCURRED', + 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR', + 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT', + 'DP_STREAM_ENC_PROGRAMMABLE', 'DP_STREAM_ENC_READ_CLOCK_CONTROL', + 'DP_STREAM_ENC_RESET', 'DP_STREAM_ENC_RESET_CONTROL', + 'DP_STREAM_ENC_STREAM_ACTIVE', 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', + 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', + 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', + 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET', + 'DP_STREAM_MAPPER_LINK0', 'DP_STREAM_MAPPER_LINK1', + 'DP_STREAM_MAPPER_RESERVED', 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', + 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', + 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', + 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', + 'DP_SYM32_ENC_COMPRESSED_FORMAT', 'DP_SYM32_ENC_CONTINUOUS_MODE', + 'DP_SYM32_ENC_CRC_NOT_VALID', 'DP_SYM32_ENC_CRC_VALID', + 'DP_SYM32_ENC_DISABLE', 'DP_SYM32_ENC_DP_SOF', + 'DP_SYM32_ENC_ENABLE', 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', + 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', + 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', + 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', + 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', + 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', + 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', + 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', + 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', + 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', + 'DP_SYM32_ENC_NOT_PENDING', 'DP_SYM32_ENC_NOT_RESET', + 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', 'DP_SYM32_ENC_ONE_SHOT_MODE', + 'DP_SYM32_ENC_OTG_SOF', 'DP_SYM32_ENC_OVERFLOW_OCCURRED', + 'DP_SYM32_ENC_PENDING', + 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', + 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', + 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', + 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', + 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', + 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', + 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', + 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', 'DP_SYM32_ENC_RESET', + 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', + 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', + 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', 'DP_SYM32_ENC_SDP_LOW_PRIORITY', + 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', + 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', + 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', + 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', 'DP_SYNC_POLARITY', + 'DP_SYNC_POLARITY_ACTIVE_HIGH', 'DP_SYNC_POLARITY_ACTIVE_LOW', + 'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_TWO_PIXEL_PER_CYCLE', + 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', 'DP_UDI_4_LANES', + 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', + 'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_M_1X_INPUT_PIXEL_RATE', + 'DP_VID_M_2X_INPUT_PIXEL_RATE', 'DP_VID_M_4X_INPUT_PIXEL_RATE', + 'DP_VID_M_8X_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO', + 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', + 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', + 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_N_MUL', + 'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK', + 'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', + 'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV', + 'DP_VID_VBID_FIELD_POL_NORMAL', 'DRAW_DONE', + 'DSCCIF_BITS_PER_COMPONENT_ENUM', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 'DSCCIF_ENABLE_ENUM', 'DSCCIF_ENABLE_ENUM_DISABLED', + 'DSCCIF_ENABLE_ENUM_ENABLED', 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', + 'DSCC_BITS_PER_COMPONENT_ENUM', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 'DSCC_DSC_VERSION_MAJOR_ENUM', + 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', + 'DSCC_DSC_VERSION_MINOR_ENUM', + 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', + 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', + 'DSCC_ENABLE_ENUM', 'DSCC_ENABLE_ENUM_DISABLED', + 'DSCC_ENABLE_ENUM_ENABLED', 'DSCC_ICH_RESET_ENUM', + 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', 'DSCC_LINEBUF_DEPTH_ENUM', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', + 'DSCC_MEM_PWR_DIS_ENUM', 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', + 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', 'DSCC_MEM_PWR_FORCE_ENUM', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', + 'DSCL_MODE_CHROMA_SCALING_BYPASS', 'DSCL_MODE_DSCL_BYPASS', + 'DSCL_MODE_LUMA_SCALING_BYPASS', 'DSCL_MODE_SCALING_444_BYPASS', + 'DSCL_MODE_SCALING_444_RGB_ENABLE', + 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', + 'DSCL_MODE_SCALING_YCBCR_ENABLE', 'DSCL_MODE_SEL', 'DSM_DATA_SEL', + 'DSM_DATA_SEL_0', 'DSM_DATA_SEL_1', 'DSM_DATA_SEL_BOTH', + 'DSM_DATA_SEL_DISABLE', 'DSM_ENABLE_ERROR_INJECT', + 'DSM_ENABLE_ERROR_INJECT_FED_IN', + 'DSM_ENABLE_ERROR_INJECT_SINGLE', + 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', + 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', + 'DSM_SELECT_INJECT_DELAY', 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', + 'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DSM_SINGLE_WRITE', + 'DSM_SINGLE_WRITE_DIS', 'DSM_SINGLE_WRITE_EN', 'DS_HW_CAL_DIS', + 'DS_HW_CAL_EN', 'DS_HW_CAL_ENABLE', 'DS_JITTER_COUNT_SRC_SEL', + 'DS_JITTER_COUNT_SRC_SEL0', 'DS_JITTER_COUNT_SRC_SEL1', + 'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', + 'DS_REF_SRC', 'DTO_FORCE_BYPASS', 'DTO_FORCE_NO_BYPASS', + 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKC_IN_PHASE', + 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', + 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE', + 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', + 'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', + 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST', + 'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE', + 'DWB_CRC_CONT_EN_CONT', 'DWB_CRC_CONT_EN_ENUM', + 'DWB_CRC_CONT_EN_ONE_SHOT', 'DWB_CRC_SRC_SEL_DWB_IN', + 'DWB_CRC_SRC_SEL_DWB_OUT', 'DWB_CRC_SRC_SEL_ENUM', + 'DWB_CRC_SRC_SEL_OGAM_OUT', 'DWB_DATA_OVERFLOW_INT_TYPE_0', + 'DWB_DATA_OVERFLOW_INT_TYPE_1', 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM', + 'DWB_DATA_OVERFLOW_TYPE_BUFFER', 'DWB_DATA_OVERFLOW_TYPE_ENUM', + 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', + 'DWB_DATA_OVERFLOW_TYPE_VREADY', 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', + 'DWB_DEBUG_SEL_DWBCP', 'DWB_DEBUG_SEL_ENUM', 'DWB_DEBUG_SEL_FC', + 'DWB_DEBUG_SEL_PERFMON', 'DWB_DEBUG_SEL_RESERVED', + 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM', + 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', + 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', + 'DWB_GAMUT_REMAP_MODE_BYPASS', 'DWB_GAMUT_REMAP_MODE_COEF_A', + 'DWB_GAMUT_REMAP_MODE_COEF_B', 'DWB_GAMUT_REMAP_MODE_ENUM', + 'DWB_GAMUT_REMAP_MODE_RESERVED', 'DWB_LUT_NUM_SEG', + 'DWB_MEM_PWR_FORCE_DIS', 'DWB_MEM_PWR_FORCE_DS', + 'DWB_MEM_PWR_FORCE_ENUM', 'DWB_MEM_PWR_FORCE_LS', + 'DWB_MEM_PWR_FORCE_SD', 'DWB_MEM_PWR_STATE_DS', + 'DWB_MEM_PWR_STATE_ENUM', 'DWB_MEM_PWR_STATE_LS', + 'DWB_MEM_PWR_STATE_ON', 'DWB_MEM_PWR_STATE_SD', + 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', 'DWB_OGAM_LUT_CONFIG_MODE_ENUM', + 'DWB_OGAM_LUT_CONFIG_MODE_SAME', 'DWB_OGAM_LUT_HOST_SEL_ENUM', + 'DWB_OGAM_LUT_HOST_SEL_RAMA', 'DWB_OGAM_LUT_HOST_SEL_RAMB', + 'DWB_OGAM_LUT_READ_COLOR_SEL_B', + 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM', + 'DWB_OGAM_LUT_READ_COLOR_SEL_G', 'DWB_OGAM_LUT_READ_COLOR_SEL_R', + 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', + 'DWB_OGAM_LUT_READ_DBG_DISABLE', 'DWB_OGAM_LUT_READ_DBG_ENABLE', + 'DWB_OGAM_LUT_READ_DBG_ENUM', 'DWB_OGAM_MODE_BYPASS', + 'DWB_OGAM_MODE_ENUM', 'DWB_OGAM_MODE_RAM_LUT_ENABLED', + 'DWB_OGAM_MODE_RESERVED', 'DWB_OGAM_PWL_DISABLE_ENUM', + 'DWB_OGAM_PWL_DISABLE_FALSE', 'DWB_OGAM_PWL_DISABLE_TRUE', + 'DWB_OGAM_SELECT_A', 'DWB_OGAM_SELECT_B', 'DWB_OGAM_SELECT_ENUM', + 'DWB_SEGMENTS_1', 'DWB_SEGMENTS_128', 'DWB_SEGMENTS_16', + 'DWB_SEGMENTS_2', 'DWB_SEGMENTS_32', 'DWB_SEGMENTS_4', + 'DWB_SEGMENTS_64', 'DWB_SEGMENTS_8', 'DWB_TEST_CLK_SEL_ENUM', + 'DWB_TEST_CLK_SEL_G', 'DWB_TEST_CLK_SEL_P', 'DWB_TEST_CLK_SEL_R', + 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE', + 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', + 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', + 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', + 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', + 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', + 'DbPRTFaultBehavior', 'DbPSLControl', 'EARLY', + 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', + 'EFC_ACrYCb16161616_10LSB', 'EFC_ACrYCb16161616_10MSB', + 'EFC_ACrYCb16161616_12LSB', 'EFC_ACrYCb16161616_12MSB', + 'EFC_ACrYCb2101010', 'EFC_ACrYCb8888', 'EFC_ARGB1555', + 'EFC_ARGB16161616_10LSB', 'EFC_ARGB16161616_10MSB', + 'EFC_ARGB16161616_12LSB', 'EFC_ARGB16161616_12MSB', + 'EFC_ARGB16161616_FLOAT', 'EFC_ARGB16161616_SNORM', + 'EFC_ARGB16161616_UNORM', 'EFC_ARGB2101010', 'EFC_ARGB4444', + 'EFC_ARGB8888', 'EFC_AYCrCb16161616_10LSB', + 'EFC_AYCrCb16161616_10MSB', 'EFC_AYCrCb16161616_12LSB', + 'EFC_AYCrCb16161616_12MSB', 'EFC_AYCrCb8888', 'EFC_BGR101111_FIX', + 'EFC_BGR101111_FLOAT', 'EFC_BGR565', + 'EFC_CbYCrY10101010_422_PACKED', 'EFC_CbYCrY12121212_422_PACKED', + 'EFC_CbYCrY8888_422_PACKED', 'EFC_CrYCbA1010102', + 'EFC_CrYCbA16161616_10LSB', 'EFC_CrYCbA16161616_10MSB', + 'EFC_CrYCbA16161616_12LSB', 'EFC_CrYCbA16161616_12MSB', + 'EFC_CrYCbA8888', 'EFC_CrYCbY10101010_422_PACKED', + 'EFC_CrYCbY12121212_422_PACKED', 'EFC_CrYCbY8888_422_PACKED', + 'EFC_MONO_10LSB', 'EFC_MONO_10MSB', 'EFC_MONO_12LSB', + 'EFC_MONO_12MSB', 'EFC_MONO_16', 'EFC_MONO_8', + 'EFC_RGB111110_FIX', 'EFC_RGB111110_FLOAT', 'EFC_RGB565', + 'EFC_RGBA1010102', 'EFC_RGBA16161616_10LSB', + 'EFC_RGBA16161616_10MSB', 'EFC_RGBA16161616_12LSB', + 'EFC_RGBA16161616_12MSB', 'EFC_RGBA16161616_FLOAT', + 'EFC_RGBA16161616_SNORM', 'EFC_RGBA16161616_UNORM', + 'EFC_RGBA4444', 'EFC_RGBA5551', 'EFC_RGBA8888', + 'EFC_SURFACE_PIXEL_FORMAT', 'EFC_Y10_CbCr1010_420_PLANAR', + 'EFC_Y10_CrCb1010_420_PLANAR', 'EFC_Y12_CbCr1212_420_PLANAR', + 'EFC_Y12_CrCb1212_420_PLANAR', 'EFC_Y8_CbCr88_420_PLANAR', + 'EFC_Y8_CrCb88_420_PLANAR', 'EFC_YCbYCr10101010_422_PACKED', + 'EFC_YCbYCr12121212_422_PACKED', 'EFC_YCbYCr8888_422_PACKED', + 'EFC_YCrCbA16161616_10LSB', 'EFC_YCrCbA16161616_10MSB', + 'EFC_YCrCbA16161616_12LSB', 'EFC_YCrCbA16161616_12MSB', + 'EFC_YCrCbA8888', 'EFC_YCrYCb10101010_422_PACKED', + 'EFC_YCrYCb12121212_422_PACKED', 'EFC_YCrYCb8888_422_PACKED', + 'ENABLE', 'ENABLE_AMCLK0', 'ENABLE_AMCLK1', 'ENABLE_CLOCK', + 'ENABLE_DEBUG', 'ENABLE_ENUM', 'ENABLE_ENUM_DISABLED', + 'ENABLE_ENUM_ENABLED', 'ENABLE_JITTER_REMOVAL', + 'ENABLE_LEGACY_PIPELINE', 'ENABLE_MEM_PWR_CTRL', + 'ENABLE_NGG_PIPELINE', 'ENABLE_PWL', 'ENABLE_TF0_OPT', + 'ENABLE_TF1_OPT', 'ENABLE_THE_FEATURE', 'ENABLE_THE_FUNC_CLOCK', + 'ENABLE_THE_INTERRUPT', 'ENABLE_THE_REFCLK', 'END_OF_PIPE_IB_END', + 'END_OF_PIPE_INCR_DE', 'END_OF_ROW_MODE', 'ENUM_DCN_ACTIVE', + 'ENUM_DCN_NOT_ACTIVE', 'ENUM_DIO_DCN_ACTIVE_STATUS', + 'ENUM_DPG_BIT_DEPTH', 'ENUM_DPG_BIT_DEPTH_10BPC', + 'ENUM_DPG_BIT_DEPTH_12BPC', 'ENUM_DPG_BIT_DEPTH_6BPC', + 'ENUM_DPG_BIT_DEPTH_8BPC', 'ENUM_DPG_DISABLE', + 'ENUM_DPG_DYNAMIC_RANGE', 'ENUM_DPG_DYNAMIC_RANGE_CEA', + 'ENUM_DPG_DYNAMIC_RANGE_VESA', 'ENUM_DPG_EN', 'ENUM_DPG_ENABLE', + 'ENUM_DPG_FIELD_POLARITY', + 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', + 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', 'ENUM_DPG_MODE', + 'ENUM_DPG_MODE_HORIZONTAL_BAR', 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', + 'ENUM_DPG_MODE_RGB_DUAL_RAMP', 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', + 'ENUM_DPG_MODE_RGB_XR_BIAS', 'ENUM_DPG_MODE_VERTICAL_BAR', + 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', + 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', + 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT', + 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT', + 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE', + 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', + 'ENUM_DP_DPHY_SYM32_ENABLE', 'ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE', + 'ENUM_DP_DPHY_SYM32_MODE', 'ENUM_DP_DPHY_SYM32_NUM_LANES', + 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING', + 'ENUM_DP_DPHY_SYM32_RESET', 'ENUM_DP_DPHY_SYM32_RESET_STATUS', + 'ENUM_DP_DPHY_SYM32_SAT_UPDATE', + 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING', + 'ENUM_DP_DPHY_SYM32_STATUS', + 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE', + 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE', + 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL', 'ENUM_DP_DPHY_SYM32_TP_SELECT', + 'ENUM_DP_SYM32_ENC_AUDIO_MUTE', + 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE', + 'ENUM_DP_SYM32_ENC_CRC_VALID', + 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH', + 'ENUM_DP_SYM32_ENC_ENABLE', + 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED', + 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION', + 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE', + 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING', + 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM', + 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS', 'ENUM_DP_SYM32_ENC_PENDING', + 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING', + 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE', + 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM', 'ENUM_DP_SYM32_ENC_RESET', + 'ENUM_DP_SYM32_ENC_SDP_PRIORITY', + 'ENUM_DP_SYM32_ENC_SOF_REFERENCE', + 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER', 'ENUM_DSCRM_DISABLE', + 'ENUM_DSCRM_EN', 'ENUM_DSCRM_ENABLE', 'ENUM_NUM_SIMD_PER_CU', + 'ES_STAGE_DS', 'ES_STAGE_OFF', 'ES_STAGE_REAL', 'EXOKAY', + 'EXPANSION_MODE', 'EXPANSION_MODE_CONSERVATIVE', + 'EXPANSION_MODE_OPTIMAL', 'EXPANSION_MODE_ZERO', + 'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR', 'EXPORT_4C_16BPC', + 'EXPORT_4C_32BPC', 'EXPORT_ANY_Z', 'EXPORT_GREATER_THAN_Z', + 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'FAULT_FAIL', + 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', 'FC_EYE_SELECTION_ENUM', + 'FC_EYE_SELECTION_LEFT_EYE', 'FC_EYE_SELECTION_RIGHT_EYE', + 'FC_EYE_SELECTION_STEREO_DIS', 'FC_FRAME_CAPTURE_RATE_ENUM', + 'FC_FRAME_CAPTURE_RATE_FULL', 'FC_FRAME_CAPTURE_RATE_HALF', + 'FC_FRAME_CAPTURE_RATE_QUARTER', 'FC_FRAME_CAPTURE_RATE_THIRD', + 'FC_STEREO_EYE_POLARITY_ENUM', 'FC_STEREO_EYE_POLARITY_LEFT', + 'FC_STEREO_EYE_POLARITY_RIGHT', 'FEC_ACTIVE_STATUS', 'FIX_S2_13', + 'FIX_S3_12', 'FLIP_ANY_FRAME', 'FLIP_LEFT_EYE', 'FLIP_RATE', + 'FLIP_RATE_0', 'FLIP_RATE_1', 'FLIP_RATE_2', 'FLIP_RATE_3', + 'FLIP_RATE_4', 'FLIP_RATE_5', 'FLIP_RATE_6', 'FLIP_RATE_7', + 'FLIP_RIGHT_EYE', 'FLUSH_AND_INV_CB_DATA_TS', + 'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA', + 'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META', + 'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED', + 'FLUSH_DFSM', 'FLUSH_ES_OUTPUT', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', + 'FMTMEM_DISABLE_MEM_PWR_CTRL', 'FMTMEM_ENABLE_MEM_PWR_CTRL', + 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', + 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', + 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', 'FMTMEM_NO_FORCE_REQUEST', + 'FMTMEM_PWR_DIS_CTRL', 'FMTMEM_PWR_FORCE_CTRL', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 'FMT_CLAMP_CNTL_COLOR_FORMAT', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', + 'FMT_CONTROL_PIXEL_ENCODING', + 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', + 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 'FMT_CONTROL_SUBSAMPLING_MODE', + 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', + 'FMT_CONTROL_SUBSAMPLING_ORDER', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', + 'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', + 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', + 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', + 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE', + 'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12', + 'FMT_FRAME_RANDOM_ENABLE_CONTROL', + 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', + 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', 'FMT_POWER_STATE_ENUM', + 'FMT_POWER_STATE_ENUM_DS', 'FMT_POWER_STATE_ENUM_LS', + 'FMT_POWER_STATE_ENUM_ON', 'FMT_POWER_STATE_ENUM_SD', + 'FMT_RGB_RANDOM_ENABLE_CONTROL', + 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', + 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', + 'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0', + 'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2', + 'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVERRIDE_CONTROL', + 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', + 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', 'FORCE_00', + 'FORCE_BINNING_ON', 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', + 'FORCE_DISABLE_CLOCK', 'FORCE_EARLY_Z', 'FORCE_ENABLE', + 'FORCE_FF', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ', + 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', + 'FORCE_ONE_ROW_FOR_FRAME', 'FORCE_ONE_ROW_FOR_FRAME_0', + 'FORCE_ONE_ROW_FOR_FRAME_1', 'FORCE_OPT_AUTO', + 'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', + 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', + 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', + 'FORCE_THE_CLOCK_DISABLED', 'FORMAT_CROSSBAR', + 'FORMAT_CROSSBAR_B', 'FORMAT_CROSSBAR_G', 'FORMAT_CROSSBAR_R', + 'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER', + 'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL', + 'ForceControl', 'GAMUT_COEF', 'GAMUT_COEF_B', 'GATCL1RequestType', + 'GATCL1_TYPE_BYPASS', 'GATCL1_TYPE_NORMAL', + 'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE', + 'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT', + 'GB_EDC_DED_MODE_LOG', 'GB_TILING_CONFIG_MACROTABLE_SIZE', + 'GB_TILING_CONFIG_TABLE_SIZE', 'GCRPerfSel', + 'GCR_PERF_SEL_ALL_REQ', + 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CPC_ALL_REQ', 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPC_METADATA_REQ', + 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', 'GCR_PERF_SEL_CPC_SQC_INST_REQ', + 'GCR_PERF_SEL_CPC_TCP_REQ', + 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_CPF_ALL_REQ', 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPF_METADATA_REQ', + 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', 'GCR_PERF_SEL_CPF_SQC_INST_REQ', + 'GCR_PERF_SEL_CPF_TCP_REQ', + 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_CPG_ALL_REQ', 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPG_METADATA_REQ', + 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', 'GCR_PERF_SEL_CPG_SQC_INST_REQ', + 'GCR_PERF_SEL_CPG_TCP_REQ', + 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', 'GCR_PERF_SEL_NONE', + 'GCR_PERF_SEL_PHY_REQ', 'GCR_PERF_SEL_PIO_ALL_REQ', + 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', 'GCR_PERF_SEL_PIO_METADATA_REQ', + 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', 'GCR_PERF_SEL_PIO_SQC_INST_REQ', + 'GCR_PERF_SEL_PIO_TCP_REQ', + 'GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_PM_ALL_REQ', 'GCR_PERF_SEL_PM_GL1_ALL_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', 'GCR_PERF_SEL_PM_GL2_ALL_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', 'GCR_PERF_SEL_PM_METADATA_REQ', + 'GCR_PERF_SEL_PM_SQC_DATA_REQ', 'GCR_PERF_SEL_PM_SQC_INST_REQ', + 'GCR_PERF_SEL_PM_TCP_REQ', + 'GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_RLC_ALL_REQ', 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', 'GCR_PERF_SEL_RLC_METADATA_REQ', + 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', 'GCR_PERF_SEL_RLC_SQC_INST_REQ', + 'GCR_PERF_SEL_RLC_TCP_REQ', + 'GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_SDMA0_ALL_REQ', 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', + 'GCR_PERF_SEL_SDMA0_METADATA_REQ', + 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', + 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA0_TCP_REQ', + 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_SDMA1_ALL_REQ', 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', + 'GCR_PERF_SEL_SDMA1_METADATA_REQ', + 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', + 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA1_TCP_REQ', + 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', + 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', + 'GCR_PERF_SEL_UTCL2_FILTERED_RET', + 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', + 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', + 'GCR_PERF_SEL_UTCL2_REQ', 'GCR_PERF_SEL_UTCL2_RET', + 'GCR_PERF_SEL_VIRT_REQ', 'GDS_PERFCOUNT_SELECT', + 'GDS_PERF_SEL_GWS_BYPASS', 'GDS_PERF_SEL_GWS_RELEASED', + 'GDS_PERF_SEL_SE0_2COMP_REQ', 'GDS_PERF_SEL_SE0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE0_GDS_BYTE_OP', 'GDS_PERF_SEL_SE0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE0_GDS_RD_OP', 'GDS_PERF_SEL_SE0_GDS_REL_OP', + 'GDS_PERF_SEL_SE0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE0_GDS_WR_OP', + 'GDS_PERF_SEL_SE0_NORET', 'GDS_PERF_SEL_SE0_ORD_CNT', + 'GDS_PERF_SEL_SE0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_RET', + 'GDS_PERF_SEL_SE1_2COMP_REQ', 'GDS_PERF_SEL_SE1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE1_GDS_BYTE_OP', 'GDS_PERF_SEL_SE1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE1_GDS_RD_OP', 'GDS_PERF_SEL_SE1_GDS_REL_OP', + 'GDS_PERF_SEL_SE1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE1_GDS_WR_OP', + 'GDS_PERF_SEL_SE1_NORET', 'GDS_PERF_SEL_SE1_ORD_CNT', + 'GDS_PERF_SEL_SE1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_RET', + 'GDS_PERF_SEL_SE2_2COMP_REQ', 'GDS_PERF_SEL_SE2_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE2_GDS_BYTE_OP', 'GDS_PERF_SEL_SE2_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE2_GDS_RD_OP', 'GDS_PERF_SEL_SE2_GDS_REL_OP', + 'GDS_PERF_SEL_SE2_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE2_GDS_WR_OP', + 'GDS_PERF_SEL_SE2_NORET', 'GDS_PERF_SEL_SE2_ORD_CNT', + 'GDS_PERF_SEL_SE2_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_RET', + 'GDS_PERF_SEL_SE3_2COMP_REQ', 'GDS_PERF_SEL_SE3_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE3_GDS_BYTE_OP', 'GDS_PERF_SEL_SE3_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE3_GDS_RD_OP', 'GDS_PERF_SEL_SE3_GDS_REL_OP', + 'GDS_PERF_SEL_SE3_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE3_GDS_WR_OP', + 'GDS_PERF_SEL_SE3_NORET', 'GDS_PERF_SEL_SE3_ORD_CNT', + 'GDS_PERF_SEL_SE3_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_RET', + 'GDS_PERF_SEL_SE4_2COMP_REQ', 'GDS_PERF_SEL_SE4_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE4_GDS_BYTE_OP', 'GDS_PERF_SEL_SE4_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE4_GDS_RD_OP', 'GDS_PERF_SEL_SE4_GDS_REL_OP', + 'GDS_PERF_SEL_SE4_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE4_GDS_WR_OP', + 'GDS_PERF_SEL_SE4_NORET', 'GDS_PERF_SEL_SE4_ORD_CNT', + 'GDS_PERF_SEL_SE4_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE4_RET', + 'GDS_PERF_SEL_SE5_2COMP_REQ', 'GDS_PERF_SEL_SE5_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE5_GDS_BYTE_OP', 'GDS_PERF_SEL_SE5_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE5_GDS_RD_OP', 'GDS_PERF_SEL_SE5_GDS_REL_OP', + 'GDS_PERF_SEL_SE5_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE5_GDS_WR_OP', + 'GDS_PERF_SEL_SE5_NORET', 'GDS_PERF_SEL_SE5_ORD_CNT', + 'GDS_PERF_SEL_SE5_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE5_RET', + 'GDS_PERF_SEL_SE6_2COMP_REQ', 'GDS_PERF_SEL_SE6_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE6_GDS_BYTE_OP', 'GDS_PERF_SEL_SE6_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE6_GDS_RD_OP', 'GDS_PERF_SEL_SE6_GDS_REL_OP', + 'GDS_PERF_SEL_SE6_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE6_GDS_WR_OP', + 'GDS_PERF_SEL_SE6_NORET', 'GDS_PERF_SEL_SE6_ORD_CNT', + 'GDS_PERF_SEL_SE6_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE6_RET', + 'GDS_PERF_SEL_SE7_2COMP_REQ', 'GDS_PERF_SEL_SE7_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE7_GDS_BYTE_OP', 'GDS_PERF_SEL_SE7_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE7_GDS_RD_OP', 'GDS_PERF_SEL_SE7_GDS_REL_OP', + 'GDS_PERF_SEL_SE7_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE7_GDS_WR_OP', + 'GDS_PERF_SEL_SE7_NORET', 'GDS_PERF_SEL_SE7_ORD_CNT', + 'GDS_PERF_SEL_SE7_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE7_RET', + 'GDS_PERF_SEL_WBUF_WR', 'GDS_PERF_SEL_WR_COMP', + 'GE1_PERFCOUNT_SELECT', 'GE2_DIST_PERFCOUNT_SELECT', + 'GE2_SE_PERFCOUNT_SELECT', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', + 'GENERIC_STEREOSYNC_SEL', 'GENERIC_STEREOSYNC_SEL_D1', + 'GENERIC_STEREOSYNC_SEL_D2', 'GENERIC_STEREOSYNC_SEL_D3', + 'GENERIC_STEREOSYNC_SEL_D4', 'GENERIC_STEREOSYNC_SEL_RESERVED', + 'GEN_ONE', 'GEN_RESERVED', 'GEN_TWO', 'GEN_ZERO', + 'GL0V_CACHE_POLICIES', 'GL0V_CACHE_POLICY_HIT_EVICT', + 'GL0V_CACHE_POLICY_HIT_LRU', 'GL0V_CACHE_POLICY_MISS_EVICT', + 'GL0V_CACHE_POLICY_MISS_LRU', 'GL1A_PERF_SEL', + 'GL1A_PERF_SEL_ARB_REQUESTS', 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', 'GL1A_PERF_SEL_BUSY', + 'GL1A_PERF_SEL_CYCLE', 'GL1A_PERF_SEL_REQUEST_GL1C0', + 'GL1A_PERF_SEL_REQUEST_GL1C1', 'GL1A_PERF_SEL_REQUEST_GL1C2', + 'GL1A_PERF_SEL_REQUEST_GL1C3', 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', + 'GL1A_PERF_SEL_STALL_GL1C0', 'GL1A_PERF_SEL_STALL_GL1C1', + 'GL1A_PERF_SEL_STALL_GL1C2', 'GL1A_PERF_SEL_STALL_GL1C3', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', + 'GL1A_PERF_SEL_WDS_32B_GL1C0', 'GL1A_PERF_SEL_WDS_32B_GL1C1', + 'GL1A_PERF_SEL_WDS_32B_GL1C2', 'GL1A_PERF_SEL_WDS_32B_GL1C3', + 'GL1C_PERF_SEL', 'GL1C_PERF_SEL_ARB_RET_LEVEL', + 'GL1C_PERF_SEL_BUSY', 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', + 'GL1C_PERF_SEL_CYCLE', 'GL1C_PERF_SEL_GL2_REQ_PREFETCH', + 'GL1C_PERF_SEL_GL2_REQ_READ', 'GL1C_PERF_SEL_GL2_REQ_READ_128B', + 'GL1C_PERF_SEL_GL2_REQ_READ_32B', + 'GL1C_PERF_SEL_GL2_REQ_READ_64B', + 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', + 'GL1C_PERF_SEL_GL2_REQ_WRITE', 'GL1C_PERF_SEL_GL2_REQ_WRITE_32B', + 'GL1C_PERF_SEL_GL2_REQ_WRITE_64B', + 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'GL1C_PERF_SEL_REQ', + 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', 'GL1C_PERF_SEL_REQ_CLIENT0', + 'GL1C_PERF_SEL_REQ_CLIENT1', 'GL1C_PERF_SEL_REQ_CLIENT10', + 'GL1C_PERF_SEL_REQ_CLIENT11', 'GL1C_PERF_SEL_REQ_CLIENT12', + 'GL1C_PERF_SEL_REQ_CLIENT13', 'GL1C_PERF_SEL_REQ_CLIENT14', + 'GL1C_PERF_SEL_REQ_CLIENT15', 'GL1C_PERF_SEL_REQ_CLIENT16', + 'GL1C_PERF_SEL_REQ_CLIENT17', 'GL1C_PERF_SEL_REQ_CLIENT18', + 'GL1C_PERF_SEL_REQ_CLIENT19', 'GL1C_PERF_SEL_REQ_CLIENT2', + 'GL1C_PERF_SEL_REQ_CLIENT20', 'GL1C_PERF_SEL_REQ_CLIENT21', + 'GL1C_PERF_SEL_REQ_CLIENT22', 'GL1C_PERF_SEL_REQ_CLIENT23', + 'GL1C_PERF_SEL_REQ_CLIENT24', 'GL1C_PERF_SEL_REQ_CLIENT25', + 'GL1C_PERF_SEL_REQ_CLIENT26', 'GL1C_PERF_SEL_REQ_CLIENT27', + 'GL1C_PERF_SEL_REQ_CLIENT3', 'GL1C_PERF_SEL_REQ_CLIENT4', + 'GL1C_PERF_SEL_REQ_CLIENT5', 'GL1C_PERF_SEL_REQ_CLIENT6', + 'GL1C_PERF_SEL_REQ_CLIENT7', 'GL1C_PERF_SEL_REQ_CLIENT8', + 'GL1C_PERF_SEL_REQ_CLIENT9', 'GL1C_PERF_SEL_REQ_MISS', + 'GL1C_PERF_SEL_REQ_NOP_ACK', 'GL1C_PERF_SEL_REQ_NOP_RTN0', + 'GL1C_PERF_SEL_REQ_READ', 'GL1C_PERF_SEL_REQ_READ_128B', + 'GL1C_PERF_SEL_REQ_READ_32B', 'GL1C_PERF_SEL_REQ_READ_64B', + 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT', + 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU', + 'GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT', + 'GL1C_PERF_SEL_REQ_SHADER_INV', 'GL1C_PERF_SEL_REQ_WRITE', + 'GL1C_PERF_SEL_REQ_WRITE_32B', 'GL1C_PERF_SEL_REQ_WRITE_64B', + 'GL1C_PERF_SEL_STALL_GCR_INV', 'GL1C_PERF_SEL_STALL_GL2_GL1', + 'GL1C_PERF_SEL_STALL_LFIFO_FULL', + 'GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE', + 'GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC', + 'GL1C_PERF_SEL_STALL_VM', 'GL1C_PERF_SEL_STARVE', + 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', + 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', + 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', + 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', + 'GL1C_PERF_SEL_UTCL0_REQUEST', + 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', + 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', + 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', + 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', + 'GL1H_REQ_PERF_SEL', 'GL1H_REQ_PERF_SEL_ARB_REQUESTS', + 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0', + 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1', 'GL1H_REQ_PERF_SEL_BUSY', + 'GL1H_REQ_PERF_SEL_CYCLE', 'GL1H_REQ_PERF_SEL_REQUEST_GL1_0', + 'GL1H_REQ_PERF_SEL_REQUEST_GL1_1', + 'GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL', + 'GL1H_REQ_PERF_SEL_STALL_GL1_0', 'GL1H_REQ_PERF_SEL_STALL_GL1_1', + 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_0', + 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_1', 'GL1_CACHE_POLICIES', + 'GL1_CACHE_POLICY_HIT_EVICT', 'GL1_CACHE_POLICY_HIT_LRU', + 'GL1_CACHE_POLICY_MISS_EVICT', 'GL1_CACHE_POLICY_MISS_LRU', + 'GL1_CACHE_STORE_POLICIES', 'GL1_CACHE_STORE_POLICY_BYPASS', + 'GL2A_PERF_SEL', 'GL2A_PERF_SEL_BUSY', 'GL2A_PERF_SEL_CYCLE', + 'GL2A_PERF_SEL_NONE', 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', + 'GL2A_PERF_SEL_REQ_BURST_GL2C0', 'GL2A_PERF_SEL_REQ_BURST_GL2C1', + 'GL2A_PERF_SEL_REQ_BURST_GL2C2', 'GL2A_PERF_SEL_REQ_BURST_GL2C3', + 'GL2A_PERF_SEL_REQ_BURST_GL2C4', 'GL2A_PERF_SEL_REQ_BURST_GL2C5', + 'GL2A_PERF_SEL_REQ_BURST_GL2C6', 'GL2A_PERF_SEL_REQ_BURST_GL2C7', + 'GL2A_PERF_SEL_REQ_GL2C0', 'GL2A_PERF_SEL_REQ_GL2C1', + 'GL2A_PERF_SEL_REQ_GL2C2', 'GL2A_PERF_SEL_REQ_GL2C3', + 'GL2A_PERF_SEL_REQ_GL2C4', 'GL2A_PERF_SEL_REQ_GL2C5', + 'GL2A_PERF_SEL_REQ_GL2C6', 'GL2A_PERF_SEL_REQ_GL2C7', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', + 'GL2A_PERF_SEL_REQ_STALL_GL2C0', 'GL2A_PERF_SEL_REQ_STALL_GL2C1', + 'GL2A_PERF_SEL_REQ_STALL_GL2C2', 'GL2A_PERF_SEL_REQ_STALL_GL2C3', + 'GL2A_PERF_SEL_REQ_STALL_GL2C4', 'GL2A_PERF_SEL_REQ_STALL_GL2C5', + 'GL2A_PERF_SEL_REQ_STALL_GL2C6', 'GL2A_PERF_SEL_REQ_STALL_GL2C7', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', + 'GL2A_PERF_SEL_RTN_CLIENT0', 'GL2A_PERF_SEL_RTN_CLIENT1', + 'GL2A_PERF_SEL_RTN_CLIENT10', 'GL2A_PERF_SEL_RTN_CLIENT11', + 'GL2A_PERF_SEL_RTN_CLIENT12', 'GL2A_PERF_SEL_RTN_CLIENT13', + 'GL2A_PERF_SEL_RTN_CLIENT14', 'GL2A_PERF_SEL_RTN_CLIENT15', + 'GL2A_PERF_SEL_RTN_CLIENT2', 'GL2A_PERF_SEL_RTN_CLIENT3', + 'GL2A_PERF_SEL_RTN_CLIENT4', 'GL2A_PERF_SEL_RTN_CLIENT5', + 'GL2A_PERF_SEL_RTN_CLIENT6', 'GL2A_PERF_SEL_RTN_CLIENT7', + 'GL2A_PERF_SEL_RTN_CLIENT8', 'GL2A_PERF_SEL_RTN_CLIENT9', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', + 'GL2A_PERF_SEL_RTN_STALL_GL2C0', 'GL2A_PERF_SEL_RTN_STALL_GL2C1', + 'GL2A_PERF_SEL_RTN_STALL_GL2C2', 'GL2A_PERF_SEL_RTN_STALL_GL2C3', + 'GL2A_PERF_SEL_RTN_STALL_GL2C4', 'GL2A_PERF_SEL_RTN_STALL_GL2C5', + 'GL2A_PERF_SEL_RTN_STALL_GL2C6', 'GL2A_PERF_SEL_RTN_STALL_GL2C7', + 'GL2C_PERF_SEL', 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', + 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', + 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', + 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', + 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', + 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', + 'GL2C_PERF_SEL_ATOMIC', 'GL2C_PERF_SEL_BUBBLE', + 'GL2C_PERF_SEL_BUSY', 'GL2C_PERF_SEL_BYPASS_REQ', + 'GL2C_PERF_SEL_CLIENT0_REQ', 'GL2C_PERF_SEL_CLIENT10_REQ', + 'GL2C_PERF_SEL_CLIENT11_REQ', 'GL2C_PERF_SEL_CLIENT12_REQ', + 'GL2C_PERF_SEL_CLIENT13_REQ', 'GL2C_PERF_SEL_CLIENT14_REQ', + 'GL2C_PERF_SEL_CLIENT15_REQ', 'GL2C_PERF_SEL_CLIENT1_REQ', + 'GL2C_PERF_SEL_CLIENT2_REQ', 'GL2C_PERF_SEL_CLIENT3_REQ', + 'GL2C_PERF_SEL_CLIENT4_REQ', 'GL2C_PERF_SEL_CLIENT5_REQ', + 'GL2C_PERF_SEL_CLIENT6_REQ', 'GL2C_PERF_SEL_CLIENT7_REQ', + 'GL2C_PERF_SEL_CLIENT8_REQ', 'GL2C_PERF_SEL_CLIENT9_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', + 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', + 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ', + 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', + 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', + 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', + 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', + 'GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ', + 'GL2C_PERF_SEL_CM_COMP_READ_REQ', + 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', + 'GL2C_PERF_SEL_CM_DCC_IN_XFC', 'GL2C_PERF_SEL_CM_DCC_OUT_1x1', + 'GL2C_PERF_SEL_CM_DCC_OUT_1x2', 'GL2C_PERF_SEL_CM_DCC_OUT_2x1', + 'GL2C_PERF_SEL_CM_DCC_OUT_2x2', 'GL2C_PERF_SEL_CM_DCC_OUT_CONST', + 'GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP', 'GL2C_PERF_SEL_CM_DCC_OUT_XFC', + 'GL2C_PERF_SEL_CM_DCC_STALL', 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', + 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', + 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', 'GL2C_PERF_SEL_CM_NOOP_REQ', + 'GL2C_PERF_SEL_CM_NO_ACK_REQ', 'GL2C_PERF_SEL_CM_READ_BACK_REQ', + 'GL2C_PERF_SEL_CM_RVF_FULL', 'GL2C_PERF_SEL_CM_SDR_FULL', + 'GL2C_PERF_SEL_CM_WR_ACK_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', 'GL2C_PERF_SEL_CYCLE', + 'GL2C_PERF_SEL_C_RO_S_REQ', 'GL2C_PERF_SEL_C_RO_US_REQ', + 'GL2C_PERF_SEL_C_RW_S_REQ', 'GL2C_PERF_SEL_C_RW_US_REQ', + 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'GL2C_PERF_SEL_EA_ATOMIC', + 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', 'GL2C_PERF_SEL_EA_OUTSTANDING', + 'GL2C_PERF_SEL_EA_RDREQ_128B', 'GL2C_PERF_SEL_EA_RDREQ_32B', + 'GL2C_PERF_SEL_EA_RDREQ_64B', 'GL2C_PERF_SEL_EA_RDREQ_96B', + 'GL2C_PERF_SEL_EA_RDREQ_DRAM', 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', + 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', + 'GL2C_PERF_SEL_EA_RDRET_NACK', + 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', + 'GL2C_PERF_SEL_EA_RD_MDC_32B', 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', + 'GL2C_PERF_SEL_EA_WRREQ_64B', 'GL2C_PERF_SEL_EA_WRREQ_DRAM', + 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', + 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', + 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', 'GL2C_PERF_SEL_EA_WRRET_NACK', + 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', 'GL2C_PERF_SEL_EVICT', + 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', 'GL2C_PERF_SEL_FULL_HIT', + 'GL2C_PERF_SEL_GARLIC_READ', 'GL2C_PERF_SEL_GARLIC_WRITE', + 'GL2C_PERF_SEL_GCR_ALL', 'GL2C_PERF_SEL_GCR_DISCARD', + 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', + 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', + 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', + 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', 'GL2C_PERF_SEL_GCR_INV', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', 'GL2C_PERF_SEL_GCR_MDC_INV', + 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', + 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', 'GL2C_PERF_SEL_GCR_RANGE', + 'GL2C_PERF_SEL_GCR_UNSHARED', 'GL2C_PERF_SEL_GCR_VOL', + 'GL2C_PERF_SEL_GCR_WB', 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', + 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', + 'GL2C_PERF_SEL_GCR_WBINVL2_START', + 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', + 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', 'GL2C_PERF_SEL_GL2A_LEVEL', + 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', 'GL2C_PERF_SEL_HIT', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', + 'GL2C_PERF_SEL_IB_CM_STALL', 'GL2C_PERF_SEL_IB_REQ', + 'GL2C_PERF_SEL_IB_STALL', 'GL2C_PERF_SEL_IB_TAG_STALL', + 'GL2C_PERF_SEL_INTERNAL_PROBE', 'GL2C_PERF_SEL_IO_READ', + 'GL2C_PERF_SEL_IO_WRITE', 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', + 'GL2C_PERF_SEL_LRU_REQ', 'GL2C_PERF_SEL_MC_RDREQ', + 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ', + 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ_STALL', + 'GL2C_PERF_SEL_MDC_INV_METADATA', 'GL2C_PERF_SEL_MDC_LEVEL', + 'GL2C_PERF_SEL_MDC_REQ', 'GL2C_PERF_SEL_MDC_SECTOR_HIT', + 'GL2C_PERF_SEL_MDC_SECTOR_MISS', + 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_MDC_TAG_HIT', + 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', + 'GL2C_PERF_SEL_MDC_TAG_STALL', + 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', + 'GL2C_PERF_SEL_METADATA_READ_REQ', 'GL2C_PERF_SEL_MISS', + 'GL2C_PERF_SEL_NOA_REQ', 'GL2C_PERF_SEL_NONE', + 'GL2C_PERF_SEL_NOP_ACK', 'GL2C_PERF_SEL_NOP_RTN0', + 'GL2C_PERF_SEL_NORMAL_EVICT', 'GL2C_PERF_SEL_NORMAL_WRITEBACK', + 'GL2C_PERF_SEL_ONION_READ', 'GL2C_PERF_SEL_ONION_WRITE', + 'GL2C_PERF_SEL_PARTIAL_32B_HIT', 'GL2C_PERF_SEL_PARTIAL_64B_HIT', + 'GL2C_PERF_SEL_PARTIAL_96B_HIT', 'GL2C_PERF_SEL_PROBE', + 'GL2C_PERF_SEL_PROBE_ALL', 'GL2C_PERF_SEL_PROBE_EVICT', + 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', + 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', + 'GL2C_PERF_SEL_READ', 'GL2C_PERF_SEL_READ_128_REQ', + 'GL2C_PERF_SEL_READ_32_REQ', 'GL2C_PERF_SEL_READ_64_REQ', + 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', 'GL2C_PERF_SEL_REQ', + 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', 'GL2C_PERF_SEL_RETURN_ACK', + 'GL2C_PERF_SEL_RETURN_DATA', 'GL2C_PERF_SEL_SHARED_REQ', + 'GL2C_PERF_SEL_SRC_FIFO_FULL', 'GL2C_PERF_SEL_STREAM_REQ', + 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', + 'GL2C_PERF_SEL_TAG_PROBE_STALL', + 'GL2C_PERF_SEL_TAG_READ_DST_STALL', 'GL2C_PERF_SEL_TAG_STALL', + 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'GL2C_PERF_SEL_UC_REQ', + 'GL2C_PERF_SEL_UNCACHED_WRITE', 'GL2C_PERF_SEL_VOL_REQ', + 'GL2C_PERF_SEL_WRITE', 'GL2C_PERF_SEL_WRITEBACK', + 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 'GL2C_PERF_SEL_WRITE_32_REQ', 'GL2C_PERF_SEL_WRITE_64_REQ', + 'GL2_CACHE_POLICIES', 'GL2_CACHE_POLICY_BYPASS', + 'GL2_CACHE_POLICY_LRU', 'GL2_CACHE_POLICY_NOA', + 'GL2_CACHE_POLICY_STREAM', 'GL2_EA_CID', 'GL2_EA_CID_CLIENT', + 'GL2_EA_CID_CP', 'GL2_EA_CID_CPDMA', 'GL2_EA_CID_DCC', + 'GL2_EA_CID_FMASK', 'GL2_EA_CID_HTILE', 'GL2_EA_CID_MES', + 'GL2_EA_CID_RLC', 'GL2_EA_CID_RT', 'GL2_EA_CID_SDMA', + 'GL2_EA_CID_SQC', 'GL2_EA_CID_TCPMETA', 'GL2_EA_CID_UTCL2', + 'GL2_EA_CID_ZPCPSD', 'GL2_EA_CID_Z_STENCIL', 'GL2_NACKS', + 'GL2_NACK_DATA_ERROR', 'GL2_NACK_NO_FAULT', 'GL2_NACK_PAGE_FAULT', + 'GL2_NACK_PROTECTION_FAULT', 'GL2_OP', 'GL2_OP_ATOMIC_ADD_32', + 'GL2_OP_ATOMIC_ADD_64', 'GL2_OP_ATOMIC_ADD_RTN_32', + 'GL2_OP_ATOMIC_ADD_RTN_64', 'GL2_OP_ATOMIC_AND_32', + 'GL2_OP_ATOMIC_AND_64', 'GL2_OP_ATOMIC_AND_RTN_32', + 'GL2_OP_ATOMIC_AND_RTN_64', 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', + 'GL2_OP_ATOMIC_CMPSWAP_32', 'GL2_OP_ATOMIC_CMPSWAP_64', + 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', + 'GL2_OP_ATOMIC_DEC_32', 'GL2_OP_ATOMIC_DEC_64', + 'GL2_OP_ATOMIC_DEC_RTN_32', 'GL2_OP_ATOMIC_DEC_RTN_64', + 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FCMPSWAP_32', 'GL2_OP_ATOMIC_FCMPSWAP_64', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', + 'GL2_OP_ATOMIC_FMAX_32', 'GL2_OP_ATOMIC_FMAX_64', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FMAX_RTN_32', 'GL2_OP_ATOMIC_FMAX_RTN_64', + 'GL2_OP_ATOMIC_FMIN_32', 'GL2_OP_ATOMIC_FMIN_64', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FMIN_RTN_32', 'GL2_OP_ATOMIC_FMIN_RTN_64', + 'GL2_OP_ATOMIC_INC_32', 'GL2_OP_ATOMIC_INC_64', + 'GL2_OP_ATOMIC_INC_RTN_32', 'GL2_OP_ATOMIC_INC_RTN_64', + 'GL2_OP_ATOMIC_OR_32', 'GL2_OP_ATOMIC_OR_64', + 'GL2_OP_ATOMIC_OR_RTN_32', 'GL2_OP_ATOMIC_OR_RTN_64', + 'GL2_OP_ATOMIC_SMAX_32', 'GL2_OP_ATOMIC_SMAX_64', + 'GL2_OP_ATOMIC_SMAX_RTN_32', 'GL2_OP_ATOMIC_SMAX_RTN_64', + 'GL2_OP_ATOMIC_SMIN_32', 'GL2_OP_ATOMIC_SMIN_64', + 'GL2_OP_ATOMIC_SMIN_RTN_32', 'GL2_OP_ATOMIC_SMIN_RTN_64', + 'GL2_OP_ATOMIC_SUB_32', 'GL2_OP_ATOMIC_SUB_64', + 'GL2_OP_ATOMIC_SUB_RTN_32', 'GL2_OP_ATOMIC_SUB_RTN_64', + 'GL2_OP_ATOMIC_SWAP_32', 'GL2_OP_ATOMIC_SWAP_64', + 'GL2_OP_ATOMIC_SWAP_RTN_32', 'GL2_OP_ATOMIC_SWAP_RTN_64', + 'GL2_OP_ATOMIC_UMAX_32', 'GL2_OP_ATOMIC_UMAX_64', + 'GL2_OP_ATOMIC_UMAX_8', 'GL2_OP_ATOMIC_UMAX_RTN_32', + 'GL2_OP_ATOMIC_UMAX_RTN_64', 'GL2_OP_ATOMIC_UMIN_32', + 'GL2_OP_ATOMIC_UMIN_64', 'GL2_OP_ATOMIC_UMIN_8', + 'GL2_OP_ATOMIC_UMIN_RTN_32', 'GL2_OP_ATOMIC_UMIN_RTN_64', + 'GL2_OP_ATOMIC_XOR_32', 'GL2_OP_ATOMIC_XOR_64', + 'GL2_OP_ATOMIC_XOR_RTN_32', 'GL2_OP_ATOMIC_XOR_RTN_64', + 'GL2_OP_GL1_INV', 'GL2_OP_MASKS', 'GL2_OP_MASK_64', + 'GL2_OP_MASK_FLUSH_DENROM', 'GL2_OP_MASK_NO_RTN', + 'GL2_OP_NOP_ACK', 'GL2_OP_NOP_RTN0', 'GL2_OP_PROBE_FILTER', + 'GL2_OP_READ', 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 'GL2_OP_WRITE', 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', + 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', + 'GLOBAL_STATUS_FLUSH_STATUS', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', + 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', + 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', + 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', + 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', + 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', + 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', + 'GRBM_PERF_SEL_BCI_BUSY', 'GRBM_PERF_SEL_CB_BUSY', + 'GRBM_PERF_SEL_CB_CLEAN', 'GRBM_PERF_SEL_CH_BUSY', + 'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPAXI_BUSY', + 'GRBM_PERF_SEL_CPC_BUSY', 'GRBM_PERF_SEL_CPF_BUSY', + 'GRBM_PERF_SEL_CPG_BUSY', 'GRBM_PERF_SEL_CP_BUSY', + 'GRBM_PERF_SEL_CP_COHER_BUSY', 'GRBM_PERF_SEL_CP_DMA_BUSY', + 'GRBM_PERF_SEL_DB_BUSY', 'GRBM_PERF_SEL_DB_CLEAN', + 'GRBM_PERF_SEL_EA_BUSY', 'GRBM_PERF_SEL_GDS_BUSY', + 'GRBM_PERF_SEL_GE_BUSY', 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', + 'GRBM_PERF_SEL_GL1CC_BUSY', 'GRBM_PERF_SEL_GL1H_BUSY', + 'GRBM_PERF_SEL_GL2CC_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE', + 'GRBM_PERF_SEL_GUS_BUSY', 'GRBM_PERF_SEL_PA_BUSY', + 'GRBM_PERF_SEL_PC_BUSY', 'GRBM_PERF_SEL_PH_BUSY', + 'GRBM_PERF_SEL_PMM_BUSY', 'GRBM_PERF_SEL_RLC_BUSY', + 'GRBM_PERF_SEL_RMI_BUSY', 'GRBM_PERF_SEL_SC_BUSY', + 'GRBM_PERF_SEL_SDMA_BUSY', 'GRBM_PERF_SEL_SPI_BUSY', + 'GRBM_PERF_SEL_SX_BUSY', 'GRBM_PERF_SEL_TA_BUSY', + 'GRBM_PERF_SEL_TCP_BUSY', 'GRBM_PERF_SEL_USER_DEFINED', + 'GRBM_PERF_SEL_UTCL1_BUSY', 'GRBM_PERF_SEL_UTCL2_BUSY', + 'GRBM_SE0_PERF_SEL', 'GRBM_SE0_PERF_SEL_BCI_BUSY', + 'GRBM_SE0_PERF_SEL_CB_BUSY', 'GRBM_SE0_PERF_SEL_CB_CLEAN', + 'GRBM_SE0_PERF_SEL_COUNT', 'GRBM_SE0_PERF_SEL_DB_BUSY', + 'GRBM_SE0_PERF_SEL_DB_CLEAN', 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', + 'GRBM_SE0_PERF_SEL_GL1H_BUSY', 'GRBM_SE0_PERF_SEL_PA_BUSY', + 'GRBM_SE0_PERF_SEL_PC_BUSY', 'GRBM_SE0_PERF_SEL_RMI_BUSY', + 'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY', + 'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY', + 'GRBM_SE0_PERF_SEL_TCP_BUSY', 'GRBM_SE0_PERF_SEL_USER_DEFINED', + 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', 'GRBM_SE1_PERF_SEL', + 'GRBM_SE1_PERF_SEL_BCI_BUSY', 'GRBM_SE1_PERF_SEL_CB_BUSY', + 'GRBM_SE1_PERF_SEL_CB_CLEAN', 'GRBM_SE1_PERF_SEL_COUNT', + 'GRBM_SE1_PERF_SEL_DB_BUSY', 'GRBM_SE1_PERF_SEL_DB_CLEAN', + 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', 'GRBM_SE1_PERF_SEL_GL1H_BUSY', + 'GRBM_SE1_PERF_SEL_PA_BUSY', 'GRBM_SE1_PERF_SEL_PC_BUSY', + 'GRBM_SE1_PERF_SEL_RMI_BUSY', 'GRBM_SE1_PERF_SEL_SC_BUSY', + 'GRBM_SE1_PERF_SEL_SPI_BUSY', 'GRBM_SE1_PERF_SEL_SX_BUSY', + 'GRBM_SE1_PERF_SEL_TA_BUSY', 'GRBM_SE1_PERF_SEL_TCP_BUSY', + 'GRBM_SE1_PERF_SEL_USER_DEFINED', 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', + 'GRBM_SE2_PERF_SEL', 'GRBM_SE2_PERF_SEL_BCI_BUSY', + 'GRBM_SE2_PERF_SEL_CB_BUSY', 'GRBM_SE2_PERF_SEL_CB_CLEAN', + 'GRBM_SE2_PERF_SEL_COUNT', 'GRBM_SE2_PERF_SEL_DB_BUSY', + 'GRBM_SE2_PERF_SEL_DB_CLEAN', 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', + 'GRBM_SE2_PERF_SEL_GL1H_BUSY', 'GRBM_SE2_PERF_SEL_PA_BUSY', + 'GRBM_SE2_PERF_SEL_PC_BUSY', 'GRBM_SE2_PERF_SEL_RMI_BUSY', + 'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY', + 'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY', + 'GRBM_SE2_PERF_SEL_TCP_BUSY', 'GRBM_SE2_PERF_SEL_USER_DEFINED', + 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', 'GRBM_SE3_PERF_SEL', + 'GRBM_SE3_PERF_SEL_BCI_BUSY', 'GRBM_SE3_PERF_SEL_CB_BUSY', + 'GRBM_SE3_PERF_SEL_CB_CLEAN', 'GRBM_SE3_PERF_SEL_COUNT', + 'GRBM_SE3_PERF_SEL_DB_BUSY', 'GRBM_SE3_PERF_SEL_DB_CLEAN', + 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', 'GRBM_SE3_PERF_SEL_GL1H_BUSY', + 'GRBM_SE3_PERF_SEL_PA_BUSY', 'GRBM_SE3_PERF_SEL_PC_BUSY', + 'GRBM_SE3_PERF_SEL_RMI_BUSY', 'GRBM_SE3_PERF_SEL_SC_BUSY', + 'GRBM_SE3_PERF_SEL_SPI_BUSY', 'GRBM_SE3_PERF_SEL_SX_BUSY', + 'GRBM_SE3_PERF_SEL_TA_BUSY', 'GRBM_SE3_PERF_SEL_TCP_BUSY', + 'GRBM_SE3_PERF_SEL_USER_DEFINED', 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', + 'GRBM_SE4_PERF_SEL', 'GRBM_SE4_PERF_SEL_BCI_BUSY', + 'GRBM_SE4_PERF_SEL_CB_BUSY', 'GRBM_SE4_PERF_SEL_CB_CLEAN', + 'GRBM_SE4_PERF_SEL_COUNT', 'GRBM_SE4_PERF_SEL_DB_BUSY', + 'GRBM_SE4_PERF_SEL_DB_CLEAN', 'GRBM_SE4_PERF_SEL_GL1CC_BUSY', + 'GRBM_SE4_PERF_SEL_GL1H_BUSY', 'GRBM_SE4_PERF_SEL_PA_BUSY', + 'GRBM_SE4_PERF_SEL_PC_BUSY', 'GRBM_SE4_PERF_SEL_RMI_BUSY', + 'GRBM_SE4_PERF_SEL_SC_BUSY', 'GRBM_SE4_PERF_SEL_SPI_BUSY', + 'GRBM_SE4_PERF_SEL_SX_BUSY', 'GRBM_SE4_PERF_SEL_TA_BUSY', + 'GRBM_SE4_PERF_SEL_TCP_BUSY', 'GRBM_SE4_PERF_SEL_USER_DEFINED', + 'GRBM_SE4_PERF_SEL_UTCL1_BUSY', 'GRBM_SE5_PERF_SEL', + 'GRBM_SE5_PERF_SEL_BCI_BUSY', 'GRBM_SE5_PERF_SEL_CB_BUSY', + 'GRBM_SE5_PERF_SEL_CB_CLEAN', 'GRBM_SE5_PERF_SEL_COUNT', + 'GRBM_SE5_PERF_SEL_DB_BUSY', 'GRBM_SE5_PERF_SEL_DB_CLEAN', + 'GRBM_SE5_PERF_SEL_GL1CC_BUSY', 'GRBM_SE5_PERF_SEL_GL1H_BUSY', + 'GRBM_SE5_PERF_SEL_PA_BUSY', 'GRBM_SE5_PERF_SEL_PC_BUSY', + 'GRBM_SE5_PERF_SEL_RMI_BUSY', 'GRBM_SE5_PERF_SEL_SC_BUSY', + 'GRBM_SE5_PERF_SEL_SPI_BUSY', 'GRBM_SE5_PERF_SEL_SX_BUSY', + 'GRBM_SE5_PERF_SEL_TA_BUSY', 'GRBM_SE5_PERF_SEL_TCP_BUSY', + 'GRBM_SE5_PERF_SEL_USER_DEFINED', 'GRBM_SE5_PERF_SEL_UTCL1_BUSY', + 'GRBM_SE6_PERF_SEL', 'GRBM_SE6_PERF_SEL_BCI_BUSY', + 'GRBM_SE6_PERF_SEL_CB_BUSY', 'GRBM_SE6_PERF_SEL_CB_CLEAN', + 'GRBM_SE6_PERF_SEL_COUNT', 'GRBM_SE6_PERF_SEL_DB_BUSY', + 'GRBM_SE6_PERF_SEL_DB_CLEAN', 'GRBM_SE6_PERF_SEL_GL1CC_BUSY', + 'GRBM_SE6_PERF_SEL_GL1H_BUSY', 'GRBM_SE6_PERF_SEL_PA_BUSY', + 'GRBM_SE6_PERF_SEL_PC_BUSY', 'GRBM_SE6_PERF_SEL_RMI_BUSY', + 'GRBM_SE6_PERF_SEL_SC_BUSY', 'GRBM_SE6_PERF_SEL_SPI_BUSY', + 'GRBM_SE6_PERF_SEL_SX_BUSY', 'GRBM_SE6_PERF_SEL_TA_BUSY', + 'GRBM_SE6_PERF_SEL_TCP_BUSY', 'GRBM_SE6_PERF_SEL_USER_DEFINED', + 'GRBM_SE6_PERF_SEL_UTCL1_BUSY', 'GRBM_SE7_PERF_SEL', + 'GRBM_SE7_PERF_SEL_BCI_BUSY', 'GRBM_SE7_PERF_SEL_CB_BUSY', + 'GRBM_SE7_PERF_SEL_CB_CLEAN', 'GRBM_SE7_PERF_SEL_COUNT', + 'GRBM_SE7_PERF_SEL_DB_BUSY', 'GRBM_SE7_PERF_SEL_DB_CLEAN', + 'GRBM_SE7_PERF_SEL_GL1CC_BUSY', 'GRBM_SE7_PERF_SEL_GL1H_BUSY', + 'GRBM_SE7_PERF_SEL_PA_BUSY', 'GRBM_SE7_PERF_SEL_PC_BUSY', + 'GRBM_SE7_PERF_SEL_RMI_BUSY', 'GRBM_SE7_PERF_SEL_SC_BUSY', + 'GRBM_SE7_PERF_SEL_SPI_BUSY', 'GRBM_SE7_PERF_SEL_SX_BUSY', + 'GRBM_SE7_PERF_SEL_TA_BUSY', 'GRBM_SE7_PERF_SEL_TCP_BUSY', + 'GRBM_SE7_PERF_SEL_USER_DEFINED', 'GRBM_SE7_PERF_SEL_UTCL1_BUSY', + 'GREEN_LUT', 'GSTHREADID_SIZE', 'GS_OFF', 'GS_SCENARIO_A', + 'GS_SCENARIO_B', 'GS_SCENARIO_C', 'GS_SCENARIO_G', 'GS_STAGE_OFF', + 'GS_STAGE_ON', 'HDMICHARCLK_SRC_SEL', + 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', 'HDMICHARCLK_SRC_SEL_UNIPHYA', + 'HDMICHARCLK_SRC_SEL_UNIPHYB', 'HDMICHARCLK_SRC_SEL_UNIPHYC', + 'HDMICHARCLK_SRC_SEL_UNIPHYD', 'HDMICHARCLK_SRC_SEL_UNIPHYE', + 'HDMISTREAMCLK_DTO_FORCE_DIS', 'HDMISTREAMCLK_SRC_SEL', + 'HDMI_ACP_NOT_SEND', 'HDMI_ACP_PKT_SEND', 'HDMI_ACP_SEND', + 'HDMI_ACR_0_MULTIPLE_RESERVED', 'HDMI_ACR_1_MULTIPLE', + 'HDMI_ACR_2_MULTIPLE', 'HDMI_ACR_3_MULTIPLE_RESERVED', + 'HDMI_ACR_4_MULTIPLE', 'HDMI_ACR_5_MULTIPLE_RESERVED', + 'HDMI_ACR_6_MULTIPLE_RESERVED', 'HDMI_ACR_7_MULTIPLE_RESERVED', + 'HDMI_ACR_AUDIO_PRIORITY', 'HDMI_ACR_CONT', + 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', + 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', + 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', + 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', + 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', + 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', + 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', + 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', + 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', + 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', + 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', + 'HDMI_AUDIO_INFO_SEND', + 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', + 'HDMI_BORROW_MODE', 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE', + 'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE', + 'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 'HDMI_DEEP_COLOR_DEPTH_48BPP', 'HDMI_DEFAULT_PAHSE', + 'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1', + 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK', + 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', + 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', + 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_FRL', + 'HDMI_GC_AVMUTE', 'HDMI_GC_AVMUTE_CONT', + 'HDMI_GC_AVMUTE_CONT_DISABLE', 'HDMI_GC_AVMUTE_CONT_ENABLE', + 'HDMI_GC_AVMUTE_SET', 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', + 'HDMI_GC_CONT_DISABLE', 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', + 'HDMI_GC_PKT_SEND', 'HDMI_GC_SEND', 'HDMI_GENERIC_CONT', + 'HDMI_GENERIC_CONT_DISABLE', 'HDMI_GENERIC_CONT_ENABLE', + 'HDMI_GENERIC_NOT_SEND', 'HDMI_GENERIC_PKT_SEND', + 'HDMI_GENERIC_SEND', 'HDMI_ISRC_CONT', 'HDMI_ISRC_CONT_DISABLE', + 'HDMI_ISRC_CONT_ENABLE', 'HDMI_ISRC_NOT_SEND', + 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', + 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', + 'HDMI_METADATA_ENABLE', 'HDMI_METADATA_NOT_SEND', + 'HDMI_METADATA_PKT_SEND', 'HDMI_MPEG_INFO_CONT', + 'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE', + 'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND', + 'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', + 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', + 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', + 'HDMI_PACKET_LINE_REFERENCE', 'HDMI_PACKING_PHASE_OVERRIDE', + 'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW', + 'HDMI_PKT_LINE_REF_OTGSOF', 'HDMI_PKT_LINE_REF_VSYNC', + 'HDMI_SEND_MAX_AUDIO_PACKETS', 'HDMI_STREAM_ENC_DB_DISABLE', + 'HDMI_STREAM_ENC_DB_DISABLE_CONTROL', 'HDMI_STREAM_ENC_DB_ENABLE', + 'HDMI_STREAM_ENC_DCCG', 'HDMI_STREAM_ENC_DISABLE', + 'HDMI_STREAM_ENC_DISPLAY_PIPE', 'HDMI_STREAM_ENC_DSC_MODE', + 'HDMI_STREAM_ENC_ENABLE', 'HDMI_STREAM_ENC_ENABLE_CONTROL', + 'HDMI_STREAM_ENC_HARDWARE', 'HDMI_STREAM_ENC_NOT_RESET', + 'HDMI_STREAM_ENC_NO_ERROR_OCCURRED', + 'HDMI_STREAM_ENC_ODM_COMBINE_MODE', + 'HDMI_STREAM_ENC_OVERFLOW_OCCURRED', + 'HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR', + 'HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT', + 'HDMI_STREAM_ENC_PIXEL_ENCODING', 'HDMI_STREAM_ENC_PROGRAMMABLE', + 'HDMI_STREAM_ENC_READ_CLOCK_CONTROL', 'HDMI_STREAM_ENC_RESET', + 'HDMI_STREAM_ENC_RESET_CONTROL', 'HDMI_STREAM_ENC_STREAM_ACTIVE', + 'HDMI_STREAM_ENC_UNDERFLOW_OCCURRED', + 'HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE', + 'HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', 'HDMI_TB_ENC_ACP_SEND', + 'HDMI_TB_ENC_ACR_AUDIO_PRIORITY', 'HDMI_TB_ENC_ACR_CONT', + 'HDMI_TB_ENC_ACR_N_MULTIPLE', 'HDMI_TB_ENC_ACR_SELECT', + 'HDMI_TB_ENC_ACR_SEND', 'HDMI_TB_ENC_ACR_SOURCE', + 'HDMI_TB_ENC_AUDIO_INFO_CONT', 'HDMI_TB_ENC_AUDIO_INFO_SEND', + 'HDMI_TB_ENC_CRC_SRC_SEL', 'HDMI_TB_ENC_CRC_TYPE', + 'HDMI_TB_ENC_DEEP_COLOR_DEPTH', 'HDMI_TB_ENC_DEFAULT_PAHSE', + 'HDMI_TB_ENC_DSC_MODE', 'HDMI_TB_ENC_ENABLE', + 'HDMI_TB_ENC_GC_AVMUTE', 'HDMI_TB_ENC_GC_AVMUTE_CONT', + 'HDMI_TB_ENC_GC_CONT', 'HDMI_TB_ENC_GC_SEND', + 'HDMI_TB_ENC_GENERIC_CONT', 'HDMI_TB_ENC_GENERIC_LOCK_DISABLE', + 'HDMI_TB_ENC_GENERIC_LOCK_EN', 'HDMI_TB_ENC_GENERIC_LOCK_ENABLE', + 'HDMI_TB_ENC_GENERIC_SEND', 'HDMI_TB_ENC_ISRC_CONT', + 'HDMI_TB_ENC_ISRC_SEND', 'HDMI_TB_ENC_METADATA_ENABLE', + 'HDMI_TB_ENC_PACKET_LINE_REFERENCE', 'HDMI_TB_ENC_PIXEL_ENCODING', + 'HDMI_TB_ENC_RESET', 'HDMI_TB_ENC_SYNC_PHASE', + 'HDMI_TMDS_OR_DP_8B10B', 'HDP_ENDIAN_8IN16', 'HDP_ENDIAN_8IN32', + 'HDP_ENDIAN_8IN64', 'HDP_ENDIAN_NONE', 'HPD_INT_CONTROL_ACK', + 'HPD_INT_CONTROL_ACK_0', 'HPD_INT_CONTROL_ACK_1', + 'HPD_INT_CONTROL_GEN_INT_ON_CON', + 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', + 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', + 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HPO_SRC0', 'HPO_SRC_RESERVED', + 'HPO_TOP_CLOCK_GATING_DIS', 'HPO_TOP_CLOCK_GATING_DISABLE', + 'HPO_TOP_CLOCK_GATING_EN', + 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', + 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', + 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', + 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', + 'HPO_TOP_PERMANENT_DISPCLK', 'HPO_TOP_PERMANENT_HDMICHARCLK0', + 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', 'HPO_TOP_PERMANENT_SOCCLK', + 'HPO_TOP_REGISTER_GATED_DISPCLK', + 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', + 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', 'HPO_TOP_TEST_CLK_SEL', + 'HPO_TOP_TEST_CLOCK_RESERVED', 'HS_GS', 'HS_STAGE_OFF', + 'HS_STAGE_ON', 'HUBP_BLANK_EN', 'HUBP_BLANK_SW_ASSERT', + 'HUBP_BLANK_SW_DEASSERT', 'HUBP_IN_ACTIVE', 'HUBP_IN_BLANK', + 'HUBP_IN_VBLANK', 'HUBP_MEASURE_WIN_MODE_DCFCLK', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', 'HUBP_NO_OUTSTANDING_REQ', + 'HUBP_SOFT_RESET', 'HUBP_SOFT_RESET_OFF', 'HUBP_SOFT_RESET_ON', + 'HUBP_TTU_DISABLE', 'HUBP_TTU_DISABLED', 'HUBP_TTU_ENABLED', + 'HUBP_VREADY_AT_OR_AFTER_VSYNC', 'HUBP_VTG_SEL', + 'HW_MIRRORING_DISABLE', 'HW_MIRRORING_ENABLE', 'H_MIRROR_EN', + 'Hdp_SurfaceEndian', 'ID_STREAM_DISABLE_ACKED', + 'ID_STREAM_DISABLE_NO_ACK', 'IHC_INTERRUPT_DEST', + 'IHC_INTERRUPT_LINE_STATUS', 'IH_CLIENT_TYPE', + 'IH_CLIENT_TYPE_RESERVED', 'IH_GFX_VMID_CLIENT', + 'IH_INTERFACE_TYPE', 'IH_LEGACY_INTERFACE', 'IH_MM_VMID_CLIENT', + 'IH_MULTI_VMID_CLIENT', 'IH_PERF_SEL', + 'IH_PERF_SEL_BIF_LINE0_FALLING', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', + 'IH_PERF_SEL_BIF_LINE0_RISING', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', + 'IH_PERF_SEL_BUFFER_FIFO_FULL', 'IH_PERF_SEL_BUFFER_IDLE', + 'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT', + 'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT', + 'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT', + 'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT', + 'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT', + 'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT', + 'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT', + 'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT', + 'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT', + 'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT', + 'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT', + 'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT', + 'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT', + 'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT', + 'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT', + 'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT', + 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', 'IH_PERF_SEL_COOKIE_REC_ERROR', + 'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE', + 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', + 'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT', + 'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL', + 'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB0_FULL_VF0', + 'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10', + 'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12', + 'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14', + 'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF2', + 'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF4', + 'IH_PERF_SEL_RB0_FULL_VF5', 'IH_PERF_SEL_RB0_FULL_VF6', + 'IH_PERF_SEL_RB0_FULL_VF7', 'IH_PERF_SEL_RB0_FULL_VF8', + 'IH_PERF_SEL_RB0_FULL_VF9', 'IH_PERF_SEL_RB0_LOAD_RPTR', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB0_OVERFLOW', + 'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1', + 'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11', + 'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13', + 'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15', + 'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF3', + 'IH_PERF_SEL_RB0_OVERFLOW_VF4', 'IH_PERF_SEL_RB0_OVERFLOW_VF5', + 'IH_PERF_SEL_RB0_OVERFLOW_VF6', 'IH_PERF_SEL_RB0_OVERFLOW_VF7', + 'IH_PERF_SEL_RB0_OVERFLOW_VF8', 'IH_PERF_SEL_RB0_OVERFLOW_VF9', + 'IH_PERF_SEL_RB0_RPTR_WRAP', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB1_FULL_VF0', + 'IH_PERF_SEL_RB1_FULL_VF1', 'IH_PERF_SEL_RB1_FULL_VF10', + 'IH_PERF_SEL_RB1_FULL_VF11', 'IH_PERF_SEL_RB1_FULL_VF12', + 'IH_PERF_SEL_RB1_FULL_VF13', 'IH_PERF_SEL_RB1_FULL_VF14', + 'IH_PERF_SEL_RB1_FULL_VF15', 'IH_PERF_SEL_RB1_FULL_VF2', + 'IH_PERF_SEL_RB1_FULL_VF3', 'IH_PERF_SEL_RB1_FULL_VF4', + 'IH_PERF_SEL_RB1_FULL_VF5', 'IH_PERF_SEL_RB1_FULL_VF6', + 'IH_PERF_SEL_RB1_FULL_VF7', 'IH_PERF_SEL_RB1_FULL_VF8', + 'IH_PERF_SEL_RB1_FULL_VF9', 'IH_PERF_SEL_RB1_LOAD_RPTR', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB1_OVERFLOW', + 'IH_PERF_SEL_RB1_OVERFLOW_VF0', 'IH_PERF_SEL_RB1_OVERFLOW_VF1', + 'IH_PERF_SEL_RB1_OVERFLOW_VF10', 'IH_PERF_SEL_RB1_OVERFLOW_VF11', + 'IH_PERF_SEL_RB1_OVERFLOW_VF12', 'IH_PERF_SEL_RB1_OVERFLOW_VF13', + 'IH_PERF_SEL_RB1_OVERFLOW_VF14', 'IH_PERF_SEL_RB1_OVERFLOW_VF15', + 'IH_PERF_SEL_RB1_OVERFLOW_VF2', 'IH_PERF_SEL_RB1_OVERFLOW_VF3', + 'IH_PERF_SEL_RB1_OVERFLOW_VF4', 'IH_PERF_SEL_RB1_OVERFLOW_VF5', + 'IH_PERF_SEL_RB1_OVERFLOW_VF6', 'IH_PERF_SEL_RB1_OVERFLOW_VF7', + 'IH_PERF_SEL_RB1_OVERFLOW_VF8', 'IH_PERF_SEL_RB1_OVERFLOW_VF9', + 'IH_PERF_SEL_RB1_RPTR_WRAP', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB2_FULL_VF0', + 'IH_PERF_SEL_RB2_FULL_VF1', 'IH_PERF_SEL_RB2_FULL_VF10', + 'IH_PERF_SEL_RB2_FULL_VF11', 'IH_PERF_SEL_RB2_FULL_VF12', + 'IH_PERF_SEL_RB2_FULL_VF13', 'IH_PERF_SEL_RB2_FULL_VF14', + 'IH_PERF_SEL_RB2_FULL_VF15', 'IH_PERF_SEL_RB2_FULL_VF2', + 'IH_PERF_SEL_RB2_FULL_VF3', 'IH_PERF_SEL_RB2_FULL_VF4', + 'IH_PERF_SEL_RB2_FULL_VF5', 'IH_PERF_SEL_RB2_FULL_VF6', + 'IH_PERF_SEL_RB2_FULL_VF7', 'IH_PERF_SEL_RB2_FULL_VF8', + 'IH_PERF_SEL_RB2_FULL_VF9', 'IH_PERF_SEL_RB2_LOAD_RPTR', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB2_OVERFLOW', + 'IH_PERF_SEL_RB2_OVERFLOW_VF0', 'IH_PERF_SEL_RB2_OVERFLOW_VF1', + 'IH_PERF_SEL_RB2_OVERFLOW_VF10', 'IH_PERF_SEL_RB2_OVERFLOW_VF11', + 'IH_PERF_SEL_RB2_OVERFLOW_VF12', 'IH_PERF_SEL_RB2_OVERFLOW_VF13', + 'IH_PERF_SEL_RB2_OVERFLOW_VF14', 'IH_PERF_SEL_RB2_OVERFLOW_VF15', + 'IH_PERF_SEL_RB2_OVERFLOW_VF2', 'IH_PERF_SEL_RB2_OVERFLOW_VF3', + 'IH_PERF_SEL_RB2_OVERFLOW_VF4', 'IH_PERF_SEL_RB2_OVERFLOW_VF5', + 'IH_PERF_SEL_RB2_OVERFLOW_VF6', 'IH_PERF_SEL_RB2_OVERFLOW_VF7', + 'IH_PERF_SEL_RB2_OVERFLOW_VF8', 'IH_PERF_SEL_RB2_OVERFLOW_VF9', + 'IH_PERF_SEL_RB2_RPTR_WRAP', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IH_PERF_SEL_SELF_IV_VALID', + 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', + 'IH_REGISTER_WRITE_INTERFACE', 'IH_RING_ID', + 'IH_RING_ID_INTERRUPT', 'IH_RING_ID_REQUEST', + 'IH_RING_ID_RESERVED', 'IH_RING_ID_TRANSLATION', + 'IH_VF_RB_SELECT', 'IH_VF_RB_SELECT_CLIENT_FCN_ID', + 'IH_VF_RB_SELECT_IH_FCN_ID', 'IH_VF_RB_SELECT_PF', + 'IH_VF_RB_SELECT_RESERVED', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_FIFO_ERROR_TYPE', + 'INPUT_INNER_COVERAGE', 'INST_ID_ECC_INTERRUPT_MSG', + 'INST_ID_HOST_REG_TRAP_MSG', 'INST_ID_HW_TRAP', + 'INST_ID_HW_TRAP_GET_TBA', 'INST_ID_KILL_SEQ', + 'INST_ID_PRIV_START', 'INST_ID_SPI_WREXEC', + 'INST_ID_TTRACE_NEW_PC_MSG', 'INTERRUPT_LINE_ASSERTED', + 'INTERRUPT_LINE_NOT_ASSERTED', 'INTERRUPT_SENT_TO_DMCUB', + 'INTERRUPT_SENT_TO_IH', 'INT_DISABLED', 'INT_ENABLED', + 'INT_LEVEL', 'INT_MASK', 'INT_PULSE', 'INVALID_REG_ACCESS_TYPE', + 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', + 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', + 'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'JITTER_REMOVE_DISABLE', + 'LATE_Z', 'LB_ALPHA_DISABLE', 'LB_ALPHA_EN', 'LB_ALPHA_ENABLE', + 'LB_INTERLEAVE_DISABLE', 'LB_INTERLEAVE_EN', + 'LB_INTERLEAVE_ENABLE', 'LB_MEMORY_CONFIG', 'LB_MEMORY_CONFIG_0', + 'LB_MEMORY_CONFIG_1', 'LB_MEMORY_CONFIG_2', 'LB_MEMORY_CONFIG_3', + 'LEGACY_PIPE_INTERLEAVE', 'LEGACY_PIPE_INTERLEAVE_256B', + 'LEGACY_PIPE_INTERLEAVE_512B', 'LINESTRIP', 'LOOSE_PACK', + 'LSDMA_PERF_SEL', 'LSDMA_PERF_SEL_ATCL2_FREE', + 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', + 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', + 'LSDMA_PERF_SEL_ATCL2_RET_ACK', 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', + 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', + 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', + 'LSDMA_PERF_SEL_CE_AFIFO_FULL', 'LSDMA_PERF_SEL_CE_BUSY', + 'LSDMA_PERF_SEL_CE_BUSY_END', 'LSDMA_PERF_SEL_CE_BUSY_START', + 'LSDMA_PERF_SEL_CE_DST_IDLE', 'LSDMA_PERF_SEL_CE_INFO1_FULL', + 'LSDMA_PERF_SEL_CE_INFO_FULL', 'LSDMA_PERF_SEL_CE_IN_IDLE', + 'LSDMA_PERF_SEL_CE_L1_STALL', 'LSDMA_PERF_SEL_CE_L1_WR_VLD', + 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', + 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', + 'LSDMA_PERF_SEL_CE_OUT_IDLE', 'LSDMA_PERF_SEL_CE_RD_STALL', + 'LSDMA_PERF_SEL_CE_RREQ_IDLE', 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', + 'LSDMA_PERF_SEL_CE_WREQ_IDLE', 'LSDMA_PERF_SEL_CE_WR_IDLE', + 'LSDMA_PERF_SEL_CE_WR_STALL', 'LSDMA_PERF_SEL_CMD_OP_END', + 'LSDMA_PERF_SEL_CMD_OP_MATCH', 'LSDMA_PERF_SEL_CMD_OP_START', + 'LSDMA_PERF_SEL_CTX_CHANGE', + 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'LSDMA_PERF_SEL_CYCLE', + 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', + 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', + 'LSDMA_PERF_SEL_DOORBELL', 'LSDMA_PERF_SEL_DRAM_ECC', + 'LSDMA_PERF_SEL_EX_IDLE', + 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'LSDMA_PERF_SEL_F32_L1_WR_VLD', + 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 'LSDMA_PERF_SEL_GFX_SELECT', 'LSDMA_PERF_SEL_IB_CMD_FULL', + 'LSDMA_PERF_SEL_IB_CMD_IDLE', 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_IDLE', + 'LSDMA_PERF_SEL_INT_IDLE', 'LSDMA_PERF_SEL_INT_REQ_COUNT', + 'LSDMA_PERF_SEL_INT_REQ_STALL', + 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', + 'LSDMA_PERF_SEL_INT_RESP_RETRY', + 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', + 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', + 'LSDMA_PERF_SEL_L1_INV_MIDDLE', 'LSDMA_PERF_SEL_L1_RDL2_IDLE', + 'LSDMA_PERF_SEL_L1_RDMC_IDLE', 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', + 'LSDMA_PERF_SEL_L1_RD_INV_EN', 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', + 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', + 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', + 'LSDMA_PERF_SEL_L1_WRL2_IDLE', 'LSDMA_PERF_SEL_L1_WRMC_IDLE', + 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', 'LSDMA_PERF_SEL_L1_WR_INV_EN', + 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', + 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', + 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', + 'LSDMA_PERF_SEL_MC_RD_COUNT', 'LSDMA_PERF_SEL_MC_RD_IDLE', + 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 'LSDMA_PERF_SEL_MC_RD_RET_STALL', 'LSDMA_PERF_SEL_MC_WR_COUNT', + 'LSDMA_PERF_SEL_MC_WR_IDLE', + 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', + 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', + 'LSDMA_PERF_SEL_NACK_GEN_ERR', 'LSDMA_PERF_SEL_NUM_PACKET', + 'LSDMA_PERF_SEL_PAGE_SELECT', 'LSDMA_PERF_SEL_RB_CMD_FULL', + 'LSDMA_PERF_SEL_RB_CMD_IDLE', 'LSDMA_PERF_SEL_RB_EMPTY', + 'LSDMA_PERF_SEL_RB_FULL', 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_RB_RPTR_WB', + 'LSDMA_PERF_SEL_RB_RPTR_WRAP', 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', + 'LSDMA_PERF_SEL_RB_WPTR_WRAP', 'LSDMA_PERF_SEL_RD_BA_RTR', + 'LSDMA_PERF_SEL_REG_IDLE', 'LSDMA_PERF_SEL_RLC0_SELECT', + 'LSDMA_PERF_SEL_RLC1_SELECT', 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', + 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', + 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'LSDMA_PERF_SEL_SEM_IDLE', + 'LSDMA_PERF_SEL_SEM_REQ_COUNT', 'LSDMA_PERF_SEL_SEM_REQ_STALL', + 'LSDMA_PERF_SEL_SEM_RESP_FAIL', + 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 'LSDMA_PERF_SEL_SEM_RESP_PASS', 'LSDMA_PERF_SEL_SRBM_REG_SEND', + 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', + 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', + 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', 'LSDMA_PERF_SEL_WR_BA_RTR', + 'LS_STAGE_OFF', 'LS_STAGE_ON', 'LUT_2CFG_MEMORY_A', + 'LUT_2CFG_MEMORY_B', 'LUT_2CFG_NO_MEMORY', 'LUT_2_MODE_BYPASS', + 'LUT_2_MODE_RAMA_LUT', 'LUT_2_MODE_RAMB_LUT', 'LUT_4CFG_MEMORY_A', + 'LUT_4CFG_MEMORY_B', 'LUT_4CFG_NO_MEMORY', 'LUT_4CFG_ROM_A', + 'LUT_4CFG_ROM_B', 'LUT_4_MODE_BYPASS', 'LUT_4_MODE_RAMA_LUT', + 'LUT_4_MODE_RAMB_LUT', 'LUT_4_MODE_ROMA_LUT', + 'LUT_4_MODE_ROMB_LUT', 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', + 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', + 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', + 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', + 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', + 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', + 'MASTER_UPDATE_LOCK_SEL', 'MASTER_UPDATE_LOCK_SEL_0', + 'MASTER_UPDATE_LOCK_SEL_1', 'MASTER_UPDATE_LOCK_SEL_2', + 'MASTER_UPDATE_LOCK_SEL_3', 'MASTER_UPDATE_LOCK_SEL_RESERVED4', + 'MASTER_UPDATE_LOCK_SEL_RESERVED5', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', + 'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH', 'MEM_ARB_MODE_FIXED', + 'MEM_ARB_MODE_WEIGHT', 'MEM_POWER_DIS_MODE_DISABLE', + 'MEM_POWER_DIS_MODE_ENABLE', 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', + 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', 'MEM_POWER_FORCE_MODE_OFF', + 'MEM_POWER_FORCE_MODE_SHUT_DOWN', 'MEM_POWER_STATUS_DEEP_SLEEP', + 'MEM_POWER_STATUS_LIGHT_SLEEP', 'MEM_POWER_STATUS_ON', + 'MEM_POWER_STATUS_SHUT_DOWN', 'MEM_PWR_DIS_CTRL', + 'MEM_PWR_DIS_MODE', 'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2', + 'MEM_PWR_FORCE_MODE', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2', + 'MEM_PWR_STATUS', 'METADATA_HUBP_SEL', 'METADATA_HUBP_SEL_0', + 'METADATA_HUBP_SEL_1', 'METADATA_HUBP_SEL_2', + 'METADATA_HUBP_SEL_3', 'METADATA_HUBP_SEL_RESERVED', + 'METADATA_STREAM_DP', 'METADATA_STREAM_DVE', + 'METADATA_STREAM_TYPE_SEL', 'META_CHUNK_SIZE', + 'META_CHUNK_SIZE_1KB', 'META_CHUNK_SIZE_2KB', + 'META_CHUNK_SIZE_4KB', 'META_CHUNK_SIZE_8KB', 'META_LINEAR', + 'META_SURF_LINEAR', 'META_SURF_TILED', 'ME_ID0', 'ME_ID1', + 'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', + 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', + 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', + 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MIN_CHUNK_SIZE', + 'MIN_CHUNK_SIZE_1024B', 'MIN_CHUNK_SIZE_256B', + 'MIN_CHUNK_SIZE_512B', 'MIN_META_CHUNK_SIZE', + 'MIN_META_CHUNK_SIZE_128B', 'MIN_META_CHUNK_SIZE_256B', + 'MIN_META_CHUNK_SIZE_64B', 'MONO_10LSB', 'MONO_10MSB', + 'MONO_12LSB', 'MONO_12MSB', 'MONO_16', 'MONO_2BIT', 'MONO_8', + 'MPCC_BG_COLOR_BPC', 'MPCC_BG_COLOR_BPC_10bit', + 'MPCC_BG_COLOR_BPC_11bit', 'MPCC_BG_COLOR_BPC_12bit', + 'MPCC_BG_COLOR_BPC_8bit', 'MPCC_BG_COLOR_BPC_9bit', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', 'MPCC_CONTROL_MPCC_MODE', + 'MPCC_CONTROL_MPCC_MODE_BYPASS', + 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', + 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', + 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', + 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM', + 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', + 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', 'MPCC_GAMUT_REMAP_MODE_0', + 'MPCC_GAMUT_REMAP_MODE_1', 'MPCC_GAMUT_REMAP_MODE_2', + 'MPCC_GAMUT_REMAP_MODE_ENUM', 'MPCC_GAMUT_REMAP_MODE_RSV', + 'MPCC_MCM_3DLUT_17CUBE', 'MPCC_MCM_3DLUT_30BIT', + 'MPCC_MCM_3DLUT_30BIT_ENUM', 'MPCC_MCM_3DLUT_36BIT', + 'MPCC_MCM_3DLUT_9CUBE', 'MPCC_MCM_3DLUT_RAM_SEL', + 'MPCC_MCM_3DLUT_SIZE_ENUM', 'MPCC_MCM_GAMMA_LUT_BYPASS', + 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', + 'MPCC_MCM_GAMMA_LUT_MODE_ENUM', + 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM', 'MPCC_MCM_GAMMA_LUT_RAMA', + 'MPCC_MCM_GAMMA_LUT_RAMB', 'MPCC_MCM_GAMMA_LUT_RAM_LUT', + 'MPCC_MCM_GAMMA_LUT_RESERVED_1', 'MPCC_MCM_GAMMA_LUT_RESERVED_3', + 'MPCC_MCM_GAMMA_LUT_SEL_ENUM', 'MPCC_MCM_LUT_2_MODE_BYPASS', + 'MPCC_MCM_LUT_2_MODE_ENUM', 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', + 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', 'MPCC_MCM_LUT_ALL_USE_R', + 'MPCC_MCM_LUT_BLUE_LUT', 'MPCC_MCM_LUT_CONFIG_MODE', + 'MPCC_MCM_LUT_DIFFERENT_RGB', 'MPCC_MCM_LUT_DISABLE_DEBUG', + 'MPCC_MCM_LUT_ENABLE_DEBUG', 'MPCC_MCM_LUT_GREEN_LUT', + 'MPCC_MCM_LUT_NUM_SEG', 'MPCC_MCM_LUT_RAMA_ACCESS', + 'MPCC_MCM_LUT_RAMB_ACCESS', 'MPCC_MCM_LUT_RAM_SEL', + 'MPCC_MCM_LUT_READ_COLOR_SEL', 'MPCC_MCM_LUT_READ_DBG', + 'MPCC_MCM_LUT_RED_LUT', 'MPCC_MCM_LUT_SEGMENTS_1', + 'MPCC_MCM_LUT_SEGMENTS_128', 'MPCC_MCM_LUT_SEGMENTS_16', + 'MPCC_MCM_LUT_SEGMENTS_2', 'MPCC_MCM_LUT_SEGMENTS_32', + 'MPCC_MCM_LUT_SEGMENTS_4', 'MPCC_MCM_LUT_SEGMENTS_64', + 'MPCC_MCM_LUT_SEGMENTS_8', 'MPCC_MCM_MEM_PWR_FORCE_DIS', + 'MPCC_MCM_MEM_PWR_FORCE_DS', 'MPCC_MCM_MEM_PWR_FORCE_ENUM', + 'MPCC_MCM_MEM_PWR_FORCE_LS', 'MPCC_MCM_MEM_PWR_FORCE_SD', + 'MPCC_MCM_MEM_PWR_STATE_DS', 'MPCC_MCM_MEM_PWR_STATE_ENUM', + 'MPCC_MCM_MEM_PWR_STATE_LS', 'MPCC_MCM_MEM_PWR_STATE_ON', + 'MPCC_MCM_MEM_PWR_STATE_SD', 'MPCC_MCM_RAM0_ACCESS', + 'MPCC_MCM_RAM1_ACCESS', 'MPCC_MCM_RAM2_ACCESS', + 'MPCC_MCM_RAM3_ACCESS', 'MPCC_OGAM_ALL_USE_R', + 'MPCC_OGAM_BLUE_LUT', 'MPCC_OGAM_DIFFERENT_RGB', + 'MPCC_OGAM_DISABLE_DEBUG', 'MPCC_OGAM_DISABLE_PWL', + 'MPCC_OGAM_ENABLE_DEBUG', 'MPCC_OGAM_ENABLE_PWL', + 'MPCC_OGAM_GREEN_LUT', 'MPCC_OGAM_LUT_2CFG_MEMORY_A', + 'MPCC_OGAM_LUT_2CFG_MEMORY_B', 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', + 'MPCC_OGAM_LUT_2_CONFIG_ENUM', 'MPCC_OGAM_LUT_CONFIG_MODE', + 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', + 'MPCC_OGAM_LUT_RAM_SEL', 'MPCC_OGAM_LUT_READ_COLOR_SEL', + 'MPCC_OGAM_LUT_READ_DBG', 'MPCC_OGAM_LUT_SEL_ENUM', + 'MPCC_OGAM_MODE_0', 'MPCC_OGAM_MODE_2', + 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM', 'MPCC_OGAM_MODE_RSV', + 'MPCC_OGAM_MODE_RSV1', 'MPCC_OGAM_NUM_SEG', 'MPCC_OGAM_RAMA', + 'MPCC_OGAM_RAMA_ACCESS', 'MPCC_OGAM_RAMB', + 'MPCC_OGAM_RAMB_ACCESS', 'MPCC_OGAM_RED_LUT', + 'MPCC_OGAM_SEGMENTS_1', 'MPCC_OGAM_SEGMENTS_128', + 'MPCC_OGAM_SEGMENTS_16', 'MPCC_OGAM_SEGMENTS_2', + 'MPCC_OGAM_SEGMENTS_32', 'MPCC_OGAM_SEGMENTS_4', + 'MPCC_OGAM_SEGMENTS_64', 'MPCC_OGAM_SEGMENTS_8', + 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN', + 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', + 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_EN', 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_MODE', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', + 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN', + 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE', + 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', 'MPC_CFG_MPC_TEST_CLK_SEL', + 'MPC_CFG_MPC_TEST_CLK_SEL_0', 'MPC_CFG_MPC_TEST_CLK_SEL_1', + 'MPC_CFG_MPC_TEST_CLK_SEL_2', 'MPC_CFG_MPC_TEST_CLK_SEL_3', + 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN', + 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', + 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', + 'MPC_CRC_CALC_INTERLACE_MODE', 'MPC_CRC_CALC_MODE', + 'MPC_CRC_CALC_STEREO_MODE', 'MPC_CRC_CONTINUOUS_MODE', + 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', + 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', + 'MPC_CRC_INTERLACE_MODE_BOTTOM', 'MPC_CRC_INTERLACE_MODE_TOP', + 'MPC_CRC_ONE_SHOT_MODE', 'MPC_CRC_SOURCE_SELECT', + 'MPC_CRC_SOURCE_SEL_DPP', 'MPC_CRC_SOURCE_SEL_DWB', + 'MPC_CRC_SOURCE_SEL_OPP', 'MPC_CRC_SOURCE_SEL_OTHER', + 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', + 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', + 'MPC_CRC_STEREO_MODE_LEFT', 'MPC_CRC_STEREO_MODE_RIGHT', + 'MPC_DEBUG_BUS1_DATA_SELECT', + 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG', + 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT', + 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV', + 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1', + 'MPC_DEBUG_BUS2_DATA_SELECT', 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC', + 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT', + 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM', + 'MPC_DEBUG_BUS2_DATA_SELECT_RES', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA', + 'MPC_DEBUG_BUS_MPCC_BYTE0', 'MPC_DEBUG_BUS_MPCC_BYTE1', + 'MPC_DEBUG_BUS_MPCC_BYTE2', 'MPC_DEBUG_BUS_MPCC_BYTE3', + 'MPC_DEBUG_BUS_MPCC_BYTE_SELECT', 'MPC_OCSC_COEF_FORMAT', + 'MPC_OCSC_COEF_FORMAT_S2_13', 'MPC_OCSC_COEF_FORMAT_S3_12', + 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN', + 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', + 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', + 'MPC_OUT_CSC_MODE', 'MPC_OUT_CSC_MODE_0', 'MPC_OUT_CSC_MODE_1', + 'MPC_OUT_CSC_MODE_2', 'MPC_OUT_CSC_MODE_RSV', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', + 'MPC_OUT_RATE_CONTROL_DISABLE_SET', + 'MPC_OUT_RATE_CONTROL_SET_DISABLE', + 'MPC_OUT_RATE_CONTROL_SET_ENABLE', + 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', + 'MTYPE', 'MTYPE_CC', 'MTYPE_C_RO_S', 'MTYPE_C_RO_US', + 'MTYPE_C_RW_S', 'MTYPE_C_RW_US', 'MTYPE_NC', 'MTYPE_RESERVED_1', + 'MTYPE_RESERVED_5', 'MTYPE_RESERVED_7', 'MTYPE_UC', 'MTYPE_WC', + 'MULTIPLE_BY1', 'MULTIPLE_BY2', 'MULTIPLE_BY3_RESERVED', + 'MULTIPLE_BY4', 'MULTIPLE_RESERVED', 'MULT_16', 'MULT_8', + 'MemArbMode', 'NON_BYPASS', 'NOT_FORCE_THE_CLOCK_DISABLED', + 'NOT_SENT', 'NO_DIST', 'NO_DIV', 'NO_FORCE', 'NO_FORCE_REQ', + 'NO_FORCE_REQUEST', 'NO_MIN_CHUNK_SIZE', 'NO_MIN_META_CHUNK_SIZE', + 'NO_OUTSTANDING_REQ', 'NUM_SIMD_PER_CU', 'OBUF_BYPASS_DIS', + 'OBUF_BYPASS_EN', 'OBUF_BYPASS_SEL', 'OBUF_FULL', + 'OBUF_FULL_RECOUT', 'OBUF_HALF_RECOUT', + 'OBUF_IS_HALF_RECOUT_WIDTH_SEL', 'OBUF_RECOUT', + 'OBUF_USE_FULL_BUFFER_SEL', 'OFFCHIP_HS_DEALLOC', 'OFF_SEQ', + 'OKAY', 'OKAY_NODATA', 'OMODE_BLEND', 'OMODE_O_THEN_B', + 'OMODE_P_THEN_O_THEN_B', 'OMODE_RESERVED_3', 'ON_SEQ', + 'OPPBUF_DISPLAY_SEGMENTATION', + 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', + 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', + 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', + 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', + 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', + 'OPP_ABM_DEBUG_BUS_SELECT_CONTROL', + 'OPP_DPG_DEBUG_BUS_SELECT_CONTROL', + 'OPP_FMT_DEBUG_BUS_SELECT_CONTROL', + 'OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL', + 'OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL', 'OPP_PIPE_CLOCK_DISABLE', + 'OPP_PIPE_CLOCK_ENABLE', 'OPP_PIPE_CLOCK_ENABLE_CONTROL', + 'OPP_PIPE_CRC_CONT_EN', 'OPP_PIPE_CRC_DISABLE', 'OPP_PIPE_CRC_EN', + 'OPP_PIPE_CRC_ENABLE', 'OPP_PIPE_CRC_INTERLACE_EN', + 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', + 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', + 'OPP_PIPE_CRC_INTERLACE_MODE', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', + 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', 'OPP_PIPE_CRC_MODE_CONTINUOUS', + 'OPP_PIPE_CRC_MODE_ONE_SHOT', 'OPP_PIPE_CRC_ONE_SHOT_PENDING', + 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', + 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', + 'OPP_PIPE_CRC_PIXEL_SELECT', + 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', + 'OPP_PIPE_CRC_SOURCE_SELECT', 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', + 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', 'OPP_PIPE_CRC_STEREO_EN', + 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', + 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', + 'OPP_PIPE_CRC_STEREO_MODE', + 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', + 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', + 'OPP_PIPE_CRC_STEREO_MODE_LEFT', 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', + 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL', + 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', + 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', 'OPP_TEST_CLK_SEL_CONTROL', + 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', + 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', + 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', + 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', + 'OPP_TEST_CLK_SEL_DISPCLK_P', 'OPP_TEST_CLK_SEL_DISPCLK_R', + 'OPP_TEST_CLK_SEL_RESERVED0', 'OPP_TEST_CLK_SEL_RESERVED1', + 'OPP_TEST_CLK_SEL_RESERVED2', 'OPP_TEST_CLK_SEL_RESERVED3', + 'OPP_TOP_CLOCK_DISABLED_STATUS', 'OPP_TOP_CLOCK_ENABLED_STATUS', + 'OPP_TOP_CLOCK_ENABLE_STATUS', 'OPP_TOP_CLOCK_GATING_CONTROL', + 'OPP_TOP_CLOCK_GATING_DISABLED', 'OPP_TOP_CLOCK_GATING_ENABLED', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', + 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX', + 'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT', + 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', + 'OTG_ADD_PIXEL', 'OTG_ADD_PIXEL_FORCE', 'OTG_ADD_PIXEL_NOOP', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', + 'OTG_CONTROL_OTG_MASTER_EN', 'OTG_CONTROL_OTG_MASTER_EN_FALSE', + 'OTG_CONTROL_OTG_MASTER_EN_TRUE', 'OTG_CONTROL_OTG_OUT_MUX', + 'OTG_CONTROL_OTG_OUT_MUX_0', 'OTG_CONTROL_OTG_OUT_MUX_1', + 'OTG_CONTROL_OTG_OUT_MUX_2', 'OTG_CONTROL_OTG_START_POINT_CNTL', + 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', + 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC1_EN', 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', + 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', 'OTG_CRC_CNTL_OTG_CRC_CONT_EN', + 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', + 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', 'OTG_CRC_CNTL_OTG_CRC_EN', + 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', + 'OTG_DIG_UPDATE_VCOUNT_0', 'OTG_DIG_UPDATE_VCOUNT_1', + 'OTG_DIG_UPDATE_VCOUNT_MODE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', + 'OTG_DROP_PIXEL', 'OTG_DROP_PIXEL_FORCE', 'OTG_DROP_PIXEL_NOOP', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', + 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL', + 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL', + 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD', + 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL', + 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', 'OTG_GLOBAL_UPDATE_LOCK_EN', + 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', 'OTG_GSL_MASTER_MODE', + 'OTG_GSL_MASTER_MODE_0', 'OTG_GSL_MASTER_MODE_1', + 'OTG_GSL_MASTER_MODE_2', 'OTG_GSL_MASTER_MODE_3', + 'OTG_HORZ_REPETITION_COUNT', 'OTG_HORZ_REPETITION_COUNT_0', + 'OTG_HORZ_REPETITION_COUNT_1', 'OTG_HORZ_REPETITION_COUNT_10', + 'OTG_HORZ_REPETITION_COUNT_11', 'OTG_HORZ_REPETITION_COUNT_12', + 'OTG_HORZ_REPETITION_COUNT_13', 'OTG_HORZ_REPETITION_COUNT_14', + 'OTG_HORZ_REPETITION_COUNT_15', 'OTG_HORZ_REPETITION_COUNT_2', + 'OTG_HORZ_REPETITION_COUNT_3', 'OTG_HORZ_REPETITION_COUNT_4', + 'OTG_HORZ_REPETITION_COUNT_5', 'OTG_HORZ_REPETITION_COUNT_6', + 'OTG_HORZ_REPETITION_COUNT_7', 'OTG_HORZ_REPETITION_COUNT_8', + 'OTG_HORZ_REPETITION_COUNT_9', 'OTG_H_SYNC_A_POL', + 'OTG_H_SYNC_A_POL_HIGH', 'OTG_H_SYNC_A_POL_LOW', + 'OTG_H_TIMING_DIV_MODE', 'OTG_H_TIMING_DIV_MODE_AUTO', + 'OTG_H_TIMING_DIV_MODE_DIV_BY2', 'OTG_H_TIMING_DIV_MODE_DIV_BY4', + 'OTG_H_TIMING_DIV_MODE_MANUAL', 'OTG_H_TIMING_DIV_MODE_NOAUTO', + 'OTG_H_TIMING_DIV_MODE_NO_DIV', 'OTG_H_TIMING_DIV_MODE_RESERVED', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', + 'OTG_MASTER_UPDATE_LOCK_DB_EN', 'OTG_MASTER_UPDATE_LOCK_DISABLE', + 'OTG_MASTER_UPDATE_LOCK_ENABLE', 'OTG_MASTER_UPDATE_LOCK_GSL_EN', + 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', + 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', + 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', + 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', + 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', + 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL', + 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', + 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGA_FREQUENCY_SELECT', 'OTG_TRIGA_FREQUENCY_SELECT_0', + 'OTG_TRIGA_FREQUENCY_SELECT_1', 'OTG_TRIGA_FREQUENCY_SELECT_2', + 'OTG_TRIGA_FREQUENCY_SELECT_3', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGB_FREQUENCY_SELECT', 'OTG_TRIGB_FREQUENCY_SELECT_0', + 'OTG_TRIGB_FREQUENCY_SELECT_1', 'OTG_TRIGB_FREQUENCY_SELECT_2', + 'OTG_TRIGB_FREQUENCY_SELECT_3', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', + 'OTG_VUPDATE_BLOCK_DISABLE', 'OTG_VUPDATE_BLOCK_DISABLE_OFF', + 'OTG_VUPDATE_BLOCK_DISABLE_ON', 'OTG_V_SYNC_A_POL', + 'OTG_V_SYNC_A_POL_HIGH', 'OTG_V_SYNC_A_POL_LOW', + 'OTG_V_SYNC_MODE', 'OTG_V_SYNC_MODE_HBLANK', + 'OTG_V_SYNC_MODE_HSYNC', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', + 'OUTPUT_LINE', 'OUTPUT_POINT', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OUTSTANDING_REQ', + 'OVERRUN', 'OreoMode', 'PART_FRAC_EVEN', 'PART_FRAC_ODD', + 'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PERFCOUNTER_ACTIVE', + 'PERFCOUNTER_CNT0_STATE', 'PERFCOUNTER_CNT0_STATE_FREEZE', + 'PERFCOUNTER_CNT0_STATE_HW', 'PERFCOUNTER_CNT0_STATE_RESET', + 'PERFCOUNTER_CNT0_STATE_START', 'PERFCOUNTER_CNT1_STATE', + 'PERFCOUNTER_CNT1_STATE_FREEZE', 'PERFCOUNTER_CNT1_STATE_HW', + 'PERFCOUNTER_CNT1_STATE_RESET', 'PERFCOUNTER_CNT1_STATE_START', + 'PERFCOUNTER_CNT2_STATE', 'PERFCOUNTER_CNT2_STATE_FREEZE', + 'PERFCOUNTER_CNT2_STATE_HW', 'PERFCOUNTER_CNT2_STATE_RESET', + 'PERFCOUNTER_CNT2_STATE_START', 'PERFCOUNTER_CNT3_STATE', + 'PERFCOUNTER_CNT3_STATE_FREEZE', 'PERFCOUNTER_CNT3_STATE_HW', + 'PERFCOUNTER_CNT3_STATE_RESET', 'PERFCOUNTER_CNT3_STATE_START', + 'PERFCOUNTER_CNT4_STATE', 'PERFCOUNTER_CNT4_STATE_FREEZE', + 'PERFCOUNTER_CNT4_STATE_HW', 'PERFCOUNTER_CNT4_STATE_RESET', + 'PERFCOUNTER_CNT4_STATE_START', 'PERFCOUNTER_CNT5_STATE', + 'PERFCOUNTER_CNT5_STATE_FREEZE', 'PERFCOUNTER_CNT5_STATE_HW', + 'PERFCOUNTER_CNT5_STATE_RESET', 'PERFCOUNTER_CNT5_STATE_START', + 'PERFCOUNTER_CNT6_STATE', 'PERFCOUNTER_CNT6_STATE_FREEZE', + 'PERFCOUNTER_CNT6_STATE_HW', 'PERFCOUNTER_CNT6_STATE_RESET', + 'PERFCOUNTER_CNT6_STATE_START', 'PERFCOUNTER_CNT7_STATE', + 'PERFCOUNTER_CNT7_STATE_FREEZE', 'PERFCOUNTER_CNT7_STATE_HW', + 'PERFCOUNTER_CNT7_STATE_RESET', 'PERFCOUNTER_CNT7_STATE_START', + 'PERFCOUNTER_CNTL_SEL', 'PERFCOUNTER_CNTL_SEL_0', + 'PERFCOUNTER_CNTL_SEL_1', 'PERFCOUNTER_CNTL_SEL_2', + 'PERFCOUNTER_CNTL_SEL_3', 'PERFCOUNTER_CNTL_SEL_4', + 'PERFCOUNTER_CNTL_SEL_5', 'PERFCOUNTER_CNTL_SEL_6', + 'PERFCOUNTER_CNTL_SEL_7', 'PERFCOUNTER_CNTOFF_START_DIS', + 'PERFCOUNTER_CNTOFF_START_DISABLE', + 'PERFCOUNTER_CNTOFF_START_ENABLE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', + 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', + 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', + 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', + 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', + 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', + 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_HW_STOP1_0', + 'PERFCOUNTER_HW_STOP1_1', 'PERFCOUNTER_HW_STOP1_SEL', + 'PERFCOUNTER_HW_STOP2_0', 'PERFCOUNTER_HW_STOP2_1', + 'PERFCOUNTER_HW_STOP2_SEL', 'PERFCOUNTER_INC_MODE', + 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', + 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', + 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', + 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', + 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', + 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', + 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', + 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', + 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', + 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', + 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', + 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', + 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', + 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', + 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', + 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', + 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', + 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', + 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', + 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', + 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', + 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', + 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', + 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', + 'PERFMON_COUNTER_MODE_ACCUM', + 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 'PERFMON_COUNTER_MODE_DIRTY', + 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', + 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', + 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', + 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', + 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', + 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', + 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', + 'PERFMON_STATE_START', 'PERF_CLIPSM_CULL_PRIMS_CNT', + 'PERF_ENGG_BUSY', 'PERF_ENGG_CSB_DELAY_BIN00', + 'PERF_ENGG_CSB_DELAY_BIN01', 'PERF_ENGG_CSB_DELAY_BIN02', + 'PERF_ENGG_CSB_DELAY_BIN03', 'PERF_ENGG_CSB_DELAY_BIN04', + 'PERF_ENGG_CSB_DELAY_BIN05', 'PERF_ENGG_CSB_DELAY_BIN06', + 'PERF_ENGG_CSB_DELAY_BIN07', 'PERF_ENGG_CSB_DELAY_BIN08', + 'PERF_ENGG_CSB_DELAY_BIN09', 'PERF_ENGG_CSB_DELAY_BIN10', + 'PERF_ENGG_CSB_DELAY_BIN11', 'PERF_ENGG_CSB_DELAY_BIN12', + 'PERF_ENGG_CSB_DELAY_BIN13', 'PERF_ENGG_CSB_DELAY_BIN14', + 'PERF_ENGG_CSB_DELAY_BIN15', 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', + 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', + 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', 'PERF_ENGG_CSB_GE_MEMORY_FULL', + 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', + 'PERF_ENGG_CSB_MACHINE_IS_STARVED', + 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', + 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', + 'PERF_ENGG_CSB_NULL_SUBGROUP', + 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', + 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', 'PERF_ENGG_CSB_SPI_DELAY_BIN00', + 'PERF_ENGG_CSB_SPI_DELAY_BIN01', 'PERF_ENGG_CSB_SPI_DELAY_BIN02', + 'PERF_ENGG_CSB_SPI_DELAY_BIN03', 'PERF_ENGG_CSB_SPI_DELAY_BIN04', + 'PERF_ENGG_CSB_SPI_DELAY_BIN05', 'PERF_ENGG_CSB_SPI_DELAY_BIN06', + 'PERF_ENGG_CSB_SPI_DELAY_BIN07', 'PERF_ENGG_CSB_SPI_DELAY_BIN08', + 'PERF_ENGG_CSB_SPI_DELAY_BIN09', 'PERF_ENGG_CSB_SPI_DELAY_BIN10', + 'PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL', + 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', 'PERF_ENGG_CSB_SPI_MEMORY_FULL', + 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', + 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', + 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', + 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', + 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', + 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', + 'PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', + 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', + 'PERF_ENGG_INDEX_REQ_STARVED', + 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', + 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', + 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', + 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', + 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', + 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', + 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', + 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', + 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', + 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', + 'PERF_ENGG_POS_REQ_STARVED', 'PERF_OUTPUT_PRIM_1_SC', + 'PERF_OUTPUT_PRIM_2_SC', 'PERF_OUTPUT_PRIM_3_SC', + 'PERF_OUTPUT_PRIM_4_SC', 'PERF_PAPC_CCGSM_BUSY', + 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', + 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', + 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', + 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', + 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', + 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', + 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', + 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', + 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', + 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE', + 'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR', + 'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE', + 'PERF_PAPC_PASX_REC_STALLED', + 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', + 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', + 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', + 'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', + 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ', + 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD', + 'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 'PERF_PAPC_PA_INPUT_END_OF_PACKET', + 'PERF_PAPC_PA_INPUT_EVENT_FLAG', + 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', + 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM', + 'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM', + 'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', + 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', + 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', + 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE01_STALLED_SC', + 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE0_STALLED_SC', + 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE1_STALLED_SC', + 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE2_STALLED_SC', + 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', + 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', + 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', 'PERF_PA_PIPE0_SWITCHED_GEN', + 'PERF_PA_PIPE1_SWITCHED_GEN', + 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', 'PERF_PA_VERTEX_FIFO_FULL', + 'PERF_PH_SEND_1_SC', 'PERF_PH_SEND_2_SC', 'PERF_PH_SEND_3_SC', + 'PERF_PH_SEND_4_SC', 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SMALL_PRIM_CULL_PRIM_1X1', 'PERF_SMALL_PRIM_CULL_PRIM_1X2', + 'PERF_SMALL_PRIM_CULL_PRIM_1X3', 'PERF_SMALL_PRIM_CULL_PRIM_1XN', + 'PERF_SMALL_PRIM_CULL_PRIM_2X1', 'PERF_SMALL_PRIM_CULL_PRIM_2X2', + 'PERF_SMALL_PRIM_CULL_PRIM_2X3', 'PERF_SMALL_PRIM_CULL_PRIM_2XN', + 'PERF_SMALL_PRIM_CULL_PRIM_3X1', 'PERF_SMALL_PRIM_CULL_PRIM_3X2', + 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', + 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', + 'PERF_SMALL_PRIM_CULL_PRIM_NX1', 'PERF_SMALL_PRIM_CULL_PRIM_NX2', + 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', + 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', 'PERSISTENT_SPACE_END', + 'PERSISTENT_SPACE_START', 'PHYSYMCLK_FORCE_EN', + 'PHYSYMCLK_FORCE_EN_DISABLE', 'PHYSYMCLK_FORCE_EN_ENABLE', + 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', + 'PHYSYMCLK_FORCE_SRC_SEL', 'PHYSYMCLK_FORCE_SRC_SYMCLK', + 'PHY_CUSTOM_RATE', 'PHY_DP_RATE_10P', 'PHY_DP_RATE_13P5', + 'PHY_DP_RATE_1P62', 'PHY_DP_RATE_20P', 'PHY_DP_RATE_2P16', + 'PHY_DP_RATE_2P43', 'PHY_DP_RATE_2P7', 'PHY_DP_RATE_3P24', + 'PHY_DP_RATE_4P32', 'PHY_DP_RATE_5P4', 'PHY_DP_RATE_8P1', + 'PHY_IF_WIDTH_10BIT', 'PHY_IF_WIDTH_20BIT', 'PHY_IF_WIDTH_40BIT', + 'PHY_IF_WIDTH_80BIT', 'PH_PERFCNT_SEL', + 'PH_PERF_SC0_FIFO_STATUS_0', 'PH_PERF_SC0_FIFO_STATUS_1', + 'PH_PERF_SC0_FIFO_STATUS_2', 'PH_PERF_SC0_FIFO_STATUS_3', + 'PH_PERF_SC1_FIFO_STATUS_0', 'PH_PERF_SC1_FIFO_STATUS_1', + 'PH_PERF_SC1_FIFO_STATUS_2', 'PH_PERF_SC1_FIFO_STATUS_3', + 'PH_PERF_SC2_FIFO_STATUS_0', 'PH_PERF_SC2_FIFO_STATUS_1', + 'PH_PERF_SC2_FIFO_STATUS_2', 'PH_PERF_SC2_FIFO_STATUS_3', + 'PH_PERF_SC3_FIFO_STATUS_0', 'PH_PERF_SC3_FIFO_STATUS_1', + 'PH_PERF_SC3_FIFO_STATUS_2', 'PH_PERF_SC3_FIFO_STATUS_3', + 'PH_PERF_SC4_FIFO_STATUS_0', 'PH_PERF_SC4_FIFO_STATUS_1', + 'PH_PERF_SC4_FIFO_STATUS_2', 'PH_PERF_SC4_FIFO_STATUS_3', + 'PH_PERF_SC5_FIFO_STATUS_0', 'PH_PERF_SC5_FIFO_STATUS_1', + 'PH_PERF_SC5_FIFO_STATUS_2', 'PH_PERF_SC5_FIFO_STATUS_3', + 'PH_PERF_SC6_FIFO_STATUS_0', 'PH_PERF_SC6_FIFO_STATUS_1', + 'PH_PERF_SC6_FIFO_STATUS_2', 'PH_PERF_SC6_FIFO_STATUS_3', + 'PH_PERF_SC7_FIFO_STATUS_0', 'PH_PERF_SC7_FIFO_STATUS_1', + 'PH_PERF_SC7_FIFO_STATUS_2', 'PH_PERF_SC7_FIFO_STATUS_3', + 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC0_ARB_BUSY', + 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA0_EOPG_WE', 'PH_PERF_SEL_SC0_PA0_EOP_WE', + 'PH_PERF_SEL_SC0_PA0_EVENT_WE', 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', 'PH_PERF_SEL_SC0_PA0_FPOV_WE', + 'PH_PERF_SEL_SC0_PA0_LPOV_WE', 'PH_PERF_SEL_SC0_PA0_NULL_WE', + 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA1_EOPG_WE', 'PH_PERF_SEL_SC0_PA1_EOP_WE', + 'PH_PERF_SEL_SC0_PA1_EVENT_WE', 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', 'PH_PERF_SEL_SC0_PA1_FPOV_WE', + 'PH_PERF_SEL_SC0_PA1_LPOV_WE', 'PH_PERF_SEL_SC0_PA1_NULL_WE', + 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA2_EOPG_WE', 'PH_PERF_SEL_SC0_PA2_EOP_WE', + 'PH_PERF_SEL_SC0_PA2_EVENT_WE', 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', 'PH_PERF_SEL_SC0_PA2_FPOV_WE', + 'PH_PERF_SEL_SC0_PA2_LPOV_WE', 'PH_PERF_SEL_SC0_PA2_NULL_WE', + 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA3_EOPG_WE', 'PH_PERF_SEL_SC0_PA3_EOP_WE', + 'PH_PERF_SEL_SC0_PA3_EVENT_WE', 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', 'PH_PERF_SEL_SC0_PA3_FPOV_WE', + 'PH_PERF_SEL_SC0_PA3_LPOV_WE', 'PH_PERF_SEL_SC0_PA3_NULL_WE', + 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA4_EOPG_WE', 'PH_PERF_SEL_SC0_PA4_EOP_WE', + 'PH_PERF_SEL_SC0_PA4_EVENT_WE', 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', 'PH_PERF_SEL_SC0_PA4_FPOV_WE', + 'PH_PERF_SEL_SC0_PA4_LPOV_WE', 'PH_PERF_SEL_SC0_PA4_NULL_WE', + 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA5_EOPG_WE', 'PH_PERF_SEL_SC0_PA5_EOP_WE', + 'PH_PERF_SEL_SC0_PA5_EVENT_WE', 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', 'PH_PERF_SEL_SC0_PA5_FPOV_WE', + 'PH_PERF_SEL_SC0_PA5_LPOV_WE', 'PH_PERF_SEL_SC0_PA5_NULL_WE', + 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA6_EOPG_WE', 'PH_PERF_SEL_SC0_PA6_EOP_WE', + 'PH_PERF_SEL_SC0_PA6_EVENT_WE', 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', 'PH_PERF_SEL_SC0_PA6_FPOV_WE', + 'PH_PERF_SEL_SC0_PA6_LPOV_WE', 'PH_PERF_SEL_SC0_PA6_NULL_WE', + 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA7_EOPG_WE', 'PH_PERF_SEL_SC0_PA7_EOP_WE', + 'PH_PERF_SEL_SC0_PA7_EVENT_WE', 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', 'PH_PERF_SEL_SC0_PA7_FPOV_WE', + 'PH_PERF_SEL_SC0_PA7_LPOV_WE', 'PH_PERF_SEL_SC0_PA7_NULL_WE', + 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC0_SEND', 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC1_ARB_BUSY', + 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA0_EOPG_WE', 'PH_PERF_SEL_SC1_PA0_EOP_WE', + 'PH_PERF_SEL_SC1_PA0_EVENT_WE', 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', 'PH_PERF_SEL_SC1_PA0_FPOV_WE', + 'PH_PERF_SEL_SC1_PA0_LPOV_WE', 'PH_PERF_SEL_SC1_PA0_NULL_WE', + 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA1_EOPG_WE', 'PH_PERF_SEL_SC1_PA1_EOP_WE', + 'PH_PERF_SEL_SC1_PA1_EVENT_WE', 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', 'PH_PERF_SEL_SC1_PA1_FPOV_WE', + 'PH_PERF_SEL_SC1_PA1_LPOV_WE', 'PH_PERF_SEL_SC1_PA1_NULL_WE', + 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA2_EOPG_WE', 'PH_PERF_SEL_SC1_PA2_EOP_WE', + 'PH_PERF_SEL_SC1_PA2_EVENT_WE', 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', 'PH_PERF_SEL_SC1_PA2_FPOV_WE', + 'PH_PERF_SEL_SC1_PA2_LPOV_WE', 'PH_PERF_SEL_SC1_PA2_NULL_WE', + 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA3_EOPG_WE', 'PH_PERF_SEL_SC1_PA3_EOP_WE', + 'PH_PERF_SEL_SC1_PA3_EVENT_WE', 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', 'PH_PERF_SEL_SC1_PA3_FPOV_WE', + 'PH_PERF_SEL_SC1_PA3_LPOV_WE', 'PH_PERF_SEL_SC1_PA3_NULL_WE', + 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA4_EOPG_WE', 'PH_PERF_SEL_SC1_PA4_EOP_WE', + 'PH_PERF_SEL_SC1_PA4_EVENT_WE', 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', 'PH_PERF_SEL_SC1_PA4_FPOV_WE', + 'PH_PERF_SEL_SC1_PA4_LPOV_WE', 'PH_PERF_SEL_SC1_PA4_NULL_WE', + 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA5_EOPG_WE', 'PH_PERF_SEL_SC1_PA5_EOP_WE', + 'PH_PERF_SEL_SC1_PA5_EVENT_WE', 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', 'PH_PERF_SEL_SC1_PA5_FPOV_WE', + 'PH_PERF_SEL_SC1_PA5_LPOV_WE', 'PH_PERF_SEL_SC1_PA5_NULL_WE', + 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA6_EOPG_WE', 'PH_PERF_SEL_SC1_PA6_EOP_WE', + 'PH_PERF_SEL_SC1_PA6_EVENT_WE', 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', 'PH_PERF_SEL_SC1_PA6_FPOV_WE', + 'PH_PERF_SEL_SC1_PA6_LPOV_WE', 'PH_PERF_SEL_SC1_PA6_NULL_WE', + 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA7_EOPG_WE', 'PH_PERF_SEL_SC1_PA7_EOP_WE', + 'PH_PERF_SEL_SC1_PA7_EVENT_WE', 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', 'PH_PERF_SEL_SC1_PA7_FPOV_WE', + 'PH_PERF_SEL_SC1_PA7_LPOV_WE', 'PH_PERF_SEL_SC1_PA7_NULL_WE', + 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC1_SEND', 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC2_ARB_BUSY', + 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA0_EOPG_WE', 'PH_PERF_SEL_SC2_PA0_EOP_WE', + 'PH_PERF_SEL_SC2_PA0_EVENT_WE', 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', 'PH_PERF_SEL_SC2_PA0_FPOV_WE', + 'PH_PERF_SEL_SC2_PA0_LPOV_WE', 'PH_PERF_SEL_SC2_PA0_NULL_WE', + 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA1_EOPG_WE', 'PH_PERF_SEL_SC2_PA1_EOP_WE', + 'PH_PERF_SEL_SC2_PA1_EVENT_WE', 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', 'PH_PERF_SEL_SC2_PA1_FPOV_WE', + 'PH_PERF_SEL_SC2_PA1_LPOV_WE', 'PH_PERF_SEL_SC2_PA1_NULL_WE', + 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA2_EOPG_WE', 'PH_PERF_SEL_SC2_PA2_EOP_WE', + 'PH_PERF_SEL_SC2_PA2_EVENT_WE', 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', 'PH_PERF_SEL_SC2_PA2_FPOV_WE', + 'PH_PERF_SEL_SC2_PA2_LPOV_WE', 'PH_PERF_SEL_SC2_PA2_NULL_WE', + 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA3_EOPG_WE', 'PH_PERF_SEL_SC2_PA3_EOP_WE', + 'PH_PERF_SEL_SC2_PA3_EVENT_WE', 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', 'PH_PERF_SEL_SC2_PA3_FPOV_WE', + 'PH_PERF_SEL_SC2_PA3_LPOV_WE', 'PH_PERF_SEL_SC2_PA3_NULL_WE', + 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA4_EOPG_WE', 'PH_PERF_SEL_SC2_PA4_EOP_WE', + 'PH_PERF_SEL_SC2_PA4_EVENT_WE', 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', 'PH_PERF_SEL_SC2_PA4_FPOV_WE', + 'PH_PERF_SEL_SC2_PA4_LPOV_WE', 'PH_PERF_SEL_SC2_PA4_NULL_WE', + 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA5_EOPG_WE', 'PH_PERF_SEL_SC2_PA5_EOP_WE', + 'PH_PERF_SEL_SC2_PA5_EVENT_WE', 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', 'PH_PERF_SEL_SC2_PA5_FPOV_WE', + 'PH_PERF_SEL_SC2_PA5_LPOV_WE', 'PH_PERF_SEL_SC2_PA5_NULL_WE', + 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA6_EOPG_WE', 'PH_PERF_SEL_SC2_PA6_EOP_WE', + 'PH_PERF_SEL_SC2_PA6_EVENT_WE', 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', 'PH_PERF_SEL_SC2_PA6_FPOV_WE', + 'PH_PERF_SEL_SC2_PA6_LPOV_WE', 'PH_PERF_SEL_SC2_PA6_NULL_WE', + 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA7_EOPG_WE', 'PH_PERF_SEL_SC2_PA7_EOP_WE', + 'PH_PERF_SEL_SC2_PA7_EVENT_WE', 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', 'PH_PERF_SEL_SC2_PA7_FPOV_WE', + 'PH_PERF_SEL_SC2_PA7_LPOV_WE', 'PH_PERF_SEL_SC2_PA7_NULL_WE', + 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC2_SEND', 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC3_ARB_BUSY', + 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA0_EOPG_WE', 'PH_PERF_SEL_SC3_PA0_EOP_WE', + 'PH_PERF_SEL_SC3_PA0_EVENT_WE', 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', 'PH_PERF_SEL_SC3_PA0_FPOV_WE', + 'PH_PERF_SEL_SC3_PA0_LPOV_WE', 'PH_PERF_SEL_SC3_PA0_NULL_WE', + 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA1_EOPG_WE', 'PH_PERF_SEL_SC3_PA1_EOP_WE', + 'PH_PERF_SEL_SC3_PA1_EVENT_WE', 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', 'PH_PERF_SEL_SC3_PA1_FPOV_WE', + 'PH_PERF_SEL_SC3_PA1_LPOV_WE', 'PH_PERF_SEL_SC3_PA1_NULL_WE', + 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA2_EOPG_WE', 'PH_PERF_SEL_SC3_PA2_EOP_WE', + 'PH_PERF_SEL_SC3_PA2_EVENT_WE', 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', 'PH_PERF_SEL_SC3_PA2_FPOV_WE', + 'PH_PERF_SEL_SC3_PA2_LPOV_WE', 'PH_PERF_SEL_SC3_PA2_NULL_WE', + 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA3_EOPG_WE', 'PH_PERF_SEL_SC3_PA3_EOP_WE', + 'PH_PERF_SEL_SC3_PA3_EVENT_WE', 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', 'PH_PERF_SEL_SC3_PA3_FPOV_WE', + 'PH_PERF_SEL_SC3_PA3_LPOV_WE', 'PH_PERF_SEL_SC3_PA3_NULL_WE', + 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA4_EOPG_WE', 'PH_PERF_SEL_SC3_PA4_EOP_WE', + 'PH_PERF_SEL_SC3_PA4_EVENT_WE', 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', 'PH_PERF_SEL_SC3_PA4_FPOV_WE', + 'PH_PERF_SEL_SC3_PA4_LPOV_WE', 'PH_PERF_SEL_SC3_PA4_NULL_WE', + 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA5_EOPG_WE', 'PH_PERF_SEL_SC3_PA5_EOP_WE', + 'PH_PERF_SEL_SC3_PA5_EVENT_WE', 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', 'PH_PERF_SEL_SC3_PA5_FPOV_WE', + 'PH_PERF_SEL_SC3_PA5_LPOV_WE', 'PH_PERF_SEL_SC3_PA5_NULL_WE', + 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA6_EOPG_WE', 'PH_PERF_SEL_SC3_PA6_EOP_WE', + 'PH_PERF_SEL_SC3_PA6_EVENT_WE', 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', 'PH_PERF_SEL_SC3_PA6_FPOV_WE', + 'PH_PERF_SEL_SC3_PA6_LPOV_WE', 'PH_PERF_SEL_SC3_PA6_NULL_WE', + 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA7_EOPG_WE', 'PH_PERF_SEL_SC3_PA7_EOP_WE', + 'PH_PERF_SEL_SC3_PA7_EVENT_WE', 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', 'PH_PERF_SEL_SC3_PA7_FPOV_WE', + 'PH_PERF_SEL_SC3_PA7_LPOV_WE', 'PH_PERF_SEL_SC3_PA7_NULL_WE', + 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC3_SEND', 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC4_ARB_BUSY', + 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA0_EOPG_WE', 'PH_PERF_SEL_SC4_PA0_EOP_WE', + 'PH_PERF_SEL_SC4_PA0_EVENT_WE', 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', 'PH_PERF_SEL_SC4_PA0_FPOV_WE', + 'PH_PERF_SEL_SC4_PA0_LPOV_WE', 'PH_PERF_SEL_SC4_PA0_NULL_WE', + 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA1_EOPG_WE', 'PH_PERF_SEL_SC4_PA1_EOP_WE', + 'PH_PERF_SEL_SC4_PA1_EVENT_WE', 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', 'PH_PERF_SEL_SC4_PA1_FPOV_WE', + 'PH_PERF_SEL_SC4_PA1_LPOV_WE', 'PH_PERF_SEL_SC4_PA1_NULL_WE', + 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA2_EOPG_WE', 'PH_PERF_SEL_SC4_PA2_EOP_WE', + 'PH_PERF_SEL_SC4_PA2_EVENT_WE', 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', 'PH_PERF_SEL_SC4_PA2_FPOV_WE', + 'PH_PERF_SEL_SC4_PA2_LPOV_WE', 'PH_PERF_SEL_SC4_PA2_NULL_WE', + 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA3_EOPG_WE', 'PH_PERF_SEL_SC4_PA3_EOP_WE', + 'PH_PERF_SEL_SC4_PA3_EVENT_WE', 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', 'PH_PERF_SEL_SC4_PA3_FPOV_WE', + 'PH_PERF_SEL_SC4_PA3_LPOV_WE', 'PH_PERF_SEL_SC4_PA3_NULL_WE', + 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA4_EOPG_WE', 'PH_PERF_SEL_SC4_PA4_EOP_WE', + 'PH_PERF_SEL_SC4_PA4_EVENT_WE', 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', 'PH_PERF_SEL_SC4_PA4_FPOV_WE', + 'PH_PERF_SEL_SC4_PA4_LPOV_WE', 'PH_PERF_SEL_SC4_PA4_NULL_WE', + 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA5_EOPG_WE', 'PH_PERF_SEL_SC4_PA5_EOP_WE', + 'PH_PERF_SEL_SC4_PA5_EVENT_WE', 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', 'PH_PERF_SEL_SC4_PA5_FPOV_WE', + 'PH_PERF_SEL_SC4_PA5_LPOV_WE', 'PH_PERF_SEL_SC4_PA5_NULL_WE', + 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA6_EOPG_WE', 'PH_PERF_SEL_SC4_PA6_EOP_WE', + 'PH_PERF_SEL_SC4_PA6_EVENT_WE', 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', 'PH_PERF_SEL_SC4_PA6_FPOV_WE', + 'PH_PERF_SEL_SC4_PA6_LPOV_WE', 'PH_PERF_SEL_SC4_PA6_NULL_WE', + 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA7_EOPG_WE', 'PH_PERF_SEL_SC4_PA7_EOP_WE', + 'PH_PERF_SEL_SC4_PA7_EVENT_WE', 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', 'PH_PERF_SEL_SC4_PA7_FPOV_WE', + 'PH_PERF_SEL_SC4_PA7_LPOV_WE', 'PH_PERF_SEL_SC4_PA7_NULL_WE', + 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC4_SEND', 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC5_ARB_BUSY', + 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA0_EOPG_WE', 'PH_PERF_SEL_SC5_PA0_EOP_WE', + 'PH_PERF_SEL_SC5_PA0_EVENT_WE', 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', 'PH_PERF_SEL_SC5_PA0_FPOV_WE', + 'PH_PERF_SEL_SC5_PA0_LPOV_WE', 'PH_PERF_SEL_SC5_PA0_NULL_WE', + 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA1_EOPG_WE', 'PH_PERF_SEL_SC5_PA1_EOP_WE', + 'PH_PERF_SEL_SC5_PA1_EVENT_WE', 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', 'PH_PERF_SEL_SC5_PA1_FPOV_WE', + 'PH_PERF_SEL_SC5_PA1_LPOV_WE', 'PH_PERF_SEL_SC5_PA1_NULL_WE', + 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA2_EOPG_WE', 'PH_PERF_SEL_SC5_PA2_EOP_WE', + 'PH_PERF_SEL_SC5_PA2_EVENT_WE', 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', 'PH_PERF_SEL_SC5_PA2_FPOV_WE', + 'PH_PERF_SEL_SC5_PA2_LPOV_WE', 'PH_PERF_SEL_SC5_PA2_NULL_WE', + 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA3_EOPG_WE', 'PH_PERF_SEL_SC5_PA3_EOP_WE', + 'PH_PERF_SEL_SC5_PA3_EVENT_WE', 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', 'PH_PERF_SEL_SC5_PA3_FPOV_WE', + 'PH_PERF_SEL_SC5_PA3_LPOV_WE', 'PH_PERF_SEL_SC5_PA3_NULL_WE', + 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA4_EOPG_WE', 'PH_PERF_SEL_SC5_PA4_EOP_WE', + 'PH_PERF_SEL_SC5_PA4_EVENT_WE', 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', 'PH_PERF_SEL_SC5_PA4_FPOV_WE', + 'PH_PERF_SEL_SC5_PA4_LPOV_WE', 'PH_PERF_SEL_SC5_PA4_NULL_WE', + 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA5_EOPG_WE', 'PH_PERF_SEL_SC5_PA5_EOP_WE', + 'PH_PERF_SEL_SC5_PA5_EVENT_WE', 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', 'PH_PERF_SEL_SC5_PA5_FPOV_WE', + 'PH_PERF_SEL_SC5_PA5_LPOV_WE', 'PH_PERF_SEL_SC5_PA5_NULL_WE', + 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA6_EOPG_WE', 'PH_PERF_SEL_SC5_PA6_EOP_WE', + 'PH_PERF_SEL_SC5_PA6_EVENT_WE', 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', 'PH_PERF_SEL_SC5_PA6_FPOV_WE', + 'PH_PERF_SEL_SC5_PA6_LPOV_WE', 'PH_PERF_SEL_SC5_PA6_NULL_WE', + 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA7_EOPG_WE', 'PH_PERF_SEL_SC5_PA7_EOP_WE', + 'PH_PERF_SEL_SC5_PA7_EVENT_WE', 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', 'PH_PERF_SEL_SC5_PA7_FPOV_WE', + 'PH_PERF_SEL_SC5_PA7_LPOV_WE', 'PH_PERF_SEL_SC5_PA7_NULL_WE', + 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC5_SEND', 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC6_ARB_BUSY', + 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA0_EOPG_WE', 'PH_PERF_SEL_SC6_PA0_EOP_WE', + 'PH_PERF_SEL_SC6_PA0_EVENT_WE', 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', 'PH_PERF_SEL_SC6_PA0_FPOV_WE', + 'PH_PERF_SEL_SC6_PA0_LPOV_WE', 'PH_PERF_SEL_SC6_PA0_NULL_WE', + 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA1_EOPG_WE', 'PH_PERF_SEL_SC6_PA1_EOP_WE', + 'PH_PERF_SEL_SC6_PA1_EVENT_WE', 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', 'PH_PERF_SEL_SC6_PA1_FPOV_WE', + 'PH_PERF_SEL_SC6_PA1_LPOV_WE', 'PH_PERF_SEL_SC6_PA1_NULL_WE', + 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA2_EOPG_WE', 'PH_PERF_SEL_SC6_PA2_EOP_WE', + 'PH_PERF_SEL_SC6_PA2_EVENT_WE', 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', 'PH_PERF_SEL_SC6_PA2_FPOV_WE', + 'PH_PERF_SEL_SC6_PA2_LPOV_WE', 'PH_PERF_SEL_SC6_PA2_NULL_WE', + 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA3_EOPG_WE', 'PH_PERF_SEL_SC6_PA3_EOP_WE', + 'PH_PERF_SEL_SC6_PA3_EVENT_WE', 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', 'PH_PERF_SEL_SC6_PA3_FPOV_WE', + 'PH_PERF_SEL_SC6_PA3_LPOV_WE', 'PH_PERF_SEL_SC6_PA3_NULL_WE', + 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA4_EOPG_WE', 'PH_PERF_SEL_SC6_PA4_EOP_WE', + 'PH_PERF_SEL_SC6_PA4_EVENT_WE', 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', 'PH_PERF_SEL_SC6_PA4_FPOV_WE', + 'PH_PERF_SEL_SC6_PA4_LPOV_WE', 'PH_PERF_SEL_SC6_PA4_NULL_WE', + 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA5_EOPG_WE', 'PH_PERF_SEL_SC6_PA5_EOP_WE', + 'PH_PERF_SEL_SC6_PA5_EVENT_WE', 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', 'PH_PERF_SEL_SC6_PA5_FPOV_WE', + 'PH_PERF_SEL_SC6_PA5_LPOV_WE', 'PH_PERF_SEL_SC6_PA5_NULL_WE', + 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA6_EOPG_WE', 'PH_PERF_SEL_SC6_PA6_EOP_WE', + 'PH_PERF_SEL_SC6_PA6_EVENT_WE', 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', 'PH_PERF_SEL_SC6_PA6_FPOV_WE', + 'PH_PERF_SEL_SC6_PA6_LPOV_WE', 'PH_PERF_SEL_SC6_PA6_NULL_WE', + 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA7_EOPG_WE', 'PH_PERF_SEL_SC6_PA7_EOP_WE', + 'PH_PERF_SEL_SC6_PA7_EVENT_WE', 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', 'PH_PERF_SEL_SC6_PA7_FPOV_WE', + 'PH_PERF_SEL_SC6_PA7_LPOV_WE', 'PH_PERF_SEL_SC6_PA7_NULL_WE', + 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC6_SEND', 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC7_ARB_BUSY', + 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA0_EOPG_WE', 'PH_PERF_SEL_SC7_PA0_EOP_WE', + 'PH_PERF_SEL_SC7_PA0_EVENT_WE', 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', 'PH_PERF_SEL_SC7_PA0_FPOV_WE', + 'PH_PERF_SEL_SC7_PA0_LPOV_WE', 'PH_PERF_SEL_SC7_PA0_NULL_WE', + 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA1_EOPG_WE', 'PH_PERF_SEL_SC7_PA1_EOP_WE', + 'PH_PERF_SEL_SC7_PA1_EVENT_WE', 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', 'PH_PERF_SEL_SC7_PA1_FPOV_WE', + 'PH_PERF_SEL_SC7_PA1_LPOV_WE', 'PH_PERF_SEL_SC7_PA1_NULL_WE', + 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA2_EOPG_WE', 'PH_PERF_SEL_SC7_PA2_EOP_WE', + 'PH_PERF_SEL_SC7_PA2_EVENT_WE', 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', 'PH_PERF_SEL_SC7_PA2_FPOV_WE', + 'PH_PERF_SEL_SC7_PA2_LPOV_WE', 'PH_PERF_SEL_SC7_PA2_NULL_WE', + 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA3_EOPG_WE', 'PH_PERF_SEL_SC7_PA3_EOP_WE', + 'PH_PERF_SEL_SC7_PA3_EVENT_WE', 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', 'PH_PERF_SEL_SC7_PA3_FPOV_WE', + 'PH_PERF_SEL_SC7_PA3_LPOV_WE', 'PH_PERF_SEL_SC7_PA3_NULL_WE', + 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA4_EOPG_WE', 'PH_PERF_SEL_SC7_PA4_EOP_WE', + 'PH_PERF_SEL_SC7_PA4_EVENT_WE', 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', 'PH_PERF_SEL_SC7_PA4_FPOV_WE', + 'PH_PERF_SEL_SC7_PA4_LPOV_WE', 'PH_PERF_SEL_SC7_PA4_NULL_WE', + 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA5_EOPG_WE', 'PH_PERF_SEL_SC7_PA5_EOP_WE', + 'PH_PERF_SEL_SC7_PA5_EVENT_WE', 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', 'PH_PERF_SEL_SC7_PA5_FPOV_WE', + 'PH_PERF_SEL_SC7_PA5_LPOV_WE', 'PH_PERF_SEL_SC7_PA5_NULL_WE', + 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA6_EOPG_WE', 'PH_PERF_SEL_SC7_PA6_EOP_WE', + 'PH_PERF_SEL_SC7_PA6_EVENT_WE', 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', 'PH_PERF_SEL_SC7_PA6_FPOV_WE', + 'PH_PERF_SEL_SC7_PA6_LPOV_WE', 'PH_PERF_SEL_SC7_PA6_NULL_WE', + 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA7_EOPG_WE', 'PH_PERF_SEL_SC7_PA7_EOP_WE', + 'PH_PERF_SEL_SC7_PA7_EVENT_WE', 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', 'PH_PERF_SEL_SC7_PA7_FPOV_WE', + 'PH_PERF_SEL_SC7_PA7_LPOV_WE', 'PH_PERF_SEL_SC7_PA7_NULL_WE', + 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC7_SEND', 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', + 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', + 'PH_SPI_MODE_DISABLED', 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', + 'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ALIGNED', + 'PIPE_ALIGNED_SURF', 'PIPE_COMPAT_LEVEL', 'PIPE_ID0', 'PIPE_ID1', + 'PIPE_ID2', 'PIPE_ID3', 'PIPE_INT_MASK_MODE', + 'PIPE_INT_MASK_MODE_DISABLE', 'PIPE_INT_MASK_MODE_ENABLE', + 'PIPE_INT_TYPE_MODE', 'PIPE_INT_TYPE_MODE_DISABLE', + 'PIPE_INT_TYPE_MODE_ENABLE', 'PIPE_IN_FLUSH_URGENT', + 'PIPE_IN_FLUSH_URGENT_DISABLE', 'PIPE_IN_FLUSH_URGENT_ENABLE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 'PIPE_PIXEL_RATE_PLL_SOURCE', + 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', + 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', + 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIPE_UNALIGNED_SURF', + 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE', 'PIXEL_PIPE_OCCLUSION_COUNT_0', + 'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2', + 'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', + 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', + 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', + 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', + 'PIX_DYNAMIC_EXPANSION', 'PIX_EXPAND_MODE', 'PIX_ZERO_EXPANSION', + 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', + 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET', + 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST', + 'POWER_STATE_ENUM', 'POWER_STATE_ENUM_DS', 'POWER_STATE_ENUM_LS', + 'POWER_STATE_ENUM_ON', 'POWER_STATE_ENUM_SD', 'PRE_CSC_BYPASS', + 'PRE_CSC_MODE_ENUM', 'PRE_CSC_SET_A', 'PRE_CSC_SET_B', + 'PRE_DEGAM_BT2020', 'PRE_DEGAM_BT2100HLG', 'PRE_DEGAM_BT2100PQ', + 'PRE_DEGAM_BYPASS', 'PRE_DEGAM_ENABLE', 'PRE_DEGAM_GAMMA_22', + 'PRE_DEGAM_GAMMA_24', 'PRE_DEGAM_GAMMA_26', 'PRE_DEGAM_MODE', + 'PRE_DEGAM_SELECT', 'PRE_DEGAM_SRGB', 'PROG_SEQ', 'PROTVIOL', + 'PRQ_MRQ_FLUSH_URGENT', 'PRQ_MRQ_FLUSH_URGENT_DISABLE', + 'PRQ_MRQ_FLUSH_URGENT_ENABLE', 'PS', 'PSLC_ASAP', 'PSLC_AUTO', + 'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PS_DONE', + 'PS_PARTIAL_FLUSH', 'PTE_BUFFER_MODE', 'PTE_BUFFER_MODE_0', + 'PTE_BUFFER_MODE_1', 'PTE_ROW_HEIGHT_LINEAR', + 'PTE_ROW_HEIGHT_LINEAR_1024L', 'PTE_ROW_HEIGHT_LINEAR_128L', + 'PTE_ROW_HEIGHT_LINEAR_16L', 'PTE_ROW_HEIGHT_LINEAR_256L', + 'PTE_ROW_HEIGHT_LINEAR_32L', 'PTE_ROW_HEIGHT_LINEAR_512L', + 'PTE_ROW_HEIGHT_LINEAR_64L', 'PTE_ROW_HEIGHT_LINEAR_8L', + 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN', + 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT', + 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN', + 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', + 'PWRSEQ_BL_PWM_DISABLE', 'PWRSEQ_BL_PWM_ENABLE', + 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', + 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', + 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', + 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', + 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', + 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', + 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 'PWRSEQ_BL_PWM_GRP1_REG_LOCK', + 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', + 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', + 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START', + 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', + 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', + 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', + 'PWRSEQ_GPIO_MASK_EN', 'PWRSEQ_GPIO_MASK_EN_HARDWARE', + 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', 'PWRSEQ_PANEL_BLON_OFF', + 'PWRSEQ_PANEL_BLON_ON', 'PWRSEQ_PANEL_BLON_POL_INVERT', + 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', 'PWRSEQ_PANEL_DIGON_OFF', + 'PWRSEQ_PANEL_DIGON_ON', 'PWRSEQ_PANEL_DIGON_POL_INVERT', + 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE', + 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN', + 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', + 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', + 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', + 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', + 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', + 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', 'PerfCounter_Vals', + 'PhSPIstatusMode', 'PixelPipeCounterId', 'PixelPipeStride', + 'PkrMap', 'PkrXsel', 'PkrXsel2', 'PkrYsel', 'RAMA', 'RAMA_ACCESS', + 'RAMB', 'RAMB_ACCESS', 'RAM_LUT', 'RANGE_00', 'RANGE_FF', + 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', + 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', + 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', + 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', + 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', + 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', + 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', + 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', + 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', + 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', + 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', + 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', + 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', + 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', + 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', + 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', + 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', + 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', + 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', + 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', + 'RASTER_CONFIG_SE_PAIR_MAP_3', + 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', + 'RDPCSPIPE_APBCLK_DISABLE', 'RDPCSPIPE_APBCLK_ENABLE', + 'RDPCSPIPE_APB_PSLVERR_MASK_DISABLE', + 'RDPCSPIPE_APB_PSLVERR_MASK_ENABLE', + 'RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS', + 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN', + 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN', + 'RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET', + 'RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET', + 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK', + 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE', + 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE', + 'RDPCSPIPE_DBG_OCLA_SEL', 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0', + 'RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE', + 'RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE', + 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE', + 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE', + 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE', + 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE', + 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE', + 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE', + 'RDPCSPIPE_ENC_TYPE', 'RDPCSPIPE_EXT_PCLK_EN_DISABLE', + 'RDPCSPIPE_EXT_PCLK_EN_ENABLE', 'RDPCSPIPE_FIFO_EMPTY', + 'RDPCSPIPE_FIFO_FULL', 'RDPCSPIPE_FIFO_IS_EMPTY', + 'RDPCSPIPE_FIFO_IS_FULL', 'RDPCSPIPE_FIFO_NOT_EMPTY', + 'RDPCSPIPE_FIFO_NOT_FULL', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK', + 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE', + 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE', + 'RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE', + 'RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE', + 'RDPCSPIPE_MEM_PWR_DEEP_SLEEP', 'RDPCSPIPE_MEM_PWR_LIGHT_SLEEP', + 'RDPCSPIPE_MEM_PWR_NO_FORCE', + 'RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP', + 'RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP', + 'RDPCSPIPE_MEM_PWR_PWR_STATE_ON', + 'RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN', + 'RDPCSPIPE_MEM_PWR_SHUT_DOWN', + 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK', + 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE', + 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE', + 'RDPCSPIPE_PACK_MODE', 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL', + 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL', + 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE', + 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE', + 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE', + 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV', + 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV', + 'RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', + 'RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL', + 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT', + 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE', + 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH', + 'RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE', + 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC', + 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB', + 'RDPCSPIPE_PHY_CR_PARA_SEL_CR', 'RDPCSPIPE_PHY_CR_PARA_SEL_JTAG', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8', + 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT', + 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT', + 'RDPCSPIPE_PHY_DP_TX_RATE', 'RDPCSPIPE_PHY_DP_TX_RATE_DIV2', + 'RDPCSPIPE_PHY_DP_TX_RATE_DIV4', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54', + 'RDPCSPIPE_PHY_DP_TX_WIDTH_10', 'RDPCSPIPE_PHY_DP_TX_WIDTH_16', + 'RDPCSPIPE_PHY_DP_TX_WIDTH_20', 'RDPCSPIPE_PHY_DP_TX_WIDTH_8', + 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', + 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', + 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', + 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', + 'RDPCSPIPE_PHY_IF_WIDTH', 'RDPCSPIPE_PHY_RATE', + 'RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE', + 'RDPCSPIPE_PHY_REF_ALT_CLK_EN', + 'RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE', 'RDPCSPIPE_PHY_REF_RANGE_0', + 'RDPCSPIPE_PHY_REF_RANGE_1', 'RDPCSPIPE_PHY_REF_RANGE_2', + 'RDPCSPIPE_PHY_REF_RANGE_3', 'RDPCSPIPE_PHY_REF_RANGE_4', + 'RDPCSPIPE_PHY_REF_RANGE_5', 'RDPCSPIPE_PHY_REF_RANGE_6', + 'RDPCSPIPE_PHY_REF_RANGE_7', + 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE', + 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE', + 'RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE', + 'RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE', + 'RDPCSPIPE_SRAMCLK_DISABLE', 'RDPCSPIPE_SRAMCLK_ENABLE', + 'RDPCSPIPE_SRAMCLK_GATE_DISABLE', 'RDPCSPIPE_SRAMCLK_GATE_ENABLE', + 'RDPCSPIPE_SRAMCLK_NOT_PASS', 'RDPCSPIPE_SRAMCLK_PASS', + 'RDPCSPIPE_SRAM_EXT_LD_DONE', 'RDPCSPIPE_SRAM_EXT_LD_NOT_DONE', + 'RDPCSPIPE_SRAM_INIT_DONE', 'RDPCSPIPE_SRAM_INIT_NOT_DONE', + 'RDPCSPIPE_SRAM_SRAM_RESET_DISABLE', + 'RDPCSPIPE_SRAM_SRAM_RESET_ENABLE', + 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF', + 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON', 'RDPCSPIPE_TEST_CLK_SEL', + 'RDPCSPIPE_TEST_CLK_SEL_CFGCLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_NONE', + 'RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk', + 'RDPCSPIPE_TEST_CLK_SEL_SRAMCLK', + 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', + 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', + 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', + 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', + 'RDPCSPIPE_TEST_CLK_SEL_dtb_out0', + 'RDPCSPIPE_TEST_CLK_SEL_dtb_out1', 'RDPCS_PIPE_CLK_CLOCK_OFF', + 'RDPCS_PIPE_CLK_CLOCK_ON', 'RDPCS_PIPE_CLK_DISABLE', + 'RDPCS_PIPE_CLK_ENABLE', 'RDPCS_PIPE_CLK_GATE_DISABLE', + 'RDPCS_PIPE_CLK_GATE_ENABLE', + 'RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB', + 'RDPCS_PIPE_FIFO_DISABLE', 'RDPCS_PIPE_FIFO_ENABLE', + 'RDPCS_PIPE_FIFO_LANE_DISABLE', 'RDPCS_PIPE_FIFO_LANE_ENABLE', + 'RDPCS_PIPE_PHYD32CLK_CLOCK_OFF', 'RDPCS_PIPE_PHYD32CLK_CLOCK_ON', + 'RDPCS_PIPE_SOFT_RESET_DISABLE', 'RDPCS_PIPE_SOFT_RESET_ENABLE', + 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE', + 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE', 'READ_SEQ', + 'RECTLIST', 'RECT_2D', 'RED_LUT', 'REFER_TO_DP_SOF', + 'REFER_TO_OTG_SOF', 'REG_SECURE_VIOLATE_READ', + 'REG_SECURE_VIOLATE_WRITE', 'REG_UNALLOCATED_ADDR_READ', + 'REG_UNALLOCATED_ADDR_WRITE', 'REG_VIRTUAL_READ', + 'REG_VIRTUAL_WRITE', 'RESERVED_1', 'RESERVED_10', 'RESERVED_11', + 'RESERVED_20', 'RESERVED_21', 'RESERVED_22', 'RESERVED_23', + 'RESERVED_3', 'RESERVED_32', 'RESERVED_33', 'RESERVED_34', + 'RESERVED_35', 'RESERVED_44', 'RESERVED_45', 'RESERVED_46', + 'RESERVED_47', 'RESERVED_56', 'RESERVED_57', 'RESERVED_58', + 'RESERVED_59', 'RESERVED_60', 'RESERVED_61', 'RESERVED_62', + 'RESERVED_63', 'RESERVED_72', 'RESERVED_73', 'RESERVED_74', + 'RESERVED_75', 'RESERVED_8', 'RESERVED_84', 'RESERVED_85', + 'RESERVED_86', 'RESERVED_87', 'RESERVED_88', 'RESERVED_89', + 'RESERVED_9', 'RESERVED_90', 'RESERVED_91', 'RESERVED_ES', + 'RESERVED_LS', 'RESERVED_RDPOLICY', 'RESERVED_VS', + 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RESPONSE_STATUS', 'RE_Z', + 'RGB111110_FIX', 'RGB111110_FLOAT', 'RGB565', 'RGBA1010102', + 'RGBA16161616_10LSB', 'RGBA16161616_10MSB', 'RGBA16161616_12LSB', + 'RGBA16161616_12MSB', 'RGBA16161616_FLOAT', 'RGBA16161616_SNORM', + 'RGBA16161616_UNORM', 'RGBA4444', 'RGBA5551', 'RGBA8888', 'RGBE', + 'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RLC_DOORBELL_MODE', 'RLC_DOORBELL_MODE_DISABLE', + 'RLC_DOORBELL_MODE_ENABLE', 'RLC_DOORBELL_MODE_ENABLE_PF', + 'RLC_DOORBELL_MODE_ENABLE_PF_VF', 'RLC_PERFCOUNTER_SEL', + 'RLC_PERFMON_STATE', 'RLC_PERFMON_STATE_DISABLE', + 'RLC_PERFMON_STATE_ENABLE', 'RLC_PERFMON_STATE_RESERVED_3', + 'RLC_PERFMON_STATE_RESERVED_4', 'RLC_PERFMON_STATE_RESERVED_5', + 'RLC_PERFMON_STATE_RESERVED_6', 'RLC_PERFMON_STATE_RESET', + 'RLC_PERFMON_STATE_ROLLOVER', 'RLC_PERF_SEL_CP_INTERRUPT', + 'RLC_PERF_SEL_GRBM_INTERRUPT', 'RLC_PERF_SEL_IH_INTERRUPT', + 'RLC_PERF_SEL_POWER_FEATURE_0', 'RLC_PERF_SEL_POWER_FEATURE_1', + 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', 'RLC_PERF_SEL_SPM_INTERRUPT', + 'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC', + 'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z', + 'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', 'ROM_SIGNATURE', + 'ROTATE_0_DEGREES', 'ROTATE_180_DEGREES', 'ROTATE_270_DEGREES', + 'ROTATE_90_DEGREES', 'ROTATION_ANGLE', 'ROW_TTU_MODE', + 'RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK', + 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD', + 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF', + 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN', + 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP', 'RSPM_CMD', + 'RSPM_CMD_CALIBRATE', 'RSPM_CMD_FORCE_SAMPLE', 'RSPM_CMD_IDLE', + 'RSPM_CMD_INVALID', 'RSPM_CMD_PERF_RESET', 'RSPM_CMD_PERF_SAMPLE', + 'RSPM_CMD_PROF_START', 'RSPM_CMD_PROF_STOP', 'RSPM_CMD_SPM_RESET', + 'RSPM_CMD_SPM_START', 'RSPM_CMD_SPM_STOP', 'RST_PIX_CNT', + 'RSV_TAG_RAM', 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', + 'ReadPolicy', 'Reserved_0x00', 'Reserved_0x09', + 'RingCounterControl', 'SAMPLE_PIPELINESTAT', + 'SAMPLE_STREAMOUTSTATS', 'SAMPLE_STREAMOUTSTATS1', + 'SAMPLE_STREAMOUTSTATS2', 'SAMPLE_STREAMOUTSTATS3', + 'SCL_2TAP_HARDCODE', 'SCL_ALPHA_COEF', 'SCL_ALPHA_COEF_FIRST', + 'SCL_ALPHA_COEF_SECOND', 'SCL_AUTOCAL_MODE', 'SCL_BOUNDARY', + 'SCL_BOUNDARY_BLACK', 'SCL_BOUNDARY_EDGE', 'SCL_CHROMA_COEF', + 'SCL_CHROMA_COEF_FIRST', 'SCL_CHROMA_COEF_SECOND', + 'SCL_COEF_2TAP_HARDCODE_OFF', 'SCL_COEF_2TAP_HARDCODE_ON', + 'SCL_COEF_CHROMA_HORZ_FILTER', 'SCL_COEF_CHROMA_VERT_FILTER', + 'SCL_COEF_FILTER_TYPE_SEL', 'SCL_COEF_LUMA_HORZ_FILTER', + 'SCL_COEF_LUMA_VERT_FILTER', 'SCL_COEF_RAM_SEL', + 'SCL_COEF_RAM_SEL_0', 'SCL_COEF_RAM_SEL_1', 'SCL_SHARP_DISABLE', + 'SCL_SHARP_EN', 'SCL_SHARP_ENABLE', 'SC_BACKEND_BUSY', + 'SC_BACKEND_PRIM_FIFO_FULL', 'SC_BB_DISCARD', + 'SC_BCI_CREDIT_AT_MAX', 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', + 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_BCI_SEND', + 'SC_BM_BE0_STALLED', 'SC_BM_BE1_STALLED', 'SC_BM_BE2_STALLED', + 'SC_BM_BE3_STALLED', 'SC_BM_BUSY', + 'SC_BM_MULTI_ACCUM_1_BE_STALLED', + 'SC_BM_MULTI_ACCUM_2_BE_STALLED', + 'SC_BM_MULTI_ACCUM_3_BE_STALLED', + 'SC_BM_MULTI_ACCUM_4_BE_STALLED', 'SC_BUSY_CNT_NOT_ZERO', + 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', 'SC_DB0_QUAD_INTF_BUSY', + 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', 'SC_DB0_QUAD_INTF_IDLE', + 'SC_DB0_QUAD_INTF_SEND', 'SC_DB0_QUAD_INTF_STALLED_BY_DB', + 'SC_DB0_TILE_INTERFACE_BUSY', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'SC_DB0_TILE_INTERFACE_SEND', 'SC_DB0_TILE_INTERFACE_SEND_EVENT', + 'SC_DB0_TILE_INTERFACE_SEND_SOP', + 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 'SC_DB0_TILE_MASK_FIFO_FULL', + 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', + 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 'SC_DB1_QUAD_INTF_BUSY', 'SC_DB1_QUAD_INTF_CREDIT_AT_MAX', + 'SC_DB1_QUAD_INTF_IDLE', 'SC_DB1_QUAD_INTF_SEND', + 'SC_DB1_QUAD_INTF_STALLED_BY_DB', 'SC_DB1_TILE_INTERFACE_BUSY', + 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', + 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'SC_DB1_TILE_INTERFACE_SEND', 'SC_DB1_TILE_INTERFACE_SEND_EVENT', + 'SC_DB1_TILE_INTERFACE_SEND_SOP', + 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 'SC_DB1_TILE_MASK_FIFO_FULL', + 'SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL', + 'SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX', + 'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX', + 'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_EOP_SYNC_WINDOW', + 'SC_FSR_WALKED', 'SC_FULL_FULL_QUAD', 'SC_FULL_HALF_QUAD', + 'SC_FULL_QTR_QUAD', 'SC_GRP0_DYN_SCLK_BUSY', + 'SC_GRP1_DYN_SCLK_BUSY', 'SC_GRP2_DYN_SCLK_BUSY', + 'SC_GRP3_DYN_SCLK_BUSY', 'SC_GRP4_DYN_SCLK_BUSY', + 'SC_GRP5_DYN_SCLK_BUSY', 'SC_GRP6_DYN_SCLK_BUSY', + 'SC_GRP7_DYN_SCLK_BUSY', 'SC_GRP8_DYN_SCLK_BUSY', + 'SC_GRP9_DYN_SCLK_BUSY', 'SC_HALF_FULL_QUAD', 'SC_HALF_HALF_QUAD', + 'SC_HALF_LSB', 'SC_HALF_QTR_QUAD', 'SC_LSB_ONE_SIDED', + 'SC_LSB_TWO_SIDED', 'SC_MULTICYCLE_BUBBLE_FREEZE', + 'SC_P0_DETAIL_QUAD_COUNT', 'SC_P0_DETAIL_QUAD_WITH_1_PIX', + 'SC_P0_DETAIL_QUAD_WITH_2_PIX', 'SC_P0_DETAIL_QUAD_WITH_3_PIX', + 'SC_P0_DETAIL_QUAD_WITH_4_PIX', 'SC_P0_HIZ_QUAD_COUNT', + 'SC_P0_HIZ_QUAD_PER_TILE_H0', 'SC_P0_HIZ_QUAD_PER_TILE_H1', + 'SC_P0_HIZ_QUAD_PER_TILE_H10', 'SC_P0_HIZ_QUAD_PER_TILE_H11', + 'SC_P0_HIZ_QUAD_PER_TILE_H12', 'SC_P0_HIZ_QUAD_PER_TILE_H13', + 'SC_P0_HIZ_QUAD_PER_TILE_H14', 'SC_P0_HIZ_QUAD_PER_TILE_H15', + 'SC_P0_HIZ_QUAD_PER_TILE_H16', 'SC_P0_HIZ_QUAD_PER_TILE_H2', + 'SC_P0_HIZ_QUAD_PER_TILE_H3', 'SC_P0_HIZ_QUAD_PER_TILE_H4', + 'SC_P0_HIZ_QUAD_PER_TILE_H5', 'SC_P0_HIZ_QUAD_PER_TILE_H6', + 'SC_P0_HIZ_QUAD_PER_TILE_H7', 'SC_P0_HIZ_QUAD_PER_TILE_H8', + 'SC_P0_HIZ_QUAD_PER_TILE_H9', 'SC_P0_HIZ_TILE_COUNT', + 'SC_P1_DETAIL_QUAD_COUNT', 'SC_P1_DETAIL_QUAD_WITH_1_PIX', + 'SC_P1_DETAIL_QUAD_WITH_2_PIX', 'SC_P1_DETAIL_QUAD_WITH_3_PIX', + 'SC_P1_DETAIL_QUAD_WITH_4_PIX', 'SC_P1_HIZ_QUAD_COUNT', + 'SC_P1_HIZ_QUAD_PER_TILE_H0', 'SC_P1_HIZ_QUAD_PER_TILE_H1', + 'SC_P1_HIZ_QUAD_PER_TILE_H10', 'SC_P1_HIZ_QUAD_PER_TILE_H11', + 'SC_P1_HIZ_QUAD_PER_TILE_H12', 'SC_P1_HIZ_QUAD_PER_TILE_H13', + 'SC_P1_HIZ_QUAD_PER_TILE_H14', 'SC_P1_HIZ_QUAD_PER_TILE_H15', + 'SC_P1_HIZ_QUAD_PER_TILE_H16', 'SC_P1_HIZ_QUAD_PER_TILE_H2', + 'SC_P1_HIZ_QUAD_PER_TILE_H3', 'SC_P1_HIZ_QUAD_PER_TILE_H4', + 'SC_P1_HIZ_QUAD_PER_TILE_H5', 'SC_P1_HIZ_QUAD_PER_TILE_H6', + 'SC_P1_HIZ_QUAD_PER_TILE_H7', 'SC_P1_HIZ_QUAD_PER_TILE_H8', + 'SC_P1_HIZ_QUAD_PER_TILE_H9', 'SC_P1_HIZ_TILE_COUNT', + 'SC_P2_DETAIL_QUAD_COUNT', 'SC_P2_DETAIL_QUAD_WITH_1_PIX', + 'SC_P2_DETAIL_QUAD_WITH_2_PIX', 'SC_P2_DETAIL_QUAD_WITH_3_PIX', + 'SC_P2_DETAIL_QUAD_WITH_4_PIX', 'SC_P2_HIZ_QUAD_COUNT', + 'SC_P2_HIZ_QUAD_PER_TILE_H0', 'SC_P2_HIZ_QUAD_PER_TILE_H1', + 'SC_P2_HIZ_QUAD_PER_TILE_H10', 'SC_P2_HIZ_QUAD_PER_TILE_H11', + 'SC_P2_HIZ_QUAD_PER_TILE_H12', 'SC_P2_HIZ_QUAD_PER_TILE_H13', + 'SC_P2_HIZ_QUAD_PER_TILE_H14', 'SC_P2_HIZ_QUAD_PER_TILE_H15', + 'SC_P2_HIZ_QUAD_PER_TILE_H16', 'SC_P2_HIZ_QUAD_PER_TILE_H2', + 'SC_P2_HIZ_QUAD_PER_TILE_H3', 'SC_P2_HIZ_QUAD_PER_TILE_H4', + 'SC_P2_HIZ_QUAD_PER_TILE_H5', 'SC_P2_HIZ_QUAD_PER_TILE_H6', + 'SC_P2_HIZ_QUAD_PER_TILE_H7', 'SC_P2_HIZ_QUAD_PER_TILE_H8', + 'SC_P2_HIZ_QUAD_PER_TILE_H9', 'SC_P2_HIZ_TILE_COUNT', + 'SC_P3_DETAIL_QUAD_COUNT', 'SC_P3_DETAIL_QUAD_WITH_1_PIX', + 'SC_P3_DETAIL_QUAD_WITH_2_PIX', 'SC_P3_DETAIL_QUAD_WITH_3_PIX', + 'SC_P3_DETAIL_QUAD_WITH_4_PIX', 'SC_P3_HIZ_QUAD_COUNT', + 'SC_P3_HIZ_QUAD_PER_TILE_H0', 'SC_P3_HIZ_QUAD_PER_TILE_H1', + 'SC_P3_HIZ_QUAD_PER_TILE_H10', 'SC_P3_HIZ_QUAD_PER_TILE_H11', + 'SC_P3_HIZ_QUAD_PER_TILE_H12', 'SC_P3_HIZ_QUAD_PER_TILE_H13', + 'SC_P3_HIZ_QUAD_PER_TILE_H14', 'SC_P3_HIZ_QUAD_PER_TILE_H15', + 'SC_P3_HIZ_QUAD_PER_TILE_H16', 'SC_P3_HIZ_QUAD_PER_TILE_H2', + 'SC_P3_HIZ_QUAD_PER_TILE_H3', 'SC_P3_HIZ_QUAD_PER_TILE_H4', + 'SC_P3_HIZ_QUAD_PER_TILE_H5', 'SC_P3_HIZ_QUAD_PER_TILE_H6', + 'SC_P3_HIZ_QUAD_PER_TILE_H7', 'SC_P3_HIZ_QUAD_PER_TILE_H8', + 'SC_P3_HIZ_QUAD_PER_TILE_H9', 'SC_P3_HIZ_TILE_COUNT', + 'SC_PA0_SC_DATA_FIFO_EOPG_RD', 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE', + 'SC_PA0_SC_DEALLOC_0_RD', 'SC_PA0_SC_DEALLOC_1_RD', + 'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE', 'SC_PA0_SC_EVENT_WE', + 'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE', + 'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE', + 'SC_PA1_SC_DATA_FIFO_EOPG_RD', 'SC_PA1_SC_DATA_FIFO_EOP_RD', + 'SC_PA1_SC_DATA_FIFO_RD', 'SC_PA1_SC_DATA_FIFO_WE', + 'SC_PA1_SC_DEALLOC_0_RD', 'SC_PA1_SC_DEALLOC_1_RD', + 'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', 'SC_PA1_SC_EVENT_WE', + 'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE', + 'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE', + 'SC_PA2_SC_DATA_FIFO_EOPG_RD', 'SC_PA2_SC_DATA_FIFO_EOP_RD', + 'SC_PA2_SC_DATA_FIFO_RD', 'SC_PA2_SC_DATA_FIFO_WE', + 'SC_PA2_SC_DEALLOC_0_RD', 'SC_PA2_SC_DEALLOC_1_RD', + 'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', 'SC_PA2_SC_EVENT_WE', + 'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE', + 'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE', + 'SC_PA3_SC_DATA_FIFO_EOPG_RD', 'SC_PA3_SC_DATA_FIFO_EOP_RD', + 'SC_PA3_SC_DATA_FIFO_RD', 'SC_PA3_SC_DATA_FIFO_WE', + 'SC_PA3_SC_DEALLOC_0_RD', 'SC_PA3_SC_DEALLOC_1_RD', + 'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', 'SC_PA3_SC_EVENT_WE', + 'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE', + 'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE', + 'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE', + 'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE', + 'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE', + 'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE', + 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', + 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', + 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', + 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', + 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', + 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', + 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', + 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', + 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', + 'SC_PBB_BUSY_AND_NO_SENDS', + 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', 'SC_PBB_END_OF_BATCH', + 'SC_PBB_END_OF_BIN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', + 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', + 'SC_PBB_RESERVED', 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', + 'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT', + 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', + 'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', + 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', + 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', + 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', + 'SC_PKR_WAVE_BREAK_FULL_TILE', 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', + 'SC_PK_BUSY', 'SC_PK_DEALLOC_WAVE_BREAK', + 'SC_PK_MAX_DEALLOC_FORCE_EOV', 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', + 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', + 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', + 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', + 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', + 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', + 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', + 'SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H', + 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', + 'SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 'SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H', + 'SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', + 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', + 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', + 'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS', + 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', + 'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP', + 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', + 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', + 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', + 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', + 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', + 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', + 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_ENG_MULTICYCLE_BUBBLE', + 'SC_PS_PA0_SC_FIFO_EMPTY', 'SC_PS_PA0_SC_FIFO_FULL', + 'SC_PS_PA1_SC_FIFO_EMPTY', 'SC_PS_PA1_SC_FIFO_FULL', + 'SC_PS_PA2_SC_FIFO_EMPTY', 'SC_PS_PA2_SC_FIFO_FULL', + 'SC_PS_PA3_SC_FIFO_EMPTY', 'SC_PS_PA3_SC_FIFO_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', + 'SC_PS_PM_PFF_PW_FULL', 'SC_PS_PM_ZFF_PW_FULL', + 'SC_PS_TO_BE_SCLK_GATE_STALL', 'SC_PS_TS_EVENT_FIFO_POP', + 'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_PW_BM_PASS_EMPTY_PRIM', + 'SC_QTR_FULL_QUAD', 'SC_QTR_HALF_QUAD', 'SC_QTR_QTR_QUAD', + 'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0', + 'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10', + 'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12', + 'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14', + 'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16', + 'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3', + 'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5', + 'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7', + 'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9', + 'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT', + 'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZ1_QUAD_COUNT', + 'SC_QZ1_QUAD_PER_TILE_H0', 'SC_QZ1_QUAD_PER_TILE_H1', + 'SC_QZ1_QUAD_PER_TILE_H10', 'SC_QZ1_QUAD_PER_TILE_H11', + 'SC_QZ1_QUAD_PER_TILE_H12', 'SC_QZ1_QUAD_PER_TILE_H13', + 'SC_QZ1_QUAD_PER_TILE_H14', 'SC_QZ1_QUAD_PER_TILE_H15', + 'SC_QZ1_QUAD_PER_TILE_H16', 'SC_QZ1_QUAD_PER_TILE_H2', + 'SC_QZ1_QUAD_PER_TILE_H3', 'SC_QZ1_QUAD_PER_TILE_H4', + 'SC_QZ1_QUAD_PER_TILE_H5', 'SC_QZ1_QUAD_PER_TILE_H6', + 'SC_QZ1_QUAD_PER_TILE_H7', 'SC_QZ1_QUAD_PER_TILE_H8', + 'SC_QZ1_QUAD_PER_TILE_H9', 'SC_QZ1_TILE_COUNT', + 'SC_QZ1_TILE_COVERED_COUNT', 'SC_QZ1_TILE_NOT_COVERED_COUNT', + 'SC_QZ2_QUAD_COUNT', 'SC_QZ2_QUAD_PER_TILE_H0', + 'SC_QZ2_QUAD_PER_TILE_H1', 'SC_QZ2_QUAD_PER_TILE_H10', + 'SC_QZ2_QUAD_PER_TILE_H11', 'SC_QZ2_QUAD_PER_TILE_H12', + 'SC_QZ2_QUAD_PER_TILE_H13', 'SC_QZ2_QUAD_PER_TILE_H14', + 'SC_QZ2_QUAD_PER_TILE_H15', 'SC_QZ2_QUAD_PER_TILE_H16', + 'SC_QZ2_QUAD_PER_TILE_H2', 'SC_QZ2_QUAD_PER_TILE_H3', + 'SC_QZ2_QUAD_PER_TILE_H4', 'SC_QZ2_QUAD_PER_TILE_H5', + 'SC_QZ2_QUAD_PER_TILE_H6', 'SC_QZ2_QUAD_PER_TILE_H7', + 'SC_QZ2_QUAD_PER_TILE_H8', 'SC_QZ2_QUAD_PER_TILE_H9', + 'SC_QZ2_TILE_COUNT', 'SC_QZ2_TILE_COVERED_COUNT', + 'SC_QZ2_TILE_NOT_COVERED_COUNT', 'SC_QZ3_QUAD_COUNT', + 'SC_QZ3_QUAD_PER_TILE_H0', 'SC_QZ3_QUAD_PER_TILE_H1', + 'SC_QZ3_QUAD_PER_TILE_H10', 'SC_QZ3_QUAD_PER_TILE_H11', + 'SC_QZ3_QUAD_PER_TILE_H12', 'SC_QZ3_QUAD_PER_TILE_H13', + 'SC_QZ3_QUAD_PER_TILE_H14', 'SC_QZ3_QUAD_PER_TILE_H15', + 'SC_QZ3_QUAD_PER_TILE_H16', 'SC_QZ3_QUAD_PER_TILE_H2', + 'SC_QZ3_QUAD_PER_TILE_H3', 'SC_QZ3_QUAD_PER_TILE_H4', + 'SC_QZ3_QUAD_PER_TILE_H5', 'SC_QZ3_QUAD_PER_TILE_H6', + 'SC_QZ3_QUAD_PER_TILE_H7', 'SC_QZ3_QUAD_PER_TILE_H8', + 'SC_QZ3_QUAD_PER_TILE_H9', 'SC_QZ3_TILE_COUNT', + 'SC_QZ3_TILE_COVERED_COUNT', 'SC_QZ3_TILE_NOT_COVERED_COUNT', + 'SC_QZQP_WINDOW_VALID', 'SC_QZQP_WINDOW_VALID_BUSY', + 'SC_REG_SCLK_BUSY', 'SC_RESERVED_0', 'SC_RESERVED_1', + 'SC_RESERVED_2', 'SC_RESERVED_3', 'SC_SCB_BUSY', + 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', + 'SC_SEND_DB_VPZ', 'SC_SPIBC_FULL_FREEZE', 'SC_SPI_CREDIT_AT_MAX', + 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', + 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_SPI_DEALLOC_0_0', + 'SC_SPI_DEALLOC_0_1', 'SC_SPI_DEALLOC_0_2', 'SC_SPI_DEALLOC_1_0', + 'SC_SPI_DEALLOC_1_1', 'SC_SPI_DEALLOC_1_2', 'SC_SPI_DEALLOC_2_0', + 'SC_SPI_DEALLOC_2_1', 'SC_SPI_DEALLOC_2_2', 'SC_SPI_DEALLOC_3_0', + 'SC_SPI_DEALLOC_3_1', 'SC_SPI_DEALLOC_3_2', 'SC_SPI_EVENT', + 'SC_SPI_FPOV_0', 'SC_SPI_FPOV_1', 'SC_SPI_FPOV_2', + 'SC_SPI_FPOV_3', 'SC_SPI_SEND', 'SC_SRPS_WINDOW_VALID', + 'SC_SRPS_WINDOW_VALID_BUSY', 'SC_STALLED_BY_BCI', + 'SC_STALLED_BY_DB0_TILEFIFO', 'SC_STALLED_BY_DB1_TILEFIFO', + 'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE', + 'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO', + 'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO', + 'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD', + 'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 'SC_SUPERTILE_COUNT', + 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', + 'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1', + 'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11', + 'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13', + 'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15', + 'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2', + 'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4', + 'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6', + 'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8', + 'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0', + 'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10', + 'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12', + 'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14', + 'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16', + 'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3', + 'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5', + 'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7', + 'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9', + 'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1', + 'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11', + 'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13', + 'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15', + 'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2', + 'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4', + 'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6', + 'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8', + 'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1', + 'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', 'SC_TILE_PICKED_H4', + 'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY', + 'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY', 'SC_UR_1X', + 'SC_UR_2X', 'SC_UR_4X', 'SC_UR_8X', 'SC_VRS_COMB_MODE_MAX', + 'SC_VRS_COMB_MODE_MIN', 'SC_VRS_COMB_MODE_OVERRIDE', + 'SC_VRS_COMB_MODE_PASSTHRU', 'SC_VRS_COMB_MODE_SATURATE', + 'SDMA_PERFMON_SEL', 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', + 'SDMA_PERFMON_SEL_CE_DST_IDLE', 'SDMA_PERFMON_SEL_CE_INFO1_FULL', + 'SDMA_PERFMON_SEL_CE_INFO_FULL', 'SDMA_PERFMON_SEL_CE_IN_IDLE', + 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', 'SDMA_PERFMON_SEL_CE_OUT_IDLE', + 'SDMA_PERFMON_SEL_CE_RD_STALL', 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', + 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', + 'SDMA_PERFMON_SEL_CE_WR_IDLE', 'SDMA_PERFMON_SEL_CE_WR_STALL', + 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', 'SDMA_PERFMON_SEL_CTX_CHANGE', + 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', + 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERFMON_SEL_CYCLE', + 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', + 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', + 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', + 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', 'SDMA_PERFMON_SEL_DOORBELL', + 'SDMA_PERFMON_SEL_EX_IDLE', + 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'SDMA_PERFMON_SEL_F32_L1_WR_VLD', 'SDMA_PERFMON_SEL_GCR_RTN', + 'SDMA_PERFMON_SEL_GCR_SEND', 'SDMA_PERFMON_SEL_GFX_SELECT', + 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', + 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', 'SDMA_PERFMON_SEL_IB_CMD_FULL', + 'SDMA_PERFMON_SEL_IB_CMD_IDLE', 'SDMA_PERFMON_SEL_IDLE', + 'SDMA_PERFMON_SEL_INT_IDLE', 'SDMA_PERFMON_SEL_INT_REQ_COUNT', + 'SDMA_PERFMON_SEL_INT_REQ_STALL', + 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', + 'SDMA_PERFMON_SEL_INT_RESP_RETRY', + 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', + 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', + 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', + 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', + 'SDMA_PERFMON_SEL_L2_META_RET_VLD', + 'SDMA_PERFMON_SEL_MC_RD_COUNT', 'SDMA_PERFMON_SEL_MC_RD_IDLE', + 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', + 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', + 'SDMA_PERFMON_SEL_MC_WR_COUNT', 'SDMA_PERFMON_SEL_MC_WR_IDLE', + 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', + 'SDMA_PERFMON_SEL_META_REQ_SEND', 'SDMA_PERFMON_SEL_META_RTN_VLD', + 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', + 'SDMA_PERFMON_SEL_NUM_PACKET', 'SDMA_PERFMON_SEL_PAGE_SELECT', + 'SDMA_PERFMON_SEL_RB_CMD_FULL', 'SDMA_PERFMON_SEL_RB_CMD_IDLE', + 'SDMA_PERFMON_SEL_RB_EMPTY', 'SDMA_PERFMON_SEL_RB_FULL', + 'SDMA_PERFMON_SEL_RB_RPTR_WB', 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', + 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', + 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', 'SDMA_PERFMON_SEL_RD_BA_RTR', + 'SDMA_PERFMON_SEL_REG_IDLE', 'SDMA_PERFMON_SEL_RLC0_SELECT', + 'SDMA_PERFMON_SEL_RLC1_SELECT', + 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', + 'SDMA_PERFMON_SEL_SEM_IDLE', 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', + 'SDMA_PERFMON_SEL_SEM_REQ_STALL', + 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', + 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', + 'SDMA_PERFMON_SEL_SEM_RESP_PASS', + 'SDMA_PERFMON_SEL_SRBM_REG_SEND', 'SDMA_PERFMON_SEL_TLBI_RTN', + 'SDMA_PERFMON_SEL_TLBI_SEND', + 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', + 'SDMA_PERFMON_SEL_UTCL2_FREE', 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', + 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', + 'SDMA_PERFMON_SEL_WR_BA_RTR', 'SDMA_PERF_SEL', + 'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_BUSY', + 'SDMA_PERF_SEL_CE_BUSY_END', 'SDMA_PERF_SEL_CE_BUSY_START', + 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', + 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', 'SDMA_PERF_SEL_CE_CH_WR_REQ', + 'SDMA_PERF_SEL_CE_CH_WR_RET', 'SDMA_PERF_SEL_CE_DST_IDLE', + 'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL', + 'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_WR_VLD', + 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ', + 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET', 'SDMA_PERF_SEL_CE_OUT_IDLE', + 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', + 'SDMA_PERF_SEL_CGCG_FENCE', 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', + 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', 'SDMA_PERF_SEL_CMD_OP_END', + 'SDMA_PERF_SEL_CMD_OP_MATCH', 'SDMA_PERF_SEL_CMD_OP_START', + 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', 'SDMA_PERF_SEL_CTX_CHANGE', + 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', + 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE', + 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'SDMA_PERF_SEL_F32_CH_WR_REQ', 'SDMA_PERF_SEL_F32_CH_WR_RET', + 'SDMA_PERF_SEL_F32_L1_WR_VLD', + 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 'SDMA_PERF_SEL_GCR_RTN', 'SDMA_PERF_SEL_GCR_SEND', + 'SDMA_PERF_SEL_GFX_SELECT', 'SDMA_PERF_SEL_GPUVM_INV_HIGH', + 'SDMA_PERF_SEL_GPUVM_INV_LOW', 'SDMA_PERF_SEL_IB_CH_RD_REQ', + 'SDMA_PERF_SEL_IB_CH_RD_RET', 'SDMA_PERF_SEL_IB_CMD_FULL', + 'SDMA_PERF_SEL_IB_CMD_IDLE', 'SDMA_PERF_SEL_IDLE', + 'SDMA_PERF_SEL_INT_IDLE', 'SDMA_PERF_SEL_INT_REQ_COUNT', + 'SDMA_PERF_SEL_INT_REQ_STALL', 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', + 'SDMA_PERF_SEL_INT_RESP_RETRY', 'SDMA_PERF_SEL_L1_RDL2_IDLE', + 'SDMA_PERF_SEL_L1_RDMC_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_IDLE', + 'SDMA_PERF_SEL_L1_WRL2_IDLE', 'SDMA_PERF_SEL_L1_WRMC_IDLE', + 'SDMA_PERF_SEL_L1_WR_INV_IDLE', 'SDMA_PERF_SEL_L2_META_RET_VLD', + 'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE', + 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', + 'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_META_L2_REQ_SEND', + 'SDMA_PERF_SEL_META_REQ_SEND', 'SDMA_PERF_SEL_META_RTN_VLD', + 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT', + 'SDMA_PERF_SEL_RB_CH_RD_REQ', 'SDMA_PERF_SEL_RB_CH_RD_RET', + 'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE', + 'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL', + 'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE', + 'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT', + 'SDMA_PERF_SEL_SDMA_CPF_INVACK', + 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', + 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', + 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', + 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', + 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', 'SDMA_PERF_SEL_SEM_IDLE', + 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', + 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', + 'SDMA_PERF_SEL_TLBI_RTN', 'SDMA_PERF_SEL_TLBI_SEND', + 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', + 'SDMA_PERF_SEL_UTCL2_FREE', 'SDMA_PERF_SEL_UTCL2_RET_ACK', + 'SDMA_PERF_SEL_UTCL2_RET_XNACK', + 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', + 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', + 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', + 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', + 'SDMA_PERF_SEL_WPTR_CH_RD_RET', 'SDMA_PERF_SEL_WR_BA_RTR', + 'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', 'SEGMENTS_1', + 'SEGMENTS_128', 'SEGMENTS_16', 'SEGMENTS_2', 'SEGMENTS_32', + 'SEGMENTS_4', 'SEGMENTS_64', 'SEGMENTS_8', 'SEL_DTBCLK0', + 'SEL_DTBCLK1', 'SEL_REFCLK0', 'SEM_ECC_ERROR', 'SEM_PERF_SEL', + 'SEM_PERF_SEL_ACP_REQ_SIGNAL', 'SEM_PERF_SEL_ACP_REQ_WAIT', + 'SEM_PERF_SEL_ATC_INVALIDATION', 'SEM_PERF_SEL_ATC_REQ', + 'SEM_PERF_SEL_ATC_RET', 'SEM_PERF_SEL_ATC_VM_INVALIDATION', + 'SEM_PERF_SEL_ATC_XNACK', 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', + 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', + 'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE', + 'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT', + 'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET', + 'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET', + 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT', + 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT', + 'SEM_PERF_SEL_SDMA2_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA2_REQ_WAIT', + 'SEM_PERF_SEL_SDMA3_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA3_REQ_WAIT', + 'SEM_PERF_SEL_UVD1_REQ_SIGNAL', 'SEM_PERF_SEL_UVD1_REQ_WAIT', + 'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT', + 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT', + 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT', + 'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT', + 'SEM_RESP_FAILED', 'SEM_RESP_PASSED', 'SEM_TRANS_ERROR', + 'SEND_AT_EARLIEST_TIME', 'SEND_AT_LINK_NUMBER', + 'SEND_NORMAL_PACKET', 'SEND_PPS_PACKET', 'SET_SMU_MSG_INTR', + 'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32', + 'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE', + 'SH_MEM_ALIGNMENT_MODE_DWORD', + 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', + 'SIGNED', 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE', + 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START', + 'SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_SA_SDST_START', + 'SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_SDST_START', + 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_START', + 'SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_VCC_START', + 'SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_VDST_START', + 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_START', + 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', + 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', + 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', + 'SIMM16_WAIT_EVENT_EXP_RDY_SIZE', + 'SIMM16_WAIT_EVENT_EXP_RDY_START', 'SIZE_16K', 'SIZE_8K', + 'SLVERR', 'SMU_INTR', 'SMU_INTR_STATUS_CLEAR', + 'SMU_INTR_STATUS_NOOP', 'SMU_MSG_INTR_NOOP', 'SM_MODE_RESERVED', + 'SOFT_RESET', 'SOFT_RESET_0', 'SOFT_RESET_1', + 'SO_VGTSTREAMOUT_FLUSH', 'SPI_FOG_EXP', 'SPI_FOG_EXP2', + 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', 'SPI_FOG_NONE', + 'SPI_LB_WAVES_RSVD', 'SPI_LB_WAVES_SELECT', 'SPI_PERFCNT_SEL', + 'SPI_PERF_BUSY', 'SPI_PERF_CSGN_BUSY', + 'SPI_PERF_CSGN_CRAWLER_STALL', 'SPI_PERF_CSGN_EVENT_WAVE', + 'SPI_PERF_CSGN_NUM_THREADGROUPS', 'SPI_PERF_CSGN_PWS_STALL', + 'SPI_PERF_CSGN_WAVE', 'SPI_PERF_CSGN_WINDOW_VALID', + 'SPI_PERF_CSN_BUSY', 'SPI_PERF_CSN_CRAWLER_STALL', + 'SPI_PERF_CSN_EVENT_WAVE', 'SPI_PERF_CSN_NUM_THREADGROUPS', + 'SPI_PERF_CSN_WAVE', 'SPI_PERF_CSN_WINDOW_VALID', + 'SPI_PERF_EXPORT_DB0_STALL', 'SPI_PERF_EXPORT_DB1_STALL', + 'SPI_PERF_EXPORT_DB2_STALL', 'SPI_PERF_EXPORT_DB3_STALL', + 'SPI_PERF_EXPORT_DB4_STALL', 'SPI_PERF_EXPORT_DB5_STALL', + 'SPI_PERF_EXPORT_DB6_STALL', 'SPI_PERF_EXPORT_DB7_STALL', + 'SPI_PERF_EXPORT_SCB0_STALL', 'SPI_PERF_EXPORT_SCB1_STALL', + 'SPI_PERF_EXPORT_SCB2_STALL', 'SPI_PERF_EXPORT_SCB3_STALL', + 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', + 'SPI_PERF_EXP_ARB_IDX_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', + 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', + 'SPI_PERF_EXP_THROT_DOWNSTEP', 'SPI_PERF_EXP_THROT_UPSTEP', + 'SPI_PERF_EXP_WITH_CONFLICT', 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', + 'SPI_PERF_GS_BUSY', 'SPI_PERF_GS_CRAWLER_STALL', + 'SPI_PERF_GS_EVENT_WAVE', 'SPI_PERF_GS_EXP_DONE', + 'SPI_PERF_GS_FIRST_SUBGRP', 'SPI_PERF_GS_HS_DEALLOC', + 'SPI_PERF_GS_INDX0_STALL', 'SPI_PERF_GS_INDX1_STALL', + 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', + 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', + 'SPI_PERF_GS_NGG_STALL_MSG_VAL', 'SPI_PERF_GS_PERS_UPD_FULL0', + 'SPI_PERF_GS_PERS_UPD_FULL1', 'SPI_PERF_GS_POS0_STALL', + 'SPI_PERF_GS_POS1_STALL', 'SPI_PERF_GS_PWS_STALL', + 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID', + 'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL', + 'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE', + 'SPI_PERF_HS_OFFCHIP_LDS_STALL', 'SPI_PERF_HS_PERS_UPD_FULL0', + 'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_PWS_STALL', + 'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WINDOW_VALID', + 'SPI_PERF_NUM_EXPGRANT_EXPORTS', + 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', + 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', + 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', + 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', + 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', + 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', + 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', + 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', + 'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PS0_2_WAVE_GROUPS', + 'SPI_PERF_PS0_ACTIVE', 'SPI_PERF_PS0_BUSY', + 'SPI_PERF_PS0_CRAWLER_STALL', 'SPI_PERF_PS0_DEALLOC', + 'SPI_PERF_PS0_EVENT_WAVE', 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', + 'SPI_PERF_PS0_OPT_WAVE', 'SPI_PERF_PS0_PRIM_BIN0', + 'SPI_PERF_PS0_PRIM_BIN1', 'SPI_PERF_PS0_WAVE', + 'SPI_PERF_PS0_WAVEID_STARVED', + 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS0_WINDOW_VALID', + 'SPI_PERF_PS1_2_WAVE_GROUPS', 'SPI_PERF_PS1_ACTIVE', + 'SPI_PERF_PS1_BUSY', 'SPI_PERF_PS1_CRAWLER_STALL', + 'SPI_PERF_PS1_DEALLOC', 'SPI_PERF_PS1_EVENT_WAVE', + 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS1_OPT_WAVE', + 'SPI_PERF_PS1_PRIM_BIN0', 'SPI_PERF_PS1_PRIM_BIN1', + 'SPI_PERF_PS1_WAVE', 'SPI_PERF_PS1_WAVEID_STARVED', + 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS1_WINDOW_VALID', + 'SPI_PERF_PS2_2_WAVE_GROUPS', 'SPI_PERF_PS2_ACTIVE', + 'SPI_PERF_PS2_BUSY', 'SPI_PERF_PS2_CRAWLER_STALL', + 'SPI_PERF_PS2_DEALLOC', 'SPI_PERF_PS2_EVENT_WAVE', + 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS2_OPT_WAVE', + 'SPI_PERF_PS2_PRIM_BIN0', 'SPI_PERF_PS2_PRIM_BIN1', + 'SPI_PERF_PS2_WAVE', 'SPI_PERF_PS2_WAVEID_STARVED', + 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS2_WINDOW_VALID', + 'SPI_PERF_PS3_2_WAVE_GROUPS', 'SPI_PERF_PS3_ACTIVE', + 'SPI_PERF_PS3_BUSY', 'SPI_PERF_PS3_CRAWLER_STALL', + 'SPI_PERF_PS3_DEALLOC', 'SPI_PERF_PS3_EVENT_WAVE', + 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS3_OPT_WAVE', + 'SPI_PERF_PS3_PRIM_BIN0', 'SPI_PERF_PS3_PRIM_BIN1', + 'SPI_PERF_PS3_WAVE', 'SPI_PERF_PS3_WAVEID_STARVED', + 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS3_WINDOW_VALID', + 'SPI_PERF_PS_EXP_ALLOC', 'SPI_PERF_PS_EXP_ARB_CONFLICT', + 'SPI_PERF_PS_EXP_DONE', 'SPI_PERF_PS_PERS_UPD_FULL0', + 'SPI_PERF_PS_PERS_UPD_FULL1', 'SPI_PERF_PS_PWS_STALL', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', 'SPI_PERF_RA_BAR_CU_FULL_CSG', + 'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_HS', + 'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN', + 'SPI_PERF_RA_CSC_UNDER_TUNNEL', 'SPI_PERF_RA_CSG_LOCK', + 'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_GFX_UNDER_TUNNEL', + 'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK', + 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 'SPI_PERF_RA_LDS_CU_FULL_GS', 'SPI_PERF_RA_LDS_CU_FULL_HS', + 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_PIPE_REQ_BIN2', + 'SPI_PERF_RA_PRE_ALLOC_STALL', 'SPI_PERF_RA_REQ_NO_ALLOC', + 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', + 'SPI_PERF_RA_REQ_NO_ALLOC_GS', 'SPI_PERF_RA_REQ_NO_ALLOC_HS', + 'SPI_PERF_RA_REQ_NO_ALLOC_PS', 'SPI_PERF_RA_RES_STALL_CSG', + 'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_GS', + 'SPI_PERF_RA_RES_STALL_HS', 'SPI_PERF_RA_RES_STALL_PS', + 'SPI_PERF_RA_RSV_UPD', 'SPI_PERF_RA_TASK_REQ_BIN3', + 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', + 'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS', + 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 'SPI_PERF_RA_WR_CTL_FULL', 'SPI_PERF_RA_WVALLOC_STALL', + 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', + 'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS', + 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_SWC_CSGN_WR', + 'SPI_PERF_SWC_CSN_WR', 'SPI_PERF_SWC_GS_WR', 'SPI_PERF_SWC_HS_WR', + 'SPI_PERF_SWC_PS_WR', 'SPI_PERF_VWC_CSGN_WR', + 'SPI_PERF_VWC_CSN_WR', 'SPI_PERF_VWC_ES_WR', 'SPI_PERF_VWC_GS_WR', + 'SPI_PERF_VWC_HS_WR', 'SPI_PERF_VWC_LS_WR', 'SPI_PERF_VWC_PS_WR', + 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', + 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', + 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', + 'SPI_PS_LDS_GROUP_1', 'SPI_PS_LDS_GROUP_2', 'SPI_PS_LDS_GROUP_4', + 'SPI_PS_LDS_GROUP_SIZE', 'SPI_SAMPLE_CNTL', 'SPI_SHADER_1COMP', + 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', 'SPI_SHADER_32_AR', + 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', 'SPI_SHADER_4COMP', + 'SPI_SHADER_4COMPRESS', 'SPI_SHADER_EX_FORMAT', + 'SPI_SHADER_FORMAT', 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', + 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', + 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', + 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', + 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', + 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', + 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', + 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', 'SP_PERF_SEL_DUMMY_LAST', + 'SP_PERF_SEL_SRC_CACHE_HIT_B0', 'SP_PERF_SEL_SRC_CACHE_HIT_B1', + 'SP_PERF_SEL_SRC_CACHE_HIT_B2', 'SP_PERF_SEL_SRC_CACHE_HIT_B3', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', + 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', + 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', + 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', + 'SP_PERF_SEL_VALU_OPERAND', + 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', + 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', + 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', 'SP_PERF_SEL_VALU_STALL', + 'SP_PERF_SEL_VALU_STALL_DST_STALL', + 'SP_PERF_SEL_VALU_STALL_SDST_FWD', + 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', + 'SP_PERF_SEL_VALU_STALL_VDST_FWD', + 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', + 'SP_PERF_SEL_VALU_VGPR_OPERAND', 'SP_PERF_SEL_VGPR_EXP_RD', + 'SP_PERF_SEL_VGPR_RD', 'SP_PERF_SEL_VGPR_SPI_WR', + 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', 'SP_PERF_SEL_VGPR_VMEM_RD', + 'SP_PERF_SEL_VGPR_WR', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GCR', + 'SQC_PERF_SEL_DCACHE_GCR_HITS', + 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_DCACHE_HITS', + 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_MISSES', + 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_DCACHE_REQ', + 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 'SQC_PERF_SEL_DCACHE_REQ_READ_8', + 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', + 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DUMMY_LAST', 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_ICACHE_GCR', 'SQC_PERF_SEL_ICACHE_GCR_HITS', + 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_ICACHE_HITS', + 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', + 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_ICACHE_REQ', + 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', + 'SQC_PERF_SEL_LDS_ADDR_STALL', 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', + 'SQC_PERF_SEL_LDS_BANK_CONFLICT', + 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', 'SQC_PERF_SEL_LDS_IDX_ACTIVE', + 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', + 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', + 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', + 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', + 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', + 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', 'SQC_PERF_SEL_LDS_VGPR_BUSY', + 'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_READ_REQ', + 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', + 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', + 'SQC_PERF_SEL_TC_STARVE', 'SQC_PERF_SEL_TD_VGPR_BUSY', + 'SQDEC_BEGIN', 'SQDEC_END', 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', + 'SQG_PERF_SEL', 'SQG_PERF_SEL_ACCUM_PREV', + 'SQG_PERF_SEL_BUSY_CYCLES', 'SQG_PERF_SEL_CYCLES', + 'SQG_PERF_SEL_DUMMY_LAST', 'SQG_PERF_SEL_EVENTS', + 'SQG_PERF_SEL_EXP_BUS0_BUSY', 'SQG_PERF_SEL_EXP_BUS1_BUSY', + 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', + 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', 'SQG_PERF_SEL_ITEMS', + 'SQG_PERF_SEL_LEVEL_WAVES', 'SQG_PERF_SEL_MSG', + 'SQG_PERF_SEL_MSG_BUS_BUSY', 'SQG_PERF_SEL_MSG_INTERRUPT', + 'SQG_PERF_SEL_NONE', 'SQG_PERF_SEL_PS_QUADS', + 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', + 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', 'SQG_PERF_SEL_TTRACE_REQS', + 'SQG_PERF_SEL_TTRACE_STALL', 'SQG_PERF_SEL_WAVE32_ITEMS', + 'SQG_PERF_SEL_WAVE64_ITEMS', 'SQG_PERF_SEL_WAVES', + 'SQG_PERF_SEL_WAVES_32', 'SQG_PERF_SEL_WAVES_64', + 'SQG_PERF_SEL_WAVES_EQ_32', 'SQG_PERF_SEL_WAVES_EQ_64', + 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', 'SQG_PERF_SEL_WAVES_LT_16', + 'SQG_PERF_SEL_WAVES_LT_32', 'SQG_PERF_SEL_WAVES_LT_48', + 'SQG_PERF_SEL_WAVES_LT_64', 'SQG_PERF_SEL_WAVES_RESTORED', + 'SQG_PERF_SEL_WAVES_SAVED', 'SQG_PERF_SEL_WAVE_CYCLES', + 'SQIND_GLOBAL_REGS_OFFSET', 'SQIND_GLOBAL_REGS_SIZE', + 'SQIND_LOCAL_REGS_OFFSET', 'SQIND_LOCAL_REGS_SIZE', + 'SQIND_WAVE_HWREGS_OFFSET', 'SQIND_WAVE_HWREGS_SIZE', + 'SQIND_WAVE_SGPRS_OFFSET', 'SQIND_WAVE_SGPRS_SIZE', + 'SQIND_WAVE_VGPRS_OFFSET', 'SQIND_WAVE_VGPRS_SIZE', + 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', 'SQPERFSDEC_BEGIN', + 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', 'SQPWRDEC_END', + 'SQ_CAC_POWER_ALU_BUSY', 'SQ_CAC_POWER_GPR_RD', + 'SQ_CAC_POWER_GPR_WR', 'SQ_CAC_POWER_LDS_BUSY', + 'SQ_CAC_POWER_SEL', 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', + 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', + 'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN', + 'SQ_EDC_FUE_CNTL_LDS', 'SQ_EDC_FUE_CNTL_SIMD0', + 'SQ_EDC_FUE_CNTL_SIMD1', 'SQ_EDC_FUE_CNTL_SIMD2', + 'SQ_EDC_FUE_CNTL_SIMD3', 'SQ_EDC_FUE_CNTL_SQ', + 'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', 'SQ_EDC_FUE_CNTL_TD', + 'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS', + 'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID', + 'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR', + 'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR', + 'SQ_EX_MODE_EXCP_ADDR_WATCH0', 'SQ_EX_MODE_EXCP_DIV0', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT', + 'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0', + 'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL', + 'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW', + 'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE', + 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', + 'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET', + 'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE', + 'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT', + 'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', + 'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX', + 'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', + 'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL', + 'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT', + 'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SPI_PRIO', + 'SQ_IND_CMD_CMD_SINGLE_STEP', 'SQ_IND_CMD_CMD_TRAP', + 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', 'SQ_IND_CMD_MODE', + 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', + 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', + 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', + 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', 'SQ_INST_STR_ST', + 'SQ_INST_TYPE', 'SQ_INST_TYPE_BARRIER', + 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', 'SQ_INST_TYPE_BRANCH_TAKEN', + 'SQ_INST_TYPE_EXP', 'SQ_INST_TYPE_JUMP', 'SQ_INST_TYPE_LDS', + 'SQ_INST_TYPE_LDS_DIRECT', 'SQ_INST_TYPE_MSG', + 'SQ_INST_TYPE_NONE', 'SQ_INST_TYPE_OTHER', 'SQ_INST_TYPE_SCALAR', + 'SQ_INST_TYPE_TEX', 'SQ_INST_TYPE_VALU', 'SQ_LLC_0', 'SQ_LLC_1', + 'SQ_LLC_BYPASS', 'SQ_LLC_CTL', 'SQ_LLC_RSVD_2', + 'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', 'SQ_NON_EVENT', + 'SQ_NO_INST_ISSUE', 'SQ_NO_INST_ISSUE_ALU_DEP', + 'SQ_NO_INST_ISSUE_BARRIER_WAIT', 'SQ_NO_INST_ISSUE_NO_ARB_WIN', + 'SQ_NO_INST_ISSUE_NO_INSTS', 'SQ_NO_INST_ISSUE_OTHER', + 'SQ_NO_INST_ISSUE_SLEEP_WAIT', 'SQ_NO_INST_ISSUE_S_WAITCNT', + 'SQ_OOB_COMPLETE', 'SQ_OOB_INDEX_AND_OFFSET', 'SQ_OOB_INDEX_ONLY', + 'SQ_OOB_NUM_RECORDS_0', 'SQ_OOB_SELECT', 'SQ_PERF_SEL', + 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_BUSY_CYCLES', + 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', + 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', + 'SQ_PERF_SEL_EXP_BUS0_BUSY', 'SQ_PERF_SEL_EXP_BUS1_BUSY', + 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', + 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_REQS', + 'SQ_PERF_SEL_INSTS_ALL', 'SQ_PERF_SEL_INSTS_BRANCH', + 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', + 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', + 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', + 'SQ_PERF_SEL_INSTS_DELAY_ALU', + 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', 'SQ_PERF_SEL_INSTS_EXP', + 'SQ_PERF_SEL_INSTS_EXP_GDS', 'SQ_PERF_SEL_INSTS_FLAT', + 'SQ_PERF_SEL_INSTS_GDS', 'SQ_PERF_SEL_INSTS_INTERNAL', + 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', + 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', 'SQ_PERF_SEL_INSTS_SALU', + 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', + 'SQ_PERF_SEL_INSTS_SMEM_NORM', 'SQ_PERF_SEL_INSTS_TEX', + 'SQ_PERF_SEL_INSTS_TEX_LOAD', 'SQ_PERF_SEL_INSTS_TEX_STORE', + 'SQ_PERF_SEL_INSTS_VALU', 'SQ_PERF_SEL_INSTS_VALU_1_PASS', + 'SQ_PERF_SEL_INSTS_VALU_2_PASS', 'SQ_PERF_SEL_INSTS_VALU_4_PASS', + 'SQ_PERF_SEL_INSTS_VALU_DP', + 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', + 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', + 'SQ_PERF_SEL_INSTS_VALU_TRANS', 'SQ_PERF_SEL_INSTS_VALU_TRANS32', + 'SQ_PERF_SEL_INSTS_VALU_VINTERP', + 'SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP', + 'SQ_PERF_SEL_INSTS_WAVE32', 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', + 'SQ_PERF_SEL_INSTS_WAVE32_LDS', + 'SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD', + 'SQ_PERF_SEL_INSTS_WAVE32_TEX', + 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', + 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', + 'SQ_PERF_SEL_INSTS_WAVE32_VALU', + 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', + 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', 'SQ_PERF_SEL_INST_CYCLES_EXP', + 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', 'SQ_PERF_SEL_INST_CYCLES_FLAT', + 'SQ_PERF_SEL_INST_CYCLES_GDS', 'SQ_PERF_SEL_INST_CYCLES_LDS', + 'SQ_PERF_SEL_INST_CYCLES_TEX', 'SQ_PERF_SEL_INST_CYCLES_VALU', + 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', + 'SQ_PERF_SEL_INST_CYCLES_VMEM', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', + 'SQ_PERF_SEL_INST_LEVEL_EXP', 'SQ_PERF_SEL_INST_LEVEL_GDS', + 'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM', + 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', + 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', 'SQ_PERF_SEL_ITEMS', + 'SQ_PERF_SEL_ITEMS_MAX_VALU', 'SQ_PERF_SEL_ITEMS_VALU', + 'SQ_PERF_SEL_ITEM_CYCLES_VALU', 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', + 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_LEVEL_WAVES', 'SQ_PERF_SEL_MSG', + 'SQ_PERF_SEL_MSG_BUS_BUSY', 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', + 'SQ_PERF_SEL_MSG_INTERRUPT', 'SQ_PERF_SEL_NONE', + 'SQ_PERF_SEL_NONE2', 'SQ_PERF_SEL_OVERFLOW_PREV', + 'SQ_PERF_SEL_PS_QUADS', 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', + 'SQ_PERF_SEL_SALU_PIPE_STALL', 'SQ_PERF_SEL_SALU_SGATHER_STALL', + 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', + 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', + 'SQ_PERF_SEL_SP_CONST_CYCLES', + 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', 'SQ_PERF_SEL_USER0', + 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', + 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', + 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', + 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', + 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', + 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', + 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', + 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', + 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', + 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', + 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', + 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', + 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', + 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', + 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', + 'SQ_PERF_SEL_VALU_RETURN_SDST', + 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', + 'SQ_PERF_SEL_VALU_SGATHER_STALL', + 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_VALU_STARVE', 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', 'SQ_PERF_SEL_VMEM_BUS_STALL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', + 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', + 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', + 'SQ_PERF_SEL_WAIT_ANY', 'SQ_PERF_SEL_WAIT_BARRIER', + 'SQ_PERF_SEL_WAIT_CNT_ANY', 'SQ_PERF_SEL_WAIT_CNT_EXP', + 'SQ_PERF_SEL_WAIT_CNT_LGKM', 'SQ_PERF_SEL_WAIT_CNT_VMVS', + 'SQ_PERF_SEL_WAIT_DELAY_ALU', 'SQ_PERF_SEL_WAIT_DEPCTR', + 'SQ_PERF_SEL_WAIT_EXP_ALLOC', 'SQ_PERF_SEL_WAIT_IFETCH', + 'SQ_PERF_SEL_WAIT_INST_ANY', 'SQ_PERF_SEL_WAIT_INST_BR_MSG', + 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', 'SQ_PERF_SEL_WAIT_INST_FLAT', + 'SQ_PERF_SEL_WAIT_INST_LDS', 'SQ_PERF_SEL_WAIT_INST_SCA', + 'SQ_PERF_SEL_WAIT_INST_TEX', 'SQ_PERF_SEL_WAIT_INST_VALU', + 'SQ_PERF_SEL_WAIT_INST_VMEM', 'SQ_PERF_SEL_WAIT_OTHER', + 'SQ_PERF_SEL_WAIT_SLEEP', 'SQ_PERF_SEL_WAIT_TTRACE', + 'SQ_PERF_SEL_WAVE32_INSTS', 'SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS', + 'SQ_PERF_SEL_WAVE32_ITEMS', 'SQ_PERF_SEL_WAVE64_HALF_SKIP', + 'SQ_PERF_SEL_WAVE64_INSTS', 'SQ_PERF_SEL_WAVE64_ITEMS', + 'SQ_PERF_SEL_WAVES', 'SQ_PERF_SEL_WAVES_32', + 'SQ_PERF_SEL_WAVES_64', 'SQ_PERF_SEL_WAVES_EQ_32', + 'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', + 'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32', + 'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64', + 'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED', + 'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY', + 'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE', + 'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY', + 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1', + 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE', + 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2', + 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D', + 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY', + 'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY', + 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0', + 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3', + 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6', + 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SEL_0', 'SQ_SEL_1', + 'SQ_SEL_N_BC_1', 'SQ_SEL_RESERVED_1', 'SQ_SEL_W', 'SQ_SEL_X', + 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', 'SQ_TEX_ANISO_RATIO', + 'SQ_TEX_ANISO_RATIO_1', 'SQ_TEX_ANISO_RATIO_16', + 'SQ_TEX_ANISO_RATIO_2', 'SQ_TEX_ANISO_RATIO_4', + 'SQ_TEX_ANISO_RATIO_8', 'SQ_TEX_BORDER_COLOR', + 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', + 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', + 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 'SQ_TEX_DEPTH_COMPARE_GREATER', + 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', + 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', + 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', + 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', + 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', + 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', + 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', + 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', + 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', + 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', + 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', + 'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT', + 'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT', + 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT', + 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT', 'SQ_TT_MODE', + 'SQ_TT_MODE_DETAIL', 'SQ_TT_MODE_GLOBAL', 'SQ_TT_MODE_OFF', + 'SQ_TT_MODE_ON', 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT', + 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT', + 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT', + 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT', + 'SQ_TT_REG_EXCLUDE_USER_DATA_BIT', + 'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT', 'SQ_TT_RT_FREQ', + 'SQ_TT_RT_FREQ_1024_CLK', 'SQ_TT_RT_FREQ_4096_CLK', + 'SQ_TT_RT_FREQ_NEVER', 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT', + 'SQ_TT_TOKEN_MASK_ALL_BIT', 'SQ_TT_TOKEN_MASK_ALL_SHIFT', + 'SQ_TT_TOKEN_MASK_COMP_BIT', 'SQ_TT_TOKEN_MASK_COMP_SHIFT', + 'SQ_TT_TOKEN_MASK_CONFIG_BIT', 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', + 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', + 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', + 'SQ_TT_TOKEN_MASK_INST_EXCLUDE', + 'SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT', + 'SQ_TT_TOKEN_MASK_REG_EXCLUDE', + 'SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT', + 'SQ_TT_TOKEN_MASK_REG_INCLUDE', + 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT', 'SQ_TT_TOKEN_MASK_RSVD_BIT', + 'SQ_TT_TOKEN_MASK_RSVD_SHIFT', 'SQ_TT_TOKEN_MASK_SHDEC_BIT', + 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', 'SQ_TT_TOKEN_MASK_SQDEC_BIT', + 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', + 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT', 'SQ_TT_UTIL_TIMER', + 'SQ_TT_UTIL_TIMER_100_CLK', 'SQ_TT_UTIL_TIMER_250_CLK', + 'SQ_TT_WAVESTART_MODE', 'SQ_TT_WAVESTART_MODE_ALLOC', + 'SQ_TT_WAVESTART_MODE_PBB_ID', 'SQ_TT_WAVESTART_MODE_SHORT', + 'SQ_TT_WTYPE_INCLUDE', 'SQ_TT_WTYPE_INCLUDE_CS_BIT', + 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_GS_BIT', + 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_HS_BIT', + 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_PS_BIT', + 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT', + 'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT', + 'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT', + 'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT', + 'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT', + 'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT', 'SQ_TT_WTYPE_INCLUDE_SHIFT', + 'SQ_WATCH_MODES', 'SQ_WATCH_MODE_ALL', 'SQ_WATCH_MODE_ATOMIC', + 'SQ_WATCH_MODE_NONREAD', 'SQ_WATCH_MODE_READ', + 'SQ_WAVE_FWD_PROG_INTERVAL', 'SQ_WAVE_FWD_PROG_INTERVAL_1024', + 'SQ_WAVE_FWD_PROG_INTERVAL_256', 'SQ_WAVE_FWD_PROG_INTERVAL_4096', + 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', 'SQ_WAVE_IB_DEP_HOLD_CNT_SIZE', + 'SQ_WAVE_IB_DEP_LDS_DIR_SIZE', 'SQ_WAVE_IB_DEP_SA_EXEC_SIZE', + 'SQ_WAVE_IB_DEP_SA_M0_SIZE', 'SQ_WAVE_IB_DEP_SA_SDST_SIZE', + 'SQ_WAVE_IB_DEP_VA_EXEC_SIZE', 'SQ_WAVE_IB_DEP_VA_SDST_SIZE', + 'SQ_WAVE_IB_DEP_VA_SSRC_SIZE', 'SQ_WAVE_IB_DEP_VA_VCC_SIZE', + 'SQ_WAVE_IB_DEP_VA_VDST_SIZE', 'SQ_WAVE_IB_DEP_VM_VSRC_SIZE', + 'SQ_WAVE_IB_ECC_CLEAN', 'SQ_WAVE_IB_ECC_ERR_CONTINUE', + 'SQ_WAVE_IB_ECC_ERR_HALT', 'SQ_WAVE_IB_ECC_ST', + 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', 'SQ_WAVE_SCHED_MODES', + 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', 'SQ_WAVE_SCHED_MODE_EXPERT', + 'SQ_WAVE_SCHED_MODE_NORMAL', 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', + 'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_PS', + 'SQ_WAVE_TYPE_PS0', 'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_PS2', + 'SQ_WAVE_TYPE_PS3', 'SQ_WAVE_TYPE_RSVD0', 'SQ_WAVE_TYPE_RSVD1', + 'SQ_WAVE_TYPE_RSVD2', 'SRCID_NONSECURE_CP', + 'SRCID_NONSECURE_CP_RCIU', 'SRCID_RLC', 'SRCID_RLCV', + 'SRCID_SECURE_CP', 'SRCID_SECURE_CP_RCIU', 'STALL', + 'STENCIL_ADD_CLAMP', 'STENCIL_ADD_WRAP', 'STENCIL_AND', + 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', + 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', + 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', + 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', + 'STREAM_0_SYNCHRONIZATION', + 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_10_SYNCHRONIZATION', + 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION', + 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION', + 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION', + 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION', + 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION', + 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_1_SYNCHRONIZATION', + 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_2_SYNCHRONIZATION', + 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_3_SYNCHRONIZATION', + 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_4_SYNCHRONIZATION', + 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_5_SYNCHRONIZATION', + 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_6_SYNCHRONIZATION', + 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION', + 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION', + 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION', + 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_DSC_444_RGB', 'STREAM_DSC_DISABLE', + 'STREAM_DSC_NATIVE_422_420', 'STREAM_ODM_COMBINE_1_SEGMENT', + 'STREAM_ODM_COMBINE_2_SEGMENT', 'STREAM_ODM_COMBINE_4_SEGMENT', + 'STREAM_ODM_COMBINE_RESERVED', 'STREAM_PIXEL_ENCODING_420', + 'STREAM_PIXEL_ENCODING_422', 'STREAM_PIXEL_ENCODING_444_RGB', + 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'STRM_PERFMON_STATE_RESERVED_3', + 'STRM_PERFMON_STATE_START_COUNTING', + 'STRM_PERFMON_STATE_STOP_COUNTING', 'SURFACE_DCC', + 'SURFACE_DCC_BLOCK_IS_IND_128B', 'SURFACE_DCC_BLOCK_IS_IND_64B', + 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', + 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', 'SURFACE_DCC_IND_128B', + 'SURFACE_DCC_IND_64B', 'SURFACE_DCC_IND_BLK', + 'SURFACE_DCC_IS_IND_128B', 'SURFACE_DCC_IS_IND_64B', + 'SURFACE_DCC_IS_NOT_IND_128B', 'SURFACE_DCC_IS_NOT_IND_64B', + 'SURFACE_FLIP_AWAY_INT_LEVEL', 'SURFACE_FLIP_AWAY_INT_PULSE', + 'SURFACE_FLIP_AWAY_INT_TYPE', 'SURFACE_FLIP_EXEC_DEBUG_MODE', + 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', + 'SURFACE_FLIP_EXEC_NORMAL_MODE', 'SURFACE_FLIP_INT_LEVEL', + 'SURFACE_FLIP_INT_PULSE', 'SURFACE_FLIP_INT_TYPE', + 'SURFACE_FLIP_IN_STEREOSYNC', 'SURFACE_FLIP_IN_STEREOSYNC_MODE', + 'SURFACE_FLIP_MODE_FOR_STEREOSYNC', + 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', + 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', + 'SURFACE_FLIP_STEREO_SELECT_DISABLE', + 'SURFACE_FLIP_STEREO_SELECT_DISABLED', + 'SURFACE_FLIP_STEREO_SELECT_ENABLED', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', + 'SURFACE_FLIP_TYPE', 'SURFACE_FLIP_VUPDATE_SKIP_NUM', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', 'SURFACE_INUSE_IS_LATCHED', + 'SURFACE_INUSE_IS_NOT_LATCHED', 'SURFACE_INUSE_RAED_NO_LATCH', + 'SURFACE_IS_DCC', 'SURFACE_IS_NOT_DCC', 'SURFACE_IS_NOT_TMZ', + 'SURFACE_IS_TMZ', 'SURFACE_I_FLIP', 'SURFACE_PIXEL_FORMAT', + 'SURFACE_TMZ', 'SURFACE_UPDATE_IS_LOCKED', + 'SURFACE_UPDATE_IS_UNLOCKED', 'SURFACE_UPDATE_LOCK', + 'SURFACE_V_FLIP', 'SU_PERFCNT_SEL', 'SWATH_HEIGHT', + 'SWATH_HEIGHT_16L', 'SWATH_HEIGHT_1L', 'SWATH_HEIGHT_2L', + 'SWATH_HEIGHT_4L', 'SWATH_HEIGHT_8L', 'SX_BLEND_OPT', + 'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT', + 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK', + 'SX_PERF_SEL_CLOCK_DROP_STALL', 'SX_PERF_SEL_COL_BUSY', + 'SX_PERF_SEL_DB0_4X2_DISCARD', 'SX_PERF_SEL_DB0_END_OF_WAVE', + 'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', + 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', + 'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB0_SIZE', + 'SX_PERF_SEL_DB1_4X2_DISCARD', 'SX_PERF_SEL_DB1_END_OF_WAVE', + 'SX_PERF_SEL_DB1_HALF_QUADS', 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', + 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', + 'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB1_SIZE', + 'SX_PERF_SEL_DB2_4X2_DISCARD', 'SX_PERF_SEL_DB2_END_OF_WAVE', + 'SX_PERF_SEL_DB2_HALF_QUADS', 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', + 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', + 'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB2_SIZE', + 'SX_PERF_SEL_DB3_4X2_DISCARD', 'SX_PERF_SEL_DB3_END_OF_WAVE', + 'SX_PERF_SEL_DB3_HALF_QUADS', 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', + 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', + 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_DB3_SIZE', + 'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2', + 'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4', + 'SX_PERF_SEL_GATE_EN5', 'SX_PERF_SEL_GATE_EN6', + 'SX_PERF_SEL_GATE_EN7', 'SX_PERF_SEL_GATE_EN8', + 'SX_PERF_SEL_IDX_BUSY', 'SX_PERF_SEL_IDX_IDLE_CYCLES', + 'SX_PERF_SEL_IDX_REQ', 'SX_PERF_SEL_IDX_REQ_LATENCY', + 'SX_PERF_SEL_IDX_RET', 'SX_PERF_SEL_IDX_SCBD_STALL', + 'SX_PERF_SEL_IDX_STALL_CYCLES', 'SX_PERF_SEL_PA_IDLE_CYCLES', + 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_POS_BANK_CONF', + 'SX_PERF_SEL_PA_REQ', 'SX_PERF_SEL_PA_REQ_LATENCY', + 'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_POS_SCBD_STALL', + 'SX_PERF_SEL_SH_COLOR_STALL', 'SX_PERF_SEL_SH_COLOR_STARVE', + 'SX_PERF_SEL_SH_IDX_STARVE', 'SX_PERF_SEL_SH_POS_STALL', + 'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11', + 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', + 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', + 'SX_RT_EXPORT_2_10_10_10_6E4', 'SX_RT_EXPORT_2_10_10_10_7E3', + 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', + 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', + 'SX_RT_EXPORT_9_9_9_E5', 'SX_RT_EXPORT_NO_CONVERSION', + 'SYMCLK_FE_FORCE_EN', 'SYMCLK_FE_FORCE_EN_DISABLE', + 'SYMCLK_FE_FORCE_EN_ENABLE', 'SYMCLK_FE_FORCE_SRC', + 'SYMCLK_FE_FORCE_SRC_RESERVED', 'SYMCLK_FE_FORCE_SRC_UNIPHYA', + 'SYMCLK_FE_FORCE_SRC_UNIPHYB', 'SYMCLK_FE_FORCE_SRC_UNIPHYC', + 'SYMCLK_FE_FORCE_SRC_UNIPHYD', 'ScMap', 'ScUncertaintyRegionMode', + 'ScUncertaintyRegionMult', 'ScXsel', 'ScYsel', 'SeMap', + 'SePairMap', 'SePairXsel', 'SePairYsel', 'SeXsel', 'SeYsel', + 'SourceFormat', 'Spare_257', 'StencilOp', 'TA_PERFCOUNT_SEL', + 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', + 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 'TA_PERF_SEL_addresser_stalled_cycles', + 'TA_PERF_SEL_aligner_busy', + 'TA_PERF_SEL_aligner_clk_valid_cycles', + 'TA_PERF_SEL_aligner_cycles', 'TA_PERF_SEL_aniso_10_cycle_quads', + 'TA_PERF_SEL_aniso_12_cycle_quads', + 'TA_PERF_SEL_aniso_14_cycle_quads', + 'TA_PERF_SEL_aniso_16_cycle_quads', + 'TA_PERF_SEL_aniso_1_cycle_quads', + 'TA_PERF_SEL_aniso_2_cycle_quads', + 'TA_PERF_SEL_aniso_4_cycle_quads', + 'TA_PERF_SEL_aniso_6_cycle_quads', + 'TA_PERF_SEL_aniso_8_cycle_quads', + 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 'TA_PERF_SEL_aniso_stalled_cycles', + 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', + 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', + 'TA_PERF_SEL_atomic_write_data_input_cycles', + 'TA_PERF_SEL_atomic_write_data_output_cycles', + 'TA_PERF_SEL_bf_busy', + 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', + 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', + 'TA_PERF_SEL_buffer_atomic_wavefronts', + 'TA_PERF_SEL_buffer_flat_1_op_burst', + 'TA_PERF_SEL_buffer_flat_2to3_op_burst', + 'TA_PERF_SEL_buffer_flat_4to31_op_burst', + 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', + 'TA_PERF_SEL_buffer_flat_ge32_op_burst', + 'TA_PERF_SEL_buffer_has_index_instructions', + 'TA_PERF_SEL_buffer_has_offset_instructions', + 'TA_PERF_SEL_buffer_load_wavefronts', + 'TA_PERF_SEL_buffer_store_wavefronts', + 'TA_PERF_SEL_buffer_total_cycles', + 'TA_PERF_SEL_buffer_wavefronts', 'TA_PERF_SEL_bvh_total_cycles', + 'TA_PERF_SEL_color_1_cycle_quads', + 'TA_PERF_SEL_color_2_cycle_quads', + 'TA_PERF_SEL_color_3_cycle_quads', + 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 'TA_PERF_SEL_deriv_stalled_cycles', + 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', + 'TA_PERF_SEL_flat_atomic_wavefronts', + 'TA_PERF_SEL_flat_load_wavefronts', + 'TA_PERF_SEL_flat_store_wavefronts', + 'TA_PERF_SEL_flat_total_cycles', 'TA_PERF_SEL_flat_wavefronts', + 'TA_PERF_SEL_gradient_busy', + 'TA_PERF_SEL_gradient_clk_valid_cycles', + 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', + 'TA_PERF_SEL_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_harvestable_register_clk_enabled_cycles', + 'TA_PERF_SEL_ibubble_16to31_cycle_burst', + 'TA_PERF_SEL_ibubble_1_cycle_burst', + 'TA_PERF_SEL_ibubble_2to3_cycle_burst', + 'TA_PERF_SEL_ibubble_32to63_cycle_burst', + 'TA_PERF_SEL_ibubble_4to15_cycle_burst', + 'TA_PERF_SEL_ibubble_ge64_cycle_burst', + 'TA_PERF_SEL_image_atomic_wavefronts', + 'TA_PERF_SEL_image_bvh_11_input_vgpr_instructions', + 'TA_PERF_SEL_image_bvh_12_input_vgpr_instructions', + 'TA_PERF_SEL_image_bvh_1_op_burst', + 'TA_PERF_SEL_image_bvh_2to3_op_burst', + 'TA_PERF_SEL_image_bvh_4to7_op_burst', + 'TA_PERF_SEL_image_bvh_8_input_vgpr_instructions', + 'TA_PERF_SEL_image_bvh_9_input_vgpr_instructions', + 'TA_PERF_SEL_image_bvh_ge8_op_burst', + 'TA_PERF_SEL_image_linked_1_op_burst', + 'TA_PERF_SEL_image_linked_2to3_op_burst', + 'TA_PERF_SEL_image_linked_4to7_op_burst', + 'TA_PERF_SEL_image_linked_ge8_op_burst', + 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_1_op_burst', + 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_2to3_op_burst', + 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_4to31_op_burst', + 'TA_PERF_SEL_image_nosampler_ge32_op_burst', + 'TA_PERF_SEL_image_nosampler_has_q_instructions', + 'TA_PERF_SEL_image_nosampler_has_r_instructions', + 'TA_PERF_SEL_image_nosampler_has_t_instructions', + 'TA_PERF_SEL_image_nosampler_total_cycles', + 'TA_PERF_SEL_image_read_wavefronts', + 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_1_op_burst', + 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_2to3_op_burst', + 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_4to7_op_burst', + 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_ge8_op_burst', + 'TA_PERF_SEL_image_sampler_has_bias_instructions', + 'TA_PERF_SEL_image_sampler_has_dr_instructions', + 'TA_PERF_SEL_image_sampler_has_ds_instructions', + 'TA_PERF_SEL_image_sampler_has_dt_instructions', + 'TA_PERF_SEL_image_sampler_has_offset_instructions', + 'TA_PERF_SEL_image_sampler_has_q_instructions', + 'TA_PERF_SEL_image_sampler_has_r_instructions', + 'TA_PERF_SEL_image_sampler_has_reference_instructions', + 'TA_PERF_SEL_image_sampler_has_t_instructions', + 'TA_PERF_SEL_image_sampler_total_cycles', + 'TA_PERF_SEL_image_sampler_wavefronts', + 'TA_PERF_SEL_image_store_wavefronts', + 'TA_PERF_SEL_image_wavefronts', 'TA_PERF_SEL_in_addr_cycles', + 'TA_PERF_SEL_in_busy', 'TA_PERF_SEL_in_cfifo_busy', + 'TA_PERF_SEL_in_data_cycles', 'TA_PERF_SEL_in_fifos_busy', + 'TA_PERF_SEL_in_qfifo_busy', 'TA_PERF_SEL_in_rfifo_busy', + 'TA_PERF_SEL_in_waiting_on_req_cycles', + 'TA_PERF_SEL_in_wfifo_busy', + 'TA_PERF_SEL_latency_ram_ref_required_instructions', + 'TA_PERF_SEL_latency_ram_weights_written_cycles', + 'TA_PERF_SEL_latency_ram_whv_required_instructions', + 'TA_PERF_SEL_latency_ram_whv_required_quads', + 'TA_PERF_SEL_latency_ram_ws_required_instructions', + 'TA_PERF_SEL_latency_ram_ws_required_quads', + 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', 'TA_PERF_SEL_lod_busy', + 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_quads', + 'TA_PERF_SEL_mip_2_cycle_quads', + 'TA_PERF_SEL_mipmap_invalid_samples', + 'TA_PERF_SEL_mipmap_lod_0_samples', + 'TA_PERF_SEL_mipmap_lod_10_samples', + 'TA_PERF_SEL_mipmap_lod_11_samples', + 'TA_PERF_SEL_mipmap_lod_12_samples', + 'TA_PERF_SEL_mipmap_lod_13_samples', + 'TA_PERF_SEL_mipmap_lod_14_samples', + 'TA_PERF_SEL_mipmap_lod_1_samples', + 'TA_PERF_SEL_mipmap_lod_2_samples', + 'TA_PERF_SEL_mipmap_lod_3_samples', + 'TA_PERF_SEL_mipmap_lod_4_samples', + 'TA_PERF_SEL_mipmap_lod_5_samples', + 'TA_PERF_SEL_mipmap_lod_6_samples', + 'TA_PERF_SEL_mipmap_lod_7_samples', + 'TA_PERF_SEL_mipmap_lod_8_samples', + 'TA_PERF_SEL_mipmap_lod_9_samples', + 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_nonsampler_clk_valid_cycles', 'TA_PERF_SEL_ns_busy', + 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', + 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', + 'TA_PERF_SEL_num_of_bvh_invalidated_first_tri', + 'TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri', + 'TA_PERF_SEL_num_of_bvh_invalidated_fp16_box', + 'TA_PERF_SEL_num_of_bvh_invalidated_fp32_box', + 'TA_PERF_SEL_num_of_bvh_invalidated_second_tri', + 'TA_PERF_SEL_num_of_bvh_invalidated_third_tri', + 'TA_PERF_SEL_num_of_bvh_valid_first_tri', + 'TA_PERF_SEL_num_of_bvh_valid_fourth_tri', + 'TA_PERF_SEL_num_of_bvh_valid_fp16_box', + 'TA_PERF_SEL_num_of_bvh_valid_fp32_box', + 'TA_PERF_SEL_num_of_bvh_valid_second_tri', + 'TA_PERF_SEL_num_of_bvh_valid_third_tri', + 'TA_PERF_SEL_num_unlit_nodes_ta_opt', + 'TA_PERF_SEL_point_sampled_quads', + 'TA_PERF_SEL_register_clk_valid_cycles', + 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', + 'TA_PERF_SEL_sampler_clk_valid_cycles', + 'TA_PERF_SEL_sampler_op_quads', 'TA_PERF_SEL_smp_busy_ns_idle', + 'TA_PERF_SEL_smp_idle_ns_busy', + 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', + 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', + 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', + 'TA_PERF_SEL_store_has_w_instructions', + 'TA_PERF_SEL_store_has_x_instructions', + 'TA_PERF_SEL_store_has_y_instructions', + 'TA_PERF_SEL_store_has_z_instructions', + 'TA_PERF_SEL_store_write_data_input_cycles', + 'TA_PERF_SEL_store_write_data_output_cycles', + 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', + 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', + 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', + 'TA_PERF_SEL_ta_busy', 'TA_PERF_SEL_tcreq_clk_valid_cycles', + 'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vmemcmd_cycles', + 'TA_PERF_SEL_vmemreq_cycles', 'TA_PERF_SEL_vol_1_cycle_quads', + 'TA_PERF_SEL_vol_2_cycle_quads', 'TA_PERF_SEL_walker_cycles', + 'TA_PERF_SEL_write_1_op_burst', 'TA_PERF_SEL_write_2to3_op_burst', + 'TA_PERF_SEL_write_4to31_op_burst', + 'TA_PERF_SEL_write_data_clk_valid_cycles', + 'TA_PERF_SEL_write_ge32_op_burst', 'TA_PERF_SEL_write_path_busy', + 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', + 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', + 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', + 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', + 'TA_TC_REQ_MODES', 'TA_TC_REQ_MODE_BORDER', 'TA_TC_REQ_MODE_BYTE', + 'TA_TC_REQ_MODE_BYTE_NV', 'TA_TC_REQ_MODE_DWORD', + 'TA_TC_REQ_MODE_NORMAL', 'TA_TC_REQ_MODE_TEX0', + 'TA_TC_REQ_MODE_TEX1', 'TA_TC_REQ_MODE_TEX2', 'TB_ACP_NOT_SEND', + 'TB_ACP_PKT_SEND', 'TB_ACR_0_MULTIPLE_RESERVED', + 'TB_ACR_1_MULTIPLE', 'TB_ACR_2_MULTIPLE', + 'TB_ACR_3_MULTIPLE_RESERVED', 'TB_ACR_4_MULTIPLE', + 'TB_ACR_5_MULTIPLE_RESERVED', 'TB_ACR_6_MULTIPLE_RESERVED', + 'TB_ACR_7_MULTIPLE_RESERVED', 'TB_ACR_CONT_DISABLE', + 'TB_ACR_CONT_ENABLE', 'TB_ACR_NOT_SEND', + 'TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', 'TB_ACR_PKT_SEND', + 'TB_ACR_SELECT_32K', 'TB_ACR_SELECT_44K', 'TB_ACR_SELECT_48K', + 'TB_ACR_SELECT_HW', 'TB_ACR_SOURCE_HW', 'TB_ACR_SOURCE_SW', + 'TB_AUDIO_INFO_CONT_DISABLE', 'TB_AUDIO_INFO_CONT_ENABLE', + 'TB_AUDIO_INFO_NOT_SEND', 'TB_AUDIO_INFO_PKT_SEND', + 'TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', + 'TB_BORROW_MODE_ACTIVE', 'TB_BORROW_MODE_BLANK', + 'TB_BORROW_MODE_NONE', 'TB_BORROW_MODE_RESERVED', + 'TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES', 'TB_CRC_ACTIVE_TRIBYTES', + 'TB_CRC_ALL_TRIBYTES', 'TB_CRC_DATAISLAND_TRIBYTES', + 'TB_CRC_DEEP_COLOR_PACKER', 'TB_CRC_DSC_PACKER', + 'TB_CRC_ENCRYPTOR_INPUT', 'TB_CRC_TB_ENC_INPUT', + 'TB_DEEP_COLOR_DEPTH_24BPP', 'TB_DEEP_COLOR_DEPTH_30BPP', + 'TB_DEEP_COLOR_DEPTH_36BPP', 'TB_DEEP_COLOR_DEPTH_RESERVED', + 'TB_DEFAULT_PHASE_IS_0', 'TB_DEFAULT_PHASE_IS_1', 'TB_DISABLE', + 'TB_DSC_444_RGB', 'TB_DSC_DISABLE', 'TB_DSC_NATIVE_422_420', + 'TB_ENABLE', 'TB_GC_AVMUTE_CONT_DISABLE', + 'TB_GC_AVMUTE_CONT_ENABLE', 'TB_GC_AVMUTE_SET', + 'TB_GC_AVMUTE_UNSET', 'TB_GC_CONT_DISABLE', 'TB_GC_CONT_ENABLE', + 'TB_GC_NOT_SEND', 'TB_GC_PKT_SEND', 'TB_GENERIC_CONT_DISABLE', + 'TB_GENERIC_CONT_ENABLE', 'TB_GENERIC_NOT_SEND', + 'TB_GENERIC_PKT_SEND', 'TB_ISRC_CONT_DISABLE', + 'TB_ISRC_CONT_ENABLE', 'TB_ISRC_NOT_SEND', 'TB_ISRC_PKT_SEND', + 'TB_METADATA_NOT_SEND', 'TB_METADATA_PKT_SEND', 'TB_NOT_RESET', + 'TB_NOT_SYNC_PHASE_ON_FRAME_START', 'TB_NO_ERROR_OCCURRED', + 'TB_OVERFLOW_OCCURRED', 'TB_PIXEL_ENCODING_420', + 'TB_PIXEL_ENCODING_422', 'TB_PIXEL_ENCODING_444_RGB', + 'TB_PKT_LINE_REF_END_OF_ACTIVE', 'TB_PKT_LINE_REF_OTGSOF', + 'TB_RESET', 'TB_SYNC_PHASE_ON_FRAME_START', 'TCC_CACHE_POLICIES', + 'TCC_CACHE_POLICY_LRU', 'TCC_CACHE_POLICY_STREAM', 'TCC_MTYPE', + 'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT', + 'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT', + 'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES', + 'TCP_CACHE_STORE_POLICY_WT_EVICT', + 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL', + 'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0', + 'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2', + 'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1', + 'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE', + 'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN', + 'TCP_OPCODE_ATOMIC', 'TCP_OPCODE_ATOMIC_CMPSWAP', + 'TCP_OPCODE_GATHERH', 'TCP_OPCODE_INV', 'TCP_OPCODE_LOAD', + 'TCP_OPCODE_READ', 'TCP_OPCODE_SAMPLER', 'TCP_OPCODE_TYPE', + 'TCP_OPCODE_WRITE', 'TCP_PERFCOUNT_SELECT', + 'TCP_PERF_SEL_ALLOC_STALL', + 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', + 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', + 'TCP_PERF_SEL_DATA_FIFO_STALL', 'TCP_PERF_SEL_GATE_EN1', + 'TCP_PERF_SEL_GATE_EN2', 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', + 'TCP_PERF_SEL_GL1_PENDING_STALL', 'TCP_PERF_SEL_GL1_READ_LATENCY', + 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', + 'TCP_PERF_SEL_GL1_REQ_READ', 'TCP_PERF_SEL_GL1_REQ_READ_128B', + 'TCP_PERF_SEL_GL1_REQ_READ_64B', 'TCP_PERF_SEL_GL1_REQ_WRITE', + 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', + 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', + 'TCP_PERF_SEL_GL1_WRITE_LATENCY', 'TCP_PERF_SEL_LFIFO_STALL', + 'TCP_PERF_SEL_LOD_STALL', 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', + 'TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL', + 'TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL', 'TCP_PERF_SEL_POWER_STALL', + 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', + 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', 'TCP_PERF_SEL_REQ', + 'TCP_PERF_SEL_REQ_MISS', 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', + 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', + 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', + 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', 'TCP_PERF_SEL_REQ_NON_READ', + 'TCP_PERF_SEL_REQ_READ', 'TCP_PERF_SEL_REQ_READ_HIT_EVICT', + 'TCP_PERF_SEL_REQ_READ_HIT_LRU', + 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', + 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', + 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', + 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', + 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', 'TCP_PERF_SEL_REQ_WRITE', + 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', + 'TCP_PERF_SEL_REQ_WRITE_MISS_LRU', 'TCP_PERF_SEL_TA_REQ', + 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', + 'TCP_PERF_SEL_TA_REQ_GL0_INV', 'TCP_PERF_SEL_TA_REQ_READ', + 'TCP_PERF_SEL_TA_REQ_STATE_READ', 'TCP_PERF_SEL_TA_REQ_WRITE', + 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', 'TCP_PERF_SEL_TCP_LATENCY', + 'TCP_PERF_SEL_TCP_TA_REQ_STALL', + 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', 'TCP_PERF_SEL_TD_TCP_STALL', + 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', + 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', + 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', 'TCP_WATCH_MODES', + 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', + 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', 'TC_EA_CID', + 'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', + 'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', + 'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', + 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', + 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', 'TC_NACKS', + 'TC_NACK_DATA_ERROR', 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', + 'TC_NACK_PROTECTION_FAULT', 'TC_OP', 'TC_OP_ATOMIC_ADD_32', + 'TC_OP_ATOMIC_ADD_64', 'TC_OP_ATOMIC_ADD_RTN_32', + 'TC_OP_ATOMIC_ADD_RTN_64', 'TC_OP_ATOMIC_AND_32', + 'TC_OP_ATOMIC_AND_64', 'TC_OP_ATOMIC_AND_RTN_32', + 'TC_OP_ATOMIC_AND_RTN_64', 'TC_OP_ATOMIC_CMPSWAP_32', + 'TC_OP_ATOMIC_CMPSWAP_64', 'TC_OP_ATOMIC_CMPSWAP_RTN_32', + 'TC_OP_ATOMIC_CMPSWAP_RTN_64', 'TC_OP_ATOMIC_DEC_32', + 'TC_OP_ATOMIC_DEC_64', 'TC_OP_ATOMIC_DEC_RTN_32', + 'TC_OP_ATOMIC_DEC_RTN_64', 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', + 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', + 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', + 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', + 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', + 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', + 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', + 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', + 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', + 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', + 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', + 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', + 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', + 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', + 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', + 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', + 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', + 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', + 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', + 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', + 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', + 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', + 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', + 'TC_OP_READ', 'TC_OP_RESERVED_FADD_32', + 'TC_OP_RESERVED_FADD_RTN_32', 'TC_OP_RESERVED_FOP_32_0', + 'TC_OP_RESERVED_FOP_32_2', 'TC_OP_RESERVED_FOP_64_0', + 'TC_OP_RESERVED_FOP_64_1', 'TC_OP_RESERVED_FOP_64_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_2', + 'TC_OP_RESERVED_FOP_RTN_64_0', 'TC_OP_RESERVED_FOP_RTN_64_1', + 'TC_OP_RESERVED_FOP_RTN_64_2', 'TC_OP_RESERVED_NON_FLOAT_32_1', + 'TC_OP_RESERVED_NON_FLOAT_32_2', 'TC_OP_RESERVED_NON_FLOAT_32_3', + 'TC_OP_RESERVED_NON_FLOAT_32_4', 'TC_OP_RESERVED_NON_FLOAT_64_1', + 'TC_OP_RESERVED_NON_FLOAT_64_2', 'TC_OP_RESERVED_NON_FLOAT_64_3', + 'TC_OP_RESERVED_NON_FLOAT_64_4', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', + 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', + 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', + 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', + 'TD_PERF_SEL_address_cmd_poison', + 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', + 'TD_PERF_SEL_blend_prt_with_prt_default_0', + 'TD_PERF_SEL_blend_prt_with_prt_default_1', + 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', + 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', + 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', + 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', + 'TD_PERF_SEL_burst_bin_bvh4_1', 'TD_PERF_SEL_burst_bin_bvh4_2to8', + 'TD_PERF_SEL_burst_bin_bvh4_9to16', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_1', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16', + 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1', + 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8', + 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16', + 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16', + 'TD_PERF_SEL_burst_bin_bvh4_gt16', + 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1', + 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8', + 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16', + 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16', + 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1', + 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8', + 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16', + 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16', + 'TD_PERF_SEL_burst_bin_gather_1', + 'TD_PERF_SEL_burst_bin_gather_2to8', + 'TD_PERF_SEL_burst_bin_gather_9to16', + 'TD_PERF_SEL_burst_bin_gather_gt16', + 'TD_PERF_SEL_burst_bin_nofilter_1', + 'TD_PERF_SEL_burst_bin_nofilter_2to4', + 'TD_PERF_SEL_burst_bin_nofilter_5to7', + 'TD_PERF_SEL_burst_bin_nofilter_8to16', + 'TD_PERF_SEL_burst_bin_nofilter_gt16', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', + 'TD_PERF_SEL_burst_bin_sampler_1', + 'TD_PERF_SEL_burst_bin_sampler_2to8', + 'TD_PERF_SEL_burst_bin_sampler_9to16', + 'TD_PERF_SEL_burst_bin_sampler_gt16', + 'TD_PERF_SEL_bypassLerp_instr', + 'TD_PERF_SEL_core_state_ram_max_cnt', + 'TD_PERF_SEL_core_state_rams_read', 'TD_PERF_SEL_d16_en_instr', + 'TD_PERF_SEL_data_poison', + 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', + 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', + 'TD_PERF_SEL_done_scoreboard_is_full', + 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', + 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', + 'TD_PERF_SEL_done_scoreboard_not_empty', + 'TD_PERF_SEL_four_comp_return_instr', 'TD_PERF_SEL_gather4_instr', + 'TD_PERF_SEL_gather4h_instr', + 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', + 'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_input_state_fifo_full', + 'TD_PERF_SEL_instruction_dest_is_lds', 'TD_PERF_SEL_ldfptr_instr', + 'TD_PERF_SEL_lds_stall', 'TD_PERF_SEL_load_instr', + 'TD_PERF_SEL_lod_warn_from_ta', + 'TD_PERF_SEL_min_max_filter_instr', 'TD_PERF_SEL_mixmode_instr', + 'TD_PERF_SEL_mixmode_resource', 'TD_PERF_SEL_msaa_load_instr', + 'TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off', + 'TD_PERF_SEL_nofilter_busy', + 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', + 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', + 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', + 'TD_PERF_SEL_nofilter_d16_sclk_en', + 'TD_PERF_SEL_nofilter_d32_sclk_en', + 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', + 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', + 'TD_PERF_SEL_nofilter_formatters_turned_on', + 'TD_PERF_SEL_nofilter_insert_extra_comps', + 'TD_PERF_SEL_nofilter_pkr_full', + 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', + 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', + 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', + 'TD_PERF_SEL_nofilter_sclk_en', + 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', + 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', 'TD_PERF_SEL_none', + 'TD_PERF_SEL_one_comp_return_instr', + 'TD_PERF_SEL_opaque_black_border', + 'TD_PERF_SEL_out_of_order_instr', + 'TD_PERF_SEL_preempting_nofilter_max_cnt', + 'TD_PERF_SEL_prt_ack_instr', + 'TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero', + 'TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en', + 'TD_PERF_SEL_ray_tracing_bvh4_box_sort_en', + 'TD_PERF_SEL_ray_tracing_bvh4_busy', + 'TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node', + 'TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node', + 'TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node', + 'TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node', + 'TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt', + 'TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node', + 'TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node', + 'TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en', + 'TD_PERF_SEL_ray_tracing_bvh4_num_box_misses', + 'TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan', + 'TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx', + 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses', + 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers', + 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx', + 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full', + 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb', + 'TD_PERF_SEL_ray_tracing_bvh4_sclk_en', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16', + 'TD_PERF_SEL_ray_tracing_bvh4_tri_node', + 'TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en', + 'TD_PERF_SEL_reference_data_rams_read', + 'TD_PERF_SEL_resmap_instr', + 'TD_PERF_SEL_resmap_with_aniso_filtering', + 'TD_PERF_SEL_resmap_with_cubemap_corner', + 'TD_PERF_SEL_resmap_with_no_more_filtering', + 'TD_PERF_SEL_resmap_with_volume_filtering', + 'TD_PERF_SEL_sample_c_instr', 'TD_PERF_SEL_sample_instr', + 'TD_PERF_SEL_sampler_accum_sclk_en', + 'TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off', + 'TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off', + 'TD_PERF_SEL_sampler_bilerp_sclk_en', + 'TD_PERF_SEL_sampler_bypass_sclk_en', + 'TD_PERF_SEL_sampler_core_sclk_en', + 'TD_PERF_SEL_sampler_format_flt_sclk_en', + 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', + 'TD_PERF_SEL_sampler_lerp0_active', + 'TD_PERF_SEL_sampler_lerp1_active', + 'TD_PERF_SEL_sampler_lerp2_active', + 'TD_PERF_SEL_sampler_lerp3_active', + 'TD_PERF_SEL_sampler_lerp_busy', + 'TD_PERF_SEL_sampler_minmax_sclk_en', + 'TD_PERF_SEL_sampler_out_busy', 'TD_PERF_SEL_sampler_out_sclk_en', + 'TD_PERF_SEL_sampler_pkr_full', + 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', + 'TD_PERF_SEL_sampler_preformatter_sclk_en', + 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', + 'TD_PERF_SEL_status_packet', 'TD_PERF_SEL_ta_data_stall', + 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', + 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', + 'TD_PERF_SEL_tc_data_stall', 'TD_PERF_SEL_tc_ram_stall', + 'TD_PERF_SEL_tc_td_data_fifo_full', + 'TD_PERF_SEL_tc_td_ram_fifo_full', + 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', 'TD_PERF_SEL_td_busy', + 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', + 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', + 'TD_PERF_SEL_three_comp_return_instr', + 'TD_PERF_SEL_total_num_instr', + 'TD_PERF_SEL_total_num_instr_with_perf_wdw', + 'TD_PERF_SEL_total_num_nofilter_instr', + 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', + 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr', + 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw', + 'TD_PERF_SEL_total_num_sampler_instr', + 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', + 'TD_PERF_SEL_two_comp_return_instr', + 'TD_PERF_SEL_user_defined_border', + 'TD_PERF_SEL_weight_data_rams_read', 'TD_PERF_SEL_white_border', + 'TD_PERF_SEL_write_ack_instr', 'TESS_ISOLINE', 'TESS_QUAD', + 'TESS_TRIANGLE', 'TEST_CLK_DIV_SEL', 'TEST_CLK_SEL', + 'TEST_CLK_SEL_0', 'TEST_CLK_SEL_1', 'TEST_CLK_SEL_2', + 'TEST_CLK_SEL_3', 'TEST_CLK_SEL_4', 'TEST_CLK_SEL_5', + 'TEST_CLK_SEL_6', 'TEST_CLK_SEL_7', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', 'TEST_CLOCK_MUX_SELECT_ENUM', + 'TEX_BC_SWIZZLE', 'TEX_BC_Swizzle_WXYZ', 'TEX_BC_Swizzle_WZYX', + 'TEX_BC_Swizzle_XWYZ', 'TEX_BC_Swizzle_XYZW', + 'TEX_BC_Swizzle_YXWZ', 'TEX_BC_Swizzle_ZYXW', + 'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack', + 'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register', + 'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP', + 'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', + 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', + 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', + 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', + 'TEX_Clamp_MirrorOnceHalfToBorder', + 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', + 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', + 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', + 'TEX_DepthCompareFunction_Always', + 'TEX_DepthCompareFunction_Equal', + 'TEX_DepthCompareFunction_Greater', + 'TEX_DepthCompareFunction_GreaterEqual', + 'TEX_DepthCompareFunction_Less', + 'TEX_DepthCompareFunction_LessEqual', + 'TEX_DepthCompareFunction_Never', + 'TEX_DepthCompareFunction_NotEqual', 'TEX_FORMAT_COMP', + 'TEX_FormatComp_RESERVED_3', 'TEX_FormatComp_Signed', + 'TEX_FormatComp_Unsigned', 'TEX_FormatComp_UnsignedBiased', + 'TEX_MAX_ANISO_RATIO', 'TEX_MIP_FILTER', + 'TEX_MaxAnisoRatio_16to1', 'TEX_MaxAnisoRatio_1to1', + 'TEX_MaxAnisoRatio_2to1', 'TEX_MaxAnisoRatio_4to1', + 'TEX_MaxAnisoRatio_8to1', 'TEX_MaxAnisoRatio_RESERVED_5', + 'TEX_MaxAnisoRatio_RESERVED_6', 'TEX_MaxAnisoRatio_RESERVED_7', + 'TEX_MipFilter_Linear', 'TEX_MipFilter_None', + 'TEX_MipFilter_Point', 'TEX_MipFilter_Point_Aniso_Adj', + 'TEX_REQUEST_SIZE', 'TEX_RequestSize_128B', + 'TEX_RequestSize_2X64B', 'TEX_RequestSize_32B', + 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', + 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', + 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', + 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', + 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', + 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', + 'THREAD_TRACE_DRAW', 'THREAD_TRACE_FINISH', 'THREAD_TRACE_MARKER', + 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TIGHT_PACK', + 'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP', + 'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', + 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', + 'TMDS_CTL0_DATA_MODULATION_BIT1', + 'TMDS_CTL0_DATA_MODULATION_BIT2', + 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', + 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', + 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', + 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', + 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', + 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', + 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', + 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', + 'TMDS_CTL1_DATA_MODULATION_BIT0', + 'TMDS_CTL1_DATA_MODULATION_BIT1', + 'TMDS_CTL1_DATA_MODULATION_BIT2', + 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', + 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', + 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', + 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', + 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', + 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', + 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', + 'TMDS_CTL2_DATA_MODULATION_BIT0', + 'TMDS_CTL2_DATA_MODULATION_BIT1', + 'TMDS_CTL2_DATA_MODULATION_BIT2', + 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', + 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', + 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', + 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', + 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', + 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', + 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', + 'TMDS_CTL3_DATA_MODULATION_BIT0', + 'TMDS_CTL3_DATA_MODULATION_BIT1', + 'TMDS_CTL3_DATA_MODULATION_BIT2', + 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', + 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', + 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', + 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', + 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', + 'TMDS_CTL3_PATTERN_OUT_ENABLE', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_MUX_SELECT', + 'TMDS_MUX_SELECT_B', 'TMDS_MUX_SELECT_G', 'TMDS_MUX_SELECT_R', + 'TMDS_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', + 'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422', + 'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', + 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', + 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', + 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', + 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', + 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', + 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', + 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', + 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', + 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', 'TRANSERR', + 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', + 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', + 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', + 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', + 'TRISTRIP', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', + 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', + 'TVX_Type_ValidVertexBuffer', 'UCONFIG_SPACE_END', + 'UCONFIG_SPACE_START', 'UNDEF', 'UNSIGNED', 'USE_MALL_FOR_CURSOR', + 'USE_MALL_FOR_CURSOR_0', 'USE_MALL_FOR_CURSOR_1', + 'USE_MALL_FOR_PSTATE_CHANGE', 'USE_MALL_FOR_PSTATE_CHANGE_0', + 'USE_MALL_FOR_PSTATE_CHANGE_1', 'USE_MALL_FOR_STATIC_SCREEN', + 'USE_MALL_FOR_STATIC_SCREEN_0', 'USE_MALL_FOR_STATIC_SCREEN_1', + 'UTCL0FaultType', 'UTCL0RequestType', 'UTCL0_TYPE_BYPASS', + 'UTCL0_TYPE_NORMAL', 'UTCL0_TYPE_SHOOTDOWN', + 'UTCL0_XNACK_NO_RETRY', 'UTCL0_XNACK_PRT', 'UTCL0_XNACK_RETRY', + 'UTCL0_XNACK_SUCCESS', 'UTCL1FaultType', 'UTCL1PerfSel', + 'UTCL1RequestType', 'UTCL1_PERF_SEL_BYPASS_REQS', + 'UTCL1_PERF_SEL_CP_INVREQS', 'UTCL1_PERF_SEL_HITS', + 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', + 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', + 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', + 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', 'UTCL1_PERF_SEL_MISSES', + 'UTCL1_PERF_SEL_NONE', 'UTCL1_PERF_SEL_RANGE_INVREQS', + 'UTCL1_PERF_SEL_REQS', 'UTCL1_PERF_SEL_RTNS', + 'UTCL1_PERF_SEL_STALL_MH_FULL', + 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', 'UTCL1_PERF_SEL_UTCL2_REQS', + 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', + 'UTCL1_PERF_SEL_UTCL2_RET_CNT', 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', + 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', + 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', + 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', + 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', + 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', 'UTCL1_TYPE_BYPASS', + 'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN', + 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY', + 'UTCL1_XNACK_SUCCESS', 'VGT_DETECT_ONE', 'VGT_DETECT_ZERO', + 'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE', 'VGT_DI_MAJOR_MODE_SELECT', + 'VGT_DI_PRIM_TYPE', 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', + 'VGT_DMA_BUF_RING', 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', + 'VGT_DMA_PTR_UPDATE', 'VGT_DMA_SWAP_16_BIT', + 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', 'VGT_DMA_SWAP_NONE', + 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', 'VGT_FLUSH', + 'VGT_GROUP_CONV_SEL', 'VGT_GRP_AUTO_PRIM', + 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', + 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_SINT_16', + 'VGT_GRP_SINT_32', 'VGT_GRP_UINT_16', 'VGT_GRP_UINT_32', + 'VGT_GS_MODE_TYPE', 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', + 'VGT_INDEX_32', 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', + 'VGT_OUTPATH_GS_BLOCK', 'VGT_OUTPATH_HS_BLOCK', + 'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT', + 'VGT_OUTPATH_TE_GS_BLOCK', 'VGT_OUTPATH_TE_OUTPUT', + 'VGT_OUTPATH_TE_PRIM_GEN', 'VGT_OUTPATH_VTX_REUSE', + 'VGT_OUT_2D_RECT', 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ', + 'VGT_OUT_PATCH', 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE', + 'VGT_OUT_RECT_V0', 'VGT_OUT_RECT_V1', 'VGT_OUT_RECT_V2', + 'VGT_OUT_RECT_V3', 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ', + 'VGT_POLICY_BYPASS', 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM', + 'VGT_RDREQ_POLICY', 'VGT_STAGES_ES_EN', 'VGT_STAGES_GS_EN', + 'VGT_STAGES_HS_EN', 'VGT_STAGES_LS_EN', 'VGT_STAGES_VS_EN', + 'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC', 'VGT_TESS_PARTITION', + 'VGT_TESS_TOPOLOGY', 'VGT_TESS_TYPE', 'VGT_TE_PRIM_INDEX_LINE', + 'VGT_TE_PRIM_INDEX_QUAD', 'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD', + 'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE', + 'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK', + 'VMEMCMD_RETURN_IN_ORDER', 'VMEMCMD_RETURN_IN_ORDER_READ', + 'VMEMCMD_RETURN_ORDER', 'VMEMCMD_RETURN_OUT_OF_ORDER', 'VMID_SZ', + 'VMPG_SIZE', 'VMPG_SIZE_4KB', 'VMPG_SIZE_64KB', 'VM_GROUP_SIZE', + 'VM_GROUP_SIZE_1024B', 'VM_GROUP_SIZE_128B', + 'VM_GROUP_SIZE_2048B', 'VM_GROUP_SIZE_256B', 'VM_GROUP_SIZE_512B', + 'VM_GROUP_SIZE_64B', 'VM_PG_SIZE_1024KB', 'VM_PG_SIZE_128KB', + 'VM_PG_SIZE_16KB', 'VM_PG_SIZE_2048KB', 'VM_PG_SIZE_256KB', + 'VM_PG_SIZE_32KB', 'VM_PG_SIZE_4KB', 'VM_PG_SIZE_512KB', + 'VM_PG_SIZE_64KB', 'VM_PG_SIZE_8KB', + 'VPG_MEM_DISABLE_MEM_PWR_CTRL', 'VPG_MEM_ENABLE_MEM_PWR_CTRL', + 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', 'VPG_MEM_NO_FORCE_REQ', + 'VPG_MEM_PWR_DIS_CTRL', 'VPG_MEM_PWR_FORCE_CTRL', + 'VREADY_AT_OR_AFTER_VSYNC', 'VREADY_BEFORE_VSYNC', + 'VRSCombinerModeSC', 'VRS_SHADING_RATE_16X_SSAA', + 'VRS_SHADING_RATE_1X1', 'VRS_SHADING_RATE_1X2', + 'VRS_SHADING_RATE_2X1', 'VRS_SHADING_RATE_2X2', + 'VRS_SHADING_RATE_2X4', 'VRS_SHADING_RATE_2X_SSAA', + 'VRS_SHADING_RATE_4X2', 'VRS_SHADING_RATE_4X4', + 'VRS_SHADING_RATE_4X_SSAA', 'VRS_SHADING_RATE_8X_SSAA', + 'VRS_SHADING_RATE_UNDEFINED0', 'VRS_SHADING_RATE_UNDEFINED1', + 'VRS_SHADING_RATE_UNDEFINED2', 'VRS_SHADING_RATE_UNDEFINED3', + 'VRS_SHADING_RATE_UNDEFINED4', 'VRSrate', 'VSYNC_CNT_LATCH_MASK', + 'VSYNC_CNT_LATCH_MASK_0', 'VSYNC_CNT_LATCH_MASK_1', + 'VSYNC_CNT_RESET_SEL', 'VSYNC_CNT_RESET_SEL_0', + 'VSYNC_CNT_RESET_SEL_1', 'VS_PARTIAL_FLUSH', + 'VS_STAGE_COPY_SHADER', 'VS_STAGE_DS', 'VS_STAGE_REAL', + 'VTG_SEL_0', 'VTG_SEL_1', 'VTG_SEL_2', 'VTG_SEL_3', 'VTG_SEL_4', + 'VTG_SEL_5', 'WAIT_SYNC', 'WATERMARK_MODE', 'WD_IA_DRAW_REG_XFER', + 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', + 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', + 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', + 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', + 'WD_IA_DRAW_REG_XFER_GE_CNTL', + 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', + 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', + 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', + 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', + 'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO', + 'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD', + 'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE', + 'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA', + 'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX', + 'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER', + 'WRITE_BASE_ONLY', 'WRITE_BOTH', 'WritePolicy', 'XNORM', + 'XNORM_A', 'XNORM_B', 'XTAL_REF_CLOCK_SOURCE_SEL', + 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', + 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', + 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'Y10_CbCr1010_420_PLANAR', + 'Y10_CrCb1010_420_PLANAR', 'Y12_CbCr1212_420_PLANAR', + 'Y12_CrCb1212_420_PLANAR', 'Y8_CbCr88_420_PLANAR', + 'Y8_CrCb88_420_PLANAR', 'YCbYCr10101010_422_PACKED', + 'YCbYCr12121212_422_PACKED', 'YCbYCr8888_422_PACKED', + 'YCrCbA16161616_10LSB', 'YCrCbA16161616_10MSB', + 'YCrCbA16161616_12LSB', 'YCrCbA16161616_12MSB', 'YCrCbA8888', + 'YCrYCb10101010_422_PACKED', 'YCrYCb12121212_422_PACKED', + 'YCrYCb8888_422_PACKED', 'Y_G_DATA_ONTO_ALPHA_PORT', + 'Y_G_DATA_ONTO_CB_B_PORT', 'Y_G_DATA_ONTO_CR_R_PORT', + 'Y_G_DATA_ONTO_Y_G_PORT', 'ZLimitSumm', 'ZModeForce', 'ZOrder', + 'ZPASS_DISABLE', 'ZPASS_PIXELS', 'ZPASS_SAMPLES', + 'ZSamplePosition', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID', + 'ZpassControl', '_soc21_ENUM_HEADER', 'ge1_assembler_busy', + 'ge1_assembler_dma_starved', 'ge1_assembler_stalled', + 'ge1_dma_busy', 'ge1_dma_lat_bin_0', 'ge1_dma_lat_bin_1', + 'ge1_dma_lat_bin_2', 'ge1_dma_lat_bin_3', 'ge1_dma_lat_bin_4', + 'ge1_dma_lat_bin_5', 'ge1_dma_lat_bin_6', 'ge1_dma_lat_bin_7', + 'ge1_dma_return_cl0', 'ge1_dma_return_cl1', + 'ge1_dma_return_size_cl0', 'ge1_dma_return_size_cl1', + 'ge1_dma_utcl1_consecutive_retry_event', + 'ge1_dma_utcl1_request_event', 'ge1_dma_utcl1_retry_event', + 'ge1_dma_utcl1_stall_event', 'ge1_dma_utcl1_stall_utcl2_event', + 'ge1_dma_utcl1_translation_hit_event', + 'ge1_dma_utcl1_translation_miss_event', 'ge1_pipe0_to_pipe1', + 'ge1_pipe1_to_pipe0', 'ge1_prim_group_limit_hit', + 'ge1_rbiu_di_fifo_stalled_p0', 'ge1_rbiu_di_fifo_stalled_p1', + 'ge1_rbiu_di_fifo_starved_p0', 'ge1_rbiu_di_fifo_starved_p1', + 'ge1_rbiu_dr_fifo_stalled_p0', 'ge1_rbiu_dr_fifo_stalled_p1', + 'ge1_rbiu_dr_fifo_starved_p0', 'ge1_rbiu_dr_fifo_starved_p1', + 'ge1_sclk_input_vld', 'ge1_sclk_reg_vld', + 'ge1_small_draws_one_instance', 'ge1_stat_busy', + 'ge1_stat_no_dma_busy', 'ge1_unopt_multi_instance_draws', + 'ge_agm_gcr_crd_stall', 'ge_agm_gcr_latency', 'ge_agm_gcr_req', + 'ge_agm_gcr_stall', 'ge_agm_gcr_tag_stall', 'ge_all_tf2', + 'ge_all_tf3', 'ge_all_tf4', 'ge_all_tf5', 'ge_all_tf6', + 'ge_all_tf_eq', 'ge_csb_spi_bp', 'ge_dist_distributer_busy', + 'ge_dist_hs_done', 'ge_dist_hs_done_latency', + 'ge_dist_hs_done_latency_se0', 'ge_dist_hs_done_latency_se1', + 'ge_dist_hs_done_latency_se2', 'ge_dist_hs_done_latency_se3', + 'ge_dist_hs_done_latency_se4', 'ge_dist_hs_done_latency_se5', + 'ge_dist_hs_done_latency_se6', 'ge_dist_hs_done_latency_se7', + 'ge_dist_hs_done_se0', 'ge_dist_hs_done_se1', + 'ge_dist_hs_done_se2', 'ge_dist_hs_done_se3', + 'ge_dist_hs_done_se4', 'ge_dist_hs_done_se5', + 'ge_dist_hs_done_se6', 'ge_dist_hs_done_se7', + 'ge_dist_inside_tf_bin_0', 'ge_dist_inside_tf_bin_1', + 'ge_dist_inside_tf_bin_2', 'ge_dist_inside_tf_bin_3', + 'ge_dist_inside_tf_bin_4', 'ge_dist_inside_tf_bin_5', + 'ge_dist_inside_tf_bin_6', 'ge_dist_inside_tf_bin_7', + 'ge_dist_inside_tf_bin_8', 'ge_dist_null_patch', + 'ge_dist_op_fifo_full_starve', 'ge_dist_pc_feorder_fifo_full', + 'ge_dist_pc_ge_manager_busy', 'ge_dist_pc_req_stall_se0', + 'ge_dist_pc_req_stall_se1', 'ge_dist_pc_req_stall_se2', + 'ge_dist_pc_req_stall_se3', 'ge_dist_pc_req_stall_se4', + 'ge_dist_pc_req_stall_se5', 'ge_dist_pc_req_stall_se6', + 'ge_dist_pc_req_stall_se7', 'ge_dist_pc_space_zero', + 'ge_dist_reserved', 'ge_dist_sclk_core_vld', + 'ge_dist_sclk_input_vld', 'ge_dist_sclk_wd_te11_vld', + 'ge_dist_switch_mode_stall', 'ge_dist_te11_starved', + 'ge_dist_tfreq_lat_bin_0', 'ge_dist_tfreq_lat_bin_1', + 'ge_dist_tfreq_lat_bin_2', 'ge_dist_tfreq_lat_bin_3', + 'ge_dist_tfreq_lat_bin_4', 'ge_dist_tfreq_lat_bin_5', + 'ge_dist_tfreq_lat_bin_6', 'ge_dist_tfreq_lat_bin_7', + 'ge_dist_tfreq_utcl1_consecutive_retry_event', + 'ge_dist_tfreq_utcl1_request_event', + 'ge_dist_tfreq_utcl1_retry_event', + 'ge_dist_tfreq_utcl1_stall_event', + 'ge_dist_tfreq_utcl1_stall_utcl2_event', + 'ge_dist_tfreq_utcl1_translation_hit_event', + 'ge_dist_tfreq_utcl1_translation_miss_event', + 'ge_dist_vs_pc_stall', 'ge_dist_wd_te11_busy', 'ge_distclk_vld', + 'ge_esvert_send', 'ge_gs_issue_rtr_stalled', 'ge_gsprim_send', + 'ge_gsprim_stalled_esvert', 'ge_gsthread_stalled', + 'ge_hs_stall_tfmm_fifo_full', 'ge_hs_tif_stall', + 'ge_ngg_agm_req_stall', 'ge_ngg_attr_discard_alloc', + 'ge_ngg_attr_grp_alloc', 'ge_ngg_attr_grp_latency', + 'ge_ngg_indx_bus_stall', 'ge_ngg_ord_id_req_stall', + 'ge_ngg_pc_space_not_avail', 'ge_ngg_reuse_prim_limit_hit', + 'ge_ngg_reuse_vert_limit_hit', 'ge_ngg_spi_esvert_partial_eov', + 'ge_ngg_spi_gsprim_partial_eov', 'ge_ngg_stall_tess_off_tess_on', + 'ge_ngg_stall_tess_on_tess_off', 'ge_ngg_starved_after_work', + 'ge_ngg_starved_idle', 'ge_ngg_starving_for_pc_grant', + 'ge_ngg_subgrp_fifo_stall', 'ge_num_of_donut_dist_patches', + 'ge_num_of_hs_alloc_events', 'ge_num_of_no_dist_patches', + 'ge_num_of_patch_dist_patches', + 'ge_num_of_se_switches_due_to_donut', + 'ge_num_of_se_switches_due_to_patch_accum', + 'ge_num_of_se_switches_due_to_trap', 'ge_pa0_csb_eop', + 'ge_pa1_csb_eop', 'ge_se0_te11_starved_on_hs_done', + 'ge_se1_te11_starved_on_hs_done', + 'ge_se2_te11_starved_on_hs_done', + 'ge_se3_te11_starved_on_hs_done', + 'ge_se4_te11_starved_on_hs_done', + 'ge_se5_te11_starved_on_hs_done', + 'ge_se6_te11_starved_on_hs_done', + 'ge_se7_te11_starved_on_hs_done', 'ge_se_ds_prims', + 'ge_se_es_thread_groups', 'ge_se_esvert_stalled_gsprim', + 'ge_se_hs_input_stall', 'ge_se_hs_tfm_stall', + 'ge_se_hs_tgs_active_high_water_mark', 'ge_se_hs_thread_groups', + 'ge_se_reused_es_indices', 'ge_se_sclk_input_vld', + 'ge_se_sclk_ngg_vld', 'ge_se_sclk_te11_vld', + 'ge_se_sending_vert_or_prim', 'ge_se_spi_esvert_eov', + 'ge_se_spi_esvert_stalled', 'ge_se_spi_esvert_starved_busy', + 'ge_se_spi_esvert_valid', 'ge_se_spi_gsprim_cont', + 'ge_se_spi_gsprim_eov', 'ge_se_spi_gsprim_stalled', + 'ge_se_spi_gsprim_starved_busy', 'ge_se_spi_gsprim_valid', + 'ge_se_spi_gssubgrp_event_window_active', + 'ge_se_spi_gssubgrp_is_event', 'ge_se_spi_gssubgrp_send', + 'ge_se_spi_hsvert_eov', 'ge_se_spi_hsvert_fifo_full_stall', + 'ge_se_spi_hsvert_stalled', 'ge_se_spi_hsvert_starved_busy', + 'ge_se_spi_hsvert_valid', 'ge_se_spi_hswave_is_event', + 'ge_se_spi_hswave_send', 'ge_se_spi_lsvert_eov', + 'ge_se_spi_lsvert_stalled', 'ge_se_spi_lsvert_starved_busy', + 'ge_se_spi_lsvert_valid', 'ge_se_spi_tgrp_fifo_stall', + 'ge_spi_gsgrp_valid', 'ge_spi_hsgrp_spi_stall', + 'ge_spi_hswave_fifo_full_stall', 'ge_spi_lswave_fifo_full_stall', + 'ge_te11_compactor_starved', 'ge_te11_con_stall', + 'ge_te11_stall_prim_funnel', 'ge_te11_stall_vert_funnel', + 'ge_tf_ret_data_stalling_hs_done'] diff --git a/tinygrad_repo/tinygrad/runtime/autogen/am/soc24.py b/tinygrad_repo/tinygrad/runtime/autogen/am/soc24.py new file mode 100644 index 000000000..42e5a6036 --- /dev/null +++ b/tinygrad_repo/tinygrad/runtime/autogen/am/soc24.py @@ -0,0 +1,37140 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_soc24_ENUM_HEADER = True # macro +CSDATA_TYPE_WIDTH = 0x00000002 # macro +CSDATA_ADDR_WIDTH = 0x00000007 # macro +CSDATA_DATA_WIDTH = 0x00000020 # macro +CSCNTL_TYPE_WIDTH = 0x00000002 # macro +CSCNTL_ADDR_WIDTH = 0x00000007 # macro +CSCNTL_DATA_WIDTH = 0x00000020 # macro +GSTHREADID_SIZE = 0x00000002 # macro +IQ_QUEUE_SLEEP = 0x00000000 # macro +IQ_OFFLOAD_RETRY = 0x00000001 # macro +IQ_SCH_WAVE_MSG = 0x00000002 # macro +IQ_DEQUEUE_RETRY = 0x00000004 # macro +IQ_INTR_TYPE_PQ = 0x00000000 # macro +IQ_INTR_TYPE_IB = 0x00000001 # macro +IQ_INTR_TYPE_MQD = 0x00000002 # macro +VMID_SZ = 0x00000004 # macro +CONFIG_SPACE_START = 0x00002000 # macro +CONFIG_SPACE_END = 0x00009fff # macro +CONFIG_SPACE1_START = 0x00002000 # macro +CONFIG_SPACE1_END = 0x00002bff # macro +CONFIG_SPACE2_START = 0x00003000 # macro +CONFIG_SPACE2_END = 0x00009fff # macro +UCONFIG_SPACE_START = 0x0000c000 # macro +UCONFIG_SPACE_END = 0x0000ffff # macro +PERSISTENT_SPACE_START = 0x00002c00 # macro +PERSISTENT_SPACE_END = 0x00002fff # macro +CONTEXT_SPACE_START = 0x0000a000 # macro +CONTEXT_SPACE_END = 0x0000a3ff # macro +SQ_WAVE_TYPE_PS0 = 0x00000000 # macro +SQ_FLAT = 0x00000000 # macro +SQ_SCRATCH = 0x00000001 # macro +SQ_GLOBAL = 0x00000002 # macro +SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro +SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro +SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro +SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro +SQIND_WAVE_HW_REGS_OFFSET = 0x00000100 # macro +SQIND_WAVE_HW_REGS_SIZE = 0x00000040 # macro +SQIND_WAVE_HOST_REGS_OFFSET = 0x00000140 # macro +SQIND_WAVE_HOST_REGS_SIZE = 0x000000c0 # macro +SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro +SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro +SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro +SQIND_WAVE_VGPRS_SIZE = 0x00000400 # macro +SQ_GFXDEC_BEGIN = 0x0000a000 # macro +SQ_GFXDEC_END = 0x0000c000 # macro +SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro +SQDEC_BEGIN = 0x00002300 # macro +SQDEC_END = 0x000023ff # macro +PFVF_SQDEC_BEGIN = 0x0000a9e0 # macro +PFVF_SQDEC_END = 0x0000a9ff # macro +SQPERFSDEC_BEGIN = 0x0000d9c0 # macro +SQPERFSDEC_END = 0x0000da40 # macro +SQPERFDDEC_BEGIN = 0x0000d1c0 # macro +SQPERFDDEC_END = 0x0000d240 # macro +SQGFXUDEC_BEGIN = 0x0000c330 # macro +SQGFXUDEC_END = 0x0000c380 # macro +SQPWRDEC_BEGIN = 0x0000f08c # macro +SQPWRDEC_END = 0x0000f094 # macro +SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro +SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro +SQ_MAX_PGM_SGPRS = 0x00000068 # macro +SQ_MAX_PGM_VGPRS = 0x00000100 # macro +SQ_EX_EXCP_VALU_BASE = 0x00000000 # macro +SQ_EX_EXCP_VALU_SIZE = 0x00000007 # macro +SQ_EX_EXCP_ALU_INVALID = 0x00000000 # macro +SQ_EX_EXCP_ALU_INPUT_DENORM = 0x00000001 # macro +SQ_EX_EXCP_ALU_FLOAT_DIV0 = 0x00000002 # macro +SQ_EX_EXCP_ALU_OVERFLOW = 0x00000003 # macro +SQ_EX_EXCP_ALU_UNDERFLOW = 0x00000004 # macro +SQ_EX_EXCP_ALU_INEXACT = 0x00000005 # macro +SQ_EX_EXCP_ALU_INT_DIV0 = 0x00000006 # macro +SQ_EX_EXCP_ADDR_WATCH = 0x00000007 # macro +INST_ID_PRIV_START = 0x80000000 # macro +INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro +INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro +INST_ID_HW_TRAP = 0xfffffff2 # macro +INST_ID_KILL_SEQ = 0xfffffff3 # macro +INST_ID_SPI_WREXEC = 0xfffffff4 # macro +INST_ID_HW_TRAP_GET_TBA = 0xfffffff5 # macro +INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro +SIMM16_WAITCNT_EXP_CNT_START = 0x00000000 # macro +SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_LGKM_CNT_START = 0x00000004 # macro +SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000006 # macro +SIMM16_WAITCNT_VM_CNT_START = 0x0000000a # macro +SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000006 # macro +SIMM16_WAITCNT_DEPCTR_SA_SDST_START = 0x00000000 # macro +SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_VCC_START = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VM_VSRC_START = 0x00000002 # macro +SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START = 0x00000007 # macro +SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_SSRC_START = 0x00000008 # macro +SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_SDST_START = 0x00000009 # macro +SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_DEPCTR_VA_VDST_START = 0x0000000c # macro +SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE = 0x00000004 # macro +SIMM16_WAIT_EVENT_EXP_RDY_START = 0x00000000 # macro +SIMM16_WAIT_EVENT_EXP_RDY_SIZE = 0x00000001 # macro +SQ_WAVE_IB_DEP_SA_SDST_SIZE = 0x00000004 # macro +SQ_WAVE_IB_DEP_SA_EXEC_SIZE = 0x00000002 # macro +SQ_WAVE_IB_DEP_SA_M0_SIZE = 0x00000001 # macro +SQ_WAVE_IB_DEP_VM_VSRC_SIZE = 0x00000004 # macro +SQ_WAVE_IB_DEP_HOLD_CNT_SIZE = 0x00000001 # macro +SQ_WAVE_IB_DEP_VA_SSRC_SIZE = 0x00000003 # macro +SQ_WAVE_IB_DEP_VA_SDST_SIZE = 0x00000004 # macro +SQ_WAVE_IB_DEP_VA_VCC_SIZE = 0x00000003 # macro +SQ_WAVE_IB_DEP_VA_EXEC_SIZE = 0x00000002 # macro +SQ_WAVE_IB_DEP_VA_VDST_SIZE = 0x00000005 # macro +SQ_WAVE_IB_DEP_LDS_DIR_SIZE = 0x00000003 # macro +SQ_ARB_STATE_ISSUED_BRMSG = 0x00000000 # macro +SQ_ARB_STATE_ISSUED_EXPORT = 0x00000001 # macro +SQ_ARB_STATE_ISSUED_LDS_DIRECT = 0x00000002 # macro +SQ_ARB_STATE_ISSUED_LDS = 0x00000003 # macro +SQ_ARB_STATE_ISSUED_TEX = 0x00000004 # macro +SQ_ARB_STATE_ISSUED_SCALAR = 0x00000005 # macro +SQ_ARB_STATE_ISSUED_VALU = 0x00000006 # macro +SQ_ARB_STATE_STALLED_BRMSG = 0x00000008 # macro +SQ_ARB_STATE_STALLED_EXPORT = 0x00000009 # macro +SQ_ARB_STATE_STALLED_LDS_DIRECT = 0x0000000a # macro +SQ_ARB_STATE_STALLED_LDS = 0x0000000b # macro +SQ_ARB_STATE_STALLED_TEX = 0x0000000c # macro +SQ_ARB_STATE_STALLED_SCALAR = 0x0000000d # macro +SQ_ARB_STATE_STALLED_VALU = 0x0000000e # macro +ROM_SIGNATURE = 0x0000aa55 # macro + +# values for enumeration 'CP_PERFMON_ENABLE_MODE' +CP_PERFMON_ENABLE_MODE__enumvalues = { + 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', + 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', +} +CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 +CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 +CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_STATE' +CP_PERFMON_STATE__enumvalues = { + 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'CP_PERFMON_STATE_START_COUNTING', + 2: 'CP_PERFMON_STATE_STOP_COUNTING', + 3: 'CP_PERFMON_STATE_RESERVED_3', + 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +CP_PERFMON_STATE_DISABLE_AND_RESET = 0 +CP_PERFMON_STATE_START_COUNTING = 1 +CP_PERFMON_STATE_STOP_COUNTING = 2 +CP_PERFMON_STATE_RESERVED_3 = 3 +CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +CP_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_NUM_SIMD_PER_CU' +ENUM_NUM_SIMD_PER_CU__enumvalues = { + 2: 'NUM_SIMD_PER_CU', +} +NUM_SIMD_PER_CU = 2 +ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum + +# values for enumeration 'GATCL1RequestType' +GATCL1RequestType__enumvalues = { + 0: 'GATCL1_TYPE_NORMAL', + 1: 'GATCL1_TYPE_SHOOTDOWN', + 2: 'GATCL1_TYPE_BYPASS', +} +GATCL1_TYPE_NORMAL = 0 +GATCL1_TYPE_SHOOTDOWN = 1 +GATCL1_TYPE_BYPASS = 2 +GATCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'GL0V_CACHE_POLICIES' +GL0V_CACHE_POLICIES__enumvalues = { + 0: 'GL0V_CACHE_POLICY_MISS_LRU', + 1: 'GL0V_CACHE_POLICY_MISS_EVICT', + 2: 'GL0V_CACHE_POLICY_HIT_LRU', + 3: 'GL0V_CACHE_POLICY_HIT_EVICT', + 4: 'GL0V_CACHE_POLICY_MISS_INVAL', +} +GL0V_CACHE_POLICY_MISS_LRU = 0 +GL0V_CACHE_POLICY_MISS_EVICT = 1 +GL0V_CACHE_POLICY_HIT_LRU = 2 +GL0V_CACHE_POLICY_HIT_EVICT = 3 +GL0V_CACHE_POLICY_MISS_INVAL = 4 +GL0V_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL1_CACHE_POLICIES' +GL1_CACHE_POLICIES__enumvalues = { + 0: 'GL1_CACHE_POLICY_MISS_LRU', + 1: 'GL1_CACHE_POLICY_MISS_EVICT', + 2: 'GL1_CACHE_POLICY_HIT_LRU', + 3: 'GL1_CACHE_POLICY_HIT_EVICT', +} +GL1_CACHE_POLICY_MISS_LRU = 0 +GL1_CACHE_POLICY_MISS_EVICT = 1 +GL1_CACHE_POLICY_HIT_LRU = 2 +GL1_CACHE_POLICY_HIT_EVICT = 3 +GL1_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL1_CACHE_STORE_POLICIES' +GL1_CACHE_STORE_POLICIES__enumvalues = { + 0: 'GL1_CACHE_STORE_POLICY_BYPASS', +} +GL1_CACHE_STORE_POLICY_BYPASS = 0 +GL1_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_CACHE_POLICIES' +GL2_CACHE_POLICIES__enumvalues = { + 0: 'GL2_CACHE_POLICY_LRU', + 1: 'GL2_CACHE_POLICY_STREAM', + 2: 'GL2_CACHE_POLICY_NOA', + 3: 'GL2_CACHE_POLICY_BYPASS', +} +GL2_CACHE_POLICY_LRU = 0 +GL2_CACHE_POLICY_STREAM = 1 +GL2_CACHE_POLICY_NOA = 2 +GL2_CACHE_POLICY_BYPASS = 3 +GL2_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_NACKS' +GL2_NACKS__enumvalues = { + 0: 'GL2_NACK_NO_FAULT', + 1: 'GL2_NACK_PAGE_FAULT', + 2: 'GL2_NACK_PROTECTION_FAULT', + 3: 'GL2_NACK_DATA_ERROR', +} +GL2_NACK_NO_FAULT = 0 +GL2_NACK_PAGE_FAULT = 1 +GL2_NACK_PROTECTION_FAULT = 2 +GL2_NACK_DATA_ERROR = 3 +GL2_NACKS = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_OP' +GL2_OP__enumvalues = { + 0: 'GL2_OP_READ', + 1: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', + 2: 'GL2_OP_ATOMIC_FMIN_RTN_32', + 3: 'GL2_OP_ATOMIC_FMAX_RTN_32', + 4: 'GL2_OP_ATOMIC_PK_ADD_FP16_RTN', + 5: 'GL2_OP_ATOMIC_FADD_RTN_32', + 6: 'GL2_OP_ATOMIC_PK_ADD_BF16_RTN', + 7: 'GL2_OP_ATOMIC_SWAP_RTN_32', + 8: 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', + 9: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 10: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 11: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 12: 'GL2_OP_PROBE_FILTER', + 13: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 14: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 15: 'GL2_OP_ATOMIC_ADD_RTN_32', + 16: 'GL2_OP_ATOMIC_SUB_RTN_32', + 17: 'GL2_OP_ATOMIC_SMIN_RTN_32', + 18: 'GL2_OP_ATOMIC_UMIN_RTN_32', + 19: 'GL2_OP_ATOMIC_SMAX_RTN_32', + 20: 'GL2_OP_ATOMIC_UMAX_RTN_32', + 21: 'GL2_OP_ATOMIC_AND_RTN_32', + 22: 'GL2_OP_ATOMIC_OR_RTN_32', + 23: 'GL2_OP_ATOMIC_XOR_RTN_32', + 24: 'GL2_OP_ATOMIC_INC_RTN_32', + 25: 'GL2_OP_ATOMIC_DEC_RTN_32', + 26: 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', + 27: 'GL2_OP_ATOMIC_COND_SUB_RTN_32', + 29: 'GL2_OP_UTC_PROBE', + 30: 'GL2_OP_LOAD_RESERVE', + 32: 'GL2_OP_WRITE', + 33: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', + 34: 'GL2_OP_ATOMIC_FMIN_RTN_64', + 35: 'GL2_OP_ATOMIC_FMAX_RTN_64', + 39: 'GL2_OP_ATOMIC_SWAP_RTN_64', + 40: 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', + 41: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 42: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 43: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 47: 'GL2_OP_ATOMIC_ADD_RTN_64', + 48: 'GL2_OP_ATOMIC_SUB_RTN_64', + 49: 'GL2_OP_ATOMIC_SMIN_RTN_64', + 50: 'GL2_OP_ATOMIC_UMIN_RTN_64', + 51: 'GL2_OP_ATOMIC_SMAX_RTN_64', + 52: 'GL2_OP_ATOMIC_UMAX_RTN_64', + 53: 'GL2_OP_ATOMIC_AND_RTN_64', + 54: 'GL2_OP_ATOMIC_OR_RTN_64', + 55: 'GL2_OP_ATOMIC_XOR_RTN_64', + 56: 'GL2_OP_ATOMIC_INC_RTN_64', + 57: 'GL2_OP_ATOMIC_DEC_RTN_64', + 59: 'GL2_OP_WRITE_ZERO_SIZE', + 61: 'GL2_OP_GL2_INV', + 62: 'GL2_OP_ATOMIC_STORE_COND_RTN', + 64: 'GL2_OP_GL1_INV', + 65: 'GL2_OP_ATOMIC_FCMPSWAP_32', + 66: 'GL2_OP_ATOMIC_FMIN_32', + 67: 'GL2_OP_ATOMIC_FMAX_32', + 68: 'GL2_OP_ATOMIC_PK_ADD_FP16', + 69: 'GL2_OP_ATOMIC_FADD_32', + 70: 'GL2_OP_ATOMIC_PK_ADD_BF16', + 71: 'GL2_OP_ATOMIC_SWAP_32', + 72: 'GL2_OP_ATOMIC_CMPSWAP_32', + 73: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 74: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 75: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 76: 'GL2_OP_ATOMIC_UMIN_8', + 77: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 79: 'GL2_OP_ATOMIC_ADD_32', + 80: 'GL2_OP_ATOMIC_SUB_32', + 81: 'GL2_OP_ATOMIC_SMIN_32', + 82: 'GL2_OP_ATOMIC_UMIN_32', + 83: 'GL2_OP_ATOMIC_SMAX_32', + 84: 'GL2_OP_ATOMIC_UMAX_32', + 85: 'GL2_OP_ATOMIC_AND_32', + 86: 'GL2_OP_ATOMIC_OR_32', + 87: 'GL2_OP_ATOMIC_XOR_32', + 88: 'GL2_OP_ATOMIC_INC_32', + 89: 'GL2_OP_ATOMIC_DEC_32', + 91: 'GL2_OP_NOP_RTN0', + 93: 'GL2_OP_GL2_WB', + 94: 'GL2_OP_FORCE_EXISTING_DATA_TO_DECOMPRESS', + 97: 'GL2_OP_ATOMIC_FCMPSWAP_64', + 98: 'GL2_OP_ATOMIC_FMIN_64', + 99: 'GL2_OP_ATOMIC_FMAX_64', + 103: 'GL2_OP_ATOMIC_SWAP_64', + 104: 'GL2_OP_ATOMIC_CMPSWAP_64', + 105: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 106: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 107: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 111: 'GL2_OP_ATOMIC_ADD_64', + 112: 'GL2_OP_ATOMIC_SUB_64', + 113: 'GL2_OP_ATOMIC_SMIN_64', + 114: 'GL2_OP_ATOMIC_UMIN_64', + 115: 'GL2_OP_ATOMIC_SMAX_64', + 116: 'GL2_OP_ATOMIC_UMAX_64', + 117: 'GL2_OP_ATOMIC_AND_64', + 118: 'GL2_OP_ATOMIC_OR_64', + 119: 'GL2_OP_ATOMIC_XOR_64', + 120: 'GL2_OP_ATOMIC_INC_64', + 121: 'GL2_OP_ATOMIC_DEC_64', + 122: 'GL2_OP_ATOMIC_UMAX_8', + 123: 'GL2_OP_NOP_ACK', + 125: 'GL2_OP_GL2_WBINV', + 126: 'GL2_OP_READ_COMPRESSION_KEY', +} +GL2_OP_READ = 0 +GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 +GL2_OP_ATOMIC_FMIN_RTN_32 = 2 +GL2_OP_ATOMIC_FMAX_RTN_32 = 3 +GL2_OP_ATOMIC_PK_ADD_FP16_RTN = 4 +GL2_OP_ATOMIC_FADD_RTN_32 = 5 +GL2_OP_ATOMIC_PK_ADD_BF16_RTN = 6 +GL2_OP_ATOMIC_SWAP_RTN_32 = 7 +GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 +GL2_OP_PROBE_FILTER = 12 +GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 +GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 +GL2_OP_ATOMIC_ADD_RTN_32 = 15 +GL2_OP_ATOMIC_SUB_RTN_32 = 16 +GL2_OP_ATOMIC_SMIN_RTN_32 = 17 +GL2_OP_ATOMIC_UMIN_RTN_32 = 18 +GL2_OP_ATOMIC_SMAX_RTN_32 = 19 +GL2_OP_ATOMIC_UMAX_RTN_32 = 20 +GL2_OP_ATOMIC_AND_RTN_32 = 21 +GL2_OP_ATOMIC_OR_RTN_32 = 22 +GL2_OP_ATOMIC_XOR_RTN_32 = 23 +GL2_OP_ATOMIC_INC_RTN_32 = 24 +GL2_OP_ATOMIC_DEC_RTN_32 = 25 +GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 26 +GL2_OP_ATOMIC_COND_SUB_RTN_32 = 27 +GL2_OP_UTC_PROBE = 29 +GL2_OP_LOAD_RESERVE = 30 +GL2_OP_WRITE = 32 +GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 +GL2_OP_ATOMIC_FMIN_RTN_64 = 34 +GL2_OP_ATOMIC_FMAX_RTN_64 = 35 +GL2_OP_ATOMIC_SWAP_RTN_64 = 39 +GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 40 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 +GL2_OP_ATOMIC_ADD_RTN_64 = 47 +GL2_OP_ATOMIC_SUB_RTN_64 = 48 +GL2_OP_ATOMIC_SMIN_RTN_64 = 49 +GL2_OP_ATOMIC_UMIN_RTN_64 = 50 +GL2_OP_ATOMIC_SMAX_RTN_64 = 51 +GL2_OP_ATOMIC_UMAX_RTN_64 = 52 +GL2_OP_ATOMIC_AND_RTN_64 = 53 +GL2_OP_ATOMIC_OR_RTN_64 = 54 +GL2_OP_ATOMIC_XOR_RTN_64 = 55 +GL2_OP_ATOMIC_INC_RTN_64 = 56 +GL2_OP_ATOMIC_DEC_RTN_64 = 57 +GL2_OP_WRITE_ZERO_SIZE = 59 +GL2_OP_GL2_INV = 61 +GL2_OP_ATOMIC_STORE_COND_RTN = 62 +GL2_OP_GL1_INV = 64 +GL2_OP_ATOMIC_FCMPSWAP_32 = 65 +GL2_OP_ATOMIC_FMIN_32 = 66 +GL2_OP_ATOMIC_FMAX_32 = 67 +GL2_OP_ATOMIC_PK_ADD_FP16 = 68 +GL2_OP_ATOMIC_FADD_32 = 69 +GL2_OP_ATOMIC_PK_ADD_BF16 = 70 +GL2_OP_ATOMIC_SWAP_32 = 71 +GL2_OP_ATOMIC_CMPSWAP_32 = 72 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 +GL2_OP_ATOMIC_UMIN_8 = 76 +GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 +GL2_OP_ATOMIC_ADD_32 = 79 +GL2_OP_ATOMIC_SUB_32 = 80 +GL2_OP_ATOMIC_SMIN_32 = 81 +GL2_OP_ATOMIC_UMIN_32 = 82 +GL2_OP_ATOMIC_SMAX_32 = 83 +GL2_OP_ATOMIC_UMAX_32 = 84 +GL2_OP_ATOMIC_AND_32 = 85 +GL2_OP_ATOMIC_OR_32 = 86 +GL2_OP_ATOMIC_XOR_32 = 87 +GL2_OP_ATOMIC_INC_32 = 88 +GL2_OP_ATOMIC_DEC_32 = 89 +GL2_OP_NOP_RTN0 = 91 +GL2_OP_GL2_WB = 93 +GL2_OP_FORCE_EXISTING_DATA_TO_DECOMPRESS = 94 +GL2_OP_ATOMIC_FCMPSWAP_64 = 97 +GL2_OP_ATOMIC_FMIN_64 = 98 +GL2_OP_ATOMIC_FMAX_64 = 99 +GL2_OP_ATOMIC_SWAP_64 = 103 +GL2_OP_ATOMIC_CMPSWAP_64 = 104 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 +GL2_OP_ATOMIC_ADD_64 = 111 +GL2_OP_ATOMIC_SUB_64 = 112 +GL2_OP_ATOMIC_SMIN_64 = 113 +GL2_OP_ATOMIC_UMIN_64 = 114 +GL2_OP_ATOMIC_SMAX_64 = 115 +GL2_OP_ATOMIC_UMAX_64 = 116 +GL2_OP_ATOMIC_AND_64 = 117 +GL2_OP_ATOMIC_OR_64 = 118 +GL2_OP_ATOMIC_XOR_64 = 119 +GL2_OP_ATOMIC_INC_64 = 120 +GL2_OP_ATOMIC_DEC_64 = 121 +GL2_OP_ATOMIC_UMAX_8 = 122 +GL2_OP_NOP_ACK = 123 +GL2_OP_GL2_WBINV = 125 +GL2_OP_READ_COMPRESSION_KEY = 126 +GL2_OP = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_OP_MASKS' +GL2_OP_MASKS__enumvalues = { + 8: 'GL2_OP_MASK_FLUSH_DENROM', + 32: 'GL2_OP_MASK_64', + 64: 'GL2_OP_MASK_NO_RTN', +} +GL2_OP_MASK_FLUSH_DENROM = 8 +GL2_OP_MASK_64 = 32 +GL2_OP_MASK_NO_RTN = 64 +GL2_OP_MASKS = ctypes.c_uint32 # enum + +# values for enumeration 'Hdp_SurfaceEndian' +Hdp_SurfaceEndian__enumvalues = { + 0: 'HDP_ENDIAN_NONE', + 1: 'HDP_ENDIAN_8IN16', + 2: 'HDP_ENDIAN_8IN32', + 3: 'HDP_ENDIAN_8IN64', +} +HDP_ENDIAN_NONE = 0 +HDP_ENDIAN_8IN16 = 1 +HDP_ENDIAN_8IN32 = 2 +HDP_ENDIAN_8IN64 = 3 +Hdp_SurfaceEndian = ctypes.c_uint32 # enum + +# values for enumeration 'MTYPE' +MTYPE__enumvalues = { + 0: 'MTYPE_C_RW_US', + 1: 'MTYPE_RESERVED_1', + 2: 'MTYPE_C_RO_S', + 3: 'MTYPE_UC', + 4: 'MTYPE_C_RW_S', + 5: 'MTYPE_RESERVED_5', + 6: 'MTYPE_C_RO_US', + 7: 'MTYPE_RESERVED_7', +} +MTYPE_C_RW_US = 0 +MTYPE_RESERVED_1 = 1 +MTYPE_C_RO_S = 2 +MTYPE_UC = 3 +MTYPE_C_RW_S = 4 +MTYPE_RESERVED_5 = 5 +MTYPE_C_RO_US = 6 +MTYPE_RESERVED_7 = 7 +MTYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_COUNTER_MODE' +PERFMON_COUNTER_MODE__enumvalues = { + 0: 'PERFMON_COUNTER_MODE_ACCUM', + 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 2: 'PERFMON_COUNTER_MODE_MAX', + 3: 'PERFMON_COUNTER_MODE_DIRTY', + 4: 'PERFMON_COUNTER_MODE_SAMPLE', + 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 15: 'PERFMON_COUNTER_MODE_RESERVED', +} +PERFMON_COUNTER_MODE_ACCUM = 0 +PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 +PERFMON_COUNTER_MODE_MAX = 2 +PERFMON_COUNTER_MODE_DIRTY = 3 +PERFMON_COUNTER_MODE_SAMPLE = 4 +PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 +PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 +PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 +PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 +PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 +PERFMON_COUNTER_MODE_RESERVED = 15 +PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_SPM_MODE' +PERFMON_SPM_MODE__enumvalues = { + 0: 'PERFMON_SPM_MODE_OFF', + 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', + 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', + 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 5: 'PERFMON_SPM_MODE_RESERVED_5', + 6: 'PERFMON_SPM_MODE_RESERVED_6', + 7: 'PERFMON_SPM_MODE_RESERVED_7', + 8: 'PERFMON_SPM_MODE_TEST_MODE_0', + 9: 'PERFMON_SPM_MODE_TEST_MODE_1', + 10: 'PERFMON_SPM_MODE_TEST_MODE_2', +} +PERFMON_SPM_MODE_OFF = 0 +PERFMON_SPM_MODE_16BIT_CLAMP = 1 +PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 +PERFMON_SPM_MODE_32BIT_CLAMP = 3 +PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 +PERFMON_SPM_MODE_RESERVED_5 = 5 +PERFMON_SPM_MODE_RESERVED_6 = 6 +PERFMON_SPM_MODE_RESERVED_7 = 7 +PERFMON_SPM_MODE_TEST_MODE_0 = 8 +PERFMON_SPM_MODE_TEST_MODE_1 = 9 +PERFMON_SPM_MODE_TEST_MODE_2 = 10 +PERFMON_SPM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'READ_COMPRESSION_MODE' +READ_COMPRESSION_MODE__enumvalues = { + 0: 'COMPRESSION_MODE_BYPASS_COMPRESSION', + 1: 'COMPRESSION_MODE_READ_RAW_COMPRESSED_DATA', + 2: 'COMPRESSION_MODE_READ_DECOMPRESSED', +} +COMPRESSION_MODE_BYPASS_COMPRESSION = 0 +COMPRESSION_MODE_READ_RAW_COMPRESSED_DATA = 1 +COMPRESSION_MODE_READ_DECOMPRESSED = 2 +READ_COMPRESSION_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ReadPolicy' +ReadPolicy__enumvalues = { + 0: 'CACHE_LRU_RD', + 1: 'CACHE_STREAM_RD', + 2: 'CACHE_NOA', + 3: 'RESERVED_RDPOLICY', +} +CACHE_LRU_RD = 0 +CACHE_STREAM_RD = 1 +CACHE_NOA = 2 +RESERVED_RDPOLICY = 3 +ReadPolicy = ctypes.c_uint32 # enum + +# values for enumeration 'SCOPE' +SCOPE__enumvalues = { + 0: 'SCOPE_CU', + 1: 'SCOPE_SE', + 2: 'SCOPE_DEV', + 3: 'SCOPE_SYS', +} +SCOPE_CU = 0 +SCOPE_SE = 1 +SCOPE_DEV = 2 +SCOPE_SYS = 3 +SCOPE = ctypes.c_uint32 # enum + +# values for enumeration 'SDMA_PERFMON_SEL' +SDMA_PERFMON_SEL__enumvalues = { + 0: 'SDMA_PERFMON_SEL_CYCLE', + 1: 'SDMA_PERFMON_SEL_IDLE', + 2: 'SDMA_PERFMON_SEL_REG_IDLE', + 3: 'SDMA_PERFMON_SEL_RB_EMPTY', + 4: 'SDMA_PERFMON_SEL_RB_FULL', + 5: 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', + 6: 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', + 7: 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', + 8: 'SDMA_PERFMON_SEL_RB_RPTR_WB', + 9: 'SDMA_PERFMON_SEL_RB_CMD_IDLE', + 10: 'SDMA_PERFMON_SEL_RB_CMD_FULL', + 11: 'SDMA_PERFMON_SEL_IB_CMD_IDLE', + 12: 'SDMA_PERFMON_SEL_IB_CMD_FULL', + 13: 'SDMA_PERFMON_SEL_EX_IDLE', + 14: 'SDMA_PERFMON_SEL_SRBM_REG_SEND', + 15: 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'SDMA_PERFMON_SEL_WR_BA_RTR', + 17: 'SDMA_PERFMON_SEL_MC_WR_IDLE', + 18: 'SDMA_PERFMON_SEL_MC_WR_COUNT', + 19: 'SDMA_PERFMON_SEL_RD_BA_RTR', + 20: 'SDMA_PERFMON_SEL_MC_RD_IDLE', + 21: 'SDMA_PERFMON_SEL_MC_RD_COUNT', + 22: 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', + 23: 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', + 26: 'SDMA_PERFMON_SEL_SEM_IDLE', + 27: 'SDMA_PERFMON_SEL_SEM_REQ_STALL', + 28: 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', + 29: 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', + 30: 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', + 31: 'SDMA_PERFMON_SEL_SEM_RESP_PASS', + 32: 'SDMA_PERFMON_SEL_INT_IDLE', + 33: 'SDMA_PERFMON_SEL_INT_REQ_STALL', + 34: 'SDMA_PERFMON_SEL_INT_REQ_COUNT', + 35: 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', + 36: 'SDMA_PERFMON_SEL_INT_RESP_RETRY', + 37: 'SDMA_PERFMON_SEL_NUM_PACKET', + 39: 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', + 40: 'SDMA_PERFMON_SEL_CE_WR_IDLE', + 41: 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', + 42: 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', + 43: 'SDMA_PERFMON_SEL_CE_OUT_IDLE', + 44: 'SDMA_PERFMON_SEL_CE_IN_IDLE', + 45: 'SDMA_PERFMON_SEL_CE_DST_IDLE', + 48: 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', + 49: 'SDMA_PERFMON_SEL_DUMMY_0', + 50: 'SDMA_PERFMON_SEL_DUMMY_1', + 51: 'SDMA_PERFMON_SEL_CE_INFO_FULL', + 52: 'SDMA_PERFMON_SEL_CE_INFO1_FULL', + 53: 'SDMA_PERFMON_SEL_CE_RD_STALL', + 54: 'SDMA_PERFMON_SEL_CE_WR_STALL', + 55: 'SDMA_PERFMON_SEL_QUEUE0_SELECT', + 56: 'SDMA_PERFMON_SEL_QUEUE1_SELECT', + 57: 'SDMA_PERFMON_SEL_QUEUE2_SELECT', + 58: 'SDMA_PERFMON_SEL_QUEUE3_SELECT', + 59: 'SDMA_PERFMON_SEL_CTX_CHANGE', + 60: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', + 61: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', + 62: 'SDMA_PERFMON_SEL_DOORBELL', + 63: 'SDMA_PERFMON_SEL_MCU_L1_WR_VLD', + 64: 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', + 65: 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', + 66: 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', + 67: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', + 68: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', + 69: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', + 70: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', + 71: 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', + 72: 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', + 73: 'SDMA_PERFMON_SEL_UTCL2_FREE', + 74: 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', + 75: 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', + 76: 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', + 77: 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', + 78: 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', + 79: 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', + 80: 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', + 81: 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', + 82: 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', + 83: 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', + 84: 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', + 85: 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', + 86: 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', + 87: 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', + 88: 'SDMA_PERFMON_SEL_L2_META_RET_VLD', + 89: 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', + 90: 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', + 91: 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', + 92: 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', + 93: 'SDMA_PERFMON_SEL_META_REQ_SEND', + 94: 'SDMA_PERFMON_SEL_META_RTN_VLD', + 95: 'SDMA_PERFMON_SEL_TLBI_SEND', + 96: 'SDMA_PERFMON_SEL_TLBI_RTN', + 97: 'SDMA_PERFMON_SEL_GCR_SEND', + 98: 'SDMA_PERFMON_SEL_GCR_RTN', + 99: 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', + 100: 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', +} +SDMA_PERFMON_SEL_CYCLE = 0 +SDMA_PERFMON_SEL_IDLE = 1 +SDMA_PERFMON_SEL_REG_IDLE = 2 +SDMA_PERFMON_SEL_RB_EMPTY = 3 +SDMA_PERFMON_SEL_RB_FULL = 4 +SDMA_PERFMON_SEL_RB_WPTR_WRAP = 5 +SDMA_PERFMON_SEL_RB_RPTR_WRAP = 6 +SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 7 +SDMA_PERFMON_SEL_RB_RPTR_WB = 8 +SDMA_PERFMON_SEL_RB_CMD_IDLE = 9 +SDMA_PERFMON_SEL_RB_CMD_FULL = 10 +SDMA_PERFMON_SEL_IB_CMD_IDLE = 11 +SDMA_PERFMON_SEL_IB_CMD_FULL = 12 +SDMA_PERFMON_SEL_EX_IDLE = 13 +SDMA_PERFMON_SEL_SRBM_REG_SEND = 14 +SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +SDMA_PERFMON_SEL_WR_BA_RTR = 16 +SDMA_PERFMON_SEL_MC_WR_IDLE = 17 +SDMA_PERFMON_SEL_MC_WR_COUNT = 18 +SDMA_PERFMON_SEL_RD_BA_RTR = 19 +SDMA_PERFMON_SEL_MC_RD_IDLE = 20 +SDMA_PERFMON_SEL_MC_RD_COUNT = 21 +SDMA_PERFMON_SEL_MC_RD_RET_STALL = 22 +SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 23 +SDMA_PERFMON_SEL_SEM_IDLE = 26 +SDMA_PERFMON_SEL_SEM_REQ_STALL = 27 +SDMA_PERFMON_SEL_SEM_REQ_COUNT = 28 +SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 29 +SDMA_PERFMON_SEL_SEM_RESP_FAIL = 30 +SDMA_PERFMON_SEL_SEM_RESP_PASS = 31 +SDMA_PERFMON_SEL_INT_IDLE = 32 +SDMA_PERFMON_SEL_INT_REQ_STALL = 33 +SDMA_PERFMON_SEL_INT_REQ_COUNT = 34 +SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 35 +SDMA_PERFMON_SEL_INT_RESP_RETRY = 36 +SDMA_PERFMON_SEL_NUM_PACKET = 37 +SDMA_PERFMON_SEL_CE_WREQ_IDLE = 39 +SDMA_PERFMON_SEL_CE_WR_IDLE = 40 +SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 41 +SDMA_PERFMON_SEL_CE_RREQ_IDLE = 42 +SDMA_PERFMON_SEL_CE_OUT_IDLE = 43 +SDMA_PERFMON_SEL_CE_IN_IDLE = 44 +SDMA_PERFMON_SEL_CE_DST_IDLE = 45 +SDMA_PERFMON_SEL_CE_AFIFO_FULL = 48 +SDMA_PERFMON_SEL_DUMMY_0 = 49 +SDMA_PERFMON_SEL_DUMMY_1 = 50 +SDMA_PERFMON_SEL_CE_INFO_FULL = 51 +SDMA_PERFMON_SEL_CE_INFO1_FULL = 52 +SDMA_PERFMON_SEL_CE_RD_STALL = 53 +SDMA_PERFMON_SEL_CE_WR_STALL = 54 +SDMA_PERFMON_SEL_QUEUE0_SELECT = 55 +SDMA_PERFMON_SEL_QUEUE1_SELECT = 56 +SDMA_PERFMON_SEL_QUEUE2_SELECT = 57 +SDMA_PERFMON_SEL_QUEUE3_SELECT = 58 +SDMA_PERFMON_SEL_CTX_CHANGE = 59 +SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 60 +SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 61 +SDMA_PERFMON_SEL_DOORBELL = 62 +SDMA_PERFMON_SEL_MCU_L1_WR_VLD = 63 +SDMA_PERFMON_SEL_CE_L1_WR_VLD = 64 +SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 65 +SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 66 +SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 67 +SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 68 +SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 69 +SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 70 +SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 71 +SDMA_PERFMON_SEL_UTCL2_RET_ACK = 72 +SDMA_PERFMON_SEL_UTCL2_FREE = 73 +SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 74 +SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 75 +SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 76 +SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 77 +SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 78 +SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 79 +SDMA_PERFMON_SEL_GPUVM_INV_LOW = 80 +SDMA_PERFMON_SEL_L1_WRL2_IDLE = 81 +SDMA_PERFMON_SEL_L1_RDL2_IDLE = 82 +SDMA_PERFMON_SEL_L1_WRMC_IDLE = 83 +SDMA_PERFMON_SEL_L1_RDMC_IDLE = 84 +SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 85 +SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 86 +SDMA_PERFMON_SEL_META_L2_REQ_SEND = 87 +SDMA_PERFMON_SEL_L2_META_RET_VLD = 88 +SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 89 +SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 90 +SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 91 +SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 92 +SDMA_PERFMON_SEL_META_REQ_SEND = 93 +SDMA_PERFMON_SEL_META_RTN_VLD = 94 +SDMA_PERFMON_SEL_TLBI_SEND = 95 +SDMA_PERFMON_SEL_TLBI_RTN = 96 +SDMA_PERFMON_SEL_GCR_SEND = 97 +SDMA_PERFMON_SEL_GCR_RTN = 98 +SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 99 +SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 100 +SDMA_PERFMON_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SDMA_PERF_SEL' +SDMA_PERF_SEL__enumvalues = { + 0: 'SDMA_PERF_SEL_CYCLE', + 1: 'SDMA_PERF_SEL_IDLE', + 2: 'SDMA_PERF_SEL_REG_IDLE', + 3: 'SDMA_PERF_SEL_RB_EMPTY', + 4: 'SDMA_PERF_SEL_RB_FULL', + 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', + 8: 'SDMA_PERF_SEL_RB_RPTR_WB', + 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', + 10: 'SDMA_PERF_SEL_RB_CMD_FULL', + 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', + 12: 'SDMA_PERF_SEL_IB_CMD_FULL', + 13: 'SDMA_PERF_SEL_EX_IDLE', + 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', + 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'SDMA_PERF_SEL_MC_WR_IDLE', + 17: 'SDMA_PERF_SEL_MC_WR_COUNT', + 18: 'SDMA_PERF_SEL_MC_RD_IDLE', + 19: 'SDMA_PERF_SEL_MC_RD_COUNT', + 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', + 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 24: 'SDMA_PERF_SEL_SEM_IDLE', + 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', + 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', + 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', + 30: 'SDMA_PERF_SEL_INT_IDLE', + 31: 'SDMA_PERF_SEL_INT_REQ_STALL', + 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', + 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', + 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', + 35: 'SDMA_PERF_SEL_NUM_PACKET', + 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 38: 'SDMA_PERF_SEL_CE_WR_IDLE', + 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', + 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', + 42: 'SDMA_PERF_SEL_CE_IN_IDLE', + 43: 'SDMA_PERF_SEL_CE_DST_IDLE', + 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', + 47: 'SDMA_PERF_SEL_DUMMY_0', + 48: 'SDMA_PERF_SEL_DUMMY_1', + 49: 'SDMA_PERF_SEL_CE_INFO_FULL', + 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', + 51: 'SDMA_PERF_SEL_CE_RD_STALL', + 52: 'SDMA_PERF_SEL_CE_WR_STALL', + 53: 'SDMA_PERF_SEL_QUEUE0_SELECT', + 54: 'SDMA_PERF_SEL_QUEUE1_SELECT', + 55: 'SDMA_PERF_SEL_QUEUE2_SELECT', + 56: 'SDMA_PERF_SEL_QUEUE3_SELECT', + 57: 'SDMA_PERF_SEL_CTX_CHANGE', + 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', + 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 60: 'SDMA_PERF_SEL_DOORBELL', + 61: 'SDMA_PERF_SEL_RD_BA_RTR', + 62: 'SDMA_PERF_SEL_WR_BA_RTR', + 63: 'SDMA_PERF_SEL_MCU_L1_WR_VLD', + 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', + 65: 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', + 66: 'SDMA_PERF_SEL_SDMA_CPF_INVACK', + 67: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', + 68: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', + 69: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', + 70: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', + 71: 'SDMA_PERF_SEL_UTCL2_RET_XNACK', + 72: 'SDMA_PERF_SEL_UTCL2_RET_ACK', + 73: 'SDMA_PERF_SEL_UTCL2_FREE', + 74: 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', + 75: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 76: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', + 77: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 78: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', + 79: 'SDMA_PERF_SEL_GPUVM_INV_HIGH', + 80: 'SDMA_PERF_SEL_GPUVM_INV_LOW', + 81: 'SDMA_PERF_SEL_L1_WRL2_IDLE', + 82: 'SDMA_PERF_SEL_L1_RDL2_IDLE', + 83: 'SDMA_PERF_SEL_L1_WRMC_IDLE', + 84: 'SDMA_PERF_SEL_L1_RDMC_IDLE', + 85: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', + 86: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', + 87: 'SDMA_PERF_SEL_META_L2_REQ_SEND', + 88: 'SDMA_PERF_SEL_L2_META_RET_VLD', + 89: 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', + 90: 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', + 91: 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', + 92: 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', + 93: 'SDMA_PERF_SEL_META_REQ_SEND', + 94: 'SDMA_PERF_SEL_META_RTN_VLD', + 95: 'SDMA_PERF_SEL_TLBI_SEND', + 96: 'SDMA_PERF_SEL_TLBI_RTN', + 97: 'SDMA_PERF_SEL_GCR_SEND', + 98: 'SDMA_PERF_SEL_GCR_RTN', + 99: 'SDMA_PERF_SEL_CGCG_FENCE', + 100: 'SDMA_PERF_SEL_CE_CH_WR_REQ', + 101: 'SDMA_PERF_SEL_CE_CH_WR_RET', + 102: 'SDMA_PERF_SEL_MCU_CH_WR_REQ', + 103: 'SDMA_PERF_SEL_MCU_CH_WR_RET', + 104: 'SDMA_PERF_SEL_CE_OR_MCU_CH_RD_REQ', + 105: 'SDMA_PERF_SEL_CE_OR_MCU_CH_RD_RET', + 106: 'SDMA_PERF_SEL_RB_CH_RD_REQ', + 107: 'SDMA_PERF_SEL_RB_CH_RD_RET', + 108: 'SDMA_PERF_SEL_IB_CH_RD_REQ', + 109: 'SDMA_PERF_SEL_IB_CH_RD_RET', + 110: 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', + 111: 'SDMA_PERF_SEL_WPTR_CH_RD_RET', + 112: 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', + 113: 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', + 114: 'SDMA_PERF_SEL_CMD_OP_MATCH', + 115: 'SDMA_PERF_SEL_CMD_OP_START', + 116: 'SDMA_PERF_SEL_CMD_OP_END', + 117: 'SDMA_PERF_SEL_CE_BUSY', + 118: 'SDMA_PERF_SEL_CE_BUSY_START', + 119: 'SDMA_PERF_SEL_CE_BUSY_END', + 120: 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER', + 121: 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_START', + 122: 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_END', + 123: 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', + 124: 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', + 125: 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', + 126: 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', + 127: 'SDMA_PERF_SEL_QUEUE4_SELECT', + 128: 'SDMA_PERF_SEL_QUEUE5_SELECT', + 129: 'SDMA_PERF_SEL_QUEUE6_SELECT', + 130: 'SDMA_PERF_SEL_QUEUE7_SELECT', +} +SDMA_PERF_SEL_CYCLE = 0 +SDMA_PERF_SEL_IDLE = 1 +SDMA_PERF_SEL_REG_IDLE = 2 +SDMA_PERF_SEL_RB_EMPTY = 3 +SDMA_PERF_SEL_RB_FULL = 4 +SDMA_PERF_SEL_RB_WPTR_WRAP = 5 +SDMA_PERF_SEL_RB_RPTR_WRAP = 6 +SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 +SDMA_PERF_SEL_RB_RPTR_WB = 8 +SDMA_PERF_SEL_RB_CMD_IDLE = 9 +SDMA_PERF_SEL_RB_CMD_FULL = 10 +SDMA_PERF_SEL_IB_CMD_IDLE = 11 +SDMA_PERF_SEL_IB_CMD_FULL = 12 +SDMA_PERF_SEL_EX_IDLE = 13 +SDMA_PERF_SEL_SRBM_REG_SEND = 14 +SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +SDMA_PERF_SEL_MC_WR_IDLE = 16 +SDMA_PERF_SEL_MC_WR_COUNT = 17 +SDMA_PERF_SEL_MC_RD_IDLE = 18 +SDMA_PERF_SEL_MC_RD_COUNT = 19 +SDMA_PERF_SEL_MC_RD_RET_STALL = 20 +SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 +SDMA_PERF_SEL_SEM_IDLE = 24 +SDMA_PERF_SEL_SEM_REQ_STALL = 25 +SDMA_PERF_SEL_SEM_REQ_COUNT = 26 +SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 +SDMA_PERF_SEL_SEM_RESP_FAIL = 28 +SDMA_PERF_SEL_SEM_RESP_PASS = 29 +SDMA_PERF_SEL_INT_IDLE = 30 +SDMA_PERF_SEL_INT_REQ_STALL = 31 +SDMA_PERF_SEL_INT_REQ_COUNT = 32 +SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 +SDMA_PERF_SEL_INT_RESP_RETRY = 34 +SDMA_PERF_SEL_NUM_PACKET = 35 +SDMA_PERF_SEL_CE_WREQ_IDLE = 37 +SDMA_PERF_SEL_CE_WR_IDLE = 38 +SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 +SDMA_PERF_SEL_CE_RREQ_IDLE = 40 +SDMA_PERF_SEL_CE_OUT_IDLE = 41 +SDMA_PERF_SEL_CE_IN_IDLE = 42 +SDMA_PERF_SEL_CE_DST_IDLE = 43 +SDMA_PERF_SEL_CE_AFIFO_FULL = 46 +SDMA_PERF_SEL_DUMMY_0 = 47 +SDMA_PERF_SEL_DUMMY_1 = 48 +SDMA_PERF_SEL_CE_INFO_FULL = 49 +SDMA_PERF_SEL_CE_INFO1_FULL = 50 +SDMA_PERF_SEL_CE_RD_STALL = 51 +SDMA_PERF_SEL_CE_WR_STALL = 52 +SDMA_PERF_SEL_QUEUE0_SELECT = 53 +SDMA_PERF_SEL_QUEUE1_SELECT = 54 +SDMA_PERF_SEL_QUEUE2_SELECT = 55 +SDMA_PERF_SEL_QUEUE3_SELECT = 56 +SDMA_PERF_SEL_CTX_CHANGE = 57 +SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 +SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 +SDMA_PERF_SEL_DOORBELL = 60 +SDMA_PERF_SEL_RD_BA_RTR = 61 +SDMA_PERF_SEL_WR_BA_RTR = 62 +SDMA_PERF_SEL_MCU_L1_WR_VLD = 63 +SDMA_PERF_SEL_CE_L1_WR_VLD = 64 +SDMA_PERF_SEL_CPF_SDMA_INVREQ = 65 +SDMA_PERF_SEL_SDMA_CPF_INVACK = 66 +SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 67 +SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 68 +SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 69 +SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 70 +SDMA_PERF_SEL_UTCL2_RET_XNACK = 71 +SDMA_PERF_SEL_UTCL2_RET_ACK = 72 +SDMA_PERF_SEL_UTCL2_FREE = 73 +SDMA_PERF_SEL_SDMA_UTCL2_SEND = 74 +SDMA_PERF_SEL_DMA_L1_WR_SEND = 75 +SDMA_PERF_SEL_DMA_L1_RD_SEND = 76 +SDMA_PERF_SEL_DMA_MC_WR_SEND = 77 +SDMA_PERF_SEL_DMA_MC_RD_SEND = 78 +SDMA_PERF_SEL_GPUVM_INV_HIGH = 79 +SDMA_PERF_SEL_GPUVM_INV_LOW = 80 +SDMA_PERF_SEL_L1_WRL2_IDLE = 81 +SDMA_PERF_SEL_L1_RDL2_IDLE = 82 +SDMA_PERF_SEL_L1_WRMC_IDLE = 83 +SDMA_PERF_SEL_L1_RDMC_IDLE = 84 +SDMA_PERF_SEL_L1_WR_INV_IDLE = 85 +SDMA_PERF_SEL_L1_RD_INV_IDLE = 86 +SDMA_PERF_SEL_META_L2_REQ_SEND = 87 +SDMA_PERF_SEL_L2_META_RET_VLD = 88 +SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 89 +SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 90 +SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 91 +SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 92 +SDMA_PERF_SEL_META_REQ_SEND = 93 +SDMA_PERF_SEL_META_RTN_VLD = 94 +SDMA_PERF_SEL_TLBI_SEND = 95 +SDMA_PERF_SEL_TLBI_RTN = 96 +SDMA_PERF_SEL_GCR_SEND = 97 +SDMA_PERF_SEL_GCR_RTN = 98 +SDMA_PERF_SEL_CGCG_FENCE = 99 +SDMA_PERF_SEL_CE_CH_WR_REQ = 100 +SDMA_PERF_SEL_CE_CH_WR_RET = 101 +SDMA_PERF_SEL_MCU_CH_WR_REQ = 102 +SDMA_PERF_SEL_MCU_CH_WR_RET = 103 +SDMA_PERF_SEL_CE_OR_MCU_CH_RD_REQ = 104 +SDMA_PERF_SEL_CE_OR_MCU_CH_RD_RET = 105 +SDMA_PERF_SEL_RB_CH_RD_REQ = 106 +SDMA_PERF_SEL_RB_CH_RD_RET = 107 +SDMA_PERF_SEL_IB_CH_RD_REQ = 108 +SDMA_PERF_SEL_IB_CH_RD_RET = 109 +SDMA_PERF_SEL_WPTR_CH_RD_REQ = 110 +SDMA_PERF_SEL_WPTR_CH_RD_RET = 111 +SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 112 +SDMA_PERF_SEL_UTCL1_UTCL2_RET = 113 +SDMA_PERF_SEL_CMD_OP_MATCH = 114 +SDMA_PERF_SEL_CMD_OP_START = 115 +SDMA_PERF_SEL_CMD_OP_END = 116 +SDMA_PERF_SEL_CE_BUSY = 117 +SDMA_PERF_SEL_CE_BUSY_START = 118 +SDMA_PERF_SEL_CE_BUSY_END = 119 +SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER = 120 +SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_START = 121 +SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_END = 122 +SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 123 +SDMA_PERF_SEL_CH_CE_WRRET_VALID = 124 +SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 125 +SDMA_PERF_SEL_CH_CE_RDRET_VALID = 126 +SDMA_PERF_SEL_QUEUE4_SELECT = 127 +SDMA_PERF_SEL_QUEUE5_SELECT = 128 +SDMA_PERF_SEL_QUEUE6_SELECT = 129 +SDMA_PERF_SEL_QUEUE7_SELECT = 130 +SDMA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SPM_PERFMON_STATE' +SPM_PERFMON_STATE__enumvalues = { + 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'STRM_PERFMON_STATE_START_COUNTING', + 2: 'STRM_PERFMON_STATE_STOP_COUNTING', + 3: 'STRM_PERFMON_STATE_RESERVED_3', + 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 +STRM_PERFMON_STATE_START_COUNTING = 1 +STRM_PERFMON_STATE_STOP_COUNTING = 2 +STRM_PERFMON_STATE_RESERVED_3 = 3 +STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +SPM_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_MTYPE' +TCC_MTYPE__enumvalues = { + 0: 'MTYPE_NC', + 1: 'MTYPE_WC', + 2: 'MTYPE_CC', +} +MTYPE_NC = 0 +MTYPE_WC = 1 +MTYPE_CC = 2 +TCC_MTYPE = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL0FaultType' +UTCL0FaultType__enumvalues = { + 0: 'UTCL0_XNACK_SUCCESS', + 1: 'UTCL0_XNACK_RETRY', + 2: 'UTCL0_XNACK_PRT', + 3: 'UTCL0_XNACK_NO_RETRY', +} +UTCL0_XNACK_SUCCESS = 0 +UTCL0_XNACK_RETRY = 1 +UTCL0_XNACK_PRT = 2 +UTCL0_XNACK_NO_RETRY = 3 +UTCL0FaultType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL0RequestType' +UTCL0RequestType__enumvalues = { + 0: 'UTCL0_TYPE_NORMAL', + 1: 'UTCL0_TYPE_SHOOTDOWN', + 2: 'UTCL0_TYPE_BYPASS', +} +UTCL0_TYPE_NORMAL = 0 +UTCL0_TYPE_SHOOTDOWN = 1 +UTCL0_TYPE_BYPASS = 2 +UTCL0RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1FaultType' +UTCL1FaultType__enumvalues = { + 0: 'UTCL1_XNACK_SUCCESS', + 1: 'UTCL1_XNACK_RETRY', + 2: 'UTCL1_XNACK_PRT', + 3: 'UTCL1_XNACK_NO_RETRY', +} +UTCL1_XNACK_SUCCESS = 0 +UTCL1_XNACK_RETRY = 1 +UTCL1_XNACK_PRT = 2 +UTCL1_XNACK_NO_RETRY = 3 +UTCL1FaultType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1RequestType' +UTCL1RequestType__enumvalues = { + 0: 'UTCL1_TYPE_NORMAL', + 1: 'UTCL1_TYPE_SHOOTDOWN', + 2: 'UTCL1_TYPE_BYPASS', +} +UTCL1_TYPE_NORMAL = 0 +UTCL1_TYPE_SHOOTDOWN = 1 +UTCL1_TYPE_BYPASS = 2 +UTCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'WRITE_COMPRESSION_MODE' +WRITE_COMPRESSION_MODE__enumvalues = { + 0: 'COMPRESSION_MODE_BYPASS_METADATA_CACHE', + 1: 'COMPRESSION_MODE_COMPRESSION_ENABLED', + 2: 'COMPRESSION_MODE_WRITE_COMPRESSION_DISABLED', +} +COMPRESSION_MODE_BYPASS_METADATA_CACHE = 0 +COMPRESSION_MODE_COMPRESSION_ENABLED = 1 +COMPRESSION_MODE_WRITE_COMPRESSION_DISABLED = 2 +WRITE_COMPRESSION_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'WritePolicy' +WritePolicy__enumvalues = { + 0: 'CACHE_LRU_WR', + 1: 'CACHE_STREAM', + 2: 'CACHE_NOA_WR', + 3: 'CACHE_BYPASS', +} +CACHE_LRU_WR = 0 +CACHE_STREAM = 1 +CACHE_NOA_WR = 2 +CACHE_BYPASS = 3 +WritePolicy = ctypes.c_uint32 # enum + +# values for enumeration 'COLOR_KEYER_ENABLE' +COLOR_KEYER_ENABLE__enumvalues = { + 0: 'COLOR_KEY_EN', + 1: 'COLOR_KEY_DIS', +} +COLOR_KEY_EN = 0 +COLOR_KEY_DIS = 1 +COLOR_KEYER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'COLOR_KEYER_MODE' +COLOR_KEYER_MODE__enumvalues = { + 0: 'FORCE_00', + 1: 'FORCE_FF', + 2: 'RANGE_00', + 3: 'RANGE_FF', +} +FORCE_00 = 0 +FORCE_FF = 1 +RANGE_00 = 2 +RANGE_FF = 3 +COLOR_KEYER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DENORM_TRUNCATE' +DENORM_TRUNCATE__enumvalues = { + 0: 'CNVC_ROUND', + 1: 'CNVC_TRUNCATE', +} +CNVC_ROUND = 0 +CNVC_TRUNCATE = 1 +DENORM_TRUNCATE = ctypes.c_uint32 # enum + +# values for enumeration 'FORMAT_CROSSBAR' +FORMAT_CROSSBAR__enumvalues = { + 0: 'FORMAT_CROSSBAR_R', + 1: 'FORMAT_CROSSBAR_G', + 2: 'FORMAT_CROSSBAR_B', +} +FORMAT_CROSSBAR_R = 0 +FORMAT_CROSSBAR_G = 1 +FORMAT_CROSSBAR_B = 2 +FORMAT_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'LUMA_KEYER_ENABLE' +LUMA_KEYER_ENABLE__enumvalues = { + 0: 'LUMA_KEY_EN', + 1: 'LUMA_KEY_DIS', +} +LUMA_KEY_EN = 0 +LUMA_KEY_DIS = 1 +LUMA_KEYER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'PIX_EXPAND_MODE' +PIX_EXPAND_MODE__enumvalues = { + 0: 'PIX_DYNAMIC_EXPANSION', + 1: 'PIX_ZERO_EXPANSION', +} +PIX_DYNAMIC_EXPANSION = 0 +PIX_ZERO_EXPANSION = 1 +PIX_EXPAND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PRE_CSC_MODE_ENUM' +PRE_CSC_MODE_ENUM__enumvalues = { + 0: 'PRE_CSC_BYPASS', + 1: 'PRE_CSC_SET_A', + 2: 'PRE_CSC_SET_B', +} +PRE_CSC_BYPASS = 0 +PRE_CSC_SET_A = 1 +PRE_CSC_SET_B = 2 +PRE_CSC_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'PRE_DEGAM_MODE' +PRE_DEGAM_MODE__enumvalues = { + 0: 'PRE_DEGAM_BYPASS', + 1: 'PRE_DEGAM_ENABLE', +} +PRE_DEGAM_BYPASS = 0 +PRE_DEGAM_ENABLE = 1 +PRE_DEGAM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PRE_DEGAM_SELECT' +PRE_DEGAM_SELECT__enumvalues = { + 0: 'PRE_DEGAM_SRGB', + 1: 'PRE_DEGAM_GAMMA_22', + 2: 'PRE_DEGAM_GAMMA_24', + 3: 'PRE_DEGAM_GAMMA_26', + 4: 'PRE_DEGAM_BT2020', + 5: 'PRE_DEGAM_BT2100PQ', + 6: 'PRE_DEGAM_BT2100HLG', +} +PRE_DEGAM_SRGB = 0 +PRE_DEGAM_GAMMA_22 = 1 +PRE_DEGAM_GAMMA_24 = 2 +PRE_DEGAM_GAMMA_26 = 3 +PRE_DEGAM_BT2020 = 4 +PRE_DEGAM_BT2100PQ = 5 +PRE_DEGAM_BT2100HLG = 6 +PRE_DEGAM_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_PIXEL_FORMAT' +SURFACE_PIXEL_FORMAT__enumvalues = { + 1: 'ARGB1555', + 2: 'RGBA5551', + 3: 'RGB565', + 4: 'BGR565', + 5: 'ARGB4444', + 6: 'RGBA4444', + 8: 'ARGB8888', + 9: 'RGBA8888', + 10: 'ARGB2101010', + 11: 'RGBA1010102', + 12: 'AYCrCb8888', + 13: 'YCrCbA8888', + 14: 'ACrYCb8888', + 15: 'CrYCbA8888', + 16: 'ARGB16161616_10MSB', + 17: 'RGBA16161616_10MSB', + 18: 'ARGB16161616_10LSB', + 19: 'RGBA16161616_10LSB', + 20: 'ARGB16161616_12MSB', + 21: 'RGBA16161616_12MSB', + 22: 'ARGB16161616_12LSB', + 23: 'RGBA16161616_12LSB', + 24: 'ARGB16161616_FLOAT', + 25: 'RGBA16161616_FLOAT', + 26: 'ARGB16161616_UNORM', + 27: 'RGBA16161616_UNORM', + 28: 'ARGB16161616_SNORM', + 29: 'RGBA16161616_SNORM', + 32: 'AYCrCb16161616_10MSB', + 33: 'AYCrCb16161616_10LSB', + 34: 'YCrCbA16161616_10MSB', + 35: 'YCrCbA16161616_10LSB', + 36: 'ACrYCb16161616_10MSB', + 37: 'ACrYCb16161616_10LSB', + 38: 'CrYCbA16161616_10MSB', + 39: 'CrYCbA16161616_10LSB', + 40: 'AYCrCb16161616_12MSB', + 41: 'AYCrCb16161616_12LSB', + 42: 'YCrCbA16161616_12MSB', + 43: 'YCrCbA16161616_12LSB', + 44: 'ACrYCb16161616_12MSB', + 45: 'ACrYCb16161616_12LSB', + 46: 'CrYCbA16161616_12MSB', + 47: 'CrYCbA16161616_12LSB', + 64: 'Y8_CrCb88_420_PLANAR', + 65: 'Y8_CbCr88_420_PLANAR', + 66: 'Y10_CrCb1010_420_PLANAR', + 67: 'Y10_CbCr1010_420_PLANAR', + 68: 'Y12_CrCb1212_420_PLANAR', + 69: 'Y12_CbCr1212_420_PLANAR', + 72: 'YCrYCb8888_422_PACKED', + 73: 'YCbYCr8888_422_PACKED', + 74: 'CrYCbY8888_422_PACKED', + 75: 'CbYCrY8888_422_PACKED', + 76: 'YCrYCb10101010_422_PACKED', + 77: 'YCbYCr10101010_422_PACKED', + 78: 'CrYCbY10101010_422_PACKED', + 79: 'CbYCrY10101010_422_PACKED', + 80: 'YCrYCb12121212_422_PACKED', + 81: 'YCbYCr12121212_422_PACKED', + 82: 'CrYCbY12121212_422_PACKED', + 83: 'CbYCrY12121212_422_PACKED', + 112: 'RGB111110_FIX', + 113: 'BGR101111_FIX', + 114: 'ACrYCb2101010', + 115: 'CrYCbA1010102', + 116: 'RGBE', + 118: 'RGB111110_FLOAT', + 119: 'BGR101111_FLOAT', + 120: 'MONO_8', + 121: 'MONO_10MSB', + 122: 'MONO_10LSB', + 123: 'MONO_12MSB', + 124: 'MONO_12LSB', + 125: 'MONO_16', +} +ARGB1555 = 1 +RGBA5551 = 2 +RGB565 = 3 +BGR565 = 4 +ARGB4444 = 5 +RGBA4444 = 6 +ARGB8888 = 8 +RGBA8888 = 9 +ARGB2101010 = 10 +RGBA1010102 = 11 +AYCrCb8888 = 12 +YCrCbA8888 = 13 +ACrYCb8888 = 14 +CrYCbA8888 = 15 +ARGB16161616_10MSB = 16 +RGBA16161616_10MSB = 17 +ARGB16161616_10LSB = 18 +RGBA16161616_10LSB = 19 +ARGB16161616_12MSB = 20 +RGBA16161616_12MSB = 21 +ARGB16161616_12LSB = 22 +RGBA16161616_12LSB = 23 +ARGB16161616_FLOAT = 24 +RGBA16161616_FLOAT = 25 +ARGB16161616_UNORM = 26 +RGBA16161616_UNORM = 27 +ARGB16161616_SNORM = 28 +RGBA16161616_SNORM = 29 +AYCrCb16161616_10MSB = 32 +AYCrCb16161616_10LSB = 33 +YCrCbA16161616_10MSB = 34 +YCrCbA16161616_10LSB = 35 +ACrYCb16161616_10MSB = 36 +ACrYCb16161616_10LSB = 37 +CrYCbA16161616_10MSB = 38 +CrYCbA16161616_10LSB = 39 +AYCrCb16161616_12MSB = 40 +AYCrCb16161616_12LSB = 41 +YCrCbA16161616_12MSB = 42 +YCrCbA16161616_12LSB = 43 +ACrYCb16161616_12MSB = 44 +ACrYCb16161616_12LSB = 45 +CrYCbA16161616_12MSB = 46 +CrYCbA16161616_12LSB = 47 +Y8_CrCb88_420_PLANAR = 64 +Y8_CbCr88_420_PLANAR = 65 +Y10_CrCb1010_420_PLANAR = 66 +Y10_CbCr1010_420_PLANAR = 67 +Y12_CrCb1212_420_PLANAR = 68 +Y12_CbCr1212_420_PLANAR = 69 +YCrYCb8888_422_PACKED = 72 +YCbYCr8888_422_PACKED = 73 +CrYCbY8888_422_PACKED = 74 +CbYCrY8888_422_PACKED = 75 +YCrYCb10101010_422_PACKED = 76 +YCbYCr10101010_422_PACKED = 77 +CrYCbY10101010_422_PACKED = 78 +CbYCrY10101010_422_PACKED = 79 +YCrYCb12121212_422_PACKED = 80 +YCbYCr12121212_422_PACKED = 81 +CrYCbY12121212_422_PACKED = 82 +CbYCrY12121212_422_PACKED = 83 +RGB111110_FIX = 112 +BGR101111_FIX = 113 +ACrYCb2101010 = 114 +CrYCbA1010102 = 115 +RGBE = 116 +RGB111110_FLOAT = 118 +BGR101111_FLOAT = 119 +MONO_8 = 120 +MONO_10MSB = 121 +MONO_10LSB = 122 +MONO_12MSB = 123 +MONO_12LSB = 124 +MONO_16 = 125 +SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'XNORM' +XNORM__enumvalues = { + 0: 'XNORM_A', + 1: 'XNORM_B', +} +XNORM_A = 0 +XNORM_B = 1 +XNORM = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_ENABLE' +CUR_ENABLE__enumvalues = { + 0: 'CUR_DIS', + 1: 'CUR_EN', +} +CUR_DIS = 0 +CUR_EN = 1 +CUR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_EXPAND_MODE' +CUR_EXPAND_MODE__enumvalues = { + 0: 'CUR_DYNAMIC_EXPANSION', + 1: 'CUR_ZERO_EXPANSION', +} +CUR_DYNAMIC_EXPANSION = 0 +CUR_ZERO_EXPANSION = 1 +CUR_EXPAND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_INV_CLAMP' +CUR_INV_CLAMP__enumvalues = { + 0: 'CUR_CLAMP_DIS', + 1: 'CUR_CLAMP_EN', +} +CUR_CLAMP_DIS = 0 +CUR_CLAMP_EN = 1 +CUR_INV_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_MATRIX_COEF_FORMAT_ENUM' +CUR_MATRIX_COEF_FORMAT_ENUM__enumvalues = { + 0: 'CUR_MATRIX_FIX_S2_13', + 1: 'CUR_MATRIX_FIX_S3_12', +} +CUR_MATRIX_FIX_S2_13 = 0 +CUR_MATRIX_FIX_S3_12 = 1 +CUR_MATRIX_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_MODE' +CUR_MODE__enumvalues = { + 0: 'MONO_2BIT', + 1: 'COLOR_24BIT_1BIT_AND', + 2: 'COLOR_24BIT_8BIT_ALPHA_PREMULT', + 3: 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 4: 'COLOR_64BIT_FP_PREMULT', + 5: 'COLOR_64BIT_FP_UNPREMULT', +} +MONO_2BIT = 0 +COLOR_24BIT_1BIT_AND = 1 +COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 +COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 +COLOR_64BIT_FP_PREMULT = 4 +COLOR_64BIT_FP_UNPREMULT = 5 +CUR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_PENDING' +CUR_PENDING__enumvalues = { + 0: 'CUR_NOT_PENDING', + 1: 'CUR_YES_PENDING', +} +CUR_NOT_PENDING = 0 +CUR_YES_PENDING = 1 +CUR_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_ROM_EN' +CUR_ROM_EN__enumvalues = { + 0: 'CUR_FP_NO_ROM', + 1: 'CUR_FP_USE_ROM', +} +CUR_FP_NO_ROM = 0 +CUR_FP_USE_ROM = 1 +CUR_ROM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'COEF_RAM_SELECT_RD' +COEF_RAM_SELECT_RD__enumvalues = { + 0: 'COEF_RAM_SELECT_BACK', + 1: 'COEF_RAM_SELECT_CURRENT', +} +COEF_RAM_SELECT_BACK = 0 +COEF_RAM_SELECT_CURRENT = 1 +COEF_RAM_SELECT_RD = ctypes.c_uint32 # enum + +# values for enumeration 'DSCL_MODE_SEL' +DSCL_MODE_SEL__enumvalues = { + 0: 'DSCL_MODE_SCALING_444_BYPASS', + 1: 'DSCL_MODE_SCALING_444_RGB_ENABLE', + 2: 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', + 3: 'DSCL_MODE_SCALING_YCBCR_ENABLE', + 4: 'DSCL_MODE_LUMA_SCALING_BYPASS', + 5: 'DSCL_MODE_CHROMA_SCALING_BYPASS', + 6: 'DSCL_MODE_DSCL_BYPASS', +} +DSCL_MODE_SCALING_444_BYPASS = 0 +DSCL_MODE_SCALING_444_RGB_ENABLE = 1 +DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2 +DSCL_MODE_SCALING_YCBCR_ENABLE = 3 +DSCL_MODE_LUMA_SCALING_BYPASS = 4 +DSCL_MODE_CHROMA_SCALING_BYPASS = 5 +DSCL_MODE_DSCL_BYPASS = 6 +DSCL_MODE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ISHARP_FMT_MODE_ENUM' +ISHARP_FMT_MODE_ENUM__enumvalues = { + 0: 'ISHARP_FMT_MODE_0', + 1: 'ISHARP_FMT_MODE_1', +} +ISHARP_FMT_MODE_0 = 0 +ISHARP_FMT_MODE_1 = 1 +ISHARP_FMT_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ISHARP_LBA_MODE_ENUM' +ISHARP_LBA_MODE_ENUM__enumvalues = { + 0: 'ISHARP_LBA_MODE_0', + 1: 'ISHARP_LBA_MODE_1', +} +ISHARP_LBA_MODE_0 = 0 +ISHARP_LBA_MODE_1 = 1 +ISHARP_LBA_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ISHARP_NOISEDET_MODE_ENUM' +ISHARP_NOISEDET_MODE_ENUM__enumvalues = { + 0: 'ISHARP_NOISEDET_MODE_0', + 1: 'ISHARP_NOISEDET_MODE_1', + 2: 'ISHARP_NOISEDET_MODE_2', + 3: 'ISHARP_NOISEDET_MODE_3', +} +ISHARP_NOISEDET_MODE_0 = 0 +ISHARP_NOISEDET_MODE_1 = 1 +ISHARP_NOISEDET_MODE_2 = 2 +ISHARP_NOISEDET_MODE_3 = 3 +ISHARP_NOISEDET_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'LB_ALPHA_EN' +LB_ALPHA_EN__enumvalues = { + 0: 'LB_ALPHA_DISABLE', + 1: 'LB_ALPHA_ENABLE', +} +LB_ALPHA_DISABLE = 0 +LB_ALPHA_ENABLE = 1 +LB_ALPHA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_INTERLEAVE_EN' +LB_INTERLEAVE_EN__enumvalues = { + 0: 'LB_INTERLEAVE_DISABLE', + 1: 'LB_INTERLEAVE_ENABLE', +} +LB_INTERLEAVE_DISABLE = 0 +LB_INTERLEAVE_ENABLE = 1 +LB_INTERLEAVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MEMORY_CONFIG' +LB_MEMORY_CONFIG__enumvalues = { + 0: 'LB_MEMORY_CONFIG_0', + 1: 'LB_MEMORY_CONFIG_1', + 2: 'LB_MEMORY_CONFIG_2', + 3: 'LB_MEMORY_CONFIG_3', +} +LB_MEMORY_CONFIG_0 = 0 +LB_MEMORY_CONFIG_1 = 1 +LB_MEMORY_CONFIG_2 = 2 +LB_MEMORY_CONFIG_3 = 3 +LB_MEMORY_CONFIG = ctypes.c_uint32 # enum + +# values for enumeration 'MATRIX_MODE_ENUM' +MATRIX_MODE_ENUM__enumvalues = { + 0: 'MATRIX_MODE_0', + 1: 'MATRIX_MODE_1', +} +MATRIX_MODE_0 = 0 +MATRIX_MODE_1 = 1 +MATRIX_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_BYPASS_SEL' +OBUF_BYPASS_SEL__enumvalues = { + 0: 'OBUF_BYPASS_DIS', + 1: 'OBUF_BYPASS_EN', +} +OBUF_BYPASS_DIS = 0 +OBUF_BYPASS_EN = 1 +OBUF_BYPASS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_IS_HALF_RECOUT_WIDTH_SEL' +OBUF_IS_HALF_RECOUT_WIDTH_SEL__enumvalues = { + 0: 'OBUF_FULL_RECOUT', + 1: 'OBUF_HALF_RECOUT', +} +OBUF_FULL_RECOUT = 0 +OBUF_HALF_RECOUT = 1 +OBUF_IS_HALF_RECOUT_WIDTH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_USE_FULL_BUFFER_SEL' +OBUF_USE_FULL_BUFFER_SEL__enumvalues = { + 0: 'OBUF_RECOUT', + 1: 'OBUF_FULL', +} +OBUF_RECOUT = 0 +OBUF_FULL = 1 +OBUF_USE_FULL_BUFFER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_2TAP_HARDCODE' +SCL_2TAP_HARDCODE__enumvalues = { + 0: 'SCL_COEF_2TAP_HARDCODE_OFF', + 1: 'SCL_COEF_2TAP_HARDCODE_ON', +} +SCL_COEF_2TAP_HARDCODE_OFF = 0 +SCL_COEF_2TAP_HARDCODE_ON = 1 +SCL_2TAP_HARDCODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_ALPHA_COEF' +SCL_ALPHA_COEF__enumvalues = { + 0: 'SCL_ALPHA_COEF_FIRST', + 1: 'SCL_ALPHA_COEF_SECOND', +} +SCL_ALPHA_COEF_FIRST = 0 +SCL_ALPHA_COEF_SECOND = 1 +SCL_ALPHA_COEF = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_AUTOCAL_MODE' +SCL_AUTOCAL_MODE__enumvalues = { + 0: 'AUTOCAL_MODE_OFF', + 1: 'AUTOCAL_MODE_AUTOSCALE', + 2: 'AUTOCAL_MODE_AUTOCENTER', + 3: 'AUTOCAL_MODE_AUTOREPLICATE', +} +AUTOCAL_MODE_OFF = 0 +AUTOCAL_MODE_AUTOSCALE = 1 +AUTOCAL_MODE_AUTOCENTER = 2 +AUTOCAL_MODE_AUTOREPLICATE = 3 +SCL_AUTOCAL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_BOUNDARY' +SCL_BOUNDARY__enumvalues = { + 0: 'SCL_BOUNDARY_EDGE', + 1: 'SCL_BOUNDARY_BLACK', +} +SCL_BOUNDARY_EDGE = 0 +SCL_BOUNDARY_BLACK = 1 +SCL_BOUNDARY = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_CHROMA_COEF' +SCL_CHROMA_COEF__enumvalues = { + 0: 'SCL_CHROMA_COEF_FIRST', + 1: 'SCL_CHROMA_COEF_SECOND', +} +SCL_CHROMA_COEF_FIRST = 0 +SCL_CHROMA_COEF_SECOND = 1 +SCL_CHROMA_COEF = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_COEF_FILTER_TYPE_SEL' +SCL_COEF_FILTER_TYPE_SEL__enumvalues = { + 0: 'SCL_COEF_LUMA_VERT_FILTER', + 1: 'SCL_COEF_LUMA_HORZ_FILTER', + 2: 'SCL_COEF_CHROMA_VERT_FILTER', + 3: 'SCL_COEF_CHROMA_HORZ_FILTER', + 4: 'SCL_COEF_SC_VERT_FILTER', + 5: 'SCL_COEF_SC_HORZ_FILTER', +} +SCL_COEF_LUMA_VERT_FILTER = 0 +SCL_COEF_LUMA_HORZ_FILTER = 1 +SCL_COEF_CHROMA_VERT_FILTER = 2 +SCL_COEF_CHROMA_HORZ_FILTER = 3 +SCL_COEF_SC_VERT_FILTER = 4 +SCL_COEF_SC_HORZ_FILTER = 5 +SCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_COEF_RAM_SEL' +SCL_COEF_RAM_SEL__enumvalues = { + 0: 'SCL_COEF_RAM_SEL_0', + 1: 'SCL_COEF_RAM_SEL_1', +} +SCL_COEF_RAM_SEL_0 = 0 +SCL_COEF_RAM_SEL_1 = 1 +SCL_COEF_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_SHARP_EN' +SCL_SHARP_EN__enumvalues = { + 0: 'SCL_SHARP_DISABLE', + 1: 'SCL_SHARP_ENABLE', +} +SCL_SHARP_DISABLE = 0 +SCL_SHARP_ENABLE = 1 +SCL_SHARP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_30BIT_ENUM' +CMC_3DLUT_30BIT_ENUM__enumvalues = { + 0: 'CMC_3DLUT_36BIT', + 1: 'CMC_3DLUT_30BIT', +} +CMC_3DLUT_36BIT = 0 +CMC_3DLUT_30BIT = 1 +CMC_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_RAM_SEL' +CMC_3DLUT_RAM_SEL__enumvalues = { + 0: 'CMC_RAM0_ACCESS', + 1: 'CMC_RAM1_ACCESS', + 2: 'CMC_RAM2_ACCESS', + 3: 'CMC_RAM3_ACCESS', +} +CMC_RAM0_ACCESS = 0 +CMC_RAM1_ACCESS = 1 +CMC_RAM2_ACCESS = 2 +CMC_RAM3_ACCESS = 3 +CMC_3DLUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_SIZE_ENUM' +CMC_3DLUT_SIZE_ENUM__enumvalues = { + 0: 'CMC_3DLUT_17CUBE', + 1: 'CMC_3DLUT_9CUBE', +} +CMC_3DLUT_17CUBE = 0 +CMC_3DLUT_9CUBE = 1 +CMC_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_2_CONFIG_ENUM' +CMC_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'CMC_LUT_2CFG_NO_MEMORY', + 1: 'CMC_LUT_2CFG_MEMORY_A', + 2: 'CMC_LUT_2CFG_MEMORY_B', +} +CMC_LUT_2CFG_NO_MEMORY = 0 +CMC_LUT_2CFG_MEMORY_A = 1 +CMC_LUT_2CFG_MEMORY_B = 2 +CMC_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_2_MODE_ENUM' +CMC_LUT_2_MODE_ENUM__enumvalues = { + 0: 'CMC_LUT_2_MODE_BYPASS', + 1: 'CMC_LUT_2_MODE_RAMA_LUT', + 2: 'CMC_LUT_2_MODE_RAMB_LUT', +} +CMC_LUT_2_MODE_BYPASS = 0 +CMC_LUT_2_MODE_RAMA_LUT = 1 +CMC_LUT_2_MODE_RAMB_LUT = 2 +CMC_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_NUM_SEG' +CMC_LUT_NUM_SEG__enumvalues = { + 0: 'CMC_SEGMENTS_1', + 1: 'CMC_SEGMENTS_2', + 2: 'CMC_SEGMENTS_4', + 3: 'CMC_SEGMENTS_8', + 4: 'CMC_SEGMENTS_16', + 5: 'CMC_SEGMENTS_32', + 6: 'CMC_SEGMENTS_64', + 7: 'CMC_SEGMENTS_128', +} +CMC_SEGMENTS_1 = 0 +CMC_SEGMENTS_2 = 1 +CMC_SEGMENTS_4 = 2 +CMC_SEGMENTS_8 = 3 +CMC_SEGMENTS_16 = 4 +CMC_SEGMENTS_32 = 5 +CMC_SEGMENTS_64 = 6 +CMC_SEGMENTS_128 = 7 +CMC_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_RAM_SEL' +CMC_LUT_RAM_SEL__enumvalues = { + 0: 'CMC_RAMA_ACCESS', + 1: 'CMC_RAMB_ACCESS', +} +CMC_RAMA_ACCESS = 0 +CMC_RAMB_ACCESS = 1 +CMC_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_BYPASS' +CM_BYPASS__enumvalues = { + 0: 'NON_BYPASS', + 1: 'BYPASS_EN', +} +NON_BYPASS = 0 +BYPASS_EN = 1 +CM_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'CM_COEF_FORMAT_ENUM' +CM_COEF_FORMAT_ENUM__enumvalues = { + 0: 'FIX_S2_13', + 1: 'FIX_S3_12', +} +FIX_S2_13 = 0 +FIX_S3_12 = 1 +CM_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_DATA_SIGNED' +CM_DATA_SIGNED__enumvalues = { + 0: 'UNSIGNED', + 1: 'SIGNED', +} +UNSIGNED = 0 +SIGNED = 1 +CM_DATA_SIGNED = ctypes.c_uint32 # enum + +# values for enumeration 'CM_EN' +CM_EN__enumvalues = { + 0: 'CM_DISABLE', + 1: 'CM_ENABLE', +} +CM_DISABLE = 0 +CM_ENABLE = 1 +CM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMMA_LUT_MODE_ENUM' +CM_GAMMA_LUT_MODE_ENUM__enumvalues = { + 0: 'BYPASS', + 1: 'RESERVED_1', + 2: 'RAM_LUT', + 3: 'RESERVED_3', +} +BYPASS = 0 +RESERVED_1 = 1 +RAM_LUT = 2 +RESERVED_3 = 3 +CM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMMA_LUT_PWL_DISABLE_ENUM' +CM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { + 0: 'ENABLE_PWL', + 1: 'DISABLE_PWL', +} +ENABLE_PWL = 0 +DISABLE_PWL = 1 +CM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMMA_LUT_SEL_ENUM' +CM_GAMMA_LUT_SEL_ENUM__enumvalues = { + 0: 'RAMA', + 1: 'RAMB', +} +RAMA = 0 +RAMB = 1 +CM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_2_CONFIG_ENUM' +CM_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'LUT_2CFG_NO_MEMORY', + 1: 'LUT_2CFG_MEMORY_A', + 2: 'LUT_2CFG_MEMORY_B', +} +LUT_2CFG_NO_MEMORY = 0 +LUT_2CFG_MEMORY_A = 1 +LUT_2CFG_MEMORY_B = 2 +CM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_2_MODE_ENUM' +CM_LUT_2_MODE_ENUM__enumvalues = { + 0: 'LUT_2_MODE_BYPASS', + 1: 'LUT_2_MODE_RAMA_LUT', + 2: 'LUT_2_MODE_RAMB_LUT', +} +LUT_2_MODE_BYPASS = 0 +LUT_2_MODE_RAMA_LUT = 1 +LUT_2_MODE_RAMB_LUT = 2 +CM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_4_CONFIG_ENUM' +CM_LUT_4_CONFIG_ENUM__enumvalues = { + 0: 'LUT_4CFG_NO_MEMORY', + 1: 'LUT_4CFG_ROM_A', + 2: 'LUT_4CFG_ROM_B', + 3: 'LUT_4CFG_MEMORY_A', + 4: 'LUT_4CFG_MEMORY_B', +} +LUT_4CFG_NO_MEMORY = 0 +LUT_4CFG_ROM_A = 1 +LUT_4CFG_ROM_B = 2 +LUT_4CFG_MEMORY_A = 3 +LUT_4CFG_MEMORY_B = 4 +CM_LUT_4_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_4_MODE_ENUM' +CM_LUT_4_MODE_ENUM__enumvalues = { + 0: 'LUT_4_MODE_BYPASS', + 1: 'LUT_4_MODE_ROMA_LUT', + 2: 'LUT_4_MODE_ROMB_LUT', + 3: 'LUT_4_MODE_RAMA_LUT', + 4: 'LUT_4_MODE_RAMB_LUT', +} +LUT_4_MODE_BYPASS = 0 +LUT_4_MODE_ROMA_LUT = 1 +LUT_4_MODE_ROMB_LUT = 2 +LUT_4_MODE_RAMA_LUT = 3 +LUT_4_MODE_RAMB_LUT = 4 +CM_LUT_4_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_CONFIG_MODE' +CM_LUT_CONFIG_MODE__enumvalues = { + 0: 'DIFFERENT_RGB', + 1: 'ALL_USE_R', +} +DIFFERENT_RGB = 0 +ALL_USE_R = 1 +CM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_NUM_SEG' +CM_LUT_NUM_SEG__enumvalues = { + 0: 'SEGMENTS_1', + 1: 'SEGMENTS_2', + 2: 'SEGMENTS_4', + 3: 'SEGMENTS_8', + 4: 'SEGMENTS_16', + 5: 'SEGMENTS_32', + 6: 'SEGMENTS_64', + 7: 'SEGMENTS_128', +} +SEGMENTS_1 = 0 +SEGMENTS_2 = 1 +SEGMENTS_4 = 2 +SEGMENTS_8 = 3 +SEGMENTS_16 = 4 +SEGMENTS_32 = 5 +SEGMENTS_64 = 6 +SEGMENTS_128 = 7 +CM_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_RAM_SEL' +CM_LUT_RAM_SEL__enumvalues = { + 0: 'RAMA_ACCESS', + 1: 'RAMB_ACCESS', +} +RAMA_ACCESS = 0 +RAMB_ACCESS = 1 +CM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_READ_COLOR_SEL' +CM_LUT_READ_COLOR_SEL__enumvalues = { + 0: 'BLUE_LUT', + 1: 'GREEN_LUT', + 2: 'RED_LUT', +} +BLUE_LUT = 0 +GREEN_LUT = 1 +RED_LUT = 2 +CM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_READ_DBG' +CM_LUT_READ_DBG__enumvalues = { + 0: 'DISABLE_DEBUG', + 1: 'ENABLE_DEBUG', +} +DISABLE_DEBUG = 0 +ENABLE_DEBUG = 1 +CM_LUT_READ_DBG = ctypes.c_uint32 # enum + +# values for enumeration 'CM_PENDING' +CM_PENDING__enumvalues = { + 0: 'CM_NOT_PENDING', + 1: 'CM_YES_PENDING', +} +CM_NOT_PENDING = 0 +CM_YES_PENDING = 1 +CM_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'CM_POST_CSC_MODE_ENUM' +CM_POST_CSC_MODE_ENUM__enumvalues = { + 0: 'BYPASS_POST_CSC', + 1: 'COEF_POST_CSC', + 2: 'COEF_POST_CSC_B', +} +BYPASS_POST_CSC = 0 +COEF_POST_CSC = 1 +COEF_POST_CSC_B = 2 +CM_POST_CSC_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_WRITE_BASE_ONLY' +CM_WRITE_BASE_ONLY__enumvalues = { + 0: 'WRITE_BOTH', + 1: 'WRITE_BASE_ONLY', +} +WRITE_BOTH = 0 +WRITE_BASE_ONLY = 1 +CM_WRITE_BASE_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_CUR_SEL' +CRC_CUR_SEL__enumvalues = { + 0: 'CRC_CUR_0', + 1: 'CRC_CUR_1', +} +CRC_CUR_0 = 0 +CRC_CUR_1 = 1 +CRC_CUR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_INTERLACE_SEL' +CRC_INTERLACE_SEL__enumvalues = { + 0: 'CRC_INTERLACE_0', + 1: 'CRC_INTERLACE_1', + 2: 'CRC_INTERLACE_2', + 3: 'CRC_INTERLACE_3', +} +CRC_INTERLACE_0 = 0 +CRC_INTERLACE_1 = 1 +CRC_INTERLACE_2 = 2 +CRC_INTERLACE_3 = 3 +CRC_INTERLACE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_IN_PIX_SEL' +CRC_IN_PIX_SEL__enumvalues = { + 0: 'CRC_IN_PIX_0', + 1: 'CRC_IN_PIX_1', + 2: 'CRC_IN_PIX_2', + 3: 'CRC_IN_PIX_3', + 4: 'CRC_IN_PIX_4', + 5: 'CRC_IN_PIX_5', + 6: 'CRC_IN_PIX_6', + 7: 'CRC_IN_PIX_7', +} +CRC_IN_PIX_0 = 0 +CRC_IN_PIX_1 = 1 +CRC_IN_PIX_2 = 2 +CRC_IN_PIX_3 = 3 +CRC_IN_PIX_4 = 4 +CRC_IN_PIX_5 = 5 +CRC_IN_PIX_6 = 6 +CRC_IN_PIX_7 = 7 +CRC_IN_PIX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_SRC_SEL' +CRC_SRC_SEL__enumvalues = { + 0: 'CRC_SRC_0', + 1: 'CRC_SRC_1', + 2: 'CRC_SRC_2', + 3: 'CRC_SRC_3', +} +CRC_SRC_0 = 0 +CRC_SRC_1 = 1 +CRC_SRC_2 = 2 +CRC_SRC_3 = 3 +CRC_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_STEREO_SEL' +CRC_STEREO_SEL__enumvalues = { + 0: 'CRC_STEREO_0', + 1: 'CRC_STEREO_1', + 2: 'CRC_STEREO_2', + 3: 'CRC_STEREO_3', +} +CRC_STEREO_0 = 0 +CRC_STEREO_1 = 1 +CRC_STEREO_2 = 2 +CRC_STEREO_3 = 3 +CRC_STEREO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLK_SEL' +TEST_CLK_SEL__enumvalues = { + 0: 'TEST_CLK_SEL_0', + 1: 'TEST_CLK_SEL_1', + 2: 'TEST_CLK_SEL_2', + 3: 'TEST_CLK_SEL_3', + 4: 'TEST_CLK_SEL_4', + 5: 'TEST_CLK_SEL_5', + 6: 'TEST_CLK_SEL_6', + 7: 'TEST_CLK_SEL_7', +} +TEST_CLK_SEL_0 = 0 +TEST_CLK_SEL_1 = 1 +TEST_CLK_SEL_2 = 2 +TEST_CLK_SEL_3 = 3 +TEST_CLK_SEL_4 = 4 +TEST_CLK_SEL_5 = 5 +TEST_CLK_SEL_6 = 6 +TEST_CLK_SEL_7 = 7 +TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_ACTIVE' +PERFCOUNTER_ACTIVE__enumvalues = { + 0: 'PERFCOUNTER_IS_IDLE', + 1: 'PERFCOUNTER_IS_ACTIVE', +} +PERFCOUNTER_IS_IDLE = 0 +PERFCOUNTER_IS_ACTIVE = 1 +PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT0_STATE' +PERFCOUNTER_CNT0_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT0_STATE_RESET', + 1: 'PERFCOUNTER_CNT0_STATE_START', + 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT0_STATE_HW', +} +PERFCOUNTER_CNT0_STATE_RESET = 0 +PERFCOUNTER_CNT0_STATE_START = 1 +PERFCOUNTER_CNT0_STATE_FREEZE = 2 +PERFCOUNTER_CNT0_STATE_HW = 3 +PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT1_STATE' +PERFCOUNTER_CNT1_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT1_STATE_RESET', + 1: 'PERFCOUNTER_CNT1_STATE_START', + 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT1_STATE_HW', +} +PERFCOUNTER_CNT1_STATE_RESET = 0 +PERFCOUNTER_CNT1_STATE_START = 1 +PERFCOUNTER_CNT1_STATE_FREEZE = 2 +PERFCOUNTER_CNT1_STATE_HW = 3 +PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT2_STATE' +PERFCOUNTER_CNT2_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT2_STATE_RESET', + 1: 'PERFCOUNTER_CNT2_STATE_START', + 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT2_STATE_HW', +} +PERFCOUNTER_CNT2_STATE_RESET = 0 +PERFCOUNTER_CNT2_STATE_START = 1 +PERFCOUNTER_CNT2_STATE_FREEZE = 2 +PERFCOUNTER_CNT2_STATE_HW = 3 +PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT3_STATE' +PERFCOUNTER_CNT3_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT3_STATE_RESET', + 1: 'PERFCOUNTER_CNT3_STATE_START', + 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT3_STATE_HW', +} +PERFCOUNTER_CNT3_STATE_RESET = 0 +PERFCOUNTER_CNT3_STATE_START = 1 +PERFCOUNTER_CNT3_STATE_FREEZE = 2 +PERFCOUNTER_CNT3_STATE_HW = 3 +PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT4_STATE' +PERFCOUNTER_CNT4_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT4_STATE_RESET', + 1: 'PERFCOUNTER_CNT4_STATE_START', + 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT4_STATE_HW', +} +PERFCOUNTER_CNT4_STATE_RESET = 0 +PERFCOUNTER_CNT4_STATE_START = 1 +PERFCOUNTER_CNT4_STATE_FREEZE = 2 +PERFCOUNTER_CNT4_STATE_HW = 3 +PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT5_STATE' +PERFCOUNTER_CNT5_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT5_STATE_RESET', + 1: 'PERFCOUNTER_CNT5_STATE_START', + 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT5_STATE_HW', +} +PERFCOUNTER_CNT5_STATE_RESET = 0 +PERFCOUNTER_CNT5_STATE_START = 1 +PERFCOUNTER_CNT5_STATE_FREEZE = 2 +PERFCOUNTER_CNT5_STATE_HW = 3 +PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT6_STATE' +PERFCOUNTER_CNT6_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT6_STATE_RESET', + 1: 'PERFCOUNTER_CNT6_STATE_START', + 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT6_STATE_HW', +} +PERFCOUNTER_CNT6_STATE_RESET = 0 +PERFCOUNTER_CNT6_STATE_START = 1 +PERFCOUNTER_CNT6_STATE_FREEZE = 2 +PERFCOUNTER_CNT6_STATE_HW = 3 +PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT7_STATE' +PERFCOUNTER_CNT7_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT7_STATE_RESET', + 1: 'PERFCOUNTER_CNT7_STATE_START', + 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT7_STATE_HW', +} +PERFCOUNTER_CNT7_STATE_RESET = 0 +PERFCOUNTER_CNT7_STATE_START = 1 +PERFCOUNTER_CNT7_STATE_FREEZE = 2 +PERFCOUNTER_CNT7_STATE_HW = 3 +PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTL_SEL' +PERFCOUNTER_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_CNTL_SEL_0', + 1: 'PERFCOUNTER_CNTL_SEL_1', + 2: 'PERFCOUNTER_CNTL_SEL_2', + 3: 'PERFCOUNTER_CNTL_SEL_3', + 4: 'PERFCOUNTER_CNTL_SEL_4', + 5: 'PERFCOUNTER_CNTL_SEL_5', + 6: 'PERFCOUNTER_CNTL_SEL_6', + 7: 'PERFCOUNTER_CNTL_SEL_7', +} +PERFCOUNTER_CNTL_SEL_0 = 0 +PERFCOUNTER_CNTL_SEL_1 = 1 +PERFCOUNTER_CNTL_SEL_2 = 2 +PERFCOUNTER_CNTL_SEL_3 = 3 +PERFCOUNTER_CNTL_SEL_4 = 4 +PERFCOUNTER_CNTL_SEL_5 = 5 +PERFCOUNTER_CNTL_SEL_6 = 6 +PERFCOUNTER_CNTL_SEL_7 = 7 +PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' +PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { + 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', + 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', +} +PERFCOUNTER_CNTOFF_START_ENABLE = 0 +PERFCOUNTER_CNTOFF_START_DISABLE = 1 +PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' +PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { + 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', +} +PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 +PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 +PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 +PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CVALUE_SEL' +PERFCOUNTER_CVALUE_SEL__enumvalues = { + 0: 'PERFCOUNTER_CVALUE_SEL_47_0', + 1: 'PERFCOUNTER_CVALUE_SEL_15_0', + 2: 'PERFCOUNTER_CVALUE_SEL_31_16', + 3: 'PERFCOUNTER_CVALUE_SEL_47_32', + 4: 'PERFCOUNTER_CVALUE_SEL_11_0', + 5: 'PERFCOUNTER_CVALUE_SEL_23_12', + 6: 'PERFCOUNTER_CVALUE_SEL_35_24', + 7: 'PERFCOUNTER_CVALUE_SEL_47_36', +} +PERFCOUNTER_CVALUE_SEL_47_0 = 0 +PERFCOUNTER_CVALUE_SEL_15_0 = 1 +PERFCOUNTER_CVALUE_SEL_31_16 = 2 +PERFCOUNTER_CVALUE_SEL_47_32 = 3 +PERFCOUNTER_CVALUE_SEL_11_0 = 4 +PERFCOUNTER_CVALUE_SEL_23_12 = 5 +PERFCOUNTER_CVALUE_SEL_35_24 = 6 +PERFCOUNTER_CVALUE_SEL_47_36 = 7 +PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' +PERFCOUNTER_HW_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', + 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', +} +PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 +PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 +PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_STOP1_SEL' +PERFCOUNTER_HW_STOP1_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_STOP1_0', + 1: 'PERFCOUNTER_HW_STOP1_1', +} +PERFCOUNTER_HW_STOP1_0 = 0 +PERFCOUNTER_HW_STOP1_1 = 1 +PERFCOUNTER_HW_STOP1_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_STOP2_SEL' +PERFCOUNTER_HW_STOP2_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_STOP2_0', + 1: 'PERFCOUNTER_HW_STOP2_1', +} +PERFCOUNTER_HW_STOP2_0 = 0 +PERFCOUNTER_HW_STOP2_1 = 1 +PERFCOUNTER_HW_STOP2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INC_MODE' +PERFCOUNTER_INC_MODE__enumvalues = { + 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', + 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', + 2: 'PERFCOUNTER_INC_MODE_LSB', + 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', + 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', +} +PERFCOUNTER_INC_MODE_MULTI_BIT = 0 +PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 +PERFCOUNTER_INC_MODE_LSB = 2 +PERFCOUNTER_INC_MODE_POS_EDGE = 3 +PERFCOUNTER_INC_MODE_NEG_EDGE = 4 +PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_EN' +PERFCOUNTER_INT_EN__enumvalues = { + 0: 'PERFCOUNTER_INT_DISABLE', + 1: 'PERFCOUNTER_INT_ENABLE', +} +PERFCOUNTER_INT_DISABLE = 0 +PERFCOUNTER_INT_ENABLE = 1 +PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_TYPE' +PERFCOUNTER_INT_TYPE__enumvalues = { + 0: 'PERFCOUNTER_INT_TYPE_LEVEL', + 1: 'PERFCOUNTER_INT_TYPE_PULSE', +} +PERFCOUNTER_INT_TYPE_LEVEL = 0 +PERFCOUNTER_INT_TYPE_PULSE = 1 +PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_OFF_MASK' +PERFCOUNTER_OFF_MASK__enumvalues = { + 0: 'PERFCOUNTER_OFF_MASK_DISABLE', + 1: 'PERFCOUNTER_OFF_MASK_ENABLE', +} +PERFCOUNTER_OFF_MASK_DISABLE = 0 +PERFCOUNTER_OFF_MASK_ENABLE = 1 +PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RESTART_EN' +PERFCOUNTER_RESTART_EN__enumvalues = { + 0: 'PERFCOUNTER_RESTART_DISABLE', + 1: 'PERFCOUNTER_RESTART_ENABLE', +} +PERFCOUNTER_RESTART_DISABLE = 0 +PERFCOUNTER_RESTART_ENABLE = 1 +PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RUNEN_MODE' +PERFCOUNTER_RUNEN_MODE__enumvalues = { + 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', +} +PERFCOUNTER_RUNEN_MODE_LEVEL = 0 +PERFCOUNTER_RUNEN_MODE_EDGE = 1 +PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL0' +PERFCOUNTER_STATE_SEL0__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', +} +PERFCOUNTER_STATE_SEL0_GLOBAL = 0 +PERFCOUNTER_STATE_SEL0_LOCAL = 1 +PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL1' +PERFCOUNTER_STATE_SEL1__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', +} +PERFCOUNTER_STATE_SEL1_GLOBAL = 0 +PERFCOUNTER_STATE_SEL1_LOCAL = 1 +PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL2' +PERFCOUNTER_STATE_SEL2__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', +} +PERFCOUNTER_STATE_SEL2_GLOBAL = 0 +PERFCOUNTER_STATE_SEL2_LOCAL = 1 +PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL3' +PERFCOUNTER_STATE_SEL3__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', +} +PERFCOUNTER_STATE_SEL3_GLOBAL = 0 +PERFCOUNTER_STATE_SEL3_LOCAL = 1 +PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL4' +PERFCOUNTER_STATE_SEL4__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', +} +PERFCOUNTER_STATE_SEL4_GLOBAL = 0 +PERFCOUNTER_STATE_SEL4_LOCAL = 1 +PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL5' +PERFCOUNTER_STATE_SEL5__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', +} +PERFCOUNTER_STATE_SEL5_GLOBAL = 0 +PERFCOUNTER_STATE_SEL5_LOCAL = 1 +PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL6' +PERFCOUNTER_STATE_SEL6__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', +} +PERFCOUNTER_STATE_SEL6_GLOBAL = 0 +PERFCOUNTER_STATE_SEL6_LOCAL = 1 +PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL7' +PERFCOUNTER_STATE_SEL7__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', +} +PERFCOUNTER_STATE_SEL7_GLOBAL = 0 +PERFCOUNTER_STATE_SEL7_LOCAL = 1 +PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_AND_OR' +PERFMON_CNTOFF_AND_OR__enumvalues = { + 0: 'PERFMON_CNTOFF_OR', + 1: 'PERFMON_CNTOFF_AND', +} +PERFMON_CNTOFF_OR = 0 +PERFMON_CNTOFF_AND = 1 +PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_EN' +PERFMON_CNTOFF_INT_EN__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_DISABLE', + 1: 'PERFMON_CNTOFF_INT_ENABLE', +} +PERFMON_CNTOFF_INT_DISABLE = 0 +PERFMON_CNTOFF_INT_ENABLE = 1 +PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_TYPE' +PERFMON_CNTOFF_INT_TYPE__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', + 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', +} +PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 +PERFMON_CNTOFF_INT_TYPE_PULSE = 1 +PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_STATE' +PERFMON_STATE__enumvalues = { + 0: 'PERFMON_STATE_RESET', + 1: 'PERFMON_STATE_START', + 2: 'PERFMON_STATE_FREEZE', + 3: 'PERFMON_STATE_HW', +} +PERFMON_STATE_RESET = 0 +PERFMON_STATE_START = 1 +PERFMON_STATE_FREEZE = 2 +PERFMON_STATE_HW = 3 +PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'BIGK_FRAGMENT_SIZE' +BIGK_FRAGMENT_SIZE__enumvalues = { + 0: 'VM_PG_SIZE_4KB', + 1: 'VM_PG_SIZE_8KB', + 2: 'VM_PG_SIZE_16KB', + 3: 'VM_PG_SIZE_32KB', + 4: 'VM_PG_SIZE_64KB', + 5: 'VM_PG_SIZE_128KB', + 6: 'VM_PG_SIZE_256KB', + 7: 'VM_PG_SIZE_512KB', + 8: 'VM_PG_SIZE_1MB', + 9: 'VM_PG_SIZE_2MB', + 10: 'VM_PG_SIZE_4MB', + 11: 'VM_PG_SIZE_8MB', + 12: 'VM_PG_SIZE_16MB', + 13: 'VM_PG_SIZE_32MB', + 14: 'VM_PG_SIZE_64MB', + 15: 'VM_PG_SIZE_128MB', +} +VM_PG_SIZE_4KB = 0 +VM_PG_SIZE_8KB = 1 +VM_PG_SIZE_16KB = 2 +VM_PG_SIZE_32KB = 3 +VM_PG_SIZE_64KB = 4 +VM_PG_SIZE_128KB = 5 +VM_PG_SIZE_256KB = 6 +VM_PG_SIZE_512KB = 7 +VM_PG_SIZE_1MB = 8 +VM_PG_SIZE_2MB = 9 +VM_PG_SIZE_4MB = 10 +VM_PG_SIZE_8MB = 11 +VM_PG_SIZE_16MB = 12 +VM_PG_SIZE_32MB = 13 +VM_PG_SIZE_64MB = 14 +VM_PG_SIZE_128MB = 15 +BIGK_FRAGMENT_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'CHUNK_SIZE' +CHUNK_SIZE__enumvalues = { + 0: 'CHUNK_SIZE_1KB', + 1: 'CHUNK_SIZE_2KB', + 2: 'CHUNK_SIZE_4KB', + 3: 'CHUNK_SIZE_8KB', + 4: 'CHUNK_SIZE_16KB', + 5: 'CHUNK_SIZE_32KB', + 6: 'CHUNK_SIZE_64KB', +} +CHUNK_SIZE_1KB = 0 +CHUNK_SIZE_2KB = 1 +CHUNK_SIZE_4KB = 2 +CHUNK_SIZE_8KB = 3 +CHUNK_SIZE_16KB = 4 +CHUNK_SIZE_32KB = 5 +CHUNK_SIZE_64KB = 6 +CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DPTE_GROUP_SIZE' +DPTE_GROUP_SIZE__enumvalues = { + 0: 'DPTE_GROUP_SIZE_64B', + 1: 'DPTE_GROUP_SIZE_128B', + 2: 'DPTE_GROUP_SIZE_256B', + 3: 'DPTE_GROUP_SIZE_512B', + 4: 'DPTE_GROUP_SIZE_1024B', + 5: 'DPTE_GROUP_SIZE_2048B', +} +DPTE_GROUP_SIZE_64B = 0 +DPTE_GROUP_SIZE_128B = 1 +DPTE_GROUP_SIZE_256B = 2 +DPTE_GROUP_SIZE_512B = 3 +DPTE_GROUP_SIZE_1024B = 4 +DPTE_GROUP_SIZE_2048B = 5 +DPTE_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'FORCE_ONE_ROW_FOR_FRAME' +FORCE_ONE_ROW_FOR_FRAME__enumvalues = { + 0: 'FORCE_ONE_ROW_FOR_FRAME_0', + 1: 'FORCE_ONE_ROW_FOR_FRAME_1', +} +FORCE_ONE_ROW_FOR_FRAME_0 = 0 +FORCE_ONE_ROW_FOR_FRAME_1 = 1 +FORCE_ONE_ROW_FOR_FRAME = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_BLANK_EN' +HUBP_BLANK_EN__enumvalues = { + 0: 'HUBP_BLANK_SW_DEASSERT', + 1: 'HUBP_BLANK_SW_ASSERT', +} +HUBP_BLANK_SW_DEASSERT = 0 +HUBP_BLANK_SW_ASSERT = 1 +HUBP_BLANK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_IN_BLANK' +HUBP_IN_BLANK__enumvalues = { + 0: 'HUBP_IN_ACTIVE', + 1: 'HUBP_IN_VBLANK', +} +HUBP_IN_ACTIVE = 0 +HUBP_IN_VBLANK = 1 +HUBP_IN_BLANK = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_MEASURE_WIN_MODE_DCFCLK' +HUBP_MEASURE_WIN_MODE_DCFCLK__enumvalues = { + 0: 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', + 1: 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', + 2: 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', + 3: 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', +} +HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0 +HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 1 +HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 2 +HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 3 +HUBP_MEASURE_WIN_MODE_DCFCLK = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_NO_OUTSTANDING_REQ' +HUBP_NO_OUTSTANDING_REQ__enumvalues = { + 0: 'OUTSTANDING_REQ', + 1: 'NO_OUTSTANDING_REQ', +} +OUTSTANDING_REQ = 0 +NO_OUTSTANDING_REQ = 1 +HUBP_NO_OUTSTANDING_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_SOFT_RESET' +HUBP_SOFT_RESET__enumvalues = { + 0: 'HUBP_SOFT_RESET_ON', + 1: 'HUBP_SOFT_RESET_OFF', +} +HUBP_SOFT_RESET_ON = 0 +HUBP_SOFT_RESET_OFF = 1 +HUBP_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_TTU_DISABLE' +HUBP_TTU_DISABLE__enumvalues = { + 0: 'HUBP_TTU_ENABLED', + 1: 'HUBP_TTU_DISABLED', +} +HUBP_TTU_ENABLED = 0 +HUBP_TTU_DISABLED = 1 +HUBP_TTU_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_VREADY_AT_OR_AFTER_VSYNC' +HUBP_VREADY_AT_OR_AFTER_VSYNC__enumvalues = { + 0: 'VREADY_BEFORE_VSYNC', + 1: 'VREADY_AT_OR_AFTER_VSYNC', +} +VREADY_BEFORE_VSYNC = 0 +VREADY_AT_OR_AFTER_VSYNC = 1 +HUBP_VREADY_AT_OR_AFTER_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_VTG_SEL' +HUBP_VTG_SEL__enumvalues = { + 0: 'VTG_SEL_0', + 1: 'VTG_SEL_1', + 2: 'VTG_SEL_2', + 3: 'VTG_SEL_3', + 4: 'VTG_SEL_4', + 5: 'VTG_SEL_5', +} +VTG_SEL_0 = 0 +VTG_SEL_1 = 1 +VTG_SEL_2 = 2 +VTG_SEL_3 = 3 +VTG_SEL_4 = 4 +VTG_SEL_5 = 5 +HUBP_VTG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'H_MIRROR_EN' +H_MIRROR_EN__enumvalues = { + 0: 'HW_MIRRORING_DISABLE', + 1: 'HW_MIRRORING_ENABLE', +} +HW_MIRRORING_DISABLE = 0 +HW_MIRRORING_ENABLE = 1 +H_MIRROR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LEGACY_PIPE_INTERLEAVE' +LEGACY_PIPE_INTERLEAVE__enumvalues = { + 0: 'LEGACY_PIPE_INTERLEAVE_256B', + 1: 'LEGACY_PIPE_INTERLEAVE_512B', +} +LEGACY_PIPE_INTERLEAVE_256B = 0 +LEGACY_PIPE_INTERLEAVE_512B = 1 +LEGACY_PIPE_INTERLEAVE = ctypes.c_uint32 # enum + +# values for enumeration 'META_CHUNK_SIZE' +META_CHUNK_SIZE__enumvalues = { + 0: 'META_CHUNK_SIZE_1KB', + 1: 'META_CHUNK_SIZE_2KB', + 2: 'META_CHUNK_SIZE_4KB', + 3: 'META_CHUNK_SIZE_8KB', +} +META_CHUNK_SIZE_1KB = 0 +META_CHUNK_SIZE_2KB = 1 +META_CHUNK_SIZE_4KB = 2 +META_CHUNK_SIZE_8KB = 3 +META_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'META_LINEAR' +META_LINEAR__enumvalues = { + 0: 'META_SURF_TILED', + 1: 'META_SURF_LINEAR', +} +META_SURF_TILED = 0 +META_SURF_LINEAR = 1 +META_LINEAR = ctypes.c_uint32 # enum + +# values for enumeration 'MIN_CHUNK_SIZE' +MIN_CHUNK_SIZE__enumvalues = { + 0: 'NO_MIN_CHUNK_SIZE', + 1: 'MIN_CHUNK_SIZE_256B', + 2: 'MIN_CHUNK_SIZE_512B', + 3: 'MIN_CHUNK_SIZE_1024B', +} +NO_MIN_CHUNK_SIZE = 0 +MIN_CHUNK_SIZE_256B = 1 +MIN_CHUNK_SIZE_512B = 2 +MIN_CHUNK_SIZE_1024B = 3 +MIN_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'MIN_META_CHUNK_SIZE' +MIN_META_CHUNK_SIZE__enumvalues = { + 0: 'NO_MIN_META_CHUNK_SIZE', + 1: 'MIN_META_CHUNK_SIZE_64B', + 2: 'MIN_META_CHUNK_SIZE_128B', + 3: 'MIN_META_CHUNK_SIZE_256B', +} +NO_MIN_META_CHUNK_SIZE = 0 +MIN_META_CHUNK_SIZE_64B = 1 +MIN_META_CHUNK_SIZE_128B = 2 +MIN_META_CHUNK_SIZE_256B = 3 +MIN_META_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_ALIGNED' +PIPE_ALIGNED__enumvalues = { + 0: 'PIPE_UNALIGNED_SURF', + 1: 'PIPE_ALIGNED_SURF', +} +PIPE_UNALIGNED_SURF = 0 +PIPE_ALIGNED_SURF = 1 +PIPE_ALIGNED = ctypes.c_uint32 # enum + +# values for enumeration 'PTE_BUFFER_MODE' +PTE_BUFFER_MODE__enumvalues = { + 0: 'PTE_BUFFER_MODE_0', + 1: 'PTE_BUFFER_MODE_1', +} +PTE_BUFFER_MODE_0 = 0 +PTE_BUFFER_MODE_1 = 1 +PTE_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PTE_ROW_HEIGHT_LINEAR' +PTE_ROW_HEIGHT_LINEAR__enumvalues = { + 0: 'PTE_ROW_HEIGHT_LINEAR_8L', + 1: 'PTE_ROW_HEIGHT_LINEAR_16L', + 2: 'PTE_ROW_HEIGHT_LINEAR_32L', + 3: 'PTE_ROW_HEIGHT_LINEAR_64L', + 4: 'PTE_ROW_HEIGHT_LINEAR_128L', + 5: 'PTE_ROW_HEIGHT_LINEAR_256L', + 6: 'PTE_ROW_HEIGHT_LINEAR_512L', + 7: 'PTE_ROW_HEIGHT_LINEAR_1024L', +} +PTE_ROW_HEIGHT_LINEAR_8L = 0 +PTE_ROW_HEIGHT_LINEAR_16L = 1 +PTE_ROW_HEIGHT_LINEAR_32L = 2 +PTE_ROW_HEIGHT_LINEAR_64L = 3 +PTE_ROW_HEIGHT_LINEAR_128L = 4 +PTE_ROW_HEIGHT_LINEAR_256L = 5 +PTE_ROW_HEIGHT_LINEAR_512L = 6 +PTE_ROW_HEIGHT_LINEAR_1024L = 7 +PTE_ROW_HEIGHT_LINEAR = ctypes.c_uint32 # enum + +# values for enumeration 'ROTATION_ANGLE' +ROTATION_ANGLE__enumvalues = { + 0: 'ROTATE_0_DEGREES', + 1: 'ROTATE_90_DEGREES', + 2: 'ROTATE_180_DEGREES', + 3: 'ROTATE_270_DEGREES', +} +ROTATE_0_DEGREES = 0 +ROTATE_90_DEGREES = 1 +ROTATE_180_DEGREES = 2 +ROTATE_270_DEGREES = 3 +ROTATION_ANGLE = ctypes.c_uint32 # enum + +# values for enumeration 'SWATH_HEIGHT' +SWATH_HEIGHT__enumvalues = { + 0: 'SWATH_HEIGHT_1L', + 1: 'SWATH_HEIGHT_2L', + 2: 'SWATH_HEIGHT_4L', + 3: 'SWATH_HEIGHT_8L', + 4: 'SWATH_HEIGHT_16L', +} +SWATH_HEIGHT_1L = 0 +SWATH_HEIGHT_2L = 1 +SWATH_HEIGHT_4L = 2 +SWATH_HEIGHT_8L = 3 +SWATH_HEIGHT_16L = 4 +SWATH_HEIGHT = ctypes.c_uint32 # enum + +# values for enumeration 'VMPG_SIZE' +VMPG_SIZE__enumvalues = { + 0: 'VMPG_SIZE_4KB', + 1: 'VMPG_SIZE_64KB', +} +VMPG_SIZE_4KB = 0 +VMPG_SIZE_64KB = 1 +VMPG_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'VM_GROUP_SIZE' +VM_GROUP_SIZE__enumvalues = { + 0: 'VM_GROUP_SIZE_64B', + 1: 'VM_GROUP_SIZE_128B', + 2: 'VM_GROUP_SIZE_256B', + 3: 'VM_GROUP_SIZE_512B', + 4: 'VM_GROUP_SIZE_1024B', + 5: 'VM_GROUP_SIZE_2048B', +} +VM_GROUP_SIZE_64B = 0 +VM_GROUP_SIZE_128B = 1 +VM_GROUP_SIZE_256B = 2 +VM_GROUP_SIZE_512B = 3 +VM_GROUP_SIZE_1024B = 4 +VM_GROUP_SIZE_2048B = 5 +VM_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_MIN_FREE_ENTRIES' +DFQ_MIN_FREE_ENTRIES__enumvalues = { + 0: 'DFQ_MIN_FREE_ENTRIES_0', + 1: 'DFQ_MIN_FREE_ENTRIES_1', + 2: 'DFQ_MIN_FREE_ENTRIES_2', + 3: 'DFQ_MIN_FREE_ENTRIES_3', + 4: 'DFQ_MIN_FREE_ENTRIES_4', + 5: 'DFQ_MIN_FREE_ENTRIES_5', + 6: 'DFQ_MIN_FREE_ENTRIES_6', + 7: 'DFQ_MIN_FREE_ENTRIES_7', +} +DFQ_MIN_FREE_ENTRIES_0 = 0 +DFQ_MIN_FREE_ENTRIES_1 = 1 +DFQ_MIN_FREE_ENTRIES_2 = 2 +DFQ_MIN_FREE_ENTRIES_3 = 3 +DFQ_MIN_FREE_ENTRIES_4 = 4 +DFQ_MIN_FREE_ENTRIES_5 = 5 +DFQ_MIN_FREE_ENTRIES_6 = 6 +DFQ_MIN_FREE_ENTRIES_7 = 7 +DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_NUM_ENTRIES' +DFQ_NUM_ENTRIES__enumvalues = { + 0: 'DFQ_NUM_ENTRIES_0', + 1: 'DFQ_NUM_ENTRIES_1', + 2: 'DFQ_NUM_ENTRIES_2', + 3: 'DFQ_NUM_ENTRIES_3', + 4: 'DFQ_NUM_ENTRIES_4', + 5: 'DFQ_NUM_ENTRIES_5', + 6: 'DFQ_NUM_ENTRIES_6', + 7: 'DFQ_NUM_ENTRIES_7', + 8: 'DFQ_NUM_ENTRIES_8', +} +DFQ_NUM_ENTRIES_0 = 0 +DFQ_NUM_ENTRIES_1 = 1 +DFQ_NUM_ENTRIES_2 = 2 +DFQ_NUM_ENTRIES_3 = 3 +DFQ_NUM_ENTRIES_4 = 4 +DFQ_NUM_ENTRIES_5 = 5 +DFQ_NUM_ENTRIES_6 = 6 +DFQ_NUM_ENTRIES_7 = 7 +DFQ_NUM_ENTRIES_8 = 8 +DFQ_NUM_ENTRIES = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_SIZE' +DFQ_SIZE__enumvalues = { + 0: 'DFQ_SIZE_0', + 1: 'DFQ_SIZE_1', + 2: 'DFQ_SIZE_2', + 3: 'DFQ_SIZE_3', + 4: 'DFQ_SIZE_4', + 5: 'DFQ_SIZE_5', + 6: 'DFQ_SIZE_6', + 7: 'DFQ_SIZE_7', +} +DFQ_SIZE_0 = 0 +DFQ_SIZE_1 = 1 +DFQ_SIZE_2 = 2 +DFQ_SIZE_3 = 3 +DFQ_SIZE_4 = 4 +DFQ_SIZE_5 = 5 +DFQ_SIZE_6 = 6 +DFQ_SIZE_7 = 7 +DFQ_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_VM_DONE' +DMDATA_VM_DONE__enumvalues = { + 0: 'DMDATA_VM_IS_NOT_DONE', + 1: 'DMDATA_VM_IS_DONE', +} +DMDATA_VM_IS_NOT_DONE = 0 +DMDATA_VM_IS_DONE = 1 +DMDATA_VM_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'EXPANSION_MODE' +EXPANSION_MODE__enumvalues = { + 0: 'EXPANSION_MODE_ZERO', + 1: 'EXPANSION_MODE_CONSERVATIVE', + 2: 'EXPANSION_MODE_OPTIMAL', +} +EXPANSION_MODE_ZERO = 0 +EXPANSION_MODE_CONSERVATIVE = 1 +EXPANSION_MODE_OPTIMAL = 2 +EXPANSION_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FLIP_RATE' +FLIP_RATE__enumvalues = { + 0: 'FLIP_RATE_0', + 1: 'FLIP_RATE_1', + 2: 'FLIP_RATE_2', + 3: 'FLIP_RATE_3', + 4: 'FLIP_RATE_4', + 5: 'FLIP_RATE_5', + 6: 'FLIP_RATE_6', + 7: 'FLIP_RATE_7', +} +FLIP_RATE_0 = 0 +FLIP_RATE_1 = 1 +FLIP_RATE_2 = 2 +FLIP_RATE_3 = 3 +FLIP_RATE_4 = 4 +FLIP_RATE_5 = 5 +FLIP_RATE_6 = 6 +FLIP_RATE_7 = 7 +FLIP_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'INT_MASK' +INT_MASK__enumvalues = { + 0: 'INT_DISABLED', + 1: 'INT_ENABLED', +} +INT_DISABLED = 0 +INT_ENABLED = 1 +INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_IN_FLUSH_URGENT' +PIPE_IN_FLUSH_URGENT__enumvalues = { + 0: 'PIPE_IN_FLUSH_URGENT_ENABLE', + 1: 'PIPE_IN_FLUSH_URGENT_DISABLE', +} +PIPE_IN_FLUSH_URGENT_ENABLE = 0 +PIPE_IN_FLUSH_URGENT_DISABLE = 1 +PIPE_IN_FLUSH_URGENT = ctypes.c_uint32 # enum + +# values for enumeration 'PRQ_MRQ_FLUSH_URGENT' +PRQ_MRQ_FLUSH_URGENT__enumvalues = { + 0: 'PRQ_MRQ_FLUSH_URGENT_ENABLE', + 1: 'PRQ_MRQ_FLUSH_URGENT_DISABLE', +} +PRQ_MRQ_FLUSH_URGENT_ENABLE = 0 +PRQ_MRQ_FLUSH_URGENT_DISABLE = 1 +PRQ_MRQ_FLUSH_URGENT = ctypes.c_uint32 # enum + +# values for enumeration 'ROW_TTU_MODE' +ROW_TTU_MODE__enumvalues = { + 0: 'END_OF_ROW_MODE', + 1: 'WATERMARK_MODE', +} +END_OF_ROW_MODE = 0 +WATERMARK_MODE = 1 +ROW_TTU_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC' +SURFACE_DCC__enumvalues = { + 0: 'SURFACE_IS_NOT_DCC', + 1: 'SURFACE_IS_DCC', +} +SURFACE_IS_NOT_DCC = 0 +SURFACE_IS_DCC = 1 +SURFACE_DCC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_128B' +SURFACE_DCC_IND_128B__enumvalues = { + 0: 'SURFACE_DCC_IS_NOT_IND_128B', + 1: 'SURFACE_DCC_IS_IND_128B', +} +SURFACE_DCC_IS_NOT_IND_128B = 0 +SURFACE_DCC_IS_IND_128B = 1 +SURFACE_DCC_IND_128B = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_64B' +SURFACE_DCC_IND_64B__enumvalues = { + 0: 'SURFACE_DCC_IS_NOT_IND_64B', + 1: 'SURFACE_DCC_IS_IND_64B', +} +SURFACE_DCC_IS_NOT_IND_64B = 0 +SURFACE_DCC_IS_IND_64B = 1 +SURFACE_DCC_IND_64B = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_BLK' +SURFACE_DCC_IND_BLK__enumvalues = { + 0: 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', + 1: 'SURFACE_DCC_BLOCK_IS_IND_64B', + 2: 'SURFACE_DCC_BLOCK_IS_IND_128B', + 3: 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', +} +SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0 +SURFACE_DCC_BLOCK_IS_IND_64B = 1 +SURFACE_DCC_BLOCK_IS_IND_128B = 2 +SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 3 +SURFACE_DCC_IND_BLK = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_AWAY_INT_TYPE' +SURFACE_FLIP_AWAY_INT_TYPE__enumvalues = { + 0: 'SURFACE_FLIP_AWAY_INT_LEVEL', + 1: 'SURFACE_FLIP_AWAY_INT_PULSE', +} +SURFACE_FLIP_AWAY_INT_LEVEL = 0 +SURFACE_FLIP_AWAY_INT_PULSE = 1 +SURFACE_FLIP_AWAY_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_EXEC_DEBUG_MODE' +SURFACE_FLIP_EXEC_DEBUG_MODE__enumvalues = { + 0: 'SURFACE_FLIP_EXEC_NORMAL_MODE', + 1: 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', +} +SURFACE_FLIP_EXEC_NORMAL_MODE = 0 +SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 1 +SURFACE_FLIP_EXEC_DEBUG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_INT_TYPE' +SURFACE_FLIP_INT_TYPE__enumvalues = { + 0: 'SURFACE_FLIP_INT_LEVEL', + 1: 'SURFACE_FLIP_INT_PULSE', +} +SURFACE_FLIP_INT_LEVEL = 0 +SURFACE_FLIP_INT_PULSE = 1 +SURFACE_FLIP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_IN_STEREOSYNC' +SURFACE_FLIP_IN_STEREOSYNC__enumvalues = { + 0: 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', + 1: 'SURFACE_FLIP_IN_STEREOSYNC_MODE', +} +SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0 +SURFACE_FLIP_IN_STEREOSYNC_MODE = 1 +SURFACE_FLIP_IN_STEREOSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_MODE_FOR_STEREOSYNC' +SURFACE_FLIP_MODE_FOR_STEREOSYNC__enumvalues = { + 0: 'FLIP_ANY_FRAME', + 1: 'FLIP_LEFT_EYE', + 2: 'FLIP_RIGHT_EYE', + 3: 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', +} +FLIP_ANY_FRAME = 0 +FLIP_LEFT_EYE = 1 +FLIP_RIGHT_EYE = 2 +SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 3 +SURFACE_FLIP_MODE_FOR_STEREOSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_DISABLE' +SURFACE_FLIP_STEREO_SELECT_DISABLE__enumvalues = { + 0: 'SURFACE_FLIP_STEREO_SELECT_ENABLED', + 1: 'SURFACE_FLIP_STEREO_SELECT_DISABLED', +} +SURFACE_FLIP_STEREO_SELECT_ENABLED = 0 +SURFACE_FLIP_STEREO_SELECT_DISABLED = 1 +SURFACE_FLIP_STEREO_SELECT_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_POLARITY' +SURFACE_FLIP_STEREO_SELECT_POLARITY__enumvalues = { + 0: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', + 1: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', +} +SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0 +SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 1 +SURFACE_FLIP_STEREO_SELECT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_TYPE' +SURFACE_FLIP_TYPE__enumvalues = { + 0: 'SURFACE_V_FLIP', + 1: 'SURFACE_I_FLIP', +} +SURFACE_V_FLIP = 0 +SURFACE_I_FLIP = 1 +SURFACE_FLIP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_VUPDATE_SKIP_NUM' +SURFACE_FLIP_VUPDATE_SKIP_NUM__enumvalues = { + 0: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', + 1: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', + 2: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', + 3: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', + 4: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', + 5: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', + 6: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', + 7: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', + 8: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', + 9: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', + 10: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', + 11: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', + 12: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', + 13: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', + 14: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', + 15: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', +} +SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0 +SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 1 +SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 2 +SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 3 +SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 4 +SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 5 +SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 6 +SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 7 +SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 8 +SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 9 +SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 10 +SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 11 +SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 12 +SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 13 +SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 14 +SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 15 +SURFACE_FLIP_VUPDATE_SKIP_NUM = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_INUSE_RAED_NO_LATCH' +SURFACE_INUSE_RAED_NO_LATCH__enumvalues = { + 0: 'SURFACE_INUSE_IS_LATCHED', + 1: 'SURFACE_INUSE_IS_NOT_LATCHED', +} +SURFACE_INUSE_IS_LATCHED = 0 +SURFACE_INUSE_IS_NOT_LATCHED = 1 +SURFACE_INUSE_RAED_NO_LATCH = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_TMZ' +SURFACE_TMZ__enumvalues = { + 0: 'SURFACE_IS_NOT_TMZ', + 1: 'SURFACE_IS_TMZ', +} +SURFACE_IS_NOT_TMZ = 0 +SURFACE_IS_TMZ = 1 +SURFACE_TMZ = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_UPDATE_LOCK' +SURFACE_UPDATE_LOCK__enumvalues = { + 0: 'SURFACE_UPDATE_IS_UNLOCKED', + 1: 'SURFACE_UPDATE_IS_LOCKED', +} +SURFACE_UPDATE_IS_UNLOCKED = 0 +SURFACE_UPDATE_IS_LOCKED = 1 +SURFACE_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_ALPHA' +CROSSBAR_FOR_ALPHA__enumvalues = { + 0: 'ALPHA_DATA_ONTO_ALPHA_PORT', + 1: 'Y_G_DATA_ONTO_ALPHA_PORT', + 2: 'CB_B_DATA_ONTO_ALPHA_PORT', + 3: 'CR_R_DATA_ONTO_ALPHA_PORT', +} +ALPHA_DATA_ONTO_ALPHA_PORT = 0 +Y_G_DATA_ONTO_ALPHA_PORT = 1 +CB_B_DATA_ONTO_ALPHA_PORT = 2 +CR_R_DATA_ONTO_ALPHA_PORT = 3 +CROSSBAR_FOR_ALPHA = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_CB_B' +CROSSBAR_FOR_CB_B__enumvalues = { + 0: 'ALPHA_DATA_ONTO_CB_B_PORT', + 1: 'Y_G_DATA_ONTO_CB_B_PORT', + 2: 'CB_B_DATA_ONTO_CB_B_PORT', + 3: 'CR_R_DATA_ONTO_CB_B_PORT', +} +ALPHA_DATA_ONTO_CB_B_PORT = 0 +Y_G_DATA_ONTO_CB_B_PORT = 1 +CB_B_DATA_ONTO_CB_B_PORT = 2 +CR_R_DATA_ONTO_CB_B_PORT = 3 +CROSSBAR_FOR_CB_B = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_CR_R' +CROSSBAR_FOR_CR_R__enumvalues = { + 0: 'ALPHA_DATA_ONTO_CR_R_PORT', + 1: 'Y_G_DATA_ONTO_CR_R_PORT', + 2: 'CB_B_DATA_ONTO_CR_R_PORT', + 3: 'CR_R_DATA_ONTO_CR_R_PORT', +} +ALPHA_DATA_ONTO_CR_R_PORT = 0 +Y_G_DATA_ONTO_CR_R_PORT = 1 +CB_B_DATA_ONTO_CR_R_PORT = 2 +CR_R_DATA_ONTO_CR_R_PORT = 3 +CROSSBAR_FOR_CR_R = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_Y_G' +CROSSBAR_FOR_Y_G__enumvalues = { + 0: 'ALPHA_DATA_ONTO_Y_G_PORT', + 1: 'Y_G_DATA_ONTO_Y_G_PORT', + 2: 'CB_B_DATA_ONTO_Y_G_PORT', + 3: 'CR_R_DATA_ONTO_Y_G_PORT', +} +ALPHA_DATA_ONTO_Y_G_PORT = 0 +Y_G_DATA_ONTO_Y_G_PORT = 1 +CB_B_DATA_ONTO_Y_G_PORT = 2 +CR_R_DATA_ONTO_Y_G_PORT = 3 +CROSSBAR_FOR_Y_G = ctypes.c_uint32 # enum + +# values for enumeration 'DETILE_BUFFER_PACKER_ENABLE' +DETILE_BUFFER_PACKER_ENABLE__enumvalues = { + 0: 'DETILE_BUFFER_PACKER_IS_DISABLE', + 1: 'DETILE_BUFFER_PACKER_IS_ENABLE', +} +DETILE_BUFFER_PACKER_IS_DISABLE = 0 +DETILE_BUFFER_PACKER_IS_ENABLE = 1 +DETILE_BUFFER_PACKER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_DIS_MODE' +MEM_PWR_DIS_MODE__enumvalues = { + 0: 'MEM_POWER_DIS_MODE_ENABLE', + 1: 'MEM_POWER_DIS_MODE_DISABLE', +} +MEM_POWER_DIS_MODE_ENABLE = 0 +MEM_POWER_DIS_MODE_DISABLE = 1 +MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_MODE' +MEM_PWR_FORCE_MODE__enumvalues = { + 0: 'MEM_POWER_FORCE_MODE_OFF', + 1: 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', + 2: 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', + 3: 'MEM_POWER_FORCE_MODE_SHUT_DOWN', +} +MEM_POWER_FORCE_MODE_OFF = 0 +MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 1 +MEM_POWER_FORCE_MODE_DEEP_SLEEP = 2 +MEM_POWER_FORCE_MODE_SHUT_DOWN = 3 +MEM_PWR_FORCE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_STATUS' +MEM_PWR_STATUS__enumvalues = { + 0: 'MEM_POWER_STATUS_ON', + 1: 'MEM_POWER_STATUS_LIGHT_SLEEP', + 2: 'MEM_POWER_STATUS_DEEP_SLEEP', + 3: 'MEM_POWER_STATUS_SHUT_DOWN', +} +MEM_POWER_STATUS_ON = 0 +MEM_POWER_STATUS_LIGHT_SLEEP = 1 +MEM_POWER_STATUS_DEEP_SLEEP = 2 +MEM_POWER_STATUS_SHUT_DOWN = 3 +MEM_PWR_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_INT_MASK_MODE' +PIPE_INT_MASK_MODE__enumvalues = { + 0: 'PIPE_INT_MASK_MODE_DISABLE', + 1: 'PIPE_INT_MASK_MODE_ENABLE', +} +PIPE_INT_MASK_MODE_DISABLE = 0 +PIPE_INT_MASK_MODE_ENABLE = 1 +PIPE_INT_MASK_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_INT_TYPE_MODE' +PIPE_INT_TYPE_MODE__enumvalues = { + 0: 'PIPE_INT_TYPE_MODE_DISABLE', + 1: 'PIPE_INT_TYPE_MODE_ENABLE', +} +PIPE_INT_TYPE_MODE_DISABLE = 0 +PIPE_INT_TYPE_MODE_ENABLE = 1 +PIPE_INT_TYPE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE' +PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', +} +PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CROB_MEM_PWR_LIGHT_SLEEP_MODE' +CROB_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', + 2: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', +} +CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 +CROB_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_2X_MAGNIFY' +CURSOR_2X_MAGNIFY__enumvalues = { + 0: 'CURSOR_2X_MAGNIFY_IS_DISABLE', + 1: 'CURSOR_2X_MAGNIFY_IS_ENABLE', +} +CURSOR_2X_MAGNIFY_IS_DISABLE = 0 +CURSOR_2X_MAGNIFY_IS_ENABLE = 1 +CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_ENABLE' +CURSOR_ENABLE__enumvalues = { + 0: 'CURSOR_IS_DISABLE', + 1: 'CURSOR_IS_ENABLE', +} +CURSOR_IS_DISABLE = 0 +CURSOR_IS_ENABLE = 1 +CURSOR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_LINES_PER_CHUNK' +CURSOR_LINES_PER_CHUNK__enumvalues = { + 0: 'CURSOR_LINE_PER_CHUNK_1', + 1: 'CURSOR_LINE_PER_CHUNK_2', + 2: 'CURSOR_LINE_PER_CHUNK_4', + 3: 'CURSOR_LINE_PER_CHUNK_8', + 4: 'CURSOR_LINE_PER_CHUNK_16', +} +CURSOR_LINE_PER_CHUNK_1 = 0 +CURSOR_LINE_PER_CHUNK_2 = 1 +CURSOR_LINE_PER_CHUNK_4 = 2 +CURSOR_LINE_PER_CHUNK_8 = 3 +CURSOR_LINE_PER_CHUNK_16 = 4 +CURSOR_LINES_PER_CHUNK = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_MODE' +CURSOR_MODE__enumvalues = { + 0: 'CURSOR_MONO_2BIT', + 1: 'CURSOR_COLOR_24BIT_1BIT_AND', + 2: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', + 3: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 4: 'CURSOR_COLOR_64BIT_FP_PREMULT', + 5: 'CURSOR_COLOR_64BIT_FP_UNPREMULT', +} +CURSOR_MONO_2BIT = 0 +CURSOR_COLOR_24BIT_1BIT_AND = 1 +CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 +CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 +CURSOR_COLOR_64BIT_FP_PREMULT = 4 +CURSOR_COLOR_64BIT_FP_UNPREMULT = 5 +CURSOR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_EN' +CURSOR_PERFMON_LATENCY_MEASURE_EN__enumvalues = { + 0: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', + 1: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', +} +CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0 +CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 1 +CURSOR_PERFMON_LATENCY_MEASURE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_SEL' +CURSOR_PERFMON_LATENCY_MEASURE_SEL__enumvalues = { + 0: 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', + 1: 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', +} +CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0 +CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 1 +CURSOR_PERFMON_LATENCY_MEASURE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PITCH' +CURSOR_PITCH__enumvalues = { + 0: 'CURSOR_PITCH_64_PIXELS', + 1: 'CURSOR_PITCH_128_PIXELS', + 2: 'CURSOR_PITCH_256_PIXELS', +} +CURSOR_PITCH_64_PIXELS = 0 +CURSOR_PITCH_128_PIXELS = 1 +CURSOR_PITCH_256_PIXELS = 2 +CURSOR_PITCH = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_REQ_MODE' +CURSOR_REQ_MODE__enumvalues = { + 0: 'CURSOR_REQUEST_NORMALLY', + 1: 'CURSOR_REQUEST_EARLY', +} +CURSOR_REQUEST_NORMALLY = 0 +CURSOR_REQUEST_EARLY = 1 +CURSOR_REQ_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SNOOP' +CURSOR_SNOOP__enumvalues = { + 0: 'CURSOR_IS_NOT_SNOOP', + 1: 'CURSOR_IS_SNOOP', +} +CURSOR_IS_NOT_SNOOP = 0 +CURSOR_IS_SNOOP = 1 +CURSOR_SNOOP = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_STEREO_EN' +CURSOR_STEREO_EN__enumvalues = { + 0: 'CURSOR_STEREO_IS_DISABLED', + 1: 'CURSOR_STEREO_IS_ENABLED', +} +CURSOR_STEREO_IS_DISABLED = 0 +CURSOR_STEREO_IS_ENABLED = 1 +CURSOR_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SURFACE_TMZ' +CURSOR_SURFACE_TMZ__enumvalues = { + 0: 'CURSOR_SURFACE_IS_NOT_TMZ', + 1: 'CURSOR_SURFACE_IS_TMZ', +} +CURSOR_SURFACE_IS_NOT_TMZ = 0 +CURSOR_SURFACE_IS_TMZ = 1 +CURSOR_SURFACE_TMZ = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SYSTEM' +CURSOR_SYSTEM__enumvalues = { + 0: 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', + 1: 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', +} +CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0 +CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 1 +CURSOR_SYSTEM = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS' +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__enumvalues = { + 0: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', + 1: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', +} +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0 +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 1 +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_DONE' +DMDATA_DONE__enumvalues = { + 0: 'DMDATA_NOT_SENT_TO_DIG', + 1: 'DMDATA_SENT_TO_DIG', +} +DMDATA_NOT_SENT_TO_DIG = 0 +DMDATA_SENT_TO_DIG = 1 +DMDATA_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_MODE' +DMDATA_MODE__enumvalues = { + 0: 'DMDATA_SOFTWARE_UPDATE_MODE', + 1: 'DMDATA_HARDWARE_UPDATE_MODE', +} +DMDATA_SOFTWARE_UPDATE_MODE = 0 +DMDATA_HARDWARE_UPDATE_MODE = 1 +DMDATA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_QOS_MODE' +DMDATA_QOS_MODE__enumvalues = { + 0: 'DMDATA_QOS_LEVEL_FROM_TTU', + 1: 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', +} +DMDATA_QOS_LEVEL_FROM_TTU = 0 +DMDATA_QOS_LEVEL_FROM_SOFTWARE = 1 +DMDATA_QOS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_REPEAT' +DMDATA_REPEAT__enumvalues = { + 0: 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', + 1: 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', +} +DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0 +DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 1 +DMDATA_REPEAT = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UNDERFLOW' +DMDATA_UNDERFLOW__enumvalues = { + 0: 'DMDATA_NOT_UNDERFLOW', + 1: 'DMDATA_UNDERFLOWED', +} +DMDATA_NOT_UNDERFLOW = 0 +DMDATA_UNDERFLOWED = 1 +DMDATA_UNDERFLOW = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UNDERFLOW_CLEAR' +DMDATA_UNDERFLOW_CLEAR__enumvalues = { + 0: 'DMDATA_DONT_CLEAR', + 1: 'DMDATA_CLEAR_UNDERFLOW_STATUS', +} +DMDATA_DONT_CLEAR = 0 +DMDATA_CLEAR_UNDERFLOW_STATUS = 1 +DMDATA_UNDERFLOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UPDATED' +DMDATA_UPDATED__enumvalues = { + 0: 'DMDATA_NOT_UPDATED', + 1: 'DMDATA_WAS_UPDATED', +} +DMDATA_NOT_UPDATED = 0 +DMDATA_WAS_UPDATED = 1 +DMDATA_UPDATED = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_3DLUT_ADDRESSING_MODE' +HUBP_3DLUT_ADDRESSING_MODE__enumvalues = { + 0: 'HUBP_3DLUT_SW_LINEAR', + 1: 'HUBP_3DLUT_SIMPLE_LINEAR', +} +HUBP_3DLUT_SW_LINEAR = 0 +HUBP_3DLUT_SIMPLE_LINEAR = 1 +HUBP_3DLUT_ADDRESSING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'RESPONSE_STATUS' +RESPONSE_STATUS__enumvalues = { + 0: 'OKAY', + 1: 'EXOKAY', + 2: 'SLVERR', + 3: 'DECERR', + 4: 'EARLY', + 5: 'OKAY_NODATA', + 6: 'PROTVIOL', + 7: 'TRANSERR', + 8: 'CMPTO', + 12: 'CRS', +} +OKAY = 0 +EXOKAY = 1 +SLVERR = 2 +DECERR = 3 +EARLY = 4 +OKAY_NODATA = 5 +PROTVIOL = 6 +TRANSERR = 7 +CMPTO = 8 +CRS = 12 +RESPONSE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE' +DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', + 2: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', +} +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 +DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCHUBBUB_MEM_PWR_DIS_MODE' +DCHUBBUB_MEM_PWR_DIS_MODE__enumvalues = { + 0: 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', + 1: 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', +} +DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0 +DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 1 +DCHUBBUB_MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCHUBBUB_MEM_PWR_MODE' +DCHUBBUB_MEM_PWR_MODE__enumvalues = { + 0: 'DCHUBBUB_MEM_POWER_MODE_OFF', + 1: 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', + 2: 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', + 3: 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', +} +DCHUBBUB_MEM_POWER_MODE_OFF = 0 +DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 1 +DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 2 +DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 3 +DCHUBBUB_MEM_PWR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_3DLUT_FL_FORMAT' +MPC_CFG_3DLUT_FL_FORMAT__enumvalues = { + 0: 'MPC_CFG_3DLUT_FL_FORMAT_0', + 1: 'MPC_CFG_3DLUT_FL_FORMAT_1', + 2: 'MPC_CFG_3DLUT_FL_FORMAT_2', +} +MPC_CFG_3DLUT_FL_FORMAT_0 = 0 +MPC_CFG_3DLUT_FL_FORMAT_1 = 1 +MPC_CFG_3DLUT_FL_FORMAT_2 = 2 +MPC_CFG_3DLUT_FL_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_3DLUT_FL_MODE' +MPC_CFG_3DLUT_FL_MODE__enumvalues = { + 0: 'MPC_CFG_3DLUT_FL_MODE_0', + 1: 'MPC_CFG_3DLUT_FL_MODE_1', + 2: 'MPC_CFG_3DLUT_FL_MODE_2', + 3: 'MPC_CFG_3DLUT_FL_MODE_3', +} +MPC_CFG_3DLUT_FL_MODE_0 = 0 +MPC_CFG_3DLUT_FL_MODE_1 = 1 +MPC_CFG_3DLUT_FL_MODE_2 = 2 +MPC_CFG_3DLUT_FL_MODE_3 = 3 +MPC_CFG_3DLUT_FL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET' +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET' +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_VUPDATE_LOCK_SET' +MPC_CFG_ADR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_CFG_VUPDATE_LOCK_SET' +MPC_CFG_CFG_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_CUR_VUPDATE_LOCK_SET' +MPC_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_MPC_TEST_CLK_SEL' +MPC_CFG_MPC_TEST_CLK_SEL__enumvalues = { + 0: 'MPC_CFG_MPC_TEST_CLK_SEL_0', + 1: 'MPC_CFG_MPC_TEST_CLK_SEL_1', + 2: 'MPC_CFG_MPC_TEST_CLK_SEL_2', + 3: 'MPC_CFG_MPC_TEST_CLK_SEL_3', +} +MPC_CFG_MPC_TEST_CLK_SEL_0 = 0 +MPC_CFG_MPC_TEST_CLK_SEL_1 = 1 +MPC_CFG_MPC_TEST_CLK_SEL_2 = 2 +MPC_CFG_MPC_TEST_CLK_SEL_3 = 3 +MPC_CFG_MPC_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN' +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', +} +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_INTERLACE_MODE' +MPC_CRC_CALC_INTERLACE_MODE__enumvalues = { + 0: 'MPC_CRC_INTERLACE_MODE_TOP', + 1: 'MPC_CRC_INTERLACE_MODE_BOTTOM', + 2: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', + 3: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', +} +MPC_CRC_INTERLACE_MODE_TOP = 0 +MPC_CRC_INTERLACE_MODE_BOTTOM = 1 +MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 2 +MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 3 +MPC_CRC_CALC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_MODE' +MPC_CRC_CALC_MODE__enumvalues = { + 0: 'MPC_CRC_ONE_SHOT_MODE', + 1: 'MPC_CRC_CONTINUOUS_MODE', +} +MPC_CRC_ONE_SHOT_MODE = 0 +MPC_CRC_CONTINUOUS_MODE = 1 +MPC_CRC_CALC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_STEREO_MODE' +MPC_CRC_CALC_STEREO_MODE__enumvalues = { + 0: 'MPC_CRC_STEREO_MODE_LEFT', + 1: 'MPC_CRC_STEREO_MODE_RIGHT', + 2: 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', + 3: 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', +} +MPC_CRC_STEREO_MODE_LEFT = 0 +MPC_CRC_STEREO_MODE_RIGHT = 1 +MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 2 +MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 3 +MPC_CRC_CALC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_SOURCE_SELECT' +MPC_CRC_SOURCE_SELECT__enumvalues = { + 0: 'MPC_CRC_SOURCE_SEL_DPP', + 1: 'MPC_CRC_SOURCE_SEL_OPP', + 2: 'MPC_CRC_SOURCE_SEL_DWB', + 3: 'MPC_CRC_SOURCE_SEL_OTHER', +} +MPC_CRC_SOURCE_SEL_DPP = 0 +MPC_CRC_SOURCE_SEL_OPP = 1 +MPC_CRC_SOURCE_SEL_DWB = 2 +MPC_CRC_SOURCE_SEL_OTHER = 3 +MPC_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OCSC_COEF_FORMAT' +MPC_OCSC_COEF_FORMAT__enumvalues = { + 0: 'MPC_OCSC_COEF_FORMAT_S2_13', + 1: 'MPC_OCSC_COEF_FORMAT_S3_12', +} +MPC_OCSC_COEF_FORMAT_S2_13 = 0 +MPC_OCSC_COEF_FORMAT_S3_12 = 1 +MPC_OCSC_COEF_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN' +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', +} +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_CSC_MODE' +MPC_OUT_CSC_MODE__enumvalues = { + 0: 'MPC_OUT_CSC_MODE_0', + 1: 'MPC_OUT_CSC_MODE_1', + 2: 'MPC_OUT_CSC_MODE_2', + 3: 'MPC_OUT_CSC_MODE_RSV', +} +MPC_OUT_CSC_MODE_0 = 0 +MPC_OUT_CSC_MODE_1 = 1 +MPC_OUT_CSC_MODE_2 = 2 +MPC_OUT_CSC_MODE_RSV = 3 +MPC_OUT_CSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE' +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE__enumvalues = { + 0: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', + 1: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', + 2: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', + 3: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', + 4: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', + 5: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', + 6: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', + 7: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', +} +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 1 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 2 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 3 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 4 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 5 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 6 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 7 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_RATE_CONTROL_DISABLE_SET' +MPC_OUT_RATE_CONTROL_DISABLE_SET__enumvalues = { + 0: 'MPC_OUT_RATE_CONTROL_SET_ENABLE', + 1: 'MPC_OUT_RATE_CONTROL_SET_DISABLE', +} +MPC_OUT_RATE_CONTROL_SET_ENABLE = 0 +MPC_OUT_RATE_CONTROL_SET_DISABLE = 1 +MPC_OUT_RATE_CONTROL_DISABLE_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_BG_COLOR_BPC' +MPCC_BG_COLOR_BPC__enumvalues = { + 0: 'MPCC_BG_COLOR_BPC_8bit', + 1: 'MPCC_BG_COLOR_BPC_9bit', + 2: 'MPCC_BG_COLOR_BPC_10bit', + 3: 'MPCC_BG_COLOR_BPC_11bit', + 4: 'MPCC_BG_COLOR_BPC_12bit', +} +MPCC_BG_COLOR_BPC_8bit = 0 +MPCC_BG_COLOR_BPC_9bit = 1 +MPCC_BG_COLOR_BPC_10bit = 2 +MPCC_BG_COLOR_BPC_11bit = 3 +MPCC_BG_COLOR_BPC_12bit = 4 +MPCC_BG_COLOR_BPC = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY' +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', + 1: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', +} +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0 +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 1 +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE' +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', + 1: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 2: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', + 3: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', +} +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 2 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 3 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE' +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', + 1: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', +} +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0 +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 1 +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE' +MPCC_CONTROL_MPCC_BOT_GAIN_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', + 1: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', +} +MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0 +MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 1 +MPCC_CONTROL_MPCC_BOT_GAIN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_MODE' +MPCC_CONTROL_MPCC_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_MODE_BYPASS', + 1: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', + 2: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', + 3: 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', +} +MPCC_CONTROL_MPCC_MODE_BYPASS = 0 +MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 1 +MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 2 +MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 3 +MPCC_CONTROL_MPCC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_EN' +MPCC_SM_CONTROL_MPCC_SM_EN__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT' +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL' +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', +} +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL' +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', + 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', +} +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT' +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_MODE' +MPCC_SM_CONTROL_MPCC_SM_MODE__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', + 2: 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', + 4: 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', + 6: 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', +} +MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0 +MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 2 +MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 4 +MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 +MPCC_SM_CONTROL_MPCC_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM' +MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { + 0: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', + 1: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', +} +MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 +MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 +MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_GAMUT_REMAP_MODE_ENUM' +MPCC_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'MPCC_GAMUT_REMAP_MODE_0', + 1: 'MPCC_GAMUT_REMAP_MODE_1', + 2: 'MPCC_GAMUT_REMAP_MODE_2', + 3: 'MPCC_GAMUT_REMAP_MODE_RSV', +} +MPCC_GAMUT_REMAP_MODE_0 = 0 +MPCC_GAMUT_REMAP_MODE_1 = 1 +MPCC_GAMUT_REMAP_MODE_2 = 2 +MPCC_GAMUT_REMAP_MODE_RSV = 3 +MPCC_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_2_CONFIG_ENUM' +MPCC_OGAM_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', + 1: 'MPCC_OGAM_LUT_2CFG_MEMORY_A', + 2: 'MPCC_OGAM_LUT_2CFG_MEMORY_B', +} +MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0 +MPCC_OGAM_LUT_2CFG_MEMORY_A = 1 +MPCC_OGAM_LUT_2CFG_MEMORY_B = 2 +MPCC_OGAM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_CONFIG_MODE' +MPCC_OGAM_LUT_CONFIG_MODE__enumvalues = { + 0: 'MPCC_OGAM_DIFFERENT_RGB', + 1: 'MPCC_OGAM_ALL_USE_R', +} +MPCC_OGAM_DIFFERENT_RGB = 0 +MPCC_OGAM_ALL_USE_R = 1 +MPCC_OGAM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM' +MPCC_OGAM_LUT_PWL_DISABLE_ENUM__enumvalues = { + 0: 'MPCC_OGAM_ENABLE_PWL', + 1: 'MPCC_OGAM_DISABLE_PWL', +} +MPCC_OGAM_ENABLE_PWL = 0 +MPCC_OGAM_DISABLE_PWL = 1 +MPCC_OGAM_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL' +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', + 1: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', +} +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0 +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 1 +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_RAM_SEL' +MPCC_OGAM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_OGAM_RAMA_ACCESS', + 1: 'MPCC_OGAM_RAMB_ACCESS', +} +MPCC_OGAM_RAMA_ACCESS = 0 +MPCC_OGAM_RAMB_ACCESS = 1 +MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_READ_COLOR_SEL' +MPCC_OGAM_LUT_READ_COLOR_SEL__enumvalues = { + 0: 'MPCC_OGAM_BLUE_LUT', + 1: 'MPCC_OGAM_GREEN_LUT', + 2: 'MPCC_OGAM_RED_LUT', +} +MPCC_OGAM_BLUE_LUT = 0 +MPCC_OGAM_GREEN_LUT = 1 +MPCC_OGAM_RED_LUT = 2 +MPCC_OGAM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_READ_DBG' +MPCC_OGAM_LUT_READ_DBG__enumvalues = { + 0: 'MPCC_OGAM_DISABLE_DEBUG', + 1: 'MPCC_OGAM_ENABLE_DEBUG', +} +MPCC_OGAM_DISABLE_DEBUG = 0 +MPCC_OGAM_ENABLE_DEBUG = 1 +MPCC_OGAM_LUT_READ_DBG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_SEL_ENUM' +MPCC_OGAM_LUT_SEL_ENUM__enumvalues = { + 0: 'MPCC_OGAM_RAMA', + 1: 'MPCC_OGAM_RAMB', +} +MPCC_OGAM_RAMA = 0 +MPCC_OGAM_RAMB = 1 +MPCC_OGAM_LUT_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM' +MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM__enumvalues = { + 0: 'MPCC_OGAM_MODE_0', + 1: 'MPCC_OGAM_MODE_RSV1', + 2: 'MPCC_OGAM_MODE_2', + 3: 'MPCC_OGAM_MODE_RSV', +} +MPCC_OGAM_MODE_0 = 0 +MPCC_OGAM_MODE_RSV1 = 1 +MPCC_OGAM_MODE_2 = 2 +MPCC_OGAM_MODE_RSV = 3 +MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_NUM_SEG' +MPCC_OGAM_NUM_SEG__enumvalues = { + 0: 'MPCC_OGAM_SEGMENTS_1', + 1: 'MPCC_OGAM_SEGMENTS_2', + 2: 'MPCC_OGAM_SEGMENTS_4', + 3: 'MPCC_OGAM_SEGMENTS_8', + 4: 'MPCC_OGAM_SEGMENTS_16', + 5: 'MPCC_OGAM_SEGMENTS_32', + 6: 'MPCC_OGAM_SEGMENTS_64', + 7: 'MPCC_OGAM_SEGMENTS_128', +} +MPCC_OGAM_SEGMENTS_1 = 0 +MPCC_OGAM_SEGMENTS_2 = 1 +MPCC_OGAM_SEGMENTS_4 = 2 +MPCC_OGAM_SEGMENTS_8 = 3 +MPCC_OGAM_SEGMENTS_16 = 4 +MPCC_OGAM_SEGMENTS_32 = 5 +MPCC_OGAM_SEGMENTS_64 = 6 +MPCC_OGAM_SEGMENTS_128 = 7 +MPCC_OGAM_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN' +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', +} +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_3DLUT_30BIT_ENUM' +MPCC_MCM_3DLUT_30BIT_ENUM__enumvalues = { + 0: 'MPCC_MCM_3DLUT_36BIT', + 1: 'MPCC_MCM_3DLUT_30BIT', +} +MPCC_MCM_3DLUT_36BIT = 0 +MPCC_MCM_3DLUT_30BIT = 1 +MPCC_MCM_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_3DLUT_RAM_SEL' +MPCC_MCM_3DLUT_RAM_SEL__enumvalues = { + 0: 'MPCC_MCM_RAM0_ACCESS', + 1: 'MPCC_MCM_RAM1_ACCESS', + 2: 'MPCC_MCM_RAM2_ACCESS', + 3: 'MPCC_MCM_RAM3_ACCESS', +} +MPCC_MCM_RAM0_ACCESS = 0 +MPCC_MCM_RAM1_ACCESS = 1 +MPCC_MCM_RAM2_ACCESS = 2 +MPCC_MCM_RAM3_ACCESS = 3 +MPCC_MCM_3DLUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_3DLUT_SIZE_ENUM' +MPCC_MCM_3DLUT_SIZE_ENUM__enumvalues = { + 0: 'MPCC_MCM_3DLUT_17CUBE', + 1: 'MPCC_MCM_3DLUT_9CUBE', +} +MPCC_MCM_3DLUT_17CUBE = 0 +MPCC_MCM_3DLUT_9CUBE = 1 +MPCC_MCM_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMMA_LUT_MODE_ENUM' +MPCC_MCM_GAMMA_LUT_MODE_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMMA_LUT_BYPASS', + 1: 'MPCC_MCM_GAMMA_LUT_RESERVED_1', + 2: 'MPCC_MCM_GAMMA_LUT_RAM_LUT', + 3: 'MPCC_MCM_GAMMA_LUT_RESERVED_3', +} +MPCC_MCM_GAMMA_LUT_BYPASS = 0 +MPCC_MCM_GAMMA_LUT_RESERVED_1 = 1 +MPCC_MCM_GAMMA_LUT_RAM_LUT = 2 +MPCC_MCM_GAMMA_LUT_RESERVED_3 = 3 +MPCC_MCM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM' +MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', + 1: 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', +} +MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0 +MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 1 +MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMMA_LUT_SEL_ENUM' +MPCC_MCM_GAMMA_LUT_SEL_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMMA_LUT_RAMA', + 1: 'MPCC_MCM_GAMMA_LUT_RAMB', +} +MPCC_MCM_GAMMA_LUT_RAMA = 0 +MPCC_MCM_GAMMA_LUT_RAMB = 1 +MPCC_MCM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM' +MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S2_13', + 1: 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S3_12', +} +MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 +MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 +MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMUT_REMAP_MODE_ENUM' +MPCC_MCM_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMUT_REMAP_MODE_0', + 1: 'MPCC_MCM_GAMUT_REMAP_MODE_1', + 2: 'MPCC_MCM_GAMUT_REMAP_MODE_2', + 3: 'MPCC_MCM_GAMUT_REMAP_MODE_RSV', +} +MPCC_MCM_GAMUT_REMAP_MODE_0 = 0 +MPCC_MCM_GAMUT_REMAP_MODE_1 = 1 +MPCC_MCM_GAMUT_REMAP_MODE_2 = 2 +MPCC_MCM_GAMUT_REMAP_MODE_RSV = 3 +MPCC_MCM_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_2_MODE_ENUM' +MPCC_MCM_LUT_2_MODE_ENUM__enumvalues = { + 0: 'MPCC_MCM_LUT_2_MODE_BYPASS', + 1: 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', + 2: 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', +} +MPCC_MCM_LUT_2_MODE_BYPASS = 0 +MPCC_MCM_LUT_2_MODE_RAMA_LUT = 1 +MPCC_MCM_LUT_2_MODE_RAMB_LUT = 2 +MPCC_MCM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_CONFIG_MODE' +MPCC_MCM_LUT_CONFIG_MODE__enumvalues = { + 0: 'MPCC_MCM_LUT_DIFFERENT_RGB', + 1: 'MPCC_MCM_LUT_ALL_USE_R', +} +MPCC_MCM_LUT_DIFFERENT_RGB = 0 +MPCC_MCM_LUT_ALL_USE_R = 1 +MPCC_MCM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_NUM_SEG' +MPCC_MCM_LUT_NUM_SEG__enumvalues = { + 0: 'MPCC_MCM_LUT_SEGMENTS_1', + 1: 'MPCC_MCM_LUT_SEGMENTS_2', + 2: 'MPCC_MCM_LUT_SEGMENTS_4', + 3: 'MPCC_MCM_LUT_SEGMENTS_8', + 4: 'MPCC_MCM_LUT_SEGMENTS_16', + 5: 'MPCC_MCM_LUT_SEGMENTS_32', + 6: 'MPCC_MCM_LUT_SEGMENTS_64', + 7: 'MPCC_MCM_LUT_SEGMENTS_128', +} +MPCC_MCM_LUT_SEGMENTS_1 = 0 +MPCC_MCM_LUT_SEGMENTS_2 = 1 +MPCC_MCM_LUT_SEGMENTS_4 = 2 +MPCC_MCM_LUT_SEGMENTS_8 = 3 +MPCC_MCM_LUT_SEGMENTS_16 = 4 +MPCC_MCM_LUT_SEGMENTS_32 = 5 +MPCC_MCM_LUT_SEGMENTS_64 = 6 +MPCC_MCM_LUT_SEGMENTS_128 = 7 +MPCC_MCM_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_RAM_SEL' +MPCC_MCM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_MCM_LUT_RAMA_ACCESS', + 1: 'MPCC_MCM_LUT_RAMB_ACCESS', +} +MPCC_MCM_LUT_RAMA_ACCESS = 0 +MPCC_MCM_LUT_RAMB_ACCESS = 1 +MPCC_MCM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_READ_COLOR_SEL' +MPCC_MCM_LUT_READ_COLOR_SEL__enumvalues = { + 0: 'MPCC_MCM_LUT_BLUE_LUT', + 1: 'MPCC_MCM_LUT_GREEN_LUT', + 2: 'MPCC_MCM_LUT_RED_LUT', +} +MPCC_MCM_LUT_BLUE_LUT = 0 +MPCC_MCM_LUT_GREEN_LUT = 1 +MPCC_MCM_LUT_RED_LUT = 2 +MPCC_MCM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_READ_DBG' +MPCC_MCM_LUT_READ_DBG__enumvalues = { + 0: 'MPCC_MCM_LUT_DISABLE_DEBUG', + 1: 'MPCC_MCM_LUT_ENABLE_DEBUG', +} +MPCC_MCM_LUT_DISABLE_DEBUG = 0 +MPCC_MCM_LUT_ENABLE_DEBUG = 1 +MPCC_MCM_LUT_READ_DBG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_MEM_PWR_FORCE_ENUM' +MPCC_MCM_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'MPCC_MCM_MEM_PWR_FORCE_DIS', + 1: 'MPCC_MCM_MEM_PWR_FORCE_LS', + 2: 'MPCC_MCM_MEM_PWR_FORCE_DS', + 3: 'MPCC_MCM_MEM_PWR_FORCE_SD', +} +MPCC_MCM_MEM_PWR_FORCE_DIS = 0 +MPCC_MCM_MEM_PWR_FORCE_LS = 1 +MPCC_MCM_MEM_PWR_FORCE_DS = 2 +MPCC_MCM_MEM_PWR_FORCE_SD = 3 +MPCC_MCM_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_MEM_PWR_STATE_ENUM' +MPCC_MCM_MEM_PWR_STATE_ENUM__enumvalues = { + 0: 'MPCC_MCM_MEM_PWR_STATE_ON', + 1: 'MPCC_MCM_MEM_PWR_STATE_LS', + 2: 'MPCC_MCM_MEM_PWR_STATE_DS', + 3: 'MPCC_MCM_MEM_PWR_STATE_SD', +} +MPCC_MCM_MEM_PWR_STATE_ON = 0 +MPCC_MCM_MEM_PWR_STATE_LS = 1 +MPCC_MCM_MEM_PWR_STATE_DS = 2 +MPCC_MCM_MEM_PWR_STATE_SD = 3 +MPCC_MCM_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_BIT_DEPTH' +ENUM_DPG_BIT_DEPTH__enumvalues = { + 0: 'ENUM_DPG_BIT_DEPTH_6BPC', + 1: 'ENUM_DPG_BIT_DEPTH_8BPC', + 2: 'ENUM_DPG_BIT_DEPTH_10BPC', + 3: 'ENUM_DPG_BIT_DEPTH_12BPC', +} +ENUM_DPG_BIT_DEPTH_6BPC = 0 +ENUM_DPG_BIT_DEPTH_8BPC = 1 +ENUM_DPG_BIT_DEPTH_10BPC = 2 +ENUM_DPG_BIT_DEPTH_12BPC = 3 +ENUM_DPG_BIT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_DYNAMIC_RANGE' +ENUM_DPG_DYNAMIC_RANGE__enumvalues = { + 0: 'ENUM_DPG_DYNAMIC_RANGE_VESA', + 1: 'ENUM_DPG_DYNAMIC_RANGE_CEA', +} +ENUM_DPG_DYNAMIC_RANGE_VESA = 0 +ENUM_DPG_DYNAMIC_RANGE_CEA = 1 +ENUM_DPG_DYNAMIC_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_EN' +ENUM_DPG_EN__enumvalues = { + 0: 'ENUM_DPG_DISABLE', + 1: 'ENUM_DPG_ENABLE', +} +ENUM_DPG_DISABLE = 0 +ENUM_DPG_ENABLE = 1 +ENUM_DPG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_FIELD_POLARITY' +ENUM_DPG_FIELD_POLARITY__enumvalues = { + 0: 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', + 1: 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', +} +ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0 +ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1 +ENUM_DPG_FIELD_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_MODE' +ENUM_DPG_MODE__enumvalues = { + 0: 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', + 1: 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', + 2: 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', + 3: 'ENUM_DPG_MODE_VERTICAL_BAR', + 4: 'ENUM_DPG_MODE_HORIZONTAL_BAR', + 5: 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', + 6: 'ENUM_DPG_MODE_RGB_DUAL_RAMP', + 7: 'ENUM_DPG_MODE_RGB_XR_BIAS', +} +ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0 +ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 1 +ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 2 +ENUM_DPG_MODE_VERTICAL_BAR = 3 +ENUM_DPG_MODE_HORIZONTAL_BAR = 4 +ENUM_DPG_MODE_RGB_SINGLE_RAMP = 5 +ENUM_DPG_MODE_RGB_DUAL_RAMP = 6 +ENUM_DPG_MODE_RGB_XR_BIAS = 7 +ENUM_DPG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMTMEM_PWR_DIS_CTRL' +FMTMEM_PWR_DIS_CTRL__enumvalues = { + 0: 'FMTMEM_ENABLE_MEM_PWR_CTRL', + 1: 'FMTMEM_DISABLE_MEM_PWR_CTRL', +} +FMTMEM_ENABLE_MEM_PWR_CTRL = 0 +FMTMEM_DISABLE_MEM_PWR_CTRL = 1 +FMTMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'FMTMEM_PWR_FORCE_CTRL' +FMTMEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'FMTMEM_NO_FORCE_REQUEST', + 1: 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', +} +FMTMEM_NO_FORCE_REQUEST = 0 +FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 2 +FMTMEM_FORCE_SHUT_DOWN_REQUEST = 3 +FMTMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' +FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' +FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', +} +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' +FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' +FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { + 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', +} +FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 +FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 +FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 +FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 +FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 +FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { + 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', +} +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' +FMT_CONTROL_PIXEL_ENCODING__enumvalues = { + 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', +} +FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 +FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 +FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 +FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 +FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' +FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', +} +FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 +FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 +FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 +FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 +FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' +FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', +} +FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 +FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 +FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT' +FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = { + 0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', + 1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', + 2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', + 3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', +} +FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0 +FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1 +FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2 +FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3 +FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DYNAMIC_EXP_MODE' +FMT_DYNAMIC_EXP_MODE__enumvalues = { + 0: 'FMT_DYNAMIC_EXP_MODE_10to12', + 1: 'FMT_DYNAMIC_EXP_MODE_8to12', +} +FMT_DYNAMIC_EXP_MODE_10to12 = 0 +FMT_DYNAMIC_EXP_MODE_8to12 = 1 +FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_FRAME_RANDOM_ENABLE_CONTROL' +FMT_FRAME_RANDOM_ENABLE_CONTROL__enumvalues = { + 0: 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', + 1: 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', +} +FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0 +FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 1 +FMT_FRAME_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_POWER_STATE_ENUM' +FMT_POWER_STATE_ENUM__enumvalues = { + 0: 'FMT_POWER_STATE_ENUM_ON', + 1: 'FMT_POWER_STATE_ENUM_LS', + 2: 'FMT_POWER_STATE_ENUM_DS', + 3: 'FMT_POWER_STATE_ENUM_SD', +} +FMT_POWER_STATE_ENUM_ON = 0 +FMT_POWER_STATE_ENUM_LS = 1 +FMT_POWER_STATE_ENUM_DS = 2 +FMT_POWER_STATE_ENUM_SD = 3 +FMT_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_RGB_RANDOM_ENABLE_CONTROL' +FMT_RGB_RANDOM_ENABLE_CONTROL__enumvalues = { + 0: 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', + 1: 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', +} +FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0 +FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 1 +FMT_RGB_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL' +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL__enumvalues = { + 0: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', + 1: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', + 2: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', + 3: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', +} +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 1 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 2 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 3 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_SPATIAL_DITHER_MODE' +FMT_SPATIAL_DITHER_MODE__enumvalues = { + 0: 'FMT_SPATIAL_DITHER_MODE_0', + 1: 'FMT_SPATIAL_DITHER_MODE_1', + 2: 'FMT_SPATIAL_DITHER_MODE_2', + 3: 'FMT_SPATIAL_DITHER_MODE_3', +} +FMT_SPATIAL_DITHER_MODE_0 = 0 +FMT_SPATIAL_DITHER_MODE_1 = 1 +FMT_SPATIAL_DITHER_MODE_2 = 2 +FMT_SPATIAL_DITHER_MODE_3 = 3 +FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_STEREOSYNC_OVERRIDE_CONTROL' +FMT_STEREOSYNC_OVERRIDE_CONTROL__enumvalues = { + 0: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', + 1: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', +} +FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0 +FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 1 +FMT_STEREOSYNC_OVERRIDE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { + 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', +} +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum + +# values for enumeration 'OPPBUF_DISPLAY_SEGMENTATION' +OPPBUF_DISPLAY_SEGMENTATION__enumvalues = { + 0: 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', + 1: 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', + 2: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', + 3: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', + 4: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', +} +OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0 +OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1 +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2 +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3 +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4 +OPPBUF_DISPLAY_SEGMENTATION = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CLOCK_ENABLE_CONTROL' +OPP_PIPE_CLOCK_ENABLE_CONTROL__enumvalues = { + 0: 'OPP_PIPE_CLOCK_DISABLE', + 1: 'OPP_PIPE_CLOCK_ENABLE', +} +OPP_PIPE_CLOCK_DISABLE = 0 +OPP_PIPE_CLOCK_ENABLE = 1 +OPP_PIPE_CLOCK_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL' +OPP_PIPE_DIGTIAL_BYPASS_CONTROL__enumvalues = { + 0: 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', + 1: 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', +} +OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0 +OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 1 +OPP_PIPE_DIGTIAL_BYPASS_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_CONT_EN' +OPP_PIPE_CRC_CONT_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_MODE_ONE_SHOT', + 1: 'OPP_PIPE_CRC_MODE_CONTINUOUS', +} +OPP_PIPE_CRC_MODE_ONE_SHOT = 0 +OPP_PIPE_CRC_MODE_CONTINUOUS = 1 +OPP_PIPE_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_EN' +OPP_PIPE_CRC_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_DISABLE', + 1: 'OPP_PIPE_CRC_ENABLE', +} +OPP_PIPE_CRC_DISABLE = 0 +OPP_PIPE_CRC_ENABLE = 1 +OPP_PIPE_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_INTERLACE_EN' +OPP_PIPE_CRC_INTERLACE_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', + 1: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', +} +OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0 +OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 1 +OPP_PIPE_CRC_INTERLACE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_INTERLACE_MODE' +OPP_PIPE_CRC_INTERLACE_MODE__enumvalues = { + 0: 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', + 1: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', + 2: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', + 3: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', +} +OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0 +OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 1 +OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 2 +OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 3 +OPP_PIPE_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_ONE_SHOT_PENDING' +OPP_PIPE_CRC_ONE_SHOT_PENDING__enumvalues = { + 0: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', + 1: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', +} +OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0 +OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 1 +OPP_PIPE_CRC_ONE_SHOT_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_PIXEL_SELECT' +OPP_PIPE_CRC_PIXEL_SELECT__enumvalues = { + 0: 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', + 1: 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', + 2: 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', + 3: 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', +} +OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0 +OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 1 +OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 2 +OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 3 +OPP_PIPE_CRC_PIXEL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_SOURCE_SELECT' +OPP_PIPE_CRC_SOURCE_SELECT__enumvalues = { + 0: 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', + 1: 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', +} +OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0 +OPP_PIPE_CRC_SOURCE_SELECT_SFT = 1 +OPP_PIPE_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_STEREO_EN' +OPP_PIPE_CRC_STEREO_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', + 1: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', +} +OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0 +OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 1 +OPP_PIPE_CRC_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_STEREO_MODE' +OPP_PIPE_CRC_STEREO_MODE__enumvalues = { + 0: 'OPP_PIPE_CRC_STEREO_MODE_LEFT', + 1: 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', + 2: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', + 3: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', +} +OPP_PIPE_CRC_STEREO_MODE_LEFT = 0 +OPP_PIPE_CRC_STEREO_MODE_RIGHT = 1 +OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 2 +OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 3 +OPP_PIPE_CRC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TEST_CLK_SEL_CONTROL' +OPP_TEST_CLK_SEL_CONTROL__enumvalues = { + 0: 'OPP_TEST_CLK_SEL_DISPCLK_P', + 1: 'OPP_TEST_CLK_SEL_DISPCLK_R', + 2: 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', + 3: 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', + 4: 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', + 5: 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', + 6: 'OPP_TEST_CLK_SEL_RESERVED0', + 7: 'OPP_TEST_CLK_SEL_RESERVED1', + 8: 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', + 9: 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', + 10: 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', + 11: 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', + 12: 'OPP_TEST_CLK_SEL_RESERVED2', + 13: 'OPP_TEST_CLK_SEL_RESERVED3', +} +OPP_TEST_CLK_SEL_DISPCLK_P = 0 +OPP_TEST_CLK_SEL_DISPCLK_R = 1 +OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 2 +OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 3 +OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 4 +OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 5 +OPP_TEST_CLK_SEL_RESERVED0 = 6 +OPP_TEST_CLK_SEL_RESERVED1 = 7 +OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 8 +OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 9 +OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 10 +OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 11 +OPP_TEST_CLK_SEL_RESERVED2 = 12 +OPP_TEST_CLK_SEL_RESERVED3 = 13 +OPP_TEST_CLK_SEL_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TOP_CLOCK_ENABLE_STATUS' +OPP_TOP_CLOCK_ENABLE_STATUS__enumvalues = { + 0: 'OPP_TOP_CLOCK_DISABLED_STATUS', + 1: 'OPP_TOP_CLOCK_ENABLED_STATUS', +} +OPP_TOP_CLOCK_DISABLED_STATUS = 0 +OPP_TOP_CLOCK_ENABLED_STATUS = 1 +OPP_TOP_CLOCK_ENABLE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TOP_CLOCK_GATING_CONTROL' +OPP_TOP_CLOCK_GATING_CONTROL__enumvalues = { + 0: 'OPP_TOP_CLOCK_GATING_ENABLED', + 1: 'OPP_TOP_CLOCK_GATING_DISABLED', +} +OPP_TOP_CLOCK_GATING_ENABLED = 0 +OPP_TOP_CLOCK_GATING_DISABLED = 1 +OPP_TOP_CLOCK_GATING_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', +} +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_SEL' +MASTER_UPDATE_LOCK_SEL__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_SEL_0', + 1: 'MASTER_UPDATE_LOCK_SEL_1', + 2: 'MASTER_UPDATE_LOCK_SEL_2', + 3: 'MASTER_UPDATE_LOCK_SEL_3', + 4: 'MASTER_UPDATE_LOCK_SEL_RESERVED4', + 5: 'MASTER_UPDATE_LOCK_SEL_RESERVED5', +} +MASTER_UPDATE_LOCK_SEL_0 = 0 +MASTER_UPDATE_LOCK_SEL_1 = 1 +MASTER_UPDATE_LOCK_SEL_2 = 2 +MASTER_UPDATE_LOCK_SEL_3 = 3 +MASTER_UPDATE_LOCK_SEL_RESERVED4 = 4 +MASTER_UPDATE_LOCK_SEL_RESERVED5 = 5 +MASTER_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { + 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', + 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', + 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', +} +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 1 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 2 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 2: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 3: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL' +OTG_CONTROL_OTG_DISABLE_POINT_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', + 1: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 2: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', + 3: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', +} +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 2 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL' +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', + 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', +} +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0 +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 1 +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY' +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY__enumvalues = { + 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', + 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', +} +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0 +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 1 +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_MASTER_EN' +OTG_CONTROL_OTG_MASTER_EN__enumvalues = { + 0: 'OTG_CONTROL_OTG_MASTER_EN_FALSE', + 1: 'OTG_CONTROL_OTG_MASTER_EN_TRUE', +} +OTG_CONTROL_OTG_MASTER_EN_FALSE = 0 +OTG_CONTROL_OTG_MASTER_EN_TRUE = 1 +OTG_CONTROL_OTG_MASTER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_OUT_MUX' +OTG_CONTROL_OTG_OUT_MUX__enumvalues = { + 0: 'OTG_CONTROL_OTG_OUT_MUX_0', + 1: 'OTG_CONTROL_OTG_OUT_MUX_1', + 2: 'OTG_CONTROL_OTG_OUT_MUX_2', +} +OTG_CONTROL_OTG_OUT_MUX_0 = 0 +OTG_CONTROL_OTG_OUT_MUX_1 = 1 +OTG_CONTROL_OTG_OUT_MUX_2 = 2 +OTG_CONTROL_OTG_OUT_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_START_POINT_CNTL' +OTG_CONTROL_OTG_START_POINT_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', + 1: 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', +} +OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0 +OTG_CONTROL_OTG_START_POINT_CNTL_DP = 1 +OTG_CONTROL_OTG_START_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN' +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN__enumvalues = { + 0: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', + 1: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', +} +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0 +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 1 +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC1_EN' +OTG_CRC_CNTL_OTG_CRC1_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC1_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_EN' +OTG_CRC_CNTL_OTG_CRC_CONT_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE' +OTG_CRC_CNTL_OTG_CRC_CONT_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', + 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', +} +OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0 +OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 1 +OTG_CRC_CNTL_OTG_CRC_CONT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_EN' +OTG_CRC_CNTL_OTG_CRC_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE' +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', + 1: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', + 2: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 3: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', +} +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 1 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 3 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE' +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', + 1: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', + 2: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', + 3: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', +} +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 1 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 2 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 3 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS' +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT' +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', + 1: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', + 2: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', + 3: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', + 4: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', + 5: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', + 6: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', + 7: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', +} +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 1 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 2 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 3 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 4 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 5 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 6 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 7 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT' +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', + 1: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', + 2: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', + 3: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', + 4: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', + 5: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', + 6: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', + 7: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', +} +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 1 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 2 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 3 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 4 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 5 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 6 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 7 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DIG_UPDATE_VCOUNT_MODE' +OTG_DIG_UPDATE_VCOUNT_MODE__enumvalues = { + 0: 'OTG_DIG_UPDATE_VCOUNT_0', + 1: 'OTG_DIG_UPDATE_VCOUNT_1', +} +OTG_DIG_UPDATE_VCOUNT_0 = 0 +OTG_DIG_UPDATE_VCOUNT_1 = 1 +OTG_DIG_UPDATE_VCOUNT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE' +OTG_DLPC_CONTROL_OTG_RESYNC_MODE__enumvalues = { + 0: 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE_0', + 1: 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE_1', +} +OTG_DLPC_CONTROL_OTG_RESYNC_MODE_0 = 0 +OTG_DLPC_CONTROL_OTG_RESYNC_MODE_1 = 1 +OTG_DLPC_CONTROL_OTG_RESYNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE' +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE__enumvalues = { + 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', + 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', + 2: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', + 3: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', +} +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 1 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 2 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 3 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY' +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY__enumvalues = { + 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', + 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', +} +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0 +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 1 +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME' +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME__enumvalues = { + 0: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', + 1: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', + 2: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', + 3: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', +} +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 1 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 2 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 3 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN' +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN__enumvalues = { + 0: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', + 1: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', +} +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0 +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 1 +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 2: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 3: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 4: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', + 5: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 6: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 7: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 8: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 9: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 10: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 11: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 12: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 13: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 14: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 15: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', + 16: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', + 17: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', + 18: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', + 19: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 2 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 3 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 4 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 5 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 6 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 7 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 8 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 9 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 10 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 11 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 12 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 13 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 14 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 15 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 16 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 17 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 18 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 19 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', + 2: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 3: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 3 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL' +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL__enumvalues = { + 0: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', + 1: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', + 2: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', + 3: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', + 4: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', + 5: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', +} +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 1 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 2 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 3 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 4 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 5 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL' +OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL__enumvalues = { + 0: 'DIG_UPDATE_EYE_SEL_BOTH', + 1: 'DIG_UPDATE_EYE_SEL_LEFT', + 2: 'DIG_UPDATE_EYE_SEL_RIGHT', +} +DIG_UPDATE_EYE_SEL_BOTH = 0 +DIG_UPDATE_EYE_SEL_LEFT = 1 +DIG_UPDATE_EYE_SEL_RIGHT = 2 +OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL' +OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL__enumvalues = { + 0: 'DIG_UPDATE_FIELD_SEL_BOTH', + 1: 'DIG_UPDATE_FIELD_SEL_TOP', + 2: 'DIG_UPDATE_FIELD_SEL_BOTTOM', + 3: 'DIG_UPDATE_FIELD_SEL_RESERVED', +} +DIG_UPDATE_FIELD_SEL_BOTH = 0 +DIG_UPDATE_FIELD_SEL_TOP = 1 +DIG_UPDATE_FIELD_SEL_BOTTOM = 2 +DIG_UPDATE_FIELD_SEL_RESERVED = 3 +OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD' +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', + 1: 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', + 2: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', + 3: 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', +} +MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0 +MASTER_UPDATE_LOCK_DB_FIELD_TOP = 1 +MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 2 +MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 3 +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL' +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', + 1: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', + 2: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', + 3: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', +} +MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 1 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 2 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 3 +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_UPDATE_LOCK_EN' +OTG_GLOBAL_UPDATE_LOCK_EN__enumvalues = { + 0: 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', + 1: 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', +} +OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0 +OTG_GLOBAL_UPDATE_LOCK_ENABLE = 1 +OTG_GLOBAL_UPDATE_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GSL_MASTER_MODE' +OTG_GSL_MASTER_MODE__enumvalues = { + 0: 'OTG_GSL_MASTER_MODE_0', + 1: 'OTG_GSL_MASTER_MODE_1', + 2: 'OTG_GSL_MASTER_MODE_2', + 3: 'OTG_GSL_MASTER_MODE_3', +} +OTG_GSL_MASTER_MODE_0 = 0 +OTG_GSL_MASTER_MODE_1 = 1 +OTG_GSL_MASTER_MODE_2 = 2 +OTG_GSL_MASTER_MODE_3 = 3 +OTG_GSL_MASTER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_HORZ_REPETITION_COUNT' +OTG_HORZ_REPETITION_COUNT__enumvalues = { + 0: 'OTG_HORZ_REPETITION_COUNT_0', + 1: 'OTG_HORZ_REPETITION_COUNT_1', + 2: 'OTG_HORZ_REPETITION_COUNT_2', + 3: 'OTG_HORZ_REPETITION_COUNT_3', + 4: 'OTG_HORZ_REPETITION_COUNT_4', + 5: 'OTG_HORZ_REPETITION_COUNT_5', + 6: 'OTG_HORZ_REPETITION_COUNT_6', + 7: 'OTG_HORZ_REPETITION_COUNT_7', + 8: 'OTG_HORZ_REPETITION_COUNT_8', + 9: 'OTG_HORZ_REPETITION_COUNT_9', + 10: 'OTG_HORZ_REPETITION_COUNT_10', + 11: 'OTG_HORZ_REPETITION_COUNT_11', + 12: 'OTG_HORZ_REPETITION_COUNT_12', + 13: 'OTG_HORZ_REPETITION_COUNT_13', + 14: 'OTG_HORZ_REPETITION_COUNT_14', + 15: 'OTG_HORZ_REPETITION_COUNT_15', +} +OTG_HORZ_REPETITION_COUNT_0 = 0 +OTG_HORZ_REPETITION_COUNT_1 = 1 +OTG_HORZ_REPETITION_COUNT_2 = 2 +OTG_HORZ_REPETITION_COUNT_3 = 3 +OTG_HORZ_REPETITION_COUNT_4 = 4 +OTG_HORZ_REPETITION_COUNT_5 = 5 +OTG_HORZ_REPETITION_COUNT_6 = 6 +OTG_HORZ_REPETITION_COUNT_7 = 7 +OTG_HORZ_REPETITION_COUNT_8 = 8 +OTG_HORZ_REPETITION_COUNT_9 = 9 +OTG_HORZ_REPETITION_COUNT_10 = 10 +OTG_HORZ_REPETITION_COUNT_11 = 11 +OTG_HORZ_REPETITION_COUNT_12 = 12 +OTG_HORZ_REPETITION_COUNT_13 = 13 +OTG_HORZ_REPETITION_COUNT_14 = 14 +OTG_HORZ_REPETITION_COUNT_15 = 15 +OTG_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_SYNC_A_POL' +OTG_H_SYNC_A_POL__enumvalues = { + 0: 'OTG_H_SYNC_A_POL_HIGH', + 1: 'OTG_H_SYNC_A_POL_LOW', +} +OTG_H_SYNC_A_POL_HIGH = 0 +OTG_H_SYNC_A_POL_LOW = 1 +OTG_H_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_TIMING_DIV_MODE' +OTG_H_TIMING_DIV_MODE__enumvalues = { + 0: 'OTG_H_TIMING_DIV_MODE_NO_DIV', + 1: 'OTG_H_TIMING_DIV_MODE_DIV_BY2', + 2: 'OTG_H_TIMING_DIV_MODE_RESERVED', + 3: 'OTG_H_TIMING_DIV_MODE_DIV_BY4', +} +OTG_H_TIMING_DIV_MODE_NO_DIV = 0 +OTG_H_TIMING_DIV_MODE_DIV_BY2 = 1 +OTG_H_TIMING_DIV_MODE_RESERVED = 2 +OTG_H_TIMING_DIV_MODE_DIV_BY4 = 3 +OTG_H_TIMING_DIV_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_TIMING_DIV_MODE_MANUAL' +OTG_H_TIMING_DIV_MODE_MANUAL__enumvalues = { + 0: 'OTG_H_TIMING_DIV_MODE_AUTO', + 1: 'OTG_H_TIMING_DIV_MODE_NOAUTO', +} +OTG_H_TIMING_DIV_MODE_AUTO = 0 +OTG_H_TIMING_DIV_MODE_NOAUTO = 1 +OTG_H_TIMING_DIV_MODE_MANUAL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE' +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE__enumvalues = { + 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', + 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', +} +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 1 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD' +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { + 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', + 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', + 2: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', + 3: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', +} +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 1 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 2 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE' +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { + 0: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 1: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', +} +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_DB_EN' +OTG_MASTER_UPDATE_LOCK_DB_EN__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_DISABLE', + 1: 'OTG_MASTER_UPDATE_LOCK_ENABLE', +} +OTG_MASTER_UPDATE_LOCK_DISABLE = 0 +OTG_MASTER_UPDATE_LOCK_ENABLE = 1 +OTG_MASTER_UPDATE_LOCK_DB_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_GSL_EN' +OTG_MASTER_UPDATE_LOCK_GSL_EN__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', + 1: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', +} +OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0 +OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 1 +OTG_MASTER_UPDATE_LOCK_GSL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE' +OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', + 1: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', +} +OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0 +OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 1 +OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL' +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { + 0: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 1: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 2: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 3: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', +} +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR' +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR__enumvalues = { + 0: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', + 1: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', +} +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0 +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 1 +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE' +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE' +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', +} +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL' +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', +} +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0 +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 1 +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EN' +OTG_STEREO_CONTROL_OTG_STEREO_EN__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY' +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY' +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE' +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE__enumvalues = { + 0: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', + 1: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', + 2: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', + 3: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', +} +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 1 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 2 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 3 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR' +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', +} +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', + 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', + 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', +} +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 6 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 7 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN' +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', +} +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', +} +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', + 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', + 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', + 8: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', + 9: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', + 10: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', + 11: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', + 12: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', + 13: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', + 14: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', + 15: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', + 16: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', + 17: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', + 18: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', + 19: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', + 20: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', + 21: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 22: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 23: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', + 24: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', +} +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 6 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 7 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 8 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 9 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 11 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 12 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 13 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 14 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 15 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 17 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 18 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 19 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 20 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 23 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 24 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL' +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_FREQUENCY_SELECT' +OTG_TRIGA_FREQUENCY_SELECT__enumvalues = { + 0: 'OTG_TRIGA_FREQUENCY_SELECT_0', + 1: 'OTG_TRIGA_FREQUENCY_SELECT_1', + 2: 'OTG_TRIGA_FREQUENCY_SELECT_2', + 3: 'OTG_TRIGA_FREQUENCY_SELECT_3', +} +OTG_TRIGA_FREQUENCY_SELECT_0 = 0 +OTG_TRIGA_FREQUENCY_SELECT_1 = 1 +OTG_TRIGA_FREQUENCY_SELECT_2 = 2 +OTG_TRIGA_FREQUENCY_SELECT_3 = 3 +OTG_TRIGA_FREQUENCY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL' +OTG_TRIGA_RISING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR' +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', +} +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', + 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', + 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', +} +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 6 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 7 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN' +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', +} +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', +} +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', + 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', + 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', + 8: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', + 9: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', + 10: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', + 11: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', + 12: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', + 13: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', + 14: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', + 15: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', + 16: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', + 17: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', + 18: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', + 19: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', + 20: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', + 21: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 22: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 23: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', + 24: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', +} +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 6 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 7 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 8 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 9 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 11 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 12 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 13 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 14 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 15 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 17 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 18 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 19 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 20 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 23 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 24 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL' +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_FREQUENCY_SELECT' +OTG_TRIGB_FREQUENCY_SELECT__enumvalues = { + 0: 'OTG_TRIGB_FREQUENCY_SELECT_0', + 1: 'OTG_TRIGB_FREQUENCY_SELECT_1', + 2: 'OTG_TRIGB_FREQUENCY_SELECT_2', + 3: 'OTG_TRIGB_FREQUENCY_SELECT_3', +} +OTG_TRIGB_FREQUENCY_SELECT_0 = 0 +OTG_TRIGB_FREQUENCY_SELECT_1 = 1 +OTG_TRIGB_FREQUENCY_SELECT_2 = 2 +OTG_TRIGB_FREQUENCY_SELECT_3 = 3 +OTG_TRIGB_FREQUENCY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL' +OTG_TRIGB_RISING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK' +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK__enumvalues = { + 0: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', + 1: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', +} +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0 +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 1 +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE' +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE__enumvalues = { + 0: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', + 1: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 2: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 3: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', +} +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR' +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { + 0: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 1: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', +} +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR' +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR__enumvalues = { + 0: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', + 1: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', +} +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0 +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 1 +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VUPDATE_BLOCK_DISABLE' +OTG_VUPDATE_BLOCK_DISABLE__enumvalues = { + 0: 'OTG_VUPDATE_BLOCK_DISABLE_OFF', + 1: 'OTG_VUPDATE_BLOCK_DISABLE_ON', +} +OTG_VUPDATE_BLOCK_DISABLE_OFF = 0 +OTG_VUPDATE_BLOCK_DISABLE_ON = 1 +OTG_VUPDATE_BLOCK_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_SYNC_A_POL' +OTG_V_SYNC_A_POL__enumvalues = { + 0: 'OTG_V_SYNC_A_POL_HIGH', + 1: 'OTG_V_SYNC_A_POL_LOW', +} +OTG_V_SYNC_A_POL_HIGH = 0 +OTG_V_SYNC_A_POL_LOW = 1 +OTG_V_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_SYNC_MODE' +OTG_V_SYNC_MODE__enumvalues = { + 0: 'OTG_V_SYNC_MODE_HSYNC', + 1: 'OTG_V_SYNC_MODE_HBLANK', +} +OTG_V_SYNC_MODE_HSYNC = 0 +OTG_V_SYNC_MODE_HBLANK = 1 +OTG_V_SYNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD' +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', + 1: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', +} +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0 +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 1 +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT' +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', +} +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 1 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC' +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', +} +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL' +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', +} +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 1 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL' +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', +} +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 1 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK' +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__enumvalues = { + 0: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', + 1: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', +} +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0 +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 1 +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL' +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL__enumvalues = { + 0: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', + 1: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', + 2: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', + 3: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', + 4: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', + 5: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', +} +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 1 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 2 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 3 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 4 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 5 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DC_DMCUB_INT_TYPE' +DC_DMCUB_INT_TYPE__enumvalues = { + 0: 'INT_LEVEL', + 1: 'INT_PULSE', +} +INT_LEVEL = 0 +INT_PULSE = 1 +DC_DMCUB_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DC_DMCUB_TIMER_WINDOW' +DC_DMCUB_TIMER_WINDOW__enumvalues = { + 0: 'BITS_31_0', + 1: 'BITS_32_1', + 2: 'BITS_33_2', + 3: 'BITS_34_3', + 4: 'BITS_35_4', + 5: 'BITS_36_5', + 6: 'BITS_37_6', + 7: 'BITS_38_7', +} +BITS_31_0 = 0 +BITS_32_1 = 1 +BITS_33_2 = 2 +BITS_34_3 = 3 +BITS_35_4 = 4 +BITS_36_5 = 5 +BITS_37_6 = 6 +BITS_38_7 = 7 +DC_DMCUB_TIMER_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'INVALID_REG_ACCESS_TYPE' +INVALID_REG_ACCESS_TYPE__enumvalues = { + 0: 'REG_UNALLOCATED_ADDR_WRITE', + 1: 'REG_UNALLOCATED_ADDR_READ', + 2: 'REG_VIRTUAL_WRITE', + 3: 'REG_VIRTUAL_READ', + 4: 'REG_SECURE_VIOLATE_WRITE', + 5: 'REG_SECURE_VIOLATE_READ', +} +REG_UNALLOCATED_ADDR_WRITE = 0 +REG_UNALLOCATED_ADDR_READ = 1 +REG_VIRTUAL_WRITE = 2 +REG_VIRTUAL_READ = 3 +REG_SECURE_VIOLATE_WRITE = 4 +REG_SECURE_VIOLATE_READ = 5 +INVALID_REG_ACCESS_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_DC_GPU_TIMER_READ_SELECT' +DMU_DC_GPU_TIMER_READ_SELECT__enumvalues = { + 0: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', + 1: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', + 2: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', + 3: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', + 4: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', + 5: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', + 6: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', + 7: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', + 8: 'RESERVED_8', + 9: 'RESERVED_9', + 10: 'RESERVED_10', + 11: 'RESERVED_11', + 12: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', + 13: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', + 14: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', + 15: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', + 16: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', + 17: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', + 18: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', + 19: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', + 20: 'RESERVED_20', + 21: 'RESERVED_21', + 22: 'RESERVED_22', + 23: 'RESERVED_23', + 24: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', + 25: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', + 26: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', + 27: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', + 28: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', + 29: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', + 30: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', + 31: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', + 32: 'RESERVED_32', + 33: 'RESERVED_33', + 34: 'RESERVED_34', + 35: 'RESERVED_35', + 36: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', + 37: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', + 38: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', + 39: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', + 40: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', + 41: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', + 42: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', + 43: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', + 44: 'RESERVED_44', + 45: 'RESERVED_45', + 46: 'RESERVED_46', + 47: 'RESERVED_47', + 48: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', + 49: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', + 50: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', + 51: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', + 52: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', + 53: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', + 54: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', + 55: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', + 56: 'RESERVED_56', + 57: 'RESERVED_57', + 58: 'RESERVED_58', + 59: 'RESERVED_59', + 60: 'RESERVED_60', + 61: 'RESERVED_61', + 62: 'RESERVED_62', + 63: 'RESERVED_63', + 64: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', + 65: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', + 66: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', + 67: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', + 68: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', + 69: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', + 70: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', + 71: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', + 72: 'RESERVED_72', + 73: 'RESERVED_73', + 74: 'RESERVED_74', + 75: 'RESERVED_75', + 76: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', + 77: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', + 78: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', + 79: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', + 80: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', + 81: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', + 82: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', + 83: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', + 84: 'RESERVED_84', + 85: 'RESERVED_85', + 86: 'RESERVED_86', + 87: 'RESERVED_87', + 88: 'RESERVED_88', + 89: 'RESERVED_89', + 90: 'RESERVED_90', + 91: 'RESERVED_91', +} +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 1 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 2 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 3 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 4 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 5 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 6 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 7 +RESERVED_8 = 8 +RESERVED_9 = 9 +RESERVED_10 = 10 +RESERVED_11 = 11 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 12 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 13 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 14 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 15 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 16 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 17 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 18 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 19 +RESERVED_20 = 20 +RESERVED_21 = 21 +RESERVED_22 = 22 +RESERVED_23 = 23 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 24 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 25 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 26 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 27 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 28 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 29 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 30 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 31 +RESERVED_32 = 32 +RESERVED_33 = 33 +RESERVED_34 = 34 +RESERVED_35 = 35 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 36 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 37 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 38 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 39 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 40 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 41 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 42 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 43 +RESERVED_44 = 44 +RESERVED_45 = 45 +RESERVED_46 = 46 +RESERVED_47 = 47 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 48 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 49 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 50 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 51 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 52 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 53 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 54 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 55 +RESERVED_56 = 56 +RESERVED_57 = 57 +RESERVED_58 = 58 +RESERVED_59 = 59 +RESERVED_60 = 60 +RESERVED_61 = 61 +RESERVED_62 = 62 +RESERVED_63 = 63 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 64 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 65 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 66 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 67 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 68 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 69 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 70 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 71 +RESERVED_72 = 72 +RESERVED_73 = 73 +RESERVED_74 = 74 +RESERVED_75 = 75 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 76 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 77 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 78 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 79 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 80 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 81 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 82 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 83 +RESERVED_84 = 84 +RESERVED_85 = 85 +RESERVED_86 = 86 +RESERVED_87 = 87 +RESERVED_88 = 88 +RESERVED_89 = 89 +RESERVED_90 = 90 +RESERVED_91 = 91 +DMU_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_DC_GPU_TIMER_START_POSITION' +DMU_DC_GPU_TIMER_START_POSITION__enumvalues = { + 0: 'DMU_GPU_TIMER_START_0_END_27', + 1: 'DMU_GPU_TIMER_START_1_END_28', + 2: 'DMU_GPU_TIMER_START_2_END_29', + 3: 'DMU_GPU_TIMER_START_3_END_30', + 4: 'DMU_GPU_TIMER_START_4_END_31', + 5: 'DMU_GPU_TIMER_START_6_END_33', + 6: 'DMU_GPU_TIMER_START_8_END_35', + 7: 'DMU_GPU_TIMER_START_10_END_37', +} +DMU_GPU_TIMER_START_0_END_27 = 0 +DMU_GPU_TIMER_START_1_END_28 = 1 +DMU_GPU_TIMER_START_2_END_29 = 2 +DMU_GPU_TIMER_START_3_END_30 = 3 +DMU_GPU_TIMER_START_4_END_31 = 4 +DMU_GPU_TIMER_START_6_END_33 = 5 +DMU_GPU_TIMER_START_8_END_35 = 6 +DMU_GPU_TIMER_START_10_END_37 = 7 +DMU_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'IHC_INTERRUPT_DEST' +IHC_INTERRUPT_DEST__enumvalues = { + 0: 'INTERRUPT_SENT_TO_IH', + 1: 'INTERRUPT_SENT_TO_DMCUB', +} +INTERRUPT_SENT_TO_IH = 0 +INTERRUPT_SENT_TO_DMCUB = 1 +IHC_INTERRUPT_DEST = ctypes.c_uint32 # enum + +# values for enumeration 'IHC_INTERRUPT_LINE_STATUS' +IHC_INTERRUPT_LINE_STATUS__enumvalues = { + 0: 'INTERRUPT_LINE_NOT_ASSERTED', + 1: 'INTERRUPT_LINE_ASSERTED', +} +INTERRUPT_LINE_NOT_ASSERTED = 0 +INTERRUPT_LINE_ASSERTED = 1 +IHC_INTERRUPT_LINE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DC_SMU_INTERRUPT_ENABLE' +DC_SMU_INTERRUPT_ENABLE__enumvalues = { + 0: 'DISABLE_THE_INTERRUPT', + 1: 'ENABLE_THE_INTERRUPT', +} +DISABLE_THE_INTERRUPT = 0 +ENABLE_THE_INTERRUPT = 1 +DC_SMU_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_CLOCK_ON' +DMU_CLOCK_ON__enumvalues = { + 0: 'DMU_CLOCK_STATUS_ON', + 1: 'DMU_CLOCK_STATUS_OFF', +} +DMU_CLOCK_STATUS_ON = 0 +DMU_CLOCK_STATUS_OFF = 1 +DMU_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'SMU_INTR' +SMU_INTR__enumvalues = { + 0: 'SMU_MSG_INTR_NOOP', + 1: 'SET_SMU_MSG_INTR', +} +SMU_MSG_INTR_NOOP = 0 +SET_SMU_MSG_INTR = 1 +SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'ALLOW_SR_ON_TRANS_REQ' +ALLOW_SR_ON_TRANS_REQ__enumvalues = { + 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', + 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', +} +ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 +ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 +ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'AMCLOCK_ENABLE' +AMCLOCK_ENABLE__enumvalues = { + 0: 'ENABLE_AMCLK0', + 1: 'ENABLE_AMCLK1', +} +ENABLE_AMCLK0 = 0 +ENABLE_AMCLK1 = 1 +AMCLOCK_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CLEAR_SMU_INTR' +CLEAR_SMU_INTR__enumvalues = { + 0: 'SMU_INTR_STATUS_NOOP', + 1: 'SMU_INTR_STATUS_CLEAR', +} +SMU_INTR_STATUS_NOOP = 0 +SMU_INTR_STATUS_CLEAR = 1 +CLEAR_SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_BRANCH_SOFT_RESET' +CLOCK_BRANCH_SOFT_RESET__enumvalues = { + 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', + 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', +} +CLOCK_BRANCH_SOFT_RESET_NOOP = 0 +CLOCK_BRANCH_SOFT_RESET_FORCE = 1 +CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' +DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', + 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', + 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', + 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', + 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', +} +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 1 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 2 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 3 +DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 4 +DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' +DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', +} +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 1 +DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_SEL' +DCCG_AUDIO_DTO_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', + 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', +} +DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 +DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 +DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 +DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' +DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { + 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', +} +DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 +DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 +DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DBG_BLOCK_SEL' +DCCG_DBG_BLOCK_SEL__enumvalues = { + 0: 'DCCG_DBG_BLOCK_SEL_DCCG', + 1: 'DCCG_DBG_BLOCK_SEL_PMON', + 2: 'DCCG_DBG_BLOCK_SEL_PMON2', +} +DCCG_DBG_BLOCK_SEL_DCCG = 0 +DCCG_DBG_BLOCK_SEL_PMON = 1 +DCCG_DBG_BLOCK_SEL_PMON2 = 2 +DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DBG_EN' +DCCG_DBG_EN__enumvalues = { + 0: 'DCCG_DBG_EN_DISABLE', + 1: 'DCCG_DBG_EN_ENABLE', +} +DCCG_DBG_EN_DISABLE = 0 +DCCG_DBG_EN_ENABLE = 1 +DCCG_DBG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DEEP_COLOR_CNTL' +DCCG_DEEP_COLOR_CNTL__enumvalues = { + 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', + 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', + 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', +} +DCCG_DEEP_COLOR_DTO_DISABLE = 0 +DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 +DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 +DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 +DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' +DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', + 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', +} +DCCG_FIFO_ERRDET_OVR_DISABLE = 0 +DCCG_FIFO_ERRDET_OVR_ENABLE = 1 +DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_RESET' +DCCG_FIFO_ERRDET_RESET__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', + 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', +} +DCCG_FIFO_ERRDET_RESET_NOOP = 0 +DCCG_FIFO_ERRDET_RESET_FORCE = 1 +DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_STATE' +DCCG_FIFO_ERRDET_STATE__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', + 1: 'DCCG_FIFO_ERRDET_STATE_DETECTION', +} +DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0 +DCCG_FIFO_ERRDET_STATE_DETECTION = 1 +DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_HSYNC' +DCCG_PERF_MODE_HSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_HSYNC_NOOP', + 1: 'DCCG_PERF_MODE_HSYNC_START', +} +DCCG_PERF_MODE_HSYNC_NOOP = 0 +DCCG_PERF_MODE_HSYNC_START = 1 +DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_VSYNC' +DCCG_PERF_MODE_VSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_VSYNC_NOOP', + 1: 'DCCG_PERF_MODE_VSYNC_START', +} +DCCG_PERF_MODE_VSYNC_NOOP = 0 +DCCG_PERF_MODE_VSYNC_START = 1 +DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_OTG_SELECT' +DCCG_PERF_OTG_SELECT__enumvalues = { + 0: 'DCCG_PERF_SEL_OTG0', + 1: 'DCCG_PERF_SEL_OTG1', + 2: 'DCCG_PERF_SEL_OTG2', + 3: 'DCCG_PERF_SEL_OTG3', + 4: 'DCCG_PERF_SEL_RESERVED', +} +DCCG_PERF_SEL_OTG0 = 0 +DCCG_PERF_SEL_OTG1 = 1 +DCCG_PERF_SEL_OTG2 = 2 +DCCG_PERF_SEL_OTG3 = 3 +DCCG_PERF_SEL_RESERVED = 4 +DCCG_PERF_OTG_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_RUN' +DCCG_PERF_RUN__enumvalues = { + 0: 'DCCG_PERF_RUN_NOOP', + 1: 'DCCG_PERF_RUN_START', +} +DCCG_PERF_RUN_NOOP = 0 +DCCG_PERF_RUN_START = 1 +DCCG_PERF_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' +DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { + 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', +} +DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 +DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 +DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_FIFO_ERROR' +DIO_FIFO_ERROR__enumvalues = { + 0: 'DIO_FIFO_ERROR_00', + 1: 'DIO_FIFO_ERROR_01', + 2: 'DIO_FIFO_ERROR_10', + 3: 'DIO_FIFO_ERROR_11', +} +DIO_FIFO_ERROR_00 = 0 +DIO_FIFO_ERROR_01 = 1 +DIO_FIFO_ERROR_10 = 2 +DIO_FIFO_ERROR_11 = 3 +DIO_FIFO_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING' +DISABLE_CLOCK_GATING__enumvalues = { + 0: 'CLOCK_GATING_ENABLED', + 1: 'CLOCK_GATING_DISABLED', +} +CLOCK_GATING_ENABLED = 0 +CLOCK_GATING_DISABLED = 1 +DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' +DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { + 0: 'CLOCK_GATING_ENABLED_IN_DCO', + 1: 'CLOCK_GATING_DISABLED_IN_DCO', +} +CLOCK_GATING_ENABLED_IN_DCO = 0 +CLOCK_GATING_DISABLED_IN_DCO = 1 +DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' +DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { + 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', +} +DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 +DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 +DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_FREQ_RAMP_DONE' +DISPCLK_FREQ_RAMP_DONE__enumvalues = { + 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', + 1: 'DISPCLK_FREQ_RAMP_COMPLETED', +} +DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 +DISPCLK_FREQ_RAMP_COMPLETED = 1 +DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DPREFCLK_SRC_SEL' +DPREFCLK_SRC_SEL__enumvalues = { + 0: 'DPREFCLK_SRC_SEL_CK', + 1: 'DPREFCLK_SRC_SEL_P0PLL', + 2: 'DPREFCLK_SRC_SEL_P1PLL', + 3: 'DPREFCLK_SRC_SEL_P2PLL', +} +DPREFCLK_SRC_SEL_CK = 0 +DPREFCLK_SRC_SEL_P0PLL = 1 +DPREFCLK_SRC_SEL_P1PLL = 2 +DPREFCLK_SRC_SEL_P2PLL = 3 +DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DTO_DS_DISABLE' +DP_DTO_DS_DISABLE__enumvalues = { + 0: 'DP_DTO_DESPREAD_DISABLE', + 1: 'DP_DTO_DESPREAD_ENABLE', +} +DP_DTO_DESPREAD_DISABLE = 0 +DP_DTO_DESPREAD_ENABLE = 1 +DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DS_HW_CAL_ENABLE' +DS_HW_CAL_ENABLE__enumvalues = { + 0: 'DS_HW_CAL_DIS', + 1: 'DS_HW_CAL_EN', +} +DS_HW_CAL_DIS = 0 +DS_HW_CAL_EN = 1 +DS_HW_CAL_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DS_REF_SRC' +DS_REF_SRC__enumvalues = { + 0: 'DS_REF_IS_XTALIN', + 1: 'DS_REF_IS_EXT_GENLOCK', + 2: 'DS_REF_IS_PCIE', +} +DS_REF_IS_XTALIN = 0 +DS_REF_IS_EXT_GENLOCK = 1 +DS_REF_IS_PCIE = 2 +DS_REF_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DVO_ENABLE_RST' +DVO_ENABLE_RST__enumvalues = { + 0: 'DVO_ENABLE_RST_DISABLE', + 1: 'DVO_ENABLE_RST_ENABLE', +} +DVO_ENABLE_RST_DISABLE = 0 +DVO_ENABLE_RST_ENABLE = 1 +DVO_ENABLE_RST = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE' +ENABLE__enumvalues = { + 0: 'DISABLE_THE_FEATURE', + 1: 'ENABLE_THE_FEATURE', +} +DISABLE_THE_FEATURE = 0 +ENABLE_THE_FEATURE = 1 +ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE_CLOCK' +ENABLE_CLOCK__enumvalues = { + 0: 'ENABLE_THE_REFCLK', + 1: 'ENABLE_THE_FUNC_CLOCK', +} +ENABLE_THE_REFCLK = 0 +ENABLE_THE_FUNC_CLOCK = 1 +ENABLE_CLOCK = ctypes.c_uint32 # enum + +# values for enumeration 'FORCE_DISABLE_CLOCK' +FORCE_DISABLE_CLOCK__enumvalues = { + 0: 'NOT_FORCE_THE_CLOCK_DISABLED', + 1: 'FORCE_THE_CLOCK_DISABLED', +} +NOT_FORCE_THE_CLOCK_DISABLED = 0 +FORCE_THE_CLOCK_DISABLED = 1 +FORCE_DISABLE_CLOCK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMICHARCLK_SRC_SEL' +HDMICHARCLK_SRC_SEL__enumvalues = { + 0: 'HDMICHARCLK_SRC_SEL_UNIPHYA', + 1: 'HDMICHARCLK_SRC_SEL_UNIPHYB', + 2: 'HDMICHARCLK_SRC_SEL_UNIPHYC', + 3: 'HDMICHARCLK_SRC_SEL_UNIPHYD', + 4: 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', +} +HDMICHARCLK_SRC_SEL_UNIPHYA = 0 +HDMICHARCLK_SRC_SEL_UNIPHYB = 1 +HDMICHARCLK_SRC_SEL_UNIPHYC = 2 +HDMICHARCLK_SRC_SEL_UNIPHYD = 3 +HDMICHARCLK_SRC_SEL_SRC_RESERVED = 4 +HDMICHARCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMISTREAMCLK_SRC_SEL' +HDMISTREAMCLK_SRC_SEL__enumvalues = { + 0: 'SEL_DTBCLK_P0', + 1: 'SEL_DTBCLK_P1', + 2: 'SEL_DTBCLK_P2', + 3: 'SEL_DTBCLK_P3', +} +SEL_DTBCLK_P0 = 0 +SEL_DTBCLK_P1 = 1 +SEL_DTBCLK_P2 = 2 +SEL_DTBCLK_P3 = 3 +HDMISTREAMCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'JITTER_REMOVE_DISABLE' +JITTER_REMOVE_DISABLE__enumvalues = { + 0: 'ENABLE_JITTER_REMOVAL', + 1: 'DISABLE_JITTER_REMOVAL', +} +ENABLE_JITTER_REMOVAL = 0 +DISABLE_JITTER_REMOVAL = 1 +JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', +} +MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', +} +MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_ADD_PIXEL' +OTG_ADD_PIXEL__enumvalues = { + 0: 'OTG_ADD_PIXEL_NOOP', + 1: 'OTG_ADD_PIXEL_FORCE', +} +OTG_ADD_PIXEL_NOOP = 0 +OTG_ADD_PIXEL_FORCE = 1 +OTG_ADD_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DROP_PIXEL' +OTG_DROP_PIXEL__enumvalues = { + 0: 'OTG_DROP_PIXEL_NOOP', + 1: 'OTG_DROP_PIXEL_FORCE', +} +OTG_DROP_PIXEL_NOOP = 0 +OTG_DROP_PIXEL_FORCE = 1 +OTG_DROP_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'PHYSYMCLK_FORCE_EN' +PHYSYMCLK_FORCE_EN__enumvalues = { + 0: 'PHYSYMCLK_FORCE_EN_DISABLE', + 1: 'PHYSYMCLK_FORCE_EN_ENABLE', +} +PHYSYMCLK_FORCE_EN_DISABLE = 0 +PHYSYMCLK_FORCE_EN_ENABLE = 1 +PHYSYMCLK_FORCE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PHYSYMCLK_FORCE_SRC_SEL' +PHYSYMCLK_FORCE_SRC_SEL__enumvalues = { + 0: 'PHYSYMCLK_FORCE_SRC_SYMCLK', + 1: 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', + 2: 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', +} +PHYSYMCLK_FORCE_SRC_SYMCLK = 0 +PHYSYMCLK_FORCE_SRC_PHYD18CLK = 1 +PHYSYMCLK_FORCE_SRC_PHYD32CLK = 2 +PHYSYMCLK_FORCE_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' +PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', +} +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 4 +PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' +PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', + 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', +} +PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 +PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 +PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_SOURCE' +PIPE_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', + 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', +} +PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 +PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 +PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 +PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PLL_CFG_IF_SOFT_RESET' +PLL_CFG_IF_SOFT_RESET__enumvalues = { + 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', + 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', +} +PLL_CFG_IF_SOFT_RESET_NOOP = 0 +PLL_CFG_IF_SOFT_RESET_FORCE = 1 +PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_SRC' +SYMCLK_FE_SRC__enumvalues = { + 0: 'SYMCLK_FE_SRC_UNIPHYA', + 1: 'SYMCLK_FE_SRC_UNIPHYB', + 2: 'SYMCLK_FE_SRC_UNIPHYC', + 3: 'SYMCLK_FE_SRC_UNIPHYD', + 4: 'SYMCLK_FE_SRC_RESERVED', +} +SYMCLK_FE_SRC_UNIPHYA = 0 +SYMCLK_FE_SRC_UNIPHYB = 1 +SYMCLK_FE_SRC_UNIPHYC = 2 +SYMCLK_FE_SRC_UNIPHYD = 3 +SYMCLK_FE_SRC_RESERVED = 4 +SYMCLK_FE_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLK_DIV_SEL' +TEST_CLK_DIV_SEL__enumvalues = { + 0: 'NO_DIV', + 1: 'DIV_2', + 2: 'DIV_4', + 3: 'DIV_8', +} +NO_DIV = 0 +DIV_2 = 1 +DIV_4 = 2 +DIV_8 = 3 +TEST_CLK_DIV_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VSYNC_CNT_LATCH_MASK' +VSYNC_CNT_LATCH_MASK__enumvalues = { + 0: 'VSYNC_CNT_LATCH_MASK_0', + 1: 'VSYNC_CNT_LATCH_MASK_1', +} +VSYNC_CNT_LATCH_MASK_0 = 0 +VSYNC_CNT_LATCH_MASK_1 = 1 +VSYNC_CNT_LATCH_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'VSYNC_CNT_RESET_SEL' +VSYNC_CNT_RESET_SEL__enumvalues = { + 0: 'VSYNC_CNT_RESET_SEL_0', + 1: 'VSYNC_CNT_RESET_SEL_1', +} +VSYNC_CNT_RESET_SEL_0 = 0 +VSYNC_CNT_RESET_SEL_1 = 1 +VSYNC_CNT_RESET_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' +XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', + 1: 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', +} +XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 +XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 1 +XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_SEL' +XTAL_REF_SEL__enumvalues = { + 0: 'XTAL_REF_SEL_1X', + 1: 'XTAL_REF_SEL_2X', +} +XTAL_REF_SEL_1X = 0 +XTAL_REF_SEL_2X = 1 +XTAL_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_CUR_DISP' +DPHY_8B10B_CUR_DISP__enumvalues = { + 0: 'DPHY_8B10B_CUR_DISP_ZERO', + 1: 'DPHY_8B10B_CUR_DISP_ONE', +} +DPHY_8B10B_CUR_DISP_ZERO = 0 +DPHY_8B10B_CUR_DISP_ONE = 1 +DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_RESET' +DPHY_8B10B_RESET__enumvalues = { + 0: 'DPHY_8B10B_NOT_RESET', + 1: 'DPHY_8B10B_RESETET', +} +DPHY_8B10B_NOT_RESET = 0 +DPHY_8B10B_RESETET = 1 +DPHY_8B10B_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE0' +DPHY_ATEST_SEL_LANE0__enumvalues = { + 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE0_REG_PATTERN', +} +DPHY_ATEST_LANE0_PRBS_PATTERN = 0 +DPHY_ATEST_LANE0_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE1' +DPHY_ATEST_SEL_LANE1__enumvalues = { + 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE1_REG_PATTERN', +} +DPHY_ATEST_LANE1_PRBS_PATTERN = 0 +DPHY_ATEST_LANE1_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE2' +DPHY_ATEST_SEL_LANE2__enumvalues = { + 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE2_REG_PATTERN', +} +DPHY_ATEST_LANE2_PRBS_PATTERN = 0 +DPHY_ATEST_LANE2_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE3' +DPHY_ATEST_SEL_LANE3__enumvalues = { + 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE3_REG_PATTERN', +} +DPHY_ATEST_LANE3_PRBS_PATTERN = 0 +DPHY_ATEST_LANE3_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_BYPASS' +DPHY_BYPASS__enumvalues = { + 0: 'DPHY_8B10B_OUTPUT', + 1: 'DPHY_DBG_OUTPUT', +} +DPHY_8B10B_OUTPUT = 0 +DPHY_DBG_OUTPUT = 1 +DPHY_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_CONT_EN' +DPHY_CRC_CONT_EN__enumvalues = { + 0: 'DPHY_CRC_ONE_SHOT', + 1: 'DPHY_CRC_CONTINUOUS', +} +DPHY_CRC_ONE_SHOT = 0 +DPHY_CRC_CONTINUOUS = 1 +DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_EN' +DPHY_CRC_EN__enumvalues = { + 0: 'DPHY_CRC_DISABLED', + 1: 'DPHY_CRC_ENABLED', +} +DPHY_CRC_DISABLED = 0 +DPHY_CRC_ENABLED = 1 +DPHY_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_FIELD' +DPHY_CRC_FIELD__enumvalues = { + 0: 'DPHY_CRC_START_FROM_TOP_FIELD', + 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', +} +DPHY_CRC_START_FROM_TOP_FIELD = 0 +DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 +DPHY_CRC_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' +DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { + 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', + 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', +} +DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 +DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 +DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_SEL' +DPHY_CRC_SEL__enumvalues = { + 0: 'DPHY_CRC_LANE0_SELECTED', + 1: 'DPHY_CRC_LANE1_SELECTED', + 2: 'DPHY_CRC_LANE2_SELECTED', + 3: 'DPHY_CRC_LANE3_SELECTED', +} +DPHY_CRC_LANE0_SELECTED = 0 +DPHY_CRC_LANE1_SELECTED = 1 +DPHY_CRC_LANE2_SELECTED = 2 +DPHY_CRC_LANE3_SELECTED = 3 +DPHY_CRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_FEC_ENABLE' +DPHY_FEC_ENABLE__enumvalues = { + 0: 'DPHY_FEC_DISABLED', + 1: 'DPHY_FEC_ENABLED', +} +DPHY_FEC_DISABLED = 0 +DPHY_FEC_ENABLED = 1 +DPHY_FEC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_FEC_READY' +DPHY_FEC_READY__enumvalues = { + 0: 'DPHY_FEC_READY_EN', + 1: 'DPHY_FEC_READY_DIS', +} +DPHY_FEC_READY_EN = 0 +DPHY_FEC_READY_DIS = 1 +DPHY_FEC_READY = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_LOAD_BS_COUNT_START' +DPHY_LOAD_BS_COUNT_START__enumvalues = { + 0: 'DPHY_LOAD_BS_COUNT_STARTED', + 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', +} +DPHY_LOAD_BS_COUNT_STARTED = 0 +DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 +DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_EN' +DPHY_PRBS_EN__enumvalues = { + 0: 'DPHY_PRBS_DISABLE', + 1: 'DPHY_PRBS_ENABLE', +} +DPHY_PRBS_DISABLE = 0 +DPHY_PRBS_ENABLE = 1 +DPHY_PRBS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_SEL' +DPHY_PRBS_SEL__enumvalues = { + 0: 'DPHY_PRBS7_SELECTED', + 1: 'DPHY_PRBS23_SELECTED', + 2: 'DPHY_PRBS11_SELECTED', +} +DPHY_PRBS7_SELECTED = 0 +DPHY_PRBS23_SELECTED = 1 +DPHY_PRBS11_SELECTED = 2 +DPHY_PRBS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' +DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { + 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 1: 'DPHY_FAST_TRAINING_CAPABLE', +} +DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 +DPHY_FAST_TRAINING_CAPABLE = 1 +DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SKEW_BYPASS' +DPHY_SKEW_BYPASS__enumvalues = { + 0: 'DPHY_WITH_SKEW', + 1: 'DPHY_NO_SKEW', +} +DPHY_WITH_SKEW = 0 +DPHY_NO_SKEW = 1 +DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM' +DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM__enumvalues = { + 0: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', + 1: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', +} +DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0 +DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 1 +DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SW_FAST_TRAINING_START' +DPHY_SW_FAST_TRAINING_START__enumvalues = { + 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 1: 'DPHY_SW_FAST_TRAINING_STARTED', +} +DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 +DPHY_SW_FAST_TRAINING_STARTED = 1 +DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_TRAINING_PATTERN_SEL' +DPHY_TRAINING_PATTERN_SEL__enumvalues = { + 0: 'DPHY_TRAINING_PATTERN_1', + 1: 'DPHY_TRAINING_PATTERN_2', + 2: 'DPHY_TRAINING_PATTERN_3', + 3: 'DPHY_TRAINING_PATTERN_4', +} +DPHY_TRAINING_PATTERN_1 = 0 +DPHY_TRAINING_PATTERN_2 = 1 +DPHY_TRAINING_PATTERN_3 = 2 +DPHY_TRAINING_PATTERN_4 = 3 +DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_COMPONENT_DEPTH' +DP_COMPONENT_DEPTH__enumvalues = { + 0: 'DP_COMPONENT_DEPTH_6BPC', + 1: 'DP_COMPONENT_DEPTH_8BPC', + 2: 'DP_COMPONENT_DEPTH_10BPC', + 3: 'DP_COMPONENT_DEPTH_12BPC', + 4: 'DP_COMPONENT_DEPTH_16BPC', +} +DP_COMPONENT_DEPTH_6BPC = 0 +DP_COMPONENT_DEPTH_8BPC = 1 +DP_COMPONENT_DEPTH_10BPC = 2 +DP_COMPONENT_DEPTH_12BPC = 3 +DP_COMPONENT_DEPTH_16BPC = 4 +DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'DP_COMPRESSED_PIXEL_FORMAT' +DP_COMPRESSED_PIXEL_FORMAT__enumvalues = { + 0: 'DP_DSC_444_S422', + 1: 'DP_DSC_N422_N420', +} +DP_DSC_444_S422 = 0 +DP_DSC_N422_N420 = 1 +DP_COMPRESSED_PIXEL_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_8B10B_EXT_DISP' +DP_DPHY_8B10B_EXT_DISP__enumvalues = { + 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', +} +DP_DPHY_8B10B_EXT_DISP_ZERO = 0 +DP_DPHY_8B10B_EXT_DISP_ONE = 1 +DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' +DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' +DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', +} +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' +DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { + 0: 'DP_DPHY_HBR2_PASS_THROUGH', + 1: 'DP_DPHY_HBR2_PATTERN_1', + 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', + 3: 'DP_DPHY_HBR2_PATTERN_3', + 6: 'DP_DPHY_HBR2_PATTERN_2_POS', +} +DP_DPHY_HBR2_PASS_THROUGH = 0 +DP_DPHY_HBR2_PATTERN_1 = 1 +DP_DPHY_HBR2_PATTERN_2_NEG = 2 +DP_DPHY_HBR2_PATTERN_3 = 3 +DP_DPHY_HBR2_PATTERN_2_POS = 6 +DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_LINK_TRAINING_COMPLETE' +DP_LINK_TRAINING_COMPLETE__enumvalues = { + 0: 'DP_LINK_TRAINING_NOT_COMPLETE', + 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', +} +DP_LINK_TRAINING_NOT_COMPLETE = 0 +DP_LINK_TRAINING_ALREADY_COMPLETE = 1 +DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_LINK_TRAINING_SWITCH_MODE' +DP_LINK_TRAINING_SWITCH_MODE__enumvalues = { + 0: 'DP_LINK_TRAINING_SWITCH_TO_IDLE', + 1: 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', +} +DP_LINK_TRAINING_SWITCH_TO_IDLE = 0 +DP_LINK_TRAINING_SWITCH_TO_VIDEO = 1 +DP_LINK_TRAINING_SWITCH_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_ML_PHY_SEQ_MODE' +DP_ML_PHY_SEQ_MODE__enumvalues = { + 0: 'DP_ML_PHY_SEQ_LINE_NUM', + 1: 'DP_ML_PHY_SEQ_IMMEDIATE', +} +DP_ML_PHY_SEQ_LINE_NUM = 0 +DP_ML_PHY_SEQ_IMMEDIATE = 1 +DP_ML_PHY_SEQ_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' +DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { + 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', + 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', +} +MSA_V_TIMING_OVERRIDE_DISABLED = 0 +MSA_V_TIMING_OVERRIDE_ENABLED = 1 +DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_BLANK_CODE' +DP_MSE_BLANK_CODE__enumvalues = { + 0: 'DP_MSE_BLANK_CODE_SF_FILLED', + 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', +} +DP_MSE_BLANK_CODE_SF_FILLED = 0 +DP_MSE_BLANK_CODE_ZERO_FILLED = 1 +DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_LINK_LINE' +DP_MSE_LINK_LINE__enumvalues = { + 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', + 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', + 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', + 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', +} +DP_MSE_LINK_LINE_32_MTP_LONG = 0 +DP_MSE_LINK_LINE_64_MTP_LONG = 1 +DP_MSE_LINK_LINE_128_MTP_LONG = 2 +DP_MSE_LINK_LINE_256_MTP_LONG = 3 +DP_MSE_LINK_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_TIMESTAMP_MODE' +DP_MSE_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', +} +DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 +DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 +DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_ZERO_ENCODER' +DP_MSE_ZERO_ENCODER__enumvalues = { + 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', + 1: 'DP_MSE_ZERO_FE_ENCODER', +} +DP_MSE_NOT_ZERO_FE_ENCODER = 0 +DP_MSE_ZERO_FE_ENCODER = 1 +DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSO_NUM_OF_SST_LINKS' +DP_MSO_NUM_OF_SST_LINKS__enumvalues = { + 0: 'DP_MSO_ONE_SSTLINK', + 1: 'DP_MSO_TWO_SSTLINK', + 2: 'DP_MSO_FOUR_SSTLINK', +} +DP_MSO_ONE_SSTLINK = 0 +DP_MSO_TWO_SSTLINK = 1 +DP_MSO_FOUR_SSTLINK = 2 +DP_MSO_NUM_OF_SST_LINKS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_PIXEL_ENCODING' +DP_PIXEL_ENCODING__enumvalues = { + 0: 'DP_PIXEL_ENCODING_RGB_YCBCR444', + 1: 'DP_PIXEL_ENCODING_YCBCR422', + 2: 'DP_PIXEL_ENCODING_YCBCR420', + 3: 'DP_PIXEL_ENCODING_Y_ONLY', +} +DP_PIXEL_ENCODING_RGB_YCBCR444 = 0 +DP_PIXEL_ENCODING_YCBCR422 = 1 +DP_PIXEL_ENCODING_YCBCR420 = 2 +DP_PIXEL_ENCODING_Y_ONLY = 3 +DP_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'DP_PIXEL_ENCODING_TYPE' +DP_PIXEL_ENCODING_TYPE__enumvalues = { + 0: 'DP_PIXEL_ENCODING_UNCOMPRESSED', + 1: 'DP_PIXEL_ENCODING_COMPRESSED', +} +DP_PIXEL_ENCODING_UNCOMPRESSED = 0 +DP_PIXEL_ENCODING_COMPRESSED = 1 +DP_PIXEL_ENCODING_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { + 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', +} +DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_PRIORITY' +DP_SEC_ASP_PRIORITY__enumvalues = { + 0: 'DP_SEC_ASP_LOW_PRIORITY', + 1: 'DP_SEC_ASP_HIGH_PRIORITY', +} +DP_SEC_ASP_LOW_PRIORITY = 0 +DP_SEC_ASP_HIGH_PRIORITY = 1 +DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_AUDIO_MUTE' +DP_SEC_AUDIO_MUTE__enumvalues = { + 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', + 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', +} +DP_SEC_AUDIO_MUTE_HW_CTRL = 0 +DP_SEC_AUDIO_MUTE_SW_CTRL = 1 +DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_COLLISION_ACK' +DP_SEC_COLLISION_ACK__enumvalues = { + 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', + 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', +} +DP_SEC_COLLISION_ACK_NO_EFFECT = 0 +DP_SEC_COLLISION_ACK_CLR_FLAG = 1 +DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP0_PRIORITY' +DP_SEC_GSP0_PRIORITY__enumvalues = { + 0: 'SEC_GSP0_PRIORITY_LOW', + 1: 'SEC_GSP0_PRIORITY_HIGH', +} +SEC_GSP0_PRIORITY_LOW = 0 +SEC_GSP0_PRIORITY_HIGH = 1 +DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND' +DP_SEC_GSP_SEND__enumvalues = { + 0: 'NOT_SENT', + 1: 'FORCE_SENT', +} +NOT_SENT = 0 +FORCE_SENT = 1 +DP_SEC_GSP_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND_ANY_LINE' +DP_SEC_GSP_SEND_ANY_LINE__enumvalues = { + 0: 'SEND_AT_LINK_NUMBER', + 1: 'SEND_AT_EARLIEST_TIME', +} +SEND_AT_LINK_NUMBER = 0 +SEND_AT_EARLIEST_TIME = 1 +DP_SEC_GSP_SEND_ANY_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND_PPS' +DP_SEC_GSP_SEND_PPS__enumvalues = { + 0: 'SEND_NORMAL_PACKET', + 1: 'SEND_PPS_PACKET', +} +SEND_NORMAL_PACKET = 0 +SEND_PPS_PACKET = 1 +DP_SEC_GSP_SEND_PPS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_LINE_REFERENCE' +DP_SEC_LINE_REFERENCE__enumvalues = { + 0: 'REFER_TO_DP_SOF', + 1: 'REFER_TO_OTG_SOF', +} +REFER_TO_DP_SOF = 0 +REFER_TO_OTG_SOF = 1 +DP_SEC_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_TIMESTAMP_MODE' +DP_SEC_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', + 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', +} +DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 +DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 +DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OUTPUT_PIXEL_PER_CYCLE' +DP_STEER_OUTPUT_PIXEL_PER_CYCLE__enumvalues = { + 0: 'DP_STEER_1_PIX_PER_CYCLE', + 1: 'DP_STEER_2_PIX_PER_CYCLE', + 2: 'DP_STEER_4_PIX_PER_CYCLE', + 3: 'DP_STEER_8_PIX_PER_CYCLE', +} +DP_STEER_1_PIX_PER_CYCLE = 0 +DP_STEER_2_PIX_PER_CYCLE = 1 +DP_STEER_4_PIX_PER_CYCLE = 2 +DP_STEER_8_PIX_PER_CYCLE = 3 +DP_STEER_OUTPUT_PIXEL_PER_CYCLE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_ACK' +DP_STEER_OVERFLOW_ACK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 +DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_MASK' +DP_STEER_OVERFLOW_MASK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_MASKED', + 1: 'DP_STEER_OVERFLOW_UNMASK', +} +DP_STEER_OVERFLOW_MASKED = 0 +DP_STEER_OVERFLOW_UNMASK = 1 +DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SYNC_POLARITY' +DP_SYNC_POLARITY__enumvalues = { + 0: 'DP_SYNC_POLARITY_ACTIVE_HIGH', + 1: 'DP_SYNC_POLARITY_ACTIVE_LOW', +} +DP_SYNC_POLARITY_ACTIVE_HIGH = 0 +DP_SYNC_POLARITY_ACTIVE_LOW = 1 +DP_SYNC_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_TU_OVERFLOW_ACK' +DP_TU_OVERFLOW_ACK__enumvalues = { + 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 +DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_UDI_LANES' +DP_UDI_LANES__enumvalues = { + 0: 'DP_UDI_1_LANE', + 1: 'DP_UDI_2_LANES', + 2: 'DP_UDI_LANES_RESERVED', + 3: 'DP_UDI_4_LANES', +} +DP_UDI_1_LANE = 0 +DP_UDI_2_LANES = 1 +DP_UDI_LANES_RESERVED = 2 +DP_UDI_4_LANES = 3 +DP_UDI_LANES = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' +DP_VID_ENHANCED_FRAME_MODE__enumvalues = { + 0: 'VID_NORMAL_FRAME_MODE', + 1: 'VID_ENHANCED_MODE', +} +VID_NORMAL_FRAME_MODE = 0 +VID_ENHANCED_MODE = 1 +DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' +DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { + 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', +} +DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 +DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 +DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_GEN_EN' +DP_VID_M_N_GEN_EN__enumvalues = { + 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', + 1: 'DP_VID_M_N_CALC_AUTO', +} +DP_VID_M_N_PROGRAMMED_VIA_REG = 0 +DP_VID_M_N_CALC_AUTO = 1 +DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_N_INTERVAL' +DP_VID_N_INTERVAL__enumvalues = { + 0: 'DP_VID_1X_Nvid', + 1: 'DP_VID_2X_Nvid', + 2: 'DP_VID_4X_Nvid', + 3: 'DP_VID_8X_Nvid', +} +DP_VID_1X_Nvid = 0 +DP_VID_2X_Nvid = 1 +DP_VID_4X_Nvid = 2 +DP_VID_8X_Nvid = 3 +DP_VID_N_INTERVAL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_ACK' +DP_VID_STREAM_DISABLE_ACK__enumvalues = { + 0: 'ID_STREAM_DISABLE_NO_ACK', + 1: 'ID_STREAM_DISABLE_ACKED', +} +ID_STREAM_DISABLE_NO_ACK = 0 +ID_STREAM_DISABLE_ACKED = 1 +DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_MASK' +DP_VID_STREAM_DISABLE_MASK__enumvalues = { + 0: 'VID_STREAM_DISABLE_MASKED', + 1: 'VID_STREAM_DISABLE_UNMASK', +} +VID_STREAM_DISABLE_MASKED = 0 +VID_STREAM_DISABLE_UNMASK = 1 +DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DIS_DEFER' +DP_VID_STREAM_DIS_DEFER__enumvalues = { + 0: 'DP_VID_STREAM_DIS_NO_DEFER', + 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', +} +DP_VID_STREAM_DIS_NO_DEFER = 0 +DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 +DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 +DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_VBID_FIELD_POL' +DP_VID_VBID_FIELD_POL__enumvalues = { + 0: 'DP_VID_VBID_FIELD_POL_NORMAL', + 1: 'DP_VID_VBID_FIELD_POL_INV', +} +DP_VID_VBID_FIELD_POL_NORMAL = 0 +DP_VID_VBID_FIELD_POL_INV = 1 +DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum + +# values for enumeration 'FEC_ACTIVE_STATUS' +FEC_ACTIVE_STATUS__enumvalues = { + 0: 'DPHY_FEC_NOT_ACTIVE', + 1: 'DPHY_FEC_ACTIVE', +} +DPHY_FEC_NOT_ACTIVE = 0 +DPHY_FEC_ACTIVE = 1 +FEC_ACTIVE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_HPD_SELECT' +DIG_BE_CNTL_HPD_SELECT__enumvalues = { + 0: 'DIG_BE_CNTL_HPD1', + 1: 'DIG_BE_CNTL_HPD2', + 2: 'DIG_BE_CNTL_HPD3', + 3: 'DIG_BE_CNTL_HPD4', + 4: 'DIG_BE_CNTL_NO_HPD', +} +DIG_BE_CNTL_HPD1 = 0 +DIG_BE_CNTL_HPD2 = 1 +DIG_BE_CNTL_HPD3 = 2 +DIG_BE_CNTL_HPD4 = 3 +DIG_BE_CNTL_NO_HPD = 4 +DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_MODE' +DIG_BE_CNTL_MODE__enumvalues = { + 0: 'DIG_BE_DP_SST_MODE', + 1: 'DIG_BE_RESERVED1', + 2: 'DIG_BE_TMDS_DVI_MODE', + 3: 'DIG_BE_TMDS_HDMI_MODE', + 4: 'DIG_BE_RESERVED4', + 5: 'DIG_BE_DP_MST_MODE', + 6: 'DIG_BE_RESERVED2', + 7: 'DIG_BE_RESERVED3', +} +DIG_BE_DP_SST_MODE = 0 +DIG_BE_RESERVED1 = 1 +DIG_BE_TMDS_DVI_MODE = 2 +DIG_BE_TMDS_HDMI_MODE = 3 +DIG_BE_RESERVED4 = 4 +DIG_BE_DP_MST_MODE = 5 +DIG_BE_RESERVED2 = 6 +DIG_BE_RESERVED3 = 7 +DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_DIGITAL_BYPASS_ENABLE' +DIG_DIGITAL_BYPASS_ENABLE__enumvalues = { + 0: 'DIG_DIGITAL_BYPASS_OFF', + 1: 'DIG_DIGITAL_BYPASS_ON', +} +DIG_DIGITAL_BYPASS_OFF = 0 +DIG_DIGITAL_BYPASS_ON = 1 +DIG_DIGITAL_BYPASS_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_DIGITAL_BYPASS_SEL' +DIG_DIGITAL_BYPASS_SEL__enumvalues = { + 0: 'DIG_DIGITAL_BYPASS_SEL_BYPASS', + 1: 'DIG_DIGITAL_BYPASS_SEL_36BPP', + 2: 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', + 3: 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', + 4: 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', + 5: 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', + 6: 'DIG_DIGITAL_BYPASS_SEL_ALPHA', +} +DIG_DIGITAL_BYPASS_SEL_BYPASS = 0 +DIG_DIGITAL_BYPASS_SEL_36BPP = 1 +DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 2 +DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 3 +DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 4 +DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 5 +DIG_DIGITAL_BYPASS_SEL_ALPHA = 6 +DIG_DIGITAL_BYPASS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' +DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { + 0: 'DIG_FE_SOURCE_FROM_OTG0', + 1: 'DIG_FE_SOURCE_FROM_OTG1', + 2: 'DIG_FE_SOURCE_FROM_OTG2', + 3: 'DIG_FE_SOURCE_FROM_OTG3', + 4: 'DIG_FE_SOURCE_RESERVED', +} +DIG_FE_SOURCE_FROM_OTG0 = 0 +DIG_FE_SOURCE_FROM_OTG1 = 1 +DIG_FE_SOURCE_FROM_OTG2 = 2 +DIG_FE_SOURCE_FROM_OTG3 = 3 +DIG_FE_SOURCE_RESERVED = 4 +DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' +DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { + 0: 'DIG_FE_STEREOSYNC_FROM_OTG0', + 1: 'DIG_FE_STEREOSYNC_FROM_OTG1', + 2: 'DIG_FE_STEREOSYNC_FROM_OTG2', + 3: 'DIG_FE_STEREOSYNC_FROM_OTG3', + 4: 'DIG_FE_STEREOSYNC_RESERVED', +} +DIG_FE_STEREOSYNC_FROM_OTG0 = 0 +DIG_FE_STEREOSYNC_FROM_OTG1 = 1 +DIG_FE_STEREOSYNC_FROM_OTG2 = 2 +DIG_FE_STEREOSYNC_FROM_OTG3 = 3 +DIG_FE_STEREOSYNC_RESERVED = 4 +DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX' +DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', + 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', +} +DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 +DIG_FIFO_FORCE_RECOMP_MINMAX = 1 +DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL' +DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL__enumvalues = { + 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', + 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', +} +DIG_FIFO_USE_OVERWRITE_LEVEL = 0 +DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 +DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_FORCE_RECAL_AVERAGE' +DIG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', +} +DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 +DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 +DIG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE' +DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__enumvalues = { + 0: 'DIG_FIFO_1_PIX_PER_CYCLE', + 1: 'DIG_FIFO_2_PIX_PER_CYCLE', + 2: 'DIG_FIFO_4_PIX_PER_CYCLE', + 3: 'DIG_FIFO_8_PIX_PER_CYCLE', +} +DIG_FIFO_1_PIX_PER_CYCLE = 0 +DIG_FIFO_2_PIX_PER_CYCLE = 1 +DIG_FIFO_4_PIX_PER_CYCLE = 2 +DIG_FIFO_8_PIX_PER_CYCLE = 3 +DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR' +DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { + 0: 'DIG_FIFO_NO_ERROR_OCCURRED', + 1: 'DIG_FIFO_UNDERFLOW_OCCURRED', + 2: 'DIG_FIFO_OVERFLOW_OCCURRED', +} +DIG_FIFO_NO_ERROR_OCCURRED = 0 +DIG_FIFO_UNDERFLOW_OCCURRED = 1 +DIG_FIFO_OVERFLOW_OCCURRED = 2 +DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' +DIG_FIFO_READ_CLOCK_SRC__enumvalues = { + 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', +} +DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 +DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 +DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_MODE' +DIG_MODE__enumvalues = { + 0: 'DP_SST_MODE', + 1: 'RESERVED1', + 2: 'TMDS_DVI_MODE', + 3: 'TMDS_HDMI_MODE', + 4: 'RESERVED4', + 5: 'DP_MST_MODE', + 6: 'RESERVED2', + 7: 'RESERVED3', +} +DP_SST_MODE = 0 +RESERVED1 = 1 +TMDS_DVI_MODE = 2 +TMDS_HDMI_MODE = 3 +RESERVED4 = 4 +DP_MST_MODE = 5 +RESERVED2 = 6 +RESERVED3 = 7 +DIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' +DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_ON_LINK0', + 1: 'DIG_OUTPUT_CRC_ON_LINK1', +} +DIG_OUTPUT_CRC_ON_LINK0 = 0 +DIG_OUTPUT_CRC_ON_LINK1 = 1 +DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' +DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', + 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', + 2: 'DIG_OUTPUT_CRC_FOR_VBI', + 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', +} +DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 +DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 +DIG_OUTPUT_CRC_FOR_VBI = 2 +DIG_OUTPUT_CRC_FOR_AUDIO = 3 +DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' +DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', +} +DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 +DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 +DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' +DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', +} +DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 +DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 +DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { + 0: 'DIG_10BIT_TEST_PATTERN', + 1: 'DIG_ALTERNATING_TEST_PATTERN', +} +DIG_10BIT_TEST_PATTERN = 0 +DIG_ALTERNATING_TEST_PATTERN = 1 +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_NORMAL', + 1: 'DIG_TEST_PATTERN_RANDOM', +} +DIG_TEST_PATTERN_NORMAL = 0 +DIG_TEST_PATTERN_RANDOM = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_ENABLED', + 1: 'DIG_RANDOM_PATTERN_RESETED', +} +DIG_RANDOM_PATTERN_ENABLED = 0 +DIG_RANDOM_PATTERN_RESETED = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_IN_NORMAL_OPERATION', + 1: 'DIG_IN_DEBUG_MODE', +} +DIG_IN_NORMAL_OPERATION = 0 +DIG_IN_DEBUG_MODE = 1 +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACP_SEND' +HDMI_ACP_SEND__enumvalues = { + 0: 'HDMI_ACP_NOT_SEND', + 1: 'HDMI_ACP_PKT_SEND', +} +HDMI_ACP_NOT_SEND = 0 +HDMI_ACP_PKT_SEND = 1 +HDMI_ACP_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' +HDMI_ACR_AUDIO_PRIORITY__enumvalues = { + 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', +} +HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 +HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 +HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_CONT' +HDMI_ACR_CONT__enumvalues = { + 0: 'HDMI_ACR_CONT_DISABLE', + 1: 'HDMI_ACR_CONT_ENABLE', +} +HDMI_ACR_CONT_DISABLE = 0 +HDMI_ACR_CONT_ENABLE = 1 +HDMI_ACR_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_N_MULTIPLE' +HDMI_ACR_N_MULTIPLE__enumvalues = { + 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', + 1: 'HDMI_ACR_1_MULTIPLE', + 2: 'HDMI_ACR_2_MULTIPLE', + 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', + 4: 'HDMI_ACR_4_MULTIPLE', + 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', + 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', + 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', +} +HDMI_ACR_0_MULTIPLE_RESERVED = 0 +HDMI_ACR_1_MULTIPLE = 1 +HDMI_ACR_2_MULTIPLE = 2 +HDMI_ACR_3_MULTIPLE_RESERVED = 3 +HDMI_ACR_4_MULTIPLE = 4 +HDMI_ACR_5_MULTIPLE_RESERVED = 5 +HDMI_ACR_6_MULTIPLE_RESERVED = 6 +HDMI_ACR_7_MULTIPLE_RESERVED = 7 +HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SELECT' +HDMI_ACR_SELECT__enumvalues = { + 0: 'HDMI_ACR_SELECT_HW', + 1: 'HDMI_ACR_SELECT_32K', + 2: 'HDMI_ACR_SELECT_44K', + 3: 'HDMI_ACR_SELECT_48K', +} +HDMI_ACR_SELECT_HW = 0 +HDMI_ACR_SELECT_32K = 1 +HDMI_ACR_SELECT_44K = 2 +HDMI_ACR_SELECT_48K = 3 +HDMI_ACR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SEND' +HDMI_ACR_SEND__enumvalues = { + 0: 'HDMI_ACR_NOT_SEND', + 1: 'HDMI_ACR_PKT_SEND', +} +HDMI_ACR_NOT_SEND = 0 +HDMI_ACR_PKT_SEND = 1 +HDMI_ACR_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SOURCE' +HDMI_ACR_SOURCE__enumvalues = { + 0: 'HDMI_ACR_SOURCE_HW', + 1: 'HDMI_ACR_SOURCE_SW', +} +HDMI_ACR_SOURCE_HW = 0 +HDMI_ACR_SOURCE_SW = 1 +HDMI_ACR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_DELAY_EN' +HDMI_AUDIO_DELAY_EN__enumvalues = { + 0: 'HDMI_AUDIO_DELAY_DISABLE', + 1: 'HDMI_AUDIO_DELAY_58CLK', + 2: 'HDMI_AUDIO_DELAY_56CLK', + 3: 'HDMI_AUDIO_DELAY_RESERVED', +} +HDMI_AUDIO_DELAY_DISABLE = 0 +HDMI_AUDIO_DELAY_58CLK = 1 +HDMI_AUDIO_DELAY_56CLK = 2 +HDMI_AUDIO_DELAY_RESERVED = 3 +HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_CONT' +HDMI_AUDIO_INFO_CONT__enumvalues = { + 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', + 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', +} +HDMI_AUDIO_INFO_CONT_DISABLE = 0 +HDMI_AUDIO_INFO_CONT_ENABLE = 1 +HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_SEND' +HDMI_AUDIO_INFO_SEND__enumvalues = { + 0: 'HDMI_AUDIO_INFO_NOT_SEND', + 1: 'HDMI_AUDIO_INFO_PKT_SEND', +} +HDMI_AUDIO_INFO_NOT_SEND = 0 +HDMI_AUDIO_INFO_PKT_SEND = 1 +HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' +HDMI_CLOCK_CHANNEL_RATE__enumvalues = { + 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', +} +HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 +HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 +HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DATA_SCRAMBLE_EN' +HDMI_DATA_SCRAMBLE_EN__enumvalues = { + 0: 'HDMI_DATA_SCRAMBLE_DISABLE', + 1: 'HDMI_DATA_SCRAMBLE_ENABLE', +} +HDMI_DATA_SCRAMBLE_DISABLE = 0 +HDMI_DATA_SCRAMBLE_ENABLE = 1 +HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEEP_COLOR_DEPTH' +HDMI_DEEP_COLOR_DEPTH__enumvalues = { + 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', + 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 3: 'HDMI_DEEP_COLOR_DEPTH_48BPP', +} +HDMI_DEEP_COLOR_DEPTH_24BPP = 0 +HDMI_DEEP_COLOR_DEPTH_30BPP = 1 +HDMI_DEEP_COLOR_DEPTH_36BPP = 2 +HDMI_DEEP_COLOR_DEPTH_48BPP = 3 +HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEFAULT_PAHSE' +HDMI_DEFAULT_PAHSE__enumvalues = { + 0: 'HDMI_DEFAULT_PHASE_IS_0', + 1: 'HDMI_DEFAULT_PHASE_IS_1', +} +HDMI_DEFAULT_PHASE_IS_0 = 0 +HDMI_DEFAULT_PHASE_IS_1 = 1 +HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_ACK' +HDMI_ERROR_ACK__enumvalues = { + 0: 'HDMI_ERROR_ACK_INT', + 1: 'HDMI_ERROR_NOT_ACK', +} +HDMI_ERROR_ACK_INT = 0 +HDMI_ERROR_NOT_ACK = 1 +HDMI_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_MASK' +HDMI_ERROR_MASK__enumvalues = { + 0: 'HDMI_ERROR_MASK_INT', + 1: 'HDMI_ERROR_NOT_MASK', +} +HDMI_ERROR_MASK_INT = 0 +HDMI_ERROR_NOT_MASK = 1 +HDMI_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE' +HDMI_GC_AVMUTE__enumvalues = { + 0: 'HDMI_GC_AVMUTE_SET', + 1: 'HDMI_GC_AVMUTE_UNSET', +} +HDMI_GC_AVMUTE_SET = 0 +HDMI_GC_AVMUTE_UNSET = 1 +HDMI_GC_AVMUTE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE_CONT' +HDMI_GC_AVMUTE_CONT__enumvalues = { + 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', + 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', +} +HDMI_GC_AVMUTE_CONT_DISABLE = 0 +HDMI_GC_AVMUTE_CONT_ENABLE = 1 +HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_CONT' +HDMI_GC_CONT__enumvalues = { + 0: 'HDMI_GC_CONT_DISABLE', + 1: 'HDMI_GC_CONT_ENABLE', +} +HDMI_GC_CONT_DISABLE = 0 +HDMI_GC_CONT_ENABLE = 1 +HDMI_GC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_SEND' +HDMI_GC_SEND__enumvalues = { + 0: 'HDMI_GC_NOT_SEND', + 1: 'HDMI_GC_PKT_SEND', +} +HDMI_GC_NOT_SEND = 0 +HDMI_GC_PKT_SEND = 1 +HDMI_GC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC_CONT' +HDMI_GENERIC_CONT__enumvalues = { + 0: 'HDMI_GENERIC_CONT_DISABLE', + 1: 'HDMI_GENERIC_CONT_ENABLE', +} +HDMI_GENERIC_CONT_DISABLE = 0 +HDMI_GENERIC_CONT_ENABLE = 1 +HDMI_GENERIC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC_SEND' +HDMI_GENERIC_SEND__enumvalues = { + 0: 'HDMI_GENERIC_NOT_SEND', + 1: 'HDMI_GENERIC_PKT_SEND', +} +HDMI_GENERIC_NOT_SEND = 0 +HDMI_GENERIC_PKT_SEND = 1 +HDMI_GENERIC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_CONT' +HDMI_ISRC_CONT__enumvalues = { + 0: 'HDMI_ISRC_CONT_DISABLE', + 1: 'HDMI_ISRC_CONT_ENABLE', +} +HDMI_ISRC_CONT_DISABLE = 0 +HDMI_ISRC_CONT_ENABLE = 1 +HDMI_ISRC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_SEND' +HDMI_ISRC_SEND__enumvalues = { + 0: 'HDMI_ISRC_NOT_SEND', + 1: 'HDMI_ISRC_PKT_SEND', +} +HDMI_ISRC_NOT_SEND = 0 +HDMI_ISRC_PKT_SEND = 1 +HDMI_ISRC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_KEEPOUT_MODE' +HDMI_KEEPOUT_MODE__enumvalues = { + 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', +} +HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 +HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 +HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_METADATA_ENABLE' +HDMI_METADATA_ENABLE__enumvalues = { + 0: 'HDMI_METADATA_NOT_SEND', + 1: 'HDMI_METADATA_PKT_SEND', +} +HDMI_METADATA_NOT_SEND = 0 +HDMI_METADATA_PKT_SEND = 1 +HDMI_METADATA_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_CONT' +HDMI_MPEG_INFO_CONT__enumvalues = { + 0: 'HDMI_MPEG_INFO_CONT_DISABLE', + 1: 'HDMI_MPEG_INFO_CONT_ENABLE', +} +HDMI_MPEG_INFO_CONT_DISABLE = 0 +HDMI_MPEG_INFO_CONT_ENABLE = 1 +HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_SEND' +HDMI_MPEG_INFO_SEND__enumvalues = { + 0: 'HDMI_MPEG_INFO_NOT_SEND', + 1: 'HDMI_MPEG_INFO_PKT_SEND', +} +HDMI_MPEG_INFO_NOT_SEND = 0 +HDMI_MPEG_INFO_PKT_SEND = 1 +HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' +HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { + 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', + 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', +} +HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 +HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 +HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NULL_SEND' +HDMI_NULL_SEND__enumvalues = { + 0: 'HDMI_NULL_NOT_SEND', + 1: 'HDMI_NULL_PKT_SEND', +} +HDMI_NULL_NOT_SEND = 0 +HDMI_NULL_PKT_SEND = 1 +HDMI_NULL_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKET_GEN_VERSION' +HDMI_PACKET_GEN_VERSION__enumvalues = { + 0: 'HDMI_PACKET_GEN_VERSION_OLD', + 1: 'HDMI_PACKET_GEN_VERSION_NEW', +} +HDMI_PACKET_GEN_VERSION_OLD = 0 +HDMI_PACKET_GEN_VERSION_NEW = 1 +HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKET_LINE_REFERENCE' +HDMI_PACKET_LINE_REFERENCE__enumvalues = { + 0: 'HDMI_PKT_LINE_REF_VSYNC', + 1: 'HDMI_PKT_LINE_REF_OTGSOF', +} +HDMI_PKT_LINE_REF_VSYNC = 0 +HDMI_PKT_LINE_REF_OTGSOF = 1 +HDMI_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' +HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { + 0: 'HDMI_PACKING_PHASE_SET_BY_HW', + 1: 'HDMI_PACKING_PHASE_SET_BY_SW', +} +HDMI_PACKING_PHASE_SET_BY_HW = 0 +HDMI_PACKING_PHASE_SET_BY_SW = 1 +HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', +} +LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 +LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_COLOR_FORMAT' +TMDS_COLOR_FORMAT__enumvalues = { + 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', + 3: 'TMDS_COLOR_FORMAT_RESERVED', +} +TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 +TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 +TMDS_COLOR_FORMAT_DUAL30BPP = 2 +TMDS_COLOR_FORMAT_RESERVED = 3 +TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_INVERT' +TMDS_CTL0_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL0_DATA_NORMAL', + 1: 'TMDS_CTL0_DATA_INVERT_EN', +} +TMDS_CTL0_DATA_NORMAL = 0 +TMDS_CTL0_DATA_INVERT_EN = 1 +TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_MODULATION' +TMDS_CTL0_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', +} +TMDS_CTL0_DATA_MODULATION_DISABLE = 0 +TMDS_CTL0_DATA_MODULATION_BIT0 = 1 +TMDS_CTL0_DATA_MODULATION_BIT1 = 2 +TMDS_CTL0_DATA_MODULATION_BIT2 = 3 +TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_SEL' +TMDS_CTL0_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', +} +TMDS_CTL0_DATA_SEL0_RESERVED = 0 +TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL0_DATA_SEL2_VSYNC = 2 +TMDS_CTL0_DATA_SEL3_RESERVED = 3 +TMDS_CTL0_DATA_SEL4_HSYNC = 4 +TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 +TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 +TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' +TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', +} +TMDS_CTL0_PATTERN_OUT_DISABLE = 0 +TMDS_CTL0_PATTERN_OUT_ENABLE = 1 +TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_INVERT' +TMDS_CTL1_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL1_DATA_NORMAL', + 1: 'TMDS_CTL1_DATA_INVERT_EN', +} +TMDS_CTL1_DATA_NORMAL = 0 +TMDS_CTL1_DATA_INVERT_EN = 1 +TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_MODULATION' +TMDS_CTL1_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', +} +TMDS_CTL1_DATA_MODULATION_DISABLE = 0 +TMDS_CTL1_DATA_MODULATION_BIT0 = 1 +TMDS_CTL1_DATA_MODULATION_BIT1 = 2 +TMDS_CTL1_DATA_MODULATION_BIT2 = 3 +TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_SEL' +TMDS_CTL1_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL1_DATA_SEL0_RESERVED = 0 +TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL1_DATA_SEL2_VSYNC = 2 +TMDS_CTL1_DATA_SEL3_RESERVED = 3 +TMDS_CTL1_DATA_SEL4_HSYNC = 4 +TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' +TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', +} +TMDS_CTL1_PATTERN_OUT_DISABLE = 0 +TMDS_CTL1_PATTERN_OUT_ENABLE = 1 +TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_INVERT' +TMDS_CTL2_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL2_DATA_NORMAL', + 1: 'TMDS_CTL2_DATA_INVERT_EN', +} +TMDS_CTL2_DATA_NORMAL = 0 +TMDS_CTL2_DATA_INVERT_EN = 1 +TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_MODULATION' +TMDS_CTL2_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', +} +TMDS_CTL2_DATA_MODULATION_DISABLE = 0 +TMDS_CTL2_DATA_MODULATION_BIT0 = 1 +TMDS_CTL2_DATA_MODULATION_BIT1 = 2 +TMDS_CTL2_DATA_MODULATION_BIT2 = 3 +TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_SEL' +TMDS_CTL2_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL2_DATA_SEL0_RESERVED = 0 +TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL2_DATA_SEL2_VSYNC = 2 +TMDS_CTL2_DATA_SEL3_RESERVED = 3 +TMDS_CTL2_DATA_SEL4_HSYNC = 4 +TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' +TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', +} +TMDS_CTL2_PATTERN_OUT_DISABLE = 0 +TMDS_CTL2_PATTERN_OUT_ENABLE = 1 +TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_INVERT' +TMDS_CTL3_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL3_DATA_NORMAL', + 1: 'TMDS_CTL3_DATA_INVERT_EN', +} +TMDS_CTL3_DATA_NORMAL = 0 +TMDS_CTL3_DATA_INVERT_EN = 1 +TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_MODULATION' +TMDS_CTL3_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', +} +TMDS_CTL3_DATA_MODULATION_DISABLE = 0 +TMDS_CTL3_DATA_MODULATION_BIT0 = 1 +TMDS_CTL3_DATA_MODULATION_BIT1 = 2 +TMDS_CTL3_DATA_MODULATION_BIT2 = 3 +TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_SEL' +TMDS_CTL3_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL3_DATA_SEL0_RESERVED = 0 +TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL3_DATA_SEL2_VSYNC = 2 +TMDS_CTL3_DATA_SEL3_RESERVED = 3 +TMDS_CTL3_DATA_SEL4_HSYNC = 4 +TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' +TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', +} +TMDS_CTL3_PATTERN_OUT_DISABLE = 0 +TMDS_CTL3_PATTERN_OUT_ENABLE = 1 +TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' +TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { + 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', +} +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_PIXEL_ENCODING' +TMDS_PIXEL_ENCODING__enumvalues = { + 0: 'TMDS_PIXEL_ENCODING_444_OR_420', + 1: 'TMDS_PIXEL_ENCODING_422', +} +TMDS_PIXEL_ENCODING_444_OR_420 = 0 +TMDS_PIXEL_ENCODING_422 = 1 +TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' +TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', +} +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 +TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 +TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' +TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', + 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', +} +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 +TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 +TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' +TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { + 0: 'TMDS_STEREOSYNC_CTL0', + 1: 'TMDS_STEREOSYNC_CTL1', + 2: 'TMDS_STEREOSYNC_CTL2', + 3: 'TMDS_STEREOSYNC_CTL3', +} +TMDS_STEREOSYNC_CTL0 = 0 +TMDS_STEREOSYNC_CTL1 = 1 +TMDS_STEREOSYNC_CTL2 = 2 +TMDS_STEREOSYNC_CTL3 = 3 +TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_SYNC_PHASE' +TMDS_SYNC_PHASE__enumvalues = { + 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', + 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', +} +TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 +TMDS_SYNC_PHASE_ON_FRAME_START = 1 +TMDS_SYNC_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' +TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' +TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', +} +TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 +TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', +} +TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', +} +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', +} +TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 +TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 +TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', + 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 +TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ACK' +DOUT_I2C_ACK__enumvalues = { + 0: 'DOUT_I2C_NO_ACK', + 1: 'DOUT_I2C_ACK_TO_CLEAN', +} +DOUT_I2C_NO_ACK = 0 +DOUT_I2C_ACK_TO_CLEAN = 1 +DOUT_I2C_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' +DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', +} +DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 +DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 +DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', +} +DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 +DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', +} +DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 +DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' +DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', +} +DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 +DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 +DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 +DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 +DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', +} +DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 +DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL' +DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG', + 1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', +} +DOUT_I2C_CONTROL_NORMAL_DEBUG = 0 +DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1 +DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' +DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', + 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', + 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', + 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', + 4: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', +} +DOUT_I2C_CONTROL_SELECT_DDC1 = 0 +DOUT_I2C_CONTROL_SELECT_DDC2 = 1 +DOUT_I2C_CONTROL_SELECT_DDC3 = 2 +DOUT_I2C_CONTROL_SELECT_DDC4 = 3 +DOUT_I2C_CONTROL_SELECT_DDCVGA = 4 +DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_GO' +DOUT_I2C_CONTROL_GO__enumvalues = { + 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 1: 'DOUT_I2C_CONTROL_START_TRANSFER', +} +DOUT_I2C_CONTROL_STOP_TRANSFER = 0 +DOUT_I2C_CONTROL_START_TRANSFER = 1 +DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' +DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 1: 'DOUT_I2C_CONTROL__SEND_RESET', +} +DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 +DOUT_I2C_CONTROL__SEND_RESET = 1 +DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH' +DOUT_I2C_CONTROL_SEND_RESET_LENGTH__enumvalues = { + 0: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', + 1: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', +} +DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0 +DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 1 +DOUT_I2C_CONTROL_SEND_RESET_LENGTH = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' +DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', +} +DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 +DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 +DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' +DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', +} +DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 +DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 +DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' +DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_TRANS0', + 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', +} +DOUT_I2C_CONTROL_TRANS0 = 0 +DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 +DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' +DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { + 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 1: 'DOUT_I2C_DATA__INDEX_WRITE', +} +DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 +DOUT_I2C_DATA__INDEX_WRITE = 1 +DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', +} +DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', +} +DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 +DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' +DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { + 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', +} +DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 +DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 +DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 +DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 +DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', +} +DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 +DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { + 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', +} +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' +DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { + 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', +} +DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 +DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 +DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_GATING_EN' +CLOCK_GATING_EN__enumvalues = { + 0: 'CLOCK_GATING_ENABLE', + 1: 'CLOCK_GATING_DISABLE', +} +CLOCK_GATING_ENABLE = 0 +CLOCK_GATING_DISABLE = 1 +CLOCK_GATING_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DAC_MUX_SELECT' +DAC_MUX_SELECT__enumvalues = { + 0: 'DAC_MUX_SELECT_DACA', + 1: 'DAC_MUX_SELECT_DACB', +} +DAC_MUX_SELECT_DACA = 0 +DAC_MUX_SELECT_DACB = 1 +DAC_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_DIS_CTRL' +DIOMEM_PWR_DIS_CTRL__enumvalues = { + 0: 'DIOMEM_ENABLE_MEM_PWR_CTRL', + 1: 'DIOMEM_DISABLE_MEM_PWR_CTRL', +} +DIOMEM_ENABLE_MEM_PWR_CTRL = 0 +DIOMEM_DISABLE_MEM_PWR_CTRL = 1 +DIOMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_FORCE_CTRL' +DIOMEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'DIOMEM_NO_FORCE_REQUEST', + 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', +} +DIOMEM_NO_FORCE_REQUEST = 0 +DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 2 +DIOMEM_FORCE_SHUT_DOWN_REQUEST = 3 +DIOMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_FORCE_CTRL2' +DIOMEM_PWR_FORCE_CTRL2__enumvalues = { + 0: 'DIOMEM_NO_FORCE_REQ', + 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', +} +DIOMEM_NO_FORCE_REQ = 0 +DIOMEM_FORCE_LIGHT_SLEEP_REQ = 1 +DIOMEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_SEL_CTRL' +DIOMEM_PWR_SEL_CTRL__enumvalues = { + 0: 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', + 1: 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', + 2: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', +} +DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0 +DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 1 +DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 2 +DIOMEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_SEL_CTRL2' +DIOMEM_PWR_SEL_CTRL2__enumvalues = { + 0: 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', + 1: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', +} +DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0 +DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 1 +DIOMEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_CLOCK_GATING_DISABLE' +DIO_CLOCK_GATING_DISABLE__enumvalues = { + 0: 'DIO_CLOCK_GATING_EN', + 1: 'DIO_CLOCK_GATING_DIS', +} +DIO_CLOCK_GATING_EN = 0 +DIO_CLOCK_GATING_DIS = 1 +DIO_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_DBG_BLOCK_SEL' +DIO_DBG_BLOCK_SEL__enumvalues = { + 0: 'DIO_DBG_BLOCK_SEL_DIO', + 11: 'DIO_DBG_BLOCK_SEL_DIGFE_A', + 12: 'DIO_DBG_BLOCK_SEL_DIGFE_B', + 13: 'DIO_DBG_BLOCK_SEL_DIGFE_C', + 14: 'DIO_DBG_BLOCK_SEL_DIGFE_D', + 18: 'DIO_DBG_BLOCK_SEL_DIGA', + 19: 'DIO_DBG_BLOCK_SEL_DIGB', + 20: 'DIO_DBG_BLOCK_SEL_DIGC', + 21: 'DIO_DBG_BLOCK_SEL_DIGD', + 25: 'DIO_DBG_BLOCK_SEL_DPFE_A', + 26: 'DIO_DBG_BLOCK_SEL_DPFE_B', + 27: 'DIO_DBG_BLOCK_SEL_DPFE_C', + 28: 'DIO_DBG_BLOCK_SEL_DPFE_D', + 32: 'DIO_DBG_BLOCK_SEL_DPA', + 33: 'DIO_DBG_BLOCK_SEL_DPB', + 34: 'DIO_DBG_BLOCK_SEL_DPC', + 35: 'DIO_DBG_BLOCK_SEL_DPD', + 39: 'DIO_DBG_BLOCK_SEL_AUX0', + 40: 'DIO_DBG_BLOCK_SEL_AUX1', + 41: 'DIO_DBG_BLOCK_SEL_AUX2', + 42: 'DIO_DBG_BLOCK_SEL_AUX3', + 45: 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', + 46: 'DIO_DBG_BLOCK_SEL_RESERVED', +} +DIO_DBG_BLOCK_SEL_DIO = 0 +DIO_DBG_BLOCK_SEL_DIGFE_A = 11 +DIO_DBG_BLOCK_SEL_DIGFE_B = 12 +DIO_DBG_BLOCK_SEL_DIGFE_C = 13 +DIO_DBG_BLOCK_SEL_DIGFE_D = 14 +DIO_DBG_BLOCK_SEL_DIGA = 18 +DIO_DBG_BLOCK_SEL_DIGB = 19 +DIO_DBG_BLOCK_SEL_DIGC = 20 +DIO_DBG_BLOCK_SEL_DIGD = 21 +DIO_DBG_BLOCK_SEL_DPFE_A = 25 +DIO_DBG_BLOCK_SEL_DPFE_B = 26 +DIO_DBG_BLOCK_SEL_DPFE_C = 27 +DIO_DBG_BLOCK_SEL_DPFE_D = 28 +DIO_DBG_BLOCK_SEL_DPA = 32 +DIO_DBG_BLOCK_SEL_DPB = 33 +DIO_DBG_BLOCK_SEL_DPC = 34 +DIO_DBG_BLOCK_SEL_DPD = 35 +DIO_DBG_BLOCK_SEL_AUX0 = 39 +DIO_DBG_BLOCK_SEL_AUX1 = 40 +DIO_DBG_BLOCK_SEL_AUX2 = 41 +DIO_DBG_BLOCK_SEL_AUX3 = 42 +DIO_DBG_BLOCK_SEL_PERFMON_DIO = 45 +DIO_DBG_BLOCK_SEL_RESERVED = 46 +DIO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE' +DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { + 0: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 1: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', +} +DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 +DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 +DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DIO_DCN_ACTIVE_STATUS' +ENUM_DIO_DCN_ACTIVE_STATUS__enumvalues = { + 0: 'ENUM_DCN_NOT_ACTIVE', + 1: 'ENUM_DCN_ACTIVE', +} +ENUM_DCN_NOT_ACTIVE = 0 +ENUM_DCN_ACTIVE = 1 +ENUM_DIO_DCN_ACTIVE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_STEREOSYNC_SEL' +GENERIC_STEREOSYNC_SEL__enumvalues = { + 0: 'GENERIC_STEREOSYNC_SEL_D1', + 1: 'GENERIC_STEREOSYNC_SEL_D2', + 2: 'GENERIC_STEREOSYNC_SEL_D3', + 3: 'GENERIC_STEREOSYNC_SEL_D4', + 4: 'GENERIC_STEREOSYNC_SEL_RESERVED', +} +GENERIC_STEREOSYNC_SEL_D1 = 0 +GENERIC_STEREOSYNC_SEL_D2 = 1 +GENERIC_STEREOSYNC_SEL_D3 = 2 +GENERIC_STEREOSYNC_SEL_D4 = 3 +GENERIC_STEREOSYNC_SEL_RESERVED = 4 +GENERIC_STEREOSYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PM_ASSERT_RESET' +PM_ASSERT_RESET__enumvalues = { + 0: 'PM_ASSERT_RESET_0', + 1: 'PM_ASSERT_RESET_1', +} +PM_ASSERT_RESET_0 = 0 +PM_ASSERT_RESET_1 = 1 +PM_ASSERT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'SOFT_RESET' +SOFT_RESET__enumvalues = { + 0: 'SOFT_RESET_0', + 1: 'SOFT_RESET_1', +} +SOFT_RESET_0 = 0 +SOFT_RESET_1 = 1 +SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_MUX_SELECT' +TMDS_MUX_SELECT__enumvalues = { + 0: 'TMDS_MUX_SELECT_B', + 1: 'TMDS_MUX_SELECT_G', + 2: 'TMDS_MUX_SELECT_R', + 3: 'TMDS_MUX_SELECT_RESERVED', +} +TMDS_MUX_SELECT_B = 0 +TMDS_MUX_SELECT_G = 1 +TMDS_MUX_SELECT_R = 2 +TMDS_MUX_SELECT_RESERVED = 3 +TMDS_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET' +DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET__enumvalues = { + 0: 'DIG_STREAM_MAPPER_LINK0', + 1: 'DIG_STREAM_MAPPER_LINK1', + 2: 'DIG_STREAM_MAPPER_LINK2', + 3: 'DIG_STREAM_MAPPER_LINK3', + 4: 'DIG_STREAM_MAPPER_LINK6', +} +DIG_STREAM_MAPPER_LINK0 = 0 +DIG_STREAM_MAPPER_LINK1 = 1 +DIG_STREAM_MAPPER_LINK2 = 2 +DIG_STREAM_MAPPER_LINK3 = 3 +DIG_STREAM_MAPPER_LINK6 = 4 +DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET = ctypes.c_uint32 # enum + +# values for enumeration 'DME_MEM_POWER_STATE_ENUM' +DME_MEM_POWER_STATE_ENUM__enumvalues = { + 0: 'DME_MEM_POWER_STATE_ENUM_ON', + 1: 'DME_MEM_POWER_STATE_ENUM_LS', + 2: 'DME_MEM_POWER_STATE_ENUM_DS', + 3: 'DME_MEM_POWER_STATE_ENUM_SD', +} +DME_MEM_POWER_STATE_ENUM_ON = 0 +DME_MEM_POWER_STATE_ENUM_LS = 1 +DME_MEM_POWER_STATE_ENUM_DS = 2 +DME_MEM_POWER_STATE_ENUM_SD = 3 +DME_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DME_MEM_PWR_DIS_CTRL' +DME_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'DME_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'DME_MEM_DISABLE_MEM_PWR_CTRL', +} +DME_MEM_ENABLE_MEM_PWR_CTRL = 0 +DME_MEM_DISABLE_MEM_PWR_CTRL = 1 +DME_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DME_MEM_PWR_FORCE_CTRL' +DME_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'DME_MEM_NO_FORCE_REQUEST', + 1: 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', +} +DME_MEM_NO_FORCE_REQUEST = 0 +DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 +DME_MEM_FORCE_SHUT_DOWN_REQUEST = 3 +DME_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'METADATA_HUBP_SEL' +METADATA_HUBP_SEL__enumvalues = { + 0: 'METADATA_HUBP_SEL_0', + 1: 'METADATA_HUBP_SEL_1', + 2: 'METADATA_HUBP_SEL_2', + 3: 'METADATA_HUBP_SEL_3', + 4: 'METADATA_HUBP_SEL_RESERVED', +} +METADATA_HUBP_SEL_0 = 0 +METADATA_HUBP_SEL_1 = 1 +METADATA_HUBP_SEL_2 = 2 +METADATA_HUBP_SEL_3 = 3 +METADATA_HUBP_SEL_RESERVED = 4 +METADATA_HUBP_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'METADATA_STREAM_TYPE_SEL' +METADATA_STREAM_TYPE_SEL__enumvalues = { + 0: 'METADATA_STREAM_DP', + 1: 'METADATA_STREAM_DVE', +} +METADATA_STREAM_DP = 0 +METADATA_STREAM_DVE = 1 +METADATA_STREAM_TYPE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VPG_MEM_PWR_DIS_CTRL' +VPG_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'VPG_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'VPG_MEM_DISABLE_MEM_PWR_CTRL', +} +VPG_MEM_ENABLE_MEM_PWR_CTRL = 0 +VPG_MEM_DISABLE_MEM_PWR_CTRL = 1 +VPG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'VPG_MEM_PWR_FORCE_CTRL' +VPG_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'VPG_MEM_NO_FORCE_REQ', + 1: 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', +} +VPG_MEM_NO_FORCE_REQ = 0 +VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 1 +VPG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_ACP_TYPE' +AFMT_ACP_TYPE__enumvalues = { + 0: 'ACP_TYPE_GENERIC_AUDIO', + 1: 'ACP_TYPE_ICE60958_AUDIO', + 2: 'ACP_TYPE_DVD_AUDIO', + 3: 'ACP_TYPE_SUPER_AUDIO_CD', +} +ACP_TYPE_GENERIC_AUDIO = 0 +ACP_TYPE_ICE60958_AUDIO = 1 +ACP_TYPE_DVD_AUDIO = 2 +ACP_TYPE_SUPER_AUDIO_CD = 3 +AFMT_ACP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' +AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { + 0: 'AFMT_AUDIO_CRC_CH0_SIG', + 1: 'AFMT_AUDIO_CRC_CH1_SIG', + 2: 'AFMT_AUDIO_CRC_CH2_SIG', + 3: 'AFMT_AUDIO_CRC_CH3_SIG', + 4: 'AFMT_AUDIO_CRC_CH4_SIG', + 5: 'AFMT_AUDIO_CRC_CH5_SIG', + 6: 'AFMT_AUDIO_CRC_CH6_SIG', + 7: 'AFMT_AUDIO_CRC_CH7_SIG', + 8: 'AFMT_AUDIO_CRC_RESERVED_8', + 9: 'AFMT_AUDIO_CRC_RESERVED_9', + 10: 'AFMT_AUDIO_CRC_RESERVED_10', + 11: 'AFMT_AUDIO_CRC_RESERVED_11', + 12: 'AFMT_AUDIO_CRC_RESERVED_12', + 13: 'AFMT_AUDIO_CRC_RESERVED_13', + 14: 'AFMT_AUDIO_CRC_RESERVED_14', + 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', +} +AFMT_AUDIO_CRC_CH0_SIG = 0 +AFMT_AUDIO_CRC_CH1_SIG = 1 +AFMT_AUDIO_CRC_CH2_SIG = 2 +AFMT_AUDIO_CRC_CH3_SIG = 3 +AFMT_AUDIO_CRC_CH4_SIG = 4 +AFMT_AUDIO_CRC_CH5_SIG = 5 +AFMT_AUDIO_CRC_CH6_SIG = 6 +AFMT_AUDIO_CRC_CH7_SIG = 7 +AFMT_AUDIO_CRC_RESERVED_8 = 8 +AFMT_AUDIO_CRC_RESERVED_9 = 9 +AFMT_AUDIO_CRC_RESERVED_10 = 10 +AFMT_AUDIO_CRC_RESERVED_11 = 11 +AFMT_AUDIO_CRC_RESERVED_12 = 12 +AFMT_AUDIO_CRC_RESERVED_13 = 13 +AFMT_AUDIO_CRC_RESERVED_14 = 14 +AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 +AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' +AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { + 0: 'AFMT_AUDIO_CRC_ONESHOT', + 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', +} +AFMT_AUDIO_CRC_ONESHOT = 0 +AFMT_AUDIO_CRC_AUTO_RESTART = 1 +AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' +AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { + 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', +} +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 +AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { + 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', +} +AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 +AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { + 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', +} +AFMT_AUDIO_PACKET_SENT_DISABLED = 0 +AFMT_AUDIO_PACKET_SENT_ENABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { + 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', +} +AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 +AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' +AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { + 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', +} +AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 +AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 +AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 +AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 +AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 +AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 +AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS' +AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { + 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', +} +HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 +HDMI_SEND_MAX_AUDIO_PACKETS = 1 +AFMT_HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { + 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', +} +AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 +AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' +AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { + 0: 'AFMT_INTERRUPT_DISABLE', + 1: 'AFMT_INTERRUPT_ENABLE', +} +AFMT_INTERRUPT_DISABLE = 0 +AFMT_INTERRUPT_ENABLE = 1 +AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_MEM_PWR_DIS_CTRL' +AFMT_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', +} +AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0 +AFMT_MEM_DISABLE_MEM_PWR_CTRL = 1 +AFMT_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_MEM_PWR_FORCE_CTRL' +AFMT_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'AFMT_MEM_NO_FORCE_REQUEST', + 1: 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', +} +AFMT_MEM_NO_FORCE_REQUEST = 0 +AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 +AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 3 +AFMT_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' +AFMT_RAMP_CONTROL0_SIGN__enumvalues = { + 0: 'AFMT_RAMP_SIGNED', + 1: 'AFMT_RAMP_UNSIGNED', +} +AFMT_RAMP_SIGNED = 0 +AFMT_RAMP_UNSIGNED = 1 +AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE' +AFMT_VBI_PACKET_CONTROL_ACP_SOURCE__enumvalues = { + 0: 'AFMT_ACP_SOURCE_FROM_AZALIA', + 1: 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', +} +AFMT_ACP_SOURCE_FROM_AZALIA = 0 +AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 1 +AFMT_VBI_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AUDIO_LAYOUT_SELECT' +AUDIO_LAYOUT_SELECT__enumvalues = { + 0: 'AUDIO_LAYOUT_0', + 1: 'AUDIO_LAYOUT_1', +} +AUDIO_LAYOUT_0 = 0 +AUDIO_LAYOUT_1 = 1 +AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCOH_TEST_CLOCK_MUX_SELECT_ENUM' +DCOH_TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = { + 0: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_P', + 1: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_R', + 2: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX1', + 3: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX2', + 4: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX3', + 5: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX4', + 6: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX5', + 7: 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX6', + 8: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_P', + 9: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_R', + 10: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX1', + 11: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX2', + 12: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX3', + 13: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX4', + 14: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX5', + 15: 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX6', + 16: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK0', + 17: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK1', + 18: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK2', + 19: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK3', + 20: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK4', + 21: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK5', + 22: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK6', + 23: 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK7', + 24: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYASYMCLK', + 25: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYBSYMCLK', + 26: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYCSYMCLK', + 27: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYDSYMCLK', + 28: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYESYMCLK', + 29: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYFSYMCLK', + 30: 'DCOH_TEST_CLOCK_MUX_SELECT_PHYGSYMCLK', +} +DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0 +DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_R = 1 +DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX1 = 2 +DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX2 = 3 +DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX3 = 4 +DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX4 = 5 +DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX5 = 6 +DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX6 = 7 +DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_P = 8 +DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_R = 9 +DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX1 = 10 +DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX2 = 11 +DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX3 = 12 +DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX4 = 13 +DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX5 = 14 +DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX6 = 15 +DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK0 = 16 +DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK1 = 17 +DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK2 = 18 +DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK3 = 19 +DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK4 = 20 +DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK5 = 21 +DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK6 = 22 +DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK7 = 23 +DCOH_TEST_CLOCK_MUX_SELECT_PHYASYMCLK = 24 +DCOH_TEST_CLOCK_MUX_SELECT_PHYBSYMCLK = 25 +DCOH_TEST_CLOCK_MUX_SELECT_PHYCSYMCLK = 26 +DCOH_TEST_CLOCK_MUX_SELECT_PHYDSYMCLK = 27 +DCOH_TEST_CLOCK_MUX_SELECT_PHYESYMCLK = 28 +DCOH_TEST_CLOCK_MUX_SELECT_PHYFSYMCLK = 29 +DCOH_TEST_CLOCK_MUX_SELECT_PHYGSYMCLK = 30 +DCOH_TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM' +DCOH_TOP_CLOCK_GATING_DISABLE_ENUM__enumvalues = { + 0: 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_ENABLED', + 1: 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_DISABLED', +} +DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_ENABLED = 0 +DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_DISABLED = 1 +DCOH_TOP_CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DCOH_TOP_ENABLE_ENUM' +DCOH_TOP_ENABLE_ENUM__enumvalues = { + 0: 'DCOH_TOP_ENABLE_ENUM_DISABLED', + 1: 'DCOH_TOP_ENABLE_ENUM_ENABLED', +} +DCOH_TOP_ENABLE_ENUM_DISABLED = 0 +DCOH_TOP_ENABLE_ENUM_ENABLED = 1 +DCOH_TOP_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'PHY_MUX_ENABLE_ENUM' +PHY_MUX_ENABLE_ENUM__enumvalues = { + 0: 'PHY_MUX_ENABLE_ENUM_DISABLED', + 1: 'PHY_MUX_ENABLE_ENUM_ENABLED', +} +PHY_MUX_ENABLE_ENUM_DISABLED = 0 +PHY_MUX_ENABLE_ENUM_ENABLED = 1 +PHY_MUX_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' +DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', +} +DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 +DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', +} +DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 +DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', +} +DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 +DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_STATUS' +DP_AUX_ARB_STATUS__enumvalues = { + 0: 'DP_AUX_IDLE', + 1: 'DP_AUX_IN_USE_LS', + 2: 'DP_AUX_IN_USE_GTC', + 3: 'DP_AUX_IN_USE_SW', + 4: 'DP_AUX_IN_USE_PHYWAKE', +} +DP_AUX_IDLE = 0 +DP_AUX_IN_USE_LS = 1 +DP_AUX_IN_USE_GTC = 2 +DP_AUX_IN_USE_SW = 3 +DP_AUX_IN_USE_PHYWAKE = 4 +DP_AUX_ARB_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_HPD_SEL' +DP_AUX_CONTROL_HPD_SEL__enumvalues = { + 0: 'DP_AUX_CONTROL_HPD1_SELECTED', + 1: 'DP_AUX_CONTROL_HPD2_SELECTED', + 2: 'DP_AUX_CONTROL_HPD3_SELECTED', + 3: 'DP_AUX_CONTROL_HPD4_SELECTED', + 4: 'DP_AUX_CONTROL_NO_HPD_SELECTED', +} +DP_AUX_CONTROL_HPD1_SELECTED = 0 +DP_AUX_CONTROL_HPD2_SELECTED = 1 +DP_AUX_CONTROL_HPD3_SELECTED = 2 +DP_AUX_CONTROL_HPD4_SELECTED = 3 +DP_AUX_CONTROL_NO_HPD_SELECTED = 4 +DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_TEST_MODE' +DP_AUX_CONTROL_TEST_MODE__enumvalues = { + 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', +} +DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 +DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 +DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' +DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { + 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', + 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', +} +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 +DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', +} +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', +} +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { + 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', +} +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { + 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', +} +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' +DP_AUX_ERR_OCCURRED_ACK__enumvalues = { + 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 1: 'DP_AUX_ERR_OCCURRED__ACK', +} +DP_AUX_ERR_OCCURRED__NOT_ACK = 0 +DP_AUX_ERR_OCCURRED__ACK = 1 +DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', +} +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', +} +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', +} +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', +} +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_INT_ACK' +DP_AUX_INT_ACK__enumvalues = { + 0: 'DP_AUX_INT__NOT_ACK', + 1: 'DP_AUX_INT__ACK', +} +DP_AUX_INT__NOT_ACK = 0 +DP_AUX_INT__ACK = 1 +DP_AUX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_LS_UPDATE_ACK' +DP_AUX_LS_UPDATE_ACK__enumvalues = { + 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', + 1: 'DP_AUX_INT_LS_UPDATE_ACK', +} +DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 +DP_AUX_INT_LS_UPDATE_ACK = 1 +DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_PHY_WAKE_PRIORITY' +DP_AUX_PHY_WAKE_PRIORITY__enumvalues = { + 0: 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', + 1: 'DP_AUX_PHY_WAKE_LOW_PRIORITY', +} +DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0 +DP_AUX_PHY_WAKE_LOW_PRIORITY = 1 +DP_AUX_PHY_WAKE_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' +DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { + 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', + 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', +} +DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 +DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 +DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET' +DP_AUX_RESET__enumvalues = { + 0: 'DP_AUX_RESET_DEASSERTED', + 1: 'DP_AUX_RESET_ASSERTED', +} +DP_AUX_RESET_DEASSERTED = 0 +DP_AUX_RESET_ASSERTED = 1 +DP_AUX_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET_DONE' +DP_AUX_RESET_DONE__enumvalues = { + 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', + 1: 'DP_AUX_RESET_SEQUENCE_DONE', +} +DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 +DP_AUX_RESET_SEQUENCE_DONE = 1 +DP_AUX_RESET_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RX_TIMEOUT_LEN_MUL' +DP_AUX_RX_TIMEOUT_LEN_MUL__enumvalues = { + 0: 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', + 1: 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', + 2: 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', + 3: 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', +} +DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0 +DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 1 +DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 2 +DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 3 +DP_AUX_RX_TIMEOUT_LEN_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' +DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', +} +DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 +DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 +DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' +DP_AUX_SW_CONTROL_SW_GO__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 1: 'DP_AUX_SW_CONTROL_SW__GO', +} +DP_AUX_SW_CONTROL_SW__NOT_GO = 0 +DP_AUX_SW_CONTROL_SW__GO = 1 +DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_TX_PRECHARGE_LEN_MUL' +DP_AUX_TX_PRECHARGE_LEN_MUL__enumvalues = { + 0: 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', + 1: 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', + 2: 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', + 3: 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', +} +DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0 +DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 1 +DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 2 +DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 3 +DP_AUX_TX_PRECHARGE_LEN_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_ACK' +HPD_INT_CONTROL_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_ACK_0', + 1: 'HPD_INT_CONTROL_ACK_1', +} +HPD_INT_CONTROL_ACK_0 = 0 +HPD_INT_CONTROL_ACK_1 = 1 +HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_POLARITY' +HPD_INT_CONTROL_POLARITY__enumvalues = { + 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', + 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', +} +HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 +HPD_INT_CONTROL_GEN_INT_ON_CON = 1 +HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' +HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', + 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', +} +HPD_INT_CONTROL_RX_INT_ACK_0 = 0 +HPD_INT_CONTROL_RX_INT_ACK_1 = 1 +HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HPO_TOP_CLOCK_GATING_DISABLE' +HPO_TOP_CLOCK_GATING_DISABLE__enumvalues = { + 0: 'HPO_TOP_CLOCK_GATING_EN', + 1: 'HPO_TOP_CLOCK_GATING_DIS', +} +HPO_TOP_CLOCK_GATING_EN = 0 +HPO_TOP_CLOCK_GATING_DIS = 1 +HPO_TOP_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HPO_TOP_TEST_CLK_SEL' +HPO_TOP_TEST_CLK_SEL__enumvalues = { + 0: 'HPO_TOP_PERMANENT_DISPCLK', + 1: 'HPO_TOP_REGISTER_GATED_DISPCLK', + 2: 'HPO_TOP_PERMANENT_SOCCLK', + 3: 'HPO_TOP_TEST_CLOCK_RESERVED', + 4: 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', + 5: 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', + 6: 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', + 7: 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', + 8: 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', + 9: 'HPO_TOP_PERMANENT_HDMICHARCLK0', + 10: 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', + 11: 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', +} +HPO_TOP_PERMANENT_DISPCLK = 0 +HPO_TOP_REGISTER_GATED_DISPCLK = 1 +HPO_TOP_PERMANENT_SOCCLK = 2 +HPO_TOP_TEST_CLOCK_RESERVED = 3 +HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 4 +HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 5 +HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 6 +HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 7 +HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 8 +HPO_TOP_PERMANENT_HDMICHARCLK0 = 9 +HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 10 +HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 11 +HPO_TOP_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET' +DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET__enumvalues = { + 0: 'DP_STREAM_MAPPER_LINK0', + 1: 'DP_STREAM_MAPPER_LINK1', + 2: 'DP_STREAM_MAPPER_LINK2', + 3: 'DP_STREAM_MAPPER_LINK3', + 4: 'DP_STREAM_MAPPER_RESERVED', +} +DP_STREAM_MAPPER_LINK0 = 0 +DP_STREAM_MAPPER_LINK1 = 1 +DP_STREAM_MAPPER_LINK2 = 2 +DP_STREAM_MAPPER_LINK3 = 3 +DP_STREAM_MAPPER_RESERVED = 4 +DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR' +DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { + 0: 'DP_STREAM_ENC_NO_ERROR_OCCURRED', + 1: 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', + 2: 'DP_STREAM_ENC_OVERFLOW_OCCURRED', +} +DP_STREAM_ENC_NO_ERROR_OCCURRED = 0 +DP_STREAM_ENC_UNDERFLOW_OCCURRED = 1 +DP_STREAM_ENC_OVERFLOW_OCCURRED = 2 +DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT' +DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = { + 0: 'DP_STREAM_ENC_HARDWARE', + 1: 'DP_STREAM_ENC_PROGRAMMABLE', +} +DP_STREAM_ENC_HARDWARE = 0 +DP_STREAM_ENC_PROGRAMMABLE = 1 +DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_READ_CLOCK_CONTROL' +DP_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = { + 0: 'DP_STREAM_ENC_DCCG', + 1: 'DP_STREAM_ENC_DISPLAY_PIPE', +} +DP_STREAM_ENC_DCCG = 0 +DP_STREAM_ENC_DISPLAY_PIPE = 1 +DP_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_RESET_CONTROL' +DP_STREAM_ENC_RESET_CONTROL__enumvalues = { + 0: 'DP_STREAM_ENC_NOT_RESET', + 1: 'DP_STREAM_ENC_RESET', +} +DP_STREAM_ENC_NOT_RESET = 0 +DP_STREAM_ENC_RESET = 1 +DP_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_STREAM_ACTIVE' +DP_STREAM_ENC_STREAM_ACTIVE__enumvalues = { + 0: 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', + 1: 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', +} +DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0 +DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1 +DP_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_AUDIO_MUTE' +ENUM_DP_SYM32_ENC_AUDIO_MUTE__enumvalues = { + 0: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', + 1: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', +} +DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0 +DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 1 +ENUM_DP_SYM32_ENC_AUDIO_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE' +ENUM_DP_SYM32_ENC_CONTINUOUS_MODE__enumvalues = { + 0: 'DP_SYM32_ENC_ONE_SHOT_MODE', + 1: 'DP_SYM32_ENC_CONTINUOUS_MODE', +} +DP_SYM32_ENC_ONE_SHOT_MODE = 0 +DP_SYM32_ENC_CONTINUOUS_MODE = 1 +ENUM_DP_SYM32_ENC_CONTINUOUS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_CRC_VALID' +ENUM_DP_SYM32_ENC_CRC_VALID__enumvalues = { + 0: 'DP_SYM32_ENC_CRC_NOT_VALID', + 1: 'DP_SYM32_ENC_CRC_VALID', +} +DP_SYM32_ENC_CRC_NOT_VALID = 0 +DP_SYM32_ENC_CRC_VALID = 1 +ENUM_DP_SYM32_ENC_CRC_VALID = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH' +ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH__enumvalues = { + 0: 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', + 1: 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', + 2: 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', + 3: 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', +} +DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0 +DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 1 +DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 2 +DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 3 +ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_ENABLE' +ENUM_DP_SYM32_ENC_ENABLE__enumvalues = { + 0: 'DP_SYM32_ENC_DISABLE', + 1: 'DP_SYM32_ENC_ENABLE', +} +DP_SYM32_ENC_DISABLE = 0 +DP_SYM32_ENC_ENABLE = 1 +ENUM_DP_SYM32_ENC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED' +ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', + 1: 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', +} +DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0 +DP_SYM32_ENC_GSP_DEADLINE_MISSED = 1 +ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION' +ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', + 1: 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', +} +DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0 +DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 1 +ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE' +ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', + 1: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', + 2: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', + 3: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', +} +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0 +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 1 +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 2 +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 3 +ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING' +ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', + 1: 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', +} +DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0 +DP_SYM32_ENC_GSP_TRIGGER_PENDING = 1 +ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM' +ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', + 1: 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', +} +DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0 +DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 1 +DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 2 +DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 3 +ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS' +ENUM_DP_SYM32_ENC_OVERFLOW_STATUS__enumvalues = { + 0: 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', + 1: 'DP_SYM32_ENC_OVERFLOW_OCCURRED', +} +DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0 +DP_SYM32_ENC_OVERFLOW_OCCURRED = 1 +ENUM_DP_SYM32_ENC_OVERFLOW_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_PENDING' +ENUM_DP_SYM32_ENC_PENDING__enumvalues = { + 0: 'DP_SYM32_ENC_NOT_PENDING', + 1: 'DP_SYM32_ENC_PENDING', +} +DP_SYM32_ENC_NOT_PENDING = 0 +DP_SYM32_ENC_PENDING = 1 +ENUM_DP_SYM32_ENC_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING' +ENUM_DP_SYM32_ENC_PIXEL_ENCODING__enumvalues = { + 0: 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', + 1: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', + 2: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', + 3: 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', +} +DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0 +DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 1 +DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 2 +DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 3 +ENUM_DP_SYM32_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE' +ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE__enumvalues = { + 0: 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', + 1: 'DP_SYM32_ENC_COMPRESSED_FORMAT', +} +DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0 +DP_SYM32_ENC_COMPRESSED_FORMAT = 1 +ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM' +ENUM_DP_SYM32_ENC_POWER_STATE_ENUM__enumvalues = { + 0: 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', + 1: 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', + 2: 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', + 3: 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', +} +DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0 +DP_SYM32_ENC_POWER_STATE_ENUM_LS = 1 +DP_SYM32_ENC_POWER_STATE_ENUM_DS = 2 +DP_SYM32_ENC_POWER_STATE_ENUM_SD = 3 +ENUM_DP_SYM32_ENC_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_RESET' +ENUM_DP_SYM32_ENC_RESET__enumvalues = { + 0: 'DP_SYM32_ENC_NOT_RESET', + 1: 'DP_SYM32_ENC_RESET', +} +DP_SYM32_ENC_NOT_RESET = 0 +DP_SYM32_ENC_RESET = 1 +ENUM_DP_SYM32_ENC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_SDP_PRIORITY' +ENUM_DP_SYM32_ENC_SDP_PRIORITY__enumvalues = { + 0: 'DP_SYM32_ENC_SDP_LOW_PRIORITY', + 1: 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', +} +DP_SYM32_ENC_SDP_LOW_PRIORITY = 0 +DP_SYM32_ENC_SDP_HIGH_PRIORITY = 1 +ENUM_DP_SYM32_ENC_SDP_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_SOF_REFERENCE' +ENUM_DP_SYM32_ENC_SOF_REFERENCE__enumvalues = { + 0: 'DP_SYM32_ENC_DP_SOF', + 1: 'DP_SYM32_ENC_OTG_SOF', +} +DP_SYM32_ENC_DP_SOF = 0 +DP_SYM32_ENC_OTG_SOF = 1 +ENUM_DP_SYM32_ENC_SOF_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER' +ENUM_DP_SYM32_ENC_VID_STREAM_DEFER__enumvalues = { + 0: 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', + 1: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', + 2: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', +} +DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0 +DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 1 +DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 2 +ENUM_DP_SYM32_ENC_VID_STREAM_DEFER = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT' +ENUM_DP_DPHY_SYM32_CRC_END_EVENT__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_END_LLCP', + 1: 'DP_DPHY_SYM32_CRC_END_PS_ONLY', + 2: 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', + 3: 'DP_DPHY_SYM32_CRC_END_PS_ANY', +} +DP_DPHY_SYM32_CRC_END_LLCP = 0 +DP_DPHY_SYM32_CRC_END_PS_ONLY = 1 +DP_DPHY_SYM32_CRC_END_PS_LT_SR = 2 +DP_DPHY_SYM32_CRC_END_PS_ANY = 3 +ENUM_DP_DPHY_SYM32_CRC_END_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT' +ENUM_DP_DPHY_SYM32_CRC_START_EVENT__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_START_LLCP', + 1: 'DP_DPHY_SYM32_CRC_START_PS_ONLY', + 2: 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', + 3: 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', + 4: 'DP_DPHY_SYM32_CRC_START_TP_START', +} +DP_DPHY_SYM32_CRC_START_LLCP = 0 +DP_DPHY_SYM32_CRC_START_PS_ONLY = 1 +DP_DPHY_SYM32_CRC_START_PS_LT_SR = 2 +DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 3 +DP_DPHY_SYM32_CRC_START_TP_START = 4 +ENUM_DP_DPHY_SYM32_CRC_START_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE' +ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', + 1: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', + 2: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', +} +DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0 +DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 1 +DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 2 +ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS' +ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_USE_END_EVENT', + 1: 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', +} +DP_DPHY_SYM32_CRC_USE_END_EVENT = 0 +DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 1 +ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_ENABLE' +ENUM_DP_DPHY_SYM32_ENABLE__enumvalues = { + 0: 'DP_DPHY_SYM32_DISABLE', + 1: 'DP_DPHY_SYM32_ENABLE', +} +DP_DPHY_SYM32_DISABLE = 0 +DP_DPHY_SYM32_ENABLE = 1 +ENUM_DP_DPHY_SYM32_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_MODE' +ENUM_DP_DPHY_SYM32_MODE__enumvalues = { + 0: 'DP_DPHY_SYM32_LT_TPS1', + 1: 'DP_DPHY_SYM32_LT_TPS2', + 2: 'DP_DPHY_SYM32_ACTIVE', + 3: 'DP_DPHY_SYM32_TEST', +} +DP_DPHY_SYM32_LT_TPS1 = 0 +DP_DPHY_SYM32_LT_TPS2 = 1 +DP_DPHY_SYM32_ACTIVE = 2 +DP_DPHY_SYM32_TEST = 3 +ENUM_DP_DPHY_SYM32_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_NUM_LANES' +ENUM_DP_DPHY_SYM32_NUM_LANES__enumvalues = { + 0: 'DP_DPHY_SYM32_1LANE', + 1: 'DP_DPHY_SYM32_2LANE', + 2: 'DP_DPHY_SYM32_RESERVED', + 3: 'DP_DPHY_SYM32_4LANE', +} +DP_DPHY_SYM32_1LANE = 0 +DP_DPHY_SYM32_2LANE = 1 +DP_DPHY_SYM32_RESERVED = 2 +DP_DPHY_SYM32_4LANE = 3 +ENUM_DP_DPHY_SYM32_NUM_LANES = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_OUTPUT_MODE' +ENUM_DP_DPHY_SYM32_OUTPUT_MODE__enumvalues = { + 0: 'DP_DPHY_SYM32_OUTPUT_PHY', + 1: 'DP_DPHY_SYM32_OUTPUT_DPIA', +} +DP_DPHY_SYM32_OUTPUT_PHY = 0 +DP_DPHY_SYM32_OUTPUT_DPIA = 1 +ENUM_DP_DPHY_SYM32_OUTPUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING' +ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING__enumvalues = { + 0: 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', + 1: 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', +} +DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0 +DP_DPHY_SYM32_RATE_UPDATE_PENDING = 1 +ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET' +ENUM_DP_DPHY_SYM32_RESET__enumvalues = { + 0: 'DP_DPHY_SYM32_NOT_RESET', + 1: 'DP_DPHY_SYM32_RESET', +} +DP_DPHY_SYM32_NOT_RESET = 0 +DP_DPHY_SYM32_RESET = 1 +ENUM_DP_DPHY_SYM32_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET_STATUS' +ENUM_DP_DPHY_SYM32_RESET_STATUS__enumvalues = { + 0: 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', + 1: 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', +} +DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0 +DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 1 +ENUM_DP_DPHY_SYM32_RESET_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE' +ENUM_DP_DPHY_SYM32_SAT_UPDATE__enumvalues = { + 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE', + 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', + 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', +} +DP_DPHY_SYM32_SAT_NO_UPDATE = 0 +DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 1 +DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 2 +ENUM_DP_DPHY_SYM32_SAT_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING' +ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING__enumvalues = { + 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', + 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', + 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', +} +DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0 +DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 1 +DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 2 +ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS' +ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS__enumvalues = { + 0: 'DP_DPHY_SYM32_SCHEDULER_OFF', + 1: 'DP_DPHY_SYM32_SCHEDULER_ASLEEP', + 2: 'DP_DPHY_SYM32_SCHEDULER_AWAKE', +} +DP_DPHY_SYM32_SCHEDULER_OFF = 0 +DP_DPHY_SYM32_SCHEDULER_ASLEEP = 1 +DP_DPHY_SYM32_SCHEDULER_AWAKE = 2 +ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_STATUS' +ENUM_DP_DPHY_SYM32_STATUS__enumvalues = { + 0: 'DP_DPHY_SYM32_STATUS_IDLE', + 1: 'DP_DPHY_SYM32_STATUS_ENABLED', +} +DP_DPHY_SYM32_STATUS_IDLE = 0 +DP_DPHY_SYM32_STATUS_ENABLED = 1 +ENUM_DP_DPHY_SYM32_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE' +ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE__enumvalues = { + 0: 'DP_DPHY_SYM32_STREAM_OVR_NONE', + 1: 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', + 2: 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', +} +DP_DPHY_SYM32_STREAM_OVR_NONE = 0 +DP_DPHY_SYM32_STREAM_OVR_REPLACE = 1 +DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 2 +ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE' +ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE__enumvalues = { + 0: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', + 1: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', +} +DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0 +DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 1 +ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL' +ENUM_DP_DPHY_SYM32_TP_PRBS_SEL__enumvalues = { + 0: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', + 1: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', + 2: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', + 3: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', + 4: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', + 5: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', +} +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 1 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 2 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 3 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 4 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 5 +ENUM_DP_DPHY_SYM32_TP_PRBS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_SELECT' +ENUM_DP_DPHY_SYM32_TP_SELECT__enumvalues = { + 0: 'DP_DPHY_SYM32_TP_SELECT_TPS1', + 1: 'DP_DPHY_SYM32_TP_SELECT_TPS2', + 2: 'DP_DPHY_SYM32_TP_SELECT_PRBS', + 3: 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', + 4: 'DP_DPHY_SYM32_TP_SELECT_SQUARE', +} +DP_DPHY_SYM32_TP_SELECT_TPS1 = 0 +DP_DPHY_SYM32_TP_SELECT_TPS2 = 1 +DP_DPHY_SYM32_TP_SELECT_PRBS = 2 +DP_DPHY_SYM32_TP_SELECT_CUSTOM = 3 +DP_DPHY_SYM32_TP_SELECT_SQUARE = 4 +ENUM_DP_DPHY_SYM32_TP_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'APG_AUDIO_CRC_CONTROL_CH_SEL' +APG_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { + 0: 'APG_AUDIO_CRC_CH0_SIG', + 1: 'APG_AUDIO_CRC_CH1_SIG', + 2: 'APG_AUDIO_CRC_CH2_SIG', + 3: 'APG_AUDIO_CRC_CH3_SIG', + 4: 'APG_AUDIO_CRC_CH4_SIG', + 5: 'APG_AUDIO_CRC_CH5_SIG', + 6: 'APG_AUDIO_CRC_CH6_SIG', + 7: 'APG_AUDIO_CRC_CH7_SIG', + 8: 'APG_AUDIO_CRC_RESERVED_8', + 9: 'APG_AUDIO_CRC_RESERVED_9', + 10: 'APG_AUDIO_CRC_RESERVED_10', + 11: 'APG_AUDIO_CRC_RESERVED_11', + 12: 'APG_AUDIO_CRC_RESERVED_12', + 13: 'APG_AUDIO_CRC_RESERVED_13', + 14: 'APG_AUDIO_CRC_RESERVED_14', + 15: 'APG_AUDIO_CRC_RESERVED_15', +} +APG_AUDIO_CRC_CH0_SIG = 0 +APG_AUDIO_CRC_CH1_SIG = 1 +APG_AUDIO_CRC_CH2_SIG = 2 +APG_AUDIO_CRC_CH3_SIG = 3 +APG_AUDIO_CRC_CH4_SIG = 4 +APG_AUDIO_CRC_CH5_SIG = 5 +APG_AUDIO_CRC_CH6_SIG = 6 +APG_AUDIO_CRC_CH7_SIG = 7 +APG_AUDIO_CRC_RESERVED_8 = 8 +APG_AUDIO_CRC_RESERVED_9 = 9 +APG_AUDIO_CRC_RESERVED_10 = 10 +APG_AUDIO_CRC_RESERVED_11 = 11 +APG_AUDIO_CRC_RESERVED_12 = 12 +APG_AUDIO_CRC_RESERVED_13 = 13 +APG_AUDIO_CRC_RESERVED_14 = 14 +APG_AUDIO_CRC_RESERVED_15 = 15 +APG_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_AUDIO_CRC_CONTROL_CONT' +APG_AUDIO_CRC_CONTROL_CONT__enumvalues = { + 0: 'APG_AUDIO_CRC_ONESHOT', + 1: 'APG_AUDIO_CRC_CONTINUOUS', +} +APG_AUDIO_CRC_ONESHOT = 0 +APG_AUDIO_CRC_CONTINUOUS = 1 +APG_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_ACP_TYPE' +APG_DBG_ACP_TYPE__enumvalues = { + 0: 'APG_ACP_TYPE_GENERIC_AUDIO', + 1: 'APG_ACP_TYPE_ICE60958_AUDIO', + 2: 'APG_ACP_TYPE_DVD_AUDIO', + 3: 'APG_ACP_TYPE_SUPER_AUDIO_CD', +} +APG_ACP_TYPE_GENERIC_AUDIO = 0 +APG_ACP_TYPE_ICE60958_AUDIO = 1 +APG_ACP_TYPE_DVD_AUDIO = 2 +APG_ACP_TYPE_SUPER_AUDIO_CD = 3 +APG_DBG_ACP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_AUDIO_DTO_BASE' +APG_DBG_AUDIO_DTO_BASE__enumvalues = { + 0: 'BASE_RATE_48KHZ', + 1: 'BASE_RATE_44P1KHZ', +} +BASE_RATE_48KHZ = 0 +BASE_RATE_44P1KHZ = 1 +APG_DBG_AUDIO_DTO_BASE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_AUDIO_DTO_DIV' +APG_DBG_AUDIO_DTO_DIV__enumvalues = { + 0: 'DIVISOR_BY1', + 1: 'DIVISOR_BY2_RESERVED', + 2: 'DIVISOR_BY3', + 3: 'DIVISOR_BY4_RESERVED', + 4: 'DIVISOR_BY5_RESERVED', + 5: 'DIVISOR_BY6_RESERVED', + 6: 'DIVISOR_BY7_RESERVED', + 7: 'DIVISOR_BY8_RESERVED', +} +DIVISOR_BY1 = 0 +DIVISOR_BY2_RESERVED = 1 +DIVISOR_BY3 = 2 +DIVISOR_BY4_RESERVED = 3 +DIVISOR_BY5_RESERVED = 4 +DIVISOR_BY6_RESERVED = 5 +DIVISOR_BY7_RESERVED = 6 +DIVISOR_BY8_RESERVED = 7 +APG_DBG_AUDIO_DTO_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_AUDIO_DTO_MULTI' +APG_DBG_AUDIO_DTO_MULTI__enumvalues = { + 0: 'MULTIPLE_BY1', + 1: 'MULTIPLE_BY2', + 2: 'MULTIPLE_BY3_RESERVED', + 3: 'MULTIPLE_BY4', + 4: 'MULTIPLE_RESERVED', +} +MULTIPLE_BY1 = 0 +MULTIPLE_BY2 = 1 +MULTIPLE_BY3_RESERVED = 2 +MULTIPLE_BY4 = 3 +MULTIPLE_RESERVED = 4 +APG_DBG_AUDIO_DTO_MULTI = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_MUX_SEL' +APG_DBG_MUX_SEL__enumvalues = { + 0: 'APG_FUNCTIONAL_MODE', + 1: 'APG_DEBUG_AUDIO_MODE', +} +APG_FUNCTIONAL_MODE = 0 +APG_DEBUG_AUDIO_MODE = 1 +APG_DBG_MUX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE' +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { + 0: 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', + 1: 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', +} +APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0 +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_MEM_POWER_STATE' +APG_MEM_POWER_STATE__enumvalues = { + 0: 'APG_MEM_POWER_STATE_ON', + 1: 'APG_MEM_POWER_STATE_LS', + 2: 'APG_MEM_POWER_STATE_DS', + 3: 'APG_MEM_POWER_STATE_SD', +} +APG_MEM_POWER_STATE_ON = 0 +APG_MEM_POWER_STATE_LS = 1 +APG_MEM_POWER_STATE_DS = 2 +APG_MEM_POWER_STATE_SD = 3 +APG_MEM_POWER_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_MEM_PWR_DIS_CTRL' +APG_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'APG_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'APG_MEM_DISABLE_MEM_PWR_CTRL', +} +APG_MEM_ENABLE_MEM_PWR_CTRL = 0 +APG_MEM_DISABLE_MEM_PWR_CTRL = 1 +APG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_MEM_PWR_FORCE_CTRL' +APG_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'APG_MEM_NO_FORCE_REQUEST', + 1: 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', +} +APG_MEM_NO_FORCE_REQUEST = 0 +APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 +APG_MEM_FORCE_SHUT_DOWN_REQUEST = 3 +APG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_PACKET_CONTROL_ACP_SOURCE' +APG_PACKET_CONTROL_ACP_SOURCE__enumvalues = { + 0: 'APG_ACP_SOURCE_NO_OVERRIDE', + 1: 'APG_ACP_OVERRIDE', +} +APG_ACP_SOURCE_NO_OVERRIDE = 0 +APG_ACP_OVERRIDE = 1 +APG_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE' +APG_PACKET_CONTROL_AUDIO_INFO_SOURCE__enumvalues = { + 0: 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', + 1: 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', +} +APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0 +APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 1 +APG_PACKET_CONTROL_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_RAMP_CONTROL_SIGN' +APG_RAMP_CONTROL_SIGN__enumvalues = { + 0: 'APG_RAMP_SIGNED', + 1: 'APG_RAMP_UNSIGNED', +} +APG_RAMP_SIGNED = 0 +APG_RAMP_UNSIGNED = 1 +APG_RAMP_CONTROL_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', +} +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { + 0: 'DCIO_TEST_CLK_SEL_DISPCLK', + 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', + 2: 'DCIO_TEST_CLK_SEL_SOCCLK', +} +DCIO_TEST_CLK_SEL_DISPCLK = 0 +DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 +DCIO_TEST_CLK_SEL_SOCCLK = 2 +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { + 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', +} +DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 +DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL' +DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = { + 0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', + 1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', + 2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', + 3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', + 4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', + 5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', + 6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', + 7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', +} +DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0 +DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1 +DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2 +DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3 +DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4 +DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5 +DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6 +DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7 +DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL' +DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = { + 0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', + 1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', + 2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', + 3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', +} +DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0 +DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1 +DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2 +DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 3 +DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' +DCIO_DCRXPHY_SOFT_RESET__enumvalues = { + 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', + 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', +} +DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 +DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 +DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICA_SEL' +DCIO_DC_GENERICA_SEL__enumvalues = { + 1: 'DCIO_GENERICA_SEL_STEREOSYNC', + 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', + 11: 'DCIO_GENERICA_SEL_SYNCEN', +} +DCIO_GENERICA_SEL_STEREOSYNC = 1 +DCIO_GENERICA_SEL_GENERICA_DCCG = 10 +DCIO_GENERICA_SEL_SYNCEN = 11 +DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICB_SEL' +DCIO_DC_GENERICB_SEL__enumvalues = { + 1: 'DCIO_GENERICB_SEL_STEREOSYNC', + 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', + 11: 'DCIO_GENERICB_SEL_SYNCEN', +} +DCIO_GENERICB_SEL_STEREOSYNC = 1 +DCIO_GENERICB_SEL_GENERICB_DCCG = 10 +DCIO_GENERICB_SEL_SYNCEN = 11 +DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', +} +DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 +DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 +DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 +DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 +DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 +DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 +DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_CLK', +} +DCIO_UNIPHYA_FBDIV_CLK = 0 +DCIO_UNIPHYB_FBDIV_CLK = 1 +DCIO_UNIPHYC_FBDIV_CLK = 2 +DCIO_UNIPHYD_FBDIV_CLK = 3 +DCIO_UNIPHYE_FBDIV_CLK = 4 +DCIO_UNIPHYF_FBDIV_CLK = 5 +DCIO_UNIPHYG_FBDIV_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', +} +DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 +DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 +DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 +DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 +DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 +DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 +DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', + 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', + 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', + 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', + 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', + 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', + 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', +} +DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 +DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 +DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 +DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 +DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 +DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 +DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE' +DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = { + 0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', + 1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', +} +DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0 +DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1 +DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' +DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { + 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', +} +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 2 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 3 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 4 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 5 +DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' +DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { + 0: 'DCIO_GPU_TIMER_START_0_END_27', + 1: 'DCIO_GPU_TIMER_START_1_END_28', + 2: 'DCIO_GPU_TIMER_START_2_END_29', + 3: 'DCIO_GPU_TIMER_START_3_END_30', + 4: 'DCIO_GPU_TIMER_START_4_END_31', + 5: 'DCIO_GPU_TIMER_START_6_END_33', + 6: 'DCIO_GPU_TIMER_START_8_END_35', + 7: 'DCIO_GPU_TIMER_START_10_END_37', +} +DCIO_GPU_TIMER_START_0_END_27 = 0 +DCIO_GPU_TIMER_START_1_END_28 = 1 +DCIO_GPU_TIMER_START_2_END_29 = 2 +DCIO_GPU_TIMER_START_3_END_30 = 3 +DCIO_GPU_TIMER_START_4_END_31 = 4 +DCIO_GPU_TIMER_START_6_END_33 = 5 +DCIO_GPU_TIMER_START_8_END_35 = 6 +DCIO_GPU_TIMER_START_10_END_37 = 7 +DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', +} +DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 +DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DIO_EXT_VSYNC_MASK' +DCIO_DIO_EXT_VSYNC_MASK__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MASK_NONE', + 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', + 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', + 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', + 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', + 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', + 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', + 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', +} +DCIO_EXT_VSYNC_MASK_NONE = 0 +DCIO_EXT_VSYNC_MASK_PIPE0 = 1 +DCIO_EXT_VSYNC_MASK_PIPE1 = 2 +DCIO_EXT_VSYNC_MASK_PIPE2 = 3 +DCIO_EXT_VSYNC_MASK_PIPE3 = 4 +DCIO_EXT_VSYNC_MASK_PIPE4 = 5 +DCIO_EXT_VSYNC_MASK_PIPE5 = 6 +DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 +DCIO_DIO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DIO_OTG_EXT_VSYNC_MUX' +DCIO_DIO_OTG_EXT_VSYNC_MUX__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 1: 'DCIO_EXT_VSYNC_MUX_OTG0', + 2: 'DCIO_EXT_VSYNC_MUX_OTG1', + 3: 'DCIO_EXT_VSYNC_MUX_OTG2', + 4: 'DCIO_EXT_VSYNC_MUX_OTG3', + 5: 'DCIO_EXT_VSYNC_MUX_OTG4', + 6: 'DCIO_EXT_VSYNC_MUX_OTG5', + 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', +} +DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 +DCIO_EXT_VSYNC_MUX_OTG0 = 1 +DCIO_EXT_VSYNC_MUX_OTG1 = 2 +DCIO_EXT_VSYNC_MUX_OTG2 = 3 +DCIO_EXT_VSYNC_MUX_OTG3 = 4 +DCIO_EXT_VSYNC_MUX_OTG4 = 5 +DCIO_EXT_VSYNC_MUX_OTG5 = 6 +DCIO_EXT_VSYNC_MUX_GENERICB = 7 +DCIO_DIO_OTG_EXT_VSYNC_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' +DCIO_DPCS_INTERRUPT_MASK__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_DISABLE', + 1: 'DCIO_DPCS_INTERRUPT_ENABLE', +} +DCIO_DPCS_INTERRUPT_DISABLE = 0 +DCIO_DPCS_INTERRUPT_ENABLE = 1 +DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' +DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', +} +DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 +DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 +DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' +DCIO_GENLK_CLK_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', + 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', +} +DCIO_GENLK_CLK_GSL_MASK_NO = 0 +DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 +DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 +DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' +DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', +} +DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 +DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 +DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 +DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL_SEL' +DCIO_GSL_SEL__enumvalues = { + 0: 'DCIO_GSL_SEL_GROUP_0', + 1: 'DCIO_GSL_SEL_GROUP_1', + 2: 'DCIO_GSL_SEL_GROUP_2', +} +DCIO_GSL_SEL_GROUP_0 = 0 +DCIO_GSL_SEL_GROUP_1 = 1 +DCIO_GSL_SEL_GROUP_2 = 2 +DCIO_GSL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_PHY_HPO_ENC_SRC_SEL' +DCIO_PHY_HPO_ENC_SRC_SEL__enumvalues = { + 0: 'HPO_SRC0', + 1: 'HPO_SRC_RESERVED', +} +HPO_SRC0 = 0 +HPO_SRC_RESERVED = 1 +DCIO_PHY_HPO_ENC_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' +DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' +DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', +} +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' +DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { + 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', +} +DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 +DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 +DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', +} +DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 +DCIO_UNIPHY_CHANNEL_INVERTED = 1 +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { + 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', + 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', +} +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_ALL_PWR_OK' +DCIOCHIP_AUX_ALL_PWR_OK__enumvalues = { + 0: 'DCIOCHIP_AUX_ALL_PWR_OK_0', + 1: 'DCIOCHIP_AUX_ALL_PWR_OK_1', +} +DCIOCHIP_AUX_ALL_PWR_OK_0 = 0 +DCIOCHIP_AUX_ALL_PWR_OK_1 = 1 +DCIOCHIP_AUX_ALL_PWR_OK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL0P9' +DCIOCHIP_AUX_CSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', +} +DCIOCHIP_AUX_CSEL_DEC1P0 = 0 +DCIOCHIP_AUX_CSEL_DEC0P9 = 1 +DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL1P1' +DCIOCHIP_AUX_CSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_INC1P0', + 1: 'DCIOCHIP_AUX_CSEL_INC1P1', +} +DCIOCHIP_AUX_CSEL_INC1P0 = 0 +DCIOCHIP_AUX_CSEL_INC1P1 = 1 +DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' +DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { + 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', + 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', +} +DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 +DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 +DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_HYS_TUNE' +DCIOCHIP_AUX_HYS_TUNE__enumvalues = { + 0: 'DCIOCHIP_AUX_HYS_TUNE_0', + 1: 'DCIOCHIP_AUX_HYS_TUNE_1', + 2: 'DCIOCHIP_AUX_HYS_TUNE_2', + 3: 'DCIOCHIP_AUX_HYS_TUNE_3', +} +DCIOCHIP_AUX_HYS_TUNE_0 = 0 +DCIOCHIP_AUX_HYS_TUNE_1 = 1 +DCIOCHIP_AUX_HYS_TUNE_2 = 2 +DCIOCHIP_AUX_HYS_TUNE_3 = 3 +DCIOCHIP_AUX_HYS_TUNE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RECEIVER_SEL' +DCIOCHIP_AUX_RECEIVER_SEL__enumvalues = { + 0: 'DCIOCHIP_AUX_RECEIVER_SEL_0', + 1: 'DCIOCHIP_AUX_RECEIVER_SEL_1', + 2: 'DCIOCHIP_AUX_RECEIVER_SEL_2', + 3: 'DCIOCHIP_AUX_RECEIVER_SEL_3', +} +DCIOCHIP_AUX_RECEIVER_SEL_0 = 0 +DCIOCHIP_AUX_RECEIVER_SEL_1 = 1 +DCIOCHIP_AUX_RECEIVER_SEL_2 = 2 +DCIOCHIP_AUX_RECEIVER_SEL_3 = 3 +DCIOCHIP_AUX_RECEIVER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL0P9' +DCIOCHIP_AUX_RSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', +} +DCIOCHIP_AUX_RSEL_DEC1P0 = 0 +DCIOCHIP_AUX_RSEL_DEC0P9 = 1 +DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL1P1' +DCIOCHIP_AUX_RSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_INC1P0', + 1: 'DCIOCHIP_AUX_RSEL_INC1P1', +} +DCIOCHIP_AUX_RSEL_INC1P0 = 0 +DCIOCHIP_AUX_RSEL_INC1P1 = 1 +DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_SPIKESEL' +DCIOCHIP_AUX_SPIKESEL__enumvalues = { + 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', + 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', +} +DCIOCHIP_AUX_SPIKESEL_50NS = 0 +DCIOCHIP_AUX_SPIKESEL_10NS = 1 +DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_VOD_TUNE' +DCIOCHIP_AUX_VOD_TUNE__enumvalues = { + 0: 'DCIOCHIP_AUX_VOD_TUNE_0', + 1: 'DCIOCHIP_AUX_VOD_TUNE_1', + 2: 'DCIOCHIP_AUX_VOD_TUNE_2', + 3: 'DCIOCHIP_AUX_VOD_TUNE_3', +} +DCIOCHIP_AUX_VOD_TUNE_0 = 0 +DCIOCHIP_AUX_VOD_TUNE_1 = 1 +DCIOCHIP_AUX_VOD_TUNE_2 = 2 +DCIOCHIP_AUX_VOD_TUNE_3 = 3 +DCIOCHIP_AUX_VOD_TUNE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_MASK_EN' +DCIOCHIP_GPIO_MASK_EN__enumvalues = { + 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', +} +DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 +DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 +DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_HPD_SEL' +DCIOCHIP_HPD_SEL__enumvalues = { + 0: 'DCIOCHIP_HPD_SEL_ASYNC', + 1: 'DCIOCHIP_HPD_SEL_CLOCKED', +} +DCIOCHIP_HPD_SEL_ASYNC = 0 +DCIOCHIP_HPD_SEL_CLOCKED = 1 +DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_COMPSEL' +DCIOCHIP_I2C_COMPSEL__enumvalues = { + 0: 'DCIOCHIP_I2C_REC_SCHMIT', + 1: 'DCIOCHIP_I2C_REC_COMPARATOR', +} +DCIOCHIP_I2C_REC_SCHMIT = 0 +DCIOCHIP_I2C_REC_COMPARATOR = 1 +DCIOCHIP_I2C_COMPSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_FALLSLEWSEL' +DCIOCHIP_I2C_FALLSLEWSEL__enumvalues = { + 0: 'DCIOCHIP_I2C_FALLSLEWSEL_00', + 1: 'DCIOCHIP_I2C_FALLSLEWSEL_01', + 2: 'DCIOCHIP_I2C_FALLSLEWSEL_10', + 3: 'DCIOCHIP_I2C_FALLSLEWSEL_11', +} +DCIOCHIP_I2C_FALLSLEWSEL_00 = 0 +DCIOCHIP_I2C_FALLSLEWSEL_01 = 1 +DCIOCHIP_I2C_FALLSLEWSEL_10 = 2 +DCIOCHIP_I2C_FALLSLEWSEL_11 = 3 +DCIOCHIP_I2C_FALLSLEWSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_RECEIVER_SEL' +DCIOCHIP_I2C_RECEIVER_SEL__enumvalues = { + 0: 'DCIOCHIP_I2C_RECEIVER_SEL_0', + 1: 'DCIOCHIP_I2C_RECEIVER_SEL_1', + 2: 'DCIOCHIP_I2C_RECEIVER_SEL_2', + 3: 'DCIOCHIP_I2C_RECEIVER_SEL_3', +} +DCIOCHIP_I2C_RECEIVER_SEL_0 = 0 +DCIOCHIP_I2C_RECEIVER_SEL_1 = 1 +DCIOCHIP_I2C_RECEIVER_SEL_2 = 2 +DCIOCHIP_I2C_RECEIVER_SEL_3 = 3 +DCIOCHIP_I2C_RECEIVER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_VPH_1V2_EN' +DCIOCHIP_I2C_VPH_1V2_EN__enumvalues = { + 0: 'DCIOCHIP_I2C_VPH_1V2_EN_0', + 1: 'DCIOCHIP_I2C_VPH_1V2_EN_1', +} +DCIOCHIP_I2C_VPH_1V2_EN_0 = 0 +DCIOCHIP_I2C_VPH_1V2_EN_1 = 1 +DCIOCHIP_I2C_VPH_1V2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_INVERT' +DCIOCHIP_INVERT__enumvalues = { + 0: 'DCIOCHIP_POL_NON_INVERT', + 1: 'DCIOCHIP_POL_INVERT', +} +DCIOCHIP_POL_NON_INVERT = 0 +DCIOCHIP_POL_INVERT = 1 +DCIOCHIP_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK' +DCIOCHIP_MASK__enumvalues = { + 0: 'DCIOCHIP_MASK_DISABLE', + 1: 'DCIOCHIP_MASK_ENABLE', +} +DCIOCHIP_MASK_DISABLE = 0 +DCIOCHIP_MASK_ENABLE = 1 +DCIOCHIP_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PAD_MODE' +DCIOCHIP_PAD_MODE__enumvalues = { + 0: 'DCIOCHIP_PAD_MODE_DDC', + 1: 'DCIOCHIP_PAD_MODE_DP', +} +DCIOCHIP_PAD_MODE_DDC = 0 +DCIOCHIP_PAD_MODE_DP = 1 +DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PD_EN' +DCIOCHIP_PD_EN__enumvalues = { + 0: 'DCIOCHIP_PD_EN_NOTALLOW', + 1: 'DCIOCHIP_PD_EN_ALLOW', +} +DCIOCHIP_PD_EN_NOTALLOW = 0 +DCIOCHIP_PD_EN_ALLOW = 1 +DCIOCHIP_PD_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' +DCIOCHIP_REF_27_SRC_SEL__enumvalues = { + 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', + 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', +} +DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 +DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 +DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { + 0: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 1: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', +} +PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 +PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN' +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', + 1: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', +} +PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0 +PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 1 +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT' +PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = { + 0: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', + 1: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', + 2: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', + 3: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', +} +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0 +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1 +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2 +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3 +PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN' +PWRSEQ_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_DISABLE', + 1: 'PWRSEQ_BL_PWM_ENABLE', +} +PWRSEQ_BL_PWM_DISABLE = 0 +PWRSEQ_BL_PWM_ENABLE = 1 +PWRSEQ_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' +PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', + 1: 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', +} +PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0 +PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 1 +PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 1: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', +} +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 1: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', +} +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_REG_LOCK' +PWRSEQ_BL_PWM_GRP1_REG_LOCK__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', + 1: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', +} +PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 +PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 +PWRSEQ_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START' +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 1: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', +} +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_GPIO_MASK_EN' +PWRSEQ_GPIO_MASK_EN__enumvalues = { + 0: 'PWRSEQ_GPIO_MASK_EN_HARDWARE', + 1: 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', +} +PWRSEQ_GPIO_MASK_EN_HARDWARE = 0 +PWRSEQ_GPIO_MASK_EN_SOFTWARE = 1 +PWRSEQ_GPIO_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON__enumvalues = { + 0: 'PWRSEQ_PANEL_BLON_OFF', + 1: 'PWRSEQ_PANEL_BLON_ON', +} +PWRSEQ_PANEL_BLON_OFF = 0 +PWRSEQ_PANEL_BLON_ON = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL__enumvalues = { + 0: 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', + 1: 'PWRSEQ_PANEL_BLON_POL_INVERT', +} +PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0 +PWRSEQ_PANEL_BLON_POL_INVERT = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON__enumvalues = { + 0: 'PWRSEQ_PANEL_DIGON_OFF', + 1: 'PWRSEQ_PANEL_DIGON_ON', +} +PWRSEQ_PANEL_DIGON_OFF = 0 +PWRSEQ_PANEL_DIGON_ON = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL__enumvalues = { + 0: 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', + 1: 'PWRSEQ_PANEL_DIGON_POL_INVERT', +} +PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0 +PWRSEQ_PANEL_DIGON_POL_INVERT = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL__enumvalues = { + 0: 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', + 1: 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', +} +PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0 +PWRSEQ_PANEL_SYNCEN_POL_INVERT = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE' +PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { + 0: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', + 1: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', +} +PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0 +PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN' +PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN__enumvalues = { + 0: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', + 1: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', +} +PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0 +PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 1 +PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_CORB_SIZE' +AZ_CORB_SIZE__enumvalues = { + 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_CORB_SIZE_256ENTRIES', + 3: 'AZ_CORB_SIZE_RESERVED', +} +AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 +AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 +AZ_CORB_SIZE_256ENTRIES = 2 +AZ_CORB_SIZE_RESERVED = 3 +AZ_CORB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_GLOBAL_CAPABILITIES' +AZ_GLOBAL_CAPABILITIES__enumvalues = { + 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', +} +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 +AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_SIZE' +AZ_RIRB_SIZE__enumvalues = { + 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_RIRB_SIZE_256ENTRIES', + 3: 'AZ_RIRB_SIZE_UNDEFINED', +} +AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 +AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 +AZ_RIRB_SIZE_256ENTRIES = 2 +AZ_RIRB_SIZE_UNDEFINED = 3 +AZ_RIRB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' +AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { + 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', + 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', +} +AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 +AZ_RIRB_WRITE_POINTER_DO_RESET = 1 +AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_STATE_CHANGE_STATUS' +AZ_STATE_CHANGE_STATUS__enumvalues = { + 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', +} +AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 +AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 +AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'CORB_READ_POINTER_RESET' +CORB_READ_POINTER_RESET__enumvalues = { + 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', +} +CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 +CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 +CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { + 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', +} +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { + 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', + 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', +} +ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 +ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' +GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { + 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', +} +CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 +CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 +GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' +GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { + 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', + 1: 'FLUSH_CONTROL_FLUSH_STARTED', +} +FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 +FLUSH_CONTROL_FLUSH_STARTED = 1 +GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' +GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { + 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', +} +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 +GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_0_SYNCHRONIZATION' +STREAM_0_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_10_SYNCHRONIZATION' +STREAM_10_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_11_SYNCHRONIZATION' +STREAM_11_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_12_SYNCHRONIZATION' +STREAM_12_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_13_SYNCHRONIZATION' +STREAM_13_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_14_SYNCHRONIZATION' +STREAM_14_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_15_SYNCHRONIZATION' +STREAM_15_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_1_SYNCHRONIZATION' +STREAM_1_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_2_SYNCHRONIZATION' +STREAM_2_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_3_SYNCHRONIZATION' +STREAM_3_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_4_SYNCHRONIZATION' +STREAM_4_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_5_SYNCHRONIZATION' +STREAM_5_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_6_SYNCHRONIZATION' +STREAM_6_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_7_SYNCHRONIZATION' +STREAM_7_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_8_SYNCHRONIZATION' +STREAM_8_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_9_SYNCHRONIZATION' +STREAM_9_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE' +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', + 2: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', + 3: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', + 4: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', + 5: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', + 6: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', + 7: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', + 8: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', + 9: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', + 10: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', + 11: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', + 12: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', + 13: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', + 14: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', + 15: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', +} +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 1 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 2 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 3 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 4 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 5 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 6 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 7 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 8 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 9 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 10 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 11 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 12 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 13 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 14 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 15 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { + 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', +} +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_DIS_CTRL' +MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'ENABLE_MEM_PWR_CTRL', + 1: 'DISABLE_MEM_PWR_CTRL', +} +ENABLE_MEM_PWR_CTRL = 0 +DISABLE_MEM_PWR_CTRL = 1 +MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL' +MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'NO_FORCE_REQUEST', + 1: 'FORCE_LIGHT_SLEEP_REQUEST', + 2: 'FORCE_DEEP_SLEEP_REQUEST', + 3: 'FORCE_SHUT_DOWN_REQUEST', +} +NO_FORCE_REQUEST = 0 +FORCE_LIGHT_SLEEP_REQUEST = 1 +FORCE_DEEP_SLEEP_REQUEST = 2 +FORCE_SHUT_DOWN_REQUEST = 3 +MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL2' +MEM_PWR_FORCE_CTRL2__enumvalues = { + 0: 'NO_FORCE_REQ', + 1: 'FORCE_LIGHT_SLEEP_REQ', +} +NO_FORCE_REQ = 0 +FORCE_LIGHT_SLEEP_REQ = 1 +MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL' +MEM_PWR_SEL_CTRL__enumvalues = { + 0: 'DYNAMIC_SHUT_DOWN_ENABLE', + 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', + 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', +} +DYNAMIC_SHUT_DOWN_ENABLE = 0 +DYNAMIC_DEEP_SLEEP_ENABLE = 1 +DYNAMIC_LIGHT_SLEEP_ENABLE = 2 +MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL2' +MEM_PWR_SEL_CTRL2__enumvalues = { + 0: 'DYNAMIC_DEEP_SLEEP_EN', + 1: 'DYNAMIC_LIGHT_SLEEP_EN', +} +DYNAMIC_DEEP_SLEEP_EN = 0 +DYNAMIC_LIGHT_SLEEP_EN = 1 +MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { + 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', +} +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' +AZ_LATENCY_COUNTER_CONTROL__enumvalues = { + 0: 'AZ_LATENCY_COUNTER_NO_RESET', + 1: 'AZ_LATENCY_COUNTER_RESET_DONE', +} +AZ_LATENCY_COUNTER_NO_RESET = 0 +AZ_LATENCY_COUNTER_RESET_DONE = 1 +AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', +} +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_BITS_PER_COMPONENT_ENUM' +DSCC_BITS_PER_COMPONENT_ENUM__enumvalues = { + 8: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 10: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 12: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', +} +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 +DSCC_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_DSC_VERSION_MAJOR_ENUM' +DSCC_DSC_VERSION_MAJOR_ENUM__enumvalues = { + 1: 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', +} +DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 1 +DSCC_DSC_VERSION_MAJOR_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_DSC_VERSION_MINOR_ENUM' +DSCC_DSC_VERSION_MINOR_ENUM__enumvalues = { + 1: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', + 2: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', +} +DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 1 +DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 2 +DSCC_DSC_VERSION_MINOR_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_ENABLE_ENUM' +DSCC_ENABLE_ENUM__enumvalues = { + 0: 'DSCC_ENABLE_ENUM_DISABLED', + 1: 'DSCC_ENABLE_ENUM_ENABLED', +} +DSCC_ENABLE_ENUM_DISABLED = 0 +DSCC_ENABLE_ENUM_ENABLED = 1 +DSCC_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_ICH_RESET_ENUM' +DSCC_ICH_RESET_ENUM__enumvalues = { + 1: 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', + 2: 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', + 4: 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', + 8: 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', +} +DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 1 +DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 2 +DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 4 +DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 8 +DSCC_ICH_RESET_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_LINEBUF_DEPTH_ENUM' +DSCC_LINEBUF_DEPTH_ENUM__enumvalues = { + 8: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', + 9: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', + 10: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', + 11: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', + 12: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', + 13: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', +} +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 8 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 9 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 10 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 11 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 12 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 13 +DSCC_LINEBUF_DEPTH_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_MEM_PWR_DIS_ENUM' +DSCC_MEM_PWR_DIS_ENUM__enumvalues = { + 0: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', + 1: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', +} +DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0 +DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 1 +DSCC_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_MEM_PWR_FORCE_ENUM' +DSCC_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', + 1: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', +} +DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 2 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 3 +DSCC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'POWER_STATE_ENUM' +POWER_STATE_ENUM__enumvalues = { + 0: 'POWER_STATE_ENUM_ON', + 1: 'POWER_STATE_ENUM_LS', + 2: 'POWER_STATE_ENUM_DS', + 3: 'POWER_STATE_ENUM_SD', +} +POWER_STATE_ENUM_ON = 0 +POWER_STATE_ENUM_LS = 1 +POWER_STATE_ENUM_DS = 2 +POWER_STATE_ENUM_SD = 3 +POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_BITS_PER_COMPONENT_ENUM' +DSCCIF_BITS_PER_COMPONENT_ENUM__enumvalues = { + 8: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 10: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 12: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', +} +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 +DSCCIF_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_ENABLE_ENUM' +DSCCIF_ENABLE_ENUM__enumvalues = { + 0: 'DSCCIF_ENABLE_ENUM_DISABLED', + 1: 'DSCCIF_ENABLE_ENUM_ENABLED', +} +DSCCIF_ENABLE_ENUM_DISABLED = 0 +DSCCIF_ENABLE_ENUM_ENABLED = 1 +DSCCIF_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM' +DSCCIF_INPUT_PIXEL_FORMAT_ENUM__enumvalues = { + 0: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', + 1: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', + 2: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', + 3: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', + 4: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', +} +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 1 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 2 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 3 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 4 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_GATING_DISABLE_ENUM' +CLOCK_GATING_DISABLE_ENUM__enumvalues = { + 0: 'CLOCK_GATING_DISABLE_ENUM_ENABLED', + 1: 'CLOCK_GATING_DISABLE_ENUM_DISABLED', +} +CLOCK_GATING_DISABLE_ENUM_ENABLED = 0 +CLOCK_GATING_DISABLE_ENUM_DISABLED = 1 +CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE_ENUM' +ENABLE_ENUM__enumvalues = { + 0: 'ENABLE_ENUM_DISABLED', + 1: 'ENABLE_ENUM_ENABLED', +} +ENABLE_ENUM_DISABLED = 0 +ENABLE_ENUM_ENABLED = 1 +ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLOCK_MUX_SELECT_ENUM' +TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = { + 0: 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', + 1: 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', + 2: 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', + 3: 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', + 4: 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', + 5: 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', + 6: 'TEST_CLOCK_MUX_SELECT_DSCCLK_D', +} +TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0 +TEST_CLOCK_MUX_SELECT_DISPCLK_G = 1 +TEST_CLOCK_MUX_SELECT_DISPCLK_R = 2 +TEST_CLOCK_MUX_SELECT_DSCCLK_P = 3 +TEST_CLOCK_MUX_SELECT_DSCCLK_G = 4 +TEST_CLOCK_MUX_SELECT_DSCCLK_R = 5 +TEST_CLOCK_MUX_SELECT_DSCCLK_D = 6 +TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_CRC_CONT_EN_ENUM' +DWB_CRC_CONT_EN_ENUM__enumvalues = { + 0: 'DWB_CRC_CONT_EN_ONE_SHOT', + 1: 'DWB_CRC_CONT_EN_CONT', +} +DWB_CRC_CONT_EN_ONE_SHOT = 0 +DWB_CRC_CONT_EN_CONT = 1 +DWB_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_CRC_SRC_SEL_ENUM' +DWB_CRC_SRC_SEL_ENUM__enumvalues = { + 0: 'DWB_CRC_SRC_SEL_DWB_IN', + 1: 'DWB_CRC_SRC_SEL_OGAM_OUT', + 2: 'DWB_CRC_SRC_SEL_DWB_OUT', +} +DWB_CRC_SRC_SEL_DWB_IN = 0 +DWB_CRC_SRC_SEL_OGAM_OUT = 1 +DWB_CRC_SRC_SEL_DWB_OUT = 2 +DWB_CRC_SRC_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM' +DWB_DATA_OVERFLOW_INT_TYPE_ENUM__enumvalues = { + 0: 'DWB_DATA_OVERFLOW_INT_TYPE_0', + 1: 'DWB_DATA_OVERFLOW_INT_TYPE_1', +} +DWB_DATA_OVERFLOW_INT_TYPE_0 = 0 +DWB_DATA_OVERFLOW_INT_TYPE_1 = 1 +DWB_DATA_OVERFLOW_INT_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DATA_OVERFLOW_TYPE_ENUM' +DWB_DATA_OVERFLOW_TYPE_ENUM__enumvalues = { + 0: 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', + 1: 'DWB_DATA_OVERFLOW_TYPE_BUFFER', + 2: 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', + 3: 'DWB_DATA_OVERFLOW_TYPE_VREADY', +} +DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0 +DWB_DATA_OVERFLOW_TYPE_BUFFER = 1 +DWB_DATA_OVERFLOW_TYPE_VUPDATE = 2 +DWB_DATA_OVERFLOW_TYPE_VREADY = 3 +DWB_DATA_OVERFLOW_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DEBUG_SEL_ENUM' +DWB_DEBUG_SEL_ENUM__enumvalues = { + 0: 'DWB_DEBUG_SEL_FC', + 1: 'DWB_DEBUG_SEL_RESERVED', + 2: 'DWB_DEBUG_SEL_DWBCP', + 3: 'DWB_DEBUG_SEL_PERFMON', +} +DWB_DEBUG_SEL_FC = 0 +DWB_DEBUG_SEL_RESERVED = 1 +DWB_DEBUG_SEL_DWBCP = 2 +DWB_DEBUG_SEL_PERFMON = 3 +DWB_DEBUG_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_MEM_PWR_FORCE_ENUM' +DWB_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DWB_MEM_PWR_FORCE_DIS', + 1: 'DWB_MEM_PWR_FORCE_LS', + 2: 'DWB_MEM_PWR_FORCE_DS', + 3: 'DWB_MEM_PWR_FORCE_SD', +} +DWB_MEM_PWR_FORCE_DIS = 0 +DWB_MEM_PWR_FORCE_LS = 1 +DWB_MEM_PWR_FORCE_DS = 2 +DWB_MEM_PWR_FORCE_SD = 3 +DWB_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_MEM_PWR_STATE_ENUM' +DWB_MEM_PWR_STATE_ENUM__enumvalues = { + 0: 'DWB_MEM_PWR_STATE_ON', + 1: 'DWB_MEM_PWR_STATE_LS', + 2: 'DWB_MEM_PWR_STATE_DS', + 3: 'DWB_MEM_PWR_STATE_SD', +} +DWB_MEM_PWR_STATE_ON = 0 +DWB_MEM_PWR_STATE_LS = 1 +DWB_MEM_PWR_STATE_DS = 2 +DWB_MEM_PWR_STATE_SD = 3 +DWB_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_TEST_CLK_SEL_ENUM' +DWB_TEST_CLK_SEL_ENUM__enumvalues = { + 0: 'DWB_TEST_CLK_SEL_R', + 1: 'DWB_TEST_CLK_SEL_G', + 2: 'DWB_TEST_CLK_SEL_P', +} +DWB_TEST_CLK_SEL_R = 0 +DWB_TEST_CLK_SEL_G = 1 +DWB_TEST_CLK_SEL_P = 2 +DWB_TEST_CLK_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FC_EYE_SELECTION_ENUM' +FC_EYE_SELECTION_ENUM__enumvalues = { + 0: 'FC_EYE_SELECTION_STEREO_DIS', + 1: 'FC_EYE_SELECTION_LEFT_EYE', + 2: 'FC_EYE_SELECTION_RIGHT_EYE', +} +FC_EYE_SELECTION_STEREO_DIS = 0 +FC_EYE_SELECTION_LEFT_EYE = 1 +FC_EYE_SELECTION_RIGHT_EYE = 2 +FC_EYE_SELECTION_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FC_FRAME_CAPTURE_RATE_ENUM' +FC_FRAME_CAPTURE_RATE_ENUM__enumvalues = { + 0: 'FC_FRAME_CAPTURE_RATE_FULL', + 1: 'FC_FRAME_CAPTURE_RATE_HALF', + 2: 'FC_FRAME_CAPTURE_RATE_THIRD', + 3: 'FC_FRAME_CAPTURE_RATE_QUARTER', +} +FC_FRAME_CAPTURE_RATE_FULL = 0 +FC_FRAME_CAPTURE_RATE_HALF = 1 +FC_FRAME_CAPTURE_RATE_THIRD = 2 +FC_FRAME_CAPTURE_RATE_QUARTER = 3 +FC_FRAME_CAPTURE_RATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FC_STEREO_EYE_POLARITY_ENUM' +FC_STEREO_EYE_POLARITY_ENUM__enumvalues = { + 0: 'FC_STEREO_EYE_POLARITY_LEFT', + 1: 'FC_STEREO_EYE_POLARITY_RIGHT', +} +FC_STEREO_EYE_POLARITY_LEFT = 0 +FC_STEREO_EYE_POLARITY_RIGHT = 1 +FC_STEREO_EYE_POLARITY_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM' +DWB_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { + 0: 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', + 1: 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', +} +DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 +DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 +DWB_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_GAMUT_REMAP_MODE_ENUM' +DWB_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'DWB_GAMUT_REMAP_MODE_BYPASS', + 1: 'DWB_GAMUT_REMAP_MODE_COEF_A', + 2: 'DWB_GAMUT_REMAP_MODE_COEF_B', + 3: 'DWB_GAMUT_REMAP_MODE_RESERVED', +} +DWB_GAMUT_REMAP_MODE_BYPASS = 0 +DWB_GAMUT_REMAP_MODE_COEF_A = 1 +DWB_GAMUT_REMAP_MODE_COEF_B = 2 +DWB_GAMUT_REMAP_MODE_RESERVED = 3 +DWB_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_LUT_NUM_SEG' +DWB_LUT_NUM_SEG__enumvalues = { + 0: 'DWB_SEGMENTS_1', + 1: 'DWB_SEGMENTS_2', + 2: 'DWB_SEGMENTS_4', + 3: 'DWB_SEGMENTS_8', + 4: 'DWB_SEGMENTS_16', + 5: 'DWB_SEGMENTS_32', + 6: 'DWB_SEGMENTS_64', + 7: 'DWB_SEGMENTS_128', +} +DWB_SEGMENTS_1 = 0 +DWB_SEGMENTS_2 = 1 +DWB_SEGMENTS_4 = 2 +DWB_SEGMENTS_8 = 3 +DWB_SEGMENTS_16 = 4 +DWB_SEGMENTS_32 = 5 +DWB_SEGMENTS_64 = 6 +DWB_SEGMENTS_128 = 7 +DWB_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_CONFIG_MODE_ENUM' +DWB_OGAM_LUT_CONFIG_MODE_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', + 1: 'DWB_OGAM_LUT_CONFIG_MODE_SAME', +} +DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0 +DWB_OGAM_LUT_CONFIG_MODE_SAME = 1 +DWB_OGAM_LUT_CONFIG_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_HOST_SEL_ENUM' +DWB_OGAM_LUT_HOST_SEL_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_HOST_SEL_RAMA', + 1: 'DWB_OGAM_LUT_HOST_SEL_RAMB', +} +DWB_OGAM_LUT_HOST_SEL_RAMA = 0 +DWB_OGAM_LUT_HOST_SEL_RAMB = 1 +DWB_OGAM_LUT_HOST_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM' +DWB_OGAM_LUT_READ_COLOR_SEL_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_READ_COLOR_SEL_B', + 1: 'DWB_OGAM_LUT_READ_COLOR_SEL_G', + 2: 'DWB_OGAM_LUT_READ_COLOR_SEL_R', + 3: 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', +} +DWB_OGAM_LUT_READ_COLOR_SEL_B = 0 +DWB_OGAM_LUT_READ_COLOR_SEL_G = 1 +DWB_OGAM_LUT_READ_COLOR_SEL_R = 2 +DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 3 +DWB_OGAM_LUT_READ_COLOR_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_READ_DBG_ENUM' +DWB_OGAM_LUT_READ_DBG_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_READ_DBG_DISABLE', + 1: 'DWB_OGAM_LUT_READ_DBG_ENABLE', +} +DWB_OGAM_LUT_READ_DBG_DISABLE = 0 +DWB_OGAM_LUT_READ_DBG_ENABLE = 1 +DWB_OGAM_LUT_READ_DBG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_MODE_ENUM' +DWB_OGAM_MODE_ENUM__enumvalues = { + 0: 'DWB_OGAM_MODE_BYPASS', + 1: 'DWB_OGAM_MODE_RESERVED', + 2: 'DWB_OGAM_MODE_RAM_LUT_ENABLED', +} +DWB_OGAM_MODE_BYPASS = 0 +DWB_OGAM_MODE_RESERVED = 1 +DWB_OGAM_MODE_RAM_LUT_ENABLED = 2 +DWB_OGAM_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_PWL_DISABLE_ENUM' +DWB_OGAM_PWL_DISABLE_ENUM__enumvalues = { + 0: 'DWB_OGAM_PWL_DISABLE_FALSE', + 1: 'DWB_OGAM_PWL_DISABLE_TRUE', +} +DWB_OGAM_PWL_DISABLE_FALSE = 0 +DWB_OGAM_PWL_DISABLE_TRUE = 1 +DWB_OGAM_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_SELECT_ENUM' +DWB_OGAM_SELECT_ENUM__enumvalues = { + 0: 'DWB_OGAM_SELECT_A', + 1: 'DWB_OGAM_SELECT_B', +} +DWB_OGAM_SELECT_A = 0 +DWB_OGAM_SELECT_B = 1 +DWB_OGAM_SELECT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN' +RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN__enumvalues = { + 0: 'RDPCS_EXT_REFCLK_DISABLE', + 1: 'RDPCS_EXT_REFCLK_ENABLE', +} +RDPCS_EXT_REFCLK_DISABLE = 0 +RDPCS_EXT_REFCLK_ENABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON' +RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON__enumvalues = { + 0: 'RDPCS_OCLACLK_CLOCK_OFF', + 1: 'RDPCS_OCLACLK_CLOCK_ON', +} +RDPCS_OCLACLK_CLOCK_OFF = 0 +RDPCS_OCLACLK_CLOCK_ON = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN' +RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN__enumvalues = { + 0: 'RDPCS_OCLACLK_DISABLE', + 1: 'RDPCS_OCLACLK_ENABLE', +} +RDPCS_OCLACLK_DISABLE = 0 +RDPCS_OCLACLK_ENABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS' +RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS__enumvalues = { + 0: 'RDPCS_OCLACLK_GATE_ENABLE', + 1: 'RDPCS_OCLACLK_GATE_DISABLE', +} +RDPCS_OCLACLK_GATE_ENABLE = 0 +RDPCS_OCLACLK_GATE_DISABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON' +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON__enumvalues = { + 0: 'RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF', + 1: 'RDPCS_SYMCLK_SRAMCLK_CLOCK_ON', +} +RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF = 0 +RDPCS_SYMCLK_SRAMCLK_CLOCK_ON = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN' +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN__enumvalues = { + 0: 'RDPCS_SRAMCLK_DISABLE', + 1: 'RDPCS_SRAMCLK_ENABLE', +} +RDPCS_SRAMCLK_DISABLE = 0 +RDPCS_SRAMCLK_ENABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS' +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS__enumvalues = { + 0: 'RDPCS_SRAMCLK_GATE_ENABLE', + 1: 'RDPCS_SRAMCLK_GATE_DISABLE', +} +RDPCS_SRAMCLK_GATE_ENABLE = 0 +RDPCS_SRAMCLK_GATE_DISABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS' +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS__enumvalues = { + 0: 'RDPCS_SRAMCLK_NOT_PASS', + 1: 'RDPCS_SRAMCLK_PASS', +} +RDPCS_SRAMCLK_NOT_PASS = 0 +RDPCS_SRAMCLK_PASS = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON' +RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON__enumvalues = { + 0: 'RDPCS_TX_CLK_CLOCK_OFF', + 1: 'RDPCS_TX_CLK_CLOCK_ON', +} +RDPCS_TX_CLK_CLOCK_OFF = 0 +RDPCS_TX_CLK_CLOCK_ON = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN' +RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN__enumvalues = { + 0: 'RDPCS_TX_CLK_DISABLE', + 1: 'RDPCS_TX_CLK_ENABLE', +} +RDPCS_TX_CLK_DISABLE = 0 +RDPCS_TX_CLK_ENABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS' +RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS__enumvalues = { + 0: 'RDPCS_TX_CLK_GATE_ENABLE', + 1: 'RDPCS_TX_CLK_GATE_DISABLE', +} +RDPCS_TX_CLK_GATE_ENABLE = 0 +RDPCS_TX_CLK_GATE_DISABLE = 1 +RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CLOCK_CNTL_TX_CLK_EN' +RDPCSTX_CLOCK_CNTL_TX_CLK_EN__enumvalues = { + 0: 'RDPCS_EXT_REFCLK_EN_DISABLE', + 1: 'RDPCS_EXT_REFCLK_EN_ENABLE', +} +RDPCS_EXT_REFCLK_EN_DISABLE = 0 +RDPCS_EXT_REFCLK_EN_ENABLE = 1 +RDPCSTX_CLOCK_CNTL_TX_CLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET' +RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET__enumvalues = { + 0: 'RDPCS_CBUS_SOFT_RESET_DISABLE', + 1: 'RDPCS_CBUS_SOFT_RESET_ENABLE', +} +RDPCS_CBUS_SOFT_RESET_DISABLE = 0 +RDPCS_CBUS_SOFT_RESET_ENABLE = 1 +RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET' +RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET__enumvalues = { + 0: 'RDPCS_SRAM_SRAM_RESET_DISABLE', + 1: 'RDPCS_SRAM_SRAM_RESET_ENABLE', +} +RDPCS_SRAM_SRAM_RESET_DISABLE = 0 +RDPCS_SRAM_SRAM_RESET_ENABLE = 1 +RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_FIFO_EN' +RDPCSTX_CNTL_RDPCS_TX_FIFO_EN__enumvalues = { + 0: 'RDPCS_TX_FIFO_DISABLE', + 1: 'RDPCS_TX_FIFO_ENABLE', +} +RDPCS_TX_FIFO_DISABLE = 0 +RDPCS_TX_FIFO_ENABLE = 1 +RDPCSTX_CNTL_RDPCS_TX_FIFO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN' +RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN__enumvalues = { + 0: 'RDPCS_TX_FIFO_LANE_DISABLE', + 1: 'RDPCS_TX_FIFO_LANE_ENABLE', +} +RDPCS_TX_FIFO_LANE_DISABLE = 0 +RDPCS_TX_FIFO_LANE_ENABLE = 1 +RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET' +RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET__enumvalues = { + 0: 'RDPCS_TX_SOFT_RESET_DISABLE', + 1: 'RDPCS_TX_SOFT_RESET_ENABLE', +} +RDPCS_TX_SOFT_RESET_DISABLE = 0 +RDPCS_TX_SOFT_RESET_ENABLE = 1 +RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_FIFO_EMPTY' +RDPCSTX_FIFO_EMPTY__enumvalues = { + 0: 'RDPCSTX_FIFO_NOT_EMPTY', + 1: 'RDPCSTX_FIFO_IS_EMPTY', +} +RDPCSTX_FIFO_NOT_EMPTY = 0 +RDPCSTX_FIFO_IS_EMPTY = 1 +RDPCSTX_FIFO_EMPTY = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_FIFO_FULL' +RDPCSTX_FIFO_FULL__enumvalues = { + 0: 'RDPCSTX_FIFO_NOT_FULL', + 1: 'RDPCSTX_FIFO_IS_FULL', +} +RDPCSTX_FIFO_NOT_FULL = 0 +RDPCSTX_FIFO_IS_FULL = 1 +RDPCSTX_FIFO_FULL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE' +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE__enumvalues = { + 0: 'RDPCS_DPALT_4LANE_TOGGLE_2LANE', + 1: 'RDPCS_DPALT_4LANE_TOGGLE_4LANE', +} +RDPCS_DPALT_4LANE_TOGGLE_2LANE = 0 +RDPCS_DPALT_4LANE_TOGGLE_4LANE = 1 +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK' +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK__enumvalues = { + 0: 'RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE', + 1: 'RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE', +} +RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0 +RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE = 1 +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE' +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE__enumvalues = { + 0: 'RDPCS_DPALT_DISABLE_TOGGLE_ENABLE', + 1: 'RDPCS_DPALT_DISABLE_TOGGLE_DISABLE', +} +RDPCS_DPALT_DISABLE_TOGGLE_ENABLE = 0 +RDPCS_DPALT_DISABLE_TOGGLE_DISABLE = 1 +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK' +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK__enumvalues = { + 0: 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE', + 1: 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE', +} +RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0 +RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 1 +RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK' +RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK__enumvalues = { + 0: 'RDPCS_REG_FIFO_ERROR_MASK_DISABLE', + 1: 'RDPCS_REG_FIFO_ERROR_MASK_ENABLE', +} +RDPCS_REG_FIFO_ERROR_MASK_DISABLE = 0 +RDPCS_REG_FIFO_ERROR_MASK_ENABLE = 1 +RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK' +RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK__enumvalues = { + 0: 'RDPCS_TX_FIFO_ERROR_MASK_DISABLE', + 1: 'RDPCS_TX_FIFO_ERROR_MASK_ENABLE', +} +RDPCS_TX_FIFO_ERROR_MASK_DISABLE = 0 +RDPCS_TX_FIFO_ERROR_MASK_ENABLE = 1 +RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL' +RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL__enumvalues = { + 0: 'RDPCS_PHY_CR_MUX_SEL_FOR_USB', + 1: 'RDPCS_PHY_CR_MUX_SEL_FOR_DC', +} +RDPCS_PHY_CR_MUX_SEL_FOR_USB = 0 +RDPCS_PHY_CR_MUX_SEL_FOR_DC = 1 +RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL' +RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL__enumvalues = { + 0: 'RDPCS_PHY_CR_PARA_SEL_JTAG', + 1: 'RDPCS_PHY_CR_PARA_SEL_CR', +} +RDPCS_PHY_CR_PARA_SEL_JTAG = 0 +RDPCS_PHY_CR_PARA_SEL_CR = 1 +RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE' +RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE__enumvalues = { + 0: 'RDPCS_PHY_REF_RANGE_0', + 1: 'RDPCS_PHY_REF_RANGE_1', + 2: 'RDPCS_PHY_REF_RANGE_2', + 3: 'RDPCS_PHY_REF_RANGE_3', + 4: 'RDPCS_PHY_REF_RANGE_4', + 5: 'RDPCS_PHY_REF_RANGE_5', + 6: 'RDPCS_PHY_REF_RANGE_6', + 7: 'RDPCS_PHY_REF_RANGE_7', +} +RDPCS_PHY_REF_RANGE_0 = 0 +RDPCS_PHY_REF_RANGE_1 = 1 +RDPCS_PHY_REF_RANGE_2 = 2 +RDPCS_PHY_REF_RANGE_3 = 3 +RDPCS_PHY_REF_RANGE_4 = 4 +RDPCS_PHY_REF_RANGE_5 = 5 +RDPCS_PHY_REF_RANGE_6 = 6 +RDPCS_PHY_REF_RANGE_7 = 7 +RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE' +RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE__enumvalues = { + 0: 'RDPCS_SRAM_EXT_LD_NOT_DONE', + 1: 'RDPCS_SRAM_EXT_LD_DONE', +} +RDPCS_SRAM_EXT_LD_NOT_DONE = 0 +RDPCS_SRAM_EXT_LD_DONE = 1 +RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE' +RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE__enumvalues = { + 0: 'RDPCS_SRAM_INIT_NOT_DONE', + 1: 'RDPCS_SRAM_INIT_DONE', +} +RDPCS_SRAM_INIT_NOT_DONE = 0 +RDPCS_SRAM_INIT_DONE = 1 +RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV' +RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__enumvalues = { + 0: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1', + 1: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2', + 2: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3', + 3: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8', + 4: 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16', +} +RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1 = 0 +RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2 = 1 +RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3 = 2 +RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8 = 3 +RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16 = 4 +RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV' +RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__enumvalues = { + 0: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', + 1: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', + 2: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', + 3: 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', +} +RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0 +RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 1 +RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 2 +RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 3 +RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV' +RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__enumvalues = { + 0: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', + 1: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2', + 2: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4', + 3: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8', + 4: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3', + 5: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5', + 6: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6', + 7: 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10', +} +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2 = 1 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4 = 2 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8 = 3 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3 = 4 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5 = 5 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6 = 6 +RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10 = 7 +RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL' +RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL__enumvalues = { + 0: 'RDPCS_PHY_DP_TX_TERM_CTRL_54', + 1: 'RDPCS_PHY_DP_TX_TERM_CTRL_52', + 2: 'RDPCS_PHY_DP_TX_TERM_CTRL_50', + 3: 'RDPCS_PHY_DP_TX_TERM_CTRL_48', + 4: 'RDPCS_PHY_DP_TX_TERM_CTRL_46', + 5: 'RDPCS_PHY_DP_TX_TERM_CTRL_44', + 6: 'RDPCS_PHY_DP_TX_TERM_CTRL_42', + 7: 'RDPCS_PHY_DP_TX_TERM_CTRL_40', +} +RDPCS_PHY_DP_TX_TERM_CTRL_54 = 0 +RDPCS_PHY_DP_TX_TERM_CTRL_52 = 1 +RDPCS_PHY_DP_TX_TERM_CTRL_50 = 2 +RDPCS_PHY_DP_TX_TERM_CTRL_48 = 3 +RDPCS_PHY_DP_TX_TERM_CTRL_46 = 4 +RDPCS_PHY_DP_TX_TERM_CTRL_44 = 5 +RDPCS_PHY_DP_TX_TERM_CTRL_42 = 6 +RDPCS_PHY_DP_TX_TERM_CTRL_40 = 7 +RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT' +RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT__enumvalues = { + 0: 'RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT', + 1: 'RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT', +} +RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0 +RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT = 1 +RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE' +RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE__enumvalues = { + 0: 'RDPCS_PHY_DP_TX_RATE', + 1: 'RDPCS_PHY_DP_TX_RATE_DIV2', + 2: 'RDPCS_PHY_DP_TX_RATE_DIV4', +} +RDPCS_PHY_DP_TX_RATE = 0 +RDPCS_PHY_DP_TX_RATE_DIV2 = 1 +RDPCS_PHY_DP_TX_RATE_DIV4 = 2 +RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH' +RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH__enumvalues = { + 0: 'RDPCS_PHY_DP_TX_WIDTH_8', + 1: 'RDPCS_PHY_DP_TX_WIDTH_10', + 2: 'RDPCS_PHY_DP_TX_WIDTH_16', + 3: 'RDPCS_PHY_DP_TX_WIDTH_20', +} +RDPCS_PHY_DP_TX_WIDTH_8 = 0 +RDPCS_PHY_DP_TX_WIDTH_10 = 1 +RDPCS_PHY_DP_TX_WIDTH_16 = 2 +RDPCS_PHY_DP_TX_WIDTH_20 = 3 +RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE' +RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE__enumvalues = { + 0: 'RRDPCS_PHY_DP_TX_PSTATE_POWER_UP', + 1: 'RRDPCS_PHY_DP_TX_PSTATE_HOLD', + 2: 'RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF', + 3: 'RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN', +} +RRDPCS_PHY_DP_TX_PSTATE_POWER_UP = 0 +RRDPCS_PHY_DP_TX_PSTATE_HOLD = 1 +RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF = 2 +RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN = 3 +RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_PHY_REF_ALT_CLK_EN' +RDPCSTX_PHY_REF_ALT_CLK_EN__enumvalues = { + 0: 'RDPCS_PHY_REF_ALT_CLK_DISABLE', + 1: 'RDPCS_PHY_REF_ALT_CLK_ENABLE', +} +RDPCS_PHY_REF_ALT_CLK_DISABLE = 0 +RDPCS_PHY_REF_ALT_CLK_ENABLE = 1 +RDPCSTX_PHY_REF_ALT_CLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSTX_TX_FIFO_DISABLED_MASK' +RDPCSTX_TX_FIFO_DISABLED_MASK__enumvalues = { + 0: 'RDPCSTX_TX_FIFO_DISABLED_MASK_DISABLE', + 1: 'RDPCSTX_TX_FIFO_DISABLED_MASK_ENABLE', +} +RDPCSTX_TX_FIFO_DISABLED_MASK_DISABLE = 0 +RDPCSTX_TX_FIFO_DISABLED_MASK_ENABLE = 1 +RDPCSTX_TX_FIFO_DISABLED_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_DBG_OCLA_SEL' +RDPCS_DBG_OCLA_SEL__enumvalues = { + 0: 'RDPCS_DBG_OCLA_SEL_MON_OUT_7_0', + 1: 'RDPCS_DBG_OCLA_SEL_MON_OUT_15_8', + 2: 'RDPCS_DBG_OCLA_SEL_MON_OUT_23_16', + 3: 'RDPCS_DBG_OCLA_SEL_MON_OUT_31_24', + 4: 'RDPCS_DBG_OCLA_SEL_MON_OUT_39_32', + 5: 'RDPCS_DBG_OCLA_SEL_MON_OUT_47_40', + 6: 'RDPCS_DBG_OCLA_SEL_MON_OUT_55_48', + 7: 'RDPCS_DBG_OCLA_SEL_MON_OUT_63_56', +} +RDPCS_DBG_OCLA_SEL_MON_OUT_7_0 = 0 +RDPCS_DBG_OCLA_SEL_MON_OUT_15_8 = 1 +RDPCS_DBG_OCLA_SEL_MON_OUT_23_16 = 2 +RDPCS_DBG_OCLA_SEL_MON_OUT_31_24 = 3 +RDPCS_DBG_OCLA_SEL_MON_OUT_39_32 = 4 +RDPCS_DBG_OCLA_SEL_MON_OUT_47_40 = 5 +RDPCS_DBG_OCLA_SEL_MON_OUT_55_48 = 6 +RDPCS_DBG_OCLA_SEL_MON_OUT_63_56 = 7 +RDPCS_DBG_OCLA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_TEST_CLK_SEL' +RDPCS_TEST_CLK_SEL__enumvalues = { + 0: 'RDPCS_TEST_CLK_SEL_NONE', + 1: 'RDPCS_TEST_CLK_SEL_CFGCLK', + 2: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', + 3: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', + 4: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', + 5: 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', + 6: 'RDPCS_TEST_CLK_SEL_SRAMCLK', + 7: 'RDPCS_TEST_CLK_SEL_EXT_CR_CLK', + 8: 'RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK', + 9: 'RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK', + 10: 'RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK', + 11: 'RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK', + 12: 'RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', + 13: 'RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', + 14: 'RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK', + 15: 'RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk', + 16: 'RDPCS_TEST_CLK_SEL_dtb_out0', + 17: 'RDPCS_TEST_CLK_SEL_dtb_out1', +} +RDPCS_TEST_CLK_SEL_NONE = 0 +RDPCS_TEST_CLK_SEL_CFGCLK = 1 +RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 2 +RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 3 +RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 4 +RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 5 +RDPCS_TEST_CLK_SEL_SRAMCLK = 6 +RDPCS_TEST_CLK_SEL_EXT_CR_CLK = 7 +RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK = 8 +RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK = 9 +RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK = 10 +RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK = 11 +RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 12 +RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 13 +RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK = 14 +RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk = 15 +RDPCS_TEST_CLK_SEL_dtb_out0 = 16 +RDPCS_TEST_CLK_SEL_dtb_out1 = 17 +RDPCS_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB' +RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB__enumvalues = { + 0: 'RDPCS_LANE_PACK_FROM_MSB_DISABLE', + 1: 'RDPCS_LANE_PACK_FROM_MSB_ENABLE', +} +RDPCS_LANE_PACK_FROM_MSB_DISABLE = 0 +RDPCS_LANE_PACK_FROM_MSB_ENABLE = 1 +RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE' +RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE__enumvalues = { + 0: 'RDPCS_MEM_PWR_NO_FORCE', + 1: 'RDPCS_MEM_PWR_LIGHT_SLEEP', + 2: 'RDPCS_MEM_PWR_DEEP_SLEEP', + 3: 'RDPCS_MEM_PWR_SHUT_DOWN', +} +RDPCS_MEM_PWR_NO_FORCE = 0 +RDPCS_MEM_PWR_LIGHT_SLEEP = 1 +RDPCS_MEM_PWR_DEEP_SLEEP = 2 +RDPCS_MEM_PWR_SHUT_DOWN = 3 +RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE' +RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE__enumvalues = { + 0: 'RDPCS_MEM_PWR_PWR_STATE_ON', + 1: 'RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP', + 2: 'RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP', + 3: 'RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN', +} +RDPCS_MEM_PWR_PWR_STATE_ON = 0 +RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 1 +RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP = 2 +RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN = 3 +RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK' +RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK__enumvalues = { + 0: 'RDPCS_LANE_BIT_ORDER_REVERSE_DISABLE', + 1: 'RDPCS_LANE_BIT_ORDER_REVERSE_ENABLE', +} +RDPCS_LANE_BIT_ORDER_REVERSE_DISABLE = 0 +RDPCS_LANE_BIT_ORDER_REVERSE_ENABLE = 1 +RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK = ctypes.c_uint32 # enum + +# values for enumeration 'RLC_DOORBELL_MODE' +RLC_DOORBELL_MODE__enumvalues = { + 0: 'RLC_DOORBELL_MODE_DISABLE', + 1: 'RLC_DOORBELL_MODE_ENABLE', + 2: 'RLC_DOORBELL_MODE_ENABLE_PF', + 3: 'RLC_DOORBELL_MODE_ENABLE_PF_VF', +} +RLC_DOORBELL_MODE_DISABLE = 0 +RLC_DOORBELL_MODE_ENABLE = 1 +RLC_DOORBELL_MODE_ENABLE_PF = 2 +RLC_DOORBELL_MODE_ENABLE_PF_VF = 3 +RLC_DOORBELL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'RLC_PERFCOUNTER_SEL' +RLC_PERFCOUNTER_SEL__enumvalues = { + 0: 'RLC_PERF_SEL_POWER_FEATURE_0', + 1: 'RLC_PERF_SEL_POWER_FEATURE_1', + 2: 'RLC_PERF_SEL_CP_INTERRUPT', + 3: 'RLC_PERF_SEL_GRBM_INTERRUPT', + 4: 'RLC_PERF_SEL_SPM_INTERRUPT', + 5: 'RLC_PERF_SEL_IH_INTERRUPT', + 6: 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', +} +RLC_PERF_SEL_POWER_FEATURE_0 = 0 +RLC_PERF_SEL_POWER_FEATURE_1 = 1 +RLC_PERF_SEL_CP_INTERRUPT = 2 +RLC_PERF_SEL_GRBM_INTERRUPT = 3 +RLC_PERF_SEL_SPM_INTERRUPT = 4 +RLC_PERF_SEL_IH_INTERRUPT = 5 +RLC_PERF_SEL_SERDES_COMMAND_WRITE = 6 +RLC_PERFCOUNTER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RLC_PERFMON_STATE' +RLC_PERFMON_STATE__enumvalues = { + 0: 'RLC_PERFMON_STATE_RESET', + 1: 'RLC_PERFMON_STATE_ENABLE', + 2: 'RLC_PERFMON_STATE_DISABLE', + 3: 'RLC_PERFMON_STATE_RESERVED_3', + 4: 'RLC_PERFMON_STATE_RESERVED_4', + 5: 'RLC_PERFMON_STATE_RESERVED_5', + 6: 'RLC_PERFMON_STATE_RESERVED_6', + 7: 'RLC_PERFMON_STATE_ROLLOVER', +} +RLC_PERFMON_STATE_RESET = 0 +RLC_PERFMON_STATE_ENABLE = 1 +RLC_PERFMON_STATE_DISABLE = 2 +RLC_PERFMON_STATE_RESERVED_3 = 3 +RLC_PERFMON_STATE_RESERVED_4 = 4 +RLC_PERFMON_STATE_RESERVED_5 = 5 +RLC_PERFMON_STATE_RESERVED_6 = 6 +RLC_PERFMON_STATE_ROLLOVER = 7 +RLC_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'RSPM_CMD' +RSPM_CMD__enumvalues = { + 0: 'RSPM_CMD_INVALID', + 1: 'RSPM_CMD_IDLE', + 2: 'RSPM_CMD_CALIBRATE', + 3: 'RSPM_CMD_SPM_RESET', + 4: 'RSPM_CMD_SPM_START', + 5: 'RSPM_CMD_SPM_STOP', + 6: 'RSPM_CMD_PERF_RESET', + 7: 'RSPM_CMD_PERF_SAMPLE', + 8: 'RSPM_CMD_PROF_START', + 9: 'RSPM_CMD_PROF_STOP', + 10: 'RSPM_CMD_FORCE_SAMPLE', +} +RSPM_CMD_INVALID = 0 +RSPM_CMD_IDLE = 1 +RSPM_CMD_CALIBRATE = 2 +RSPM_CMD_SPM_RESET = 3 +RSPM_CMD_SPM_START = 4 +RSPM_CMD_SPM_STOP = 5 +RSPM_CMD_PERF_RESET = 6 +RSPM_CMD_PERF_SAMPLE = 7 +RSPM_CMD_PROF_START = 8 +RSPM_CMD_PROF_STOP = 9 +RSPM_CMD_FORCE_SAMPLE = 10 +RSPM_CMD = ctypes.c_uint32 # enum + +# values for enumeration 'CSCNTL_TYPE' +CSCNTL_TYPE__enumvalues = { + 0: 'CSCNTL_TYPE_TG', + 1: 'CSCNTL_TYPE_STATE', + 2: 'CSCNTL_TYPE_EVENT', + 3: 'CSCNTL_TYPE_PRIVATE', +} +CSCNTL_TYPE_TG = 0 +CSCNTL_TYPE_STATE = 1 +CSCNTL_TYPE_EVENT = 2 +CSCNTL_TYPE_PRIVATE = 3 +CSCNTL_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CSDATA_TYPE' +CSDATA_TYPE__enumvalues = { + 0: 'CSDATA_TYPE_TG', + 1: 'CSDATA_TYPE_STATE', + 2: 'CSDATA_TYPE_EVENT', + 3: 'CSDATA_TYPE_PRIVATE', +} +CSDATA_TYPE_TG = 0 +CSDATA_TYPE_STATE = 1 +CSDATA_TYPE_EVENT = 2 +CSDATA_TYPE_PRIVATE = 3 +CSDATA_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'GE1_PERFCOUNT_SELECT' +GE1_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge1_assembler_busy', + 1: 'ge1_assembler_stalled', + 2: 'ge1_dma_busy', + 3: 'ge1_dma_lat_bin_0', + 4: 'ge1_dma_lat_bin_1', + 5: 'ge1_dma_lat_bin_2', + 6: 'ge1_dma_lat_bin_3', + 7: 'ge1_dma_lat_bin_4', + 8: 'ge1_dma_lat_bin_5', + 9: 'ge1_dma_lat_bin_6', + 10: 'ge1_dma_lat_bin_7', + 11: 'ge1_dma_return_cl0', + 12: 'ge1_dma_return_cl1', + 13: 'ge1_dma_utcl1_consecutive_retry_event', + 14: 'ge1_dma_utcl1_request_event', + 15: 'ge1_dma_utcl1_retry_event', + 16: 'ge1_dma_utcl1_stall_event', + 17: 'ge1_dma_utcl1_stall_utcl2_event', + 18: 'ge1_dma_utcl1_translation_hit_event', + 19: 'ge1_dma_utcl1_translation_miss_event', + 20: 'ge1_assembler_dma_starved', + 21: 'ge1_rbiu_di_fifo_stalled_p0', + 22: 'ge1_rbiu_di_fifo_starved_p0', + 23: 'ge1_rbiu_dr_fifo_stalled_p0', + 24: 'ge1_rbiu_dr_fifo_starved_p0', + 25: 'ge1_sclk_reg_vld', + 26: 'ge1_stat_busy', + 27: 'ge1_stat_no_dma_busy', + 28: 'ge1_pipe0_to_pipe1', + 29: 'ge1_pipe1_to_pipe0', + 30: 'ge1_dma_return_size_cl0', + 31: 'ge1_dma_return_size_cl1', + 32: 'ge1_small_draws_one_instance', + 33: 'ge1_sclk_input_vld', + 34: 'ge1_prim_group_limit_hit', + 35: 'ge1_unopt_multi_instance_draws', + 36: 'ge1_rbiu_di_fifo_stalled_p1', + 37: 'ge1_rbiu_di_fifo_starved_p1', + 38: 'ge1_rbiu_dr_fifo_stalled_p1', + 39: 'ge1_rbiu_dr_fifo_starved_p1', +} +ge1_assembler_busy = 0 +ge1_assembler_stalled = 1 +ge1_dma_busy = 2 +ge1_dma_lat_bin_0 = 3 +ge1_dma_lat_bin_1 = 4 +ge1_dma_lat_bin_2 = 5 +ge1_dma_lat_bin_3 = 6 +ge1_dma_lat_bin_4 = 7 +ge1_dma_lat_bin_5 = 8 +ge1_dma_lat_bin_6 = 9 +ge1_dma_lat_bin_7 = 10 +ge1_dma_return_cl0 = 11 +ge1_dma_return_cl1 = 12 +ge1_dma_utcl1_consecutive_retry_event = 13 +ge1_dma_utcl1_request_event = 14 +ge1_dma_utcl1_retry_event = 15 +ge1_dma_utcl1_stall_event = 16 +ge1_dma_utcl1_stall_utcl2_event = 17 +ge1_dma_utcl1_translation_hit_event = 18 +ge1_dma_utcl1_translation_miss_event = 19 +ge1_assembler_dma_starved = 20 +ge1_rbiu_di_fifo_stalled_p0 = 21 +ge1_rbiu_di_fifo_starved_p0 = 22 +ge1_rbiu_dr_fifo_stalled_p0 = 23 +ge1_rbiu_dr_fifo_starved_p0 = 24 +ge1_sclk_reg_vld = 25 +ge1_stat_busy = 26 +ge1_stat_no_dma_busy = 27 +ge1_pipe0_to_pipe1 = 28 +ge1_pipe1_to_pipe0 = 29 +ge1_dma_return_size_cl0 = 30 +ge1_dma_return_size_cl1 = 31 +ge1_small_draws_one_instance = 32 +ge1_sclk_input_vld = 33 +ge1_prim_group_limit_hit = 34 +ge1_unopt_multi_instance_draws = 35 +ge1_rbiu_di_fifo_stalled_p1 = 36 +ge1_rbiu_di_fifo_starved_p1 = 37 +ge1_rbiu_dr_fifo_stalled_p1 = 38 +ge1_rbiu_dr_fifo_starved_p1 = 39 +GE1_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'GE2_DIST_PERFCOUNT_SELECT' +GE2_DIST_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge_dist_hs_done', + 1: 'ge_dist_hs_done_latency_se0', + 2: 'ge_dist_hs_done_latency_se1', + 3: 'ge_dist_hs_done_latency_se2', + 4: 'ge_dist_hs_done_latency_se3', + 5: 'ge_dist_hs_done_latency_se4', + 6: 'ge_dist_hs_done_latency_se5', + 7: 'ge_dist_hs_done_latency_se6', + 8: 'ge_dist_hs_done_latency_se7', + 9: 'ge_dist_inside_tf_bin_0', + 10: 'ge_dist_inside_tf_bin_1', + 11: 'ge_dist_inside_tf_bin_2', + 12: 'ge_dist_inside_tf_bin_3', + 13: 'ge_dist_inside_tf_bin_4', + 14: 'ge_dist_inside_tf_bin_5', + 15: 'ge_dist_inside_tf_bin_6', + 16: 'ge_dist_inside_tf_bin_7', + 17: 'ge_dist_inside_tf_bin_8', + 18: 'ge_dist_null_patch', + 19: 'ge_dist_sclk_core_vld', + 20: 'ge_dist_sclk_wd_te11_vld', + 21: 'ge_dist_tfreq_lat_bin_0', + 22: 'ge_dist_tfreq_lat_bin_1', + 23: 'ge_dist_tfreq_lat_bin_2', + 24: 'ge_dist_tfreq_lat_bin_3', + 25: 'ge_dist_tfreq_lat_bin_4', + 26: 'ge_dist_tfreq_lat_bin_5', + 27: 'ge_dist_tfreq_lat_bin_6', + 28: 'ge_dist_tfreq_lat_bin_7', + 29: 'ge_dist_tfreq_utcl1_consecutive_retry_event', + 30: 'ge_dist_tfreq_utcl1_request_event', + 31: 'ge_dist_tfreq_utcl1_retry_event', + 32: 'ge_dist_tfreq_utcl1_stall_event', + 33: 'ge_dist_tfreq_utcl1_stall_utcl2_event', + 34: 'ge_dist_tfreq_utcl1_translation_hit_event', + 35: 'ge_dist_tfreq_utcl1_translation_miss_event', + 36: 'ge_dist_pc_feorder_fifo_full', + 37: 'ge_dist_pc_ge_manager_busy', + 38: 'ge_dist_sclk_input_vld', + 39: 'ge_dist_wd_te11_busy', + 40: 'ge_dist_te11_starved', + 41: 'ge_dist_switch_mode_stall', + 42: 'ge_all_tf_eq', + 43: 'ge_all_tf2', + 44: 'ge_all_tf3', + 45: 'ge_all_tf4', + 46: 'ge_all_tf5', + 47: 'ge_all_tf6', + 48: 'ge_se0_te11_starved_on_hs_done', + 49: 'ge_se1_te11_starved_on_hs_done', + 50: 'ge_se2_te11_starved_on_hs_done', + 51: 'ge_se3_te11_starved_on_hs_done', + 52: 'ge_se4_te11_starved_on_hs_done', + 53: 'ge_se5_te11_starved_on_hs_done', + 54: 'ge_se6_te11_starved_on_hs_done', + 55: 'ge_se7_te11_starved_on_hs_done', + 56: 'ge_dist_op_fifo_full_starve', + 57: 'ge_dist_hs_done_se0', + 58: 'ge_dist_hs_done_se1', + 59: 'ge_dist_hs_done_se2', + 60: 'ge_dist_hs_done_se3', + 61: 'ge_dist_hs_done_se4', + 62: 'ge_dist_hs_done_se5', + 63: 'ge_dist_hs_done_se6', + 64: 'ge_dist_hs_done_se7', + 65: 'ge_dist_hs_done_latency', + 66: 'ge_dist_distributer_busy', + 67: 'ge_tf_ret_data_stalling_hs_done', + 68: 'ge_num_of_no_dist_patches', + 69: 'ge_num_of_donut_dist_patches', + 70: 'ge_num_of_patch_dist_patches', + 71: 'ge_num_of_se_switches_due_to_patch_accum', + 72: 'ge_num_of_se_switches_due_to_donut', + 73: 'ge_num_of_se_switches_due_to_trap', + 74: 'ge_num_of_hs_dealloc_events', + 75: 'ge_agm_gcr_req', + 76: 'ge_agm_gcr_tag_stall', + 77: 'ge_agm_gcr_crd_stall', + 78: 'ge_agm_gcr_stall', + 79: 'ge_agm_gcr_latency', + 80: 'ge_distclk_vld', + 81: 'ge_dist_indx_fifos_full_and_empty', + 82: 'ge_hs_done_all_tf0_se0', + 83: 'ge_hs_done_all_tf0_se1', + 84: 'ge_hs_done_all_tf0_se2', + 85: 'ge_hs_done_all_tf0_se3', + 86: 'ge_hs_done_all_tf0_se4', + 87: 'ge_hs_done_all_tf0_se5', + 88: 'ge_hs_done_all_tf0_se6', + 89: 'ge_hs_done_all_tf0_se7', + 90: 'ge_hs_done_all_tf1_se0', + 91: 'ge_hs_done_all_tf1_se1', + 92: 'ge_hs_done_all_tf1_se2', + 93: 'ge_hs_done_all_tf1_se3', + 94: 'ge_hs_done_all_tf1_se4', + 95: 'ge_hs_done_all_tf1_se5', + 96: 'ge_hs_done_all_tf1_se6', + 97: 'ge_hs_done_all_tf1_se7', + 98: 'ge_agm_gcr_req_outstanding', + 99: 'ge_agm_gcr_req_amount', + 100: 'ge_agm_gcr_combine', +} +ge_dist_hs_done = 0 +ge_dist_hs_done_latency_se0 = 1 +ge_dist_hs_done_latency_se1 = 2 +ge_dist_hs_done_latency_se2 = 3 +ge_dist_hs_done_latency_se3 = 4 +ge_dist_hs_done_latency_se4 = 5 +ge_dist_hs_done_latency_se5 = 6 +ge_dist_hs_done_latency_se6 = 7 +ge_dist_hs_done_latency_se7 = 8 +ge_dist_inside_tf_bin_0 = 9 +ge_dist_inside_tf_bin_1 = 10 +ge_dist_inside_tf_bin_2 = 11 +ge_dist_inside_tf_bin_3 = 12 +ge_dist_inside_tf_bin_4 = 13 +ge_dist_inside_tf_bin_5 = 14 +ge_dist_inside_tf_bin_6 = 15 +ge_dist_inside_tf_bin_7 = 16 +ge_dist_inside_tf_bin_8 = 17 +ge_dist_null_patch = 18 +ge_dist_sclk_core_vld = 19 +ge_dist_sclk_wd_te11_vld = 20 +ge_dist_tfreq_lat_bin_0 = 21 +ge_dist_tfreq_lat_bin_1 = 22 +ge_dist_tfreq_lat_bin_2 = 23 +ge_dist_tfreq_lat_bin_3 = 24 +ge_dist_tfreq_lat_bin_4 = 25 +ge_dist_tfreq_lat_bin_5 = 26 +ge_dist_tfreq_lat_bin_6 = 27 +ge_dist_tfreq_lat_bin_7 = 28 +ge_dist_tfreq_utcl1_consecutive_retry_event = 29 +ge_dist_tfreq_utcl1_request_event = 30 +ge_dist_tfreq_utcl1_retry_event = 31 +ge_dist_tfreq_utcl1_stall_event = 32 +ge_dist_tfreq_utcl1_stall_utcl2_event = 33 +ge_dist_tfreq_utcl1_translation_hit_event = 34 +ge_dist_tfreq_utcl1_translation_miss_event = 35 +ge_dist_pc_feorder_fifo_full = 36 +ge_dist_pc_ge_manager_busy = 37 +ge_dist_sclk_input_vld = 38 +ge_dist_wd_te11_busy = 39 +ge_dist_te11_starved = 40 +ge_dist_switch_mode_stall = 41 +ge_all_tf_eq = 42 +ge_all_tf2 = 43 +ge_all_tf3 = 44 +ge_all_tf4 = 45 +ge_all_tf5 = 46 +ge_all_tf6 = 47 +ge_se0_te11_starved_on_hs_done = 48 +ge_se1_te11_starved_on_hs_done = 49 +ge_se2_te11_starved_on_hs_done = 50 +ge_se3_te11_starved_on_hs_done = 51 +ge_se4_te11_starved_on_hs_done = 52 +ge_se5_te11_starved_on_hs_done = 53 +ge_se6_te11_starved_on_hs_done = 54 +ge_se7_te11_starved_on_hs_done = 55 +ge_dist_op_fifo_full_starve = 56 +ge_dist_hs_done_se0 = 57 +ge_dist_hs_done_se1 = 58 +ge_dist_hs_done_se2 = 59 +ge_dist_hs_done_se3 = 60 +ge_dist_hs_done_se4 = 61 +ge_dist_hs_done_se5 = 62 +ge_dist_hs_done_se6 = 63 +ge_dist_hs_done_se7 = 64 +ge_dist_hs_done_latency = 65 +ge_dist_distributer_busy = 66 +ge_tf_ret_data_stalling_hs_done = 67 +ge_num_of_no_dist_patches = 68 +ge_num_of_donut_dist_patches = 69 +ge_num_of_patch_dist_patches = 70 +ge_num_of_se_switches_due_to_patch_accum = 71 +ge_num_of_se_switches_due_to_donut = 72 +ge_num_of_se_switches_due_to_trap = 73 +ge_num_of_hs_dealloc_events = 74 +ge_agm_gcr_req = 75 +ge_agm_gcr_tag_stall = 76 +ge_agm_gcr_crd_stall = 77 +ge_agm_gcr_stall = 78 +ge_agm_gcr_latency = 79 +ge_distclk_vld = 80 +ge_dist_indx_fifos_full_and_empty = 81 +ge_hs_done_all_tf0_se0 = 82 +ge_hs_done_all_tf0_se1 = 83 +ge_hs_done_all_tf0_se2 = 84 +ge_hs_done_all_tf0_se3 = 85 +ge_hs_done_all_tf0_se4 = 86 +ge_hs_done_all_tf0_se5 = 87 +ge_hs_done_all_tf0_se6 = 88 +ge_hs_done_all_tf0_se7 = 89 +ge_hs_done_all_tf1_se0 = 90 +ge_hs_done_all_tf1_se1 = 91 +ge_hs_done_all_tf1_se2 = 92 +ge_hs_done_all_tf1_se3 = 93 +ge_hs_done_all_tf1_se4 = 94 +ge_hs_done_all_tf1_se5 = 95 +ge_hs_done_all_tf1_se6 = 96 +ge_hs_done_all_tf1_se7 = 97 +ge_agm_gcr_req_outstanding = 98 +ge_agm_gcr_req_amount = 99 +ge_agm_gcr_combine = 100 +GE2_DIST_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'GE2_SE_PERFCOUNT_SELECT' +GE2_SE_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge_se_ds_prims', + 1: 'ge_se_es_thread_groups', + 2: 'ge_se_esvert_stalled_gsprim', + 3: 'ge_se_hs_tfm_stall', + 4: 'ge_se_hs_tgs_active_high_water_mark', + 5: 'ge_se_hs_thread_groups', + 6: 'ge_se_reused_es_indices', + 7: 'ge_se_sclk_ngg_vld', + 8: 'ge_se_sclk_te11_vld', + 9: 'ge_se_spi_esvert_eov', + 10: 'ge_se_spi_esvert_stalled', + 11: 'ge_se_spi_esvert_starved_busy', + 12: 'ge_se_spi_esvert_valid', + 13: 'ge_se_spi_gsprim_cont', + 14: 'ge_se_spi_gsprim_eov', + 15: 'ge_se_spi_gsprim_stalled', + 16: 'ge_se_spi_gsprim_starved_busy', + 17: 'ge_se_spi_gsprim_valid', + 18: 'ge_se_spi_gssubgrp_is_event', + 19: 'ge_se_spi_gssubgrp_send', + 20: 'ge_se_spi_hsvert_eov', + 21: 'ge_se_spi_hsvert_stalled', + 22: 'ge_se_spi_hsvert_starved_busy', + 23: 'ge_se_spi_hsvert_valid', + 24: 'ge_se_spi_hsgrp_is_event', + 25: 'ge_se_spi_hsgrp_send', + 26: 'ge_se_spi_lsvert_eov', + 27: 'ge_se_spi_lsvert_stalled', + 28: 'ge_se_spi_lsvert_starved_busy', + 29: 'ge_se_spi_lsvert_valid', + 30: 'ge_se_spi_hsvert_fifo_full_stall', + 31: 'ge_se_spi_tgrp_fifo_stall', + 32: 'ge_spi_hsgrp_spi_stall', + 33: 'ge_se_spi_gssubgrp_event_window_active', + 34: 'ge_se_hs_input_stall', + 35: 'ge_se_sending_vert_or_prim', + 36: 'ge_se_sclk_input_vld', + 37: 'ge_spi_lswave_fifo_full_stall', + 38: 'ge_spi_hswave_fifo_full_stall', + 39: 'ge_hs_tif_stall', + 40: 'ge_csb_spi_bp', + 41: 'ge_ngg_starving_for_wave_id', + 42: 'ge_pa0_csb_eop', + 43: 'ge_ngg_starved_idle', + 44: 'ge_gsprim_send', + 45: 'ge_esvert_send', + 46: 'ge_ngg_starved_after_work', + 47: 'ge_ngg_subgrp_fifo_stall', + 48: 'ge_ngg_ord_id_req_stall', + 49: 'ge_ngg_indx_bus_stall', + 50: 'ge_hs_stall_tfmm_fifo_full', + 51: 'ge_gs_issue_rtr_stalled', + 52: 'ge_gsprim_stalled_esvert', + 53: 'ge_gsthread_stalled', + 54: 'ge_ngg_attr_grp_alloc', + 55: 'ge_ngg_attr_discard_alloc', + 56: 'ge_ngg_pc_space_not_avail', + 57: 'ge_ngg_agm_req_stall', + 58: 'ge_ngg_spi_esvert_partial_eov', + 59: 'ge_ngg_spi_gsprim_partial_eov', + 60: 'ge_spi_gsgrp_valid', + 61: 'ge_ngg_attr_grp_latency', + 62: 'ge_ngg_reuse_prim_limit_hit', + 63: 'ge_ngg_reuse_vert_limit_hit', + 64: 'ge_te11_con_stall', + 65: 'ge_te11_compactor_starved', + 66: 'ge_ngg_stall_tess_off_tess_on', + 67: 'ge_ngg_stall_tess_on_tess_off', + 68: 'ge_merged_lses_vert_stalled', + 69: 'ge_merged_hsgs_vert_stalled', + 70: 'ge_merged_hsgs_grp_stalled', + 71: 'ge_merge_lses_fifo_blocked', + 72: 'ge_merge_hsgs_fifo_blocked', + 73: 'ge_merge_lses_vert_switch', + 74: 'ge_merge_hsgs_vert_switch', + 75: 'ge_merge_hsgs_grp_switch', + 76: 'ge_merge_gsgrp_rdy_pending_verts', + 77: 'ge_merge_hsgrp_rdy_pending_verts', + 78: 'ge_se_ds_cache_hits', + 79: 'ge_se_api_vs_verts', + 80: 'ge_se_api_ds_verts', + 81: 'ge_se_combined_busy', + 82: 'ge_spi_lsvert_send', + 83: 'ge_spi_hsvert_send', + 84: 'ge_ngg_attr_grp_wasted', + 85: 'ge_spi_gssubgrp_stalled', + 86: 'ge_ngg_attr_null_dealloc', + 87: 'ge_ngg_busy_base', +} +ge_se_ds_prims = 0 +ge_se_es_thread_groups = 1 +ge_se_esvert_stalled_gsprim = 2 +ge_se_hs_tfm_stall = 3 +ge_se_hs_tgs_active_high_water_mark = 4 +ge_se_hs_thread_groups = 5 +ge_se_reused_es_indices = 6 +ge_se_sclk_ngg_vld = 7 +ge_se_sclk_te11_vld = 8 +ge_se_spi_esvert_eov = 9 +ge_se_spi_esvert_stalled = 10 +ge_se_spi_esvert_starved_busy = 11 +ge_se_spi_esvert_valid = 12 +ge_se_spi_gsprim_cont = 13 +ge_se_spi_gsprim_eov = 14 +ge_se_spi_gsprim_stalled = 15 +ge_se_spi_gsprim_starved_busy = 16 +ge_se_spi_gsprim_valid = 17 +ge_se_spi_gssubgrp_is_event = 18 +ge_se_spi_gssubgrp_send = 19 +ge_se_spi_hsvert_eov = 20 +ge_se_spi_hsvert_stalled = 21 +ge_se_spi_hsvert_starved_busy = 22 +ge_se_spi_hsvert_valid = 23 +ge_se_spi_hsgrp_is_event = 24 +ge_se_spi_hsgrp_send = 25 +ge_se_spi_lsvert_eov = 26 +ge_se_spi_lsvert_stalled = 27 +ge_se_spi_lsvert_starved_busy = 28 +ge_se_spi_lsvert_valid = 29 +ge_se_spi_hsvert_fifo_full_stall = 30 +ge_se_spi_tgrp_fifo_stall = 31 +ge_spi_hsgrp_spi_stall = 32 +ge_se_spi_gssubgrp_event_window_active = 33 +ge_se_hs_input_stall = 34 +ge_se_sending_vert_or_prim = 35 +ge_se_sclk_input_vld = 36 +ge_spi_lswave_fifo_full_stall = 37 +ge_spi_hswave_fifo_full_stall = 38 +ge_hs_tif_stall = 39 +ge_csb_spi_bp = 40 +ge_ngg_starving_for_wave_id = 41 +ge_pa0_csb_eop = 42 +ge_ngg_starved_idle = 43 +ge_gsprim_send = 44 +ge_esvert_send = 45 +ge_ngg_starved_after_work = 46 +ge_ngg_subgrp_fifo_stall = 47 +ge_ngg_ord_id_req_stall = 48 +ge_ngg_indx_bus_stall = 49 +ge_hs_stall_tfmm_fifo_full = 50 +ge_gs_issue_rtr_stalled = 51 +ge_gsprim_stalled_esvert = 52 +ge_gsthread_stalled = 53 +ge_ngg_attr_grp_alloc = 54 +ge_ngg_attr_discard_alloc = 55 +ge_ngg_pc_space_not_avail = 56 +ge_ngg_agm_req_stall = 57 +ge_ngg_spi_esvert_partial_eov = 58 +ge_ngg_spi_gsprim_partial_eov = 59 +ge_spi_gsgrp_valid = 60 +ge_ngg_attr_grp_latency = 61 +ge_ngg_reuse_prim_limit_hit = 62 +ge_ngg_reuse_vert_limit_hit = 63 +ge_te11_con_stall = 64 +ge_te11_compactor_starved = 65 +ge_ngg_stall_tess_off_tess_on = 66 +ge_ngg_stall_tess_on_tess_off = 67 +ge_merged_lses_vert_stalled = 68 +ge_merged_hsgs_vert_stalled = 69 +ge_merged_hsgs_grp_stalled = 70 +ge_merge_lses_fifo_blocked = 71 +ge_merge_hsgs_fifo_blocked = 72 +ge_merge_lses_vert_switch = 73 +ge_merge_hsgs_vert_switch = 74 +ge_merge_hsgs_grp_switch = 75 +ge_merge_gsgrp_rdy_pending_verts = 76 +ge_merge_hsgrp_rdy_pending_verts = 77 +ge_se_ds_cache_hits = 78 +ge_se_api_vs_verts = 79 +ge_se_api_ds_verts = 80 +ge_se_combined_busy = 81 +ge_spi_lsvert_send = 82 +ge_spi_hsvert_send = 83 +ge_ngg_attr_grp_wasted = 84 +ge_spi_gssubgrp_stalled = 85 +ge_ngg_attr_null_dealloc = 86 +ge_ngg_busy_base = 87 +GE2_SE_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DETECT_ONE' +VGT_DETECT_ONE__enumvalues = { + 0: 'ENABLE_TF1_OPT', + 1: 'DISABLE_TF1_OPT', +} +ENABLE_TF1_OPT = 0 +DISABLE_TF1_OPT = 1 +VGT_DETECT_ONE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DETECT_ZERO' +VGT_DETECT_ZERO__enumvalues = { + 0: 'ENABLE_TF0_OPT', + 1: 'DISABLE_TF0_OPT', +} +ENABLE_TF0_OPT = 0 +DISABLE_TF0_OPT = 1 +VGT_DETECT_ZERO = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DIST_MODE' +VGT_DIST_MODE__enumvalues = { + 0: 'NO_DIST', + 1: 'PATCHES', + 2: 'DONUTS', + 3: 'TRAPEZOIDS', +} +NO_DIST = 0 +PATCHES = 1 +DONUTS = 2 +TRAPEZOIDS = 3 +VGT_DIST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_INDEX_SIZE' +VGT_DI_INDEX_SIZE__enumvalues = { + 0: 'DI_INDEX_SIZE_16_BIT', + 1: 'DI_INDEX_SIZE_32_BIT', + 2: 'DI_INDEX_SIZE_8_BIT', +} +DI_INDEX_SIZE_16_BIT = 0 +DI_INDEX_SIZE_32_BIT = 1 +DI_INDEX_SIZE_8_BIT = 2 +VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_PRIM_TYPE' +VGT_DI_PRIM_TYPE__enumvalues = { + 0: 'DI_PT_NONE', + 1: 'DI_PT_POINTLIST', + 2: 'DI_PT_LINELIST', + 3: 'DI_PT_LINESTRIP', + 4: 'DI_PT_TRILIST', + 5: 'DI_PT_TRIFAN', + 6: 'DI_PT_TRISTRIP', + 7: 'DI_PT_2D_RECTANGLE', + 8: 'DI_PT_UNUSED_1', + 9: 'DI_PT_PATCH', + 10: 'DI_PT_LINELIST_ADJ', + 11: 'DI_PT_LINESTRIP_ADJ', + 12: 'DI_PT_TRILIST_ADJ', + 13: 'DI_PT_TRISTRIP_ADJ', + 14: 'DI_PT_UNUSED_3', + 15: 'DI_PT_UNUSED_4', + 16: 'DI_PT_UNUSED_5', + 17: 'DI_PT_RECTLIST', + 18: 'DI_PT_LINELOOP', + 19: 'DI_PT_QUADLIST', + 20: 'DI_PT_QUADSTRIP', + 21: 'DI_PT_POLYGON', +} +DI_PT_NONE = 0 +DI_PT_POINTLIST = 1 +DI_PT_LINELIST = 2 +DI_PT_LINESTRIP = 3 +DI_PT_TRILIST = 4 +DI_PT_TRIFAN = 5 +DI_PT_TRISTRIP = 6 +DI_PT_2D_RECTANGLE = 7 +DI_PT_UNUSED_1 = 8 +DI_PT_PATCH = 9 +DI_PT_LINELIST_ADJ = 10 +DI_PT_LINESTRIP_ADJ = 11 +DI_PT_TRILIST_ADJ = 12 +DI_PT_TRISTRIP_ADJ = 13 +DI_PT_UNUSED_3 = 14 +DI_PT_UNUSED_4 = 15 +DI_PT_UNUSED_5 = 16 +DI_PT_RECTLIST = 17 +DI_PT_LINELOOP = 18 +DI_PT_QUADLIST = 19 +DI_PT_QUADSTRIP = 20 +DI_PT_POLYGON = 21 +VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_SOURCE_SELECT' +VGT_DI_SOURCE_SELECT__enumvalues = { + 0: 'DI_SRC_SEL_DMA', + 1: 'DI_SRC_SEL_IMMEDIATE', + 2: 'DI_SRC_SEL_AUTO_INDEX', + 3: 'DI_SRC_SEL_RESERVED', +} +DI_SRC_SEL_DMA = 0 +DI_SRC_SEL_IMMEDIATE = 1 +DI_SRC_SEL_AUTO_INDEX = 2 +DI_SRC_SEL_RESERVED = 3 +VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_BUF_TYPE' +VGT_DMA_BUF_TYPE__enumvalues = { + 0: 'VGT_DMA_BUF_MEM', + 1: 'VGT_DMA_BUF_RING', + 2: 'VGT_DMA_BUF_SETUP', + 3: 'VGT_DMA_PTR_UPDATE', +} +VGT_DMA_BUF_MEM = 0 +VGT_DMA_BUF_RING = 1 +VGT_DMA_BUF_SETUP = 2 +VGT_DMA_PTR_UPDATE = 3 +VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_SWAP_MODE' +VGT_DMA_SWAP_MODE__enumvalues = { + 0: 'VGT_DMA_SWAP_NONE', + 1: 'VGT_DMA_SWAP_16_BIT', + 2: 'VGT_DMA_SWAP_32_BIT', + 3: 'VGT_DMA_SWAP_WORD', +} +VGT_DMA_SWAP_NONE = 0 +VGT_DMA_SWAP_16_BIT = 1 +VGT_DMA_SWAP_32_BIT = 2 +VGT_DMA_SWAP_WORD = 3 +VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_EVENT_TYPE' +VGT_EVENT_TYPE__enumvalues = { + 0: 'Reserved_0x00', + 1: 'SAMPLE_STREAMOUTSTATS1', + 2: 'SAMPLE_STREAMOUTSTATS2', + 3: 'SAMPLE_STREAMOUTSTATS3', + 4: 'CACHE_FLUSH_TS', + 5: 'CONTEXT_DONE', + 6: 'CACHE_FLUSH', + 7: 'CS_PARTIAL_FLUSH', + 8: 'VGT_STREAMOUT_SYNC', + 9: 'EVENT_STATE_CHANGE', + 10: 'VGT_STREAMOUT_RESET', + 11: 'END_OF_PIPE_INCR_DE', + 12: 'END_OF_PIPE_IB_END', + 13: 'RST_PIX_CNT', + 14: 'BREAK_BATCH', + 15: 'VS_PARTIAL_FLUSH', + 16: 'PS_PARTIAL_FLUSH', + 17: 'FLUSH_HS_OUTPUT', + 18: 'FLUSH_DFSM', + 19: 'RESET_TO_LOWEST_VGT', + 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', + 21: 'WAIT_SYNC', + 22: 'CACHE_FLUSH_AND_INV_EVENT', + 23: 'PERFCOUNTER_START', + 24: 'PERFCOUNTER_STOP', + 25: 'PIPELINESTAT_START', + 26: 'PIPELINESTAT_STOP', + 27: 'PERFCOUNTER_SAMPLE', + 28: 'FLUSH_ES_OUTPUT', + 29: 'BIN_CONF_OVERRIDE_CHECK', + 30: 'SAMPLE_PIPELINESTAT', + 31: 'SO_VGTSTREAMOUT_FLUSH', + 32: 'SAMPLE_STREAMOUTSTATS', + 33: 'RESET_VTX_CNT', + 34: 'BLOCK_CONTEXT_DONE', + 35: 'CS_CONTEXT_DONE', + 36: 'VGT_FLUSH', + 37: 'TGID_ROLLOVER', + 38: 'SQ_NON_EVENT', + 39: 'SC_SEND_DB_VPZ', + 40: 'BOTTOM_OF_PIPE_TS', + 41: 'FLUSH_SX_TS', + 42: 'DB_CACHE_FLUSH_AND_INV', + 43: 'FLUSH_AND_INV_DB_DATA_TS', + 44: 'FLUSH_AND_INV_DB_META', + 45: 'FLUSH_AND_INV_CB_DATA_TS', + 46: 'FLUSH_AND_INV_CB_META', + 47: 'CS_DONE', + 48: 'PS_DONE', + 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', + 50: 'SX_CB_RAT_ACK_REQUEST', + 51: 'THREAD_TRACE_START', + 52: 'THREAD_TRACE_STOP', + 53: 'THREAD_TRACE_MARKER', + 54: 'THREAD_TRACE_DRAW', + 55: 'THREAD_TRACE_FINISH', + 56: 'PIXEL_PIPE_STAT_CONTROL', + 57: 'PIXEL_PIPE_STAT_DUMP', + 58: 'PIXEL_PIPE_STAT_RESET', + 59: 'CONTEXT_SUSPEND', + 60: 'OFFCHIP_HS_DEALLOC', + 61: 'ENABLE_NGG_PIPELINE', + 62: 'ENABLE_PIPELINE_NOT_USED', + 63: 'DRAW_DONE', +} +Reserved_0x00 = 0 +SAMPLE_STREAMOUTSTATS1 = 1 +SAMPLE_STREAMOUTSTATS2 = 2 +SAMPLE_STREAMOUTSTATS3 = 3 +CACHE_FLUSH_TS = 4 +CONTEXT_DONE = 5 +CACHE_FLUSH = 6 +CS_PARTIAL_FLUSH = 7 +VGT_STREAMOUT_SYNC = 8 +EVENT_STATE_CHANGE = 9 +VGT_STREAMOUT_RESET = 10 +END_OF_PIPE_INCR_DE = 11 +END_OF_PIPE_IB_END = 12 +RST_PIX_CNT = 13 +BREAK_BATCH = 14 +VS_PARTIAL_FLUSH = 15 +PS_PARTIAL_FLUSH = 16 +FLUSH_HS_OUTPUT = 17 +FLUSH_DFSM = 18 +RESET_TO_LOWEST_VGT = 19 +CACHE_FLUSH_AND_INV_TS_EVENT = 20 +WAIT_SYNC = 21 +CACHE_FLUSH_AND_INV_EVENT = 22 +PERFCOUNTER_START = 23 +PERFCOUNTER_STOP = 24 +PIPELINESTAT_START = 25 +PIPELINESTAT_STOP = 26 +PERFCOUNTER_SAMPLE = 27 +FLUSH_ES_OUTPUT = 28 +BIN_CONF_OVERRIDE_CHECK = 29 +SAMPLE_PIPELINESTAT = 30 +SO_VGTSTREAMOUT_FLUSH = 31 +SAMPLE_STREAMOUTSTATS = 32 +RESET_VTX_CNT = 33 +BLOCK_CONTEXT_DONE = 34 +CS_CONTEXT_DONE = 35 +VGT_FLUSH = 36 +TGID_ROLLOVER = 37 +SQ_NON_EVENT = 38 +SC_SEND_DB_VPZ = 39 +BOTTOM_OF_PIPE_TS = 40 +FLUSH_SX_TS = 41 +DB_CACHE_FLUSH_AND_INV = 42 +FLUSH_AND_INV_DB_DATA_TS = 43 +FLUSH_AND_INV_DB_META = 44 +FLUSH_AND_INV_CB_DATA_TS = 45 +FLUSH_AND_INV_CB_META = 46 +CS_DONE = 47 +PS_DONE = 48 +FLUSH_AND_INV_CB_PIXEL_DATA = 49 +SX_CB_RAT_ACK_REQUEST = 50 +THREAD_TRACE_START = 51 +THREAD_TRACE_STOP = 52 +THREAD_TRACE_MARKER = 53 +THREAD_TRACE_DRAW = 54 +THREAD_TRACE_FINISH = 55 +PIXEL_PIPE_STAT_CONTROL = 56 +PIXEL_PIPE_STAT_DUMP = 57 +PIXEL_PIPE_STAT_RESET = 58 +CONTEXT_SUSPEND = 59 +OFFCHIP_HS_DEALLOC = 60 +ENABLE_NGG_PIPELINE = 61 +ENABLE_PIPELINE_NOT_USED = 62 +DRAW_DONE = 63 +VGT_EVENT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GROUP_CONV_SEL' +VGT_GROUP_CONV_SEL__enumvalues = { + 0: 'VGT_GRP_INDEX_16', + 1: 'VGT_GRP_INDEX_32', + 2: 'VGT_GRP_UINT_16', + 3: 'VGT_GRP_UINT_32', + 4: 'VGT_GRP_SINT_16', + 5: 'VGT_GRP_SINT_32', + 6: 'VGT_GRP_FLOAT_32', + 7: 'VGT_GRP_AUTO_PRIM', + 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', +} +VGT_GRP_INDEX_16 = 0 +VGT_GRP_INDEX_32 = 1 +VGT_GRP_UINT_16 = 2 +VGT_GRP_UINT_32 = 3 +VGT_GRP_SINT_16 = 4 +VGT_GRP_SINT_32 = 5 +VGT_GRP_FLOAT_32 = 6 +VGT_GRP_AUTO_PRIM = 7 +VGT_GRP_FIX_1_23_TO_FLOAT = 8 +VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_MODE_TYPE' +VGT_GS_MODE_TYPE__enumvalues = { + 0: 'GS_OFF', + 1: 'GS_SCENARIO_A', + 2: 'GS_SCENARIO_B', + 3: 'GS_SCENARIO_G', + 4: 'GS_SCENARIO_C', + 5: 'SPRITE_EN', +} +GS_OFF = 0 +GS_SCENARIO_A = 1 +GS_SCENARIO_B = 2 +GS_SCENARIO_G = 3 +GS_SCENARIO_C = 4 +SPRITE_EN = 5 +VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_OUTPRIM_TYPE' +VGT_GS_OUTPRIM_TYPE__enumvalues = { + 0: 'POINTLIST', + 1: 'LINESTRIP', + 2: 'TRISTRIP', + 3: 'RECT_2D', + 4: 'RECTLIST', +} +POINTLIST = 0 +LINESTRIP = 1 +TRISTRIP = 2 +RECT_2D = 3 +RECTLIST = 4 +VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_INDEX_TYPE_MODE' +VGT_INDEX_TYPE_MODE__enumvalues = { + 0: 'VGT_INDEX_16', + 1: 'VGT_INDEX_32', + 2: 'VGT_INDEX_8', +} +VGT_INDEX_16 = 0 +VGT_INDEX_32 = 1 +VGT_INDEX_8 = 2 +VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUTPATH_SELECT' +VGT_OUTPATH_SELECT__enumvalues = { + 0: 'VGT_OUTPATH_VTX_REUSE', + 1: 'VGT_OUTPATH_GS_BLOCK', + 2: 'VGT_OUTPATH_HS_BLOCK', + 3: 'VGT_OUTPATH_PRIM_GEN', + 4: 'VGT_OUTPATH_TE_PRIM_GEN', + 5: 'VGT_OUTPATH_TE_GS_BLOCK', + 6: 'VGT_OUTPATH_TE_OUTPUT', +} +VGT_OUTPATH_VTX_REUSE = 0 +VGT_OUTPATH_GS_BLOCK = 1 +VGT_OUTPATH_HS_BLOCK = 2 +VGT_OUTPATH_PRIM_GEN = 3 +VGT_OUTPATH_TE_PRIM_GEN = 4 +VGT_OUTPATH_TE_GS_BLOCK = 5 +VGT_OUTPATH_TE_OUTPUT = 6 +VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUT_PRIM_TYPE' +VGT_OUT_PRIM_TYPE__enumvalues = { + 0: 'VGT_OUT_POINT', + 1: 'VGT_OUT_LINE', + 2: 'VGT_OUT_TRI', + 3: 'VGT_OUT_2D_RECT', + 4: 'VGT_OUT_RECT_V0', + 5: 'VGT_OUT_DUMMY_1', + 6: 'VGT_OUT_DUMMY_2', + 7: 'VGT_OUT_DUMMY_3', + 8: 'VGT_OUT_PATCH', + 9: 'VGT_OUT_LINE_ADJ', + 10: 'VGT_OUT_TRI_ADJ', +} +VGT_OUT_POINT = 0 +VGT_OUT_LINE = 1 +VGT_OUT_TRI = 2 +VGT_OUT_2D_RECT = 3 +VGT_OUT_RECT_V0 = 4 +VGT_OUT_DUMMY_1 = 5 +VGT_OUT_DUMMY_2 = 6 +VGT_OUT_DUMMY_3 = 7 +VGT_OUT_PATCH = 8 +VGT_OUT_LINE_ADJ = 9 +VGT_OUT_TRI_ADJ = 10 +VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_RDREQ_POLICY' +VGT_RDREQ_POLICY__enumvalues = { + 0: 'VGT_POLICY_LRU', + 1: 'VGT_POLICY_STREAM', + 2: 'VGT_POLICY_BYPASS', +} +VGT_POLICY_LRU = 0 +VGT_POLICY_STREAM = 1 +VGT_POLICY_BYPASS = 2 +VGT_RDREQ_POLICY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_SPEC_DATA_READ' +VGT_SPEC_DATA_READ__enumvalues = { + 0: 'VGT_SPEC_DATA_READ_AUTO', + 1: 'VGT_SPEC_DATA_READ_FORCE_ON', + 2: 'VGT_SPEC_DATA_READ_FORCE_OFF', +} +VGT_SPEC_DATA_READ_AUTO = 0 +VGT_SPEC_DATA_READ_FORCE_ON = 1 +VGT_SPEC_DATA_READ_FORCE_OFF = 2 +VGT_SPEC_DATA_READ = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_GS_EN' +VGT_STAGES_GS_EN__enumvalues = { + 0: 'GS_STAGE_OFF', + 1: 'GS_STAGE_ON', +} +GS_STAGE_OFF = 0 +GS_STAGE_ON = 1 +VGT_STAGES_GS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_HS_EN' +VGT_STAGES_HS_EN__enumvalues = { + 0: 'HS_STAGE_OFF', + 1: 'HS_STAGE_ON', +} +HS_STAGE_OFF = 0 +HS_STAGE_ON = 1 +VGT_STAGES_HS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TEMPORAL' +VGT_TEMPORAL__enumvalues = { + 0: 'VGT_TEMPORAL_NORMAL', + 1: 'VGT_TEMPORAL_HIGH_PRIORITY', + 2: 'VGT_TEMPORAL_STREAM', + 3: 'VGT_TEMPORAL_DISCARD', +} +VGT_TEMPORAL_NORMAL = 0 +VGT_TEMPORAL_HIGH_PRIORITY = 1 +VGT_TEMPORAL_STREAM = 2 +VGT_TEMPORAL_DISCARD = 3 +VGT_TEMPORAL = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_PARTITION' +VGT_TESS_PARTITION__enumvalues = { + 0: 'PART_INTEGER', + 1: 'PART_POW2', + 2: 'PART_FRAC_ODD', + 3: 'PART_FRAC_EVEN', +} +PART_INTEGER = 0 +PART_POW2 = 1 +PART_FRAC_ODD = 2 +PART_FRAC_EVEN = 3 +VGT_TESS_PARTITION = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TOPOLOGY' +VGT_TESS_TOPOLOGY__enumvalues = { + 0: 'OUTPUT_POINT', + 1: 'OUTPUT_LINE', + 2: 'OUTPUT_TRIANGLE_CW', + 3: 'OUTPUT_TRIANGLE_CCW', +} +OUTPUT_POINT = 0 +OUTPUT_LINE = 1 +OUTPUT_TRIANGLE_CW = 2 +OUTPUT_TRIANGLE_CCW = 3 +VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TYPE' +VGT_TESS_TYPE__enumvalues = { + 0: 'TESS_ISOLINE', + 1: 'TESS_TRIANGLE', + 2: 'TESS_QUAD', +} +TESS_ISOLINE = 0 +TESS_TRIANGLE = 1 +TESS_QUAD = 2 +VGT_TESS_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_REG_XFER' +WD_IA_DRAW_REG_XFER__enumvalues = { + 0: 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', + 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', + 2: 'WD_IA_DRAW_REG_XFER_VGT_GS_OUT_PRIM_TYPE', + 3: 'WD_IA_DRAW_REG_XFER_GE_CNTL', + 4: 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVE_TYPE', + 5: 'WD_IA_DRAW_REG_XFER_GFX_PIPE_CONTROL', + 6: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', + 7: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', + 8: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', + 9: 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', + 10: 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', + 11: 'WD_IA_DRAW_REG_XFER_VGT_DRAW_PAYLOAD_CNTL', + 12: 'WD_IA_DRAW_REG_XFER_GE_STEREO_CNTL', + 13: 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_RESET', + 14: 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_EN', + 15: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR1', + 16: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR2', + 17: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR3', + 18: 'WD_IA_DRAW_REG_XFER_GE_VRS_RATE', + 19: 'WD_IA_DRAW_REG_XFER_GE_PC_ALLOC', + 20: 'WD_IA_DRAW_REG_XFER_SPI_SHADER_GS_OUT_CONFIG_PS', + 21: 'WD_IA_DRAW_REG_XFER_GE_GS_THROTTLE', +} +WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0 +WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 +WD_IA_DRAW_REG_XFER_VGT_GS_OUT_PRIM_TYPE = 2 +WD_IA_DRAW_REG_XFER_GE_CNTL = 3 +WD_IA_DRAW_REG_XFER_VGT_PRIMITIVE_TYPE = 4 +WD_IA_DRAW_REG_XFER_GFX_PIPE_CONTROL = 5 +WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 6 +WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 7 +WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 8 +WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 9 +WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 10 +WD_IA_DRAW_REG_XFER_VGT_DRAW_PAYLOAD_CNTL = 11 +WD_IA_DRAW_REG_XFER_GE_STEREO_CNTL = 12 +WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_RESET = 13 +WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_EN = 14 +WD_IA_DRAW_REG_XFER_GE_USER_VGPR1 = 15 +WD_IA_DRAW_REG_XFER_GE_USER_VGPR2 = 16 +WD_IA_DRAW_REG_XFER_GE_USER_VGPR3 = 17 +WD_IA_DRAW_REG_XFER_GE_VRS_RATE = 18 +WD_IA_DRAW_REG_XFER_GE_PC_ALLOC = 19 +WD_IA_DRAW_REG_XFER_SPI_SHADER_GS_OUT_CONFIG_PS = 20 +WD_IA_DRAW_REG_XFER_GE_GS_THROTTLE = 21 +WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_SOURCE' +WD_IA_DRAW_SOURCE__enumvalues = { + 0: 'WD_IA_DRAW_SOURCE_DMA', + 1: 'WD_IA_DRAW_SOURCE_IMMD', + 2: 'WD_IA_DRAW_SOURCE_AUTO', + 3: 'WD_IA_DRAW_SOURCE_OPAQ', +} +WD_IA_DRAW_SOURCE_DMA = 0 +WD_IA_DRAW_SOURCE_IMMD = 1 +WD_IA_DRAW_SOURCE_AUTO = 2 +WD_IA_DRAW_SOURCE_OPAQ = 3 +WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_TYPE' +WD_IA_DRAW_TYPE__enumvalues = { + 0: 'WD_IA_DRAW_TYPE_DI_MM0', + 1: 'WD_IA_DRAW_TYPE_INDX_OFF', + 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', + 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 4: 'WD_IA_DRAW_TYPE_REG_XFER', + 5: 'WD_IA_DRAW_TYPE_MIN_INDX', + 6: 'WD_IA_DRAW_TYPE_MAX_INDX', + 7: 'WD_IA_DRAW_TYPE_IMM_DATA', +} +WD_IA_DRAW_TYPE_DI_MM0 = 0 +WD_IA_DRAW_TYPE_INDX_OFF = 1 +WD_IA_DRAW_TYPE_EVENT_INIT = 2 +WD_IA_DRAW_TYPE_EVENT_ADDR = 3 +WD_IA_DRAW_TYPE_REG_XFER = 4 +WD_IA_DRAW_TYPE_MIN_INDX = 5 +WD_IA_DRAW_TYPE_MAX_INDX = 6 +WD_IA_DRAW_TYPE_IMM_DATA = 7 +WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CHA_PERF_SEL' +CHA_PERF_SEL__enumvalues = { + 0: 'CHA_PERF_SEL_BUSY', + 1: 'CHA_PERF_SEL_STALL_CHC0', + 2: 'CHA_PERF_SEL_STALL_CHC1', + 3: 'CHA_PERF_SEL_STALL_CHC2', + 4: 'CHA_PERF_SEL_STALL_CHC3', + 5: 'CHA_PERF_SEL_REQUEST_CHC0', + 6: 'CHA_PERF_SEL_REQUEST_CHC1', + 7: 'CHA_PERF_SEL_REQUEST_CHC2', + 8: 'CHA_PERF_SEL_REQUEST_CHC3', + 9: 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', + 10: 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', + 11: 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', + 12: 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', + 13: 'CHA_PERF_SEL_IO_32B_WDS_CHC0', + 14: 'CHA_PERF_SEL_IO_32B_WDS_CHC1', + 15: 'CHA_PERF_SEL_IO_32B_WDS_CHC2', + 16: 'CHA_PERF_SEL_IO_32B_WDS_CHC3', + 17: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', + 18: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', + 19: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', + 20: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', + 21: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', + 22: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', + 23: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', + 24: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', + 25: 'CHA_PERF_SEL_ARB_REQUESTS', + 26: 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', + 27: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', + 28: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', + 29: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', + 30: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', + 31: 'CHA_PERF_SEL_CYCLE', +} +CHA_PERF_SEL_BUSY = 0 +CHA_PERF_SEL_STALL_CHC0 = 1 +CHA_PERF_SEL_STALL_CHC1 = 2 +CHA_PERF_SEL_STALL_CHC2 = 3 +CHA_PERF_SEL_STALL_CHC3 = 4 +CHA_PERF_SEL_REQUEST_CHC0 = 5 +CHA_PERF_SEL_REQUEST_CHC1 = 6 +CHA_PERF_SEL_REQUEST_CHC2 = 7 +CHA_PERF_SEL_REQUEST_CHC3 = 8 +CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 9 +CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 10 +CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 11 +CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 12 +CHA_PERF_SEL_IO_32B_WDS_CHC0 = 13 +CHA_PERF_SEL_IO_32B_WDS_CHC1 = 14 +CHA_PERF_SEL_IO_32B_WDS_CHC2 = 15 +CHA_PERF_SEL_IO_32B_WDS_CHC3 = 16 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 17 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 18 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 19 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 20 +CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 21 +CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 22 +CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 23 +CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 24 +CHA_PERF_SEL_ARB_REQUESTS = 25 +CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 26 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 27 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 28 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 29 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 30 +CHA_PERF_SEL_CYCLE = 31 +CHA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CHC_PERF_SEL' +CHC_PERF_SEL__enumvalues = { + 0: 'CHC_PERF_SEL_CYCLE', + 1: 'CHC_PERF_SEL_BUSY', + 2: 'CHC_PERF_SEL_STARVE', + 3: 'CHC_PERF_SEL_ARB_RET_LEVEL', + 4: 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', + 5: 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', + 6: 'CHC_PERF_SEL_REQ', + 7: 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', + 8: 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 9: 'CHC_PERF_SEL_REQ_NOP_ACK', + 10: 'CHC_PERF_SEL_REQ_NOP_RTN0', + 11: 'CHC_PERF_SEL_REQ_READ', + 12: 'CHC_PERF_SEL_REQ_READ_128B', + 13: 'CHC_PERF_SEL_REQ_READ_32B', + 14: 'CHC_PERF_SEL_REQ_READ_64B', + 15: 'CHC_PERF_SEL_REQ_WRITE', + 16: 'CHC_PERF_SEL_REQ_WRITE_32B', + 17: 'CHC_PERF_SEL_REQ_WRITE_64B', + 18: 'CHC_PERF_SEL_STALL_GL2_GL1', + 19: 'CHC_PERF_SEL_STALL_BUFFER_FULL', + 20: 'CHC_PERF_SEL_REQ_CLIENT0', + 21: 'CHC_PERF_SEL_REQ_CLIENT1', + 22: 'CHC_PERF_SEL_REQ_CLIENT2', + 23: 'CHC_PERF_SEL_REQ_CLIENT3', + 24: 'CHC_PERF_SEL_REQ_CLIENT4', + 25: 'CHC_PERF_SEL_REQ_CLIENT5', + 26: 'CHC_PERF_SEL_REQ_CLIENT6', + 27: 'CHC_PERF_SEL_REQ_CLIENT7', + 28: 'CHC_PERF_SEL_REQ_CLIENT8', + 29: 'CHC_PERF_SEL_REQ_CLIENT9', + 30: 'CHC_PERF_SEL_REQ_CLIENT10', + 31: 'CHC_PERF_SEL_REQ_CLIENT11', + 32: 'CHC_PERF_SEL_REQ_CLIENT12', + 33: 'CHC_PERF_SEL_REQ_CLIENT13', + 34: 'CHC_PERF_SEL_REQ_CLIENT14', + 35: 'CHC_PERF_SEL_REQ_CLIENT15', + 36: 'CHC_PERF_SEL_REQ_CLIENT16', + 37: 'CHC_PERF_SEL_REQ_CLIENT17', + 38: 'CHC_PERF_SEL_REQ_CLIENT18', + 39: 'CHC_PERF_SEL_REQ_CLIENT19', + 40: 'CHC_PERF_SEL_REQ_CLIENT20', + 41: 'CHC_PERF_SEL_REQ_CLIENT21', + 42: 'CHC_PERF_SEL_REQ_CLIENT22', + 43: 'CHC_PERF_SEL_REQ_CLIENT23', +} +CHC_PERF_SEL_CYCLE = 0 +CHC_PERF_SEL_BUSY = 1 +CHC_PERF_SEL_STARVE = 2 +CHC_PERF_SEL_ARB_RET_LEVEL = 3 +CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 4 +CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 +CHC_PERF_SEL_REQ = 6 +CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 +CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 +CHC_PERF_SEL_REQ_NOP_ACK = 9 +CHC_PERF_SEL_REQ_NOP_RTN0 = 10 +CHC_PERF_SEL_REQ_READ = 11 +CHC_PERF_SEL_REQ_READ_128B = 12 +CHC_PERF_SEL_REQ_READ_32B = 13 +CHC_PERF_SEL_REQ_READ_64B = 14 +CHC_PERF_SEL_REQ_WRITE = 15 +CHC_PERF_SEL_REQ_WRITE_32B = 16 +CHC_PERF_SEL_REQ_WRITE_64B = 17 +CHC_PERF_SEL_STALL_GL2_GL1 = 18 +CHC_PERF_SEL_STALL_BUFFER_FULL = 19 +CHC_PERF_SEL_REQ_CLIENT0 = 20 +CHC_PERF_SEL_REQ_CLIENT1 = 21 +CHC_PERF_SEL_REQ_CLIENT2 = 22 +CHC_PERF_SEL_REQ_CLIENT3 = 23 +CHC_PERF_SEL_REQ_CLIENT4 = 24 +CHC_PERF_SEL_REQ_CLIENT5 = 25 +CHC_PERF_SEL_REQ_CLIENT6 = 26 +CHC_PERF_SEL_REQ_CLIENT7 = 27 +CHC_PERF_SEL_REQ_CLIENT8 = 28 +CHC_PERF_SEL_REQ_CLIENT9 = 29 +CHC_PERF_SEL_REQ_CLIENT10 = 30 +CHC_PERF_SEL_REQ_CLIENT11 = 31 +CHC_PERF_SEL_REQ_CLIENT12 = 32 +CHC_PERF_SEL_REQ_CLIENT13 = 33 +CHC_PERF_SEL_REQ_CLIENT14 = 34 +CHC_PERF_SEL_REQ_CLIENT15 = 35 +CHC_PERF_SEL_REQ_CLIENT16 = 36 +CHC_PERF_SEL_REQ_CLIENT17 = 37 +CHC_PERF_SEL_REQ_CLIENT18 = 38 +CHC_PERF_SEL_REQ_CLIENT19 = 39 +CHC_PERF_SEL_REQ_CLIENT20 = 40 +CHC_PERF_SEL_REQ_CLIENT21 = 41 +CHC_PERF_SEL_REQ_CLIENT22 = 42 +CHC_PERF_SEL_REQ_CLIENT23 = 43 +CHC_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_PERF_SEL' +GRBM_PERF_SEL__enumvalues = { + 0: 'GRBM_PERF_SEL_COUNT', + 1: 'GRBM_PERF_SEL_USER_DEFINED', + 2: 'GRBM_PERF_SEL_GUI_ACTIVE', + 3: 'GRBM_PERF_SEL_CP_BUSY', + 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', + 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', + 6: 'GRBM_PERF_SEL_CB_BUSY', + 7: 'GRBM_PERF_SEL_DB_BUSY', + 8: 'GRBM_PERF_SEL_PA_BUSY', + 9: 'GRBM_PERF_SEL_SC_BUSY', + 11: 'GRBM_PERF_SEL_SPI_BUSY', + 12: 'GRBM_PERF_SEL_SX_BUSY', + 13: 'GRBM_PERF_SEL_TA_BUSY', + 14: 'GRBM_PERF_SEL_CB_CLEAN', + 15: 'GRBM_PERF_SEL_DB_CLEAN', + 26: 'GRBM_PERF_SEL_BCI_BUSY', + 27: 'GRBM_PERF_SEL_RLC_BUSY', + 28: 'GRBM_PERF_SEL_TCP_BUSY', + 29: 'GRBM_PERF_SEL_CPG_BUSY', + 30: 'GRBM_PERF_SEL_CPC_BUSY', + 31: 'GRBM_PERF_SEL_CPF_BUSY', + 32: 'GRBM_PERF_SEL_GE_BUSY', + 33: 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', + 34: 'GRBM_PERF_SEL_UTCL2_BUSY', + 35: 'GRBM_PERF_SEL_EA_BUSY', + 39: 'GRBM_PERF_SEL_UTCL1_BUSY', + 40: 'GRBM_PERF_SEL_GL2CC_BUSY', + 41: 'GRBM_PERF_SEL_SDMA_BUSY', + 42: 'GRBM_PERF_SEL_CH_BUSY', + 44: 'GRBM_PERF_SEL_PMM_BUSY', + 45: 'GRBM_PERF_SEL_GUS_BUSY', + 46: 'GRBM_PERF_SEL_GL1CC_BUSY', + 47: 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', + 48: 'GRBM_PERF_SEL_GL1XCC_BUSY', + 49: 'GRBM_PERF_SEL_PC_BUSY', +} +GRBM_PERF_SEL_COUNT = 0 +GRBM_PERF_SEL_USER_DEFINED = 1 +GRBM_PERF_SEL_GUI_ACTIVE = 2 +GRBM_PERF_SEL_CP_BUSY = 3 +GRBM_PERF_SEL_CP_COHER_BUSY = 4 +GRBM_PERF_SEL_CP_DMA_BUSY = 5 +GRBM_PERF_SEL_CB_BUSY = 6 +GRBM_PERF_SEL_DB_BUSY = 7 +GRBM_PERF_SEL_PA_BUSY = 8 +GRBM_PERF_SEL_SC_BUSY = 9 +GRBM_PERF_SEL_SPI_BUSY = 11 +GRBM_PERF_SEL_SX_BUSY = 12 +GRBM_PERF_SEL_TA_BUSY = 13 +GRBM_PERF_SEL_CB_CLEAN = 14 +GRBM_PERF_SEL_DB_CLEAN = 15 +GRBM_PERF_SEL_BCI_BUSY = 26 +GRBM_PERF_SEL_RLC_BUSY = 27 +GRBM_PERF_SEL_TCP_BUSY = 28 +GRBM_PERF_SEL_CPG_BUSY = 29 +GRBM_PERF_SEL_CPC_BUSY = 30 +GRBM_PERF_SEL_CPF_BUSY = 31 +GRBM_PERF_SEL_GE_BUSY = 32 +GRBM_PERF_SEL_GE_NO_DMA_BUSY = 33 +GRBM_PERF_SEL_UTCL2_BUSY = 34 +GRBM_PERF_SEL_EA_BUSY = 35 +GRBM_PERF_SEL_UTCL1_BUSY = 39 +GRBM_PERF_SEL_GL2CC_BUSY = 40 +GRBM_PERF_SEL_SDMA_BUSY = 41 +GRBM_PERF_SEL_CH_BUSY = 42 +GRBM_PERF_SEL_PMM_BUSY = 44 +GRBM_PERF_SEL_GUS_BUSY = 45 +GRBM_PERF_SEL_GL1CC_BUSY = 46 +GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 47 +GRBM_PERF_SEL_GL1XCC_BUSY = 48 +GRBM_PERF_SEL_PC_BUSY = 49 +GRBM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPC_LATENCY_STATS_SEL' +CPC_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPC_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPC_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPC_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPC_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPC_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPC_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPC_LATENCY_STATS_SEL_INVAL_MAX', + 7: 'CPC_LATENCY_STATS_SEL_INVAL_MIN', + 8: 'CPC_LATENCY_STATS_SEL_INVAL_LAST', +} +CPC_LATENCY_STATS_SEL_XACK_MAX = 0 +CPC_LATENCY_STATS_SEL_XACK_MIN = 1 +CPC_LATENCY_STATS_SEL_XACK_LAST = 2 +CPC_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPC_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPC_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPC_LATENCY_STATS_SEL_INVAL_MAX = 6 +CPC_LATENCY_STATS_SEL_INVAL_MIN = 7 +CPC_LATENCY_STATS_SEL_INVAL_LAST = 8 +CPC_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPC_PERFCOUNT_SEL' +CPC_PERFCOUNT_SEL__enumvalues = { + 0: 'CPC_PERF_SEL_ALWAYS_COUNT', + 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_READ', + 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_WRITE', + 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_READ', + 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_WRITE', + 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 25: 'CPC_PERF_SEL_CPC_STAT_BUSY', + 26: 'CPC_PERF_SEL_CPC_STAT_IDLE', + 27: 'CPC_PERF_SEL_CPC_STAT_STALL', + 28: 'CPC_PERF_SEL_CPC_TCIU_BUSY', + 29: 'CPC_PERF_SEL_CPC_TCIU_IDLE', + 30: 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', + 31: 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', + 32: 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', + 33: 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', + 34: 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', + 35: 'CPC_PERF_SEL_CPC_GCRIU_BUSY', + 36: 'CPC_PERF_SEL_CPC_GCRIU_IDLE', + 37: 'CPC_PERF_SEL_CPC_GCRIU_STALL', + 38: 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 39: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', + 40: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', + 41: 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', + 42: 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', + 43: 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', + 44: 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', + 45: 'CPC_PERF_SEL_MES_THREAD0', + 46: 'CPC_PERF_SEL_MES_THREAD1', + 47: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 48: 'CPC_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 49: 'CPC_PERF_SEL_TCIU_READ_REQUEST_SENT', + 50: 'CPC_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 51: 'CPC_PERF_SEL_GUS_READ_REQUEST_SENT', + 52: 'CPC_PERF_SEL_MEC_THREAD0', + 53: 'CPC_PERF_SEL_MEC_THREAD1', + 54: 'CPC_PERF_SEL_MEC_THREAD2', + 55: 'CPC_PERF_SEL_MEC_THREAD3', +} +CPC_PERF_SEL_ALWAYS_COUNT = 0 +CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 +CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 +CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_READ = 9 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_WRITE = 10 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 +CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_READ = 17 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_WRITE = 18 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 +CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 +CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 +CPC_PERF_SEL_CPC_STAT_BUSY = 25 +CPC_PERF_SEL_CPC_STAT_IDLE = 26 +CPC_PERF_SEL_CPC_STAT_STALL = 27 +CPC_PERF_SEL_CPC_TCIU_BUSY = 28 +CPC_PERF_SEL_CPC_TCIU_IDLE = 29 +CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 30 +CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 31 +CPC_PERF_SEL_CPC_UTCL2IU_STALL = 32 +CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 33 +CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 34 +CPC_PERF_SEL_CPC_GCRIU_BUSY = 35 +CPC_PERF_SEL_CPC_GCRIU_IDLE = 36 +CPC_PERF_SEL_CPC_GCRIU_STALL = 37 +CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 38 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 39 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 40 +CPC_PERF_SEL_CPC_UTCL2IU_XACK = 41 +CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 42 +CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 43 +CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 44 +CPC_PERF_SEL_MES_THREAD0 = 45 +CPC_PERF_SEL_MES_THREAD1 = 46 +CPC_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 47 +CPC_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 48 +CPC_PERF_SEL_TCIU_READ_REQUEST_SENT = 49 +CPC_PERF_SEL_GUS_WRITE_REQUEST_SENT = 50 +CPC_PERF_SEL_GUS_READ_REQUEST_SENT = 51 +CPC_PERF_SEL_MEC_THREAD0 = 52 +CPC_PERF_SEL_MEC_THREAD1 = 53 +CPC_PERF_SEL_MEC_THREAD2 = 54 +CPC_PERF_SEL_MEC_THREAD3 = 55 +CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_LATENCY_STATS_SEL' +CPF_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPF_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPF_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPF_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPF_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPF_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPF_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPF_LATENCY_STATS_SEL_READ_MAX', + 7: 'CPF_LATENCY_STATS_SEL_READ_MIN', + 8: 'CPF_LATENCY_STATS_SEL_READ_LAST', + 9: 'CPF_LATENCY_STATS_SEL_INVAL_MAX', + 10: 'CPF_LATENCY_STATS_SEL_INVAL_MIN', + 11: 'CPF_LATENCY_STATS_SEL_INVAL_LAST', +} +CPF_LATENCY_STATS_SEL_XACK_MAX = 0 +CPF_LATENCY_STATS_SEL_XACK_MIN = 1 +CPF_LATENCY_STATS_SEL_XACK_LAST = 2 +CPF_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPF_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPF_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPF_LATENCY_STATS_SEL_READ_MAX = 6 +CPF_LATENCY_STATS_SEL_READ_MIN = 7 +CPF_LATENCY_STATS_SEL_READ_LAST = 8 +CPF_LATENCY_STATS_SEL_INVAL_MAX = 9 +CPF_LATENCY_STATS_SEL_INVAL_MIN = 10 +CPF_LATENCY_STATS_SEL_INVAL_LAST = 11 +CPF_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_PERFCOUNTWINDOW_SEL' +CPF_PERFCOUNTWINDOW_SEL__enumvalues = { + 0: 'CPF_PERFWINDOW_SEL_CSF', + 1: 'CPF_PERFWINDOW_SEL_HQD1', + 2: 'CPF_PERFWINDOW_SEL_HQD2', + 3: 'CPF_PERFWINDOW_SEL_RDMA', + 4: 'CPF_PERFWINDOW_SEL_RWPP', +} +CPF_PERFWINDOW_SEL_CSF = 0 +CPF_PERFWINDOW_SEL_HQD1 = 1 +CPF_PERFWINDOW_SEL_HQD2 = 2 +CPF_PERFWINDOW_SEL_RDMA = 3 +CPF_PERFWINDOW_SEL_RWPP = 4 +CPF_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_PERFCOUNT_SEL' +CPF_PERFCOUNT_SEL__enumvalues = { + 0: 'CPF_PERF_SEL_ALWAYS_COUNT', + 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', + 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 15: 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 16: 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', + 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 19: 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', + 20: 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', + 21: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 22: 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 23: 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', + 24: 'CPF_PERF_SEL_CPF_STAT_BUSY', + 25: 'CPF_PERF_SEL_CPF_STAT_IDLE', + 26: 'CPF_PERF_SEL_CPF_STAT_STALL', + 27: 'CPF_PERF_SEL_CPF_TCIU_BUSY', + 28: 'CPF_PERF_SEL_CPF_TCIU_IDLE', + 29: 'CPF_PERF_SEL_CPF_TCIU_STALL', + 30: 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', + 31: 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', + 32: 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', + 33: 'CPF_PERF_SEL_CPF_GCRIU_BUSY', + 34: 'CPF_PERF_SEL_CPF_GCRIU_IDLE', + 35: 'CPF_PERF_SEL_CPF_GCRIU_STALL', + 36: 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 37: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', + 38: 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', + 39: 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', + 40: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', + 41: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', + 42: 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', + 43: 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', +} +CPF_PERF_SEL_ALWAYS_COUNT = 0 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 7 +CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 +CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 +CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 +CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 +CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 +CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 15 +CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 16 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 +CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 19 +CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 20 +CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 21 +CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 22 +CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 23 +CPF_PERF_SEL_CPF_STAT_BUSY = 24 +CPF_PERF_SEL_CPF_STAT_IDLE = 25 +CPF_PERF_SEL_CPF_STAT_STALL = 26 +CPF_PERF_SEL_CPF_TCIU_BUSY = 27 +CPF_PERF_SEL_CPF_TCIU_IDLE = 28 +CPF_PERF_SEL_CPF_TCIU_STALL = 29 +CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 30 +CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 31 +CPF_PERF_SEL_CPF_UTCL2IU_STALL = 32 +CPF_PERF_SEL_CPF_GCRIU_BUSY = 33 +CPF_PERF_SEL_CPF_GCRIU_IDLE = 34 +CPF_PERF_SEL_CPF_GCRIU_STALL = 35 +CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 36 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 37 +CPF_PERF_SEL_CPF_UTCL2IU_XACK = 38 +CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 39 +CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 40 +CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 41 +CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 42 +CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 43 +CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_SCRATCH_REG_ATOMIC_OP' +CPF_SCRATCH_REG_ATOMIC_OP__enumvalues = { + 0: 'CPF_SCRATCH_REG_ATOMIC_ADD', + 1: 'CPF_SCRATCH_REG_ATOMIC_SUB', + 2: 'CPF_SCRATCH_REG_ATOMIC_OR', + 3: 'CPF_SCRATCH_REG_ATOMIC_AND', + 4: 'CPF_SCRATCH_REG_ATOMIC_NOT', + 5: 'CPF_SCRATCH_REG_ATOMIC_MIN', + 6: 'CPF_SCRATCH_REG_ATOMIC_MAX', + 7: 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', +} +CPF_SCRATCH_REG_ATOMIC_ADD = 0 +CPF_SCRATCH_REG_ATOMIC_SUB = 1 +CPF_SCRATCH_REG_ATOMIC_OR = 2 +CPF_SCRATCH_REG_ATOMIC_AND = 3 +CPF_SCRATCH_REG_ATOMIC_NOT = 4 +CPF_SCRATCH_REG_ATOMIC_MIN = 5 +CPF_SCRATCH_REG_ATOMIC_MAX = 6 +CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 7 +CPF_SCRATCH_REG_ATOMIC_OP = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_LATENCY_STATS_SEL' +CPG_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPG_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPG_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPG_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPG_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPG_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPG_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPG_LATENCY_STATS_SEL_WRITE_MAX', + 7: 'CPG_LATENCY_STATS_SEL_WRITE_MIN', + 8: 'CPG_LATENCY_STATS_SEL_WRITE_LAST', + 9: 'CPG_LATENCY_STATS_SEL_READ_MAX', + 10: 'CPG_LATENCY_STATS_SEL_READ_MIN', + 11: 'CPG_LATENCY_STATS_SEL_READ_LAST', + 12: 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', + 13: 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', + 14: 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', + 15: 'CPG_LATENCY_STATS_SEL_INVAL_MAX', + 16: 'CPG_LATENCY_STATS_SEL_INVAL_MIN', + 17: 'CPG_LATENCY_STATS_SEL_INVAL_LAST', +} +CPG_LATENCY_STATS_SEL_XACK_MAX = 0 +CPG_LATENCY_STATS_SEL_XACK_MIN = 1 +CPG_LATENCY_STATS_SEL_XACK_LAST = 2 +CPG_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPG_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPG_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPG_LATENCY_STATS_SEL_WRITE_MAX = 6 +CPG_LATENCY_STATS_SEL_WRITE_MIN = 7 +CPG_LATENCY_STATS_SEL_WRITE_LAST = 8 +CPG_LATENCY_STATS_SEL_READ_MAX = 9 +CPG_LATENCY_STATS_SEL_READ_MIN = 10 +CPG_LATENCY_STATS_SEL_READ_LAST = 11 +CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 12 +CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 13 +CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 14 +CPG_LATENCY_STATS_SEL_INVAL_MAX = 15 +CPG_LATENCY_STATS_SEL_INVAL_MIN = 16 +CPG_LATENCY_STATS_SEL_INVAL_LAST = 17 +CPG_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_PERFCOUNTWINDOW_SEL' +CPG_PERFCOUNTWINDOW_SEL__enumvalues = { + 0: 'CPG_PERFWINDOW_SEL_PFP', + 1: 'CPG_PERFWINDOW_SEL_ME', + 2: 'CPG_PERFWINDOW_SEL_CE', + 3: 'CPG_PERFWINDOW_SEL_MES', + 4: 'CPG_PERFWINDOW_SEL_MEC1', + 5: 'CPG_PERFWINDOW_SEL_MEC2', + 6: 'CPG_PERFWINDOW_SEL_DFY', + 7: 'CPG_PERFWINDOW_SEL_DMA', + 8: 'CPG_PERFWINDOW_SEL_SHADOW', + 9: 'CPG_PERFWINDOW_SEL_RB', + 10: 'CPG_PERFWINDOW_SEL_CEDMA', + 11: 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', + 12: 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', + 13: 'CPG_PERFWINDOW_SEL_PQ1', + 14: 'CPG_PERFWINDOW_SEL_PQ2', + 15: 'CPG_PERFWINDOW_SEL_PQ3', + 16: 'CPG_PERFWINDOW_SEL_MEMWR', + 17: 'CPG_PERFWINDOW_SEL_MEMRD', + 18: 'CPG_PERFWINDOW_SEL_VGT0', + 19: 'CPG_PERFWINDOW_SEL_VGT1', + 20: 'CPG_PERFWINDOW_SEL_APPEND', + 21: 'CPG_PERFWINDOW_SEL_QURD', + 22: 'CPG_PERFWINDOW_SEL_DDID', + 23: 'CPG_PERFWINDOW_SEL_SR', + 24: 'CPG_PERFWINDOW_SEL_QU_EOP', + 25: 'CPG_PERFWINDOW_SEL_QU_STRM', + 26: 'CPG_PERFWINDOW_SEL_QU_PIPE', + 27: 'CPG_PERFWINDOW_SEL_RESERVED1', + 28: 'CPG_PERFWINDOW_SEL_CPC_IC', + 29: 'CPG_PERFWINDOW_SEL_RESERVED2', + 30: 'CPG_PERFWINDOW_SEL_CPG_IC', +} +CPG_PERFWINDOW_SEL_PFP = 0 +CPG_PERFWINDOW_SEL_ME = 1 +CPG_PERFWINDOW_SEL_CE = 2 +CPG_PERFWINDOW_SEL_MES = 3 +CPG_PERFWINDOW_SEL_MEC1 = 4 +CPG_PERFWINDOW_SEL_MEC2 = 5 +CPG_PERFWINDOW_SEL_DFY = 6 +CPG_PERFWINDOW_SEL_DMA = 7 +CPG_PERFWINDOW_SEL_SHADOW = 8 +CPG_PERFWINDOW_SEL_RB = 9 +CPG_PERFWINDOW_SEL_CEDMA = 10 +CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 11 +CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 12 +CPG_PERFWINDOW_SEL_PQ1 = 13 +CPG_PERFWINDOW_SEL_PQ2 = 14 +CPG_PERFWINDOW_SEL_PQ3 = 15 +CPG_PERFWINDOW_SEL_MEMWR = 16 +CPG_PERFWINDOW_SEL_MEMRD = 17 +CPG_PERFWINDOW_SEL_VGT0 = 18 +CPG_PERFWINDOW_SEL_VGT1 = 19 +CPG_PERFWINDOW_SEL_APPEND = 20 +CPG_PERFWINDOW_SEL_QURD = 21 +CPG_PERFWINDOW_SEL_DDID = 22 +CPG_PERFWINDOW_SEL_SR = 23 +CPG_PERFWINDOW_SEL_QU_EOP = 24 +CPG_PERFWINDOW_SEL_QU_STRM = 25 +CPG_PERFWINDOW_SEL_QU_PIPE = 26 +CPG_PERFWINDOW_SEL_RESERVED1 = 27 +CPG_PERFWINDOW_SEL_CPC_IC = 28 +CPG_PERFWINDOW_SEL_RESERVED2 = 29 +CPG_PERFWINDOW_SEL_CPG_IC = 30 +CPG_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_PERFCOUNT_SEL' +CPG_PERFCOUNT_SEL__enumvalues = { + 0: 'CPG_PERF_SEL_ALWAYS_COUNT', + 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', + 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', + 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 34: 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 35: 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', + 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 49: 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 50: 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', + 51: 'CPG_PERF_SEL_CPG_STAT_BUSY', + 52: 'CPG_PERF_SEL_CPG_STAT_IDLE', + 53: 'CPG_PERF_SEL_CPG_STAT_STALL', + 54: 'CPG_PERF_SEL_CPG_TCIU_BUSY', + 55: 'CPG_PERF_SEL_CPG_TCIU_IDLE', + 56: 'CPG_PERF_SEL_CPG_TCIU_STALL', + 57: 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', + 58: 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', + 59: 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', + 60: 'CPG_PERF_SEL_CPG_GCRIU_BUSY', + 61: 'CPG_PERF_SEL_CPG_GCRIU_IDLE', + 62: 'CPG_PERF_SEL_CPG_GCRIU_STALL', + 63: 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 64: 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', + 65: 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', + 66: 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', + 67: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', + 68: 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', + 69: 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', + 70: 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', + 71: 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', + 72: 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', + 73: 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', + 74: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', + 75: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', + 76: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', + 77: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', + 78: 'CPG_PERF_SEL_DMA_BUSY', + 79: 'CPG_PERF_SEL_DMA_STARVED', + 80: 'CPG_PERF_SEL_DMA_STALLED', + 81: 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', + 82: 'CPG_PERF_SEL_PFP_PWS_STALLED0', + 83: 'CPG_PERF_SEL_ME_PWS_STALLED0', + 84: 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS0', + 85: 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS0', + 86: 'CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL0', + 87: 'CPG_PERF_SEL_PFP_PWS_STALLED1', + 88: 'CPG_PERF_SEL_ME_PWS_STALLED1', + 89: 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS1', + 90: 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS1', + 91: 'CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL1', +} +CPG_PERF_SEL_ALWAYS_COUNT = 0 +CPG_PERF_SEL_RBIU_FIFO_FULL = 1 +CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 +CPG_PERF_SEL_ME_PARSER_BUSY = 5 +CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 +CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 +CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 +CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 +CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 +CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 +CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 +CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 +CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 +CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 +CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 +CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 +CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 +CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 +CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 +CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 +CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 +CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 +CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 +CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 +CPG_PERF_SEL_REGISTER_CLK_VALID = 33 +CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 34 +CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 35 +CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 +CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 +CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 +CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 +CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 +CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 +CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 +CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 49 +CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 50 +CPG_PERF_SEL_CPG_STAT_BUSY = 51 +CPG_PERF_SEL_CPG_STAT_IDLE = 52 +CPG_PERF_SEL_CPG_STAT_STALL = 53 +CPG_PERF_SEL_CPG_TCIU_BUSY = 54 +CPG_PERF_SEL_CPG_TCIU_IDLE = 55 +CPG_PERF_SEL_CPG_TCIU_STALL = 56 +CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 57 +CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 58 +CPG_PERF_SEL_CPG_UTCL2IU_STALL = 59 +CPG_PERF_SEL_CPG_GCRIU_BUSY = 60 +CPG_PERF_SEL_CPG_GCRIU_IDLE = 61 +CPG_PERF_SEL_CPG_GCRIU_STALL = 62 +CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 63 +CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 64 +CPG_PERF_SEL_CPG_UTCL2IU_XACK = 65 +CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 66 +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 67 +CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 68 +CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 69 +CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 70 +CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 71 +CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 72 +CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 73 +CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 74 +CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 75 +CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 76 +CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 77 +CPG_PERF_SEL_DMA_BUSY = 78 +CPG_PERF_SEL_DMA_STARVED = 79 +CPG_PERF_SEL_DMA_STALLED = 80 +CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 81 +CPG_PERF_SEL_PFP_PWS_STALLED0 = 82 +CPG_PERF_SEL_ME_PWS_STALLED0 = 83 +CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS0 = 84 +CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS0 = 85 +CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL0 = 86 +CPG_PERF_SEL_PFP_PWS_STALLED1 = 87 +CPG_PERF_SEL_ME_PWS_STALLED1 = 88 +CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS1 = 89 +CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS1 = 90 +CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL1 = 91 +CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ALPHA_TAG_RAM_SEL' +CP_ALPHA_TAG_RAM_SEL__enumvalues = { + 0: 'CPG_TAG_RAM', + 1: 'CPC_TAG_RAM', + 2: 'CPF_TAG_RAM', + 3: 'RSV_TAG_RAM', +} +CPG_TAG_RAM = 0 +CPC_TAG_RAM = 1 +CPF_TAG_RAM = 2 +RSV_TAG_RAM = 3 +CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_MODE' +CP_DDID_CNTL_MODE__enumvalues = { + 0: 'STALL', + 1: 'OVERRUN', +} +STALL = 0 +OVERRUN = 1 +CP_DDID_CNTL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_SIZE' +CP_DDID_CNTL_SIZE__enumvalues = { + 0: 'SIZE_8K', + 1: 'SIZE_16K', +} +SIZE_8K = 0 +SIZE_16K = 1 +CP_DDID_CNTL_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_VMID_SEL' +CP_DDID_CNTL_VMID_SEL__enumvalues = { + 0: 'DDID_VMID_PIPE', + 1: 'DDID_VMID_CNTL', +} +DDID_VMID_PIPE = 0 +DDID_VMID_CNTL = 1 +CP_DDID_CNTL_VMID_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ME_ID' +CP_ME_ID__enumvalues = { + 0: 'ME_ID0', + 1: 'ME_ID1', + 2: 'ME_ID2', + 3: 'ME_ID3', +} +ME_ID0 = 0 +ME_ID1 = 1 +ME_ID2 = 2 +ME_ID3 = 3 +CP_ME_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PIPE_ID' +CP_PIPE_ID__enumvalues = { + 0: 'PIPE_ID0', + 1: 'PIPE_ID1', + 2: 'PIPE_ID2', + 3: 'PIPE_ID3', +} +PIPE_ID0 = 0 +PIPE_ID1 = 1 +PIPE_ID2 = 2 +PIPE_ID3 = 3 +CP_PIPE_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_RING_ID' +CP_RING_ID__enumvalues = { + 0: 'RINGID0', + 1: 'RINGID1', + 2: 'RINGID2', + 3: 'RINGID3', +} +RINGID0 = 0 +RINGID1 = 1 +RINGID2 = 2 +RINGID3 = 3 +CP_RING_ID = ctypes.c_uint32 # enum + +# values for enumeration 'GCRPerfSel' +GCRPerfSel__enumvalues = { + 0: 'GCR_PERF_SEL_NONE', + 1: 'GCR_PERF_SEL_SDMA0_ALL_REQ', + 2: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', + 3: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', + 4: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', + 5: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', + 6: 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', + 7: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', + 8: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', + 9: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', + 10: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', + 11: 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', + 12: 'GCR_PERF_SEL_SDMA0_METADATA_REQ', + 13: 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', + 14: 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', + 15: 'GCR_PERF_SEL_SDMA0_TCP_REQ', + 16: 'GCR_PERF_SEL_SDMA0_GL1_TLB_SHOOTDOWN_REQ', + 17: 'GCR_PERF_SEL_SDMA1_ALL_REQ', + 18: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', + 19: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', + 20: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', + 21: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', + 22: 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', + 23: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', + 24: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', + 25: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', + 26: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', + 27: 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', + 28: 'GCR_PERF_SEL_SDMA1_METADATA_REQ', + 29: 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', + 30: 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', + 31: 'GCR_PERF_SEL_SDMA1_TCP_REQ', + 32: 'GCR_PERF_SEL_SDMA1_GL1_TLB_SHOOTDOWN_REQ', + 33: 'GCR_PERF_SEL_CPC_ALL_REQ', + 34: 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', + 35: 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', + 36: 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', + 37: 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', + 38: 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', + 39: 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', + 40: 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', + 41: 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', + 42: 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', + 43: 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', + 44: 'GCR_PERF_SEL_CPC_METADATA_REQ', + 45: 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', + 46: 'GCR_PERF_SEL_CPC_SQC_INST_REQ', + 47: 'GCR_PERF_SEL_CPC_TCP_REQ', + 48: 'GCR_PERF_SEL_CPC_GL1_TLB_SHOOTDOWN_REQ', + 49: 'GCR_PERF_SEL_CPG_ALL_REQ', + 50: 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', + 51: 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', + 52: 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', + 53: 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', + 54: 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', + 55: 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', + 56: 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', + 57: 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', + 58: 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', + 59: 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', + 60: 'GCR_PERF_SEL_CPG_METADATA_REQ', + 61: 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', + 62: 'GCR_PERF_SEL_CPG_SQC_INST_REQ', + 63: 'GCR_PERF_SEL_CPG_TCP_REQ', + 64: 'GCR_PERF_SEL_CPG_GL1_TLB_SHOOTDOWN_REQ', + 65: 'GCR_PERF_SEL_CPF_ALL_REQ', + 66: 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', + 67: 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', + 68: 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', + 69: 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', + 70: 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', + 71: 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', + 72: 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', + 73: 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', + 74: 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', + 75: 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', + 76: 'GCR_PERF_SEL_CPF_METADATA_REQ', + 77: 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', + 78: 'GCR_PERF_SEL_CPF_SQC_INST_REQ', + 79: 'GCR_PERF_SEL_CPF_TCP_REQ', + 80: 'GCR_PERF_SEL_CPF_GL1_TLB_SHOOTDOWN_REQ', + 81: 'GCR_PERF_SEL_VIRT_REQ', + 82: 'GCR_PERF_SEL_PHY_REQ', + 83: 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', + 84: 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', + 85: 'GCR_PERF_SEL_ALL_REQ', + 86: 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', + 87: 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', + 88: 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', + 89: 'GCR_PERF_SEL_UTCL2_REQ', + 90: 'GCR_PERF_SEL_UTCL2_RET', + 91: 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', + 92: 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', + 93: 'GCR_PERF_SEL_UTCL2_FILTERED_RET', + 94: 'GCR_PERF_SEL_PMM_ABIT_NUM_FLUSH', + 95: 'GCR_PERF_SEL_PMM_ABIT_FLUSH_ONGOING', + 96: 'GCR_PERF_SEL_PMM_NUM_INTERRUPT', + 97: 'GCR_PERF_SEL_PMM_STALL_PMM_IH_CREDITS', + 98: 'GCR_PERF_SEL_PMM_INTERRUPT_READY_TO_SEND', + 99: 'GCR_PERF_SEL_PMM_ABIT_TIMER_FLUSH', + 100: 'GCR_PERF_SEL_PMM_ABIT_FORCE_FLUSH', + 101: 'GCR_PERF_SEL_PMM_ABIT_FLUSH_INTERRUPT', + 102: 'GCR_PERF_SEL_PMM_ALOG_INTERRUPT', + 103: 'GCR_PERF_SEL_PMM_MAM_FLUSH_REQ', + 104: 'GCR_PERF_SEL_PMM_MAM_FLUSH_RESP', + 105: 'GCR_PERF_SEL_PMM_RLC_CGCG_REQ', + 106: 'GCR_PERF_SEL_PMM_RLC_CGCG_RESP', + 107: 'GCR_PERF_SEL_RLC_ALL_REQ', + 108: 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', + 109: 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', + 110: 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', + 111: 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', + 112: 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', + 113: 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', + 114: 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', + 115: 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', + 116: 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', + 117: 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', + 118: 'GCR_PERF_SEL_RLC_METADATA_REQ', + 119: 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', + 120: 'GCR_PERF_SEL_RLC_SQC_INST_REQ', + 121: 'GCR_PERF_SEL_RLC_TCP_REQ', + 122: 'GCR_PERF_SEL_RLC_GL1_TLB_SHOOTDOWN_REQ', + 123: 'GCR_PERF_SEL_PM_ALL_REQ', + 124: 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', + 125: 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', + 126: 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', + 127: 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', + 128: 'GCR_PERF_SEL_PM_GL2_ALL_REQ', + 129: 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', + 130: 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', + 131: 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', + 132: 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', + 133: 'GCR_PERF_SEL_PM_GL1_ALL_REQ', + 134: 'GCR_PERF_SEL_PM_METADATA_REQ', + 135: 'GCR_PERF_SEL_PM_SQC_DATA_REQ', + 136: 'GCR_PERF_SEL_PM_SQC_INST_REQ', + 137: 'GCR_PERF_SEL_PM_TCP_REQ', + 138: 'GCR_PERF_SEL_PM_GL1_TLB_SHOOTDOWN_REQ', + 139: 'GCR_PERF_SEL_PIO_ALL_REQ', + 140: 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', + 141: 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', + 142: 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', + 143: 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', + 144: 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', + 145: 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', + 146: 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', + 147: 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', + 148: 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', + 149: 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', + 150: 'GCR_PERF_SEL_PIO_METADATA_REQ', + 151: 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', + 152: 'GCR_PERF_SEL_PIO_SQC_INST_REQ', + 153: 'GCR_PERF_SEL_PIO_TCP_REQ', + 154: 'GCR_PERF_SEL_PIO_GL1_TLB_SHOOTDOWN_REQ', +} +GCR_PERF_SEL_NONE = 0 +GCR_PERF_SEL_SDMA0_ALL_REQ = 1 +GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 2 +GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 3 +GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 4 +GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 5 +GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 6 +GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 7 +GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 8 +GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 9 +GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 10 +GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 11 +GCR_PERF_SEL_SDMA0_METADATA_REQ = 12 +GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 13 +GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 14 +GCR_PERF_SEL_SDMA0_TCP_REQ = 15 +GCR_PERF_SEL_SDMA0_GL1_TLB_SHOOTDOWN_REQ = 16 +GCR_PERF_SEL_SDMA1_ALL_REQ = 17 +GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 18 +GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 19 +GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 20 +GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 21 +GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 22 +GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 23 +GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 24 +GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 25 +GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 26 +GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 27 +GCR_PERF_SEL_SDMA1_METADATA_REQ = 28 +GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 29 +GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 30 +GCR_PERF_SEL_SDMA1_TCP_REQ = 31 +GCR_PERF_SEL_SDMA1_GL1_TLB_SHOOTDOWN_REQ = 32 +GCR_PERF_SEL_CPC_ALL_REQ = 33 +GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 34 +GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 35 +GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 36 +GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 37 +GCR_PERF_SEL_CPC_GL2_ALL_REQ = 38 +GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 39 +GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 40 +GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 41 +GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 42 +GCR_PERF_SEL_CPC_GL1_ALL_REQ = 43 +GCR_PERF_SEL_CPC_METADATA_REQ = 44 +GCR_PERF_SEL_CPC_SQC_DATA_REQ = 45 +GCR_PERF_SEL_CPC_SQC_INST_REQ = 46 +GCR_PERF_SEL_CPC_TCP_REQ = 47 +GCR_PERF_SEL_CPC_GL1_TLB_SHOOTDOWN_REQ = 48 +GCR_PERF_SEL_CPG_ALL_REQ = 49 +GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 50 +GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 51 +GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 52 +GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 53 +GCR_PERF_SEL_CPG_GL2_ALL_REQ = 54 +GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 55 +GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 56 +GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 57 +GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 58 +GCR_PERF_SEL_CPG_GL1_ALL_REQ = 59 +GCR_PERF_SEL_CPG_METADATA_REQ = 60 +GCR_PERF_SEL_CPG_SQC_DATA_REQ = 61 +GCR_PERF_SEL_CPG_SQC_INST_REQ = 62 +GCR_PERF_SEL_CPG_TCP_REQ = 63 +GCR_PERF_SEL_CPG_GL1_TLB_SHOOTDOWN_REQ = 64 +GCR_PERF_SEL_CPF_ALL_REQ = 65 +GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 66 +GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 67 +GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 68 +GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 69 +GCR_PERF_SEL_CPF_GL2_ALL_REQ = 70 +GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 71 +GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 72 +GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 73 +GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 74 +GCR_PERF_SEL_CPF_GL1_ALL_REQ = 75 +GCR_PERF_SEL_CPF_METADATA_REQ = 76 +GCR_PERF_SEL_CPF_SQC_DATA_REQ = 77 +GCR_PERF_SEL_CPF_SQC_INST_REQ = 78 +GCR_PERF_SEL_CPF_TCP_REQ = 79 +GCR_PERF_SEL_CPF_GL1_TLB_SHOOTDOWN_REQ = 80 +GCR_PERF_SEL_VIRT_REQ = 81 +GCR_PERF_SEL_PHY_REQ = 82 +GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 83 +GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 84 +GCR_PERF_SEL_ALL_REQ = 85 +GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 86 +GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 87 +GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 88 +GCR_PERF_SEL_UTCL2_REQ = 89 +GCR_PERF_SEL_UTCL2_RET = 90 +GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 91 +GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 92 +GCR_PERF_SEL_UTCL2_FILTERED_RET = 93 +GCR_PERF_SEL_PMM_ABIT_NUM_FLUSH = 94 +GCR_PERF_SEL_PMM_ABIT_FLUSH_ONGOING = 95 +GCR_PERF_SEL_PMM_NUM_INTERRUPT = 96 +GCR_PERF_SEL_PMM_STALL_PMM_IH_CREDITS = 97 +GCR_PERF_SEL_PMM_INTERRUPT_READY_TO_SEND = 98 +GCR_PERF_SEL_PMM_ABIT_TIMER_FLUSH = 99 +GCR_PERF_SEL_PMM_ABIT_FORCE_FLUSH = 100 +GCR_PERF_SEL_PMM_ABIT_FLUSH_INTERRUPT = 101 +GCR_PERF_SEL_PMM_ALOG_INTERRUPT = 102 +GCR_PERF_SEL_PMM_MAM_FLUSH_REQ = 103 +GCR_PERF_SEL_PMM_MAM_FLUSH_RESP = 104 +GCR_PERF_SEL_PMM_RLC_CGCG_REQ = 105 +GCR_PERF_SEL_PMM_RLC_CGCG_RESP = 106 +GCR_PERF_SEL_RLC_ALL_REQ = 107 +GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 108 +GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 109 +GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 110 +GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 111 +GCR_PERF_SEL_RLC_GL2_ALL_REQ = 112 +GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 113 +GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 114 +GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 115 +GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 116 +GCR_PERF_SEL_RLC_GL1_ALL_REQ = 117 +GCR_PERF_SEL_RLC_METADATA_REQ = 118 +GCR_PERF_SEL_RLC_SQC_DATA_REQ = 119 +GCR_PERF_SEL_RLC_SQC_INST_REQ = 120 +GCR_PERF_SEL_RLC_TCP_REQ = 121 +GCR_PERF_SEL_RLC_GL1_TLB_SHOOTDOWN_REQ = 122 +GCR_PERF_SEL_PM_ALL_REQ = 123 +GCR_PERF_SEL_PM_GL2_RANGE_REQ = 124 +GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 125 +GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 126 +GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 127 +GCR_PERF_SEL_PM_GL2_ALL_REQ = 128 +GCR_PERF_SEL_PM_GL1_RANGE_REQ = 129 +GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 130 +GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 131 +GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 132 +GCR_PERF_SEL_PM_GL1_ALL_REQ = 133 +GCR_PERF_SEL_PM_METADATA_REQ = 134 +GCR_PERF_SEL_PM_SQC_DATA_REQ = 135 +GCR_PERF_SEL_PM_SQC_INST_REQ = 136 +GCR_PERF_SEL_PM_TCP_REQ = 137 +GCR_PERF_SEL_PM_GL1_TLB_SHOOTDOWN_REQ = 138 +GCR_PERF_SEL_PIO_ALL_REQ = 139 +GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 140 +GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 141 +GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 142 +GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 143 +GCR_PERF_SEL_PIO_GL2_ALL_REQ = 144 +GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 145 +GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 146 +GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 147 +GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 148 +GCR_PERF_SEL_PIO_GL1_ALL_REQ = 149 +GCR_PERF_SEL_PIO_METADATA_REQ = 150 +GCR_PERF_SEL_PIO_SQC_DATA_REQ = 151 +GCR_PERF_SEL_PIO_SQC_INST_REQ = 152 +GCR_PERF_SEL_PIO_TCP_REQ = 153 +GCR_PERF_SEL_PIO_GL1_TLB_SHOOTDOWN_REQ = 154 +GCRPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'GC_EA_CPWD_PERFCOUNT_SEL' +GC_EA_CPWD_PERFCOUNT_SEL__enumvalues = { + 0: 'GC_EA_CPWD_PERF_SEL_ALWAYS_COUNT', + 1: 'GC_EA_CPWD_PERF_SEL_RDRAM_NUM_BANKS_VLD', + 2: 'GC_EA_CPWD_PERF_SEL_RDRAM_REQ_PER_CLIGRP', + 3: 'GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP', + 4: 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START0', + 5: 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END0', + 6: 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START1', + 7: 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END1', + 8: 'GC_EA_CPWD_PERF_SEL_WDRAM_NUM_BANKS_VLD', + 9: 'GC_EA_CPWD_PERF_SEL_WDRAM_REQ_PER_CLIGRP', + 10: 'GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP', + 11: 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START0', + 12: 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END0', + 13: 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START1', + 14: 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END1', + 15: 'GC_EA_CPWD_PERF_SEL_RGMI_NUM_BANKS_VLD', + 16: 'GC_EA_CPWD_PERF_SEL_RGMI_REQ_PER_CLIGRP', + 17: 'GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR', + 18: 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START0', + 19: 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END0', + 20: 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START1', + 21: 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END1', + 22: 'GC_EA_CPWD_PERF_SEL_WGMI_NUM_BANKS_VLD', + 23: 'GC_EA_CPWD_PERF_SEL_WGMI_REQ_PER_CLIGRP', + 24: 'GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP', + 25: 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START0', + 26: 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END0', + 27: 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START1', + 28: 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END1', + 29: 'GC_EA_CPWD_PERF_SEL_RIO_REQ_PER_CLIGRP', + 30: 'GC_EA_CPWD_PERF_SEL_RIO_SIZE_REQ', + 31: 'GC_EA_CPWD_PERF_SEL_RIO_GRP0_SIZE_REQ', + 32: 'GC_EA_CPWD_PERF_SEL_RIO_GRP1_SIZE_REQ', + 33: 'GC_EA_CPWD_PERF_SEL_RIO_GRP2_SIZE_REQ', + 34: 'GC_EA_CPWD_PERF_SEL_RIO_GRP3_SIZE_REQ', + 35: 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START0', + 36: 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END0', + 37: 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START1', + 38: 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END1', + 39: 'GC_EA_CPWD_PERF_SEL_WIO_REQ_PER_CLIGRP', + 40: 'GC_EA_CPWD_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP', + 41: 'GC_EA_CPWD_PERF_SEL_WIO_SIZE_REQ', + 42: 'GC_EA_CPWD_PERF_SEL_WIO_GRP0_SIZE_REQ', + 43: 'GC_EA_CPWD_PERF_SEL_WIO_GRP1_SIZE_REQ', + 44: 'GC_EA_CPWD_PERF_SEL_WIO_GRP2_SIZE_REQ', + 45: 'GC_EA_CPWD_PERF_SEL_WIO_GRP3_SIZE_REQ', + 46: 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START0', + 47: 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END0', + 48: 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START1', + 49: 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END1', + 50: 'GC_EA_CPWD_PERF_SEL_SARB_REQ_PER_VC', + 51: 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_REQ_PER_VC', + 52: 'GC_EA_CPWD_PERF_SEL_SARB_GMI_REQ_PER_VC', + 53: 'GC_EA_CPWD_PERF_SEL_SARB_IO_REQ_PER_VC', + 54: 'GC_EA_CPWD_PERF_SEL_SARB_SIZE_REQ', + 55: 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_SIZE_REQ', + 56: 'GC_EA_CPWD_PERF_SEL_SARB_GMI_SIZE_REQ', + 57: 'GC_EA_CPWD_PERF_SEL_SARB_IO_SIZE_REQ', + 58: 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START0', + 59: 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END0', + 60: 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START1', + 61: 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END1', + 62: 'GC_EA_CPWD_PERF_SEL_SARB_BUSY', + 63: 'GC_EA_CPWD_PERF_SEL_SARB_STALLED', + 64: 'GC_EA_CPWD_PERF_SEL_SARB_STARVING', + 65: 'GC_EA_CPWD_PERF_SEL_SARB_IDLE', + 66: 'GC_EA_CPWD_PERF_SEL_RRET_VLD', + 67: 'GC_EA_CPWD_PERF_SEL_WRET_VLD', + 68: 'GC_EA_CPWD_PERF_SEL_PRB_REQ', + 69: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_EVICT', + 70: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_REQ_VLD', + 71: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT', + 72: 'GC_EA_CPWD_PERF_SEL_MAM_NUM_DQRY', + 73: 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT', + 74: 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED', + 75: 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_COMPLETED', + 76: 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_ONGOING', + 77: 'GC_EA_CPWD_PERF_SEL_RDRAM_SIZE_REQ', + 78: 'GC_EA_CPWD_PERF_SEL_WDRAM_SIZE_REQ', + 79: 'GC_EA_CPWD_PERF_SEL_RGMI_SIZE_REQ', + 80: 'GC_EA_CPWD_PERF_SEL_WGMI_SIZE_REQ', + 81: 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_RW_TURN_AROUND', + 82: 'GC_EA_CPWD_PERF_SEL_SARB_GMI_RW_TURN_AROUND', + 83: 'GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', + 84: 'GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', + 85: 'GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH', + 86: 'GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH', + 87: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_EVICT', + 88: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_REQ_VLD', + 89: 'GC_EA_CPWD_PERF_SEL_SARB_COHERENT_SIZE_REQ', + 90: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT_EVICT', + 91: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_LRU_EVICT', + 92: 'GC_EA_CPWD_PERF_SEL_MAM_FLUSH_REQ', + 93: 'GC_EA_CPWD_PERF_SEL_MAM_FLUSH_RESP', + 94: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT_EVICT', + 95: 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_LRU_EVICT', + 96: 'GC_EA_CPWD_PERF_SEL_MAM_DQRY_ONGOING', + 97: 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT', +} +GC_EA_CPWD_PERF_SEL_ALWAYS_COUNT = 0 +GC_EA_CPWD_PERF_SEL_RDRAM_NUM_BANKS_VLD = 1 +GC_EA_CPWD_PERF_SEL_RDRAM_REQ_PER_CLIGRP = 2 +GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP = 3 +GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START0 = 4 +GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END0 = 5 +GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START1 = 6 +GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END1 = 7 +GC_EA_CPWD_PERF_SEL_WDRAM_NUM_BANKS_VLD = 8 +GC_EA_CPWD_PERF_SEL_WDRAM_REQ_PER_CLIGRP = 9 +GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP = 10 +GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START0 = 11 +GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END0 = 12 +GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START1 = 13 +GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END1 = 14 +GC_EA_CPWD_PERF_SEL_RGMI_NUM_BANKS_VLD = 15 +GC_EA_CPWD_PERF_SEL_RGMI_REQ_PER_CLIGRP = 16 +GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR = 17 +GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START0 = 18 +GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END0 = 19 +GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START1 = 20 +GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END1 = 21 +GC_EA_CPWD_PERF_SEL_WGMI_NUM_BANKS_VLD = 22 +GC_EA_CPWD_PERF_SEL_WGMI_REQ_PER_CLIGRP = 23 +GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP = 24 +GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START0 = 25 +GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END0 = 26 +GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START1 = 27 +GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END1 = 28 +GC_EA_CPWD_PERF_SEL_RIO_REQ_PER_CLIGRP = 29 +GC_EA_CPWD_PERF_SEL_RIO_SIZE_REQ = 30 +GC_EA_CPWD_PERF_SEL_RIO_GRP0_SIZE_REQ = 31 +GC_EA_CPWD_PERF_SEL_RIO_GRP1_SIZE_REQ = 32 +GC_EA_CPWD_PERF_SEL_RIO_GRP2_SIZE_REQ = 33 +GC_EA_CPWD_PERF_SEL_RIO_GRP3_SIZE_REQ = 34 +GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START0 = 35 +GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END0 = 36 +GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START1 = 37 +GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END1 = 38 +GC_EA_CPWD_PERF_SEL_WIO_REQ_PER_CLIGRP = 39 +GC_EA_CPWD_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP = 40 +GC_EA_CPWD_PERF_SEL_WIO_SIZE_REQ = 41 +GC_EA_CPWD_PERF_SEL_WIO_GRP0_SIZE_REQ = 42 +GC_EA_CPWD_PERF_SEL_WIO_GRP1_SIZE_REQ = 43 +GC_EA_CPWD_PERF_SEL_WIO_GRP2_SIZE_REQ = 44 +GC_EA_CPWD_PERF_SEL_WIO_GRP3_SIZE_REQ = 45 +GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START0 = 46 +GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END0 = 47 +GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START1 = 48 +GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END1 = 49 +GC_EA_CPWD_PERF_SEL_SARB_REQ_PER_VC = 50 +GC_EA_CPWD_PERF_SEL_SARB_DRAM_REQ_PER_VC = 51 +GC_EA_CPWD_PERF_SEL_SARB_GMI_REQ_PER_VC = 52 +GC_EA_CPWD_PERF_SEL_SARB_IO_REQ_PER_VC = 53 +GC_EA_CPWD_PERF_SEL_SARB_SIZE_REQ = 54 +GC_EA_CPWD_PERF_SEL_SARB_DRAM_SIZE_REQ = 55 +GC_EA_CPWD_PERF_SEL_SARB_GMI_SIZE_REQ = 56 +GC_EA_CPWD_PERF_SEL_SARB_IO_SIZE_REQ = 57 +GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START0 = 58 +GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END0 = 59 +GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START1 = 60 +GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END1 = 61 +GC_EA_CPWD_PERF_SEL_SARB_BUSY = 62 +GC_EA_CPWD_PERF_SEL_SARB_STALLED = 63 +GC_EA_CPWD_PERF_SEL_SARB_STARVING = 64 +GC_EA_CPWD_PERF_SEL_SARB_IDLE = 65 +GC_EA_CPWD_PERF_SEL_RRET_VLD = 66 +GC_EA_CPWD_PERF_SEL_WRET_VLD = 67 +GC_EA_CPWD_PERF_SEL_PRB_REQ = 68 +GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_EVICT = 69 +GC_EA_CPWD_PERF_SEL_MAM_ARAM_REQ_VLD = 70 +GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT = 71 +GC_EA_CPWD_PERF_SEL_MAM_NUM_DQRY = 72 +GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT = 73 +GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED = 74 +GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_COMPLETED = 75 +GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_ONGOING = 76 +GC_EA_CPWD_PERF_SEL_RDRAM_SIZE_REQ = 77 +GC_EA_CPWD_PERF_SEL_WDRAM_SIZE_REQ = 78 +GC_EA_CPWD_PERF_SEL_RGMI_SIZE_REQ = 79 +GC_EA_CPWD_PERF_SEL_WGMI_SIZE_REQ = 80 +GC_EA_CPWD_PERF_SEL_SARB_DRAM_RW_TURN_AROUND = 81 +GC_EA_CPWD_PERF_SEL_SARB_GMI_RW_TURN_AROUND = 82 +GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 83 +GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 84 +GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 85 +GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 86 +GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_EVICT = 87 +GC_EA_CPWD_PERF_SEL_MAM_DBIT_REQ_VLD = 88 +GC_EA_CPWD_PERF_SEL_SARB_COHERENT_SIZE_REQ = 89 +GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT_EVICT = 90 +GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_LRU_EVICT = 91 +GC_EA_CPWD_PERF_SEL_MAM_FLUSH_REQ = 92 +GC_EA_CPWD_PERF_SEL_MAM_FLUSH_RESP = 93 +GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT_EVICT = 94 +GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_LRU_EVICT = 95 +GC_EA_CPWD_PERF_SEL_MAM_DQRY_ONGOING = 96 +GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT = 97 +GC_EA_CPWD_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GCVML2_SPM_PERF_SEL' +GCVML2_SPM_PERF_SEL__enumvalues = { + 0: 'GCVML2_SPM_PERF_SEL_EVENT_0', + 1: 'GCVML2_SPM_PERF_SEL_EVENT_1', + 2: 'GCVML2_SPM_PERF_SEL_EVENT_2', + 3: 'GCVML2_SPM_PERF_SEL_EVENT_3', + 4: 'GCVML2_SPM_PERF_SEL_EVENT_4', + 5: 'GCVML2_SPM_PERF_SEL_EVENT_5', + 6: 'GCVML2_SPM_PERF_SEL_EVENT_6', + 7: 'GCVML2_SPM_PERF_SEL_EVENT_7', + 8: 'GCVML2_SPM_PERF_SEL_EVENT_8', + 9: 'GCVML2_SPM_PERF_SEL_EVENT_9', + 10: 'GCVML2_SPM_PERF_SEL_EVENT_10', + 11: 'GCVML2_SPM_PERF_SEL_EVENT_11', + 12: 'GCVML2_SPM_PERF_SEL_EVENT_12', + 13: 'GCVML2_SPM_PERF_SEL_EVENT_13', + 14: 'GCVML2_SPM_PERF_SEL_EVENT_14', + 15: 'GCVML2_SPM_PERF_SEL_EVENT_15', + 16: 'GCVML2_SPM_PERF_SEL_EVENT_16', + 17: 'GCVML2_SPM_PERF_SEL_EVENT_17', + 18: 'GCVML2_SPM_PERF_SEL_EVENT_18', + 19: 'GCVML2_SPM_PERF_SEL_EVENT_19', + 20: 'GCVML2_SPM_PERF_SEL_EVENT_20', + 21: 'GCVML2_SPM_PERF_SEL_EVENT_21', + 22: 'GCVML2_SPM_PERF_SEL_EVENT_22', + 23: 'GCVML2_SPM_PERF_SEL_EVENT_23', + 24: 'GCVML2_SPM_PERF_SEL_EVENT_24', + 25: 'GCVML2_SPM_PERF_SEL_EVENT_25', + 26: 'GCVML2_SPM_PERF_SEL_EVENT_26', + 27: 'GCVML2_SPM_PERF_SEL_EVENT_27', + 28: 'GCVML2_SPM_PERF_SEL_EVENT_28', + 29: 'GCVML2_SPM_PERF_SEL_EVENT_29', + 30: 'GCVML2_SPM_PERF_SEL_EVENT_30', + 31: 'GCVML2_SPM_PERF_SEL_EVENT_31', + 32: 'GCVML2_SPM_PERF_SEL_EVENT_32', + 33: 'GCVML2_SPM_PERF_SEL_EVENT_33', + 34: 'GCVML2_SPM_PERF_SEL_EVENT_34', + 35: 'GCVML2_SPM_PERF_SEL_EVENT_35', + 36: 'GCVML2_SPM_PERF_SEL_EVENT_36', + 37: 'GCVML2_SPM_PERF_SEL_EVENT_37', + 38: 'GCVML2_SPM_PERF_SEL_EVENT_38', + 39: 'GCVML2_SPM_PERF_SEL_EVENT_39', + 40: 'GCVML2_SPM_PERF_SEL_EVENT_40', + 41: 'GCVML2_SPM_PERF_SEL_EVENT_41', + 42: 'GCVML2_SPM_PERF_SEL_EVENT_42', + 43: 'GCVML2_SPM_PERF_SEL_EVENT_43', + 44: 'GCVML2_SPM_PERF_SEL_EVENT_44', + 45: 'GCVML2_SPM_PERF_SEL_EVENT_45', + 46: 'GCVML2_SPM_PERF_SEL_EVENT_46', + 47: 'GCVML2_SPM_PERF_SEL_EVENT_47', + 48: 'GCVML2_SPM_PERF_SEL_EVENT_48', + 49: 'GCVML2_SPM_PERF_SEL_EVENT_49', + 50: 'GCVML2_SPM_PERF_SEL_EVENT_50', + 51: 'GCVML2_SPM_PERF_SEL_EVENT_51', + 52: 'GCVML2_SPM_PERF_SEL_EVENT_52', + 53: 'GCVML2_SPM_PERF_SEL_EVENT_53', + 54: 'GCVML2_SPM_PERF_SEL_EVENT_54', + 55: 'GCVML2_SPM_PERF_SEL_EVENT_55', + 56: 'GCVML2_SPM_PERF_SEL_EVENT_56', + 57: 'GCVML2_SPM_PERF_SEL_EVENT_57', + 58: 'GCVML2_SPM_PERF_SEL_EVENT_58', + 59: 'GCVML2_SPM_PERF_SEL_EVENT_59', + 60: 'GCVML2_SPM_PERF_SEL_EVENT_60', + 61: 'GCVML2_SPM_PERF_SEL_EVENT_61', + 62: 'GCVML2_SPM_PERF_SEL_EVENT_62', + 63: 'GCVML2_SPM_PERF_SEL_EVENT_63', + 64: 'GCVML2_SPM_PERF_SEL_EVENT_64', + 65: 'GCVML2_SPM_PERF_SEL_EVENT_65', + 66: 'GCVML2_SPM_PERF_SEL_EVENT_66', + 67: 'GCVML2_SPM_PERF_SEL_EVENT_67', + 68: 'GCVML2_SPM_PERF_SEL_EVENT_68', + 69: 'GCVML2_SPM_PERF_SEL_EVENT_69', + 70: 'GCVML2_SPM_PERF_SEL_EVENT_70', + 71: 'GCVML2_SPM_PERF_SEL_EVENT_71', + 72: 'GCVML2_SPM_PERF_SEL_EVENT_72', + 73: 'GCVML2_SPM_PERF_SEL_EVENT_73', + 74: 'GCVML2_SPM_PERF_SEL_EVENT_74', + 75: 'GCVML2_SPM_PERF_SEL_EVENT_75', + 76: 'GCVML2_SPM_PERF_SEL_EVENT_76', + 77: 'GCVML2_SPM_PERF_SEL_EVENT_77', + 78: 'GCVML2_SPM_PERF_SEL_EVENT_78', + 79: 'GCVML2_SPM_PERF_SEL_EVENT_79', + 80: 'GCVML2_SPM_PERF_SEL_EVENT_80', + 81: 'GCVML2_SPM_PERF_SEL_EVENT_81', + 82: 'GCVML2_SPM_PERF_SEL_EVENT_82', + 83: 'GCVML2_SPM_PERF_SEL_EVENT_83', + 84: 'GCVML2_SPM_PERF_SEL_EVENT_84', + 85: 'GCVML2_SPM_PERF_SEL_EVENT_85', + 86: 'GCVML2_SPM_PERF_SEL_EVENT_86', + 87: 'GCVML2_SPM_PERF_SEL_EVENT_87', + 88: 'GCVML2_SPM_PERF_SEL_EVENT_88', + 89: 'GCVML2_SPM_PERF_SEL_EVENT_89', + 90: 'GCVML2_SPM_PERF_SEL_EVENT_90', +} +GCVML2_SPM_PERF_SEL_EVENT_0 = 0 +GCVML2_SPM_PERF_SEL_EVENT_1 = 1 +GCVML2_SPM_PERF_SEL_EVENT_2 = 2 +GCVML2_SPM_PERF_SEL_EVENT_3 = 3 +GCVML2_SPM_PERF_SEL_EVENT_4 = 4 +GCVML2_SPM_PERF_SEL_EVENT_5 = 5 +GCVML2_SPM_PERF_SEL_EVENT_6 = 6 +GCVML2_SPM_PERF_SEL_EVENT_7 = 7 +GCVML2_SPM_PERF_SEL_EVENT_8 = 8 +GCVML2_SPM_PERF_SEL_EVENT_9 = 9 +GCVML2_SPM_PERF_SEL_EVENT_10 = 10 +GCVML2_SPM_PERF_SEL_EVENT_11 = 11 +GCVML2_SPM_PERF_SEL_EVENT_12 = 12 +GCVML2_SPM_PERF_SEL_EVENT_13 = 13 +GCVML2_SPM_PERF_SEL_EVENT_14 = 14 +GCVML2_SPM_PERF_SEL_EVENT_15 = 15 +GCVML2_SPM_PERF_SEL_EVENT_16 = 16 +GCVML2_SPM_PERF_SEL_EVENT_17 = 17 +GCVML2_SPM_PERF_SEL_EVENT_18 = 18 +GCVML2_SPM_PERF_SEL_EVENT_19 = 19 +GCVML2_SPM_PERF_SEL_EVENT_20 = 20 +GCVML2_SPM_PERF_SEL_EVENT_21 = 21 +GCVML2_SPM_PERF_SEL_EVENT_22 = 22 +GCVML2_SPM_PERF_SEL_EVENT_23 = 23 +GCVML2_SPM_PERF_SEL_EVENT_24 = 24 +GCVML2_SPM_PERF_SEL_EVENT_25 = 25 +GCVML2_SPM_PERF_SEL_EVENT_26 = 26 +GCVML2_SPM_PERF_SEL_EVENT_27 = 27 +GCVML2_SPM_PERF_SEL_EVENT_28 = 28 +GCVML2_SPM_PERF_SEL_EVENT_29 = 29 +GCVML2_SPM_PERF_SEL_EVENT_30 = 30 +GCVML2_SPM_PERF_SEL_EVENT_31 = 31 +GCVML2_SPM_PERF_SEL_EVENT_32 = 32 +GCVML2_SPM_PERF_SEL_EVENT_33 = 33 +GCVML2_SPM_PERF_SEL_EVENT_34 = 34 +GCVML2_SPM_PERF_SEL_EVENT_35 = 35 +GCVML2_SPM_PERF_SEL_EVENT_36 = 36 +GCVML2_SPM_PERF_SEL_EVENT_37 = 37 +GCVML2_SPM_PERF_SEL_EVENT_38 = 38 +GCVML2_SPM_PERF_SEL_EVENT_39 = 39 +GCVML2_SPM_PERF_SEL_EVENT_40 = 40 +GCVML2_SPM_PERF_SEL_EVENT_41 = 41 +GCVML2_SPM_PERF_SEL_EVENT_42 = 42 +GCVML2_SPM_PERF_SEL_EVENT_43 = 43 +GCVML2_SPM_PERF_SEL_EVENT_44 = 44 +GCVML2_SPM_PERF_SEL_EVENT_45 = 45 +GCVML2_SPM_PERF_SEL_EVENT_46 = 46 +GCVML2_SPM_PERF_SEL_EVENT_47 = 47 +GCVML2_SPM_PERF_SEL_EVENT_48 = 48 +GCVML2_SPM_PERF_SEL_EVENT_49 = 49 +GCVML2_SPM_PERF_SEL_EVENT_50 = 50 +GCVML2_SPM_PERF_SEL_EVENT_51 = 51 +GCVML2_SPM_PERF_SEL_EVENT_52 = 52 +GCVML2_SPM_PERF_SEL_EVENT_53 = 53 +GCVML2_SPM_PERF_SEL_EVENT_54 = 54 +GCVML2_SPM_PERF_SEL_EVENT_55 = 55 +GCVML2_SPM_PERF_SEL_EVENT_56 = 56 +GCVML2_SPM_PERF_SEL_EVENT_57 = 57 +GCVML2_SPM_PERF_SEL_EVENT_58 = 58 +GCVML2_SPM_PERF_SEL_EVENT_59 = 59 +GCVML2_SPM_PERF_SEL_EVENT_60 = 60 +GCVML2_SPM_PERF_SEL_EVENT_61 = 61 +GCVML2_SPM_PERF_SEL_EVENT_62 = 62 +GCVML2_SPM_PERF_SEL_EVENT_63 = 63 +GCVML2_SPM_PERF_SEL_EVENT_64 = 64 +GCVML2_SPM_PERF_SEL_EVENT_65 = 65 +GCVML2_SPM_PERF_SEL_EVENT_66 = 66 +GCVML2_SPM_PERF_SEL_EVENT_67 = 67 +GCVML2_SPM_PERF_SEL_EVENT_68 = 68 +GCVML2_SPM_PERF_SEL_EVENT_69 = 69 +GCVML2_SPM_PERF_SEL_EVENT_70 = 70 +GCVML2_SPM_PERF_SEL_EVENT_71 = 71 +GCVML2_SPM_PERF_SEL_EVENT_72 = 72 +GCVML2_SPM_PERF_SEL_EVENT_73 = 73 +GCVML2_SPM_PERF_SEL_EVENT_74 = 74 +GCVML2_SPM_PERF_SEL_EVENT_75 = 75 +GCVML2_SPM_PERF_SEL_EVENT_76 = 76 +GCVML2_SPM_PERF_SEL_EVENT_77 = 77 +GCVML2_SPM_PERF_SEL_EVENT_78 = 78 +GCVML2_SPM_PERF_SEL_EVENT_79 = 79 +GCVML2_SPM_PERF_SEL_EVENT_80 = 80 +GCVML2_SPM_PERF_SEL_EVENT_81 = 81 +GCVML2_SPM_PERF_SEL_EVENT_82 = 82 +GCVML2_SPM_PERF_SEL_EVENT_83 = 83 +GCVML2_SPM_PERF_SEL_EVENT_84 = 84 +GCVML2_SPM_PERF_SEL_EVENT_85 = 85 +GCVML2_SPM_PERF_SEL_EVENT_86 = 86 +GCVML2_SPM_PERF_SEL_EVENT_87 = 87 +GCVML2_SPM_PERF_SEL_EVENT_88 = 88 +GCVML2_SPM_PERF_SEL_EVENT_89 = 89 +GCVML2_SPM_PERF_SEL_EVENT_90 = 90 +GCVML2_SPM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GCUTCL2_PERF_SEL' +GCUTCL2_PERF_SEL__enumvalues = { + 0: 'GCUTCL2_PERF_SEL_EVENT_0', + 1: 'GCUTCL2_PERF_SEL_EVENT_1', + 2: 'GCUTCL2_PERF_SEL_EVENT_2', + 3: 'GCUTCL2_PERF_SEL_EVENT_3', + 4: 'GCUTCL2_PERF_SEL_EVENT_4', + 5: 'GCUTCL2_PERF_SEL_EVENT_5', + 6: 'GCUTCL2_PERF_SEL_EVENT_6', + 7: 'GCUTCL2_PERF_SEL_EVENT_7', + 8: 'GCUTCL2_PERF_SEL_EVENT_8', + 9: 'GCUTCL2_PERF_SEL_EVENT_9', + 10: 'GCUTCL2_PERF_SEL_EVENT_10', + 11: 'GCUTCL2_PERF_SEL_EVENT_11', + 12: 'GCUTCL2_PERF_SEL_EVENT_12', + 13: 'GCUTCL2_PERF_SEL_EVENT_13', + 14: 'GCUTCL2_PERF_SEL_EVENT_14', + 15: 'GCUTCL2_PERF_SEL_EVENT_15', + 16: 'GCUTCL2_PERF_SEL_EVENT_16', + 17: 'GCUTCL2_PERF_SEL_EVENT_17', + 18: 'GCUTCL2_PERF_SEL_EVENT_18', + 19: 'GCUTCL2_PERF_SEL_EVENT_19', + 20: 'GCUTCL2_PERF_SEL_EVENT_20', + 21: 'GCUTCL2_PERF_SEL_EVENT_21', + 22: 'GCUTCL2_PERF_SEL_EVENT_22', + 23: 'GCUTCL2_PERF_SEL_EVENT_23', + 24: 'GCUTCL2_PERF_SEL_EVENT_24', + 25: 'GCUTCL2_PERF_SEL_EVENT_25', + 26: 'GCUTCL2_PERF_SEL_EVENT_26', + 27: 'GCUTCL2_PERF_SEL_EVENT_27', + 28: 'GCUTCL2_PERF_SEL_EVENT_28', + 29: 'GCUTCL2_PERF_SEL_EVENT_29', + 30: 'GCUTCL2_PERF_SEL_EVENT_30', + 31: 'GCUTCL2_PERF_SEL_EVENT_31', + 32: 'GCUTCL2_PERF_SEL_EVENT_32', + 33: 'GCUTCL2_PERF_SEL_EVENT_33', + 34: 'GCUTCL2_PERF_SEL_EVENT_34', + 35: 'GCUTCL2_PERF_SEL_EVENT_35', + 36: 'GCUTCL2_PERF_SEL_EVENT_36', +} +GCUTCL2_PERF_SEL_EVENT_0 = 0 +GCUTCL2_PERF_SEL_EVENT_1 = 1 +GCUTCL2_PERF_SEL_EVENT_2 = 2 +GCUTCL2_PERF_SEL_EVENT_3 = 3 +GCUTCL2_PERF_SEL_EVENT_4 = 4 +GCUTCL2_PERF_SEL_EVENT_5 = 5 +GCUTCL2_PERF_SEL_EVENT_6 = 6 +GCUTCL2_PERF_SEL_EVENT_7 = 7 +GCUTCL2_PERF_SEL_EVENT_8 = 8 +GCUTCL2_PERF_SEL_EVENT_9 = 9 +GCUTCL2_PERF_SEL_EVENT_10 = 10 +GCUTCL2_PERF_SEL_EVENT_11 = 11 +GCUTCL2_PERF_SEL_EVENT_12 = 12 +GCUTCL2_PERF_SEL_EVENT_13 = 13 +GCUTCL2_PERF_SEL_EVENT_14 = 14 +GCUTCL2_PERF_SEL_EVENT_15 = 15 +GCUTCL2_PERF_SEL_EVENT_16 = 16 +GCUTCL2_PERF_SEL_EVENT_17 = 17 +GCUTCL2_PERF_SEL_EVENT_18 = 18 +GCUTCL2_PERF_SEL_EVENT_19 = 19 +GCUTCL2_PERF_SEL_EVENT_20 = 20 +GCUTCL2_PERF_SEL_EVENT_21 = 21 +GCUTCL2_PERF_SEL_EVENT_22 = 22 +GCUTCL2_PERF_SEL_EVENT_23 = 23 +GCUTCL2_PERF_SEL_EVENT_24 = 24 +GCUTCL2_PERF_SEL_EVENT_25 = 25 +GCUTCL2_PERF_SEL_EVENT_26 = 26 +GCUTCL2_PERF_SEL_EVENT_27 = 27 +GCUTCL2_PERF_SEL_EVENT_28 = 28 +GCUTCL2_PERF_SEL_EVENT_29 = 29 +GCUTCL2_PERF_SEL_EVENT_30 = 30 +GCUTCL2_PERF_SEL_EVENT_31 = 31 +GCUTCL2_PERF_SEL_EVENT_32 = 32 +GCUTCL2_PERF_SEL_EVENT_33 = 33 +GCUTCL2_PERF_SEL_EVENT_34 = 34 +GCUTCL2_PERF_SEL_EVENT_35 = 35 +GCUTCL2_PERF_SEL_EVENT_36 = 36 +GCUTCL2_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GCVML2_PERF_SEL' +GCVML2_PERF_SEL__enumvalues = { + 0: 'GCVML2_PERF_SEL_EVENT_0', + 1: 'GCVML2_PERF_SEL_EVENT_1', + 2: 'GCVML2_PERF_SEL_EVENT_2', + 3: 'GCVML2_PERF_SEL_EVENT_3', + 4: 'GCVML2_PERF_SEL_EVENT_4', + 5: 'GCVML2_PERF_SEL_EVENT_5', + 6: 'GCVML2_PERF_SEL_EVENT_6', + 7: 'GCVML2_PERF_SEL_EVENT_7', + 8: 'GCVML2_PERF_SEL_EVENT_8', + 9: 'GCVML2_PERF_SEL_EVENT_9', + 10: 'GCVML2_PERF_SEL_EVENT_10', + 11: 'GCVML2_PERF_SEL_EVENT_11', + 12: 'GCVML2_PERF_SEL_EVENT_12', + 13: 'GCVML2_PERF_SEL_EVENT_13', + 14: 'GCVML2_PERF_SEL_EVENT_14', + 15: 'GCVML2_PERF_SEL_EVENT_15', + 16: 'GCVML2_PERF_SEL_EVENT_16', + 17: 'GCVML2_PERF_SEL_EVENT_17', + 18: 'GCVML2_PERF_SEL_EVENT_18', + 19: 'GCVML2_PERF_SEL_EVENT_19', + 20: 'GCVML2_PERF_SEL_EVENT_20', + 21: 'GCVML2_PERF_SEL_EVENT_21', + 22: 'GCVML2_PERF_SEL_EVENT_22', + 23: 'GCVML2_PERF_SEL_EVENT_23', + 24: 'GCVML2_PERF_SEL_EVENT_24', + 25: 'GCVML2_PERF_SEL_EVENT_25', + 26: 'GCVML2_PERF_SEL_EVENT_26', + 27: 'GCVML2_PERF_SEL_EVENT_27', + 28: 'GCVML2_PERF_SEL_EVENT_28', + 29: 'GCVML2_PERF_SEL_EVENT_29', + 30: 'GCVML2_PERF_SEL_EVENT_30', + 31: 'GCVML2_PERF_SEL_EVENT_31', + 32: 'GCVML2_PERF_SEL_EVENT_32', + 33: 'GCVML2_PERF_SEL_EVENT_33', + 34: 'GCVML2_PERF_SEL_EVENT_34', + 35: 'GCVML2_PERF_SEL_EVENT_35', + 36: 'GCVML2_PERF_SEL_EVENT_36', + 37: 'GCVML2_PERF_SEL_EVENT_37', + 38: 'GCVML2_PERF_SEL_EVENT_38', + 39: 'GCVML2_PERF_SEL_EVENT_39', + 40: 'GCVML2_PERF_SEL_EVENT_40', + 41: 'GCVML2_PERF_SEL_EVENT_41', + 42: 'GCVML2_PERF_SEL_EVENT_42', + 43: 'GCVML2_PERF_SEL_EVENT_43', + 44: 'GCVML2_PERF_SEL_EVENT_44', + 45: 'GCVML2_PERF_SEL_EVENT_45', + 46: 'GCVML2_PERF_SEL_EVENT_46', + 47: 'GCVML2_PERF_SEL_EVENT_47', + 48: 'GCVML2_PERF_SEL_EVENT_48', + 49: 'GCVML2_PERF_SEL_EVENT_49', + 50: 'GCVML2_PERF_SEL_EVENT_50', + 51: 'GCVML2_PERF_SEL_EVENT_51', + 52: 'GCVML2_PERF_SEL_EVENT_52', + 53: 'GCVML2_PERF_SEL_EVENT_53', + 54: 'GCVML2_PERF_SEL_EVENT_54', + 55: 'GCVML2_PERF_SEL_EVENT_55', + 56: 'GCVML2_PERF_SEL_EVENT_56', + 57: 'GCVML2_PERF_SEL_EVENT_57', + 58: 'GCVML2_PERF_SEL_EVENT_58', + 59: 'GCVML2_PERF_SEL_EVENT_59', + 60: 'GCVML2_PERF_SEL_EVENT_60', + 61: 'GCVML2_PERF_SEL_EVENT_61', + 62: 'GCVML2_PERF_SEL_EVENT_62', + 63: 'GCVML2_PERF_SEL_EVENT_63', + 64: 'GCVML2_PERF_SEL_EVENT_64', + 65: 'GCVML2_PERF_SEL_EVENT_65', + 66: 'GCVML2_PERF_SEL_EVENT_66', + 67: 'GCVML2_PERF_SEL_EVENT_67', + 68: 'GCVML2_PERF_SEL_EVENT_68', + 69: 'GCVML2_PERF_SEL_EVENT_69', + 70: 'GCVML2_PERF_SEL_EVENT_70', + 71: 'GCVML2_PERF_SEL_EVENT_71', + 72: 'GCVML2_PERF_SEL_EVENT_72', + 73: 'GCVML2_PERF_SEL_EVENT_73', + 74: 'GCVML2_PERF_SEL_EVENT_74', + 75: 'GCVML2_PERF_SEL_EVENT_75', + 76: 'GCVML2_PERF_SEL_EVENT_76', + 77: 'GCVML2_PERF_SEL_EVENT_77', + 78: 'GCVML2_PERF_SEL_EVENT_78', + 79: 'GCVML2_PERF_SEL_EVENT_79', + 80: 'GCVML2_PERF_SEL_EVENT_80', + 81: 'GCVML2_PERF_SEL_EVENT_81', + 82: 'GCVML2_PERF_SEL_EVENT_82', + 83: 'GCVML2_PERF_SEL_EVENT_83', + 84: 'GCVML2_PERF_SEL_EVENT_84', + 85: 'GCVML2_PERF_SEL_EVENT_85', + 86: 'GCVML2_PERF_SEL_EVENT_86', + 87: 'GCVML2_PERF_SEL_EVENT_87', + 88: 'GCVML2_PERF_SEL_EVENT_88', + 89: 'GCVML2_PERF_SEL_EVENT_89', + 90: 'GCVML2_PERF_SEL_EVENT_90', +} +GCVML2_PERF_SEL_EVENT_0 = 0 +GCVML2_PERF_SEL_EVENT_1 = 1 +GCVML2_PERF_SEL_EVENT_2 = 2 +GCVML2_PERF_SEL_EVENT_3 = 3 +GCVML2_PERF_SEL_EVENT_4 = 4 +GCVML2_PERF_SEL_EVENT_5 = 5 +GCVML2_PERF_SEL_EVENT_6 = 6 +GCVML2_PERF_SEL_EVENT_7 = 7 +GCVML2_PERF_SEL_EVENT_8 = 8 +GCVML2_PERF_SEL_EVENT_9 = 9 +GCVML2_PERF_SEL_EVENT_10 = 10 +GCVML2_PERF_SEL_EVENT_11 = 11 +GCVML2_PERF_SEL_EVENT_12 = 12 +GCVML2_PERF_SEL_EVENT_13 = 13 +GCVML2_PERF_SEL_EVENT_14 = 14 +GCVML2_PERF_SEL_EVENT_15 = 15 +GCVML2_PERF_SEL_EVENT_16 = 16 +GCVML2_PERF_SEL_EVENT_17 = 17 +GCVML2_PERF_SEL_EVENT_18 = 18 +GCVML2_PERF_SEL_EVENT_19 = 19 +GCVML2_PERF_SEL_EVENT_20 = 20 +GCVML2_PERF_SEL_EVENT_21 = 21 +GCVML2_PERF_SEL_EVENT_22 = 22 +GCVML2_PERF_SEL_EVENT_23 = 23 +GCVML2_PERF_SEL_EVENT_24 = 24 +GCVML2_PERF_SEL_EVENT_25 = 25 +GCVML2_PERF_SEL_EVENT_26 = 26 +GCVML2_PERF_SEL_EVENT_27 = 27 +GCVML2_PERF_SEL_EVENT_28 = 28 +GCVML2_PERF_SEL_EVENT_29 = 29 +GCVML2_PERF_SEL_EVENT_30 = 30 +GCVML2_PERF_SEL_EVENT_31 = 31 +GCVML2_PERF_SEL_EVENT_32 = 32 +GCVML2_PERF_SEL_EVENT_33 = 33 +GCVML2_PERF_SEL_EVENT_34 = 34 +GCVML2_PERF_SEL_EVENT_35 = 35 +GCVML2_PERF_SEL_EVENT_36 = 36 +GCVML2_PERF_SEL_EVENT_37 = 37 +GCVML2_PERF_SEL_EVENT_38 = 38 +GCVML2_PERF_SEL_EVENT_39 = 39 +GCVML2_PERF_SEL_EVENT_40 = 40 +GCVML2_PERF_SEL_EVENT_41 = 41 +GCVML2_PERF_SEL_EVENT_42 = 42 +GCVML2_PERF_SEL_EVENT_43 = 43 +GCVML2_PERF_SEL_EVENT_44 = 44 +GCVML2_PERF_SEL_EVENT_45 = 45 +GCVML2_PERF_SEL_EVENT_46 = 46 +GCVML2_PERF_SEL_EVENT_47 = 47 +GCVML2_PERF_SEL_EVENT_48 = 48 +GCVML2_PERF_SEL_EVENT_49 = 49 +GCVML2_PERF_SEL_EVENT_50 = 50 +GCVML2_PERF_SEL_EVENT_51 = 51 +GCVML2_PERF_SEL_EVENT_52 = 52 +GCVML2_PERF_SEL_EVENT_53 = 53 +GCVML2_PERF_SEL_EVENT_54 = 54 +GCVML2_PERF_SEL_EVENT_55 = 55 +GCVML2_PERF_SEL_EVENT_56 = 56 +GCVML2_PERF_SEL_EVENT_57 = 57 +GCVML2_PERF_SEL_EVENT_58 = 58 +GCVML2_PERF_SEL_EVENT_59 = 59 +GCVML2_PERF_SEL_EVENT_60 = 60 +GCVML2_PERF_SEL_EVENT_61 = 61 +GCVML2_PERF_SEL_EVENT_62 = 62 +GCVML2_PERF_SEL_EVENT_63 = 63 +GCVML2_PERF_SEL_EVENT_64 = 64 +GCVML2_PERF_SEL_EVENT_65 = 65 +GCVML2_PERF_SEL_EVENT_66 = 66 +GCVML2_PERF_SEL_EVENT_67 = 67 +GCVML2_PERF_SEL_EVENT_68 = 68 +GCVML2_PERF_SEL_EVENT_69 = 69 +GCVML2_PERF_SEL_EVENT_70 = 70 +GCVML2_PERF_SEL_EVENT_71 = 71 +GCVML2_PERF_SEL_EVENT_72 = 72 +GCVML2_PERF_SEL_EVENT_73 = 73 +GCVML2_PERF_SEL_EVENT_74 = 74 +GCVML2_PERF_SEL_EVENT_75 = 75 +GCVML2_PERF_SEL_EVENT_76 = 76 +GCVML2_PERF_SEL_EVENT_77 = 77 +GCVML2_PERF_SEL_EVENT_78 = 78 +GCVML2_PERF_SEL_EVENT_79 = 79 +GCVML2_PERF_SEL_EVENT_80 = 80 +GCVML2_PERF_SEL_EVENT_81 = 81 +GCVML2_PERF_SEL_EVENT_82 = 82 +GCVML2_PERF_SEL_EVENT_83 = 83 +GCVML2_PERF_SEL_EVENT_84 = 84 +GCVML2_PERF_SEL_EVENT_85 = 85 +GCVML2_PERF_SEL_EVENT_86 = 86 +GCVML2_PERF_SEL_EVENT_87 = 87 +GCVML2_PERF_SEL_EVENT_88 = 88 +GCVML2_PERF_SEL_EVENT_89 = 89 +GCVML2_PERF_SEL_EVENT_90 = 90 +GCVML2_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'BlendOp' +BlendOp__enumvalues = { + 0: 'BLEND_ZERO', + 1: 'BLEND_ONE', + 2: 'BLEND_SRC_COLOR', + 3: 'BLEND_ONE_MINUS_SRC_COLOR', + 4: 'BLEND_SRC_ALPHA', + 5: 'BLEND_ONE_MINUS_SRC_ALPHA', + 6: 'BLEND_DST_ALPHA', + 7: 'BLEND_ONE_MINUS_DST_ALPHA', + 8: 'BLEND_DST_COLOR', + 9: 'BLEND_ONE_MINUS_DST_COLOR', + 10: 'BLEND_SRC_ALPHA_SATURATE', + 11: 'BLEND_CONSTANT_COLOR', + 12: 'BLEND_ONE_MINUS_CONSTANT_COLOR', + 13: 'BLEND_SRC1_COLOR', + 14: 'BLEND_INV_SRC1_COLOR', + 15: 'BLEND_SRC1_ALPHA', + 16: 'BLEND_INV_SRC1_ALPHA', + 17: 'BLEND_CONSTANT_ALPHA', + 18: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', +} +BLEND_ZERO = 0 +BLEND_ONE = 1 +BLEND_SRC_COLOR = 2 +BLEND_ONE_MINUS_SRC_COLOR = 3 +BLEND_SRC_ALPHA = 4 +BLEND_ONE_MINUS_SRC_ALPHA = 5 +BLEND_DST_ALPHA = 6 +BLEND_ONE_MINUS_DST_ALPHA = 7 +BLEND_DST_COLOR = 8 +BLEND_ONE_MINUS_DST_COLOR = 9 +BLEND_SRC_ALPHA_SATURATE = 10 +BLEND_CONSTANT_COLOR = 11 +BLEND_ONE_MINUS_CONSTANT_COLOR = 12 +BLEND_SRC1_COLOR = 13 +BLEND_INV_SRC1_COLOR = 14 +BLEND_SRC1_ALPHA = 15 +BLEND_INV_SRC1_ALPHA = 16 +BLEND_CONSTANT_ALPHA = 17 +BLEND_ONE_MINUS_CONSTANT_ALPHA = 18 +BlendOp = ctypes.c_uint32 # enum +GL__ZERO = BLEND_ZERO # macro +GL__ONE = BLEND_ONE # macro +GL__SRC_COLOR = BLEND_SRC_COLOR # macro +GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro +GL__DST_COLOR = BLEND_DST_COLOR # macro +GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro +GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro +GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro +GL__DST_ALPHA = BLEND_DST_ALPHA # macro +GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro +GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro +GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro +GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro +GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro +GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro + +# values for enumeration 'BlendOpt' +BlendOpt__enumvalues = { + 0: 'FORCE_OPT_AUTO', + 1: 'FORCE_OPT_DISABLE', + 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', + 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', + 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', +} +FORCE_OPT_AUTO = 0 +FORCE_OPT_DISABLE = 1 +FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 +FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 +FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 +FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 +FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 +FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 +BlendOpt = ctypes.c_uint32 # enum + +# values for enumeration 'CBMode' +CBMode__enumvalues = { + 0: 'CB_DISABLE', + 1: 'CB_NORMAL', + 2: 'CB_ELIMINATE_FAST_CLEAR', + 3: 'CB_DCC_DECOMPRESS', + 4: 'CB_RESERVED', +} +CB_DISABLE = 0 +CB_NORMAL = 1 +CB_ELIMINATE_FAST_CLEAR = 2 +CB_DCC_DECOMPRESS = 3 +CB_RESERVED = 4 +CBMode = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfClearFilterSel' +CBPerfClearFilterSel__enumvalues = { + 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', +} +CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 +CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 +CBPerfClearFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfOpFilterSel' +CBPerfOpFilterSel__enumvalues = { + 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', +} +CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 +CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 +CB_PERF_OP_FILTER_SEL_RESOLVE = 2 +CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 +CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 +CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 +CBPerfOpFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfSel' +CBPerfSel__enumvalues = { + 1: 'CB_PERF_SEL_BUSY', + 2: 'CB_PERF_SEL_DRAWN_BUSY', + 3: 'CB_PERF_SEL_DRAWN_PIXEL', + 4: 'CB_PERF_SEL_DRAWN_QUAD', + 5: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', + 15: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', + 16: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', + 17: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', + 18: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', + 21: 'CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST', + 22: 'CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST_IN_FLIGHT', + 23: 'CB_PERF_SEL_CC_CRW_GLX_REQ_WRITE_REQUEST', + 24: 'CB_PERF_SEL_CC_CRW_GLX_SRC_WRITE_CYCLES', + 25: 'CB_PERF_SEL_CC_FDCC_COMPRESS_FRAG_TIDS_IN', + 26: 'CB_PERF_SEL_CC_FDCC_DECOMPRESS_FRAG_TIDS_OUT', + 50: 'CB_PERF_SEL_EVENT', + 51: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 52: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 53: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 54: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 55: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 56: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 57: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 58: 'CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS', + 60: 'CB_PERF_SEL_STATIC_CLOCK_EN', + 61: 'CB_PERF_SEL_PERFMON_CLOCK_EN', + 62: 'CB_PERF_SEL_BLEND_CLOCK_EN', + 63: 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', + 64: 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', + 65: 'CB_PERF_SEL_GRBM_CLOCK_EN', + 66: 'CB_PERF_SEL_MEMARB_CLOCK_EN', + 67: 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', + 68: 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', + 69: 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', + 70: 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', + 71: 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', + 72: 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', + 73: 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', + 74: 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', + 75: 'CB_PERF_SEL_EVENTS_CLK_EN', + 80: 'CB_PERF_SEL_CC_TAG_HIT', + 81: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 82: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', + 83: 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', + 88: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 89: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 90: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 91: 'CB_PERF_SEL_CC_CACHE_STALL', + 92: 'CB_PERF_SEL_CC_CACHE_FLUSH', + 93: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 94: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 95: 'CB_PERF_SEL_CC_CACHE_QBLOCKS_FLUSHED', + 96: 'CB_PERF_SEL_CC_CACHE_DIRTY_QBLOCKS_FLUSHED', + 97: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 98: 'CB_PERF_SEL_CCC_IN_EVICT_HAZARD_STALL', + 99: 'CB_PERF_SEL_CCC_COLOR_RESOURCE_PANIC', + 100: 'CB_PERF_SEL_CCC_FMASK_RESOURCE_PANIC', + 101: 'CB_PERF_SEL_CCC_FREE_WAYS_PANIC', + 102: 'CB_PERF_SEL_CCC_SKID_FIFO_FULL', + 103: 'CB_PERF_SEL_CCC_SKID_FIFO_STALL', + 104: 'CB_PERF_SEL_CCC_COLOR_RESOURCE_STALL', + 105: 'CB_PERF_SEL_CCC_FMASK_RESOURCE_STALL', + 106: 'CB_PERF_SEL_CCC_FREE_WAYS_STALL', + 110: 'CB_PERF_SEL_BE_SRCFIFO_FULL', + 111: 'CB_PERF_SEL_BE_RDLATFIFO_FULL', + 112: 'CB_PERF_SEL_RDLAT_FIFO_QUAD_RESIDENCY_STALL', + 113: 'CB_PERF_SEL_CC_QUADFRAG_VALID_READY', + 114: 'CB_PERF_SEL_CC_QUADFRAG_VALID_READYB', + 115: 'CB_PERF_SEL_CC_QUADFRAG_VALIDB_READY', + 116: 'CB_PERF_SEL_CC_QUADFRAG_VALIDB_READYB', + 118: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READY', + 119: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READYB', + 120: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READY', + 121: 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READYB', + 150: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', + 151: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', + 152: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', + 180: 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 181: 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 182: 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', + 183: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', + 184: 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', + 185: 'CB_PERF_SEL_BLEND_STALL_ON_CACHE_ACCESS', + 186: 'CB_PERF_SEL_BLEND_COLLISION_DUE_TO_CACHE_WRITE', + 187: 'CB_PERF_SEL_BLEND_RAW_HAZARD_STALL', + 190: 'CB_PERF_SEL_BE_CS_FILLRATE_1X2', + 191: 'CB_PERF_SEL_BE_CS_FILLRATE_2X1', + 192: 'CB_PERF_SEL_BE_CS_FILLRATE_2X2', + 250: 'CB_PERF_SEL_FORMAT_IS_32_R', + 251: 'CB_PERF_SEL_FORMAT_IS_32_AR', + 252: 'CB_PERF_SEL_FORMAT_IS_32_GR', + 253: 'CB_PERF_SEL_FORMAT_IS_32_ABGR', + 254: 'CB_PERF_SEL_FORMAT_IS_FP16_ABGR', + 255: 'CB_PERF_SEL_FORMAT_IS_SIGNED16_ABGR', + 256: 'CB_PERF_SEL_FORMAT_IS_UNSIGNED16_ABGR', + 257: 'CB_PERF_SEL_FORMAT_IS_32BPP_8PIX', + 258: 'CB_PERF_SEL_FORMAT_IS_16_16_UNSIGNED_8PIX', + 259: 'CB_PERF_SEL_FORMAT_IS_16_16_SIGNED_8PIX', + 260: 'CB_PERF_SEL_FORMAT_IS_16_16_FLOAT_8PIX', + 261: 'CB_PERF_SEL_EXPORT_ADDED_1_FRAGMENT', + 262: 'CB_PERF_SEL_EXPORT_ADDED_2_FRAGMENTS', + 263: 'CB_PERF_SEL_EXPORT_ADDED_3_FRAGMENTS', + 264: 'CB_PERF_SEL_EXPORT_ADDED_4_FRAGMENTS', + 265: 'CB_PERF_SEL_EXPORT_ADDED_5_FRAGMENTS', + 266: 'CB_PERF_SEL_EXPORT_ADDED_6_FRAGMENTS', + 267: 'CB_PERF_SEL_EXPORT_ADDED_7_FRAGMENTS', + 268: 'CB_PERF_SEL_EXPORT_BLEND_OPT_DONT_READ_DST', + 269: 'CB_PERF_SEL_EXPORT_BLEND_OPT_BLEND_BYPASS', + 270: 'CB_PERF_SEL_EXPORT_BLEND_OPT_DISCARD_PIXELS', + 271: 'CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_BEFORE_UPDATE', + 272: 'CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_AFTER_UPDATE', + 273: 'CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_BEFORE_UPDATE', + 274: 'CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_AFTER_UPDATE', + 275: 'CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_BEFORE_UPDATE', + 276: 'CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_AFTER_UPDATE', + 277: 'CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_BEFORE_UPDATE', + 278: 'CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_AFTER_UPDATE', + 279: 'CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_BEFORE_UPDATE', + 280: 'CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_AFTER_UPDATE', + 281: 'CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_BEFORE_UPDATE', + 282: 'CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_AFTER_UPDATE', + 283: 'CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_BEFORE_UPDATE', + 284: 'CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_AFTER_UPDATE', + 285: 'CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_BEFORE_UPDATE', + 286: 'CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_AFTER_UPDATE', + 287: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_0', + 288: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_1', + 289: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_2', + 290: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_3', + 291: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_4', + 292: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_5', + 293: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_6', + 294: 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_7', + 295: 'CB_PERF_SEL_EXPORT_REMOVED_1_FRAGMENT', + 296: 'CB_PERF_SEL_EXPORT_REMOVED_2_FRAGMENTS', + 297: 'CB_PERF_SEL_EXPORT_REMOVED_3_FRAGMENTS', + 298: 'CB_PERF_SEL_EXPORT_REMOVED_4_FRAGMENTS', + 299: 'CB_PERF_SEL_EXPORT_REMOVED_5_FRAGMENTS', + 300: 'CB_PERF_SEL_EXPORT_REMOVED_6_FRAGMENTS', + 301: 'CB_PERF_SEL_EXPORT_REMOVED_7_FRAGMENTS', + 302: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_0', + 303: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_1', + 304: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_2', + 305: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_3', + 306: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_4', + 307: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_5', + 308: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_6', + 309: 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_7', + 310: 'CB_PERF_SEL_EXPORT_KILLED_BY_COLOR_INVALID', + 311: 'CB_PERF_SEL_EXPORT_KILLED_BY_DISCARD_PIXEL', + 312: 'CB_PERF_SEL_EXPORT_KILLED_BY_NULL_SAMPLE_MASK', + 313: 'CB_PERF_SEL_EXPORT_KILLED_BY_NULL_TARGET_SHADER_MASK', +} +CB_PERF_SEL_BUSY = 1 +CB_PERF_SEL_DRAWN_BUSY = 2 +CB_PERF_SEL_DRAWN_PIXEL = 3 +CB_PERF_SEL_DRAWN_QUAD = 4 +CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 5 +CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 15 +CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 16 +CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 17 +CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 18 +CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST = 21 +CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST_IN_FLIGHT = 22 +CB_PERF_SEL_CC_CRW_GLX_REQ_WRITE_REQUEST = 23 +CB_PERF_SEL_CC_CRW_GLX_SRC_WRITE_CYCLES = 24 +CB_PERF_SEL_CC_FDCC_COMPRESS_FRAG_TIDS_IN = 25 +CB_PERF_SEL_CC_FDCC_DECOMPRESS_FRAG_TIDS_OUT = 26 +CB_PERF_SEL_EVENT = 50 +CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 51 +CB_PERF_SEL_EVENT_CONTEXT_DONE = 52 +CB_PERF_SEL_EVENT_CACHE_FLUSH = 53 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 54 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 55 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 56 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 57 +CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS = 58 +CB_PERF_SEL_STATIC_CLOCK_EN = 60 +CB_PERF_SEL_PERFMON_CLOCK_EN = 61 +CB_PERF_SEL_BLEND_CLOCK_EN = 62 +CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 63 +CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 64 +CB_PERF_SEL_GRBM_CLOCK_EN = 65 +CB_PERF_SEL_MEMARB_CLOCK_EN = 66 +CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 67 +CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 68 +CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 69 +CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 70 +CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 71 +CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 72 +CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 73 +CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 74 +CB_PERF_SEL_EVENTS_CLK_EN = 75 +CB_PERF_SEL_CC_TAG_HIT = 80 +CB_PERF_SEL_CC_CACHE_TAG_MISS = 81 +CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 82 +CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 83 +CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 88 +CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 89 +CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 90 +CB_PERF_SEL_CC_CACHE_STALL = 91 +CB_PERF_SEL_CC_CACHE_FLUSH = 92 +CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 93 +CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 94 +CB_PERF_SEL_CC_CACHE_QBLOCKS_FLUSHED = 95 +CB_PERF_SEL_CC_CACHE_DIRTY_QBLOCKS_FLUSHED = 96 +CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 97 +CB_PERF_SEL_CCC_IN_EVICT_HAZARD_STALL = 98 +CB_PERF_SEL_CCC_COLOR_RESOURCE_PANIC = 99 +CB_PERF_SEL_CCC_FMASK_RESOURCE_PANIC = 100 +CB_PERF_SEL_CCC_FREE_WAYS_PANIC = 101 +CB_PERF_SEL_CCC_SKID_FIFO_FULL = 102 +CB_PERF_SEL_CCC_SKID_FIFO_STALL = 103 +CB_PERF_SEL_CCC_COLOR_RESOURCE_STALL = 104 +CB_PERF_SEL_CCC_FMASK_RESOURCE_STALL = 105 +CB_PERF_SEL_CCC_FREE_WAYS_STALL = 106 +CB_PERF_SEL_BE_SRCFIFO_FULL = 110 +CB_PERF_SEL_BE_RDLATFIFO_FULL = 111 +CB_PERF_SEL_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 112 +CB_PERF_SEL_CC_QUADFRAG_VALID_READY = 113 +CB_PERF_SEL_CC_QUADFRAG_VALID_READYB = 114 +CB_PERF_SEL_CC_QUADFRAG_VALIDB_READY = 115 +CB_PERF_SEL_CC_QUADFRAG_VALIDB_READYB = 116 +CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READY = 118 +CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READYB = 119 +CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READY = 120 +CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READYB = 121 +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 150 +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 151 +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 152 +CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 180 +CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 181 +CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 182 +CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 183 +CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 184 +CB_PERF_SEL_BLEND_STALL_ON_CACHE_ACCESS = 185 +CB_PERF_SEL_BLEND_COLLISION_DUE_TO_CACHE_WRITE = 186 +CB_PERF_SEL_BLEND_RAW_HAZARD_STALL = 187 +CB_PERF_SEL_BE_CS_FILLRATE_1X2 = 190 +CB_PERF_SEL_BE_CS_FILLRATE_2X1 = 191 +CB_PERF_SEL_BE_CS_FILLRATE_2X2 = 192 +CB_PERF_SEL_FORMAT_IS_32_R = 250 +CB_PERF_SEL_FORMAT_IS_32_AR = 251 +CB_PERF_SEL_FORMAT_IS_32_GR = 252 +CB_PERF_SEL_FORMAT_IS_32_ABGR = 253 +CB_PERF_SEL_FORMAT_IS_FP16_ABGR = 254 +CB_PERF_SEL_FORMAT_IS_SIGNED16_ABGR = 255 +CB_PERF_SEL_FORMAT_IS_UNSIGNED16_ABGR = 256 +CB_PERF_SEL_FORMAT_IS_32BPP_8PIX = 257 +CB_PERF_SEL_FORMAT_IS_16_16_UNSIGNED_8PIX = 258 +CB_PERF_SEL_FORMAT_IS_16_16_SIGNED_8PIX = 259 +CB_PERF_SEL_FORMAT_IS_16_16_FLOAT_8PIX = 260 +CB_PERF_SEL_EXPORT_ADDED_1_FRAGMENT = 261 +CB_PERF_SEL_EXPORT_ADDED_2_FRAGMENTS = 262 +CB_PERF_SEL_EXPORT_ADDED_3_FRAGMENTS = 263 +CB_PERF_SEL_EXPORT_ADDED_4_FRAGMENTS = 264 +CB_PERF_SEL_EXPORT_ADDED_5_FRAGMENTS = 265 +CB_PERF_SEL_EXPORT_ADDED_6_FRAGMENTS = 266 +CB_PERF_SEL_EXPORT_ADDED_7_FRAGMENTS = 267 +CB_PERF_SEL_EXPORT_BLEND_OPT_DONT_READ_DST = 268 +CB_PERF_SEL_EXPORT_BLEND_OPT_BLEND_BYPASS = 269 +CB_PERF_SEL_EXPORT_BLEND_OPT_DISCARD_PIXELS = 270 +CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_BEFORE_UPDATE = 271 +CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_AFTER_UPDATE = 272 +CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_BEFORE_UPDATE = 273 +CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_AFTER_UPDATE = 274 +CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_BEFORE_UPDATE = 275 +CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_AFTER_UPDATE = 276 +CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_BEFORE_UPDATE = 277 +CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_AFTER_UPDATE = 278 +CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_BEFORE_UPDATE = 279 +CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_AFTER_UPDATE = 280 +CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_BEFORE_UPDATE = 281 +CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_AFTER_UPDATE = 282 +CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_BEFORE_UPDATE = 283 +CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_AFTER_UPDATE = 284 +CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_BEFORE_UPDATE = 285 +CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_AFTER_UPDATE = 286 +CB_PERF_SEL_EXPORT_READS_FRAGMENT_0 = 287 +CB_PERF_SEL_EXPORT_READS_FRAGMENT_1 = 288 +CB_PERF_SEL_EXPORT_READS_FRAGMENT_2 = 289 +CB_PERF_SEL_EXPORT_READS_FRAGMENT_3 = 290 +CB_PERF_SEL_EXPORT_READS_FRAGMENT_4 = 291 +CB_PERF_SEL_EXPORT_READS_FRAGMENT_5 = 292 +CB_PERF_SEL_EXPORT_READS_FRAGMENT_6 = 293 +CB_PERF_SEL_EXPORT_READS_FRAGMENT_7 = 294 +CB_PERF_SEL_EXPORT_REMOVED_1_FRAGMENT = 295 +CB_PERF_SEL_EXPORT_REMOVED_2_FRAGMENTS = 296 +CB_PERF_SEL_EXPORT_REMOVED_3_FRAGMENTS = 297 +CB_PERF_SEL_EXPORT_REMOVED_4_FRAGMENTS = 298 +CB_PERF_SEL_EXPORT_REMOVED_5_FRAGMENTS = 299 +CB_PERF_SEL_EXPORT_REMOVED_6_FRAGMENTS = 300 +CB_PERF_SEL_EXPORT_REMOVED_7_FRAGMENTS = 301 +CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_0 = 302 +CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_1 = 303 +CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_2 = 304 +CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_3 = 305 +CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_4 = 306 +CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_5 = 307 +CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_6 = 308 +CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_7 = 309 +CB_PERF_SEL_EXPORT_KILLED_BY_COLOR_INVALID = 310 +CB_PERF_SEL_EXPORT_KILLED_BY_DISCARD_PIXEL = 311 +CB_PERF_SEL_EXPORT_KILLED_BY_NULL_SAMPLE_MASK = 312 +CB_PERF_SEL_EXPORT_KILLED_BY_NULL_TARGET_SHADER_MASK = 313 +CBPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'CombFunc' +CombFunc__enumvalues = { + 0: 'COMB_DST_PLUS_SRC', + 1: 'COMB_SRC_MINUS_DST', + 2: 'COMB_MIN_DST_SRC', + 3: 'COMB_MAX_DST_SRC', + 4: 'COMB_DST_MINUS_SRC', +} +COMB_DST_PLUS_SRC = 0 +COMB_SRC_MINUS_DST = 1 +COMB_MIN_DST_SRC = 2 +COMB_MAX_DST_SRC = 3 +COMB_DST_MINUS_SRC = 4 +CombFunc = ctypes.c_uint32 # enum + +# values for enumeration 'MemArbMode' +MemArbMode__enumvalues = { + 0: 'MEM_ARB_MODE_FIXED', + 1: 'MEM_ARB_MODE_AGE', + 2: 'MEM_ARB_MODE_WEIGHT', + 3: 'MEM_ARB_MODE_BOTH', +} +MEM_ARB_MODE_FIXED = 0 +MEM_ARB_MODE_AGE = 1 +MEM_ARB_MODE_WEIGHT = 2 +MEM_ARB_MODE_BOTH = 3 +MemArbMode = ctypes.c_uint32 # enum + +# values for enumeration 'PH_PERFCNT_SEL' +PH_PERFCNT_SEL__enumvalues = { + 0: 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', + 1: 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 2: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', + 3: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 4: 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', + 5: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', + 6: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 7: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 8: 'PH_PERF_SEL_SC0_ARB_BUSY', + 9: 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', + 10: 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', + 11: 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', + 12: 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', + 13: 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', + 14: 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', + 15: 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', + 16: 'PH_PERF_SEL_SC0_SEND', + 17: 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 18: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', + 19: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', + 20: 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', + 21: 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', + 22: 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', + 23: 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 24: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', + 25: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', + 26: 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', + 27: 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', + 28: 'PH_PERF_SEL_SC0_PA0_NULL_WE', + 29: 'PH_PERF_SEL_SC0_PA0_EVENT_WE', + 30: 'PH_PERF_SEL_SC0_PA0_FPOV_WE', + 31: 'PH_PERF_SEL_SC0_PA0_FPOP_WE', + 32: 'PH_PERF_SEL_SC0_PA0_EOP_WE', + 33: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', + 34: 'PH_PERF_SEL_SC0_PA0_EOPG_WE', + 35: 'PH_PERF_SEL_SC0_PA0_DEALLOC_WE', + 36: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', + 37: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', + 38: 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', + 39: 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', + 40: 'PH_PERF_SEL_SC0_PA1_NULL_WE', + 41: 'PH_PERF_SEL_SC0_PA1_EVENT_WE', + 42: 'PH_PERF_SEL_SC0_PA1_FPOV_WE', + 43: 'PH_PERF_SEL_SC0_PA1_FPOP_WE', + 44: 'PH_PERF_SEL_SC0_PA1_EOP_WE', + 45: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', + 46: 'PH_PERF_SEL_SC0_PA1_EOPG_WE', + 47: 'PH_PERF_SEL_SC0_PA1_DEALLOC_WE', + 48: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', + 49: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', + 50: 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', + 51: 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', + 52: 'PH_PERF_SEL_SC0_PA2_NULL_WE', + 53: 'PH_PERF_SEL_SC0_PA2_EVENT_WE', + 54: 'PH_PERF_SEL_SC0_PA2_FPOV_WE', + 55: 'PH_PERF_SEL_SC0_PA2_FPOP_WE', + 56: 'PH_PERF_SEL_SC0_PA2_EOP_WE', + 57: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', + 58: 'PH_PERF_SEL_SC0_PA2_EOPG_WE', + 59: 'PH_PERF_SEL_SC0_PA2_DEALLOC_WE', + 60: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', + 61: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', + 62: 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', + 63: 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', + 64: 'PH_PERF_SEL_SC0_PA3_NULL_WE', + 65: 'PH_PERF_SEL_SC0_PA3_EVENT_WE', + 66: 'PH_PERF_SEL_SC0_PA3_FPOV_WE', + 67: 'PH_PERF_SEL_SC0_PA3_FPOP_WE', + 68: 'PH_PERF_SEL_SC0_PA3_EOP_WE', + 69: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', + 70: 'PH_PERF_SEL_SC0_PA3_EOPG_WE', + 71: 'PH_PERF_SEL_SC0_PA3_DEALLOC_WE', + 72: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', + 73: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', + 74: 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', + 75: 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', + 76: 'PH_PERF_SEL_SC0_PA4_NULL_WE', + 77: 'PH_PERF_SEL_SC0_PA4_EVENT_WE', + 78: 'PH_PERF_SEL_SC0_PA4_FPOV_WE', + 79: 'PH_PERF_SEL_SC0_PA4_FPOP_WE', + 80: 'PH_PERF_SEL_SC0_PA4_EOP_WE', + 81: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', + 82: 'PH_PERF_SEL_SC0_PA4_EOPG_WE', + 83: 'PH_PERF_SEL_SC0_PA4_DEALLOC_WE', + 84: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', + 85: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', + 86: 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', + 87: 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', + 88: 'PH_PERF_SEL_SC0_PA5_NULL_WE', + 89: 'PH_PERF_SEL_SC0_PA5_EVENT_WE', + 90: 'PH_PERF_SEL_SC0_PA5_FPOV_WE', + 91: 'PH_PERF_SEL_SC0_PA5_FPOP_WE', + 92: 'PH_PERF_SEL_SC0_PA5_EOP_WE', + 93: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', + 94: 'PH_PERF_SEL_SC0_PA5_EOPG_WE', + 95: 'PH_PERF_SEL_SC0_PA5_DEALLOC_WE', + 96: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', + 97: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', + 98: 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', + 99: 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', + 100: 'PH_PERF_SEL_SC0_PA6_NULL_WE', + 101: 'PH_PERF_SEL_SC0_PA6_EVENT_WE', + 102: 'PH_PERF_SEL_SC0_PA6_FPOV_WE', + 103: 'PH_PERF_SEL_SC0_PA6_FPOP_WE', + 104: 'PH_PERF_SEL_SC0_PA6_EOP_WE', + 105: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', + 106: 'PH_PERF_SEL_SC0_PA6_EOPG_WE', + 107: 'PH_PERF_SEL_SC0_PA6_DEALLOC_WE', + 108: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', + 109: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', + 110: 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', + 111: 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', + 112: 'PH_PERF_SEL_SC0_PA7_NULL_WE', + 113: 'PH_PERF_SEL_SC0_PA7_EVENT_WE', + 114: 'PH_PERF_SEL_SC0_PA7_FPOV_WE', + 115: 'PH_PERF_SEL_SC0_PA7_FPOP_WE', + 116: 'PH_PERF_SEL_SC0_PA7_EOP_WE', + 117: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', + 118: 'PH_PERF_SEL_SC0_PA7_EOPG_WE', + 119: 'PH_PERF_SEL_SC0_PA7_DEALLOC_WE', + 120: 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', + 121: 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 122: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', + 123: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 124: 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', + 125: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', + 126: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 127: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 128: 'PH_PERF_SEL_SC1_ARB_BUSY', + 129: 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', + 130: 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', + 131: 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', + 132: 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', + 133: 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', + 134: 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', + 135: 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', + 136: 'PH_PERF_SEL_SC1_SEND', + 137: 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 138: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', + 139: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', + 140: 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', + 141: 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', + 142: 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 143: 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 144: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', + 145: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', + 146: 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', + 147: 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', + 148: 'PH_PERF_SEL_SC1_PA0_NULL_WE', + 149: 'PH_PERF_SEL_SC1_PA0_EVENT_WE', + 150: 'PH_PERF_SEL_SC1_PA0_FPOV_WE', + 151: 'PH_PERF_SEL_SC1_PA0_FPOP_WE', + 152: 'PH_PERF_SEL_SC1_PA0_EOP_WE', + 153: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', + 154: 'PH_PERF_SEL_SC1_PA0_EOPG_WE', + 155: 'PH_PERF_SEL_SC1_PA0_DEALLOC_WE', + 156: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', + 157: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', + 158: 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', + 159: 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', + 160: 'PH_PERF_SEL_SC1_PA1_NULL_WE', + 161: 'PH_PERF_SEL_SC1_PA1_EVENT_WE', + 162: 'PH_PERF_SEL_SC1_PA1_FPOV_WE', + 163: 'PH_PERF_SEL_SC1_PA1_FPOP_WE', + 164: 'PH_PERF_SEL_SC1_PA1_EOP_WE', + 165: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', + 166: 'PH_PERF_SEL_SC1_PA1_EOPG_WE', + 167: 'PH_PERF_SEL_SC1_PA1_DEALLOC_WE', + 168: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', + 169: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', + 170: 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', + 171: 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', + 172: 'PH_PERF_SEL_SC1_PA2_NULL_WE', + 173: 'PH_PERF_SEL_SC1_PA2_EVENT_WE', + 174: 'PH_PERF_SEL_SC1_PA2_FPOV_WE', + 175: 'PH_PERF_SEL_SC1_PA2_FPOP_WE', + 176: 'PH_PERF_SEL_SC1_PA2_EOP_WE', + 177: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', + 178: 'PH_PERF_SEL_SC1_PA2_EOPG_WE', + 179: 'PH_PERF_SEL_SC1_PA2_DEALLOC_WE', + 180: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', + 181: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', + 182: 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', + 183: 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', + 184: 'PH_PERF_SEL_SC1_PA3_NULL_WE', + 185: 'PH_PERF_SEL_SC1_PA3_EVENT_WE', + 186: 'PH_PERF_SEL_SC1_PA3_FPOV_WE', + 187: 'PH_PERF_SEL_SC1_PA3_FPOP_WE', + 188: 'PH_PERF_SEL_SC1_PA3_EOP_WE', + 189: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', + 190: 'PH_PERF_SEL_SC1_PA3_EOPG_WE', + 191: 'PH_PERF_SEL_SC1_PA3_DEALLOC_WE', + 192: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', + 193: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', + 194: 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', + 195: 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', + 196: 'PH_PERF_SEL_SC1_PA4_NULL_WE', + 197: 'PH_PERF_SEL_SC1_PA4_EVENT_WE', + 198: 'PH_PERF_SEL_SC1_PA4_FPOV_WE', + 199: 'PH_PERF_SEL_SC1_PA4_FPOP_WE', + 200: 'PH_PERF_SEL_SC1_PA4_EOP_WE', + 201: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', + 202: 'PH_PERF_SEL_SC1_PA4_EOPG_WE', + 203: 'PH_PERF_SEL_SC1_PA4_DEALLOC_WE', + 204: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', + 205: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', + 206: 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', + 207: 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', + 208: 'PH_PERF_SEL_SC1_PA5_NULL_WE', + 209: 'PH_PERF_SEL_SC1_PA5_EVENT_WE', + 210: 'PH_PERF_SEL_SC1_PA5_FPOV_WE', + 211: 'PH_PERF_SEL_SC1_PA5_FPOP_WE', + 212: 'PH_PERF_SEL_SC1_PA5_EOP_WE', + 213: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', + 214: 'PH_PERF_SEL_SC1_PA5_EOPG_WE', + 215: 'PH_PERF_SEL_SC1_PA5_DEALLOC_WE', + 216: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', + 217: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', + 218: 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', + 219: 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', + 220: 'PH_PERF_SEL_SC1_PA6_NULL_WE', + 221: 'PH_PERF_SEL_SC1_PA6_EVENT_WE', + 222: 'PH_PERF_SEL_SC1_PA6_FPOV_WE', + 223: 'PH_PERF_SEL_SC1_PA6_FPOP_WE', + 224: 'PH_PERF_SEL_SC1_PA6_EOP_WE', + 225: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', + 226: 'PH_PERF_SEL_SC1_PA6_EOPG_WE', + 227: 'PH_PERF_SEL_SC1_PA6_DEALLOC_WE', + 228: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', + 229: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', + 230: 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', + 231: 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', + 232: 'PH_PERF_SEL_SC1_PA7_NULL_WE', + 233: 'PH_PERF_SEL_SC1_PA7_EVENT_WE', + 234: 'PH_PERF_SEL_SC1_PA7_FPOV_WE', + 235: 'PH_PERF_SEL_SC1_PA7_FPOP_WE', + 236: 'PH_PERF_SEL_SC1_PA7_EOP_WE', + 237: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', + 238: 'PH_PERF_SEL_SC1_PA7_EOPG_WE', + 239: 'PH_PERF_SEL_SC1_PA7_DEALLOC_WE', + 240: 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', + 241: 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 242: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', + 243: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 244: 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', + 245: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', + 246: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 247: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 248: 'PH_PERF_SEL_SC2_ARB_BUSY', + 249: 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', + 250: 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', + 251: 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', + 252: 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', + 253: 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', + 254: 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', + 255: 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', + 256: 'PH_PERF_SEL_SC2_SEND', + 257: 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 258: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', + 259: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', + 260: 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', + 261: 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', + 262: 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 263: 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 264: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', + 265: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', + 266: 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', + 267: 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', + 268: 'PH_PERF_SEL_SC2_PA0_NULL_WE', + 269: 'PH_PERF_SEL_SC2_PA0_EVENT_WE', + 270: 'PH_PERF_SEL_SC2_PA0_FPOV_WE', + 271: 'PH_PERF_SEL_SC2_PA0_FPOP_WE', + 272: 'PH_PERF_SEL_SC2_PA0_EOP_WE', + 273: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', + 274: 'PH_PERF_SEL_SC2_PA0_EOPG_WE', + 275: 'PH_PERF_SEL_SC2_PA0_DEALLOC_WE', + 276: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', + 277: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', + 278: 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', + 279: 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', + 280: 'PH_PERF_SEL_SC2_PA1_NULL_WE', + 281: 'PH_PERF_SEL_SC2_PA1_EVENT_WE', + 282: 'PH_PERF_SEL_SC2_PA1_FPOV_WE', + 283: 'PH_PERF_SEL_SC2_PA1_FPOP_WE', + 284: 'PH_PERF_SEL_SC2_PA1_EOP_WE', + 285: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', + 286: 'PH_PERF_SEL_SC2_PA1_EOPG_WE', + 287: 'PH_PERF_SEL_SC2_PA1_DEALLOC_WE', + 288: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', + 289: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', + 290: 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', + 291: 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', + 292: 'PH_PERF_SEL_SC2_PA2_NULL_WE', + 293: 'PH_PERF_SEL_SC2_PA2_EVENT_WE', + 294: 'PH_PERF_SEL_SC2_PA2_FPOV_WE', + 295: 'PH_PERF_SEL_SC2_PA2_FPOP_WE', + 296: 'PH_PERF_SEL_SC2_PA2_EOP_WE', + 297: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', + 298: 'PH_PERF_SEL_SC2_PA2_EOPG_WE', + 299: 'PH_PERF_SEL_SC2_PA2_DEALLOC_WE', + 300: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', + 301: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', + 302: 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', + 303: 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', + 304: 'PH_PERF_SEL_SC2_PA3_NULL_WE', + 305: 'PH_PERF_SEL_SC2_PA3_EVENT_WE', + 306: 'PH_PERF_SEL_SC2_PA3_FPOV_WE', + 307: 'PH_PERF_SEL_SC2_PA3_FPOP_WE', + 308: 'PH_PERF_SEL_SC2_PA3_EOP_WE', + 309: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', + 310: 'PH_PERF_SEL_SC2_PA3_EOPG_WE', + 311: 'PH_PERF_SEL_SC2_PA3_DEALLOC_WE', + 312: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', + 313: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', + 314: 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', + 315: 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', + 316: 'PH_PERF_SEL_SC2_PA4_NULL_WE', + 317: 'PH_PERF_SEL_SC2_PA4_EVENT_WE', + 318: 'PH_PERF_SEL_SC2_PA4_FPOV_WE', + 319: 'PH_PERF_SEL_SC2_PA4_FPOP_WE', + 320: 'PH_PERF_SEL_SC2_PA4_EOP_WE', + 321: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', + 322: 'PH_PERF_SEL_SC2_PA4_EOPG_WE', + 323: 'PH_PERF_SEL_SC2_PA4_DEALLOC_WE', + 324: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', + 325: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', + 326: 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', + 327: 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', + 328: 'PH_PERF_SEL_SC2_PA5_NULL_WE', + 329: 'PH_PERF_SEL_SC2_PA5_EVENT_WE', + 330: 'PH_PERF_SEL_SC2_PA5_FPOV_WE', + 331: 'PH_PERF_SEL_SC2_PA5_FPOP_WE', + 332: 'PH_PERF_SEL_SC2_PA5_EOP_WE', + 333: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', + 334: 'PH_PERF_SEL_SC2_PA5_EOPG_WE', + 335: 'PH_PERF_SEL_SC2_PA5_DEALLOC_WE', + 336: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', + 337: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', + 338: 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', + 339: 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', + 340: 'PH_PERF_SEL_SC2_PA6_NULL_WE', + 341: 'PH_PERF_SEL_SC2_PA6_EVENT_WE', + 342: 'PH_PERF_SEL_SC2_PA6_FPOV_WE', + 343: 'PH_PERF_SEL_SC2_PA6_FPOP_WE', + 344: 'PH_PERF_SEL_SC2_PA6_EOP_WE', + 345: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', + 346: 'PH_PERF_SEL_SC2_PA6_EOPG_WE', + 347: 'PH_PERF_SEL_SC2_PA6_DEALLOC_WE', + 348: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', + 349: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', + 350: 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', + 351: 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', + 352: 'PH_PERF_SEL_SC2_PA7_NULL_WE', + 353: 'PH_PERF_SEL_SC2_PA7_EVENT_WE', + 354: 'PH_PERF_SEL_SC2_PA7_FPOV_WE', + 355: 'PH_PERF_SEL_SC2_PA7_FPOP_WE', + 356: 'PH_PERF_SEL_SC2_PA7_EOP_WE', + 357: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', + 358: 'PH_PERF_SEL_SC2_PA7_EOPG_WE', + 359: 'PH_PERF_SEL_SC2_PA7_DEALLOC_WE', + 360: 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', + 361: 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 362: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', + 363: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 364: 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', + 365: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', + 366: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 367: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 368: 'PH_PERF_SEL_SC3_ARB_BUSY', + 369: 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', + 370: 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', + 371: 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', + 372: 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', + 373: 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', + 374: 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', + 375: 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', + 376: 'PH_PERF_SEL_SC3_SEND', + 377: 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 378: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', + 379: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', + 380: 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', + 381: 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', + 382: 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 383: 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 384: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', + 385: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', + 386: 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', + 387: 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', + 388: 'PH_PERF_SEL_SC3_PA0_NULL_WE', + 389: 'PH_PERF_SEL_SC3_PA0_EVENT_WE', + 390: 'PH_PERF_SEL_SC3_PA0_FPOV_WE', + 391: 'PH_PERF_SEL_SC3_PA0_FPOP_WE', + 392: 'PH_PERF_SEL_SC3_PA0_EOP_WE', + 393: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', + 394: 'PH_PERF_SEL_SC3_PA0_EOPG_WE', + 395: 'PH_PERF_SEL_SC3_PA0_DEALLOC_WE', + 396: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', + 397: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', + 398: 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', + 399: 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', + 400: 'PH_PERF_SEL_SC3_PA1_NULL_WE', + 401: 'PH_PERF_SEL_SC3_PA1_EVENT_WE', + 402: 'PH_PERF_SEL_SC3_PA1_FPOV_WE', + 403: 'PH_PERF_SEL_SC3_PA1_FPOP_WE', + 404: 'PH_PERF_SEL_SC3_PA1_EOP_WE', + 405: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', + 406: 'PH_PERF_SEL_SC3_PA1_EOPG_WE', + 407: 'PH_PERF_SEL_SC3_PA1_DEALLOC_WE', + 408: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', + 409: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', + 410: 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', + 411: 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', + 412: 'PH_PERF_SEL_SC3_PA2_NULL_WE', + 413: 'PH_PERF_SEL_SC3_PA2_EVENT_WE', + 414: 'PH_PERF_SEL_SC3_PA2_FPOV_WE', + 415: 'PH_PERF_SEL_SC3_PA2_FPOP_WE', + 416: 'PH_PERF_SEL_SC3_PA2_EOP_WE', + 417: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', + 418: 'PH_PERF_SEL_SC3_PA2_EOPG_WE', + 419: 'PH_PERF_SEL_SC3_PA2_DEALLOC_WE', + 420: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', + 421: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', + 422: 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', + 423: 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', + 424: 'PH_PERF_SEL_SC3_PA3_NULL_WE', + 425: 'PH_PERF_SEL_SC3_PA3_EVENT_WE', + 426: 'PH_PERF_SEL_SC3_PA3_FPOV_WE', + 427: 'PH_PERF_SEL_SC3_PA3_FPOP_WE', + 428: 'PH_PERF_SEL_SC3_PA3_EOP_WE', + 429: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', + 430: 'PH_PERF_SEL_SC3_PA3_EOPG_WE', + 431: 'PH_PERF_SEL_SC3_PA3_DEALLOC_WE', + 432: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', + 433: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', + 434: 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', + 435: 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', + 436: 'PH_PERF_SEL_SC3_PA4_NULL_WE', + 437: 'PH_PERF_SEL_SC3_PA4_EVENT_WE', + 438: 'PH_PERF_SEL_SC3_PA4_FPOV_WE', + 439: 'PH_PERF_SEL_SC3_PA4_FPOP_WE', + 440: 'PH_PERF_SEL_SC3_PA4_EOP_WE', + 441: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', + 442: 'PH_PERF_SEL_SC3_PA4_EOPG_WE', + 443: 'PH_PERF_SEL_SC3_PA4_DEALLOC_WE', + 444: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', + 445: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', + 446: 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', + 447: 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', + 448: 'PH_PERF_SEL_SC3_PA5_NULL_WE', + 449: 'PH_PERF_SEL_SC3_PA5_EVENT_WE', + 450: 'PH_PERF_SEL_SC3_PA5_FPOV_WE', + 451: 'PH_PERF_SEL_SC3_PA5_FPOP_WE', + 452: 'PH_PERF_SEL_SC3_PA5_EOP_WE', + 453: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', + 454: 'PH_PERF_SEL_SC3_PA5_EOPG_WE', + 455: 'PH_PERF_SEL_SC3_PA5_DEALLOC_WE', + 456: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', + 457: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', + 458: 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', + 459: 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', + 460: 'PH_PERF_SEL_SC3_PA6_NULL_WE', + 461: 'PH_PERF_SEL_SC3_PA6_EVENT_WE', + 462: 'PH_PERF_SEL_SC3_PA6_FPOV_WE', + 463: 'PH_PERF_SEL_SC3_PA6_FPOP_WE', + 464: 'PH_PERF_SEL_SC3_PA6_EOP_WE', + 465: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', + 466: 'PH_PERF_SEL_SC3_PA6_EOPG_WE', + 467: 'PH_PERF_SEL_SC3_PA6_DEALLOC_WE', + 468: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', + 469: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', + 470: 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', + 471: 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', + 472: 'PH_PERF_SEL_SC3_PA7_NULL_WE', + 473: 'PH_PERF_SEL_SC3_PA7_EVENT_WE', + 474: 'PH_PERF_SEL_SC3_PA7_FPOV_WE', + 475: 'PH_PERF_SEL_SC3_PA7_FPOP_WE', + 476: 'PH_PERF_SEL_SC3_PA7_EOP_WE', + 477: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', + 478: 'PH_PERF_SEL_SC3_PA7_EOPG_WE', + 479: 'PH_PERF_SEL_SC3_PA7_DEALLOC_WE', + 480: 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', + 481: 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 482: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', + 483: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 484: 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', + 485: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', + 486: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 487: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 488: 'PH_PERF_SEL_SC4_ARB_BUSY', + 489: 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', + 490: 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', + 491: 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', + 492: 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', + 493: 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', + 494: 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', + 495: 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', + 496: 'PH_PERF_SEL_SC4_SEND', + 497: 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 498: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', + 499: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', + 500: 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', + 501: 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', + 502: 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 503: 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 504: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', + 505: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', + 506: 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', + 507: 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', + 508: 'PH_PERF_SEL_SC4_PA0_NULL_WE', + 509: 'PH_PERF_SEL_SC4_PA0_EVENT_WE', + 510: 'PH_PERF_SEL_SC4_PA0_FPOV_WE', + 511: 'PH_PERF_SEL_SC4_PA0_FPOP_WE', + 512: 'PH_PERF_SEL_SC4_PA0_EOP_WE', + 513: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', + 514: 'PH_PERF_SEL_SC4_PA0_EOPG_WE', + 515: 'PH_PERF_SEL_SC4_PA0_DEALLOC_WE', + 516: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', + 517: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', + 518: 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', + 519: 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', + 520: 'PH_PERF_SEL_SC4_PA1_NULL_WE', + 521: 'PH_PERF_SEL_SC4_PA1_EVENT_WE', + 522: 'PH_PERF_SEL_SC4_PA1_FPOV_WE', + 523: 'PH_PERF_SEL_SC4_PA1_FPOP_WE', + 524: 'PH_PERF_SEL_SC4_PA1_EOP_WE', + 525: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', + 526: 'PH_PERF_SEL_SC4_PA1_EOPG_WE', + 527: 'PH_PERF_SEL_SC4_PA1_DEALLOC_WE', + 528: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', + 529: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', + 530: 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', + 531: 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', + 532: 'PH_PERF_SEL_SC4_PA2_NULL_WE', + 533: 'PH_PERF_SEL_SC4_PA2_EVENT_WE', + 534: 'PH_PERF_SEL_SC4_PA2_FPOV_WE', + 535: 'PH_PERF_SEL_SC4_PA2_FPOP_WE', + 536: 'PH_PERF_SEL_SC4_PA2_EOP_WE', + 537: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', + 538: 'PH_PERF_SEL_SC4_PA2_EOPG_WE', + 539: 'PH_PERF_SEL_SC4_PA2_DEALLOC_WE', + 540: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', + 541: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', + 542: 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', + 543: 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', + 544: 'PH_PERF_SEL_SC4_PA3_NULL_WE', + 545: 'PH_PERF_SEL_SC4_PA3_EVENT_WE', + 546: 'PH_PERF_SEL_SC4_PA3_FPOV_WE', + 547: 'PH_PERF_SEL_SC4_PA3_FPOP_WE', + 548: 'PH_PERF_SEL_SC4_PA3_EOP_WE', + 549: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', + 550: 'PH_PERF_SEL_SC4_PA3_EOPG_WE', + 551: 'PH_PERF_SEL_SC4_PA3_DEALLOC_WE', + 552: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', + 553: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', + 554: 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', + 555: 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', + 556: 'PH_PERF_SEL_SC4_PA4_NULL_WE', + 557: 'PH_PERF_SEL_SC4_PA4_EVENT_WE', + 558: 'PH_PERF_SEL_SC4_PA4_FPOV_WE', + 559: 'PH_PERF_SEL_SC4_PA4_FPOP_WE', + 560: 'PH_PERF_SEL_SC4_PA4_EOP_WE', + 561: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', + 562: 'PH_PERF_SEL_SC4_PA4_EOPG_WE', + 563: 'PH_PERF_SEL_SC4_PA4_DEALLOC_WE', + 564: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', + 565: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', + 566: 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', + 567: 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', + 568: 'PH_PERF_SEL_SC4_PA5_NULL_WE', + 569: 'PH_PERF_SEL_SC4_PA5_EVENT_WE', + 570: 'PH_PERF_SEL_SC4_PA5_FPOV_WE', + 571: 'PH_PERF_SEL_SC4_PA5_FPOP_WE', + 572: 'PH_PERF_SEL_SC4_PA5_EOP_WE', + 573: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', + 574: 'PH_PERF_SEL_SC4_PA5_EOPG_WE', + 575: 'PH_PERF_SEL_SC4_PA5_DEALLOC_WE', + 576: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', + 577: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', + 578: 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', + 579: 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', + 580: 'PH_PERF_SEL_SC4_PA6_NULL_WE', + 581: 'PH_PERF_SEL_SC4_PA6_EVENT_WE', + 582: 'PH_PERF_SEL_SC4_PA6_FPOV_WE', + 583: 'PH_PERF_SEL_SC4_PA6_FPOP_WE', + 584: 'PH_PERF_SEL_SC4_PA6_EOP_WE', + 585: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', + 586: 'PH_PERF_SEL_SC4_PA6_EOPG_WE', + 587: 'PH_PERF_SEL_SC4_PA6_DEALLOC_WE', + 588: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', + 589: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', + 590: 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', + 591: 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', + 592: 'PH_PERF_SEL_SC4_PA7_NULL_WE', + 593: 'PH_PERF_SEL_SC4_PA7_EVENT_WE', + 594: 'PH_PERF_SEL_SC4_PA7_FPOV_WE', + 595: 'PH_PERF_SEL_SC4_PA7_FPOP_WE', + 596: 'PH_PERF_SEL_SC4_PA7_EOP_WE', + 597: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', + 598: 'PH_PERF_SEL_SC4_PA7_EOPG_WE', + 599: 'PH_PERF_SEL_SC4_PA7_DEALLOC_WE', + 600: 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', + 601: 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 602: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', + 603: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 604: 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', + 605: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', + 606: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 607: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 608: 'PH_PERF_SEL_SC5_ARB_BUSY', + 609: 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', + 610: 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', + 611: 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', + 612: 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', + 613: 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', + 614: 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', + 615: 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', + 616: 'PH_PERF_SEL_SC5_SEND', + 617: 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 618: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', + 619: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', + 620: 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', + 621: 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', + 622: 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 623: 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 624: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', + 625: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', + 626: 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', + 627: 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', + 628: 'PH_PERF_SEL_SC5_PA0_NULL_WE', + 629: 'PH_PERF_SEL_SC5_PA0_EVENT_WE', + 630: 'PH_PERF_SEL_SC5_PA0_FPOV_WE', + 631: 'PH_PERF_SEL_SC5_PA0_FPOP_WE', + 632: 'PH_PERF_SEL_SC5_PA0_EOP_WE', + 633: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', + 634: 'PH_PERF_SEL_SC5_PA0_EOPG_WE', + 635: 'PH_PERF_SEL_SC5_PA0_DEALLOC_WE', + 636: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', + 637: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', + 638: 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', + 639: 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', + 640: 'PH_PERF_SEL_SC5_PA1_NULL_WE', + 641: 'PH_PERF_SEL_SC5_PA1_EVENT_WE', + 642: 'PH_PERF_SEL_SC5_PA1_FPOV_WE', + 643: 'PH_PERF_SEL_SC5_PA1_FPOP_WE', + 644: 'PH_PERF_SEL_SC5_PA1_EOP_WE', + 645: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', + 646: 'PH_PERF_SEL_SC5_PA1_EOPG_WE', + 647: 'PH_PERF_SEL_SC5_PA1_DEALLOC_WE', + 648: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', + 649: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', + 650: 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', + 651: 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', + 652: 'PH_PERF_SEL_SC5_PA2_NULL_WE', + 653: 'PH_PERF_SEL_SC5_PA2_EVENT_WE', + 654: 'PH_PERF_SEL_SC5_PA2_FPOV_WE', + 655: 'PH_PERF_SEL_SC5_PA2_FPOP_WE', + 656: 'PH_PERF_SEL_SC5_PA2_EOP_WE', + 657: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', + 658: 'PH_PERF_SEL_SC5_PA2_EOPG_WE', + 659: 'PH_PERF_SEL_SC5_PA2_DEALLOC_WE', + 660: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', + 661: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', + 662: 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', + 663: 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', + 664: 'PH_PERF_SEL_SC5_PA3_NULL_WE', + 665: 'PH_PERF_SEL_SC5_PA3_EVENT_WE', + 666: 'PH_PERF_SEL_SC5_PA3_FPOV_WE', + 667: 'PH_PERF_SEL_SC5_PA3_FPOP_WE', + 668: 'PH_PERF_SEL_SC5_PA3_EOP_WE', + 669: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', + 670: 'PH_PERF_SEL_SC5_PA3_EOPG_WE', + 671: 'PH_PERF_SEL_SC5_PA3_DEALLOC_WE', + 672: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', + 673: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', + 674: 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', + 675: 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', + 676: 'PH_PERF_SEL_SC5_PA4_NULL_WE', + 677: 'PH_PERF_SEL_SC5_PA4_EVENT_WE', + 678: 'PH_PERF_SEL_SC5_PA4_FPOV_WE', + 679: 'PH_PERF_SEL_SC5_PA4_FPOP_WE', + 680: 'PH_PERF_SEL_SC5_PA4_EOP_WE', + 681: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', + 682: 'PH_PERF_SEL_SC5_PA4_EOPG_WE', + 683: 'PH_PERF_SEL_SC5_PA4_DEALLOC_WE', + 684: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', + 685: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', + 686: 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', + 687: 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', + 688: 'PH_PERF_SEL_SC5_PA5_NULL_WE', + 689: 'PH_PERF_SEL_SC5_PA5_EVENT_WE', + 690: 'PH_PERF_SEL_SC5_PA5_FPOV_WE', + 691: 'PH_PERF_SEL_SC5_PA5_FPOP_WE', + 692: 'PH_PERF_SEL_SC5_PA5_EOP_WE', + 693: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', + 694: 'PH_PERF_SEL_SC5_PA5_EOPG_WE', + 695: 'PH_PERF_SEL_SC5_PA5_DEALLOC_WE', + 696: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', + 697: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', + 698: 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', + 699: 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', + 700: 'PH_PERF_SEL_SC5_PA6_NULL_WE', + 701: 'PH_PERF_SEL_SC5_PA6_EVENT_WE', + 702: 'PH_PERF_SEL_SC5_PA6_FPOV_WE', + 703: 'PH_PERF_SEL_SC5_PA6_FPOP_WE', + 704: 'PH_PERF_SEL_SC5_PA6_EOP_WE', + 705: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', + 706: 'PH_PERF_SEL_SC5_PA6_EOPG_WE', + 707: 'PH_PERF_SEL_SC5_PA6_DEALLOC_WE', + 708: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', + 709: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', + 710: 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', + 711: 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', + 712: 'PH_PERF_SEL_SC5_PA7_NULL_WE', + 713: 'PH_PERF_SEL_SC5_PA7_EVENT_WE', + 714: 'PH_PERF_SEL_SC5_PA7_FPOV_WE', + 715: 'PH_PERF_SEL_SC5_PA7_FPOP_WE', + 716: 'PH_PERF_SEL_SC5_PA7_EOP_WE', + 717: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', + 718: 'PH_PERF_SEL_SC5_PA7_EOPG_WE', + 719: 'PH_PERF_SEL_SC5_PA7_DEALLOC_WE', + 720: 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', + 721: 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 722: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', + 723: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 724: 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', + 725: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', + 726: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 727: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 728: 'PH_PERF_SEL_SC6_ARB_BUSY', + 729: 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', + 730: 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', + 731: 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', + 732: 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', + 733: 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', + 734: 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', + 735: 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', + 736: 'PH_PERF_SEL_SC6_SEND', + 737: 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 738: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', + 739: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', + 740: 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', + 741: 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', + 742: 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 743: 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 744: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', + 745: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', + 746: 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', + 747: 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', + 748: 'PH_PERF_SEL_SC6_PA0_NULL_WE', + 749: 'PH_PERF_SEL_SC6_PA0_EVENT_WE', + 750: 'PH_PERF_SEL_SC6_PA0_FPOV_WE', + 751: 'PH_PERF_SEL_SC6_PA0_FPOP_WE', + 752: 'PH_PERF_SEL_SC6_PA0_EOP_WE', + 753: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', + 754: 'PH_PERF_SEL_SC6_PA0_EOPG_WE', + 755: 'PH_PERF_SEL_SC6_PA0_DEALLOC_WE', + 756: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', + 757: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', + 758: 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', + 759: 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', + 760: 'PH_PERF_SEL_SC6_PA1_NULL_WE', + 761: 'PH_PERF_SEL_SC6_PA1_EVENT_WE', + 762: 'PH_PERF_SEL_SC6_PA1_FPOV_WE', + 763: 'PH_PERF_SEL_SC6_PA1_FPOP_WE', + 764: 'PH_PERF_SEL_SC6_PA1_EOP_WE', + 765: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', + 766: 'PH_PERF_SEL_SC6_PA1_EOPG_WE', + 767: 'PH_PERF_SEL_SC6_PA1_DEALLOC_WE', + 768: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', + 769: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', + 770: 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', + 771: 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', + 772: 'PH_PERF_SEL_SC6_PA2_NULL_WE', + 773: 'PH_PERF_SEL_SC6_PA2_EVENT_WE', + 774: 'PH_PERF_SEL_SC6_PA2_FPOV_WE', + 775: 'PH_PERF_SEL_SC6_PA2_FPOP_WE', + 776: 'PH_PERF_SEL_SC6_PA2_EOP_WE', + 777: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', + 778: 'PH_PERF_SEL_SC6_PA2_EOPG_WE', + 779: 'PH_PERF_SEL_SC6_PA2_DEALLOC_WE', + 780: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', + 781: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', + 782: 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', + 783: 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', + 784: 'PH_PERF_SEL_SC6_PA3_NULL_WE', + 785: 'PH_PERF_SEL_SC6_PA3_EVENT_WE', + 786: 'PH_PERF_SEL_SC6_PA3_FPOV_WE', + 787: 'PH_PERF_SEL_SC6_PA3_FPOP_WE', + 788: 'PH_PERF_SEL_SC6_PA3_EOP_WE', + 789: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', + 790: 'PH_PERF_SEL_SC6_PA3_EOPG_WE', + 791: 'PH_PERF_SEL_SC6_PA3_DEALLOC_WE', + 792: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', + 793: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', + 794: 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', + 795: 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', + 796: 'PH_PERF_SEL_SC6_PA4_NULL_WE', + 797: 'PH_PERF_SEL_SC6_PA4_EVENT_WE', + 798: 'PH_PERF_SEL_SC6_PA4_FPOV_WE', + 799: 'PH_PERF_SEL_SC6_PA4_FPOP_WE', + 800: 'PH_PERF_SEL_SC6_PA4_EOP_WE', + 801: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', + 802: 'PH_PERF_SEL_SC6_PA4_EOPG_WE', + 803: 'PH_PERF_SEL_SC6_PA4_DEALLOC_WE', + 804: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', + 805: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', + 806: 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', + 807: 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', + 808: 'PH_PERF_SEL_SC6_PA5_NULL_WE', + 809: 'PH_PERF_SEL_SC6_PA5_EVENT_WE', + 810: 'PH_PERF_SEL_SC6_PA5_FPOV_WE', + 811: 'PH_PERF_SEL_SC6_PA5_FPOP_WE', + 812: 'PH_PERF_SEL_SC6_PA5_EOP_WE', + 813: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', + 814: 'PH_PERF_SEL_SC6_PA5_EOPG_WE', + 815: 'PH_PERF_SEL_SC6_PA5_DEALLOC_WE', + 816: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', + 817: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', + 818: 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', + 819: 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', + 820: 'PH_PERF_SEL_SC6_PA6_NULL_WE', + 821: 'PH_PERF_SEL_SC6_PA6_EVENT_WE', + 822: 'PH_PERF_SEL_SC6_PA6_FPOV_WE', + 823: 'PH_PERF_SEL_SC6_PA6_FPOP_WE', + 824: 'PH_PERF_SEL_SC6_PA6_EOP_WE', + 825: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', + 826: 'PH_PERF_SEL_SC6_PA6_EOPG_WE', + 827: 'PH_PERF_SEL_SC6_PA6_DEALLOC_WE', + 828: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', + 829: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', + 830: 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', + 831: 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', + 832: 'PH_PERF_SEL_SC6_PA7_NULL_WE', + 833: 'PH_PERF_SEL_SC6_PA7_EVENT_WE', + 834: 'PH_PERF_SEL_SC6_PA7_FPOV_WE', + 835: 'PH_PERF_SEL_SC6_PA7_FPOP_WE', + 836: 'PH_PERF_SEL_SC6_PA7_EOP_WE', + 837: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', + 838: 'PH_PERF_SEL_SC6_PA7_EOPG_WE', + 839: 'PH_PERF_SEL_SC6_PA7_DEALLOC_WE', + 840: 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', + 841: 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 842: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', + 843: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 844: 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', + 845: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', + 846: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 847: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 848: 'PH_PERF_SEL_SC7_ARB_BUSY', + 849: 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', + 850: 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', + 851: 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', + 852: 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', + 853: 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', + 854: 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', + 855: 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', + 856: 'PH_PERF_SEL_SC7_SEND', + 857: 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 858: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', + 859: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', + 860: 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', + 861: 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', + 862: 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 863: 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 864: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', + 865: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', + 866: 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', + 867: 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', + 868: 'PH_PERF_SEL_SC7_PA0_NULL_WE', + 869: 'PH_PERF_SEL_SC7_PA0_EVENT_WE', + 870: 'PH_PERF_SEL_SC7_PA0_FPOV_WE', + 871: 'PH_PERF_SEL_SC7_PA0_FPOP_WE', + 872: 'PH_PERF_SEL_SC7_PA0_EOP_WE', + 873: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', + 874: 'PH_PERF_SEL_SC7_PA0_EOPG_WE', + 875: 'PH_PERF_SEL_SC7_PA0_DEALLOC_WE', + 876: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', + 877: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', + 878: 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', + 879: 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', + 880: 'PH_PERF_SEL_SC7_PA1_NULL_WE', + 881: 'PH_PERF_SEL_SC7_PA1_EVENT_WE', + 882: 'PH_PERF_SEL_SC7_PA1_FPOV_WE', + 883: 'PH_PERF_SEL_SC7_PA1_FPOP_WE', + 884: 'PH_PERF_SEL_SC7_PA1_EOP_WE', + 885: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', + 886: 'PH_PERF_SEL_SC7_PA1_EOPG_WE', + 887: 'PH_PERF_SEL_SC7_PA1_DEALLOC_WE', + 888: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', + 889: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', + 890: 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', + 891: 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', + 892: 'PH_PERF_SEL_SC7_PA2_NULL_WE', + 893: 'PH_PERF_SEL_SC7_PA2_EVENT_WE', + 894: 'PH_PERF_SEL_SC7_PA2_FPOV_WE', + 895: 'PH_PERF_SEL_SC7_PA2_FPOP_WE', + 896: 'PH_PERF_SEL_SC7_PA2_EOP_WE', + 897: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', + 898: 'PH_PERF_SEL_SC7_PA2_EOPG_WE', + 899: 'PH_PERF_SEL_SC7_PA2_DEALLOC_WE', + 900: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', + 901: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', + 902: 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', + 903: 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', + 904: 'PH_PERF_SEL_SC7_PA3_NULL_WE', + 905: 'PH_PERF_SEL_SC7_PA3_EVENT_WE', + 906: 'PH_PERF_SEL_SC7_PA3_FPOV_WE', + 907: 'PH_PERF_SEL_SC7_PA3_FPOP_WE', + 908: 'PH_PERF_SEL_SC7_PA3_EOP_WE', + 909: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', + 910: 'PH_PERF_SEL_SC7_PA3_EOPG_WE', + 911: 'PH_PERF_SEL_SC7_PA3_DEALLOC_WE', + 912: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', + 913: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', + 914: 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', + 915: 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', + 916: 'PH_PERF_SEL_SC7_PA4_NULL_WE', + 917: 'PH_PERF_SEL_SC7_PA4_EVENT_WE', + 918: 'PH_PERF_SEL_SC7_PA4_FPOV_WE', + 919: 'PH_PERF_SEL_SC7_PA4_FPOP_WE', + 920: 'PH_PERF_SEL_SC7_PA4_EOP_WE', + 921: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', + 922: 'PH_PERF_SEL_SC7_PA4_EOPG_WE', + 923: 'PH_PERF_SEL_SC7_PA4_DEALLOC_WE', + 924: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', + 925: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', + 926: 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', + 927: 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', + 928: 'PH_PERF_SEL_SC7_PA5_NULL_WE', + 929: 'PH_PERF_SEL_SC7_PA5_EVENT_WE', + 930: 'PH_PERF_SEL_SC7_PA5_FPOV_WE', + 931: 'PH_PERF_SEL_SC7_PA5_FPOP_WE', + 932: 'PH_PERF_SEL_SC7_PA5_EOP_WE', + 933: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', + 934: 'PH_PERF_SEL_SC7_PA5_EOPG_WE', + 935: 'PH_PERF_SEL_SC7_PA5_DEALLOC_WE', + 936: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', + 937: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', + 938: 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', + 939: 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', + 940: 'PH_PERF_SEL_SC7_PA6_NULL_WE', + 941: 'PH_PERF_SEL_SC7_PA6_EVENT_WE', + 942: 'PH_PERF_SEL_SC7_PA6_FPOV_WE', + 943: 'PH_PERF_SEL_SC7_PA6_FPOP_WE', + 944: 'PH_PERF_SEL_SC7_PA6_EOP_WE', + 945: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', + 946: 'PH_PERF_SEL_SC7_PA6_EOPG_WE', + 947: 'PH_PERF_SEL_SC7_PA6_DEALLOC_WE', + 948: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', + 949: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', + 950: 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', + 951: 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', + 952: 'PH_PERF_SEL_SC7_PA7_NULL_WE', + 953: 'PH_PERF_SEL_SC7_PA7_EVENT_WE', + 954: 'PH_PERF_SEL_SC7_PA7_FPOV_WE', + 955: 'PH_PERF_SEL_SC7_PA7_FPOP_WE', + 956: 'PH_PERF_SEL_SC7_PA7_EOP_WE', + 957: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', + 958: 'PH_PERF_SEL_SC7_PA7_EOPG_WE', + 959: 'PH_PERF_SEL_SC7_PA7_DEALLOC_WE', + 960: 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', + 961: 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', + 962: 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', + 963: 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', + 964: 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', + 965: 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', + 966: 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', + 967: 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', + 968: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', + 969: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', + 970: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', + 971: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', + 972: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', + 973: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', + 974: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', + 975: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', + 976: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 977: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 978: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 979: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 980: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 981: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 982: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 983: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 984: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 985: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 986: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 987: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 988: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 989: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 990: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 991: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 992: 'PH_PERF_SC0_FIFO_STATUS_0', + 993: 'PH_PERF_SC0_FIFO_STATUS_1', + 994: 'PH_PERF_SC0_FIFO_STATUS_2', + 995: 'PH_PERF_SC0_FIFO_STATUS_3', + 996: 'PH_PERF_SC1_FIFO_STATUS_0', + 997: 'PH_PERF_SC1_FIFO_STATUS_1', + 998: 'PH_PERF_SC1_FIFO_STATUS_2', + 999: 'PH_PERF_SC1_FIFO_STATUS_3', + 1000: 'PH_PERF_SC2_FIFO_STATUS_0', + 1001: 'PH_PERF_SC2_FIFO_STATUS_1', + 1002: 'PH_PERF_SC2_FIFO_STATUS_2', + 1003: 'PH_PERF_SC2_FIFO_STATUS_3', + 1004: 'PH_PERF_SC3_FIFO_STATUS_0', + 1005: 'PH_PERF_SC3_FIFO_STATUS_1', + 1006: 'PH_PERF_SC3_FIFO_STATUS_2', + 1007: 'PH_PERF_SC3_FIFO_STATUS_3', + 1008: 'PH_PERF_SC4_FIFO_STATUS_0', + 1009: 'PH_PERF_SC4_FIFO_STATUS_1', + 1010: 'PH_PERF_SC4_FIFO_STATUS_2', + 1011: 'PH_PERF_SC4_FIFO_STATUS_3', + 1012: 'PH_PERF_SC5_FIFO_STATUS_0', + 1013: 'PH_PERF_SC5_FIFO_STATUS_1', + 1014: 'PH_PERF_SC5_FIFO_STATUS_2', + 1015: 'PH_PERF_SC5_FIFO_STATUS_3', + 1016: 'PH_PERF_SC6_FIFO_STATUS_0', + 1017: 'PH_PERF_SC6_FIFO_STATUS_1', + 1018: 'PH_PERF_SC6_FIFO_STATUS_2', + 1019: 'PH_PERF_SC6_FIFO_STATUS_3', + 1020: 'PH_PERF_SC7_FIFO_STATUS_0', + 1021: 'PH_PERF_SC7_FIFO_STATUS_1', + 1022: 'PH_PERF_SC7_FIFO_STATUS_2', + 1023: 'PH_PERF_SC7_FIFO_STATUS_3', +} +PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0 +PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 1 +PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 2 +PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 3 +PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 4 +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 5 +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 6 +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 7 +PH_PERF_SEL_SC0_ARB_BUSY = 8 +PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 9 +PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 10 +PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 11 +PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 12 +PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 13 +PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 14 +PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 15 +PH_PERF_SEL_SC0_SEND = 16 +PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 17 +PH_PERF_SEL_SC0_CREDIT_AT_MAX = 18 +PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 19 +PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 20 +PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 21 +PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 22 +PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 23 +PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 24 +PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 25 +PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 26 +PH_PERF_SEL_SC0_PA0_FIFO_FULL = 27 +PH_PERF_SEL_SC0_PA0_NULL_WE = 28 +PH_PERF_SEL_SC0_PA0_EVENT_WE = 29 +PH_PERF_SEL_SC0_PA0_FPOV_WE = 30 +PH_PERF_SEL_SC0_PA0_FPOP_WE = 31 +PH_PERF_SEL_SC0_PA0_EOP_WE = 32 +PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 33 +PH_PERF_SEL_SC0_PA0_EOPG_WE = 34 +PH_PERF_SEL_SC0_PA0_DEALLOC_WE = 35 +PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 36 +PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 37 +PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 38 +PH_PERF_SEL_SC0_PA1_FIFO_FULL = 39 +PH_PERF_SEL_SC0_PA1_NULL_WE = 40 +PH_PERF_SEL_SC0_PA1_EVENT_WE = 41 +PH_PERF_SEL_SC0_PA1_FPOV_WE = 42 +PH_PERF_SEL_SC0_PA1_FPOP_WE = 43 +PH_PERF_SEL_SC0_PA1_EOP_WE = 44 +PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 45 +PH_PERF_SEL_SC0_PA1_EOPG_WE = 46 +PH_PERF_SEL_SC0_PA1_DEALLOC_WE = 47 +PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 48 +PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 49 +PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 50 +PH_PERF_SEL_SC0_PA2_FIFO_FULL = 51 +PH_PERF_SEL_SC0_PA2_NULL_WE = 52 +PH_PERF_SEL_SC0_PA2_EVENT_WE = 53 +PH_PERF_SEL_SC0_PA2_FPOV_WE = 54 +PH_PERF_SEL_SC0_PA2_FPOP_WE = 55 +PH_PERF_SEL_SC0_PA2_EOP_WE = 56 +PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 57 +PH_PERF_SEL_SC0_PA2_EOPG_WE = 58 +PH_PERF_SEL_SC0_PA2_DEALLOC_WE = 59 +PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 60 +PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 61 +PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 62 +PH_PERF_SEL_SC0_PA3_FIFO_FULL = 63 +PH_PERF_SEL_SC0_PA3_NULL_WE = 64 +PH_PERF_SEL_SC0_PA3_EVENT_WE = 65 +PH_PERF_SEL_SC0_PA3_FPOV_WE = 66 +PH_PERF_SEL_SC0_PA3_FPOP_WE = 67 +PH_PERF_SEL_SC0_PA3_EOP_WE = 68 +PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 69 +PH_PERF_SEL_SC0_PA3_EOPG_WE = 70 +PH_PERF_SEL_SC0_PA3_DEALLOC_WE = 71 +PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 72 +PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 73 +PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 74 +PH_PERF_SEL_SC0_PA4_FIFO_FULL = 75 +PH_PERF_SEL_SC0_PA4_NULL_WE = 76 +PH_PERF_SEL_SC0_PA4_EVENT_WE = 77 +PH_PERF_SEL_SC0_PA4_FPOV_WE = 78 +PH_PERF_SEL_SC0_PA4_FPOP_WE = 79 +PH_PERF_SEL_SC0_PA4_EOP_WE = 80 +PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 81 +PH_PERF_SEL_SC0_PA4_EOPG_WE = 82 +PH_PERF_SEL_SC0_PA4_DEALLOC_WE = 83 +PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 84 +PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 85 +PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 86 +PH_PERF_SEL_SC0_PA5_FIFO_FULL = 87 +PH_PERF_SEL_SC0_PA5_NULL_WE = 88 +PH_PERF_SEL_SC0_PA5_EVENT_WE = 89 +PH_PERF_SEL_SC0_PA5_FPOV_WE = 90 +PH_PERF_SEL_SC0_PA5_FPOP_WE = 91 +PH_PERF_SEL_SC0_PA5_EOP_WE = 92 +PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 93 +PH_PERF_SEL_SC0_PA5_EOPG_WE = 94 +PH_PERF_SEL_SC0_PA5_DEALLOC_WE = 95 +PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 96 +PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 97 +PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 98 +PH_PERF_SEL_SC0_PA6_FIFO_FULL = 99 +PH_PERF_SEL_SC0_PA6_NULL_WE = 100 +PH_PERF_SEL_SC0_PA6_EVENT_WE = 101 +PH_PERF_SEL_SC0_PA6_FPOV_WE = 102 +PH_PERF_SEL_SC0_PA6_FPOP_WE = 103 +PH_PERF_SEL_SC0_PA6_EOP_WE = 104 +PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 105 +PH_PERF_SEL_SC0_PA6_EOPG_WE = 106 +PH_PERF_SEL_SC0_PA6_DEALLOC_WE = 107 +PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 108 +PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 109 +PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 110 +PH_PERF_SEL_SC0_PA7_FIFO_FULL = 111 +PH_PERF_SEL_SC0_PA7_NULL_WE = 112 +PH_PERF_SEL_SC0_PA7_EVENT_WE = 113 +PH_PERF_SEL_SC0_PA7_FPOV_WE = 114 +PH_PERF_SEL_SC0_PA7_FPOP_WE = 115 +PH_PERF_SEL_SC0_PA7_EOP_WE = 116 +PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 117 +PH_PERF_SEL_SC0_PA7_EOPG_WE = 118 +PH_PERF_SEL_SC0_PA7_DEALLOC_WE = 119 +PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 120 +PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 121 +PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 122 +PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 123 +PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 124 +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 125 +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 126 +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 127 +PH_PERF_SEL_SC1_ARB_BUSY = 128 +PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 129 +PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 130 +PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 131 +PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 132 +PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 133 +PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 134 +PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 135 +PH_PERF_SEL_SC1_SEND = 136 +PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 137 +PH_PERF_SEL_SC1_CREDIT_AT_MAX = 138 +PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 139 +PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 140 +PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 141 +PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 142 +PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 143 +PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 144 +PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 145 +PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 146 +PH_PERF_SEL_SC1_PA0_FIFO_FULL = 147 +PH_PERF_SEL_SC1_PA0_NULL_WE = 148 +PH_PERF_SEL_SC1_PA0_EVENT_WE = 149 +PH_PERF_SEL_SC1_PA0_FPOV_WE = 150 +PH_PERF_SEL_SC1_PA0_FPOP_WE = 151 +PH_PERF_SEL_SC1_PA0_EOP_WE = 152 +PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 153 +PH_PERF_SEL_SC1_PA0_EOPG_WE = 154 +PH_PERF_SEL_SC1_PA0_DEALLOC_WE = 155 +PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 156 +PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 157 +PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 158 +PH_PERF_SEL_SC1_PA1_FIFO_FULL = 159 +PH_PERF_SEL_SC1_PA1_NULL_WE = 160 +PH_PERF_SEL_SC1_PA1_EVENT_WE = 161 +PH_PERF_SEL_SC1_PA1_FPOV_WE = 162 +PH_PERF_SEL_SC1_PA1_FPOP_WE = 163 +PH_PERF_SEL_SC1_PA1_EOP_WE = 164 +PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 165 +PH_PERF_SEL_SC1_PA1_EOPG_WE = 166 +PH_PERF_SEL_SC1_PA1_DEALLOC_WE = 167 +PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 168 +PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 169 +PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 170 +PH_PERF_SEL_SC1_PA2_FIFO_FULL = 171 +PH_PERF_SEL_SC1_PA2_NULL_WE = 172 +PH_PERF_SEL_SC1_PA2_EVENT_WE = 173 +PH_PERF_SEL_SC1_PA2_FPOV_WE = 174 +PH_PERF_SEL_SC1_PA2_FPOP_WE = 175 +PH_PERF_SEL_SC1_PA2_EOP_WE = 176 +PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 177 +PH_PERF_SEL_SC1_PA2_EOPG_WE = 178 +PH_PERF_SEL_SC1_PA2_DEALLOC_WE = 179 +PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 180 +PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 181 +PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 182 +PH_PERF_SEL_SC1_PA3_FIFO_FULL = 183 +PH_PERF_SEL_SC1_PA3_NULL_WE = 184 +PH_PERF_SEL_SC1_PA3_EVENT_WE = 185 +PH_PERF_SEL_SC1_PA3_FPOV_WE = 186 +PH_PERF_SEL_SC1_PA3_FPOP_WE = 187 +PH_PERF_SEL_SC1_PA3_EOP_WE = 188 +PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 189 +PH_PERF_SEL_SC1_PA3_EOPG_WE = 190 +PH_PERF_SEL_SC1_PA3_DEALLOC_WE = 191 +PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 192 +PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 193 +PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 194 +PH_PERF_SEL_SC1_PA4_FIFO_FULL = 195 +PH_PERF_SEL_SC1_PA4_NULL_WE = 196 +PH_PERF_SEL_SC1_PA4_EVENT_WE = 197 +PH_PERF_SEL_SC1_PA4_FPOV_WE = 198 +PH_PERF_SEL_SC1_PA4_FPOP_WE = 199 +PH_PERF_SEL_SC1_PA4_EOP_WE = 200 +PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 201 +PH_PERF_SEL_SC1_PA4_EOPG_WE = 202 +PH_PERF_SEL_SC1_PA4_DEALLOC_WE = 203 +PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 204 +PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 205 +PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 206 +PH_PERF_SEL_SC1_PA5_FIFO_FULL = 207 +PH_PERF_SEL_SC1_PA5_NULL_WE = 208 +PH_PERF_SEL_SC1_PA5_EVENT_WE = 209 +PH_PERF_SEL_SC1_PA5_FPOV_WE = 210 +PH_PERF_SEL_SC1_PA5_FPOP_WE = 211 +PH_PERF_SEL_SC1_PA5_EOP_WE = 212 +PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 213 +PH_PERF_SEL_SC1_PA5_EOPG_WE = 214 +PH_PERF_SEL_SC1_PA5_DEALLOC_WE = 215 +PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 216 +PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 217 +PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 218 +PH_PERF_SEL_SC1_PA6_FIFO_FULL = 219 +PH_PERF_SEL_SC1_PA6_NULL_WE = 220 +PH_PERF_SEL_SC1_PA6_EVENT_WE = 221 +PH_PERF_SEL_SC1_PA6_FPOV_WE = 222 +PH_PERF_SEL_SC1_PA6_FPOP_WE = 223 +PH_PERF_SEL_SC1_PA6_EOP_WE = 224 +PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 225 +PH_PERF_SEL_SC1_PA6_EOPG_WE = 226 +PH_PERF_SEL_SC1_PA6_DEALLOC_WE = 227 +PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 228 +PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 229 +PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 230 +PH_PERF_SEL_SC1_PA7_FIFO_FULL = 231 +PH_PERF_SEL_SC1_PA7_NULL_WE = 232 +PH_PERF_SEL_SC1_PA7_EVENT_WE = 233 +PH_PERF_SEL_SC1_PA7_FPOV_WE = 234 +PH_PERF_SEL_SC1_PA7_FPOP_WE = 235 +PH_PERF_SEL_SC1_PA7_EOP_WE = 236 +PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 237 +PH_PERF_SEL_SC1_PA7_EOPG_WE = 238 +PH_PERF_SEL_SC1_PA7_DEALLOC_WE = 239 +PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 240 +PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 241 +PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 242 +PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 243 +PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 244 +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 245 +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 246 +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 247 +PH_PERF_SEL_SC2_ARB_BUSY = 248 +PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 249 +PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 250 +PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 251 +PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 252 +PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 253 +PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 254 +PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 255 +PH_PERF_SEL_SC2_SEND = 256 +PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 257 +PH_PERF_SEL_SC2_CREDIT_AT_MAX = 258 +PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 259 +PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 260 +PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 261 +PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 262 +PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 263 +PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 264 +PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 265 +PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 266 +PH_PERF_SEL_SC2_PA0_FIFO_FULL = 267 +PH_PERF_SEL_SC2_PA0_NULL_WE = 268 +PH_PERF_SEL_SC2_PA0_EVENT_WE = 269 +PH_PERF_SEL_SC2_PA0_FPOV_WE = 270 +PH_PERF_SEL_SC2_PA0_FPOP_WE = 271 +PH_PERF_SEL_SC2_PA0_EOP_WE = 272 +PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 273 +PH_PERF_SEL_SC2_PA0_EOPG_WE = 274 +PH_PERF_SEL_SC2_PA0_DEALLOC_WE = 275 +PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 276 +PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 277 +PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 278 +PH_PERF_SEL_SC2_PA1_FIFO_FULL = 279 +PH_PERF_SEL_SC2_PA1_NULL_WE = 280 +PH_PERF_SEL_SC2_PA1_EVENT_WE = 281 +PH_PERF_SEL_SC2_PA1_FPOV_WE = 282 +PH_PERF_SEL_SC2_PA1_FPOP_WE = 283 +PH_PERF_SEL_SC2_PA1_EOP_WE = 284 +PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 285 +PH_PERF_SEL_SC2_PA1_EOPG_WE = 286 +PH_PERF_SEL_SC2_PA1_DEALLOC_WE = 287 +PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 288 +PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 289 +PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 290 +PH_PERF_SEL_SC2_PA2_FIFO_FULL = 291 +PH_PERF_SEL_SC2_PA2_NULL_WE = 292 +PH_PERF_SEL_SC2_PA2_EVENT_WE = 293 +PH_PERF_SEL_SC2_PA2_FPOV_WE = 294 +PH_PERF_SEL_SC2_PA2_FPOP_WE = 295 +PH_PERF_SEL_SC2_PA2_EOP_WE = 296 +PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 297 +PH_PERF_SEL_SC2_PA2_EOPG_WE = 298 +PH_PERF_SEL_SC2_PA2_DEALLOC_WE = 299 +PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 300 +PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 301 +PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 302 +PH_PERF_SEL_SC2_PA3_FIFO_FULL = 303 +PH_PERF_SEL_SC2_PA3_NULL_WE = 304 +PH_PERF_SEL_SC2_PA3_EVENT_WE = 305 +PH_PERF_SEL_SC2_PA3_FPOV_WE = 306 +PH_PERF_SEL_SC2_PA3_FPOP_WE = 307 +PH_PERF_SEL_SC2_PA3_EOP_WE = 308 +PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 309 +PH_PERF_SEL_SC2_PA3_EOPG_WE = 310 +PH_PERF_SEL_SC2_PA3_DEALLOC_WE = 311 +PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 312 +PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 313 +PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 314 +PH_PERF_SEL_SC2_PA4_FIFO_FULL = 315 +PH_PERF_SEL_SC2_PA4_NULL_WE = 316 +PH_PERF_SEL_SC2_PA4_EVENT_WE = 317 +PH_PERF_SEL_SC2_PA4_FPOV_WE = 318 +PH_PERF_SEL_SC2_PA4_FPOP_WE = 319 +PH_PERF_SEL_SC2_PA4_EOP_WE = 320 +PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 321 +PH_PERF_SEL_SC2_PA4_EOPG_WE = 322 +PH_PERF_SEL_SC2_PA4_DEALLOC_WE = 323 +PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 324 +PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 325 +PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 326 +PH_PERF_SEL_SC2_PA5_FIFO_FULL = 327 +PH_PERF_SEL_SC2_PA5_NULL_WE = 328 +PH_PERF_SEL_SC2_PA5_EVENT_WE = 329 +PH_PERF_SEL_SC2_PA5_FPOV_WE = 330 +PH_PERF_SEL_SC2_PA5_FPOP_WE = 331 +PH_PERF_SEL_SC2_PA5_EOP_WE = 332 +PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 333 +PH_PERF_SEL_SC2_PA5_EOPG_WE = 334 +PH_PERF_SEL_SC2_PA5_DEALLOC_WE = 335 +PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 336 +PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 337 +PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 338 +PH_PERF_SEL_SC2_PA6_FIFO_FULL = 339 +PH_PERF_SEL_SC2_PA6_NULL_WE = 340 +PH_PERF_SEL_SC2_PA6_EVENT_WE = 341 +PH_PERF_SEL_SC2_PA6_FPOV_WE = 342 +PH_PERF_SEL_SC2_PA6_FPOP_WE = 343 +PH_PERF_SEL_SC2_PA6_EOP_WE = 344 +PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 345 +PH_PERF_SEL_SC2_PA6_EOPG_WE = 346 +PH_PERF_SEL_SC2_PA6_DEALLOC_WE = 347 +PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 348 +PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 349 +PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 350 +PH_PERF_SEL_SC2_PA7_FIFO_FULL = 351 +PH_PERF_SEL_SC2_PA7_NULL_WE = 352 +PH_PERF_SEL_SC2_PA7_EVENT_WE = 353 +PH_PERF_SEL_SC2_PA7_FPOV_WE = 354 +PH_PERF_SEL_SC2_PA7_FPOP_WE = 355 +PH_PERF_SEL_SC2_PA7_EOP_WE = 356 +PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 357 +PH_PERF_SEL_SC2_PA7_EOPG_WE = 358 +PH_PERF_SEL_SC2_PA7_DEALLOC_WE = 359 +PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 360 +PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 361 +PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 362 +PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 363 +PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 364 +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 365 +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 366 +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 367 +PH_PERF_SEL_SC3_ARB_BUSY = 368 +PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 369 +PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 370 +PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 371 +PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 372 +PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 373 +PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 374 +PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 375 +PH_PERF_SEL_SC3_SEND = 376 +PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 377 +PH_PERF_SEL_SC3_CREDIT_AT_MAX = 378 +PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 379 +PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 380 +PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 381 +PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 382 +PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 383 +PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 384 +PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 385 +PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 386 +PH_PERF_SEL_SC3_PA0_FIFO_FULL = 387 +PH_PERF_SEL_SC3_PA0_NULL_WE = 388 +PH_PERF_SEL_SC3_PA0_EVENT_WE = 389 +PH_PERF_SEL_SC3_PA0_FPOV_WE = 390 +PH_PERF_SEL_SC3_PA0_FPOP_WE = 391 +PH_PERF_SEL_SC3_PA0_EOP_WE = 392 +PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 393 +PH_PERF_SEL_SC3_PA0_EOPG_WE = 394 +PH_PERF_SEL_SC3_PA0_DEALLOC_WE = 395 +PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 396 +PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 397 +PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 398 +PH_PERF_SEL_SC3_PA1_FIFO_FULL = 399 +PH_PERF_SEL_SC3_PA1_NULL_WE = 400 +PH_PERF_SEL_SC3_PA1_EVENT_WE = 401 +PH_PERF_SEL_SC3_PA1_FPOV_WE = 402 +PH_PERF_SEL_SC3_PA1_FPOP_WE = 403 +PH_PERF_SEL_SC3_PA1_EOP_WE = 404 +PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 405 +PH_PERF_SEL_SC3_PA1_EOPG_WE = 406 +PH_PERF_SEL_SC3_PA1_DEALLOC_WE = 407 +PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 408 +PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 409 +PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 410 +PH_PERF_SEL_SC3_PA2_FIFO_FULL = 411 +PH_PERF_SEL_SC3_PA2_NULL_WE = 412 +PH_PERF_SEL_SC3_PA2_EVENT_WE = 413 +PH_PERF_SEL_SC3_PA2_FPOV_WE = 414 +PH_PERF_SEL_SC3_PA2_FPOP_WE = 415 +PH_PERF_SEL_SC3_PA2_EOP_WE = 416 +PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 417 +PH_PERF_SEL_SC3_PA2_EOPG_WE = 418 +PH_PERF_SEL_SC3_PA2_DEALLOC_WE = 419 +PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 420 +PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 421 +PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 422 +PH_PERF_SEL_SC3_PA3_FIFO_FULL = 423 +PH_PERF_SEL_SC3_PA3_NULL_WE = 424 +PH_PERF_SEL_SC3_PA3_EVENT_WE = 425 +PH_PERF_SEL_SC3_PA3_FPOV_WE = 426 +PH_PERF_SEL_SC3_PA3_FPOP_WE = 427 +PH_PERF_SEL_SC3_PA3_EOP_WE = 428 +PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 429 +PH_PERF_SEL_SC3_PA3_EOPG_WE = 430 +PH_PERF_SEL_SC3_PA3_DEALLOC_WE = 431 +PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 432 +PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 433 +PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 434 +PH_PERF_SEL_SC3_PA4_FIFO_FULL = 435 +PH_PERF_SEL_SC3_PA4_NULL_WE = 436 +PH_PERF_SEL_SC3_PA4_EVENT_WE = 437 +PH_PERF_SEL_SC3_PA4_FPOV_WE = 438 +PH_PERF_SEL_SC3_PA4_FPOP_WE = 439 +PH_PERF_SEL_SC3_PA4_EOP_WE = 440 +PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 441 +PH_PERF_SEL_SC3_PA4_EOPG_WE = 442 +PH_PERF_SEL_SC3_PA4_DEALLOC_WE = 443 +PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 444 +PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 445 +PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 446 +PH_PERF_SEL_SC3_PA5_FIFO_FULL = 447 +PH_PERF_SEL_SC3_PA5_NULL_WE = 448 +PH_PERF_SEL_SC3_PA5_EVENT_WE = 449 +PH_PERF_SEL_SC3_PA5_FPOV_WE = 450 +PH_PERF_SEL_SC3_PA5_FPOP_WE = 451 +PH_PERF_SEL_SC3_PA5_EOP_WE = 452 +PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 453 +PH_PERF_SEL_SC3_PA5_EOPG_WE = 454 +PH_PERF_SEL_SC3_PA5_DEALLOC_WE = 455 +PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 456 +PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 457 +PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 458 +PH_PERF_SEL_SC3_PA6_FIFO_FULL = 459 +PH_PERF_SEL_SC3_PA6_NULL_WE = 460 +PH_PERF_SEL_SC3_PA6_EVENT_WE = 461 +PH_PERF_SEL_SC3_PA6_FPOV_WE = 462 +PH_PERF_SEL_SC3_PA6_FPOP_WE = 463 +PH_PERF_SEL_SC3_PA6_EOP_WE = 464 +PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 465 +PH_PERF_SEL_SC3_PA6_EOPG_WE = 466 +PH_PERF_SEL_SC3_PA6_DEALLOC_WE = 467 +PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 468 +PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 469 +PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 470 +PH_PERF_SEL_SC3_PA7_FIFO_FULL = 471 +PH_PERF_SEL_SC3_PA7_NULL_WE = 472 +PH_PERF_SEL_SC3_PA7_EVENT_WE = 473 +PH_PERF_SEL_SC3_PA7_FPOV_WE = 474 +PH_PERF_SEL_SC3_PA7_FPOP_WE = 475 +PH_PERF_SEL_SC3_PA7_EOP_WE = 476 +PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 477 +PH_PERF_SEL_SC3_PA7_EOPG_WE = 478 +PH_PERF_SEL_SC3_PA7_DEALLOC_WE = 479 +PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 480 +PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 481 +PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 482 +PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 483 +PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 484 +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 485 +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 486 +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 487 +PH_PERF_SEL_SC4_ARB_BUSY = 488 +PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 489 +PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 490 +PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 491 +PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 492 +PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 493 +PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 494 +PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 495 +PH_PERF_SEL_SC4_SEND = 496 +PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 497 +PH_PERF_SEL_SC4_CREDIT_AT_MAX = 498 +PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 499 +PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 500 +PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 501 +PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 502 +PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 503 +PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 504 +PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 505 +PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 506 +PH_PERF_SEL_SC4_PA0_FIFO_FULL = 507 +PH_PERF_SEL_SC4_PA0_NULL_WE = 508 +PH_PERF_SEL_SC4_PA0_EVENT_WE = 509 +PH_PERF_SEL_SC4_PA0_FPOV_WE = 510 +PH_PERF_SEL_SC4_PA0_FPOP_WE = 511 +PH_PERF_SEL_SC4_PA0_EOP_WE = 512 +PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 513 +PH_PERF_SEL_SC4_PA0_EOPG_WE = 514 +PH_PERF_SEL_SC4_PA0_DEALLOC_WE = 515 +PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 516 +PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 517 +PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 518 +PH_PERF_SEL_SC4_PA1_FIFO_FULL = 519 +PH_PERF_SEL_SC4_PA1_NULL_WE = 520 +PH_PERF_SEL_SC4_PA1_EVENT_WE = 521 +PH_PERF_SEL_SC4_PA1_FPOV_WE = 522 +PH_PERF_SEL_SC4_PA1_FPOP_WE = 523 +PH_PERF_SEL_SC4_PA1_EOP_WE = 524 +PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 525 +PH_PERF_SEL_SC4_PA1_EOPG_WE = 526 +PH_PERF_SEL_SC4_PA1_DEALLOC_WE = 527 +PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 528 +PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 529 +PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 530 +PH_PERF_SEL_SC4_PA2_FIFO_FULL = 531 +PH_PERF_SEL_SC4_PA2_NULL_WE = 532 +PH_PERF_SEL_SC4_PA2_EVENT_WE = 533 +PH_PERF_SEL_SC4_PA2_FPOV_WE = 534 +PH_PERF_SEL_SC4_PA2_FPOP_WE = 535 +PH_PERF_SEL_SC4_PA2_EOP_WE = 536 +PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 537 +PH_PERF_SEL_SC4_PA2_EOPG_WE = 538 +PH_PERF_SEL_SC4_PA2_DEALLOC_WE = 539 +PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 540 +PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 541 +PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 542 +PH_PERF_SEL_SC4_PA3_FIFO_FULL = 543 +PH_PERF_SEL_SC4_PA3_NULL_WE = 544 +PH_PERF_SEL_SC4_PA3_EVENT_WE = 545 +PH_PERF_SEL_SC4_PA3_FPOV_WE = 546 +PH_PERF_SEL_SC4_PA3_FPOP_WE = 547 +PH_PERF_SEL_SC4_PA3_EOP_WE = 548 +PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 549 +PH_PERF_SEL_SC4_PA3_EOPG_WE = 550 +PH_PERF_SEL_SC4_PA3_DEALLOC_WE = 551 +PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 552 +PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 553 +PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 554 +PH_PERF_SEL_SC4_PA4_FIFO_FULL = 555 +PH_PERF_SEL_SC4_PA4_NULL_WE = 556 +PH_PERF_SEL_SC4_PA4_EVENT_WE = 557 +PH_PERF_SEL_SC4_PA4_FPOV_WE = 558 +PH_PERF_SEL_SC4_PA4_FPOP_WE = 559 +PH_PERF_SEL_SC4_PA4_EOP_WE = 560 +PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 561 +PH_PERF_SEL_SC4_PA4_EOPG_WE = 562 +PH_PERF_SEL_SC4_PA4_DEALLOC_WE = 563 +PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 564 +PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 565 +PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 566 +PH_PERF_SEL_SC4_PA5_FIFO_FULL = 567 +PH_PERF_SEL_SC4_PA5_NULL_WE = 568 +PH_PERF_SEL_SC4_PA5_EVENT_WE = 569 +PH_PERF_SEL_SC4_PA5_FPOV_WE = 570 +PH_PERF_SEL_SC4_PA5_FPOP_WE = 571 +PH_PERF_SEL_SC4_PA5_EOP_WE = 572 +PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 573 +PH_PERF_SEL_SC4_PA5_EOPG_WE = 574 +PH_PERF_SEL_SC4_PA5_DEALLOC_WE = 575 +PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 576 +PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 577 +PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 578 +PH_PERF_SEL_SC4_PA6_FIFO_FULL = 579 +PH_PERF_SEL_SC4_PA6_NULL_WE = 580 +PH_PERF_SEL_SC4_PA6_EVENT_WE = 581 +PH_PERF_SEL_SC4_PA6_FPOV_WE = 582 +PH_PERF_SEL_SC4_PA6_FPOP_WE = 583 +PH_PERF_SEL_SC4_PA6_EOP_WE = 584 +PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 585 +PH_PERF_SEL_SC4_PA6_EOPG_WE = 586 +PH_PERF_SEL_SC4_PA6_DEALLOC_WE = 587 +PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 588 +PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 589 +PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 590 +PH_PERF_SEL_SC4_PA7_FIFO_FULL = 591 +PH_PERF_SEL_SC4_PA7_NULL_WE = 592 +PH_PERF_SEL_SC4_PA7_EVENT_WE = 593 +PH_PERF_SEL_SC4_PA7_FPOV_WE = 594 +PH_PERF_SEL_SC4_PA7_FPOP_WE = 595 +PH_PERF_SEL_SC4_PA7_EOP_WE = 596 +PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 597 +PH_PERF_SEL_SC4_PA7_EOPG_WE = 598 +PH_PERF_SEL_SC4_PA7_DEALLOC_WE = 599 +PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 600 +PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 601 +PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 602 +PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 603 +PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 604 +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 605 +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 606 +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 607 +PH_PERF_SEL_SC5_ARB_BUSY = 608 +PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 609 +PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 610 +PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 611 +PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 612 +PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 613 +PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 614 +PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 615 +PH_PERF_SEL_SC5_SEND = 616 +PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 617 +PH_PERF_SEL_SC5_CREDIT_AT_MAX = 618 +PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 619 +PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 620 +PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 621 +PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 622 +PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 623 +PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 624 +PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 625 +PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 626 +PH_PERF_SEL_SC5_PA0_FIFO_FULL = 627 +PH_PERF_SEL_SC5_PA0_NULL_WE = 628 +PH_PERF_SEL_SC5_PA0_EVENT_WE = 629 +PH_PERF_SEL_SC5_PA0_FPOV_WE = 630 +PH_PERF_SEL_SC5_PA0_FPOP_WE = 631 +PH_PERF_SEL_SC5_PA0_EOP_WE = 632 +PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 633 +PH_PERF_SEL_SC5_PA0_EOPG_WE = 634 +PH_PERF_SEL_SC5_PA0_DEALLOC_WE = 635 +PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 636 +PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 637 +PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 638 +PH_PERF_SEL_SC5_PA1_FIFO_FULL = 639 +PH_PERF_SEL_SC5_PA1_NULL_WE = 640 +PH_PERF_SEL_SC5_PA1_EVENT_WE = 641 +PH_PERF_SEL_SC5_PA1_FPOV_WE = 642 +PH_PERF_SEL_SC5_PA1_FPOP_WE = 643 +PH_PERF_SEL_SC5_PA1_EOP_WE = 644 +PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 645 +PH_PERF_SEL_SC5_PA1_EOPG_WE = 646 +PH_PERF_SEL_SC5_PA1_DEALLOC_WE = 647 +PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 648 +PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 649 +PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 650 +PH_PERF_SEL_SC5_PA2_FIFO_FULL = 651 +PH_PERF_SEL_SC5_PA2_NULL_WE = 652 +PH_PERF_SEL_SC5_PA2_EVENT_WE = 653 +PH_PERF_SEL_SC5_PA2_FPOV_WE = 654 +PH_PERF_SEL_SC5_PA2_FPOP_WE = 655 +PH_PERF_SEL_SC5_PA2_EOP_WE = 656 +PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 657 +PH_PERF_SEL_SC5_PA2_EOPG_WE = 658 +PH_PERF_SEL_SC5_PA2_DEALLOC_WE = 659 +PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 660 +PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 661 +PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 662 +PH_PERF_SEL_SC5_PA3_FIFO_FULL = 663 +PH_PERF_SEL_SC5_PA3_NULL_WE = 664 +PH_PERF_SEL_SC5_PA3_EVENT_WE = 665 +PH_PERF_SEL_SC5_PA3_FPOV_WE = 666 +PH_PERF_SEL_SC5_PA3_FPOP_WE = 667 +PH_PERF_SEL_SC5_PA3_EOP_WE = 668 +PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 669 +PH_PERF_SEL_SC5_PA3_EOPG_WE = 670 +PH_PERF_SEL_SC5_PA3_DEALLOC_WE = 671 +PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 672 +PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 673 +PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 674 +PH_PERF_SEL_SC5_PA4_FIFO_FULL = 675 +PH_PERF_SEL_SC5_PA4_NULL_WE = 676 +PH_PERF_SEL_SC5_PA4_EVENT_WE = 677 +PH_PERF_SEL_SC5_PA4_FPOV_WE = 678 +PH_PERF_SEL_SC5_PA4_FPOP_WE = 679 +PH_PERF_SEL_SC5_PA4_EOP_WE = 680 +PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 681 +PH_PERF_SEL_SC5_PA4_EOPG_WE = 682 +PH_PERF_SEL_SC5_PA4_DEALLOC_WE = 683 +PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 684 +PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 685 +PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 686 +PH_PERF_SEL_SC5_PA5_FIFO_FULL = 687 +PH_PERF_SEL_SC5_PA5_NULL_WE = 688 +PH_PERF_SEL_SC5_PA5_EVENT_WE = 689 +PH_PERF_SEL_SC5_PA5_FPOV_WE = 690 +PH_PERF_SEL_SC5_PA5_FPOP_WE = 691 +PH_PERF_SEL_SC5_PA5_EOP_WE = 692 +PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 693 +PH_PERF_SEL_SC5_PA5_EOPG_WE = 694 +PH_PERF_SEL_SC5_PA5_DEALLOC_WE = 695 +PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 696 +PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 697 +PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 698 +PH_PERF_SEL_SC5_PA6_FIFO_FULL = 699 +PH_PERF_SEL_SC5_PA6_NULL_WE = 700 +PH_PERF_SEL_SC5_PA6_EVENT_WE = 701 +PH_PERF_SEL_SC5_PA6_FPOV_WE = 702 +PH_PERF_SEL_SC5_PA6_FPOP_WE = 703 +PH_PERF_SEL_SC5_PA6_EOP_WE = 704 +PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 705 +PH_PERF_SEL_SC5_PA6_EOPG_WE = 706 +PH_PERF_SEL_SC5_PA6_DEALLOC_WE = 707 +PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 708 +PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 709 +PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 710 +PH_PERF_SEL_SC5_PA7_FIFO_FULL = 711 +PH_PERF_SEL_SC5_PA7_NULL_WE = 712 +PH_PERF_SEL_SC5_PA7_EVENT_WE = 713 +PH_PERF_SEL_SC5_PA7_FPOV_WE = 714 +PH_PERF_SEL_SC5_PA7_FPOP_WE = 715 +PH_PERF_SEL_SC5_PA7_EOP_WE = 716 +PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 717 +PH_PERF_SEL_SC5_PA7_EOPG_WE = 718 +PH_PERF_SEL_SC5_PA7_DEALLOC_WE = 719 +PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 720 +PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 721 +PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 722 +PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 723 +PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 724 +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 725 +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 726 +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 727 +PH_PERF_SEL_SC6_ARB_BUSY = 728 +PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 729 +PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 730 +PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 731 +PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 732 +PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 733 +PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 734 +PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 735 +PH_PERF_SEL_SC6_SEND = 736 +PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 737 +PH_PERF_SEL_SC6_CREDIT_AT_MAX = 738 +PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 739 +PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 740 +PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 741 +PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 742 +PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 743 +PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 744 +PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 745 +PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 746 +PH_PERF_SEL_SC6_PA0_FIFO_FULL = 747 +PH_PERF_SEL_SC6_PA0_NULL_WE = 748 +PH_PERF_SEL_SC6_PA0_EVENT_WE = 749 +PH_PERF_SEL_SC6_PA0_FPOV_WE = 750 +PH_PERF_SEL_SC6_PA0_FPOP_WE = 751 +PH_PERF_SEL_SC6_PA0_EOP_WE = 752 +PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 753 +PH_PERF_SEL_SC6_PA0_EOPG_WE = 754 +PH_PERF_SEL_SC6_PA0_DEALLOC_WE = 755 +PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 756 +PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 757 +PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 758 +PH_PERF_SEL_SC6_PA1_FIFO_FULL = 759 +PH_PERF_SEL_SC6_PA1_NULL_WE = 760 +PH_PERF_SEL_SC6_PA1_EVENT_WE = 761 +PH_PERF_SEL_SC6_PA1_FPOV_WE = 762 +PH_PERF_SEL_SC6_PA1_FPOP_WE = 763 +PH_PERF_SEL_SC6_PA1_EOP_WE = 764 +PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 765 +PH_PERF_SEL_SC6_PA1_EOPG_WE = 766 +PH_PERF_SEL_SC6_PA1_DEALLOC_WE = 767 +PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 768 +PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 769 +PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 770 +PH_PERF_SEL_SC6_PA2_FIFO_FULL = 771 +PH_PERF_SEL_SC6_PA2_NULL_WE = 772 +PH_PERF_SEL_SC6_PA2_EVENT_WE = 773 +PH_PERF_SEL_SC6_PA2_FPOV_WE = 774 +PH_PERF_SEL_SC6_PA2_FPOP_WE = 775 +PH_PERF_SEL_SC6_PA2_EOP_WE = 776 +PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 777 +PH_PERF_SEL_SC6_PA2_EOPG_WE = 778 +PH_PERF_SEL_SC6_PA2_DEALLOC_WE = 779 +PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 780 +PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 781 +PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 782 +PH_PERF_SEL_SC6_PA3_FIFO_FULL = 783 +PH_PERF_SEL_SC6_PA3_NULL_WE = 784 +PH_PERF_SEL_SC6_PA3_EVENT_WE = 785 +PH_PERF_SEL_SC6_PA3_FPOV_WE = 786 +PH_PERF_SEL_SC6_PA3_FPOP_WE = 787 +PH_PERF_SEL_SC6_PA3_EOP_WE = 788 +PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 789 +PH_PERF_SEL_SC6_PA3_EOPG_WE = 790 +PH_PERF_SEL_SC6_PA3_DEALLOC_WE = 791 +PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 792 +PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 793 +PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 794 +PH_PERF_SEL_SC6_PA4_FIFO_FULL = 795 +PH_PERF_SEL_SC6_PA4_NULL_WE = 796 +PH_PERF_SEL_SC6_PA4_EVENT_WE = 797 +PH_PERF_SEL_SC6_PA4_FPOV_WE = 798 +PH_PERF_SEL_SC6_PA4_FPOP_WE = 799 +PH_PERF_SEL_SC6_PA4_EOP_WE = 800 +PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 801 +PH_PERF_SEL_SC6_PA4_EOPG_WE = 802 +PH_PERF_SEL_SC6_PA4_DEALLOC_WE = 803 +PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 804 +PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 805 +PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 806 +PH_PERF_SEL_SC6_PA5_FIFO_FULL = 807 +PH_PERF_SEL_SC6_PA5_NULL_WE = 808 +PH_PERF_SEL_SC6_PA5_EVENT_WE = 809 +PH_PERF_SEL_SC6_PA5_FPOV_WE = 810 +PH_PERF_SEL_SC6_PA5_FPOP_WE = 811 +PH_PERF_SEL_SC6_PA5_EOP_WE = 812 +PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 813 +PH_PERF_SEL_SC6_PA5_EOPG_WE = 814 +PH_PERF_SEL_SC6_PA5_DEALLOC_WE = 815 +PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 816 +PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 817 +PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 818 +PH_PERF_SEL_SC6_PA6_FIFO_FULL = 819 +PH_PERF_SEL_SC6_PA6_NULL_WE = 820 +PH_PERF_SEL_SC6_PA6_EVENT_WE = 821 +PH_PERF_SEL_SC6_PA6_FPOV_WE = 822 +PH_PERF_SEL_SC6_PA6_FPOP_WE = 823 +PH_PERF_SEL_SC6_PA6_EOP_WE = 824 +PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 825 +PH_PERF_SEL_SC6_PA6_EOPG_WE = 826 +PH_PERF_SEL_SC6_PA6_DEALLOC_WE = 827 +PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 828 +PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 829 +PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 830 +PH_PERF_SEL_SC6_PA7_FIFO_FULL = 831 +PH_PERF_SEL_SC6_PA7_NULL_WE = 832 +PH_PERF_SEL_SC6_PA7_EVENT_WE = 833 +PH_PERF_SEL_SC6_PA7_FPOV_WE = 834 +PH_PERF_SEL_SC6_PA7_FPOP_WE = 835 +PH_PERF_SEL_SC6_PA7_EOP_WE = 836 +PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 837 +PH_PERF_SEL_SC6_PA7_EOPG_WE = 838 +PH_PERF_SEL_SC6_PA7_DEALLOC_WE = 839 +PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 840 +PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 841 +PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 842 +PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 843 +PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 844 +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 845 +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 846 +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 847 +PH_PERF_SEL_SC7_ARB_BUSY = 848 +PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 849 +PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 850 +PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 851 +PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 852 +PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 853 +PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 854 +PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 855 +PH_PERF_SEL_SC7_SEND = 856 +PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 857 +PH_PERF_SEL_SC7_CREDIT_AT_MAX = 858 +PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 859 +PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 860 +PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 861 +PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 862 +PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 863 +PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 864 +PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 865 +PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 866 +PH_PERF_SEL_SC7_PA0_FIFO_FULL = 867 +PH_PERF_SEL_SC7_PA0_NULL_WE = 868 +PH_PERF_SEL_SC7_PA0_EVENT_WE = 869 +PH_PERF_SEL_SC7_PA0_FPOV_WE = 870 +PH_PERF_SEL_SC7_PA0_FPOP_WE = 871 +PH_PERF_SEL_SC7_PA0_EOP_WE = 872 +PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 873 +PH_PERF_SEL_SC7_PA0_EOPG_WE = 874 +PH_PERF_SEL_SC7_PA0_DEALLOC_WE = 875 +PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 876 +PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 877 +PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 878 +PH_PERF_SEL_SC7_PA1_FIFO_FULL = 879 +PH_PERF_SEL_SC7_PA1_NULL_WE = 880 +PH_PERF_SEL_SC7_PA1_EVENT_WE = 881 +PH_PERF_SEL_SC7_PA1_FPOV_WE = 882 +PH_PERF_SEL_SC7_PA1_FPOP_WE = 883 +PH_PERF_SEL_SC7_PA1_EOP_WE = 884 +PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 885 +PH_PERF_SEL_SC7_PA1_EOPG_WE = 886 +PH_PERF_SEL_SC7_PA1_DEALLOC_WE = 887 +PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 888 +PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 889 +PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 890 +PH_PERF_SEL_SC7_PA2_FIFO_FULL = 891 +PH_PERF_SEL_SC7_PA2_NULL_WE = 892 +PH_PERF_SEL_SC7_PA2_EVENT_WE = 893 +PH_PERF_SEL_SC7_PA2_FPOV_WE = 894 +PH_PERF_SEL_SC7_PA2_FPOP_WE = 895 +PH_PERF_SEL_SC7_PA2_EOP_WE = 896 +PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 897 +PH_PERF_SEL_SC7_PA2_EOPG_WE = 898 +PH_PERF_SEL_SC7_PA2_DEALLOC_WE = 899 +PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 900 +PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 901 +PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 902 +PH_PERF_SEL_SC7_PA3_FIFO_FULL = 903 +PH_PERF_SEL_SC7_PA3_NULL_WE = 904 +PH_PERF_SEL_SC7_PA3_EVENT_WE = 905 +PH_PERF_SEL_SC7_PA3_FPOV_WE = 906 +PH_PERF_SEL_SC7_PA3_FPOP_WE = 907 +PH_PERF_SEL_SC7_PA3_EOP_WE = 908 +PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 909 +PH_PERF_SEL_SC7_PA3_EOPG_WE = 910 +PH_PERF_SEL_SC7_PA3_DEALLOC_WE = 911 +PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 912 +PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 913 +PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 914 +PH_PERF_SEL_SC7_PA4_FIFO_FULL = 915 +PH_PERF_SEL_SC7_PA4_NULL_WE = 916 +PH_PERF_SEL_SC7_PA4_EVENT_WE = 917 +PH_PERF_SEL_SC7_PA4_FPOV_WE = 918 +PH_PERF_SEL_SC7_PA4_FPOP_WE = 919 +PH_PERF_SEL_SC7_PA4_EOP_WE = 920 +PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 921 +PH_PERF_SEL_SC7_PA4_EOPG_WE = 922 +PH_PERF_SEL_SC7_PA4_DEALLOC_WE = 923 +PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 924 +PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 925 +PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 926 +PH_PERF_SEL_SC7_PA5_FIFO_FULL = 927 +PH_PERF_SEL_SC7_PA5_NULL_WE = 928 +PH_PERF_SEL_SC7_PA5_EVENT_WE = 929 +PH_PERF_SEL_SC7_PA5_FPOV_WE = 930 +PH_PERF_SEL_SC7_PA5_FPOP_WE = 931 +PH_PERF_SEL_SC7_PA5_EOP_WE = 932 +PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 933 +PH_PERF_SEL_SC7_PA5_EOPG_WE = 934 +PH_PERF_SEL_SC7_PA5_DEALLOC_WE = 935 +PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 936 +PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 937 +PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 938 +PH_PERF_SEL_SC7_PA6_FIFO_FULL = 939 +PH_PERF_SEL_SC7_PA6_NULL_WE = 940 +PH_PERF_SEL_SC7_PA6_EVENT_WE = 941 +PH_PERF_SEL_SC7_PA6_FPOV_WE = 942 +PH_PERF_SEL_SC7_PA6_FPOP_WE = 943 +PH_PERF_SEL_SC7_PA6_EOP_WE = 944 +PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 945 +PH_PERF_SEL_SC7_PA6_EOPG_WE = 946 +PH_PERF_SEL_SC7_PA6_DEALLOC_WE = 947 +PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 948 +PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 949 +PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 950 +PH_PERF_SEL_SC7_PA7_FIFO_FULL = 951 +PH_PERF_SEL_SC7_PA7_NULL_WE = 952 +PH_PERF_SEL_SC7_PA7_EVENT_WE = 953 +PH_PERF_SEL_SC7_PA7_FPOV_WE = 954 +PH_PERF_SEL_SC7_PA7_FPOP_WE = 955 +PH_PERF_SEL_SC7_PA7_EOP_WE = 956 +PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 957 +PH_PERF_SEL_SC7_PA7_EOPG_WE = 958 +PH_PERF_SEL_SC7_PA7_DEALLOC_WE = 959 +PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 960 +PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 961 +PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 962 +PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 963 +PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 964 +PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 965 +PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 966 +PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 967 +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 968 +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 969 +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 970 +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 971 +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 972 +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 973 +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 974 +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 975 +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 976 +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 977 +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 978 +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 979 +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 980 +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 981 +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 982 +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 983 +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 984 +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 985 +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 986 +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 987 +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 988 +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 989 +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 990 +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 991 +PH_PERF_SC0_FIFO_STATUS_0 = 992 +PH_PERF_SC0_FIFO_STATUS_1 = 993 +PH_PERF_SC0_FIFO_STATUS_2 = 994 +PH_PERF_SC0_FIFO_STATUS_3 = 995 +PH_PERF_SC1_FIFO_STATUS_0 = 996 +PH_PERF_SC1_FIFO_STATUS_1 = 997 +PH_PERF_SC1_FIFO_STATUS_2 = 998 +PH_PERF_SC1_FIFO_STATUS_3 = 999 +PH_PERF_SC2_FIFO_STATUS_0 = 1000 +PH_PERF_SC2_FIFO_STATUS_1 = 1001 +PH_PERF_SC2_FIFO_STATUS_2 = 1002 +PH_PERF_SC2_FIFO_STATUS_3 = 1003 +PH_PERF_SC3_FIFO_STATUS_0 = 1004 +PH_PERF_SC3_FIFO_STATUS_1 = 1005 +PH_PERF_SC3_FIFO_STATUS_2 = 1006 +PH_PERF_SC3_FIFO_STATUS_3 = 1007 +PH_PERF_SC4_FIFO_STATUS_0 = 1008 +PH_PERF_SC4_FIFO_STATUS_1 = 1009 +PH_PERF_SC4_FIFO_STATUS_2 = 1010 +PH_PERF_SC4_FIFO_STATUS_3 = 1011 +PH_PERF_SC5_FIFO_STATUS_0 = 1012 +PH_PERF_SC5_FIFO_STATUS_1 = 1013 +PH_PERF_SC5_FIFO_STATUS_2 = 1014 +PH_PERF_SC5_FIFO_STATUS_3 = 1015 +PH_PERF_SC6_FIFO_STATUS_0 = 1016 +PH_PERF_SC6_FIFO_STATUS_1 = 1017 +PH_PERF_SC6_FIFO_STATUS_2 = 1018 +PH_PERF_SC6_FIFO_STATUS_3 = 1019 +PH_PERF_SC7_FIFO_STATUS_0 = 1020 +PH_PERF_SC7_FIFO_STATUS_1 = 1021 +PH_PERF_SC7_FIFO_STATUS_2 = 1022 +PH_PERF_SC7_FIFO_STATUS_3 = 1023 +PH_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PhSPIstatusMode' +PhSPIstatusMode__enumvalues = { + 0: 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', + 1: 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', + 2: 'PH_SPI_MODE_DISABLED', +} +PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0 +PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 1 +PH_SPI_MODE_DISABLED = 2 +PhSPIstatusMode = ctypes.c_uint32 # enum + +# values for enumeration 'BinEventCntl' +BinEventCntl__enumvalues = { + 0: 'BINNER_BREAK_BATCH', + 1: 'BINNER_PIPELINE', + 2: 'BINNER_DROP', + 3: 'BINNER_PIPELINE_BREAK', +} +BINNER_BREAK_BATCH = 0 +BINNER_PIPELINE = 1 +BINNER_DROP = 2 +BINNER_PIPELINE_BREAK = 3 +BinEventCntl = ctypes.c_uint32 # enum + +# values for enumeration 'BinMapMode' +BinMapMode__enumvalues = { + 0: 'BIN_MAP_MODE_NONE', + 1: 'BIN_MAP_MODE_RTA_INDEX', + 2: 'BIN_MAP_MODE_POPS', +} +BIN_MAP_MODE_NONE = 0 +BIN_MAP_MODE_RTA_INDEX = 1 +BIN_MAP_MODE_POPS = 2 +BinMapMode = ctypes.c_uint32 # enum + +# values for enumeration 'BinSizeExtend' +BinSizeExtend__enumvalues = { + 0: 'BIN_SIZE_32_PIXELS', + 1: 'BIN_SIZE_64_PIXELS', + 2: 'BIN_SIZE_128_PIXELS', + 3: 'BIN_SIZE_256_PIXELS', + 4: 'BIN_SIZE_512_PIXELS', +} +BIN_SIZE_32_PIXELS = 0 +BIN_SIZE_64_PIXELS = 1 +BIN_SIZE_128_PIXELS = 2 +BIN_SIZE_256_PIXELS = 3 +BIN_SIZE_512_PIXELS = 4 +BinSizeExtend = ctypes.c_uint32 # enum + +# values for enumeration 'BinningMode' +BinningMode__enumvalues = { + 0: 'BINNING_ALLOWED', + 1: 'FORCE_BINNING_ON', + 2: 'BINNING_ONE_PRIM_PER_BATCH', + 3: 'BINNING_DISABLED', +} +BINNING_ALLOWED = 0 +FORCE_BINNING_ON = 1 +BINNING_ONE_PRIM_PER_BATCH = 2 +BINNING_DISABLED = 3 +BinningMode = ctypes.c_uint32 # enum + +# values for enumeration 'PkrMap' +PkrMap__enumvalues = { + 0: 'RASTER_CONFIG_PKR_MAP_0', + 1: 'RASTER_CONFIG_PKR_MAP_1', + 2: 'RASTER_CONFIG_PKR_MAP_2', + 3: 'RASTER_CONFIG_PKR_MAP_3', +} +RASTER_CONFIG_PKR_MAP_0 = 0 +RASTER_CONFIG_PKR_MAP_1 = 1 +RASTER_CONFIG_PKR_MAP_2 = 2 +RASTER_CONFIG_PKR_MAP_3 = 3 +PkrMap = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel' +PkrXsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL_0', + 1: 'RASTER_CONFIG_PKR_XSEL_1', + 2: 'RASTER_CONFIG_PKR_XSEL_2', + 3: 'RASTER_CONFIG_PKR_XSEL_3', +} +RASTER_CONFIG_PKR_XSEL_0 = 0 +RASTER_CONFIG_PKR_XSEL_1 = 1 +RASTER_CONFIG_PKR_XSEL_2 = 2 +RASTER_CONFIG_PKR_XSEL_3 = 3 +PkrXsel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel2' +PkrXsel2__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL2_0', + 1: 'RASTER_CONFIG_PKR_XSEL2_1', + 2: 'RASTER_CONFIG_PKR_XSEL2_2', + 3: 'RASTER_CONFIG_PKR_XSEL2_3', +} +RASTER_CONFIG_PKR_XSEL2_0 = 0 +RASTER_CONFIG_PKR_XSEL2_1 = 1 +RASTER_CONFIG_PKR_XSEL2_2 = 2 +RASTER_CONFIG_PKR_XSEL2_3 = 3 +PkrXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'PkrYsel' +PkrYsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_YSEL_0', + 1: 'RASTER_CONFIG_PKR_YSEL_1', + 2: 'RASTER_CONFIG_PKR_YSEL_2', + 3: 'RASTER_CONFIG_PKR_YSEL_3', +} +RASTER_CONFIG_PKR_YSEL_0 = 0 +RASTER_CONFIG_PKR_YSEL_1 = 1 +RASTER_CONFIG_PKR_YSEL_2 = 2 +RASTER_CONFIG_PKR_YSEL_3 = 3 +PkrYsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbMap' +RbMap__enumvalues = { + 0: 'RASTER_CONFIG_RB_MAP_0', + 1: 'RASTER_CONFIG_RB_MAP_1', + 2: 'RASTER_CONFIG_RB_MAP_2', + 3: 'RASTER_CONFIG_RB_MAP_3', +} +RASTER_CONFIG_RB_MAP_0 = 0 +RASTER_CONFIG_RB_MAP_1 = 1 +RASTER_CONFIG_RB_MAP_2 = 2 +RASTER_CONFIG_RB_MAP_3 = 3 +RbMap = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel' +RbXsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL_0', + 1: 'RASTER_CONFIG_RB_XSEL_1', +} +RASTER_CONFIG_RB_XSEL_0 = 0 +RASTER_CONFIG_RB_XSEL_1 = 1 +RbXsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel2' +RbXsel2__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL2_0', + 1: 'RASTER_CONFIG_RB_XSEL2_1', + 2: 'RASTER_CONFIG_RB_XSEL2_2', + 3: 'RASTER_CONFIG_RB_XSEL2_3', +} +RASTER_CONFIG_RB_XSEL2_0 = 0 +RASTER_CONFIG_RB_XSEL2_1 = 1 +RASTER_CONFIG_RB_XSEL2_2 = 2 +RASTER_CONFIG_RB_XSEL2_3 = 3 +RbXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'RbYsel' +RbYsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_YSEL_0', + 1: 'RASTER_CONFIG_RB_YSEL_1', +} +RASTER_CONFIG_RB_YSEL_0 = 0 +RASTER_CONFIG_RB_YSEL_1 = 1 +RbYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SC_PERFCNT_SEL' +SC_PERFCNT_SEL__enumvalues = { + 0: 'SC_SRPS_WINDOW_VALID', + 1: 'SC_PSSW_WINDOW_VALID', + 2: 'SC_TPQZ_WINDOW_VALID', + 3: 'SC_QZQP_WINDOW_VALID', + 4: 'SC_TRPK_WINDOW_VALID', + 5: 'SC_SRPS_WINDOW_VALID_BUSY', + 6: 'SC_PSSW_WINDOW_VALID_BUSY', + 7: 'SC_TPQZ_WINDOW_VALID_BUSY', + 8: 'SC_QZQP_WINDOW_VALID_BUSY', + 9: 'SC_TRPK_WINDOW_VALID_BUSY', + 10: 'SC_STARVED_BY_PA', + 11: 'SC_STALLED_BY_PRIMFIFO', + 12: 'SC_STALLED_BY_DB_TILE', + 13: 'SC_STARVED_BY_DB_TILE', + 14: 'SC_STALLED_BY_TILEORDERFIFO', + 15: 'SC_STALLED_BY_TILEFIFO', + 16: 'SC_STALLED_BY_DB_QUAD', + 17: 'SC_STARVED_BY_DB_QUAD', + 18: 'SC_STALLED_BY_QUADFIFO', + 19: 'SC_STALLED_BY_BCI', + 20: 'SC_STALLED_BY_SPI', + 21: 'SC_SCISSOR_DISCARD', + 22: 'SC_BB_DISCARD', + 23: 'SC_SUPERTILE_COUNT', + 24: 'SC_SUPERTILE_PER_PRIM_H0', + 25: 'SC_SUPERTILE_PER_PRIM_H1', + 26: 'SC_SUPERTILE_PER_PRIM_H2', + 27: 'SC_SUPERTILE_PER_PRIM_H3', + 28: 'SC_SUPERTILE_PER_PRIM_H4', + 29: 'SC_SUPERTILE_PER_PRIM_H5', + 30: 'SC_SUPERTILE_PER_PRIM_H6', + 31: 'SC_SUPERTILE_PER_PRIM_H7', + 32: 'SC_SUPERTILE_PER_PRIM_H8', + 33: 'SC_SUPERTILE_PER_PRIM_H9', + 34: 'SC_SUPERTILE_PER_PRIM_H10', + 35: 'SC_SUPERTILE_PER_PRIM_H11', + 36: 'SC_SUPERTILE_PER_PRIM_H12', + 37: 'SC_SUPERTILE_PER_PRIM_H13', + 38: 'SC_SUPERTILE_PER_PRIM_H14', + 39: 'SC_SUPERTILE_PER_PRIM_H15', + 40: 'SC_SUPERTILE_PER_PRIM_H16', + 41: 'SC_TILE_PER_PRIM_H0', + 42: 'SC_TILE_PER_PRIM_H1', + 43: 'SC_TILE_PER_PRIM_H2', + 44: 'SC_TILE_PER_PRIM_H3', + 45: 'SC_TILE_PER_PRIM_H4', + 46: 'SC_TILE_PER_PRIM_H5', + 47: 'SC_TILE_PER_PRIM_H6', + 48: 'SC_TILE_PER_PRIM_H7', + 49: 'SC_TILE_PER_PRIM_H8', + 50: 'SC_TILE_PER_PRIM_H9', + 51: 'SC_TILE_PER_PRIM_H10', + 52: 'SC_TILE_PER_PRIM_H11', + 53: 'SC_TILE_PER_PRIM_H12', + 54: 'SC_TILE_PER_PRIM_H13', + 55: 'SC_TILE_PER_PRIM_H14', + 56: 'SC_TILE_PER_PRIM_H15', + 57: 'SC_TILE_PER_PRIM_H16', + 58: 'SC_TILE_PER_SUPERTILE_H0', + 59: 'SC_TILE_PER_SUPERTILE_H1', + 60: 'SC_TILE_PER_SUPERTILE_H2', + 61: 'SC_TILE_PER_SUPERTILE_H3', + 62: 'SC_TILE_PER_SUPERTILE_H4', + 63: 'SC_TILE_PER_SUPERTILE_H5', + 64: 'SC_TILE_PER_SUPERTILE_H6', + 65: 'SC_TILE_PER_SUPERTILE_H7', + 66: 'SC_TILE_PER_SUPERTILE_H8', + 67: 'SC_TILE_PER_SUPERTILE_H9', + 68: 'SC_TILE_PER_SUPERTILE_H10', + 69: 'SC_TILE_PER_SUPERTILE_H11', + 70: 'SC_TILE_PER_SUPERTILE_H12', + 71: 'SC_TILE_PER_SUPERTILE_H13', + 72: 'SC_TILE_PER_SUPERTILE_H14', + 73: 'SC_TILE_PER_SUPERTILE_H15', + 74: 'SC_TILE_PER_SUPERTILE_H16', + 75: 'SC_TILE_PICKED_H1', + 76: 'SC_PERF_SEL_RESERVED_76', + 77: 'SC_PERF_SEL_RESERVED_77', + 78: 'SC_PERF_SEL_RESERVED_78', + 79: 'SC_QZ0_TILE_COUNT', + 80: 'SC_PERF_SEL_RESERVED_80', + 81: 'SC_PERF_SEL_RESERVED_81', + 82: 'SC_PERF_SEL_RESERVED_82', + 83: 'SC_QZ0_TILE_COVERED_COUNT', + 84: 'SC_PERF_SEL_RESERVED_84', + 85: 'SC_PERF_SEL_RESERVED_85', + 86: 'SC_PERF_SEL_RESERVED_86', + 87: 'SC_QZ0_TILE_NOT_COVERED_COUNT', + 88: 'SC_PERF_SEL_RESERVED_88', + 89: 'SC_PERF_SEL_RESERVED_89', + 90: 'SC_PERF_SEL_RESERVED_90', + 91: 'SC_QZ0_QUAD_PER_TILE_H0', + 92: 'SC_QZ0_QUAD_PER_TILE_H1', + 93: 'SC_QZ0_QUAD_PER_TILE_H2', + 94: 'SC_QZ0_QUAD_PER_TILE_H3', + 95: 'SC_QZ0_QUAD_PER_TILE_H4', + 96: 'SC_QZ0_QUAD_PER_TILE_H5', + 97: 'SC_QZ0_QUAD_PER_TILE_H6', + 98: 'SC_QZ0_QUAD_PER_TILE_H7', + 99: 'SC_QZ0_QUAD_PER_TILE_H8', + 100: 'SC_QZ0_QUAD_PER_TILE_H9', + 101: 'SC_QZ0_QUAD_PER_TILE_H10', + 102: 'SC_QZ0_QUAD_PER_TILE_H11', + 103: 'SC_QZ0_QUAD_PER_TILE_H12', + 104: 'SC_QZ0_QUAD_PER_TILE_H13', + 105: 'SC_QZ0_QUAD_PER_TILE_H14', + 106: 'SC_QZ0_QUAD_PER_TILE_H15', + 107: 'SC_QZ0_QUAD_PER_TILE_H16', + 108: 'SC_PERF_SEL_RESERVED_108', + 109: 'SC_PERF_SEL_RESERVED_109', + 110: 'SC_PERF_SEL_RESERVED_110', + 111: 'SC_PERF_SEL_RESERVED_111', + 112: 'SC_PERF_SEL_RESERVED_112', + 113: 'SC_PERF_SEL_RESERVED_113', + 114: 'SC_PERF_SEL_RESERVED_114', + 115: 'SC_PERF_SEL_RESERVED_115', + 116: 'SC_PERF_SEL_RESERVED_116', + 117: 'SC_PERF_SEL_RESERVED_117', + 118: 'SC_PERF_SEL_RESERVED_118', + 119: 'SC_PERF_SEL_RESERVED_119', + 120: 'SC_PERF_SEL_RESERVED_120', + 121: 'SC_PERF_SEL_RESERVED_121', + 122: 'SC_PERF_SEL_RESERVED_122', + 123: 'SC_PERF_SEL_RESERVED_123', + 124: 'SC_PERF_SEL_RESERVED_124', + 125: 'SC_PERF_SEL_RESERVED_125', + 126: 'SC_PERF_SEL_RESERVED_126', + 127: 'SC_PERF_SEL_RESERVED_127', + 128: 'SC_PERF_SEL_RESERVED_128', + 129: 'SC_PERF_SEL_RESERVED_129', + 130: 'SC_PERF_SEL_RESERVED_130', + 131: 'SC_PERF_SEL_RESERVED_131', + 132: 'SC_PERF_SEL_RESERVED_132', + 133: 'SC_PERF_SEL_RESERVED_133', + 134: 'SC_PERF_SEL_RESERVED_134', + 135: 'SC_PERF_SEL_RESERVED_135', + 136: 'SC_PERF_SEL_RESERVED_136', + 137: 'SC_PERF_SEL_RESERVED_137', + 138: 'SC_PERF_SEL_RESERVED_138', + 139: 'SC_PERF_SEL_RESERVED_139', + 140: 'SC_PERF_SEL_RESERVED_140', + 141: 'SC_PERF_SEL_RESERVED_141', + 142: 'SC_PERF_SEL_RESERVED_142', + 143: 'SC_PERF_SEL_RESERVED_143', + 144: 'SC_PERF_SEL_RESERVED_144', + 145: 'SC_PERF_SEL_RESERVED_145', + 146: 'SC_PERF_SEL_RESERVED_146', + 147: 'SC_PERF_SEL_RESERVED_147', + 148: 'SC_PERF_SEL_RESERVED_148', + 149: 'SC_PERF_SEL_RESERVED_149', + 150: 'SC_PERF_SEL_RESERVED_150', + 151: 'SC_PERF_SEL_RESERVED_151', + 152: 'SC_PERF_SEL_RESERVED_152', + 153: 'SC_PERF_SEL_RESERVED_153', + 154: 'SC_PERF_SEL_RESERVED_154', + 155: 'SC_PERF_SEL_RESERVED_155', + 156: 'SC_PERF_SEL_RESERVED_156', + 157: 'SC_PERF_SEL_RESERVED_157', + 158: 'SC_PERF_SEL_RESERVED_158', + 159: 'SC_QZ0_QUAD_COUNT', + 160: 'SC_PERF_SEL_RESERVED_160', + 161: 'SC_PERF_SEL_RESERVED_161', + 162: 'SC_PERF_SEL_RESERVED_162', + 163: 'SC_P0_HIZ_TILE_COUNT', + 164: 'SC_PERF_SEL_RESERVED_164', + 165: 'SC_PERF_SEL_RESERVED_165', + 166: 'SC_PERF_SEL_RESERVED_166', + 167: 'SC_P0_HIZ_QUAD_PER_TILE_H0', + 168: 'SC_P0_HIZ_QUAD_PER_TILE_H1', + 169: 'SC_P0_HIZ_QUAD_PER_TILE_H2', + 170: 'SC_P0_HIZ_QUAD_PER_TILE_H3', + 171: 'SC_P0_HIZ_QUAD_PER_TILE_H4', + 172: 'SC_P0_HIZ_QUAD_PER_TILE_H5', + 173: 'SC_P0_HIZ_QUAD_PER_TILE_H6', + 174: 'SC_P0_HIZ_QUAD_PER_TILE_H7', + 175: 'SC_P0_HIZ_QUAD_PER_TILE_H8', + 176: 'SC_P0_HIZ_QUAD_PER_TILE_H9', + 177: 'SC_P0_HIZ_QUAD_PER_TILE_H10', + 178: 'SC_P0_HIZ_QUAD_PER_TILE_H11', + 179: 'SC_P0_HIZ_QUAD_PER_TILE_H12', + 180: 'SC_P0_HIZ_QUAD_PER_TILE_H13', + 181: 'SC_P0_HIZ_QUAD_PER_TILE_H14', + 182: 'SC_P0_HIZ_QUAD_PER_TILE_H15', + 183: 'SC_P0_HIZ_QUAD_PER_TILE_H16', + 184: 'SC_PERF_SEL_RESERVED_184', + 185: 'SC_PERF_SEL_RESERVED_185', + 186: 'SC_PERF_SEL_RESERVED_186', + 187: 'SC_PERF_SEL_RESERVED_187', + 188: 'SC_PERF_SEL_RESERVED_188', + 189: 'SC_PERF_SEL_RESERVED_189', + 190: 'SC_PERF_SEL_RESERVED_190', + 191: 'SC_PERF_SEL_RESERVED_191', + 192: 'SC_PERF_SEL_RESERVED_192', + 193: 'SC_PERF_SEL_RESERVED_193', + 194: 'SC_PERF_SEL_RESERVED_194', + 195: 'SC_PERF_SEL_RESERVED_195', + 196: 'SC_PERF_SEL_RESERVED_196', + 197: 'SC_PERF_SEL_RESERVED_197', + 198: 'SC_PERF_SEL_RESERVED_198', + 199: 'SC_PERF_SEL_RESERVED_199', + 200: 'SC_PERF_SEL_RESERVED_200', + 201: 'SC_PERF_SEL_RESERVED_201', + 202: 'SC_PERF_SEL_RESERVED_202', + 203: 'SC_PERF_SEL_RESERVED_203', + 204: 'SC_PERF_SEL_RESERVED_204', + 205: 'SC_PERF_SEL_RESERVED_205', + 206: 'SC_PERF_SEL_RESERVED_206', + 207: 'SC_PERF_SEL_RESERVED_207', + 208: 'SC_PERF_SEL_RESERVED_208', + 209: 'SC_PERF_SEL_RESERVED_209', + 210: 'SC_PERF_SEL_RESERVED_210', + 211: 'SC_PERF_SEL_RESERVED_211', + 212: 'SC_PERF_SEL_RESERVED_212', + 213: 'SC_PERF_SEL_RESERVED_213', + 214: 'SC_PERF_SEL_RESERVED_214', + 215: 'SC_PERF_SEL_RESERVED_215', + 216: 'SC_PERF_SEL_RESERVED_216', + 217: 'SC_PERF_SEL_RESERVED_217', + 218: 'SC_PERF_SEL_RESERVED_218', + 219: 'SC_PERF_SEL_RESERVED_219', + 220: 'SC_PERF_SEL_RESERVED_220', + 221: 'SC_PERF_SEL_RESERVED_221', + 222: 'SC_PERF_SEL_RESERVED_222', + 223: 'SC_PERF_SEL_RESERVED_223', + 224: 'SC_PERF_SEL_RESERVED_224', + 225: 'SC_PERF_SEL_RESERVED_225', + 226: 'SC_PERF_SEL_RESERVED_226', + 227: 'SC_PERF_SEL_RESERVED_227', + 228: 'SC_PERF_SEL_RESERVED_228', + 229: 'SC_PERF_SEL_RESERVED_229', + 230: 'SC_PERF_SEL_RESERVED_230', + 231: 'SC_PERF_SEL_RESERVED_231', + 232: 'SC_PERF_SEL_RESERVED_232', + 233: 'SC_PERF_SEL_RESERVED_233', + 234: 'SC_PERF_SEL_RESERVED_234', + 235: 'SC_P0_HIZ_QUAD_COUNT', + 236: 'SC_PERF_SEL_RESERVED_236', + 237: 'SC_PERF_SEL_RESERVED_237', + 238: 'SC_PERF_SEL_RESERVED_238', + 239: 'SC_P0_DETAIL_QUAD_COUNT', + 240: 'SC_PERF_SEL_RESERVED_240', + 241: 'SC_PERF_SEL_RESERVED_241', + 242: 'SC_PERF_SEL_RESERVED_242', + 243: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', + 244: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', + 245: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', + 246: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', + 247: 'SC_PERF_SEL_RESERVED_247', + 248: 'SC_PERF_SEL_RESERVED_248', + 249: 'SC_PERF_SEL_RESERVED_249', + 250: 'SC_PERF_SEL_RESERVED_250', + 251: 'SC_PERF_SEL_RESERVED_251', + 252: 'SC_PERF_SEL_RESERVED_252', + 253: 'SC_PERF_SEL_RESERVED_253', + 254: 'SC_PERF_SEL_RESERVED_254', + 255: 'SC_PERF_SEL_RESERVED_255', + 256: 'SC_PERF_SEL_RESERVED_256', + 257: 'SC_PERF_SEL_RESERVED_257', + 258: 'SC_PERF_SEL_RESERVED_258', + 259: 'SC_EARLYZ_QUAD_COUNT', + 260: 'SC_EARLYZ_QUAD_WITH_1_PIX', + 261: 'SC_EARLYZ_QUAD_WITH_2_PIX', + 262: 'SC_EARLYZ_QUAD_WITH_3_PIX', + 263: 'SC_EARLYZ_QUAD_WITH_4_PIX', + 264: 'SC_PKR_QUAD_PER_ROW_H1', + 265: 'SC_PKR_QUAD_PER_ROW_H2', + 266: 'SC_PKR_4X2_QUAD_SPLIT', + 267: 'SC_PKR_4X2_FILL_QUAD', + 268: 'SC_PKR_END_OF_VECTOR', + 269: 'SC_PKR_CONTROL_XFER', + 270: 'SC_PKR_DBHANG_FORCE_EOV', + 271: 'SC_REG_SCLK_BUSY', + 272: 'SC_GRP0_DYN_SCLK_BUSY', + 273: 'SC_GRP1_DYN_SCLK_BUSY', + 274: 'SC_GRP2_DYN_SCLK_BUSY', + 275: 'SC_GRP3_DYN_SCLK_BUSY', + 276: 'SC_GRP4_DYN_SCLK_BUSY', + 277: 'SC_PA0_SC_DATA_FIFO_RD', + 278: 'SC_PA0_SC_DATA_FIFO_WE', + 279: 'SC_PERF_SEL_RESERVED_279', + 280: 'SC_PERF_SEL_RESERVED_280', + 281: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 282: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', + 283: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 284: 'SC_PS_ARB_STALLED_FROM_BELOW', + 285: 'SC_PS_ARB_STARVED_FROM_ABOVE', + 286: 'SC_PS_ARB_SC_BUSY', + 287: 'SC_PS_ARB_PA_SC_BUSY', + 288: 'SC_PERF_SEL_RESERVED_288', + 289: 'SC_PERF_SEL_RESERVED_289', + 290: 'SC_PERF_SEL_RESERVED_290', + 291: 'SC_PERF_SEL_RESERVED_291', + 292: 'SC_PA_SC_DEALLOC_2_0_WE', + 293: 'SC_PERF_SEL_RESERVED_293', + 294: 'SC_PERF_SEL_RESERVED_294', + 295: 'SC_PERF_SEL_RESERVED_295', + 296: 'SC_PERF_SEL_RESERVED_296', + 297: 'SC_PERF_SEL_RESERVED_297', + 298: 'SC_PERF_SEL_RESERVED_298', + 299: 'SC_PERF_SEL_RESERVED_299', + 300: 'SC_PA0_SC_EOP_WE', + 301: 'SC_PERF_SEL_RESERVED_301', + 302: 'SC_PA0_SC_EVENT_WE', + 303: 'SC_PERF_SEL_RESERVED_303', + 304: 'SC_PERF_SEL_RESERVED_304', + 305: 'SC_PERF_SEL_RESERVED_305', + 306: 'SC_PERF_SEL_RESERVED_306', + 307: 'SC_PERF_SEL_RESERVED_307', + 308: 'SC_PERF_SEL_RESERVED_308', + 309: 'SC_PERF_SEL_RESERVED_309', + 310: 'SC_PERF_SEL_RESERVED_310', + 311: 'SC_PERF_SEL_RESERVED_311', + 312: 'SC_PERF_SEL_RESERVED_312', + 313: 'SC_PERF_SEL_RESERVED_313', + 314: 'SC_PERF_SEL_RESERVED_314', + 315: 'SC_PERF_SEL_RESERVED_315', + 316: 'SC_PERF_SEL_RESERVED_316', + 317: 'SC_PERF_SEL_RESERVED_317', + 318: 'SC_PA_SC_FPOV_WE', + 319: 'SC_PERF_SEL_RESERVED_319', + 320: 'SC_PERF_SEL_RESERVED_320', + 321: 'SC_PERF_SEL_RESERVED_321', + 322: 'SC_PERF_SEL_RESERVED_322', + 323: 'SC_PERF_SEL_RESERVED_323', + 324: 'SC_PERF_SEL_RESERVED_324', + 325: 'SC_PERF_SEL_RESERVED_325', + 326: 'SC_SPI_DEALLOC_4_0', + 327: 'SC_SPI_DEALLOC_7_5', + 328: 'SC_PERF_SEL_RESERVED_328', + 329: 'SC_PERF_SEL_RESERVED_329', + 330: 'SC_PERF_SEL_RESERVED_330', + 331: 'SC_PERF_SEL_RESERVED_331', + 332: 'SC_PERF_SEL_RESERVED_332', + 333: 'SC_PERF_SEL_RESERVED_333', + 334: 'SC_PERF_SEL_RESERVED_334', + 335: 'SC_PERF_SEL_RESERVED_335', + 336: 'SC_PERF_SEL_RESERVED_336', + 337: 'SC_PERF_SEL_RESERVED_337', + 338: 'SC_SPI_FPOV_4_0', + 339: 'SC_SPI_FPOV_7_5', + 340: 'SC_PERF_SEL_RESERVED_340', + 341: 'SC_PERF_SEL_RESERVED_341', + 342: 'SC_SPI_EVENT', + 343: 'SC_PS_TS_EVENT_FIFO_PUSH', + 344: 'SC_PS_TS_EVENT_FIFO_POP', + 345: 'SC_PS_CTX_DONE_FIFO_PUSH', + 346: 'SC_PS_CTX_DONE_FIFO_POP', + 347: 'SC_PERF_SEL_RESERVED_347', + 348: 'SC_PERF_SEL_RESERVED_348', + 349: 'SC_PA0_SC_NULL_WE', + 350: 'SC_PA0_SC_NULL_DEALLOC_WE', + 351: 'SC_PERF_SEL_RESERVED_351', + 352: 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 353: 'SC_PA0_SC_DEALLOC_2_0_RD', + 354: 'SC_PERF_SEL_RESERVED_354', + 355: 'SC_PERF_SEL_RESERVED_355', + 356: 'SC_PERF_SEL_RESERVED_356', + 357: 'SC_PERF_SEL_RESERVED_357', + 358: 'SC_PERF_SEL_RESERVED_358', + 359: 'SC_PERF_SEL_RESERVED_359', + 360: 'SC_PERF_SEL_RESERVED_360', + 361: 'SC_PERF_SEL_RESERVED_361', + 362: 'SC_PERF_SEL_RESERVED_362', + 363: 'SC_PERF_SEL_RESERVED_363', + 364: 'SC_PERF_SEL_RESERVED_364', + 365: 'SC_PERF_SEL_RESERVED_365', + 366: 'SC_PERF_SEL_RESERVED_366', + 367: 'SC_PERF_SEL_RESERVED_367', + 368: 'SC_PERF_SEL_RESERVED_368', + 369: 'SC_PERF_SEL_RESERVED_369', + 370: 'SC_PERF_SEL_RESERVED_370', + 371: 'SC_PERF_SEL_RESERVED_371', + 372: 'SC_PERF_SEL_RESERVED_372', + 373: 'SC_PS_PA0_SC_FIFO_EMPTY', + 374: 'SC_PS_PA0_SC_FIFO_FULL', + 375: 'SC_PERF_SEL_RESERVED_375', + 376: 'SC_PERF_SEL_RESERVED_376', + 377: 'SC_PERF_SEL_RESERVED_377', + 378: 'SC_PERF_SEL_RESERVED_378', + 379: 'SC_PERF_SEL_RESERVED_379', + 380: 'SC_PERF_SEL_RESERVED_380', + 381: 'SC_PERF_SEL_RESERVED_381', + 382: 'SC_PERF_SEL_RESERVED_382', + 383: 'SC_PERF_SEL_RESERVED_383', + 384: 'SC_PERF_SEL_RESERVED_384', + 385: 'SC_PERF_SEL_RESERVED_385', + 386: 'SC_BUSY_CNT_NOT_ZERO', + 387: 'SC_BM_BUSY', + 388: 'SC_BACKEND_BUSY', + 389: 'SC_SCF_SCB_INTERFACE_BUSY', + 390: 'SC_SCB_BUSY', + 391: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 392: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 393: 'SC_PBB_BIN_HIST_NUM_PRIMS', + 394: 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 395: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 396: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 397: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 398: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 399: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 400: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 401: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 402: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 403: 'SC_PBB_BUSY', + 404: 'SC_PBB_BUSY_AND_NO_SENDS', + 405: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 406: 'SC_PBB_NUM_BINS', + 407: 'SC_PBB_END_OF_BIN', + 408: 'SC_PBB_END_OF_BATCH', + 409: 'SC_PBB_PRIMBIN_PROCESSED', + 410: 'SC_PBB_PRIM_ADDED_TO_BATCH', + 411: 'SC_PBB_NONBINNED_PRIM', + 412: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', + 413: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 414: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 415: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 416: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 417: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 418: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 419: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 420: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 421: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 422: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 423: 'SC_PERF_SEL_RESERVED_423', + 424: 'SC_PERF_SEL_RESERVED_424', + 425: 'SC_PERF_SEL_RESERVED_425', + 426: 'SC_PERF_SEL_RESERVED_426', + 427: 'SC_PERF_SEL_RESERVED_427', + 428: 'SC_PERF_SEL_RESERVED_428', + 429: 'SC_PERF_SEL_RESERVED_429', + 430: 'SC_PERF_SEL_RESERVED_430', + 431: 'SC_PERF_SEL_RESERVED_431', + 432: 'SC_PERF_SEL_RESERVED_432', + 433: 'SC_PERF_SEL_RESERVED_433', + 434: 'SC_PERF_SEL_RESERVED_434', + 435: 'SC_PERF_SEL_RESERVED_435', + 436: 'SC_PERF_SEL_RESERVED_436', + 437: 'SC_GRP5_DYN_SCLK_BUSY', + 438: 'SC_GRP6_DYN_SCLK_BUSY', + 439: 'SC_GRP7_DYN_SCLK_BUSY', + 440: 'SC_GRP8_DYN_SCLK_BUSY', + 441: 'SC_GRP9_DYN_SCLK_BUSY', + 442: 'SC_PS_TO_BE_SCLK_GATE_STALL', + 443: 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', + 444: 'SC_PK_BUSY', + 445: 'SC_PK_MAX_DEALLOC_FORCE_EOV', + 446: 'SC_PK_DEALLOC_WAVE_BREAK', + 447: 'SC_SPI_SEND', + 448: 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 449: 'SC_SPI_CREDIT_AT_MAX', + 450: 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', + 451: 'SC_BCI_SEND', + 452: 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 453: 'SC_BCI_CREDIT_AT_MAX', + 454: 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', + 455: 'SC_SPIBC_FULL_FREEZE', + 456: 'SC_PW_BM_PASS_EMPTY_PRIM', + 457: 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', + 458: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', + 459: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', + 460: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', + 461: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', + 462: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', + 463: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', + 464: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', + 465: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', + 466: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', + 467: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', + 468: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', + 469: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', + 470: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', + 471: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', + 472: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', + 473: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', + 474: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', + 475: 'SC_DB0_TILE_INTERFACE_BUSY', + 476: 'SC_DB0_TILE_INTERFACE_SEND', + 477: 'SC_DB0_TILE_INTERFACE_SEND_EVENT', + 478: 'SC_PERF_SEL_RESERVED_478', + 479: 'SC_PERF_SEL_RESERVED_479', + 480: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 481: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', + 482: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 483: 'SC_PERF_SEL_RESERVED_483', + 484: 'SC_PERF_SEL_RESERVED_484', + 485: 'SC_PERF_SEL_RESERVED_485', + 486: 'SC_PERF_SEL_RESERVED_486', + 487: 'SC_PERF_SEL_RESERVED_487', + 488: 'SC_PERF_SEL_RESERVED_488', + 489: 'SC_PERF_SEL_RESERVED_489', + 490: 'SC_PERF_SEL_RESERVED_490', + 491: 'SC_BACKEND_PRIM_FIFO_FULL', + 492: 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', + 493: 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', + 494: 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', + 495: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', + 496: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', + 497: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', + 498: 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', + 499: 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', + 500: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', + 501: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', + 502: 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', + 503: 'SC_STALLED_BY_DB0_TILEFIFO', + 504: 'SC_DB0_QUAD_INTF_SEND', + 505: 'SC_DB0_QUAD_INTF_BUSY', + 506: 'SC_DB0_QUAD_INTF_STALLED_BY_DB', + 507: 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', + 508: 'SC_DB0_QUAD_INTF_IDLE', + 509: 'SC_PERF_SEL_RESERVED_509', + 510: 'SC_PERF_SEL_RESERVED_510', + 511: 'SC_PERF_SEL_RESERVED_511', + 512: 'SC_PERF_SEL_RESERVED_512', + 513: 'SC_PERF_SEL_RESERVED_513', + 514: 'SC_PERF_SEL_RESERVED_514', + 515: 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', + 516: 'SC_PKR_WAVE_BREAK_FULL_TILE', + 517: 'SC_RESERVED_60', + 518: 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', + 519: 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', + 520: 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', + 521: 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 522: 'SC_DB0_TILE_MASK_FIFO_FULL', + 523: 'SC_PERF_SEL_RESERVED_523', + 524: 'SC_PERF_SEL_RESERVED_524', + 525: 'SC_PERF_SEL_RESERVED_525', + 526: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', + 527: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', + 528: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', + 529: 'SC_PS_PM_PFF_PW_FULL', + 530: 'SC_PS_PM_ZFF_PW_FULL', + 531: 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', + 532: 'SC_PERF_SEL_RESERVED_532', + 533: 'SC_PERF_SEL_RESERVED_533', + 534: 'SC_PERF_SEL_RESERVED_534', + 535: 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', + 536: 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', + 537: 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', + 538: 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', + 539: 'SC_PERF_SEL_RESERVED_539', + 540: 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', + 541: 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 542: 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', + 543: 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 544: 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', + 545: 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', + 546: 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', + 547: 'SC_PK_PM_OREO_CONFLICT_QUAD_FORCE_EOV_WAVE_BRK_1H', + 548: 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', + 549: 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', + 550: 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', + 551: 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', + 552: 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', + 553: 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', + 554: 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', + 555: 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', + 556: 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', + 557: 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', + 558: 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', + 559: 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', + 560: 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', + 561: 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', + 562: 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', + 563: 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', + 564: 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', + 565: 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', + 566: 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', + 567: 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', + 568: 'SC_PERF_SEL_RESERVED_568', + 569: 'SC_PBB_RESERVED', + 570: 'SC_BM_BE0_STALLED', + 571: 'SC_BM_BE1_STALLED', + 572: 'SC_BM_BE2_STALLED', + 573: 'SC_BM_BE3_STALLED', + 574: 'SC_BM_MULTI_ACCUM_1_BE_STALLED', + 575: 'SC_BM_MULTI_ACCUM_2_BE_STALLED', + 576: 'SC_BM_MULTI_ACCUM_3_BE_STALLED', + 577: 'SC_BM_MULTI_ACCUM_4_BE_STALLED', + 578: 'SC_PBB_READ_PH0', + 579: 'SC_PBB_READ_DEALLOC_4_0', + 580: 'SC_PBB_READ_DEALLOC_7_5', + 581: 'SC_PBB_READ_FPOG_4_0', + 582: 'SC_PBB_READ_FPOG_7_5', + 583: 'SC_VRC_SECTOR_HIT', + 584: 'SC_VRC_TAG_MISS', + 585: 'SC_VRC_SECTOR_MISS', + 586: 'SC_VRC_LRU_EVICT_STALL', + 587: 'SC_VRC_LRU_EVICT_SCHEDULED_EVICT_STALL', + 588: 'SC_VRC_LRU_EVICT_PENDING_EVICT_STALL', + 589: 'SC_VRC_REEVICTION_STALL', + 590: 'SC_VRC_EVICT_NONZERO_INFLIGHT_STALL', + 591: 'SC_VRC_REPLACE_SCHEDULED_EVICT_STALL', + 592: 'SC_VRC_REPLACE_PENDING_EVICT_STALL', + 593: 'SC_VRC_REPLACE_FLUSH_IN_PROGRESS_STALL', + 594: 'SC_VRC_INFLIGHT_COUNTER_MAXIMUM_STALL', + 595: 'SC_VRC_READ_OUTPUT_STALL', + 596: 'SC_VRC_WRITE_OUTPUT_STALL', + 597: 'SC_VRC_ACK_OUTPUT_STALL', + 598: 'SC_VRC_FLUSH_EVICT_STALL', + 599: 'SC_VRC_FLUSH_REFLUSH_STALL', + 600: 'SC_VRC_FLUSH_FIP_HIT_STALL', + 601: 'SC_VRC_FLUSH_WRREQ_DRAIN_STALL', + 602: 'SC_VRC_FLUSH_DONE_STALL', + 603: 'SC_VRC_FLUSH_STALL', + 604: 'SC_VRC_STALL', + 605: 'SC_VRC_FLUSH', + 606: 'SC_VRC_SECTORS_FLUSHED', + 607: 'SC_VRC_DIRTY_SECTORS_FLUSHED', + 608: 'SC_VRC_TAGS_FLUSHED', + 609: 'SC_VRC_HPF_REQ', + 610: 'SC_VRC_HPF_EVENT', + 611: 'SC_VRC_HPF_STALLED', + 612: 'SC_VRC_PROBE_ACK_TILES', + 613: 'SC_VRC_GL1X_RD_REQ', + 614: 'SC_VRC_GL1X_WR_REQ', + 615: 'SC_VRC_GL1X_SRC_XFR', + 616: 'SC_VRC_GL1X_RD_RET', + 617: 'SC_VRC_GL1X_WR_ACK', + 618: 'SC_VRC_GL1X_RD_XNACK', + 619: 'SC_VRC_GL1X_WR_XNACK', + 620: 'SC_VRC_GL1X_REQ_STALLED', + 621: 'SC_VRC_GL1X_SRC_STALLED', + 622: 'SC_VRC_RATEMEM_WE_CNT', + 623: 'SC_VRC_RATEMEM_RE_CNT', + 624: 'SC_VRC_HINTMEM_WE_CNT', + 625: 'SC_VRC_HINTMEM_RE_CNT', + 626: 'SC_VRC_BUSY', + 627: 'SC_GL1X_BUSY', + 628: 'SC_BE_VRS_RD_REQ', + 629: 'SC_BE_VRS_RD_REQ_STALLED', + 630: 'SC_BE_VRS_RD_REQ_HIT', + 631: 'SC_BE_VRS_RD_RET', + 632: 'SC_BE_VRS_RD_RET_STALLED', + 633: 'SC_BE_VRS_FB_RET', + 634: 'SC_BE_VRS_FB_RET_STALLED', + 635: 'SC_BE_VRS_FB_RET_HIT', + 636: 'SC_VRS_BE_BUSY', + 637: 'SC_PWS_CS_EVENTS_PWS_ENABLE', + 638: 'SC_PWS_PS_EVENTS_PWS_ENABLE', + 639: 'SC_PWS_TS_EVENTS_PWS_ENABLE', + 640: 'SC_PWS_STALLED', + 641: 'SC_PWS_P0_CS_SYNC_COMPLETE', + 642: 'SC_PWS_P0_PS_SYNC_COMPLETE', + 643: 'SC_PWS_P0_TS_SYNC_COMPLETE', + 644: 'SC_PWS_P1_CS_SYNC_COMPLETE', + 645: 'SC_PWS_P1_PS_SYNC_COMPLETE', + 646: 'SC_PWS_P1_TS_SYNC_COMPLETE', + 647: 'SC_PKR_PC_NO_CREDITS', + 648: 'SC_PKR_PC_STALLED', + 649: 'SC_PKR_PC_SEND', + 650: 'SC_PKR_PC_SEND_PRIM_VALID_1', + 651: 'SC_PKR_PC_SEND_PRIM_VALID_0', + 652: 'SC_PKR_PC_SEND_TRUE_PRIM', + 653: 'SC_PKR_PC_SEND_EOV', + 654: 'SC_PKR_PC_SEND_EVENT', + 655: 'SC_PKR_DB_WAVE_STALL', + 656: 'SC_PKR_PSINVOC_SEDC_FIFO_FULL', + 657: 'SC_PKR_OREO_STALLED_BY_NO_VALID_WAIVE_ID', + 658: 'SC_PKR_SPI_QUAD_COUNT', + 659: 'SC_PKR_DB_OREO_WAVE_QUAD_COUNT', + 660: 'SC_PKR_BCI_QUAD_NEW_PRIM', + 661: 'SC_SPI_WAVE_STALLED_BY_SPI', +} +SC_SRPS_WINDOW_VALID = 0 +SC_PSSW_WINDOW_VALID = 1 +SC_TPQZ_WINDOW_VALID = 2 +SC_QZQP_WINDOW_VALID = 3 +SC_TRPK_WINDOW_VALID = 4 +SC_SRPS_WINDOW_VALID_BUSY = 5 +SC_PSSW_WINDOW_VALID_BUSY = 6 +SC_TPQZ_WINDOW_VALID_BUSY = 7 +SC_QZQP_WINDOW_VALID_BUSY = 8 +SC_TRPK_WINDOW_VALID_BUSY = 9 +SC_STARVED_BY_PA = 10 +SC_STALLED_BY_PRIMFIFO = 11 +SC_STALLED_BY_DB_TILE = 12 +SC_STARVED_BY_DB_TILE = 13 +SC_STALLED_BY_TILEORDERFIFO = 14 +SC_STALLED_BY_TILEFIFO = 15 +SC_STALLED_BY_DB_QUAD = 16 +SC_STARVED_BY_DB_QUAD = 17 +SC_STALLED_BY_QUADFIFO = 18 +SC_STALLED_BY_BCI = 19 +SC_STALLED_BY_SPI = 20 +SC_SCISSOR_DISCARD = 21 +SC_BB_DISCARD = 22 +SC_SUPERTILE_COUNT = 23 +SC_SUPERTILE_PER_PRIM_H0 = 24 +SC_SUPERTILE_PER_PRIM_H1 = 25 +SC_SUPERTILE_PER_PRIM_H2 = 26 +SC_SUPERTILE_PER_PRIM_H3 = 27 +SC_SUPERTILE_PER_PRIM_H4 = 28 +SC_SUPERTILE_PER_PRIM_H5 = 29 +SC_SUPERTILE_PER_PRIM_H6 = 30 +SC_SUPERTILE_PER_PRIM_H7 = 31 +SC_SUPERTILE_PER_PRIM_H8 = 32 +SC_SUPERTILE_PER_PRIM_H9 = 33 +SC_SUPERTILE_PER_PRIM_H10 = 34 +SC_SUPERTILE_PER_PRIM_H11 = 35 +SC_SUPERTILE_PER_PRIM_H12 = 36 +SC_SUPERTILE_PER_PRIM_H13 = 37 +SC_SUPERTILE_PER_PRIM_H14 = 38 +SC_SUPERTILE_PER_PRIM_H15 = 39 +SC_SUPERTILE_PER_PRIM_H16 = 40 +SC_TILE_PER_PRIM_H0 = 41 +SC_TILE_PER_PRIM_H1 = 42 +SC_TILE_PER_PRIM_H2 = 43 +SC_TILE_PER_PRIM_H3 = 44 +SC_TILE_PER_PRIM_H4 = 45 +SC_TILE_PER_PRIM_H5 = 46 +SC_TILE_PER_PRIM_H6 = 47 +SC_TILE_PER_PRIM_H7 = 48 +SC_TILE_PER_PRIM_H8 = 49 +SC_TILE_PER_PRIM_H9 = 50 +SC_TILE_PER_PRIM_H10 = 51 +SC_TILE_PER_PRIM_H11 = 52 +SC_TILE_PER_PRIM_H12 = 53 +SC_TILE_PER_PRIM_H13 = 54 +SC_TILE_PER_PRIM_H14 = 55 +SC_TILE_PER_PRIM_H15 = 56 +SC_TILE_PER_PRIM_H16 = 57 +SC_TILE_PER_SUPERTILE_H0 = 58 +SC_TILE_PER_SUPERTILE_H1 = 59 +SC_TILE_PER_SUPERTILE_H2 = 60 +SC_TILE_PER_SUPERTILE_H3 = 61 +SC_TILE_PER_SUPERTILE_H4 = 62 +SC_TILE_PER_SUPERTILE_H5 = 63 +SC_TILE_PER_SUPERTILE_H6 = 64 +SC_TILE_PER_SUPERTILE_H7 = 65 +SC_TILE_PER_SUPERTILE_H8 = 66 +SC_TILE_PER_SUPERTILE_H9 = 67 +SC_TILE_PER_SUPERTILE_H10 = 68 +SC_TILE_PER_SUPERTILE_H11 = 69 +SC_TILE_PER_SUPERTILE_H12 = 70 +SC_TILE_PER_SUPERTILE_H13 = 71 +SC_TILE_PER_SUPERTILE_H14 = 72 +SC_TILE_PER_SUPERTILE_H15 = 73 +SC_TILE_PER_SUPERTILE_H16 = 74 +SC_TILE_PICKED_H1 = 75 +SC_PERF_SEL_RESERVED_76 = 76 +SC_PERF_SEL_RESERVED_77 = 77 +SC_PERF_SEL_RESERVED_78 = 78 +SC_QZ0_TILE_COUNT = 79 +SC_PERF_SEL_RESERVED_80 = 80 +SC_PERF_SEL_RESERVED_81 = 81 +SC_PERF_SEL_RESERVED_82 = 82 +SC_QZ0_TILE_COVERED_COUNT = 83 +SC_PERF_SEL_RESERVED_84 = 84 +SC_PERF_SEL_RESERVED_85 = 85 +SC_PERF_SEL_RESERVED_86 = 86 +SC_QZ0_TILE_NOT_COVERED_COUNT = 87 +SC_PERF_SEL_RESERVED_88 = 88 +SC_PERF_SEL_RESERVED_89 = 89 +SC_PERF_SEL_RESERVED_90 = 90 +SC_QZ0_QUAD_PER_TILE_H0 = 91 +SC_QZ0_QUAD_PER_TILE_H1 = 92 +SC_QZ0_QUAD_PER_TILE_H2 = 93 +SC_QZ0_QUAD_PER_TILE_H3 = 94 +SC_QZ0_QUAD_PER_TILE_H4 = 95 +SC_QZ0_QUAD_PER_TILE_H5 = 96 +SC_QZ0_QUAD_PER_TILE_H6 = 97 +SC_QZ0_QUAD_PER_TILE_H7 = 98 +SC_QZ0_QUAD_PER_TILE_H8 = 99 +SC_QZ0_QUAD_PER_TILE_H9 = 100 +SC_QZ0_QUAD_PER_TILE_H10 = 101 +SC_QZ0_QUAD_PER_TILE_H11 = 102 +SC_QZ0_QUAD_PER_TILE_H12 = 103 +SC_QZ0_QUAD_PER_TILE_H13 = 104 +SC_QZ0_QUAD_PER_TILE_H14 = 105 +SC_QZ0_QUAD_PER_TILE_H15 = 106 +SC_QZ0_QUAD_PER_TILE_H16 = 107 +SC_PERF_SEL_RESERVED_108 = 108 +SC_PERF_SEL_RESERVED_109 = 109 +SC_PERF_SEL_RESERVED_110 = 110 +SC_PERF_SEL_RESERVED_111 = 111 +SC_PERF_SEL_RESERVED_112 = 112 +SC_PERF_SEL_RESERVED_113 = 113 +SC_PERF_SEL_RESERVED_114 = 114 +SC_PERF_SEL_RESERVED_115 = 115 +SC_PERF_SEL_RESERVED_116 = 116 +SC_PERF_SEL_RESERVED_117 = 117 +SC_PERF_SEL_RESERVED_118 = 118 +SC_PERF_SEL_RESERVED_119 = 119 +SC_PERF_SEL_RESERVED_120 = 120 +SC_PERF_SEL_RESERVED_121 = 121 +SC_PERF_SEL_RESERVED_122 = 122 +SC_PERF_SEL_RESERVED_123 = 123 +SC_PERF_SEL_RESERVED_124 = 124 +SC_PERF_SEL_RESERVED_125 = 125 +SC_PERF_SEL_RESERVED_126 = 126 +SC_PERF_SEL_RESERVED_127 = 127 +SC_PERF_SEL_RESERVED_128 = 128 +SC_PERF_SEL_RESERVED_129 = 129 +SC_PERF_SEL_RESERVED_130 = 130 +SC_PERF_SEL_RESERVED_131 = 131 +SC_PERF_SEL_RESERVED_132 = 132 +SC_PERF_SEL_RESERVED_133 = 133 +SC_PERF_SEL_RESERVED_134 = 134 +SC_PERF_SEL_RESERVED_135 = 135 +SC_PERF_SEL_RESERVED_136 = 136 +SC_PERF_SEL_RESERVED_137 = 137 +SC_PERF_SEL_RESERVED_138 = 138 +SC_PERF_SEL_RESERVED_139 = 139 +SC_PERF_SEL_RESERVED_140 = 140 +SC_PERF_SEL_RESERVED_141 = 141 +SC_PERF_SEL_RESERVED_142 = 142 +SC_PERF_SEL_RESERVED_143 = 143 +SC_PERF_SEL_RESERVED_144 = 144 +SC_PERF_SEL_RESERVED_145 = 145 +SC_PERF_SEL_RESERVED_146 = 146 +SC_PERF_SEL_RESERVED_147 = 147 +SC_PERF_SEL_RESERVED_148 = 148 +SC_PERF_SEL_RESERVED_149 = 149 +SC_PERF_SEL_RESERVED_150 = 150 +SC_PERF_SEL_RESERVED_151 = 151 +SC_PERF_SEL_RESERVED_152 = 152 +SC_PERF_SEL_RESERVED_153 = 153 +SC_PERF_SEL_RESERVED_154 = 154 +SC_PERF_SEL_RESERVED_155 = 155 +SC_PERF_SEL_RESERVED_156 = 156 +SC_PERF_SEL_RESERVED_157 = 157 +SC_PERF_SEL_RESERVED_158 = 158 +SC_QZ0_QUAD_COUNT = 159 +SC_PERF_SEL_RESERVED_160 = 160 +SC_PERF_SEL_RESERVED_161 = 161 +SC_PERF_SEL_RESERVED_162 = 162 +SC_P0_HIZ_TILE_COUNT = 163 +SC_PERF_SEL_RESERVED_164 = 164 +SC_PERF_SEL_RESERVED_165 = 165 +SC_PERF_SEL_RESERVED_166 = 166 +SC_P0_HIZ_QUAD_PER_TILE_H0 = 167 +SC_P0_HIZ_QUAD_PER_TILE_H1 = 168 +SC_P0_HIZ_QUAD_PER_TILE_H2 = 169 +SC_P0_HIZ_QUAD_PER_TILE_H3 = 170 +SC_P0_HIZ_QUAD_PER_TILE_H4 = 171 +SC_P0_HIZ_QUAD_PER_TILE_H5 = 172 +SC_P0_HIZ_QUAD_PER_TILE_H6 = 173 +SC_P0_HIZ_QUAD_PER_TILE_H7 = 174 +SC_P0_HIZ_QUAD_PER_TILE_H8 = 175 +SC_P0_HIZ_QUAD_PER_TILE_H9 = 176 +SC_P0_HIZ_QUAD_PER_TILE_H10 = 177 +SC_P0_HIZ_QUAD_PER_TILE_H11 = 178 +SC_P0_HIZ_QUAD_PER_TILE_H12 = 179 +SC_P0_HIZ_QUAD_PER_TILE_H13 = 180 +SC_P0_HIZ_QUAD_PER_TILE_H14 = 181 +SC_P0_HIZ_QUAD_PER_TILE_H15 = 182 +SC_P0_HIZ_QUAD_PER_TILE_H16 = 183 +SC_PERF_SEL_RESERVED_184 = 184 +SC_PERF_SEL_RESERVED_185 = 185 +SC_PERF_SEL_RESERVED_186 = 186 +SC_PERF_SEL_RESERVED_187 = 187 +SC_PERF_SEL_RESERVED_188 = 188 +SC_PERF_SEL_RESERVED_189 = 189 +SC_PERF_SEL_RESERVED_190 = 190 +SC_PERF_SEL_RESERVED_191 = 191 +SC_PERF_SEL_RESERVED_192 = 192 +SC_PERF_SEL_RESERVED_193 = 193 +SC_PERF_SEL_RESERVED_194 = 194 +SC_PERF_SEL_RESERVED_195 = 195 +SC_PERF_SEL_RESERVED_196 = 196 +SC_PERF_SEL_RESERVED_197 = 197 +SC_PERF_SEL_RESERVED_198 = 198 +SC_PERF_SEL_RESERVED_199 = 199 +SC_PERF_SEL_RESERVED_200 = 200 +SC_PERF_SEL_RESERVED_201 = 201 +SC_PERF_SEL_RESERVED_202 = 202 +SC_PERF_SEL_RESERVED_203 = 203 +SC_PERF_SEL_RESERVED_204 = 204 +SC_PERF_SEL_RESERVED_205 = 205 +SC_PERF_SEL_RESERVED_206 = 206 +SC_PERF_SEL_RESERVED_207 = 207 +SC_PERF_SEL_RESERVED_208 = 208 +SC_PERF_SEL_RESERVED_209 = 209 +SC_PERF_SEL_RESERVED_210 = 210 +SC_PERF_SEL_RESERVED_211 = 211 +SC_PERF_SEL_RESERVED_212 = 212 +SC_PERF_SEL_RESERVED_213 = 213 +SC_PERF_SEL_RESERVED_214 = 214 +SC_PERF_SEL_RESERVED_215 = 215 +SC_PERF_SEL_RESERVED_216 = 216 +SC_PERF_SEL_RESERVED_217 = 217 +SC_PERF_SEL_RESERVED_218 = 218 +SC_PERF_SEL_RESERVED_219 = 219 +SC_PERF_SEL_RESERVED_220 = 220 +SC_PERF_SEL_RESERVED_221 = 221 +SC_PERF_SEL_RESERVED_222 = 222 +SC_PERF_SEL_RESERVED_223 = 223 +SC_PERF_SEL_RESERVED_224 = 224 +SC_PERF_SEL_RESERVED_225 = 225 +SC_PERF_SEL_RESERVED_226 = 226 +SC_PERF_SEL_RESERVED_227 = 227 +SC_PERF_SEL_RESERVED_228 = 228 +SC_PERF_SEL_RESERVED_229 = 229 +SC_PERF_SEL_RESERVED_230 = 230 +SC_PERF_SEL_RESERVED_231 = 231 +SC_PERF_SEL_RESERVED_232 = 232 +SC_PERF_SEL_RESERVED_233 = 233 +SC_PERF_SEL_RESERVED_234 = 234 +SC_P0_HIZ_QUAD_COUNT = 235 +SC_PERF_SEL_RESERVED_236 = 236 +SC_PERF_SEL_RESERVED_237 = 237 +SC_PERF_SEL_RESERVED_238 = 238 +SC_P0_DETAIL_QUAD_COUNT = 239 +SC_PERF_SEL_RESERVED_240 = 240 +SC_PERF_SEL_RESERVED_241 = 241 +SC_PERF_SEL_RESERVED_242 = 242 +SC_P0_DETAIL_QUAD_WITH_1_PIX = 243 +SC_P0_DETAIL_QUAD_WITH_2_PIX = 244 +SC_P0_DETAIL_QUAD_WITH_3_PIX = 245 +SC_P0_DETAIL_QUAD_WITH_4_PIX = 246 +SC_PERF_SEL_RESERVED_247 = 247 +SC_PERF_SEL_RESERVED_248 = 248 +SC_PERF_SEL_RESERVED_249 = 249 +SC_PERF_SEL_RESERVED_250 = 250 +SC_PERF_SEL_RESERVED_251 = 251 +SC_PERF_SEL_RESERVED_252 = 252 +SC_PERF_SEL_RESERVED_253 = 253 +SC_PERF_SEL_RESERVED_254 = 254 +SC_PERF_SEL_RESERVED_255 = 255 +SC_PERF_SEL_RESERVED_256 = 256 +SC_PERF_SEL_RESERVED_257 = 257 +SC_PERF_SEL_RESERVED_258 = 258 +SC_EARLYZ_QUAD_COUNT = 259 +SC_EARLYZ_QUAD_WITH_1_PIX = 260 +SC_EARLYZ_QUAD_WITH_2_PIX = 261 +SC_EARLYZ_QUAD_WITH_3_PIX = 262 +SC_EARLYZ_QUAD_WITH_4_PIX = 263 +SC_PKR_QUAD_PER_ROW_H1 = 264 +SC_PKR_QUAD_PER_ROW_H2 = 265 +SC_PKR_4X2_QUAD_SPLIT = 266 +SC_PKR_4X2_FILL_QUAD = 267 +SC_PKR_END_OF_VECTOR = 268 +SC_PKR_CONTROL_XFER = 269 +SC_PKR_DBHANG_FORCE_EOV = 270 +SC_REG_SCLK_BUSY = 271 +SC_GRP0_DYN_SCLK_BUSY = 272 +SC_GRP1_DYN_SCLK_BUSY = 273 +SC_GRP2_DYN_SCLK_BUSY = 274 +SC_GRP3_DYN_SCLK_BUSY = 275 +SC_GRP4_DYN_SCLK_BUSY = 276 +SC_PA0_SC_DATA_FIFO_RD = 277 +SC_PA0_SC_DATA_FIFO_WE = 278 +SC_PERF_SEL_RESERVED_279 = 279 +SC_PERF_SEL_RESERVED_280 = 280 +SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 281 +SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 282 +SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 283 +SC_PS_ARB_STALLED_FROM_BELOW = 284 +SC_PS_ARB_STARVED_FROM_ABOVE = 285 +SC_PS_ARB_SC_BUSY = 286 +SC_PS_ARB_PA_SC_BUSY = 287 +SC_PERF_SEL_RESERVED_288 = 288 +SC_PERF_SEL_RESERVED_289 = 289 +SC_PERF_SEL_RESERVED_290 = 290 +SC_PERF_SEL_RESERVED_291 = 291 +SC_PA_SC_DEALLOC_2_0_WE = 292 +SC_PERF_SEL_RESERVED_293 = 293 +SC_PERF_SEL_RESERVED_294 = 294 +SC_PERF_SEL_RESERVED_295 = 295 +SC_PERF_SEL_RESERVED_296 = 296 +SC_PERF_SEL_RESERVED_297 = 297 +SC_PERF_SEL_RESERVED_298 = 298 +SC_PERF_SEL_RESERVED_299 = 299 +SC_PA0_SC_EOP_WE = 300 +SC_PERF_SEL_RESERVED_301 = 301 +SC_PA0_SC_EVENT_WE = 302 +SC_PERF_SEL_RESERVED_303 = 303 +SC_PERF_SEL_RESERVED_304 = 304 +SC_PERF_SEL_RESERVED_305 = 305 +SC_PERF_SEL_RESERVED_306 = 306 +SC_PERF_SEL_RESERVED_307 = 307 +SC_PERF_SEL_RESERVED_308 = 308 +SC_PERF_SEL_RESERVED_309 = 309 +SC_PERF_SEL_RESERVED_310 = 310 +SC_PERF_SEL_RESERVED_311 = 311 +SC_PERF_SEL_RESERVED_312 = 312 +SC_PERF_SEL_RESERVED_313 = 313 +SC_PERF_SEL_RESERVED_314 = 314 +SC_PERF_SEL_RESERVED_315 = 315 +SC_PERF_SEL_RESERVED_316 = 316 +SC_PERF_SEL_RESERVED_317 = 317 +SC_PA_SC_FPOV_WE = 318 +SC_PERF_SEL_RESERVED_319 = 319 +SC_PERF_SEL_RESERVED_320 = 320 +SC_PERF_SEL_RESERVED_321 = 321 +SC_PERF_SEL_RESERVED_322 = 322 +SC_PERF_SEL_RESERVED_323 = 323 +SC_PERF_SEL_RESERVED_324 = 324 +SC_PERF_SEL_RESERVED_325 = 325 +SC_SPI_DEALLOC_4_0 = 326 +SC_SPI_DEALLOC_7_5 = 327 +SC_PERF_SEL_RESERVED_328 = 328 +SC_PERF_SEL_RESERVED_329 = 329 +SC_PERF_SEL_RESERVED_330 = 330 +SC_PERF_SEL_RESERVED_331 = 331 +SC_PERF_SEL_RESERVED_332 = 332 +SC_PERF_SEL_RESERVED_333 = 333 +SC_PERF_SEL_RESERVED_334 = 334 +SC_PERF_SEL_RESERVED_335 = 335 +SC_PERF_SEL_RESERVED_336 = 336 +SC_PERF_SEL_RESERVED_337 = 337 +SC_SPI_FPOV_4_0 = 338 +SC_SPI_FPOV_7_5 = 339 +SC_PERF_SEL_RESERVED_340 = 340 +SC_PERF_SEL_RESERVED_341 = 341 +SC_SPI_EVENT = 342 +SC_PS_TS_EVENT_FIFO_PUSH = 343 +SC_PS_TS_EVENT_FIFO_POP = 344 +SC_PS_CTX_DONE_FIFO_PUSH = 345 +SC_PS_CTX_DONE_FIFO_POP = 346 +SC_PERF_SEL_RESERVED_347 = 347 +SC_PERF_SEL_RESERVED_348 = 348 +SC_PA0_SC_NULL_WE = 349 +SC_PA0_SC_NULL_DEALLOC_WE = 350 +SC_PERF_SEL_RESERVED_351 = 351 +SC_PA0_SC_DATA_FIFO_EOP_RD = 352 +SC_PA0_SC_DEALLOC_2_0_RD = 353 +SC_PERF_SEL_RESERVED_354 = 354 +SC_PERF_SEL_RESERVED_355 = 355 +SC_PERF_SEL_RESERVED_356 = 356 +SC_PERF_SEL_RESERVED_357 = 357 +SC_PERF_SEL_RESERVED_358 = 358 +SC_PERF_SEL_RESERVED_359 = 359 +SC_PERF_SEL_RESERVED_360 = 360 +SC_PERF_SEL_RESERVED_361 = 361 +SC_PERF_SEL_RESERVED_362 = 362 +SC_PERF_SEL_RESERVED_363 = 363 +SC_PERF_SEL_RESERVED_364 = 364 +SC_PERF_SEL_RESERVED_365 = 365 +SC_PERF_SEL_RESERVED_366 = 366 +SC_PERF_SEL_RESERVED_367 = 367 +SC_PERF_SEL_RESERVED_368 = 368 +SC_PERF_SEL_RESERVED_369 = 369 +SC_PERF_SEL_RESERVED_370 = 370 +SC_PERF_SEL_RESERVED_371 = 371 +SC_PERF_SEL_RESERVED_372 = 372 +SC_PS_PA0_SC_FIFO_EMPTY = 373 +SC_PS_PA0_SC_FIFO_FULL = 374 +SC_PERF_SEL_RESERVED_375 = 375 +SC_PERF_SEL_RESERVED_376 = 376 +SC_PERF_SEL_RESERVED_377 = 377 +SC_PERF_SEL_RESERVED_378 = 378 +SC_PERF_SEL_RESERVED_379 = 379 +SC_PERF_SEL_RESERVED_380 = 380 +SC_PERF_SEL_RESERVED_381 = 381 +SC_PERF_SEL_RESERVED_382 = 382 +SC_PERF_SEL_RESERVED_383 = 383 +SC_PERF_SEL_RESERVED_384 = 384 +SC_PERF_SEL_RESERVED_385 = 385 +SC_BUSY_CNT_NOT_ZERO = 386 +SC_BM_BUSY = 387 +SC_BACKEND_BUSY = 388 +SC_SCF_SCB_INTERFACE_BUSY = 389 +SC_SCB_BUSY = 390 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 391 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 392 +SC_PBB_BIN_HIST_NUM_PRIMS = 393 +SC_PBB_BATCH_HIST_NUM_PRIMS = 394 +SC_PBB_BIN_HIST_NUM_CONTEXTS = 395 +SC_PBB_BATCH_HIST_NUM_CONTEXTS = 396 +SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 397 +SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 398 +SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 399 +SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 400 +SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 401 +SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 402 +SC_PBB_BUSY = 403 +SC_PBB_BUSY_AND_NO_SENDS = 404 +SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 405 +SC_PBB_NUM_BINS = 406 +SC_PBB_END_OF_BIN = 407 +SC_PBB_END_OF_BATCH = 408 +SC_PBB_PRIMBIN_PROCESSED = 409 +SC_PBB_PRIM_ADDED_TO_BATCH = 410 +SC_PBB_NONBINNED_PRIM = 411 +SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 412 +SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 413 +SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 414 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 415 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 416 +SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 417 +SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 418 +SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 419 +SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 420 +SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 421 +SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 422 +SC_PERF_SEL_RESERVED_423 = 423 +SC_PERF_SEL_RESERVED_424 = 424 +SC_PERF_SEL_RESERVED_425 = 425 +SC_PERF_SEL_RESERVED_426 = 426 +SC_PERF_SEL_RESERVED_427 = 427 +SC_PERF_SEL_RESERVED_428 = 428 +SC_PERF_SEL_RESERVED_429 = 429 +SC_PERF_SEL_RESERVED_430 = 430 +SC_PERF_SEL_RESERVED_431 = 431 +SC_PERF_SEL_RESERVED_432 = 432 +SC_PERF_SEL_RESERVED_433 = 433 +SC_PERF_SEL_RESERVED_434 = 434 +SC_PERF_SEL_RESERVED_435 = 435 +SC_PERF_SEL_RESERVED_436 = 436 +SC_GRP5_DYN_SCLK_BUSY = 437 +SC_GRP6_DYN_SCLK_BUSY = 438 +SC_GRP7_DYN_SCLK_BUSY = 439 +SC_GRP8_DYN_SCLK_BUSY = 440 +SC_GRP9_DYN_SCLK_BUSY = 441 +SC_PS_TO_BE_SCLK_GATE_STALL = 442 +SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 443 +SC_PK_BUSY = 444 +SC_PK_MAX_DEALLOC_FORCE_EOV = 445 +SC_PK_DEALLOC_WAVE_BREAK = 446 +SC_SPI_SEND = 447 +SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 448 +SC_SPI_CREDIT_AT_MAX = 449 +SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 450 +SC_BCI_SEND = 451 +SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 452 +SC_BCI_CREDIT_AT_MAX = 453 +SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 454 +SC_SPIBC_FULL_FREEZE = 455 +SC_PW_BM_PASS_EMPTY_PRIM = 456 +SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 457 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 458 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 459 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 460 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 461 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 462 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 463 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 464 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 465 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 466 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 467 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 468 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 469 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 470 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 471 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 472 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 473 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 474 +SC_DB0_TILE_INTERFACE_BUSY = 475 +SC_DB0_TILE_INTERFACE_SEND = 476 +SC_DB0_TILE_INTERFACE_SEND_EVENT = 477 +SC_PERF_SEL_RESERVED_478 = 478 +SC_PERF_SEL_RESERVED_479 = 479 +SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 480 +SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 481 +SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 482 +SC_PERF_SEL_RESERVED_483 = 483 +SC_PERF_SEL_RESERVED_484 = 484 +SC_PERF_SEL_RESERVED_485 = 485 +SC_PERF_SEL_RESERVED_486 = 486 +SC_PERF_SEL_RESERVED_487 = 487 +SC_PERF_SEL_RESERVED_488 = 488 +SC_PERF_SEL_RESERVED_489 = 489 +SC_PERF_SEL_RESERVED_490 = 490 +SC_BACKEND_PRIM_FIFO_FULL = 491 +SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 492 +SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 493 +SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 494 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 495 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 496 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 497 +SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 498 +SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 499 +SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 500 +SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 501 +SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 502 +SC_STALLED_BY_DB0_TILEFIFO = 503 +SC_DB0_QUAD_INTF_SEND = 504 +SC_DB0_QUAD_INTF_BUSY = 505 +SC_DB0_QUAD_INTF_STALLED_BY_DB = 506 +SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 507 +SC_DB0_QUAD_INTF_IDLE = 508 +SC_PERF_SEL_RESERVED_509 = 509 +SC_PERF_SEL_RESERVED_510 = 510 +SC_PERF_SEL_RESERVED_511 = 511 +SC_PERF_SEL_RESERVED_512 = 512 +SC_PERF_SEL_RESERVED_513 = 513 +SC_PERF_SEL_RESERVED_514 = 514 +SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 515 +SC_PKR_WAVE_BREAK_FULL_TILE = 516 +SC_RESERVED_60 = 517 +SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 518 +SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 519 +SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 520 +SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 521 +SC_DB0_TILE_MASK_FIFO_FULL = 522 +SC_PERF_SEL_RESERVED_523 = 523 +SC_PERF_SEL_RESERVED_524 = 524 +SC_PERF_SEL_RESERVED_525 = 525 +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 526 +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 527 +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 528 +SC_PS_PM_PFF_PW_FULL = 529 +SC_PS_PM_ZFF_PW_FULL = 530 +SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 531 +SC_PERF_SEL_RESERVED_532 = 532 +SC_PERF_SEL_RESERVED_533 = 533 +SC_PERF_SEL_RESERVED_534 = 534 +SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 535 +SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 536 +SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 537 +SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 538 +SC_PERF_SEL_RESERVED_539 = 539 +SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 540 +SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 541 +SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 542 +SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 543 +SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 544 +SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 545 +SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 546 +SC_PK_PM_OREO_CONFLICT_QUAD_FORCE_EOV_WAVE_BRK_1H = 547 +SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 548 +SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 549 +SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 550 +SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 551 +SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 552 +SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 553 +SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 554 +SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 555 +SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 556 +SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 557 +SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 558 +SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 559 +SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 560 +SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 561 +SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 562 +SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 563 +SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 564 +SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 565 +SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 566 +SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 567 +SC_PERF_SEL_RESERVED_568 = 568 +SC_PBB_RESERVED = 569 +SC_BM_BE0_STALLED = 570 +SC_BM_BE1_STALLED = 571 +SC_BM_BE2_STALLED = 572 +SC_BM_BE3_STALLED = 573 +SC_BM_MULTI_ACCUM_1_BE_STALLED = 574 +SC_BM_MULTI_ACCUM_2_BE_STALLED = 575 +SC_BM_MULTI_ACCUM_3_BE_STALLED = 576 +SC_BM_MULTI_ACCUM_4_BE_STALLED = 577 +SC_PBB_READ_PH0 = 578 +SC_PBB_READ_DEALLOC_4_0 = 579 +SC_PBB_READ_DEALLOC_7_5 = 580 +SC_PBB_READ_FPOG_4_0 = 581 +SC_PBB_READ_FPOG_7_5 = 582 +SC_VRC_SECTOR_HIT = 583 +SC_VRC_TAG_MISS = 584 +SC_VRC_SECTOR_MISS = 585 +SC_VRC_LRU_EVICT_STALL = 586 +SC_VRC_LRU_EVICT_SCHEDULED_EVICT_STALL = 587 +SC_VRC_LRU_EVICT_PENDING_EVICT_STALL = 588 +SC_VRC_REEVICTION_STALL = 589 +SC_VRC_EVICT_NONZERO_INFLIGHT_STALL = 590 +SC_VRC_REPLACE_SCHEDULED_EVICT_STALL = 591 +SC_VRC_REPLACE_PENDING_EVICT_STALL = 592 +SC_VRC_REPLACE_FLUSH_IN_PROGRESS_STALL = 593 +SC_VRC_INFLIGHT_COUNTER_MAXIMUM_STALL = 594 +SC_VRC_READ_OUTPUT_STALL = 595 +SC_VRC_WRITE_OUTPUT_STALL = 596 +SC_VRC_ACK_OUTPUT_STALL = 597 +SC_VRC_FLUSH_EVICT_STALL = 598 +SC_VRC_FLUSH_REFLUSH_STALL = 599 +SC_VRC_FLUSH_FIP_HIT_STALL = 600 +SC_VRC_FLUSH_WRREQ_DRAIN_STALL = 601 +SC_VRC_FLUSH_DONE_STALL = 602 +SC_VRC_FLUSH_STALL = 603 +SC_VRC_STALL = 604 +SC_VRC_FLUSH = 605 +SC_VRC_SECTORS_FLUSHED = 606 +SC_VRC_DIRTY_SECTORS_FLUSHED = 607 +SC_VRC_TAGS_FLUSHED = 608 +SC_VRC_HPF_REQ = 609 +SC_VRC_HPF_EVENT = 610 +SC_VRC_HPF_STALLED = 611 +SC_VRC_PROBE_ACK_TILES = 612 +SC_VRC_GL1X_RD_REQ = 613 +SC_VRC_GL1X_WR_REQ = 614 +SC_VRC_GL1X_SRC_XFR = 615 +SC_VRC_GL1X_RD_RET = 616 +SC_VRC_GL1X_WR_ACK = 617 +SC_VRC_GL1X_RD_XNACK = 618 +SC_VRC_GL1X_WR_XNACK = 619 +SC_VRC_GL1X_REQ_STALLED = 620 +SC_VRC_GL1X_SRC_STALLED = 621 +SC_VRC_RATEMEM_WE_CNT = 622 +SC_VRC_RATEMEM_RE_CNT = 623 +SC_VRC_HINTMEM_WE_CNT = 624 +SC_VRC_HINTMEM_RE_CNT = 625 +SC_VRC_BUSY = 626 +SC_GL1X_BUSY = 627 +SC_BE_VRS_RD_REQ = 628 +SC_BE_VRS_RD_REQ_STALLED = 629 +SC_BE_VRS_RD_REQ_HIT = 630 +SC_BE_VRS_RD_RET = 631 +SC_BE_VRS_RD_RET_STALLED = 632 +SC_BE_VRS_FB_RET = 633 +SC_BE_VRS_FB_RET_STALLED = 634 +SC_BE_VRS_FB_RET_HIT = 635 +SC_VRS_BE_BUSY = 636 +SC_PWS_CS_EVENTS_PWS_ENABLE = 637 +SC_PWS_PS_EVENTS_PWS_ENABLE = 638 +SC_PWS_TS_EVENTS_PWS_ENABLE = 639 +SC_PWS_STALLED = 640 +SC_PWS_P0_CS_SYNC_COMPLETE = 641 +SC_PWS_P0_PS_SYNC_COMPLETE = 642 +SC_PWS_P0_TS_SYNC_COMPLETE = 643 +SC_PWS_P1_CS_SYNC_COMPLETE = 644 +SC_PWS_P1_PS_SYNC_COMPLETE = 645 +SC_PWS_P1_TS_SYNC_COMPLETE = 646 +SC_PKR_PC_NO_CREDITS = 647 +SC_PKR_PC_STALLED = 648 +SC_PKR_PC_SEND = 649 +SC_PKR_PC_SEND_PRIM_VALID_1 = 650 +SC_PKR_PC_SEND_PRIM_VALID_0 = 651 +SC_PKR_PC_SEND_TRUE_PRIM = 652 +SC_PKR_PC_SEND_EOV = 653 +SC_PKR_PC_SEND_EVENT = 654 +SC_PKR_DB_WAVE_STALL = 655 +SC_PKR_PSINVOC_SEDC_FIFO_FULL = 656 +SC_PKR_OREO_STALLED_BY_NO_VALID_WAIVE_ID = 657 +SC_PKR_SPI_QUAD_COUNT = 658 +SC_PKR_DB_OREO_WAVE_QUAD_COUNT = 659 +SC_PKR_BCI_QUAD_NEW_PRIM = 660 +SC_SPI_WAVE_STALLED_BY_SPI = 661 +SC_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ScMap' +ScMap__enumvalues = { + 0: 'RASTER_CONFIG_SC_MAP_0', + 1: 'RASTER_CONFIG_SC_MAP_1', + 2: 'RASTER_CONFIG_SC_MAP_2', + 3: 'RASTER_CONFIG_SC_MAP_3', +} +RASTER_CONFIG_SC_MAP_0 = 0 +RASTER_CONFIG_SC_MAP_1 = 1 +RASTER_CONFIG_SC_MAP_2 = 2 +RASTER_CONFIG_SC_MAP_3 = 3 +ScMap = ctypes.c_uint32 # enum + +# values for enumeration 'ScUncertaintyRegionMode' +ScUncertaintyRegionMode__enumvalues = { + 0: 'SC_HALF_LSB', + 1: 'SC_LSB_ONE_SIDED', + 2: 'SC_LSB_TWO_SIDED', +} +SC_HALF_LSB = 0 +SC_LSB_ONE_SIDED = 1 +SC_LSB_TWO_SIDED = 2 +ScUncertaintyRegionMode = ctypes.c_uint32 # enum + +# values for enumeration 'ScUncertaintyRegionMult' +ScUncertaintyRegionMult__enumvalues = { + 0: 'SC_UR_1X', + 1: 'SC_UR_2X', + 2: 'SC_UR_4X', + 3: 'SC_UR_8X', +} +SC_UR_1X = 0 +SC_UR_2X = 1 +SC_UR_4X = 2 +SC_UR_8X = 3 +ScUncertaintyRegionMult = ctypes.c_uint32 # enum + +# values for enumeration 'ScXsel' +ScXsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 +ScXsel = ctypes.c_uint32 # enum + +# values for enumeration 'ScYsel' +ScYsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 +ScYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeMap' +SeMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_MAP_0', + 1: 'RASTER_CONFIG_SE_MAP_1', + 2: 'RASTER_CONFIG_SE_MAP_2', + 3: 'RASTER_CONFIG_SE_MAP_3', +} +RASTER_CONFIG_SE_MAP_0 = 0 +RASTER_CONFIG_SE_MAP_1 = 1 +RASTER_CONFIG_SE_MAP_2 = 2 +RASTER_CONFIG_SE_MAP_3 = 3 +SeMap = ctypes.c_uint32 # enum + +# values for enumeration 'SePairMap' +SePairMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', + 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', + 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', + 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', +} +RASTER_CONFIG_SE_PAIR_MAP_0 = 0 +RASTER_CONFIG_SE_PAIR_MAP_1 = 1 +RASTER_CONFIG_SE_PAIR_MAP_2 = 2 +RASTER_CONFIG_SE_PAIR_MAP_3 = 3 +SePairMap = ctypes.c_uint32 # enum + +# values for enumeration 'SePairXsel' +SePairXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 +SePairXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SePairYsel' +SePairYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 +SePairYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeXsel' +SeXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 +SeXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeYsel' +SeYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 +SeYsel = ctypes.c_uint32 # enum + +# values for enumeration 'VRSCombinerModeSC' +VRSCombinerModeSC__enumvalues = { + 0: 'SC_VRS_COMB_MODE_PASSTHRU', + 1: 'SC_VRS_COMB_MODE_OVERRIDE', + 2: 'SC_VRS_COMB_MODE_MIN', + 3: 'SC_VRS_COMB_MODE_MAX', + 4: 'SC_VRS_COMB_MODE_SATURATE', +} +SC_VRS_COMB_MODE_PASSTHRU = 0 +SC_VRS_COMB_MODE_OVERRIDE = 1 +SC_VRS_COMB_MODE_MIN = 2 +SC_VRS_COMB_MODE_MAX = 3 +SC_VRS_COMB_MODE_SATURATE = 4 +VRSCombinerModeSC = ctypes.c_uint32 # enum + +# values for enumeration 'VRSrate' +VRSrate__enumvalues = { + 0: 'VRS_SHADING_RATE_1X1', + 1: 'VRS_SHADING_RATE_1X2', + 2: 'VRS_SHADING_RATE_UNDEFINED0', + 3: 'VRS_SHADING_RATE_UNDEFINED1', + 4: 'VRS_SHADING_RATE_2X1', + 5: 'VRS_SHADING_RATE_2X2', + 6: 'VRS_SHADING_RATE_2X4', + 7: 'VRS_SHADING_RATE_UNDEFINED2', + 8: 'VRS_SHADING_RATE_UNDEFINED3', + 9: 'VRS_SHADING_RATE_4X2', + 10: 'VRS_SHADING_RATE_4X4', + 11: 'VRS_SHADING_RATE_UNDEFINED4', + 12: 'VRS_SHADING_RATE_16X_SSAA', + 13: 'VRS_SHADING_RATE_8X_SSAA', + 14: 'VRS_SHADING_RATE_4X_SSAA', + 15: 'VRS_SHADING_RATE_2X_SSAA', +} +VRS_SHADING_RATE_1X1 = 0 +VRS_SHADING_RATE_1X2 = 1 +VRS_SHADING_RATE_UNDEFINED0 = 2 +VRS_SHADING_RATE_UNDEFINED1 = 3 +VRS_SHADING_RATE_2X1 = 4 +VRS_SHADING_RATE_2X2 = 5 +VRS_SHADING_RATE_2X4 = 6 +VRS_SHADING_RATE_UNDEFINED2 = 7 +VRS_SHADING_RATE_UNDEFINED3 = 8 +VRS_SHADING_RATE_4X2 = 9 +VRS_SHADING_RATE_4X4 = 10 +VRS_SHADING_RATE_UNDEFINED4 = 11 +VRS_SHADING_RATE_16X_SSAA = 12 +VRS_SHADING_RATE_8X_SSAA = 13 +VRS_SHADING_RATE_4X_SSAA = 14 +VRS_SHADING_RATE_2X_SSAA = 15 +VRSrate = ctypes.c_uint32 # enum + +# values for enumeration 'TC_EA_CID' +TC_EA_CID__enumvalues = { + 0: 'TC_EA_CID_RT', + 1: 'TC_EA_CID_FMASK', + 2: 'TC_EA_CID_DCC', + 3: 'TC_EA_CID_TCPMETA', + 4: 'TC_EA_CID_Z', + 5: 'TC_EA_CID_STENCIL', + 6: 'TC_EA_CID_HTILE', + 7: 'TC_EA_CID_MISC', + 8: 'TC_EA_CID_TCP', + 9: 'TC_EA_CID_SQC', + 10: 'TC_EA_CID_CPF', + 11: 'TC_EA_CID_CPG', + 12: 'TC_EA_CID_IA', + 13: 'TC_EA_CID_WD', + 14: 'TC_EA_CID_PA', + 15: 'TC_EA_CID_UTCL2_TPI', +} +TC_EA_CID_RT = 0 +TC_EA_CID_FMASK = 1 +TC_EA_CID_DCC = 2 +TC_EA_CID_TCPMETA = 3 +TC_EA_CID_Z = 4 +TC_EA_CID_STENCIL = 5 +TC_EA_CID_HTILE = 6 +TC_EA_CID_MISC = 7 +TC_EA_CID_TCP = 8 +TC_EA_CID_SQC = 9 +TC_EA_CID_CPF = 10 +TC_EA_CID_CPG = 11 +TC_EA_CID_IA = 12 +TC_EA_CID_WD = 13 +TC_EA_CID_PA = 14 +TC_EA_CID_UTCL2_TPI = 15 +TC_EA_CID = ctypes.c_uint32 # enum + +# values for enumeration 'TC_NACKS' +TC_NACKS__enumvalues = { + 0: 'TC_NACK_NO_FAULT', + 1: 'TC_NACK_PAGE_FAULT', + 2: 'TC_NACK_PROTECTION_FAULT', + 3: 'TC_NACK_DATA_ERROR', +} +TC_NACK_NO_FAULT = 0 +TC_NACK_PAGE_FAULT = 1 +TC_NACK_PROTECTION_FAULT = 2 +TC_NACK_DATA_ERROR = 3 +TC_NACKS = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP' +TC_OP__enumvalues = { + 0: 'TC_OP_READ', + 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', + 2: 'TC_OP_ATOMIC_FMIN_RTN_32', + 3: 'TC_OP_ATOMIC_FMAX_RTN_32', + 4: 'TC_OP_RESERVED_FOP_RTN_32_0', + 5: 'TC_OP_RESERVED_FADD_RTN_32', + 6: 'TC_OP_RESERVED_FOP_RTN_32_2', + 7: 'TC_OP_ATOMIC_SWAP_RTN_32', + 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', + 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 12: 'TC_OP_PROBE_FILTER', + 13: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 15: 'TC_OP_ATOMIC_ADD_RTN_32', + 16: 'TC_OP_ATOMIC_SUB_RTN_32', + 17: 'TC_OP_ATOMIC_SMIN_RTN_32', + 18: 'TC_OP_ATOMIC_UMIN_RTN_32', + 19: 'TC_OP_ATOMIC_SMAX_RTN_32', + 20: 'TC_OP_ATOMIC_UMAX_RTN_32', + 21: 'TC_OP_ATOMIC_AND_RTN_32', + 22: 'TC_OP_ATOMIC_OR_RTN_32', + 23: 'TC_OP_ATOMIC_XOR_RTN_32', + 24: 'TC_OP_ATOMIC_INC_RTN_32', + 25: 'TC_OP_ATOMIC_DEC_RTN_32', + 26: 'TC_OP_WBINVL1_VOL', + 27: 'TC_OP_WBINVL1_SD', + 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 32: 'TC_OP_WRITE', + 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 34: 'TC_OP_ATOMIC_FMIN_RTN_64', + 35: 'TC_OP_ATOMIC_FMAX_RTN_64', + 36: 'TC_OP_RESERVED_FOP_RTN_64_0', + 37: 'TC_OP_RESERVED_FOP_RTN_64_1', + 38: 'TC_OP_RESERVED_FOP_RTN_64_2', + 39: 'TC_OP_ATOMIC_SWAP_RTN_64', + 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', + 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 44: 'TC_OP_WBINVL2_SD', + 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 47: 'TC_OP_ATOMIC_ADD_RTN_64', + 48: 'TC_OP_ATOMIC_SUB_RTN_64', + 49: 'TC_OP_ATOMIC_SMIN_RTN_64', + 50: 'TC_OP_ATOMIC_UMIN_RTN_64', + 51: 'TC_OP_ATOMIC_SMAX_RTN_64', + 52: 'TC_OP_ATOMIC_UMAX_RTN_64', + 53: 'TC_OP_ATOMIC_AND_RTN_64', + 54: 'TC_OP_ATOMIC_OR_RTN_64', + 55: 'TC_OP_ATOMIC_XOR_RTN_64', + 56: 'TC_OP_ATOMIC_INC_RTN_64', + 57: 'TC_OP_ATOMIC_DEC_RTN_64', + 58: 'TC_OP_WBL2_NC', + 59: 'TC_OP_WBL2_WC', + 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', + 64: 'TC_OP_WBINVL1', + 65: 'TC_OP_ATOMIC_FCMPSWAP_32', + 66: 'TC_OP_ATOMIC_FMIN_32', + 67: 'TC_OP_ATOMIC_FMAX_32', + 68: 'TC_OP_RESERVED_FOP_32_0', + 69: 'TC_OP_RESERVED_FADD_32', + 70: 'TC_OP_RESERVED_FOP_32_2', + 71: 'TC_OP_ATOMIC_SWAP_32', + 72: 'TC_OP_ATOMIC_CMPSWAP_32', + 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 76: 'TC_OP_INV_METADATA', + 77: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 79: 'TC_OP_ATOMIC_ADD_32', + 80: 'TC_OP_ATOMIC_SUB_32', + 81: 'TC_OP_ATOMIC_SMIN_32', + 82: 'TC_OP_ATOMIC_UMIN_32', + 83: 'TC_OP_ATOMIC_SMAX_32', + 84: 'TC_OP_ATOMIC_UMAX_32', + 85: 'TC_OP_ATOMIC_AND_32', + 86: 'TC_OP_ATOMIC_OR_32', + 87: 'TC_OP_ATOMIC_XOR_32', + 88: 'TC_OP_ATOMIC_INC_32', + 89: 'TC_OP_ATOMIC_DEC_32', + 90: 'TC_OP_INVL2_NC', + 91: 'TC_OP_NOP_RTN0', + 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', + 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', + 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', + 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', + 96: 'TC_OP_WBINVL2', + 97: 'TC_OP_ATOMIC_FCMPSWAP_64', + 98: 'TC_OP_ATOMIC_FMIN_64', + 99: 'TC_OP_ATOMIC_FMAX_64', + 100: 'TC_OP_RESERVED_FOP_64_0', + 101: 'TC_OP_RESERVED_FOP_64_1', + 102: 'TC_OP_RESERVED_FOP_64_2', + 103: 'TC_OP_ATOMIC_SWAP_64', + 104: 'TC_OP_ATOMIC_CMPSWAP_64', + 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 111: 'TC_OP_ATOMIC_ADD_64', + 112: 'TC_OP_ATOMIC_SUB_64', + 113: 'TC_OP_ATOMIC_SMIN_64', + 114: 'TC_OP_ATOMIC_UMIN_64', + 115: 'TC_OP_ATOMIC_SMAX_64', + 116: 'TC_OP_ATOMIC_UMAX_64', + 117: 'TC_OP_ATOMIC_AND_64', + 118: 'TC_OP_ATOMIC_OR_64', + 119: 'TC_OP_ATOMIC_XOR_64', + 120: 'TC_OP_ATOMIC_INC_64', + 121: 'TC_OP_ATOMIC_DEC_64', + 122: 'TC_OP_WBINVL2_NC', + 123: 'TC_OP_NOP_ACK', + 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', + 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', + 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', + 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', +} +TC_OP_READ = 0 +TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 +TC_OP_ATOMIC_FMIN_RTN_32 = 2 +TC_OP_ATOMIC_FMAX_RTN_32 = 3 +TC_OP_RESERVED_FOP_RTN_32_0 = 4 +TC_OP_RESERVED_FADD_RTN_32 = 5 +TC_OP_RESERVED_FOP_RTN_32_2 = 6 +TC_OP_ATOMIC_SWAP_RTN_32 = 7 +TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 +TC_OP_PROBE_FILTER = 12 +TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 +TC_OP_ATOMIC_ADD_RTN_32 = 15 +TC_OP_ATOMIC_SUB_RTN_32 = 16 +TC_OP_ATOMIC_SMIN_RTN_32 = 17 +TC_OP_ATOMIC_UMIN_RTN_32 = 18 +TC_OP_ATOMIC_SMAX_RTN_32 = 19 +TC_OP_ATOMIC_UMAX_RTN_32 = 20 +TC_OP_ATOMIC_AND_RTN_32 = 21 +TC_OP_ATOMIC_OR_RTN_32 = 22 +TC_OP_ATOMIC_XOR_RTN_32 = 23 +TC_OP_ATOMIC_INC_RTN_32 = 24 +TC_OP_ATOMIC_DEC_RTN_32 = 25 +TC_OP_WBINVL1_VOL = 26 +TC_OP_WBINVL1_SD = 27 +TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 +TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 +TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 +TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 +TC_OP_WRITE = 32 +TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 +TC_OP_ATOMIC_FMIN_RTN_64 = 34 +TC_OP_ATOMIC_FMAX_RTN_64 = 35 +TC_OP_RESERVED_FOP_RTN_64_0 = 36 +TC_OP_RESERVED_FOP_RTN_64_1 = 37 +TC_OP_RESERVED_FOP_RTN_64_2 = 38 +TC_OP_ATOMIC_SWAP_RTN_64 = 39 +TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 +TC_OP_WBINVL2_SD = 44 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 +TC_OP_ATOMIC_ADD_RTN_64 = 47 +TC_OP_ATOMIC_SUB_RTN_64 = 48 +TC_OP_ATOMIC_SMIN_RTN_64 = 49 +TC_OP_ATOMIC_UMIN_RTN_64 = 50 +TC_OP_ATOMIC_SMAX_RTN_64 = 51 +TC_OP_ATOMIC_UMAX_RTN_64 = 52 +TC_OP_ATOMIC_AND_RTN_64 = 53 +TC_OP_ATOMIC_OR_RTN_64 = 54 +TC_OP_ATOMIC_XOR_RTN_64 = 55 +TC_OP_ATOMIC_INC_RTN_64 = 56 +TC_OP_ATOMIC_DEC_RTN_64 = 57 +TC_OP_WBL2_NC = 58 +TC_OP_WBL2_WC = 59 +TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 +TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 +TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 +TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 +TC_OP_WBINVL1 = 64 +TC_OP_ATOMIC_FCMPSWAP_32 = 65 +TC_OP_ATOMIC_FMIN_32 = 66 +TC_OP_ATOMIC_FMAX_32 = 67 +TC_OP_RESERVED_FOP_32_0 = 68 +TC_OP_RESERVED_FADD_32 = 69 +TC_OP_RESERVED_FOP_32_2 = 70 +TC_OP_ATOMIC_SWAP_32 = 71 +TC_OP_ATOMIC_CMPSWAP_32 = 72 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 +TC_OP_INV_METADATA = 76 +TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 +TC_OP_ATOMIC_ADD_32 = 79 +TC_OP_ATOMIC_SUB_32 = 80 +TC_OP_ATOMIC_SMIN_32 = 81 +TC_OP_ATOMIC_UMIN_32 = 82 +TC_OP_ATOMIC_SMAX_32 = 83 +TC_OP_ATOMIC_UMAX_32 = 84 +TC_OP_ATOMIC_AND_32 = 85 +TC_OP_ATOMIC_OR_32 = 86 +TC_OP_ATOMIC_XOR_32 = 87 +TC_OP_ATOMIC_INC_32 = 88 +TC_OP_ATOMIC_DEC_32 = 89 +TC_OP_INVL2_NC = 90 +TC_OP_NOP_RTN0 = 91 +TC_OP_RESERVED_NON_FLOAT_32_1 = 92 +TC_OP_RESERVED_NON_FLOAT_32_2 = 93 +TC_OP_RESERVED_NON_FLOAT_32_3 = 94 +TC_OP_RESERVED_NON_FLOAT_32_4 = 95 +TC_OP_WBINVL2 = 96 +TC_OP_ATOMIC_FCMPSWAP_64 = 97 +TC_OP_ATOMIC_FMIN_64 = 98 +TC_OP_ATOMIC_FMAX_64 = 99 +TC_OP_RESERVED_FOP_64_0 = 100 +TC_OP_RESERVED_FOP_64_1 = 101 +TC_OP_RESERVED_FOP_64_2 = 102 +TC_OP_ATOMIC_SWAP_64 = 103 +TC_OP_ATOMIC_CMPSWAP_64 = 104 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 +TC_OP_ATOMIC_ADD_64 = 111 +TC_OP_ATOMIC_SUB_64 = 112 +TC_OP_ATOMIC_SMIN_64 = 113 +TC_OP_ATOMIC_UMIN_64 = 114 +TC_OP_ATOMIC_SMAX_64 = 115 +TC_OP_ATOMIC_UMAX_64 = 116 +TC_OP_ATOMIC_AND_64 = 117 +TC_OP_ATOMIC_OR_64 = 118 +TC_OP_ATOMIC_XOR_64 = 119 +TC_OP_ATOMIC_INC_64 = 120 +TC_OP_ATOMIC_DEC_64 = 121 +TC_OP_WBINVL2_NC = 122 +TC_OP_NOP_ACK = 123 +TC_OP_RESERVED_NON_FLOAT_64_1 = 124 +TC_OP_RESERVED_NON_FLOAT_64_2 = 125 +TC_OP_RESERVED_NON_FLOAT_64_3 = 126 +TC_OP_RESERVED_NON_FLOAT_64_4 = 127 +TC_OP = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP_MASKS' +TC_OP_MASKS__enumvalues = { + 8: 'TC_OP_MASK_FLUSH_DENROM', + 32: 'TC_OP_MASK_64', + 64: 'TC_OP_MASK_NO_RTN', +} +TC_OP_MASK_FLUSH_DENROM = 8 +TC_OP_MASK_64 = 32 +TC_OP_MASK_NO_RTN = 64 +TC_OP_MASKS = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_BASE_MODE' +CLKGATE_BASE_MODE__enumvalues = { + 0: 'MULT_8', + 1: 'MULT_16', +} +MULT_8 = 0 +MULT_16 = 1 +CLKGATE_BASE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_SM_MODE' +CLKGATE_SM_MODE__enumvalues = { + 0: 'ON_SEQ', + 1: 'OFF_SEQ', + 2: 'PROG_SEQ', + 3: 'READ_SEQ', + 4: 'SM_MODE_RESERVED', +} +ON_SEQ = 0 +OFF_SEQ = 1 +PROG_SEQ = 2 +READ_SEQ = 3 +SM_MODE_RESERVED = 4 +CLKGATE_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CovToShaderSel' +CovToShaderSel__enumvalues = { + 0: 'INPUT_COVERAGE', + 1: 'INPUT_INNER_COVERAGE', + 2: 'INPUT_DEPTH_COVERAGE', + 3: 'RAW', +} +INPUT_COVERAGE = 0 +INPUT_INNER_COVERAGE = 1 +INPUT_DEPTH_COVERAGE = 2 +RAW = 3 +CovToShaderSel = ctypes.c_uint32 # enum + +# values for enumeration 'PC_PERFCNT_SEL' +PC_PERFCNT_SEL__enumvalues = { + 0: 'PC_PERF_SC_PC_PTR_SEND0', + 1: 'PC_PERF_SC_PC_PTR_VALID0', + 2: 'PC_PERF_SC_FPOSG0', + 3: 'PC_PERF_SC_FPOSG_WAIT0', + 4: 'PC_PERF_SC_WAIT_SYNC0', + 5: 'PC_PERF_SC_PQ_FREEZE0', + 6: 'PC_PERF_PKR0_FPOSG_EQ1', + 7: 'PC_PERF_PKR0_FPOSG_GT1', + 8: 'PC_PERF_PKR0_FPOSG_GT16', + 9: 'PC_PERF_PKR0_FPOSG_GT64', + 10: 'PC_PERF_PKR0_FPOSG_GT128', + 11: 'PC_PERF_PKR0_FPOSG_OUT_OF_WAVE', + 12: 'PC_PERF_PKR0_NUM_PROBES', + 13: 'PC_PERF_PKR0_PRIMS_PER_PROBE_EQ1', + 14: 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT1', + 15: 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT2', + 16: 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT4', + 17: 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT8', + 18: 'PC_PERF_PKR0_NUM_WAVES', + 19: 'PC_PERF_PKR0_PRIMS_PER_WAVE_EQ1', + 20: 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT1', + 21: 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT2', + 22: 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT4', + 23: 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT8', + 24: 'PC_PERF_PKR0_PROBES_PER_WAVE_EQ1', + 25: 'PC_PERF_PKR0_PROBES_PER_WAVE_GT1', + 26: 'PC_PERF_PKR0_PROBES_PER_WAVE_GT2', + 27: 'PC_PERF_PKR0_PROBES_PER_WAVE_GT4', + 28: 'PC_PERF_PKR0_PROBES_PER_WAVE_GT8', + 29: 'PC_PERF_PKR0_PRIMS_REUSE', + 30: 'PC_PERF_SC_PC_PTR_SEND1', + 31: 'PC_PERF_SC_PC_PTR_VALID1', + 32: 'PC_PERF_SC_FPOSG1', + 33: 'PC_PERF_SC_FPOSG_WAIT1', + 34: 'PC_PERF_SC_WAIT_SYNC1', + 35: 'PC_PERF_SC_PQ_FREEZE1', + 36: 'PC_PERF_PKR1_FPOSG_EQ1', + 37: 'PC_PERF_PKR1_FPOSG_GT1', + 38: 'PC_PERF_PKR1_FPOSG_GT16', + 39: 'PC_PERF_PKR1_FPOSG_GT64', + 40: 'PC_PERF_PKR1_FPOSG_GT128', + 41: 'PC_PERF_PKR1_FPOSG_OUT_OF_WAVE', + 42: 'PC_PERF_PKR1_NUM_PROBES', + 43: 'PC_PERF_PKR1_PRIMS_PER_PROBE_EQ1', + 44: 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT1', + 45: 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT2', + 46: 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT4', + 47: 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT8', + 48: 'PC_PERF_PKR1_NUM_WAVES', + 49: 'PC_PERF_PKR1_PRIMS_PER_WAVE_EQ1', + 50: 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT1', + 51: 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT2', + 52: 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT4', + 53: 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT8', + 54: 'PC_PERF_PKR1_PROBES_PER_WAVE_EQ1', + 55: 'PC_PERF_PKR1_PROBES_PER_WAVE_GT1', + 56: 'PC_PERF_PKR1_PROBES_PER_WAVE_GT2', + 57: 'PC_PERF_PKR1_PROBES_PER_WAVE_GT4', + 58: 'PC_PERF_PKR1_PROBES_PER_WAVE_GT8', + 59: 'PC_PERF_PKR1_PRIMS_REUSE', + 60: 'PC_PERF_SC_PC_PTR_SEND2', + 61: 'PC_PERF_SC_PC_PTR_VALID2', + 62: 'PC_PERF_SC_FPOSG2', + 63: 'PC_PERF_SC_FPOSG_WAIT2', + 64: 'PC_PERF_SC_WAIT_SYNC2', + 65: 'PC_PERF_SC_PQ_FREEZE2', + 66: 'PC_PERF_PKR2_FPOSG_EQ1', + 67: 'PC_PERF_PKR2_FPOSG_GT1', + 68: 'PC_PERF_PKR2_FPOSG_GT16', + 69: 'PC_PERF_PKR2_FPOSG_GT64', + 70: 'PC_PERF_PKR2_FPOSG_GT128', + 71: 'PC_PERF_PKR2_FPOSG_OUT_OF_WAVE', + 72: 'PC_PERF_PKR2_NUM_PROBES', + 73: 'PC_PERF_PKR2_PRIMS_PER_PROBE_EQ1', + 74: 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT1', + 75: 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT2', + 76: 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT4', + 77: 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT8', + 78: 'PC_PERF_PKR2_NUM_WAVES', + 79: 'PC_PERF_PKR2_PRIMS_PER_WAVE_EQ1', + 80: 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT1', + 81: 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT2', + 82: 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT4', + 83: 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT8', + 84: 'PC_PERF_PKR2_PROBES_PER_WAVE_EQ1', + 85: 'PC_PERF_PKR2_PROBES_PER_WAVE_GT1', + 86: 'PC_PERF_PKR2_PROBES_PER_WAVE_GT2', + 87: 'PC_PERF_PKR2_PROBES_PER_WAVE_GT4', + 88: 'PC_PERF_PKR2_PROBES_PER_WAVE_GT8', + 89: 'PC_PERF_PKR2_PRIMS_REUSE', + 90: 'PC_PERF_SC_PC_PTR_SEND3', + 91: 'PC_PERF_SC_PC_PTR_VALID3', + 92: 'PC_PERF_SC_FPOSG3', + 93: 'PC_PERF_SC_FPOSG_WAIT3', + 94: 'PC_PERF_SC_WAIT_SYNC3', + 95: 'PC_PERF_SC_PQ_FREEZE3', + 96: 'PC_PERF_PKR3_FPOSG_EQ1', + 97: 'PC_PERF_PKR3_FPOSG_GT1', + 98: 'PC_PERF_PKR3_FPOSG_GT16', + 99: 'PC_PERF_PKR3_FPOSG_GT64', + 100: 'PC_PERF_PKR3_FPOSG_GT128', + 101: 'PC_PERF_PKR3_FPOSG_OUT_OF_WAVE', + 102: 'PC_PERF_PKR3_NUM_PROBES', + 103: 'PC_PERF_PKR3_PRIMS_PER_PROBE_EQ1', + 104: 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT1', + 105: 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT2', + 106: 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT4', + 107: 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT8', + 108: 'PC_PERF_PKR3_NUM_WAVES', + 109: 'PC_PERF_PKR3_PRIMS_PER_WAVE_EQ1', + 110: 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT1', + 111: 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT2', + 112: 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT4', + 113: 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT8', + 114: 'PC_PERF_PKR3_PROBES_PER_WAVE_EQ1', + 115: 'PC_PERF_PKR3_PROBES_PER_WAVE_GT1', + 116: 'PC_PERF_PKR3_PROBES_PER_WAVE_GT2', + 117: 'PC_PERF_PKR3_PROBES_PER_WAVE_GT4', + 118: 'PC_PERF_PKR3_PROBES_PER_WAVE_GT8', + 119: 'PC_PERF_PKR3_PRIMS_REUSE', + 120: 'PC_PERF_SC_MW_FREEZE', + 121: 'PC_PERF_SC_NUM_PROBES', + 122: 'PC_PERF_SC_NUM_WAVES', + 123: 'PC_PERF_SC_NUM_SPLIT_WAVES', + 124: 'PC_PERF_GE_GSDONE', + 125: 'PC_PERF_PKR0_GSDONE_WHILE_IDLE', + 126: 'PC_PERF_PKR1_GSDONE_WHILE_IDLE', + 127: 'PC_PERF_PKR2_GSDONE_WHILE_IDLE', + 128: 'PC_PERF_PKR3_GSDONE_WHILE_IDLE', + 129: 'PC_PERF_PC_SPI_PROBE_FREEZE', + 130: 'PC_PERF_PC_SPI_PROBE_OUT_OF_CREDIT', + 131: 'PC_PERF_MW_RTN_ADDR_FREEZE', + 132: 'PC_PERF_MW_PROBE_CNT_FREEZE', + 133: 'PC_PERF_MW_GL1H_REQ_FREEZE', + 134: 'PC_PERF_MW_GL1H_NUM_REQS', + 135: 'PC_PERF_MW_DLINE_ALLOC', + 136: 'PC_PERF_MW_DLINE_DEALLOC', + 137: 'PC_PERF_MW_TAGLINE_ALLOC', + 138: 'PC_PERF_MW_TAGLINE_DEALLOC', + 139: 'PC_PERF_MW_PHY_DLINE_FULL_STALL', + 140: 'PC_PERF_MW_CACHE_CNTL_FULL_STALL', + 141: 'PC_PERF_MW_STAMP_LIMIT_STALL', + 142: 'PC_PERF_MW_CACHE_MISS', + 143: 'PC_PERF_MW_CACHE_HIT', + 144: 'PC_PERF_MW_CACHE_REUSE', + 145: 'PC_PERF_MW_DEALLOC_HIT', + 146: 'PC_PERF_PC_MEM_BANK_CONF0', + 147: 'PC_PERF_PC_MEM_BANK_CONF1', + 148: 'PC_PERF_PC_LDS_VERTEX_REUSE0', + 149: 'PC_PERF_PC_LDS_CNTL_VALID0', + 150: 'PC_PERF_PC_LDS_VERTEX_REUSE1', + 151: 'PC_PERF_PC_LDS_CNTL_VALID1', + 152: 'PC_PERF_GRBM_BUSY', + 153: 'PC_PERF_GL1_RTN_CNT_GTE1', + 154: 'PC_PERF_GL1_RTN_CNT_GT512', + 155: 'PC_PERF_GL1_RTN_CNT_GT768', + 156: 'PC_PERF_LWC0_PROBE_ORDER_STALL', + 157: 'PC_PERF_LWC0_PC_MEM_READ_STALL', + 158: 'PC_PERF_LWC0_PKR2_SA_BDRY_CROSSING', + 159: 'PC_PERF_LWC0_PKR3_SA_BDRY_CROSSING', + 160: 'PC_PERF_LWC1_PROBE_ORDER_STALL', + 161: 'PC_PERF_LWC1_PC_MEM_READ_STALL', + 162: 'PC_PERF_LWC1_PKR0_SA_BDRY_CROSSING', + 163: 'PC_PERF_LWC1_PKR1_SA_BDRY_CROSSING', + 164: 'PC_PERF_NUM_PSWAVE', +} +PC_PERF_SC_PC_PTR_SEND0 = 0 +PC_PERF_SC_PC_PTR_VALID0 = 1 +PC_PERF_SC_FPOSG0 = 2 +PC_PERF_SC_FPOSG_WAIT0 = 3 +PC_PERF_SC_WAIT_SYNC0 = 4 +PC_PERF_SC_PQ_FREEZE0 = 5 +PC_PERF_PKR0_FPOSG_EQ1 = 6 +PC_PERF_PKR0_FPOSG_GT1 = 7 +PC_PERF_PKR0_FPOSG_GT16 = 8 +PC_PERF_PKR0_FPOSG_GT64 = 9 +PC_PERF_PKR0_FPOSG_GT128 = 10 +PC_PERF_PKR0_FPOSG_OUT_OF_WAVE = 11 +PC_PERF_PKR0_NUM_PROBES = 12 +PC_PERF_PKR0_PRIMS_PER_PROBE_EQ1 = 13 +PC_PERF_PKR0_PRIMS_PER_PROBE_GT1 = 14 +PC_PERF_PKR0_PRIMS_PER_PROBE_GT2 = 15 +PC_PERF_PKR0_PRIMS_PER_PROBE_GT4 = 16 +PC_PERF_PKR0_PRIMS_PER_PROBE_GT8 = 17 +PC_PERF_PKR0_NUM_WAVES = 18 +PC_PERF_PKR0_PRIMS_PER_WAVE_EQ1 = 19 +PC_PERF_PKR0_PRIMS_PER_WAVE_GT1 = 20 +PC_PERF_PKR0_PRIMS_PER_WAVE_GT2 = 21 +PC_PERF_PKR0_PRIMS_PER_WAVE_GT4 = 22 +PC_PERF_PKR0_PRIMS_PER_WAVE_GT8 = 23 +PC_PERF_PKR0_PROBES_PER_WAVE_EQ1 = 24 +PC_PERF_PKR0_PROBES_PER_WAVE_GT1 = 25 +PC_PERF_PKR0_PROBES_PER_WAVE_GT2 = 26 +PC_PERF_PKR0_PROBES_PER_WAVE_GT4 = 27 +PC_PERF_PKR0_PROBES_PER_WAVE_GT8 = 28 +PC_PERF_PKR0_PRIMS_REUSE = 29 +PC_PERF_SC_PC_PTR_SEND1 = 30 +PC_PERF_SC_PC_PTR_VALID1 = 31 +PC_PERF_SC_FPOSG1 = 32 +PC_PERF_SC_FPOSG_WAIT1 = 33 +PC_PERF_SC_WAIT_SYNC1 = 34 +PC_PERF_SC_PQ_FREEZE1 = 35 +PC_PERF_PKR1_FPOSG_EQ1 = 36 +PC_PERF_PKR1_FPOSG_GT1 = 37 +PC_PERF_PKR1_FPOSG_GT16 = 38 +PC_PERF_PKR1_FPOSG_GT64 = 39 +PC_PERF_PKR1_FPOSG_GT128 = 40 +PC_PERF_PKR1_FPOSG_OUT_OF_WAVE = 41 +PC_PERF_PKR1_NUM_PROBES = 42 +PC_PERF_PKR1_PRIMS_PER_PROBE_EQ1 = 43 +PC_PERF_PKR1_PRIMS_PER_PROBE_GT1 = 44 +PC_PERF_PKR1_PRIMS_PER_PROBE_GT2 = 45 +PC_PERF_PKR1_PRIMS_PER_PROBE_GT4 = 46 +PC_PERF_PKR1_PRIMS_PER_PROBE_GT8 = 47 +PC_PERF_PKR1_NUM_WAVES = 48 +PC_PERF_PKR1_PRIMS_PER_WAVE_EQ1 = 49 +PC_PERF_PKR1_PRIMS_PER_WAVE_GT1 = 50 +PC_PERF_PKR1_PRIMS_PER_WAVE_GT2 = 51 +PC_PERF_PKR1_PRIMS_PER_WAVE_GT4 = 52 +PC_PERF_PKR1_PRIMS_PER_WAVE_GT8 = 53 +PC_PERF_PKR1_PROBES_PER_WAVE_EQ1 = 54 +PC_PERF_PKR1_PROBES_PER_WAVE_GT1 = 55 +PC_PERF_PKR1_PROBES_PER_WAVE_GT2 = 56 +PC_PERF_PKR1_PROBES_PER_WAVE_GT4 = 57 +PC_PERF_PKR1_PROBES_PER_WAVE_GT8 = 58 +PC_PERF_PKR1_PRIMS_REUSE = 59 +PC_PERF_SC_PC_PTR_SEND2 = 60 +PC_PERF_SC_PC_PTR_VALID2 = 61 +PC_PERF_SC_FPOSG2 = 62 +PC_PERF_SC_FPOSG_WAIT2 = 63 +PC_PERF_SC_WAIT_SYNC2 = 64 +PC_PERF_SC_PQ_FREEZE2 = 65 +PC_PERF_PKR2_FPOSG_EQ1 = 66 +PC_PERF_PKR2_FPOSG_GT1 = 67 +PC_PERF_PKR2_FPOSG_GT16 = 68 +PC_PERF_PKR2_FPOSG_GT64 = 69 +PC_PERF_PKR2_FPOSG_GT128 = 70 +PC_PERF_PKR2_FPOSG_OUT_OF_WAVE = 71 +PC_PERF_PKR2_NUM_PROBES = 72 +PC_PERF_PKR2_PRIMS_PER_PROBE_EQ1 = 73 +PC_PERF_PKR2_PRIMS_PER_PROBE_GT1 = 74 +PC_PERF_PKR2_PRIMS_PER_PROBE_GT2 = 75 +PC_PERF_PKR2_PRIMS_PER_PROBE_GT4 = 76 +PC_PERF_PKR2_PRIMS_PER_PROBE_GT8 = 77 +PC_PERF_PKR2_NUM_WAVES = 78 +PC_PERF_PKR2_PRIMS_PER_WAVE_EQ1 = 79 +PC_PERF_PKR2_PRIMS_PER_WAVE_GT1 = 80 +PC_PERF_PKR2_PRIMS_PER_WAVE_GT2 = 81 +PC_PERF_PKR2_PRIMS_PER_WAVE_GT4 = 82 +PC_PERF_PKR2_PRIMS_PER_WAVE_GT8 = 83 +PC_PERF_PKR2_PROBES_PER_WAVE_EQ1 = 84 +PC_PERF_PKR2_PROBES_PER_WAVE_GT1 = 85 +PC_PERF_PKR2_PROBES_PER_WAVE_GT2 = 86 +PC_PERF_PKR2_PROBES_PER_WAVE_GT4 = 87 +PC_PERF_PKR2_PROBES_PER_WAVE_GT8 = 88 +PC_PERF_PKR2_PRIMS_REUSE = 89 +PC_PERF_SC_PC_PTR_SEND3 = 90 +PC_PERF_SC_PC_PTR_VALID3 = 91 +PC_PERF_SC_FPOSG3 = 92 +PC_PERF_SC_FPOSG_WAIT3 = 93 +PC_PERF_SC_WAIT_SYNC3 = 94 +PC_PERF_SC_PQ_FREEZE3 = 95 +PC_PERF_PKR3_FPOSG_EQ1 = 96 +PC_PERF_PKR3_FPOSG_GT1 = 97 +PC_PERF_PKR3_FPOSG_GT16 = 98 +PC_PERF_PKR3_FPOSG_GT64 = 99 +PC_PERF_PKR3_FPOSG_GT128 = 100 +PC_PERF_PKR3_FPOSG_OUT_OF_WAVE = 101 +PC_PERF_PKR3_NUM_PROBES = 102 +PC_PERF_PKR3_PRIMS_PER_PROBE_EQ1 = 103 +PC_PERF_PKR3_PRIMS_PER_PROBE_GT1 = 104 +PC_PERF_PKR3_PRIMS_PER_PROBE_GT2 = 105 +PC_PERF_PKR3_PRIMS_PER_PROBE_GT4 = 106 +PC_PERF_PKR3_PRIMS_PER_PROBE_GT8 = 107 +PC_PERF_PKR3_NUM_WAVES = 108 +PC_PERF_PKR3_PRIMS_PER_WAVE_EQ1 = 109 +PC_PERF_PKR3_PRIMS_PER_WAVE_GT1 = 110 +PC_PERF_PKR3_PRIMS_PER_WAVE_GT2 = 111 +PC_PERF_PKR3_PRIMS_PER_WAVE_GT4 = 112 +PC_PERF_PKR3_PRIMS_PER_WAVE_GT8 = 113 +PC_PERF_PKR3_PROBES_PER_WAVE_EQ1 = 114 +PC_PERF_PKR3_PROBES_PER_WAVE_GT1 = 115 +PC_PERF_PKR3_PROBES_PER_WAVE_GT2 = 116 +PC_PERF_PKR3_PROBES_PER_WAVE_GT4 = 117 +PC_PERF_PKR3_PROBES_PER_WAVE_GT8 = 118 +PC_PERF_PKR3_PRIMS_REUSE = 119 +PC_PERF_SC_MW_FREEZE = 120 +PC_PERF_SC_NUM_PROBES = 121 +PC_PERF_SC_NUM_WAVES = 122 +PC_PERF_SC_NUM_SPLIT_WAVES = 123 +PC_PERF_GE_GSDONE = 124 +PC_PERF_PKR0_GSDONE_WHILE_IDLE = 125 +PC_PERF_PKR1_GSDONE_WHILE_IDLE = 126 +PC_PERF_PKR2_GSDONE_WHILE_IDLE = 127 +PC_PERF_PKR3_GSDONE_WHILE_IDLE = 128 +PC_PERF_PC_SPI_PROBE_FREEZE = 129 +PC_PERF_PC_SPI_PROBE_OUT_OF_CREDIT = 130 +PC_PERF_MW_RTN_ADDR_FREEZE = 131 +PC_PERF_MW_PROBE_CNT_FREEZE = 132 +PC_PERF_MW_GL1H_REQ_FREEZE = 133 +PC_PERF_MW_GL1H_NUM_REQS = 134 +PC_PERF_MW_DLINE_ALLOC = 135 +PC_PERF_MW_DLINE_DEALLOC = 136 +PC_PERF_MW_TAGLINE_ALLOC = 137 +PC_PERF_MW_TAGLINE_DEALLOC = 138 +PC_PERF_MW_PHY_DLINE_FULL_STALL = 139 +PC_PERF_MW_CACHE_CNTL_FULL_STALL = 140 +PC_PERF_MW_STAMP_LIMIT_STALL = 141 +PC_PERF_MW_CACHE_MISS = 142 +PC_PERF_MW_CACHE_HIT = 143 +PC_PERF_MW_CACHE_REUSE = 144 +PC_PERF_MW_DEALLOC_HIT = 145 +PC_PERF_PC_MEM_BANK_CONF0 = 146 +PC_PERF_PC_MEM_BANK_CONF1 = 147 +PC_PERF_PC_LDS_VERTEX_REUSE0 = 148 +PC_PERF_PC_LDS_CNTL_VALID0 = 149 +PC_PERF_PC_LDS_VERTEX_REUSE1 = 150 +PC_PERF_PC_LDS_CNTL_VALID1 = 151 +PC_PERF_GRBM_BUSY = 152 +PC_PERF_GL1_RTN_CNT_GTE1 = 153 +PC_PERF_GL1_RTN_CNT_GT512 = 154 +PC_PERF_GL1_RTN_CNT_GT768 = 155 +PC_PERF_LWC0_PROBE_ORDER_STALL = 156 +PC_PERF_LWC0_PC_MEM_READ_STALL = 157 +PC_PERF_LWC0_PKR2_SA_BDRY_CROSSING = 158 +PC_PERF_LWC0_PKR3_SA_BDRY_CROSSING = 159 +PC_PERF_LWC1_PROBE_ORDER_STALL = 160 +PC_PERF_LWC1_PC_MEM_READ_STALL = 161 +PC_PERF_LWC1_PKR0_SA_BDRY_CROSSING = 162 +PC_PERF_LWC1_PKR1_SA_BDRY_CROSSING = 163 +PC_PERF_NUM_PSWAVE = 164 +PC_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_FOG_MODE' +SPI_FOG_MODE__enumvalues = { + 0: 'SPI_FOG_NONE', + 1: 'SPI_FOG_EXP', + 2: 'SPI_FOG_EXP2', + 3: 'SPI_FOG_LINEAR', +} +SPI_FOG_NONE = 0 +SPI_FOG_EXP = 1 +SPI_FOG_EXP2 = 2 +SPI_FOG_LINEAR = 3 +SPI_FOG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_LB_WAVES_SELECT' +SPI_LB_WAVES_SELECT__enumvalues = { + 0: 'HS_GS', + 1: 'PS', + 2: 'CS_NA', + 3: 'SPI_LB_WAVES_RSVD', +} +HS_GS = 0 +PS = 1 +CS_NA = 2 +SPI_LB_WAVES_RSVD = 3 +SPI_LB_WAVES_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PERFCNT_SEL' +SPI_PERFCNT_SEL__enumvalues = { + 1: 'SPI_PERF_GS_WINDOW_VALID', + 2: 'SPI_PERF_GS_BUSY', + 3: 'SPI_PERF_GS_CRAWLER_STALL', + 4: 'SPI_PERF_GS_EVENT_WAVE', + 5: 'SPI_PERF_GS_WAVE', + 6: 'SPI_PERF_GS_PERS_UPD_FULL0', + 7: 'SPI_PERF_GS_PERS_UPD_FULL1', + 8: 'SPI_PERF_GS_FIRST_SUBGRP', + 9: 'SPI_PERF_GS_HS_DEALLOC', + 10: 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', + 11: 'SPI_PERF_GS_POS0_STALL', + 12: 'SPI_PERF_GS_POS1_STALL', + 13: 'SPI_PERF_GS_INDX0_STALL', + 14: 'SPI_PERF_GS_INDX1_STALL', + 15: 'SPI_PERF_GS_PWS_STALL', + 16: 'SPI_PERF_GS_GRP_LIFETIME', + 17: 'SPI_PERF_GS_WAVE_IN_FLIGHT', + 18: 'SPI_PERF_GS_GRP_LIFETIME_SAMPLE', + 21: 'SPI_PERF_HS_WINDOW_VALID', + 22: 'SPI_PERF_HS_BUSY', + 23: 'SPI_PERF_HS_CRAWLER_STALL', + 24: 'SPI_PERF_HS_FIRST_WAVE', + 26: 'SPI_PERF_HS_EVENT_WAVE', + 27: 'SPI_PERF_HS_WAVE', + 28: 'SPI_PERF_HS_PERS_UPD_FULL0', + 29: 'SPI_PERF_HS_PERS_UPD_FULL1', + 30: 'SPI_PERF_HS_PWS_STALL', + 31: 'SPI_PERF_HS_WAVE_IN_FLIGHT', + 37: 'SPI_PERF_CSGN_WINDOW_VALID', + 38: 'SPI_PERF_CSGN_BUSY', + 39: 'SPI_PERF_CSGN_NUM_THREADGROUPS', + 40: 'SPI_PERF_CSGN_CRAWLER_STALL', + 41: 'SPI_PERF_CSGN_EVENT_WAVE', + 42: 'SPI_PERF_CSGN_WAVE', + 43: 'SPI_PERF_CSGN_PWS_STALL', + 44: 'SPI_PERF_CSGN_WAVE_IN_FLIGHT', + 45: 'SPI_PERF_CSN_WINDOW_VALID', + 46: 'SPI_PERF_CSN_BUSY', + 47: 'SPI_PERF_CSN_NUM_THREADGROUPS', + 48: 'SPI_PERF_CSN_CRAWLER_STALL', + 49: 'SPI_PERF_CSN_EVENT_WAVE', + 50: 'SPI_PERF_CSN_WAVE', + 51: 'SPI_PERF_CSN_WAVE_IN_FLIGHT', + 53: 'SPI_PERF_PS0_WINDOW_VALID', + 54: 'SPI_PERF_PS1_WINDOW_VALID', + 55: 'SPI_PERF_PS2_WINDOW_VALID', + 56: 'SPI_PERF_PS3_WINDOW_VALID', + 57: 'SPI_PERF_PS0_BUSY', + 58: 'SPI_PERF_PS1_BUSY', + 59: 'SPI_PERF_PS2_BUSY', + 60: 'SPI_PERF_PS3_BUSY', + 61: 'SPI_PERF_PS0_ACTIVE', + 62: 'SPI_PERF_PS1_ACTIVE', + 63: 'SPI_PERF_PS2_ACTIVE', + 64: 'SPI_PERF_PS3_ACTIVE', + 65: 'SPI_PERF_PS0_DEALLOC', + 66: 'SPI_PERF_PS1_DEALLOC', + 67: 'SPI_PERF_PS2_DEALLOC', + 68: 'SPI_PERF_PS3_DEALLOC', + 69: 'SPI_PERF_PS0_EVENT_WAVE', + 70: 'SPI_PERF_PS1_EVENT_WAVE', + 71: 'SPI_PERF_PS2_EVENT_WAVE', + 72: 'SPI_PERF_PS3_EVENT_WAVE', + 73: 'SPI_PERF_PS0_WAVE', + 74: 'SPI_PERF_PS1_WAVE', + 75: 'SPI_PERF_PS2_WAVE', + 76: 'SPI_PERF_PS3_WAVE', + 77: 'SPI_PERF_PS0_OPT_WAVE', + 78: 'SPI_PERF_PS1_OPT_WAVE', + 79: 'SPI_PERF_PS2_OPT_WAVE', + 80: 'SPI_PERF_PS3_OPT_WAVE', + 81: 'SPI_PERF_PS0_PRIM_BIN0', + 82: 'SPI_PERF_PS1_PRIM_BIN0', + 83: 'SPI_PERF_PS2_PRIM_BIN0', + 84: 'SPI_PERF_PS3_PRIM_BIN0', + 85: 'SPI_PERF_PS0_PRIM_BIN1', + 86: 'SPI_PERF_PS1_PRIM_BIN1', + 87: 'SPI_PERF_PS2_PRIM_BIN1', + 88: 'SPI_PERF_PS3_PRIM_BIN1', + 89: 'SPI_PERF_PS0_CRAWLER_STALL', + 90: 'SPI_PERF_PS1_CRAWLER_STALL', + 91: 'SPI_PERF_PS2_CRAWLER_STALL', + 92: 'SPI_PERF_PS3_CRAWLER_STALL', + 93: 'SPI_PERF_PS_PERS_UPD_FULL0', + 94: 'SPI_PERF_PS_PERS_UPD_FULL1', + 95: 'SPI_PERF_PS0_2_WAVE_GROUPS', + 96: 'SPI_PERF_PS1_2_WAVE_GROUPS', + 97: 'SPI_PERF_PS2_2_WAVE_GROUPS', + 98: 'SPI_PERF_PS3_2_WAVE_GROUPS', + 99: 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', + 100: 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', + 101: 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', + 102: 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', + 103: 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', + 104: 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', + 105: 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', + 106: 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', + 107: 'SPI_PERF_PS_PWS_STALL', + 108: 'SPI_PERF_PS0_LDS_DONE_FULL', + 109: 'SPI_PERF_PS1_LDS_DONE_FULL', + 110: 'SPI_PERF_PS2_LDS_DONE_FULL', + 111: 'SPI_PERF_PS3_LDS_DONE_FULL', + 112: 'SPI_PERF_PS0_DEALLOC_FULL', + 113: 'SPI_PERF_PS1_DEALLOC_FULL', + 114: 'SPI_PERF_PS2_DEALLOC_FULL', + 115: 'SPI_PERF_PS3_DEALLOC_FULL', + 116: 'SPI_PERF_PS0_WAVE_IN_FLIGHT', + 117: 'SPI_PERF_PS1_WAVE_IN_FLIGHT', + 118: 'SPI_PERF_PS2_WAVE_IN_FLIGHT', + 119: 'SPI_PERF_PS3_WAVE_IN_FLIGHT', + 133: 'SPI_PERF_RA_GS_LDS_OCCUPANCY', + 134: 'SPI_PERF_RA_GS_VGPR_OCCUPANCY', + 135: 'SPI_PERF_RA_PS_LDS_OCCUPANCY', + 136: 'SPI_PERF_RA_PS_VGPR_OCCUPANCY', + 137: 'SPI_PERF_RA_SPI_THROTTLE', + 138: 'SPI_PERF_RA_PH_THROTTLE', + 139: 'SPI_PERF_RA_PC_PROBE_STALL_PS', + 140: 'SPI_PERF_RA_PC_PSWAVE_STALL_PS', + 141: 'SPI_PERF_RA_PIPE_REQ_BIN2', + 142: 'SPI_PERF_RA_TASK_REQ_BIN3', + 143: 'SPI_PERF_RA_WR_CTL_FULL', + 144: 'SPI_PERF_RA_REQ_NO_ALLOC', + 145: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', + 146: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', + 147: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', + 148: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', + 149: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', + 150: 'SPI_PERF_RA_RES_STALL_PS', + 151: 'SPI_PERF_RA_RES_STALL_GS', + 152: 'SPI_PERF_RA_RES_STALL_HS', + 153: 'SPI_PERF_RA_RES_STALL_CSG', + 154: 'SPI_PERF_RA_RES_STALL_CSN', + 155: 'SPI_PERF_RA_TMP_STALL_PS', + 156: 'SPI_PERF_RA_TMP_STALL_GS', + 157: 'SPI_PERF_RA_TMP_STALL_HS', + 158: 'SPI_PERF_RA_TMP_STALL_CSG', + 159: 'SPI_PERF_RA_TMP_STALL_CSN', + 160: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 161: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', + 162: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', + 163: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 164: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', + 165: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 166: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', + 167: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', + 168: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 169: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', + 170: 'SPI_PERF_RA_LDS_CU_FULL_PS', + 171: 'SPI_PERF_RA_LDS_CU_FULL_HS', + 172: 'SPI_PERF_RA_LDS_CU_FULL_GS', + 173: 'SPI_PERF_RA_LDS_CU_FULL_CSG', + 174: 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 175: 'SPI_PERF_RA_BAR_CU_FULL_PS', + 176: 'SPI_PERF_RA_BAR_CU_FULL_GS', + 177: 'SPI_PERF_RA_BAR_CU_FULL_HS', + 178: 'SPI_PERF_RA_BAR_CU_FULL_CSG', + 179: 'SPI_PERF_RA_BAR_CU_FULL_CSN', + 180: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', + 181: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', + 182: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', + 183: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 184: 'SPI_PERF_RA_WVLIM_STALL_PS', + 185: 'SPI_PERF_RA_WVLIM_STALL_GS', + 186: 'SPI_PERF_RA_WVLIM_STALL_HS', + 187: 'SPI_PERF_RA_WVLIM_STALL_CSG', + 188: 'SPI_PERF_RA_WVLIM_STALL_CSN', + 189: 'SPI_PERF_RA_GS_LOCK', + 190: 'SPI_PERF_RA_HS_LOCK', + 191: 'SPI_PERF_RA_CSG_LOCK', + 192: 'SPI_PERF_RA_CSN_LOCK', + 193: 'SPI_PERF_RA_RSV_UPD', + 194: 'SPI_PERF_RA_PRE_ALLOC_STALL', + 195: 'SPI_PERF_RA_GFX_UNDER_TUNNEL', + 196: 'SPI_PERF_RA_CSC_UNDER_TUNNEL', + 197: 'SPI_PERF_RA_WVALLOC_STALL', + 198: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', + 199: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', + 200: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', + 201: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', + 202: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', + 203: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', + 204: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', + 205: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', + 206: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', + 207: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', + 208: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', + 209: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', + 210: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', + 211: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', + 212: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', + 213: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', + 214: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', + 215: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', + 216: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', + 217: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', + 218: 'SPI_PERF_EXP_ARB_COL_CNT', + 219: 'SPI_PERF_EXP_ARB_POS_CNT', + 220: 'SPI_PERF_EXP_ARB_GDS_CNT', + 221: 'SPI_PERF_EXP_ARB_IDX_CNT', + 222: 'SPI_PERF_EXP_WITH_CONFLICT', + 223: 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', + 224: 'SPI_PERF_GS_EXP_DONE', + 225: 'SPI_PERF_PS_EXP_DONE', + 226: 'SPI_PERF_PS_EXP_ARB_CONFLICT', + 227: 'SPI_PERF_GS_SCBD_IDX_CLEANUP', + 228: 'SPI_PERF_GS_SCBD_POS_CLEANUP', + 229: 'SPI_PERF_PS_EXP_ALLOC', + 230: 'SPI_PERF_PS0_WAVEID_STARVED', + 231: 'SPI_PERF_PS1_WAVEID_STARVED', + 232: 'SPI_PERF_PS2_WAVEID_STARVED', + 233: 'SPI_PERF_PS3_WAVEID_STARVED', + 234: 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', + 235: 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', + 236: 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', + 237: 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', + 238: 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', + 239: 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', + 240: 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', + 241: 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', + 242: 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', + 243: 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', + 244: 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', + 245: 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', + 246: 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', + 247: 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', + 248: 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', + 249: 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', + 250: 'SPI_PERF_NUM_EXPGRANT_EXPORTS', + 251: 'SPI_PERF_GS_ALLOC_IDX', + 252: 'SPI_PERF_GS_ALLOC_POS', + 253: 'SPI_PERF_PIX_ALLOC_PEND_CNT', + 254: 'SPI_PERF_EXPORT_SCB0_STALL', + 255: 'SPI_PERF_EXPORT_SCB1_STALL', + 256: 'SPI_PERF_EXPORT_SCB2_STALL', + 257: 'SPI_PERF_EXPORT_SCB3_STALL', + 258: 'SPI_PERF_EXPORT_DB0_STALL', + 259: 'SPI_PERF_EXPORT_DB1_STALL', + 260: 'SPI_PERF_EXPORT_DB2_STALL', + 261: 'SPI_PERF_EXPORT_DB3_STALL', + 262: 'SPI_PERF_EXPORT_DB4_STALL', + 263: 'SPI_PERF_EXPORT_DB5_STALL', + 264: 'SPI_PERF_EXPORT_DB6_STALL', + 265: 'SPI_PERF_EXPORT_DB7_STALL', + 266: 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', + 267: 'SPI_PERF_GS_NGG_STALL_MSG_VAL', + 268: 'SPI_PERF_SWC_PS_WR', + 269: 'SPI_PERF_SWC_GS_WR', + 270: 'SPI_PERF_SWC_HS_WR', + 271: 'SPI_PERF_SWC_CSGN_WR', + 272: 'SPI_PERF_SWC_CSN_WR', + 273: 'SPI_PERF_VWC_PS_WR', + 274: 'SPI_PERF_VWC_ES_WR', + 275: 'SPI_PERF_VWC_GS_WR', + 276: 'SPI_PERF_VWC_LS_WR', + 277: 'SPI_PERF_VWC_HS_WR', + 278: 'SPI_PERF_VWC_CSGN_WR', + 279: 'SPI_PERF_VWC_CSN_WR', + 280: 'SPI_PERF_EXP_THROT_UPSTEP', + 281: 'SPI_PERF_EXP_THROT_DOWNSTEP', + 282: 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', + 283: 'SPI_PERF_BUSY', + 284: 'SPI_PERF_ALL_PS_WAVE', + 285: 'SPI_PERF_ALL_PS_WAVE_IN_FLIGHT', + 286: 'SPI_PERF_ALL_WAVE', + 287: 'SPI_PERF_ALL_WAVE_IN_FLIGHT', + 288: 'SPI_PERF_RA_REQ_ALLOC', + 289: 'SPI_PERF_VGPR_INIT', + 290: 'SPI_PERF_SGPR_INIT', + 291: 'SPI_PERF_VGPR_ALLOC_LEVEL', + 292: 'SPI_PERF_LDS_ALLOC_LEVEL', + 293: 'SPI_PERF_GFX_TEMP_ALLOC_LEVEL', + 294: 'SPI_PERF_CSG_TEMP_ALLOC_LEVEL', + 295: 'SPI_PERF_CSN_TEMP_ALLOC_LEVEL', + 296: 'SPI_PERF_ALL_WAVE_RESTORED', + 297: 'SPI_PERF_ALL_WAVE_SAVED', + 298: 'SPI_PERF_ALL_WAVE_W32', + 299: 'SPI_PERF_ALL_WAVE_W64', + 300: 'SPI_PERF_ALL_WAVE_ITEMS', + 301: 'SPI_PERF_ALL_WAVE_ITEMS_W32', + 302: 'SPI_PERF_ALL_WAVE_ITEMS_W64', + 303: 'SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_STALL', + 304: 'SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_LEVEL', + 305: 'SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_STALL', + 306: 'SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_CU_LEVEL', +} +SPI_PERF_GS_WINDOW_VALID = 1 +SPI_PERF_GS_BUSY = 2 +SPI_PERF_GS_CRAWLER_STALL = 3 +SPI_PERF_GS_EVENT_WAVE = 4 +SPI_PERF_GS_WAVE = 5 +SPI_PERF_GS_PERS_UPD_FULL0 = 6 +SPI_PERF_GS_PERS_UPD_FULL1 = 7 +SPI_PERF_GS_FIRST_SUBGRP = 8 +SPI_PERF_GS_HS_DEALLOC = 9 +SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 10 +SPI_PERF_GS_POS0_STALL = 11 +SPI_PERF_GS_POS1_STALL = 12 +SPI_PERF_GS_INDX0_STALL = 13 +SPI_PERF_GS_INDX1_STALL = 14 +SPI_PERF_GS_PWS_STALL = 15 +SPI_PERF_GS_GRP_LIFETIME = 16 +SPI_PERF_GS_WAVE_IN_FLIGHT = 17 +SPI_PERF_GS_GRP_LIFETIME_SAMPLE = 18 +SPI_PERF_HS_WINDOW_VALID = 21 +SPI_PERF_HS_BUSY = 22 +SPI_PERF_HS_CRAWLER_STALL = 23 +SPI_PERF_HS_FIRST_WAVE = 24 +SPI_PERF_HS_EVENT_WAVE = 26 +SPI_PERF_HS_WAVE = 27 +SPI_PERF_HS_PERS_UPD_FULL0 = 28 +SPI_PERF_HS_PERS_UPD_FULL1 = 29 +SPI_PERF_HS_PWS_STALL = 30 +SPI_PERF_HS_WAVE_IN_FLIGHT = 31 +SPI_PERF_CSGN_WINDOW_VALID = 37 +SPI_PERF_CSGN_BUSY = 38 +SPI_PERF_CSGN_NUM_THREADGROUPS = 39 +SPI_PERF_CSGN_CRAWLER_STALL = 40 +SPI_PERF_CSGN_EVENT_WAVE = 41 +SPI_PERF_CSGN_WAVE = 42 +SPI_PERF_CSGN_PWS_STALL = 43 +SPI_PERF_CSGN_WAVE_IN_FLIGHT = 44 +SPI_PERF_CSN_WINDOW_VALID = 45 +SPI_PERF_CSN_BUSY = 46 +SPI_PERF_CSN_NUM_THREADGROUPS = 47 +SPI_PERF_CSN_CRAWLER_STALL = 48 +SPI_PERF_CSN_EVENT_WAVE = 49 +SPI_PERF_CSN_WAVE = 50 +SPI_PERF_CSN_WAVE_IN_FLIGHT = 51 +SPI_PERF_PS0_WINDOW_VALID = 53 +SPI_PERF_PS1_WINDOW_VALID = 54 +SPI_PERF_PS2_WINDOW_VALID = 55 +SPI_PERF_PS3_WINDOW_VALID = 56 +SPI_PERF_PS0_BUSY = 57 +SPI_PERF_PS1_BUSY = 58 +SPI_PERF_PS2_BUSY = 59 +SPI_PERF_PS3_BUSY = 60 +SPI_PERF_PS0_ACTIVE = 61 +SPI_PERF_PS1_ACTIVE = 62 +SPI_PERF_PS2_ACTIVE = 63 +SPI_PERF_PS3_ACTIVE = 64 +SPI_PERF_PS0_DEALLOC = 65 +SPI_PERF_PS1_DEALLOC = 66 +SPI_PERF_PS2_DEALLOC = 67 +SPI_PERF_PS3_DEALLOC = 68 +SPI_PERF_PS0_EVENT_WAVE = 69 +SPI_PERF_PS1_EVENT_WAVE = 70 +SPI_PERF_PS2_EVENT_WAVE = 71 +SPI_PERF_PS3_EVENT_WAVE = 72 +SPI_PERF_PS0_WAVE = 73 +SPI_PERF_PS1_WAVE = 74 +SPI_PERF_PS2_WAVE = 75 +SPI_PERF_PS3_WAVE = 76 +SPI_PERF_PS0_OPT_WAVE = 77 +SPI_PERF_PS1_OPT_WAVE = 78 +SPI_PERF_PS2_OPT_WAVE = 79 +SPI_PERF_PS3_OPT_WAVE = 80 +SPI_PERF_PS0_PRIM_BIN0 = 81 +SPI_PERF_PS1_PRIM_BIN0 = 82 +SPI_PERF_PS2_PRIM_BIN0 = 83 +SPI_PERF_PS3_PRIM_BIN0 = 84 +SPI_PERF_PS0_PRIM_BIN1 = 85 +SPI_PERF_PS1_PRIM_BIN1 = 86 +SPI_PERF_PS2_PRIM_BIN1 = 87 +SPI_PERF_PS3_PRIM_BIN1 = 88 +SPI_PERF_PS0_CRAWLER_STALL = 89 +SPI_PERF_PS1_CRAWLER_STALL = 90 +SPI_PERF_PS2_CRAWLER_STALL = 91 +SPI_PERF_PS3_CRAWLER_STALL = 92 +SPI_PERF_PS_PERS_UPD_FULL0 = 93 +SPI_PERF_PS_PERS_UPD_FULL1 = 94 +SPI_PERF_PS0_2_WAVE_GROUPS = 95 +SPI_PERF_PS1_2_WAVE_GROUPS = 96 +SPI_PERF_PS2_2_WAVE_GROUPS = 97 +SPI_PERF_PS3_2_WAVE_GROUPS = 98 +SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 99 +SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 100 +SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 101 +SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 102 +SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 103 +SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 104 +SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 105 +SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 106 +SPI_PERF_PS_PWS_STALL = 107 +SPI_PERF_PS0_LDS_DONE_FULL = 108 +SPI_PERF_PS1_LDS_DONE_FULL = 109 +SPI_PERF_PS2_LDS_DONE_FULL = 110 +SPI_PERF_PS3_LDS_DONE_FULL = 111 +SPI_PERF_PS0_DEALLOC_FULL = 112 +SPI_PERF_PS1_DEALLOC_FULL = 113 +SPI_PERF_PS2_DEALLOC_FULL = 114 +SPI_PERF_PS3_DEALLOC_FULL = 115 +SPI_PERF_PS0_WAVE_IN_FLIGHT = 116 +SPI_PERF_PS1_WAVE_IN_FLIGHT = 117 +SPI_PERF_PS2_WAVE_IN_FLIGHT = 118 +SPI_PERF_PS3_WAVE_IN_FLIGHT = 119 +SPI_PERF_RA_GS_LDS_OCCUPANCY = 133 +SPI_PERF_RA_GS_VGPR_OCCUPANCY = 134 +SPI_PERF_RA_PS_LDS_OCCUPANCY = 135 +SPI_PERF_RA_PS_VGPR_OCCUPANCY = 136 +SPI_PERF_RA_SPI_THROTTLE = 137 +SPI_PERF_RA_PH_THROTTLE = 138 +SPI_PERF_RA_PC_PROBE_STALL_PS = 139 +SPI_PERF_RA_PC_PSWAVE_STALL_PS = 140 +SPI_PERF_RA_PIPE_REQ_BIN2 = 141 +SPI_PERF_RA_TASK_REQ_BIN3 = 142 +SPI_PERF_RA_WR_CTL_FULL = 143 +SPI_PERF_RA_REQ_NO_ALLOC = 144 +SPI_PERF_RA_REQ_NO_ALLOC_PS = 145 +SPI_PERF_RA_REQ_NO_ALLOC_GS = 146 +SPI_PERF_RA_REQ_NO_ALLOC_HS = 147 +SPI_PERF_RA_REQ_NO_ALLOC_CSG = 148 +SPI_PERF_RA_REQ_NO_ALLOC_CSN = 149 +SPI_PERF_RA_RES_STALL_PS = 150 +SPI_PERF_RA_RES_STALL_GS = 151 +SPI_PERF_RA_RES_STALL_HS = 152 +SPI_PERF_RA_RES_STALL_CSG = 153 +SPI_PERF_RA_RES_STALL_CSN = 154 +SPI_PERF_RA_TMP_STALL_PS = 155 +SPI_PERF_RA_TMP_STALL_GS = 156 +SPI_PERF_RA_TMP_STALL_HS = 157 +SPI_PERF_RA_TMP_STALL_CSG = 158 +SPI_PERF_RA_TMP_STALL_CSN = 159 +SPI_PERF_RA_WAVE_SIMD_FULL_PS = 160 +SPI_PERF_RA_WAVE_SIMD_FULL_GS = 161 +SPI_PERF_RA_WAVE_SIMD_FULL_HS = 162 +SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 163 +SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 164 +SPI_PERF_RA_VGPR_SIMD_FULL_PS = 165 +SPI_PERF_RA_VGPR_SIMD_FULL_GS = 166 +SPI_PERF_RA_VGPR_SIMD_FULL_HS = 167 +SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 168 +SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 169 +SPI_PERF_RA_LDS_CU_FULL_PS = 170 +SPI_PERF_RA_LDS_CU_FULL_HS = 171 +SPI_PERF_RA_LDS_CU_FULL_GS = 172 +SPI_PERF_RA_LDS_CU_FULL_CSG = 173 +SPI_PERF_RA_LDS_CU_FULL_CSN = 174 +SPI_PERF_RA_BAR_CU_FULL_PS = 175 +SPI_PERF_RA_BAR_CU_FULL_GS = 176 +SPI_PERF_RA_BAR_CU_FULL_HS = 177 +SPI_PERF_RA_BAR_CU_FULL_CSG = 178 +SPI_PERF_RA_BAR_CU_FULL_CSN = 179 +SPI_PERF_RA_BULKY_CU_FULL_CSG = 180 +SPI_PERF_RA_BULKY_CU_FULL_CSN = 181 +SPI_PERF_RA_TGLIM_CU_FULL_CSG = 182 +SPI_PERF_RA_TGLIM_CU_FULL_CSN = 183 +SPI_PERF_RA_WVLIM_STALL_PS = 184 +SPI_PERF_RA_WVLIM_STALL_GS = 185 +SPI_PERF_RA_WVLIM_STALL_HS = 186 +SPI_PERF_RA_WVLIM_STALL_CSG = 187 +SPI_PERF_RA_WVLIM_STALL_CSN = 188 +SPI_PERF_RA_GS_LOCK = 189 +SPI_PERF_RA_HS_LOCK = 190 +SPI_PERF_RA_CSG_LOCK = 191 +SPI_PERF_RA_CSN_LOCK = 192 +SPI_PERF_RA_RSV_UPD = 193 +SPI_PERF_RA_PRE_ALLOC_STALL = 194 +SPI_PERF_RA_GFX_UNDER_TUNNEL = 195 +SPI_PERF_RA_CSC_UNDER_TUNNEL = 196 +SPI_PERF_RA_WVALLOC_STALL = 197 +SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 198 +SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 199 +SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 200 +SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 201 +SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 202 +SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 203 +SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 204 +SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 205 +SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 206 +SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 207 +SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 208 +SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 209 +SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 210 +SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 211 +SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 212 +SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 213 +SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 214 +SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 215 +SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 216 +SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 217 +SPI_PERF_EXP_ARB_COL_CNT = 218 +SPI_PERF_EXP_ARB_POS_CNT = 219 +SPI_PERF_EXP_ARB_GDS_CNT = 220 +SPI_PERF_EXP_ARB_IDX_CNT = 221 +SPI_PERF_EXP_WITH_CONFLICT = 222 +SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 223 +SPI_PERF_GS_EXP_DONE = 224 +SPI_PERF_PS_EXP_DONE = 225 +SPI_PERF_PS_EXP_ARB_CONFLICT = 226 +SPI_PERF_GS_SCBD_IDX_CLEANUP = 227 +SPI_PERF_GS_SCBD_POS_CLEANUP = 228 +SPI_PERF_PS_EXP_ALLOC = 229 +SPI_PERF_PS0_WAVEID_STARVED = 230 +SPI_PERF_PS1_WAVEID_STARVED = 231 +SPI_PERF_PS2_WAVEID_STARVED = 232 +SPI_PERF_PS3_WAVEID_STARVED = 233 +SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 234 +SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 235 +SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 236 +SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 237 +SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 238 +SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 239 +SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 240 +SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 241 +SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 242 +SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 243 +SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 244 +SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 245 +SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 246 +SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 247 +SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 248 +SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 249 +SPI_PERF_NUM_EXPGRANT_EXPORTS = 250 +SPI_PERF_GS_ALLOC_IDX = 251 +SPI_PERF_GS_ALLOC_POS = 252 +SPI_PERF_PIX_ALLOC_PEND_CNT = 253 +SPI_PERF_EXPORT_SCB0_STALL = 254 +SPI_PERF_EXPORT_SCB1_STALL = 255 +SPI_PERF_EXPORT_SCB2_STALL = 256 +SPI_PERF_EXPORT_SCB3_STALL = 257 +SPI_PERF_EXPORT_DB0_STALL = 258 +SPI_PERF_EXPORT_DB1_STALL = 259 +SPI_PERF_EXPORT_DB2_STALL = 260 +SPI_PERF_EXPORT_DB3_STALL = 261 +SPI_PERF_EXPORT_DB4_STALL = 262 +SPI_PERF_EXPORT_DB5_STALL = 263 +SPI_PERF_EXPORT_DB6_STALL = 264 +SPI_PERF_EXPORT_DB7_STALL = 265 +SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 266 +SPI_PERF_GS_NGG_STALL_MSG_VAL = 267 +SPI_PERF_SWC_PS_WR = 268 +SPI_PERF_SWC_GS_WR = 269 +SPI_PERF_SWC_HS_WR = 270 +SPI_PERF_SWC_CSGN_WR = 271 +SPI_PERF_SWC_CSN_WR = 272 +SPI_PERF_VWC_PS_WR = 273 +SPI_PERF_VWC_ES_WR = 274 +SPI_PERF_VWC_GS_WR = 275 +SPI_PERF_VWC_LS_WR = 276 +SPI_PERF_VWC_HS_WR = 277 +SPI_PERF_VWC_CSGN_WR = 278 +SPI_PERF_VWC_CSN_WR = 279 +SPI_PERF_EXP_THROT_UPSTEP = 280 +SPI_PERF_EXP_THROT_DOWNSTEP = 281 +SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 282 +SPI_PERF_BUSY = 283 +SPI_PERF_ALL_PS_WAVE = 284 +SPI_PERF_ALL_PS_WAVE_IN_FLIGHT = 285 +SPI_PERF_ALL_WAVE = 286 +SPI_PERF_ALL_WAVE_IN_FLIGHT = 287 +SPI_PERF_RA_REQ_ALLOC = 288 +SPI_PERF_VGPR_INIT = 289 +SPI_PERF_SGPR_INIT = 290 +SPI_PERF_VGPR_ALLOC_LEVEL = 291 +SPI_PERF_LDS_ALLOC_LEVEL = 292 +SPI_PERF_GFX_TEMP_ALLOC_LEVEL = 293 +SPI_PERF_CSG_TEMP_ALLOC_LEVEL = 294 +SPI_PERF_CSN_TEMP_ALLOC_LEVEL = 295 +SPI_PERF_ALL_WAVE_RESTORED = 296 +SPI_PERF_ALL_WAVE_SAVED = 297 +SPI_PERF_ALL_WAVE_W32 = 298 +SPI_PERF_ALL_WAVE_W64 = 299 +SPI_PERF_ALL_WAVE_ITEMS = 300 +SPI_PERF_ALL_WAVE_ITEMS_W32 = 301 +SPI_PERF_ALL_WAVE_ITEMS_W64 = 302 +SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_STALL = 303 +SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_LEVEL = 304 +SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_STALL = 305 +SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_CU_LEVEL = 306 +SPI_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' +SPI_PNT_SPRITE_OVERRIDE__enumvalues = { + 0: 'SPI_PNT_SPRITE_SEL_0', + 1: 'SPI_PNT_SPRITE_SEL_1', + 2: 'SPI_PNT_SPRITE_SEL_S', + 3: 'SPI_PNT_SPRITE_SEL_T', + 4: 'SPI_PNT_SPRITE_SEL_NONE', +} +SPI_PNT_SPRITE_SEL_0 = 0 +SPI_PNT_SPRITE_SEL_1 = 1 +SPI_PNT_SPRITE_SEL_S = 2 +SPI_PNT_SPRITE_SEL_T = 3 +SPI_PNT_SPRITE_SEL_NONE = 4 +SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PS_LDS_GROUP_SIZE' +SPI_PS_LDS_GROUP_SIZE__enumvalues = { + 0: 'SPI_PS_LDS_GROUP_1', + 1: 'SPI_PS_LDS_GROUP_2', + 2: 'SPI_PS_LDS_GROUP_4', +} +SPI_PS_LDS_GROUP_1 = 0 +SPI_PS_LDS_GROUP_2 = 1 +SPI_PS_LDS_GROUP_4 = 2 +SPI_PS_LDS_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SAMPLE_CNTL' +SPI_SAMPLE_CNTL__enumvalues = { + 0: 'CENTROIDS_ONLY', + 1: 'CENTERS_ONLY', + 2: 'CENTROIDS_AND_CENTERS', + 3: 'UNDEF', +} +CENTROIDS_ONLY = 0 +CENTERS_ONLY = 1 +CENTROIDS_AND_CENTERS = 2 +UNDEF = 3 +SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_EX_FORMAT' +SPI_SHADER_EX_FORMAT__enumvalues = { + 0: 'SPI_SHADER_ZERO', + 1: 'SPI_SHADER_32_R', + 2: 'SPI_SHADER_32_GR', + 3: 'SPI_SHADER_32_AR', + 4: 'SPI_SHADER_FP16_ABGR', + 5: 'SPI_SHADER_UNORM16_ABGR', + 6: 'SPI_SHADER_SNORM16_ABGR', + 7: 'SPI_SHADER_UINT16_ABGR', + 8: 'SPI_SHADER_SINT16_ABGR', + 9: 'SPI_SHADER_32_ABGR', +} +SPI_SHADER_ZERO = 0 +SPI_SHADER_32_R = 1 +SPI_SHADER_32_GR = 2 +SPI_SHADER_32_AR = 3 +SPI_SHADER_FP16_ABGR = 4 +SPI_SHADER_UNORM16_ABGR = 5 +SPI_SHADER_SNORM16_ABGR = 6 +SPI_SHADER_UINT16_ABGR = 7 +SPI_SHADER_SINT16_ABGR = 8 +SPI_SHADER_32_ABGR = 9 +SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_FORMAT' +SPI_SHADER_FORMAT__enumvalues = { + 0: 'SPI_SHADER_NONE', + 1: 'SPI_SHADER_1COMP', + 2: 'SPI_SHADER_2COMP', + 3: 'SPI_SHADER_4COMPRESS', + 4: 'SPI_SHADER_4COMP', +} +SPI_SHADER_NONE = 0 +SPI_SHADER_1COMP = 1 +SPI_SHADER_2COMP = 2 +SPI_SHADER_4COMPRESS = 3 +SPI_SHADER_4COMP = 4 +SPI_SHADER_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ADDRESS_MODE' +SH_MEM_ADDRESS_MODE__enumvalues = { + 0: 'SH_MEM_ADDRESS_MODE_64', + 1: 'SH_MEM_ADDRESS_MODE_32', +} +SH_MEM_ADDRESS_MODE_64 = 0 +SH_MEM_ADDRESS_MODE_32 = 1 +SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ALIGNMENT_MODE' +SH_MEM_ALIGNMENT_MODE__enumvalues = { + 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', + 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', + 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', +} +SH_MEM_ALIGNMENT_MODE_DWORD = 0 +SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 +SH_MEM_ALIGNMENT_MODE_STRICT = 2 +SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 +SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQG_PERF_SEL' +SQG_PERF_SEL__enumvalues = { + 0: 'SQG_PERF_SEL_NONE', + 1: 'SQG_PERF_SEL_MSG_BUS_BUSY', + 2: 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', + 3: 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', + 4: 'SQG_PERF_SEL_EXP_BUS0_BUSY', + 5: 'SQG_PERF_SEL_EXP_BUS1_BUSY', + 6: 'SQG_PERF_SEL_TTRACE_WRITE_DATA', + 7: 'SQG_PERF_SEL_TTRACE_STALL', + 8: 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', + 9: 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', + 10: 'SQG_PERF_SEL_EVENTS', + 11: 'SQG_PERF_SEL_WAVES_RESTORED', + 12: 'SQG_PERF_SEL_WAVES_SAVED', + 13: 'SQG_PERF_SEL_ACCUM_PREV', + 14: 'SQG_PERF_SEL_CYCLES', + 15: 'SQG_PERF_SEL_BUSY_CYCLES', + 16: 'SQG_PERF_SEL_WAVE_CYCLES', + 17: 'SQG_PERF_SEL_MSG', + 18: 'SQG_PERF_SEL_MSG_INTERRUPT', + 19: 'SQG_PERF_SEL_WAVES', + 20: 'SQG_PERF_SEL_WAVES_32', + 21: 'SQG_PERF_SEL_WAVES_64', + 22: 'SQG_PERF_SEL_LEVEL_WAVES', + 23: 'SQG_PERF_SEL_ITEMS', + 24: 'SQG_PERF_SEL_WAVE32_ITEMS', + 25: 'SQG_PERF_SEL_WAVE64_ITEMS', + 26: 'SQG_PERF_SEL_PS_QUADS', + 27: 'SQG_PERF_SEL_WAVES_EQ_64', + 28: 'SQG_PERF_SEL_WAVES_EQ_32', + 29: 'SQG_PERF_SEL_WAVES_LT_64', + 30: 'SQG_PERF_SEL_WAVES_LT_48', + 31: 'SQG_PERF_SEL_WAVES_LT_32', + 32: 'SQG_PERF_SEL_WAVES_LT_16', + 33: 'SQG_PERF_SEL_REFCLKS', + 34: 'SQG_PERF_SEL_WAVES_WGP_TAKEOVER', + 35: 'SQG_PERF_SEL_WAVES_DYN_VGPR', + 36: 'SQG_PERF_SEL_ITEMS_PS', + 37: 'SQG_PERF_SEL_ITEMS_GS', + 38: 'SQG_PERF_SEL_ITEMS_HS', + 39: 'SQG_PERF_SEL_ITEMS_CS', + 40: 'SQG_PERF_SEL_WAVES_VEC32', + 41: 'SQG_PERF_SEL_WAVES_PS_VEC32', + 42: 'SQG_PERF_SEL_WAVES_GS_VEC32', + 43: 'SQG_PERF_SEL_WAVES_HS_VEC32', + 44: 'SQG_PERF_SEL_WAVES_CS_VEC32', + 45: 'SQG_PERF_SEL_LEVEL_WGP_ACTIVE', + 46: 'SQG_PERF_SEL_DUMMY_LAST', +} +SQG_PERF_SEL_NONE = 0 +SQG_PERF_SEL_MSG_BUS_BUSY = 1 +SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 2 +SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 3 +SQG_PERF_SEL_EXP_BUS0_BUSY = 4 +SQG_PERF_SEL_EXP_BUS1_BUSY = 5 +SQG_PERF_SEL_TTRACE_WRITE_DATA = 6 +SQG_PERF_SEL_TTRACE_STALL = 7 +SQG_PERF_SEL_TTRACE_LOST_PACKETS = 8 +SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 9 +SQG_PERF_SEL_EVENTS = 10 +SQG_PERF_SEL_WAVES_RESTORED = 11 +SQG_PERF_SEL_WAVES_SAVED = 12 +SQG_PERF_SEL_ACCUM_PREV = 13 +SQG_PERF_SEL_CYCLES = 14 +SQG_PERF_SEL_BUSY_CYCLES = 15 +SQG_PERF_SEL_WAVE_CYCLES = 16 +SQG_PERF_SEL_MSG = 17 +SQG_PERF_SEL_MSG_INTERRUPT = 18 +SQG_PERF_SEL_WAVES = 19 +SQG_PERF_SEL_WAVES_32 = 20 +SQG_PERF_SEL_WAVES_64 = 21 +SQG_PERF_SEL_LEVEL_WAVES = 22 +SQG_PERF_SEL_ITEMS = 23 +SQG_PERF_SEL_WAVE32_ITEMS = 24 +SQG_PERF_SEL_WAVE64_ITEMS = 25 +SQG_PERF_SEL_PS_QUADS = 26 +SQG_PERF_SEL_WAVES_EQ_64 = 27 +SQG_PERF_SEL_WAVES_EQ_32 = 28 +SQG_PERF_SEL_WAVES_LT_64 = 29 +SQG_PERF_SEL_WAVES_LT_48 = 30 +SQG_PERF_SEL_WAVES_LT_32 = 31 +SQG_PERF_SEL_WAVES_LT_16 = 32 +SQG_PERF_SEL_REFCLKS = 33 +SQG_PERF_SEL_WAVES_WGP_TAKEOVER = 34 +SQG_PERF_SEL_WAVES_DYN_VGPR = 35 +SQG_PERF_SEL_ITEMS_PS = 36 +SQG_PERF_SEL_ITEMS_GS = 37 +SQG_PERF_SEL_ITEMS_HS = 38 +SQG_PERF_SEL_ITEMS_CS = 39 +SQG_PERF_SEL_WAVES_VEC32 = 40 +SQG_PERF_SEL_WAVES_PS_VEC32 = 41 +SQG_PERF_SEL_WAVES_GS_VEC32 = 42 +SQG_PERF_SEL_WAVES_HS_VEC32 = 43 +SQG_PERF_SEL_WAVES_CS_VEC32 = 44 +SQG_PERF_SEL_LEVEL_WGP_ACTIVE = 45 +SQG_PERF_SEL_DUMMY_LAST = 46 +SQG_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_CAC_POWER_SEL' +SQ_CAC_POWER_SEL__enumvalues = { + 0: 'SQ_CAC_POWER_VALU', + 1: 'SQ_CAC_POWER_VALU0', + 2: 'SQ_CAC_POWER_VALU1', + 3: 'SQ_CAC_POWER_VALU2', + 4: 'SQ_CAC_POWER_GPR_RD', + 5: 'SQ_CAC_POWER_GPR_WR', + 6: 'SQ_CAC_POWER_LDS_BUSY', + 7: 'SQ_CAC_POWER_ALU_BUSY', + 8: 'SQ_CAC_POWER_TEX_BUSY', +} +SQ_CAC_POWER_VALU = 0 +SQ_CAC_POWER_VALU0 = 1 +SQ_CAC_POWER_VALU1 = 2 +SQ_CAC_POWER_VALU2 = 3 +SQ_CAC_POWER_GPR_RD = 4 +SQ_CAC_POWER_GPR_WR = 5 +SQ_CAC_POWER_LDS_BUSY = 6 +SQ_CAC_POWER_ALU_BUSY = 7 +SQ_CAC_POWER_TEX_BUSY = 8 +SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_EDC_INFO_SOURCE' +SQ_EDC_INFO_SOURCE__enumvalues = { + 0: 'SQ_EDC_INFO_SOURCE_INVALID', + 1: 'SQ_EDC_INFO_SOURCE_INST', + 2: 'SQ_EDC_INFO_SOURCE_SGPR', + 3: 'SQ_EDC_INFO_SOURCE_VGPR', + 4: 'SQ_EDC_INFO_SOURCE_LDS', + 5: 'SQ_EDC_INFO_SOURCE_GDS', + 6: 'SQ_EDC_INFO_SOURCE_TA', +} +SQ_EDC_INFO_SOURCE_INVALID = 0 +SQ_EDC_INFO_SOURCE_INST = 1 +SQ_EDC_INFO_SOURCE_SGPR = 2 +SQ_EDC_INFO_SOURCE_VGPR = 3 +SQ_EDC_INFO_SOURCE_LDS = 4 +SQ_EDC_INFO_SOURCE_GDS = 5 +SQ_EDC_INFO_SOURCE_TA = 6 +SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IBUF_ST' +SQ_IBUF_ST__enumvalues = { + 0: 'SQ_IBUF_IB_IDLE', + 1: 'SQ_IBUF_IB_INI_WAIT_GNT', + 2: 'SQ_IBUF_IB_INI_WAIT_DRET', + 3: 'SQ_IBUF_IB_LE_4DW', + 4: 'SQ_IBUF_IB_WAIT_DRET', + 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', + 6: 'SQ_IBUF_IB_DRET', + 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', +} +SQ_IBUF_IB_IDLE = 0 +SQ_IBUF_IB_INI_WAIT_GNT = 1 +SQ_IBUF_IB_INI_WAIT_DRET = 2 +SQ_IBUF_IB_LE_4DW = 3 +SQ_IBUF_IB_WAIT_DRET = 4 +SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 +SQ_IBUF_IB_DRET = 6 +SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 +SQ_IBUF_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IMG_FILTER_TYPE' +SQ_IMG_FILTER_TYPE__enumvalues = { + 0: 'SQ_IMG_FILTER_MODE_BLEND', + 1: 'SQ_IMG_FILTER_MODE_MIN', + 2: 'SQ_IMG_FILTER_MODE_MAX', +} +SQ_IMG_FILTER_MODE_BLEND = 0 +SQ_IMG_FILTER_MODE_MIN = 1 +SQ_IMG_FILTER_MODE_MAX = 2 +SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_CMD' +SQ_IND_CMD_CMD__enumvalues = { + 0: 'SQ_IND_CMD_CMD_NULL', + 1: 'SQ_IND_CMD_CMD_SETHALT', + 2: 'SQ_IND_CMD_CMD_SAVECTX', + 3: 'SQ_IND_CMD_CMD_KILL', + 4: 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', + 5: 'SQ_IND_CMD_CMD_TRAP', + 6: 'SQ_IND_CMD_CMD_SET_SYS_PRIO', + 7: 'SQ_IND_CMD_CMD_SETFATALHALT', + 8: 'SQ_IND_CMD_CMD_SINGLE_STEP', +} +SQ_IND_CMD_CMD_NULL = 0 +SQ_IND_CMD_CMD_SETHALT = 1 +SQ_IND_CMD_CMD_SAVECTX = 2 +SQ_IND_CMD_CMD_KILL = 3 +SQ_IND_CMD_CMD_TRAP_AFTER_INST = 4 +SQ_IND_CMD_CMD_TRAP = 5 +SQ_IND_CMD_CMD_SET_SYS_PRIO = 6 +SQ_IND_CMD_CMD_SETFATALHALT = 7 +SQ_IND_CMD_CMD_SINGLE_STEP = 8 +SQ_IND_CMD_CMD = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_MODE' +SQ_IND_CMD_MODE__enumvalues = { + 0: 'SQ_IND_CMD_MODE_SINGLE', + 1: 'SQ_IND_CMD_MODE_BROADCAST', + 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', + 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', +} +SQ_IND_CMD_MODE_SINGLE = 0 +SQ_IND_CMD_MODE_BROADCAST = 1 +SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 +SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 +SQ_IND_CMD_MODE_BROADCAST_ME = 4 +SQ_IND_CMD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INST_STR_ST' +SQ_INST_STR_ST__enumvalues = { + 0: 'SQ_INST_STR_IB_WAVE_NORML', + 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 4: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', + 5: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', +} +SQ_INST_STR_IB_WAVE_NORML = 0 +SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 +SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 +SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 +SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 4 +SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 5 +SQ_INST_STR_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INST_TYPE' +SQ_INST_TYPE__enumvalues = { + 0: 'SQ_INST_TYPE_VALU', + 1: 'SQ_INST_TYPE_SCALAR', + 2: 'SQ_INST_TYPE_TEX', + 3: 'SQ_INST_TYPE_LDS', + 4: 'SQ_INST_TYPE_LDS_DIRECT', + 5: 'SQ_INST_TYPE_EXP', + 6: 'SQ_INST_TYPE_MSG', + 7: 'SQ_INST_TYPE_BARRIER', + 8: 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', + 9: 'SQ_INST_TYPE_BRANCH_TAKEN', + 10: 'SQ_INST_TYPE_JUMP', + 11: 'SQ_INST_TYPE_OTHER', + 12: 'SQ_INST_TYPE_NONE', + 13: 'SQ_INST_TYPE_DUAL_VALU', + 14: 'SQ_INST_TYPE_FLAT', + 15: 'SQ_INST_TYPE_VALU_MATRIX', +} +SQ_INST_TYPE_VALU = 0 +SQ_INST_TYPE_SCALAR = 1 +SQ_INST_TYPE_TEX = 2 +SQ_INST_TYPE_LDS = 3 +SQ_INST_TYPE_LDS_DIRECT = 4 +SQ_INST_TYPE_EXP = 5 +SQ_INST_TYPE_MSG = 6 +SQ_INST_TYPE_BARRIER = 7 +SQ_INST_TYPE_BRANCH_NOT_TAKEN = 8 +SQ_INST_TYPE_BRANCH_TAKEN = 9 +SQ_INST_TYPE_JUMP = 10 +SQ_INST_TYPE_OTHER = 11 +SQ_INST_TYPE_NONE = 12 +SQ_INST_TYPE_DUAL_VALU = 13 +SQ_INST_TYPE_FLAT = 14 +SQ_INST_TYPE_VALU_MATRIX = 15 +SQ_INST_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_LLC_CTL' +SQ_LLC_CTL__enumvalues = { + 0: 'SQ_LLC_0', + 1: 'SQ_LLC_1', + 2: 'SQ_LLC_RSVD_2', + 3: 'SQ_LLC_BYPASS', +} +SQ_LLC_0 = 0 +SQ_LLC_1 = 1 +SQ_LLC_RSVD_2 = 2 +SQ_LLC_BYPASS = 3 +SQ_LLC_CTL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_NO_INST_ISSUE' +SQ_NO_INST_ISSUE__enumvalues = { + 0: 'SQ_NO_INST_ISSUE_NO_INSTS', + 1: 'SQ_NO_INST_ISSUE_ALU_DEP', + 2: 'SQ_NO_INST_ISSUE_S_WAITCNT', + 3: 'SQ_NO_INST_ISSUE_NO_ARB_WIN', + 4: 'SQ_NO_INST_ISSUE_SLEEP_WAIT', + 5: 'SQ_NO_INST_ISSUE_BARRIER_WAIT', + 6: 'SQ_NO_INST_ISSUE_OTHER', + 7: 'SQ_NO_INST_ISSUE_INTERNAL', +} +SQ_NO_INST_ISSUE_NO_INSTS = 0 +SQ_NO_INST_ISSUE_ALU_DEP = 1 +SQ_NO_INST_ISSUE_S_WAITCNT = 2 +SQ_NO_INST_ISSUE_NO_ARB_WIN = 3 +SQ_NO_INST_ISSUE_SLEEP_WAIT = 4 +SQ_NO_INST_ISSUE_BARRIER_WAIT = 5 +SQ_NO_INST_ISSUE_OTHER = 6 +SQ_NO_INST_ISSUE_INTERNAL = 7 +SQ_NO_INST_ISSUE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_OOB_SELECT' +SQ_OOB_SELECT__enumvalues = { + 0: 'SQ_OOB_INDEX_AND_OFFSET', + 1: 'SQ_OOB_INDEX_ONLY', + 2: 'SQ_OOB_NUM_RECORDS_0', + 3: 'SQ_OOB_COMPLETE', +} +SQ_OOB_INDEX_AND_OFFSET = 0 +SQ_OOB_INDEX_ONLY = 1 +SQ_OOB_NUM_RECORDS_0 = 2 +SQ_OOB_COMPLETE = 3 +SQ_OOB_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_PERF_SEL' +SQ_PERF_SEL__enumvalues = { + 0: 'SQ_PERF_SEL_NONE', + 1: 'SQ_PERF_SEL_ACCUM_PREV', + 2: 'SQ_PERF_SEL_CYCLES', + 3: 'SQ_PERF_SEL_BUSY_CYCLES', + 4: 'SQ_PERF_SEL_WAVES', + 5: 'SQ_PERF_SEL_WAVES_32', + 6: 'SQ_PERF_SEL_WAVES_64', + 7: 'SQ_PERF_SEL_LEVEL_WAVES', + 8: 'SQ_PERF_SEL_ITEMS', + 9: 'SQ_PERF_SEL_WAVE32_ITEMS', + 10: 'SQ_PERF_SEL_WAVE64_ITEMS', + 11: 'SQ_PERF_SEL_PS_QUADS', + 12: 'SQ_PERF_SEL_EVENTS', + 13: 'SQ_PERF_SEL_WAVES_EQ_32', + 14: 'SQ_PERF_SEL_WAVES_EQ_64', + 15: 'SQ_PERF_SEL_WAVES_LT_64', + 16: 'SQ_PERF_SEL_WAVES_LT_48', + 17: 'SQ_PERF_SEL_WAVES_LT_32', + 18: 'SQ_PERF_SEL_WAVES_LT_16', + 19: 'SQ_PERF_SEL_WAVES_RESTORED', + 20: 'SQ_PERF_SEL_WAVES_SAVED', + 21: 'SQ_PERF_SEL_MSG', + 22: 'SQ_PERF_SEL_MSG_INTERRUPT', + 23: 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', + 24: 'SQ_PERF_SEL_WAVE_CYCLES', + 25: 'SQ_PERF_SEL_WAVE_READY', + 26: 'SQ_PERF_SEL_WAIT_INST_ANY', + 27: 'SQ_PERF_SEL_WAIT_ANY', + 28: 'SQ_PERF_SEL_WAIT_CNT_ANY', + 29: 'SQ_PERF_SEL_WAIT_CNT_LOAD', + 30: 'SQ_PERF_SEL_WAIT_CNT_STORE', + 31: 'SQ_PERF_SEL_WAIT_TTRACE', + 32: 'SQ_PERF_SEL_WAIT_IFETCH', + 33: 'SQ_PERF_SEL_WAIT_BARRIER', + 34: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', + 35: 'SQ_PERF_SEL_WAIT_SLEEP', + 36: 'SQ_PERF_SEL_WAIT_DELAY_ALU', + 37: 'SQ_PERF_SEL_WAIT_DEPCTR', + 38: 'SQ_PERF_SEL_WAIT_OTHER', + 39: 'SQ_PERF_SEL_INSTS_ALL', + 40: 'SQ_PERF_SEL_INSTS_BRANCH', + 41: 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', + 42: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', + 43: 'SQ_PERF_SEL_INSTS_EXP', + 44: 'SQ_PERF_SEL_INSTS_FLAT', + 45: 'SQ_PERF_SEL_INSTS_LDS', + 46: 'SQ_PERF_SEL_INSTS_SALU', + 47: 'SQ_PERF_SEL_INSTS_SMEM', + 48: 'SQ_PERF_SEL_INSTS_SMEM_NORM', + 49: 'SQ_PERF_SEL_INSTS_SENDMSG', + 50: 'SQ_PERF_SEL_INSTS_VALU', + 51: 'SQ_PERF_SEL_INSTS_VALU_TRANS32', + 52: 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', + 53: 'SQ_PERF_SEL_INSTS_TEX', + 54: 'SQ_PERF_SEL_INSTS_TEX_LOAD', + 55: 'SQ_PERF_SEL_INSTS_TEX_STORE', + 56: 'SQ_PERF_SEL_INSTS_DELAY_ALU', + 57: 'SQ_PERF_SEL_INSTS_INTERNAL', + 58: 'SQ_PERF_SEL_INSTS_VEC32', + 59: 'SQ_PERF_SEL_INSTS_VEC32_FLAT', + 60: 'SQ_PERF_SEL_INSTS_VEC32_LDS', + 61: 'SQ_PERF_SEL_INSTS_VEC32_VALU', + 62: 'SQ_PERF_SEL_VEC32_INSTS_EXP', + 63: 'SQ_PERF_SEL_INSTS_VEC32_VALU_TRANS32', + 64: 'SQ_PERF_SEL_INSTS_VEC32_VALU_NO_COEXEC', + 65: 'SQ_PERF_SEL_INSTS_VEC32_TEX', + 66: 'SQ_PERF_SEL_INSTS_VEC32_TEX_LOAD', + 67: 'SQ_PERF_SEL_INSTS_VEC32_TEX_STORE', + 68: 'SQ_PERF_SEL_ITEM_CYCLES_VALU', + 69: 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', + 70: 'SQ_PERF_SEL_WAVE32_INSTS', + 71: 'SQ_PERF_SEL_WAVE64_INSTS', + 72: 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', + 73: 'SQ_PERF_SEL_WAVE64_HALF_SKIP', + 74: 'SQ_PERF_SEL_INST_LEVEL_EXP', + 75: 'SQ_PERF_SEL_INST_LEVEL_LDS', + 76: 'SQ_PERF_SEL_INST_LEVEL_SMEM', + 77: 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', + 78: 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', + 79: 'SQ_PERF_SEL_IFETCH_REQS', + 80: 'SQ_PERF_SEL_IFETCH_LEVEL', + 81: 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', + 82: 'SQ_PERF_SEL_VALU_SGATHER_STALL', + 83: 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', + 84: 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', + 85: 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', + 86: 'SQ_PERF_SEL_SALU_SGATHER_STALL', + 87: 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', + 88: 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', + 89: 'SQ_PERF_SEL_INST_ISSUE_SMEM_STALL', + 90: 'SQ_PERF_SEL_INST_ISSUE_ALL_STALL', + 91: 'SQ_PERF_SEL_INST_ISSUE_VALU_STALL', + 92: 'SQ_PERF_SEL_INST_ISSUE_SALU_STALL', + 93: 'SQ_PERF_SEL_INST_ISSUE_TEX_STALL', + 94: 'SQ_PERF_SEL_INST_ISSUE_LDS_STALL', + 96: 'SQ_PERF_SEL_INST_ISSUE_EXP_STALL', + 97: 'SQ_PERF_SEL_INST_WAITCNT_STALL', + 98: 'SQ_PERF_SEL_INST_BARRIER_STALL', + 99: 'SQ_PERF_SEL_INST_CYCLES_VALU', + 100: 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', + 101: 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', + 102: 'SQ_PERF_SEL_INST_CYCLES_VMEM', + 103: 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', + 104: 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', + 105: 'SQ_PERF_SEL_INST_CYCLES_LDS', + 106: 'SQ_PERF_SEL_INST_CYCLES_TEX', + 107: 'SQ_PERF_SEL_INST_CYCLES_FLAT', + 108: 'SQ_PERF_SEL_INST_CYCLES_EXP', + 109: 'SQ_PERF_SEL_VALU_STARVE', + 110: 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', + 111: 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', + 112: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 113: 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', + 114: 'SQ_PERF_SEL_VMEM_BUS_STALL', + 115: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', + 116: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', + 117: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', + 118: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', + 119: 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', + 120: 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', + 121: 'SQ_PERF_SEL_SALU_PIPE_STALL', + 122: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', + 123: 'SQ_PERF_SEL_MSG_BUS_BUSY', + 124: 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', + 125: 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', + 126: 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', + 127: 'SQ_PERF_SEL_EXP_BUS0_BUSY', + 128: 'SQ_PERF_SEL_EXP_BUS1_BUSY', + 129: 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', + 130: 'SQ_PERF_SEL_USER0', + 131: 'SQ_PERF_SEL_USER1', + 132: 'SQ_PERF_SEL_USER2', + 133: 'SQ_PERF_SEL_USER3', + 134: 'SQ_PERF_SEL_USER4', + 135: 'SQ_PERF_SEL_USER5', + 136: 'SQ_PERF_SEL_USER6', + 137: 'SQ_PERF_SEL_USER7', + 138: 'SQ_PERF_SEL_USER8', + 139: 'SQ_PERF_SEL_USER9', + 140: 'SQ_PERF_SEL_USER10', + 141: 'SQ_PERF_SEL_USER11', + 142: 'SQ_PERF_SEL_USER12', + 143: 'SQ_PERF_SEL_USER13', + 144: 'SQ_PERF_SEL_USER14', + 145: 'SQ_PERF_SEL_USER15', + 146: 'SQ_PERF_SEL_USER_LEVEL0', + 147: 'SQ_PERF_SEL_USER_LEVEL1', + 148: 'SQ_PERF_SEL_USER_LEVEL2', + 149: 'SQ_PERF_SEL_USER_LEVEL3', + 150: 'SQ_PERF_SEL_USER_LEVEL4', + 151: 'SQ_PERF_SEL_USER_LEVEL5', + 152: 'SQ_PERF_SEL_USER_LEVEL6', + 153: 'SQ_PERF_SEL_USER_LEVEL7', + 154: 'SQ_PERF_SEL_USER_LEVEL8', + 155: 'SQ_PERF_SEL_USER_LEVEL9', + 156: 'SQ_PERF_SEL_USER_LEVEL10', + 157: 'SQ_PERF_SEL_USER_LEVEL11', + 158: 'SQ_PERF_SEL_USER_LEVEL12', + 159: 'SQ_PERF_SEL_USER_LEVEL13', + 160: 'SQ_PERF_SEL_USER_LEVEL14', + 161: 'SQ_PERF_SEL_USER_LEVEL15', + 162: 'SQ_PERF_SEL_VALU_RETURN_SDST', + 163: 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', + 164: 'SQ_PERF_SEL_INSTS_VALU_TRANS', + 165: 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', + 166: 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', + 167: 'SQ_PERF_SEL_INSTS_VEC32_LDS_PARAM_LOAD', + 168: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', + 169: 'SQ_PERF_SEL_INSTS_VALU_VINTERP', + 170: 'SQ_PERF_SEL_INSTS_VEC32_VALU_VINTERP', + 171: 'SQ_PERF_SEL_OVERFLOW_PREV', + 172: 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', + 173: 'SQ_PERF_SEL_INSTS_VALU_1_PASS', + 174: 'SQ_PERF_SEL_INSTS_VALU_2_PASS', + 175: 'SQ_PERF_SEL_INSTS_VALU_4_PASS', + 176: 'SQ_PERF_SEL_INSTS_VALU_DP', + 177: 'SQ_PERF_SEL_SP_CONST_CYCLES', + 178: 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', + 179: 'SQ_PERF_SEL_ITEMS_VALU', + 180: 'SQ_PERF_SEL_ITEMS_MAX_VALU', + 181: 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', + 182: 'SQ_PERF_SEL_INSTS_DELAY_ALU_COISSUE', + 183: 'SQ_PERF_SEL_INSTS_FLAT_LOAD', + 184: 'SQ_PERF_SEL_INSTS_FLAT_STORE', + 185: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_16BIT', + 186: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_32BIT', + 187: 'SQ_PERF_SEL_INSTS_NON_VALU_EXEC_SKIPPED', + 188: 'SQ_PERF_SEL_INSTS_BARRIER_LOCK', + 189: 'SQ_PERF_SEL_INSTS_WAKEUP', + 190: 'SQ_PERF_SEL_IS_CACHE_REQ', + 191: 'SQ_PERF_SEL_INSTS_SALU_PS', + 192: 'SQ_PERF_SEL_INSTS_SALU_GS', + 193: 'SQ_PERF_SEL_INSTS_SALU_HS', + 194: 'SQ_PERF_SEL_INSTS_SALU_CS', + 195: 'SQ_PERF_SEL_INSTS_SMEM_PS', + 196: 'SQ_PERF_SEL_INSTS_SMEM_GS', + 197: 'SQ_PERF_SEL_INSTS_SMEM_HS', + 198: 'SQ_PERF_SEL_INSTS_SMEM_CS', + 199: 'SQ_PERF_SEL_INSTS_VEC32_TEX_PS', + 200: 'SQ_PERF_SEL_INSTS_VEC32_TEX_GS', + 201: 'SQ_PERF_SEL_INSTS_VEC32_TEX_HS', + 202: 'SQ_PERF_SEL_INSTS_VEC32_TEX_CS', + 203: 'SQ_PERF_SEL_INSTS_VEC32_VALU_PS', + 204: 'SQ_PERF_SEL_INSTS_VEC32_VALU_GS', + 205: 'SQ_PERF_SEL_INSTS_VEC32_VALU_HS', + 206: 'SQ_PERF_SEL_INSTS_VEC32_VALU_CS', + 207: 'SQ_PERF_SEL_WAIT_CNT_SAMPLE', + 209: 'SQ_PERF_SEL_WAIT_CNT_KM', + 210: 'SQ_PERF_SEL_WAIT_CNT_DS', + 211: 'SQ_PERF_SEL_WAIT_CNT_EXP', + 212: 'SQ_PERF_SEL_INSTS_SALU_FLOAT', + 213: 'SQ_PERF_SEL_INSTS_VGPR_ALLOC', + 214: 'SQ_PERF_SEL_INSTS_VGPR_ALLOC_FAIL', + 215: 'SQ_PERF_SEL_INSTS_LOCK', + 216: 'SQ_PERF_SEL_INSTS_VALU_COISSUE', + 217: 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_LOAD', + 218: 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_STORE', + 219: 'SQ_PERF_SEL_IS_CACHE_MISS', + 220: 'SQ_PERF_SEL_IS_CACHE_DUP_MISS', + 221: 'SQ_PERF_SEL_INST_CYCLES_VMEM_ATOMIC', + 222: 'SQ_PERF_SEL_INSTS_TEX_BLOCK_LOAD', + 224: 'SQ_PERF_SEL_INSTS_TEX_SAMPLE', + 225: 'SQ_PERF_SEL_INSTS_TEX_ATOMIC_RTN', + 226: 'SQ_PERF_SEL_INSTS_TEX_BLOCK_STORE', + 227: 'SQ_PERF_SEL_INSTS_TEX_ATOMIC_NORTN', + 228: 'SQ_PERF_SEL_INSTS_GLOBAL_SCRATCH', + 229: 'SQ_PERF_SEL_INSTS_WMMA_LOAD', + 230: 'SQ_PERF_SEL_INSTS_FLAT_ATOMIC', + 231: 'SQ_PERF_SEL_INSTS_EXP_MRT', + 232: 'SQ_PERF_SEL_INSTS_EXP_Z', + 233: 'SQ_PERF_SEL_INSTS_VEC32_VALU_WMMA', + 234: 'SQ_PERF_SEL_INSTS_VEC32_LDS_LOAD', + 235: 'SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_RTN', + 236: 'SQ_PERF_SEL_INSTS_VEC32_LDS_STORE', + 237: 'SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_NORTN', + 239: 'SQ_PERF_SEL_INSTS_VEC32_LDS_OTHER', + 241: 'SQ_PERF_SEL_INSTS_VEC32_TEX_SAMPLE', + 242: 'SQ_PERF_SEL_INSTS_VEC32_TEX_ATOMIC', + 243: 'SQ_PERF_SEL_INSTS_VEC32_FLAT_LOAD', + 244: 'SQ_PERF_SEL_INSTS_VEC32_FLAT_STORE', + 245: 'SQ_PERF_SEL_INSTS_VEC32_FLAT_ATOMIC', + 246: 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH', + 247: 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_LOAD', + 248: 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_STORE', + 249: 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_ATOMIC', + 250: 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS', + 251: 'SQ_PERF_SEL_DUMMY_END', + 287: 'SQ_PERF_SEL_DUMMY_LAST', + 288: 'SQC_PERF_SEL_LDS_BANK_CONFLICT', + 289: 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', + 290: 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', + 291: 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', + 292: 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', + 293: 'SQC_PERF_SEL_LDS_IDX_ACTIVE', + 294: 'SQC_PERF_SEL_LDS_ADDR_STALL', + 295: 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', + 296: 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', + 297: 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', + 298: 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', + 299: 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', + 300: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 301: 'SQC_PERF_SEL_ICACHE_REQ', + 302: 'SQC_PERF_SEL_ICACHE_HITS', + 303: 'SQC_PERF_SEL_ICACHE_MISSES', + 304: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', + 305: 'SQC_PERF_SEL_ICACHE_INVAL_INST', + 306: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 307: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 308: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 309: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', + 310: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 311: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 312: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 313: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 314: 'SQC_PERF_SEL_TC_REQ', + 315: 'SQC_PERF_SEL_TC_INST_REQ', + 316: 'SQC_PERF_SEL_TC_DATA_READ_REQ', + 317: 'SQC_PERF_SEL_TC_STALL', + 318: 'SQC_PERF_SEL_TC_STARVE', + 319: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 320: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 321: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 322: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 323: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 324: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 325: 'SQC_PERF_SEL_DCACHE_REQ', + 326: 'SQC_PERF_SEL_DCACHE_HITS', + 327: 'SQC_PERF_SEL_DCACHE_MISSES', + 328: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', + 329: 'SQC_PERF_SEL_DCACHE_INVAL_INST', + 330: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 331: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 332: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 333: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 334: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 335: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 336: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 337: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 338: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 339: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 340: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 341: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', + 342: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 343: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 344: 'SQC_PERF_SEL_SQ_DCACHE_REQS', + 345: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', + 346: 'SQC_PERF_SEL_TD_VGPR_BUSY', + 347: 'SQC_PERF_SEL_LDS_VGPR_BUSY', + 348: 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', + 349: 'SQC_PERF_SEL_ICACHE_GCR', + 350: 'SQC_PERF_SEL_ICACHE_GCR_HITS', + 351: 'SQC_PERF_SEL_DCACHE_GCR', + 352: 'SQC_PERF_SEL_DCACHE_GCR_HITS', + 353: 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', + 354: 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', + 355: 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', + 356: 'SQC_PERF_SEL_ICACHE_PREFETCH_REQ_CACHELINES', + 357: 'SQC_PERF_SEL_DCACHE_PREFETCH_REQ_CACHELINES', + 358: 'SQC_PERF_SEL_ICACHE_PREFETCH_MISSES', + 359: 'SQC_PERF_SEL_DCACHE_PREFETCH_MISSES', + 360: 'SQC_PERF_SEL_LDS_BANKCONF_LOAD_CNT', + 361: 'SQC_PERF_SEL_LDS_BANKCONF_STORE_CNT', + 362: 'SQC_PERF_SEL_LDS_BANKCONF_ATOMIC_CNT', + 363: 'SQC_PERF_SEL_LDS_ACTIVE_LOAD_CNT', + 364: 'SQC_PERF_SEL_LDS_ACTIVE_STORE_CNT', + 365: 'SQC_PERF_SEL_LDS_ACTIVE_ATOMIC_CNT', + 366: 'SQC_PERF_SEL_LDS_STORE_DWORDS', + 367: 'SQC_PERF_SEL_LDS_LOAD_DWORDS', + 368: 'SQC_PERF_SEL_LDS_ATOMIC_DWORDS', + 369: 'SQC_PERF_SEL_LDS_LDS_EXECUTION_STALL', + 370: 'SQC_PERF_SEL_DUMMY_LAST', + 448: 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', + 449: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', + 450: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', + 451: 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', + 452: 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', + 453: 'SP_PERF_SEL_SRC_CACHE_HIT_B0', + 454: 'SP_PERF_SEL_SRC_CACHE_HIT_B1', + 455: 'SP_PERF_SEL_SRC_CACHE_HIT_B2', + 456: 'SP_PERF_SEL_SRC_CACHE_HIT_B3', + 457: 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', + 458: 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', + 459: 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', + 460: 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', + 461: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', + 462: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', + 463: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', + 464: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', + 465: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', + 466: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', + 467: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', + 468: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', + 469: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', + 470: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', + 471: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', + 472: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', + 473: 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', + 474: 'SP_PERF_SEL_VALU_OPERAND', + 475: 'SP_PERF_SEL_VALU_VGPR_OPERAND', + 476: 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', + 477: 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', + 478: 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', + 479: 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', + 480: 'SP_PERF_SEL_VALU_STALL', + 481: 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', + 482: 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', + 483: 'SP_PERF_SEL_VALU_STALL_VDST_FWD', + 484: 'SP_PERF_SEL_VALU_STALL_SDST_FWD', + 485: 'SP_PERF_SEL_VALU_STALL_DST_STALL', + 486: 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', + 487: 'SP_PERF_SEL_VGPR_VMEM_RD', + 488: 'SP_PERF_SEL_VGPR_EXP_RD', + 489: 'SP_PERF_SEL_VGPR_SPI_WR', + 490: 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', + 491: 'SP_PERF_SEL_VGPR_WR', + 492: 'SP_PERF_SEL_VGPR_RD', + 493: 'SP_PERF_SEL_VGPR_WR_KILL', + 494: 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_EXP', + 495: 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_LDS', + 496: 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_TEX', + 497: 'SP_PERF_SEL_DUMMY_LAST', + 511: 'SQ_PERF_SEL_NONE2', +} +SQ_PERF_SEL_NONE = 0 +SQ_PERF_SEL_ACCUM_PREV = 1 +SQ_PERF_SEL_CYCLES = 2 +SQ_PERF_SEL_BUSY_CYCLES = 3 +SQ_PERF_SEL_WAVES = 4 +SQ_PERF_SEL_WAVES_32 = 5 +SQ_PERF_SEL_WAVES_64 = 6 +SQ_PERF_SEL_LEVEL_WAVES = 7 +SQ_PERF_SEL_ITEMS = 8 +SQ_PERF_SEL_WAVE32_ITEMS = 9 +SQ_PERF_SEL_WAVE64_ITEMS = 10 +SQ_PERF_SEL_PS_QUADS = 11 +SQ_PERF_SEL_EVENTS = 12 +SQ_PERF_SEL_WAVES_EQ_32 = 13 +SQ_PERF_SEL_WAVES_EQ_64 = 14 +SQ_PERF_SEL_WAVES_LT_64 = 15 +SQ_PERF_SEL_WAVES_LT_48 = 16 +SQ_PERF_SEL_WAVES_LT_32 = 17 +SQ_PERF_SEL_WAVES_LT_16 = 18 +SQ_PERF_SEL_WAVES_RESTORED = 19 +SQ_PERF_SEL_WAVES_SAVED = 20 +SQ_PERF_SEL_MSG = 21 +SQ_PERF_SEL_MSG_INTERRUPT = 22 +SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 23 +SQ_PERF_SEL_WAVE_CYCLES = 24 +SQ_PERF_SEL_WAVE_READY = 25 +SQ_PERF_SEL_WAIT_INST_ANY = 26 +SQ_PERF_SEL_WAIT_ANY = 27 +SQ_PERF_SEL_WAIT_CNT_ANY = 28 +SQ_PERF_SEL_WAIT_CNT_LOAD = 29 +SQ_PERF_SEL_WAIT_CNT_STORE = 30 +SQ_PERF_SEL_WAIT_TTRACE = 31 +SQ_PERF_SEL_WAIT_IFETCH = 32 +SQ_PERF_SEL_WAIT_BARRIER = 33 +SQ_PERF_SEL_WAIT_EXP_ALLOC = 34 +SQ_PERF_SEL_WAIT_SLEEP = 35 +SQ_PERF_SEL_WAIT_DELAY_ALU = 36 +SQ_PERF_SEL_WAIT_DEPCTR = 37 +SQ_PERF_SEL_WAIT_OTHER = 38 +SQ_PERF_SEL_INSTS_ALL = 39 +SQ_PERF_SEL_INSTS_BRANCH = 40 +SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 41 +SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 42 +SQ_PERF_SEL_INSTS_EXP = 43 +SQ_PERF_SEL_INSTS_FLAT = 44 +SQ_PERF_SEL_INSTS_LDS = 45 +SQ_PERF_SEL_INSTS_SALU = 46 +SQ_PERF_SEL_INSTS_SMEM = 47 +SQ_PERF_SEL_INSTS_SMEM_NORM = 48 +SQ_PERF_SEL_INSTS_SENDMSG = 49 +SQ_PERF_SEL_INSTS_VALU = 50 +SQ_PERF_SEL_INSTS_VALU_TRANS32 = 51 +SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 52 +SQ_PERF_SEL_INSTS_TEX = 53 +SQ_PERF_SEL_INSTS_TEX_LOAD = 54 +SQ_PERF_SEL_INSTS_TEX_STORE = 55 +SQ_PERF_SEL_INSTS_DELAY_ALU = 56 +SQ_PERF_SEL_INSTS_INTERNAL = 57 +SQ_PERF_SEL_INSTS_VEC32 = 58 +SQ_PERF_SEL_INSTS_VEC32_FLAT = 59 +SQ_PERF_SEL_INSTS_VEC32_LDS = 60 +SQ_PERF_SEL_INSTS_VEC32_VALU = 61 +SQ_PERF_SEL_VEC32_INSTS_EXP = 62 +SQ_PERF_SEL_INSTS_VEC32_VALU_TRANS32 = 63 +SQ_PERF_SEL_INSTS_VEC32_VALU_NO_COEXEC = 64 +SQ_PERF_SEL_INSTS_VEC32_TEX = 65 +SQ_PERF_SEL_INSTS_VEC32_TEX_LOAD = 66 +SQ_PERF_SEL_INSTS_VEC32_TEX_STORE = 67 +SQ_PERF_SEL_ITEM_CYCLES_VALU = 68 +SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 69 +SQ_PERF_SEL_WAVE32_INSTS = 70 +SQ_PERF_SEL_WAVE64_INSTS = 71 +SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 72 +SQ_PERF_SEL_WAVE64_HALF_SKIP = 73 +SQ_PERF_SEL_INST_LEVEL_EXP = 74 +SQ_PERF_SEL_INST_LEVEL_LDS = 75 +SQ_PERF_SEL_INST_LEVEL_SMEM = 76 +SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 77 +SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 78 +SQ_PERF_SEL_IFETCH_REQS = 79 +SQ_PERF_SEL_IFETCH_LEVEL = 80 +SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 81 +SQ_PERF_SEL_VALU_SGATHER_STALL = 82 +SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 83 +SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 84 +SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 85 +SQ_PERF_SEL_SALU_SGATHER_STALL = 86 +SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 87 +SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 88 +SQ_PERF_SEL_INST_ISSUE_SMEM_STALL = 89 +SQ_PERF_SEL_INST_ISSUE_ALL_STALL = 90 +SQ_PERF_SEL_INST_ISSUE_VALU_STALL = 91 +SQ_PERF_SEL_INST_ISSUE_SALU_STALL = 92 +SQ_PERF_SEL_INST_ISSUE_TEX_STALL = 93 +SQ_PERF_SEL_INST_ISSUE_LDS_STALL = 94 +SQ_PERF_SEL_INST_ISSUE_EXP_STALL = 96 +SQ_PERF_SEL_INST_WAITCNT_STALL = 97 +SQ_PERF_SEL_INST_BARRIER_STALL = 98 +SQ_PERF_SEL_INST_CYCLES_VALU = 99 +SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 100 +SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 101 +SQ_PERF_SEL_INST_CYCLES_VMEM = 102 +SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 103 +SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 104 +SQ_PERF_SEL_INST_CYCLES_LDS = 105 +SQ_PERF_SEL_INST_CYCLES_TEX = 106 +SQ_PERF_SEL_INST_CYCLES_FLAT = 107 +SQ_PERF_SEL_INST_CYCLES_EXP = 108 +SQ_PERF_SEL_VALU_STARVE = 109 +SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 110 +SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 111 +SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 112 +SQ_PERF_SEL_VMEM_BUS_ACTIVE = 113 +SQ_PERF_SEL_VMEM_BUS_STALL = 114 +SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 115 +SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 116 +SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 117 +SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 118 +SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 119 +SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 120 +SQ_PERF_SEL_SALU_PIPE_STALL = 121 +SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 122 +SQ_PERF_SEL_MSG_BUS_BUSY = 123 +SQ_PERF_SEL_EXP_REQ_BUS_STALL = 124 +SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 125 +SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 126 +SQ_PERF_SEL_EXP_BUS0_BUSY = 127 +SQ_PERF_SEL_EXP_BUS1_BUSY = 128 +SQ_PERF_SEL_INST_CACHE_REQ_STALL = 129 +SQ_PERF_SEL_USER0 = 130 +SQ_PERF_SEL_USER1 = 131 +SQ_PERF_SEL_USER2 = 132 +SQ_PERF_SEL_USER3 = 133 +SQ_PERF_SEL_USER4 = 134 +SQ_PERF_SEL_USER5 = 135 +SQ_PERF_SEL_USER6 = 136 +SQ_PERF_SEL_USER7 = 137 +SQ_PERF_SEL_USER8 = 138 +SQ_PERF_SEL_USER9 = 139 +SQ_PERF_SEL_USER10 = 140 +SQ_PERF_SEL_USER11 = 141 +SQ_PERF_SEL_USER12 = 142 +SQ_PERF_SEL_USER13 = 143 +SQ_PERF_SEL_USER14 = 144 +SQ_PERF_SEL_USER15 = 145 +SQ_PERF_SEL_USER_LEVEL0 = 146 +SQ_PERF_SEL_USER_LEVEL1 = 147 +SQ_PERF_SEL_USER_LEVEL2 = 148 +SQ_PERF_SEL_USER_LEVEL3 = 149 +SQ_PERF_SEL_USER_LEVEL4 = 150 +SQ_PERF_SEL_USER_LEVEL5 = 151 +SQ_PERF_SEL_USER_LEVEL6 = 152 +SQ_PERF_SEL_USER_LEVEL7 = 153 +SQ_PERF_SEL_USER_LEVEL8 = 154 +SQ_PERF_SEL_USER_LEVEL9 = 155 +SQ_PERF_SEL_USER_LEVEL10 = 156 +SQ_PERF_SEL_USER_LEVEL11 = 157 +SQ_PERF_SEL_USER_LEVEL12 = 158 +SQ_PERF_SEL_USER_LEVEL13 = 159 +SQ_PERF_SEL_USER_LEVEL14 = 160 +SQ_PERF_SEL_USER_LEVEL15 = 161 +SQ_PERF_SEL_VALU_RETURN_SDST = 162 +SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 163 +SQ_PERF_SEL_INSTS_VALU_TRANS = 164 +SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 165 +SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 166 +SQ_PERF_SEL_INSTS_VEC32_LDS_PARAM_LOAD = 167 +SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 168 +SQ_PERF_SEL_INSTS_VALU_VINTERP = 169 +SQ_PERF_SEL_INSTS_VEC32_VALU_VINTERP = 170 +SQ_PERF_SEL_OVERFLOW_PREV = 171 +SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 172 +SQ_PERF_SEL_INSTS_VALU_1_PASS = 173 +SQ_PERF_SEL_INSTS_VALU_2_PASS = 174 +SQ_PERF_SEL_INSTS_VALU_4_PASS = 175 +SQ_PERF_SEL_INSTS_VALU_DP = 176 +SQ_PERF_SEL_SP_CONST_CYCLES = 177 +SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 178 +SQ_PERF_SEL_ITEMS_VALU = 179 +SQ_PERF_SEL_ITEMS_MAX_VALU = 180 +SQ_PERF_SEL_ITEM_CYCLES_VMEM = 181 +SQ_PERF_SEL_INSTS_DELAY_ALU_COISSUE = 182 +SQ_PERF_SEL_INSTS_FLAT_LOAD = 183 +SQ_PERF_SEL_INSTS_FLAT_STORE = 184 +SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_16BIT = 185 +SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_32BIT = 186 +SQ_PERF_SEL_INSTS_NON_VALU_EXEC_SKIPPED = 187 +SQ_PERF_SEL_INSTS_BARRIER_LOCK = 188 +SQ_PERF_SEL_INSTS_WAKEUP = 189 +SQ_PERF_SEL_IS_CACHE_REQ = 190 +SQ_PERF_SEL_INSTS_SALU_PS = 191 +SQ_PERF_SEL_INSTS_SALU_GS = 192 +SQ_PERF_SEL_INSTS_SALU_HS = 193 +SQ_PERF_SEL_INSTS_SALU_CS = 194 +SQ_PERF_SEL_INSTS_SMEM_PS = 195 +SQ_PERF_SEL_INSTS_SMEM_GS = 196 +SQ_PERF_SEL_INSTS_SMEM_HS = 197 +SQ_PERF_SEL_INSTS_SMEM_CS = 198 +SQ_PERF_SEL_INSTS_VEC32_TEX_PS = 199 +SQ_PERF_SEL_INSTS_VEC32_TEX_GS = 200 +SQ_PERF_SEL_INSTS_VEC32_TEX_HS = 201 +SQ_PERF_SEL_INSTS_VEC32_TEX_CS = 202 +SQ_PERF_SEL_INSTS_VEC32_VALU_PS = 203 +SQ_PERF_SEL_INSTS_VEC32_VALU_GS = 204 +SQ_PERF_SEL_INSTS_VEC32_VALU_HS = 205 +SQ_PERF_SEL_INSTS_VEC32_VALU_CS = 206 +SQ_PERF_SEL_WAIT_CNT_SAMPLE = 207 +SQ_PERF_SEL_WAIT_CNT_KM = 209 +SQ_PERF_SEL_WAIT_CNT_DS = 210 +SQ_PERF_SEL_WAIT_CNT_EXP = 211 +SQ_PERF_SEL_INSTS_SALU_FLOAT = 212 +SQ_PERF_SEL_INSTS_VGPR_ALLOC = 213 +SQ_PERF_SEL_INSTS_VGPR_ALLOC_FAIL = 214 +SQ_PERF_SEL_INSTS_LOCK = 215 +SQ_PERF_SEL_INSTS_VALU_COISSUE = 216 +SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_LOAD = 217 +SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_STORE = 218 +SQ_PERF_SEL_IS_CACHE_MISS = 219 +SQ_PERF_SEL_IS_CACHE_DUP_MISS = 220 +SQ_PERF_SEL_INST_CYCLES_VMEM_ATOMIC = 221 +SQ_PERF_SEL_INSTS_TEX_BLOCK_LOAD = 222 +SQ_PERF_SEL_INSTS_TEX_SAMPLE = 224 +SQ_PERF_SEL_INSTS_TEX_ATOMIC_RTN = 225 +SQ_PERF_SEL_INSTS_TEX_BLOCK_STORE = 226 +SQ_PERF_SEL_INSTS_TEX_ATOMIC_NORTN = 227 +SQ_PERF_SEL_INSTS_GLOBAL_SCRATCH = 228 +SQ_PERF_SEL_INSTS_WMMA_LOAD = 229 +SQ_PERF_SEL_INSTS_FLAT_ATOMIC = 230 +SQ_PERF_SEL_INSTS_EXP_MRT = 231 +SQ_PERF_SEL_INSTS_EXP_Z = 232 +SQ_PERF_SEL_INSTS_VEC32_VALU_WMMA = 233 +SQ_PERF_SEL_INSTS_VEC32_LDS_LOAD = 234 +SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_RTN = 235 +SQ_PERF_SEL_INSTS_VEC32_LDS_STORE = 236 +SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_NORTN = 237 +SQ_PERF_SEL_INSTS_VEC32_LDS_OTHER = 239 +SQ_PERF_SEL_INSTS_VEC32_TEX_SAMPLE = 241 +SQ_PERF_SEL_INSTS_VEC32_TEX_ATOMIC = 242 +SQ_PERF_SEL_INSTS_VEC32_FLAT_LOAD = 243 +SQ_PERF_SEL_INSTS_VEC32_FLAT_STORE = 244 +SQ_PERF_SEL_INSTS_VEC32_FLAT_ATOMIC = 245 +SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH = 246 +SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_LOAD = 247 +SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_STORE = 248 +SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_ATOMIC = 249 +SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS = 250 +SQ_PERF_SEL_DUMMY_END = 251 +SQ_PERF_SEL_DUMMY_LAST = 287 +SQC_PERF_SEL_LDS_BANK_CONFLICT = 288 +SQC_PERF_SEL_LDS_ADDR_CONFLICT = 289 +SQC_PERF_SEL_LDS_UNALIGNED_STALL = 290 +SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 291 +SQC_PERF_SEL_LDS_ATOMIC_RETURN = 292 +SQC_PERF_SEL_LDS_IDX_ACTIVE = 293 +SQC_PERF_SEL_LDS_ADDR_STALL = 294 +SQC_PERF_SEL_LDS_ADDR_ACTIVE = 295 +SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 296 +SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 297 +SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 298 +SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 299 +SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 300 +SQC_PERF_SEL_ICACHE_REQ = 301 +SQC_PERF_SEL_ICACHE_HITS = 302 +SQC_PERF_SEL_ICACHE_MISSES = 303 +SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 304 +SQC_PERF_SEL_ICACHE_INVAL_INST = 305 +SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 306 +SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 307 +SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 308 +SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 309 +SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 310 +SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 311 +SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 312 +SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 313 +SQC_PERF_SEL_TC_REQ = 314 +SQC_PERF_SEL_TC_INST_REQ = 315 +SQC_PERF_SEL_TC_DATA_READ_REQ = 316 +SQC_PERF_SEL_TC_STALL = 317 +SQC_PERF_SEL_TC_STARVE = 318 +SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 319 +SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 320 +SQC_PERF_SEL_ICACHE_CACHE_STALLED = 321 +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 322 +SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 323 +SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 324 +SQC_PERF_SEL_DCACHE_REQ = 325 +SQC_PERF_SEL_DCACHE_HITS = 326 +SQC_PERF_SEL_DCACHE_MISSES = 327 +SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 328 +SQC_PERF_SEL_DCACHE_INVAL_INST = 329 +SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 330 +SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 331 +SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 332 +SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 333 +SQC_PERF_SEL_DCACHE_CACHE_STALLED = 334 +SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 335 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 336 +SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 337 +SQC_PERF_SEL_DCACHE_REQ_READ_1 = 338 +SQC_PERF_SEL_DCACHE_REQ_READ_2 = 339 +SQC_PERF_SEL_DCACHE_REQ_READ_4 = 340 +SQC_PERF_SEL_DCACHE_REQ_READ_8 = 341 +SQC_PERF_SEL_DCACHE_REQ_READ_16 = 342 +SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 343 +SQC_PERF_SEL_SQ_DCACHE_REQS = 344 +SQC_PERF_SEL_DCACHE_FLAT_REQ = 345 +SQC_PERF_SEL_TD_VGPR_BUSY = 346 +SQC_PERF_SEL_LDS_VGPR_BUSY = 347 +SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 348 +SQC_PERF_SEL_ICACHE_GCR = 349 +SQC_PERF_SEL_ICACHE_GCR_HITS = 350 +SQC_PERF_SEL_DCACHE_GCR = 351 +SQC_PERF_SEL_DCACHE_GCR_HITS = 352 +SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 353 +SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 354 +SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 355 +SQC_PERF_SEL_ICACHE_PREFETCH_REQ_CACHELINES = 356 +SQC_PERF_SEL_DCACHE_PREFETCH_REQ_CACHELINES = 357 +SQC_PERF_SEL_ICACHE_PREFETCH_MISSES = 358 +SQC_PERF_SEL_DCACHE_PREFETCH_MISSES = 359 +SQC_PERF_SEL_LDS_BANKCONF_LOAD_CNT = 360 +SQC_PERF_SEL_LDS_BANKCONF_STORE_CNT = 361 +SQC_PERF_SEL_LDS_BANKCONF_ATOMIC_CNT = 362 +SQC_PERF_SEL_LDS_ACTIVE_LOAD_CNT = 363 +SQC_PERF_SEL_LDS_ACTIVE_STORE_CNT = 364 +SQC_PERF_SEL_LDS_ACTIVE_ATOMIC_CNT = 365 +SQC_PERF_SEL_LDS_STORE_DWORDS = 366 +SQC_PERF_SEL_LDS_LOAD_DWORDS = 367 +SQC_PERF_SEL_LDS_ATOMIC_DWORDS = 368 +SQC_PERF_SEL_LDS_LDS_EXECUTION_STALL = 369 +SQC_PERF_SEL_DUMMY_LAST = 370 +SP_PERF_SEL_DST_BUF_ALLOC_STALL = 448 +SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 449 +SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 450 +SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 451 +SP_PERF_SEL_DST_BUF_ODD_DIRTY = 452 +SP_PERF_SEL_SRC_CACHE_HIT_B0 = 453 +SP_PERF_SEL_SRC_CACHE_HIT_B1 = 454 +SP_PERF_SEL_SRC_CACHE_HIT_B2 = 455 +SP_PERF_SEL_SRC_CACHE_HIT_B3 = 456 +SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 457 +SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 458 +SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 459 +SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 460 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 461 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 462 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 463 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 464 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 465 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 466 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 467 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 468 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 469 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 470 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 471 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 472 +SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 473 +SP_PERF_SEL_VALU_OPERAND = 474 +SP_PERF_SEL_VALU_VGPR_OPERAND = 475 +SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 476 +SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 477 +SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 478 +SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 479 +SP_PERF_SEL_VALU_STALL = 480 +SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 481 +SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 482 +SP_PERF_SEL_VALU_STALL_VDST_FWD = 483 +SP_PERF_SEL_VALU_STALL_SDST_FWD = 484 +SP_PERF_SEL_VALU_STALL_DST_STALL = 485 +SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 486 +SP_PERF_SEL_VGPR_VMEM_RD = 487 +SP_PERF_SEL_VGPR_EXP_RD = 488 +SP_PERF_SEL_VGPR_SPI_WR = 489 +SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 490 +SP_PERF_SEL_VGPR_WR = 491 +SP_PERF_SEL_VGPR_RD = 492 +SP_PERF_SEL_VGPR_WR_KILL = 493 +SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_EXP = 494 +SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_LDS = 495 +SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_TEX = 496 +SP_PERF_SEL_DUMMY_LAST = 497 +SQ_PERF_SEL_NONE2 = 511 +SQ_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_ROUND_MODE' +SQ_ROUND_MODE__enumvalues = { + 0: 'SQ_ROUND_NEAREST_EVEN', + 1: 'SQ_ROUND_PLUS_INFINITY', + 2: 'SQ_ROUND_MINUS_INFINITY', + 3: 'SQ_ROUND_TO_ZERO', +} +SQ_ROUND_NEAREST_EVEN = 0 +SQ_ROUND_PLUS_INFINITY = 1 +SQ_ROUND_MINUS_INFINITY = 2 +SQ_ROUND_TO_ZERO = 3 +SQ_ROUND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_BUF_TYPE' +SQ_RSRC_BUF_TYPE__enumvalues = { + 0: 'SQ_RSRC_BUF', + 1: 'SQ_RSRC_BUF_RSVD_1', + 2: 'SQ_RSRC_BUF_RSVD_2', + 3: 'SQ_RSRC_BUF_RSVD_3', +} +SQ_RSRC_BUF = 0 +SQ_RSRC_BUF_RSVD_1 = 1 +SQ_RSRC_BUF_RSVD_2 = 2 +SQ_RSRC_BUF_RSVD_3 = 3 +SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_FLAT_TYPE' +SQ_RSRC_FLAT_TYPE__enumvalues = { + 0: 'SQ_RSRC_FLAT_RSVD_0', + 1: 'SQ_RSRC_FLAT', + 2: 'SQ_RSRC_FLAT_RSVD_2', + 3: 'SQ_RSRC_FLAT_RSVD_3', +} +SQ_RSRC_FLAT_RSVD_0 = 0 +SQ_RSRC_FLAT = 1 +SQ_RSRC_FLAT_RSVD_2 = 2 +SQ_RSRC_FLAT_RSVD_3 = 3 +SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_IMG_TYPE' +SQ_RSRC_IMG_TYPE__enumvalues = { + 0: 'SQ_RSRC_IMG_RSVD_0', + 1: 'SQ_RSRC_IMG_RSVD_1', + 2: 'SQ_RSRC_IMG_RSVD_2', + 3: 'SQ_RSRC_IMG_RSVD_3', + 4: 'SQ_RSRC_IMG_RSVD_4', + 5: 'SQ_RSRC_IMG_RSVD_5', + 6: 'SQ_RSRC_IMG_RSVD_6', + 7: 'SQ_RSRC_IMG_RSVD_7', + 8: 'SQ_RSRC_IMG_1D', + 9: 'SQ_RSRC_IMG_2D', + 10: 'SQ_RSRC_IMG_3D', + 11: 'SQ_RSRC_IMG_CUBE', + 12: 'SQ_RSRC_IMG_1D_ARRAY', + 13: 'SQ_RSRC_IMG_2D_ARRAY', + 14: 'SQ_RSRC_IMG_2D_MSAA', + 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', +} +SQ_RSRC_IMG_RSVD_0 = 0 +SQ_RSRC_IMG_RSVD_1 = 1 +SQ_RSRC_IMG_RSVD_2 = 2 +SQ_RSRC_IMG_RSVD_3 = 3 +SQ_RSRC_IMG_RSVD_4 = 4 +SQ_RSRC_IMG_RSVD_5 = 5 +SQ_RSRC_IMG_RSVD_6 = 6 +SQ_RSRC_IMG_RSVD_7 = 7 +SQ_RSRC_IMG_1D = 8 +SQ_RSRC_IMG_2D = 9 +SQ_RSRC_IMG_3D = 10 +SQ_RSRC_IMG_CUBE = 11 +SQ_RSRC_IMG_1D_ARRAY = 12 +SQ_RSRC_IMG_2D_ARRAY = 13 +SQ_RSRC_IMG_2D_MSAA = 14 +SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 +SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_SEL_XYZW01' +SQ_SEL_XYZW01__enumvalues = { + 0: 'SQ_SEL_0', + 1: 'SQ_SEL_1', + 2: 'SQ_SEL_N_BC_1', + 3: 'SQ_SEL_RESERVED_1', + 4: 'SQ_SEL_X', + 5: 'SQ_SEL_Y', + 6: 'SQ_SEL_Z', + 7: 'SQ_SEL_W', +} +SQ_SEL_0 = 0 +SQ_SEL_1 = 1 +SQ_SEL_N_BC_1 = 2 +SQ_SEL_RESERVED_1 = 3 +SQ_SEL_X = 4 +SQ_SEL_Y = 5 +SQ_SEL_Z = 6 +SQ_SEL_W = 7 +SQ_SEL_XYZW01 = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_ANISO_RATIO' +SQ_TEX_ANISO_RATIO__enumvalues = { + 0: 'SQ_TEX_ANISO_RATIO_1', + 1: 'SQ_TEX_ANISO_RATIO_2', + 2: 'SQ_TEX_ANISO_RATIO_4', + 3: 'SQ_TEX_ANISO_RATIO_8', + 4: 'SQ_TEX_ANISO_RATIO_16', +} +SQ_TEX_ANISO_RATIO_1 = 0 +SQ_TEX_ANISO_RATIO_2 = 1 +SQ_TEX_ANISO_RATIO_4 = 2 +SQ_TEX_ANISO_RATIO_8 = 3 +SQ_TEX_ANISO_RATIO_16 = 4 +SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_BORDER_COLOR' +SQ_TEX_BORDER_COLOR__enumvalues = { + 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 3: 'SQ_TEX_BORDER_COLOR_REGISTER', +} +SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 +SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 +SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 +SQ_TEX_BORDER_COLOR_REGISTER = 3 +SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_CLAMP' +SQ_TEX_CLAMP__enumvalues = { + 0: 'SQ_TEX_WRAP', + 1: 'SQ_TEX_MIRROR', + 2: 'SQ_TEX_CLAMP_LAST_TEXEL', + 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 4: 'SQ_TEX_CLAMP_HALF_BORDER', + 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', + 6: 'SQ_TEX_CLAMP_BORDER', + 7: 'SQ_TEX_MIRROR_ONCE_BORDER', +} +SQ_TEX_WRAP = 0 +SQ_TEX_MIRROR = 1 +SQ_TEX_CLAMP_LAST_TEXEL = 2 +SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 +SQ_TEX_CLAMP_HALF_BORDER = 4 +SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 +SQ_TEX_CLAMP_BORDER = 6 +SQ_TEX_MIRROR_ONCE_BORDER = 7 +SQ_TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_DEPTH_COMPARE' +SQ_TEX_DEPTH_COMPARE__enumvalues = { + 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', + 1: 'SQ_TEX_DEPTH_COMPARE_LESS', + 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', + 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', + 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', + 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', + 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', +} +SQ_TEX_DEPTH_COMPARE_NEVER = 0 +SQ_TEX_DEPTH_COMPARE_LESS = 1 +SQ_TEX_DEPTH_COMPARE_EQUAL = 2 +SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 +SQ_TEX_DEPTH_COMPARE_GREATER = 4 +SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 +SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 +SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 +SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_MIP_FILTER' +SQ_TEX_MIP_FILTER__enumvalues = { + 0: 'SQ_TEX_MIP_FILTER_NONE', + 1: 'SQ_TEX_MIP_FILTER_POINT', + 2: 'SQ_TEX_MIP_FILTER_LINEAR', + 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', +} +SQ_TEX_MIP_FILTER_NONE = 0 +SQ_TEX_MIP_FILTER_POINT = 1 +SQ_TEX_MIP_FILTER_LINEAR = 2 +SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 +SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_XY_FILTER' +SQ_TEX_XY_FILTER__enumvalues = { + 0: 'SQ_TEX_XY_FILTER_POINT', + 1: 'SQ_TEX_XY_FILTER_BILINEAR', + 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', + 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', +} +SQ_TEX_XY_FILTER_POINT = 0 +SQ_TEX_XY_FILTER_BILINEAR = 1 +SQ_TEX_XY_FILTER_ANISO_POINT = 2 +SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 +SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_Z_FILTER' +SQ_TEX_Z_FILTER__enumvalues = { + 0: 'SQ_TEX_Z_FILTER_NONE', + 1: 'SQ_TEX_Z_FILTER_POINT', + 2: 'SQ_TEX_Z_FILTER_LINEAR', +} +SQ_TEX_Z_FILTER_NONE = 0 +SQ_TEX_Z_FILTER_POINT = 1 +SQ_TEX_Z_FILTER_LINEAR = 2 +SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WATCH_MODES' +SQ_WATCH_MODES__enumvalues = { + 0: 'SQ_WATCH_MODE_READ', + 1: 'SQ_WATCH_MODE_NONREAD', + 2: 'SQ_WATCH_MODE_ATOMIC', + 3: 'SQ_WATCH_MODE_ALL', +} +SQ_WATCH_MODE_READ = 0 +SQ_WATCH_MODE_NONREAD = 1 +SQ_WATCH_MODE_ATOMIC = 2 +SQ_WATCH_MODE_ALL = 3 +SQ_WATCH_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_FWD_PROG_INTERVAL' +SQ_WAVE_FWD_PROG_INTERVAL__enumvalues = { + 0: 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', + 1: 'SQ_WAVE_FWD_PROG_INTERVAL_256', + 2: 'SQ_WAVE_FWD_PROG_INTERVAL_1024', + 3: 'SQ_WAVE_FWD_PROG_INTERVAL_4096', +} +SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0 +SQ_WAVE_FWD_PROG_INTERVAL_256 = 1 +SQ_WAVE_FWD_PROG_INTERVAL_1024 = 2 +SQ_WAVE_FWD_PROG_INTERVAL_4096 = 3 +SQ_WAVE_FWD_PROG_INTERVAL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_SCHED_MODES' +SQ_WAVE_SCHED_MODES__enumvalues = { + 0: 'SQ_WAVE_SCHED_MODE_NORMAL', + 1: 'SQ_WAVE_SCHED_MODE_EXPERT', + 2: 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST_VM_VSRC', +} +SQ_WAVE_SCHED_MODE_NORMAL = 0 +SQ_WAVE_SCHED_MODE_EXPERT = 1 +SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST_VM_VSRC = 2 +SQ_WAVE_SCHED_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_TYPE' +SQ_WAVE_TYPE__enumvalues = { + 0: 'SQ_WAVE_TYPE_PS', + 1: 'SQ_WAVE_TYPE_RSVD0', + 2: 'SQ_WAVE_TYPE_GS', + 3: 'SQ_WAVE_TYPE_RSVD1', + 4: 'SQ_WAVE_TYPE_HS', + 5: 'SQ_WAVE_TYPE_RSVD2', + 6: 'SQ_WAVE_TYPE_CS', + 7: 'SQ_WAVE_TYPE_PS1', + 8: 'SQ_WAVE_TYPE_PS2', + 9: 'SQ_WAVE_TYPE_PS3', +} +SQ_WAVE_TYPE_PS = 0 +SQ_WAVE_TYPE_RSVD0 = 1 +SQ_WAVE_TYPE_GS = 2 +SQ_WAVE_TYPE_RSVD1 = 3 +SQ_WAVE_TYPE_HS = 4 +SQ_WAVE_TYPE_RSVD2 = 5 +SQ_WAVE_TYPE_CS = 6 +SQ_WAVE_TYPE_PS1 = 7 +SQ_WAVE_TYPE_PS2 = 8 +SQ_WAVE_TYPE_PS3 = 9 +SQ_WAVE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'GL1A_PERF_SEL' +GL1A_PERF_SEL__enumvalues = { + 0: 'GL1A_PERF_SEL_BUSY', + 1: 'GL1A_PERF_SEL_STALL_GL1C0', + 2: 'GL1A_PERF_SEL_STALL_GL1C1', + 3: 'GL1A_PERF_SEL_STALL_GL1C2', + 4: 'GL1A_PERF_SEL_STALL_GL1C3', + 5: 'GL1A_PERF_SEL_REQUEST_GL1C0', + 6: 'GL1A_PERF_SEL_REQUEST_GL1C1', + 7: 'GL1A_PERF_SEL_REQUEST_GL1C2', + 8: 'GL1A_PERF_SEL_REQUEST_GL1C3', + 9: 'GL1A_PERF_SEL_WDS_32B_GL1C0', + 10: 'GL1A_PERF_SEL_WDS_32B_GL1C1', + 11: 'GL1A_PERF_SEL_WDS_32B_GL1C2', + 12: 'GL1A_PERF_SEL_WDS_32B_GL1C3', + 13: 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', + 14: 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', + 15: 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', + 16: 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', + 17: 'GL1A_PERF_SEL_ARB_REQUESTS', + 18: 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', + 19: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', + 20: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', + 21: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', + 22: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', + 23: 'GL1A_PERF_SEL_CYCLE', +} +GL1A_PERF_SEL_BUSY = 0 +GL1A_PERF_SEL_STALL_GL1C0 = 1 +GL1A_PERF_SEL_STALL_GL1C1 = 2 +GL1A_PERF_SEL_STALL_GL1C2 = 3 +GL1A_PERF_SEL_STALL_GL1C3 = 4 +GL1A_PERF_SEL_REQUEST_GL1C0 = 5 +GL1A_PERF_SEL_REQUEST_GL1C1 = 6 +GL1A_PERF_SEL_REQUEST_GL1C2 = 7 +GL1A_PERF_SEL_REQUEST_GL1C3 = 8 +GL1A_PERF_SEL_WDS_32B_GL1C0 = 9 +GL1A_PERF_SEL_WDS_32B_GL1C1 = 10 +GL1A_PERF_SEL_WDS_32B_GL1C2 = 11 +GL1A_PERF_SEL_WDS_32B_GL1C3 = 12 +GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 13 +GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 14 +GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 15 +GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 16 +GL1A_PERF_SEL_ARB_REQUESTS = 17 +GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 18 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 19 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 20 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 21 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 22 +GL1A_PERF_SEL_CYCLE = 23 +GL1A_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1C_PERF_SEL' +GL1C_PERF_SEL__enumvalues = { + 0: 'GL1C_PERF_SEL_CYCLE', + 1: 'GL1C_PERF_SEL_BUSY', + 2: 'GL1C_PERF_SEL_STARVE', + 3: 'GL1C_PERF_SEL_ARB_RET_LEVEL', + 4: 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', + 5: 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', + 6: 'GL1C_PERF_SEL_REQ', + 7: 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', + 8: 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 9: 'GL1C_PERF_SEL_REQ_NOP_ACK', + 10: 'GL1C_PERF_SEL_REQ_NOP_RTN0', + 11: 'GL1C_PERF_SEL_REQ_READ', + 12: 'GL1C_PERF_SEL_REQ_READ_128B', + 13: 'GL1C_PERF_SEL_REQ_READ_32B', + 14: 'GL1C_PERF_SEL_REQ_READ_64B', + 15: 'GL1C_PERF_SEL_REQ_WRITE', + 16: 'GL1C_PERF_SEL_REQ_WRITE_32B', + 17: 'GL1C_PERF_SEL_REQ_WRITE_64B', + 18: 'GL1C_PERF_SEL_STALL_GL2_GL1', + 19: 'GL1C_PERF_SEL_STALL_BUFFER_FULL', + 20: 'GL1C_PERF_SEL_STALL_VM', + 21: 'GL1C_PERF_SEL_REQ_CLIENT0', + 22: 'GL1C_PERF_SEL_REQ_CLIENT1', + 23: 'GL1C_PERF_SEL_REQ_CLIENT2', + 24: 'GL1C_PERF_SEL_REQ_CLIENT3', + 25: 'GL1C_PERF_SEL_REQ_CLIENT4', + 26: 'GL1C_PERF_SEL_REQ_CLIENT5', + 27: 'GL1C_PERF_SEL_REQ_CLIENT6', + 28: 'GL1C_PERF_SEL_REQ_CLIENT7', + 29: 'GL1C_PERF_SEL_REQ_CLIENT8', + 30: 'GL1C_PERF_SEL_REQ_CLIENT9', + 31: 'GL1C_PERF_SEL_REQ_CLIENT10', + 32: 'GL1C_PERF_SEL_REQ_CLIENT11', + 33: 'GL1C_PERF_SEL_REQ_CLIENT12', + 34: 'GL1C_PERF_SEL_REQ_CLIENT13', + 35: 'GL1C_PERF_SEL_REQ_CLIENT14', + 36: 'GL1C_PERF_SEL_REQ_CLIENT15', + 37: 'GL1C_PERF_SEL_REQ_CLIENT16', + 38: 'GL1C_PERF_SEL_REQ_CLIENT17', + 39: 'GL1C_PERF_SEL_REQ_CLIENT18', + 40: 'GL1C_PERF_SEL_REQ_CLIENT19', + 41: 'GL1C_PERF_SEL_REQ_CLIENT20', + 42: 'GL1C_PERF_SEL_REQ_CLIENT21', + 43: 'GL1C_PERF_SEL_REQ_CLIENT22', + 44: 'GL1C_PERF_SEL_REQ_CLIENT23', + 45: 'GL1C_PERF_SEL_REQ_CLIENT24', + 46: 'GL1C_PERF_SEL_REQ_CLIENT25', + 47: 'GL1C_PERF_SEL_REQ_CLIENT26', + 48: 'GL1C_PERF_SEL_REQ_CLIENT27', + 49: 'GL1C_PERF_SEL_UTCL0_REQUEST', + 50: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', + 51: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', + 52: 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', + 53: 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', + 54: 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', + 55: 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 56: 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 57: 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 58: 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 59: 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', + 60: 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 61: 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', + 62: 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', + 63: 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', + 64: 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', + 65: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', + 66: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', + 67: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', + 68: 'GL1C_PERF_SEL_UTCL0_GPA3_REQUEST', +} +GL1C_PERF_SEL_CYCLE = 0 +GL1C_PERF_SEL_BUSY = 1 +GL1C_PERF_SEL_STARVE = 2 +GL1C_PERF_SEL_ARB_RET_LEVEL = 3 +GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 4 +GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 +GL1C_PERF_SEL_REQ = 6 +GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 +GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 +GL1C_PERF_SEL_REQ_NOP_ACK = 9 +GL1C_PERF_SEL_REQ_NOP_RTN0 = 10 +GL1C_PERF_SEL_REQ_READ = 11 +GL1C_PERF_SEL_REQ_READ_128B = 12 +GL1C_PERF_SEL_REQ_READ_32B = 13 +GL1C_PERF_SEL_REQ_READ_64B = 14 +GL1C_PERF_SEL_REQ_WRITE = 15 +GL1C_PERF_SEL_REQ_WRITE_32B = 16 +GL1C_PERF_SEL_REQ_WRITE_64B = 17 +GL1C_PERF_SEL_STALL_GL2_GL1 = 18 +GL1C_PERF_SEL_STALL_BUFFER_FULL = 19 +GL1C_PERF_SEL_STALL_VM = 20 +GL1C_PERF_SEL_REQ_CLIENT0 = 21 +GL1C_PERF_SEL_REQ_CLIENT1 = 22 +GL1C_PERF_SEL_REQ_CLIENT2 = 23 +GL1C_PERF_SEL_REQ_CLIENT3 = 24 +GL1C_PERF_SEL_REQ_CLIENT4 = 25 +GL1C_PERF_SEL_REQ_CLIENT5 = 26 +GL1C_PERF_SEL_REQ_CLIENT6 = 27 +GL1C_PERF_SEL_REQ_CLIENT7 = 28 +GL1C_PERF_SEL_REQ_CLIENT8 = 29 +GL1C_PERF_SEL_REQ_CLIENT9 = 30 +GL1C_PERF_SEL_REQ_CLIENT10 = 31 +GL1C_PERF_SEL_REQ_CLIENT11 = 32 +GL1C_PERF_SEL_REQ_CLIENT12 = 33 +GL1C_PERF_SEL_REQ_CLIENT13 = 34 +GL1C_PERF_SEL_REQ_CLIENT14 = 35 +GL1C_PERF_SEL_REQ_CLIENT15 = 36 +GL1C_PERF_SEL_REQ_CLIENT16 = 37 +GL1C_PERF_SEL_REQ_CLIENT17 = 38 +GL1C_PERF_SEL_REQ_CLIENT18 = 39 +GL1C_PERF_SEL_REQ_CLIENT19 = 40 +GL1C_PERF_SEL_REQ_CLIENT20 = 41 +GL1C_PERF_SEL_REQ_CLIENT21 = 42 +GL1C_PERF_SEL_REQ_CLIENT22 = 43 +GL1C_PERF_SEL_REQ_CLIENT23 = 44 +GL1C_PERF_SEL_REQ_CLIENT24 = 45 +GL1C_PERF_SEL_REQ_CLIENT25 = 46 +GL1C_PERF_SEL_REQ_CLIENT26 = 47 +GL1C_PERF_SEL_REQ_CLIENT27 = 48 +GL1C_PERF_SEL_UTCL0_REQUEST = 49 +GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 50 +GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 51 +GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 52 +GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 53 +GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 54 +GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 55 +GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 56 +GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 57 +GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 58 +GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 59 +GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 60 +GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 61 +GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 62 +GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 63 +GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 64 +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 65 +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 66 +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 67 +GL1C_PERF_SEL_UTCL0_GPA3_REQUEST = 68 +GL1C_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1XA_PERF_SEL' +GL1XA_PERF_SEL__enumvalues = { + 0: 'GL1XA_PERF_SEL_BUSY', + 1: 'GL1XA_PERF_SEL_STALL_GL1XC0', + 2: 'GL1XA_PERF_SEL_STALL_GL1XC1', + 3: 'GL1XA_PERF_SEL_STALL_GL1XC2', + 4: 'GL1XA_PERF_SEL_STALL_GL1XC3', + 5: 'GL1XA_PERF_SEL_REQUEST_GL1XC0', + 6: 'GL1XA_PERF_SEL_REQUEST_GL1XC1', + 7: 'GL1XA_PERF_SEL_REQUEST_GL1XC2', + 8: 'GL1XA_PERF_SEL_REQUEST_GL1XC3', + 9: 'GL1XA_PERF_SEL_WDS_32B_GL1XC0', + 10: 'GL1XA_PERF_SEL_WDS_32B_GL1XC1', + 11: 'GL1XA_PERF_SEL_WDS_32B_GL1XC2', + 12: 'GL1XA_PERF_SEL_WDS_32B_GL1XC3', + 13: 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC0', + 14: 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC1', + 15: 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC2', + 16: 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC3', + 17: 'GL1XA_PERF_SEL_ARB_REQUESTS', + 18: 'GL1XA_PERF_SEL_REQ_INFLIGHT_LEVEL', + 19: 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC0', + 20: 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC1', + 21: 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC2', + 22: 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC3', + 23: 'GL1XA_PERF_SEL_CYCLE', +} +GL1XA_PERF_SEL_BUSY = 0 +GL1XA_PERF_SEL_STALL_GL1XC0 = 1 +GL1XA_PERF_SEL_STALL_GL1XC1 = 2 +GL1XA_PERF_SEL_STALL_GL1XC2 = 3 +GL1XA_PERF_SEL_STALL_GL1XC3 = 4 +GL1XA_PERF_SEL_REQUEST_GL1XC0 = 5 +GL1XA_PERF_SEL_REQUEST_GL1XC1 = 6 +GL1XA_PERF_SEL_REQUEST_GL1XC2 = 7 +GL1XA_PERF_SEL_REQUEST_GL1XC3 = 8 +GL1XA_PERF_SEL_WDS_32B_GL1XC0 = 9 +GL1XA_PERF_SEL_WDS_32B_GL1XC1 = 10 +GL1XA_PERF_SEL_WDS_32B_GL1XC2 = 11 +GL1XA_PERF_SEL_WDS_32B_GL1XC3 = 12 +GL1XA_PERF_SEL_BURST_COUNT_GL1XC0 = 13 +GL1XA_PERF_SEL_BURST_COUNT_GL1XC1 = 14 +GL1XA_PERF_SEL_BURST_COUNT_GL1XC2 = 15 +GL1XA_PERF_SEL_BURST_COUNT_GL1XC3 = 16 +GL1XA_PERF_SEL_ARB_REQUESTS = 17 +GL1XA_PERF_SEL_REQ_INFLIGHT_LEVEL = 18 +GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC0 = 19 +GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC1 = 20 +GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC2 = 21 +GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC3 = 22 +GL1XA_PERF_SEL_CYCLE = 23 +GL1XA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1XC_PERF_SEL' +GL1XC_PERF_SEL__enumvalues = { + 0: 'GL1XC_PERF_SEL_CYCLE', + 1: 'GL1XC_PERF_SEL_BUSY', + 2: 'GL1XC_PERF_SEL_STARVE', + 3: 'GL1XC_PERF_SEL_ARB_RET_LEVEL', + 4: 'GL1XC_PERF_SEL_GL2_REQ_READ_LATENCY', + 5: 'GL1XC_PERF_SEL_GL2_REQ_WRITE_LATENCY', + 6: 'GL1XC_PERF_SEL_REQ', + 7: 'GL1XC_PERF_SEL_REQ_ATOMIC_WITH_RET', + 8: 'GL1XC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 9: 'GL1XC_PERF_SEL_REQ_NOP_ACK', + 10: 'GL1XC_PERF_SEL_REQ_NOP_RTN0', + 11: 'GL1XC_PERF_SEL_REQ_READ', + 12: 'GL1XC_PERF_SEL_REQ_READ_128B', + 13: 'GL1XC_PERF_SEL_REQ_READ_32B', + 14: 'GL1XC_PERF_SEL_REQ_READ_64B', + 15: 'GL1XC_PERF_SEL_REQ_WRITE', + 16: 'GL1XC_PERF_SEL_REQ_WRITE_32B', + 17: 'GL1XC_PERF_SEL_REQ_WRITE_64B', + 18: 'GL1XC_PERF_SEL_STALL_GL2_GL1', + 19: 'GL1XC_PERF_SEL_STALL_BUFFER_FULL', + 20: 'GL1XC_PERF_SEL_STALL_VM', + 21: 'GL1XC_PERF_SEL_REQ_CLIENT0', + 22: 'GL1XC_PERF_SEL_REQ_CLIENT1', + 23: 'GL1XC_PERF_SEL_REQ_CLIENT2', + 24: 'GL1XC_PERF_SEL_REQ_CLIENT3', + 25: 'GL1XC_PERF_SEL_REQ_CLIENT4', + 26: 'GL1XC_PERF_SEL_REQ_CLIENT5', + 27: 'GL1XC_PERF_SEL_REQ_CLIENT6', + 28: 'GL1XC_PERF_SEL_REQ_CLIENT7', + 29: 'GL1XC_PERF_SEL_REQ_CLIENT8', + 30: 'GL1XC_PERF_SEL_REQ_CLIENT9', + 31: 'GL1XC_PERF_SEL_REQ_CLIENT10', + 32: 'GL1XC_PERF_SEL_REQ_CLIENT11', + 33: 'GL1XC_PERF_SEL_REQ_CLIENT12', + 34: 'GL1XC_PERF_SEL_REQ_CLIENT13', + 35: 'GL1XC_PERF_SEL_REQ_CLIENT14', + 36: 'GL1XC_PERF_SEL_REQ_CLIENT15', + 37: 'GL1XC_PERF_SEL_REQ_CLIENT16', + 38: 'GL1XC_PERF_SEL_REQ_CLIENT17', + 39: 'GL1XC_PERF_SEL_REQ_CLIENT18', + 40: 'GL1XC_PERF_SEL_REQ_CLIENT19', + 41: 'GL1XC_PERF_SEL_REQ_CLIENT20', + 42: 'GL1XC_PERF_SEL_REQ_CLIENT21', + 43: 'GL1XC_PERF_SEL_REQ_CLIENT22', + 44: 'GL1XC_PERF_SEL_REQ_CLIENT23', + 45: 'GL1XC_PERF_SEL_REQ_CLIENT24', + 46: 'GL1XC_PERF_SEL_REQ_CLIENT25', + 47: 'GL1XC_PERF_SEL_REQ_CLIENT26', + 48: 'GL1XC_PERF_SEL_REQ_CLIENT27', + 49: 'GL1XC_PERF_SEL_UTCL0_REQUEST', + 50: 'GL1XC_PERF_SEL_UTCL0_TRANSLATION_HIT', + 51: 'GL1XC_PERF_SEL_UTCL0_TRANSLATION_MISS', + 52: 'GL1XC_PERF_SEL_UTCL0_PERMISSION_MISS', + 53: 'GL1XC_PERF_SEL_UTCL0_MISS_UNDER_MISS', + 54: 'GL1XC_PERF_SEL_UTCL0_LFIFO_FULL', + 55: 'GL1XC_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 56: 'GL1XC_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 57: 'GL1XC_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 58: 'GL1XC_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 59: 'GL1XC_PERF_SEL_UTCL0_STALL_MULTI_MISS', + 60: 'GL1XC_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 61: 'GL1XC_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', + 62: 'GL1XC_PERF_SEL_CLIENT_UTCL0_INFLIGHT', + 63: 'GL1XC_PERF_SEL_UTCL0_UTCL1_INFLIGHT', + 64: 'GL1XC_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', + 65: 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', + 66: 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', + 67: 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', + 68: 'GL1XC_PERF_SEL_UTCL0_GPA3_REQUEST', +} +GL1XC_PERF_SEL_CYCLE = 0 +GL1XC_PERF_SEL_BUSY = 1 +GL1XC_PERF_SEL_STARVE = 2 +GL1XC_PERF_SEL_ARB_RET_LEVEL = 3 +GL1XC_PERF_SEL_GL2_REQ_READ_LATENCY = 4 +GL1XC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 +GL1XC_PERF_SEL_REQ = 6 +GL1XC_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 +GL1XC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 +GL1XC_PERF_SEL_REQ_NOP_ACK = 9 +GL1XC_PERF_SEL_REQ_NOP_RTN0 = 10 +GL1XC_PERF_SEL_REQ_READ = 11 +GL1XC_PERF_SEL_REQ_READ_128B = 12 +GL1XC_PERF_SEL_REQ_READ_32B = 13 +GL1XC_PERF_SEL_REQ_READ_64B = 14 +GL1XC_PERF_SEL_REQ_WRITE = 15 +GL1XC_PERF_SEL_REQ_WRITE_32B = 16 +GL1XC_PERF_SEL_REQ_WRITE_64B = 17 +GL1XC_PERF_SEL_STALL_GL2_GL1 = 18 +GL1XC_PERF_SEL_STALL_BUFFER_FULL = 19 +GL1XC_PERF_SEL_STALL_VM = 20 +GL1XC_PERF_SEL_REQ_CLIENT0 = 21 +GL1XC_PERF_SEL_REQ_CLIENT1 = 22 +GL1XC_PERF_SEL_REQ_CLIENT2 = 23 +GL1XC_PERF_SEL_REQ_CLIENT3 = 24 +GL1XC_PERF_SEL_REQ_CLIENT4 = 25 +GL1XC_PERF_SEL_REQ_CLIENT5 = 26 +GL1XC_PERF_SEL_REQ_CLIENT6 = 27 +GL1XC_PERF_SEL_REQ_CLIENT7 = 28 +GL1XC_PERF_SEL_REQ_CLIENT8 = 29 +GL1XC_PERF_SEL_REQ_CLIENT9 = 30 +GL1XC_PERF_SEL_REQ_CLIENT10 = 31 +GL1XC_PERF_SEL_REQ_CLIENT11 = 32 +GL1XC_PERF_SEL_REQ_CLIENT12 = 33 +GL1XC_PERF_SEL_REQ_CLIENT13 = 34 +GL1XC_PERF_SEL_REQ_CLIENT14 = 35 +GL1XC_PERF_SEL_REQ_CLIENT15 = 36 +GL1XC_PERF_SEL_REQ_CLIENT16 = 37 +GL1XC_PERF_SEL_REQ_CLIENT17 = 38 +GL1XC_PERF_SEL_REQ_CLIENT18 = 39 +GL1XC_PERF_SEL_REQ_CLIENT19 = 40 +GL1XC_PERF_SEL_REQ_CLIENT20 = 41 +GL1XC_PERF_SEL_REQ_CLIENT21 = 42 +GL1XC_PERF_SEL_REQ_CLIENT22 = 43 +GL1XC_PERF_SEL_REQ_CLIENT23 = 44 +GL1XC_PERF_SEL_REQ_CLIENT24 = 45 +GL1XC_PERF_SEL_REQ_CLIENT25 = 46 +GL1XC_PERF_SEL_REQ_CLIENT26 = 47 +GL1XC_PERF_SEL_REQ_CLIENT27 = 48 +GL1XC_PERF_SEL_UTCL0_REQUEST = 49 +GL1XC_PERF_SEL_UTCL0_TRANSLATION_HIT = 50 +GL1XC_PERF_SEL_UTCL0_TRANSLATION_MISS = 51 +GL1XC_PERF_SEL_UTCL0_PERMISSION_MISS = 52 +GL1XC_PERF_SEL_UTCL0_MISS_UNDER_MISS = 53 +GL1XC_PERF_SEL_UTCL0_LFIFO_FULL = 54 +GL1XC_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 55 +GL1XC_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 56 +GL1XC_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 57 +GL1XC_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 58 +GL1XC_PERF_SEL_UTCL0_STALL_MULTI_MISS = 59 +GL1XC_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 60 +GL1XC_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 61 +GL1XC_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 62 +GL1XC_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 63 +GL1XC_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 64 +GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 65 +GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 66 +GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 67 +GL1XC_PERF_SEL_UTCL0_GPA3_REQUEST = 68 +GL1XC_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBMH_PERF_SEL' +GRBMH_PERF_SEL__enumvalues = { + 0: 'GRBMH_PERF_SEL_COUNT', + 1: 'GRBMH_PERF_SEL_USER_DEFINED', + 2: 'GRBMH_PERF_SEL_CB_BUSY', + 3: 'GRBMH_PERF_SEL_CB_CLEAN', + 4: 'GRBMH_PERF_SEL_DB_BUSY', + 5: 'GRBMH_PERF_SEL_DB_CLEAN', + 6: 'GRBMH_PERF_SEL_SC_BUSY', + 7: 'GRBMH_PERF_SEL_SC_CLEAN', + 9: 'GRBMH_PERF_SEL_SPI_BUSY', + 10: 'GRBMH_PERF_SEL_SX_BUSY', + 11: 'GRBMH_PERF_SEL_TA_BUSY', + 12: 'GRBMH_PERF_SEL_EA_BUSY', + 13: 'GRBMH_PERF_SEL_EA_LINK_BUSY', + 14: 'GRBMH_PERF_SEL_PA_BUSY', + 15: 'GRBMH_PERF_SEL_BCI_BUSY', + 16: 'GRBMH_PERF_SEL_GL2A_BUSY', + 17: 'GRBMH_PERF_SEL_GL2C_BUSY', + 18: 'GRBMH_PERF_SEL_UTCL1_BUSY', + 19: 'GRBMH_PERF_SEL_TCP_BUSY', + 20: 'GRBMH_PERF_SEL_GL1A_BUSY', + 21: 'GRBMH_PERF_SEL_GL1CC_BUSY', + 22: 'GRBMH_PERF_SEL_GL1XCC_BUSY', + 23: 'GRBMH_PERF_SEL_PC_BUSY', + 24: 'GRBMH_PERF_SEL_GE_BUSY', + 25: 'GRBMH_PERF_SEL_RLC_BUSY', +} +GRBMH_PERF_SEL_COUNT = 0 +GRBMH_PERF_SEL_USER_DEFINED = 1 +GRBMH_PERF_SEL_CB_BUSY = 2 +GRBMH_PERF_SEL_CB_CLEAN = 3 +GRBMH_PERF_SEL_DB_BUSY = 4 +GRBMH_PERF_SEL_DB_CLEAN = 5 +GRBMH_PERF_SEL_SC_BUSY = 6 +GRBMH_PERF_SEL_SC_CLEAN = 7 +GRBMH_PERF_SEL_SPI_BUSY = 9 +GRBMH_PERF_SEL_SX_BUSY = 10 +GRBMH_PERF_SEL_TA_BUSY = 11 +GRBMH_PERF_SEL_EA_BUSY = 12 +GRBMH_PERF_SEL_EA_LINK_BUSY = 13 +GRBMH_PERF_SEL_PA_BUSY = 14 +GRBMH_PERF_SEL_BCI_BUSY = 15 +GRBMH_PERF_SEL_GL2A_BUSY = 16 +GRBMH_PERF_SEL_GL2C_BUSY = 17 +GRBMH_PERF_SEL_UTCL1_BUSY = 18 +GRBMH_PERF_SEL_TCP_BUSY = 19 +GRBMH_PERF_SEL_GL1A_BUSY = 20 +GRBMH_PERF_SEL_GL1CC_BUSY = 21 +GRBMH_PERF_SEL_GL1XCC_BUSY = 22 +GRBMH_PERF_SEL_PC_BUSY = 23 +GRBMH_PERF_SEL_GE_BUSY = 24 +GRBMH_PERF_SEL_RLC_BUSY = 25 +GRBMH_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TA_PERFCOUNT_SEL' +TA_PERFCOUNT_SEL__enumvalues = { + 0: 'TA_PERF_SEL_NULL', + 1: 'TA_PERF_SEL_image_sampler_has_offset_instructions', + 2: 'TA_PERF_SEL_image_sampler_has_bias_instructions', + 3: 'TA_PERF_SEL_image_sampler_has_reference_instructions', + 4: 'TA_PERF_SEL_image_sampler_has_ds_instructions', + 5: 'TA_PERF_SEL_image_sampler_has_dt_instructions', + 6: 'TA_PERF_SEL_image_sampler_has_dr_instructions', + 7: 'TA_PERF_SEL_gradient_busy', + 8: 'TA_PERF_SEL_gradient_fifo_busy', + 9: 'TA_PERF_SEL_lod_busy', + 10: 'TA_PERF_SEL_lod_fifo_busy', + 11: 'TA_PERF_SEL_addresser_busy', + 12: 'TA_PERF_SEL_addresser_fifo_busy', + 13: 'TA_PERF_SEL_aligner_busy', + 14: 'TA_PERF_SEL_write_path_busy', + 15: 'TA_PERF_SEL_ta_busy', + 16: 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', + 17: 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', + 18: 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', + 19: 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', + 20: 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', + 21: 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', + 22: 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', + 23: 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', + 24: 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', + 25: 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', + 26: 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', + 27: 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', + 28: 'TA_PERF_SEL_image_sampler_has_t_instructions', + 29: 'TA_PERF_SEL_image_sampler_has_r_instructions', + 30: 'TA_PERF_SEL_image_sampler_has_q_instructions', + 32: 'TA_PERF_SEL_total_wavefronts', + 33: 'TA_PERF_SEL_gradient_cycles', + 34: 'TA_PERF_SEL_walker_cycles', + 35: 'TA_PERF_SEL_aligner_cycles', + 36: 'TA_PERF_SEL_image_wavefronts', + 37: 'TA_PERF_SEL_image_read_wavefronts', + 38: 'TA_PERF_SEL_image_store_wavefronts', + 39: 'TA_PERF_SEL_image_atomic_wavefronts', + 40: 'TA_PERF_SEL_image_sampler_total_cycles', + 41: 'TA_PERF_SEL_image_nosampler_total_cycles', + 42: 'TA_PERF_SEL_flat_total_cycles', + 44: 'TA_PERF_SEL_buffer_wavefronts', + 45: 'TA_PERF_SEL_buffer_load_wavefronts', + 46: 'TA_PERF_SEL_buffer_store_wavefronts', + 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', + 49: 'TA_PERF_SEL_buffer_total_cycles', + 50: 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', + 51: 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', + 52: 'TA_PERF_SEL_buffer_has_index_instructions', + 53: 'TA_PERF_SEL_buffer_has_offset_instructions', + 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 56: 'TA_PERF_SEL_image_sampler_wavefronts', + 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 58: 'TA_PERF_SEL_addresser_stalled_cycles', + 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 60: 'TA_PERF_SEL_aniso_stalled_cycles', + 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 62: 'TA_PERF_SEL_deriv_stalled_cycles', + 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 64: 'TA_PERF_SEL_color_1_cycle_quads', + 65: 'TA_PERF_SEL_color_2_cycle_quads', + 66: 'TA_PERF_SEL_color_3_cycle_quads', + 68: 'TA_PERF_SEL_mip_1_cycle_quads', + 69: 'TA_PERF_SEL_mip_2_cycle_quads', + 70: 'TA_PERF_SEL_vol_1_cycle_quads', + 71: 'TA_PERF_SEL_vol_2_cycle_quads', + 72: 'TA_PERF_SEL_sampler_op_quads', + 73: 'TA_PERF_SEL_mipmap_lod_0_samples', + 74: 'TA_PERF_SEL_mipmap_lod_1_samples', + 75: 'TA_PERF_SEL_mipmap_lod_2_samples', + 76: 'TA_PERF_SEL_mipmap_lod_3_samples', + 77: 'TA_PERF_SEL_mipmap_lod_4_samples', + 78: 'TA_PERF_SEL_mipmap_lod_5_samples', + 79: 'TA_PERF_SEL_mipmap_lod_6_samples', + 80: 'TA_PERF_SEL_mipmap_lod_7_samples', + 81: 'TA_PERF_SEL_mipmap_lod_8_samples', + 82: 'TA_PERF_SEL_mipmap_lod_9_samples', + 83: 'TA_PERF_SEL_mipmap_lod_10_samples', + 84: 'TA_PERF_SEL_mipmap_lod_11_samples', + 85: 'TA_PERF_SEL_mipmap_lod_12_samples', + 86: 'TA_PERF_SEL_mipmap_lod_13_samples', + 87: 'TA_PERF_SEL_mipmap_lod_14_samples', + 88: 'TA_PERF_SEL_mipmap_invalid_samples', + 89: 'TA_PERF_SEL_aniso_1_cycle_quads', + 90: 'TA_PERF_SEL_aniso_2_cycle_quads', + 91: 'TA_PERF_SEL_aniso_4_cycle_quads', + 92: 'TA_PERF_SEL_aniso_6_cycle_quads', + 93: 'TA_PERF_SEL_aniso_8_cycle_quads', + 94: 'TA_PERF_SEL_aniso_10_cycle_quads', + 95: 'TA_PERF_SEL_aniso_12_cycle_quads', + 96: 'TA_PERF_SEL_aniso_14_cycle_quads', + 97: 'TA_PERF_SEL_aniso_16_cycle_quads', + 98: 'TA_PERF_SEL_store_write_data_input_cycles', + 99: 'TA_PERF_SEL_store_write_data_output_cycles', + 100: 'TA_PERF_SEL_flat_wavefronts', + 101: 'TA_PERF_SEL_flat_load_wavefronts', + 102: 'TA_PERF_SEL_flat_store_wavefronts', + 103: 'TA_PERF_SEL_flat_atomic_wavefronts', + 104: 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', + 105: 'TA_PERF_SEL_register_clk_valid_cycles', + 106: 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', + 107: 'TA_PERF_SEL_harvestable_clk_enabled_cycles', + 108: 'TA_PERF_SEL_flat_2_address_input_vgpr_instructions', + 109: 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', + 110: 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', + 112: 'TA_PERF_SEL_mipmap_lod_15_samples', + 113: 'TA_PERF_SEL_mipmap_lod_16_samples', + 114: 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', + 115: 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', + 116: 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', + 117: 'TA_PERF_SEL_store_has_x_instructions', + 118: 'TA_PERF_SEL_store_has_y_instructions', + 119: 'TA_PERF_SEL_store_has_z_instructions', + 120: 'TA_PERF_SEL_store_has_w_instructions', + 121: 'TA_PERF_SEL_image_nosampler_has_t_instructions', + 122: 'TA_PERF_SEL_image_nosampler_has_r_instructions', + 123: 'TA_PERF_SEL_image_nosampler_has_q_instructions', + 124: 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', + 125: 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', + 126: 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', + 127: 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', + 128: 'TA_PERF_SEL_in_busy', + 129: 'TA_PERF_SEL_in_fifos_busy', + 130: 'TA_PERF_SEL_in_cfifo_busy', + 131: 'TA_PERF_SEL_in_qfifo_busy', + 132: 'TA_PERF_SEL_in_wfifo_busy', + 133: 'TA_PERF_SEL_in_rfifo_busy', + 134: 'TA_PERF_SEL_bf_busy', + 135: 'TA_PERF_SEL_ns_busy', + 136: 'TA_PERF_SEL_smp_busy_ns_idle', + 137: 'TA_PERF_SEL_smp_idle_ns_busy', + 144: 'TA_PERF_SEL_vmemcmd_cycles', + 145: 'TA_PERF_SEL_vmemreq_cycles', + 146: 'TA_PERF_SEL_in_waiting_on_req_cycles', + 150: 'TA_PERF_SEL_in_addr_cycles', + 151: 'TA_PERF_SEL_in_data_cycles', + 160: 'TA_PERF_SEL_point_sampled_quads', + 162: 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', + 163: 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', + 164: 'TA_PERF_SEL_atomic_write_data_input_cycles', + 165: 'TA_PERF_SEL_atomic_write_data_output_cycles', + 173: 'TA_PERF_SEL_num_unlit_nodes_ta_opt', + 174: 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', + 175: 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', + 192: 'TA_PERF_SEL_image_sampler_1_op_burst', + 193: 'TA_PERF_SEL_image_sampler_2to3_op_burst', + 194: 'TA_PERF_SEL_image_sampler_4to7_op_burst', + 195: 'TA_PERF_SEL_image_sampler_ge8_op_burst', + 196: 'TA_PERF_SEL_image_linked_1_op_burst', + 197: 'TA_PERF_SEL_image_linked_2to3_op_burst', + 198: 'TA_PERF_SEL_image_linked_4to7_op_burst', + 199: 'TA_PERF_SEL_image_linked_ge8_op_burst', + 204: 'TA_PERF_SEL_image_nosampler_1_op_burst', + 205: 'TA_PERF_SEL_image_nosampler_2to3_op_burst', + 206: 'TA_PERF_SEL_image_nosampler_4to31_op_burst', + 207: 'TA_PERF_SEL_image_nosampler_ge32_op_burst', + 208: 'TA_PERF_SEL_buffer_flat_1_op_burst', + 209: 'TA_PERF_SEL_buffer_flat_2to3_op_burst', + 210: 'TA_PERF_SEL_buffer_flat_4to31_op_burst', + 211: 'TA_PERF_SEL_buffer_flat_ge32_op_burst', + 212: 'TA_PERF_SEL_write_1_op_burst', + 213: 'TA_PERF_SEL_write_2to3_op_burst', + 214: 'TA_PERF_SEL_write_4to31_op_burst', + 215: 'TA_PERF_SEL_write_ge32_op_burst', + 216: 'TA_PERF_SEL_ibubble_1_cycle_burst', + 217: 'TA_PERF_SEL_ibubble_2to3_cycle_burst', + 218: 'TA_PERF_SEL_ibubble_4to15_cycle_burst', + 219: 'TA_PERF_SEL_ibubble_16to31_cycle_burst', + 220: 'TA_PERF_SEL_ibubble_32to63_cycle_burst', + 221: 'TA_PERF_SEL_ibubble_ge64_cycle_burst', + 224: 'TA_PERF_SEL_sampler_clk_valid_cycles', + 225: 'TA_PERF_SEL_nonsampler_clk_valid_cycles', + 226: 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', + 227: 'TA_PERF_SEL_write_data_clk_valid_cycles', + 228: 'TA_PERF_SEL_gradient_clk_valid_cycles', + 229: 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', + 230: 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', + 231: 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', + 232: 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', + 233: 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', + 234: 'TA_PERF_SEL_aligner_clk_valid_cycles', + 235: 'TA_PERF_SEL_tcreq_clk_valid_cycles', +} +TA_PERF_SEL_NULL = 0 +TA_PERF_SEL_image_sampler_has_offset_instructions = 1 +TA_PERF_SEL_image_sampler_has_bias_instructions = 2 +TA_PERF_SEL_image_sampler_has_reference_instructions = 3 +TA_PERF_SEL_image_sampler_has_ds_instructions = 4 +TA_PERF_SEL_image_sampler_has_dt_instructions = 5 +TA_PERF_SEL_image_sampler_has_dr_instructions = 6 +TA_PERF_SEL_gradient_busy = 7 +TA_PERF_SEL_gradient_fifo_busy = 8 +TA_PERF_SEL_lod_busy = 9 +TA_PERF_SEL_lod_fifo_busy = 10 +TA_PERF_SEL_addresser_busy = 11 +TA_PERF_SEL_addresser_fifo_busy = 12 +TA_PERF_SEL_aligner_busy = 13 +TA_PERF_SEL_write_path_busy = 14 +TA_PERF_SEL_ta_busy = 15 +TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 16 +TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 17 +TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 18 +TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 19 +TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 20 +TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 21 +TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 22 +TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 23 +TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 24 +TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 25 +TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 26 +TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 27 +TA_PERF_SEL_image_sampler_has_t_instructions = 28 +TA_PERF_SEL_image_sampler_has_r_instructions = 29 +TA_PERF_SEL_image_sampler_has_q_instructions = 30 +TA_PERF_SEL_total_wavefronts = 32 +TA_PERF_SEL_gradient_cycles = 33 +TA_PERF_SEL_walker_cycles = 34 +TA_PERF_SEL_aligner_cycles = 35 +TA_PERF_SEL_image_wavefronts = 36 +TA_PERF_SEL_image_read_wavefronts = 37 +TA_PERF_SEL_image_store_wavefronts = 38 +TA_PERF_SEL_image_atomic_wavefronts = 39 +TA_PERF_SEL_image_sampler_total_cycles = 40 +TA_PERF_SEL_image_nosampler_total_cycles = 41 +TA_PERF_SEL_flat_total_cycles = 42 +TA_PERF_SEL_buffer_wavefronts = 44 +TA_PERF_SEL_buffer_load_wavefronts = 45 +TA_PERF_SEL_buffer_store_wavefronts = 46 +TA_PERF_SEL_buffer_atomic_wavefronts = 47 +TA_PERF_SEL_buffer_total_cycles = 49 +TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 50 +TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 51 +TA_PERF_SEL_buffer_has_index_instructions = 52 +TA_PERF_SEL_buffer_has_offset_instructions = 53 +TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 +TA_PERF_SEL_addr_stalled_by_td_cycles = 55 +TA_PERF_SEL_image_sampler_wavefronts = 56 +TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 +TA_PERF_SEL_addresser_stalled_cycles = 58 +TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 +TA_PERF_SEL_aniso_stalled_cycles = 60 +TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 +TA_PERF_SEL_deriv_stalled_cycles = 62 +TA_PERF_SEL_aniso_gt1_cycle_quads = 63 +TA_PERF_SEL_color_1_cycle_quads = 64 +TA_PERF_SEL_color_2_cycle_quads = 65 +TA_PERF_SEL_color_3_cycle_quads = 66 +TA_PERF_SEL_mip_1_cycle_quads = 68 +TA_PERF_SEL_mip_2_cycle_quads = 69 +TA_PERF_SEL_vol_1_cycle_quads = 70 +TA_PERF_SEL_vol_2_cycle_quads = 71 +TA_PERF_SEL_sampler_op_quads = 72 +TA_PERF_SEL_mipmap_lod_0_samples = 73 +TA_PERF_SEL_mipmap_lod_1_samples = 74 +TA_PERF_SEL_mipmap_lod_2_samples = 75 +TA_PERF_SEL_mipmap_lod_3_samples = 76 +TA_PERF_SEL_mipmap_lod_4_samples = 77 +TA_PERF_SEL_mipmap_lod_5_samples = 78 +TA_PERF_SEL_mipmap_lod_6_samples = 79 +TA_PERF_SEL_mipmap_lod_7_samples = 80 +TA_PERF_SEL_mipmap_lod_8_samples = 81 +TA_PERF_SEL_mipmap_lod_9_samples = 82 +TA_PERF_SEL_mipmap_lod_10_samples = 83 +TA_PERF_SEL_mipmap_lod_11_samples = 84 +TA_PERF_SEL_mipmap_lod_12_samples = 85 +TA_PERF_SEL_mipmap_lod_13_samples = 86 +TA_PERF_SEL_mipmap_lod_14_samples = 87 +TA_PERF_SEL_mipmap_invalid_samples = 88 +TA_PERF_SEL_aniso_1_cycle_quads = 89 +TA_PERF_SEL_aniso_2_cycle_quads = 90 +TA_PERF_SEL_aniso_4_cycle_quads = 91 +TA_PERF_SEL_aniso_6_cycle_quads = 92 +TA_PERF_SEL_aniso_8_cycle_quads = 93 +TA_PERF_SEL_aniso_10_cycle_quads = 94 +TA_PERF_SEL_aniso_12_cycle_quads = 95 +TA_PERF_SEL_aniso_14_cycle_quads = 96 +TA_PERF_SEL_aniso_16_cycle_quads = 97 +TA_PERF_SEL_store_write_data_input_cycles = 98 +TA_PERF_SEL_store_write_data_output_cycles = 99 +TA_PERF_SEL_flat_wavefronts = 100 +TA_PERF_SEL_flat_load_wavefronts = 101 +TA_PERF_SEL_flat_store_wavefronts = 102 +TA_PERF_SEL_flat_atomic_wavefronts = 103 +TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 104 +TA_PERF_SEL_register_clk_valid_cycles = 105 +TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 106 +TA_PERF_SEL_harvestable_clk_enabled_cycles = 107 +TA_PERF_SEL_flat_2_address_input_vgpr_instructions = 108 +TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 109 +TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 110 +TA_PERF_SEL_mipmap_lod_15_samples = 112 +TA_PERF_SEL_mipmap_lod_16_samples = 113 +TA_PERF_SEL_store_2_write_data_vgpr_instructions = 114 +TA_PERF_SEL_store_3_write_data_vgpr_instructions = 115 +TA_PERF_SEL_store_4_write_data_vgpr_instructions = 116 +TA_PERF_SEL_store_has_x_instructions = 117 +TA_PERF_SEL_store_has_y_instructions = 118 +TA_PERF_SEL_store_has_z_instructions = 119 +TA_PERF_SEL_store_has_w_instructions = 120 +TA_PERF_SEL_image_nosampler_has_t_instructions = 121 +TA_PERF_SEL_image_nosampler_has_r_instructions = 122 +TA_PERF_SEL_image_nosampler_has_q_instructions = 123 +TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 124 +TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 125 +TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 126 +TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 127 +TA_PERF_SEL_in_busy = 128 +TA_PERF_SEL_in_fifos_busy = 129 +TA_PERF_SEL_in_cfifo_busy = 130 +TA_PERF_SEL_in_qfifo_busy = 131 +TA_PERF_SEL_in_wfifo_busy = 132 +TA_PERF_SEL_in_rfifo_busy = 133 +TA_PERF_SEL_bf_busy = 134 +TA_PERF_SEL_ns_busy = 135 +TA_PERF_SEL_smp_busy_ns_idle = 136 +TA_PERF_SEL_smp_idle_ns_busy = 137 +TA_PERF_SEL_vmemcmd_cycles = 144 +TA_PERF_SEL_vmemreq_cycles = 145 +TA_PERF_SEL_in_waiting_on_req_cycles = 146 +TA_PERF_SEL_in_addr_cycles = 150 +TA_PERF_SEL_in_data_cycles = 151 +TA_PERF_SEL_point_sampled_quads = 160 +TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 162 +TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 163 +TA_PERF_SEL_atomic_write_data_input_cycles = 164 +TA_PERF_SEL_atomic_write_data_output_cycles = 165 +TA_PERF_SEL_num_unlit_nodes_ta_opt = 173 +TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 174 +TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 175 +TA_PERF_SEL_image_sampler_1_op_burst = 192 +TA_PERF_SEL_image_sampler_2to3_op_burst = 193 +TA_PERF_SEL_image_sampler_4to7_op_burst = 194 +TA_PERF_SEL_image_sampler_ge8_op_burst = 195 +TA_PERF_SEL_image_linked_1_op_burst = 196 +TA_PERF_SEL_image_linked_2to3_op_burst = 197 +TA_PERF_SEL_image_linked_4to7_op_burst = 198 +TA_PERF_SEL_image_linked_ge8_op_burst = 199 +TA_PERF_SEL_image_nosampler_1_op_burst = 204 +TA_PERF_SEL_image_nosampler_2to3_op_burst = 205 +TA_PERF_SEL_image_nosampler_4to31_op_burst = 206 +TA_PERF_SEL_image_nosampler_ge32_op_burst = 207 +TA_PERF_SEL_buffer_flat_1_op_burst = 208 +TA_PERF_SEL_buffer_flat_2to3_op_burst = 209 +TA_PERF_SEL_buffer_flat_4to31_op_burst = 210 +TA_PERF_SEL_buffer_flat_ge32_op_burst = 211 +TA_PERF_SEL_write_1_op_burst = 212 +TA_PERF_SEL_write_2to3_op_burst = 213 +TA_PERF_SEL_write_4to31_op_burst = 214 +TA_PERF_SEL_write_ge32_op_burst = 215 +TA_PERF_SEL_ibubble_1_cycle_burst = 216 +TA_PERF_SEL_ibubble_2to3_cycle_burst = 217 +TA_PERF_SEL_ibubble_4to15_cycle_burst = 218 +TA_PERF_SEL_ibubble_16to31_cycle_burst = 219 +TA_PERF_SEL_ibubble_32to63_cycle_burst = 220 +TA_PERF_SEL_ibubble_ge64_cycle_burst = 221 +TA_PERF_SEL_sampler_clk_valid_cycles = 224 +TA_PERF_SEL_nonsampler_clk_valid_cycles = 225 +TA_PERF_SEL_buffer_flat_clk_valid_cycles = 226 +TA_PERF_SEL_write_data_clk_valid_cycles = 227 +TA_PERF_SEL_gradient_clk_valid_cycles = 228 +TA_PERF_SEL_lod_aniso_clk_valid_cycles = 229 +TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 230 +TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 231 +TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 232 +TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 233 +TA_PERF_SEL_aligner_clk_valid_cycles = 234 +TA_PERF_SEL_tcreq_clk_valid_cycles = 235 +TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_BC_SWIZZLE' +TEX_BC_SWIZZLE__enumvalues = { + 0: 'TEX_BC_Swizzle_XYZW', + 1: 'TEX_BC_Swizzle_XWYZ', + 2: 'TEX_BC_Swizzle_WZYX', + 3: 'TEX_BC_Swizzle_WXYZ', + 4: 'TEX_BC_Swizzle_ZYXW', + 5: 'TEX_BC_Swizzle_YXWZ', +} +TEX_BC_Swizzle_XYZW = 0 +TEX_BC_Swizzle_XWYZ = 1 +TEX_BC_Swizzle_WZYX = 2 +TEX_BC_Swizzle_WXYZ = 3 +TEX_BC_Swizzle_ZYXW = 4 +TEX_BC_Swizzle_YXWZ = 5 +TEX_BC_SWIZZLE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_BORDER_COLOR_TYPE' +TEX_BORDER_COLOR_TYPE__enumvalues = { + 0: 'TEX_BorderColor_TransparentBlack', + 1: 'TEX_BorderColor_OpaqueBlack', + 2: 'TEX_BorderColor_OpaqueWhite', + 3: 'TEX_BorderColor_Register', +} +TEX_BorderColor_TransparentBlack = 0 +TEX_BorderColor_OpaqueBlack = 1 +TEX_BorderColor_OpaqueWhite = 2 +TEX_BorderColor_Register = 3 +TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CHROMA_KEY' +TEX_CHROMA_KEY__enumvalues = { + 0: 'TEX_ChromaKey_Disabled', + 1: 'TEX_ChromaKey_Kill', + 2: 'TEX_ChromaKey_Blend', + 3: 'TEX_ChromaKey_RESERVED_3', +} +TEX_ChromaKey_Disabled = 0 +TEX_ChromaKey_Kill = 1 +TEX_ChromaKey_Blend = 2 +TEX_ChromaKey_RESERVED_3 = 3 +TEX_CHROMA_KEY = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CLAMP' +TEX_CLAMP__enumvalues = { + 0: 'TEX_Clamp_Repeat', + 1: 'TEX_Clamp_Mirror', + 2: 'TEX_Clamp_ClampToLast', + 3: 'TEX_Clamp_MirrorOnceToLast', + 4: 'TEX_Clamp_ClampHalfToBorder', + 5: 'TEX_Clamp_MirrorOnceHalfToBorder', + 6: 'TEX_Clamp_ClampToBorder', + 7: 'TEX_Clamp_MirrorOnceToBorder', +} +TEX_Clamp_Repeat = 0 +TEX_Clamp_Mirror = 1 +TEX_Clamp_ClampToLast = 2 +TEX_Clamp_MirrorOnceToLast = 3 +TEX_Clamp_ClampHalfToBorder = 4 +TEX_Clamp_MirrorOnceHalfToBorder = 5 +TEX_Clamp_ClampToBorder = 6 +TEX_Clamp_MirrorOnceToBorder = 7 +TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_COORD_TYPE' +TEX_COORD_TYPE__enumvalues = { + 0: 'TEX_CoordType_Unnormalized', + 1: 'TEX_CoordType_Normalized', +} +TEX_CoordType_Unnormalized = 0 +TEX_CoordType_Normalized = 1 +TEX_COORD_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' +TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { + 0: 'TEX_DepthCompareFunction_Never', + 1: 'TEX_DepthCompareFunction_Less', + 2: 'TEX_DepthCompareFunction_Equal', + 3: 'TEX_DepthCompareFunction_LessEqual', + 4: 'TEX_DepthCompareFunction_Greater', + 5: 'TEX_DepthCompareFunction_NotEqual', + 6: 'TEX_DepthCompareFunction_GreaterEqual', + 7: 'TEX_DepthCompareFunction_Always', +} +TEX_DepthCompareFunction_Never = 0 +TEX_DepthCompareFunction_Less = 1 +TEX_DepthCompareFunction_Equal = 2 +TEX_DepthCompareFunction_LessEqual = 3 +TEX_DepthCompareFunction_Greater = 4 +TEX_DepthCompareFunction_NotEqual = 5 +TEX_DepthCompareFunction_GreaterEqual = 6 +TEX_DepthCompareFunction_Always = 7 +TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_FORMAT_COMP' +TEX_FORMAT_COMP__enumvalues = { + 0: 'TEX_FormatComp_Unsigned', + 1: 'TEX_FormatComp_Signed', + 2: 'TEX_FormatComp_UnsignedBiased', + 3: 'TEX_FormatComp_RESERVED_3', +} +TEX_FormatComp_Unsigned = 0 +TEX_FormatComp_Signed = 1 +TEX_FormatComp_UnsignedBiased = 2 +TEX_FormatComp_RESERVED_3 = 3 +TEX_FORMAT_COMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MAX_ANISO_RATIO' +TEX_MAX_ANISO_RATIO__enumvalues = { + 0: 'TEX_MaxAnisoRatio_1to1', + 1: 'TEX_MaxAnisoRatio_2to1', + 2: 'TEX_MaxAnisoRatio_4to1', + 3: 'TEX_MaxAnisoRatio_8to1', + 4: 'TEX_MaxAnisoRatio_16to1', + 5: 'TEX_MaxAnisoRatio_RESERVED_5', + 6: 'TEX_MaxAnisoRatio_RESERVED_6', + 7: 'TEX_MaxAnisoRatio_RESERVED_7', +} +TEX_MaxAnisoRatio_1to1 = 0 +TEX_MaxAnisoRatio_2to1 = 1 +TEX_MaxAnisoRatio_4to1 = 2 +TEX_MaxAnisoRatio_8to1 = 3 +TEX_MaxAnisoRatio_16to1 = 4 +TEX_MaxAnisoRatio_RESERVED_5 = 5 +TEX_MaxAnisoRatio_RESERVED_6 = 6 +TEX_MaxAnisoRatio_RESERVED_7 = 7 +TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MIP_FILTER' +TEX_MIP_FILTER__enumvalues = { + 0: 'TEX_MipFilter_None', + 1: 'TEX_MipFilter_Point', + 2: 'TEX_MipFilter_Linear', + 3: 'TEX_MipFilter_Point_Aniso_Adj', +} +TEX_MipFilter_None = 0 +TEX_MipFilter_Point = 1 +TEX_MipFilter_Linear = 2 +TEX_MipFilter_Point_Aniso_Adj = 3 +TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_REQUEST_SIZE' +TEX_REQUEST_SIZE__enumvalues = { + 0: 'TEX_RequestSize_32B', + 1: 'TEX_RequestSize_64B', + 2: 'TEX_RequestSize_128B', + 3: 'TEX_RequestSize_2X64B', +} +TEX_RequestSize_32B = 0 +TEX_RequestSize_64B = 1 +TEX_RequestSize_128B = 2 +TEX_RequestSize_2X64B = 3 +TEX_REQUEST_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_SAMPLER_TYPE' +TEX_SAMPLER_TYPE__enumvalues = { + 0: 'TEX_SamplerType_Invalid', + 1: 'TEX_SamplerType_Valid', +} +TEX_SamplerType_Invalid = 0 +TEX_SamplerType_Valid = 1 +TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_XY_FILTER' +TEX_XY_FILTER__enumvalues = { + 0: 'TEX_XYFilter_Point', + 1: 'TEX_XYFilter_Linear', + 2: 'TEX_XYFilter_AnisoPoint', + 3: 'TEX_XYFilter_AnisoLinear', +} +TEX_XYFilter_Point = 0 +TEX_XYFilter_Linear = 1 +TEX_XYFilter_AnisoPoint = 2 +TEX_XYFilter_AnisoLinear = 3 +TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_Z_FILTER' +TEX_Z_FILTER__enumvalues = { + 0: 'TEX_ZFilter_None', + 1: 'TEX_ZFilter_Point', + 2: 'TEX_ZFilter_Linear', + 3: 'TEX_ZFilter_RESERVED_3', +} +TEX_ZFilter_None = 0 +TEX_ZFilter_Point = 1 +TEX_ZFilter_Linear = 2 +TEX_ZFilter_RESERVED_3 = 3 +TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_TYPE' +TVX_TYPE__enumvalues = { + 0: 'TVX_Type_InvalidTextureResource', + 1: 'TVX_Type_InvalidVertexBuffer', + 2: 'TVX_Type_ValidTextureResource', + 3: 'TVX_Type_ValidVertexBuffer', +} +TVX_Type_InvalidTextureResource = 0 +TVX_Type_InvalidVertexBuffer = 1 +TVX_Type_ValidTextureResource = 2 +TVX_Type_ValidVertexBuffer = 3 +TVX_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TA_TC_ADDR_MODES' +TA_TC_ADDR_MODES__enumvalues = { + 0: 'TA_TC_ADDR_MODE_DEFAULT', + 1: 'TA_TC_ADDR_MODE_COMP0', + 2: 'TA_TC_ADDR_MODE_COMP1', + 3: 'TA_TC_ADDR_MODE_COMP2', + 4: 'TA_TC_ADDR_MODE_COMP3', + 5: 'TA_TC_ADDR_MODE_UNALIGNED', + 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', +} +TA_TC_ADDR_MODE_DEFAULT = 0 +TA_TC_ADDR_MODE_COMP0 = 1 +TA_TC_ADDR_MODE_COMP1 = 2 +TA_TC_ADDR_MODE_COMP2 = 3 +TA_TC_ADDR_MODE_COMP3 = 4 +TA_TC_ADDR_MODE_UNALIGNED = 5 +TA_TC_ADDR_MODE_BORDER_COLOR = 6 +TA_TC_ADDR_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TA_TC_REQ_MODES' +TA_TC_REQ_MODES__enumvalues = { + 0: 'TA_TC_REQ_MODE_BORDER', + 1: 'TA_TC_REQ_MODE_TEX2', + 2: 'TA_TC_REQ_MODE_TEX1', + 3: 'TA_TC_REQ_MODE_TEX0', + 4: 'TA_TC_REQ_MODE_NORMAL', + 5: 'TA_TC_REQ_MODE_DWORD', + 6: 'TA_TC_REQ_MODE_BYTE', + 7: 'TA_TC_REQ_MODE_BYTE_NV', +} +TA_TC_REQ_MODE_BORDER = 0 +TA_TC_REQ_MODE_TEX2 = 1 +TA_TC_REQ_MODE_TEX1 = 2 +TA_TC_REQ_MODE_TEX0 = 3 +TA_TC_REQ_MODE_NORMAL = 4 +TA_TC_REQ_MODE_DWORD = 5 +TA_TC_REQ_MODE_BYTE = 6 +TA_TC_REQ_MODE_BYTE_NV = 7 +TA_TC_REQ_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_POLICIES' +TCP_CACHE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_POLICY_MISS_LRU', + 1: 'TCP_CACHE_POLICY_MISS_EVICT', + 2: 'TCP_CACHE_POLICY_HIT_LRU', + 3: 'TCP_CACHE_POLICY_HIT_EVICT', +} +TCP_CACHE_POLICY_MISS_LRU = 0 +TCP_CACHE_POLICY_MISS_EVICT = 1 +TCP_CACHE_POLICY_HIT_LRU = 2 +TCP_CACHE_POLICY_HIT_EVICT = 3 +TCP_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_STORE_POLICIES' +TCP_CACHE_STORE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', + 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', +} +TCP_CACHE_STORE_POLICY_WT_LRU = 0 +TCP_CACHE_STORE_POLICY_WT_EVICT = 1 +TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_COMPRESSION_BYPASS' +TCP_COMPRESSION_BYPASS__enumvalues = { + 0: 'TCP_COMPRESSION_BYPASS_DIS', + 1: 'TCP_COMPRESSION_BYPASS_EN', +} +TCP_COMPRESSION_BYPASS_DIS = 0 +TCP_COMPRESSION_BYPASS_EN = 1 +TCP_COMPRESSION_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_COMPRESSION_OVERRIDE' +TCP_COMPRESSION_OVERRIDE__enumvalues = { + 0: 'TCP_COMPRESSION_OVERRIDE_DIS', + 1: 'TCP_COMPRESSION_OVERRIDE_EN', +} +TCP_COMPRESSION_OVERRIDE_DIS = 0 +TCP_COMPRESSION_OVERRIDE_EN = 1 +TCP_COMPRESSION_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_OPCODE_TYPE' +TCP_OPCODE_TYPE__enumvalues = { + 0: 'TCP_OPCODE_READ', + 1: 'TCP_OPCODE_WRITE', + 2: 'TCP_OPCODE_ATOMIC', + 3: 'TCP_OPCODE_INV', + 4: 'TCP_OPCODE_ATOMIC_CMPSWAP', + 5: 'TCP_OPCODE_SAMPLER', + 6: 'TCP_OPCODE_LOAD', + 7: 'TCP_OPCODE_GATHERH', +} +TCP_OPCODE_READ = 0 +TCP_OPCODE_WRITE = 1 +TCP_OPCODE_ATOMIC = 2 +TCP_OPCODE_INV = 3 +TCP_OPCODE_ATOMIC_CMPSWAP = 4 +TCP_OPCODE_SAMPLER = 5 +TCP_OPCODE_LOAD = 6 +TCP_OPCODE_GATHERH = 7 +TCP_OPCODE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_PERFCOUNT_SELECT' +TCP_PERFCOUNT_SELECT__enumvalues = { + 0: 'TCP_PERF_SEL_GATE_EN1', + 1: 'TCP_PERF_SEL_GATE_EN2', + 2: 'TCP_PERF_SEL_TA_REQ', + 3: 'TCP_PERF_SEL_TA_REQ_STATE_READ', + 4: 'TCP_PERF_SEL_TA_REQ_READ', + 5: 'TCP_PERF_SEL_TA_REQ_WRITE', + 6: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', + 7: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', + 8: 'TCP_PERF_SEL_TA_REQ_GL0_INV', + 9: 'TCP_PERF_SEL_REQ', + 10: 'TCP_PERF_SEL_REQ_READ', + 12: 'TCP_PERF_SEL_REQ_READ_HIT_LRU', + 13: 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', + 14: 'TCP_PERF_SEL_REQ_WRITE', + 15: 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', + 16: 'TCP_PERF_SEL_REQ_NON_READ', + 17: 'TCP_PERF_SEL_REQ_MISS', + 18: 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', + 19: 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', + 20: 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', + 21: 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', + 22: 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', + 23: 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', + 24: 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', + 25: 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', + 26: 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', + 27: 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', + 28: 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', + 29: 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', + 30: 'TCP_PERF_SEL_GL1_REQ_READ', + 31: 'TCP_PERF_SEL_GL1_REQ_READ_128B', + 32: 'TCP_PERF_SEL_GL1_REQ_READ_64B', + 33: 'TCP_PERF_SEL_GL1_REQ_WRITE', + 34: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', + 35: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', + 36: 'TCP_PERF_SEL_GL1_READ_LATENCY', + 37: 'TCP_PERF_SEL_GL1_WRITE_LATENCY', + 38: 'TCP_PERF_SEL_TCP_LATENCY', + 39: 'TCP_PERF_SEL_TCP_TA_REQ_STALL', + 40: 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', + 41: 'TCP_PERF_SEL_DATA_FIFO_STALL', + 42: 'TCP_PERF_SEL_LOD_STALL', + 43: 'TCP_PERF_SEL_POWER_STALL', + 44: 'TCP_PERF_SEL_ALLOC_STALL', + 46: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', + 47: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', + 48: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', + 49: 'TCP_PERF_SEL_LFIFO_STALL', + 50: 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', + 51: 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', + 52: 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', + 53: 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', + 54: 'TCP_PERF_SEL_GL1_PENDING_STALL', + 55: 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', + 56: 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', + 57: 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', + 58: 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', + 59: 'TCP_PERF_SEL_TD_TCP_STALL', + 60: 'TCP_PERF_SEL_TA_REQ_BUFFERNOP', + 61: 'TCP_PERF_SEL_WRITECOMBINE_ENDCLAUSE', + 62: 'TCP_PERF_SEL_TAGFAKE_EOW', + 63: 'TCP_PERF_SEL_REQ_TAG_MATCH_AND_NOT_VALID', + 64: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_0', + 65: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_1to2', + 66: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_3to4', + 67: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_5to8', + 68: 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_9to16', + 70: 'TCP_PERF_SEL_BURST_BIN_READHIT_0', + 71: 'TCP_PERF_SEL_BURST_BIN_READHIT_1', + 72: 'TCP_PERF_SEL_BURST_BIN_READHIT_2to4', + 73: 'TCP_PERF_SEL_BURST_BIN_READHIT_5to8', + 74: 'TCP_PERF_SEL_BURST_BIN_READHIT_9to16', + 75: 'TCP_PERF_SEL_BURST_BIN_READHIT_gt16', + 76: 'TCP_PERF_SEL_TA_TC_REQ_EN_SUM', + 77: 'TCP_PERF_SEL_GL1_REQ_LU', + 78: 'TCP_PERF_SEL_REQ_TAG_MATCH_AND_LU_INVALIDATE', +} +TCP_PERF_SEL_GATE_EN1 = 0 +TCP_PERF_SEL_GATE_EN2 = 1 +TCP_PERF_SEL_TA_REQ = 2 +TCP_PERF_SEL_TA_REQ_STATE_READ = 3 +TCP_PERF_SEL_TA_REQ_READ = 4 +TCP_PERF_SEL_TA_REQ_WRITE = 5 +TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 6 +TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 7 +TCP_PERF_SEL_TA_REQ_GL0_INV = 8 +TCP_PERF_SEL_REQ = 9 +TCP_PERF_SEL_REQ_READ = 10 +TCP_PERF_SEL_REQ_READ_HIT_LRU = 12 +TCP_PERF_SEL_REQ_READ_MISS_EVICT = 13 +TCP_PERF_SEL_REQ_WRITE = 14 +TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 15 +TCP_PERF_SEL_REQ_NON_READ = 16 +TCP_PERF_SEL_REQ_MISS = 17 +TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 18 +TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 19 +TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 20 +TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 21 +TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 22 +TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 23 +TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 24 +TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 25 +TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 26 +TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 27 +TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 28 +TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 29 +TCP_PERF_SEL_GL1_REQ_READ = 30 +TCP_PERF_SEL_GL1_REQ_READ_128B = 31 +TCP_PERF_SEL_GL1_REQ_READ_64B = 32 +TCP_PERF_SEL_GL1_REQ_WRITE = 33 +TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 34 +TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 35 +TCP_PERF_SEL_GL1_READ_LATENCY = 36 +TCP_PERF_SEL_GL1_WRITE_LATENCY = 37 +TCP_PERF_SEL_TCP_LATENCY = 38 +TCP_PERF_SEL_TCP_TA_REQ_STALL = 39 +TCP_PERF_SEL_TA_TCP_REQ_STARVE = 40 +TCP_PERF_SEL_DATA_FIFO_STALL = 41 +TCP_PERF_SEL_LOD_STALL = 42 +TCP_PERF_SEL_POWER_STALL = 43 +TCP_PERF_SEL_ALLOC_STALL = 44 +TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 46 +TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 47 +TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 48 +TCP_PERF_SEL_LFIFO_STALL = 49 +TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 50 +TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 51 +TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 52 +TCP_PERF_SEL_GL1_GRANT_READ_STALL = 53 +TCP_PERF_SEL_GL1_PENDING_STALL = 54 +TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 55 +TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 56 +TCP_PERF_SEL_READ_DATACONFLICT_STALL = 57 +TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 58 +TCP_PERF_SEL_TD_TCP_STALL = 59 +TCP_PERF_SEL_TA_REQ_BUFFERNOP = 60 +TCP_PERF_SEL_WRITECOMBINE_ENDCLAUSE = 61 +TCP_PERF_SEL_TAGFAKE_EOW = 62 +TCP_PERF_SEL_REQ_TAG_MATCH_AND_NOT_VALID = 63 +TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_0 = 64 +TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_1to2 = 65 +TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_3to4 = 66 +TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_5to8 = 67 +TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_9to16 = 68 +TCP_PERF_SEL_BURST_BIN_READHIT_0 = 70 +TCP_PERF_SEL_BURST_BIN_READHIT_1 = 71 +TCP_PERF_SEL_BURST_BIN_READHIT_2to4 = 72 +TCP_PERF_SEL_BURST_BIN_READHIT_5to8 = 73 +TCP_PERF_SEL_BURST_BIN_READHIT_9to16 = 74 +TCP_PERF_SEL_BURST_BIN_READHIT_gt16 = 75 +TCP_PERF_SEL_TA_TC_REQ_EN_SUM = 76 +TCP_PERF_SEL_GL1_REQ_LU = 77 +TCP_PERF_SEL_REQ_TAG_MATCH_AND_LU_INVALIDATE = 78 +TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_WATCH_MODES' +TCP_WATCH_MODES__enumvalues = { + 0: 'TCP_WATCH_MODE_READ', + 1: 'TCP_WATCH_MODE_NONREAD', + 2: 'TCP_WATCH_MODE_ATOMIC', + 3: 'TCP_WATCH_MODE_ALL', +} +TCP_WATCH_MODE_READ = 0 +TCP_WATCH_MODE_NONREAD = 1 +TCP_WATCH_MODE_ATOMIC = 2 +TCP_WATCH_MODE_ALL = 3 +TCP_WATCH_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_WRITE_COMPRESSION_DISABLE' +TCP_WRITE_COMPRESSION_DISABLE__enumvalues = { + 0: 'TCP_WRITE_COMPRESSION_DISABLE_DIS', + 1: 'TCP_WRITE_COMPRESSION_DISABLE_EN', +} +TCP_WRITE_COMPRESSION_DISABLE_DIS = 0 +TCP_WRITE_COMPRESSION_DISABLE_EN = 1 +TCP_WRITE_COMPRESSION_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'TD_PERFCOUNT_SEL' +TD_PERFCOUNT_SEL__enumvalues = { + 0: 'TD_PERF_SEL_none', + 1: 'TD_PERF_SEL_td_busy', + 2: 'TD_PERF_SEL_input_busy', + 3: 'TD_PERF_SEL_sampler_lerp_busy', + 4: 'TD_PERF_SEL_sampler_out_busy', + 5: 'TD_PERF_SEL_nofilter_busy', + 7: 'TD_PERF_SEL_sampler_core_sclk_en', + 8: 'TD_PERF_SEL_sampler_preformatter_sclk_en', + 9: 'TD_PERF_SEL_sampler_bilerp_sclk_en', + 10: 'TD_PERF_SEL_sampler_bypass_sclk_en', + 11: 'TD_PERF_SEL_sampler_minmax_sclk_en', + 12: 'TD_PERF_SEL_sampler_accum_sclk_en', + 13: 'TD_PERF_SEL_sampler_format_flt_sclk_en', + 14: 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', + 15: 'TD_PERF_SEL_sampler_out_sclk_en', + 16: 'TD_PERF_SEL_nofilter_sclk_en', + 17: 'TD_PERF_SEL_nofilter_d32_sclk_en', + 18: 'TD_PERF_SEL_nofilter_d16_sclk_en', + 26: 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', + 27: 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', + 28: 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', + 32: 'TD_PERF_SEL_core_state_ram_max_cnt', + 33: 'TD_PERF_SEL_core_state_rams_read', + 34: 'TD_PERF_SEL_weight_data_rams_read', + 35: 'TD_PERF_SEL_reference_data_rams_read', + 36: 'TD_PERF_SEL_tc_td_ram_fifo_full', + 37: 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', + 38: 'TD_PERF_SEL_tc_td_data_fifo_full', + 39: 'TD_PERF_SEL_input_state_fifo_full', + 40: 'TD_PERF_SEL_ta_data_stall', + 41: 'TD_PERF_SEL_tc_data_stall', + 42: 'TD_PERF_SEL_tc_ram_stall', + 43: 'TD_PERF_SEL_lds_stall', + 44: 'TD_PERF_SEL_sampler_pkr_full', + 45: 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', + 46: 'TD_PERF_SEL_nofilter_pkr_full', + 47: 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', + 50: 'TD_PERF_SEL_gather4_instr', + 51: 'TD_PERF_SEL_gather4h_instr', + 52: 'TD_PERF_SEL_getlod_instr', + 54: 'TD_PERF_SEL_sample_instr', + 55: 'TD_PERF_SEL_sample_c_instr', + 56: 'TD_PERF_SEL_load_instr', + 57: 'TD_PERF_SEL_ps_load_instr', + 58: 'TD_PERF_SEL_write_ack_instr', + 59: 'TD_PERF_SEL_d16_en_instr', + 60: 'TD_PERF_SEL_bypassLerp_instr', + 61: 'TD_PERF_SEL_min_max_filter_instr', + 62: 'TD_PERF_SEL_one_comp_return_instr', + 63: 'TD_PERF_SEL_two_comp_return_instr', + 64: 'TD_PERF_SEL_three_comp_return_instr', + 65: 'TD_PERF_SEL_four_comp_return_instr', + 66: 'TD_PERF_SEL_user_defined_border', + 67: 'TD_PERF_SEL_white_border', + 68: 'TD_PERF_SEL_opaque_black_border', + 69: 'TD_PERF_SEL_lod_warn_from_ta', + 70: 'TD_PERF_SEL_instruction_dest_is_lds', + 71: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', + 72: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', + 73: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', + 74: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', + 75: 'TD_PERF_SEL_out_of_order_instr', + 76: 'TD_PERF_SEL_total_num_instr', + 77: 'TD_PERF_SEL_total_num_instr_with_perf_wdw', + 78: 'TD_PERF_SEL_total_num_sampler_instr', + 79: 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', + 80: 'TD_PERF_SEL_total_num_nofilter_instr', + 81: 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', + 84: 'TD_PERF_SEL_mixmode_instr', + 85: 'TD_PERF_SEL_mixmode_resource', + 86: 'TD_PERF_SEL_status_packet', + 89: 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', + 90: 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', + 91: 'TD_PERF_SEL_done_scoreboard_not_empty', + 92: 'TD_PERF_SEL_done_scoreboard_is_full', + 93: 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', + 94: 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', + 95: 'TD_PERF_SEL_nofilter_formatters_turned_on', + 96: 'TD_PERF_SEL_nofilter_insert_extra_comps', + 97: 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', + 98: 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', + 99: 'TD_PERF_SEL_msaa_load_instr', + 100: 'TD_PERF_SEL_blend_prt_with_prt_default_0', + 102: 'TD_PERF_SEL_resmap_instr', + 103: 'TD_PERF_SEL_prt_ack_instr', + 104: 'TD_PERF_SEL_resmap_with_volume_filtering', + 105: 'TD_PERF_SEL_resmap_with_aniso_filtering', + 106: 'TD_PERF_SEL_resmap_with_no_more_filtering', + 107: 'TD_PERF_SEL_resmap_with_cubemap_corner', + 131: 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', + 132: 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', + 133: 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', + 134: 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', + 135: 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', + 136: 'TD_PERF_SEL_burst_bin_sampler_1', + 137: 'TD_PERF_SEL_burst_bin_sampler_2to8', + 138: 'TD_PERF_SEL_burst_bin_sampler_9to16', + 139: 'TD_PERF_SEL_burst_bin_sampler_gt16', + 140: 'TD_PERF_SEL_burst_bin_gather_1', + 141: 'TD_PERF_SEL_burst_bin_gather_2to8', + 142: 'TD_PERF_SEL_burst_bin_gather_9to16', + 143: 'TD_PERF_SEL_burst_bin_gather_gt16', + 144: 'TD_PERF_SEL_burst_bin_nofilter_1', + 145: 'TD_PERF_SEL_burst_bin_nofilter_2to4', + 146: 'TD_PERF_SEL_burst_bin_nofilter_5to7', + 147: 'TD_PERF_SEL_burst_bin_nofilter_8to16', + 148: 'TD_PERF_SEL_burst_bin_nofilter_gt16', + 170: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', + 171: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', + 172: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', + 173: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', + 174: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', + 175: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', + 176: 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', + 177: 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', + 178: 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', + 179: 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', + 180: 'TD_PERF_SEL_preempting_nofilter_max_cnt', + 181: 'TD_PERF_SEL_sampler_lerp0_active', + 182: 'TD_PERF_SEL_sampler_lerp1_active', + 183: 'TD_PERF_SEL_sampler_lerp2_active', + 184: 'TD_PERF_SEL_sampler_lerp3_active', + 185: 'TD_PERF_SEL_sampler_lerp4_active', + 186: 'TD_PERF_SEL_sampler_lerp5_active', + 187: 'TD_PERF_SEL_sampler_lerp6_active', + 188: 'TD_PERF_SEL_sampler_lerp7_active', + 189: 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', + 190: 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', + 191: 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', + 192: 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', + 193: 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', + 194: 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', + 195: 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', + 200: 'TD_PERF_SEL_store_preempts_a_load', + 201: 'TD_PERF_SEL_sample_2x_instr', + 202: 'TD_PERF_SEL_gather4_2x_instr', + 203: 'TD_PERF_SEL_gather4h_2x_instr', + 204: 'TD_PERF_SEL_getlod_2x_instr', + 205: 'TD_PERF_SEL_resmap_2x_instr', + 206: 'TD_PERF_SEL_2x_sampler_op_with_1_unlit_quad', + 207: 'TD_PERF_SEL_2x_sampler_op_with_both_quads_unlit', + 208: 'TD_PERF_SEL_tri_proc_node_override_slot0', + 209: 'TD_PERF_SEL_tri_run_intersect_ahs_slot0', + 210: 'TD_PERF_SEL_tri_run_ahs_slot0', + 231: 'TD_PERF_SEL_tri_proc_node_override_slot1', + 232: 'TD_PERF_SEL_tri_run_intersect_ahs_slot1', + 233: 'TD_PERF_SEL_tri_run_ahs_slot1', + 241: 'TD_PERF_SEL_instance_mask_culled', + 242: 'TD_PERF_SEL_box_opaque_culled', + 243: 'TD_PERF_SEL_box_non_opaque_culled', + 244: 'TD_PERF_SEL_box_with_triangle_children_only_culled', + 245: 'TD_PERF_SEL_box_with_procedural_children_only_culled', + 246: 'TD_PERF_SEL_triangle_opaque_culled', + 247: 'TD_PERF_SEL_triangle_non_opaque_culled', + 248: 'TD_PERF_SEL_triangle_front_facing_culled', + 249: 'TD_PERF_SEL_triangle_back_facing_culled', +} +TD_PERF_SEL_none = 0 +TD_PERF_SEL_td_busy = 1 +TD_PERF_SEL_input_busy = 2 +TD_PERF_SEL_sampler_lerp_busy = 3 +TD_PERF_SEL_sampler_out_busy = 4 +TD_PERF_SEL_nofilter_busy = 5 +TD_PERF_SEL_sampler_core_sclk_en = 7 +TD_PERF_SEL_sampler_preformatter_sclk_en = 8 +TD_PERF_SEL_sampler_bilerp_sclk_en = 9 +TD_PERF_SEL_sampler_bypass_sclk_en = 10 +TD_PERF_SEL_sampler_minmax_sclk_en = 11 +TD_PERF_SEL_sampler_accum_sclk_en = 12 +TD_PERF_SEL_sampler_format_flt_sclk_en = 13 +TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 14 +TD_PERF_SEL_sampler_out_sclk_en = 15 +TD_PERF_SEL_nofilter_sclk_en = 16 +TD_PERF_SEL_nofilter_d32_sclk_en = 17 +TD_PERF_SEL_nofilter_d16_sclk_en = 18 +TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 26 +TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 27 +TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 28 +TD_PERF_SEL_core_state_ram_max_cnt = 32 +TD_PERF_SEL_core_state_rams_read = 33 +TD_PERF_SEL_weight_data_rams_read = 34 +TD_PERF_SEL_reference_data_rams_read = 35 +TD_PERF_SEL_tc_td_ram_fifo_full = 36 +TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 37 +TD_PERF_SEL_tc_td_data_fifo_full = 38 +TD_PERF_SEL_input_state_fifo_full = 39 +TD_PERF_SEL_ta_data_stall = 40 +TD_PERF_SEL_tc_data_stall = 41 +TD_PERF_SEL_tc_ram_stall = 42 +TD_PERF_SEL_lds_stall = 43 +TD_PERF_SEL_sampler_pkr_full = 44 +TD_PERF_SEL_sampler_pkr_full_due_to_arb = 45 +TD_PERF_SEL_nofilter_pkr_full = 46 +TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 47 +TD_PERF_SEL_gather4_instr = 50 +TD_PERF_SEL_gather4h_instr = 51 +TD_PERF_SEL_getlod_instr = 52 +TD_PERF_SEL_sample_instr = 54 +TD_PERF_SEL_sample_c_instr = 55 +TD_PERF_SEL_load_instr = 56 +TD_PERF_SEL_ps_load_instr = 57 +TD_PERF_SEL_write_ack_instr = 58 +TD_PERF_SEL_d16_en_instr = 59 +TD_PERF_SEL_bypassLerp_instr = 60 +TD_PERF_SEL_min_max_filter_instr = 61 +TD_PERF_SEL_one_comp_return_instr = 62 +TD_PERF_SEL_two_comp_return_instr = 63 +TD_PERF_SEL_three_comp_return_instr = 64 +TD_PERF_SEL_four_comp_return_instr = 65 +TD_PERF_SEL_user_defined_border = 66 +TD_PERF_SEL_white_border = 67 +TD_PERF_SEL_opaque_black_border = 68 +TD_PERF_SEL_lod_warn_from_ta = 69 +TD_PERF_SEL_instruction_dest_is_lds = 70 +TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 71 +TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 72 +TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 73 +TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 74 +TD_PERF_SEL_out_of_order_instr = 75 +TD_PERF_SEL_total_num_instr = 76 +TD_PERF_SEL_total_num_instr_with_perf_wdw = 77 +TD_PERF_SEL_total_num_sampler_instr = 78 +TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 79 +TD_PERF_SEL_total_num_nofilter_instr = 80 +TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 81 +TD_PERF_SEL_mixmode_instr = 84 +TD_PERF_SEL_mixmode_resource = 85 +TD_PERF_SEL_status_packet = 86 +TD_PERF_SEL_done_scoreboard_max_stored_cnt = 89 +TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 90 +TD_PERF_SEL_done_scoreboard_not_empty = 91 +TD_PERF_SEL_done_scoreboard_is_full = 92 +TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 93 +TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 94 +TD_PERF_SEL_nofilter_formatters_turned_on = 95 +TD_PERF_SEL_nofilter_insert_extra_comps = 96 +TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 97 +TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 98 +TD_PERF_SEL_msaa_load_instr = 99 +TD_PERF_SEL_blend_prt_with_prt_default_0 = 100 +TD_PERF_SEL_resmap_instr = 102 +TD_PERF_SEL_prt_ack_instr = 103 +TD_PERF_SEL_resmap_with_volume_filtering = 104 +TD_PERF_SEL_resmap_with_aniso_filtering = 105 +TD_PERF_SEL_resmap_with_no_more_filtering = 106 +TD_PERF_SEL_resmap_with_cubemap_corner = 107 +TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 131 +TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 132 +TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 133 +TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 134 +TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 135 +TD_PERF_SEL_burst_bin_sampler_1 = 136 +TD_PERF_SEL_burst_bin_sampler_2to8 = 137 +TD_PERF_SEL_burst_bin_sampler_9to16 = 138 +TD_PERF_SEL_burst_bin_sampler_gt16 = 139 +TD_PERF_SEL_burst_bin_gather_1 = 140 +TD_PERF_SEL_burst_bin_gather_2to8 = 141 +TD_PERF_SEL_burst_bin_gather_9to16 = 142 +TD_PERF_SEL_burst_bin_gather_gt16 = 143 +TD_PERF_SEL_burst_bin_nofilter_1 = 144 +TD_PERF_SEL_burst_bin_nofilter_2to4 = 145 +TD_PERF_SEL_burst_bin_nofilter_5to7 = 146 +TD_PERF_SEL_burst_bin_nofilter_8to16 = 147 +TD_PERF_SEL_burst_bin_nofilter_gt16 = 148 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 170 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 171 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 172 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 173 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 174 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 175 +TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 176 +TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 177 +TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 178 +TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 179 +TD_PERF_SEL_preempting_nofilter_max_cnt = 180 +TD_PERF_SEL_sampler_lerp0_active = 181 +TD_PERF_SEL_sampler_lerp1_active = 182 +TD_PERF_SEL_sampler_lerp2_active = 183 +TD_PERF_SEL_sampler_lerp3_active = 184 +TD_PERF_SEL_sampler_lerp4_active = 185 +TD_PERF_SEL_sampler_lerp5_active = 186 +TD_PERF_SEL_sampler_lerp6_active = 187 +TD_PERF_SEL_sampler_lerp7_active = 188 +TD_PERF_SEL_nofilter_total_num_comps_to_lds = 189 +TD_PERF_SEL_nofilter_byte_cycling_4cycles = 190 +TD_PERF_SEL_nofilter_byte_cycling_8cycles = 191 +TD_PERF_SEL_nofilter_byte_cycling_16cycles = 192 +TD_PERF_SEL_nofilter_dword_cycling_2cycles = 193 +TD_PERF_SEL_nofilter_dword_cycling_4cycles = 194 +TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 195 +TD_PERF_SEL_store_preempts_a_load = 200 +TD_PERF_SEL_sample_2x_instr = 201 +TD_PERF_SEL_gather4_2x_instr = 202 +TD_PERF_SEL_gather4h_2x_instr = 203 +TD_PERF_SEL_getlod_2x_instr = 204 +TD_PERF_SEL_resmap_2x_instr = 205 +TD_PERF_SEL_2x_sampler_op_with_1_unlit_quad = 206 +TD_PERF_SEL_2x_sampler_op_with_both_quads_unlit = 207 +TD_PERF_SEL_tri_proc_node_override_slot0 = 208 +TD_PERF_SEL_tri_run_intersect_ahs_slot0 = 209 +TD_PERF_SEL_tri_run_ahs_slot0 = 210 +TD_PERF_SEL_tri_proc_node_override_slot1 = 231 +TD_PERF_SEL_tri_run_intersect_ahs_slot1 = 232 +TD_PERF_SEL_tri_run_ahs_slot1 = 233 +TD_PERF_SEL_instance_mask_culled = 241 +TD_PERF_SEL_box_opaque_culled = 242 +TD_PERF_SEL_box_non_opaque_culled = 243 +TD_PERF_SEL_box_with_triangle_children_only_culled = 244 +TD_PERF_SEL_box_with_procedural_children_only_culled = 245 +TD_PERF_SEL_triangle_opaque_culled = 246 +TD_PERF_SEL_triangle_non_opaque_culled = 247 +TD_PERF_SEL_triangle_front_facing_culled = 248 +TD_PERF_SEL_triangle_back_facing_culled = 249 +TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL2A_PERF_SEL' +GL2A_PERF_SEL__enumvalues = { + 0: 'GL2A_PERF_SEL_NONE', + 1: 'GL2A_PERF_SEL_CYCLE', + 2: 'GL2A_PERF_SEL_BUSY', + 3: 'GL2A_PERF_SEL_REQ_GL2C0', + 4: 'GL2A_PERF_SEL_REQ_GL2C1', + 5: 'GL2A_PERF_SEL_REQ_GL2C2', + 6: 'GL2A_PERF_SEL_REQ_GL2C3', + 7: 'GL2A_PERF_SEL_REQ_GL2C4', + 8: 'GL2A_PERF_SEL_REQ_GL2C5', + 9: 'GL2A_PERF_SEL_REQ_GL2C6', + 10: 'GL2A_PERF_SEL_REQ_GL2C7', + 19: 'GL2A_PERF_SEL_REQ_BURST_GL2C0', + 20: 'GL2A_PERF_SEL_REQ_BURST_GL2C1', + 21: 'GL2A_PERF_SEL_REQ_BURST_GL2C2', + 22: 'GL2A_PERF_SEL_REQ_BURST_GL2C3', + 23: 'GL2A_PERF_SEL_REQ_BURST_GL2C4', + 24: 'GL2A_PERF_SEL_REQ_BURST_GL2C5', + 25: 'GL2A_PERF_SEL_REQ_BURST_GL2C6', + 26: 'GL2A_PERF_SEL_REQ_BURST_GL2C7', + 27: 'GL2A_PERF_SEL_REQ_STALL_GL2C0', + 28: 'GL2A_PERF_SEL_REQ_STALL_GL2C1', + 29: 'GL2A_PERF_SEL_REQ_STALL_GL2C2', + 30: 'GL2A_PERF_SEL_REQ_STALL_GL2C3', + 31: 'GL2A_PERF_SEL_REQ_STALL_GL2C4', + 32: 'GL2A_PERF_SEL_REQ_STALL_GL2C5', + 33: 'GL2A_PERF_SEL_REQ_STALL_GL2C6', + 34: 'GL2A_PERF_SEL_REQ_STALL_GL2C7', + 35: 'GL2A_PERF_SEL_RTN_STALL_GL2C0', + 36: 'GL2A_PERF_SEL_RTN_STALL_GL2C1', + 37: 'GL2A_PERF_SEL_RTN_STALL_GL2C2', + 38: 'GL2A_PERF_SEL_RTN_STALL_GL2C3', + 39: 'GL2A_PERF_SEL_RTN_STALL_GL2C4', + 40: 'GL2A_PERF_SEL_RTN_STALL_GL2C5', + 41: 'GL2A_PERF_SEL_RTN_STALL_GL2C6', + 42: 'GL2A_PERF_SEL_RTN_STALL_GL2C7', + 43: 'GL2A_PERF_SEL_RTN_CLIENT0', + 44: 'GL2A_PERF_SEL_RTN_CLIENT1', + 45: 'GL2A_PERF_SEL_RTN_CLIENT2', + 46: 'GL2A_PERF_SEL_RTN_CLIENT3', + 47: 'GL2A_PERF_SEL_RTN_CLIENT4', + 48: 'GL2A_PERF_SEL_RTN_CLIENT5', + 49: 'GL2A_PERF_SEL_RTN_CLIENT6', + 50: 'GL2A_PERF_SEL_RTN_CLIENT7', + 51: 'GL2A_PERF_SEL_RTN_CLIENT8', + 52: 'GL2A_PERF_SEL_RTN_CLIENT9', + 53: 'GL2A_PERF_SEL_RTN_CLIENT10', + 54: 'GL2A_PERF_SEL_RTN_CLIENT11', + 55: 'GL2A_PERF_SEL_RTN_CLIENT12', + 56: 'GL2A_PERF_SEL_RTN_CLIENT13', + 57: 'GL2A_PERF_SEL_RTN_CLIENT14', + 58: 'GL2A_PERF_SEL_RTN_CLIENT15', + 59: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', + 60: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', + 61: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', + 62: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', + 63: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', + 64: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', + 65: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', + 66: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', + 67: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', + 68: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', + 69: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', + 70: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', + 71: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', + 72: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', + 73: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', + 74: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', + 75: 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', + 76: 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', + 77: 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', + 78: 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', + 79: 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', + 80: 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', + 81: 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', + 82: 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', + 83: 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', + 84: 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', + 85: 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', + 86: 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', + 87: 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', + 88: 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', + 89: 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', + 90: 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', + 91: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', + 92: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', + 93: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', + 94: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', + 95: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', + 96: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', + 97: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', + 98: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', + 99: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', + 100: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', + 101: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', + 103: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', + 104: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', + 105: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', + 106: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', + 107: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', +} +GL2A_PERF_SEL_NONE = 0 +GL2A_PERF_SEL_CYCLE = 1 +GL2A_PERF_SEL_BUSY = 2 +GL2A_PERF_SEL_REQ_GL2C0 = 3 +GL2A_PERF_SEL_REQ_GL2C1 = 4 +GL2A_PERF_SEL_REQ_GL2C2 = 5 +GL2A_PERF_SEL_REQ_GL2C3 = 6 +GL2A_PERF_SEL_REQ_GL2C4 = 7 +GL2A_PERF_SEL_REQ_GL2C5 = 8 +GL2A_PERF_SEL_REQ_GL2C6 = 9 +GL2A_PERF_SEL_REQ_GL2C7 = 10 +GL2A_PERF_SEL_REQ_BURST_GL2C0 = 19 +GL2A_PERF_SEL_REQ_BURST_GL2C1 = 20 +GL2A_PERF_SEL_REQ_BURST_GL2C2 = 21 +GL2A_PERF_SEL_REQ_BURST_GL2C3 = 22 +GL2A_PERF_SEL_REQ_BURST_GL2C4 = 23 +GL2A_PERF_SEL_REQ_BURST_GL2C5 = 24 +GL2A_PERF_SEL_REQ_BURST_GL2C6 = 25 +GL2A_PERF_SEL_REQ_BURST_GL2C7 = 26 +GL2A_PERF_SEL_REQ_STALL_GL2C0 = 27 +GL2A_PERF_SEL_REQ_STALL_GL2C1 = 28 +GL2A_PERF_SEL_REQ_STALL_GL2C2 = 29 +GL2A_PERF_SEL_REQ_STALL_GL2C3 = 30 +GL2A_PERF_SEL_REQ_STALL_GL2C4 = 31 +GL2A_PERF_SEL_REQ_STALL_GL2C5 = 32 +GL2A_PERF_SEL_REQ_STALL_GL2C6 = 33 +GL2A_PERF_SEL_REQ_STALL_GL2C7 = 34 +GL2A_PERF_SEL_RTN_STALL_GL2C0 = 35 +GL2A_PERF_SEL_RTN_STALL_GL2C1 = 36 +GL2A_PERF_SEL_RTN_STALL_GL2C2 = 37 +GL2A_PERF_SEL_RTN_STALL_GL2C3 = 38 +GL2A_PERF_SEL_RTN_STALL_GL2C4 = 39 +GL2A_PERF_SEL_RTN_STALL_GL2C5 = 40 +GL2A_PERF_SEL_RTN_STALL_GL2C6 = 41 +GL2A_PERF_SEL_RTN_STALL_GL2C7 = 42 +GL2A_PERF_SEL_RTN_CLIENT0 = 43 +GL2A_PERF_SEL_RTN_CLIENT1 = 44 +GL2A_PERF_SEL_RTN_CLIENT2 = 45 +GL2A_PERF_SEL_RTN_CLIENT3 = 46 +GL2A_PERF_SEL_RTN_CLIENT4 = 47 +GL2A_PERF_SEL_RTN_CLIENT5 = 48 +GL2A_PERF_SEL_RTN_CLIENT6 = 49 +GL2A_PERF_SEL_RTN_CLIENT7 = 50 +GL2A_PERF_SEL_RTN_CLIENT8 = 51 +GL2A_PERF_SEL_RTN_CLIENT9 = 52 +GL2A_PERF_SEL_RTN_CLIENT10 = 53 +GL2A_PERF_SEL_RTN_CLIENT11 = 54 +GL2A_PERF_SEL_RTN_CLIENT12 = 55 +GL2A_PERF_SEL_RTN_CLIENT13 = 56 +GL2A_PERF_SEL_RTN_CLIENT14 = 57 +GL2A_PERF_SEL_RTN_CLIENT15 = 58 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 59 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 60 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 61 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 62 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 63 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 64 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 65 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 66 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 67 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 68 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 69 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 70 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 71 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 72 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 73 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 74 +GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 75 +GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 76 +GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 77 +GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 78 +GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 79 +GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 80 +GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 81 +GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 82 +GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 83 +GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 84 +GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 85 +GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 86 +GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 87 +GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 88 +GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 89 +GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 90 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 91 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 92 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 93 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 94 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 95 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 96 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 97 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 98 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 99 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 100 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 101 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 103 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 104 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 105 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 106 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 107 +GL2A_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL2C_PERF_SEL' +GL2C_PERF_SEL__enumvalues = { + 0: 'GL2C_PERF_SEL_NONE', + 1: 'GL2C_PERF_SEL_CYCLE', + 2: 'GL2C_PERF_SEL_BUSY', + 3: 'GL2C_PERF_SEL_REQ', + 4: 'GL2C_PERF_SEL_VOL_REQ', + 5: 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', + 6: 'GL2C_PERF_SEL_READ', + 7: 'GL2C_PERF_SEL_WRITE', + 8: 'GL2C_PERF_SEL_ATOMIC', + 9: 'GL2C_PERF_SEL_NOP_ACK', + 10: 'GL2C_PERF_SEL_NOP_RTN0', + 11: 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', + 12: 'GL2C_PERF_SEL_METADATA_READ_REQ', + 13: 'GL2C_PERF_SEL_CLIENT0_REQ', + 14: 'GL2C_PERF_SEL_CLIENT1_REQ', + 15: 'GL2C_PERF_SEL_CLIENT2_REQ', + 16: 'GL2C_PERF_SEL_CLIENT3_REQ', + 17: 'GL2C_PERF_SEL_CLIENT4_REQ', + 18: 'GL2C_PERF_SEL_CLIENT5_REQ', + 19: 'GL2C_PERF_SEL_CLIENT6_REQ', + 20: 'GL2C_PERF_SEL_CLIENT7_REQ', + 21: 'GL2C_PERF_SEL_CLIENT8_REQ', + 22: 'GL2C_PERF_SEL_CLIENT9_REQ', + 23: 'GL2C_PERF_SEL_CLIENT10_REQ', + 24: 'GL2C_PERF_SEL_CLIENT11_REQ', + 25: 'GL2C_PERF_SEL_CLIENT12_REQ', + 26: 'GL2C_PERF_SEL_CLIENT13_REQ', + 27: 'GL2C_PERF_SEL_CLIENT14_REQ', + 28: 'GL2C_PERF_SEL_CLIENT15_REQ', + 29: 'GL2C_PERF_SEL_C_RW_S_REQ', + 30: 'GL2C_PERF_SEL_C_RW_US_REQ', + 31: 'GL2C_PERF_SEL_C_RO_S_REQ', + 32: 'GL2C_PERF_SEL_C_RO_US_REQ', + 33: 'GL2C_PERF_SEL_UC_REQ', + 34: 'GL2C_PERF_SEL_LRU_REQ', + 35: 'GL2C_PERF_SEL_STREAM_REQ', + 36: 'GL2C_PERF_SEL_BYPASS_REQ', + 37: 'GL2C_PERF_SEL_NOA_REQ', + 38: 'GL2C_PERF_SEL_SHARED_REQ', + 39: 'GL2C_PERF_SEL_HIT', + 40: 'GL2C_PERF_SEL_MISS', + 41: 'GL2C_PERF_SEL_FULL_HIT', + 42: 'GL2C_PERF_SEL_PARTIAL_32B_HIT', + 43: 'GL2C_PERF_SEL_PARTIAL_64B_HIT', + 44: 'GL2C_PERF_SEL_PARTIAL_96B_HIT', + 45: 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', + 46: 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', + 47: 'GL2C_PERF_SEL_UNCACHED_WRITE', + 48: 'GL2C_PERF_SEL_WRITEBACK', + 49: 'GL2C_PERF_SEL_NORMAL_WRITEBACK', + 50: 'GL2C_PERF_SEL_EVICT', + 51: 'GL2C_PERF_SEL_NORMAL_EVICT', + 52: 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', + 53: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', + 54: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', + 55: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', + 56: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', + 57: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', + 58: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', + 59: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', + 60: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', + 61: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', + 62: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', + 63: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', + 64: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', + 65: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', + 66: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', + 67: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', + 68: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', + 69: 'GL2C_PERF_SEL_READ_32_REQ', + 70: 'GL2C_PERF_SEL_READ_64_REQ', + 71: 'GL2C_PERF_SEL_READ_128_REQ', + 72: 'GL2C_PERF_SEL_WRITE_32_REQ', + 73: 'GL2C_PERF_SEL_WRITE_64_REQ', + 74: 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', + 75: 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', + 76: 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', + 77: 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', + 78: 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', + 79: 'GL2C_PERF_SEL_MC_WRREQ', + 80: 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', + 81: 'GL2C_PERF_SEL_EA_WRREQ_64B', + 82: 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', + 83: 'GL2C_PERF_SEL_MC_WRREQ_STALL', + 84: 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', + 85: 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', + 86: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', + 87: 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', + 88: 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', + 89: 'GL2C_PERF_SEL_EA_ATOMIC', + 90: 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', + 91: 'GL2C_PERF_SEL_MC_RDREQ', + 92: 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', + 93: 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', + 94: 'GL2C_PERF_SEL_EA_RDREQ_32B', + 95: 'GL2C_PERF_SEL_EA_RDREQ_64B', + 96: 'GL2C_PERF_SEL_EA_RDREQ_96B', + 97: 'GL2C_PERF_SEL_EA_RDREQ_128B', + 98: 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', + 99: 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', + 100: 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', + 101: 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', + 102: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', + 103: 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', + 104: 'GL2C_PERF_SEL_EA_RDREQ_DRAM', + 105: 'GL2C_PERF_SEL_EA_WRREQ_DRAM', + 106: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', + 107: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', + 108: 'GL2C_PERF_SEL_ONION_READ', + 109: 'GL2C_PERF_SEL_ONION_WRITE', + 110: 'GL2C_PERF_SEL_IO_READ', + 111: 'GL2C_PERF_SEL_IO_WRITE', + 112: 'GL2C_PERF_SEL_GARLIC_READ', + 113: 'GL2C_PERF_SEL_GARLIC_WRITE', + 114: 'GL2C_PERF_SEL_EA_OUTSTANDING', + 115: 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', + 116: 'GL2C_PERF_SEL_SRC_FIFO_FULL', + 117: 'GL2C_PERF_SEL_TAG_STALL', + 118: 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 119: 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 120: 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 121: 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 122: 'GL2C_PERF_SEL_TAG_READ_DST_STALL', + 123: 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', + 124: 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 125: 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 126: 'GL2C_PERF_SEL_BUBBLE', + 127: 'GL2C_PERF_SEL_IB_REQ', + 128: 'GL2C_PERF_SEL_IB_STALL', + 129: 'GL2C_PERF_SEL_IB_TAG_STALL', + 130: 'GL2C_PERF_SEL_RETURN_ACK', + 131: 'GL2C_PERF_SEL_RETURN_DATA', + 132: 'GL2C_PERF_SEL_EA_RDRET_NACK', + 133: 'GL2C_PERF_SEL_EA_WRRET_NACK', + 134: 'GL2C_PERF_SEL_GL2A_LEVEL', + 135: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 136: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', + 137: 'GL2C_PERF_SEL_GCR_INV', + 138: 'GL2C_PERF_SEL_GCR_WB', + 139: 'GL2C_PERF_SEL_GCR_DISCARD', + 140: 'GL2C_PERF_SEL_GCR_RANGE', + 141: 'GL2C_PERF_SEL_GCR_ALL', + 142: 'GL2C_PERF_SEL_GCR_VOL', + 143: 'GL2C_PERF_SEL_GCR_UNSHARED', + 144: 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', + 145: 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', + 146: 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', + 147: 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', + 148: 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', + 149: 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', + 150: 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', + 151: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', + 152: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', + 153: 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', + 154: 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', + 155: 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', + 156: 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', + 157: 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', + 158: 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', + 159: 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', + 160: 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', + 161: 'GL2C_PERF_SEL_GCR_WBINVL2_START', + 162: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', + 163: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', + 164: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', + 165: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', +} +GL2C_PERF_SEL_NONE = 0 +GL2C_PERF_SEL_CYCLE = 1 +GL2C_PERF_SEL_BUSY = 2 +GL2C_PERF_SEL_REQ = 3 +GL2C_PERF_SEL_VOL_REQ = 4 +GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 5 +GL2C_PERF_SEL_READ = 6 +GL2C_PERF_SEL_WRITE = 7 +GL2C_PERF_SEL_ATOMIC = 8 +GL2C_PERF_SEL_NOP_ACK = 9 +GL2C_PERF_SEL_NOP_RTN0 = 10 +GL2C_PERF_SEL_COMPRESSED_READ_REQ = 11 +GL2C_PERF_SEL_METADATA_READ_REQ = 12 +GL2C_PERF_SEL_CLIENT0_REQ = 13 +GL2C_PERF_SEL_CLIENT1_REQ = 14 +GL2C_PERF_SEL_CLIENT2_REQ = 15 +GL2C_PERF_SEL_CLIENT3_REQ = 16 +GL2C_PERF_SEL_CLIENT4_REQ = 17 +GL2C_PERF_SEL_CLIENT5_REQ = 18 +GL2C_PERF_SEL_CLIENT6_REQ = 19 +GL2C_PERF_SEL_CLIENT7_REQ = 20 +GL2C_PERF_SEL_CLIENT8_REQ = 21 +GL2C_PERF_SEL_CLIENT9_REQ = 22 +GL2C_PERF_SEL_CLIENT10_REQ = 23 +GL2C_PERF_SEL_CLIENT11_REQ = 24 +GL2C_PERF_SEL_CLIENT12_REQ = 25 +GL2C_PERF_SEL_CLIENT13_REQ = 26 +GL2C_PERF_SEL_CLIENT14_REQ = 27 +GL2C_PERF_SEL_CLIENT15_REQ = 28 +GL2C_PERF_SEL_C_RW_S_REQ = 29 +GL2C_PERF_SEL_C_RW_US_REQ = 30 +GL2C_PERF_SEL_C_RO_S_REQ = 31 +GL2C_PERF_SEL_C_RO_US_REQ = 32 +GL2C_PERF_SEL_UC_REQ = 33 +GL2C_PERF_SEL_LRU_REQ = 34 +GL2C_PERF_SEL_STREAM_REQ = 35 +GL2C_PERF_SEL_BYPASS_REQ = 36 +GL2C_PERF_SEL_NOA_REQ = 37 +GL2C_PERF_SEL_SHARED_REQ = 38 +GL2C_PERF_SEL_HIT = 39 +GL2C_PERF_SEL_MISS = 40 +GL2C_PERF_SEL_FULL_HIT = 41 +GL2C_PERF_SEL_PARTIAL_32B_HIT = 42 +GL2C_PERF_SEL_PARTIAL_64B_HIT = 43 +GL2C_PERF_SEL_PARTIAL_96B_HIT = 44 +GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 45 +GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 46 +GL2C_PERF_SEL_UNCACHED_WRITE = 47 +GL2C_PERF_SEL_WRITEBACK = 48 +GL2C_PERF_SEL_NORMAL_WRITEBACK = 49 +GL2C_PERF_SEL_EVICT = 50 +GL2C_PERF_SEL_NORMAL_EVICT = 51 +GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 52 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 53 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 54 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 55 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 56 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 57 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 58 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 59 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 60 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 61 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 62 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 63 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 64 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 65 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 66 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 67 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 68 +GL2C_PERF_SEL_READ_32_REQ = 69 +GL2C_PERF_SEL_READ_64_REQ = 70 +GL2C_PERF_SEL_READ_128_REQ = 71 +GL2C_PERF_SEL_WRITE_32_REQ = 72 +GL2C_PERF_SEL_WRITE_64_REQ = 73 +GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 74 +GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 75 +GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 76 +GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 77 +GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 78 +GL2C_PERF_SEL_MC_WRREQ = 79 +GL2C_PERF_SEL_EA_WRREQ_SNOOP = 80 +GL2C_PERF_SEL_EA_WRREQ_64B = 81 +GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 82 +GL2C_PERF_SEL_MC_WRREQ_STALL = 83 +GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 84 +GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 85 +GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 86 +GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 87 +GL2C_PERF_SEL_MC_WRREQ_LEVEL = 88 +GL2C_PERF_SEL_EA_ATOMIC = 89 +GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 90 +GL2C_PERF_SEL_MC_RDREQ = 91 +GL2C_PERF_SEL_EA_RDREQ_SNOOP = 92 +GL2C_PERF_SEL_EA_RDREQ_SPLIT = 93 +GL2C_PERF_SEL_EA_RDREQ_32B = 94 +GL2C_PERF_SEL_EA_RDREQ_64B = 95 +GL2C_PERF_SEL_EA_RDREQ_96B = 96 +GL2C_PERF_SEL_EA_RDREQ_128B = 97 +GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 98 +GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 99 +GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 100 +GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 101 +GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 102 +GL2C_PERF_SEL_MC_RDREQ_LEVEL = 103 +GL2C_PERF_SEL_EA_RDREQ_DRAM = 104 +GL2C_PERF_SEL_EA_WRREQ_DRAM = 105 +GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 106 +GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 107 +GL2C_PERF_SEL_ONION_READ = 108 +GL2C_PERF_SEL_ONION_WRITE = 109 +GL2C_PERF_SEL_IO_READ = 110 +GL2C_PERF_SEL_IO_WRITE = 111 +GL2C_PERF_SEL_GARLIC_READ = 112 +GL2C_PERF_SEL_GARLIC_WRITE = 113 +GL2C_PERF_SEL_EA_OUTSTANDING = 114 +GL2C_PERF_SEL_LATENCY_FIFO_FULL = 115 +GL2C_PERF_SEL_SRC_FIFO_FULL = 116 +GL2C_PERF_SEL_TAG_STALL = 117 +GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 118 +GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 119 +GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 120 +GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 121 +GL2C_PERF_SEL_TAG_READ_DST_STALL = 122 +GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 123 +GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 124 +GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 125 +GL2C_PERF_SEL_BUBBLE = 126 +GL2C_PERF_SEL_IB_REQ = 127 +GL2C_PERF_SEL_IB_STALL = 128 +GL2C_PERF_SEL_IB_TAG_STALL = 129 +GL2C_PERF_SEL_RETURN_ACK = 130 +GL2C_PERF_SEL_RETURN_DATA = 131 +GL2C_PERF_SEL_EA_RDRET_NACK = 132 +GL2C_PERF_SEL_EA_WRRET_NACK = 133 +GL2C_PERF_SEL_GL2A_LEVEL = 134 +GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 135 +GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 136 +GL2C_PERF_SEL_GCR_INV = 137 +GL2C_PERF_SEL_GCR_WB = 138 +GL2C_PERF_SEL_GCR_DISCARD = 139 +GL2C_PERF_SEL_GCR_RANGE = 140 +GL2C_PERF_SEL_GCR_ALL = 141 +GL2C_PERF_SEL_GCR_VOL = 142 +GL2C_PERF_SEL_GCR_UNSHARED = 143 +GL2C_PERF_SEL_GCR_GL2_INV_ALL = 144 +GL2C_PERF_SEL_GCR_GL2_WB_ALL = 145 +GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 146 +GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 147 +GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 148 +GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 149 +GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 150 +GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 151 +GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 152 +GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 153 +GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 154 +GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 155 +GL2C_PERF_SEL_GCR_INVL2_VOL_START = 156 +GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 157 +GL2C_PERF_SEL_GCR_WBL2_VOL_START = 158 +GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 159 +GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 160 +GL2C_PERF_SEL_GCR_WBINVL2_START = 161 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 162 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 163 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 164 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 165 +GL2C_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SX_BLEND_OPT' +SX_BLEND_OPT__enumvalues = { + 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', +} +BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 +BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 +BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 +BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 +BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 +BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 +BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 +BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 +SX_BLEND_OPT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_DOWNCONVERT_FORMAT' +SX_DOWNCONVERT_FORMAT__enumvalues = { + 0: 'SX_RT_EXPORT_NO_CONVERSION', + 1: 'SX_RT_EXPORT_32_R', + 2: 'SX_RT_EXPORT_32_A', + 3: 'SX_RT_EXPORT_10_11_11', + 4: 'SX_RT_EXPORT_2_10_10_10', + 5: 'SX_RT_EXPORT_8_8_8_8', + 6: 'SX_RT_EXPORT_5_6_5', + 7: 'SX_RT_EXPORT_1_5_5_5', + 8: 'SX_RT_EXPORT_4_4_4_4', + 9: 'SX_RT_EXPORT_16_16_GR', + 10: 'SX_RT_EXPORT_16_16_AR', + 11: 'SX_RT_EXPORT_9_9_9_E5', + 12: 'SX_RT_EXPORT_2_10_10_10_7E3', + 13: 'SX_RT_EXPORT_2_10_10_10_6E4', +} +SX_RT_EXPORT_NO_CONVERSION = 0 +SX_RT_EXPORT_32_R = 1 +SX_RT_EXPORT_32_A = 2 +SX_RT_EXPORT_10_11_11 = 3 +SX_RT_EXPORT_2_10_10_10 = 4 +SX_RT_EXPORT_8_8_8_8 = 5 +SX_RT_EXPORT_5_6_5 = 6 +SX_RT_EXPORT_1_5_5_5 = 7 +SX_RT_EXPORT_4_4_4_4 = 8 +SX_RT_EXPORT_16_16_GR = 9 +SX_RT_EXPORT_16_16_AR = 10 +SX_RT_EXPORT_9_9_9_E5 = 11 +SX_RT_EXPORT_2_10_10_10_7E3 = 12 +SX_RT_EXPORT_2_10_10_10_6E4 = 13 +SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_OPT_COMB_FCN' +SX_OPT_COMB_FCN__enumvalues = { + 0: 'OPT_COMB_NONE', + 1: 'OPT_COMB_ADD', + 2: 'OPT_COMB_SUBTRACT', + 3: 'OPT_COMB_MIN', + 4: 'OPT_COMB_MAX', + 5: 'OPT_COMB_REVSUBTRACT', + 6: 'OPT_COMB_BLEND_DISABLED', + 7: 'OPT_COMB_SAFE_ADD', +} +OPT_COMB_NONE = 0 +OPT_COMB_ADD = 1 +OPT_COMB_SUBTRACT = 2 +OPT_COMB_MIN = 3 +OPT_COMB_MAX = 4 +OPT_COMB_REVSUBTRACT = 5 +OPT_COMB_BLEND_DISABLED = 6 +OPT_COMB_SAFE_ADD = 7 +SX_OPT_COMB_FCN = ctypes.c_uint32 # enum + +# values for enumeration 'SX_PERFCOUNTER_VALS' +SX_PERFCOUNTER_VALS__enumvalues = { + 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', + 1: 'SX_PERF_SEL_PA_REQ', + 2: 'SX_PERF_SEL_PA_POS', + 3: 'SX_PERF_SEL_CLOCK', + 4: 'SX_PERF_SEL_GATE_EN1', + 5: 'SX_PERF_SEL_GATE_EN2', + 6: 'SX_PERF_SEL_GATE_EN3', + 7: 'SX_PERF_SEL_GATE_EN4', + 8: 'SX_PERF_SEL_SH_POS_STARVE', + 9: 'SX_PERF_SEL_SH_COLOR_STARVE', + 10: 'SX_PERF_SEL_SH_POS_STALL', + 11: 'SX_PERF_SEL_SH_COLOR_STALL', + 12: 'SX_PERF_SEL_DB0_PIXELS', + 13: 'SX_PERF_SEL_DB0_HALF_QUADS', + 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', + 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', + 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', + 17: 'SX_PERF_SEL_DB1_PIXELS', + 18: 'SX_PERF_SEL_DB1_HALF_QUADS', + 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', + 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', + 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', + 22: 'SX_PERF_SEL_DB2_PIXELS', + 23: 'SX_PERF_SEL_DB2_HALF_QUADS', + 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', + 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', + 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', + 27: 'SX_PERF_SEL_DB3_PIXELS', + 28: 'SX_PERF_SEL_DB3_HALF_QUADS', + 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', + 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', + 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', + 32: 'SX_PERF_SEL_COL_BUSY', + 33: 'SX_PERF_SEL_POS_BUSY', + 34: 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', + 35: 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', + 36: 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', + 37: 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', + 38: 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', + 39: 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', + 40: 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', + 41: 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', + 42: 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', + 43: 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', + 44: 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', + 45: 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', + 46: 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', + 47: 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', + 48: 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', + 49: 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', + 50: 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', + 51: 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', + 52: 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', + 53: 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', + 54: 'SX_PERF_SEL_PA_REQ_LATENCY', + 55: 'SX_PERF_SEL_POS_SCBD_STALL', + 56: 'SX_PERF_SEL_CLOCK_DROP_STALL', + 57: 'SX_PERF_SEL_GATE_EN5', + 58: 'SX_PERF_SEL_GATE_EN6', + 59: 'SX_PERF_SEL_DB0_SIZE', + 60: 'SX_PERF_SEL_DB1_SIZE', + 61: 'SX_PERF_SEL_DB2_SIZE', + 62: 'SX_PERF_SEL_DB3_SIZE', + 63: 'SX_PERF_SEL_IDX_STALL_CYCLES', + 64: 'SX_PERF_SEL_IDX_IDLE_CYCLES', + 65: 'SX_PERF_SEL_IDX_REQ', + 66: 'SX_PERF_SEL_IDX_RET', + 67: 'SX_PERF_SEL_IDX_REQ_LATENCY', + 68: 'SX_PERF_SEL_IDX_SCBD_STALL', + 69: 'SX_PERF_SEL_GATE_EN7', + 70: 'SX_PERF_SEL_GATE_EN8', + 71: 'SX_PERF_SEL_SH_IDX_STARVE', + 72: 'SX_PERF_SEL_IDX_BUSY', + 73: 'SX_PERF_SEL_PA_POS_BANK_CONF', + 74: 'SX_PERF_SEL_DB0_END_OF_WAVE', + 75: 'SX_PERF_SEL_DB0_4X2_DISCARD', + 76: 'SX_PERF_SEL_DB1_END_OF_WAVE', + 77: 'SX_PERF_SEL_DB1_4X2_DISCARD', + 78: 'SX_PERF_SEL_DB2_END_OF_WAVE', + 79: 'SX_PERF_SEL_DB2_4X2_DISCARD', + 80: 'SX_PERF_SEL_DB3_END_OF_WAVE', + 81: 'SX_PERF_SEL_DB3_4X2_DISCARD', +} +SX_PERF_SEL_PA_IDLE_CYCLES = 0 +SX_PERF_SEL_PA_REQ = 1 +SX_PERF_SEL_PA_POS = 2 +SX_PERF_SEL_CLOCK = 3 +SX_PERF_SEL_GATE_EN1 = 4 +SX_PERF_SEL_GATE_EN2 = 5 +SX_PERF_SEL_GATE_EN3 = 6 +SX_PERF_SEL_GATE_EN4 = 7 +SX_PERF_SEL_SH_POS_STARVE = 8 +SX_PERF_SEL_SH_COLOR_STARVE = 9 +SX_PERF_SEL_SH_POS_STALL = 10 +SX_PERF_SEL_SH_COLOR_STALL = 11 +SX_PERF_SEL_DB0_PIXELS = 12 +SX_PERF_SEL_DB0_HALF_QUADS = 13 +SX_PERF_SEL_DB0_PIXEL_STALL = 14 +SX_PERF_SEL_DB0_PIXEL_IDLE = 15 +SX_PERF_SEL_DB0_PRED_PIXELS = 16 +SX_PERF_SEL_DB1_PIXELS = 17 +SX_PERF_SEL_DB1_HALF_QUADS = 18 +SX_PERF_SEL_DB1_PIXEL_STALL = 19 +SX_PERF_SEL_DB1_PIXEL_IDLE = 20 +SX_PERF_SEL_DB1_PRED_PIXELS = 21 +SX_PERF_SEL_DB2_PIXELS = 22 +SX_PERF_SEL_DB2_HALF_QUADS = 23 +SX_PERF_SEL_DB2_PIXEL_STALL = 24 +SX_PERF_SEL_DB2_PIXEL_IDLE = 25 +SX_PERF_SEL_DB2_PRED_PIXELS = 26 +SX_PERF_SEL_DB3_PIXELS = 27 +SX_PERF_SEL_DB3_HALF_QUADS = 28 +SX_PERF_SEL_DB3_PIXEL_STALL = 29 +SX_PERF_SEL_DB3_PIXEL_IDLE = 30 +SX_PERF_SEL_DB3_PRED_PIXELS = 31 +SX_PERF_SEL_COL_BUSY = 32 +SX_PERF_SEL_POS_BUSY = 33 +SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 34 +SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 35 +SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 36 +SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 37 +SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 38 +SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 39 +SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 40 +SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 41 +SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 42 +SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 43 +SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 44 +SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 45 +SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 46 +SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 47 +SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 48 +SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 49 +SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 50 +SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 51 +SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 52 +SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 53 +SX_PERF_SEL_PA_REQ_LATENCY = 54 +SX_PERF_SEL_POS_SCBD_STALL = 55 +SX_PERF_SEL_CLOCK_DROP_STALL = 56 +SX_PERF_SEL_GATE_EN5 = 57 +SX_PERF_SEL_GATE_EN6 = 58 +SX_PERF_SEL_DB0_SIZE = 59 +SX_PERF_SEL_DB1_SIZE = 60 +SX_PERF_SEL_DB2_SIZE = 61 +SX_PERF_SEL_DB3_SIZE = 62 +SX_PERF_SEL_IDX_STALL_CYCLES = 63 +SX_PERF_SEL_IDX_IDLE_CYCLES = 64 +SX_PERF_SEL_IDX_REQ = 65 +SX_PERF_SEL_IDX_RET = 66 +SX_PERF_SEL_IDX_REQ_LATENCY = 67 +SX_PERF_SEL_IDX_SCBD_STALL = 68 +SX_PERF_SEL_GATE_EN7 = 69 +SX_PERF_SEL_GATE_EN8 = 70 +SX_PERF_SEL_SH_IDX_STARVE = 71 +SX_PERF_SEL_IDX_BUSY = 72 +SX_PERF_SEL_PA_POS_BANK_CONF = 73 +SX_PERF_SEL_DB0_END_OF_WAVE = 74 +SX_PERF_SEL_DB0_4X2_DISCARD = 75 +SX_PERF_SEL_DB1_END_OF_WAVE = 76 +SX_PERF_SEL_DB1_4X2_DISCARD = 77 +SX_PERF_SEL_DB2_END_OF_WAVE = 78 +SX_PERF_SEL_DB2_4X2_DISCARD = 79 +SX_PERF_SEL_DB3_END_OF_WAVE = 80 +SX_PERF_SEL_DB3_4X2_DISCARD = 81 +SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum + +# values for enumeration 'CompareFrag' +CompareFrag__enumvalues = { + 0: 'FRAG_NEVER', + 1: 'FRAG_LESS', + 2: 'FRAG_EQUAL', + 3: 'FRAG_LEQUAL', + 4: 'FRAG_GREATER', + 5: 'FRAG_NOTEQUAL', + 6: 'FRAG_GEQUAL', + 7: 'FRAG_ALWAYS', +} +FRAG_NEVER = 0 +FRAG_LESS = 1 +FRAG_EQUAL = 2 +FRAG_LEQUAL = 3 +FRAG_GREATER = 4 +FRAG_NOTEQUAL = 5 +FRAG_GEQUAL = 6 +FRAG_ALWAYS = 7 +CompareFrag = ctypes.c_uint32 # enum + +# values for enumeration 'ConservativeZExport' +ConservativeZExport__enumvalues = { + 0: 'EXPORT_ANY_Z', + 1: 'EXPORT_LESS_THAN_Z', + 2: 'EXPORT_GREATER_THAN_Z', + 3: 'EXPORT_RESERVED', +} +EXPORT_ANY_Z = 0 +EXPORT_LESS_THAN_Z = 1 +EXPORT_GREATER_THAN_Z = 2 +EXPORT_RESERVED = 3 +ConservativeZExport = ctypes.c_uint32 # enum + +# values for enumeration 'DbMemArbWatermarks' +DbMemArbWatermarks__enumvalues = { + 0: 'TRANSFERRED_64_BYTES', + 1: 'TRANSFERRED_128_BYTES', + 2: 'TRANSFERRED_256_BYTES', + 3: 'TRANSFERRED_512_BYTES', + 4: 'TRANSFERRED_1024_BYTES', + 5: 'TRANSFERRED_2048_BYTES', + 6: 'TRANSFERRED_4096_BYTES', + 7: 'TRANSFERRED_8192_BYTES', +} +TRANSFERRED_64_BYTES = 0 +TRANSFERRED_128_BYTES = 1 +TRANSFERRED_256_BYTES = 2 +TRANSFERRED_512_BYTES = 3 +TRANSFERRED_1024_BYTES = 4 +TRANSFERRED_2048_BYTES = 5 +TRANSFERRED_4096_BYTES = 6 +TRANSFERRED_8192_BYTES = 7 +DbMemArbWatermarks = ctypes.c_uint32 # enum + +# values for enumeration 'DbPRTFaultBehavior' +DbPRTFaultBehavior__enumvalues = { + 0: 'FAULT_ZERO', + 1: 'FAULT_ONE', + 2: 'FAULT_FAIL', + 3: 'FAULT_PASS', +} +FAULT_ZERO = 0 +FAULT_ONE = 1 +FAULT_FAIL = 2 +FAULT_PASS = 3 +DbPRTFaultBehavior = ctypes.c_uint32 # enum + +# values for enumeration 'DbPSLControl' +DbPSLControl__enumvalues = { + 0: 'PSLC_AUTO', + 1: 'PSLC_ON_HANG_ONLY', + 2: 'PSLC_ASAP', + 3: 'PSLC_COUNTDOWN', +} +PSLC_AUTO = 0 +PSLC_ON_HANG_ONLY = 1 +PSLC_ASAP = 2 +PSLC_COUNTDOWN = 3 +DbPSLControl = ctypes.c_uint32 # enum + +# values for enumeration 'ForceControl' +ForceControl__enumvalues = { + 0: 'FORCE_OFF', + 1: 'FORCE_ENABLE', + 2: 'FORCE_DISABLE', + 3: 'FORCE_RESERVED', +} +FORCE_OFF = 0 +FORCE_ENABLE = 1 +FORCE_DISABLE = 2 +FORCE_RESERVED = 3 +ForceControl = ctypes.c_uint32 # enum + +# values for enumeration 'GLCompressionMode' +GLCompressionMode__enumvalues = { + 0: 'DB_DEFAULT', + 1: 'DB_BYPASS', + 2: 'DB_COMP_WR_DISABLE', + 3: 'DB_BYPASS_WR_DISABLE', +} +DB_DEFAULT = 0 +DB_BYPASS = 1 +DB_COMP_WR_DISABLE = 2 +DB_BYPASS_WR_DISABLE = 3 +GLCompressionMode = ctypes.c_uint32 # enum + +# values for enumeration 'OreoMode' +OreoMode__enumvalues = { + 0: 'OMODE_BLEND', + 1: 'OMODE_O_THEN_B', + 2: 'OMODE_P_THEN_O_THEN_B', + 3: 'OMODE_RESERVED_3', +} +OMODE_BLEND = 0 +OMODE_O_THEN_B = 1 +OMODE_P_THEN_O_THEN_B = 2 +OMODE_RESERVED_3 = 3 +OreoMode = ctypes.c_uint32 # enum + +# values for enumeration 'PerfCounter_Vals' +PerfCounter_Vals__enumvalues = { + 0: 'DB_PERF_SEL_SC_DB_tile_sends', + 1: 'DB_PERF_SEL_SC_DB_tile_busy', + 2: 'DB_PERF_SEL_SC_DB_tile_stalls', + 3: 'DB_PERF_SEL_SC_DB_tile_events', + 4: 'DB_PERF_SEL_SC_DB_tile_tiles', + 5: 'DB_PERF_SEL_SC_DB_tile_covered', + 6: 'DB_PERF_SEL_hiz_tc_read_starved', + 7: 'DB_PERF_SEL_hiz_tc_write_stall', + 8: 'DB_PERF_SEL_hiz_tile_culled', + 9: 'DB_PERF_SEL_his_tile_culled', + 10: 'DB_PERF_SEL_DB_SC_tile_sends', + 11: 'DB_PERF_SEL_DB_SC_tile_busy', + 12: 'DB_PERF_SEL_DB_SC_tile_stalls', + 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 14: 'DB_PERF_SEL_DB_SC_tile_tiles', + 15: 'DB_PERF_SEL_DB_SC_tile_culled', + 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', + 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 23: 'DB_PERF_SEL_SC_DB_quad_sends', + 24: 'DB_PERF_SEL_SC_DB_quad_busy', + 25: 'DB_PERF_SEL_SC_DB_quad_squads', + 26: 'DB_PERF_SEL_SC_DB_quad_tiles', + 27: 'DB_PERF_SEL_SC_DB_quad_pixels', + 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 29: 'DB_PERF_SEL_DB_SC_quad_sends', + 30: 'DB_PERF_SEL_DB_SC_quad_busy', + 31: 'DB_PERF_SEL_DB_SC_quad_stalls', + 32: 'DB_PERF_SEL_DB_SC_quad_tiles', + 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', + 34: 'DB_PERF_SEL_DB_CB_export_events', + 37: 'DB_PERF_SEL_SX_DB_quad_sends', + 38: 'DB_PERF_SEL_SX_DB_quad_busy', + 39: 'DB_PERF_SEL_SX_DB_quad_stalls', + 40: 'DB_PERF_SEL_SX_DB_quad_quads', + 41: 'DB_PERF_SEL_SX_DB_quad_pixels', + 42: 'DB_PERF_SEL_SX_DB_quad_exports', + 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', + 44: 'DB_PERF_SEL_DB_CB_export_sends', + 45: 'DB_PERF_SEL_DB_CB_export_busy', + 46: 'DB_PERF_SEL_DB_CB_export_stalls', + 47: 'DB_PERF_SEL_DB_CB_export_quads', + 48: 'DB_PERF_SEL_tile_rd_sends', + 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 50: 'DB_PERF_SEL_quad_rd_sends', + 51: 'DB_PERF_SEL_quad_rd_busy', + 52: 'DB_PERF_SEL_quad_rd_mi_stall', + 53: 'DB_PERF_SEL_quad_rd_rw_collision', + 54: 'DB_PERF_SEL_quad_rd_tag_stall', + 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', + 56: 'DB_PERF_SEL_quad_rd_panic', + 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 58: 'DB_PERF_SEL_quad_rdret_sends', + 59: 'DB_PERF_SEL_quad_rdret_busy', + 60: 'DB_PERF_SEL_tile_wr_sends', + 61: 'DB_PERF_SEL_tile_wr_acks', + 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 63: 'DB_PERF_SEL_quad_wr_sends', + 64: 'DB_PERF_SEL_quad_wr_busy', + 65: 'DB_PERF_SEL_quad_wr_mi_stall', + 66: 'DB_PERF_SEL_quad_wr_coherency_stall', + 67: 'DB_PERF_SEL_quad_wr_acks', + 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 69: 'DB_PERF_SEL_Tile_Cache_misses', + 70: 'DB_PERF_SEL_Tile_Cache_hits', + 71: 'DB_PERF_SEL_Tile_Cache_flushes', + 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', + 73: 'DB_PERF_SEL_Tile_Cache_starves', + 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 75: 'DB_PERF_SEL_tcp_dispatcher_reads', + 76: 'DB_PERF_SEL_tcp_prefetcher_reads', + 77: 'DB_PERF_SEL_tcp_preloader_reads', + 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', + 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', + 80: 'DB_PERF_SEL_tcp_preloader_flushes', + 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', + 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 95: 'DB_PERF_SEL_Stencil_Cache_misses', + 96: 'DB_PERF_SEL_Stencil_Cache_hits', + 97: 'DB_PERF_SEL_Stencil_Cache_flushes', + 98: 'DB_PERF_SEL_Stencil_Cache_starves', + 99: 'DB_PERF_SEL_Stencil_Cache_frees', + 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', + 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', + 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', + 108: 'DB_PERF_SEL_Z_Cache_frees', + 109: 'DB_PERF_SEL_Plane_Cache_misses', + 110: 'DB_PERF_SEL_Plane_Cache_hits', + 111: 'DB_PERF_SEL_Plane_Cache_flushes', + 112: 'DB_PERF_SEL_Plane_Cache_starves', + 113: 'DB_PERF_SEL_Plane_Cache_frees', + 114: 'DB_PERF_SEL_flush_expanded_stencil', + 115: 'DB_PERF_SEL_flush_compressed_stencil', + 116: 'DB_PERF_SEL_flush_single_stencil', + 117: 'DB_PERF_SEL_planes_flushed', + 118: 'DB_PERF_SEL_flush_1plane', + 119: 'DB_PERF_SEL_flush_2plane', + 120: 'DB_PERF_SEL_flush_3plane', + 121: 'DB_PERF_SEL_flush_4plane', + 122: 'DB_PERF_SEL_flush_5plane', + 123: 'DB_PERF_SEL_flush_6plane', + 124: 'DB_PERF_SEL_flush_7plane', + 125: 'DB_PERF_SEL_flush_8plane', + 126: 'DB_PERF_SEL_flush_9plane', + 127: 'DB_PERF_SEL_flush_10plane', + 128: 'DB_PERF_SEL_flush_11plane', + 129: 'DB_PERF_SEL_flush_12plane', + 130: 'DB_PERF_SEL_flush_13plane', + 131: 'DB_PERF_SEL_flush_14plane', + 132: 'DB_PERF_SEL_flush_15plane', + 133: 'DB_PERF_SEL_flush_16plane', + 134: 'DB_PERF_SEL_flush_expanded_z', + 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 137: 'DB_PERF_SEL_dk_tile_sends', + 138: 'DB_PERF_SEL_dk_tile_busy', + 139: 'DB_PERF_SEL_dk_tile_quad_starves', + 140: 'DB_PERF_SEL_dk_tile_stalls', + 141: 'DB_PERF_SEL_dk_squad_sends', + 142: 'DB_PERF_SEL_dk_squad_busy', + 143: 'DB_PERF_SEL_dk_squad_stalls', + 144: 'DB_PERF_SEL_Op_Pipe_Busy', + 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 146: 'DB_PERF_SEL_qc_busy', + 147: 'DB_PERF_SEL_qc_xfc', + 148: 'DB_PERF_SEL_qc_conflicts', + 149: 'DB_PERF_SEL_qc_full_stall', + 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', + 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', + 153: 'DB_PERF_SEL_tl_busy', + 154: 'DB_PERF_SEL_tl_dtc_read_starved', + 155: 'DB_PERF_SEL_tl_z_fetch_stall', + 156: 'DB_PERF_SEL_tl_stencil_stall', + 157: 'DB_PERF_SEL_tl_z_decompress_stall', + 158: 'DB_PERF_SEL_tl_stencil_locked_stall', + 159: 'DB_PERF_SEL_tl_events', + 160: 'DB_PERF_SEL_tl_summarize_squads', + 161: 'DB_PERF_SEL_tl_flush_expand_squads', + 162: 'DB_PERF_SEL_tl_expand_squads', + 163: 'DB_PERF_SEL_tl_preZ_squads', + 164: 'DB_PERF_SEL_tl_postZ_squads', + 165: 'DB_PERF_SEL_tl_preZ_noop_squads', + 166: 'DB_PERF_SEL_tl_postZ_noop_squads', + 167: 'DB_PERF_SEL_tl_tile_ops', + 168: 'DB_PERF_SEL_tl_in_xfc', + 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 170: 'DB_PERF_SEL_tl_in_fast_z_stall', + 171: 'DB_PERF_SEL_tl_out_xfc', + 172: 'DB_PERF_SEL_tl_out_squads', + 173: 'DB_PERF_SEL_zf_plane_multicycle', + 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', + 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', + 180: 'DB_PERF_SEL_ts_tc_update_stall', + 181: 'DB_PERF_SEL_sc_kick_start', + 182: 'DB_PERF_SEL_sc_kick_end', + 183: 'DB_PERF_SEL_clock_reg_active', + 184: 'DB_PERF_SEL_clock_main_active', + 185: 'DB_PERF_SEL_clock_mem_export_active', + 186: 'DB_PERF_SEL_esr_ps_out_busy', + 187: 'DB_PERF_SEL_esr_ps_lqf_busy', + 188: 'DB_PERF_SEL_esr_ps_lqf_stall', + 189: 'DB_PERF_SEL_etr_out_send', + 190: 'DB_PERF_SEL_etr_out_busy', + 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 193: 'DB_PERF_SEL_etr_out_esr_stall', + 194: 'DB_PERF_SEL_esr_ps_vic_busy', + 195: 'DB_PERF_SEL_esr_ps_vic_stall', + 196: 'DB_PERF_SEL_esr_eot_fwd_busy', + 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 198: 'DB_PERF_SEL_esr_eot_fwd_forward', + 199: 'DB_PERF_SEL_esr_sqq_zi_busy', + 200: 'DB_PERF_SEL_esr_sqq_zi_stall', + 201: 'DB_PERF_SEL_postzl_sq_pt_busy', + 202: 'DB_PERF_SEL_postzl_sq_pt_stall', + 203: 'DB_PERF_SEL_postzl_se_busy', + 204: 'DB_PERF_SEL_postzl_se_stall', + 205: 'DB_PERF_SEL_postzl_partial_launch', + 206: 'DB_PERF_SEL_postzl_full_launch', + 207: 'DB_PERF_SEL_postzl_partial_waiting', + 208: 'DB_PERF_SEL_postzl_tile_mem_stall', + 209: 'DB_PERF_SEL_postzl_tile_init_stall', + 210: 'DB_PERF_SEL_prezl_tile_mem_stall', + 211: 'DB_PERF_SEL_prezl_tile_init_stall', + 212: 'DB_PERF_SEL_dtt_sm_clash_stall', + 213: 'DB_PERF_SEL_dtt_sm_slot_stall', + 214: 'DB_PERF_SEL_dtt_sm_miss_stall', + 215: 'DB_PERF_SEL_mi_rdreq_busy', + 216: 'DB_PERF_SEL_mi_rdreq_stall', + 217: 'DB_PERF_SEL_mi_wrreq_busy', + 218: 'DB_PERF_SEL_mi_wrreq_stall', + 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 220: 'DB_PERF_SEL_dkg_tile_rate_tile', + 221: 'DB_PERF_SEL_prezl_src_in_sends', + 222: 'DB_PERF_SEL_prezl_src_in_stall', + 223: 'DB_PERF_SEL_prezl_src_in_squads', + 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', + 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 227: 'DB_PERF_SEL_prezl_src_out_stall', + 228: 'DB_PERF_SEL_postzl_src_in_sends', + 229: 'DB_PERF_SEL_postzl_src_in_stall', + 230: 'DB_PERF_SEL_postzl_src_in_squads', + 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', + 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 234: 'DB_PERF_SEL_postzl_src_out_stall', + 235: 'DB_PERF_SEL_esr_ps_src_in_sends', + 236: 'DB_PERF_SEL_esr_ps_src_in_stall', + 237: 'DB_PERF_SEL_esr_ps_src_in_squads', + 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 242: 'DB_PERF_SEL_esr_ps_src_out_stall', + 243: 'DB_PERF_SEL_depth_bounds_tile_culled', + 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 246: 'DB_PERF_SEL_flush_compressed', + 247: 'DB_PERF_SEL_flush_plane_le4', + 248: 'DB_PERF_SEL_tiles_z_fully_summarized', + 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', + 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', + 256: 'DB_PERF_SEL_di_dt_stall', + 258: 'DB_PERF_SEL_DB_SC_s_tile_rate', + 259: 'DB_PERF_SEL_DB_SC_c_tile_rate', + 260: 'DB_PERF_SEL_DB_SC_z_tile_rate', + 261: 'DB_PERF_SEL_DB_CB_export_export_quads', + 262: 'DB_PERF_SEL_DB_CB_export_double_format', + 263: 'DB_PERF_SEL_DB_CB_export_fast_format', + 264: 'DB_PERF_SEL_DB_CB_export_slow_format', + 265: 'DB_PERF_SEL_CB_DB_rdreq_sends', + 266: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 267: 'DB_PERF_SEL_CB_DB_wrreq_sends', + 268: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 269: 'DB_PERF_SEL_DB_CB_rdret_ack', + 270: 'DB_PERF_SEL_DB_CB_rdret_nack', + 271: 'DB_PERF_SEL_DB_CB_wrret_ack', + 272: 'DB_PERF_SEL_DB_CB_wrret_nack', + 273: 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', + 274: 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', + 275: 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', + 276: 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', + 277: 'DB_PERF_SEL_unmapped_z_tile_culled', + 278: 'DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_DB_DATA_TS', + 279: 'DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', + 280: 'DB_PERF_SEL_DB_CB_export_is_event_BOTTOM_OF_PIPE_TS', + 281: 'DB_PERF_SEL_DB_CB_export_waiting_for_perfcounter_stop_event', + 282: 'DB_PERF_SEL_DB_CB_export_fmt_32bpp_8pix', + 283: 'DB_PERF_SEL_DB_CB_export_fmt_16_16_unsigned_8pix', + 284: 'DB_PERF_SEL_DB_CB_export_fmt_16_16_signed_8pix', + 285: 'DB_PERF_SEL_DB_CB_export_fmt_16_16_float_8pix', + 286: 'DB_PERF_SEL_DB_CB_export_num_pixels_need_blending', + 287: 'DB_PERF_SEL_DB_CB_context_dones', + 288: 'DB_PERF_SEL_DB_CB_eop_dones', + 289: 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', + 290: 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', + 291: 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', + 292: 'DB_PERF_SEL_SC_DB_tile_backface', + 293: 'DB_PERF_SEL_SC_DB_quad_quads', + 294: 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', + 295: 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', + 296: 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', + 297: 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', + 298: 'DB_PERF_SEL_DB_SC_quad_double_quad', + 299: 'DB_PERF_SEL_SX_DB_quad_export_quads', + 300: 'DB_PERF_SEL_SX_DB_quad_double_format', + 301: 'DB_PERF_SEL_SX_DB_quad_fast_format', + 302: 'DB_PERF_SEL_SX_DB_quad_slow_format', + 303: 'DB_PERF_SEL_quad_rd_sends_unc', + 304: 'DB_PERF_SEL_quad_rd_mi_stall_unc', + 305: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', + 306: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', + 307: 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', + 308: 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', + 309: 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', + 310: 'DB_PERF_SEL_noz_waiting_for_postz_done', + 311: 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x1', + 312: 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x1', + 313: 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x2', + 314: 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x2', + 315: 'DB_PERF_SEL_RMI_rd_tile_32byte_req', + 316: 'DB_PERF_SEL_RMI_rd_z_32byte_req', + 317: 'DB_PERF_SEL_RMI_rd_s_32byte_req', + 318: 'DB_PERF_SEL_RMI_wr_tile_32byte_req', + 319: 'DB_PERF_SEL_RMI_wr_z_32byte_req', + 320: 'DB_PERF_SEL_RMI_wr_s_32byte_req', + 321: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', + 322: 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', + 323: 'DB_PERF_SEL_RMI_rd_z_32byte_ret', + 324: 'DB_PERF_SEL_RMI_rd_s_32byte_ret', + 325: 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', + 326: 'DB_PERF_SEL_RMI_wr_z_32byte_ack', + 327: 'DB_PERF_SEL_RMI_wr_s_32byte_ack', + 328: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', + 329: 'DB_PERF_SEL_esr_vic_sqq_busy', + 330: 'DB_PERF_SEL_esr_vic_sqq_stall', + 331: 'DB_PERF_SEL_esr_psi_vic_tile_rate', + 332: 'DB_PERF_SEL_esr_vic_footprint_match_2x2', + 333: 'DB_PERF_SEL_esr_vic_footprint_match_2x1', + 334: 'DB_PERF_SEL_esr_vic_footprint_match_1x2', + 335: 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', + 336: 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', + 337: 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', + 338: 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', + 339: 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', + 340: 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', + 341: 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', + 342: 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', + 343: 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', + 344: 'DB_PERF_SEL_ts_events_pws_enable', + 345: 'DB_PERF_SEL_ps_events_pws_enable', + 346: 'DB_PERF_SEL_cs_events_pws_enable', + 347: 'DB_PERF_SEL_DB_SC_quad_noz_tiles', + 348: 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', + 349: 'DB_PERF_SEL_DB_SC_quad_conflicts', + 350: 'DB_PERF_SEL_SC_DB_quad_vrs_1x1', + 351: 'DB_PERF_SEL_SC_DB_quad_vrs_1x2', + 352: 'DB_PERF_SEL_SC_DB_quad_vrs_2x1', + 353: 'DB_PERF_SEL_SC_DB_quad_vrs_2x2', + 354: 'DB_PERF_SEL_SC_DB_quad_vrs_2x_ssaa', + 355: 'DB_PERF_SEL_SC_DB_quad_vrs_4x_ssaa', + 356: 'DB_PERF_SEL_SC_DB_quad_vrs_8x_ssaa', + 357: 'DB_PERF_SEL_SC_DB_wave_sends', + 358: 'DB_PERF_SEL_SC_DB_wave_busy', + 359: 'DB_PERF_SEL_SC_DB_wave_quads', + 360: 'DB_PERF_SEL_SC_DB_wave_id_wrapped', + 361: 'DB_PERF_SEL_DB_SC_wave_sends', + 362: 'DB_PERF_SEL_DB_SC_wave_busy', + 363: 'DB_PERF_SEL_DB_SC_wave_stalls', + 364: 'DB_PERF_SEL_DB_SC_wave_conflict', + 365: 'DB_PERF_SEL_DB_SC_wave_hard_conflict', + 366: 'DB_PERF_SEL_DB_SC_wave_id_wrapped', + 367: 'DB_PERF_SEL_SX_DB_quad_waves', + 368: 'DB_PERF_SEL_pws_stall', + 369: 'DB_PERF_SEL_pws_liveness_stall_dtt_tag', + 370: 'DB_PERF_SEL_pws_liveness_stall_tcp_cache_mgr', + 371: 'DB_PERF_SEL_OREO_TT_load', + 372: 'DB_PERF_SEL_OREO_TT_read', + 373: 'DB_PERF_SEL_OREO_TT_stalls', + 374: 'DB_PERF_SEL_OREO_ST_load', + 375: 'DB_PERF_SEL_OREO_ST_read', + 376: 'DB_PERF_SEL_OREO_ST_stalls', + 377: 'DB_PERF_SEL_OREO_WT_load', + 378: 'DB_PERF_SEL_OREO_WT_read', + 379: 'DB_PERF_SEL_OREO_SB_misses', + 380: 'DB_PERF_SEL_OREO_SB_hits', + 381: 'DB_PERF_SEL_OREO_SB_evicts', + 382: 'DB_PERF_SEL_OREO_SB_stalls', + 383: 'DB_PERF_SEL_OREO_Events_load', + 384: 'DB_PERF_SEL_OREO_Events_transition', + 385: 'DB_PERF_SEL_OREO_Events_non_transition', + 386: 'DB_PERF_SEL_OREO_Events_delayed', + 387: 'DB_PERF_SEL_OREO_Events_stalls', +} +DB_PERF_SEL_SC_DB_tile_sends = 0 +DB_PERF_SEL_SC_DB_tile_busy = 1 +DB_PERF_SEL_SC_DB_tile_stalls = 2 +DB_PERF_SEL_SC_DB_tile_events = 3 +DB_PERF_SEL_SC_DB_tile_tiles = 4 +DB_PERF_SEL_SC_DB_tile_covered = 5 +DB_PERF_SEL_hiz_tc_read_starved = 6 +DB_PERF_SEL_hiz_tc_write_stall = 7 +DB_PERF_SEL_hiz_tile_culled = 8 +DB_PERF_SEL_his_tile_culled = 9 +DB_PERF_SEL_DB_SC_tile_sends = 10 +DB_PERF_SEL_DB_SC_tile_busy = 11 +DB_PERF_SEL_DB_SC_tile_stalls = 12 +DB_PERF_SEL_DB_SC_tile_df_stalls = 13 +DB_PERF_SEL_DB_SC_tile_tiles = 14 +DB_PERF_SEL_DB_SC_tile_culled = 15 +DB_PERF_SEL_DB_SC_tile_hier_kill = 16 +DB_PERF_SEL_DB_SC_tile_fast_ops = 17 +DB_PERF_SEL_DB_SC_tile_no_ops = 18 +DB_PERF_SEL_DB_SC_tile_tile_rate = 19 +DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 +DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 +DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 +DB_PERF_SEL_SC_DB_quad_sends = 23 +DB_PERF_SEL_SC_DB_quad_busy = 24 +DB_PERF_SEL_SC_DB_quad_squads = 25 +DB_PERF_SEL_SC_DB_quad_tiles = 26 +DB_PERF_SEL_SC_DB_quad_pixels = 27 +DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 +DB_PERF_SEL_DB_SC_quad_sends = 29 +DB_PERF_SEL_DB_SC_quad_busy = 30 +DB_PERF_SEL_DB_SC_quad_stalls = 31 +DB_PERF_SEL_DB_SC_quad_tiles = 32 +DB_PERF_SEL_DB_SC_quad_lit_quad = 33 +DB_PERF_SEL_DB_CB_export_events = 34 +DB_PERF_SEL_SX_DB_quad_sends = 37 +DB_PERF_SEL_SX_DB_quad_busy = 38 +DB_PERF_SEL_SX_DB_quad_stalls = 39 +DB_PERF_SEL_SX_DB_quad_quads = 40 +DB_PERF_SEL_SX_DB_quad_pixels = 41 +DB_PERF_SEL_SX_DB_quad_exports = 42 +DB_PERF_SEL_SH_quads_outstanding_sum = 43 +DB_PERF_SEL_DB_CB_export_sends = 44 +DB_PERF_SEL_DB_CB_export_busy = 45 +DB_PERF_SEL_DB_CB_export_stalls = 46 +DB_PERF_SEL_DB_CB_export_quads = 47 +DB_PERF_SEL_tile_rd_sends = 48 +DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 +DB_PERF_SEL_quad_rd_sends = 50 +DB_PERF_SEL_quad_rd_busy = 51 +DB_PERF_SEL_quad_rd_mi_stall = 52 +DB_PERF_SEL_quad_rd_rw_collision = 53 +DB_PERF_SEL_quad_rd_tag_stall = 54 +DB_PERF_SEL_quad_rd_32byte_reqs = 55 +DB_PERF_SEL_quad_rd_panic = 56 +DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 +DB_PERF_SEL_quad_rdret_sends = 58 +DB_PERF_SEL_quad_rdret_busy = 59 +DB_PERF_SEL_tile_wr_sends = 60 +DB_PERF_SEL_tile_wr_acks = 61 +DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 +DB_PERF_SEL_quad_wr_sends = 63 +DB_PERF_SEL_quad_wr_busy = 64 +DB_PERF_SEL_quad_wr_mi_stall = 65 +DB_PERF_SEL_quad_wr_coherency_stall = 66 +DB_PERF_SEL_quad_wr_acks = 67 +DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 +DB_PERF_SEL_Tile_Cache_misses = 69 +DB_PERF_SEL_Tile_Cache_hits = 70 +DB_PERF_SEL_Tile_Cache_flushes = 71 +DB_PERF_SEL_Tile_Cache_surface_stall = 72 +DB_PERF_SEL_Tile_Cache_starves = 73 +DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 +DB_PERF_SEL_tcp_dispatcher_reads = 75 +DB_PERF_SEL_tcp_prefetcher_reads = 76 +DB_PERF_SEL_tcp_preloader_reads = 77 +DB_PERF_SEL_tcp_dispatcher_flushes = 78 +DB_PERF_SEL_tcp_prefetcher_flushes = 79 +DB_PERF_SEL_tcp_preloader_flushes = 80 +DB_PERF_SEL_Depth_Tile_Cache_sends = 81 +DB_PERF_SEL_Depth_Tile_Cache_busy = 82 +DB_PERF_SEL_Depth_Tile_Cache_starves = 83 +DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 +DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 +DB_PERF_SEL_Depth_Tile_Cache_misses = 86 +DB_PERF_SEL_Depth_Tile_Cache_hits = 87 +DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 +DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 +DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 +DB_PERF_SEL_Depth_Tile_Cache_event = 91 +DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 +DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 +DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 +DB_PERF_SEL_Stencil_Cache_misses = 95 +DB_PERF_SEL_Stencil_Cache_hits = 96 +DB_PERF_SEL_Stencil_Cache_flushes = 97 +DB_PERF_SEL_Stencil_Cache_starves = 98 +DB_PERF_SEL_Stencil_Cache_frees = 99 +DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 +DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 +DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 +DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 +DB_PERF_SEL_Z_Cache_pmask_misses = 104 +DB_PERF_SEL_Z_Cache_pmask_hits = 105 +DB_PERF_SEL_Z_Cache_pmask_flushes = 106 +DB_PERF_SEL_Z_Cache_pmask_starves = 107 +DB_PERF_SEL_Z_Cache_frees = 108 +DB_PERF_SEL_Plane_Cache_misses = 109 +DB_PERF_SEL_Plane_Cache_hits = 110 +DB_PERF_SEL_Plane_Cache_flushes = 111 +DB_PERF_SEL_Plane_Cache_starves = 112 +DB_PERF_SEL_Plane_Cache_frees = 113 +DB_PERF_SEL_flush_expanded_stencil = 114 +DB_PERF_SEL_flush_compressed_stencil = 115 +DB_PERF_SEL_flush_single_stencil = 116 +DB_PERF_SEL_planes_flushed = 117 +DB_PERF_SEL_flush_1plane = 118 +DB_PERF_SEL_flush_2plane = 119 +DB_PERF_SEL_flush_3plane = 120 +DB_PERF_SEL_flush_4plane = 121 +DB_PERF_SEL_flush_5plane = 122 +DB_PERF_SEL_flush_6plane = 123 +DB_PERF_SEL_flush_7plane = 124 +DB_PERF_SEL_flush_8plane = 125 +DB_PERF_SEL_flush_9plane = 126 +DB_PERF_SEL_flush_10plane = 127 +DB_PERF_SEL_flush_11plane = 128 +DB_PERF_SEL_flush_12plane = 129 +DB_PERF_SEL_flush_13plane = 130 +DB_PERF_SEL_flush_14plane = 131 +DB_PERF_SEL_flush_15plane = 132 +DB_PERF_SEL_flush_16plane = 133 +DB_PERF_SEL_flush_expanded_z = 134 +DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 +DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 +DB_PERF_SEL_dk_tile_sends = 137 +DB_PERF_SEL_dk_tile_busy = 138 +DB_PERF_SEL_dk_tile_quad_starves = 139 +DB_PERF_SEL_dk_tile_stalls = 140 +DB_PERF_SEL_dk_squad_sends = 141 +DB_PERF_SEL_dk_squad_busy = 142 +DB_PERF_SEL_dk_squad_stalls = 143 +DB_PERF_SEL_Op_Pipe_Busy = 144 +DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 +DB_PERF_SEL_qc_busy = 146 +DB_PERF_SEL_qc_xfc = 147 +DB_PERF_SEL_qc_conflicts = 148 +DB_PERF_SEL_qc_full_stall = 149 +DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 +DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 +DB_PERF_SEL_tsc_insert_summarize_stall = 152 +DB_PERF_SEL_tl_busy = 153 +DB_PERF_SEL_tl_dtc_read_starved = 154 +DB_PERF_SEL_tl_z_fetch_stall = 155 +DB_PERF_SEL_tl_stencil_stall = 156 +DB_PERF_SEL_tl_z_decompress_stall = 157 +DB_PERF_SEL_tl_stencil_locked_stall = 158 +DB_PERF_SEL_tl_events = 159 +DB_PERF_SEL_tl_summarize_squads = 160 +DB_PERF_SEL_tl_flush_expand_squads = 161 +DB_PERF_SEL_tl_expand_squads = 162 +DB_PERF_SEL_tl_preZ_squads = 163 +DB_PERF_SEL_tl_postZ_squads = 164 +DB_PERF_SEL_tl_preZ_noop_squads = 165 +DB_PERF_SEL_tl_postZ_noop_squads = 166 +DB_PERF_SEL_tl_tile_ops = 167 +DB_PERF_SEL_tl_in_xfc = 168 +DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 +DB_PERF_SEL_tl_in_fast_z_stall = 170 +DB_PERF_SEL_tl_out_xfc = 171 +DB_PERF_SEL_tl_out_squads = 172 +DB_PERF_SEL_zf_plane_multicycle = 173 +DB_PERF_SEL_PostZ_Samples_passing_Z = 174 +DB_PERF_SEL_PostZ_Samples_failing_Z = 175 +DB_PERF_SEL_PostZ_Samples_failing_S = 176 +DB_PERF_SEL_PreZ_Samples_passing_Z = 177 +DB_PERF_SEL_PreZ_Samples_failing_Z = 178 +DB_PERF_SEL_PreZ_Samples_failing_S = 179 +DB_PERF_SEL_ts_tc_update_stall = 180 +DB_PERF_SEL_sc_kick_start = 181 +DB_PERF_SEL_sc_kick_end = 182 +DB_PERF_SEL_clock_reg_active = 183 +DB_PERF_SEL_clock_main_active = 184 +DB_PERF_SEL_clock_mem_export_active = 185 +DB_PERF_SEL_esr_ps_out_busy = 186 +DB_PERF_SEL_esr_ps_lqf_busy = 187 +DB_PERF_SEL_esr_ps_lqf_stall = 188 +DB_PERF_SEL_etr_out_send = 189 +DB_PERF_SEL_etr_out_busy = 190 +DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 +DB_PERF_SEL_etr_out_esr_stall = 193 +DB_PERF_SEL_esr_ps_vic_busy = 194 +DB_PERF_SEL_esr_ps_vic_stall = 195 +DB_PERF_SEL_esr_eot_fwd_busy = 196 +DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 +DB_PERF_SEL_esr_eot_fwd_forward = 198 +DB_PERF_SEL_esr_sqq_zi_busy = 199 +DB_PERF_SEL_esr_sqq_zi_stall = 200 +DB_PERF_SEL_postzl_sq_pt_busy = 201 +DB_PERF_SEL_postzl_sq_pt_stall = 202 +DB_PERF_SEL_postzl_se_busy = 203 +DB_PERF_SEL_postzl_se_stall = 204 +DB_PERF_SEL_postzl_partial_launch = 205 +DB_PERF_SEL_postzl_full_launch = 206 +DB_PERF_SEL_postzl_partial_waiting = 207 +DB_PERF_SEL_postzl_tile_mem_stall = 208 +DB_PERF_SEL_postzl_tile_init_stall = 209 +DB_PERF_SEL_prezl_tile_mem_stall = 210 +DB_PERF_SEL_prezl_tile_init_stall = 211 +DB_PERF_SEL_dtt_sm_clash_stall = 212 +DB_PERF_SEL_dtt_sm_slot_stall = 213 +DB_PERF_SEL_dtt_sm_miss_stall = 214 +DB_PERF_SEL_mi_rdreq_busy = 215 +DB_PERF_SEL_mi_rdreq_stall = 216 +DB_PERF_SEL_mi_wrreq_busy = 217 +DB_PERF_SEL_mi_wrreq_stall = 218 +DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 +DB_PERF_SEL_dkg_tile_rate_tile = 220 +DB_PERF_SEL_prezl_src_in_sends = 221 +DB_PERF_SEL_prezl_src_in_stall = 222 +DB_PERF_SEL_prezl_src_in_squads = 223 +DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 +DB_PERF_SEL_prezl_src_in_tile_rate = 225 +DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 +DB_PERF_SEL_prezl_src_out_stall = 227 +DB_PERF_SEL_postzl_src_in_sends = 228 +DB_PERF_SEL_postzl_src_in_stall = 229 +DB_PERF_SEL_postzl_src_in_squads = 230 +DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 +DB_PERF_SEL_postzl_src_in_tile_rate = 232 +DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 +DB_PERF_SEL_postzl_src_out_stall = 234 +DB_PERF_SEL_esr_ps_src_in_sends = 235 +DB_PERF_SEL_esr_ps_src_in_stall = 236 +DB_PERF_SEL_esr_ps_src_in_squads = 237 +DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 +DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 +DB_PERF_SEL_esr_ps_src_out_stall = 242 +DB_PERF_SEL_depth_bounds_tile_culled = 243 +DB_PERF_SEL_PreZ_Samples_failing_DB = 244 +DB_PERF_SEL_PostZ_Samples_failing_DB = 245 +DB_PERF_SEL_flush_compressed = 246 +DB_PERF_SEL_flush_plane_le4 = 247 +DB_PERF_SEL_tiles_z_fully_summarized = 248 +DB_PERF_SEL_tiles_stencil_fully_summarized = 249 +DB_PERF_SEL_tiles_z_clear_on_expclear = 250 +DB_PERF_SEL_tiles_s_clear_on_expclear = 251 +DB_PERF_SEL_tiles_decomp_on_expclear = 252 +DB_PERF_SEL_tiles_compressed_to_decompressed = 253 +DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 +DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 +DB_PERF_SEL_di_dt_stall = 256 +DB_PERF_SEL_DB_SC_s_tile_rate = 258 +DB_PERF_SEL_DB_SC_c_tile_rate = 259 +DB_PERF_SEL_DB_SC_z_tile_rate = 260 +DB_PERF_SEL_DB_CB_export_export_quads = 261 +DB_PERF_SEL_DB_CB_export_double_format = 262 +DB_PERF_SEL_DB_CB_export_fast_format = 263 +DB_PERF_SEL_DB_CB_export_slow_format = 264 +DB_PERF_SEL_CB_DB_rdreq_sends = 265 +DB_PERF_SEL_CB_DB_rdreq_prt_sends = 266 +DB_PERF_SEL_CB_DB_wrreq_sends = 267 +DB_PERF_SEL_CB_DB_wrreq_prt_sends = 268 +DB_PERF_SEL_DB_CB_rdret_ack = 269 +DB_PERF_SEL_DB_CB_rdret_nack = 270 +DB_PERF_SEL_DB_CB_wrret_ack = 271 +DB_PERF_SEL_DB_CB_wrret_nack = 272 +DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 273 +DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 274 +DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 275 +DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 276 +DB_PERF_SEL_unmapped_z_tile_culled = 277 +DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_DB_DATA_TS = 278 +DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 279 +DB_PERF_SEL_DB_CB_export_is_event_BOTTOM_OF_PIPE_TS = 280 +DB_PERF_SEL_DB_CB_export_waiting_for_perfcounter_stop_event = 281 +DB_PERF_SEL_DB_CB_export_fmt_32bpp_8pix = 282 +DB_PERF_SEL_DB_CB_export_fmt_16_16_unsigned_8pix = 283 +DB_PERF_SEL_DB_CB_export_fmt_16_16_signed_8pix = 284 +DB_PERF_SEL_DB_CB_export_fmt_16_16_float_8pix = 285 +DB_PERF_SEL_DB_CB_export_num_pixels_need_blending = 286 +DB_PERF_SEL_DB_CB_context_dones = 287 +DB_PERF_SEL_DB_CB_eop_dones = 288 +DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 289 +DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 290 +DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 291 +DB_PERF_SEL_SC_DB_tile_backface = 292 +DB_PERF_SEL_SC_DB_quad_quads = 293 +DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 294 +DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 295 +DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 296 +DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 297 +DB_PERF_SEL_DB_SC_quad_double_quad = 298 +DB_PERF_SEL_SX_DB_quad_export_quads = 299 +DB_PERF_SEL_SX_DB_quad_double_format = 300 +DB_PERF_SEL_SX_DB_quad_fast_format = 301 +DB_PERF_SEL_SX_DB_quad_slow_format = 302 +DB_PERF_SEL_quad_rd_sends_unc = 303 +DB_PERF_SEL_quad_rd_mi_stall_unc = 304 +DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 305 +DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 306 +DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 307 +DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 308 +DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 309 +DB_PERF_SEL_noz_waiting_for_postz_done = 310 +DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x1 = 311 +DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x1 = 312 +DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x2 = 313 +DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x2 = 314 +DB_PERF_SEL_RMI_rd_tile_32byte_req = 315 +DB_PERF_SEL_RMI_rd_z_32byte_req = 316 +DB_PERF_SEL_RMI_rd_s_32byte_req = 317 +DB_PERF_SEL_RMI_wr_tile_32byte_req = 318 +DB_PERF_SEL_RMI_wr_z_32byte_req = 319 +DB_PERF_SEL_RMI_wr_s_32byte_req = 320 +DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 321 +DB_PERF_SEL_RMI_rd_tile_32byte_ret = 322 +DB_PERF_SEL_RMI_rd_z_32byte_ret = 323 +DB_PERF_SEL_RMI_rd_s_32byte_ret = 324 +DB_PERF_SEL_RMI_wr_tile_32byte_ack = 325 +DB_PERF_SEL_RMI_wr_z_32byte_ack = 326 +DB_PERF_SEL_RMI_wr_s_32byte_ack = 327 +DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 328 +DB_PERF_SEL_esr_vic_sqq_busy = 329 +DB_PERF_SEL_esr_vic_sqq_stall = 330 +DB_PERF_SEL_esr_psi_vic_tile_rate = 331 +DB_PERF_SEL_esr_vic_footprint_match_2x2 = 332 +DB_PERF_SEL_esr_vic_footprint_match_2x1 = 333 +DB_PERF_SEL_esr_vic_footprint_match_1x2 = 334 +DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 335 +DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 336 +DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 337 +DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 338 +DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 339 +DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 340 +DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 341 +DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 342 +DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 343 +DB_PERF_SEL_ts_events_pws_enable = 344 +DB_PERF_SEL_ps_events_pws_enable = 345 +DB_PERF_SEL_cs_events_pws_enable = 346 +DB_PERF_SEL_DB_SC_quad_noz_tiles = 347 +DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 348 +DB_PERF_SEL_DB_SC_quad_conflicts = 349 +DB_PERF_SEL_SC_DB_quad_vrs_1x1 = 350 +DB_PERF_SEL_SC_DB_quad_vrs_1x2 = 351 +DB_PERF_SEL_SC_DB_quad_vrs_2x1 = 352 +DB_PERF_SEL_SC_DB_quad_vrs_2x2 = 353 +DB_PERF_SEL_SC_DB_quad_vrs_2x_ssaa = 354 +DB_PERF_SEL_SC_DB_quad_vrs_4x_ssaa = 355 +DB_PERF_SEL_SC_DB_quad_vrs_8x_ssaa = 356 +DB_PERF_SEL_SC_DB_wave_sends = 357 +DB_PERF_SEL_SC_DB_wave_busy = 358 +DB_PERF_SEL_SC_DB_wave_quads = 359 +DB_PERF_SEL_SC_DB_wave_id_wrapped = 360 +DB_PERF_SEL_DB_SC_wave_sends = 361 +DB_PERF_SEL_DB_SC_wave_busy = 362 +DB_PERF_SEL_DB_SC_wave_stalls = 363 +DB_PERF_SEL_DB_SC_wave_conflict = 364 +DB_PERF_SEL_DB_SC_wave_hard_conflict = 365 +DB_PERF_SEL_DB_SC_wave_id_wrapped = 366 +DB_PERF_SEL_SX_DB_quad_waves = 367 +DB_PERF_SEL_pws_stall = 368 +DB_PERF_SEL_pws_liveness_stall_dtt_tag = 369 +DB_PERF_SEL_pws_liveness_stall_tcp_cache_mgr = 370 +DB_PERF_SEL_OREO_TT_load = 371 +DB_PERF_SEL_OREO_TT_read = 372 +DB_PERF_SEL_OREO_TT_stalls = 373 +DB_PERF_SEL_OREO_ST_load = 374 +DB_PERF_SEL_OREO_ST_read = 375 +DB_PERF_SEL_OREO_ST_stalls = 376 +DB_PERF_SEL_OREO_WT_load = 377 +DB_PERF_SEL_OREO_WT_read = 378 +DB_PERF_SEL_OREO_SB_misses = 379 +DB_PERF_SEL_OREO_SB_hits = 380 +DB_PERF_SEL_OREO_SB_evicts = 381 +DB_PERF_SEL_OREO_SB_stalls = 382 +DB_PERF_SEL_OREO_Events_load = 383 +DB_PERF_SEL_OREO_Events_transition = 384 +DB_PERF_SEL_OREO_Events_non_transition = 385 +DB_PERF_SEL_OREO_Events_delayed = 386 +DB_PERF_SEL_OREO_Events_stalls = 387 +PerfCounter_Vals = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeCounterId' +PixelPipeCounterId__enumvalues = { + 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', + 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', + 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', + 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', + 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', + 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', +} +PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 +PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 +PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 +PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 +PixelPipeCounterId = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeStride' +PixelPipeStride__enumvalues = { + 0: 'PIXEL_PIPE_STRIDE_32_BITS', + 1: 'PIXEL_PIPE_STRIDE_64_BITS', + 2: 'PIXEL_PIPE_STRIDE_128_BITS', + 3: 'PIXEL_PIPE_STRIDE_256_BITS', +} +PIXEL_PIPE_STRIDE_32_BITS = 0 +PIXEL_PIPE_STRIDE_64_BITS = 1 +PIXEL_PIPE_STRIDE_128_BITS = 2 +PIXEL_PIPE_STRIDE_256_BITS = 3 +PixelPipeStride = ctypes.c_uint32 # enum + +# values for enumeration 'RingCounterControl' +RingCounterControl__enumvalues = { + 0: 'COUNTER_RING_SPLIT', + 1: 'COUNTER_RING_0', + 2: 'COUNTER_RING_1', +} +COUNTER_RING_SPLIT = 0 +COUNTER_RING_0 = 1 +COUNTER_RING_1 = 2 +RingCounterControl = ctypes.c_uint32 # enum + +# values for enumeration 'StencilOp' +StencilOp__enumvalues = { + 0: 'STENCIL_KEEP', + 1: 'STENCIL_ZERO', + 2: 'STENCIL_ONES', + 3: 'STENCIL_REPLACE_TEST', + 4: 'STENCIL_REPLACE_OP', + 5: 'STENCIL_ADD_CLAMP', + 6: 'STENCIL_SUB_CLAMP', + 7: 'STENCIL_INVERT', + 8: 'STENCIL_ADD_WRAP', + 9: 'STENCIL_SUB_WRAP', + 10: 'STENCIL_AND', + 11: 'STENCIL_OR', + 12: 'STENCIL_XOR', + 13: 'STENCIL_NAND', + 14: 'STENCIL_NOR', + 15: 'STENCIL_XNOR', +} +STENCIL_KEEP = 0 +STENCIL_ZERO = 1 +STENCIL_ONES = 2 +STENCIL_REPLACE_TEST = 3 +STENCIL_REPLACE_OP = 4 +STENCIL_ADD_CLAMP = 5 +STENCIL_SUB_CLAMP = 6 +STENCIL_INVERT = 7 +STENCIL_ADD_WRAP = 8 +STENCIL_SUB_WRAP = 9 +STENCIL_AND = 10 +STENCIL_OR = 11 +STENCIL_XOR = 12 +STENCIL_NAND = 13 +STENCIL_NOR = 14 +STENCIL_XNOR = 15 +StencilOp = ctypes.c_uint32 # enum + +# values for enumeration 'ZLimitSumm' +ZLimitSumm__enumvalues = { + 0: 'FORCE_SUMM_OFF', + 1: 'FORCE_SUMM_MINZ', + 2: 'FORCE_SUMM_MAXZ', + 3: 'FORCE_SUMM_BOTH', +} +FORCE_SUMM_OFF = 0 +FORCE_SUMM_MINZ = 1 +FORCE_SUMM_MAXZ = 2 +FORCE_SUMM_BOTH = 3 +ZLimitSumm = ctypes.c_uint32 # enum + +# values for enumeration 'ZModeForce' +ZModeForce__enumvalues = { + 0: 'NO_FORCE', + 1: 'FORCE_EARLY_Z', + 2: 'FORCE_LATE_Z', + 3: 'FORCE_RE_Z', +} +NO_FORCE = 0 +FORCE_EARLY_Z = 1 +FORCE_LATE_Z = 2 +FORCE_RE_Z = 3 +ZModeForce = ctypes.c_uint32 # enum + +# values for enumeration 'ZOrder' +ZOrder__enumvalues = { + 0: 'LATE_Z', + 1: 'EARLY_Z_THEN_LATE_Z', + 2: 'RE_Z', + 3: 'EARLY_Z_THEN_RE_Z', +} +LATE_Z = 0 +EARLY_Z_THEN_LATE_Z = 1 +RE_Z = 2 +EARLY_Z_THEN_RE_Z = 3 +ZOrder = ctypes.c_uint32 # enum + +# values for enumeration 'ZSamplePosition' +ZSamplePosition__enumvalues = { + 0: 'Z_SAMPLE_CENTER', + 1: 'Z_SAMPLE_CENTROID', +} +Z_SAMPLE_CENTER = 0 +Z_SAMPLE_CENTROID = 1 +ZSamplePosition = ctypes.c_uint32 # enum + +# values for enumeration 'SU_PERFCNT_SEL' +SU_PERFCNT_SEL__enumvalues = { + 0: 'PERF_PAPC_PASX_REQ', + 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 8: 'PERF_CLPR_INPUT_PRIM', + 9: 'PERF_CLPR_INPUT_NULL_PRIM', + 10: 'PERF_CLPR_INPUT_EVENT', + 11: 'PERF_CLPR_INPUT_FIRST_OF_SUBGROUP', + 12: 'PERF_CLPR_INPUT_END_OF_PACKET', + 13: 'PERF_CLPR_INPUT_EXTENDED_EVENT', + 14: 'PERF_PAPC_CLPR_CULL_PRIM', + 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', + 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', + 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', + 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 30: 'PERF_CLPR_CLIP_PLANE_CNT_9_PLUS', + 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', + 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', + 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 39: 'PERF_PAPC_CLSM_NULL_PRIM', + 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', + 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', + 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', + 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_PLUS', + 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', + 49: 'PERF_PAPC_SU_INPUT_PRIM', + 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', + 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 61: 'PERF_PAPC_SU_OUTPUT_PRIM', + 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', + 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', + 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 77: 'PERF_PAPC_PASX_REQ_IDLE', + 78: 'PERF_PAPC_PASX_REQ_BUSY', + 79: 'PERF_PAPC_PASX_REQ_STALLED', + 80: 'PERF_PAPC_PASX_REC_IDLE', + 81: 'PERF_PAPC_PASX_REC_BUSY', + 82: 'PERF_PAPC_PASX_REC_STARVED_SX', + 83: 'PERF_PAPC_PASX_REC_STALLED', + 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 86: 'PERF_PAPC_CCGSM_IDLE', + 87: 'PERF_PAPC_CCGSM_BUSY', + 88: 'PERF_PAPC_CCGSM_STALLED', + 89: 'PERF_PAPC_CLPRIM_IDLE', + 90: 'PERF_PAPC_CLPRIM_BUSY', + 91: 'PERF_PAPC_CLPRIM_STALLED', + 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 93: 'PERF_PAPC_CLIPSM_IDLE', + 94: 'PERF_PAPC_CLIPSM_BUSY', + 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', + 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 100: 'PERF_PAPC_CLIPGA_IDLE', + 101: 'PERF_PAPC_CLIPGA_BUSY', + 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 103: 'PERF_PAPC_CLIPGA_STALLED', + 104: 'PERF_PAPC_CLIP_IDLE', + 105: 'PERF_PAPC_CLIP_BUSY', + 106: 'PERF_PAPC_SU_IDLE', + 107: 'PERF_PAPC_SU_BUSY', + 108: 'PERF_PAPC_SU_STARVED_CLIP', + 109: 'PERF_PAPC_SU_STALLED_SC', + 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', + 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', + 112: 'PERF_PAPC_PA_REG_SCLK_VLD', + 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 125: 'PERF_PAPC_SU_ALL_OUTPUT_PRIM', + 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 128: 'PERF_PAPC_SU_ALL_OUTPUT_NULL_PRIM', + 131: 'PERF_PAPC_SU_SE0_STALLED_SC', + 132: 'PERF_PAPC_SU_SE1_STALLED_SC', + 133: 'PERF_PAPC_SU_ALL_STALLED_SC', + 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 135: 'PERF_PAPC_SU_CULLED_PRIM', + 136: 'PERF_PAPC_SU_OUTPUT_EOPG', + 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 151: 'PERF_PAPC_SU_SE2_STALLED_SC', + 152: 'PERF_PAPC_SU_SE3_STALLED_SC', + 153: 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', + 154: 'PERF_SMALL_PRIM_CULL_PRIM_1X1', + 155: 'PERF_SMALL_PRIM_CULL_PRIM_2X1', + 156: 'PERF_SMALL_PRIM_CULL_PRIM_1X2', + 157: 'PERF_SMALL_PRIM_CULL_PRIM_2X2', + 158: 'PERF_SMALL_PRIM_CULL_PRIM_3X1', + 159: 'PERF_SMALL_PRIM_CULL_PRIM_1X3', + 160: 'PERF_SMALL_PRIM_CULL_PRIM_3X2', + 161: 'PERF_SMALL_PRIM_CULL_PRIM_2X3', + 162: 'PERF_SMALL_PRIM_CULL_PRIM_NX1', + 163: 'PERF_SMALL_PRIM_CULL_PRIM_1XN', + 164: 'PERF_SMALL_PRIM_CULL_PRIM_NX2', + 165: 'PERF_SMALL_PRIM_CULL_PRIM_2XN', + 169: 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', + 170: 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', + 171: 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', + 172: 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', + 173: 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', + 174: 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', + 175: 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', + 176: 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', + 177: 'PERF_PA_VERTEX_FIFO_FULL', + 178: 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', + 179: 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', + 183: 'PERF_ENGG_CSB_MACHINE_IS_STARVED', + 184: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', + 185: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', + 186: 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', + 188: 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', + 189: 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', + 190: 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', + 191: 'PERF_ENGG_CSB_NULL_SUBGROUP', + 192: 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', + 193: 'PERF_ENGG_CSB_GE_MEMORY_FULL', + 194: 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', + 195: 'PERF_ENGG_CSB_SPI_MEMORY_FULL', + 196: 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', + 224: 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', + 225: 'PERF_ENGG_INDEX_RET_0_NEW_VERTS_THIS_PRIM', + 226: 'PERF_ENGG_INDEX_RET_1_NEW_VERTS_THIS_PRIM', + 227: 'PERF_ENGG_INDEX_RET_2_NEW_VERTS_THIS_PRIM', + 228: 'PERF_ENGG_INDEX_RET_3_NEW_VERTS_THIS_PRIM', + 229: 'PERF_ENGG_INDEX_REQ_STARVED', + 230: 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 231: 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 232: 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', + 233: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', + 234: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', + 235: 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', + 236: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', + 237: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', + 238: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', + 239: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', + 240: 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', + 241: 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', + 242: 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', + 243: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', + 244: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', + 245: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', + 246: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', + 247: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', + 248: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', + 249: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', + 250: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', + 251: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', + 252: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', + 258: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', + 259: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', + 260: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', + 261: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', + 262: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', + 263: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', + 264: 'PERF_ENGG_POS_REQ_STARVED', + 265: 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', + 266: 'PERF_ENGG_BUSY', + 267: 'PERF_CLIPSM_CULL_PRIMS_CNT', + 268: 'PERF_PH_SEND_1_SC', + 269: 'PERF_PH_SEND_2_SC', + 270: 'PERF_PH_SEND_3_SC', + 271: 'PERF_PH_SEND_4_SC', + 272: 'PERF_OUTPUT_PRIM_1_SC', + 273: 'PERF_OUTPUT_PRIM_2_SC', + 274: 'PERF_OUTPUT_PRIM_3_SC', + 275: 'PERF_OUTPUT_PRIM_4_SC', + 276: 'PERF_PASX_POS_VECTOR', + 277: 'PERF_PASX_MISC_VECTOR', + 278: 'PERF_PASX_CCDIST0_VECTOR', + 279: 'PERF_PASX_CCDIST1_VECTOR', + 280: 'PERF_PASX_STEREO_POS_VECTOR', + 281: 'PERF_CLPR_INPUT_SEND', + 282: 'PERF_SU_INPUT_SEND', + 283: 'PERF_SU_OUTPUT_SEND', + 284: 'PERF_PAPC_SU_SE4_PRIM_FILTER_CULL', + 285: 'PERF_PAPC_SU_SE5_PRIM_FILTER_CULL', + 286: 'PERF_PAPC_SU_SE4_OUTPUT_PRIM', + 287: 'PERF_PAPC_SU_SE5_OUTPUT_PRIM', + 288: 'PERF_PAPC_SU_SE4_OUTPUT_NULL_PRIM', + 289: 'PERF_PAPC_SU_SE5_OUTPUT_NULL_PRIM', + 290: 'PERF_PAPC_SU_SE4_STALLED_SC', + 291: 'PERF_PAPC_SU_SE5_STALLED_SC', + 292: 'PERF_ENGG_INDEX_RET0_NEW_VERTS', + 293: 'PERF_ENGG_INDEX_RET1_NEW_VERTS', + 294: 'PERF_ENGG_INDEX_RET2_NEW_VERTS', + 295: 'PERF_ENGG_INDEX_RET3_NEW_VERTS', + 296: 'PERF_ENGG_INDEX_RET4_NEW_VERTS', + 297: 'PERF_ENGG_INDEX_RET5_NEW_VERTS', + 298: 'PERF_ENGG_INDEX_RET6_NEW_VERTS', + 299: 'PERF_ENGG_INDEX_RET7_NEW_VERTS', + 300: 'PERF_ENGG_INDEX_RET8_NEW_VERTS', + 301: 'PERF_ENGG_INDEX_RET9_NEW_VERTS', + 302: 'PERF_ENGG_INDEX_RET10_NEW_VERTS', + 303: 'PERF_ENGG_INDEX_RET11_NEW_VERTS', + 304: 'PERF_ENGG_INDEX_RET12_NEW_VERTS', + 305: 'PERF_PH_SEND_5_SC', + 306: 'PERF_PH_SEND_6_SC', + 307: 'PERF_OUTPUT_PRIM_5_SC', + 308: 'PERF_OUTPUT_PRIM_6_SC', + 309: 'PERF_CLPR_BACK_PRIM', + 310: 'PERF_PA_BUSY', +} +PERF_PAPC_PASX_REQ = 0 +PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 +PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 +PERF_CLPR_INPUT_PRIM = 8 +PERF_CLPR_INPUT_NULL_PRIM = 9 +PERF_CLPR_INPUT_EVENT = 10 +PERF_CLPR_INPUT_FIRST_OF_SUBGROUP = 11 +PERF_CLPR_INPUT_END_OF_PACKET = 12 +PERF_CLPR_INPUT_EXTENDED_EVENT = 13 +PERF_PAPC_CLPR_CULL_PRIM = 14 +PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 +PERF_PAPC_CLPR_VV_CULL_PRIM = 16 +PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 +PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 +PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 +PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 +PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 +PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 +PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 +PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 +PERF_CLPR_CLIP_PLANE_CNT_9_PLUS = 30 +PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 +PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 +PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 +PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 +PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 +PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 +PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 +PERF_PAPC_CLSM_NULL_PRIM = 39 +PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 +PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 +PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 +PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 +PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 +PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 +PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 +PERF_PAPC_CLSM_OUT_PRIM_CNT_9_PLUS = 47 +PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 +PERF_PAPC_SU_INPUT_PRIM = 49 +PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 +PERF_PAPC_SU_INPUT_NULL_PRIM = 51 +PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 +PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 +PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 +PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 +PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 +PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 +PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 +PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 +PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 +PERF_PAPC_SU_OUTPUT_PRIM = 61 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 +PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 +PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 +PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 +PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 +PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 +PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 +PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 +PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 +PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 +PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 +PERF_PAPC_PASX_REQ_IDLE = 77 +PERF_PAPC_PASX_REQ_BUSY = 78 +PERF_PAPC_PASX_REQ_STALLED = 79 +PERF_PAPC_PASX_REC_IDLE = 80 +PERF_PAPC_PASX_REC_BUSY = 81 +PERF_PAPC_PASX_REC_STARVED_SX = 82 +PERF_PAPC_PASX_REC_STALLED = 83 +PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 +PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 +PERF_PAPC_CCGSM_IDLE = 86 +PERF_PAPC_CCGSM_BUSY = 87 +PERF_PAPC_CCGSM_STALLED = 88 +PERF_PAPC_CLPRIM_IDLE = 89 +PERF_PAPC_CLPRIM_BUSY = 90 +PERF_PAPC_CLPRIM_STALLED = 91 +PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 +PERF_PAPC_CLIPSM_IDLE = 93 +PERF_PAPC_CLIPSM_BUSY = 94 +PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 +PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 +PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 +PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 +PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 +PERF_PAPC_CLIPGA_IDLE = 100 +PERF_PAPC_CLIPGA_BUSY = 101 +PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 +PERF_PAPC_CLIPGA_STALLED = 103 +PERF_PAPC_CLIP_IDLE = 104 +PERF_PAPC_CLIP_BUSY = 105 +PERF_PAPC_SU_IDLE = 106 +PERF_PAPC_SU_BUSY = 107 +PERF_PAPC_SU_STARVED_CLIP = 108 +PERF_PAPC_SU_STALLED_SC = 109 +PERF_PAPC_CL_DYN_SCLK_VLD = 110 +PERF_PAPC_SU_DYN_SCLK_VLD = 111 +PERF_PAPC_PA_REG_SCLK_VLD = 112 +PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 +PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 +PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 +PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 +PERF_PAPC_SU_ALL_OUTPUT_PRIM = 125 +PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 +PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 +PERF_PAPC_SU_ALL_OUTPUT_NULL_PRIM = 128 +PERF_PAPC_SU_SE0_STALLED_SC = 131 +PERF_PAPC_SU_SE1_STALLED_SC = 132 +PERF_PAPC_SU_ALL_STALLED_SC = 133 +PERF_PAPC_CLSM_CLIPPING_PRIM = 134 +PERF_PAPC_SU_CULLED_PRIM = 135 +PERF_PAPC_SU_OUTPUT_EOPG = 136 +PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 +PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 +PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 +PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 +PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 +PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 +PERF_PAPC_SU_SE2_STALLED_SC = 151 +PERF_PAPC_SU_SE3_STALLED_SC = 152 +PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 153 +PERF_SMALL_PRIM_CULL_PRIM_1X1 = 154 +PERF_SMALL_PRIM_CULL_PRIM_2X1 = 155 +PERF_SMALL_PRIM_CULL_PRIM_1X2 = 156 +PERF_SMALL_PRIM_CULL_PRIM_2X2 = 157 +PERF_SMALL_PRIM_CULL_PRIM_3X1 = 158 +PERF_SMALL_PRIM_CULL_PRIM_1X3 = 159 +PERF_SMALL_PRIM_CULL_PRIM_3X2 = 160 +PERF_SMALL_PRIM_CULL_PRIM_2X3 = 161 +PERF_SMALL_PRIM_CULL_PRIM_NX1 = 162 +PERF_SMALL_PRIM_CULL_PRIM_1XN = 163 +PERF_SMALL_PRIM_CULL_PRIM_NX2 = 164 +PERF_SMALL_PRIM_CULL_PRIM_2XN = 165 +PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 169 +PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 170 +PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 171 +PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 172 +PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 173 +PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 174 +PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 175 +PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 176 +PERF_PA_VERTEX_FIFO_FULL = 177 +PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 178 +PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 179 +PERF_ENGG_CSB_MACHINE_IS_STARVED = 183 +PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 184 +PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 185 +PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 186 +PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 188 +PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 189 +PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 190 +PERF_ENGG_CSB_NULL_SUBGROUP = 191 +PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 192 +PERF_ENGG_CSB_GE_MEMORY_FULL = 193 +PERF_ENGG_CSB_GE_MEMORY_EMPTY = 194 +PERF_ENGG_CSB_SPI_MEMORY_FULL = 195 +PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 196 +PERF_ENGG_INDEX_REQ_NULL_REQUEST = 224 +PERF_ENGG_INDEX_RET_0_NEW_VERTS_THIS_PRIM = 225 +PERF_ENGG_INDEX_RET_1_NEW_VERTS_THIS_PRIM = 226 +PERF_ENGG_INDEX_RET_2_NEW_VERTS_THIS_PRIM = 227 +PERF_ENGG_INDEX_RET_3_NEW_VERTS_THIS_PRIM = 228 +PERF_ENGG_INDEX_REQ_STARVED = 229 +PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 230 +PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 231 +PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 232 +PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 233 +PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 234 +PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 235 +PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 236 +PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 237 +PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 238 +PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 239 +PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 240 +PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 241 +PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 242 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 243 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 244 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 245 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 246 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 247 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 248 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 249 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 250 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 251 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 252 +PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 258 +PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 259 +PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 260 +PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 261 +PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 262 +PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 263 +PERF_ENGG_POS_REQ_STARVED = 264 +PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 265 +PERF_ENGG_BUSY = 266 +PERF_CLIPSM_CULL_PRIMS_CNT = 267 +PERF_PH_SEND_1_SC = 268 +PERF_PH_SEND_2_SC = 269 +PERF_PH_SEND_3_SC = 270 +PERF_PH_SEND_4_SC = 271 +PERF_OUTPUT_PRIM_1_SC = 272 +PERF_OUTPUT_PRIM_2_SC = 273 +PERF_OUTPUT_PRIM_3_SC = 274 +PERF_OUTPUT_PRIM_4_SC = 275 +PERF_PASX_POS_VECTOR = 276 +PERF_PASX_MISC_VECTOR = 277 +PERF_PASX_CCDIST0_VECTOR = 278 +PERF_PASX_CCDIST1_VECTOR = 279 +PERF_PASX_STEREO_POS_VECTOR = 280 +PERF_CLPR_INPUT_SEND = 281 +PERF_SU_INPUT_SEND = 282 +PERF_SU_OUTPUT_SEND = 283 +PERF_PAPC_SU_SE4_PRIM_FILTER_CULL = 284 +PERF_PAPC_SU_SE5_PRIM_FILTER_CULL = 285 +PERF_PAPC_SU_SE4_OUTPUT_PRIM = 286 +PERF_PAPC_SU_SE5_OUTPUT_PRIM = 287 +PERF_PAPC_SU_SE4_OUTPUT_NULL_PRIM = 288 +PERF_PAPC_SU_SE5_OUTPUT_NULL_PRIM = 289 +PERF_PAPC_SU_SE4_STALLED_SC = 290 +PERF_PAPC_SU_SE5_STALLED_SC = 291 +PERF_ENGG_INDEX_RET0_NEW_VERTS = 292 +PERF_ENGG_INDEX_RET1_NEW_VERTS = 293 +PERF_ENGG_INDEX_RET2_NEW_VERTS = 294 +PERF_ENGG_INDEX_RET3_NEW_VERTS = 295 +PERF_ENGG_INDEX_RET4_NEW_VERTS = 296 +PERF_ENGG_INDEX_RET5_NEW_VERTS = 297 +PERF_ENGG_INDEX_RET6_NEW_VERTS = 298 +PERF_ENGG_INDEX_RET7_NEW_VERTS = 299 +PERF_ENGG_INDEX_RET8_NEW_VERTS = 300 +PERF_ENGG_INDEX_RET9_NEW_VERTS = 301 +PERF_ENGG_INDEX_RET10_NEW_VERTS = 302 +PERF_ENGG_INDEX_RET11_NEW_VERTS = 303 +PERF_ENGG_INDEX_RET12_NEW_VERTS = 304 +PERF_PH_SEND_5_SC = 305 +PERF_PH_SEND_6_SC = 306 +PERF_OUTPUT_PRIM_5_SC = 307 +PERF_OUTPUT_PRIM_6_SC = 308 +PERF_CLPR_BACK_PRIM = 309 +PERF_PA_BUSY = 310 +SU_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RMIPerfSel' +RMIPerfSel__enumvalues = { + 0: 'RMI_PERF_SEL_NONE', + 1: 'RMI_PERF_SEL_BUSY', + 2: 'RMI_PERF_SEL_REG_CLK_VLD', + 3: 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', + 4: 'RMI_PERF_SEL_DYN_CLK_RB_VLD', + 5: 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', + 6: 'RMI_PERF_SEL_PERF_WINDOW', + 7: 'RMI_PERF_SEL_EVENT_SEND', + 8: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', + 9: 'RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY', + 10: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', + 11: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', + 12: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', + 13: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', + 14: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', + 15: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', + 16: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', + 17: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', + 18: 'RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID', + 19: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', + 20: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', + 21: 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', + 22: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', + 23: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', + 24: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', + 25: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', + 26: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', + 27: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', + 28: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', + 29: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', + 30: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', + 31: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', + 32: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', + 33: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', + 34: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', + 35: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', + 36: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', + 37: 'RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY', + 38: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', + 39: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', + 40: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', + 41: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', + 42: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', + 43: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', + 44: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', + 45: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', + 46: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', + 47: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', + 48: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', + 49: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', + 50: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', + 51: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', + 52: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', + 53: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', + 54: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', + 55: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', + 56: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', + 57: 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', + 58: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', + 59: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', + 60: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', + 61: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', + 62: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', + 63: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', + 64: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', + 65: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', + 66: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', + 67: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', + 68: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', + 69: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', + 70: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', + 71: 'RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX', + 72: 'RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY', + 73: 'RMI_PERF_SEL_RB_RMI_WR_IDLE', + 74: 'RMI_PERF_SEL_RB_RMI_WR_STARVE', + 75: 'RMI_PERF_SEL_RB_RMI_WR_STALL', + 76: 'RMI_PERF_SEL_RB_RMI_WR_BUSY', + 77: 'RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY', + 78: 'RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX', + 79: 'RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY', + 80: 'RMI_PERF_SEL_RB_RMI_RD_IDLE', + 81: 'RMI_PERF_SEL_RB_RMI_RD_STARVE', + 82: 'RMI_PERF_SEL_RB_RMI_RD_STALL', + 83: 'RMI_PERF_SEL_RB_RMI_RD_BUSY', + 84: 'RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY', + 85: 'RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID', + 86: 'RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID', + 87: 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', + 88: 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', + 89: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', + 90: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', + 91: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', + 92: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', + 93: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', + 94: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', + 95: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', + 96: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', + 97: 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', + 98: 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', + 99: 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', + 100: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', + 101: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', + 102: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', + 103: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', + 104: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', + 105: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', + 106: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', + 107: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', + 108: 'RMI_PERF_SEL_RMI_TC_STALL_RDREQ', + 109: 'RMI_PERF_SEL_RMI_TC_STALL_WRREQ', + 110: 'RMI_PERF_SEL_RMI_TC_STALL_ALLREQ', + 111: 'RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND', + 112: 'RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND', + 113: 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', + 114: 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', + 115: 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', + 116: 'RMI_PERF_SEL_TCIW_REQ', + 117: 'RMI_PERF_SEL_TCIW_BUSY', + 118: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', + 119: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', + 120: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', + 121: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', + 122: 'RMI_PERF_SEL_REORDER_FIFO_REQ', + 123: 'RMI_PERF_SEL_REORDER_FIFO_BUSY', + 124: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', + 125: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', + 126: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', + 127: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', + 128: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', + 129: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', + 130: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', + 131: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', + 132: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', + 133: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_READ_RTS_RTR', + 134: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_WRITE_RTS_RTR', + 135: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_IN0_RTS_RTR', + 136: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_IN1_RTS_RTR', + 137: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_CB_RTS_RTR', + 138: 'RMI_PERF_SEL_CONSUMER_PROBEGEN_DB_RTS_RTR', +} +RMI_PERF_SEL_NONE = 0 +RMI_PERF_SEL_BUSY = 1 +RMI_PERF_SEL_REG_CLK_VLD = 2 +RMI_PERF_SEL_DYN_CLK_CMN_VLD = 3 +RMI_PERF_SEL_DYN_CLK_RB_VLD = 4 +RMI_PERF_SEL_DYN_CLK_PERF_VLD = 5 +RMI_PERF_SEL_PERF_WINDOW = 6 +RMI_PERF_SEL_EVENT_SEND = 7 +RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 8 +RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY = 9 +RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 10 +RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 11 +RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 12 +RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 13 +RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 14 +RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 15 +RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 16 +RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 17 +RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID = 18 +RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 19 +RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 20 +RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 21 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 22 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 23 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 24 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 25 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 26 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 27 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 28 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 29 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 30 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 31 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 32 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 33 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 34 +RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 35 +RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 36 +RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY = 37 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 38 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 39 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 40 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 41 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 42 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 43 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 44 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 45 +RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 46 +RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 47 +RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 48 +RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 49 +RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 50 +RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 51 +RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 52 +RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 53 +RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 54 +RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 55 +RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 56 +RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 57 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 58 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 59 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 60 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 61 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 62 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 63 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 64 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 65 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 66 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 67 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 68 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 69 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 70 +RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX = 71 +RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY = 72 +RMI_PERF_SEL_RB_RMI_WR_IDLE = 73 +RMI_PERF_SEL_RB_RMI_WR_STARVE = 74 +RMI_PERF_SEL_RB_RMI_WR_STALL = 75 +RMI_PERF_SEL_RB_RMI_WR_BUSY = 76 +RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY = 77 +RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX = 78 +RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY = 79 +RMI_PERF_SEL_RB_RMI_RD_IDLE = 80 +RMI_PERF_SEL_RB_RMI_RD_STARVE = 81 +RMI_PERF_SEL_RB_RMI_RD_STALL = 82 +RMI_PERF_SEL_RB_RMI_RD_BUSY = 83 +RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY = 84 +RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID = 85 +RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID = 86 +RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 87 +RMI_PERF_SEL_RMI_TC_REQ_BUSY = 88 +RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 89 +RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 90 +RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 91 +RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 92 +RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 93 +RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 94 +RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 95 +RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 96 +RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 97 +RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 98 +RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 99 +RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 100 +RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 101 +RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 102 +RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 103 +RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 104 +RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 105 +RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 106 +RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 107 +RMI_PERF_SEL_RMI_TC_STALL_RDREQ = 108 +RMI_PERF_SEL_RMI_TC_STALL_WRREQ = 109 +RMI_PERF_SEL_RMI_TC_STALL_ALLREQ = 110 +RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND = 111 +RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND = 112 +RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 113 +RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 114 +RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 115 +RMI_PERF_SEL_TCIW_REQ = 116 +RMI_PERF_SEL_TCIW_BUSY = 117 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 118 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 119 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 120 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 121 +RMI_PERF_SEL_REORDER_FIFO_REQ = 122 +RMI_PERF_SEL_REORDER_FIFO_BUSY = 123 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 124 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 125 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 126 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 127 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 128 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 129 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 130 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 131 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 132 +RMI_PERF_SEL_CONSUMER_PROBEGEN_READ_RTS_RTR = 133 +RMI_PERF_SEL_CONSUMER_PROBEGEN_WRITE_RTS_RTR = 134 +RMI_PERF_SEL_CONSUMER_PROBEGEN_IN0_RTS_RTR = 135 +RMI_PERF_SEL_CONSUMER_PROBEGEN_IN1_RTS_RTR = 136 +RMI_PERF_SEL_CONSUMER_PROBEGEN_CB_RTS_RTR = 137 +RMI_PERF_SEL_CONSUMER_PROBEGEN_DB_RTS_RTR = 138 +RMIPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1PerfSel' +UTCL1PerfSel__enumvalues = { + 0: 'UTCL1_PERF_SEL_NONE', + 1: 'UTCL1_PERF_SEL_REQS', + 2: 'UTCL1_PERF_SEL_HITS', + 3: 'UTCL1_PERF_SEL_MISSES', + 4: 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', + 5: 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', + 6: 'UTCL1_PERF_SEL_UTCL2_REQS', + 7: 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', + 8: 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', + 9: 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', + 10: 'UTCL1_PERF_SEL_STALL_MH_FULL', + 11: 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', + 12: 'UTCL1_PERF_SEL_UTCL2_RET_CNT', + 13: 'UTCL1_PERF_SEL_RTNS', + 14: 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', + 15: 'UTCL1_PERF_SEL_RANGE_INVREQS', + 16: 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', + 17: 'UTCL1_PERF_SEL_BYPASS_REQS', + 18: 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', + 19: 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', + 20: 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', + 21: 'UTCL1_PERF_SEL_CP_INVREQS', + 22: 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', + 23: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4K_64K', + 24: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_64K_256K', + 25: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_256K_512K', + 26: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_512K_1M', + 27: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_1M_2M', + 28: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_2M_4M', + 29: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4M_8M', + 30: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_8M_16M', + 31: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_16M_32M', + 32: 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_32M_INF', + 33: 'UTCL1_PERF_SEL_UTCL2_REQ_SQUASHED_NUM', + 34: 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_0', + 35: 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_1', + 36: 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_2', + 37: 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_3', + 38: 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_0', + 39: 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_1', + 40: 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_2', + 41: 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_3', + 42: 'UTCL1_PERF_SEL_UTCL1_UTCL2_INVACKS', + 43: 'UTCL1_PERF_SEL_UTCL0_UTCL1_INVACKS', + 44: 'UTCL1_PERF_SEL_HITS_PG_SIZE_1', + 45: 'UTCL1_PERF_SEL_HITS_PG_SIZE_2', + 46: 'UTCL1_PERF_SEL_HITS_PG_SIZE_3', + 47: 'UTCL1_PERF_SEL_HITS_PG_SIZE_4', + 48: 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_0', + 49: 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_1', + 50: 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_2', + 51: 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_3', + 52: 'UTCL1_PERF_SEL_AVG_INV_LATENCY', + 53: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC0', + 54: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC1', + 55: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC2', + 56: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC3', + 57: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC0', + 58: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC1', + 59: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC2', + 60: 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC3', + 61: 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC0', + 62: 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC1', + 63: 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC2', + 64: 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC3', + 65: 'UTCL1_PERF_SEL_ALOG_INTERRUPT', + 66: 'UTCL1_PERF_SEL_ALOG_INTERRUPT_DROPPED', + 67: 'UTCL1_PERF_SEL_ALOG_CACHE_REQ', + 68: 'UTCL1_PERF_SEL_ALOG_CACHE_HIT', + 69: 'UTCL1_PERF_SEL_ALOG_STALL_PMM_CREDITS', +} +UTCL1_PERF_SEL_NONE = 0 +UTCL1_PERF_SEL_REQS = 1 +UTCL1_PERF_SEL_HITS = 2 +UTCL1_PERF_SEL_MISSES = 3 +UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 4 +UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 5 +UTCL1_PERF_SEL_UTCL2_REQS = 6 +UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 7 +UTCL1_PERF_SEL_UTCL2_RET_FAULT = 8 +UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 9 +UTCL1_PERF_SEL_STALL_MH_FULL = 10 +UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 11 +UTCL1_PERF_SEL_UTCL2_RET_CNT = 12 +UTCL1_PERF_SEL_RTNS = 13 +UTCL1_PERF_SEL_XLAT_REQ_BUSY = 14 +UTCL1_PERF_SEL_RANGE_INVREQS = 15 +UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 16 +UTCL1_PERF_SEL_BYPASS_REQS = 17 +UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 18 +UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 19 +UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 20 +UTCL1_PERF_SEL_CP_INVREQS = 21 +UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 22 +UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4K_64K = 23 +UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_64K_256K = 24 +UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_256K_512K = 25 +UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_512K_1M = 26 +UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_1M_2M = 27 +UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_2M_4M = 28 +UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4M_8M = 29 +UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_8M_16M = 30 +UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_16M_32M = 31 +UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_32M_INF = 32 +UTCL1_PERF_SEL_UTCL2_REQ_SQUASHED_NUM = 33 +UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_0 = 34 +UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_1 = 35 +UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_2 = 36 +UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_3 = 37 +UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_0 = 38 +UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_1 = 39 +UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_2 = 40 +UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_3 = 41 +UTCL1_PERF_SEL_UTCL1_UTCL2_INVACKS = 42 +UTCL1_PERF_SEL_UTCL0_UTCL1_INVACKS = 43 +UTCL1_PERF_SEL_HITS_PG_SIZE_1 = 44 +UTCL1_PERF_SEL_HITS_PG_SIZE_2 = 45 +UTCL1_PERF_SEL_HITS_PG_SIZE_3 = 46 +UTCL1_PERF_SEL_HITS_PG_SIZE_4 = 47 +UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_0 = 48 +UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_1 = 49 +UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_2 = 50 +UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_3 = 51 +UTCL1_PERF_SEL_AVG_INV_LATENCY = 52 +UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC0 = 53 +UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC1 = 54 +UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC2 = 55 +UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC3 = 56 +UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC0 = 57 +UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC1 = 58 +UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC2 = 59 +UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC3 = 60 +UTCL1_PERF_SEL_EVICTIONS_NUM_CC0 = 61 +UTCL1_PERF_SEL_EVICTIONS_NUM_CC1 = 62 +UTCL1_PERF_SEL_EVICTIONS_NUM_CC2 = 63 +UTCL1_PERF_SEL_EVICTIONS_NUM_CC3 = 64 +UTCL1_PERF_SEL_ALOG_INTERRUPT = 65 +UTCL1_PERF_SEL_ALOG_INTERRUPT_DROPPED = 66 +UTCL1_PERF_SEL_ALOG_CACHE_REQ = 67 +UTCL1_PERF_SEL_ALOG_CACHE_HIT = 68 +UTCL1_PERF_SEL_ALOG_STALL_PMM_CREDITS = 69 +UTCL1PerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'GC_EA_SE_PERFCOUNT_SEL' +GC_EA_SE_PERFCOUNT_SEL__enumvalues = { + 0: 'GC_EA_SE_PERF_SEL_ALWAYS_COUNT', + 1: 'GC_EA_SE_PERF_SEL_RDRAM_NUM_BANKS_VLD', + 2: 'GC_EA_SE_PERF_SEL_RDRAM_REQ_PER_CLIGRP', + 3: 'GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP', + 4: 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START0', + 5: 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END0', + 6: 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START1', + 7: 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END1', + 8: 'GC_EA_SE_PERF_SEL_WDRAM_NUM_BANKS_VLD', + 9: 'GC_EA_SE_PERF_SEL_WDRAM_REQ_PER_CLIGRP', + 10: 'GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP', + 11: 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START0', + 12: 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END0', + 13: 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START1', + 14: 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END1', + 15: 'GC_EA_SE_PERF_SEL_RGMI_NUM_BANKS_VLD', + 16: 'GC_EA_SE_PERF_SEL_RGMI_REQ_PER_CLIGRP', + 17: 'GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR', + 18: 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_START0', + 19: 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_END0', + 20: 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_START1', + 21: 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_END1', + 22: 'GC_EA_SE_PERF_SEL_WGMI_NUM_BANKS_VLD', + 23: 'GC_EA_SE_PERF_SEL_WGMI_REQ_PER_CLIGRP', + 24: 'GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP', + 25: 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_START0', + 26: 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_END0', + 27: 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_START1', + 28: 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_END1', + 29: 'GC_EA_SE_PERF_SEL_RIO_REQ_PER_CLIGRP', + 30: 'GC_EA_SE_PERF_SEL_RIO_SIZE_REQ', + 31: 'GC_EA_SE_PERF_SEL_RIO_GRP0_SIZE_REQ', + 32: 'GC_EA_SE_PERF_SEL_RIO_GRP1_SIZE_REQ', + 33: 'GC_EA_SE_PERF_SEL_RIO_GRP2_SIZE_REQ', + 34: 'GC_EA_SE_PERF_SEL_RIO_GRP3_SIZE_REQ', + 35: 'GC_EA_SE_PERF_SEL_RIO_LATENCY_START0', + 36: 'GC_EA_SE_PERF_SEL_RIO_LATENCY_END0', + 37: 'GC_EA_SE_PERF_SEL_RIO_LATENCY_START1', + 38: 'GC_EA_SE_PERF_SEL_RIO_LATENCY_END1', + 39: 'GC_EA_SE_PERF_SEL_WIO_REQ_PER_CLIGRP', + 40: 'GC_EA_SE_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP', + 41: 'GC_EA_SE_PERF_SEL_WIO_SIZE_REQ', + 42: 'GC_EA_SE_PERF_SEL_WIO_GRP0_SIZE_REQ', + 43: 'GC_EA_SE_PERF_SEL_WIO_GRP1_SIZE_REQ', + 44: 'GC_EA_SE_PERF_SEL_WIO_GRP2_SIZE_REQ', + 45: 'GC_EA_SE_PERF_SEL_WIO_GRP3_SIZE_REQ', + 46: 'GC_EA_SE_PERF_SEL_WIO_LATENCY_START0', + 47: 'GC_EA_SE_PERF_SEL_WIO_LATENCY_END0', + 48: 'GC_EA_SE_PERF_SEL_WIO_LATENCY_START1', + 49: 'GC_EA_SE_PERF_SEL_WIO_LATENCY_END1', + 50: 'GC_EA_SE_PERF_SEL_SARB_REQ_PER_VC', + 51: 'GC_EA_SE_PERF_SEL_SARB_DRAM_REQ_PER_VC', + 52: 'GC_EA_SE_PERF_SEL_SARB_GMI_REQ_PER_VC', + 53: 'GC_EA_SE_PERF_SEL_SARB_IO_REQ_PER_VC', + 54: 'GC_EA_SE_PERF_SEL_SARB_SIZE_REQ', + 55: 'GC_EA_SE_PERF_SEL_SARB_DRAM_SIZE_REQ', + 56: 'GC_EA_SE_PERF_SEL_SARB_GMI_SIZE_REQ', + 57: 'GC_EA_SE_PERF_SEL_SARB_IO_SIZE_REQ', + 58: 'GC_EA_SE_PERF_SEL_SARB_LATENCY_START0', + 59: 'GC_EA_SE_PERF_SEL_SARB_LATENCY_END0', + 60: 'GC_EA_SE_PERF_SEL_SARB_LATENCY_START1', + 61: 'GC_EA_SE_PERF_SEL_SARB_LATENCY_END1', + 62: 'GC_EA_SE_PERF_SEL_SARB_BUSY', + 63: 'GC_EA_SE_PERF_SEL_SARB_STALLED', + 64: 'GC_EA_SE_PERF_SEL_SARB_STARVING', + 65: 'GC_EA_SE_PERF_SEL_SARB_IDLE', + 66: 'GC_EA_SE_PERF_SEL_RRET_VLD', + 67: 'GC_EA_SE_PERF_SEL_WRET_VLD', + 68: 'GC_EA_SE_PERF_SEL_PRB_REQ', + 69: 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_EVICT', + 70: 'GC_EA_SE_PERF_SEL_MAM_ARAM_REQ_VLD', + 71: 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT', + 72: 'GC_EA_SE_PERF_SEL_MAM_NUM_DQRY', + 73: 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT', + 74: 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED', + 75: 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_COMPLETED', + 76: 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_ONGOING', + 77: 'GC_EA_SE_PERF_SEL_RDRAM_SIZE_REQ', + 78: 'GC_EA_SE_PERF_SEL_WDRAM_SIZE_REQ', + 79: 'GC_EA_SE_PERF_SEL_RGMI_SIZE_REQ', + 80: 'GC_EA_SE_PERF_SEL_WGMI_SIZE_REQ', + 81: 'GC_EA_SE_PERF_SEL_SARB_DRAM_RW_TURN_AROUND', + 82: 'GC_EA_SE_PERF_SEL_SARB_GMI_RW_TURN_AROUND', + 83: 'GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', + 84: 'GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', + 85: 'GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH', + 86: 'GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH', + 87: 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_EVICT', + 88: 'GC_EA_SE_PERF_SEL_MAM_DBIT_REQ_VLD', + 89: 'GC_EA_SE_PERF_SEL_SARB_COHERENT_SIZE_REQ', + 90: 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT_EVICT', + 91: 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_LRU_EVICT', + 92: 'GC_EA_SE_PERF_SEL_MAM_FLUSH_REQ', + 93: 'GC_EA_SE_PERF_SEL_MAM_FLUSH_RESP', + 94: 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT_EVICT', + 95: 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_LRU_EVICT', + 96: 'GC_EA_SE_PERF_SEL_MAM_DQRY_ONGOING', + 97: 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT', +} +GC_EA_SE_PERF_SEL_ALWAYS_COUNT = 0 +GC_EA_SE_PERF_SEL_RDRAM_NUM_BANKS_VLD = 1 +GC_EA_SE_PERF_SEL_RDRAM_REQ_PER_CLIGRP = 2 +GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP = 3 +GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START0 = 4 +GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END0 = 5 +GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START1 = 6 +GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END1 = 7 +GC_EA_SE_PERF_SEL_WDRAM_NUM_BANKS_VLD = 8 +GC_EA_SE_PERF_SEL_WDRAM_REQ_PER_CLIGRP = 9 +GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP = 10 +GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START0 = 11 +GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END0 = 12 +GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START1 = 13 +GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END1 = 14 +GC_EA_SE_PERF_SEL_RGMI_NUM_BANKS_VLD = 15 +GC_EA_SE_PERF_SEL_RGMI_REQ_PER_CLIGRP = 16 +GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR = 17 +GC_EA_SE_PERF_SEL_RGMI_LATENCY_START0 = 18 +GC_EA_SE_PERF_SEL_RGMI_LATENCY_END0 = 19 +GC_EA_SE_PERF_SEL_RGMI_LATENCY_START1 = 20 +GC_EA_SE_PERF_SEL_RGMI_LATENCY_END1 = 21 +GC_EA_SE_PERF_SEL_WGMI_NUM_BANKS_VLD = 22 +GC_EA_SE_PERF_SEL_WGMI_REQ_PER_CLIGRP = 23 +GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP = 24 +GC_EA_SE_PERF_SEL_WGMI_LATENCY_START0 = 25 +GC_EA_SE_PERF_SEL_WGMI_LATENCY_END0 = 26 +GC_EA_SE_PERF_SEL_WGMI_LATENCY_START1 = 27 +GC_EA_SE_PERF_SEL_WGMI_LATENCY_END1 = 28 +GC_EA_SE_PERF_SEL_RIO_REQ_PER_CLIGRP = 29 +GC_EA_SE_PERF_SEL_RIO_SIZE_REQ = 30 +GC_EA_SE_PERF_SEL_RIO_GRP0_SIZE_REQ = 31 +GC_EA_SE_PERF_SEL_RIO_GRP1_SIZE_REQ = 32 +GC_EA_SE_PERF_SEL_RIO_GRP2_SIZE_REQ = 33 +GC_EA_SE_PERF_SEL_RIO_GRP3_SIZE_REQ = 34 +GC_EA_SE_PERF_SEL_RIO_LATENCY_START0 = 35 +GC_EA_SE_PERF_SEL_RIO_LATENCY_END0 = 36 +GC_EA_SE_PERF_SEL_RIO_LATENCY_START1 = 37 +GC_EA_SE_PERF_SEL_RIO_LATENCY_END1 = 38 +GC_EA_SE_PERF_SEL_WIO_REQ_PER_CLIGRP = 39 +GC_EA_SE_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP = 40 +GC_EA_SE_PERF_SEL_WIO_SIZE_REQ = 41 +GC_EA_SE_PERF_SEL_WIO_GRP0_SIZE_REQ = 42 +GC_EA_SE_PERF_SEL_WIO_GRP1_SIZE_REQ = 43 +GC_EA_SE_PERF_SEL_WIO_GRP2_SIZE_REQ = 44 +GC_EA_SE_PERF_SEL_WIO_GRP3_SIZE_REQ = 45 +GC_EA_SE_PERF_SEL_WIO_LATENCY_START0 = 46 +GC_EA_SE_PERF_SEL_WIO_LATENCY_END0 = 47 +GC_EA_SE_PERF_SEL_WIO_LATENCY_START1 = 48 +GC_EA_SE_PERF_SEL_WIO_LATENCY_END1 = 49 +GC_EA_SE_PERF_SEL_SARB_REQ_PER_VC = 50 +GC_EA_SE_PERF_SEL_SARB_DRAM_REQ_PER_VC = 51 +GC_EA_SE_PERF_SEL_SARB_GMI_REQ_PER_VC = 52 +GC_EA_SE_PERF_SEL_SARB_IO_REQ_PER_VC = 53 +GC_EA_SE_PERF_SEL_SARB_SIZE_REQ = 54 +GC_EA_SE_PERF_SEL_SARB_DRAM_SIZE_REQ = 55 +GC_EA_SE_PERF_SEL_SARB_GMI_SIZE_REQ = 56 +GC_EA_SE_PERF_SEL_SARB_IO_SIZE_REQ = 57 +GC_EA_SE_PERF_SEL_SARB_LATENCY_START0 = 58 +GC_EA_SE_PERF_SEL_SARB_LATENCY_END0 = 59 +GC_EA_SE_PERF_SEL_SARB_LATENCY_START1 = 60 +GC_EA_SE_PERF_SEL_SARB_LATENCY_END1 = 61 +GC_EA_SE_PERF_SEL_SARB_BUSY = 62 +GC_EA_SE_PERF_SEL_SARB_STALLED = 63 +GC_EA_SE_PERF_SEL_SARB_STARVING = 64 +GC_EA_SE_PERF_SEL_SARB_IDLE = 65 +GC_EA_SE_PERF_SEL_RRET_VLD = 66 +GC_EA_SE_PERF_SEL_WRET_VLD = 67 +GC_EA_SE_PERF_SEL_PRB_REQ = 68 +GC_EA_SE_PERF_SEL_MAM_ARAM_FA_EVICT = 69 +GC_EA_SE_PERF_SEL_MAM_ARAM_REQ_VLD = 70 +GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT = 71 +GC_EA_SE_PERF_SEL_MAM_NUM_DQRY = 72 +GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT = 73 +GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED = 74 +GC_EA_SE_PERF_SEL_MAM_AFLUSH_COMPLETED = 75 +GC_EA_SE_PERF_SEL_MAM_AFLUSH_ONGOING = 76 +GC_EA_SE_PERF_SEL_RDRAM_SIZE_REQ = 77 +GC_EA_SE_PERF_SEL_WDRAM_SIZE_REQ = 78 +GC_EA_SE_PERF_SEL_RGMI_SIZE_REQ = 79 +GC_EA_SE_PERF_SEL_WGMI_SIZE_REQ = 80 +GC_EA_SE_PERF_SEL_SARB_DRAM_RW_TURN_AROUND = 81 +GC_EA_SE_PERF_SEL_SARB_GMI_RW_TURN_AROUND = 82 +GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 83 +GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 84 +GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 85 +GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 86 +GC_EA_SE_PERF_SEL_MAM_DBIT_FA_EVICT = 87 +GC_EA_SE_PERF_SEL_MAM_DBIT_REQ_VLD = 88 +GC_EA_SE_PERF_SEL_SARB_COHERENT_SIZE_REQ = 89 +GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT_EVICT = 90 +GC_EA_SE_PERF_SEL_MAM_ARAM_FA_LRU_EVICT = 91 +GC_EA_SE_PERF_SEL_MAM_FLUSH_REQ = 92 +GC_EA_SE_PERF_SEL_MAM_FLUSH_RESP = 93 +GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT_EVICT = 94 +GC_EA_SE_PERF_SEL_MAM_DBIT_FA_LRU_EVICT = 95 +GC_EA_SE_PERF_SEL_MAM_DQRY_ONGOING = 96 +GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT = 97 +GC_EA_SE_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'LSDMA_PERF_SEL' +LSDMA_PERF_SEL__enumvalues = { + 0: 'LSDMA_PERF_SEL_CYCLE', + 1: 'LSDMA_PERF_SEL_IDLE', + 2: 'LSDMA_PERF_SEL_REG_IDLE', + 3: 'LSDMA_PERF_SEL_RB_EMPTY', + 4: 'LSDMA_PERF_SEL_RB_FULL', + 5: 'LSDMA_PERF_SEL_RB_WPTR_WRAP', + 6: 'LSDMA_PERF_SEL_RB_RPTR_WRAP', + 7: 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', + 8: 'LSDMA_PERF_SEL_RB_RPTR_WB', + 9: 'LSDMA_PERF_SEL_RB_CMD_IDLE', + 10: 'LSDMA_PERF_SEL_RB_CMD_FULL', + 11: 'LSDMA_PERF_SEL_IB_CMD_IDLE', + 12: 'LSDMA_PERF_SEL_IB_CMD_FULL', + 13: 'LSDMA_PERF_SEL_EX_IDLE', + 14: 'LSDMA_PERF_SEL_SRBM_REG_SEND', + 15: 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'LSDMA_PERF_SEL_MC_WR_IDLE', + 17: 'LSDMA_PERF_SEL_MC_WR_COUNT', + 18: 'LSDMA_PERF_SEL_MC_RD_IDLE', + 19: 'LSDMA_PERF_SEL_MC_RD_COUNT', + 20: 'LSDMA_PERF_SEL_MC_RD_RET_STALL', + 21: 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 24: 'LSDMA_PERF_SEL_SEM_IDLE', + 25: 'LSDMA_PERF_SEL_SEM_REQ_STALL', + 26: 'LSDMA_PERF_SEL_SEM_REQ_COUNT', + 27: 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 28: 'LSDMA_PERF_SEL_SEM_RESP_FAIL', + 29: 'LSDMA_PERF_SEL_SEM_RESP_PASS', + 30: 'LSDMA_PERF_SEL_INT_IDLE', + 31: 'LSDMA_PERF_SEL_INT_REQ_STALL', + 32: 'LSDMA_PERF_SEL_INT_REQ_COUNT', + 33: 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', + 34: 'LSDMA_PERF_SEL_INT_RESP_RETRY', + 35: 'LSDMA_PERF_SEL_NUM_PACKET', + 37: 'LSDMA_PERF_SEL_CE_WREQ_IDLE', + 38: 'LSDMA_PERF_SEL_CE_WR_IDLE', + 39: 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', + 40: 'LSDMA_PERF_SEL_CE_RREQ_IDLE', + 41: 'LSDMA_PERF_SEL_CE_OUT_IDLE', + 42: 'LSDMA_PERF_SEL_CE_IN_IDLE', + 43: 'LSDMA_PERF_SEL_CE_DST_IDLE', + 46: 'LSDMA_PERF_SEL_CE_AFIFO_FULL', + 47: 'LSDMA_PERF_SEL_DUMMY_0', + 48: 'LSDMA_PERF_SEL_DUMMY_1', + 49: 'LSDMA_PERF_SEL_CE_INFO_FULL', + 50: 'LSDMA_PERF_SEL_CE_INFO1_FULL', + 51: 'LSDMA_PERF_SEL_CE_RD_STALL', + 52: 'LSDMA_PERF_SEL_CE_WR_STALL', + 53: 'LSDMA_PERF_SEL_GFX_SELECT', + 54: 'LSDMA_PERF_SEL_RLC0_SELECT', + 55: 'LSDMA_PERF_SEL_RLC1_SELECT', + 56: 'LSDMA_PERF_SEL_PAGE_SELECT', + 57: 'LSDMA_PERF_SEL_CTX_CHANGE', + 58: 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', + 59: 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 60: 'LSDMA_PERF_SEL_DOORBELL', + 61: 'LSDMA_PERF_SEL_RD_BA_RTR', + 62: 'LSDMA_PERF_SEL_WR_BA_RTR', + 63: 'LSDMA_PERF_SEL_F32_L1_WR_VLD', + 64: 'LSDMA_PERF_SEL_CE_L1_WR_VLD', + 65: 'LSDMA_PERF_SEL_CE_L1_STALL', + 66: 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', + 67: 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', + 68: 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', + 69: 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', + 70: 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', + 71: 'LSDMA_PERF_SEL_ATCL2_RET_ACK', + 72: 'LSDMA_PERF_SEL_ATCL2_FREE', + 73: 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', + 74: 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', + 75: 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', + 76: 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', + 77: 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', + 78: 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', + 79: 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', + 80: 'LSDMA_PERF_SEL_L1_WRL2_IDLE', + 81: 'LSDMA_PERF_SEL_L1_RDL2_IDLE', + 82: 'LSDMA_PERF_SEL_L1_WRMC_IDLE', + 83: 'LSDMA_PERF_SEL_L1_RDMC_IDLE', + 84: 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', + 85: 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', + 86: 'LSDMA_PERF_SEL_L1_WR_INV_EN', + 87: 'LSDMA_PERF_SEL_L1_RD_INV_EN', + 88: 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', + 89: 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', + 90: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', + 91: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', + 92: 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', + 93: 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', + 94: 'LSDMA_PERF_SEL_L1_INV_MIDDLE', + 95: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', + 96: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', + 97: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', + 98: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', + 99: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', + 100: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', + 101: 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', + 102: 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', + 103: 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', + 104: 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', + 105: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', + 106: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', + 107: 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', + 108: 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', + 109: 'LSDMA_PERF_SEL_CMD_OP_MATCH', + 110: 'LSDMA_PERF_SEL_CMD_OP_START', + 111: 'LSDMA_PERF_SEL_CMD_OP_END', + 112: 'LSDMA_PERF_SEL_CE_BUSY', + 113: 'LSDMA_PERF_SEL_CE_BUSY_START', + 114: 'LSDMA_PERF_SEL_CE_BUSY_END', + 115: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 116: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 117: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 118: 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', + 119: 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', + 120: 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', + 121: 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', + 122: 'LSDMA_PERF_SEL_DRAM_ECC', + 123: 'LSDMA_PERF_SEL_NACK_GEN_ERR', +} +LSDMA_PERF_SEL_CYCLE = 0 +LSDMA_PERF_SEL_IDLE = 1 +LSDMA_PERF_SEL_REG_IDLE = 2 +LSDMA_PERF_SEL_RB_EMPTY = 3 +LSDMA_PERF_SEL_RB_FULL = 4 +LSDMA_PERF_SEL_RB_WPTR_WRAP = 5 +LSDMA_PERF_SEL_RB_RPTR_WRAP = 6 +LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 +LSDMA_PERF_SEL_RB_RPTR_WB = 8 +LSDMA_PERF_SEL_RB_CMD_IDLE = 9 +LSDMA_PERF_SEL_RB_CMD_FULL = 10 +LSDMA_PERF_SEL_IB_CMD_IDLE = 11 +LSDMA_PERF_SEL_IB_CMD_FULL = 12 +LSDMA_PERF_SEL_EX_IDLE = 13 +LSDMA_PERF_SEL_SRBM_REG_SEND = 14 +LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +LSDMA_PERF_SEL_MC_WR_IDLE = 16 +LSDMA_PERF_SEL_MC_WR_COUNT = 17 +LSDMA_PERF_SEL_MC_RD_IDLE = 18 +LSDMA_PERF_SEL_MC_RD_COUNT = 19 +LSDMA_PERF_SEL_MC_RD_RET_STALL = 20 +LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 +LSDMA_PERF_SEL_SEM_IDLE = 24 +LSDMA_PERF_SEL_SEM_REQ_STALL = 25 +LSDMA_PERF_SEL_SEM_REQ_COUNT = 26 +LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 +LSDMA_PERF_SEL_SEM_RESP_FAIL = 28 +LSDMA_PERF_SEL_SEM_RESP_PASS = 29 +LSDMA_PERF_SEL_INT_IDLE = 30 +LSDMA_PERF_SEL_INT_REQ_STALL = 31 +LSDMA_PERF_SEL_INT_REQ_COUNT = 32 +LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 +LSDMA_PERF_SEL_INT_RESP_RETRY = 34 +LSDMA_PERF_SEL_NUM_PACKET = 35 +LSDMA_PERF_SEL_CE_WREQ_IDLE = 37 +LSDMA_PERF_SEL_CE_WR_IDLE = 38 +LSDMA_PERF_SEL_CE_SPLIT_IDLE = 39 +LSDMA_PERF_SEL_CE_RREQ_IDLE = 40 +LSDMA_PERF_SEL_CE_OUT_IDLE = 41 +LSDMA_PERF_SEL_CE_IN_IDLE = 42 +LSDMA_PERF_SEL_CE_DST_IDLE = 43 +LSDMA_PERF_SEL_CE_AFIFO_FULL = 46 +LSDMA_PERF_SEL_DUMMY_0 = 47 +LSDMA_PERF_SEL_DUMMY_1 = 48 +LSDMA_PERF_SEL_CE_INFO_FULL = 49 +LSDMA_PERF_SEL_CE_INFO1_FULL = 50 +LSDMA_PERF_SEL_CE_RD_STALL = 51 +LSDMA_PERF_SEL_CE_WR_STALL = 52 +LSDMA_PERF_SEL_GFX_SELECT = 53 +LSDMA_PERF_SEL_RLC0_SELECT = 54 +LSDMA_PERF_SEL_RLC1_SELECT = 55 +LSDMA_PERF_SEL_PAGE_SELECT = 56 +LSDMA_PERF_SEL_CTX_CHANGE = 57 +LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 +LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 +LSDMA_PERF_SEL_DOORBELL = 60 +LSDMA_PERF_SEL_RD_BA_RTR = 61 +LSDMA_PERF_SEL_WR_BA_RTR = 62 +LSDMA_PERF_SEL_F32_L1_WR_VLD = 63 +LSDMA_PERF_SEL_CE_L1_WR_VLD = 64 +LSDMA_PERF_SEL_CE_L1_STALL = 65 +LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66 +LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67 +LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68 +LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69 +LSDMA_PERF_SEL_ATCL2_RET_XNACK = 70 +LSDMA_PERF_SEL_ATCL2_RET_ACK = 71 +LSDMA_PERF_SEL_ATCL2_FREE = 72 +LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 73 +LSDMA_PERF_SEL_DMA_L1_WR_SEND = 74 +LSDMA_PERF_SEL_DMA_L1_RD_SEND = 75 +LSDMA_PERF_SEL_DMA_MC_WR_SEND = 76 +LSDMA_PERF_SEL_DMA_MC_RD_SEND = 77 +LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78 +LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79 +LSDMA_PERF_SEL_L1_WRL2_IDLE = 80 +LSDMA_PERF_SEL_L1_RDL2_IDLE = 81 +LSDMA_PERF_SEL_L1_WRMC_IDLE = 82 +LSDMA_PERF_SEL_L1_RDMC_IDLE = 83 +LSDMA_PERF_SEL_L1_WR_INV_IDLE = 84 +LSDMA_PERF_SEL_L1_RD_INV_IDLE = 85 +LSDMA_PERF_SEL_L1_WR_INV_EN = 86 +LSDMA_PERF_SEL_L1_RD_INV_EN = 87 +LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88 +LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89 +LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90 +LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91 +LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92 +LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93 +LSDMA_PERF_SEL_L1_INV_MIDDLE = 94 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 95 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 96 +LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 97 +LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 98 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 99 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 100 +LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 101 +LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 102 +LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 103 +LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 104 +LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 105 +LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 106 +LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 107 +LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 108 +LSDMA_PERF_SEL_CMD_OP_MATCH = 109 +LSDMA_PERF_SEL_CMD_OP_START = 110 +LSDMA_PERF_SEL_CMD_OP_END = 111 +LSDMA_PERF_SEL_CE_BUSY = 112 +LSDMA_PERF_SEL_CE_BUSY_START = 113 +LSDMA_PERF_SEL_CE_BUSY_END = 114 +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 115 +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 116 +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 117 +LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 118 +LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 119 +LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 120 +LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 121 +LSDMA_PERF_SEL_DRAM_ECC = 122 +LSDMA_PERF_SEL_NACK_GEN_ERR = 123 +LSDMA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'EFC_SURFACE_PIXEL_FORMAT' +EFC_SURFACE_PIXEL_FORMAT__enumvalues = { + 1: 'EFC_ARGB1555', + 2: 'EFC_RGBA5551', + 3: 'EFC_RGB565', + 4: 'EFC_BGR565', + 5: 'EFC_ARGB4444', + 6: 'EFC_RGBA4444', + 8: 'EFC_ARGB8888', + 9: 'EFC_RGBA8888', + 10: 'EFC_ARGB2101010', + 11: 'EFC_RGBA1010102', + 12: 'EFC_AYCrCb8888', + 13: 'EFC_YCrCbA8888', + 14: 'EFC_ACrYCb8888', + 15: 'EFC_CrYCbA8888', + 16: 'EFC_ARGB16161616_10MSB', + 17: 'EFC_RGBA16161616_10MSB', + 18: 'EFC_ARGB16161616_10LSB', + 19: 'EFC_RGBA16161616_10LSB', + 20: 'EFC_ARGB16161616_12MSB', + 21: 'EFC_RGBA16161616_12MSB', + 22: 'EFC_ARGB16161616_12LSB', + 23: 'EFC_RGBA16161616_12LSB', + 24: 'EFC_ARGB16161616_FLOAT', + 25: 'EFC_RGBA16161616_FLOAT', + 26: 'EFC_ARGB16161616_UNORM', + 27: 'EFC_RGBA16161616_UNORM', + 28: 'EFC_ARGB16161616_SNORM', + 29: 'EFC_RGBA16161616_SNORM', + 32: 'EFC_AYCrCb16161616_10MSB', + 33: 'EFC_AYCrCb16161616_10LSB', + 34: 'EFC_YCrCbA16161616_10MSB', + 35: 'EFC_YCrCbA16161616_10LSB', + 36: 'EFC_ACrYCb16161616_10MSB', + 37: 'EFC_ACrYCb16161616_10LSB', + 38: 'EFC_CrYCbA16161616_10MSB', + 39: 'EFC_CrYCbA16161616_10LSB', + 40: 'EFC_AYCrCb16161616_12MSB', + 41: 'EFC_AYCrCb16161616_12LSB', + 42: 'EFC_YCrCbA16161616_12MSB', + 43: 'EFC_YCrCbA16161616_12LSB', + 44: 'EFC_ACrYCb16161616_12MSB', + 45: 'EFC_ACrYCb16161616_12LSB', + 46: 'EFC_CrYCbA16161616_12MSB', + 47: 'EFC_CrYCbA16161616_12LSB', + 64: 'EFC_Y8_CrCb88_420_PLANAR', + 65: 'EFC_Y8_CbCr88_420_PLANAR', + 66: 'EFC_Y10_CrCb1010_420_PLANAR', + 67: 'EFC_Y10_CbCr1010_420_PLANAR', + 68: 'EFC_Y12_CrCb1212_420_PLANAR', + 69: 'EFC_Y12_CbCr1212_420_PLANAR', + 72: 'EFC_YCrYCb8888_422_PACKED', + 73: 'EFC_YCbYCr8888_422_PACKED', + 74: 'EFC_CrYCbY8888_422_PACKED', + 75: 'EFC_CbYCrY8888_422_PACKED', + 76: 'EFC_YCrYCb10101010_422_PACKED', + 77: 'EFC_YCbYCr10101010_422_PACKED', + 78: 'EFC_CrYCbY10101010_422_PACKED', + 79: 'EFC_CbYCrY10101010_422_PACKED', + 80: 'EFC_YCrYCb12121212_422_PACKED', + 81: 'EFC_YCbYCr12121212_422_PACKED', + 82: 'EFC_CrYCbY12121212_422_PACKED', + 83: 'EFC_CbYCrY12121212_422_PACKED', + 112: 'EFC_RGB111110_FIX', + 113: 'EFC_BGR101111_FIX', + 114: 'EFC_ACrYCb2101010', + 115: 'EFC_CrYCbA1010102', + 118: 'EFC_RGB111110_FLOAT', + 119: 'EFC_BGR101111_FLOAT', + 120: 'EFC_MONO_8', + 121: 'EFC_MONO_10MSB', + 122: 'EFC_MONO_10LSB', + 123: 'EFC_MONO_12MSB', + 124: 'EFC_MONO_12LSB', + 125: 'EFC_MONO_16', +} +EFC_ARGB1555 = 1 +EFC_RGBA5551 = 2 +EFC_RGB565 = 3 +EFC_BGR565 = 4 +EFC_ARGB4444 = 5 +EFC_RGBA4444 = 6 +EFC_ARGB8888 = 8 +EFC_RGBA8888 = 9 +EFC_ARGB2101010 = 10 +EFC_RGBA1010102 = 11 +EFC_AYCrCb8888 = 12 +EFC_YCrCbA8888 = 13 +EFC_ACrYCb8888 = 14 +EFC_CrYCbA8888 = 15 +EFC_ARGB16161616_10MSB = 16 +EFC_RGBA16161616_10MSB = 17 +EFC_ARGB16161616_10LSB = 18 +EFC_RGBA16161616_10LSB = 19 +EFC_ARGB16161616_12MSB = 20 +EFC_RGBA16161616_12MSB = 21 +EFC_ARGB16161616_12LSB = 22 +EFC_RGBA16161616_12LSB = 23 +EFC_ARGB16161616_FLOAT = 24 +EFC_RGBA16161616_FLOAT = 25 +EFC_ARGB16161616_UNORM = 26 +EFC_RGBA16161616_UNORM = 27 +EFC_ARGB16161616_SNORM = 28 +EFC_RGBA16161616_SNORM = 29 +EFC_AYCrCb16161616_10MSB = 32 +EFC_AYCrCb16161616_10LSB = 33 +EFC_YCrCbA16161616_10MSB = 34 +EFC_YCrCbA16161616_10LSB = 35 +EFC_ACrYCb16161616_10MSB = 36 +EFC_ACrYCb16161616_10LSB = 37 +EFC_CrYCbA16161616_10MSB = 38 +EFC_CrYCbA16161616_10LSB = 39 +EFC_AYCrCb16161616_12MSB = 40 +EFC_AYCrCb16161616_12LSB = 41 +EFC_YCrCbA16161616_12MSB = 42 +EFC_YCrCbA16161616_12LSB = 43 +EFC_ACrYCb16161616_12MSB = 44 +EFC_ACrYCb16161616_12LSB = 45 +EFC_CrYCbA16161616_12MSB = 46 +EFC_CrYCbA16161616_12LSB = 47 +EFC_Y8_CrCb88_420_PLANAR = 64 +EFC_Y8_CbCr88_420_PLANAR = 65 +EFC_Y10_CrCb1010_420_PLANAR = 66 +EFC_Y10_CbCr1010_420_PLANAR = 67 +EFC_Y12_CrCb1212_420_PLANAR = 68 +EFC_Y12_CbCr1212_420_PLANAR = 69 +EFC_YCrYCb8888_422_PACKED = 72 +EFC_YCbYCr8888_422_PACKED = 73 +EFC_CrYCbY8888_422_PACKED = 74 +EFC_CbYCrY8888_422_PACKED = 75 +EFC_YCrYCb10101010_422_PACKED = 76 +EFC_YCbYCr10101010_422_PACKED = 77 +EFC_CrYCbY10101010_422_PACKED = 78 +EFC_CbYCrY10101010_422_PACKED = 79 +EFC_YCrYCb12121212_422_PACKED = 80 +EFC_YCbYCr12121212_422_PACKED = 81 +EFC_CrYCbY12121212_422_PACKED = 82 +EFC_CbYCrY12121212_422_PACKED = 83 +EFC_RGB111110_FIX = 112 +EFC_BGR101111_FIX = 113 +EFC_ACrYCb2101010 = 114 +EFC_CrYCbA1010102 = 115 +EFC_RGB111110_FLOAT = 118 +EFC_BGR101111_FLOAT = 119 +EFC_MONO_8 = 120 +EFC_MONO_10MSB = 121 +EFC_MONO_10LSB = 122 +EFC_MONO_12MSB = 123 +EFC_MONO_12LSB = 124 +EFC_MONO_16 = 125 +EFC_SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum +__all__ = \ + ['ACCEPT_UNSOLICITED_RESPONSE_ENABLE', + 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ACP_TYPE_DVD_AUDIO', + 'ACP_TYPE_GENERIC_AUDIO', 'ACP_TYPE_ICE60958_AUDIO', + 'ACP_TYPE_SUPER_AUDIO_CD', 'ACrYCb16161616_10LSB', + 'ACrYCb16161616_10MSB', 'ACrYCb16161616_12LSB', + 'ACrYCb16161616_12MSB', 'ACrYCb2101010', 'ACrYCb8888', + 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', + 'AFMT_ACP_SOURCE_FROM_AZALIA', 'AFMT_ACP_TYPE', + 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', + 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', + 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', + 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', + 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', + 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', + 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', + 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', + 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', + 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', + 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', + 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', + 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', + 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', + 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', + 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', + 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS', + 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', + 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', + 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', + 'AFMT_INTERRUPT_STATUS_CHG_MASK', 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', + 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', + 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', + 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', 'AFMT_MEM_NO_FORCE_REQUEST', + 'AFMT_MEM_PWR_DIS_CTRL', 'AFMT_MEM_PWR_FORCE_CTRL', + 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', + 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', + 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE', 'ALLOW_SR_ON_TRANS_REQ', + 'ALLOW_SR_ON_TRANS_REQ_DISABLE', 'ALLOW_SR_ON_TRANS_REQ_ENABLE', + 'ALL_USE_R', 'ALPHA_DATA_ONTO_ALPHA_PORT', + 'ALPHA_DATA_ONTO_CB_B_PORT', 'ALPHA_DATA_ONTO_CR_R_PORT', + 'ALPHA_DATA_ONTO_Y_G_PORT', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'AMCLOCK_ENABLE', + 'APG_ACP_OVERRIDE', 'APG_ACP_SOURCE_NO_OVERRIDE', + 'APG_ACP_TYPE_DVD_AUDIO', 'APG_ACP_TYPE_GENERIC_AUDIO', + 'APG_ACP_TYPE_ICE60958_AUDIO', 'APG_ACP_TYPE_SUPER_AUDIO_CD', + 'APG_AUDIO_CRC_CH0_SIG', 'APG_AUDIO_CRC_CH1_SIG', + 'APG_AUDIO_CRC_CH2_SIG', 'APG_AUDIO_CRC_CH3_SIG', + 'APG_AUDIO_CRC_CH4_SIG', 'APG_AUDIO_CRC_CH5_SIG', + 'APG_AUDIO_CRC_CH6_SIG', 'APG_AUDIO_CRC_CH7_SIG', + 'APG_AUDIO_CRC_CONTINUOUS', 'APG_AUDIO_CRC_CONTROL_CH_SEL', + 'APG_AUDIO_CRC_CONTROL_CONT', 'APG_AUDIO_CRC_ONESHOT', + 'APG_AUDIO_CRC_RESERVED_10', 'APG_AUDIO_CRC_RESERVED_11', + 'APG_AUDIO_CRC_RESERVED_12', 'APG_AUDIO_CRC_RESERVED_13', + 'APG_AUDIO_CRC_RESERVED_14', 'APG_AUDIO_CRC_RESERVED_15', + 'APG_AUDIO_CRC_RESERVED_8', 'APG_AUDIO_CRC_RESERVED_9', + 'APG_DBG_ACP_TYPE', 'APG_DBG_AUDIO_DTO_BASE', + 'APG_DBG_AUDIO_DTO_DIV', 'APG_DBG_AUDIO_DTO_MULTI', + 'APG_DBG_MUX_SEL', 'APG_DEBUG_AUDIO_MODE', + 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', + 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE', + 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', + 'APG_FUNCTIONAL_MODE', 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', + 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', + 'APG_MEM_DISABLE_MEM_PWR_CTRL', 'APG_MEM_ENABLE_MEM_PWR_CTRL', + 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', + 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', 'APG_MEM_NO_FORCE_REQUEST', + 'APG_MEM_POWER_STATE', 'APG_MEM_POWER_STATE_DS', + 'APG_MEM_POWER_STATE_LS', 'APG_MEM_POWER_STATE_ON', + 'APG_MEM_POWER_STATE_SD', 'APG_MEM_PWR_DIS_CTRL', + 'APG_MEM_PWR_FORCE_CTRL', 'APG_PACKET_CONTROL_ACP_SOURCE', + 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE', 'APG_RAMP_CONTROL_SIGN', + 'APG_RAMP_SIGNED', 'APG_RAMP_UNSIGNED', 'ARGB1555', + 'ARGB16161616_10LSB', 'ARGB16161616_10MSB', 'ARGB16161616_12LSB', + 'ARGB16161616_12MSB', 'ARGB16161616_FLOAT', 'ARGB16161616_SNORM', + 'ARGB16161616_UNORM', 'ARGB2101010', 'ARGB4444', 'ARGB8888', + 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT', + 'AUTOCAL_MODE_AUTOCENTER', 'AUTOCAL_MODE_AUTOREPLICATE', + 'AUTOCAL_MODE_AUTOSCALE', 'AUTOCAL_MODE_OFF', + 'AYCrCb16161616_10LSB', 'AYCrCb16161616_10MSB', + 'AYCrCb16161616_12LSB', 'AYCrCb16161616_12MSB', 'AYCrCb8888', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', + 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', + 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', + 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', + 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', + 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', + 'AZ_RIRB_WRITE_POINTER_DO_RESET', + 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', + 'AZ_STATE_CHANGE_STATUS', + 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'BASE_RATE_44P1KHZ', + 'BASE_RATE_48KHZ', 'BGR101111_FIX', 'BGR101111_FLOAT', 'BGR565', + 'BIGK_FRAGMENT_SIZE', 'BINNER_BREAK_BATCH', 'BINNER_DROP', + 'BINNER_PIPELINE', 'BINNER_PIPELINE_BREAK', 'BINNING_ALLOWED', + 'BINNING_DISABLED', 'BINNING_ONE_PRIM_PER_BATCH', + 'BIN_CONF_OVERRIDE_CHECK', 'BIN_MAP_MODE_NONE', + 'BIN_MAP_MODE_POPS', 'BIN_MAP_MODE_RTA_INDEX', + 'BIN_SIZE_128_PIXELS', 'BIN_SIZE_256_PIXELS', + 'BIN_SIZE_32_PIXELS', 'BIN_SIZE_512_PIXELS', 'BIN_SIZE_64_PIXELS', + 'BITS_31_0', 'BITS_32_1', 'BITS_33_2', 'BITS_34_3', 'BITS_35_4', + 'BITS_36_5', 'BITS_37_6', 'BITS_38_7', 'BLEND_CONSTANT_ALPHA', + 'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', + 'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', + 'BLEND_ONE_MINUS_CONSTANT_ALPHA', + 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', + 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', + 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', + 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', + 'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLOCK_CONTEXT_DONE', 'BLUE_LUT', + 'BOTTOM_OF_PIPE_TS', 'BREAK_BATCH', 'BYPASS', 'BYPASS_EN', + 'BYPASS_POST_CSC', 'BinEventCntl', 'BinMapMode', 'BinSizeExtend', + 'BinningMode', 'BlendOp', 'BlendOpt', 'CACHE_BYPASS', + 'CACHE_FLUSH', 'CACHE_FLUSH_AND_INV_EVENT', + 'CACHE_FLUSH_AND_INV_TS_EVENT', 'CACHE_FLUSH_TS', 'CACHE_LRU_RD', + 'CACHE_LRU_WR', 'CACHE_NOA', 'CACHE_NOA_WR', 'CACHE_STREAM', + 'CACHE_STREAM_RD', 'CBMode', 'CBPerfClearFilterSel', + 'CBPerfOpFilterSel', 'CBPerfSel', 'CB_B_DATA_ONTO_ALPHA_PORT', + 'CB_B_DATA_ONTO_CB_B_PORT', 'CB_B_DATA_ONTO_CR_R_PORT', + 'CB_B_DATA_ONTO_Y_G_PORT', 'CB_DCC_DECOMPRESS', 'CB_DISABLE', + 'CB_ELIMINATE_FAST_CLEAR', 'CB_NORMAL', + 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', + 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', + 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', + 'CB_PERF_SEL_BE_CS_FILLRATE_1X2', + 'CB_PERF_SEL_BE_CS_FILLRATE_2X1', + 'CB_PERF_SEL_BE_CS_FILLRATE_2X2', 'CB_PERF_SEL_BE_RDLATFIFO_FULL', + 'CB_PERF_SEL_BE_SRCFIFO_FULL', 'CB_PERF_SEL_BLEND_CLOCK_EN', + 'CB_PERF_SEL_BLEND_COLLISION_DUE_TO_CACHE_WRITE', + 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', + 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', + 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 'CB_PERF_SEL_BLEND_RAW_HAZARD_STALL', + 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', + 'CB_PERF_SEL_BLEND_STALL_ON_CACHE_ACCESS', 'CB_PERF_SEL_BUSY', + 'CB_PERF_SEL_CCC_COLOR_RESOURCE_PANIC', + 'CB_PERF_SEL_CCC_COLOR_RESOURCE_STALL', + 'CB_PERF_SEL_CCC_FMASK_RESOURCE_PANIC', + 'CB_PERF_SEL_CCC_FMASK_RESOURCE_STALL', + 'CB_PERF_SEL_CCC_FREE_WAYS_PANIC', + 'CB_PERF_SEL_CCC_FREE_WAYS_STALL', + 'CB_PERF_SEL_CCC_IN_EVICT_HAZARD_STALL', + 'CB_PERF_SEL_CCC_SKID_FIFO_FULL', + 'CB_PERF_SEL_CCC_SKID_FIFO_STALL', + 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READY', + 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READYB', + 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READY', + 'CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READYB', + 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_DIRTY_QBLOCKS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_FLUSH', + 'CB_PERF_SEL_CC_CACHE_QBLOCKS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', + 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', + 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST', + 'CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST_IN_FLIGHT', + 'CB_PERF_SEL_CC_CRW_GLX_REQ_WRITE_REQUEST', + 'CB_PERF_SEL_CC_CRW_GLX_SRC_WRITE_CYCLES', + 'CB_PERF_SEL_CC_FDCC_COMPRESS_FRAG_TIDS_IN', + 'CB_PERF_SEL_CC_FDCC_DECOMPRESS_FRAG_TIDS_OUT', + 'CB_PERF_SEL_CC_QUADFRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_QUADFRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_QUADFRAG_VALID_READY', + 'CB_PERF_SEL_CC_QUADFRAG_VALID_READYB', 'CB_PERF_SEL_CC_TAG_HIT', + 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', + 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', + 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', + 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', + 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', 'CB_PERF_SEL_DRAWN_BUSY', + 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', + 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_EVENT', + 'CB_PERF_SEL_EVENTS_CLK_EN', + 'CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 'CB_PERF_SEL_EXPORT_ADDED_1_FRAGMENT', + 'CB_PERF_SEL_EXPORT_ADDED_2_FRAGMENTS', + 'CB_PERF_SEL_EXPORT_ADDED_3_FRAGMENTS', + 'CB_PERF_SEL_EXPORT_ADDED_4_FRAGMENTS', + 'CB_PERF_SEL_EXPORT_ADDED_5_FRAGMENTS', + 'CB_PERF_SEL_EXPORT_ADDED_6_FRAGMENTS', + 'CB_PERF_SEL_EXPORT_ADDED_7_FRAGMENTS', + 'CB_PERF_SEL_EXPORT_BLEND_OPT_BLEND_BYPASS', + 'CB_PERF_SEL_EXPORT_BLEND_OPT_DISCARD_PIXELS', + 'CB_PERF_SEL_EXPORT_BLEND_OPT_DONT_READ_DST', + 'CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_AFTER_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_BEFORE_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_EXPORT_KILLED_BY_COLOR_INVALID', + 'CB_PERF_SEL_EXPORT_KILLED_BY_DISCARD_PIXEL', + 'CB_PERF_SEL_EXPORT_KILLED_BY_NULL_SAMPLE_MASK', + 'CB_PERF_SEL_EXPORT_KILLED_BY_NULL_TARGET_SHADER_MASK', + 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_0', + 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_1', + 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_2', + 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_3', + 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_4', + 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_5', + 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_6', + 'CB_PERF_SEL_EXPORT_READS_FRAGMENT_7', + 'CB_PERF_SEL_EXPORT_REMOVED_1_FRAGMENT', + 'CB_PERF_SEL_EXPORT_REMOVED_2_FRAGMENTS', + 'CB_PERF_SEL_EXPORT_REMOVED_3_FRAGMENTS', + 'CB_PERF_SEL_EXPORT_REMOVED_4_FRAGMENTS', + 'CB_PERF_SEL_EXPORT_REMOVED_5_FRAGMENTS', + 'CB_PERF_SEL_EXPORT_REMOVED_6_FRAGMENTS', + 'CB_PERF_SEL_EXPORT_REMOVED_7_FRAGMENTS', + 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_0', + 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_1', + 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_2', + 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_3', + 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_4', + 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_5', + 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_6', + 'CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_7', + 'CB_PERF_SEL_FORMAT_IS_16_16_FLOAT_8PIX', + 'CB_PERF_SEL_FORMAT_IS_16_16_SIGNED_8PIX', + 'CB_PERF_SEL_FORMAT_IS_16_16_UNSIGNED_8PIX', + 'CB_PERF_SEL_FORMAT_IS_32BPP_8PIX', + 'CB_PERF_SEL_FORMAT_IS_32_ABGR', 'CB_PERF_SEL_FORMAT_IS_32_AR', + 'CB_PERF_SEL_FORMAT_IS_32_GR', 'CB_PERF_SEL_FORMAT_IS_32_R', + 'CB_PERF_SEL_FORMAT_IS_FP16_ABGR', + 'CB_PERF_SEL_FORMAT_IS_SIGNED16_ABGR', + 'CB_PERF_SEL_FORMAT_IS_UNSIGNED16_ABGR', + 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', + 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', + 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', + 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', + 'CB_PERF_SEL_GRBM_CLOCK_EN', 'CB_PERF_SEL_MEMARB_CLOCK_EN', + 'CB_PERF_SEL_PERFMON_CLOCK_EN', + 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', + 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', + 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', + 'CB_PERF_SEL_RDLAT_FIFO_QUAD_RESIDENCY_STALL', + 'CB_PERF_SEL_STATIC_CLOCK_EN', 'CB_RESERVED', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', + 'CHA_PERF_SEL', 'CHA_PERF_SEL_ARB_REQUESTS', 'CHA_PERF_SEL_BUSY', + 'CHA_PERF_SEL_CYCLE', 'CHA_PERF_SEL_IO_32B_WDS_CHC0', + 'CHA_PERF_SEL_IO_32B_WDS_CHC1', 'CHA_PERF_SEL_IO_32B_WDS_CHC2', + 'CHA_PERF_SEL_IO_32B_WDS_CHC3', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', 'CHA_PERF_SEL_REQUEST_CHC0', + 'CHA_PERF_SEL_REQUEST_CHC1', 'CHA_PERF_SEL_REQUEST_CHC2', + 'CHA_PERF_SEL_REQUEST_CHC3', 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', + 'CHA_PERF_SEL_STALL_CHC0', 'CHA_PERF_SEL_STALL_CHC1', + 'CHA_PERF_SEL_STALL_CHC2', 'CHA_PERF_SEL_STALL_CHC3', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', 'CHC_PERF_SEL', + 'CHC_PERF_SEL_ARB_RET_LEVEL', 'CHC_PERF_SEL_BUSY', + 'CHC_PERF_SEL_CYCLE', 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', + 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHC_PERF_SEL_REQ', + 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHC_PERF_SEL_REQ_CLIENT0', + 'CHC_PERF_SEL_REQ_CLIENT1', 'CHC_PERF_SEL_REQ_CLIENT10', + 'CHC_PERF_SEL_REQ_CLIENT11', 'CHC_PERF_SEL_REQ_CLIENT12', + 'CHC_PERF_SEL_REQ_CLIENT13', 'CHC_PERF_SEL_REQ_CLIENT14', + 'CHC_PERF_SEL_REQ_CLIENT15', 'CHC_PERF_SEL_REQ_CLIENT16', + 'CHC_PERF_SEL_REQ_CLIENT17', 'CHC_PERF_SEL_REQ_CLIENT18', + 'CHC_PERF_SEL_REQ_CLIENT19', 'CHC_PERF_SEL_REQ_CLIENT2', + 'CHC_PERF_SEL_REQ_CLIENT20', 'CHC_PERF_SEL_REQ_CLIENT21', + 'CHC_PERF_SEL_REQ_CLIENT22', 'CHC_PERF_SEL_REQ_CLIENT23', + 'CHC_PERF_SEL_REQ_CLIENT3', 'CHC_PERF_SEL_REQ_CLIENT4', + 'CHC_PERF_SEL_REQ_CLIENT5', 'CHC_PERF_SEL_REQ_CLIENT6', + 'CHC_PERF_SEL_REQ_CLIENT7', 'CHC_PERF_SEL_REQ_CLIENT8', + 'CHC_PERF_SEL_REQ_CLIENT9', 'CHC_PERF_SEL_REQ_NOP_ACK', + 'CHC_PERF_SEL_REQ_NOP_RTN0', 'CHC_PERF_SEL_REQ_READ', + 'CHC_PERF_SEL_REQ_READ_128B', 'CHC_PERF_SEL_REQ_READ_32B', + 'CHC_PERF_SEL_REQ_READ_64B', 'CHC_PERF_SEL_REQ_WRITE', + 'CHC_PERF_SEL_REQ_WRITE_32B', 'CHC_PERF_SEL_REQ_WRITE_64B', + 'CHC_PERF_SEL_STALL_BUFFER_FULL', 'CHC_PERF_SEL_STALL_GL2_GL1', + 'CHC_PERF_SEL_STARVE', 'CHUNK_SIZE', 'CHUNK_SIZE_16KB', + 'CHUNK_SIZE_1KB', 'CHUNK_SIZE_2KB', 'CHUNK_SIZE_32KB', + 'CHUNK_SIZE_4KB', 'CHUNK_SIZE_64KB', 'CHUNK_SIZE_8KB', + 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', 'CLKGATE_SM_MODE', + 'CLOCK_BRANCH_SOFT_RESET', 'CLOCK_BRANCH_SOFT_RESET_FORCE', + 'CLOCK_BRANCH_SOFT_RESET_NOOP', 'CLOCK_GATING_DISABLE', + 'CLOCK_GATING_DISABLED', 'CLOCK_GATING_DISABLED_IN_DCO', + 'CLOCK_GATING_DISABLE_ENUM', 'CLOCK_GATING_DISABLE_ENUM_DISABLED', + 'CLOCK_GATING_DISABLE_ENUM_ENABLED', 'CLOCK_GATING_EN', + 'CLOCK_GATING_ENABLE', 'CLOCK_GATING_ENABLED', + 'CLOCK_GATING_ENABLED_IN_DCO', 'CMC_3DLUT_17CUBE', + 'CMC_3DLUT_30BIT', 'CMC_3DLUT_30BIT_ENUM', 'CMC_3DLUT_36BIT', + 'CMC_3DLUT_9CUBE', 'CMC_3DLUT_RAM_SEL', 'CMC_3DLUT_SIZE_ENUM', + 'CMC_LUT_2CFG_MEMORY_A', 'CMC_LUT_2CFG_MEMORY_B', + 'CMC_LUT_2CFG_NO_MEMORY', 'CMC_LUT_2_CONFIG_ENUM', + 'CMC_LUT_2_MODE_BYPASS', 'CMC_LUT_2_MODE_ENUM', + 'CMC_LUT_2_MODE_RAMA_LUT', 'CMC_LUT_2_MODE_RAMB_LUT', + 'CMC_LUT_NUM_SEG', 'CMC_LUT_RAM_SEL', 'CMC_RAM0_ACCESS', + 'CMC_RAM1_ACCESS', 'CMC_RAM2_ACCESS', 'CMC_RAM3_ACCESS', + 'CMC_RAMA_ACCESS', 'CMC_RAMB_ACCESS', 'CMC_SEGMENTS_1', + 'CMC_SEGMENTS_128', 'CMC_SEGMENTS_16', 'CMC_SEGMENTS_2', + 'CMC_SEGMENTS_32', 'CMC_SEGMENTS_4', 'CMC_SEGMENTS_64', + 'CMC_SEGMENTS_8', 'CMPTO', 'CM_BYPASS', 'CM_COEF_FORMAT_ENUM', + 'CM_DATA_SIGNED', 'CM_DISABLE', 'CM_EN', 'CM_ENABLE', + 'CM_GAMMA_LUT_MODE_ENUM', 'CM_GAMMA_LUT_PWL_DISABLE_ENUM', + 'CM_GAMMA_LUT_SEL_ENUM', 'CM_LUT_2_CONFIG_ENUM', + 'CM_LUT_2_MODE_ENUM', 'CM_LUT_4_CONFIG_ENUM', + 'CM_LUT_4_MODE_ENUM', 'CM_LUT_CONFIG_MODE', 'CM_LUT_NUM_SEG', + 'CM_LUT_RAM_SEL', 'CM_LUT_READ_COLOR_SEL', 'CM_LUT_READ_DBG', + 'CM_NOT_PENDING', 'CM_PENDING', 'CM_POST_CSC_MODE_ENUM', + 'CM_WRITE_BASE_ONLY', 'CM_YES_PENDING', 'CNVC_ROUND', + 'CNVC_TRUNCATE', 'COEF_POST_CSC', 'COEF_POST_CSC_B', + 'COEF_RAM_SELECT_BACK', 'COEF_RAM_SELECT_CURRENT', + 'COEF_RAM_SELECT_RD', 'COLOR_24BIT_1BIT_AND', + 'COLOR_24BIT_8BIT_ALPHA_PREMULT', + 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', 'COLOR_64BIT_FP_PREMULT', + 'COLOR_64BIT_FP_UNPREMULT', 'COLOR_KEYER_ENABLE', + 'COLOR_KEYER_MODE', 'COLOR_KEY_DIS', 'COLOR_KEY_EN', + 'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', + 'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST', + 'COMPRESSION_MODE_BYPASS_COMPRESSION', + 'COMPRESSION_MODE_BYPASS_METADATA_CACHE', + 'COMPRESSION_MODE_COMPRESSION_ENABLED', + 'COMPRESSION_MODE_READ_DECOMPRESSED', + 'COMPRESSION_MODE_READ_RAW_COMPRESSED_DATA', + 'COMPRESSION_MODE_WRITE_COMPRESSION_DISABLED', + 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END', + 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START', + 'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START', + 'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', + 'CORB_READ_POINTER_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', + 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_LATENCY_STATS_SEL', + 'CPC_LATENCY_STATS_SEL_INVAL_LAST', + 'CPC_LATENCY_STATS_SEL_INVAL_MAX', + 'CPC_LATENCY_STATS_SEL_INVAL_MIN', + 'CPC_LATENCY_STATS_SEL_XACK_LAST', + 'CPC_LATENCY_STATS_SEL_XACK_MAX', + 'CPC_LATENCY_STATS_SEL_XACK_MIN', + 'CPC_LATENCY_STATS_SEL_XNACK_LAST', + 'CPC_LATENCY_STATS_SEL_XNACK_MAX', + 'CPC_LATENCY_STATS_SEL_XNACK_MIN', 'CPC_PERFCOUNT_SEL', + 'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_CPC_GCRIU_BUSY', + 'CPC_PERF_SEL_CPC_GCRIU_IDLE', 'CPC_PERF_SEL_CPC_GCRIU_STALL', + 'CPC_PERF_SEL_CPC_STAT_BUSY', 'CPC_PERF_SEL_CPC_STAT_IDLE', + 'CPC_PERF_SEL_CPC_STAT_STALL', 'CPC_PERF_SEL_CPC_TCIU_BUSY', + 'CPC_PERF_SEL_CPC_TCIU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', + 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', + 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', + 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_GUS_READ_REQUEST_SENT', + 'CPC_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_WRITE', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', + 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_WRITE', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', + 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', + 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', 'CPC_PERF_SEL_MEC_THREAD0', + 'CPC_PERF_SEL_MEC_THREAD1', 'CPC_PERF_SEL_MEC_THREAD2', + 'CPC_PERF_SEL_MEC_THREAD3', 'CPC_PERF_SEL_MES_THREAD0', + 'CPC_PERF_SEL_MES_THREAD1', + 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_TCIU_READ_REQUEST_SENT', + 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 'CPC_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', + 'CPF_LATENCY_STATS_SEL', 'CPF_LATENCY_STATS_SEL_INVAL_LAST', + 'CPF_LATENCY_STATS_SEL_INVAL_MAX', + 'CPF_LATENCY_STATS_SEL_INVAL_MIN', + 'CPF_LATENCY_STATS_SEL_READ_LAST', + 'CPF_LATENCY_STATS_SEL_READ_MAX', + 'CPF_LATENCY_STATS_SEL_READ_MIN', + 'CPF_LATENCY_STATS_SEL_XACK_LAST', + 'CPF_LATENCY_STATS_SEL_XACK_MAX', + 'CPF_LATENCY_STATS_SEL_XACK_MIN', + 'CPF_LATENCY_STATS_SEL_XNACK_LAST', + 'CPF_LATENCY_STATS_SEL_XNACK_MAX', + 'CPF_LATENCY_STATS_SEL_XNACK_MIN', 'CPF_PERFCOUNTWINDOW_SEL', + 'CPF_PERFCOUNT_SEL', 'CPF_PERFWINDOW_SEL_CSF', + 'CPF_PERFWINDOW_SEL_HQD1', 'CPF_PERFWINDOW_SEL_HQD2', + 'CPF_PERFWINDOW_SEL_RDMA', 'CPF_PERFWINDOW_SEL_RWPP', + 'CPF_PERF_SEL_ALWAYS_COUNT', + 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', + 'CPF_PERF_SEL_CPF_GCRIU_BUSY', 'CPF_PERF_SEL_CPF_GCRIU_IDLE', + 'CPF_PERF_SEL_CPF_GCRIU_STALL', 'CPF_PERF_SEL_CPF_STAT_BUSY', + 'CPF_PERF_SEL_CPF_STAT_IDLE', 'CPF_PERF_SEL_CPF_STAT_STALL', + 'CPF_PERF_SEL_CPF_TCIU_BUSY', 'CPF_PERF_SEL_CPF_TCIU_IDLE', + 'CPF_PERF_SEL_CPF_TCIU_STALL', 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', + 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', + 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', + 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', + 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', + 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', + 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', + 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', + 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', + 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 'CPF_SCRATCH_REG_ATOMIC_ADD', 'CPF_SCRATCH_REG_ATOMIC_AND', + 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', 'CPF_SCRATCH_REG_ATOMIC_MAX', + 'CPF_SCRATCH_REG_ATOMIC_MIN', 'CPF_SCRATCH_REG_ATOMIC_NOT', + 'CPF_SCRATCH_REG_ATOMIC_OP', 'CPF_SCRATCH_REG_ATOMIC_OR', + 'CPF_SCRATCH_REG_ATOMIC_SUB', 'CPF_TAG_RAM', + 'CPG_LATENCY_STATS_SEL', 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', + 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', + 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', + 'CPG_LATENCY_STATS_SEL_INVAL_LAST', + 'CPG_LATENCY_STATS_SEL_INVAL_MAX', + 'CPG_LATENCY_STATS_SEL_INVAL_MIN', + 'CPG_LATENCY_STATS_SEL_READ_LAST', + 'CPG_LATENCY_STATS_SEL_READ_MAX', + 'CPG_LATENCY_STATS_SEL_READ_MIN', + 'CPG_LATENCY_STATS_SEL_WRITE_LAST', + 'CPG_LATENCY_STATS_SEL_WRITE_MAX', + 'CPG_LATENCY_STATS_SEL_WRITE_MIN', + 'CPG_LATENCY_STATS_SEL_XACK_LAST', + 'CPG_LATENCY_STATS_SEL_XACK_MAX', + 'CPG_LATENCY_STATS_SEL_XACK_MIN', + 'CPG_LATENCY_STATS_SEL_XNACK_LAST', + 'CPG_LATENCY_STATS_SEL_XNACK_MAX', + 'CPG_LATENCY_STATS_SEL_XNACK_MIN', 'CPG_PERFCOUNTWINDOW_SEL', + 'CPG_PERFCOUNT_SEL', 'CPG_PERFWINDOW_SEL_APPEND', + 'CPG_PERFWINDOW_SEL_CE', 'CPG_PERFWINDOW_SEL_CEDMA', + 'CPG_PERFWINDOW_SEL_CPC_IC', 'CPG_PERFWINDOW_SEL_CPG_IC', + 'CPG_PERFWINDOW_SEL_DDID', 'CPG_PERFWINDOW_SEL_DFY', + 'CPG_PERFWINDOW_SEL_DMA', 'CPG_PERFWINDOW_SEL_ME', + 'CPG_PERFWINDOW_SEL_MEC1', 'CPG_PERFWINDOW_SEL_MEC2', + 'CPG_PERFWINDOW_SEL_MEMRD', 'CPG_PERFWINDOW_SEL_MEMWR', + 'CPG_PERFWINDOW_SEL_MES', 'CPG_PERFWINDOW_SEL_PFP', + 'CPG_PERFWINDOW_SEL_PQ1', 'CPG_PERFWINDOW_SEL_PQ2', + 'CPG_PERFWINDOW_SEL_PQ3', 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', + 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', 'CPG_PERFWINDOW_SEL_QURD', + 'CPG_PERFWINDOW_SEL_QU_EOP', 'CPG_PERFWINDOW_SEL_QU_PIPE', + 'CPG_PERFWINDOW_SEL_QU_STRM', 'CPG_PERFWINDOW_SEL_RB', + 'CPG_PERFWINDOW_SEL_RESERVED1', 'CPG_PERFWINDOW_SEL_RESERVED2', + 'CPG_PERFWINDOW_SEL_SHADOW', 'CPG_PERFWINDOW_SEL_SR', + 'CPG_PERFWINDOW_SEL_VGT0', 'CPG_PERFWINDOW_SEL_VGT1', + 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', 'CPG_PERF_SEL_ALWAYS_COUNT', + 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', + 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CPG_GCRIU_BUSY', + 'CPG_PERF_SEL_CPG_GCRIU_IDLE', 'CPG_PERF_SEL_CPG_GCRIU_STALL', + 'CPG_PERF_SEL_CPG_STAT_BUSY', 'CPG_PERF_SEL_CPG_STAT_IDLE', + 'CPG_PERF_SEL_CPG_STAT_STALL', 'CPG_PERF_SEL_CPG_TCIU_BUSY', + 'CPG_PERF_SEL_CPG_TCIU_IDLE', 'CPG_PERF_SEL_CPG_TCIU_STALL', + 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', + 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', + 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', + 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_DMA_BUSY', + 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', + 'CPG_PERF_SEL_DMA_STALLED', 'CPG_PERF_SEL_DMA_STARVED', + 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', + 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', 'CPG_PERF_SEL_ME_PARSER_BUSY', + 'CPG_PERF_SEL_ME_PWS_STALLED0', 'CPG_PERF_SEL_ME_PWS_STALLED1', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', + 'CPG_PERF_SEL_PFP_PWS_STALLED0', 'CPG_PERF_SEL_PFP_PWS_STALLED1', + 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 'CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL0', + 'CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL1', + 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS0', + 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS1', + 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS0', + 'CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS1', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', + 'CP_ALPHA_TAG_RAM_SEL', 'CP_DDID_CNTL_MODE', 'CP_DDID_CNTL_SIZE', + 'CP_DDID_CNTL_VMID_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE', + 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', + 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', + 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', + 'CRC_CUR_0', 'CRC_CUR_1', 'CRC_CUR_SEL', 'CRC_INTERLACE_0', + 'CRC_INTERLACE_1', 'CRC_INTERLACE_2', 'CRC_INTERLACE_3', + 'CRC_INTERLACE_SEL', 'CRC_IN_PIX_0', 'CRC_IN_PIX_1', + 'CRC_IN_PIX_2', 'CRC_IN_PIX_3', 'CRC_IN_PIX_4', 'CRC_IN_PIX_5', + 'CRC_IN_PIX_6', 'CRC_IN_PIX_7', 'CRC_IN_PIX_SEL', 'CRC_SRC_0', + 'CRC_SRC_1', 'CRC_SRC_2', 'CRC_SRC_3', 'CRC_SRC_SEL', + 'CRC_STEREO_0', 'CRC_STEREO_1', 'CRC_STEREO_2', 'CRC_STEREO_3', + 'CRC_STEREO_SEL', 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', + 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'CROB_MEM_PWR_LIGHT_SLEEP_MODE', 'CROSSBAR_FOR_ALPHA', + 'CROSSBAR_FOR_CB_B', 'CROSSBAR_FOR_CR_R', 'CROSSBAR_FOR_Y_G', + 'CRS', 'CR_R_DATA_ONTO_ALPHA_PORT', 'CR_R_DATA_ONTO_CB_B_PORT', + 'CR_R_DATA_ONTO_CR_R_PORT', 'CR_R_DATA_ONTO_Y_G_PORT', + 'CSCNTL_ADDR_WIDTH', 'CSCNTL_DATA_WIDTH', 'CSCNTL_TYPE', + 'CSCNTL_TYPE_EVENT', 'CSCNTL_TYPE_PRIVATE', 'CSCNTL_TYPE_STATE', + 'CSCNTL_TYPE_TG', 'CSCNTL_TYPE_WIDTH', 'CSDATA_ADDR_WIDTH', + 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT', + 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG', + 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_NA', + 'CS_PARTIAL_FLUSH', 'CURSOR_2X_MAGNIFY', + 'CURSOR_2X_MAGNIFY_IS_DISABLE', 'CURSOR_2X_MAGNIFY_IS_ENABLE', + 'CURSOR_COLOR_24BIT_1BIT_AND', + 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', + 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 'CURSOR_COLOR_64BIT_FP_PREMULT', + 'CURSOR_COLOR_64BIT_FP_UNPREMULT', 'CURSOR_ENABLE', + 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', + 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', 'CURSOR_IS_DISABLE', + 'CURSOR_IS_ENABLE', 'CURSOR_IS_NOT_SNOOP', 'CURSOR_IS_SNOOP', + 'CURSOR_LINES_PER_CHUNK', 'CURSOR_LINE_PER_CHUNK_1', + 'CURSOR_LINE_PER_CHUNK_16', 'CURSOR_LINE_PER_CHUNK_2', + 'CURSOR_LINE_PER_CHUNK_4', 'CURSOR_LINE_PER_CHUNK_8', + 'CURSOR_MODE', 'CURSOR_MONO_2BIT', + 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', + 'CURSOR_PERFMON_LATENCY_MEASURE_EN', + 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', + 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', + 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', + 'CURSOR_PERFMON_LATENCY_MEASURE_SEL', 'CURSOR_PITCH', + 'CURSOR_PITCH_128_PIXELS', 'CURSOR_PITCH_256_PIXELS', + 'CURSOR_PITCH_64_PIXELS', 'CURSOR_REQUEST_EARLY', + 'CURSOR_REQUEST_NORMALLY', 'CURSOR_REQ_MODE', 'CURSOR_SNOOP', + 'CURSOR_STEREO_EN', 'CURSOR_STEREO_IS_DISABLED', + 'CURSOR_STEREO_IS_ENABLED', 'CURSOR_SURFACE_IS_NOT_TMZ', + 'CURSOR_SURFACE_IS_TMZ', 'CURSOR_SURFACE_TMZ', 'CURSOR_SYSTEM', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', + 'CUR_CLAMP_DIS', 'CUR_CLAMP_EN', 'CUR_DIS', + 'CUR_DYNAMIC_EXPANSION', 'CUR_EN', 'CUR_ENABLE', + 'CUR_EXPAND_MODE', 'CUR_FP_NO_ROM', 'CUR_FP_USE_ROM', + 'CUR_INV_CLAMP', 'CUR_MATRIX_COEF_FORMAT_ENUM', + 'CUR_MATRIX_FIX_S2_13', 'CUR_MATRIX_FIX_S3_12', 'CUR_MODE', + 'CUR_NOT_PENDING', 'CUR_PENDING', 'CUR_ROM_EN', 'CUR_YES_PENDING', + 'CUR_ZERO_EXPANSION', 'CbYCrY10101010_422_PACKED', + 'CbYCrY12121212_422_PACKED', 'CbYCrY8888_422_PACKED', 'CombFunc', + 'CompareFrag', 'ConservativeZExport', 'CovToShaderSel', + 'CrYCbA1010102', 'CrYCbA16161616_10LSB', 'CrYCbA16161616_10MSB', + 'CrYCbA16161616_12LSB', 'CrYCbA16161616_12MSB', 'CrYCbA8888', + 'CrYCbY10101010_422_PACKED', 'CrYCbY12121212_422_PACKED', + 'CrYCbY8888_422_PACKED', 'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA', + 'DAC_MUX_SELECT_DACB', 'DB_BYPASS', 'DB_BYPASS_WR_DISABLE', + 'DB_CACHE_FLUSH_AND_INV', 'DB_COMP_WR_DISABLE', 'DB_DEFAULT', + 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 'DB_PERF_SEL_CB_DB_rdreq_sends', + 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 'DB_PERF_SEL_CB_DB_wrreq_sends', + 'DB_PERF_SEL_DB_CB_context_dones', 'DB_PERF_SEL_DB_CB_eop_dones', + 'DB_PERF_SEL_DB_CB_export_busy', + 'DB_PERF_SEL_DB_CB_export_double_format', + 'DB_PERF_SEL_DB_CB_export_events', + 'DB_PERF_SEL_DB_CB_export_export_quads', + 'DB_PERF_SEL_DB_CB_export_fast_format', + 'DB_PERF_SEL_DB_CB_export_fmt_16_16_float_8pix', + 'DB_PERF_SEL_DB_CB_export_fmt_16_16_signed_8pix', + 'DB_PERF_SEL_DB_CB_export_fmt_16_16_unsigned_8pix', + 'DB_PERF_SEL_DB_CB_export_fmt_32bpp_8pix', + 'DB_PERF_SEL_DB_CB_export_is_event_BOTTOM_OF_PIPE_TS', + 'DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', + 'DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_DB_DATA_TS', + 'DB_PERF_SEL_DB_CB_export_num_pixels_need_blending', + 'DB_PERF_SEL_DB_CB_export_quads', + 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x1', + 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x2', + 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x1', + 'DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x2', + 'DB_PERF_SEL_DB_CB_export_sends', + 'DB_PERF_SEL_DB_CB_export_slow_format', + 'DB_PERF_SEL_DB_CB_export_stalls', + 'DB_PERF_SEL_DB_CB_export_waiting_for_perfcounter_stop_event', + 'DB_PERF_SEL_DB_CB_rdret_ack', 'DB_PERF_SEL_DB_CB_rdret_nack', + 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', + 'DB_PERF_SEL_DB_SC_c_tile_rate', 'DB_PERF_SEL_DB_SC_quad_busy', + 'DB_PERF_SEL_DB_SC_quad_conflicts', + 'DB_PERF_SEL_DB_SC_quad_double_quad', + 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', + 'DB_PERF_SEL_DB_SC_quad_lit_quad', + 'DB_PERF_SEL_DB_SC_quad_noz_tiles', + 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', + 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', + 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', + 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', + 'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls', + 'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_s_tile_rate', + 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', + 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', + 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 'DB_PERF_SEL_DB_SC_tile_stalls', + 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DB_SC_wave_busy', + 'DB_PERF_SEL_DB_SC_wave_conflict', + 'DB_PERF_SEL_DB_SC_wave_hard_conflict', + 'DB_PERF_SEL_DB_SC_wave_id_wrapped', + 'DB_PERF_SEL_DB_SC_wave_sends', 'DB_PERF_SEL_DB_SC_wave_stalls', + 'DB_PERF_SEL_DB_SC_z_tile_rate', + 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 'DB_PERF_SEL_Depth_Tile_Cache_event', + 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', + 'DB_PERF_SEL_OREO_Events_delayed', 'DB_PERF_SEL_OREO_Events_load', + 'DB_PERF_SEL_OREO_Events_non_transition', + 'DB_PERF_SEL_OREO_Events_stalls', + 'DB_PERF_SEL_OREO_Events_transition', + 'DB_PERF_SEL_OREO_SB_evicts', 'DB_PERF_SEL_OREO_SB_hits', + 'DB_PERF_SEL_OREO_SB_misses', 'DB_PERF_SEL_OREO_SB_stalls', + 'DB_PERF_SEL_OREO_ST_load', 'DB_PERF_SEL_OREO_ST_read', + 'DB_PERF_SEL_OREO_ST_stalls', 'DB_PERF_SEL_OREO_TT_load', + 'DB_PERF_SEL_OREO_TT_read', 'DB_PERF_SEL_OREO_TT_stalls', + 'DB_PERF_SEL_OREO_WT_load', 'DB_PERF_SEL_OREO_WT_read', + 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', + 'DB_PERF_SEL_Plane_Cache_flushes', + 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', + 'DB_PERF_SEL_Plane_Cache_misses', + 'DB_PERF_SEL_Plane_Cache_starves', + 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 'DB_PERF_SEL_PostZ_Samples_failing_S', + 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 'DB_PERF_SEL_PreZ_Samples_failing_S', + 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 'DB_PERF_SEL_RMI_rd_s_32byte_req', + 'DB_PERF_SEL_RMI_rd_s_32byte_ret', + 'DB_PERF_SEL_RMI_rd_tile_32byte_req', + 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', + 'DB_PERF_SEL_RMI_rd_z_32byte_req', + 'DB_PERF_SEL_RMI_rd_z_32byte_ret', + 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', + 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', + 'DB_PERF_SEL_RMI_wr_s_32byte_ack', + 'DB_PERF_SEL_RMI_wr_s_32byte_req', + 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', + 'DB_PERF_SEL_RMI_wr_tile_32byte_req', + 'DB_PERF_SEL_RMI_wr_z_32byte_ack', + 'DB_PERF_SEL_RMI_wr_z_32byte_req', 'DB_PERF_SEL_SC_DB_quad_busy', + 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_quads', + 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', + 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', + 'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads', + 'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_quad_vrs_1x1', + 'DB_PERF_SEL_SC_DB_quad_vrs_1x2', + 'DB_PERF_SEL_SC_DB_quad_vrs_2x1', + 'DB_PERF_SEL_SC_DB_quad_vrs_2x2', + 'DB_PERF_SEL_SC_DB_quad_vrs_2x_ssaa', + 'DB_PERF_SEL_SC_DB_quad_vrs_4x_ssaa', + 'DB_PERF_SEL_SC_DB_quad_vrs_8x_ssaa', + 'DB_PERF_SEL_SC_DB_tile_backface', 'DB_PERF_SEL_SC_DB_tile_busy', + 'DB_PERF_SEL_SC_DB_tile_covered', 'DB_PERF_SEL_SC_DB_tile_events', + 'DB_PERF_SEL_SC_DB_tile_sends', 'DB_PERF_SEL_SC_DB_tile_stalls', + 'DB_PERF_SEL_SC_DB_tile_tiles', + 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', + 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', + 'DB_PERF_SEL_SC_DB_wave_busy', + 'DB_PERF_SEL_SC_DB_wave_id_wrapped', + 'DB_PERF_SEL_SC_DB_wave_quads', 'DB_PERF_SEL_SC_DB_wave_sends', + 'DB_PERF_SEL_SH_quads_outstanding_sum', + 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', + 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', + 'DB_PERF_SEL_SX_DB_quad_busy', + 'DB_PERF_SEL_SX_DB_quad_double_format', + 'DB_PERF_SEL_SX_DB_quad_export_quads', + 'DB_PERF_SEL_SX_DB_quad_exports', + 'DB_PERF_SEL_SX_DB_quad_fast_format', + 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', + 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', + 'DB_PERF_SEL_SX_DB_quad_sends', + 'DB_PERF_SEL_SX_DB_quad_slow_format', + 'DB_PERF_SEL_SX_DB_quad_stalls', 'DB_PERF_SEL_SX_DB_quad_waves', + 'DB_PERF_SEL_Stencil_Cache_flushes', + 'DB_PERF_SEL_Stencil_Cache_frees', + 'DB_PERF_SEL_Stencil_Cache_hits', + 'DB_PERF_SEL_Stencil_Cache_misses', + 'DB_PERF_SEL_Stencil_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', + 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_surface_stall', + 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 'DB_PERF_SEL_Z_Cache_pmask_hits', + 'DB_PERF_SEL_Z_Cache_pmask_misses', + 'DB_PERF_SEL_Z_Cache_pmask_starves', + 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 'DB_PERF_SEL_clock_main_active', + 'DB_PERF_SEL_clock_mem_export_active', + 'DB_PERF_SEL_clock_reg_active', + 'DB_PERF_SEL_cs_events_pws_enable', + 'DB_PERF_SEL_depth_bounds_tile_culled', 'DB_PERF_SEL_di_dt_stall', + 'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends', + 'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy', + 'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends', + 'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile', + 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', + 'DB_PERF_SEL_dtt_sm_slot_stall', + 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', + 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', + 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_src_in_sends', + 'DB_PERF_SEL_esr_ps_src_in_squads', + 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_stall', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_ps_vic_busy', + 'DB_PERF_SEL_esr_ps_vic_stall', + 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', + 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', + 'DB_PERF_SEL_esr_psi_vic_tile_rate', + 'DB_PERF_SEL_esr_sqq_zi_busy', 'DB_PERF_SEL_esr_sqq_zi_stall', + 'DB_PERF_SEL_esr_vic_footprint_match_1x2', + 'DB_PERF_SEL_esr_vic_footprint_match_2x1', + 'DB_PERF_SEL_esr_vic_footprint_match_2x2', + 'DB_PERF_SEL_esr_vic_sqq_busy', 'DB_PERF_SEL_esr_vic_sqq_stall', + 'DB_PERF_SEL_etr_out_busy', 'DB_PERF_SEL_etr_out_esr_stall', + 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', + 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', + 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', + 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', + 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', + 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', + 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', + 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', + 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', + 'DB_PERF_SEL_flush_compressed_stencil', + 'DB_PERF_SEL_flush_expanded_stencil', + 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', + 'DB_PERF_SEL_flush_single_stencil', + 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', + 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', + 'DB_PERF_SEL_his_tile_culled', 'DB_PERF_SEL_hiz_tc_read_starved', + 'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_hiz_tile_culled', + 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', + 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', + 'DB_PERF_SEL_noz_waiting_for_postz_done', + 'DB_PERF_SEL_planes_flushed', + 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', + 'DB_PERF_SEL_postzl_full_launch', + 'DB_PERF_SEL_postzl_partial_launch', + 'DB_PERF_SEL_postzl_partial_waiting', + 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', + 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', + 'DB_PERF_SEL_postzl_src_in_sends', + 'DB_PERF_SEL_postzl_src_in_squads', + 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 'DB_PERF_SEL_postzl_src_in_stall', + 'DB_PERF_SEL_postzl_src_in_tile_rate', + 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_postzl_src_out_stall', + 'DB_PERF_SEL_postzl_tile_init_stall', + 'DB_PERF_SEL_postzl_tile_mem_stall', + 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', + 'DB_PERF_SEL_prezl_src_in_sends', + 'DB_PERF_SEL_prezl_src_in_squads', + 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 'DB_PERF_SEL_prezl_src_in_stall', + 'DB_PERF_SEL_prezl_src_in_tile_rate', + 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_prezl_src_out_stall', + 'DB_PERF_SEL_prezl_tile_init_stall', + 'DB_PERF_SEL_prezl_tile_mem_stall', + 'DB_PERF_SEL_ps_events_pws_enable', + 'DB_PERF_SEL_pws_liveness_stall_dtt_tag', + 'DB_PERF_SEL_pws_liveness_stall_tcp_cache_mgr', + 'DB_PERF_SEL_pws_stall', 'DB_PERF_SEL_qc_busy', + 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', + 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', + 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', + 'DB_PERF_SEL_quad_rd_mi_stall', + 'DB_PERF_SEL_quad_rd_mi_stall_unc', 'DB_PERF_SEL_quad_rd_panic', + 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', + 'DB_PERF_SEL_quad_rd_sends_unc', 'DB_PERF_SEL_quad_rd_tag_stall', + 'DB_PERF_SEL_quad_rdret_busy', 'DB_PERF_SEL_quad_rdret_sends', + 'DB_PERF_SEL_quad_wr_acks', 'DB_PERF_SEL_quad_wr_busy', + 'DB_PERF_SEL_quad_wr_coherency_stall', + 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', + 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', + 'DB_PERF_SEL_tcp_dispatcher_flushes', + 'DB_PERF_SEL_tcp_dispatcher_reads', + 'DB_PERF_SEL_tcp_prefetcher_flushes', + 'DB_PERF_SEL_tcp_prefetcher_reads', + 'DB_PERF_SEL_tcp_preloader_flushes', + 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', + 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', + 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 'DB_PERF_SEL_tiles_decomp_on_expclear', + 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', + 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', + 'DB_PERF_SEL_tl_expand_squads', + 'DB_PERF_SEL_tl_flush_expand_squads', + 'DB_PERF_SEL_tl_in_fast_z_stall', + 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', + 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', + 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', + 'DB_PERF_SEL_tl_preZ_squads', + 'DB_PERF_SEL_tl_stencil_locked_stall', + 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', + 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', + 'DB_PERF_SEL_tl_z_fetch_stall', + 'DB_PERF_SEL_ts_events_pws_enable', + 'DB_PERF_SEL_ts_tc_update_stall', + 'DB_PERF_SEL_tsc_insert_summarize_stall', + 'DB_PERF_SEL_unmapped_z_tile_culled', + 'DB_PERF_SEL_zf_plane_multicycle', 'DCCG_AUDIO_DTO0_SOURCE_SEL', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', + 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', 'DCCG_AUDIO_DTO_SEL', + 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', + 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 'DCCG_AUDIO_DTO_USE_512FBR_DTO', + 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL', + 'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON', + 'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE', + 'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL', + 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', + 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', + 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', + 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', + 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', + 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_MODE_HSYNC', + 'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START', + 'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP', + 'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_OTG_SELECT', + 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', + 'DCCG_PERF_SEL_OTG0', 'DCCG_PERF_SEL_OTG1', 'DCCG_PERF_SEL_OTG2', + 'DCCG_PERF_SEL_OTG3', 'DCCG_PERF_SEL_RESERVED', + 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', + 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE', + 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', + 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', + 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', + 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', + 'DCHUBBUB_MEM_POWER_MODE_OFF', + 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', 'DCHUBBUB_MEM_PWR_DIS_MODE', + 'DCHUBBUB_MEM_PWR_MODE', 'DCIOCHIP_AUX_ALL_PWR_OK', + 'DCIOCHIP_AUX_ALL_PWR_OK_0', 'DCIOCHIP_AUX_ALL_PWR_OK_1', + 'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1', + 'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0', + 'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1', + 'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_HYS_TUNE', + 'DCIOCHIP_AUX_HYS_TUNE_0', 'DCIOCHIP_AUX_HYS_TUNE_1', + 'DCIOCHIP_AUX_HYS_TUNE_2', 'DCIOCHIP_AUX_HYS_TUNE_3', + 'DCIOCHIP_AUX_RECEIVER_SEL', 'DCIOCHIP_AUX_RECEIVER_SEL_0', + 'DCIOCHIP_AUX_RECEIVER_SEL_1', 'DCIOCHIP_AUX_RECEIVER_SEL_2', + 'DCIOCHIP_AUX_RECEIVER_SEL_3', 'DCIOCHIP_AUX_RSEL0P9', + 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', + 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', + 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', + 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', + 'DCIOCHIP_AUX_VOD_TUNE', 'DCIOCHIP_AUX_VOD_TUNE_0', + 'DCIOCHIP_AUX_VOD_TUNE_1', 'DCIOCHIP_AUX_VOD_TUNE_2', + 'DCIOCHIP_AUX_VOD_TUNE_3', 'DCIOCHIP_GPIO_MASK_EN', + 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', + 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', + 'DCIOCHIP_I2C_COMPSEL', 'DCIOCHIP_I2C_FALLSLEWSEL', + 'DCIOCHIP_I2C_FALLSLEWSEL_00', 'DCIOCHIP_I2C_FALLSLEWSEL_01', + 'DCIOCHIP_I2C_FALLSLEWSEL_10', 'DCIOCHIP_I2C_FALLSLEWSEL_11', + 'DCIOCHIP_I2C_RECEIVER_SEL', 'DCIOCHIP_I2C_RECEIVER_SEL_0', + 'DCIOCHIP_I2C_RECEIVER_SEL_1', 'DCIOCHIP_I2C_RECEIVER_SEL_2', + 'DCIOCHIP_I2C_RECEIVER_SEL_3', 'DCIOCHIP_I2C_REC_COMPARATOR', + 'DCIOCHIP_I2C_REC_SCHMIT', 'DCIOCHIP_I2C_VPH_1V2_EN', + 'DCIOCHIP_I2C_VPH_1V2_EN_0', 'DCIOCHIP_I2C_VPH_1V2_EN_1', + 'DCIOCHIP_INVERT', 'DCIOCHIP_MASK', 'DCIOCHIP_MASK_DISABLE', + 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', + 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', + 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', + 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', + 'DCIOCHIP_REF_27_SRC_SEL', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', + 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', + 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', + 'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', + 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', + 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', + 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', + 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', + 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', + 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL', + 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', + 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', + 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', 'DCIO_DCRXPHY_SOFT_RESET', + 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', + 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', 'DCIO_DC_GENERICA_SEL', + 'DCIO_DC_GENERICB_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', + 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE', + 'DCIO_DC_GPU_TIMER_READ_SELECT', + 'DCIO_DC_GPU_TIMER_START_POSITION', + 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', + 'DCIO_DIO_EXT_VSYNC_MASK', 'DCIO_DIO_OTG_EXT_VSYNC_MUX', + 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', + 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', + 'DCIO_DPCS_INTERRUPT_TYPE', + 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', + 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', + 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_EXT_VSYNC_MASK_NONE', + 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', 'DCIO_EXT_VSYNC_MASK_PIPE0', + 'DCIO_EXT_VSYNC_MASK_PIPE1', 'DCIO_EXT_VSYNC_MASK_PIPE2', + 'DCIO_EXT_VSYNC_MASK_PIPE3', 'DCIO_EXT_VSYNC_MASK_PIPE4', + 'DCIO_EXT_VSYNC_MASK_PIPE5', 'DCIO_EXT_VSYNC_MUX_GENERICB', + 'DCIO_EXT_VSYNC_MUX_OTG0', 'DCIO_EXT_VSYNC_MUX_OTG1', + 'DCIO_EXT_VSYNC_MUX_OTG2', 'DCIO_EXT_VSYNC_MUX_OTG3', + 'DCIO_EXT_VSYNC_MUX_OTG4', 'DCIO_EXT_VSYNC_MUX_OTG5', + 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', 'DCIO_GENERICA_SEL_GENERICA_DCCG', + 'DCIO_GENERICA_SEL_STEREOSYNC', 'DCIO_GENERICA_SEL_SYNCEN', + 'DCIO_GENERICB_SEL_GENERICB_DCCG', 'DCIO_GENERICB_SEL_STEREOSYNC', + 'DCIO_GENERICB_SEL_SYNCEN', 'DCIO_GENLK_CLK_GSL_MASK', + 'DCIO_GENLK_CLK_GSL_MASK_NO', 'DCIO_GENLK_CLK_GSL_MASK_STEREO', + 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', + 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', + 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', + 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', + 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', + 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', + 'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', + 'DCIO_GSL_SEL_GROUP_2', 'DCIO_PHY_HPO_ENC_SRC_SEL', + 'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO', + 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', + 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', + 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SOCCLK', + 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', + 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', + 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', + 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', + 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', + 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', + 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', + 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', + 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', + 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', + 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', + 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX1', + 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX2', + 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX3', + 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX4', + 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX5', + 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX6', + 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_P', + 'DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_R', + 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK0', + 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK1', + 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK2', + 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK3', + 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK4', + 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK5', + 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK6', + 'DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK7', + 'DCOH_TEST_CLOCK_MUX_SELECT_ENUM', + 'DCOH_TEST_CLOCK_MUX_SELECT_PHYASYMCLK', + 'DCOH_TEST_CLOCK_MUX_SELECT_PHYBSYMCLK', + 'DCOH_TEST_CLOCK_MUX_SELECT_PHYCSYMCLK', + 'DCOH_TEST_CLOCK_MUX_SELECT_PHYDSYMCLK', + 'DCOH_TEST_CLOCK_MUX_SELECT_PHYESYMCLK', + 'DCOH_TEST_CLOCK_MUX_SELECT_PHYFSYMCLK', + 'DCOH_TEST_CLOCK_MUX_SELECT_PHYGSYMCLK', + 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX1', + 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX2', + 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX3', + 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX4', + 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX5', + 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX6', + 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_P', + 'DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_R', + 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM', + 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_DISABLED', + 'DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_ENABLED', + 'DCOH_TOP_ENABLE_ENUM', 'DCOH_TOP_ENABLE_ENUM_DISABLED', + 'DCOH_TOP_ENABLE_ENUM_ENABLED', 'DC_DMCUB_INT_TYPE', + 'DC_DMCUB_TIMER_WINDOW', 'DC_MEM_GLOBAL_PWR_REQ_DIS', + 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 'DC_SMU_INTERRUPT_ENABLE', 'DDID_VMID_CNTL', 'DDID_VMID_PIPE', + 'DECERR', 'DENORM_TRUNCATE', 'DETILE_BUFFER_PACKER_ENABLE', + 'DETILE_BUFFER_PACKER_IS_DISABLE', + 'DETILE_BUFFER_PACKER_IS_ENABLE', 'DFQ_MIN_FREE_ENTRIES', + 'DFQ_MIN_FREE_ENTRIES_0', 'DFQ_MIN_FREE_ENTRIES_1', + 'DFQ_MIN_FREE_ENTRIES_2', 'DFQ_MIN_FREE_ENTRIES_3', + 'DFQ_MIN_FREE_ENTRIES_4', 'DFQ_MIN_FREE_ENTRIES_5', + 'DFQ_MIN_FREE_ENTRIES_6', 'DFQ_MIN_FREE_ENTRIES_7', + 'DFQ_NUM_ENTRIES', 'DFQ_NUM_ENTRIES_0', 'DFQ_NUM_ENTRIES_1', + 'DFQ_NUM_ENTRIES_2', 'DFQ_NUM_ENTRIES_3', 'DFQ_NUM_ENTRIES_4', + 'DFQ_NUM_ENTRIES_5', 'DFQ_NUM_ENTRIES_6', 'DFQ_NUM_ENTRIES_7', + 'DFQ_NUM_ENTRIES_8', 'DFQ_SIZE', 'DFQ_SIZE_0', 'DFQ_SIZE_1', + 'DFQ_SIZE_2', 'DFQ_SIZE_3', 'DFQ_SIZE_4', 'DFQ_SIZE_5', + 'DFQ_SIZE_6', 'DFQ_SIZE_7', 'DIFFERENT_RGB', + 'DIG_10BIT_TEST_PATTERN', 'DIG_ALTERNATING_TEST_PATTERN', + 'DIG_BE_CNTL_HPD1', 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', + 'DIG_BE_CNTL_HPD4', 'DIG_BE_CNTL_HPD_SELECT', 'DIG_BE_CNTL_MODE', + 'DIG_BE_CNTL_NO_HPD', 'DIG_BE_DP_MST_MODE', 'DIG_BE_DP_SST_MODE', + 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', 'DIG_BE_RESERVED3', + 'DIG_BE_RESERVED4', 'DIG_BE_TMDS_DVI_MODE', + 'DIG_BE_TMDS_HDMI_MODE', 'DIG_DIGITAL_BYPASS_ENABLE', + 'DIG_DIGITAL_BYPASS_OFF', 'DIG_DIGITAL_BYPASS_ON', + 'DIG_DIGITAL_BYPASS_SEL', 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', + 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', + 'DIG_DIGITAL_BYPASS_SEL_36BPP', + 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', + 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', + 'DIG_DIGITAL_BYPASS_SEL_ALPHA', 'DIG_DIGITAL_BYPASS_SEL_BYPASS', + 'DIG_FE_CNTL_SOURCE_SELECT', 'DIG_FE_CNTL_STEREOSYNC_SELECT', + 'DIG_FE_SOURCE_FROM_OTG0', 'DIG_FE_SOURCE_FROM_OTG1', + 'DIG_FE_SOURCE_FROM_OTG2', 'DIG_FE_SOURCE_FROM_OTG3', + 'DIG_FE_SOURCE_RESERVED', 'DIG_FE_STEREOSYNC_FROM_OTG0', + 'DIG_FE_STEREOSYNC_FROM_OTG1', 'DIG_FE_STEREOSYNC_FROM_OTG2', + 'DIG_FE_STEREOSYNC_FROM_OTG3', 'DIG_FE_STEREOSYNC_RESERVED', + 'DIG_FIFO_1_PIX_PER_CYCLE', 'DIG_FIFO_2_PIX_PER_CYCLE', + 'DIG_FIFO_4_PIX_PER_CYCLE', 'DIG_FIFO_8_PIX_PER_CYCLE', + 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL', + 'DIG_FIFO_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', + 'DIG_FIFO_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_NO_ERROR_OCCURRED', + 'DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE', 'DIG_FIFO_OVERFLOW_OCCURRED', + 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR', 'DIG_FIFO_READ_CLOCK_SRC', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', + 'DIG_FIFO_UNDERFLOW_OCCURRED', 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', + 'DIG_FIFO_USE_OVERWRITE_LEVEL', 'DIG_IN_DEBUG_MODE', + 'DIG_IN_NORMAL_OPERATION', 'DIG_MODE', + 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', 'DIG_OUTPUT_CRC_DATA_SEL', + 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', 'DIG_OUTPUT_CRC_FOR_AUDIO', + 'DIG_OUTPUT_CRC_FOR_FULLFRAME', 'DIG_OUTPUT_CRC_FOR_VBI', + 'DIG_OUTPUT_CRC_ON_LINK0', 'DIG_OUTPUT_CRC_ON_LINK1', + 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', + 'DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET', + 'DIG_STREAM_MAPPER_LINK0', 'DIG_STREAM_MAPPER_LINK1', + 'DIG_STREAM_MAPPER_LINK2', 'DIG_STREAM_MAPPER_LINK3', + 'DIG_STREAM_MAPPER_LINK6', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', + 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', + 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DIG_UPDATE_EYE_SEL_BOTH', + 'DIG_UPDATE_EYE_SEL_LEFT', 'DIG_UPDATE_EYE_SEL_RIGHT', + 'DIG_UPDATE_FIELD_SEL_BOTH', 'DIG_UPDATE_FIELD_SEL_BOTTOM', + 'DIG_UPDATE_FIELD_SEL_RESERVED', 'DIG_UPDATE_FIELD_SEL_TOP', + 'DIOMEM_DISABLE_MEM_PWR_CTRL', 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', + 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', + 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', + 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', + 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', 'DIOMEM_ENABLE_MEM_PWR_CTRL', + 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', + 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', + 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', 'DIOMEM_NO_FORCE_REQ', + 'DIOMEM_NO_FORCE_REQUEST', 'DIOMEM_PWR_DIS_CTRL', + 'DIOMEM_PWR_FORCE_CTRL', 'DIOMEM_PWR_FORCE_CTRL2', + 'DIOMEM_PWR_SEL_CTRL', 'DIOMEM_PWR_SEL_CTRL2', + 'DIO_CLOCK_GATING_DIS', 'DIO_CLOCK_GATING_DISABLE', + 'DIO_CLOCK_GATING_EN', 'DIO_DBG_BLOCK_SEL', + 'DIO_DBG_BLOCK_SEL_AUX0', 'DIO_DBG_BLOCK_SEL_AUX1', + 'DIO_DBG_BLOCK_SEL_AUX2', 'DIO_DBG_BLOCK_SEL_AUX3', + 'DIO_DBG_BLOCK_SEL_DIGA', 'DIO_DBG_BLOCK_SEL_DIGB', + 'DIO_DBG_BLOCK_SEL_DIGC', 'DIO_DBG_BLOCK_SEL_DIGD', + 'DIO_DBG_BLOCK_SEL_DIGFE_A', 'DIO_DBG_BLOCK_SEL_DIGFE_B', + 'DIO_DBG_BLOCK_SEL_DIGFE_C', 'DIO_DBG_BLOCK_SEL_DIGFE_D', + 'DIO_DBG_BLOCK_SEL_DIO', 'DIO_DBG_BLOCK_SEL_DPA', + 'DIO_DBG_BLOCK_SEL_DPB', 'DIO_DBG_BLOCK_SEL_DPC', + 'DIO_DBG_BLOCK_SEL_DPD', 'DIO_DBG_BLOCK_SEL_DPFE_A', + 'DIO_DBG_BLOCK_SEL_DPFE_B', 'DIO_DBG_BLOCK_SEL_DPFE_C', + 'DIO_DBG_BLOCK_SEL_DPFE_D', 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', + 'DIO_DBG_BLOCK_SEL_RESERVED', 'DIO_FIFO_ERROR', + 'DIO_FIFO_ERROR_00', 'DIO_FIFO_ERROR_01', 'DIO_FIFO_ERROR_10', + 'DIO_FIFO_ERROR_11', + 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE', + 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', 'DISABLE_CLOCK_GATING', + 'DISABLE_CLOCK_GATING_IN_DCO', 'DISABLE_DEBUG', + 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', 'DISABLE_PWL', + 'DISABLE_TF0_OPT', 'DISABLE_TF1_OPT', 'DISABLE_THE_FEATURE', + 'DISABLE_THE_INTERRUPT', 'DISPCLK_CHG_FWD_CORR_DISABLE', + 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', + 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', + 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DIVISOR_BY1', + 'DIVISOR_BY2_RESERVED', 'DIVISOR_BY3', 'DIVISOR_BY4_RESERVED', + 'DIVISOR_BY5_RESERVED', 'DIVISOR_BY6_RESERVED', + 'DIVISOR_BY7_RESERVED', 'DIVISOR_BY8_RESERVED', 'DIV_2', 'DIV_4', + 'DIV_8', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', + 'DI_INDEX_SIZE_8_BIT', 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', + 'DI_PT_LINELIST_ADJ', 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', + 'DI_PT_LINESTRIP_ADJ', 'DI_PT_NONE', 'DI_PT_PATCH', + 'DI_PT_POINTLIST', 'DI_PT_POLYGON', 'DI_PT_QUADLIST', + 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', 'DI_PT_TRIFAN', + 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', 'DI_PT_TRISTRIP', + 'DI_PT_TRISTRIP_ADJ', 'DI_PT_UNUSED_1', 'DI_PT_UNUSED_3', + 'DI_PT_UNUSED_4', 'DI_PT_UNUSED_5', 'DI_SRC_SEL_AUTO_INDEX', + 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', 'DI_SRC_SEL_RESERVED', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', + 'DMDATA_CLEAR_UNDERFLOW_STATUS', 'DMDATA_DONE', + 'DMDATA_DONT_CLEAR', 'DMDATA_HARDWARE_UPDATE_MODE', 'DMDATA_MODE', + 'DMDATA_NOT_SENT_TO_DIG', 'DMDATA_NOT_UNDERFLOW', + 'DMDATA_NOT_UPDATED', 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', + 'DMDATA_QOS_LEVEL_FROM_TTU', 'DMDATA_QOS_MODE', 'DMDATA_REPEAT', + 'DMDATA_SENT_TO_DIG', 'DMDATA_SOFTWARE_UPDATE_MODE', + 'DMDATA_UNDERFLOW', 'DMDATA_UNDERFLOWED', + 'DMDATA_UNDERFLOW_CLEAR', 'DMDATA_UPDATED', + 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', + 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', 'DMDATA_VM_DONE', + 'DMDATA_VM_IS_DONE', 'DMDATA_VM_IS_NOT_DONE', + 'DMDATA_WAS_UPDATED', 'DME_MEM_DISABLE_MEM_PWR_CTRL', + 'DME_MEM_ENABLE_MEM_PWR_CTRL', 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', + 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', 'DME_MEM_NO_FORCE_REQUEST', + 'DME_MEM_POWER_STATE_ENUM', 'DME_MEM_POWER_STATE_ENUM_DS', + 'DME_MEM_POWER_STATE_ENUM_LS', 'DME_MEM_POWER_STATE_ENUM_ON', + 'DME_MEM_POWER_STATE_ENUM_SD', 'DME_MEM_PWR_DIS_CTRL', + 'DME_MEM_PWR_FORCE_CTRL', 'DMU_CLOCK_ON', 'DMU_CLOCK_STATUS_OFF', + 'DMU_CLOCK_STATUS_ON', 'DMU_DC_GPU_TIMER_READ_SELECT', + 'DMU_DC_GPU_TIMER_START_POSITION', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', + 'DMU_GPU_TIMER_START_0_END_27', 'DMU_GPU_TIMER_START_10_END_37', + 'DMU_GPU_TIMER_START_1_END_28', 'DMU_GPU_TIMER_START_2_END_29', + 'DMU_GPU_TIMER_START_3_END_30', 'DMU_GPU_TIMER_START_4_END_31', + 'DMU_GPU_TIMER_START_6_END_33', 'DMU_GPU_TIMER_START_8_END_35', + 'DONUTS', 'DOUT_I2C_ACK', 'DOUT_I2C_ACK_TO_CLEAN', + 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_ABORT_XFER', + 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', + 'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT', + 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO', + 'DOUT_I2C_CONTROL_NORMAL_DEBUG', + 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', + 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', + 'DOUT_I2C_CONTROL_SELECT_DDCVGA', 'DOUT_I2C_CONTROL_SEND_RESET', + 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH', + 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', + 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', + 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', + 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 'DOUT_I2C_CONTROL__SEND_RESET', + 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', + 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', + 'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE', + 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', + 'DOUT_I2C_DDC_SPEED_THRESHOLD', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', + 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', + 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', + 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DPHY_8B10B_CUR_DISP', + 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', + 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', + 'DPHY_8B10B_RESETET', 'DPHY_ATEST_LANE0_PRBS_PATTERN', + 'DPHY_ATEST_LANE0_REG_PATTERN', 'DPHY_ATEST_LANE1_PRBS_PATTERN', + 'DPHY_ATEST_LANE1_REG_PATTERN', 'DPHY_ATEST_LANE2_PRBS_PATTERN', + 'DPHY_ATEST_LANE2_REG_PATTERN', 'DPHY_ATEST_LANE3_PRBS_PATTERN', + 'DPHY_ATEST_LANE3_REG_PATTERN', 'DPHY_ATEST_SEL_LANE0', + 'DPHY_ATEST_SEL_LANE1', 'DPHY_ATEST_SEL_LANE2', + 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', 'DPHY_CRC_CONTINUOUS', + 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', 'DPHY_CRC_EN', + 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', 'DPHY_CRC_LANE0_SELECTED', + 'DPHY_CRC_LANE1_SELECTED', 'DPHY_CRC_LANE2_SELECTED', + 'DPHY_CRC_LANE3_SELECTED', 'DPHY_CRC_MST_PHASE_ERROR_ACK', + 'DPHY_CRC_MST_PHASE_ERROR_ACKED', + 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', + 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', + 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', + 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 'DPHY_FEC_ACTIVE', 'DPHY_FEC_DISABLED', 'DPHY_FEC_ENABLE', + 'DPHY_FEC_ENABLED', 'DPHY_FEC_NOT_ACTIVE', 'DPHY_FEC_READY', + 'DPHY_FEC_READY_DIS', 'DPHY_FEC_READY_EN', + 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', + 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', + 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', + 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', + 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', + 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SKEW_BYPASS', + 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM', + 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', + 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', + 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', + 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', + 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', + 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', + 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', + 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', + 'DPTE_GROUP_SIZE', 'DPTE_GROUP_SIZE_1024B', + 'DPTE_GROUP_SIZE_128B', 'DPTE_GROUP_SIZE_2048B', + 'DPTE_GROUP_SIZE_256B', 'DPTE_GROUP_SIZE_512B', + 'DPTE_GROUP_SIZE_64B', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', 'DP_AUX_ARB_STATUS', + 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', + 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', + 'DP_AUX_CONTROL_HPD_SEL', 'DP_AUX_CONTROL_NO_HPD_SELECTED', + 'DP_AUX_CONTROL_TEST_MODE', 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 'DP_AUX_CONTROL_TEST_MODE_ENABLE', + 'DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', + 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', + 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 'DP_AUX_IDLE', 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', + 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', + 'DP_AUX_INT__NOT_ACK', 'DP_AUX_IN_USE_GTC', 'DP_AUX_IN_USE_LS', + 'DP_AUX_IN_USE_PHYWAKE', 'DP_AUX_IN_USE_SW', + 'DP_AUX_LS_UPDATE_ACK', 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', + 'DP_AUX_PHY_WAKE_LOW_PRIORITY', 'DP_AUX_PHY_WAKE_PRIORITY', + 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', + 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', + 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', + 'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_RX_TIMEOUT_LEN_MUL', + 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', + 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', + 'DP_AUX_SW_CONTROL_LS_READ_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', + 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 'DP_AUX_TX_PRECHARGE_LEN_MUL', 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', + 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', + 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', 'DP_COMPONENT_DEPTH', + 'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC', + 'DP_COMPONENT_DEPTH_16BPC', 'DP_COMPONENT_DEPTH_6BPC', + 'DP_COMPONENT_DEPTH_8BPC', 'DP_COMPRESSED_PIXEL_FORMAT', + 'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE', + 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', + 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', + 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', + 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', + 'DP_DPHY_SYM32_1LANE', 'DP_DPHY_SYM32_2LANE', + 'DP_DPHY_SYM32_4LANE', 'DP_DPHY_SYM32_ACTIVE', + 'DP_DPHY_SYM32_CRC_END_LLCP', 'DP_DPHY_SYM32_CRC_END_PS_ANY', + 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', 'DP_DPHY_SYM32_CRC_END_PS_ONLY', + 'DP_DPHY_SYM32_CRC_START_LLCP', + 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', + 'DP_DPHY_SYM32_CRC_START_PS_ONLY', + 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', + 'DP_DPHY_SYM32_CRC_START_TP_START', + 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', + 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', + 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', + 'DP_DPHY_SYM32_CRC_USE_END_EVENT', + 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', 'DP_DPHY_SYM32_DISABLE', + 'DP_DPHY_SYM32_ENABLE', 'DP_DPHY_SYM32_LT_TPS1', + 'DP_DPHY_SYM32_LT_TPS2', 'DP_DPHY_SYM32_NOT_RESET', + 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', + 'DP_DPHY_SYM32_OUTPUT_DPIA', 'DP_DPHY_SYM32_OUTPUT_PHY', + 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', 'DP_DPHY_SYM32_RESERVED', + 'DP_DPHY_SYM32_RESET', 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', + 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', + 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', + 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', + 'DP_DPHY_SYM32_SAT_NO_UPDATE', + 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', + 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', + 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', + 'DP_DPHY_SYM32_SCHEDULER_ASLEEP', 'DP_DPHY_SYM32_SCHEDULER_AWAKE', + 'DP_DPHY_SYM32_SCHEDULER_OFF', 'DP_DPHY_SYM32_STATUS_ENABLED', + 'DP_DPHY_SYM32_STATUS_IDLE', 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', + 'DP_DPHY_SYM32_STREAM_OVR_NONE', + 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', + 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', + 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', 'DP_DPHY_SYM32_TEST', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', + 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', 'DP_DPHY_SYM32_TP_SELECT_PRBS', + 'DP_DPHY_SYM32_TP_SELECT_SQUARE', 'DP_DPHY_SYM32_TP_SELECT_TPS1', + 'DP_DPHY_SYM32_TP_SELECT_TPS2', 'DP_DSC_444_S422', + 'DP_DSC_N422_N420', 'DP_DTO_DESPREAD_DISABLE', + 'DP_DTO_DESPREAD_ENABLE', 'DP_DTO_DS_DISABLE', + 'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE', + 'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_LINK_TRAINING_SWITCH_MODE', + 'DP_LINK_TRAINING_SWITCH_TO_IDLE', + 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', 'DP_ML_PHY_SEQ_IMMEDIATE', + 'DP_ML_PHY_SEQ_LINE_NUM', 'DP_ML_PHY_SEQ_MODE', + 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', + 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', + 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', + 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', + 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', + 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', + 'DP_MSO_FOUR_SSTLINK', 'DP_MSO_NUM_OF_SST_LINKS', + 'DP_MSO_ONE_SSTLINK', 'DP_MSO_TWO_SSTLINK', 'DP_MST_MODE', + 'DP_PIXEL_ENCODING', 'DP_PIXEL_ENCODING_COMPRESSED', + 'DP_PIXEL_ENCODING_RGB_YCBCR444', 'DP_PIXEL_ENCODING_TYPE', + 'DP_PIXEL_ENCODING_UNCOMPRESSED', 'DP_PIXEL_ENCODING_YCBCR420', + 'DP_PIXEL_ENCODING_YCBCR422', 'DP_PIXEL_ENCODING_Y_ONLY', + 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', + 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', + 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', + 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', + 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', + 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', + 'DP_SEC_GSP_SEND', 'DP_SEC_GSP_SEND_ANY_LINE', + 'DP_SEC_GSP_SEND_PPS', 'DP_SEC_LINE_REFERENCE', + 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE', + 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_SST_MODE', + 'DP_STEER_1_PIX_PER_CYCLE', 'DP_STEER_2_PIX_PER_CYCLE', + 'DP_STEER_4_PIX_PER_CYCLE', 'DP_STEER_8_PIX_PER_CYCLE', + 'DP_STEER_OUTPUT_PIXEL_PER_CYCLE', 'DP_STEER_OVERFLOW_ACK', + 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', + 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', + 'DP_STREAM_ENC_DCCG', 'DP_STREAM_ENC_DISPLAY_PIPE', + 'DP_STREAM_ENC_HARDWARE', 'DP_STREAM_ENC_NOT_RESET', + 'DP_STREAM_ENC_NO_ERROR_OCCURRED', + 'DP_STREAM_ENC_OVERFLOW_OCCURRED', + 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR', + 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT', + 'DP_STREAM_ENC_PROGRAMMABLE', 'DP_STREAM_ENC_READ_CLOCK_CONTROL', + 'DP_STREAM_ENC_RESET', 'DP_STREAM_ENC_RESET_CONTROL', + 'DP_STREAM_ENC_STREAM_ACTIVE', 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', + 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', + 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', + 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET', + 'DP_STREAM_MAPPER_LINK0', 'DP_STREAM_MAPPER_LINK1', + 'DP_STREAM_MAPPER_LINK2', 'DP_STREAM_MAPPER_LINK3', + 'DP_STREAM_MAPPER_RESERVED', 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', + 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', + 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', + 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', + 'DP_SYM32_ENC_COMPRESSED_FORMAT', 'DP_SYM32_ENC_CONTINUOUS_MODE', + 'DP_SYM32_ENC_CRC_NOT_VALID', 'DP_SYM32_ENC_CRC_VALID', + 'DP_SYM32_ENC_DISABLE', 'DP_SYM32_ENC_DP_SOF', + 'DP_SYM32_ENC_ENABLE', 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', + 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', + 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', + 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', + 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', + 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', + 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', + 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', + 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', + 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', + 'DP_SYM32_ENC_NOT_PENDING', 'DP_SYM32_ENC_NOT_RESET', + 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', 'DP_SYM32_ENC_ONE_SHOT_MODE', + 'DP_SYM32_ENC_OTG_SOF', 'DP_SYM32_ENC_OVERFLOW_OCCURRED', + 'DP_SYM32_ENC_PENDING', + 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', + 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', + 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', + 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', + 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', + 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', + 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', + 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', 'DP_SYM32_ENC_RESET', + 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', + 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', + 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', 'DP_SYM32_ENC_SDP_LOW_PRIORITY', + 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', + 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', + 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', + 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', 'DP_SYNC_POLARITY', + 'DP_SYNC_POLARITY_ACTIVE_HIGH', 'DP_SYNC_POLARITY_ACTIVE_LOW', + 'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', + 'DP_UDI_4_LANES', 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', + 'DP_VID_1X_Nvid', 'DP_VID_2X_Nvid', 'DP_VID_4X_Nvid', + 'DP_VID_8X_Nvid', 'DP_VID_ENHANCED_FRAME_MODE', + 'DP_VID_M_N_CALC_AUTO', + 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', + 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', + 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_N_INTERVAL', + 'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK', + 'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', + 'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV', + 'DP_VID_VBID_FIELD_POL_NORMAL', 'DRAW_DONE', + 'DSCCIF_BITS_PER_COMPONENT_ENUM', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 'DSCCIF_ENABLE_ENUM', 'DSCCIF_ENABLE_ENUM_DISABLED', + 'DSCCIF_ENABLE_ENUM_ENABLED', 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', + 'DSCC_BITS_PER_COMPONENT_ENUM', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 'DSCC_DSC_VERSION_MAJOR_ENUM', + 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', + 'DSCC_DSC_VERSION_MINOR_ENUM', + 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', + 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', + 'DSCC_ENABLE_ENUM', 'DSCC_ENABLE_ENUM_DISABLED', + 'DSCC_ENABLE_ENUM_ENABLED', 'DSCC_ICH_RESET_ENUM', + 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', 'DSCC_LINEBUF_DEPTH_ENUM', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', + 'DSCC_MEM_PWR_DIS_ENUM', 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', + 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', 'DSCC_MEM_PWR_FORCE_ENUM', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', + 'DSCL_MODE_CHROMA_SCALING_BYPASS', 'DSCL_MODE_DSCL_BYPASS', + 'DSCL_MODE_LUMA_SCALING_BYPASS', 'DSCL_MODE_SCALING_444_BYPASS', + 'DSCL_MODE_SCALING_444_RGB_ENABLE', + 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', + 'DSCL_MODE_SCALING_YCBCR_ENABLE', 'DSCL_MODE_SEL', + 'DS_HW_CAL_DIS', 'DS_HW_CAL_EN', 'DS_HW_CAL_ENABLE', + 'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', + 'DS_REF_SRC', 'DVO_ENABLE_RST', 'DVO_ENABLE_RST_DISABLE', + 'DVO_ENABLE_RST_ENABLE', 'DWB_CRC_CONT_EN_CONT', + 'DWB_CRC_CONT_EN_ENUM', 'DWB_CRC_CONT_EN_ONE_SHOT', + 'DWB_CRC_SRC_SEL_DWB_IN', 'DWB_CRC_SRC_SEL_DWB_OUT', + 'DWB_CRC_SRC_SEL_ENUM', 'DWB_CRC_SRC_SEL_OGAM_OUT', + 'DWB_DATA_OVERFLOW_INT_TYPE_0', 'DWB_DATA_OVERFLOW_INT_TYPE_1', + 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM', + 'DWB_DATA_OVERFLOW_TYPE_BUFFER', 'DWB_DATA_OVERFLOW_TYPE_ENUM', + 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', + 'DWB_DATA_OVERFLOW_TYPE_VREADY', 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', + 'DWB_DEBUG_SEL_DWBCP', 'DWB_DEBUG_SEL_ENUM', 'DWB_DEBUG_SEL_FC', + 'DWB_DEBUG_SEL_PERFMON', 'DWB_DEBUG_SEL_RESERVED', + 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM', + 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', + 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', + 'DWB_GAMUT_REMAP_MODE_BYPASS', 'DWB_GAMUT_REMAP_MODE_COEF_A', + 'DWB_GAMUT_REMAP_MODE_COEF_B', 'DWB_GAMUT_REMAP_MODE_ENUM', + 'DWB_GAMUT_REMAP_MODE_RESERVED', 'DWB_LUT_NUM_SEG', + 'DWB_MEM_PWR_FORCE_DIS', 'DWB_MEM_PWR_FORCE_DS', + 'DWB_MEM_PWR_FORCE_ENUM', 'DWB_MEM_PWR_FORCE_LS', + 'DWB_MEM_PWR_FORCE_SD', 'DWB_MEM_PWR_STATE_DS', + 'DWB_MEM_PWR_STATE_ENUM', 'DWB_MEM_PWR_STATE_LS', + 'DWB_MEM_PWR_STATE_ON', 'DWB_MEM_PWR_STATE_SD', + 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', 'DWB_OGAM_LUT_CONFIG_MODE_ENUM', + 'DWB_OGAM_LUT_CONFIG_MODE_SAME', 'DWB_OGAM_LUT_HOST_SEL_ENUM', + 'DWB_OGAM_LUT_HOST_SEL_RAMA', 'DWB_OGAM_LUT_HOST_SEL_RAMB', + 'DWB_OGAM_LUT_READ_COLOR_SEL_B', + 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM', + 'DWB_OGAM_LUT_READ_COLOR_SEL_G', 'DWB_OGAM_LUT_READ_COLOR_SEL_R', + 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', + 'DWB_OGAM_LUT_READ_DBG_DISABLE', 'DWB_OGAM_LUT_READ_DBG_ENABLE', + 'DWB_OGAM_LUT_READ_DBG_ENUM', 'DWB_OGAM_MODE_BYPASS', + 'DWB_OGAM_MODE_ENUM', 'DWB_OGAM_MODE_RAM_LUT_ENABLED', + 'DWB_OGAM_MODE_RESERVED', 'DWB_OGAM_PWL_DISABLE_ENUM', + 'DWB_OGAM_PWL_DISABLE_FALSE', 'DWB_OGAM_PWL_DISABLE_TRUE', + 'DWB_OGAM_SELECT_A', 'DWB_OGAM_SELECT_B', 'DWB_OGAM_SELECT_ENUM', + 'DWB_SEGMENTS_1', 'DWB_SEGMENTS_128', 'DWB_SEGMENTS_16', + 'DWB_SEGMENTS_2', 'DWB_SEGMENTS_32', 'DWB_SEGMENTS_4', + 'DWB_SEGMENTS_64', 'DWB_SEGMENTS_8', 'DWB_TEST_CLK_SEL_ENUM', + 'DWB_TEST_CLK_SEL_G', 'DWB_TEST_CLK_SEL_P', 'DWB_TEST_CLK_SEL_R', + 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', + 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', + 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', + 'DbPRTFaultBehavior', 'DbPSLControl', 'EARLY', + 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', + 'EFC_ACrYCb16161616_10LSB', 'EFC_ACrYCb16161616_10MSB', + 'EFC_ACrYCb16161616_12LSB', 'EFC_ACrYCb16161616_12MSB', + 'EFC_ACrYCb2101010', 'EFC_ACrYCb8888', 'EFC_ARGB1555', + 'EFC_ARGB16161616_10LSB', 'EFC_ARGB16161616_10MSB', + 'EFC_ARGB16161616_12LSB', 'EFC_ARGB16161616_12MSB', + 'EFC_ARGB16161616_FLOAT', 'EFC_ARGB16161616_SNORM', + 'EFC_ARGB16161616_UNORM', 'EFC_ARGB2101010', 'EFC_ARGB4444', + 'EFC_ARGB8888', 'EFC_AYCrCb16161616_10LSB', + 'EFC_AYCrCb16161616_10MSB', 'EFC_AYCrCb16161616_12LSB', + 'EFC_AYCrCb16161616_12MSB', 'EFC_AYCrCb8888', 'EFC_BGR101111_FIX', + 'EFC_BGR101111_FLOAT', 'EFC_BGR565', + 'EFC_CbYCrY10101010_422_PACKED', 'EFC_CbYCrY12121212_422_PACKED', + 'EFC_CbYCrY8888_422_PACKED', 'EFC_CrYCbA1010102', + 'EFC_CrYCbA16161616_10LSB', 'EFC_CrYCbA16161616_10MSB', + 'EFC_CrYCbA16161616_12LSB', 'EFC_CrYCbA16161616_12MSB', + 'EFC_CrYCbA8888', 'EFC_CrYCbY10101010_422_PACKED', + 'EFC_CrYCbY12121212_422_PACKED', 'EFC_CrYCbY8888_422_PACKED', + 'EFC_MONO_10LSB', 'EFC_MONO_10MSB', 'EFC_MONO_12LSB', + 'EFC_MONO_12MSB', 'EFC_MONO_16', 'EFC_MONO_8', + 'EFC_RGB111110_FIX', 'EFC_RGB111110_FLOAT', 'EFC_RGB565', + 'EFC_RGBA1010102', 'EFC_RGBA16161616_10LSB', + 'EFC_RGBA16161616_10MSB', 'EFC_RGBA16161616_12LSB', + 'EFC_RGBA16161616_12MSB', 'EFC_RGBA16161616_FLOAT', + 'EFC_RGBA16161616_SNORM', 'EFC_RGBA16161616_UNORM', + 'EFC_RGBA4444', 'EFC_RGBA5551', 'EFC_RGBA8888', + 'EFC_SURFACE_PIXEL_FORMAT', 'EFC_Y10_CbCr1010_420_PLANAR', + 'EFC_Y10_CrCb1010_420_PLANAR', 'EFC_Y12_CbCr1212_420_PLANAR', + 'EFC_Y12_CrCb1212_420_PLANAR', 'EFC_Y8_CbCr88_420_PLANAR', + 'EFC_Y8_CrCb88_420_PLANAR', 'EFC_YCbYCr10101010_422_PACKED', + 'EFC_YCbYCr12121212_422_PACKED', 'EFC_YCbYCr8888_422_PACKED', + 'EFC_YCrCbA16161616_10LSB', 'EFC_YCrCbA16161616_10MSB', + 'EFC_YCrCbA16161616_12LSB', 'EFC_YCrCbA16161616_12MSB', + 'EFC_YCrCbA8888', 'EFC_YCrYCb10101010_422_PACKED', + 'EFC_YCrYCb12121212_422_PACKED', 'EFC_YCrYCb8888_422_PACKED', + 'ENABLE', 'ENABLE_AMCLK0', 'ENABLE_AMCLK1', 'ENABLE_CLOCK', + 'ENABLE_DEBUG', 'ENABLE_ENUM', 'ENABLE_ENUM_DISABLED', + 'ENABLE_ENUM_ENABLED', 'ENABLE_JITTER_REMOVAL', + 'ENABLE_MEM_PWR_CTRL', 'ENABLE_NGG_PIPELINE', + 'ENABLE_PIPELINE_NOT_USED', 'ENABLE_PWL', 'ENABLE_TF0_OPT', + 'ENABLE_TF1_OPT', 'ENABLE_THE_FEATURE', 'ENABLE_THE_FUNC_CLOCK', + 'ENABLE_THE_INTERRUPT', 'ENABLE_THE_REFCLK', 'END_OF_PIPE_IB_END', + 'END_OF_PIPE_INCR_DE', 'END_OF_ROW_MODE', 'ENUM_DCN_ACTIVE', + 'ENUM_DCN_NOT_ACTIVE', 'ENUM_DIO_DCN_ACTIVE_STATUS', + 'ENUM_DPG_BIT_DEPTH', 'ENUM_DPG_BIT_DEPTH_10BPC', + 'ENUM_DPG_BIT_DEPTH_12BPC', 'ENUM_DPG_BIT_DEPTH_6BPC', + 'ENUM_DPG_BIT_DEPTH_8BPC', 'ENUM_DPG_DISABLE', + 'ENUM_DPG_DYNAMIC_RANGE', 'ENUM_DPG_DYNAMIC_RANGE_CEA', + 'ENUM_DPG_DYNAMIC_RANGE_VESA', 'ENUM_DPG_EN', 'ENUM_DPG_ENABLE', + 'ENUM_DPG_FIELD_POLARITY', + 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', + 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', 'ENUM_DPG_MODE', + 'ENUM_DPG_MODE_HORIZONTAL_BAR', 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', + 'ENUM_DPG_MODE_RGB_DUAL_RAMP', 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', + 'ENUM_DPG_MODE_RGB_XR_BIAS', 'ENUM_DPG_MODE_VERTICAL_BAR', + 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', + 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', + 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT', + 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT', + 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE', + 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', + 'ENUM_DP_DPHY_SYM32_ENABLE', 'ENUM_DP_DPHY_SYM32_MODE', + 'ENUM_DP_DPHY_SYM32_NUM_LANES', 'ENUM_DP_DPHY_SYM32_OUTPUT_MODE', + 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING', + 'ENUM_DP_DPHY_SYM32_RESET', 'ENUM_DP_DPHY_SYM32_RESET_STATUS', + 'ENUM_DP_DPHY_SYM32_SAT_UPDATE', + 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING', + 'ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS', + 'ENUM_DP_DPHY_SYM32_STATUS', + 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE', + 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE', + 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL', 'ENUM_DP_DPHY_SYM32_TP_SELECT', + 'ENUM_DP_SYM32_ENC_AUDIO_MUTE', + 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE', + 'ENUM_DP_SYM32_ENC_CRC_VALID', + 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH', + 'ENUM_DP_SYM32_ENC_ENABLE', + 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED', + 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION', + 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE', + 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING', + 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM', + 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS', 'ENUM_DP_SYM32_ENC_PENDING', + 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING', + 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE', + 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM', 'ENUM_DP_SYM32_ENC_RESET', + 'ENUM_DP_SYM32_ENC_SDP_PRIORITY', + 'ENUM_DP_SYM32_ENC_SOF_REFERENCE', + 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER', 'ENUM_NUM_SIMD_PER_CU', + 'EVENT_STATE_CHANGE', 'EXOKAY', 'EXPANSION_MODE', + 'EXPANSION_MODE_CONSERVATIVE', 'EXPANSION_MODE_OPTIMAL', + 'EXPANSION_MODE_ZERO', 'EXPORT_ANY_Z', 'EXPORT_GREATER_THAN_Z', + 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'FAULT_FAIL', + 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', 'FC_EYE_SELECTION_ENUM', + 'FC_EYE_SELECTION_LEFT_EYE', 'FC_EYE_SELECTION_RIGHT_EYE', + 'FC_EYE_SELECTION_STEREO_DIS', 'FC_FRAME_CAPTURE_RATE_ENUM', + 'FC_FRAME_CAPTURE_RATE_FULL', 'FC_FRAME_CAPTURE_RATE_HALF', + 'FC_FRAME_CAPTURE_RATE_QUARTER', 'FC_FRAME_CAPTURE_RATE_THIRD', + 'FC_STEREO_EYE_POLARITY_ENUM', 'FC_STEREO_EYE_POLARITY_LEFT', + 'FC_STEREO_EYE_POLARITY_RIGHT', 'FEC_ACTIVE_STATUS', 'FIX_S2_13', + 'FIX_S3_12', 'FLIP_ANY_FRAME', 'FLIP_LEFT_EYE', 'FLIP_RATE', + 'FLIP_RATE_0', 'FLIP_RATE_1', 'FLIP_RATE_2', 'FLIP_RATE_3', + 'FLIP_RATE_4', 'FLIP_RATE_5', 'FLIP_RATE_6', 'FLIP_RATE_7', + 'FLIP_RIGHT_EYE', 'FLUSH_AND_INV_CB_DATA_TS', + 'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA', + 'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META', + 'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED', + 'FLUSH_DFSM', 'FLUSH_ES_OUTPUT', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', + 'FMTMEM_DISABLE_MEM_PWR_CTRL', 'FMTMEM_ENABLE_MEM_PWR_CTRL', + 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', + 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', + 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', 'FMTMEM_NO_FORCE_REQUEST', + 'FMTMEM_PWR_DIS_CTRL', 'FMTMEM_PWR_FORCE_CTRL', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 'FMT_CLAMP_CNTL_COLOR_FORMAT', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', + 'FMT_CONTROL_PIXEL_ENCODING', + 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', + 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 'FMT_CONTROL_SUBSAMPLING_MODE', + 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', + 'FMT_CONTROL_SUBSAMPLING_ORDER', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', + 'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', + 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', + 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', + 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE', + 'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12', + 'FMT_FRAME_RANDOM_ENABLE_CONTROL', + 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', + 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', 'FMT_POWER_STATE_ENUM', + 'FMT_POWER_STATE_ENUM_DS', 'FMT_POWER_STATE_ENUM_LS', + 'FMT_POWER_STATE_ENUM_ON', 'FMT_POWER_STATE_ENUM_SD', + 'FMT_RGB_RANDOM_ENABLE_CONTROL', + 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', + 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', + 'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0', + 'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2', + 'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVERRIDE_CONTROL', + 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', + 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', 'FORCE_00', + 'FORCE_BINNING_ON', 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', + 'FORCE_DISABLE_CLOCK', 'FORCE_EARLY_Z', 'FORCE_ENABLE', + 'FORCE_FF', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ', + 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', + 'FORCE_ONE_ROW_FOR_FRAME', 'FORCE_ONE_ROW_FOR_FRAME_0', + 'FORCE_ONE_ROW_FOR_FRAME_1', 'FORCE_OPT_AUTO', + 'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', + 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', + 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', + 'FORCE_THE_CLOCK_DISABLED', 'FORMAT_CROSSBAR', + 'FORMAT_CROSSBAR_B', 'FORMAT_CROSSBAR_G', 'FORMAT_CROSSBAR_R', + 'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER', + 'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL', + 'ForceControl', 'GATCL1RequestType', 'GATCL1_TYPE_BYPASS', + 'GATCL1_TYPE_NORMAL', 'GATCL1_TYPE_SHOOTDOWN', 'GCRPerfSel', + 'GCR_PERF_SEL_ALL_REQ', + 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CPC_ALL_REQ', 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', + 'GCR_PERF_SEL_CPC_GL1_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPC_METADATA_REQ', + 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', 'GCR_PERF_SEL_CPC_SQC_INST_REQ', + 'GCR_PERF_SEL_CPC_TCP_REQ', 'GCR_PERF_SEL_CPF_ALL_REQ', + 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', + 'GCR_PERF_SEL_CPF_GL1_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPF_METADATA_REQ', + 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', 'GCR_PERF_SEL_CPF_SQC_INST_REQ', + 'GCR_PERF_SEL_CPF_TCP_REQ', 'GCR_PERF_SEL_CPG_ALL_REQ', + 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', + 'GCR_PERF_SEL_CPG_GL1_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPG_METADATA_REQ', + 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', 'GCR_PERF_SEL_CPG_SQC_INST_REQ', + 'GCR_PERF_SEL_CPG_TCP_REQ', 'GCR_PERF_SEL_NONE', + 'GCR_PERF_SEL_PHY_REQ', 'GCR_PERF_SEL_PIO_ALL_REQ', + 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', + 'GCR_PERF_SEL_PIO_GL1_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', 'GCR_PERF_SEL_PIO_METADATA_REQ', + 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', 'GCR_PERF_SEL_PIO_SQC_INST_REQ', + 'GCR_PERF_SEL_PIO_TCP_REQ', + 'GCR_PERF_SEL_PMM_ABIT_FLUSH_INTERRUPT', + 'GCR_PERF_SEL_PMM_ABIT_FLUSH_ONGOING', + 'GCR_PERF_SEL_PMM_ABIT_FORCE_FLUSH', + 'GCR_PERF_SEL_PMM_ABIT_NUM_FLUSH', + 'GCR_PERF_SEL_PMM_ABIT_TIMER_FLUSH', + 'GCR_PERF_SEL_PMM_ALOG_INTERRUPT', + 'GCR_PERF_SEL_PMM_INTERRUPT_READY_TO_SEND', + 'GCR_PERF_SEL_PMM_MAM_FLUSH_REQ', + 'GCR_PERF_SEL_PMM_MAM_FLUSH_RESP', + 'GCR_PERF_SEL_PMM_NUM_INTERRUPT', 'GCR_PERF_SEL_PMM_RLC_CGCG_REQ', + 'GCR_PERF_SEL_PMM_RLC_CGCG_RESP', + 'GCR_PERF_SEL_PMM_STALL_PMM_IH_CREDITS', + 'GCR_PERF_SEL_PM_ALL_REQ', 'GCR_PERF_SEL_PM_GL1_ALL_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', + 'GCR_PERF_SEL_PM_GL1_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_PM_GL2_ALL_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', 'GCR_PERF_SEL_PM_METADATA_REQ', + 'GCR_PERF_SEL_PM_SQC_DATA_REQ', 'GCR_PERF_SEL_PM_SQC_INST_REQ', + 'GCR_PERF_SEL_PM_TCP_REQ', 'GCR_PERF_SEL_RLC_ALL_REQ', + 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', + 'GCR_PERF_SEL_RLC_GL1_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', 'GCR_PERF_SEL_RLC_METADATA_REQ', + 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', 'GCR_PERF_SEL_RLC_SQC_INST_REQ', + 'GCR_PERF_SEL_RLC_TCP_REQ', 'GCR_PERF_SEL_SDMA0_ALL_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', + 'GCR_PERF_SEL_SDMA0_METADATA_REQ', + 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', + 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA0_TCP_REQ', + 'GCR_PERF_SEL_SDMA1_ALL_REQ', 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', + 'GCR_PERF_SEL_SDMA1_METADATA_REQ', + 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', + 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA1_TCP_REQ', + 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', + 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', + 'GCR_PERF_SEL_UTCL2_FILTERED_RET', + 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', + 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', + 'GCR_PERF_SEL_UTCL2_REQ', 'GCR_PERF_SEL_UTCL2_RET', + 'GCR_PERF_SEL_VIRT_REQ', 'GCUTCL2_PERF_SEL', + 'GCUTCL2_PERF_SEL_EVENT_0', 'GCUTCL2_PERF_SEL_EVENT_1', + 'GCUTCL2_PERF_SEL_EVENT_10', 'GCUTCL2_PERF_SEL_EVENT_11', + 'GCUTCL2_PERF_SEL_EVENT_12', 'GCUTCL2_PERF_SEL_EVENT_13', + 'GCUTCL2_PERF_SEL_EVENT_14', 'GCUTCL2_PERF_SEL_EVENT_15', + 'GCUTCL2_PERF_SEL_EVENT_16', 'GCUTCL2_PERF_SEL_EVENT_17', + 'GCUTCL2_PERF_SEL_EVENT_18', 'GCUTCL2_PERF_SEL_EVENT_19', + 'GCUTCL2_PERF_SEL_EVENT_2', 'GCUTCL2_PERF_SEL_EVENT_20', + 'GCUTCL2_PERF_SEL_EVENT_21', 'GCUTCL2_PERF_SEL_EVENT_22', + 'GCUTCL2_PERF_SEL_EVENT_23', 'GCUTCL2_PERF_SEL_EVENT_24', + 'GCUTCL2_PERF_SEL_EVENT_25', 'GCUTCL2_PERF_SEL_EVENT_26', + 'GCUTCL2_PERF_SEL_EVENT_27', 'GCUTCL2_PERF_SEL_EVENT_28', + 'GCUTCL2_PERF_SEL_EVENT_29', 'GCUTCL2_PERF_SEL_EVENT_3', + 'GCUTCL2_PERF_SEL_EVENT_30', 'GCUTCL2_PERF_SEL_EVENT_31', + 'GCUTCL2_PERF_SEL_EVENT_32', 'GCUTCL2_PERF_SEL_EVENT_33', + 'GCUTCL2_PERF_SEL_EVENT_34', 'GCUTCL2_PERF_SEL_EVENT_35', + 'GCUTCL2_PERF_SEL_EVENT_36', 'GCUTCL2_PERF_SEL_EVENT_4', + 'GCUTCL2_PERF_SEL_EVENT_5', 'GCUTCL2_PERF_SEL_EVENT_6', + 'GCUTCL2_PERF_SEL_EVENT_7', 'GCUTCL2_PERF_SEL_EVENT_8', + 'GCUTCL2_PERF_SEL_EVENT_9', 'GCVML2_PERF_SEL', + 'GCVML2_PERF_SEL_EVENT_0', 'GCVML2_PERF_SEL_EVENT_1', + 'GCVML2_PERF_SEL_EVENT_10', 'GCVML2_PERF_SEL_EVENT_11', + 'GCVML2_PERF_SEL_EVENT_12', 'GCVML2_PERF_SEL_EVENT_13', + 'GCVML2_PERF_SEL_EVENT_14', 'GCVML2_PERF_SEL_EVENT_15', + 'GCVML2_PERF_SEL_EVENT_16', 'GCVML2_PERF_SEL_EVENT_17', + 'GCVML2_PERF_SEL_EVENT_18', 'GCVML2_PERF_SEL_EVENT_19', + 'GCVML2_PERF_SEL_EVENT_2', 'GCVML2_PERF_SEL_EVENT_20', + 'GCVML2_PERF_SEL_EVENT_21', 'GCVML2_PERF_SEL_EVENT_22', + 'GCVML2_PERF_SEL_EVENT_23', 'GCVML2_PERF_SEL_EVENT_24', + 'GCVML2_PERF_SEL_EVENT_25', 'GCVML2_PERF_SEL_EVENT_26', + 'GCVML2_PERF_SEL_EVENT_27', 'GCVML2_PERF_SEL_EVENT_28', + 'GCVML2_PERF_SEL_EVENT_29', 'GCVML2_PERF_SEL_EVENT_3', + 'GCVML2_PERF_SEL_EVENT_30', 'GCVML2_PERF_SEL_EVENT_31', + 'GCVML2_PERF_SEL_EVENT_32', 'GCVML2_PERF_SEL_EVENT_33', + 'GCVML2_PERF_SEL_EVENT_34', 'GCVML2_PERF_SEL_EVENT_35', + 'GCVML2_PERF_SEL_EVENT_36', 'GCVML2_PERF_SEL_EVENT_37', + 'GCVML2_PERF_SEL_EVENT_38', 'GCVML2_PERF_SEL_EVENT_39', + 'GCVML2_PERF_SEL_EVENT_4', 'GCVML2_PERF_SEL_EVENT_40', + 'GCVML2_PERF_SEL_EVENT_41', 'GCVML2_PERF_SEL_EVENT_42', + 'GCVML2_PERF_SEL_EVENT_43', 'GCVML2_PERF_SEL_EVENT_44', + 'GCVML2_PERF_SEL_EVENT_45', 'GCVML2_PERF_SEL_EVENT_46', + 'GCVML2_PERF_SEL_EVENT_47', 'GCVML2_PERF_SEL_EVENT_48', + 'GCVML2_PERF_SEL_EVENT_49', 'GCVML2_PERF_SEL_EVENT_5', + 'GCVML2_PERF_SEL_EVENT_50', 'GCVML2_PERF_SEL_EVENT_51', + 'GCVML2_PERF_SEL_EVENT_52', 'GCVML2_PERF_SEL_EVENT_53', + 'GCVML2_PERF_SEL_EVENT_54', 'GCVML2_PERF_SEL_EVENT_55', + 'GCVML2_PERF_SEL_EVENT_56', 'GCVML2_PERF_SEL_EVENT_57', + 'GCVML2_PERF_SEL_EVENT_58', 'GCVML2_PERF_SEL_EVENT_59', + 'GCVML2_PERF_SEL_EVENT_6', 'GCVML2_PERF_SEL_EVENT_60', + 'GCVML2_PERF_SEL_EVENT_61', 'GCVML2_PERF_SEL_EVENT_62', + 'GCVML2_PERF_SEL_EVENT_63', 'GCVML2_PERF_SEL_EVENT_64', + 'GCVML2_PERF_SEL_EVENT_65', 'GCVML2_PERF_SEL_EVENT_66', + 'GCVML2_PERF_SEL_EVENT_67', 'GCVML2_PERF_SEL_EVENT_68', + 'GCVML2_PERF_SEL_EVENT_69', 'GCVML2_PERF_SEL_EVENT_7', + 'GCVML2_PERF_SEL_EVENT_70', 'GCVML2_PERF_SEL_EVENT_71', + 'GCVML2_PERF_SEL_EVENT_72', 'GCVML2_PERF_SEL_EVENT_73', + 'GCVML2_PERF_SEL_EVENT_74', 'GCVML2_PERF_SEL_EVENT_75', + 'GCVML2_PERF_SEL_EVENT_76', 'GCVML2_PERF_SEL_EVENT_77', + 'GCVML2_PERF_SEL_EVENT_78', 'GCVML2_PERF_SEL_EVENT_79', + 'GCVML2_PERF_SEL_EVENT_8', 'GCVML2_PERF_SEL_EVENT_80', + 'GCVML2_PERF_SEL_EVENT_81', 'GCVML2_PERF_SEL_EVENT_82', + 'GCVML2_PERF_SEL_EVENT_83', 'GCVML2_PERF_SEL_EVENT_84', + 'GCVML2_PERF_SEL_EVENT_85', 'GCVML2_PERF_SEL_EVENT_86', + 'GCVML2_PERF_SEL_EVENT_87', 'GCVML2_PERF_SEL_EVENT_88', + 'GCVML2_PERF_SEL_EVENT_89', 'GCVML2_PERF_SEL_EVENT_9', + 'GCVML2_PERF_SEL_EVENT_90', 'GCVML2_SPM_PERF_SEL', + 'GCVML2_SPM_PERF_SEL_EVENT_0', 'GCVML2_SPM_PERF_SEL_EVENT_1', + 'GCVML2_SPM_PERF_SEL_EVENT_10', 'GCVML2_SPM_PERF_SEL_EVENT_11', + 'GCVML2_SPM_PERF_SEL_EVENT_12', 'GCVML2_SPM_PERF_SEL_EVENT_13', + 'GCVML2_SPM_PERF_SEL_EVENT_14', 'GCVML2_SPM_PERF_SEL_EVENT_15', + 'GCVML2_SPM_PERF_SEL_EVENT_16', 'GCVML2_SPM_PERF_SEL_EVENT_17', + 'GCVML2_SPM_PERF_SEL_EVENT_18', 'GCVML2_SPM_PERF_SEL_EVENT_19', + 'GCVML2_SPM_PERF_SEL_EVENT_2', 'GCVML2_SPM_PERF_SEL_EVENT_20', + 'GCVML2_SPM_PERF_SEL_EVENT_21', 'GCVML2_SPM_PERF_SEL_EVENT_22', + 'GCVML2_SPM_PERF_SEL_EVENT_23', 'GCVML2_SPM_PERF_SEL_EVENT_24', + 'GCVML2_SPM_PERF_SEL_EVENT_25', 'GCVML2_SPM_PERF_SEL_EVENT_26', + 'GCVML2_SPM_PERF_SEL_EVENT_27', 'GCVML2_SPM_PERF_SEL_EVENT_28', + 'GCVML2_SPM_PERF_SEL_EVENT_29', 'GCVML2_SPM_PERF_SEL_EVENT_3', + 'GCVML2_SPM_PERF_SEL_EVENT_30', 'GCVML2_SPM_PERF_SEL_EVENT_31', + 'GCVML2_SPM_PERF_SEL_EVENT_32', 'GCVML2_SPM_PERF_SEL_EVENT_33', + 'GCVML2_SPM_PERF_SEL_EVENT_34', 'GCVML2_SPM_PERF_SEL_EVENT_35', + 'GCVML2_SPM_PERF_SEL_EVENT_36', 'GCVML2_SPM_PERF_SEL_EVENT_37', + 'GCVML2_SPM_PERF_SEL_EVENT_38', 'GCVML2_SPM_PERF_SEL_EVENT_39', + 'GCVML2_SPM_PERF_SEL_EVENT_4', 'GCVML2_SPM_PERF_SEL_EVENT_40', + 'GCVML2_SPM_PERF_SEL_EVENT_41', 'GCVML2_SPM_PERF_SEL_EVENT_42', + 'GCVML2_SPM_PERF_SEL_EVENT_43', 'GCVML2_SPM_PERF_SEL_EVENT_44', + 'GCVML2_SPM_PERF_SEL_EVENT_45', 'GCVML2_SPM_PERF_SEL_EVENT_46', + 'GCVML2_SPM_PERF_SEL_EVENT_47', 'GCVML2_SPM_PERF_SEL_EVENT_48', + 'GCVML2_SPM_PERF_SEL_EVENT_49', 'GCVML2_SPM_PERF_SEL_EVENT_5', + 'GCVML2_SPM_PERF_SEL_EVENT_50', 'GCVML2_SPM_PERF_SEL_EVENT_51', + 'GCVML2_SPM_PERF_SEL_EVENT_52', 'GCVML2_SPM_PERF_SEL_EVENT_53', + 'GCVML2_SPM_PERF_SEL_EVENT_54', 'GCVML2_SPM_PERF_SEL_EVENT_55', + 'GCVML2_SPM_PERF_SEL_EVENT_56', 'GCVML2_SPM_PERF_SEL_EVENT_57', + 'GCVML2_SPM_PERF_SEL_EVENT_58', 'GCVML2_SPM_PERF_SEL_EVENT_59', + 'GCVML2_SPM_PERF_SEL_EVENT_6', 'GCVML2_SPM_PERF_SEL_EVENT_60', + 'GCVML2_SPM_PERF_SEL_EVENT_61', 'GCVML2_SPM_PERF_SEL_EVENT_62', + 'GCVML2_SPM_PERF_SEL_EVENT_63', 'GCVML2_SPM_PERF_SEL_EVENT_64', + 'GCVML2_SPM_PERF_SEL_EVENT_65', 'GCVML2_SPM_PERF_SEL_EVENT_66', + 'GCVML2_SPM_PERF_SEL_EVENT_67', 'GCVML2_SPM_PERF_SEL_EVENT_68', + 'GCVML2_SPM_PERF_SEL_EVENT_69', 'GCVML2_SPM_PERF_SEL_EVENT_7', + 'GCVML2_SPM_PERF_SEL_EVENT_70', 'GCVML2_SPM_PERF_SEL_EVENT_71', + 'GCVML2_SPM_PERF_SEL_EVENT_72', 'GCVML2_SPM_PERF_SEL_EVENT_73', + 'GCVML2_SPM_PERF_SEL_EVENT_74', 'GCVML2_SPM_PERF_SEL_EVENT_75', + 'GCVML2_SPM_PERF_SEL_EVENT_76', 'GCVML2_SPM_PERF_SEL_EVENT_77', + 'GCVML2_SPM_PERF_SEL_EVENT_78', 'GCVML2_SPM_PERF_SEL_EVENT_79', + 'GCVML2_SPM_PERF_SEL_EVENT_8', 'GCVML2_SPM_PERF_SEL_EVENT_80', + 'GCVML2_SPM_PERF_SEL_EVENT_81', 'GCVML2_SPM_PERF_SEL_EVENT_82', + 'GCVML2_SPM_PERF_SEL_EVENT_83', 'GCVML2_SPM_PERF_SEL_EVENT_84', + 'GCVML2_SPM_PERF_SEL_EVENT_85', 'GCVML2_SPM_PERF_SEL_EVENT_86', + 'GCVML2_SPM_PERF_SEL_EVENT_87', 'GCVML2_SPM_PERF_SEL_EVENT_88', + 'GCVML2_SPM_PERF_SEL_EVENT_89', 'GCVML2_SPM_PERF_SEL_EVENT_9', + 'GCVML2_SPM_PERF_SEL_EVENT_90', 'GC_EA_CPWD_PERFCOUNT_SEL', + 'GC_EA_CPWD_PERF_SEL_ALWAYS_COUNT', + 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_COMPLETED', + 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT', + 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED', + 'GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_ONGOING', + 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_EVICT', + 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT', + 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT_EVICT', + 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_LRU_EVICT', + 'GC_EA_CPWD_PERF_SEL_MAM_ARAM_REQ_VLD', + 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_EVICT', + 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT', + 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT_EVICT', + 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_LRU_EVICT', + 'GC_EA_CPWD_PERF_SEL_MAM_DBIT_REQ_VLD', + 'GC_EA_CPWD_PERF_SEL_MAM_DQRY_ONGOING', + 'GC_EA_CPWD_PERF_SEL_MAM_FLUSH_REQ', + 'GC_EA_CPWD_PERF_SEL_MAM_FLUSH_RESP', + 'GC_EA_CPWD_PERF_SEL_MAM_NUM_DQRY', 'GC_EA_CPWD_PERF_SEL_PRB_REQ', + 'GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', + 'GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP', + 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END0', + 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END1', + 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START0', + 'GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START1', + 'GC_EA_CPWD_PERF_SEL_RDRAM_NUM_BANKS_VLD', + 'GC_EA_CPWD_PERF_SEL_RDRAM_REQ_PER_CLIGRP', + 'GC_EA_CPWD_PERF_SEL_RDRAM_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH', + 'GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR', + 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END0', + 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END1', + 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START0', + 'GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START1', + 'GC_EA_CPWD_PERF_SEL_RGMI_NUM_BANKS_VLD', + 'GC_EA_CPWD_PERF_SEL_RGMI_REQ_PER_CLIGRP', + 'GC_EA_CPWD_PERF_SEL_RGMI_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_RIO_GRP0_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_RIO_GRP1_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_RIO_GRP2_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_RIO_GRP3_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END0', + 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END1', + 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START0', + 'GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START1', + 'GC_EA_CPWD_PERF_SEL_RIO_REQ_PER_CLIGRP', + 'GC_EA_CPWD_PERF_SEL_RIO_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_RRET_VLD', 'GC_EA_CPWD_PERF_SEL_SARB_BUSY', + 'GC_EA_CPWD_PERF_SEL_SARB_COHERENT_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_REQ_PER_VC', + 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_RW_TURN_AROUND', + 'GC_EA_CPWD_PERF_SEL_SARB_DRAM_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_SARB_GMI_REQ_PER_VC', + 'GC_EA_CPWD_PERF_SEL_SARB_GMI_RW_TURN_AROUND', + 'GC_EA_CPWD_PERF_SEL_SARB_GMI_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_SARB_IDLE', + 'GC_EA_CPWD_PERF_SEL_SARB_IO_REQ_PER_VC', + 'GC_EA_CPWD_PERF_SEL_SARB_IO_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END0', + 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END1', + 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START0', + 'GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START1', + 'GC_EA_CPWD_PERF_SEL_SARB_REQ_PER_VC', + 'GC_EA_CPWD_PERF_SEL_SARB_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_SARB_STALLED', + 'GC_EA_CPWD_PERF_SEL_SARB_STARVING', + 'GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', + 'GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP', + 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END0', + 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END1', + 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START0', + 'GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START1', + 'GC_EA_CPWD_PERF_SEL_WDRAM_NUM_BANKS_VLD', + 'GC_EA_CPWD_PERF_SEL_WDRAM_REQ_PER_CLIGRP', + 'GC_EA_CPWD_PERF_SEL_WDRAM_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH', + 'GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP', + 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END0', + 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END1', + 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START0', + 'GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START1', + 'GC_EA_CPWD_PERF_SEL_WGMI_NUM_BANKS_VLD', + 'GC_EA_CPWD_PERF_SEL_WGMI_REQ_PER_CLIGRP', + 'GC_EA_CPWD_PERF_SEL_WGMI_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP', + 'GC_EA_CPWD_PERF_SEL_WIO_GRP0_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_WIO_GRP1_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_WIO_GRP2_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_WIO_GRP3_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END0', + 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END1', + 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START0', + 'GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START1', + 'GC_EA_CPWD_PERF_SEL_WIO_REQ_PER_CLIGRP', + 'GC_EA_CPWD_PERF_SEL_WIO_SIZE_REQ', + 'GC_EA_CPWD_PERF_SEL_WRET_VLD', 'GC_EA_SE_PERFCOUNT_SEL', + 'GC_EA_SE_PERF_SEL_ALWAYS_COUNT', + 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_COMPLETED', + 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT', + 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED', + 'GC_EA_SE_PERF_SEL_MAM_AFLUSH_ONGOING', + 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_EVICT', + 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT', + 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT_EVICT', + 'GC_EA_SE_PERF_SEL_MAM_ARAM_FA_LRU_EVICT', + 'GC_EA_SE_PERF_SEL_MAM_ARAM_REQ_VLD', + 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_EVICT', + 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT', + 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT_EVICT', + 'GC_EA_SE_PERF_SEL_MAM_DBIT_FA_LRU_EVICT', + 'GC_EA_SE_PERF_SEL_MAM_DBIT_REQ_VLD', + 'GC_EA_SE_PERF_SEL_MAM_DQRY_ONGOING', + 'GC_EA_SE_PERF_SEL_MAM_FLUSH_REQ', + 'GC_EA_SE_PERF_SEL_MAM_FLUSH_RESP', + 'GC_EA_SE_PERF_SEL_MAM_NUM_DQRY', 'GC_EA_SE_PERF_SEL_PRB_REQ', + 'GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', + 'GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP', + 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END0', + 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END1', + 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START0', + 'GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START1', + 'GC_EA_SE_PERF_SEL_RDRAM_NUM_BANKS_VLD', + 'GC_EA_SE_PERF_SEL_RDRAM_REQ_PER_CLIGRP', + 'GC_EA_SE_PERF_SEL_RDRAM_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH', + 'GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR', + 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_END0', + 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_END1', + 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_START0', + 'GC_EA_SE_PERF_SEL_RGMI_LATENCY_START1', + 'GC_EA_SE_PERF_SEL_RGMI_NUM_BANKS_VLD', + 'GC_EA_SE_PERF_SEL_RGMI_REQ_PER_CLIGRP', + 'GC_EA_SE_PERF_SEL_RGMI_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_RIO_GRP0_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_RIO_GRP1_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_RIO_GRP2_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_RIO_GRP3_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_RIO_LATENCY_END0', + 'GC_EA_SE_PERF_SEL_RIO_LATENCY_END1', + 'GC_EA_SE_PERF_SEL_RIO_LATENCY_START0', + 'GC_EA_SE_PERF_SEL_RIO_LATENCY_START1', + 'GC_EA_SE_PERF_SEL_RIO_REQ_PER_CLIGRP', + 'GC_EA_SE_PERF_SEL_RIO_SIZE_REQ', 'GC_EA_SE_PERF_SEL_RRET_VLD', + 'GC_EA_SE_PERF_SEL_SARB_BUSY', + 'GC_EA_SE_PERF_SEL_SARB_COHERENT_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_SARB_DRAM_REQ_PER_VC', + 'GC_EA_SE_PERF_SEL_SARB_DRAM_RW_TURN_AROUND', + 'GC_EA_SE_PERF_SEL_SARB_DRAM_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_SARB_GMI_REQ_PER_VC', + 'GC_EA_SE_PERF_SEL_SARB_GMI_RW_TURN_AROUND', + 'GC_EA_SE_PERF_SEL_SARB_GMI_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_SARB_IDLE', + 'GC_EA_SE_PERF_SEL_SARB_IO_REQ_PER_VC', + 'GC_EA_SE_PERF_SEL_SARB_IO_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_SARB_LATENCY_END0', + 'GC_EA_SE_PERF_SEL_SARB_LATENCY_END1', + 'GC_EA_SE_PERF_SEL_SARB_LATENCY_START0', + 'GC_EA_SE_PERF_SEL_SARB_LATENCY_START1', + 'GC_EA_SE_PERF_SEL_SARB_REQ_PER_VC', + 'GC_EA_SE_PERF_SEL_SARB_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_SARB_STALLED', + 'GC_EA_SE_PERF_SEL_SARB_STARVING', + 'GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH', + 'GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP', + 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END0', + 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END1', + 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START0', + 'GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START1', + 'GC_EA_SE_PERF_SEL_WDRAM_NUM_BANKS_VLD', + 'GC_EA_SE_PERF_SEL_WDRAM_REQ_PER_CLIGRP', + 'GC_EA_SE_PERF_SEL_WDRAM_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH', + 'GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP', + 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_END0', + 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_END1', + 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_START0', + 'GC_EA_SE_PERF_SEL_WGMI_LATENCY_START1', + 'GC_EA_SE_PERF_SEL_WGMI_NUM_BANKS_VLD', + 'GC_EA_SE_PERF_SEL_WGMI_REQ_PER_CLIGRP', + 'GC_EA_SE_PERF_SEL_WGMI_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP', + 'GC_EA_SE_PERF_SEL_WIO_GRP0_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_WIO_GRP1_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_WIO_GRP2_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_WIO_GRP3_SIZE_REQ', + 'GC_EA_SE_PERF_SEL_WIO_LATENCY_END0', + 'GC_EA_SE_PERF_SEL_WIO_LATENCY_END1', + 'GC_EA_SE_PERF_SEL_WIO_LATENCY_START0', + 'GC_EA_SE_PERF_SEL_WIO_LATENCY_START1', + 'GC_EA_SE_PERF_SEL_WIO_REQ_PER_CLIGRP', + 'GC_EA_SE_PERF_SEL_WIO_SIZE_REQ', 'GC_EA_SE_PERF_SEL_WRET_VLD', + 'GE1_PERFCOUNT_SELECT', 'GE2_DIST_PERFCOUNT_SELECT', + 'GE2_SE_PERFCOUNT_SELECT', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', + 'GENERIC_STEREOSYNC_SEL', 'GENERIC_STEREOSYNC_SEL_D1', + 'GENERIC_STEREOSYNC_SEL_D2', 'GENERIC_STEREOSYNC_SEL_D3', + 'GENERIC_STEREOSYNC_SEL_D4', 'GENERIC_STEREOSYNC_SEL_RESERVED', + 'GL0V_CACHE_POLICIES', 'GL0V_CACHE_POLICY_HIT_EVICT', + 'GL0V_CACHE_POLICY_HIT_LRU', 'GL0V_CACHE_POLICY_MISS_EVICT', + 'GL0V_CACHE_POLICY_MISS_INVAL', 'GL0V_CACHE_POLICY_MISS_LRU', + 'GL1A_PERF_SEL', 'GL1A_PERF_SEL_ARB_REQUESTS', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', 'GL1A_PERF_SEL_BUSY', + 'GL1A_PERF_SEL_CYCLE', 'GL1A_PERF_SEL_REQUEST_GL1C0', + 'GL1A_PERF_SEL_REQUEST_GL1C1', 'GL1A_PERF_SEL_REQUEST_GL1C2', + 'GL1A_PERF_SEL_REQUEST_GL1C3', 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', + 'GL1A_PERF_SEL_STALL_GL1C0', 'GL1A_PERF_SEL_STALL_GL1C1', + 'GL1A_PERF_SEL_STALL_GL1C2', 'GL1A_PERF_SEL_STALL_GL1C3', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', + 'GL1A_PERF_SEL_WDS_32B_GL1C0', 'GL1A_PERF_SEL_WDS_32B_GL1C1', + 'GL1A_PERF_SEL_WDS_32B_GL1C2', 'GL1A_PERF_SEL_WDS_32B_GL1C3', + 'GL1C_PERF_SEL', 'GL1C_PERF_SEL_ARB_RET_LEVEL', + 'GL1C_PERF_SEL_BUSY', 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', + 'GL1C_PERF_SEL_CYCLE', 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', + 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'GL1C_PERF_SEL_REQ', + 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', 'GL1C_PERF_SEL_REQ_CLIENT0', + 'GL1C_PERF_SEL_REQ_CLIENT1', 'GL1C_PERF_SEL_REQ_CLIENT10', + 'GL1C_PERF_SEL_REQ_CLIENT11', 'GL1C_PERF_SEL_REQ_CLIENT12', + 'GL1C_PERF_SEL_REQ_CLIENT13', 'GL1C_PERF_SEL_REQ_CLIENT14', + 'GL1C_PERF_SEL_REQ_CLIENT15', 'GL1C_PERF_SEL_REQ_CLIENT16', + 'GL1C_PERF_SEL_REQ_CLIENT17', 'GL1C_PERF_SEL_REQ_CLIENT18', + 'GL1C_PERF_SEL_REQ_CLIENT19', 'GL1C_PERF_SEL_REQ_CLIENT2', + 'GL1C_PERF_SEL_REQ_CLIENT20', 'GL1C_PERF_SEL_REQ_CLIENT21', + 'GL1C_PERF_SEL_REQ_CLIENT22', 'GL1C_PERF_SEL_REQ_CLIENT23', + 'GL1C_PERF_SEL_REQ_CLIENT24', 'GL1C_PERF_SEL_REQ_CLIENT25', + 'GL1C_PERF_SEL_REQ_CLIENT26', 'GL1C_PERF_SEL_REQ_CLIENT27', + 'GL1C_PERF_SEL_REQ_CLIENT3', 'GL1C_PERF_SEL_REQ_CLIENT4', + 'GL1C_PERF_SEL_REQ_CLIENT5', 'GL1C_PERF_SEL_REQ_CLIENT6', + 'GL1C_PERF_SEL_REQ_CLIENT7', 'GL1C_PERF_SEL_REQ_CLIENT8', + 'GL1C_PERF_SEL_REQ_CLIENT9', 'GL1C_PERF_SEL_REQ_NOP_ACK', + 'GL1C_PERF_SEL_REQ_NOP_RTN0', 'GL1C_PERF_SEL_REQ_READ', + 'GL1C_PERF_SEL_REQ_READ_128B', 'GL1C_PERF_SEL_REQ_READ_32B', + 'GL1C_PERF_SEL_REQ_READ_64B', 'GL1C_PERF_SEL_REQ_WRITE', + 'GL1C_PERF_SEL_REQ_WRITE_32B', 'GL1C_PERF_SEL_REQ_WRITE_64B', + 'GL1C_PERF_SEL_STALL_BUFFER_FULL', 'GL1C_PERF_SEL_STALL_GL2_GL1', + 'GL1C_PERF_SEL_STALL_VM', 'GL1C_PERF_SEL_STARVE', + 'GL1C_PERF_SEL_UTCL0_GPA3_REQUEST', + 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', + 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', + 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', + 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', + 'GL1C_PERF_SEL_UTCL0_REQUEST', + 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', + 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', + 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', + 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', 'GL1XA_PERF_SEL', + 'GL1XA_PERF_SEL_ARB_REQUESTS', + 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC0', + 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC1', + 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC2', + 'GL1XA_PERF_SEL_BURST_COUNT_GL1XC3', 'GL1XA_PERF_SEL_BUSY', + 'GL1XA_PERF_SEL_CYCLE', 'GL1XA_PERF_SEL_REQUEST_GL1XC0', + 'GL1XA_PERF_SEL_REQUEST_GL1XC1', 'GL1XA_PERF_SEL_REQUEST_GL1XC2', + 'GL1XA_PERF_SEL_REQUEST_GL1XC3', + 'GL1XA_PERF_SEL_REQ_INFLIGHT_LEVEL', + 'GL1XA_PERF_SEL_STALL_GL1XC0', 'GL1XA_PERF_SEL_STALL_GL1XC1', + 'GL1XA_PERF_SEL_STALL_GL1XC2', 'GL1XA_PERF_SEL_STALL_GL1XC3', + 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC0', + 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC1', + 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC2', + 'GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC3', + 'GL1XA_PERF_SEL_WDS_32B_GL1XC0', 'GL1XA_PERF_SEL_WDS_32B_GL1XC1', + 'GL1XA_PERF_SEL_WDS_32B_GL1XC2', 'GL1XA_PERF_SEL_WDS_32B_GL1XC3', + 'GL1XC_PERF_SEL', 'GL1XC_PERF_SEL_ARB_RET_LEVEL', + 'GL1XC_PERF_SEL_BUSY', 'GL1XC_PERF_SEL_CLIENT_UTCL0_INFLIGHT', + 'GL1XC_PERF_SEL_CYCLE', 'GL1XC_PERF_SEL_GL2_REQ_READ_LATENCY', + 'GL1XC_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'GL1XC_PERF_SEL_REQ', + 'GL1XC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 'GL1XC_PERF_SEL_REQ_ATOMIC_WITH_RET', + 'GL1XC_PERF_SEL_REQ_CLIENT0', 'GL1XC_PERF_SEL_REQ_CLIENT1', + 'GL1XC_PERF_SEL_REQ_CLIENT10', 'GL1XC_PERF_SEL_REQ_CLIENT11', + 'GL1XC_PERF_SEL_REQ_CLIENT12', 'GL1XC_PERF_SEL_REQ_CLIENT13', + 'GL1XC_PERF_SEL_REQ_CLIENT14', 'GL1XC_PERF_SEL_REQ_CLIENT15', + 'GL1XC_PERF_SEL_REQ_CLIENT16', 'GL1XC_PERF_SEL_REQ_CLIENT17', + 'GL1XC_PERF_SEL_REQ_CLIENT18', 'GL1XC_PERF_SEL_REQ_CLIENT19', + 'GL1XC_PERF_SEL_REQ_CLIENT2', 'GL1XC_PERF_SEL_REQ_CLIENT20', + 'GL1XC_PERF_SEL_REQ_CLIENT21', 'GL1XC_PERF_SEL_REQ_CLIENT22', + 'GL1XC_PERF_SEL_REQ_CLIENT23', 'GL1XC_PERF_SEL_REQ_CLIENT24', + 'GL1XC_PERF_SEL_REQ_CLIENT25', 'GL1XC_PERF_SEL_REQ_CLIENT26', + 'GL1XC_PERF_SEL_REQ_CLIENT27', 'GL1XC_PERF_SEL_REQ_CLIENT3', + 'GL1XC_PERF_SEL_REQ_CLIENT4', 'GL1XC_PERF_SEL_REQ_CLIENT5', + 'GL1XC_PERF_SEL_REQ_CLIENT6', 'GL1XC_PERF_SEL_REQ_CLIENT7', + 'GL1XC_PERF_SEL_REQ_CLIENT8', 'GL1XC_PERF_SEL_REQ_CLIENT9', + 'GL1XC_PERF_SEL_REQ_NOP_ACK', 'GL1XC_PERF_SEL_REQ_NOP_RTN0', + 'GL1XC_PERF_SEL_REQ_READ', 'GL1XC_PERF_SEL_REQ_READ_128B', + 'GL1XC_PERF_SEL_REQ_READ_32B', 'GL1XC_PERF_SEL_REQ_READ_64B', + 'GL1XC_PERF_SEL_REQ_WRITE', 'GL1XC_PERF_SEL_REQ_WRITE_32B', + 'GL1XC_PERF_SEL_REQ_WRITE_64B', + 'GL1XC_PERF_SEL_STALL_BUFFER_FULL', + 'GL1XC_PERF_SEL_STALL_GL2_GL1', 'GL1XC_PERF_SEL_STALL_VM', + 'GL1XC_PERF_SEL_STARVE', 'GL1XC_PERF_SEL_UTCL0_GPA3_REQUEST', + 'GL1XC_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', + 'GL1XC_PERF_SEL_UTCL0_LFIFO_FULL', + 'GL1XC_PERF_SEL_UTCL0_MISS_UNDER_MISS', + 'GL1XC_PERF_SEL_UTCL0_PERMISSION_MISS', + 'GL1XC_PERF_SEL_UTCL0_REQUEST', + 'GL1XC_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 'GL1XC_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 'GL1XC_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 'GL1XC_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 'GL1XC_PERF_SEL_UTCL0_STALL_MULTI_MISS', + 'GL1XC_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 'GL1XC_PERF_SEL_UTCL0_TRANSLATION_HIT', + 'GL1XC_PERF_SEL_UTCL0_TRANSLATION_MISS', + 'GL1XC_PERF_SEL_UTCL0_UTCL1_INFLIGHT', + 'GL1XC_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', + 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', + 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', + 'GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', + 'GL1_CACHE_POLICIES', 'GL1_CACHE_POLICY_HIT_EVICT', + 'GL1_CACHE_POLICY_HIT_LRU', 'GL1_CACHE_POLICY_MISS_EVICT', + 'GL1_CACHE_POLICY_MISS_LRU', 'GL1_CACHE_STORE_POLICIES', + 'GL1_CACHE_STORE_POLICY_BYPASS', 'GL2A_PERF_SEL', + 'GL2A_PERF_SEL_BUSY', 'GL2A_PERF_SEL_CYCLE', 'GL2A_PERF_SEL_NONE', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', + 'GL2A_PERF_SEL_REQ_BURST_GL2C0', 'GL2A_PERF_SEL_REQ_BURST_GL2C1', + 'GL2A_PERF_SEL_REQ_BURST_GL2C2', 'GL2A_PERF_SEL_REQ_BURST_GL2C3', + 'GL2A_PERF_SEL_REQ_BURST_GL2C4', 'GL2A_PERF_SEL_REQ_BURST_GL2C5', + 'GL2A_PERF_SEL_REQ_BURST_GL2C6', 'GL2A_PERF_SEL_REQ_BURST_GL2C7', + 'GL2A_PERF_SEL_REQ_GL2C0', 'GL2A_PERF_SEL_REQ_GL2C1', + 'GL2A_PERF_SEL_REQ_GL2C2', 'GL2A_PERF_SEL_REQ_GL2C3', + 'GL2A_PERF_SEL_REQ_GL2C4', 'GL2A_PERF_SEL_REQ_GL2C5', + 'GL2A_PERF_SEL_REQ_GL2C6', 'GL2A_PERF_SEL_REQ_GL2C7', + 'GL2A_PERF_SEL_REQ_STALL_GL2C0', 'GL2A_PERF_SEL_REQ_STALL_GL2C1', + 'GL2A_PERF_SEL_REQ_STALL_GL2C2', 'GL2A_PERF_SEL_REQ_STALL_GL2C3', + 'GL2A_PERF_SEL_REQ_STALL_GL2C4', 'GL2A_PERF_SEL_REQ_STALL_GL2C5', + 'GL2A_PERF_SEL_REQ_STALL_GL2C6', 'GL2A_PERF_SEL_REQ_STALL_GL2C7', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', + 'GL2A_PERF_SEL_RTN_CLIENT0', 'GL2A_PERF_SEL_RTN_CLIENT1', + 'GL2A_PERF_SEL_RTN_CLIENT10', 'GL2A_PERF_SEL_RTN_CLIENT11', + 'GL2A_PERF_SEL_RTN_CLIENT12', 'GL2A_PERF_SEL_RTN_CLIENT13', + 'GL2A_PERF_SEL_RTN_CLIENT14', 'GL2A_PERF_SEL_RTN_CLIENT15', + 'GL2A_PERF_SEL_RTN_CLIENT2', 'GL2A_PERF_SEL_RTN_CLIENT3', + 'GL2A_PERF_SEL_RTN_CLIENT4', 'GL2A_PERF_SEL_RTN_CLIENT5', + 'GL2A_PERF_SEL_RTN_CLIENT6', 'GL2A_PERF_SEL_RTN_CLIENT7', + 'GL2A_PERF_SEL_RTN_CLIENT8', 'GL2A_PERF_SEL_RTN_CLIENT9', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', + 'GL2A_PERF_SEL_RTN_STALL_GL2C0', 'GL2A_PERF_SEL_RTN_STALL_GL2C1', + 'GL2A_PERF_SEL_RTN_STALL_GL2C2', 'GL2A_PERF_SEL_RTN_STALL_GL2C3', + 'GL2A_PERF_SEL_RTN_STALL_GL2C4', 'GL2A_PERF_SEL_RTN_STALL_GL2C5', + 'GL2A_PERF_SEL_RTN_STALL_GL2C6', 'GL2A_PERF_SEL_RTN_STALL_GL2C7', + 'GL2C_PERF_SEL', 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', + 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', + 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', + 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', + 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', + 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', + 'GL2C_PERF_SEL_ATOMIC', 'GL2C_PERF_SEL_BUBBLE', + 'GL2C_PERF_SEL_BUSY', 'GL2C_PERF_SEL_BYPASS_REQ', + 'GL2C_PERF_SEL_CLIENT0_REQ', 'GL2C_PERF_SEL_CLIENT10_REQ', + 'GL2C_PERF_SEL_CLIENT11_REQ', 'GL2C_PERF_SEL_CLIENT12_REQ', + 'GL2C_PERF_SEL_CLIENT13_REQ', 'GL2C_PERF_SEL_CLIENT14_REQ', + 'GL2C_PERF_SEL_CLIENT15_REQ', 'GL2C_PERF_SEL_CLIENT1_REQ', + 'GL2C_PERF_SEL_CLIENT2_REQ', 'GL2C_PERF_SEL_CLIENT3_REQ', + 'GL2C_PERF_SEL_CLIENT4_REQ', 'GL2C_PERF_SEL_CLIENT5_REQ', + 'GL2C_PERF_SEL_CLIENT6_REQ', 'GL2C_PERF_SEL_CLIENT7_REQ', + 'GL2C_PERF_SEL_CLIENT8_REQ', 'GL2C_PERF_SEL_CLIENT9_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', 'GL2C_PERF_SEL_CYCLE', + 'GL2C_PERF_SEL_C_RO_S_REQ', 'GL2C_PERF_SEL_C_RO_US_REQ', + 'GL2C_PERF_SEL_C_RW_S_REQ', 'GL2C_PERF_SEL_C_RW_US_REQ', + 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'GL2C_PERF_SEL_EA_ATOMIC', + 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', 'GL2C_PERF_SEL_EA_OUTSTANDING', + 'GL2C_PERF_SEL_EA_RDREQ_128B', 'GL2C_PERF_SEL_EA_RDREQ_32B', + 'GL2C_PERF_SEL_EA_RDREQ_64B', 'GL2C_PERF_SEL_EA_RDREQ_96B', + 'GL2C_PERF_SEL_EA_RDREQ_DRAM', 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', + 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', + 'GL2C_PERF_SEL_EA_RDRET_NACK', + 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', + 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', 'GL2C_PERF_SEL_EA_WRREQ_64B', + 'GL2C_PERF_SEL_EA_WRREQ_DRAM', 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', + 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', 'GL2C_PERF_SEL_EA_WRRET_NACK', + 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', 'GL2C_PERF_SEL_EVICT', + 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', 'GL2C_PERF_SEL_FULL_HIT', + 'GL2C_PERF_SEL_GARLIC_READ', 'GL2C_PERF_SEL_GARLIC_WRITE', + 'GL2C_PERF_SEL_GCR_ALL', 'GL2C_PERF_SEL_GCR_DISCARD', + 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', + 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', + 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', + 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', 'GL2C_PERF_SEL_GCR_INV', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', 'GL2C_PERF_SEL_GCR_RANGE', + 'GL2C_PERF_SEL_GCR_UNSHARED', 'GL2C_PERF_SEL_GCR_VOL', + 'GL2C_PERF_SEL_GCR_WB', 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', + 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', + 'GL2C_PERF_SEL_GCR_WBINVL2_START', + 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', + 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', 'GL2C_PERF_SEL_GL2A_LEVEL', + 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', 'GL2C_PERF_SEL_HIT', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', 'GL2C_PERF_SEL_IB_REQ', + 'GL2C_PERF_SEL_IB_STALL', 'GL2C_PERF_SEL_IB_TAG_STALL', + 'GL2C_PERF_SEL_IO_READ', 'GL2C_PERF_SEL_IO_WRITE', + 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', 'GL2C_PERF_SEL_LRU_REQ', + 'GL2C_PERF_SEL_MC_RDREQ', 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', + 'GL2C_PERF_SEL_MC_WRREQ', 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', + 'GL2C_PERF_SEL_MC_WRREQ_STALL', 'GL2C_PERF_SEL_METADATA_READ_REQ', + 'GL2C_PERF_SEL_MISS', 'GL2C_PERF_SEL_NOA_REQ', + 'GL2C_PERF_SEL_NONE', 'GL2C_PERF_SEL_NOP_ACK', + 'GL2C_PERF_SEL_NOP_RTN0', 'GL2C_PERF_SEL_NORMAL_EVICT', + 'GL2C_PERF_SEL_NORMAL_WRITEBACK', 'GL2C_PERF_SEL_ONION_READ', + 'GL2C_PERF_SEL_ONION_WRITE', 'GL2C_PERF_SEL_PARTIAL_32B_HIT', + 'GL2C_PERF_SEL_PARTIAL_64B_HIT', 'GL2C_PERF_SEL_PARTIAL_96B_HIT', + 'GL2C_PERF_SEL_READ', 'GL2C_PERF_SEL_READ_128_REQ', + 'GL2C_PERF_SEL_READ_32_REQ', 'GL2C_PERF_SEL_READ_64_REQ', + 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', 'GL2C_PERF_SEL_REQ', + 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', 'GL2C_PERF_SEL_RETURN_ACK', + 'GL2C_PERF_SEL_RETURN_DATA', 'GL2C_PERF_SEL_SHARED_REQ', + 'GL2C_PERF_SEL_SRC_FIFO_FULL', 'GL2C_PERF_SEL_STREAM_REQ', + 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 'GL2C_PERF_SEL_TAG_READ_DST_STALL', 'GL2C_PERF_SEL_TAG_STALL', + 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'GL2C_PERF_SEL_UC_REQ', + 'GL2C_PERF_SEL_UNCACHED_WRITE', 'GL2C_PERF_SEL_VOL_REQ', + 'GL2C_PERF_SEL_WRITE', 'GL2C_PERF_SEL_WRITEBACK', + 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 'GL2C_PERF_SEL_WRITE_32_REQ', 'GL2C_PERF_SEL_WRITE_64_REQ', + 'GL2_CACHE_POLICIES', 'GL2_CACHE_POLICY_BYPASS', + 'GL2_CACHE_POLICY_LRU', 'GL2_CACHE_POLICY_NOA', + 'GL2_CACHE_POLICY_STREAM', 'GL2_NACKS', 'GL2_NACK_DATA_ERROR', + 'GL2_NACK_NO_FAULT', 'GL2_NACK_PAGE_FAULT', + 'GL2_NACK_PROTECTION_FAULT', 'GL2_OP', 'GL2_OP_ATOMIC_ADD_32', + 'GL2_OP_ATOMIC_ADD_64', 'GL2_OP_ATOMIC_ADD_RTN_32', + 'GL2_OP_ATOMIC_ADD_RTN_64', 'GL2_OP_ATOMIC_AND_32', + 'GL2_OP_ATOMIC_AND_64', 'GL2_OP_ATOMIC_AND_RTN_32', + 'GL2_OP_ATOMIC_AND_RTN_64', 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', + 'GL2_OP_ATOMIC_CMPSWAP_32', 'GL2_OP_ATOMIC_CMPSWAP_64', + 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', + 'GL2_OP_ATOMIC_COND_SUB_RTN_32', 'GL2_OP_ATOMIC_DEC_32', + 'GL2_OP_ATOMIC_DEC_64', 'GL2_OP_ATOMIC_DEC_RTN_32', + 'GL2_OP_ATOMIC_DEC_RTN_64', 'GL2_OP_ATOMIC_FADD_32', + 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FADD_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_32', + 'GL2_OP_ATOMIC_FCMPSWAP_64', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', + 'GL2_OP_ATOMIC_FMAX_32', 'GL2_OP_ATOMIC_FMAX_64', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FMAX_RTN_32', 'GL2_OP_ATOMIC_FMAX_RTN_64', + 'GL2_OP_ATOMIC_FMIN_32', 'GL2_OP_ATOMIC_FMIN_64', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FMIN_RTN_32', 'GL2_OP_ATOMIC_FMIN_RTN_64', + 'GL2_OP_ATOMIC_INC_32', 'GL2_OP_ATOMIC_INC_64', + 'GL2_OP_ATOMIC_INC_RTN_32', 'GL2_OP_ATOMIC_INC_RTN_64', + 'GL2_OP_ATOMIC_OR_32', 'GL2_OP_ATOMIC_OR_64', + 'GL2_OP_ATOMIC_OR_RTN_32', 'GL2_OP_ATOMIC_OR_RTN_64', + 'GL2_OP_ATOMIC_PK_ADD_BF16', 'GL2_OP_ATOMIC_PK_ADD_BF16_RTN', + 'GL2_OP_ATOMIC_PK_ADD_FP16', 'GL2_OP_ATOMIC_PK_ADD_FP16_RTN', + 'GL2_OP_ATOMIC_SMAX_32', 'GL2_OP_ATOMIC_SMAX_64', + 'GL2_OP_ATOMIC_SMAX_RTN_32', 'GL2_OP_ATOMIC_SMAX_RTN_64', + 'GL2_OP_ATOMIC_SMIN_32', 'GL2_OP_ATOMIC_SMIN_64', + 'GL2_OP_ATOMIC_SMIN_RTN_32', 'GL2_OP_ATOMIC_SMIN_RTN_64', + 'GL2_OP_ATOMIC_STORE_COND_RTN', 'GL2_OP_ATOMIC_SUB_32', + 'GL2_OP_ATOMIC_SUB_64', 'GL2_OP_ATOMIC_SUB_RTN_32', + 'GL2_OP_ATOMIC_SUB_RTN_64', 'GL2_OP_ATOMIC_SWAP_32', + 'GL2_OP_ATOMIC_SWAP_64', 'GL2_OP_ATOMIC_SWAP_RTN_32', + 'GL2_OP_ATOMIC_SWAP_RTN_64', 'GL2_OP_ATOMIC_UMAX_32', + 'GL2_OP_ATOMIC_UMAX_64', 'GL2_OP_ATOMIC_UMAX_8', + 'GL2_OP_ATOMIC_UMAX_RTN_32', 'GL2_OP_ATOMIC_UMAX_RTN_64', + 'GL2_OP_ATOMIC_UMIN_32', 'GL2_OP_ATOMIC_UMIN_64', + 'GL2_OP_ATOMIC_UMIN_8', 'GL2_OP_ATOMIC_UMIN_RTN_32', + 'GL2_OP_ATOMIC_UMIN_RTN_64', 'GL2_OP_ATOMIC_XOR_32', + 'GL2_OP_ATOMIC_XOR_64', 'GL2_OP_ATOMIC_XOR_RTN_32', + 'GL2_OP_ATOMIC_XOR_RTN_64', + 'GL2_OP_FORCE_EXISTING_DATA_TO_DECOMPRESS', 'GL2_OP_GL1_INV', + 'GL2_OP_GL2_INV', 'GL2_OP_GL2_WB', 'GL2_OP_GL2_WBINV', + 'GL2_OP_LOAD_RESERVE', 'GL2_OP_MASKS', 'GL2_OP_MASK_64', + 'GL2_OP_MASK_FLUSH_DENROM', 'GL2_OP_MASK_NO_RTN', + 'GL2_OP_NOP_ACK', 'GL2_OP_NOP_RTN0', 'GL2_OP_PROBE_FILTER', + 'GL2_OP_READ', 'GL2_OP_READ_COMPRESSION_KEY', + 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', 'GL2_OP_UTC_PROBE', + 'GL2_OP_WRITE', 'GL2_OP_WRITE_ZERO_SIZE', 'GLCompressionMode', + 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', + 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', + 'GLOBAL_STATUS_FLUSH_STATUS', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', + 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', + 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', + 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', + 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', + 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', + 'GRBMH_PERF_SEL', 'GRBMH_PERF_SEL_BCI_BUSY', + 'GRBMH_PERF_SEL_CB_BUSY', 'GRBMH_PERF_SEL_CB_CLEAN', + 'GRBMH_PERF_SEL_COUNT', 'GRBMH_PERF_SEL_DB_BUSY', + 'GRBMH_PERF_SEL_DB_CLEAN', 'GRBMH_PERF_SEL_EA_BUSY', + 'GRBMH_PERF_SEL_EA_LINK_BUSY', 'GRBMH_PERF_SEL_GE_BUSY', + 'GRBMH_PERF_SEL_GL1A_BUSY', 'GRBMH_PERF_SEL_GL1CC_BUSY', + 'GRBMH_PERF_SEL_GL1XCC_BUSY', 'GRBMH_PERF_SEL_GL2A_BUSY', + 'GRBMH_PERF_SEL_GL2C_BUSY', 'GRBMH_PERF_SEL_PA_BUSY', + 'GRBMH_PERF_SEL_PC_BUSY', 'GRBMH_PERF_SEL_RLC_BUSY', + 'GRBMH_PERF_SEL_SC_BUSY', 'GRBMH_PERF_SEL_SC_CLEAN', + 'GRBMH_PERF_SEL_SPI_BUSY', 'GRBMH_PERF_SEL_SX_BUSY', + 'GRBMH_PERF_SEL_TA_BUSY', 'GRBMH_PERF_SEL_TCP_BUSY', + 'GRBMH_PERF_SEL_USER_DEFINED', 'GRBMH_PERF_SEL_UTCL1_BUSY', + 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', + 'GRBM_PERF_SEL_BCI_BUSY', 'GRBM_PERF_SEL_CB_BUSY', + 'GRBM_PERF_SEL_CB_CLEAN', 'GRBM_PERF_SEL_CH_BUSY', + 'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPC_BUSY', + 'GRBM_PERF_SEL_CPF_BUSY', 'GRBM_PERF_SEL_CPG_BUSY', + 'GRBM_PERF_SEL_CP_BUSY', 'GRBM_PERF_SEL_CP_COHER_BUSY', + 'GRBM_PERF_SEL_CP_DMA_BUSY', 'GRBM_PERF_SEL_DB_BUSY', + 'GRBM_PERF_SEL_DB_CLEAN', 'GRBM_PERF_SEL_EA_BUSY', + 'GRBM_PERF_SEL_GE_BUSY', 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', + 'GRBM_PERF_SEL_GL1CC_BUSY', 'GRBM_PERF_SEL_GL1XCC_BUSY', + 'GRBM_PERF_SEL_GL2CC_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE', + 'GRBM_PERF_SEL_GUS_BUSY', 'GRBM_PERF_SEL_PA_BUSY', + 'GRBM_PERF_SEL_PC_BUSY', 'GRBM_PERF_SEL_PMM_BUSY', + 'GRBM_PERF_SEL_RLC_BUSY', 'GRBM_PERF_SEL_SC_BUSY', + 'GRBM_PERF_SEL_SDMA_BUSY', 'GRBM_PERF_SEL_SPI_BUSY', + 'GRBM_PERF_SEL_SX_BUSY', 'GRBM_PERF_SEL_TA_BUSY', + 'GRBM_PERF_SEL_TCP_BUSY', 'GRBM_PERF_SEL_USER_DEFINED', + 'GRBM_PERF_SEL_UTCL1_BUSY', 'GRBM_PERF_SEL_UTCL2_BUSY', + 'GREEN_LUT', 'GSTHREADID_SIZE', 'GS_OFF', 'GS_SCENARIO_A', + 'GS_SCENARIO_B', 'GS_SCENARIO_C', 'GS_SCENARIO_G', 'GS_STAGE_OFF', + 'GS_STAGE_ON', 'HDMICHARCLK_SRC_SEL', + 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', 'HDMICHARCLK_SRC_SEL_UNIPHYA', + 'HDMICHARCLK_SRC_SEL_UNIPHYB', 'HDMICHARCLK_SRC_SEL_UNIPHYC', + 'HDMICHARCLK_SRC_SEL_UNIPHYD', 'HDMISTREAMCLK_SRC_SEL', + 'HDMI_ACP_NOT_SEND', 'HDMI_ACP_PKT_SEND', 'HDMI_ACP_SEND', + 'HDMI_ACR_0_MULTIPLE_RESERVED', 'HDMI_ACR_1_MULTIPLE', + 'HDMI_ACR_2_MULTIPLE', 'HDMI_ACR_3_MULTIPLE_RESERVED', + 'HDMI_ACR_4_MULTIPLE', 'HDMI_ACR_5_MULTIPLE_RESERVED', + 'HDMI_ACR_6_MULTIPLE_RESERVED', 'HDMI_ACR_7_MULTIPLE_RESERVED', + 'HDMI_ACR_AUDIO_PRIORITY', 'HDMI_ACR_CONT', + 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', + 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', + 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', + 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', + 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', + 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', + 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', + 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', + 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', + 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', + 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', + 'HDMI_AUDIO_INFO_SEND', + 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', + 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE', + 'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE', + 'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 'HDMI_DEEP_COLOR_DEPTH_48BPP', 'HDMI_DEFAULT_PAHSE', + 'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1', + 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK', + 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', + 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', + 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_GC_AVMUTE', + 'HDMI_GC_AVMUTE_CONT', 'HDMI_GC_AVMUTE_CONT_DISABLE', + 'HDMI_GC_AVMUTE_CONT_ENABLE', 'HDMI_GC_AVMUTE_SET', + 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', 'HDMI_GC_CONT_DISABLE', + 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', 'HDMI_GC_PKT_SEND', + 'HDMI_GC_SEND', 'HDMI_GENERIC_CONT', 'HDMI_GENERIC_CONT_DISABLE', + 'HDMI_GENERIC_CONT_ENABLE', 'HDMI_GENERIC_NOT_SEND', + 'HDMI_GENERIC_PKT_SEND', 'HDMI_GENERIC_SEND', 'HDMI_ISRC_CONT', + 'HDMI_ISRC_CONT_DISABLE', 'HDMI_ISRC_CONT_ENABLE', + 'HDMI_ISRC_NOT_SEND', 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', + 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', + 'HDMI_METADATA_ENABLE', 'HDMI_METADATA_NOT_SEND', + 'HDMI_METADATA_PKT_SEND', 'HDMI_MPEG_INFO_CONT', + 'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE', + 'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND', + 'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', + 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', + 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', + 'HDMI_PACKET_LINE_REFERENCE', 'HDMI_PACKING_PHASE_OVERRIDE', + 'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW', + 'HDMI_PKT_LINE_REF_OTGSOF', 'HDMI_PKT_LINE_REF_VSYNC', + 'HDMI_SEND_MAX_AUDIO_PACKETS', 'HDP_ENDIAN_8IN16', + 'HDP_ENDIAN_8IN32', 'HDP_ENDIAN_8IN64', 'HDP_ENDIAN_NONE', + 'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0', + 'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON', + 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', + 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', + 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HPO_SRC0', 'HPO_SRC_RESERVED', + 'HPO_TOP_CLOCK_GATING_DIS', 'HPO_TOP_CLOCK_GATING_DISABLE', + 'HPO_TOP_CLOCK_GATING_EN', + 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', + 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', + 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', + 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', + 'HPO_TOP_PERMANENT_DISPCLK', 'HPO_TOP_PERMANENT_HDMICHARCLK0', + 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', 'HPO_TOP_PERMANENT_SOCCLK', + 'HPO_TOP_REGISTER_GATED_DISPCLK', + 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', + 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', 'HPO_TOP_TEST_CLK_SEL', + 'HPO_TOP_TEST_CLOCK_RESERVED', 'HS_GS', 'HS_STAGE_OFF', + 'HS_STAGE_ON', 'HUBP_3DLUT_ADDRESSING_MODE', + 'HUBP_3DLUT_SIMPLE_LINEAR', 'HUBP_3DLUT_SW_LINEAR', + 'HUBP_BLANK_EN', 'HUBP_BLANK_SW_ASSERT', 'HUBP_BLANK_SW_DEASSERT', + 'HUBP_IN_ACTIVE', 'HUBP_IN_BLANK', 'HUBP_IN_VBLANK', + 'HUBP_MEASURE_WIN_MODE_DCFCLK', 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', 'HUBP_NO_OUTSTANDING_REQ', + 'HUBP_SOFT_RESET', 'HUBP_SOFT_RESET_OFF', 'HUBP_SOFT_RESET_ON', + 'HUBP_TTU_DISABLE', 'HUBP_TTU_DISABLED', 'HUBP_TTU_ENABLED', + 'HUBP_VREADY_AT_OR_AFTER_VSYNC', 'HUBP_VTG_SEL', + 'HW_MIRRORING_DISABLE', 'HW_MIRRORING_ENABLE', 'H_MIRROR_EN', + 'Hdp_SurfaceEndian', 'ID_STREAM_DISABLE_ACKED', + 'ID_STREAM_DISABLE_NO_ACK', 'IHC_INTERRUPT_DEST', + 'IHC_INTERRUPT_LINE_STATUS', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_INNER_COVERAGE', + 'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG', + 'INST_ID_HW_TRAP', 'INST_ID_HW_TRAP_GET_TBA', 'INST_ID_KILL_SEQ', + 'INST_ID_PRIV_START', 'INST_ID_SPI_WREXEC', + 'INST_ID_TTRACE_NEW_PC_MSG', 'INTERRUPT_LINE_ASSERTED', + 'INTERRUPT_LINE_NOT_ASSERTED', 'INTERRUPT_SENT_TO_DMCUB', + 'INTERRUPT_SENT_TO_IH', 'INT_DISABLED', 'INT_ENABLED', + 'INT_LEVEL', 'INT_MASK', 'INT_PULSE', 'INVALID_REG_ACCESS_TYPE', + 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', + 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', + 'IQ_SCH_WAVE_MSG', 'ISHARP_FMT_MODE_0', 'ISHARP_FMT_MODE_1', + 'ISHARP_FMT_MODE_ENUM', 'ISHARP_LBA_MODE_0', 'ISHARP_LBA_MODE_1', + 'ISHARP_LBA_MODE_ENUM', 'ISHARP_NOISEDET_MODE_0', + 'ISHARP_NOISEDET_MODE_1', 'ISHARP_NOISEDET_MODE_2', + 'ISHARP_NOISEDET_MODE_3', 'ISHARP_NOISEDET_MODE_ENUM', + 'JITTER_REMOVE_DISABLE', 'LATE_Z', 'LB_ALPHA_DISABLE', + 'LB_ALPHA_EN', 'LB_ALPHA_ENABLE', 'LB_INTERLEAVE_DISABLE', + 'LB_INTERLEAVE_EN', 'LB_INTERLEAVE_ENABLE', 'LB_MEMORY_CONFIG', + 'LB_MEMORY_CONFIG_0', 'LB_MEMORY_CONFIG_1', 'LB_MEMORY_CONFIG_2', + 'LB_MEMORY_CONFIG_3', 'LEGACY_PIPE_INTERLEAVE', + 'LEGACY_PIPE_INTERLEAVE_256B', 'LEGACY_PIPE_INTERLEAVE_512B', + 'LINESTRIP', 'LSDMA_PERF_SEL', 'LSDMA_PERF_SEL_ATCL2_FREE', + 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', + 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', + 'LSDMA_PERF_SEL_ATCL2_RET_ACK', 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', + 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', + 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', + 'LSDMA_PERF_SEL_CE_AFIFO_FULL', 'LSDMA_PERF_SEL_CE_BUSY', + 'LSDMA_PERF_SEL_CE_BUSY_END', 'LSDMA_PERF_SEL_CE_BUSY_START', + 'LSDMA_PERF_SEL_CE_DST_IDLE', 'LSDMA_PERF_SEL_CE_INFO1_FULL', + 'LSDMA_PERF_SEL_CE_INFO_FULL', 'LSDMA_PERF_SEL_CE_IN_IDLE', + 'LSDMA_PERF_SEL_CE_L1_STALL', 'LSDMA_PERF_SEL_CE_L1_WR_VLD', + 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', + 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', + 'LSDMA_PERF_SEL_CE_OUT_IDLE', 'LSDMA_PERF_SEL_CE_RD_STALL', + 'LSDMA_PERF_SEL_CE_RREQ_IDLE', 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', + 'LSDMA_PERF_SEL_CE_WREQ_IDLE', 'LSDMA_PERF_SEL_CE_WR_IDLE', + 'LSDMA_PERF_SEL_CE_WR_STALL', 'LSDMA_PERF_SEL_CMD_OP_END', + 'LSDMA_PERF_SEL_CMD_OP_MATCH', 'LSDMA_PERF_SEL_CMD_OP_START', + 'LSDMA_PERF_SEL_CTX_CHANGE', + 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'LSDMA_PERF_SEL_CYCLE', + 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', + 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', + 'LSDMA_PERF_SEL_DOORBELL', 'LSDMA_PERF_SEL_DRAM_ECC', + 'LSDMA_PERF_SEL_DUMMY_0', 'LSDMA_PERF_SEL_DUMMY_1', + 'LSDMA_PERF_SEL_EX_IDLE', + 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'LSDMA_PERF_SEL_F32_L1_WR_VLD', + 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 'LSDMA_PERF_SEL_GFX_SELECT', 'LSDMA_PERF_SEL_IB_CMD_FULL', + 'LSDMA_PERF_SEL_IB_CMD_IDLE', 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_IDLE', + 'LSDMA_PERF_SEL_INT_IDLE', 'LSDMA_PERF_SEL_INT_REQ_COUNT', + 'LSDMA_PERF_SEL_INT_REQ_STALL', + 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', + 'LSDMA_PERF_SEL_INT_RESP_RETRY', + 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', + 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', + 'LSDMA_PERF_SEL_L1_INV_MIDDLE', 'LSDMA_PERF_SEL_L1_RDL2_IDLE', + 'LSDMA_PERF_SEL_L1_RDMC_IDLE', 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', + 'LSDMA_PERF_SEL_L1_RD_INV_EN', 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', + 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', + 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', + 'LSDMA_PERF_SEL_L1_WRL2_IDLE', 'LSDMA_PERF_SEL_L1_WRMC_IDLE', + 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', 'LSDMA_PERF_SEL_L1_WR_INV_EN', + 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', + 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', + 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', + 'LSDMA_PERF_SEL_MC_RD_COUNT', 'LSDMA_PERF_SEL_MC_RD_IDLE', + 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 'LSDMA_PERF_SEL_MC_RD_RET_STALL', 'LSDMA_PERF_SEL_MC_WR_COUNT', + 'LSDMA_PERF_SEL_MC_WR_IDLE', + 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', + 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', + 'LSDMA_PERF_SEL_NACK_GEN_ERR', 'LSDMA_PERF_SEL_NUM_PACKET', + 'LSDMA_PERF_SEL_PAGE_SELECT', 'LSDMA_PERF_SEL_RB_CMD_FULL', + 'LSDMA_PERF_SEL_RB_CMD_IDLE', 'LSDMA_PERF_SEL_RB_EMPTY', + 'LSDMA_PERF_SEL_RB_FULL', 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_RB_RPTR_WB', + 'LSDMA_PERF_SEL_RB_RPTR_WRAP', 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', + 'LSDMA_PERF_SEL_RB_WPTR_WRAP', 'LSDMA_PERF_SEL_RD_BA_RTR', + 'LSDMA_PERF_SEL_REG_IDLE', 'LSDMA_PERF_SEL_RLC0_SELECT', + 'LSDMA_PERF_SEL_RLC1_SELECT', 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', + 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', + 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'LSDMA_PERF_SEL_SEM_IDLE', + 'LSDMA_PERF_SEL_SEM_REQ_COUNT', 'LSDMA_PERF_SEL_SEM_REQ_STALL', + 'LSDMA_PERF_SEL_SEM_RESP_FAIL', + 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 'LSDMA_PERF_SEL_SEM_RESP_PASS', 'LSDMA_PERF_SEL_SRBM_REG_SEND', + 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', + 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', + 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', 'LSDMA_PERF_SEL_WR_BA_RTR', + 'LUMA_KEYER_ENABLE', 'LUMA_KEY_DIS', 'LUMA_KEY_EN', + 'LUT_2CFG_MEMORY_A', 'LUT_2CFG_MEMORY_B', 'LUT_2CFG_NO_MEMORY', + 'LUT_2_MODE_BYPASS', 'LUT_2_MODE_RAMA_LUT', 'LUT_2_MODE_RAMB_LUT', + 'LUT_4CFG_MEMORY_A', 'LUT_4CFG_MEMORY_B', 'LUT_4CFG_NO_MEMORY', + 'LUT_4CFG_ROM_A', 'LUT_4CFG_ROM_B', 'LUT_4_MODE_BYPASS', + 'LUT_4_MODE_RAMA_LUT', 'LUT_4_MODE_RAMB_LUT', + 'LUT_4_MODE_ROMA_LUT', 'LUT_4_MODE_ROMB_LUT', + 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', + 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', + 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', + 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', + 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', + 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', + 'MASTER_UPDATE_LOCK_SEL', 'MASTER_UPDATE_LOCK_SEL_0', + 'MASTER_UPDATE_LOCK_SEL_1', 'MASTER_UPDATE_LOCK_SEL_2', + 'MASTER_UPDATE_LOCK_SEL_3', 'MASTER_UPDATE_LOCK_SEL_RESERVED4', + 'MASTER_UPDATE_LOCK_SEL_RESERVED5', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', + 'MATRIX_MODE_0', 'MATRIX_MODE_1', 'MATRIX_MODE_ENUM', + 'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH', 'MEM_ARB_MODE_FIXED', + 'MEM_ARB_MODE_WEIGHT', 'MEM_POWER_DIS_MODE_DISABLE', + 'MEM_POWER_DIS_MODE_ENABLE', 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', + 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', 'MEM_POWER_FORCE_MODE_OFF', + 'MEM_POWER_FORCE_MODE_SHUT_DOWN', 'MEM_POWER_STATUS_DEEP_SLEEP', + 'MEM_POWER_STATUS_LIGHT_SLEEP', 'MEM_POWER_STATUS_ON', + 'MEM_POWER_STATUS_SHUT_DOWN', 'MEM_PWR_DIS_CTRL', + 'MEM_PWR_DIS_MODE', 'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2', + 'MEM_PWR_FORCE_MODE', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2', + 'MEM_PWR_STATUS', 'METADATA_HUBP_SEL', 'METADATA_HUBP_SEL_0', + 'METADATA_HUBP_SEL_1', 'METADATA_HUBP_SEL_2', + 'METADATA_HUBP_SEL_3', 'METADATA_HUBP_SEL_RESERVED', + 'METADATA_STREAM_DP', 'METADATA_STREAM_DVE', + 'METADATA_STREAM_TYPE_SEL', 'META_CHUNK_SIZE', + 'META_CHUNK_SIZE_1KB', 'META_CHUNK_SIZE_2KB', + 'META_CHUNK_SIZE_4KB', 'META_CHUNK_SIZE_8KB', 'META_LINEAR', + 'META_SURF_LINEAR', 'META_SURF_TILED', 'ME_ID0', 'ME_ID1', + 'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', + 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', + 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', + 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MIN_CHUNK_SIZE', + 'MIN_CHUNK_SIZE_1024B', 'MIN_CHUNK_SIZE_256B', + 'MIN_CHUNK_SIZE_512B', 'MIN_META_CHUNK_SIZE', + 'MIN_META_CHUNK_SIZE_128B', 'MIN_META_CHUNK_SIZE_256B', + 'MIN_META_CHUNK_SIZE_64B', 'MONO_10LSB', 'MONO_10MSB', + 'MONO_12LSB', 'MONO_12MSB', 'MONO_16', 'MONO_2BIT', 'MONO_8', + 'MPCC_BG_COLOR_BPC', 'MPCC_BG_COLOR_BPC_10bit', + 'MPCC_BG_COLOR_BPC_11bit', 'MPCC_BG_COLOR_BPC_12bit', + 'MPCC_BG_COLOR_BPC_8bit', 'MPCC_BG_COLOR_BPC_9bit', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', 'MPCC_CONTROL_MPCC_MODE', + 'MPCC_CONTROL_MPCC_MODE_BYPASS', + 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', + 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', + 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', + 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM', + 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', + 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', 'MPCC_GAMUT_REMAP_MODE_0', + 'MPCC_GAMUT_REMAP_MODE_1', 'MPCC_GAMUT_REMAP_MODE_2', + 'MPCC_GAMUT_REMAP_MODE_ENUM', 'MPCC_GAMUT_REMAP_MODE_RSV', + 'MPCC_MCM_3DLUT_17CUBE', 'MPCC_MCM_3DLUT_30BIT', + 'MPCC_MCM_3DLUT_30BIT_ENUM', 'MPCC_MCM_3DLUT_36BIT', + 'MPCC_MCM_3DLUT_9CUBE', 'MPCC_MCM_3DLUT_RAM_SEL', + 'MPCC_MCM_3DLUT_SIZE_ENUM', 'MPCC_MCM_GAMMA_LUT_BYPASS', + 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', + 'MPCC_MCM_GAMMA_LUT_MODE_ENUM', + 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM', 'MPCC_MCM_GAMMA_LUT_RAMA', + 'MPCC_MCM_GAMMA_LUT_RAMB', 'MPCC_MCM_GAMMA_LUT_RAM_LUT', + 'MPCC_MCM_GAMMA_LUT_RESERVED_1', 'MPCC_MCM_GAMMA_LUT_RESERVED_3', + 'MPCC_MCM_GAMMA_LUT_SEL_ENUM', + 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM', + 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S2_13', + 'MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S3_12', + 'MPCC_MCM_GAMUT_REMAP_MODE_0', 'MPCC_MCM_GAMUT_REMAP_MODE_1', + 'MPCC_MCM_GAMUT_REMAP_MODE_2', 'MPCC_MCM_GAMUT_REMAP_MODE_ENUM', + 'MPCC_MCM_GAMUT_REMAP_MODE_RSV', 'MPCC_MCM_LUT_2_MODE_BYPASS', + 'MPCC_MCM_LUT_2_MODE_ENUM', 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', + 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', 'MPCC_MCM_LUT_ALL_USE_R', + 'MPCC_MCM_LUT_BLUE_LUT', 'MPCC_MCM_LUT_CONFIG_MODE', + 'MPCC_MCM_LUT_DIFFERENT_RGB', 'MPCC_MCM_LUT_DISABLE_DEBUG', + 'MPCC_MCM_LUT_ENABLE_DEBUG', 'MPCC_MCM_LUT_GREEN_LUT', + 'MPCC_MCM_LUT_NUM_SEG', 'MPCC_MCM_LUT_RAMA_ACCESS', + 'MPCC_MCM_LUT_RAMB_ACCESS', 'MPCC_MCM_LUT_RAM_SEL', + 'MPCC_MCM_LUT_READ_COLOR_SEL', 'MPCC_MCM_LUT_READ_DBG', + 'MPCC_MCM_LUT_RED_LUT', 'MPCC_MCM_LUT_SEGMENTS_1', + 'MPCC_MCM_LUT_SEGMENTS_128', 'MPCC_MCM_LUT_SEGMENTS_16', + 'MPCC_MCM_LUT_SEGMENTS_2', 'MPCC_MCM_LUT_SEGMENTS_32', + 'MPCC_MCM_LUT_SEGMENTS_4', 'MPCC_MCM_LUT_SEGMENTS_64', + 'MPCC_MCM_LUT_SEGMENTS_8', 'MPCC_MCM_MEM_PWR_FORCE_DIS', + 'MPCC_MCM_MEM_PWR_FORCE_DS', 'MPCC_MCM_MEM_PWR_FORCE_ENUM', + 'MPCC_MCM_MEM_PWR_FORCE_LS', 'MPCC_MCM_MEM_PWR_FORCE_SD', + 'MPCC_MCM_MEM_PWR_STATE_DS', 'MPCC_MCM_MEM_PWR_STATE_ENUM', + 'MPCC_MCM_MEM_PWR_STATE_LS', 'MPCC_MCM_MEM_PWR_STATE_ON', + 'MPCC_MCM_MEM_PWR_STATE_SD', 'MPCC_MCM_RAM0_ACCESS', + 'MPCC_MCM_RAM1_ACCESS', 'MPCC_MCM_RAM2_ACCESS', + 'MPCC_MCM_RAM3_ACCESS', 'MPCC_OGAM_ALL_USE_R', + 'MPCC_OGAM_BLUE_LUT', 'MPCC_OGAM_DIFFERENT_RGB', + 'MPCC_OGAM_DISABLE_DEBUG', 'MPCC_OGAM_DISABLE_PWL', + 'MPCC_OGAM_ENABLE_DEBUG', 'MPCC_OGAM_ENABLE_PWL', + 'MPCC_OGAM_GREEN_LUT', 'MPCC_OGAM_LUT_2CFG_MEMORY_A', + 'MPCC_OGAM_LUT_2CFG_MEMORY_B', 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', + 'MPCC_OGAM_LUT_2_CONFIG_ENUM', 'MPCC_OGAM_LUT_CONFIG_MODE', + 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', + 'MPCC_OGAM_LUT_RAM_SEL', 'MPCC_OGAM_LUT_READ_COLOR_SEL', + 'MPCC_OGAM_LUT_READ_DBG', 'MPCC_OGAM_LUT_SEL_ENUM', + 'MPCC_OGAM_MODE_0', 'MPCC_OGAM_MODE_2', + 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM', 'MPCC_OGAM_MODE_RSV', + 'MPCC_OGAM_MODE_RSV1', 'MPCC_OGAM_NUM_SEG', 'MPCC_OGAM_RAMA', + 'MPCC_OGAM_RAMA_ACCESS', 'MPCC_OGAM_RAMB', + 'MPCC_OGAM_RAMB_ACCESS', 'MPCC_OGAM_RED_LUT', + 'MPCC_OGAM_SEGMENTS_1', 'MPCC_OGAM_SEGMENTS_128', + 'MPCC_OGAM_SEGMENTS_16', 'MPCC_OGAM_SEGMENTS_2', + 'MPCC_OGAM_SEGMENTS_32', 'MPCC_OGAM_SEGMENTS_4', + 'MPCC_OGAM_SEGMENTS_64', 'MPCC_OGAM_SEGMENTS_8', + 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN', + 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', + 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_EN', 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_MODE', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', + 'MPC_CFG_3DLUT_FL_FORMAT', 'MPC_CFG_3DLUT_FL_FORMAT_0', + 'MPC_CFG_3DLUT_FL_FORMAT_1', 'MPC_CFG_3DLUT_FL_FORMAT_2', + 'MPC_CFG_3DLUT_FL_MODE', 'MPC_CFG_3DLUT_FL_MODE_0', + 'MPC_CFG_3DLUT_FL_MODE_1', 'MPC_CFG_3DLUT_FL_MODE_2', + 'MPC_CFG_3DLUT_FL_MODE_3', 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', 'MPC_CFG_MPC_TEST_CLK_SEL', + 'MPC_CFG_MPC_TEST_CLK_SEL_0', 'MPC_CFG_MPC_TEST_CLK_SEL_1', + 'MPC_CFG_MPC_TEST_CLK_SEL_2', 'MPC_CFG_MPC_TEST_CLK_SEL_3', + 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN', + 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', + 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', + 'MPC_CRC_CALC_INTERLACE_MODE', 'MPC_CRC_CALC_MODE', + 'MPC_CRC_CALC_STEREO_MODE', 'MPC_CRC_CONTINUOUS_MODE', + 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', + 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', + 'MPC_CRC_INTERLACE_MODE_BOTTOM', 'MPC_CRC_INTERLACE_MODE_TOP', + 'MPC_CRC_ONE_SHOT_MODE', 'MPC_CRC_SOURCE_SELECT', + 'MPC_CRC_SOURCE_SEL_DPP', 'MPC_CRC_SOURCE_SEL_DWB', + 'MPC_CRC_SOURCE_SEL_OPP', 'MPC_CRC_SOURCE_SEL_OTHER', + 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', + 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', + 'MPC_CRC_STEREO_MODE_LEFT', 'MPC_CRC_STEREO_MODE_RIGHT', + 'MPC_OCSC_COEF_FORMAT', 'MPC_OCSC_COEF_FORMAT_S2_13', + 'MPC_OCSC_COEF_FORMAT_S3_12', + 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN', + 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', + 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', + 'MPC_OUT_CSC_MODE', 'MPC_OUT_CSC_MODE_0', 'MPC_OUT_CSC_MODE_1', + 'MPC_OUT_CSC_MODE_2', 'MPC_OUT_CSC_MODE_RSV', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', + 'MPC_OUT_RATE_CONTROL_DISABLE_SET', + 'MPC_OUT_RATE_CONTROL_SET_DISABLE', + 'MPC_OUT_RATE_CONTROL_SET_ENABLE', + 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', + 'MTYPE', 'MTYPE_CC', 'MTYPE_C_RO_S', 'MTYPE_C_RO_US', + 'MTYPE_C_RW_S', 'MTYPE_C_RW_US', 'MTYPE_NC', 'MTYPE_RESERVED_1', + 'MTYPE_RESERVED_5', 'MTYPE_RESERVED_7', 'MTYPE_UC', 'MTYPE_WC', + 'MULTIPLE_BY1', 'MULTIPLE_BY2', 'MULTIPLE_BY3_RESERVED', + 'MULTIPLE_BY4', 'MULTIPLE_RESERVED', 'MULT_16', 'MULT_8', + 'MemArbMode', 'NON_BYPASS', 'NOT_FORCE_THE_CLOCK_DISABLED', + 'NOT_SENT', 'NO_DIST', 'NO_DIV', 'NO_FORCE', 'NO_FORCE_REQ', + 'NO_FORCE_REQUEST', 'NO_MIN_CHUNK_SIZE', 'NO_MIN_META_CHUNK_SIZE', + 'NO_OUTSTANDING_REQ', 'NUM_SIMD_PER_CU', 'OBUF_BYPASS_DIS', + 'OBUF_BYPASS_EN', 'OBUF_BYPASS_SEL', 'OBUF_FULL', + 'OBUF_FULL_RECOUT', 'OBUF_HALF_RECOUT', + 'OBUF_IS_HALF_RECOUT_WIDTH_SEL', 'OBUF_RECOUT', + 'OBUF_USE_FULL_BUFFER_SEL', 'OFFCHIP_HS_DEALLOC', 'OFF_SEQ', + 'OKAY', 'OKAY_NODATA', 'OMODE_BLEND', 'OMODE_O_THEN_B', + 'OMODE_P_THEN_O_THEN_B', 'OMODE_RESERVED_3', 'ON_SEQ', + 'OPPBUF_DISPLAY_SEGMENTATION', + 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', + 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', + 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', + 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', + 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', + 'OPP_PIPE_CLOCK_DISABLE', 'OPP_PIPE_CLOCK_ENABLE', + 'OPP_PIPE_CLOCK_ENABLE_CONTROL', 'OPP_PIPE_CRC_CONT_EN', + 'OPP_PIPE_CRC_DISABLE', 'OPP_PIPE_CRC_EN', 'OPP_PIPE_CRC_ENABLE', + 'OPP_PIPE_CRC_INTERLACE_EN', + 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', + 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', + 'OPP_PIPE_CRC_INTERLACE_MODE', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', + 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', 'OPP_PIPE_CRC_MODE_CONTINUOUS', + 'OPP_PIPE_CRC_MODE_ONE_SHOT', 'OPP_PIPE_CRC_ONE_SHOT_PENDING', + 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', + 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', + 'OPP_PIPE_CRC_PIXEL_SELECT', + 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', + 'OPP_PIPE_CRC_SOURCE_SELECT', 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', + 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', 'OPP_PIPE_CRC_STEREO_EN', + 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', + 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', + 'OPP_PIPE_CRC_STEREO_MODE', + 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', + 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', + 'OPP_PIPE_CRC_STEREO_MODE_LEFT', 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', + 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL', + 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', + 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', 'OPP_TEST_CLK_SEL_CONTROL', + 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', + 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', + 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', + 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', + 'OPP_TEST_CLK_SEL_DISPCLK_P', 'OPP_TEST_CLK_SEL_DISPCLK_R', + 'OPP_TEST_CLK_SEL_RESERVED0', 'OPP_TEST_CLK_SEL_RESERVED1', + 'OPP_TEST_CLK_SEL_RESERVED2', 'OPP_TEST_CLK_SEL_RESERVED3', + 'OPP_TOP_CLOCK_DISABLED_STATUS', 'OPP_TOP_CLOCK_ENABLED_STATUS', + 'OPP_TOP_CLOCK_ENABLE_STATUS', 'OPP_TOP_CLOCK_GATING_CONTROL', + 'OPP_TOP_CLOCK_GATING_DISABLED', 'OPP_TOP_CLOCK_GATING_ENABLED', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', + 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX', + 'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT', + 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', + 'OTG_ADD_PIXEL', 'OTG_ADD_PIXEL_FORCE', 'OTG_ADD_PIXEL_NOOP', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', + 'OTG_CONTROL_OTG_MASTER_EN', 'OTG_CONTROL_OTG_MASTER_EN_FALSE', + 'OTG_CONTROL_OTG_MASTER_EN_TRUE', 'OTG_CONTROL_OTG_OUT_MUX', + 'OTG_CONTROL_OTG_OUT_MUX_0', 'OTG_CONTROL_OTG_OUT_MUX_1', + 'OTG_CONTROL_OTG_OUT_MUX_2', 'OTG_CONTROL_OTG_START_POINT_CNTL', + 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', + 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC1_EN', 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', + 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', 'OTG_CRC_CNTL_OTG_CRC_CONT_EN', + 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', + 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', 'OTG_CRC_CNTL_OTG_CRC_EN', + 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', + 'OTG_DIG_UPDATE_VCOUNT_0', 'OTG_DIG_UPDATE_VCOUNT_1', + 'OTG_DIG_UPDATE_VCOUNT_MODE', 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE', + 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE_0', + 'OTG_DLPC_CONTROL_OTG_RESYNC_MODE_1', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', + 'OTG_DROP_PIXEL', 'OTG_DROP_PIXEL_FORCE', 'OTG_DROP_PIXEL_NOOP', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', + 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL', + 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL', + 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD', + 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL', + 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', 'OTG_GLOBAL_UPDATE_LOCK_EN', + 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', 'OTG_GSL_MASTER_MODE', + 'OTG_GSL_MASTER_MODE_0', 'OTG_GSL_MASTER_MODE_1', + 'OTG_GSL_MASTER_MODE_2', 'OTG_GSL_MASTER_MODE_3', + 'OTG_HORZ_REPETITION_COUNT', 'OTG_HORZ_REPETITION_COUNT_0', + 'OTG_HORZ_REPETITION_COUNT_1', 'OTG_HORZ_REPETITION_COUNT_10', + 'OTG_HORZ_REPETITION_COUNT_11', 'OTG_HORZ_REPETITION_COUNT_12', + 'OTG_HORZ_REPETITION_COUNT_13', 'OTG_HORZ_REPETITION_COUNT_14', + 'OTG_HORZ_REPETITION_COUNT_15', 'OTG_HORZ_REPETITION_COUNT_2', + 'OTG_HORZ_REPETITION_COUNT_3', 'OTG_HORZ_REPETITION_COUNT_4', + 'OTG_HORZ_REPETITION_COUNT_5', 'OTG_HORZ_REPETITION_COUNT_6', + 'OTG_HORZ_REPETITION_COUNT_7', 'OTG_HORZ_REPETITION_COUNT_8', + 'OTG_HORZ_REPETITION_COUNT_9', 'OTG_H_SYNC_A_POL', + 'OTG_H_SYNC_A_POL_HIGH', 'OTG_H_SYNC_A_POL_LOW', + 'OTG_H_TIMING_DIV_MODE', 'OTG_H_TIMING_DIV_MODE_AUTO', + 'OTG_H_TIMING_DIV_MODE_DIV_BY2', 'OTG_H_TIMING_DIV_MODE_DIV_BY4', + 'OTG_H_TIMING_DIV_MODE_MANUAL', 'OTG_H_TIMING_DIV_MODE_NOAUTO', + 'OTG_H_TIMING_DIV_MODE_NO_DIV', 'OTG_H_TIMING_DIV_MODE_RESERVED', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', + 'OTG_MASTER_UPDATE_LOCK_DB_EN', 'OTG_MASTER_UPDATE_LOCK_DISABLE', + 'OTG_MASTER_UPDATE_LOCK_ENABLE', 'OTG_MASTER_UPDATE_LOCK_GSL_EN', + 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', + 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', + 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', + 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', + 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', + 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL', + 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', + 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGA_FREQUENCY_SELECT', 'OTG_TRIGA_FREQUENCY_SELECT_0', + 'OTG_TRIGA_FREQUENCY_SELECT_1', 'OTG_TRIGA_FREQUENCY_SELECT_2', + 'OTG_TRIGA_FREQUENCY_SELECT_3', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGB_FREQUENCY_SELECT', 'OTG_TRIGB_FREQUENCY_SELECT_0', + 'OTG_TRIGB_FREQUENCY_SELECT_1', 'OTG_TRIGB_FREQUENCY_SELECT_2', + 'OTG_TRIGB_FREQUENCY_SELECT_3', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', + 'OTG_VUPDATE_BLOCK_DISABLE', 'OTG_VUPDATE_BLOCK_DISABLE_OFF', + 'OTG_VUPDATE_BLOCK_DISABLE_ON', 'OTG_V_SYNC_A_POL', + 'OTG_V_SYNC_A_POL_HIGH', 'OTG_V_SYNC_A_POL_LOW', + 'OTG_V_SYNC_MODE', 'OTG_V_SYNC_MODE_HBLANK', + 'OTG_V_SYNC_MODE_HSYNC', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', + 'OUTPUT_LINE', 'OUTPUT_POINT', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OUTSTANDING_REQ', + 'OVERRUN', 'OreoMode', 'PART_FRAC_EVEN', 'PART_FRAC_ODD', + 'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PC_PERFCNT_SEL', + 'PC_PERF_GE_GSDONE', 'PC_PERF_GL1_RTN_CNT_GT512', + 'PC_PERF_GL1_RTN_CNT_GT768', 'PC_PERF_GL1_RTN_CNT_GTE1', + 'PC_PERF_GRBM_BUSY', 'PC_PERF_LWC0_PC_MEM_READ_STALL', + 'PC_PERF_LWC0_PKR2_SA_BDRY_CROSSING', + 'PC_PERF_LWC0_PKR3_SA_BDRY_CROSSING', + 'PC_PERF_LWC0_PROBE_ORDER_STALL', + 'PC_PERF_LWC1_PC_MEM_READ_STALL', + 'PC_PERF_LWC1_PKR0_SA_BDRY_CROSSING', + 'PC_PERF_LWC1_PKR1_SA_BDRY_CROSSING', + 'PC_PERF_LWC1_PROBE_ORDER_STALL', + 'PC_PERF_MW_CACHE_CNTL_FULL_STALL', 'PC_PERF_MW_CACHE_HIT', + 'PC_PERF_MW_CACHE_MISS', 'PC_PERF_MW_CACHE_REUSE', + 'PC_PERF_MW_DEALLOC_HIT', 'PC_PERF_MW_DLINE_ALLOC', + 'PC_PERF_MW_DLINE_DEALLOC', 'PC_PERF_MW_GL1H_NUM_REQS', + 'PC_PERF_MW_GL1H_REQ_FREEZE', 'PC_PERF_MW_PHY_DLINE_FULL_STALL', + 'PC_PERF_MW_PROBE_CNT_FREEZE', 'PC_PERF_MW_RTN_ADDR_FREEZE', + 'PC_PERF_MW_STAMP_LIMIT_STALL', 'PC_PERF_MW_TAGLINE_ALLOC', + 'PC_PERF_MW_TAGLINE_DEALLOC', 'PC_PERF_NUM_PSWAVE', + 'PC_PERF_PC_LDS_CNTL_VALID0', 'PC_PERF_PC_LDS_CNTL_VALID1', + 'PC_PERF_PC_LDS_VERTEX_REUSE0', 'PC_PERF_PC_LDS_VERTEX_REUSE1', + 'PC_PERF_PC_MEM_BANK_CONF0', 'PC_PERF_PC_MEM_BANK_CONF1', + 'PC_PERF_PC_SPI_PROBE_FREEZE', + 'PC_PERF_PC_SPI_PROBE_OUT_OF_CREDIT', 'PC_PERF_PKR0_FPOSG_EQ1', + 'PC_PERF_PKR0_FPOSG_GT1', 'PC_PERF_PKR0_FPOSG_GT128', + 'PC_PERF_PKR0_FPOSG_GT16', 'PC_PERF_PKR0_FPOSG_GT64', + 'PC_PERF_PKR0_FPOSG_OUT_OF_WAVE', + 'PC_PERF_PKR0_GSDONE_WHILE_IDLE', 'PC_PERF_PKR0_NUM_PROBES', + 'PC_PERF_PKR0_NUM_WAVES', 'PC_PERF_PKR0_PRIMS_PER_PROBE_EQ1', + 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT1', + 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT2', + 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT4', + 'PC_PERF_PKR0_PRIMS_PER_PROBE_GT8', + 'PC_PERF_PKR0_PRIMS_PER_WAVE_EQ1', + 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT1', + 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT2', + 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT4', + 'PC_PERF_PKR0_PRIMS_PER_WAVE_GT8', 'PC_PERF_PKR0_PRIMS_REUSE', + 'PC_PERF_PKR0_PROBES_PER_WAVE_EQ1', + 'PC_PERF_PKR0_PROBES_PER_WAVE_GT1', + 'PC_PERF_PKR0_PROBES_PER_WAVE_GT2', + 'PC_PERF_PKR0_PROBES_PER_WAVE_GT4', + 'PC_PERF_PKR0_PROBES_PER_WAVE_GT8', 'PC_PERF_PKR1_FPOSG_EQ1', + 'PC_PERF_PKR1_FPOSG_GT1', 'PC_PERF_PKR1_FPOSG_GT128', + 'PC_PERF_PKR1_FPOSG_GT16', 'PC_PERF_PKR1_FPOSG_GT64', + 'PC_PERF_PKR1_FPOSG_OUT_OF_WAVE', + 'PC_PERF_PKR1_GSDONE_WHILE_IDLE', 'PC_PERF_PKR1_NUM_PROBES', + 'PC_PERF_PKR1_NUM_WAVES', 'PC_PERF_PKR1_PRIMS_PER_PROBE_EQ1', + 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT1', + 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT2', + 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT4', + 'PC_PERF_PKR1_PRIMS_PER_PROBE_GT8', + 'PC_PERF_PKR1_PRIMS_PER_WAVE_EQ1', + 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT1', + 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT2', + 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT4', + 'PC_PERF_PKR1_PRIMS_PER_WAVE_GT8', 'PC_PERF_PKR1_PRIMS_REUSE', + 'PC_PERF_PKR1_PROBES_PER_WAVE_EQ1', + 'PC_PERF_PKR1_PROBES_PER_WAVE_GT1', + 'PC_PERF_PKR1_PROBES_PER_WAVE_GT2', + 'PC_PERF_PKR1_PROBES_PER_WAVE_GT4', + 'PC_PERF_PKR1_PROBES_PER_WAVE_GT8', 'PC_PERF_PKR2_FPOSG_EQ1', + 'PC_PERF_PKR2_FPOSG_GT1', 'PC_PERF_PKR2_FPOSG_GT128', + 'PC_PERF_PKR2_FPOSG_GT16', 'PC_PERF_PKR2_FPOSG_GT64', + 'PC_PERF_PKR2_FPOSG_OUT_OF_WAVE', + 'PC_PERF_PKR2_GSDONE_WHILE_IDLE', 'PC_PERF_PKR2_NUM_PROBES', + 'PC_PERF_PKR2_NUM_WAVES', 'PC_PERF_PKR2_PRIMS_PER_PROBE_EQ1', + 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT1', + 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT2', + 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT4', + 'PC_PERF_PKR2_PRIMS_PER_PROBE_GT8', + 'PC_PERF_PKR2_PRIMS_PER_WAVE_EQ1', + 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT1', + 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT2', + 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT4', + 'PC_PERF_PKR2_PRIMS_PER_WAVE_GT8', 'PC_PERF_PKR2_PRIMS_REUSE', + 'PC_PERF_PKR2_PROBES_PER_WAVE_EQ1', + 'PC_PERF_PKR2_PROBES_PER_WAVE_GT1', + 'PC_PERF_PKR2_PROBES_PER_WAVE_GT2', + 'PC_PERF_PKR2_PROBES_PER_WAVE_GT4', + 'PC_PERF_PKR2_PROBES_PER_WAVE_GT8', 'PC_PERF_PKR3_FPOSG_EQ1', + 'PC_PERF_PKR3_FPOSG_GT1', 'PC_PERF_PKR3_FPOSG_GT128', + 'PC_PERF_PKR3_FPOSG_GT16', 'PC_PERF_PKR3_FPOSG_GT64', + 'PC_PERF_PKR3_FPOSG_OUT_OF_WAVE', + 'PC_PERF_PKR3_GSDONE_WHILE_IDLE', 'PC_PERF_PKR3_NUM_PROBES', + 'PC_PERF_PKR3_NUM_WAVES', 'PC_PERF_PKR3_PRIMS_PER_PROBE_EQ1', + 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT1', + 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT2', + 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT4', + 'PC_PERF_PKR3_PRIMS_PER_PROBE_GT8', + 'PC_PERF_PKR3_PRIMS_PER_WAVE_EQ1', + 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT1', + 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT2', + 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT4', + 'PC_PERF_PKR3_PRIMS_PER_WAVE_GT8', 'PC_PERF_PKR3_PRIMS_REUSE', + 'PC_PERF_PKR3_PROBES_PER_WAVE_EQ1', + 'PC_PERF_PKR3_PROBES_PER_WAVE_GT1', + 'PC_PERF_PKR3_PROBES_PER_WAVE_GT2', + 'PC_PERF_PKR3_PROBES_PER_WAVE_GT4', + 'PC_PERF_PKR3_PROBES_PER_WAVE_GT8', 'PC_PERF_SC_FPOSG0', + 'PC_PERF_SC_FPOSG1', 'PC_PERF_SC_FPOSG2', 'PC_PERF_SC_FPOSG3', + 'PC_PERF_SC_FPOSG_WAIT0', 'PC_PERF_SC_FPOSG_WAIT1', + 'PC_PERF_SC_FPOSG_WAIT2', 'PC_PERF_SC_FPOSG_WAIT3', + 'PC_PERF_SC_MW_FREEZE', 'PC_PERF_SC_NUM_PROBES', + 'PC_PERF_SC_NUM_SPLIT_WAVES', 'PC_PERF_SC_NUM_WAVES', + 'PC_PERF_SC_PC_PTR_SEND0', 'PC_PERF_SC_PC_PTR_SEND1', + 'PC_PERF_SC_PC_PTR_SEND2', 'PC_PERF_SC_PC_PTR_SEND3', + 'PC_PERF_SC_PC_PTR_VALID0', 'PC_PERF_SC_PC_PTR_VALID1', + 'PC_PERF_SC_PC_PTR_VALID2', 'PC_PERF_SC_PC_PTR_VALID3', + 'PC_PERF_SC_PQ_FREEZE0', 'PC_PERF_SC_PQ_FREEZE1', + 'PC_PERF_SC_PQ_FREEZE2', 'PC_PERF_SC_PQ_FREEZE3', + 'PC_PERF_SC_WAIT_SYNC0', 'PC_PERF_SC_WAIT_SYNC1', + 'PC_PERF_SC_WAIT_SYNC2', 'PC_PERF_SC_WAIT_SYNC3', + 'PERFCOUNTER_ACTIVE', 'PERFCOUNTER_CNT0_STATE', + 'PERFCOUNTER_CNT0_STATE_FREEZE', 'PERFCOUNTER_CNT0_STATE_HW', + 'PERFCOUNTER_CNT0_STATE_RESET', 'PERFCOUNTER_CNT0_STATE_START', + 'PERFCOUNTER_CNT1_STATE', 'PERFCOUNTER_CNT1_STATE_FREEZE', + 'PERFCOUNTER_CNT1_STATE_HW', 'PERFCOUNTER_CNT1_STATE_RESET', + 'PERFCOUNTER_CNT1_STATE_START', 'PERFCOUNTER_CNT2_STATE', + 'PERFCOUNTER_CNT2_STATE_FREEZE', 'PERFCOUNTER_CNT2_STATE_HW', + 'PERFCOUNTER_CNT2_STATE_RESET', 'PERFCOUNTER_CNT2_STATE_START', + 'PERFCOUNTER_CNT3_STATE', 'PERFCOUNTER_CNT3_STATE_FREEZE', + 'PERFCOUNTER_CNT3_STATE_HW', 'PERFCOUNTER_CNT3_STATE_RESET', + 'PERFCOUNTER_CNT3_STATE_START', 'PERFCOUNTER_CNT4_STATE', + 'PERFCOUNTER_CNT4_STATE_FREEZE', 'PERFCOUNTER_CNT4_STATE_HW', + 'PERFCOUNTER_CNT4_STATE_RESET', 'PERFCOUNTER_CNT4_STATE_START', + 'PERFCOUNTER_CNT5_STATE', 'PERFCOUNTER_CNT5_STATE_FREEZE', + 'PERFCOUNTER_CNT5_STATE_HW', 'PERFCOUNTER_CNT5_STATE_RESET', + 'PERFCOUNTER_CNT5_STATE_START', 'PERFCOUNTER_CNT6_STATE', + 'PERFCOUNTER_CNT6_STATE_FREEZE', 'PERFCOUNTER_CNT6_STATE_HW', + 'PERFCOUNTER_CNT6_STATE_RESET', 'PERFCOUNTER_CNT6_STATE_START', + 'PERFCOUNTER_CNT7_STATE', 'PERFCOUNTER_CNT7_STATE_FREEZE', + 'PERFCOUNTER_CNT7_STATE_HW', 'PERFCOUNTER_CNT7_STATE_RESET', + 'PERFCOUNTER_CNT7_STATE_START', 'PERFCOUNTER_CNTL_SEL', + 'PERFCOUNTER_CNTL_SEL_0', 'PERFCOUNTER_CNTL_SEL_1', + 'PERFCOUNTER_CNTL_SEL_2', 'PERFCOUNTER_CNTL_SEL_3', + 'PERFCOUNTER_CNTL_SEL_4', 'PERFCOUNTER_CNTL_SEL_5', + 'PERFCOUNTER_CNTL_SEL_6', 'PERFCOUNTER_CNTL_SEL_7', + 'PERFCOUNTER_CNTOFF_START_DIS', + 'PERFCOUNTER_CNTOFF_START_DISABLE', + 'PERFCOUNTER_CNTOFF_START_ENABLE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', + 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', + 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', + 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', + 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', + 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', + 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_HW_STOP1_0', + 'PERFCOUNTER_HW_STOP1_1', 'PERFCOUNTER_HW_STOP1_SEL', + 'PERFCOUNTER_HW_STOP2_0', 'PERFCOUNTER_HW_STOP2_1', + 'PERFCOUNTER_HW_STOP2_SEL', 'PERFCOUNTER_INC_MODE', + 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', + 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', + 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', + 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', + 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', + 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', + 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', + 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', + 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', + 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', + 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', + 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', + 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', + 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', + 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', + 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', + 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', + 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', + 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', + 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', + 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', + 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', + 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', + 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', + 'PERFMON_COUNTER_MODE_ACCUM', + 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 'PERFMON_COUNTER_MODE_DIRTY', + 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', + 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', + 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', + 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', + 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', + 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', + 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', + 'PERFMON_STATE_START', 'PERF_CLIPSM_CULL_PRIMS_CNT', + 'PERF_CLPR_BACK_PRIM', 'PERF_CLPR_CLIP_PLANE_CNT_9_PLUS', + 'PERF_CLPR_INPUT_END_OF_PACKET', 'PERF_CLPR_INPUT_EVENT', + 'PERF_CLPR_INPUT_EXTENDED_EVENT', + 'PERF_CLPR_INPUT_FIRST_OF_SUBGROUP', 'PERF_CLPR_INPUT_NULL_PRIM', + 'PERF_CLPR_INPUT_PRIM', 'PERF_CLPR_INPUT_SEND', 'PERF_ENGG_BUSY', + 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', + 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', + 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', 'PERF_ENGG_CSB_GE_MEMORY_FULL', + 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', + 'PERF_ENGG_CSB_MACHINE_IS_STARVED', + 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', + 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', + 'PERF_ENGG_CSB_NULL_SUBGROUP', + 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', + 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', + 'PERF_ENGG_CSB_SPI_MEMORY_FULL', + 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', + 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', + 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', + 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', + 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', + 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', + 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', + 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', + 'PERF_ENGG_INDEX_REQ_STARVED', 'PERF_ENGG_INDEX_RET0_NEW_VERTS', + 'PERF_ENGG_INDEX_RET10_NEW_VERTS', + 'PERF_ENGG_INDEX_RET11_NEW_VERTS', + 'PERF_ENGG_INDEX_RET12_NEW_VERTS', + 'PERF_ENGG_INDEX_RET1_NEW_VERTS', + 'PERF_ENGG_INDEX_RET2_NEW_VERTS', + 'PERF_ENGG_INDEX_RET3_NEW_VERTS', + 'PERF_ENGG_INDEX_RET4_NEW_VERTS', + 'PERF_ENGG_INDEX_RET5_NEW_VERTS', + 'PERF_ENGG_INDEX_RET6_NEW_VERTS', + 'PERF_ENGG_INDEX_RET7_NEW_VERTS', + 'PERF_ENGG_INDEX_RET8_NEW_VERTS', + 'PERF_ENGG_INDEX_RET9_NEW_VERTS', + 'PERF_ENGG_INDEX_RET_0_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_RET_1_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_RET_2_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_RET_3_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', + 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', + 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', + 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', + 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', + 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', + 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', + 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', + 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', + 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', + 'PERF_ENGG_POS_REQ_STARVED', 'PERF_OUTPUT_PRIM_1_SC', + 'PERF_OUTPUT_PRIM_2_SC', 'PERF_OUTPUT_PRIM_3_SC', + 'PERF_OUTPUT_PRIM_4_SC', 'PERF_OUTPUT_PRIM_5_SC', + 'PERF_OUTPUT_PRIM_6_SC', 'PERF_PAPC_CCGSM_BUSY', + 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', + 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', + 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', + 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', + 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', + 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', + 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', + 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_PLUS', + 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_REC_BUSY', + 'PERF_PAPC_PASX_REC_IDLE', 'PERF_PAPC_PASX_REC_STALLED', + 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', + 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', + 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 'PERF_PAPC_PASX_VTX_NAN_DISCARD', 'PERF_PAPC_PA_REG_SCLK_VLD', + 'PERF_PAPC_SU_ALL_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_ALL_OUTPUT_PRIM', 'PERF_PAPC_SU_ALL_STALLED_SC', + 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', 'PERF_PAPC_SU_BUSY', + 'PERF_PAPC_SU_CULLED_PRIM', 'PERF_PAPC_SU_DYN_SCLK_VLD', + 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', 'PERF_PAPC_SU_IDLE', + 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', + 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', + 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', + 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE0_STALLED_SC', + 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE1_STALLED_SC', + 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE2_STALLED_SC', + 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE3_STALLED_SC', + 'PERF_PAPC_SU_SE4_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE4_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE4_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE4_STALLED_SC', + 'PERF_PAPC_SU_SE5_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE5_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE5_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE5_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', + 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 'PERF_PASX_CCDIST0_VECTOR', 'PERF_PASX_CCDIST1_VECTOR', + 'PERF_PASX_MISC_VECTOR', 'PERF_PASX_POS_VECTOR', + 'PERF_PASX_STEREO_POS_VECTOR', 'PERF_PA_BUSY', + 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', + 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', 'PERF_PA_VERTEX_FIFO_FULL', + 'PERF_PH_SEND_1_SC', 'PERF_PH_SEND_2_SC', 'PERF_PH_SEND_3_SC', + 'PERF_PH_SEND_4_SC', 'PERF_PH_SEND_5_SC', 'PERF_PH_SEND_6_SC', + 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SMALL_PRIM_CULL_PRIM_1X1', 'PERF_SMALL_PRIM_CULL_PRIM_1X2', + 'PERF_SMALL_PRIM_CULL_PRIM_1X3', 'PERF_SMALL_PRIM_CULL_PRIM_1XN', + 'PERF_SMALL_PRIM_CULL_PRIM_2X1', 'PERF_SMALL_PRIM_CULL_PRIM_2X2', + 'PERF_SMALL_PRIM_CULL_PRIM_2X3', 'PERF_SMALL_PRIM_CULL_PRIM_2XN', + 'PERF_SMALL_PRIM_CULL_PRIM_3X1', 'PERF_SMALL_PRIM_CULL_PRIM_3X2', + 'PERF_SMALL_PRIM_CULL_PRIM_NX1', 'PERF_SMALL_PRIM_CULL_PRIM_NX2', + 'PERF_SU_INPUT_SEND', 'PERF_SU_OUTPUT_SEND', + 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', 'PERSISTENT_SPACE_END', + 'PERSISTENT_SPACE_START', 'PFVF_SQDEC_BEGIN', 'PFVF_SQDEC_END', + 'PHYSYMCLK_FORCE_EN', 'PHYSYMCLK_FORCE_EN_DISABLE', + 'PHYSYMCLK_FORCE_EN_ENABLE', 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', + 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', 'PHYSYMCLK_FORCE_SRC_SEL', + 'PHYSYMCLK_FORCE_SRC_SYMCLK', 'PHY_MUX_ENABLE_ENUM', + 'PHY_MUX_ENABLE_ENUM_DISABLED', 'PHY_MUX_ENABLE_ENUM_ENABLED', + 'PH_PERFCNT_SEL', 'PH_PERF_SC0_FIFO_STATUS_0', + 'PH_PERF_SC0_FIFO_STATUS_1', 'PH_PERF_SC0_FIFO_STATUS_2', + 'PH_PERF_SC0_FIFO_STATUS_3', 'PH_PERF_SC1_FIFO_STATUS_0', + 'PH_PERF_SC1_FIFO_STATUS_1', 'PH_PERF_SC1_FIFO_STATUS_2', + 'PH_PERF_SC1_FIFO_STATUS_3', 'PH_PERF_SC2_FIFO_STATUS_0', + 'PH_PERF_SC2_FIFO_STATUS_1', 'PH_PERF_SC2_FIFO_STATUS_2', + 'PH_PERF_SC2_FIFO_STATUS_3', 'PH_PERF_SC3_FIFO_STATUS_0', + 'PH_PERF_SC3_FIFO_STATUS_1', 'PH_PERF_SC3_FIFO_STATUS_2', + 'PH_PERF_SC3_FIFO_STATUS_3', 'PH_PERF_SC4_FIFO_STATUS_0', + 'PH_PERF_SC4_FIFO_STATUS_1', 'PH_PERF_SC4_FIFO_STATUS_2', + 'PH_PERF_SC4_FIFO_STATUS_3', 'PH_PERF_SC5_FIFO_STATUS_0', + 'PH_PERF_SC5_FIFO_STATUS_1', 'PH_PERF_SC5_FIFO_STATUS_2', + 'PH_PERF_SC5_FIFO_STATUS_3', 'PH_PERF_SC6_FIFO_STATUS_0', + 'PH_PERF_SC6_FIFO_STATUS_1', 'PH_PERF_SC6_FIFO_STATUS_2', + 'PH_PERF_SC6_FIFO_STATUS_3', 'PH_PERF_SC7_FIFO_STATUS_0', + 'PH_PERF_SC7_FIFO_STATUS_1', 'PH_PERF_SC7_FIFO_STATUS_2', + 'PH_PERF_SC7_FIFO_STATUS_3', + 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC0_ARB_BUSY', + 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA0_EOPG_WE', + 'PH_PERF_SEL_SC0_PA0_EOP_WE', 'PH_PERF_SEL_SC0_PA0_EVENT_WE', + 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', + 'PH_PERF_SEL_SC0_PA0_FPOP_WE', 'PH_PERF_SEL_SC0_PA0_FPOV_WE', + 'PH_PERF_SEL_SC0_PA0_NULL_WE', + 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA1_EOPG_WE', + 'PH_PERF_SEL_SC0_PA1_EOP_WE', 'PH_PERF_SEL_SC0_PA1_EVENT_WE', + 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', + 'PH_PERF_SEL_SC0_PA1_FPOP_WE', 'PH_PERF_SEL_SC0_PA1_FPOV_WE', + 'PH_PERF_SEL_SC0_PA1_NULL_WE', + 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA2_EOPG_WE', + 'PH_PERF_SEL_SC0_PA2_EOP_WE', 'PH_PERF_SEL_SC0_PA2_EVENT_WE', + 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', + 'PH_PERF_SEL_SC0_PA2_FPOP_WE', 'PH_PERF_SEL_SC0_PA2_FPOV_WE', + 'PH_PERF_SEL_SC0_PA2_NULL_WE', + 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA3_EOPG_WE', + 'PH_PERF_SEL_SC0_PA3_EOP_WE', 'PH_PERF_SEL_SC0_PA3_EVENT_WE', + 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', + 'PH_PERF_SEL_SC0_PA3_FPOP_WE', 'PH_PERF_SEL_SC0_PA3_FPOV_WE', + 'PH_PERF_SEL_SC0_PA3_NULL_WE', + 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA4_EOPG_WE', + 'PH_PERF_SEL_SC0_PA4_EOP_WE', 'PH_PERF_SEL_SC0_PA4_EVENT_WE', + 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', + 'PH_PERF_SEL_SC0_PA4_FPOP_WE', 'PH_PERF_SEL_SC0_PA4_FPOV_WE', + 'PH_PERF_SEL_SC0_PA4_NULL_WE', + 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA5_EOPG_WE', + 'PH_PERF_SEL_SC0_PA5_EOP_WE', 'PH_PERF_SEL_SC0_PA5_EVENT_WE', + 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', + 'PH_PERF_SEL_SC0_PA5_FPOP_WE', 'PH_PERF_SEL_SC0_PA5_FPOV_WE', + 'PH_PERF_SEL_SC0_PA5_NULL_WE', + 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA6_EOPG_WE', + 'PH_PERF_SEL_SC0_PA6_EOP_WE', 'PH_PERF_SEL_SC0_PA6_EVENT_WE', + 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', + 'PH_PERF_SEL_SC0_PA6_FPOP_WE', 'PH_PERF_SEL_SC0_PA6_FPOV_WE', + 'PH_PERF_SEL_SC0_PA6_NULL_WE', + 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC0_PA7_EOPG_WE', + 'PH_PERF_SEL_SC0_PA7_EOP_WE', 'PH_PERF_SEL_SC0_PA7_EVENT_WE', + 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', + 'PH_PERF_SEL_SC0_PA7_FPOP_WE', 'PH_PERF_SEL_SC0_PA7_FPOV_WE', + 'PH_PERF_SEL_SC0_PA7_NULL_WE', + 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC0_SEND', 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC1_ARB_BUSY', + 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA0_EOPG_WE', + 'PH_PERF_SEL_SC1_PA0_EOP_WE', 'PH_PERF_SEL_SC1_PA0_EVENT_WE', + 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', + 'PH_PERF_SEL_SC1_PA0_FPOP_WE', 'PH_PERF_SEL_SC1_PA0_FPOV_WE', + 'PH_PERF_SEL_SC1_PA0_NULL_WE', + 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA1_EOPG_WE', + 'PH_PERF_SEL_SC1_PA1_EOP_WE', 'PH_PERF_SEL_SC1_PA1_EVENT_WE', + 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', + 'PH_PERF_SEL_SC1_PA1_FPOP_WE', 'PH_PERF_SEL_SC1_PA1_FPOV_WE', + 'PH_PERF_SEL_SC1_PA1_NULL_WE', + 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA2_EOPG_WE', + 'PH_PERF_SEL_SC1_PA2_EOP_WE', 'PH_PERF_SEL_SC1_PA2_EVENT_WE', + 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', + 'PH_PERF_SEL_SC1_PA2_FPOP_WE', 'PH_PERF_SEL_SC1_PA2_FPOV_WE', + 'PH_PERF_SEL_SC1_PA2_NULL_WE', + 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA3_EOPG_WE', + 'PH_PERF_SEL_SC1_PA3_EOP_WE', 'PH_PERF_SEL_SC1_PA3_EVENT_WE', + 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', + 'PH_PERF_SEL_SC1_PA3_FPOP_WE', 'PH_PERF_SEL_SC1_PA3_FPOV_WE', + 'PH_PERF_SEL_SC1_PA3_NULL_WE', + 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA4_EOPG_WE', + 'PH_PERF_SEL_SC1_PA4_EOP_WE', 'PH_PERF_SEL_SC1_PA4_EVENT_WE', + 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', + 'PH_PERF_SEL_SC1_PA4_FPOP_WE', 'PH_PERF_SEL_SC1_PA4_FPOV_WE', + 'PH_PERF_SEL_SC1_PA4_NULL_WE', + 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA5_EOPG_WE', + 'PH_PERF_SEL_SC1_PA5_EOP_WE', 'PH_PERF_SEL_SC1_PA5_EVENT_WE', + 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', + 'PH_PERF_SEL_SC1_PA5_FPOP_WE', 'PH_PERF_SEL_SC1_PA5_FPOV_WE', + 'PH_PERF_SEL_SC1_PA5_NULL_WE', + 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA6_EOPG_WE', + 'PH_PERF_SEL_SC1_PA6_EOP_WE', 'PH_PERF_SEL_SC1_PA6_EVENT_WE', + 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', + 'PH_PERF_SEL_SC1_PA6_FPOP_WE', 'PH_PERF_SEL_SC1_PA6_FPOV_WE', + 'PH_PERF_SEL_SC1_PA6_NULL_WE', + 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC1_PA7_EOPG_WE', + 'PH_PERF_SEL_SC1_PA7_EOP_WE', 'PH_PERF_SEL_SC1_PA7_EVENT_WE', + 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', + 'PH_PERF_SEL_SC1_PA7_FPOP_WE', 'PH_PERF_SEL_SC1_PA7_FPOV_WE', + 'PH_PERF_SEL_SC1_PA7_NULL_WE', + 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC1_SEND', 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC2_ARB_BUSY', + 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA0_EOPG_WE', + 'PH_PERF_SEL_SC2_PA0_EOP_WE', 'PH_PERF_SEL_SC2_PA0_EVENT_WE', + 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', + 'PH_PERF_SEL_SC2_PA0_FPOP_WE', 'PH_PERF_SEL_SC2_PA0_FPOV_WE', + 'PH_PERF_SEL_SC2_PA0_NULL_WE', + 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA1_EOPG_WE', + 'PH_PERF_SEL_SC2_PA1_EOP_WE', 'PH_PERF_SEL_SC2_PA1_EVENT_WE', + 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', + 'PH_PERF_SEL_SC2_PA1_FPOP_WE', 'PH_PERF_SEL_SC2_PA1_FPOV_WE', + 'PH_PERF_SEL_SC2_PA1_NULL_WE', + 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA2_EOPG_WE', + 'PH_PERF_SEL_SC2_PA2_EOP_WE', 'PH_PERF_SEL_SC2_PA2_EVENT_WE', + 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', + 'PH_PERF_SEL_SC2_PA2_FPOP_WE', 'PH_PERF_SEL_SC2_PA2_FPOV_WE', + 'PH_PERF_SEL_SC2_PA2_NULL_WE', + 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA3_EOPG_WE', + 'PH_PERF_SEL_SC2_PA3_EOP_WE', 'PH_PERF_SEL_SC2_PA3_EVENT_WE', + 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', + 'PH_PERF_SEL_SC2_PA3_FPOP_WE', 'PH_PERF_SEL_SC2_PA3_FPOV_WE', + 'PH_PERF_SEL_SC2_PA3_NULL_WE', + 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA4_EOPG_WE', + 'PH_PERF_SEL_SC2_PA4_EOP_WE', 'PH_PERF_SEL_SC2_PA4_EVENT_WE', + 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', + 'PH_PERF_SEL_SC2_PA4_FPOP_WE', 'PH_PERF_SEL_SC2_PA4_FPOV_WE', + 'PH_PERF_SEL_SC2_PA4_NULL_WE', + 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA5_EOPG_WE', + 'PH_PERF_SEL_SC2_PA5_EOP_WE', 'PH_PERF_SEL_SC2_PA5_EVENT_WE', + 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', + 'PH_PERF_SEL_SC2_PA5_FPOP_WE', 'PH_PERF_SEL_SC2_PA5_FPOV_WE', + 'PH_PERF_SEL_SC2_PA5_NULL_WE', + 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA6_EOPG_WE', + 'PH_PERF_SEL_SC2_PA6_EOP_WE', 'PH_PERF_SEL_SC2_PA6_EVENT_WE', + 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', + 'PH_PERF_SEL_SC2_PA6_FPOP_WE', 'PH_PERF_SEL_SC2_PA6_FPOV_WE', + 'PH_PERF_SEL_SC2_PA6_NULL_WE', + 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC2_PA7_EOPG_WE', + 'PH_PERF_SEL_SC2_PA7_EOP_WE', 'PH_PERF_SEL_SC2_PA7_EVENT_WE', + 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', + 'PH_PERF_SEL_SC2_PA7_FPOP_WE', 'PH_PERF_SEL_SC2_PA7_FPOV_WE', + 'PH_PERF_SEL_SC2_PA7_NULL_WE', + 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC2_SEND', 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC3_ARB_BUSY', + 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA0_EOPG_WE', + 'PH_PERF_SEL_SC3_PA0_EOP_WE', 'PH_PERF_SEL_SC3_PA0_EVENT_WE', + 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', + 'PH_PERF_SEL_SC3_PA0_FPOP_WE', 'PH_PERF_SEL_SC3_PA0_FPOV_WE', + 'PH_PERF_SEL_SC3_PA0_NULL_WE', + 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA1_EOPG_WE', + 'PH_PERF_SEL_SC3_PA1_EOP_WE', 'PH_PERF_SEL_SC3_PA1_EVENT_WE', + 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', + 'PH_PERF_SEL_SC3_PA1_FPOP_WE', 'PH_PERF_SEL_SC3_PA1_FPOV_WE', + 'PH_PERF_SEL_SC3_PA1_NULL_WE', + 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA2_EOPG_WE', + 'PH_PERF_SEL_SC3_PA2_EOP_WE', 'PH_PERF_SEL_SC3_PA2_EVENT_WE', + 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', + 'PH_PERF_SEL_SC3_PA2_FPOP_WE', 'PH_PERF_SEL_SC3_PA2_FPOV_WE', + 'PH_PERF_SEL_SC3_PA2_NULL_WE', + 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA3_EOPG_WE', + 'PH_PERF_SEL_SC3_PA3_EOP_WE', 'PH_PERF_SEL_SC3_PA3_EVENT_WE', + 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', + 'PH_PERF_SEL_SC3_PA3_FPOP_WE', 'PH_PERF_SEL_SC3_PA3_FPOV_WE', + 'PH_PERF_SEL_SC3_PA3_NULL_WE', + 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA4_EOPG_WE', + 'PH_PERF_SEL_SC3_PA4_EOP_WE', 'PH_PERF_SEL_SC3_PA4_EVENT_WE', + 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', + 'PH_PERF_SEL_SC3_PA4_FPOP_WE', 'PH_PERF_SEL_SC3_PA4_FPOV_WE', + 'PH_PERF_SEL_SC3_PA4_NULL_WE', + 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA5_EOPG_WE', + 'PH_PERF_SEL_SC3_PA5_EOP_WE', 'PH_PERF_SEL_SC3_PA5_EVENT_WE', + 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', + 'PH_PERF_SEL_SC3_PA5_FPOP_WE', 'PH_PERF_SEL_SC3_PA5_FPOV_WE', + 'PH_PERF_SEL_SC3_PA5_NULL_WE', + 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA6_EOPG_WE', + 'PH_PERF_SEL_SC3_PA6_EOP_WE', 'PH_PERF_SEL_SC3_PA6_EVENT_WE', + 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', + 'PH_PERF_SEL_SC3_PA6_FPOP_WE', 'PH_PERF_SEL_SC3_PA6_FPOV_WE', + 'PH_PERF_SEL_SC3_PA6_NULL_WE', + 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC3_PA7_EOPG_WE', + 'PH_PERF_SEL_SC3_PA7_EOP_WE', 'PH_PERF_SEL_SC3_PA7_EVENT_WE', + 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', + 'PH_PERF_SEL_SC3_PA7_FPOP_WE', 'PH_PERF_SEL_SC3_PA7_FPOV_WE', + 'PH_PERF_SEL_SC3_PA7_NULL_WE', + 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC3_SEND', 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC4_ARB_BUSY', + 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA0_EOPG_WE', + 'PH_PERF_SEL_SC4_PA0_EOP_WE', 'PH_PERF_SEL_SC4_PA0_EVENT_WE', + 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', + 'PH_PERF_SEL_SC4_PA0_FPOP_WE', 'PH_PERF_SEL_SC4_PA0_FPOV_WE', + 'PH_PERF_SEL_SC4_PA0_NULL_WE', + 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA1_EOPG_WE', + 'PH_PERF_SEL_SC4_PA1_EOP_WE', 'PH_PERF_SEL_SC4_PA1_EVENT_WE', + 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', + 'PH_PERF_SEL_SC4_PA1_FPOP_WE', 'PH_PERF_SEL_SC4_PA1_FPOV_WE', + 'PH_PERF_SEL_SC4_PA1_NULL_WE', + 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA2_EOPG_WE', + 'PH_PERF_SEL_SC4_PA2_EOP_WE', 'PH_PERF_SEL_SC4_PA2_EVENT_WE', + 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', + 'PH_PERF_SEL_SC4_PA2_FPOP_WE', 'PH_PERF_SEL_SC4_PA2_FPOV_WE', + 'PH_PERF_SEL_SC4_PA2_NULL_WE', + 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA3_EOPG_WE', + 'PH_PERF_SEL_SC4_PA3_EOP_WE', 'PH_PERF_SEL_SC4_PA3_EVENT_WE', + 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', + 'PH_PERF_SEL_SC4_PA3_FPOP_WE', 'PH_PERF_SEL_SC4_PA3_FPOV_WE', + 'PH_PERF_SEL_SC4_PA3_NULL_WE', + 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA4_EOPG_WE', + 'PH_PERF_SEL_SC4_PA4_EOP_WE', 'PH_PERF_SEL_SC4_PA4_EVENT_WE', + 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', + 'PH_PERF_SEL_SC4_PA4_FPOP_WE', 'PH_PERF_SEL_SC4_PA4_FPOV_WE', + 'PH_PERF_SEL_SC4_PA4_NULL_WE', + 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA5_EOPG_WE', + 'PH_PERF_SEL_SC4_PA5_EOP_WE', 'PH_PERF_SEL_SC4_PA5_EVENT_WE', + 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', + 'PH_PERF_SEL_SC4_PA5_FPOP_WE', 'PH_PERF_SEL_SC4_PA5_FPOV_WE', + 'PH_PERF_SEL_SC4_PA5_NULL_WE', + 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA6_EOPG_WE', + 'PH_PERF_SEL_SC4_PA6_EOP_WE', 'PH_PERF_SEL_SC4_PA6_EVENT_WE', + 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', + 'PH_PERF_SEL_SC4_PA6_FPOP_WE', 'PH_PERF_SEL_SC4_PA6_FPOV_WE', + 'PH_PERF_SEL_SC4_PA6_NULL_WE', + 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC4_PA7_EOPG_WE', + 'PH_PERF_SEL_SC4_PA7_EOP_WE', 'PH_PERF_SEL_SC4_PA7_EVENT_WE', + 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', + 'PH_PERF_SEL_SC4_PA7_FPOP_WE', 'PH_PERF_SEL_SC4_PA7_FPOV_WE', + 'PH_PERF_SEL_SC4_PA7_NULL_WE', + 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC4_SEND', 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC5_ARB_BUSY', + 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA0_EOPG_WE', + 'PH_PERF_SEL_SC5_PA0_EOP_WE', 'PH_PERF_SEL_SC5_PA0_EVENT_WE', + 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', + 'PH_PERF_SEL_SC5_PA0_FPOP_WE', 'PH_PERF_SEL_SC5_PA0_FPOV_WE', + 'PH_PERF_SEL_SC5_PA0_NULL_WE', + 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA1_EOPG_WE', + 'PH_PERF_SEL_SC5_PA1_EOP_WE', 'PH_PERF_SEL_SC5_PA1_EVENT_WE', + 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', + 'PH_PERF_SEL_SC5_PA1_FPOP_WE', 'PH_PERF_SEL_SC5_PA1_FPOV_WE', + 'PH_PERF_SEL_SC5_PA1_NULL_WE', + 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA2_EOPG_WE', + 'PH_PERF_SEL_SC5_PA2_EOP_WE', 'PH_PERF_SEL_SC5_PA2_EVENT_WE', + 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', + 'PH_PERF_SEL_SC5_PA2_FPOP_WE', 'PH_PERF_SEL_SC5_PA2_FPOV_WE', + 'PH_PERF_SEL_SC5_PA2_NULL_WE', + 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA3_EOPG_WE', + 'PH_PERF_SEL_SC5_PA3_EOP_WE', 'PH_PERF_SEL_SC5_PA3_EVENT_WE', + 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', + 'PH_PERF_SEL_SC5_PA3_FPOP_WE', 'PH_PERF_SEL_SC5_PA3_FPOV_WE', + 'PH_PERF_SEL_SC5_PA3_NULL_WE', + 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA4_EOPG_WE', + 'PH_PERF_SEL_SC5_PA4_EOP_WE', 'PH_PERF_SEL_SC5_PA4_EVENT_WE', + 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', + 'PH_PERF_SEL_SC5_PA4_FPOP_WE', 'PH_PERF_SEL_SC5_PA4_FPOV_WE', + 'PH_PERF_SEL_SC5_PA4_NULL_WE', + 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA5_EOPG_WE', + 'PH_PERF_SEL_SC5_PA5_EOP_WE', 'PH_PERF_SEL_SC5_PA5_EVENT_WE', + 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', + 'PH_PERF_SEL_SC5_PA5_FPOP_WE', 'PH_PERF_SEL_SC5_PA5_FPOV_WE', + 'PH_PERF_SEL_SC5_PA5_NULL_WE', + 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA6_EOPG_WE', + 'PH_PERF_SEL_SC5_PA6_EOP_WE', 'PH_PERF_SEL_SC5_PA6_EVENT_WE', + 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', + 'PH_PERF_SEL_SC5_PA6_FPOP_WE', 'PH_PERF_SEL_SC5_PA6_FPOV_WE', + 'PH_PERF_SEL_SC5_PA6_NULL_WE', + 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC5_PA7_EOPG_WE', + 'PH_PERF_SEL_SC5_PA7_EOP_WE', 'PH_PERF_SEL_SC5_PA7_EVENT_WE', + 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', + 'PH_PERF_SEL_SC5_PA7_FPOP_WE', 'PH_PERF_SEL_SC5_PA7_FPOV_WE', + 'PH_PERF_SEL_SC5_PA7_NULL_WE', + 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC5_SEND', 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC6_ARB_BUSY', + 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA0_EOPG_WE', + 'PH_PERF_SEL_SC6_PA0_EOP_WE', 'PH_PERF_SEL_SC6_PA0_EVENT_WE', + 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', + 'PH_PERF_SEL_SC6_PA0_FPOP_WE', 'PH_PERF_SEL_SC6_PA0_FPOV_WE', + 'PH_PERF_SEL_SC6_PA0_NULL_WE', + 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA1_EOPG_WE', + 'PH_PERF_SEL_SC6_PA1_EOP_WE', 'PH_PERF_SEL_SC6_PA1_EVENT_WE', + 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', + 'PH_PERF_SEL_SC6_PA1_FPOP_WE', 'PH_PERF_SEL_SC6_PA1_FPOV_WE', + 'PH_PERF_SEL_SC6_PA1_NULL_WE', + 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA2_EOPG_WE', + 'PH_PERF_SEL_SC6_PA2_EOP_WE', 'PH_PERF_SEL_SC6_PA2_EVENT_WE', + 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', + 'PH_PERF_SEL_SC6_PA2_FPOP_WE', 'PH_PERF_SEL_SC6_PA2_FPOV_WE', + 'PH_PERF_SEL_SC6_PA2_NULL_WE', + 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA3_EOPG_WE', + 'PH_PERF_SEL_SC6_PA3_EOP_WE', 'PH_PERF_SEL_SC6_PA3_EVENT_WE', + 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', + 'PH_PERF_SEL_SC6_PA3_FPOP_WE', 'PH_PERF_SEL_SC6_PA3_FPOV_WE', + 'PH_PERF_SEL_SC6_PA3_NULL_WE', + 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA4_EOPG_WE', + 'PH_PERF_SEL_SC6_PA4_EOP_WE', 'PH_PERF_SEL_SC6_PA4_EVENT_WE', + 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', + 'PH_PERF_SEL_SC6_PA4_FPOP_WE', 'PH_PERF_SEL_SC6_PA4_FPOV_WE', + 'PH_PERF_SEL_SC6_PA4_NULL_WE', + 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA5_EOPG_WE', + 'PH_PERF_SEL_SC6_PA5_EOP_WE', 'PH_PERF_SEL_SC6_PA5_EVENT_WE', + 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', + 'PH_PERF_SEL_SC6_PA5_FPOP_WE', 'PH_PERF_SEL_SC6_PA5_FPOV_WE', + 'PH_PERF_SEL_SC6_PA5_NULL_WE', + 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA6_EOPG_WE', + 'PH_PERF_SEL_SC6_PA6_EOP_WE', 'PH_PERF_SEL_SC6_PA6_EVENT_WE', + 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', + 'PH_PERF_SEL_SC6_PA6_FPOP_WE', 'PH_PERF_SEL_SC6_PA6_FPOV_WE', + 'PH_PERF_SEL_SC6_PA6_NULL_WE', + 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC6_PA7_EOPG_WE', + 'PH_PERF_SEL_SC6_PA7_EOP_WE', 'PH_PERF_SEL_SC6_PA7_EVENT_WE', + 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', + 'PH_PERF_SEL_SC6_PA7_FPOP_WE', 'PH_PERF_SEL_SC6_PA7_FPOV_WE', + 'PH_PERF_SEL_SC6_PA7_NULL_WE', + 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC6_SEND', 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC7_ARB_BUSY', + 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA0_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA0_EOPG_WE', + 'PH_PERF_SEL_SC7_PA0_EOP_WE', 'PH_PERF_SEL_SC7_PA0_EVENT_WE', + 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', + 'PH_PERF_SEL_SC7_PA0_FPOP_WE', 'PH_PERF_SEL_SC7_PA0_FPOV_WE', + 'PH_PERF_SEL_SC7_PA0_NULL_WE', + 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA1_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA1_EOPG_WE', + 'PH_PERF_SEL_SC7_PA1_EOP_WE', 'PH_PERF_SEL_SC7_PA1_EVENT_WE', + 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', + 'PH_PERF_SEL_SC7_PA1_FPOP_WE', 'PH_PERF_SEL_SC7_PA1_FPOV_WE', + 'PH_PERF_SEL_SC7_PA1_NULL_WE', + 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA2_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA2_EOPG_WE', + 'PH_PERF_SEL_SC7_PA2_EOP_WE', 'PH_PERF_SEL_SC7_PA2_EVENT_WE', + 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', + 'PH_PERF_SEL_SC7_PA2_FPOP_WE', 'PH_PERF_SEL_SC7_PA2_FPOV_WE', + 'PH_PERF_SEL_SC7_PA2_NULL_WE', + 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA3_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA3_EOPG_WE', + 'PH_PERF_SEL_SC7_PA3_EOP_WE', 'PH_PERF_SEL_SC7_PA3_EVENT_WE', + 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', + 'PH_PERF_SEL_SC7_PA3_FPOP_WE', 'PH_PERF_SEL_SC7_PA3_FPOV_WE', + 'PH_PERF_SEL_SC7_PA3_NULL_WE', + 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA4_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA4_EOPG_WE', + 'PH_PERF_SEL_SC7_PA4_EOP_WE', 'PH_PERF_SEL_SC7_PA4_EVENT_WE', + 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', + 'PH_PERF_SEL_SC7_PA4_FPOP_WE', 'PH_PERF_SEL_SC7_PA4_FPOV_WE', + 'PH_PERF_SEL_SC7_PA4_NULL_WE', + 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA5_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA5_EOPG_WE', + 'PH_PERF_SEL_SC7_PA5_EOP_WE', 'PH_PERF_SEL_SC7_PA5_EVENT_WE', + 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', + 'PH_PERF_SEL_SC7_PA5_FPOP_WE', 'PH_PERF_SEL_SC7_PA5_FPOV_WE', + 'PH_PERF_SEL_SC7_PA5_NULL_WE', + 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA6_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA6_EOPG_WE', + 'PH_PERF_SEL_SC7_PA6_EOP_WE', 'PH_PERF_SEL_SC7_PA6_EVENT_WE', + 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', + 'PH_PERF_SEL_SC7_PA6_FPOP_WE', 'PH_PERF_SEL_SC7_PA6_FPOV_WE', + 'PH_PERF_SEL_SC7_PA6_NULL_WE', + 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA7_DEALLOC_WE', 'PH_PERF_SEL_SC7_PA7_EOPG_WE', + 'PH_PERF_SEL_SC7_PA7_EOP_WE', 'PH_PERF_SEL_SC7_PA7_EVENT_WE', + 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', + 'PH_PERF_SEL_SC7_PA7_FPOP_WE', 'PH_PERF_SEL_SC7_PA7_FPOV_WE', + 'PH_PERF_SEL_SC7_PA7_NULL_WE', + 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC7_SEND', 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', + 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', + 'PH_SPI_MODE_DISABLED', 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', + 'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ALIGNED', + 'PIPE_ALIGNED_SURF', 'PIPE_ID0', 'PIPE_ID1', 'PIPE_ID2', + 'PIPE_ID3', 'PIPE_INT_MASK_MODE', 'PIPE_INT_MASK_MODE_DISABLE', + 'PIPE_INT_MASK_MODE_ENABLE', 'PIPE_INT_TYPE_MODE', + 'PIPE_INT_TYPE_MODE_DISABLE', 'PIPE_INT_TYPE_MODE_ENABLE', + 'PIPE_IN_FLUSH_URGENT', 'PIPE_IN_FLUSH_URGENT_DISABLE', + 'PIPE_IN_FLUSH_URGENT_ENABLE', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 'PIPE_PIXEL_RATE_PLL_SOURCE', + 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', + 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', + 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIPE_UNALIGNED_SURF', + 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE', 'PIXEL_PIPE_OCCLUSION_COUNT_0', + 'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2', + 'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', + 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', + 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', + 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', + 'PIX_DYNAMIC_EXPANSION', 'PIX_EXPAND_MODE', 'PIX_ZERO_EXPANSION', + 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', + 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET', + 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST', + 'POWER_STATE_ENUM', 'POWER_STATE_ENUM_DS', 'POWER_STATE_ENUM_LS', + 'POWER_STATE_ENUM_ON', 'POWER_STATE_ENUM_SD', 'PRE_CSC_BYPASS', + 'PRE_CSC_MODE_ENUM', 'PRE_CSC_SET_A', 'PRE_CSC_SET_B', + 'PRE_DEGAM_BT2020', 'PRE_DEGAM_BT2100HLG', 'PRE_DEGAM_BT2100PQ', + 'PRE_DEGAM_BYPASS', 'PRE_DEGAM_ENABLE', 'PRE_DEGAM_GAMMA_22', + 'PRE_DEGAM_GAMMA_24', 'PRE_DEGAM_GAMMA_26', 'PRE_DEGAM_MODE', + 'PRE_DEGAM_SELECT', 'PRE_DEGAM_SRGB', 'PROG_SEQ', 'PROTVIOL', + 'PRQ_MRQ_FLUSH_URGENT', 'PRQ_MRQ_FLUSH_URGENT_DISABLE', + 'PRQ_MRQ_FLUSH_URGENT_ENABLE', 'PS', 'PSLC_ASAP', 'PSLC_AUTO', + 'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PS_DONE', + 'PS_PARTIAL_FLUSH', 'PTE_BUFFER_MODE', 'PTE_BUFFER_MODE_0', + 'PTE_BUFFER_MODE_1', 'PTE_ROW_HEIGHT_LINEAR', + 'PTE_ROW_HEIGHT_LINEAR_1024L', 'PTE_ROW_HEIGHT_LINEAR_128L', + 'PTE_ROW_HEIGHT_LINEAR_16L', 'PTE_ROW_HEIGHT_LINEAR_256L', + 'PTE_ROW_HEIGHT_LINEAR_32L', 'PTE_ROW_HEIGHT_LINEAR_512L', + 'PTE_ROW_HEIGHT_LINEAR_64L', 'PTE_ROW_HEIGHT_LINEAR_8L', + 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN', + 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT', + 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN', + 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', + 'PWRSEQ_BL_PWM_DISABLE', 'PWRSEQ_BL_PWM_ENABLE', + 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', + 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', + 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', + 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', + 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', + 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', + 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 'PWRSEQ_BL_PWM_GRP1_REG_LOCK', + 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', + 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', + 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START', + 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', + 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', + 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', + 'PWRSEQ_GPIO_MASK_EN', 'PWRSEQ_GPIO_MASK_EN_HARDWARE', + 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', 'PWRSEQ_PANEL_BLON_OFF', + 'PWRSEQ_PANEL_BLON_ON', 'PWRSEQ_PANEL_BLON_POL_INVERT', + 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', 'PWRSEQ_PANEL_DIGON_OFF', + 'PWRSEQ_PANEL_DIGON_ON', 'PWRSEQ_PANEL_DIGON_POL_INVERT', + 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE', + 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN', + 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', + 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', + 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', + 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', + 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', + 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', 'PerfCounter_Vals', + 'PhSPIstatusMode', 'PixelPipeCounterId', 'PixelPipeStride', + 'PkrMap', 'PkrXsel', 'PkrXsel2', 'PkrYsel', 'RAMA', 'RAMA_ACCESS', + 'RAMB', 'RAMB_ACCESS', 'RAM_LUT', 'RANGE_00', 'RANGE_FF', + 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', + 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', + 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', + 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', + 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', + 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', + 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', + 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', + 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', + 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', + 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', + 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', + 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', + 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', + 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', + 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', + 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', + 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', + 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', + 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', + 'RASTER_CONFIG_SE_PAIR_MAP_3', + 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', + 'RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN', + 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON', + 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN', + 'RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS', + 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON', + 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN', + 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS', + 'RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS', + 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON', + 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN', + 'RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS', + 'RDPCSTX_CLOCK_CNTL_TX_CLK_EN', + 'RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET', + 'RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET', + 'RDPCSTX_CNTL_RDPCS_TX_FIFO_EN', + 'RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN', + 'RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET', 'RDPCSTX_FIFO_EMPTY', + 'RDPCSTX_FIFO_FULL', 'RDPCSTX_FIFO_IS_EMPTY', + 'RDPCSTX_FIFO_IS_FULL', 'RDPCSTX_FIFO_NOT_EMPTY', + 'RDPCSTX_FIFO_NOT_FULL', + 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE', + 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK', + 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE', + 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK', + 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK', + 'RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK', + 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL', + 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL', + 'RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE', + 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE', + 'RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE', + 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV', + 'RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV', + 'RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', + 'RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL', + 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT', + 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE', + 'RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH', + 'RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE', + 'RDPCSTX_PHY_REF_ALT_CLK_EN', 'RDPCSTX_TX_FIFO_DISABLED_MASK', + 'RDPCSTX_TX_FIFO_DISABLED_MASK_DISABLE', + 'RDPCSTX_TX_FIFO_DISABLED_MASK_ENABLE', + 'RDPCS_CBUS_SOFT_RESET_DISABLE', 'RDPCS_CBUS_SOFT_RESET_ENABLE', + 'RDPCS_DBG_OCLA_SEL', 'RDPCS_DBG_OCLA_SEL_MON_OUT_15_8', + 'RDPCS_DBG_OCLA_SEL_MON_OUT_23_16', + 'RDPCS_DBG_OCLA_SEL_MON_OUT_31_24', + 'RDPCS_DBG_OCLA_SEL_MON_OUT_39_32', + 'RDPCS_DBG_OCLA_SEL_MON_OUT_47_40', + 'RDPCS_DBG_OCLA_SEL_MON_OUT_55_48', + 'RDPCS_DBG_OCLA_SEL_MON_OUT_63_56', + 'RDPCS_DBG_OCLA_SEL_MON_OUT_7_0', + 'RDPCS_DPALT_4LANE_TOGGLE_2LANE', + 'RDPCS_DPALT_4LANE_TOGGLE_4LANE', + 'RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE', + 'RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE', + 'RDPCS_DPALT_DISABLE_TOGGLE_DISABLE', + 'RDPCS_DPALT_DISABLE_TOGGLE_ENABLE', + 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE', + 'RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE', + 'RDPCS_EXT_REFCLK_DISABLE', 'RDPCS_EXT_REFCLK_ENABLE', + 'RDPCS_EXT_REFCLK_EN_DISABLE', 'RDPCS_EXT_REFCLK_EN_ENABLE', + 'RDPCS_LANE_BIT_ORDER_REVERSE_DISABLE', + 'RDPCS_LANE_BIT_ORDER_REVERSE_ENABLE', + 'RDPCS_LANE_PACK_FROM_MSB_DISABLE', + 'RDPCS_LANE_PACK_FROM_MSB_ENABLE', 'RDPCS_MEM_PWR_DEEP_SLEEP', + 'RDPCS_MEM_PWR_LIGHT_SLEEP', 'RDPCS_MEM_PWR_NO_FORCE', + 'RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP', + 'RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP', + 'RDPCS_MEM_PWR_PWR_STATE_ON', 'RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN', + 'RDPCS_MEM_PWR_SHUT_DOWN', 'RDPCS_OCLACLK_CLOCK_OFF', + 'RDPCS_OCLACLK_CLOCK_ON', 'RDPCS_OCLACLK_DISABLE', + 'RDPCS_OCLACLK_ENABLE', 'RDPCS_OCLACLK_GATE_DISABLE', + 'RDPCS_OCLACLK_GATE_ENABLE', 'RDPCS_PHY_CR_MUX_SEL_FOR_DC', + 'RDPCS_PHY_CR_MUX_SEL_FOR_USB', 'RDPCS_PHY_CR_PARA_SEL_CR', + 'RDPCS_PHY_CR_PARA_SEL_JTAG', 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6', + 'RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8', + 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1', + 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16', + 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2', + 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3', + 'RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8', + 'RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT', + 'RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT', 'RDPCS_PHY_DP_TX_RATE', + 'RDPCS_PHY_DP_TX_RATE_DIV2', 'RDPCS_PHY_DP_TX_RATE_DIV4', + 'RDPCS_PHY_DP_TX_TERM_CTRL_40', 'RDPCS_PHY_DP_TX_TERM_CTRL_42', + 'RDPCS_PHY_DP_TX_TERM_CTRL_44', 'RDPCS_PHY_DP_TX_TERM_CTRL_46', + 'RDPCS_PHY_DP_TX_TERM_CTRL_48', 'RDPCS_PHY_DP_TX_TERM_CTRL_50', + 'RDPCS_PHY_DP_TX_TERM_CTRL_52', 'RDPCS_PHY_DP_TX_TERM_CTRL_54', + 'RDPCS_PHY_DP_TX_WIDTH_10', 'RDPCS_PHY_DP_TX_WIDTH_16', + 'RDPCS_PHY_DP_TX_WIDTH_20', 'RDPCS_PHY_DP_TX_WIDTH_8', + 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', + 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', + 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', + 'RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', + 'RDPCS_PHY_REF_ALT_CLK_DISABLE', 'RDPCS_PHY_REF_ALT_CLK_ENABLE', + 'RDPCS_PHY_REF_RANGE_0', 'RDPCS_PHY_REF_RANGE_1', + 'RDPCS_PHY_REF_RANGE_2', 'RDPCS_PHY_REF_RANGE_3', + 'RDPCS_PHY_REF_RANGE_4', 'RDPCS_PHY_REF_RANGE_5', + 'RDPCS_PHY_REF_RANGE_6', 'RDPCS_PHY_REF_RANGE_7', + 'RDPCS_REG_FIFO_ERROR_MASK_DISABLE', + 'RDPCS_REG_FIFO_ERROR_MASK_ENABLE', 'RDPCS_SRAMCLK_DISABLE', + 'RDPCS_SRAMCLK_ENABLE', 'RDPCS_SRAMCLK_GATE_DISABLE', + 'RDPCS_SRAMCLK_GATE_ENABLE', 'RDPCS_SRAMCLK_NOT_PASS', + 'RDPCS_SRAMCLK_PASS', 'RDPCS_SRAM_EXT_LD_DONE', + 'RDPCS_SRAM_EXT_LD_NOT_DONE', 'RDPCS_SRAM_INIT_DONE', + 'RDPCS_SRAM_INIT_NOT_DONE', 'RDPCS_SRAM_SRAM_RESET_DISABLE', + 'RDPCS_SRAM_SRAM_RESET_ENABLE', 'RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF', + 'RDPCS_SYMCLK_SRAMCLK_CLOCK_ON', 'RDPCS_TEST_CLK_SEL', + 'RDPCS_TEST_CLK_SEL_CFGCLK', + 'RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', + 'RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK', + 'RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK', + 'RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK', + 'RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK', + 'RDPCS_TEST_CLK_SEL_EXT_CR_CLK', + 'RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', + 'RDPCS_TEST_CLK_SEL_NONE', 'RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK', + 'RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk', 'RDPCS_TEST_CLK_SEL_SRAMCLK', + 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', + 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', + 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', + 'RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', + 'RDPCS_TEST_CLK_SEL_dtb_out0', 'RDPCS_TEST_CLK_SEL_dtb_out1', + 'RDPCS_TX_CLK_CLOCK_OFF', 'RDPCS_TX_CLK_CLOCK_ON', + 'RDPCS_TX_CLK_DISABLE', 'RDPCS_TX_CLK_ENABLE', + 'RDPCS_TX_CLK_GATE_DISABLE', 'RDPCS_TX_CLK_GATE_ENABLE', + 'RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB', 'RDPCS_TX_FIFO_DISABLE', + 'RDPCS_TX_FIFO_ENABLE', 'RDPCS_TX_FIFO_ERROR_MASK_DISABLE', + 'RDPCS_TX_FIFO_ERROR_MASK_ENABLE', 'RDPCS_TX_FIFO_LANE_DISABLE', + 'RDPCS_TX_FIFO_LANE_ENABLE', 'RDPCS_TX_SOFT_RESET_DISABLE', + 'RDPCS_TX_SOFT_RESET_ENABLE', + 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE', + 'RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE', + 'READ_COMPRESSION_MODE', 'READ_SEQ', 'RECTLIST', 'RECT_2D', + 'RED_LUT', 'REFER_TO_DP_SOF', 'REFER_TO_OTG_SOF', + 'REG_SECURE_VIOLATE_READ', 'REG_SECURE_VIOLATE_WRITE', + 'REG_UNALLOCATED_ADDR_READ', 'REG_UNALLOCATED_ADDR_WRITE', + 'REG_VIRTUAL_READ', 'REG_VIRTUAL_WRITE', 'RESERVED1', 'RESERVED2', + 'RESERVED3', 'RESERVED4', 'RESERVED_1', 'RESERVED_10', + 'RESERVED_11', 'RESERVED_20', 'RESERVED_21', 'RESERVED_22', + 'RESERVED_23', 'RESERVED_3', 'RESERVED_32', 'RESERVED_33', + 'RESERVED_34', 'RESERVED_35', 'RESERVED_44', 'RESERVED_45', + 'RESERVED_46', 'RESERVED_47', 'RESERVED_56', 'RESERVED_57', + 'RESERVED_58', 'RESERVED_59', 'RESERVED_60', 'RESERVED_61', + 'RESERVED_62', 'RESERVED_63', 'RESERVED_72', 'RESERVED_73', + 'RESERVED_74', 'RESERVED_75', 'RESERVED_8', 'RESERVED_84', + 'RESERVED_85', 'RESERVED_86', 'RESERVED_87', 'RESERVED_88', + 'RESERVED_89', 'RESERVED_9', 'RESERVED_90', 'RESERVED_91', + 'RESERVED_RDPOLICY', 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', + 'RESPONSE_STATUS', 'RE_Z', 'RGB111110_FIX', 'RGB111110_FLOAT', + 'RGB565', 'RGBA1010102', 'RGBA16161616_10LSB', + 'RGBA16161616_10MSB', 'RGBA16161616_12LSB', 'RGBA16161616_12MSB', + 'RGBA16161616_FLOAT', 'RGBA16161616_SNORM', 'RGBA16161616_UNORM', + 'RGBA4444', 'RGBA5551', 'RGBA8888', 'RGBE', 'RINGID0', 'RINGID1', + 'RINGID2', 'RINGID3', 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RLC_DOORBELL_MODE', 'RLC_DOORBELL_MODE_DISABLE', + 'RLC_DOORBELL_MODE_ENABLE', 'RLC_DOORBELL_MODE_ENABLE_PF', + 'RLC_DOORBELL_MODE_ENABLE_PF_VF', 'RLC_PERFCOUNTER_SEL', + 'RLC_PERFMON_STATE', 'RLC_PERFMON_STATE_DISABLE', + 'RLC_PERFMON_STATE_ENABLE', 'RLC_PERFMON_STATE_RESERVED_3', + 'RLC_PERFMON_STATE_RESERVED_4', 'RLC_PERFMON_STATE_RESERVED_5', + 'RLC_PERFMON_STATE_RESERVED_6', 'RLC_PERFMON_STATE_RESET', + 'RLC_PERFMON_STATE_ROLLOVER', 'RLC_PERF_SEL_CP_INTERRUPT', + 'RLC_PERF_SEL_GRBM_INTERRUPT', 'RLC_PERF_SEL_IH_INTERRUPT', + 'RLC_PERF_SEL_POWER_FEATURE_0', 'RLC_PERF_SEL_POWER_FEATURE_1', + 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', 'RLC_PERF_SEL_SPM_INTERRUPT', + 'RMIPerfSel', 'RMI_PERF_SEL_BUSY', + 'RMI_PERF_SEL_CONSUMER_PROBEGEN_CB_RTS_RTR', + 'RMI_PERF_SEL_CONSUMER_PROBEGEN_DB_RTS_RTR', + 'RMI_PERF_SEL_CONSUMER_PROBEGEN_IN0_RTS_RTR', + 'RMI_PERF_SEL_CONSUMER_PROBEGEN_IN1_RTS_RTR', + 'RMI_PERF_SEL_CONSUMER_PROBEGEN_READ_RTS_RTR', + 'RMI_PERF_SEL_CONSUMER_PROBEGEN_WRITE_RTS_RTR', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', + 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', + 'RMI_PERF_SEL_DYN_CLK_RB_VLD', 'RMI_PERF_SEL_EVENT_SEND', + 'RMI_PERF_SEL_NONE', 'RMI_PERF_SEL_PERF_WINDOW', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', + 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', + 'RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY', + 'RMI_PERF_SEL_RB_RMI_RD_BUSY', + 'RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY', + 'RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX', 'RMI_PERF_SEL_RB_RMI_RD_IDLE', + 'RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY', + 'RMI_PERF_SEL_RB_RMI_RD_STALL', 'RMI_PERF_SEL_RB_RMI_RD_STARVE', + 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', + 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', + 'RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY', + 'RMI_PERF_SEL_RB_RMI_WR_BUSY', + 'RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY', + 'RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX', 'RMI_PERF_SEL_RB_RMI_WR_IDLE', + 'RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY', + 'RMI_PERF_SEL_RB_RMI_WR_STALL', 'RMI_PERF_SEL_RB_RMI_WR_STARVE', + 'RMI_PERF_SEL_REG_CLK_VLD', 'RMI_PERF_SEL_REORDER_FIFO_BUSY', + 'RMI_PERF_SEL_REORDER_FIFO_REQ', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', + 'RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID', + 'RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID', + 'RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND', + 'RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND', + 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', + 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', + 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', + 'RMI_PERF_SEL_RMI_TC_STALL_ALLREQ', + 'RMI_PERF_SEL_RMI_TC_STALL_RDREQ', + 'RMI_PERF_SEL_RMI_TC_STALL_WRREQ', + 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', + 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', + 'RMI_PERF_SEL_TCIW_BUSY', 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', + 'RMI_PERF_SEL_TCIW_REQ', + 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', + 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', 'ROM_SIGNATURE', + 'ROTATE_0_DEGREES', 'ROTATE_180_DEGREES', 'ROTATE_270_DEGREES', + 'ROTATE_90_DEGREES', 'ROTATION_ANGLE', 'ROW_TTU_MODE', + 'RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK', + 'RRDPCS_PHY_DP_TX_PSTATE_HOLD', + 'RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF', + 'RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN', + 'RRDPCS_PHY_DP_TX_PSTATE_POWER_UP', 'RSPM_CMD', + 'RSPM_CMD_CALIBRATE', 'RSPM_CMD_FORCE_SAMPLE', 'RSPM_CMD_IDLE', + 'RSPM_CMD_INVALID', 'RSPM_CMD_PERF_RESET', 'RSPM_CMD_PERF_SAMPLE', + 'RSPM_CMD_PROF_START', 'RSPM_CMD_PROF_STOP', 'RSPM_CMD_SPM_RESET', + 'RSPM_CMD_SPM_START', 'RSPM_CMD_SPM_STOP', 'RST_PIX_CNT', + 'RSV_TAG_RAM', 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', + 'ReadPolicy', 'Reserved_0x00', 'RingCounterControl', + 'SAMPLE_PIPELINESTAT', 'SAMPLE_STREAMOUTSTATS', + 'SAMPLE_STREAMOUTSTATS1', 'SAMPLE_STREAMOUTSTATS2', + 'SAMPLE_STREAMOUTSTATS3', 'SCL_2TAP_HARDCODE', 'SCL_ALPHA_COEF', + 'SCL_ALPHA_COEF_FIRST', 'SCL_ALPHA_COEF_SECOND', + 'SCL_AUTOCAL_MODE', 'SCL_BOUNDARY', 'SCL_BOUNDARY_BLACK', + 'SCL_BOUNDARY_EDGE', 'SCL_CHROMA_COEF', 'SCL_CHROMA_COEF_FIRST', + 'SCL_CHROMA_COEF_SECOND', 'SCL_COEF_2TAP_HARDCODE_OFF', + 'SCL_COEF_2TAP_HARDCODE_ON', 'SCL_COEF_CHROMA_HORZ_FILTER', + 'SCL_COEF_CHROMA_VERT_FILTER', 'SCL_COEF_FILTER_TYPE_SEL', + 'SCL_COEF_LUMA_HORZ_FILTER', 'SCL_COEF_LUMA_VERT_FILTER', + 'SCL_COEF_RAM_SEL', 'SCL_COEF_RAM_SEL_0', 'SCL_COEF_RAM_SEL_1', + 'SCL_COEF_SC_HORZ_FILTER', 'SCL_COEF_SC_VERT_FILTER', + 'SCL_SHARP_DISABLE', 'SCL_SHARP_EN', 'SCL_SHARP_ENABLE', 'SCOPE', + 'SCOPE_CU', 'SCOPE_DEV', 'SCOPE_SE', 'SCOPE_SYS', + 'SC_BACKEND_BUSY', 'SC_BACKEND_PRIM_FIFO_FULL', 'SC_BB_DISCARD', + 'SC_BCI_CREDIT_AT_MAX', 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', + 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_BCI_SEND', + 'SC_BE_VRS_FB_RET', 'SC_BE_VRS_FB_RET_HIT', + 'SC_BE_VRS_FB_RET_STALLED', 'SC_BE_VRS_RD_REQ', + 'SC_BE_VRS_RD_REQ_HIT', 'SC_BE_VRS_RD_REQ_STALLED', + 'SC_BE_VRS_RD_RET', 'SC_BE_VRS_RD_RET_STALLED', + 'SC_BM_BE0_STALLED', 'SC_BM_BE1_STALLED', 'SC_BM_BE2_STALLED', + 'SC_BM_BE3_STALLED', 'SC_BM_BUSY', + 'SC_BM_MULTI_ACCUM_1_BE_STALLED', + 'SC_BM_MULTI_ACCUM_2_BE_STALLED', + 'SC_BM_MULTI_ACCUM_3_BE_STALLED', + 'SC_BM_MULTI_ACCUM_4_BE_STALLED', 'SC_BUSY_CNT_NOT_ZERO', + 'SC_DB0_QUAD_INTF_BUSY', 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', + 'SC_DB0_QUAD_INTF_IDLE', 'SC_DB0_QUAD_INTF_SEND', + 'SC_DB0_QUAD_INTF_STALLED_BY_DB', 'SC_DB0_TILE_INTERFACE_BUSY', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'SC_DB0_TILE_INTERFACE_SEND', 'SC_DB0_TILE_INTERFACE_SEND_EVENT', + 'SC_DB0_TILE_MASK_FIFO_FULL', + 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', + 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX', + 'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX', + 'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_GL1X_BUSY', + 'SC_GRP0_DYN_SCLK_BUSY', 'SC_GRP1_DYN_SCLK_BUSY', + 'SC_GRP2_DYN_SCLK_BUSY', 'SC_GRP3_DYN_SCLK_BUSY', + 'SC_GRP4_DYN_SCLK_BUSY', 'SC_GRP5_DYN_SCLK_BUSY', + 'SC_GRP6_DYN_SCLK_BUSY', 'SC_GRP7_DYN_SCLK_BUSY', + 'SC_GRP8_DYN_SCLK_BUSY', 'SC_GRP9_DYN_SCLK_BUSY', 'SC_HALF_LSB', + 'SC_LSB_ONE_SIDED', 'SC_LSB_TWO_SIDED', 'SC_P0_DETAIL_QUAD_COUNT', + 'SC_P0_DETAIL_QUAD_WITH_1_PIX', 'SC_P0_DETAIL_QUAD_WITH_2_PIX', + 'SC_P0_DETAIL_QUAD_WITH_3_PIX', 'SC_P0_DETAIL_QUAD_WITH_4_PIX', + 'SC_P0_HIZ_QUAD_COUNT', 'SC_P0_HIZ_QUAD_PER_TILE_H0', + 'SC_P0_HIZ_QUAD_PER_TILE_H1', 'SC_P0_HIZ_QUAD_PER_TILE_H10', + 'SC_P0_HIZ_QUAD_PER_TILE_H11', 'SC_P0_HIZ_QUAD_PER_TILE_H12', + 'SC_P0_HIZ_QUAD_PER_TILE_H13', 'SC_P0_HIZ_QUAD_PER_TILE_H14', + 'SC_P0_HIZ_QUAD_PER_TILE_H15', 'SC_P0_HIZ_QUAD_PER_TILE_H16', + 'SC_P0_HIZ_QUAD_PER_TILE_H2', 'SC_P0_HIZ_QUAD_PER_TILE_H3', + 'SC_P0_HIZ_QUAD_PER_TILE_H4', 'SC_P0_HIZ_QUAD_PER_TILE_H5', + 'SC_P0_HIZ_QUAD_PER_TILE_H6', 'SC_P0_HIZ_QUAD_PER_TILE_H7', + 'SC_P0_HIZ_QUAD_PER_TILE_H8', 'SC_P0_HIZ_QUAD_PER_TILE_H9', + 'SC_P0_HIZ_TILE_COUNT', 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE', + 'SC_PA0_SC_DEALLOC_2_0_RD', 'SC_PA0_SC_EOP_WE', + 'SC_PA0_SC_EVENT_WE', 'SC_PA0_SC_NULL_DEALLOC_WE', + 'SC_PA0_SC_NULL_WE', 'SC_PA_SC_DEALLOC_2_0_WE', + 'SC_PA_SC_FPOV_WE', 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', + 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', + 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', + 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', + 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', + 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', + 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', + 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', + 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', + 'SC_PBB_BUSY_AND_NO_SENDS', + 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', 'SC_PBB_END_OF_BATCH', + 'SC_PBB_END_OF_BIN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', + 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', + 'SC_PBB_READ_DEALLOC_4_0', 'SC_PBB_READ_DEALLOC_7_5', + 'SC_PBB_READ_FPOG_4_0', 'SC_PBB_READ_FPOG_7_5', 'SC_PBB_READ_PH0', + 'SC_PBB_RESERVED', 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', + 'SC_PERF_SEL_RESERVED_108', 'SC_PERF_SEL_RESERVED_109', + 'SC_PERF_SEL_RESERVED_110', 'SC_PERF_SEL_RESERVED_111', + 'SC_PERF_SEL_RESERVED_112', 'SC_PERF_SEL_RESERVED_113', + 'SC_PERF_SEL_RESERVED_114', 'SC_PERF_SEL_RESERVED_115', + 'SC_PERF_SEL_RESERVED_116', 'SC_PERF_SEL_RESERVED_117', + 'SC_PERF_SEL_RESERVED_118', 'SC_PERF_SEL_RESERVED_119', + 'SC_PERF_SEL_RESERVED_120', 'SC_PERF_SEL_RESERVED_121', + 'SC_PERF_SEL_RESERVED_122', 'SC_PERF_SEL_RESERVED_123', + 'SC_PERF_SEL_RESERVED_124', 'SC_PERF_SEL_RESERVED_125', + 'SC_PERF_SEL_RESERVED_126', 'SC_PERF_SEL_RESERVED_127', + 'SC_PERF_SEL_RESERVED_128', 'SC_PERF_SEL_RESERVED_129', + 'SC_PERF_SEL_RESERVED_130', 'SC_PERF_SEL_RESERVED_131', + 'SC_PERF_SEL_RESERVED_132', 'SC_PERF_SEL_RESERVED_133', + 'SC_PERF_SEL_RESERVED_134', 'SC_PERF_SEL_RESERVED_135', + 'SC_PERF_SEL_RESERVED_136', 'SC_PERF_SEL_RESERVED_137', + 'SC_PERF_SEL_RESERVED_138', 'SC_PERF_SEL_RESERVED_139', + 'SC_PERF_SEL_RESERVED_140', 'SC_PERF_SEL_RESERVED_141', + 'SC_PERF_SEL_RESERVED_142', 'SC_PERF_SEL_RESERVED_143', + 'SC_PERF_SEL_RESERVED_144', 'SC_PERF_SEL_RESERVED_145', + 'SC_PERF_SEL_RESERVED_146', 'SC_PERF_SEL_RESERVED_147', + 'SC_PERF_SEL_RESERVED_148', 'SC_PERF_SEL_RESERVED_149', + 'SC_PERF_SEL_RESERVED_150', 'SC_PERF_SEL_RESERVED_151', + 'SC_PERF_SEL_RESERVED_152', 'SC_PERF_SEL_RESERVED_153', + 'SC_PERF_SEL_RESERVED_154', 'SC_PERF_SEL_RESERVED_155', + 'SC_PERF_SEL_RESERVED_156', 'SC_PERF_SEL_RESERVED_157', + 'SC_PERF_SEL_RESERVED_158', 'SC_PERF_SEL_RESERVED_160', + 'SC_PERF_SEL_RESERVED_161', 'SC_PERF_SEL_RESERVED_162', + 'SC_PERF_SEL_RESERVED_164', 'SC_PERF_SEL_RESERVED_165', + 'SC_PERF_SEL_RESERVED_166', 'SC_PERF_SEL_RESERVED_184', + 'SC_PERF_SEL_RESERVED_185', 'SC_PERF_SEL_RESERVED_186', + 'SC_PERF_SEL_RESERVED_187', 'SC_PERF_SEL_RESERVED_188', + 'SC_PERF_SEL_RESERVED_189', 'SC_PERF_SEL_RESERVED_190', + 'SC_PERF_SEL_RESERVED_191', 'SC_PERF_SEL_RESERVED_192', + 'SC_PERF_SEL_RESERVED_193', 'SC_PERF_SEL_RESERVED_194', + 'SC_PERF_SEL_RESERVED_195', 'SC_PERF_SEL_RESERVED_196', + 'SC_PERF_SEL_RESERVED_197', 'SC_PERF_SEL_RESERVED_198', + 'SC_PERF_SEL_RESERVED_199', 'SC_PERF_SEL_RESERVED_200', + 'SC_PERF_SEL_RESERVED_201', 'SC_PERF_SEL_RESERVED_202', + 'SC_PERF_SEL_RESERVED_203', 'SC_PERF_SEL_RESERVED_204', + 'SC_PERF_SEL_RESERVED_205', 'SC_PERF_SEL_RESERVED_206', + 'SC_PERF_SEL_RESERVED_207', 'SC_PERF_SEL_RESERVED_208', + 'SC_PERF_SEL_RESERVED_209', 'SC_PERF_SEL_RESERVED_210', + 'SC_PERF_SEL_RESERVED_211', 'SC_PERF_SEL_RESERVED_212', + 'SC_PERF_SEL_RESERVED_213', 'SC_PERF_SEL_RESERVED_214', + 'SC_PERF_SEL_RESERVED_215', 'SC_PERF_SEL_RESERVED_216', + 'SC_PERF_SEL_RESERVED_217', 'SC_PERF_SEL_RESERVED_218', + 'SC_PERF_SEL_RESERVED_219', 'SC_PERF_SEL_RESERVED_220', + 'SC_PERF_SEL_RESERVED_221', 'SC_PERF_SEL_RESERVED_222', + 'SC_PERF_SEL_RESERVED_223', 'SC_PERF_SEL_RESERVED_224', + 'SC_PERF_SEL_RESERVED_225', 'SC_PERF_SEL_RESERVED_226', + 'SC_PERF_SEL_RESERVED_227', 'SC_PERF_SEL_RESERVED_228', + 'SC_PERF_SEL_RESERVED_229', 'SC_PERF_SEL_RESERVED_230', + 'SC_PERF_SEL_RESERVED_231', 'SC_PERF_SEL_RESERVED_232', + 'SC_PERF_SEL_RESERVED_233', 'SC_PERF_SEL_RESERVED_234', + 'SC_PERF_SEL_RESERVED_236', 'SC_PERF_SEL_RESERVED_237', + 'SC_PERF_SEL_RESERVED_238', 'SC_PERF_SEL_RESERVED_240', + 'SC_PERF_SEL_RESERVED_241', 'SC_PERF_SEL_RESERVED_242', + 'SC_PERF_SEL_RESERVED_247', 'SC_PERF_SEL_RESERVED_248', + 'SC_PERF_SEL_RESERVED_249', 'SC_PERF_SEL_RESERVED_250', + 'SC_PERF_SEL_RESERVED_251', 'SC_PERF_SEL_RESERVED_252', + 'SC_PERF_SEL_RESERVED_253', 'SC_PERF_SEL_RESERVED_254', + 'SC_PERF_SEL_RESERVED_255', 'SC_PERF_SEL_RESERVED_256', + 'SC_PERF_SEL_RESERVED_257', 'SC_PERF_SEL_RESERVED_258', + 'SC_PERF_SEL_RESERVED_279', 'SC_PERF_SEL_RESERVED_280', + 'SC_PERF_SEL_RESERVED_288', 'SC_PERF_SEL_RESERVED_289', + 'SC_PERF_SEL_RESERVED_290', 'SC_PERF_SEL_RESERVED_291', + 'SC_PERF_SEL_RESERVED_293', 'SC_PERF_SEL_RESERVED_294', + 'SC_PERF_SEL_RESERVED_295', 'SC_PERF_SEL_RESERVED_296', + 'SC_PERF_SEL_RESERVED_297', 'SC_PERF_SEL_RESERVED_298', + 'SC_PERF_SEL_RESERVED_299', 'SC_PERF_SEL_RESERVED_301', + 'SC_PERF_SEL_RESERVED_303', 'SC_PERF_SEL_RESERVED_304', + 'SC_PERF_SEL_RESERVED_305', 'SC_PERF_SEL_RESERVED_306', + 'SC_PERF_SEL_RESERVED_307', 'SC_PERF_SEL_RESERVED_308', + 'SC_PERF_SEL_RESERVED_309', 'SC_PERF_SEL_RESERVED_310', + 'SC_PERF_SEL_RESERVED_311', 'SC_PERF_SEL_RESERVED_312', + 'SC_PERF_SEL_RESERVED_313', 'SC_PERF_SEL_RESERVED_314', + 'SC_PERF_SEL_RESERVED_315', 'SC_PERF_SEL_RESERVED_316', + 'SC_PERF_SEL_RESERVED_317', 'SC_PERF_SEL_RESERVED_319', + 'SC_PERF_SEL_RESERVED_320', 'SC_PERF_SEL_RESERVED_321', + 'SC_PERF_SEL_RESERVED_322', 'SC_PERF_SEL_RESERVED_323', + 'SC_PERF_SEL_RESERVED_324', 'SC_PERF_SEL_RESERVED_325', + 'SC_PERF_SEL_RESERVED_328', 'SC_PERF_SEL_RESERVED_329', + 'SC_PERF_SEL_RESERVED_330', 'SC_PERF_SEL_RESERVED_331', + 'SC_PERF_SEL_RESERVED_332', 'SC_PERF_SEL_RESERVED_333', + 'SC_PERF_SEL_RESERVED_334', 'SC_PERF_SEL_RESERVED_335', + 'SC_PERF_SEL_RESERVED_336', 'SC_PERF_SEL_RESERVED_337', + 'SC_PERF_SEL_RESERVED_340', 'SC_PERF_SEL_RESERVED_341', + 'SC_PERF_SEL_RESERVED_347', 'SC_PERF_SEL_RESERVED_348', + 'SC_PERF_SEL_RESERVED_351', 'SC_PERF_SEL_RESERVED_354', + 'SC_PERF_SEL_RESERVED_355', 'SC_PERF_SEL_RESERVED_356', + 'SC_PERF_SEL_RESERVED_357', 'SC_PERF_SEL_RESERVED_358', + 'SC_PERF_SEL_RESERVED_359', 'SC_PERF_SEL_RESERVED_360', + 'SC_PERF_SEL_RESERVED_361', 'SC_PERF_SEL_RESERVED_362', + 'SC_PERF_SEL_RESERVED_363', 'SC_PERF_SEL_RESERVED_364', + 'SC_PERF_SEL_RESERVED_365', 'SC_PERF_SEL_RESERVED_366', + 'SC_PERF_SEL_RESERVED_367', 'SC_PERF_SEL_RESERVED_368', + 'SC_PERF_SEL_RESERVED_369', 'SC_PERF_SEL_RESERVED_370', + 'SC_PERF_SEL_RESERVED_371', 'SC_PERF_SEL_RESERVED_372', + 'SC_PERF_SEL_RESERVED_375', 'SC_PERF_SEL_RESERVED_376', + 'SC_PERF_SEL_RESERVED_377', 'SC_PERF_SEL_RESERVED_378', + 'SC_PERF_SEL_RESERVED_379', 'SC_PERF_SEL_RESERVED_380', + 'SC_PERF_SEL_RESERVED_381', 'SC_PERF_SEL_RESERVED_382', + 'SC_PERF_SEL_RESERVED_383', 'SC_PERF_SEL_RESERVED_384', + 'SC_PERF_SEL_RESERVED_385', 'SC_PERF_SEL_RESERVED_423', + 'SC_PERF_SEL_RESERVED_424', 'SC_PERF_SEL_RESERVED_425', + 'SC_PERF_SEL_RESERVED_426', 'SC_PERF_SEL_RESERVED_427', + 'SC_PERF_SEL_RESERVED_428', 'SC_PERF_SEL_RESERVED_429', + 'SC_PERF_SEL_RESERVED_430', 'SC_PERF_SEL_RESERVED_431', + 'SC_PERF_SEL_RESERVED_432', 'SC_PERF_SEL_RESERVED_433', + 'SC_PERF_SEL_RESERVED_434', 'SC_PERF_SEL_RESERVED_435', + 'SC_PERF_SEL_RESERVED_436', 'SC_PERF_SEL_RESERVED_478', + 'SC_PERF_SEL_RESERVED_479', 'SC_PERF_SEL_RESERVED_483', + 'SC_PERF_SEL_RESERVED_484', 'SC_PERF_SEL_RESERVED_485', + 'SC_PERF_SEL_RESERVED_486', 'SC_PERF_SEL_RESERVED_487', + 'SC_PERF_SEL_RESERVED_488', 'SC_PERF_SEL_RESERVED_489', + 'SC_PERF_SEL_RESERVED_490', 'SC_PERF_SEL_RESERVED_509', + 'SC_PERF_SEL_RESERVED_510', 'SC_PERF_SEL_RESERVED_511', + 'SC_PERF_SEL_RESERVED_512', 'SC_PERF_SEL_RESERVED_513', + 'SC_PERF_SEL_RESERVED_514', 'SC_PERF_SEL_RESERVED_523', + 'SC_PERF_SEL_RESERVED_524', 'SC_PERF_SEL_RESERVED_525', + 'SC_PERF_SEL_RESERVED_532', 'SC_PERF_SEL_RESERVED_533', + 'SC_PERF_SEL_RESERVED_534', 'SC_PERF_SEL_RESERVED_539', + 'SC_PERF_SEL_RESERVED_568', 'SC_PERF_SEL_RESERVED_76', + 'SC_PERF_SEL_RESERVED_77', 'SC_PERF_SEL_RESERVED_78', + 'SC_PERF_SEL_RESERVED_80', 'SC_PERF_SEL_RESERVED_81', + 'SC_PERF_SEL_RESERVED_82', 'SC_PERF_SEL_RESERVED_84', + 'SC_PERF_SEL_RESERVED_85', 'SC_PERF_SEL_RESERVED_86', + 'SC_PERF_SEL_RESERVED_88', 'SC_PERF_SEL_RESERVED_89', + 'SC_PERF_SEL_RESERVED_90', 'SC_PKR_4X2_FILL_QUAD', + 'SC_PKR_4X2_QUAD_SPLIT', 'SC_PKR_BCI_QUAD_NEW_PRIM', + 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', + 'SC_PKR_DB_OREO_WAVE_QUAD_COUNT', 'SC_PKR_DB_WAVE_STALL', + 'SC_PKR_END_OF_VECTOR', + 'SC_PKR_OREO_STALLED_BY_NO_VALID_WAIVE_ID', + 'SC_PKR_PC_NO_CREDITS', 'SC_PKR_PC_SEND', 'SC_PKR_PC_SEND_EOV', + 'SC_PKR_PC_SEND_EVENT', 'SC_PKR_PC_SEND_PRIM_VALID_0', + 'SC_PKR_PC_SEND_PRIM_VALID_1', 'SC_PKR_PC_SEND_TRUE_PRIM', + 'SC_PKR_PC_STALLED', 'SC_PKR_PSINVOC_SEDC_FIFO_FULL', + 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', + 'SC_PKR_SPI_QUAD_COUNT', 'SC_PKR_WAVE_BREAK_FULL_TILE', + 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', 'SC_PK_BUSY', + 'SC_PK_DEALLOC_WAVE_BREAK', 'SC_PK_MAX_DEALLOC_FORCE_EOV', + 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', + 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', + 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', + 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', + 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', + 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', + 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', + 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_OREO_CONFLICT_QUAD_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', + 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', + 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', + 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', + 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', + 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', + 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', + 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', + 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_PA0_SC_FIFO_EMPTY', + 'SC_PS_PA0_SC_FIFO_FULL', 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', + 'SC_PS_PM_PFF_PW_FULL', 'SC_PS_PM_ZFF_PW_FULL', + 'SC_PS_TO_BE_SCLK_GATE_STALL', 'SC_PS_TS_EVENT_FIFO_POP', + 'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_PWS_CS_EVENTS_PWS_ENABLE', + 'SC_PWS_P0_CS_SYNC_COMPLETE', 'SC_PWS_P0_PS_SYNC_COMPLETE', + 'SC_PWS_P0_TS_SYNC_COMPLETE', 'SC_PWS_P1_CS_SYNC_COMPLETE', + 'SC_PWS_P1_PS_SYNC_COMPLETE', 'SC_PWS_P1_TS_SYNC_COMPLETE', + 'SC_PWS_PS_EVENTS_PWS_ENABLE', 'SC_PWS_STALLED', + 'SC_PWS_TS_EVENTS_PWS_ENABLE', 'SC_PW_BM_PASS_EMPTY_PRIM', + 'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0', + 'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10', + 'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12', + 'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14', + 'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16', + 'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3', + 'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5', + 'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7', + 'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9', + 'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT', + 'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZQP_WINDOW_VALID', + 'SC_QZQP_WINDOW_VALID_BUSY', 'SC_REG_SCLK_BUSY', 'SC_RESERVED_60', + 'SC_SCB_BUSY', 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', + 'SC_SEND_DB_VPZ', 'SC_SPIBC_FULL_FREEZE', 'SC_SPI_CREDIT_AT_MAX', + 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', + 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_SPI_DEALLOC_4_0', + 'SC_SPI_DEALLOC_7_5', 'SC_SPI_EVENT', 'SC_SPI_FPOV_4_0', + 'SC_SPI_FPOV_7_5', 'SC_SPI_SEND', 'SC_SPI_WAVE_STALLED_BY_SPI', + 'SC_SRPS_WINDOW_VALID', 'SC_SRPS_WINDOW_VALID_BUSY', + 'SC_STALLED_BY_BCI', 'SC_STALLED_BY_DB0_TILEFIFO', + 'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE', + 'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO', + 'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO', + 'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD', + 'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 'SC_SUPERTILE_COUNT', + 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', + 'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1', + 'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11', + 'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13', + 'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15', + 'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2', + 'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4', + 'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6', + 'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8', + 'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0', + 'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10', + 'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12', + 'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14', + 'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16', + 'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3', + 'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5', + 'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7', + 'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9', + 'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1', + 'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11', + 'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13', + 'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15', + 'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2', + 'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4', + 'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6', + 'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8', + 'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1', + 'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY', + 'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY', 'SC_UR_1X', + 'SC_UR_2X', 'SC_UR_4X', 'SC_UR_8X', 'SC_VRC_ACK_OUTPUT_STALL', + 'SC_VRC_BUSY', 'SC_VRC_DIRTY_SECTORS_FLUSHED', + 'SC_VRC_EVICT_NONZERO_INFLIGHT_STALL', 'SC_VRC_FLUSH', + 'SC_VRC_FLUSH_DONE_STALL', 'SC_VRC_FLUSH_EVICT_STALL', + 'SC_VRC_FLUSH_FIP_HIT_STALL', 'SC_VRC_FLUSH_REFLUSH_STALL', + 'SC_VRC_FLUSH_STALL', 'SC_VRC_FLUSH_WRREQ_DRAIN_STALL', + 'SC_VRC_GL1X_RD_REQ', 'SC_VRC_GL1X_RD_RET', + 'SC_VRC_GL1X_RD_XNACK', 'SC_VRC_GL1X_REQ_STALLED', + 'SC_VRC_GL1X_SRC_STALLED', 'SC_VRC_GL1X_SRC_XFR', + 'SC_VRC_GL1X_WR_ACK', 'SC_VRC_GL1X_WR_REQ', + 'SC_VRC_GL1X_WR_XNACK', 'SC_VRC_HINTMEM_RE_CNT', + 'SC_VRC_HINTMEM_WE_CNT', 'SC_VRC_HPF_EVENT', 'SC_VRC_HPF_REQ', + 'SC_VRC_HPF_STALLED', 'SC_VRC_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'SC_VRC_LRU_EVICT_PENDING_EVICT_STALL', + 'SC_VRC_LRU_EVICT_SCHEDULED_EVICT_STALL', + 'SC_VRC_LRU_EVICT_STALL', 'SC_VRC_PROBE_ACK_TILES', + 'SC_VRC_RATEMEM_RE_CNT', 'SC_VRC_RATEMEM_WE_CNT', + 'SC_VRC_READ_OUTPUT_STALL', 'SC_VRC_REEVICTION_STALL', + 'SC_VRC_REPLACE_FLUSH_IN_PROGRESS_STALL', + 'SC_VRC_REPLACE_PENDING_EVICT_STALL', + 'SC_VRC_REPLACE_SCHEDULED_EVICT_STALL', 'SC_VRC_SECTORS_FLUSHED', + 'SC_VRC_SECTOR_HIT', 'SC_VRC_SECTOR_MISS', 'SC_VRC_STALL', + 'SC_VRC_TAGS_FLUSHED', 'SC_VRC_TAG_MISS', + 'SC_VRC_WRITE_OUTPUT_STALL', 'SC_VRS_BE_BUSY', + 'SC_VRS_COMB_MODE_MAX', 'SC_VRS_COMB_MODE_MIN', + 'SC_VRS_COMB_MODE_OVERRIDE', 'SC_VRS_COMB_MODE_PASSTHRU', + 'SC_VRS_COMB_MODE_SATURATE', 'SDMA_PERFMON_SEL', + 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', 'SDMA_PERFMON_SEL_CE_DST_IDLE', + 'SDMA_PERFMON_SEL_CE_INFO1_FULL', 'SDMA_PERFMON_SEL_CE_INFO_FULL', + 'SDMA_PERFMON_SEL_CE_IN_IDLE', 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', + 'SDMA_PERFMON_SEL_CE_OUT_IDLE', 'SDMA_PERFMON_SEL_CE_RD_STALL', + 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', + 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', 'SDMA_PERFMON_SEL_CE_WR_IDLE', + 'SDMA_PERFMON_SEL_CE_WR_STALL', + 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', 'SDMA_PERFMON_SEL_CTX_CHANGE', + 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', + 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERFMON_SEL_CYCLE', + 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', + 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', + 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', + 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', 'SDMA_PERFMON_SEL_DOORBELL', + 'SDMA_PERFMON_SEL_DUMMY_0', 'SDMA_PERFMON_SEL_DUMMY_1', + 'SDMA_PERFMON_SEL_EX_IDLE', + 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'SDMA_PERFMON_SEL_GCR_RTN', 'SDMA_PERFMON_SEL_GCR_SEND', + 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', + 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', 'SDMA_PERFMON_SEL_IB_CMD_FULL', + 'SDMA_PERFMON_SEL_IB_CMD_IDLE', 'SDMA_PERFMON_SEL_IDLE', + 'SDMA_PERFMON_SEL_INT_IDLE', 'SDMA_PERFMON_SEL_INT_REQ_COUNT', + 'SDMA_PERFMON_SEL_INT_REQ_STALL', + 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', + 'SDMA_PERFMON_SEL_INT_RESP_RETRY', + 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', + 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', + 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', + 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', + 'SDMA_PERFMON_SEL_L2_META_RET_VLD', + 'SDMA_PERFMON_SEL_MCU_L1_WR_VLD', 'SDMA_PERFMON_SEL_MC_RD_COUNT', + 'SDMA_PERFMON_SEL_MC_RD_IDLE', + 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', + 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', + 'SDMA_PERFMON_SEL_MC_WR_COUNT', 'SDMA_PERFMON_SEL_MC_WR_IDLE', + 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', + 'SDMA_PERFMON_SEL_META_REQ_SEND', 'SDMA_PERFMON_SEL_META_RTN_VLD', + 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', + 'SDMA_PERFMON_SEL_NUM_PACKET', 'SDMA_PERFMON_SEL_QUEUE0_SELECT', + 'SDMA_PERFMON_SEL_QUEUE1_SELECT', + 'SDMA_PERFMON_SEL_QUEUE2_SELECT', + 'SDMA_PERFMON_SEL_QUEUE3_SELECT', 'SDMA_PERFMON_SEL_RB_CMD_FULL', + 'SDMA_PERFMON_SEL_RB_CMD_IDLE', 'SDMA_PERFMON_SEL_RB_EMPTY', + 'SDMA_PERFMON_SEL_RB_FULL', 'SDMA_PERFMON_SEL_RB_RPTR_WB', + 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', + 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', + 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', 'SDMA_PERFMON_SEL_RD_BA_RTR', + 'SDMA_PERFMON_SEL_REG_IDLE', 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', + 'SDMA_PERFMON_SEL_SEM_IDLE', 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', + 'SDMA_PERFMON_SEL_SEM_REQ_STALL', + 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', + 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', + 'SDMA_PERFMON_SEL_SEM_RESP_PASS', + 'SDMA_PERFMON_SEL_SRBM_REG_SEND', 'SDMA_PERFMON_SEL_TLBI_RTN', + 'SDMA_PERFMON_SEL_TLBI_SEND', + 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', + 'SDMA_PERFMON_SEL_UTCL2_FREE', 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', + 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', + 'SDMA_PERFMON_SEL_WR_BA_RTR', 'SDMA_PERF_SEL', + 'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_BUSY', + 'SDMA_PERF_SEL_CE_BUSY_END', 'SDMA_PERF_SEL_CE_BUSY_START', + 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', + 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', 'SDMA_PERF_SEL_CE_CH_WR_REQ', + 'SDMA_PERF_SEL_CE_CH_WR_RET', 'SDMA_PERF_SEL_CE_DST_IDLE', + 'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL', + 'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_WR_VLD', + 'SDMA_PERF_SEL_CE_OR_MCU_CH_RD_REQ', + 'SDMA_PERF_SEL_CE_OR_MCU_CH_RD_RET', 'SDMA_PERF_SEL_CE_OUT_IDLE', + 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', + 'SDMA_PERF_SEL_CGCG_FENCE', 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', + 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', 'SDMA_PERF_SEL_CMD_OP_END', + 'SDMA_PERF_SEL_CMD_OP_MATCH', 'SDMA_PERF_SEL_CMD_OP_START', + 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', 'SDMA_PERF_SEL_CTX_CHANGE', + 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', + 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_DUMMY_0', + 'SDMA_PERF_SEL_DUMMY_1', 'SDMA_PERF_SEL_EX_IDLE', + 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'SDMA_PERF_SEL_GCR_RTN', 'SDMA_PERF_SEL_GCR_SEND', + 'SDMA_PERF_SEL_GPUVM_INV_HIGH', 'SDMA_PERF_SEL_GPUVM_INV_LOW', + 'SDMA_PERF_SEL_IB_CH_RD_REQ', 'SDMA_PERF_SEL_IB_CH_RD_RET', + 'SDMA_PERF_SEL_IB_CMD_FULL', 'SDMA_PERF_SEL_IB_CMD_IDLE', + 'SDMA_PERF_SEL_IDLE', 'SDMA_PERF_SEL_INT_IDLE', + 'SDMA_PERF_SEL_INT_REQ_COUNT', 'SDMA_PERF_SEL_INT_REQ_STALL', + 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', 'SDMA_PERF_SEL_INT_RESP_RETRY', + 'SDMA_PERF_SEL_L1_RDL2_IDLE', 'SDMA_PERF_SEL_L1_RDMC_IDLE', + 'SDMA_PERF_SEL_L1_RD_INV_IDLE', 'SDMA_PERF_SEL_L1_WRL2_IDLE', + 'SDMA_PERF_SEL_L1_WRMC_IDLE', 'SDMA_PERF_SEL_L1_WR_INV_IDLE', + 'SDMA_PERF_SEL_L2_META_RET_VLD', 'SDMA_PERF_SEL_MCU_CH_WR_REQ', + 'SDMA_PERF_SEL_MCU_CH_WR_RET', 'SDMA_PERF_SEL_MCU_L1_WR_VLD', + 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER', + 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_END', + 'SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_START', + 'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE', + 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', + 'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_META_L2_REQ_SEND', + 'SDMA_PERF_SEL_META_REQ_SEND', 'SDMA_PERF_SEL_META_RTN_VLD', + 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_QUEUE0_SELECT', + 'SDMA_PERF_SEL_QUEUE1_SELECT', 'SDMA_PERF_SEL_QUEUE2_SELECT', + 'SDMA_PERF_SEL_QUEUE3_SELECT', 'SDMA_PERF_SEL_QUEUE4_SELECT', + 'SDMA_PERF_SEL_QUEUE5_SELECT', 'SDMA_PERF_SEL_QUEUE6_SELECT', + 'SDMA_PERF_SEL_QUEUE7_SELECT', 'SDMA_PERF_SEL_RB_CH_RD_REQ', + 'SDMA_PERF_SEL_RB_CH_RD_RET', 'SDMA_PERF_SEL_RB_CMD_FULL', + 'SDMA_PERF_SEL_RB_CMD_IDLE', 'SDMA_PERF_SEL_RB_EMPTY', + 'SDMA_PERF_SEL_RB_FULL', 'SDMA_PERF_SEL_RB_RPTR_WB', + 'SDMA_PERF_SEL_RB_RPTR_WRAP', 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', + 'SDMA_PERF_SEL_RB_WPTR_WRAP', 'SDMA_PERF_SEL_RD_BA_RTR', + 'SDMA_PERF_SEL_REG_IDLE', 'SDMA_PERF_SEL_SDMA_CPF_INVACK', + 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', + 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', + 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', + 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', + 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', 'SDMA_PERF_SEL_SEM_IDLE', + 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', + 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', + 'SDMA_PERF_SEL_TLBI_RTN', 'SDMA_PERF_SEL_TLBI_SEND', + 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', + 'SDMA_PERF_SEL_UTCL2_FREE', 'SDMA_PERF_SEL_UTCL2_RET_ACK', + 'SDMA_PERF_SEL_UTCL2_RET_XNACK', + 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', + 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', + 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', + 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', + 'SDMA_PERF_SEL_WPTR_CH_RD_RET', 'SDMA_PERF_SEL_WR_BA_RTR', + 'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', 'SEGMENTS_1', + 'SEGMENTS_128', 'SEGMENTS_16', 'SEGMENTS_2', 'SEGMENTS_32', + 'SEGMENTS_4', 'SEGMENTS_64', 'SEGMENTS_8', 'SEL_DTBCLK_P0', + 'SEL_DTBCLK_P1', 'SEL_DTBCLK_P2', 'SEL_DTBCLK_P3', + 'SEND_AT_EARLIEST_TIME', 'SEND_AT_LINK_NUMBER', + 'SEND_NORMAL_PACKET', 'SEND_PPS_PACKET', 'SET_SMU_MSG_INTR', + 'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32', + 'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE', + 'SH_MEM_ALIGNMENT_MODE_DWORD', + 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', + 'SIGNED', 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE', + 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START', + 'SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_SA_SDST_START', + 'SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_SDST_START', + 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_START', + 'SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_VCC_START', + 'SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_VDST_START', + 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_START', + 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', + 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', + 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', + 'SIMM16_WAIT_EVENT_EXP_RDY_SIZE', + 'SIMM16_WAIT_EVENT_EXP_RDY_START', 'SIZE_16K', 'SIZE_8K', + 'SLVERR', 'SMU_INTR', 'SMU_INTR_STATUS_CLEAR', + 'SMU_INTR_STATUS_NOOP', 'SMU_MSG_INTR_NOOP', 'SM_MODE_RESERVED', + 'SOFT_RESET', 'SOFT_RESET_0', 'SOFT_RESET_1', + 'SO_VGTSTREAMOUT_FLUSH', 'SPI_FOG_EXP', 'SPI_FOG_EXP2', + 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', 'SPI_FOG_NONE', + 'SPI_LB_WAVES_RSVD', 'SPI_LB_WAVES_SELECT', 'SPI_PERFCNT_SEL', + 'SPI_PERF_ALL_PS_WAVE', 'SPI_PERF_ALL_PS_WAVE_IN_FLIGHT', + 'SPI_PERF_ALL_WAVE', 'SPI_PERF_ALL_WAVE_IN_FLIGHT', + 'SPI_PERF_ALL_WAVE_ITEMS', 'SPI_PERF_ALL_WAVE_ITEMS_W32', + 'SPI_PERF_ALL_WAVE_ITEMS_W64', 'SPI_PERF_ALL_WAVE_RESTORED', + 'SPI_PERF_ALL_WAVE_SAVED', 'SPI_PERF_ALL_WAVE_W32', + 'SPI_PERF_ALL_WAVE_W64', 'SPI_PERF_BUSY', 'SPI_PERF_CSGN_BUSY', + 'SPI_PERF_CSGN_CRAWLER_STALL', 'SPI_PERF_CSGN_EVENT_WAVE', + 'SPI_PERF_CSGN_NUM_THREADGROUPS', 'SPI_PERF_CSGN_PWS_STALL', + 'SPI_PERF_CSGN_WAVE', 'SPI_PERF_CSGN_WAVE_IN_FLIGHT', + 'SPI_PERF_CSGN_WINDOW_VALID', 'SPI_PERF_CSG_TEMP_ALLOC_LEVEL', + 'SPI_PERF_CSN_BUSY', 'SPI_PERF_CSN_CRAWLER_STALL', + 'SPI_PERF_CSN_EVENT_WAVE', 'SPI_PERF_CSN_NUM_THREADGROUPS', + 'SPI_PERF_CSN_TEMP_ALLOC_LEVEL', 'SPI_PERF_CSN_WAVE', + 'SPI_PERF_CSN_WAVE_IN_FLIGHT', 'SPI_PERF_CSN_WINDOW_VALID', + 'SPI_PERF_EXPORT_DB0_STALL', 'SPI_PERF_EXPORT_DB1_STALL', + 'SPI_PERF_EXPORT_DB2_STALL', 'SPI_PERF_EXPORT_DB3_STALL', + 'SPI_PERF_EXPORT_DB4_STALL', 'SPI_PERF_EXPORT_DB5_STALL', + 'SPI_PERF_EXPORT_DB6_STALL', 'SPI_PERF_EXPORT_DB7_STALL', + 'SPI_PERF_EXPORT_SCB0_STALL', 'SPI_PERF_EXPORT_SCB1_STALL', + 'SPI_PERF_EXPORT_SCB2_STALL', 'SPI_PERF_EXPORT_SCB3_STALL', + 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', + 'SPI_PERF_EXP_ARB_IDX_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', + 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', + 'SPI_PERF_EXP_THROT_DOWNSTEP', 'SPI_PERF_EXP_THROT_UPSTEP', + 'SPI_PERF_EXP_WITH_CONFLICT', 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', + 'SPI_PERF_GFX_TEMP_ALLOC_LEVEL', 'SPI_PERF_GS_ALLOC_IDX', + 'SPI_PERF_GS_ALLOC_POS', 'SPI_PERF_GS_BUSY', + 'SPI_PERF_GS_CRAWLER_STALL', 'SPI_PERF_GS_EVENT_WAVE', + 'SPI_PERF_GS_EXP_DONE', 'SPI_PERF_GS_FIRST_SUBGRP', + 'SPI_PERF_GS_GRP_LIFETIME', 'SPI_PERF_GS_GRP_LIFETIME_SAMPLE', + 'SPI_PERF_GS_HS_DEALLOC', 'SPI_PERF_GS_INDX0_STALL', + 'SPI_PERF_GS_INDX1_STALL', 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', + 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', + 'SPI_PERF_GS_NGG_STALL_MSG_VAL', 'SPI_PERF_GS_PERS_UPD_FULL0', + 'SPI_PERF_GS_PERS_UPD_FULL1', 'SPI_PERF_GS_POS0_STALL', + 'SPI_PERF_GS_POS1_STALL', 'SPI_PERF_GS_PWS_STALL', + 'SPI_PERF_GS_SCBD_IDX_CLEANUP', 'SPI_PERF_GS_SCBD_POS_CLEANUP', + 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WAVE_IN_FLIGHT', + 'SPI_PERF_GS_WINDOW_VALID', 'SPI_PERF_HS_BUSY', + 'SPI_PERF_HS_CRAWLER_STALL', 'SPI_PERF_HS_EVENT_WAVE', + 'SPI_PERF_HS_FIRST_WAVE', 'SPI_PERF_HS_PERS_UPD_FULL0', + 'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_PWS_STALL', + 'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WAVE_IN_FLIGHT', + 'SPI_PERF_HS_WINDOW_VALID', 'SPI_PERF_LDS_ALLOC_LEVEL', + 'SPI_PERF_NUM_EXPGRANT_EXPORTS', + 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', + 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', + 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', + 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', + 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', + 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', + 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', + 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', + 'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PS0_2_WAVE_GROUPS', + 'SPI_PERF_PS0_ACTIVE', 'SPI_PERF_PS0_BUSY', + 'SPI_PERF_PS0_CRAWLER_STALL', 'SPI_PERF_PS0_DEALLOC', + 'SPI_PERF_PS0_DEALLOC_FULL', 'SPI_PERF_PS0_EVENT_WAVE', + 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', + 'SPI_PERF_PS0_LDS_DONE_FULL', 'SPI_PERF_PS0_OPT_WAVE', + 'SPI_PERF_PS0_PRIM_BIN0', 'SPI_PERF_PS0_PRIM_BIN1', + 'SPI_PERF_PS0_WAVE', 'SPI_PERF_PS0_WAVEID_STARVED', + 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS0_WAVE_IN_FLIGHT', + 'SPI_PERF_PS0_WINDOW_VALID', 'SPI_PERF_PS1_2_WAVE_GROUPS', + 'SPI_PERF_PS1_ACTIVE', 'SPI_PERF_PS1_BUSY', + 'SPI_PERF_PS1_CRAWLER_STALL', 'SPI_PERF_PS1_DEALLOC', + 'SPI_PERF_PS1_DEALLOC_FULL', 'SPI_PERF_PS1_EVENT_WAVE', + 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', + 'SPI_PERF_PS1_LDS_DONE_FULL', 'SPI_PERF_PS1_OPT_WAVE', + 'SPI_PERF_PS1_PRIM_BIN0', 'SPI_PERF_PS1_PRIM_BIN1', + 'SPI_PERF_PS1_WAVE', 'SPI_PERF_PS1_WAVEID_STARVED', + 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS1_WAVE_IN_FLIGHT', + 'SPI_PERF_PS1_WINDOW_VALID', 'SPI_PERF_PS2_2_WAVE_GROUPS', + 'SPI_PERF_PS2_ACTIVE', 'SPI_PERF_PS2_BUSY', + 'SPI_PERF_PS2_CRAWLER_STALL', 'SPI_PERF_PS2_DEALLOC', + 'SPI_PERF_PS2_DEALLOC_FULL', 'SPI_PERF_PS2_EVENT_WAVE', + 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', + 'SPI_PERF_PS2_LDS_DONE_FULL', 'SPI_PERF_PS2_OPT_WAVE', + 'SPI_PERF_PS2_PRIM_BIN0', 'SPI_PERF_PS2_PRIM_BIN1', + 'SPI_PERF_PS2_WAVE', 'SPI_PERF_PS2_WAVEID_STARVED', + 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS2_WAVE_IN_FLIGHT', + 'SPI_PERF_PS2_WINDOW_VALID', 'SPI_PERF_PS3_2_WAVE_GROUPS', + 'SPI_PERF_PS3_ACTIVE', 'SPI_PERF_PS3_BUSY', + 'SPI_PERF_PS3_CRAWLER_STALL', 'SPI_PERF_PS3_DEALLOC', + 'SPI_PERF_PS3_DEALLOC_FULL', 'SPI_PERF_PS3_EVENT_WAVE', + 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', + 'SPI_PERF_PS3_LDS_DONE_FULL', 'SPI_PERF_PS3_OPT_WAVE', + 'SPI_PERF_PS3_PRIM_BIN0', 'SPI_PERF_PS3_PRIM_BIN1', + 'SPI_PERF_PS3_WAVE', 'SPI_PERF_PS3_WAVEID_STARVED', + 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS3_WAVE_IN_FLIGHT', + 'SPI_PERF_PS3_WINDOW_VALID', 'SPI_PERF_PS_EXP_ALLOC', + 'SPI_PERF_PS_EXP_ARB_CONFLICT', 'SPI_PERF_PS_EXP_DONE', + 'SPI_PERF_PS_PERS_UPD_FULL0', 'SPI_PERF_PS_PERS_UPD_FULL1', + 'SPI_PERF_PS_PWS_STALL', 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', 'SPI_PERF_RA_BAR_CU_FULL_CSG', + 'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_GS', + 'SPI_PERF_RA_BAR_CU_FULL_HS', 'SPI_PERF_RA_BAR_CU_FULL_PS', + 'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN', + 'SPI_PERF_RA_CSC_UNDER_TUNNEL', 'SPI_PERF_RA_CSG_LOCK', + 'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_GFX_UNDER_TUNNEL', + 'SPI_PERF_RA_GS_LDS_OCCUPANCY', 'SPI_PERF_RA_GS_LOCK', + 'SPI_PERF_RA_GS_VGPR_OCCUPANCY', 'SPI_PERF_RA_HS_LOCK', + 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 'SPI_PERF_RA_LDS_CU_FULL_GS', 'SPI_PERF_RA_LDS_CU_FULL_HS', + 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_PC_PROBE_STALL_PS', + 'SPI_PERF_RA_PC_PSWAVE_STALL_PS', 'SPI_PERF_RA_PH_THROTTLE', + 'SPI_PERF_RA_PIPE_REQ_BIN2', 'SPI_PERF_RA_PRE_ALLOC_STALL', + 'SPI_PERF_RA_PS_LDS_OCCUPANCY', 'SPI_PERF_RA_PS_VGPR_OCCUPANCY', + 'SPI_PERF_RA_REQ_ALLOC', + 'SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_CU_LEVEL', + 'SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_STALL', + 'SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_LEVEL', + 'SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_STALL', + 'SPI_PERF_RA_REQ_NO_ALLOC', 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', + 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', 'SPI_PERF_RA_REQ_NO_ALLOC_GS', + 'SPI_PERF_RA_REQ_NO_ALLOC_HS', 'SPI_PERF_RA_REQ_NO_ALLOC_PS', + 'SPI_PERF_RA_RES_STALL_CSG', 'SPI_PERF_RA_RES_STALL_CSN', + 'SPI_PERF_RA_RES_STALL_GS', 'SPI_PERF_RA_RES_STALL_HS', + 'SPI_PERF_RA_RES_STALL_PS', 'SPI_PERF_RA_RSV_UPD', + 'SPI_PERF_RA_SPI_THROTTLE', 'SPI_PERF_RA_TASK_REQ_BIN3', + 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', + 'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS', + 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 'SPI_PERF_RA_WR_CTL_FULL', 'SPI_PERF_RA_WVALLOC_STALL', + 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', + 'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS', + 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_SGPR_INIT', + 'SPI_PERF_SWC_CSGN_WR', 'SPI_PERF_SWC_CSN_WR', + 'SPI_PERF_SWC_GS_WR', 'SPI_PERF_SWC_HS_WR', 'SPI_PERF_SWC_PS_WR', + 'SPI_PERF_VGPR_ALLOC_LEVEL', 'SPI_PERF_VGPR_INIT', + 'SPI_PERF_VWC_CSGN_WR', 'SPI_PERF_VWC_CSN_WR', + 'SPI_PERF_VWC_ES_WR', 'SPI_PERF_VWC_GS_WR', 'SPI_PERF_VWC_HS_WR', + 'SPI_PERF_VWC_LS_WR', 'SPI_PERF_VWC_PS_WR', + 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', + 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', + 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', + 'SPI_PS_LDS_GROUP_1', 'SPI_PS_LDS_GROUP_2', 'SPI_PS_LDS_GROUP_4', + 'SPI_PS_LDS_GROUP_SIZE', 'SPI_SAMPLE_CNTL', 'SPI_SHADER_1COMP', + 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', 'SPI_SHADER_32_AR', + 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', 'SPI_SHADER_4COMP', + 'SPI_SHADER_4COMPRESS', 'SPI_SHADER_EX_FORMAT', + 'SPI_SHADER_FORMAT', 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', + 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', + 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', + 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', + 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', + 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', + 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', + 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', 'SP_PERF_SEL_DUMMY_LAST', + 'SP_PERF_SEL_SRC_CACHE_HIT_B0', 'SP_PERF_SEL_SRC_CACHE_HIT_B1', + 'SP_PERF_SEL_SRC_CACHE_HIT_B2', 'SP_PERF_SEL_SRC_CACHE_HIT_B3', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', + 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', + 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', + 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', + 'SP_PERF_SEL_VALU_OPERAND', + 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', + 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', + 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', 'SP_PERF_SEL_VALU_STALL', + 'SP_PERF_SEL_VALU_STALL_DST_STALL', + 'SP_PERF_SEL_VALU_STALL_SDST_FWD', + 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', + 'SP_PERF_SEL_VALU_STALL_VDST_FWD', + 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', + 'SP_PERF_SEL_VALU_VGPR_OPERAND', + 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_EXP', + 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_LDS', + 'SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_TEX', + 'SP_PERF_SEL_VGPR_EXP_RD', 'SP_PERF_SEL_VGPR_RD', + 'SP_PERF_SEL_VGPR_SPI_WR', 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', + 'SP_PERF_SEL_VGPR_VMEM_RD', 'SP_PERF_SEL_VGPR_WR', + 'SP_PERF_SEL_VGPR_WR_KILL', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GCR', + 'SQC_PERF_SEL_DCACHE_GCR_HITS', + 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_DCACHE_HITS', + 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_MISSES', + 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', + 'SQC_PERF_SEL_DCACHE_PREFETCH_MISSES', + 'SQC_PERF_SEL_DCACHE_PREFETCH_REQ_CACHELINES', + 'SQC_PERF_SEL_DCACHE_REQ', 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 'SQC_PERF_SEL_DCACHE_REQ_READ_8', + 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', + 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DUMMY_LAST', 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_ICACHE_GCR', 'SQC_PERF_SEL_ICACHE_GCR_HITS', + 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_ICACHE_HITS', + 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', + 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', + 'SQC_PERF_SEL_ICACHE_PREFETCH_MISSES', + 'SQC_PERF_SEL_ICACHE_PREFETCH_REQ_CACHELINES', + 'SQC_PERF_SEL_ICACHE_REQ', + 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_LDS_ACTIVE_ATOMIC_CNT', + 'SQC_PERF_SEL_LDS_ACTIVE_LOAD_CNT', + 'SQC_PERF_SEL_LDS_ACTIVE_STORE_CNT', + 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', + 'SQC_PERF_SEL_LDS_ADDR_STALL', 'SQC_PERF_SEL_LDS_ATOMIC_DWORDS', + 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', + 'SQC_PERF_SEL_LDS_BANKCONF_ATOMIC_CNT', + 'SQC_PERF_SEL_LDS_BANKCONF_LOAD_CNT', + 'SQC_PERF_SEL_LDS_BANKCONF_STORE_CNT', + 'SQC_PERF_SEL_LDS_BANK_CONFLICT', + 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', 'SQC_PERF_SEL_LDS_IDX_ACTIVE', + 'SQC_PERF_SEL_LDS_LDS_EXECUTION_STALL', + 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', + 'SQC_PERF_SEL_LDS_LOAD_DWORDS', 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', + 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', + 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', + 'SQC_PERF_SEL_LDS_STORE_DWORDS', + 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', + 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', 'SQC_PERF_SEL_LDS_VGPR_BUSY', + 'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_READ_REQ', + 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', + 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', + 'SQC_PERF_SEL_TC_STARVE', 'SQC_PERF_SEL_TD_VGPR_BUSY', + 'SQDEC_BEGIN', 'SQDEC_END', 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', + 'SQG_PERF_SEL', 'SQG_PERF_SEL_ACCUM_PREV', + 'SQG_PERF_SEL_BUSY_CYCLES', 'SQG_PERF_SEL_CYCLES', + 'SQG_PERF_SEL_DUMMY_LAST', 'SQG_PERF_SEL_EVENTS', + 'SQG_PERF_SEL_EXP_BUS0_BUSY', 'SQG_PERF_SEL_EXP_BUS1_BUSY', + 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', + 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', 'SQG_PERF_SEL_ITEMS', + 'SQG_PERF_SEL_ITEMS_CS', 'SQG_PERF_SEL_ITEMS_GS', + 'SQG_PERF_SEL_ITEMS_HS', 'SQG_PERF_SEL_ITEMS_PS', + 'SQG_PERF_SEL_LEVEL_WAVES', 'SQG_PERF_SEL_LEVEL_WGP_ACTIVE', + 'SQG_PERF_SEL_MSG', 'SQG_PERF_SEL_MSG_BUS_BUSY', + 'SQG_PERF_SEL_MSG_INTERRUPT', 'SQG_PERF_SEL_NONE', + 'SQG_PERF_SEL_PS_QUADS', 'SQG_PERF_SEL_REFCLKS', + 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', 'SQG_PERF_SEL_TTRACE_STALL', + 'SQG_PERF_SEL_TTRACE_WRITE_DATA', 'SQG_PERF_SEL_WAVE32_ITEMS', + 'SQG_PERF_SEL_WAVE64_ITEMS', 'SQG_PERF_SEL_WAVES', + 'SQG_PERF_SEL_WAVES_32', 'SQG_PERF_SEL_WAVES_64', + 'SQG_PERF_SEL_WAVES_CS_VEC32', 'SQG_PERF_SEL_WAVES_DYN_VGPR', + 'SQG_PERF_SEL_WAVES_EQ_32', 'SQG_PERF_SEL_WAVES_EQ_64', + 'SQG_PERF_SEL_WAVES_GS_VEC32', 'SQG_PERF_SEL_WAVES_HS_VEC32', + 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', 'SQG_PERF_SEL_WAVES_LT_16', + 'SQG_PERF_SEL_WAVES_LT_32', 'SQG_PERF_SEL_WAVES_LT_48', + 'SQG_PERF_SEL_WAVES_LT_64', 'SQG_PERF_SEL_WAVES_PS_VEC32', + 'SQG_PERF_SEL_WAVES_RESTORED', 'SQG_PERF_SEL_WAVES_SAVED', + 'SQG_PERF_SEL_WAVES_VEC32', 'SQG_PERF_SEL_WAVES_WGP_TAKEOVER', + 'SQG_PERF_SEL_WAVE_CYCLES', 'SQIND_GLOBAL_REGS_OFFSET', + 'SQIND_GLOBAL_REGS_SIZE', 'SQIND_LOCAL_REGS_OFFSET', + 'SQIND_LOCAL_REGS_SIZE', 'SQIND_WAVE_HOST_REGS_OFFSET', + 'SQIND_WAVE_HOST_REGS_SIZE', 'SQIND_WAVE_HW_REGS_OFFSET', + 'SQIND_WAVE_HW_REGS_SIZE', 'SQIND_WAVE_SGPRS_OFFSET', + 'SQIND_WAVE_SGPRS_SIZE', 'SQIND_WAVE_VGPRS_OFFSET', + 'SQIND_WAVE_VGPRS_SIZE', 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', + 'SQPERFSDEC_BEGIN', 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', + 'SQPWRDEC_END', 'SQ_ARB_STATE_ISSUED_BRMSG', + 'SQ_ARB_STATE_ISSUED_EXPORT', 'SQ_ARB_STATE_ISSUED_LDS', + 'SQ_ARB_STATE_ISSUED_LDS_DIRECT', 'SQ_ARB_STATE_ISSUED_SCALAR', + 'SQ_ARB_STATE_ISSUED_TEX', 'SQ_ARB_STATE_ISSUED_VALU', + 'SQ_ARB_STATE_STALLED_BRMSG', 'SQ_ARB_STATE_STALLED_EXPORT', + 'SQ_ARB_STATE_STALLED_LDS', 'SQ_ARB_STATE_STALLED_LDS_DIRECT', + 'SQ_ARB_STATE_STALLED_SCALAR', 'SQ_ARB_STATE_STALLED_TEX', + 'SQ_ARB_STATE_STALLED_VALU', 'SQ_CAC_POWER_ALU_BUSY', + 'SQ_CAC_POWER_GPR_RD', 'SQ_CAC_POWER_GPR_WR', + 'SQ_CAC_POWER_LDS_BUSY', 'SQ_CAC_POWER_SEL', + 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', + 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', + 'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN', + 'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS', + 'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID', + 'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR', + 'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR', + 'SQ_EX_EXCP_ADDR_WATCH', 'SQ_EX_EXCP_ALU_FLOAT_DIV0', + 'SQ_EX_EXCP_ALU_INEXACT', 'SQ_EX_EXCP_ALU_INPUT_DENORM', + 'SQ_EX_EXCP_ALU_INT_DIV0', 'SQ_EX_EXCP_ALU_INVALID', + 'SQ_EX_EXCP_ALU_OVERFLOW', 'SQ_EX_EXCP_ALU_UNDERFLOW', + 'SQ_EX_EXCP_VALU_BASE', 'SQ_EX_EXCP_VALU_SIZE', 'SQ_FLAT', + 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', + 'SQ_GLOBAL', 'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET', + 'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE', + 'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT', + 'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', + 'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX', + 'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', + 'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL', + 'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT', + 'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SYS_PRIO', + 'SQ_IND_CMD_CMD_SINGLE_STEP', 'SQ_IND_CMD_CMD_TRAP', + 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', 'SQ_IND_CMD_MODE', + 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', + 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', + 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', + 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', 'SQ_INST_STR_ST', + 'SQ_INST_TYPE', 'SQ_INST_TYPE_BARRIER', + 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', 'SQ_INST_TYPE_BRANCH_TAKEN', + 'SQ_INST_TYPE_DUAL_VALU', 'SQ_INST_TYPE_EXP', 'SQ_INST_TYPE_FLAT', + 'SQ_INST_TYPE_JUMP', 'SQ_INST_TYPE_LDS', + 'SQ_INST_TYPE_LDS_DIRECT', 'SQ_INST_TYPE_MSG', + 'SQ_INST_TYPE_NONE', 'SQ_INST_TYPE_OTHER', 'SQ_INST_TYPE_SCALAR', + 'SQ_INST_TYPE_TEX', 'SQ_INST_TYPE_VALU', + 'SQ_INST_TYPE_VALU_MATRIX', 'SQ_LLC_0', 'SQ_LLC_1', + 'SQ_LLC_BYPASS', 'SQ_LLC_CTL', 'SQ_LLC_RSVD_2', + 'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', 'SQ_NON_EVENT', + 'SQ_NO_INST_ISSUE', 'SQ_NO_INST_ISSUE_ALU_DEP', + 'SQ_NO_INST_ISSUE_BARRIER_WAIT', 'SQ_NO_INST_ISSUE_INTERNAL', + 'SQ_NO_INST_ISSUE_NO_ARB_WIN', 'SQ_NO_INST_ISSUE_NO_INSTS', + 'SQ_NO_INST_ISSUE_OTHER', 'SQ_NO_INST_ISSUE_SLEEP_WAIT', + 'SQ_NO_INST_ISSUE_S_WAITCNT', 'SQ_OOB_COMPLETE', + 'SQ_OOB_INDEX_AND_OFFSET', 'SQ_OOB_INDEX_ONLY', + 'SQ_OOB_NUM_RECORDS_0', 'SQ_OOB_SELECT', 'SQ_PERF_SEL', + 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_BUSY_CYCLES', + 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', + 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', + 'SQ_PERF_SEL_EXP_BUS0_BUSY', 'SQ_PERF_SEL_EXP_BUS1_BUSY', + 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', + 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_REQS', + 'SQ_PERF_SEL_INSTS_ALL', 'SQ_PERF_SEL_INSTS_BARRIER_LOCK', + 'SQ_PERF_SEL_INSTS_BRANCH', 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', + 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', 'SQ_PERF_SEL_INSTS_DELAY_ALU', + 'SQ_PERF_SEL_INSTS_DELAY_ALU_COISSUE', + 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', 'SQ_PERF_SEL_INSTS_EXP', + 'SQ_PERF_SEL_INSTS_EXP_MRT', 'SQ_PERF_SEL_INSTS_EXP_Z', + 'SQ_PERF_SEL_INSTS_FLAT', 'SQ_PERF_SEL_INSTS_FLAT_ATOMIC', + 'SQ_PERF_SEL_INSTS_FLAT_LOAD', 'SQ_PERF_SEL_INSTS_FLAT_STORE', + 'SQ_PERF_SEL_INSTS_GLOBAL_SCRATCH', 'SQ_PERF_SEL_INSTS_INTERNAL', + 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', + 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', 'SQ_PERF_SEL_INSTS_LOCK', + 'SQ_PERF_SEL_INSTS_NON_VALU_EXEC_SKIPPED', + 'SQ_PERF_SEL_INSTS_SALU', 'SQ_PERF_SEL_INSTS_SALU_CS', + 'SQ_PERF_SEL_INSTS_SALU_FLOAT', 'SQ_PERF_SEL_INSTS_SALU_GS', + 'SQ_PERF_SEL_INSTS_SALU_HS', 'SQ_PERF_SEL_INSTS_SALU_PS', + 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', + 'SQ_PERF_SEL_INSTS_SMEM_CS', 'SQ_PERF_SEL_INSTS_SMEM_GS', + 'SQ_PERF_SEL_INSTS_SMEM_HS', 'SQ_PERF_SEL_INSTS_SMEM_NORM', + 'SQ_PERF_SEL_INSTS_SMEM_PS', 'SQ_PERF_SEL_INSTS_TEX', + 'SQ_PERF_SEL_INSTS_TEX_ATOMIC_NORTN', + 'SQ_PERF_SEL_INSTS_TEX_ATOMIC_RTN', + 'SQ_PERF_SEL_INSTS_TEX_BLOCK_LOAD', + 'SQ_PERF_SEL_INSTS_TEX_BLOCK_STORE', 'SQ_PERF_SEL_INSTS_TEX_LOAD', + 'SQ_PERF_SEL_INSTS_TEX_SAMPLE', 'SQ_PERF_SEL_INSTS_TEX_STORE', + 'SQ_PERF_SEL_INSTS_VALU', 'SQ_PERF_SEL_INSTS_VALU_1_PASS', + 'SQ_PERF_SEL_INSTS_VALU_2_PASS', 'SQ_PERF_SEL_INSTS_VALU_4_PASS', + 'SQ_PERF_SEL_INSTS_VALU_COISSUE', 'SQ_PERF_SEL_INSTS_VALU_DP', + 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', + 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', + 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_16BIT', + 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_32BIT', + 'SQ_PERF_SEL_INSTS_VALU_TRANS', 'SQ_PERF_SEL_INSTS_VALU_TRANS32', + 'SQ_PERF_SEL_INSTS_VALU_VINTERP', 'SQ_PERF_SEL_INSTS_VEC32', + 'SQ_PERF_SEL_INSTS_VEC32_FLAT', + 'SQ_PERF_SEL_INSTS_VEC32_FLAT_ATOMIC', + 'SQ_PERF_SEL_INSTS_VEC32_FLAT_LOAD', + 'SQ_PERF_SEL_INSTS_VEC32_FLAT_STORE', + 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH', + 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_ATOMIC', + 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_LOAD', + 'SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_STORE', + 'SQ_PERF_SEL_INSTS_VEC32_LDS', + 'SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_NORTN', + 'SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_RTN', + 'SQ_PERF_SEL_INSTS_VEC32_LDS_LOAD', + 'SQ_PERF_SEL_INSTS_VEC32_LDS_OTHER', + 'SQ_PERF_SEL_INSTS_VEC32_LDS_PARAM_LOAD', + 'SQ_PERF_SEL_INSTS_VEC32_LDS_STORE', + 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS', + 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_LOAD', + 'SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_STORE', + 'SQ_PERF_SEL_INSTS_VEC32_TEX', + 'SQ_PERF_SEL_INSTS_VEC32_TEX_ATOMIC', + 'SQ_PERF_SEL_INSTS_VEC32_TEX_CS', + 'SQ_PERF_SEL_INSTS_VEC32_TEX_GS', + 'SQ_PERF_SEL_INSTS_VEC32_TEX_HS', + 'SQ_PERF_SEL_INSTS_VEC32_TEX_LOAD', + 'SQ_PERF_SEL_INSTS_VEC32_TEX_PS', + 'SQ_PERF_SEL_INSTS_VEC32_TEX_SAMPLE', + 'SQ_PERF_SEL_INSTS_VEC32_TEX_STORE', + 'SQ_PERF_SEL_INSTS_VEC32_VALU', 'SQ_PERF_SEL_INSTS_VEC32_VALU_CS', + 'SQ_PERF_SEL_INSTS_VEC32_VALU_GS', + 'SQ_PERF_SEL_INSTS_VEC32_VALU_HS', + 'SQ_PERF_SEL_INSTS_VEC32_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INSTS_VEC32_VALU_PS', + 'SQ_PERF_SEL_INSTS_VEC32_VALU_TRANS32', + 'SQ_PERF_SEL_INSTS_VEC32_VALU_VINTERP', + 'SQ_PERF_SEL_INSTS_VEC32_VALU_WMMA', + 'SQ_PERF_SEL_INSTS_VGPR_ALLOC', + 'SQ_PERF_SEL_INSTS_VGPR_ALLOC_FAIL', 'SQ_PERF_SEL_INSTS_WAKEUP', + 'SQ_PERF_SEL_INSTS_WMMA_LOAD', 'SQ_PERF_SEL_INST_BARRIER_STALL', + 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', 'SQ_PERF_SEL_INST_CYCLES_EXP', + 'SQ_PERF_SEL_INST_CYCLES_FLAT', 'SQ_PERF_SEL_INST_CYCLES_LDS', + 'SQ_PERF_SEL_INST_CYCLES_TEX', 'SQ_PERF_SEL_INST_CYCLES_VALU', + 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', + 'SQ_PERF_SEL_INST_CYCLES_VMEM', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_ATOMIC', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', + 'SQ_PERF_SEL_INST_ISSUE_ALL_STALL', + 'SQ_PERF_SEL_INST_ISSUE_EXP_STALL', + 'SQ_PERF_SEL_INST_ISSUE_LDS_STALL', + 'SQ_PERF_SEL_INST_ISSUE_SALU_STALL', + 'SQ_PERF_SEL_INST_ISSUE_SMEM_STALL', + 'SQ_PERF_SEL_INST_ISSUE_TEX_STALL', + 'SQ_PERF_SEL_INST_ISSUE_VALU_STALL', 'SQ_PERF_SEL_INST_LEVEL_EXP', + 'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM', + 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', + 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', + 'SQ_PERF_SEL_INST_WAITCNT_STALL', 'SQ_PERF_SEL_IS_CACHE_DUP_MISS', + 'SQ_PERF_SEL_IS_CACHE_MISS', 'SQ_PERF_SEL_IS_CACHE_REQ', + 'SQ_PERF_SEL_ITEMS', 'SQ_PERF_SEL_ITEMS_MAX_VALU', + 'SQ_PERF_SEL_ITEMS_VALU', 'SQ_PERF_SEL_ITEM_CYCLES_VALU', + 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', + 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_LEVEL_WAVES', 'SQ_PERF_SEL_MSG', + 'SQ_PERF_SEL_MSG_BUS_BUSY', 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', + 'SQ_PERF_SEL_MSG_INTERRUPT', 'SQ_PERF_SEL_NONE', + 'SQ_PERF_SEL_NONE2', 'SQ_PERF_SEL_OVERFLOW_PREV', + 'SQ_PERF_SEL_PS_QUADS', 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', + 'SQ_PERF_SEL_SALU_PIPE_STALL', 'SQ_PERF_SEL_SALU_SGATHER_STALL', + 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', + 'SQ_PERF_SEL_SP_CONST_CYCLES', + 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', 'SQ_PERF_SEL_USER0', + 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', + 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', + 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', + 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', + 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', + 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', + 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', + 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', + 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', + 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', + 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', + 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', + 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', + 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', + 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', + 'SQ_PERF_SEL_VALU_RETURN_SDST', + 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', + 'SQ_PERF_SEL_VALU_SGATHER_STALL', + 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_VALU_STARVE', 'SQ_PERF_SEL_VEC32_INSTS_EXP', + 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', + 'SQ_PERF_SEL_VMEM_BUS_STALL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', + 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', + 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', + 'SQ_PERF_SEL_WAIT_ANY', 'SQ_PERF_SEL_WAIT_BARRIER', + 'SQ_PERF_SEL_WAIT_CNT_ANY', 'SQ_PERF_SEL_WAIT_CNT_DS', + 'SQ_PERF_SEL_WAIT_CNT_EXP', 'SQ_PERF_SEL_WAIT_CNT_KM', + 'SQ_PERF_SEL_WAIT_CNT_LOAD', 'SQ_PERF_SEL_WAIT_CNT_SAMPLE', + 'SQ_PERF_SEL_WAIT_CNT_STORE', 'SQ_PERF_SEL_WAIT_DELAY_ALU', + 'SQ_PERF_SEL_WAIT_DEPCTR', 'SQ_PERF_SEL_WAIT_EXP_ALLOC', + 'SQ_PERF_SEL_WAIT_IFETCH', 'SQ_PERF_SEL_WAIT_INST_ANY', + 'SQ_PERF_SEL_WAIT_OTHER', 'SQ_PERF_SEL_WAIT_SLEEP', + 'SQ_PERF_SEL_WAIT_TTRACE', 'SQ_PERF_SEL_WAVE32_INSTS', + 'SQ_PERF_SEL_WAVE32_ITEMS', 'SQ_PERF_SEL_WAVE64_HALF_SKIP', + 'SQ_PERF_SEL_WAVE64_INSTS', 'SQ_PERF_SEL_WAVE64_ITEMS', + 'SQ_PERF_SEL_WAVES', 'SQ_PERF_SEL_WAVES_32', + 'SQ_PERF_SEL_WAVES_64', 'SQ_PERF_SEL_WAVES_EQ_32', + 'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', + 'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32', + 'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64', + 'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED', + 'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY', + 'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE', + 'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY', + 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1', + 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE', + 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2', + 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D', + 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY', + 'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY', + 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0', + 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3', + 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6', + 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SCRATCH', + 'SQ_SEL_0', 'SQ_SEL_1', 'SQ_SEL_N_BC_1', 'SQ_SEL_RESERVED_1', + 'SQ_SEL_W', 'SQ_SEL_X', 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', + 'SQ_TEX_ANISO_RATIO', 'SQ_TEX_ANISO_RATIO_1', + 'SQ_TEX_ANISO_RATIO_16', 'SQ_TEX_ANISO_RATIO_2', + 'SQ_TEX_ANISO_RATIO_4', 'SQ_TEX_ANISO_RATIO_8', + 'SQ_TEX_BORDER_COLOR', 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', + 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', + 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 'SQ_TEX_DEPTH_COMPARE_GREATER', + 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', + 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', + 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', + 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', + 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', + 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', + 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', + 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', + 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', + 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', + 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', 'SQ_WATCH_MODES', + 'SQ_WATCH_MODE_ALL', 'SQ_WATCH_MODE_ATOMIC', + 'SQ_WATCH_MODE_NONREAD', 'SQ_WATCH_MODE_READ', + 'SQ_WAVE_FWD_PROG_INTERVAL', 'SQ_WAVE_FWD_PROG_INTERVAL_1024', + 'SQ_WAVE_FWD_PROG_INTERVAL_256', 'SQ_WAVE_FWD_PROG_INTERVAL_4096', + 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', 'SQ_WAVE_IB_DEP_HOLD_CNT_SIZE', + 'SQ_WAVE_IB_DEP_LDS_DIR_SIZE', 'SQ_WAVE_IB_DEP_SA_EXEC_SIZE', + 'SQ_WAVE_IB_DEP_SA_M0_SIZE', 'SQ_WAVE_IB_DEP_SA_SDST_SIZE', + 'SQ_WAVE_IB_DEP_VA_EXEC_SIZE', 'SQ_WAVE_IB_DEP_VA_SDST_SIZE', + 'SQ_WAVE_IB_DEP_VA_SSRC_SIZE', 'SQ_WAVE_IB_DEP_VA_VCC_SIZE', + 'SQ_WAVE_IB_DEP_VA_VDST_SIZE', 'SQ_WAVE_IB_DEP_VM_VSRC_SIZE', + 'SQ_WAVE_SCHED_MODES', + 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST_VM_VSRC', + 'SQ_WAVE_SCHED_MODE_EXPERT', 'SQ_WAVE_SCHED_MODE_NORMAL', + 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', 'SQ_WAVE_TYPE_GS', + 'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_PS', 'SQ_WAVE_TYPE_PS0', + 'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_PS2', 'SQ_WAVE_TYPE_PS3', + 'SQ_WAVE_TYPE_RSVD0', 'SQ_WAVE_TYPE_RSVD1', 'SQ_WAVE_TYPE_RSVD2', + 'STALL', 'STENCIL_ADD_CLAMP', 'STENCIL_ADD_WRAP', 'STENCIL_AND', + 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', + 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', + 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', + 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', + 'STREAM_0_SYNCHRONIZATION', + 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_10_SYNCHRONIZATION', + 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION', + 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION', + 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION', + 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION', + 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION', + 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_1_SYNCHRONIZATION', + 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_2_SYNCHRONIZATION', + 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_3_SYNCHRONIZATION', + 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_4_SYNCHRONIZATION', + 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_5_SYNCHRONIZATION', + 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_6_SYNCHRONIZATION', + 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION', + 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION', + 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION', + 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'STRM_PERFMON_STATE_RESERVED_3', + 'STRM_PERFMON_STATE_START_COUNTING', + 'STRM_PERFMON_STATE_STOP_COUNTING', 'SURFACE_DCC', + 'SURFACE_DCC_BLOCK_IS_IND_128B', 'SURFACE_DCC_BLOCK_IS_IND_64B', + 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', + 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', 'SURFACE_DCC_IND_128B', + 'SURFACE_DCC_IND_64B', 'SURFACE_DCC_IND_BLK', + 'SURFACE_DCC_IS_IND_128B', 'SURFACE_DCC_IS_IND_64B', + 'SURFACE_DCC_IS_NOT_IND_128B', 'SURFACE_DCC_IS_NOT_IND_64B', + 'SURFACE_FLIP_AWAY_INT_LEVEL', 'SURFACE_FLIP_AWAY_INT_PULSE', + 'SURFACE_FLIP_AWAY_INT_TYPE', 'SURFACE_FLIP_EXEC_DEBUG_MODE', + 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', + 'SURFACE_FLIP_EXEC_NORMAL_MODE', 'SURFACE_FLIP_INT_LEVEL', + 'SURFACE_FLIP_INT_PULSE', 'SURFACE_FLIP_INT_TYPE', + 'SURFACE_FLIP_IN_STEREOSYNC', 'SURFACE_FLIP_IN_STEREOSYNC_MODE', + 'SURFACE_FLIP_MODE_FOR_STEREOSYNC', + 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', + 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', + 'SURFACE_FLIP_STEREO_SELECT_DISABLE', + 'SURFACE_FLIP_STEREO_SELECT_DISABLED', + 'SURFACE_FLIP_STEREO_SELECT_ENABLED', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', + 'SURFACE_FLIP_TYPE', 'SURFACE_FLIP_VUPDATE_SKIP_NUM', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', 'SURFACE_INUSE_IS_LATCHED', + 'SURFACE_INUSE_IS_NOT_LATCHED', 'SURFACE_INUSE_RAED_NO_LATCH', + 'SURFACE_IS_DCC', 'SURFACE_IS_NOT_DCC', 'SURFACE_IS_NOT_TMZ', + 'SURFACE_IS_TMZ', 'SURFACE_I_FLIP', 'SURFACE_PIXEL_FORMAT', + 'SURFACE_TMZ', 'SURFACE_UPDATE_IS_LOCKED', + 'SURFACE_UPDATE_IS_UNLOCKED', 'SURFACE_UPDATE_LOCK', + 'SURFACE_V_FLIP', 'SU_PERFCNT_SEL', 'SWATH_HEIGHT', + 'SWATH_HEIGHT_16L', 'SWATH_HEIGHT_1L', 'SWATH_HEIGHT_2L', + 'SWATH_HEIGHT_4L', 'SWATH_HEIGHT_8L', 'SX_BLEND_OPT', + 'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT', + 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK', + 'SX_PERF_SEL_CLOCK_DROP_STALL', 'SX_PERF_SEL_COL_BUSY', + 'SX_PERF_SEL_DB0_4X2_DISCARD', 'SX_PERF_SEL_DB0_END_OF_WAVE', + 'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', + 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', + 'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB0_SIZE', + 'SX_PERF_SEL_DB1_4X2_DISCARD', 'SX_PERF_SEL_DB1_END_OF_WAVE', + 'SX_PERF_SEL_DB1_HALF_QUADS', 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', + 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', + 'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB1_SIZE', + 'SX_PERF_SEL_DB2_4X2_DISCARD', 'SX_PERF_SEL_DB2_END_OF_WAVE', + 'SX_PERF_SEL_DB2_HALF_QUADS', 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', + 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', + 'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB2_SIZE', + 'SX_PERF_SEL_DB3_4X2_DISCARD', 'SX_PERF_SEL_DB3_END_OF_WAVE', + 'SX_PERF_SEL_DB3_HALF_QUADS', 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', + 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', + 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_DB3_SIZE', + 'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2', + 'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4', + 'SX_PERF_SEL_GATE_EN5', 'SX_PERF_SEL_GATE_EN6', + 'SX_PERF_SEL_GATE_EN7', 'SX_PERF_SEL_GATE_EN8', + 'SX_PERF_SEL_IDX_BUSY', 'SX_PERF_SEL_IDX_IDLE_CYCLES', + 'SX_PERF_SEL_IDX_REQ', 'SX_PERF_SEL_IDX_REQ_LATENCY', + 'SX_PERF_SEL_IDX_RET', 'SX_PERF_SEL_IDX_SCBD_STALL', + 'SX_PERF_SEL_IDX_STALL_CYCLES', 'SX_PERF_SEL_PA_IDLE_CYCLES', + 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_POS_BANK_CONF', + 'SX_PERF_SEL_PA_REQ', 'SX_PERF_SEL_PA_REQ_LATENCY', + 'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_POS_SCBD_STALL', + 'SX_PERF_SEL_SH_COLOR_STALL', 'SX_PERF_SEL_SH_COLOR_STARVE', + 'SX_PERF_SEL_SH_IDX_STARVE', 'SX_PERF_SEL_SH_POS_STALL', + 'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11', + 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', + 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', + 'SX_RT_EXPORT_2_10_10_10_6E4', 'SX_RT_EXPORT_2_10_10_10_7E3', + 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', + 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', + 'SX_RT_EXPORT_9_9_9_E5', 'SX_RT_EXPORT_NO_CONVERSION', + 'SYMCLK_FE_SRC', 'SYMCLK_FE_SRC_RESERVED', + 'SYMCLK_FE_SRC_UNIPHYA', 'SYMCLK_FE_SRC_UNIPHYB', + 'SYMCLK_FE_SRC_UNIPHYC', 'SYMCLK_FE_SRC_UNIPHYD', 'ScMap', + 'ScUncertaintyRegionMode', 'ScUncertaintyRegionMult', 'ScXsel', + 'ScYsel', 'SeMap', 'SePairMap', 'SePairXsel', 'SePairYsel', + 'SeXsel', 'SeYsel', 'StencilOp', 'TA_PERFCOUNT_SEL', + 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', + 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 'TA_PERF_SEL_addresser_stalled_cycles', + 'TA_PERF_SEL_aligner_busy', + 'TA_PERF_SEL_aligner_clk_valid_cycles', + 'TA_PERF_SEL_aligner_cycles', 'TA_PERF_SEL_aniso_10_cycle_quads', + 'TA_PERF_SEL_aniso_12_cycle_quads', + 'TA_PERF_SEL_aniso_14_cycle_quads', + 'TA_PERF_SEL_aniso_16_cycle_quads', + 'TA_PERF_SEL_aniso_1_cycle_quads', + 'TA_PERF_SEL_aniso_2_cycle_quads', + 'TA_PERF_SEL_aniso_4_cycle_quads', + 'TA_PERF_SEL_aniso_6_cycle_quads', + 'TA_PERF_SEL_aniso_8_cycle_quads', + 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 'TA_PERF_SEL_aniso_stalled_cycles', + 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', + 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', + 'TA_PERF_SEL_atomic_write_data_input_cycles', + 'TA_PERF_SEL_atomic_write_data_output_cycles', + 'TA_PERF_SEL_bf_busy', + 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', + 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', + 'TA_PERF_SEL_buffer_atomic_wavefronts', + 'TA_PERF_SEL_buffer_flat_1_op_burst', + 'TA_PERF_SEL_buffer_flat_2to3_op_burst', + 'TA_PERF_SEL_buffer_flat_4to31_op_burst', + 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', + 'TA_PERF_SEL_buffer_flat_ge32_op_burst', + 'TA_PERF_SEL_buffer_has_index_instructions', + 'TA_PERF_SEL_buffer_has_offset_instructions', + 'TA_PERF_SEL_buffer_load_wavefronts', + 'TA_PERF_SEL_buffer_store_wavefronts', + 'TA_PERF_SEL_buffer_total_cycles', + 'TA_PERF_SEL_buffer_wavefronts', + 'TA_PERF_SEL_color_1_cycle_quads', + 'TA_PERF_SEL_color_2_cycle_quads', + 'TA_PERF_SEL_color_3_cycle_quads', + 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 'TA_PERF_SEL_deriv_stalled_cycles', + 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', + 'TA_PERF_SEL_flat_2_address_input_vgpr_instructions', + 'TA_PERF_SEL_flat_atomic_wavefronts', + 'TA_PERF_SEL_flat_load_wavefronts', + 'TA_PERF_SEL_flat_store_wavefronts', + 'TA_PERF_SEL_flat_total_cycles', 'TA_PERF_SEL_flat_wavefronts', + 'TA_PERF_SEL_gradient_busy', + 'TA_PERF_SEL_gradient_clk_valid_cycles', + 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', + 'TA_PERF_SEL_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_ibubble_16to31_cycle_burst', + 'TA_PERF_SEL_ibubble_1_cycle_burst', + 'TA_PERF_SEL_ibubble_2to3_cycle_burst', + 'TA_PERF_SEL_ibubble_32to63_cycle_burst', + 'TA_PERF_SEL_ibubble_4to15_cycle_burst', + 'TA_PERF_SEL_ibubble_ge64_cycle_burst', + 'TA_PERF_SEL_image_atomic_wavefronts', + 'TA_PERF_SEL_image_linked_1_op_burst', + 'TA_PERF_SEL_image_linked_2to3_op_burst', + 'TA_PERF_SEL_image_linked_4to7_op_burst', + 'TA_PERF_SEL_image_linked_ge8_op_burst', + 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_1_op_burst', + 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_2to3_op_burst', + 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_4to31_op_burst', + 'TA_PERF_SEL_image_nosampler_ge32_op_burst', + 'TA_PERF_SEL_image_nosampler_has_q_instructions', + 'TA_PERF_SEL_image_nosampler_has_r_instructions', + 'TA_PERF_SEL_image_nosampler_has_t_instructions', + 'TA_PERF_SEL_image_nosampler_total_cycles', + 'TA_PERF_SEL_image_read_wavefronts', + 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_1_op_burst', + 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_2to3_op_burst', + 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_4to7_op_burst', + 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_ge8_op_burst', + 'TA_PERF_SEL_image_sampler_has_bias_instructions', + 'TA_PERF_SEL_image_sampler_has_dr_instructions', + 'TA_PERF_SEL_image_sampler_has_ds_instructions', + 'TA_PERF_SEL_image_sampler_has_dt_instructions', + 'TA_PERF_SEL_image_sampler_has_offset_instructions', + 'TA_PERF_SEL_image_sampler_has_q_instructions', + 'TA_PERF_SEL_image_sampler_has_r_instructions', + 'TA_PERF_SEL_image_sampler_has_reference_instructions', + 'TA_PERF_SEL_image_sampler_has_t_instructions', + 'TA_PERF_SEL_image_sampler_total_cycles', + 'TA_PERF_SEL_image_sampler_wavefronts', + 'TA_PERF_SEL_image_store_wavefronts', + 'TA_PERF_SEL_image_wavefronts', 'TA_PERF_SEL_in_addr_cycles', + 'TA_PERF_SEL_in_busy', 'TA_PERF_SEL_in_cfifo_busy', + 'TA_PERF_SEL_in_data_cycles', 'TA_PERF_SEL_in_fifos_busy', + 'TA_PERF_SEL_in_qfifo_busy', 'TA_PERF_SEL_in_rfifo_busy', + 'TA_PERF_SEL_in_waiting_on_req_cycles', + 'TA_PERF_SEL_in_wfifo_busy', + 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', 'TA_PERF_SEL_lod_busy', + 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_quads', + 'TA_PERF_SEL_mip_2_cycle_quads', + 'TA_PERF_SEL_mipmap_invalid_samples', + 'TA_PERF_SEL_mipmap_lod_0_samples', + 'TA_PERF_SEL_mipmap_lod_10_samples', + 'TA_PERF_SEL_mipmap_lod_11_samples', + 'TA_PERF_SEL_mipmap_lod_12_samples', + 'TA_PERF_SEL_mipmap_lod_13_samples', + 'TA_PERF_SEL_mipmap_lod_14_samples', + 'TA_PERF_SEL_mipmap_lod_15_samples', + 'TA_PERF_SEL_mipmap_lod_16_samples', + 'TA_PERF_SEL_mipmap_lod_1_samples', + 'TA_PERF_SEL_mipmap_lod_2_samples', + 'TA_PERF_SEL_mipmap_lod_3_samples', + 'TA_PERF_SEL_mipmap_lod_4_samples', + 'TA_PERF_SEL_mipmap_lod_5_samples', + 'TA_PERF_SEL_mipmap_lod_6_samples', + 'TA_PERF_SEL_mipmap_lod_7_samples', + 'TA_PERF_SEL_mipmap_lod_8_samples', + 'TA_PERF_SEL_mipmap_lod_9_samples', + 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_nonsampler_clk_valid_cycles', 'TA_PERF_SEL_ns_busy', + 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', + 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', + 'TA_PERF_SEL_num_unlit_nodes_ta_opt', + 'TA_PERF_SEL_point_sampled_quads', + 'TA_PERF_SEL_register_clk_valid_cycles', + 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', + 'TA_PERF_SEL_sampler_clk_valid_cycles', + 'TA_PERF_SEL_sampler_op_quads', 'TA_PERF_SEL_smp_busy_ns_idle', + 'TA_PERF_SEL_smp_idle_ns_busy', + 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', + 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', + 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', + 'TA_PERF_SEL_store_has_w_instructions', + 'TA_PERF_SEL_store_has_x_instructions', + 'TA_PERF_SEL_store_has_y_instructions', + 'TA_PERF_SEL_store_has_z_instructions', + 'TA_PERF_SEL_store_write_data_input_cycles', + 'TA_PERF_SEL_store_write_data_output_cycles', + 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', + 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', + 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', + 'TA_PERF_SEL_ta_busy', 'TA_PERF_SEL_tcreq_clk_valid_cycles', + 'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vmemcmd_cycles', + 'TA_PERF_SEL_vmemreq_cycles', 'TA_PERF_SEL_vol_1_cycle_quads', + 'TA_PERF_SEL_vol_2_cycle_quads', 'TA_PERF_SEL_walker_cycles', + 'TA_PERF_SEL_write_1_op_burst', 'TA_PERF_SEL_write_2to3_op_burst', + 'TA_PERF_SEL_write_4to31_op_burst', + 'TA_PERF_SEL_write_data_clk_valid_cycles', + 'TA_PERF_SEL_write_ge32_op_burst', 'TA_PERF_SEL_write_path_busy', + 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', + 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', + 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', + 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', + 'TA_TC_REQ_MODES', 'TA_TC_REQ_MODE_BORDER', 'TA_TC_REQ_MODE_BYTE', + 'TA_TC_REQ_MODE_BYTE_NV', 'TA_TC_REQ_MODE_DWORD', + 'TA_TC_REQ_MODE_NORMAL', 'TA_TC_REQ_MODE_TEX0', + 'TA_TC_REQ_MODE_TEX1', 'TA_TC_REQ_MODE_TEX2', 'TCC_MTYPE', + 'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT', + 'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT', + 'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES', + 'TCP_CACHE_STORE_POLICY_WT_EVICT', + 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_COMPRESSION_BYPASS', + 'TCP_COMPRESSION_BYPASS_DIS', 'TCP_COMPRESSION_BYPASS_EN', + 'TCP_COMPRESSION_OVERRIDE', 'TCP_COMPRESSION_OVERRIDE_DIS', + 'TCP_COMPRESSION_OVERRIDE_EN', 'TCP_OPCODE_ATOMIC', + 'TCP_OPCODE_ATOMIC_CMPSWAP', 'TCP_OPCODE_GATHERH', + 'TCP_OPCODE_INV', 'TCP_OPCODE_LOAD', 'TCP_OPCODE_READ', + 'TCP_OPCODE_SAMPLER', 'TCP_OPCODE_TYPE', 'TCP_OPCODE_WRITE', + 'TCP_PERFCOUNT_SELECT', 'TCP_PERF_SEL_ALLOC_STALL', + 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', + 'TCP_PERF_SEL_BURST_BIN_READHIT_0', + 'TCP_PERF_SEL_BURST_BIN_READHIT_1', + 'TCP_PERF_SEL_BURST_BIN_READHIT_2to4', + 'TCP_PERF_SEL_BURST_BIN_READHIT_5to8', + 'TCP_PERF_SEL_BURST_BIN_READHIT_9to16', + 'TCP_PERF_SEL_BURST_BIN_READHIT_gt16', + 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_0', + 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_1to2', + 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_3to4', + 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_5to8', + 'TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_9to16', + 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', + 'TCP_PERF_SEL_DATA_FIFO_STALL', 'TCP_PERF_SEL_GATE_EN1', + 'TCP_PERF_SEL_GATE_EN2', 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', + 'TCP_PERF_SEL_GL1_PENDING_STALL', 'TCP_PERF_SEL_GL1_READ_LATENCY', + 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', 'TCP_PERF_SEL_GL1_REQ_LU', + 'TCP_PERF_SEL_GL1_REQ_READ', 'TCP_PERF_SEL_GL1_REQ_READ_128B', + 'TCP_PERF_SEL_GL1_REQ_READ_64B', 'TCP_PERF_SEL_GL1_REQ_WRITE', + 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', + 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', + 'TCP_PERF_SEL_GL1_WRITE_LATENCY', 'TCP_PERF_SEL_LFIFO_STALL', + 'TCP_PERF_SEL_LOD_STALL', 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', + 'TCP_PERF_SEL_POWER_STALL', + 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', + 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', 'TCP_PERF_SEL_REQ', + 'TCP_PERF_SEL_REQ_MISS', 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', + 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', + 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', + 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', 'TCP_PERF_SEL_REQ_NON_READ', + 'TCP_PERF_SEL_REQ_READ', 'TCP_PERF_SEL_REQ_READ_HIT_LRU', + 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', + 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', + 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', + 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', + 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', + 'TCP_PERF_SEL_REQ_TAG_MATCH_AND_LU_INVALIDATE', + 'TCP_PERF_SEL_REQ_TAG_MATCH_AND_NOT_VALID', + 'TCP_PERF_SEL_REQ_WRITE', 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', + 'TCP_PERF_SEL_TAGFAKE_EOW', 'TCP_PERF_SEL_TA_REQ', + 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', + 'TCP_PERF_SEL_TA_REQ_BUFFERNOP', 'TCP_PERF_SEL_TA_REQ_GL0_INV', + 'TCP_PERF_SEL_TA_REQ_READ', 'TCP_PERF_SEL_TA_REQ_STATE_READ', + 'TCP_PERF_SEL_TA_REQ_WRITE', 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', + 'TCP_PERF_SEL_TA_TC_REQ_EN_SUM', 'TCP_PERF_SEL_TCP_LATENCY', + 'TCP_PERF_SEL_TCP_TA_REQ_STALL', + 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', 'TCP_PERF_SEL_TD_TCP_STALL', + 'TCP_PERF_SEL_WRITECOMBINE_ENDCLAUSE', + 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', + 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', 'TCP_WATCH_MODES', + 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', + 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', + 'TCP_WRITE_COMPRESSION_DISABLE', + 'TCP_WRITE_COMPRESSION_DISABLE_DIS', + 'TCP_WRITE_COMPRESSION_DISABLE_EN', 'TC_EA_CID', 'TC_EA_CID_CPF', + 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', 'TC_EA_CID_FMASK', + 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', 'TC_EA_CID_MISC', + 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', + 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', + 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', 'TC_NACKS', + 'TC_NACK_DATA_ERROR', 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', + 'TC_NACK_PROTECTION_FAULT', 'TC_OP', 'TC_OP_ATOMIC_ADD_32', + 'TC_OP_ATOMIC_ADD_64', 'TC_OP_ATOMIC_ADD_RTN_32', + 'TC_OP_ATOMIC_ADD_RTN_64', 'TC_OP_ATOMIC_AND_32', + 'TC_OP_ATOMIC_AND_64', 'TC_OP_ATOMIC_AND_RTN_32', + 'TC_OP_ATOMIC_AND_RTN_64', 'TC_OP_ATOMIC_CMPSWAP_32', + 'TC_OP_ATOMIC_CMPSWAP_64', 'TC_OP_ATOMIC_CMPSWAP_RTN_32', + 'TC_OP_ATOMIC_CMPSWAP_RTN_64', 'TC_OP_ATOMIC_DEC_32', + 'TC_OP_ATOMIC_DEC_64', 'TC_OP_ATOMIC_DEC_RTN_32', + 'TC_OP_ATOMIC_DEC_RTN_64', 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', + 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', + 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', + 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', + 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', + 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', + 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', + 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', + 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', + 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', + 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', + 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', + 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', + 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', + 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', + 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', + 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', + 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', + 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', + 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', + 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', + 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', + 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', + 'TC_OP_READ', 'TC_OP_RESERVED_FADD_32', + 'TC_OP_RESERVED_FADD_RTN_32', 'TC_OP_RESERVED_FOP_32_0', + 'TC_OP_RESERVED_FOP_32_2', 'TC_OP_RESERVED_FOP_64_0', + 'TC_OP_RESERVED_FOP_64_1', 'TC_OP_RESERVED_FOP_64_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_2', + 'TC_OP_RESERVED_FOP_RTN_64_0', 'TC_OP_RESERVED_FOP_RTN_64_1', + 'TC_OP_RESERVED_FOP_RTN_64_2', 'TC_OP_RESERVED_NON_FLOAT_32_1', + 'TC_OP_RESERVED_NON_FLOAT_32_2', 'TC_OP_RESERVED_NON_FLOAT_32_3', + 'TC_OP_RESERVED_NON_FLOAT_32_4', 'TC_OP_RESERVED_NON_FLOAT_64_1', + 'TC_OP_RESERVED_NON_FLOAT_64_2', 'TC_OP_RESERVED_NON_FLOAT_64_3', + 'TC_OP_RESERVED_NON_FLOAT_64_4', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', + 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', + 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', + 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', + 'TD_PERF_SEL_2x_sampler_op_with_1_unlit_quad', + 'TD_PERF_SEL_2x_sampler_op_with_both_quads_unlit', + 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', + 'TD_PERF_SEL_blend_prt_with_prt_default_0', + 'TD_PERF_SEL_box_non_opaque_culled', + 'TD_PERF_SEL_box_opaque_culled', + 'TD_PERF_SEL_box_with_procedural_children_only_culled', + 'TD_PERF_SEL_box_with_triangle_children_only_culled', + 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', + 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', + 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', + 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', + 'TD_PERF_SEL_burst_bin_gather_1', + 'TD_PERF_SEL_burst_bin_gather_2to8', + 'TD_PERF_SEL_burst_bin_gather_9to16', + 'TD_PERF_SEL_burst_bin_gather_gt16', + 'TD_PERF_SEL_burst_bin_nofilter_1', + 'TD_PERF_SEL_burst_bin_nofilter_2to4', + 'TD_PERF_SEL_burst_bin_nofilter_5to7', + 'TD_PERF_SEL_burst_bin_nofilter_8to16', + 'TD_PERF_SEL_burst_bin_nofilter_gt16', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', + 'TD_PERF_SEL_burst_bin_sampler_1', + 'TD_PERF_SEL_burst_bin_sampler_2to8', + 'TD_PERF_SEL_burst_bin_sampler_9to16', + 'TD_PERF_SEL_burst_bin_sampler_gt16', + 'TD_PERF_SEL_bypassLerp_instr', + 'TD_PERF_SEL_core_state_ram_max_cnt', + 'TD_PERF_SEL_core_state_rams_read', 'TD_PERF_SEL_d16_en_instr', + 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', + 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', + 'TD_PERF_SEL_done_scoreboard_is_full', + 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', + 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', + 'TD_PERF_SEL_done_scoreboard_not_empty', + 'TD_PERF_SEL_four_comp_return_instr', + 'TD_PERF_SEL_gather4_2x_instr', 'TD_PERF_SEL_gather4_instr', + 'TD_PERF_SEL_gather4h_2x_instr', 'TD_PERF_SEL_gather4h_instr', + 'TD_PERF_SEL_getlod_2x_instr', 'TD_PERF_SEL_getlod_instr', + 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', + 'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_input_state_fifo_full', + 'TD_PERF_SEL_instance_mask_culled', + 'TD_PERF_SEL_instruction_dest_is_lds', 'TD_PERF_SEL_lds_stall', + 'TD_PERF_SEL_load_instr', 'TD_PERF_SEL_lod_warn_from_ta', + 'TD_PERF_SEL_min_max_filter_instr', 'TD_PERF_SEL_mixmode_instr', + 'TD_PERF_SEL_mixmode_resource', 'TD_PERF_SEL_msaa_load_instr', + 'TD_PERF_SEL_nofilter_busy', + 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', + 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', + 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', + 'TD_PERF_SEL_nofilter_d16_sclk_en', + 'TD_PERF_SEL_nofilter_d32_sclk_en', + 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', + 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', + 'TD_PERF_SEL_nofilter_formatters_turned_on', + 'TD_PERF_SEL_nofilter_insert_extra_comps', + 'TD_PERF_SEL_nofilter_pkr_full', + 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', + 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', + 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', + 'TD_PERF_SEL_nofilter_sclk_en', + 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', + 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', 'TD_PERF_SEL_none', + 'TD_PERF_SEL_one_comp_return_instr', + 'TD_PERF_SEL_opaque_black_border', + 'TD_PERF_SEL_out_of_order_instr', + 'TD_PERF_SEL_preempting_nofilter_max_cnt', + 'TD_PERF_SEL_prt_ack_instr', 'TD_PERF_SEL_ps_load_instr', + 'TD_PERF_SEL_reference_data_rams_read', + 'TD_PERF_SEL_resmap_2x_instr', 'TD_PERF_SEL_resmap_instr', + 'TD_PERF_SEL_resmap_with_aniso_filtering', + 'TD_PERF_SEL_resmap_with_cubemap_corner', + 'TD_PERF_SEL_resmap_with_no_more_filtering', + 'TD_PERF_SEL_resmap_with_volume_filtering', + 'TD_PERF_SEL_sample_2x_instr', 'TD_PERF_SEL_sample_c_instr', + 'TD_PERF_SEL_sample_instr', 'TD_PERF_SEL_sampler_accum_sclk_en', + 'TD_PERF_SEL_sampler_bilerp_sclk_en', + 'TD_PERF_SEL_sampler_bypass_sclk_en', + 'TD_PERF_SEL_sampler_core_sclk_en', + 'TD_PERF_SEL_sampler_format_flt_sclk_en', + 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', + 'TD_PERF_SEL_sampler_lerp0_active', + 'TD_PERF_SEL_sampler_lerp1_active', + 'TD_PERF_SEL_sampler_lerp2_active', + 'TD_PERF_SEL_sampler_lerp3_active', + 'TD_PERF_SEL_sampler_lerp4_active', + 'TD_PERF_SEL_sampler_lerp5_active', + 'TD_PERF_SEL_sampler_lerp6_active', + 'TD_PERF_SEL_sampler_lerp7_active', + 'TD_PERF_SEL_sampler_lerp_busy', + 'TD_PERF_SEL_sampler_minmax_sclk_en', + 'TD_PERF_SEL_sampler_out_busy', 'TD_PERF_SEL_sampler_out_sclk_en', + 'TD_PERF_SEL_sampler_pkr_full', + 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', + 'TD_PERF_SEL_sampler_preformatter_sclk_en', + 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', + 'TD_PERF_SEL_status_packet', 'TD_PERF_SEL_store_preempts_a_load', + 'TD_PERF_SEL_ta_data_stall', + 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', + 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', + 'TD_PERF_SEL_tc_data_stall', 'TD_PERF_SEL_tc_ram_stall', + 'TD_PERF_SEL_tc_td_data_fifo_full', + 'TD_PERF_SEL_tc_td_ram_fifo_full', + 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', 'TD_PERF_SEL_td_busy', + 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', + 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', + 'TD_PERF_SEL_three_comp_return_instr', + 'TD_PERF_SEL_total_num_instr', + 'TD_PERF_SEL_total_num_instr_with_perf_wdw', + 'TD_PERF_SEL_total_num_nofilter_instr', + 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', + 'TD_PERF_SEL_total_num_sampler_instr', + 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', + 'TD_PERF_SEL_tri_proc_node_override_slot0', + 'TD_PERF_SEL_tri_proc_node_override_slot1', + 'TD_PERF_SEL_tri_run_ahs_slot0', 'TD_PERF_SEL_tri_run_ahs_slot1', + 'TD_PERF_SEL_tri_run_intersect_ahs_slot0', + 'TD_PERF_SEL_tri_run_intersect_ahs_slot1', + 'TD_PERF_SEL_triangle_back_facing_culled', + 'TD_PERF_SEL_triangle_front_facing_culled', + 'TD_PERF_SEL_triangle_non_opaque_culled', + 'TD_PERF_SEL_triangle_opaque_culled', + 'TD_PERF_SEL_two_comp_return_instr', + 'TD_PERF_SEL_user_defined_border', + 'TD_PERF_SEL_weight_data_rams_read', 'TD_PERF_SEL_white_border', + 'TD_PERF_SEL_write_ack_instr', 'TESS_ISOLINE', 'TESS_QUAD', + 'TESS_TRIANGLE', 'TEST_CLK_DIV_SEL', 'TEST_CLK_SEL', + 'TEST_CLK_SEL_0', 'TEST_CLK_SEL_1', 'TEST_CLK_SEL_2', + 'TEST_CLK_SEL_3', 'TEST_CLK_SEL_4', 'TEST_CLK_SEL_5', + 'TEST_CLK_SEL_6', 'TEST_CLK_SEL_7', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_D', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', 'TEST_CLOCK_MUX_SELECT_ENUM', + 'TEX_BC_SWIZZLE', 'TEX_BC_Swizzle_WXYZ', 'TEX_BC_Swizzle_WZYX', + 'TEX_BC_Swizzle_XWYZ', 'TEX_BC_Swizzle_XYZW', + 'TEX_BC_Swizzle_YXWZ', 'TEX_BC_Swizzle_ZYXW', + 'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack', + 'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register', + 'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP', + 'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', + 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', + 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', + 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', + 'TEX_Clamp_MirrorOnceHalfToBorder', + 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', + 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', + 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', + 'TEX_DepthCompareFunction_Always', + 'TEX_DepthCompareFunction_Equal', + 'TEX_DepthCompareFunction_Greater', + 'TEX_DepthCompareFunction_GreaterEqual', + 'TEX_DepthCompareFunction_Less', + 'TEX_DepthCompareFunction_LessEqual', + 'TEX_DepthCompareFunction_Never', + 'TEX_DepthCompareFunction_NotEqual', 'TEX_FORMAT_COMP', + 'TEX_FormatComp_RESERVED_3', 'TEX_FormatComp_Signed', + 'TEX_FormatComp_Unsigned', 'TEX_FormatComp_UnsignedBiased', + 'TEX_MAX_ANISO_RATIO', 'TEX_MIP_FILTER', + 'TEX_MaxAnisoRatio_16to1', 'TEX_MaxAnisoRatio_1to1', + 'TEX_MaxAnisoRatio_2to1', 'TEX_MaxAnisoRatio_4to1', + 'TEX_MaxAnisoRatio_8to1', 'TEX_MaxAnisoRatio_RESERVED_5', + 'TEX_MaxAnisoRatio_RESERVED_6', 'TEX_MaxAnisoRatio_RESERVED_7', + 'TEX_MipFilter_Linear', 'TEX_MipFilter_None', + 'TEX_MipFilter_Point', 'TEX_MipFilter_Point_Aniso_Adj', + 'TEX_REQUEST_SIZE', 'TEX_RequestSize_128B', + 'TEX_RequestSize_2X64B', 'TEX_RequestSize_32B', + 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', + 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', + 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', + 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', + 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', + 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', + 'THREAD_TRACE_DRAW', 'THREAD_TRACE_FINISH', 'THREAD_TRACE_MARKER', + 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TMDS_COLOR_FORMAT', + 'TMDS_COLOR_FORMAT_DUAL30BPP', 'TMDS_COLOR_FORMAT_RESERVED', + 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', + 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', + 'TMDS_CTL0_DATA_MODULATION_BIT1', + 'TMDS_CTL0_DATA_MODULATION_BIT2', + 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', + 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', + 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', + 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', + 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', + 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', + 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', + 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', + 'TMDS_CTL1_DATA_MODULATION_BIT0', + 'TMDS_CTL1_DATA_MODULATION_BIT1', + 'TMDS_CTL1_DATA_MODULATION_BIT2', + 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', + 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', + 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', + 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', + 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', + 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', + 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', + 'TMDS_CTL2_DATA_MODULATION_BIT0', + 'TMDS_CTL2_DATA_MODULATION_BIT1', + 'TMDS_CTL2_DATA_MODULATION_BIT2', + 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', + 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', + 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', + 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', + 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', + 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', + 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', + 'TMDS_CTL3_DATA_MODULATION_BIT0', + 'TMDS_CTL3_DATA_MODULATION_BIT1', + 'TMDS_CTL3_DATA_MODULATION_BIT2', + 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', + 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', + 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', + 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', + 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', + 'TMDS_CTL3_PATTERN_OUT_ENABLE', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_DVI_MODE', + 'TMDS_HDMI_MODE', 'TMDS_MUX_SELECT', 'TMDS_MUX_SELECT_B', + 'TMDS_MUX_SELECT_G', 'TMDS_MUX_SELECT_R', + 'TMDS_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', + 'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422', + 'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', + 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', + 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', + 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', + 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', + 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', + 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', + 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', + 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', + 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', 'TRANSERR', + 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', + 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', + 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', + 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', + 'TRISTRIP', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', + 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', + 'TVX_Type_ValidVertexBuffer', 'UCONFIG_SPACE_END', + 'UCONFIG_SPACE_START', 'UNDEF', 'UNSIGNED', 'UTCL0FaultType', + 'UTCL0RequestType', 'UTCL0_TYPE_BYPASS', 'UTCL0_TYPE_NORMAL', + 'UTCL0_TYPE_SHOOTDOWN', 'UTCL0_XNACK_NO_RETRY', 'UTCL0_XNACK_PRT', + 'UTCL0_XNACK_RETRY', 'UTCL0_XNACK_SUCCESS', 'UTCL1FaultType', + 'UTCL1PerfSel', 'UTCL1RequestType', + 'UTCL1_PERF_SEL_ALOG_CACHE_HIT', 'UTCL1_PERF_SEL_ALOG_CACHE_REQ', + 'UTCL1_PERF_SEL_ALOG_INTERRUPT', + 'UTCL1_PERF_SEL_ALOG_INTERRUPT_DROPPED', + 'UTCL1_PERF_SEL_ALOG_STALL_PMM_CREDITS', + 'UTCL1_PERF_SEL_AVG_INV_LATENCY', 'UTCL1_PERF_SEL_BYPASS_REQS', + 'UTCL1_PERF_SEL_CP_INVREQS', 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC0', + 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC1', + 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC2', + 'UTCL1_PERF_SEL_EVICTIONS_NUM_CC3', 'UTCL1_PERF_SEL_HITS', + 'UTCL1_PERF_SEL_HITS_PG_SIZE_1', 'UTCL1_PERF_SEL_HITS_PG_SIZE_2', + 'UTCL1_PERF_SEL_HITS_PG_SIZE_3', 'UTCL1_PERF_SEL_HITS_PG_SIZE_4', + 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', + 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', + 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', + 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', 'UTCL1_PERF_SEL_MISSES', + 'UTCL1_PERF_SEL_NONE', + 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC0', + 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC1', + 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC2', + 'UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC3', + 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC0', + 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC1', + 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC2', + 'UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC3', + 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_16M_32M', + 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_1M_2M', + 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_256K_512K', + 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_2M_4M', + 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_32M_INF', + 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4K_64K', + 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4M_8M', + 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_512K_1M', + 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_64K_256K', + 'UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_8M_16M', + 'UTCL1_PERF_SEL_RANGE_INVREQS', 'UTCL1_PERF_SEL_REQS', + 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_0', + 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_1', + 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_2', + 'UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_3', + 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_0', + 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_1', + 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_2', + 'UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_3', 'UTCL1_PERF_SEL_RTNS', + 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_0', + 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_1', + 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_2', + 'UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_3', + 'UTCL1_PERF_SEL_STALL_MH_FULL', + 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', + 'UTCL1_PERF_SEL_UTCL0_UTCL1_INVACKS', + 'UTCL1_PERF_SEL_UTCL1_UTCL2_INVACKS', 'UTCL1_PERF_SEL_UTCL2_REQS', + 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', + 'UTCL1_PERF_SEL_UTCL2_REQ_SQUASHED_NUM', + 'UTCL1_PERF_SEL_UTCL2_RET_CNT', 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', + 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', + 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', + 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', + 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', + 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', 'UTCL1_TYPE_BYPASS', + 'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN', + 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY', + 'UTCL1_XNACK_SUCCESS', 'VGT_DETECT_ONE', 'VGT_DETECT_ZERO', + 'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE', 'VGT_DI_PRIM_TYPE', + 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', 'VGT_DMA_BUF_RING', + 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', 'VGT_DMA_PTR_UPDATE', + 'VGT_DMA_SWAP_16_BIT', 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', + 'VGT_DMA_SWAP_NONE', 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', + 'VGT_FLUSH', 'VGT_GROUP_CONV_SEL', 'VGT_GRP_AUTO_PRIM', + 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', + 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_SINT_16', + 'VGT_GRP_SINT_32', 'VGT_GRP_UINT_16', 'VGT_GRP_UINT_32', + 'VGT_GS_MODE_TYPE', 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', + 'VGT_INDEX_32', 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', + 'VGT_OUTPATH_GS_BLOCK', 'VGT_OUTPATH_HS_BLOCK', + 'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT', + 'VGT_OUTPATH_TE_GS_BLOCK', 'VGT_OUTPATH_TE_OUTPUT', + 'VGT_OUTPATH_TE_PRIM_GEN', 'VGT_OUTPATH_VTX_REUSE', + 'VGT_OUT_2D_RECT', 'VGT_OUT_DUMMY_1', 'VGT_OUT_DUMMY_2', + 'VGT_OUT_DUMMY_3', 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ', + 'VGT_OUT_PATCH', 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE', + 'VGT_OUT_RECT_V0', 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ', + 'VGT_POLICY_BYPASS', 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM', + 'VGT_RDREQ_POLICY', 'VGT_SPEC_DATA_READ', + 'VGT_SPEC_DATA_READ_AUTO', 'VGT_SPEC_DATA_READ_FORCE_OFF', + 'VGT_SPEC_DATA_READ_FORCE_ON', 'VGT_STAGES_GS_EN', + 'VGT_STAGES_HS_EN', 'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC', + 'VGT_TEMPORAL', 'VGT_TEMPORAL_DISCARD', + 'VGT_TEMPORAL_HIGH_PRIORITY', 'VGT_TEMPORAL_NORMAL', + 'VGT_TEMPORAL_STREAM', 'VGT_TESS_PARTITION', 'VGT_TESS_TOPOLOGY', + 'VGT_TESS_TYPE', 'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE', + 'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK', + 'VMID_SZ', 'VMPG_SIZE', 'VMPG_SIZE_4KB', 'VMPG_SIZE_64KB', + 'VM_GROUP_SIZE', 'VM_GROUP_SIZE_1024B', 'VM_GROUP_SIZE_128B', + 'VM_GROUP_SIZE_2048B', 'VM_GROUP_SIZE_256B', 'VM_GROUP_SIZE_512B', + 'VM_GROUP_SIZE_64B', 'VM_PG_SIZE_128KB', 'VM_PG_SIZE_128MB', + 'VM_PG_SIZE_16KB', 'VM_PG_SIZE_16MB', 'VM_PG_SIZE_1MB', + 'VM_PG_SIZE_256KB', 'VM_PG_SIZE_2MB', 'VM_PG_SIZE_32KB', + 'VM_PG_SIZE_32MB', 'VM_PG_SIZE_4KB', 'VM_PG_SIZE_4MB', + 'VM_PG_SIZE_512KB', 'VM_PG_SIZE_64KB', 'VM_PG_SIZE_64MB', + 'VM_PG_SIZE_8KB', 'VM_PG_SIZE_8MB', + 'VPG_MEM_DISABLE_MEM_PWR_CTRL', 'VPG_MEM_ENABLE_MEM_PWR_CTRL', + 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', 'VPG_MEM_NO_FORCE_REQ', + 'VPG_MEM_PWR_DIS_CTRL', 'VPG_MEM_PWR_FORCE_CTRL', + 'VREADY_AT_OR_AFTER_VSYNC', 'VREADY_BEFORE_VSYNC', + 'VRSCombinerModeSC', 'VRS_SHADING_RATE_16X_SSAA', + 'VRS_SHADING_RATE_1X1', 'VRS_SHADING_RATE_1X2', + 'VRS_SHADING_RATE_2X1', 'VRS_SHADING_RATE_2X2', + 'VRS_SHADING_RATE_2X4', 'VRS_SHADING_RATE_2X_SSAA', + 'VRS_SHADING_RATE_4X2', 'VRS_SHADING_RATE_4X4', + 'VRS_SHADING_RATE_4X_SSAA', 'VRS_SHADING_RATE_8X_SSAA', + 'VRS_SHADING_RATE_UNDEFINED0', 'VRS_SHADING_RATE_UNDEFINED1', + 'VRS_SHADING_RATE_UNDEFINED2', 'VRS_SHADING_RATE_UNDEFINED3', + 'VRS_SHADING_RATE_UNDEFINED4', 'VRSrate', 'VSYNC_CNT_LATCH_MASK', + 'VSYNC_CNT_LATCH_MASK_0', 'VSYNC_CNT_LATCH_MASK_1', + 'VSYNC_CNT_RESET_SEL', 'VSYNC_CNT_RESET_SEL_0', + 'VSYNC_CNT_RESET_SEL_1', 'VS_PARTIAL_FLUSH', 'VTG_SEL_0', + 'VTG_SEL_1', 'VTG_SEL_2', 'VTG_SEL_3', 'VTG_SEL_4', 'VTG_SEL_5', + 'WAIT_SYNC', 'WATERMARK_MODE', 'WD_IA_DRAW_REG_XFER', + 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', + 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', + 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', + 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', + 'WD_IA_DRAW_REG_XFER_GE_CNTL', + 'WD_IA_DRAW_REG_XFER_GE_GS_THROTTLE', + 'WD_IA_DRAW_REG_XFER_GE_PC_ALLOC', + 'WD_IA_DRAW_REG_XFER_GE_STEREO_CNTL', + 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR1', + 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR2', + 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR3', + 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', + 'WD_IA_DRAW_REG_XFER_GE_VRS_RATE', + 'WD_IA_DRAW_REG_XFER_GFX_PIPE_CONTROL', + 'WD_IA_DRAW_REG_XFER_SPI_SHADER_GS_OUT_CONFIG_PS', + 'WD_IA_DRAW_REG_XFER_VGT_DRAW_PAYLOAD_CNTL', + 'WD_IA_DRAW_REG_XFER_VGT_GS_OUT_PRIM_TYPE', + 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', + 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', + 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_EN', + 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_RESET', + 'WD_IA_DRAW_REG_XFER_VGT_PRIMITIVE_TYPE', 'WD_IA_DRAW_SOURCE', + 'WD_IA_DRAW_SOURCE_AUTO', 'WD_IA_DRAW_SOURCE_DMA', + 'WD_IA_DRAW_SOURCE_IMMD', 'WD_IA_DRAW_SOURCE_OPAQ', + 'WD_IA_DRAW_TYPE', 'WD_IA_DRAW_TYPE_DI_MM0', + 'WD_IA_DRAW_TYPE_EVENT_ADDR', 'WD_IA_DRAW_TYPE_EVENT_INIT', + 'WD_IA_DRAW_TYPE_IMM_DATA', 'WD_IA_DRAW_TYPE_INDX_OFF', + 'WD_IA_DRAW_TYPE_MAX_INDX', 'WD_IA_DRAW_TYPE_MIN_INDX', + 'WD_IA_DRAW_TYPE_REG_XFER', 'WRITE_BASE_ONLY', 'WRITE_BOTH', + 'WRITE_COMPRESSION_MODE', 'WritePolicy', 'XNORM', 'XNORM_A', + 'XNORM_B', 'XTAL_REF_CLOCK_SOURCE_SEL', + 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', + 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', + 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'Y10_CbCr1010_420_PLANAR', + 'Y10_CrCb1010_420_PLANAR', 'Y12_CbCr1212_420_PLANAR', + 'Y12_CrCb1212_420_PLANAR', 'Y8_CbCr88_420_PLANAR', + 'Y8_CrCb88_420_PLANAR', 'YCbYCr10101010_422_PACKED', + 'YCbYCr12121212_422_PACKED', 'YCbYCr8888_422_PACKED', + 'YCrCbA16161616_10LSB', 'YCrCbA16161616_10MSB', + 'YCrCbA16161616_12LSB', 'YCrCbA16161616_12MSB', 'YCrCbA8888', + 'YCrYCb10101010_422_PACKED', 'YCrYCb12121212_422_PACKED', + 'YCrYCb8888_422_PACKED', 'Y_G_DATA_ONTO_ALPHA_PORT', + 'Y_G_DATA_ONTO_CB_B_PORT', 'Y_G_DATA_ONTO_CR_R_PORT', + 'Y_G_DATA_ONTO_Y_G_PORT', 'ZLimitSumm', 'ZModeForce', 'ZOrder', + 'ZSamplePosition', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID', + '_soc24_ENUM_HEADER', 'ge1_assembler_busy', + 'ge1_assembler_dma_starved', 'ge1_assembler_stalled', + 'ge1_dma_busy', 'ge1_dma_lat_bin_0', 'ge1_dma_lat_bin_1', + 'ge1_dma_lat_bin_2', 'ge1_dma_lat_bin_3', 'ge1_dma_lat_bin_4', + 'ge1_dma_lat_bin_5', 'ge1_dma_lat_bin_6', 'ge1_dma_lat_bin_7', + 'ge1_dma_return_cl0', 'ge1_dma_return_cl1', + 'ge1_dma_return_size_cl0', 'ge1_dma_return_size_cl1', + 'ge1_dma_utcl1_consecutive_retry_event', + 'ge1_dma_utcl1_request_event', 'ge1_dma_utcl1_retry_event', + 'ge1_dma_utcl1_stall_event', 'ge1_dma_utcl1_stall_utcl2_event', + 'ge1_dma_utcl1_translation_hit_event', + 'ge1_dma_utcl1_translation_miss_event', 'ge1_pipe0_to_pipe1', + 'ge1_pipe1_to_pipe0', 'ge1_prim_group_limit_hit', + 'ge1_rbiu_di_fifo_stalled_p0', 'ge1_rbiu_di_fifo_stalled_p1', + 'ge1_rbiu_di_fifo_starved_p0', 'ge1_rbiu_di_fifo_starved_p1', + 'ge1_rbiu_dr_fifo_stalled_p0', 'ge1_rbiu_dr_fifo_stalled_p1', + 'ge1_rbiu_dr_fifo_starved_p0', 'ge1_rbiu_dr_fifo_starved_p1', + 'ge1_sclk_input_vld', 'ge1_sclk_reg_vld', + 'ge1_small_draws_one_instance', 'ge1_stat_busy', + 'ge1_stat_no_dma_busy', 'ge1_unopt_multi_instance_draws', + 'ge_agm_gcr_combine', 'ge_agm_gcr_crd_stall', + 'ge_agm_gcr_latency', 'ge_agm_gcr_req', 'ge_agm_gcr_req_amount', + 'ge_agm_gcr_req_outstanding', 'ge_agm_gcr_stall', + 'ge_agm_gcr_tag_stall', 'ge_all_tf2', 'ge_all_tf3', 'ge_all_tf4', + 'ge_all_tf5', 'ge_all_tf6', 'ge_all_tf_eq', 'ge_csb_spi_bp', + 'ge_dist_distributer_busy', 'ge_dist_hs_done', + 'ge_dist_hs_done_latency', 'ge_dist_hs_done_latency_se0', + 'ge_dist_hs_done_latency_se1', 'ge_dist_hs_done_latency_se2', + 'ge_dist_hs_done_latency_se3', 'ge_dist_hs_done_latency_se4', + 'ge_dist_hs_done_latency_se5', 'ge_dist_hs_done_latency_se6', + 'ge_dist_hs_done_latency_se7', 'ge_dist_hs_done_se0', + 'ge_dist_hs_done_se1', 'ge_dist_hs_done_se2', + 'ge_dist_hs_done_se3', 'ge_dist_hs_done_se4', + 'ge_dist_hs_done_se5', 'ge_dist_hs_done_se6', + 'ge_dist_hs_done_se7', 'ge_dist_indx_fifos_full_and_empty', + 'ge_dist_inside_tf_bin_0', 'ge_dist_inside_tf_bin_1', + 'ge_dist_inside_tf_bin_2', 'ge_dist_inside_tf_bin_3', + 'ge_dist_inside_tf_bin_4', 'ge_dist_inside_tf_bin_5', + 'ge_dist_inside_tf_bin_6', 'ge_dist_inside_tf_bin_7', + 'ge_dist_inside_tf_bin_8', 'ge_dist_null_patch', + 'ge_dist_op_fifo_full_starve', 'ge_dist_pc_feorder_fifo_full', + 'ge_dist_pc_ge_manager_busy', 'ge_dist_sclk_core_vld', + 'ge_dist_sclk_input_vld', 'ge_dist_sclk_wd_te11_vld', + 'ge_dist_switch_mode_stall', 'ge_dist_te11_starved', + 'ge_dist_tfreq_lat_bin_0', 'ge_dist_tfreq_lat_bin_1', + 'ge_dist_tfreq_lat_bin_2', 'ge_dist_tfreq_lat_bin_3', + 'ge_dist_tfreq_lat_bin_4', 'ge_dist_tfreq_lat_bin_5', + 'ge_dist_tfreq_lat_bin_6', 'ge_dist_tfreq_lat_bin_7', + 'ge_dist_tfreq_utcl1_consecutive_retry_event', + 'ge_dist_tfreq_utcl1_request_event', + 'ge_dist_tfreq_utcl1_retry_event', + 'ge_dist_tfreq_utcl1_stall_event', + 'ge_dist_tfreq_utcl1_stall_utcl2_event', + 'ge_dist_tfreq_utcl1_translation_hit_event', + 'ge_dist_tfreq_utcl1_translation_miss_event', + 'ge_dist_wd_te11_busy', 'ge_distclk_vld', 'ge_esvert_send', + 'ge_gs_issue_rtr_stalled', 'ge_gsprim_send', + 'ge_gsprim_stalled_esvert', 'ge_gsthread_stalled', + 'ge_hs_done_all_tf0_se0', 'ge_hs_done_all_tf0_se1', + 'ge_hs_done_all_tf0_se2', 'ge_hs_done_all_tf0_se3', + 'ge_hs_done_all_tf0_se4', 'ge_hs_done_all_tf0_se5', + 'ge_hs_done_all_tf0_se6', 'ge_hs_done_all_tf0_se7', + 'ge_hs_done_all_tf1_se0', 'ge_hs_done_all_tf1_se1', + 'ge_hs_done_all_tf1_se2', 'ge_hs_done_all_tf1_se3', + 'ge_hs_done_all_tf1_se4', 'ge_hs_done_all_tf1_se5', + 'ge_hs_done_all_tf1_se6', 'ge_hs_done_all_tf1_se7', + 'ge_hs_stall_tfmm_fifo_full', 'ge_hs_tif_stall', + 'ge_merge_gsgrp_rdy_pending_verts', + 'ge_merge_hsgrp_rdy_pending_verts', 'ge_merge_hsgs_fifo_blocked', + 'ge_merge_hsgs_grp_switch', 'ge_merge_hsgs_vert_switch', + 'ge_merge_lses_fifo_blocked', 'ge_merge_lses_vert_switch', + 'ge_merged_hsgs_grp_stalled', 'ge_merged_hsgs_vert_stalled', + 'ge_merged_lses_vert_stalled', 'ge_ngg_agm_req_stall', + 'ge_ngg_attr_discard_alloc', 'ge_ngg_attr_grp_alloc', + 'ge_ngg_attr_grp_latency', 'ge_ngg_attr_grp_wasted', + 'ge_ngg_attr_null_dealloc', 'ge_ngg_busy_base', + 'ge_ngg_indx_bus_stall', 'ge_ngg_ord_id_req_stall', + 'ge_ngg_pc_space_not_avail', 'ge_ngg_reuse_prim_limit_hit', + 'ge_ngg_reuse_vert_limit_hit', 'ge_ngg_spi_esvert_partial_eov', + 'ge_ngg_spi_gsprim_partial_eov', 'ge_ngg_stall_tess_off_tess_on', + 'ge_ngg_stall_tess_on_tess_off', 'ge_ngg_starved_after_work', + 'ge_ngg_starved_idle', 'ge_ngg_starving_for_wave_id', + 'ge_ngg_subgrp_fifo_stall', 'ge_num_of_donut_dist_patches', + 'ge_num_of_hs_dealloc_events', 'ge_num_of_no_dist_patches', + 'ge_num_of_patch_dist_patches', + 'ge_num_of_se_switches_due_to_donut', + 'ge_num_of_se_switches_due_to_patch_accum', + 'ge_num_of_se_switches_due_to_trap', 'ge_pa0_csb_eop', + 'ge_se0_te11_starved_on_hs_done', + 'ge_se1_te11_starved_on_hs_done', + 'ge_se2_te11_starved_on_hs_done', + 'ge_se3_te11_starved_on_hs_done', + 'ge_se4_te11_starved_on_hs_done', + 'ge_se5_te11_starved_on_hs_done', + 'ge_se6_te11_starved_on_hs_done', + 'ge_se7_te11_starved_on_hs_done', 'ge_se_api_ds_verts', + 'ge_se_api_vs_verts', 'ge_se_combined_busy', + 'ge_se_ds_cache_hits', 'ge_se_ds_prims', 'ge_se_es_thread_groups', + 'ge_se_esvert_stalled_gsprim', 'ge_se_hs_input_stall', + 'ge_se_hs_tfm_stall', 'ge_se_hs_tgs_active_high_water_mark', + 'ge_se_hs_thread_groups', 'ge_se_reused_es_indices', + 'ge_se_sclk_input_vld', 'ge_se_sclk_ngg_vld', + 'ge_se_sclk_te11_vld', 'ge_se_sending_vert_or_prim', + 'ge_se_spi_esvert_eov', 'ge_se_spi_esvert_stalled', + 'ge_se_spi_esvert_starved_busy', 'ge_se_spi_esvert_valid', + 'ge_se_spi_gsprim_cont', 'ge_se_spi_gsprim_eov', + 'ge_se_spi_gsprim_stalled', 'ge_se_spi_gsprim_starved_busy', + 'ge_se_spi_gsprim_valid', + 'ge_se_spi_gssubgrp_event_window_active', + 'ge_se_spi_gssubgrp_is_event', 'ge_se_spi_gssubgrp_send', + 'ge_se_spi_hsgrp_is_event', 'ge_se_spi_hsgrp_send', + 'ge_se_spi_hsvert_eov', 'ge_se_spi_hsvert_fifo_full_stall', + 'ge_se_spi_hsvert_stalled', 'ge_se_spi_hsvert_starved_busy', + 'ge_se_spi_hsvert_valid', 'ge_se_spi_lsvert_eov', + 'ge_se_spi_lsvert_stalled', 'ge_se_spi_lsvert_starved_busy', + 'ge_se_spi_lsvert_valid', 'ge_se_spi_tgrp_fifo_stall', + 'ge_spi_gsgrp_valid', 'ge_spi_gssubgrp_stalled', + 'ge_spi_hsgrp_spi_stall', 'ge_spi_hsvert_send', + 'ge_spi_hswave_fifo_full_stall', 'ge_spi_lsvert_send', + 'ge_spi_lswave_fifo_full_stall', 'ge_te11_compactor_starved', + 'ge_te11_con_stall', 'ge_tf_ret_data_stalling_hs_done'] diff --git a/tinygrad_repo/tinygrad/runtime/autogen/am/vega10.py b/tinygrad_repo/tinygrad/runtime/autogen/am/vega10.py new file mode 100644 index 000000000..510fbe6a0 --- /dev/null +++ b/tinygrad_repo/tinygrad/runtime/autogen/am/vega10.py @@ -0,0 +1,36196 @@ +# mypy: ignore-errors +# -*- coding: utf-8 -*- +# +# TARGET arch is: [] +# WORD_SIZE is: 8 +# POINTER_SIZE is: 8 +# LONGDOUBLE_SIZE is: 16 +# +import ctypes + + + + +_vega10_ENUM_HEADER = True # macro +ENUMS_GDS_PERFCOUNT_SELECT_H = True # macro +SQ_WAVE_TYPE_PS0 = 0x00000000 # macro +SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro +SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro +SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro +SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro +SQIND_WAVE_HWREGS_OFFSET = 0x00000010 # macro +SQIND_WAVE_HWREGS_SIZE = 0x000001f0 # macro +SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro +SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro +SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro +SQIND_WAVE_VGPRS_SIZE = 0x00000100 # macro +SQ_GFXDEC_BEGIN = 0x0000a000 # macro +SQ_GFXDEC_END = 0x0000c000 # macro +SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro +SQDEC_BEGIN = 0x00002300 # macro +SQDEC_END = 0x000023ff # macro +SQPERFSDEC_BEGIN = 0x0000d9c0 # macro +SQPERFSDEC_END = 0x0000da40 # macro +SQPERFDDEC_BEGIN = 0x0000d1c0 # macro +SQPERFDDEC_END = 0x0000d240 # macro +SQGFXUDEC_BEGIN = 0x0000c330 # macro +SQGFXUDEC_END = 0x0000c380 # macro +SQPWRDEC_BEGIN = 0x0000f08c # macro +SQPWRDEC_END = 0x0000f094 # macro +SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro +SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro +SQ_MAX_PGM_SGPRS = 0x00000068 # macro +SQ_MAX_PGM_VGPRS = 0x00000100 # macro +SQ_THREAD_TRACE_TIME_UNIT = 0x00000004 # macro +SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro +SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro +SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro +SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro +SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro +SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro +SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro +SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro +SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro +SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro +SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro +INST_ID_PRIV_START = 0x80000000 # macro +INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro +INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro +INST_ID_HW_TRAP = 0xfffffff2 # macro +INST_ID_KILL_SEQ = 0xfffffff3 # macro +INST_ID_SPI_WREXEC = 0xfffffff4 # macro +INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro +SIMM16_WAITCNT_VM_CNT_START = 0x00000000 # macro +SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000004 # macro +SIMM16_WAITCNT_EXP_CNT_START = 0x00000004 # macro +SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_LGKM_CNT_START = 0x00000008 # macro +SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000004 # macro +SIMM16_WAITCNT_VM_CNT_HI_START = 0x0000000e # macro +SIMM16_WAITCNT_VM_CNT_HI_SIZE = 0x00000002 # macro +SQ_EDC_FUE_CNTL_SQ = 0x00000000 # macro +SQ_EDC_FUE_CNTL_LDS = 0x00000001 # macro +SQ_EDC_FUE_CNTL_SIMD0 = 0x00000002 # macro +SQ_EDC_FUE_CNTL_SIMD1 = 0x00000003 # macro +SQ_EDC_FUE_CNTL_SIMD2 = 0x00000004 # macro +SQ_EDC_FUE_CNTL_SIMD3 = 0x00000005 # macro +SQ_EDC_FUE_CNTL_TA = 0x00000006 # macro +SQ_EDC_FUE_CNTL_TD = 0x00000007 # macro +SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro +CSDATA_TYPE_WIDTH = 0x00000002 # macro +CSDATA_ADDR_WIDTH = 0x00000007 # macro +CSDATA_DATA_WIDTH = 0x00000020 # macro +GSTHREADID_SIZE = 0x00000002 # macro +GB_TILING_CONFIG_TABLE_SIZE = 0x00000020 # macro +GB_TILING_CONFIG_MACROTABLE_SIZE = 0x00000010 # macro +SEM_ECC_ERROR = 0x00000000 # macro +SEM_TRANS_ERROR = 0x00000001 # macro +SEM_FAILED = 0x00000002 # macro +SEM_PASSED = 0x00000003 # macro +IQ_QUEUE_SLEEP = 0x00000000 # macro +IQ_OFFLOAD_RETRY = 0x00000001 # macro +IQ_SCH_WAVE_MSG = 0x00000002 # macro +IQ_SEM_REARM = 0x00000003 # macro +IQ_DEQUEUE_RETRY = 0x00000004 # macro +IQ_INTR_TYPE_PQ = 0x00000000 # macro +IQ_INTR_TYPE_IB = 0x00000001 # macro +IQ_INTR_TYPE_MQD = 0x00000002 # macro +VMID_SZ = 0x00000004 # macro +CONFIG_SPACE_START = 0x00002000 # macro +CONFIG_SPACE_END = 0x00009fff # macro +CONFIG_SPACE1_START = 0x00002000 # macro +CONFIG_SPACE1_END = 0x00002bff # macro +CONFIG_SPACE2_START = 0x00003000 # macro +CONFIG_SPACE2_END = 0x00009fff # macro +UCONFIG_SPACE_START = 0x0000c000 # macro +UCONFIG_SPACE_END = 0x0000ffff # macro +PERSISTENT_SPACE_START = 0x00002c00 # macro +PERSISTENT_SPACE_END = 0x00002fff # macro +CONTEXT_SPACE_START = 0x0000a000 # macro +CONTEXT_SPACE_END = 0x0000bfff # macro +SQ_ENC_SOP1_BITS = 0xbe800000 # macro +SQ_ENC_SOP1_MASK = 0xff800000 # macro +SQ_ENC_SOP1_FIELD = 0x0000017d # macro +SQ_ENC_SOPC_BITS = 0xbf000000 # macro +SQ_ENC_SOPC_MASK = 0xff800000 # macro +SQ_ENC_SOPC_FIELD = 0x0000017e # macro +SQ_ENC_SOPP_BITS = 0xbf800000 # macro +SQ_ENC_SOPP_MASK = 0xff800000 # macro +SQ_ENC_SOPP_FIELD = 0x0000017f # macro +SQ_ENC_SOPK_BITS = 0xb0000000 # macro +SQ_ENC_SOPK_MASK = 0xf0000000 # macro +SQ_ENC_SOPK_FIELD = 0x0000000b # macro +SQ_ENC_SOP2_BITS = 0x80000000 # macro +SQ_ENC_SOP2_MASK = 0xc0000000 # macro +SQ_ENC_SOP2_FIELD = 0x00000002 # macro +SQ_ENC_SMEM_BITS = 0xc0000000 # macro +SQ_ENC_SMEM_MASK = 0xfc000000 # macro +SQ_ENC_SMEM_FIELD = 0x00000030 # macro +SQ_ENC_VOP1_BITS = 0x7e000000 # macro +SQ_ENC_VOP1_MASK = 0xfe000000 # macro +SQ_ENC_VOP1_FIELD = 0x0000003f # macro +SQ_ENC_VOPC_BITS = 0x7c000000 # macro +SQ_ENC_VOPC_MASK = 0xfe000000 # macro +SQ_ENC_VOPC_FIELD = 0x0000003e # macro +SQ_ENC_VOP2_BITS = 0x00000000 # macro +SQ_ENC_VOP2_MASK = 0x80000000 # macro +SQ_ENC_VOP2_FIELD = 0x00000000 # macro +SQ_ENC_VINTRP_BITS = 0xd4000000 # macro +SQ_ENC_VINTRP_MASK = 0xfc000000 # macro +SQ_ENC_VINTRP_FIELD = 0x00000035 # macro +SQ_ENC_VOP3P_BITS = 0xd3800000 # macro +SQ_ENC_VOP3P_MASK = 0xff800000 # macro +SQ_ENC_VOP3P_FIELD = 0x000001a7 # macro +SQ_ENC_VOP3_BITS = 0xd0000000 # macro +SQ_ENC_VOP3_MASK = 0xfc000000 # macro +SQ_ENC_VOP3_FIELD = 0x00000034 # macro +SQ_ENC_DS_BITS = 0xd8000000 # macro +SQ_ENC_DS_MASK = 0xfc000000 # macro +SQ_ENC_DS_FIELD = 0x00000036 # macro +SQ_ENC_MUBUF_BITS = 0xe0000000 # macro +SQ_ENC_MUBUF_MASK = 0xfc000000 # macro +SQ_ENC_MUBUF_FIELD = 0x00000038 # macro +SQ_ENC_MTBUF_BITS = 0xe8000000 # macro +SQ_ENC_MTBUF_MASK = 0xfc000000 # macro +SQ_ENC_MTBUF_FIELD = 0x0000003a # macro +SQ_ENC_MIMG_BITS = 0xf0000000 # macro +SQ_ENC_MIMG_MASK = 0xfc000000 # macro +SQ_ENC_MIMG_FIELD = 0x0000003c # macro +SQ_ENC_EXP_BITS = 0xc4000000 # macro +SQ_ENC_EXP_MASK = 0xfc000000 # macro +SQ_ENC_EXP_FIELD = 0x00000031 # macro +SQ_ENC_FLAT_BITS = 0xdc000000 # macro +SQ_ENC_FLAT_MASK = 0xfc000000 # macro +SQ_ENC_FLAT_FIELD = 0x00000037 # macro +SQ_V_OP3_INTRP_COUNT = 0x0000000c # macro +SQ_SENDMSG_SYSTEM_SIZE = 0x00000003 # macro +SQ_HWREG_ID_SIZE = 0x00000006 # macro +SQ_V_OPC_COUNT = 0x00000100 # macro +SQ_NUM_VGPR = 0x00000100 # macro +SQ_WAITCNT_LGKM_SHIFT = 0x00000008 # macro +SQ_HWREG_ID_SHIFT = 0x00000000 # macro +SQ_EXP_NUM_POS = 0x00000004 # macro +SQ_XLATE_VOP3_TO_VOPC_OFFSET = 0x00000000 # macro +SQ_V_OP3_2IN_OFFSET = 0x00000280 # macro +SQ_XLATE_VOP3_TO_VOP2_OFFSET = 0x00000100 # macro +SQ_EXP_NUM_MRT = 0x00000008 # macro +SQ_NUM_TTMP = 0x00000010 # macro +SQ_SENDMSG_STREAMID_SHIFT = 0x00000008 # macro +SQ_V_OP1_COUNT = 0x00000080 # macro +SQ_WAITCNT_LGKM_SIZE = 0x00000004 # macro +SQ_XLATE_VOP3_TO_VOPC_COUNT = 0x00000100 # macro +SQ_SENDMSG_MSG_SHIFT = 0x00000000 # macro +SQ_V_OP3_3IN_OFFSET = 0x000001c0 # macro +SQ_HWREG_OFFSET_SHIFT = 0x00000006 # macro +SQ_HWREG_SIZE_SHIFT = 0x0000000b # macro +SQ_HWREG_OFFSET_SIZE = 0x00000005 # macro +SQ_V_OP3_3IN_COUNT = 0x000000b0 # macro +SQ_SENDMSG_MSG_SIZE = 0x00000004 # macro +SQ_XLATE_VOP3_TO_VOP1_COUNT = 0x00000080 # macro +SQ_EXP_NUM_GDS = 0x00000005 # macro +SQ_V_OP2_COUNT = 0x00000040 # macro +SQ_SENDMSG_GSOP_SIZE = 0x00000002 # macro +SQ_WAITCNT_VM_SHIFT = 0x00000000 # macro +SQ_XLATE_VOP3_TO_VOP3P_COUNT = 0x00000080 # macro +SQ_V_OP3_2IN_COUNT = 0x00000080 # macro +SQ_SENDMSG_SYSTEM_SHIFT = 0x00000004 # macro +SQ_WAITCNT_VM_SIZE = 0x00000004 # macro +SQ_XLATE_VOP3_TO_VOP3P_OFFSET = 0x00000380 # macro +SQ_WAITCNT_EXP_SHIFT = 0x00000004 # macro +SQ_XLATE_VOP3_TO_VOP2_COUNT = 0x00000040 # macro +SQ_EXP_NUM_PARAM = 0x00000020 # macro +SQ_HWREG_SIZE_SIZE = 0x00000005 # macro +SQ_WAITCNT_EXP_SIZE = 0x00000003 # macro +SQ_V_OP3_INTRP_OFFSET = 0x00000274 # macro +SQ_SENDMSG_GSOP_SHIFT = 0x00000004 # macro +SQ_XLATE_VOP3_TO_VINTRP_OFFSET = 0x00000270 # macro +SQ_NUM_ATTR = 0x00000021 # macro +SQ_NUM_SGPR = 0x00000066 # macro +SQ_SRC_VGPR_BIT = 0x00000100 # macro +SQ_V_INTRP_COUNT = 0x00000004 # macro +SQ_SENDMSG_STREAMID_SIZE = 0x00000002 # macro +SQ_V_OP3P_COUNT = 0x00000080 # macro +SQ_XLATE_VOP3_TO_VOP1_OFFSET = 0x00000140 # macro +SQ_XLATE_VOP3_TO_VINTRP_COUNT = 0x00000004 # macro +SQ_SRC_DPP = 0x000000fa # macro +SQ_TBUFFER_LOAD_FORMAT_X = 0x00000000 # macro +SQ_TBUFFER_LOAD_FORMAT_XY = 0x00000001 # macro +SQ_TBUFFER_LOAD_FORMAT_XYZ = 0x00000002 # macro +SQ_TBUFFER_LOAD_FORMAT_XYZW = 0x00000003 # macro +SQ_TBUFFER_STORE_FORMAT_X = 0x00000004 # macro +SQ_TBUFFER_STORE_FORMAT_XY = 0x00000005 # macro +SQ_TBUFFER_STORE_FORMAT_XYZ = 0x00000006 # macro +SQ_TBUFFER_STORE_FORMAT_XYZW = 0x00000007 # macro +SQ_TBUFFER_LOAD_FORMAT_D16_X = 0x00000008 # macro +SQ_TBUFFER_LOAD_FORMAT_D16_XY = 0x00000009 # macro +SQ_TBUFFER_LOAD_FORMAT_D16_XYZ = 0x0000000a # macro +SQ_TBUFFER_LOAD_FORMAT_D16_XYZW = 0x0000000b # macro +SQ_TBUFFER_STORE_FORMAT_D16_X = 0x0000000c # macro +SQ_TBUFFER_STORE_FORMAT_D16_XY = 0x0000000d # macro +SQ_TBUFFER_STORE_FORMAT_D16_XYZ = 0x0000000e # macro +SQ_TBUFFER_STORE_FORMAT_D16_XYZW = 0x0000000f # macro +SQ_GLOBAL_LOAD_UBYTE = 0x00000010 # macro +SQ_GLOBAL_LOAD_SBYTE = 0x00000011 # macro +SQ_GLOBAL_LOAD_USHORT = 0x00000012 # macro +SQ_GLOBAL_LOAD_SSHORT = 0x00000013 # macro +SQ_GLOBAL_LOAD_DWORD = 0x00000014 # macro +SQ_GLOBAL_LOAD_DWORDX2 = 0x00000015 # macro +SQ_GLOBAL_LOAD_DWORDX3 = 0x00000016 # macro +SQ_GLOBAL_LOAD_DWORDX4 = 0x00000017 # macro +SQ_GLOBAL_STORE_BYTE = 0x00000018 # macro +SQ_GLOBAL_STORE_SHORT = 0x0000001a # macro +SQ_GLOBAL_STORE_DWORD = 0x0000001c # macro +SQ_GLOBAL_STORE_DWORDX2 = 0x0000001d # macro +SQ_GLOBAL_STORE_DWORDX3 = 0x0000001e # macro +SQ_GLOBAL_STORE_DWORDX4 = 0x0000001f # macro +SQ_GLOBAL_ATOMIC_SWAP = 0x00000040 # macro +SQ_GLOBAL_ATOMIC_CMPSWAP = 0x00000041 # macro +SQ_GLOBAL_ATOMIC_ADD = 0x00000042 # macro +SQ_GLOBAL_ATOMIC_SUB = 0x00000043 # macro +SQ_GLOBAL_ATOMIC_SMIN = 0x00000044 # macro +SQ_GLOBAL_ATOMIC_UMIN = 0x00000045 # macro +SQ_GLOBAL_ATOMIC_SMAX = 0x00000046 # macro +SQ_GLOBAL_ATOMIC_UMAX = 0x00000047 # macro +SQ_GLOBAL_ATOMIC_AND = 0x00000048 # macro +SQ_GLOBAL_ATOMIC_OR = 0x00000049 # macro +SQ_GLOBAL_ATOMIC_XOR = 0x0000004a # macro +SQ_GLOBAL_ATOMIC_INC = 0x0000004b # macro +SQ_GLOBAL_ATOMIC_DEC = 0x0000004c # macro +SQ_GLOBAL_ATOMIC_SWAP_X2 = 0x00000060 # macro +SQ_GLOBAL_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro +SQ_GLOBAL_ATOMIC_ADD_X2 = 0x00000062 # macro +SQ_GLOBAL_ATOMIC_SUB_X2 = 0x00000063 # macro +SQ_GLOBAL_ATOMIC_SMIN_X2 = 0x00000064 # macro +SQ_GLOBAL_ATOMIC_UMIN_X2 = 0x00000065 # macro +SQ_GLOBAL_ATOMIC_SMAX_X2 = 0x00000066 # macro +SQ_GLOBAL_ATOMIC_UMAX_X2 = 0x00000067 # macro +SQ_GLOBAL_ATOMIC_AND_X2 = 0x00000068 # macro +SQ_GLOBAL_ATOMIC_OR_X2 = 0x00000069 # macro +SQ_GLOBAL_ATOMIC_XOR_X2 = 0x0000006a # macro +SQ_GLOBAL_ATOMIC_INC_X2 = 0x0000006b # macro +SQ_GLOBAL_ATOMIC_DEC_X2 = 0x0000006c # macro +SQ_VGPR0 = 0x00000000 # macro +SQ_SCRATCH_LOAD_UBYTE = 0x00000010 # macro +SQ_SCRATCH_LOAD_SBYTE = 0x00000011 # macro +SQ_SCRATCH_LOAD_USHORT = 0x00000012 # macro +SQ_SCRATCH_LOAD_SSHORT = 0x00000013 # macro +SQ_SCRATCH_LOAD_DWORD = 0x00000014 # macro +SQ_SCRATCH_LOAD_DWORDX2 = 0x00000015 # macro +SQ_SCRATCH_LOAD_DWORDX3 = 0x00000016 # macro +SQ_SCRATCH_LOAD_DWORDX4 = 0x00000017 # macro +SQ_SCRATCH_STORE_BYTE = 0x00000018 # macro +SQ_SCRATCH_STORE_SHORT = 0x0000001a # macro +SQ_SCRATCH_STORE_DWORD = 0x0000001c # macro +SQ_SCRATCH_STORE_DWORDX2 = 0x0000001d # macro +SQ_SCRATCH_STORE_DWORDX3 = 0x0000001e # macro +SQ_SCRATCH_STORE_DWORDX4 = 0x0000001f # macro +SQ_VCC_ALL = 0x00000000 # macro +SQ_SRC_0 = 0x00000080 # macro +SQ_SRC_1_INT = 0x00000081 # macro +SQ_SRC_2_INT = 0x00000082 # macro +SQ_SRC_3_INT = 0x00000083 # macro +SQ_SRC_4_INT = 0x00000084 # macro +SQ_SRC_5_INT = 0x00000085 # macro +SQ_SRC_6_INT = 0x00000086 # macro +SQ_SRC_7_INT = 0x00000087 # macro +SQ_SRC_8_INT = 0x00000088 # macro +SQ_SRC_9_INT = 0x00000089 # macro +SQ_SRC_10_INT = 0x0000008a # macro +SQ_SRC_11_INT = 0x0000008b # macro +SQ_SRC_12_INT = 0x0000008c # macro +SQ_SRC_13_INT = 0x0000008d # macro +SQ_SRC_14_INT = 0x0000008e # macro +SQ_SRC_15_INT = 0x0000008f # macro +SQ_SRC_16_INT = 0x00000090 # macro +SQ_SRC_17_INT = 0x00000091 # macro +SQ_SRC_18_INT = 0x00000092 # macro +SQ_SRC_19_INT = 0x00000093 # macro +SQ_SRC_20_INT = 0x00000094 # macro +SQ_SRC_21_INT = 0x00000095 # macro +SQ_SRC_22_INT = 0x00000096 # macro +SQ_SRC_23_INT = 0x00000097 # macro +SQ_SRC_24_INT = 0x00000098 # macro +SQ_SRC_25_INT = 0x00000099 # macro +SQ_SRC_26_INT = 0x0000009a # macro +SQ_SRC_27_INT = 0x0000009b # macro +SQ_SRC_28_INT = 0x0000009c # macro +SQ_SRC_29_INT = 0x0000009d # macro +SQ_SRC_30_INT = 0x0000009e # macro +SQ_SRC_31_INT = 0x0000009f # macro +SQ_SRC_32_INT = 0x000000a0 # macro +SQ_SRC_33_INT = 0x000000a1 # macro +SQ_SRC_34_INT = 0x000000a2 # macro +SQ_SRC_35_INT = 0x000000a3 # macro +SQ_SRC_36_INT = 0x000000a4 # macro +SQ_SRC_37_INT = 0x000000a5 # macro +SQ_SRC_38_INT = 0x000000a6 # macro +SQ_SRC_39_INT = 0x000000a7 # macro +SQ_SRC_40_INT = 0x000000a8 # macro +SQ_SRC_41_INT = 0x000000a9 # macro +SQ_SRC_42_INT = 0x000000aa # macro +SQ_SRC_43_INT = 0x000000ab # macro +SQ_SRC_44_INT = 0x000000ac # macro +SQ_SRC_45_INT = 0x000000ad # macro +SQ_SRC_46_INT = 0x000000ae # macro +SQ_SRC_47_INT = 0x000000af # macro +SQ_SRC_48_INT = 0x000000b0 # macro +SQ_SRC_49_INT = 0x000000b1 # macro +SQ_SRC_50_INT = 0x000000b2 # macro +SQ_SRC_51_INT = 0x000000b3 # macro +SQ_SRC_52_INT = 0x000000b4 # macro +SQ_SRC_53_INT = 0x000000b5 # macro +SQ_SRC_54_INT = 0x000000b6 # macro +SQ_SRC_55_INT = 0x000000b7 # macro +SQ_SRC_56_INT = 0x000000b8 # macro +SQ_SRC_57_INT = 0x000000b9 # macro +SQ_SRC_58_INT = 0x000000ba # macro +SQ_SRC_59_INT = 0x000000bb # macro +SQ_SRC_60_INT = 0x000000bc # macro +SQ_SRC_61_INT = 0x000000bd # macro +SQ_SRC_62_INT = 0x000000be # macro +SQ_SRC_63_INT = 0x000000bf # macro +SQ_IMAGE_LOAD = 0x00000000 # macro +SQ_IMAGE_LOAD_MIP = 0x00000001 # macro +SQ_IMAGE_LOAD_PCK = 0x00000002 # macro +SQ_IMAGE_LOAD_PCK_SGN = 0x00000003 # macro +SQ_IMAGE_LOAD_MIP_PCK = 0x00000004 # macro +SQ_IMAGE_LOAD_MIP_PCK_SGN = 0x00000005 # macro +SQ_IMAGE_STORE = 0x00000008 # macro +SQ_IMAGE_STORE_MIP = 0x00000009 # macro +SQ_IMAGE_STORE_PCK = 0x0000000a # macro +SQ_IMAGE_STORE_MIP_PCK = 0x0000000b # macro +SQ_IMAGE_GET_RESINFO = 0x0000000e # macro +SQ_IMAGE_ATOMIC_SWAP = 0x00000010 # macro +SQ_IMAGE_ATOMIC_CMPSWAP = 0x00000011 # macro +SQ_IMAGE_ATOMIC_ADD = 0x00000012 # macro +SQ_IMAGE_ATOMIC_SUB = 0x00000013 # macro +SQ_IMAGE_ATOMIC_SMIN = 0x00000014 # macro +SQ_IMAGE_ATOMIC_UMIN = 0x00000015 # macro +SQ_IMAGE_ATOMIC_SMAX = 0x00000016 # macro +SQ_IMAGE_ATOMIC_UMAX = 0x00000017 # macro +SQ_IMAGE_ATOMIC_AND = 0x00000018 # macro +SQ_IMAGE_ATOMIC_OR = 0x00000019 # macro +SQ_IMAGE_ATOMIC_XOR = 0x0000001a # macro +SQ_IMAGE_ATOMIC_INC = 0x0000001b # macro +SQ_IMAGE_ATOMIC_DEC = 0x0000001c # macro +SQ_IMAGE_SAMPLE = 0x00000020 # macro +SQ_IMAGE_SAMPLE_CL = 0x00000021 # macro +SQ_IMAGE_SAMPLE_D = 0x00000022 # macro +SQ_IMAGE_SAMPLE_D_CL = 0x00000023 # macro +SQ_IMAGE_SAMPLE_L = 0x00000024 # macro +SQ_IMAGE_SAMPLE_B = 0x00000025 # macro +SQ_IMAGE_SAMPLE_B_CL = 0x00000026 # macro +SQ_IMAGE_SAMPLE_LZ = 0x00000027 # macro +SQ_IMAGE_SAMPLE_C = 0x00000028 # macro +SQ_IMAGE_SAMPLE_C_CL = 0x00000029 # macro +SQ_IMAGE_SAMPLE_C_D = 0x0000002a # macro +SQ_IMAGE_SAMPLE_C_D_CL = 0x0000002b # macro +SQ_IMAGE_SAMPLE_C_L = 0x0000002c # macro +SQ_IMAGE_SAMPLE_C_B = 0x0000002d # macro +SQ_IMAGE_SAMPLE_C_B_CL = 0x0000002e # macro +SQ_IMAGE_SAMPLE_C_LZ = 0x0000002f # macro +SQ_IMAGE_SAMPLE_O = 0x00000030 # macro +SQ_IMAGE_SAMPLE_CL_O = 0x00000031 # macro +SQ_IMAGE_SAMPLE_D_O = 0x00000032 # macro +SQ_IMAGE_SAMPLE_D_CL_O = 0x00000033 # macro +SQ_IMAGE_SAMPLE_L_O = 0x00000034 # macro +SQ_IMAGE_SAMPLE_B_O = 0x00000035 # macro +SQ_IMAGE_SAMPLE_B_CL_O = 0x00000036 # macro +SQ_IMAGE_SAMPLE_LZ_O = 0x00000037 # macro +SQ_IMAGE_SAMPLE_C_O = 0x00000038 # macro +SQ_IMAGE_SAMPLE_C_CL_O = 0x00000039 # macro +SQ_IMAGE_SAMPLE_C_D_O = 0x0000003a # macro +SQ_IMAGE_SAMPLE_C_D_CL_O = 0x0000003b # macro +SQ_IMAGE_SAMPLE_C_L_O = 0x0000003c # macro +SQ_IMAGE_SAMPLE_C_B_O = 0x0000003d # macro +SQ_IMAGE_SAMPLE_C_B_CL_O = 0x0000003e # macro +SQ_IMAGE_SAMPLE_C_LZ_O = 0x0000003f # macro +SQ_IMAGE_GATHER4 = 0x00000040 # macro +SQ_IMAGE_GATHER4_CL = 0x00000041 # macro +SQ_IMAGE_GATHER4H = 0x00000042 # macro +SQ_IMAGE_GATHER4_L = 0x00000044 # macro +SQ_IMAGE_GATHER4_B = 0x00000045 # macro +SQ_IMAGE_GATHER4_B_CL = 0x00000046 # macro +SQ_IMAGE_GATHER4_LZ = 0x00000047 # macro +SQ_IMAGE_GATHER4_C = 0x00000048 # macro +SQ_IMAGE_GATHER4_C_CL = 0x00000049 # macro +SQ_IMAGE_GATHER4H_PCK = 0x0000004a # macro +SQ_IMAGE_GATHER8H_PCK = 0x0000004b # macro +SQ_IMAGE_GATHER4_C_L = 0x0000004c # macro +SQ_IMAGE_GATHER4_C_B = 0x0000004d # macro +SQ_IMAGE_GATHER4_C_B_CL = 0x0000004e # macro +SQ_IMAGE_GATHER4_C_LZ = 0x0000004f # macro +SQ_IMAGE_GATHER4_O = 0x00000050 # macro +SQ_IMAGE_GATHER4_CL_O = 0x00000051 # macro +SQ_IMAGE_GATHER4_L_O = 0x00000054 # macro +SQ_IMAGE_GATHER4_B_O = 0x00000055 # macro +SQ_IMAGE_GATHER4_B_CL_O = 0x00000056 # macro +SQ_IMAGE_GATHER4_LZ_O = 0x00000057 # macro +SQ_IMAGE_GATHER4_C_O = 0x00000058 # macro +SQ_IMAGE_GATHER4_C_CL_O = 0x00000059 # macro +SQ_IMAGE_GATHER4_C_L_O = 0x0000005c # macro +SQ_IMAGE_GATHER4_C_B_O = 0x0000005d # macro +SQ_IMAGE_GATHER4_C_B_CL_O = 0x0000005e # macro +SQ_IMAGE_GATHER4_C_LZ_O = 0x0000005f # macro +SQ_IMAGE_GET_LOD = 0x00000060 # macro +SQ_IMAGE_SAMPLE_CD = 0x00000068 # macro +SQ_IMAGE_SAMPLE_CD_CL = 0x00000069 # macro +SQ_IMAGE_SAMPLE_C_CD = 0x0000006a # macro +SQ_IMAGE_SAMPLE_C_CD_CL = 0x0000006b # macro +SQ_IMAGE_SAMPLE_CD_O = 0x0000006c # macro +SQ_IMAGE_SAMPLE_CD_CL_O = 0x0000006d # macro +SQ_IMAGE_SAMPLE_C_CD_O = 0x0000006e # macro +SQ_IMAGE_SAMPLE_C_CD_CL_O = 0x0000006f # macro +SQ_IMAGE_RSRC256 = 0x0000007e # macro +SQ_IMAGE_SAMPLER = 0x0000007f # macro +SQ_HW_REG_MODE = 0x00000001 # macro +SQ_HW_REG_STATUS = 0x00000002 # macro +SQ_HW_REG_TRAPSTS = 0x00000003 # macro +SQ_HW_REG_HW_ID = 0x00000004 # macro +SQ_HW_REG_GPR_ALLOC = 0x00000005 # macro +SQ_HW_REG_LDS_ALLOC = 0x00000006 # macro +SQ_HW_REG_IB_STS = 0x00000007 # macro +SQ_HW_REG_PC_LO = 0x00000008 # macro +SQ_HW_REG_PC_HI = 0x00000009 # macro +SQ_HW_REG_INST_DW0 = 0x0000000a # macro +SQ_HW_REG_INST_DW1 = 0x0000000b # macro +SQ_HW_REG_IB_DBG0 = 0x0000000c # macro +SQ_HW_REG_IB_DBG1 = 0x0000000d # macro +SQ_HW_REG_FLUSH_IB = 0x0000000e # macro +SQ_HW_REG_SH_MEM_BASES = 0x0000000f # macro +SQ_HW_REG_SQ_SHADER_TBA_LO = 0x00000010 # macro +SQ_HW_REG_SQ_SHADER_TBA_HI = 0x00000011 # macro +SQ_HW_REG_SQ_SHADER_TMA_LO = 0x00000012 # macro +SQ_HW_REG_SQ_SHADER_TMA_HI = 0x00000013 # macro +SQ_S_MOV_B32 = 0x00000000 # macro +SQ_S_MOV_B64 = 0x00000001 # macro +SQ_S_CMOV_B32 = 0x00000002 # macro +SQ_S_CMOV_B64 = 0x00000003 # macro +SQ_S_NOT_B32 = 0x00000004 # macro +SQ_S_NOT_B64 = 0x00000005 # macro +SQ_S_WQM_B32 = 0x00000006 # macro +SQ_S_WQM_B64 = 0x00000007 # macro +SQ_S_BREV_B32 = 0x00000008 # macro +SQ_S_BREV_B64 = 0x00000009 # macro +SQ_S_BCNT0_I32_B32 = 0x0000000a # macro +SQ_S_BCNT0_I32_B64 = 0x0000000b # macro +SQ_S_BCNT1_I32_B32 = 0x0000000c # macro +SQ_S_BCNT1_I32_B64 = 0x0000000d # macro +SQ_S_FF0_I32_B32 = 0x0000000e # macro +SQ_S_FF0_I32_B64 = 0x0000000f # macro +SQ_S_FF1_I32_B32 = 0x00000010 # macro +SQ_S_FF1_I32_B64 = 0x00000011 # macro +SQ_S_FLBIT_I32_B32 = 0x00000012 # macro +SQ_S_FLBIT_I32_B64 = 0x00000013 # macro +SQ_S_FLBIT_I32 = 0x00000014 # macro +SQ_S_FLBIT_I32_I64 = 0x00000015 # macro +SQ_S_SEXT_I32_I8 = 0x00000016 # macro +SQ_S_SEXT_I32_I16 = 0x00000017 # macro +SQ_S_BITSET0_B32 = 0x00000018 # macro +SQ_S_BITSET0_B64 = 0x00000019 # macro +SQ_S_BITSET1_B32 = 0x0000001a # macro +SQ_S_BITSET1_B64 = 0x0000001b # macro +SQ_S_GETPC_B64 = 0x0000001c # macro +SQ_S_SETPC_B64 = 0x0000001d # macro +SQ_S_SWAPPC_B64 = 0x0000001e # macro +SQ_S_RFE_B64 = 0x0000001f # macro +SQ_S_AND_SAVEEXEC_B64 = 0x00000020 # macro +SQ_S_OR_SAVEEXEC_B64 = 0x00000021 # macro +SQ_S_XOR_SAVEEXEC_B64 = 0x00000022 # macro +SQ_S_ANDN2_SAVEEXEC_B64 = 0x00000023 # macro +SQ_S_ORN2_SAVEEXEC_B64 = 0x00000024 # macro +SQ_S_NAND_SAVEEXEC_B64 = 0x00000025 # macro +SQ_S_NOR_SAVEEXEC_B64 = 0x00000026 # macro +SQ_S_XNOR_SAVEEXEC_B64 = 0x00000027 # macro +SQ_S_QUADMASK_B32 = 0x00000028 # macro +SQ_S_QUADMASK_B64 = 0x00000029 # macro +SQ_S_MOVRELS_B32 = 0x0000002a # macro +SQ_S_MOVRELS_B64 = 0x0000002b # macro +SQ_S_MOVRELD_B32 = 0x0000002c # macro +SQ_S_MOVRELD_B64 = 0x0000002d # macro +SQ_S_CBRANCH_JOIN = 0x0000002e # macro +SQ_S_MOV_REGRD_B32 = 0x0000002f # macro +SQ_S_ABS_I32 = 0x00000030 # macro +SQ_S_MOV_FED_B32 = 0x00000031 # macro +SQ_S_SET_GPR_IDX_IDX = 0x00000032 # macro +SQ_S_ANDN1_SAVEEXEC_B64 = 0x00000033 # macro +SQ_S_ORN1_SAVEEXEC_B64 = 0x00000034 # macro +SQ_S_ANDN1_WREXEC_B64 = 0x00000035 # macro +SQ_S_ANDN2_WREXEC_B64 = 0x00000036 # macro +SQ_S_BITREPLICATE_B64_B32 = 0x00000037 # macro +SQ_CNT1 = 0x00000000 # macro +SQ_CNT2 = 0x00000001 # macro +SQ_CNT3 = 0x00000002 # macro +SQ_CNT4 = 0x00000003 # macro +SQ_V_MAD_LEGACY_F32 = 0x000001c0 # macro +SQ_V_MAD_F32 = 0x000001c1 # macro +SQ_V_MAD_I32_I24 = 0x000001c2 # macro +SQ_V_MAD_U32_U24 = 0x000001c3 # macro +SQ_V_CUBEID_F32 = 0x000001c4 # macro +SQ_V_CUBESC_F32 = 0x000001c5 # macro +SQ_V_CUBETC_F32 = 0x000001c6 # macro +SQ_V_CUBEMA_F32 = 0x000001c7 # macro +SQ_V_BFE_U32 = 0x000001c8 # macro +SQ_V_BFE_I32 = 0x000001c9 # macro +SQ_V_BFI_B32 = 0x000001ca # macro +SQ_V_FMA_F32 = 0x000001cb # macro +SQ_V_FMA_F64 = 0x000001cc # macro +SQ_V_LERP_U8 = 0x000001cd # macro +SQ_V_ALIGNBIT_B32 = 0x000001ce # macro +SQ_V_ALIGNBYTE_B32 = 0x000001cf # macro +SQ_V_MIN3_F32 = 0x000001d0 # macro +SQ_V_MIN3_I32 = 0x000001d1 # macro +SQ_V_MIN3_U32 = 0x000001d2 # macro +SQ_V_MAX3_F32 = 0x000001d3 # macro +SQ_V_MAX3_I32 = 0x000001d4 # macro +SQ_V_MAX3_U32 = 0x000001d5 # macro +SQ_V_MED3_F32 = 0x000001d6 # macro +SQ_V_MED3_I32 = 0x000001d7 # macro +SQ_V_MED3_U32 = 0x000001d8 # macro +SQ_V_SAD_U8 = 0x000001d9 # macro +SQ_V_SAD_HI_U8 = 0x000001da # macro +SQ_V_SAD_U16 = 0x000001db # macro +SQ_V_SAD_U32 = 0x000001dc # macro +SQ_V_CVT_PK_U8_F32 = 0x000001dd # macro +SQ_V_DIV_FIXUP_F32 = 0x000001de # macro +SQ_V_DIV_FIXUP_F64 = 0x000001df # macro +SQ_V_DIV_SCALE_F32 = 0x000001e0 # macro +SQ_V_DIV_SCALE_F64 = 0x000001e1 # macro +SQ_V_DIV_FMAS_F32 = 0x000001e2 # macro +SQ_V_DIV_FMAS_F64 = 0x000001e3 # macro +SQ_V_MSAD_U8 = 0x000001e4 # macro +SQ_V_QSAD_PK_U16_U8 = 0x000001e5 # macro +SQ_V_MQSAD_PK_U16_U8 = 0x000001e6 # macro +SQ_V_MQSAD_U32_U8 = 0x000001e7 # macro +SQ_V_MAD_U64_U32 = 0x000001e8 # macro +SQ_V_MAD_I64_I32 = 0x000001e9 # macro +SQ_V_MAD_LEGACY_F16 = 0x000001ea # macro +SQ_V_MAD_LEGACY_U16 = 0x000001eb # macro +SQ_V_MAD_LEGACY_I16 = 0x000001ec # macro +SQ_V_PERM_B32 = 0x000001ed # macro +SQ_V_FMA_LEGACY_F16 = 0x000001ee # macro +SQ_V_DIV_FIXUP_LEGACY_F16 = 0x000001ef # macro +SQ_V_CVT_PKACCUM_U8_F32 = 0x000001f0 # macro +SQ_V_MAD_U32_U16 = 0x000001f1 # macro +SQ_V_MAD_I32_I16 = 0x000001f2 # macro +SQ_V_XAD_U32 = 0x000001f3 # macro +SQ_V_MIN3_F16 = 0x000001f4 # macro +SQ_V_MIN3_I16 = 0x000001f5 # macro +SQ_V_MIN3_U16 = 0x000001f6 # macro +SQ_V_MAX3_F16 = 0x000001f7 # macro +SQ_V_MAX3_I16 = 0x000001f8 # macro +SQ_V_MAX3_U16 = 0x000001f9 # macro +SQ_V_MED3_F16 = 0x000001fa # macro +SQ_V_MED3_I16 = 0x000001fb # macro +SQ_V_MED3_U16 = 0x000001fc # macro +SQ_V_LSHL_ADD_U32 = 0x000001fd # macro +SQ_V_ADD_LSHL_U32 = 0x000001fe # macro +SQ_V_ADD3_U32 = 0x000001ff # macro +SQ_V_LSHL_OR_B32 = 0x00000200 # macro +SQ_V_AND_OR_B32 = 0x00000201 # macro +SQ_V_OR3_B32 = 0x00000202 # macro +SQ_V_MAD_F16 = 0x00000203 # macro +SQ_V_MAD_U16 = 0x00000204 # macro +SQ_V_MAD_I16 = 0x00000205 # macro +SQ_V_FMA_F16 = 0x00000206 # macro +SQ_V_DIV_FIXUP_F16 = 0x00000207 # macro +SQ_V_INTERP_P1LL_F16 = 0x00000274 # macro +SQ_V_INTERP_P1LV_F16 = 0x00000275 # macro +SQ_V_INTERP_P2_LEGACY_F16 = 0x00000276 # macro +SQ_V_INTERP_P2_F16 = 0x00000277 # macro +SQ_V_ADD_F64 = 0x00000280 # macro +SQ_V_MUL_F64 = 0x00000281 # macro +SQ_V_MIN_F64 = 0x00000282 # macro +SQ_V_MAX_F64 = 0x00000283 # macro +SQ_V_LDEXP_F64 = 0x00000284 # macro +SQ_V_MUL_LO_U32 = 0x00000285 # macro +SQ_V_MUL_HI_U32 = 0x00000286 # macro +SQ_V_MUL_HI_I32 = 0x00000287 # macro +SQ_V_LDEXP_F32 = 0x00000288 # macro +SQ_V_READLANE_B32 = 0x00000289 # macro +SQ_V_WRITELANE_B32 = 0x0000028a # macro +SQ_V_BCNT_U32_B32 = 0x0000028b # macro +SQ_V_MBCNT_LO_U32_B32 = 0x0000028c # macro +SQ_V_MBCNT_HI_U32_B32 = 0x0000028d # macro +SQ_V_MAC_LEGACY_F32 = 0x0000028e # macro +SQ_V_LSHLREV_B64 = 0x0000028f # macro +SQ_V_LSHRREV_B64 = 0x00000290 # macro +SQ_V_ASHRREV_I64 = 0x00000291 # macro +SQ_V_TRIG_PREOP_F64 = 0x00000292 # macro +SQ_V_BFM_B32 = 0x00000293 # macro +SQ_V_CVT_PKNORM_I16_F32 = 0x00000294 # macro +SQ_V_CVT_PKNORM_U16_F32 = 0x00000295 # macro +SQ_V_CVT_PKRTZ_F16_F32 = 0x00000296 # macro +SQ_V_CVT_PK_U16_U32 = 0x00000297 # macro +SQ_V_CVT_PK_I16_I32 = 0x00000298 # macro +SQ_V_CVT_PKNORM_I16_F16 = 0x00000299 # macro +SQ_V_CVT_PKNORM_U16_F16 = 0x0000029a # macro +SQ_V_READLANE_REGRD_B32 = 0x0000029b # macro +SQ_V_ADD_I32 = 0x0000029c # macro +SQ_V_SUB_I32 = 0x0000029d # macro +SQ_V_ADD_I16 = 0x0000029e # macro +SQ_V_SUB_I16 = 0x0000029f # macro +SQ_V_PACK_B32_F16 = 0x000002a0 # macro +SQ_SRC_LITERAL = 0x000000ff # macro +SQ_DPP_QUAD_PERM = 0x00000000 # macro +SQ_DPP_ROW_SL1 = 0x00000101 # macro +SQ_DPP_ROW_SL2 = 0x00000102 # macro +SQ_DPP_ROW_SL3 = 0x00000103 # macro +SQ_DPP_ROW_SL4 = 0x00000104 # macro +SQ_DPP_ROW_SL5 = 0x00000105 # macro +SQ_DPP_ROW_SL6 = 0x00000106 # macro +SQ_DPP_ROW_SL7 = 0x00000107 # macro +SQ_DPP_ROW_SL8 = 0x00000108 # macro +SQ_DPP_ROW_SL9 = 0x00000109 # macro +SQ_DPP_ROW_SL10 = 0x0000010a # macro +SQ_DPP_ROW_SL11 = 0x0000010b # macro +SQ_DPP_ROW_SL12 = 0x0000010c # macro +SQ_DPP_ROW_SL13 = 0x0000010d # macro +SQ_DPP_ROW_SL14 = 0x0000010e # macro +SQ_DPP_ROW_SL15 = 0x0000010f # macro +SQ_DPP_ROW_SR1 = 0x00000111 # macro +SQ_DPP_ROW_SR2 = 0x00000112 # macro +SQ_DPP_ROW_SR3 = 0x00000113 # macro +SQ_DPP_ROW_SR4 = 0x00000114 # macro +SQ_DPP_ROW_SR5 = 0x00000115 # macro +SQ_DPP_ROW_SR6 = 0x00000116 # macro +SQ_DPP_ROW_SR7 = 0x00000117 # macro +SQ_DPP_ROW_SR8 = 0x00000118 # macro +SQ_DPP_ROW_SR9 = 0x00000119 # macro +SQ_DPP_ROW_SR10 = 0x0000011a # macro +SQ_DPP_ROW_SR11 = 0x0000011b # macro +SQ_DPP_ROW_SR12 = 0x0000011c # macro +SQ_DPP_ROW_SR13 = 0x0000011d # macro +SQ_DPP_ROW_SR14 = 0x0000011e # macro +SQ_DPP_ROW_SR15 = 0x0000011f # macro +SQ_DPP_ROW_RR1 = 0x00000121 # macro +SQ_DPP_ROW_RR2 = 0x00000122 # macro +SQ_DPP_ROW_RR3 = 0x00000123 # macro +SQ_DPP_ROW_RR4 = 0x00000124 # macro +SQ_DPP_ROW_RR5 = 0x00000125 # macro +SQ_DPP_ROW_RR6 = 0x00000126 # macro +SQ_DPP_ROW_RR7 = 0x00000127 # macro +SQ_DPP_ROW_RR8 = 0x00000128 # macro +SQ_DPP_ROW_RR9 = 0x00000129 # macro +SQ_DPP_ROW_RR10 = 0x0000012a # macro +SQ_DPP_ROW_RR11 = 0x0000012b # macro +SQ_DPP_ROW_RR12 = 0x0000012c # macro +SQ_DPP_ROW_RR13 = 0x0000012d # macro +SQ_DPP_ROW_RR14 = 0x0000012e # macro +SQ_DPP_ROW_RR15 = 0x0000012f # macro +SQ_DPP_WF_SL1 = 0x00000130 # macro +SQ_DPP_WF_RL1 = 0x00000134 # macro +SQ_DPP_WF_SR1 = 0x00000138 # macro +SQ_DPP_WF_RR1 = 0x0000013c # macro +SQ_DPP_ROW_MIRROR = 0x00000140 # macro +SQ_DPP_ROW_HALF_MIRROR = 0x00000141 # macro +SQ_DPP_ROW_BCAST15 = 0x00000142 # macro +SQ_DPP_ROW_BCAST31 = 0x00000143 # macro +SQ_FLAT_SCRATCH_LO = 0x00000066 # macro +SQ_FLAT_SCRATCH_HI = 0x00000067 # macro +SQ_V_NOP = 0x00000000 # macro +SQ_V_MOV_B32 = 0x00000001 # macro +SQ_V_READFIRSTLANE_B32 = 0x00000002 # macro +SQ_V_CVT_I32_F64 = 0x00000003 # macro +SQ_V_CVT_F64_I32 = 0x00000004 # macro +SQ_V_CVT_F32_I32 = 0x00000005 # macro +SQ_V_CVT_F32_U32 = 0x00000006 # macro +SQ_V_CVT_U32_F32 = 0x00000007 # macro +SQ_V_CVT_I32_F32 = 0x00000008 # macro +SQ_V_MOV_FED_B32 = 0x00000009 # macro +SQ_V_CVT_F16_F32 = 0x0000000a # macro +SQ_V_CVT_F32_F16 = 0x0000000b # macro +SQ_V_CVT_RPI_I32_F32 = 0x0000000c # macro +SQ_V_CVT_FLR_I32_F32 = 0x0000000d # macro +SQ_V_CVT_OFF_F32_I4 = 0x0000000e # macro +SQ_V_CVT_F32_F64 = 0x0000000f # macro +SQ_V_CVT_F64_F32 = 0x00000010 # macro +SQ_V_CVT_F32_UBYTE0 = 0x00000011 # macro +SQ_V_CVT_F32_UBYTE1 = 0x00000012 # macro +SQ_V_CVT_F32_UBYTE2 = 0x00000013 # macro +SQ_V_CVT_F32_UBYTE3 = 0x00000014 # macro +SQ_V_CVT_U32_F64 = 0x00000015 # macro +SQ_V_CVT_F64_U32 = 0x00000016 # macro +SQ_V_TRUNC_F64 = 0x00000017 # macro +SQ_V_CEIL_F64 = 0x00000018 # macro +SQ_V_RNDNE_F64 = 0x00000019 # macro +SQ_V_FLOOR_F64 = 0x0000001a # macro +SQ_V_FRACT_F32 = 0x0000001b # macro +SQ_V_TRUNC_F32 = 0x0000001c # macro +SQ_V_CEIL_F32 = 0x0000001d # macro +SQ_V_RNDNE_F32 = 0x0000001e # macro +SQ_V_FLOOR_F32 = 0x0000001f # macro +SQ_V_EXP_F32 = 0x00000020 # macro +SQ_V_LOG_F32 = 0x00000021 # macro +SQ_V_RCP_F32 = 0x00000022 # macro +SQ_V_RCP_IFLAG_F32 = 0x00000023 # macro +SQ_V_RSQ_F32 = 0x00000024 # macro +SQ_V_RCP_F64 = 0x00000025 # macro +SQ_V_RSQ_F64 = 0x00000026 # macro +SQ_V_SQRT_F32 = 0x00000027 # macro +SQ_V_SQRT_F64 = 0x00000028 # macro +SQ_V_SIN_F32 = 0x00000029 # macro +SQ_V_COS_F32 = 0x0000002a # macro +SQ_V_NOT_B32 = 0x0000002b # macro +SQ_V_BFREV_B32 = 0x0000002c # macro +SQ_V_FFBH_U32 = 0x0000002d # macro +SQ_V_FFBL_B32 = 0x0000002e # macro +SQ_V_FFBH_I32 = 0x0000002f # macro +SQ_V_FREXP_EXP_I32_F64 = 0x00000030 # macro +SQ_V_FREXP_MANT_F64 = 0x00000031 # macro +SQ_V_FRACT_F64 = 0x00000032 # macro +SQ_V_FREXP_EXP_I32_F32 = 0x00000033 # macro +SQ_V_FREXP_MANT_F32 = 0x00000034 # macro +SQ_V_CLREXCP = 0x00000035 # macro +SQ_V_MOV_PRSV_B32 = 0x00000036 # macro +SQ_V_CVT_F16_U16 = 0x00000039 # macro +SQ_V_CVT_F16_I16 = 0x0000003a # macro +SQ_V_CVT_U16_F16 = 0x0000003b # macro +SQ_V_CVT_I16_F16 = 0x0000003c # macro +SQ_V_RCP_F16 = 0x0000003d # macro +SQ_V_SQRT_F16 = 0x0000003e # macro +SQ_V_RSQ_F16 = 0x0000003f # macro +SQ_V_LOG_F16 = 0x00000040 # macro +SQ_V_EXP_F16 = 0x00000041 # macro +SQ_V_FREXP_MANT_F16 = 0x00000042 # macro +SQ_V_FREXP_EXP_I16_F16 = 0x00000043 # macro +SQ_V_FLOOR_F16 = 0x00000044 # macro +SQ_V_CEIL_F16 = 0x00000045 # macro +SQ_V_TRUNC_F16 = 0x00000046 # macro +SQ_V_RNDNE_F16 = 0x00000047 # macro +SQ_V_FRACT_F16 = 0x00000048 # macro +SQ_V_SIN_F16 = 0x00000049 # macro +SQ_V_COS_F16 = 0x0000004a # macro +SQ_V_EXP_LEGACY_F32 = 0x0000004b # macro +SQ_V_LOG_LEGACY_F32 = 0x0000004c # macro +SQ_V_CVT_NORM_I16_F16 = 0x0000004d # macro +SQ_V_CVT_NORM_U16_F16 = 0x0000004e # macro +SQ_V_SAT_PK_U8_I16 = 0x0000004f # macro +SQ_V_WRITELANE_IMM32 = 0x00000050 # macro +SQ_V_SWAP_B32 = 0x00000051 # macro +SQ_FLAT_LOAD_UBYTE = 0x00000010 # macro +SQ_FLAT_LOAD_SBYTE = 0x00000011 # macro +SQ_FLAT_LOAD_USHORT = 0x00000012 # macro +SQ_FLAT_LOAD_SSHORT = 0x00000013 # macro +SQ_FLAT_LOAD_DWORD = 0x00000014 # macro +SQ_FLAT_LOAD_DWORDX2 = 0x00000015 # macro +SQ_FLAT_LOAD_DWORDX3 = 0x00000016 # macro +SQ_FLAT_LOAD_DWORDX4 = 0x00000017 # macro +SQ_FLAT_STORE_BYTE = 0x00000018 # macro +SQ_FLAT_STORE_SHORT = 0x0000001a # macro +SQ_FLAT_STORE_DWORD = 0x0000001c # macro +SQ_FLAT_STORE_DWORDX2 = 0x0000001d # macro +SQ_FLAT_STORE_DWORDX3 = 0x0000001e # macro +SQ_FLAT_STORE_DWORDX4 = 0x0000001f # macro +SQ_FLAT_ATOMIC_SWAP = 0x00000040 # macro +SQ_FLAT_ATOMIC_CMPSWAP = 0x00000041 # macro +SQ_FLAT_ATOMIC_ADD = 0x00000042 # macro +SQ_FLAT_ATOMIC_SUB = 0x00000043 # macro +SQ_FLAT_ATOMIC_SMIN = 0x00000044 # macro +SQ_FLAT_ATOMIC_UMIN = 0x00000045 # macro +SQ_FLAT_ATOMIC_SMAX = 0x00000046 # macro +SQ_FLAT_ATOMIC_UMAX = 0x00000047 # macro +SQ_FLAT_ATOMIC_AND = 0x00000048 # macro +SQ_FLAT_ATOMIC_OR = 0x00000049 # macro +SQ_FLAT_ATOMIC_XOR = 0x0000004a # macro +SQ_FLAT_ATOMIC_INC = 0x0000004b # macro +SQ_FLAT_ATOMIC_DEC = 0x0000004c # macro +SQ_FLAT_ATOMIC_SWAP_X2 = 0x00000060 # macro +SQ_FLAT_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro +SQ_FLAT_ATOMIC_ADD_X2 = 0x00000062 # macro +SQ_FLAT_ATOMIC_SUB_X2 = 0x00000063 # macro +SQ_FLAT_ATOMIC_SMIN_X2 = 0x00000064 # macro +SQ_FLAT_ATOMIC_UMIN_X2 = 0x00000065 # macro +SQ_FLAT_ATOMIC_SMAX_X2 = 0x00000066 # macro +SQ_FLAT_ATOMIC_UMAX_X2 = 0x00000067 # macro +SQ_FLAT_ATOMIC_AND_X2 = 0x00000068 # macro +SQ_FLAT_ATOMIC_OR_X2 = 0x00000069 # macro +SQ_FLAT_ATOMIC_XOR_X2 = 0x0000006a # macro +SQ_FLAT_ATOMIC_INC_X2 = 0x0000006b # macro +SQ_FLAT_ATOMIC_DEC_X2 = 0x0000006c # macro +SQ_DS_ADD_U32 = 0x00000000 # macro +SQ_DS_SUB_U32 = 0x00000001 # macro +SQ_DS_RSUB_U32 = 0x00000002 # macro +SQ_DS_INC_U32 = 0x00000003 # macro +SQ_DS_DEC_U32 = 0x00000004 # macro +SQ_DS_MIN_I32 = 0x00000005 # macro +SQ_DS_MAX_I32 = 0x00000006 # macro +SQ_DS_MIN_U32 = 0x00000007 # macro +SQ_DS_MAX_U32 = 0x00000008 # macro +SQ_DS_AND_B32 = 0x00000009 # macro +SQ_DS_OR_B32 = 0x0000000a # macro +SQ_DS_XOR_B32 = 0x0000000b # macro +SQ_DS_MSKOR_B32 = 0x0000000c # macro +SQ_DS_WRITE_B32 = 0x0000000d # macro +SQ_DS_WRITE2_B32 = 0x0000000e # macro +SQ_DS_WRITE2ST64_B32 = 0x0000000f # macro +SQ_DS_CMPST_B32 = 0x00000010 # macro +SQ_DS_CMPST_F32 = 0x00000011 # macro +SQ_DS_MIN_F32 = 0x00000012 # macro +SQ_DS_MAX_F32 = 0x00000013 # macro +SQ_DS_NOP = 0x00000014 # macro +SQ_DS_ADD_F32 = 0x00000015 # macro +SQ_DS_WRITE_ADDTID_B32 = 0x0000001d # macro +SQ_DS_WRITE_B8 = 0x0000001e # macro +SQ_DS_WRITE_B16 = 0x0000001f # macro +SQ_DS_ADD_RTN_U32 = 0x00000020 # macro +SQ_DS_SUB_RTN_U32 = 0x00000021 # macro +SQ_DS_RSUB_RTN_U32 = 0x00000022 # macro +SQ_DS_INC_RTN_U32 = 0x00000023 # macro +SQ_DS_DEC_RTN_U32 = 0x00000024 # macro +SQ_DS_MIN_RTN_I32 = 0x00000025 # macro +SQ_DS_MAX_RTN_I32 = 0x00000026 # macro +SQ_DS_MIN_RTN_U32 = 0x00000027 # macro +SQ_DS_MAX_RTN_U32 = 0x00000028 # macro +SQ_DS_AND_RTN_B32 = 0x00000029 # macro +SQ_DS_OR_RTN_B32 = 0x0000002a # macro +SQ_DS_XOR_RTN_B32 = 0x0000002b # macro +SQ_DS_MSKOR_RTN_B32 = 0x0000002c # macro +SQ_DS_WRXCHG_RTN_B32 = 0x0000002d # macro +SQ_DS_WRXCHG2_RTN_B32 = 0x0000002e # macro +SQ_DS_WRXCHG2ST64_RTN_B32 = 0x0000002f # macro +SQ_DS_CMPST_RTN_B32 = 0x00000030 # macro +SQ_DS_CMPST_RTN_F32 = 0x00000031 # macro +SQ_DS_MIN_RTN_F32 = 0x00000032 # macro +SQ_DS_MAX_RTN_F32 = 0x00000033 # macro +SQ_DS_WRAP_RTN_B32 = 0x00000034 # macro +SQ_DS_ADD_RTN_F32 = 0x00000035 # macro +SQ_DS_READ_B32 = 0x00000036 # macro +SQ_DS_READ2_B32 = 0x00000037 # macro +SQ_DS_READ2ST64_B32 = 0x00000038 # macro +SQ_DS_READ_I8 = 0x00000039 # macro +SQ_DS_READ_U8 = 0x0000003a # macro +SQ_DS_READ_I16 = 0x0000003b # macro +SQ_DS_READ_U16 = 0x0000003c # macro +SQ_DS_SWIZZLE_B32 = 0x0000003d # macro +SQ_DS_PERMUTE_B32 = 0x0000003e # macro +SQ_DS_BPERMUTE_B32 = 0x0000003f # macro +SQ_DS_ADD_U64 = 0x00000040 # macro +SQ_DS_SUB_U64 = 0x00000041 # macro +SQ_DS_RSUB_U64 = 0x00000042 # macro +SQ_DS_INC_U64 = 0x00000043 # macro +SQ_DS_DEC_U64 = 0x00000044 # macro +SQ_DS_MIN_I64 = 0x00000045 # macro +SQ_DS_MAX_I64 = 0x00000046 # macro +SQ_DS_MIN_U64 = 0x00000047 # macro +SQ_DS_MAX_U64 = 0x00000048 # macro +SQ_DS_AND_B64 = 0x00000049 # macro +SQ_DS_OR_B64 = 0x0000004a # macro +SQ_DS_XOR_B64 = 0x0000004b # macro +SQ_DS_MSKOR_B64 = 0x0000004c # macro +SQ_DS_WRITE_B64 = 0x0000004d # macro +SQ_DS_WRITE2_B64 = 0x0000004e # macro +SQ_DS_WRITE2ST64_B64 = 0x0000004f # macro +SQ_DS_CMPST_B64 = 0x00000050 # macro +SQ_DS_CMPST_F64 = 0x00000051 # macro +SQ_DS_MIN_F64 = 0x00000052 # macro +SQ_DS_MAX_F64 = 0x00000053 # macro +SQ_DS_ADD_RTN_U64 = 0x00000060 # macro +SQ_DS_SUB_RTN_U64 = 0x00000061 # macro +SQ_DS_RSUB_RTN_U64 = 0x00000062 # macro +SQ_DS_INC_RTN_U64 = 0x00000063 # macro +SQ_DS_DEC_RTN_U64 = 0x00000064 # macro +SQ_DS_MIN_RTN_I64 = 0x00000065 # macro +SQ_DS_MAX_RTN_I64 = 0x00000066 # macro +SQ_DS_MIN_RTN_U64 = 0x00000067 # macro +SQ_DS_MAX_RTN_U64 = 0x00000068 # macro +SQ_DS_AND_RTN_B64 = 0x00000069 # macro +SQ_DS_OR_RTN_B64 = 0x0000006a # macro +SQ_DS_XOR_RTN_B64 = 0x0000006b # macro +SQ_DS_MSKOR_RTN_B64 = 0x0000006c # macro +SQ_DS_WRXCHG_RTN_B64 = 0x0000006d # macro +SQ_DS_WRXCHG2_RTN_B64 = 0x0000006e # macro +SQ_DS_WRXCHG2ST64_RTN_B64 = 0x0000006f # macro +SQ_DS_CMPST_RTN_B64 = 0x00000070 # macro +SQ_DS_CMPST_RTN_F64 = 0x00000071 # macro +SQ_DS_MIN_RTN_F64 = 0x00000072 # macro +SQ_DS_MAX_RTN_F64 = 0x00000073 # macro +SQ_DS_READ_B64 = 0x00000076 # macro +SQ_DS_READ2_B64 = 0x00000077 # macro +SQ_DS_READ2ST64_B64 = 0x00000078 # macro +SQ_DS_CONDXCHG32_RTN_B64 = 0x0000007e # macro +SQ_DS_ADD_SRC2_U32 = 0x00000080 # macro +SQ_DS_SUB_SRC2_U32 = 0x00000081 # macro +SQ_DS_RSUB_SRC2_U32 = 0x00000082 # macro +SQ_DS_INC_SRC2_U32 = 0x00000083 # macro +SQ_DS_DEC_SRC2_U32 = 0x00000084 # macro +SQ_DS_MIN_SRC2_I32 = 0x00000085 # macro +SQ_DS_MAX_SRC2_I32 = 0x00000086 # macro +SQ_DS_MIN_SRC2_U32 = 0x00000087 # macro +SQ_DS_MAX_SRC2_U32 = 0x00000088 # macro +SQ_DS_AND_SRC2_B32 = 0x00000089 # macro +SQ_DS_OR_SRC2_B32 = 0x0000008a # macro +SQ_DS_XOR_SRC2_B32 = 0x0000008b # macro +SQ_DS_WRITE_SRC2_B32 = 0x0000008d # macro +SQ_DS_MIN_SRC2_F32 = 0x00000092 # macro +SQ_DS_MAX_SRC2_F32 = 0x00000093 # macro +SQ_DS_ADD_SRC2_F32 = 0x00000095 # macro +SQ_DS_GWS_SEMA_RELEASE_ALL = 0x00000098 # macro +SQ_DS_GWS_INIT = 0x00000099 # macro +SQ_DS_GWS_SEMA_V = 0x0000009a # macro +SQ_DS_GWS_SEMA_BR = 0x0000009b # macro +SQ_DS_GWS_SEMA_P = 0x0000009c # macro +SQ_DS_GWS_BARRIER = 0x0000009d # macro +SQ_DS_READ_ADDTID_B32 = 0x000000b6 # macro +SQ_DS_CONSUME = 0x000000bd # macro +SQ_DS_APPEND = 0x000000be # macro +SQ_DS_ORDERED_COUNT = 0x000000bf # macro +SQ_DS_ADD_SRC2_U64 = 0x000000c0 # macro +SQ_DS_SUB_SRC2_U64 = 0x000000c1 # macro +SQ_DS_RSUB_SRC2_U64 = 0x000000c2 # macro +SQ_DS_INC_SRC2_U64 = 0x000000c3 # macro +SQ_DS_DEC_SRC2_U64 = 0x000000c4 # macro +SQ_DS_MIN_SRC2_I64 = 0x000000c5 # macro +SQ_DS_MAX_SRC2_I64 = 0x000000c6 # macro +SQ_DS_MIN_SRC2_U64 = 0x000000c7 # macro +SQ_DS_MAX_SRC2_U64 = 0x000000c8 # macro +SQ_DS_AND_SRC2_B64 = 0x000000c9 # macro +SQ_DS_OR_SRC2_B64 = 0x000000ca # macro +SQ_DS_XOR_SRC2_B64 = 0x000000cb # macro +SQ_DS_WRITE_SRC2_B64 = 0x000000cd # macro +SQ_DS_MIN_SRC2_F64 = 0x000000d2 # macro +SQ_DS_MAX_SRC2_F64 = 0x000000d3 # macro +SQ_DS_WRITE_B96 = 0x000000de # macro +SQ_DS_WRITE_B128 = 0x000000df # macro +SQ_DS_CONDXCHG32_RTN_B128 = 0x000000fd # macro +SQ_DS_READ_B96 = 0x000000fe # macro +SQ_DS_READ_B128 = 0x000000ff # macro +SQ_S_LOAD_DWORD = 0x00000000 # macro +SQ_S_LOAD_DWORDX2 = 0x00000001 # macro +SQ_S_LOAD_DWORDX4 = 0x00000002 # macro +SQ_S_LOAD_DWORDX8 = 0x00000003 # macro +SQ_S_LOAD_DWORDX16 = 0x00000004 # macro +SQ_S_SCRATCH_LOAD_DWORD = 0x00000005 # macro +SQ_S_SCRATCH_LOAD_DWORDX2 = 0x00000006 # macro +SQ_S_SCRATCH_LOAD_DWORDX4 = 0x00000007 # macro +SQ_S_BUFFER_LOAD_DWORD = 0x00000008 # macro +SQ_S_BUFFER_LOAD_DWORDX2 = 0x00000009 # macro +SQ_S_BUFFER_LOAD_DWORDX4 = 0x0000000a # macro +SQ_S_BUFFER_LOAD_DWORDX8 = 0x0000000b # macro +SQ_S_BUFFER_LOAD_DWORDX16 = 0x0000000c # macro +SQ_S_STORE_DWORD = 0x00000010 # macro +SQ_S_STORE_DWORDX2 = 0x00000011 # macro +SQ_S_STORE_DWORDX4 = 0x00000012 # macro +SQ_S_SCRATCH_STORE_DWORD = 0x00000015 # macro +SQ_S_SCRATCH_STORE_DWORDX2 = 0x00000016 # macro +SQ_S_SCRATCH_STORE_DWORDX4 = 0x00000017 # macro +SQ_S_BUFFER_STORE_DWORD = 0x00000018 # macro +SQ_S_BUFFER_STORE_DWORDX2 = 0x00000019 # macro +SQ_S_BUFFER_STORE_DWORDX4 = 0x0000001a # macro +SQ_S_DCACHE_INV = 0x00000020 # macro +SQ_S_DCACHE_WB = 0x00000021 # macro +SQ_S_DCACHE_INV_VOL = 0x00000022 # macro +SQ_S_DCACHE_WB_VOL = 0x00000023 # macro +SQ_S_MEMTIME = 0x00000024 # macro +SQ_S_MEMREALTIME = 0x00000025 # macro +SQ_S_ATC_PROBE = 0x00000026 # macro +SQ_S_ATC_PROBE_BUFFER = 0x00000027 # macro +SQ_S_BUFFER_ATOMIC_SWAP = 0x00000040 # macro +SQ_S_BUFFER_ATOMIC_CMPSWAP = 0x00000041 # macro +SQ_S_BUFFER_ATOMIC_ADD = 0x00000042 # macro +SQ_S_BUFFER_ATOMIC_SUB = 0x00000043 # macro +SQ_S_BUFFER_ATOMIC_SMIN = 0x00000044 # macro +SQ_S_BUFFER_ATOMIC_UMIN = 0x00000045 # macro +SQ_S_BUFFER_ATOMIC_SMAX = 0x00000046 # macro +SQ_S_BUFFER_ATOMIC_UMAX = 0x00000047 # macro +SQ_S_BUFFER_ATOMIC_AND = 0x00000048 # macro +SQ_S_BUFFER_ATOMIC_OR = 0x00000049 # macro +SQ_S_BUFFER_ATOMIC_XOR = 0x0000004a # macro +SQ_S_BUFFER_ATOMIC_INC = 0x0000004b # macro +SQ_S_BUFFER_ATOMIC_DEC = 0x0000004c # macro +SQ_S_BUFFER_ATOMIC_SWAP_X2 = 0x00000060 # macro +SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro +SQ_S_BUFFER_ATOMIC_ADD_X2 = 0x00000062 # macro +SQ_S_BUFFER_ATOMIC_SUB_X2 = 0x00000063 # macro +SQ_S_BUFFER_ATOMIC_SMIN_X2 = 0x00000064 # macro +SQ_S_BUFFER_ATOMIC_UMIN_X2 = 0x00000065 # macro +SQ_S_BUFFER_ATOMIC_SMAX_X2 = 0x00000066 # macro +SQ_S_BUFFER_ATOMIC_UMAX_X2 = 0x00000067 # macro +SQ_S_BUFFER_ATOMIC_AND_X2 = 0x00000068 # macro +SQ_S_BUFFER_ATOMIC_OR_X2 = 0x00000069 # macro +SQ_S_BUFFER_ATOMIC_XOR_X2 = 0x0000006a # macro +SQ_S_BUFFER_ATOMIC_INC_X2 = 0x0000006b # macro +SQ_S_BUFFER_ATOMIC_DEC_X2 = 0x0000006c # macro +SQ_S_ATOMIC_SWAP = 0x00000080 # macro +SQ_S_ATOMIC_CMPSWAP = 0x00000081 # macro +SQ_S_ATOMIC_ADD = 0x00000082 # macro +SQ_S_ATOMIC_SUB = 0x00000083 # macro +SQ_S_ATOMIC_SMIN = 0x00000084 # macro +SQ_S_ATOMIC_UMIN = 0x00000085 # macro +SQ_S_ATOMIC_SMAX = 0x00000086 # macro +SQ_S_ATOMIC_UMAX = 0x00000087 # macro +SQ_S_ATOMIC_AND = 0x00000088 # macro +SQ_S_ATOMIC_OR = 0x00000089 # macro +SQ_S_ATOMIC_XOR = 0x0000008a # macro +SQ_S_ATOMIC_INC = 0x0000008b # macro +SQ_S_ATOMIC_DEC = 0x0000008c # macro +SQ_S_ATOMIC_SWAP_X2 = 0x000000a0 # macro +SQ_S_ATOMIC_CMPSWAP_X2 = 0x000000a1 # macro +SQ_S_ATOMIC_ADD_X2 = 0x000000a2 # macro +SQ_S_ATOMIC_SUB_X2 = 0x000000a3 # macro +SQ_S_ATOMIC_SMIN_X2 = 0x000000a4 # macro +SQ_S_ATOMIC_UMIN_X2 = 0x000000a5 # macro +SQ_S_ATOMIC_SMAX_X2 = 0x000000a6 # macro +SQ_S_ATOMIC_UMAX_X2 = 0x000000a7 # macro +SQ_S_ATOMIC_AND_X2 = 0x000000a8 # macro +SQ_S_ATOMIC_OR_X2 = 0x000000a9 # macro +SQ_S_ATOMIC_XOR_X2 = 0x000000aa # macro +SQ_S_ATOMIC_INC_X2 = 0x000000ab # macro +SQ_S_ATOMIC_DEC_X2 = 0x000000ac # macro +SQ_V_CNDMASK_B32 = 0x00000000 # macro +SQ_V_ADD_F32 = 0x00000001 # macro +SQ_V_SUB_F32 = 0x00000002 # macro +SQ_V_SUBREV_F32 = 0x00000003 # macro +SQ_V_MUL_LEGACY_F32 = 0x00000004 # macro +SQ_V_MUL_F32 = 0x00000005 # macro +SQ_V_MUL_I32_I24 = 0x00000006 # macro +SQ_V_MUL_HI_I32_I24 = 0x00000007 # macro +SQ_V_MUL_U32_U24 = 0x00000008 # macro +SQ_V_MUL_HI_U32_U24 = 0x00000009 # macro +SQ_V_MIN_F32 = 0x0000000a # macro +SQ_V_MAX_F32 = 0x0000000b # macro +SQ_V_MIN_I32 = 0x0000000c # macro +SQ_V_MAX_I32 = 0x0000000d # macro +SQ_V_MIN_U32 = 0x0000000e # macro +SQ_V_MAX_U32 = 0x0000000f # macro +SQ_V_LSHRREV_B32 = 0x00000010 # macro +SQ_V_ASHRREV_I32 = 0x00000011 # macro +SQ_V_LSHLREV_B32 = 0x00000012 # macro +SQ_V_AND_B32 = 0x00000013 # macro +SQ_V_OR_B32 = 0x00000014 # macro +SQ_V_XOR_B32 = 0x00000015 # macro +SQ_V_MAC_F32 = 0x00000016 # macro +SQ_V_MADMK_F32 = 0x00000017 # macro +SQ_V_MADAK_F32 = 0x00000018 # macro +SQ_V_ADD_CO_U32 = 0x00000019 # macro +SQ_V_SUB_CO_U32 = 0x0000001a # macro +SQ_V_SUBREV_CO_U32 = 0x0000001b # macro +SQ_V_ADDC_CO_U32 = 0x0000001c # macro +SQ_V_SUBB_CO_U32 = 0x0000001d # macro +SQ_V_SUBBREV_CO_U32 = 0x0000001e # macro +SQ_V_ADD_F16 = 0x0000001f # macro +SQ_V_SUB_F16 = 0x00000020 # macro +SQ_V_SUBREV_F16 = 0x00000021 # macro +SQ_V_MUL_F16 = 0x00000022 # macro +SQ_V_MAC_F16 = 0x00000023 # macro +SQ_V_MADMK_F16 = 0x00000024 # macro +SQ_V_MADAK_F16 = 0x00000025 # macro +SQ_V_ADD_U16 = 0x00000026 # macro +SQ_V_SUB_U16 = 0x00000027 # macro +SQ_V_SUBREV_U16 = 0x00000028 # macro +SQ_V_MUL_LO_U16 = 0x00000029 # macro +SQ_V_LSHLREV_B16 = 0x0000002a # macro +SQ_V_LSHRREV_B16 = 0x0000002b # macro +SQ_V_ASHRREV_I16 = 0x0000002c # macro +SQ_V_MAX_F16 = 0x0000002d # macro +SQ_V_MIN_F16 = 0x0000002e # macro +SQ_V_MAX_U16 = 0x0000002f # macro +SQ_V_MAX_I16 = 0x00000030 # macro +SQ_V_MIN_U16 = 0x00000031 # macro +SQ_V_MIN_I16 = 0x00000032 # macro +SQ_V_LDEXP_F16 = 0x00000033 # macro +SQ_V_ADD_U32 = 0x00000034 # macro +SQ_V_SUB_U32 = 0x00000035 # macro +SQ_V_SUBREV_U32 = 0x00000036 # macro +SQ_SYSMSG_OP_ECC_ERR_INTERRUPT = 0x00000001 # macro +SQ_SYSMSG_OP_REG_RD = 0x00000002 # macro +SQ_SYSMSG_OP_HOST_TRAP_ACK = 0x00000003 # macro +SQ_SYSMSG_OP_TTRACE_PC = 0x00000004 # macro +SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT = 0x00000005 # macro +SQ_SYSMSG_OP_MEMVIOL_INTERRUPT = 0x00000006 # macro +SQ_SRC_VCCZ = 0x000000fb # macro +SQ_CHAN_X = 0x00000000 # macro +SQ_CHAN_Y = 0x00000001 # macro +SQ_CHAN_Z = 0x00000002 # macro +SQ_CHAN_W = 0x00000003 # macro +SQ_S_MOVK_I32 = 0x00000000 # macro +SQ_S_CMOVK_I32 = 0x00000001 # macro +SQ_S_CMPK_EQ_I32 = 0x00000002 # macro +SQ_S_CMPK_LG_I32 = 0x00000003 # macro +SQ_S_CMPK_GT_I32 = 0x00000004 # macro +SQ_S_CMPK_GE_I32 = 0x00000005 # macro +SQ_S_CMPK_LT_I32 = 0x00000006 # macro +SQ_S_CMPK_LE_I32 = 0x00000007 # macro +SQ_S_CMPK_EQ_U32 = 0x00000008 # macro +SQ_S_CMPK_LG_U32 = 0x00000009 # macro +SQ_S_CMPK_GT_U32 = 0x0000000a # macro +SQ_S_CMPK_GE_U32 = 0x0000000b # macro +SQ_S_CMPK_LT_U32 = 0x0000000c # macro +SQ_S_CMPK_LE_U32 = 0x0000000d # macro +SQ_S_ADDK_I32 = 0x0000000e # macro +SQ_S_MULK_I32 = 0x0000000f # macro +SQ_S_CBRANCH_I_FORK = 0x00000010 # macro +SQ_S_GETREG_B32 = 0x00000011 # macro +SQ_S_SETREG_B32 = 0x00000012 # macro +SQ_S_GETREG_REGRD_B32 = 0x00000013 # macro +SQ_S_SETREG_IMM32_B32 = 0x00000014 # macro +SQ_S_CALL_B64 = 0x00000015 # macro +SQ_L1 = 0x00000001 # macro +SQ_L2 = 0x00000002 # macro +SQ_L3 = 0x00000003 # macro +SQ_L4 = 0x00000004 # macro +SQ_L5 = 0x00000005 # macro +SQ_L6 = 0x00000006 # macro +SQ_L7 = 0x00000007 # macro +SQ_L8 = 0x00000008 # macro +SQ_L9 = 0x00000009 # macro +SQ_L10 = 0x0000000a # macro +SQ_L11 = 0x0000000b # macro +SQ_L12 = 0x0000000c # macro +SQ_L13 = 0x0000000d # macro +SQ_L14 = 0x0000000e # macro +SQ_L15 = 0x0000000f # macro +SQ_SGPR0 = 0x00000000 # macro +SQ_V_PK_MAD_I16 = 0x00000000 # macro +SQ_V_PK_MUL_LO_U16 = 0x00000001 # macro +SQ_V_PK_ADD_I16 = 0x00000002 # macro +SQ_V_PK_SUB_I16 = 0x00000003 # macro +SQ_V_PK_LSHLREV_B16 = 0x00000004 # macro +SQ_V_PK_LSHRREV_B16 = 0x00000005 # macro +SQ_V_PK_ASHRREV_I16 = 0x00000006 # macro +SQ_V_PK_MAX_I16 = 0x00000007 # macro +SQ_V_PK_MIN_I16 = 0x00000008 # macro +SQ_V_PK_MAD_U16 = 0x00000009 # macro +SQ_V_PK_ADD_U16 = 0x0000000a # macro +SQ_V_PK_SUB_U16 = 0x0000000b # macro +SQ_V_PK_MAX_U16 = 0x0000000c # macro +SQ_V_PK_MIN_U16 = 0x0000000d # macro +SQ_V_PK_MAD_F16 = 0x0000000e # macro +SQ_V_PK_ADD_F16 = 0x0000000f # macro +SQ_V_PK_MUL_F16 = 0x00000010 # macro +SQ_V_PK_MIN_F16 = 0x00000011 # macro +SQ_V_PK_MAX_F16 = 0x00000012 # macro +SQ_V_MAD_MIX_F32 = 0x00000020 # macro +SQ_V_MAD_MIXLO_F16 = 0x00000021 # macro +SQ_V_MAD_MIXHI_F16 = 0x00000022 # macro +SQ_V_INTERP_P1_F32 = 0x00000000 # macro +SQ_V_INTERP_P2_F32 = 0x00000001 # macro +SQ_V_INTERP_MOV_F32 = 0x00000002 # macro +SQ_R1 = 0x00000001 # macro +SQ_R2 = 0x00000002 # macro +SQ_R3 = 0x00000003 # macro +SQ_R4 = 0x00000004 # macro +SQ_R5 = 0x00000005 # macro +SQ_R6 = 0x00000006 # macro +SQ_R7 = 0x00000007 # macro +SQ_R8 = 0x00000008 # macro +SQ_R9 = 0x00000009 # macro +SQ_R10 = 0x0000000a # macro +SQ_R11 = 0x0000000b # macro +SQ_R12 = 0x0000000c # macro +SQ_R13 = 0x0000000d # macro +SQ_R14 = 0x0000000e # macro +SQ_R15 = 0x0000000f # macro +SQ_S_ADD_U32 = 0x00000000 # macro +SQ_S_SUB_U32 = 0x00000001 # macro +SQ_S_ADD_I32 = 0x00000002 # macro +SQ_S_SUB_I32 = 0x00000003 # macro +SQ_S_ADDC_U32 = 0x00000004 # macro +SQ_S_SUBB_U32 = 0x00000005 # macro +SQ_S_MIN_I32 = 0x00000006 # macro +SQ_S_MIN_U32 = 0x00000007 # macro +SQ_S_MAX_I32 = 0x00000008 # macro +SQ_S_MAX_U32 = 0x00000009 # macro +SQ_S_CSELECT_B32 = 0x0000000a # macro +SQ_S_CSELECT_B64 = 0x0000000b # macro +SQ_S_AND_B32 = 0x0000000c # macro +SQ_S_AND_B64 = 0x0000000d # macro +SQ_S_OR_B32 = 0x0000000e # macro +SQ_S_OR_B64 = 0x0000000f # macro +SQ_S_XOR_B32 = 0x00000010 # macro +SQ_S_XOR_B64 = 0x00000011 # macro +SQ_S_ANDN2_B32 = 0x00000012 # macro +SQ_S_ANDN2_B64 = 0x00000013 # macro +SQ_S_ORN2_B32 = 0x00000014 # macro +SQ_S_ORN2_B64 = 0x00000015 # macro +SQ_S_NAND_B32 = 0x00000016 # macro +SQ_S_NAND_B64 = 0x00000017 # macro +SQ_S_NOR_B32 = 0x00000018 # macro +SQ_S_NOR_B64 = 0x00000019 # macro +SQ_S_XNOR_B32 = 0x0000001a # macro +SQ_S_XNOR_B64 = 0x0000001b # macro +SQ_S_LSHL_B32 = 0x0000001c # macro +SQ_S_LSHL_B64 = 0x0000001d # macro +SQ_S_LSHR_B32 = 0x0000001e # macro +SQ_S_LSHR_B64 = 0x0000001f # macro +SQ_S_ASHR_I32 = 0x00000020 # macro +SQ_S_ASHR_I64 = 0x00000021 # macro +SQ_S_BFM_B32 = 0x00000022 # macro +SQ_S_BFM_B64 = 0x00000023 # macro +SQ_S_MUL_I32 = 0x00000024 # macro +SQ_S_BFE_U32 = 0x00000025 # macro +SQ_S_BFE_I32 = 0x00000026 # macro +SQ_S_BFE_U64 = 0x00000027 # macro +SQ_S_BFE_I64 = 0x00000028 # macro +SQ_S_CBRANCH_G_FORK = 0x00000029 # macro +SQ_S_ABSDIFF_I32 = 0x0000002a # macro +SQ_S_RFE_RESTORE_B64 = 0x0000002b # macro +SQ_S_MUL_HI_U32 = 0x0000002c # macro +SQ_S_MUL_HI_I32 = 0x0000002d # macro +SQ_S_LSHL1_ADD_U32 = 0x0000002e # macro +SQ_S_LSHL2_ADD_U32 = 0x0000002f # macro +SQ_S_LSHL3_ADD_U32 = 0x00000030 # macro +SQ_S_LSHL4_ADD_U32 = 0x00000031 # macro +SQ_S_PACK_LL_B32_B16 = 0x00000032 # macro +SQ_S_PACK_LH_B32_B16 = 0x00000033 # macro +SQ_S_PACK_HH_B32_B16 = 0x00000034 # macro +SQ_FLAT = 0x00000000 # macro +SQ_SCRATCH = 0x00000001 # macro +SQ_GLOBAL = 0x00000002 # macro +SQ_EXEC_LO = 0x0000007e # macro +SQ_EXEC_HI = 0x0000007f # macro +SQ_SRC_64_INT = 0x000000c0 # macro +SQ_SRC_M_1_INT = 0x000000c1 # macro +SQ_SRC_M_2_INT = 0x000000c2 # macro +SQ_SRC_M_3_INT = 0x000000c3 # macro +SQ_SRC_M_4_INT = 0x000000c4 # macro +SQ_SRC_M_5_INT = 0x000000c5 # macro +SQ_SRC_M_6_INT = 0x000000c6 # macro +SQ_SRC_M_7_INT = 0x000000c7 # macro +SQ_SRC_M_8_INT = 0x000000c8 # macro +SQ_SRC_M_9_INT = 0x000000c9 # macro +SQ_SRC_M_10_INT = 0x000000ca # macro +SQ_SRC_M_11_INT = 0x000000cb # macro +SQ_SRC_M_12_INT = 0x000000cc # macro +SQ_SRC_M_13_INT = 0x000000cd # macro +SQ_SRC_M_14_INT = 0x000000ce # macro +SQ_SRC_M_15_INT = 0x000000cf # macro +SQ_SRC_M_16_INT = 0x000000d0 # macro +SQ_SRC_0_5 = 0x000000f0 # macro +SQ_SRC_M_0_5 = 0x000000f1 # macro +SQ_SRC_1 = 0x000000f2 # macro +SQ_SRC_M_1 = 0x000000f3 # macro +SQ_SRC_2 = 0x000000f4 # macro +SQ_SRC_M_2 = 0x000000f5 # macro +SQ_SRC_4 = 0x000000f6 # macro +SQ_SRC_M_4 = 0x000000f7 # macro +SQ_SRC_INV_2PI = 0x000000f8 # macro +SQ_VCC_LO = 0x0000006a # macro +SQ_VCC_HI = 0x0000006b # macro +SQ_EXP_MRT0 = 0x00000000 # macro +SQ_EXP_MRTZ = 0x00000008 # macro +SQ_EXP_NULL = 0x00000009 # macro +SQ_EXP_POS0 = 0x0000000c # macro +SQ_EXP_PARAM0 = 0x00000020 # macro +SQ_S_NOP = 0x00000000 # macro +SQ_S_ENDPGM = 0x00000001 # macro +SQ_S_BRANCH = 0x00000002 # macro +SQ_S_WAKEUP = 0x00000003 # macro +SQ_S_CBRANCH_SCC0 = 0x00000004 # macro +SQ_S_CBRANCH_SCC1 = 0x00000005 # macro +SQ_S_CBRANCH_VCCZ = 0x00000006 # macro +SQ_S_CBRANCH_VCCNZ = 0x00000007 # macro +SQ_S_CBRANCH_EXECZ = 0x00000008 # macro +SQ_S_CBRANCH_EXECNZ = 0x00000009 # macro +SQ_S_BARRIER = 0x0000000a # macro +SQ_S_SETKILL = 0x0000000b # macro +SQ_S_WAITCNT = 0x0000000c # macro +SQ_S_SETHALT = 0x0000000d # macro +SQ_S_SLEEP = 0x0000000e # macro +SQ_S_SETPRIO = 0x0000000f # macro +SQ_S_SENDMSG = 0x00000010 # macro +SQ_S_SENDMSGHALT = 0x00000011 # macro +SQ_S_TRAP = 0x00000012 # macro +SQ_S_ICACHE_INV = 0x00000013 # macro +SQ_S_INCPERFLEVEL = 0x00000014 # macro +SQ_S_DECPERFLEVEL = 0x00000015 # macro +SQ_S_TTRACEDATA = 0x00000016 # macro +SQ_S_CBRANCH_CDBGSYS = 0x00000017 # macro +SQ_S_CBRANCH_CDBGUSER = 0x00000018 # macro +SQ_S_CBRANCH_CDBGSYS_OR_USER = 0x00000019 # macro +SQ_S_CBRANCH_CDBGSYS_AND_USER = 0x0000001a # macro +SQ_S_ENDPGM_SAVED = 0x0000001b # macro +SQ_S_SET_GPR_IDX_OFF = 0x0000001c # macro +SQ_S_SET_GPR_IDX_MODE = 0x0000001d # macro +SQ_S_ENDPGM_ORDERED_PS_DONE = 0x0000001e # macro +SQ_EXP = 0x00000000 # macro +SQ_SRC_POPS_EXITING_WAVE_ID = 0x000000ef # macro +SQ_XNACK_MASK_LO = 0x00000068 # macro +SQ_XNACK_MASK_HI = 0x00000069 # macro +SQ_OMOD_OFF = 0x00000000 # macro +SQ_OMOD_M2 = 0x00000001 # macro +SQ_OMOD_M4 = 0x00000002 # macro +SQ_OMOD_D2 = 0x00000003 # macro +SQ_SRC_EXECZ = 0x000000fc # macro +SQ_F = 0x00000000 # macro +SQ_LT = 0x00000001 # macro +SQ_EQ = 0x00000002 # macro +SQ_LE = 0x00000003 # macro +SQ_GT = 0x00000004 # macro +SQ_NE = 0x00000005 # macro +SQ_GE = 0x00000006 # macro +SQ_T = 0x00000007 # macro +SQ_DPP_BOUND_OFF = 0x00000000 # macro +SQ_DPP_BOUND_ZERO = 0x00000001 # macro +SQ_M0 = 0x0000007c # macro +SQ_MSG_INTERRUPT = 0x00000001 # macro +SQ_MSG_GS = 0x00000002 # macro +SQ_MSG_GS_DONE = 0x00000003 # macro +SQ_MSG_SAVEWAVE = 0x00000004 # macro +SQ_MSG_STALL_WAVE_GEN = 0x00000005 # macro +SQ_MSG_HALT_WAVES = 0x00000006 # macro +SQ_MSG_ORDERED_PS_DONE = 0x00000007 # macro +SQ_MSG_EARLY_PRIM_DEALLOC = 0x00000008 # macro +SQ_MSG_GS_ALLOC_REQ = 0x00000009 # macro +SQ_MSG_SYSMSG = 0x0000000f # macro +SQ_PARAM_P10 = 0x00000000 # macro +SQ_PARAM_P20 = 0x00000001 # macro +SQ_PARAM_P0 = 0x00000002 # macro +SQ_V_OPC_OFFSET = 0x00000000 # macro +SQ_V_OP2_OFFSET = 0x00000100 # macro +SQ_V_OP1_OFFSET = 0x00000140 # macro +SQ_V_INTRP_OFFSET = 0x00000270 # macro +SQ_V_OP3P_OFFSET = 0x00000380 # macro +SQ_SRC_SDWA = 0x000000f9 # macro +SQ_SRC_SHARED_BASE = 0x000000eb # macro +SQ_SRC_SHARED_LIMIT = 0x000000ec # macro +SQ_SRC_PRIVATE_BASE = 0x000000ed # macro +SQ_SRC_PRIVATE_LIMIT = 0x000000ee # macro +SQ_LG = 0x00000005 # macro +SQ_O = 0x00000007 # macro +SQ_U = 0x00000008 # macro +SQ_NGE = 0x00000009 # macro +SQ_NLG = 0x0000000a # macro +SQ_NGT = 0x0000000b # macro +SQ_NLE = 0x0000000c # macro +SQ_NEQ = 0x0000000d # macro +SQ_NLT = 0x0000000e # macro +SQ_TRU = 0x0000000f # macro +SQ_SDWA_UNUSED_PAD = 0x00000000 # macro +SQ_SDWA_UNUSED_SEXT = 0x00000001 # macro +SQ_SDWA_UNUSED_PRESERVE = 0x00000002 # macro +SQ_SRC_SCC = 0x000000fd # macro +SQ_V_CMP_CLASS_F32 = 0x00000010 # macro +SQ_V_CMPX_CLASS_F32 = 0x00000011 # macro +SQ_V_CMP_CLASS_F64 = 0x00000012 # macro +SQ_V_CMPX_CLASS_F64 = 0x00000013 # macro +SQ_V_CMP_CLASS_F16 = 0x00000014 # macro +SQ_V_CMPX_CLASS_F16 = 0x00000015 # macro +SQ_V_CMP_F_F16 = 0x00000020 # macro +SQ_V_CMP_LT_F16 = 0x00000021 # macro +SQ_V_CMP_EQ_F16 = 0x00000022 # macro +SQ_V_CMP_LE_F16 = 0x00000023 # macro +SQ_V_CMP_GT_F16 = 0x00000024 # macro +SQ_V_CMP_LG_F16 = 0x00000025 # macro +SQ_V_CMP_GE_F16 = 0x00000026 # macro +SQ_V_CMP_O_F16 = 0x00000027 # macro +SQ_V_CMP_U_F16 = 0x00000028 # macro +SQ_V_CMP_NGE_F16 = 0x00000029 # macro +SQ_V_CMP_NLG_F16 = 0x0000002a # macro +SQ_V_CMP_NGT_F16 = 0x0000002b # macro +SQ_V_CMP_NLE_F16 = 0x0000002c # macro +SQ_V_CMP_NEQ_F16 = 0x0000002d # macro +SQ_V_CMP_NLT_F16 = 0x0000002e # macro +SQ_V_CMP_TRU_F16 = 0x0000002f # macro +SQ_V_CMPX_F_F16 = 0x00000030 # macro +SQ_V_CMPX_LT_F16 = 0x00000031 # macro +SQ_V_CMPX_EQ_F16 = 0x00000032 # macro +SQ_V_CMPX_LE_F16 = 0x00000033 # macro +SQ_V_CMPX_GT_F16 = 0x00000034 # macro +SQ_V_CMPX_LG_F16 = 0x00000035 # macro +SQ_V_CMPX_GE_F16 = 0x00000036 # macro +SQ_V_CMPX_O_F16 = 0x00000037 # macro +SQ_V_CMPX_U_F16 = 0x00000038 # macro +SQ_V_CMPX_NGE_F16 = 0x00000039 # macro +SQ_V_CMPX_NLG_F16 = 0x0000003a # macro +SQ_V_CMPX_NGT_F16 = 0x0000003b # macro +SQ_V_CMPX_NLE_F16 = 0x0000003c # macro +SQ_V_CMPX_NEQ_F16 = 0x0000003d # macro +SQ_V_CMPX_NLT_F16 = 0x0000003e # macro +SQ_V_CMPX_TRU_F16 = 0x0000003f # macro +SQ_V_CMP_F_F32 = 0x00000040 # macro +SQ_V_CMP_LT_F32 = 0x00000041 # macro +SQ_V_CMP_EQ_F32 = 0x00000042 # macro +SQ_V_CMP_LE_F32 = 0x00000043 # macro +SQ_V_CMP_GT_F32 = 0x00000044 # macro +SQ_V_CMP_LG_F32 = 0x00000045 # macro +SQ_V_CMP_GE_F32 = 0x00000046 # macro +SQ_V_CMP_O_F32 = 0x00000047 # macro +SQ_V_CMP_U_F32 = 0x00000048 # macro +SQ_V_CMP_NGE_F32 = 0x00000049 # macro +SQ_V_CMP_NLG_F32 = 0x0000004a # macro +SQ_V_CMP_NGT_F32 = 0x0000004b # macro +SQ_V_CMP_NLE_F32 = 0x0000004c # macro +SQ_V_CMP_NEQ_F32 = 0x0000004d # macro +SQ_V_CMP_NLT_F32 = 0x0000004e # macro +SQ_V_CMP_TRU_F32 = 0x0000004f # macro +SQ_V_CMPX_F_F32 = 0x00000050 # macro +SQ_V_CMPX_LT_F32 = 0x00000051 # macro +SQ_V_CMPX_EQ_F32 = 0x00000052 # macro +SQ_V_CMPX_LE_F32 = 0x00000053 # macro +SQ_V_CMPX_GT_F32 = 0x00000054 # macro +SQ_V_CMPX_LG_F32 = 0x00000055 # macro +SQ_V_CMPX_GE_F32 = 0x00000056 # macro +SQ_V_CMPX_O_F32 = 0x00000057 # macro +SQ_V_CMPX_U_F32 = 0x00000058 # macro +SQ_V_CMPX_NGE_F32 = 0x00000059 # macro +SQ_V_CMPX_NLG_F32 = 0x0000005a # macro +SQ_V_CMPX_NGT_F32 = 0x0000005b # macro +SQ_V_CMPX_NLE_F32 = 0x0000005c # macro +SQ_V_CMPX_NEQ_F32 = 0x0000005d # macro +SQ_V_CMPX_NLT_F32 = 0x0000005e # macro +SQ_V_CMPX_TRU_F32 = 0x0000005f # macro +SQ_V_CMP_F_F64 = 0x00000060 # macro +SQ_V_CMP_LT_F64 = 0x00000061 # macro +SQ_V_CMP_EQ_F64 = 0x00000062 # macro +SQ_V_CMP_LE_F64 = 0x00000063 # macro +SQ_V_CMP_GT_F64 = 0x00000064 # macro +SQ_V_CMP_LG_F64 = 0x00000065 # macro +SQ_V_CMP_GE_F64 = 0x00000066 # macro +SQ_V_CMP_O_F64 = 0x00000067 # macro +SQ_V_CMP_U_F64 = 0x00000068 # macro +SQ_V_CMP_NGE_F64 = 0x00000069 # macro +SQ_V_CMP_NLG_F64 = 0x0000006a # macro +SQ_V_CMP_NGT_F64 = 0x0000006b # macro +SQ_V_CMP_NLE_F64 = 0x0000006c # macro +SQ_V_CMP_NEQ_F64 = 0x0000006d # macro +SQ_V_CMP_NLT_F64 = 0x0000006e # macro +SQ_V_CMP_TRU_F64 = 0x0000006f # macro +SQ_V_CMPX_F_F64 = 0x00000070 # macro +SQ_V_CMPX_LT_F64 = 0x00000071 # macro +SQ_V_CMPX_EQ_F64 = 0x00000072 # macro +SQ_V_CMPX_LE_F64 = 0x00000073 # macro +SQ_V_CMPX_GT_F64 = 0x00000074 # macro +SQ_V_CMPX_LG_F64 = 0x00000075 # macro +SQ_V_CMPX_GE_F64 = 0x00000076 # macro +SQ_V_CMPX_O_F64 = 0x00000077 # macro +SQ_V_CMPX_U_F64 = 0x00000078 # macro +SQ_V_CMPX_NGE_F64 = 0x00000079 # macro +SQ_V_CMPX_NLG_F64 = 0x0000007a # macro +SQ_V_CMPX_NGT_F64 = 0x0000007b # macro +SQ_V_CMPX_NLE_F64 = 0x0000007c # macro +SQ_V_CMPX_NEQ_F64 = 0x0000007d # macro +SQ_V_CMPX_NLT_F64 = 0x0000007e # macro +SQ_V_CMPX_TRU_F64 = 0x0000007f # macro +SQ_V_CMP_F_I16 = 0x000000a0 # macro +SQ_V_CMP_LT_I16 = 0x000000a1 # macro +SQ_V_CMP_EQ_I16 = 0x000000a2 # macro +SQ_V_CMP_LE_I16 = 0x000000a3 # macro +SQ_V_CMP_GT_I16 = 0x000000a4 # macro +SQ_V_CMP_NE_I16 = 0x000000a5 # macro +SQ_V_CMP_GE_I16 = 0x000000a6 # macro +SQ_V_CMP_T_I16 = 0x000000a7 # macro +SQ_V_CMP_F_U16 = 0x000000a8 # macro +SQ_V_CMP_LT_U16 = 0x000000a9 # macro +SQ_V_CMP_EQ_U16 = 0x000000aa # macro +SQ_V_CMP_LE_U16 = 0x000000ab # macro +SQ_V_CMP_GT_U16 = 0x000000ac # macro +SQ_V_CMP_NE_U16 = 0x000000ad # macro +SQ_V_CMP_GE_U16 = 0x000000ae # macro +SQ_V_CMP_T_U16 = 0x000000af # macro +SQ_V_CMPX_F_I16 = 0x000000b0 # macro +SQ_V_CMPX_LT_I16 = 0x000000b1 # macro +SQ_V_CMPX_EQ_I16 = 0x000000b2 # macro +SQ_V_CMPX_LE_I16 = 0x000000b3 # macro +SQ_V_CMPX_GT_I16 = 0x000000b4 # macro +SQ_V_CMPX_NE_I16 = 0x000000b5 # macro +SQ_V_CMPX_GE_I16 = 0x000000b6 # macro +SQ_V_CMPX_T_I16 = 0x000000b7 # macro +SQ_V_CMPX_F_U16 = 0x000000b8 # macro +SQ_V_CMPX_LT_U16 = 0x000000b9 # macro +SQ_V_CMPX_EQ_U16 = 0x000000ba # macro +SQ_V_CMPX_LE_U16 = 0x000000bb # macro +SQ_V_CMPX_GT_U16 = 0x000000bc # macro +SQ_V_CMPX_NE_U16 = 0x000000bd # macro +SQ_V_CMPX_GE_U16 = 0x000000be # macro +SQ_V_CMPX_T_U16 = 0x000000bf # macro +SQ_V_CMP_F_I32 = 0x000000c0 # macro +SQ_V_CMP_LT_I32 = 0x000000c1 # macro +SQ_V_CMP_EQ_I32 = 0x000000c2 # macro +SQ_V_CMP_LE_I32 = 0x000000c3 # macro +SQ_V_CMP_GT_I32 = 0x000000c4 # macro +SQ_V_CMP_NE_I32 = 0x000000c5 # macro +SQ_V_CMP_GE_I32 = 0x000000c6 # macro +SQ_V_CMP_T_I32 = 0x000000c7 # macro +SQ_V_CMP_F_U32 = 0x000000c8 # macro +SQ_V_CMP_LT_U32 = 0x000000c9 # macro +SQ_V_CMP_EQ_U32 = 0x000000ca # macro +SQ_V_CMP_LE_U32 = 0x000000cb # macro +SQ_V_CMP_GT_U32 = 0x000000cc # macro +SQ_V_CMP_NE_U32 = 0x000000cd # macro +SQ_V_CMP_GE_U32 = 0x000000ce # macro +SQ_V_CMP_T_U32 = 0x000000cf # macro +SQ_V_CMPX_F_I32 = 0x000000d0 # macro +SQ_V_CMPX_LT_I32 = 0x000000d1 # macro +SQ_V_CMPX_EQ_I32 = 0x000000d2 # macro +SQ_V_CMPX_LE_I32 = 0x000000d3 # macro +SQ_V_CMPX_GT_I32 = 0x000000d4 # macro +SQ_V_CMPX_NE_I32 = 0x000000d5 # macro +SQ_V_CMPX_GE_I32 = 0x000000d6 # macro +SQ_V_CMPX_T_I32 = 0x000000d7 # macro +SQ_V_CMPX_F_U32 = 0x000000d8 # macro +SQ_V_CMPX_LT_U32 = 0x000000d9 # macro +SQ_V_CMPX_EQ_U32 = 0x000000da # macro +SQ_V_CMPX_LE_U32 = 0x000000db # macro +SQ_V_CMPX_GT_U32 = 0x000000dc # macro +SQ_V_CMPX_NE_U32 = 0x000000dd # macro +SQ_V_CMPX_GE_U32 = 0x000000de # macro +SQ_V_CMPX_T_U32 = 0x000000df # macro +SQ_V_CMP_F_I64 = 0x000000e0 # macro +SQ_V_CMP_LT_I64 = 0x000000e1 # macro +SQ_V_CMP_EQ_I64 = 0x000000e2 # macro +SQ_V_CMP_LE_I64 = 0x000000e3 # macro +SQ_V_CMP_GT_I64 = 0x000000e4 # macro +SQ_V_CMP_NE_I64 = 0x000000e5 # macro +SQ_V_CMP_GE_I64 = 0x000000e6 # macro +SQ_V_CMP_T_I64 = 0x000000e7 # macro +SQ_V_CMP_F_U64 = 0x000000e8 # macro +SQ_V_CMP_LT_U64 = 0x000000e9 # macro +SQ_V_CMP_EQ_U64 = 0x000000ea # macro +SQ_V_CMP_LE_U64 = 0x000000eb # macro +SQ_V_CMP_GT_U64 = 0x000000ec # macro +SQ_V_CMP_NE_U64 = 0x000000ed # macro +SQ_V_CMP_GE_U64 = 0x000000ee # macro +SQ_V_CMP_T_U64 = 0x000000ef # macro +SQ_V_CMPX_F_I64 = 0x000000f0 # macro +SQ_V_CMPX_LT_I64 = 0x000000f1 # macro +SQ_V_CMPX_EQ_I64 = 0x000000f2 # macro +SQ_V_CMPX_LE_I64 = 0x000000f3 # macro +SQ_V_CMPX_GT_I64 = 0x000000f4 # macro +SQ_V_CMPX_NE_I64 = 0x000000f5 # macro +SQ_V_CMPX_GE_I64 = 0x000000f6 # macro +SQ_V_CMPX_T_I64 = 0x000000f7 # macro +SQ_V_CMPX_F_U64 = 0x000000f8 # macro +SQ_V_CMPX_LT_U64 = 0x000000f9 # macro +SQ_V_CMPX_EQ_U64 = 0x000000fa # macro +SQ_V_CMPX_LE_U64 = 0x000000fb # macro +SQ_V_CMPX_GT_U64 = 0x000000fc # macro +SQ_V_CMPX_NE_U64 = 0x000000fd # macro +SQ_V_CMPX_GE_U64 = 0x000000fe # macro +SQ_V_CMPX_T_U64 = 0x000000ff # macro +SQ_GS_OP_NOP = 0x00000000 # macro +SQ_GS_OP_CUT = 0x00000001 # macro +SQ_GS_OP_EMIT = 0x00000002 # macro +SQ_GS_OP_EMIT_CUT = 0x00000003 # macro +SQ_SRC_LDS_DIRECT = 0x000000fe # macro +SQ_ATTR0 = 0x00000000 # macro +SQ_EXP_GDS0 = 0x00000018 # macro +SQ_S_CMP_EQ_I32 = 0x00000000 # macro +SQ_S_CMP_LG_I32 = 0x00000001 # macro +SQ_S_CMP_GT_I32 = 0x00000002 # macro +SQ_S_CMP_GE_I32 = 0x00000003 # macro +SQ_S_CMP_LT_I32 = 0x00000004 # macro +SQ_S_CMP_LE_I32 = 0x00000005 # macro +SQ_S_CMP_EQ_U32 = 0x00000006 # macro +SQ_S_CMP_LG_U32 = 0x00000007 # macro +SQ_S_CMP_GT_U32 = 0x00000008 # macro +SQ_S_CMP_GE_U32 = 0x00000009 # macro +SQ_S_CMP_LT_U32 = 0x0000000a # macro +SQ_S_CMP_LE_U32 = 0x0000000b # macro +SQ_S_BITCMP0_B32 = 0x0000000c # macro +SQ_S_BITCMP1_B32 = 0x0000000d # macro +SQ_S_BITCMP0_B64 = 0x0000000e # macro +SQ_S_BITCMP1_B64 = 0x0000000f # macro +SQ_S_SETVSKIP = 0x00000010 # macro +SQ_S_SET_GPR_IDX_ON = 0x00000011 # macro +SQ_S_CMP_EQ_U64 = 0x00000012 # macro +SQ_S_CMP_LG_U64 = 0x00000013 # macro +SQ_TTMP0 = 0x0000006c # macro +SQ_TTMP1 = 0x0000006d # macro +SQ_TTMP2 = 0x0000006e # macro +SQ_TTMP3 = 0x0000006f # macro +SQ_TTMP4 = 0x00000070 # macro +SQ_TTMP5 = 0x00000071 # macro +SQ_TTMP6 = 0x00000072 # macro +SQ_TTMP7 = 0x00000073 # macro +SQ_TTMP8 = 0x00000074 # macro +SQ_TTMP9 = 0x00000075 # macro +SQ_TTMP10 = 0x00000076 # macro +SQ_TTMP11 = 0x00000077 # macro +SQ_TTMP12 = 0x00000078 # macro +SQ_TTMP13 = 0x00000079 # macro +SQ_TTMP14 = 0x0000007a # macro +SQ_TTMP15 = 0x0000007b # macro +SQ_SRC_VGPR0 = 0x00000100 # macro +SQ_BUFFER_LOAD_FORMAT_X = 0x00000000 # macro +SQ_BUFFER_LOAD_FORMAT_XY = 0x00000001 # macro +SQ_BUFFER_LOAD_FORMAT_XYZ = 0x00000002 # macro +SQ_BUFFER_LOAD_FORMAT_XYZW = 0x00000003 # macro +SQ_BUFFER_STORE_FORMAT_X = 0x00000004 # macro +SQ_BUFFER_STORE_FORMAT_XY = 0x00000005 # macro +SQ_BUFFER_STORE_FORMAT_XYZ = 0x00000006 # macro +SQ_BUFFER_STORE_FORMAT_XYZW = 0x00000007 # macro +SQ_BUFFER_LOAD_FORMAT_D16_X = 0x00000008 # macro +SQ_BUFFER_LOAD_FORMAT_D16_XY = 0x00000009 # macro +SQ_BUFFER_LOAD_FORMAT_D16_XYZ = 0x0000000a # macro +SQ_BUFFER_LOAD_FORMAT_D16_XYZW = 0x0000000b # macro +SQ_BUFFER_STORE_FORMAT_D16_X = 0x0000000c # macro +SQ_BUFFER_STORE_FORMAT_D16_XY = 0x0000000d # macro +SQ_BUFFER_STORE_FORMAT_D16_XYZ = 0x0000000e # macro +SQ_BUFFER_STORE_FORMAT_D16_XYZW = 0x0000000f # macro +SQ_BUFFER_LOAD_UBYTE = 0x00000010 # macro +SQ_BUFFER_LOAD_SBYTE = 0x00000011 # macro +SQ_BUFFER_LOAD_USHORT = 0x00000012 # macro +SQ_BUFFER_LOAD_SSHORT = 0x00000013 # macro +SQ_BUFFER_LOAD_DWORD = 0x00000014 # macro +SQ_BUFFER_LOAD_DWORDX2 = 0x00000015 # macro +SQ_BUFFER_LOAD_DWORDX3 = 0x00000016 # macro +SQ_BUFFER_LOAD_DWORDX4 = 0x00000017 # macro +SQ_BUFFER_STORE_BYTE = 0x00000018 # macro +SQ_BUFFER_STORE_SHORT = 0x0000001a # macro +SQ_BUFFER_STORE_DWORD = 0x0000001c # macro +SQ_BUFFER_STORE_DWORDX2 = 0x0000001d # macro +SQ_BUFFER_STORE_DWORDX3 = 0x0000001e # macro +SQ_BUFFER_STORE_DWORDX4 = 0x0000001f # macro +SQ_BUFFER_STORE_LDS_DWORD = 0x0000003d # macro +SQ_BUFFER_WBINVL1 = 0x0000003e # macro +SQ_BUFFER_WBINVL1_VOL = 0x0000003f # macro +SQ_BUFFER_ATOMIC_SWAP = 0x00000040 # macro +SQ_BUFFER_ATOMIC_CMPSWAP = 0x00000041 # macro +SQ_BUFFER_ATOMIC_ADD = 0x00000042 # macro +SQ_BUFFER_ATOMIC_SUB = 0x00000043 # macro +SQ_BUFFER_ATOMIC_SMIN = 0x00000044 # macro +SQ_BUFFER_ATOMIC_UMIN = 0x00000045 # macro +SQ_BUFFER_ATOMIC_SMAX = 0x00000046 # macro +SQ_BUFFER_ATOMIC_UMAX = 0x00000047 # macro +SQ_BUFFER_ATOMIC_AND = 0x00000048 # macro +SQ_BUFFER_ATOMIC_OR = 0x00000049 # macro +SQ_BUFFER_ATOMIC_XOR = 0x0000004a # macro +SQ_BUFFER_ATOMIC_INC = 0x0000004b # macro +SQ_BUFFER_ATOMIC_DEC = 0x0000004c # macro +SQ_BUFFER_ATOMIC_SWAP_X2 = 0x00000060 # macro +SQ_BUFFER_ATOMIC_CMPSWAP_X2 = 0x00000061 # macro +SQ_BUFFER_ATOMIC_ADD_X2 = 0x00000062 # macro +SQ_BUFFER_ATOMIC_SUB_X2 = 0x00000063 # macro +SQ_BUFFER_ATOMIC_SMIN_X2 = 0x00000064 # macro +SQ_BUFFER_ATOMIC_UMIN_X2 = 0x00000065 # macro +SQ_BUFFER_ATOMIC_SMAX_X2 = 0x00000066 # macro +SQ_BUFFER_ATOMIC_UMAX_X2 = 0x00000067 # macro +SQ_BUFFER_ATOMIC_AND_X2 = 0x00000068 # macro +SQ_BUFFER_ATOMIC_OR_X2 = 0x00000069 # macro +SQ_BUFFER_ATOMIC_XOR_X2 = 0x0000006a # macro +SQ_BUFFER_ATOMIC_INC_X2 = 0x0000006b # macro +SQ_BUFFER_ATOMIC_DEC_X2 = 0x0000006c # macro +SQ_SDWA_BYTE_0 = 0x00000000 # macro +SQ_SDWA_BYTE_1 = 0x00000001 # macro +SQ_SDWA_BYTE_2 = 0x00000002 # macro +SQ_SDWA_BYTE_3 = 0x00000003 # macro +SQ_SDWA_WORD_0 = 0x00000004 # macro +SQ_SDWA_WORD_1 = 0x00000005 # macro +SQ_SDWA_DWORD = 0x00000006 # macro +ROM_SIGNATURE = 0x0000aa55 # macro + +# values for enumeration 'GDS_PERFCOUNT_SELECT' +GDS_PERFCOUNT_SELECT__enumvalues = { + 0: 'GDS_PERF_SEL_DS_ADDR_CONFL', + 1: 'GDS_PERF_SEL_DS_BANK_CONFL', + 2: 'GDS_PERF_SEL_WBUF_FLUSH', + 3: 'GDS_PERF_SEL_WR_COMP', + 4: 'GDS_PERF_SEL_WBUF_WR', + 5: 'GDS_PERF_SEL_RBUF_HIT', + 6: 'GDS_PERF_SEL_RBUF_MISS', + 7: 'GDS_PERF_SEL_SE0_SH0_NORET', + 8: 'GDS_PERF_SEL_SE0_SH0_RET', + 9: 'GDS_PERF_SEL_SE0_SH0_ORD_CNT', + 10: 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ', + 11: 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', + 12: 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID', + 13: 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD', + 14: 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', + 15: 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP', + 16: 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP', + 17: 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP', + 18: 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP', + 19: 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP', + 20: 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP', + 21: 'GDS_PERF_SEL_SE0_SH1_NORET', + 22: 'GDS_PERF_SEL_SE0_SH1_RET', + 23: 'GDS_PERF_SEL_SE0_SH1_ORD_CNT', + 24: 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ', + 25: 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', + 26: 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID', + 27: 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD', + 28: 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', + 29: 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP', + 30: 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP', + 31: 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP', + 32: 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP', + 33: 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP', + 34: 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP', + 35: 'GDS_PERF_SEL_SE1_SH0_NORET', + 36: 'GDS_PERF_SEL_SE1_SH0_RET', + 37: 'GDS_PERF_SEL_SE1_SH0_ORD_CNT', + 38: 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ', + 39: 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', + 40: 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID', + 41: 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD', + 42: 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', + 43: 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP', + 44: 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP', + 45: 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP', + 46: 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP', + 47: 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP', + 48: 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP', + 49: 'GDS_PERF_SEL_SE1_SH1_NORET', + 50: 'GDS_PERF_SEL_SE1_SH1_RET', + 51: 'GDS_PERF_SEL_SE1_SH1_ORD_CNT', + 52: 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ', + 53: 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', + 54: 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID', + 55: 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD', + 56: 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', + 57: 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP', + 58: 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP', + 59: 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP', + 60: 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP', + 61: 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP', + 62: 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP', + 63: 'GDS_PERF_SEL_SE2_SH0_NORET', + 64: 'GDS_PERF_SEL_SE2_SH0_RET', + 65: 'GDS_PERF_SEL_SE2_SH0_ORD_CNT', + 66: 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ', + 67: 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', + 68: 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID', + 69: 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD', + 70: 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', + 71: 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP', + 72: 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP', + 73: 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP', + 74: 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP', + 75: 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP', + 76: 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP', + 77: 'GDS_PERF_SEL_SE2_SH1_NORET', + 78: 'GDS_PERF_SEL_SE2_SH1_RET', + 79: 'GDS_PERF_SEL_SE2_SH1_ORD_CNT', + 80: 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ', + 81: 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', + 82: 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID', + 83: 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD', + 84: 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', + 85: 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP', + 86: 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP', + 87: 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP', + 88: 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP', + 89: 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP', + 90: 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP', + 91: 'GDS_PERF_SEL_SE3_SH0_NORET', + 92: 'GDS_PERF_SEL_SE3_SH0_RET', + 93: 'GDS_PERF_SEL_SE3_SH0_ORD_CNT', + 94: 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ', + 95: 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', + 96: 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID', + 97: 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD', + 98: 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', + 99: 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP', + 100: 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP', + 101: 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP', + 102: 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP', + 103: 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP', + 104: 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP', + 105: 'GDS_PERF_SEL_SE3_SH1_NORET', + 106: 'GDS_PERF_SEL_SE3_SH1_RET', + 107: 'GDS_PERF_SEL_SE3_SH1_ORD_CNT', + 108: 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ', + 109: 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', + 110: 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID', + 111: 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD', + 112: 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', + 113: 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP', + 114: 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP', + 115: 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP', + 116: 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP', + 117: 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP', + 118: 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP', + 119: 'GDS_PERF_SEL_GWS_RELEASED', + 120: 'GDS_PERF_SEL_GWS_BYPASS', +} +GDS_PERF_SEL_DS_ADDR_CONFL = 0 +GDS_PERF_SEL_DS_BANK_CONFL = 1 +GDS_PERF_SEL_WBUF_FLUSH = 2 +GDS_PERF_SEL_WR_COMP = 3 +GDS_PERF_SEL_WBUF_WR = 4 +GDS_PERF_SEL_RBUF_HIT = 5 +GDS_PERF_SEL_RBUF_MISS = 6 +GDS_PERF_SEL_SE0_SH0_NORET = 7 +GDS_PERF_SEL_SE0_SH0_RET = 8 +GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9 +GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10 +GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11 +GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12 +GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13 +GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14 +GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15 +GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16 +GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17 +GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18 +GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19 +GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20 +GDS_PERF_SEL_SE0_SH1_NORET = 21 +GDS_PERF_SEL_SE0_SH1_RET = 22 +GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23 +GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24 +GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25 +GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26 +GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27 +GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28 +GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29 +GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30 +GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31 +GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32 +GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33 +GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34 +GDS_PERF_SEL_SE1_SH0_NORET = 35 +GDS_PERF_SEL_SE1_SH0_RET = 36 +GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37 +GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38 +GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39 +GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40 +GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41 +GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42 +GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43 +GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44 +GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45 +GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46 +GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47 +GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48 +GDS_PERF_SEL_SE1_SH1_NORET = 49 +GDS_PERF_SEL_SE1_SH1_RET = 50 +GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51 +GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52 +GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53 +GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54 +GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55 +GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56 +GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57 +GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58 +GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59 +GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60 +GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61 +GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62 +GDS_PERF_SEL_SE2_SH0_NORET = 63 +GDS_PERF_SEL_SE2_SH0_RET = 64 +GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65 +GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66 +GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67 +GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68 +GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69 +GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70 +GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71 +GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72 +GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73 +GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74 +GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75 +GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76 +GDS_PERF_SEL_SE2_SH1_NORET = 77 +GDS_PERF_SEL_SE2_SH1_RET = 78 +GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79 +GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80 +GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81 +GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82 +GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83 +GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84 +GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85 +GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86 +GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87 +GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88 +GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89 +GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90 +GDS_PERF_SEL_SE3_SH0_NORET = 91 +GDS_PERF_SEL_SE3_SH0_RET = 92 +GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93 +GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94 +GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95 +GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96 +GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97 +GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98 +GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99 +GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100 +GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101 +GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102 +GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103 +GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104 +GDS_PERF_SEL_SE3_SH1_NORET = 105 +GDS_PERF_SEL_SE3_SH1_RET = 106 +GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107 +GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108 +GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109 +GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110 +GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111 +GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112 +GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113 +GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114 +GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115 +GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116 +GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117 +GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118 +GDS_PERF_SEL_GWS_RELEASED = 119 +GDS_PERF_SEL_GWS_BYPASS = 120 +GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL' +MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'NO_FORCE_REQUEST', + 1: 'FORCE_LIGHT_SLEEP_REQUEST', + 2: 'FORCE_DEEP_SLEEP_REQUEST', + 3: 'FORCE_SHUT_DOWN_REQUEST', +} +NO_FORCE_REQUEST = 0 +FORCE_LIGHT_SLEEP_REQUEST = 1 +FORCE_DEEP_SLEEP_REQUEST = 2 +FORCE_SHUT_DOWN_REQUEST = 3 +MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL2' +MEM_PWR_FORCE_CTRL2__enumvalues = { + 0: 'NO_FORCE_REQ', + 1: 'FORCE_LIGHT_SLEEP_REQ', +} +NO_FORCE_REQ = 0 +FORCE_LIGHT_SLEEP_REQ = 1 +MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_DIS_CTRL' +MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'ENABLE_MEM_PWR_CTRL', + 1: 'DISABLE_MEM_PWR_CTRL', +} +ENABLE_MEM_PWR_CTRL = 0 +DISABLE_MEM_PWR_CTRL = 1 +MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL' +MEM_PWR_SEL_CTRL__enumvalues = { + 0: 'DYNAMIC_SHUT_DOWN_ENABLE', + 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', + 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', +} +DYNAMIC_SHUT_DOWN_ENABLE = 0 +DYNAMIC_DEEP_SLEEP_ENABLE = 1 +DYNAMIC_LIGHT_SLEEP_ENABLE = 2 +MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL2' +MEM_PWR_SEL_CTRL2__enumvalues = { + 0: 'DYNAMIC_DEEP_SLEEP_EN', + 1: 'DYNAMIC_LIGHT_SLEEP_EN', +} +DYNAMIC_DEEP_SLEEP_EN = 0 +DYNAMIC_LIGHT_SLEEP_EN = 1 +MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'RowSize' +RowSize__enumvalues = { + 0: 'ADDR_CONFIG_1KB_ROW', + 1: 'ADDR_CONFIG_2KB_ROW', + 2: 'ADDR_CONFIG_4KB_ROW', +} +ADDR_CONFIG_1KB_ROW = 0 +ADDR_CONFIG_2KB_ROW = 1 +ADDR_CONFIG_4KB_ROW = 2 +RowSize = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceEndian' +SurfaceEndian__enumvalues = { + 0: 'ENDIAN_NONE', + 1: 'ENDIAN_8IN16', + 2: 'ENDIAN_8IN32', + 3: 'ENDIAN_8IN64', +} +ENDIAN_NONE = 0 +ENDIAN_8IN16 = 1 +ENDIAN_8IN32 = 2 +ENDIAN_8IN64 = 3 +SurfaceEndian = ctypes.c_uint32 # enum + +# values for enumeration 'ArrayMode' +ArrayMode__enumvalues = { + 0: 'ARRAY_LINEAR_GENERAL', + 1: 'ARRAY_LINEAR_ALIGNED', + 2: 'ARRAY_1D_TILED_THIN1', + 3: 'ARRAY_1D_TILED_THICK', + 4: 'ARRAY_2D_TILED_THIN1', + 5: 'ARRAY_PRT_TILED_THIN1', + 6: 'ARRAY_PRT_2D_TILED_THIN1', + 7: 'ARRAY_2D_TILED_THICK', + 8: 'ARRAY_2D_TILED_XTHICK', + 9: 'ARRAY_PRT_TILED_THICK', + 10: 'ARRAY_PRT_2D_TILED_THICK', + 11: 'ARRAY_PRT_3D_TILED_THIN1', + 12: 'ARRAY_3D_TILED_THIN1', + 13: 'ARRAY_3D_TILED_THICK', + 14: 'ARRAY_3D_TILED_XTHICK', + 15: 'ARRAY_PRT_3D_TILED_THICK', +} +ARRAY_LINEAR_GENERAL = 0 +ARRAY_LINEAR_ALIGNED = 1 +ARRAY_1D_TILED_THIN1 = 2 +ARRAY_1D_TILED_THICK = 3 +ARRAY_2D_TILED_THIN1 = 4 +ARRAY_PRT_TILED_THIN1 = 5 +ARRAY_PRT_2D_TILED_THIN1 = 6 +ARRAY_2D_TILED_THICK = 7 +ARRAY_2D_TILED_XTHICK = 8 +ARRAY_PRT_TILED_THICK = 9 +ARRAY_PRT_2D_TILED_THICK = 10 +ARRAY_PRT_3D_TILED_THIN1 = 11 +ARRAY_3D_TILED_THIN1 = 12 +ARRAY_3D_TILED_THICK = 13 +ARRAY_3D_TILED_XTHICK = 14 +ARRAY_PRT_3D_TILED_THICK = 15 +ArrayMode = ctypes.c_uint32 # enum + +# values for enumeration 'NumPipes' +NumPipes__enumvalues = { + 0: 'ADDR_CONFIG_1_PIPE', + 1: 'ADDR_CONFIG_2_PIPE', + 2: 'ADDR_CONFIG_4_PIPE', + 3: 'ADDR_CONFIG_8_PIPE', + 4: 'ADDR_CONFIG_16_PIPE', + 5: 'ADDR_CONFIG_32_PIPE', +} +ADDR_CONFIG_1_PIPE = 0 +ADDR_CONFIG_2_PIPE = 1 +ADDR_CONFIG_4_PIPE = 2 +ADDR_CONFIG_8_PIPE = 3 +ADDR_CONFIG_16_PIPE = 4 +ADDR_CONFIG_32_PIPE = 5 +NumPipes = ctypes.c_uint32 # enum + +# values for enumeration 'NumBanksConfig' +NumBanksConfig__enumvalues = { + 0: 'ADDR_CONFIG_1_BANK', + 1: 'ADDR_CONFIG_2_BANK', + 2: 'ADDR_CONFIG_4_BANK', + 3: 'ADDR_CONFIG_8_BANK', + 4: 'ADDR_CONFIG_16_BANK', +} +ADDR_CONFIG_1_BANK = 0 +ADDR_CONFIG_2_BANK = 1 +ADDR_CONFIG_4_BANK = 2 +ADDR_CONFIG_8_BANK = 3 +ADDR_CONFIG_16_BANK = 4 +NumBanksConfig = ctypes.c_uint32 # enum + +# values for enumeration 'PipeInterleaveSize' +PipeInterleaveSize__enumvalues = { + 0: 'ADDR_CONFIG_PIPE_INTERLEAVE_256B', + 1: 'ADDR_CONFIG_PIPE_INTERLEAVE_512B', + 2: 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB', + 3: 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB', +} +ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0 +ADDR_CONFIG_PIPE_INTERLEAVE_512B = 1 +ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 2 +ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 3 +PipeInterleaveSize = ctypes.c_uint32 # enum + +# values for enumeration 'BankInterleaveSize' +BankInterleaveSize__enumvalues = { + 0: 'ADDR_CONFIG_BANK_INTERLEAVE_1', + 1: 'ADDR_CONFIG_BANK_INTERLEAVE_2', + 2: 'ADDR_CONFIG_BANK_INTERLEAVE_4', + 3: 'ADDR_CONFIG_BANK_INTERLEAVE_8', +} +ADDR_CONFIG_BANK_INTERLEAVE_1 = 0 +ADDR_CONFIG_BANK_INTERLEAVE_2 = 1 +ADDR_CONFIG_BANK_INTERLEAVE_4 = 2 +ADDR_CONFIG_BANK_INTERLEAVE_8 = 3 +BankInterleaveSize = ctypes.c_uint32 # enum + +# values for enumeration 'NumShaderEngines' +NumShaderEngines__enumvalues = { + 0: 'ADDR_CONFIG_1_SHADER_ENGINE', + 1: 'ADDR_CONFIG_2_SHADER_ENGINE', + 2: 'ADDR_CONFIG_4_SHADER_ENGINE', + 3: 'ADDR_CONFIG_8_SHADER_ENGINE', +} +ADDR_CONFIG_1_SHADER_ENGINE = 0 +ADDR_CONFIG_2_SHADER_ENGINE = 1 +ADDR_CONFIG_4_SHADER_ENGINE = 2 +ADDR_CONFIG_8_SHADER_ENGINE = 3 +NumShaderEngines = ctypes.c_uint32 # enum + +# values for enumeration 'NumRbPerShaderEngine' +NumRbPerShaderEngine__enumvalues = { + 0: 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE', + 1: 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE', + 2: 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE', +} +ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0 +ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 1 +ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 2 +NumRbPerShaderEngine = ctypes.c_uint32 # enum + +# values for enumeration 'NumGPUs' +NumGPUs__enumvalues = { + 0: 'ADDR_CONFIG_1_GPU', + 1: 'ADDR_CONFIG_2_GPU', + 2: 'ADDR_CONFIG_4_GPU', + 3: 'ADDR_CONFIG_8_GPU', +} +ADDR_CONFIG_1_GPU = 0 +ADDR_CONFIG_2_GPU = 1 +ADDR_CONFIG_4_GPU = 2 +ADDR_CONFIG_8_GPU = 3 +NumGPUs = ctypes.c_uint32 # enum + +# values for enumeration 'NumMaxCompressedFragments' +NumMaxCompressedFragments__enumvalues = { + 0: 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', + 1: 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', + 2: 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', + 3: 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', +} +ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0 +ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 1 +ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 2 +ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 3 +NumMaxCompressedFragments = ctypes.c_uint32 # enum + +# values for enumeration 'ShaderEngineTileSize' +ShaderEngineTileSize__enumvalues = { + 0: 'ADDR_CONFIG_SE_TILE_16', + 1: 'ADDR_CONFIG_SE_TILE_32', +} +ADDR_CONFIG_SE_TILE_16 = 0 +ADDR_CONFIG_SE_TILE_32 = 1 +ShaderEngineTileSize = ctypes.c_uint32 # enum + +# values for enumeration 'MultiGPUTileSize' +MultiGPUTileSize__enumvalues = { + 0: 'ADDR_CONFIG_GPU_TILE_16', + 1: 'ADDR_CONFIG_GPU_TILE_32', + 2: 'ADDR_CONFIG_GPU_TILE_64', + 3: 'ADDR_CONFIG_GPU_TILE_128', +} +ADDR_CONFIG_GPU_TILE_16 = 0 +ADDR_CONFIG_GPU_TILE_32 = 1 +ADDR_CONFIG_GPU_TILE_64 = 2 +ADDR_CONFIG_GPU_TILE_128 = 3 +MultiGPUTileSize = ctypes.c_uint32 # enum + +# values for enumeration 'NumLowerPipes' +NumLowerPipes__enumvalues = { + 0: 'ADDR_CONFIG_1_LOWER_PIPES', + 1: 'ADDR_CONFIG_2_LOWER_PIPES', +} +ADDR_CONFIG_1_LOWER_PIPES = 0 +ADDR_CONFIG_2_LOWER_PIPES = 1 +NumLowerPipes = ctypes.c_uint32 # enum + +# values for enumeration 'ColorTransform' +ColorTransform__enumvalues = { + 0: 'DCC_CT_AUTO', + 1: 'DCC_CT_NONE', + 2: 'ABGR_TO_A_BG_G_RB', + 3: 'BGRA_TO_BG_G_RB_A', +} +DCC_CT_AUTO = 0 +DCC_CT_NONE = 1 +ABGR_TO_A_BG_G_RB = 2 +BGRA_TO_BG_G_RB_A = 3 +ColorTransform = ctypes.c_uint32 # enum + +# values for enumeration 'CompareRef' +CompareRef__enumvalues = { + 0: 'REF_NEVER', + 1: 'REF_LESS', + 2: 'REF_EQUAL', + 3: 'REF_LEQUAL', + 4: 'REF_GREATER', + 5: 'REF_NOTEQUAL', + 6: 'REF_GEQUAL', + 7: 'REF_ALWAYS', +} +REF_NEVER = 0 +REF_LESS = 1 +REF_EQUAL = 2 +REF_LEQUAL = 3 +REF_GREATER = 4 +REF_NOTEQUAL = 5 +REF_GEQUAL = 6 +REF_ALWAYS = 7 +CompareRef = ctypes.c_uint32 # enum + +# values for enumeration 'ReadSize' +ReadSize__enumvalues = { + 0: 'READ_256_BITS', + 1: 'READ_512_BITS', +} +READ_256_BITS = 0 +READ_512_BITS = 1 +ReadSize = ctypes.c_uint32 # enum + +# values for enumeration 'DepthFormat' +DepthFormat__enumvalues = { + 0: 'DEPTH_INVALID', + 1: 'DEPTH_16', + 2: 'DEPTH_X8_24', + 3: 'DEPTH_8_24', + 4: 'DEPTH_X8_24_FLOAT', + 5: 'DEPTH_8_24_FLOAT', + 6: 'DEPTH_32_FLOAT', + 7: 'DEPTH_X24_8_32_FLOAT', +} +DEPTH_INVALID = 0 +DEPTH_16 = 1 +DEPTH_X8_24 = 2 +DEPTH_8_24 = 3 +DEPTH_X8_24_FLOAT = 4 +DEPTH_8_24_FLOAT = 5 +DEPTH_32_FLOAT = 6 +DEPTH_X24_8_32_FLOAT = 7 +DepthFormat = ctypes.c_uint32 # enum + +# values for enumeration 'ZFormat' +ZFormat__enumvalues = { + 0: 'Z_INVALID', + 1: 'Z_16', + 2: 'Z_24', + 3: 'Z_32_FLOAT', +} +Z_INVALID = 0 +Z_16 = 1 +Z_24 = 2 +Z_32_FLOAT = 3 +ZFormat = ctypes.c_uint32 # enum + +# values for enumeration 'StencilFormat' +StencilFormat__enumvalues = { + 0: 'STENCIL_INVALID', + 1: 'STENCIL_8', +} +STENCIL_INVALID = 0 +STENCIL_8 = 1 +StencilFormat = ctypes.c_uint32 # enum + +# values for enumeration 'CmaskMode' +CmaskMode__enumvalues = { + 0: 'CMASK_CLEAR_NONE', + 1: 'CMASK_CLEAR_ONE', + 2: 'CMASK_CLEAR_ALL', + 3: 'CMASK_ANY_EXPANDED', + 4: 'CMASK_ALPHA0_FRAG1', + 5: 'CMASK_ALPHA0_FRAG2', + 6: 'CMASK_ALPHA0_FRAG4', + 7: 'CMASK_ALPHA0_FRAGS', + 8: 'CMASK_ALPHA1_FRAG1', + 9: 'CMASK_ALPHA1_FRAG2', + 10: 'CMASK_ALPHA1_FRAG4', + 11: 'CMASK_ALPHA1_FRAGS', + 12: 'CMASK_ALPHAX_FRAG1', + 13: 'CMASK_ALPHAX_FRAG2', + 14: 'CMASK_ALPHAX_FRAG4', + 15: 'CMASK_ALPHAX_FRAGS', +} +CMASK_CLEAR_NONE = 0 +CMASK_CLEAR_ONE = 1 +CMASK_CLEAR_ALL = 2 +CMASK_ANY_EXPANDED = 3 +CMASK_ALPHA0_FRAG1 = 4 +CMASK_ALPHA0_FRAG2 = 5 +CMASK_ALPHA0_FRAG4 = 6 +CMASK_ALPHA0_FRAGS = 7 +CMASK_ALPHA1_FRAG1 = 8 +CMASK_ALPHA1_FRAG2 = 9 +CMASK_ALPHA1_FRAG4 = 10 +CMASK_ALPHA1_FRAGS = 11 +CMASK_ALPHAX_FRAG1 = 12 +CMASK_ALPHAX_FRAG2 = 13 +CMASK_ALPHAX_FRAG4 = 14 +CMASK_ALPHAX_FRAGS = 15 +CmaskMode = ctypes.c_uint32 # enum + +# values for enumeration 'QuadExportFormat' +QuadExportFormat__enumvalues = { + 0: 'EXPORT_UNUSED', + 1: 'EXPORT_32_R', + 2: 'EXPORT_32_GR', + 3: 'EXPORT_32_AR', + 4: 'EXPORT_FP16_ABGR', + 5: 'EXPORT_UNSIGNED16_ABGR', + 6: 'EXPORT_SIGNED16_ABGR', + 7: 'EXPORT_32_ABGR', + 8: 'EXPORT_32BPP_8PIX', + 9: 'EXPORT_16_16_UNSIGNED_8PIX', + 10: 'EXPORT_16_16_SIGNED_8PIX', + 11: 'EXPORT_16_16_FLOAT_8PIX', +} +EXPORT_UNUSED = 0 +EXPORT_32_R = 1 +EXPORT_32_GR = 2 +EXPORT_32_AR = 3 +EXPORT_FP16_ABGR = 4 +EXPORT_UNSIGNED16_ABGR = 5 +EXPORT_SIGNED16_ABGR = 6 +EXPORT_32_ABGR = 7 +EXPORT_32BPP_8PIX = 8 +EXPORT_16_16_UNSIGNED_8PIX = 9 +EXPORT_16_16_SIGNED_8PIX = 10 +EXPORT_16_16_FLOAT_8PIX = 11 +QuadExportFormat = ctypes.c_uint32 # enum + +# values for enumeration 'QuadExportFormatOld' +QuadExportFormatOld__enumvalues = { + 0: 'EXPORT_4P_32BPC_ABGR', + 1: 'EXPORT_4P_16BPC_ABGR', + 2: 'EXPORT_4P_32BPC_GR', + 3: 'EXPORT_4P_32BPC_AR', + 4: 'EXPORT_2P_32BPC_ABGR', + 5: 'EXPORT_8P_32BPC_R', +} +EXPORT_4P_32BPC_ABGR = 0 +EXPORT_4P_16BPC_ABGR = 1 +EXPORT_4P_32BPC_GR = 2 +EXPORT_4P_32BPC_AR = 3 +EXPORT_2P_32BPC_ABGR = 4 +EXPORT_8P_32BPC_R = 5 +QuadExportFormatOld = ctypes.c_uint32 # enum + +# values for enumeration 'ColorFormat' +ColorFormat__enumvalues = { + 0: 'COLOR_INVALID', + 1: 'COLOR_8', + 2: 'COLOR_16', + 3: 'COLOR_8_8', + 4: 'COLOR_32', + 5: 'COLOR_16_16', + 6: 'COLOR_10_11_11', + 7: 'COLOR_11_11_10', + 8: 'COLOR_10_10_10_2', + 9: 'COLOR_2_10_10_10', + 10: 'COLOR_8_8_8_8', + 11: 'COLOR_32_32', + 12: 'COLOR_16_16_16_16', + 13: 'COLOR_RESERVED_13', + 14: 'COLOR_32_32_32_32', + 15: 'COLOR_RESERVED_15', + 16: 'COLOR_5_6_5', + 17: 'COLOR_1_5_5_5', + 18: 'COLOR_5_5_5_1', + 19: 'COLOR_4_4_4_4', + 20: 'COLOR_8_24', + 21: 'COLOR_24_8', + 22: 'COLOR_X24_8_32_FLOAT', + 23: 'COLOR_RESERVED_23', + 24: 'COLOR_RESERVED_24', + 25: 'COLOR_RESERVED_25', + 26: 'COLOR_RESERVED_26', + 27: 'COLOR_RESERVED_27', + 28: 'COLOR_RESERVED_28', + 29: 'COLOR_RESERVED_29', + 30: 'COLOR_RESERVED_30', + 31: 'COLOR_2_10_10_10_6E4', +} +COLOR_INVALID = 0 +COLOR_8 = 1 +COLOR_16 = 2 +COLOR_8_8 = 3 +COLOR_32 = 4 +COLOR_16_16 = 5 +COLOR_10_11_11 = 6 +COLOR_11_11_10 = 7 +COLOR_10_10_10_2 = 8 +COLOR_2_10_10_10 = 9 +COLOR_8_8_8_8 = 10 +COLOR_32_32 = 11 +COLOR_16_16_16_16 = 12 +COLOR_RESERVED_13 = 13 +COLOR_32_32_32_32 = 14 +COLOR_RESERVED_15 = 15 +COLOR_5_6_5 = 16 +COLOR_1_5_5_5 = 17 +COLOR_5_5_5_1 = 18 +COLOR_4_4_4_4 = 19 +COLOR_8_24 = 20 +COLOR_24_8 = 21 +COLOR_X24_8_32_FLOAT = 22 +COLOR_RESERVED_23 = 23 +COLOR_RESERVED_24 = 24 +COLOR_RESERVED_25 = 25 +COLOR_RESERVED_26 = 26 +COLOR_RESERVED_27 = 27 +COLOR_RESERVED_28 = 28 +COLOR_RESERVED_29 = 29 +COLOR_RESERVED_30 = 30 +COLOR_2_10_10_10_6E4 = 31 +ColorFormat = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceFormat' +SurfaceFormat__enumvalues = { + 0: 'FMT_INVALID', + 1: 'FMT_8', + 2: 'FMT_16', + 3: 'FMT_8_8', + 4: 'FMT_32', + 5: 'FMT_16_16', + 6: 'FMT_10_11_11', + 7: 'FMT_11_11_10', + 8: 'FMT_10_10_10_2', + 9: 'FMT_2_10_10_10', + 10: 'FMT_8_8_8_8', + 11: 'FMT_32_32', + 12: 'FMT_16_16_16_16', + 13: 'FMT_32_32_32', + 14: 'FMT_32_32_32_32', + 15: 'FMT_RESERVED_4', + 16: 'FMT_5_6_5', + 17: 'FMT_1_5_5_5', + 18: 'FMT_5_5_5_1', + 19: 'FMT_4_4_4_4', + 20: 'FMT_8_24', + 21: 'FMT_24_8', + 22: 'FMT_X24_8_32_FLOAT', + 23: 'FMT_RESERVED_33', + 24: 'FMT_11_11_10_FLOAT', + 25: 'FMT_16_FLOAT', + 26: 'FMT_32_FLOAT', + 27: 'FMT_16_16_FLOAT', + 28: 'FMT_8_24_FLOAT', + 29: 'FMT_24_8_FLOAT', + 30: 'FMT_32_32_FLOAT', + 31: 'FMT_10_11_11_FLOAT', + 32: 'FMT_16_16_16_16_FLOAT', + 33: 'FMT_3_3_2', + 34: 'FMT_6_5_5', + 35: 'FMT_32_32_32_32_FLOAT', + 36: 'FMT_RESERVED_36', + 37: 'FMT_1', + 38: 'FMT_1_REVERSED', + 39: 'FMT_GB_GR', + 40: 'FMT_BG_RG', + 41: 'FMT_32_AS_8', + 42: 'FMT_32_AS_8_8', + 43: 'FMT_5_9_9_9_SHAREDEXP', + 44: 'FMT_8_8_8', + 45: 'FMT_16_16_16', + 46: 'FMT_16_16_16_FLOAT', + 47: 'FMT_4_4', + 48: 'FMT_32_32_32_FLOAT', + 49: 'FMT_BC1', + 50: 'FMT_BC2', + 51: 'FMT_BC3', + 52: 'FMT_BC4', + 53: 'FMT_BC5', + 54: 'FMT_BC6', + 55: 'FMT_BC7', + 56: 'FMT_32_AS_32_32_32_32', + 57: 'FMT_APC3', + 58: 'FMT_APC4', + 59: 'FMT_APC5', + 60: 'FMT_APC6', + 61: 'FMT_APC7', + 62: 'FMT_CTX1', + 63: 'FMT_RESERVED_63', +} +FMT_INVALID = 0 +FMT_8 = 1 +FMT_16 = 2 +FMT_8_8 = 3 +FMT_32 = 4 +FMT_16_16 = 5 +FMT_10_11_11 = 6 +FMT_11_11_10 = 7 +FMT_10_10_10_2 = 8 +FMT_2_10_10_10 = 9 +FMT_8_8_8_8 = 10 +FMT_32_32 = 11 +FMT_16_16_16_16 = 12 +FMT_32_32_32 = 13 +FMT_32_32_32_32 = 14 +FMT_RESERVED_4 = 15 +FMT_5_6_5 = 16 +FMT_1_5_5_5 = 17 +FMT_5_5_5_1 = 18 +FMT_4_4_4_4 = 19 +FMT_8_24 = 20 +FMT_24_8 = 21 +FMT_X24_8_32_FLOAT = 22 +FMT_RESERVED_33 = 23 +FMT_11_11_10_FLOAT = 24 +FMT_16_FLOAT = 25 +FMT_32_FLOAT = 26 +FMT_16_16_FLOAT = 27 +FMT_8_24_FLOAT = 28 +FMT_24_8_FLOAT = 29 +FMT_32_32_FLOAT = 30 +FMT_10_11_11_FLOAT = 31 +FMT_16_16_16_16_FLOAT = 32 +FMT_3_3_2 = 33 +FMT_6_5_5 = 34 +FMT_32_32_32_32_FLOAT = 35 +FMT_RESERVED_36 = 36 +FMT_1 = 37 +FMT_1_REVERSED = 38 +FMT_GB_GR = 39 +FMT_BG_RG = 40 +FMT_32_AS_8 = 41 +FMT_32_AS_8_8 = 42 +FMT_5_9_9_9_SHAREDEXP = 43 +FMT_8_8_8 = 44 +FMT_16_16_16 = 45 +FMT_16_16_16_FLOAT = 46 +FMT_4_4 = 47 +FMT_32_32_32_FLOAT = 48 +FMT_BC1 = 49 +FMT_BC2 = 50 +FMT_BC3 = 51 +FMT_BC4 = 52 +FMT_BC5 = 53 +FMT_BC6 = 54 +FMT_BC7 = 55 +FMT_32_AS_32_32_32_32 = 56 +FMT_APC3 = 57 +FMT_APC4 = 58 +FMT_APC5 = 59 +FMT_APC6 = 60 +FMT_APC7 = 61 +FMT_CTX1 = 62 +FMT_RESERVED_63 = 63 +SurfaceFormat = ctypes.c_uint32 # enum + +# values for enumeration 'BUF_DATA_FORMAT' +BUF_DATA_FORMAT__enumvalues = { + 0: 'BUF_DATA_FORMAT_INVALID', + 1: 'BUF_DATA_FORMAT_8', + 2: 'BUF_DATA_FORMAT_16', + 3: 'BUF_DATA_FORMAT_8_8', + 4: 'BUF_DATA_FORMAT_32', + 5: 'BUF_DATA_FORMAT_16_16', + 6: 'BUF_DATA_FORMAT_10_11_11', + 7: 'BUF_DATA_FORMAT_11_11_10', + 8: 'BUF_DATA_FORMAT_10_10_10_2', + 9: 'BUF_DATA_FORMAT_2_10_10_10', + 10: 'BUF_DATA_FORMAT_8_8_8_8', + 11: 'BUF_DATA_FORMAT_32_32', + 12: 'BUF_DATA_FORMAT_16_16_16_16', + 13: 'BUF_DATA_FORMAT_32_32_32', + 14: 'BUF_DATA_FORMAT_32_32_32_32', + 15: 'BUF_DATA_FORMAT_RESERVED_15', +} +BUF_DATA_FORMAT_INVALID = 0 +BUF_DATA_FORMAT_8 = 1 +BUF_DATA_FORMAT_16 = 2 +BUF_DATA_FORMAT_8_8 = 3 +BUF_DATA_FORMAT_32 = 4 +BUF_DATA_FORMAT_16_16 = 5 +BUF_DATA_FORMAT_10_11_11 = 6 +BUF_DATA_FORMAT_11_11_10 = 7 +BUF_DATA_FORMAT_10_10_10_2 = 8 +BUF_DATA_FORMAT_2_10_10_10 = 9 +BUF_DATA_FORMAT_8_8_8_8 = 10 +BUF_DATA_FORMAT_32_32 = 11 +BUF_DATA_FORMAT_16_16_16_16 = 12 +BUF_DATA_FORMAT_32_32_32 = 13 +BUF_DATA_FORMAT_32_32_32_32 = 14 +BUF_DATA_FORMAT_RESERVED_15 = 15 +BUF_DATA_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_DATA_FORMAT' +IMG_DATA_FORMAT__enumvalues = { + 0: 'IMG_DATA_FORMAT_INVALID', + 1: 'IMG_DATA_FORMAT_8', + 2: 'IMG_DATA_FORMAT_16', + 3: 'IMG_DATA_FORMAT_8_8', + 4: 'IMG_DATA_FORMAT_32', + 5: 'IMG_DATA_FORMAT_16_16', + 6: 'IMG_DATA_FORMAT_10_11_11', + 7: 'IMG_DATA_FORMAT_11_11_10', + 8: 'IMG_DATA_FORMAT_10_10_10_2', + 9: 'IMG_DATA_FORMAT_2_10_10_10', + 10: 'IMG_DATA_FORMAT_8_8_8_8', + 11: 'IMG_DATA_FORMAT_32_32', + 12: 'IMG_DATA_FORMAT_16_16_16_16', + 13: 'IMG_DATA_FORMAT_32_32_32', + 14: 'IMG_DATA_FORMAT_32_32_32_32', + 15: 'IMG_DATA_FORMAT_RESERVED_15', + 16: 'IMG_DATA_FORMAT_5_6_5', + 17: 'IMG_DATA_FORMAT_1_5_5_5', + 18: 'IMG_DATA_FORMAT_5_5_5_1', + 19: 'IMG_DATA_FORMAT_4_4_4_4', + 20: 'IMG_DATA_FORMAT_8_24', + 21: 'IMG_DATA_FORMAT_24_8', + 22: 'IMG_DATA_FORMAT_X24_8_32', + 23: 'IMG_DATA_FORMAT_8_AS_8_8_8_8', + 24: 'IMG_DATA_FORMAT_ETC2_RGB', + 25: 'IMG_DATA_FORMAT_ETC2_RGBA', + 26: 'IMG_DATA_FORMAT_ETC2_R', + 27: 'IMG_DATA_FORMAT_ETC2_RG', + 28: 'IMG_DATA_FORMAT_ETC2_RGBA1', + 29: 'IMG_DATA_FORMAT_RESERVED_29', + 30: 'IMG_DATA_FORMAT_RESERVED_30', + 31: 'IMG_DATA_FORMAT_6E4', + 32: 'IMG_DATA_FORMAT_GB_GR', + 33: 'IMG_DATA_FORMAT_BG_RG', + 34: 'IMG_DATA_FORMAT_5_9_9_9', + 35: 'IMG_DATA_FORMAT_BC1', + 36: 'IMG_DATA_FORMAT_BC2', + 37: 'IMG_DATA_FORMAT_BC3', + 38: 'IMG_DATA_FORMAT_BC4', + 39: 'IMG_DATA_FORMAT_BC5', + 40: 'IMG_DATA_FORMAT_BC6', + 41: 'IMG_DATA_FORMAT_BC7', + 42: 'IMG_DATA_FORMAT_16_AS_32_32', + 43: 'IMG_DATA_FORMAT_16_AS_16_16_16_16', + 44: 'IMG_DATA_FORMAT_16_AS_32_32_32_32', + 45: 'IMG_DATA_FORMAT_FMASK', + 46: 'IMG_DATA_FORMAT_ASTC_2D_LDR', + 47: 'IMG_DATA_FORMAT_ASTC_2D_HDR', + 48: 'IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB', + 49: 'IMG_DATA_FORMAT_ASTC_3D_LDR', + 50: 'IMG_DATA_FORMAT_ASTC_3D_HDR', + 51: 'IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB', + 52: 'IMG_DATA_FORMAT_N_IN_16', + 53: 'IMG_DATA_FORMAT_N_IN_16_16', + 54: 'IMG_DATA_FORMAT_N_IN_16_16_16_16', + 55: 'IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16', + 56: 'IMG_DATA_FORMAT_RESERVED_56', + 57: 'IMG_DATA_FORMAT_4_4', + 58: 'IMG_DATA_FORMAT_6_5_5', + 59: 'IMG_DATA_FORMAT_RESERVED_59', + 60: 'IMG_DATA_FORMAT_RESERVED_60', + 61: 'IMG_DATA_FORMAT_8_AS_32', + 62: 'IMG_DATA_FORMAT_8_AS_32_32', + 63: 'IMG_DATA_FORMAT_32_AS_32_32_32_32', +} +IMG_DATA_FORMAT_INVALID = 0 +IMG_DATA_FORMAT_8 = 1 +IMG_DATA_FORMAT_16 = 2 +IMG_DATA_FORMAT_8_8 = 3 +IMG_DATA_FORMAT_32 = 4 +IMG_DATA_FORMAT_16_16 = 5 +IMG_DATA_FORMAT_10_11_11 = 6 +IMG_DATA_FORMAT_11_11_10 = 7 +IMG_DATA_FORMAT_10_10_10_2 = 8 +IMG_DATA_FORMAT_2_10_10_10 = 9 +IMG_DATA_FORMAT_8_8_8_8 = 10 +IMG_DATA_FORMAT_32_32 = 11 +IMG_DATA_FORMAT_16_16_16_16 = 12 +IMG_DATA_FORMAT_32_32_32 = 13 +IMG_DATA_FORMAT_32_32_32_32 = 14 +IMG_DATA_FORMAT_RESERVED_15 = 15 +IMG_DATA_FORMAT_5_6_5 = 16 +IMG_DATA_FORMAT_1_5_5_5 = 17 +IMG_DATA_FORMAT_5_5_5_1 = 18 +IMG_DATA_FORMAT_4_4_4_4 = 19 +IMG_DATA_FORMAT_8_24 = 20 +IMG_DATA_FORMAT_24_8 = 21 +IMG_DATA_FORMAT_X24_8_32 = 22 +IMG_DATA_FORMAT_8_AS_8_8_8_8 = 23 +IMG_DATA_FORMAT_ETC2_RGB = 24 +IMG_DATA_FORMAT_ETC2_RGBA = 25 +IMG_DATA_FORMAT_ETC2_R = 26 +IMG_DATA_FORMAT_ETC2_RG = 27 +IMG_DATA_FORMAT_ETC2_RGBA1 = 28 +IMG_DATA_FORMAT_RESERVED_29 = 29 +IMG_DATA_FORMAT_RESERVED_30 = 30 +IMG_DATA_FORMAT_6E4 = 31 +IMG_DATA_FORMAT_GB_GR = 32 +IMG_DATA_FORMAT_BG_RG = 33 +IMG_DATA_FORMAT_5_9_9_9 = 34 +IMG_DATA_FORMAT_BC1 = 35 +IMG_DATA_FORMAT_BC2 = 36 +IMG_DATA_FORMAT_BC3 = 37 +IMG_DATA_FORMAT_BC4 = 38 +IMG_DATA_FORMAT_BC5 = 39 +IMG_DATA_FORMAT_BC6 = 40 +IMG_DATA_FORMAT_BC7 = 41 +IMG_DATA_FORMAT_16_AS_32_32 = 42 +IMG_DATA_FORMAT_16_AS_16_16_16_16 = 43 +IMG_DATA_FORMAT_16_AS_32_32_32_32 = 44 +IMG_DATA_FORMAT_FMASK = 45 +IMG_DATA_FORMAT_ASTC_2D_LDR = 46 +IMG_DATA_FORMAT_ASTC_2D_HDR = 47 +IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB = 48 +IMG_DATA_FORMAT_ASTC_3D_LDR = 49 +IMG_DATA_FORMAT_ASTC_3D_HDR = 50 +IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB = 51 +IMG_DATA_FORMAT_N_IN_16 = 52 +IMG_DATA_FORMAT_N_IN_16_16 = 53 +IMG_DATA_FORMAT_N_IN_16_16_16_16 = 54 +IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 = 55 +IMG_DATA_FORMAT_RESERVED_56 = 56 +IMG_DATA_FORMAT_4_4 = 57 +IMG_DATA_FORMAT_6_5_5 = 58 +IMG_DATA_FORMAT_RESERVED_59 = 59 +IMG_DATA_FORMAT_RESERVED_60 = 60 +IMG_DATA_FORMAT_8_AS_32 = 61 +IMG_DATA_FORMAT_8_AS_32_32 = 62 +IMG_DATA_FORMAT_32_AS_32_32_32_32 = 63 +IMG_DATA_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'BUF_NUM_FORMAT' +BUF_NUM_FORMAT__enumvalues = { + 0: 'BUF_NUM_FORMAT_UNORM', + 1: 'BUF_NUM_FORMAT_SNORM', + 2: 'BUF_NUM_FORMAT_USCALED', + 3: 'BUF_NUM_FORMAT_SSCALED', + 4: 'BUF_NUM_FORMAT_UINT', + 5: 'BUF_NUM_FORMAT_SINT', + 6: 'BUF_NUM_FORMAT_UNORM_UINT', + 7: 'BUF_NUM_FORMAT_FLOAT', +} +BUF_NUM_FORMAT_UNORM = 0 +BUF_NUM_FORMAT_SNORM = 1 +BUF_NUM_FORMAT_USCALED = 2 +BUF_NUM_FORMAT_SSCALED = 3 +BUF_NUM_FORMAT_UINT = 4 +BUF_NUM_FORMAT_SINT = 5 +BUF_NUM_FORMAT_UNORM_UINT = 6 +BUF_NUM_FORMAT_FLOAT = 7 +BUF_NUM_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT' +IMG_NUM_FORMAT__enumvalues = { + 0: 'IMG_NUM_FORMAT_UNORM', + 1: 'IMG_NUM_FORMAT_SNORM', + 2: 'IMG_NUM_FORMAT_USCALED', + 3: 'IMG_NUM_FORMAT_SSCALED', + 4: 'IMG_NUM_FORMAT_UINT', + 5: 'IMG_NUM_FORMAT_SINT', + 6: 'IMG_NUM_FORMAT_UNORM_UINT', + 7: 'IMG_NUM_FORMAT_FLOAT', + 8: 'IMG_NUM_FORMAT_RESERVED_8', + 9: 'IMG_NUM_FORMAT_SRGB', + 10: 'IMG_NUM_FORMAT_RESERVED_10', + 11: 'IMG_NUM_FORMAT_RESERVED_11', + 12: 'IMG_NUM_FORMAT_RESERVED_12', + 13: 'IMG_NUM_FORMAT_RESERVED_13', + 14: 'IMG_NUM_FORMAT_RESERVED_14', + 15: 'IMG_NUM_FORMAT_RESERVED_15', +} +IMG_NUM_FORMAT_UNORM = 0 +IMG_NUM_FORMAT_SNORM = 1 +IMG_NUM_FORMAT_USCALED = 2 +IMG_NUM_FORMAT_SSCALED = 3 +IMG_NUM_FORMAT_UINT = 4 +IMG_NUM_FORMAT_SINT = 5 +IMG_NUM_FORMAT_UNORM_UINT = 6 +IMG_NUM_FORMAT_FLOAT = 7 +IMG_NUM_FORMAT_RESERVED_8 = 8 +IMG_NUM_FORMAT_SRGB = 9 +IMG_NUM_FORMAT_RESERVED_10 = 10 +IMG_NUM_FORMAT_RESERVED_11 = 11 +IMG_NUM_FORMAT_RESERVED_12 = 12 +IMG_NUM_FORMAT_RESERVED_13 = 13 +IMG_NUM_FORMAT_RESERVED_14 = 14 +IMG_NUM_FORMAT_RESERVED_15 = 15 +IMG_NUM_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT_FMASK' +IMG_NUM_FORMAT_FMASK__enumvalues = { + 0: 'IMG_NUM_FORMAT_FMASK_8_2_1', + 1: 'IMG_NUM_FORMAT_FMASK_8_4_1', + 2: 'IMG_NUM_FORMAT_FMASK_8_8_1', + 3: 'IMG_NUM_FORMAT_FMASK_8_2_2', + 4: 'IMG_NUM_FORMAT_FMASK_8_4_2', + 5: 'IMG_NUM_FORMAT_FMASK_8_4_4', + 6: 'IMG_NUM_FORMAT_FMASK_16_16_1', + 7: 'IMG_NUM_FORMAT_FMASK_16_8_2', + 8: 'IMG_NUM_FORMAT_FMASK_32_16_2', + 9: 'IMG_NUM_FORMAT_FMASK_32_8_4', + 10: 'IMG_NUM_FORMAT_FMASK_32_8_8', + 11: 'IMG_NUM_FORMAT_FMASK_64_16_4', + 12: 'IMG_NUM_FORMAT_FMASK_64_16_8', + 13: 'IMG_NUM_FORMAT_FMASK_RESERVED_13', + 14: 'IMG_NUM_FORMAT_FMASK_RESERVED_14', + 15: 'IMG_NUM_FORMAT_FMASK_RESERVED_15', +} +IMG_NUM_FORMAT_FMASK_8_2_1 = 0 +IMG_NUM_FORMAT_FMASK_8_4_1 = 1 +IMG_NUM_FORMAT_FMASK_8_8_1 = 2 +IMG_NUM_FORMAT_FMASK_8_2_2 = 3 +IMG_NUM_FORMAT_FMASK_8_4_2 = 4 +IMG_NUM_FORMAT_FMASK_8_4_4 = 5 +IMG_NUM_FORMAT_FMASK_16_16_1 = 6 +IMG_NUM_FORMAT_FMASK_16_8_2 = 7 +IMG_NUM_FORMAT_FMASK_32_16_2 = 8 +IMG_NUM_FORMAT_FMASK_32_8_4 = 9 +IMG_NUM_FORMAT_FMASK_32_8_8 = 10 +IMG_NUM_FORMAT_FMASK_64_16_4 = 11 +IMG_NUM_FORMAT_FMASK_64_16_8 = 12 +IMG_NUM_FORMAT_FMASK_RESERVED_13 = 13 +IMG_NUM_FORMAT_FMASK_RESERVED_14 = 14 +IMG_NUM_FORMAT_FMASK_RESERVED_15 = 15 +IMG_NUM_FORMAT_FMASK = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT_N_IN_16' +IMG_NUM_FORMAT_N_IN_16__enumvalues = { + 0: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0', + 1: 'IMG_NUM_FORMAT_N_IN_16_UNORM_10', + 2: 'IMG_NUM_FORMAT_N_IN_16_UNORM_9', + 3: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3', + 4: 'IMG_NUM_FORMAT_N_IN_16_UINT_10', + 5: 'IMG_NUM_FORMAT_N_IN_16_UINT_9', + 6: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6', + 7: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10', + 8: 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9', + 9: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9', + 10: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10', + 11: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11', + 12: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12', + 13: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13', + 14: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14', + 15: 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15', +} +IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0 +IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 1 +IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 2 +IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 3 +IMG_NUM_FORMAT_N_IN_16_UINT_10 = 4 +IMG_NUM_FORMAT_N_IN_16_UINT_9 = 5 +IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 6 +IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 7 +IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 8 +IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 9 +IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 10 +IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 11 +IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 12 +IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 13 +IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 14 +IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 15 +IMG_NUM_FORMAT_N_IN_16 = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT_ASTC_2D' +IMG_NUM_FORMAT_ASTC_2D__enumvalues = { + 0: 'IMG_NUM_FORMAT_ASTC_2D_4x4', + 1: 'IMG_NUM_FORMAT_ASTC_2D_5x4', + 2: 'IMG_NUM_FORMAT_ASTC_2D_5x5', + 3: 'IMG_NUM_FORMAT_ASTC_2D_6x5', + 4: 'IMG_NUM_FORMAT_ASTC_2D_6x6', + 5: 'IMG_NUM_FORMAT_ASTC_2D_8x5', + 6: 'IMG_NUM_FORMAT_ASTC_2D_8x6', + 7: 'IMG_NUM_FORMAT_ASTC_2D_8x8', + 8: 'IMG_NUM_FORMAT_ASTC_2D_10x5', + 9: 'IMG_NUM_FORMAT_ASTC_2D_10x6', + 10: 'IMG_NUM_FORMAT_ASTC_2D_10x8', + 11: 'IMG_NUM_FORMAT_ASTC_2D_10x10', + 12: 'IMG_NUM_FORMAT_ASTC_2D_12x10', + 13: 'IMG_NUM_FORMAT_ASTC_2D_12x12', + 14: 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_14', + 15: 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_15', +} +IMG_NUM_FORMAT_ASTC_2D_4x4 = 0 +IMG_NUM_FORMAT_ASTC_2D_5x4 = 1 +IMG_NUM_FORMAT_ASTC_2D_5x5 = 2 +IMG_NUM_FORMAT_ASTC_2D_6x5 = 3 +IMG_NUM_FORMAT_ASTC_2D_6x6 = 4 +IMG_NUM_FORMAT_ASTC_2D_8x5 = 5 +IMG_NUM_FORMAT_ASTC_2D_8x6 = 6 +IMG_NUM_FORMAT_ASTC_2D_8x8 = 7 +IMG_NUM_FORMAT_ASTC_2D_10x5 = 8 +IMG_NUM_FORMAT_ASTC_2D_10x6 = 9 +IMG_NUM_FORMAT_ASTC_2D_10x8 = 10 +IMG_NUM_FORMAT_ASTC_2D_10x10 = 11 +IMG_NUM_FORMAT_ASTC_2D_12x10 = 12 +IMG_NUM_FORMAT_ASTC_2D_12x12 = 13 +IMG_NUM_FORMAT_ASTC_2D_RESERVED_14 = 14 +IMG_NUM_FORMAT_ASTC_2D_RESERVED_15 = 15 +IMG_NUM_FORMAT_ASTC_2D = ctypes.c_uint32 # enum + +# values for enumeration 'IMG_NUM_FORMAT_ASTC_3D' +IMG_NUM_FORMAT_ASTC_3D__enumvalues = { + 0: 'IMG_NUM_FORMAT_ASTC_3D_3x3x3', + 1: 'IMG_NUM_FORMAT_ASTC_3D_4x3x3', + 2: 'IMG_NUM_FORMAT_ASTC_3D_4x4x3', + 3: 'IMG_NUM_FORMAT_ASTC_3D_4x4x4', + 4: 'IMG_NUM_FORMAT_ASTC_3D_5x4x4', + 5: 'IMG_NUM_FORMAT_ASTC_3D_5x5x4', + 6: 'IMG_NUM_FORMAT_ASTC_3D_5x5x5', + 7: 'IMG_NUM_FORMAT_ASTC_3D_6x5x5', + 8: 'IMG_NUM_FORMAT_ASTC_3D_6x6x5', + 9: 'IMG_NUM_FORMAT_ASTC_3D_6x6x6', + 10: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_10', + 11: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_11', + 12: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_12', + 13: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_13', + 14: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_14', + 15: 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_15', +} +IMG_NUM_FORMAT_ASTC_3D_3x3x3 = 0 +IMG_NUM_FORMAT_ASTC_3D_4x3x3 = 1 +IMG_NUM_FORMAT_ASTC_3D_4x4x3 = 2 +IMG_NUM_FORMAT_ASTC_3D_4x4x4 = 3 +IMG_NUM_FORMAT_ASTC_3D_5x4x4 = 4 +IMG_NUM_FORMAT_ASTC_3D_5x5x4 = 5 +IMG_NUM_FORMAT_ASTC_3D_5x5x5 = 6 +IMG_NUM_FORMAT_ASTC_3D_6x5x5 = 7 +IMG_NUM_FORMAT_ASTC_3D_6x6x5 = 8 +IMG_NUM_FORMAT_ASTC_3D_6x6x6 = 9 +IMG_NUM_FORMAT_ASTC_3D_RESERVED_10 = 10 +IMG_NUM_FORMAT_ASTC_3D_RESERVED_11 = 11 +IMG_NUM_FORMAT_ASTC_3D_RESERVED_12 = 12 +IMG_NUM_FORMAT_ASTC_3D_RESERVED_13 = 13 +IMG_NUM_FORMAT_ASTC_3D_RESERVED_14 = 14 +IMG_NUM_FORMAT_ASTC_3D_RESERVED_15 = 15 +IMG_NUM_FORMAT_ASTC_3D = ctypes.c_uint32 # enum + +# values for enumeration 'TileType' +TileType__enumvalues = { + 0: 'ARRAY_COLOR_TILE', + 1: 'ARRAY_DEPTH_TILE', +} +ARRAY_COLOR_TILE = 0 +ARRAY_DEPTH_TILE = 1 +TileType = ctypes.c_uint32 # enum + +# values for enumeration 'NonDispTilingOrder' +NonDispTilingOrder__enumvalues = { + 0: 'ADDR_SURF_MICRO_TILING_DISPLAY', + 1: 'ADDR_SURF_MICRO_TILING_NON_DISPLAY', +} +ADDR_SURF_MICRO_TILING_DISPLAY = 0 +ADDR_SURF_MICRO_TILING_NON_DISPLAY = 1 +NonDispTilingOrder = ctypes.c_uint32 # enum + +# values for enumeration 'MicroTileMode' +MicroTileMode__enumvalues = { + 0: 'ADDR_SURF_DISPLAY_MICRO_TILING', + 1: 'ADDR_SURF_THIN_MICRO_TILING', + 2: 'ADDR_SURF_DEPTH_MICRO_TILING', + 3: 'ADDR_SURF_ROTATED_MICRO_TILING', + 4: 'ADDR_SURF_THICK_MICRO_TILING', +} +ADDR_SURF_DISPLAY_MICRO_TILING = 0 +ADDR_SURF_THIN_MICRO_TILING = 1 +ADDR_SURF_DEPTH_MICRO_TILING = 2 +ADDR_SURF_ROTATED_MICRO_TILING = 3 +ADDR_SURF_THICK_MICRO_TILING = 4 +MicroTileMode = ctypes.c_uint32 # enum + +# values for enumeration 'TileSplit' +TileSplit__enumvalues = { + 0: 'ADDR_SURF_TILE_SPLIT_64B', + 1: 'ADDR_SURF_TILE_SPLIT_128B', + 2: 'ADDR_SURF_TILE_SPLIT_256B', + 3: 'ADDR_SURF_TILE_SPLIT_512B', + 4: 'ADDR_SURF_TILE_SPLIT_1KB', + 5: 'ADDR_SURF_TILE_SPLIT_2KB', + 6: 'ADDR_SURF_TILE_SPLIT_4KB', +} +ADDR_SURF_TILE_SPLIT_64B = 0 +ADDR_SURF_TILE_SPLIT_128B = 1 +ADDR_SURF_TILE_SPLIT_256B = 2 +ADDR_SURF_TILE_SPLIT_512B = 3 +ADDR_SURF_TILE_SPLIT_1KB = 4 +ADDR_SURF_TILE_SPLIT_2KB = 5 +ADDR_SURF_TILE_SPLIT_4KB = 6 +TileSplit = ctypes.c_uint32 # enum + +# values for enumeration 'SampleSplit' +SampleSplit__enumvalues = { + 0: 'ADDR_SURF_SAMPLE_SPLIT_1', + 1: 'ADDR_SURF_SAMPLE_SPLIT_2', + 2: 'ADDR_SURF_SAMPLE_SPLIT_4', + 3: 'ADDR_SURF_SAMPLE_SPLIT_8', +} +ADDR_SURF_SAMPLE_SPLIT_1 = 0 +ADDR_SURF_SAMPLE_SPLIT_2 = 1 +ADDR_SURF_SAMPLE_SPLIT_4 = 2 +ADDR_SURF_SAMPLE_SPLIT_8 = 3 +SampleSplit = ctypes.c_uint32 # enum + +# values for enumeration 'PipeConfig' +PipeConfig__enumvalues = { + 0: 'ADDR_SURF_P2', + 1: 'ADDR_SURF_P2_RESERVED0', + 2: 'ADDR_SURF_P2_RESERVED1', + 3: 'ADDR_SURF_P2_RESERVED2', + 4: 'ADDR_SURF_P4_8x16', + 5: 'ADDR_SURF_P4_16x16', + 6: 'ADDR_SURF_P4_16x32', + 7: 'ADDR_SURF_P4_32x32', + 8: 'ADDR_SURF_P8_16x16_8x16', + 9: 'ADDR_SURF_P8_16x32_8x16', + 10: 'ADDR_SURF_P8_32x32_8x16', + 11: 'ADDR_SURF_P8_16x32_16x16', + 12: 'ADDR_SURF_P8_32x32_16x16', + 13: 'ADDR_SURF_P8_32x32_16x32', + 14: 'ADDR_SURF_P8_32x64_32x32', + 15: 'ADDR_SURF_P8_RESERVED0', + 16: 'ADDR_SURF_P16_32x32_8x16', + 17: 'ADDR_SURF_P16_32x32_16x16', +} +ADDR_SURF_P2 = 0 +ADDR_SURF_P2_RESERVED0 = 1 +ADDR_SURF_P2_RESERVED1 = 2 +ADDR_SURF_P2_RESERVED2 = 3 +ADDR_SURF_P4_8x16 = 4 +ADDR_SURF_P4_16x16 = 5 +ADDR_SURF_P4_16x32 = 6 +ADDR_SURF_P4_32x32 = 7 +ADDR_SURF_P8_16x16_8x16 = 8 +ADDR_SURF_P8_16x32_8x16 = 9 +ADDR_SURF_P8_32x32_8x16 = 10 +ADDR_SURF_P8_16x32_16x16 = 11 +ADDR_SURF_P8_32x32_16x16 = 12 +ADDR_SURF_P8_32x32_16x32 = 13 +ADDR_SURF_P8_32x64_32x32 = 14 +ADDR_SURF_P8_RESERVED0 = 15 +ADDR_SURF_P16_32x32_8x16 = 16 +ADDR_SURF_P16_32x32_16x16 = 17 +PipeConfig = ctypes.c_uint32 # enum + +# values for enumeration 'SeEnable' +SeEnable__enumvalues = { + 0: 'ADDR_CONFIG_DISABLE_SE', + 1: 'ADDR_CONFIG_ENABLE_SE', +} +ADDR_CONFIG_DISABLE_SE = 0 +ADDR_CONFIG_ENABLE_SE = 1 +SeEnable = ctypes.c_uint32 # enum + +# values for enumeration 'NumBanks' +NumBanks__enumvalues = { + 0: 'ADDR_SURF_2_BANK', + 1: 'ADDR_SURF_4_BANK', + 2: 'ADDR_SURF_8_BANK', + 3: 'ADDR_SURF_16_BANK', +} +ADDR_SURF_2_BANK = 0 +ADDR_SURF_4_BANK = 1 +ADDR_SURF_8_BANK = 2 +ADDR_SURF_16_BANK = 3 +NumBanks = ctypes.c_uint32 # enum + +# values for enumeration 'BankWidth' +BankWidth__enumvalues = { + 0: 'ADDR_SURF_BANK_WIDTH_1', + 1: 'ADDR_SURF_BANK_WIDTH_2', + 2: 'ADDR_SURF_BANK_WIDTH_4', + 3: 'ADDR_SURF_BANK_WIDTH_8', +} +ADDR_SURF_BANK_WIDTH_1 = 0 +ADDR_SURF_BANK_WIDTH_2 = 1 +ADDR_SURF_BANK_WIDTH_4 = 2 +ADDR_SURF_BANK_WIDTH_8 = 3 +BankWidth = ctypes.c_uint32 # enum + +# values for enumeration 'BankHeight' +BankHeight__enumvalues = { + 0: 'ADDR_SURF_BANK_HEIGHT_1', + 1: 'ADDR_SURF_BANK_HEIGHT_2', + 2: 'ADDR_SURF_BANK_HEIGHT_4', + 3: 'ADDR_SURF_BANK_HEIGHT_8', +} +ADDR_SURF_BANK_HEIGHT_1 = 0 +ADDR_SURF_BANK_HEIGHT_2 = 1 +ADDR_SURF_BANK_HEIGHT_4 = 2 +ADDR_SURF_BANK_HEIGHT_8 = 3 +BankHeight = ctypes.c_uint32 # enum + +# values for enumeration 'BankWidthHeight' +BankWidthHeight__enumvalues = { + 0: 'ADDR_SURF_BANK_WH_1', + 1: 'ADDR_SURF_BANK_WH_2', + 2: 'ADDR_SURF_BANK_WH_4', + 3: 'ADDR_SURF_BANK_WH_8', +} +ADDR_SURF_BANK_WH_1 = 0 +ADDR_SURF_BANK_WH_2 = 1 +ADDR_SURF_BANK_WH_4 = 2 +ADDR_SURF_BANK_WH_8 = 3 +BankWidthHeight = ctypes.c_uint32 # enum + +# values for enumeration 'MacroTileAspect' +MacroTileAspect__enumvalues = { + 0: 'ADDR_SURF_MACRO_ASPECT_1', + 1: 'ADDR_SURF_MACRO_ASPECT_2', + 2: 'ADDR_SURF_MACRO_ASPECT_4', + 3: 'ADDR_SURF_MACRO_ASPECT_8', +} +ADDR_SURF_MACRO_ASPECT_1 = 0 +ADDR_SURF_MACRO_ASPECT_2 = 1 +ADDR_SURF_MACRO_ASPECT_4 = 2 +ADDR_SURF_MACRO_ASPECT_8 = 3 +MacroTileAspect = ctypes.c_uint32 # enum + +# values for enumeration 'GATCL1RequestType' +GATCL1RequestType__enumvalues = { + 0: 'GATCL1_TYPE_NORMAL', + 1: 'GATCL1_TYPE_SHOOTDOWN', + 2: 'GATCL1_TYPE_BYPASS', +} +GATCL1_TYPE_NORMAL = 0 +GATCL1_TYPE_SHOOTDOWN = 1 +GATCL1_TYPE_BYPASS = 2 +GATCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1RequestType' +UTCL1RequestType__enumvalues = { + 0: 'UTCL1_TYPE_NORMAL', + 1: 'UTCL1_TYPE_SHOOTDOWN', + 2: 'UTCL1_TYPE_BYPASS', +} +UTCL1_TYPE_NORMAL = 0 +UTCL1_TYPE_SHOOTDOWN = 1 +UTCL1_TYPE_BYPASS = 2 +UTCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1FaultType' +UTCL1FaultType__enumvalues = { + 0: 'UTCL1_XNACK_SUCCESS', + 1: 'UTCL1_XNACK_RETRY', + 2: 'UTCL1_XNACK_PRT', + 3: 'UTCL1_XNACK_NO_RETRY', +} +UTCL1_XNACK_SUCCESS = 0 +UTCL1_XNACK_RETRY = 1 +UTCL1_XNACK_PRT = 2 +UTCL1_XNACK_NO_RETRY = 3 +UTCL1FaultType = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_CACHE_POLICIES' +TCC_CACHE_POLICIES__enumvalues = { + 0: 'TCC_CACHE_POLICY_LRU', + 1: 'TCC_CACHE_POLICY_STREAM', +} +TCC_CACHE_POLICY_LRU = 0 +TCC_CACHE_POLICY_STREAM = 1 +TCC_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'MTYPE' +MTYPE__enumvalues = { + 0: 'MTYPE_NC', + 1: 'MTYPE_WC', + 1: 'MTYPE_RW', + 2: 'MTYPE_CC', + 3: 'MTYPE_UC', +} +MTYPE_NC = 0 +MTYPE_WC = 1 +MTYPE_RW = 1 +MTYPE_CC = 2 +MTYPE_UC = 3 +MTYPE = ctypes.c_uint32 # enum + +# values for enumeration 'RMI_CID' +RMI_CID__enumvalues = { + 0: 'RMI_CID_CC', + 1: 'RMI_CID_FC', + 2: 'RMI_CID_CM', + 3: 'RMI_CID_DC', + 4: 'RMI_CID_Z', + 5: 'RMI_CID_S', + 6: 'RMI_CID_TILE', + 7: 'RMI_CID_ZPCPSD', +} +RMI_CID_CC = 0 +RMI_CID_FC = 1 +RMI_CID_CM = 2 +RMI_CID_DC = 3 +RMI_CID_Z = 4 +RMI_CID_S = 5 +RMI_CID_TILE = 6 +RMI_CID_ZPCPSD = 7 +RMI_CID = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_COUNTER_MODE' +PERFMON_COUNTER_MODE__enumvalues = { + 0: 'PERFMON_COUNTER_MODE_ACCUM', + 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 2: 'PERFMON_COUNTER_MODE_MAX', + 3: 'PERFMON_COUNTER_MODE_DIRTY', + 4: 'PERFMON_COUNTER_MODE_SAMPLE', + 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 15: 'PERFMON_COUNTER_MODE_RESERVED', +} +PERFMON_COUNTER_MODE_ACCUM = 0 +PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 +PERFMON_COUNTER_MODE_MAX = 2 +PERFMON_COUNTER_MODE_DIRTY = 3 +PERFMON_COUNTER_MODE_SAMPLE = 4 +PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 +PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 +PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 +PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 +PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 +PERFMON_COUNTER_MODE_RESERVED = 15 +PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_SPM_MODE' +PERFMON_SPM_MODE__enumvalues = { + 0: 'PERFMON_SPM_MODE_OFF', + 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', + 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', + 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 5: 'PERFMON_SPM_MODE_RESERVED_5', + 6: 'PERFMON_SPM_MODE_RESERVED_6', + 7: 'PERFMON_SPM_MODE_RESERVED_7', + 8: 'PERFMON_SPM_MODE_TEST_MODE_0', + 9: 'PERFMON_SPM_MODE_TEST_MODE_1', + 10: 'PERFMON_SPM_MODE_TEST_MODE_2', +} +PERFMON_SPM_MODE_OFF = 0 +PERFMON_SPM_MODE_16BIT_CLAMP = 1 +PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 +PERFMON_SPM_MODE_32BIT_CLAMP = 3 +PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 +PERFMON_SPM_MODE_RESERVED_5 = 5 +PERFMON_SPM_MODE_RESERVED_6 = 6 +PERFMON_SPM_MODE_RESERVED_7 = 7 +PERFMON_SPM_MODE_TEST_MODE_0 = 8 +PERFMON_SPM_MODE_TEST_MODE_1 = 9 +PERFMON_SPM_MODE_TEST_MODE_2 = 10 +PERFMON_SPM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceTiling' +SurfaceTiling__enumvalues = { + 0: 'ARRAY_LINEAR', + 1: 'ARRAY_TILED', +} +ARRAY_LINEAR = 0 +ARRAY_TILED = 1 +SurfaceTiling = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceArray' +SurfaceArray__enumvalues = { + 0: 'ARRAY_1D', + 1: 'ARRAY_2D', + 2: 'ARRAY_3D', + 3: 'ARRAY_3D_SLICE', +} +ARRAY_1D = 0 +ARRAY_2D = 1 +ARRAY_3D = 2 +ARRAY_3D_SLICE = 3 +SurfaceArray = ctypes.c_uint32 # enum + +# values for enumeration 'ColorArray' +ColorArray__enumvalues = { + 0: 'ARRAY_2D_ALT_COLOR', + 1: 'ARRAY_2D_COLOR', + 3: 'ARRAY_3D_SLICE_COLOR', +} +ARRAY_2D_ALT_COLOR = 0 +ARRAY_2D_COLOR = 1 +ARRAY_3D_SLICE_COLOR = 3 +ColorArray = ctypes.c_uint32 # enum + +# values for enumeration 'DepthArray' +DepthArray__enumvalues = { + 0: 'ARRAY_2D_ALT_DEPTH', + 1: 'ARRAY_2D_DEPTH', +} +ARRAY_2D_ALT_DEPTH = 0 +ARRAY_2D_DEPTH = 1 +DepthArray = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_NUM_SIMD_PER_CU' +ENUM_NUM_SIMD_PER_CU__enumvalues = { + 4: 'NUM_SIMD_PER_CU', +} +NUM_SIMD_PER_CU = 4 +ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_ENABLE_ERROR_INJECT' +DSM_ENABLE_ERROR_INJECT__enumvalues = { + 0: 'DSM_ENABLE_ERROR_INJECT_FED_IN', + 1: 'DSM_ENABLE_ERROR_INJECT_SINGLE', + 2: 'DSM_ENABLE_ERROR_INJECT_DOUBLE', + 3: 'DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED', +} +DSM_ENABLE_ERROR_INJECT_FED_IN = 0 +DSM_ENABLE_ERROR_INJECT_SINGLE = 1 +DSM_ENABLE_ERROR_INJECT_DOUBLE = 2 +DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED = 3 +DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_SELECT_INJECT_DELAY' +DSM_SELECT_INJECT_DELAY__enumvalues = { + 0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY', + 1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', +} +DSM_SELECT_INJECT_DELAY_NO_DELAY = 0 +DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1 +DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'SWIZZLE_TYPE_ENUM' +SWIZZLE_TYPE_ENUM__enumvalues = { + 0: 'SW_Z', + 1: 'SW_S', + 2: 'SW_D', + 3: 'SW_R', + 4: 'SW_L', +} +SW_Z = 0 +SW_S = 1 +SW_D = 2 +SW_R = 3 +SW_L = 4 +SWIZZLE_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'TC_MICRO_TILE_MODE' +TC_MICRO_TILE_MODE__enumvalues = { + 0: 'MICRO_TILE_MODE_LINEAR', + 1: 'MICRO_TILE_MODE_ROTATED', + 2: 'MICRO_TILE_MODE_STD_2D', + 3: 'MICRO_TILE_MODE_STD_3D', + 4: 'MICRO_TILE_MODE_DISPLAY_2D', + 5: 'MICRO_TILE_MODE_DISPLAY_3D', + 6: 'MICRO_TILE_MODE_Z_2D', + 7: 'MICRO_TILE_MODE_Z_3D', +} +MICRO_TILE_MODE_LINEAR = 0 +MICRO_TILE_MODE_ROTATED = 1 +MICRO_TILE_MODE_STD_2D = 2 +MICRO_TILE_MODE_STD_3D = 3 +MICRO_TILE_MODE_DISPLAY_2D = 4 +MICRO_TILE_MODE_DISPLAY_3D = 5 +MICRO_TILE_MODE_Z_2D = 6 +MICRO_TILE_MODE_Z_3D = 7 +TC_MICRO_TILE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SWIZZLE_MODE_ENUM' +SWIZZLE_MODE_ENUM__enumvalues = { + 0: 'SW_LINEAR', + 1: 'SW_256B_S', + 2: 'SW_256B_D', + 3: 'SW_256B_R', + 4: 'SW_4KB_Z', + 5: 'SW_4KB_S', + 6: 'SW_4KB_D', + 7: 'SW_4KB_R', + 8: 'SW_64KB_Z', + 9: 'SW_64KB_S', + 10: 'SW_64KB_D', + 11: 'SW_64KB_R', + 12: 'SW_VAR_Z', + 13: 'SW_VAR_S', + 14: 'SW_VAR_D', + 15: 'SW_VAR_R', + 16: 'SW_RESERVED_16', + 17: 'SW_RESERVED_17', + 18: 'SW_RESERVED_18', + 19: 'SW_RESERVED_19', + 20: 'SW_4KB_Z_X', + 21: 'SW_4KB_S_X', + 22: 'SW_4KB_D_X', + 23: 'SW_4KB_R_X', + 24: 'SW_64KB_Z_X', + 25: 'SW_64KB_S_X', + 26: 'SW_64KB_D_X', + 27: 'SW_64KB_R_X', + 28: 'SW_VAR_Z_X', + 29: 'SW_VAR_S_X', + 30: 'SW_VAR_D_X', + 31: 'SW_VAR_R_X', + 32: 'SW_RESERVED_12', + 33: 'SW_RESERVED_13', + 34: 'SW_RESERVED_14', + 35: 'SW_RESERVED_15', +} +SW_LINEAR = 0 +SW_256B_S = 1 +SW_256B_D = 2 +SW_256B_R = 3 +SW_4KB_Z = 4 +SW_4KB_S = 5 +SW_4KB_D = 6 +SW_4KB_R = 7 +SW_64KB_Z = 8 +SW_64KB_S = 9 +SW_64KB_D = 10 +SW_64KB_R = 11 +SW_VAR_Z = 12 +SW_VAR_S = 13 +SW_VAR_D = 14 +SW_VAR_R = 15 +SW_RESERVED_16 = 16 +SW_RESERVED_17 = 17 +SW_RESERVED_18 = 18 +SW_RESERVED_19 = 19 +SW_4KB_Z_X = 20 +SW_4KB_S_X = 21 +SW_4KB_D_X = 22 +SW_4KB_R_X = 23 +SW_64KB_Z_X = 24 +SW_64KB_S_X = 25 +SW_64KB_D_X = 26 +SW_64KB_R_X = 27 +SW_VAR_Z_X = 28 +SW_VAR_S_X = 29 +SW_VAR_D_X = 30 +SW_VAR_R_X = 31 +SW_RESERVED_12 = 32 +SW_RESERVED_13 = 33 +SW_RESERVED_14 = 34 +SW_RESERVED_15 = 35 +SWIZZLE_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'PipeTiling' +PipeTiling__enumvalues = { + 0: 'CONFIG_1_PIPE', + 1: 'CONFIG_2_PIPE', + 2: 'CONFIG_4_PIPE', + 3: 'CONFIG_8_PIPE', +} +CONFIG_1_PIPE = 0 +CONFIG_2_PIPE = 1 +CONFIG_4_PIPE = 2 +CONFIG_8_PIPE = 3 +PipeTiling = ctypes.c_uint32 # enum + +# values for enumeration 'BankTiling' +BankTiling__enumvalues = { + 0: 'CONFIG_4_BANK', + 1: 'CONFIG_8_BANK', +} +CONFIG_4_BANK = 0 +CONFIG_8_BANK = 1 +BankTiling = ctypes.c_uint32 # enum + +# values for enumeration 'GroupInterleave' +GroupInterleave__enumvalues = { + 0: 'CONFIG_256B_GROUP', + 1: 'CONFIG_512B_GROUP', +} +CONFIG_256B_GROUP = 0 +CONFIG_512B_GROUP = 1 +GroupInterleave = ctypes.c_uint32 # enum + +# values for enumeration 'RowTiling' +RowTiling__enumvalues = { + 0: 'CONFIG_1KB_ROW', + 1: 'CONFIG_2KB_ROW', + 2: 'CONFIG_4KB_ROW', + 3: 'CONFIG_8KB_ROW', + 4: 'CONFIG_1KB_ROW_OPT', + 5: 'CONFIG_2KB_ROW_OPT', + 6: 'CONFIG_4KB_ROW_OPT', + 7: 'CONFIG_8KB_ROW_OPT', +} +CONFIG_1KB_ROW = 0 +CONFIG_2KB_ROW = 1 +CONFIG_4KB_ROW = 2 +CONFIG_8KB_ROW = 3 +CONFIG_1KB_ROW_OPT = 4 +CONFIG_2KB_ROW_OPT = 5 +CONFIG_4KB_ROW_OPT = 6 +CONFIG_8KB_ROW_OPT = 7 +RowTiling = ctypes.c_uint32 # enum + +# values for enumeration 'BankSwapBytes' +BankSwapBytes__enumvalues = { + 0: 'CONFIG_128B_SWAPS', + 1: 'CONFIG_256B_SWAPS', + 2: 'CONFIG_512B_SWAPS', + 3: 'CONFIG_1KB_SWAPS', +} +CONFIG_128B_SWAPS = 0 +CONFIG_256B_SWAPS = 1 +CONFIG_512B_SWAPS = 2 +CONFIG_1KB_SWAPS = 3 +BankSwapBytes = ctypes.c_uint32 # enum + +# values for enumeration 'SampleSplitBytes' +SampleSplitBytes__enumvalues = { + 0: 'CONFIG_1KB_SPLIT', + 1: 'CONFIG_2KB_SPLIT', + 2: 'CONFIG_4KB_SPLIT', + 3: 'CONFIG_8KB_SPLIT', +} +CONFIG_1KB_SPLIT = 0 +CONFIG_2KB_SPLIT = 1 +CONFIG_4KB_SPLIT = 2 +CONFIG_8KB_SPLIT = 3 +SampleSplitBytes = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_MODE' +BLNDV_CONTROL_BLND_MODE__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', + 1: 'BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', + 2: 'BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', + 3: 'BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', +} +BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0 +BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 1 +BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 2 +BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 3 +BLNDV_CONTROL_BLND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_STEREO_TYPE' +BLNDV_CONTROL_BLND_STEREO_TYPE__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', + 1: 'BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', + 2: 'BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', + 3: 'BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED', +} +BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0 +BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 1 +BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 2 +BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 3 +BLNDV_CONTROL_BLND_STEREO_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_STEREO_POLARITY' +BLNDV_CONTROL_BLND_STEREO_POLARITY__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW', + 1: 'BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH', +} +BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0 +BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 1 +BLNDV_CONTROL_BLND_STEREO_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN' +BLNDV_CONTROL_BLND_FEEDTHROUGH_EN__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', + 1: 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', +} +BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0 +BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 1 +BLNDV_CONTROL_BLND_FEEDTHROUGH_EN = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_ALPHA_MODE' +BLNDV_CONTROL_BLND_ALPHA_MODE__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', + 1: 'BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 2: 'BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', + 3: 'BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED', +} +BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0 +BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 +BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 2 +BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 3 +BLNDV_CONTROL_BLND_ALPHA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY' +BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE', + 1: 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE', +} +BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0 +BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 1 +BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE' +BLNDV_CONTROL_BLND_MULTIPLIED_MODE__enumvalues = { + 0: 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE', + 1: 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE', +} +BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0 +BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 1 +BLNDV_CONTROL_BLND_MULTIPLIED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_SM_CONTROL2_SM_MODE' +BLNDV_SM_CONTROL2_SM_MODE__enumvalues = { + 0: 'BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE', + 2: 'BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', + 4: 'BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', + 6: 'BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', +} +BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0 +BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 2 +BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 4 +BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 +BLNDV_SM_CONTROL2_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE' +BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE__enumvalues = { + 0: 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', + 1: 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', +} +BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0 +BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 1 +BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE' +BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE__enumvalues = { + 0: 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', + 1: 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', +} +BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0 +BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 1 +BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL' +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL__enumvalues = { + 0: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 1: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 2: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 3: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', +} +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL' +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL__enumvalues = { + 0: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 1: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', + 2: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 3: 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', +} +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 +BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL2_PTI_ENABLE' +BLNDV_CONTROL2_PTI_ENABLE__enumvalues = { + 0: 'BLNDV_CONTROL2_PTI_ENABLE_FALSE', + 1: 'BLNDV_CONTROL2_PTI_ENABLE_TRUE', +} +BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0 +BLNDV_CONTROL2_PTI_ENABLE_TRUE = 1 +BLNDV_CONTROL2_PTI_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN' +BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN__enumvalues = { + 0: 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', + 1: 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', +} +BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0 +BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 1 +BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN' +BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN__enumvalues = { + 0: 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', + 1: 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', +} +BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0 +BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 1 +BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK' +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK__enumvalues = { + 0: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', + 1: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', +} +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0 +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 1 +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK' +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK__enumvalues = { + 0: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', + 1: 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', +} +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0 +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 1 +BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK' +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK' +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK' +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK' +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK' +BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK' +BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE' +BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE__enumvalues = { + 0: 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', + 1: 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', +} +BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0 +BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 1 +BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT' +BLNDV_DEBUG_BLND_CNV_MUX_SELECT__enumvalues = { + 0: 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW', + 1: 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH', +} +BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0 +BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 1 +BLNDV_DEBUG_BLND_CNV_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN' +BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', +} +BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0 +BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 1 +BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_PIXEL_DEPTH' +LBV_PIXEL_DEPTH__enumvalues = { + 0: 'PIXEL_DEPTH_30BPP', + 1: 'PIXEL_DEPTH_24BPP', + 2: 'PIXEL_DEPTH_18BPP', + 3: 'PIXEL_DEPTH_38BPP', +} +PIXEL_DEPTH_30BPP = 0 +PIXEL_DEPTH_24BPP = 1 +PIXEL_DEPTH_18BPP = 2 +PIXEL_DEPTH_38BPP = 3 +LBV_PIXEL_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_PIXEL_EXPAN_MODE' +LBV_PIXEL_EXPAN_MODE__enumvalues = { + 0: 'PIXEL_EXPAN_MODE_ZERO_EXP', + 1: 'PIXEL_EXPAN_MODE_DYN_EXP', +} +PIXEL_EXPAN_MODE_ZERO_EXP = 0 +PIXEL_EXPAN_MODE_DYN_EXP = 1 +LBV_PIXEL_EXPAN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_INTERLEAVE_EN' +LBV_INTERLEAVE_EN__enumvalues = { + 0: 'INTERLEAVE_DIS', + 1: 'INTERLEAVE_EN', +} +INTERLEAVE_DIS = 0 +INTERLEAVE_EN = 1 +LBV_INTERLEAVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_PIXEL_REDUCE_MODE' +LBV_PIXEL_REDUCE_MODE__enumvalues = { + 0: 'PIXEL_REDUCE_MODE_TRUNCATION', + 1: 'PIXEL_REDUCE_MODE_ROUNDING', +} +PIXEL_REDUCE_MODE_TRUNCATION = 0 +PIXEL_REDUCE_MODE_ROUNDING = 1 +LBV_PIXEL_REDUCE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_DYNAMIC_PIXEL_DEPTH' +LBV_DYNAMIC_PIXEL_DEPTH__enumvalues = { + 0: 'DYNAMIC_PIXEL_DEPTH_36BPP', + 1: 'DYNAMIC_PIXEL_DEPTH_30BPP', +} +DYNAMIC_PIXEL_DEPTH_36BPP = 0 +DYNAMIC_PIXEL_DEPTH_30BPP = 1 +LBV_DYNAMIC_PIXEL_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_DITHER_EN' +LBV_DITHER_EN__enumvalues = { + 0: 'DITHER_DIS', + 1: 'DITHER_EN', +} +DITHER_DIS = 0 +DITHER_EN = 1 +LBV_DITHER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_DOWNSCALE_PREFETCH_EN' +LBV_DOWNSCALE_PREFETCH_EN__enumvalues = { + 0: 'DOWNSCALE_PREFETCH_DIS', + 1: 'DOWNSCALE_PREFETCH_EN', +} +DOWNSCALE_PREFETCH_DIS = 0 +DOWNSCALE_PREFETCH_EN = 1 +LBV_DOWNSCALE_PREFETCH_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_MEMORY_CONFIG' +LBV_MEMORY_CONFIG__enumvalues = { + 0: 'MEMORY_CONFIG_0', + 1: 'MEMORY_CONFIG_1', + 2: 'MEMORY_CONFIG_2', + 3: 'MEMORY_CONFIG_3', +} +MEMORY_CONFIG_0 = 0 +MEMORY_CONFIG_1 = 1 +MEMORY_CONFIG_2 = 2 +MEMORY_CONFIG_3 = 3 +LBV_MEMORY_CONFIG = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_SYNC_RESET_SEL2' +LBV_SYNC_RESET_SEL2__enumvalues = { + 0: 'SYNC_RESET_SEL2_VBLANK', + 1: 'SYNC_RESET_SEL2_VSYNC', +} +SYNC_RESET_SEL2_VBLANK = 0 +SYNC_RESET_SEL2_VSYNC = 1 +LBV_SYNC_RESET_SEL2 = ctypes.c_uint32 # enum + +# values for enumeration 'LBV_SYNC_DURATION' +LBV_SYNC_DURATION__enumvalues = { + 0: 'SYNC_DURATION_16', + 1: 'SYNC_DURATION_32', + 2: 'SYNC_DURATION_64', + 3: 'SYNC_DURATION_128', +} +SYNC_DURATION_16 = 0 +SYNC_DURATION_32 = 1 +SYNC_DURATION_64 = 2 +SYNC_DURATION_128 = 3 +LBV_SYNC_DURATION = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_START_POINT_CNTL' +CRTC_CONTROL_CRTC_START_POINT_CNTL__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL', + 1: 'CRTC_CONTROL_CRTC_START_POINT_CNTL_DP', +} +CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0 +CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 1 +CRTC_CONTROL_CRTC_START_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL' +CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL', + 1: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP', +} +CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0 +CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 1 +CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL' +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE', + 1: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 2: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED', + 3: 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST', +} +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0 +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 2 +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 +CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY' +CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE', + 1: 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE', +} +CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0 +CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 1 +CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE' +CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE', + 1: 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE', +} +CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE = 0 +CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 1 +CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_SOF_PULL_EN' +CRTC_CONTROL_CRTC_SOF_PULL_EN__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE', + 1: 'CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE', +} +CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0 +CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 1 +CRTC_CONTROL_CRTC_SOF_PULL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL' +CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL__enumvalues = { + 0: 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE', + 1: 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE', +} +CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0 +CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 1 +CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL' +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL__enumvalues = { + 0: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE', + 1: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE', +} +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0 +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 1 +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL' +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL__enumvalues = { + 0: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE', + 1: 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE', +} +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0 +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 1 +CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN' +CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN__enumvalues = { + 0: 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE', + 1: 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE', +} +CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0 +CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE = 1 +CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC' +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { + 0: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 1: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', +} +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT' +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT__enumvalues = { + 0: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE', + 1: 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE', +} +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0 +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE = 1 +CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK' +CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__enumvalues = { + 0: 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE', + 1: 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE', +} +CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0 +CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 1 +CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR' +CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR__enumvalues = { + 0: 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE', + 1: 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE', +} +CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0 +CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE = 1 +CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL' +CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL__enumvalues = { + 0: 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE', + 1: 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE', +} +CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0 +CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 1 +CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN' +CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN__enumvalues = { + 0: 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE', + 1: 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE', +} +CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0 +CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 1 +CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT' +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT__enumvalues = { + 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER', + 2: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER', + 5: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF', + 6: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE', + 7: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA', + 8: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA', + 9: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB', + 10: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB', + 11: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1', + 12: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2', + 13: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD', + 14: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC', + 16: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0', + 17: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1', + 18: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2', + 19: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON', + 20: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA', + 21: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB', + 22: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW', + 23: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW', +} +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER = 1 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER = 2 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF = 5 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE = 6 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 7 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 8 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 9 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 10 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 11 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 12 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD = 13 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC = 14 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 16 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 17 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 18 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 19 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA = 20 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB = 21 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW = 22 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW = 23 +CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT' +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT__enumvalues = { + 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE', + 2: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA', + 3: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB', + 4: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA', + 5: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB', + 6: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO', + 7: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC', +} +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE = 1 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA = 2 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB = 3 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA = 4 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB = 5 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 6 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC = 7 +CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN' +CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN__enumvalues = { + 0: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE', + 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE', +} +CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 +CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 +CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR' +CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR__enumvalues = { + 0: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE', + 1: 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE', +} +CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0 +CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 1 +CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT' +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT__enumvalues = { + 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER', + 2: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER', + 5: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF', + 6: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE', + 7: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA', + 8: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA', + 9: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB', + 10: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB', + 11: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1', + 12: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2', + 13: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD', + 14: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC', + 16: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0', + 17: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1', + 18: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2', + 19: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON', + 20: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA', + 21: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB', + 22: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW', + 23: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW', +} +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER = 1 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER = 2 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF = 5 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE = 6 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 7 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 8 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 9 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 10 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 11 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 12 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD = 13 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC = 14 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 16 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 17 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 18 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 19 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA = 20 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB = 21 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW = 22 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW = 23 +CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT' +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT__enumvalues = { + 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE', + 2: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA', + 3: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB', + 4: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA', + 5: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB', + 6: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO', + 7: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC', +} +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE = 1 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA = 2 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB = 3 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA = 4 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB = 5 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 6 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC = 7 +CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN' +CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN__enumvalues = { + 0: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE', + 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE', +} +CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 +CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 +CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR' +CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR__enumvalues = { + 0: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE', + 1: 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE', +} +CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0 +CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 1 +CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE' +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE__enumvalues = { + 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE', + 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT', + 2: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 3: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED', +} +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE = 0 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT = 1 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED = 3 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK' +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK__enumvalues = { + 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE', + 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE', +} +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE = 0 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE = 1 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL' +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { + 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE', +} +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR' +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR__enumvalues = { + 0: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE', + 1: 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE', +} +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE = 1 +CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT' +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { + 0: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 1: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 2: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 3: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 4: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 5: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 6: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 7: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 8: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 9: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK', + 10: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL', + 11: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 12: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 13: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 14: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 15: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC', +} +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 1 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 2 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 3 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 4 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 5 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 6 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 7 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 8 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK = 9 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL = 10 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 11 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 12 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 13 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 14 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 15 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY' +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY__enumvalues = { + 0: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE', + 1: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE', +} +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE = 0 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE = 1 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY' +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY__enumvalues = { + 0: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE', + 1: 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE', +} +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE = 0 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE = 1 +CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE' +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE__enumvalues = { + 0: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO', + 1: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT', + 2: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT', + 3: 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED', +} +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO = 0 +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT = 1 +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT = 2 +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED = 3 +CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CONTROL_CRTC_MASTER_EN' +CRTC_CONTROL_CRTC_MASTER_EN__enumvalues = { + 0: 'CRTC_CONTROL_CRTC_MASTER_EN_FALSE', + 1: 'CRTC_CONTROL_CRTC_MASTER_EN_TRUE', +} +CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0 +CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 1 +CRTC_CONTROL_CRTC_MASTER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN' +CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN__enumvalues = { + 0: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE', + 1: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE', +} +CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0 +CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 1 +CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE' +CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE__enumvalues = { + 0: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE', + 1: 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE', +} +CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0 +CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 1 +CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE' +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE__enumvalues = { + 0: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE', + 1: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE', +} +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE = 0 +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE = 1 +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD' +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { + 0: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT', + 1: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD', + 2: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN', + 3: 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2', +} +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD = 1 +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN = 2 +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 +CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY' +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY__enumvalues = { + 0: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE', + 1: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE', +} +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0 +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 1 +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT' +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT__enumvalues = { + 0: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE', + 1: 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE', +} +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE = 0 +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE = 1 +CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN' +CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN__enumvalues = { + 0: 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE', + 1: 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE', +} +CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0 +CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 1 +CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE' +CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { + 0: 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 1: 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', +} +CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 +CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 +CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR' +CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { + 0: 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 1: 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', +} +CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 +CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 +CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE' +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE__enumvalues = { + 0: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE', + 1: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 2: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 3: 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED', +} +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 +CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY' +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { + 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE', +} +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY' +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY__enumvalues = { + 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE', + 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE', +} +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE = 0 +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE = 1 +CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY' +CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY__enumvalues = { + 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE', + 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE', +} +CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE = 0 +CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE = 1 +CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN' +CRTC_STEREO_CONTROL_CRTC_STEREO_EN__enumvalues = { + 0: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE', + 1: 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE', +} +CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0 +CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 1 +CRTC_STEREO_CONTROL_CRTC_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR' +CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR__enumvalues = { + 0: 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE', + 1: 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE', +} +CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0 +CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 1 +CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL' +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { + 0: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 1: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 2: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 3: 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', +} +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 +CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY' +CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY__enumvalues = { + 0: 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE', + 1: 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE', +} +CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0 +CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE = 1 +CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY' +CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY__enumvalues = { + 0: 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE', + 1: 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE', +} +CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0 +CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE = 1 +CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN' +CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN__enumvalues = { + 0: 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE', + 1: 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE', +} +CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE = 0 +CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE = 1 +CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN' +CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN__enumvalues = { + 0: 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE', + 1: 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE', +} +CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0 +CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 1 +CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK' +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE' +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { + 0: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 1: 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE', +} +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 +CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK' +CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK__enumvalues = { + 0: 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE', + 1: 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE', +} +CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0 +CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 1 +CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY' +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY__enumvalues = { + 0: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE', + 1: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE', +} +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE = 0 +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE = 1 +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN' +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__enumvalues = { + 0: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE', + 1: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE', +} +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0 +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 1 +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE' +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE__enumvalues = { + 0: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0', + 1: 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1', +} +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0 +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 1 +CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE' +CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE__enumvalues = { + 0: 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE', + 1: 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE', +} +CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0 +CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE = 1 +CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN' +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN__enumvalues = { + 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE', + 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE', +} +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE = 0 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE = 1 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE' +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE__enumvalues = { + 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB', + 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601', + 2: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709', + 3: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS', + 4: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS', + 5: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB', + 6: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB', + 7: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS', +} +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB = 0 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601 = 1 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709 = 2 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS = 3 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS = 4 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB = 5 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB = 6 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS = 7 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE' +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE__enumvalues = { + 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE', + 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE', +} +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE = 0 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE = 1 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT' +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT__enumvalues = { + 0: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC', + 1: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC', + 2: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC', + 3: 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED', +} +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC = 0 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC = 1 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC = 2 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED = 3 +CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', +} +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK' +MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE', + 1: 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE', +} +MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE = 0 +MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE = 1 +MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK' +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE', + 1: 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE', +} +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0 +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 1 +MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE' +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE__enumvalues = { + 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN', + 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA', + 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA', + 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE', +} +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0 +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 1 +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 2 +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 3 +MASTER_UPDATE_MODE_MASTER_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { + 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN', + 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD', + 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', +} +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN = 1 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD = 2 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE' +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE__enumvalues = { + 0: 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE', + 1: 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG', + 2: 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL', +} +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE = 0 +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG = 1 +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL = 2 +CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR' +CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR__enumvalues = { + 0: 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE', + 1: 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE', +} +CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0 +CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 1 +CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR' +CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__enumvalues = { + 0: 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE', + 1: 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE', +} +CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0 +CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 1 +CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR' +CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR__enumvalues = { + 0: 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE', + 1: 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE', +} +CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0 +CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE = 1 +CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', +} +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE' +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', +} +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR' +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE', +} +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE' +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', +} +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 +CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR' +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE', +} +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE' +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', +} +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE' +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', +} +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 +CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR' +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE', +} +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE' +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', +} +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE' +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { + 0: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 1: 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', +} +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 +CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_EN' +CRTC_CRC_CNTL_CRTC_CRC_EN__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE', + 1: 'CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE', +} +CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0 +CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 1 +CRTC_CRC_CNTL_CRTC_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN' +CRTC_CRC_CNTL_CRTC_CRC_CONT_EN__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE', + 1: 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE', +} +CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0 +CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 1 +CRTC_CRC_CNTL_CRTC_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE' +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT', + 1: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT', + 2: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES', + 3: 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS', +} +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0 +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 1 +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 2 +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 3 +CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE' +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP', + 1: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM', + 2: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 3: 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD', +} +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0 +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 1 +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 3 +CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS' +CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 1: 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', +} +CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 +CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 +CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT' +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB', + 1: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B', + 2: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB', + 3: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B', + 4: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB', + 5: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B', + 6: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB', + 7: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B', +} +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 1 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 2 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 3 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 4 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 5 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 6 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 7 +CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT' +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT__enumvalues = { + 0: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB', + 1: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B', + 2: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB', + 3: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B', + 4: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB', + 5: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B', + 6: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB', + 7: 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B', +} +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 1 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 2 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 3 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 4 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 5 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 6 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 7 +CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT', + 2: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS', + 3: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 2 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED = 3 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel', + 2: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel', + 3: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 2 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 3 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE' +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE', +} +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE' +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE', +} +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR' +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE', +} +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 1 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE' +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE', +} +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT' +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME', + 1: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME', + 2: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME', + 3: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME', + 4: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME', + 5: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME', + 6: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME', + 7: 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME', +} +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 1 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 2 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 3 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 4 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 5 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 6 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 7 +CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE' +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE', +} +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR' +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE', +} +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0 +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE = 1 +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE' +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE', +} +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE' +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE', +} +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR' +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE', +} +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0 +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 1 +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE' +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__enumvalues = { + 0: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE', + 1: 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE', +} +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0 +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 1 +CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE' +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE__enumvalues = { + 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE', + 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE', +} +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE = 0 +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE = 1 +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR' +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR__enumvalues = { + 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE', + 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE', +} +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0 +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE = 1 +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE' +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE__enumvalues = { + 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE', + 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE', +} +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE = 0 +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE = 1 +CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE' +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE__enumvalues = { + 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE', + 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE', +} +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE = 0 +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE = 1 +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE' +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { + 0: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 1: 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON', +} +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 +CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN' +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN__enumvalues = { + 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE', + 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE', +} +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE = 0 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE = 1 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB' +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB__enumvalues = { + 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE', + 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE', +} +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE = 0 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE = 1 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE' +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { + 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 2: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 3: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', +} +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR' +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { + 0: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 1: 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', +} +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 +CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_V_SYNC_A_POL' +CRTC_V_SYNC_A_POL__enumvalues = { + 0: 'CRTC_V_SYNC_A_POL_HIGH', + 1: 'CRTC_V_SYNC_A_POL_LOW', +} +CRTC_V_SYNC_A_POL_HIGH = 0 +CRTC_V_SYNC_A_POL_LOW = 1 +CRTC_V_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_H_SYNC_A_POL' +CRTC_H_SYNC_A_POL__enumvalues = { + 0: 'CRTC_H_SYNC_A_POL_HIGH', + 1: 'CRTC_H_SYNC_A_POL_LOW', +} +CRTC_H_SYNC_A_POL_HIGH = 0 +CRTC_H_SYNC_A_POL_LOW = 1 +CRTC_H_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_HORZ_REPETITION_COUNT' +CRTC_HORZ_REPETITION_COUNT__enumvalues = { + 0: 'CRTC_HORZ_REPETITION_COUNT_0', + 1: 'CRTC_HORZ_REPETITION_COUNT_1', + 2: 'CRTC_HORZ_REPETITION_COUNT_2', + 3: 'CRTC_HORZ_REPETITION_COUNT_3', + 4: 'CRTC_HORZ_REPETITION_COUNT_4', + 5: 'CRTC_HORZ_REPETITION_COUNT_5', + 6: 'CRTC_HORZ_REPETITION_COUNT_6', + 7: 'CRTC_HORZ_REPETITION_COUNT_7', + 8: 'CRTC_HORZ_REPETITION_COUNT_8', + 9: 'CRTC_HORZ_REPETITION_COUNT_9', + 10: 'CRTC_HORZ_REPETITION_COUNT_10', + 11: 'CRTC_HORZ_REPETITION_COUNT_11', + 12: 'CRTC_HORZ_REPETITION_COUNT_12', + 13: 'CRTC_HORZ_REPETITION_COUNT_13', + 14: 'CRTC_HORZ_REPETITION_COUNT_14', + 15: 'CRTC_HORZ_REPETITION_COUNT_15', +} +CRTC_HORZ_REPETITION_COUNT_0 = 0 +CRTC_HORZ_REPETITION_COUNT_1 = 1 +CRTC_HORZ_REPETITION_COUNT_2 = 2 +CRTC_HORZ_REPETITION_COUNT_3 = 3 +CRTC_HORZ_REPETITION_COUNT_4 = 4 +CRTC_HORZ_REPETITION_COUNT_5 = 5 +CRTC_HORZ_REPETITION_COUNT_6 = 6 +CRTC_HORZ_REPETITION_COUNT_7 = 7 +CRTC_HORZ_REPETITION_COUNT_8 = 8 +CRTC_HORZ_REPETITION_COUNT_9 = 9 +CRTC_HORZ_REPETITION_COUNT_10 = 10 +CRTC_HORZ_REPETITION_COUNT_11 = 11 +CRTC_HORZ_REPETITION_COUNT_12 = 12 +CRTC_HORZ_REPETITION_COUNT_13 = 13 +CRTC_HORZ_REPETITION_COUNT_14 = 14 +CRTC_HORZ_REPETITION_COUNT_15 = 15 +CRTC_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_DRR_MODE_DBUF_UPDATE_MODE' +CRTC_DRR_MODE_DBUF_UPDATE_MODE__enumvalues = { + 0: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE', + 1: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL', + 2: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF', + 3: 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF', +} +CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE = 0 +CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL = 1 +CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF = 2 +CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF = 3 +CRTC_DRR_MODE_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' +FMT_CONTROL_PIXEL_ENCODING__enumvalues = { + 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', +} +FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 +FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 +FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 +FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 +FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' +FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', +} +FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 +FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 +FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 +FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 +FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' +FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', +} +FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 +FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 +FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { + 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', +} +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' +FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' +FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', +} +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' +FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT' +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT__enumvalues = { + 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN', + 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN', +} +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN = 0 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN = 1 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { + 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', +} +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' +FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { + 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', +} +FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 +FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 +FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 +FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 +FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 +FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_CONT_EN' +FMT_CRC_CNTL_CONT_EN__enumvalues = { + 0: 'FMT_CRC_CNTL_CONT_EN_ONE_SHOT', + 1: 'FMT_CRC_CNTL_CONT_EN_CONT', +} +FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0 +FMT_CRC_CNTL_CONT_EN_CONT = 1 +FMT_CRC_CNTL_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_INCLUDE_OVERSCAN' +FMT_CRC_CNTL_INCLUDE_OVERSCAN__enumvalues = { + 0: 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE', + 1: 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE', +} +FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0 +FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 1 +FMT_CRC_CNTL_INCLUDE_OVERSCAN = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_ONLY_BLANKB' +FMT_CRC_CNTL_ONLY_BLANKB__enumvalues = { + 0: 'FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD', + 1: 'FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK', +} +FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0 +FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 1 +FMT_CRC_CNTL_ONLY_BLANKB = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_PSR_MODE_ENABLE' +FMT_CRC_CNTL_PSR_MODE_ENABLE__enumvalues = { + 0: 'FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL', + 1: 'FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC', +} +FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0 +FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 1 +FMT_CRC_CNTL_PSR_MODE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_INTERLACE_MODE' +FMT_CRC_CNTL_INTERLACE_MODE__enumvalues = { + 0: 'FMT_CRC_CNTL_INTERLACE_MODE_TOP', + 1: 'FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM', + 2: 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM', + 3: 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH', +} +FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0 +FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 1 +FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 2 +FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 3 +FMT_CRC_CNTL_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE' +FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE__enumvalues = { + 0: 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL', + 1: 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN', +} +FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0 +FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 1 +FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT' +FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT__enumvalues = { + 0: 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN', + 1: 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD', +} +FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0 +FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 1 +FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT' +FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = { + 0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', + 1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', + 2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', + 3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', +} +FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0 +FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1 +FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2 +FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3 +FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_SPATIAL_DITHER_MODE' +FMT_SPATIAL_DITHER_MODE__enumvalues = { + 0: 'FMT_SPATIAL_DITHER_MODE_0', + 1: 'FMT_SPATIAL_DITHER_MODE_1', + 2: 'FMT_SPATIAL_DITHER_MODE_2', + 3: 'FMT_SPATIAL_DITHER_MODE_3', +} +FMT_SPATIAL_DITHER_MODE_0 = 0 +FMT_SPATIAL_DITHER_MODE_1 = 1 +FMT_SPATIAL_DITHER_MODE_2 = 2 +FMT_SPATIAL_DITHER_MODE_3 = 3 +FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_STEREOSYNC_OVR_POL' +FMT_STEREOSYNC_OVR_POL__enumvalues = { + 0: 'FMT_STEREOSYNC_OVR_POL_INVERTED', + 1: 'FMT_STEREOSYNC_OVR_POL_NOT_INVERTED', +} +FMT_STEREOSYNC_OVR_POL_INVERTED = 0 +FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 1 +FMT_STEREOSYNC_OVR_POL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DYNAMIC_EXP_MODE' +FMT_DYNAMIC_EXP_MODE__enumvalues = { + 0: 'FMT_DYNAMIC_EXP_MODE_10to12', + 1: 'FMT_DYNAMIC_EXP_MODE_8to12', +} +FMT_DYNAMIC_EXP_MODE_10to12 = 0 +FMT_DYNAMIC_EXP_MODE_8to12 = 1 +FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_ACK' +HPD_INT_CONTROL_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_ACK_0', + 1: 'HPD_INT_CONTROL_ACK_1', +} +HPD_INT_CONTROL_ACK_0 = 0 +HPD_INT_CONTROL_ACK_1 = 1 +HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_POLARITY' +HPD_INT_CONTROL_POLARITY__enumvalues = { + 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', + 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', +} +HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 +HPD_INT_CONTROL_GEN_INT_ON_CON = 1 +HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' +HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', + 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', +} +HPD_INT_CONTROL_RX_INT_ACK_0 = 0 +HPD_INT_CONTROL_RX_INT_ACK_1 = 1 +HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_PIXEL_DEPTH' +LB_DATA_FORMAT_PIXEL_DEPTH__enumvalues = { + 0: 'LB_DATA_FORMAT_PIXEL_DEPTH_30BPP', + 1: 'LB_DATA_FORMAT_PIXEL_DEPTH_24BPP', + 2: 'LB_DATA_FORMAT_PIXEL_DEPTH_18BPP', + 3: 'LB_DATA_FORMAT_PIXEL_DEPTH_36BPP', +} +LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0 +LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 1 +LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 2 +LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 3 +LB_DATA_FORMAT_PIXEL_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE' +LB_DATA_FORMAT_PIXEL_EXPAN_MODE__enumvalues = { + 0: 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION', + 1: 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION', +} +LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0 +LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 1 +LB_DATA_FORMAT_PIXEL_EXPAN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE' +LB_DATA_FORMAT_PIXEL_REDUCE_MODE__enumvalues = { + 0: 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION', + 1: 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING', +} +LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0 +LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 1 +LB_DATA_FORMAT_PIXEL_REDUCE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH' +LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH__enumvalues = { + 0: 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP', + 1: 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP', +} +LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0 +LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 1 +LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_INTERLEAVE_EN' +LB_DATA_FORMAT_INTERLEAVE_EN__enumvalues = { + 0: 'LB_DATA_FORMAT_INTERLEAVE_DISABLE', + 1: 'LB_DATA_FORMAT_INTERLEAVE_ENABLE', +} +LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0 +LB_DATA_FORMAT_INTERLEAVE_ENABLE = 1 +LB_DATA_FORMAT_INTERLEAVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_REQUEST_MODE' +LB_DATA_FORMAT_REQUEST_MODE__enumvalues = { + 0: 'LB_DATA_FORMAT_REQUEST_MODE_NORMAL', + 1: 'LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE', +} +LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0 +LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 1 +LB_DATA_FORMAT_REQUEST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DATA_FORMAT_ALPHA_EN' +LB_DATA_FORMAT_ALPHA_EN__enumvalues = { + 0: 'LB_DATA_FORMAT_ALPHA_DISABLE', + 1: 'LB_DATA_FORMAT_ALPHA_ENABLE', +} +LB_DATA_FORMAT_ALPHA_DISABLE = 0 +LB_DATA_FORMAT_ALPHA_ENABLE = 1 +LB_DATA_FORMAT_ALPHA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VLINE_START_END_VLINE_INV' +LB_VLINE_START_END_VLINE_INV__enumvalues = { + 0: 'LB_VLINE_START_END_VLINE_NORMAL', + 1: 'LB_VLINE_START_END_VLINE_INVERSE', +} +LB_VLINE_START_END_VLINE_NORMAL = 0 +LB_VLINE_START_END_VLINE_INVERSE = 1 +LB_VLINE_START_END_VLINE_INV = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VLINE2_START_END_VLINE2_INV' +LB_VLINE2_START_END_VLINE2_INV__enumvalues = { + 0: 'LB_VLINE2_START_END_VLINE2_NORMAL', + 1: 'LB_VLINE2_START_END_VLINE2_INVERSE', +} +LB_VLINE2_START_END_VLINE2_NORMAL = 0 +LB_VLINE2_START_END_VLINE2_INVERSE = 1 +LB_VLINE2_START_END_VLINE2_INV = ctypes.c_uint32 # enum + +# values for enumeration 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK' +LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK__enumvalues = { + 0: 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE', + 1: 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE', +} +LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0 +LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 1 +LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK' +LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK__enumvalues = { + 0: 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE', + 1: 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE', +} +LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0 +LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 1 +LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK' +LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK__enumvalues = { + 0: 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE', + 1: 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE', +} +LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0 +LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 1 +LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VLINE_STATUS_VLINE_ACK' +LB_VLINE_STATUS_VLINE_ACK__enumvalues = { + 0: 'LB_VLINE_STATUS_VLINE_NORMAL', + 1: 'LB_VLINE_STATUS_VLINE_CLEAR', +} +LB_VLINE_STATUS_VLINE_NORMAL = 0 +LB_VLINE_STATUS_VLINE_CLEAR = 1 +LB_VLINE_STATUS_VLINE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE' +LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE__enumvalues = { + 0: 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED', +} +LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0 +LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 1 +LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VLINE2_STATUS_VLINE2_ACK' +LB_VLINE2_STATUS_VLINE2_ACK__enumvalues = { + 0: 'LB_VLINE2_STATUS_VLINE2_NORMAL', + 1: 'LB_VLINE2_STATUS_VLINE2_CLEAR', +} +LB_VLINE2_STATUS_VLINE2_NORMAL = 0 +LB_VLINE2_STATUS_VLINE2_CLEAR = 1 +LB_VLINE2_STATUS_VLINE2_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE' +LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE__enumvalues = { + 0: 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED', +} +LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED = 0 +LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED = 1 +LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VBLANK_STATUS_VBLANK_ACK' +LB_VBLANK_STATUS_VBLANK_ACK__enumvalues = { + 0: 'LB_VBLANK_STATUS_VBLANK_NORMAL', + 1: 'LB_VBLANK_STATUS_VBLANK_CLEAR', +} +LB_VBLANK_STATUS_VBLANK_NORMAL = 0 +LB_VBLANK_STATUS_VBLANK_CLEAR = 1 +LB_VBLANK_STATUS_VBLANK_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE' +LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE__enumvalues = { + 0: 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED', +} +LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED = 0 +LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED = 1 +LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL' +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL__enumvalues = { + 0: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE', + 1: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK', + 2: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET', + 3: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET', +} +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0 +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK = 1 +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET = 2 +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET = 3 +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2' +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2__enumvalues = { + 0: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK', + 1: 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC', +} +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0 +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 1 +LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 = ctypes.c_uint32 # enum + +# values for enumeration 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION' +LB_SYNC_RESET_SEL_LB_SYNC_DURATION__enumvalues = { + 0: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS', + 1: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS', + 2: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS', + 3: 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS', +} +LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0 +LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 1 +LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 2 +LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 3 +LB_SYNC_RESET_SEL_LB_SYNC_DURATION = ctypes.c_uint32 # enum + +# values for enumeration 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN' +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN__enumvalues = { + 0: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE', + 1: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE', +} +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0 +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 1 +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN' +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN__enumvalues = { + 0: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE', + 1: 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE', +} +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0 +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 1 +LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK' +LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK__enumvalues = { + 0: 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL', + 1: 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET', +} +LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0 +LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 1 +LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK' +LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK__enumvalues = { + 0: 'LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL', + 1: 'LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET', +} +LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0 +LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 1 +LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE' +LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE__enumvalues = { + 2: 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP', + 3: 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP', +} +LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 2 +LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP = 3 +LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET' +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET__enumvalues = { + 0: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL', + 1: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE', +} +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0 +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE = 1 +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK' +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK__enumvalues = { + 0: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0', + 1: 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1', +} +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0 +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 1 +LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE' +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE__enumvalues = { + 0: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT', + 1: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG', + 2: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE', +} +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT = 0 +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG = 1 +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE = 2 +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE' +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE__enumvalues = { + 0: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE', + 1: 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN', +} +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE = 0 +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 1 +LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE' +LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE__enumvalues = { + 1: 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER', + 2: 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE', +} +ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER = 1 +ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE = 2 +LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL' +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL__enumvalues = { + 0: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0', + 1: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1', +} +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0 +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 1 +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE' +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__enumvalues = { + 0: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE', + 1: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE', +} +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0 +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE = 1 +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE = ctypes.c_uint32 # enum + +# values for enumeration 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO' +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__enumvalues = { + 0: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO', + 1: 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO', +} +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0 +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO = 1 +LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO = ctypes.c_uint32 # enum + +# values for enumeration 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN' +LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0', + 1: 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1', +} +LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0 +LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 1 +LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_KEEPOUT_MODE' +HDMI_KEEPOUT_MODE__enumvalues = { + 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', +} +HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 +HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 +HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DATA_SCRAMBLE_EN' +HDMI_DATA_SCRAMBLE_EN__enumvalues = { + 0: 'HDMI_DATA_SCRAMBLE_DISABLE', + 1: 'HDMI_DATA_SCRAMBLE_ENABLE', +} +HDMI_DATA_SCRAMBLE_DISABLE = 0 +HDMI_DATA_SCRAMBLE_ENABLE = 1 +HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' +HDMI_CLOCK_CHANNEL_RATE__enumvalues = { + 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', +} +HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 +HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 +HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' +HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { + 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', + 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', +} +HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 +HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 +HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKET_GEN_VERSION' +HDMI_PACKET_GEN_VERSION__enumvalues = { + 0: 'HDMI_PACKET_GEN_VERSION_OLD', + 1: 'HDMI_PACKET_GEN_VERSION_NEW', +} +HDMI_PACKET_GEN_VERSION_OLD = 0 +HDMI_PACKET_GEN_VERSION_NEW = 1 +HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_ACK' +HDMI_ERROR_ACK__enumvalues = { + 0: 'HDMI_ERROR_ACK_INT', + 1: 'HDMI_ERROR_NOT_ACK', +} +HDMI_ERROR_ACK_INT = 0 +HDMI_ERROR_NOT_ACK = 1 +HDMI_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_MASK' +HDMI_ERROR_MASK__enumvalues = { + 0: 'HDMI_ERROR_MASK_INT', + 1: 'HDMI_ERROR_NOT_MASK', +} +HDMI_ERROR_MASK_INT = 0 +HDMI_ERROR_NOT_MASK = 1 +HDMI_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEEP_COLOR_DEPTH' +HDMI_DEEP_COLOR_DEPTH__enumvalues = { + 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', + 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 3: 'HDMI_DEEP_COLOR_DEPTH_RESERVED', +} +HDMI_DEEP_COLOR_DEPTH_24BPP = 0 +HDMI_DEEP_COLOR_DEPTH_30BPP = 1 +HDMI_DEEP_COLOR_DEPTH_36BPP = 2 +HDMI_DEEP_COLOR_DEPTH_RESERVED = 3 +HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_DELAY_EN' +HDMI_AUDIO_DELAY_EN__enumvalues = { + 0: 'HDMI_AUDIO_DELAY_DISABLE', + 1: 'HDMI_AUDIO_DELAY_58CLK', + 2: 'HDMI_AUDIO_DELAY_56CLK', + 3: 'HDMI_AUDIO_DELAY_RESERVED', +} +HDMI_AUDIO_DELAY_DISABLE = 0 +HDMI_AUDIO_DELAY_58CLK = 1 +HDMI_AUDIO_DELAY_56CLK = 2 +HDMI_AUDIO_DELAY_RESERVED = 3 +HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_SEND_MAX_PACKETS' +HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { + 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', +} +HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 +HDMI_SEND_MAX_AUDIO_PACKETS = 1 +HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SEND' +HDMI_ACR_SEND__enumvalues = { + 0: 'HDMI_ACR_NOT_SEND', + 1: 'HDMI_ACR_PKT_SEND', +} +HDMI_ACR_NOT_SEND = 0 +HDMI_ACR_PKT_SEND = 1 +HDMI_ACR_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_CONT' +HDMI_ACR_CONT__enumvalues = { + 0: 'HDMI_ACR_CONT_DISABLE', + 1: 'HDMI_ACR_CONT_ENABLE', +} +HDMI_ACR_CONT_DISABLE = 0 +HDMI_ACR_CONT_ENABLE = 1 +HDMI_ACR_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SELECT' +HDMI_ACR_SELECT__enumvalues = { + 0: 'HDMI_ACR_SELECT_HW', + 1: 'HDMI_ACR_SELECT_32K', + 2: 'HDMI_ACR_SELECT_44K', + 3: 'HDMI_ACR_SELECT_48K', +} +HDMI_ACR_SELECT_HW = 0 +HDMI_ACR_SELECT_32K = 1 +HDMI_ACR_SELECT_44K = 2 +HDMI_ACR_SELECT_48K = 3 +HDMI_ACR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SOURCE' +HDMI_ACR_SOURCE__enumvalues = { + 0: 'HDMI_ACR_SOURCE_HW', + 1: 'HDMI_ACR_SOURCE_SW', +} +HDMI_ACR_SOURCE_HW = 0 +HDMI_ACR_SOURCE_SW = 1 +HDMI_ACR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_N_MULTIPLE' +HDMI_ACR_N_MULTIPLE__enumvalues = { + 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', + 1: 'HDMI_ACR_1_MULTIPLE', + 2: 'HDMI_ACR_2_MULTIPLE', + 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', + 4: 'HDMI_ACR_4_MULTIPLE', + 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', + 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', + 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', +} +HDMI_ACR_0_MULTIPLE_RESERVED = 0 +HDMI_ACR_1_MULTIPLE = 1 +HDMI_ACR_2_MULTIPLE = 2 +HDMI_ACR_3_MULTIPLE_RESERVED = 3 +HDMI_ACR_4_MULTIPLE = 4 +HDMI_ACR_5_MULTIPLE_RESERVED = 5 +HDMI_ACR_6_MULTIPLE_RESERVED = 6 +HDMI_ACR_7_MULTIPLE_RESERVED = 7 +HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' +HDMI_ACR_AUDIO_PRIORITY__enumvalues = { + 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', +} +HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 +HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 +HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NULL_SEND' +HDMI_NULL_SEND__enumvalues = { + 0: 'HDMI_NULL_NOT_SEND', + 1: 'HDMI_NULL_PKT_SEND', +} +HDMI_NULL_NOT_SEND = 0 +HDMI_NULL_PKT_SEND = 1 +HDMI_NULL_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_SEND' +HDMI_GC_SEND__enumvalues = { + 0: 'HDMI_GC_NOT_SEND', + 1: 'HDMI_GC_PKT_SEND', +} +HDMI_GC_NOT_SEND = 0 +HDMI_GC_PKT_SEND = 1 +HDMI_GC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_CONT' +HDMI_GC_CONT__enumvalues = { + 0: 'HDMI_GC_CONT_DISABLE', + 1: 'HDMI_GC_CONT_ENABLE', +} +HDMI_GC_CONT_DISABLE = 0 +HDMI_GC_CONT_ENABLE = 1 +HDMI_GC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_SEND' +HDMI_ISRC_SEND__enumvalues = { + 0: 'HDMI_ISRC_NOT_SEND', + 1: 'HDMI_ISRC_PKT_SEND', +} +HDMI_ISRC_NOT_SEND = 0 +HDMI_ISRC_PKT_SEND = 1 +HDMI_ISRC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_CONT' +HDMI_ISRC_CONT__enumvalues = { + 0: 'HDMI_ISRC_CONT_DISABLE', + 1: 'HDMI_ISRC_CONT_ENABLE', +} +HDMI_ISRC_CONT_DISABLE = 0 +HDMI_ISRC_CONT_ENABLE = 1 +HDMI_ISRC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AVI_INFO_SEND' +HDMI_AVI_INFO_SEND__enumvalues = { + 0: 'HDMI_AVI_INFO_NOT_SEND', + 1: 'HDMI_AVI_INFO_PKT_SEND', +} +HDMI_AVI_INFO_NOT_SEND = 0 +HDMI_AVI_INFO_PKT_SEND = 1 +HDMI_AVI_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AVI_INFO_CONT' +HDMI_AVI_INFO_CONT__enumvalues = { + 0: 'HDMI_AVI_INFO_CONT_DISABLE', + 1: 'HDMI_AVI_INFO_CONT_ENABLE', +} +HDMI_AVI_INFO_CONT_DISABLE = 0 +HDMI_AVI_INFO_CONT_ENABLE = 1 +HDMI_AVI_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_SEND' +HDMI_AUDIO_INFO_SEND__enumvalues = { + 0: 'HDMI_AUDIO_INFO_NOT_SEND', + 1: 'HDMI_AUDIO_INFO_PKT_SEND', +} +HDMI_AUDIO_INFO_NOT_SEND = 0 +HDMI_AUDIO_INFO_PKT_SEND = 1 +HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_CONT' +HDMI_AUDIO_INFO_CONT__enumvalues = { + 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', + 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', +} +HDMI_AUDIO_INFO_CONT_DISABLE = 0 +HDMI_AUDIO_INFO_CONT_ENABLE = 1 +HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_SEND' +HDMI_MPEG_INFO_SEND__enumvalues = { + 0: 'HDMI_MPEG_INFO_NOT_SEND', + 1: 'HDMI_MPEG_INFO_PKT_SEND', +} +HDMI_MPEG_INFO_NOT_SEND = 0 +HDMI_MPEG_INFO_PKT_SEND = 1 +HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_CONT' +HDMI_MPEG_INFO_CONT__enumvalues = { + 0: 'HDMI_MPEG_INFO_CONT_DISABLE', + 1: 'HDMI_MPEG_INFO_CONT_ENABLE', +} +HDMI_MPEG_INFO_CONT_DISABLE = 0 +HDMI_MPEG_INFO_CONT_ENABLE = 1 +HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC0_SEND' +HDMI_GENERIC0_SEND__enumvalues = { + 0: 'HDMI_GENERIC0_NOT_SEND', + 1: 'HDMI_GENERIC0_PKT_SEND', +} +HDMI_GENERIC0_NOT_SEND = 0 +HDMI_GENERIC0_PKT_SEND = 1 +HDMI_GENERIC0_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC0_CONT' +HDMI_GENERIC0_CONT__enumvalues = { + 0: 'HDMI_GENERIC0_CONT_DISABLE', + 1: 'HDMI_GENERIC0_CONT_ENABLE', +} +HDMI_GENERIC0_CONT_DISABLE = 0 +HDMI_GENERIC0_CONT_ENABLE = 1 +HDMI_GENERIC0_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC1_SEND' +HDMI_GENERIC1_SEND__enumvalues = { + 0: 'HDMI_GENERIC1_NOT_SEND', + 1: 'HDMI_GENERIC1_PKT_SEND', +} +HDMI_GENERIC1_NOT_SEND = 0 +HDMI_GENERIC1_PKT_SEND = 1 +HDMI_GENERIC1_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC1_CONT' +HDMI_GENERIC1_CONT__enumvalues = { + 0: 'HDMI_GENERIC1_CONT_DISABLE', + 1: 'HDMI_GENERIC1_CONT_ENABLE', +} +HDMI_GENERIC1_CONT_DISABLE = 0 +HDMI_GENERIC1_CONT_ENABLE = 1 +HDMI_GENERIC1_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE_CONT' +HDMI_GC_AVMUTE_CONT__enumvalues = { + 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', + 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', +} +HDMI_GC_AVMUTE_CONT_DISABLE = 0 +HDMI_GC_AVMUTE_CONT_ENABLE = 1 +HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' +HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { + 0: 'HDMI_PACKING_PHASE_SET_BY_HW', + 1: 'HDMI_PACKING_PHASE_SET_BY_SW', +} +HDMI_PACKING_PHASE_SET_BY_HW = 0 +HDMI_PACKING_PHASE_SET_BY_SW = 1 +HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC2_SEND' +HDMI_GENERIC2_SEND__enumvalues = { + 0: 'HDMI_GENERIC2_NOT_SEND', + 1: 'HDMI_GENERIC2_PKT_SEND', +} +HDMI_GENERIC2_NOT_SEND = 0 +HDMI_GENERIC2_PKT_SEND = 1 +HDMI_GENERIC2_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC2_CONT' +HDMI_GENERIC2_CONT__enumvalues = { + 0: 'HDMI_GENERIC2_CONT_DISABLE', + 1: 'HDMI_GENERIC2_CONT_ENABLE', +} +HDMI_GENERIC2_CONT_DISABLE = 0 +HDMI_GENERIC2_CONT_ENABLE = 1 +HDMI_GENERIC2_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC3_SEND' +HDMI_GENERIC3_SEND__enumvalues = { + 0: 'HDMI_GENERIC3_NOT_SEND', + 1: 'HDMI_GENERIC3_PKT_SEND', +} +HDMI_GENERIC3_NOT_SEND = 0 +HDMI_GENERIC3_PKT_SEND = 1 +HDMI_GENERIC3_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC3_CONT' +HDMI_GENERIC3_CONT__enumvalues = { + 0: 'HDMI_GENERIC3_CONT_DISABLE', + 1: 'HDMI_GENERIC3_CONT_ENABLE', +} +HDMI_GENERIC3_CONT_DISABLE = 0 +HDMI_GENERIC3_CONT_ENABLE = 1 +HDMI_GENERIC3_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_PIXEL_ENCODING' +TMDS_PIXEL_ENCODING__enumvalues = { + 0: 'TMDS_PIXEL_ENCODING_444_OR_420', + 1: 'TMDS_PIXEL_ENCODING_422', +} +TMDS_PIXEL_ENCODING_444_OR_420 = 0 +TMDS_PIXEL_ENCODING_422 = 1 +TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_COLOR_FORMAT' +TMDS_COLOR_FORMAT__enumvalues = { + 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', + 3: 'TMDS_COLOR_FORMAT_RESERVED', +} +TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 +TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 +TMDS_COLOR_FORMAT_DUAL30BPP = 2 +TMDS_COLOR_FORMAT_RESERVED = 3 +TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' +TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { + 0: 'TMDS_STEREOSYNC_CTL0', + 1: 'TMDS_STEREOSYNC_CTL1', + 2: 'TMDS_STEREOSYNC_CTL2', + 3: 'TMDS_STEREOSYNC_CTL3', +} +TMDS_STEREOSYNC_CTL0 = 0 +TMDS_STEREOSYNC_CTL1 = 1 +TMDS_STEREOSYNC_CTL2 = 2 +TMDS_STEREOSYNC_CTL3 = 3 +TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_SEL' +TMDS_CTL0_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', +} +TMDS_CTL0_DATA_SEL0_RESERVED = 0 +TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL0_DATA_SEL2_VSYNC = 2 +TMDS_CTL0_DATA_SEL3_RESERVED = 3 +TMDS_CTL0_DATA_SEL4_HSYNC = 4 +TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 +TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 +TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_INVERT' +TMDS_CTL0_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL0_DATA_NORMAL', + 1: 'TMDS_CTL0_DATA_INVERT_EN', +} +TMDS_CTL0_DATA_NORMAL = 0 +TMDS_CTL0_DATA_INVERT_EN = 1 +TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_MODULATION' +TMDS_CTL0_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', +} +TMDS_CTL0_DATA_MODULATION_DISABLE = 0 +TMDS_CTL0_DATA_MODULATION_BIT0 = 1 +TMDS_CTL0_DATA_MODULATION_BIT1 = 2 +TMDS_CTL0_DATA_MODULATION_BIT2 = 3 +TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' +TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', +} +TMDS_CTL0_PATTERN_OUT_DISABLE = 0 +TMDS_CTL0_PATTERN_OUT_ENABLE = 1 +TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_SEL' +TMDS_CTL1_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL1_DATA_SEL0_RESERVED = 0 +TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL1_DATA_SEL2_VSYNC = 2 +TMDS_CTL1_DATA_SEL3_RESERVED = 3 +TMDS_CTL1_DATA_SEL4_HSYNC = 4 +TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_INVERT' +TMDS_CTL1_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL1_DATA_NORMAL', + 1: 'TMDS_CTL1_DATA_INVERT_EN', +} +TMDS_CTL1_DATA_NORMAL = 0 +TMDS_CTL1_DATA_INVERT_EN = 1 +TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_MODULATION' +TMDS_CTL1_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', +} +TMDS_CTL1_DATA_MODULATION_DISABLE = 0 +TMDS_CTL1_DATA_MODULATION_BIT0 = 1 +TMDS_CTL1_DATA_MODULATION_BIT1 = 2 +TMDS_CTL1_DATA_MODULATION_BIT2 = 3 +TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' +TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', +} +TMDS_CTL1_PATTERN_OUT_DISABLE = 0 +TMDS_CTL1_PATTERN_OUT_ENABLE = 1 +TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_SEL' +TMDS_CTL2_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL2_DATA_SEL0_RESERVED = 0 +TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL2_DATA_SEL2_VSYNC = 2 +TMDS_CTL2_DATA_SEL3_RESERVED = 3 +TMDS_CTL2_DATA_SEL4_HSYNC = 4 +TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_INVERT' +TMDS_CTL2_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL2_DATA_NORMAL', + 1: 'TMDS_CTL2_DATA_INVERT_EN', +} +TMDS_CTL2_DATA_NORMAL = 0 +TMDS_CTL2_DATA_INVERT_EN = 1 +TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_MODULATION' +TMDS_CTL2_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', +} +TMDS_CTL2_DATA_MODULATION_DISABLE = 0 +TMDS_CTL2_DATA_MODULATION_BIT0 = 1 +TMDS_CTL2_DATA_MODULATION_BIT1 = 2 +TMDS_CTL2_DATA_MODULATION_BIT2 = 3 +TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' +TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', +} +TMDS_CTL2_PATTERN_OUT_DISABLE = 0 +TMDS_CTL2_PATTERN_OUT_ENABLE = 1 +TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_INVERT' +TMDS_CTL3_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL3_DATA_NORMAL', + 1: 'TMDS_CTL3_DATA_INVERT_EN', +} +TMDS_CTL3_DATA_NORMAL = 0 +TMDS_CTL3_DATA_INVERT_EN = 1 +TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_MODULATION' +TMDS_CTL3_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', +} +TMDS_CTL3_DATA_MODULATION_DISABLE = 0 +TMDS_CTL3_DATA_MODULATION_BIT0 = 1 +TMDS_CTL3_DATA_MODULATION_BIT1 = 2 +TMDS_CTL3_DATA_MODULATION_BIT2 = 3 +TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' +TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', +} +TMDS_CTL3_PATTERN_OUT_DISABLE = 0 +TMDS_CTL3_PATTERN_OUT_ENABLE = 1 +TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_SEL' +TMDS_CTL3_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL3_DATA_SEL0_RESERVED = 0 +TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL3_DATA_SEL2_VSYNC = 2 +TMDS_CTL3_DATA_SEL3_RESERVED = 3 +TMDS_CTL3_DATA_SEL4_HSYNC = 4 +TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' +DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { + 0: 'DIG_FE_SOURCE_FROM_FMT0', + 1: 'DIG_FE_SOURCE_FROM_FMT1', + 2: 'DIG_FE_SOURCE_FROM_FMT2', + 3: 'DIG_FE_SOURCE_FROM_FMT3', + 4: 'DIG_FE_SOURCE_FROM_FMT4', + 5: 'DIG_FE_SOURCE_FROM_FMT5', +} +DIG_FE_SOURCE_FROM_FMT0 = 0 +DIG_FE_SOURCE_FROM_FMT1 = 1 +DIG_FE_SOURCE_FROM_FMT2 = 2 +DIG_FE_SOURCE_FROM_FMT3 = 3 +DIG_FE_SOURCE_FROM_FMT4 = 4 +DIG_FE_SOURCE_FROM_FMT5 = 5 +DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' +DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { + 0: 'DIG_FE_STEREOSYNC_FROM_FMT0', + 1: 'DIG_FE_STEREOSYNC_FROM_FMT1', + 2: 'DIG_FE_STEREOSYNC_FROM_FMT2', + 3: 'DIG_FE_STEREOSYNC_FROM_FMT3', + 4: 'DIG_FE_STEREOSYNC_FROM_FMT4', + 5: 'DIG_FE_STEREOSYNC_FROM_FMT5', +} +DIG_FE_STEREOSYNC_FROM_FMT0 = 0 +DIG_FE_STEREOSYNC_FROM_FMT1 = 1 +DIG_FE_STEREOSYNC_FROM_FMT2 = 2 +DIG_FE_STEREOSYNC_FROM_FMT3 = 3 +DIG_FE_STEREOSYNC_FROM_FMT4 = 4 +DIG_FE_STEREOSYNC_FROM_FMT5 = 5 +DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' +DIG_FIFO_READ_CLOCK_SRC__enumvalues = { + 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', +} +DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 +DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 +DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' +DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_ON_LINK0', + 1: 'DIG_OUTPUT_CRC_ON_LINK1', +} +DIG_OUTPUT_CRC_ON_LINK0 = 0 +DIG_OUTPUT_CRC_ON_LINK1 = 1 +DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' +DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', + 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', + 2: 'DIG_OUTPUT_CRC_FOR_VBI', + 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', +} +DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 +DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 +DIG_OUTPUT_CRC_FOR_VBI = 2 +DIG_OUTPUT_CRC_FOR_AUDIO = 3 +DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_IN_NORMAL_OPERATION', + 1: 'DIG_IN_DEBUG_MODE', +} +DIG_IN_NORMAL_OPERATION = 0 +DIG_IN_DEBUG_MODE = 1 +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { + 0: 'DIG_10BIT_TEST_PATTERN', + 1: 'DIG_ALTERNATING_TEST_PATTERN', +} +DIG_10BIT_TEST_PATTERN = 0 +DIG_ALTERNATING_TEST_PATTERN = 1 +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_NORMAL', + 1: 'DIG_TEST_PATTERN_RANDOM', +} +DIG_TEST_PATTERN_NORMAL = 0 +DIG_TEST_PATTERN_RANDOM = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_ENABLED', + 1: 'DIG_RANDOM_PATTERN_RESETED', +} +DIG_RANDOM_PATTERN_ENABLED = 0 +DIG_RANDOM_PATTERN_RESETED = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' +DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', +} +DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 +DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 +DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' +DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', +} +DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 +DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 +DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL' +DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL__enumvalues = { + 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', + 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', +} +DIG_FIFO_USE_OVERWRITE_LEVEL = 0 +DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 +DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_ERROR_ACK' +DIG_FIFO_ERROR_ACK__enumvalues = { + 0: 'DIG_FIFO_ERROR_ACK_INT', + 1: 'DIG_FIFO_ERROR_NOT_ACK', +} +DIG_FIFO_ERROR_ACK_INT = 0 +DIG_FIFO_ERROR_NOT_ACK = 1 +DIG_FIFO_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE' +DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', +} +DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 +DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 +DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX' +DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', + 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', +} +DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 +DIG_FIFO_FORCE_RECOMP_MINMAX = 1 +DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' +AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { + 0: 'AFMT_INTERRUPT_DISABLE', + 1: 'AFMT_INTERRUPT_ENABLE', +} +AFMT_INTERRUPT_DISABLE = 0 +AFMT_INTERRUPT_ENABLE = 1 +AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE' +HDMI_GC_AVMUTE__enumvalues = { + 0: 'HDMI_GC_AVMUTE_SET', + 1: 'HDMI_GC_AVMUTE_UNSET', +} +HDMI_GC_AVMUTE_SET = 0 +HDMI_GC_AVMUTE_UNSET = 1 +HDMI_GC_AVMUTE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEFAULT_PAHSE' +HDMI_DEFAULT_PAHSE__enumvalues = { + 0: 'HDMI_DEFAULT_PHASE_IS_0', + 1: 'HDMI_DEFAULT_PHASE_IS_1', +} +HDMI_DEFAULT_PHASE_IS_0 = 0 +HDMI_DEFAULT_PHASE_IS_1 = 1 +HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { + 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', +} +AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 +AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum + +# values for enumeration 'AUDIO_LAYOUT_SELECT' +AUDIO_LAYOUT_SELECT__enumvalues = { + 0: 'AUDIO_LAYOUT_0', + 1: 'AUDIO_LAYOUT_1', +} +AUDIO_LAYOUT_0 = 0 +AUDIO_LAYOUT_1 = 1 +AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' +AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { + 0: 'AFMT_AUDIO_CRC_ONESHOT', + 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', +} +AFMT_AUDIO_CRC_ONESHOT = 0 +AFMT_AUDIO_CRC_AUTO_RESTART = 1 +AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' +AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { + 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', +} +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 +AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' +AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { + 0: 'AFMT_AUDIO_CRC_CH0_SIG', + 1: 'AFMT_AUDIO_CRC_CH1_SIG', + 2: 'AFMT_AUDIO_CRC_CH2_SIG', + 3: 'AFMT_AUDIO_CRC_CH3_SIG', + 4: 'AFMT_AUDIO_CRC_CH4_SIG', + 5: 'AFMT_AUDIO_CRC_CH5_SIG', + 6: 'AFMT_AUDIO_CRC_CH6_SIG', + 7: 'AFMT_AUDIO_CRC_CH7_SIG', + 8: 'AFMT_AUDIO_CRC_RESERVED_8', + 9: 'AFMT_AUDIO_CRC_RESERVED_9', + 10: 'AFMT_AUDIO_CRC_RESERVED_10', + 11: 'AFMT_AUDIO_CRC_RESERVED_11', + 12: 'AFMT_AUDIO_CRC_RESERVED_12', + 13: 'AFMT_AUDIO_CRC_RESERVED_13', + 14: 'AFMT_AUDIO_CRC_RESERVED_14', + 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', +} +AFMT_AUDIO_CRC_CH0_SIG = 0 +AFMT_AUDIO_CRC_CH1_SIG = 1 +AFMT_AUDIO_CRC_CH2_SIG = 2 +AFMT_AUDIO_CRC_CH3_SIG = 3 +AFMT_AUDIO_CRC_CH4_SIG = 4 +AFMT_AUDIO_CRC_CH5_SIG = 5 +AFMT_AUDIO_CRC_CH6_SIG = 6 +AFMT_AUDIO_CRC_CH7_SIG = 7 +AFMT_AUDIO_CRC_RESERVED_8 = 8 +AFMT_AUDIO_CRC_RESERVED_9 = 9 +AFMT_AUDIO_CRC_RESERVED_10 = 10 +AFMT_AUDIO_CRC_RESERVED_11 = 11 +AFMT_AUDIO_CRC_RESERVED_12 = 12 +AFMT_AUDIO_CRC_RESERVED_13 = 13 +AFMT_AUDIO_CRC_RESERVED_14 = 14 +AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 +AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' +AFMT_RAMP_CONTROL0_SIGN__enumvalues = { + 0: 'AFMT_RAMP_SIGNED', + 1: 'AFMT_RAMP_UNSIGNED', +} +AFMT_RAMP_SIGNED = 0 +AFMT_RAMP_UNSIGNED = 1 +AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { + 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', +} +AFMT_AUDIO_PACKET_SENT_DISABLED = 0 +AFMT_AUDIO_PACKET_SENT_ENABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { + 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', +} +AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 +AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { + 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', +} +AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 +AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' +AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { + 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', + 6: 'AFMT_AUDIO_SRC_RESERVED', +} +AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 +AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 +AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 +AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 +AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 +AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 +AFMT_AUDIO_SRC_RESERVED = 6 +AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_MODE' +DIG_BE_CNTL_MODE__enumvalues = { + 0: 'DIG_BE_DP_SST_MODE', + 1: 'DIG_BE_RESERVED1', + 2: 'DIG_BE_TMDS_DVI_MODE', + 3: 'DIG_BE_TMDS_HDMI_MODE', + 4: 'DIG_BE_SDVO_RESERVED', + 5: 'DIG_BE_DP_MST_MODE', + 6: 'DIG_BE_RESERVED2', + 7: 'DIG_BE_RESERVED3', +} +DIG_BE_DP_SST_MODE = 0 +DIG_BE_RESERVED1 = 1 +DIG_BE_TMDS_DVI_MODE = 2 +DIG_BE_TMDS_HDMI_MODE = 3 +DIG_BE_SDVO_RESERVED = 4 +DIG_BE_DP_MST_MODE = 5 +DIG_BE_RESERVED2 = 6 +DIG_BE_RESERVED3 = 7 +DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_HPD_SELECT' +DIG_BE_CNTL_HPD_SELECT__enumvalues = { + 0: 'DIG_BE_CNTL_HPD1', + 1: 'DIG_BE_CNTL_HPD2', + 2: 'DIG_BE_CNTL_HPD3', + 3: 'DIG_BE_CNTL_HPD4', + 4: 'DIG_BE_CNTL_HPD5', + 5: 'DIG_BE_CNTL_HPD6', +} +DIG_BE_CNTL_HPD1 = 0 +DIG_BE_CNTL_HPD2 = 1 +DIG_BE_CNTL_HPD3 = 2 +DIG_BE_CNTL_HPD4 = 3 +DIG_BE_CNTL_HPD5 = 4 +DIG_BE_CNTL_HPD6 = 5 +DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', +} +LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 +LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_SYNC_PHASE' +TMDS_SYNC_PHASE__enumvalues = { + 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', + 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', +} +TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 +TMDS_SYNC_PHASE_ON_FRAME_START = 1 +TMDS_SYNC_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' +TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { + 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', +} +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', +} +TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' +TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' +TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', +} +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', +} +TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 +TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', + 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 +TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 +TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', +} +TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 +TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' +TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', +} +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 +TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 +TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' +TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', + 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', +} +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 +TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 +TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_ENABLE' +DCP_GRPH_ENABLE__enumvalues = { + 0: 'DCP_GRPH_ENABLE_FALSE', + 1: 'DCP_GRPH_ENABLE_TRUE', +} +DCP_GRPH_ENABLE_FALSE = 0 +DCP_GRPH_ENABLE_TRUE = 1 +DCP_GRPH_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_KEYER_ALPHA_SEL' +DCP_GRPH_KEYER_ALPHA_SEL__enumvalues = { + 0: 'DCP_GRPH_KEYER_ALPHA_SEL_FALSE', + 1: 'DCP_GRPH_KEYER_ALPHA_SEL_TRUE', +} +DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0 +DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 1 +DCP_GRPH_KEYER_ALPHA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_DEPTH' +DCP_GRPH_DEPTH__enumvalues = { + 0: 'DCP_GRPH_DEPTH_8BPP', + 1: 'DCP_GRPH_DEPTH_16BPP', + 2: 'DCP_GRPH_DEPTH_32BPP', + 3: 'DCP_GRPH_DEPTH_64BPP', +} +DCP_GRPH_DEPTH_8BPP = 0 +DCP_GRPH_DEPTH_16BPP = 1 +DCP_GRPH_DEPTH_32BPP = 2 +DCP_GRPH_DEPTH_64BPP = 3 +DCP_GRPH_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_NUM_BANKS' +DCP_GRPH_NUM_BANKS__enumvalues = { + 0: 'DCP_GRPH_NUM_BANKS_1BANK', + 1: 'DCP_GRPH_NUM_BANKS_2BANK', + 2: 'DCP_GRPH_NUM_BANKS_4BANK', + 3: 'DCP_GRPH_NUM_BANKS_8BANK', + 4: 'DCP_GRPH_NUM_BANKS_16BANK', +} +DCP_GRPH_NUM_BANKS_1BANK = 0 +DCP_GRPH_NUM_BANKS_2BANK = 1 +DCP_GRPH_NUM_BANKS_4BANK = 2 +DCP_GRPH_NUM_BANKS_8BANK = 3 +DCP_GRPH_NUM_BANKS_16BANK = 4 +DCP_GRPH_NUM_BANKS = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_NUM_PIPES' +DCP_GRPH_NUM_PIPES__enumvalues = { + 0: 'DCP_GRPH_NUM_PIPES_1PIPE', + 1: 'DCP_GRPH_NUM_PIPES_2PIPE', + 2: 'DCP_GRPH_NUM_PIPES_4PIPE', + 3: 'DCP_GRPH_NUM_PIPES_8PIPE', +} +DCP_GRPH_NUM_PIPES_1PIPE = 0 +DCP_GRPH_NUM_PIPES_2PIPE = 1 +DCP_GRPH_NUM_PIPES_4PIPE = 2 +DCP_GRPH_NUM_PIPES_8PIPE = 3 +DCP_GRPH_NUM_PIPES = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_FORMAT' +DCP_GRPH_FORMAT__enumvalues = { + 0: 'DCP_GRPH_FORMAT_8BPP', + 1: 'DCP_GRPH_FORMAT_16BPP', + 2: 'DCP_GRPH_FORMAT_32BPP', + 3: 'DCP_GRPH_FORMAT_64BPP', +} +DCP_GRPH_FORMAT_8BPP = 0 +DCP_GRPH_FORMAT_16BPP = 1 +DCP_GRPH_FORMAT_32BPP = 2 +DCP_GRPH_FORMAT_64BPP = 3 +DCP_GRPH_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE' +DCP_GRPH_ADDRESS_TRANSLATION_ENABLE__enumvalues = { + 0: 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE', + 1: 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE', +} +DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0 +DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 1 +DCP_GRPH_ADDRESS_TRANSLATION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SW_MODE' +DCP_GRPH_SW_MODE__enumvalues = { + 0: 'DCP_GRPH_SW_MODE_0', + 2: 'DCP_GRPH_SW_MODE_2', + 3: 'DCP_GRPH_SW_MODE_3', + 22: 'DCP_GRPH_SW_MODE_22', + 23: 'DCP_GRPH_SW_MODE_23', + 26: 'DCP_GRPH_SW_MODE_26', + 27: 'DCP_GRPH_SW_MODE_27', + 30: 'DCP_GRPH_SW_MODE_30', + 31: 'DCP_GRPH_SW_MODE_31', +} +DCP_GRPH_SW_MODE_0 = 0 +DCP_GRPH_SW_MODE_2 = 2 +DCP_GRPH_SW_MODE_3 = 3 +DCP_GRPH_SW_MODE_22 = 22 +DCP_GRPH_SW_MODE_23 = 23 +DCP_GRPH_SW_MODE_26 = 26 +DCP_GRPH_SW_MODE_27 = 27 +DCP_GRPH_SW_MODE_30 = 30 +DCP_GRPH_SW_MODE_31 = 31 +DCP_GRPH_SW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_COLOR_EXPANSION_MODE' +DCP_GRPH_COLOR_EXPANSION_MODE__enumvalues = { + 0: 'DCP_GRPH_COLOR_EXPANSION_MODE_DEXP', + 1: 'DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP', +} +DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0 +DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 1 +DCP_GRPH_COLOR_EXPANSION_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_LUT_10BIT_BYPASS_EN' +DCP_GRPH_LUT_10BIT_BYPASS_EN__enumvalues = { + 0: 'DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE', + 1: 'DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE', +} +DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0 +DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 1 +DCP_GRPH_LUT_10BIT_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN' +DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__enumvalues = { + 0: 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE', + 1: 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE', +} +DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0 +DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 1 +DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_ENDIAN_SWAP' +DCP_GRPH_ENDIAN_SWAP__enumvalues = { + 0: 'DCP_GRPH_ENDIAN_SWAP_NONE', + 1: 'DCP_GRPH_ENDIAN_SWAP_8IN16', + 2: 'DCP_GRPH_ENDIAN_SWAP_8IN32', + 3: 'DCP_GRPH_ENDIAN_SWAP_8IN64', +} +DCP_GRPH_ENDIAN_SWAP_NONE = 0 +DCP_GRPH_ENDIAN_SWAP_8IN16 = 1 +DCP_GRPH_ENDIAN_SWAP_8IN32 = 2 +DCP_GRPH_ENDIAN_SWAP_8IN64 = 3 +DCP_GRPH_ENDIAN_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_RED_CROSSBAR' +DCP_GRPH_RED_CROSSBAR__enumvalues = { + 0: 'DCP_GRPH_RED_CROSSBAR_FROM_R', + 1: 'DCP_GRPH_RED_CROSSBAR_FROM_G', + 2: 'DCP_GRPH_RED_CROSSBAR_FROM_B', + 3: 'DCP_GRPH_RED_CROSSBAR_FROM_A', +} +DCP_GRPH_RED_CROSSBAR_FROM_R = 0 +DCP_GRPH_RED_CROSSBAR_FROM_G = 1 +DCP_GRPH_RED_CROSSBAR_FROM_B = 2 +DCP_GRPH_RED_CROSSBAR_FROM_A = 3 +DCP_GRPH_RED_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_GREEN_CROSSBAR' +DCP_GRPH_GREEN_CROSSBAR__enumvalues = { + 0: 'DCP_GRPH_GREEN_CROSSBAR_FROM_G', + 1: 'DCP_GRPH_GREEN_CROSSBAR_FROM_B', + 2: 'DCP_GRPH_GREEN_CROSSBAR_FROM_A', + 3: 'DCP_GRPH_GREEN_CROSSBAR_FROM_R', +} +DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0 +DCP_GRPH_GREEN_CROSSBAR_FROM_B = 1 +DCP_GRPH_GREEN_CROSSBAR_FROM_A = 2 +DCP_GRPH_GREEN_CROSSBAR_FROM_R = 3 +DCP_GRPH_GREEN_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_BLUE_CROSSBAR' +DCP_GRPH_BLUE_CROSSBAR__enumvalues = { + 0: 'DCP_GRPH_BLUE_CROSSBAR_FROM_B', + 1: 'DCP_GRPH_BLUE_CROSSBAR_FROM_A', + 2: 'DCP_GRPH_BLUE_CROSSBAR_FROM_R', + 3: 'DCP_GRPH_BLUE_CROSSBAR_FROM_G', +} +DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0 +DCP_GRPH_BLUE_CROSSBAR_FROM_A = 1 +DCP_GRPH_BLUE_CROSSBAR_FROM_R = 2 +DCP_GRPH_BLUE_CROSSBAR_FROM_G = 3 +DCP_GRPH_BLUE_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_ALPHA_CROSSBAR' +DCP_GRPH_ALPHA_CROSSBAR__enumvalues = { + 0: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_A', + 1: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_R', + 2: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_G', + 3: 'DCP_GRPH_ALPHA_CROSSBAR_FROM_B', +} +DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0 +DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 1 +DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 2 +DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 3 +DCP_GRPH_ALPHA_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PRIMARY_DFQ_ENABLE' +DCP_GRPH_PRIMARY_DFQ_ENABLE__enumvalues = { + 0: 'DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE', + 1: 'DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE', +} +DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0 +DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 1 +DCP_GRPH_PRIMARY_DFQ_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SECONDARY_DFQ_ENABLE' +DCP_GRPH_SECONDARY_DFQ_ENABLE__enumvalues = { + 0: 'DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE', + 1: 'DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE', +} +DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0 +DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 1 +DCP_GRPH_SECONDARY_DFQ_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_INPUT_GAMMA_MODE' +DCP_GRPH_INPUT_GAMMA_MODE__enumvalues = { + 0: 'DCP_GRPH_INPUT_GAMMA_MODE_LUT', + 1: 'DCP_GRPH_INPUT_GAMMA_MODE_BYPASS', +} +DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0 +DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 1 +DCP_GRPH_INPUT_GAMMA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_MODE_UPDATE_PENDING' +DCP_GRPH_MODE_UPDATE_PENDING__enumvalues = { + 0: 'DCP_GRPH_MODE_UPDATE_PENDING_FALSE', + 1: 'DCP_GRPH_MODE_UPDATE_PENDING_TRUE', +} +DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0 +DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 1 +DCP_GRPH_MODE_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_MODE_UPDATE_TAKEN' +DCP_GRPH_MODE_UPDATE_TAKEN__enumvalues = { + 0: 'DCP_GRPH_MODE_UPDATE_TAKEN_FALSE', + 1: 'DCP_GRPH_MODE_UPDATE_TAKEN_TRUE', +} +DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0 +DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 1 +DCP_GRPH_MODE_UPDATE_TAKEN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_UPDATE_PENDING' +DCP_GRPH_SURFACE_UPDATE_PENDING__enumvalues = { + 0: 'DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE', + 1: 'DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE', +} +DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0 +DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 1 +DCP_GRPH_SURFACE_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_UPDATE_TAKEN' +DCP_GRPH_SURFACE_UPDATE_TAKEN__enumvalues = { + 0: 'DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE', + 1: 'DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE', +} +DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0 +DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 1 +DCP_GRPH_SURFACE_UPDATE_TAKEN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE' +DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE__enumvalues = { + 0: 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE', + 1: 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE', +} +DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0 +DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 1 +DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_UPDATE_LOCK' +DCP_GRPH_UPDATE_LOCK__enumvalues = { + 0: 'DCP_GRPH_UPDATE_LOCK_FALSE', + 1: 'DCP_GRPH_UPDATE_LOCK_TRUE', +} +DCP_GRPH_UPDATE_LOCK_FALSE = 0 +DCP_GRPH_UPDATE_LOCK_TRUE = 1 +DCP_GRPH_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK' +DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK__enumvalues = { + 0: 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE', + 1: 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE', +} +DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0 +DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 1 +DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE' +DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE__enumvalues = { + 0: 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE', + 1: 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE', +} +DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0 +DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 1 +DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE' +DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__enumvalues = { + 0: 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE', + 1: 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE', +} +DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0 +DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 1 +DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN' +DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN__enumvalues = { + 0: 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE', + 1: 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE', +} +DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0 +DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 1 +DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_SUPER_AA_EN' +DCP_GRPH_XDMA_SUPER_AA_EN__enumvalues = { + 0: 'DCP_GRPH_XDMA_SUPER_AA_EN_FALSE', + 1: 'DCP_GRPH_XDMA_SUPER_AA_EN_TRUE', +} +DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0 +DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 1 +DCP_GRPH_XDMA_SUPER_AA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_DFQ_RESET' +DCP_GRPH_DFQ_RESET__enumvalues = { + 0: 'DCP_GRPH_DFQ_RESET_FALSE', + 1: 'DCP_GRPH_DFQ_RESET_TRUE', +} +DCP_GRPH_DFQ_RESET_FALSE = 0 +DCP_GRPH_DFQ_RESET_TRUE = 1 +DCP_GRPH_DFQ_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_DFQ_SIZE' +DCP_GRPH_DFQ_SIZE__enumvalues = { + 0: 'DCP_GRPH_DFQ_SIZE_DEEP1', + 1: 'DCP_GRPH_DFQ_SIZE_DEEP2', + 2: 'DCP_GRPH_DFQ_SIZE_DEEP3', + 3: 'DCP_GRPH_DFQ_SIZE_DEEP4', + 4: 'DCP_GRPH_DFQ_SIZE_DEEP5', + 5: 'DCP_GRPH_DFQ_SIZE_DEEP6', + 6: 'DCP_GRPH_DFQ_SIZE_DEEP7', + 7: 'DCP_GRPH_DFQ_SIZE_DEEP8', +} +DCP_GRPH_DFQ_SIZE_DEEP1 = 0 +DCP_GRPH_DFQ_SIZE_DEEP2 = 1 +DCP_GRPH_DFQ_SIZE_DEEP3 = 2 +DCP_GRPH_DFQ_SIZE_DEEP4 = 3 +DCP_GRPH_DFQ_SIZE_DEEP5 = 4 +DCP_GRPH_DFQ_SIZE_DEEP6 = 5 +DCP_GRPH_DFQ_SIZE_DEEP7 = 6 +DCP_GRPH_DFQ_SIZE_DEEP8 = 7 +DCP_GRPH_DFQ_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES' +DCP_GRPH_DFQ_MIN_FREE_ENTRIES__enumvalues = { + 0: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1', + 1: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2', + 2: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3', + 3: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4', + 4: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5', + 5: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6', + 6: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7', + 7: 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8', +} +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 1 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 2 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 3 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 4 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 5 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 6 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 7 +DCP_GRPH_DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_DFQ_RESET_ACK' +DCP_GRPH_DFQ_RESET_ACK__enumvalues = { + 0: 'DCP_GRPH_DFQ_RESET_ACK_FALSE', + 1: 'DCP_GRPH_DFQ_RESET_ACK_TRUE', +} +DCP_GRPH_DFQ_RESET_ACK_FALSE = 0 +DCP_GRPH_DFQ_RESET_ACK_TRUE = 1 +DCP_GRPH_DFQ_RESET_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PFLIP_INT_CLEAR' +DCP_GRPH_PFLIP_INT_CLEAR__enumvalues = { + 0: 'DCP_GRPH_PFLIP_INT_CLEAR_FALSE', + 1: 'DCP_GRPH_PFLIP_INT_CLEAR_TRUE', +} +DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0 +DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 1 +DCP_GRPH_PFLIP_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PFLIP_INT_MASK' +DCP_GRPH_PFLIP_INT_MASK__enumvalues = { + 0: 'DCP_GRPH_PFLIP_INT_MASK_FALSE', + 1: 'DCP_GRPH_PFLIP_INT_MASK_TRUE', +} +DCP_GRPH_PFLIP_INT_MASK_FALSE = 0 +DCP_GRPH_PFLIP_INT_MASK_TRUE = 1 +DCP_GRPH_PFLIP_INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PFLIP_INT_TYPE' +DCP_GRPH_PFLIP_INT_TYPE__enumvalues = { + 0: 'DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL', + 1: 'DCP_GRPH_PFLIP_INT_TYPE_PULSE', +} +DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0 +DCP_GRPH_PFLIP_INT_TYPE_PULSE = 1 +DCP_GRPH_PFLIP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PRESCALE_SELECT' +DCP_GRPH_PRESCALE_SELECT__enumvalues = { + 0: 'DCP_GRPH_PRESCALE_SELECT_FIXED', + 1: 'DCP_GRPH_PRESCALE_SELECT_FLOATING', +} +DCP_GRPH_PRESCALE_SELECT_FIXED = 0 +DCP_GRPH_PRESCALE_SELECT_FLOATING = 1 +DCP_GRPH_PRESCALE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PRESCALE_R_SIGN' +DCP_GRPH_PRESCALE_R_SIGN__enumvalues = { + 0: 'DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED', + 1: 'DCP_GRPH_PRESCALE_R_SIGN_SIGNED', +} +DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0 +DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 1 +DCP_GRPH_PRESCALE_R_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PRESCALE_G_SIGN' +DCP_GRPH_PRESCALE_G_SIGN__enumvalues = { + 0: 'DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED', + 1: 'DCP_GRPH_PRESCALE_G_SIGN_SIGNED', +} +DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0 +DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 1 +DCP_GRPH_PRESCALE_G_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PRESCALE_B_SIGN' +DCP_GRPH_PRESCALE_B_SIGN__enumvalues = { + 0: 'DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED', + 1: 'DCP_GRPH_PRESCALE_B_SIGN_SIGNED', +} +DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0 +DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 1 +DCP_GRPH_PRESCALE_B_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_PRESCALE_BYPASS' +DCP_GRPH_PRESCALE_BYPASS__enumvalues = { + 0: 'DCP_GRPH_PRESCALE_BYPASS_FALSE', + 1: 'DCP_GRPH_PRESCALE_BYPASS_TRUE', +} +DCP_GRPH_PRESCALE_BYPASS_FALSE = 0 +DCP_GRPH_PRESCALE_BYPASS_TRUE = 1 +DCP_GRPH_PRESCALE_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_INPUT_CSC_GRPH_MODE' +DCP_INPUT_CSC_GRPH_MODE__enumvalues = { + 0: 'DCP_INPUT_CSC_GRPH_MODE_BYPASS', + 1: 'DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF', + 2: 'DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF', + 3: 'DCP_INPUT_CSC_GRPH_MODE_RESERVED', +} +DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0 +DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 1 +DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 2 +DCP_INPUT_CSC_GRPH_MODE_RESERVED = 3 +DCP_INPUT_CSC_GRPH_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_OUTPUT_CSC_GRPH_MODE' +DCP_OUTPUT_CSC_GRPH_MODE__enumvalues = { + 0: 'DCP_OUTPUT_CSC_GRPH_MODE_BYPASS', + 1: 'DCP_OUTPUT_CSC_GRPH_MODE_RGB', + 2: 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601', + 3: 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709', + 4: 'DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF', + 5: 'DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF', + 6: 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0', + 7: 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1', +} +DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0 +DCP_OUTPUT_CSC_GRPH_MODE_RGB = 1 +DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 2 +DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 3 +DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 4 +DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 5 +DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 6 +DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 7 +DCP_OUTPUT_CSC_GRPH_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DENORM_MODE' +DCP_DENORM_MODE__enumvalues = { + 0: 'DCP_DENORM_MODE_UNITY', + 1: 'DCP_DENORM_MODE_6BIT', + 2: 'DCP_DENORM_MODE_8BIT', + 3: 'DCP_DENORM_MODE_10BIT', + 4: 'DCP_DENORM_MODE_11BIT', + 5: 'DCP_DENORM_MODE_12BIT', + 6: 'DCP_DENORM_MODE_RESERVED0', + 7: 'DCP_DENORM_MODE_RESERVED1', +} +DCP_DENORM_MODE_UNITY = 0 +DCP_DENORM_MODE_6BIT = 1 +DCP_DENORM_MODE_8BIT = 2 +DCP_DENORM_MODE_10BIT = 3 +DCP_DENORM_MODE_11BIT = 4 +DCP_DENORM_MODE_12BIT = 5 +DCP_DENORM_MODE_RESERVED0 = 6 +DCP_DENORM_MODE_RESERVED1 = 7 +DCP_DENORM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DENORM_14BIT_OUT' +DCP_DENORM_14BIT_OUT__enumvalues = { + 0: 'DCP_DENORM_14BIT_OUT_FALSE', + 1: 'DCP_DENORM_14BIT_OUT_TRUE', +} +DCP_DENORM_14BIT_OUT_FALSE = 0 +DCP_DENORM_14BIT_OUT_TRUE = 1 +DCP_DENORM_14BIT_OUT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_OUT_ROUND_TRUNC_MODE' +DCP_OUT_ROUND_TRUNC_MODE__enumvalues = { + 0: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12', + 1: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11', + 2: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10', + 3: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9', + 4: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8', + 5: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED', + 6: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14', + 7: 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13', + 8: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_12', + 9: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_11', + 10: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_10', + 11: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_9', + 12: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_8', + 13: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED', + 14: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_14', + 15: 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_13', +} +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 1 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 2 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 3 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 4 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 5 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 6 +DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 7 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 8 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 9 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 10 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 11 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 12 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 13 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 14 +DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 15 +DCP_OUT_ROUND_TRUNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_KEY_MODE' +DCP_KEY_MODE__enumvalues = { + 0: 'DCP_KEY_MODE_ALPHA0', + 1: 'DCP_KEY_MODE_ALPHA1', + 2: 'DCP_KEY_MODE_IN_RANGE_ALPHA1', + 3: 'DCP_KEY_MODE_IN_RANGE_ALPHA0', +} +DCP_KEY_MODE_ALPHA0 = 0 +DCP_KEY_MODE_ALPHA1 = 1 +DCP_KEY_MODE_IN_RANGE_ALPHA1 = 2 +DCP_KEY_MODE_IN_RANGE_ALPHA0 = 3 +DCP_KEY_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_DEGAMMA_MODE' +DCP_GRPH_DEGAMMA_MODE__enumvalues = { + 0: 'DCP_GRPH_DEGAMMA_MODE_BYPASS', + 1: 'DCP_GRPH_DEGAMMA_MODE_ROMA', + 2: 'DCP_GRPH_DEGAMMA_MODE_ROMB', + 3: 'DCP_GRPH_DEGAMMA_MODE_RESERVED', +} +DCP_GRPH_DEGAMMA_MODE_BYPASS = 0 +DCP_GRPH_DEGAMMA_MODE_ROMA = 1 +DCP_GRPH_DEGAMMA_MODE_ROMB = 2 +DCP_GRPH_DEGAMMA_MODE_RESERVED = 3 +DCP_GRPH_DEGAMMA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_DEGAMMA_MODE' +DCP_CURSOR_DEGAMMA_MODE__enumvalues = { + 0: 'DCP_CURSOR_DEGAMMA_MODE_BYPASS', + 1: 'DCP_CURSOR_DEGAMMA_MODE_ROMA', + 2: 'DCP_CURSOR_DEGAMMA_MODE_ROMB', + 3: 'DCP_CURSOR_DEGAMMA_MODE_RESERVED', +} +DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0 +DCP_CURSOR_DEGAMMA_MODE_ROMA = 1 +DCP_CURSOR_DEGAMMA_MODE_ROMB = 2 +DCP_CURSOR_DEGAMMA_MODE_RESERVED = 3 +DCP_CURSOR_DEGAMMA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_GAMUT_REMAP_MODE' +DCP_GRPH_GAMUT_REMAP_MODE__enumvalues = { + 0: 'DCP_GRPH_GAMUT_REMAP_MODE_BYPASS', + 1: 'DCP_GRPH_GAMUT_REMAP_MODE_ROMA', + 2: 'DCP_GRPH_GAMUT_REMAP_MODE_ROMB', + 3: 'DCP_GRPH_GAMUT_REMAP_MODE_RESERVED', +} +DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0 +DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 1 +DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 2 +DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 3 +DCP_GRPH_GAMUT_REMAP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_SPATIAL_DITHER_EN' +DCP_SPATIAL_DITHER_EN__enumvalues = { + 0: 'DCP_SPATIAL_DITHER_EN_FALSE', + 1: 'DCP_SPATIAL_DITHER_EN_TRUE', +} +DCP_SPATIAL_DITHER_EN_FALSE = 0 +DCP_SPATIAL_DITHER_EN_TRUE = 1 +DCP_SPATIAL_DITHER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_SPATIAL_DITHER_MODE' +DCP_SPATIAL_DITHER_MODE__enumvalues = { + 0: 'DCP_SPATIAL_DITHER_MODE_BYPASS', + 1: 'DCP_SPATIAL_DITHER_MODE_ROMA', + 2: 'DCP_SPATIAL_DITHER_MODE_ROMB', + 3: 'DCP_SPATIAL_DITHER_MODE_RESERVED', +} +DCP_SPATIAL_DITHER_MODE_BYPASS = 0 +DCP_SPATIAL_DITHER_MODE_ROMA = 1 +DCP_SPATIAL_DITHER_MODE_ROMB = 2 +DCP_SPATIAL_DITHER_MODE_RESERVED = 3 +DCP_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_SPATIAL_DITHER_DEPTH' +DCP_SPATIAL_DITHER_DEPTH__enumvalues = { + 0: 'DCP_SPATIAL_DITHER_DEPTH_30BPP', + 1: 'DCP_SPATIAL_DITHER_DEPTH_24BPP', + 2: 'DCP_SPATIAL_DITHER_DEPTH_36BPP', + 3: 'DCP_SPATIAL_DITHER_DEPTH_UNDEFINED', +} +DCP_SPATIAL_DITHER_DEPTH_30BPP = 0 +DCP_SPATIAL_DITHER_DEPTH_24BPP = 1 +DCP_SPATIAL_DITHER_DEPTH_36BPP = 2 +DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 3 +DCP_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_FRAME_RANDOM_ENABLE' +DCP_FRAME_RANDOM_ENABLE__enumvalues = { + 0: 'DCP_FRAME_RANDOM_ENABLE_FALSE', + 1: 'DCP_FRAME_RANDOM_ENABLE_TRUE', +} +DCP_FRAME_RANDOM_ENABLE_FALSE = 0 +DCP_FRAME_RANDOM_ENABLE_TRUE = 1 +DCP_FRAME_RANDOM_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_RGB_RANDOM_ENABLE' +DCP_RGB_RANDOM_ENABLE__enumvalues = { + 0: 'DCP_RGB_RANDOM_ENABLE_FALSE', + 1: 'DCP_RGB_RANDOM_ENABLE_TRUE', +} +DCP_RGB_RANDOM_ENABLE_FALSE = 0 +DCP_RGB_RANDOM_ENABLE_TRUE = 1 +DCP_RGB_RANDOM_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_HIGHPASS_RANDOM_ENABLE' +DCP_HIGHPASS_RANDOM_ENABLE__enumvalues = { + 0: 'DCP_HIGHPASS_RANDOM_ENABLE_FALSE', + 1: 'DCP_HIGHPASS_RANDOM_ENABLE_TRUE', +} +DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0 +DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 1 +DCP_HIGHPASS_RANDOM_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_EN' +DCP_CURSOR_EN__enumvalues = { + 0: 'DCP_CURSOR_EN_FALSE', + 1: 'DCP_CURSOR_EN_TRUE', +} +DCP_CURSOR_EN_FALSE = 0 +DCP_CURSOR_EN_TRUE = 1 +DCP_CURSOR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CUR_INV_TRANS_CLAMP' +DCP_CUR_INV_TRANS_CLAMP__enumvalues = { + 0: 'DCP_CUR_INV_TRANS_CLAMP_FALSE', + 1: 'DCP_CUR_INV_TRANS_CLAMP_TRUE', +} +DCP_CUR_INV_TRANS_CLAMP_FALSE = 0 +DCP_CUR_INV_TRANS_CLAMP_TRUE = 1 +DCP_CUR_INV_TRANS_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_MODE' +DCP_CURSOR_MODE__enumvalues = { + 0: 'DCP_CURSOR_MODE_MONO_2BPP', + 1: 'DCP_CURSOR_MODE_24BPP_1BIT', + 2: 'DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI', + 3: 'DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI', +} +DCP_CURSOR_MODE_MONO_2BPP = 0 +DCP_CURSOR_MODE_24BPP_1BIT = 1 +DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 2 +DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 3 +DCP_CURSOR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM' +DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM__enumvalues = { + 0: 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE', + 1: 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO', +} +DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE = 0 +DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO = 1 +DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_2X_MAGNIFY' +DCP_CURSOR_2X_MAGNIFY__enumvalues = { + 0: 'DCP_CURSOR_2X_MAGNIFY_FALSE', + 1: 'DCP_CURSOR_2X_MAGNIFY_TRUE', +} +DCP_CURSOR_2X_MAGNIFY_FALSE = 0 +DCP_CURSOR_2X_MAGNIFY_TRUE = 1 +DCP_CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_FORCE_MC_ON' +DCP_CURSOR_FORCE_MC_ON__enumvalues = { + 0: 'DCP_CURSOR_FORCE_MC_ON_FALSE', + 1: 'DCP_CURSOR_FORCE_MC_ON_TRUE', +} +DCP_CURSOR_FORCE_MC_ON_FALSE = 0 +DCP_CURSOR_FORCE_MC_ON_TRUE = 1 +DCP_CURSOR_FORCE_MC_ON = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_URGENT_CONTROL' +DCP_CURSOR_URGENT_CONTROL__enumvalues = { + 0: 'DCP_CURSOR_URGENT_CONTROL_MODE_0', + 1: 'DCP_CURSOR_URGENT_CONTROL_MODE_1', + 2: 'DCP_CURSOR_URGENT_CONTROL_MODE_2', + 3: 'DCP_CURSOR_URGENT_CONTROL_MODE_3', + 4: 'DCP_CURSOR_URGENT_CONTROL_MODE_4', +} +DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0 +DCP_CURSOR_URGENT_CONTROL_MODE_1 = 1 +DCP_CURSOR_URGENT_CONTROL_MODE_2 = 2 +DCP_CURSOR_URGENT_CONTROL_MODE_3 = 3 +DCP_CURSOR_URGENT_CONTROL_MODE_4 = 4 +DCP_CURSOR_URGENT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_UPDATE_PENDING' +DCP_CURSOR_UPDATE_PENDING__enumvalues = { + 0: 'DCP_CURSOR_UPDATE_PENDING_FALSE', + 1: 'DCP_CURSOR_UPDATE_PENDING_TRUE', +} +DCP_CURSOR_UPDATE_PENDING_FALSE = 0 +DCP_CURSOR_UPDATE_PENDING_TRUE = 1 +DCP_CURSOR_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_UPDATE_TAKEN' +DCP_CURSOR_UPDATE_TAKEN__enumvalues = { + 0: 'DCP_CURSOR_UPDATE_TAKEN_FALSE', + 1: 'DCP_CURSOR_UPDATE_TAKEN_TRUE', +} +DCP_CURSOR_UPDATE_TAKEN_FALSE = 0 +DCP_CURSOR_UPDATE_TAKEN_TRUE = 1 +DCP_CURSOR_UPDATE_TAKEN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_UPDATE_LOCK' +DCP_CURSOR_UPDATE_LOCK__enumvalues = { + 0: 'DCP_CURSOR_UPDATE_LOCK_FALSE', + 1: 'DCP_CURSOR_UPDATE_LOCK_TRUE', +} +DCP_CURSOR_UPDATE_LOCK_FALSE = 0 +DCP_CURSOR_UPDATE_LOCK_TRUE = 1 +DCP_CURSOR_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE' +DCP_CURSOR_DISABLE_MULTIPLE_UPDATE__enumvalues = { + 0: 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE', + 1: 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE', +} +DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0 +DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 1 +DCP_CURSOR_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_UPDATE_STEREO_MODE' +DCP_CURSOR_UPDATE_STEREO_MODE__enumvalues = { + 0: 'DCP_CURSOR_UPDATE_STEREO_MODE_BOTH', + 1: 'DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY', + 2: 'DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED', + 3: 'DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY', +} +DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0 +DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 1 +DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 2 +DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 3 +DCP_CURSOR_UPDATE_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CUR2_INV_TRANS_CLAMP' +DCP_CUR2_INV_TRANS_CLAMP__enumvalues = { + 0: 'DCP_CUR2_INV_TRANS_CLAMP_FALSE', + 1: 'DCP_CUR2_INV_TRANS_CLAMP_TRUE', +} +DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0 +DCP_CUR2_INV_TRANS_CLAMP_TRUE = 1 +DCP_CUR2_INV_TRANS_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CUR_REQUEST_FILTER_DIS' +DCP_CUR_REQUEST_FILTER_DIS__enumvalues = { + 0: 'DCP_CUR_REQUEST_FILTER_DIS_FALSE', + 1: 'DCP_CUR_REQUEST_FILTER_DIS_TRUE', +} +DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0 +DCP_CUR_REQUEST_FILTER_DIS_TRUE = 1 +DCP_CUR_REQUEST_FILTER_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_STEREO_EN' +DCP_CURSOR_STEREO_EN__enumvalues = { + 0: 'DCP_CURSOR_STEREO_EN_FALSE', + 1: 'DCP_CURSOR_STEREO_EN_TRUE', +} +DCP_CURSOR_STEREO_EN_FALSE = 0 +DCP_CURSOR_STEREO_EN_TRUE = 1 +DCP_CURSOR_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_STEREO_OFFSET_YNX' +DCP_CURSOR_STEREO_OFFSET_YNX__enumvalues = { + 0: 'DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION', + 1: 'DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION', +} +DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0 +DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 1 +DCP_CURSOR_STEREO_OFFSET_YNX = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_RW_MODE' +DCP_DC_LUT_RW_MODE__enumvalues = { + 0: 'DCP_DC_LUT_RW_MODE_256_ENTRY', + 1: 'DCP_DC_LUT_RW_MODE_PWL', +} +DCP_DC_LUT_RW_MODE_256_ENTRY = 0 +DCP_DC_LUT_RW_MODE_PWL = 1 +DCP_DC_LUT_RW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_VGA_ACCESS_ENABLE' +DCP_DC_LUT_VGA_ACCESS_ENABLE__enumvalues = { + 0: 'DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE', + 1: 'DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE', +} +DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0 +DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 1 +DCP_DC_LUT_VGA_ACCESS_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_AUTOFILL' +DCP_DC_LUT_AUTOFILL__enumvalues = { + 0: 'DCP_DC_LUT_AUTOFILL_FALSE', + 1: 'DCP_DC_LUT_AUTOFILL_TRUE', +} +DCP_DC_LUT_AUTOFILL_FALSE = 0 +DCP_DC_LUT_AUTOFILL_TRUE = 1 +DCP_DC_LUT_AUTOFILL = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_AUTOFILL_DONE' +DCP_DC_LUT_AUTOFILL_DONE__enumvalues = { + 0: 'DCP_DC_LUT_AUTOFILL_DONE_FALSE', + 1: 'DCP_DC_LUT_AUTOFILL_DONE_TRUE', +} +DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0 +DCP_DC_LUT_AUTOFILL_DONE_TRUE = 1 +DCP_DC_LUT_AUTOFILL_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_INC_B' +DCP_DC_LUT_INC_B__enumvalues = { + 0: 'DCP_DC_LUT_INC_B_NA', + 1: 'DCP_DC_LUT_INC_B_2', + 2: 'DCP_DC_LUT_INC_B_4', + 3: 'DCP_DC_LUT_INC_B_8', + 4: 'DCP_DC_LUT_INC_B_16', + 5: 'DCP_DC_LUT_INC_B_32', + 6: 'DCP_DC_LUT_INC_B_64', + 7: 'DCP_DC_LUT_INC_B_128', + 8: 'DCP_DC_LUT_INC_B_256', + 9: 'DCP_DC_LUT_INC_B_512', +} +DCP_DC_LUT_INC_B_NA = 0 +DCP_DC_LUT_INC_B_2 = 1 +DCP_DC_LUT_INC_B_4 = 2 +DCP_DC_LUT_INC_B_8 = 3 +DCP_DC_LUT_INC_B_16 = 4 +DCP_DC_LUT_INC_B_32 = 5 +DCP_DC_LUT_INC_B_64 = 6 +DCP_DC_LUT_INC_B_128 = 7 +DCP_DC_LUT_INC_B_256 = 8 +DCP_DC_LUT_INC_B_512 = 9 +DCP_DC_LUT_INC_B = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_B_SIGNED_EN' +DCP_DC_LUT_DATA_B_SIGNED_EN__enumvalues = { + 0: 'DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE', + 1: 'DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE', +} +DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0 +DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 1 +DCP_DC_LUT_DATA_B_SIGNED_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN' +DCP_DC_LUT_DATA_B_FLOAT_POINT_EN__enumvalues = { + 0: 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE', + 1: 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE', +} +DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0 +DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 1 +DCP_DC_LUT_DATA_B_FLOAT_POINT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_B_FORMAT' +DCP_DC_LUT_DATA_B_FORMAT__enumvalues = { + 0: 'DCP_DC_LUT_DATA_B_FORMAT_U0P10', + 1: 'DCP_DC_LUT_DATA_B_FORMAT_S1P10', + 2: 'DCP_DC_LUT_DATA_B_FORMAT_U1P11', + 3: 'DCP_DC_LUT_DATA_B_FORMAT_U0P12', +} +DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0 +DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 1 +DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 2 +DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 3 +DCP_DC_LUT_DATA_B_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_INC_G' +DCP_DC_LUT_INC_G__enumvalues = { + 0: 'DCP_DC_LUT_INC_G_NA', + 1: 'DCP_DC_LUT_INC_G_2', + 2: 'DCP_DC_LUT_INC_G_4', + 3: 'DCP_DC_LUT_INC_G_8', + 4: 'DCP_DC_LUT_INC_G_16', + 5: 'DCP_DC_LUT_INC_G_32', + 6: 'DCP_DC_LUT_INC_G_64', + 7: 'DCP_DC_LUT_INC_G_128', + 8: 'DCP_DC_LUT_INC_G_256', + 9: 'DCP_DC_LUT_INC_G_512', +} +DCP_DC_LUT_INC_G_NA = 0 +DCP_DC_LUT_INC_G_2 = 1 +DCP_DC_LUT_INC_G_4 = 2 +DCP_DC_LUT_INC_G_8 = 3 +DCP_DC_LUT_INC_G_16 = 4 +DCP_DC_LUT_INC_G_32 = 5 +DCP_DC_LUT_INC_G_64 = 6 +DCP_DC_LUT_INC_G_128 = 7 +DCP_DC_LUT_INC_G_256 = 8 +DCP_DC_LUT_INC_G_512 = 9 +DCP_DC_LUT_INC_G = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_G_SIGNED_EN' +DCP_DC_LUT_DATA_G_SIGNED_EN__enumvalues = { + 0: 'DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE', + 1: 'DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE', +} +DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0 +DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 1 +DCP_DC_LUT_DATA_G_SIGNED_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN' +DCP_DC_LUT_DATA_G_FLOAT_POINT_EN__enumvalues = { + 0: 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE', + 1: 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE', +} +DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0 +DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 1 +DCP_DC_LUT_DATA_G_FLOAT_POINT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_G_FORMAT' +DCP_DC_LUT_DATA_G_FORMAT__enumvalues = { + 0: 'DCP_DC_LUT_DATA_G_FORMAT_U0P10', + 1: 'DCP_DC_LUT_DATA_G_FORMAT_S1P10', + 2: 'DCP_DC_LUT_DATA_G_FORMAT_U1P11', + 3: 'DCP_DC_LUT_DATA_G_FORMAT_U0P12', +} +DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0 +DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 1 +DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 2 +DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 3 +DCP_DC_LUT_DATA_G_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_INC_R' +DCP_DC_LUT_INC_R__enumvalues = { + 0: 'DCP_DC_LUT_INC_R_NA', + 1: 'DCP_DC_LUT_INC_R_2', + 2: 'DCP_DC_LUT_INC_R_4', + 3: 'DCP_DC_LUT_INC_R_8', + 4: 'DCP_DC_LUT_INC_R_16', + 5: 'DCP_DC_LUT_INC_R_32', + 6: 'DCP_DC_LUT_INC_R_64', + 7: 'DCP_DC_LUT_INC_R_128', + 8: 'DCP_DC_LUT_INC_R_256', + 9: 'DCP_DC_LUT_INC_R_512', +} +DCP_DC_LUT_INC_R_NA = 0 +DCP_DC_LUT_INC_R_2 = 1 +DCP_DC_LUT_INC_R_4 = 2 +DCP_DC_LUT_INC_R_8 = 3 +DCP_DC_LUT_INC_R_16 = 4 +DCP_DC_LUT_INC_R_32 = 5 +DCP_DC_LUT_INC_R_64 = 6 +DCP_DC_LUT_INC_R_128 = 7 +DCP_DC_LUT_INC_R_256 = 8 +DCP_DC_LUT_INC_R_512 = 9 +DCP_DC_LUT_INC_R = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_R_SIGNED_EN' +DCP_DC_LUT_DATA_R_SIGNED_EN__enumvalues = { + 0: 'DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE', + 1: 'DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE', +} +DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0 +DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 1 +DCP_DC_LUT_DATA_R_SIGNED_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN' +DCP_DC_LUT_DATA_R_FLOAT_POINT_EN__enumvalues = { + 0: 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE', + 1: 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE', +} +DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0 +DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 1 +DCP_DC_LUT_DATA_R_FLOAT_POINT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_DC_LUT_DATA_R_FORMAT' +DCP_DC_LUT_DATA_R_FORMAT__enumvalues = { + 0: 'DCP_DC_LUT_DATA_R_FORMAT_U0P10', + 1: 'DCP_DC_LUT_DATA_R_FORMAT_S1P10', + 2: 'DCP_DC_LUT_DATA_R_FORMAT_U1P11', + 3: 'DCP_DC_LUT_DATA_R_FORMAT_U0P12', +} +DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0 +DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 1 +DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 2 +DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 3 +DCP_DC_LUT_DATA_R_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CRC_ENABLE' +DCP_CRC_ENABLE__enumvalues = { + 0: 'DCP_CRC_ENABLE_FALSE', + 1: 'DCP_CRC_ENABLE_TRUE', +} +DCP_CRC_ENABLE_FALSE = 0 +DCP_CRC_ENABLE_TRUE = 1 +DCP_CRC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CRC_SOURCE_SEL' +DCP_CRC_SOURCE_SEL__enumvalues = { + 0: 'DCP_CRC_SOURCE_SEL_OUTPUT_PIX', + 1: 'DCP_CRC_SOURCE_SEL_INPUT_L32', + 2: 'DCP_CRC_SOURCE_SEL_INPUT_H32', + 4: 'DCP_CRC_SOURCE_SEL_OUTPUT_CNTL', +} +DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0 +DCP_CRC_SOURCE_SEL_INPUT_L32 = 1 +DCP_CRC_SOURCE_SEL_INPUT_H32 = 2 +DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 4 +DCP_CRC_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CRC_LINE_SEL' +DCP_CRC_LINE_SEL__enumvalues = { + 0: 'DCP_CRC_LINE_SEL_RESERVED', + 1: 'DCP_CRC_LINE_SEL_EVEN', + 2: 'DCP_CRC_LINE_SEL_ODD', + 3: 'DCP_CRC_LINE_SEL_BOTH', +} +DCP_CRC_LINE_SEL_RESERVED = 0 +DCP_CRC_LINE_SEL_EVEN = 1 +DCP_CRC_LINE_SEL_ODD = 2 +DCP_CRC_LINE_SEL_BOTH = 3 +DCP_CRC_LINE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_FLIP_RATE' +DCP_GRPH_FLIP_RATE__enumvalues = { + 0: 'DCP_GRPH_FLIP_RATE_1FRAME', + 1: 'DCP_GRPH_FLIP_RATE_2FRAME', + 2: 'DCP_GRPH_FLIP_RATE_3FRAME', + 3: 'DCP_GRPH_FLIP_RATE_4FRAME', + 4: 'DCP_GRPH_FLIP_RATE_5FRAME', + 5: 'DCP_GRPH_FLIP_RATE_6FRAME', + 6: 'DCP_GRPH_FLIP_RATE_7FRAME', + 7: 'DCP_GRPH_FLIP_RATE_8FRAME', +} +DCP_GRPH_FLIP_RATE_1FRAME = 0 +DCP_GRPH_FLIP_RATE_2FRAME = 1 +DCP_GRPH_FLIP_RATE_3FRAME = 2 +DCP_GRPH_FLIP_RATE_4FRAME = 3 +DCP_GRPH_FLIP_RATE_5FRAME = 4 +DCP_GRPH_FLIP_RATE_6FRAME = 5 +DCP_GRPH_FLIP_RATE_7FRAME = 6 +DCP_GRPH_FLIP_RATE_8FRAME = 7 +DCP_GRPH_FLIP_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_FLIP_RATE_ENABLE' +DCP_GRPH_FLIP_RATE_ENABLE__enumvalues = { + 0: 'DCP_GRPH_FLIP_RATE_ENABLE_FALSE', + 1: 'DCP_GRPH_FLIP_RATE_ENABLE_TRUE', +} +DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0 +DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 1 +DCP_GRPH_FLIP_RATE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL0_EN' +DCP_GSL0_EN__enumvalues = { + 0: 'DCP_GSL0_EN_FALSE', + 1: 'DCP_GSL0_EN_TRUE', +} +DCP_GSL0_EN_FALSE = 0 +DCP_GSL0_EN_TRUE = 1 +DCP_GSL0_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL1_EN' +DCP_GSL1_EN__enumvalues = { + 0: 'DCP_GSL1_EN_FALSE', + 1: 'DCP_GSL1_EN_TRUE', +} +DCP_GSL1_EN_FALSE = 0 +DCP_GSL1_EN_TRUE = 1 +DCP_GSL1_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL2_EN' +DCP_GSL2_EN__enumvalues = { + 0: 'DCP_GSL2_EN_FALSE', + 1: 'DCP_GSL2_EN_TRUE', +} +DCP_GSL2_EN_FALSE = 0 +DCP_GSL2_EN_TRUE = 1 +DCP_GSL2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL_MASTER_EN' +DCP_GSL_MASTER_EN__enumvalues = { + 0: 'DCP_GSL_MASTER_EN_FALSE', + 1: 'DCP_GSL_MASTER_EN_TRUE', +} +DCP_GSL_MASTER_EN_FALSE = 0 +DCP_GSL_MASTER_EN_TRUE = 1 +DCP_GSL_MASTER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL_XDMA_GROUP' +DCP_GSL_XDMA_GROUP__enumvalues = { + 0: 'DCP_GSL_XDMA_GROUP_VSYNC', + 1: 'DCP_GSL_XDMA_GROUP_HSYNC0', + 2: 'DCP_GSL_XDMA_GROUP_HSYNC1', + 3: 'DCP_GSL_XDMA_GROUP_HSYNC2', +} +DCP_GSL_XDMA_GROUP_VSYNC = 0 +DCP_GSL_XDMA_GROUP_HSYNC0 = 1 +DCP_GSL_XDMA_GROUP_HSYNC1 = 2 +DCP_GSL_XDMA_GROUP_HSYNC2 = 3 +DCP_GSL_XDMA_GROUP = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN' +DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__enumvalues = { + 0: 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE', + 1: 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE', +} +DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0 +DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 1 +DCP_GSL_XDMA_GROUP_UNDERFLOW_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL_SYNC_SOURCE' +DCP_GSL_SYNC_SOURCE__enumvalues = { + 0: 'DCP_GSL_SYNC_SOURCE_FLIP', + 1: 'DCP_GSL_SYNC_SOURCE_PHASE0', + 2: 'DCP_GSL_SYNC_SOURCE_RESET', + 3: 'DCP_GSL_SYNC_SOURCE_PHASE1', +} +DCP_GSL_SYNC_SOURCE_FLIP = 0 +DCP_GSL_SYNC_SOURCE_PHASE0 = 1 +DCP_GSL_SYNC_SOURCE_RESET = 2 +DCP_GSL_SYNC_SOURCE_PHASE1 = 3 +DCP_GSL_SYNC_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC' +DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC__enumvalues = { + 0: 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS', + 1: 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN', +} +DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS = 0 +DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN = 1 +DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING' +DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__enumvalues = { + 0: 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE', + 1: 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE', +} +DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0 +DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 1 +DCP_GSL_DELAY_SURFACE_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_TEST_DEBUG_WRITE_EN' +DCP_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'DCP_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'DCP_TEST_DEBUG_WRITE_EN_TRUE', +} +DCP_TEST_DEBUG_WRITE_EN_FALSE = 0 +DCP_TEST_DEBUG_WRITE_EN_TRUE = 1 +DCP_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_STEREOSYNC_FLIP_EN' +DCP_GRPH_STEREOSYNC_FLIP_EN__enumvalues = { + 0: 'DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE', + 1: 'DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE', +} +DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0 +DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 1 +DCP_GRPH_STEREOSYNC_FLIP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_STEREOSYNC_FLIP_MODE' +DCP_GRPH_STEREOSYNC_FLIP_MODE__enumvalues = { + 0: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP', + 1: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0', + 2: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET', + 3: 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1', +} +DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0 +DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 1 +DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 2 +DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 3 +DCP_GRPH_STEREOSYNC_FLIP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE' +DCP_GRPH_STEREOSYNC_SELECT_DISABLE__enumvalues = { + 0: 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE', + 1: 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE', +} +DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0 +DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 1 +DCP_GRPH_STEREOSYNC_SELECT_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_ROTATION_ANGLE' +DCP_GRPH_ROTATION_ANGLE__enumvalues = { + 0: 'DCP_GRPH_ROTATION_ANGLE_0', + 1: 'DCP_GRPH_ROTATION_ANGLE_90', + 2: 'DCP_GRPH_ROTATION_ANGLE_180', + 3: 'DCP_GRPH_ROTATION_ANGLE_270', +} +DCP_GRPH_ROTATION_ANGLE_0 = 0 +DCP_GRPH_ROTATION_ANGLE_90 = 1 +DCP_GRPH_ROTATION_ANGLE_180 = 2 +DCP_GRPH_ROTATION_ANGLE_270 = 3 +DCP_GRPH_ROTATION_ANGLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN' +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__enumvalues = { + 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE', + 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE', +} +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 1 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE' +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__enumvalues = { + 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM', + 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE', +} +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE = 1 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_REGAMMA_MODE' +DCP_GRPH_REGAMMA_MODE__enumvalues = { + 0: 'DCP_GRPH_REGAMMA_MODE_BYPASS', + 1: 'DCP_GRPH_REGAMMA_MODE_SRGB', + 2: 'DCP_GRPH_REGAMMA_MODE_XVYCC', + 3: 'DCP_GRPH_REGAMMA_MODE_PROGA', + 4: 'DCP_GRPH_REGAMMA_MODE_PROGB', +} +DCP_GRPH_REGAMMA_MODE_BYPASS = 0 +DCP_GRPH_REGAMMA_MODE_SRGB = 1 +DCP_GRPH_REGAMMA_MODE_XVYCC = 2 +DCP_GRPH_REGAMMA_MODE_PROGA = 3 +DCP_GRPH_REGAMMA_MODE_PROGB = 4 +DCP_GRPH_REGAMMA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_ALPHA_ROUND_TRUNC_MODE' +DCP_ALPHA_ROUND_TRUNC_MODE__enumvalues = { + 0: 'DCP_ALPHA_ROUND_TRUNC_MODE_ROUND', + 1: 'DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC', +} +DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0 +DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 1 +DCP_ALPHA_ROUND_TRUNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_CURSOR_ALPHA_BLND_ENA' +DCP_CURSOR_ALPHA_BLND_ENA__enumvalues = { + 0: 'DCP_CURSOR_ALPHA_BLND_ENA_FALSE', + 1: 'DCP_CURSOR_ALPHA_BLND_ENA_TRUE', +} +DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0 +DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 1 +DCP_CURSOR_ALPHA_BLND_ENA = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK' +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__enumvalues = { + 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE', + 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE', +} +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 1 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK' +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__enumvalues = { + 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE', + 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE', +} +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 1 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK' +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__enumvalues = { + 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE', + 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE', +} +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 1 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK' +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__enumvalues = { + 0: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE', + 1: 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE', +} +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 1 +DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_COUNTER_EN' +DCP_GRPH_SURFACE_COUNTER_EN__enumvalues = { + 0: 'DCP_GRPH_SURFACE_COUNTER_EN_DISABLE', + 1: 'DCP_GRPH_SURFACE_COUNTER_EN_ENABLE', +} +DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0 +DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 1 +DCP_GRPH_SURFACE_COUNTER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT' +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT__enumvalues = { + 0: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0', + 1: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1', + 2: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2', + 3: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3', + 4: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4', + 5: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5', + 6: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6', + 7: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7', + 8: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8', + 9: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9', + 10: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10', + 11: 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11', +} +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 1 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 2 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 3 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 4 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 5 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 6 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 7 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 8 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 9 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 10 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 11 +DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED' +DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__enumvalues = { + 0: 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO', + 1: 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES', +} +DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0 +DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 1 +DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR' +DCP_GRPH_XDMA_FLIP_TYPE_CLEAR__enumvalues = { + 0: 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE', + 1: 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE', +} +DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE = 0 +DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE = 1 +DCP_GRPH_XDMA_FLIP_TYPE_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_DRR_MODE_ENABLE' +DCP_GRPH_XDMA_DRR_MODE_ENABLE__enumvalues = { + 0: 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE', + 1: 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE', +} +DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE = 0 +DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE = 1 +DCP_GRPH_XDMA_DRR_MODE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE' +DCP_GRPH_XDMA_MULTIFLIP_ENABLE__enumvalues = { + 0: 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE', + 1: 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE', +} +DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE = 0 +DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE = 1 +DCP_GRPH_XDMA_MULTIFLIP_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK' +DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK__enumvalues = { + 0: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE', + 1: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE', +} +DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE = 0 +DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE = 1 +DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK' +DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK__enumvalues = { + 0: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE', + 1: 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE', +} +DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE = 0 +DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE = 1 +DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CVALUE_SEL' +PERFCOUNTER_CVALUE_SEL__enumvalues = { + 0: 'PERFCOUNTER_CVALUE_SEL_47_0', + 1: 'PERFCOUNTER_CVALUE_SEL_15_0', + 2: 'PERFCOUNTER_CVALUE_SEL_31_16', + 3: 'PERFCOUNTER_CVALUE_SEL_47_32', + 4: 'PERFCOUNTER_CVALUE_SEL_11_0', + 5: 'PERFCOUNTER_CVALUE_SEL_23_12', + 6: 'PERFCOUNTER_CVALUE_SEL_35_24', + 7: 'PERFCOUNTER_CVALUE_SEL_47_36', +} +PERFCOUNTER_CVALUE_SEL_47_0 = 0 +PERFCOUNTER_CVALUE_SEL_15_0 = 1 +PERFCOUNTER_CVALUE_SEL_31_16 = 2 +PERFCOUNTER_CVALUE_SEL_47_32 = 3 +PERFCOUNTER_CVALUE_SEL_11_0 = 4 +PERFCOUNTER_CVALUE_SEL_23_12 = 5 +PERFCOUNTER_CVALUE_SEL_35_24 = 6 +PERFCOUNTER_CVALUE_SEL_47_36 = 7 +PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INC_MODE' +PERFCOUNTER_INC_MODE__enumvalues = { + 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', + 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', + 2: 'PERFCOUNTER_INC_MODE_LSB', + 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', + 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', +} +PERFCOUNTER_INC_MODE_MULTI_BIT = 0 +PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 +PERFCOUNTER_INC_MODE_LSB = 2 +PERFCOUNTER_INC_MODE_POS_EDGE = 3 +PERFCOUNTER_INC_MODE_NEG_EDGE = 4 +PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' +PERFCOUNTER_HW_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', + 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', +} +PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 +PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 +PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RUNEN_MODE' +PERFCOUNTER_RUNEN_MODE__enumvalues = { + 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', +} +PERFCOUNTER_RUNEN_MODE_LEVEL = 0 +PERFCOUNTER_RUNEN_MODE_EDGE = 1 +PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' +PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { + 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', + 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', +} +PERFCOUNTER_CNTOFF_START_ENABLE = 0 +PERFCOUNTER_CNTOFF_START_DISABLE = 1 +PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RESTART_EN' +PERFCOUNTER_RESTART_EN__enumvalues = { + 0: 'PERFCOUNTER_RESTART_DISABLE', + 1: 'PERFCOUNTER_RESTART_ENABLE', +} +PERFCOUNTER_RESTART_DISABLE = 0 +PERFCOUNTER_RESTART_ENABLE = 1 +PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_EN' +PERFCOUNTER_INT_EN__enumvalues = { + 0: 'PERFCOUNTER_INT_DISABLE', + 1: 'PERFCOUNTER_INT_ENABLE', +} +PERFCOUNTER_INT_DISABLE = 0 +PERFCOUNTER_INT_ENABLE = 1 +PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_OFF_MASK' +PERFCOUNTER_OFF_MASK__enumvalues = { + 0: 'PERFCOUNTER_OFF_MASK_DISABLE', + 1: 'PERFCOUNTER_OFF_MASK_ENABLE', +} +PERFCOUNTER_OFF_MASK_DISABLE = 0 +PERFCOUNTER_OFF_MASK_ENABLE = 1 +PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_ACTIVE' +PERFCOUNTER_ACTIVE__enumvalues = { + 0: 'PERFCOUNTER_IS_IDLE', + 1: 'PERFCOUNTER_IS_ACTIVE', +} +PERFCOUNTER_IS_IDLE = 0 +PERFCOUNTER_IS_ACTIVE = 1 +PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_TYPE' +PERFCOUNTER_INT_TYPE__enumvalues = { + 0: 'PERFCOUNTER_INT_TYPE_LEVEL', + 1: 'PERFCOUNTER_INT_TYPE_PULSE', +} +PERFCOUNTER_INT_TYPE_LEVEL = 0 +PERFCOUNTER_INT_TYPE_PULSE = 1 +PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' +PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { + 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', +} +PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 +PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 +PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 +PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTL_SEL' +PERFCOUNTER_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_CNTL_SEL_0', + 1: 'PERFCOUNTER_CNTL_SEL_1', + 2: 'PERFCOUNTER_CNTL_SEL_2', + 3: 'PERFCOUNTER_CNTL_SEL_3', + 4: 'PERFCOUNTER_CNTL_SEL_4', + 5: 'PERFCOUNTER_CNTL_SEL_5', + 6: 'PERFCOUNTER_CNTL_SEL_6', + 7: 'PERFCOUNTER_CNTL_SEL_7', +} +PERFCOUNTER_CNTL_SEL_0 = 0 +PERFCOUNTER_CNTL_SEL_1 = 1 +PERFCOUNTER_CNTL_SEL_2 = 2 +PERFCOUNTER_CNTL_SEL_3 = 3 +PERFCOUNTER_CNTL_SEL_4 = 4 +PERFCOUNTER_CNTL_SEL_5 = 5 +PERFCOUNTER_CNTL_SEL_6 = 6 +PERFCOUNTER_CNTL_SEL_7 = 7 +PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT0_STATE' +PERFCOUNTER_CNT0_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT0_STATE_RESET', + 1: 'PERFCOUNTER_CNT0_STATE_START', + 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT0_STATE_HW', +} +PERFCOUNTER_CNT0_STATE_RESET = 0 +PERFCOUNTER_CNT0_STATE_START = 1 +PERFCOUNTER_CNT0_STATE_FREEZE = 2 +PERFCOUNTER_CNT0_STATE_HW = 3 +PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL0' +PERFCOUNTER_STATE_SEL0__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', +} +PERFCOUNTER_STATE_SEL0_GLOBAL = 0 +PERFCOUNTER_STATE_SEL0_LOCAL = 1 +PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT1_STATE' +PERFCOUNTER_CNT1_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT1_STATE_RESET', + 1: 'PERFCOUNTER_CNT1_STATE_START', + 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT1_STATE_HW', +} +PERFCOUNTER_CNT1_STATE_RESET = 0 +PERFCOUNTER_CNT1_STATE_START = 1 +PERFCOUNTER_CNT1_STATE_FREEZE = 2 +PERFCOUNTER_CNT1_STATE_HW = 3 +PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL1' +PERFCOUNTER_STATE_SEL1__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', +} +PERFCOUNTER_STATE_SEL1_GLOBAL = 0 +PERFCOUNTER_STATE_SEL1_LOCAL = 1 +PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT2_STATE' +PERFCOUNTER_CNT2_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT2_STATE_RESET', + 1: 'PERFCOUNTER_CNT2_STATE_START', + 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT2_STATE_HW', +} +PERFCOUNTER_CNT2_STATE_RESET = 0 +PERFCOUNTER_CNT2_STATE_START = 1 +PERFCOUNTER_CNT2_STATE_FREEZE = 2 +PERFCOUNTER_CNT2_STATE_HW = 3 +PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL2' +PERFCOUNTER_STATE_SEL2__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', +} +PERFCOUNTER_STATE_SEL2_GLOBAL = 0 +PERFCOUNTER_STATE_SEL2_LOCAL = 1 +PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT3_STATE' +PERFCOUNTER_CNT3_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT3_STATE_RESET', + 1: 'PERFCOUNTER_CNT3_STATE_START', + 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT3_STATE_HW', +} +PERFCOUNTER_CNT3_STATE_RESET = 0 +PERFCOUNTER_CNT3_STATE_START = 1 +PERFCOUNTER_CNT3_STATE_FREEZE = 2 +PERFCOUNTER_CNT3_STATE_HW = 3 +PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL3' +PERFCOUNTER_STATE_SEL3__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', +} +PERFCOUNTER_STATE_SEL3_GLOBAL = 0 +PERFCOUNTER_STATE_SEL3_LOCAL = 1 +PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT4_STATE' +PERFCOUNTER_CNT4_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT4_STATE_RESET', + 1: 'PERFCOUNTER_CNT4_STATE_START', + 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT4_STATE_HW', +} +PERFCOUNTER_CNT4_STATE_RESET = 0 +PERFCOUNTER_CNT4_STATE_START = 1 +PERFCOUNTER_CNT4_STATE_FREEZE = 2 +PERFCOUNTER_CNT4_STATE_HW = 3 +PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL4' +PERFCOUNTER_STATE_SEL4__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', +} +PERFCOUNTER_STATE_SEL4_GLOBAL = 0 +PERFCOUNTER_STATE_SEL4_LOCAL = 1 +PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT5_STATE' +PERFCOUNTER_CNT5_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT5_STATE_RESET', + 1: 'PERFCOUNTER_CNT5_STATE_START', + 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT5_STATE_HW', +} +PERFCOUNTER_CNT5_STATE_RESET = 0 +PERFCOUNTER_CNT5_STATE_START = 1 +PERFCOUNTER_CNT5_STATE_FREEZE = 2 +PERFCOUNTER_CNT5_STATE_HW = 3 +PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL5' +PERFCOUNTER_STATE_SEL5__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', +} +PERFCOUNTER_STATE_SEL5_GLOBAL = 0 +PERFCOUNTER_STATE_SEL5_LOCAL = 1 +PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT6_STATE' +PERFCOUNTER_CNT6_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT6_STATE_RESET', + 1: 'PERFCOUNTER_CNT6_STATE_START', + 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT6_STATE_HW', +} +PERFCOUNTER_CNT6_STATE_RESET = 0 +PERFCOUNTER_CNT6_STATE_START = 1 +PERFCOUNTER_CNT6_STATE_FREEZE = 2 +PERFCOUNTER_CNT6_STATE_HW = 3 +PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL6' +PERFCOUNTER_STATE_SEL6__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', +} +PERFCOUNTER_STATE_SEL6_GLOBAL = 0 +PERFCOUNTER_STATE_SEL6_LOCAL = 1 +PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT7_STATE' +PERFCOUNTER_CNT7_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT7_STATE_RESET', + 1: 'PERFCOUNTER_CNT7_STATE_START', + 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT7_STATE_HW', +} +PERFCOUNTER_CNT7_STATE_RESET = 0 +PERFCOUNTER_CNT7_STATE_START = 1 +PERFCOUNTER_CNT7_STATE_FREEZE = 2 +PERFCOUNTER_CNT7_STATE_HW = 3 +PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL7' +PERFCOUNTER_STATE_SEL7__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', +} +PERFCOUNTER_STATE_SEL7_GLOBAL = 0 +PERFCOUNTER_STATE_SEL7_LOCAL = 1 +PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_STATE' +PERFMON_STATE__enumvalues = { + 0: 'PERFMON_STATE_RESET', + 1: 'PERFMON_STATE_START', + 2: 'PERFMON_STATE_FREEZE', + 3: 'PERFMON_STATE_HW', +} +PERFMON_STATE_RESET = 0 +PERFMON_STATE_START = 1 +PERFMON_STATE_FREEZE = 2 +PERFMON_STATE_HW = 3 +PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_AND_OR' +PERFMON_CNTOFF_AND_OR__enumvalues = { + 0: 'PERFMON_CNTOFF_OR', + 1: 'PERFMON_CNTOFF_AND', +} +PERFMON_CNTOFF_OR = 0 +PERFMON_CNTOFF_AND = 1 +PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_EN' +PERFMON_CNTOFF_INT_EN__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_DISABLE', + 1: 'PERFMON_CNTOFF_INT_ENABLE', +} +PERFMON_CNTOFF_INT_DISABLE = 0 +PERFMON_CNTOFF_INT_ENABLE = 1 +PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_TYPE' +PERFMON_CNTOFF_INT_TYPE__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', + 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', +} +PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 +PERFMON_CNTOFF_INT_TYPE_PULSE = 1 +PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_C_RAM_TAP_PAIR_IDX' +SCL_C_RAM_TAP_PAIR_IDX__enumvalues = { + 0: 'SCL_C_RAM_TAP_PAIR_ID0', + 1: 'SCL_C_RAM_TAP_PAIR_ID1', + 2: 'SCL_C_RAM_TAP_PAIR_ID2', + 3: 'SCL_C_RAM_TAP_PAIR_ID3', + 4: 'SCL_C_RAM_TAP_PAIR_ID4', +} +SCL_C_RAM_TAP_PAIR_ID0 = 0 +SCL_C_RAM_TAP_PAIR_ID1 = 1 +SCL_C_RAM_TAP_PAIR_ID2 = 2 +SCL_C_RAM_TAP_PAIR_ID3 = 3 +SCL_C_RAM_TAP_PAIR_ID4 = 4 +SCL_C_RAM_TAP_PAIR_IDX = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_C_RAM_PHASE' +SCL_C_RAM_PHASE__enumvalues = { + 0: 'SCL_C_RAM_PHASE_0', + 1: 'SCL_C_RAM_PHASE_1', + 2: 'SCL_C_RAM_PHASE_2', + 3: 'SCL_C_RAM_PHASE_3', + 4: 'SCL_C_RAM_PHASE_4', + 5: 'SCL_C_RAM_PHASE_5', + 6: 'SCL_C_RAM_PHASE_6', + 7: 'SCL_C_RAM_PHASE_7', + 8: 'SCL_C_RAM_PHASE_8', +} +SCL_C_RAM_PHASE_0 = 0 +SCL_C_RAM_PHASE_1 = 1 +SCL_C_RAM_PHASE_2 = 2 +SCL_C_RAM_PHASE_3 = 3 +SCL_C_RAM_PHASE_4 = 4 +SCL_C_RAM_PHASE_5 = 5 +SCL_C_RAM_PHASE_6 = 6 +SCL_C_RAM_PHASE_7 = 7 +SCL_C_RAM_PHASE_8 = 8 +SCL_C_RAM_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_C_RAM_FILTER_TYPE' +SCL_C_RAM_FILTER_TYPE__enumvalues = { + 0: 'SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT', + 1: 'SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT', + 2: 'SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT', + 3: 'SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT', +} +SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0 +SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 1 +SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 2 +SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 3 +SCL_C_RAM_FILTER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_MODE_SEL' +SCL_MODE_SEL__enumvalues = { + 0: 'SCL_MODE_RGB_BYPASS', + 1: 'SCL_MODE_RGB_SCALING', + 2: 'SCL_MODE_YCBCR_SCALING', + 3: 'SCL_MODE_YCBCR_BYPASS', +} +SCL_MODE_RGB_BYPASS = 0 +SCL_MODE_RGB_SCALING = 1 +SCL_MODE_YCBCR_SCALING = 2 +SCL_MODE_YCBCR_BYPASS = 3 +SCL_MODE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_PSCL_EN' +SCL_PSCL_EN__enumvalues = { + 0: 'SCL_PSCL_DISABLE', + 1: 'SCL_PSCL_ENANBLE', +} +SCL_PSCL_DISABLE = 0 +SCL_PSCL_ENANBLE = 1 +SCL_PSCL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_V_NUM_OF_TAPS' +SCL_V_NUM_OF_TAPS__enumvalues = { + 0: 'SCL_V_NUM_OF_TAPS_1', + 1: 'SCL_V_NUM_OF_TAPS_2', + 2: 'SCL_V_NUM_OF_TAPS_3', + 3: 'SCL_V_NUM_OF_TAPS_4', + 4: 'SCL_V_NUM_OF_TAPS_5', + 5: 'SCL_V_NUM_OF_TAPS_6', +} +SCL_V_NUM_OF_TAPS_1 = 0 +SCL_V_NUM_OF_TAPS_2 = 1 +SCL_V_NUM_OF_TAPS_3 = 2 +SCL_V_NUM_OF_TAPS_4 = 3 +SCL_V_NUM_OF_TAPS_5 = 4 +SCL_V_NUM_OF_TAPS_6 = 5 +SCL_V_NUM_OF_TAPS = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_H_NUM_OF_TAPS' +SCL_H_NUM_OF_TAPS__enumvalues = { + 0: 'SCL_H_NUM_OF_TAPS_1', + 1: 'SCL_H_NUM_OF_TAPS_2', + 3: 'SCL_H_NUM_OF_TAPS_4', + 5: 'SCL_H_NUM_OF_TAPS_6', + 7: 'SCL_H_NUM_OF_TAPS_8', + 9: 'SCL_H_NUM_OF_TAPS_10', +} +SCL_H_NUM_OF_TAPS_1 = 0 +SCL_H_NUM_OF_TAPS_2 = 1 +SCL_H_NUM_OF_TAPS_4 = 3 +SCL_H_NUM_OF_TAPS_6 = 5 +SCL_H_NUM_OF_TAPS_8 = 7 +SCL_H_NUM_OF_TAPS_10 = 9 +SCL_H_NUM_OF_TAPS = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_BOUNDARY_MODE' +SCL_BOUNDARY_MODE__enumvalues = { + 0: 'SCL_BOUNDARY_MODE_BLACK', + 1: 'SCL_BOUNDARY_MODE_EDGE', +} +SCL_BOUNDARY_MODE_BLACK = 0 +SCL_BOUNDARY_MODE_EDGE = 1 +SCL_BOUNDARY_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_EARLY_EOL_MOD' +SCL_EARLY_EOL_MOD__enumvalues = { + 0: 'SCL_EARLY_EOL_MODE_CRTC', + 1: 'SCL_EARLY_EOL_MODE_INTERNAL', +} +SCL_EARLY_EOL_MODE_CRTC = 0 +SCL_EARLY_EOL_MODE_INTERNAL = 1 +SCL_EARLY_EOL_MOD = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_BYPASS_MODE' +SCL_BYPASS_MODE__enumvalues = { + 0: 'SCL_BYPASS_MODE_MC_MR', + 1: 'SCL_BYPASS_MODE_AC_NR', + 2: 'SCL_BYPASS_MODE_AC_AR', + 3: 'SCL_BYPASS_MODE_RESERVED', +} +SCL_BYPASS_MODE_MC_MR = 0 +SCL_BYPASS_MODE_AC_NR = 1 +SCL_BYPASS_MODE_AC_AR = 2 +SCL_BYPASS_MODE_RESERVED = 3 +SCL_BYPASS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_V_MANUAL_REPLICATE_FACTOR' +SCL_V_MANUAL_REPLICATE_FACTOR__enumvalues = { + 0: 'SCL_V_MANUAL_REPLICATE_FACTOR_1', + 1: 'SCL_V_MANUAL_REPLICATE_FACTOR_2', + 2: 'SCL_V_MANUAL_REPLICATE_FACTOR_3', + 3: 'SCL_V_MANUAL_REPLICATE_FACTOR_4', + 4: 'SCL_V_MANUAL_REPLICATE_FACTOR_5', + 5: 'SCL_V_MANUAL_REPLICATE_FACTOR_6', + 6: 'SCL_V_MANUAL_REPLICATE_FACTOR_7', + 7: 'SCL_V_MANUAL_REPLICATE_FACTOR_8', + 8: 'SCL_V_MANUAL_REPLICATE_FACTOR_9', + 9: 'SCL_V_MANUAL_REPLICATE_FACTOR_10', + 10: 'SCL_V_MANUAL_REPLICATE_FACTOR_11', + 11: 'SCL_V_MANUAL_REPLICATE_FACTOR_12', + 12: 'SCL_V_MANUAL_REPLICATE_FACTOR_13', + 13: 'SCL_V_MANUAL_REPLICATE_FACTOR_14', + 14: 'SCL_V_MANUAL_REPLICATE_FACTOR_15', + 15: 'SCL_V_MANUAL_REPLICATE_FACTOR_16', +} +SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0 +SCL_V_MANUAL_REPLICATE_FACTOR_2 = 1 +SCL_V_MANUAL_REPLICATE_FACTOR_3 = 2 +SCL_V_MANUAL_REPLICATE_FACTOR_4 = 3 +SCL_V_MANUAL_REPLICATE_FACTOR_5 = 4 +SCL_V_MANUAL_REPLICATE_FACTOR_6 = 5 +SCL_V_MANUAL_REPLICATE_FACTOR_7 = 6 +SCL_V_MANUAL_REPLICATE_FACTOR_8 = 7 +SCL_V_MANUAL_REPLICATE_FACTOR_9 = 8 +SCL_V_MANUAL_REPLICATE_FACTOR_10 = 9 +SCL_V_MANUAL_REPLICATE_FACTOR_11 = 10 +SCL_V_MANUAL_REPLICATE_FACTOR_12 = 11 +SCL_V_MANUAL_REPLICATE_FACTOR_13 = 12 +SCL_V_MANUAL_REPLICATE_FACTOR_14 = 13 +SCL_V_MANUAL_REPLICATE_FACTOR_15 = 14 +SCL_V_MANUAL_REPLICATE_FACTOR_16 = 15 +SCL_V_MANUAL_REPLICATE_FACTOR = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_H_MANUAL_REPLICATE_FACTOR' +SCL_H_MANUAL_REPLICATE_FACTOR__enumvalues = { + 0: 'SCL_H_MANUAL_REPLICATE_FACTOR_1', + 1: 'SCL_H_MANUAL_REPLICATE_FACTOR_2', + 2: 'SCL_H_MANUAL_REPLICATE_FACTOR_3', + 3: 'SCL_H_MANUAL_REPLICATE_FACTOR_4', + 4: 'SCL_H_MANUAL_REPLICATE_FACTOR_5', + 5: 'SCL_H_MANUAL_REPLICATE_FACTOR_6', + 6: 'SCL_H_MANUAL_REPLICATE_FACTOR_7', + 7: 'SCL_H_MANUAL_REPLICATE_FACTOR_8', + 8: 'SCL_H_MANUAL_REPLICATE_FACTOR_9', + 9: 'SCL_H_MANUAL_REPLICATE_FACTOR_10', + 10: 'SCL_H_MANUAL_REPLICATE_FACTOR_11', + 11: 'SCL_H_MANUAL_REPLICATE_FACTOR_12', + 12: 'SCL_H_MANUAL_REPLICATE_FACTOR_13', + 13: 'SCL_H_MANUAL_REPLICATE_FACTOR_14', + 14: 'SCL_H_MANUAL_REPLICATE_FACTOR_15', + 15: 'SCL_H_MANUAL_REPLICATE_FACTOR_16', +} +SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0 +SCL_H_MANUAL_REPLICATE_FACTOR_2 = 1 +SCL_H_MANUAL_REPLICATE_FACTOR_3 = 2 +SCL_H_MANUAL_REPLICATE_FACTOR_4 = 3 +SCL_H_MANUAL_REPLICATE_FACTOR_5 = 4 +SCL_H_MANUAL_REPLICATE_FACTOR_6 = 5 +SCL_H_MANUAL_REPLICATE_FACTOR_7 = 6 +SCL_H_MANUAL_REPLICATE_FACTOR_8 = 7 +SCL_H_MANUAL_REPLICATE_FACTOR_9 = 8 +SCL_H_MANUAL_REPLICATE_FACTOR_10 = 9 +SCL_H_MANUAL_REPLICATE_FACTOR_11 = 10 +SCL_H_MANUAL_REPLICATE_FACTOR_12 = 11 +SCL_H_MANUAL_REPLICATE_FACTOR_13 = 12 +SCL_H_MANUAL_REPLICATE_FACTOR_14 = 13 +SCL_H_MANUAL_REPLICATE_FACTOR_15 = 14 +SCL_H_MANUAL_REPLICATE_FACTOR_16 = 15 +SCL_H_MANUAL_REPLICATE_FACTOR = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_V_CALC_AUTO_RATIO_EN' +SCL_V_CALC_AUTO_RATIO_EN__enumvalues = { + 0: 'SCL_V_CALC_AUTO_RATIO_DISABLE', + 1: 'SCL_V_CALC_AUTO_RATIO_ENABLE', +} +SCL_V_CALC_AUTO_RATIO_DISABLE = 0 +SCL_V_CALC_AUTO_RATIO_ENABLE = 1 +SCL_V_CALC_AUTO_RATIO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_H_CALC_AUTO_RATIO_EN' +SCL_H_CALC_AUTO_RATIO_EN__enumvalues = { + 0: 'SCL_H_CALC_AUTO_RATIO_DISABLE', + 1: 'SCL_H_CALC_AUTO_RATIO_ENABLE', +} +SCL_H_CALC_AUTO_RATIO_DISABLE = 0 +SCL_H_CALC_AUTO_RATIO_ENABLE = 1 +SCL_H_CALC_AUTO_RATIO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_H_FILTER_PICK_NEAREST' +SCL_H_FILTER_PICK_NEAREST__enumvalues = { + 0: 'SCL_H_FILTER_PICK_NEAREST_DISABLE', + 1: 'SCL_H_FILTER_PICK_NEAREST_ENABLE', +} +SCL_H_FILTER_PICK_NEAREST_DISABLE = 0 +SCL_H_FILTER_PICK_NEAREST_ENABLE = 1 +SCL_H_FILTER_PICK_NEAREST = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_H_2TAP_HARDCODE_COEF_EN' +SCL_H_2TAP_HARDCODE_COEF_EN__enumvalues = { + 0: 'SCL_H_2TAP_HARDCODE_COEF_DISABLE', + 1: 'SCL_H_2TAP_HARDCODE_COEF_ENABLE', +} +SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0 +SCL_H_2TAP_HARDCODE_COEF_ENABLE = 1 +SCL_H_2TAP_HARDCODE_COEF_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_V_FILTER_PICK_NEAREST' +SCL_V_FILTER_PICK_NEAREST__enumvalues = { + 0: 'SCL_V_FILTER_PICK_NEAREST_DISABLE', + 1: 'SCL_V_FILTER_PICK_NEAREST_ENABLE', +} +SCL_V_FILTER_PICK_NEAREST_DISABLE = 0 +SCL_V_FILTER_PICK_NEAREST_ENABLE = 1 +SCL_V_FILTER_PICK_NEAREST = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_V_2TAP_HARDCODE_COEF_EN' +SCL_V_2TAP_HARDCODE_COEF_EN__enumvalues = { + 0: 'SCL_V_2TAP_HARDCODE_COEF_DISABLE', + 1: 'SCL_V_2TAP_HARDCODE_COEF_ENABLE', +} +SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0 +SCL_V_2TAP_HARDCODE_COEF_ENABLE = 1 +SCL_V_2TAP_HARDCODE_COEF_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_UPDATE_TAKEN' +SCL_UPDATE_TAKEN__enumvalues = { + 0: 'SCL_UPDATE_TAKEN_NO', + 1: 'SCL_UPDATE_TAKEN_YES', +} +SCL_UPDATE_TAKEN_NO = 0 +SCL_UPDATE_TAKEN_YES = 1 +SCL_UPDATE_TAKEN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_UPDATE_LOCK' +SCL_UPDATE_LOCK__enumvalues = { + 0: 'SCL_UPDATE_UNLOCKED', + 1: 'SCL_UPDATE_LOCKED', +} +SCL_UPDATE_UNLOCKED = 0 +SCL_UPDATE_LOCKED = 1 +SCL_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_COEF_UPDATE_COMPLETE' +SCL_COEF_UPDATE_COMPLETE__enumvalues = { + 0: 'SCL_COEF_UPDATE_NOT_COMPLETED', + 1: 'SCL_COEF_UPDATE_COMPLETED', +} +SCL_COEF_UPDATE_NOT_COMPLETED = 0 +SCL_COEF_UPDATE_COMPLETED = 1 +SCL_COEF_UPDATE_COMPLETE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_HF_SHARP_SCALE_FACTOR' +SCL_HF_SHARP_SCALE_FACTOR__enumvalues = { + 0: 'SCL_HF_SHARP_SCALE_FACTOR_0', + 1: 'SCL_HF_SHARP_SCALE_FACTOR_1', + 2: 'SCL_HF_SHARP_SCALE_FACTOR_2', + 3: 'SCL_HF_SHARP_SCALE_FACTOR_3', + 4: 'SCL_HF_SHARP_SCALE_FACTOR_4', + 5: 'SCL_HF_SHARP_SCALE_FACTOR_5', + 6: 'SCL_HF_SHARP_SCALE_FACTOR_6', + 7: 'SCL_HF_SHARP_SCALE_FACTOR_7', +} +SCL_HF_SHARP_SCALE_FACTOR_0 = 0 +SCL_HF_SHARP_SCALE_FACTOR_1 = 1 +SCL_HF_SHARP_SCALE_FACTOR_2 = 2 +SCL_HF_SHARP_SCALE_FACTOR_3 = 3 +SCL_HF_SHARP_SCALE_FACTOR_4 = 4 +SCL_HF_SHARP_SCALE_FACTOR_5 = 5 +SCL_HF_SHARP_SCALE_FACTOR_6 = 6 +SCL_HF_SHARP_SCALE_FACTOR_7 = 7 +SCL_HF_SHARP_SCALE_FACTOR = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_HF_SHARP_EN' +SCL_HF_SHARP_EN__enumvalues = { + 0: 'SCL_HF_SHARP_DISABLE', + 1: 'SCL_HF_SHARP_ENABLE', +} +SCL_HF_SHARP_DISABLE = 0 +SCL_HF_SHARP_ENABLE = 1 +SCL_HF_SHARP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_VF_SHARP_SCALE_FACTOR' +SCL_VF_SHARP_SCALE_FACTOR__enumvalues = { + 0: 'SCL_VF_SHARP_SCALE_FACTOR_0', + 1: 'SCL_VF_SHARP_SCALE_FACTOR_1', + 2: 'SCL_VF_SHARP_SCALE_FACTOR_2', + 3: 'SCL_VF_SHARP_SCALE_FACTOR_3', + 4: 'SCL_VF_SHARP_SCALE_FACTOR_4', + 5: 'SCL_VF_SHARP_SCALE_FACTOR_5', + 6: 'SCL_VF_SHARP_SCALE_FACTOR_6', + 7: 'SCL_VF_SHARP_SCALE_FACTOR_7', +} +SCL_VF_SHARP_SCALE_FACTOR_0 = 0 +SCL_VF_SHARP_SCALE_FACTOR_1 = 1 +SCL_VF_SHARP_SCALE_FACTOR_2 = 2 +SCL_VF_SHARP_SCALE_FACTOR_3 = 3 +SCL_VF_SHARP_SCALE_FACTOR_4 = 4 +SCL_VF_SHARP_SCALE_FACTOR_5 = 5 +SCL_VF_SHARP_SCALE_FACTOR_6 = 6 +SCL_VF_SHARP_SCALE_FACTOR_7 = 7 +SCL_VF_SHARP_SCALE_FACTOR = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_VF_SHARP_EN' +SCL_VF_SHARP_EN__enumvalues = { + 0: 'SCL_VF_SHARP_DISABLE', + 1: 'SCL_VF_SHARP_ENABLE', +} +SCL_VF_SHARP_DISABLE = 0 +SCL_VF_SHARP_ENABLE = 1 +SCL_VF_SHARP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_ALU_DISABLE' +SCL_ALU_DISABLE__enumvalues = { + 0: 'SCL_ALU_ENABLED', + 1: 'SCL_ALU_DISABLED', +} +SCL_ALU_ENABLED = 0 +SCL_ALU_DISABLED = 1 +SCL_ALU_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_HOST_CONFLICT_MASK' +SCL_HOST_CONFLICT_MASK__enumvalues = { + 0: 'SCL_HOST_CONFLICT_DISABLE_INTERRUPT', + 1: 'SCL_HOST_CONFLICT_ENABLE_INTERRUPT', +} +SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0 +SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 1 +SCL_HOST_CONFLICT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_SCL_MODE_CHANGE_MASK' +SCL_SCL_MODE_CHANGE_MASK__enumvalues = { + 0: 'SCL_MODE_CHANGE_DISABLE_INTERRUPT', + 1: 'SCL_MODE_CHANGE_ENABLE_INTERRUPT', +} +SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0 +SCL_MODE_CHANGE_ENABLE_INTERRUPT = 1 +SCL_SCL_MODE_CHANGE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'SCLV_MODE_SEL' +SCLV_MODE_SEL__enumvalues = { + 0: 'SCLV_MODE_RGB_BYPASS', + 1: 'SCLV_MODE_RGB_SCALING', + 2: 'SCLV_MODE_YCBCR_SCALING', + 3: 'SCLV_MODE_YCBCR_BYPASS', +} +SCLV_MODE_RGB_BYPASS = 0 +SCLV_MODE_RGB_SCALING = 1 +SCLV_MODE_YCBCR_SCALING = 2 +SCLV_MODE_YCBCR_BYPASS = 3 +SCLV_MODE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCLV_INTERLACE_SOURCE' +SCLV_INTERLACE_SOURCE__enumvalues = { + 0: 'INTERLACE_SOURCE_PROGRESSIVE', + 1: 'INTERLACE_SOURCE_INTERLEAVE', + 2: 'INTERLACE_SOURCE_STACK', +} +INTERLACE_SOURCE_PROGRESSIVE = 0 +INTERLACE_SOURCE_INTERLEAVE = 1 +INTERLACE_SOURCE_STACK = 2 +SCLV_INTERLACE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'SCLV_UPDATE_LOCK' +SCLV_UPDATE_LOCK__enumvalues = { + 0: 'UPDATE_UNLOCKED', + 1: 'UPDATE_LOCKED', +} +UPDATE_UNLOCKED = 0 +UPDATE_LOCKED = 1 +SCLV_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'SCLV_COEF_UPDATE_COMPLETE' +SCLV_COEF_UPDATE_COMPLETE__enumvalues = { + 0: 'COEF_UPDATE_NOT_COMPLETE', + 1: 'COEF_UPDATE_COMPLETE', +} +COEF_UPDATE_NOT_COMPLETE = 0 +COEF_UPDATE_COMPLETE = 1 +SCLV_COEF_UPDATE_COMPLETE = ctypes.c_uint32 # enum + +# values for enumeration 'DPRX_SD_PIXEL_ENCODING' +DPRX_SD_PIXEL_ENCODING__enumvalues = { + 0: 'PIXEL_FORMAT_RGB_444', + 1: 'PIXEL_FORMAT_YCBCR_444', + 2: 'PIXEL_FORMAT_YCBCR_422', + 3: 'PIXEL_FORMAT_Y_ONLY', +} +PIXEL_FORMAT_RGB_444 = 0 +PIXEL_FORMAT_YCBCR_444 = 1 +PIXEL_FORMAT_YCBCR_422 = 2 +PIXEL_FORMAT_Y_ONLY = 3 +DPRX_SD_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'DPRX_SD_COMPONENT_DEPTH' +DPRX_SD_COMPONENT_DEPTH__enumvalues = { + 0: 'COMPONENT_DEPTH_6BPC', + 1: 'COMPONENT_DEPTH_8BPC', + 2: 'COMPONENT_DEPTH_10BPC', + 3: 'COMPONENT_DEPTH_12BPC', + 4: 'COMPONENT_DEPTH_16BPC', +} +COMPONENT_DEPTH_6BPC = 0 +COMPONENT_DEPTH_8BPC = 1 +COMPONENT_DEPTH_10BPC = 2 +COMPONENT_DEPTH_12BPC = 3 +COMPONENT_DEPTH_16BPC = 4 +DPRX_SD_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' +AZ_LATENCY_COUNTER_CONTROL__enumvalues = { + 0: 'AZ_LATENCY_COUNTER_NO_RESET', + 1: 'AZ_LATENCY_COUNTER_RESET_DONE', +} +AZ_LATENCY_COUNTER_NO_RESET = 0 +AZ_LATENCY_COUNTER_RESET_DONE = 1 +AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_MODE' +BLND_CONTROL_BLND_MODE__enumvalues = { + 0: 'BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', + 1: 'BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', + 2: 'BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', + 3: 'BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', +} +BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0 +BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 1 +BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 2 +BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 3 +BLND_CONTROL_BLND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_STEREO_TYPE' +BLND_CONTROL_BLND_STEREO_TYPE__enumvalues = { + 0: 'BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', + 1: 'BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', + 2: 'BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', + 3: 'BLND_CONTROL_BLND_STEREO_TYPE_UNUSED', +} +BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0 +BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 1 +BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 2 +BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 3 +BLND_CONTROL_BLND_STEREO_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_STEREO_POLARITY' +BLND_CONTROL_BLND_STEREO_POLARITY__enumvalues = { + 0: 'BLND_CONTROL_BLND_STEREO_POLARITY_LOW', + 1: 'BLND_CONTROL_BLND_STEREO_POLARITY_HIGH', +} +BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0 +BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 1 +BLND_CONTROL_BLND_STEREO_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_FEEDTHROUGH_EN' +BLND_CONTROL_BLND_FEEDTHROUGH_EN__enumvalues = { + 0: 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', + 1: 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', +} +BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0 +BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 1 +BLND_CONTROL_BLND_FEEDTHROUGH_EN = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_ALPHA_MODE' +BLND_CONTROL_BLND_ALPHA_MODE__enumvalues = { + 0: 'BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', + 1: 'BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 2: 'BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', + 3: 'BLND_CONTROL_BLND_ALPHA_MODE_UNUSED', +} +BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0 +BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 +BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 2 +BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 3 +BLND_CONTROL_BLND_ALPHA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY' +BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY__enumvalues = { + 0: 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE', + 1: 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE', +} +BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE = 0 +BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE = 1 +BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL_BLND_MULTIPLIED_MODE' +BLND_CONTROL_BLND_MULTIPLIED_MODE__enumvalues = { + 0: 'BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE', + 1: 'BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE', +} +BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0 +BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 1 +BLND_CONTROL_BLND_MULTIPLIED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_SM_CONTROL2_SM_MODE' +BLND_SM_CONTROL2_SM_MODE__enumvalues = { + 0: 'BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE', + 2: 'BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', + 4: 'BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', + 6: 'BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', +} +BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0 +BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 2 +BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 4 +BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 +BLND_SM_CONTROL2_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE' +BLND_SM_CONTROL2_SM_FRAME_ALTERNATE__enumvalues = { + 0: 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', + 1: 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', +} +BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0 +BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 1 +BLND_SM_CONTROL2_SM_FRAME_ALTERNATE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE' +BLND_SM_CONTROL2_SM_FIELD_ALTERNATE__enumvalues = { + 0: 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', + 1: 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', +} +BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0 +BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 1 +BLND_SM_CONTROL2_SM_FIELD_ALTERNATE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL' +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL__enumvalues = { + 0: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 1: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 2: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 3: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', +} +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 +BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL' +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL__enumvalues = { + 0: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 1: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', + 2: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 3: 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', +} +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 +BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL2_PTI_ENABLE' +BLND_CONTROL2_PTI_ENABLE__enumvalues = { + 0: 'BLND_CONTROL2_PTI_ENABLE_FALSE', + 1: 'BLND_CONTROL2_PTI_ENABLE_TRUE', +} +BLND_CONTROL2_PTI_ENABLE_FALSE = 0 +BLND_CONTROL2_PTI_ENABLE_TRUE = 1 +BLND_CONTROL2_PTI_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN' +BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN__enumvalues = { + 0: 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', + 1: 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', +} +BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0 +BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 1 +BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN' +BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN__enumvalues = { + 0: 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', + 1: 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', +} +BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0 +BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 1 +BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK' +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK__enumvalues = { + 0: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', + 1: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', +} +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0 +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 1 +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK' +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK__enumvalues = { + 0: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', + 1: 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', +} +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0 +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 1 +BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK' +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK' +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK' +BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK' +BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK' +BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK' +BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE' +BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE__enumvalues = { + 0: 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', + 1: 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', +} +BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0 +BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 1 +BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_DEBUG_BLND_CNV_MUX_SELECT' +BLND_DEBUG_BLND_CNV_MUX_SELECT__enumvalues = { + 0: 'BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW', + 1: 'BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH', +} +BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0 +BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 1 +BLND_DEBUG_BLND_CNV_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN' +BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', +} +BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0 +BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 1 +BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', +} +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_EN' +UNP_GRPH_EN__enumvalues = { + 0: 'UNP_GRPH_DISABLED', + 1: 'UNP_GRPH_ENABLED', +} +UNP_GRPH_DISABLED = 0 +UNP_GRPH_ENABLED = 1 +UNP_GRPH_EN = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_DEPTH' +UNP_GRPH_DEPTH__enumvalues = { + 0: 'UNP_GRPH_8BPP', + 1: 'UNP_GRPH_16BPP', + 2: 'UNP_GRPH_32BPP', +} +UNP_GRPH_8BPP = 0 +UNP_GRPH_16BPP = 1 +UNP_GRPH_32BPP = 2 +UNP_GRPH_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_NUM_BANKS' +UNP_GRPH_NUM_BANKS__enumvalues = { + 0: 'UNP_GRPH_ADDR_SURF_2_BANK', + 1: 'UNP_GRPH_ADDR_SURF_4_BANK', + 2: 'UNP_GRPH_ADDR_SURF_8_BANK', + 3: 'UNP_GRPH_ADDR_SURF_16_BANK', +} +UNP_GRPH_ADDR_SURF_2_BANK = 0 +UNP_GRPH_ADDR_SURF_4_BANK = 1 +UNP_GRPH_ADDR_SURF_8_BANK = 2 +UNP_GRPH_ADDR_SURF_16_BANK = 3 +UNP_GRPH_NUM_BANKS = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_BANK_WIDTH' +UNP_GRPH_BANK_WIDTH__enumvalues = { + 0: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_1', + 1: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_2', + 2: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_4', + 3: 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_8', +} +UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0 +UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 1 +UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 2 +UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 3 +UNP_GRPH_BANK_WIDTH = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_BANK_HEIGHT' +UNP_GRPH_BANK_HEIGHT__enumvalues = { + 0: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1', + 1: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2', + 2: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4', + 3: 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8', +} +UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0 +UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 1 +UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 2 +UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 3 +UNP_GRPH_BANK_HEIGHT = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_TILE_SPLIT' +UNP_GRPH_TILE_SPLIT__enumvalues = { + 0: 'UNP_ADDR_SURF_TILE_SPLIT_64B', + 1: 'UNP_ADDR_SURF_TILE_SPLIT_128B', + 2: 'UNP_ADDR_SURF_TILE_SPLIT_256B', + 3: 'UNP_ADDR_SURF_TILE_SPLIT_512B', + 4: 'UNP_ADDR_SURF_TILE_SPLIT_1KB', + 5: 'UNP_ADDR_SURF_TILE_SPLIT_2KB', + 6: 'UNP_ADDR_SURF_TILE_SPLIT_4KB', +} +UNP_ADDR_SURF_TILE_SPLIT_64B = 0 +UNP_ADDR_SURF_TILE_SPLIT_128B = 1 +UNP_ADDR_SURF_TILE_SPLIT_256B = 2 +UNP_ADDR_SURF_TILE_SPLIT_512B = 3 +UNP_ADDR_SURF_TILE_SPLIT_1KB = 4 +UNP_ADDR_SURF_TILE_SPLIT_2KB = 5 +UNP_ADDR_SURF_TILE_SPLIT_4KB = 6 +UNP_GRPH_TILE_SPLIT = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE' +UNP_GRPH_ADDRESS_TRANSLATION_ENABLE__enumvalues = { + 0: 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0', + 1: 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1', +} +UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0 +UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 1 +UNP_GRPH_ADDRESS_TRANSLATION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_MACRO_TILE_ASPECT' +UNP_GRPH_MACRO_TILE_ASPECT__enumvalues = { + 0: 'UNP_ADDR_SURF_MACRO_ASPECT_1', + 1: 'UNP_ADDR_SURF_MACRO_ASPECT_2', + 2: 'UNP_ADDR_SURF_MACRO_ASPECT_4', + 3: 'UNP_ADDR_SURF_MACRO_ASPECT_8', +} +UNP_ADDR_SURF_MACRO_ASPECT_1 = 0 +UNP_ADDR_SURF_MACRO_ASPECT_2 = 1 +UNP_ADDR_SURF_MACRO_ASPECT_4 = 2 +UNP_ADDR_SURF_MACRO_ASPECT_8 = 3 +UNP_GRPH_MACRO_TILE_ASPECT = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_COLOR_EXPANSION_MODE' +UNP_GRPH_COLOR_EXPANSION_MODE__enumvalues = { + 0: 'UNP_GRPH_DYNAMIC_EXPANSION', + 1: 'UNP_GRPH_ZERO_EXPANSION', +} +UNP_GRPH_DYNAMIC_EXPANSION = 0 +UNP_GRPH_ZERO_EXPANSION = 1 +UNP_GRPH_COLOR_EXPANSION_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_VIDEO_FORMAT' +UNP_VIDEO_FORMAT__enumvalues = { + 0: 'UNP_VIDEO_FORMAT0', + 1: 'UNP_VIDEO_FORMAT1', + 2: 'UNP_VIDEO_FORMAT_YUV420_YCbCr', + 3: 'UNP_VIDEO_FORMAT_YUV420_YCrCb', + 4: 'UNP_VIDEO_FORMAT_YUV422_YCb', + 5: 'UNP_VIDEO_FORMAT_YUV422_YCr', + 6: 'UNP_VIDEO_FORMAT_YUV422_CbY', + 7: 'UNP_VIDEO_FORMAT_YUV422_CrY', +} +UNP_VIDEO_FORMAT0 = 0 +UNP_VIDEO_FORMAT1 = 1 +UNP_VIDEO_FORMAT_YUV420_YCbCr = 2 +UNP_VIDEO_FORMAT_YUV420_YCrCb = 3 +UNP_VIDEO_FORMAT_YUV422_YCb = 4 +UNP_VIDEO_FORMAT_YUV422_YCr = 5 +UNP_VIDEO_FORMAT_YUV422_CbY = 6 +UNP_VIDEO_FORMAT_YUV422_CrY = 7 +UNP_VIDEO_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_ENDIAN_SWAP' +UNP_GRPH_ENDIAN_SWAP__enumvalues = { + 0: 'UNP_GRPH_ENDIAN_SWAP_NONE', + 1: 'UNP_GRPH_ENDIAN_SWAP_8IN16', + 2: 'UNP_GRPH_ENDIAN_SWAP_8IN32', + 3: 'UNP_GRPH_ENDIAN_SWAP_8IN43', +} +UNP_GRPH_ENDIAN_SWAP_NONE = 0 +UNP_GRPH_ENDIAN_SWAP_8IN16 = 1 +UNP_GRPH_ENDIAN_SWAP_8IN32 = 2 +UNP_GRPH_ENDIAN_SWAP_8IN43 = 3 +UNP_GRPH_ENDIAN_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_RED_CROSSBAR' +UNP_GRPH_RED_CROSSBAR__enumvalues = { + 0: 'UNP_GRPH_RED_CROSSBAR_R_Cr', + 1: 'UNP_GRPH_RED_CROSSBAR_G_Y', + 2: 'UNP_GRPH_RED_CROSSBAR_B_Cb', + 3: 'UNP_GRPH_RED_CROSSBAR_A', +} +UNP_GRPH_RED_CROSSBAR_R_Cr = 0 +UNP_GRPH_RED_CROSSBAR_G_Y = 1 +UNP_GRPH_RED_CROSSBAR_B_Cb = 2 +UNP_GRPH_RED_CROSSBAR_A = 3 +UNP_GRPH_RED_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_GREEN_CROSSBAR' +UNP_GRPH_GREEN_CROSSBAR__enumvalues = { + 0: 'UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y', + 1: 'UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C', + 2: 'UNP_UNP_GRPH_GREEN_CROSSBAR_A', + 3: 'UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr', +} +UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0 +UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 1 +UNP_UNP_GRPH_GREEN_CROSSBAR_A = 2 +UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 3 +UNP_GRPH_GREEN_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_BLUE_CROSSBAR' +UNP_GRPH_BLUE_CROSSBAR__enumvalues = { + 0: 'UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C', + 1: 'UNP_GRPH_BLUE_CROSSBAR_A', + 2: 'UNP_GRPH_BLUE_CROSSBAR_R_Cr', + 3: 'UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y', +} +UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0 +UNP_GRPH_BLUE_CROSSBAR_A = 1 +UNP_GRPH_BLUE_CROSSBAR_R_Cr = 2 +UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 3 +UNP_GRPH_BLUE_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_MODE_UPDATE_LOCKG' +UNP_GRPH_MODE_UPDATE_LOCKG__enumvalues = { + 0: 'UNP_GRPH_UPDATE_LOCK_0', + 1: 'UNP_GRPH_UPDATE_LOCK_1', +} +UNP_GRPH_UPDATE_LOCK_0 = 0 +UNP_GRPH_UPDATE_LOCK_1 = 1 +UNP_GRPH_MODE_UPDATE_LOCKG = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK' +UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK__enumvalues = { + 0: 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0', + 1: 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1', +} +UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0 +UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 1 +UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE' +UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE__enumvalues = { + 0: 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0', + 1: 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1', +} +UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0 +UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 1 +UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE' +UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__enumvalues = { + 0: 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0', + 1: 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1', +} +UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0 +UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 1 +UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_STEREOSYNC_FLIP_EN' +UNP_GRPH_STEREOSYNC_FLIP_EN__enumvalues = { + 0: 'UNP_GRPH_STEREOSYNC_FLIP_DISABLE', + 1: 'UNP_GRPH_STEREOSYNC_FLIP_ENABLE', +} +UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0 +UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 1 +UNP_GRPH_STEREOSYNC_FLIP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_STEREOSYNC_FLIP_MODE' +UNP_GRPH_STEREOSYNC_FLIP_MODE__enumvalues = { + 0: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_0', + 1: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_1', + 2: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_2', + 3: 'UNP_GRPH_STEREOSYNC_FLIP_MODE_3', +} +UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0 +UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 1 +UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 2 +UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 3 +UNP_GRPH_STEREOSYNC_FLIP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_STACK_INTERLACE_FLIP_EN' +UNP_GRPH_STACK_INTERLACE_FLIP_EN__enumvalues = { + 0: 'UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE', + 1: 'UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE', +} +UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0 +UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 1 +UNP_GRPH_STACK_INTERLACE_FLIP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE' +UNP_GRPH_STACK_INTERLACE_FLIP_MODE__enumvalues = { + 0: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0', + 1: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1', + 2: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2', + 3: 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3', +} +UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0 +UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 1 +UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 2 +UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 3 +UNP_GRPH_STACK_INTERLACE_FLIP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_GRPH_STEREOSYNC_SELECT_DISABLE' +UNP_GRPH_STEREOSYNC_SELECT_DISABLE__enumvalues = { + 0: 'UNP_GRPH_STEREOSYNC_SELECT_EN', + 1: 'UNP_GRPH_STEREOSYNC_SELECT_DIS', +} +UNP_GRPH_STEREOSYNC_SELECT_EN = 0 +UNP_GRPH_STEREOSYNC_SELECT_DIS = 1 +UNP_GRPH_STEREOSYNC_SELECT_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_CRC_SOURCE_SEL' +UNP_CRC_SOURCE_SEL__enumvalues = { + 0: 'UNP_CRC_SOURCE_SEL_NP_TO_LBV', + 1: 'UNP_CRC_SOURCE_SEL_LOWER32', + 2: 'UNP_CRC_SOURCE_SEL_RESERVED', + 3: 'UNP_CRC_SOURCE_SEL_LOWER16', + 4: 'UNP_CRC_SOURCE_SEL_UNP_TO_LBV', +} +UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0 +UNP_CRC_SOURCE_SEL_LOWER32 = 1 +UNP_CRC_SOURCE_SEL_RESERVED = 2 +UNP_CRC_SOURCE_SEL_LOWER16 = 3 +UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 4 +UNP_CRC_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_CRC_LINE_SEL' +UNP_CRC_LINE_SEL__enumvalues = { + 0: 'UNP_CRC_LINE_SEL_RESERVED', + 1: 'UNP_CRC_LINE_SEL_EVEN_ONLY', + 2: 'UNP_CRC_LINE_SEL_ODD_ONLY', + 3: 'UNP_CRC_LINE_SEL_ODD_EVEN', +} +UNP_CRC_LINE_SEL_RESERVED = 0 +UNP_CRC_LINE_SEL_EVEN_ONLY = 1 +UNP_CRC_LINE_SEL_ODD_ONLY = 2 +UNP_CRC_LINE_SEL_ODD_EVEN = 3 +UNP_CRC_LINE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_ROTATION_ANGLE' +UNP_ROTATION_ANGLE__enumvalues = { + 0: 'UNP_ROTATION_ANGLE_0', + 1: 'UNP_ROTATION_ANGLE_90', + 2: 'UNP_ROTATION_ANGLE_180', + 3: 'UNP_ROTATION_ANGLE_270', + 4: 'UNP_ROTATION_ANGLE_0m', + 5: 'UNP_ROTATION_ANGLE_90m', + 6: 'UNP_ROTATION_ANGLE_180m', + 7: 'UNP_ROTATION_ANGLE_270m', +} +UNP_ROTATION_ANGLE_0 = 0 +UNP_ROTATION_ANGLE_90 = 1 +UNP_ROTATION_ANGLE_180 = 2 +UNP_ROTATION_ANGLE_270 = 3 +UNP_ROTATION_ANGLE_0m = 4 +UNP_ROTATION_ANGLE_90m = 5 +UNP_ROTATION_ANGLE_180m = 6 +UNP_ROTATION_ANGLE_270m = 7 +UNP_ROTATION_ANGLE = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_PIXEL_DROP' +UNP_PIXEL_DROP__enumvalues = { + 0: 'UNP_PIXEL_NO_DROP', + 1: 'UNP_PIXEL_DROPPING', +} +UNP_PIXEL_NO_DROP = 0 +UNP_PIXEL_DROPPING = 1 +UNP_PIXEL_DROP = ctypes.c_uint32 # enum + +# values for enumeration 'UNP_BUFFER_MODE' +UNP_BUFFER_MODE__enumvalues = { + 0: 'UNP_BUFFER_MODE_LUMA', + 1: 'UNP_BUFFER_MODE_LUMA_CHROMA', +} +UNP_BUFFER_MODE_LUMA = 0 +UNP_BUFFER_MODE_LUMA_CHROMA = 1 +UNP_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_LINK_TRAINING_COMPLETE' +DP_LINK_TRAINING_COMPLETE__enumvalues = { + 0: 'DP_LINK_TRAINING_NOT_COMPLETE', + 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', +} +DP_LINK_TRAINING_NOT_COMPLETE = 0 +DP_LINK_TRAINING_ALREADY_COMPLETE = 1 +DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_EMBEDDED_PANEL_MODE' +DP_EMBEDDED_PANEL_MODE__enumvalues = { + 0: 'DP_EXTERNAL_PANEL', + 1: 'DP_EMBEDDED_PANEL', +} +DP_EXTERNAL_PANEL = 0 +DP_EMBEDDED_PANEL = 1 +DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_PIXEL_ENCODING' +DP_PIXEL_ENCODING__enumvalues = { + 0: 'DP_PIXEL_ENCODING_RGB444', + 1: 'DP_PIXEL_ENCODING_YCBCR422', + 2: 'DP_PIXEL_ENCODING_YCBCR444', + 3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', + 4: 'DP_PIXEL_ENCODING_Y_ONLY', + 5: 'DP_PIXEL_ENCODING_YCBCR420', + 6: 'DP_PIXEL_ENCODING_RESERVED', +} +DP_PIXEL_ENCODING_RGB444 = 0 +DP_PIXEL_ENCODING_YCBCR422 = 1 +DP_PIXEL_ENCODING_YCBCR444 = 2 +DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3 +DP_PIXEL_ENCODING_Y_ONLY = 4 +DP_PIXEL_ENCODING_YCBCR420 = 5 +DP_PIXEL_ENCODING_RESERVED = 6 +DP_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DYN_RANGE' +DP_DYN_RANGE__enumvalues = { + 0: 'DP_DYN_VESA_RANGE', + 1: 'DP_DYN_CEA_RANGE', +} +DP_DYN_VESA_RANGE = 0 +DP_DYN_CEA_RANGE = 1 +DP_DYN_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_YCBCR_RANGE' +DP_YCBCR_RANGE__enumvalues = { + 0: 'DP_YCBCR_RANGE_BT601_5', + 1: 'DP_YCBCR_RANGE_BT709_5', +} +DP_YCBCR_RANGE_BT601_5 = 0 +DP_YCBCR_RANGE_BT709_5 = 1 +DP_YCBCR_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_COMPONENT_DEPTH' +DP_COMPONENT_DEPTH__enumvalues = { + 0: 'DP_COMPONENT_DEPTH_6BPC', + 1: 'DP_COMPONENT_DEPTH_8BPC', + 2: 'DP_COMPONENT_DEPTH_10BPC', + 3: 'DP_COMPONENT_DEPTH_12BPC', + 4: 'DP_COMPONENT_DEPTH_16BPC_RESERVED', + 5: 'DP_COMPONENT_DEPTH_RESERVED', +} +DP_COMPONENT_DEPTH_6BPC = 0 +DP_COMPONENT_DEPTH_8BPC = 1 +DP_COMPONENT_DEPTH_10BPC = 2 +DP_COMPONENT_DEPTH_12BPC = 3 +DP_COMPONENT_DEPTH_16BPC_RESERVED = 4 +DP_COMPONENT_DEPTH_RESERVED = 5 +DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSA_MISC0_OVERRIDE_ENABLE' +DP_MSA_MISC0_OVERRIDE_ENABLE__enumvalues = { + 0: 'MSA_MISC0_OVERRIDE_DISABLE', + 1: 'MSA_MISC0_OVERRIDE_ENABLE', +} +MSA_MISC0_OVERRIDE_DISABLE = 0 +MSA_MISC0_OVERRIDE_ENABLE = 1 +DP_MSA_MISC0_OVERRIDE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE' +DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE__enumvalues = { + 0: 'MSA_MISC1_BIT7_OVERRIDE_DISABLE', + 1: 'MSA_MISC1_BIT7_OVERRIDE_ENABLE', +} +MSA_MISC1_BIT7_OVERRIDE_DISABLE = 0 +MSA_MISC1_BIT7_OVERRIDE_ENABLE = 1 +DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_UDI_LANES' +DP_UDI_LANES__enumvalues = { + 0: 'DP_UDI_1_LANE', + 1: 'DP_UDI_2_LANES', + 2: 'DP_UDI_LANES_RESERVED', + 3: 'DP_UDI_4_LANES', +} +DP_UDI_1_LANE = 0 +DP_UDI_2_LANES = 1 +DP_UDI_LANES_RESERVED = 2 +DP_UDI_4_LANES = 3 +DP_UDI_LANES = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DIS_DEFER' +DP_VID_STREAM_DIS_DEFER__enumvalues = { + 0: 'DP_VID_STREAM_DIS_NO_DEFER', + 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', +} +DP_VID_STREAM_DIS_NO_DEFER = 0 +DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 +DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 +DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_ACK' +DP_STEER_OVERFLOW_ACK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 +DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_MASK' +DP_STEER_OVERFLOW_MASK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_MASKED', + 1: 'DP_STEER_OVERFLOW_UNMASK', +} +DP_STEER_OVERFLOW_MASKED = 0 +DP_STEER_OVERFLOW_UNMASK = 1 +DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_TU_OVERFLOW_ACK' +DP_TU_OVERFLOW_ACK__enumvalues = { + 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 +DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_EN' +DPHY_ALT_SCRAMBLER_RESET_EN__enumvalues = { + 0: 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', + 1: 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', +} +DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0 +DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 1 +DPHY_ALT_SCRAMBLER_RESET_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_SEL' +DPHY_ALT_SCRAMBLER_RESET_SEL__enumvalues = { + 0: 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', + 1: 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', +} +DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0 +DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 1 +DPHY_ALT_SCRAMBLER_RESET_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_TIMING_MODE' +DP_VID_TIMING_MODE__enumvalues = { + 0: 'DP_VID_TIMING_MODE_ASYNC', + 1: 'DP_VID_TIMING_MODE_SYNC', +} +DP_VID_TIMING_MODE_ASYNC = 0 +DP_VID_TIMING_MODE_SYNC = 1 +DP_VID_TIMING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' +DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { + 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', +} +DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 +DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 +DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_GEN_EN' +DP_VID_M_N_GEN_EN__enumvalues = { + 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', + 1: 'DP_VID_M_N_CALC_AUTO', +} +DP_VID_M_N_PROGRAMMED_VIA_REG = 0 +DP_VID_M_N_CALC_AUTO = 1 +DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_DOUBLE_VALUE_EN' +DP_VID_M_DOUBLE_VALUE_EN__enumvalues = { + 0: 'DP_VID_M_INPUT_PIXEL_RATE', + 1: 'DP_VID_M_DOUBLE_INPUT_PIXEL_RATE', +} +DP_VID_M_INPUT_PIXEL_RATE = 0 +DP_VID_M_DOUBLE_INPUT_PIXEL_RATE = 1 +DP_VID_M_DOUBLE_VALUE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' +DP_VID_ENHANCED_FRAME_MODE__enumvalues = { + 0: 'VID_NORMAL_FRAME_MODE', + 1: 'VID_ENHANCED_MODE', +} +VID_NORMAL_FRAME_MODE = 0 +VID_ENHANCED_MODE = 1 +DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_MSA_TOP_FIELD_MODE' +DP_VID_MSA_TOP_FIELD_MODE__enumvalues = { + 0: 'DP_TOP_FIELD_ONLY', + 1: 'DP_TOP_PLUS_BOTTOM_FIELD', +} +DP_TOP_FIELD_ONLY = 0 +DP_TOP_PLUS_BOTTOM_FIELD = 1 +DP_VID_MSA_TOP_FIELD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_VBID_FIELD_POL' +DP_VID_VBID_FIELD_POL__enumvalues = { + 0: 'DP_VID_VBID_FIELD_POL_NORMAL', + 1: 'DP_VID_VBID_FIELD_POL_INV', +} +DP_VID_VBID_FIELD_POL_NORMAL = 0 +DP_VID_VBID_FIELD_POL_INV = 1 +DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_ACK' +DP_VID_STREAM_DISABLE_ACK__enumvalues = { + 0: 'ID_STREAM_DISABLE_NO_ACK', + 1: 'ID_STREAM_DISABLE_ACKED', +} +ID_STREAM_DISABLE_NO_ACK = 0 +ID_STREAM_DISABLE_ACKED = 1 +DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_MASK' +DP_VID_STREAM_DISABLE_MASK__enumvalues = { + 0: 'VID_STREAM_DISABLE_MASKED', + 1: 'VID_STREAM_DISABLE_UNMASK', +} +VID_STREAM_DISABLE_MASKED = 0 +VID_STREAM_DISABLE_UNMASK = 1 +DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE0' +DPHY_ATEST_SEL_LANE0__enumvalues = { + 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE0_REG_PATTERN', +} +DPHY_ATEST_LANE0_PRBS_PATTERN = 0 +DPHY_ATEST_LANE0_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE1' +DPHY_ATEST_SEL_LANE1__enumvalues = { + 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE1_REG_PATTERN', +} +DPHY_ATEST_LANE1_PRBS_PATTERN = 0 +DPHY_ATEST_LANE1_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE2' +DPHY_ATEST_SEL_LANE2__enumvalues = { + 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE2_REG_PATTERN', +} +DPHY_ATEST_LANE2_PRBS_PATTERN = 0 +DPHY_ATEST_LANE2_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE3' +DPHY_ATEST_SEL_LANE3__enumvalues = { + 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE3_REG_PATTERN', +} +DPHY_ATEST_LANE3_PRBS_PATTERN = 0 +DPHY_ATEST_LANE3_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_SEL' +DPHY_SCRAMBLER_SEL__enumvalues = { + 0: 'DPHY_SCRAMBLER_SEL_LANE_DATA', + 1: 'DPHY_SCRAMBLER_SEL_DBG_DATA', +} +DPHY_SCRAMBLER_SEL_LANE_DATA = 0 +DPHY_SCRAMBLER_SEL_DBG_DATA = 1 +DPHY_SCRAMBLER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_BYPASS' +DPHY_BYPASS__enumvalues = { + 0: 'DPHY_8B10B_OUTPUT', + 1: 'DPHY_DBG_OUTPUT', +} +DPHY_8B10B_OUTPUT = 0 +DPHY_DBG_OUTPUT = 1 +DPHY_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SKEW_BYPASS' +DPHY_SKEW_BYPASS__enumvalues = { + 0: 'DPHY_WITH_SKEW', + 1: 'DPHY_NO_SKEW', +} +DPHY_WITH_SKEW = 0 +DPHY_NO_SKEW = 1 +DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_TRAINING_PATTERN_SEL' +DPHY_TRAINING_PATTERN_SEL__enumvalues = { + 0: 'DPHY_TRAINING_PATTERN_1', + 1: 'DPHY_TRAINING_PATTERN_2', + 2: 'DPHY_TRAINING_PATTERN_3', + 3: 'DPHY_TRAINING_PATTERN_4', +} +DPHY_TRAINING_PATTERN_1 = 0 +DPHY_TRAINING_PATTERN_2 = 1 +DPHY_TRAINING_PATTERN_3 = 2 +DPHY_TRAINING_PATTERN_4 = 3 +DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_RESET' +DPHY_8B10B_RESET__enumvalues = { + 0: 'DPHY_8B10B_NOT_RESET', + 1: 'DPHY_8B10B_RESETET', +} +DPHY_8B10B_NOT_RESET = 0 +DPHY_8B10B_RESETET = 1 +DPHY_8B10B_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_8B10B_EXT_DISP' +DP_DPHY_8B10B_EXT_DISP__enumvalues = { + 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', +} +DP_DPHY_8B10B_EXT_DISP_ZERO = 0 +DP_DPHY_8B10B_EXT_DISP_ONE = 1 +DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_CUR_DISP' +DPHY_8B10B_CUR_DISP__enumvalues = { + 0: 'DPHY_8B10B_CUR_DISP_ZERO', + 1: 'DPHY_8B10B_CUR_DISP_ONE', +} +DPHY_8B10B_CUR_DISP_ZERO = 0 +DPHY_8B10B_CUR_DISP_ONE = 1 +DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_EN' +DPHY_PRBS_EN__enumvalues = { + 0: 'DPHY_PRBS_DISABLE', + 1: 'DPHY_PRBS_ENABLE', +} +DPHY_PRBS_DISABLE = 0 +DPHY_PRBS_ENABLE = 1 +DPHY_PRBS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_SEL' +DPHY_PRBS_SEL__enumvalues = { + 0: 'DPHY_PRBS7_SELECTED', + 1: 'DPHY_PRBS23_SELECTED', + 2: 'DPHY_PRBS11_SELECTED', +} +DPHY_PRBS7_SELECTED = 0 +DPHY_PRBS23_SELECTED = 1 +DPHY_PRBS11_SELECTED = 2 +DPHY_PRBS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_DIS' +DPHY_SCRAMBLER_DIS__enumvalues = { + 0: 'DPHY_SCR_ENABLED', + 1: 'DPHY_SCR_DISABLED', +} +DPHY_SCR_ENABLED = 0 +DPHY_SCR_DISABLED = 1 +DPHY_SCRAMBLER_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_ADVANCE' +DPHY_SCRAMBLER_ADVANCE__enumvalues = { + 0: 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', + 1: 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', +} +DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0 +DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 1 +DPHY_SCRAMBLER_ADVANCE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_KCODE' +DPHY_SCRAMBLER_KCODE__enumvalues = { + 0: 'DPHY_SCRAMBLER_KCODE_DISABLED', + 1: 'DPHY_SCRAMBLER_KCODE_ENABLED', +} +DPHY_SCRAMBLER_KCODE_DISABLED = 0 +DPHY_SCRAMBLER_KCODE_ENABLED = 1 +DPHY_SCRAMBLER_KCODE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_LOAD_BS_COUNT_START' +DPHY_LOAD_BS_COUNT_START__enumvalues = { + 0: 'DPHY_LOAD_BS_COUNT_STARTED', + 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', +} +DPHY_LOAD_BS_COUNT_STARTED = 0 +DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 +DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_EN' +DPHY_CRC_EN__enumvalues = { + 0: 'DPHY_CRC_DISABLED', + 1: 'DPHY_CRC_ENABLED', +} +DPHY_CRC_DISABLED = 0 +DPHY_CRC_ENABLED = 1 +DPHY_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_CONT_EN' +DPHY_CRC_CONT_EN__enumvalues = { + 0: 'DPHY_CRC_ONE_SHOT', + 1: 'DPHY_CRC_CONTINUOUS', +} +DPHY_CRC_ONE_SHOT = 0 +DPHY_CRC_CONTINUOUS = 1 +DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_FIELD' +DPHY_CRC_FIELD__enumvalues = { + 0: 'DPHY_CRC_START_FROM_TOP_FIELD', + 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', +} +DPHY_CRC_START_FROM_TOP_FIELD = 0 +DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 +DPHY_CRC_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_SEL' +DPHY_CRC_SEL__enumvalues = { + 0: 'DPHY_CRC_LANE0_SELECTED', + 1: 'DPHY_CRC_LANE1_SELECTED', + 2: 'DPHY_CRC_LANE2_SELECTED', + 3: 'DPHY_CRC_LANE3_SELECTED', +} +DPHY_CRC_LANE0_SELECTED = 0 +DPHY_CRC_LANE1_SELECTED = 1 +DPHY_CRC_LANE2_SELECTED = 2 +DPHY_CRC_LANE3_SELECTED = 3 +DPHY_CRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' +DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { + 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 1: 'DPHY_FAST_TRAINING_CAPABLE', +} +DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 +DPHY_FAST_TRAINING_CAPABLE = 1 +DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_COLLISION_ACK' +DP_SEC_COLLISION_ACK__enumvalues = { + 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', + 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', +} +DP_SEC_COLLISION_ACK_NO_EFFECT = 0 +DP_SEC_COLLISION_ACK_CLR_FLAG = 1 +DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_AUDIO_MUTE' +DP_SEC_AUDIO_MUTE__enumvalues = { + 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', + 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', +} +DP_SEC_AUDIO_MUTE_HW_CTRL = 0 +DP_SEC_AUDIO_MUTE_SW_CTRL = 1 +DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_TIMESTAMP_MODE' +DP_SEC_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', + 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', +} +DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 +DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 +DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_PRIORITY' +DP_SEC_ASP_PRIORITY__enumvalues = { + 0: 'DP_SEC_ASP_LOW_PRIORITY', + 1: 'DP_SEC_ASP_HIGH_PRIORITY', +} +DP_SEC_ASP_LOW_PRIORITY = 0 +DP_SEC_ASP_HIGH_PRIORITY = 1 +DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { + 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', +} +DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_UPDATE_ACT' +DP_MSE_SAT_UPDATE_ACT__enumvalues = { + 0: 'DP_MSE_SAT_UPDATE_NO_ACTION', + 1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', + 2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', +} +DP_MSE_SAT_UPDATE_NO_ACTION = 0 +DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1 +DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2 +DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_LINK_LINE' +DP_MSE_LINK_LINE__enumvalues = { + 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', + 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', + 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', + 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', +} +DP_MSE_LINK_LINE_32_MTP_LONG = 0 +DP_MSE_LINK_LINE_64_MTP_LONG = 1 +DP_MSE_LINK_LINE_128_MTP_LONG = 2 +DP_MSE_LINK_LINE_256_MTP_LONG = 3 +DP_MSE_LINK_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_BLANK_CODE' +DP_MSE_BLANK_CODE__enumvalues = { + 0: 'DP_MSE_BLANK_CODE_SF_FILLED', + 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', +} +DP_MSE_BLANK_CODE_SF_FILLED = 0 +DP_MSE_BLANK_CODE_ZERO_FILLED = 1 +DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_TIMESTAMP_MODE' +DP_MSE_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', +} +DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 +DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 +DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_ZERO_ENCODER' +DP_MSE_ZERO_ENCODER__enumvalues = { + 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', + 1: 'DP_MSE_ZERO_FE_ENCODER', +} +DP_MSE_NOT_ZERO_FE_ENCODER = 0 +DP_MSE_ZERO_FE_ENCODER = 1 +DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_OUTPUT_DPDBG_DATA' +DP_MSE_OUTPUT_DPDBG_DATA__enumvalues = { + 0: 'DP_MSE_OUTPUT_DPDBG_DATA_DIS', + 1: 'DP_MSE_OUTPUT_DPDBG_DATA_EN', +} +DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0 +DP_MSE_OUTPUT_DPDBG_DATA_EN = 1 +DP_MSE_OUTPUT_DPDBG_DATA = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' +DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { + 0: 'DP_DPHY_HBR2_PASS_THROUGH', + 1: 'DP_DPHY_HBR2_PATTERN_1', + 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', + 3: 'DP_DPHY_HBR2_PATTERN_3', + 6: 'DP_DPHY_HBR2_PATTERN_2_POS', +} +DP_DPHY_HBR2_PASS_THROUGH = 0 +DP_DPHY_HBR2_PATTERN_1 = 1 +DP_DPHY_HBR2_PATTERN_2_NEG = 2 +DP_DPHY_HBR2_PATTERN_3 = 3 +DP_DPHY_HBR2_PATTERN_2_POS = 6 +DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' +DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { + 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', + 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', +} +DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 +DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 +DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SW_FAST_TRAINING_START' +DPHY_SW_FAST_TRAINING_START__enumvalues = { + 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 1: 'DPHY_SW_FAST_TRAINING_STARTED', +} +DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 +DPHY_SW_FAST_TRAINING_STARTED = 1 +DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', +} +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' +DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' +DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' +DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { + 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', + 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', +} +MSA_V_TIMING_OVERRIDE_DISABLED = 0 +MSA_V_TIMING_OVERRIDE_ENABLED = 1 +DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP0_PRIORITY' +DP_SEC_GSP0_PRIORITY__enumvalues = { + 0: 'SEC_GSP0_PRIORITY_LOW', + 1: 'SEC_GSP0_PRIORITY_HIGH', +} +SEC_GSP0_PRIORITY_LOW = 0 +SEC_GSP0_PRIORITY_HIGH = 1 +DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP0_SEND' +DP_SEC_GSP0_SEND__enumvalues = { + 0: 'NOT_SENT', + 1: 'FORCE_SENT', +} +NOT_SENT = 0 +FORCE_SENT = 1 +DP_SEC_GSP0_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_UPDATE_LOCK' +COL_MAN_UPDATE_LOCK__enumvalues = { + 0: 'COL_MAN_UPDATE_UNLOCKED', + 1: 'COL_MAN_UPDATE_LOCKED', +} +COL_MAN_UPDATE_UNLOCKED = 0 +COL_MAN_UPDATE_LOCKED = 1 +COL_MAN_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_DISABLE_MULTIPLE_UPDATE' +COL_MAN_DISABLE_MULTIPLE_UPDATE__enumvalues = { + 0: 'COL_MAN_MULTIPLE_UPDATE', + 1: 'COL_MAN_MULTIPLE_UPDAT_EDISABLE', +} +COL_MAN_MULTIPLE_UPDATE = 0 +COL_MAN_MULTIPLE_UPDAT_EDISABLE = 1 +COL_MAN_DISABLE_MULTIPLE_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_INPUTCSC_MODE' +COL_MAN_INPUTCSC_MODE__enumvalues = { + 0: 'INPUTCSC_MODE_BYPASS', + 1: 'INPUTCSC_MODE_A', + 2: 'INPUTCSC_MODE_B', + 3: 'INPUTCSC_MODE_UNITY', +} +INPUTCSC_MODE_BYPASS = 0 +INPUTCSC_MODE_A = 1 +INPUTCSC_MODE_B = 2 +INPUTCSC_MODE_UNITY = 3 +COL_MAN_INPUTCSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_INPUTCSC_TYPE' +COL_MAN_INPUTCSC_TYPE__enumvalues = { + 0: 'INPUTCSC_TYPE_12_0', + 1: 'INPUTCSC_TYPE_10_2', + 2: 'INPUTCSC_TYPE_8_4', +} +INPUTCSC_TYPE_12_0 = 0 +INPUTCSC_TYPE_10_2 = 1 +INPUTCSC_TYPE_8_4 = 2 +COL_MAN_INPUTCSC_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_INPUTCSC_CONVERT' +COL_MAN_INPUTCSC_CONVERT__enumvalues = { + 0: 'INPUTCSC_ROUND', + 1: 'INPUTCSC_TRUNCATE', +} +INPUTCSC_ROUND = 0 +INPUTCSC_TRUNCATE = 1 +COL_MAN_INPUTCSC_CONVERT = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_PRESCALE_MODE' +COL_MAN_PRESCALE_MODE__enumvalues = { + 0: 'PRESCALE_MODE_BYPASS', + 1: 'PRESCALE_MODE_PROGRAM', + 2: 'PRESCALE_MODE_UNITY', +} +PRESCALE_MODE_BYPASS = 0 +PRESCALE_MODE_PROGRAM = 1 +PRESCALE_MODE_UNITY = 2 +COL_MAN_PRESCALE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_INPUT_GAMMA_MODE' +COL_MAN_INPUT_GAMMA_MODE__enumvalues = { + 0: 'INGAMMA_MODE_BYPASS', + 1: 'INGAMMA_MODE_FIX', + 2: 'INGAMMA_MODE_FLOAT', +} +INGAMMA_MODE_BYPASS = 0 +INGAMMA_MODE_FIX = 1 +INGAMMA_MODE_FLOAT = 2 +COL_MAN_INPUT_GAMMA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_OUTPUT_CSC_MODE' +COL_MAN_OUTPUT_CSC_MODE__enumvalues = { + 0: 'COL_MAN_OUTPUT_CSC_BYPASS', + 1: 'COL_MAN_OUTPUT_CSC_RGB', + 2: 'COL_MAN_OUTPUT_CSC_YCrCb601', + 3: 'COL_MAN_OUTPUT_CSC_YCrCb709', + 4: 'COL_MAN_OUTPUT_CSC_A', + 5: 'COL_MAN_OUTPUT_CSC_B', + 6: 'COL_MAN_OUTPUT_CSC_UNITY', +} +COL_MAN_OUTPUT_CSC_BYPASS = 0 +COL_MAN_OUTPUT_CSC_RGB = 1 +COL_MAN_OUTPUT_CSC_YCrCb601 = 2 +COL_MAN_OUTPUT_CSC_YCrCb709 = 3 +COL_MAN_OUTPUT_CSC_A = 4 +COL_MAN_OUTPUT_CSC_B = 5 +COL_MAN_OUTPUT_CSC_UNITY = 6 +COL_MAN_OUTPUT_CSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_DENORM_CLAMP_CONTROL' +COL_MAN_DENORM_CLAMP_CONTROL__enumvalues = { + 0: 'DENORM_CLAMP_MODE_UNITY', + 1: 'DENORM_CLAMP_MODE_8', + 2: 'DENORM_CLAMP_MODE_10', + 3: 'DENORM_CLAMP_MODE_12', +} +DENORM_CLAMP_MODE_UNITY = 0 +DENORM_CLAMP_MODE_8 = 1 +DENORM_CLAMP_MODE_10 = 2 +DENORM_CLAMP_MODE_12 = 3 +COL_MAN_DENORM_CLAMP_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_REGAMMA_MODE_CONTROL' +COL_MAN_REGAMMA_MODE_CONTROL__enumvalues = { + 0: 'COL_MAN_REGAMMA_MODE_BYPASS', + 1: 'COL_MAN_REGAMMA_MODE_ROM_A', + 2: 'COL_MAN_REGAMMA_MODE_ROM_B', + 3: 'COL_MAN_REGAMMA_MODE_A', + 4: 'COL_MAN_REGAMMA_MODE_B', +} +COL_MAN_REGAMMA_MODE_BYPASS = 0 +COL_MAN_REGAMMA_MODE_ROM_A = 1 +COL_MAN_REGAMMA_MODE_ROM_B = 2 +COL_MAN_REGAMMA_MODE_A = 3 +COL_MAN_REGAMMA_MODE_B = 4 +COL_MAN_REGAMMA_MODE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_GLOBAL_PASSTHROUGH_ENABLE' +COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__enumvalues = { + 0: 'CM_GLOBAL_PASSTHROUGH_DISBALE', + 1: 'CM_GLOBAL_PASSTHROUGH_ENABLE', +} +CM_GLOBAL_PASSTHROUGH_DISBALE = 0 +CM_GLOBAL_PASSTHROUGH_ENABLE = 1 +COL_MAN_GLOBAL_PASSTHROUGH_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_DEGAMMA_MODE' +COL_MAN_DEGAMMA_MODE__enumvalues = { + 0: 'DEGAMMA_MODE_BYPASS', + 1: 'DEGAMMA_MODE_A', + 2: 'DEGAMMA_MODE_B', +} +DEGAMMA_MODE_BYPASS = 0 +DEGAMMA_MODE_A = 1 +DEGAMMA_MODE_B = 2 +COL_MAN_DEGAMMA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'COL_MAN_GAMUT_REMAP_MODE' +COL_MAN_GAMUT_REMAP_MODE__enumvalues = { + 0: 'GAMUT_REMAP_MODE_BYPASS', + 1: 'GAMUT_REMAP_MODE_1', + 2: 'GAMUT_REMAP_MODE_2', + 3: 'GAMUT_REMAP_MODE_3', +} +GAMUT_REMAP_MODE_BYPASS = 0 +GAMUT_REMAP_MODE_1 = 1 +GAMUT_REMAP_MODE_2 = 2 +GAMUT_REMAP_MODE_3 = 3 +COL_MAN_GAMUT_REMAP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_HPD_SEL' +DP_AUX_CONTROL_HPD_SEL__enumvalues = { + 0: 'DP_AUX_CONTROL_HPD1_SELECTED', + 1: 'DP_AUX_CONTROL_HPD2_SELECTED', + 2: 'DP_AUX_CONTROL_HPD3_SELECTED', + 3: 'DP_AUX_CONTROL_HPD4_SELECTED', + 4: 'DP_AUX_CONTROL_HPD5_SELECTED', + 5: 'DP_AUX_CONTROL_HPD6_SELECTED', +} +DP_AUX_CONTROL_HPD1_SELECTED = 0 +DP_AUX_CONTROL_HPD2_SELECTED = 1 +DP_AUX_CONTROL_HPD3_SELECTED = 2 +DP_AUX_CONTROL_HPD4_SELECTED = 3 +DP_AUX_CONTROL_HPD5_SELECTED = 4 +DP_AUX_CONTROL_HPD6_SELECTED = 5 +DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_TEST_MODE' +DP_AUX_CONTROL_TEST_MODE__enumvalues = { + 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', +} +DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 +DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 +DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' +DP_AUX_SW_CONTROL_SW_GO__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 1: 'DP_AUX_SW_CONTROL_SW__GO', +} +DP_AUX_SW_CONTROL_SW__NOT_GO = 0 +DP_AUX_SW_CONTROL_SW__GO = 1 +DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' +DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', +} +DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 +DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 +DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' +DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', +} +DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 +DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', +} +DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 +DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', +} +DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 +DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_INT_ACK' +DP_AUX_INT_ACK__enumvalues = { + 0: 'DP_AUX_INT__NOT_ACK', + 1: 'DP_AUX_INT__ACK', +} +DP_AUX_INT__NOT_ACK = 0 +DP_AUX_INT__ACK = 1 +DP_AUX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_LS_UPDATE_ACK' +DP_AUX_LS_UPDATE_ACK__enumvalues = { + 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', + 1: 'DP_AUX_INT_LS_UPDATE_ACK', +} +DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 +DP_AUX_INT_LS_UPDATE_ACK = 1 +DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN' +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US', + 1: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US', + 2: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US', + 3: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US', + 4: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US', + 5: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US', + 6: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US', + 7: 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US', +} +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 1 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 2 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 3 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 4 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 5 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 6 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 7 +DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { + 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', +} +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', +} +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', +} +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN' +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US', + 1: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US', + 2: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US', + 3: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US', + 4: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US', + 5: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US', + 6: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US', + 7: 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US', +} +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 1 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 2 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 3 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 4 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 5 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 6 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 7 +DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { + 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', +} +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', +} +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', +} +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', +} +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', +} +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' +DP_AUX_ERR_OCCURRED_ACK__enumvalues = { + 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 1: 'DP_AUX_ERR_OCCURRED__ACK', +} +DP_AUX_ERR_OCCURRED__NOT_ACK = 0 +DP_AUX_ERR_OCCURRED__ACK = 1 +DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' +DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { + 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', + 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', +} +DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 +DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 +DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' +DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { + 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', + 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', +} +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 +DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET' +DP_AUX_RESET__enumvalues = { + 0: 'DP_AUX_RESET_DEASSERTED', + 1: 'DP_AUX_RESET_ASSERTED', +} +DP_AUX_RESET_DEASSERTED = 0 +DP_AUX_RESET_ASSERTED = 1 +DP_AUX_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET_DONE' +DP_AUX_RESET_DONE__enumvalues = { + 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', + 1: 'DP_AUX_RESET_SEQUENCE_DONE', +} +DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 +DP_AUX_RESET_SEQUENCE_DONE = 1 +DP_AUX_RESET_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_COMMAND_MODE_SRC_FORMAT' +DSI_COMMAND_MODE_SRC_FORMAT__enumvalues = { + 2: 'DSI_COMMAND_SRC_FORMAT_RGB8BIT', + 3: 'DSI_COMMAND_SRC_FORMAT_RGB332', + 4: 'DSI_COMMAND_SRC_FORMAT_RGB444', + 5: 'DSI_COMMAND_SRC_FORMAT_RGB555', + 6: 'DSI_COMMAND_SRC_FORMAT_RGB565', + 8: 'DSI_COMMAND_SRC_FORMAT_RGB888', +} +DSI_COMMAND_SRC_FORMAT_RGB8BIT = 2 +DSI_COMMAND_SRC_FORMAT_RGB332 = 3 +DSI_COMMAND_SRC_FORMAT_RGB444 = 4 +DSI_COMMAND_SRC_FORMAT_RGB555 = 5 +DSI_COMMAND_SRC_FORMAT_RGB565 = 6 +DSI_COMMAND_SRC_FORMAT_RGB888 = 8 +DSI_COMMAND_MODE_SRC_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_COMMAND_MODE_DST_FORMAT' +DSI_COMMAND_MODE_DST_FORMAT__enumvalues = { + 0: 'DSI_COMMAND_DST_FORMAT_RGB111', + 3: 'DSI_COMMAND_DST_FORMAT_RGB332', + 4: 'DSI_COMMAND_DST_FORMAT_RGB444', + 6: 'DSI_COMMAND_DST_FORMAT_RGB565', + 7: 'DSI_COMMAND_DST_FORMAT_RGB666', + 8: 'DSI_COMMAND_DST_FORMAT_RGB888', +} +DSI_COMMAND_DST_FORMAT_RGB111 = 0 +DSI_COMMAND_DST_FORMAT_RGB332 = 3 +DSI_COMMAND_DST_FORMAT_RGB444 = 4 +DSI_COMMAND_DST_FORMAT_RGB565 = 6 +DSI_COMMAND_DST_FORMAT_RGB666 = 7 +DSI_COMMAND_DST_FORMAT_RGB888 = 8 +DSI_COMMAND_MODE_DST_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_FLAG_CLR' +DSI_FLAG_CLR__enumvalues = { + 0: 'DSI_FLAG_NO_CLEAR', + 1: 'DSI_FLAG_CLEAR', +} +DSI_FLAG_NO_CLEAR = 0 +DSI_FLAG_CLEAR = 1 +DSI_FLAG_CLR = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_BIT_SWAP' +DSI_BIT_SWAP__enumvalues = { + 0: 'DSI_BIT_SWAP_DISABLE', + 1: 'DSI_BIT_SWAP_ENABLE', +} +DSI_BIT_SWAP_DISABLE = 0 +DSI_BIT_SWAP_ENABLE = 1 +DSI_BIT_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CLK_GATING' +DSI_CLK_GATING__enumvalues = { + 0: 'DSI_CLK_GATING_ENABLE', + 1: 'DSI_CLK_GATING_DISABLE', +} +DSI_CLK_GATING_ENABLE = 0 +DSI_CLK_GATING_DISABLE = 1 +DSI_CLK_GATING = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_LANE_ULPS_REQUEST' +DSI_LANE_ULPS_REQUEST__enumvalues = { + 0: 'DSI_LANE_ULPS_REQUEST_DEASSERT', + 1: 'DSI_LANE_ULPS_REQUEST_ASSERT', +} +DSI_LANE_ULPS_REQUEST_DEASSERT = 0 +DSI_LANE_ULPS_REQUEST_ASSERT = 1 +DSI_LANE_ULPS_REQUEST = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_LANE_ULPS_EXIT' +DSI_LANE_ULPS_EXIT__enumvalues = { + 0: 'DSI_LANE_ULPS_EXIT_DEASSERT', + 1: 'DSI_LANE_ULPS_EXIT_ASSERT', +} +DSI_LANE_ULPS_EXIT_DEASSERT = 0 +DSI_LANE_ULPS_EXIT_ASSERT = 1 +DSI_LANE_ULPS_EXIT = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_LANE_FORCE_TX_STOP' +DSI_LANE_FORCE_TX_STOP__enumvalues = { + 0: 'DSI_LANE_FORCE_TX_STOP_DEASSERT', + 1: 'DSI_LANE_FORCE_TX_STOP_ASSERT', +} +DSI_LANE_FORCE_TX_STOP_DEASSERT = 0 +DSI_LANE_FORCE_TX_STOP_ASSERT = 1 +DSI_LANE_FORCE_TX_STOP = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CLOCK_LANE_HS_FORCE_REQUEST' +DSI_CLOCK_LANE_HS_FORCE_REQUEST__enumvalues = { + 0: 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT', + 1: 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT', +} +DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT = 0 +DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT = 1 +DSI_CLOCK_LANE_HS_FORCE_REQUEST = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CONTROLLER_EN' +DSI_CONTROLLER_EN__enumvalues = { + 0: 'DSI_CONTROLLER_DISABLE', + 1: 'DSI_CONTROLLER_ENABLE', +} +DSI_CONTROLLER_DISABLE = 0 +DSI_CONTROLLER_ENABLE = 1 +DSI_CONTROLLER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_MODE_EN' +DSI_VIDEO_MODE_EN__enumvalues = { + 0: 'DSI_VIDEO_MODE_DISABLE', + 1: 'DSI_VIDEO_MODE_ENABLE', +} +DSI_VIDEO_MODE_DISABLE = 0 +DSI_VIDEO_MODE_ENABLE = 1 +DSI_VIDEO_MODE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CMD_MODE_EN' +DSI_CMD_MODE_EN__enumvalues = { + 0: 'DSI_CMD_MODE_DISABLE', + 1: 'DSI_CMD_MODE_ENABLE', +} +DSI_CMD_MODE_DISABLE = 0 +DSI_CMD_MODE_ENABLE = 1 +DSI_CMD_MODE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DATA_LANE0_EN' +DSI_DATA_LANE0_EN__enumvalues = { + 0: 'DSI_DATA_LANE0_DISABLE', + 1: 'DSI_DATA_LANE0_ENABLE', +} +DSI_DATA_LANE0_DISABLE = 0 +DSI_DATA_LANE0_ENABLE = 1 +DSI_DATA_LANE0_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DATA_LANE1_EN' +DSI_DATA_LANE1_EN__enumvalues = { + 0: 'DSI_DATA_LANE1_DISABLE', + 1: 'DSI_DATA_LANE1_ENABLE', +} +DSI_DATA_LANE1_DISABLE = 0 +DSI_DATA_LANE1_ENABLE = 1 +DSI_DATA_LANE1_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DATA_LANE2_EN' +DSI_DATA_LANE2_EN__enumvalues = { + 0: 'DSI_DATA_LANE2_DISABLE', + 1: 'DSI_DATA_LANE2_ENABLE', +} +DSI_DATA_LANE2_DISABLE = 0 +DSI_DATA_LANE2_ENABLE = 1 +DSI_DATA_LANE2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DATA_LANE3_EN' +DSI_DATA_LANE3_EN__enumvalues = { + 0: 'DSI_DATA_LANE3_DISABLE', + 1: 'DSI_DATA_LANE3_ENABLE', +} +DSI_DATA_LANE3_DISABLE = 0 +DSI_DATA_LANE3_ENABLE = 1 +DSI_DATA_LANE3_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CLOCK_LANE_EN' +DSI_CLOCK_LANE_EN__enumvalues = { + 0: 'DSI_CLOCK_LANE_DISABLE', + 1: 'DSI_CLOCK_LANE_ENABLE', +} +DSI_CLOCK_LANE_DISABLE = 0 +DSI_CLOCK_LANE_ENABLE = 1 +DSI_CLOCK_LANE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_PHY_DATA_LANE0_EN' +DSI_PHY_DATA_LANE0_EN__enumvalues = { + 0: 'DSI_PHY_DATA_LANE0_DISABLE', + 1: 'DSI_PHY_DATA_LANE0_ENABLE', +} +DSI_PHY_DATA_LANE0_DISABLE = 0 +DSI_PHY_DATA_LANE0_ENABLE = 1 +DSI_PHY_DATA_LANE0_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_PHY_DATA_LANE1_EN' +DSI_PHY_DATA_LANE1_EN__enumvalues = { + 0: 'DSI_PHY_DATA_LANE1_DISABLE', + 1: 'DSI_PHY_DATA_LANE1_ENABLE', +} +DSI_PHY_DATA_LANE1_DISABLE = 0 +DSI_PHY_DATA_LANE1_ENABLE = 1 +DSI_PHY_DATA_LANE1_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_PHY_DATA_LANE2_EN' +DSI_PHY_DATA_LANE2_EN__enumvalues = { + 0: 'DSI_PHY_DATA_LANE2_DISABLE', + 1: 'DSI_PHY_DATA_LANE2_ENABLE', +} +DSI_PHY_DATA_LANE2_DISABLE = 0 +DSI_PHY_DATA_LANE2_ENABLE = 1 +DSI_PHY_DATA_LANE2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_PHY_DATA_LANE3_EN' +DSI_PHY_DATA_LANE3_EN__enumvalues = { + 0: 'DSI_PHY_DATA_LANE3_DISABLE', + 1: 'DSI_PHY_DATA_LANE3_ENABLE', +} +DSI_PHY_DATA_LANE3_DISABLE = 0 +DSI_PHY_DATA_LANE3_ENABLE = 1 +DSI_PHY_DATA_LANE3_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RESET_DISPCLK' +DSI_RESET_DISPCLK__enumvalues = { + 0: 'DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC', + 1: 'DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC', +} +DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC = 0 +DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC = 1 +DSI_RESET_DISPCLK = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RESET_DSICLK' +DSI_RESET_DSICLK__enumvalues = { + 0: 'DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC', + 1: 'DSI_RESET_ON_DSICLK_DOMAIN_LOGIC', +} +DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC = 0 +DSI_RESET_ON_DSICLK_DOMAIN_LOGIC = 1 +DSI_RESET_DSICLK = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RESET_BYTECLK' +DSI_RESET_BYTECLK__enumvalues = { + 0: 'DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC', + 1: 'DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC', +} +DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC = 0 +DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC = 1 +DSI_RESET_BYTECLK = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RESET_ESCCLK' +DSI_RESET_ESCCLK__enumvalues = { + 0: 'DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC', + 1: 'DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC', +} +DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC = 0 +DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC = 1 +DSI_RESET_ESCCLK = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CRTC_SEL' +DSI_CRTC_SEL__enumvalues = { + 0: 'DSI_GET_PIXEL_STREAM_FROM_FMT0', + 1: 'DSI_GET_PIXEL_STREAM_FROM_FMT1', + 2: 'DSI_GET_PIXEL_STREAM_FROM_FMT2', + 3: 'DSI_GET_PIXEL_STREAM_FROM_FMT3', + 4: 'DSI_GET_PIXEL_STREAM_FROM_FMT4', + 5: 'DSI_GET_PIXEL_STREAM_FROM_FMT5', +} +DSI_GET_PIXEL_STREAM_FROM_FMT0 = 0 +DSI_GET_PIXEL_STREAM_FROM_FMT1 = 1 +DSI_GET_PIXEL_STREAM_FROM_FMT2 = 2 +DSI_GET_PIXEL_STREAM_FROM_FMT3 = 3 +DSI_GET_PIXEL_STREAM_FROM_FMT4 = 4 +DSI_GET_PIXEL_STREAM_FROM_FMT5 = 5 +DSI_CRTC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_PACKET_BYTE_MSB_LSB_FLIP' +DSI_PACKET_BYTE_MSB_LSB_FLIP__enumvalues = { + 0: 'DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP', + 1: 'DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP', +} +DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP = 0 +DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP = 1 +DSI_PACKET_BYTE_MSB_LSB_FLIP = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_MODE_DST_FORMAT' +DSI_VIDEO_MODE_DST_FORMAT__enumvalues = { + 0: 'DSI_VIDEO_DST_FORMAT_RGB565', + 1: 'DSI_VIDEO_DST_FORMAT_RGB666_PACKED', + 2: 'DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED', + 3: 'DSI_VIDEO_DST_FORMAT_RGB888', +} +DSI_VIDEO_DST_FORMAT_RGB565 = 0 +DSI_VIDEO_DST_FORMAT_RGB666_PACKED = 1 +DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED = 2 +DSI_VIDEO_DST_FORMAT_RGB888 = 3 +DSI_VIDEO_MODE_DST_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_TRAFFIC_MODE' +DSI_VIDEO_TRAFFIC_MODE__enumvalues = { + 0: 'DSI_TRAFFIC_MODE_SYNC_PULSES', + 1: 'DSI_TRAFFIC_MODE_SYNC_EVENTS', + 2: 'DSI_TRAFFIC_MODE_BURST', + 3: 'DSI_TRAFFIC_MODE_RESERVED', +} +DSI_TRAFFIC_MODE_SYNC_PULSES = 0 +DSI_TRAFFIC_MODE_SYNC_EVENTS = 1 +DSI_TRAFFIC_MODE_BURST = 2 +DSI_TRAFFIC_MODE_RESERVED = 3 +DSI_VIDEO_TRAFFIC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_BLLP_PWR_MODE' +DSI_VIDEO_BLLP_PWR_MODE__enumvalues = { + 0: 'DSI_VIDEO_BLLP_PWR_MODE_HS', + 1: 'DSI_VIDEO_BLLP_PWR_MODE_LP', +} +DSI_VIDEO_BLLP_PWR_MODE_HS = 0 +DSI_VIDEO_BLLP_PWR_MODE_LP = 1 +DSI_VIDEO_BLLP_PWR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_EOF_BLLP_PWR_MODE' +DSI_VIDEO_EOF_BLLP_PWR_MODE__enumvalues = { + 0: 'DSI_VIDEO_EOF_BLLP_PWR_MODE_HS', + 1: 'DSI_VIDEO_EOF_BLLP_PWR_MODE_LP', +} +DSI_VIDEO_EOF_BLLP_PWR_MODE_HS = 0 +DSI_VIDEO_EOF_BLLP_PWR_MODE_LP = 1 +DSI_VIDEO_EOF_BLLP_PWR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_PWR_MODE' +DSI_VIDEO_PWR_MODE__enumvalues = { + 0: 'DSI_VIDEO_PWR_MODE_HS', + 1: 'DSI_VIDEO_PWR_MODE_LP', +} +DSI_VIDEO_PWR_MODE_HS = 0 +DSI_VIDEO_PWR_MODE_LP = 1 +DSI_VIDEO_PWR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_VIDEO_PULSE_MODE_OPT' +DSI_VIDEO_PULSE_MODE_OPT__enumvalues = { + 0: 'PULSE_MODE_OPT_NO_HSA', + 1: 'PULSE_MODE_OPT_SEND', +} +PULSE_MODE_OPT_NO_HSA = 0 +PULSE_MODE_OPT_SEND = 1 +DSI_VIDEO_PULSE_MODE_OPT = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RGB_SWAP' +DSI_RGB_SWAP__enumvalues = { + 0: 'DSI_SWAP_RGB', + 1: 'DSI_SWAP_RBG', + 2: 'DSI_SWAP_BGR', + 3: 'DSI_SWAP_BRG', + 4: 'DSI_SWAP_GRB', + 5: 'DSI_SWAP_GBR', +} +DSI_SWAP_RGB = 0 +DSI_SWAP_RBG = 1 +DSI_SWAP_BGR = 2 +DSI_SWAP_BRG = 3 +DSI_SWAP_GRB = 4 +DSI_SWAP_GBR = 5 +DSI_RGB_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CMD_PACKET_TYPE' +DSI_CMD_PACKET_TYPE__enumvalues = { + 0: 'DSI_CMD_PACKET_TYPE_SHORT', + 1: 'DSI_CMD_PACKET_TYPE_LONG', +} +DSI_CMD_PACKET_TYPE_SHORT = 0 +DSI_CMD_PACKET_TYPE_LONG = 1 +DSI_CMD_PACKET_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CMD_PWR_MODE' +DSI_CMD_PWR_MODE__enumvalues = { + 0: 'DSI_CMD_PWR_MODE_HS', + 1: 'DSI_CMD_PWR_MODE_LP', +} +DSI_CMD_PWR_MODE_HS = 0 +DSI_CMD_PWR_MODE_LP = 1 +DSI_CMD_PWR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CMD_EMBEDDED_MODE' +DSI_CMD_EMBEDDED_MODE__enumvalues = { + 0: 'CMD_EMBEDDED_MODE_DISABLE', + 1: 'CMD_EMBEDDED_MODE_ENABLE', +} +CMD_EMBEDDED_MODE_DISABLE = 0 +CMD_EMBEDDED_MODE_ENABLE = 1 +DSI_CMD_EMBEDDED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CMD_ORDER' +DSI_CMD_ORDER__enumvalues = { + 0: 'DSI_CMD_ORDER_COMMAND_FIRST', + 1: 'DSI_CMD_ORDER_DATA_FIRST', +} +DSI_CMD_ORDER_COMMAND_FIRST = 0 +DSI_CMD_ORDER_DATA_FIRST = 1 +DSI_CMD_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DATA_BUFFER_ID' +DSI_DATA_BUFFER_ID__enumvalues = { + 0: 'DSI_DATA_BUFFER_OFFSET0', + 1: 'DSI_DATA_BUFFER_OFFSET1', +} +DSI_DATA_BUFFER_OFFSET0 = 0 +DSI_DATA_BUFFER_OFFSET1 = 1 +DSI_DATA_BUFFER_ID = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DWORD_BYTE_SWAP' +DSI_DWORD_BYTE_SWAP__enumvalues = { + 0: 'DWORD_BYTE_SWAP_NO_SWAP', + 1: 'DWORD_BYTE_SWAP_BYTE_SWAP', + 2: 'DWORD_BYTE_SWAP_WORD_SWAP', + 3: 'DWORD_BYTE_SWAP_BOTH_SWAP', +} +DWORD_BYTE_SWAP_NO_SWAP = 0 +DWORD_BYTE_SWAP_BYTE_SWAP = 1 +DWORD_BYTE_SWAP_WORD_SWAP = 2 +DWORD_BYTE_SWAP_BOTH_SWAP = 3 +DSI_DWORD_BYTE_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_INSERT_DCS_COMMAND' +DSI_INSERT_DCS_COMMAND__enumvalues = { + 0: 'DSI_INSERT_DCS_COMMAND_DISABLE', + 1: 'DSI_INSERT_DCS_COMMAND_ENABLE', +} +DSI_INSERT_DCS_COMMAND_DISABLE = 0 +DSI_INSERT_DCS_COMMAND_ENABLE = 1 +DSI_INSERT_DCS_COMMAND = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DMAFIFO_WRITE_WATERMARK' +DSI_DMAFIFO_WRITE_WATERMARK__enumvalues = { + 0: 'DSI_DMAFIFO_WRITE_WATERMARK_HALF', + 1: 'DSI_DMAFIFO_WRITE_WATERMARK_FOURTH', + 2: 'DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH', + 3: 'DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH', +} +DSI_DMAFIFO_WRITE_WATERMARK_HALF = 0 +DSI_DMAFIFO_WRITE_WATERMARK_FOURTH = 1 +DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH = 2 +DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH = 3 +DSI_DMAFIFO_WRITE_WATERMARK = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DMAFIFO_READ_WATERMARK' +DSI_DMAFIFO_READ_WATERMARK__enumvalues = { + 0: 'DSI_DMAFIFO_READ_WATERMARK_HALF', + 1: 'DSI_DMAFIFO_READ_WATERMARK_FOURTH', + 2: 'DSI_DMAFIFO_READ_WATERMARK_EIGHTH', + 3: 'DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH', +} +DSI_DMAFIFO_READ_WATERMARK_HALF = 0 +DSI_DMAFIFO_READ_WATERMARK_FOURTH = 1 +DSI_DMAFIFO_READ_WATERMARK_EIGHTH = 2 +DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH = 3 +DSI_DMAFIFO_READ_WATERMARK = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_USE_DENG_LENGTH' +DSI_USE_DENG_LENGTH__enumvalues = { + 0: 'DSI_USE_DENG_LENGTH_DISABLE', + 1: 'DSI_USE_DENG_LENGTH_ENABLE', +} +DSI_USE_DENG_LENGTH_DISABLE = 0 +DSI_USE_DENG_LENGTH_ENABLE = 1 +DSI_USE_DENG_LENGTH = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_COMMAND_TRIGGER_MODE' +DSI_COMMAND_TRIGGER_MODE__enumvalues = { + 0: 'DSI_COMMAND_TRIGGER_MODE_AUTO', + 1: 'DSI_COMMAND_TRIGGER_MODE_MANUAL', +} +DSI_COMMAND_TRIGGER_MODE_AUTO = 0 +DSI_COMMAND_TRIGGER_MODE_MANUAL = 1 +DSI_COMMAND_TRIGGER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_COMMAND_TRIGGER_SEL' +DSI_COMMAND_TRIGGER_SEL__enumvalues = { + 0: 'DSI_COMMAND_TRIGGER_SEL_NONE', + 1: 'DSI_COMMAND_TRIGGER_SEL_CRTC', + 2: 'DSI_COMMAND_TRIGGER_SEL_TE', + 3: 'DSI_COMMAND_TRIGGER_SEL_HW', +} +DSI_COMMAND_TRIGGER_SEL_NONE = 0 +DSI_COMMAND_TRIGGER_SEL_CRTC = 1 +DSI_COMMAND_TRIGGER_SEL_TE = 2 +DSI_COMMAND_TRIGGER_SEL_HW = 3 +DSI_COMMAND_TRIGGER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_HW_SOURCE_SEL' +DSI_HW_SOURCE_SEL__enumvalues = { + 0: 'HW_SOURCE_SEL_NONE', + 1: 'HW_SOURCE_SEL_DSC_VUP', + 2: 'HW_SOURCE_SEL_DSC_VLP', + 3: 'HW_SOURCE_SEL_DSC_JPEG', +} +HW_SOURCE_SEL_NONE = 0 +HW_SOURCE_SEL_DSC_VUP = 1 +HW_SOURCE_SEL_DSC_VLP = 2 +HW_SOURCE_SEL_DSC_JPEG = 3 +DSI_HW_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_COMMAND_TRIGGER_ORDER' +DSI_COMMAND_TRIGGER_ORDER__enumvalues = { + 0: 'DSI_COMMAND_TRIGGER_ORDER_DMA', + 1: 'DSI_COMMAND_TRIGGER_ORDER_DENG', +} +DSI_COMMAND_TRIGGER_ORDER_DMA = 0 +DSI_COMMAND_TRIGGER_ORDER_DENG = 1 +DSI_COMMAND_TRIGGER_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_TE_SRC_SEL' +DSI_TE_SRC_SEL__enumvalues = { + 0: 'DSI_TE_SEL_LINK', + 1: 'DSI_TE_SEL_PIN', +} +DSI_TE_SEL_LINK = 0 +DSI_TE_SEL_PIN = 1 +DSI_TE_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_EXT_TE_MUX' +DSI_EXT_TE_MUX__enumvalues = { + 0: 'DSI_XT_TE_MUX_LCDD17', + 1: 'DSI_XT_TE_MUX_DCLK', + 2: 'DSI_XT_TE_MUX_SS', + 3: 'DSI_XT_TE_MUX_GCLK', + 4: 'DSI_XT_TE_MUX_GOE', + 5: 'DSI_XT_TE_MUX_DINV', + 6: 'DSI_XT_TE_MUX_FRAME', + 7: 'DSI_XT_TE_MUX_GPIO4', + 8: 'DSI_XT_TE_MUX_GPIO5', +} +DSI_XT_TE_MUX_LCDD17 = 0 +DSI_XT_TE_MUX_DCLK = 1 +DSI_XT_TE_MUX_SS = 2 +DSI_XT_TE_MUX_GCLK = 3 +DSI_XT_TE_MUX_GOE = 4 +DSI_XT_TE_MUX_DINV = 5 +DSI_XT_TE_MUX_FRAME = 6 +DSI_XT_TE_MUX_GPIO4 = 7 +DSI_XT_TE_MUX_GPIO5 = 8 +DSI_EXT_TE_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_EXT_TE_MODE' +DSI_EXT_TE_MODE__enumvalues = { + 0: 'DSI_EXT_TE_MODE_VSYNC_EDGE', + 1: 'DSI_EXT_TE_MODE_VSYNC_WIDTH', + 2: 'DSI_EXT_TE_MODE_HVSYNC_EDGE', + 3: 'DSI_EXT_TE_MODE_HVSYNC_WIDTH', +} +DSI_EXT_TE_MODE_VSYNC_EDGE = 0 +DSI_EXT_TE_MODE_VSYNC_WIDTH = 1 +DSI_EXT_TE_MODE_HVSYNC_EDGE = 2 +DSI_EXT_TE_MODE_HVSYNC_WIDTH = 3 +DSI_EXT_TE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_EXT_RESET_POL' +DSI_EXT_RESET_POL__enumvalues = { + 0: 'DSI_EXT_RESET_POL_HIGH', + 1: 'DSI_EXT_RESET_POL_LOW', +} +DSI_EXT_RESET_POL_HIGH = 0 +DSI_EXT_RESET_POL_LOW = 1 +DSI_EXT_RESET_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_EXT_TE_POL' +DSI_EXT_TE_POL__enumvalues = { + 0: 'DSI_EXT_TE_POL_RISING', + 1: 'DSI_EXT_TE_POL_FALLING', +} +DSI_EXT_TE_POL_RISING = 0 +DSI_EXT_TE_POL_FALLING = 1 +DSI_EXT_TE_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RESET_PANEL' +DSI_RESET_PANEL__enumvalues = { + 0: 'DSI_RESET_PANEL_DEASSERT', + 1: 'DSI_RESET_PANEL_ASSERT', +} +DSI_RESET_PANEL_DEASSERT = 0 +DSI_RESET_PANEL_ASSERT = 1 +DSI_RESET_PANEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CRC_ENABLE' +DSI_CRC_ENABLE__enumvalues = { + 0: 'DSI_CRC_CAL_DISABLE', + 1: 'DSI_CRC_CAL_ENABLE', +} +DSI_CRC_CAL_DISABLE = 0 +DSI_CRC_CAL_ENABLE = 1 +DSI_CRC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_TX_EOT_APPEND' +DSI_TX_EOT_APPEND__enumvalues = { + 0: 'DSI_TX_EOT_APPEND_DISABLE', + 1: 'DSI_TX_EOT_APPEND_ENABLE', +} +DSI_TX_EOT_APPEND_DISABLE = 0 +DSI_TX_EOT_APPEND_ENABLE = 1 +DSI_TX_EOT_APPEND = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_RX_EOT_IGNORE' +DSI_RX_EOT_IGNORE__enumvalues = { + 0: 'DSI_RX_EOT_IGNORE_DISABLE', + 1: 'DSI_RX_EOT_IGNORE_ENABLE', +} +DSI_RX_EOT_IGNORE_DISABLE = 0 +DSI_RX_EOT_IGNORE_ENABLE = 1 +DSI_RX_EOT_IGNORE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_MIPI_BIST_RESET' +DSI_MIPI_BIST_RESET__enumvalues = { + 0: 'DSI_MIPI_BIST_RESET_DEASSERT', + 1: 'DSI_MIPI_BIST_RESET_ASSERT', +} +DSI_MIPI_BIST_RESET_DEASSERT = 0 +DSI_MIPI_BIST_RESET_ASSERT = 1 +DSI_MIPI_BIST_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_MIPI_BIST_VIDEO_FRMT' +DSI_MIPI_BIST_VIDEO_FRMT__enumvalues = { + 0: 'DSI_MIPI_BIST_VIDEO_FRMT_YUV422', + 1: 'DSI_MIPI_BIST_VIDEO_FRMT_RAW8', +} +DSI_MIPI_BIST_VIDEO_FRMT_YUV422 = 0 +DSI_MIPI_BIST_VIDEO_FRMT_RAW8 = 1 +DSI_MIPI_BIST_VIDEO_FRMT = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_MIPI_BIST_START' +DSI_MIPI_BIST_START__enumvalues = { + 0: 'DSI_MIPI_BIST_START_DEASSERT', + 1: 'DSI_MIPI_BIST_START_ASSERT', +} +DSI_MIPI_BIST_START_DEASSERT = 0 +DSI_MIPI_BIST_START_ASSERT = 1 +DSI_MIPI_BIST_START = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DBG_CLK_SEL' +DSI_DBG_CLK_SEL__enumvalues = { + 0: 'DSI_TEST_CLK_SEL_DISPCLK_P', + 1: 'DSI_TEST_CLK_SEL_DISPCLK_G', + 2: 'DSI_TEST_CLK_SEL_DISPCLK_R', + 3: 'DSI_TEST_CLK_SEL_ESCCLK_G', + 4: 'DSI_TEST_CLK_SEL_BYTECLK_G', + 5: 'DSI_TEST_CLK_SEL_DSICLK_P', + 6: 'DSI_TEST_CLK_SEL_DSICLK_R', + 7: 'DSI_TEST_CLK_SEL_DSICLK_G', + 8: 'DSI_TEST_CLK_SEL_DSICLK_TRN', +} +DSI_TEST_CLK_SEL_DISPCLK_P = 0 +DSI_TEST_CLK_SEL_DISPCLK_G = 1 +DSI_TEST_CLK_SEL_DISPCLK_R = 2 +DSI_TEST_CLK_SEL_ESCCLK_G = 3 +DSI_TEST_CLK_SEL_BYTECLK_G = 4 +DSI_TEST_CLK_SEL_DSICLK_P = 5 +DSI_TEST_CLK_SEL_DSICLK_R = 6 +DSI_TEST_CLK_SEL_DSICLK_G = 7 +DSI_TEST_CLK_SEL_DSICLK_TRN = 8 +DSI_DBG_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DENG_FIFO_USE_OVERWRITE_LEVEL' +DSI_DENG_FIFO_USE_OVERWRITE_LEVEL__enumvalues = { + 0: 'DSI_DENG_FIFO_LEVEL_OVERWRITE', + 1: 'DSI_DENG_FIFO_LEVEL_CAL_AVERAGE', +} +DSI_DENG_FIFO_LEVEL_OVERWRITE = 0 +DSI_DENG_FIFO_LEVEL_CAL_AVERAGE = 1 +DSI_DENG_FIFO_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE' +DSI_DENG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = { + 0: 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT', + 1: 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT', +} +DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT = 0 +DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT = 1 +DSI_DENG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX' +DSI_DENG_FIFO_FORCE_RECOMP_MINMAX__enumvalues = { + 0: 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT', + 1: 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT', +} +DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT = 0 +DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT = 1 +DSI_DENG_FIFO_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DENG_FIFO_START' +DSI_DENG_FIFO_START__enumvalues = { + 0: 'DSI_DENG_FIFO_START_DEASSERT', + 1: 'DSI_DENG_FIFO_START_ASSERT', +} +DSI_DENG_FIFO_START_DEASSERT = 0 +DSI_DENG_FIFO_START_ASSERT = 1 +DSI_DENG_FIFO_START = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_USE_CMDFIFO' +DSI_USE_CMDFIFO__enumvalues = { + 0: 'DSI_CMD_USE_DMAFIFO', + 1: 'DSI_CMD_USE_CMDFIFO', +} +DSI_CMD_USE_DMAFIFO = 0 +DSI_CMD_USE_CMDFIFO = 1 +DSI_USE_CMDFIFO = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_CRTC_FREEZE_TRIG' +DSI_CRTC_FREEZE_TRIG__enumvalues = { + 0: 'DSI_CRTC_FREEZE_TRIG_DEASSERT', + 1: 'DSI_CRTC_FREEZE_TRIG_ASSERT', +} +DSI_CRTC_FREEZE_TRIG_DEASSERT = 0 +DSI_CRTC_FREEZE_TRIG_ASSERT = 1 +DSI_CRTC_FREEZE_TRIG = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_PERF_LATENCY_SEL' +DSI_PERF_LATENCY_SEL__enumvalues = { + 0: 'DSI_PERF_LATENCY_SEL_DATA_LANE0', + 1: 'DSI_PERF_LATENCY_SEL_DATA_LANE1', + 2: 'DSI_PERF_LATENCY_SEL_DATA_LANE2', + 3: 'DSI_PERF_LATENCY_SEL_DATA_LANE3', +} +DSI_PERF_LATENCY_SEL_DATA_LANE0 = 0 +DSI_PERF_LATENCY_SEL_DATA_LANE1 = 1 +DSI_PERF_LATENCY_SEL_DATA_LANE2 = 2 +DSI_PERF_LATENCY_SEL_DATA_LANE3 = 3 +DSI_PERF_LATENCY_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DEBUG_DSICLK_SEL' +DSI_DEBUG_DSICLK_SEL__enumvalues = { + 0: 'DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE', + 1: 'DSI_DEBUG_DSICLK_SEL_CMD_ENGINE', + 2: 'DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO', + 3: 'DSI_DEBUG_DSICLK_SEL_CMDFIFO', + 4: 'DSI_DEBUG_DSICLK_SEL_CMDBUFFER', + 5: 'DSI_DEBUG_DSICLK_SEL_AFIFO', + 6: 'DSI_DEBUG_DSICLK_SEL_LANECTRL', +} +DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE = 0 +DSI_DEBUG_DSICLK_SEL_CMD_ENGINE = 1 +DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO = 2 +DSI_DEBUG_DSICLK_SEL_CMDFIFO = 3 +DSI_DEBUG_DSICLK_SEL_CMDBUFFER = 4 +DSI_DEBUG_DSICLK_SEL_AFIFO = 5 +DSI_DEBUG_DSICLK_SEL_LANECTRL = 6 +DSI_DEBUG_DSICLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSI_DEBUG_BYTECLK_SEL' +DSI_DEBUG_BYTECLK_SEL__enumvalues = { + 0: 'DSI_DEBUG_BYTECLK_SEL_AFIFO', + 1: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO0', + 2: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO1', + 3: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO2', + 4: 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO3', + 5: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF0', + 6: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF1', + 7: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF2', + 8: 'DSI_DEBUG_BYTECLK_SEL_LANEBUF3', + 9: 'DSI_DEBUG_BYTECLK_SEL_PINGPONG0', + 10: 'DSI_DEBUG_BYTECLK_SEL_PINGPONG1', + 11: 'DSI_DEBUG_BYTECLK_SEL_PINGPING2', + 12: 'DSI_DEBUG_BYTECLK_SEL_PINGPING3', + 13: 'DSI_DEBUG_BYTECLK_SEL_EOT', + 14: 'DSI_DEBUG_BYTECLK_SEL_LANECTRL', +} +DSI_DEBUG_BYTECLK_SEL_AFIFO = 0 +DSI_DEBUG_BYTECLK_SEL_LANEFIFO0 = 1 +DSI_DEBUG_BYTECLK_SEL_LANEFIFO1 = 2 +DSI_DEBUG_BYTECLK_SEL_LANEFIFO2 = 3 +DSI_DEBUG_BYTECLK_SEL_LANEFIFO3 = 4 +DSI_DEBUG_BYTECLK_SEL_LANEBUF0 = 5 +DSI_DEBUG_BYTECLK_SEL_LANEBUF1 = 6 +DSI_DEBUG_BYTECLK_SEL_LANEBUF2 = 7 +DSI_DEBUG_BYTECLK_SEL_LANEBUF3 = 8 +DSI_DEBUG_BYTECLK_SEL_PINGPONG0 = 9 +DSI_DEBUG_BYTECLK_SEL_PINGPONG1 = 10 +DSI_DEBUG_BYTECLK_SEL_PINGPING2 = 11 +DSI_DEBUG_BYTECLK_SEL_PINGPING3 = 12 +DSI_DEBUG_BYTECLK_SEL_EOT = 13 +DSI_DEBUG_BYTECLK_SEL_LANECTRL = 14 +DSI_DEBUG_BYTECLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_HPD_SEL' +DCIOCHIP_HPD_SEL__enumvalues = { + 0: 'DCIOCHIP_HPD_SEL_ASYNC', + 1: 'DCIOCHIP_HPD_SEL_CLOCKED', +} +DCIOCHIP_HPD_SEL_ASYNC = 0 +DCIOCHIP_HPD_SEL_CLOCKED = 1 +DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PAD_MODE' +DCIOCHIP_PAD_MODE__enumvalues = { + 0: 'DCIOCHIP_PAD_MODE_DDC', + 1: 'DCIOCHIP_PAD_MODE_DP', +} +DCIOCHIP_PAD_MODE_DDC = 0 +DCIOCHIP_PAD_MODE_DP = 1 +DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUXSLAVE_PAD_MODE' +DCIOCHIP_AUXSLAVE_PAD_MODE__enumvalues = { + 0: 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', + 1: 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX', +} +DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0 +DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 1 +DCIOCHIP_AUXSLAVE_PAD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_INVERT' +DCIOCHIP_INVERT__enumvalues = { + 0: 'DCIOCHIP_POL_NON_INVERT', + 1: 'DCIOCHIP_POL_INVERT', +} +DCIOCHIP_POL_NON_INVERT = 0 +DCIOCHIP_POL_INVERT = 1 +DCIOCHIP_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PD_EN' +DCIOCHIP_PD_EN__enumvalues = { + 0: 'DCIOCHIP_PD_EN_NOTALLOW', + 1: 'DCIOCHIP_PD_EN_ALLOW', +} +DCIOCHIP_PD_EN_NOTALLOW = 0 +DCIOCHIP_PD_EN_ALLOW = 1 +DCIOCHIP_PD_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_MASK_EN' +DCIOCHIP_GPIO_MASK_EN__enumvalues = { + 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', +} +DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 +DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 +DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK' +DCIOCHIP_MASK__enumvalues = { + 0: 'DCIOCHIP_MASK_DISABLE', + 1: 'DCIOCHIP_MASK_ENABLE', +} +DCIOCHIP_MASK_DISABLE = 0 +DCIOCHIP_MASK_ENABLE = 1 +DCIOCHIP_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_I2C_MASK' +DCIOCHIP_GPIO_I2C_MASK__enumvalues = { + 0: 'DCIOCHIP_GPIO_I2C_MASK_DISABLE', + 1: 'DCIOCHIP_GPIO_I2C_MASK_ENABLE', +} +DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0 +DCIOCHIP_GPIO_I2C_MASK_ENABLE = 1 +DCIOCHIP_GPIO_I2C_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_I2C_DRIVE' +DCIOCHIP_GPIO_I2C_DRIVE__enumvalues = { + 0: 'DCIOCHIP_GPIO_I2C_DRIVE_LOW', + 1: 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', +} +DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0 +DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 1 +DCIOCHIP_GPIO_I2C_DRIVE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_I2C_EN' +DCIOCHIP_GPIO_I2C_EN__enumvalues = { + 0: 'DCIOCHIP_GPIO_I2C_DISABLE', + 1: 'DCIOCHIP_GPIO_I2C_ENABLE', +} +DCIOCHIP_GPIO_I2C_DISABLE = 0 +DCIOCHIP_GPIO_I2C_ENABLE = 1 +DCIOCHIP_GPIO_I2C_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK_4BIT' +DCIOCHIP_MASK_4BIT__enumvalues = { + 0: 'DCIOCHIP_MASK_4BIT_DISABLE', + 15: 'DCIOCHIP_MASK_4BIT_ENABLE', +} +DCIOCHIP_MASK_4BIT_DISABLE = 0 +DCIOCHIP_MASK_4BIT_ENABLE = 15 +DCIOCHIP_MASK_4BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_ENABLE_4BIT' +DCIOCHIP_ENABLE_4BIT__enumvalues = { + 0: 'DCIOCHIP_4BIT_DISABLE', + 15: 'DCIOCHIP_4BIT_ENABLE', +} +DCIOCHIP_4BIT_DISABLE = 0 +DCIOCHIP_4BIT_ENABLE = 15 +DCIOCHIP_ENABLE_4BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK_5BIT' +DCIOCHIP_MASK_5BIT__enumvalues = { + 0: 'DCIOCHIP_MASIK_5BIT_DISABLE', + 31: 'DCIOCHIP_MASIK_5BIT_ENABLE', +} +DCIOCHIP_MASIK_5BIT_DISABLE = 0 +DCIOCHIP_MASIK_5BIT_ENABLE = 31 +DCIOCHIP_MASK_5BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_ENABLE_5BIT' +DCIOCHIP_ENABLE_5BIT__enumvalues = { + 0: 'DCIOCHIP_5BIT_DISABLE', + 31: 'DCIOCHIP_5BIT_ENABLE', +} +DCIOCHIP_5BIT_DISABLE = 0 +DCIOCHIP_5BIT_ENABLE = 31 +DCIOCHIP_ENABLE_5BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK_2BIT' +DCIOCHIP_MASK_2BIT__enumvalues = { + 0: 'DCIOCHIP_MASK_2BIT_DISABLE', + 3: 'DCIOCHIP_MASK_2BIT_ENABLE', +} +DCIOCHIP_MASK_2BIT_DISABLE = 0 +DCIOCHIP_MASK_2BIT_ENABLE = 3 +DCIOCHIP_MASK_2BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_ENABLE_2BIT' +DCIOCHIP_ENABLE_2BIT__enumvalues = { + 0: 'DCIOCHIP_2BIT_DISABLE', + 3: 'DCIOCHIP_2BIT_ENABLE', +} +DCIOCHIP_2BIT_DISABLE = 0 +DCIOCHIP_2BIT_ENABLE = 3 +DCIOCHIP_ENABLE_2BIT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' +DCIOCHIP_REF_27_SRC_SEL__enumvalues = { + 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', + 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', +} +DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 +DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 +DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_DVO_VREFPON' +DCIOCHIP_DVO_VREFPON__enumvalues = { + 0: 'DCIOCHIP_DVO_VREFPON_DISABLE', + 1: 'DCIOCHIP_DVO_VREFPON_ENABLE', +} +DCIOCHIP_DVO_VREFPON_DISABLE = 0 +DCIOCHIP_DVO_VREFPON_ENABLE = 1 +DCIOCHIP_DVO_VREFPON = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_DVO_VREFSEL' +DCIOCHIP_DVO_VREFSEL__enumvalues = { + 0: 'DCIOCHIP_DVO_VREFSEL_ONCHIP', + 1: 'DCIOCHIP_DVO_VREFSEL_EXTERNAL', +} +DCIOCHIP_DVO_VREFSEL_ONCHIP = 0 +DCIOCHIP_DVO_VREFSEL_EXTERNAL = 1 +DCIOCHIP_DVO_VREFSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_SPDIF1_IMODE' +DCIOCHIP_SPDIF1_IMODE__enumvalues = { + 0: 'DCIOCHIP_SPDIF1_IMODE_OE_A', + 1: 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO', +} +DCIOCHIP_SPDIF1_IMODE_OE_A = 0 +DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 1 +DCIOCHIP_SPDIF1_IMODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' +DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { + 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', + 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', +} +DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 +DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 +DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_SPIKESEL' +DCIOCHIP_AUX_SPIKESEL__enumvalues = { + 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', + 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', +} +DCIOCHIP_AUX_SPIKESEL_50NS = 0 +DCIOCHIP_AUX_SPIKESEL_10NS = 1 +DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL0P9' +DCIOCHIP_AUX_CSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', +} +DCIOCHIP_AUX_CSEL_DEC1P0 = 0 +DCIOCHIP_AUX_CSEL_DEC0P9 = 1 +DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL1P1' +DCIOCHIP_AUX_CSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_INC1P0', + 1: 'DCIOCHIP_AUX_CSEL_INC1P1', +} +DCIOCHIP_AUX_CSEL_INC1P0 = 0 +DCIOCHIP_AUX_CSEL_INC1P1 = 1 +DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL0P9' +DCIOCHIP_AUX_RSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', +} +DCIOCHIP_AUX_RSEL_DEC1P0 = 0 +DCIOCHIP_AUX_RSEL_DEC0P9 = 1 +DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL1P1' +DCIOCHIP_AUX_RSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_INC1P0', + 1: 'DCIOCHIP_AUX_RSEL_INC1P1', +} +DCIOCHIP_AUX_RSEL_INC1P0 = 0 +DCIOCHIP_AUX_RSEL_INC1P1 = 1 +DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_GLOBAL_CAPABILITIES' +AZ_GLOBAL_CAPABILITIES__enumvalues = { + 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', +} +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 +AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { + 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', + 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', +} +ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 +ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' +GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { + 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', + 1: 'FLUSH_CONTROL_FLUSH_STARTED', +} +FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 +FLUSH_CONTROL_FLUSH_STARTED = 1 +GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' +GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { + 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', +} +CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 +CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 +GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_STATE_CHANGE_STATUS' +AZ_STATE_CHANGE_STATUS__enumvalues = { + 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', +} +AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 +AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 +AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' +GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { + 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', +} +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 +GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_0_SYNCHRONIZATION' +STREAM_0_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_1_SYNCHRONIZATION' +STREAM_1_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_2_SYNCHRONIZATION' +STREAM_2_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_3_SYNCHRONIZATION' +STREAM_3_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_4_SYNCHRONIZATION' +STREAM_4_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_5_SYNCHRONIZATION' +STREAM_5_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_6_SYNCHRONIZATION' +STREAM_6_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_7_SYNCHRONIZATION' +STREAM_7_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_8_SYNCHRONIZATION' +STREAM_8_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_9_SYNCHRONIZATION' +STREAM_9_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_10_SYNCHRONIZATION' +STREAM_10_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_11_SYNCHRONIZATION' +STREAM_11_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_12_SYNCHRONIZATION' +STREAM_12_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_13_SYNCHRONIZATION' +STREAM_13_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_14_SYNCHRONIZATION' +STREAM_14_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_15_SYNCHRONIZATION' +STREAM_15_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'CORB_READ_POINTER_RESET' +CORB_READ_POINTER_RESET__enumvalues = { + 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', +} +CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 +CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 +CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_CORB_SIZE' +AZ_CORB_SIZE__enumvalues = { + 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_CORB_SIZE_256ENTRIES', + 3: 'AZ_CORB_SIZE_RESERVED', +} +AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 +AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 +AZ_CORB_SIZE_256ENTRIES = 2 +AZ_CORB_SIZE_RESERVED = 3 +AZ_CORB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' +AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { + 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', + 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', +} +AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 +AZ_RIRB_WRITE_POINTER_DO_RESET = 1 +AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_SIZE' +AZ_RIRB_SIZE__enumvalues = { + 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_RIRB_SIZE_256ENTRIES', + 3: 'AZ_RIRB_SIZE_UNDEFINED', +} +AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 +AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 +AZ_RIRB_SIZE_256ENTRIES = 2 +AZ_RIRB_SIZE_UNDEFINED = 3 +AZ_RIRB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum + +# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { + 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', +} +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { + 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', +} +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { + 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', +} +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE' +ENABLE__enumvalues = { + 0: 'DISABLE_THE_FEATURE', + 1: 'ENABLE_THE_FEATURE', +} +DISABLE_THE_FEATURE = 0 +ENABLE_THE_FEATURE = 1 +ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE_CLOCK' +ENABLE_CLOCK__enumvalues = { + 0: 'DISABLE_THE_CLOCK', + 1: 'ENABLE_THE_CLOCK', +} +DISABLE_THE_CLOCK = 0 +ENABLE_THE_CLOCK = 1 +ENABLE_CLOCK = ctypes.c_uint32 # enum + +# values for enumeration 'FORCE_VBI' +FORCE_VBI__enumvalues = { + 0: 'FORCE_VBI_LOW', + 1: 'FORCE_VBI_HIGH', +} +FORCE_VBI_LOW = 0 +FORCE_VBI_HIGH = 1 +FORCE_VBI = ctypes.c_uint32 # enum + +# values for enumeration 'OVERRIDE_CGTT_SCLK' +OVERRIDE_CGTT_SCLK__enumvalues = { + 0: 'OVERRIDE_CGTT_SCLK_NOOP', + 1: 'SET_OVERRIDE_CGTT_SCLK', +} +OVERRIDE_CGTT_SCLK_NOOP = 0 +SET_OVERRIDE_CGTT_SCLK = 1 +OVERRIDE_CGTT_SCLK = ctypes.c_uint32 # enum + +# values for enumeration 'CLEAR_SMU_INTR' +CLEAR_SMU_INTR__enumvalues = { + 0: 'SMU_INTR_STATUS_NOOP', + 1: 'SMU_INTR_STATUS_CLEAR', +} +SMU_INTR_STATUS_NOOP = 0 +SMU_INTR_STATUS_CLEAR = 1 +CLEAR_SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'STATIC_SCREEN_SMU_INTR' +STATIC_SCREEN_SMU_INTR__enumvalues = { + 0: 'STATIC_SCREEN_SMU_INTR_NOOP', + 1: 'SET_STATIC_SCREEN_SMU_INTR', +} +STATIC_SCREEN_SMU_INTR_NOOP = 0 +SET_STATIC_SCREEN_SMU_INTR = 1 +STATIC_SCREEN_SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'JITTER_REMOVE_DISABLE' +JITTER_REMOVE_DISABLE__enumvalues = { + 0: 'ENABLE_JITTER_REMOVAL', + 1: 'DISABLE_JITTER_REMOVAL', +} +ENABLE_JITTER_REMOVAL = 0 +DISABLE_JITTER_REMOVAL = 1 +JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DS_REF_SRC' +DS_REF_SRC__enumvalues = { + 0: 'DS_REF_IS_XTALIN', + 1: 'DS_REF_IS_EXT_GENLOCK', + 2: 'DS_REF_IS_PCIE', +} +DS_REF_IS_XTALIN = 0 +DS_REF_IS_EXT_GENLOCK = 1 +DS_REF_IS_PCIE = 2 +DS_REF_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING' +DISABLE_CLOCK_GATING__enumvalues = { + 0: 'CLOCK_GATING_ENABLED', + 1: 'CLOCK_GATING_DISABLED', +} +CLOCK_GATING_ENABLED = 0 +CLOCK_GATING_DISABLED = 1 +DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' +DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { + 0: 'CLOCK_GATING_ENABLED_IN_DCO', + 1: 'CLOCK_GATING_DISABLED_IN_DCO', +} +CLOCK_GATING_ENABLED_IN_DCO = 0 +CLOCK_GATING_DISABLED_IN_DCO = 1 +DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DEEP_COLOR_CNTL' +DCCG_DEEP_COLOR_CNTL__enumvalues = { + 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', + 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', + 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', +} +DCCG_DEEP_COLOR_DTO_DISABLE = 0 +DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 +DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 +DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 +DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'REFCLK_CLOCK_EN' +REFCLK_CLOCK_EN__enumvalues = { + 0: 'REFCLK_CLOCK_EN_XTALIN_CLK', + 1: 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', +} +REFCLK_CLOCK_EN_XTALIN_CLK = 0 +REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 1 +REFCLK_CLOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'REFCLK_SRC_SEL' +REFCLK_SRC_SEL__enumvalues = { + 0: 'REFCLK_SRC_SEL_PCIE_REFCLK', + 1: 'REFCLK_SRC_SEL_CPL_REFCLK', +} +REFCLK_SRC_SEL_PCIE_REFCLK = 0 +REFCLK_SRC_SEL_CPL_REFCLK = 1 +REFCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPREFCLK_SRC_SEL' +DPREFCLK_SRC_SEL__enumvalues = { + 0: 'DPREFCLK_SRC_SEL_CK', + 1: 'DPREFCLK_SRC_SEL_P0PLL', + 2: 'DPREFCLK_SRC_SEL_P1PLL', + 3: 'DPREFCLK_SRC_SEL_P2PLL', + 4: 'DPREFCLK_SRC_SEL_P3PLL', +} +DPREFCLK_SRC_SEL_CK = 0 +DPREFCLK_SRC_SEL_P0PLL = 1 +DPREFCLK_SRC_SEL_P1PLL = 2 +DPREFCLK_SRC_SEL_P2PLL = 3 +DPREFCLK_SRC_SEL_P3PLL = 4 +DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_SEL' +XTAL_REF_SEL__enumvalues = { + 0: 'XTAL_REF_SEL_1X', + 1: 'XTAL_REF_SEL_2X', +} +XTAL_REF_SEL_1X = 0 +XTAL_REF_SEL_2X = 1 +XTAL_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' +XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', + 1: 'XTAL_REF_CLOCK_SOURCE_SEL_PPLL', +} +XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 +XTAL_REF_CLOCK_SOURCE_SEL_PPLL = 1 +XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', +} +MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 1 +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ALLOW_SR_ON_TRANS_REQ' +ALLOW_SR_ON_TRANS_REQ__enumvalues = { + 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', + 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', +} +ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 +ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 +ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', +} +MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 1 +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_SOURCE' +PIPE_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', + 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', +} +PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 +PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 +PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 +PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' +PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE', + 5: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF', + 6: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG', +} +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 4 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 5 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG = 6 +PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' +PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', + 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', +} +PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 +PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 +PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DTO_DS_DISABLE' +DP_DTO_DS_DISABLE__enumvalues = { + 0: 'DP_DTO_DESPREAD_DISABLE', + 1: 'DP_DTO_DESPREAD_ENABLE', +} +DP_DTO_DESPREAD_DISABLE = 0 +DP_DTO_DESPREAD_ENABLE = 1 +DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_ADD_PIXEL' +CRTC_ADD_PIXEL__enumvalues = { + 0: 'CRTC_ADD_PIXEL_NOOP', + 1: 'CRTC_ADD_PIXEL_FORCE', +} +CRTC_ADD_PIXEL_NOOP = 0 +CRTC_ADD_PIXEL_FORCE = 1 +CRTC_ADD_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRTC_DROP_PIXEL' +CRTC_DROP_PIXEL__enumvalues = { + 0: 'CRTC_DROP_PIXEL_NOOP', + 1: 'CRTC_DROP_PIXEL_FORCE', +} +CRTC_DROP_PIXEL_NOOP = 0 +CRTC_DROP_PIXEL_FORCE = 1 +CRTC_DROP_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_FORCE_EN' +SYMCLK_FE_FORCE_EN__enumvalues = { + 0: 'SYMCLK_FE_FORCE_EN_DISABLE', + 1: 'SYMCLK_FE_FORCE_EN_ENABLE', +} +SYMCLK_FE_FORCE_EN_DISABLE = 0 +SYMCLK_FE_FORCE_EN_ENABLE = 1 +SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_FORCE_SRC' +SYMCLK_FE_FORCE_SRC__enumvalues = { + 0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA', + 1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB', + 2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC', + 3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD', + 4: 'SYMCLK_FE_FORCE_SRC_UNIPHYE', + 5: 'SYMCLK_FE_FORCE_SRC_UNIPHYF', + 6: 'SYMCLK_FE_FORCE_SRC_UNIPHYG', +} +SYMCLK_FE_FORCE_SRC_UNIPHYA = 0 +SYMCLK_FE_FORCE_SRC_UNIPHYB = 1 +SYMCLK_FE_FORCE_SRC_UNIPHYC = 2 +SYMCLK_FE_FORCE_SRC_UNIPHYD = 3 +SYMCLK_FE_FORCE_SRC_UNIPHYE = 4 +SYMCLK_FE_FORCE_SRC_UNIPHYF = 5 +SYMCLK_FE_FORCE_SRC_UNIPHYG = 6 +SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_CLK_FORCE_EN' +DPDBG_CLK_FORCE_EN__enumvalues = { + 0: 'DPDBG_CLK_FORCE_EN_DISABLE', + 1: 'DPDBG_CLK_FORCE_EN_ENABLE', +} +DPDBG_CLK_FORCE_EN_DISABLE = 0 +DPDBG_CLK_FORCE_EN_ENABLE = 1 +DPDBG_CLK_FORCE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLK_COARSE_SKEW_CNTL' +DVOACLK_COARSE_SKEW_CNTL__enumvalues = { + 0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', + 1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', + 2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', + 3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', + 4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', + 5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', + 6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', + 7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', + 8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', + 9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', + 10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', + 11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', + 12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', + 13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', + 14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', + 15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', + 16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', + 17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', + 18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', + 19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', + 20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', + 21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', + 22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', + 23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', + 24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', + 25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', + 26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', + 27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', + 28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', + 29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', + 30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', +} +DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0 +DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1 +DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2 +DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3 +DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4 +DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5 +DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6 +DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7 +DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8 +DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9 +DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10 +DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11 +DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12 +DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13 +DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14 +DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15 +DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16 +DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17 +DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18 +DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19 +DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20 +DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21 +DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22 +DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23 +DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24 +DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25 +DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26 +DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27 +DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28 +DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29 +DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30 +DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLK_FINE_SKEW_CNTL' +DVOACLK_FINE_SKEW_CNTL__enumvalues = { + 0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', + 1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', + 2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', + 3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', + 4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', + 5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', + 6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', + 7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', +} +DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0 +DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1 +DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2 +DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3 +DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4 +DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5 +DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6 +DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7 +DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKD_IN_PHASE' +DVOACLKD_IN_PHASE__enumvalues = { + 0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_IN_PHASE' +DVOACLKC_IN_PHASE__enumvalues = { + 0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_MVP_IN_PHASE' +DVOACLKC_MVP_IN_PHASE__enumvalues = { + 0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE' +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = { + 0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', + 1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', +} +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0 +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1 +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'MVP_CLK_SRC_SEL' +MVP_CLK_SRC_SEL__enumvalues = { + 0: 'MVP_CLK_SRC_SEL_RSRV', + 1: 'MVP_CLK_SRC_SEL_IO_1', + 2: 'MVP_CLK_SRC_SEL_IO_2', + 3: 'MVP_CLK_SRC_SEL_REFCLK', +} +MVP_CLK_SRC_SEL_RSRV = 0 +MVP_CLK_SRC_SEL_IO_1 = 1 +MVP_CLK_SRC_SEL_IO_2 = 2 +MVP_CLK_SRC_SEL_REFCLK = 3 +MVP_CLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' +DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0', + 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1', + 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2', + 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3', + 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4', + 5: 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5', + 6: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', +} +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0 = 0 +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1 = 1 +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2 = 2 +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3 = 3 +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4 = 4 +DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5 = 5 +DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 6 +DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_SEL' +DCCG_AUDIO_DTO_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', + 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', +} +DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 +DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 +DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 +DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' +DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', +} +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 1 +DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' +DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { + 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', +} +DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 +DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 +DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DBG_EN' +DCCG_DBG_EN__enumvalues = { + 0: 'DCCG_DBG_EN_DISABLE', + 1: 'DCCG_DBG_EN_ENABLE', +} +DCCG_DBG_EN_DISABLE = 0 +DCCG_DBG_EN_ENABLE = 1 +DCCG_DBG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DBG_BLOCK_SEL' +DCCG_DBG_BLOCK_SEL__enumvalues = { + 0: 'DCCG_DBG_BLOCK_SEL_DCCG', + 1: 'DCCG_DBG_BLOCK_SEL_PMON', + 2: 'DCCG_DBG_BLOCK_SEL_PMON2', +} +DCCG_DBG_BLOCK_SEL_DCCG = 0 +DCCG_DBG_BLOCK_SEL_PMON = 1 +DCCG_DBG_BLOCK_SEL_PMON2 = 2 +DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_FREQ_RAMP_DONE' +DISPCLK_FREQ_RAMP_DONE__enumvalues = { + 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', + 1: 'DISPCLK_FREQ_RAMP_COMPLETED', +} +DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 +DISPCLK_FREQ_RAMP_COMPLETED = 1 +DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_RESET' +DCCG_FIFO_ERRDET_RESET__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', + 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', +} +DCCG_FIFO_ERRDET_RESET_NOOP = 0 +DCCG_FIFO_ERRDET_RESET_FORCE = 1 +DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_STATE' +DCCG_FIFO_ERRDET_STATE__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_STATE_DETECTION', + 1: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', +} +DCCG_FIFO_ERRDET_STATE_DETECTION = 0 +DCCG_FIFO_ERRDET_STATE_CALIBRATION = 1 +DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' +DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', + 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', +} +DCCG_FIFO_ERRDET_OVR_DISABLE = 0 +DCCG_FIFO_ERRDET_OVR_ENABLE = 1 +DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' +DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { + 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', +} +DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 +DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 +DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' +DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { + 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', +} +DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 +DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 +DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_RUN' +DCCG_PERF_RUN__enumvalues = { + 0: 'DCCG_PERF_RUN_NOOP', + 1: 'DCCG_PERF_RUN_START', +} +DCCG_PERF_RUN_NOOP = 0 +DCCG_PERF_RUN_START = 1 +DCCG_PERF_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_VSYNC' +DCCG_PERF_MODE_VSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_VSYNC_NOOP', + 1: 'DCCG_PERF_MODE_VSYNC_START', +} +DCCG_PERF_MODE_VSYNC_NOOP = 0 +DCCG_PERF_MODE_VSYNC_START = 1 +DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_HSYNC' +DCCG_PERF_MODE_HSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_HSYNC_NOOP', + 1: 'DCCG_PERF_MODE_HSYNC_START', +} +DCCG_PERF_MODE_HSYNC_NOOP = 0 +DCCG_PERF_MODE_HSYNC_START = 1 +DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_CRTC_SELECT' +DCCG_PERF_CRTC_SELECT__enumvalues = { + 0: 'DCCG_PERF_SEL_CRTC0', + 1: 'DCCG_PERF_SEL_CRTC1', + 2: 'DCCG_PERF_SEL_CRTC2', + 3: 'DCCG_PERF_SEL_CRTC3', + 4: 'DCCG_PERF_SEL_CRTC4', + 5: 'DCCG_PERF_SEL_CRTC5', +} +DCCG_PERF_SEL_CRTC0 = 0 +DCCG_PERF_SEL_CRTC1 = 1 +DCCG_PERF_SEL_CRTC2 = 2 +DCCG_PERF_SEL_CRTC3 = 3 +DCCG_PERF_SEL_CRTC4 = 4 +DCCG_PERF_SEL_CRTC5 = 5 +DCCG_PERF_CRTC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_BRANCH_SOFT_RESET' +CLOCK_BRANCH_SOFT_RESET__enumvalues = { + 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', + 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', +} +CLOCK_BRANCH_SOFT_RESET_NOOP = 0 +CLOCK_BRANCH_SOFT_RESET_FORCE = 1 +CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'PLL_CFG_IF_SOFT_RESET' +PLL_CFG_IF_SOFT_RESET__enumvalues = { + 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', + 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', +} +PLL_CFG_IF_SOFT_RESET_NOOP = 0 +PLL_CFG_IF_SOFT_RESET_FORCE = 1 +PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DVO_ENABLE_RST' +DVO_ENABLE_RST__enumvalues = { + 0: 'DVO_ENABLE_RST_DISABLE', + 1: 'DVO_ENABLE_RST_ENABLE', +} +DVO_ENABLE_RST_DISABLE = 0 +DVO_ENABLE_RST_ENABLE = 1 +DVO_ENABLE_RST = ctypes.c_uint32 # enum + +# values for enumeration 'LptNumPipes' +LptNumPipes__enumvalues = { + 0: 'LPT_NUM_PIPES_1CH', + 1: 'LPT_NUM_PIPES_2CH', + 2: 'LPT_NUM_PIPES_4CH', + 3: 'LPT_NUM_PIPES_8CH', +} +LPT_NUM_PIPES_1CH = 0 +LPT_NUM_PIPES_2CH = 1 +LPT_NUM_PIPES_4CH = 2 +LPT_NUM_PIPES_8CH = 3 +LptNumPipes = ctypes.c_uint32 # enum + +# values for enumeration 'LptNumBanks' +LptNumBanks__enumvalues = { + 0: 'LPT_NUM_BANKS_2BANK', + 1: 'LPT_NUM_BANKS_4BANK', + 2: 'LPT_NUM_BANKS_8BANK', + 3: 'LPT_NUM_BANKS_16BANK', + 4: 'LPT_NUM_BANKS_32BANK', +} +LPT_NUM_BANKS_2BANK = 0 +LPT_NUM_BANKS_4BANK = 1 +LPT_NUM_BANKS_8BANK = 2 +LPT_NUM_BANKS_16BANK = 3 +LPT_NUM_BANKS_32BANK = 4 +LptNumBanks = ctypes.c_uint32 # enum + +# values for enumeration 'OVERRIDE_CGTT_DCEFCLK' +OVERRIDE_CGTT_DCEFCLK__enumvalues = { + 0: 'OVERRIDE_CGTT_DCEFCLK_NOOP', + 1: 'SET_OVERRIDE_CGTT_DCEFCLK', +} +OVERRIDE_CGTT_DCEFCLK_NOOP = 0 +SET_OVERRIDE_CGTT_DCEFCLK = 1 +OVERRIDE_CGTT_DCEFCLK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICA_SEL' +DCIO_DC_GENERICA_SEL__enumvalues = { + 0: 'DCIO_GENERICA_SEL_DACA_STEREOSYNC', + 1: 'DCIO_GENERICA_SEL_STEREOSYNC', + 2: 'DCIO_GENERICA_SEL_DACA_PIXCLK', + 3: 'DCIO_GENERICA_SEL_DACB_PIXCLK', + 4: 'DCIO_GENERICA_SEL_DVOA_CTL3', + 5: 'DCIO_GENERICA_SEL_P1_PLLCLK', + 6: 'DCIO_GENERICA_SEL_P2_PLLCLK', + 7: 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC', + 8: 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER', + 9: 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER', + 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', + 11: 'DCIO_GENERICA_SEL_SYNCEN', + 12: 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK', + 13: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK', + 14: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK', + 15: 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2', + 16: 'DCIO_GENERICA_SEL_GENERICA_DPRX', + 17: 'DCIO_GENERICA_SEL_GENERICB_DPRX', +} +DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0 +DCIO_GENERICA_SEL_STEREOSYNC = 1 +DCIO_GENERICA_SEL_DACA_PIXCLK = 2 +DCIO_GENERICA_SEL_DACB_PIXCLK = 3 +DCIO_GENERICA_SEL_DVOA_CTL3 = 4 +DCIO_GENERICA_SEL_P1_PLLCLK = 5 +DCIO_GENERICA_SEL_P2_PLLCLK = 6 +DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 7 +DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 8 +DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 9 +DCIO_GENERICA_SEL_GENERICA_DCCG = 10 +DCIO_GENERICA_SEL_SYNCEN = 11 +DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 12 +DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 13 +DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 14 +DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15 +DCIO_GENERICA_SEL_GENERICA_DPRX = 16 +DCIO_GENERICA_SEL_GENERICB_DPRX = 17 +DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', + 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', + 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', + 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', + 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', + 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', + 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', + 7: 'DCIO_UNIPHYLPA_TEST_REFDIV_CLK', + 8: 'DCIO_UNIPHYLPB_TEST_REFDIV_CLK', +} +DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 +DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 +DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 +DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 +DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 +DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 +DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 +DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 7 +DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 8 +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_CLK', + 7: 'DCIO_UNIPHYLPA_FBDIV_CLK', + 8: 'DCIO_UNIPHYLPB_FBDIV_CLK', +} +DCIO_UNIPHYA_FBDIV_CLK = 0 +DCIO_UNIPHYB_FBDIV_CLK = 1 +DCIO_UNIPHYC_FBDIV_CLK = 2 +DCIO_UNIPHYD_FBDIV_CLK = 3 +DCIO_UNIPHYE_FBDIV_CLK = 4 +DCIO_UNIPHYF_FBDIV_CLK = 5 +DCIO_UNIPHYG_FBDIV_CLK = 6 +DCIO_UNIPHYLPA_FBDIV_CLK = 7 +DCIO_UNIPHYLPB_FBDIV_CLK = 8 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', + 7: 'DCIO_UNIPHYLPA_FBDIV_SSC_CLK', + 8: 'DCIO_UNIPHYLPB_FBDIV_SSC_CLK', +} +DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 +DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 +DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 +DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 +DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 +DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 +DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 +DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 7 +DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 8 +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', + 7: 'DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2', + 8: 'DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2', +} +DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 +DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 +DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 +DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 +DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 +DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 +DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 +DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 7 +DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 8 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICB_SEL' +DCIO_DC_GENERICB_SEL__enumvalues = { + 0: 'DCIO_GENERICB_SEL_DACA_STEREOSYNC', + 1: 'DCIO_GENERICB_SEL_STEREOSYNC', + 2: 'DCIO_GENERICB_SEL_DACA_PIXCLK', + 3: 'DCIO_GENERICB_SEL_DACB_PIXCLK', + 4: 'DCIO_GENERICB_SEL_DVOA_CTL3', + 5: 'DCIO_GENERICB_SEL_P1_PLLCLK', + 6: 'DCIO_GENERICB_SEL_P2_PLLCLK', + 7: 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC', + 8: 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER', + 9: 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER', + 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', + 11: 'DCIO_GENERICB_SEL_SYNCEN', + 12: 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', + 13: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK', + 14: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK', + 15: 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2', +} +DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0 +DCIO_GENERICB_SEL_STEREOSYNC = 1 +DCIO_GENERICB_SEL_DACA_PIXCLK = 2 +DCIO_GENERICB_SEL_DACB_PIXCLK = 3 +DCIO_GENERICB_SEL_DVOA_CTL3 = 4 +DCIO_GENERICB_SEL_P1_PLLCLK = 5 +DCIO_GENERICB_SEL_P2_PLLCLK = 6 +DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 7 +DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 8 +DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 9 +DCIO_GENERICB_SEL_GENERICB_DCCG = 10 +DCIO_GENERICB_SEL_SYNCEN = 11 +DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 12 +DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 13 +DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 14 +DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 15 +DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_PAD_EXTERN_SIG_SEL' +DCIO_DC_PAD_EXTERN_SIG_SEL__enumvalues = { + 0: 'DCIO_DC_PAD_EXTERN_SIG_SEL_MVP', + 1: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA', + 2: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK', + 3: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC', + 4: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA', + 5: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB', + 6: 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC', + 7: 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1', + 8: 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2', + 9: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK', + 10: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA', + 11: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK', + 12: 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA', + 13: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1', + 14: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0', + 15: 'DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL', +} +DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0 +DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 1 +DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 2 +DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 3 +DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 4 +DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 5 +DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 6 +DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 7 +DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 8 +DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 9 +DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 10 +DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 11 +DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 12 +DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 13 +DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 14 +DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 15 +DCIO_DC_PAD_EXTERN_SIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS' +DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS__enumvalues = { + 0: 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA', + 1: 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE', + 2: 'DCIO_MVP_PIXEL_SRC_STATUS_CRTC', + 3: 'DCIO_MVP_PIXEL_SRC_STATUS_LB', +} +DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0 +DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 1 +DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 2 +DCIO_MVP_PIXEL_SRC_STATUS_LB = 3 +DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', + 1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', + 2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', + 3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', +} +DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0 +DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1 +DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2 +DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3 +DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', +} +DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 +DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_VIP_DEBUG' +DCIO_DC_GPIO_VIP_DEBUG__enumvalues = { + 0: 'DCIO_DC_GPIO_VIP_DEBUG_NORMAL', + 1: 'DCIO_DC_GPIO_VIP_DEBUG_CG_BIG', +} +DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0 +DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 1 +DCIO_DC_GPIO_VIP_DEBUG = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_MACRO_DEBUG' +DCIO_DC_GPIO_MACRO_DEBUG__enumvalues = { + 0: 'DCIO_DC_GPIO_MACRO_DEBUG_NORMAL', + 1: 'DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF', + 2: 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2', + 3: 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3', +} +DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0 +DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 1 +DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 2 +DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 3 +DCIO_DC_GPIO_MACRO_DEBUG = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL' +DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__enumvalues = { + 0: 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL', + 1: 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP', +} +DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0 +DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 1 +DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN' +DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN__enumvalues = { + 0: 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS', + 1: 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE', +} +DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0 +DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 1 +DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE' +DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = { + 0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', + 1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', +} +DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0 +DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1 +DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION' +DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION__enumvalues = { + 0: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS', + 1: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS', + 2: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS', + 3: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS', + 4: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS', + 5: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS', + 6: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS', + 7: 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS', +} +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 1 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 2 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 3 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 4 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 5 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 6 +DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 7 +DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', +} +DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 +DCIO_UNIPHY_CHANNEL_INVERTED = 1 +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { + 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', + 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', +} +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', +} +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN' +DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN__enumvalues = { + 0: 'DCIO_VIP_MUX_EN_DVO', + 1: 'DCIO_VIP_MUX_EN_VIP', +} +DCIO_VIP_MUX_EN_DVO = 0 +DCIO_VIP_MUX_EN_VIP = 1 +DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN' +DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN__enumvalues = { + 0: 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', + 1: 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE', +} +DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0 +DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 1 +DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN' +DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN__enumvalues = { + 0: 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', + 1: 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE', +} +DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0 +DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 1 +DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN' +DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN__enumvalues = { + 0: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE', + 1: 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE', +} +DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0 +DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 1 +DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE' +DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { + 0: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF', + 1: 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON', +} +DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0 +DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 1 +DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL__enumvalues = { + 0: 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT', + 1: 'DCIO_LVTMA_SYNCEN_POL_INVERT', +} +DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0 +DCIO_LVTMA_SYNCEN_POL_INVERT = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON__enumvalues = { + 0: 'DCIO_LVTMA_DIGON_OFF', + 1: 'DCIO_LVTMA_DIGON_ON', +} +DCIO_LVTMA_DIGON_OFF = 0 +DCIO_LVTMA_DIGON_ON = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL__enumvalues = { + 0: 'DCIO_LVTMA_DIGON_POL_NON_INVERT', + 1: 'DCIO_LVTMA_DIGON_POL_INVERT', +} +DCIO_LVTMA_DIGON_POL_NON_INVERT = 0 +DCIO_LVTMA_DIGON_POL_INVERT = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON__enumvalues = { + 0: 'DCIO_LVTMA_BLON_OFF', + 1: 'DCIO_LVTMA_BLON_ON', +} +DCIO_LVTMA_BLON_OFF = 0 +DCIO_LVTMA_BLON_ON = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL' +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL__enumvalues = { + 0: 'DCIO_LVTMA_BLON_POL_NON_INVERT', + 1: 'DCIO_LVTMA_BLON_POL_INVERT', +} +DCIO_LVTMA_BLON_POL_NON_INVERT = 0 +DCIO_LVTMA_BLON_POL_INVERT = 1 +DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN' +DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN__enumvalues = { + 0: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON', + 1: 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE', +} +DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0 +DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 1 +DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' +DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { + 0: 'DCIO_BL_PWM_FRACTIONAL_DISABLE', + 1: 'DCIO_BL_PWM_FRACTIONAL_ENABLE', +} +DCIO_BL_PWM_FRACTIONAL_DISABLE = 0 +DCIO_BL_PWM_FRACTIONAL_ENABLE = 1 +DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL_BL_PWM_EN' +DCIO_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { + 0: 'DCIO_BL_PWM_DISABLE', + 1: 'DCIO_BL_PWM_ENABLE', +} +DCIO_BL_PWM_DISABLE = 0 +DCIO_BL_PWM_ENABLE = 1 +DCIO_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT' +DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = { + 0: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', + 1: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', + 2: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', + 3: 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', +} +DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0 +DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1 +DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2 +DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3 +DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' +DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { + 0: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 1: 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE', +} +DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 +DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 +DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN' +DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__enumvalues = { + 0: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL', + 1: 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM', +} +DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0 +DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 1 +DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_REG_LOCK' +DCIO_BL_PWM_GRP1_REG_LOCK__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE', + 1: 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE', +} +DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 +DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 +DCIO_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START' +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 1: 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', +} +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 +DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', +} +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 1: 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', +} +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 +DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 1: 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', +} +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 +DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL_SEL' +DCIO_GSL_SEL__enumvalues = { + 0: 'DCIO_GSL_SEL_GROUP_0', + 1: 'DCIO_GSL_SEL_GROUP_1', + 2: 'DCIO_GSL_SEL_GROUP_2', +} +DCIO_GSL_SEL_GROUP_0 = 0 +DCIO_GSL_SEL_GROUP_1 = 1 +DCIO_GSL_SEL_GROUP_2 = 2 +DCIO_GSL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' +DCIO_GENLK_CLK_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', + 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', +} +DCIO_GENLK_CLK_GSL_MASK_NO = 0 +DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 +DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 +DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' +DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', +} +DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 +DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 +DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 +DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' +DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' +DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL_VSYNC_SEL' +DCIO_GSL_VSYNC_SEL__enumvalues = { + 0: 'DCIO_GSL_VSYNC_SEL_PIPE0', + 1: 'DCIO_GSL_VSYNC_SEL_PIPE1', + 2: 'DCIO_GSL_VSYNC_SEL_PIPE2', + 3: 'DCIO_GSL_VSYNC_SEL_PIPE3', + 4: 'DCIO_GSL_VSYNC_SEL_PIPE4', + 5: 'DCIO_GSL_VSYNC_SEL_PIPE5', +} +DCIO_GSL_VSYNC_SEL_PIPE0 = 0 +DCIO_GSL_VSYNC_SEL_PIPE1 = 1 +DCIO_GSL_VSYNC_SEL_PIPE2 = 2 +DCIO_GSL_VSYNC_SEL_PIPE3 = 3 +DCIO_GSL_VSYNC_SEL_PIPE4 = 4 +DCIO_GSL_VSYNC_SEL_PIPE5 = 5 +DCIO_GSL_VSYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL0_TIMING_SYNC_SEL' +DCIO_GSL0_TIMING_SYNC_SEL__enumvalues = { + 0: 'DCIO_GSL0_TIMING_SYNC_SEL_PIPE', + 1: 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC', + 2: 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK', + 3: 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A', + 4: 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B', +} +DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0 +DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 1 +DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 2 +DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 3 +DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 4 +DCIO_GSL0_TIMING_SYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL0_GLOBAL_UNLOCK_SEL' +DCIO_GSL0_GLOBAL_UNLOCK_SEL__enumvalues = { + 0: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION', + 1: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', + 2: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK', + 3: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', + 4: 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', +} +DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0 +DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 1 +DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 2 +DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 3 +DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 4 +DCIO_GSL0_GLOBAL_UNLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL1_TIMING_SYNC_SEL' +DCIO_GSL1_TIMING_SYNC_SEL__enumvalues = { + 0: 'DCIO_GSL1_TIMING_SYNC_SEL_PIPE', + 1: 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC', + 2: 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK', + 3: 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A', + 4: 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B', +} +DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0 +DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 1 +DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 2 +DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 3 +DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 4 +DCIO_GSL1_TIMING_SYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL1_GLOBAL_UNLOCK_SEL' +DCIO_GSL1_GLOBAL_UNLOCK_SEL__enumvalues = { + 0: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION', + 1: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', + 2: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK', + 3: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', + 4: 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', +} +DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0 +DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 1 +DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 2 +DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 3 +DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 4 +DCIO_GSL1_GLOBAL_UNLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL2_TIMING_SYNC_SEL' +DCIO_GSL2_TIMING_SYNC_SEL__enumvalues = { + 0: 'DCIO_GSL2_TIMING_SYNC_SEL_PIPE', + 1: 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC', + 2: 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK', + 3: 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A', + 4: 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B', +} +DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0 +DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 1 +DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 2 +DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 3 +DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 4 +DCIO_GSL2_TIMING_SYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL2_GLOBAL_UNLOCK_SEL' +DCIO_GSL2_GLOBAL_UNLOCK_SEL__enumvalues = { + 0: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION', + 1: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', + 2: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK', + 3: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', + 4: 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', +} +DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0 +DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 1 +DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 2 +DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 3 +DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 4 +DCIO_GSL2_GLOBAL_UNLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' +DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { + 0: 'DCIO_GPU_TIMER_START_0_END_27', + 1: 'DCIO_GPU_TIMER_START_1_END_28', + 2: 'DCIO_GPU_TIMER_START_2_END_29', + 3: 'DCIO_GPU_TIMER_START_3_END_30', + 4: 'DCIO_GPU_TIMER_START_4_END_31', + 5: 'DCIO_GPU_TIMER_START_6_END_33', + 6: 'DCIO_GPU_TIMER_START_8_END_35', + 7: 'DCIO_GPU_TIMER_START_10_END_37', +} +DCIO_GPU_TIMER_START_0_END_27 = 0 +DCIO_GPU_TIMER_START_1_END_28 = 1 +DCIO_GPU_TIMER_START_2_END_29 = 2 +DCIO_GPU_TIMER_START_3_END_30 = 3 +DCIO_GPU_TIMER_START_4_END_31 = 4 +DCIO_GPU_TIMER_START_6_END_33 = 5 +DCIO_GPU_TIMER_START_8_END_35 = 6 +DCIO_GPU_TIMER_START_10_END_37 = 7 +DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { + 0: 'DCIO_TEST_CLK_SEL_DISPCLK', + 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', + 2: 'DCIO_TEST_CLK_SEL_SCLK', +} +DCIO_TEST_CLK_SEL_DISPCLK = 0 +DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 +DCIO_TEST_CLK_SEL_SCLK = 2 +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { + 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', +} +DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 +DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DCO_DCFE_EXT_VSYNC_MUX' +DCIO_DCO_DCFE_EXT_VSYNC_MUX__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 1: 'DCIO_EXT_VSYNC_MUX_CRTC0', + 2: 'DCIO_EXT_VSYNC_MUX_CRTC1', + 3: 'DCIO_EXT_VSYNC_MUX_CRTC2', + 4: 'DCIO_EXT_VSYNC_MUX_CRTC3', + 5: 'DCIO_EXT_VSYNC_MUX_CRTC4', + 6: 'DCIO_EXT_VSYNC_MUX_CRTC5', + 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', +} +DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 +DCIO_EXT_VSYNC_MUX_CRTC0 = 1 +DCIO_EXT_VSYNC_MUX_CRTC1 = 2 +DCIO_EXT_VSYNC_MUX_CRTC2 = 3 +DCIO_EXT_VSYNC_MUX_CRTC3 = 4 +DCIO_EXT_VSYNC_MUX_CRTC4 = 5 +DCIO_EXT_VSYNC_MUX_CRTC5 = 6 +DCIO_EXT_VSYNC_MUX_GENERICB = 7 +DCIO_DCO_DCFE_EXT_VSYNC_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DCO_EXT_VSYNC_MASK' +DCIO_DCO_EXT_VSYNC_MASK__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MASK_NONE', + 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', + 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', + 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', + 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', + 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', + 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', + 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', +} +DCIO_EXT_VSYNC_MASK_NONE = 0 +DCIO_EXT_VSYNC_MASK_PIPE0 = 1 +DCIO_EXT_VSYNC_MASK_PIPE1 = 2 +DCIO_EXT_VSYNC_MASK_PIPE2 = 3 +DCIO_EXT_VSYNC_MASK_PIPE3 = 4 +DCIO_EXT_VSYNC_MASK_PIPE4 = 5 +DCIO_EXT_VSYNC_MASK_PIPE5 = 6 +DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 +DCIO_DCO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DSYNC_SOFT_RESET' +DCIO_DSYNC_SOFT_RESET__enumvalues = { + 0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT', + 1: 'DCIO_DSYNC_SOFT_RESET_ASSERT', +} +DCIO_DSYNC_SOFT_RESET_DEASSERT = 0 +DCIO_DSYNC_SOFT_RESET_ASSERT = 1 +DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DACA_SOFT_RESET' +DCIO_DACA_SOFT_RESET__enumvalues = { + 0: 'DCIO_DACA_SOFT_RESET_DEASSERT', + 1: 'DCIO_DACA_SOFT_RESET_ASSERT', +} +DCIO_DACA_SOFT_RESET_DEASSERT = 0 +DCIO_DACA_SOFT_RESET_ASSERT = 1 +DCIO_DACA_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' +DCIO_DCRXPHY_SOFT_RESET__enumvalues = { + 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', + 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', +} +DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 +DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 +DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPHY_LANE_SEL' +DCIO_DPHY_LANE_SEL__enumvalues = { + 0: 'DCIO_DPHY_LANE_SEL_LANE0', + 1: 'DCIO_DPHY_LANE_SEL_LANE1', + 2: 'DCIO_DPHY_LANE_SEL_LANE2', + 3: 'DCIO_DPHY_LANE_SEL_LANE3', +} +DCIO_DPHY_LANE_SEL_LANE0 = 0 +DCIO_DPHY_LANE_SEL_LANE1 = 1 +DCIO_DPHY_LANE_SEL_LANE2 = 2 +DCIO_DPHY_LANE_SEL_LANE3 = 3 +DCIO_DPHY_LANE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' +DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', +} +DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 +DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 +DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' +DCIO_DPCS_INTERRUPT_MASK__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_DISABLE', + 1: 'DCIO_DPCS_INTERRUPT_ENABLE', +} +DCIO_DPCS_INTERRUPT_DISABLE = 0 +DCIO_DPCS_INTERRUPT_ENABLE = 1 +DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' +DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { + 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE', + 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE', + 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE', + 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE', + 6: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE', + 7: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE', + 8: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE', + 9: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE', + 10: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE', + 11: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE', + 12: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 13: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 14: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP', + 15: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP', + 16: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP', + 17: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP', + 18: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP', + 19: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP', + 20: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP', + 21: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP', + 22: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP', + 23: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP', + 24: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 25: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', + 26: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM', + 27: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM', + 28: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM', + 29: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM', + 30: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM', + 31: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM', + 32: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM', + 33: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM', + 34: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM', + 35: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM', +} +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 2 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 3 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 4 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 5 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 6 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 7 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 8 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 9 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 10 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 11 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 12 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 13 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 14 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 15 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 16 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 17 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 18 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 19 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 20 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 21 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 22 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 23 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 24 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 25 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 26 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 27 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 28 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 29 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 30 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 31 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 32 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 33 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 34 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 35 +DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_IMPCAL_STEP_DELAY' +DCIO_IMPCAL_STEP_DELAY__enumvalues = { + 0: 'DCIO_IMPCAL_STEP_DELAY_1us', + 1: 'DCIO_IMPCAL_STEP_DELAY_2us', + 2: 'DCIO_IMPCAL_STEP_DELAY_3us', + 3: 'DCIO_IMPCAL_STEP_DELAY_4us', + 4: 'DCIO_IMPCAL_STEP_DELAY_5us', + 5: 'DCIO_IMPCAL_STEP_DELAY_6us', + 6: 'DCIO_IMPCAL_STEP_DELAY_7us', + 7: 'DCIO_IMPCAL_STEP_DELAY_8us', + 8: 'DCIO_IMPCAL_STEP_DELAY_9us', + 9: 'DCIO_IMPCAL_STEP_DELAY_10us', + 10: 'DCIO_IMPCAL_STEP_DELAY_11us', + 11: 'DCIO_IMPCAL_STEP_DELAY_12us', + 12: 'DCIO_IMPCAL_STEP_DELAY_13us', + 13: 'DCIO_IMPCAL_STEP_DELAY_14us', + 14: 'DCIO_IMPCAL_STEP_DELAY_15us', + 15: 'DCIO_IMPCAL_STEP_DELAY_16us', +} +DCIO_IMPCAL_STEP_DELAY_1us = 0 +DCIO_IMPCAL_STEP_DELAY_2us = 1 +DCIO_IMPCAL_STEP_DELAY_3us = 2 +DCIO_IMPCAL_STEP_DELAY_4us = 3 +DCIO_IMPCAL_STEP_DELAY_5us = 4 +DCIO_IMPCAL_STEP_DELAY_6us = 5 +DCIO_IMPCAL_STEP_DELAY_7us = 6 +DCIO_IMPCAL_STEP_DELAY_8us = 7 +DCIO_IMPCAL_STEP_DELAY_9us = 8 +DCIO_IMPCAL_STEP_DELAY_10us = 9 +DCIO_IMPCAL_STEP_DELAY_11us = 10 +DCIO_IMPCAL_STEP_DELAY_12us = 11 +DCIO_IMPCAL_STEP_DELAY_13us = 12 +DCIO_IMPCAL_STEP_DELAY_14us = 13 +DCIO_IMPCAL_STEP_DELAY_15us = 14 +DCIO_IMPCAL_STEP_DELAY_16us = 15 +DCIO_IMPCAL_STEP_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' +DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { + 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', +} +DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 +DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 +DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL' +DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = { + 0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', + 1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', + 2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', + 3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCO', +} +DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0 +DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1 +DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2 +DCIO_DBG_ASYNC_BLOCK_SEL_DCO = 3 +DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL' +DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = { + 0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', + 1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', + 2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', + 3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', + 4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', + 5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', + 6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', + 7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', +} +DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0 +DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1 +DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2 +DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3 +DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4 +DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5 +DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6 +DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7 +DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'AOUT_EN' +AOUT_EN__enumvalues = { + 0: 'AOUT_DISABLE', + 1: 'AOUT_ENABLE', +} +AOUT_DISABLE = 0 +AOUT_ENABLE = 1 +AOUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'AOUT_FIFO_START_ADDR' +AOUT_FIFO_START_ADDR__enumvalues = { + 0: 'AOUT_FIFO_START_ADDR_2', + 1: 'AOUT_FIFO_START_ADDR_3', +} +AOUT_FIFO_START_ADDR_2 = 0 +AOUT_FIFO_START_ADDR_3 = 1 +AOUT_FIFO_START_ADDR = ctypes.c_uint32 # enum + +# values for enumeration 'AOUT_CRC_TEST_EN' +AOUT_CRC_TEST_EN__enumvalues = { + 0: 'AOUT_CRC_DISABLE', + 1: 'AOUT_CRC_ENABLE', +} +AOUT_CRC_DISABLE = 0 +AOUT_CRC_ENABLE = 1 +AOUT_CRC_TEST_EN = ctypes.c_uint32 # enum + +# values for enumeration 'AOUT_CRC_SOFT_RESET' +AOUT_CRC_SOFT_RESET__enumvalues = { + 0: 'AOUT_CRC_NO_RESET', + 1: 'AOUT_CRC_RESET', +} +AOUT_CRC_NO_RESET = 0 +AOUT_CRC_RESET = 1 +AOUT_CRC_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AOUT_CRC_CONT_EN' +AOUT_CRC_CONT_EN__enumvalues = { + 0: 'AOUT_CRC_ONE_SHOT', + 1: 'AOUT_CRC_CONT', +} +AOUT_CRC_ONE_SHOT = 0 +AOUT_CRC_CONT = 1 +AOUT_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'I2S_WORD_SIZE' +I2S_WORD_SIZE__enumvalues = { + 0: 'I2S_WORD_SIZE_32', + 1: 'I2S_WORD_SIZE_16', +} +I2S_WORD_SIZE_32 = 0 +I2S_WORD_SIZE_16 = 1 +I2S_WORD_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'I2S_SAMPLE_ALIGNMENT' +I2S_SAMPLE_ALIGNMENT__enumvalues = { + 0: 'I2S_SAMPLE_LEFT_ALIGNED', + 1: 'I2S_SAMPLE_RIGHT_ALIGNED', +} +I2S_SAMPLE_LEFT_ALIGNED = 0 +I2S_SAMPLE_RIGHT_ALIGNED = 1 +I2S_SAMPLE_ALIGNMENT = ctypes.c_uint32 # enum + +# values for enumeration 'I2S_SAMPLE_BIT_ORDER' +I2S_SAMPLE_BIT_ORDER__enumvalues = { + 0: 'I2S_SAMPLE_BIT_ORDER_MSB', + 1: 'I2S_SAMPLE_BIT_ORDER_LSB', +} +I2S_SAMPLE_BIT_ORDER_MSB = 0 +I2S_SAMPLE_BIT_ORDER_LSB = 1 +I2S_SAMPLE_BIT_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'I2S_LRCLK_POLARITY' +I2S_LRCLK_POLARITY__enumvalues = { + 0: 'I2S_LRCLK_LOW_LEFT', + 1: 'I2S_LRCLK_HIGH_LEFT', +} +I2S_LRCLK_LOW_LEFT = 0 +I2S_LRCLK_HIGH_LEFT = 1 +I2S_LRCLK_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'I2S_WORD_ALIGNMENT' +I2S_WORD_ALIGNMENT__enumvalues = { + 0: 'I2S_WORD_ALTERNATE_ALIGNMENT', + 1: 'I2S_WORD_I2S_ALIGNMENT', +} +I2S_WORD_ALTERNATE_ALIGNMENT = 0 +I2S_WORD_I2S_ALIGNMENT = 1 +I2S_WORD_ALIGNMENT = ctypes.c_uint32 # enum + +# values for enumeration 'SPDIF_INVERT_EN' +SPDIF_INVERT_EN__enumvalues = { + 0: 'SPDIF_INVERT_DISABLE', + 1: 'SPDIF_INVERT_ENABLE', +} +SPDIF_INVERT_DISABLE = 0 +SPDIF_INVERT_ENABLE = 1 +SPDIF_INVERT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_EN' +DPDBG_EN__enumvalues = { + 0: 'DPDBG_DISABLE', + 1: 'DPDBG_ENABLE', +} +DPDBG_DISABLE = 0 +DPDBG_ENABLE = 1 +DPDBG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_INPUT_EN' +DPDBG_INPUT_EN__enumvalues = { + 0: 'DPDBG_INPUT_DISABLE', + 1: 'DPDBG_INPUT_ENABLE', +} +DPDBG_INPUT_DISABLE = 0 +DPDBG_INPUT_ENABLE = 1 +DPDBG_INPUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_ERROR_DETECTION_MODE' +DPDBG_ERROR_DETECTION_MODE__enumvalues = { + 0: 'DPDBG_ERROR_DETECTION_MODE_CSC', + 1: 'DPDBG_ERROR_DETECTION_MODE_RS_ENCODING', +} +DPDBG_ERROR_DETECTION_MODE_CSC = 0 +DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 1 +DPDBG_ERROR_DETECTION_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK' +DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK__enumvalues = { + 0: 'DPDBG_FIFO_OVERFLOW_INT_DISABLE', + 1: 'DPDBG_FIFO_OVERFLOW_INT_ENABLE', +} +DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0 +DPDBG_FIFO_OVERFLOW_INT_ENABLE = 1 +DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE' +DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE__enumvalues = { + 0: 'DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED', + 1: 'DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED', +} +DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0 +DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 1 +DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK' +DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK__enumvalues = { + 0: 'DPDBG_FIFO_OVERFLOW_INT_NO_ACK', + 1: 'DPDBG_FIFO_OVERFLOW_INT_CLEAR', +} +DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0 +DPDBG_FIFO_OVERFLOW_INT_CLEAR = 1 +DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'PM_ASSERT_RESET' +PM_ASSERT_RESET__enumvalues = { + 0: 'PM_ASSERT_RESET_0', + 1: 'PM_ASSERT_RESET_1', +} +PM_ASSERT_RESET_0 = 0 +PM_ASSERT_RESET_1 = 1 +PM_ASSERT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DAC_MUX_SELECT' +DAC_MUX_SELECT__enumvalues = { + 0: 'DAC_MUX_SELECT_DACA', + 1: 'DAC_MUX_SELECT_DACB', +} +DAC_MUX_SELECT_DACA = 0 +DAC_MUX_SELECT_DACB = 1 +DAC_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_DVO_MUX_SELECT' +TMDS_DVO_MUX_SELECT__enumvalues = { + 0: 'TMDS_DVO_MUX_SELECT_B', + 1: 'TMDS_DVO_MUX_SELECT_G', + 2: 'TMDS_DVO_MUX_SELECT_R', + 3: 'TMDS_DVO_MUX_SELECT_RESERVED', +} +TMDS_DVO_MUX_SELECT_B = 0 +TMDS_DVO_MUX_SELECT_G = 1 +TMDS_DVO_MUX_SELECT_R = 2 +TMDS_DVO_MUX_SELECT_RESERVED = 3 +TMDS_DVO_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DACA_SOFT_RESET' +DACA_SOFT_RESET__enumvalues = { + 0: 'DACA_SOFT_RESET_0', + 1: 'DACA_SOFT_RESET_1', +} +DACA_SOFT_RESET_0 = 0 +DACA_SOFT_RESET_1 = 1 +DACA_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'I2S0_SPDIF0_SOFT_RESET' +I2S0_SPDIF0_SOFT_RESET__enumvalues = { + 0: 'I2S0_SPDIF0_SOFT_RESET_0', + 1: 'I2S0_SPDIF0_SOFT_RESET_1', +} +I2S0_SPDIF0_SOFT_RESET_0 = 0 +I2S0_SPDIF0_SOFT_RESET_1 = 1 +I2S0_SPDIF0_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'I2S1_SOFT_RESET' +I2S1_SOFT_RESET__enumvalues = { + 0: 'I2S1_SOFT_RESET_0', + 1: 'I2S1_SOFT_RESET_1', +} +I2S1_SOFT_RESET_0 = 0 +I2S1_SOFT_RESET_1 = 1 +I2S1_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'SPDIF1_SOFT_RESET' +SPDIF1_SOFT_RESET__enumvalues = { + 0: 'SPDIF1_SOFT_RESET_0', + 1: 'SPDIF1_SOFT_RESET_1', +} +SPDIF1_SOFT_RESET_0 = 0 +SPDIF1_SOFT_RESET_1 = 1 +SPDIF1_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DB_CLK_SOFT_RESET' +DB_CLK_SOFT_RESET__enumvalues = { + 0: 'DB_CLK_SOFT_RESET_0', + 1: 'DB_CLK_SOFT_RESET_1', +} +DB_CLK_SOFT_RESET_0 = 0 +DB_CLK_SOFT_RESET_1 = 1 +DB_CLK_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'FMT0_SOFT_RESET' +FMT0_SOFT_RESET__enumvalues = { + 0: 'FMT0_SOFT_RESET_0', + 1: 'FMT0_SOFT_RESET_1', +} +FMT0_SOFT_RESET_0 = 0 +FMT0_SOFT_RESET_1 = 1 +FMT0_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'FMT1_SOFT_RESET' +FMT1_SOFT_RESET__enumvalues = { + 0: 'FMT1_SOFT_RESET_0', + 1: 'FMT1_SOFT_RESET_1', +} +FMT1_SOFT_RESET_0 = 0 +FMT1_SOFT_RESET_1 = 1 +FMT1_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'FMT2_SOFT_RESET' +FMT2_SOFT_RESET__enumvalues = { + 0: 'FMT2_SOFT_RESET_0', + 1: 'FMT2_SOFT_RESET_1', +} +FMT2_SOFT_RESET_0 = 0 +FMT2_SOFT_RESET_1 = 1 +FMT2_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'FMT3_SOFT_RESET' +FMT3_SOFT_RESET__enumvalues = { + 0: 'FMT3_SOFT_RESET_0', + 1: 'FMT3_SOFT_RESET_1', +} +FMT3_SOFT_RESET_0 = 0 +FMT3_SOFT_RESET_1 = 1 +FMT3_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'FMT4_SOFT_RESET' +FMT4_SOFT_RESET__enumvalues = { + 0: 'FMT4_SOFT_RESET_0', + 1: 'FMT4_SOFT_RESET_1', +} +FMT4_SOFT_RESET_0 = 0 +FMT4_SOFT_RESET_1 = 1 +FMT4_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'FMT5_SOFT_RESET' +FMT5_SOFT_RESET__enumvalues = { + 0: 'FMT5_SOFT_RESET_0', + 1: 'FMT5_SOFT_RESET_1', +} +FMT5_SOFT_RESET_0 = 0 +FMT5_SOFT_RESET_1 = 1 +FMT5_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'MVP_SOFT_RESET' +MVP_SOFT_RESET__enumvalues = { + 0: 'MVP_SOFT_RESET_0', + 1: 'MVP_SOFT_RESET_1', +} +MVP_SOFT_RESET_0 = 0 +MVP_SOFT_RESET_1 = 1 +MVP_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'ABM_SOFT_RESET' +ABM_SOFT_RESET__enumvalues = { + 0: 'ABM_SOFT_RESET_0', + 1: 'ABM_SOFT_RESET_1', +} +ABM_SOFT_RESET_0 = 0 +ABM_SOFT_RESET_1 = 1 +ABM_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DVO_SOFT_RESET' +DVO_SOFT_RESET__enumvalues = { + 0: 'DVO_SOFT_RESET_0', + 1: 'DVO_SOFT_RESET_1', +} +DVO_SOFT_RESET_0 = 0 +DVO_SOFT_RESET_1 = 1 +DVO_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGA_FE_SOFT_RESET' +DIGA_FE_SOFT_RESET__enumvalues = { + 0: 'DIGA_FE_SOFT_RESET_0', + 1: 'DIGA_FE_SOFT_RESET_1', +} +DIGA_FE_SOFT_RESET_0 = 0 +DIGA_FE_SOFT_RESET_1 = 1 +DIGA_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGA_BE_SOFT_RESET' +DIGA_BE_SOFT_RESET__enumvalues = { + 0: 'DIGA_BE_SOFT_RESET_0', + 1: 'DIGA_BE_SOFT_RESET_1', +} +DIGA_BE_SOFT_RESET_0 = 0 +DIGA_BE_SOFT_RESET_1 = 1 +DIGA_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGB_FE_SOFT_RESET' +DIGB_FE_SOFT_RESET__enumvalues = { + 0: 'DIGB_FE_SOFT_RESET_0', + 1: 'DIGB_FE_SOFT_RESET_1', +} +DIGB_FE_SOFT_RESET_0 = 0 +DIGB_FE_SOFT_RESET_1 = 1 +DIGB_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGB_BE_SOFT_RESET' +DIGB_BE_SOFT_RESET__enumvalues = { + 0: 'DIGB_BE_SOFT_RESET_0', + 1: 'DIGB_BE_SOFT_RESET_1', +} +DIGB_BE_SOFT_RESET_0 = 0 +DIGB_BE_SOFT_RESET_1 = 1 +DIGB_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGC_FE_SOFT_RESET' +DIGC_FE_SOFT_RESET__enumvalues = { + 0: 'DIGC_FE_SOFT_RESET_0', + 1: 'DIGC_FE_SOFT_RESET_1', +} +DIGC_FE_SOFT_RESET_0 = 0 +DIGC_FE_SOFT_RESET_1 = 1 +DIGC_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGC_BE_SOFT_RESET' +DIGC_BE_SOFT_RESET__enumvalues = { + 0: 'DIGC_BE_SOFT_RESET_0', + 1: 'DIGC_BE_SOFT_RESET_1', +} +DIGC_BE_SOFT_RESET_0 = 0 +DIGC_BE_SOFT_RESET_1 = 1 +DIGC_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGD_FE_SOFT_RESET' +DIGD_FE_SOFT_RESET__enumvalues = { + 0: 'DIGD_FE_SOFT_RESET_0', + 1: 'DIGD_FE_SOFT_RESET_1', +} +DIGD_FE_SOFT_RESET_0 = 0 +DIGD_FE_SOFT_RESET_1 = 1 +DIGD_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGD_BE_SOFT_RESET' +DIGD_BE_SOFT_RESET__enumvalues = { + 0: 'DIGD_BE_SOFT_RESET_0', + 1: 'DIGD_BE_SOFT_RESET_1', +} +DIGD_BE_SOFT_RESET_0 = 0 +DIGD_BE_SOFT_RESET_1 = 1 +DIGD_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGE_FE_SOFT_RESET' +DIGE_FE_SOFT_RESET__enumvalues = { + 0: 'DIGE_FE_SOFT_RESET_0', + 1: 'DIGE_FE_SOFT_RESET_1', +} +DIGE_FE_SOFT_RESET_0 = 0 +DIGE_FE_SOFT_RESET_1 = 1 +DIGE_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGE_BE_SOFT_RESET' +DIGE_BE_SOFT_RESET__enumvalues = { + 0: 'DIGE_BE_SOFT_RESET_0', + 1: 'DIGE_BE_SOFT_RESET_1', +} +DIGE_BE_SOFT_RESET_0 = 0 +DIGE_BE_SOFT_RESET_1 = 1 +DIGE_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGF_FE_SOFT_RESET' +DIGF_FE_SOFT_RESET__enumvalues = { + 0: 'DIGF_FE_SOFT_RESET_0', + 1: 'DIGF_FE_SOFT_RESET_1', +} +DIGF_FE_SOFT_RESET_0 = 0 +DIGF_FE_SOFT_RESET_1 = 1 +DIGF_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGF_BE_SOFT_RESET' +DIGF_BE_SOFT_RESET__enumvalues = { + 0: 'DIGF_BE_SOFT_RESET_0', + 1: 'DIGF_BE_SOFT_RESET_1', +} +DIGF_BE_SOFT_RESET_0 = 0 +DIGF_BE_SOFT_RESET_1 = 1 +DIGF_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGG_FE_SOFT_RESET' +DIGG_FE_SOFT_RESET__enumvalues = { + 0: 'DIGG_FE_SOFT_RESET_0', + 1: 'DIGG_FE_SOFT_RESET_1', +} +DIGG_FE_SOFT_RESET_0 = 0 +DIGG_FE_SOFT_RESET_1 = 1 +DIGG_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGG_BE_SOFT_RESET' +DIGG_BE_SOFT_RESET__enumvalues = { + 0: 'DIGG_BE_SOFT_RESET_0', + 1: 'DIGG_BE_SOFT_RESET_1', +} +DIGG_BE_SOFT_RESET_0 = 0 +DIGG_BE_SOFT_RESET_1 = 1 +DIGG_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DPDBG_SOFT_RESET' +DPDBG_SOFT_RESET__enumvalues = { + 0: 'DPDBG_SOFT_RESET_0', + 1: 'DPDBG_SOFT_RESET_1', +} +DPDBG_SOFT_RESET_0 = 0 +DPDBG_SOFT_RESET_1 = 1 +DPDBG_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGLPA_FE_SOFT_RESET' +DIGLPA_FE_SOFT_RESET__enumvalues = { + 0: 'DIGLPA_FE_SOFT_RESET_0', + 1: 'DIGLPA_FE_SOFT_RESET_1', +} +DIGLPA_FE_SOFT_RESET_0 = 0 +DIGLPA_FE_SOFT_RESET_1 = 1 +DIGLPA_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGLPA_BE_SOFT_RESET' +DIGLPA_BE_SOFT_RESET__enumvalues = { + 0: 'DIGLPA_BE_SOFT_RESET_0', + 1: 'DIGLPA_BE_SOFT_RESET_1', +} +DIGLPA_BE_SOFT_RESET_0 = 0 +DIGLPA_BE_SOFT_RESET_1 = 1 +DIGLPA_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGLPB_FE_SOFT_RESET' +DIGLPB_FE_SOFT_RESET__enumvalues = { + 0: 'DIGLPB_FE_SOFT_RESET_0', + 1: 'DIGLPB_FE_SOFT_RESET_1', +} +DIGLPB_FE_SOFT_RESET_0 = 0 +DIGLPB_FE_SOFT_RESET_1 = 1 +DIGLPB_FE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIGLPB_BE_SOFT_RESET' +DIGLPB_BE_SOFT_RESET__enumvalues = { + 0: 'DIGLPB_BE_SOFT_RESET_0', + 1: 'DIGLPB_BE_SOFT_RESET_1', +} +DIGLPB_BE_SOFT_RESET_0 = 0 +DIGLPB_BE_SOFT_RESET_1 = 1 +DIGLPB_BE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'GENERICA_STEREOSYNC_SEL' +GENERICA_STEREOSYNC_SEL__enumvalues = { + 0: 'GENERICA_STEREOSYNC_SEL_D1', + 1: 'GENERICA_STEREOSYNC_SEL_D2', + 2: 'GENERICA_STEREOSYNC_SEL_D3', + 3: 'GENERICA_STEREOSYNC_SEL_D4', + 4: 'GENERICA_STEREOSYNC_SEL_D5', + 5: 'GENERICA_STEREOSYNC_SEL_D6', + 6: 'GENERICA_STEREOSYNC_SEL_RESERVED', +} +GENERICA_STEREOSYNC_SEL_D1 = 0 +GENERICA_STEREOSYNC_SEL_D2 = 1 +GENERICA_STEREOSYNC_SEL_D3 = 2 +GENERICA_STEREOSYNC_SEL_D4 = 3 +GENERICA_STEREOSYNC_SEL_D5 = 4 +GENERICA_STEREOSYNC_SEL_D6 = 5 +GENERICA_STEREOSYNC_SEL_RESERVED = 6 +GENERICA_STEREOSYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GENERICB_STEREOSYNC_SEL' +GENERICB_STEREOSYNC_SEL__enumvalues = { + 0: 'GENERICB_STEREOSYNC_SEL_D1', + 1: 'GENERICB_STEREOSYNC_SEL_D2', + 2: 'GENERICB_STEREOSYNC_SEL_D3', + 3: 'GENERICB_STEREOSYNC_SEL_D4', + 4: 'GENERICB_STEREOSYNC_SEL_D5', + 5: 'GENERICB_STEREOSYNC_SEL_D6', + 6: 'GENERICB_STEREOSYNC_SEL_RESERVED', +} +GENERICB_STEREOSYNC_SEL_D1 = 0 +GENERICB_STEREOSYNC_SEL_D2 = 1 +GENERICB_STEREOSYNC_SEL_D3 = 2 +GENERICB_STEREOSYNC_SEL_D4 = 3 +GENERICB_STEREOSYNC_SEL_D5 = 4 +GENERICB_STEREOSYNC_SEL_D6 = 5 +GENERICB_STEREOSYNC_SEL_RESERVED = 6 +GENERICB_STEREOSYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCO_DBG_BLOCK_SEL' +DCO_DBG_BLOCK_SEL__enumvalues = { + 0: 'DCO_DBG_BLOCK_SEL_DCO', + 1: 'DCO_DBG_BLOCK_SEL_ABM', + 2: 'DCO_DBG_BLOCK_SEL_DVO', + 3: 'DCO_DBG_BLOCK_SEL_DAC', + 4: 'DCO_DBG_BLOCK_SEL_MVP', + 5: 'DCO_DBG_BLOCK_SEL_FMT0', + 6: 'DCO_DBG_BLOCK_SEL_FMT1', + 7: 'DCO_DBG_BLOCK_SEL_FMT2', + 8: 'DCO_DBG_BLOCK_SEL_FMT3', + 9: 'DCO_DBG_BLOCK_SEL_FMT4', + 10: 'DCO_DBG_BLOCK_SEL_FMT5', + 11: 'DCO_DBG_BLOCK_SEL_DIGFE_A', + 12: 'DCO_DBG_BLOCK_SEL_DIGFE_B', + 13: 'DCO_DBG_BLOCK_SEL_DIGFE_C', + 14: 'DCO_DBG_BLOCK_SEL_DIGFE_D', + 15: 'DCO_DBG_BLOCK_SEL_DIGFE_E', + 16: 'DCO_DBG_BLOCK_SEL_DIGFE_F', + 17: 'DCO_DBG_BLOCK_SEL_DIGFE_G', + 18: 'DCO_DBG_BLOCK_SEL_DIGA', + 19: 'DCO_DBG_BLOCK_SEL_DIGB', + 20: 'DCO_DBG_BLOCK_SEL_DIGC', + 21: 'DCO_DBG_BLOCK_SEL_DIGD', + 22: 'DCO_DBG_BLOCK_SEL_DIGE', + 23: 'DCO_DBG_BLOCK_SEL_DIGF', + 24: 'DCO_DBG_BLOCK_SEL_DIGG', + 25: 'DCO_DBG_BLOCK_SEL_DPFE_A', + 26: 'DCO_DBG_BLOCK_SEL_DPFE_B', + 27: 'DCO_DBG_BLOCK_SEL_DPFE_C', + 28: 'DCO_DBG_BLOCK_SEL_DPFE_D', + 29: 'DCO_DBG_BLOCK_SEL_DPFE_E', + 30: 'DCO_DBG_BLOCK_SEL_DPFE_F', + 31: 'DCO_DBG_BLOCK_SEL_DPFE_G', + 32: 'DCO_DBG_BLOCK_SEL_DPA', + 33: 'DCO_DBG_BLOCK_SEL_DPB', + 34: 'DCO_DBG_BLOCK_SEL_DPC', + 35: 'DCO_DBG_BLOCK_SEL_DPD', + 36: 'DCO_DBG_BLOCK_SEL_DPE', + 37: 'DCO_DBG_BLOCK_SEL_DPF', + 38: 'DCO_DBG_BLOCK_SEL_DPG', + 39: 'DCO_DBG_BLOCK_SEL_AUX0', + 40: 'DCO_DBG_BLOCK_SEL_AUX1', + 41: 'DCO_DBG_BLOCK_SEL_AUX2', + 42: 'DCO_DBG_BLOCK_SEL_AUX3', + 43: 'DCO_DBG_BLOCK_SEL_AUX4', + 44: 'DCO_DBG_BLOCK_SEL_AUX5', + 45: 'DCO_DBG_BLOCK_SEL_PERFMON_DCO', + 46: 'DCO_DBG_BLOCK_SEL_AUDIO_OUT', + 47: 'DCO_DBG_BLOCK_SEL_DIGLPFEA', + 48: 'DCO_DBG_BLOCK_SEL_DIGLPFEB', + 49: 'DCO_DBG_BLOCK_SEL_DIGLPA', + 50: 'DCO_DBG_BLOCK_SEL_DIGLPB', + 51: 'DCO_DBG_BLOCK_SEL_DPLPFEA', + 52: 'DCO_DBG_BLOCK_SEL_DPLPFEB', + 53: 'DCO_DBG_BLOCK_SEL_DPLPA', + 54: 'DCO_DBG_BLOCK_SEL_DPLPB', +} +DCO_DBG_BLOCK_SEL_DCO = 0 +DCO_DBG_BLOCK_SEL_ABM = 1 +DCO_DBG_BLOCK_SEL_DVO = 2 +DCO_DBG_BLOCK_SEL_DAC = 3 +DCO_DBG_BLOCK_SEL_MVP = 4 +DCO_DBG_BLOCK_SEL_FMT0 = 5 +DCO_DBG_BLOCK_SEL_FMT1 = 6 +DCO_DBG_BLOCK_SEL_FMT2 = 7 +DCO_DBG_BLOCK_SEL_FMT3 = 8 +DCO_DBG_BLOCK_SEL_FMT4 = 9 +DCO_DBG_BLOCK_SEL_FMT5 = 10 +DCO_DBG_BLOCK_SEL_DIGFE_A = 11 +DCO_DBG_BLOCK_SEL_DIGFE_B = 12 +DCO_DBG_BLOCK_SEL_DIGFE_C = 13 +DCO_DBG_BLOCK_SEL_DIGFE_D = 14 +DCO_DBG_BLOCK_SEL_DIGFE_E = 15 +DCO_DBG_BLOCK_SEL_DIGFE_F = 16 +DCO_DBG_BLOCK_SEL_DIGFE_G = 17 +DCO_DBG_BLOCK_SEL_DIGA = 18 +DCO_DBG_BLOCK_SEL_DIGB = 19 +DCO_DBG_BLOCK_SEL_DIGC = 20 +DCO_DBG_BLOCK_SEL_DIGD = 21 +DCO_DBG_BLOCK_SEL_DIGE = 22 +DCO_DBG_BLOCK_SEL_DIGF = 23 +DCO_DBG_BLOCK_SEL_DIGG = 24 +DCO_DBG_BLOCK_SEL_DPFE_A = 25 +DCO_DBG_BLOCK_SEL_DPFE_B = 26 +DCO_DBG_BLOCK_SEL_DPFE_C = 27 +DCO_DBG_BLOCK_SEL_DPFE_D = 28 +DCO_DBG_BLOCK_SEL_DPFE_E = 29 +DCO_DBG_BLOCK_SEL_DPFE_F = 30 +DCO_DBG_BLOCK_SEL_DPFE_G = 31 +DCO_DBG_BLOCK_SEL_DPA = 32 +DCO_DBG_BLOCK_SEL_DPB = 33 +DCO_DBG_BLOCK_SEL_DPC = 34 +DCO_DBG_BLOCK_SEL_DPD = 35 +DCO_DBG_BLOCK_SEL_DPE = 36 +DCO_DBG_BLOCK_SEL_DPF = 37 +DCO_DBG_BLOCK_SEL_DPG = 38 +DCO_DBG_BLOCK_SEL_AUX0 = 39 +DCO_DBG_BLOCK_SEL_AUX1 = 40 +DCO_DBG_BLOCK_SEL_AUX2 = 41 +DCO_DBG_BLOCK_SEL_AUX3 = 42 +DCO_DBG_BLOCK_SEL_AUX4 = 43 +DCO_DBG_BLOCK_SEL_AUX5 = 44 +DCO_DBG_BLOCK_SEL_PERFMON_DCO = 45 +DCO_DBG_BLOCK_SEL_AUDIO_OUT = 46 +DCO_DBG_BLOCK_SEL_DIGLPFEA = 47 +DCO_DBG_BLOCK_SEL_DIGLPFEB = 48 +DCO_DBG_BLOCK_SEL_DIGLPA = 49 +DCO_DBG_BLOCK_SEL_DIGLPB = 50 +DCO_DBG_BLOCK_SEL_DPLPFEA = 51 +DCO_DBG_BLOCK_SEL_DPLPFEB = 52 +DCO_DBG_BLOCK_SEL_DPLPA = 53 +DCO_DBG_BLOCK_SEL_DPLPB = 54 +DCO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE' +DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { + 0: 'DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 1: 'DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', +} +DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 +DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 +DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT420_MEMORY_SOURCE_SEL' +FMT420_MEMORY_SOURCE_SEL__enumvalues = { + 0: 'FMT420_MEMORY_SOURCE_SEL_FMT0', + 1: 'FMT420_MEMORY_SOURCE_SEL_FMT1', + 2: 'FMT420_MEMORY_SOURCE_SEL_FMT2', + 3: 'FMT420_MEMORY_SOURCE_SEL_FMT3', + 4: 'FMT420_MEMORY_SOURCE_SEL_FMT4', + 5: 'FMT420_MEMORY_SOURCE_SEL_FMT5', + 6: 'FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED', +} +FMT420_MEMORY_SOURCE_SEL_FMT0 = 0 +FMT420_MEMORY_SOURCE_SEL_FMT1 = 1 +FMT420_MEMORY_SOURCE_SEL_FMT2 = 2 +FMT420_MEMORY_SOURCE_SEL_FMT3 = 3 +FMT420_MEMORY_SOURCE_SEL_FMT4 = 4 +FMT420_MEMORY_SOURCE_SEL_FMT5 = 5 +FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED = 6 +FMT420_MEMORY_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_GO' +DOUT_I2C_CONTROL_GO__enumvalues = { + 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 1: 'DOUT_I2C_CONTROL_START_TRANSFER', +} +DOUT_I2C_CONTROL_STOP_TRANSFER = 0 +DOUT_I2C_CONTROL_START_TRANSFER = 1 +DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' +DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', +} +DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 +DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 +DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' +DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 1: 'DOUT_I2C_CONTROL__SEND_RESET', +} +DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 +DOUT_I2C_CONTROL__SEND_RESET = 1 +DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' +DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', +} +DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 +DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 +DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' +DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', + 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', + 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', + 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', + 4: 'DOUT_I2C_CONTROL_SELECT_DDC5', + 5: 'DOUT_I2C_CONTROL_SELECT_DDC6', + 6: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', +} +DOUT_I2C_CONTROL_SELECT_DDC1 = 0 +DOUT_I2C_CONTROL_SELECT_DDC2 = 1 +DOUT_I2C_CONTROL_SELECT_DDC3 = 2 +DOUT_I2C_CONTROL_SELECT_DDC4 = 3 +DOUT_I2C_CONTROL_SELECT_DDC5 = 4 +DOUT_I2C_CONTROL_SELECT_DDC6 = 5 +DOUT_I2C_CONTROL_SELECT_DDCVGA = 6 +DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' +DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_TRANS0', + 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', +} +DOUT_I2C_CONTROL_TRANS0 = 0 +DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 +DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL' +DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG', + 1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', +} +DOUT_I2C_CONTROL_NORMAL_DEBUG = 0 +DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1 +DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' +DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', +} +DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 +DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 +DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 +DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 +DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', +} +DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 +DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' +DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', +} +DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 +DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 +DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', +} +DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 +DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', +} +DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 +DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ACK' +DOUT_I2C_ACK__enumvalues = { + 0: 'DOUT_I2C_NO_ACK', + 1: 'DOUT_I2C_ACK_TO_CLEAN', +} +DOUT_I2C_NO_ACK = 0 +DOUT_I2C_ACK_TO_CLEAN = 1 +DOUT_I2C_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' +DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { + 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', +} +DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 +DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 +DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 +DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 +DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', +} +DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 +DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', +} +DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' +DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { + 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', +} +DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 +DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 +DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' +DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { + 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 1: 'DOUT_I2C_DATA__INDEX_WRITE', +} +DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 +DOUT_I2C_DATA__INDEX_WRITE = 1 +DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', +} +DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 +DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { + 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', +} +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'FBC_IDLE_MASK_MASK_BITS' +FBC_IDLE_MASK_MASK_BITS__enumvalues = { + 0: 'FBC_IDLE_MASK_DISP_REG_UPDATE', + 1: 'FBC_IDLE_MASK_RESERVED1', + 2: 'FBC_IDLE_MASK_FBC_GRPH_COMP_EN', + 3: 'FBC_IDLE_MASK_FBC_MIN_COMPRESSION', + 4: 'FBC_IDLE_MASK_FBC_ALPHA_COMP_EN', + 5: 'FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN', + 6: 'FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF', + 7: 'FBC_IDLE_MASK_RESERVED7', + 8: 'FBC_IDLE_MASK_RESERVED8', + 9: 'FBC_IDLE_MASK_RESERVED9', + 10: 'FBC_IDLE_MASK_RESERVED10', + 11: 'FBC_IDLE_MASK_RESERVED11', + 12: 'FBC_IDLE_MASK_RESERVED12', + 13: 'FBC_IDLE_MASK_RESERVED13', + 14: 'FBC_IDLE_MASK_RESERVED14', + 15: 'FBC_IDLE_MASK_RESERVED15', + 16: 'FBC_IDLE_MASK_RESERVED16', + 17: 'FBC_IDLE_MASK_RESERVED17', + 18: 'FBC_IDLE_MASK_RESERVED18', + 19: 'FBC_IDLE_MASK_RESERVED19', + 20: 'FBC_IDLE_MASK_RESERVED20', + 21: 'FBC_IDLE_MASK_RESERVED21', + 22: 'FBC_IDLE_MASK_RESERVED22', + 23: 'FBC_IDLE_MASK_RESERVED23', + 24: 'FBC_IDLE_MASK_MC_HIT_REGION_0', + 25: 'FBC_IDLE_MASK_MC_HIT_REGION_1', + 26: 'FBC_IDLE_MASK_MC_HIT_REGION_2', + 27: 'FBC_IDLE_MASK_MC_HIT_REGION_3', + 28: 'FBC_IDLE_MASK_MC_WRITE', + 29: 'FBC_IDLE_MASK_RESERVED29', + 30: 'FBC_IDLE_MASK_RESERVED30', + 31: 'FBC_IDLE_MASK_RESERVED31', +} +FBC_IDLE_MASK_DISP_REG_UPDATE = 0 +FBC_IDLE_MASK_RESERVED1 = 1 +FBC_IDLE_MASK_FBC_GRPH_COMP_EN = 2 +FBC_IDLE_MASK_FBC_MIN_COMPRESSION = 3 +FBC_IDLE_MASK_FBC_ALPHA_COMP_EN = 4 +FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN = 5 +FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF = 6 +FBC_IDLE_MASK_RESERVED7 = 7 +FBC_IDLE_MASK_RESERVED8 = 8 +FBC_IDLE_MASK_RESERVED9 = 9 +FBC_IDLE_MASK_RESERVED10 = 10 +FBC_IDLE_MASK_RESERVED11 = 11 +FBC_IDLE_MASK_RESERVED12 = 12 +FBC_IDLE_MASK_RESERVED13 = 13 +FBC_IDLE_MASK_RESERVED14 = 14 +FBC_IDLE_MASK_RESERVED15 = 15 +FBC_IDLE_MASK_RESERVED16 = 16 +FBC_IDLE_MASK_RESERVED17 = 17 +FBC_IDLE_MASK_RESERVED18 = 18 +FBC_IDLE_MASK_RESERVED19 = 19 +FBC_IDLE_MASK_RESERVED20 = 20 +FBC_IDLE_MASK_RESERVED21 = 21 +FBC_IDLE_MASK_RESERVED22 = 22 +FBC_IDLE_MASK_RESERVED23 = 23 +FBC_IDLE_MASK_MC_HIT_REGION_0 = 24 +FBC_IDLE_MASK_MC_HIT_REGION_1 = 25 +FBC_IDLE_MASK_MC_HIT_REGION_2 = 26 +FBC_IDLE_MASK_MC_HIT_REGION_3 = 27 +FBC_IDLE_MASK_MC_WRITE = 28 +FBC_IDLE_MASK_RESERVED29 = 29 +FBC_IDLE_MASK_RESERVED30 = 30 +FBC_IDLE_MASK_RESERVED31 = 31 +FBC_IDLE_MASK_MASK_BITS = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL' +DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL__enumvalues = { + 0: 'DPCSRX_BPHY_PCS_RX0_CLK', + 1: 'DPCSRX_BPHY_PCS_RX1_CLK', + 2: 'DPCSRX_BPHY_PCS_RX2_CLK', + 3: 'DPCSRX_BPHY_PCS_RX3_CLK', +} +DPCSRX_BPHY_PCS_RX0_CLK = 0 +DPCSRX_BPHY_PCS_RX1_CLK = 1 +DPCSRX_BPHY_PCS_RX2_CLK = 2 +DPCSRX_BPHY_PCS_RX3_CLK = 3 +DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSRX_DBG_CFGCLK_SEL' +DPCSRX_DBG_CFGCLK_SEL__enumvalues = { + 0: 'DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF', + 1: 'DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', + 2: 'DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE', + 3: 'DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER', +} +DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0 +DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 1 +DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE = 2 +DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER = 3 +DPCSRX_DBG_CFGCLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSRX_RX_SYMCLK_SEL' +DPCSRX_RX_SYMCLK_SEL__enumvalues = { + 0: 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT0', + 1: 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT1', + 2: 'DPCSRX_DBG_RX_SYMCLK_SEL_INT', +} +DPCSRX_DBG_RX_SYMCLK_SEL_OUT0 = 0 +DPCSRX_DBG_RX_SYMCLK_SEL_OUT1 = 1 +DPCSRX_DBG_RX_SYMCLK_SEL_INT = 2 +DPCSRX_RX_SYMCLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSTX_DBG_CFGCLK_SEL' +DPCSTX_DBG_CFGCLK_SEL__enumvalues = { + 0: 'DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF', + 1: 'DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', + 2: 'DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE', + 3: 'DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER', +} +DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0 +DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 1 +DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE = 2 +DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER = 3 +DPCSTX_DBG_CFGCLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSTX_TX_SYMCLK_SEL' +DPCSTX_TX_SYMCLK_SEL__enumvalues = { + 0: 'DPCSTX_DBG_TX_SYMCLK_SEL_IN0', + 1: 'DPCSTX_DBG_TX_SYMCLK_SEL_IN1', + 2: 'DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR', +} +DPCSTX_DBG_TX_SYMCLK_SEL_IN0 = 0 +DPCSTX_DBG_TX_SYMCLK_SEL_IN1 = 1 +DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR = 2 +DPCSTX_TX_SYMCLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPCSTX_TX_SYMCLK_DIV2_SEL' +DPCSTX_TX_SYMCLK_DIV2_SEL__enumvalues = { + 0: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0', + 1: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1', + 2: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2', + 3: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3', + 4: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD', + 5: 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT', +} +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0 = 0 +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1 = 1 +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2 = 2 +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3 = 3 +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD = 4 +DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT = 5 +DPCSTX_TX_SYMCLK_DIV2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceNumber' +SurfaceNumber__enumvalues = { + 0: 'NUMBER_UNORM', + 1: 'NUMBER_SNORM', + 2: 'NUMBER_USCALED', + 3: 'NUMBER_SSCALED', + 4: 'NUMBER_UINT', + 5: 'NUMBER_SINT', + 6: 'NUMBER_SRGB', + 7: 'NUMBER_FLOAT', +} +NUMBER_UNORM = 0 +NUMBER_SNORM = 1 +NUMBER_USCALED = 2 +NUMBER_SSCALED = 3 +NUMBER_UINT = 4 +NUMBER_SINT = 5 +NUMBER_SRGB = 6 +NUMBER_FLOAT = 7 +SurfaceNumber = ctypes.c_uint32 # enum + +# values for enumeration 'SurfaceSwap' +SurfaceSwap__enumvalues = { + 0: 'SWAP_STD', + 1: 'SWAP_ALT', + 2: 'SWAP_STD_REV', + 3: 'SWAP_ALT_REV', +} +SWAP_STD = 0 +SWAP_ALT = 1 +SWAP_STD_REV = 2 +SWAP_ALT_REV = 3 +SurfaceSwap = ctypes.c_uint32 # enum + +# values for enumeration 'CBMode' +CBMode__enumvalues = { + 0: 'CB_DISABLE', + 1: 'CB_NORMAL', + 2: 'CB_ELIMINATE_FAST_CLEAR', + 3: 'CB_RESOLVE', + 4: 'CB_DECOMPRESS', + 5: 'CB_FMASK_DECOMPRESS', + 6: 'CB_DCC_DECOMPRESS', +} +CB_DISABLE = 0 +CB_NORMAL = 1 +CB_ELIMINATE_FAST_CLEAR = 2 +CB_RESOLVE = 3 +CB_DECOMPRESS = 4 +CB_FMASK_DECOMPRESS = 5 +CB_DCC_DECOMPRESS = 6 +CBMode = ctypes.c_uint32 # enum + +# values for enumeration 'RoundMode' +RoundMode__enumvalues = { + 0: 'ROUND_BY_HALF', + 1: 'ROUND_TRUNCATE', +} +ROUND_BY_HALF = 0 +ROUND_TRUNCATE = 1 +RoundMode = ctypes.c_uint32 # enum + +# values for enumeration 'SourceFormat' +SourceFormat__enumvalues = { + 0: 'EXPORT_4C_32BPC', + 1: 'EXPORT_4C_16BPC', + 2: 'EXPORT_2C_32BPC_GR', + 3: 'EXPORT_2C_32BPC_AR', +} +EXPORT_4C_32BPC = 0 +EXPORT_4C_16BPC = 1 +EXPORT_2C_32BPC_GR = 2 +EXPORT_2C_32BPC_AR = 3 +SourceFormat = ctypes.c_uint32 # enum + +# values for enumeration 'BlendOp' +BlendOp__enumvalues = { + 0: 'BLEND_ZERO', + 1: 'BLEND_ONE', + 2: 'BLEND_SRC_COLOR', + 3: 'BLEND_ONE_MINUS_SRC_COLOR', + 4: 'BLEND_SRC_ALPHA', + 5: 'BLEND_ONE_MINUS_SRC_ALPHA', + 6: 'BLEND_DST_ALPHA', + 7: 'BLEND_ONE_MINUS_DST_ALPHA', + 8: 'BLEND_DST_COLOR', + 9: 'BLEND_ONE_MINUS_DST_COLOR', + 10: 'BLEND_SRC_ALPHA_SATURATE', + 11: 'BLEND_BOTH_SRC_ALPHA', + 12: 'BLEND_BOTH_INV_SRC_ALPHA', + 13: 'BLEND_CONSTANT_COLOR', + 14: 'BLEND_ONE_MINUS_CONSTANT_COLOR', + 15: 'BLEND_SRC1_COLOR', + 16: 'BLEND_INV_SRC1_COLOR', + 17: 'BLEND_SRC1_ALPHA', + 18: 'BLEND_INV_SRC1_ALPHA', + 19: 'BLEND_CONSTANT_ALPHA', + 20: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', +} +BLEND_ZERO = 0 +BLEND_ONE = 1 +BLEND_SRC_COLOR = 2 +BLEND_ONE_MINUS_SRC_COLOR = 3 +BLEND_SRC_ALPHA = 4 +BLEND_ONE_MINUS_SRC_ALPHA = 5 +BLEND_DST_ALPHA = 6 +BLEND_ONE_MINUS_DST_ALPHA = 7 +BLEND_DST_COLOR = 8 +BLEND_ONE_MINUS_DST_COLOR = 9 +BLEND_SRC_ALPHA_SATURATE = 10 +BLEND_BOTH_SRC_ALPHA = 11 +BLEND_BOTH_INV_SRC_ALPHA = 12 +BLEND_CONSTANT_COLOR = 13 +BLEND_ONE_MINUS_CONSTANT_COLOR = 14 +BLEND_SRC1_COLOR = 15 +BLEND_INV_SRC1_COLOR = 16 +BLEND_SRC1_ALPHA = 17 +BLEND_INV_SRC1_ALPHA = 18 +BLEND_CONSTANT_ALPHA = 19 +BLEND_ONE_MINUS_CONSTANT_ALPHA = 20 +BlendOp = ctypes.c_uint32 # enum +GL__ZERO = BLEND_ZERO # macro +GL__ONE = BLEND_ONE # macro +GL__SRC_COLOR = BLEND_SRC_COLOR # macro +GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro +GL__DST_COLOR = BLEND_DST_COLOR # macro +GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro +GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro +GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro +GL__DST_ALPHA = BLEND_DST_ALPHA # macro +GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro +GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro +GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro +GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro +GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro +GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro + +# values for enumeration 'CombFunc' +CombFunc__enumvalues = { + 0: 'COMB_DST_PLUS_SRC', + 1: 'COMB_SRC_MINUS_DST', + 2: 'COMB_MIN_DST_SRC', + 3: 'COMB_MAX_DST_SRC', + 4: 'COMB_DST_MINUS_SRC', +} +COMB_DST_PLUS_SRC = 0 +COMB_SRC_MINUS_DST = 1 +COMB_MIN_DST_SRC = 2 +COMB_MAX_DST_SRC = 3 +COMB_DST_MINUS_SRC = 4 +CombFunc = ctypes.c_uint32 # enum + +# values for enumeration 'BlendOpt' +BlendOpt__enumvalues = { + 0: 'FORCE_OPT_AUTO', + 1: 'FORCE_OPT_DISABLE', + 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', + 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', + 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', +} +FORCE_OPT_AUTO = 0 +FORCE_OPT_DISABLE = 1 +FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 +FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 +FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 +FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 +FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 +FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 +BlendOpt = ctypes.c_uint32 # enum + +# values for enumeration 'CmaskCode' +CmaskCode__enumvalues = { + 0: 'CMASK_CLR00_F0', + 1: 'CMASK_CLR00_F1', + 2: 'CMASK_CLR00_F2', + 3: 'CMASK_CLR00_FX', + 4: 'CMASK_CLR01_F0', + 5: 'CMASK_CLR01_F1', + 6: 'CMASK_CLR01_F2', + 7: 'CMASK_CLR01_FX', + 8: 'CMASK_CLR10_F0', + 9: 'CMASK_CLR10_F1', + 10: 'CMASK_CLR10_F2', + 11: 'CMASK_CLR10_FX', + 12: 'CMASK_CLR11_F0', + 13: 'CMASK_CLR11_F1', + 14: 'CMASK_CLR11_F2', + 15: 'CMASK_CLR11_FX', +} +CMASK_CLR00_F0 = 0 +CMASK_CLR00_F1 = 1 +CMASK_CLR00_F2 = 2 +CMASK_CLR00_FX = 3 +CMASK_CLR01_F0 = 4 +CMASK_CLR01_F1 = 5 +CMASK_CLR01_F2 = 6 +CMASK_CLR01_FX = 7 +CMASK_CLR10_F0 = 8 +CMASK_CLR10_F1 = 9 +CMASK_CLR10_F2 = 10 +CMASK_CLR10_FX = 11 +CMASK_CLR11_F0 = 12 +CMASK_CLR11_F1 = 13 +CMASK_CLR11_F2 = 14 +CMASK_CLR11_FX = 15 +CmaskCode = ctypes.c_uint32 # enum + +# values for enumeration 'CmaskAddr' +CmaskAddr__enumvalues = { + 0: 'CMASK_ADDR_TILED', + 1: 'CMASK_ADDR_LINEAR', + 2: 'CMASK_ADDR_COMPATIBLE', +} +CMASK_ADDR_TILED = 0 +CMASK_ADDR_LINEAR = 1 +CMASK_ADDR_COMPATIBLE = 2 +CmaskAddr = ctypes.c_uint32 # enum + +# values for enumeration 'MemArbMode' +MemArbMode__enumvalues = { + 0: 'MEM_ARB_MODE_FIXED', + 1: 'MEM_ARB_MODE_AGE', + 2: 'MEM_ARB_MODE_WEIGHT', + 3: 'MEM_ARB_MODE_BOTH', +} +MEM_ARB_MODE_FIXED = 0 +MEM_ARB_MODE_AGE = 1 +MEM_ARB_MODE_WEIGHT = 2 +MEM_ARB_MODE_BOTH = 3 +MemArbMode = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfSel' +CBPerfSel__enumvalues = { + 0: 'CB_PERF_SEL_NONE', + 1: 'CB_PERF_SEL_BUSY', + 2: 'CB_PERF_SEL_CORE_SCLK_VLD', + 3: 'CB_PERF_SEL_REG_SCLK0_VLD', + 4: 'CB_PERF_SEL_REG_SCLK1_VLD', + 5: 'CB_PERF_SEL_DRAWN_QUAD', + 6: 'CB_PERF_SEL_DRAWN_PIXEL', + 7: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', + 8: 'CB_PERF_SEL_DRAWN_TILE', + 9: 'CB_PERF_SEL_DB_CB_TILE_VALID_READY', + 10: 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB', + 11: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY', + 12: 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB', + 13: 'CB_PERF_SEL_CM_FC_TILE_VALID_READY', + 14: 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB', + 15: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY', + 16: 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB', + 17: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY', + 18: 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB', + 19: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY', + 20: 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB', + 21: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY', + 22: 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB', + 23: 'CB_PERF_SEL_LQUAD_NO_TILE', + 24: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R', + 25: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR', + 26: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR', + 27: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR', + 28: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR', + 29: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR', + 30: 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR', + 31: 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT', + 32: 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID', + 33: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK', + 34: 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK', + 35: 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL', + 36: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY', + 37: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB', + 38: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY', + 39: 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB', + 40: 'CB_PERF_SEL_FOP_IN_VALID_READY', + 41: 'CB_PERF_SEL_FOP_IN_VALID_READYB', + 42: 'CB_PERF_SEL_FOP_IN_VALIDB_READY', + 43: 'CB_PERF_SEL_FOP_IN_VALIDB_READYB', + 44: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY', + 45: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB', + 46: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY', + 47: 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB', + 48: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY', + 49: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB', + 50: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY', + 51: 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB', + 52: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY', + 53: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB', + 54: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY', + 55: 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB', + 56: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY', + 57: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB', + 58: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY', + 59: 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB', + 60: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY', + 61: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB', + 62: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY', + 63: 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB', + 64: 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID', + 65: 'CB_PERF_SEL_CM_CACHE_HIT', + 66: 'CB_PERF_SEL_CM_CACHE_TAG_MISS', + 67: 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', + 68: 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL', + 69: 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 70: 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL', + 71: 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 72: 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL', + 73: 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL', + 74: 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL', + 75: 'CB_PERF_SEL_CM_CACHE_STALL', + 76: 'CB_PERF_SEL_CM_CACHE_FLUSH', + 77: 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED', + 78: 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED', + 79: 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED', + 80: 'CB_PERF_SEL_FC_CACHE_HIT', + 81: 'CB_PERF_SEL_FC_CACHE_TAG_MISS', + 82: 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', + 83: 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL', + 84: 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 85: 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL', + 86: 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 87: 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL', + 88: 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL', + 89: 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL', + 90: 'CB_PERF_SEL_FC_CACHE_STALL', + 91: 'CB_PERF_SEL_FC_CACHE_FLUSH', + 92: 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED', + 93: 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED', + 94: 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED', + 95: 'CB_PERF_SEL_CC_CACHE_HIT', + 96: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 97: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', + 98: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', + 99: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 100: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', + 101: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 102: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 103: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 104: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 105: 'CB_PERF_SEL_CC_CACHE_STALL', + 106: 'CB_PERF_SEL_CC_CACHE_FLUSH', + 107: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', + 108: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 109: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', + 110: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 111: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 112: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY', + 113: 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB', + 114: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY', + 115: 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB', + 116: 'CB_PERF_SEL_CM_MC_WRITE_REQUEST', + 117: 'CB_PERF_SEL_FC_MC_WRITE_REQUEST', + 118: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', + 119: 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT', + 120: 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT', + 121: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', + 122: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY', + 123: 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB', + 124: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY', + 125: 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB', + 126: 'CB_PERF_SEL_CM_MC_READ_REQUEST', + 127: 'CB_PERF_SEL_FC_MC_READ_REQUEST', + 128: 'CB_PERF_SEL_CC_MC_READ_REQUEST', + 129: 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT', + 130: 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT', + 131: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', + 132: 'CB_PERF_SEL_CM_TQ_FULL', + 133: 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL', + 134: 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL', + 135: 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL', + 136: 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL', + 137: 'CB_PERF_SEL_FOP_FMASK_RAW_STALL', + 138: 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL', + 139: 'CB_PERF_SEL_CC_SF_FULL', + 140: 'CB_PERF_SEL_CC_RB_FULL', + 141: 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL', + 142: 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL', + 143: 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL', + 144: 'CB_PERF_SEL_EVENT', + 145: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 146: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 147: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 148: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 149: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 150: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 151: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 152: 'CB_PERF_SEL_CC_SURFACE_SYNC', + 153: 'CB_PERF_SEL_CMASK_READ_DATA_0xC', + 154: 'CB_PERF_SEL_CMASK_READ_DATA_0xD', + 155: 'CB_PERF_SEL_CMASK_READ_DATA_0xE', + 156: 'CB_PERF_SEL_CMASK_READ_DATA_0xF', + 157: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC', + 158: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD', + 159: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE', + 160: 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF', + 161: 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', + 162: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', + 163: 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT', + 164: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE', + 165: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE', + 166: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE', + 167: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE', + 168: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE', + 169: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE', + 170: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE', + 171: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE', + 172: 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE', + 173: 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE', + 174: 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE', + 175: 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE', + 176: 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE', + 177: 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE', + 178: 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE', + 179: 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE', + 180: 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT', + 181: 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS', + 182: 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS', + 183: 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS', + 184: 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS', + 185: 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS', + 186: 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS', + 187: 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT', + 188: 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS', + 189: 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS', + 190: 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS', + 191: 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS', + 192: 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS', + 193: 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS', + 194: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0', + 195: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1', + 196: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2', + 197: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3', + 198: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4', + 199: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5', + 200: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6', + 201: 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7', + 202: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0', + 203: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1', + 204: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2', + 205: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3', + 206: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4', + 207: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5', + 208: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6', + 209: 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7', + 210: 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST', + 211: 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS', + 212: 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS', + 213: 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 214: 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 215: 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED', + 216: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', + 217: 'CB_PERF_SEL_DRAWN_BUSY', + 218: 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY', + 219: 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY', + 220: 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY', + 221: 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY', + 222: 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED', + 223: 'CB_PERF_SEL_FC_SEQUENCER_CLEAR', + 224: 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR', + 225: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS', + 226: 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE', + 227: 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL', + 228: 'CB_PERF_SEL_FC_DOC_IS_STALLED', + 229: 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED', + 230: 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED', + 231: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS', + 232: 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT', + 233: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS', + 234: 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT', + 235: 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL', + 236: 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR', + 237: 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS', + 238: 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS', + 239: 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS', + 240: 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS', + 241: 'CB_PERF_SEL_FC_DCC_CACHE_HIT', + 242: 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS', + 243: 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS', + 244: 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL', + 245: 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 246: 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', + 247: 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 248: 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL', + 249: 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL', + 250: 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL', + 251: 'CB_PERF_SEL_FC_DCC_CACHE_STALL', + 252: 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', + 253: 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED', + 254: 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED', + 255: 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED', + 256: 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT', + 257: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST', + 258: 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT', + 259: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST', + 260: 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT', + 261: 'CB_PERF_SEL_CC_DCC_RDREQ_STALL', + 262: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN', + 263: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT', + 264: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN', + 265: 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT', + 266: 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR', + 267: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1', + 268: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2', + 269: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 270: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1', + 271: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1', + 272: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2', + 273: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1', + 274: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 275: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 276: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1', + 277: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2', + 278: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2', + 279: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2', + 280: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 281: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1', + 282: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1', + 283: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2', + 284: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3', + 285: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4', + 286: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1', + 287: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2', + 288: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3', + 289: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4', + 290: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1', + 291: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2', + 292: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3', + 293: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4', + 294: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1', + 295: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2', + 296: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3', + 297: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1', + 298: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2', + 299: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3', + 300: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4', + 301: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1', + 302: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2', + 303: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3', + 304: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4', + 305: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1', + 306: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2', + 307: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3', + 308: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4', + 309: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1', + 310: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2', + 311: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3', + 312: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1', + 313: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1', + 314: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1', + 315: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1', + 316: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1', + 317: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1', + 318: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1', + 319: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1', + 320: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2', + 321: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2', + 322: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2', + 323: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2', + 324: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2', + 325: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2', + 326: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2', + 327: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1', + 328: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1', + 329: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1', + 330: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1', + 331: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2', + 332: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2', + 333: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2', + 334: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2', + 335: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 336: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2', + 337: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2', + 338: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 339: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1', + 340: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1', + 341: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1', + 342: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1', + 343: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2', + 344: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3', + 345: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4', + 346: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5', + 347: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6', + 348: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0', + 349: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1', + 350: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1', + 351: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2', + 352: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3', + 353: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4', + 354: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5', + 355: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0', + 356: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1', + 357: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1', + 358: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1', + 359: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1', + 360: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1', + 361: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1', + 362: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1', + 363: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1', + 364: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1', + 365: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2', + 366: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2', + 367: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2', + 368: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2', + 369: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2', + 370: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2', + 371: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2', + 372: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1', + 373: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2', + 374: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3', + 375: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4', + 376: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5', + 377: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6', + 378: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7', + 379: 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED', + 380: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1', + 381: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1', + 382: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2', + 383: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3', + 384: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1', + 385: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2', + 386: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3', + 387: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4', + 388: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5', + 389: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1', + 390: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2', + 391: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3', + 392: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4', + 393: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5', + 394: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6', + 395: 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7', + 396: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', + 397: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', + 398: 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', + 399: 'CB_PERF_SEL_RBP_SPLIT_MICROTILE', + 400: 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK', + 401: 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK', + 402: 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING', + 403: 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS', + 404: 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD', +} +CB_PERF_SEL_NONE = 0 +CB_PERF_SEL_BUSY = 1 +CB_PERF_SEL_CORE_SCLK_VLD = 2 +CB_PERF_SEL_REG_SCLK0_VLD = 3 +CB_PERF_SEL_REG_SCLK1_VLD = 4 +CB_PERF_SEL_DRAWN_QUAD = 5 +CB_PERF_SEL_DRAWN_PIXEL = 6 +CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 7 +CB_PERF_SEL_DRAWN_TILE = 8 +CB_PERF_SEL_DB_CB_TILE_VALID_READY = 9 +CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 10 +CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 11 +CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 12 +CB_PERF_SEL_CM_FC_TILE_VALID_READY = 13 +CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 14 +CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 15 +CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 16 +CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 17 +CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 18 +CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 19 +CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 20 +CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 21 +CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 22 +CB_PERF_SEL_LQUAD_NO_TILE = 23 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 24 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 25 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 26 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 27 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 28 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 29 +CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 30 +CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 31 +CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 32 +CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 33 +CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 34 +CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 35 +CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 36 +CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 37 +CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 38 +CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 39 +CB_PERF_SEL_FOP_IN_VALID_READY = 40 +CB_PERF_SEL_FOP_IN_VALID_READYB = 41 +CB_PERF_SEL_FOP_IN_VALIDB_READY = 42 +CB_PERF_SEL_FOP_IN_VALIDB_READYB = 43 +CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 44 +CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 45 +CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 46 +CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 47 +CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 48 +CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 49 +CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 50 +CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 51 +CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 52 +CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 53 +CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 54 +CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 55 +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 56 +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 57 +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 58 +CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 59 +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 60 +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 61 +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 62 +CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 63 +CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 64 +CB_PERF_SEL_CM_CACHE_HIT = 65 +CB_PERF_SEL_CM_CACHE_TAG_MISS = 66 +CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 67 +CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 68 +CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 69 +CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 70 +CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 71 +CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 72 +CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 73 +CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 74 +CB_PERF_SEL_CM_CACHE_STALL = 75 +CB_PERF_SEL_CM_CACHE_FLUSH = 76 +CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 77 +CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 78 +CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 79 +CB_PERF_SEL_FC_CACHE_HIT = 80 +CB_PERF_SEL_FC_CACHE_TAG_MISS = 81 +CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 82 +CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 83 +CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 84 +CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 85 +CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 86 +CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 87 +CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 88 +CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 89 +CB_PERF_SEL_FC_CACHE_STALL = 90 +CB_PERF_SEL_FC_CACHE_FLUSH = 91 +CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 92 +CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 93 +CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 94 +CB_PERF_SEL_CC_CACHE_HIT = 95 +CB_PERF_SEL_CC_CACHE_TAG_MISS = 96 +CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 97 +CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 98 +CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 99 +CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 100 +CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 101 +CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 102 +CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 103 +CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 104 +CB_PERF_SEL_CC_CACHE_STALL = 105 +CB_PERF_SEL_CC_CACHE_FLUSH = 106 +CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 107 +CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 108 +CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 109 +CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 110 +CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 111 +CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 112 +CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 113 +CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 114 +CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 115 +CB_PERF_SEL_CM_MC_WRITE_REQUEST = 116 +CB_PERF_SEL_FC_MC_WRITE_REQUEST = 117 +CB_PERF_SEL_CC_MC_WRITE_REQUEST = 118 +CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 119 +CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 120 +CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 121 +CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 122 +CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 123 +CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 124 +CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 125 +CB_PERF_SEL_CM_MC_READ_REQUEST = 126 +CB_PERF_SEL_FC_MC_READ_REQUEST = 127 +CB_PERF_SEL_CC_MC_READ_REQUEST = 128 +CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 129 +CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 130 +CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 131 +CB_PERF_SEL_CM_TQ_FULL = 132 +CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 133 +CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 134 +CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 135 +CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 136 +CB_PERF_SEL_FOP_FMASK_RAW_STALL = 137 +CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 138 +CB_PERF_SEL_CC_SF_FULL = 139 +CB_PERF_SEL_CC_RB_FULL = 140 +CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 141 +CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 142 +CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 143 +CB_PERF_SEL_EVENT = 144 +CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 145 +CB_PERF_SEL_EVENT_CONTEXT_DONE = 146 +CB_PERF_SEL_EVENT_CACHE_FLUSH = 147 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 148 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 149 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 150 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 151 +CB_PERF_SEL_CC_SURFACE_SYNC = 152 +CB_PERF_SEL_CMASK_READ_DATA_0xC = 153 +CB_PERF_SEL_CMASK_READ_DATA_0xD = 154 +CB_PERF_SEL_CMASK_READ_DATA_0xE = 155 +CB_PERF_SEL_CMASK_READ_DATA_0xF = 156 +CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 157 +CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 158 +CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 159 +CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 160 +CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 161 +CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 162 +CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 163 +CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 164 +CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 165 +CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 166 +CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 167 +CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 168 +CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 169 +CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 170 +CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 171 +CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 172 +CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 173 +CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 174 +CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 175 +CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 176 +CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 177 +CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 178 +CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 179 +CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 180 +CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 181 +CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 182 +CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 183 +CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 184 +CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 185 +CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 186 +CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 187 +CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 188 +CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 189 +CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 190 +CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 191 +CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 192 +CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 193 +CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 194 +CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 195 +CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 196 +CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 197 +CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 198 +CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 199 +CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 200 +CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 201 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 202 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 203 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 204 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 205 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 206 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 207 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 208 +CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 209 +CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 210 +CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 211 +CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 212 +CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 213 +CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 214 +CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 215 +CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 216 +CB_PERF_SEL_DRAWN_BUSY = 217 +CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 218 +CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 219 +CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 220 +CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 221 +CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 222 +CB_PERF_SEL_FC_SEQUENCER_CLEAR = 223 +CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 224 +CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 225 +CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 226 +CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 227 +CB_PERF_SEL_FC_DOC_IS_STALLED = 228 +CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 229 +CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 230 +CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 231 +CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 232 +CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 233 +CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 234 +CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 235 +CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 236 +CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 237 +CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 238 +CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 239 +CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 240 +CB_PERF_SEL_FC_DCC_CACHE_HIT = 241 +CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 242 +CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 243 +CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 244 +CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 245 +CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 246 +CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 247 +CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 248 +CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 249 +CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 250 +CB_PERF_SEL_FC_DCC_CACHE_STALL = 251 +CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 252 +CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 253 +CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 254 +CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 255 +CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 256 +CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 257 +CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 258 +CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 259 +CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 260 +CB_PERF_SEL_CC_DCC_RDREQ_STALL = 261 +CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 262 +CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 263 +CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 264 +CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 265 +CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 266 +CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 267 +CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 268 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 269 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 270 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 271 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 272 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 273 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 274 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 275 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 276 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 277 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 278 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 279 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 280 +CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 281 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 282 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 283 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 284 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 285 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 286 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 287 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 288 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 289 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 290 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 291 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 292 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 293 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 294 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 295 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 296 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 297 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 298 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 299 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 300 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 301 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 302 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 303 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 304 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 305 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 306 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 307 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 308 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 309 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 310 +CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 311 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 312 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 313 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 314 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 315 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 316 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 317 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 318 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 319 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 320 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 321 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 322 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 323 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 324 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 325 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 326 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 327 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 328 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 329 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 330 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 331 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 332 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 333 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 334 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 335 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 336 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 337 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 338 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 339 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 340 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 341 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 342 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 343 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 344 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 345 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 346 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 347 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 348 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 349 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 350 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 351 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 352 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 353 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 354 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 355 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 356 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 357 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 358 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 359 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 360 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 361 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 362 +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 363 +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 364 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 365 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 366 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 367 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 368 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 369 +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 370 +CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 371 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 372 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 373 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 374 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 375 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 376 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 377 +CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 378 +CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 379 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 380 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 381 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 382 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 383 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 384 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 385 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 386 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 387 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 388 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 389 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 390 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 391 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 392 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 393 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 394 +CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 395 +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 396 +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 397 +CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 398 +CB_PERF_SEL_RBP_SPLIT_MICROTILE = 399 +CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 400 +CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 401 +CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 402 +CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 403 +CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 404 +CBPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfOpFilterSel' +CBPerfOpFilterSel__enumvalues = { + 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', +} +CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 +CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 +CB_PERF_OP_FILTER_SEL_RESOLVE = 2 +CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 +CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 +CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 +CBPerfOpFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfClearFilterSel' +CBPerfClearFilterSel__enumvalues = { + 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', +} +CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 +CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 +CBPerfClearFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP_MASKS' +TC_OP_MASKS__enumvalues = { + 8: 'TC_OP_MASK_FLUSH_DENROM', + 32: 'TC_OP_MASK_64', + 64: 'TC_OP_MASK_NO_RTN', +} +TC_OP_MASK_FLUSH_DENROM = 8 +TC_OP_MASK_64 = 32 +TC_OP_MASK_NO_RTN = 64 +TC_OP_MASKS = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP' +TC_OP__enumvalues = { + 0: 'TC_OP_READ', + 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', + 2: 'TC_OP_ATOMIC_FMIN_RTN_32', + 3: 'TC_OP_ATOMIC_FMAX_RTN_32', + 4: 'TC_OP_RESERVED_FOP_RTN_32_0', + 5: 'TC_OP_RESERVED_FOP_RTN_32_1', + 6: 'TC_OP_RESERVED_FOP_RTN_32_2', + 7: 'TC_OP_ATOMIC_SWAP_RTN_32', + 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', + 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 12: 'TC_OP_PROBE_FILTER', + 13: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', + 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 15: 'TC_OP_ATOMIC_ADD_RTN_32', + 16: 'TC_OP_ATOMIC_SUB_RTN_32', + 17: 'TC_OP_ATOMIC_SMIN_RTN_32', + 18: 'TC_OP_ATOMIC_UMIN_RTN_32', + 19: 'TC_OP_ATOMIC_SMAX_RTN_32', + 20: 'TC_OP_ATOMIC_UMAX_RTN_32', + 21: 'TC_OP_ATOMIC_AND_RTN_32', + 22: 'TC_OP_ATOMIC_OR_RTN_32', + 23: 'TC_OP_ATOMIC_XOR_RTN_32', + 24: 'TC_OP_ATOMIC_INC_RTN_32', + 25: 'TC_OP_ATOMIC_DEC_RTN_32', + 26: 'TC_OP_WBINVL1_VOL', + 27: 'TC_OP_WBINVL1_SD', + 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 32: 'TC_OP_WRITE', + 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 34: 'TC_OP_ATOMIC_FMIN_RTN_64', + 35: 'TC_OP_ATOMIC_FMAX_RTN_64', + 36: 'TC_OP_RESERVED_FOP_RTN_64_0', + 37: 'TC_OP_RESERVED_FOP_RTN_64_1', + 38: 'TC_OP_RESERVED_FOP_RTN_64_2', + 39: 'TC_OP_ATOMIC_SWAP_RTN_64', + 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', + 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 44: 'TC_OP_WBINVL2_SD', + 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 47: 'TC_OP_ATOMIC_ADD_RTN_64', + 48: 'TC_OP_ATOMIC_SUB_RTN_64', + 49: 'TC_OP_ATOMIC_SMIN_RTN_64', + 50: 'TC_OP_ATOMIC_UMIN_RTN_64', + 51: 'TC_OP_ATOMIC_SMAX_RTN_64', + 52: 'TC_OP_ATOMIC_UMAX_RTN_64', + 53: 'TC_OP_ATOMIC_AND_RTN_64', + 54: 'TC_OP_ATOMIC_OR_RTN_64', + 55: 'TC_OP_ATOMIC_XOR_RTN_64', + 56: 'TC_OP_ATOMIC_INC_RTN_64', + 57: 'TC_OP_ATOMIC_DEC_RTN_64', + 58: 'TC_OP_WBL2_NC', + 59: 'TC_OP_WBL2_WC', + 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', + 64: 'TC_OP_WBINVL1', + 65: 'TC_OP_ATOMIC_FCMPSWAP_32', + 66: 'TC_OP_ATOMIC_FMIN_32', + 67: 'TC_OP_ATOMIC_FMAX_32', + 68: 'TC_OP_RESERVED_FOP_32_0', + 69: 'TC_OP_RESERVED_FOP_32_1', + 70: 'TC_OP_RESERVED_FOP_32_2', + 71: 'TC_OP_ATOMIC_SWAP_32', + 72: 'TC_OP_ATOMIC_CMPSWAP_32', + 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 76: 'TC_OP_INV_METADATA', + 77: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1', + 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 79: 'TC_OP_ATOMIC_ADD_32', + 80: 'TC_OP_ATOMIC_SUB_32', + 81: 'TC_OP_ATOMIC_SMIN_32', + 82: 'TC_OP_ATOMIC_UMIN_32', + 83: 'TC_OP_ATOMIC_SMAX_32', + 84: 'TC_OP_ATOMIC_UMAX_32', + 85: 'TC_OP_ATOMIC_AND_32', + 86: 'TC_OP_ATOMIC_OR_32', + 87: 'TC_OP_ATOMIC_XOR_32', + 88: 'TC_OP_ATOMIC_INC_32', + 89: 'TC_OP_ATOMIC_DEC_32', + 90: 'TC_OP_INVL2_NC', + 91: 'TC_OP_NOP_RTN0', + 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', + 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', + 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', + 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', + 96: 'TC_OP_WBINVL2', + 97: 'TC_OP_ATOMIC_FCMPSWAP_64', + 98: 'TC_OP_ATOMIC_FMIN_64', + 99: 'TC_OP_ATOMIC_FMAX_64', + 100: 'TC_OP_RESERVED_FOP_64_0', + 101: 'TC_OP_RESERVED_FOP_64_1', + 102: 'TC_OP_RESERVED_FOP_64_2', + 103: 'TC_OP_ATOMIC_SWAP_64', + 104: 'TC_OP_ATOMIC_CMPSWAP_64', + 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 111: 'TC_OP_ATOMIC_ADD_64', + 112: 'TC_OP_ATOMIC_SUB_64', + 113: 'TC_OP_ATOMIC_SMIN_64', + 114: 'TC_OP_ATOMIC_UMIN_64', + 115: 'TC_OP_ATOMIC_SMAX_64', + 116: 'TC_OP_ATOMIC_UMAX_64', + 117: 'TC_OP_ATOMIC_AND_64', + 118: 'TC_OP_ATOMIC_OR_64', + 119: 'TC_OP_ATOMIC_XOR_64', + 120: 'TC_OP_ATOMIC_INC_64', + 121: 'TC_OP_ATOMIC_DEC_64', + 122: 'TC_OP_WBINVL2_NC', + 123: 'TC_OP_NOP_ACK', + 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', + 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', + 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', + 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', +} +TC_OP_READ = 0 +TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 +TC_OP_ATOMIC_FMIN_RTN_32 = 2 +TC_OP_ATOMIC_FMAX_RTN_32 = 3 +TC_OP_RESERVED_FOP_RTN_32_0 = 4 +TC_OP_RESERVED_FOP_RTN_32_1 = 5 +TC_OP_RESERVED_FOP_RTN_32_2 = 6 +TC_OP_ATOMIC_SWAP_RTN_32 = 7 +TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 +TC_OP_PROBE_FILTER = 12 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 13 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 +TC_OP_ATOMIC_ADD_RTN_32 = 15 +TC_OP_ATOMIC_SUB_RTN_32 = 16 +TC_OP_ATOMIC_SMIN_RTN_32 = 17 +TC_OP_ATOMIC_UMIN_RTN_32 = 18 +TC_OP_ATOMIC_SMAX_RTN_32 = 19 +TC_OP_ATOMIC_UMAX_RTN_32 = 20 +TC_OP_ATOMIC_AND_RTN_32 = 21 +TC_OP_ATOMIC_OR_RTN_32 = 22 +TC_OP_ATOMIC_XOR_RTN_32 = 23 +TC_OP_ATOMIC_INC_RTN_32 = 24 +TC_OP_ATOMIC_DEC_RTN_32 = 25 +TC_OP_WBINVL1_VOL = 26 +TC_OP_WBINVL1_SD = 27 +TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 +TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 +TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 +TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 +TC_OP_WRITE = 32 +TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 +TC_OP_ATOMIC_FMIN_RTN_64 = 34 +TC_OP_ATOMIC_FMAX_RTN_64 = 35 +TC_OP_RESERVED_FOP_RTN_64_0 = 36 +TC_OP_RESERVED_FOP_RTN_64_1 = 37 +TC_OP_RESERVED_FOP_RTN_64_2 = 38 +TC_OP_ATOMIC_SWAP_RTN_64 = 39 +TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 +TC_OP_WBINVL2_SD = 44 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 +TC_OP_ATOMIC_ADD_RTN_64 = 47 +TC_OP_ATOMIC_SUB_RTN_64 = 48 +TC_OP_ATOMIC_SMIN_RTN_64 = 49 +TC_OP_ATOMIC_UMIN_RTN_64 = 50 +TC_OP_ATOMIC_SMAX_RTN_64 = 51 +TC_OP_ATOMIC_UMAX_RTN_64 = 52 +TC_OP_ATOMIC_AND_RTN_64 = 53 +TC_OP_ATOMIC_OR_RTN_64 = 54 +TC_OP_ATOMIC_XOR_RTN_64 = 55 +TC_OP_ATOMIC_INC_RTN_64 = 56 +TC_OP_ATOMIC_DEC_RTN_64 = 57 +TC_OP_WBL2_NC = 58 +TC_OP_WBL2_WC = 59 +TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 +TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 +TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 +TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 +TC_OP_WBINVL1 = 64 +TC_OP_ATOMIC_FCMPSWAP_32 = 65 +TC_OP_ATOMIC_FMIN_32 = 66 +TC_OP_ATOMIC_FMAX_32 = 67 +TC_OP_RESERVED_FOP_32_0 = 68 +TC_OP_RESERVED_FOP_32_1 = 69 +TC_OP_RESERVED_FOP_32_2 = 70 +TC_OP_ATOMIC_SWAP_32 = 71 +TC_OP_ATOMIC_CMPSWAP_32 = 72 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 +TC_OP_INV_METADATA = 76 +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 77 +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 +TC_OP_ATOMIC_ADD_32 = 79 +TC_OP_ATOMIC_SUB_32 = 80 +TC_OP_ATOMIC_SMIN_32 = 81 +TC_OP_ATOMIC_UMIN_32 = 82 +TC_OP_ATOMIC_SMAX_32 = 83 +TC_OP_ATOMIC_UMAX_32 = 84 +TC_OP_ATOMIC_AND_32 = 85 +TC_OP_ATOMIC_OR_32 = 86 +TC_OP_ATOMIC_XOR_32 = 87 +TC_OP_ATOMIC_INC_32 = 88 +TC_OP_ATOMIC_DEC_32 = 89 +TC_OP_INVL2_NC = 90 +TC_OP_NOP_RTN0 = 91 +TC_OP_RESERVED_NON_FLOAT_32_1 = 92 +TC_OP_RESERVED_NON_FLOAT_32_2 = 93 +TC_OP_RESERVED_NON_FLOAT_32_3 = 94 +TC_OP_RESERVED_NON_FLOAT_32_4 = 95 +TC_OP_WBINVL2 = 96 +TC_OP_ATOMIC_FCMPSWAP_64 = 97 +TC_OP_ATOMIC_FMIN_64 = 98 +TC_OP_ATOMIC_FMAX_64 = 99 +TC_OP_RESERVED_FOP_64_0 = 100 +TC_OP_RESERVED_FOP_64_1 = 101 +TC_OP_RESERVED_FOP_64_2 = 102 +TC_OP_ATOMIC_SWAP_64 = 103 +TC_OP_ATOMIC_CMPSWAP_64 = 104 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 +TC_OP_ATOMIC_ADD_64 = 111 +TC_OP_ATOMIC_SUB_64 = 112 +TC_OP_ATOMIC_SMIN_64 = 113 +TC_OP_ATOMIC_UMIN_64 = 114 +TC_OP_ATOMIC_SMAX_64 = 115 +TC_OP_ATOMIC_UMAX_64 = 116 +TC_OP_ATOMIC_AND_64 = 117 +TC_OP_ATOMIC_OR_64 = 118 +TC_OP_ATOMIC_XOR_64 = 119 +TC_OP_ATOMIC_INC_64 = 120 +TC_OP_ATOMIC_DEC_64 = 121 +TC_OP_WBINVL2_NC = 122 +TC_OP_NOP_ACK = 123 +TC_OP_RESERVED_NON_FLOAT_64_1 = 124 +TC_OP_RESERVED_NON_FLOAT_64_2 = 125 +TC_OP_RESERVED_NON_FLOAT_64_3 = 126 +TC_OP_RESERVED_NON_FLOAT_64_4 = 127 +TC_OP = ctypes.c_uint32 # enum + +# values for enumeration 'TC_CHUB_REQ_CREDITS_ENUM' +TC_CHUB_REQ_CREDITS_ENUM__enumvalues = { + 16: 'TC_CHUB_REQ_CREDITS', +} +TC_CHUB_REQ_CREDITS = 16 +TC_CHUB_REQ_CREDITS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CHUB_TC_RET_CREDITS_ENUM' +CHUB_TC_RET_CREDITS_ENUM__enumvalues = { + 32: 'CHUB_TC_RET_CREDITS', +} +CHUB_TC_RET_CREDITS = 32 +CHUB_TC_RET_CREDITS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'TC_NACKS' +TC_NACKS__enumvalues = { + 0: 'TC_NACK_NO_FAULT', + 1: 'TC_NACK_PAGE_FAULT', + 2: 'TC_NACK_PROTECTION_FAULT', + 3: 'TC_NACK_DATA_ERROR', +} +TC_NACK_NO_FAULT = 0 +TC_NACK_PAGE_FAULT = 1 +TC_NACK_PROTECTION_FAULT = 2 +TC_NACK_DATA_ERROR = 3 +TC_NACKS = ctypes.c_uint32 # enum + +# values for enumeration 'TC_EA_CID' +TC_EA_CID__enumvalues = { + 0: 'TC_EA_CID_RT', + 1: 'TC_EA_CID_FMASK', + 2: 'TC_EA_CID_DCC', + 3: 'TC_EA_CID_TCPMETA', + 4: 'TC_EA_CID_Z', + 5: 'TC_EA_CID_STENCIL', + 6: 'TC_EA_CID_HTILE', + 7: 'TC_EA_CID_MISC', + 8: 'TC_EA_CID_TCP', + 9: 'TC_EA_CID_SQC', + 10: 'TC_EA_CID_CPF', + 11: 'TC_EA_CID_CPG', + 12: 'TC_EA_CID_IA', + 13: 'TC_EA_CID_WD', + 14: 'TC_EA_CID_PA', + 15: 'TC_EA_CID_UTCL2_TPI', +} +TC_EA_CID_RT = 0 +TC_EA_CID_FMASK = 1 +TC_EA_CID_DCC = 2 +TC_EA_CID_TCPMETA = 3 +TC_EA_CID_Z = 4 +TC_EA_CID_STENCIL = 5 +TC_EA_CID_HTILE = 6 +TC_EA_CID_MISC = 7 +TC_EA_CID_TCP = 8 +TC_EA_CID_SQC = 9 +TC_EA_CID_CPF = 10 +TC_EA_CID_CPG = 11 +TC_EA_CID_IA = 12 +TC_EA_CID_WD = 13 +TC_EA_CID_PA = 14 +TC_EA_CID_UTCL2_TPI = 15 +TC_EA_CID = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SAMPLE_CNTL' +SPI_SAMPLE_CNTL__enumvalues = { + 0: 'CENTROIDS_ONLY', + 1: 'CENTERS_ONLY', + 2: 'CENTROIDS_AND_CENTERS', + 3: 'UNDEF', +} +CENTROIDS_ONLY = 0 +CENTERS_ONLY = 1 +CENTROIDS_AND_CENTERS = 2 +UNDEF = 3 +SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_FOG_MODE' +SPI_FOG_MODE__enumvalues = { + 0: 'SPI_FOG_NONE', + 1: 'SPI_FOG_EXP', + 2: 'SPI_FOG_EXP2', + 3: 'SPI_FOG_LINEAR', +} +SPI_FOG_NONE = 0 +SPI_FOG_EXP = 1 +SPI_FOG_EXP2 = 2 +SPI_FOG_LINEAR = 3 +SPI_FOG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' +SPI_PNT_SPRITE_OVERRIDE__enumvalues = { + 0: 'SPI_PNT_SPRITE_SEL_0', + 1: 'SPI_PNT_SPRITE_SEL_1', + 2: 'SPI_PNT_SPRITE_SEL_S', + 3: 'SPI_PNT_SPRITE_SEL_T', + 4: 'SPI_PNT_SPRITE_SEL_NONE', +} +SPI_PNT_SPRITE_SEL_0 = 0 +SPI_PNT_SPRITE_SEL_1 = 1 +SPI_PNT_SPRITE_SEL_S = 2 +SPI_PNT_SPRITE_SEL_T = 3 +SPI_PNT_SPRITE_SEL_NONE = 4 +SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PERFCNT_SEL' +SPI_PERFCNT_SEL__enumvalues = { + 0: 'SPI_PERF_VS_WINDOW_VALID', + 1: 'SPI_PERF_VS_BUSY', + 2: 'SPI_PERF_VS_FIRST_WAVE', + 3: 'SPI_PERF_VS_LAST_WAVE', + 4: 'SPI_PERF_VS_LSHS_DEALLOC', + 5: 'SPI_PERF_VS_PC_STALL', + 6: 'SPI_PERF_VS_POS0_STALL', + 7: 'SPI_PERF_VS_POS1_STALL', + 8: 'SPI_PERF_VS_CRAWLER_STALL', + 9: 'SPI_PERF_VS_EVENT_WAVE', + 10: 'SPI_PERF_VS_WAVE', + 11: 'SPI_PERF_VS_PERS_UPD_FULL0', + 12: 'SPI_PERF_VS_PERS_UPD_FULL1', + 13: 'SPI_PERF_VS_LATE_ALLOC_FULL', + 14: 'SPI_PERF_VS_FIRST_SUBGRP', + 15: 'SPI_PERF_VS_LAST_SUBGRP', + 16: 'SPI_PERF_GS_WINDOW_VALID', + 17: 'SPI_PERF_GS_BUSY', + 18: 'SPI_PERF_GS_CRAWLER_STALL', + 19: 'SPI_PERF_GS_EVENT_WAVE', + 20: 'SPI_PERF_GS_WAVE', + 21: 'SPI_PERF_GS_PERS_UPD_FULL0', + 22: 'SPI_PERF_GS_PERS_UPD_FULL1', + 23: 'SPI_PERF_GS_FIRST_SUBGRP', + 24: 'SPI_PERF_GS_LAST_SUBGRP', + 25: 'SPI_PERF_ES_WINDOW_VALID', + 26: 'SPI_PERF_ES_BUSY', + 27: 'SPI_PERF_ES_CRAWLER_STALL', + 28: 'SPI_PERF_ES_FIRST_WAVE', + 29: 'SPI_PERF_ES_LAST_WAVE', + 30: 'SPI_PERF_ES_LSHS_DEALLOC', + 31: 'SPI_PERF_ES_EVENT_WAVE', + 32: 'SPI_PERF_ES_WAVE', + 33: 'SPI_PERF_ES_PERS_UPD_FULL0', + 34: 'SPI_PERF_ES_PERS_UPD_FULL1', + 35: 'SPI_PERF_ES_FIRST_SUBGRP', + 36: 'SPI_PERF_ES_LAST_SUBGRP', + 37: 'SPI_PERF_HS_WINDOW_VALID', + 38: 'SPI_PERF_HS_BUSY', + 39: 'SPI_PERF_HS_CRAWLER_STALL', + 40: 'SPI_PERF_HS_FIRST_WAVE', + 41: 'SPI_PERF_HS_LAST_WAVE', + 42: 'SPI_PERF_HS_LSHS_DEALLOC', + 43: 'SPI_PERF_HS_EVENT_WAVE', + 44: 'SPI_PERF_HS_WAVE', + 45: 'SPI_PERF_HS_PERS_UPD_FULL0', + 46: 'SPI_PERF_HS_PERS_UPD_FULL1', + 47: 'SPI_PERF_LS_WINDOW_VALID', + 48: 'SPI_PERF_LS_BUSY', + 49: 'SPI_PERF_LS_CRAWLER_STALL', + 50: 'SPI_PERF_LS_FIRST_WAVE', + 51: 'SPI_PERF_LS_LAST_WAVE', + 52: 'SPI_PERF_OFFCHIP_LDS_STALL_LS', + 53: 'SPI_PERF_LS_EVENT_WAVE', + 54: 'SPI_PERF_LS_WAVE', + 55: 'SPI_PERF_LS_PERS_UPD_FULL0', + 56: 'SPI_PERF_LS_PERS_UPD_FULL1', + 57: 'SPI_PERF_CSG_WINDOW_VALID', + 58: 'SPI_PERF_CSG_BUSY', + 59: 'SPI_PERF_CSG_NUM_THREADGROUPS', + 60: 'SPI_PERF_CSG_CRAWLER_STALL', + 61: 'SPI_PERF_CSG_EVENT_WAVE', + 62: 'SPI_PERF_CSG_WAVE', + 63: 'SPI_PERF_CSN_WINDOW_VALID', + 64: 'SPI_PERF_CSN_BUSY', + 65: 'SPI_PERF_CSN_NUM_THREADGROUPS', + 66: 'SPI_PERF_CSN_CRAWLER_STALL', + 67: 'SPI_PERF_CSN_EVENT_WAVE', + 68: 'SPI_PERF_CSN_WAVE', + 69: 'SPI_PERF_PS_CTL_WINDOW_VALID', + 70: 'SPI_PERF_PS_CTL_BUSY', + 71: 'SPI_PERF_PS_CTL_ACTIVE', + 72: 'SPI_PERF_PS_CTL_DEALLOC_BIN0', + 73: 'SPI_PERF_PS_CTL_FPOS_BIN1_STALL', + 74: 'SPI_PERF_PS_CTL_EVENT_WAVE', + 75: 'SPI_PERF_PS_CTL_WAVE', + 76: 'SPI_PERF_PS_CTL_OPT_WAVE', + 77: 'SPI_PERF_PS_CTL_PASS_BIN0', + 78: 'SPI_PERF_PS_CTL_PASS_BIN1', + 79: 'SPI_PERF_PS_CTL_FPOS_BIN2', + 80: 'SPI_PERF_PS_CTL_PRIM_BIN0', + 81: 'SPI_PERF_PS_CTL_PRIM_BIN1', + 82: 'SPI_PERF_PS_CTL_CNF_BIN2', + 83: 'SPI_PERF_PS_CTL_CNF_BIN3', + 84: 'SPI_PERF_PS_CTL_CRAWLER_STALL', + 85: 'SPI_PERF_PS_CTL_LDS_RES_FULL', + 86: 'SPI_PERF_PS_PERS_UPD_FULL0', + 87: 'SPI_PERF_PS_PERS_UPD_FULL1', + 88: 'SPI_PERF_PIX_ALLOC_PEND_CNT', + 89: 'SPI_PERF_PIX_ALLOC_SCB_STALL', + 90: 'SPI_PERF_PIX_ALLOC_DB0_STALL', + 91: 'SPI_PERF_PIX_ALLOC_DB1_STALL', + 92: 'SPI_PERF_PIX_ALLOC_DB2_STALL', + 93: 'SPI_PERF_PIX_ALLOC_DB3_STALL', + 94: 'SPI_PERF_LDS0_PC_VALID', + 95: 'SPI_PERF_LDS1_PC_VALID', + 96: 'SPI_PERF_RA_PIPE_REQ_BIN2', + 97: 'SPI_PERF_RA_TASK_REQ_BIN3', + 98: 'SPI_PERF_RA_WR_CTL_FULL', + 99: 'SPI_PERF_RA_REQ_NO_ALLOC', + 100: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', + 101: 'SPI_PERF_RA_REQ_NO_ALLOC_VS', + 102: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', + 103: 'SPI_PERF_RA_REQ_NO_ALLOC_ES', + 104: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', + 105: 'SPI_PERF_RA_REQ_NO_ALLOC_LS', + 106: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', + 107: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', + 108: 'SPI_PERF_RA_RES_STALL_PS', + 109: 'SPI_PERF_RA_RES_STALL_VS', + 110: 'SPI_PERF_RA_RES_STALL_GS', + 111: 'SPI_PERF_RA_RES_STALL_ES', + 112: 'SPI_PERF_RA_RES_STALL_HS', + 113: 'SPI_PERF_RA_RES_STALL_LS', + 114: 'SPI_PERF_RA_RES_STALL_CSG', + 115: 'SPI_PERF_RA_RES_STALL_CSN', + 116: 'SPI_PERF_RA_TMP_STALL_PS', + 117: 'SPI_PERF_RA_TMP_STALL_VS', + 118: 'SPI_PERF_RA_TMP_STALL_GS', + 119: 'SPI_PERF_RA_TMP_STALL_ES', + 120: 'SPI_PERF_RA_TMP_STALL_HS', + 121: 'SPI_PERF_RA_TMP_STALL_LS', + 122: 'SPI_PERF_RA_TMP_STALL_CSG', + 123: 'SPI_PERF_RA_TMP_STALL_CSN', + 124: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 125: 'SPI_PERF_RA_WAVE_SIMD_FULL_VS', + 126: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', + 127: 'SPI_PERF_RA_WAVE_SIMD_FULL_ES', + 128: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', + 129: 'SPI_PERF_RA_WAVE_SIMD_FULL_LS', + 130: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 131: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', + 132: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 133: 'SPI_PERF_RA_VGPR_SIMD_FULL_VS', + 134: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', + 135: 'SPI_PERF_RA_VGPR_SIMD_FULL_ES', + 136: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', + 137: 'SPI_PERF_RA_VGPR_SIMD_FULL_LS', + 138: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 139: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', + 140: 'SPI_PERF_RA_SGPR_SIMD_FULL_PS', + 141: 'SPI_PERF_RA_SGPR_SIMD_FULL_VS', + 142: 'SPI_PERF_RA_SGPR_SIMD_FULL_GS', + 143: 'SPI_PERF_RA_SGPR_SIMD_FULL_ES', + 144: 'SPI_PERF_RA_SGPR_SIMD_FULL_HS', + 145: 'SPI_PERF_RA_SGPR_SIMD_FULL_LS', + 146: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG', + 147: 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', + 148: 'SPI_PERF_RA_LDS_CU_FULL_PS', + 149: 'SPI_PERF_RA_LDS_CU_FULL_LS', + 150: 'SPI_PERF_RA_LDS_CU_FULL_ES', + 151: 'SPI_PERF_RA_LDS_CU_FULL_CSG', + 152: 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 153: 'SPI_PERF_RA_BAR_CU_FULL_HS', + 154: 'SPI_PERF_RA_BAR_CU_FULL_CSG', + 155: 'SPI_PERF_RA_BAR_CU_FULL_CSN', + 156: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', + 157: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', + 158: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', + 159: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 160: 'SPI_PERF_RA_WVLIM_STALL_PS', + 161: 'SPI_PERF_RA_WVLIM_STALL_VS', + 162: 'SPI_PERF_RA_WVLIM_STALL_GS', + 163: 'SPI_PERF_RA_WVLIM_STALL_ES', + 164: 'SPI_PERF_RA_WVLIM_STALL_HS', + 165: 'SPI_PERF_RA_WVLIM_STALL_LS', + 166: 'SPI_PERF_RA_WVLIM_STALL_CSG', + 167: 'SPI_PERF_RA_WVLIM_STALL_CSN', + 168: 'SPI_PERF_RA_PS_LOCK_NA', + 169: 'SPI_PERF_RA_VS_LOCK', + 170: 'SPI_PERF_RA_GS_LOCK', + 171: 'SPI_PERF_RA_ES_LOCK', + 172: 'SPI_PERF_RA_HS_LOCK', + 173: 'SPI_PERF_RA_LS_LOCK', + 174: 'SPI_PERF_RA_CSG_LOCK', + 175: 'SPI_PERF_RA_CSN_LOCK', + 176: 'SPI_PERF_RA_RSV_UPD', + 177: 'SPI_PERF_EXP_ARB_COL_CNT', + 178: 'SPI_PERF_EXP_ARB_PAR_CNT', + 179: 'SPI_PERF_EXP_ARB_POS_CNT', + 180: 'SPI_PERF_EXP_ARB_GDS_CNT', + 181: 'SPI_PERF_CLKGATE_BUSY_STALL', + 182: 'SPI_PERF_CLKGATE_ACTIVE_STALL', + 183: 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON', + 184: 'SPI_PERF_CLKGATE_CGTT_DYN_ON', + 185: 'SPI_PERF_CLKGATE_CGTT_REG_ON', + 186: 'SPI_PERF_NUM_VS_POS_EXPORTS', + 187: 'SPI_PERF_NUM_VS_PARAM_EXPORTS', + 188: 'SPI_PERF_NUM_PS_COL_EXPORTS', + 189: 'SPI_PERF_ES_GRP_FIFO_FULL', + 190: 'SPI_PERF_GS_GRP_FIFO_FULL', + 191: 'SPI_PERF_HS_GRP_FIFO_FULL', + 192: 'SPI_PERF_LS_GRP_FIFO_FULL', + 193: 'SPI_PERF_VS_ALLOC_CNT', + 194: 'SPI_PERF_VS_LATE_ALLOC_ACCUM', + 195: 'SPI_PERF_PC_ALLOC_CNT', + 196: 'SPI_PERF_PC_ALLOC_ACCUM', +} +SPI_PERF_VS_WINDOW_VALID = 0 +SPI_PERF_VS_BUSY = 1 +SPI_PERF_VS_FIRST_WAVE = 2 +SPI_PERF_VS_LAST_WAVE = 3 +SPI_PERF_VS_LSHS_DEALLOC = 4 +SPI_PERF_VS_PC_STALL = 5 +SPI_PERF_VS_POS0_STALL = 6 +SPI_PERF_VS_POS1_STALL = 7 +SPI_PERF_VS_CRAWLER_STALL = 8 +SPI_PERF_VS_EVENT_WAVE = 9 +SPI_PERF_VS_WAVE = 10 +SPI_PERF_VS_PERS_UPD_FULL0 = 11 +SPI_PERF_VS_PERS_UPD_FULL1 = 12 +SPI_PERF_VS_LATE_ALLOC_FULL = 13 +SPI_PERF_VS_FIRST_SUBGRP = 14 +SPI_PERF_VS_LAST_SUBGRP = 15 +SPI_PERF_GS_WINDOW_VALID = 16 +SPI_PERF_GS_BUSY = 17 +SPI_PERF_GS_CRAWLER_STALL = 18 +SPI_PERF_GS_EVENT_WAVE = 19 +SPI_PERF_GS_WAVE = 20 +SPI_PERF_GS_PERS_UPD_FULL0 = 21 +SPI_PERF_GS_PERS_UPD_FULL1 = 22 +SPI_PERF_GS_FIRST_SUBGRP = 23 +SPI_PERF_GS_LAST_SUBGRP = 24 +SPI_PERF_ES_WINDOW_VALID = 25 +SPI_PERF_ES_BUSY = 26 +SPI_PERF_ES_CRAWLER_STALL = 27 +SPI_PERF_ES_FIRST_WAVE = 28 +SPI_PERF_ES_LAST_WAVE = 29 +SPI_PERF_ES_LSHS_DEALLOC = 30 +SPI_PERF_ES_EVENT_WAVE = 31 +SPI_PERF_ES_WAVE = 32 +SPI_PERF_ES_PERS_UPD_FULL0 = 33 +SPI_PERF_ES_PERS_UPD_FULL1 = 34 +SPI_PERF_ES_FIRST_SUBGRP = 35 +SPI_PERF_ES_LAST_SUBGRP = 36 +SPI_PERF_HS_WINDOW_VALID = 37 +SPI_PERF_HS_BUSY = 38 +SPI_PERF_HS_CRAWLER_STALL = 39 +SPI_PERF_HS_FIRST_WAVE = 40 +SPI_PERF_HS_LAST_WAVE = 41 +SPI_PERF_HS_LSHS_DEALLOC = 42 +SPI_PERF_HS_EVENT_WAVE = 43 +SPI_PERF_HS_WAVE = 44 +SPI_PERF_HS_PERS_UPD_FULL0 = 45 +SPI_PERF_HS_PERS_UPD_FULL1 = 46 +SPI_PERF_LS_WINDOW_VALID = 47 +SPI_PERF_LS_BUSY = 48 +SPI_PERF_LS_CRAWLER_STALL = 49 +SPI_PERF_LS_FIRST_WAVE = 50 +SPI_PERF_LS_LAST_WAVE = 51 +SPI_PERF_OFFCHIP_LDS_STALL_LS = 52 +SPI_PERF_LS_EVENT_WAVE = 53 +SPI_PERF_LS_WAVE = 54 +SPI_PERF_LS_PERS_UPD_FULL0 = 55 +SPI_PERF_LS_PERS_UPD_FULL1 = 56 +SPI_PERF_CSG_WINDOW_VALID = 57 +SPI_PERF_CSG_BUSY = 58 +SPI_PERF_CSG_NUM_THREADGROUPS = 59 +SPI_PERF_CSG_CRAWLER_STALL = 60 +SPI_PERF_CSG_EVENT_WAVE = 61 +SPI_PERF_CSG_WAVE = 62 +SPI_PERF_CSN_WINDOW_VALID = 63 +SPI_PERF_CSN_BUSY = 64 +SPI_PERF_CSN_NUM_THREADGROUPS = 65 +SPI_PERF_CSN_CRAWLER_STALL = 66 +SPI_PERF_CSN_EVENT_WAVE = 67 +SPI_PERF_CSN_WAVE = 68 +SPI_PERF_PS_CTL_WINDOW_VALID = 69 +SPI_PERF_PS_CTL_BUSY = 70 +SPI_PERF_PS_CTL_ACTIVE = 71 +SPI_PERF_PS_CTL_DEALLOC_BIN0 = 72 +SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 73 +SPI_PERF_PS_CTL_EVENT_WAVE = 74 +SPI_PERF_PS_CTL_WAVE = 75 +SPI_PERF_PS_CTL_OPT_WAVE = 76 +SPI_PERF_PS_CTL_PASS_BIN0 = 77 +SPI_PERF_PS_CTL_PASS_BIN1 = 78 +SPI_PERF_PS_CTL_FPOS_BIN2 = 79 +SPI_PERF_PS_CTL_PRIM_BIN0 = 80 +SPI_PERF_PS_CTL_PRIM_BIN1 = 81 +SPI_PERF_PS_CTL_CNF_BIN2 = 82 +SPI_PERF_PS_CTL_CNF_BIN3 = 83 +SPI_PERF_PS_CTL_CRAWLER_STALL = 84 +SPI_PERF_PS_CTL_LDS_RES_FULL = 85 +SPI_PERF_PS_PERS_UPD_FULL0 = 86 +SPI_PERF_PS_PERS_UPD_FULL1 = 87 +SPI_PERF_PIX_ALLOC_PEND_CNT = 88 +SPI_PERF_PIX_ALLOC_SCB_STALL = 89 +SPI_PERF_PIX_ALLOC_DB0_STALL = 90 +SPI_PERF_PIX_ALLOC_DB1_STALL = 91 +SPI_PERF_PIX_ALLOC_DB2_STALL = 92 +SPI_PERF_PIX_ALLOC_DB3_STALL = 93 +SPI_PERF_LDS0_PC_VALID = 94 +SPI_PERF_LDS1_PC_VALID = 95 +SPI_PERF_RA_PIPE_REQ_BIN2 = 96 +SPI_PERF_RA_TASK_REQ_BIN3 = 97 +SPI_PERF_RA_WR_CTL_FULL = 98 +SPI_PERF_RA_REQ_NO_ALLOC = 99 +SPI_PERF_RA_REQ_NO_ALLOC_PS = 100 +SPI_PERF_RA_REQ_NO_ALLOC_VS = 101 +SPI_PERF_RA_REQ_NO_ALLOC_GS = 102 +SPI_PERF_RA_REQ_NO_ALLOC_ES = 103 +SPI_PERF_RA_REQ_NO_ALLOC_HS = 104 +SPI_PERF_RA_REQ_NO_ALLOC_LS = 105 +SPI_PERF_RA_REQ_NO_ALLOC_CSG = 106 +SPI_PERF_RA_REQ_NO_ALLOC_CSN = 107 +SPI_PERF_RA_RES_STALL_PS = 108 +SPI_PERF_RA_RES_STALL_VS = 109 +SPI_PERF_RA_RES_STALL_GS = 110 +SPI_PERF_RA_RES_STALL_ES = 111 +SPI_PERF_RA_RES_STALL_HS = 112 +SPI_PERF_RA_RES_STALL_LS = 113 +SPI_PERF_RA_RES_STALL_CSG = 114 +SPI_PERF_RA_RES_STALL_CSN = 115 +SPI_PERF_RA_TMP_STALL_PS = 116 +SPI_PERF_RA_TMP_STALL_VS = 117 +SPI_PERF_RA_TMP_STALL_GS = 118 +SPI_PERF_RA_TMP_STALL_ES = 119 +SPI_PERF_RA_TMP_STALL_HS = 120 +SPI_PERF_RA_TMP_STALL_LS = 121 +SPI_PERF_RA_TMP_STALL_CSG = 122 +SPI_PERF_RA_TMP_STALL_CSN = 123 +SPI_PERF_RA_WAVE_SIMD_FULL_PS = 124 +SPI_PERF_RA_WAVE_SIMD_FULL_VS = 125 +SPI_PERF_RA_WAVE_SIMD_FULL_GS = 126 +SPI_PERF_RA_WAVE_SIMD_FULL_ES = 127 +SPI_PERF_RA_WAVE_SIMD_FULL_HS = 128 +SPI_PERF_RA_WAVE_SIMD_FULL_LS = 129 +SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 130 +SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 131 +SPI_PERF_RA_VGPR_SIMD_FULL_PS = 132 +SPI_PERF_RA_VGPR_SIMD_FULL_VS = 133 +SPI_PERF_RA_VGPR_SIMD_FULL_GS = 134 +SPI_PERF_RA_VGPR_SIMD_FULL_ES = 135 +SPI_PERF_RA_VGPR_SIMD_FULL_HS = 136 +SPI_PERF_RA_VGPR_SIMD_FULL_LS = 137 +SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 138 +SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 139 +SPI_PERF_RA_SGPR_SIMD_FULL_PS = 140 +SPI_PERF_RA_SGPR_SIMD_FULL_VS = 141 +SPI_PERF_RA_SGPR_SIMD_FULL_GS = 142 +SPI_PERF_RA_SGPR_SIMD_FULL_ES = 143 +SPI_PERF_RA_SGPR_SIMD_FULL_HS = 144 +SPI_PERF_RA_SGPR_SIMD_FULL_LS = 145 +SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 146 +SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 147 +SPI_PERF_RA_LDS_CU_FULL_PS = 148 +SPI_PERF_RA_LDS_CU_FULL_LS = 149 +SPI_PERF_RA_LDS_CU_FULL_ES = 150 +SPI_PERF_RA_LDS_CU_FULL_CSG = 151 +SPI_PERF_RA_LDS_CU_FULL_CSN = 152 +SPI_PERF_RA_BAR_CU_FULL_HS = 153 +SPI_PERF_RA_BAR_CU_FULL_CSG = 154 +SPI_PERF_RA_BAR_CU_FULL_CSN = 155 +SPI_PERF_RA_BULKY_CU_FULL_CSG = 156 +SPI_PERF_RA_BULKY_CU_FULL_CSN = 157 +SPI_PERF_RA_TGLIM_CU_FULL_CSG = 158 +SPI_PERF_RA_TGLIM_CU_FULL_CSN = 159 +SPI_PERF_RA_WVLIM_STALL_PS = 160 +SPI_PERF_RA_WVLIM_STALL_VS = 161 +SPI_PERF_RA_WVLIM_STALL_GS = 162 +SPI_PERF_RA_WVLIM_STALL_ES = 163 +SPI_PERF_RA_WVLIM_STALL_HS = 164 +SPI_PERF_RA_WVLIM_STALL_LS = 165 +SPI_PERF_RA_WVLIM_STALL_CSG = 166 +SPI_PERF_RA_WVLIM_STALL_CSN = 167 +SPI_PERF_RA_PS_LOCK_NA = 168 +SPI_PERF_RA_VS_LOCK = 169 +SPI_PERF_RA_GS_LOCK = 170 +SPI_PERF_RA_ES_LOCK = 171 +SPI_PERF_RA_HS_LOCK = 172 +SPI_PERF_RA_LS_LOCK = 173 +SPI_PERF_RA_CSG_LOCK = 174 +SPI_PERF_RA_CSN_LOCK = 175 +SPI_PERF_RA_RSV_UPD = 176 +SPI_PERF_EXP_ARB_COL_CNT = 177 +SPI_PERF_EXP_ARB_PAR_CNT = 178 +SPI_PERF_EXP_ARB_POS_CNT = 179 +SPI_PERF_EXP_ARB_GDS_CNT = 180 +SPI_PERF_CLKGATE_BUSY_STALL = 181 +SPI_PERF_CLKGATE_ACTIVE_STALL = 182 +SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 183 +SPI_PERF_CLKGATE_CGTT_DYN_ON = 184 +SPI_PERF_CLKGATE_CGTT_REG_ON = 185 +SPI_PERF_NUM_VS_POS_EXPORTS = 186 +SPI_PERF_NUM_VS_PARAM_EXPORTS = 187 +SPI_PERF_NUM_PS_COL_EXPORTS = 188 +SPI_PERF_ES_GRP_FIFO_FULL = 189 +SPI_PERF_GS_GRP_FIFO_FULL = 190 +SPI_PERF_HS_GRP_FIFO_FULL = 191 +SPI_PERF_LS_GRP_FIFO_FULL = 192 +SPI_PERF_VS_ALLOC_CNT = 193 +SPI_PERF_VS_LATE_ALLOC_ACCUM = 194 +SPI_PERF_PC_ALLOC_CNT = 195 +SPI_PERF_PC_ALLOC_ACCUM = 196 +SPI_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_FORMAT' +SPI_SHADER_FORMAT__enumvalues = { + 0: 'SPI_SHADER_NONE', + 1: 'SPI_SHADER_1COMP', + 2: 'SPI_SHADER_2COMP', + 3: 'SPI_SHADER_4COMPRESS', + 4: 'SPI_SHADER_4COMP', +} +SPI_SHADER_NONE = 0 +SPI_SHADER_1COMP = 1 +SPI_SHADER_2COMP = 2 +SPI_SHADER_4COMPRESS = 3 +SPI_SHADER_4COMP = 4 +SPI_SHADER_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_EX_FORMAT' +SPI_SHADER_EX_FORMAT__enumvalues = { + 0: 'SPI_SHADER_ZERO', + 1: 'SPI_SHADER_32_R', + 2: 'SPI_SHADER_32_GR', + 3: 'SPI_SHADER_32_AR', + 4: 'SPI_SHADER_FP16_ABGR', + 5: 'SPI_SHADER_UNORM16_ABGR', + 6: 'SPI_SHADER_SNORM16_ABGR', + 7: 'SPI_SHADER_UINT16_ABGR', + 8: 'SPI_SHADER_SINT16_ABGR', + 9: 'SPI_SHADER_32_ABGR', +} +SPI_SHADER_ZERO = 0 +SPI_SHADER_32_R = 1 +SPI_SHADER_32_GR = 2 +SPI_SHADER_32_AR = 3 +SPI_SHADER_FP16_ABGR = 4 +SPI_SHADER_UNORM16_ABGR = 5 +SPI_SHADER_SNORM16_ABGR = 6 +SPI_SHADER_UINT16_ABGR = 7 +SPI_SHADER_SINT16_ABGR = 8 +SPI_SHADER_32_ABGR = 9 +SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_SM_MODE' +CLKGATE_SM_MODE__enumvalues = { + 0: 'ON_SEQ', + 1: 'OFF_SEQ', + 2: 'PROG_SEQ', + 3: 'READ_SEQ', + 4: 'SM_MODE_RESERVED', +} +ON_SEQ = 0 +OFF_SEQ = 1 +PROG_SEQ = 2 +READ_SEQ = 3 +SM_MODE_RESERVED = 4 +CLKGATE_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_BASE_MODE' +CLKGATE_BASE_MODE__enumvalues = { + 0: 'MULT_8', + 1: 'MULT_16', +} +MULT_8 = 0 +MULT_16 = 1 +CLKGATE_BASE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_CLAMP' +SQ_TEX_CLAMP__enumvalues = { + 0: 'SQ_TEX_WRAP', + 1: 'SQ_TEX_MIRROR', + 2: 'SQ_TEX_CLAMP_LAST_TEXEL', + 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 4: 'SQ_TEX_CLAMP_HALF_BORDER', + 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', + 6: 'SQ_TEX_CLAMP_BORDER', + 7: 'SQ_TEX_MIRROR_ONCE_BORDER', +} +SQ_TEX_WRAP = 0 +SQ_TEX_MIRROR = 1 +SQ_TEX_CLAMP_LAST_TEXEL = 2 +SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 +SQ_TEX_CLAMP_HALF_BORDER = 4 +SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 +SQ_TEX_CLAMP_BORDER = 6 +SQ_TEX_MIRROR_ONCE_BORDER = 7 +SQ_TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_XY_FILTER' +SQ_TEX_XY_FILTER__enumvalues = { + 0: 'SQ_TEX_XY_FILTER_POINT', + 1: 'SQ_TEX_XY_FILTER_BILINEAR', + 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', + 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', +} +SQ_TEX_XY_FILTER_POINT = 0 +SQ_TEX_XY_FILTER_BILINEAR = 1 +SQ_TEX_XY_FILTER_ANISO_POINT = 2 +SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 +SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_Z_FILTER' +SQ_TEX_Z_FILTER__enumvalues = { + 0: 'SQ_TEX_Z_FILTER_NONE', + 1: 'SQ_TEX_Z_FILTER_POINT', + 2: 'SQ_TEX_Z_FILTER_LINEAR', +} +SQ_TEX_Z_FILTER_NONE = 0 +SQ_TEX_Z_FILTER_POINT = 1 +SQ_TEX_Z_FILTER_LINEAR = 2 +SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_MIP_FILTER' +SQ_TEX_MIP_FILTER__enumvalues = { + 0: 'SQ_TEX_MIP_FILTER_NONE', + 1: 'SQ_TEX_MIP_FILTER_POINT', + 2: 'SQ_TEX_MIP_FILTER_LINEAR', + 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', +} +SQ_TEX_MIP_FILTER_NONE = 0 +SQ_TEX_MIP_FILTER_POINT = 1 +SQ_TEX_MIP_FILTER_LINEAR = 2 +SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 +SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_ANISO_RATIO' +SQ_TEX_ANISO_RATIO__enumvalues = { + 0: 'SQ_TEX_ANISO_RATIO_1', + 1: 'SQ_TEX_ANISO_RATIO_2', + 2: 'SQ_TEX_ANISO_RATIO_4', + 3: 'SQ_TEX_ANISO_RATIO_8', + 4: 'SQ_TEX_ANISO_RATIO_16', +} +SQ_TEX_ANISO_RATIO_1 = 0 +SQ_TEX_ANISO_RATIO_2 = 1 +SQ_TEX_ANISO_RATIO_4 = 2 +SQ_TEX_ANISO_RATIO_8 = 3 +SQ_TEX_ANISO_RATIO_16 = 4 +SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_DEPTH_COMPARE' +SQ_TEX_DEPTH_COMPARE__enumvalues = { + 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', + 1: 'SQ_TEX_DEPTH_COMPARE_LESS', + 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', + 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', + 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', + 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', + 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', +} +SQ_TEX_DEPTH_COMPARE_NEVER = 0 +SQ_TEX_DEPTH_COMPARE_LESS = 1 +SQ_TEX_DEPTH_COMPARE_EQUAL = 2 +SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 +SQ_TEX_DEPTH_COMPARE_GREATER = 4 +SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 +SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 +SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 +SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_BORDER_COLOR' +SQ_TEX_BORDER_COLOR__enumvalues = { + 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 3: 'SQ_TEX_BORDER_COLOR_REGISTER', +} +SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 +SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 +SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 +SQ_TEX_BORDER_COLOR_REGISTER = 3 +SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_BUF_TYPE' +SQ_RSRC_BUF_TYPE__enumvalues = { + 0: 'SQ_RSRC_BUF', + 1: 'SQ_RSRC_BUF_RSVD_1', + 2: 'SQ_RSRC_BUF_RSVD_2', + 3: 'SQ_RSRC_BUF_RSVD_3', +} +SQ_RSRC_BUF = 0 +SQ_RSRC_BUF_RSVD_1 = 1 +SQ_RSRC_BUF_RSVD_2 = 2 +SQ_RSRC_BUF_RSVD_3 = 3 +SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_IMG_TYPE' +SQ_RSRC_IMG_TYPE__enumvalues = { + 0: 'SQ_RSRC_IMG_RSVD_0', + 1: 'SQ_RSRC_IMG_RSVD_1', + 2: 'SQ_RSRC_IMG_RSVD_2', + 3: 'SQ_RSRC_IMG_RSVD_3', + 4: 'SQ_RSRC_IMG_RSVD_4', + 5: 'SQ_RSRC_IMG_RSVD_5', + 6: 'SQ_RSRC_IMG_RSVD_6', + 7: 'SQ_RSRC_IMG_RSVD_7', + 8: 'SQ_RSRC_IMG_1D', + 9: 'SQ_RSRC_IMG_2D', + 10: 'SQ_RSRC_IMG_3D', + 11: 'SQ_RSRC_IMG_CUBE', + 12: 'SQ_RSRC_IMG_1D_ARRAY', + 13: 'SQ_RSRC_IMG_2D_ARRAY', + 14: 'SQ_RSRC_IMG_2D_MSAA', + 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', +} +SQ_RSRC_IMG_RSVD_0 = 0 +SQ_RSRC_IMG_RSVD_1 = 1 +SQ_RSRC_IMG_RSVD_2 = 2 +SQ_RSRC_IMG_RSVD_3 = 3 +SQ_RSRC_IMG_RSVD_4 = 4 +SQ_RSRC_IMG_RSVD_5 = 5 +SQ_RSRC_IMG_RSVD_6 = 6 +SQ_RSRC_IMG_RSVD_7 = 7 +SQ_RSRC_IMG_1D = 8 +SQ_RSRC_IMG_2D = 9 +SQ_RSRC_IMG_3D = 10 +SQ_RSRC_IMG_CUBE = 11 +SQ_RSRC_IMG_1D_ARRAY = 12 +SQ_RSRC_IMG_2D_ARRAY = 13 +SQ_RSRC_IMG_2D_MSAA = 14 +SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 +SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_FLAT_TYPE' +SQ_RSRC_FLAT_TYPE__enumvalues = { + 0: 'SQ_RSRC_FLAT_RSVD_0', + 1: 'SQ_RSRC_FLAT', + 2: 'SQ_RSRC_FLAT_RSVD_2', + 3: 'SQ_RSRC_FLAT_RSVD_3', +} +SQ_RSRC_FLAT_RSVD_0 = 0 +SQ_RSRC_FLAT = 1 +SQ_RSRC_FLAT_RSVD_2 = 2 +SQ_RSRC_FLAT_RSVD_3 = 3 +SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IMG_FILTER_TYPE' +SQ_IMG_FILTER_TYPE__enumvalues = { + 0: 'SQ_IMG_FILTER_MODE_BLEND', + 1: 'SQ_IMG_FILTER_MODE_MIN', + 2: 'SQ_IMG_FILTER_MODE_MAX', +} +SQ_IMG_FILTER_MODE_BLEND = 0 +SQ_IMG_FILTER_MODE_MIN = 1 +SQ_IMG_FILTER_MODE_MAX = 2 +SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_SEL_XYZW01' +SQ_SEL_XYZW01__enumvalues = { + 0: 'SQ_SEL_0', + 1: 'SQ_SEL_1', + 2: 'SQ_SEL_RESERVED_0', + 3: 'SQ_SEL_RESERVED_1', + 4: 'SQ_SEL_X', + 5: 'SQ_SEL_Y', + 6: 'SQ_SEL_Z', + 7: 'SQ_SEL_W', +} +SQ_SEL_0 = 0 +SQ_SEL_1 = 1 +SQ_SEL_RESERVED_0 = 2 +SQ_SEL_RESERVED_1 = 3 +SQ_SEL_X = 4 +SQ_SEL_Y = 5 +SQ_SEL_Z = 6 +SQ_SEL_W = 7 +SQ_SEL_XYZW01 = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_TYPE' +SQ_WAVE_TYPE__enumvalues = { + 0: 'SQ_WAVE_TYPE_PS', + 1: 'SQ_WAVE_TYPE_VS', + 2: 'SQ_WAVE_TYPE_GS', + 3: 'SQ_WAVE_TYPE_ES', + 4: 'SQ_WAVE_TYPE_HS', + 5: 'SQ_WAVE_TYPE_LS', + 6: 'SQ_WAVE_TYPE_CS', + 7: 'SQ_WAVE_TYPE_PS1', +} +SQ_WAVE_TYPE_PS = 0 +SQ_WAVE_TYPE_VS = 1 +SQ_WAVE_TYPE_GS = 2 +SQ_WAVE_TYPE_ES = 3 +SQ_WAVE_TYPE_HS = 4 +SQ_WAVE_TYPE_LS = 5 +SQ_WAVE_TYPE_CS = 6 +SQ_WAVE_TYPE_PS1 = 7 +SQ_WAVE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_TOKEN_TYPE' +SQ_THREAD_TRACE_TOKEN_TYPE__enumvalues = { + 0: 'SQ_THREAD_TRACE_TOKEN_MISC', + 1: 'SQ_THREAD_TRACE_TOKEN_TIMESTAMP', + 2: 'SQ_THREAD_TRACE_TOKEN_REG', + 3: 'SQ_THREAD_TRACE_TOKEN_WAVE_START', + 4: 'SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC', + 5: 'SQ_THREAD_TRACE_TOKEN_REG_CSPRIV', + 6: 'SQ_THREAD_TRACE_TOKEN_WAVE_END', + 7: 'SQ_THREAD_TRACE_TOKEN_EVENT', + 8: 'SQ_THREAD_TRACE_TOKEN_EVENT_CS', + 9: 'SQ_THREAD_TRACE_TOKEN_EVENT_GFX1', + 10: 'SQ_THREAD_TRACE_TOKEN_INST', + 11: 'SQ_THREAD_TRACE_TOKEN_INST_PC', + 12: 'SQ_THREAD_TRACE_TOKEN_INST_USERDATA', + 13: 'SQ_THREAD_TRACE_TOKEN_ISSUE', + 14: 'SQ_THREAD_TRACE_TOKEN_PERF', + 15: 'SQ_THREAD_TRACE_TOKEN_REG_CS', +} +SQ_THREAD_TRACE_TOKEN_MISC = 0 +SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 1 +SQ_THREAD_TRACE_TOKEN_REG = 2 +SQ_THREAD_TRACE_TOKEN_WAVE_START = 3 +SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 4 +SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 5 +SQ_THREAD_TRACE_TOKEN_WAVE_END = 6 +SQ_THREAD_TRACE_TOKEN_EVENT = 7 +SQ_THREAD_TRACE_TOKEN_EVENT_CS = 8 +SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 9 +SQ_THREAD_TRACE_TOKEN_INST = 10 +SQ_THREAD_TRACE_TOKEN_INST_PC = 11 +SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 12 +SQ_THREAD_TRACE_TOKEN_ISSUE = 13 +SQ_THREAD_TRACE_TOKEN_PERF = 14 +SQ_THREAD_TRACE_TOKEN_REG_CS = 15 +SQ_THREAD_TRACE_TOKEN_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_MISC_TOKEN_TYPE' +SQ_THREAD_TRACE_MISC_TOKEN_TYPE__enumvalues = { + 0: 'SQ_THREAD_TRACE_MISC_TOKEN_TIME', + 1: 'SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET', + 2: 'SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST', + 3: 'SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC', + 4: 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN', + 5: 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END', + 6: 'SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX', + 7: 'SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN', +} +SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0 +SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 1 +SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 2 +SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 3 +SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 4 +SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 5 +SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 6 +SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 7 +SQ_THREAD_TRACE_MISC_TOKEN_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_INST_TYPE' +SQ_THREAD_TRACE_INST_TYPE__enumvalues = { + 0: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD', + 1: 'SQ_THREAD_TRACE_INST_TYPE_SALU_32', + 2: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD', + 3: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR', + 4: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR', + 5: 'SQ_THREAD_TRACE_INST_TYPE_VALU_32', + 6: 'SQ_THREAD_TRACE_INST_TYPE_LDS', + 7: 'SQ_THREAD_TRACE_INST_TYPE_PC', + 8: 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS', + 9: 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX', + 10: 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL', + 11: 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS', + 12: 'SQ_THREAD_TRACE_INST_TYPE_JUMP', + 13: 'SQ_THREAD_TRACE_INST_TYPE_NEXT', + 14: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD', + 15: 'SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG', + 16: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR', + 17: 'SQ_THREAD_TRACE_INST_TYPE_SALU_64', + 18: 'SQ_THREAD_TRACE_INST_TYPE_VALU_64', + 19: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY', + 20: 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY', + 21: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY', + 22: 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY', + 23: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY', + 24: 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY', + 25: 'SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT', +} +SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0 +SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 1 +SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 2 +SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 3 +SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 4 +SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 5 +SQ_THREAD_TRACE_INST_TYPE_LDS = 6 +SQ_THREAD_TRACE_INST_TYPE_PC = 7 +SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 8 +SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 9 +SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 10 +SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 11 +SQ_THREAD_TRACE_INST_TYPE_JUMP = 12 +SQ_THREAD_TRACE_INST_TYPE_NEXT = 13 +SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 14 +SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 15 +SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 16 +SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 17 +SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 18 +SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 19 +SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 20 +SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 21 +SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 22 +SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 23 +SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 24 +SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT = 25 +SQ_THREAD_TRACE_INST_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_REG_TYPE' +SQ_THREAD_TRACE_REG_TYPE__enumvalues = { + 0: 'SQ_THREAD_TRACE_REG_TYPE_EVENT', + 1: 'SQ_THREAD_TRACE_REG_TYPE_DRAW', + 2: 'SQ_THREAD_TRACE_REG_TYPE_DISPATCH', + 3: 'SQ_THREAD_TRACE_REG_TYPE_USERDATA', + 4: 'SQ_THREAD_TRACE_REG_TYPE_MARKER', + 5: 'SQ_THREAD_TRACE_REG_TYPE_GFXDEC', + 6: 'SQ_THREAD_TRACE_REG_TYPE_SHDEC', + 7: 'SQ_THREAD_TRACE_REG_TYPE_OTHER', +} +SQ_THREAD_TRACE_REG_TYPE_EVENT = 0 +SQ_THREAD_TRACE_REG_TYPE_DRAW = 1 +SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 2 +SQ_THREAD_TRACE_REG_TYPE_USERDATA = 3 +SQ_THREAD_TRACE_REG_TYPE_MARKER = 4 +SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 5 +SQ_THREAD_TRACE_REG_TYPE_SHDEC = 6 +SQ_THREAD_TRACE_REG_TYPE_OTHER = 7 +SQ_THREAD_TRACE_REG_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_REG_OP' +SQ_THREAD_TRACE_REG_OP__enumvalues = { + 0: 'SQ_THREAD_TRACE_REG_OP_READ', + 1: 'SQ_THREAD_TRACE_REG_OP_WRITE', +} +SQ_THREAD_TRACE_REG_OP_READ = 0 +SQ_THREAD_TRACE_REG_OP_WRITE = 1 +SQ_THREAD_TRACE_REG_OP = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_MODE_SEL' +SQ_THREAD_TRACE_MODE_SEL__enumvalues = { + 0: 'SQ_THREAD_TRACE_MODE_OFF', + 1: 'SQ_THREAD_TRACE_MODE_ON', +} +SQ_THREAD_TRACE_MODE_OFF = 0 +SQ_THREAD_TRACE_MODE_ON = 1 +SQ_THREAD_TRACE_MODE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_CAPTURE_MODE' +SQ_THREAD_TRACE_CAPTURE_MODE__enumvalues = { + 0: 'SQ_THREAD_TRACE_CAPTURE_MODE_ALL', + 1: 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT', + 2: 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL', +} +SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0 +SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 1 +SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 2 +SQ_THREAD_TRACE_CAPTURE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_VM_ID_MASK' +SQ_THREAD_TRACE_VM_ID_MASK__enumvalues = { + 0: 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE', + 1: 'SQ_THREAD_TRACE_VM_ID_MASK_ALL', + 2: 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL', +} +SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0 +SQ_THREAD_TRACE_VM_ID_MASK_ALL = 1 +SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 2 +SQ_THREAD_TRACE_VM_ID_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_WAVE_MASK' +SQ_THREAD_TRACE_WAVE_MASK__enumvalues = { + 0: 'SQ_THREAD_TRACE_WAVE_MASK_NONE', + 1: 'SQ_THREAD_TRACE_WAVE_MASK_ALL', +} +SQ_THREAD_TRACE_WAVE_MASK_NONE = 0 +SQ_THREAD_TRACE_WAVE_MASK_ALL = 1 +SQ_THREAD_TRACE_WAVE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_ISSUE' +SQ_THREAD_TRACE_ISSUE__enumvalues = { + 0: 'SQ_THREAD_TRACE_ISSUE_NULL', + 1: 'SQ_THREAD_TRACE_ISSUE_STALL', + 2: 'SQ_THREAD_TRACE_ISSUE_INST', + 3: 'SQ_THREAD_TRACE_ISSUE_IMMED', +} +SQ_THREAD_TRACE_ISSUE_NULL = 0 +SQ_THREAD_TRACE_ISSUE_STALL = 1 +SQ_THREAD_TRACE_ISSUE_INST = 2 +SQ_THREAD_TRACE_ISSUE_IMMED = 3 +SQ_THREAD_TRACE_ISSUE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_ISSUE_MASK' +SQ_THREAD_TRACE_ISSUE_MASK__enumvalues = { + 0: 'SQ_THREAD_TRACE_ISSUE_MASK_ALL', + 1: 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED', + 2: 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED', + 3: 'SQ_THREAD_TRACE_ISSUE_MASK_IMMED', +} +SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0 +SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 1 +SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 2 +SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 3 +SQ_THREAD_TRACE_ISSUE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_PERF_SEL' +SQ_PERF_SEL__enumvalues = { + 0: 'SQ_PERF_SEL_NONE', + 1: 'SQ_PERF_SEL_ACCUM_PREV', + 2: 'SQ_PERF_SEL_CYCLES', + 3: 'SQ_PERF_SEL_BUSY_CYCLES', + 4: 'SQ_PERF_SEL_WAVES', + 5: 'SQ_PERF_SEL_LEVEL_WAVES', + 6: 'SQ_PERF_SEL_WAVES_EQ_64', + 7: 'SQ_PERF_SEL_WAVES_LT_64', + 8: 'SQ_PERF_SEL_WAVES_LT_48', + 9: 'SQ_PERF_SEL_WAVES_LT_32', + 10: 'SQ_PERF_SEL_WAVES_LT_16', + 11: 'SQ_PERF_SEL_WAVES_CU', + 12: 'SQ_PERF_SEL_LEVEL_WAVES_CU', + 13: 'SQ_PERF_SEL_BUSY_CU_CYCLES', + 14: 'SQ_PERF_SEL_ITEMS', + 15: 'SQ_PERF_SEL_QUADS', + 16: 'SQ_PERF_SEL_EVENTS', + 17: 'SQ_PERF_SEL_SURF_SYNCS', + 18: 'SQ_PERF_SEL_TTRACE_REQS', + 19: 'SQ_PERF_SEL_TTRACE_INFLIGHT_REQS', + 20: 'SQ_PERF_SEL_TTRACE_STALL', + 21: 'SQ_PERF_SEL_MSG_CNTR', + 22: 'SQ_PERF_SEL_MSG_PERF', + 23: 'SQ_PERF_SEL_MSG_GSCNT', + 24: 'SQ_PERF_SEL_MSG_INTERRUPT', + 25: 'SQ_PERF_SEL_INSTS', + 26: 'SQ_PERF_SEL_INSTS_VALU', + 27: 'SQ_PERF_SEL_INSTS_VMEM_WR', + 28: 'SQ_PERF_SEL_INSTS_VMEM_RD', + 29: 'SQ_PERF_SEL_INSTS_VMEM', + 30: 'SQ_PERF_SEL_INSTS_SALU', + 31: 'SQ_PERF_SEL_INSTS_SMEM', + 32: 'SQ_PERF_SEL_INSTS_FLAT', + 33: 'SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY', + 34: 'SQ_PERF_SEL_INSTS_LDS', + 35: 'SQ_PERF_SEL_INSTS_GDS', + 36: 'SQ_PERF_SEL_INSTS_EXP', + 37: 'SQ_PERF_SEL_INSTS_EXP_GDS', + 38: 'SQ_PERF_SEL_INSTS_BRANCH', + 39: 'SQ_PERF_SEL_INSTS_SENDMSG', + 40: 'SQ_PERF_SEL_INSTS_VSKIPPED', + 41: 'SQ_PERF_SEL_INST_LEVEL_VMEM', + 42: 'SQ_PERF_SEL_INST_LEVEL_SMEM', + 43: 'SQ_PERF_SEL_INST_LEVEL_LDS', + 44: 'SQ_PERF_SEL_INST_LEVEL_GDS', + 45: 'SQ_PERF_SEL_INST_LEVEL_EXP', + 46: 'SQ_PERF_SEL_WAVE_CYCLES', + 47: 'SQ_PERF_SEL_WAVE_READY', + 48: 'SQ_PERF_SEL_WAIT_CNT_VM', + 49: 'SQ_PERF_SEL_WAIT_CNT_LGKM', + 50: 'SQ_PERF_SEL_WAIT_CNT_EXP', + 51: 'SQ_PERF_SEL_WAIT_CNT_ANY', + 52: 'SQ_PERF_SEL_WAIT_BARRIER', + 53: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', + 54: 'SQ_PERF_SEL_WAIT_SLEEP', + 55: 'SQ_PERF_SEL_WAIT_SLEEP_XNACK', + 56: 'SQ_PERF_SEL_WAIT_OTHER', + 57: 'SQ_PERF_SEL_WAIT_ANY', + 58: 'SQ_PERF_SEL_WAIT_TTRACE', + 59: 'SQ_PERF_SEL_WAIT_IFETCH', + 60: 'SQ_PERF_SEL_WAIT_INST_ANY', + 61: 'SQ_PERF_SEL_WAIT_INST_VMEM', + 62: 'SQ_PERF_SEL_WAIT_INST_SCA', + 63: 'SQ_PERF_SEL_WAIT_INST_LDS', + 64: 'SQ_PERF_SEL_WAIT_INST_VALU', + 65: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', + 66: 'SQ_PERF_SEL_WAIT_INST_MISC', + 67: 'SQ_PERF_SEL_WAIT_INST_FLAT', + 68: 'SQ_PERF_SEL_ACTIVE_INST_ANY', + 69: 'SQ_PERF_SEL_ACTIVE_INST_VMEM', + 70: 'SQ_PERF_SEL_ACTIVE_INST_LDS', + 71: 'SQ_PERF_SEL_ACTIVE_INST_VALU', + 72: 'SQ_PERF_SEL_ACTIVE_INST_SCA', + 73: 'SQ_PERF_SEL_ACTIVE_INST_EXP_GDS', + 74: 'SQ_PERF_SEL_ACTIVE_INST_MISC', + 75: 'SQ_PERF_SEL_ACTIVE_INST_FLAT', + 76: 'SQ_PERF_SEL_INST_CYCLES_VMEM_WR', + 77: 'SQ_PERF_SEL_INST_CYCLES_VMEM_RD', + 78: 'SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR', + 79: 'SQ_PERF_SEL_INST_CYCLES_VMEM_DATA', + 80: 'SQ_PERF_SEL_INST_CYCLES_VMEM_CMD', + 81: 'SQ_PERF_SEL_INST_CYCLES_EXP', + 82: 'SQ_PERF_SEL_INST_CYCLES_GDS', + 83: 'SQ_PERF_SEL_INST_CYCLES_SMEM', + 84: 'SQ_PERF_SEL_INST_CYCLES_SALU', + 85: 'SQ_PERF_SEL_THREAD_CYCLES_VALU', + 86: 'SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX', + 87: 'SQ_PERF_SEL_IFETCH', + 88: 'SQ_PERF_SEL_IFETCH_LEVEL', + 89: 'SQ_PERF_SEL_CBRANCH_FORK', + 90: 'SQ_PERF_SEL_CBRANCH_FORK_SPLIT', + 91: 'SQ_PERF_SEL_VALU_LDS_DIRECT_RD', + 92: 'SQ_PERF_SEL_VALU_LDS_INTERP_OP', + 93: 'SQ_PERF_SEL_LDS_BANK_CONFLICT', + 94: 'SQ_PERF_SEL_LDS_ADDR_CONFLICT', + 95: 'SQ_PERF_SEL_LDS_UNALIGNED_STALL', + 96: 'SQ_PERF_SEL_LDS_MEM_VIOLATIONS', + 97: 'SQ_PERF_SEL_LDS_ATOMIC_RETURN', + 98: 'SQ_PERF_SEL_LDS_IDX_ACTIVE', + 99: 'SQ_PERF_SEL_VALU_DEP_STALL', + 100: 'SQ_PERF_SEL_VALU_STARVE', + 101: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 102: 'SQ_PERF_SEL_LDS_DATA_FIFO_FULL', + 103: 'SQ_PERF_SEL_LDS_CMD_FIFO_FULL', + 104: 'SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL', + 105: 'SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL', + 106: 'SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY', + 107: 'SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL', + 108: 'SQ_PERF_SEL_VALU_SRC_C_CONFLICT', + 109: 'SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT', + 110: 'SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT', + 111: 'SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT', + 112: 'SQ_PERF_SEL_LDS_SRC_CD_CONFLICT', + 113: 'SQ_PERF_SEL_SRC_CD_BUSY', + 114: 'SQ_PERF_SEL_PT_POWER_STALL', + 115: 'SQ_PERF_SEL_USER0', + 116: 'SQ_PERF_SEL_USER1', + 117: 'SQ_PERF_SEL_USER2', + 118: 'SQ_PERF_SEL_USER3', + 119: 'SQ_PERF_SEL_USER4', + 120: 'SQ_PERF_SEL_USER5', + 121: 'SQ_PERF_SEL_USER6', + 122: 'SQ_PERF_SEL_USER7', + 123: 'SQ_PERF_SEL_USER8', + 124: 'SQ_PERF_SEL_USER9', + 125: 'SQ_PERF_SEL_USER10', + 126: 'SQ_PERF_SEL_USER11', + 127: 'SQ_PERF_SEL_USER12', + 128: 'SQ_PERF_SEL_USER13', + 129: 'SQ_PERF_SEL_USER14', + 130: 'SQ_PERF_SEL_USER15', + 131: 'SQ_PERF_SEL_USER_LEVEL0', + 132: 'SQ_PERF_SEL_USER_LEVEL1', + 133: 'SQ_PERF_SEL_USER_LEVEL2', + 134: 'SQ_PERF_SEL_USER_LEVEL3', + 135: 'SQ_PERF_SEL_USER_LEVEL4', + 136: 'SQ_PERF_SEL_USER_LEVEL5', + 137: 'SQ_PERF_SEL_USER_LEVEL6', + 138: 'SQ_PERF_SEL_USER_LEVEL7', + 139: 'SQ_PERF_SEL_USER_LEVEL8', + 140: 'SQ_PERF_SEL_USER_LEVEL9', + 141: 'SQ_PERF_SEL_USER_LEVEL10', + 142: 'SQ_PERF_SEL_USER_LEVEL11', + 143: 'SQ_PERF_SEL_USER_LEVEL12', + 144: 'SQ_PERF_SEL_USER_LEVEL13', + 145: 'SQ_PERF_SEL_USER_LEVEL14', + 146: 'SQ_PERF_SEL_USER_LEVEL15', + 147: 'SQ_PERF_SEL_POWER_VALU', + 148: 'SQ_PERF_SEL_POWER_VALU0', + 149: 'SQ_PERF_SEL_POWER_VALU1', + 150: 'SQ_PERF_SEL_POWER_VALU2', + 151: 'SQ_PERF_SEL_POWER_GPR_RD', + 152: 'SQ_PERF_SEL_POWER_GPR_WR', + 153: 'SQ_PERF_SEL_POWER_LDS_BUSY', + 154: 'SQ_PERF_SEL_POWER_ALU_BUSY', + 155: 'SQ_PERF_SEL_POWER_TEX_BUSY', + 156: 'SQ_PERF_SEL_ACCUM_PREV_HIRES', + 157: 'SQ_PERF_SEL_WAVES_RESTORED', + 158: 'SQ_PERF_SEL_WAVES_SAVED', + 159: 'SQ_PERF_SEL_INSTS_SMEM_NORM', + 160: 'SQ_PERF_SEL_ATC_INSTS_VMEM', + 161: 'SQ_PERF_SEL_ATC_INST_LEVEL_VMEM', + 162: 'SQ_PERF_SEL_ATC_XNACK_FIRST', + 163: 'SQ_PERF_SEL_ATC_XNACK_ALL', + 164: 'SQ_PERF_SEL_ATC_XNACK_FIFO_FULL', + 165: 'SQ_PERF_SEL_ATC_INSTS_SMEM', + 166: 'SQ_PERF_SEL_ATC_INST_LEVEL_SMEM', + 167: 'SQ_PERF_SEL_IFETCH_XNACK', + 168: 'SQ_PERF_SEL_TLB_SHOOTDOWN', + 169: 'SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES', + 170: 'SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY', + 171: 'SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY', + 172: 'SQ_PERF_SEL_INSTS_VMEM_REPLAY', + 173: 'SQ_PERF_SEL_INSTS_SMEM_REPLAY', + 174: 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY', + 175: 'SQ_PERF_SEL_INSTS_FLAT_REPLAY', + 176: 'SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY', + 177: 'SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY', + 178: 'SQ_PERF_SEL_UTCL1_TRANSLATION_MISS', + 179: 'SQ_PERF_SEL_UTCL1_PERMISSION_MISS', + 180: 'SQ_PERF_SEL_UTCL1_REQUEST', + 181: 'SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 182: 'SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 183: 'SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 184: 'SQ_PERF_SEL_UTCL1_LFIFO_FULL', + 185: 'SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 186: 'SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 187: 'SQ_PERF_SEL_DUMMY_END', + 255: 'SQ_PERF_SEL_DUMMY_LAST', + 256: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY', + 257: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 258: 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB', + 259: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY', + 260: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 261: 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB', + 262: 'SQC_PERF_SEL_TC_REQ', + 263: 'SQC_PERF_SEL_TC_INST_REQ', + 264: 'SQC_PERF_SEL_TC_DATA_READ_REQ', + 265: 'SQC_PERF_SEL_TC_DATA_WRITE_REQ', + 266: 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ', + 267: 'SQC_PERF_SEL_TC_STALL', + 268: 'SQC_PERF_SEL_TC_STARVE', + 269: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 270: 'SQC_PERF_SEL_ICACHE_REQ', + 271: 'SQC_PERF_SEL_ICACHE_HITS', + 272: 'SQC_PERF_SEL_ICACHE_MISSES', + 273: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', + 274: 'SQC_PERF_SEL_ICACHE_INVAL_INST', + 275: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 276: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 277: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 278: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 279: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO', + 280: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 281: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT', + 282: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO', + 283: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO', + 284: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF', + 285: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 286: 'SQC_PERF_SEL_ICACHE_PREFETCH_1', + 287: 'SQC_PERF_SEL_ICACHE_PREFETCH_2', + 288: 'SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED', + 289: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 290: 'SQC_PERF_SEL_DCACHE_REQ', + 291: 'SQC_PERF_SEL_DCACHE_HITS', + 292: 'SQC_PERF_SEL_DCACHE_MISSES', + 293: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', + 294: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 295: 'SQC_PERF_SEL_DCACHE_MISS_EVICT_READ', + 296: 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE', + 297: 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', + 298: 'SQC_PERF_SEL_DCACHE_ATOMIC', + 299: 'SQC_PERF_SEL_DCACHE_VOLATILE', + 300: 'SQC_PERF_SEL_DCACHE_INVAL_INST', + 301: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 302: 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST', + 303: 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC', + 304: 'SQC_PERF_SEL_DCACHE_WB_INST', + 305: 'SQC_PERF_SEL_DCACHE_WB_ASYNC', + 306: 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST', + 307: 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC', + 308: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 309: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 310: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 311: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 312: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 313: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT', + 314: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED', + 315: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE', + 316: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT', + 317: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH', + 318: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE', + 319: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO', + 320: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO', + 321: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF', + 322: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 323: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 324: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 325: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 326: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', + 327: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 328: 'SQC_PERF_SEL_DCACHE_REQ_TIME', + 329: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1', + 330: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2', + 331: 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4', + 332: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 333: 'SQC_PERF_SEL_SQ_DCACHE_REQS', + 334: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', + 335: 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', + 336: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 337: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 338: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', + 339: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 340: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 341: 'SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS', + 342: 'SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS', + 343: 'SQC_PERF_SEL_ICACHE_GATCL1_REQUEST', + 344: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX', + 345: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT', + 346: 'SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL', + 347: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES', + 348: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', + 349: 'SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT', + 350: 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL', + 351: 'SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS', + 352: 'SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS', + 353: 'SQC_PERF_SEL_DCACHE_GATCL1_REQUEST', + 354: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX', + 355: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT', + 356: 'SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL', + 357: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES', + 358: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', + 359: 'SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT', + 360: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL', + 361: 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS', + 362: 'SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL', + 363: 'SQC_PERF_SEL_DUMMY_LAST', +} +SQ_PERF_SEL_NONE = 0 +SQ_PERF_SEL_ACCUM_PREV = 1 +SQ_PERF_SEL_CYCLES = 2 +SQ_PERF_SEL_BUSY_CYCLES = 3 +SQ_PERF_SEL_WAVES = 4 +SQ_PERF_SEL_LEVEL_WAVES = 5 +SQ_PERF_SEL_WAVES_EQ_64 = 6 +SQ_PERF_SEL_WAVES_LT_64 = 7 +SQ_PERF_SEL_WAVES_LT_48 = 8 +SQ_PERF_SEL_WAVES_LT_32 = 9 +SQ_PERF_SEL_WAVES_LT_16 = 10 +SQ_PERF_SEL_WAVES_CU = 11 +SQ_PERF_SEL_LEVEL_WAVES_CU = 12 +SQ_PERF_SEL_BUSY_CU_CYCLES = 13 +SQ_PERF_SEL_ITEMS = 14 +SQ_PERF_SEL_QUADS = 15 +SQ_PERF_SEL_EVENTS = 16 +SQ_PERF_SEL_SURF_SYNCS = 17 +SQ_PERF_SEL_TTRACE_REQS = 18 +SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 19 +SQ_PERF_SEL_TTRACE_STALL = 20 +SQ_PERF_SEL_MSG_CNTR = 21 +SQ_PERF_SEL_MSG_PERF = 22 +SQ_PERF_SEL_MSG_GSCNT = 23 +SQ_PERF_SEL_MSG_INTERRUPT = 24 +SQ_PERF_SEL_INSTS = 25 +SQ_PERF_SEL_INSTS_VALU = 26 +SQ_PERF_SEL_INSTS_VMEM_WR = 27 +SQ_PERF_SEL_INSTS_VMEM_RD = 28 +SQ_PERF_SEL_INSTS_VMEM = 29 +SQ_PERF_SEL_INSTS_SALU = 30 +SQ_PERF_SEL_INSTS_SMEM = 31 +SQ_PERF_SEL_INSTS_FLAT = 32 +SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 33 +SQ_PERF_SEL_INSTS_LDS = 34 +SQ_PERF_SEL_INSTS_GDS = 35 +SQ_PERF_SEL_INSTS_EXP = 36 +SQ_PERF_SEL_INSTS_EXP_GDS = 37 +SQ_PERF_SEL_INSTS_BRANCH = 38 +SQ_PERF_SEL_INSTS_SENDMSG = 39 +SQ_PERF_SEL_INSTS_VSKIPPED = 40 +SQ_PERF_SEL_INST_LEVEL_VMEM = 41 +SQ_PERF_SEL_INST_LEVEL_SMEM = 42 +SQ_PERF_SEL_INST_LEVEL_LDS = 43 +SQ_PERF_SEL_INST_LEVEL_GDS = 44 +SQ_PERF_SEL_INST_LEVEL_EXP = 45 +SQ_PERF_SEL_WAVE_CYCLES = 46 +SQ_PERF_SEL_WAVE_READY = 47 +SQ_PERF_SEL_WAIT_CNT_VM = 48 +SQ_PERF_SEL_WAIT_CNT_LGKM = 49 +SQ_PERF_SEL_WAIT_CNT_EXP = 50 +SQ_PERF_SEL_WAIT_CNT_ANY = 51 +SQ_PERF_SEL_WAIT_BARRIER = 52 +SQ_PERF_SEL_WAIT_EXP_ALLOC = 53 +SQ_PERF_SEL_WAIT_SLEEP = 54 +SQ_PERF_SEL_WAIT_SLEEP_XNACK = 55 +SQ_PERF_SEL_WAIT_OTHER = 56 +SQ_PERF_SEL_WAIT_ANY = 57 +SQ_PERF_SEL_WAIT_TTRACE = 58 +SQ_PERF_SEL_WAIT_IFETCH = 59 +SQ_PERF_SEL_WAIT_INST_ANY = 60 +SQ_PERF_SEL_WAIT_INST_VMEM = 61 +SQ_PERF_SEL_WAIT_INST_SCA = 62 +SQ_PERF_SEL_WAIT_INST_LDS = 63 +SQ_PERF_SEL_WAIT_INST_VALU = 64 +SQ_PERF_SEL_WAIT_INST_EXP_GDS = 65 +SQ_PERF_SEL_WAIT_INST_MISC = 66 +SQ_PERF_SEL_WAIT_INST_FLAT = 67 +SQ_PERF_SEL_ACTIVE_INST_ANY = 68 +SQ_PERF_SEL_ACTIVE_INST_VMEM = 69 +SQ_PERF_SEL_ACTIVE_INST_LDS = 70 +SQ_PERF_SEL_ACTIVE_INST_VALU = 71 +SQ_PERF_SEL_ACTIVE_INST_SCA = 72 +SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 73 +SQ_PERF_SEL_ACTIVE_INST_MISC = 74 +SQ_PERF_SEL_ACTIVE_INST_FLAT = 75 +SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 76 +SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 77 +SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 78 +SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 79 +SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 80 +SQ_PERF_SEL_INST_CYCLES_EXP = 81 +SQ_PERF_SEL_INST_CYCLES_GDS = 82 +SQ_PERF_SEL_INST_CYCLES_SMEM = 83 +SQ_PERF_SEL_INST_CYCLES_SALU = 84 +SQ_PERF_SEL_THREAD_CYCLES_VALU = 85 +SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 86 +SQ_PERF_SEL_IFETCH = 87 +SQ_PERF_SEL_IFETCH_LEVEL = 88 +SQ_PERF_SEL_CBRANCH_FORK = 89 +SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 90 +SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 91 +SQ_PERF_SEL_VALU_LDS_INTERP_OP = 92 +SQ_PERF_SEL_LDS_BANK_CONFLICT = 93 +SQ_PERF_SEL_LDS_ADDR_CONFLICT = 94 +SQ_PERF_SEL_LDS_UNALIGNED_STALL = 95 +SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 96 +SQ_PERF_SEL_LDS_ATOMIC_RETURN = 97 +SQ_PERF_SEL_LDS_IDX_ACTIVE = 98 +SQ_PERF_SEL_VALU_DEP_STALL = 99 +SQ_PERF_SEL_VALU_STARVE = 100 +SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 101 +SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 102 +SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 103 +SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 104 +SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 105 +SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 106 +SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 107 +SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 108 +SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 109 +SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 110 +SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 111 +SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 112 +SQ_PERF_SEL_SRC_CD_BUSY = 113 +SQ_PERF_SEL_PT_POWER_STALL = 114 +SQ_PERF_SEL_USER0 = 115 +SQ_PERF_SEL_USER1 = 116 +SQ_PERF_SEL_USER2 = 117 +SQ_PERF_SEL_USER3 = 118 +SQ_PERF_SEL_USER4 = 119 +SQ_PERF_SEL_USER5 = 120 +SQ_PERF_SEL_USER6 = 121 +SQ_PERF_SEL_USER7 = 122 +SQ_PERF_SEL_USER8 = 123 +SQ_PERF_SEL_USER9 = 124 +SQ_PERF_SEL_USER10 = 125 +SQ_PERF_SEL_USER11 = 126 +SQ_PERF_SEL_USER12 = 127 +SQ_PERF_SEL_USER13 = 128 +SQ_PERF_SEL_USER14 = 129 +SQ_PERF_SEL_USER15 = 130 +SQ_PERF_SEL_USER_LEVEL0 = 131 +SQ_PERF_SEL_USER_LEVEL1 = 132 +SQ_PERF_SEL_USER_LEVEL2 = 133 +SQ_PERF_SEL_USER_LEVEL3 = 134 +SQ_PERF_SEL_USER_LEVEL4 = 135 +SQ_PERF_SEL_USER_LEVEL5 = 136 +SQ_PERF_SEL_USER_LEVEL6 = 137 +SQ_PERF_SEL_USER_LEVEL7 = 138 +SQ_PERF_SEL_USER_LEVEL8 = 139 +SQ_PERF_SEL_USER_LEVEL9 = 140 +SQ_PERF_SEL_USER_LEVEL10 = 141 +SQ_PERF_SEL_USER_LEVEL11 = 142 +SQ_PERF_SEL_USER_LEVEL12 = 143 +SQ_PERF_SEL_USER_LEVEL13 = 144 +SQ_PERF_SEL_USER_LEVEL14 = 145 +SQ_PERF_SEL_USER_LEVEL15 = 146 +SQ_PERF_SEL_POWER_VALU = 147 +SQ_PERF_SEL_POWER_VALU0 = 148 +SQ_PERF_SEL_POWER_VALU1 = 149 +SQ_PERF_SEL_POWER_VALU2 = 150 +SQ_PERF_SEL_POWER_GPR_RD = 151 +SQ_PERF_SEL_POWER_GPR_WR = 152 +SQ_PERF_SEL_POWER_LDS_BUSY = 153 +SQ_PERF_SEL_POWER_ALU_BUSY = 154 +SQ_PERF_SEL_POWER_TEX_BUSY = 155 +SQ_PERF_SEL_ACCUM_PREV_HIRES = 156 +SQ_PERF_SEL_WAVES_RESTORED = 157 +SQ_PERF_SEL_WAVES_SAVED = 158 +SQ_PERF_SEL_INSTS_SMEM_NORM = 159 +SQ_PERF_SEL_ATC_INSTS_VMEM = 160 +SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 161 +SQ_PERF_SEL_ATC_XNACK_FIRST = 162 +SQ_PERF_SEL_ATC_XNACK_ALL = 163 +SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 164 +SQ_PERF_SEL_ATC_INSTS_SMEM = 165 +SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 166 +SQ_PERF_SEL_IFETCH_XNACK = 167 +SQ_PERF_SEL_TLB_SHOOTDOWN = 168 +SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 169 +SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 170 +SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 171 +SQ_PERF_SEL_INSTS_VMEM_REPLAY = 172 +SQ_PERF_SEL_INSTS_SMEM_REPLAY = 173 +SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 174 +SQ_PERF_SEL_INSTS_FLAT_REPLAY = 175 +SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 176 +SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 177 +SQ_PERF_SEL_UTCL1_TRANSLATION_MISS = 178 +SQ_PERF_SEL_UTCL1_PERMISSION_MISS = 179 +SQ_PERF_SEL_UTCL1_REQUEST = 180 +SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 181 +SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 182 +SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 183 +SQ_PERF_SEL_UTCL1_LFIFO_FULL = 184 +SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 185 +SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 186 +SQ_PERF_SEL_DUMMY_END = 187 +SQ_PERF_SEL_DUMMY_LAST = 255 +SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 256 +SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 257 +SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 258 +SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 259 +SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 260 +SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 261 +SQC_PERF_SEL_TC_REQ = 262 +SQC_PERF_SEL_TC_INST_REQ = 263 +SQC_PERF_SEL_TC_DATA_READ_REQ = 264 +SQC_PERF_SEL_TC_DATA_WRITE_REQ = 265 +SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 266 +SQC_PERF_SEL_TC_STALL = 267 +SQC_PERF_SEL_TC_STARVE = 268 +SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 269 +SQC_PERF_SEL_ICACHE_REQ = 270 +SQC_PERF_SEL_ICACHE_HITS = 271 +SQC_PERF_SEL_ICACHE_MISSES = 272 +SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 273 +SQC_PERF_SEL_ICACHE_INVAL_INST = 274 +SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 275 +SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 276 +SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 277 +SQC_PERF_SEL_ICACHE_CACHE_STALLED = 278 +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 279 +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 280 +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 281 +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 282 +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 283 +SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 284 +SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 285 +SQC_PERF_SEL_ICACHE_PREFETCH_1 = 286 +SQC_PERF_SEL_ICACHE_PREFETCH_2 = 287 +SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED = 288 +SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 289 +SQC_PERF_SEL_DCACHE_REQ = 290 +SQC_PERF_SEL_DCACHE_HITS = 291 +SQC_PERF_SEL_DCACHE_MISSES = 292 +SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 293 +SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 294 +SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 295 +SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 296 +SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 297 +SQC_PERF_SEL_DCACHE_ATOMIC = 298 +SQC_PERF_SEL_DCACHE_VOLATILE = 299 +SQC_PERF_SEL_DCACHE_INVAL_INST = 300 +SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 301 +SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 302 +SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 303 +SQC_PERF_SEL_DCACHE_WB_INST = 304 +SQC_PERF_SEL_DCACHE_WB_ASYNC = 305 +SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 306 +SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 307 +SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 308 +SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 309 +SQC_PERF_SEL_DCACHE_CACHE_STALLED = 310 +SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 311 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 312 +SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 313 +SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 314 +SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 315 +SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 316 +SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 317 +SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 318 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 319 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 320 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 321 +SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 322 +SQC_PERF_SEL_DCACHE_REQ_READ_1 = 323 +SQC_PERF_SEL_DCACHE_REQ_READ_2 = 324 +SQC_PERF_SEL_DCACHE_REQ_READ_4 = 325 +SQC_PERF_SEL_DCACHE_REQ_READ_8 = 326 +SQC_PERF_SEL_DCACHE_REQ_READ_16 = 327 +SQC_PERF_SEL_DCACHE_REQ_TIME = 328 +SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 329 +SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 330 +SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 331 +SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 332 +SQC_PERF_SEL_SQ_DCACHE_REQS = 333 +SQC_PERF_SEL_DCACHE_FLAT_REQ = 334 +SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 335 +SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 336 +SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 337 +SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 338 +SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 339 +SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 340 +SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 341 +SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 342 +SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 343 +SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 344 +SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 345 +SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 346 +SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 347 +SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 348 +SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 349 +SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 350 +SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 351 +SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 352 +SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 353 +SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 354 +SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 355 +SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 356 +SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 357 +SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS = 358 +SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 359 +SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 360 +SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 361 +SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 362 +SQC_PERF_SEL_DUMMY_LAST = 363 +SQ_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_CAC_POWER_SEL' +SQ_CAC_POWER_SEL__enumvalues = { + 0: 'SQ_CAC_POWER_VALU', + 1: 'SQ_CAC_POWER_VALU0', + 2: 'SQ_CAC_POWER_VALU1', + 3: 'SQ_CAC_POWER_VALU2', + 4: 'SQ_CAC_POWER_GPR_RD', + 5: 'SQ_CAC_POWER_GPR_WR', + 6: 'SQ_CAC_POWER_LDS_BUSY', + 7: 'SQ_CAC_POWER_ALU_BUSY', + 8: 'SQ_CAC_POWER_TEX_BUSY', +} +SQ_CAC_POWER_VALU = 0 +SQ_CAC_POWER_VALU0 = 1 +SQ_CAC_POWER_VALU1 = 2 +SQ_CAC_POWER_VALU2 = 3 +SQ_CAC_POWER_GPR_RD = 4 +SQ_CAC_POWER_GPR_WR = 5 +SQ_CAC_POWER_LDS_BUSY = 6 +SQ_CAC_POWER_ALU_BUSY = 7 +SQ_CAC_POWER_TEX_BUSY = 8 +SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_CMD' +SQ_IND_CMD_CMD__enumvalues = { + 0: 'SQ_IND_CMD_CMD_NULL', + 1: 'SQ_IND_CMD_CMD_SETHALT', + 2: 'SQ_IND_CMD_CMD_SAVECTX', + 3: 'SQ_IND_CMD_CMD_KILL', + 4: 'SQ_IND_CMD_CMD_DEBUG', + 5: 'SQ_IND_CMD_CMD_TRAP', + 6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO', + 7: 'SQ_IND_CMD_CMD_SETFATALHALT', +} +SQ_IND_CMD_CMD_NULL = 0 +SQ_IND_CMD_CMD_SETHALT = 1 +SQ_IND_CMD_CMD_SAVECTX = 2 +SQ_IND_CMD_CMD_KILL = 3 +SQ_IND_CMD_CMD_DEBUG = 4 +SQ_IND_CMD_CMD_TRAP = 5 +SQ_IND_CMD_CMD_SET_SPI_PRIO = 6 +SQ_IND_CMD_CMD_SETFATALHALT = 7 +SQ_IND_CMD_CMD = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_MODE' +SQ_IND_CMD_MODE__enumvalues = { + 0: 'SQ_IND_CMD_MODE_SINGLE', + 1: 'SQ_IND_CMD_MODE_BROADCAST', + 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', + 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', +} +SQ_IND_CMD_MODE_SINGLE = 0 +SQ_IND_CMD_MODE_BROADCAST = 1 +SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 +SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 +SQ_IND_CMD_MODE_BROADCAST_ME = 4 +SQ_IND_CMD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_EDC_INFO_SOURCE' +SQ_EDC_INFO_SOURCE__enumvalues = { + 0: 'SQ_EDC_INFO_SOURCE_INVALID', + 1: 'SQ_EDC_INFO_SOURCE_INST', + 2: 'SQ_EDC_INFO_SOURCE_SGPR', + 3: 'SQ_EDC_INFO_SOURCE_VGPR', + 4: 'SQ_EDC_INFO_SOURCE_LDS', + 5: 'SQ_EDC_INFO_SOURCE_GDS', + 6: 'SQ_EDC_INFO_SOURCE_TA', +} +SQ_EDC_INFO_SOURCE_INVALID = 0 +SQ_EDC_INFO_SOURCE_INST = 1 +SQ_EDC_INFO_SOURCE_SGPR = 2 +SQ_EDC_INFO_SOURCE_VGPR = 3 +SQ_EDC_INFO_SOURCE_LDS = 4 +SQ_EDC_INFO_SOURCE_GDS = 5 +SQ_EDC_INFO_SOURCE_TA = 6 +SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_ROUND_MODE' +SQ_ROUND_MODE__enumvalues = { + 0: 'SQ_ROUND_NEAREST_EVEN', + 1: 'SQ_ROUND_PLUS_INFINITY', + 2: 'SQ_ROUND_MINUS_INFINITY', + 3: 'SQ_ROUND_TO_ZERO', +} +SQ_ROUND_NEAREST_EVEN = 0 +SQ_ROUND_PLUS_INFINITY = 1 +SQ_ROUND_MINUS_INFINITY = 2 +SQ_ROUND_TO_ZERO = 3 +SQ_ROUND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INTERRUPT_WORD_ENCODING' +SQ_INTERRUPT_WORD_ENCODING__enumvalues = { + 0: 'SQ_INTERRUPT_WORD_ENCODING_AUTO', + 1: 'SQ_INTERRUPT_WORD_ENCODING_INST', + 2: 'SQ_INTERRUPT_WORD_ENCODING_ERROR', +} +SQ_INTERRUPT_WORD_ENCODING_AUTO = 0 +SQ_INTERRUPT_WORD_ENCODING_INST = 1 +SQ_INTERRUPT_WORD_ENCODING_ERROR = 2 +SQ_INTERRUPT_WORD_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_SQ_EXPORT_RAT_INST' +ENUM_SQ_EXPORT_RAT_INST__enumvalues = { + 0: 'SQ_EXPORT_RAT_INST_NOP', + 1: 'SQ_EXPORT_RAT_INST_STORE_TYPED', + 2: 'SQ_EXPORT_RAT_INST_STORE_RAW', + 3: 'SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM', + 4: 'SQ_EXPORT_RAT_INST_CMPXCHG_INT', + 5: 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT', + 6: 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM', + 7: 'SQ_EXPORT_RAT_INST_ADD', + 8: 'SQ_EXPORT_RAT_INST_SUB', + 9: 'SQ_EXPORT_RAT_INST_RSUB', + 10: 'SQ_EXPORT_RAT_INST_MIN_INT', + 11: 'SQ_EXPORT_RAT_INST_MIN_UINT', + 12: 'SQ_EXPORT_RAT_INST_MAX_INT', + 13: 'SQ_EXPORT_RAT_INST_MAX_UINT', + 14: 'SQ_EXPORT_RAT_INST_AND', + 15: 'SQ_EXPORT_RAT_INST_OR', + 16: 'SQ_EXPORT_RAT_INST_XOR', + 17: 'SQ_EXPORT_RAT_INST_MSKOR', + 18: 'SQ_EXPORT_RAT_INST_INC_UINT', + 19: 'SQ_EXPORT_RAT_INST_DEC_UINT', + 20: 'SQ_EXPORT_RAT_INST_STORE_DWORD', + 21: 'SQ_EXPORT_RAT_INST_STORE_SHORT', + 22: 'SQ_EXPORT_RAT_INST_STORE_BYTE', + 32: 'SQ_EXPORT_RAT_INST_NOP_RTN', + 34: 'SQ_EXPORT_RAT_INST_XCHG_RTN', + 35: 'SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN', + 36: 'SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN', + 37: 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN', + 38: 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN', + 39: 'SQ_EXPORT_RAT_INST_ADD_RTN', + 40: 'SQ_EXPORT_RAT_INST_SUB_RTN', + 41: 'SQ_EXPORT_RAT_INST_RSUB_RTN', + 42: 'SQ_EXPORT_RAT_INST_MIN_INT_RTN', + 43: 'SQ_EXPORT_RAT_INST_MIN_UINT_RTN', + 44: 'SQ_EXPORT_RAT_INST_MAX_INT_RTN', + 45: 'SQ_EXPORT_RAT_INST_MAX_UINT_RTN', + 46: 'SQ_EXPORT_RAT_INST_AND_RTN', + 47: 'SQ_EXPORT_RAT_INST_OR_RTN', + 48: 'SQ_EXPORT_RAT_INST_XOR_RTN', + 49: 'SQ_EXPORT_RAT_INST_MSKOR_RTN', + 50: 'SQ_EXPORT_RAT_INST_INC_UINT_RTN', + 51: 'SQ_EXPORT_RAT_INST_DEC_UINT_RTN', +} +SQ_EXPORT_RAT_INST_NOP = 0 +SQ_EXPORT_RAT_INST_STORE_TYPED = 1 +SQ_EXPORT_RAT_INST_STORE_RAW = 2 +SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 3 +SQ_EXPORT_RAT_INST_CMPXCHG_INT = 4 +SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 5 +SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 6 +SQ_EXPORT_RAT_INST_ADD = 7 +SQ_EXPORT_RAT_INST_SUB = 8 +SQ_EXPORT_RAT_INST_RSUB = 9 +SQ_EXPORT_RAT_INST_MIN_INT = 10 +SQ_EXPORT_RAT_INST_MIN_UINT = 11 +SQ_EXPORT_RAT_INST_MAX_INT = 12 +SQ_EXPORT_RAT_INST_MAX_UINT = 13 +SQ_EXPORT_RAT_INST_AND = 14 +SQ_EXPORT_RAT_INST_OR = 15 +SQ_EXPORT_RAT_INST_XOR = 16 +SQ_EXPORT_RAT_INST_MSKOR = 17 +SQ_EXPORT_RAT_INST_INC_UINT = 18 +SQ_EXPORT_RAT_INST_DEC_UINT = 19 +SQ_EXPORT_RAT_INST_STORE_DWORD = 20 +SQ_EXPORT_RAT_INST_STORE_SHORT = 21 +SQ_EXPORT_RAT_INST_STORE_BYTE = 22 +SQ_EXPORT_RAT_INST_NOP_RTN = 32 +SQ_EXPORT_RAT_INST_XCHG_RTN = 34 +SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 35 +SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 36 +SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 37 +SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 38 +SQ_EXPORT_RAT_INST_ADD_RTN = 39 +SQ_EXPORT_RAT_INST_SUB_RTN = 40 +SQ_EXPORT_RAT_INST_RSUB_RTN = 41 +SQ_EXPORT_RAT_INST_MIN_INT_RTN = 42 +SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 43 +SQ_EXPORT_RAT_INST_MAX_INT_RTN = 44 +SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 45 +SQ_EXPORT_RAT_INST_AND_RTN = 46 +SQ_EXPORT_RAT_INST_OR_RTN = 47 +SQ_EXPORT_RAT_INST_XOR_RTN = 48 +SQ_EXPORT_RAT_INST_MSKOR_RTN = 49 +SQ_EXPORT_RAT_INST_INC_UINT_RTN = 50 +SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 51 +ENUM_SQ_EXPORT_RAT_INST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IBUF_ST' +SQ_IBUF_ST__enumvalues = { + 0: 'SQ_IBUF_IB_IDLE', + 1: 'SQ_IBUF_IB_INI_WAIT_GNT', + 2: 'SQ_IBUF_IB_INI_WAIT_DRET', + 3: 'SQ_IBUF_IB_LE_4DW', + 4: 'SQ_IBUF_IB_WAIT_DRET', + 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', + 6: 'SQ_IBUF_IB_DRET', + 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', +} +SQ_IBUF_IB_IDLE = 0 +SQ_IBUF_IB_INI_WAIT_GNT = 1 +SQ_IBUF_IB_INI_WAIT_DRET = 2 +SQ_IBUF_IB_LE_4DW = 3 +SQ_IBUF_IB_WAIT_DRET = 4 +SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 +SQ_IBUF_IB_DRET = 6 +SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 +SQ_IBUF_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INST_STR_ST' +SQ_INST_STR_ST__enumvalues = { + 0: 'SQ_INST_STR_IB_WAVE_NORML', + 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 4: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0', + 5: 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', + 6: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', + 7: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', +} +SQ_INST_STR_IB_WAVE_NORML = 0 +SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 +SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 +SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 +SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 4 +SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 5 +SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 6 +SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 7 +SQ_INST_STR_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_IB_ECC_ST' +SQ_WAVE_IB_ECC_ST__enumvalues = { + 0: 'SQ_WAVE_IB_ECC_CLEAN', + 1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE', + 2: 'SQ_WAVE_IB_ECC_ERR_HALT', + 3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', +} +SQ_WAVE_IB_ECC_CLEAN = 0 +SQ_WAVE_IB_ECC_ERR_CONTINUE = 1 +SQ_WAVE_IB_ECC_ERR_HALT = 2 +SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3 +SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ADDRESS_MODE' +SH_MEM_ADDRESS_MODE__enumvalues = { + 0: 'SH_MEM_ADDRESS_MODE_64', + 1: 'SH_MEM_ADDRESS_MODE_32', +} +SH_MEM_ADDRESS_MODE_64 = 0 +SH_MEM_ADDRESS_MODE_32 = 1 +SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ALIGNMENT_MODE' +SH_MEM_ALIGNMENT_MODE__enumvalues = { + 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', + 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', + 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', +} +SH_MEM_ALIGNMENT_MODE_DWORD = 0 +SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 +SH_MEM_ALIGNMENT_MODE_STRICT = 2 +SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 +SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX' +SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX__enumvalues = { + 24: 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC', + 25: 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE', +} +SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 24 +SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 25 +SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_LB_CTR_SEL_VALUES' +SQ_LB_CTR_SEL_VALUES__enumvalues = { + 0: 'SQ_LB_CTR_SEL_ALU_CYCLES', + 1: 'SQ_LB_CTR_SEL_ALU_STALLS', + 2: 'SQ_LB_CTR_SEL_TEX_CYCLES', + 3: 'SQ_LB_CTR_SEL_TEX_STALLS', + 4: 'SQ_LB_CTR_SEL_SALU_CYCLES', + 5: 'SQ_LB_CTR_SEL_SCALAR_STALLS', + 6: 'SQ_LB_CTR_SEL_SMEM_CYCLES', + 7: 'SQ_LB_CTR_SEL_ICACHE_STALLS', + 8: 'SQ_LB_CTR_SEL_DCACHE_STALLS', + 9: 'SQ_LB_CTR_SEL_RESERVED0', + 10: 'SQ_LB_CTR_SEL_RESERVED1', + 11: 'SQ_LB_CTR_SEL_RESERVED2', + 12: 'SQ_LB_CTR_SEL_RESERVED3', + 13: 'SQ_LB_CTR_SEL_RESERVED4', + 14: 'SQ_LB_CTR_SEL_RESERVED5', + 15: 'SQ_LB_CTR_SEL_RESERVED6', +} +SQ_LB_CTR_SEL_ALU_CYCLES = 0 +SQ_LB_CTR_SEL_ALU_STALLS = 1 +SQ_LB_CTR_SEL_TEX_CYCLES = 2 +SQ_LB_CTR_SEL_TEX_STALLS = 3 +SQ_LB_CTR_SEL_SALU_CYCLES = 4 +SQ_LB_CTR_SEL_SCALAR_STALLS = 5 +SQ_LB_CTR_SEL_SMEM_CYCLES = 6 +SQ_LB_CTR_SEL_ICACHE_STALLS = 7 +SQ_LB_CTR_SEL_DCACHE_STALLS = 8 +SQ_LB_CTR_SEL_RESERVED0 = 9 +SQ_LB_CTR_SEL_RESERVED1 = 10 +SQ_LB_CTR_SEL_RESERVED2 = 11 +SQ_LB_CTR_SEL_RESERVED3 = 12 +SQ_LB_CTR_SEL_RESERVED4 = 13 +SQ_LB_CTR_SEL_RESERVED5 = 14 +SQ_LB_CTR_SEL_RESERVED6 = 15 +SQ_LB_CTR_SEL_VALUES = ctypes.c_uint32 # enum + +# values for enumeration 'CSDATA_TYPE' +CSDATA_TYPE__enumvalues = { + 0: 'CSDATA_TYPE_TG', + 1: 'CSDATA_TYPE_STATE', + 2: 'CSDATA_TYPE_EVENT', + 3: 'CSDATA_TYPE_PRIVATE', +} +CSDATA_TYPE_TG = 0 +CSDATA_TYPE_STATE = 1 +CSDATA_TYPE_EVENT = 2 +CSDATA_TYPE_PRIVATE = 3 +CSDATA_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUT_PRIM_TYPE' +VGT_OUT_PRIM_TYPE__enumvalues = { + 0: 'VGT_OUT_POINT', + 1: 'VGT_OUT_LINE', + 2: 'VGT_OUT_TRI', + 3: 'VGT_OUT_RECT_V0', + 4: 'VGT_OUT_RECT_V1', + 5: 'VGT_OUT_RECT_V2', + 6: 'VGT_OUT_RECT_V3', + 7: 'VGT_OUT_2D_RECT', + 8: 'VGT_TE_QUAD', + 9: 'VGT_TE_PRIM_INDEX_LINE', + 10: 'VGT_TE_PRIM_INDEX_TRI', + 11: 'VGT_TE_PRIM_INDEX_QUAD', + 12: 'VGT_OUT_LINE_ADJ', + 13: 'VGT_OUT_TRI_ADJ', + 14: 'VGT_OUT_PATCH', +} +VGT_OUT_POINT = 0 +VGT_OUT_LINE = 1 +VGT_OUT_TRI = 2 +VGT_OUT_RECT_V0 = 3 +VGT_OUT_RECT_V1 = 4 +VGT_OUT_RECT_V2 = 5 +VGT_OUT_RECT_V3 = 6 +VGT_OUT_2D_RECT = 7 +VGT_TE_QUAD = 8 +VGT_TE_PRIM_INDEX_LINE = 9 +VGT_TE_PRIM_INDEX_TRI = 10 +VGT_TE_PRIM_INDEX_QUAD = 11 +VGT_OUT_LINE_ADJ = 12 +VGT_OUT_TRI_ADJ = 13 +VGT_OUT_PATCH = 14 +VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_PRIM_TYPE' +VGT_DI_PRIM_TYPE__enumvalues = { + 0: 'DI_PT_NONE', + 1: 'DI_PT_POINTLIST', + 2: 'DI_PT_LINELIST', + 3: 'DI_PT_LINESTRIP', + 4: 'DI_PT_TRILIST', + 5: 'DI_PT_TRIFAN', + 6: 'DI_PT_TRISTRIP', + 7: 'DI_PT_2D_RECTANGLE', + 8: 'DI_PT_UNUSED_1', + 9: 'DI_PT_PATCH', + 10: 'DI_PT_LINELIST_ADJ', + 11: 'DI_PT_LINESTRIP_ADJ', + 12: 'DI_PT_TRILIST_ADJ', + 13: 'DI_PT_TRISTRIP_ADJ', + 14: 'DI_PT_UNUSED_3', + 15: 'DI_PT_UNUSED_4', + 16: 'DI_PT_TRI_WITH_WFLAGS', + 17: 'DI_PT_RECTLIST', + 18: 'DI_PT_LINELOOP', + 19: 'DI_PT_QUADLIST', + 20: 'DI_PT_QUADSTRIP', + 21: 'DI_PT_POLYGON', +} +DI_PT_NONE = 0 +DI_PT_POINTLIST = 1 +DI_PT_LINELIST = 2 +DI_PT_LINESTRIP = 3 +DI_PT_TRILIST = 4 +DI_PT_TRIFAN = 5 +DI_PT_TRISTRIP = 6 +DI_PT_2D_RECTANGLE = 7 +DI_PT_UNUSED_1 = 8 +DI_PT_PATCH = 9 +DI_PT_LINELIST_ADJ = 10 +DI_PT_LINESTRIP_ADJ = 11 +DI_PT_TRILIST_ADJ = 12 +DI_PT_TRISTRIP_ADJ = 13 +DI_PT_UNUSED_3 = 14 +DI_PT_UNUSED_4 = 15 +DI_PT_TRI_WITH_WFLAGS = 16 +DI_PT_RECTLIST = 17 +DI_PT_LINELOOP = 18 +DI_PT_QUADLIST = 19 +DI_PT_QUADSTRIP = 20 +DI_PT_POLYGON = 21 +VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_SOURCE_SELECT' +VGT_DI_SOURCE_SELECT__enumvalues = { + 0: 'DI_SRC_SEL_DMA', + 1: 'DI_SRC_SEL_IMMEDIATE', + 2: 'DI_SRC_SEL_AUTO_INDEX', + 3: 'DI_SRC_SEL_RESERVED', +} +DI_SRC_SEL_DMA = 0 +DI_SRC_SEL_IMMEDIATE = 1 +DI_SRC_SEL_AUTO_INDEX = 2 +DI_SRC_SEL_RESERVED = 3 +VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_MAJOR_MODE_SELECT' +VGT_DI_MAJOR_MODE_SELECT__enumvalues = { + 0: 'DI_MAJOR_MODE_0', + 1: 'DI_MAJOR_MODE_1', +} +DI_MAJOR_MODE_0 = 0 +DI_MAJOR_MODE_1 = 1 +VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_INDEX_SIZE' +VGT_DI_INDEX_SIZE__enumvalues = { + 0: 'DI_INDEX_SIZE_16_BIT', + 1: 'DI_INDEX_SIZE_32_BIT', + 2: 'DI_INDEX_SIZE_8_BIT', +} +DI_INDEX_SIZE_16_BIT = 0 +DI_INDEX_SIZE_32_BIT = 1 +DI_INDEX_SIZE_8_BIT = 2 +VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_EVENT_TYPE' +VGT_EVENT_TYPE__enumvalues = { + 0: 'Reserved_0x00', + 1: 'SAMPLE_STREAMOUTSTATS1', + 2: 'SAMPLE_STREAMOUTSTATS2', + 3: 'SAMPLE_STREAMOUTSTATS3', + 4: 'CACHE_FLUSH_TS', + 5: 'CONTEXT_DONE', + 6: 'CACHE_FLUSH', + 7: 'CS_PARTIAL_FLUSH', + 8: 'VGT_STREAMOUT_SYNC', + 9: 'Reserved_0x09', + 10: 'VGT_STREAMOUT_RESET', + 11: 'END_OF_PIPE_INCR_DE', + 12: 'END_OF_PIPE_IB_END', + 13: 'RST_PIX_CNT', + 14: 'BREAK_BATCH', + 15: 'VS_PARTIAL_FLUSH', + 16: 'PS_PARTIAL_FLUSH', + 17: 'FLUSH_HS_OUTPUT', + 18: 'FLUSH_DFSM', + 19: 'RESET_TO_LOWEST_VGT', + 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', + 21: 'ZPASS_DONE', + 22: 'CACHE_FLUSH_AND_INV_EVENT', + 23: 'PERFCOUNTER_START', + 24: 'PERFCOUNTER_STOP', + 25: 'PIPELINESTAT_START', + 26: 'PIPELINESTAT_STOP', + 27: 'PERFCOUNTER_SAMPLE', + 28: 'Available_0x1c', + 29: 'Available_0x1d', + 30: 'SAMPLE_PIPELINESTAT', + 31: 'SO_VGTSTREAMOUT_FLUSH', + 32: 'SAMPLE_STREAMOUTSTATS', + 33: 'RESET_VTX_CNT', + 34: 'BLOCK_CONTEXT_DONE', + 35: 'CS_CONTEXT_DONE', + 36: 'VGT_FLUSH', + 37: 'TGID_ROLLOVER', + 38: 'SQ_NON_EVENT', + 39: 'SC_SEND_DB_VPZ', + 40: 'BOTTOM_OF_PIPE_TS', + 41: 'FLUSH_SX_TS', + 42: 'DB_CACHE_FLUSH_AND_INV', + 43: 'FLUSH_AND_INV_DB_DATA_TS', + 44: 'FLUSH_AND_INV_DB_META', + 45: 'FLUSH_AND_INV_CB_DATA_TS', + 46: 'FLUSH_AND_INV_CB_META', + 47: 'CS_DONE', + 48: 'PS_DONE', + 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', + 50: 'SX_CB_RAT_ACK_REQUEST', + 51: 'THREAD_TRACE_START', + 52: 'THREAD_TRACE_STOP', + 53: 'THREAD_TRACE_MARKER', + 54: 'THREAD_TRACE_FLUSH', + 55: 'THREAD_TRACE_FINISH', + 56: 'PIXEL_PIPE_STAT_CONTROL', + 57: 'PIXEL_PIPE_STAT_DUMP', + 58: 'PIXEL_PIPE_STAT_RESET', + 59: 'CONTEXT_SUSPEND', + 60: 'OFFCHIP_HS_DEALLOC', + 61: 'ENABLE_NGG_PIPELINE', + 62: 'ENABLE_LEGACY_PIPELINE', + 63: 'Reserved_0x3f', +} +Reserved_0x00 = 0 +SAMPLE_STREAMOUTSTATS1 = 1 +SAMPLE_STREAMOUTSTATS2 = 2 +SAMPLE_STREAMOUTSTATS3 = 3 +CACHE_FLUSH_TS = 4 +CONTEXT_DONE = 5 +CACHE_FLUSH = 6 +CS_PARTIAL_FLUSH = 7 +VGT_STREAMOUT_SYNC = 8 +Reserved_0x09 = 9 +VGT_STREAMOUT_RESET = 10 +END_OF_PIPE_INCR_DE = 11 +END_OF_PIPE_IB_END = 12 +RST_PIX_CNT = 13 +BREAK_BATCH = 14 +VS_PARTIAL_FLUSH = 15 +PS_PARTIAL_FLUSH = 16 +FLUSH_HS_OUTPUT = 17 +FLUSH_DFSM = 18 +RESET_TO_LOWEST_VGT = 19 +CACHE_FLUSH_AND_INV_TS_EVENT = 20 +ZPASS_DONE = 21 +CACHE_FLUSH_AND_INV_EVENT = 22 +PERFCOUNTER_START = 23 +PERFCOUNTER_STOP = 24 +PIPELINESTAT_START = 25 +PIPELINESTAT_STOP = 26 +PERFCOUNTER_SAMPLE = 27 +Available_0x1c = 28 +Available_0x1d = 29 +SAMPLE_PIPELINESTAT = 30 +SO_VGTSTREAMOUT_FLUSH = 31 +SAMPLE_STREAMOUTSTATS = 32 +RESET_VTX_CNT = 33 +BLOCK_CONTEXT_DONE = 34 +CS_CONTEXT_DONE = 35 +VGT_FLUSH = 36 +TGID_ROLLOVER = 37 +SQ_NON_EVENT = 38 +SC_SEND_DB_VPZ = 39 +BOTTOM_OF_PIPE_TS = 40 +FLUSH_SX_TS = 41 +DB_CACHE_FLUSH_AND_INV = 42 +FLUSH_AND_INV_DB_DATA_TS = 43 +FLUSH_AND_INV_DB_META = 44 +FLUSH_AND_INV_CB_DATA_TS = 45 +FLUSH_AND_INV_CB_META = 46 +CS_DONE = 47 +PS_DONE = 48 +FLUSH_AND_INV_CB_PIXEL_DATA = 49 +SX_CB_RAT_ACK_REQUEST = 50 +THREAD_TRACE_START = 51 +THREAD_TRACE_STOP = 52 +THREAD_TRACE_MARKER = 53 +THREAD_TRACE_FLUSH = 54 +THREAD_TRACE_FINISH = 55 +PIXEL_PIPE_STAT_CONTROL = 56 +PIXEL_PIPE_STAT_DUMP = 57 +PIXEL_PIPE_STAT_RESET = 58 +CONTEXT_SUSPEND = 59 +OFFCHIP_HS_DEALLOC = 60 +ENABLE_NGG_PIPELINE = 61 +ENABLE_LEGACY_PIPELINE = 62 +Reserved_0x3f = 63 +VGT_EVENT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_SWAP_MODE' +VGT_DMA_SWAP_MODE__enumvalues = { + 0: 'VGT_DMA_SWAP_NONE', + 1: 'VGT_DMA_SWAP_16_BIT', + 2: 'VGT_DMA_SWAP_32_BIT', + 3: 'VGT_DMA_SWAP_WORD', +} +VGT_DMA_SWAP_NONE = 0 +VGT_DMA_SWAP_16_BIT = 1 +VGT_DMA_SWAP_32_BIT = 2 +VGT_DMA_SWAP_WORD = 3 +VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_INDEX_TYPE_MODE' +VGT_INDEX_TYPE_MODE__enumvalues = { + 0: 'VGT_INDEX_16', + 1: 'VGT_INDEX_32', + 2: 'VGT_INDEX_8', +} +VGT_INDEX_16 = 0 +VGT_INDEX_32 = 1 +VGT_INDEX_8 = 2 +VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_BUF_TYPE' +VGT_DMA_BUF_TYPE__enumvalues = { + 0: 'VGT_DMA_BUF_MEM', + 1: 'VGT_DMA_BUF_RING', + 2: 'VGT_DMA_BUF_SETUP', + 3: 'VGT_DMA_PTR_UPDATE', +} +VGT_DMA_BUF_MEM = 0 +VGT_DMA_BUF_RING = 1 +VGT_DMA_BUF_SETUP = 2 +VGT_DMA_PTR_UPDATE = 3 +VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUTPATH_SELECT' +VGT_OUTPATH_SELECT__enumvalues = { + 0: 'VGT_OUTPATH_VTX_REUSE', + 1: 'VGT_OUTPATH_TESS_EN', + 2: 'VGT_OUTPATH_PASSTHRU', + 3: 'VGT_OUTPATH_GS_BLOCK', + 4: 'VGT_OUTPATH_HS_BLOCK', + 5: 'VGT_OUTPATH_PRIM_GEN', +} +VGT_OUTPATH_VTX_REUSE = 0 +VGT_OUTPATH_TESS_EN = 1 +VGT_OUTPATH_PASSTHRU = 2 +VGT_OUTPATH_GS_BLOCK = 3 +VGT_OUTPATH_HS_BLOCK = 4 +VGT_OUTPATH_PRIM_GEN = 5 +VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GRP_PRIM_TYPE' +VGT_GRP_PRIM_TYPE__enumvalues = { + 0: 'VGT_GRP_3D_POINT', + 1: 'VGT_GRP_3D_LINE', + 2: 'VGT_GRP_3D_TRI', + 3: 'VGT_GRP_3D_RECT', + 4: 'VGT_GRP_3D_QUAD', + 5: 'VGT_GRP_2D_COPY_RECT_V0', + 6: 'VGT_GRP_2D_COPY_RECT_V1', + 7: 'VGT_GRP_2D_COPY_RECT_V2', + 8: 'VGT_GRP_2D_COPY_RECT_V3', + 9: 'VGT_GRP_2D_FILL_RECT', + 10: 'VGT_GRP_2D_LINE', + 11: 'VGT_GRP_2D_TRI', + 12: 'VGT_GRP_PRIM_INDEX_LINE', + 13: 'VGT_GRP_PRIM_INDEX_TRI', + 14: 'VGT_GRP_PRIM_INDEX_QUAD', + 15: 'VGT_GRP_3D_LINE_ADJ', + 16: 'VGT_GRP_3D_TRI_ADJ', + 17: 'VGT_GRP_3D_PATCH', + 18: 'VGT_GRP_2D_RECT', +} +VGT_GRP_3D_POINT = 0 +VGT_GRP_3D_LINE = 1 +VGT_GRP_3D_TRI = 2 +VGT_GRP_3D_RECT = 3 +VGT_GRP_3D_QUAD = 4 +VGT_GRP_2D_COPY_RECT_V0 = 5 +VGT_GRP_2D_COPY_RECT_V1 = 6 +VGT_GRP_2D_COPY_RECT_V2 = 7 +VGT_GRP_2D_COPY_RECT_V3 = 8 +VGT_GRP_2D_FILL_RECT = 9 +VGT_GRP_2D_LINE = 10 +VGT_GRP_2D_TRI = 11 +VGT_GRP_PRIM_INDEX_LINE = 12 +VGT_GRP_PRIM_INDEX_TRI = 13 +VGT_GRP_PRIM_INDEX_QUAD = 14 +VGT_GRP_3D_LINE_ADJ = 15 +VGT_GRP_3D_TRI_ADJ = 16 +VGT_GRP_3D_PATCH = 17 +VGT_GRP_2D_RECT = 18 +VGT_GRP_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GRP_PRIM_ORDER' +VGT_GRP_PRIM_ORDER__enumvalues = { + 0: 'VGT_GRP_LIST', + 1: 'VGT_GRP_STRIP', + 2: 'VGT_GRP_FAN', + 3: 'VGT_GRP_LOOP', + 4: 'VGT_GRP_POLYGON', +} +VGT_GRP_LIST = 0 +VGT_GRP_STRIP = 1 +VGT_GRP_FAN = 2 +VGT_GRP_LOOP = 3 +VGT_GRP_POLYGON = 4 +VGT_GRP_PRIM_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GROUP_CONV_SEL' +VGT_GROUP_CONV_SEL__enumvalues = { + 0: 'VGT_GRP_INDEX_16', + 1: 'VGT_GRP_INDEX_32', + 2: 'VGT_GRP_UINT_16', + 3: 'VGT_GRP_UINT_32', + 4: 'VGT_GRP_SINT_16', + 5: 'VGT_GRP_SINT_32', + 6: 'VGT_GRP_FLOAT_32', + 7: 'VGT_GRP_AUTO_PRIM', + 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', +} +VGT_GRP_INDEX_16 = 0 +VGT_GRP_INDEX_32 = 1 +VGT_GRP_UINT_16 = 2 +VGT_GRP_UINT_32 = 3 +VGT_GRP_SINT_16 = 4 +VGT_GRP_SINT_32 = 5 +VGT_GRP_FLOAT_32 = 6 +VGT_GRP_AUTO_PRIM = 7 +VGT_GRP_FIX_1_23_TO_FLOAT = 8 +VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_MODE_TYPE' +VGT_GS_MODE_TYPE__enumvalues = { + 0: 'GS_OFF', + 1: 'GS_SCENARIO_A', + 2: 'GS_SCENARIO_B', + 3: 'GS_SCENARIO_G', + 4: 'GS_SCENARIO_C', + 5: 'SPRITE_EN', +} +GS_OFF = 0 +GS_SCENARIO_A = 1 +GS_SCENARIO_B = 2 +GS_SCENARIO_G = 3 +GS_SCENARIO_C = 4 +SPRITE_EN = 5 +VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_CUT_MODE' +VGT_GS_CUT_MODE__enumvalues = { + 0: 'GS_CUT_1024', + 1: 'GS_CUT_512', + 2: 'GS_CUT_256', + 3: 'GS_CUT_128', +} +GS_CUT_1024 = 0 +GS_CUT_512 = 1 +GS_CUT_256 = 2 +GS_CUT_128 = 3 +VGT_GS_CUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_OUTPRIM_TYPE' +VGT_GS_OUTPRIM_TYPE__enumvalues = { + 0: 'POINTLIST', + 1: 'LINESTRIP', + 2: 'TRISTRIP', + 3: 'RECTLIST', +} +POINTLIST = 0 +LINESTRIP = 1 +TRISTRIP = 2 +RECTLIST = 3 +VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_CACHE_INVALID_MODE' +VGT_CACHE_INVALID_MODE__enumvalues = { + 0: 'VC_ONLY', + 1: 'TC_ONLY', + 2: 'VC_AND_TC', +} +VC_ONLY = 0 +TC_ONLY = 1 +VC_AND_TC = 2 +VGT_CACHE_INVALID_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TYPE' +VGT_TESS_TYPE__enumvalues = { + 0: 'TESS_ISOLINE', + 1: 'TESS_TRIANGLE', + 2: 'TESS_QUAD', +} +TESS_ISOLINE = 0 +TESS_TRIANGLE = 1 +TESS_QUAD = 2 +VGT_TESS_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_PARTITION' +VGT_TESS_PARTITION__enumvalues = { + 0: 'PART_INTEGER', + 1: 'PART_POW2', + 2: 'PART_FRAC_ODD', + 3: 'PART_FRAC_EVEN', +} +PART_INTEGER = 0 +PART_POW2 = 1 +PART_FRAC_ODD = 2 +PART_FRAC_EVEN = 3 +VGT_TESS_PARTITION = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TOPOLOGY' +VGT_TESS_TOPOLOGY__enumvalues = { + 0: 'OUTPUT_POINT', + 1: 'OUTPUT_LINE', + 2: 'OUTPUT_TRIANGLE_CW', + 3: 'OUTPUT_TRIANGLE_CCW', +} +OUTPUT_POINT = 0 +OUTPUT_LINE = 1 +OUTPUT_TRIANGLE_CW = 2 +OUTPUT_TRIANGLE_CCW = 3 +VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_RDREQ_POLICY' +VGT_RDREQ_POLICY__enumvalues = { + 0: 'VGT_POLICY_LRU', + 1: 'VGT_POLICY_STREAM', +} +VGT_POLICY_LRU = 0 +VGT_POLICY_STREAM = 1 +VGT_RDREQ_POLICY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DIST_MODE' +VGT_DIST_MODE__enumvalues = { + 0: 'NO_DIST', + 1: 'PATCHES', + 2: 'DONUTS', + 3: 'TRAPEZOIDS', +} +NO_DIST = 0 +PATCHES = 1 +DONUTS = 2 +TRAPEZOIDS = 3 +VGT_DIST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_LS_EN' +VGT_STAGES_LS_EN__enumvalues = { + 0: 'LS_STAGE_OFF', + 1: 'LS_STAGE_ON', + 2: 'CS_STAGE_ON', + 3: 'RESERVED_LS', +} +LS_STAGE_OFF = 0 +LS_STAGE_ON = 1 +CS_STAGE_ON = 2 +RESERVED_LS = 3 +VGT_STAGES_LS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_HS_EN' +VGT_STAGES_HS_EN__enumvalues = { + 0: 'HS_STAGE_OFF', + 1: 'HS_STAGE_ON', +} +HS_STAGE_OFF = 0 +HS_STAGE_ON = 1 +VGT_STAGES_HS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_ES_EN' +VGT_STAGES_ES_EN__enumvalues = { + 0: 'ES_STAGE_OFF', + 1: 'ES_STAGE_DS', + 2: 'ES_STAGE_REAL', + 3: 'RESERVED_ES', +} +ES_STAGE_OFF = 0 +ES_STAGE_DS = 1 +ES_STAGE_REAL = 2 +RESERVED_ES = 3 +VGT_STAGES_ES_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_GS_EN' +VGT_STAGES_GS_EN__enumvalues = { + 0: 'GS_STAGE_OFF', + 1: 'GS_STAGE_ON', +} +GS_STAGE_OFF = 0 +GS_STAGE_ON = 1 +VGT_STAGES_GS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_VS_EN' +VGT_STAGES_VS_EN__enumvalues = { + 0: 'VS_STAGE_REAL', + 1: 'VS_STAGE_DS', + 2: 'VS_STAGE_COPY_SHADER', + 3: 'RESERVED_VS', +} +VS_STAGE_REAL = 0 +VS_STAGE_DS = 1 +VS_STAGE_COPY_SHADER = 2 +RESERVED_VS = 3 +VGT_STAGES_VS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_PERFCOUNT_SELECT' +VGT_PERFCOUNT_SELECT__enumvalues = { + 0: 'vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE', + 1: 'vgt_perf_VGT_SPI_ESVERT_VALID', + 2: 'vgt_perf_VGT_SPI_ESVERT_EOV', + 3: 'vgt_perf_VGT_SPI_ESVERT_STALLED', + 4: 'vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY', + 5: 'vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE', + 6: 'vgt_perf_VGT_SPI_ESVERT_STATIC', + 7: 'vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT', + 8: 'vgt_perf_VGT_SPI_ESTHREAD_SEND', + 9: 'vgt_perf_VGT_SPI_GSPRIM_VALID', + 10: 'vgt_perf_VGT_SPI_GSPRIM_EOV', + 11: 'vgt_perf_VGT_SPI_GSPRIM_CONT', + 12: 'vgt_perf_VGT_SPI_GSPRIM_STALLED', + 13: 'vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY', + 14: 'vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE', + 15: 'vgt_perf_VGT_SPI_GSPRIM_STATIC', + 16: 'vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE', + 17: 'vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT', + 18: 'vgt_perf_VGT_SPI_GSTHREAD_SEND', + 19: 'vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE', + 20: 'vgt_perf_VGT_SPI_VSVERT_SEND', + 21: 'vgt_perf_VGT_SPI_VSVERT_EOV', + 22: 'vgt_perf_VGT_SPI_VSVERT_STALLED', + 23: 'vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY', + 24: 'vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE', + 25: 'vgt_perf_VGT_SPI_VSVERT_STATIC', + 26: 'vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT', + 27: 'vgt_perf_VGT_SPI_VSTHREAD_SEND', + 28: 'vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE', + 29: 'vgt_perf_VGT_PA_CLIPV_SEND', + 30: 'vgt_perf_VGT_PA_CLIPV_FIRSTVERT', + 31: 'vgt_perf_VGT_PA_CLIPV_STALLED', + 32: 'vgt_perf_VGT_PA_CLIPV_STARVED_BUSY', + 33: 'vgt_perf_VGT_PA_CLIPV_STARVED_IDLE', + 34: 'vgt_perf_VGT_PA_CLIPV_STATIC', + 35: 'vgt_perf_VGT_PA_CLIPP_SEND', + 36: 'vgt_perf_VGT_PA_CLIPP_EOP', + 37: 'vgt_perf_VGT_PA_CLIPP_IS_EVENT', + 38: 'vgt_perf_VGT_PA_CLIPP_NULL_PRIM', + 39: 'vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT', + 40: 'vgt_perf_VGT_PA_CLIPP_STALLED', + 41: 'vgt_perf_VGT_PA_CLIPP_STARVED_BUSY', + 42: 'vgt_perf_VGT_PA_CLIPP_STARVED_IDLE', + 43: 'vgt_perf_VGT_PA_CLIPP_STATIC', + 44: 'vgt_perf_VGT_PA_CLIPS_SEND', + 45: 'vgt_perf_VGT_PA_CLIPS_STALLED', + 46: 'vgt_perf_VGT_PA_CLIPS_STARVED_BUSY', + 47: 'vgt_perf_VGT_PA_CLIPS_STARVED_IDLE', + 48: 'vgt_perf_VGT_PA_CLIPS_STATIC', + 49: 'vgt_perf_vsvert_ds_send', + 50: 'vgt_perf_vsvert_api_send', + 51: 'vgt_perf_hs_tif_stall', + 52: 'vgt_perf_hs_input_stall', + 53: 'vgt_perf_hs_interface_stall', + 54: 'vgt_perf_hs_tfm_stall', + 55: 'vgt_perf_te11_starved', + 56: 'vgt_perf_gs_event_stall', + 57: 'vgt_perf_vgt_pa_clipp_send_not_event', + 58: 'vgt_perf_vgt_pa_clipp_valid_prim', + 59: 'vgt_perf_reused_es_indices', + 60: 'vgt_perf_vs_cache_hits', + 61: 'vgt_perf_gs_cache_hits', + 62: 'vgt_perf_ds_cache_hits', + 63: 'vgt_perf_total_cache_hits', + 64: 'vgt_perf_vgt_busy', + 65: 'vgt_perf_vgt_gs_busy', + 66: 'vgt_perf_esvert_stalled_es_tbl', + 67: 'vgt_perf_esvert_stalled_gs_tbl', + 68: 'vgt_perf_esvert_stalled_gs_event', + 69: 'vgt_perf_esvert_stalled_gsprim', + 70: 'vgt_perf_gsprim_stalled_es_tbl', + 71: 'vgt_perf_gsprim_stalled_gs_tbl', + 72: 'vgt_perf_gsprim_stalled_gs_event', + 73: 'vgt_perf_gsprim_stalled_esvert', + 74: 'vgt_perf_esthread_stalled_es_rb_full', + 75: 'vgt_perf_esthread_stalled_spi_bp', + 76: 'vgt_perf_counters_avail_stalled', + 77: 'vgt_perf_gs_rb_space_avail_stalled', + 78: 'vgt_perf_gs_issue_rtr_stalled', + 79: 'vgt_perf_gsthread_stalled', + 80: 'vgt_perf_strmout_stalled', + 81: 'vgt_perf_wait_for_es_done_stalled', + 82: 'vgt_perf_cm_stalled_by_gog', + 83: 'vgt_perf_cm_reading_stalled', + 84: 'vgt_perf_cm_stalled_by_gsfetch_done', + 85: 'vgt_perf_gog_vs_tbl_stalled', + 86: 'vgt_perf_gog_out_indx_stalled', + 87: 'vgt_perf_gog_out_prim_stalled', + 88: 'vgt_perf_waveid_stalled', + 89: 'vgt_perf_gog_busy', + 90: 'vgt_perf_reused_vs_indices', + 91: 'vgt_perf_sclk_reg_vld_event', + 92: 'vgt_perf_vs_conflicting_indices', + 93: 'vgt_perf_sclk_core_vld_event', + 94: 'vgt_perf_hswave_stalled', + 95: 'vgt_perf_sclk_gs_vld_event', + 96: 'vgt_perf_VGT_SPI_LSVERT_VALID', + 97: 'vgt_perf_VGT_SPI_LSVERT_EOV', + 98: 'vgt_perf_VGT_SPI_LSVERT_STALLED', + 99: 'vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY', + 100: 'vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE', + 101: 'vgt_perf_VGT_SPI_LSVERT_STATIC', + 102: 'vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE', + 103: 'vgt_perf_VGT_SPI_LSWAVE_IS_EVENT', + 104: 'vgt_perf_VGT_SPI_LSWAVE_SEND', + 105: 'vgt_perf_VGT_SPI_HSVERT_VALID', + 106: 'vgt_perf_VGT_SPI_HSVERT_EOV', + 107: 'vgt_perf_VGT_SPI_HSVERT_STALLED', + 108: 'vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY', + 109: 'vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE', + 110: 'vgt_perf_VGT_SPI_HSVERT_STATIC', + 111: 'vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE', + 112: 'vgt_perf_VGT_SPI_HSWAVE_IS_EVENT', + 113: 'vgt_perf_VGT_SPI_HSWAVE_SEND', + 114: 'vgt_perf_ds_prims', + 115: 'vgt_perf_ds_RESERVED', + 116: 'vgt_perf_ls_thread_groups', + 117: 'vgt_perf_hs_thread_groups', + 118: 'vgt_perf_es_thread_groups', + 119: 'vgt_perf_vs_thread_groups', + 120: 'vgt_perf_ls_done_latency', + 121: 'vgt_perf_hs_done_latency', + 122: 'vgt_perf_es_done_latency', + 123: 'vgt_perf_gs_done_latency', + 124: 'vgt_perf_vgt_hs_busy', + 125: 'vgt_perf_vgt_te11_busy', + 126: 'vgt_perf_ls_flush', + 127: 'vgt_perf_hs_flush', + 128: 'vgt_perf_es_flush', + 129: 'vgt_perf_vgt_pa_clipp_eopg', + 130: 'vgt_perf_ls_done', + 131: 'vgt_perf_hs_done', + 132: 'vgt_perf_es_done', + 133: 'vgt_perf_gs_done', + 134: 'vgt_perf_vsfetch_done', + 135: 'vgt_perf_gs_done_received', + 136: 'vgt_perf_es_ring_high_water_mark', + 137: 'vgt_perf_gs_ring_high_water_mark', + 138: 'vgt_perf_vs_table_high_water_mark', + 139: 'vgt_perf_hs_tgs_active_high_water_mark', + 140: 'vgt_perf_pa_clipp_dealloc', + 141: 'vgt_perf_cut_mem_flush_stalled', + 142: 'vgt_perf_vsvert_work_received', + 143: 'vgt_perf_vgt_pa_clipp_starved_after_work', + 144: 'vgt_perf_te11_con_starved_after_work', + 145: 'vgt_perf_hs_waiting_on_ls_done_stall', + 146: 'vgt_spi_vsvert_valid', +} +vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0 +vgt_perf_VGT_SPI_ESVERT_VALID = 1 +vgt_perf_VGT_SPI_ESVERT_EOV = 2 +vgt_perf_VGT_SPI_ESVERT_STALLED = 3 +vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 4 +vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 5 +vgt_perf_VGT_SPI_ESVERT_STATIC = 6 +vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 7 +vgt_perf_VGT_SPI_ESTHREAD_SEND = 8 +vgt_perf_VGT_SPI_GSPRIM_VALID = 9 +vgt_perf_VGT_SPI_GSPRIM_EOV = 10 +vgt_perf_VGT_SPI_GSPRIM_CONT = 11 +vgt_perf_VGT_SPI_GSPRIM_STALLED = 12 +vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 13 +vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 14 +vgt_perf_VGT_SPI_GSPRIM_STATIC = 15 +vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 16 +vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 17 +vgt_perf_VGT_SPI_GSTHREAD_SEND = 18 +vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 19 +vgt_perf_VGT_SPI_VSVERT_SEND = 20 +vgt_perf_VGT_SPI_VSVERT_EOV = 21 +vgt_perf_VGT_SPI_VSVERT_STALLED = 22 +vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 23 +vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 24 +vgt_perf_VGT_SPI_VSVERT_STATIC = 25 +vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 26 +vgt_perf_VGT_SPI_VSTHREAD_SEND = 27 +vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 28 +vgt_perf_VGT_PA_CLIPV_SEND = 29 +vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 30 +vgt_perf_VGT_PA_CLIPV_STALLED = 31 +vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 32 +vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 33 +vgt_perf_VGT_PA_CLIPV_STATIC = 34 +vgt_perf_VGT_PA_CLIPP_SEND = 35 +vgt_perf_VGT_PA_CLIPP_EOP = 36 +vgt_perf_VGT_PA_CLIPP_IS_EVENT = 37 +vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 38 +vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 39 +vgt_perf_VGT_PA_CLIPP_STALLED = 40 +vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 41 +vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 42 +vgt_perf_VGT_PA_CLIPP_STATIC = 43 +vgt_perf_VGT_PA_CLIPS_SEND = 44 +vgt_perf_VGT_PA_CLIPS_STALLED = 45 +vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 46 +vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 47 +vgt_perf_VGT_PA_CLIPS_STATIC = 48 +vgt_perf_vsvert_ds_send = 49 +vgt_perf_vsvert_api_send = 50 +vgt_perf_hs_tif_stall = 51 +vgt_perf_hs_input_stall = 52 +vgt_perf_hs_interface_stall = 53 +vgt_perf_hs_tfm_stall = 54 +vgt_perf_te11_starved = 55 +vgt_perf_gs_event_stall = 56 +vgt_perf_vgt_pa_clipp_send_not_event = 57 +vgt_perf_vgt_pa_clipp_valid_prim = 58 +vgt_perf_reused_es_indices = 59 +vgt_perf_vs_cache_hits = 60 +vgt_perf_gs_cache_hits = 61 +vgt_perf_ds_cache_hits = 62 +vgt_perf_total_cache_hits = 63 +vgt_perf_vgt_busy = 64 +vgt_perf_vgt_gs_busy = 65 +vgt_perf_esvert_stalled_es_tbl = 66 +vgt_perf_esvert_stalled_gs_tbl = 67 +vgt_perf_esvert_stalled_gs_event = 68 +vgt_perf_esvert_stalled_gsprim = 69 +vgt_perf_gsprim_stalled_es_tbl = 70 +vgt_perf_gsprim_stalled_gs_tbl = 71 +vgt_perf_gsprim_stalled_gs_event = 72 +vgt_perf_gsprim_stalled_esvert = 73 +vgt_perf_esthread_stalled_es_rb_full = 74 +vgt_perf_esthread_stalled_spi_bp = 75 +vgt_perf_counters_avail_stalled = 76 +vgt_perf_gs_rb_space_avail_stalled = 77 +vgt_perf_gs_issue_rtr_stalled = 78 +vgt_perf_gsthread_stalled = 79 +vgt_perf_strmout_stalled = 80 +vgt_perf_wait_for_es_done_stalled = 81 +vgt_perf_cm_stalled_by_gog = 82 +vgt_perf_cm_reading_stalled = 83 +vgt_perf_cm_stalled_by_gsfetch_done = 84 +vgt_perf_gog_vs_tbl_stalled = 85 +vgt_perf_gog_out_indx_stalled = 86 +vgt_perf_gog_out_prim_stalled = 87 +vgt_perf_waveid_stalled = 88 +vgt_perf_gog_busy = 89 +vgt_perf_reused_vs_indices = 90 +vgt_perf_sclk_reg_vld_event = 91 +vgt_perf_vs_conflicting_indices = 92 +vgt_perf_sclk_core_vld_event = 93 +vgt_perf_hswave_stalled = 94 +vgt_perf_sclk_gs_vld_event = 95 +vgt_perf_VGT_SPI_LSVERT_VALID = 96 +vgt_perf_VGT_SPI_LSVERT_EOV = 97 +vgt_perf_VGT_SPI_LSVERT_STALLED = 98 +vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 99 +vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 100 +vgt_perf_VGT_SPI_LSVERT_STATIC = 101 +vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 102 +vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 103 +vgt_perf_VGT_SPI_LSWAVE_SEND = 104 +vgt_perf_VGT_SPI_HSVERT_VALID = 105 +vgt_perf_VGT_SPI_HSVERT_EOV = 106 +vgt_perf_VGT_SPI_HSVERT_STALLED = 107 +vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 108 +vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 109 +vgt_perf_VGT_SPI_HSVERT_STATIC = 110 +vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 111 +vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 112 +vgt_perf_VGT_SPI_HSWAVE_SEND = 113 +vgt_perf_ds_prims = 114 +vgt_perf_ds_RESERVED = 115 +vgt_perf_ls_thread_groups = 116 +vgt_perf_hs_thread_groups = 117 +vgt_perf_es_thread_groups = 118 +vgt_perf_vs_thread_groups = 119 +vgt_perf_ls_done_latency = 120 +vgt_perf_hs_done_latency = 121 +vgt_perf_es_done_latency = 122 +vgt_perf_gs_done_latency = 123 +vgt_perf_vgt_hs_busy = 124 +vgt_perf_vgt_te11_busy = 125 +vgt_perf_ls_flush = 126 +vgt_perf_hs_flush = 127 +vgt_perf_es_flush = 128 +vgt_perf_vgt_pa_clipp_eopg = 129 +vgt_perf_ls_done = 130 +vgt_perf_hs_done = 131 +vgt_perf_es_done = 132 +vgt_perf_gs_done = 133 +vgt_perf_vsfetch_done = 134 +vgt_perf_gs_done_received = 135 +vgt_perf_es_ring_high_water_mark = 136 +vgt_perf_gs_ring_high_water_mark = 137 +vgt_perf_vs_table_high_water_mark = 138 +vgt_perf_hs_tgs_active_high_water_mark = 139 +vgt_perf_pa_clipp_dealloc = 140 +vgt_perf_cut_mem_flush_stalled = 141 +vgt_perf_vsvert_work_received = 142 +vgt_perf_vgt_pa_clipp_starved_after_work = 143 +vgt_perf_te11_con_starved_after_work = 144 +vgt_perf_hs_waiting_on_ls_done_stall = 145 +vgt_spi_vsvert_valid = 146 +VGT_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'IA_PERFCOUNT_SELECT' +IA_PERFCOUNT_SELECT__enumvalues = { + 0: 'ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE', + 1: 'ia_perf_dma_data_fifo_full', + 2: 'ia_perf_RESERVED1', + 3: 'ia_perf_RESERVED2', + 4: 'ia_perf_RESERVED3', + 5: 'ia_perf_RESERVED4', + 6: 'ia_perf_RESERVED5', + 7: 'ia_perf_MC_LAT_BIN_0', + 8: 'ia_perf_MC_LAT_BIN_1', + 9: 'ia_perf_MC_LAT_BIN_2', + 10: 'ia_perf_MC_LAT_BIN_3', + 11: 'ia_perf_MC_LAT_BIN_4', + 12: 'ia_perf_MC_LAT_BIN_5', + 13: 'ia_perf_MC_LAT_BIN_6', + 14: 'ia_perf_MC_LAT_BIN_7', + 15: 'ia_perf_ia_busy', + 16: 'ia_perf_ia_sclk_reg_vld_event', + 17: 'ia_perf_RESERVED6', + 18: 'ia_perf_ia_sclk_core_vld_event', + 19: 'ia_perf_RESERVED7', + 20: 'ia_perf_ia_dma_return', + 21: 'ia_perf_ia_stalled', + 22: 'ia_perf_shift_starved_pipe0_event', + 23: 'ia_perf_shift_starved_pipe1_event', +} +ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0 +ia_perf_dma_data_fifo_full = 1 +ia_perf_RESERVED1 = 2 +ia_perf_RESERVED2 = 3 +ia_perf_RESERVED3 = 4 +ia_perf_RESERVED4 = 5 +ia_perf_RESERVED5 = 6 +ia_perf_MC_LAT_BIN_0 = 7 +ia_perf_MC_LAT_BIN_1 = 8 +ia_perf_MC_LAT_BIN_2 = 9 +ia_perf_MC_LAT_BIN_3 = 10 +ia_perf_MC_LAT_BIN_4 = 11 +ia_perf_MC_LAT_BIN_5 = 12 +ia_perf_MC_LAT_BIN_6 = 13 +ia_perf_MC_LAT_BIN_7 = 14 +ia_perf_ia_busy = 15 +ia_perf_ia_sclk_reg_vld_event = 16 +ia_perf_RESERVED6 = 17 +ia_perf_ia_sclk_core_vld_event = 18 +ia_perf_RESERVED7 = 19 +ia_perf_ia_dma_return = 20 +ia_perf_ia_stalled = 21 +ia_perf_shift_starved_pipe0_event = 22 +ia_perf_shift_starved_pipe1_event = 23 +IA_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'WD_PERFCOUNT_SELECT' +WD_PERFCOUNT_SELECT__enumvalues = { + 0: 'wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE', + 1: 'wd_perf_RBIU_DR_FIFO_STARVED', + 2: 'wd_perf_RBIU_DR_FIFO_STALLED', + 3: 'wd_perf_RBIU_DI_FIFO_STARVED', + 4: 'wd_perf_RBIU_DI_FIFO_STALLED', + 5: 'wd_perf_wd_busy', + 6: 'wd_perf_wd_sclk_reg_vld_event', + 7: 'wd_perf_wd_sclk_input_vld_event', + 8: 'wd_perf_wd_sclk_core_vld_event', + 9: 'wd_perf_wd_stalled', + 10: 'wd_perf_inside_tf_bin_0', + 11: 'wd_perf_inside_tf_bin_1', + 12: 'wd_perf_inside_tf_bin_2', + 13: 'wd_perf_inside_tf_bin_3', + 14: 'wd_perf_inside_tf_bin_4', + 15: 'wd_perf_inside_tf_bin_5', + 16: 'wd_perf_inside_tf_bin_6', + 17: 'wd_perf_inside_tf_bin_7', + 18: 'wd_perf_inside_tf_bin_8', + 19: 'wd_perf_tfreq_lat_bin_0', + 20: 'wd_perf_tfreq_lat_bin_1', + 21: 'wd_perf_tfreq_lat_bin_2', + 22: 'wd_perf_tfreq_lat_bin_3', + 23: 'wd_perf_tfreq_lat_bin_4', + 24: 'wd_perf_tfreq_lat_bin_5', + 25: 'wd_perf_tfreq_lat_bin_6', + 26: 'wd_perf_tfreq_lat_bin_7', + 27: 'wd_starved_on_hs_done', + 28: 'wd_perf_se0_hs_done_latency', + 29: 'wd_perf_se1_hs_done_latency', + 30: 'wd_perf_se2_hs_done_latency', + 31: 'wd_perf_se3_hs_done_latency', + 32: 'wd_perf_hs_done_se0', + 33: 'wd_perf_hs_done_se1', + 34: 'wd_perf_hs_done_se2', + 35: 'wd_perf_hs_done_se3', + 36: 'wd_perf_null_patches', +} +wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0 +wd_perf_RBIU_DR_FIFO_STARVED = 1 +wd_perf_RBIU_DR_FIFO_STALLED = 2 +wd_perf_RBIU_DI_FIFO_STARVED = 3 +wd_perf_RBIU_DI_FIFO_STALLED = 4 +wd_perf_wd_busy = 5 +wd_perf_wd_sclk_reg_vld_event = 6 +wd_perf_wd_sclk_input_vld_event = 7 +wd_perf_wd_sclk_core_vld_event = 8 +wd_perf_wd_stalled = 9 +wd_perf_inside_tf_bin_0 = 10 +wd_perf_inside_tf_bin_1 = 11 +wd_perf_inside_tf_bin_2 = 12 +wd_perf_inside_tf_bin_3 = 13 +wd_perf_inside_tf_bin_4 = 14 +wd_perf_inside_tf_bin_5 = 15 +wd_perf_inside_tf_bin_6 = 16 +wd_perf_inside_tf_bin_7 = 17 +wd_perf_inside_tf_bin_8 = 18 +wd_perf_tfreq_lat_bin_0 = 19 +wd_perf_tfreq_lat_bin_1 = 20 +wd_perf_tfreq_lat_bin_2 = 21 +wd_perf_tfreq_lat_bin_3 = 22 +wd_perf_tfreq_lat_bin_4 = 23 +wd_perf_tfreq_lat_bin_5 = 24 +wd_perf_tfreq_lat_bin_6 = 25 +wd_perf_tfreq_lat_bin_7 = 26 +wd_starved_on_hs_done = 27 +wd_perf_se0_hs_done_latency = 28 +wd_perf_se1_hs_done_latency = 29 +wd_perf_se2_hs_done_latency = 30 +wd_perf_se3_hs_done_latency = 31 +wd_perf_hs_done_se0 = 32 +wd_perf_hs_done_se1 = 33 +wd_perf_hs_done_se2 = 34 +wd_perf_hs_done_se3 = 35 +wd_perf_null_patches = 36 +WD_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_TYPE' +WD_IA_DRAW_TYPE__enumvalues = { + 0: 'WD_IA_DRAW_TYPE_DI_MM0', + 1: 'WD_IA_DRAW_TYPE_REG_XFER', + 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', + 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 4: 'WD_IA_DRAW_TYPE_MIN_INDX', + 5: 'WD_IA_DRAW_TYPE_MAX_INDX', + 6: 'WD_IA_DRAW_TYPE_INDX_OFF', + 7: 'WD_IA_DRAW_TYPE_IMM_DATA', +} +WD_IA_DRAW_TYPE_DI_MM0 = 0 +WD_IA_DRAW_TYPE_REG_XFER = 1 +WD_IA_DRAW_TYPE_EVENT_INIT = 2 +WD_IA_DRAW_TYPE_EVENT_ADDR = 3 +WD_IA_DRAW_TYPE_MIN_INDX = 4 +WD_IA_DRAW_TYPE_MAX_INDX = 5 +WD_IA_DRAW_TYPE_INDX_OFF = 6 +WD_IA_DRAW_TYPE_IMM_DATA = 7 +WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_REG_XFER' +WD_IA_DRAW_REG_XFER__enumvalues = { + 0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', + 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', +} +WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0 +WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 +WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_SOURCE' +WD_IA_DRAW_SOURCE__enumvalues = { + 0: 'WD_IA_DRAW_SOURCE_DMA', + 1: 'WD_IA_DRAW_SOURCE_IMMD', + 2: 'WD_IA_DRAW_SOURCE_AUTO', + 3: 'WD_IA_DRAW_SOURCE_OPAQ', +} +WD_IA_DRAW_SOURCE_DMA = 0 +WD_IA_DRAW_SOURCE_IMMD = 1 +WD_IA_DRAW_SOURCE_AUTO = 2 +WD_IA_DRAW_SOURCE_OPAQ = 3 +WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'GB_EDC_DED_MODE' +GB_EDC_DED_MODE__enumvalues = { + 0: 'GB_EDC_DED_MODE_LOG', + 1: 'GB_EDC_DED_MODE_HALT', + 2: 'GB_EDC_DED_MODE_INT_HALT', +} +GB_EDC_DED_MODE_LOG = 0 +GB_EDC_DED_MODE_HALT = 1 +GB_EDC_DED_MODE_INT_HALT = 2 +GB_EDC_DED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'TA_TC_ADDR_MODES' +TA_TC_ADDR_MODES__enumvalues = { + 0: 'TA_TC_ADDR_MODE_DEFAULT', + 1: 'TA_TC_ADDR_MODE_COMP0', + 2: 'TA_TC_ADDR_MODE_COMP1', + 3: 'TA_TC_ADDR_MODE_COMP2', + 4: 'TA_TC_ADDR_MODE_COMP3', + 5: 'TA_TC_ADDR_MODE_UNALIGNED', + 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', +} +TA_TC_ADDR_MODE_DEFAULT = 0 +TA_TC_ADDR_MODE_COMP0 = 1 +TA_TC_ADDR_MODE_COMP1 = 2 +TA_TC_ADDR_MODE_COMP2 = 3 +TA_TC_ADDR_MODE_COMP3 = 4 +TA_TC_ADDR_MODE_UNALIGNED = 5 +TA_TC_ADDR_MODE_BORDER_COLOR = 6 +TA_TC_ADDR_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TA_PERFCOUNT_SEL' +TA_PERFCOUNT_SEL__enumvalues = { + 0: 'TA_PERF_SEL_NULL', + 1: 'TA_PERF_SEL_sh_fifo_busy', + 2: 'TA_PERF_SEL_sh_fifo_cmd_busy', + 3: 'TA_PERF_SEL_sh_fifo_addr_busy', + 4: 'TA_PERF_SEL_sh_fifo_data_busy', + 5: 'TA_PERF_SEL_sh_fifo_data_sfifo_busy', + 6: 'TA_PERF_SEL_sh_fifo_data_tfifo_busy', + 7: 'TA_PERF_SEL_gradient_busy', + 8: 'TA_PERF_SEL_gradient_fifo_busy', + 9: 'TA_PERF_SEL_lod_busy', + 10: 'TA_PERF_SEL_lod_fifo_busy', + 11: 'TA_PERF_SEL_addresser_busy', + 12: 'TA_PERF_SEL_addresser_fifo_busy', + 13: 'TA_PERF_SEL_aligner_busy', + 14: 'TA_PERF_SEL_write_path_busy', + 15: 'TA_PERF_SEL_ta_busy', + 16: 'TA_PERF_SEL_sq_ta_cmd_cycles', + 17: 'TA_PERF_SEL_sp_ta_addr_cycles', + 18: 'TA_PERF_SEL_sp_ta_data_cycles', + 19: 'TA_PERF_SEL_ta_fa_data_state_cycles', + 20: 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles', + 21: 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles', + 22: 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles', + 23: 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles', + 24: 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles', + 25: 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles', + 26: 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles', + 27: 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles', + 28: 'TA_PERF_SEL_RESERVED_28', + 29: 'TA_PERF_SEL_RESERVED_29', + 30: 'TA_PERF_SEL_sh_fifo_addr_cycles', + 31: 'TA_PERF_SEL_sh_fifo_data_cycles', + 32: 'TA_PERF_SEL_total_wavefronts', + 33: 'TA_PERF_SEL_gradient_cycles', + 34: 'TA_PERF_SEL_walker_cycles', + 35: 'TA_PERF_SEL_aligner_cycles', + 36: 'TA_PERF_SEL_image_wavefronts', + 37: 'TA_PERF_SEL_image_read_wavefronts', + 38: 'TA_PERF_SEL_image_write_wavefronts', + 39: 'TA_PERF_SEL_image_atomic_wavefronts', + 40: 'TA_PERF_SEL_image_total_cycles', + 41: 'TA_PERF_SEL_RESERVED_41', + 42: 'TA_PERF_SEL_RESERVED_42', + 43: 'TA_PERF_SEL_RESERVED_43', + 44: 'TA_PERF_SEL_buffer_wavefronts', + 45: 'TA_PERF_SEL_buffer_read_wavefronts', + 46: 'TA_PERF_SEL_buffer_write_wavefronts', + 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', + 48: 'TA_PERF_SEL_buffer_coalescable_wavefronts', + 49: 'TA_PERF_SEL_buffer_total_cycles', + 50: 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles', + 51: 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles', + 52: 'TA_PERF_SEL_buffer_coalesced_read_cycles', + 53: 'TA_PERF_SEL_buffer_coalesced_write_cycles', + 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 56: 'TA_PERF_SEL_data_stalled_by_tc_cycles', + 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 58: 'TA_PERF_SEL_addresser_stalled_cycles', + 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 60: 'TA_PERF_SEL_aniso_stalled_cycles', + 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 62: 'TA_PERF_SEL_deriv_stalled_cycles', + 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 64: 'TA_PERF_SEL_color_1_cycle_pixels', + 65: 'TA_PERF_SEL_color_2_cycle_pixels', + 66: 'TA_PERF_SEL_color_3_cycle_pixels', + 67: 'TA_PERF_SEL_color_4_cycle_pixels', + 68: 'TA_PERF_SEL_mip_1_cycle_pixels', + 69: 'TA_PERF_SEL_mip_2_cycle_pixels', + 70: 'TA_PERF_SEL_vol_1_cycle_pixels', + 71: 'TA_PERF_SEL_vol_2_cycle_pixels', + 72: 'TA_PERF_SEL_bilin_point_1_cycle_pixels', + 73: 'TA_PERF_SEL_mipmap_lod_0_samples', + 74: 'TA_PERF_SEL_mipmap_lod_1_samples', + 75: 'TA_PERF_SEL_mipmap_lod_2_samples', + 76: 'TA_PERF_SEL_mipmap_lod_3_samples', + 77: 'TA_PERF_SEL_mipmap_lod_4_samples', + 78: 'TA_PERF_SEL_mipmap_lod_5_samples', + 79: 'TA_PERF_SEL_mipmap_lod_6_samples', + 80: 'TA_PERF_SEL_mipmap_lod_7_samples', + 81: 'TA_PERF_SEL_mipmap_lod_8_samples', + 82: 'TA_PERF_SEL_mipmap_lod_9_samples', + 83: 'TA_PERF_SEL_mipmap_lod_10_samples', + 84: 'TA_PERF_SEL_mipmap_lod_11_samples', + 85: 'TA_PERF_SEL_mipmap_lod_12_samples', + 86: 'TA_PERF_SEL_mipmap_lod_13_samples', + 87: 'TA_PERF_SEL_mipmap_lod_14_samples', + 88: 'TA_PERF_SEL_mipmap_invalid_samples', + 89: 'TA_PERF_SEL_aniso_1_cycle_quads', + 90: 'TA_PERF_SEL_aniso_2_cycle_quads', + 91: 'TA_PERF_SEL_aniso_4_cycle_quads', + 92: 'TA_PERF_SEL_aniso_6_cycle_quads', + 93: 'TA_PERF_SEL_aniso_8_cycle_quads', + 94: 'TA_PERF_SEL_aniso_10_cycle_quads', + 95: 'TA_PERF_SEL_aniso_12_cycle_quads', + 96: 'TA_PERF_SEL_aniso_14_cycle_quads', + 97: 'TA_PERF_SEL_aniso_16_cycle_quads', + 98: 'TA_PERF_SEL_write_path_input_cycles', + 99: 'TA_PERF_SEL_write_path_output_cycles', + 100: 'TA_PERF_SEL_flat_wavefronts', + 101: 'TA_PERF_SEL_flat_read_wavefronts', + 102: 'TA_PERF_SEL_flat_write_wavefronts', + 103: 'TA_PERF_SEL_flat_atomic_wavefronts', + 104: 'TA_PERF_SEL_flat_coalesceable_wavefronts', + 105: 'TA_PERF_SEL_reg_sclk_vld', + 106: 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en', + 107: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en', + 108: 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en', + 109: 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en', + 110: 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', + 111: 'TA_PERF_SEL_xnack_on_phase0', + 112: 'TA_PERF_SEL_xnack_on_phase1', + 113: 'TA_PERF_SEL_xnack_on_phase2', + 114: 'TA_PERF_SEL_xnack_on_phase3', + 115: 'TA_PERF_SEL_first_xnack_on_phase0', + 116: 'TA_PERF_SEL_first_xnack_on_phase1', + 117: 'TA_PERF_SEL_first_xnack_on_phase2', + 118: 'TA_PERF_SEL_first_xnack_on_phase3', +} +TA_PERF_SEL_NULL = 0 +TA_PERF_SEL_sh_fifo_busy = 1 +TA_PERF_SEL_sh_fifo_cmd_busy = 2 +TA_PERF_SEL_sh_fifo_addr_busy = 3 +TA_PERF_SEL_sh_fifo_data_busy = 4 +TA_PERF_SEL_sh_fifo_data_sfifo_busy = 5 +TA_PERF_SEL_sh_fifo_data_tfifo_busy = 6 +TA_PERF_SEL_gradient_busy = 7 +TA_PERF_SEL_gradient_fifo_busy = 8 +TA_PERF_SEL_lod_busy = 9 +TA_PERF_SEL_lod_fifo_busy = 10 +TA_PERF_SEL_addresser_busy = 11 +TA_PERF_SEL_addresser_fifo_busy = 12 +TA_PERF_SEL_aligner_busy = 13 +TA_PERF_SEL_write_path_busy = 14 +TA_PERF_SEL_ta_busy = 15 +TA_PERF_SEL_sq_ta_cmd_cycles = 16 +TA_PERF_SEL_sp_ta_addr_cycles = 17 +TA_PERF_SEL_sp_ta_data_cycles = 18 +TA_PERF_SEL_ta_fa_data_state_cycles = 19 +TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 20 +TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 21 +TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 22 +TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 23 +TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 24 +TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 25 +TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 26 +TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 27 +TA_PERF_SEL_RESERVED_28 = 28 +TA_PERF_SEL_RESERVED_29 = 29 +TA_PERF_SEL_sh_fifo_addr_cycles = 30 +TA_PERF_SEL_sh_fifo_data_cycles = 31 +TA_PERF_SEL_total_wavefronts = 32 +TA_PERF_SEL_gradient_cycles = 33 +TA_PERF_SEL_walker_cycles = 34 +TA_PERF_SEL_aligner_cycles = 35 +TA_PERF_SEL_image_wavefronts = 36 +TA_PERF_SEL_image_read_wavefronts = 37 +TA_PERF_SEL_image_write_wavefronts = 38 +TA_PERF_SEL_image_atomic_wavefronts = 39 +TA_PERF_SEL_image_total_cycles = 40 +TA_PERF_SEL_RESERVED_41 = 41 +TA_PERF_SEL_RESERVED_42 = 42 +TA_PERF_SEL_RESERVED_43 = 43 +TA_PERF_SEL_buffer_wavefronts = 44 +TA_PERF_SEL_buffer_read_wavefronts = 45 +TA_PERF_SEL_buffer_write_wavefronts = 46 +TA_PERF_SEL_buffer_atomic_wavefronts = 47 +TA_PERF_SEL_buffer_coalescable_wavefronts = 48 +TA_PERF_SEL_buffer_total_cycles = 49 +TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 50 +TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 51 +TA_PERF_SEL_buffer_coalesced_read_cycles = 52 +TA_PERF_SEL_buffer_coalesced_write_cycles = 53 +TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 +TA_PERF_SEL_addr_stalled_by_td_cycles = 55 +TA_PERF_SEL_data_stalled_by_tc_cycles = 56 +TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 +TA_PERF_SEL_addresser_stalled_cycles = 58 +TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 +TA_PERF_SEL_aniso_stalled_cycles = 60 +TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 +TA_PERF_SEL_deriv_stalled_cycles = 62 +TA_PERF_SEL_aniso_gt1_cycle_quads = 63 +TA_PERF_SEL_color_1_cycle_pixels = 64 +TA_PERF_SEL_color_2_cycle_pixels = 65 +TA_PERF_SEL_color_3_cycle_pixels = 66 +TA_PERF_SEL_color_4_cycle_pixels = 67 +TA_PERF_SEL_mip_1_cycle_pixels = 68 +TA_PERF_SEL_mip_2_cycle_pixels = 69 +TA_PERF_SEL_vol_1_cycle_pixels = 70 +TA_PERF_SEL_vol_2_cycle_pixels = 71 +TA_PERF_SEL_bilin_point_1_cycle_pixels = 72 +TA_PERF_SEL_mipmap_lod_0_samples = 73 +TA_PERF_SEL_mipmap_lod_1_samples = 74 +TA_PERF_SEL_mipmap_lod_2_samples = 75 +TA_PERF_SEL_mipmap_lod_3_samples = 76 +TA_PERF_SEL_mipmap_lod_4_samples = 77 +TA_PERF_SEL_mipmap_lod_5_samples = 78 +TA_PERF_SEL_mipmap_lod_6_samples = 79 +TA_PERF_SEL_mipmap_lod_7_samples = 80 +TA_PERF_SEL_mipmap_lod_8_samples = 81 +TA_PERF_SEL_mipmap_lod_9_samples = 82 +TA_PERF_SEL_mipmap_lod_10_samples = 83 +TA_PERF_SEL_mipmap_lod_11_samples = 84 +TA_PERF_SEL_mipmap_lod_12_samples = 85 +TA_PERF_SEL_mipmap_lod_13_samples = 86 +TA_PERF_SEL_mipmap_lod_14_samples = 87 +TA_PERF_SEL_mipmap_invalid_samples = 88 +TA_PERF_SEL_aniso_1_cycle_quads = 89 +TA_PERF_SEL_aniso_2_cycle_quads = 90 +TA_PERF_SEL_aniso_4_cycle_quads = 91 +TA_PERF_SEL_aniso_6_cycle_quads = 92 +TA_PERF_SEL_aniso_8_cycle_quads = 93 +TA_PERF_SEL_aniso_10_cycle_quads = 94 +TA_PERF_SEL_aniso_12_cycle_quads = 95 +TA_PERF_SEL_aniso_14_cycle_quads = 96 +TA_PERF_SEL_aniso_16_cycle_quads = 97 +TA_PERF_SEL_write_path_input_cycles = 98 +TA_PERF_SEL_write_path_output_cycles = 99 +TA_PERF_SEL_flat_wavefronts = 100 +TA_PERF_SEL_flat_read_wavefronts = 101 +TA_PERF_SEL_flat_write_wavefronts = 102 +TA_PERF_SEL_flat_atomic_wavefronts = 103 +TA_PERF_SEL_flat_coalesceable_wavefronts = 104 +TA_PERF_SEL_reg_sclk_vld = 105 +TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 106 +TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 107 +TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 108 +TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 109 +TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 110 +TA_PERF_SEL_xnack_on_phase0 = 111 +TA_PERF_SEL_xnack_on_phase1 = 112 +TA_PERF_SEL_xnack_on_phase2 = 113 +TA_PERF_SEL_xnack_on_phase3 = 114 +TA_PERF_SEL_first_xnack_on_phase0 = 115 +TA_PERF_SEL_first_xnack_on_phase1 = 116 +TA_PERF_SEL_first_xnack_on_phase2 = 117 +TA_PERF_SEL_first_xnack_on_phase3 = 118 +TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TD_PERFCOUNT_SEL' +TD_PERFCOUNT_SEL__enumvalues = { + 0: 'TD_PERF_SEL_none', + 1: 'TD_PERF_SEL_td_busy', + 2: 'TD_PERF_SEL_input_busy', + 3: 'TD_PERF_SEL_output_busy', + 4: 'TD_PERF_SEL_lerp_busy', + 5: 'TD_PERF_SEL_reg_sclk_vld', + 6: 'TD_PERF_SEL_local_cg_dyn_sclk_grp0_en', + 7: 'TD_PERF_SEL_local_cg_dyn_sclk_grp1_en', + 8: 'TD_PERF_SEL_local_cg_dyn_sclk_grp4_en', + 9: 'TD_PERF_SEL_local_cg_dyn_sclk_grp5_en', + 10: 'TD_PERF_SEL_tc_td_fifo_full', + 11: 'TD_PERF_SEL_constant_state_full', + 12: 'TD_PERF_SEL_sample_state_full', + 13: 'TD_PERF_SEL_output_fifo_full', + 14: 'TD_PERF_SEL_RESERVED_14', + 15: 'TD_PERF_SEL_tc_stall', + 16: 'TD_PERF_SEL_pc_stall', + 17: 'TD_PERF_SEL_gds_stall', + 18: 'TD_PERF_SEL_RESERVED_18', + 19: 'TD_PERF_SEL_RESERVED_19', + 20: 'TD_PERF_SEL_gather4_wavefront', + 21: 'TD_PERF_SEL_gather4h_wavefront', + 22: 'TD_PERF_SEL_gather4h_packed_wavefront', + 23: 'TD_PERF_SEL_gather8h_packed_wavefront', + 24: 'TD_PERF_SEL_sample_c_wavefront', + 25: 'TD_PERF_SEL_load_wavefront', + 26: 'TD_PERF_SEL_atomic_wavefront', + 27: 'TD_PERF_SEL_store_wavefront', + 28: 'TD_PERF_SEL_ldfptr_wavefront', + 29: 'TD_PERF_SEL_d16_en_wavefront', + 30: 'TD_PERF_SEL_bypass_filter_wavefront', + 31: 'TD_PERF_SEL_min_max_filter_wavefront', + 32: 'TD_PERF_SEL_coalescable_wavefront', + 33: 'TD_PERF_SEL_coalesced_phase', + 34: 'TD_PERF_SEL_four_phase_wavefront', + 35: 'TD_PERF_SEL_eight_phase_wavefront', + 36: 'TD_PERF_SEL_sixteen_phase_wavefront', + 37: 'TD_PERF_SEL_four_phase_forward_wavefront', + 38: 'TD_PERF_SEL_write_ack_wavefront', + 39: 'TD_PERF_SEL_RESERVED_39', + 40: 'TD_PERF_SEL_user_defined_border', + 41: 'TD_PERF_SEL_white_border', + 42: 'TD_PERF_SEL_opaque_black_border', + 43: 'TD_PERF_SEL_RESERVED_43', + 44: 'TD_PERF_SEL_RESERVED_44', + 45: 'TD_PERF_SEL_nack', + 46: 'TD_PERF_SEL_td_sp_traffic', + 47: 'TD_PERF_SEL_consume_gds_traffic', + 48: 'TD_PERF_SEL_addresscmd_poison', + 49: 'TD_PERF_SEL_data_poison', + 50: 'TD_PERF_SEL_start_cycle_0', + 51: 'TD_PERF_SEL_start_cycle_1', + 52: 'TD_PERF_SEL_start_cycle_2', + 53: 'TD_PERF_SEL_start_cycle_3', + 54: 'TD_PERF_SEL_null_cycle_output', + 55: 'TD_PERF_SEL_d16_data_packed', + 56: 'TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt', +} +TD_PERF_SEL_none = 0 +TD_PERF_SEL_td_busy = 1 +TD_PERF_SEL_input_busy = 2 +TD_PERF_SEL_output_busy = 3 +TD_PERF_SEL_lerp_busy = 4 +TD_PERF_SEL_reg_sclk_vld = 5 +TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 6 +TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 7 +TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 8 +TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 9 +TD_PERF_SEL_tc_td_fifo_full = 10 +TD_PERF_SEL_constant_state_full = 11 +TD_PERF_SEL_sample_state_full = 12 +TD_PERF_SEL_output_fifo_full = 13 +TD_PERF_SEL_RESERVED_14 = 14 +TD_PERF_SEL_tc_stall = 15 +TD_PERF_SEL_pc_stall = 16 +TD_PERF_SEL_gds_stall = 17 +TD_PERF_SEL_RESERVED_18 = 18 +TD_PERF_SEL_RESERVED_19 = 19 +TD_PERF_SEL_gather4_wavefront = 20 +TD_PERF_SEL_gather4h_wavefront = 21 +TD_PERF_SEL_gather4h_packed_wavefront = 22 +TD_PERF_SEL_gather8h_packed_wavefront = 23 +TD_PERF_SEL_sample_c_wavefront = 24 +TD_PERF_SEL_load_wavefront = 25 +TD_PERF_SEL_atomic_wavefront = 26 +TD_PERF_SEL_store_wavefront = 27 +TD_PERF_SEL_ldfptr_wavefront = 28 +TD_PERF_SEL_d16_en_wavefront = 29 +TD_PERF_SEL_bypass_filter_wavefront = 30 +TD_PERF_SEL_min_max_filter_wavefront = 31 +TD_PERF_SEL_coalescable_wavefront = 32 +TD_PERF_SEL_coalesced_phase = 33 +TD_PERF_SEL_four_phase_wavefront = 34 +TD_PERF_SEL_eight_phase_wavefront = 35 +TD_PERF_SEL_sixteen_phase_wavefront = 36 +TD_PERF_SEL_four_phase_forward_wavefront = 37 +TD_PERF_SEL_write_ack_wavefront = 38 +TD_PERF_SEL_RESERVED_39 = 39 +TD_PERF_SEL_user_defined_border = 40 +TD_PERF_SEL_white_border = 41 +TD_PERF_SEL_opaque_black_border = 42 +TD_PERF_SEL_RESERVED_43 = 43 +TD_PERF_SEL_RESERVED_44 = 44 +TD_PERF_SEL_nack = 45 +TD_PERF_SEL_td_sp_traffic = 46 +TD_PERF_SEL_consume_gds_traffic = 47 +TD_PERF_SEL_addresscmd_poison = 48 +TD_PERF_SEL_data_poison = 49 +TD_PERF_SEL_start_cycle_0 = 50 +TD_PERF_SEL_start_cycle_1 = 51 +TD_PERF_SEL_start_cycle_2 = 52 +TD_PERF_SEL_start_cycle_3 = 53 +TD_PERF_SEL_null_cycle_output = 54 +TD_PERF_SEL_d16_data_packed = 55 +TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt = 56 +TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_PERFCOUNT_SELECT' +TCP_PERFCOUNT_SELECT__enumvalues = { + 0: 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES', + 1: 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES', + 2: 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES', + 3: 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES', + 4: 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', + 5: 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES', + 6: 'TCP_PERF_SEL_LOD_STALL_CYCLES', + 7: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES', + 8: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', + 9: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES', + 10: 'TCP_PERF_SEL_ALLOC_STALL_CYCLES', + 11: 'TCP_PERF_SEL_LFIFO_STALL_CYCLES', + 12: 'TCP_PERF_SEL_RFIFO_STALL_CYCLES', + 13: 'TCP_PERF_SEL_TCR_RDRET_STALL', + 14: 'TCP_PERF_SEL_WRITE_CONFLICT_STALL', + 15: 'TCP_PERF_SEL_HOLE_READ_STALL', + 16: 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES', + 17: 'TCP_PERF_SEL_PENDING_STALL_CYCLES', + 18: 'TCP_PERF_SEL_READFIFO_STALL_CYCLES', + 19: 'TCP_PERF_SEL_TCP_LATENCY', + 20: 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY', + 21: 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', + 22: 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY', + 23: 'TCP_PERF_SEL_TCC_READ_REQ', + 24: 'TCP_PERF_SEL_TCC_WRITE_REQ', + 25: 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ', + 26: 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ', + 27: 'TCP_PERF_SEL_TOTAL_LOCAL_READ', + 28: 'TCP_PERF_SEL_TOTAL_GLOBAL_READ', + 29: 'TCP_PERF_SEL_TOTAL_LOCAL_WRITE', + 30: 'TCP_PERF_SEL_TOTAL_GLOBAL_WRITE', + 31: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET', + 32: 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET', + 33: 'TCP_PERF_SEL_TOTAL_WBINVL1', + 34: 'TCP_PERF_SEL_IMG_READ_FMT_1', + 35: 'TCP_PERF_SEL_IMG_READ_FMT_8', + 36: 'TCP_PERF_SEL_IMG_READ_FMT_16', + 37: 'TCP_PERF_SEL_IMG_READ_FMT_32', + 38: 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_8', + 39: 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_16', + 40: 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_128', + 41: 'TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE', + 42: 'TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE', + 43: 'TCP_PERF_SEL_IMG_READ_FMT_96', + 44: 'TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE', + 45: 'TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE', + 46: 'TCP_PERF_SEL_IMG_READ_FMT_BC1', + 47: 'TCP_PERF_SEL_IMG_READ_FMT_BC2', + 48: 'TCP_PERF_SEL_IMG_READ_FMT_BC3', + 49: 'TCP_PERF_SEL_IMG_READ_FMT_BC4', + 50: 'TCP_PERF_SEL_IMG_READ_FMT_BC5', + 51: 'TCP_PERF_SEL_IMG_READ_FMT_BC6', + 52: 'TCP_PERF_SEL_IMG_READ_FMT_BC7', + 53: 'TCP_PERF_SEL_IMG_READ_FMT_I8', + 54: 'TCP_PERF_SEL_IMG_READ_FMT_I16', + 55: 'TCP_PERF_SEL_IMG_READ_FMT_I32', + 56: 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8', + 57: 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16', + 58: 'TCP_PERF_SEL_IMG_READ_FMT_D8', + 59: 'TCP_PERF_SEL_IMG_READ_FMT_D16', + 60: 'TCP_PERF_SEL_IMG_READ_FMT_D32', + 61: 'TCP_PERF_SEL_IMG_WRITE_FMT_8', + 62: 'TCP_PERF_SEL_IMG_WRITE_FMT_16', + 63: 'TCP_PERF_SEL_IMG_WRITE_FMT_32', + 64: 'TCP_PERF_SEL_IMG_WRITE_FMT_64', + 65: 'TCP_PERF_SEL_IMG_WRITE_FMT_128', + 66: 'TCP_PERF_SEL_IMG_WRITE_FMT_D8', + 67: 'TCP_PERF_SEL_IMG_WRITE_FMT_D16', + 68: 'TCP_PERF_SEL_IMG_WRITE_FMT_D32', + 69: 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32', + 70: 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32', + 71: 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64', + 72: 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64', + 73: 'TCP_PERF_SEL_BUF_READ_FMT_8', + 74: 'TCP_PERF_SEL_BUF_READ_FMT_16', + 75: 'TCP_PERF_SEL_BUF_READ_FMT_32', + 76: 'TCP_PERF_SEL_BUF_WRITE_FMT_8', + 77: 'TCP_PERF_SEL_BUF_WRITE_FMT_16', + 78: 'TCP_PERF_SEL_BUF_WRITE_FMT_32', + 79: 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32', + 80: 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32', + 81: 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64', + 82: 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64', + 83: 'TCP_PERF_SEL_ARR_LINEAR_GENERAL', + 84: 'TCP_PERF_SEL_ARR_LINEAR_ALIGNED', + 85: 'TCP_PERF_SEL_ARR_1D_THIN1', + 86: 'TCP_PERF_SEL_ARR_1D_THICK', + 87: 'TCP_PERF_SEL_ARR_2D_THIN1', + 88: 'TCP_PERF_SEL_ARR_2D_THICK', + 89: 'TCP_PERF_SEL_ARR_2D_XTHICK', + 90: 'TCP_PERF_SEL_ARR_3D_THIN1', + 91: 'TCP_PERF_SEL_ARR_3D_THICK', + 92: 'TCP_PERF_SEL_ARR_3D_XTHICK', + 93: 'TCP_PERF_SEL_DIM_1D', + 94: 'TCP_PERF_SEL_DIM_2D', + 95: 'TCP_PERF_SEL_DIM_3D', + 96: 'TCP_PERF_SEL_DIM_1D_ARRAY', + 97: 'TCP_PERF_SEL_DIM_2D_ARRAY', + 98: 'TCP_PERF_SEL_DIM_2D_MSAA', + 99: 'TCP_PERF_SEL_DIM_2D_ARRAY_MSAA', + 100: 'TCP_PERF_SEL_DIM_CUBE_ARRAY', + 101: 'TCP_PERF_SEL_CP_TCP_INVALIDATE', + 102: 'TCP_PERF_SEL_TA_TCP_STATE_READ', + 103: 'TCP_PERF_SEL_TAGRAM0_REQ', + 104: 'TCP_PERF_SEL_TAGRAM1_REQ', + 105: 'TCP_PERF_SEL_TAGRAM2_REQ', + 106: 'TCP_PERF_SEL_TAGRAM3_REQ', + 107: 'TCP_PERF_SEL_GATE_EN1', + 108: 'TCP_PERF_SEL_GATE_EN2', + 109: 'TCP_PERF_SEL_CORE_REG_SCLK_VLD', + 110: 'TCP_PERF_SEL_TCC_REQ', + 111: 'TCP_PERF_SEL_TCC_NON_READ_REQ', + 112: 'TCP_PERF_SEL_TCC_BYPASS_READ_REQ', + 113: 'TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ', + 114: 'TCP_PERF_SEL_TCC_VOLATILE_READ_REQ', + 115: 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ', + 116: 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ', + 117: 'TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ', + 118: 'TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ', + 119: 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ', + 120: 'TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ', + 121: 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ', + 122: 'TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ', + 123: 'TCP_PERF_SEL_TCC_ATOMIC_REQ', + 124: 'TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ', + 125: 'TCP_PERF_SEL_TCC_DATA_BUS_BUSY', + 126: 'TCP_PERF_SEL_TOTAL_ACCESSES', + 127: 'TCP_PERF_SEL_TOTAL_READ', + 128: 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ', + 129: 'TCP_PERF_SEL_TOTAL_HIT_EVICT_READ', + 130: 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ', + 131: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ', + 132: 'TCP_PERF_SEL_TOTAL_NON_READ', + 133: 'TCP_PERF_SEL_TOTAL_WRITE', + 134: 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE', + 135: 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE', + 136: 'TCP_PERF_SEL_TOTAL_WBINVL1_VOL', + 137: 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES', + 138: 'TCP_PERF_SEL_DISPLAY_MICROTILING', + 139: 'TCP_PERF_SEL_THIN_MICROTILING', + 140: 'TCP_PERF_SEL_DEPTH_MICROTILING', + 141: 'TCP_PERF_SEL_ARR_PRT_THIN1', + 142: 'TCP_PERF_SEL_ARR_PRT_2D_THIN1', + 143: 'TCP_PERF_SEL_ARR_PRT_3D_THIN1', + 144: 'TCP_PERF_SEL_ARR_PRT_THICK', + 145: 'TCP_PERF_SEL_ARR_PRT_2D_THICK', + 146: 'TCP_PERF_SEL_ARR_PRT_3D_THICK', + 147: 'TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL', + 148: 'TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL', + 149: 'TCP_PERF_SEL_UNALIGNED', + 150: 'TCP_PERF_SEL_ROTATED_MICROTILING', + 151: 'TCP_PERF_SEL_THICK_MICROTILING', + 152: 'TCP_PERF_SEL_ATC', + 153: 'TCP_PERF_SEL_POWER_STALL', + 154: 'TCP_PERF_SEL_RESERVED_154', + 155: 'TCP_PERF_SEL_TCC_LRU_REQ', + 156: 'TCP_PERF_SEL_TCC_STREAM_REQ', + 157: 'TCP_PERF_SEL_TCC_NC_READ_REQ', + 158: 'TCP_PERF_SEL_TCC_NC_WRITE_REQ', + 159: 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ', + 160: 'TCP_PERF_SEL_TCC_UC_READ_REQ', + 161: 'TCP_PERF_SEL_TCC_UC_WRITE_REQ', + 162: 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ', + 163: 'TCP_PERF_SEL_TCC_CC_READ_REQ', + 164: 'TCP_PERF_SEL_TCC_CC_WRITE_REQ', + 165: 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', + 166: 'TCP_PERF_SEL_TCC_DCC_REQ', + 167: 'TCP_PERF_SEL_TCC_PHYSICAL_REQ', + 168: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', + 169: 'TCP_PERF_SEL_VOLATILE', + 170: 'TCP_PERF_SEL_TC_TA_XNACK_STALL', + 171: 'TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL', + 172: 'TCP_PERF_SEL_SHOOTDOWN', + 173: 'TCP_PERF_SEL_UTCL1_TRANSLATION_MISS', + 174: 'TCP_PERF_SEL_UTCL1_PERMISSION_MISS', + 175: 'TCP_PERF_SEL_UTCL1_REQUEST', + 176: 'TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 177: 'TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 178: 'TCP_PERF_SEL_UTCL1_LFIFO_FULL', + 179: 'TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 180: 'TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 181: 'TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT', + 182: 'TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 183: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB', + 184: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA', + 185: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1', + 186: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_R', + 187: 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG', + 188: 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_32', + 189: 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_64', + 190: 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_64', + 191: 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_128', + 192: 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32', + 193: 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64', + 194: 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64', + 195: 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128', +} +TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0 +TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 1 +TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 2 +TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 3 +TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 4 +TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 5 +TCP_PERF_SEL_LOD_STALL_CYCLES = 6 +TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 7 +TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 8 +TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 9 +TCP_PERF_SEL_ALLOC_STALL_CYCLES = 10 +TCP_PERF_SEL_LFIFO_STALL_CYCLES = 11 +TCP_PERF_SEL_RFIFO_STALL_CYCLES = 12 +TCP_PERF_SEL_TCR_RDRET_STALL = 13 +TCP_PERF_SEL_WRITE_CONFLICT_STALL = 14 +TCP_PERF_SEL_HOLE_READ_STALL = 15 +TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 16 +TCP_PERF_SEL_PENDING_STALL_CYCLES = 17 +TCP_PERF_SEL_READFIFO_STALL_CYCLES = 18 +TCP_PERF_SEL_TCP_LATENCY = 19 +TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 20 +TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 21 +TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 22 +TCP_PERF_SEL_TCC_READ_REQ = 23 +TCP_PERF_SEL_TCC_WRITE_REQ = 24 +TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 25 +TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 26 +TCP_PERF_SEL_TOTAL_LOCAL_READ = 27 +TCP_PERF_SEL_TOTAL_GLOBAL_READ = 28 +TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 29 +TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 30 +TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 31 +TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 32 +TCP_PERF_SEL_TOTAL_WBINVL1 = 33 +TCP_PERF_SEL_IMG_READ_FMT_1 = 34 +TCP_PERF_SEL_IMG_READ_FMT_8 = 35 +TCP_PERF_SEL_IMG_READ_FMT_16 = 36 +TCP_PERF_SEL_IMG_READ_FMT_32 = 37 +TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 38 +TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 39 +TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 40 +TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 41 +TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 42 +TCP_PERF_SEL_IMG_READ_FMT_96 = 43 +TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 44 +TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 45 +TCP_PERF_SEL_IMG_READ_FMT_BC1 = 46 +TCP_PERF_SEL_IMG_READ_FMT_BC2 = 47 +TCP_PERF_SEL_IMG_READ_FMT_BC3 = 48 +TCP_PERF_SEL_IMG_READ_FMT_BC4 = 49 +TCP_PERF_SEL_IMG_READ_FMT_BC5 = 50 +TCP_PERF_SEL_IMG_READ_FMT_BC6 = 51 +TCP_PERF_SEL_IMG_READ_FMT_BC7 = 52 +TCP_PERF_SEL_IMG_READ_FMT_I8 = 53 +TCP_PERF_SEL_IMG_READ_FMT_I16 = 54 +TCP_PERF_SEL_IMG_READ_FMT_I32 = 55 +TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 56 +TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 57 +TCP_PERF_SEL_IMG_READ_FMT_D8 = 58 +TCP_PERF_SEL_IMG_READ_FMT_D16 = 59 +TCP_PERF_SEL_IMG_READ_FMT_D32 = 60 +TCP_PERF_SEL_IMG_WRITE_FMT_8 = 61 +TCP_PERF_SEL_IMG_WRITE_FMT_16 = 62 +TCP_PERF_SEL_IMG_WRITE_FMT_32 = 63 +TCP_PERF_SEL_IMG_WRITE_FMT_64 = 64 +TCP_PERF_SEL_IMG_WRITE_FMT_128 = 65 +TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 66 +TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 67 +TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 68 +TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 69 +TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 70 +TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 71 +TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 72 +TCP_PERF_SEL_BUF_READ_FMT_8 = 73 +TCP_PERF_SEL_BUF_READ_FMT_16 = 74 +TCP_PERF_SEL_BUF_READ_FMT_32 = 75 +TCP_PERF_SEL_BUF_WRITE_FMT_8 = 76 +TCP_PERF_SEL_BUF_WRITE_FMT_16 = 77 +TCP_PERF_SEL_BUF_WRITE_FMT_32 = 78 +TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 79 +TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 80 +TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 81 +TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 82 +TCP_PERF_SEL_ARR_LINEAR_GENERAL = 83 +TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 84 +TCP_PERF_SEL_ARR_1D_THIN1 = 85 +TCP_PERF_SEL_ARR_1D_THICK = 86 +TCP_PERF_SEL_ARR_2D_THIN1 = 87 +TCP_PERF_SEL_ARR_2D_THICK = 88 +TCP_PERF_SEL_ARR_2D_XTHICK = 89 +TCP_PERF_SEL_ARR_3D_THIN1 = 90 +TCP_PERF_SEL_ARR_3D_THICK = 91 +TCP_PERF_SEL_ARR_3D_XTHICK = 92 +TCP_PERF_SEL_DIM_1D = 93 +TCP_PERF_SEL_DIM_2D = 94 +TCP_PERF_SEL_DIM_3D = 95 +TCP_PERF_SEL_DIM_1D_ARRAY = 96 +TCP_PERF_SEL_DIM_2D_ARRAY = 97 +TCP_PERF_SEL_DIM_2D_MSAA = 98 +TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 99 +TCP_PERF_SEL_DIM_CUBE_ARRAY = 100 +TCP_PERF_SEL_CP_TCP_INVALIDATE = 101 +TCP_PERF_SEL_TA_TCP_STATE_READ = 102 +TCP_PERF_SEL_TAGRAM0_REQ = 103 +TCP_PERF_SEL_TAGRAM1_REQ = 104 +TCP_PERF_SEL_TAGRAM2_REQ = 105 +TCP_PERF_SEL_TAGRAM3_REQ = 106 +TCP_PERF_SEL_GATE_EN1 = 107 +TCP_PERF_SEL_GATE_EN2 = 108 +TCP_PERF_SEL_CORE_REG_SCLK_VLD = 109 +TCP_PERF_SEL_TCC_REQ = 110 +TCP_PERF_SEL_TCC_NON_READ_REQ = 111 +TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 112 +TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 113 +TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 114 +TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 115 +TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 116 +TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 117 +TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 118 +TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 119 +TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 120 +TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 121 +TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 122 +TCP_PERF_SEL_TCC_ATOMIC_REQ = 123 +TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 124 +TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 125 +TCP_PERF_SEL_TOTAL_ACCESSES = 126 +TCP_PERF_SEL_TOTAL_READ = 127 +TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 128 +TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 129 +TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 130 +TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 131 +TCP_PERF_SEL_TOTAL_NON_READ = 132 +TCP_PERF_SEL_TOTAL_WRITE = 133 +TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 134 +TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 135 +TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 136 +TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 137 +TCP_PERF_SEL_DISPLAY_MICROTILING = 138 +TCP_PERF_SEL_THIN_MICROTILING = 139 +TCP_PERF_SEL_DEPTH_MICROTILING = 140 +TCP_PERF_SEL_ARR_PRT_THIN1 = 141 +TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 142 +TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 143 +TCP_PERF_SEL_ARR_PRT_THICK = 144 +TCP_PERF_SEL_ARR_PRT_2D_THICK = 145 +TCP_PERF_SEL_ARR_PRT_3D_THICK = 146 +TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 147 +TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 148 +TCP_PERF_SEL_UNALIGNED = 149 +TCP_PERF_SEL_ROTATED_MICROTILING = 150 +TCP_PERF_SEL_THICK_MICROTILING = 151 +TCP_PERF_SEL_ATC = 152 +TCP_PERF_SEL_POWER_STALL = 153 +TCP_PERF_SEL_RESERVED_154 = 154 +TCP_PERF_SEL_TCC_LRU_REQ = 155 +TCP_PERF_SEL_TCC_STREAM_REQ = 156 +TCP_PERF_SEL_TCC_NC_READ_REQ = 157 +TCP_PERF_SEL_TCC_NC_WRITE_REQ = 158 +TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 159 +TCP_PERF_SEL_TCC_UC_READ_REQ = 160 +TCP_PERF_SEL_TCC_UC_WRITE_REQ = 161 +TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 162 +TCP_PERF_SEL_TCC_CC_READ_REQ = 163 +TCP_PERF_SEL_TCC_CC_WRITE_REQ = 164 +TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 165 +TCP_PERF_SEL_TCC_DCC_REQ = 166 +TCP_PERF_SEL_TCC_PHYSICAL_REQ = 167 +TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 168 +TCP_PERF_SEL_VOLATILE = 169 +TCP_PERF_SEL_TC_TA_XNACK_STALL = 170 +TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL = 171 +TCP_PERF_SEL_SHOOTDOWN = 172 +TCP_PERF_SEL_UTCL1_TRANSLATION_MISS = 173 +TCP_PERF_SEL_UTCL1_PERMISSION_MISS = 174 +TCP_PERF_SEL_UTCL1_REQUEST = 175 +TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 176 +TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 177 +TCP_PERF_SEL_UTCL1_LFIFO_FULL = 178 +TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 179 +TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 180 +TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT = 181 +TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 182 +TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB = 183 +TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA = 184 +TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1 = 185 +TCP_PERF_SEL_IMG_READ_FMT_ETC2_R = 186 +TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG = 187 +TCP_PERF_SEL_IMG_READ_FMT_8_AS_32 = 188 +TCP_PERF_SEL_IMG_READ_FMT_8_AS_64 = 189 +TCP_PERF_SEL_IMG_READ_FMT_16_AS_64 = 190 +TCP_PERF_SEL_IMG_READ_FMT_16_AS_128 = 191 +TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32 = 192 +TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64 = 193 +TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64 = 194 +TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128 = 195 +TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_POLICIES' +TCP_CACHE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_POLICY_MISS_LRU', + 1: 'TCP_CACHE_POLICY_MISS_EVICT', + 2: 'TCP_CACHE_POLICY_HIT_LRU', + 3: 'TCP_CACHE_POLICY_HIT_EVICT', +} +TCP_CACHE_POLICY_MISS_LRU = 0 +TCP_CACHE_POLICY_MISS_EVICT = 1 +TCP_CACHE_POLICY_HIT_LRU = 2 +TCP_CACHE_POLICY_HIT_EVICT = 3 +TCP_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_STORE_POLICIES' +TCP_CACHE_STORE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', + 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', +} +TCP_CACHE_STORE_POLICY_WT_LRU = 0 +TCP_CACHE_STORE_POLICY_WT_EVICT = 1 +TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_WATCH_MODES' +TCP_WATCH_MODES__enumvalues = { + 0: 'TCP_WATCH_MODE_READ', + 1: 'TCP_WATCH_MODE_NONREAD', + 2: 'TCP_WATCH_MODE_ATOMIC', + 3: 'TCP_WATCH_MODE_ALL', +} +TCP_WATCH_MODE_READ = 0 +TCP_WATCH_MODE_NONREAD = 1 +TCP_WATCH_MODE_ATOMIC = 2 +TCP_WATCH_MODE_ALL = 3 +TCP_WATCH_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_DATA_SEL' +TCP_DSM_DATA_SEL__enumvalues = { + 0: 'TCP_DSM_DISABLE', + 1: 'TCP_DSM_SEL0', + 2: 'TCP_DSM_SEL1', + 3: 'TCP_DSM_SEL_BOTH', +} +TCP_DSM_DISABLE = 0 +TCP_DSM_SEL0 = 1 +TCP_DSM_SEL1 = 2 +TCP_DSM_SEL_BOTH = 3 +TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_SINGLE_WRITE' +TCP_DSM_SINGLE_WRITE__enumvalues = { + 0: 'TCP_DSM_SINGLE_WRITE_DIS', + 1: 'TCP_DSM_SINGLE_WRITE_EN', +} +TCP_DSM_SINGLE_WRITE_DIS = 0 +TCP_DSM_SINGLE_WRITE_EN = 1 +TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_INJECT_SEL' +TCP_DSM_INJECT_SEL__enumvalues = { + 0: 'TCP_DSM_INJECT_SEL0', + 1: 'TCP_DSM_INJECT_SEL1', + 2: 'TCP_DSM_INJECT_SEL2', + 3: 'TCP_DSM_INJECT_SEL3', +} +TCP_DSM_INJECT_SEL0 = 0 +TCP_DSM_INJECT_SEL1 = 1 +TCP_DSM_INJECT_SEL2 = 2 +TCP_DSM_INJECT_SEL3 = 3 +TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_PERF_SEL' +TCC_PERF_SEL__enumvalues = { + 0: 'TCC_PERF_SEL_NONE', + 1: 'TCC_PERF_SEL_CYCLE', + 2: 'TCC_PERF_SEL_BUSY', + 3: 'TCC_PERF_SEL_REQ', + 4: 'TCC_PERF_SEL_STREAMING_REQ', + 5: 'TCC_PERF_SEL_EXE_REQ', + 6: 'TCC_PERF_SEL_COMPRESSED_REQ', + 7: 'TCC_PERF_SEL_COMPRESSED_0_REQ', + 8: 'TCC_PERF_SEL_METADATA_REQ', + 9: 'TCC_PERF_SEL_NC_VIRTUAL_REQ', + 10: 'TCC_PERF_SEL_UC_VIRTUAL_REQ', + 11: 'TCC_PERF_SEL_CC_PHYSICAL_REQ', + 12: 'TCC_PERF_SEL_PROBE', + 13: 'TCC_PERF_SEL_PROBE_ALL', + 14: 'TCC_PERF_SEL_READ', + 15: 'TCC_PERF_SEL_WRITE', + 16: 'TCC_PERF_SEL_ATOMIC', + 17: 'TCC_PERF_SEL_HIT', + 18: 'TCC_PERF_SEL_SECTOR_HIT', + 19: 'TCC_PERF_SEL_MISS', + 20: 'TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT', + 21: 'TCC_PERF_SEL_FULLY_WRITTEN_HIT', + 22: 'TCC_PERF_SEL_WRITEBACK', + 23: 'TCC_PERF_SEL_LATENCY_FIFO_FULL', + 24: 'TCC_PERF_SEL_SRC_FIFO_FULL', + 25: 'TCC_PERF_SEL_HOLE_FIFO_FULL', + 26: 'TCC_PERF_SEL_EA_WRREQ', + 27: 'TCC_PERF_SEL_EA_WRREQ_64B', + 28: 'TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND', + 29: 'TCC_PERF_SEL_EA_WR_UNCACHED_32B', + 30: 'TCC_PERF_SEL_EA_WRREQ_STALL', + 31: 'TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL', + 32: 'TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', + 33: 'TCC_PERF_SEL_EA_WRREQ_LEVEL', + 34: 'TCC_PERF_SEL_EA_ATOMIC', + 35: 'TCC_PERF_SEL_EA_ATOMIC_LEVEL', + 36: 'TCC_PERF_SEL_EA_RDREQ', + 37: 'TCC_PERF_SEL_EA_RDREQ_32B', + 38: 'TCC_PERF_SEL_EA_RD_UNCACHED_32B', + 39: 'TCC_PERF_SEL_EA_RD_MDC_32B', + 40: 'TCC_PERF_SEL_EA_RD_COMPRESSED_32B', + 41: 'TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL', + 42: 'TCC_PERF_SEL_EA_RDREQ_LEVEL', + 43: 'TCC_PERF_SEL_TAG_STALL', + 44: 'TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 45: 'TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 46: 'TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 47: 'TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 48: 'TCC_PERF_SEL_TAG_PROBE_STALL', + 49: 'TCC_PERF_SEL_TAG_PROBE_FILTER_STALL', + 50: 'TCC_PERF_SEL_READ_RETURN_TIMEOUT', + 51: 'TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 52: 'TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 53: 'TCC_PERF_SEL_BUBBLE', + 54: 'TCC_PERF_SEL_RETURN_ACK', + 55: 'TCC_PERF_SEL_RETURN_DATA', + 56: 'TCC_PERF_SEL_RETURN_HOLE', + 57: 'TCC_PERF_SEL_RETURN_ACK_HOLE', + 58: 'TCC_PERF_SEL_IB_REQ', + 59: 'TCC_PERF_SEL_IB_STALL', + 60: 'TCC_PERF_SEL_IB_TAG_STALL', + 61: 'TCC_PERF_SEL_IB_MDC_STALL', + 62: 'TCC_PERF_SEL_TCA_LEVEL', + 63: 'TCC_PERF_SEL_HOLE_LEVEL', + 64: 'TCC_PERF_SEL_NORMAL_WRITEBACK', + 65: 'TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK', + 66: 'TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK', + 67: 'TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK', + 68: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK', + 69: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK', + 70: 'TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK', + 71: 'TCC_PERF_SEL_NORMAL_EVICT', + 72: 'TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT', + 73: 'TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT', + 74: 'TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT', + 75: 'TCC_PERF_SEL_TC_OP_WBINVL2_EVICT', + 76: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT', + 77: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT', + 78: 'TCC_PERF_SEL_ALL_TC_OP_INV_EVICT', + 79: 'TCC_PERF_SEL_PROBE_EVICT', + 80: 'TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE', + 81: 'TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE', + 82: 'TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE', + 83: 'TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE', + 84: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE', + 85: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE', + 86: 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE', + 87: 'TCC_PERF_SEL_TC_OP_WBL2_NC_START', + 88: 'TCC_PERF_SEL_TC_OP_WBL2_WC_START', + 89: 'TCC_PERF_SEL_TC_OP_INVL2_NC_START', + 90: 'TCC_PERF_SEL_TC_OP_WBINVL2_START', + 91: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_START', + 92: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_START', + 93: 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 94: 'TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH', + 95: 'TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH', + 96: 'TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH', + 97: 'TCC_PERF_SEL_TC_OP_WBINVL2_FINISH', + 98: 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH', + 99: 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH', + 100: 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH', + 101: 'TCC_PERF_SEL_MDC_REQ', + 102: 'TCC_PERF_SEL_MDC_LEVEL', + 103: 'TCC_PERF_SEL_MDC_TAG_HIT', + 104: 'TCC_PERF_SEL_MDC_SECTOR_HIT', + 105: 'TCC_PERF_SEL_MDC_SECTOR_MISS', + 106: 'TCC_PERF_SEL_MDC_TAG_STALL', + 107: 'TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', + 108: 'TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', + 109: 'TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', + 110: 'TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', + 111: 'TCC_PERF_SEL_PROBE_FILTER_DISABLED', + 128: 'TCC_PERF_SEL_CLIENT0_REQ', + 129: 'TCC_PERF_SEL_CLIENT1_REQ', + 130: 'TCC_PERF_SEL_CLIENT2_REQ', + 131: 'TCC_PERF_SEL_CLIENT3_REQ', + 132: 'TCC_PERF_SEL_CLIENT4_REQ', + 133: 'TCC_PERF_SEL_CLIENT5_REQ', + 134: 'TCC_PERF_SEL_CLIENT6_REQ', + 135: 'TCC_PERF_SEL_CLIENT7_REQ', + 136: 'TCC_PERF_SEL_CLIENT8_REQ', + 137: 'TCC_PERF_SEL_CLIENT9_REQ', + 138: 'TCC_PERF_SEL_CLIENT10_REQ', + 139: 'TCC_PERF_SEL_CLIENT11_REQ', + 140: 'TCC_PERF_SEL_CLIENT12_REQ', + 141: 'TCC_PERF_SEL_CLIENT13_REQ', + 142: 'TCC_PERF_SEL_CLIENT14_REQ', + 143: 'TCC_PERF_SEL_CLIENT15_REQ', + 144: 'TCC_PERF_SEL_CLIENT16_REQ', + 145: 'TCC_PERF_SEL_CLIENT17_REQ', + 146: 'TCC_PERF_SEL_CLIENT18_REQ', + 147: 'TCC_PERF_SEL_CLIENT19_REQ', + 148: 'TCC_PERF_SEL_CLIENT20_REQ', + 149: 'TCC_PERF_SEL_CLIENT21_REQ', + 150: 'TCC_PERF_SEL_CLIENT22_REQ', + 151: 'TCC_PERF_SEL_CLIENT23_REQ', + 152: 'TCC_PERF_SEL_CLIENT24_REQ', + 153: 'TCC_PERF_SEL_CLIENT25_REQ', + 154: 'TCC_PERF_SEL_CLIENT26_REQ', + 155: 'TCC_PERF_SEL_CLIENT27_REQ', + 156: 'TCC_PERF_SEL_CLIENT28_REQ', + 157: 'TCC_PERF_SEL_CLIENT29_REQ', + 158: 'TCC_PERF_SEL_CLIENT30_REQ', + 159: 'TCC_PERF_SEL_CLIENT31_REQ', + 160: 'TCC_PERF_SEL_CLIENT32_REQ', + 161: 'TCC_PERF_SEL_CLIENT33_REQ', + 162: 'TCC_PERF_SEL_CLIENT34_REQ', + 163: 'TCC_PERF_SEL_CLIENT35_REQ', + 164: 'TCC_PERF_SEL_CLIENT36_REQ', + 165: 'TCC_PERF_SEL_CLIENT37_REQ', + 166: 'TCC_PERF_SEL_CLIENT38_REQ', + 167: 'TCC_PERF_SEL_CLIENT39_REQ', + 168: 'TCC_PERF_SEL_CLIENT40_REQ', + 169: 'TCC_PERF_SEL_CLIENT41_REQ', + 170: 'TCC_PERF_SEL_CLIENT42_REQ', + 171: 'TCC_PERF_SEL_CLIENT43_REQ', + 172: 'TCC_PERF_SEL_CLIENT44_REQ', + 173: 'TCC_PERF_SEL_CLIENT45_REQ', + 174: 'TCC_PERF_SEL_CLIENT46_REQ', + 175: 'TCC_PERF_SEL_CLIENT47_REQ', + 176: 'TCC_PERF_SEL_CLIENT48_REQ', + 177: 'TCC_PERF_SEL_CLIENT49_REQ', + 178: 'TCC_PERF_SEL_CLIENT50_REQ', + 179: 'TCC_PERF_SEL_CLIENT51_REQ', + 180: 'TCC_PERF_SEL_CLIENT52_REQ', + 181: 'TCC_PERF_SEL_CLIENT53_REQ', + 182: 'TCC_PERF_SEL_CLIENT54_REQ', + 183: 'TCC_PERF_SEL_CLIENT55_REQ', + 184: 'TCC_PERF_SEL_CLIENT56_REQ', + 185: 'TCC_PERF_SEL_CLIENT57_REQ', + 186: 'TCC_PERF_SEL_CLIENT58_REQ', + 187: 'TCC_PERF_SEL_CLIENT59_REQ', + 188: 'TCC_PERF_SEL_CLIENT60_REQ', + 189: 'TCC_PERF_SEL_CLIENT61_REQ', + 190: 'TCC_PERF_SEL_CLIENT62_REQ', + 191: 'TCC_PERF_SEL_CLIENT63_REQ', + 192: 'TCC_PERF_SEL_CLIENT64_REQ', + 193: 'TCC_PERF_SEL_CLIENT65_REQ', + 194: 'TCC_PERF_SEL_CLIENT66_REQ', + 195: 'TCC_PERF_SEL_CLIENT67_REQ', + 196: 'TCC_PERF_SEL_CLIENT68_REQ', + 197: 'TCC_PERF_SEL_CLIENT69_REQ', + 198: 'TCC_PERF_SEL_CLIENT70_REQ', + 199: 'TCC_PERF_SEL_CLIENT71_REQ', + 200: 'TCC_PERF_SEL_CLIENT72_REQ', + 201: 'TCC_PERF_SEL_CLIENT73_REQ', + 202: 'TCC_PERF_SEL_CLIENT74_REQ', + 203: 'TCC_PERF_SEL_CLIENT75_REQ', + 204: 'TCC_PERF_SEL_CLIENT76_REQ', + 205: 'TCC_PERF_SEL_CLIENT77_REQ', + 206: 'TCC_PERF_SEL_CLIENT78_REQ', + 207: 'TCC_PERF_SEL_CLIENT79_REQ', + 208: 'TCC_PERF_SEL_CLIENT80_REQ', + 209: 'TCC_PERF_SEL_CLIENT81_REQ', + 210: 'TCC_PERF_SEL_CLIENT82_REQ', + 211: 'TCC_PERF_SEL_CLIENT83_REQ', + 212: 'TCC_PERF_SEL_CLIENT84_REQ', + 213: 'TCC_PERF_SEL_CLIENT85_REQ', + 214: 'TCC_PERF_SEL_CLIENT86_REQ', + 215: 'TCC_PERF_SEL_CLIENT87_REQ', + 216: 'TCC_PERF_SEL_CLIENT88_REQ', + 217: 'TCC_PERF_SEL_CLIENT89_REQ', + 218: 'TCC_PERF_SEL_CLIENT90_REQ', + 219: 'TCC_PERF_SEL_CLIENT91_REQ', + 220: 'TCC_PERF_SEL_CLIENT92_REQ', + 221: 'TCC_PERF_SEL_CLIENT93_REQ', + 222: 'TCC_PERF_SEL_CLIENT94_REQ', + 223: 'TCC_PERF_SEL_CLIENT95_REQ', + 224: 'TCC_PERF_SEL_CLIENT96_REQ', + 225: 'TCC_PERF_SEL_CLIENT97_REQ', + 226: 'TCC_PERF_SEL_CLIENT98_REQ', + 227: 'TCC_PERF_SEL_CLIENT99_REQ', + 228: 'TCC_PERF_SEL_CLIENT100_REQ', + 229: 'TCC_PERF_SEL_CLIENT101_REQ', + 230: 'TCC_PERF_SEL_CLIENT102_REQ', + 231: 'TCC_PERF_SEL_CLIENT103_REQ', + 232: 'TCC_PERF_SEL_CLIENT104_REQ', + 233: 'TCC_PERF_SEL_CLIENT105_REQ', + 234: 'TCC_PERF_SEL_CLIENT106_REQ', + 235: 'TCC_PERF_SEL_CLIENT107_REQ', + 236: 'TCC_PERF_SEL_CLIENT108_REQ', + 237: 'TCC_PERF_SEL_CLIENT109_REQ', + 238: 'TCC_PERF_SEL_CLIENT110_REQ', + 239: 'TCC_PERF_SEL_CLIENT111_REQ', + 240: 'TCC_PERF_SEL_CLIENT112_REQ', + 241: 'TCC_PERF_SEL_CLIENT113_REQ', + 242: 'TCC_PERF_SEL_CLIENT114_REQ', + 243: 'TCC_PERF_SEL_CLIENT115_REQ', + 244: 'TCC_PERF_SEL_CLIENT116_REQ', + 245: 'TCC_PERF_SEL_CLIENT117_REQ', + 246: 'TCC_PERF_SEL_CLIENT118_REQ', + 247: 'TCC_PERF_SEL_CLIENT119_REQ', + 248: 'TCC_PERF_SEL_CLIENT120_REQ', + 249: 'TCC_PERF_SEL_CLIENT121_REQ', + 250: 'TCC_PERF_SEL_CLIENT122_REQ', + 251: 'TCC_PERF_SEL_CLIENT123_REQ', + 252: 'TCC_PERF_SEL_CLIENT124_REQ', + 253: 'TCC_PERF_SEL_CLIENT125_REQ', + 254: 'TCC_PERF_SEL_CLIENT126_REQ', + 255: 'TCC_PERF_SEL_CLIENT127_REQ', +} +TCC_PERF_SEL_NONE = 0 +TCC_PERF_SEL_CYCLE = 1 +TCC_PERF_SEL_BUSY = 2 +TCC_PERF_SEL_REQ = 3 +TCC_PERF_SEL_STREAMING_REQ = 4 +TCC_PERF_SEL_EXE_REQ = 5 +TCC_PERF_SEL_COMPRESSED_REQ = 6 +TCC_PERF_SEL_COMPRESSED_0_REQ = 7 +TCC_PERF_SEL_METADATA_REQ = 8 +TCC_PERF_SEL_NC_VIRTUAL_REQ = 9 +TCC_PERF_SEL_UC_VIRTUAL_REQ = 10 +TCC_PERF_SEL_CC_PHYSICAL_REQ = 11 +TCC_PERF_SEL_PROBE = 12 +TCC_PERF_SEL_PROBE_ALL = 13 +TCC_PERF_SEL_READ = 14 +TCC_PERF_SEL_WRITE = 15 +TCC_PERF_SEL_ATOMIC = 16 +TCC_PERF_SEL_HIT = 17 +TCC_PERF_SEL_SECTOR_HIT = 18 +TCC_PERF_SEL_MISS = 19 +TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 20 +TCC_PERF_SEL_FULLY_WRITTEN_HIT = 21 +TCC_PERF_SEL_WRITEBACK = 22 +TCC_PERF_SEL_LATENCY_FIFO_FULL = 23 +TCC_PERF_SEL_SRC_FIFO_FULL = 24 +TCC_PERF_SEL_HOLE_FIFO_FULL = 25 +TCC_PERF_SEL_EA_WRREQ = 26 +TCC_PERF_SEL_EA_WRREQ_64B = 27 +TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 28 +TCC_PERF_SEL_EA_WR_UNCACHED_32B = 29 +TCC_PERF_SEL_EA_WRREQ_STALL = 30 +TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL = 31 +TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 32 +TCC_PERF_SEL_EA_WRREQ_LEVEL = 33 +TCC_PERF_SEL_EA_ATOMIC = 34 +TCC_PERF_SEL_EA_ATOMIC_LEVEL = 35 +TCC_PERF_SEL_EA_RDREQ = 36 +TCC_PERF_SEL_EA_RDREQ_32B = 37 +TCC_PERF_SEL_EA_RD_UNCACHED_32B = 38 +TCC_PERF_SEL_EA_RD_MDC_32B = 39 +TCC_PERF_SEL_EA_RD_COMPRESSED_32B = 40 +TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL = 41 +TCC_PERF_SEL_EA_RDREQ_LEVEL = 42 +TCC_PERF_SEL_TAG_STALL = 43 +TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 44 +TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 45 +TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 46 +TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 47 +TCC_PERF_SEL_TAG_PROBE_STALL = 48 +TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 49 +TCC_PERF_SEL_READ_RETURN_TIMEOUT = 50 +TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 51 +TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 52 +TCC_PERF_SEL_BUBBLE = 53 +TCC_PERF_SEL_RETURN_ACK = 54 +TCC_PERF_SEL_RETURN_DATA = 55 +TCC_PERF_SEL_RETURN_HOLE = 56 +TCC_PERF_SEL_RETURN_ACK_HOLE = 57 +TCC_PERF_SEL_IB_REQ = 58 +TCC_PERF_SEL_IB_STALL = 59 +TCC_PERF_SEL_IB_TAG_STALL = 60 +TCC_PERF_SEL_IB_MDC_STALL = 61 +TCC_PERF_SEL_TCA_LEVEL = 62 +TCC_PERF_SEL_HOLE_LEVEL = 63 +TCC_PERF_SEL_NORMAL_WRITEBACK = 64 +TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 65 +TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK = 66 +TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 67 +TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 68 +TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 69 +TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 70 +TCC_PERF_SEL_NORMAL_EVICT = 71 +TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 72 +TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT = 73 +TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 74 +TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 75 +TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 76 +TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 77 +TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 78 +TCC_PERF_SEL_PROBE_EVICT = 79 +TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 80 +TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE = 81 +TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 82 +TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 83 +TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 84 +TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 85 +TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 86 +TCC_PERF_SEL_TC_OP_WBL2_NC_START = 87 +TCC_PERF_SEL_TC_OP_WBL2_WC_START = 88 +TCC_PERF_SEL_TC_OP_INVL2_NC_START = 89 +TCC_PERF_SEL_TC_OP_WBINVL2_START = 90 +TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 91 +TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 92 +TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 93 +TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 94 +TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH = 95 +TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 96 +TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 97 +TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 98 +TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 99 +TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 100 +TCC_PERF_SEL_MDC_REQ = 101 +TCC_PERF_SEL_MDC_LEVEL = 102 +TCC_PERF_SEL_MDC_TAG_HIT = 103 +TCC_PERF_SEL_MDC_SECTOR_HIT = 104 +TCC_PERF_SEL_MDC_SECTOR_MISS = 105 +TCC_PERF_SEL_MDC_TAG_STALL = 106 +TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 107 +TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 108 +TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 109 +TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 110 +TCC_PERF_SEL_PROBE_FILTER_DISABLED = 111 +TCC_PERF_SEL_CLIENT0_REQ = 128 +TCC_PERF_SEL_CLIENT1_REQ = 129 +TCC_PERF_SEL_CLIENT2_REQ = 130 +TCC_PERF_SEL_CLIENT3_REQ = 131 +TCC_PERF_SEL_CLIENT4_REQ = 132 +TCC_PERF_SEL_CLIENT5_REQ = 133 +TCC_PERF_SEL_CLIENT6_REQ = 134 +TCC_PERF_SEL_CLIENT7_REQ = 135 +TCC_PERF_SEL_CLIENT8_REQ = 136 +TCC_PERF_SEL_CLIENT9_REQ = 137 +TCC_PERF_SEL_CLIENT10_REQ = 138 +TCC_PERF_SEL_CLIENT11_REQ = 139 +TCC_PERF_SEL_CLIENT12_REQ = 140 +TCC_PERF_SEL_CLIENT13_REQ = 141 +TCC_PERF_SEL_CLIENT14_REQ = 142 +TCC_PERF_SEL_CLIENT15_REQ = 143 +TCC_PERF_SEL_CLIENT16_REQ = 144 +TCC_PERF_SEL_CLIENT17_REQ = 145 +TCC_PERF_SEL_CLIENT18_REQ = 146 +TCC_PERF_SEL_CLIENT19_REQ = 147 +TCC_PERF_SEL_CLIENT20_REQ = 148 +TCC_PERF_SEL_CLIENT21_REQ = 149 +TCC_PERF_SEL_CLIENT22_REQ = 150 +TCC_PERF_SEL_CLIENT23_REQ = 151 +TCC_PERF_SEL_CLIENT24_REQ = 152 +TCC_PERF_SEL_CLIENT25_REQ = 153 +TCC_PERF_SEL_CLIENT26_REQ = 154 +TCC_PERF_SEL_CLIENT27_REQ = 155 +TCC_PERF_SEL_CLIENT28_REQ = 156 +TCC_PERF_SEL_CLIENT29_REQ = 157 +TCC_PERF_SEL_CLIENT30_REQ = 158 +TCC_PERF_SEL_CLIENT31_REQ = 159 +TCC_PERF_SEL_CLIENT32_REQ = 160 +TCC_PERF_SEL_CLIENT33_REQ = 161 +TCC_PERF_SEL_CLIENT34_REQ = 162 +TCC_PERF_SEL_CLIENT35_REQ = 163 +TCC_PERF_SEL_CLIENT36_REQ = 164 +TCC_PERF_SEL_CLIENT37_REQ = 165 +TCC_PERF_SEL_CLIENT38_REQ = 166 +TCC_PERF_SEL_CLIENT39_REQ = 167 +TCC_PERF_SEL_CLIENT40_REQ = 168 +TCC_PERF_SEL_CLIENT41_REQ = 169 +TCC_PERF_SEL_CLIENT42_REQ = 170 +TCC_PERF_SEL_CLIENT43_REQ = 171 +TCC_PERF_SEL_CLIENT44_REQ = 172 +TCC_PERF_SEL_CLIENT45_REQ = 173 +TCC_PERF_SEL_CLIENT46_REQ = 174 +TCC_PERF_SEL_CLIENT47_REQ = 175 +TCC_PERF_SEL_CLIENT48_REQ = 176 +TCC_PERF_SEL_CLIENT49_REQ = 177 +TCC_PERF_SEL_CLIENT50_REQ = 178 +TCC_PERF_SEL_CLIENT51_REQ = 179 +TCC_PERF_SEL_CLIENT52_REQ = 180 +TCC_PERF_SEL_CLIENT53_REQ = 181 +TCC_PERF_SEL_CLIENT54_REQ = 182 +TCC_PERF_SEL_CLIENT55_REQ = 183 +TCC_PERF_SEL_CLIENT56_REQ = 184 +TCC_PERF_SEL_CLIENT57_REQ = 185 +TCC_PERF_SEL_CLIENT58_REQ = 186 +TCC_PERF_SEL_CLIENT59_REQ = 187 +TCC_PERF_SEL_CLIENT60_REQ = 188 +TCC_PERF_SEL_CLIENT61_REQ = 189 +TCC_PERF_SEL_CLIENT62_REQ = 190 +TCC_PERF_SEL_CLIENT63_REQ = 191 +TCC_PERF_SEL_CLIENT64_REQ = 192 +TCC_PERF_SEL_CLIENT65_REQ = 193 +TCC_PERF_SEL_CLIENT66_REQ = 194 +TCC_PERF_SEL_CLIENT67_REQ = 195 +TCC_PERF_SEL_CLIENT68_REQ = 196 +TCC_PERF_SEL_CLIENT69_REQ = 197 +TCC_PERF_SEL_CLIENT70_REQ = 198 +TCC_PERF_SEL_CLIENT71_REQ = 199 +TCC_PERF_SEL_CLIENT72_REQ = 200 +TCC_PERF_SEL_CLIENT73_REQ = 201 +TCC_PERF_SEL_CLIENT74_REQ = 202 +TCC_PERF_SEL_CLIENT75_REQ = 203 +TCC_PERF_SEL_CLIENT76_REQ = 204 +TCC_PERF_SEL_CLIENT77_REQ = 205 +TCC_PERF_SEL_CLIENT78_REQ = 206 +TCC_PERF_SEL_CLIENT79_REQ = 207 +TCC_PERF_SEL_CLIENT80_REQ = 208 +TCC_PERF_SEL_CLIENT81_REQ = 209 +TCC_PERF_SEL_CLIENT82_REQ = 210 +TCC_PERF_SEL_CLIENT83_REQ = 211 +TCC_PERF_SEL_CLIENT84_REQ = 212 +TCC_PERF_SEL_CLIENT85_REQ = 213 +TCC_PERF_SEL_CLIENT86_REQ = 214 +TCC_PERF_SEL_CLIENT87_REQ = 215 +TCC_PERF_SEL_CLIENT88_REQ = 216 +TCC_PERF_SEL_CLIENT89_REQ = 217 +TCC_PERF_SEL_CLIENT90_REQ = 218 +TCC_PERF_SEL_CLIENT91_REQ = 219 +TCC_PERF_SEL_CLIENT92_REQ = 220 +TCC_PERF_SEL_CLIENT93_REQ = 221 +TCC_PERF_SEL_CLIENT94_REQ = 222 +TCC_PERF_SEL_CLIENT95_REQ = 223 +TCC_PERF_SEL_CLIENT96_REQ = 224 +TCC_PERF_SEL_CLIENT97_REQ = 225 +TCC_PERF_SEL_CLIENT98_REQ = 226 +TCC_PERF_SEL_CLIENT99_REQ = 227 +TCC_PERF_SEL_CLIENT100_REQ = 228 +TCC_PERF_SEL_CLIENT101_REQ = 229 +TCC_PERF_SEL_CLIENT102_REQ = 230 +TCC_PERF_SEL_CLIENT103_REQ = 231 +TCC_PERF_SEL_CLIENT104_REQ = 232 +TCC_PERF_SEL_CLIENT105_REQ = 233 +TCC_PERF_SEL_CLIENT106_REQ = 234 +TCC_PERF_SEL_CLIENT107_REQ = 235 +TCC_PERF_SEL_CLIENT108_REQ = 236 +TCC_PERF_SEL_CLIENT109_REQ = 237 +TCC_PERF_SEL_CLIENT110_REQ = 238 +TCC_PERF_SEL_CLIENT111_REQ = 239 +TCC_PERF_SEL_CLIENT112_REQ = 240 +TCC_PERF_SEL_CLIENT113_REQ = 241 +TCC_PERF_SEL_CLIENT114_REQ = 242 +TCC_PERF_SEL_CLIENT115_REQ = 243 +TCC_PERF_SEL_CLIENT116_REQ = 244 +TCC_PERF_SEL_CLIENT117_REQ = 245 +TCC_PERF_SEL_CLIENT118_REQ = 246 +TCC_PERF_SEL_CLIENT119_REQ = 247 +TCC_PERF_SEL_CLIENT120_REQ = 248 +TCC_PERF_SEL_CLIENT121_REQ = 249 +TCC_PERF_SEL_CLIENT122_REQ = 250 +TCC_PERF_SEL_CLIENT123_REQ = 251 +TCC_PERF_SEL_CLIENT124_REQ = 252 +TCC_PERF_SEL_CLIENT125_REQ = 253 +TCC_PERF_SEL_CLIENT126_REQ = 254 +TCC_PERF_SEL_CLIENT127_REQ = 255 +TCC_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCA_PERF_SEL' +TCA_PERF_SEL__enumvalues = { + 0: 'TCA_PERF_SEL_NONE', + 1: 'TCA_PERF_SEL_CYCLE', + 2: 'TCA_PERF_SEL_BUSY', + 3: 'TCA_PERF_SEL_FORCED_HOLE_TCC0', + 4: 'TCA_PERF_SEL_FORCED_HOLE_TCC1', + 5: 'TCA_PERF_SEL_FORCED_HOLE_TCC2', + 6: 'TCA_PERF_SEL_FORCED_HOLE_TCC3', + 7: 'TCA_PERF_SEL_FORCED_HOLE_TCC4', + 8: 'TCA_PERF_SEL_FORCED_HOLE_TCC5', + 9: 'TCA_PERF_SEL_FORCED_HOLE_TCC6', + 10: 'TCA_PERF_SEL_FORCED_HOLE_TCC7', + 11: 'TCA_PERF_SEL_REQ_TCC0', + 12: 'TCA_PERF_SEL_REQ_TCC1', + 13: 'TCA_PERF_SEL_REQ_TCC2', + 14: 'TCA_PERF_SEL_REQ_TCC3', + 15: 'TCA_PERF_SEL_REQ_TCC4', + 16: 'TCA_PERF_SEL_REQ_TCC5', + 17: 'TCA_PERF_SEL_REQ_TCC6', + 18: 'TCA_PERF_SEL_REQ_TCC7', + 19: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0', + 20: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1', + 21: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2', + 22: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3', + 23: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4', + 24: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5', + 25: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6', + 26: 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7', + 27: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC0', + 28: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC1', + 29: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC2', + 30: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC3', + 31: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC4', + 32: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC5', + 33: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC6', + 34: 'TCA_PERF_SEL_CROSSBAR_STALL_TCC7', +} +TCA_PERF_SEL_NONE = 0 +TCA_PERF_SEL_CYCLE = 1 +TCA_PERF_SEL_BUSY = 2 +TCA_PERF_SEL_FORCED_HOLE_TCC0 = 3 +TCA_PERF_SEL_FORCED_HOLE_TCC1 = 4 +TCA_PERF_SEL_FORCED_HOLE_TCC2 = 5 +TCA_PERF_SEL_FORCED_HOLE_TCC3 = 6 +TCA_PERF_SEL_FORCED_HOLE_TCC4 = 7 +TCA_PERF_SEL_FORCED_HOLE_TCC5 = 8 +TCA_PERF_SEL_FORCED_HOLE_TCC6 = 9 +TCA_PERF_SEL_FORCED_HOLE_TCC7 = 10 +TCA_PERF_SEL_REQ_TCC0 = 11 +TCA_PERF_SEL_REQ_TCC1 = 12 +TCA_PERF_SEL_REQ_TCC2 = 13 +TCA_PERF_SEL_REQ_TCC3 = 14 +TCA_PERF_SEL_REQ_TCC4 = 15 +TCA_PERF_SEL_REQ_TCC5 = 16 +TCA_PERF_SEL_REQ_TCC6 = 17 +TCA_PERF_SEL_REQ_TCC7 = 18 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 19 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 20 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 21 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 22 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 23 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 24 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 25 +TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 26 +TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 27 +TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 28 +TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 29 +TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 30 +TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 31 +TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 32 +TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 33 +TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 34 +TCA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_PERF_SEL' +GRBM_PERF_SEL__enumvalues = { + 0: 'GRBM_PERF_SEL_COUNT', + 1: 'GRBM_PERF_SEL_USER_DEFINED', + 2: 'GRBM_PERF_SEL_GUI_ACTIVE', + 3: 'GRBM_PERF_SEL_CP_BUSY', + 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', + 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', + 6: 'GRBM_PERF_SEL_CB_BUSY', + 7: 'GRBM_PERF_SEL_DB_BUSY', + 8: 'GRBM_PERF_SEL_PA_BUSY', + 9: 'GRBM_PERF_SEL_SC_BUSY', + 10: 'GRBM_PERF_SEL_RESERVED_6', + 11: 'GRBM_PERF_SEL_SPI_BUSY', + 12: 'GRBM_PERF_SEL_SX_BUSY', + 13: 'GRBM_PERF_SEL_TA_BUSY', + 14: 'GRBM_PERF_SEL_CB_CLEAN', + 15: 'GRBM_PERF_SEL_DB_CLEAN', + 16: 'GRBM_PERF_SEL_RESERVED_5', + 17: 'GRBM_PERF_SEL_VGT_BUSY', + 18: 'GRBM_PERF_SEL_RESERVED_4', + 19: 'GRBM_PERF_SEL_RESERVED_3', + 20: 'GRBM_PERF_SEL_RESERVED_2', + 21: 'GRBM_PERF_SEL_RESERVED_1', + 22: 'GRBM_PERF_SEL_RESERVED_0', + 23: 'GRBM_PERF_SEL_IA_BUSY', + 24: 'GRBM_PERF_SEL_IA_NO_DMA_BUSY', + 25: 'GRBM_PERF_SEL_GDS_BUSY', + 26: 'GRBM_PERF_SEL_BCI_BUSY', + 27: 'GRBM_PERF_SEL_RLC_BUSY', + 28: 'GRBM_PERF_SEL_TC_BUSY', + 29: 'GRBM_PERF_SEL_CPG_BUSY', + 30: 'GRBM_PERF_SEL_CPC_BUSY', + 31: 'GRBM_PERF_SEL_CPF_BUSY', + 32: 'GRBM_PERF_SEL_WD_BUSY', + 33: 'GRBM_PERF_SEL_WD_NO_DMA_BUSY', + 34: 'GRBM_PERF_SEL_UTCL2_BUSY', + 35: 'GRBM_PERF_SEL_EA_BUSY', + 36: 'GRBM_PERF_SEL_RMI_BUSY', + 37: 'GRBM_PERF_SEL_CPAXI_BUSY', +} +GRBM_PERF_SEL_COUNT = 0 +GRBM_PERF_SEL_USER_DEFINED = 1 +GRBM_PERF_SEL_GUI_ACTIVE = 2 +GRBM_PERF_SEL_CP_BUSY = 3 +GRBM_PERF_SEL_CP_COHER_BUSY = 4 +GRBM_PERF_SEL_CP_DMA_BUSY = 5 +GRBM_PERF_SEL_CB_BUSY = 6 +GRBM_PERF_SEL_DB_BUSY = 7 +GRBM_PERF_SEL_PA_BUSY = 8 +GRBM_PERF_SEL_SC_BUSY = 9 +GRBM_PERF_SEL_RESERVED_6 = 10 +GRBM_PERF_SEL_SPI_BUSY = 11 +GRBM_PERF_SEL_SX_BUSY = 12 +GRBM_PERF_SEL_TA_BUSY = 13 +GRBM_PERF_SEL_CB_CLEAN = 14 +GRBM_PERF_SEL_DB_CLEAN = 15 +GRBM_PERF_SEL_RESERVED_5 = 16 +GRBM_PERF_SEL_VGT_BUSY = 17 +GRBM_PERF_SEL_RESERVED_4 = 18 +GRBM_PERF_SEL_RESERVED_3 = 19 +GRBM_PERF_SEL_RESERVED_2 = 20 +GRBM_PERF_SEL_RESERVED_1 = 21 +GRBM_PERF_SEL_RESERVED_0 = 22 +GRBM_PERF_SEL_IA_BUSY = 23 +GRBM_PERF_SEL_IA_NO_DMA_BUSY = 24 +GRBM_PERF_SEL_GDS_BUSY = 25 +GRBM_PERF_SEL_BCI_BUSY = 26 +GRBM_PERF_SEL_RLC_BUSY = 27 +GRBM_PERF_SEL_TC_BUSY = 28 +GRBM_PERF_SEL_CPG_BUSY = 29 +GRBM_PERF_SEL_CPC_BUSY = 30 +GRBM_PERF_SEL_CPF_BUSY = 31 +GRBM_PERF_SEL_WD_BUSY = 32 +GRBM_PERF_SEL_WD_NO_DMA_BUSY = 33 +GRBM_PERF_SEL_UTCL2_BUSY = 34 +GRBM_PERF_SEL_EA_BUSY = 35 +GRBM_PERF_SEL_RMI_BUSY = 36 +GRBM_PERF_SEL_CPAXI_BUSY = 37 +GRBM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE0_PERF_SEL' +GRBM_SE0_PERF_SEL__enumvalues = { + 0: 'GRBM_SE0_PERF_SEL_COUNT', + 1: 'GRBM_SE0_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE0_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE0_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE0_PERF_SEL_SC_BUSY', + 5: 'GRBM_SE0_PERF_SEL_RESERVED_1', + 6: 'GRBM_SE0_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE0_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE0_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE0_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE0_PERF_SEL_DB_CLEAN', + 11: 'GRBM_SE0_PERF_SEL_RESERVED_0', + 12: 'GRBM_SE0_PERF_SEL_PA_BUSY', + 13: 'GRBM_SE0_PERF_SEL_VGT_BUSY', + 14: 'GRBM_SE0_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE0_PERF_SEL_RMI_BUSY', +} +GRBM_SE0_PERF_SEL_COUNT = 0 +GRBM_SE0_PERF_SEL_USER_DEFINED = 1 +GRBM_SE0_PERF_SEL_CB_BUSY = 2 +GRBM_SE0_PERF_SEL_DB_BUSY = 3 +GRBM_SE0_PERF_SEL_SC_BUSY = 4 +GRBM_SE0_PERF_SEL_RESERVED_1 = 5 +GRBM_SE0_PERF_SEL_SPI_BUSY = 6 +GRBM_SE0_PERF_SEL_SX_BUSY = 7 +GRBM_SE0_PERF_SEL_TA_BUSY = 8 +GRBM_SE0_PERF_SEL_CB_CLEAN = 9 +GRBM_SE0_PERF_SEL_DB_CLEAN = 10 +GRBM_SE0_PERF_SEL_RESERVED_0 = 11 +GRBM_SE0_PERF_SEL_PA_BUSY = 12 +GRBM_SE0_PERF_SEL_VGT_BUSY = 13 +GRBM_SE0_PERF_SEL_BCI_BUSY = 14 +GRBM_SE0_PERF_SEL_RMI_BUSY = 15 +GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE1_PERF_SEL' +GRBM_SE1_PERF_SEL__enumvalues = { + 0: 'GRBM_SE1_PERF_SEL_COUNT', + 1: 'GRBM_SE1_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE1_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE1_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE1_PERF_SEL_SC_BUSY', + 5: 'GRBM_SE1_PERF_SEL_RESERVED_1', + 6: 'GRBM_SE1_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE1_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE1_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE1_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE1_PERF_SEL_DB_CLEAN', + 11: 'GRBM_SE1_PERF_SEL_RESERVED_0', + 12: 'GRBM_SE1_PERF_SEL_PA_BUSY', + 13: 'GRBM_SE1_PERF_SEL_VGT_BUSY', + 14: 'GRBM_SE1_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE1_PERF_SEL_RMI_BUSY', +} +GRBM_SE1_PERF_SEL_COUNT = 0 +GRBM_SE1_PERF_SEL_USER_DEFINED = 1 +GRBM_SE1_PERF_SEL_CB_BUSY = 2 +GRBM_SE1_PERF_SEL_DB_BUSY = 3 +GRBM_SE1_PERF_SEL_SC_BUSY = 4 +GRBM_SE1_PERF_SEL_RESERVED_1 = 5 +GRBM_SE1_PERF_SEL_SPI_BUSY = 6 +GRBM_SE1_PERF_SEL_SX_BUSY = 7 +GRBM_SE1_PERF_SEL_TA_BUSY = 8 +GRBM_SE1_PERF_SEL_CB_CLEAN = 9 +GRBM_SE1_PERF_SEL_DB_CLEAN = 10 +GRBM_SE1_PERF_SEL_RESERVED_0 = 11 +GRBM_SE1_PERF_SEL_PA_BUSY = 12 +GRBM_SE1_PERF_SEL_VGT_BUSY = 13 +GRBM_SE1_PERF_SEL_BCI_BUSY = 14 +GRBM_SE1_PERF_SEL_RMI_BUSY = 15 +GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE2_PERF_SEL' +GRBM_SE2_PERF_SEL__enumvalues = { + 0: 'GRBM_SE2_PERF_SEL_COUNT', + 1: 'GRBM_SE2_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE2_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE2_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE2_PERF_SEL_SC_BUSY', + 5: 'GRBM_SE2_PERF_SEL_RESERVED_1', + 6: 'GRBM_SE2_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE2_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE2_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE2_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE2_PERF_SEL_DB_CLEAN', + 11: 'GRBM_SE2_PERF_SEL_RESERVED_0', + 12: 'GRBM_SE2_PERF_SEL_PA_BUSY', + 13: 'GRBM_SE2_PERF_SEL_VGT_BUSY', + 14: 'GRBM_SE2_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE2_PERF_SEL_RMI_BUSY', +} +GRBM_SE2_PERF_SEL_COUNT = 0 +GRBM_SE2_PERF_SEL_USER_DEFINED = 1 +GRBM_SE2_PERF_SEL_CB_BUSY = 2 +GRBM_SE2_PERF_SEL_DB_BUSY = 3 +GRBM_SE2_PERF_SEL_SC_BUSY = 4 +GRBM_SE2_PERF_SEL_RESERVED_1 = 5 +GRBM_SE2_PERF_SEL_SPI_BUSY = 6 +GRBM_SE2_PERF_SEL_SX_BUSY = 7 +GRBM_SE2_PERF_SEL_TA_BUSY = 8 +GRBM_SE2_PERF_SEL_CB_CLEAN = 9 +GRBM_SE2_PERF_SEL_DB_CLEAN = 10 +GRBM_SE2_PERF_SEL_RESERVED_0 = 11 +GRBM_SE2_PERF_SEL_PA_BUSY = 12 +GRBM_SE2_PERF_SEL_VGT_BUSY = 13 +GRBM_SE2_PERF_SEL_BCI_BUSY = 14 +GRBM_SE2_PERF_SEL_RMI_BUSY = 15 +GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE3_PERF_SEL' +GRBM_SE3_PERF_SEL__enumvalues = { + 0: 'GRBM_SE3_PERF_SEL_COUNT', + 1: 'GRBM_SE3_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE3_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE3_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE3_PERF_SEL_SC_BUSY', + 5: 'GRBM_SE3_PERF_SEL_RESERVED_1', + 6: 'GRBM_SE3_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE3_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE3_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE3_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE3_PERF_SEL_DB_CLEAN', + 11: 'GRBM_SE3_PERF_SEL_RESERVED_0', + 12: 'GRBM_SE3_PERF_SEL_PA_BUSY', + 13: 'GRBM_SE3_PERF_SEL_VGT_BUSY', + 14: 'GRBM_SE3_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE3_PERF_SEL_RMI_BUSY', +} +GRBM_SE3_PERF_SEL_COUNT = 0 +GRBM_SE3_PERF_SEL_USER_DEFINED = 1 +GRBM_SE3_PERF_SEL_CB_BUSY = 2 +GRBM_SE3_PERF_SEL_DB_BUSY = 3 +GRBM_SE3_PERF_SEL_SC_BUSY = 4 +GRBM_SE3_PERF_SEL_RESERVED_1 = 5 +GRBM_SE3_PERF_SEL_SPI_BUSY = 6 +GRBM_SE3_PERF_SEL_SX_BUSY = 7 +GRBM_SE3_PERF_SEL_TA_BUSY = 8 +GRBM_SE3_PERF_SEL_CB_CLEAN = 9 +GRBM_SE3_PERF_SEL_DB_CLEAN = 10 +GRBM_SE3_PERF_SEL_RESERVED_0 = 11 +GRBM_SE3_PERF_SEL_PA_BUSY = 12 +GRBM_SE3_PERF_SEL_VGT_BUSY = 13 +GRBM_SE3_PERF_SEL_BCI_BUSY = 14 +GRBM_SE3_PERF_SEL_RMI_BUSY = 15 +GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_RING_ID' +CP_RING_ID__enumvalues = { + 0: 'RINGID0', + 1: 'RINGID1', + 2: 'RINGID2', + 3: 'RINGID3', +} +RINGID0 = 0 +RINGID1 = 1 +RINGID2 = 2 +RINGID3 = 3 +CP_RING_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PIPE_ID' +CP_PIPE_ID__enumvalues = { + 0: 'PIPE_ID0', + 1: 'PIPE_ID1', + 2: 'PIPE_ID2', + 3: 'PIPE_ID3', +} +PIPE_ID0 = 0 +PIPE_ID1 = 1 +PIPE_ID2 = 2 +PIPE_ID3 = 3 +CP_PIPE_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ME_ID' +CP_ME_ID__enumvalues = { + 0: 'ME_ID0', + 1: 'ME_ID1', + 2: 'ME_ID2', + 3: 'ME_ID3', +} +ME_ID0 = 0 +ME_ID1 = 1 +ME_ID2 = 2 +ME_ID3 = 3 +CP_ME_ID = ctypes.c_uint32 # enum + +# values for enumeration 'SPM_PERFMON_STATE' +SPM_PERFMON_STATE__enumvalues = { + 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'STRM_PERFMON_STATE_START_COUNTING', + 2: 'STRM_PERFMON_STATE_STOP_COUNTING', + 3: 'STRM_PERFMON_STATE_RESERVED_3', + 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 +STRM_PERFMON_STATE_START_COUNTING = 1 +STRM_PERFMON_STATE_STOP_COUNTING = 2 +STRM_PERFMON_STATE_RESERVED_3 = 3 +STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +SPM_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_STATE' +CP_PERFMON_STATE__enumvalues = { + 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'CP_PERFMON_STATE_START_COUNTING', + 2: 'CP_PERFMON_STATE_STOP_COUNTING', + 3: 'CP_PERFMON_STATE_RESERVED_3', + 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +CP_PERFMON_STATE_DISABLE_AND_RESET = 0 +CP_PERFMON_STATE_START_COUNTING = 1 +CP_PERFMON_STATE_STOP_COUNTING = 2 +CP_PERFMON_STATE_RESERVED_3 = 3 +CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +CP_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_ENABLE_MODE' +CP_PERFMON_ENABLE_MODE__enumvalues = { + 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', + 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', +} +CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 +CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 +CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_PERFCOUNT_SEL' +CPG_PERFCOUNT_SEL__enumvalues = { + 0: 'CPG_PERF_SEL_ALWAYS_COUNT', + 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 2: 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR', + 3: 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL', + 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', + 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', + 8: 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 30: 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS', + 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 34: 'CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT', + 35: 'CPG_PERF_SEL_MIU_READ_REQUEST_SENT', + 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 40: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU', + 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', +} +CPG_PERF_SEL_ALWAYS_COUNT = 0 +CPG_PERF_SEL_RBIU_FIFO_FULL = 1 +CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 2 +CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 3 +CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 +CPG_PERF_SEL_ME_PARSER_BUSY = 5 +CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 +CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 +CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 8 +CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 +CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 +CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 +CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 +CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 +CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 +CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 +CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 +CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 +CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 +CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 +CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 +CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 +CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 +CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 +CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 +CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 30 +CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 +CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 +CPG_PERF_SEL_REGISTER_CLK_VALID = 33 +CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 34 +CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 35 +CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 +CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 +CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 +CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 40 +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 +CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 +CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 +CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 +CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_PERFCOUNT_SEL' +CPF_PERFCOUNT_SEL__enumvalues = { + 0: 'CPF_PERF_SEL_ALWAYS_COUNT', + 1: 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE', + 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE', + 8: 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS', + 9: 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR', + 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 15: 'CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND', + 16: 'CPF_PERF_SEL_MIU_READ_REQUEST_SEND', + 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 19: 'CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 20: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', +} +CPF_PERF_SEL_ALWAYS_COUNT = 0 +CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 1 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 +CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 7 +CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 8 +CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 9 +CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 +CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 +CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 +CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 +CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 +CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 15 +CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 16 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 +CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 19 +CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 20 +CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPC_PERFCOUNT_SEL' +CPC_PERFCOUNT_SEL__enumvalues = { + 0: 'CPC_PERF_SEL_ALWAYS_COUNT', + 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 3: 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE', + 4: 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE', + 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ', + 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE', + 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ', + 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE', + 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', +} +CPC_PERF_SEL_ALWAYS_COUNT = 0 +CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 +CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 +CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 3 +CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 4 +CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 9 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 10 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 +CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 17 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 18 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 +CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 +CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 +CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ALPHA_TAG_RAM_SEL' +CP_ALPHA_TAG_RAM_SEL__enumvalues = { + 0: 'CPG_TAG_RAM', + 1: 'CPC_TAG_RAM', + 2: 'CPF_TAG_RAM', + 3: 'RSV_TAG_RAM', +} +CPG_TAG_RAM = 0 +CPC_TAG_RAM = 1 +CPF_TAG_RAM = 2 +RSV_TAG_RAM = 3 +CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SX_BLEND_OPT' +SX_BLEND_OPT__enumvalues = { + 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', +} +BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 +BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 +BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 +BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 +BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 +BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 +BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 +BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 +SX_BLEND_OPT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_OPT_COMB_FCN' +SX_OPT_COMB_FCN__enumvalues = { + 0: 'OPT_COMB_NONE', + 1: 'OPT_COMB_ADD', + 2: 'OPT_COMB_SUBTRACT', + 3: 'OPT_COMB_MIN', + 4: 'OPT_COMB_MAX', + 5: 'OPT_COMB_REVSUBTRACT', + 6: 'OPT_COMB_BLEND_DISABLED', + 7: 'OPT_COMB_SAFE_ADD', +} +OPT_COMB_NONE = 0 +OPT_COMB_ADD = 1 +OPT_COMB_SUBTRACT = 2 +OPT_COMB_MIN = 3 +OPT_COMB_MAX = 4 +OPT_COMB_REVSUBTRACT = 5 +OPT_COMB_BLEND_DISABLED = 6 +OPT_COMB_SAFE_ADD = 7 +SX_OPT_COMB_FCN = ctypes.c_uint32 # enum + +# values for enumeration 'SX_DOWNCONVERT_FORMAT' +SX_DOWNCONVERT_FORMAT__enumvalues = { + 0: 'SX_RT_EXPORT_NO_CONVERSION', + 1: 'SX_RT_EXPORT_32_R', + 2: 'SX_RT_EXPORT_32_A', + 3: 'SX_RT_EXPORT_10_11_11', + 4: 'SX_RT_EXPORT_2_10_10_10', + 5: 'SX_RT_EXPORT_8_8_8_8', + 6: 'SX_RT_EXPORT_5_6_5', + 7: 'SX_RT_EXPORT_1_5_5_5', + 8: 'SX_RT_EXPORT_4_4_4_4', + 9: 'SX_RT_EXPORT_16_16_GR', + 10: 'SX_RT_EXPORT_16_16_AR', +} +SX_RT_EXPORT_NO_CONVERSION = 0 +SX_RT_EXPORT_32_R = 1 +SX_RT_EXPORT_32_A = 2 +SX_RT_EXPORT_10_11_11 = 3 +SX_RT_EXPORT_2_10_10_10 = 4 +SX_RT_EXPORT_8_8_8_8 = 5 +SX_RT_EXPORT_5_6_5 = 6 +SX_RT_EXPORT_1_5_5_5 = 7 +SX_RT_EXPORT_4_4_4_4 = 8 +SX_RT_EXPORT_16_16_GR = 9 +SX_RT_EXPORT_16_16_AR = 10 +SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_PERFCOUNTER_VALS' +SX_PERFCOUNTER_VALS__enumvalues = { + 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', + 1: 'SX_PERF_SEL_PA_REQ', + 2: 'SX_PERF_SEL_PA_POS', + 3: 'SX_PERF_SEL_CLOCK', + 4: 'SX_PERF_SEL_GATE_EN1', + 5: 'SX_PERF_SEL_GATE_EN2', + 6: 'SX_PERF_SEL_GATE_EN3', + 7: 'SX_PERF_SEL_GATE_EN4', + 8: 'SX_PERF_SEL_SH_POS_STARVE', + 9: 'SX_PERF_SEL_SH_COLOR_STARVE', + 10: 'SX_PERF_SEL_SH_POS_STALL', + 11: 'SX_PERF_SEL_SH_COLOR_STALL', + 12: 'SX_PERF_SEL_DB0_PIXELS', + 13: 'SX_PERF_SEL_DB0_HALF_QUADS', + 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', + 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', + 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', + 17: 'SX_PERF_SEL_DB1_PIXELS', + 18: 'SX_PERF_SEL_DB1_HALF_QUADS', + 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', + 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', + 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', + 22: 'SX_PERF_SEL_DB2_PIXELS', + 23: 'SX_PERF_SEL_DB2_HALF_QUADS', + 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', + 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', + 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', + 27: 'SX_PERF_SEL_DB3_PIXELS', + 28: 'SX_PERF_SEL_DB3_HALF_QUADS', + 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', + 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', + 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', + 32: 'SX_PERF_SEL_COL_BUSY', + 33: 'SX_PERF_SEL_POS_BUSY', + 34: 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', + 35: 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS', + 36: 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST', + 37: 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC', + 38: 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS', + 39: 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS', + 40: 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS', + 41: 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST', + 42: 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC', + 43: 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS', + 44: 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS', + 45: 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS', + 46: 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST', + 47: 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC', + 48: 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS', + 49: 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS', + 50: 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS', + 51: 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST', + 52: 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC', + 53: 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS', + 54: 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS', + 55: 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS', + 56: 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST', + 57: 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC', + 58: 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS', + 59: 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS', + 60: 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS', + 61: 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST', + 62: 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC', + 63: 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS', + 64: 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS', + 65: 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS', + 66: 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST', + 67: 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC', + 68: 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS', + 69: 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS', + 70: 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS', + 71: 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST', + 72: 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC', + 73: 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', + 74: 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS', + 75: 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', + 76: 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS', + 77: 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST', + 78: 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC', + 79: 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS', + 80: 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS', + 81: 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS', + 82: 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST', + 83: 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC', + 84: 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS', + 85: 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS', + 86: 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS', + 87: 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST', + 88: 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC', + 89: 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS', + 90: 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS', + 91: 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS', + 92: 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST', + 93: 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC', + 94: 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS', + 95: 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS', + 96: 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS', + 97: 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST', + 98: 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC', + 99: 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS', + 100: 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS', + 101: 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS', + 102: 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST', + 103: 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC', + 104: 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS', + 105: 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS', + 106: 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS', + 107: 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST', + 108: 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC', + 109: 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS', + 110: 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS', + 111: 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS', + 112: 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST', + 113: 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC', + 114: 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', + 115: 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS', + 116: 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', + 117: 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS', + 118: 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST', + 119: 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC', + 120: 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS', + 121: 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS', + 122: 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS', + 123: 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST', + 124: 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC', + 125: 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS', + 126: 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS', + 127: 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS', + 128: 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST', + 129: 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC', + 130: 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS', + 131: 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS', + 132: 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS', + 133: 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST', + 134: 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC', + 135: 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS', + 136: 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS', + 137: 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS', + 138: 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST', + 139: 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC', + 140: 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS', + 141: 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS', + 142: 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS', + 143: 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST', + 144: 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC', + 145: 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS', + 146: 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS', + 147: 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS', + 148: 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST', + 149: 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC', + 150: 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS', + 151: 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS', + 152: 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS', + 153: 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST', + 154: 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC', + 155: 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', + 156: 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS', + 157: 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', + 158: 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS', + 159: 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST', + 160: 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC', + 161: 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS', + 162: 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS', + 163: 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS', + 164: 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST', + 165: 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC', + 166: 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS', + 167: 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS', + 168: 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS', + 169: 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST', + 170: 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC', + 171: 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS', + 172: 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS', + 173: 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS', + 174: 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST', + 175: 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC', + 176: 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS', + 177: 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS', + 178: 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS', + 179: 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST', + 180: 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC', + 181: 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS', + 182: 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS', + 183: 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS', + 184: 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST', + 185: 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC', + 186: 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS', + 187: 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS', + 188: 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS', + 189: 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST', + 190: 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC', + 191: 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS', + 192: 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS', + 193: 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS', + 194: 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST', + 195: 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC', + 196: 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', + 197: 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS', +} +SX_PERF_SEL_PA_IDLE_CYCLES = 0 +SX_PERF_SEL_PA_REQ = 1 +SX_PERF_SEL_PA_POS = 2 +SX_PERF_SEL_CLOCK = 3 +SX_PERF_SEL_GATE_EN1 = 4 +SX_PERF_SEL_GATE_EN2 = 5 +SX_PERF_SEL_GATE_EN3 = 6 +SX_PERF_SEL_GATE_EN4 = 7 +SX_PERF_SEL_SH_POS_STARVE = 8 +SX_PERF_SEL_SH_COLOR_STARVE = 9 +SX_PERF_SEL_SH_POS_STALL = 10 +SX_PERF_SEL_SH_COLOR_STALL = 11 +SX_PERF_SEL_DB0_PIXELS = 12 +SX_PERF_SEL_DB0_HALF_QUADS = 13 +SX_PERF_SEL_DB0_PIXEL_STALL = 14 +SX_PERF_SEL_DB0_PIXEL_IDLE = 15 +SX_PERF_SEL_DB0_PRED_PIXELS = 16 +SX_PERF_SEL_DB1_PIXELS = 17 +SX_PERF_SEL_DB1_HALF_QUADS = 18 +SX_PERF_SEL_DB1_PIXEL_STALL = 19 +SX_PERF_SEL_DB1_PIXEL_IDLE = 20 +SX_PERF_SEL_DB1_PRED_PIXELS = 21 +SX_PERF_SEL_DB2_PIXELS = 22 +SX_PERF_SEL_DB2_HALF_QUADS = 23 +SX_PERF_SEL_DB2_PIXEL_STALL = 24 +SX_PERF_SEL_DB2_PIXEL_IDLE = 25 +SX_PERF_SEL_DB2_PRED_PIXELS = 26 +SX_PERF_SEL_DB3_PIXELS = 27 +SX_PERF_SEL_DB3_HALF_QUADS = 28 +SX_PERF_SEL_DB3_PIXEL_STALL = 29 +SX_PERF_SEL_DB3_PIXEL_IDLE = 30 +SX_PERF_SEL_DB3_PRED_PIXELS = 31 +SX_PERF_SEL_COL_BUSY = 32 +SX_PERF_SEL_POS_BUSY = 33 +SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 34 +SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 35 +SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 36 +SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 37 +SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 38 +SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 39 +SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 40 +SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 41 +SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 42 +SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 43 +SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 44 +SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 45 +SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 46 +SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 47 +SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 48 +SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 49 +SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 50 +SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 51 +SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 52 +SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 53 +SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 54 +SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 55 +SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 56 +SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 57 +SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 58 +SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 59 +SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 60 +SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 61 +SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 62 +SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 63 +SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 64 +SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 65 +SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 66 +SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 67 +SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 68 +SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 69 +SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 70 +SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 71 +SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 72 +SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 73 +SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 74 +SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 75 +SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 76 +SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 77 +SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 78 +SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 79 +SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 80 +SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 81 +SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 82 +SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 83 +SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 84 +SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 85 +SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 86 +SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 87 +SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 88 +SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 89 +SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 90 +SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 91 +SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 92 +SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 93 +SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 94 +SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 95 +SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 96 +SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 97 +SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 98 +SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 99 +SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 100 +SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 101 +SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 102 +SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 103 +SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 104 +SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 105 +SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 106 +SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 107 +SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 108 +SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 109 +SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 110 +SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 111 +SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 112 +SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 113 +SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 114 +SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 115 +SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 116 +SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 117 +SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 118 +SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 119 +SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 120 +SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 121 +SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 122 +SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 123 +SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 124 +SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 125 +SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 126 +SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 127 +SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 128 +SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 129 +SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 130 +SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 131 +SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 132 +SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 133 +SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 134 +SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 135 +SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 136 +SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 137 +SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 138 +SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 139 +SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 140 +SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 141 +SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 142 +SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 143 +SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 144 +SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 145 +SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 146 +SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 147 +SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 148 +SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 149 +SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 150 +SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 151 +SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 152 +SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 153 +SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 154 +SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 155 +SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 156 +SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 157 +SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 158 +SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 159 +SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 160 +SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 161 +SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 162 +SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 163 +SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 164 +SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 165 +SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 166 +SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 167 +SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 168 +SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 169 +SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 170 +SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 171 +SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 172 +SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 173 +SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 174 +SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 175 +SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 176 +SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 177 +SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 178 +SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 179 +SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 180 +SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 181 +SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 182 +SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 183 +SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 184 +SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 185 +SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 186 +SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 187 +SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 188 +SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 189 +SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 190 +SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 191 +SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 192 +SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 193 +SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 194 +SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 195 +SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 196 +SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 197 +SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum + +# values for enumeration 'ForceControl' +ForceControl__enumvalues = { + 0: 'FORCE_OFF', + 1: 'FORCE_ENABLE', + 2: 'FORCE_DISABLE', + 3: 'FORCE_RESERVED', +} +FORCE_OFF = 0 +FORCE_ENABLE = 1 +FORCE_DISABLE = 2 +FORCE_RESERVED = 3 +ForceControl = ctypes.c_uint32 # enum + +# values for enumeration 'ZSamplePosition' +ZSamplePosition__enumvalues = { + 0: 'Z_SAMPLE_CENTER', + 1: 'Z_SAMPLE_CENTROID', +} +Z_SAMPLE_CENTER = 0 +Z_SAMPLE_CENTROID = 1 +ZSamplePosition = ctypes.c_uint32 # enum + +# values for enumeration 'ZOrder' +ZOrder__enumvalues = { + 0: 'LATE_Z', + 1: 'EARLY_Z_THEN_LATE_Z', + 2: 'RE_Z', + 3: 'EARLY_Z_THEN_RE_Z', +} +LATE_Z = 0 +EARLY_Z_THEN_LATE_Z = 1 +RE_Z = 2 +EARLY_Z_THEN_RE_Z = 3 +ZOrder = ctypes.c_uint32 # enum + +# values for enumeration 'ZpassControl' +ZpassControl__enumvalues = { + 0: 'ZPASS_DISABLE', + 1: 'ZPASS_SAMPLES', + 2: 'ZPASS_PIXELS', +} +ZPASS_DISABLE = 0 +ZPASS_SAMPLES = 1 +ZPASS_PIXELS = 2 +ZpassControl = ctypes.c_uint32 # enum + +# values for enumeration 'ZModeForce' +ZModeForce__enumvalues = { + 0: 'NO_FORCE', + 1: 'FORCE_EARLY_Z', + 2: 'FORCE_LATE_Z', + 3: 'FORCE_RE_Z', +} +NO_FORCE = 0 +FORCE_EARLY_Z = 1 +FORCE_LATE_Z = 2 +FORCE_RE_Z = 3 +ZModeForce = ctypes.c_uint32 # enum + +# values for enumeration 'ZLimitSumm' +ZLimitSumm__enumvalues = { + 0: 'FORCE_SUMM_OFF', + 1: 'FORCE_SUMM_MINZ', + 2: 'FORCE_SUMM_MAXZ', + 3: 'FORCE_SUMM_BOTH', +} +FORCE_SUMM_OFF = 0 +FORCE_SUMM_MINZ = 1 +FORCE_SUMM_MAXZ = 2 +FORCE_SUMM_BOTH = 3 +ZLimitSumm = ctypes.c_uint32 # enum + +# values for enumeration 'CompareFrag' +CompareFrag__enumvalues = { + 0: 'FRAG_NEVER', + 1: 'FRAG_LESS', + 2: 'FRAG_EQUAL', + 3: 'FRAG_LEQUAL', + 4: 'FRAG_GREATER', + 5: 'FRAG_NOTEQUAL', + 6: 'FRAG_GEQUAL', + 7: 'FRAG_ALWAYS', +} +FRAG_NEVER = 0 +FRAG_LESS = 1 +FRAG_EQUAL = 2 +FRAG_LEQUAL = 3 +FRAG_GREATER = 4 +FRAG_NOTEQUAL = 5 +FRAG_GEQUAL = 6 +FRAG_ALWAYS = 7 +CompareFrag = ctypes.c_uint32 # enum + +# values for enumeration 'StencilOp' +StencilOp__enumvalues = { + 0: 'STENCIL_KEEP', + 1: 'STENCIL_ZERO', + 2: 'STENCIL_ONES', + 3: 'STENCIL_REPLACE_TEST', + 4: 'STENCIL_REPLACE_OP', + 5: 'STENCIL_ADD_CLAMP', + 6: 'STENCIL_SUB_CLAMP', + 7: 'STENCIL_INVERT', + 8: 'STENCIL_ADD_WRAP', + 9: 'STENCIL_SUB_WRAP', + 10: 'STENCIL_AND', + 11: 'STENCIL_OR', + 12: 'STENCIL_XOR', + 13: 'STENCIL_NAND', + 14: 'STENCIL_NOR', + 15: 'STENCIL_XNOR', +} +STENCIL_KEEP = 0 +STENCIL_ZERO = 1 +STENCIL_ONES = 2 +STENCIL_REPLACE_TEST = 3 +STENCIL_REPLACE_OP = 4 +STENCIL_ADD_CLAMP = 5 +STENCIL_SUB_CLAMP = 6 +STENCIL_INVERT = 7 +STENCIL_ADD_WRAP = 8 +STENCIL_SUB_WRAP = 9 +STENCIL_AND = 10 +STENCIL_OR = 11 +STENCIL_XOR = 12 +STENCIL_NAND = 13 +STENCIL_NOR = 14 +STENCIL_XNOR = 15 +StencilOp = ctypes.c_uint32 # enum + +# values for enumeration 'ConservativeZExport' +ConservativeZExport__enumvalues = { + 0: 'EXPORT_ANY_Z', + 1: 'EXPORT_LESS_THAN_Z', + 2: 'EXPORT_GREATER_THAN_Z', + 3: 'EXPORT_RESERVED', +} +EXPORT_ANY_Z = 0 +EXPORT_LESS_THAN_Z = 1 +EXPORT_GREATER_THAN_Z = 2 +EXPORT_RESERVED = 3 +ConservativeZExport = ctypes.c_uint32 # enum + +# values for enumeration 'DbPSLControl' +DbPSLControl__enumvalues = { + 0: 'PSLC_AUTO', + 1: 'PSLC_ON_HANG_ONLY', + 2: 'PSLC_ASAP', + 3: 'PSLC_COUNTDOWN', +} +PSLC_AUTO = 0 +PSLC_ON_HANG_ONLY = 1 +PSLC_ASAP = 2 +PSLC_COUNTDOWN = 3 +DbPSLControl = ctypes.c_uint32 # enum + +# values for enumeration 'DbPRTFaultBehavior' +DbPRTFaultBehavior__enumvalues = { + 0: 'FAULT_ZERO', + 1: 'FAULT_ONE', + 2: 'FAULT_FAIL', + 3: 'FAULT_PASS', +} +FAULT_ZERO = 0 +FAULT_ONE = 1 +FAULT_FAIL = 2 +FAULT_PASS = 3 +DbPRTFaultBehavior = ctypes.c_uint32 # enum + +# values for enumeration 'PerfCounter_Vals' +PerfCounter_Vals__enumvalues = { + 0: 'DB_PERF_SEL_SC_DB_tile_sends', + 1: 'DB_PERF_SEL_SC_DB_tile_busy', + 2: 'DB_PERF_SEL_SC_DB_tile_stalls', + 3: 'DB_PERF_SEL_SC_DB_tile_events', + 4: 'DB_PERF_SEL_SC_DB_tile_tiles', + 5: 'DB_PERF_SEL_SC_DB_tile_covered', + 6: 'DB_PERF_SEL_hiz_tc_read_starved', + 7: 'DB_PERF_SEL_hiz_tc_write_stall', + 8: 'DB_PERF_SEL_hiz_qtiles_culled', + 9: 'DB_PERF_SEL_his_qtiles_culled', + 10: 'DB_PERF_SEL_DB_SC_tile_sends', + 11: 'DB_PERF_SEL_DB_SC_tile_busy', + 12: 'DB_PERF_SEL_DB_SC_tile_stalls', + 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 14: 'DB_PERF_SEL_DB_SC_tile_tiles', + 15: 'DB_PERF_SEL_DB_SC_tile_culled', + 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', + 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 23: 'DB_PERF_SEL_SC_DB_quad_sends', + 24: 'DB_PERF_SEL_SC_DB_quad_busy', + 25: 'DB_PERF_SEL_SC_DB_quad_squads', + 26: 'DB_PERF_SEL_SC_DB_quad_tiles', + 27: 'DB_PERF_SEL_SC_DB_quad_pixels', + 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 29: 'DB_PERF_SEL_DB_SC_quad_sends', + 30: 'DB_PERF_SEL_DB_SC_quad_busy', + 31: 'DB_PERF_SEL_DB_SC_quad_stalls', + 32: 'DB_PERF_SEL_DB_SC_quad_tiles', + 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', + 34: 'DB_PERF_SEL_DB_CB_tile_sends', + 35: 'DB_PERF_SEL_DB_CB_tile_busy', + 36: 'DB_PERF_SEL_DB_CB_tile_stalls', + 37: 'DB_PERF_SEL_SX_DB_quad_sends', + 38: 'DB_PERF_SEL_SX_DB_quad_busy', + 39: 'DB_PERF_SEL_SX_DB_quad_stalls', + 40: 'DB_PERF_SEL_SX_DB_quad_quads', + 41: 'DB_PERF_SEL_SX_DB_quad_pixels', + 42: 'DB_PERF_SEL_SX_DB_quad_exports', + 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', + 44: 'DB_PERF_SEL_DB_CB_lquad_sends', + 45: 'DB_PERF_SEL_DB_CB_lquad_busy', + 46: 'DB_PERF_SEL_DB_CB_lquad_stalls', + 47: 'DB_PERF_SEL_DB_CB_lquad_quads', + 48: 'DB_PERF_SEL_tile_rd_sends', + 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 50: 'DB_PERF_SEL_quad_rd_sends', + 51: 'DB_PERF_SEL_quad_rd_busy', + 52: 'DB_PERF_SEL_quad_rd_mi_stall', + 53: 'DB_PERF_SEL_quad_rd_rw_collision', + 54: 'DB_PERF_SEL_quad_rd_tag_stall', + 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', + 56: 'DB_PERF_SEL_quad_rd_panic', + 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 58: 'DB_PERF_SEL_quad_rdret_sends', + 59: 'DB_PERF_SEL_quad_rdret_busy', + 60: 'DB_PERF_SEL_tile_wr_sends', + 61: 'DB_PERF_SEL_tile_wr_acks', + 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 63: 'DB_PERF_SEL_quad_wr_sends', + 64: 'DB_PERF_SEL_quad_wr_busy', + 65: 'DB_PERF_SEL_quad_wr_mi_stall', + 66: 'DB_PERF_SEL_quad_wr_coherency_stall', + 67: 'DB_PERF_SEL_quad_wr_acks', + 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 69: 'DB_PERF_SEL_Tile_Cache_misses', + 70: 'DB_PERF_SEL_Tile_Cache_hits', + 71: 'DB_PERF_SEL_Tile_Cache_flushes', + 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', + 73: 'DB_PERF_SEL_Tile_Cache_starves', + 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 75: 'DB_PERF_SEL_tcp_dispatcher_reads', + 76: 'DB_PERF_SEL_tcp_prefetcher_reads', + 77: 'DB_PERF_SEL_tcp_preloader_reads', + 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', + 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', + 80: 'DB_PERF_SEL_tcp_preloader_flushes', + 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', + 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 95: 'DB_PERF_SEL_Stencil_Cache_misses', + 96: 'DB_PERF_SEL_Stencil_Cache_hits', + 97: 'DB_PERF_SEL_Stencil_Cache_flushes', + 98: 'DB_PERF_SEL_Stencil_Cache_starves', + 99: 'DB_PERF_SEL_Stencil_Cache_frees', + 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', + 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', + 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', + 108: 'DB_PERF_SEL_Z_Cache_frees', + 109: 'DB_PERF_SEL_Plane_Cache_misses', + 110: 'DB_PERF_SEL_Plane_Cache_hits', + 111: 'DB_PERF_SEL_Plane_Cache_flushes', + 112: 'DB_PERF_SEL_Plane_Cache_starves', + 113: 'DB_PERF_SEL_Plane_Cache_frees', + 114: 'DB_PERF_SEL_flush_expanded_stencil', + 115: 'DB_PERF_SEL_flush_compressed_stencil', + 116: 'DB_PERF_SEL_flush_single_stencil', + 117: 'DB_PERF_SEL_planes_flushed', + 118: 'DB_PERF_SEL_flush_1plane', + 119: 'DB_PERF_SEL_flush_2plane', + 120: 'DB_PERF_SEL_flush_3plane', + 121: 'DB_PERF_SEL_flush_4plane', + 122: 'DB_PERF_SEL_flush_5plane', + 123: 'DB_PERF_SEL_flush_6plane', + 124: 'DB_PERF_SEL_flush_7plane', + 125: 'DB_PERF_SEL_flush_8plane', + 126: 'DB_PERF_SEL_flush_9plane', + 127: 'DB_PERF_SEL_flush_10plane', + 128: 'DB_PERF_SEL_flush_11plane', + 129: 'DB_PERF_SEL_flush_12plane', + 130: 'DB_PERF_SEL_flush_13plane', + 131: 'DB_PERF_SEL_flush_14plane', + 132: 'DB_PERF_SEL_flush_15plane', + 133: 'DB_PERF_SEL_flush_16plane', + 134: 'DB_PERF_SEL_flush_expanded_z', + 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 137: 'DB_PERF_SEL_dk_tile_sends', + 138: 'DB_PERF_SEL_dk_tile_busy', + 139: 'DB_PERF_SEL_dk_tile_quad_starves', + 140: 'DB_PERF_SEL_dk_tile_stalls', + 141: 'DB_PERF_SEL_dk_squad_sends', + 142: 'DB_PERF_SEL_dk_squad_busy', + 143: 'DB_PERF_SEL_dk_squad_stalls', + 144: 'DB_PERF_SEL_Op_Pipe_Busy', + 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 146: 'DB_PERF_SEL_qc_busy', + 147: 'DB_PERF_SEL_qc_xfc', + 148: 'DB_PERF_SEL_qc_conflicts', + 149: 'DB_PERF_SEL_qc_full_stall', + 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', + 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', + 153: 'DB_PERF_SEL_tl_busy', + 154: 'DB_PERF_SEL_tl_dtc_read_starved', + 155: 'DB_PERF_SEL_tl_z_fetch_stall', + 156: 'DB_PERF_SEL_tl_stencil_stall', + 157: 'DB_PERF_SEL_tl_z_decompress_stall', + 158: 'DB_PERF_SEL_tl_stencil_locked_stall', + 159: 'DB_PERF_SEL_tl_events', + 160: 'DB_PERF_SEL_tl_summarize_squads', + 161: 'DB_PERF_SEL_tl_flush_expand_squads', + 162: 'DB_PERF_SEL_tl_expand_squads', + 163: 'DB_PERF_SEL_tl_preZ_squads', + 164: 'DB_PERF_SEL_tl_postZ_squads', + 165: 'DB_PERF_SEL_tl_preZ_noop_squads', + 166: 'DB_PERF_SEL_tl_postZ_noop_squads', + 167: 'DB_PERF_SEL_tl_tile_ops', + 168: 'DB_PERF_SEL_tl_in_xfc', + 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 170: 'DB_PERF_SEL_tl_in_fast_z_stall', + 171: 'DB_PERF_SEL_tl_out_xfc', + 172: 'DB_PERF_SEL_tl_out_squads', + 173: 'DB_PERF_SEL_zf_plane_multicycle', + 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', + 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', + 180: 'DB_PERF_SEL_ts_tc_update_stall', + 181: 'DB_PERF_SEL_sc_kick_start', + 182: 'DB_PERF_SEL_sc_kick_end', + 183: 'DB_PERF_SEL_clock_reg_active', + 184: 'DB_PERF_SEL_clock_main_active', + 185: 'DB_PERF_SEL_clock_mem_export_active', + 186: 'DB_PERF_SEL_esr_ps_out_busy', + 187: 'DB_PERF_SEL_esr_ps_lqf_busy', + 188: 'DB_PERF_SEL_esr_ps_lqf_stall', + 189: 'DB_PERF_SEL_etr_out_send', + 190: 'DB_PERF_SEL_etr_out_busy', + 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 192: 'DB_PERF_SEL_etr_out_cb_tile_stall', + 193: 'DB_PERF_SEL_etr_out_esr_stall', + 194: 'DB_PERF_SEL_esr_ps_sqq_busy', + 195: 'DB_PERF_SEL_esr_ps_sqq_stall', + 196: 'DB_PERF_SEL_esr_eot_fwd_busy', + 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 198: 'DB_PERF_SEL_esr_eot_fwd_forward', + 199: 'DB_PERF_SEL_esr_sqq_zi_busy', + 200: 'DB_PERF_SEL_esr_sqq_zi_stall', + 201: 'DB_PERF_SEL_postzl_sq_pt_busy', + 202: 'DB_PERF_SEL_postzl_sq_pt_stall', + 203: 'DB_PERF_SEL_postzl_se_busy', + 204: 'DB_PERF_SEL_postzl_se_stall', + 205: 'DB_PERF_SEL_postzl_partial_launch', + 206: 'DB_PERF_SEL_postzl_full_launch', + 207: 'DB_PERF_SEL_postzl_partial_waiting', + 208: 'DB_PERF_SEL_postzl_tile_mem_stall', + 209: 'DB_PERF_SEL_postzl_tile_init_stall', + 210: 'DB_PEFF_SEL_prezl_tile_mem_stall', + 211: 'DB_PERF_SEL_prezl_tile_init_stall', + 212: 'DB_PERF_SEL_dtt_sm_clash_stall', + 213: 'DB_PERF_SEL_dtt_sm_slot_stall', + 214: 'DB_PERF_SEL_dtt_sm_miss_stall', + 215: 'DB_PERF_SEL_mi_rdreq_busy', + 216: 'DB_PERF_SEL_mi_rdreq_stall', + 217: 'DB_PERF_SEL_mi_wrreq_busy', + 218: 'DB_PERF_SEL_mi_wrreq_stall', + 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 220: 'DB_PERF_SEL_dkg_tile_rate_tile', + 221: 'DB_PERF_SEL_prezl_src_in_sends', + 222: 'DB_PERF_SEL_prezl_src_in_stall', + 223: 'DB_PERF_SEL_prezl_src_in_squads', + 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', + 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 227: 'DB_PERF_SEL_prezl_src_out_stall', + 228: 'DB_PERF_SEL_postzl_src_in_sends', + 229: 'DB_PERF_SEL_postzl_src_in_stall', + 230: 'DB_PERF_SEL_postzl_src_in_squads', + 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', + 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 234: 'DB_PERF_SEL_postzl_src_out_stall', + 235: 'DB_PERF_SEL_esr_ps_src_in_sends', + 236: 'DB_PERF_SEL_esr_ps_src_in_stall', + 237: 'DB_PERF_SEL_esr_ps_src_in_squads', + 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 242: 'DB_PERF_SEL_esr_ps_src_out_stall', + 243: 'DB_PERF_SEL_depth_bounds_qtiles_culled', + 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 246: 'DB_PERF_SEL_flush_compressed', + 247: 'DB_PERF_SEL_flush_plane_le4', + 248: 'DB_PERF_SEL_tiles_z_fully_summarized', + 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', + 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', + 256: 'DB_PERF_SEL_di_dt_stall', + 257: 'DB_PERF_SEL_DB_SC_quad_double_quad', + 258: 'DB_PERF_SEL_SX_DB_quad_export_quads', + 259: 'DB_PERF_SEL_SX_DB_quad_double_format', + 260: 'DB_PERF_SEL_SX_DB_quad_fast_format', + 261: 'DB_PERF_SEL_SX_DB_quad_slow_format', + 262: 'DB_PERF_SEL_DB_CB_lquad_export_quads', + 263: 'DB_PERF_SEL_DB_CB_lquad_double_format', + 264: 'DB_PERF_SEL_DB_CB_lquad_fast_format', + 265: 'DB_PERF_SEL_DB_CB_lquad_slow_format', + 266: 'DB_PERF_SEL_CB_DB_rdreq_sends', + 267: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 268: 'DB_PERF_SEL_CB_DB_wrreq_sends', + 269: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 270: 'DB_PERF_SEL_DB_CB_rdret_ack', + 271: 'DB_PERF_SEL_DB_CB_rdret_nack', + 272: 'DB_PERF_SEL_DB_CB_wrret_ack', + 273: 'DB_PERF_SEL_DB_CB_wrret_nack', + 274: 'DB_PERF_SEL_DFSM_squads_in', + 275: 'DB_PERF_SEL_DFSM_full_cleared_squads_out', + 276: 'DB_PERF_SEL_DFSM_quads_in', + 277: 'DB_PERF_SEL_DFSM_fully_cleared_quads_out', + 278: 'DB_PERF_SEL_DFSM_lit_pixels_in', + 279: 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out', + 280: 'DB_PERF_SEL_DFSM_lit_samples_in', + 281: 'DB_PERF_SEL_DFSM_lit_samples_out', + 282: 'DB_PERF_SEL_DFSM_cycles_above_watermark', + 283: 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream', + 284: 'DB_PERF_SEL_DFSM_stalled_by_downstream', + 285: 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark', + 286: 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow', + 287: 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO', + 288: 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark', +} +DB_PERF_SEL_SC_DB_tile_sends = 0 +DB_PERF_SEL_SC_DB_tile_busy = 1 +DB_PERF_SEL_SC_DB_tile_stalls = 2 +DB_PERF_SEL_SC_DB_tile_events = 3 +DB_PERF_SEL_SC_DB_tile_tiles = 4 +DB_PERF_SEL_SC_DB_tile_covered = 5 +DB_PERF_SEL_hiz_tc_read_starved = 6 +DB_PERF_SEL_hiz_tc_write_stall = 7 +DB_PERF_SEL_hiz_qtiles_culled = 8 +DB_PERF_SEL_his_qtiles_culled = 9 +DB_PERF_SEL_DB_SC_tile_sends = 10 +DB_PERF_SEL_DB_SC_tile_busy = 11 +DB_PERF_SEL_DB_SC_tile_stalls = 12 +DB_PERF_SEL_DB_SC_tile_df_stalls = 13 +DB_PERF_SEL_DB_SC_tile_tiles = 14 +DB_PERF_SEL_DB_SC_tile_culled = 15 +DB_PERF_SEL_DB_SC_tile_hier_kill = 16 +DB_PERF_SEL_DB_SC_tile_fast_ops = 17 +DB_PERF_SEL_DB_SC_tile_no_ops = 18 +DB_PERF_SEL_DB_SC_tile_tile_rate = 19 +DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 +DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 +DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 +DB_PERF_SEL_SC_DB_quad_sends = 23 +DB_PERF_SEL_SC_DB_quad_busy = 24 +DB_PERF_SEL_SC_DB_quad_squads = 25 +DB_PERF_SEL_SC_DB_quad_tiles = 26 +DB_PERF_SEL_SC_DB_quad_pixels = 27 +DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 +DB_PERF_SEL_DB_SC_quad_sends = 29 +DB_PERF_SEL_DB_SC_quad_busy = 30 +DB_PERF_SEL_DB_SC_quad_stalls = 31 +DB_PERF_SEL_DB_SC_quad_tiles = 32 +DB_PERF_SEL_DB_SC_quad_lit_quad = 33 +DB_PERF_SEL_DB_CB_tile_sends = 34 +DB_PERF_SEL_DB_CB_tile_busy = 35 +DB_PERF_SEL_DB_CB_tile_stalls = 36 +DB_PERF_SEL_SX_DB_quad_sends = 37 +DB_PERF_SEL_SX_DB_quad_busy = 38 +DB_PERF_SEL_SX_DB_quad_stalls = 39 +DB_PERF_SEL_SX_DB_quad_quads = 40 +DB_PERF_SEL_SX_DB_quad_pixels = 41 +DB_PERF_SEL_SX_DB_quad_exports = 42 +DB_PERF_SEL_SH_quads_outstanding_sum = 43 +DB_PERF_SEL_DB_CB_lquad_sends = 44 +DB_PERF_SEL_DB_CB_lquad_busy = 45 +DB_PERF_SEL_DB_CB_lquad_stalls = 46 +DB_PERF_SEL_DB_CB_lquad_quads = 47 +DB_PERF_SEL_tile_rd_sends = 48 +DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 +DB_PERF_SEL_quad_rd_sends = 50 +DB_PERF_SEL_quad_rd_busy = 51 +DB_PERF_SEL_quad_rd_mi_stall = 52 +DB_PERF_SEL_quad_rd_rw_collision = 53 +DB_PERF_SEL_quad_rd_tag_stall = 54 +DB_PERF_SEL_quad_rd_32byte_reqs = 55 +DB_PERF_SEL_quad_rd_panic = 56 +DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 +DB_PERF_SEL_quad_rdret_sends = 58 +DB_PERF_SEL_quad_rdret_busy = 59 +DB_PERF_SEL_tile_wr_sends = 60 +DB_PERF_SEL_tile_wr_acks = 61 +DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 +DB_PERF_SEL_quad_wr_sends = 63 +DB_PERF_SEL_quad_wr_busy = 64 +DB_PERF_SEL_quad_wr_mi_stall = 65 +DB_PERF_SEL_quad_wr_coherency_stall = 66 +DB_PERF_SEL_quad_wr_acks = 67 +DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 +DB_PERF_SEL_Tile_Cache_misses = 69 +DB_PERF_SEL_Tile_Cache_hits = 70 +DB_PERF_SEL_Tile_Cache_flushes = 71 +DB_PERF_SEL_Tile_Cache_surface_stall = 72 +DB_PERF_SEL_Tile_Cache_starves = 73 +DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 +DB_PERF_SEL_tcp_dispatcher_reads = 75 +DB_PERF_SEL_tcp_prefetcher_reads = 76 +DB_PERF_SEL_tcp_preloader_reads = 77 +DB_PERF_SEL_tcp_dispatcher_flushes = 78 +DB_PERF_SEL_tcp_prefetcher_flushes = 79 +DB_PERF_SEL_tcp_preloader_flushes = 80 +DB_PERF_SEL_Depth_Tile_Cache_sends = 81 +DB_PERF_SEL_Depth_Tile_Cache_busy = 82 +DB_PERF_SEL_Depth_Tile_Cache_starves = 83 +DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 +DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 +DB_PERF_SEL_Depth_Tile_Cache_misses = 86 +DB_PERF_SEL_Depth_Tile_Cache_hits = 87 +DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 +DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 +DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 +DB_PERF_SEL_Depth_Tile_Cache_event = 91 +DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 +DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 +DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 +DB_PERF_SEL_Stencil_Cache_misses = 95 +DB_PERF_SEL_Stencil_Cache_hits = 96 +DB_PERF_SEL_Stencil_Cache_flushes = 97 +DB_PERF_SEL_Stencil_Cache_starves = 98 +DB_PERF_SEL_Stencil_Cache_frees = 99 +DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 +DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 +DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 +DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 +DB_PERF_SEL_Z_Cache_pmask_misses = 104 +DB_PERF_SEL_Z_Cache_pmask_hits = 105 +DB_PERF_SEL_Z_Cache_pmask_flushes = 106 +DB_PERF_SEL_Z_Cache_pmask_starves = 107 +DB_PERF_SEL_Z_Cache_frees = 108 +DB_PERF_SEL_Plane_Cache_misses = 109 +DB_PERF_SEL_Plane_Cache_hits = 110 +DB_PERF_SEL_Plane_Cache_flushes = 111 +DB_PERF_SEL_Plane_Cache_starves = 112 +DB_PERF_SEL_Plane_Cache_frees = 113 +DB_PERF_SEL_flush_expanded_stencil = 114 +DB_PERF_SEL_flush_compressed_stencil = 115 +DB_PERF_SEL_flush_single_stencil = 116 +DB_PERF_SEL_planes_flushed = 117 +DB_PERF_SEL_flush_1plane = 118 +DB_PERF_SEL_flush_2plane = 119 +DB_PERF_SEL_flush_3plane = 120 +DB_PERF_SEL_flush_4plane = 121 +DB_PERF_SEL_flush_5plane = 122 +DB_PERF_SEL_flush_6plane = 123 +DB_PERF_SEL_flush_7plane = 124 +DB_PERF_SEL_flush_8plane = 125 +DB_PERF_SEL_flush_9plane = 126 +DB_PERF_SEL_flush_10plane = 127 +DB_PERF_SEL_flush_11plane = 128 +DB_PERF_SEL_flush_12plane = 129 +DB_PERF_SEL_flush_13plane = 130 +DB_PERF_SEL_flush_14plane = 131 +DB_PERF_SEL_flush_15plane = 132 +DB_PERF_SEL_flush_16plane = 133 +DB_PERF_SEL_flush_expanded_z = 134 +DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 +DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 +DB_PERF_SEL_dk_tile_sends = 137 +DB_PERF_SEL_dk_tile_busy = 138 +DB_PERF_SEL_dk_tile_quad_starves = 139 +DB_PERF_SEL_dk_tile_stalls = 140 +DB_PERF_SEL_dk_squad_sends = 141 +DB_PERF_SEL_dk_squad_busy = 142 +DB_PERF_SEL_dk_squad_stalls = 143 +DB_PERF_SEL_Op_Pipe_Busy = 144 +DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 +DB_PERF_SEL_qc_busy = 146 +DB_PERF_SEL_qc_xfc = 147 +DB_PERF_SEL_qc_conflicts = 148 +DB_PERF_SEL_qc_full_stall = 149 +DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 +DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 +DB_PERF_SEL_tsc_insert_summarize_stall = 152 +DB_PERF_SEL_tl_busy = 153 +DB_PERF_SEL_tl_dtc_read_starved = 154 +DB_PERF_SEL_tl_z_fetch_stall = 155 +DB_PERF_SEL_tl_stencil_stall = 156 +DB_PERF_SEL_tl_z_decompress_stall = 157 +DB_PERF_SEL_tl_stencil_locked_stall = 158 +DB_PERF_SEL_tl_events = 159 +DB_PERF_SEL_tl_summarize_squads = 160 +DB_PERF_SEL_tl_flush_expand_squads = 161 +DB_PERF_SEL_tl_expand_squads = 162 +DB_PERF_SEL_tl_preZ_squads = 163 +DB_PERF_SEL_tl_postZ_squads = 164 +DB_PERF_SEL_tl_preZ_noop_squads = 165 +DB_PERF_SEL_tl_postZ_noop_squads = 166 +DB_PERF_SEL_tl_tile_ops = 167 +DB_PERF_SEL_tl_in_xfc = 168 +DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 +DB_PERF_SEL_tl_in_fast_z_stall = 170 +DB_PERF_SEL_tl_out_xfc = 171 +DB_PERF_SEL_tl_out_squads = 172 +DB_PERF_SEL_zf_plane_multicycle = 173 +DB_PERF_SEL_PostZ_Samples_passing_Z = 174 +DB_PERF_SEL_PostZ_Samples_failing_Z = 175 +DB_PERF_SEL_PostZ_Samples_failing_S = 176 +DB_PERF_SEL_PreZ_Samples_passing_Z = 177 +DB_PERF_SEL_PreZ_Samples_failing_Z = 178 +DB_PERF_SEL_PreZ_Samples_failing_S = 179 +DB_PERF_SEL_ts_tc_update_stall = 180 +DB_PERF_SEL_sc_kick_start = 181 +DB_PERF_SEL_sc_kick_end = 182 +DB_PERF_SEL_clock_reg_active = 183 +DB_PERF_SEL_clock_main_active = 184 +DB_PERF_SEL_clock_mem_export_active = 185 +DB_PERF_SEL_esr_ps_out_busy = 186 +DB_PERF_SEL_esr_ps_lqf_busy = 187 +DB_PERF_SEL_esr_ps_lqf_stall = 188 +DB_PERF_SEL_etr_out_send = 189 +DB_PERF_SEL_etr_out_busy = 190 +DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 +DB_PERF_SEL_etr_out_cb_tile_stall = 192 +DB_PERF_SEL_etr_out_esr_stall = 193 +DB_PERF_SEL_esr_ps_sqq_busy = 194 +DB_PERF_SEL_esr_ps_sqq_stall = 195 +DB_PERF_SEL_esr_eot_fwd_busy = 196 +DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 +DB_PERF_SEL_esr_eot_fwd_forward = 198 +DB_PERF_SEL_esr_sqq_zi_busy = 199 +DB_PERF_SEL_esr_sqq_zi_stall = 200 +DB_PERF_SEL_postzl_sq_pt_busy = 201 +DB_PERF_SEL_postzl_sq_pt_stall = 202 +DB_PERF_SEL_postzl_se_busy = 203 +DB_PERF_SEL_postzl_se_stall = 204 +DB_PERF_SEL_postzl_partial_launch = 205 +DB_PERF_SEL_postzl_full_launch = 206 +DB_PERF_SEL_postzl_partial_waiting = 207 +DB_PERF_SEL_postzl_tile_mem_stall = 208 +DB_PERF_SEL_postzl_tile_init_stall = 209 +DB_PEFF_SEL_prezl_tile_mem_stall = 210 +DB_PERF_SEL_prezl_tile_init_stall = 211 +DB_PERF_SEL_dtt_sm_clash_stall = 212 +DB_PERF_SEL_dtt_sm_slot_stall = 213 +DB_PERF_SEL_dtt_sm_miss_stall = 214 +DB_PERF_SEL_mi_rdreq_busy = 215 +DB_PERF_SEL_mi_rdreq_stall = 216 +DB_PERF_SEL_mi_wrreq_busy = 217 +DB_PERF_SEL_mi_wrreq_stall = 218 +DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 +DB_PERF_SEL_dkg_tile_rate_tile = 220 +DB_PERF_SEL_prezl_src_in_sends = 221 +DB_PERF_SEL_prezl_src_in_stall = 222 +DB_PERF_SEL_prezl_src_in_squads = 223 +DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 +DB_PERF_SEL_prezl_src_in_tile_rate = 225 +DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 +DB_PERF_SEL_prezl_src_out_stall = 227 +DB_PERF_SEL_postzl_src_in_sends = 228 +DB_PERF_SEL_postzl_src_in_stall = 229 +DB_PERF_SEL_postzl_src_in_squads = 230 +DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 +DB_PERF_SEL_postzl_src_in_tile_rate = 232 +DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 +DB_PERF_SEL_postzl_src_out_stall = 234 +DB_PERF_SEL_esr_ps_src_in_sends = 235 +DB_PERF_SEL_esr_ps_src_in_stall = 236 +DB_PERF_SEL_esr_ps_src_in_squads = 237 +DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 +DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 +DB_PERF_SEL_esr_ps_src_out_stall = 242 +DB_PERF_SEL_depth_bounds_qtiles_culled = 243 +DB_PERF_SEL_PreZ_Samples_failing_DB = 244 +DB_PERF_SEL_PostZ_Samples_failing_DB = 245 +DB_PERF_SEL_flush_compressed = 246 +DB_PERF_SEL_flush_plane_le4 = 247 +DB_PERF_SEL_tiles_z_fully_summarized = 248 +DB_PERF_SEL_tiles_stencil_fully_summarized = 249 +DB_PERF_SEL_tiles_z_clear_on_expclear = 250 +DB_PERF_SEL_tiles_s_clear_on_expclear = 251 +DB_PERF_SEL_tiles_decomp_on_expclear = 252 +DB_PERF_SEL_tiles_compressed_to_decompressed = 253 +DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 +DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 +DB_PERF_SEL_di_dt_stall = 256 +DB_PERF_SEL_DB_SC_quad_double_quad = 257 +DB_PERF_SEL_SX_DB_quad_export_quads = 258 +DB_PERF_SEL_SX_DB_quad_double_format = 259 +DB_PERF_SEL_SX_DB_quad_fast_format = 260 +DB_PERF_SEL_SX_DB_quad_slow_format = 261 +DB_PERF_SEL_DB_CB_lquad_export_quads = 262 +DB_PERF_SEL_DB_CB_lquad_double_format = 263 +DB_PERF_SEL_DB_CB_lquad_fast_format = 264 +DB_PERF_SEL_DB_CB_lquad_slow_format = 265 +DB_PERF_SEL_CB_DB_rdreq_sends = 266 +DB_PERF_SEL_CB_DB_rdreq_prt_sends = 267 +DB_PERF_SEL_CB_DB_wrreq_sends = 268 +DB_PERF_SEL_CB_DB_wrreq_prt_sends = 269 +DB_PERF_SEL_DB_CB_rdret_ack = 270 +DB_PERF_SEL_DB_CB_rdret_nack = 271 +DB_PERF_SEL_DB_CB_wrret_ack = 272 +DB_PERF_SEL_DB_CB_wrret_nack = 273 +DB_PERF_SEL_DFSM_squads_in = 274 +DB_PERF_SEL_DFSM_full_cleared_squads_out = 275 +DB_PERF_SEL_DFSM_quads_in = 276 +DB_PERF_SEL_DFSM_fully_cleared_quads_out = 277 +DB_PERF_SEL_DFSM_lit_pixels_in = 278 +DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 279 +DB_PERF_SEL_DFSM_lit_samples_in = 280 +DB_PERF_SEL_DFSM_lit_samples_out = 281 +DB_PERF_SEL_DFSM_cycles_above_watermark = 282 +DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 283 +DB_PERF_SEL_DFSM_stalled_by_downstream = 284 +DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 285 +DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 286 +DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 287 +DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 288 +PerfCounter_Vals = ctypes.c_uint32 # enum + +# values for enumeration 'RingCounterControl' +RingCounterControl__enumvalues = { + 0: 'COUNTER_RING_SPLIT', + 1: 'COUNTER_RING_0', + 2: 'COUNTER_RING_1', +} +COUNTER_RING_SPLIT = 0 +COUNTER_RING_0 = 1 +COUNTER_RING_1 = 2 +RingCounterControl = ctypes.c_uint32 # enum + +# values for enumeration 'DbMemArbWatermarks' +DbMemArbWatermarks__enumvalues = { + 0: 'TRANSFERRED_64_BYTES', + 1: 'TRANSFERRED_128_BYTES', + 2: 'TRANSFERRED_256_BYTES', + 3: 'TRANSFERRED_512_BYTES', + 4: 'TRANSFERRED_1024_BYTES', + 5: 'TRANSFERRED_2048_BYTES', + 6: 'TRANSFERRED_4096_BYTES', + 7: 'TRANSFERRED_8192_BYTES', +} +TRANSFERRED_64_BYTES = 0 +TRANSFERRED_128_BYTES = 1 +TRANSFERRED_256_BYTES = 2 +TRANSFERRED_512_BYTES = 3 +TRANSFERRED_1024_BYTES = 4 +TRANSFERRED_2048_BYTES = 5 +TRANSFERRED_4096_BYTES = 6 +TRANSFERRED_8192_BYTES = 7 +DbMemArbWatermarks = ctypes.c_uint32 # enum + +# values for enumeration 'DFSMFlushEvents' +DFSMFlushEvents__enumvalues = { + 0: 'DB_FLUSH_AND_INV_DB_DATA_TS', + 1: 'DB_FLUSH_AND_INV_DB_META', + 2: 'DB_CACHE_FLUSH', + 3: 'DB_CACHE_FLUSH_TS', + 4: 'DB_CACHE_FLUSH_AND_INV_EVENT', + 5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', +} +DB_FLUSH_AND_INV_DB_DATA_TS = 0 +DB_FLUSH_AND_INV_DB_META = 1 +DB_CACHE_FLUSH = 2 +DB_CACHE_FLUSH_TS = 3 +DB_CACHE_FLUSH_AND_INV_EVENT = 4 +DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5 +DFSMFlushEvents = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeCounterId' +PixelPipeCounterId__enumvalues = { + 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', + 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', + 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', + 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', + 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', + 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', +} +PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 +PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 +PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 +PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 +PixelPipeCounterId = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeStride' +PixelPipeStride__enumvalues = { + 0: 'PIXEL_PIPE_STRIDE_32_BITS', + 1: 'PIXEL_PIPE_STRIDE_64_BITS', + 2: 'PIXEL_PIPE_STRIDE_128_BITS', + 3: 'PIXEL_PIPE_STRIDE_256_BITS', +} +PIXEL_PIPE_STRIDE_32_BITS = 0 +PIXEL_PIPE_STRIDE_64_BITS = 1 +PIXEL_PIPE_STRIDE_128_BITS = 2 +PIXEL_PIPE_STRIDE_256_BITS = 3 +PixelPipeStride = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_BORDER_COLOR_TYPE' +TEX_BORDER_COLOR_TYPE__enumvalues = { + 0: 'TEX_BorderColor_TransparentBlack', + 1: 'TEX_BorderColor_OpaqueBlack', + 2: 'TEX_BorderColor_OpaqueWhite', + 3: 'TEX_BorderColor_Register', +} +TEX_BorderColor_TransparentBlack = 0 +TEX_BorderColor_OpaqueBlack = 1 +TEX_BorderColor_OpaqueWhite = 2 +TEX_BorderColor_Register = 3 +TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CHROMA_KEY' +TEX_CHROMA_KEY__enumvalues = { + 0: 'TEX_ChromaKey_Disabled', + 1: 'TEX_ChromaKey_Kill', + 2: 'TEX_ChromaKey_Blend', + 3: 'TEX_ChromaKey_RESERVED_3', +} +TEX_ChromaKey_Disabled = 0 +TEX_ChromaKey_Kill = 1 +TEX_ChromaKey_Blend = 2 +TEX_ChromaKey_RESERVED_3 = 3 +TEX_CHROMA_KEY = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CLAMP' +TEX_CLAMP__enumvalues = { + 0: 'TEX_Clamp_Repeat', + 1: 'TEX_Clamp_Mirror', + 2: 'TEX_Clamp_ClampToLast', + 3: 'TEX_Clamp_MirrorOnceToLast', + 4: 'TEX_Clamp_ClampHalfToBorder', + 5: 'TEX_Clamp_MirrorOnceHalfToBorder', + 6: 'TEX_Clamp_ClampToBorder', + 7: 'TEX_Clamp_MirrorOnceToBorder', +} +TEX_Clamp_Repeat = 0 +TEX_Clamp_Mirror = 1 +TEX_Clamp_ClampToLast = 2 +TEX_Clamp_MirrorOnceToLast = 3 +TEX_Clamp_ClampHalfToBorder = 4 +TEX_Clamp_MirrorOnceHalfToBorder = 5 +TEX_Clamp_ClampToBorder = 6 +TEX_Clamp_MirrorOnceToBorder = 7 +TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_COORD_TYPE' +TEX_COORD_TYPE__enumvalues = { + 0: 'TEX_CoordType_Unnormalized', + 1: 'TEX_CoordType_Normalized', +} +TEX_CoordType_Unnormalized = 0 +TEX_CoordType_Normalized = 1 +TEX_COORD_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' +TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { + 0: 'TEX_DepthCompareFunction_Never', + 1: 'TEX_DepthCompareFunction_Less', + 2: 'TEX_DepthCompareFunction_Equal', + 3: 'TEX_DepthCompareFunction_LessEqual', + 4: 'TEX_DepthCompareFunction_Greater', + 5: 'TEX_DepthCompareFunction_NotEqual', + 6: 'TEX_DepthCompareFunction_GreaterEqual', + 7: 'TEX_DepthCompareFunction_Always', +} +TEX_DepthCompareFunction_Never = 0 +TEX_DepthCompareFunction_Less = 1 +TEX_DepthCompareFunction_Equal = 2 +TEX_DepthCompareFunction_LessEqual = 3 +TEX_DepthCompareFunction_Greater = 4 +TEX_DepthCompareFunction_NotEqual = 5 +TEX_DepthCompareFunction_GreaterEqual = 6 +TEX_DepthCompareFunction_Always = 7 +TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_DIM' +TEX_DIM__enumvalues = { + 0: 'TEX_Dim_1D', + 1: 'TEX_Dim_2D', + 2: 'TEX_Dim_3D', + 3: 'TEX_Dim_CubeMap', + 4: 'TEX_Dim_1DArray', + 5: 'TEX_Dim_2DArray', + 6: 'TEX_Dim_2D_MSAA', + 7: 'TEX_Dim_2DArray_MSAA', +} +TEX_Dim_1D = 0 +TEX_Dim_2D = 1 +TEX_Dim_3D = 2 +TEX_Dim_CubeMap = 3 +TEX_Dim_1DArray = 4 +TEX_Dim_2DArray = 5 +TEX_Dim_2D_MSAA = 6 +TEX_Dim_2DArray_MSAA = 7 +TEX_DIM = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_FORMAT_COMP' +TEX_FORMAT_COMP__enumvalues = { + 0: 'TEX_FormatComp_Unsigned', + 1: 'TEX_FormatComp_Signed', + 2: 'TEX_FormatComp_UnsignedBiased', + 3: 'TEX_FormatComp_RESERVED_3', +} +TEX_FormatComp_Unsigned = 0 +TEX_FormatComp_Signed = 1 +TEX_FormatComp_UnsignedBiased = 2 +TEX_FormatComp_RESERVED_3 = 3 +TEX_FORMAT_COMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MAX_ANISO_RATIO' +TEX_MAX_ANISO_RATIO__enumvalues = { + 0: 'TEX_MaxAnisoRatio_1to1', + 1: 'TEX_MaxAnisoRatio_2to1', + 2: 'TEX_MaxAnisoRatio_4to1', + 3: 'TEX_MaxAnisoRatio_8to1', + 4: 'TEX_MaxAnisoRatio_16to1', + 5: 'TEX_MaxAnisoRatio_RESERVED_5', + 6: 'TEX_MaxAnisoRatio_RESERVED_6', + 7: 'TEX_MaxAnisoRatio_RESERVED_7', +} +TEX_MaxAnisoRatio_1to1 = 0 +TEX_MaxAnisoRatio_2to1 = 1 +TEX_MaxAnisoRatio_4to1 = 2 +TEX_MaxAnisoRatio_8to1 = 3 +TEX_MaxAnisoRatio_16to1 = 4 +TEX_MaxAnisoRatio_RESERVED_5 = 5 +TEX_MaxAnisoRatio_RESERVED_6 = 6 +TEX_MaxAnisoRatio_RESERVED_7 = 7 +TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MIP_FILTER' +TEX_MIP_FILTER__enumvalues = { + 0: 'TEX_MipFilter_None', + 1: 'TEX_MipFilter_Point', + 2: 'TEX_MipFilter_Linear', + 3: 'TEX_MipFilter_Point_Aniso_Adj', +} +TEX_MipFilter_None = 0 +TEX_MipFilter_Point = 1 +TEX_MipFilter_Linear = 2 +TEX_MipFilter_Point_Aniso_Adj = 3 +TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_REQUEST_SIZE' +TEX_REQUEST_SIZE__enumvalues = { + 0: 'TEX_RequestSize_32B', + 1: 'TEX_RequestSize_64B', + 2: 'TEX_RequestSize_128B', + 3: 'TEX_RequestSize_2X64B', +} +TEX_RequestSize_32B = 0 +TEX_RequestSize_64B = 1 +TEX_RequestSize_128B = 2 +TEX_RequestSize_2X64B = 3 +TEX_REQUEST_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_SAMPLER_TYPE' +TEX_SAMPLER_TYPE__enumvalues = { + 0: 'TEX_SamplerType_Invalid', + 1: 'TEX_SamplerType_Valid', +} +TEX_SamplerType_Invalid = 0 +TEX_SamplerType_Valid = 1 +TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_XY_FILTER' +TEX_XY_FILTER__enumvalues = { + 0: 'TEX_XYFilter_Point', + 1: 'TEX_XYFilter_Linear', + 2: 'TEX_XYFilter_AnisoPoint', + 3: 'TEX_XYFilter_AnisoLinear', +} +TEX_XYFilter_Point = 0 +TEX_XYFilter_Linear = 1 +TEX_XYFilter_AnisoPoint = 2 +TEX_XYFilter_AnisoLinear = 3 +TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_Z_FILTER' +TEX_Z_FILTER__enumvalues = { + 0: 'TEX_ZFilter_None', + 1: 'TEX_ZFilter_Point', + 2: 'TEX_ZFilter_Linear', + 3: 'TEX_ZFilter_RESERVED_3', +} +TEX_ZFilter_None = 0 +TEX_ZFilter_Point = 1 +TEX_ZFilter_Linear = 2 +TEX_ZFilter_RESERVED_3 = 3 +TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'VTX_CLAMP' +VTX_CLAMP__enumvalues = { + 0: 'VTX_Clamp_ClampToZero', + 1: 'VTX_Clamp_ClampToNAN', +} +VTX_Clamp_ClampToZero = 0 +VTX_Clamp_ClampToNAN = 1 +VTX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'VTX_FETCH_TYPE' +VTX_FETCH_TYPE__enumvalues = { + 0: 'VTX_FetchType_VertexData', + 1: 'VTX_FetchType_InstanceData', + 2: 'VTX_FetchType_NoIndexOffset', + 3: 'VTX_FetchType_RESERVED_3', +} +VTX_FetchType_VertexData = 0 +VTX_FetchType_InstanceData = 1 +VTX_FetchType_NoIndexOffset = 2 +VTX_FetchType_RESERVED_3 = 3 +VTX_FETCH_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VTX_FORMAT_COMP_ALL' +VTX_FORMAT_COMP_ALL__enumvalues = { + 0: 'VTX_FormatCompAll_Unsigned', + 1: 'VTX_FormatCompAll_Signed', +} +VTX_FormatCompAll_Unsigned = 0 +VTX_FormatCompAll_Signed = 1 +VTX_FORMAT_COMP_ALL = ctypes.c_uint32 # enum + +# values for enumeration 'VTX_MEM_REQUEST_SIZE' +VTX_MEM_REQUEST_SIZE__enumvalues = { + 0: 'VTX_MemRequestSize_32B', + 1: 'VTX_MemRequestSize_64B', +} +VTX_MemRequestSize_32B = 0 +VTX_MemRequestSize_64B = 1 +VTX_MEM_REQUEST_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_DATA_FORMAT' +TVX_DATA_FORMAT__enumvalues = { + 0: 'TVX_FMT_INVALID', + 1: 'TVX_FMT_8', + 2: 'TVX_FMT_4_4', + 3: 'TVX_FMT_3_3_2', + 4: 'TVX_FMT_RESERVED_4', + 5: 'TVX_FMT_16', + 6: 'TVX_FMT_16_FLOAT', + 7: 'TVX_FMT_8_8', + 8: 'TVX_FMT_5_6_5', + 9: 'TVX_FMT_6_5_5', + 10: 'TVX_FMT_1_5_5_5', + 11: 'TVX_FMT_4_4_4_4', + 12: 'TVX_FMT_5_5_5_1', + 13: 'TVX_FMT_32', + 14: 'TVX_FMT_32_FLOAT', + 15: 'TVX_FMT_16_16', + 16: 'TVX_FMT_16_16_FLOAT', + 17: 'TVX_FMT_8_24', + 18: 'TVX_FMT_8_24_FLOAT', + 19: 'TVX_FMT_24_8', + 20: 'TVX_FMT_24_8_FLOAT', + 21: 'TVX_FMT_10_11_11', + 22: 'TVX_FMT_10_11_11_FLOAT', + 23: 'TVX_FMT_11_11_10', + 24: 'TVX_FMT_11_11_10_FLOAT', + 25: 'TVX_FMT_2_10_10_10', + 26: 'TVX_FMT_8_8_8_8', + 27: 'TVX_FMT_10_10_10_2', + 28: 'TVX_FMT_X24_8_32_FLOAT', + 29: 'TVX_FMT_32_32', + 30: 'TVX_FMT_32_32_FLOAT', + 31: 'TVX_FMT_16_16_16_16', + 32: 'TVX_FMT_16_16_16_16_FLOAT', + 33: 'TVX_FMT_RESERVED_33', + 34: 'TVX_FMT_32_32_32_32', + 35: 'TVX_FMT_32_32_32_32_FLOAT', + 36: 'TVX_FMT_RESERVED_36', + 37: 'TVX_FMT_1', + 38: 'TVX_FMT_1_REVERSED', + 39: 'TVX_FMT_GB_GR', + 40: 'TVX_FMT_BG_RG', + 41: 'TVX_FMT_32_AS_8', + 42: 'TVX_FMT_32_AS_8_8', + 43: 'TVX_FMT_5_9_9_9_SHAREDEXP', + 44: 'TVX_FMT_8_8_8', + 45: 'TVX_FMT_16_16_16', + 46: 'TVX_FMT_16_16_16_FLOAT', + 47: 'TVX_FMT_32_32_32', + 48: 'TVX_FMT_32_32_32_FLOAT', + 49: 'TVX_FMT_BC1', + 50: 'TVX_FMT_BC2', + 51: 'TVX_FMT_BC3', + 52: 'TVX_FMT_BC4', + 53: 'TVX_FMT_BC5', + 54: 'TVX_FMT_APC0', + 55: 'TVX_FMT_APC1', + 56: 'TVX_FMT_APC2', + 57: 'TVX_FMT_APC3', + 58: 'TVX_FMT_APC4', + 59: 'TVX_FMT_APC5', + 60: 'TVX_FMT_APC6', + 61: 'TVX_FMT_APC7', + 62: 'TVX_FMT_CTX1', + 63: 'TVX_FMT_RESERVED_63', +} +TVX_FMT_INVALID = 0 +TVX_FMT_8 = 1 +TVX_FMT_4_4 = 2 +TVX_FMT_3_3_2 = 3 +TVX_FMT_RESERVED_4 = 4 +TVX_FMT_16 = 5 +TVX_FMT_16_FLOAT = 6 +TVX_FMT_8_8 = 7 +TVX_FMT_5_6_5 = 8 +TVX_FMT_6_5_5 = 9 +TVX_FMT_1_5_5_5 = 10 +TVX_FMT_4_4_4_4 = 11 +TVX_FMT_5_5_5_1 = 12 +TVX_FMT_32 = 13 +TVX_FMT_32_FLOAT = 14 +TVX_FMT_16_16 = 15 +TVX_FMT_16_16_FLOAT = 16 +TVX_FMT_8_24 = 17 +TVX_FMT_8_24_FLOAT = 18 +TVX_FMT_24_8 = 19 +TVX_FMT_24_8_FLOAT = 20 +TVX_FMT_10_11_11 = 21 +TVX_FMT_10_11_11_FLOAT = 22 +TVX_FMT_11_11_10 = 23 +TVX_FMT_11_11_10_FLOAT = 24 +TVX_FMT_2_10_10_10 = 25 +TVX_FMT_8_8_8_8 = 26 +TVX_FMT_10_10_10_2 = 27 +TVX_FMT_X24_8_32_FLOAT = 28 +TVX_FMT_32_32 = 29 +TVX_FMT_32_32_FLOAT = 30 +TVX_FMT_16_16_16_16 = 31 +TVX_FMT_16_16_16_16_FLOAT = 32 +TVX_FMT_RESERVED_33 = 33 +TVX_FMT_32_32_32_32 = 34 +TVX_FMT_32_32_32_32_FLOAT = 35 +TVX_FMT_RESERVED_36 = 36 +TVX_FMT_1 = 37 +TVX_FMT_1_REVERSED = 38 +TVX_FMT_GB_GR = 39 +TVX_FMT_BG_RG = 40 +TVX_FMT_32_AS_8 = 41 +TVX_FMT_32_AS_8_8 = 42 +TVX_FMT_5_9_9_9_SHAREDEXP = 43 +TVX_FMT_8_8_8 = 44 +TVX_FMT_16_16_16 = 45 +TVX_FMT_16_16_16_FLOAT = 46 +TVX_FMT_32_32_32 = 47 +TVX_FMT_32_32_32_FLOAT = 48 +TVX_FMT_BC1 = 49 +TVX_FMT_BC2 = 50 +TVX_FMT_BC3 = 51 +TVX_FMT_BC4 = 52 +TVX_FMT_BC5 = 53 +TVX_FMT_APC0 = 54 +TVX_FMT_APC1 = 55 +TVX_FMT_APC2 = 56 +TVX_FMT_APC3 = 57 +TVX_FMT_APC4 = 58 +TVX_FMT_APC5 = 59 +TVX_FMT_APC6 = 60 +TVX_FMT_APC7 = 61 +TVX_FMT_CTX1 = 62 +TVX_FMT_RESERVED_63 = 63 +TVX_DATA_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_DST_SEL' +TVX_DST_SEL__enumvalues = { + 0: 'TVX_DstSel_X', + 1: 'TVX_DstSel_Y', + 2: 'TVX_DstSel_Z', + 3: 'TVX_DstSel_W', + 4: 'TVX_DstSel_0f', + 5: 'TVX_DstSel_1f', + 6: 'TVX_DstSel_RESERVED_6', + 7: 'TVX_DstSel_Mask', +} +TVX_DstSel_X = 0 +TVX_DstSel_Y = 1 +TVX_DstSel_Z = 2 +TVX_DstSel_W = 3 +TVX_DstSel_0f = 4 +TVX_DstSel_1f = 5 +TVX_DstSel_RESERVED_6 = 6 +TVX_DstSel_Mask = 7 +TVX_DST_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_ENDIAN_SWAP' +TVX_ENDIAN_SWAP__enumvalues = { + 0: 'TVX_EndianSwap_None', + 1: 'TVX_EndianSwap_8in16', + 2: 'TVX_EndianSwap_8in32', + 3: 'TVX_EndianSwap_8in64', +} +TVX_EndianSwap_None = 0 +TVX_EndianSwap_8in16 = 1 +TVX_EndianSwap_8in32 = 2 +TVX_EndianSwap_8in64 = 3 +TVX_ENDIAN_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_INST' +TVX_INST__enumvalues = { + 0: 'TVX_Inst_NormalVertexFetch', + 1: 'TVX_Inst_SemanticVertexFetch', + 2: 'TVX_Inst_RESERVED_2', + 3: 'TVX_Inst_LD', + 4: 'TVX_Inst_GetTextureResInfo', + 5: 'TVX_Inst_GetNumberOfSamples', + 6: 'TVX_Inst_GetLOD', + 7: 'TVX_Inst_GetGradientsH', + 8: 'TVX_Inst_GetGradientsV', + 9: 'TVX_Inst_SetTextureOffsets', + 10: 'TVX_Inst_KeepGradients', + 11: 'TVX_Inst_SetGradientsH', + 12: 'TVX_Inst_SetGradientsV', + 13: 'TVX_Inst_Pass', + 14: 'TVX_Inst_GetBufferResInfo', + 15: 'TVX_Inst_RESERVED_15', + 16: 'TVX_Inst_Sample', + 17: 'TVX_Inst_Sample_L', + 18: 'TVX_Inst_Sample_LB', + 19: 'TVX_Inst_Sample_LZ', + 20: 'TVX_Inst_Sample_G', + 21: 'TVX_Inst_Gather4', + 22: 'TVX_Inst_Sample_G_LB', + 23: 'TVX_Inst_Gather4_O', + 24: 'TVX_Inst_Sample_C', + 25: 'TVX_Inst_Sample_C_L', + 26: 'TVX_Inst_Sample_C_LB', + 27: 'TVX_Inst_Sample_C_LZ', + 28: 'TVX_Inst_Sample_C_G', + 29: 'TVX_Inst_Gather4_C', + 30: 'TVX_Inst_Sample_C_G_LB', + 31: 'TVX_Inst_Gather4_C_O', +} +TVX_Inst_NormalVertexFetch = 0 +TVX_Inst_SemanticVertexFetch = 1 +TVX_Inst_RESERVED_2 = 2 +TVX_Inst_LD = 3 +TVX_Inst_GetTextureResInfo = 4 +TVX_Inst_GetNumberOfSamples = 5 +TVX_Inst_GetLOD = 6 +TVX_Inst_GetGradientsH = 7 +TVX_Inst_GetGradientsV = 8 +TVX_Inst_SetTextureOffsets = 9 +TVX_Inst_KeepGradients = 10 +TVX_Inst_SetGradientsH = 11 +TVX_Inst_SetGradientsV = 12 +TVX_Inst_Pass = 13 +TVX_Inst_GetBufferResInfo = 14 +TVX_Inst_RESERVED_15 = 15 +TVX_Inst_Sample = 16 +TVX_Inst_Sample_L = 17 +TVX_Inst_Sample_LB = 18 +TVX_Inst_Sample_LZ = 19 +TVX_Inst_Sample_G = 20 +TVX_Inst_Gather4 = 21 +TVX_Inst_Sample_G_LB = 22 +TVX_Inst_Gather4_O = 23 +TVX_Inst_Sample_C = 24 +TVX_Inst_Sample_C_L = 25 +TVX_Inst_Sample_C_LB = 26 +TVX_Inst_Sample_C_LZ = 27 +TVX_Inst_Sample_C_G = 28 +TVX_Inst_Gather4_C = 29 +TVX_Inst_Sample_C_G_LB = 30 +TVX_Inst_Gather4_C_O = 31 +TVX_INST = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_NUM_FORMAT_ALL' +TVX_NUM_FORMAT_ALL__enumvalues = { + 0: 'TVX_NumFormatAll_Norm', + 1: 'TVX_NumFormatAll_Int', + 2: 'TVX_NumFormatAll_Scaled', + 3: 'TVX_NumFormatAll_RESERVED_3', +} +TVX_NumFormatAll_Norm = 0 +TVX_NumFormatAll_Int = 1 +TVX_NumFormatAll_Scaled = 2 +TVX_NumFormatAll_RESERVED_3 = 3 +TVX_NUM_FORMAT_ALL = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_SRC_SEL' +TVX_SRC_SEL__enumvalues = { + 0: 'TVX_SrcSel_X', + 1: 'TVX_SrcSel_Y', + 2: 'TVX_SrcSel_Z', + 3: 'TVX_SrcSel_W', + 4: 'TVX_SrcSel_0f', + 5: 'TVX_SrcSel_1f', +} +TVX_SrcSel_X = 0 +TVX_SrcSel_Y = 1 +TVX_SrcSel_Z = 2 +TVX_SrcSel_W = 3 +TVX_SrcSel_0f = 4 +TVX_SrcSel_1f = 5 +TVX_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_SRF_MODE_ALL' +TVX_SRF_MODE_ALL__enumvalues = { + 0: 'TVX_SRFModeAll_ZCMO', + 1: 'TVX_SRFModeAll_NZ', +} +TVX_SRFModeAll_ZCMO = 0 +TVX_SRFModeAll_NZ = 1 +TVX_SRF_MODE_ALL = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_TYPE' +TVX_TYPE__enumvalues = { + 0: 'TVX_Type_InvalidTextureResource', + 1: 'TVX_Type_InvalidVertexBuffer', + 2: 'TVX_Type_ValidTextureResource', + 3: 'TVX_Type_ValidVertexBuffer', +} +TVX_Type_InvalidTextureResource = 0 +TVX_Type_InvalidVertexBuffer = 1 +TVX_Type_ValidTextureResource = 2 +TVX_Type_ValidVertexBuffer = 3 +TVX_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SU_PERFCNT_SEL' +SU_PERFCNT_SEL__enumvalues = { + 0: 'PERF_PAPC_PASX_REQ', + 1: 'PERF_PAPC_PASX_DISABLE_PIPE', + 2: 'PERF_PAPC_PASX_FIRST_VECTOR', + 3: 'PERF_PAPC_PASX_SECOND_VECTOR', + 4: 'PERF_PAPC_PASX_FIRST_DEAD', + 5: 'PERF_PAPC_PASX_SECOND_DEAD', + 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 8: 'PERF_PAPC_PA_INPUT_PRIM', + 9: 'PERF_PAPC_PA_INPUT_NULL_PRIM', + 10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG', + 11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', + 12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET', + 13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', + 14: 'PERF_PAPC_CLPR_CULL_PRIM', + 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', + 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', + 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', + 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', + 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', + 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', + 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', + 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 39: 'PERF_PAPC_CLSM_NULL_PRIM', + 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', + 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', + 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', + 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', + 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', + 49: 'PERF_PAPC_SU_INPUT_PRIM', + 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', + 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 61: 'PERF_PAPC_SU_OUTPUT_PRIM', + 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', + 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', + 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 77: 'PERF_PAPC_PASX_REQ_IDLE', + 78: 'PERF_PAPC_PASX_REQ_BUSY', + 79: 'PERF_PAPC_PASX_REQ_STALLED', + 80: 'PERF_PAPC_PASX_REC_IDLE', + 81: 'PERF_PAPC_PASX_REC_BUSY', + 82: 'PERF_PAPC_PASX_REC_STARVED_SX', + 83: 'PERF_PAPC_PASX_REC_STALLED', + 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 86: 'PERF_PAPC_CCGSM_IDLE', + 87: 'PERF_PAPC_CCGSM_BUSY', + 88: 'PERF_PAPC_CCGSM_STALLED', + 89: 'PERF_PAPC_CLPRIM_IDLE', + 90: 'PERF_PAPC_CLPRIM_BUSY', + 91: 'PERF_PAPC_CLPRIM_STALLED', + 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 93: 'PERF_PAPC_CLIPSM_IDLE', + 94: 'PERF_PAPC_CLIPSM_BUSY', + 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', + 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 100: 'PERF_PAPC_CLIPGA_IDLE', + 101: 'PERF_PAPC_CLIPGA_BUSY', + 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 103: 'PERF_PAPC_CLIPGA_STALLED', + 104: 'PERF_PAPC_CLIP_IDLE', + 105: 'PERF_PAPC_CLIP_BUSY', + 106: 'PERF_PAPC_SU_IDLE', + 107: 'PERF_PAPC_SU_BUSY', + 108: 'PERF_PAPC_SU_STARVED_CLIP', + 109: 'PERF_PAPC_SU_STALLED_SC', + 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', + 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', + 112: 'PERF_PAPC_PA_REG_SCLK_VLD', + 113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', + 114: 'PERF_PAPC_PASX_SE0_REQ', + 115: 'PERF_PAPC_PASX_SE1_REQ', + 116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', + 117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', + 118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', + 119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', + 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', + 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', + 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', + 129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', + 130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', + 131: 'PERF_PAPC_SU_SE0_STALLED_SC', + 132: 'PERF_PAPC_SU_SE1_STALLED_SC', + 133: 'PERF_PAPC_SU_SE01_STALLED_SC', + 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 135: 'PERF_PAPC_SU_CULLED_PRIM', + 136: 'PERF_PAPC_SU_OUTPUT_EOPG', + 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', + 144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', + 145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', + 146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', + 147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', + 148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', + 149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', + 150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', + 151: 'PERF_PAPC_SU_SE2_STALLED_SC', + 152: 'PERF_PAPC_SU_SE3_STALLED_SC', +} +PERF_PAPC_PASX_REQ = 0 +PERF_PAPC_PASX_DISABLE_PIPE = 1 +PERF_PAPC_PASX_FIRST_VECTOR = 2 +PERF_PAPC_PASX_SECOND_VECTOR = 3 +PERF_PAPC_PASX_FIRST_DEAD = 4 +PERF_PAPC_PASX_SECOND_DEAD = 5 +PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 +PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 +PERF_PAPC_PA_INPUT_PRIM = 8 +PERF_PAPC_PA_INPUT_NULL_PRIM = 9 +PERF_PAPC_PA_INPUT_EVENT_FLAG = 10 +PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11 +PERF_PAPC_PA_INPUT_END_OF_PACKET = 12 +PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13 +PERF_PAPC_CLPR_CULL_PRIM = 14 +PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 +PERF_PAPC_CLPR_VV_CULL_PRIM = 16 +PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 +PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 +PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 +PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 +PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 +PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 +PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 +PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30 +PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 +PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 +PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 +PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 +PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 +PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 +PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37 +PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 +PERF_PAPC_CLSM_NULL_PRIM = 39 +PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 +PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 +PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 +PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 +PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 +PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 +PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 +PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47 +PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 +PERF_PAPC_SU_INPUT_PRIM = 49 +PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 +PERF_PAPC_SU_INPUT_NULL_PRIM = 51 +PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 +PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 +PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 +PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 +PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 +PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 +PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 +PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 +PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 +PERF_PAPC_SU_OUTPUT_PRIM = 61 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 +PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 +PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 +PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 +PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 +PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 +PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 +PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 +PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 +PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 +PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 +PERF_PAPC_PASX_REQ_IDLE = 77 +PERF_PAPC_PASX_REQ_BUSY = 78 +PERF_PAPC_PASX_REQ_STALLED = 79 +PERF_PAPC_PASX_REC_IDLE = 80 +PERF_PAPC_PASX_REC_BUSY = 81 +PERF_PAPC_PASX_REC_STARVED_SX = 82 +PERF_PAPC_PASX_REC_STALLED = 83 +PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 +PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 +PERF_PAPC_CCGSM_IDLE = 86 +PERF_PAPC_CCGSM_BUSY = 87 +PERF_PAPC_CCGSM_STALLED = 88 +PERF_PAPC_CLPRIM_IDLE = 89 +PERF_PAPC_CLPRIM_BUSY = 90 +PERF_PAPC_CLPRIM_STALLED = 91 +PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 +PERF_PAPC_CLIPSM_IDLE = 93 +PERF_PAPC_CLIPSM_BUSY = 94 +PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 +PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 +PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 +PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 +PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 +PERF_PAPC_CLIPGA_IDLE = 100 +PERF_PAPC_CLIPGA_BUSY = 101 +PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 +PERF_PAPC_CLIPGA_STALLED = 103 +PERF_PAPC_CLIP_IDLE = 104 +PERF_PAPC_CLIP_BUSY = 105 +PERF_PAPC_SU_IDLE = 106 +PERF_PAPC_SU_BUSY = 107 +PERF_PAPC_SU_STARVED_CLIP = 108 +PERF_PAPC_SU_STALLED_SC = 109 +PERF_PAPC_CL_DYN_SCLK_VLD = 110 +PERF_PAPC_SU_DYN_SCLK_VLD = 111 +PERF_PAPC_PA_REG_SCLK_VLD = 112 +PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113 +PERF_PAPC_PASX_SE0_REQ = 114 +PERF_PAPC_PASX_SE1_REQ = 115 +PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116 +PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117 +PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118 +PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119 +PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 +PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 +PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122 +PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 +PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 +PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125 +PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 +PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 +PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128 +PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129 +PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130 +PERF_PAPC_SU_SE0_STALLED_SC = 131 +PERF_PAPC_SU_SE1_STALLED_SC = 132 +PERF_PAPC_SU_SE01_STALLED_SC = 133 +PERF_PAPC_CLSM_CLIPPING_PRIM = 134 +PERF_PAPC_SU_CULLED_PRIM = 135 +PERF_PAPC_SU_OUTPUT_EOPG = 136 +PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 +PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 +PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 +PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 +PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 +PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 +PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143 +PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144 +PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145 +PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146 +PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147 +PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148 +PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149 +PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150 +PERF_PAPC_SU_SE2_STALLED_SC = 151 +PERF_PAPC_SU_SE3_STALLED_SC = 152 +SU_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SC_PERFCNT_SEL' +SC_PERFCNT_SEL__enumvalues = { + 0: 'SC_SRPS_WINDOW_VALID', + 1: 'SC_PSSW_WINDOW_VALID', + 2: 'SC_TPQZ_WINDOW_VALID', + 3: 'SC_QZQP_WINDOW_VALID', + 4: 'SC_TRPK_WINDOW_VALID', + 5: 'SC_SRPS_WINDOW_VALID_BUSY', + 6: 'SC_PSSW_WINDOW_VALID_BUSY', + 7: 'SC_TPQZ_WINDOW_VALID_BUSY', + 8: 'SC_QZQP_WINDOW_VALID_BUSY', + 9: 'SC_TRPK_WINDOW_VALID_BUSY', + 10: 'SC_STARVED_BY_PA', + 11: 'SC_STALLED_BY_PRIMFIFO', + 12: 'SC_STALLED_BY_DB_TILE', + 13: 'SC_STARVED_BY_DB_TILE', + 14: 'SC_STALLED_BY_TILEORDERFIFO', + 15: 'SC_STALLED_BY_TILEFIFO', + 16: 'SC_STALLED_BY_DB_QUAD', + 17: 'SC_STARVED_BY_DB_QUAD', + 18: 'SC_STALLED_BY_QUADFIFO', + 19: 'SC_STALLED_BY_BCI', + 20: 'SC_STALLED_BY_SPI', + 21: 'SC_SCISSOR_DISCARD', + 22: 'SC_BB_DISCARD', + 23: 'SC_SUPERTILE_COUNT', + 24: 'SC_SUPERTILE_PER_PRIM_H0', + 25: 'SC_SUPERTILE_PER_PRIM_H1', + 26: 'SC_SUPERTILE_PER_PRIM_H2', + 27: 'SC_SUPERTILE_PER_PRIM_H3', + 28: 'SC_SUPERTILE_PER_PRIM_H4', + 29: 'SC_SUPERTILE_PER_PRIM_H5', + 30: 'SC_SUPERTILE_PER_PRIM_H6', + 31: 'SC_SUPERTILE_PER_PRIM_H7', + 32: 'SC_SUPERTILE_PER_PRIM_H8', + 33: 'SC_SUPERTILE_PER_PRIM_H9', + 34: 'SC_SUPERTILE_PER_PRIM_H10', + 35: 'SC_SUPERTILE_PER_PRIM_H11', + 36: 'SC_SUPERTILE_PER_PRIM_H12', + 37: 'SC_SUPERTILE_PER_PRIM_H13', + 38: 'SC_SUPERTILE_PER_PRIM_H14', + 39: 'SC_SUPERTILE_PER_PRIM_H15', + 40: 'SC_SUPERTILE_PER_PRIM_H16', + 41: 'SC_TILE_PER_PRIM_H0', + 42: 'SC_TILE_PER_PRIM_H1', + 43: 'SC_TILE_PER_PRIM_H2', + 44: 'SC_TILE_PER_PRIM_H3', + 45: 'SC_TILE_PER_PRIM_H4', + 46: 'SC_TILE_PER_PRIM_H5', + 47: 'SC_TILE_PER_PRIM_H6', + 48: 'SC_TILE_PER_PRIM_H7', + 49: 'SC_TILE_PER_PRIM_H8', + 50: 'SC_TILE_PER_PRIM_H9', + 51: 'SC_TILE_PER_PRIM_H10', + 52: 'SC_TILE_PER_PRIM_H11', + 53: 'SC_TILE_PER_PRIM_H12', + 54: 'SC_TILE_PER_PRIM_H13', + 55: 'SC_TILE_PER_PRIM_H14', + 56: 'SC_TILE_PER_PRIM_H15', + 57: 'SC_TILE_PER_PRIM_H16', + 58: 'SC_TILE_PER_SUPERTILE_H0', + 59: 'SC_TILE_PER_SUPERTILE_H1', + 60: 'SC_TILE_PER_SUPERTILE_H2', + 61: 'SC_TILE_PER_SUPERTILE_H3', + 62: 'SC_TILE_PER_SUPERTILE_H4', + 63: 'SC_TILE_PER_SUPERTILE_H5', + 64: 'SC_TILE_PER_SUPERTILE_H6', + 65: 'SC_TILE_PER_SUPERTILE_H7', + 66: 'SC_TILE_PER_SUPERTILE_H8', + 67: 'SC_TILE_PER_SUPERTILE_H9', + 68: 'SC_TILE_PER_SUPERTILE_H10', + 69: 'SC_TILE_PER_SUPERTILE_H11', + 70: 'SC_TILE_PER_SUPERTILE_H12', + 71: 'SC_TILE_PER_SUPERTILE_H13', + 72: 'SC_TILE_PER_SUPERTILE_H14', + 73: 'SC_TILE_PER_SUPERTILE_H15', + 74: 'SC_TILE_PER_SUPERTILE_H16', + 75: 'SC_TILE_PICKED_H1', + 76: 'SC_TILE_PICKED_H2', + 77: 'SC_TILE_PICKED_H3', + 78: 'SC_TILE_PICKED_H4', + 79: 'SC_QZ0_MULTI_GPU_TILE_DISCARD', + 80: 'SC_QZ1_MULTI_GPU_TILE_DISCARD', + 81: 'SC_QZ2_MULTI_GPU_TILE_DISCARD', + 82: 'SC_QZ3_MULTI_GPU_TILE_DISCARD', + 83: 'SC_QZ0_TILE_COUNT', + 84: 'SC_QZ1_TILE_COUNT', + 85: 'SC_QZ2_TILE_COUNT', + 86: 'SC_QZ3_TILE_COUNT', + 87: 'SC_QZ0_TILE_COVERED_COUNT', + 88: 'SC_QZ1_TILE_COVERED_COUNT', + 89: 'SC_QZ2_TILE_COVERED_COUNT', + 90: 'SC_QZ3_TILE_COVERED_COUNT', + 91: 'SC_QZ0_TILE_NOT_COVERED_COUNT', + 92: 'SC_QZ1_TILE_NOT_COVERED_COUNT', + 93: 'SC_QZ2_TILE_NOT_COVERED_COUNT', + 94: 'SC_QZ3_TILE_NOT_COVERED_COUNT', + 95: 'SC_QZ0_QUAD_PER_TILE_H0', + 96: 'SC_QZ0_QUAD_PER_TILE_H1', + 97: 'SC_QZ0_QUAD_PER_TILE_H2', + 98: 'SC_QZ0_QUAD_PER_TILE_H3', + 99: 'SC_QZ0_QUAD_PER_TILE_H4', + 100: 'SC_QZ0_QUAD_PER_TILE_H5', + 101: 'SC_QZ0_QUAD_PER_TILE_H6', + 102: 'SC_QZ0_QUAD_PER_TILE_H7', + 103: 'SC_QZ0_QUAD_PER_TILE_H8', + 104: 'SC_QZ0_QUAD_PER_TILE_H9', + 105: 'SC_QZ0_QUAD_PER_TILE_H10', + 106: 'SC_QZ0_QUAD_PER_TILE_H11', + 107: 'SC_QZ0_QUAD_PER_TILE_H12', + 108: 'SC_QZ0_QUAD_PER_TILE_H13', + 109: 'SC_QZ0_QUAD_PER_TILE_H14', + 110: 'SC_QZ0_QUAD_PER_TILE_H15', + 111: 'SC_QZ0_QUAD_PER_TILE_H16', + 112: 'SC_QZ1_QUAD_PER_TILE_H0', + 113: 'SC_QZ1_QUAD_PER_TILE_H1', + 114: 'SC_QZ1_QUAD_PER_TILE_H2', + 115: 'SC_QZ1_QUAD_PER_TILE_H3', + 116: 'SC_QZ1_QUAD_PER_TILE_H4', + 117: 'SC_QZ1_QUAD_PER_TILE_H5', + 118: 'SC_QZ1_QUAD_PER_TILE_H6', + 119: 'SC_QZ1_QUAD_PER_TILE_H7', + 120: 'SC_QZ1_QUAD_PER_TILE_H8', + 121: 'SC_QZ1_QUAD_PER_TILE_H9', + 122: 'SC_QZ1_QUAD_PER_TILE_H10', + 123: 'SC_QZ1_QUAD_PER_TILE_H11', + 124: 'SC_QZ1_QUAD_PER_TILE_H12', + 125: 'SC_QZ1_QUAD_PER_TILE_H13', + 126: 'SC_QZ1_QUAD_PER_TILE_H14', + 127: 'SC_QZ1_QUAD_PER_TILE_H15', + 128: 'SC_QZ1_QUAD_PER_TILE_H16', + 129: 'SC_QZ2_QUAD_PER_TILE_H0', + 130: 'SC_QZ2_QUAD_PER_TILE_H1', + 131: 'SC_QZ2_QUAD_PER_TILE_H2', + 132: 'SC_QZ2_QUAD_PER_TILE_H3', + 133: 'SC_QZ2_QUAD_PER_TILE_H4', + 134: 'SC_QZ2_QUAD_PER_TILE_H5', + 135: 'SC_QZ2_QUAD_PER_TILE_H6', + 136: 'SC_QZ2_QUAD_PER_TILE_H7', + 137: 'SC_QZ2_QUAD_PER_TILE_H8', + 138: 'SC_QZ2_QUAD_PER_TILE_H9', + 139: 'SC_QZ2_QUAD_PER_TILE_H10', + 140: 'SC_QZ2_QUAD_PER_TILE_H11', + 141: 'SC_QZ2_QUAD_PER_TILE_H12', + 142: 'SC_QZ2_QUAD_PER_TILE_H13', + 143: 'SC_QZ2_QUAD_PER_TILE_H14', + 144: 'SC_QZ2_QUAD_PER_TILE_H15', + 145: 'SC_QZ2_QUAD_PER_TILE_H16', + 146: 'SC_QZ3_QUAD_PER_TILE_H0', + 147: 'SC_QZ3_QUAD_PER_TILE_H1', + 148: 'SC_QZ3_QUAD_PER_TILE_H2', + 149: 'SC_QZ3_QUAD_PER_TILE_H3', + 150: 'SC_QZ3_QUAD_PER_TILE_H4', + 151: 'SC_QZ3_QUAD_PER_TILE_H5', + 152: 'SC_QZ3_QUAD_PER_TILE_H6', + 153: 'SC_QZ3_QUAD_PER_TILE_H7', + 154: 'SC_QZ3_QUAD_PER_TILE_H8', + 155: 'SC_QZ3_QUAD_PER_TILE_H9', + 156: 'SC_QZ3_QUAD_PER_TILE_H10', + 157: 'SC_QZ3_QUAD_PER_TILE_H11', + 158: 'SC_QZ3_QUAD_PER_TILE_H12', + 159: 'SC_QZ3_QUAD_PER_TILE_H13', + 160: 'SC_QZ3_QUAD_PER_TILE_H14', + 161: 'SC_QZ3_QUAD_PER_TILE_H15', + 162: 'SC_QZ3_QUAD_PER_TILE_H16', + 163: 'SC_QZ0_QUAD_COUNT', + 164: 'SC_QZ1_QUAD_COUNT', + 165: 'SC_QZ2_QUAD_COUNT', + 166: 'SC_QZ3_QUAD_COUNT', + 167: 'SC_P0_HIZ_TILE_COUNT', + 168: 'SC_P1_HIZ_TILE_COUNT', + 169: 'SC_P2_HIZ_TILE_COUNT', + 170: 'SC_P3_HIZ_TILE_COUNT', + 171: 'SC_P0_HIZ_QUAD_PER_TILE_H0', + 172: 'SC_P0_HIZ_QUAD_PER_TILE_H1', + 173: 'SC_P0_HIZ_QUAD_PER_TILE_H2', + 174: 'SC_P0_HIZ_QUAD_PER_TILE_H3', + 175: 'SC_P0_HIZ_QUAD_PER_TILE_H4', + 176: 'SC_P0_HIZ_QUAD_PER_TILE_H5', + 177: 'SC_P0_HIZ_QUAD_PER_TILE_H6', + 178: 'SC_P0_HIZ_QUAD_PER_TILE_H7', + 179: 'SC_P0_HIZ_QUAD_PER_TILE_H8', + 180: 'SC_P0_HIZ_QUAD_PER_TILE_H9', + 181: 'SC_P0_HIZ_QUAD_PER_TILE_H10', + 182: 'SC_P0_HIZ_QUAD_PER_TILE_H11', + 183: 'SC_P0_HIZ_QUAD_PER_TILE_H12', + 184: 'SC_P0_HIZ_QUAD_PER_TILE_H13', + 185: 'SC_P0_HIZ_QUAD_PER_TILE_H14', + 186: 'SC_P0_HIZ_QUAD_PER_TILE_H15', + 187: 'SC_P0_HIZ_QUAD_PER_TILE_H16', + 188: 'SC_P1_HIZ_QUAD_PER_TILE_H0', + 189: 'SC_P1_HIZ_QUAD_PER_TILE_H1', + 190: 'SC_P1_HIZ_QUAD_PER_TILE_H2', + 191: 'SC_P1_HIZ_QUAD_PER_TILE_H3', + 192: 'SC_P1_HIZ_QUAD_PER_TILE_H4', + 193: 'SC_P1_HIZ_QUAD_PER_TILE_H5', + 194: 'SC_P1_HIZ_QUAD_PER_TILE_H6', + 195: 'SC_P1_HIZ_QUAD_PER_TILE_H7', + 196: 'SC_P1_HIZ_QUAD_PER_TILE_H8', + 197: 'SC_P1_HIZ_QUAD_PER_TILE_H9', + 198: 'SC_P1_HIZ_QUAD_PER_TILE_H10', + 199: 'SC_P1_HIZ_QUAD_PER_TILE_H11', + 200: 'SC_P1_HIZ_QUAD_PER_TILE_H12', + 201: 'SC_P1_HIZ_QUAD_PER_TILE_H13', + 202: 'SC_P1_HIZ_QUAD_PER_TILE_H14', + 203: 'SC_P1_HIZ_QUAD_PER_TILE_H15', + 204: 'SC_P1_HIZ_QUAD_PER_TILE_H16', + 205: 'SC_P2_HIZ_QUAD_PER_TILE_H0', + 206: 'SC_P2_HIZ_QUAD_PER_TILE_H1', + 207: 'SC_P2_HIZ_QUAD_PER_TILE_H2', + 208: 'SC_P2_HIZ_QUAD_PER_TILE_H3', + 209: 'SC_P2_HIZ_QUAD_PER_TILE_H4', + 210: 'SC_P2_HIZ_QUAD_PER_TILE_H5', + 211: 'SC_P2_HIZ_QUAD_PER_TILE_H6', + 212: 'SC_P2_HIZ_QUAD_PER_TILE_H7', + 213: 'SC_P2_HIZ_QUAD_PER_TILE_H8', + 214: 'SC_P2_HIZ_QUAD_PER_TILE_H9', + 215: 'SC_P2_HIZ_QUAD_PER_TILE_H10', + 216: 'SC_P2_HIZ_QUAD_PER_TILE_H11', + 217: 'SC_P2_HIZ_QUAD_PER_TILE_H12', + 218: 'SC_P2_HIZ_QUAD_PER_TILE_H13', + 219: 'SC_P2_HIZ_QUAD_PER_TILE_H14', + 220: 'SC_P2_HIZ_QUAD_PER_TILE_H15', + 221: 'SC_P2_HIZ_QUAD_PER_TILE_H16', + 222: 'SC_P3_HIZ_QUAD_PER_TILE_H0', + 223: 'SC_P3_HIZ_QUAD_PER_TILE_H1', + 224: 'SC_P3_HIZ_QUAD_PER_TILE_H2', + 225: 'SC_P3_HIZ_QUAD_PER_TILE_H3', + 226: 'SC_P3_HIZ_QUAD_PER_TILE_H4', + 227: 'SC_P3_HIZ_QUAD_PER_TILE_H5', + 228: 'SC_P3_HIZ_QUAD_PER_TILE_H6', + 229: 'SC_P3_HIZ_QUAD_PER_TILE_H7', + 230: 'SC_P3_HIZ_QUAD_PER_TILE_H8', + 231: 'SC_P3_HIZ_QUAD_PER_TILE_H9', + 232: 'SC_P3_HIZ_QUAD_PER_TILE_H10', + 233: 'SC_P3_HIZ_QUAD_PER_TILE_H11', + 234: 'SC_P3_HIZ_QUAD_PER_TILE_H12', + 235: 'SC_P3_HIZ_QUAD_PER_TILE_H13', + 236: 'SC_P3_HIZ_QUAD_PER_TILE_H14', + 237: 'SC_P3_HIZ_QUAD_PER_TILE_H15', + 238: 'SC_P3_HIZ_QUAD_PER_TILE_H16', + 239: 'SC_P0_HIZ_QUAD_COUNT', + 240: 'SC_P1_HIZ_QUAD_COUNT', + 241: 'SC_P2_HIZ_QUAD_COUNT', + 242: 'SC_P3_HIZ_QUAD_COUNT', + 243: 'SC_P0_DETAIL_QUAD_COUNT', + 244: 'SC_P1_DETAIL_QUAD_COUNT', + 245: 'SC_P2_DETAIL_QUAD_COUNT', + 246: 'SC_P3_DETAIL_QUAD_COUNT', + 247: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', + 248: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', + 249: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', + 250: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', + 251: 'SC_P1_DETAIL_QUAD_WITH_1_PIX', + 252: 'SC_P1_DETAIL_QUAD_WITH_2_PIX', + 253: 'SC_P1_DETAIL_QUAD_WITH_3_PIX', + 254: 'SC_P1_DETAIL_QUAD_WITH_4_PIX', + 255: 'SC_P2_DETAIL_QUAD_WITH_1_PIX', + 256: 'SC_P2_DETAIL_QUAD_WITH_2_PIX', + 257: 'SC_P2_DETAIL_QUAD_WITH_3_PIX', + 258: 'SC_P2_DETAIL_QUAD_WITH_4_PIX', + 259: 'SC_P3_DETAIL_QUAD_WITH_1_PIX', + 260: 'SC_P3_DETAIL_QUAD_WITH_2_PIX', + 261: 'SC_P3_DETAIL_QUAD_WITH_3_PIX', + 262: 'SC_P3_DETAIL_QUAD_WITH_4_PIX', + 263: 'SC_EARLYZ_QUAD_COUNT', + 264: 'SC_EARLYZ_QUAD_WITH_1_PIX', + 265: 'SC_EARLYZ_QUAD_WITH_2_PIX', + 266: 'SC_EARLYZ_QUAD_WITH_3_PIX', + 267: 'SC_EARLYZ_QUAD_WITH_4_PIX', + 268: 'SC_PKR_QUAD_PER_ROW_H1', + 269: 'SC_PKR_QUAD_PER_ROW_H2', + 270: 'SC_PKR_4X2_QUAD_SPLIT', + 271: 'SC_PKR_4X2_FILL_QUAD', + 272: 'SC_PKR_END_OF_VECTOR', + 273: 'SC_PKR_CONTROL_XFER', + 274: 'SC_PKR_DBHANG_FORCE_EOV', + 275: 'SC_REG_SCLK_BUSY', + 276: 'SC_GRP0_DYN_SCLK_BUSY', + 277: 'SC_GRP1_DYN_SCLK_BUSY', + 278: 'SC_GRP2_DYN_SCLK_BUSY', + 279: 'SC_GRP3_DYN_SCLK_BUSY', + 280: 'SC_GRP4_DYN_SCLK_BUSY', + 281: 'SC_PA0_SC_DATA_FIFO_RD', + 282: 'SC_PA0_SC_DATA_FIFO_WE', + 283: 'SC_PA1_SC_DATA_FIFO_RD', + 284: 'SC_PA1_SC_DATA_FIFO_WE', + 285: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 286: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', + 287: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 288: 'SC_PS_ARB_STALLED_FROM_BELOW', + 289: 'SC_PS_ARB_STARVED_FROM_ABOVE', + 290: 'SC_PS_ARB_SC_BUSY', + 291: 'SC_PS_ARB_PA_SC_BUSY', + 292: 'SC_PA2_SC_DATA_FIFO_RD', + 293: 'SC_PA2_SC_DATA_FIFO_WE', + 294: 'SC_PA3_SC_DATA_FIFO_RD', + 295: 'SC_PA3_SC_DATA_FIFO_WE', + 296: 'SC_PA_SC_DEALLOC_0_0_WE', + 297: 'SC_PA_SC_DEALLOC_0_1_WE', + 298: 'SC_PA_SC_DEALLOC_1_0_WE', + 299: 'SC_PA_SC_DEALLOC_1_1_WE', + 300: 'SC_PA_SC_DEALLOC_2_0_WE', + 301: 'SC_PA_SC_DEALLOC_2_1_WE', + 302: 'SC_PA_SC_DEALLOC_3_0_WE', + 303: 'SC_PA_SC_DEALLOC_3_1_WE', + 304: 'SC_PA0_SC_EOP_WE', + 305: 'SC_PA0_SC_EOPG_WE', + 306: 'SC_PA0_SC_EVENT_WE', + 307: 'SC_PA1_SC_EOP_WE', + 308: 'SC_PA1_SC_EOPG_WE', + 309: 'SC_PA1_SC_EVENT_WE', + 310: 'SC_PA2_SC_EOP_WE', + 311: 'SC_PA2_SC_EOPG_WE', + 312: 'SC_PA2_SC_EVENT_WE', + 313: 'SC_PA3_SC_EOP_WE', + 314: 'SC_PA3_SC_EOPG_WE', + 315: 'SC_PA3_SC_EVENT_WE', + 316: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', + 317: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', + 318: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', + 319: 'SC_PS_ARB_EOP_POP_SYNC_POP', + 320: 'SC_PS_ARB_EVENT_SYNC_POP', + 321: 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', + 322: 'SC_PA0_SC_FPOV_WE', + 323: 'SC_PA1_SC_FPOV_WE', + 324: 'SC_PA2_SC_FPOV_WE', + 325: 'SC_PA3_SC_FPOV_WE', + 326: 'SC_PA0_SC_LPOV_WE', + 327: 'SC_PA1_SC_LPOV_WE', + 328: 'SC_PA2_SC_LPOV_WE', + 329: 'SC_PA3_SC_LPOV_WE', + 330: 'SC_SC_SPI_DEALLOC_0_0', + 331: 'SC_SC_SPI_DEALLOC_0_1', + 332: 'SC_SC_SPI_DEALLOC_0_2', + 333: 'SC_SC_SPI_DEALLOC_1_0', + 334: 'SC_SC_SPI_DEALLOC_1_1', + 335: 'SC_SC_SPI_DEALLOC_1_2', + 336: 'SC_SC_SPI_DEALLOC_2_0', + 337: 'SC_SC_SPI_DEALLOC_2_1', + 338: 'SC_SC_SPI_DEALLOC_2_2', + 339: 'SC_SC_SPI_DEALLOC_3_0', + 340: 'SC_SC_SPI_DEALLOC_3_1', + 341: 'SC_SC_SPI_DEALLOC_3_2', + 342: 'SC_SC_SPI_FPOV_0', + 343: 'SC_SC_SPI_FPOV_1', + 344: 'SC_SC_SPI_FPOV_2', + 345: 'SC_SC_SPI_FPOV_3', + 346: 'SC_SC_SPI_EVENT', + 347: 'SC_PS_TS_EVENT_FIFO_PUSH', + 348: 'SC_PS_TS_EVENT_FIFO_POP', + 349: 'SC_PS_CTX_DONE_FIFO_PUSH', + 350: 'SC_PS_CTX_DONE_FIFO_POP', + 351: 'SC_MULTICYCLE_BUBBLE_FREEZE', + 352: 'SC_EOP_SYNC_WINDOW', + 353: 'SC_PA0_SC_NULL_WE', + 354: 'SC_PA0_SC_NULL_DEALLOC_WE', + 355: 'SC_PA0_SC_DATA_FIFO_EOPG_RD', + 356: 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 357: 'SC_PA0_SC_DEALLOC_0_RD', + 358: 'SC_PA0_SC_DEALLOC_1_RD', + 359: 'SC_PA1_SC_DATA_FIFO_EOPG_RD', + 360: 'SC_PA1_SC_DATA_FIFO_EOP_RD', + 361: 'SC_PA1_SC_DEALLOC_0_RD', + 362: 'SC_PA1_SC_DEALLOC_1_RD', + 363: 'SC_PA1_SC_NULL_WE', + 364: 'SC_PA1_SC_NULL_DEALLOC_WE', + 365: 'SC_PA2_SC_DATA_FIFO_EOPG_RD', + 366: 'SC_PA2_SC_DATA_FIFO_EOP_RD', + 367: 'SC_PA2_SC_DEALLOC_0_RD', + 368: 'SC_PA2_SC_DEALLOC_1_RD', + 369: 'SC_PA2_SC_NULL_WE', + 370: 'SC_PA2_SC_NULL_DEALLOC_WE', + 371: 'SC_PA3_SC_DATA_FIFO_EOPG_RD', + 372: 'SC_PA3_SC_DATA_FIFO_EOP_RD', + 373: 'SC_PA3_SC_DEALLOC_0_RD', + 374: 'SC_PA3_SC_DEALLOC_1_RD', + 375: 'SC_PA3_SC_NULL_WE', + 376: 'SC_PA3_SC_NULL_DEALLOC_WE', + 377: 'SC_PS_PA0_SC_FIFO_EMPTY', + 378: 'SC_PS_PA0_SC_FIFO_FULL', + 379: 'SC_PA0_PS_DATA_SEND', + 380: 'SC_PS_PA1_SC_FIFO_EMPTY', + 381: 'SC_PS_PA1_SC_FIFO_FULL', + 382: 'SC_PA1_PS_DATA_SEND', + 383: 'SC_PS_PA2_SC_FIFO_EMPTY', + 384: 'SC_PS_PA2_SC_FIFO_FULL', + 385: 'SC_PA2_PS_DATA_SEND', + 386: 'SC_PS_PA3_SC_FIFO_EMPTY', + 387: 'SC_PS_PA3_SC_FIFO_FULL', + 388: 'SC_PA3_PS_DATA_SEND', + 389: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', + 390: 'SC_BUSY_CNT_NOT_ZERO', + 391: 'SC_BM_BUSY', + 392: 'SC_BACKEND_BUSY', + 393: 'SC_SCF_SCB_INTERFACE_BUSY', + 394: 'SC_SCB_BUSY', + 395: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 396: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 397: 'SC_PBB_BIN_HIST_NUM_PRIMS', + 398: 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 399: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 400: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 401: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 402: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 403: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 404: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 405: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 406: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 407: 'SC_PBB_BUSY', + 408: 'SC_PBB_BUSY_AND_RTR', + 409: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 410: 'SC_PBB_NUM_BINS', + 411: 'SC_PBB_END_OF_BIN', + 412: 'SC_PBB_END_OF_BATCH', + 413: 'SC_PBB_PRIMBIN_PROCESSED', + 414: 'SC_PBB_PRIM_ADDED_TO_BATCH', + 415: 'SC_PBB_NONBINNED_PRIM', + 416: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', + 417: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 418: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 419: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 420: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 421: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 422: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 423: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 424: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 425: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 426: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 427: 'SC_POPS_INTRA_WAVE_OVERLAPS', + 428: 'SC_POPS_FORCE_EOV', + 429: 'SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE', + 430: 'SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE', +} +SC_SRPS_WINDOW_VALID = 0 +SC_PSSW_WINDOW_VALID = 1 +SC_TPQZ_WINDOW_VALID = 2 +SC_QZQP_WINDOW_VALID = 3 +SC_TRPK_WINDOW_VALID = 4 +SC_SRPS_WINDOW_VALID_BUSY = 5 +SC_PSSW_WINDOW_VALID_BUSY = 6 +SC_TPQZ_WINDOW_VALID_BUSY = 7 +SC_QZQP_WINDOW_VALID_BUSY = 8 +SC_TRPK_WINDOW_VALID_BUSY = 9 +SC_STARVED_BY_PA = 10 +SC_STALLED_BY_PRIMFIFO = 11 +SC_STALLED_BY_DB_TILE = 12 +SC_STARVED_BY_DB_TILE = 13 +SC_STALLED_BY_TILEORDERFIFO = 14 +SC_STALLED_BY_TILEFIFO = 15 +SC_STALLED_BY_DB_QUAD = 16 +SC_STARVED_BY_DB_QUAD = 17 +SC_STALLED_BY_QUADFIFO = 18 +SC_STALLED_BY_BCI = 19 +SC_STALLED_BY_SPI = 20 +SC_SCISSOR_DISCARD = 21 +SC_BB_DISCARD = 22 +SC_SUPERTILE_COUNT = 23 +SC_SUPERTILE_PER_PRIM_H0 = 24 +SC_SUPERTILE_PER_PRIM_H1 = 25 +SC_SUPERTILE_PER_PRIM_H2 = 26 +SC_SUPERTILE_PER_PRIM_H3 = 27 +SC_SUPERTILE_PER_PRIM_H4 = 28 +SC_SUPERTILE_PER_PRIM_H5 = 29 +SC_SUPERTILE_PER_PRIM_H6 = 30 +SC_SUPERTILE_PER_PRIM_H7 = 31 +SC_SUPERTILE_PER_PRIM_H8 = 32 +SC_SUPERTILE_PER_PRIM_H9 = 33 +SC_SUPERTILE_PER_PRIM_H10 = 34 +SC_SUPERTILE_PER_PRIM_H11 = 35 +SC_SUPERTILE_PER_PRIM_H12 = 36 +SC_SUPERTILE_PER_PRIM_H13 = 37 +SC_SUPERTILE_PER_PRIM_H14 = 38 +SC_SUPERTILE_PER_PRIM_H15 = 39 +SC_SUPERTILE_PER_PRIM_H16 = 40 +SC_TILE_PER_PRIM_H0 = 41 +SC_TILE_PER_PRIM_H1 = 42 +SC_TILE_PER_PRIM_H2 = 43 +SC_TILE_PER_PRIM_H3 = 44 +SC_TILE_PER_PRIM_H4 = 45 +SC_TILE_PER_PRIM_H5 = 46 +SC_TILE_PER_PRIM_H6 = 47 +SC_TILE_PER_PRIM_H7 = 48 +SC_TILE_PER_PRIM_H8 = 49 +SC_TILE_PER_PRIM_H9 = 50 +SC_TILE_PER_PRIM_H10 = 51 +SC_TILE_PER_PRIM_H11 = 52 +SC_TILE_PER_PRIM_H12 = 53 +SC_TILE_PER_PRIM_H13 = 54 +SC_TILE_PER_PRIM_H14 = 55 +SC_TILE_PER_PRIM_H15 = 56 +SC_TILE_PER_PRIM_H16 = 57 +SC_TILE_PER_SUPERTILE_H0 = 58 +SC_TILE_PER_SUPERTILE_H1 = 59 +SC_TILE_PER_SUPERTILE_H2 = 60 +SC_TILE_PER_SUPERTILE_H3 = 61 +SC_TILE_PER_SUPERTILE_H4 = 62 +SC_TILE_PER_SUPERTILE_H5 = 63 +SC_TILE_PER_SUPERTILE_H6 = 64 +SC_TILE_PER_SUPERTILE_H7 = 65 +SC_TILE_PER_SUPERTILE_H8 = 66 +SC_TILE_PER_SUPERTILE_H9 = 67 +SC_TILE_PER_SUPERTILE_H10 = 68 +SC_TILE_PER_SUPERTILE_H11 = 69 +SC_TILE_PER_SUPERTILE_H12 = 70 +SC_TILE_PER_SUPERTILE_H13 = 71 +SC_TILE_PER_SUPERTILE_H14 = 72 +SC_TILE_PER_SUPERTILE_H15 = 73 +SC_TILE_PER_SUPERTILE_H16 = 74 +SC_TILE_PICKED_H1 = 75 +SC_TILE_PICKED_H2 = 76 +SC_TILE_PICKED_H3 = 77 +SC_TILE_PICKED_H4 = 78 +SC_QZ0_MULTI_GPU_TILE_DISCARD = 79 +SC_QZ1_MULTI_GPU_TILE_DISCARD = 80 +SC_QZ2_MULTI_GPU_TILE_DISCARD = 81 +SC_QZ3_MULTI_GPU_TILE_DISCARD = 82 +SC_QZ0_TILE_COUNT = 83 +SC_QZ1_TILE_COUNT = 84 +SC_QZ2_TILE_COUNT = 85 +SC_QZ3_TILE_COUNT = 86 +SC_QZ0_TILE_COVERED_COUNT = 87 +SC_QZ1_TILE_COVERED_COUNT = 88 +SC_QZ2_TILE_COVERED_COUNT = 89 +SC_QZ3_TILE_COVERED_COUNT = 90 +SC_QZ0_TILE_NOT_COVERED_COUNT = 91 +SC_QZ1_TILE_NOT_COVERED_COUNT = 92 +SC_QZ2_TILE_NOT_COVERED_COUNT = 93 +SC_QZ3_TILE_NOT_COVERED_COUNT = 94 +SC_QZ0_QUAD_PER_TILE_H0 = 95 +SC_QZ0_QUAD_PER_TILE_H1 = 96 +SC_QZ0_QUAD_PER_TILE_H2 = 97 +SC_QZ0_QUAD_PER_TILE_H3 = 98 +SC_QZ0_QUAD_PER_TILE_H4 = 99 +SC_QZ0_QUAD_PER_TILE_H5 = 100 +SC_QZ0_QUAD_PER_TILE_H6 = 101 +SC_QZ0_QUAD_PER_TILE_H7 = 102 +SC_QZ0_QUAD_PER_TILE_H8 = 103 +SC_QZ0_QUAD_PER_TILE_H9 = 104 +SC_QZ0_QUAD_PER_TILE_H10 = 105 +SC_QZ0_QUAD_PER_TILE_H11 = 106 +SC_QZ0_QUAD_PER_TILE_H12 = 107 +SC_QZ0_QUAD_PER_TILE_H13 = 108 +SC_QZ0_QUAD_PER_TILE_H14 = 109 +SC_QZ0_QUAD_PER_TILE_H15 = 110 +SC_QZ0_QUAD_PER_TILE_H16 = 111 +SC_QZ1_QUAD_PER_TILE_H0 = 112 +SC_QZ1_QUAD_PER_TILE_H1 = 113 +SC_QZ1_QUAD_PER_TILE_H2 = 114 +SC_QZ1_QUAD_PER_TILE_H3 = 115 +SC_QZ1_QUAD_PER_TILE_H4 = 116 +SC_QZ1_QUAD_PER_TILE_H5 = 117 +SC_QZ1_QUAD_PER_TILE_H6 = 118 +SC_QZ1_QUAD_PER_TILE_H7 = 119 +SC_QZ1_QUAD_PER_TILE_H8 = 120 +SC_QZ1_QUAD_PER_TILE_H9 = 121 +SC_QZ1_QUAD_PER_TILE_H10 = 122 +SC_QZ1_QUAD_PER_TILE_H11 = 123 +SC_QZ1_QUAD_PER_TILE_H12 = 124 +SC_QZ1_QUAD_PER_TILE_H13 = 125 +SC_QZ1_QUAD_PER_TILE_H14 = 126 +SC_QZ1_QUAD_PER_TILE_H15 = 127 +SC_QZ1_QUAD_PER_TILE_H16 = 128 +SC_QZ2_QUAD_PER_TILE_H0 = 129 +SC_QZ2_QUAD_PER_TILE_H1 = 130 +SC_QZ2_QUAD_PER_TILE_H2 = 131 +SC_QZ2_QUAD_PER_TILE_H3 = 132 +SC_QZ2_QUAD_PER_TILE_H4 = 133 +SC_QZ2_QUAD_PER_TILE_H5 = 134 +SC_QZ2_QUAD_PER_TILE_H6 = 135 +SC_QZ2_QUAD_PER_TILE_H7 = 136 +SC_QZ2_QUAD_PER_TILE_H8 = 137 +SC_QZ2_QUAD_PER_TILE_H9 = 138 +SC_QZ2_QUAD_PER_TILE_H10 = 139 +SC_QZ2_QUAD_PER_TILE_H11 = 140 +SC_QZ2_QUAD_PER_TILE_H12 = 141 +SC_QZ2_QUAD_PER_TILE_H13 = 142 +SC_QZ2_QUAD_PER_TILE_H14 = 143 +SC_QZ2_QUAD_PER_TILE_H15 = 144 +SC_QZ2_QUAD_PER_TILE_H16 = 145 +SC_QZ3_QUAD_PER_TILE_H0 = 146 +SC_QZ3_QUAD_PER_TILE_H1 = 147 +SC_QZ3_QUAD_PER_TILE_H2 = 148 +SC_QZ3_QUAD_PER_TILE_H3 = 149 +SC_QZ3_QUAD_PER_TILE_H4 = 150 +SC_QZ3_QUAD_PER_TILE_H5 = 151 +SC_QZ3_QUAD_PER_TILE_H6 = 152 +SC_QZ3_QUAD_PER_TILE_H7 = 153 +SC_QZ3_QUAD_PER_TILE_H8 = 154 +SC_QZ3_QUAD_PER_TILE_H9 = 155 +SC_QZ3_QUAD_PER_TILE_H10 = 156 +SC_QZ3_QUAD_PER_TILE_H11 = 157 +SC_QZ3_QUAD_PER_TILE_H12 = 158 +SC_QZ3_QUAD_PER_TILE_H13 = 159 +SC_QZ3_QUAD_PER_TILE_H14 = 160 +SC_QZ3_QUAD_PER_TILE_H15 = 161 +SC_QZ3_QUAD_PER_TILE_H16 = 162 +SC_QZ0_QUAD_COUNT = 163 +SC_QZ1_QUAD_COUNT = 164 +SC_QZ2_QUAD_COUNT = 165 +SC_QZ3_QUAD_COUNT = 166 +SC_P0_HIZ_TILE_COUNT = 167 +SC_P1_HIZ_TILE_COUNT = 168 +SC_P2_HIZ_TILE_COUNT = 169 +SC_P3_HIZ_TILE_COUNT = 170 +SC_P0_HIZ_QUAD_PER_TILE_H0 = 171 +SC_P0_HIZ_QUAD_PER_TILE_H1 = 172 +SC_P0_HIZ_QUAD_PER_TILE_H2 = 173 +SC_P0_HIZ_QUAD_PER_TILE_H3 = 174 +SC_P0_HIZ_QUAD_PER_TILE_H4 = 175 +SC_P0_HIZ_QUAD_PER_TILE_H5 = 176 +SC_P0_HIZ_QUAD_PER_TILE_H6 = 177 +SC_P0_HIZ_QUAD_PER_TILE_H7 = 178 +SC_P0_HIZ_QUAD_PER_TILE_H8 = 179 +SC_P0_HIZ_QUAD_PER_TILE_H9 = 180 +SC_P0_HIZ_QUAD_PER_TILE_H10 = 181 +SC_P0_HIZ_QUAD_PER_TILE_H11 = 182 +SC_P0_HIZ_QUAD_PER_TILE_H12 = 183 +SC_P0_HIZ_QUAD_PER_TILE_H13 = 184 +SC_P0_HIZ_QUAD_PER_TILE_H14 = 185 +SC_P0_HIZ_QUAD_PER_TILE_H15 = 186 +SC_P0_HIZ_QUAD_PER_TILE_H16 = 187 +SC_P1_HIZ_QUAD_PER_TILE_H0 = 188 +SC_P1_HIZ_QUAD_PER_TILE_H1 = 189 +SC_P1_HIZ_QUAD_PER_TILE_H2 = 190 +SC_P1_HIZ_QUAD_PER_TILE_H3 = 191 +SC_P1_HIZ_QUAD_PER_TILE_H4 = 192 +SC_P1_HIZ_QUAD_PER_TILE_H5 = 193 +SC_P1_HIZ_QUAD_PER_TILE_H6 = 194 +SC_P1_HIZ_QUAD_PER_TILE_H7 = 195 +SC_P1_HIZ_QUAD_PER_TILE_H8 = 196 +SC_P1_HIZ_QUAD_PER_TILE_H9 = 197 +SC_P1_HIZ_QUAD_PER_TILE_H10 = 198 +SC_P1_HIZ_QUAD_PER_TILE_H11 = 199 +SC_P1_HIZ_QUAD_PER_TILE_H12 = 200 +SC_P1_HIZ_QUAD_PER_TILE_H13 = 201 +SC_P1_HIZ_QUAD_PER_TILE_H14 = 202 +SC_P1_HIZ_QUAD_PER_TILE_H15 = 203 +SC_P1_HIZ_QUAD_PER_TILE_H16 = 204 +SC_P2_HIZ_QUAD_PER_TILE_H0 = 205 +SC_P2_HIZ_QUAD_PER_TILE_H1 = 206 +SC_P2_HIZ_QUAD_PER_TILE_H2 = 207 +SC_P2_HIZ_QUAD_PER_TILE_H3 = 208 +SC_P2_HIZ_QUAD_PER_TILE_H4 = 209 +SC_P2_HIZ_QUAD_PER_TILE_H5 = 210 +SC_P2_HIZ_QUAD_PER_TILE_H6 = 211 +SC_P2_HIZ_QUAD_PER_TILE_H7 = 212 +SC_P2_HIZ_QUAD_PER_TILE_H8 = 213 +SC_P2_HIZ_QUAD_PER_TILE_H9 = 214 +SC_P2_HIZ_QUAD_PER_TILE_H10 = 215 +SC_P2_HIZ_QUAD_PER_TILE_H11 = 216 +SC_P2_HIZ_QUAD_PER_TILE_H12 = 217 +SC_P2_HIZ_QUAD_PER_TILE_H13 = 218 +SC_P2_HIZ_QUAD_PER_TILE_H14 = 219 +SC_P2_HIZ_QUAD_PER_TILE_H15 = 220 +SC_P2_HIZ_QUAD_PER_TILE_H16 = 221 +SC_P3_HIZ_QUAD_PER_TILE_H0 = 222 +SC_P3_HIZ_QUAD_PER_TILE_H1 = 223 +SC_P3_HIZ_QUAD_PER_TILE_H2 = 224 +SC_P3_HIZ_QUAD_PER_TILE_H3 = 225 +SC_P3_HIZ_QUAD_PER_TILE_H4 = 226 +SC_P3_HIZ_QUAD_PER_TILE_H5 = 227 +SC_P3_HIZ_QUAD_PER_TILE_H6 = 228 +SC_P3_HIZ_QUAD_PER_TILE_H7 = 229 +SC_P3_HIZ_QUAD_PER_TILE_H8 = 230 +SC_P3_HIZ_QUAD_PER_TILE_H9 = 231 +SC_P3_HIZ_QUAD_PER_TILE_H10 = 232 +SC_P3_HIZ_QUAD_PER_TILE_H11 = 233 +SC_P3_HIZ_QUAD_PER_TILE_H12 = 234 +SC_P3_HIZ_QUAD_PER_TILE_H13 = 235 +SC_P3_HIZ_QUAD_PER_TILE_H14 = 236 +SC_P3_HIZ_QUAD_PER_TILE_H15 = 237 +SC_P3_HIZ_QUAD_PER_TILE_H16 = 238 +SC_P0_HIZ_QUAD_COUNT = 239 +SC_P1_HIZ_QUAD_COUNT = 240 +SC_P2_HIZ_QUAD_COUNT = 241 +SC_P3_HIZ_QUAD_COUNT = 242 +SC_P0_DETAIL_QUAD_COUNT = 243 +SC_P1_DETAIL_QUAD_COUNT = 244 +SC_P2_DETAIL_QUAD_COUNT = 245 +SC_P3_DETAIL_QUAD_COUNT = 246 +SC_P0_DETAIL_QUAD_WITH_1_PIX = 247 +SC_P0_DETAIL_QUAD_WITH_2_PIX = 248 +SC_P0_DETAIL_QUAD_WITH_3_PIX = 249 +SC_P0_DETAIL_QUAD_WITH_4_PIX = 250 +SC_P1_DETAIL_QUAD_WITH_1_PIX = 251 +SC_P1_DETAIL_QUAD_WITH_2_PIX = 252 +SC_P1_DETAIL_QUAD_WITH_3_PIX = 253 +SC_P1_DETAIL_QUAD_WITH_4_PIX = 254 +SC_P2_DETAIL_QUAD_WITH_1_PIX = 255 +SC_P2_DETAIL_QUAD_WITH_2_PIX = 256 +SC_P2_DETAIL_QUAD_WITH_3_PIX = 257 +SC_P2_DETAIL_QUAD_WITH_4_PIX = 258 +SC_P3_DETAIL_QUAD_WITH_1_PIX = 259 +SC_P3_DETAIL_QUAD_WITH_2_PIX = 260 +SC_P3_DETAIL_QUAD_WITH_3_PIX = 261 +SC_P3_DETAIL_QUAD_WITH_4_PIX = 262 +SC_EARLYZ_QUAD_COUNT = 263 +SC_EARLYZ_QUAD_WITH_1_PIX = 264 +SC_EARLYZ_QUAD_WITH_2_PIX = 265 +SC_EARLYZ_QUAD_WITH_3_PIX = 266 +SC_EARLYZ_QUAD_WITH_4_PIX = 267 +SC_PKR_QUAD_PER_ROW_H1 = 268 +SC_PKR_QUAD_PER_ROW_H2 = 269 +SC_PKR_4X2_QUAD_SPLIT = 270 +SC_PKR_4X2_FILL_QUAD = 271 +SC_PKR_END_OF_VECTOR = 272 +SC_PKR_CONTROL_XFER = 273 +SC_PKR_DBHANG_FORCE_EOV = 274 +SC_REG_SCLK_BUSY = 275 +SC_GRP0_DYN_SCLK_BUSY = 276 +SC_GRP1_DYN_SCLK_BUSY = 277 +SC_GRP2_DYN_SCLK_BUSY = 278 +SC_GRP3_DYN_SCLK_BUSY = 279 +SC_GRP4_DYN_SCLK_BUSY = 280 +SC_PA0_SC_DATA_FIFO_RD = 281 +SC_PA0_SC_DATA_FIFO_WE = 282 +SC_PA1_SC_DATA_FIFO_RD = 283 +SC_PA1_SC_DATA_FIFO_WE = 284 +SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 285 +SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 286 +SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 287 +SC_PS_ARB_STALLED_FROM_BELOW = 288 +SC_PS_ARB_STARVED_FROM_ABOVE = 289 +SC_PS_ARB_SC_BUSY = 290 +SC_PS_ARB_PA_SC_BUSY = 291 +SC_PA2_SC_DATA_FIFO_RD = 292 +SC_PA2_SC_DATA_FIFO_WE = 293 +SC_PA3_SC_DATA_FIFO_RD = 294 +SC_PA3_SC_DATA_FIFO_WE = 295 +SC_PA_SC_DEALLOC_0_0_WE = 296 +SC_PA_SC_DEALLOC_0_1_WE = 297 +SC_PA_SC_DEALLOC_1_0_WE = 298 +SC_PA_SC_DEALLOC_1_1_WE = 299 +SC_PA_SC_DEALLOC_2_0_WE = 300 +SC_PA_SC_DEALLOC_2_1_WE = 301 +SC_PA_SC_DEALLOC_3_0_WE = 302 +SC_PA_SC_DEALLOC_3_1_WE = 303 +SC_PA0_SC_EOP_WE = 304 +SC_PA0_SC_EOPG_WE = 305 +SC_PA0_SC_EVENT_WE = 306 +SC_PA1_SC_EOP_WE = 307 +SC_PA1_SC_EOPG_WE = 308 +SC_PA1_SC_EVENT_WE = 309 +SC_PA2_SC_EOP_WE = 310 +SC_PA2_SC_EOPG_WE = 311 +SC_PA2_SC_EVENT_WE = 312 +SC_PA3_SC_EOP_WE = 313 +SC_PA3_SC_EOPG_WE = 314 +SC_PA3_SC_EVENT_WE = 315 +SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 316 +SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 317 +SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 318 +SC_PS_ARB_EOP_POP_SYNC_POP = 319 +SC_PS_ARB_EVENT_SYNC_POP = 320 +SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 321 +SC_PA0_SC_FPOV_WE = 322 +SC_PA1_SC_FPOV_WE = 323 +SC_PA2_SC_FPOV_WE = 324 +SC_PA3_SC_FPOV_WE = 325 +SC_PA0_SC_LPOV_WE = 326 +SC_PA1_SC_LPOV_WE = 327 +SC_PA2_SC_LPOV_WE = 328 +SC_PA3_SC_LPOV_WE = 329 +SC_SC_SPI_DEALLOC_0_0 = 330 +SC_SC_SPI_DEALLOC_0_1 = 331 +SC_SC_SPI_DEALLOC_0_2 = 332 +SC_SC_SPI_DEALLOC_1_0 = 333 +SC_SC_SPI_DEALLOC_1_1 = 334 +SC_SC_SPI_DEALLOC_1_2 = 335 +SC_SC_SPI_DEALLOC_2_0 = 336 +SC_SC_SPI_DEALLOC_2_1 = 337 +SC_SC_SPI_DEALLOC_2_2 = 338 +SC_SC_SPI_DEALLOC_3_0 = 339 +SC_SC_SPI_DEALLOC_3_1 = 340 +SC_SC_SPI_DEALLOC_3_2 = 341 +SC_SC_SPI_FPOV_0 = 342 +SC_SC_SPI_FPOV_1 = 343 +SC_SC_SPI_FPOV_2 = 344 +SC_SC_SPI_FPOV_3 = 345 +SC_SC_SPI_EVENT = 346 +SC_PS_TS_EVENT_FIFO_PUSH = 347 +SC_PS_TS_EVENT_FIFO_POP = 348 +SC_PS_CTX_DONE_FIFO_PUSH = 349 +SC_PS_CTX_DONE_FIFO_POP = 350 +SC_MULTICYCLE_BUBBLE_FREEZE = 351 +SC_EOP_SYNC_WINDOW = 352 +SC_PA0_SC_NULL_WE = 353 +SC_PA0_SC_NULL_DEALLOC_WE = 354 +SC_PA0_SC_DATA_FIFO_EOPG_RD = 355 +SC_PA0_SC_DATA_FIFO_EOP_RD = 356 +SC_PA0_SC_DEALLOC_0_RD = 357 +SC_PA0_SC_DEALLOC_1_RD = 358 +SC_PA1_SC_DATA_FIFO_EOPG_RD = 359 +SC_PA1_SC_DATA_FIFO_EOP_RD = 360 +SC_PA1_SC_DEALLOC_0_RD = 361 +SC_PA1_SC_DEALLOC_1_RD = 362 +SC_PA1_SC_NULL_WE = 363 +SC_PA1_SC_NULL_DEALLOC_WE = 364 +SC_PA2_SC_DATA_FIFO_EOPG_RD = 365 +SC_PA2_SC_DATA_FIFO_EOP_RD = 366 +SC_PA2_SC_DEALLOC_0_RD = 367 +SC_PA2_SC_DEALLOC_1_RD = 368 +SC_PA2_SC_NULL_WE = 369 +SC_PA2_SC_NULL_DEALLOC_WE = 370 +SC_PA3_SC_DATA_FIFO_EOPG_RD = 371 +SC_PA3_SC_DATA_FIFO_EOP_RD = 372 +SC_PA3_SC_DEALLOC_0_RD = 373 +SC_PA3_SC_DEALLOC_1_RD = 374 +SC_PA3_SC_NULL_WE = 375 +SC_PA3_SC_NULL_DEALLOC_WE = 376 +SC_PS_PA0_SC_FIFO_EMPTY = 377 +SC_PS_PA0_SC_FIFO_FULL = 378 +SC_PA0_PS_DATA_SEND = 379 +SC_PS_PA1_SC_FIFO_EMPTY = 380 +SC_PS_PA1_SC_FIFO_FULL = 381 +SC_PA1_PS_DATA_SEND = 382 +SC_PS_PA2_SC_FIFO_EMPTY = 383 +SC_PS_PA2_SC_FIFO_FULL = 384 +SC_PA2_PS_DATA_SEND = 385 +SC_PS_PA3_SC_FIFO_EMPTY = 386 +SC_PS_PA3_SC_FIFO_FULL = 387 +SC_PA3_PS_DATA_SEND = 388 +SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 389 +SC_BUSY_CNT_NOT_ZERO = 390 +SC_BM_BUSY = 391 +SC_BACKEND_BUSY = 392 +SC_SCF_SCB_INTERFACE_BUSY = 393 +SC_SCB_BUSY = 394 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 395 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 396 +SC_PBB_BIN_HIST_NUM_PRIMS = 397 +SC_PBB_BATCH_HIST_NUM_PRIMS = 398 +SC_PBB_BIN_HIST_NUM_CONTEXTS = 399 +SC_PBB_BATCH_HIST_NUM_CONTEXTS = 400 +SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 401 +SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 402 +SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 403 +SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 404 +SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 405 +SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 406 +SC_PBB_BUSY = 407 +SC_PBB_BUSY_AND_RTR = 408 +SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 409 +SC_PBB_NUM_BINS = 410 +SC_PBB_END_OF_BIN = 411 +SC_PBB_END_OF_BATCH = 412 +SC_PBB_PRIMBIN_PROCESSED = 413 +SC_PBB_PRIM_ADDED_TO_BATCH = 414 +SC_PBB_NONBINNED_PRIM = 415 +SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 416 +SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 417 +SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 418 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 419 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 420 +SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 421 +SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 422 +SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 423 +SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 424 +SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 425 +SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 426 +SC_POPS_INTRA_WAVE_OVERLAPS = 427 +SC_POPS_FORCE_EOV = 428 +SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE = 429 +SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE = 430 +SC_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SePairXsel' +SePairXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', + 4: 'RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 +RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE = 4 +SePairXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SePairYsel' +SePairYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', + 4: 'RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 +RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE = 4 +SePairYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SePairMap' +SePairMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', + 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', + 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', + 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', +} +RASTER_CONFIG_SE_PAIR_MAP_0 = 0 +RASTER_CONFIG_SE_PAIR_MAP_1 = 1 +RASTER_CONFIG_SE_PAIR_MAP_2 = 2 +RASTER_CONFIG_SE_PAIR_MAP_3 = 3 +SePairMap = ctypes.c_uint32 # enum + +# values for enumeration 'SeXsel' +SeXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', + 4: 'RASTER_CONFIG_SE_XSEL_128_WIDE_TILE', +} +RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 +RASTER_CONFIG_SE_XSEL_128_WIDE_TILE = 4 +SeXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeYsel' +SeYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', + 4: 'RASTER_CONFIG_SE_YSEL_128_WIDE_TILE', +} +RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 +RASTER_CONFIG_SE_YSEL_128_WIDE_TILE = 4 +SeYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeMap' +SeMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_MAP_0', + 1: 'RASTER_CONFIG_SE_MAP_1', + 2: 'RASTER_CONFIG_SE_MAP_2', + 3: 'RASTER_CONFIG_SE_MAP_3', +} +RASTER_CONFIG_SE_MAP_0 = 0 +RASTER_CONFIG_SE_MAP_1 = 1 +RASTER_CONFIG_SE_MAP_2 = 2 +RASTER_CONFIG_SE_MAP_3 = 3 +SeMap = ctypes.c_uint32 # enum + +# values for enumeration 'ScXsel' +ScXsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 +ScXsel = ctypes.c_uint32 # enum + +# values for enumeration 'ScYsel' +ScYsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 +ScYsel = ctypes.c_uint32 # enum + +# values for enumeration 'ScMap' +ScMap__enumvalues = { + 0: 'RASTER_CONFIG_SC_MAP_0', + 1: 'RASTER_CONFIG_SC_MAP_1', + 2: 'RASTER_CONFIG_SC_MAP_2', + 3: 'RASTER_CONFIG_SC_MAP_3', +} +RASTER_CONFIG_SC_MAP_0 = 0 +RASTER_CONFIG_SC_MAP_1 = 1 +RASTER_CONFIG_SC_MAP_2 = 2 +RASTER_CONFIG_SC_MAP_3 = 3 +ScMap = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel2' +PkrXsel2__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL2_0', + 1: 'RASTER_CONFIG_PKR_XSEL2_1', + 2: 'RASTER_CONFIG_PKR_XSEL2_2', + 3: 'RASTER_CONFIG_PKR_XSEL2_3', +} +RASTER_CONFIG_PKR_XSEL2_0 = 0 +RASTER_CONFIG_PKR_XSEL2_1 = 1 +RASTER_CONFIG_PKR_XSEL2_2 = 2 +RASTER_CONFIG_PKR_XSEL2_3 = 3 +PkrXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel' +PkrXsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL_0', + 1: 'RASTER_CONFIG_PKR_XSEL_1', + 2: 'RASTER_CONFIG_PKR_XSEL_2', + 3: 'RASTER_CONFIG_PKR_XSEL_3', +} +RASTER_CONFIG_PKR_XSEL_0 = 0 +RASTER_CONFIG_PKR_XSEL_1 = 1 +RASTER_CONFIG_PKR_XSEL_2 = 2 +RASTER_CONFIG_PKR_XSEL_3 = 3 +PkrXsel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrYsel' +PkrYsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_YSEL_0', + 1: 'RASTER_CONFIG_PKR_YSEL_1', + 2: 'RASTER_CONFIG_PKR_YSEL_2', + 3: 'RASTER_CONFIG_PKR_YSEL_3', +} +RASTER_CONFIG_PKR_YSEL_0 = 0 +RASTER_CONFIG_PKR_YSEL_1 = 1 +RASTER_CONFIG_PKR_YSEL_2 = 2 +RASTER_CONFIG_PKR_YSEL_3 = 3 +PkrYsel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrMap' +PkrMap__enumvalues = { + 0: 'RASTER_CONFIG_PKR_MAP_0', + 1: 'RASTER_CONFIG_PKR_MAP_1', + 2: 'RASTER_CONFIG_PKR_MAP_2', + 3: 'RASTER_CONFIG_PKR_MAP_3', +} +RASTER_CONFIG_PKR_MAP_0 = 0 +RASTER_CONFIG_PKR_MAP_1 = 1 +RASTER_CONFIG_PKR_MAP_2 = 2 +RASTER_CONFIG_PKR_MAP_3 = 3 +PkrMap = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel' +RbXsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL_0', + 1: 'RASTER_CONFIG_RB_XSEL_1', +} +RASTER_CONFIG_RB_XSEL_0 = 0 +RASTER_CONFIG_RB_XSEL_1 = 1 +RbXsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbYsel' +RbYsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_YSEL_0', + 1: 'RASTER_CONFIG_RB_YSEL_1', +} +RASTER_CONFIG_RB_YSEL_0 = 0 +RASTER_CONFIG_RB_YSEL_1 = 1 +RbYsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel2' +RbXsel2__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL2_0', + 1: 'RASTER_CONFIG_RB_XSEL2_1', + 2: 'RASTER_CONFIG_RB_XSEL2_2', + 3: 'RASTER_CONFIG_RB_XSEL2_3', +} +RASTER_CONFIG_RB_XSEL2_0 = 0 +RASTER_CONFIG_RB_XSEL2_1 = 1 +RASTER_CONFIG_RB_XSEL2_2 = 2 +RASTER_CONFIG_RB_XSEL2_3 = 3 +RbXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'RbMap' +RbMap__enumvalues = { + 0: 'RASTER_CONFIG_RB_MAP_0', + 1: 'RASTER_CONFIG_RB_MAP_1', + 2: 'RASTER_CONFIG_RB_MAP_2', + 3: 'RASTER_CONFIG_RB_MAP_3', +} +RASTER_CONFIG_RB_MAP_0 = 0 +RASTER_CONFIG_RB_MAP_1 = 1 +RASTER_CONFIG_RB_MAP_2 = 2 +RASTER_CONFIG_RB_MAP_3 = 3 +RbMap = ctypes.c_uint32 # enum + +# values for enumeration 'BinningMode' +BinningMode__enumvalues = { + 0: 'BINNING_ALLOWED', + 1: 'FORCE_BINNING_ON', + 2: 'DISABLE_BINNING_USE_NEW_SC', + 3: 'DISABLE_BINNING_USE_LEGACY_SC', +} +BINNING_ALLOWED = 0 +FORCE_BINNING_ON = 1 +DISABLE_BINNING_USE_NEW_SC = 2 +DISABLE_BINNING_USE_LEGACY_SC = 3 +BinningMode = ctypes.c_uint32 # enum + +# values for enumeration 'BinEventCntl' +BinEventCntl__enumvalues = { + 0: 'BINNER_BREAK_BATCH', + 1: 'BINNER_PIPELINE', + 2: 'BINNER_DROP_ASSERT', +} +BINNER_BREAK_BATCH = 0 +BINNER_PIPELINE = 1 +BINNER_DROP_ASSERT = 2 +BinEventCntl = ctypes.c_uint32 # enum + +# values for enumeration 'CovToShaderSel' +CovToShaderSel__enumvalues = { + 0: 'INPUT_COVERAGE', + 1: 'INPUT_INNER_COVERAGE', + 2: 'INPUT_DEPTH_COVERAGE', + 3: 'RAW', +} +INPUT_COVERAGE = 0 +INPUT_INNER_COVERAGE = 1 +INPUT_DEPTH_COVERAGE = 2 +RAW = 3 +CovToShaderSel = ctypes.c_uint32 # enum + +# values for enumeration 'RMIPerfSel' +RMIPerfSel__enumvalues = { + 0: 'RMI_PERF_SEL_NONE', + 1: 'RMI_PERF_SEL_BUSY', + 2: 'RMI_PERF_SEL_REG_CLK_VLD', + 3: 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', + 4: 'RMI_PERF_SEL_DYN_CLK_RB_VLD', + 5: 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', + 6: 'RMI_PERF_SEL_PERF_WINDOW', + 7: 'RMI_PERF_SEL_EVENT_SEND', + 8: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0', + 9: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1', + 10: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2', + 11: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3', + 12: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4', + 13: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5', + 14: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6', + 15: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7', + 16: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8', + 17: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9', + 18: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10', + 19: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11', + 20: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12', + 21: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13', + 22: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14', + 23: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15', + 24: 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL', + 25: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0', + 26: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1', + 27: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2', + 28: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3', + 29: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4', + 30: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5', + 31: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6', + 32: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7', + 33: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8', + 34: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9', + 35: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10', + 36: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11', + 37: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12', + 38: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13', + 39: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14', + 40: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15', + 41: 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL', + 42: 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS', + 43: 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS', + 44: 'RMI_PERF_SEL_UTCL1_REQUEST', + 45: 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 46: 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 47: 'RMI_PERF_SEL_UTCL1_LFIFO_FULL', + 48: 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 49: 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 50: 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 51: 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL', + 52: 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS', + 53: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', + 54: 'RMI_PERF_SEL_RB_RMI_WRREQ_BUSY', + 55: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', + 56: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', + 57: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', + 58: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', + 59: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', + 60: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', + 61: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', + 62: 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', + 63: 'RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID', + 64: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', + 65: 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', + 66: 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', + 67: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', + 68: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', + 69: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', + 70: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', + 71: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', + 72: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', + 73: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', + 74: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', + 75: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', + 76: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', + 77: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', + 78: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', + 79: 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', + 80: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', + 81: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', + 82: 'RMI_PERF_SEL_RB_RMI_RDREQ_BUSY', + 83: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', + 84: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', + 85: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', + 86: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', + 87: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', + 88: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', + 89: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', + 90: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', + 91: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', + 92: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', + 93: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', + 94: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', + 95: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', + 96: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', + 97: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', + 98: 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', + 99: 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', + 100: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', + 101: 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', + 102: 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', + 103: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', + 104: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', + 105: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', + 106: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', + 107: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', + 108: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', + 109: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', + 110: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', + 111: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', + 112: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', + 113: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', + 114: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', + 115: 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', + 116: 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', + 117: 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', + 118: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', + 119: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', + 120: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', + 121: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', + 122: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', + 123: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', + 124: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', + 125: 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', + 126: 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', + 127: 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', + 128: 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', + 129: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', + 130: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', + 131: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', + 132: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', + 133: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', + 134: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', + 135: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', + 136: 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', + 137: 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', + 138: 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', + 139: 'RMI_PERF_SEL_UTCL1_BUSY', + 140: 'RMI_PERF_SEL_RMI_UTC_REQ', + 141: 'RMI_PERF_SEL_RMI_UTC_BUSY', + 142: 'RMI_PERF_SEL_UTCL1_UTCL2_REQ', + 143: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY', + 144: 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT', + 145: 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT', + 146: 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT', + 147: 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED', + 148: 'RMI_PERF_SEL_LAT_FIFO_NUM_USED', + 149: 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ', + 150: 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ', + 151: 'RMI_PERF_SEL_XNACK_FIFO_FULL', + 152: 'RMI_PERF_SEL_XNACK_FIFO_BUSY', + 153: 'RMI_PERF_SEL_LAT_FIFO_FULL', + 154: 'RMI_PERF_SEL_SKID_FIFO_DEPTH', + 155: 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', + 156: 'RMI_PERF_SEL_PRT_FIFO_NUM_USED', + 157: 'RMI_PERF_SEL_PRT_FIFO_REQ', + 158: 'RMI_PERF_SEL_PRT_FIFO_BUSY', + 159: 'RMI_PERF_SEL_TCIW_REQ', + 160: 'RMI_PERF_SEL_TCIW_BUSY', + 161: 'RMI_PERF_SEL_SKID_FIFO_REQ', + 162: 'RMI_PERF_SEL_SKID_FIFO_BUSY', + 163: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0', + 164: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1', + 165: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2', + 166: 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3', + 167: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR', + 168: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR', + 169: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB', + 170: 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB', + 171: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', + 172: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', + 173: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', + 174: 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', + 175: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR', + 176: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR', + 177: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB', + 178: 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB', + 179: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR', + 180: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR', + 181: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB', + 182: 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB', + 183: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR', + 184: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR', + 185: 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB', + 186: 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB', + 187: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR', + 188: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR', + 189: 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB', + 190: 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB', + 191: 'RMI_PERF_SEL_UTC_POP_RTS_RTR', + 192: 'RMI_PERF_SEL_UTC_POP_RTSB_RTR', + 193: 'RMI_PERF_SEL_UTC_POP_RTS_RTRB', + 194: 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', + 195: 'RMI_PERF_SEL_POP_XNACK_RTS_RTR', + 196: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR', + 197: 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB', + 198: 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB', + 199: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR', + 200: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR', + 201: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', + 202: 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB', + 203: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR', + 204: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR', + 205: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB', + 206: 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB', + 207: 'RMI_PERF_SEL_SKID_FIFO_IN_RTS', + 208: 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB', + 209: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS', + 210: 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', + 211: 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR', + 212: 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR', + 213: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR', + 214: 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR', + 215: 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR', + 216: 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR', + 217: 'RMI_PERF_SEL_REORDER_FIFO_REQ', + 218: 'RMI_PERF_SEL_REORDER_FIFO_BUSY', + 219: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', + 220: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', + 221: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', + 222: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', + 223: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', + 224: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', + 225: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', + 226: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', + 227: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', + 228: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0', + 229: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1', + 230: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2', + 231: 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3', +} +RMI_PERF_SEL_NONE = 0 +RMI_PERF_SEL_BUSY = 1 +RMI_PERF_SEL_REG_CLK_VLD = 2 +RMI_PERF_SEL_DYN_CLK_CMN_VLD = 3 +RMI_PERF_SEL_DYN_CLK_RB_VLD = 4 +RMI_PERF_SEL_DYN_CLK_PERF_VLD = 5 +RMI_PERF_SEL_PERF_WINDOW = 6 +RMI_PERF_SEL_EVENT_SEND = 7 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 8 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 9 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 10 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 11 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 12 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 13 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 14 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 15 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 16 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 17 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 18 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 19 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 20 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 21 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 22 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 23 +RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 24 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 25 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 26 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 27 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 28 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 29 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 30 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 31 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 32 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 33 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 34 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 35 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 36 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 37 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 38 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 39 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 40 +RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 41 +RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 42 +RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 43 +RMI_PERF_SEL_UTCL1_REQUEST = 44 +RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 45 +RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 46 +RMI_PERF_SEL_UTCL1_LFIFO_FULL = 47 +RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 48 +RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 49 +RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 50 +RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 51 +RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 52 +RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 53 +RMI_PERF_SEL_RB_RMI_WRREQ_BUSY = 54 +RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 55 +RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 56 +RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 57 +RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 58 +RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 59 +RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 60 +RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 61 +RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 62 +RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID = 63 +RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 64 +RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 65 +RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 66 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 67 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 68 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 69 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 70 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 71 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 72 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 73 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 74 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 75 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 76 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 77 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 78 +RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 79 +RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 80 +RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 81 +RMI_PERF_SEL_RB_RMI_RDREQ_BUSY = 82 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 83 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 84 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 85 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 86 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 87 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 88 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 89 +RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 90 +RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 91 +RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 92 +RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 93 +RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 94 +RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 95 +RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 96 +RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 97 +RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 98 +RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 99 +RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 100 +RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 101 +RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 102 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 103 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 104 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 105 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 106 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 107 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 108 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 109 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 110 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 111 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 112 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 113 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 114 +RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 115 +RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 116 +RMI_PERF_SEL_RMI_TC_REQ_BUSY = 117 +RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 118 +RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 119 +RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 120 +RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 121 +RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 122 +RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 123 +RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 124 +RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 125 +RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 126 +RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 127 +RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 128 +RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 129 +RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 130 +RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 131 +RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 132 +RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 133 +RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 134 +RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 135 +RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 136 +RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 137 +RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 138 +RMI_PERF_SEL_UTCL1_BUSY = 139 +RMI_PERF_SEL_RMI_UTC_REQ = 140 +RMI_PERF_SEL_RMI_UTC_BUSY = 141 +RMI_PERF_SEL_UTCL1_UTCL2_REQ = 142 +RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 143 +RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 144 +RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 145 +RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 146 +RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 147 +RMI_PERF_SEL_LAT_FIFO_NUM_USED = 148 +RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 149 +RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 150 +RMI_PERF_SEL_XNACK_FIFO_FULL = 151 +RMI_PERF_SEL_XNACK_FIFO_BUSY = 152 +RMI_PERF_SEL_LAT_FIFO_FULL = 153 +RMI_PERF_SEL_SKID_FIFO_DEPTH = 154 +RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 155 +RMI_PERF_SEL_PRT_FIFO_NUM_USED = 156 +RMI_PERF_SEL_PRT_FIFO_REQ = 157 +RMI_PERF_SEL_PRT_FIFO_BUSY = 158 +RMI_PERF_SEL_TCIW_REQ = 159 +RMI_PERF_SEL_TCIW_BUSY = 160 +RMI_PERF_SEL_SKID_FIFO_REQ = 161 +RMI_PERF_SEL_SKID_FIFO_BUSY = 162 +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 163 +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 164 +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 165 +RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 166 +RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 167 +RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 168 +RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 169 +RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 170 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 171 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 172 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 173 +RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 174 +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 175 +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 176 +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 177 +RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 178 +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 179 +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 180 +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 181 +RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 182 +RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 183 +RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 184 +RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 185 +RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 186 +RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 187 +RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 188 +RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 189 +RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 190 +RMI_PERF_SEL_UTC_POP_RTS_RTR = 191 +RMI_PERF_SEL_UTC_POP_RTSB_RTR = 192 +RMI_PERF_SEL_UTC_POP_RTS_RTRB = 193 +RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 194 +RMI_PERF_SEL_POP_XNACK_RTS_RTR = 195 +RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 196 +RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 197 +RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 198 +RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 199 +RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 200 +RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 201 +RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 202 +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 203 +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 204 +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 205 +RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 206 +RMI_PERF_SEL_SKID_FIFO_IN_RTS = 207 +RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 208 +RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 209 +RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 210 +RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 211 +RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 212 +RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 213 +RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 214 +RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 215 +RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 216 +RMI_PERF_SEL_REORDER_FIFO_REQ = 217 +RMI_PERF_SEL_REORDER_FIFO_BUSY = 218 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 219 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 220 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 221 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 222 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 223 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 224 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 225 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 226 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 227 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 228 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 229 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 230 +RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 231 +RMIPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'IH_PERF_SEL' +IH_PERF_SEL__enumvalues = { + 0: 'IH_PERF_SEL_CYCLE', + 1: 'IH_PERF_SEL_IDLE', + 2: 'IH_PERF_SEL_INPUT_IDLE', + 3: 'IH_PERF_SEL_BUFFER_IDLE', + 4: 'IH_PERF_SEL_RB0_FULL', + 5: 'IH_PERF_SEL_RB0_OVERFLOW', + 6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', + 7: 'IH_PERF_SEL_RB0_WPTR_WRAP', + 8: 'IH_PERF_SEL_RB0_RPTR_WRAP', + 9: 'IH_PERF_SEL_MC_WR_IDLE', + 10: 'IH_PERF_SEL_MC_WR_COUNT', + 11: 'IH_PERF_SEL_MC_WR_STALL', + 12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', + 13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL', + 14: 'IH_PERF_SEL_BIF_LINE0_RISING', + 15: 'IH_PERF_SEL_BIF_LINE0_FALLING', + 16: 'IH_PERF_SEL_RB1_FULL', + 17: 'IH_PERF_SEL_RB1_OVERFLOW', + 18: 'Reserved18', + 19: 'IH_PERF_SEL_RB1_WPTR_WRAP', + 20: 'IH_PERF_SEL_RB1_RPTR_WRAP', + 21: 'IH_PERF_SEL_RB2_FULL', + 22: 'IH_PERF_SEL_RB2_OVERFLOW', + 23: 'Reserved23', + 24: 'IH_PERF_SEL_RB2_WPTR_WRAP', + 25: 'IH_PERF_SEL_RB2_RPTR_WRAP', + 26: 'Reserved26', + 27: 'Reserved27', + 28: 'Reserved28', + 29: 'Reserved29', + 30: 'IH_PERF_SEL_RB0_FULL_VF0', + 31: 'IH_PERF_SEL_RB0_FULL_VF1', + 32: 'IH_PERF_SEL_RB0_FULL_VF2', + 33: 'IH_PERF_SEL_RB0_FULL_VF3', + 34: 'IH_PERF_SEL_RB0_FULL_VF4', + 35: 'IH_PERF_SEL_RB0_FULL_VF5', + 36: 'IH_PERF_SEL_RB0_FULL_VF6', + 37: 'IH_PERF_SEL_RB0_FULL_VF7', + 38: 'IH_PERF_SEL_RB0_FULL_VF8', + 39: 'IH_PERF_SEL_RB0_FULL_VF9', + 40: 'IH_PERF_SEL_RB0_FULL_VF10', + 41: 'IH_PERF_SEL_RB0_FULL_VF11', + 42: 'IH_PERF_SEL_RB0_FULL_VF12', + 43: 'IH_PERF_SEL_RB0_FULL_VF13', + 44: 'IH_PERF_SEL_RB0_FULL_VF14', + 45: 'IH_PERF_SEL_RB0_FULL_VF15', + 46: 'IH_PERF_SEL_RB0_OVERFLOW_VF0', + 47: 'IH_PERF_SEL_RB0_OVERFLOW_VF1', + 48: 'IH_PERF_SEL_RB0_OVERFLOW_VF2', + 49: 'IH_PERF_SEL_RB0_OVERFLOW_VF3', + 50: 'IH_PERF_SEL_RB0_OVERFLOW_VF4', + 51: 'IH_PERF_SEL_RB0_OVERFLOW_VF5', + 52: 'IH_PERF_SEL_RB0_OVERFLOW_VF6', + 53: 'IH_PERF_SEL_RB0_OVERFLOW_VF7', + 54: 'IH_PERF_SEL_RB0_OVERFLOW_VF8', + 55: 'IH_PERF_SEL_RB0_OVERFLOW_VF9', + 56: 'IH_PERF_SEL_RB0_OVERFLOW_VF10', + 57: 'IH_PERF_SEL_RB0_OVERFLOW_VF11', + 58: 'IH_PERF_SEL_RB0_OVERFLOW_VF12', + 59: 'IH_PERF_SEL_RB0_OVERFLOW_VF13', + 60: 'IH_PERF_SEL_RB0_OVERFLOW_VF14', + 61: 'IH_PERF_SEL_RB0_OVERFLOW_VF15', + 62: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', + 63: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', + 64: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', + 65: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', + 66: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', + 67: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', + 68: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', + 69: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', + 70: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', + 71: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', + 72: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', + 73: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', + 74: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', + 75: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', + 76: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', + 77: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', + 78: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', + 79: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', + 80: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', + 81: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', + 82: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', + 83: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', + 84: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', + 85: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', + 86: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', + 87: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', + 88: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', + 89: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', + 90: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', + 91: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', + 92: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', + 93: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', + 94: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', + 95: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', + 96: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', + 97: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', + 98: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', + 99: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', + 100: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', + 101: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', + 102: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', + 103: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', + 104: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', + 105: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', + 106: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', + 107: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', + 108: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', + 109: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', + 110: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', + 111: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', + 112: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', + 113: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', + 114: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', + 115: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', + 116: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', + 117: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', + 118: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', + 119: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', + 120: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', + 121: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', + 122: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', + 123: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', + 124: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', + 125: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', + 126: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', + 127: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', + 128: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', + 129: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', + 130: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', + 131: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', + 132: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', + 133: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', + 134: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', + 135: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', + 136: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', + 137: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', + 138: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', + 139: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', + 140: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', + 141: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', + 142: 'Reserved142', + 143: 'Reserved143', + 144: 'Reserved144', + 145: 'Reserved145', + 146: 'Reserved146', + 147: 'Reserved147', + 148: 'Reserved148', + 149: 'Reserved149', + 150: 'IH_PERF_SEL_CLIENT0_INT', + 151: 'IH_PERF_SEL_CLIENT1_INT', + 152: 'IH_PERF_SEL_CLIENT2_INT', + 153: 'IH_PERF_SEL_CLIENT3_INT', + 154: 'IH_PERF_SEL_CLIENT4_INT', + 155: 'IH_PERF_SEL_CLIENT5_INT', + 156: 'IH_PERF_SEL_CLIENT6_INT', + 157: 'IH_PERF_SEL_CLIENT7_INT', + 158: 'IH_PERF_SEL_CLIENT8_INT', + 159: 'IH_PERF_SEL_CLIENT9_INT', + 160: 'IH_PERF_SEL_CLIENT10_INT', + 161: 'IH_PERF_SEL_CLIENT11_INT', + 162: 'IH_PERF_SEL_CLIENT12_INT', + 163: 'IH_PERF_SEL_CLIENT13_INT', + 164: 'IH_PERF_SEL_CLIENT14_INT', + 165: 'IH_PERF_SEL_CLIENT15_INT', + 166: 'IH_PERF_SEL_CLIENT16_INT', + 167: 'IH_PERF_SEL_CLIENT17_INT', + 168: 'IH_PERF_SEL_CLIENT18_INT', + 169: 'IH_PERF_SEL_CLIENT19_INT', + 170: 'IH_PERF_SEL_CLIENT20_INT', + 171: 'IH_PERF_SEL_CLIENT21_INT', + 172: 'IH_PERF_SEL_CLIENT22_INT', + 173: 'IH_PERF_SEL_CLIENT23_INT', + 174: 'IH_PERF_SEL_CLIENT24_INT', + 175: 'IH_PERF_SEL_CLIENT25_INT', + 176: 'IH_PERF_SEL_CLIENT26_INT', + 177: 'IH_PERF_SEL_CLIENT27_INT', + 178: 'IH_PERF_SEL_CLIENT28_INT', + 179: 'IH_PERF_SEL_CLIENT29_INT', + 180: 'IH_PERF_SEL_CLIENT30_INT', + 181: 'IH_PERF_SEL_CLIENT31_INT', + 182: 'Reserved182', + 183: 'Reserved183', + 184: 'Reserved184', + 185: 'Reserved185', + 186: 'Reserved186', + 187: 'Reserved187', + 188: 'Reserved188', + 189: 'Reserved189', + 190: 'Reserved190', + 191: 'Reserved191', + 192: 'Reserved192', + 193: 'Reserved193', + 194: 'Reserved194', + 195: 'Reserved195', + 196: 'Reserved196', + 197: 'Reserved197', + 198: 'Reserved198', + 199: 'Reserved199', + 200: 'Reserved200', + 201: 'Reserved201', + 202: 'Reserved202', + 203: 'Reserved203', + 204: 'Reserved204', + 205: 'Reserved205', + 206: 'Reserved206', + 207: 'Reserved207', + 208: 'Reserved208', + 209: 'Reserved209', + 210: 'Reserved210', + 211: 'Reserved211', + 212: 'Reserved212', + 213: 'Reserved213', + 214: 'Reserved214', + 215: 'Reserved215', + 216: 'Reserved216', + 217: 'Reserved217', + 218: 'Reserved218', + 219: 'Reserved219', + 220: 'IH_PERF_SEL_RB1_FULL_VF0', + 221: 'IH_PERF_SEL_RB1_FULL_VF1', + 222: 'IH_PERF_SEL_RB1_FULL_VF2', + 223: 'IH_PERF_SEL_RB1_FULL_VF3', + 224: 'IH_PERF_SEL_RB1_FULL_VF4', + 225: 'IH_PERF_SEL_RB1_FULL_VF5', + 226: 'IH_PERF_SEL_RB1_FULL_VF6', + 227: 'IH_PERF_SEL_RB1_FULL_VF7', + 228: 'IH_PERF_SEL_RB1_FULL_VF8', + 229: 'IH_PERF_SEL_RB1_FULL_VF9', + 230: 'IH_PERF_SEL_RB1_FULL_VF10', + 231: 'IH_PERF_SEL_RB1_FULL_VF11', + 232: 'IH_PERF_SEL_RB1_FULL_VF12', + 233: 'IH_PERF_SEL_RB1_FULL_VF13', + 234: 'IH_PERF_SEL_RB1_FULL_VF14', + 235: 'IH_PERF_SEL_RB1_FULL_VF15', + 236: 'IH_PERF_SEL_RB1_OVERFLOW_VF0', + 237: 'IH_PERF_SEL_RB1_OVERFLOW_VF1', + 238: 'IH_PERF_SEL_RB1_OVERFLOW_VF2', + 239: 'IH_PERF_SEL_RB1_OVERFLOW_VF3', + 240: 'IH_PERF_SEL_RB1_OVERFLOW_VF4', + 241: 'IH_PERF_SEL_RB1_OVERFLOW_VF5', + 242: 'IH_PERF_SEL_RB1_OVERFLOW_VF6', + 243: 'IH_PERF_SEL_RB1_OVERFLOW_VF7', + 244: 'IH_PERF_SEL_RB1_OVERFLOW_VF8', + 245: 'IH_PERF_SEL_RB1_OVERFLOW_VF9', + 246: 'IH_PERF_SEL_RB1_OVERFLOW_VF10', + 247: 'IH_PERF_SEL_RB1_OVERFLOW_VF11', + 248: 'IH_PERF_SEL_RB1_OVERFLOW_VF12', + 249: 'IH_PERF_SEL_RB1_OVERFLOW_VF13', + 250: 'IH_PERF_SEL_RB1_OVERFLOW_VF14', + 251: 'IH_PERF_SEL_RB1_OVERFLOW_VF15', + 252: 'Reserved252', + 253: 'Reserved253', + 254: 'Reserved254', + 255: 'Reserved255', + 256: 'Reserved256', + 257: 'Reserved257', + 258: 'Reserved258', + 259: 'Reserved259', + 260: 'Reserved260', + 261: 'Reserved261', + 262: 'Reserved262', + 263: 'Reserved263', + 264: 'Reserved264', + 265: 'Reserved265', + 266: 'Reserved266', + 267: 'Reserved267', + 268: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', + 269: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', + 270: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', + 271: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', + 272: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', + 273: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', + 274: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', + 275: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', + 276: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', + 277: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', + 278: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', + 279: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', + 280: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', + 281: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', + 282: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', + 283: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', + 284: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', + 285: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', + 286: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', + 287: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', + 288: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', + 289: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', + 290: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', + 291: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', + 292: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', + 293: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', + 294: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', + 295: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', + 296: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', + 297: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', + 298: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', + 299: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', + 300: 'Reserved300', + 301: 'Reserved301', + 302: 'Reserved302', + 303: 'Reserved303', + 304: 'Reserved304', + 305: 'Reserved305', + 306: 'Reserved306', + 307: 'Reserved307', + 308: 'Reserved308', + 309: 'Reserved309', + 310: 'Reserved310', + 311: 'Reserved311', + 312: 'Reserved312', + 313: 'Reserved313', + 314: 'Reserved314', + 315: 'Reserved315', + 316: 'Reserved316', + 317: 'Reserved317', + 318: 'Reserved318', + 319: 'Reserved319', + 320: 'Reserved320', + 321: 'Reserved321', + 322: 'Reserved322', + 323: 'Reserved323', + 324: 'Reserved324', + 325: 'Reserved325', + 326: 'Reserved326', + 327: 'Reserved327', + 328: 'Reserved328', + 329: 'Reserved329', + 330: 'Reserved330', + 331: 'Reserved331', + 332: 'IH_PERF_SEL_RB2_FULL_VF0', + 333: 'IH_PERF_SEL_RB2_FULL_VF1', + 334: 'IH_PERF_SEL_RB2_FULL_VF2', + 335: 'IH_PERF_SEL_RB2_FULL_VF3', + 336: 'IH_PERF_SEL_RB2_FULL_VF4', + 337: 'IH_PERF_SEL_RB2_FULL_VF5', + 338: 'IH_PERF_SEL_RB2_FULL_VF6', + 339: 'IH_PERF_SEL_RB2_FULL_VF7', + 340: 'IH_PERF_SEL_RB2_FULL_VF8', + 341: 'IH_PERF_SEL_RB2_FULL_VF9', + 342: 'IH_PERF_SEL_RB2_FULL_VF10', + 343: 'IH_PERF_SEL_RB2_FULL_VF11', + 344: 'IH_PERF_SEL_RB2_FULL_VF12', + 345: 'IH_PERF_SEL_RB2_FULL_VF13', + 346: 'IH_PERF_SEL_RB2_FULL_VF14', + 347: 'IH_PERF_SEL_RB2_FULL_VF15', + 348: 'IH_PERF_SEL_RB2_OVERFLOW_VF0', + 349: 'IH_PERF_SEL_RB2_OVERFLOW_VF1', + 350: 'IH_PERF_SEL_RB2_OVERFLOW_VF2', + 351: 'IH_PERF_SEL_RB2_OVERFLOW_VF3', + 352: 'IH_PERF_SEL_RB2_OVERFLOW_VF4', + 353: 'IH_PERF_SEL_RB2_OVERFLOW_VF5', + 354: 'IH_PERF_SEL_RB2_OVERFLOW_VF6', + 355: 'IH_PERF_SEL_RB2_OVERFLOW_VF7', + 356: 'IH_PERF_SEL_RB2_OVERFLOW_VF8', + 357: 'IH_PERF_SEL_RB2_OVERFLOW_VF9', + 358: 'IH_PERF_SEL_RB2_OVERFLOW_VF10', + 359: 'IH_PERF_SEL_RB2_OVERFLOW_VF11', + 360: 'IH_PERF_SEL_RB2_OVERFLOW_VF12', + 361: 'IH_PERF_SEL_RB2_OVERFLOW_VF13', + 362: 'IH_PERF_SEL_RB2_OVERFLOW_VF14', + 363: 'IH_PERF_SEL_RB2_OVERFLOW_VF15', + 364: 'Reserved364', + 365: 'Reserved365', + 366: 'Reserved366', + 367: 'Reserved367', + 368: 'Reserved368', + 369: 'Reserved369', + 370: 'Reserved370', + 371: 'Reserved371', + 372: 'Reserved372', + 373: 'Reserved373', + 374: 'Reserved374', + 375: 'Reserved375', + 376: 'Reserved376', + 377: 'Reserved377', + 378: 'Reserved378', + 379: 'Reserved379', + 380: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', + 381: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', + 382: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', + 383: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', + 384: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', + 385: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', + 386: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', + 387: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', + 388: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', + 389: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', + 390: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', + 391: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', + 392: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', + 393: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', + 394: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', + 395: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', + 396: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', + 397: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', + 398: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', + 399: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', + 400: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', + 401: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', + 402: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', + 403: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', + 404: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', + 405: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', + 406: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', + 407: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', + 408: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', + 409: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', + 410: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', + 411: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', + 412: 'Reserved412', + 413: 'Reserved413', + 414: 'Reserved414', + 415: 'Reserved415', + 416: 'Reserved416', + 417: 'Reserved417', + 418: 'Reserved418', + 419: 'Reserved419', + 420: 'Reserved420', + 421: 'Reserved421', + 422: 'Reserved422', + 423: 'Reserved423', + 424: 'Reserved424', + 425: 'Reserved425', + 426: 'Reserved426', + 427: 'Reserved427', + 428: 'Reserved428', + 429: 'Reserved429', + 430: 'Reserved430', + 431: 'Reserved431', + 432: 'Reserved432', + 433: 'Reserved433', + 434: 'Reserved434', + 435: 'Reserved435', + 436: 'Reserved436', + 437: 'Reserved437', + 438: 'Reserved438', + 439: 'Reserved439', + 440: 'Reserved440', + 441: 'Reserved441', + 442: 'Reserved442', + 443: 'Reserved443', + 444: 'Reserved444', + 445: 'Reserved445', + 446: 'Reserved446', + 447: 'Reserved447', + 448: 'Reserved448', + 449: 'Reserved449', + 450: 'Reserved450', + 451: 'Reserved451', + 452: 'Reserved452', + 453: 'Reserved453', + 454: 'Reserved454', + 455: 'Reserved455', + 456: 'Reserved456', + 457: 'Reserved457', + 458: 'Reserved458', + 459: 'Reserved459', + 460: 'Reserved460', + 461: 'Reserved461', + 462: 'Reserved462', + 463: 'Reserved463', + 464: 'Reserved464', + 465: 'Reserved465', + 466: 'Reserved466', + 467: 'Reserved467', + 468: 'Reserved468', + 469: 'Reserved469', + 470: 'Reserved470', + 471: 'Reserved471', + 472: 'Reserved472', + 473: 'Reserved473', + 474: 'Reserved474', + 475: 'Reserved475', + 476: 'Reserved476', + 477: 'Reserved477', + 478: 'Reserved478', + 479: 'Reserved479', + 480: 'Reserved480', + 481: 'Reserved481', + 482: 'Reserved482', + 483: 'Reserved483', + 484: 'Reserved484', + 485: 'Reserved485', + 486: 'Reserved486', + 487: 'Reserved487', + 488: 'Reserved488', + 489: 'Reserved489', + 490: 'Reserved490', + 491: 'Reserved491', + 492: 'Reserved492', + 493: 'Reserved493', + 494: 'Reserved494', + 495: 'Reserved495', + 496: 'Reserved496', + 497: 'Reserved497', + 498: 'Reserved498', + 499: 'Reserved499', + 500: 'Reserved500', + 501: 'Reserved501', + 502: 'Reserved502', + 503: 'Reserved503', + 504: 'Reserved504', + 505: 'Reserved505', + 506: 'Reserved506', + 507: 'Reserved507', + 508: 'Reserved508', + 509: 'Reserved509', + 510: 'Reserved510', + 511: 'Reserved511', +} +IH_PERF_SEL_CYCLE = 0 +IH_PERF_SEL_IDLE = 1 +IH_PERF_SEL_INPUT_IDLE = 2 +IH_PERF_SEL_BUFFER_IDLE = 3 +IH_PERF_SEL_RB0_FULL = 4 +IH_PERF_SEL_RB0_OVERFLOW = 5 +IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6 +IH_PERF_SEL_RB0_WPTR_WRAP = 7 +IH_PERF_SEL_RB0_RPTR_WRAP = 8 +IH_PERF_SEL_MC_WR_IDLE = 9 +IH_PERF_SEL_MC_WR_COUNT = 10 +IH_PERF_SEL_MC_WR_STALL = 11 +IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12 +IH_PERF_SEL_MC_WR_CLEAN_STALL = 13 +IH_PERF_SEL_BIF_LINE0_RISING = 14 +IH_PERF_SEL_BIF_LINE0_FALLING = 15 +IH_PERF_SEL_RB1_FULL = 16 +IH_PERF_SEL_RB1_OVERFLOW = 17 +Reserved18 = 18 +IH_PERF_SEL_RB1_WPTR_WRAP = 19 +IH_PERF_SEL_RB1_RPTR_WRAP = 20 +IH_PERF_SEL_RB2_FULL = 21 +IH_PERF_SEL_RB2_OVERFLOW = 22 +Reserved23 = 23 +IH_PERF_SEL_RB2_WPTR_WRAP = 24 +IH_PERF_SEL_RB2_RPTR_WRAP = 25 +Reserved26 = 26 +Reserved27 = 27 +Reserved28 = 28 +Reserved29 = 29 +IH_PERF_SEL_RB0_FULL_VF0 = 30 +IH_PERF_SEL_RB0_FULL_VF1 = 31 +IH_PERF_SEL_RB0_FULL_VF2 = 32 +IH_PERF_SEL_RB0_FULL_VF3 = 33 +IH_PERF_SEL_RB0_FULL_VF4 = 34 +IH_PERF_SEL_RB0_FULL_VF5 = 35 +IH_PERF_SEL_RB0_FULL_VF6 = 36 +IH_PERF_SEL_RB0_FULL_VF7 = 37 +IH_PERF_SEL_RB0_FULL_VF8 = 38 +IH_PERF_SEL_RB0_FULL_VF9 = 39 +IH_PERF_SEL_RB0_FULL_VF10 = 40 +IH_PERF_SEL_RB0_FULL_VF11 = 41 +IH_PERF_SEL_RB0_FULL_VF12 = 42 +IH_PERF_SEL_RB0_FULL_VF13 = 43 +IH_PERF_SEL_RB0_FULL_VF14 = 44 +IH_PERF_SEL_RB0_FULL_VF15 = 45 +IH_PERF_SEL_RB0_OVERFLOW_VF0 = 46 +IH_PERF_SEL_RB0_OVERFLOW_VF1 = 47 +IH_PERF_SEL_RB0_OVERFLOW_VF2 = 48 +IH_PERF_SEL_RB0_OVERFLOW_VF3 = 49 +IH_PERF_SEL_RB0_OVERFLOW_VF4 = 50 +IH_PERF_SEL_RB0_OVERFLOW_VF5 = 51 +IH_PERF_SEL_RB0_OVERFLOW_VF6 = 52 +IH_PERF_SEL_RB0_OVERFLOW_VF7 = 53 +IH_PERF_SEL_RB0_OVERFLOW_VF8 = 54 +IH_PERF_SEL_RB0_OVERFLOW_VF9 = 55 +IH_PERF_SEL_RB0_OVERFLOW_VF10 = 56 +IH_PERF_SEL_RB0_OVERFLOW_VF11 = 57 +IH_PERF_SEL_RB0_OVERFLOW_VF12 = 58 +IH_PERF_SEL_RB0_OVERFLOW_VF13 = 59 +IH_PERF_SEL_RB0_OVERFLOW_VF14 = 60 +IH_PERF_SEL_RB0_OVERFLOW_VF15 = 61 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 62 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 63 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 64 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 65 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 66 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 67 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 68 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 69 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 70 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 71 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 72 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 73 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 74 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 75 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 76 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 77 +IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 78 +IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 79 +IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 80 +IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 81 +IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 82 +IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 83 +IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 84 +IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 85 +IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 86 +IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 87 +IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 88 +IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 89 +IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 90 +IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 91 +IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 92 +IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 93 +IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 94 +IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 95 +IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 96 +IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 97 +IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 98 +IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 99 +IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 100 +IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 101 +IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 102 +IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 103 +IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 104 +IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 105 +IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 106 +IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 107 +IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 108 +IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 109 +IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 110 +IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 111 +IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 112 +IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 113 +IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 114 +IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 115 +IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 116 +IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 117 +IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 118 +IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 119 +IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 120 +IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 121 +IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 122 +IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 123 +IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 124 +IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 125 +IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 126 +IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 127 +IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 128 +IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 129 +IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 130 +IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 131 +IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 132 +IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 133 +IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 134 +IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 135 +IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 136 +IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 137 +IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 138 +IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 139 +IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 140 +IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 141 +Reserved142 = 142 +Reserved143 = 143 +Reserved144 = 144 +Reserved145 = 145 +Reserved146 = 146 +Reserved147 = 147 +Reserved148 = 148 +Reserved149 = 149 +IH_PERF_SEL_CLIENT0_INT = 150 +IH_PERF_SEL_CLIENT1_INT = 151 +IH_PERF_SEL_CLIENT2_INT = 152 +IH_PERF_SEL_CLIENT3_INT = 153 +IH_PERF_SEL_CLIENT4_INT = 154 +IH_PERF_SEL_CLIENT5_INT = 155 +IH_PERF_SEL_CLIENT6_INT = 156 +IH_PERF_SEL_CLIENT7_INT = 157 +IH_PERF_SEL_CLIENT8_INT = 158 +IH_PERF_SEL_CLIENT9_INT = 159 +IH_PERF_SEL_CLIENT10_INT = 160 +IH_PERF_SEL_CLIENT11_INT = 161 +IH_PERF_SEL_CLIENT12_INT = 162 +IH_PERF_SEL_CLIENT13_INT = 163 +IH_PERF_SEL_CLIENT14_INT = 164 +IH_PERF_SEL_CLIENT15_INT = 165 +IH_PERF_SEL_CLIENT16_INT = 166 +IH_PERF_SEL_CLIENT17_INT = 167 +IH_PERF_SEL_CLIENT18_INT = 168 +IH_PERF_SEL_CLIENT19_INT = 169 +IH_PERF_SEL_CLIENT20_INT = 170 +IH_PERF_SEL_CLIENT21_INT = 171 +IH_PERF_SEL_CLIENT22_INT = 172 +IH_PERF_SEL_CLIENT23_INT = 173 +IH_PERF_SEL_CLIENT24_INT = 174 +IH_PERF_SEL_CLIENT25_INT = 175 +IH_PERF_SEL_CLIENT26_INT = 176 +IH_PERF_SEL_CLIENT27_INT = 177 +IH_PERF_SEL_CLIENT28_INT = 178 +IH_PERF_SEL_CLIENT29_INT = 179 +IH_PERF_SEL_CLIENT30_INT = 180 +IH_PERF_SEL_CLIENT31_INT = 181 +Reserved182 = 182 +Reserved183 = 183 +Reserved184 = 184 +Reserved185 = 185 +Reserved186 = 186 +Reserved187 = 187 +Reserved188 = 188 +Reserved189 = 189 +Reserved190 = 190 +Reserved191 = 191 +Reserved192 = 192 +Reserved193 = 193 +Reserved194 = 194 +Reserved195 = 195 +Reserved196 = 196 +Reserved197 = 197 +Reserved198 = 198 +Reserved199 = 199 +Reserved200 = 200 +Reserved201 = 201 +Reserved202 = 202 +Reserved203 = 203 +Reserved204 = 204 +Reserved205 = 205 +Reserved206 = 206 +Reserved207 = 207 +Reserved208 = 208 +Reserved209 = 209 +Reserved210 = 210 +Reserved211 = 211 +Reserved212 = 212 +Reserved213 = 213 +Reserved214 = 214 +Reserved215 = 215 +Reserved216 = 216 +Reserved217 = 217 +Reserved218 = 218 +Reserved219 = 219 +IH_PERF_SEL_RB1_FULL_VF0 = 220 +IH_PERF_SEL_RB1_FULL_VF1 = 221 +IH_PERF_SEL_RB1_FULL_VF2 = 222 +IH_PERF_SEL_RB1_FULL_VF3 = 223 +IH_PERF_SEL_RB1_FULL_VF4 = 224 +IH_PERF_SEL_RB1_FULL_VF5 = 225 +IH_PERF_SEL_RB1_FULL_VF6 = 226 +IH_PERF_SEL_RB1_FULL_VF7 = 227 +IH_PERF_SEL_RB1_FULL_VF8 = 228 +IH_PERF_SEL_RB1_FULL_VF9 = 229 +IH_PERF_SEL_RB1_FULL_VF10 = 230 +IH_PERF_SEL_RB1_FULL_VF11 = 231 +IH_PERF_SEL_RB1_FULL_VF12 = 232 +IH_PERF_SEL_RB1_FULL_VF13 = 233 +IH_PERF_SEL_RB1_FULL_VF14 = 234 +IH_PERF_SEL_RB1_FULL_VF15 = 235 +IH_PERF_SEL_RB1_OVERFLOW_VF0 = 236 +IH_PERF_SEL_RB1_OVERFLOW_VF1 = 237 +IH_PERF_SEL_RB1_OVERFLOW_VF2 = 238 +IH_PERF_SEL_RB1_OVERFLOW_VF3 = 239 +IH_PERF_SEL_RB1_OVERFLOW_VF4 = 240 +IH_PERF_SEL_RB1_OVERFLOW_VF5 = 241 +IH_PERF_SEL_RB1_OVERFLOW_VF6 = 242 +IH_PERF_SEL_RB1_OVERFLOW_VF7 = 243 +IH_PERF_SEL_RB1_OVERFLOW_VF8 = 244 +IH_PERF_SEL_RB1_OVERFLOW_VF9 = 245 +IH_PERF_SEL_RB1_OVERFLOW_VF10 = 246 +IH_PERF_SEL_RB1_OVERFLOW_VF11 = 247 +IH_PERF_SEL_RB1_OVERFLOW_VF12 = 248 +IH_PERF_SEL_RB1_OVERFLOW_VF13 = 249 +IH_PERF_SEL_RB1_OVERFLOW_VF14 = 250 +IH_PERF_SEL_RB1_OVERFLOW_VF15 = 251 +Reserved252 = 252 +Reserved253 = 253 +Reserved254 = 254 +Reserved255 = 255 +Reserved256 = 256 +Reserved257 = 257 +Reserved258 = 258 +Reserved259 = 259 +Reserved260 = 260 +Reserved261 = 261 +Reserved262 = 262 +Reserved263 = 263 +Reserved264 = 264 +Reserved265 = 265 +Reserved266 = 266 +Reserved267 = 267 +IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 268 +IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 269 +IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 270 +IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 271 +IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 272 +IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 273 +IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 274 +IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 275 +IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 276 +IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 277 +IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 278 +IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 279 +IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 280 +IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 281 +IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 282 +IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 283 +IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 284 +IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 285 +IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 286 +IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 287 +IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 288 +IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 289 +IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 290 +IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 291 +IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 292 +IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 293 +IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 294 +IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 295 +IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 296 +IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 297 +IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 298 +IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 299 +Reserved300 = 300 +Reserved301 = 301 +Reserved302 = 302 +Reserved303 = 303 +Reserved304 = 304 +Reserved305 = 305 +Reserved306 = 306 +Reserved307 = 307 +Reserved308 = 308 +Reserved309 = 309 +Reserved310 = 310 +Reserved311 = 311 +Reserved312 = 312 +Reserved313 = 313 +Reserved314 = 314 +Reserved315 = 315 +Reserved316 = 316 +Reserved317 = 317 +Reserved318 = 318 +Reserved319 = 319 +Reserved320 = 320 +Reserved321 = 321 +Reserved322 = 322 +Reserved323 = 323 +Reserved324 = 324 +Reserved325 = 325 +Reserved326 = 326 +Reserved327 = 327 +Reserved328 = 328 +Reserved329 = 329 +Reserved330 = 330 +Reserved331 = 331 +IH_PERF_SEL_RB2_FULL_VF0 = 332 +IH_PERF_SEL_RB2_FULL_VF1 = 333 +IH_PERF_SEL_RB2_FULL_VF2 = 334 +IH_PERF_SEL_RB2_FULL_VF3 = 335 +IH_PERF_SEL_RB2_FULL_VF4 = 336 +IH_PERF_SEL_RB2_FULL_VF5 = 337 +IH_PERF_SEL_RB2_FULL_VF6 = 338 +IH_PERF_SEL_RB2_FULL_VF7 = 339 +IH_PERF_SEL_RB2_FULL_VF8 = 340 +IH_PERF_SEL_RB2_FULL_VF9 = 341 +IH_PERF_SEL_RB2_FULL_VF10 = 342 +IH_PERF_SEL_RB2_FULL_VF11 = 343 +IH_PERF_SEL_RB2_FULL_VF12 = 344 +IH_PERF_SEL_RB2_FULL_VF13 = 345 +IH_PERF_SEL_RB2_FULL_VF14 = 346 +IH_PERF_SEL_RB2_FULL_VF15 = 347 +IH_PERF_SEL_RB2_OVERFLOW_VF0 = 348 +IH_PERF_SEL_RB2_OVERFLOW_VF1 = 349 +IH_PERF_SEL_RB2_OVERFLOW_VF2 = 350 +IH_PERF_SEL_RB2_OVERFLOW_VF3 = 351 +IH_PERF_SEL_RB2_OVERFLOW_VF4 = 352 +IH_PERF_SEL_RB2_OVERFLOW_VF5 = 353 +IH_PERF_SEL_RB2_OVERFLOW_VF6 = 354 +IH_PERF_SEL_RB2_OVERFLOW_VF7 = 355 +IH_PERF_SEL_RB2_OVERFLOW_VF8 = 356 +IH_PERF_SEL_RB2_OVERFLOW_VF9 = 357 +IH_PERF_SEL_RB2_OVERFLOW_VF10 = 358 +IH_PERF_SEL_RB2_OVERFLOW_VF11 = 359 +IH_PERF_SEL_RB2_OVERFLOW_VF12 = 360 +IH_PERF_SEL_RB2_OVERFLOW_VF13 = 361 +IH_PERF_SEL_RB2_OVERFLOW_VF14 = 362 +IH_PERF_SEL_RB2_OVERFLOW_VF15 = 363 +Reserved364 = 364 +Reserved365 = 365 +Reserved366 = 366 +Reserved367 = 367 +Reserved368 = 368 +Reserved369 = 369 +Reserved370 = 370 +Reserved371 = 371 +Reserved372 = 372 +Reserved373 = 373 +Reserved374 = 374 +Reserved375 = 375 +Reserved376 = 376 +Reserved377 = 377 +Reserved378 = 378 +Reserved379 = 379 +IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 380 +IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 381 +IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 382 +IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 383 +IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 384 +IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 385 +IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 386 +IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 387 +IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 388 +IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 389 +IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 390 +IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 391 +IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 392 +IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 393 +IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 394 +IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 395 +IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 396 +IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 397 +IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 398 +IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 399 +IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 400 +IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 401 +IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 402 +IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 403 +IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 404 +IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 405 +IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 406 +IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 407 +IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 408 +IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 409 +IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 410 +IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 411 +Reserved412 = 412 +Reserved413 = 413 +Reserved414 = 414 +Reserved415 = 415 +Reserved416 = 416 +Reserved417 = 417 +Reserved418 = 418 +Reserved419 = 419 +Reserved420 = 420 +Reserved421 = 421 +Reserved422 = 422 +Reserved423 = 423 +Reserved424 = 424 +Reserved425 = 425 +Reserved426 = 426 +Reserved427 = 427 +Reserved428 = 428 +Reserved429 = 429 +Reserved430 = 430 +Reserved431 = 431 +Reserved432 = 432 +Reserved433 = 433 +Reserved434 = 434 +Reserved435 = 435 +Reserved436 = 436 +Reserved437 = 437 +Reserved438 = 438 +Reserved439 = 439 +Reserved440 = 440 +Reserved441 = 441 +Reserved442 = 442 +Reserved443 = 443 +Reserved444 = 444 +Reserved445 = 445 +Reserved446 = 446 +Reserved447 = 447 +Reserved448 = 448 +Reserved449 = 449 +Reserved450 = 450 +Reserved451 = 451 +Reserved452 = 452 +Reserved453 = 453 +Reserved454 = 454 +Reserved455 = 455 +Reserved456 = 456 +Reserved457 = 457 +Reserved458 = 458 +Reserved459 = 459 +Reserved460 = 460 +Reserved461 = 461 +Reserved462 = 462 +Reserved463 = 463 +Reserved464 = 464 +Reserved465 = 465 +Reserved466 = 466 +Reserved467 = 467 +Reserved468 = 468 +Reserved469 = 469 +Reserved470 = 470 +Reserved471 = 471 +Reserved472 = 472 +Reserved473 = 473 +Reserved474 = 474 +Reserved475 = 475 +Reserved476 = 476 +Reserved477 = 477 +Reserved478 = 478 +Reserved479 = 479 +Reserved480 = 480 +Reserved481 = 481 +Reserved482 = 482 +Reserved483 = 483 +Reserved484 = 484 +Reserved485 = 485 +Reserved486 = 486 +Reserved487 = 487 +Reserved488 = 488 +Reserved489 = 489 +Reserved490 = 490 +Reserved491 = 491 +Reserved492 = 492 +Reserved493 = 493 +Reserved494 = 494 +Reserved495 = 495 +Reserved496 = 496 +Reserved497 = 497 +Reserved498 = 498 +Reserved499 = 499 +Reserved500 = 500 +Reserved501 = 501 +Reserved502 = 502 +Reserved503 = 503 +Reserved504 = 504 +Reserved505 = 505 +Reserved506 = 506 +Reserved507 = 507 +Reserved508 = 508 +Reserved509 = 509 +Reserved510 = 510 +Reserved511 = 511 +IH_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SEM_PERF_SEL' +SEM_PERF_SEL__enumvalues = { + 0: 'SEM_PERF_SEL_CYCLE', + 1: 'SEM_PERF_SEL_IDLE', + 2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', + 3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', + 4: 'SEM_PERF_SEL_UVD_REQ_SIGNAL', + 5: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', + 6: 'SEM_PERF_SEL_ACP_REQ_SIGNAL', + 7: 'SEM_PERF_SEL_ISP_REQ_SIGNAL', + 8: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', + 9: 'SEM_PERF_SEL_VP8_REQ_SIGNAL', + 10: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', + 11: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', + 12: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', + 13: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', + 14: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', + 15: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', + 16: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', + 17: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', + 18: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', + 19: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', + 20: 'SEM_PERF_SEL_SDMA0_REQ_WAIT', + 21: 'SEM_PERF_SEL_SDMA1_REQ_WAIT', + 22: 'SEM_PERF_SEL_UVD_REQ_WAIT', + 23: 'SEM_PERF_SEL_VCE0_REQ_WAIT', + 24: 'SEM_PERF_SEL_ACP_REQ_WAIT', + 25: 'SEM_PERF_SEL_ISP_REQ_WAIT', + 26: 'SEM_PERF_SEL_VCE1_REQ_WAIT', + 27: 'SEM_PERF_SEL_VP8_REQ_WAIT', + 28: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', + 29: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', + 30: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', + 31: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', + 32: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', + 33: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', + 34: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', + 35: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', + 36: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', + 37: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', + 38: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', + 39: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', + 40: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', + 41: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', + 42: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', + 43: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', + 44: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', + 45: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', + 46: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', + 47: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', + 48: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', + 49: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', + 50: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', + 51: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', + 52: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', + 53: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', + 54: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', + 55: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', + 56: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', + 57: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', + 58: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', + 59: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', + 60: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', + 61: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', + 62: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', + 63: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', + 64: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', + 65: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', + 66: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', + 67: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', + 68: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', + 69: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', + 70: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', + 71: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', + 72: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', + 73: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', + 74: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', + 75: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', + 76: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', + 77: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', + 78: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', + 79: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', + 80: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', + 81: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', + 82: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', + 83: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', + 84: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', + 85: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', + 86: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', + 87: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', + 88: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', + 89: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', + 90: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', + 91: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', + 92: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', + 93: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', + 94: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', + 95: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', + 96: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', + 97: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', + 98: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', + 99: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', + 100: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', + 101: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', + 102: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', + 103: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', + 104: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', + 105: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', + 106: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', + 107: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', + 108: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', + 109: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', + 110: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', + 111: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', + 112: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', + 113: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', + 114: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', + 115: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', + 116: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', + 117: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', + 118: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', + 119: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', + 120: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', + 121: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', + 122: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', + 123: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', + 124: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', + 125: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', + 126: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', + 127: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', + 128: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', + 129: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', + 130: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', + 131: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', + 132: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', + 133: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', + 134: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', + 135: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', + 136: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', + 137: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', + 138: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', + 139: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', + 140: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', + 141: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', + 142: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', + 143: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', + 144: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', + 145: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', + 146: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', + 147: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', + 148: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', + 149: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', + 150: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', + 151: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', + 152: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', + 153: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', + 154: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', + 155: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', + 156: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', + 157: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', + 158: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', + 159: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', + 160: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', + 161: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', + 162: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', + 163: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', + 164: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', + 165: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', + 166: 'SEM_PERF_SEL_MC_RD_REQ', + 167: 'SEM_PERF_SEL_MC_RD_RET', + 168: 'SEM_PERF_SEL_MC_WR_REQ', + 169: 'SEM_PERF_SEL_MC_WR_RET', + 170: 'SEM_PERF_SEL_ATC_REQ', + 171: 'SEM_PERF_SEL_ATC_RET', + 172: 'SEM_PERF_SEL_ATC_XNACK', + 173: 'SEM_PERF_SEL_ATC_INVALIDATION', +} +SEM_PERF_SEL_CYCLE = 0 +SEM_PERF_SEL_IDLE = 1 +SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2 +SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3 +SEM_PERF_SEL_UVD_REQ_SIGNAL = 4 +SEM_PERF_SEL_VCE0_REQ_SIGNAL = 5 +SEM_PERF_SEL_ACP_REQ_SIGNAL = 6 +SEM_PERF_SEL_ISP_REQ_SIGNAL = 7 +SEM_PERF_SEL_VCE1_REQ_SIGNAL = 8 +SEM_PERF_SEL_VP8_REQ_SIGNAL = 9 +SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 10 +SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 11 +SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 12 +SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 13 +SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 14 +SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 15 +SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 16 +SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 17 +SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 18 +SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 19 +SEM_PERF_SEL_SDMA0_REQ_WAIT = 20 +SEM_PERF_SEL_SDMA1_REQ_WAIT = 21 +SEM_PERF_SEL_UVD_REQ_WAIT = 22 +SEM_PERF_SEL_VCE0_REQ_WAIT = 23 +SEM_PERF_SEL_ACP_REQ_WAIT = 24 +SEM_PERF_SEL_ISP_REQ_WAIT = 25 +SEM_PERF_SEL_VCE1_REQ_WAIT = 26 +SEM_PERF_SEL_VP8_REQ_WAIT = 27 +SEM_PERF_SEL_CPG_E0_REQ_WAIT = 28 +SEM_PERF_SEL_CPG_E1_REQ_WAIT = 29 +SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 30 +SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 31 +SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 32 +SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 33 +SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 34 +SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 35 +SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 36 +SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 37 +SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 38 +SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 39 +SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 40 +SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 41 +SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 42 +SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 43 +SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 44 +SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 45 +SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 46 +SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 47 +SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 48 +SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 49 +SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 50 +SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 51 +SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 52 +SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 53 +SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 54 +SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 55 +SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 56 +SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 57 +SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 58 +SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 59 +SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 60 +SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 61 +SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 62 +SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 63 +SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 64 +SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 65 +SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 66 +SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 67 +SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 68 +SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 69 +SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 70 +SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 71 +SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 72 +SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 73 +SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 74 +SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 75 +SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 76 +SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 77 +SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 78 +SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 79 +SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 80 +SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 81 +SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 82 +SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 83 +SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 84 +SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 85 +SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 86 +SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 87 +SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 88 +SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 89 +SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 90 +SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 91 +SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 92 +SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 93 +SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 94 +SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 95 +SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 96 +SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 97 +SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 98 +SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 99 +SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 100 +SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 101 +SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 102 +SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 103 +SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 104 +SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 105 +SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 106 +SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 107 +SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 108 +SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 109 +SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 110 +SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 111 +SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 112 +SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 113 +SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 114 +SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 115 +SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 116 +SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 117 +SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 118 +SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 119 +SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 120 +SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 121 +SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 122 +SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 123 +SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 124 +SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 125 +SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 126 +SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 127 +SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 128 +SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 129 +SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 130 +SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 131 +SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 132 +SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 133 +SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 134 +SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 135 +SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 136 +SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 137 +SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 138 +SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 139 +SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 140 +SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 141 +SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 142 +SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 143 +SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 144 +SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 145 +SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 146 +SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 147 +SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 148 +SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 149 +SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 150 +SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 151 +SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 152 +SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 153 +SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 154 +SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 155 +SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 156 +SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 157 +SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 158 +SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 159 +SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 160 +SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 161 +SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 162 +SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 163 +SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 164 +SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 165 +SEM_PERF_SEL_MC_RD_REQ = 166 +SEM_PERF_SEL_MC_RD_RET = 167 +SEM_PERF_SEL_MC_WR_REQ = 168 +SEM_PERF_SEL_MC_WR_RET = 169 +SEM_PERF_SEL_ATC_REQ = 170 +SEM_PERF_SEL_ATC_RET = 171 +SEM_PERF_SEL_ATC_XNACK = 172 +SEM_PERF_SEL_ATC_INVALIDATION = 173 +SEM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SDMA_PERF_SEL' +SDMA_PERF_SEL__enumvalues = { + 0: 'SDMA_PERF_SEL_CYCLE', + 1: 'SDMA_PERF_SEL_IDLE', + 2: 'SDMA_PERF_SEL_REG_IDLE', + 3: 'SDMA_PERF_SEL_RB_EMPTY', + 4: 'SDMA_PERF_SEL_RB_FULL', + 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', + 8: 'SDMA_PERF_SEL_RB_RPTR_WB', + 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', + 10: 'SDMA_PERF_SEL_RB_CMD_FULL', + 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', + 12: 'SDMA_PERF_SEL_IB_CMD_FULL', + 13: 'SDMA_PERF_SEL_EX_IDLE', + 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', + 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'SDMA_PERF_SEL_MC_WR_IDLE', + 17: 'SDMA_PERF_SEL_MC_WR_COUNT', + 18: 'SDMA_PERF_SEL_MC_RD_IDLE', + 19: 'SDMA_PERF_SEL_MC_RD_COUNT', + 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', + 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 24: 'SDMA_PERF_SEL_SEM_IDLE', + 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', + 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', + 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', + 30: 'SDMA_PERF_SEL_INT_IDLE', + 31: 'SDMA_PERF_SEL_INT_REQ_STALL', + 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', + 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', + 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', + 35: 'SDMA_PERF_SEL_NUM_PACKET', + 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 38: 'SDMA_PERF_SEL_CE_WR_IDLE', + 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', + 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', + 42: 'SDMA_PERF_SEL_CE_IN_IDLE', + 43: 'SDMA_PERF_SEL_CE_DST_IDLE', + 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', + 49: 'SDMA_PERF_SEL_CE_INFO_FULL', + 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', + 51: 'SDMA_PERF_SEL_CE_RD_STALL', + 52: 'SDMA_PERF_SEL_CE_WR_STALL', + 53: 'SDMA_PERF_SEL_GFX_SELECT', + 54: 'SDMA_PERF_SEL_RLC0_SELECT', + 55: 'SDMA_PERF_SEL_RLC1_SELECT', + 56: 'SDMA_PERF_SEL_PAGE_SELECT', + 57: 'SDMA_PERF_SEL_CTX_CHANGE', + 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', + 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 60: 'SDMA_PERF_SEL_DOORBELL', + 61: 'SDMA_PERF_SEL_RD_BA_RTR', + 62: 'SDMA_PERF_SEL_WR_BA_RTR', + 63: 'SDMA_PERF_SEL_F32_L1_WR_VLD', + 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', + 65: 'SDMA_PERF_SEL_CE_L1_STALL', + 66: 'SDMA_PERF_SEL_SDMA_INVACK_NFLUSH', + 67: 'SDMA_PERF_SEL_SDMA_INVACK_FLUSH', + 68: 'SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', + 69: 'SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', + 70: 'SDMA_PERF_SEL_ATCL2_RET_XNACK', + 71: 'SDMA_PERF_SEL_ATCL2_RET_ACK', + 72: 'SDMA_PERF_SEL_ATCL2_FREE', + 73: 'SDMA_PERF_SEL_SDMA_ATCL2_SEND', + 74: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 75: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', + 76: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 77: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', + 78: 'SDMA_PERF_SEL_L1_WR_FIFO_IDLE', + 79: 'SDMA_PERF_SEL_L1_RD_FIFO_IDLE', + 80: 'SDMA_PERF_SEL_L1_WRL2_IDLE', + 81: 'SDMA_PERF_SEL_L1_RDL2_IDLE', + 82: 'SDMA_PERF_SEL_L1_WRMC_IDLE', + 83: 'SDMA_PERF_SEL_L1_RDMC_IDLE', + 84: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', + 85: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', + 86: 'SDMA_PERF_SEL_L1_WR_INV_EN', + 87: 'SDMA_PERF_SEL_L1_RD_INV_EN', + 88: 'SDMA_PERF_SEL_L1_WR_WAIT_INVADR', + 89: 'SDMA_PERF_SEL_L1_RD_WAIT_INVADR', + 90: 'SDMA_PERF_SEL_IS_INVREQ_ADDR_WR', + 91: 'SDMA_PERF_SEL_IS_INVREQ_ADDR_RD', + 92: 'SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', + 93: 'SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', + 94: 'SDMA_PERF_SEL_L1_INV_MIDDLE', + 254: 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER', + 255: 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER', +} +SDMA_PERF_SEL_CYCLE = 0 +SDMA_PERF_SEL_IDLE = 1 +SDMA_PERF_SEL_REG_IDLE = 2 +SDMA_PERF_SEL_RB_EMPTY = 3 +SDMA_PERF_SEL_RB_FULL = 4 +SDMA_PERF_SEL_RB_WPTR_WRAP = 5 +SDMA_PERF_SEL_RB_RPTR_WRAP = 6 +SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 +SDMA_PERF_SEL_RB_RPTR_WB = 8 +SDMA_PERF_SEL_RB_CMD_IDLE = 9 +SDMA_PERF_SEL_RB_CMD_FULL = 10 +SDMA_PERF_SEL_IB_CMD_IDLE = 11 +SDMA_PERF_SEL_IB_CMD_FULL = 12 +SDMA_PERF_SEL_EX_IDLE = 13 +SDMA_PERF_SEL_SRBM_REG_SEND = 14 +SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +SDMA_PERF_SEL_MC_WR_IDLE = 16 +SDMA_PERF_SEL_MC_WR_COUNT = 17 +SDMA_PERF_SEL_MC_RD_IDLE = 18 +SDMA_PERF_SEL_MC_RD_COUNT = 19 +SDMA_PERF_SEL_MC_RD_RET_STALL = 20 +SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 +SDMA_PERF_SEL_SEM_IDLE = 24 +SDMA_PERF_SEL_SEM_REQ_STALL = 25 +SDMA_PERF_SEL_SEM_REQ_COUNT = 26 +SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 +SDMA_PERF_SEL_SEM_RESP_FAIL = 28 +SDMA_PERF_SEL_SEM_RESP_PASS = 29 +SDMA_PERF_SEL_INT_IDLE = 30 +SDMA_PERF_SEL_INT_REQ_STALL = 31 +SDMA_PERF_SEL_INT_REQ_COUNT = 32 +SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 +SDMA_PERF_SEL_INT_RESP_RETRY = 34 +SDMA_PERF_SEL_NUM_PACKET = 35 +SDMA_PERF_SEL_CE_WREQ_IDLE = 37 +SDMA_PERF_SEL_CE_WR_IDLE = 38 +SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 +SDMA_PERF_SEL_CE_RREQ_IDLE = 40 +SDMA_PERF_SEL_CE_OUT_IDLE = 41 +SDMA_PERF_SEL_CE_IN_IDLE = 42 +SDMA_PERF_SEL_CE_DST_IDLE = 43 +SDMA_PERF_SEL_CE_AFIFO_FULL = 46 +SDMA_PERF_SEL_CE_INFO_FULL = 49 +SDMA_PERF_SEL_CE_INFO1_FULL = 50 +SDMA_PERF_SEL_CE_RD_STALL = 51 +SDMA_PERF_SEL_CE_WR_STALL = 52 +SDMA_PERF_SEL_GFX_SELECT = 53 +SDMA_PERF_SEL_RLC0_SELECT = 54 +SDMA_PERF_SEL_RLC1_SELECT = 55 +SDMA_PERF_SEL_PAGE_SELECT = 56 +SDMA_PERF_SEL_CTX_CHANGE = 57 +SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 +SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 +SDMA_PERF_SEL_DOORBELL = 60 +SDMA_PERF_SEL_RD_BA_RTR = 61 +SDMA_PERF_SEL_WR_BA_RTR = 62 +SDMA_PERF_SEL_F32_L1_WR_VLD = 63 +SDMA_PERF_SEL_CE_L1_WR_VLD = 64 +SDMA_PERF_SEL_CE_L1_STALL = 65 +SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66 +SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67 +SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68 +SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69 +SDMA_PERF_SEL_ATCL2_RET_XNACK = 70 +SDMA_PERF_SEL_ATCL2_RET_ACK = 71 +SDMA_PERF_SEL_ATCL2_FREE = 72 +SDMA_PERF_SEL_SDMA_ATCL2_SEND = 73 +SDMA_PERF_SEL_DMA_L1_WR_SEND = 74 +SDMA_PERF_SEL_DMA_L1_RD_SEND = 75 +SDMA_PERF_SEL_DMA_MC_WR_SEND = 76 +SDMA_PERF_SEL_DMA_MC_RD_SEND = 77 +SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78 +SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79 +SDMA_PERF_SEL_L1_WRL2_IDLE = 80 +SDMA_PERF_SEL_L1_RDL2_IDLE = 81 +SDMA_PERF_SEL_L1_WRMC_IDLE = 82 +SDMA_PERF_SEL_L1_RDMC_IDLE = 83 +SDMA_PERF_SEL_L1_WR_INV_IDLE = 84 +SDMA_PERF_SEL_L1_RD_INV_IDLE = 85 +SDMA_PERF_SEL_L1_WR_INV_EN = 86 +SDMA_PERF_SEL_L1_RD_INV_EN = 87 +SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88 +SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89 +SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90 +SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91 +SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92 +SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93 +SDMA_PERF_SEL_L1_INV_MIDDLE = 94 +SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 254 +SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 255 +SDMA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_XDMA_LOCAL_SW_MODE' +ENUM_XDMA_LOCAL_SW_MODE__enumvalues = { + 2: 'XDMA_LOCAL_SW_MODE_SW_256B_D', + 10: 'XDMA_LOCAL_SW_MODE_SW_64KB_D', + 26: 'XDMA_LOCAL_SW_MODE_SW_64KB_D_X', +} +XDMA_LOCAL_SW_MODE_SW_256B_D = 2 +XDMA_LOCAL_SW_MODE_SW_64KB_D = 10 +XDMA_LOCAL_SW_MODE_SW_64KB_D_X = 26 +ENUM_XDMA_LOCAL_SW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_XDMA_SLV_ALPHA_POSITION' +ENUM_XDMA_SLV_ALPHA_POSITION__enumvalues = { + 0: 'XDMA_SLV_ALPHA_POSITION_7_0', + 1: 'XDMA_SLV_ALPHA_POSITION_15_8', + 2: 'XDMA_SLV_ALPHA_POSITION_23_16', + 3: 'XDMA_SLV_ALPHA_POSITION_31_24', +} +XDMA_SLV_ALPHA_POSITION_7_0 = 0 +XDMA_SLV_ALPHA_POSITION_15_8 = 1 +XDMA_SLV_ALPHA_POSITION_23_16 = 2 +XDMA_SLV_ALPHA_POSITION_31_24 = 3 +ENUM_XDMA_SLV_ALPHA_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_XDMA_MSTR_ALPHA_POSITION' +ENUM_XDMA_MSTR_ALPHA_POSITION__enumvalues = { + 0: 'XDMA_MSTR_ALPHA_POSITION_7_0', + 1: 'XDMA_MSTR_ALPHA_POSITION_15_8', + 2: 'XDMA_MSTR_ALPHA_POSITION_23_16', + 3: 'XDMA_MSTR_ALPHA_POSITION_31_24', +} +XDMA_MSTR_ALPHA_POSITION_7_0 = 0 +XDMA_MSTR_ALPHA_POSITION_15_8 = 1 +XDMA_MSTR_ALPHA_POSITION_23_16 = 2 +XDMA_MSTR_ALPHA_POSITION_31_24 = 3 +ENUM_XDMA_MSTR_ALPHA_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL' +ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL__enumvalues = { + 0: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0', + 1: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1', + 2: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2', + 3: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3', + 4: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4', + 5: 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5', +} +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0 = 0 +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1 = 1 +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2 = 2 +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3 = 3 +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4 = 4 +XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5 = 5 +ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL = ctypes.c_uint32 # enum +__all__ = \ + ['ABGR_TO_A_BG_G_RB', 'ABM_SOFT_RESET', 'ABM_SOFT_RESET_0', + 'ABM_SOFT_RESET_1', 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', + 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ADDR_CONFIG_16_BANK', + 'ADDR_CONFIG_16_PIPE', 'ADDR_CONFIG_1KB_ROW', + 'ADDR_CONFIG_1_BANK', 'ADDR_CONFIG_1_GPU', + 'ADDR_CONFIG_1_LOWER_PIPES', + 'ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_1_PIPE', + 'ADDR_CONFIG_1_RB_PER_SHADER_ENGINE', + 'ADDR_CONFIG_1_SHADER_ENGINE', 'ADDR_CONFIG_2KB_ROW', + 'ADDR_CONFIG_2_BANK', 'ADDR_CONFIG_2_GPU', + 'ADDR_CONFIG_2_LOWER_PIPES', + 'ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_2_PIPE', + 'ADDR_CONFIG_2_RB_PER_SHADER_ENGINE', + 'ADDR_CONFIG_2_SHADER_ENGINE', 'ADDR_CONFIG_32_PIPE', + 'ADDR_CONFIG_4KB_ROW', 'ADDR_CONFIG_4_BANK', 'ADDR_CONFIG_4_GPU', + 'ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS', 'ADDR_CONFIG_4_PIPE', + 'ADDR_CONFIG_4_RB_PER_SHADER_ENGINE', + 'ADDR_CONFIG_4_SHADER_ENGINE', 'ADDR_CONFIG_8_BANK', + 'ADDR_CONFIG_8_GPU', 'ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS', + 'ADDR_CONFIG_8_PIPE', 'ADDR_CONFIG_8_SHADER_ENGINE', + 'ADDR_CONFIG_BANK_INTERLEAVE_1', 'ADDR_CONFIG_BANK_INTERLEAVE_2', + 'ADDR_CONFIG_BANK_INTERLEAVE_4', 'ADDR_CONFIG_BANK_INTERLEAVE_8', + 'ADDR_CONFIG_DISABLE_SE', 'ADDR_CONFIG_ENABLE_SE', + 'ADDR_CONFIG_GPU_TILE_128', 'ADDR_CONFIG_GPU_TILE_16', + 'ADDR_CONFIG_GPU_TILE_32', 'ADDR_CONFIG_GPU_TILE_64', + 'ADDR_CONFIG_PIPE_INTERLEAVE_1KB', + 'ADDR_CONFIG_PIPE_INTERLEAVE_256B', + 'ADDR_CONFIG_PIPE_INTERLEAVE_2KB', + 'ADDR_CONFIG_PIPE_INTERLEAVE_512B', 'ADDR_CONFIG_SE_TILE_16', + 'ADDR_CONFIG_SE_TILE_32', 'ADDR_SURF_16_BANK', 'ADDR_SURF_2_BANK', + 'ADDR_SURF_4_BANK', 'ADDR_SURF_8_BANK', 'ADDR_SURF_BANK_HEIGHT_1', + 'ADDR_SURF_BANK_HEIGHT_2', 'ADDR_SURF_BANK_HEIGHT_4', + 'ADDR_SURF_BANK_HEIGHT_8', 'ADDR_SURF_BANK_WH_1', + 'ADDR_SURF_BANK_WH_2', 'ADDR_SURF_BANK_WH_4', + 'ADDR_SURF_BANK_WH_8', 'ADDR_SURF_BANK_WIDTH_1', + 'ADDR_SURF_BANK_WIDTH_2', 'ADDR_SURF_BANK_WIDTH_4', + 'ADDR_SURF_BANK_WIDTH_8', 'ADDR_SURF_DEPTH_MICRO_TILING', + 'ADDR_SURF_DISPLAY_MICRO_TILING', 'ADDR_SURF_MACRO_ASPECT_1', + 'ADDR_SURF_MACRO_ASPECT_2', 'ADDR_SURF_MACRO_ASPECT_4', + 'ADDR_SURF_MACRO_ASPECT_8', 'ADDR_SURF_MICRO_TILING_DISPLAY', + 'ADDR_SURF_MICRO_TILING_NON_DISPLAY', 'ADDR_SURF_P16_32x32_16x16', + 'ADDR_SURF_P16_32x32_8x16', 'ADDR_SURF_P2', + 'ADDR_SURF_P2_RESERVED0', 'ADDR_SURF_P2_RESERVED1', + 'ADDR_SURF_P2_RESERVED2', 'ADDR_SURF_P4_16x16', + 'ADDR_SURF_P4_16x32', 'ADDR_SURF_P4_32x32', 'ADDR_SURF_P4_8x16', + 'ADDR_SURF_P8_16x16_8x16', 'ADDR_SURF_P8_16x32_16x16', + 'ADDR_SURF_P8_16x32_8x16', 'ADDR_SURF_P8_32x32_16x16', + 'ADDR_SURF_P8_32x32_16x32', 'ADDR_SURF_P8_32x32_8x16', + 'ADDR_SURF_P8_32x64_32x32', 'ADDR_SURF_P8_RESERVED0', + 'ADDR_SURF_ROTATED_MICRO_TILING', 'ADDR_SURF_SAMPLE_SPLIT_1', + 'ADDR_SURF_SAMPLE_SPLIT_2', 'ADDR_SURF_SAMPLE_SPLIT_4', + 'ADDR_SURF_SAMPLE_SPLIT_8', 'ADDR_SURF_THICK_MICRO_TILING', + 'ADDR_SURF_THIN_MICRO_TILING', 'ADDR_SURF_TILE_SPLIT_128B', + 'ADDR_SURF_TILE_SPLIT_1KB', 'ADDR_SURF_TILE_SPLIT_256B', + 'ADDR_SURF_TILE_SPLIT_2KB', 'ADDR_SURF_TILE_SPLIT_4KB', + 'ADDR_SURF_TILE_SPLIT_512B', 'ADDR_SURF_TILE_SPLIT_64B', + 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', + 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', + 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', + 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', + 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', + 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', + 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', + 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', + 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', + 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', + 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', + 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', + 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', + 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', + 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', + 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', 'AFMT_AUDIO_SRC_RESERVED', + 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', + 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', + 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', + 'AFMT_INTERRUPT_STATUS_CHG_MASK', + 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', + 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', + 'ALLOW_SR_ON_TRANS_REQ', 'ALLOW_SR_ON_TRANS_REQ_DISABLE', + 'ALLOW_SR_ON_TRANS_REQ_ENABLE', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', + 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER', + 'ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE', + 'AOUT_CRC_CONT', 'AOUT_CRC_CONT_EN', 'AOUT_CRC_DISABLE', + 'AOUT_CRC_ENABLE', 'AOUT_CRC_NO_RESET', 'AOUT_CRC_ONE_SHOT', + 'AOUT_CRC_RESET', 'AOUT_CRC_SOFT_RESET', 'AOUT_CRC_TEST_EN', + 'AOUT_DISABLE', 'AOUT_EN', 'AOUT_ENABLE', 'AOUT_FIFO_START_ADDR', + 'AOUT_FIFO_START_ADDR_2', 'AOUT_FIFO_START_ADDR_3', 'ARRAY_1D', + 'ARRAY_1D_TILED_THICK', 'ARRAY_1D_TILED_THIN1', 'ARRAY_2D', + 'ARRAY_2D_ALT_COLOR', 'ARRAY_2D_ALT_DEPTH', 'ARRAY_2D_COLOR', + 'ARRAY_2D_DEPTH', 'ARRAY_2D_TILED_THICK', 'ARRAY_2D_TILED_THIN1', + 'ARRAY_2D_TILED_XTHICK', 'ARRAY_3D', 'ARRAY_3D_SLICE', + 'ARRAY_3D_SLICE_COLOR', 'ARRAY_3D_TILED_THICK', + 'ARRAY_3D_TILED_THIN1', 'ARRAY_3D_TILED_XTHICK', + 'ARRAY_COLOR_TILE', 'ARRAY_DEPTH_TILE', 'ARRAY_LINEAR', + 'ARRAY_LINEAR_ALIGNED', 'ARRAY_LINEAR_GENERAL', + 'ARRAY_PRT_2D_TILED_THICK', 'ARRAY_PRT_2D_TILED_THIN1', + 'ARRAY_PRT_3D_TILED_THICK', 'ARRAY_PRT_3D_TILED_THIN1', + 'ARRAY_PRT_TILED_THICK', 'ARRAY_PRT_TILED_THIN1', 'ARRAY_TILED', + 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', 'AUDIO_LAYOUT_SELECT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', + 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', + 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', + 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', + 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', + 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', + 'AZ_RIRB_WRITE_POINTER_DO_RESET', + 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', + 'AZ_STATE_CHANGE_STATUS', + 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'ArrayMode', + 'Available_0x1c', 'Available_0x1d', 'BGRA_TO_BG_G_RB_A', + 'BINNER_BREAK_BATCH', 'BINNER_DROP_ASSERT', 'BINNER_PIPELINE', + 'BINNING_ALLOWED', 'BLEND_BOTH_INV_SRC_ALPHA', + 'BLEND_BOTH_SRC_ALPHA', 'BLEND_CONSTANT_ALPHA', + 'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', + 'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', + 'BLEND_ONE_MINUS_CONSTANT_ALPHA', + 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', + 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', + 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', + 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', + 'BLEND_SRC_COLOR', 'BLEND_ZERO', + 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN', + 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', + 'BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', + 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN', + 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', + 'BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', + 'BLNDV_CONTROL2_PTI_ENABLE', 'BLNDV_CONTROL2_PTI_ENABLE_FALSE', + 'BLNDV_CONTROL2_PTI_ENABLE_TRUE', + 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY', + 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE', + 'BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE', + 'BLNDV_CONTROL_BLND_ALPHA_MODE', + 'BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', + 'BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', + 'BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 'BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED', + 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN', + 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', + 'BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', + 'BLNDV_CONTROL_BLND_MODE', + 'BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', + 'BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', + 'BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', + 'BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', + 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE', + 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE', + 'BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE', + 'BLNDV_CONTROL_BLND_STEREO_POLARITY', + 'BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH', + 'BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW', + 'BLNDV_CONTROL_BLND_STEREO_TYPE', + 'BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', + 'BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', + 'BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', + 'BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED', + 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT', + 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH', + 'BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW', + 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE', + 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', + 'BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 'BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', + 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE', + 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', + 'BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', + 'BLNDV_SM_CONTROL2_SM_MODE', + 'BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', + 'BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', + 'BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', + 'BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE', + 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN', + 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', + 'BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', + 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK', + 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', + 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', + 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK', + 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', + 'BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK', + 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK', + 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', + 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE', + 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', + 'BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', + 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN', + 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE', + 'BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE', + 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN', + 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE', + 'BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE', + 'BLND_CONTROL2_PTI_ENABLE', 'BLND_CONTROL2_PTI_ENABLE_FALSE', + 'BLND_CONTROL2_PTI_ENABLE_TRUE', + 'BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY', + 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE', + 'BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE', + 'BLND_CONTROL_BLND_ALPHA_MODE', + 'BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA', + 'BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY', + 'BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 'BLND_CONTROL_BLND_ALPHA_MODE_UNUSED', + 'BLND_CONTROL_BLND_FEEDTHROUGH_EN', + 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE', + 'BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE', 'BLND_CONTROL_BLND_MODE', + 'BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE', + 'BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY', + 'BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY', + 'BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE', + 'BLND_CONTROL_BLND_MULTIPLIED_MODE', + 'BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE', + 'BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE', + 'BLND_CONTROL_BLND_STEREO_POLARITY', + 'BLND_CONTROL_BLND_STEREO_POLARITY_HIGH', + 'BLND_CONTROL_BLND_STEREO_POLARITY_LOW', + 'BLND_CONTROL_BLND_STEREO_TYPE', + 'BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO', + 'BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO', + 'BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO', + 'BLND_CONTROL_BLND_STEREO_TYPE_UNUSED', + 'BLND_DEBUG_BLND_CNV_MUX_SELECT', + 'BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH', + 'BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW', + 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE', + 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE', + 'BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 'BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED', + 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE', + 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE', + 'BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE', + 'BLND_SM_CONTROL2_SM_MODE', + 'BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING', + 'BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING', + 'BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING', + 'BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE', + 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN', + 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE', + 'BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE', + 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK', + 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE', + 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE', + 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK', + 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE', + 'BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK', + 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK', + 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK', + 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK', + 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK', + 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK', + 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE', + 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE', + 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE', + 'BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE', + 'BLOCK_CONTEXT_DONE', 'BOTTOM_OF_PIPE_TS', 'BREAK_BATCH', + 'BUF_DATA_FORMAT', 'BUF_DATA_FORMAT_10_10_10_2', + 'BUF_DATA_FORMAT_10_11_11', 'BUF_DATA_FORMAT_11_11_10', + 'BUF_DATA_FORMAT_16', 'BUF_DATA_FORMAT_16_16', + 'BUF_DATA_FORMAT_16_16_16_16', 'BUF_DATA_FORMAT_2_10_10_10', + 'BUF_DATA_FORMAT_32', 'BUF_DATA_FORMAT_32_32', + 'BUF_DATA_FORMAT_32_32_32', 'BUF_DATA_FORMAT_32_32_32_32', + 'BUF_DATA_FORMAT_8', 'BUF_DATA_FORMAT_8_8', + 'BUF_DATA_FORMAT_8_8_8_8', 'BUF_DATA_FORMAT_INVALID', + 'BUF_DATA_FORMAT_RESERVED_15', 'BUF_NUM_FORMAT', + 'BUF_NUM_FORMAT_FLOAT', 'BUF_NUM_FORMAT_SINT', + 'BUF_NUM_FORMAT_SNORM', 'BUF_NUM_FORMAT_SSCALED', + 'BUF_NUM_FORMAT_UINT', 'BUF_NUM_FORMAT_UNORM', + 'BUF_NUM_FORMAT_UNORM_UINT', 'BUF_NUM_FORMAT_USCALED', + 'BankHeight', 'BankInterleaveSize', 'BankSwapBytes', 'BankTiling', + 'BankWidth', 'BankWidthHeight', 'BinEventCntl', 'BinningMode', + 'BlendOp', 'BlendOpt', 'CACHE_FLUSH', 'CACHE_FLUSH_AND_INV_EVENT', + 'CACHE_FLUSH_AND_INV_TS_EVENT', 'CACHE_FLUSH_TS', 'CBMode', + 'CBPerfClearFilterSel', 'CBPerfOpFilterSel', 'CBPerfSel', + 'CB_DCC_DECOMPRESS', 'CB_DECOMPRESS', 'CB_DISABLE', + 'CB_ELIMINATE_FAST_CLEAR', 'CB_FMASK_DECOMPRESS', 'CB_NORMAL', + 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', + 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', + 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 'CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL', + 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', 'CB_PERF_SEL_BUSY', + 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY', + 'CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB', + 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY', + 'CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB', + 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY', + 'CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB', + 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY', + 'CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB', + 'CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY', + 'CB_PERF_SEL_CC_BC_CS_FRAG_VALID', + 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_CC_CACHE_FLUSH', 'CB_PERF_SEL_CC_CACHE_HIT', + 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', + 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6', + 'CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7', + 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN', + 'CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT', + 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN', + 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2', + 'CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED', + 'CB_PERF_SEL_CC_DCC_RDREQ_STALL', + 'CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL', + 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY', + 'CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB', + 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY', + 'CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB', + 'CB_PERF_SEL_CC_MC_READ_REQUEST', + 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', + 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL', + 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY', + 'CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB', + 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY', + 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB', + 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY', + 'CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB', + 'CB_PERF_SEL_CC_RB_FULL', 'CB_PERF_SEL_CC_SF_FULL', + 'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CMASK_READ_DATA_0xC', + 'CB_PERF_SEL_CMASK_READ_DATA_0xD', + 'CB_PERF_SEL_CMASK_READ_DATA_0xE', + 'CB_PERF_SEL_CMASK_READ_DATA_0xF', + 'CB_PERF_SEL_CMASK_WRITE_DATA_0xC', + 'CB_PERF_SEL_CMASK_WRITE_DATA_0xD', + 'CB_PERF_SEL_CMASK_WRITE_DATA_0xE', + 'CB_PERF_SEL_CMASK_WRITE_DATA_0xF', + 'CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY', + 'CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_CM_CACHE_FLUSH', 'CB_PERF_SEL_CM_CACHE_HIT', + 'CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_CM_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_CM_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CM_CACHE_STALL', + 'CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_CM_CACHE_TAG_MISS', + 'CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READY', + 'CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB', + 'CB_PERF_SEL_CM_FC_TILE_VALID_READY', + 'CB_PERF_SEL_CM_FC_TILE_VALID_READYB', + 'CB_PERF_SEL_CM_MC_READ_REQUEST', + 'CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CM_MC_WRITE_REQUEST', + 'CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL', + 'CB_PERF_SEL_CM_TQ_FULL', 'CB_PERF_SEL_CORE_SCLK_VLD', + 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY', + 'CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB', + 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READY', + 'CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB', + 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READY', + 'CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB', + 'CB_PERF_SEL_DB_CB_TILE_VALID_READY', + 'CB_PERF_SEL_DB_CB_TILE_VALID_READYB', 'CB_PERF_SEL_DRAWN_BUSY', + 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', + 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE', + 'CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT', + 'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', + 'CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY', + 'CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_FC_CACHE_FLUSH', 'CB_PERF_SEL_FC_CACHE_HIT', + 'CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_FC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_FC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_FC_CACHE_STALL', + 'CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_FC_CACHE_TAG_MISS', + 'CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY', + 'CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB', + 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY', + 'CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB', + 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY', + 'CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB', + 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY', + 'CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB', + 'CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_FLUSH', 'CB_PERF_SEL_FC_DCC_CACHE_HIT', + 'CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS', + 'CB_PERF_SEL_FC_DCC_CACHE_STALL', + 'CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS', + 'CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR', + 'CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT', + 'CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS', + 'CB_PERF_SEL_FC_DOC_IS_STALLED', + 'CB_PERF_SEL_FC_DOC_MRTS_COMBINED', + 'CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED', + 'CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR', + 'CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS', + 'CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS', + 'CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS', + 'CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT', + 'CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS', + 'CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL', + 'CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS', + 'CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL', + 'CB_PERF_SEL_FC_MC_DCC_READ_REQUEST', + 'CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST', + 'CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_MC_READ_REQUEST', + 'CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_MC_WRITE_REQUEST', + 'CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED', + 'CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL', + 'CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL', + 'CB_PERF_SEL_FC_SEQUENCER_CLEAR', + 'CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR', + 'CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE', + 'CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS', + 'CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL', + 'CB_PERF_SEL_FOP_FMASK_BYPASS_STALL', + 'CB_PERF_SEL_FOP_FMASK_RAW_STALL', + 'CB_PERF_SEL_FOP_IN_VALIDB_READY', + 'CB_PERF_SEL_FOP_IN_VALIDB_READYB', + 'CB_PERF_SEL_FOP_IN_VALID_READY', + 'CB_PERF_SEL_FOP_IN_VALID_READYB', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR', + 'CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR', + 'CB_PERF_SEL_LQUAD_NO_TILE', + 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY', + 'CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB', 'CB_PERF_SEL_NONE', + 'CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT', + 'CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS', + 'CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS', + 'CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 'CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS', + 'CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS', + 'CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST', + 'CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED', + 'CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE', + 'CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE', + 'CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID', + 'CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL', + 'CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT', + 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK', + 'CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_0', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_1', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_2', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_3', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_4', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_5', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_6', + 'CB_PERF_SEL_QUAD_READS_FRAGMENT_7', + 'CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT', + 'CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS', + 'CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6', + 'CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7', + 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH', + 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT', + 'CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT', + 'CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD', + 'CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS', + 'CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK', + 'CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING', + 'CB_PERF_SEL_RBP_SPLIT_MICROTILE', + 'CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK', + 'CB_PERF_SEL_REG_SCLK0_VLD', 'CB_PERF_SEL_REG_SCLK1_VLD', + 'CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY', + 'CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT', 'CB_RESOLVE', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', + 'CHUB_TC_RET_CREDITS', 'CHUB_TC_RET_CREDITS_ENUM', + 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', 'CLKGATE_SM_MODE', + 'CLOCK_BRANCH_SOFT_RESET', 'CLOCK_BRANCH_SOFT_RESET_FORCE', + 'CLOCK_BRANCH_SOFT_RESET_NOOP', 'CLOCK_GATING_DISABLED', + 'CLOCK_GATING_DISABLED_IN_DCO', 'CLOCK_GATING_ENABLED', + 'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_ADDR_COMPATIBLE', + 'CMASK_ADDR_LINEAR', 'CMASK_ADDR_TILED', 'CMASK_ALPHA0_FRAG1', + 'CMASK_ALPHA0_FRAG2', 'CMASK_ALPHA0_FRAG4', 'CMASK_ALPHA0_FRAGS', + 'CMASK_ALPHA1_FRAG1', 'CMASK_ALPHA1_FRAG2', 'CMASK_ALPHA1_FRAG4', + 'CMASK_ALPHA1_FRAGS', 'CMASK_ALPHAX_FRAG1', 'CMASK_ALPHAX_FRAG2', + 'CMASK_ALPHAX_FRAG4', 'CMASK_ALPHAX_FRAGS', 'CMASK_ANY_EXPANDED', + 'CMASK_CLEAR_ALL', 'CMASK_CLEAR_NONE', 'CMASK_CLEAR_ONE', + 'CMASK_CLR00_F0', 'CMASK_CLR00_F1', 'CMASK_CLR00_F2', + 'CMASK_CLR00_FX', 'CMASK_CLR01_F0', 'CMASK_CLR01_F1', + 'CMASK_CLR01_F2', 'CMASK_CLR01_FX', 'CMASK_CLR10_F0', + 'CMASK_CLR10_F1', 'CMASK_CLR10_F2', 'CMASK_CLR10_FX', + 'CMASK_CLR11_F0', 'CMASK_CLR11_F1', 'CMASK_CLR11_F2', + 'CMASK_CLR11_FX', 'CMD_EMBEDDED_MODE_DISABLE', + 'CMD_EMBEDDED_MODE_ENABLE', 'CM_GLOBAL_PASSTHROUGH_DISBALE', + 'CM_GLOBAL_PASSTHROUGH_ENABLE', 'COEF_UPDATE_COMPLETE', + 'COEF_UPDATE_NOT_COMPLETE', 'COLOR_10_10_10_2', 'COLOR_10_11_11', + 'COLOR_11_11_10', 'COLOR_16', 'COLOR_16_16', 'COLOR_16_16_16_16', + 'COLOR_1_5_5_5', 'COLOR_24_8', 'COLOR_2_10_10_10', + 'COLOR_2_10_10_10_6E4', 'COLOR_32', 'COLOR_32_32', + 'COLOR_32_32_32_32', 'COLOR_4_4_4_4', 'COLOR_5_5_5_1', + 'COLOR_5_6_5', 'COLOR_8', 'COLOR_8_24', 'COLOR_8_8', + 'COLOR_8_8_8_8', 'COLOR_INVALID', 'COLOR_RESERVED_13', + 'COLOR_RESERVED_15', 'COLOR_RESERVED_23', 'COLOR_RESERVED_24', + 'COLOR_RESERVED_25', 'COLOR_RESERVED_26', 'COLOR_RESERVED_27', + 'COLOR_RESERVED_28', 'COLOR_RESERVED_29', 'COLOR_RESERVED_30', + 'COLOR_X24_8_32_FLOAT', 'COL_MAN_DEGAMMA_MODE', + 'COL_MAN_DENORM_CLAMP_CONTROL', 'COL_MAN_DISABLE_MULTIPLE_UPDATE', + 'COL_MAN_GAMUT_REMAP_MODE', 'COL_MAN_GLOBAL_PASSTHROUGH_ENABLE', + 'COL_MAN_INPUTCSC_CONVERT', 'COL_MAN_INPUTCSC_MODE', + 'COL_MAN_INPUTCSC_TYPE', 'COL_MAN_INPUT_GAMMA_MODE', + 'COL_MAN_MULTIPLE_UPDATE', 'COL_MAN_MULTIPLE_UPDAT_EDISABLE', + 'COL_MAN_OUTPUT_CSC_A', 'COL_MAN_OUTPUT_CSC_B', + 'COL_MAN_OUTPUT_CSC_BYPASS', 'COL_MAN_OUTPUT_CSC_MODE', + 'COL_MAN_OUTPUT_CSC_RGB', 'COL_MAN_OUTPUT_CSC_UNITY', + 'COL_MAN_OUTPUT_CSC_YCrCb601', 'COL_MAN_OUTPUT_CSC_YCrCb709', + 'COL_MAN_PRESCALE_MODE', 'COL_MAN_REGAMMA_MODE_A', + 'COL_MAN_REGAMMA_MODE_B', 'COL_MAN_REGAMMA_MODE_BYPASS', + 'COL_MAN_REGAMMA_MODE_CONTROL', 'COL_MAN_REGAMMA_MODE_ROM_A', + 'COL_MAN_REGAMMA_MODE_ROM_B', 'COL_MAN_UPDATE_LOCK', + 'COL_MAN_UPDATE_LOCKED', 'COL_MAN_UPDATE_UNLOCKED', + 'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', + 'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST', 'COMPONENT_DEPTH_10BPC', + 'COMPONENT_DEPTH_12BPC', 'COMPONENT_DEPTH_16BPC', + 'COMPONENT_DEPTH_6BPC', 'COMPONENT_DEPTH_8BPC', + 'CONFIG_128B_SWAPS', 'CONFIG_1KB_ROW', 'CONFIG_1KB_ROW_OPT', + 'CONFIG_1KB_SPLIT', 'CONFIG_1KB_SWAPS', 'CONFIG_1_PIPE', + 'CONFIG_256B_GROUP', 'CONFIG_256B_SWAPS', 'CONFIG_2KB_ROW', + 'CONFIG_2KB_ROW_OPT', 'CONFIG_2KB_SPLIT', 'CONFIG_2_PIPE', + 'CONFIG_4KB_ROW', 'CONFIG_4KB_ROW_OPT', 'CONFIG_4KB_SPLIT', + 'CONFIG_4_BANK', 'CONFIG_4_PIPE', 'CONFIG_512B_GROUP', + 'CONFIG_512B_SWAPS', 'CONFIG_8KB_ROW', 'CONFIG_8KB_ROW_OPT', + 'CONFIG_8KB_SPLIT', 'CONFIG_8_BANK', 'CONFIG_8_PIPE', + 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END', + 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START', + 'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START', + 'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', + 'CORB_READ_POINTER_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', + 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_PERFCOUNT_SEL', + 'CPC_PERF_SEL_ALWAYS_COUNT', + 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE', + 'CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE', + 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', + 'CPF_PERFCOUNT_SEL', 'CPF_PERF_SEL_ALWAYS_COUNT', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 'CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR', + 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 'CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS', + 'CPF_PERF_SEL_MIU_READ_REQUEST_SEND', + 'CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE', + 'CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND', + 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 'CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPF_TAG_RAM', + 'CPG_PERFCOUNT_SEL', 'CPG_PERF_SEL_ALWAYS_COUNT', + 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU', + 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', + 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 'CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR', + 'CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL', + 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 'CPG_PERF_SEL_ME_PARSER_BUSY', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 'CPG_PERF_SEL_MIU_READ_REQUEST_SENT', + 'CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT', + 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 'CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS', + 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', + 'CP_ALPHA_TAG_RAM_SEL', 'CP_ME_ID', 'CP_PERFMON_ENABLE_MODE', + 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', + 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', + 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 'CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', + 'CRTC_ADD_PIXEL', 'CRTC_ADD_PIXEL_FORCE', 'CRTC_ADD_PIXEL_NOOP', + 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN', + 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE', + 'CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE', + 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE', + 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE', + 'CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE', + 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL', + 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE', + 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST', + 'CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED', + 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE', + 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE', + 'CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE', + 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL', + 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP', + 'CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL', + 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY', + 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE', + 'CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE', + 'CRTC_CONTROL_CRTC_MASTER_EN', + 'CRTC_CONTROL_CRTC_MASTER_EN_FALSE', + 'CRTC_CONTROL_CRTC_MASTER_EN_TRUE', + 'CRTC_CONTROL_CRTC_SOF_PULL_EN', + 'CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE', + 'CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE', + 'CRTC_CONTROL_CRTC_START_POINT_CNTL', + 'CRTC_CONTROL_CRTC_START_POINT_CNTL_DP', + 'CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL', + 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN', + 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE', + 'CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE', + 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN', + 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE', + 'CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE', + 'CRTC_CRC_CNTL_CRTC_CRC_EN', 'CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE', + 'CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE', + 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE', + 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD', + 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM', + 'CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP', + 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE', + 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES', + 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS', + 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT', + 'CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT', + 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS', + 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 'CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB', + 'CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE', + 'CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE', + 'CRTC_DROP_PIXEL', 'CRTC_DROP_PIXEL_FORCE', + 'CRTC_DROP_PIXEL_NOOP', 'CRTC_DRR_MODE_DBUF_UPDATE_MODE', + 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE', + 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL', + 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF', + 'CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF', + 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN', + 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE', + 'CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE', + 'CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE', + 'CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE', + 'CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE', + 'CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE', + 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT', + 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE', + 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE', + 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY', + 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE', + 'CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 'CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 'CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE', + 'CRTC_HORZ_REPETITION_COUNT', 'CRTC_HORZ_REPETITION_COUNT_0', + 'CRTC_HORZ_REPETITION_COUNT_1', 'CRTC_HORZ_REPETITION_COUNT_10', + 'CRTC_HORZ_REPETITION_COUNT_11', 'CRTC_HORZ_REPETITION_COUNT_12', + 'CRTC_HORZ_REPETITION_COUNT_13', 'CRTC_HORZ_REPETITION_COUNT_14', + 'CRTC_HORZ_REPETITION_COUNT_15', 'CRTC_HORZ_REPETITION_COUNT_2', + 'CRTC_HORZ_REPETITION_COUNT_3', 'CRTC_HORZ_REPETITION_COUNT_4', + 'CRTC_HORZ_REPETITION_COUNT_5', 'CRTC_HORZ_REPETITION_COUNT_6', + 'CRTC_HORZ_REPETITION_COUNT_7', 'CRTC_HORZ_REPETITION_COUNT_8', + 'CRTC_HORZ_REPETITION_COUNT_9', 'CRTC_H_SYNC_A_POL', + 'CRTC_H_SYNC_A_POL_HIGH', 'CRTC_H_SYNC_A_POL_LOW', + 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL', + 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE', + 'CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2', + 'CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK', + 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE', + 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE', + 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE', + 'CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE', + 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE', + 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 'CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', + 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE', + 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG', + 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE', + 'CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL', + 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR', + 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE', + 'CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE', + 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR', + 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE', + 'CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE', + 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL', + 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', + 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 'CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR', + 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE', + 'CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE', + 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY', + 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE', + 'CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE', + 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN', + 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE', + 'CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE', + 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN', + 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE', + 'CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE', + 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY', + 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE', + 'CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 'CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE', + 'CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE', + 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE', + 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT', + 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO', + 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED', + 'CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601', + 'CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER', + 'CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER', + 'CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB', + 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK', + 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE', + 'CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 'CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 'CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 'CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', + 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE', + 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE', + 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED', + 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 'CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR', + 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 'CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', + 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE', + 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE', + 'CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE', + 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR', + 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE', + 'CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE', + 'CRTC_V_SYNC_A_POL', 'CRTC_V_SYNC_A_POL_HIGH', + 'CRTC_V_SYNC_A_POL_LOW', 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL', + 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE', + 'CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE', + 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT', + 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE', + 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE', + 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC', + 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 'CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', + 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN', + 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE', + 'CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE', + 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL', + 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE', + 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE', + 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL', + 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE', + 'CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE', + 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK', + 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE', + 'CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE', + 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR', + 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE', + 'CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE', + 'CSDATA_ADDR_WIDTH', 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', + 'CSDATA_TYPE_EVENT', 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', + 'CSDATA_TYPE_TG', 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', + 'CS_DONE', 'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CmaskAddr', + 'CmaskCode', 'CmaskMode', 'ColorArray', 'ColorFormat', + 'ColorTransform', 'CombFunc', 'CompareFrag', 'CompareRef', + 'ConservativeZExport', 'CovToShaderSel', 'DACA_SOFT_RESET', + 'DACA_SOFT_RESET_0', 'DACA_SOFT_RESET_1', 'DAC_MUX_SELECT', + 'DAC_MUX_SELECT_DACA', 'DAC_MUX_SELECT_DACB', 'DB_CACHE_FLUSH', + 'DB_CACHE_FLUSH_AND_INV', 'DB_CACHE_FLUSH_AND_INV_EVENT', + 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', 'DB_CACHE_FLUSH_TS', + 'DB_CLK_SOFT_RESET', 'DB_CLK_SOFT_RESET_0', 'DB_CLK_SOFT_RESET_1', + 'DB_FLUSH_AND_INV_DB_DATA_TS', 'DB_FLUSH_AND_INV_DB_META', + 'DB_PEFF_SEL_prezl_tile_mem_stall', + 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 'DB_PERF_SEL_CB_DB_rdreq_sends', + 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 'DB_PERF_SEL_CB_DB_wrreq_sends', 'DB_PERF_SEL_DB_CB_lquad_busy', + 'DB_PERF_SEL_DB_CB_lquad_double_format', + 'DB_PERF_SEL_DB_CB_lquad_export_quads', + 'DB_PERF_SEL_DB_CB_lquad_fast_format', + 'DB_PERF_SEL_DB_CB_lquad_quads', 'DB_PERF_SEL_DB_CB_lquad_sends', + 'DB_PERF_SEL_DB_CB_lquad_slow_format', + 'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack', + 'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy', + 'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls', + 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', + 'DB_PERF_SEL_DB_SC_quad_busy', + 'DB_PERF_SEL_DB_SC_quad_double_quad', + 'DB_PERF_SEL_DB_SC_quad_lit_quad', 'DB_PERF_SEL_DB_SC_quad_sends', + 'DB_PERF_SEL_DB_SC_quad_stalls', 'DB_PERF_SEL_DB_SC_quad_tiles', + 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', + 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', + 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 'DB_PERF_SEL_DB_SC_tile_stalls', + 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 'DB_PERF_SEL_DB_SC_tile_tiles', + 'DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream', + 'DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO', + 'DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow', + 'DB_PERF_SEL_DFSM_cycles_above_watermark', + 'DB_PERF_SEL_DFSM_evicted_squads_above_watermark', + 'DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark', + 'DB_PERF_SEL_DFSM_full_cleared_squads_out', + 'DB_PERF_SEL_DFSM_fully_cleared_pixels_out', + 'DB_PERF_SEL_DFSM_fully_cleared_quads_out', + 'DB_PERF_SEL_DFSM_lit_pixels_in', + 'DB_PERF_SEL_DFSM_lit_samples_in', + 'DB_PERF_SEL_DFSM_lit_samples_out', 'DB_PERF_SEL_DFSM_quads_in', + 'DB_PERF_SEL_DFSM_squads_in', + 'DB_PERF_SEL_DFSM_stalled_by_downstream', + 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 'DB_PERF_SEL_Depth_Tile_Cache_event', + 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 'DB_PERF_SEL_Plane_Cache_flushes', + 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', + 'DB_PERF_SEL_Plane_Cache_misses', + 'DB_PERF_SEL_Plane_Cache_starves', + 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 'DB_PERF_SEL_PostZ_Samples_failing_S', + 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 'DB_PERF_SEL_PreZ_Samples_failing_S', + 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 'DB_PERF_SEL_SC_DB_quad_busy', + 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_sends', + 'DB_PERF_SEL_SC_DB_quad_squads', 'DB_PERF_SEL_SC_DB_quad_tiles', + 'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered', + 'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends', + 'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles', + 'DB_PERF_SEL_SH_quads_outstanding_sum', + 'DB_PERF_SEL_SX_DB_quad_busy', + 'DB_PERF_SEL_SX_DB_quad_double_format', + 'DB_PERF_SEL_SX_DB_quad_export_quads', + 'DB_PERF_SEL_SX_DB_quad_exports', + 'DB_PERF_SEL_SX_DB_quad_fast_format', + 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', + 'DB_PERF_SEL_SX_DB_quad_sends', + 'DB_PERF_SEL_SX_DB_quad_slow_format', + 'DB_PERF_SEL_SX_DB_quad_stalls', + 'DB_PERF_SEL_Stencil_Cache_flushes', + 'DB_PERF_SEL_Stencil_Cache_frees', + 'DB_PERF_SEL_Stencil_Cache_hits', + 'DB_PERF_SEL_Stencil_Cache_misses', + 'DB_PERF_SEL_Stencil_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', + 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_surface_stall', + 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 'DB_PERF_SEL_Z_Cache_pmask_hits', + 'DB_PERF_SEL_Z_Cache_pmask_misses', + 'DB_PERF_SEL_Z_Cache_pmask_starves', + 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 'DB_PERF_SEL_clock_main_active', + 'DB_PERF_SEL_clock_mem_export_active', + 'DB_PERF_SEL_clock_reg_active', + 'DB_PERF_SEL_depth_bounds_qtiles_culled', + 'DB_PERF_SEL_di_dt_stall', 'DB_PERF_SEL_dk_squad_busy', + 'DB_PERF_SEL_dk_squad_sends', 'DB_PERF_SEL_dk_squad_stalls', + 'DB_PERF_SEL_dk_tile_busy', 'DB_PERF_SEL_dk_tile_quad_starves', + 'DB_PERF_SEL_dk_tile_sends', 'DB_PERF_SEL_dk_tile_stalls', + 'DB_PERF_SEL_dkg_tile_rate_tile', + 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', + 'DB_PERF_SEL_dtt_sm_slot_stall', + 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', + 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', + 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_sqq_busy', + 'DB_PERF_SEL_esr_ps_sqq_stall', 'DB_PERF_SEL_esr_ps_src_in_sends', + 'DB_PERF_SEL_esr_ps_src_in_squads', + 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_stall', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_sqq_zi_busy', + 'DB_PERF_SEL_esr_sqq_zi_stall', 'DB_PERF_SEL_etr_out_busy', + 'DB_PERF_SEL_etr_out_cb_tile_stall', + 'DB_PERF_SEL_etr_out_esr_stall', + 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', + 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', + 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', + 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', + 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', + 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', + 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', + 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', + 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', + 'DB_PERF_SEL_flush_compressed_stencil', + 'DB_PERF_SEL_flush_expanded_stencil', + 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', + 'DB_PERF_SEL_flush_single_stencil', + 'DB_PERF_SEL_his_qtiles_culled', 'DB_PERF_SEL_hiz_qtiles_culled', + 'DB_PERF_SEL_hiz_tc_read_starved', + 'DB_PERF_SEL_hiz_tc_write_stall', + 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', + 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', + 'DB_PERF_SEL_planes_flushed', 'DB_PERF_SEL_postzl_full_launch', + 'DB_PERF_SEL_postzl_partial_launch', + 'DB_PERF_SEL_postzl_partial_waiting', + 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', + 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', + 'DB_PERF_SEL_postzl_src_in_sends', + 'DB_PERF_SEL_postzl_src_in_squads', + 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 'DB_PERF_SEL_postzl_src_in_stall', + 'DB_PERF_SEL_postzl_src_in_tile_rate', + 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_postzl_src_out_stall', + 'DB_PERF_SEL_postzl_tile_init_stall', + 'DB_PERF_SEL_postzl_tile_mem_stall', + 'DB_PERF_SEL_prezl_src_in_sends', + 'DB_PERF_SEL_prezl_src_in_squads', + 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 'DB_PERF_SEL_prezl_src_in_stall', + 'DB_PERF_SEL_prezl_src_in_tile_rate', + 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_prezl_src_out_stall', + 'DB_PERF_SEL_prezl_tile_init_stall', 'DB_PERF_SEL_qc_busy', + 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', + 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', + 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', + 'DB_PERF_SEL_quad_rd_mi_stall', 'DB_PERF_SEL_quad_rd_panic', + 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', + 'DB_PERF_SEL_quad_rd_tag_stall', 'DB_PERF_SEL_quad_rdret_busy', + 'DB_PERF_SEL_quad_rdret_sends', 'DB_PERF_SEL_quad_wr_acks', + 'DB_PERF_SEL_quad_wr_busy', 'DB_PERF_SEL_quad_wr_coherency_stall', + 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', + 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', + 'DB_PERF_SEL_tcp_dispatcher_flushes', + 'DB_PERF_SEL_tcp_dispatcher_reads', + 'DB_PERF_SEL_tcp_prefetcher_flushes', + 'DB_PERF_SEL_tcp_prefetcher_reads', + 'DB_PERF_SEL_tcp_preloader_flushes', + 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', + 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', + 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 'DB_PERF_SEL_tiles_decomp_on_expclear', + 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', + 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', + 'DB_PERF_SEL_tl_expand_squads', + 'DB_PERF_SEL_tl_flush_expand_squads', + 'DB_PERF_SEL_tl_in_fast_z_stall', + 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', + 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', + 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', + 'DB_PERF_SEL_tl_preZ_squads', + 'DB_PERF_SEL_tl_stencil_locked_stall', + 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', + 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', + 'DB_PERF_SEL_tl_z_fetch_stall', 'DB_PERF_SEL_ts_tc_update_stall', + 'DB_PERF_SEL_tsc_insert_summarize_stall', + 'DB_PERF_SEL_zf_plane_multicycle', 'DCCG_AUDIO_DTO0_SOURCE_SEL', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', + 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1', 'DCCG_AUDIO_DTO_SEL', + 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', + 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 'DCCG_AUDIO_DTO_USE_512FBR_DTO', + 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL', + 'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON', + 'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE', + 'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL', + 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', + 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', + 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', + 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', + 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', + 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_CRTC_SELECT', + 'DCCG_PERF_MODE_HSYNC', 'DCCG_PERF_MODE_HSYNC_NOOP', + 'DCCG_PERF_MODE_HSYNC_START', 'DCCG_PERF_MODE_VSYNC', + 'DCCG_PERF_MODE_VSYNC_NOOP', 'DCCG_PERF_MODE_VSYNC_START', + 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', + 'DCCG_PERF_SEL_CRTC0', 'DCCG_PERF_SEL_CRTC1', + 'DCCG_PERF_SEL_CRTC2', 'DCCG_PERF_SEL_CRTC3', + 'DCCG_PERF_SEL_CRTC4', 'DCCG_PERF_SEL_CRTC5', 'DCC_CT_AUTO', + 'DCC_CT_NONE', 'DCIOCHIP_2BIT_DISABLE', 'DCIOCHIP_2BIT_ENABLE', + 'DCIOCHIP_4BIT_DISABLE', 'DCIOCHIP_4BIT_ENABLE', + 'DCIOCHIP_5BIT_DISABLE', 'DCIOCHIP_5BIT_ENABLE', + 'DCIOCHIP_AUXSLAVE_PAD_MODE', 'DCIOCHIP_AUXSLAVE_PAD_MODE_AUX', + 'DCIOCHIP_AUXSLAVE_PAD_MODE_I2C', 'DCIOCHIP_AUX_CSEL0P9', + 'DCIOCHIP_AUX_CSEL1P1', 'DCIOCHIP_AUX_CSEL_DEC0P9', + 'DCIOCHIP_AUX_CSEL_DEC1P0', 'DCIOCHIP_AUX_CSEL_INC1P0', + 'DCIOCHIP_AUX_CSEL_INC1P1', 'DCIOCHIP_AUX_FALLSLEWSEL', + 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_RSEL0P9', + 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', + 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', + 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', + 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', + 'DCIOCHIP_DVO_VREFPON', 'DCIOCHIP_DVO_VREFPON_DISABLE', + 'DCIOCHIP_DVO_VREFPON_ENABLE', 'DCIOCHIP_DVO_VREFSEL', + 'DCIOCHIP_DVO_VREFSEL_EXTERNAL', 'DCIOCHIP_DVO_VREFSEL_ONCHIP', + 'DCIOCHIP_ENABLE_2BIT', 'DCIOCHIP_ENABLE_4BIT', + 'DCIOCHIP_ENABLE_5BIT', 'DCIOCHIP_GPIO_I2C_DISABLE', + 'DCIOCHIP_GPIO_I2C_DRIVE', 'DCIOCHIP_GPIO_I2C_DRIVE_HIGH', + 'DCIOCHIP_GPIO_I2C_DRIVE_LOW', 'DCIOCHIP_GPIO_I2C_EN', + 'DCIOCHIP_GPIO_I2C_ENABLE', 'DCIOCHIP_GPIO_I2C_MASK', + 'DCIOCHIP_GPIO_I2C_MASK_DISABLE', 'DCIOCHIP_GPIO_I2C_MASK_ENABLE', + 'DCIOCHIP_GPIO_MASK_EN', 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', + 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', + 'DCIOCHIP_INVERT', 'DCIOCHIP_MASIK_5BIT_DISABLE', + 'DCIOCHIP_MASIK_5BIT_ENABLE', 'DCIOCHIP_MASK', + 'DCIOCHIP_MASK_2BIT', 'DCIOCHIP_MASK_2BIT_DISABLE', + 'DCIOCHIP_MASK_2BIT_ENABLE', 'DCIOCHIP_MASK_4BIT', + 'DCIOCHIP_MASK_4BIT_DISABLE', 'DCIOCHIP_MASK_4BIT_ENABLE', + 'DCIOCHIP_MASK_5BIT', 'DCIOCHIP_MASK_DISABLE', + 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', + 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', + 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', + 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', + 'DCIOCHIP_REF_27_SRC_SEL', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', 'DCIOCHIP_SPDIF1_IMODE', + 'DCIOCHIP_SPDIF1_IMODE_OE_A', 'DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO', + 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN', + 'DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT', + 'DCIO_BL_PWM_CNTL_BL_PWM_EN', + 'DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', 'DCIO_BL_PWM_DISABLE', + 'DCIO_BL_PWM_ENABLE', 'DCIO_BL_PWM_FRACTIONAL_DISABLE', + 'DCIO_BL_PWM_FRACTIONAL_ENABLE', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', + 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', + 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', + 'DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', + 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', + 'DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 'DCIO_BL_PWM_GRP1_REG_LOCK', 'DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE', + 'DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE', + 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START', + 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 'DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', + 'DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 'DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL', + 'DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM', + 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', + 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', 'DCIO_DACA_SOFT_RESET', + 'DCIO_DACA_SOFT_RESET_ASSERT', 'DCIO_DACA_SOFT_RESET_DEASSERT', + 'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', + 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', + 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', + 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', + 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', + 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', + 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL', + 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', + 'DCIO_DBG_ASYNC_BLOCK_SEL_DCO', + 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', + 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', + 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', + 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', + 'DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', + 'DCIO_DCO_DCFE_EXT_VSYNC_MUX', 'DCIO_DCO_EXT_VSYNC_MASK', + 'DCIO_DCRXPHY_SOFT_RESET', 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', + 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', + 'DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN', + 'DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN', + 'DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN', 'DCIO_DC_GENERICA_SEL', + 'DCIO_DC_GENERICB_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', + 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL', + 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL', + 'DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP', + 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN', + 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS', + 'DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE', + 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE', + 'DCIO_DC_GPIO_MACRO_DEBUG', 'DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF', + 'DCIO_DC_GPIO_MACRO_DEBUG_NORMAL', + 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2', + 'DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3', + 'DCIO_DC_GPIO_VIP_DEBUG', 'DCIO_DC_GPIO_VIP_DEBUG_CG_BIG', + 'DCIO_DC_GPIO_VIP_DEBUG_NORMAL', 'DCIO_DC_GPU_TIMER_READ_SELECT', + 'DCIO_DC_GPU_TIMER_START_POSITION', + 'DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS', + 'DCIO_DC_PAD_EXTERN_SIG_SEL', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_MVP', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL', + 'DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA', + 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', + 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL', + 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', + 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', + 'DCIO_DPCS_INTERRUPT_TYPE', + 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', 'DCIO_DPHY_LANE_SEL', + 'DCIO_DPHY_LANE_SEL_LANE0', 'DCIO_DPHY_LANE_SEL_LANE1', + 'DCIO_DPHY_LANE_SEL_LANE2', 'DCIO_DPHY_LANE_SEL_LANE3', + 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', + 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_DSYNC_SOFT_RESET', + 'DCIO_DSYNC_SOFT_RESET_ASSERT', 'DCIO_DSYNC_SOFT_RESET_DEASSERT', + 'DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE', + 'DCIO_DVO_ALTER_MAPPING_EN_DEFAULT', 'DCIO_EXT_VSYNC_MASK_NONE', + 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', 'DCIO_EXT_VSYNC_MASK_PIPE0', + 'DCIO_EXT_VSYNC_MASK_PIPE1', 'DCIO_EXT_VSYNC_MASK_PIPE2', + 'DCIO_EXT_VSYNC_MASK_PIPE3', 'DCIO_EXT_VSYNC_MASK_PIPE4', + 'DCIO_EXT_VSYNC_MASK_PIPE5', 'DCIO_EXT_VSYNC_MUX_CRTC0', + 'DCIO_EXT_VSYNC_MUX_CRTC1', 'DCIO_EXT_VSYNC_MUX_CRTC2', + 'DCIO_EXT_VSYNC_MUX_CRTC3', 'DCIO_EXT_VSYNC_MUX_CRTC4', + 'DCIO_EXT_VSYNC_MUX_CRTC5', 'DCIO_EXT_VSYNC_MUX_GENERICB', + 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 'DCIO_GENERICA_SEL_DACA_FIELD_NUMBER', + 'DCIO_GENERICA_SEL_DACA_PIXCLK', + 'DCIO_GENERICA_SEL_DACA_STEREOSYNC', + 'DCIO_GENERICA_SEL_DACB_FIELD_NUMBER', + 'DCIO_GENERICA_SEL_DACB_PIXCLK', 'DCIO_GENERICA_SEL_DVOA_CTL3', + 'DCIO_GENERICA_SEL_DVOA_STEREOSYNC', + 'DCIO_GENERICA_SEL_GENERICA_DCCG', + 'DCIO_GENERICA_SEL_GENERICA_DPRX', + 'DCIO_GENERICA_SEL_GENERICB_DPRX', 'DCIO_GENERICA_SEL_P1_PLLCLK', + 'DCIO_GENERICA_SEL_P2_PLLCLK', 'DCIO_GENERICA_SEL_STEREOSYNC', + 'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK', + 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2', + 'DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK', + 'DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK', + 'DCIO_GENERICB_SEL_DACA_FIELD_NUMBER', + 'DCIO_GENERICB_SEL_DACA_PIXCLK', + 'DCIO_GENERICB_SEL_DACA_STEREOSYNC', + 'DCIO_GENERICB_SEL_DACB_FIELD_NUMBER', + 'DCIO_GENERICB_SEL_DACB_PIXCLK', 'DCIO_GENERICB_SEL_DVOA_CTL3', + 'DCIO_GENERICB_SEL_DVOA_STEREOSYNC', + 'DCIO_GENERICB_SEL_GENERICB_DCCG', 'DCIO_GENERICB_SEL_P1_PLLCLK', + 'DCIO_GENERICB_SEL_P2_PLLCLK', 'DCIO_GENERICB_SEL_STEREOSYNC', + 'DCIO_GENERICB_SEL_SYNCEN', 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK', + 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2', + 'DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK', + 'DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK', 'DCIO_GENLK_CLK_GSL_MASK', + 'DCIO_GENLK_CLK_GSL_MASK_NO', 'DCIO_GENLK_CLK_GSL_MASK_STEREO', + 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', + 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', + 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE', + 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', + 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', + 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', + 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', + 'DCIO_GSL0_GLOBAL_UNLOCK_SEL', + 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', + 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK', + 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION', + 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', + 'DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', + 'DCIO_GSL0_TIMING_SYNC_SEL', + 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK', + 'DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC', + 'DCIO_GSL0_TIMING_SYNC_SEL_PIPE', + 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A', + 'DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B', + 'DCIO_GSL1_GLOBAL_UNLOCK_SEL', + 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', + 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK', + 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION', + 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', + 'DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', + 'DCIO_GSL1_TIMING_SYNC_SEL', + 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK', + 'DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC', + 'DCIO_GSL1_TIMING_SYNC_SEL_PIPE', + 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A', + 'DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B', + 'DCIO_GSL2_GLOBAL_UNLOCK_SEL', + 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC', + 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK', + 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION', + 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A', + 'DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B', + 'DCIO_GSL2_TIMING_SYNC_SEL', + 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK', + 'DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC', + 'DCIO_GSL2_TIMING_SYNC_SEL_PIPE', + 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A', + 'DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B', 'DCIO_GSL_SEL', + 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', + 'DCIO_GSL_SEL_GROUP_2', 'DCIO_GSL_VSYNC_SEL', + 'DCIO_GSL_VSYNC_SEL_PIPE0', 'DCIO_GSL_VSYNC_SEL_PIPE1', + 'DCIO_GSL_VSYNC_SEL_PIPE2', 'DCIO_GSL_VSYNC_SEL_PIPE3', + 'DCIO_GSL_VSYNC_SEL_PIPE4', 'DCIO_GSL_VSYNC_SEL_PIPE5', + 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', + 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', + 'DCIO_IMPCAL_STEP_DELAY', 'DCIO_IMPCAL_STEP_DELAY_10us', + 'DCIO_IMPCAL_STEP_DELAY_11us', 'DCIO_IMPCAL_STEP_DELAY_12us', + 'DCIO_IMPCAL_STEP_DELAY_13us', 'DCIO_IMPCAL_STEP_DELAY_14us', + 'DCIO_IMPCAL_STEP_DELAY_15us', 'DCIO_IMPCAL_STEP_DELAY_16us', + 'DCIO_IMPCAL_STEP_DELAY_1us', 'DCIO_IMPCAL_STEP_DELAY_2us', + 'DCIO_IMPCAL_STEP_DELAY_3us', 'DCIO_IMPCAL_STEP_DELAY_4us', + 'DCIO_IMPCAL_STEP_DELAY_5us', 'DCIO_IMPCAL_STEP_DELAY_6us', + 'DCIO_IMPCAL_STEP_DELAY_7us', 'DCIO_IMPCAL_STEP_DELAY_8us', + 'DCIO_IMPCAL_STEP_DELAY_9us', 'DCIO_LVTMA_BLON_OFF', + 'DCIO_LVTMA_BLON_ON', 'DCIO_LVTMA_BLON_POL_INVERT', + 'DCIO_LVTMA_BLON_POL_NON_INVERT', 'DCIO_LVTMA_DIGON_OFF', + 'DCIO_LVTMA_DIGON_ON', 'DCIO_LVTMA_DIGON_POL_INVERT', + 'DCIO_LVTMA_DIGON_POL_NON_INVERT', + 'DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL', + 'DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL', + 'DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE', + 'DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN', + 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE', + 'DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE', + 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF', + 'DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON', + 'DCIO_LVTMA_SYNCEN_POL_INVERT', + 'DCIO_LVTMA_SYNCEN_POL_NON_INVERT', + 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON', + 'DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE', + 'DCIO_MVP_PIXEL_SRC_STATUS_CRTC', + 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA', + 'DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE', + 'DCIO_MVP_PIXEL_SRC_STATUS_LB', 'DCIO_SWAPLOCK_A_GSL_MASK', + 'DCIO_SWAPLOCK_A_GSL_MASK_NO', 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', + 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', + 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SCLK', + 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', + 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', + 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', + 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', + 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', + 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', + 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHYLPA_FBDIV_CLK', + 'DCIO_UNIPHYLPA_FBDIV_SSC_CLK', + 'DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYLPA_TEST_REFDIV_CLK', 'DCIO_UNIPHYLPB_FBDIV_CLK', + 'DCIO_UNIPHYLPB_FBDIV_SSC_CLK', + 'DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYLPB_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', + 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', + 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', + 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', + 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', + 'DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS', + 'DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS', + 'DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE', + 'DCIO_VIP_ALTER_MAPPING_EN_DEFAULT', 'DCIO_VIP_MUX_EN_DVO', + 'DCIO_VIP_MUX_EN_VIP', 'DCO_DBG_BLOCK_SEL', + 'DCO_DBG_BLOCK_SEL_ABM', 'DCO_DBG_BLOCK_SEL_AUDIO_OUT', + 'DCO_DBG_BLOCK_SEL_AUX0', 'DCO_DBG_BLOCK_SEL_AUX1', + 'DCO_DBG_BLOCK_SEL_AUX2', 'DCO_DBG_BLOCK_SEL_AUX3', + 'DCO_DBG_BLOCK_SEL_AUX4', 'DCO_DBG_BLOCK_SEL_AUX5', + 'DCO_DBG_BLOCK_SEL_DAC', 'DCO_DBG_BLOCK_SEL_DCO', + 'DCO_DBG_BLOCK_SEL_DIGA', 'DCO_DBG_BLOCK_SEL_DIGB', + 'DCO_DBG_BLOCK_SEL_DIGC', 'DCO_DBG_BLOCK_SEL_DIGD', + 'DCO_DBG_BLOCK_SEL_DIGE', 'DCO_DBG_BLOCK_SEL_DIGF', + 'DCO_DBG_BLOCK_SEL_DIGFE_A', 'DCO_DBG_BLOCK_SEL_DIGFE_B', + 'DCO_DBG_BLOCK_SEL_DIGFE_C', 'DCO_DBG_BLOCK_SEL_DIGFE_D', + 'DCO_DBG_BLOCK_SEL_DIGFE_E', 'DCO_DBG_BLOCK_SEL_DIGFE_F', + 'DCO_DBG_BLOCK_SEL_DIGFE_G', 'DCO_DBG_BLOCK_SEL_DIGG', + 'DCO_DBG_BLOCK_SEL_DIGLPA', 'DCO_DBG_BLOCK_SEL_DIGLPB', + 'DCO_DBG_BLOCK_SEL_DIGLPFEA', 'DCO_DBG_BLOCK_SEL_DIGLPFEB', + 'DCO_DBG_BLOCK_SEL_DPA', 'DCO_DBG_BLOCK_SEL_DPB', + 'DCO_DBG_BLOCK_SEL_DPC', 'DCO_DBG_BLOCK_SEL_DPD', + 'DCO_DBG_BLOCK_SEL_DPE', 'DCO_DBG_BLOCK_SEL_DPF', + 'DCO_DBG_BLOCK_SEL_DPFE_A', 'DCO_DBG_BLOCK_SEL_DPFE_B', + 'DCO_DBG_BLOCK_SEL_DPFE_C', 'DCO_DBG_BLOCK_SEL_DPFE_D', + 'DCO_DBG_BLOCK_SEL_DPFE_E', 'DCO_DBG_BLOCK_SEL_DPFE_F', + 'DCO_DBG_BLOCK_SEL_DPFE_G', 'DCO_DBG_BLOCK_SEL_DPG', + 'DCO_DBG_BLOCK_SEL_DPLPA', 'DCO_DBG_BLOCK_SEL_DPLPB', + 'DCO_DBG_BLOCK_SEL_DPLPFEA', 'DCO_DBG_BLOCK_SEL_DPLPFEB', + 'DCO_DBG_BLOCK_SEL_DVO', 'DCO_DBG_BLOCK_SEL_FMT0', + 'DCO_DBG_BLOCK_SEL_FMT1', 'DCO_DBG_BLOCK_SEL_FMT2', + 'DCO_DBG_BLOCK_SEL_FMT3', 'DCO_DBG_BLOCK_SEL_FMT4', + 'DCO_DBG_BLOCK_SEL_FMT5', 'DCO_DBG_BLOCK_SEL_MVP', + 'DCO_DBG_BLOCK_SEL_PERFMON_DCO', + 'DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE', + 'DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 'DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', + 'DCP_ALPHA_ROUND_TRUNC_MODE', 'DCP_ALPHA_ROUND_TRUNC_MODE_ROUND', + 'DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC', 'DCP_CRC_ENABLE', + 'DCP_CRC_ENABLE_FALSE', 'DCP_CRC_ENABLE_TRUE', 'DCP_CRC_LINE_SEL', + 'DCP_CRC_LINE_SEL_BOTH', 'DCP_CRC_LINE_SEL_EVEN', + 'DCP_CRC_LINE_SEL_ODD', 'DCP_CRC_LINE_SEL_RESERVED', + 'DCP_CRC_SOURCE_SEL', 'DCP_CRC_SOURCE_SEL_INPUT_H32', + 'DCP_CRC_SOURCE_SEL_INPUT_L32', 'DCP_CRC_SOURCE_SEL_OUTPUT_CNTL', + 'DCP_CRC_SOURCE_SEL_OUTPUT_PIX', 'DCP_CUR2_INV_TRANS_CLAMP', + 'DCP_CUR2_INV_TRANS_CLAMP_FALSE', 'DCP_CUR2_INV_TRANS_CLAMP_TRUE', + 'DCP_CURSOR_2X_MAGNIFY', 'DCP_CURSOR_2X_MAGNIFY_FALSE', + 'DCP_CURSOR_2X_MAGNIFY_TRUE', 'DCP_CURSOR_ALPHA_BLND_ENA', + 'DCP_CURSOR_ALPHA_BLND_ENA_FALSE', + 'DCP_CURSOR_ALPHA_BLND_ENA_TRUE', 'DCP_CURSOR_DEGAMMA_MODE', + 'DCP_CURSOR_DEGAMMA_MODE_BYPASS', + 'DCP_CURSOR_DEGAMMA_MODE_RESERVED', + 'DCP_CURSOR_DEGAMMA_MODE_ROMA', 'DCP_CURSOR_DEGAMMA_MODE_ROMB', + 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE', + 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE', + 'DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE', 'DCP_CURSOR_EN', + 'DCP_CURSOR_EN_FALSE', 'DCP_CURSOR_EN_TRUE', + 'DCP_CURSOR_FORCE_MC_ON', 'DCP_CURSOR_FORCE_MC_ON_FALSE', + 'DCP_CURSOR_FORCE_MC_ON_TRUE', + 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM', + 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE', + 'DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO', 'DCP_CURSOR_MODE', + 'DCP_CURSOR_MODE_24BPP_1BIT', + 'DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI', + 'DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI', + 'DCP_CURSOR_MODE_MONO_2BPP', 'DCP_CURSOR_STEREO_EN', + 'DCP_CURSOR_STEREO_EN_FALSE', 'DCP_CURSOR_STEREO_EN_TRUE', + 'DCP_CURSOR_STEREO_OFFSET_YNX', + 'DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION', + 'DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION', + 'DCP_CURSOR_UPDATE_LOCK', 'DCP_CURSOR_UPDATE_LOCK_FALSE', + 'DCP_CURSOR_UPDATE_LOCK_TRUE', 'DCP_CURSOR_UPDATE_PENDING', + 'DCP_CURSOR_UPDATE_PENDING_FALSE', + 'DCP_CURSOR_UPDATE_PENDING_TRUE', 'DCP_CURSOR_UPDATE_STEREO_MODE', + 'DCP_CURSOR_UPDATE_STEREO_MODE_BOTH', + 'DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY', + 'DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY', + 'DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED', + 'DCP_CURSOR_UPDATE_TAKEN', 'DCP_CURSOR_UPDATE_TAKEN_FALSE', + 'DCP_CURSOR_UPDATE_TAKEN_TRUE', 'DCP_CURSOR_URGENT_CONTROL', + 'DCP_CURSOR_URGENT_CONTROL_MODE_0', + 'DCP_CURSOR_URGENT_CONTROL_MODE_1', + 'DCP_CURSOR_URGENT_CONTROL_MODE_2', + 'DCP_CURSOR_URGENT_CONTROL_MODE_3', + 'DCP_CURSOR_URGENT_CONTROL_MODE_4', 'DCP_CUR_INV_TRANS_CLAMP', + 'DCP_CUR_INV_TRANS_CLAMP_FALSE', 'DCP_CUR_INV_TRANS_CLAMP_TRUE', + 'DCP_CUR_REQUEST_FILTER_DIS', 'DCP_CUR_REQUEST_FILTER_DIS_FALSE', + 'DCP_CUR_REQUEST_FILTER_DIS_TRUE', 'DCP_DC_LUT_AUTOFILL', + 'DCP_DC_LUT_AUTOFILL_DONE', 'DCP_DC_LUT_AUTOFILL_DONE_FALSE', + 'DCP_DC_LUT_AUTOFILL_DONE_TRUE', 'DCP_DC_LUT_AUTOFILL_FALSE', + 'DCP_DC_LUT_AUTOFILL_TRUE', 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN', + 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE', + 'DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE', + 'DCP_DC_LUT_DATA_B_FORMAT', 'DCP_DC_LUT_DATA_B_FORMAT_S1P10', + 'DCP_DC_LUT_DATA_B_FORMAT_U0P10', + 'DCP_DC_LUT_DATA_B_FORMAT_U0P12', + 'DCP_DC_LUT_DATA_B_FORMAT_U1P11', 'DCP_DC_LUT_DATA_B_SIGNED_EN', + 'DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE', + 'DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE', + 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN', + 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE', + 'DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE', + 'DCP_DC_LUT_DATA_G_FORMAT', 'DCP_DC_LUT_DATA_G_FORMAT_S1P10', + 'DCP_DC_LUT_DATA_G_FORMAT_U0P10', + 'DCP_DC_LUT_DATA_G_FORMAT_U0P12', + 'DCP_DC_LUT_DATA_G_FORMAT_U1P11', 'DCP_DC_LUT_DATA_G_SIGNED_EN', + 'DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE', + 'DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE', + 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN', + 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE', + 'DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE', + 'DCP_DC_LUT_DATA_R_FORMAT', 'DCP_DC_LUT_DATA_R_FORMAT_S1P10', + 'DCP_DC_LUT_DATA_R_FORMAT_U0P10', + 'DCP_DC_LUT_DATA_R_FORMAT_U0P12', + 'DCP_DC_LUT_DATA_R_FORMAT_U1P11', 'DCP_DC_LUT_DATA_R_SIGNED_EN', + 'DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE', + 'DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE', 'DCP_DC_LUT_INC_B', + 'DCP_DC_LUT_INC_B_128', 'DCP_DC_LUT_INC_B_16', + 'DCP_DC_LUT_INC_B_2', 'DCP_DC_LUT_INC_B_256', + 'DCP_DC_LUT_INC_B_32', 'DCP_DC_LUT_INC_B_4', + 'DCP_DC_LUT_INC_B_512', 'DCP_DC_LUT_INC_B_64', + 'DCP_DC_LUT_INC_B_8', 'DCP_DC_LUT_INC_B_NA', 'DCP_DC_LUT_INC_G', + 'DCP_DC_LUT_INC_G_128', 'DCP_DC_LUT_INC_G_16', + 'DCP_DC_LUT_INC_G_2', 'DCP_DC_LUT_INC_G_256', + 'DCP_DC_LUT_INC_G_32', 'DCP_DC_LUT_INC_G_4', + 'DCP_DC_LUT_INC_G_512', 'DCP_DC_LUT_INC_G_64', + 'DCP_DC_LUT_INC_G_8', 'DCP_DC_LUT_INC_G_NA', 'DCP_DC_LUT_INC_R', + 'DCP_DC_LUT_INC_R_128', 'DCP_DC_LUT_INC_R_16', + 'DCP_DC_LUT_INC_R_2', 'DCP_DC_LUT_INC_R_256', + 'DCP_DC_LUT_INC_R_32', 'DCP_DC_LUT_INC_R_4', + 'DCP_DC_LUT_INC_R_512', 'DCP_DC_LUT_INC_R_64', + 'DCP_DC_LUT_INC_R_8', 'DCP_DC_LUT_INC_R_NA', 'DCP_DC_LUT_RW_MODE', + 'DCP_DC_LUT_RW_MODE_256_ENTRY', 'DCP_DC_LUT_RW_MODE_PWL', + 'DCP_DC_LUT_VGA_ACCESS_ENABLE', + 'DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE', + 'DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE', 'DCP_DENORM_14BIT_OUT', + 'DCP_DENORM_14BIT_OUT_FALSE', 'DCP_DENORM_14BIT_OUT_TRUE', + 'DCP_DENORM_MODE', 'DCP_DENORM_MODE_10BIT', + 'DCP_DENORM_MODE_11BIT', 'DCP_DENORM_MODE_12BIT', + 'DCP_DENORM_MODE_6BIT', 'DCP_DENORM_MODE_8BIT', + 'DCP_DENORM_MODE_RESERVED0', 'DCP_DENORM_MODE_RESERVED1', + 'DCP_DENORM_MODE_UNITY', 'DCP_FRAME_RANDOM_ENABLE', + 'DCP_FRAME_RANDOM_ENABLE_FALSE', 'DCP_FRAME_RANDOM_ENABLE_TRUE', + 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE', + 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE', + 'DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE', + 'DCP_GRPH_ALPHA_CROSSBAR', 'DCP_GRPH_ALPHA_CROSSBAR_FROM_A', + 'DCP_GRPH_ALPHA_CROSSBAR_FROM_B', + 'DCP_GRPH_ALPHA_CROSSBAR_FROM_G', + 'DCP_GRPH_ALPHA_CROSSBAR_FROM_R', 'DCP_GRPH_BLUE_CROSSBAR', + 'DCP_GRPH_BLUE_CROSSBAR_FROM_A', 'DCP_GRPH_BLUE_CROSSBAR_FROM_B', + 'DCP_GRPH_BLUE_CROSSBAR_FROM_G', 'DCP_GRPH_BLUE_CROSSBAR_FROM_R', + 'DCP_GRPH_COLOR_EXPANSION_MODE', + 'DCP_GRPH_COLOR_EXPANSION_MODE_DEXP', + 'DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP', 'DCP_GRPH_DEGAMMA_MODE', + 'DCP_GRPH_DEGAMMA_MODE_BYPASS', 'DCP_GRPH_DEGAMMA_MODE_RESERVED', + 'DCP_GRPH_DEGAMMA_MODE_ROMA', 'DCP_GRPH_DEGAMMA_MODE_ROMB', + 'DCP_GRPH_DEPTH', 'DCP_GRPH_DEPTH_16BPP', 'DCP_GRPH_DEPTH_32BPP', + 'DCP_GRPH_DEPTH_64BPP', 'DCP_GRPH_DEPTH_8BPP', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7', + 'DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8', 'DCP_GRPH_DFQ_RESET', + 'DCP_GRPH_DFQ_RESET_ACK', 'DCP_GRPH_DFQ_RESET_ACK_FALSE', + 'DCP_GRPH_DFQ_RESET_ACK_TRUE', 'DCP_GRPH_DFQ_RESET_FALSE', + 'DCP_GRPH_DFQ_RESET_TRUE', 'DCP_GRPH_DFQ_SIZE', + 'DCP_GRPH_DFQ_SIZE_DEEP1', 'DCP_GRPH_DFQ_SIZE_DEEP2', + 'DCP_GRPH_DFQ_SIZE_DEEP3', 'DCP_GRPH_DFQ_SIZE_DEEP4', + 'DCP_GRPH_DFQ_SIZE_DEEP5', 'DCP_GRPH_DFQ_SIZE_DEEP6', + 'DCP_GRPH_DFQ_SIZE_DEEP7', 'DCP_GRPH_DFQ_SIZE_DEEP8', + 'DCP_GRPH_ENABLE', 'DCP_GRPH_ENABLE_FALSE', + 'DCP_GRPH_ENABLE_TRUE', 'DCP_GRPH_ENDIAN_SWAP', + 'DCP_GRPH_ENDIAN_SWAP_8IN16', 'DCP_GRPH_ENDIAN_SWAP_8IN32', + 'DCP_GRPH_ENDIAN_SWAP_8IN64', 'DCP_GRPH_ENDIAN_SWAP_NONE', + 'DCP_GRPH_FLIP_RATE', 'DCP_GRPH_FLIP_RATE_1FRAME', + 'DCP_GRPH_FLIP_RATE_2FRAME', 'DCP_GRPH_FLIP_RATE_3FRAME', + 'DCP_GRPH_FLIP_RATE_4FRAME', 'DCP_GRPH_FLIP_RATE_5FRAME', + 'DCP_GRPH_FLIP_RATE_6FRAME', 'DCP_GRPH_FLIP_RATE_7FRAME', + 'DCP_GRPH_FLIP_RATE_8FRAME', 'DCP_GRPH_FLIP_RATE_ENABLE', + 'DCP_GRPH_FLIP_RATE_ENABLE_FALSE', + 'DCP_GRPH_FLIP_RATE_ENABLE_TRUE', 'DCP_GRPH_FORMAT', + 'DCP_GRPH_FORMAT_16BPP', 'DCP_GRPH_FORMAT_32BPP', + 'DCP_GRPH_FORMAT_64BPP', 'DCP_GRPH_FORMAT_8BPP', + 'DCP_GRPH_GAMUT_REMAP_MODE', 'DCP_GRPH_GAMUT_REMAP_MODE_BYPASS', + 'DCP_GRPH_GAMUT_REMAP_MODE_RESERVED', + 'DCP_GRPH_GAMUT_REMAP_MODE_ROMA', + 'DCP_GRPH_GAMUT_REMAP_MODE_ROMB', 'DCP_GRPH_GREEN_CROSSBAR', + 'DCP_GRPH_GREEN_CROSSBAR_FROM_A', + 'DCP_GRPH_GREEN_CROSSBAR_FROM_B', + 'DCP_GRPH_GREEN_CROSSBAR_FROM_G', + 'DCP_GRPH_GREEN_CROSSBAR_FROM_R', 'DCP_GRPH_INPUT_GAMMA_MODE', + 'DCP_GRPH_INPUT_GAMMA_MODE_BYPASS', + 'DCP_GRPH_INPUT_GAMMA_MODE_LUT', 'DCP_GRPH_KEYER_ALPHA_SEL', + 'DCP_GRPH_KEYER_ALPHA_SEL_FALSE', 'DCP_GRPH_KEYER_ALPHA_SEL_TRUE', + 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN', + 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE', + 'DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE', + 'DCP_GRPH_LUT_10BIT_BYPASS_EN', + 'DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE', + 'DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE', + 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE', + 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE', + 'DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE', + 'DCP_GRPH_MODE_UPDATE_PENDING', + 'DCP_GRPH_MODE_UPDATE_PENDING_FALSE', + 'DCP_GRPH_MODE_UPDATE_PENDING_TRUE', 'DCP_GRPH_MODE_UPDATE_TAKEN', + 'DCP_GRPH_MODE_UPDATE_TAKEN_FALSE', + 'DCP_GRPH_MODE_UPDATE_TAKEN_TRUE', 'DCP_GRPH_NUM_BANKS', + 'DCP_GRPH_NUM_BANKS_16BANK', 'DCP_GRPH_NUM_BANKS_1BANK', + 'DCP_GRPH_NUM_BANKS_2BANK', 'DCP_GRPH_NUM_BANKS_4BANK', + 'DCP_GRPH_NUM_BANKS_8BANK', 'DCP_GRPH_NUM_PIPES', + 'DCP_GRPH_NUM_PIPES_1PIPE', 'DCP_GRPH_NUM_PIPES_2PIPE', + 'DCP_GRPH_NUM_PIPES_4PIPE', 'DCP_GRPH_NUM_PIPES_8PIPE', + 'DCP_GRPH_PFLIP_INT_CLEAR', 'DCP_GRPH_PFLIP_INT_CLEAR_FALSE', + 'DCP_GRPH_PFLIP_INT_CLEAR_TRUE', 'DCP_GRPH_PFLIP_INT_MASK', + 'DCP_GRPH_PFLIP_INT_MASK_FALSE', 'DCP_GRPH_PFLIP_INT_MASK_TRUE', + 'DCP_GRPH_PFLIP_INT_TYPE', 'DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL', + 'DCP_GRPH_PFLIP_INT_TYPE_PULSE', 'DCP_GRPH_PRESCALE_BYPASS', + 'DCP_GRPH_PRESCALE_BYPASS_FALSE', 'DCP_GRPH_PRESCALE_BYPASS_TRUE', + 'DCP_GRPH_PRESCALE_B_SIGN', 'DCP_GRPH_PRESCALE_B_SIGN_SIGNED', + 'DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED', 'DCP_GRPH_PRESCALE_G_SIGN', + 'DCP_GRPH_PRESCALE_G_SIGN_SIGNED', + 'DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED', 'DCP_GRPH_PRESCALE_R_SIGN', + 'DCP_GRPH_PRESCALE_R_SIGN_SIGNED', + 'DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED', 'DCP_GRPH_PRESCALE_SELECT', + 'DCP_GRPH_PRESCALE_SELECT_FIXED', + 'DCP_GRPH_PRESCALE_SELECT_FLOATING', + 'DCP_GRPH_PRIMARY_DFQ_ENABLE', + 'DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE', + 'DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE', 'DCP_GRPH_RED_CROSSBAR', + 'DCP_GRPH_RED_CROSSBAR_FROM_A', 'DCP_GRPH_RED_CROSSBAR_FROM_B', + 'DCP_GRPH_RED_CROSSBAR_FROM_G', 'DCP_GRPH_RED_CROSSBAR_FROM_R', + 'DCP_GRPH_REGAMMA_MODE', 'DCP_GRPH_REGAMMA_MODE_BYPASS', + 'DCP_GRPH_REGAMMA_MODE_PROGA', 'DCP_GRPH_REGAMMA_MODE_PROGB', + 'DCP_GRPH_REGAMMA_MODE_SRGB', 'DCP_GRPH_REGAMMA_MODE_XVYCC', + 'DCP_GRPH_ROTATION_ANGLE', 'DCP_GRPH_ROTATION_ANGLE_0', + 'DCP_GRPH_ROTATION_ANGLE_180', 'DCP_GRPH_ROTATION_ANGLE_270', + 'DCP_GRPH_ROTATION_ANGLE_90', 'DCP_GRPH_SECONDARY_DFQ_ENABLE', + 'DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE', + 'DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE', + 'DCP_GRPH_STEREOSYNC_FLIP_EN', + 'DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE', + 'DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE', + 'DCP_GRPH_STEREOSYNC_FLIP_MODE', + 'DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP', + 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0', + 'DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1', + 'DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET', + 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE', + 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE', + 'DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE', + 'DCP_GRPH_SURFACE_COUNTER_EN', + 'DCP_GRPH_SURFACE_COUNTER_EN_DISABLE', + 'DCP_GRPH_SURFACE_COUNTER_EN_ENABLE', + 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED', + 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO', + 'DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8', + 'DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9', + 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE', + 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE', + 'DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE', + 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK', + 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE', + 'DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE', + 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN', + 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE', + 'DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE', + 'DCP_GRPH_SURFACE_UPDATE_PENDING', + 'DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE', + 'DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE', + 'DCP_GRPH_SURFACE_UPDATE_TAKEN', + 'DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE', + 'DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE', + 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE', + 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE', + 'DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE', 'DCP_GRPH_SW_MODE', + 'DCP_GRPH_SW_MODE_0', 'DCP_GRPH_SW_MODE_2', 'DCP_GRPH_SW_MODE_22', + 'DCP_GRPH_SW_MODE_23', 'DCP_GRPH_SW_MODE_26', + 'DCP_GRPH_SW_MODE_27', 'DCP_GRPH_SW_MODE_3', + 'DCP_GRPH_SW_MODE_30', 'DCP_GRPH_SW_MODE_31', + 'DCP_GRPH_UPDATE_LOCK', 'DCP_GRPH_UPDATE_LOCK_FALSE', + 'DCP_GRPH_UPDATE_LOCK_TRUE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE', + 'DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE', + 'DCP_GRPH_XDMA_DRR_MODE_ENABLE', + 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE', + 'DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE', + 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK', + 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE', + 'DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE', + 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK', + 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE', + 'DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE', + 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR', + 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE', + 'DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE', + 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE', + 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE', + 'DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE', + 'DCP_GRPH_XDMA_SUPER_AA_EN', 'DCP_GRPH_XDMA_SUPER_AA_EN_FALSE', + 'DCP_GRPH_XDMA_SUPER_AA_EN_TRUE', 'DCP_GSL0_EN', + 'DCP_GSL0_EN_FALSE', 'DCP_GSL0_EN_TRUE', 'DCP_GSL1_EN', + 'DCP_GSL1_EN_FALSE', 'DCP_GSL1_EN_TRUE', 'DCP_GSL2_EN', + 'DCP_GSL2_EN_FALSE', 'DCP_GSL2_EN_TRUE', + 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING', + 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE', + 'DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE', 'DCP_GSL_MASTER_EN', + 'DCP_GSL_MASTER_EN_FALSE', 'DCP_GSL_MASTER_EN_TRUE', + 'DCP_GSL_SYNC_SOURCE', 'DCP_GSL_SYNC_SOURCE_FLIP', + 'DCP_GSL_SYNC_SOURCE_PHASE0', 'DCP_GSL_SYNC_SOURCE_PHASE1', + 'DCP_GSL_SYNC_SOURCE_RESET', + 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC', + 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS', + 'DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN', 'DCP_GSL_XDMA_GROUP', + 'DCP_GSL_XDMA_GROUP_HSYNC0', 'DCP_GSL_XDMA_GROUP_HSYNC1', + 'DCP_GSL_XDMA_GROUP_HSYNC2', 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN', + 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE', + 'DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE', + 'DCP_GSL_XDMA_GROUP_VSYNC', 'DCP_HIGHPASS_RANDOM_ENABLE', + 'DCP_HIGHPASS_RANDOM_ENABLE_FALSE', + 'DCP_HIGHPASS_RANDOM_ENABLE_TRUE', 'DCP_INPUT_CSC_GRPH_MODE', + 'DCP_INPUT_CSC_GRPH_MODE_BYPASS', + 'DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF', + 'DCP_INPUT_CSC_GRPH_MODE_RESERVED', + 'DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF', 'DCP_KEY_MODE', + 'DCP_KEY_MODE_ALPHA0', 'DCP_KEY_MODE_ALPHA1', + 'DCP_KEY_MODE_IN_RANGE_ALPHA0', 'DCP_KEY_MODE_IN_RANGE_ALPHA1', + 'DCP_OUTPUT_CSC_GRPH_MODE', 'DCP_OUTPUT_CSC_GRPH_MODE_BYPASS', + 'DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF', + 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0', + 'DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1', + 'DCP_OUTPUT_CSC_GRPH_MODE_RGB', + 'DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF', + 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601', + 'DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709', 'DCP_OUT_ROUND_TRUNC_MODE', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_10', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_11', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_12', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_13', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_14', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_8', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_9', + 'DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9', + 'DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED', + 'DCP_RGB_RANDOM_ENABLE', 'DCP_RGB_RANDOM_ENABLE_FALSE', + 'DCP_RGB_RANDOM_ENABLE_TRUE', 'DCP_SPATIAL_DITHER_DEPTH', + 'DCP_SPATIAL_DITHER_DEPTH_24BPP', + 'DCP_SPATIAL_DITHER_DEPTH_30BPP', + 'DCP_SPATIAL_DITHER_DEPTH_36BPP', + 'DCP_SPATIAL_DITHER_DEPTH_UNDEFINED', 'DCP_SPATIAL_DITHER_EN', + 'DCP_SPATIAL_DITHER_EN_FALSE', 'DCP_SPATIAL_DITHER_EN_TRUE', + 'DCP_SPATIAL_DITHER_MODE', 'DCP_SPATIAL_DITHER_MODE_BYPASS', + 'DCP_SPATIAL_DITHER_MODE_RESERVED', + 'DCP_SPATIAL_DITHER_MODE_ROMA', 'DCP_SPATIAL_DITHER_MODE_ROMB', + 'DCP_TEST_DEBUG_WRITE_EN', 'DCP_TEST_DEBUG_WRITE_EN_FALSE', + 'DCP_TEST_DEBUG_WRITE_EN_TRUE', 'DC_MEM_GLOBAL_PWR_REQ_DIS', + 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 'DEGAMMA_MODE_A', 'DEGAMMA_MODE_B', 'DEGAMMA_MODE_BYPASS', + 'DENORM_CLAMP_MODE_10', 'DENORM_CLAMP_MODE_12', + 'DENORM_CLAMP_MODE_8', 'DENORM_CLAMP_MODE_UNITY', 'DEPTH_16', + 'DEPTH_32_FLOAT', 'DEPTH_8_24', 'DEPTH_8_24_FLOAT', + 'DEPTH_INVALID', 'DEPTH_X24_8_32_FLOAT', 'DEPTH_X8_24', + 'DEPTH_X8_24_FLOAT', 'DFSMFlushEvents', 'DIGA_BE_SOFT_RESET', + 'DIGA_BE_SOFT_RESET_0', 'DIGA_BE_SOFT_RESET_1', + 'DIGA_FE_SOFT_RESET', 'DIGA_FE_SOFT_RESET_0', + 'DIGA_FE_SOFT_RESET_1', 'DIGB_BE_SOFT_RESET', + 'DIGB_BE_SOFT_RESET_0', 'DIGB_BE_SOFT_RESET_1', + 'DIGB_FE_SOFT_RESET', 'DIGB_FE_SOFT_RESET_0', + 'DIGB_FE_SOFT_RESET_1', 'DIGC_BE_SOFT_RESET', + 'DIGC_BE_SOFT_RESET_0', 'DIGC_BE_SOFT_RESET_1', + 'DIGC_FE_SOFT_RESET', 'DIGC_FE_SOFT_RESET_0', + 'DIGC_FE_SOFT_RESET_1', 'DIGD_BE_SOFT_RESET', + 'DIGD_BE_SOFT_RESET_0', 'DIGD_BE_SOFT_RESET_1', + 'DIGD_FE_SOFT_RESET', 'DIGD_FE_SOFT_RESET_0', + 'DIGD_FE_SOFT_RESET_1', 'DIGE_BE_SOFT_RESET', + 'DIGE_BE_SOFT_RESET_0', 'DIGE_BE_SOFT_RESET_1', + 'DIGE_FE_SOFT_RESET', 'DIGE_FE_SOFT_RESET_0', + 'DIGE_FE_SOFT_RESET_1', 'DIGF_BE_SOFT_RESET', + 'DIGF_BE_SOFT_RESET_0', 'DIGF_BE_SOFT_RESET_1', + 'DIGF_FE_SOFT_RESET', 'DIGF_FE_SOFT_RESET_0', + 'DIGF_FE_SOFT_RESET_1', 'DIGG_BE_SOFT_RESET', + 'DIGG_BE_SOFT_RESET_0', 'DIGG_BE_SOFT_RESET_1', + 'DIGG_FE_SOFT_RESET', 'DIGG_FE_SOFT_RESET_0', + 'DIGG_FE_SOFT_RESET_1', 'DIGLPA_BE_SOFT_RESET', + 'DIGLPA_BE_SOFT_RESET_0', 'DIGLPA_BE_SOFT_RESET_1', + 'DIGLPA_FE_SOFT_RESET', 'DIGLPA_FE_SOFT_RESET_0', + 'DIGLPA_FE_SOFT_RESET_1', 'DIGLPB_BE_SOFT_RESET', + 'DIGLPB_BE_SOFT_RESET_0', 'DIGLPB_BE_SOFT_RESET_1', + 'DIGLPB_FE_SOFT_RESET', 'DIGLPB_FE_SOFT_RESET_0', + 'DIGLPB_FE_SOFT_RESET_1', 'DIG_10BIT_TEST_PATTERN', + 'DIG_ALTERNATING_TEST_PATTERN', 'DIG_BE_CNTL_HPD1', + 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', 'DIG_BE_CNTL_HPD4', + 'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD6', 'DIG_BE_CNTL_HPD_SELECT', + 'DIG_BE_CNTL_MODE', 'DIG_BE_DP_MST_MODE', 'DIG_BE_DP_SST_MODE', + 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', 'DIG_BE_RESERVED3', + 'DIG_BE_SDVO_RESERVED', 'DIG_BE_TMDS_DVI_MODE', + 'DIG_BE_TMDS_HDMI_MODE', 'DIG_FE_CNTL_SOURCE_SELECT', + 'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_FMT0', + 'DIG_FE_SOURCE_FROM_FMT1', 'DIG_FE_SOURCE_FROM_FMT2', + 'DIG_FE_SOURCE_FROM_FMT3', 'DIG_FE_SOURCE_FROM_FMT4', + 'DIG_FE_SOURCE_FROM_FMT5', 'DIG_FE_STEREOSYNC_FROM_FMT0', + 'DIG_FE_STEREOSYNC_FROM_FMT1', 'DIG_FE_STEREOSYNC_FROM_FMT2', + 'DIG_FE_STEREOSYNC_FROM_FMT3', 'DIG_FE_STEREOSYNC_FROM_FMT4', + 'DIG_FE_STEREOSYNC_FROM_FMT5', 'DIG_FIFO_ERROR_ACK', + 'DIG_FIFO_ERROR_ACK_INT', 'DIG_FIFO_ERROR_NOT_ACK', + 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', + 'DIG_FIFO_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_READ_CLOCK_SRC', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', + 'DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL', + 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', 'DIG_FIFO_USE_OVERWRITE_LEVEL', + 'DIG_IN_DEBUG_MODE', 'DIG_IN_NORMAL_OPERATION', + 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', 'DIG_OUTPUT_CRC_DATA_SEL', + 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', 'DIG_OUTPUT_CRC_FOR_AUDIO', + 'DIG_OUTPUT_CRC_FOR_FULLFRAME', 'DIG_OUTPUT_CRC_FOR_VBI', + 'DIG_OUTPUT_CRC_ON_LINK0', 'DIG_OUTPUT_CRC_ON_LINK1', + 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', + 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', + 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', + 'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC', + 'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO', + 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', + 'DISABLE_THE_CLOCK', 'DISABLE_THE_FEATURE', + 'DISPCLK_CHG_FWD_CORR_DISABLE', + 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', + 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', + 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DITHER_DIS', 'DITHER_EN', + 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', + 'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1', + 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ', + 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', + 'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON', + 'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', + 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', + 'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_TRI_WITH_WFLAGS', + 'DI_PT_UNUSED_1', 'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4', + 'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', + 'DI_SRC_SEL_RESERVED', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', + 'DONUTS', 'DOUT_I2C_ACK', 'DOUT_I2C_ACK_TO_CLEAN', + 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_ABORT_XFER', + 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', + 'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT', + 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO', + 'DOUT_I2C_CONTROL_NORMAL_DEBUG', + 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', + 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', + 'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDC6', + 'DOUT_I2C_CONTROL_SELECT_DDCVGA', 'DOUT_I2C_CONTROL_SEND_RESET', + 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', + 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', + 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', + 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 'DOUT_I2C_CONTROL__SEND_RESET', 'DOUT_I2C_DATA_INDEX_WRITE', + 'DOUT_I2C_DATA__INDEX_WRITE', 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', + 'DOUT_I2C_DDC_SPEED_THRESHOLD', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', + 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', + 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', + 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DOWNSCALE_PREFETCH_DIS', + 'DOWNSCALE_PREFETCH_EN', 'DPCSRX_BPHY_PCS_RX0_CLK', + 'DPCSRX_BPHY_PCS_RX1_CLK', 'DPCSRX_BPHY_PCS_RX2_CLK', + 'DPCSRX_BPHY_PCS_RX3_CLK', 'DPCSRX_DBG_CFGCLK_SEL', + 'DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER', + 'DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE', + 'DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF', + 'DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', + 'DPCSRX_DBG_RX_SYMCLK_SEL_INT', 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT0', + 'DPCSRX_DBG_RX_SYMCLK_SEL_OUT1', + 'DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL', 'DPCSRX_RX_SYMCLK_SEL', + 'DPCSTX_DBG_CFGCLK_SEL', 'DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER', + 'DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE', + 'DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF', + 'DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF', + 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD', + 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT', + 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0', + 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1', + 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2', + 'DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3', + 'DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR', + 'DPCSTX_DBG_TX_SYMCLK_SEL_IN0', 'DPCSTX_DBG_TX_SYMCLK_SEL_IN1', + 'DPCSTX_TX_SYMCLK_DIV2_SEL', 'DPCSTX_TX_SYMCLK_SEL', + 'DPDBG_CLK_FORCE_EN', 'DPDBG_CLK_FORCE_EN_DISABLE', + 'DPDBG_CLK_FORCE_EN_ENABLE', 'DPDBG_DISABLE', 'DPDBG_EN', + 'DPDBG_ENABLE', 'DPDBG_ERROR_DETECTION_MODE', + 'DPDBG_ERROR_DETECTION_MODE_CSC', + 'DPDBG_ERROR_DETECTION_MODE_RS_ENCODING', + 'DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK', + 'DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK', + 'DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE', + 'DPDBG_FIFO_OVERFLOW_INT_CLEAR', + 'DPDBG_FIFO_OVERFLOW_INT_DISABLE', + 'DPDBG_FIFO_OVERFLOW_INT_ENABLE', + 'DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED', + 'DPDBG_FIFO_OVERFLOW_INT_NO_ACK', + 'DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED', 'DPDBG_INPUT_DISABLE', + 'DPDBG_INPUT_EN', 'DPDBG_INPUT_ENABLE', 'DPDBG_SOFT_RESET', + 'DPDBG_SOFT_RESET_0', 'DPDBG_SOFT_RESET_1', 'DPHY_8B10B_CUR_DISP', + 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', + 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', + 'DPHY_8B10B_RESETET', + 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', + 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', + 'DPHY_ALT_SCRAMBLER_RESET_EN', 'DPHY_ALT_SCRAMBLER_RESET_SEL', + 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', + 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', + 'DPHY_ATEST_LANE0_PRBS_PATTERN', 'DPHY_ATEST_LANE0_REG_PATTERN', + 'DPHY_ATEST_LANE1_PRBS_PATTERN', 'DPHY_ATEST_LANE1_REG_PATTERN', + 'DPHY_ATEST_LANE2_PRBS_PATTERN', 'DPHY_ATEST_LANE2_REG_PATTERN', + 'DPHY_ATEST_LANE3_PRBS_PATTERN', 'DPHY_ATEST_LANE3_REG_PATTERN', + 'DPHY_ATEST_SEL_LANE0', 'DPHY_ATEST_SEL_LANE1', + 'DPHY_ATEST_SEL_LANE2', 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', + 'DPHY_CRC_CONTINUOUS', 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', + 'DPHY_CRC_EN', 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', + 'DPHY_CRC_LANE0_SELECTED', 'DPHY_CRC_LANE1_SELECTED', + 'DPHY_CRC_LANE2_SELECTED', 'DPHY_CRC_LANE3_SELECTED', + 'DPHY_CRC_MST_PHASE_ERROR_ACK', 'DPHY_CRC_MST_PHASE_ERROR_ACKED', + 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', + 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', + 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', + 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', + 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', + 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', + 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', + 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', + 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', + 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SCRAMBLER_ADVANCE', + 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', + 'DPHY_SCRAMBLER_DIS', 'DPHY_SCRAMBLER_KCODE', + 'DPHY_SCRAMBLER_KCODE_DISABLED', 'DPHY_SCRAMBLER_KCODE_ENABLED', + 'DPHY_SCRAMBLER_SEL', 'DPHY_SCRAMBLER_SEL_DBG_DATA', + 'DPHY_SCRAMBLER_SEL_LANE_DATA', 'DPHY_SCR_DISABLED', + 'DPHY_SCR_ENABLED', 'DPHY_SKEW_BYPASS', + 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', + 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', + 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', + 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', + 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', + 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', + 'DPREFCLK_SRC_SEL_P3PLL', 'DPRX_SD_COMPONENT_DEPTH', + 'DPRX_SD_PIXEL_ENCODING', 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', + 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', + 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', + 'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD6_SELECTED', + 'DP_AUX_CONTROL_HPD_SEL', 'DP_AUX_CONTROL_TEST_MODE', + 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 'DP_AUX_CONTROL_TEST_MODE_ENABLE', + 'DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US', + 'DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US', + 'DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', + 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', + 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', + 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', + 'DP_AUX_INT__NOT_ACK', 'DP_AUX_LS_UPDATE_ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', + 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', + 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', + 'DP_AUX_RESET_SEQUENCE_NOT_DONE', + 'DP_AUX_SW_CONTROL_LS_READ_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', + 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 'DP_COMPONENT_DEPTH', 'DP_COMPONENT_DEPTH_10BPC', + 'DP_COMPONENT_DEPTH_12BPC', 'DP_COMPONENT_DEPTH_16BPC_RESERVED', + 'DP_COMPONENT_DEPTH_6BPC', 'DP_COMPONENT_DEPTH_8BPC', + 'DP_COMPONENT_DEPTH_RESERVED', 'DP_DPHY_8B10B_EXT_DISP', + 'DP_DPHY_8B10B_EXT_DISP_ONE', 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', + 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', + 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', + 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', + 'DP_DTO_DESPREAD_DISABLE', 'DP_DTO_DESPREAD_ENABLE', + 'DP_DTO_DS_DISABLE', 'DP_DYN_CEA_RANGE', 'DP_DYN_RANGE', + 'DP_DYN_VESA_RANGE', 'DP_EMBEDDED_PANEL', + 'DP_EMBEDDED_PANEL_MODE', 'DP_EXTERNAL_PANEL', + 'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE', + 'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_MSA_MISC0_OVERRIDE_ENABLE', + 'DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE', + 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', + 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', + 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', + 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', + 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', + 'DP_MSE_OUTPUT_DPDBG_DATA', 'DP_MSE_OUTPUT_DPDBG_DATA_DIS', + 'DP_MSE_OUTPUT_DPDBG_DATA_EN', 'DP_MSE_SAT_UPDATE_ACT', + 'DP_MSE_SAT_UPDATE_NO_ACTION', + 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', + 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', + 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', + 'DP_PIXEL_ENCODING', 'DP_PIXEL_ENCODING_RESERVED', + 'DP_PIXEL_ENCODING_RGB444', 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', + 'DP_PIXEL_ENCODING_YCBCR420', 'DP_PIXEL_ENCODING_YCBCR422', + 'DP_PIXEL_ENCODING_YCBCR444', 'DP_PIXEL_ENCODING_Y_ONLY', + 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', + 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', + 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', + 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', + 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', + 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', + 'DP_SEC_GSP0_SEND', 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', + 'DP_SEC_TIMESTAMP_MODE', 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', + 'DP_STEER_OVERFLOW_ACK', 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', + 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', + 'DP_TOP_FIELD_ONLY', 'DP_TOP_PLUS_BOTTOM_FIELD', + 'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', + 'DP_UDI_4_LANES', 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', + 'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_MSA_TOP_FIELD_MODE', + 'DP_VID_M_DOUBLE_INPUT_PIXEL_RATE', 'DP_VID_M_DOUBLE_VALUE_EN', + 'DP_VID_M_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO', + 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', + 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', + 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_STREAM_DISABLE_ACK', + 'DP_VID_STREAM_DISABLE_MASK', 'DP_VID_STREAM_DIS_DEFER', + 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', + 'DP_VID_TIMING_MODE', 'DP_VID_TIMING_MODE_ASYNC', + 'DP_VID_TIMING_MODE_SYNC', 'DP_VID_VBID_FIELD_POL', + 'DP_VID_VBID_FIELD_POL_INV', 'DP_VID_VBID_FIELD_POL_NORMAL', + 'DP_YCBCR_RANGE', 'DP_YCBCR_RANGE_BT601_5', + 'DP_YCBCR_RANGE_BT709_5', 'DSI_BIT_SWAP', 'DSI_BIT_SWAP_DISABLE', + 'DSI_BIT_SWAP_ENABLE', 'DSI_CLK_GATING', 'DSI_CLK_GATING_DISABLE', + 'DSI_CLK_GATING_ENABLE', 'DSI_CLOCK_LANE_DISABLE', + 'DSI_CLOCK_LANE_EN', 'DSI_CLOCK_LANE_ENABLE', + 'DSI_CLOCK_LANE_HS_FORCE_REQUEST', + 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT', + 'DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT', + 'DSI_CMD_EMBEDDED_MODE', 'DSI_CMD_MODE_DISABLE', + 'DSI_CMD_MODE_EN', 'DSI_CMD_MODE_ENABLE', 'DSI_CMD_ORDER', + 'DSI_CMD_ORDER_COMMAND_FIRST', 'DSI_CMD_ORDER_DATA_FIRST', + 'DSI_CMD_PACKET_TYPE', 'DSI_CMD_PACKET_TYPE_LONG', + 'DSI_CMD_PACKET_TYPE_SHORT', 'DSI_CMD_PWR_MODE', + 'DSI_CMD_PWR_MODE_HS', 'DSI_CMD_PWR_MODE_LP', + 'DSI_CMD_USE_CMDFIFO', 'DSI_CMD_USE_DMAFIFO', + 'DSI_COMMAND_DST_FORMAT_RGB111', 'DSI_COMMAND_DST_FORMAT_RGB332', + 'DSI_COMMAND_DST_FORMAT_RGB444', 'DSI_COMMAND_DST_FORMAT_RGB565', + 'DSI_COMMAND_DST_FORMAT_RGB666', 'DSI_COMMAND_DST_FORMAT_RGB888', + 'DSI_COMMAND_MODE_DST_FORMAT', 'DSI_COMMAND_MODE_SRC_FORMAT', + 'DSI_COMMAND_SRC_FORMAT_RGB332', 'DSI_COMMAND_SRC_FORMAT_RGB444', + 'DSI_COMMAND_SRC_FORMAT_RGB555', 'DSI_COMMAND_SRC_FORMAT_RGB565', + 'DSI_COMMAND_SRC_FORMAT_RGB888', 'DSI_COMMAND_SRC_FORMAT_RGB8BIT', + 'DSI_COMMAND_TRIGGER_MODE', 'DSI_COMMAND_TRIGGER_MODE_AUTO', + 'DSI_COMMAND_TRIGGER_MODE_MANUAL', 'DSI_COMMAND_TRIGGER_ORDER', + 'DSI_COMMAND_TRIGGER_ORDER_DENG', 'DSI_COMMAND_TRIGGER_ORDER_DMA', + 'DSI_COMMAND_TRIGGER_SEL', 'DSI_COMMAND_TRIGGER_SEL_CRTC', + 'DSI_COMMAND_TRIGGER_SEL_HW', 'DSI_COMMAND_TRIGGER_SEL_NONE', + 'DSI_COMMAND_TRIGGER_SEL_TE', 'DSI_CONTROLLER_DISABLE', + 'DSI_CONTROLLER_EN', 'DSI_CONTROLLER_ENABLE', + 'DSI_CRC_CAL_DISABLE', 'DSI_CRC_CAL_ENABLE', 'DSI_CRC_ENABLE', + 'DSI_CRTC_FREEZE_TRIG', 'DSI_CRTC_FREEZE_TRIG_ASSERT', + 'DSI_CRTC_FREEZE_TRIG_DEASSERT', 'DSI_CRTC_SEL', + 'DSI_DATA_BUFFER_ID', 'DSI_DATA_BUFFER_OFFSET0', + 'DSI_DATA_BUFFER_OFFSET1', 'DSI_DATA_LANE0_DISABLE', + 'DSI_DATA_LANE0_EN', 'DSI_DATA_LANE0_ENABLE', + 'DSI_DATA_LANE1_DISABLE', 'DSI_DATA_LANE1_EN', + 'DSI_DATA_LANE1_ENABLE', 'DSI_DATA_LANE2_DISABLE', + 'DSI_DATA_LANE2_EN', 'DSI_DATA_LANE2_ENABLE', + 'DSI_DATA_LANE3_DISABLE', 'DSI_DATA_LANE3_EN', + 'DSI_DATA_LANE3_ENABLE', 'DSI_DBG_CLK_SEL', + 'DSI_DEBUG_BYTECLK_SEL', 'DSI_DEBUG_BYTECLK_SEL_AFIFO', + 'DSI_DEBUG_BYTECLK_SEL_EOT', 'DSI_DEBUG_BYTECLK_SEL_LANEBUF0', + 'DSI_DEBUG_BYTECLK_SEL_LANEBUF1', + 'DSI_DEBUG_BYTECLK_SEL_LANEBUF2', + 'DSI_DEBUG_BYTECLK_SEL_LANEBUF3', + 'DSI_DEBUG_BYTECLK_SEL_LANECTRL', + 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO0', + 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO1', + 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO2', + 'DSI_DEBUG_BYTECLK_SEL_LANEFIFO3', + 'DSI_DEBUG_BYTECLK_SEL_PINGPING2', + 'DSI_DEBUG_BYTECLK_SEL_PINGPING3', + 'DSI_DEBUG_BYTECLK_SEL_PINGPONG0', + 'DSI_DEBUG_BYTECLK_SEL_PINGPONG1', 'DSI_DEBUG_DSICLK_SEL', + 'DSI_DEBUG_DSICLK_SEL_AFIFO', 'DSI_DEBUG_DSICLK_SEL_CMDBUFFER', + 'DSI_DEBUG_DSICLK_SEL_CMDFIFO', 'DSI_DEBUG_DSICLK_SEL_CMD_ENGINE', + 'DSI_DEBUG_DSICLK_SEL_LANECTRL', + 'DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO', + 'DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE', + 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE', + 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT', + 'DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT', + 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX', + 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT', + 'DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT', + 'DSI_DENG_FIFO_LEVEL_CAL_AVERAGE', + 'DSI_DENG_FIFO_LEVEL_OVERWRITE', 'DSI_DENG_FIFO_START', + 'DSI_DENG_FIFO_START_ASSERT', 'DSI_DENG_FIFO_START_DEASSERT', + 'DSI_DENG_FIFO_USE_OVERWRITE_LEVEL', 'DSI_DMAFIFO_READ_WATERMARK', + 'DSI_DMAFIFO_READ_WATERMARK_EIGHTH', + 'DSI_DMAFIFO_READ_WATERMARK_FOURTH', + 'DSI_DMAFIFO_READ_WATERMARK_HALF', + 'DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH', + 'DSI_DMAFIFO_WRITE_WATERMARK', + 'DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH', + 'DSI_DMAFIFO_WRITE_WATERMARK_FOURTH', + 'DSI_DMAFIFO_WRITE_WATERMARK_HALF', + 'DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH', 'DSI_DWORD_BYTE_SWAP', + 'DSI_EXT_RESET_POL', 'DSI_EXT_RESET_POL_HIGH', + 'DSI_EXT_RESET_POL_LOW', 'DSI_EXT_TE_MODE', + 'DSI_EXT_TE_MODE_HVSYNC_EDGE', 'DSI_EXT_TE_MODE_HVSYNC_WIDTH', + 'DSI_EXT_TE_MODE_VSYNC_EDGE', 'DSI_EXT_TE_MODE_VSYNC_WIDTH', + 'DSI_EXT_TE_MUX', 'DSI_EXT_TE_POL', 'DSI_EXT_TE_POL_FALLING', + 'DSI_EXT_TE_POL_RISING', 'DSI_FLAG_CLEAR', 'DSI_FLAG_CLR', + 'DSI_FLAG_NO_CLEAR', 'DSI_GET_PIXEL_STREAM_FROM_FMT0', + 'DSI_GET_PIXEL_STREAM_FROM_FMT1', + 'DSI_GET_PIXEL_STREAM_FROM_FMT2', + 'DSI_GET_PIXEL_STREAM_FROM_FMT3', + 'DSI_GET_PIXEL_STREAM_FROM_FMT4', + 'DSI_GET_PIXEL_STREAM_FROM_FMT5', 'DSI_HW_SOURCE_SEL', + 'DSI_INSERT_DCS_COMMAND', 'DSI_INSERT_DCS_COMMAND_DISABLE', + 'DSI_INSERT_DCS_COMMAND_ENABLE', 'DSI_LANE_FORCE_TX_STOP', + 'DSI_LANE_FORCE_TX_STOP_ASSERT', + 'DSI_LANE_FORCE_TX_STOP_DEASSERT', 'DSI_LANE_ULPS_EXIT', + 'DSI_LANE_ULPS_EXIT_ASSERT', 'DSI_LANE_ULPS_EXIT_DEASSERT', + 'DSI_LANE_ULPS_REQUEST', 'DSI_LANE_ULPS_REQUEST_ASSERT', + 'DSI_LANE_ULPS_REQUEST_DEASSERT', 'DSI_MIPI_BIST_RESET', + 'DSI_MIPI_BIST_RESET_ASSERT', 'DSI_MIPI_BIST_RESET_DEASSERT', + 'DSI_MIPI_BIST_START', 'DSI_MIPI_BIST_START_ASSERT', + 'DSI_MIPI_BIST_START_DEASSERT', 'DSI_MIPI_BIST_VIDEO_FRMT', + 'DSI_MIPI_BIST_VIDEO_FRMT_RAW8', + 'DSI_MIPI_BIST_VIDEO_FRMT_YUV422', + 'DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC', + 'DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC', + 'DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC', + 'DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC', + 'DSI_PACKET_BYTE_MSB_LSB_FLIP', + 'DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP', + 'DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP', 'DSI_PERF_LATENCY_SEL', + 'DSI_PERF_LATENCY_SEL_DATA_LANE0', + 'DSI_PERF_LATENCY_SEL_DATA_LANE1', + 'DSI_PERF_LATENCY_SEL_DATA_LANE2', + 'DSI_PERF_LATENCY_SEL_DATA_LANE3', 'DSI_PHY_DATA_LANE0_DISABLE', + 'DSI_PHY_DATA_LANE0_EN', 'DSI_PHY_DATA_LANE0_ENABLE', + 'DSI_PHY_DATA_LANE1_DISABLE', 'DSI_PHY_DATA_LANE1_EN', + 'DSI_PHY_DATA_LANE1_ENABLE', 'DSI_PHY_DATA_LANE2_DISABLE', + 'DSI_PHY_DATA_LANE2_EN', 'DSI_PHY_DATA_LANE2_ENABLE', + 'DSI_PHY_DATA_LANE3_DISABLE', 'DSI_PHY_DATA_LANE3_EN', + 'DSI_PHY_DATA_LANE3_ENABLE', 'DSI_RESET_BYTECLK', + 'DSI_RESET_DISPCLK', 'DSI_RESET_DSICLK', 'DSI_RESET_ESCCLK', + 'DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC', + 'DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC', + 'DSI_RESET_ON_DSICLK_DOMAIN_LOGIC', + 'DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC', 'DSI_RESET_PANEL', + 'DSI_RESET_PANEL_ASSERT', 'DSI_RESET_PANEL_DEASSERT', + 'DSI_RGB_SWAP', 'DSI_RX_EOT_IGNORE', 'DSI_RX_EOT_IGNORE_DISABLE', + 'DSI_RX_EOT_IGNORE_ENABLE', 'DSI_SWAP_BGR', 'DSI_SWAP_BRG', + 'DSI_SWAP_GBR', 'DSI_SWAP_GRB', 'DSI_SWAP_RBG', 'DSI_SWAP_RGB', + 'DSI_TEST_CLK_SEL_BYTECLK_G', 'DSI_TEST_CLK_SEL_DISPCLK_G', + 'DSI_TEST_CLK_SEL_DISPCLK_P', 'DSI_TEST_CLK_SEL_DISPCLK_R', + 'DSI_TEST_CLK_SEL_DSICLK_G', 'DSI_TEST_CLK_SEL_DSICLK_P', + 'DSI_TEST_CLK_SEL_DSICLK_R', 'DSI_TEST_CLK_SEL_DSICLK_TRN', + 'DSI_TEST_CLK_SEL_ESCCLK_G', 'DSI_TE_SEL_LINK', 'DSI_TE_SEL_PIN', + 'DSI_TE_SRC_SEL', 'DSI_TRAFFIC_MODE_BURST', + 'DSI_TRAFFIC_MODE_RESERVED', 'DSI_TRAFFIC_MODE_SYNC_EVENTS', + 'DSI_TRAFFIC_MODE_SYNC_PULSES', 'DSI_TX_EOT_APPEND', + 'DSI_TX_EOT_APPEND_DISABLE', 'DSI_TX_EOT_APPEND_ENABLE', + 'DSI_USE_CMDFIFO', 'DSI_USE_DENG_LENGTH', + 'DSI_USE_DENG_LENGTH_DISABLE', 'DSI_USE_DENG_LENGTH_ENABLE', + 'DSI_VIDEO_BLLP_PWR_MODE', 'DSI_VIDEO_BLLP_PWR_MODE_HS', + 'DSI_VIDEO_BLLP_PWR_MODE_LP', 'DSI_VIDEO_DST_FORMAT_RGB565', + 'DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED', + 'DSI_VIDEO_DST_FORMAT_RGB666_PACKED', + 'DSI_VIDEO_DST_FORMAT_RGB888', 'DSI_VIDEO_EOF_BLLP_PWR_MODE', + 'DSI_VIDEO_EOF_BLLP_PWR_MODE_HS', + 'DSI_VIDEO_EOF_BLLP_PWR_MODE_LP', 'DSI_VIDEO_MODE_DISABLE', + 'DSI_VIDEO_MODE_DST_FORMAT', 'DSI_VIDEO_MODE_EN', + 'DSI_VIDEO_MODE_ENABLE', 'DSI_VIDEO_PULSE_MODE_OPT', + 'DSI_VIDEO_PWR_MODE', 'DSI_VIDEO_PWR_MODE_HS', + 'DSI_VIDEO_PWR_MODE_LP', 'DSI_VIDEO_TRAFFIC_MODE', + 'DSI_XT_TE_MUX_DCLK', 'DSI_XT_TE_MUX_DINV', 'DSI_XT_TE_MUX_FRAME', + 'DSI_XT_TE_MUX_GCLK', 'DSI_XT_TE_MUX_GOE', 'DSI_XT_TE_MUX_GPIO4', + 'DSI_XT_TE_MUX_GPIO5', 'DSI_XT_TE_MUX_LCDD17', 'DSI_XT_TE_MUX_SS', + 'DSM_ENABLE_ERROR_INJECT', 'DSM_ENABLE_ERROR_INJECT_DOUBLE', + 'DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED', + 'DSM_ENABLE_ERROR_INJECT_FED_IN', + 'DSM_ENABLE_ERROR_INJECT_SINGLE', 'DSM_SELECT_INJECT_DELAY', + 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', + 'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DS_REF_IS_EXT_GENLOCK', + 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', 'DS_REF_SRC', + 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKC_IN_PHASE', + 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', + 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE', + 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', + 'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', + 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST', + 'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE', + 'DVO_SOFT_RESET', 'DVO_SOFT_RESET_0', 'DVO_SOFT_RESET_1', + 'DWORD_BYTE_SWAP_BOTH_SWAP', 'DWORD_BYTE_SWAP_BYTE_SWAP', + 'DWORD_BYTE_SWAP_NO_SWAP', 'DWORD_BYTE_SWAP_WORD_SWAP', + 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', + 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', + 'DYNAMIC_PIXEL_DEPTH_30BPP', 'DYNAMIC_PIXEL_DEPTH_36BPP', + 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', + 'DbPRTFaultBehavior', 'DbPSLControl', 'DepthArray', 'DepthFormat', + 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', 'ENABLE', + 'ENABLE_CLOCK', 'ENABLE_JITTER_REMOVAL', 'ENABLE_LEGACY_PIPELINE', + 'ENABLE_MEM_PWR_CTRL', 'ENABLE_NGG_PIPELINE', 'ENABLE_THE_CLOCK', + 'ENABLE_THE_FEATURE', 'ENDIAN_8IN16', 'ENDIAN_8IN32', + 'ENDIAN_8IN64', 'ENDIAN_NONE', 'END_OF_PIPE_IB_END', + 'END_OF_PIPE_INCR_DE', 'ENUMS_GDS_PERFCOUNT_SELECT_H', + 'ENUM_NUM_SIMD_PER_CU', 'ENUM_SQ_EXPORT_RAT_INST', + 'ENUM_XDMA_LOCAL_SW_MODE', 'ENUM_XDMA_MSTR_ALPHA_POSITION', + 'ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL', + 'ENUM_XDMA_SLV_ALPHA_POSITION', 'ES_STAGE_DS', 'ES_STAGE_OFF', + 'ES_STAGE_REAL', 'EXPORT_16_16_FLOAT_8PIX', + 'EXPORT_16_16_SIGNED_8PIX', 'EXPORT_16_16_UNSIGNED_8PIX', + 'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR', + 'EXPORT_2P_32BPC_ABGR', 'EXPORT_32BPP_8PIX', 'EXPORT_32_ABGR', + 'EXPORT_32_AR', 'EXPORT_32_GR', 'EXPORT_32_R', 'EXPORT_4C_16BPC', + 'EXPORT_4C_32BPC', 'EXPORT_4P_16BPC_ABGR', 'EXPORT_4P_32BPC_ABGR', + 'EXPORT_4P_32BPC_AR', 'EXPORT_4P_32BPC_GR', 'EXPORT_8P_32BPC_R', + 'EXPORT_ANY_Z', 'EXPORT_FP16_ABGR', 'EXPORT_GREATER_THAN_Z', + 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'EXPORT_SIGNED16_ABGR', + 'EXPORT_UNSIGNED16_ABGR', 'EXPORT_UNUSED', 'FAULT_FAIL', + 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', + 'FBC_IDLE_MASK_DISP_REG_UPDATE', + 'FBC_IDLE_MASK_FBC_ALPHA_COMP_EN', + 'FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF', + 'FBC_IDLE_MASK_FBC_GRPH_COMP_EN', + 'FBC_IDLE_MASK_FBC_MIN_COMPRESSION', + 'FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN', + 'FBC_IDLE_MASK_MASK_BITS', 'FBC_IDLE_MASK_MC_HIT_REGION_0', + 'FBC_IDLE_MASK_MC_HIT_REGION_1', 'FBC_IDLE_MASK_MC_HIT_REGION_2', + 'FBC_IDLE_MASK_MC_HIT_REGION_3', 'FBC_IDLE_MASK_MC_WRITE', + 'FBC_IDLE_MASK_RESERVED1', 'FBC_IDLE_MASK_RESERVED10', + 'FBC_IDLE_MASK_RESERVED11', 'FBC_IDLE_MASK_RESERVED12', + 'FBC_IDLE_MASK_RESERVED13', 'FBC_IDLE_MASK_RESERVED14', + 'FBC_IDLE_MASK_RESERVED15', 'FBC_IDLE_MASK_RESERVED16', + 'FBC_IDLE_MASK_RESERVED17', 'FBC_IDLE_MASK_RESERVED18', + 'FBC_IDLE_MASK_RESERVED19', 'FBC_IDLE_MASK_RESERVED20', + 'FBC_IDLE_MASK_RESERVED21', 'FBC_IDLE_MASK_RESERVED22', + 'FBC_IDLE_MASK_RESERVED23', 'FBC_IDLE_MASK_RESERVED29', + 'FBC_IDLE_MASK_RESERVED30', 'FBC_IDLE_MASK_RESERVED31', + 'FBC_IDLE_MASK_RESERVED7', 'FBC_IDLE_MASK_RESERVED8', + 'FBC_IDLE_MASK_RESERVED9', 'FLUSH_AND_INV_CB_DATA_TS', + 'FLUSH_AND_INV_CB_META', 'FLUSH_AND_INV_CB_PIXEL_DATA', + 'FLUSH_AND_INV_DB_DATA_TS', 'FLUSH_AND_INV_DB_META', + 'FLUSH_CONTROL_FLUSH_NOT_STARTED', 'FLUSH_CONTROL_FLUSH_STARTED', + 'FLUSH_DFSM', 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', 'FMT0_SOFT_RESET', + 'FMT0_SOFT_RESET_0', 'FMT0_SOFT_RESET_1', 'FMT1_SOFT_RESET', + 'FMT1_SOFT_RESET_0', 'FMT1_SOFT_RESET_1', 'FMT2_SOFT_RESET', + 'FMT2_SOFT_RESET_0', 'FMT2_SOFT_RESET_1', 'FMT3_SOFT_RESET', + 'FMT3_SOFT_RESET_0', 'FMT3_SOFT_RESET_1', + 'FMT420_MEMORY_SOURCE_SEL', 'FMT420_MEMORY_SOURCE_SEL_FMT0', + 'FMT420_MEMORY_SOURCE_SEL_FMT1', 'FMT420_MEMORY_SOURCE_SEL_FMT2', + 'FMT420_MEMORY_SOURCE_SEL_FMT3', 'FMT420_MEMORY_SOURCE_SEL_FMT4', + 'FMT420_MEMORY_SOURCE_SEL_FMT5', + 'FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED', 'FMT4_SOFT_RESET', + 'FMT4_SOFT_RESET_0', 'FMT4_SOFT_RESET_1', 'FMT5_SOFT_RESET', + 'FMT5_SOFT_RESET_0', 'FMT5_SOFT_RESET_1', 'FMT_1', + 'FMT_10_10_10_2', 'FMT_10_11_11', 'FMT_10_11_11_FLOAT', + 'FMT_11_11_10', 'FMT_11_11_10_FLOAT', 'FMT_16', 'FMT_16_16', + 'FMT_16_16_16', 'FMT_16_16_16_16', 'FMT_16_16_16_16_FLOAT', + 'FMT_16_16_16_FLOAT', 'FMT_16_16_FLOAT', 'FMT_16_FLOAT', + 'FMT_1_5_5_5', 'FMT_1_REVERSED', 'FMT_24_8', 'FMT_24_8_FLOAT', + 'FMT_2_10_10_10', 'FMT_32', 'FMT_32_32', 'FMT_32_32_32', + 'FMT_32_32_32_32', 'FMT_32_32_32_32_FLOAT', 'FMT_32_32_32_FLOAT', + 'FMT_32_32_FLOAT', 'FMT_32_AS_32_32_32_32', 'FMT_32_AS_8', + 'FMT_32_AS_8_8', 'FMT_32_FLOAT', 'FMT_3_3_2', 'FMT_4_4', + 'FMT_4_4_4_4', 'FMT_5_5_5_1', 'FMT_5_6_5', + 'FMT_5_9_9_9_SHAREDEXP', 'FMT_6_5_5', 'FMT_8', 'FMT_8_24', + 'FMT_8_24_FLOAT', 'FMT_8_8', 'FMT_8_8_8', 'FMT_8_8_8_8', + 'FMT_APC3', 'FMT_APC4', 'FMT_APC5', 'FMT_APC6', 'FMT_APC7', + 'FMT_BC1', 'FMT_BC2', 'FMT_BC3', 'FMT_BC4', 'FMT_BC5', 'FMT_BC6', + 'FMT_BC7', 'FMT_BG_RG', 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 'FMT_CLAMP_CNTL_COLOR_FORMAT', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', + 'FMT_CONTROL_PIXEL_ENCODING', + 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', + 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 'FMT_CONTROL_SUBSAMPLING_MODE', + 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', + 'FMT_CONTROL_SUBSAMPLING_ORDER', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', + 'FMT_CRC_CNTL_CONT_EN', 'FMT_CRC_CNTL_CONT_EN_CONT', + 'FMT_CRC_CNTL_CONT_EN_ONE_SHOT', + 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE', + 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL', + 'FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN', + 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT', + 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN', + 'FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD', + 'FMT_CRC_CNTL_INCLUDE_OVERSCAN', + 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE', + 'FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE', + 'FMT_CRC_CNTL_INTERLACE_MODE', + 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM', + 'FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH', + 'FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM', + 'FMT_CRC_CNTL_INTERLACE_MODE_TOP', 'FMT_CRC_CNTL_ONLY_BLANKB', + 'FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD', + 'FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK', + 'FMT_CRC_CNTL_PSR_MODE_ENABLE', + 'FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC', + 'FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL', 'FMT_CTX1', + 'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', + 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', + 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', + 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE', + 'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12', + 'FMT_GB_GR', 'FMT_INVALID', 'FMT_RESERVED_33', 'FMT_RESERVED_36', + 'FMT_RESERVED_4', 'FMT_RESERVED_63', 'FMT_SPATIAL_DITHER_MODE', + 'FMT_SPATIAL_DITHER_MODE_0', 'FMT_SPATIAL_DITHER_MODE_1', + 'FMT_SPATIAL_DITHER_MODE_2', 'FMT_SPATIAL_DITHER_MODE_3', + 'FMT_STEREOSYNC_OVR_POL', 'FMT_STEREOSYNC_OVR_POL_INVERTED', + 'FMT_STEREOSYNC_OVR_POL_NOT_INVERTED', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN', + 'FMT_X24_8_32_FLOAT', 'FORCE_BINNING_ON', + 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', 'FORCE_EARLY_Z', + 'FORCE_ENABLE', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ', + 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', 'FORCE_OPT_AUTO', + 'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', + 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', + 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', + 'FORCE_VBI', 'FORCE_VBI_HIGH', 'FORCE_VBI_LOW', 'FRAG_ALWAYS', + 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER', 'FRAG_LEQUAL', + 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL', 'ForceControl', + 'GAMUT_REMAP_MODE_1', 'GAMUT_REMAP_MODE_2', 'GAMUT_REMAP_MODE_3', + 'GAMUT_REMAP_MODE_BYPASS', 'GATCL1RequestType', + 'GATCL1_TYPE_BYPASS', 'GATCL1_TYPE_NORMAL', + 'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE', + 'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT', + 'GB_EDC_DED_MODE_LOG', 'GB_TILING_CONFIG_MACROTABLE_SIZE', + 'GB_TILING_CONFIG_TABLE_SIZE', 'GDS_PERFCOUNT_SELECT', + 'GDS_PERF_SEL_DS_ADDR_CONFL', 'GDS_PERF_SEL_DS_BANK_CONFL', + 'GDS_PERF_SEL_GWS_BYPASS', 'GDS_PERF_SEL_GWS_RELEASED', + 'GDS_PERF_SEL_RBUF_HIT', 'GDS_PERF_SEL_RBUF_MISS', + 'GDS_PERF_SEL_SE0_SH0_2COMP_REQ', + 'GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE0_SH0_GDS_RD_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_REL_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE0_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH0_NORET', + 'GDS_PERF_SEL_SE0_SH0_ORD_CNT', + 'GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH0_RET', + 'GDS_PERF_SEL_SE0_SH1_2COMP_REQ', + 'GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE0_SH1_GDS_RD_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_REL_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE0_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE0_SH1_NORET', + 'GDS_PERF_SEL_SE0_SH1_ORD_CNT', + 'GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_SH1_RET', + 'GDS_PERF_SEL_SE1_SH0_2COMP_REQ', + 'GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE1_SH0_GDS_RD_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_REL_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE1_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH0_NORET', + 'GDS_PERF_SEL_SE1_SH0_ORD_CNT', + 'GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH0_RET', + 'GDS_PERF_SEL_SE1_SH1_2COMP_REQ', + 'GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE1_SH1_GDS_RD_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_REL_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE1_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE1_SH1_NORET', + 'GDS_PERF_SEL_SE1_SH1_ORD_CNT', + 'GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_SH1_RET', + 'GDS_PERF_SEL_SE2_SH0_2COMP_REQ', + 'GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE2_SH0_GDS_RD_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_REL_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE2_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH0_NORET', + 'GDS_PERF_SEL_SE2_SH0_ORD_CNT', + 'GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH0_RET', + 'GDS_PERF_SEL_SE2_SH1_2COMP_REQ', + 'GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE2_SH1_GDS_RD_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_REL_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE2_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE2_SH1_NORET', + 'GDS_PERF_SEL_SE2_SH1_ORD_CNT', + 'GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_SH1_RET', + 'GDS_PERF_SEL_SE3_SH0_2COMP_REQ', + 'GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE3_SH0_GDS_RD_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_REL_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE3_SH0_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH0_NORET', + 'GDS_PERF_SEL_SE3_SH0_ORD_CNT', + 'GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH0_RET', + 'GDS_PERF_SEL_SE3_SH1_2COMP_REQ', + 'GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID', + 'GDS_PERF_SEL_SE3_SH1_GDS_RD_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_REL_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD', + 'GDS_PERF_SEL_SE3_SH1_GDS_WR_OP', 'GDS_PERF_SEL_SE3_SH1_NORET', + 'GDS_PERF_SEL_SE3_SH1_ORD_CNT', + 'GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_SH1_RET', + 'GDS_PERF_SEL_WBUF_FLUSH', 'GDS_PERF_SEL_WBUF_WR', + 'GDS_PERF_SEL_WR_COMP', 'GENERICA_STEREOSYNC_SEL', + 'GENERICA_STEREOSYNC_SEL_D1', 'GENERICA_STEREOSYNC_SEL_D2', + 'GENERICA_STEREOSYNC_SEL_D3', 'GENERICA_STEREOSYNC_SEL_D4', + 'GENERICA_STEREOSYNC_SEL_D5', 'GENERICA_STEREOSYNC_SEL_D6', + 'GENERICA_STEREOSYNC_SEL_RESERVED', 'GENERICB_STEREOSYNC_SEL', + 'GENERICB_STEREOSYNC_SEL_D1', 'GENERICB_STEREOSYNC_SEL_D2', + 'GENERICB_STEREOSYNC_SEL_D3', 'GENERICB_STEREOSYNC_SEL_D4', + 'GENERICB_STEREOSYNC_SEL_D5', 'GENERICB_STEREOSYNC_SEL_D6', + 'GENERICB_STEREOSYNC_SEL_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', + 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', + 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', + 'GLOBAL_STATUS_FLUSH_STATUS', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', + 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', + 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', + 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', + 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', + 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', + 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_BCI_BUSY', + 'GRBM_PERF_SEL_CB_BUSY', 'GRBM_PERF_SEL_CB_CLEAN', + 'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPAXI_BUSY', + 'GRBM_PERF_SEL_CPC_BUSY', 'GRBM_PERF_SEL_CPF_BUSY', + 'GRBM_PERF_SEL_CPG_BUSY', 'GRBM_PERF_SEL_CP_BUSY', + 'GRBM_PERF_SEL_CP_COHER_BUSY', 'GRBM_PERF_SEL_CP_DMA_BUSY', + 'GRBM_PERF_SEL_DB_BUSY', 'GRBM_PERF_SEL_DB_CLEAN', + 'GRBM_PERF_SEL_EA_BUSY', 'GRBM_PERF_SEL_GDS_BUSY', + 'GRBM_PERF_SEL_GUI_ACTIVE', 'GRBM_PERF_SEL_IA_BUSY', + 'GRBM_PERF_SEL_IA_NO_DMA_BUSY', 'GRBM_PERF_SEL_PA_BUSY', + 'GRBM_PERF_SEL_RESERVED_0', 'GRBM_PERF_SEL_RESERVED_1', + 'GRBM_PERF_SEL_RESERVED_2', 'GRBM_PERF_SEL_RESERVED_3', + 'GRBM_PERF_SEL_RESERVED_4', 'GRBM_PERF_SEL_RESERVED_5', + 'GRBM_PERF_SEL_RESERVED_6', 'GRBM_PERF_SEL_RLC_BUSY', + 'GRBM_PERF_SEL_RMI_BUSY', 'GRBM_PERF_SEL_SC_BUSY', + 'GRBM_PERF_SEL_SPI_BUSY', 'GRBM_PERF_SEL_SX_BUSY', + 'GRBM_PERF_SEL_TA_BUSY', 'GRBM_PERF_SEL_TC_BUSY', + 'GRBM_PERF_SEL_USER_DEFINED', 'GRBM_PERF_SEL_UTCL2_BUSY', + 'GRBM_PERF_SEL_VGT_BUSY', 'GRBM_PERF_SEL_WD_BUSY', + 'GRBM_PERF_SEL_WD_NO_DMA_BUSY', 'GRBM_SE0_PERF_SEL', + 'GRBM_SE0_PERF_SEL_BCI_BUSY', 'GRBM_SE0_PERF_SEL_CB_BUSY', + 'GRBM_SE0_PERF_SEL_CB_CLEAN', 'GRBM_SE0_PERF_SEL_COUNT', + 'GRBM_SE0_PERF_SEL_DB_BUSY', 'GRBM_SE0_PERF_SEL_DB_CLEAN', + 'GRBM_SE0_PERF_SEL_PA_BUSY', 'GRBM_SE0_PERF_SEL_RESERVED_0', + 'GRBM_SE0_PERF_SEL_RESERVED_1', 'GRBM_SE0_PERF_SEL_RMI_BUSY', + 'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY', + 'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY', + 'GRBM_SE0_PERF_SEL_USER_DEFINED', 'GRBM_SE0_PERF_SEL_VGT_BUSY', + 'GRBM_SE1_PERF_SEL', 'GRBM_SE1_PERF_SEL_BCI_BUSY', + 'GRBM_SE1_PERF_SEL_CB_BUSY', 'GRBM_SE1_PERF_SEL_CB_CLEAN', + 'GRBM_SE1_PERF_SEL_COUNT', 'GRBM_SE1_PERF_SEL_DB_BUSY', + 'GRBM_SE1_PERF_SEL_DB_CLEAN', 'GRBM_SE1_PERF_SEL_PA_BUSY', + 'GRBM_SE1_PERF_SEL_RESERVED_0', 'GRBM_SE1_PERF_SEL_RESERVED_1', + 'GRBM_SE1_PERF_SEL_RMI_BUSY', 'GRBM_SE1_PERF_SEL_SC_BUSY', + 'GRBM_SE1_PERF_SEL_SPI_BUSY', 'GRBM_SE1_PERF_SEL_SX_BUSY', + 'GRBM_SE1_PERF_SEL_TA_BUSY', 'GRBM_SE1_PERF_SEL_USER_DEFINED', + 'GRBM_SE1_PERF_SEL_VGT_BUSY', 'GRBM_SE2_PERF_SEL', + 'GRBM_SE2_PERF_SEL_BCI_BUSY', 'GRBM_SE2_PERF_SEL_CB_BUSY', + 'GRBM_SE2_PERF_SEL_CB_CLEAN', 'GRBM_SE2_PERF_SEL_COUNT', + 'GRBM_SE2_PERF_SEL_DB_BUSY', 'GRBM_SE2_PERF_SEL_DB_CLEAN', + 'GRBM_SE2_PERF_SEL_PA_BUSY', 'GRBM_SE2_PERF_SEL_RESERVED_0', + 'GRBM_SE2_PERF_SEL_RESERVED_1', 'GRBM_SE2_PERF_SEL_RMI_BUSY', + 'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY', + 'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY', + 'GRBM_SE2_PERF_SEL_USER_DEFINED', 'GRBM_SE2_PERF_SEL_VGT_BUSY', + 'GRBM_SE3_PERF_SEL', 'GRBM_SE3_PERF_SEL_BCI_BUSY', + 'GRBM_SE3_PERF_SEL_CB_BUSY', 'GRBM_SE3_PERF_SEL_CB_CLEAN', + 'GRBM_SE3_PERF_SEL_COUNT', 'GRBM_SE3_PERF_SEL_DB_BUSY', + 'GRBM_SE3_PERF_SEL_DB_CLEAN', 'GRBM_SE3_PERF_SEL_PA_BUSY', + 'GRBM_SE3_PERF_SEL_RESERVED_0', 'GRBM_SE3_PERF_SEL_RESERVED_1', + 'GRBM_SE3_PERF_SEL_RMI_BUSY', 'GRBM_SE3_PERF_SEL_SC_BUSY', + 'GRBM_SE3_PERF_SEL_SPI_BUSY', 'GRBM_SE3_PERF_SEL_SX_BUSY', + 'GRBM_SE3_PERF_SEL_TA_BUSY', 'GRBM_SE3_PERF_SEL_USER_DEFINED', + 'GRBM_SE3_PERF_SEL_VGT_BUSY', 'GSTHREADID_SIZE', 'GS_CUT_1024', + 'GS_CUT_128', 'GS_CUT_256', 'GS_CUT_512', 'GS_OFF', + 'GS_SCENARIO_A', 'GS_SCENARIO_B', 'GS_SCENARIO_C', + 'GS_SCENARIO_G', 'GS_STAGE_OFF', 'GS_STAGE_ON', 'GroupInterleave', + 'HDMI_ACR_0_MULTIPLE_RESERVED', 'HDMI_ACR_1_MULTIPLE', + 'HDMI_ACR_2_MULTIPLE', 'HDMI_ACR_3_MULTIPLE_RESERVED', + 'HDMI_ACR_4_MULTIPLE', 'HDMI_ACR_5_MULTIPLE_RESERVED', + 'HDMI_ACR_6_MULTIPLE_RESERVED', 'HDMI_ACR_7_MULTIPLE_RESERVED', + 'HDMI_ACR_AUDIO_PRIORITY', 'HDMI_ACR_CONT', + 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', + 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', + 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', + 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', + 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', + 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', + 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', + 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', + 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', + 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', + 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', + 'HDMI_AUDIO_INFO_SEND', + 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', + 'HDMI_AUDIO_SEND_MAX_PACKETS', 'HDMI_AVI_INFO_CONT', + 'HDMI_AVI_INFO_CONT_DISABLE', 'HDMI_AVI_INFO_CONT_ENABLE', + 'HDMI_AVI_INFO_NOT_SEND', 'HDMI_AVI_INFO_PKT_SEND', + 'HDMI_AVI_INFO_SEND', + 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE', + 'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE', + 'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 'HDMI_DEEP_COLOR_DEPTH_RESERVED', 'HDMI_DEFAULT_PAHSE', + 'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1', + 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK', + 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', + 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', + 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_GC_AVMUTE', + 'HDMI_GC_AVMUTE_CONT', 'HDMI_GC_AVMUTE_CONT_DISABLE', + 'HDMI_GC_AVMUTE_CONT_ENABLE', 'HDMI_GC_AVMUTE_SET', + 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', 'HDMI_GC_CONT_DISABLE', + 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', 'HDMI_GC_PKT_SEND', + 'HDMI_GC_SEND', 'HDMI_GENERIC0_CONT', + 'HDMI_GENERIC0_CONT_DISABLE', 'HDMI_GENERIC0_CONT_ENABLE', + 'HDMI_GENERIC0_NOT_SEND', 'HDMI_GENERIC0_PKT_SEND', + 'HDMI_GENERIC0_SEND', 'HDMI_GENERIC1_CONT', + 'HDMI_GENERIC1_CONT_DISABLE', 'HDMI_GENERIC1_CONT_ENABLE', + 'HDMI_GENERIC1_NOT_SEND', 'HDMI_GENERIC1_PKT_SEND', + 'HDMI_GENERIC1_SEND', 'HDMI_GENERIC2_CONT', + 'HDMI_GENERIC2_CONT_DISABLE', 'HDMI_GENERIC2_CONT_ENABLE', + 'HDMI_GENERIC2_NOT_SEND', 'HDMI_GENERIC2_PKT_SEND', + 'HDMI_GENERIC2_SEND', 'HDMI_GENERIC3_CONT', + 'HDMI_GENERIC3_CONT_DISABLE', 'HDMI_GENERIC3_CONT_ENABLE', + 'HDMI_GENERIC3_NOT_SEND', 'HDMI_GENERIC3_PKT_SEND', + 'HDMI_GENERIC3_SEND', 'HDMI_ISRC_CONT', 'HDMI_ISRC_CONT_DISABLE', + 'HDMI_ISRC_CONT_ENABLE', 'HDMI_ISRC_NOT_SEND', + 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', + 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', + 'HDMI_MPEG_INFO_CONT', 'HDMI_MPEG_INFO_CONT_DISABLE', + 'HDMI_MPEG_INFO_CONT_ENABLE', 'HDMI_MPEG_INFO_NOT_SEND', + 'HDMI_MPEG_INFO_PKT_SEND', 'HDMI_MPEG_INFO_SEND', + 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', + 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', + 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', + 'HDMI_PACKING_PHASE_OVERRIDE', 'HDMI_PACKING_PHASE_SET_BY_HW', + 'HDMI_PACKING_PHASE_SET_BY_SW', 'HDMI_SEND_MAX_AUDIO_PACKETS', + 'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0', + 'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON', + 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', + 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', + 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HS_STAGE_OFF', 'HS_STAGE_ON', + 'HW_SOURCE_SEL_DSC_JPEG', 'HW_SOURCE_SEL_DSC_VLP', + 'HW_SOURCE_SEL_DSC_VUP', 'HW_SOURCE_SEL_NONE', + 'I2S0_SPDIF0_SOFT_RESET', 'I2S0_SPDIF0_SOFT_RESET_0', + 'I2S0_SPDIF0_SOFT_RESET_1', 'I2S1_SOFT_RESET', + 'I2S1_SOFT_RESET_0', 'I2S1_SOFT_RESET_1', 'I2S_LRCLK_HIGH_LEFT', + 'I2S_LRCLK_LOW_LEFT', 'I2S_LRCLK_POLARITY', + 'I2S_SAMPLE_ALIGNMENT', 'I2S_SAMPLE_BIT_ORDER', + 'I2S_SAMPLE_BIT_ORDER_LSB', 'I2S_SAMPLE_BIT_ORDER_MSB', + 'I2S_SAMPLE_LEFT_ALIGNED', 'I2S_SAMPLE_RIGHT_ALIGNED', + 'I2S_WORD_ALIGNMENT', 'I2S_WORD_ALTERNATE_ALIGNMENT', + 'I2S_WORD_I2S_ALIGNMENT', 'I2S_WORD_SIZE', 'I2S_WORD_SIZE_16', + 'I2S_WORD_SIZE_32', 'IA_PERFCOUNT_SELECT', + 'ID_STREAM_DISABLE_ACKED', 'ID_STREAM_DISABLE_NO_ACK', + 'IH_PERF_SEL', 'IH_PERF_SEL_BIF_LINE0_FALLING', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', + 'IH_PERF_SEL_BIF_LINE0_RISING', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', 'IH_PERF_SEL_BUFFER_IDLE', + 'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT', + 'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT', + 'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT', + 'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT', + 'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT', + 'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT', + 'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT', + 'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT', + 'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT', + 'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT', + 'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT', + 'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT', + 'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT', + 'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT', + 'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT', + 'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT', + 'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE', + 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', + 'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT', + 'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL', + 'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_VF0', + 'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10', + 'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12', + 'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14', + 'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF2', + 'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF4', + 'IH_PERF_SEL_RB0_FULL_VF5', 'IH_PERF_SEL_RB0_FULL_VF6', + 'IH_PERF_SEL_RB0_FULL_VF7', 'IH_PERF_SEL_RB0_FULL_VF8', + 'IH_PERF_SEL_RB0_FULL_VF9', 'IH_PERF_SEL_RB0_OVERFLOW', + 'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1', + 'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11', + 'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13', + 'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15', + 'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF3', + 'IH_PERF_SEL_RB0_OVERFLOW_VF4', 'IH_PERF_SEL_RB0_OVERFLOW_VF5', + 'IH_PERF_SEL_RB0_OVERFLOW_VF6', 'IH_PERF_SEL_RB0_OVERFLOW_VF7', + 'IH_PERF_SEL_RB0_OVERFLOW_VF8', 'IH_PERF_SEL_RB0_OVERFLOW_VF9', + 'IH_PERF_SEL_RB0_RPTR_WRAP', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL', + 'IH_PERF_SEL_RB1_FULL_VF0', 'IH_PERF_SEL_RB1_FULL_VF1', + 'IH_PERF_SEL_RB1_FULL_VF10', 'IH_PERF_SEL_RB1_FULL_VF11', + 'IH_PERF_SEL_RB1_FULL_VF12', 'IH_PERF_SEL_RB1_FULL_VF13', + 'IH_PERF_SEL_RB1_FULL_VF14', 'IH_PERF_SEL_RB1_FULL_VF15', + 'IH_PERF_SEL_RB1_FULL_VF2', 'IH_PERF_SEL_RB1_FULL_VF3', + 'IH_PERF_SEL_RB1_FULL_VF4', 'IH_PERF_SEL_RB1_FULL_VF5', + 'IH_PERF_SEL_RB1_FULL_VF6', 'IH_PERF_SEL_RB1_FULL_VF7', + 'IH_PERF_SEL_RB1_FULL_VF8', 'IH_PERF_SEL_RB1_FULL_VF9', + 'IH_PERF_SEL_RB1_OVERFLOW', 'IH_PERF_SEL_RB1_OVERFLOW_VF0', + 'IH_PERF_SEL_RB1_OVERFLOW_VF1', 'IH_PERF_SEL_RB1_OVERFLOW_VF10', + 'IH_PERF_SEL_RB1_OVERFLOW_VF11', 'IH_PERF_SEL_RB1_OVERFLOW_VF12', + 'IH_PERF_SEL_RB1_OVERFLOW_VF13', 'IH_PERF_SEL_RB1_OVERFLOW_VF14', + 'IH_PERF_SEL_RB1_OVERFLOW_VF15', 'IH_PERF_SEL_RB1_OVERFLOW_VF2', + 'IH_PERF_SEL_RB1_OVERFLOW_VF3', 'IH_PERF_SEL_RB1_OVERFLOW_VF4', + 'IH_PERF_SEL_RB1_OVERFLOW_VF5', 'IH_PERF_SEL_RB1_OVERFLOW_VF6', + 'IH_PERF_SEL_RB1_OVERFLOW_VF7', 'IH_PERF_SEL_RB1_OVERFLOW_VF8', + 'IH_PERF_SEL_RB1_OVERFLOW_VF9', 'IH_PERF_SEL_RB1_RPTR_WRAP', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL', + 'IH_PERF_SEL_RB2_FULL_VF0', 'IH_PERF_SEL_RB2_FULL_VF1', + 'IH_PERF_SEL_RB2_FULL_VF10', 'IH_PERF_SEL_RB2_FULL_VF11', + 'IH_PERF_SEL_RB2_FULL_VF12', 'IH_PERF_SEL_RB2_FULL_VF13', + 'IH_PERF_SEL_RB2_FULL_VF14', 'IH_PERF_SEL_RB2_FULL_VF15', + 'IH_PERF_SEL_RB2_FULL_VF2', 'IH_PERF_SEL_RB2_FULL_VF3', + 'IH_PERF_SEL_RB2_FULL_VF4', 'IH_PERF_SEL_RB2_FULL_VF5', + 'IH_PERF_SEL_RB2_FULL_VF6', 'IH_PERF_SEL_RB2_FULL_VF7', + 'IH_PERF_SEL_RB2_FULL_VF8', 'IH_PERF_SEL_RB2_FULL_VF9', + 'IH_PERF_SEL_RB2_OVERFLOW', 'IH_PERF_SEL_RB2_OVERFLOW_VF0', + 'IH_PERF_SEL_RB2_OVERFLOW_VF1', 'IH_PERF_SEL_RB2_OVERFLOW_VF10', + 'IH_PERF_SEL_RB2_OVERFLOW_VF11', 'IH_PERF_SEL_RB2_OVERFLOW_VF12', + 'IH_PERF_SEL_RB2_OVERFLOW_VF13', 'IH_PERF_SEL_RB2_OVERFLOW_VF14', + 'IH_PERF_SEL_RB2_OVERFLOW_VF15', 'IH_PERF_SEL_RB2_OVERFLOW_VF2', + 'IH_PERF_SEL_RB2_OVERFLOW_VF3', 'IH_PERF_SEL_RB2_OVERFLOW_VF4', + 'IH_PERF_SEL_RB2_OVERFLOW_VF5', 'IH_PERF_SEL_RB2_OVERFLOW_VF6', + 'IH_PERF_SEL_RB2_OVERFLOW_VF7', 'IH_PERF_SEL_RB2_OVERFLOW_VF8', + 'IH_PERF_SEL_RB2_OVERFLOW_VF9', 'IH_PERF_SEL_RB2_RPTR_WRAP', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IMG_DATA_FORMAT', + 'IMG_DATA_FORMAT_10_10_10_2', 'IMG_DATA_FORMAT_10_11_11', + 'IMG_DATA_FORMAT_11_11_10', 'IMG_DATA_FORMAT_16', + 'IMG_DATA_FORMAT_16_16', 'IMG_DATA_FORMAT_16_16_16_16', + 'IMG_DATA_FORMAT_16_AS_16_16_16_16', + 'IMG_DATA_FORMAT_16_AS_32_32', + 'IMG_DATA_FORMAT_16_AS_32_32_32_32', 'IMG_DATA_FORMAT_1_5_5_5', + 'IMG_DATA_FORMAT_24_8', 'IMG_DATA_FORMAT_2_10_10_10', + 'IMG_DATA_FORMAT_32', 'IMG_DATA_FORMAT_32_32', + 'IMG_DATA_FORMAT_32_32_32', 'IMG_DATA_FORMAT_32_32_32_32', + 'IMG_DATA_FORMAT_32_AS_32_32_32_32', 'IMG_DATA_FORMAT_4_4', + 'IMG_DATA_FORMAT_4_4_4_4', 'IMG_DATA_FORMAT_5_5_5_1', + 'IMG_DATA_FORMAT_5_6_5', 'IMG_DATA_FORMAT_5_9_9_9', + 'IMG_DATA_FORMAT_6E4', 'IMG_DATA_FORMAT_6_5_5', + 'IMG_DATA_FORMAT_8', 'IMG_DATA_FORMAT_8_24', + 'IMG_DATA_FORMAT_8_8', 'IMG_DATA_FORMAT_8_8_8_8', + 'IMG_DATA_FORMAT_8_AS_32', 'IMG_DATA_FORMAT_8_AS_32_32', + 'IMG_DATA_FORMAT_8_AS_8_8_8_8', 'IMG_DATA_FORMAT_ASTC_2D_HDR', + 'IMG_DATA_FORMAT_ASTC_2D_LDR', 'IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB', + 'IMG_DATA_FORMAT_ASTC_3D_HDR', 'IMG_DATA_FORMAT_ASTC_3D_LDR', + 'IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB', 'IMG_DATA_FORMAT_BC1', + 'IMG_DATA_FORMAT_BC2', 'IMG_DATA_FORMAT_BC3', + 'IMG_DATA_FORMAT_BC4', 'IMG_DATA_FORMAT_BC5', + 'IMG_DATA_FORMAT_BC6', 'IMG_DATA_FORMAT_BC7', + 'IMG_DATA_FORMAT_BG_RG', 'IMG_DATA_FORMAT_ETC2_R', + 'IMG_DATA_FORMAT_ETC2_RG', 'IMG_DATA_FORMAT_ETC2_RGB', + 'IMG_DATA_FORMAT_ETC2_RGBA', 'IMG_DATA_FORMAT_ETC2_RGBA1', + 'IMG_DATA_FORMAT_FMASK', 'IMG_DATA_FORMAT_GB_GR', + 'IMG_DATA_FORMAT_INVALID', 'IMG_DATA_FORMAT_N_IN_16', + 'IMG_DATA_FORMAT_N_IN_16_16', 'IMG_DATA_FORMAT_N_IN_16_16_16_16', + 'IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16', + 'IMG_DATA_FORMAT_RESERVED_15', 'IMG_DATA_FORMAT_RESERVED_29', + 'IMG_DATA_FORMAT_RESERVED_30', 'IMG_DATA_FORMAT_RESERVED_56', + 'IMG_DATA_FORMAT_RESERVED_59', 'IMG_DATA_FORMAT_RESERVED_60', + 'IMG_DATA_FORMAT_X24_8_32', 'IMG_NUM_FORMAT', + 'IMG_NUM_FORMAT_ASTC_2D', 'IMG_NUM_FORMAT_ASTC_2D_10x10', + 'IMG_NUM_FORMAT_ASTC_2D_10x5', 'IMG_NUM_FORMAT_ASTC_2D_10x6', + 'IMG_NUM_FORMAT_ASTC_2D_10x8', 'IMG_NUM_FORMAT_ASTC_2D_12x10', + 'IMG_NUM_FORMAT_ASTC_2D_12x12', 'IMG_NUM_FORMAT_ASTC_2D_4x4', + 'IMG_NUM_FORMAT_ASTC_2D_5x4', 'IMG_NUM_FORMAT_ASTC_2D_5x5', + 'IMG_NUM_FORMAT_ASTC_2D_6x5', 'IMG_NUM_FORMAT_ASTC_2D_6x6', + 'IMG_NUM_FORMAT_ASTC_2D_8x5', 'IMG_NUM_FORMAT_ASTC_2D_8x6', + 'IMG_NUM_FORMAT_ASTC_2D_8x8', + 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_14', + 'IMG_NUM_FORMAT_ASTC_2D_RESERVED_15', 'IMG_NUM_FORMAT_ASTC_3D', + 'IMG_NUM_FORMAT_ASTC_3D_3x3x3', 'IMG_NUM_FORMAT_ASTC_3D_4x3x3', + 'IMG_NUM_FORMAT_ASTC_3D_4x4x3', 'IMG_NUM_FORMAT_ASTC_3D_4x4x4', + 'IMG_NUM_FORMAT_ASTC_3D_5x4x4', 'IMG_NUM_FORMAT_ASTC_3D_5x5x4', + 'IMG_NUM_FORMAT_ASTC_3D_5x5x5', 'IMG_NUM_FORMAT_ASTC_3D_6x5x5', + 'IMG_NUM_FORMAT_ASTC_3D_6x6x5', 'IMG_NUM_FORMAT_ASTC_3D_6x6x6', + 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_10', + 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_11', + 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_12', + 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_13', + 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_14', + 'IMG_NUM_FORMAT_ASTC_3D_RESERVED_15', 'IMG_NUM_FORMAT_FLOAT', + 'IMG_NUM_FORMAT_FMASK', 'IMG_NUM_FORMAT_FMASK_16_16_1', + 'IMG_NUM_FORMAT_FMASK_16_8_2', 'IMG_NUM_FORMAT_FMASK_32_16_2', + 'IMG_NUM_FORMAT_FMASK_32_8_4', 'IMG_NUM_FORMAT_FMASK_32_8_8', + 'IMG_NUM_FORMAT_FMASK_64_16_4', 'IMG_NUM_FORMAT_FMASK_64_16_8', + 'IMG_NUM_FORMAT_FMASK_8_2_1', 'IMG_NUM_FORMAT_FMASK_8_2_2', + 'IMG_NUM_FORMAT_FMASK_8_4_1', 'IMG_NUM_FORMAT_FMASK_8_4_2', + 'IMG_NUM_FORMAT_FMASK_8_4_4', 'IMG_NUM_FORMAT_FMASK_8_8_1', + 'IMG_NUM_FORMAT_FMASK_RESERVED_13', + 'IMG_NUM_FORMAT_FMASK_RESERVED_14', + 'IMG_NUM_FORMAT_FMASK_RESERVED_15', 'IMG_NUM_FORMAT_N_IN_16', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_0', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_10', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_11', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_12', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_13', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_14', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_15', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_3', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_6', + 'IMG_NUM_FORMAT_N_IN_16_RESERVED_9', + 'IMG_NUM_FORMAT_N_IN_16_UINT_10', 'IMG_NUM_FORMAT_N_IN_16_UINT_9', + 'IMG_NUM_FORMAT_N_IN_16_UNORM_10', + 'IMG_NUM_FORMAT_N_IN_16_UNORM_9', + 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10', + 'IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9', + 'IMG_NUM_FORMAT_RESERVED_10', 'IMG_NUM_FORMAT_RESERVED_11', + 'IMG_NUM_FORMAT_RESERVED_12', 'IMG_NUM_FORMAT_RESERVED_13', + 'IMG_NUM_FORMAT_RESERVED_14', 'IMG_NUM_FORMAT_RESERVED_15', + 'IMG_NUM_FORMAT_RESERVED_8', 'IMG_NUM_FORMAT_SINT', + 'IMG_NUM_FORMAT_SNORM', 'IMG_NUM_FORMAT_SRGB', + 'IMG_NUM_FORMAT_SSCALED', 'IMG_NUM_FORMAT_UINT', + 'IMG_NUM_FORMAT_UNORM', 'IMG_NUM_FORMAT_UNORM_UINT', + 'IMG_NUM_FORMAT_USCALED', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 'INGAMMA_MODE_BYPASS', 'INGAMMA_MODE_FIX', 'INGAMMA_MODE_FLOAT', + 'INPUTCSC_MODE_A', 'INPUTCSC_MODE_B', 'INPUTCSC_MODE_BYPASS', + 'INPUTCSC_MODE_UNITY', 'INPUTCSC_ROUND', 'INPUTCSC_TRUNCATE', + 'INPUTCSC_TYPE_10_2', 'INPUTCSC_TYPE_12_0', 'INPUTCSC_TYPE_8_4', + 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', 'INPUT_INNER_COVERAGE', + 'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG', + 'INST_ID_HW_TRAP', 'INST_ID_KILL_SEQ', 'INST_ID_PRIV_START', + 'INST_ID_SPI_WREXEC', 'INST_ID_TTRACE_NEW_PC_MSG', + 'INTERLACE_SOURCE_INTERLEAVE', 'INTERLACE_SOURCE_PROGRESSIVE', + 'INTERLACE_SOURCE_STACK', 'INTERLEAVE_DIS', 'INTERLEAVE_EN', + 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', + 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', + 'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'JITTER_REMOVE_DISABLE', + 'LATE_Z', 'LBV_DITHER_EN', 'LBV_DOWNSCALE_PREFETCH_EN', + 'LBV_DYNAMIC_PIXEL_DEPTH', 'LBV_INTERLEAVE_EN', + 'LBV_MEMORY_CONFIG', 'LBV_PIXEL_DEPTH', 'LBV_PIXEL_EXPAN_MODE', + 'LBV_PIXEL_REDUCE_MODE', 'LBV_SYNC_DURATION', + 'LBV_SYNC_RESET_SEL2', 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK', + 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL', + 'LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET', + 'LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK', + 'LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL', + 'LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET', + 'LB_DATA_FORMAT_ALPHA_DISABLE', 'LB_DATA_FORMAT_ALPHA_EN', + 'LB_DATA_FORMAT_ALPHA_ENABLE', + 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH', + 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP', + 'LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP', + 'LB_DATA_FORMAT_INTERLEAVE_DISABLE', + 'LB_DATA_FORMAT_INTERLEAVE_EN', + 'LB_DATA_FORMAT_INTERLEAVE_ENABLE', 'LB_DATA_FORMAT_PIXEL_DEPTH', + 'LB_DATA_FORMAT_PIXEL_DEPTH_18BPP', + 'LB_DATA_FORMAT_PIXEL_DEPTH_24BPP', + 'LB_DATA_FORMAT_PIXEL_DEPTH_30BPP', + 'LB_DATA_FORMAT_PIXEL_DEPTH_36BPP', + 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE', + 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION', + 'LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION', + 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE', + 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING', + 'LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION', + 'LB_DATA_FORMAT_REQUEST_MODE', + 'LB_DATA_FORMAT_REQUEST_MODE_NORMAL', + 'LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0', + 'LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1', + 'LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE', + 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE', + 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE', + 'LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK', + 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE', + 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE', + 'LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK', + 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE', + 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE', + 'LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK', + 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE', + 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN', + 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE', + 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE', + 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE', + 'LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN', + 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL', + 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET', + 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK', + 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0', + 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1', + 'LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE', + 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE', + 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP', + 'LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE', + 'LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT', + 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION', + 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS', + 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS', + 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS', + 'LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK', + 'LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET', + 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN', + 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0', + 'LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1', + 'LB_VBLANK_STATUS_VBLANK_ACK', 'LB_VBLANK_STATUS_VBLANK_CLEAR', + 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE', + 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED', + 'LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED', + 'LB_VBLANK_STATUS_VBLANK_NORMAL', + 'LB_VLINE2_START_END_VLINE2_INV', + 'LB_VLINE2_START_END_VLINE2_INVERSE', + 'LB_VLINE2_START_END_VLINE2_NORMAL', + 'LB_VLINE2_STATUS_VLINE2_ACK', 'LB_VLINE2_STATUS_VLINE2_CLEAR', + 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE', + 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED', + 'LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED', + 'LB_VLINE2_STATUS_VLINE2_NORMAL', 'LB_VLINE_START_END_VLINE_INV', + 'LB_VLINE_START_END_VLINE_INVERSE', + 'LB_VLINE_START_END_VLINE_NORMAL', 'LB_VLINE_STATUS_VLINE_ACK', + 'LB_VLINE_STATUS_VLINE_CLEAR', + 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE', + 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED', + 'LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED', + 'LB_VLINE_STATUS_VLINE_NORMAL', 'LINESTRIP', + 'LPT_NUM_BANKS_16BANK', 'LPT_NUM_BANKS_2BANK', + 'LPT_NUM_BANKS_32BANK', 'LPT_NUM_BANKS_4BANK', + 'LPT_NUM_BANKS_8BANK', 'LPT_NUM_PIPES_1CH', 'LPT_NUM_PIPES_2CH', + 'LPT_NUM_PIPES_4CH', 'LPT_NUM_PIPES_8CH', 'LS_STAGE_OFF', + 'LS_STAGE_ON', 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', + 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', 'LptNumBanks', 'LptNumPipes', + 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK', + 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE', + 'MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', + 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK', + 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE', + 'MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA', 'MEMORY_CONFIG_0', + 'MEMORY_CONFIG_1', 'MEMORY_CONFIG_2', 'MEMORY_CONFIG_3', + 'MEM_ARB_MODE_AGE', 'MEM_ARB_MODE_BOTH', 'MEM_ARB_MODE_FIXED', + 'MEM_ARB_MODE_WEIGHT', 'MEM_PWR_DIS_CTRL', 'MEM_PWR_FORCE_CTRL', + 'MEM_PWR_FORCE_CTRL2', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2', + 'ME_ID0', 'ME_ID1', 'ME_ID2', 'ME_ID3', + 'MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', + 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', + 'MICRO_TILE_MODE_DISPLAY_2D', 'MICRO_TILE_MODE_DISPLAY_3D', + 'MICRO_TILE_MODE_LINEAR', 'MICRO_TILE_MODE_ROTATED', + 'MICRO_TILE_MODE_STD_2D', 'MICRO_TILE_MODE_STD_3D', + 'MICRO_TILE_MODE_Z_2D', 'MICRO_TILE_MODE_Z_3D', + 'MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK', + 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', + 'MSA_MISC0_OVERRIDE_DISABLE', 'MSA_MISC0_OVERRIDE_ENABLE', + 'MSA_MISC1_BIT7_OVERRIDE_DISABLE', + 'MSA_MISC1_BIT7_OVERRIDE_ENABLE', + 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', + 'MTYPE', 'MTYPE_CC', 'MTYPE_NC', 'MTYPE_RW', 'MTYPE_UC', + 'MTYPE_WC', 'MULT_16', 'MULT_8', 'MVP_CLK_SRC_SEL', + 'MVP_CLK_SRC_SEL_IO_1', 'MVP_CLK_SRC_SEL_IO_2', + 'MVP_CLK_SRC_SEL_REFCLK', 'MVP_CLK_SRC_SEL_RSRV', + 'MVP_SOFT_RESET', 'MVP_SOFT_RESET_0', 'MVP_SOFT_RESET_1', + 'MacroTileAspect', 'MemArbMode', 'MicroTileMode', + 'MultiGPUTileSize', 'NOT_SENT', 'NO_DIST', 'NO_FORCE', + 'NO_FORCE_REQ', 'NO_FORCE_REQUEST', 'NUMBER_FLOAT', 'NUMBER_SINT', + 'NUMBER_SNORM', 'NUMBER_SRGB', 'NUMBER_SSCALED', 'NUMBER_UINT', + 'NUMBER_UNORM', 'NUMBER_USCALED', 'NUM_SIMD_PER_CU', + 'NonDispTilingOrder', 'NumBanks', 'NumBanksConfig', 'NumGPUs', + 'NumLowerPipes', 'NumMaxCompressedFragments', 'NumPipes', + 'NumRbPerShaderEngine', 'NumShaderEngines', 'OFFCHIP_HS_DEALLOC', + 'OFF_SEQ', 'ON_SEQ', 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', + 'OPT_COMB_MAX', 'OPT_COMB_MIN', 'OPT_COMB_NONE', + 'OPT_COMB_REVSUBTRACT', 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', + 'OUTPUT_LINE', 'OUTPUT_POINT', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', + 'OVERRIDE_CGTT_DCEFCLK', 'OVERRIDE_CGTT_DCEFCLK_NOOP', + 'OVERRIDE_CGTT_SCLK', 'OVERRIDE_CGTT_SCLK_NOOP', 'PART_FRAC_EVEN', + 'PART_FRAC_ODD', 'PART_INTEGER', 'PART_POW2', 'PATCHES', + 'PERFCOUNTER_ACTIVE', 'PERFCOUNTER_CNT0_STATE', + 'PERFCOUNTER_CNT0_STATE_FREEZE', 'PERFCOUNTER_CNT0_STATE_HW', + 'PERFCOUNTER_CNT0_STATE_RESET', 'PERFCOUNTER_CNT0_STATE_START', + 'PERFCOUNTER_CNT1_STATE', 'PERFCOUNTER_CNT1_STATE_FREEZE', + 'PERFCOUNTER_CNT1_STATE_HW', 'PERFCOUNTER_CNT1_STATE_RESET', + 'PERFCOUNTER_CNT1_STATE_START', 'PERFCOUNTER_CNT2_STATE', + 'PERFCOUNTER_CNT2_STATE_FREEZE', 'PERFCOUNTER_CNT2_STATE_HW', + 'PERFCOUNTER_CNT2_STATE_RESET', 'PERFCOUNTER_CNT2_STATE_START', + 'PERFCOUNTER_CNT3_STATE', 'PERFCOUNTER_CNT3_STATE_FREEZE', + 'PERFCOUNTER_CNT3_STATE_HW', 'PERFCOUNTER_CNT3_STATE_RESET', + 'PERFCOUNTER_CNT3_STATE_START', 'PERFCOUNTER_CNT4_STATE', + 'PERFCOUNTER_CNT4_STATE_FREEZE', 'PERFCOUNTER_CNT4_STATE_HW', + 'PERFCOUNTER_CNT4_STATE_RESET', 'PERFCOUNTER_CNT4_STATE_START', + 'PERFCOUNTER_CNT5_STATE', 'PERFCOUNTER_CNT5_STATE_FREEZE', + 'PERFCOUNTER_CNT5_STATE_HW', 'PERFCOUNTER_CNT5_STATE_RESET', + 'PERFCOUNTER_CNT5_STATE_START', 'PERFCOUNTER_CNT6_STATE', + 'PERFCOUNTER_CNT6_STATE_FREEZE', 'PERFCOUNTER_CNT6_STATE_HW', + 'PERFCOUNTER_CNT6_STATE_RESET', 'PERFCOUNTER_CNT6_STATE_START', + 'PERFCOUNTER_CNT7_STATE', 'PERFCOUNTER_CNT7_STATE_FREEZE', + 'PERFCOUNTER_CNT7_STATE_HW', 'PERFCOUNTER_CNT7_STATE_RESET', + 'PERFCOUNTER_CNT7_STATE_START', 'PERFCOUNTER_CNTL_SEL', + 'PERFCOUNTER_CNTL_SEL_0', 'PERFCOUNTER_CNTL_SEL_1', + 'PERFCOUNTER_CNTL_SEL_2', 'PERFCOUNTER_CNTL_SEL_3', + 'PERFCOUNTER_CNTL_SEL_4', 'PERFCOUNTER_CNTL_SEL_5', + 'PERFCOUNTER_CNTL_SEL_6', 'PERFCOUNTER_CNTL_SEL_7', + 'PERFCOUNTER_CNTOFF_START_DIS', + 'PERFCOUNTER_CNTOFF_START_DISABLE', + 'PERFCOUNTER_CNTOFF_START_ENABLE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', + 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', + 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', + 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', + 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', + 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', + 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_INC_MODE', + 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', + 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', + 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', + 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', + 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', + 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', + 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', + 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', + 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', + 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', + 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', + 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', + 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', + 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', + 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', + 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', + 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', + 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', + 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', + 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', + 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', + 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', + 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', + 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', + 'PERFMON_COUNTER_MODE_ACCUM', + 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 'PERFMON_COUNTER_MODE_DIRTY', + 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', + 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', + 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', + 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', + 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', + 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', + 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', + 'PERFMON_STATE_START', 'PERF_PAPC_CCGSM_BUSY', + 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', + 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', + 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', + 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', + 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', + 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', + 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', + 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', + 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', + 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE', + 'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR', + 'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE', + 'PERF_PAPC_PASX_REC_STALLED', + 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', + 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', + 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', + 'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', + 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ', + 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD', + 'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 'PERF_PAPC_PA_INPUT_END_OF_PACKET', + 'PERF_PAPC_PA_INPUT_EVENT_FLAG', + 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', + 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM', + 'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM', + 'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', + 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', + 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', + 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE01_STALLED_SC', + 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE0_STALLED_SC', + 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE1_STALLED_SC', + 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE2_STALLED_SC', + 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', + 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 'PERSISTENT_SPACE_END', 'PERSISTENT_SPACE_START', + 'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ID0', 'PIPE_ID1', + 'PIPE_ID2', 'PIPE_ID3', 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG', + 'PIPE_PIXEL_RATE_PLL_SOURCE', + 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', + 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', + 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIXEL_DEPTH_18BPP', + 'PIXEL_DEPTH_24BPP', 'PIXEL_DEPTH_30BPP', 'PIXEL_DEPTH_38BPP', + 'PIXEL_EXPAN_MODE_DYN_EXP', 'PIXEL_EXPAN_MODE_ZERO_EXP', + 'PIXEL_FORMAT_RGB_444', 'PIXEL_FORMAT_YCBCR_422', + 'PIXEL_FORMAT_YCBCR_444', 'PIXEL_FORMAT_Y_ONLY', + 'PIXEL_PIPE_OCCLUSION_COUNT_0', 'PIXEL_PIPE_OCCLUSION_COUNT_1', + 'PIXEL_PIPE_OCCLUSION_COUNT_2', 'PIXEL_PIPE_OCCLUSION_COUNT_3', + 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', + 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', + 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', + 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', + 'PIXEL_REDUCE_MODE_ROUNDING', 'PIXEL_REDUCE_MODE_TRUNCATION', + 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', + 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM_ASSERT_RESET', + 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', 'POINTLIST', + 'PRESCALE_MODE_BYPASS', 'PRESCALE_MODE_PROGRAM', + 'PRESCALE_MODE_UNITY', 'PROG_SEQ', 'PSLC_ASAP', 'PSLC_AUTO', + 'PSLC_COUNTDOWN', 'PSLC_ON_HANG_ONLY', 'PS_DONE', + 'PS_PARTIAL_FLUSH', 'PULSE_MODE_OPT_NO_HSA', + 'PULSE_MODE_OPT_SEND', 'PerfCounter_Vals', 'PipeConfig', + 'PipeInterleaveSize', 'PipeTiling', 'PixelPipeCounterId', + 'PixelPipeStride', 'PkrMap', 'PkrXsel', 'PkrXsel2', 'PkrYsel', + 'QuadExportFormat', 'QuadExportFormatOld', + 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', + 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', + 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', + 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', + 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', + 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', + 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', + 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', + 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', + 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', + 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', + 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', + 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', + 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', + 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', + 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', + 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', + 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', + 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', + 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', + 'RASTER_CONFIG_SE_PAIR_MAP_3', + 'RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_128_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_128_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', 'READ_256_BITS', + 'READ_512_BITS', 'READ_SEQ', 'RECTLIST', 'REFCLK_CLOCK_EN', + 'REFCLK_CLOCK_EN_ALLOW_SRC_SEL', 'REFCLK_CLOCK_EN_XTALIN_CLK', + 'REFCLK_SRC_SEL', 'REFCLK_SRC_SEL_CPL_REFCLK', + 'REFCLK_SRC_SEL_PCIE_REFCLK', 'REF_ALWAYS', 'REF_EQUAL', + 'REF_GEQUAL', 'REF_GREATER', 'REF_LEQUAL', 'REF_LESS', + 'REF_NEVER', 'REF_NOTEQUAL', 'RESERVED_ES', 'RESERVED_LS', + 'RESERVED_VS', 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RE_Z', + 'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC', + 'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z', + 'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_BUSY', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR', + 'RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB', + 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0', + 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1', + 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2', + 'RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3', + 'RMI_PERF_SEL_DYN_CLK_CMN_VLD', 'RMI_PERF_SEL_DYN_CLK_PERF_VLD', + 'RMI_PERF_SEL_DYN_CLK_RB_VLD', 'RMI_PERF_SEL_EVENT_SEND', + 'RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ', + 'RMI_PERF_SEL_LAT_FIFO_FULL', + 'RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ', + 'RMI_PERF_SEL_LAT_FIFO_NUM_USED', 'RMI_PERF_SEL_NONE', + 'RMI_PERF_SEL_PERF_WINDOW', 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTR', + 'RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB', + 'RMI_PERF_SEL_POP_DEMUX_RTS_RTR', + 'RMI_PERF_SEL_POP_DEMUX_RTS_RTRB', + 'RMI_PERF_SEL_POP_XNACK_RTSB_RTR', + 'RMI_PERF_SEL_POP_XNACK_RTSB_RTRB', + 'RMI_PERF_SEL_POP_XNACK_RTS_RTR', + 'RMI_PERF_SEL_POP_XNACK_RTS_RTRB', + 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR', + 'RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB', + 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR', + 'RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB', + 'RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT', + 'RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT', + 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT', + 'RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY', + 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR', + 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB', + 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR', + 'RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB', + 'RMI_PERF_SEL_PRT_FIFO_BUSY', 'RMI_PERF_SEL_PRT_FIFO_NUM_USED', + 'RMI_PERF_SEL_PRT_FIFO_REQ', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7', + 'RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_RDREQ_BUSY', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID0', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID1', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID2', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID3', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID4', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID5', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID6', + 'RMI_PERF_SEL_RB_RMI_RDREQ_CID7', + 'RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY', + 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_BUSY', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID0', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID1', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID2', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID3', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID4', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID5', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID6', + 'RMI_PERF_SEL_RB_RMI_WRREQ_CID7', + 'RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY', + 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR', + 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB', + 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR', + 'RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB', + 'RMI_PERF_SEL_REG_CLK_VLD', 'RMI_PERF_SEL_REORDER_FIFO_BUSY', + 'RMI_PERF_SEL_REORDER_FIFO_REQ', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9', + 'RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9', + 'RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2', + 'RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2', + 'RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2', + 'RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3', + 'RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID0', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID1', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID2', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID3', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID4', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID5', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID6', + 'RMI_PERF_SEL_RMI_TC_RDREQ_CID7', + 'RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID', + 'RMI_PERF_SEL_RMI_TC_REQ_BUSY', + 'RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID0', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID1', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID2', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID3', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID4', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID5', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID6', + 'RMI_PERF_SEL_RMI_TC_WRREQ_CID7', + 'RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID', + 'RMI_PERF_SEL_RMI_UTC_BUSY', 'RMI_PERF_SEL_RMI_UTC_REQ', + 'RMI_PERF_SEL_SKID_FIFO_BUSY', 'RMI_PERF_SEL_SKID_FIFO_DEPTH', + 'RMI_PERF_SEL_SKID_FIFO_IN_RTS', 'RMI_PERF_SEL_SKID_FIFO_IN_RTSB', + 'RMI_PERF_SEL_SKID_FIFO_OUT_RTS', + 'RMI_PERF_SEL_SKID_FIFO_OUT_RTSB', 'RMI_PERF_SEL_SKID_FIFO_REQ', + 'RMI_PERF_SEL_TCIW_BUSY', 'RMI_PERF_SEL_TCIW_INFLIGHT_COUNT', + 'RMI_PERF_SEL_TCIW_REQ', + 'RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID', + 'RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID', + 'RMI_PERF_SEL_UTCL1_BUSY', 'RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL', + 'RMI_PERF_SEL_UTCL1_LFIFO_FULL', + 'RMI_PERF_SEL_UTCL1_PERMISSION_MISS', + 'RMI_PERF_SEL_UTCL1_REQUEST', + 'RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 'RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 'RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 'RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 'RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS', + 'RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 'RMI_PERF_SEL_UTCL1_TRANSLATION_MISS', + 'RMI_PERF_SEL_UTCL1_UTCL2_REQ', 'RMI_PERF_SEL_UTC_POP_RTSB_RTR', + 'RMI_PERF_SEL_UTC_POP_RTSB_RTRB', 'RMI_PERF_SEL_UTC_POP_RTS_RTR', + 'RMI_PERF_SEL_UTC_POP_RTS_RTRB', + 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR', + 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB', + 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR', + 'RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB', + 'RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB', + 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR', + 'RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB', + 'RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR', + 'RMI_PERF_SEL_XNACK_FIFO_BUSY', 'RMI_PERF_SEL_XNACK_FIFO_FULL', + 'RMI_PERF_SEL_XNACK_FIFO_NUM_USED', + 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR', + 'RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB', + 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR', + 'RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB', 'ROM_SIGNATURE', + 'ROUND_BY_HALF', 'ROUND_TRUNCATE', 'RST_PIX_CNT', 'RSV_TAG_RAM', + 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', 'ReadSize', 'Reserved142', + 'Reserved143', 'Reserved144', 'Reserved145', 'Reserved146', + 'Reserved147', 'Reserved148', 'Reserved149', 'Reserved18', + 'Reserved182', 'Reserved183', 'Reserved184', 'Reserved185', + 'Reserved186', 'Reserved187', 'Reserved188', 'Reserved189', + 'Reserved190', 'Reserved191', 'Reserved192', 'Reserved193', + 'Reserved194', 'Reserved195', 'Reserved196', 'Reserved197', + 'Reserved198', 'Reserved199', 'Reserved200', 'Reserved201', + 'Reserved202', 'Reserved203', 'Reserved204', 'Reserved205', + 'Reserved206', 'Reserved207', 'Reserved208', 'Reserved209', + 'Reserved210', 'Reserved211', 'Reserved212', 'Reserved213', + 'Reserved214', 'Reserved215', 'Reserved216', 'Reserved217', + 'Reserved218', 'Reserved219', 'Reserved23', 'Reserved252', + 'Reserved253', 'Reserved254', 'Reserved255', 'Reserved256', + 'Reserved257', 'Reserved258', 'Reserved259', 'Reserved26', + 'Reserved260', 'Reserved261', 'Reserved262', 'Reserved263', + 'Reserved264', 'Reserved265', 'Reserved266', 'Reserved267', + 'Reserved27', 'Reserved28', 'Reserved29', 'Reserved300', + 'Reserved301', 'Reserved302', 'Reserved303', 'Reserved304', + 'Reserved305', 'Reserved306', 'Reserved307', 'Reserved308', + 'Reserved309', 'Reserved310', 'Reserved311', 'Reserved312', + 'Reserved313', 'Reserved314', 'Reserved315', 'Reserved316', + 'Reserved317', 'Reserved318', 'Reserved319', 'Reserved320', + 'Reserved321', 'Reserved322', 'Reserved323', 'Reserved324', + 'Reserved325', 'Reserved326', 'Reserved327', 'Reserved328', + 'Reserved329', 'Reserved330', 'Reserved331', 'Reserved364', + 'Reserved365', 'Reserved366', 'Reserved367', 'Reserved368', + 'Reserved369', 'Reserved370', 'Reserved371', 'Reserved372', + 'Reserved373', 'Reserved374', 'Reserved375', 'Reserved376', + 'Reserved377', 'Reserved378', 'Reserved379', 'Reserved412', + 'Reserved413', 'Reserved414', 'Reserved415', 'Reserved416', + 'Reserved417', 'Reserved418', 'Reserved419', 'Reserved420', + 'Reserved421', 'Reserved422', 'Reserved423', 'Reserved424', + 'Reserved425', 'Reserved426', 'Reserved427', 'Reserved428', + 'Reserved429', 'Reserved430', 'Reserved431', 'Reserved432', + 'Reserved433', 'Reserved434', 'Reserved435', 'Reserved436', + 'Reserved437', 'Reserved438', 'Reserved439', 'Reserved440', + 'Reserved441', 'Reserved442', 'Reserved443', 'Reserved444', + 'Reserved445', 'Reserved446', 'Reserved447', 'Reserved448', + 'Reserved449', 'Reserved450', 'Reserved451', 'Reserved452', + 'Reserved453', 'Reserved454', 'Reserved455', 'Reserved456', + 'Reserved457', 'Reserved458', 'Reserved459', 'Reserved460', + 'Reserved461', 'Reserved462', 'Reserved463', 'Reserved464', + 'Reserved465', 'Reserved466', 'Reserved467', 'Reserved468', + 'Reserved469', 'Reserved470', 'Reserved471', 'Reserved472', + 'Reserved473', 'Reserved474', 'Reserved475', 'Reserved476', + 'Reserved477', 'Reserved478', 'Reserved479', 'Reserved480', + 'Reserved481', 'Reserved482', 'Reserved483', 'Reserved484', + 'Reserved485', 'Reserved486', 'Reserved487', 'Reserved488', + 'Reserved489', 'Reserved490', 'Reserved491', 'Reserved492', + 'Reserved493', 'Reserved494', 'Reserved495', 'Reserved496', + 'Reserved497', 'Reserved498', 'Reserved499', 'Reserved500', + 'Reserved501', 'Reserved502', 'Reserved503', 'Reserved504', + 'Reserved505', 'Reserved506', 'Reserved507', 'Reserved508', + 'Reserved509', 'Reserved510', 'Reserved511', 'Reserved_0x00', + 'Reserved_0x09', 'Reserved_0x3f', 'RingCounterControl', + 'RoundMode', 'RowSize', 'RowTiling', 'SAMPLE_PIPELINESTAT', + 'SAMPLE_STREAMOUTSTATS', 'SAMPLE_STREAMOUTSTATS1', + 'SAMPLE_STREAMOUTSTATS2', 'SAMPLE_STREAMOUTSTATS3', + 'SCLV_COEF_UPDATE_COMPLETE', 'SCLV_INTERLACE_SOURCE', + 'SCLV_MODE_RGB_BYPASS', 'SCLV_MODE_RGB_SCALING', 'SCLV_MODE_SEL', + 'SCLV_MODE_YCBCR_BYPASS', 'SCLV_MODE_YCBCR_SCALING', + 'SCLV_UPDATE_LOCK', 'SCL_ALU_DISABLE', 'SCL_ALU_DISABLED', + 'SCL_ALU_ENABLED', 'SCL_BOUNDARY_MODE', 'SCL_BOUNDARY_MODE_BLACK', + 'SCL_BOUNDARY_MODE_EDGE', 'SCL_BYPASS_MODE', + 'SCL_BYPASS_MODE_AC_AR', 'SCL_BYPASS_MODE_AC_NR', + 'SCL_BYPASS_MODE_MC_MR', 'SCL_BYPASS_MODE_RESERVED', + 'SCL_COEF_UPDATE_COMPLETE', 'SCL_COEF_UPDATE_COMPLETED', + 'SCL_COEF_UPDATE_NOT_COMPLETED', 'SCL_C_RAM_FILTER_TYPE', + 'SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT', + 'SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT', + 'SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT', + 'SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT', 'SCL_C_RAM_PHASE', + 'SCL_C_RAM_PHASE_0', 'SCL_C_RAM_PHASE_1', 'SCL_C_RAM_PHASE_2', + 'SCL_C_RAM_PHASE_3', 'SCL_C_RAM_PHASE_4', 'SCL_C_RAM_PHASE_5', + 'SCL_C_RAM_PHASE_6', 'SCL_C_RAM_PHASE_7', 'SCL_C_RAM_PHASE_8', + 'SCL_C_RAM_TAP_PAIR_ID0', 'SCL_C_RAM_TAP_PAIR_ID1', + 'SCL_C_RAM_TAP_PAIR_ID2', 'SCL_C_RAM_TAP_PAIR_ID3', + 'SCL_C_RAM_TAP_PAIR_ID4', 'SCL_C_RAM_TAP_PAIR_IDX', + 'SCL_EARLY_EOL_MOD', 'SCL_EARLY_EOL_MODE_CRTC', + 'SCL_EARLY_EOL_MODE_INTERNAL', 'SCL_HF_SHARP_DISABLE', + 'SCL_HF_SHARP_EN', 'SCL_HF_SHARP_ENABLE', + 'SCL_HF_SHARP_SCALE_FACTOR', 'SCL_HF_SHARP_SCALE_FACTOR_0', + 'SCL_HF_SHARP_SCALE_FACTOR_1', 'SCL_HF_SHARP_SCALE_FACTOR_2', + 'SCL_HF_SHARP_SCALE_FACTOR_3', 'SCL_HF_SHARP_SCALE_FACTOR_4', + 'SCL_HF_SHARP_SCALE_FACTOR_5', 'SCL_HF_SHARP_SCALE_FACTOR_6', + 'SCL_HF_SHARP_SCALE_FACTOR_7', + 'SCL_HOST_CONFLICT_DISABLE_INTERRUPT', + 'SCL_HOST_CONFLICT_ENABLE_INTERRUPT', 'SCL_HOST_CONFLICT_MASK', + 'SCL_H_2TAP_HARDCODE_COEF_DISABLE', 'SCL_H_2TAP_HARDCODE_COEF_EN', + 'SCL_H_2TAP_HARDCODE_COEF_ENABLE', + 'SCL_H_CALC_AUTO_RATIO_DISABLE', 'SCL_H_CALC_AUTO_RATIO_EN', + 'SCL_H_CALC_AUTO_RATIO_ENABLE', 'SCL_H_FILTER_PICK_NEAREST', + 'SCL_H_FILTER_PICK_NEAREST_DISABLE', + 'SCL_H_FILTER_PICK_NEAREST_ENABLE', + 'SCL_H_MANUAL_REPLICATE_FACTOR', + 'SCL_H_MANUAL_REPLICATE_FACTOR_1', + 'SCL_H_MANUAL_REPLICATE_FACTOR_10', + 'SCL_H_MANUAL_REPLICATE_FACTOR_11', + 'SCL_H_MANUAL_REPLICATE_FACTOR_12', + 'SCL_H_MANUAL_REPLICATE_FACTOR_13', + 'SCL_H_MANUAL_REPLICATE_FACTOR_14', + 'SCL_H_MANUAL_REPLICATE_FACTOR_15', + 'SCL_H_MANUAL_REPLICATE_FACTOR_16', + 'SCL_H_MANUAL_REPLICATE_FACTOR_2', + 'SCL_H_MANUAL_REPLICATE_FACTOR_3', + 'SCL_H_MANUAL_REPLICATE_FACTOR_4', + 'SCL_H_MANUAL_REPLICATE_FACTOR_5', + 'SCL_H_MANUAL_REPLICATE_FACTOR_6', + 'SCL_H_MANUAL_REPLICATE_FACTOR_7', + 'SCL_H_MANUAL_REPLICATE_FACTOR_8', + 'SCL_H_MANUAL_REPLICATE_FACTOR_9', 'SCL_H_NUM_OF_TAPS', + 'SCL_H_NUM_OF_TAPS_1', 'SCL_H_NUM_OF_TAPS_10', + 'SCL_H_NUM_OF_TAPS_2', 'SCL_H_NUM_OF_TAPS_4', + 'SCL_H_NUM_OF_TAPS_6', 'SCL_H_NUM_OF_TAPS_8', + 'SCL_MODE_CHANGE_DISABLE_INTERRUPT', + 'SCL_MODE_CHANGE_ENABLE_INTERRUPT', 'SCL_MODE_RGB_BYPASS', + 'SCL_MODE_RGB_SCALING', 'SCL_MODE_SEL', 'SCL_MODE_YCBCR_BYPASS', + 'SCL_MODE_YCBCR_SCALING', 'SCL_PSCL_DISABLE', 'SCL_PSCL_EN', + 'SCL_PSCL_ENANBLE', 'SCL_SCL_MODE_CHANGE_MASK', 'SCL_UPDATE_LOCK', + 'SCL_UPDATE_LOCKED', 'SCL_UPDATE_TAKEN', 'SCL_UPDATE_TAKEN_NO', + 'SCL_UPDATE_TAKEN_YES', 'SCL_UPDATE_UNLOCKED', + 'SCL_VF_SHARP_DISABLE', 'SCL_VF_SHARP_EN', 'SCL_VF_SHARP_ENABLE', + 'SCL_VF_SHARP_SCALE_FACTOR', 'SCL_VF_SHARP_SCALE_FACTOR_0', + 'SCL_VF_SHARP_SCALE_FACTOR_1', 'SCL_VF_SHARP_SCALE_FACTOR_2', + 'SCL_VF_SHARP_SCALE_FACTOR_3', 'SCL_VF_SHARP_SCALE_FACTOR_4', + 'SCL_VF_SHARP_SCALE_FACTOR_5', 'SCL_VF_SHARP_SCALE_FACTOR_6', + 'SCL_VF_SHARP_SCALE_FACTOR_7', 'SCL_V_2TAP_HARDCODE_COEF_DISABLE', + 'SCL_V_2TAP_HARDCODE_COEF_EN', 'SCL_V_2TAP_HARDCODE_COEF_ENABLE', + 'SCL_V_CALC_AUTO_RATIO_DISABLE', 'SCL_V_CALC_AUTO_RATIO_EN', + 'SCL_V_CALC_AUTO_RATIO_ENABLE', 'SCL_V_FILTER_PICK_NEAREST', + 'SCL_V_FILTER_PICK_NEAREST_DISABLE', + 'SCL_V_FILTER_PICK_NEAREST_ENABLE', + 'SCL_V_MANUAL_REPLICATE_FACTOR', + 'SCL_V_MANUAL_REPLICATE_FACTOR_1', + 'SCL_V_MANUAL_REPLICATE_FACTOR_10', + 'SCL_V_MANUAL_REPLICATE_FACTOR_11', + 'SCL_V_MANUAL_REPLICATE_FACTOR_12', + 'SCL_V_MANUAL_REPLICATE_FACTOR_13', + 'SCL_V_MANUAL_REPLICATE_FACTOR_14', + 'SCL_V_MANUAL_REPLICATE_FACTOR_15', + 'SCL_V_MANUAL_REPLICATE_FACTOR_16', + 'SCL_V_MANUAL_REPLICATE_FACTOR_2', + 'SCL_V_MANUAL_REPLICATE_FACTOR_3', + 'SCL_V_MANUAL_REPLICATE_FACTOR_4', + 'SCL_V_MANUAL_REPLICATE_FACTOR_5', + 'SCL_V_MANUAL_REPLICATE_FACTOR_6', + 'SCL_V_MANUAL_REPLICATE_FACTOR_7', + 'SCL_V_MANUAL_REPLICATE_FACTOR_8', + 'SCL_V_MANUAL_REPLICATE_FACTOR_9', 'SCL_V_NUM_OF_TAPS', + 'SCL_V_NUM_OF_TAPS_1', 'SCL_V_NUM_OF_TAPS_2', + 'SCL_V_NUM_OF_TAPS_3', 'SCL_V_NUM_OF_TAPS_4', + 'SCL_V_NUM_OF_TAPS_5', 'SCL_V_NUM_OF_TAPS_6', 'SC_BACKEND_BUSY', + 'SC_BB_DISCARD', 'SC_BM_BUSY', 'SC_BUSY_CNT_NOT_ZERO', + 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', 'SC_EARLYZ_QUAD_COUNT', + 'SC_EARLYZ_QUAD_WITH_1_PIX', 'SC_EARLYZ_QUAD_WITH_2_PIX', + 'SC_EARLYZ_QUAD_WITH_3_PIX', 'SC_EARLYZ_QUAD_WITH_4_PIX', + 'SC_EOP_SYNC_WINDOW', 'SC_GRP0_DYN_SCLK_BUSY', + 'SC_GRP1_DYN_SCLK_BUSY', 'SC_GRP2_DYN_SCLK_BUSY', + 'SC_GRP3_DYN_SCLK_BUSY', 'SC_GRP4_DYN_SCLK_BUSY', + 'SC_MULTICYCLE_BUBBLE_FREEZE', 'SC_P0_DETAIL_QUAD_COUNT', + 'SC_P0_DETAIL_QUAD_WITH_1_PIX', 'SC_P0_DETAIL_QUAD_WITH_2_PIX', + 'SC_P0_DETAIL_QUAD_WITH_3_PIX', 'SC_P0_DETAIL_QUAD_WITH_4_PIX', + 'SC_P0_HIZ_QUAD_COUNT', 'SC_P0_HIZ_QUAD_PER_TILE_H0', + 'SC_P0_HIZ_QUAD_PER_TILE_H1', 'SC_P0_HIZ_QUAD_PER_TILE_H10', + 'SC_P0_HIZ_QUAD_PER_TILE_H11', 'SC_P0_HIZ_QUAD_PER_TILE_H12', + 'SC_P0_HIZ_QUAD_PER_TILE_H13', 'SC_P0_HIZ_QUAD_PER_TILE_H14', + 'SC_P0_HIZ_QUAD_PER_TILE_H15', 'SC_P0_HIZ_QUAD_PER_TILE_H16', + 'SC_P0_HIZ_QUAD_PER_TILE_H2', 'SC_P0_HIZ_QUAD_PER_TILE_H3', + 'SC_P0_HIZ_QUAD_PER_TILE_H4', 'SC_P0_HIZ_QUAD_PER_TILE_H5', + 'SC_P0_HIZ_QUAD_PER_TILE_H6', 'SC_P0_HIZ_QUAD_PER_TILE_H7', + 'SC_P0_HIZ_QUAD_PER_TILE_H8', 'SC_P0_HIZ_QUAD_PER_TILE_H9', + 'SC_P0_HIZ_TILE_COUNT', 'SC_P1_DETAIL_QUAD_COUNT', + 'SC_P1_DETAIL_QUAD_WITH_1_PIX', 'SC_P1_DETAIL_QUAD_WITH_2_PIX', + 'SC_P1_DETAIL_QUAD_WITH_3_PIX', 'SC_P1_DETAIL_QUAD_WITH_4_PIX', + 'SC_P1_HIZ_QUAD_COUNT', 'SC_P1_HIZ_QUAD_PER_TILE_H0', + 'SC_P1_HIZ_QUAD_PER_TILE_H1', 'SC_P1_HIZ_QUAD_PER_TILE_H10', + 'SC_P1_HIZ_QUAD_PER_TILE_H11', 'SC_P1_HIZ_QUAD_PER_TILE_H12', + 'SC_P1_HIZ_QUAD_PER_TILE_H13', 'SC_P1_HIZ_QUAD_PER_TILE_H14', + 'SC_P1_HIZ_QUAD_PER_TILE_H15', 'SC_P1_HIZ_QUAD_PER_TILE_H16', + 'SC_P1_HIZ_QUAD_PER_TILE_H2', 'SC_P1_HIZ_QUAD_PER_TILE_H3', + 'SC_P1_HIZ_QUAD_PER_TILE_H4', 'SC_P1_HIZ_QUAD_PER_TILE_H5', + 'SC_P1_HIZ_QUAD_PER_TILE_H6', 'SC_P1_HIZ_QUAD_PER_TILE_H7', + 'SC_P1_HIZ_QUAD_PER_TILE_H8', 'SC_P1_HIZ_QUAD_PER_TILE_H9', + 'SC_P1_HIZ_TILE_COUNT', 'SC_P2_DETAIL_QUAD_COUNT', + 'SC_P2_DETAIL_QUAD_WITH_1_PIX', 'SC_P2_DETAIL_QUAD_WITH_2_PIX', + 'SC_P2_DETAIL_QUAD_WITH_3_PIX', 'SC_P2_DETAIL_QUAD_WITH_4_PIX', + 'SC_P2_HIZ_QUAD_COUNT', 'SC_P2_HIZ_QUAD_PER_TILE_H0', + 'SC_P2_HIZ_QUAD_PER_TILE_H1', 'SC_P2_HIZ_QUAD_PER_TILE_H10', + 'SC_P2_HIZ_QUAD_PER_TILE_H11', 'SC_P2_HIZ_QUAD_PER_TILE_H12', + 'SC_P2_HIZ_QUAD_PER_TILE_H13', 'SC_P2_HIZ_QUAD_PER_TILE_H14', + 'SC_P2_HIZ_QUAD_PER_TILE_H15', 'SC_P2_HIZ_QUAD_PER_TILE_H16', + 'SC_P2_HIZ_QUAD_PER_TILE_H2', 'SC_P2_HIZ_QUAD_PER_TILE_H3', + 'SC_P2_HIZ_QUAD_PER_TILE_H4', 'SC_P2_HIZ_QUAD_PER_TILE_H5', + 'SC_P2_HIZ_QUAD_PER_TILE_H6', 'SC_P2_HIZ_QUAD_PER_TILE_H7', + 'SC_P2_HIZ_QUAD_PER_TILE_H8', 'SC_P2_HIZ_QUAD_PER_TILE_H9', + 'SC_P2_HIZ_TILE_COUNT', 'SC_P3_DETAIL_QUAD_COUNT', + 'SC_P3_DETAIL_QUAD_WITH_1_PIX', 'SC_P3_DETAIL_QUAD_WITH_2_PIX', + 'SC_P3_DETAIL_QUAD_WITH_3_PIX', 'SC_P3_DETAIL_QUAD_WITH_4_PIX', + 'SC_P3_HIZ_QUAD_COUNT', 'SC_P3_HIZ_QUAD_PER_TILE_H0', + 'SC_P3_HIZ_QUAD_PER_TILE_H1', 'SC_P3_HIZ_QUAD_PER_TILE_H10', + 'SC_P3_HIZ_QUAD_PER_TILE_H11', 'SC_P3_HIZ_QUAD_PER_TILE_H12', + 'SC_P3_HIZ_QUAD_PER_TILE_H13', 'SC_P3_HIZ_QUAD_PER_TILE_H14', + 'SC_P3_HIZ_QUAD_PER_TILE_H15', 'SC_P3_HIZ_QUAD_PER_TILE_H16', + 'SC_P3_HIZ_QUAD_PER_TILE_H2', 'SC_P3_HIZ_QUAD_PER_TILE_H3', + 'SC_P3_HIZ_QUAD_PER_TILE_H4', 'SC_P3_HIZ_QUAD_PER_TILE_H5', + 'SC_P3_HIZ_QUAD_PER_TILE_H6', 'SC_P3_HIZ_QUAD_PER_TILE_H7', + 'SC_P3_HIZ_QUAD_PER_TILE_H8', 'SC_P3_HIZ_QUAD_PER_TILE_H9', + 'SC_P3_HIZ_TILE_COUNT', 'SC_PA0_PS_DATA_SEND', + 'SC_PA0_SC_DATA_FIFO_EOPG_RD', 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE', + 'SC_PA0_SC_DEALLOC_0_RD', 'SC_PA0_SC_DEALLOC_1_RD', + 'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE', 'SC_PA0_SC_EVENT_WE', + 'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE', + 'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE', + 'SC_PA1_PS_DATA_SEND', 'SC_PA1_SC_DATA_FIFO_EOPG_RD', + 'SC_PA1_SC_DATA_FIFO_EOP_RD', 'SC_PA1_SC_DATA_FIFO_RD', + 'SC_PA1_SC_DATA_FIFO_WE', 'SC_PA1_SC_DEALLOC_0_RD', + 'SC_PA1_SC_DEALLOC_1_RD', 'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', + 'SC_PA1_SC_EVENT_WE', 'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE', + 'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE', + 'SC_PA2_PS_DATA_SEND', 'SC_PA2_SC_DATA_FIFO_EOPG_RD', + 'SC_PA2_SC_DATA_FIFO_EOP_RD', 'SC_PA2_SC_DATA_FIFO_RD', + 'SC_PA2_SC_DATA_FIFO_WE', 'SC_PA2_SC_DEALLOC_0_RD', + 'SC_PA2_SC_DEALLOC_1_RD', 'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', + 'SC_PA2_SC_EVENT_WE', 'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE', + 'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE', + 'SC_PA3_PS_DATA_SEND', 'SC_PA3_SC_DATA_FIFO_EOPG_RD', + 'SC_PA3_SC_DATA_FIFO_EOP_RD', 'SC_PA3_SC_DATA_FIFO_RD', + 'SC_PA3_SC_DATA_FIFO_WE', 'SC_PA3_SC_DEALLOC_0_RD', + 'SC_PA3_SC_DEALLOC_1_RD', 'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', + 'SC_PA3_SC_EVENT_WE', 'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE', + 'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE', + 'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE', + 'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE', + 'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE', + 'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE', + 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', 'SC_PBB_BUSY_AND_RTR', + 'SC_PBB_END_OF_BATCH', 'SC_PBB_END_OF_BIN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', + 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', + 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', + 'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT', + 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', + 'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE', + 'SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE', + 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', + 'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS', + 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', + 'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP', + 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', + 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', + 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', + 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', + 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', + 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', + 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_PA0_SC_FIFO_EMPTY', + 'SC_PS_PA0_SC_FIFO_FULL', 'SC_PS_PA1_SC_FIFO_EMPTY', + 'SC_PS_PA1_SC_FIFO_FULL', 'SC_PS_PA2_SC_FIFO_EMPTY', + 'SC_PS_PA2_SC_FIFO_FULL', 'SC_PS_PA3_SC_FIFO_EMPTY', + 'SC_PS_PA3_SC_FIFO_FULL', 'SC_PS_TS_EVENT_FIFO_POP', + 'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_QZ0_MULTI_GPU_TILE_DISCARD', + 'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0', + 'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10', + 'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12', + 'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14', + 'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16', + 'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3', + 'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5', + 'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7', + 'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9', + 'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT', + 'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZ1_MULTI_GPU_TILE_DISCARD', + 'SC_QZ1_QUAD_COUNT', 'SC_QZ1_QUAD_PER_TILE_H0', + 'SC_QZ1_QUAD_PER_TILE_H1', 'SC_QZ1_QUAD_PER_TILE_H10', + 'SC_QZ1_QUAD_PER_TILE_H11', 'SC_QZ1_QUAD_PER_TILE_H12', + 'SC_QZ1_QUAD_PER_TILE_H13', 'SC_QZ1_QUAD_PER_TILE_H14', + 'SC_QZ1_QUAD_PER_TILE_H15', 'SC_QZ1_QUAD_PER_TILE_H16', + 'SC_QZ1_QUAD_PER_TILE_H2', 'SC_QZ1_QUAD_PER_TILE_H3', + 'SC_QZ1_QUAD_PER_TILE_H4', 'SC_QZ1_QUAD_PER_TILE_H5', + 'SC_QZ1_QUAD_PER_TILE_H6', 'SC_QZ1_QUAD_PER_TILE_H7', + 'SC_QZ1_QUAD_PER_TILE_H8', 'SC_QZ1_QUAD_PER_TILE_H9', + 'SC_QZ1_TILE_COUNT', 'SC_QZ1_TILE_COVERED_COUNT', + 'SC_QZ1_TILE_NOT_COVERED_COUNT', 'SC_QZ2_MULTI_GPU_TILE_DISCARD', + 'SC_QZ2_QUAD_COUNT', 'SC_QZ2_QUAD_PER_TILE_H0', + 'SC_QZ2_QUAD_PER_TILE_H1', 'SC_QZ2_QUAD_PER_TILE_H10', + 'SC_QZ2_QUAD_PER_TILE_H11', 'SC_QZ2_QUAD_PER_TILE_H12', + 'SC_QZ2_QUAD_PER_TILE_H13', 'SC_QZ2_QUAD_PER_TILE_H14', + 'SC_QZ2_QUAD_PER_TILE_H15', 'SC_QZ2_QUAD_PER_TILE_H16', + 'SC_QZ2_QUAD_PER_TILE_H2', 'SC_QZ2_QUAD_PER_TILE_H3', + 'SC_QZ2_QUAD_PER_TILE_H4', 'SC_QZ2_QUAD_PER_TILE_H5', + 'SC_QZ2_QUAD_PER_TILE_H6', 'SC_QZ2_QUAD_PER_TILE_H7', + 'SC_QZ2_QUAD_PER_TILE_H8', 'SC_QZ2_QUAD_PER_TILE_H9', + 'SC_QZ2_TILE_COUNT', 'SC_QZ2_TILE_COVERED_COUNT', + 'SC_QZ2_TILE_NOT_COVERED_COUNT', 'SC_QZ3_MULTI_GPU_TILE_DISCARD', + 'SC_QZ3_QUAD_COUNT', 'SC_QZ3_QUAD_PER_TILE_H0', + 'SC_QZ3_QUAD_PER_TILE_H1', 'SC_QZ3_QUAD_PER_TILE_H10', + 'SC_QZ3_QUAD_PER_TILE_H11', 'SC_QZ3_QUAD_PER_TILE_H12', + 'SC_QZ3_QUAD_PER_TILE_H13', 'SC_QZ3_QUAD_PER_TILE_H14', + 'SC_QZ3_QUAD_PER_TILE_H15', 'SC_QZ3_QUAD_PER_TILE_H16', + 'SC_QZ3_QUAD_PER_TILE_H2', 'SC_QZ3_QUAD_PER_TILE_H3', + 'SC_QZ3_QUAD_PER_TILE_H4', 'SC_QZ3_QUAD_PER_TILE_H5', + 'SC_QZ3_QUAD_PER_TILE_H6', 'SC_QZ3_QUAD_PER_TILE_H7', + 'SC_QZ3_QUAD_PER_TILE_H8', 'SC_QZ3_QUAD_PER_TILE_H9', + 'SC_QZ3_TILE_COUNT', 'SC_QZ3_TILE_COVERED_COUNT', + 'SC_QZ3_TILE_NOT_COVERED_COUNT', 'SC_QZQP_WINDOW_VALID', + 'SC_QZQP_WINDOW_VALID_BUSY', 'SC_REG_SCLK_BUSY', 'SC_SCB_BUSY', + 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', + 'SC_SC_PS_ENG_MULTICYCLE_BUBBLE', 'SC_SC_SPI_DEALLOC_0_0', + 'SC_SC_SPI_DEALLOC_0_1', 'SC_SC_SPI_DEALLOC_0_2', + 'SC_SC_SPI_DEALLOC_1_0', 'SC_SC_SPI_DEALLOC_1_1', + 'SC_SC_SPI_DEALLOC_1_2', 'SC_SC_SPI_DEALLOC_2_0', + 'SC_SC_SPI_DEALLOC_2_1', 'SC_SC_SPI_DEALLOC_2_2', + 'SC_SC_SPI_DEALLOC_3_0', 'SC_SC_SPI_DEALLOC_3_1', + 'SC_SC_SPI_DEALLOC_3_2', 'SC_SC_SPI_EVENT', 'SC_SC_SPI_FPOV_0', + 'SC_SC_SPI_FPOV_1', 'SC_SC_SPI_FPOV_2', 'SC_SC_SPI_FPOV_3', + 'SC_SEND_DB_VPZ', 'SC_SRPS_WINDOW_VALID', + 'SC_SRPS_WINDOW_VALID_BUSY', 'SC_STALLED_BY_BCI', + 'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE', + 'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO', + 'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO', + 'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD', + 'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 'SC_SUPERTILE_COUNT', 'SC_SUPERTILE_PER_PRIM_H0', + 'SC_SUPERTILE_PER_PRIM_H1', 'SC_SUPERTILE_PER_PRIM_H10', + 'SC_SUPERTILE_PER_PRIM_H11', 'SC_SUPERTILE_PER_PRIM_H12', + 'SC_SUPERTILE_PER_PRIM_H13', 'SC_SUPERTILE_PER_PRIM_H14', + 'SC_SUPERTILE_PER_PRIM_H15', 'SC_SUPERTILE_PER_PRIM_H16', + 'SC_SUPERTILE_PER_PRIM_H2', 'SC_SUPERTILE_PER_PRIM_H3', + 'SC_SUPERTILE_PER_PRIM_H4', 'SC_SUPERTILE_PER_PRIM_H5', + 'SC_SUPERTILE_PER_PRIM_H6', 'SC_SUPERTILE_PER_PRIM_H7', + 'SC_SUPERTILE_PER_PRIM_H8', 'SC_SUPERTILE_PER_PRIM_H9', + 'SC_TILE_PER_PRIM_H0', 'SC_TILE_PER_PRIM_H1', + 'SC_TILE_PER_PRIM_H10', 'SC_TILE_PER_PRIM_H11', + 'SC_TILE_PER_PRIM_H12', 'SC_TILE_PER_PRIM_H13', + 'SC_TILE_PER_PRIM_H14', 'SC_TILE_PER_PRIM_H15', + 'SC_TILE_PER_PRIM_H16', 'SC_TILE_PER_PRIM_H2', + 'SC_TILE_PER_PRIM_H3', 'SC_TILE_PER_PRIM_H4', + 'SC_TILE_PER_PRIM_H5', 'SC_TILE_PER_PRIM_H6', + 'SC_TILE_PER_PRIM_H7', 'SC_TILE_PER_PRIM_H8', + 'SC_TILE_PER_PRIM_H9', 'SC_TILE_PER_SUPERTILE_H0', + 'SC_TILE_PER_SUPERTILE_H1', 'SC_TILE_PER_SUPERTILE_H10', + 'SC_TILE_PER_SUPERTILE_H11', 'SC_TILE_PER_SUPERTILE_H12', + 'SC_TILE_PER_SUPERTILE_H13', 'SC_TILE_PER_SUPERTILE_H14', + 'SC_TILE_PER_SUPERTILE_H15', 'SC_TILE_PER_SUPERTILE_H16', + 'SC_TILE_PER_SUPERTILE_H2', 'SC_TILE_PER_SUPERTILE_H3', + 'SC_TILE_PER_SUPERTILE_H4', 'SC_TILE_PER_SUPERTILE_H5', + 'SC_TILE_PER_SUPERTILE_H6', 'SC_TILE_PER_SUPERTILE_H7', + 'SC_TILE_PER_SUPERTILE_H8', 'SC_TILE_PER_SUPERTILE_H9', + 'SC_TILE_PICKED_H1', 'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', + 'SC_TILE_PICKED_H4', 'SC_TPQZ_WINDOW_VALID', + 'SC_TPQZ_WINDOW_VALID_BUSY', 'SC_TRPK_WINDOW_VALID', + 'SC_TRPK_WINDOW_VALID_BUSY', 'SDMA_PERF_SEL', + 'SDMA_PERF_SEL_ATCL2_FREE', 'SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', + 'SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', + 'SDMA_PERF_SEL_ATCL2_RET_ACK', 'SDMA_PERF_SEL_ATCL2_RET_XNACK', + 'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_DST_IDLE', + 'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL', + 'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_STALL', + 'SDMA_PERF_SEL_CE_L1_WR_VLD', 'SDMA_PERF_SEL_CE_OUT_IDLE', + 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', + 'SDMA_PERF_SEL_CTX_CHANGE', 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', + 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE', + 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'SDMA_PERF_SEL_F32_L1_WR_VLD', 'SDMA_PERF_SEL_GFX_SELECT', + 'SDMA_PERF_SEL_IB_CMD_FULL', 'SDMA_PERF_SEL_IB_CMD_IDLE', + 'SDMA_PERF_SEL_IDLE', 'SDMA_PERF_SEL_INT_IDLE', + 'SDMA_PERF_SEL_INT_REQ_COUNT', 'SDMA_PERF_SEL_INT_REQ_STALL', + 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', 'SDMA_PERF_SEL_INT_RESP_RETRY', + 'SDMA_PERF_SEL_IS_INVREQ_ADDR_RD', + 'SDMA_PERF_SEL_IS_INVREQ_ADDR_WR', 'SDMA_PERF_SEL_L1_INV_MIDDLE', + 'SDMA_PERF_SEL_L1_RDL2_IDLE', 'SDMA_PERF_SEL_L1_RDMC_IDLE', + 'SDMA_PERF_SEL_L1_RD_FIFO_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_EN', + 'SDMA_PERF_SEL_L1_RD_INV_IDLE', 'SDMA_PERF_SEL_L1_RD_WAIT_INVADR', + 'SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', 'SDMA_PERF_SEL_L1_WRL2_IDLE', + 'SDMA_PERF_SEL_L1_WRMC_IDLE', 'SDMA_PERF_SEL_L1_WR_FIFO_IDLE', + 'SDMA_PERF_SEL_L1_WR_INV_EN', 'SDMA_PERF_SEL_L1_WR_INV_IDLE', + 'SDMA_PERF_SEL_L1_WR_WAIT_INVADR', + 'SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', 'SDMA_PERF_SEL_MC_RD_COUNT', + 'SDMA_PERF_SEL_MC_RD_IDLE', 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', + 'SDMA_PERF_SEL_MC_WR_IDLE', + 'SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER', + 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT', + 'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE', + 'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL', + 'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE', + 'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT', + 'SDMA_PERF_SEL_SDMA_ATCL2_SEND', + 'SDMA_PERF_SEL_SDMA_INVACK_FLUSH', + 'SDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'SDMA_PERF_SEL_SEM_IDLE', + 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', + 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', + 'SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER', + 'SDMA_PERF_SEL_WR_BA_RTR', 'SEC_GSP0_PRIORITY_HIGH', + 'SEC_GSP0_PRIORITY_LOW', 'SEM_ECC_ERROR', 'SEM_FAILED', + 'SEM_PASSED', 'SEM_PERF_SEL', 'SEM_PERF_SEL_ACP_REQ_SIGNAL', + 'SEM_PERF_SEL_ACP_REQ_WAIT', 'SEM_PERF_SEL_ATC_INVALIDATION', + 'SEM_PERF_SEL_ATC_REQ', 'SEM_PERF_SEL_ATC_RET', + 'SEM_PERF_SEL_ATC_XNACK', 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', + 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', + 'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE', + 'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT', + 'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET', + 'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET', + 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT', + 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT', + 'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT', + 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT', + 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT', + 'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT', + 'SEM_TRANS_ERROR', 'SET_OVERRIDE_CGTT_DCEFCLK', + 'SET_OVERRIDE_CGTT_SCLK', 'SET_STATIC_SCREEN_SMU_INTR', + 'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32', + 'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE', + 'SH_MEM_ALIGNMENT_MODE_DWORD', + 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', + 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', + 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', + 'SIMM16_WAITCNT_VM_CNT_HI_SIZE', 'SIMM16_WAITCNT_VM_CNT_HI_START', + 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', + 'SMU_INTR_STATUS_CLEAR', 'SMU_INTR_STATUS_NOOP', + 'SM_MODE_RESERVED', 'SO_VGTSTREAMOUT_FLUSH', 'SPDIF1_SOFT_RESET', + 'SPDIF1_SOFT_RESET_0', 'SPDIF1_SOFT_RESET_1', + 'SPDIF_INVERT_DISABLE', 'SPDIF_INVERT_EN', 'SPDIF_INVERT_ENABLE', + 'SPI_FOG_EXP', 'SPI_FOG_EXP2', 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', + 'SPI_FOG_NONE', 'SPI_PERFCNT_SEL', + 'SPI_PERF_CLKGATE_ACTIVE_STALL', 'SPI_PERF_CLKGATE_ALL_CLOCKS_ON', + 'SPI_PERF_CLKGATE_BUSY_STALL', 'SPI_PERF_CLKGATE_CGTT_DYN_ON', + 'SPI_PERF_CLKGATE_CGTT_REG_ON', 'SPI_PERF_CSG_BUSY', + 'SPI_PERF_CSG_CRAWLER_STALL', 'SPI_PERF_CSG_EVENT_WAVE', + 'SPI_PERF_CSG_NUM_THREADGROUPS', 'SPI_PERF_CSG_WAVE', + 'SPI_PERF_CSG_WINDOW_VALID', 'SPI_PERF_CSN_BUSY', + 'SPI_PERF_CSN_CRAWLER_STALL', 'SPI_PERF_CSN_EVENT_WAVE', + 'SPI_PERF_CSN_NUM_THREADGROUPS', 'SPI_PERF_CSN_WAVE', + 'SPI_PERF_CSN_WINDOW_VALID', 'SPI_PERF_ES_BUSY', + 'SPI_PERF_ES_CRAWLER_STALL', 'SPI_PERF_ES_EVENT_WAVE', + 'SPI_PERF_ES_FIRST_SUBGRP', 'SPI_PERF_ES_FIRST_WAVE', + 'SPI_PERF_ES_GRP_FIFO_FULL', 'SPI_PERF_ES_LAST_SUBGRP', + 'SPI_PERF_ES_LAST_WAVE', 'SPI_PERF_ES_LSHS_DEALLOC', + 'SPI_PERF_ES_PERS_UPD_FULL0', 'SPI_PERF_ES_PERS_UPD_FULL1', + 'SPI_PERF_ES_WAVE', 'SPI_PERF_ES_WINDOW_VALID', + 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', + 'SPI_PERF_EXP_ARB_PAR_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', + 'SPI_PERF_GS_BUSY', 'SPI_PERF_GS_CRAWLER_STALL', + 'SPI_PERF_GS_EVENT_WAVE', 'SPI_PERF_GS_FIRST_SUBGRP', + 'SPI_PERF_GS_GRP_FIFO_FULL', 'SPI_PERF_GS_LAST_SUBGRP', + 'SPI_PERF_GS_PERS_UPD_FULL0', 'SPI_PERF_GS_PERS_UPD_FULL1', + 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID', + 'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL', + 'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE', + 'SPI_PERF_HS_GRP_FIFO_FULL', 'SPI_PERF_HS_LAST_WAVE', + 'SPI_PERF_HS_LSHS_DEALLOC', 'SPI_PERF_HS_PERS_UPD_FULL0', + 'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_WAVE', + 'SPI_PERF_HS_WINDOW_VALID', 'SPI_PERF_LDS0_PC_VALID', + 'SPI_PERF_LDS1_PC_VALID', 'SPI_PERF_LS_BUSY', + 'SPI_PERF_LS_CRAWLER_STALL', 'SPI_PERF_LS_EVENT_WAVE', + 'SPI_PERF_LS_FIRST_WAVE', 'SPI_PERF_LS_GRP_FIFO_FULL', + 'SPI_PERF_LS_LAST_WAVE', 'SPI_PERF_LS_PERS_UPD_FULL0', + 'SPI_PERF_LS_PERS_UPD_FULL1', 'SPI_PERF_LS_WAVE', + 'SPI_PERF_LS_WINDOW_VALID', 'SPI_PERF_NUM_PS_COL_EXPORTS', + 'SPI_PERF_NUM_VS_PARAM_EXPORTS', 'SPI_PERF_NUM_VS_POS_EXPORTS', + 'SPI_PERF_OFFCHIP_LDS_STALL_LS', 'SPI_PERF_PC_ALLOC_ACCUM', + 'SPI_PERF_PC_ALLOC_CNT', 'SPI_PERF_PIX_ALLOC_DB0_STALL', + 'SPI_PERF_PIX_ALLOC_DB1_STALL', 'SPI_PERF_PIX_ALLOC_DB2_STALL', + 'SPI_PERF_PIX_ALLOC_DB3_STALL', 'SPI_PERF_PIX_ALLOC_PEND_CNT', + 'SPI_PERF_PIX_ALLOC_SCB_STALL', 'SPI_PERF_PS_CTL_ACTIVE', + 'SPI_PERF_PS_CTL_BUSY', 'SPI_PERF_PS_CTL_CNF_BIN2', + 'SPI_PERF_PS_CTL_CNF_BIN3', 'SPI_PERF_PS_CTL_CRAWLER_STALL', + 'SPI_PERF_PS_CTL_DEALLOC_BIN0', 'SPI_PERF_PS_CTL_EVENT_WAVE', + 'SPI_PERF_PS_CTL_FPOS_BIN1_STALL', 'SPI_PERF_PS_CTL_FPOS_BIN2', + 'SPI_PERF_PS_CTL_LDS_RES_FULL', 'SPI_PERF_PS_CTL_OPT_WAVE', + 'SPI_PERF_PS_CTL_PASS_BIN0', 'SPI_PERF_PS_CTL_PASS_BIN1', + 'SPI_PERF_PS_CTL_PRIM_BIN0', 'SPI_PERF_PS_CTL_PRIM_BIN1', + 'SPI_PERF_PS_CTL_WAVE', 'SPI_PERF_PS_CTL_WINDOW_VALID', + 'SPI_PERF_PS_PERS_UPD_FULL0', 'SPI_PERF_PS_PERS_UPD_FULL1', + 'SPI_PERF_RA_BAR_CU_FULL_CSG', 'SPI_PERF_RA_BAR_CU_FULL_CSN', + 'SPI_PERF_RA_BAR_CU_FULL_HS', 'SPI_PERF_RA_BULKY_CU_FULL_CSG', + 'SPI_PERF_RA_BULKY_CU_FULL_CSN', 'SPI_PERF_RA_CSG_LOCK', + 'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_ES_LOCK', + 'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK', + 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 'SPI_PERF_RA_LDS_CU_FULL_ES', 'SPI_PERF_RA_LDS_CU_FULL_LS', + 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_LS_LOCK', + 'SPI_PERF_RA_PIPE_REQ_BIN2', 'SPI_PERF_RA_PS_LOCK_NA', + 'SPI_PERF_RA_REQ_NO_ALLOC', 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', + 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', 'SPI_PERF_RA_REQ_NO_ALLOC_ES', + 'SPI_PERF_RA_REQ_NO_ALLOC_GS', 'SPI_PERF_RA_REQ_NO_ALLOC_HS', + 'SPI_PERF_RA_REQ_NO_ALLOC_LS', 'SPI_PERF_RA_REQ_NO_ALLOC_PS', + 'SPI_PERF_RA_REQ_NO_ALLOC_VS', 'SPI_PERF_RA_RES_STALL_CSG', + 'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_ES', + 'SPI_PERF_RA_RES_STALL_GS', 'SPI_PERF_RA_RES_STALL_HS', + 'SPI_PERF_RA_RES_STALL_LS', 'SPI_PERF_RA_RES_STALL_PS', + 'SPI_PERF_RA_RES_STALL_VS', 'SPI_PERF_RA_RSV_UPD', + 'SPI_PERF_RA_SGPR_SIMD_FULL_CSG', + 'SPI_PERF_RA_SGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_SGPR_SIMD_FULL_ES', + 'SPI_PERF_RA_SGPR_SIMD_FULL_GS', 'SPI_PERF_RA_SGPR_SIMD_FULL_HS', + 'SPI_PERF_RA_SGPR_SIMD_FULL_LS', 'SPI_PERF_RA_SGPR_SIMD_FULL_PS', + 'SPI_PERF_RA_SGPR_SIMD_FULL_VS', 'SPI_PERF_RA_TASK_REQ_BIN3', + 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', + 'SPI_PERF_RA_TMP_STALL_ES', 'SPI_PERF_RA_TMP_STALL_GS', + 'SPI_PERF_RA_TMP_STALL_HS', 'SPI_PERF_RA_TMP_STALL_LS', + 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_TMP_STALL_VS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_ES', + 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_LS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_VS', 'SPI_PERF_RA_VS_LOCK', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_ES', + 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_LS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_VS', 'SPI_PERF_RA_WR_CTL_FULL', + 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', + 'SPI_PERF_RA_WVLIM_STALL_ES', 'SPI_PERF_RA_WVLIM_STALL_GS', + 'SPI_PERF_RA_WVLIM_STALL_HS', 'SPI_PERF_RA_WVLIM_STALL_LS', + 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_RA_WVLIM_STALL_VS', + 'SPI_PERF_VS_ALLOC_CNT', 'SPI_PERF_VS_BUSY', + 'SPI_PERF_VS_CRAWLER_STALL', 'SPI_PERF_VS_EVENT_WAVE', + 'SPI_PERF_VS_FIRST_SUBGRP', 'SPI_PERF_VS_FIRST_WAVE', + 'SPI_PERF_VS_LAST_SUBGRP', 'SPI_PERF_VS_LAST_WAVE', + 'SPI_PERF_VS_LATE_ALLOC_ACCUM', 'SPI_PERF_VS_LATE_ALLOC_FULL', + 'SPI_PERF_VS_LSHS_DEALLOC', 'SPI_PERF_VS_PC_STALL', + 'SPI_PERF_VS_PERS_UPD_FULL0', 'SPI_PERF_VS_PERS_UPD_FULL1', + 'SPI_PERF_VS_POS0_STALL', 'SPI_PERF_VS_POS1_STALL', + 'SPI_PERF_VS_WAVE', 'SPI_PERF_VS_WINDOW_VALID', + 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', + 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', + 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', 'SPI_SAMPLE_CNTL', + 'SPI_SHADER_1COMP', 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', + 'SPI_SHADER_32_AR', 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', + 'SPI_SHADER_4COMP', 'SPI_SHADER_4COMPRESS', + 'SPI_SHADER_EX_FORMAT', 'SPI_SHADER_FORMAT', + 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', + 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', + 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', + 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', + 'SQC_PERF_SEL_DCACHE_ATOMIC', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED', + 'SQC_PERF_SEL_DCACHE_FLAT_REQ', + 'SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT', + 'SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL', + 'SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL', + 'SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS', + 'SQC_PERF_SEL_DCACHE_GATCL1_REQUEST', + 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', + 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES', + 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT', + 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL', + 'SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS', + 'SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS', + 'SQC_PERF_SEL_DCACHE_HITS', 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_DCACHE_INPUT_VALIDB', + 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READY', + 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_DCACHE_INVAL_INST', + 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC', + 'SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST', + 'SQC_PERF_SEL_DCACHE_MISSES', + 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', + 'SQC_PERF_SEL_DCACHE_MISS_EVICT_READ', + 'SQC_PERF_SEL_DCACHE_NONFLAT_REQ', 'SQC_PERF_SEL_DCACHE_REQ', + 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 'SQC_PERF_SEL_DCACHE_REQ_READ_8', 'SQC_PERF_SEL_DCACHE_REQ_TIME', + 'SQC_PERF_SEL_DCACHE_REQ_WRITE_1', + 'SQC_PERF_SEL_DCACHE_REQ_WRITE_2', + 'SQC_PERF_SEL_DCACHE_REQ_WRITE_4', + 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DCACHE_VOLATILE', 'SQC_PERF_SEL_DCACHE_WB_ASYNC', + 'SQC_PERF_SEL_DCACHE_WB_INST', + 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC', + 'SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST', + 'SQC_PERF_SEL_DCACHE_WC_LRU_WRITE', + 'SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE', 'SQC_PERF_SEL_DUMMY_LAST', + 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF', + 'SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT', + 'SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL', + 'SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS', + 'SQC_PERF_SEL_ICACHE_GATCL1_REQUEST', + 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS', + 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES', + 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT', + 'SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL', + 'SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS', + 'SQC_PERF_SEL_ICACHE_HITS', 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_ICACHE_INPUT_VALIDB', + 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READY', + 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', + 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', + 'SQC_PERF_SEL_ICACHE_PREFETCH_1', + 'SQC_PERF_SEL_ICACHE_PREFETCH_2', + 'SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED', + 'SQC_PERF_SEL_ICACHE_REQ', + 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_ATOMIC_REQ', + 'SQC_PERF_SEL_TC_DATA_READ_REQ', 'SQC_PERF_SEL_TC_DATA_WRITE_REQ', + 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', + 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', + 'SQC_PERF_SEL_TC_STARVE', 'SQDEC_BEGIN', 'SQDEC_END', + 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', 'SQIND_GLOBAL_REGS_OFFSET', + 'SQIND_GLOBAL_REGS_SIZE', 'SQIND_LOCAL_REGS_OFFSET', + 'SQIND_LOCAL_REGS_SIZE', 'SQIND_WAVE_HWREGS_OFFSET', + 'SQIND_WAVE_HWREGS_SIZE', 'SQIND_WAVE_SGPRS_OFFSET', + 'SQIND_WAVE_SGPRS_SIZE', 'SQIND_WAVE_VGPRS_OFFSET', + 'SQIND_WAVE_VGPRS_SIZE', 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', + 'SQPERFSDEC_BEGIN', 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', + 'SQPWRDEC_END', 'SQ_ATTR0', 'SQ_BUFFER_ATOMIC_ADD', + 'SQ_BUFFER_ATOMIC_ADD_X2', 'SQ_BUFFER_ATOMIC_AND', + 'SQ_BUFFER_ATOMIC_AND_X2', 'SQ_BUFFER_ATOMIC_CMPSWAP', + 'SQ_BUFFER_ATOMIC_CMPSWAP_X2', 'SQ_BUFFER_ATOMIC_DEC', + 'SQ_BUFFER_ATOMIC_DEC_X2', 'SQ_BUFFER_ATOMIC_INC', + 'SQ_BUFFER_ATOMIC_INC_X2', 'SQ_BUFFER_ATOMIC_OR', + 'SQ_BUFFER_ATOMIC_OR_X2', 'SQ_BUFFER_ATOMIC_SMAX', + 'SQ_BUFFER_ATOMIC_SMAX_X2', 'SQ_BUFFER_ATOMIC_SMIN', + 'SQ_BUFFER_ATOMIC_SMIN_X2', 'SQ_BUFFER_ATOMIC_SUB', + 'SQ_BUFFER_ATOMIC_SUB_X2', 'SQ_BUFFER_ATOMIC_SWAP', + 'SQ_BUFFER_ATOMIC_SWAP_X2', 'SQ_BUFFER_ATOMIC_UMAX', + 'SQ_BUFFER_ATOMIC_UMAX_X2', 'SQ_BUFFER_ATOMIC_UMIN', + 'SQ_BUFFER_ATOMIC_UMIN_X2', 'SQ_BUFFER_ATOMIC_XOR', + 'SQ_BUFFER_ATOMIC_XOR_X2', 'SQ_BUFFER_LOAD_DWORD', + 'SQ_BUFFER_LOAD_DWORDX2', 'SQ_BUFFER_LOAD_DWORDX3', + 'SQ_BUFFER_LOAD_DWORDX4', 'SQ_BUFFER_LOAD_FORMAT_D16_X', + 'SQ_BUFFER_LOAD_FORMAT_D16_XY', 'SQ_BUFFER_LOAD_FORMAT_D16_XYZ', + 'SQ_BUFFER_LOAD_FORMAT_D16_XYZW', 'SQ_BUFFER_LOAD_FORMAT_X', + 'SQ_BUFFER_LOAD_FORMAT_XY', 'SQ_BUFFER_LOAD_FORMAT_XYZ', + 'SQ_BUFFER_LOAD_FORMAT_XYZW', 'SQ_BUFFER_LOAD_SBYTE', + 'SQ_BUFFER_LOAD_SSHORT', 'SQ_BUFFER_LOAD_UBYTE', + 'SQ_BUFFER_LOAD_USHORT', 'SQ_BUFFER_STORE_BYTE', + 'SQ_BUFFER_STORE_DWORD', 'SQ_BUFFER_STORE_DWORDX2', + 'SQ_BUFFER_STORE_DWORDX3', 'SQ_BUFFER_STORE_DWORDX4', + 'SQ_BUFFER_STORE_FORMAT_D16_X', 'SQ_BUFFER_STORE_FORMAT_D16_XY', + 'SQ_BUFFER_STORE_FORMAT_D16_XYZ', + 'SQ_BUFFER_STORE_FORMAT_D16_XYZW', 'SQ_BUFFER_STORE_FORMAT_X', + 'SQ_BUFFER_STORE_FORMAT_XY', 'SQ_BUFFER_STORE_FORMAT_XYZ', + 'SQ_BUFFER_STORE_FORMAT_XYZW', 'SQ_BUFFER_STORE_LDS_DWORD', + 'SQ_BUFFER_STORE_SHORT', 'SQ_BUFFER_WBINVL1', + 'SQ_BUFFER_WBINVL1_VOL', 'SQ_CAC_POWER_ALU_BUSY', + 'SQ_CAC_POWER_GPR_RD', 'SQ_CAC_POWER_GPR_WR', + 'SQ_CAC_POWER_LDS_BUSY', 'SQ_CAC_POWER_SEL', + 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', + 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', + 'SQ_CHAN_W', 'SQ_CHAN_X', 'SQ_CHAN_Y', 'SQ_CHAN_Z', 'SQ_CNT1', + 'SQ_CNT2', 'SQ_CNT3', 'SQ_CNT4', 'SQ_DISPATCHER_GFX_CNT_PER_RING', + 'SQ_DISPATCHER_GFX_MIN', 'SQ_DPP_BOUND_OFF', 'SQ_DPP_BOUND_ZERO', + 'SQ_DPP_QUAD_PERM', 'SQ_DPP_ROW_BCAST15', 'SQ_DPP_ROW_BCAST31', + 'SQ_DPP_ROW_HALF_MIRROR', 'SQ_DPP_ROW_MIRROR', 'SQ_DPP_ROW_RR1', + 'SQ_DPP_ROW_RR10', 'SQ_DPP_ROW_RR11', 'SQ_DPP_ROW_RR12', + 'SQ_DPP_ROW_RR13', 'SQ_DPP_ROW_RR14', 'SQ_DPP_ROW_RR15', + 'SQ_DPP_ROW_RR2', 'SQ_DPP_ROW_RR3', 'SQ_DPP_ROW_RR4', + 'SQ_DPP_ROW_RR5', 'SQ_DPP_ROW_RR6', 'SQ_DPP_ROW_RR7', + 'SQ_DPP_ROW_RR8', 'SQ_DPP_ROW_RR9', 'SQ_DPP_ROW_SL1', + 'SQ_DPP_ROW_SL10', 'SQ_DPP_ROW_SL11', 'SQ_DPP_ROW_SL12', + 'SQ_DPP_ROW_SL13', 'SQ_DPP_ROW_SL14', 'SQ_DPP_ROW_SL15', + 'SQ_DPP_ROW_SL2', 'SQ_DPP_ROW_SL3', 'SQ_DPP_ROW_SL4', + 'SQ_DPP_ROW_SL5', 'SQ_DPP_ROW_SL6', 'SQ_DPP_ROW_SL7', + 'SQ_DPP_ROW_SL8', 'SQ_DPP_ROW_SL9', 'SQ_DPP_ROW_SR1', + 'SQ_DPP_ROW_SR10', 'SQ_DPP_ROW_SR11', 'SQ_DPP_ROW_SR12', + 'SQ_DPP_ROW_SR13', 'SQ_DPP_ROW_SR14', 'SQ_DPP_ROW_SR15', + 'SQ_DPP_ROW_SR2', 'SQ_DPP_ROW_SR3', 'SQ_DPP_ROW_SR4', + 'SQ_DPP_ROW_SR5', 'SQ_DPP_ROW_SR6', 'SQ_DPP_ROW_SR7', + 'SQ_DPP_ROW_SR8', 'SQ_DPP_ROW_SR9', 'SQ_DPP_WF_RL1', + 'SQ_DPP_WF_RR1', 'SQ_DPP_WF_SL1', 'SQ_DPP_WF_SR1', + 'SQ_DS_ADD_F32', 'SQ_DS_ADD_RTN_F32', 'SQ_DS_ADD_RTN_U32', + 'SQ_DS_ADD_RTN_U64', 'SQ_DS_ADD_SRC2_F32', 'SQ_DS_ADD_SRC2_U32', + 'SQ_DS_ADD_SRC2_U64', 'SQ_DS_ADD_U32', 'SQ_DS_ADD_U64', + 'SQ_DS_AND_B32', 'SQ_DS_AND_B64', 'SQ_DS_AND_RTN_B32', + 'SQ_DS_AND_RTN_B64', 'SQ_DS_AND_SRC2_B32', 'SQ_DS_AND_SRC2_B64', + 'SQ_DS_APPEND', 'SQ_DS_BPERMUTE_B32', 'SQ_DS_CMPST_B32', + 'SQ_DS_CMPST_B64', 'SQ_DS_CMPST_F32', 'SQ_DS_CMPST_F64', + 'SQ_DS_CMPST_RTN_B32', 'SQ_DS_CMPST_RTN_B64', + 'SQ_DS_CMPST_RTN_F32', 'SQ_DS_CMPST_RTN_F64', + 'SQ_DS_CONDXCHG32_RTN_B128', 'SQ_DS_CONDXCHG32_RTN_B64', + 'SQ_DS_CONSUME', 'SQ_DS_DEC_RTN_U32', 'SQ_DS_DEC_RTN_U64', + 'SQ_DS_DEC_SRC2_U32', 'SQ_DS_DEC_SRC2_U64', 'SQ_DS_DEC_U32', + 'SQ_DS_DEC_U64', 'SQ_DS_GWS_BARRIER', 'SQ_DS_GWS_INIT', + 'SQ_DS_GWS_SEMA_BR', 'SQ_DS_GWS_SEMA_P', + 'SQ_DS_GWS_SEMA_RELEASE_ALL', 'SQ_DS_GWS_SEMA_V', + 'SQ_DS_INC_RTN_U32', 'SQ_DS_INC_RTN_U64', 'SQ_DS_INC_SRC2_U32', + 'SQ_DS_INC_SRC2_U64', 'SQ_DS_INC_U32', 'SQ_DS_INC_U64', + 'SQ_DS_MAX_F32', 'SQ_DS_MAX_F64', 'SQ_DS_MAX_I32', + 'SQ_DS_MAX_I64', 'SQ_DS_MAX_RTN_F32', 'SQ_DS_MAX_RTN_F64', + 'SQ_DS_MAX_RTN_I32', 'SQ_DS_MAX_RTN_I64', 'SQ_DS_MAX_RTN_U32', + 'SQ_DS_MAX_RTN_U64', 'SQ_DS_MAX_SRC2_F32', 'SQ_DS_MAX_SRC2_F64', + 'SQ_DS_MAX_SRC2_I32', 'SQ_DS_MAX_SRC2_I64', 'SQ_DS_MAX_SRC2_U32', + 'SQ_DS_MAX_SRC2_U64', 'SQ_DS_MAX_U32', 'SQ_DS_MAX_U64', + 'SQ_DS_MIN_F32', 'SQ_DS_MIN_F64', 'SQ_DS_MIN_I32', + 'SQ_DS_MIN_I64', 'SQ_DS_MIN_RTN_F32', 'SQ_DS_MIN_RTN_F64', + 'SQ_DS_MIN_RTN_I32', 'SQ_DS_MIN_RTN_I64', 'SQ_DS_MIN_RTN_U32', + 'SQ_DS_MIN_RTN_U64', 'SQ_DS_MIN_SRC2_F32', 'SQ_DS_MIN_SRC2_F64', + 'SQ_DS_MIN_SRC2_I32', 'SQ_DS_MIN_SRC2_I64', 'SQ_DS_MIN_SRC2_U32', + 'SQ_DS_MIN_SRC2_U64', 'SQ_DS_MIN_U32', 'SQ_DS_MIN_U64', + 'SQ_DS_MSKOR_B32', 'SQ_DS_MSKOR_B64', 'SQ_DS_MSKOR_RTN_B32', + 'SQ_DS_MSKOR_RTN_B64', 'SQ_DS_NOP', 'SQ_DS_ORDERED_COUNT', + 'SQ_DS_OR_B32', 'SQ_DS_OR_B64', 'SQ_DS_OR_RTN_B32', + 'SQ_DS_OR_RTN_B64', 'SQ_DS_OR_SRC2_B32', 'SQ_DS_OR_SRC2_B64', + 'SQ_DS_PERMUTE_B32', 'SQ_DS_READ2ST64_B32', 'SQ_DS_READ2ST64_B64', + 'SQ_DS_READ2_B32', 'SQ_DS_READ2_B64', 'SQ_DS_READ_ADDTID_B32', + 'SQ_DS_READ_B128', 'SQ_DS_READ_B32', 'SQ_DS_READ_B64', + 'SQ_DS_READ_B96', 'SQ_DS_READ_I16', 'SQ_DS_READ_I8', + 'SQ_DS_READ_U16', 'SQ_DS_READ_U8', 'SQ_DS_RSUB_RTN_U32', + 'SQ_DS_RSUB_RTN_U64', 'SQ_DS_RSUB_SRC2_U32', + 'SQ_DS_RSUB_SRC2_U64', 'SQ_DS_RSUB_U32', 'SQ_DS_RSUB_U64', + 'SQ_DS_SUB_RTN_U32', 'SQ_DS_SUB_RTN_U64', 'SQ_DS_SUB_SRC2_U32', + 'SQ_DS_SUB_SRC2_U64', 'SQ_DS_SUB_U32', 'SQ_DS_SUB_U64', + 'SQ_DS_SWIZZLE_B32', 'SQ_DS_WRAP_RTN_B32', 'SQ_DS_WRITE2ST64_B32', + 'SQ_DS_WRITE2ST64_B64', 'SQ_DS_WRITE2_B32', 'SQ_DS_WRITE2_B64', + 'SQ_DS_WRITE_ADDTID_B32', 'SQ_DS_WRITE_B128', 'SQ_DS_WRITE_B16', + 'SQ_DS_WRITE_B32', 'SQ_DS_WRITE_B64', 'SQ_DS_WRITE_B8', + 'SQ_DS_WRITE_B96', 'SQ_DS_WRITE_SRC2_B32', 'SQ_DS_WRITE_SRC2_B64', + 'SQ_DS_WRXCHG2ST64_RTN_B32', 'SQ_DS_WRXCHG2ST64_RTN_B64', + 'SQ_DS_WRXCHG2_RTN_B32', 'SQ_DS_WRXCHG2_RTN_B64', + 'SQ_DS_WRXCHG_RTN_B32', 'SQ_DS_WRXCHG_RTN_B64', 'SQ_DS_XOR_B32', + 'SQ_DS_XOR_B64', 'SQ_DS_XOR_RTN_B32', 'SQ_DS_XOR_RTN_B64', + 'SQ_DS_XOR_SRC2_B32', 'SQ_DS_XOR_SRC2_B64', 'SQ_EDC_FUE_CNTL_LDS', + 'SQ_EDC_FUE_CNTL_SIMD0', 'SQ_EDC_FUE_CNTL_SIMD1', + 'SQ_EDC_FUE_CNTL_SIMD2', 'SQ_EDC_FUE_CNTL_SIMD3', + 'SQ_EDC_FUE_CNTL_SQ', 'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', + 'SQ_EDC_FUE_CNTL_TD', 'SQ_EDC_INFO_SOURCE', + 'SQ_EDC_INFO_SOURCE_GDS', 'SQ_EDC_INFO_SOURCE_INST', + 'SQ_EDC_INFO_SOURCE_INVALID', 'SQ_EDC_INFO_SOURCE_LDS', + 'SQ_EDC_INFO_SOURCE_SGPR', 'SQ_EDC_INFO_SOURCE_TA', + 'SQ_EDC_INFO_SOURCE_VGPR', 'SQ_ENC_DS_BITS', 'SQ_ENC_DS_FIELD', + 'SQ_ENC_DS_MASK', 'SQ_ENC_EXP_BITS', 'SQ_ENC_EXP_FIELD', + 'SQ_ENC_EXP_MASK', 'SQ_ENC_FLAT_BITS', 'SQ_ENC_FLAT_FIELD', + 'SQ_ENC_FLAT_MASK', 'SQ_ENC_MIMG_BITS', 'SQ_ENC_MIMG_FIELD', + 'SQ_ENC_MIMG_MASK', 'SQ_ENC_MTBUF_BITS', 'SQ_ENC_MTBUF_FIELD', + 'SQ_ENC_MTBUF_MASK', 'SQ_ENC_MUBUF_BITS', 'SQ_ENC_MUBUF_FIELD', + 'SQ_ENC_MUBUF_MASK', 'SQ_ENC_SMEM_BITS', 'SQ_ENC_SMEM_FIELD', + 'SQ_ENC_SMEM_MASK', 'SQ_ENC_SOP1_BITS', 'SQ_ENC_SOP1_FIELD', + 'SQ_ENC_SOP1_MASK', 'SQ_ENC_SOP2_BITS', 'SQ_ENC_SOP2_FIELD', + 'SQ_ENC_SOP2_MASK', 'SQ_ENC_SOPC_BITS', 'SQ_ENC_SOPC_FIELD', + 'SQ_ENC_SOPC_MASK', 'SQ_ENC_SOPK_BITS', 'SQ_ENC_SOPK_FIELD', + 'SQ_ENC_SOPK_MASK', 'SQ_ENC_SOPP_BITS', 'SQ_ENC_SOPP_FIELD', + 'SQ_ENC_SOPP_MASK', 'SQ_ENC_VINTRP_BITS', 'SQ_ENC_VINTRP_FIELD', + 'SQ_ENC_VINTRP_MASK', 'SQ_ENC_VOP1_BITS', 'SQ_ENC_VOP1_FIELD', + 'SQ_ENC_VOP1_MASK', 'SQ_ENC_VOP2_BITS', 'SQ_ENC_VOP2_FIELD', + 'SQ_ENC_VOP2_MASK', 'SQ_ENC_VOP3P_BITS', 'SQ_ENC_VOP3P_FIELD', + 'SQ_ENC_VOP3P_MASK', 'SQ_ENC_VOP3_BITS', 'SQ_ENC_VOP3_FIELD', + 'SQ_ENC_VOP3_MASK', 'SQ_ENC_VOPC_BITS', 'SQ_ENC_VOPC_FIELD', + 'SQ_ENC_VOPC_MASK', 'SQ_EQ', 'SQ_EXEC_HI', 'SQ_EXEC_LO', 'SQ_EXP', + 'SQ_EXPORT_RAT_INST_ADD', 'SQ_EXPORT_RAT_INST_ADD_RTN', + 'SQ_EXPORT_RAT_INST_AND', 'SQ_EXPORT_RAT_INST_AND_RTN', + 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM', + 'SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN', + 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT', + 'SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN', + 'SQ_EXPORT_RAT_INST_CMPXCHG_INT', + 'SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN', + 'SQ_EXPORT_RAT_INST_DEC_UINT', 'SQ_EXPORT_RAT_INST_DEC_UINT_RTN', + 'SQ_EXPORT_RAT_INST_INC_UINT', 'SQ_EXPORT_RAT_INST_INC_UINT_RTN', + 'SQ_EXPORT_RAT_INST_MAX_INT', 'SQ_EXPORT_RAT_INST_MAX_INT_RTN', + 'SQ_EXPORT_RAT_INST_MAX_UINT', 'SQ_EXPORT_RAT_INST_MAX_UINT_RTN', + 'SQ_EXPORT_RAT_INST_MIN_INT', 'SQ_EXPORT_RAT_INST_MIN_INT_RTN', + 'SQ_EXPORT_RAT_INST_MIN_UINT', 'SQ_EXPORT_RAT_INST_MIN_UINT_RTN', + 'SQ_EXPORT_RAT_INST_MSKOR', 'SQ_EXPORT_RAT_INST_MSKOR_RTN', + 'SQ_EXPORT_RAT_INST_NOP', 'SQ_EXPORT_RAT_INST_NOP_RTN', + 'SQ_EXPORT_RAT_INST_OR', 'SQ_EXPORT_RAT_INST_OR_RTN', + 'SQ_EXPORT_RAT_INST_RSUB', 'SQ_EXPORT_RAT_INST_RSUB_RTN', + 'SQ_EXPORT_RAT_INST_STORE_BYTE', 'SQ_EXPORT_RAT_INST_STORE_DWORD', + 'SQ_EXPORT_RAT_INST_STORE_RAW', + 'SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM', + 'SQ_EXPORT_RAT_INST_STORE_SHORT', + 'SQ_EXPORT_RAT_INST_STORE_TYPED', 'SQ_EXPORT_RAT_INST_SUB', + 'SQ_EXPORT_RAT_INST_SUB_RTN', + 'SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN', + 'SQ_EXPORT_RAT_INST_XCHG_RTN', 'SQ_EXPORT_RAT_INST_XOR', + 'SQ_EXPORT_RAT_INST_XOR_RTN', 'SQ_EXP_GDS0', 'SQ_EXP_MRT0', + 'SQ_EXP_MRTZ', 'SQ_EXP_NULL', 'SQ_EXP_NUM_GDS', 'SQ_EXP_NUM_MRT', + 'SQ_EXP_NUM_PARAM', 'SQ_EXP_NUM_POS', 'SQ_EXP_PARAM0', + 'SQ_EXP_POS0', 'SQ_EX_MODE_EXCP_ADDR_WATCH0', + 'SQ_EX_MODE_EXCP_DIV0', 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT', + 'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0', + 'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL', + 'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW', + 'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE', 'SQ_F', + 'SQ_FLAT', 'SQ_FLAT_ATOMIC_ADD', 'SQ_FLAT_ATOMIC_ADD_X2', + 'SQ_FLAT_ATOMIC_AND', 'SQ_FLAT_ATOMIC_AND_X2', + 'SQ_FLAT_ATOMIC_CMPSWAP', 'SQ_FLAT_ATOMIC_CMPSWAP_X2', + 'SQ_FLAT_ATOMIC_DEC', 'SQ_FLAT_ATOMIC_DEC_X2', + 'SQ_FLAT_ATOMIC_INC', 'SQ_FLAT_ATOMIC_INC_X2', + 'SQ_FLAT_ATOMIC_OR', 'SQ_FLAT_ATOMIC_OR_X2', + 'SQ_FLAT_ATOMIC_SMAX', 'SQ_FLAT_ATOMIC_SMAX_X2', + 'SQ_FLAT_ATOMIC_SMIN', 'SQ_FLAT_ATOMIC_SMIN_X2', + 'SQ_FLAT_ATOMIC_SUB', 'SQ_FLAT_ATOMIC_SUB_X2', + 'SQ_FLAT_ATOMIC_SWAP', 'SQ_FLAT_ATOMIC_SWAP_X2', + 'SQ_FLAT_ATOMIC_UMAX', 'SQ_FLAT_ATOMIC_UMAX_X2', + 'SQ_FLAT_ATOMIC_UMIN', 'SQ_FLAT_ATOMIC_UMIN_X2', + 'SQ_FLAT_ATOMIC_XOR', 'SQ_FLAT_ATOMIC_XOR_X2', + 'SQ_FLAT_LOAD_DWORD', 'SQ_FLAT_LOAD_DWORDX2', + 'SQ_FLAT_LOAD_DWORDX3', 'SQ_FLAT_LOAD_DWORDX4', + 'SQ_FLAT_LOAD_SBYTE', 'SQ_FLAT_LOAD_SSHORT', 'SQ_FLAT_LOAD_UBYTE', + 'SQ_FLAT_LOAD_USHORT', 'SQ_FLAT_SCRATCH_HI', 'SQ_FLAT_SCRATCH_LO', + 'SQ_FLAT_STORE_BYTE', 'SQ_FLAT_STORE_DWORD', + 'SQ_FLAT_STORE_DWORDX2', 'SQ_FLAT_STORE_DWORDX3', + 'SQ_FLAT_STORE_DWORDX4', 'SQ_FLAT_STORE_SHORT', 'SQ_GE', + 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', + 'SQ_GLOBAL', 'SQ_GLOBAL_ATOMIC_ADD', 'SQ_GLOBAL_ATOMIC_ADD_X2', + 'SQ_GLOBAL_ATOMIC_AND', 'SQ_GLOBAL_ATOMIC_AND_X2', + 'SQ_GLOBAL_ATOMIC_CMPSWAP', 'SQ_GLOBAL_ATOMIC_CMPSWAP_X2', + 'SQ_GLOBAL_ATOMIC_DEC', 'SQ_GLOBAL_ATOMIC_DEC_X2', + 'SQ_GLOBAL_ATOMIC_INC', 'SQ_GLOBAL_ATOMIC_INC_X2', + 'SQ_GLOBAL_ATOMIC_OR', 'SQ_GLOBAL_ATOMIC_OR_X2', + 'SQ_GLOBAL_ATOMIC_SMAX', 'SQ_GLOBAL_ATOMIC_SMAX_X2', + 'SQ_GLOBAL_ATOMIC_SMIN', 'SQ_GLOBAL_ATOMIC_SMIN_X2', + 'SQ_GLOBAL_ATOMIC_SUB', 'SQ_GLOBAL_ATOMIC_SUB_X2', + 'SQ_GLOBAL_ATOMIC_SWAP', 'SQ_GLOBAL_ATOMIC_SWAP_X2', + 'SQ_GLOBAL_ATOMIC_UMAX', 'SQ_GLOBAL_ATOMIC_UMAX_X2', + 'SQ_GLOBAL_ATOMIC_UMIN', 'SQ_GLOBAL_ATOMIC_UMIN_X2', + 'SQ_GLOBAL_ATOMIC_XOR', 'SQ_GLOBAL_ATOMIC_XOR_X2', + 'SQ_GLOBAL_LOAD_DWORD', 'SQ_GLOBAL_LOAD_DWORDX2', + 'SQ_GLOBAL_LOAD_DWORDX3', 'SQ_GLOBAL_LOAD_DWORDX4', + 'SQ_GLOBAL_LOAD_SBYTE', 'SQ_GLOBAL_LOAD_SSHORT', + 'SQ_GLOBAL_LOAD_UBYTE', 'SQ_GLOBAL_LOAD_USHORT', + 'SQ_GLOBAL_STORE_BYTE', 'SQ_GLOBAL_STORE_DWORD', + 'SQ_GLOBAL_STORE_DWORDX2', 'SQ_GLOBAL_STORE_DWORDX3', + 'SQ_GLOBAL_STORE_DWORDX4', 'SQ_GLOBAL_STORE_SHORT', + 'SQ_GS_OP_CUT', 'SQ_GS_OP_EMIT', 'SQ_GS_OP_EMIT_CUT', + 'SQ_GS_OP_NOP', 'SQ_GT', 'SQ_HWREG_ID_SHIFT', 'SQ_HWREG_ID_SIZE', + 'SQ_HWREG_OFFSET_SHIFT', 'SQ_HWREG_OFFSET_SIZE', + 'SQ_HWREG_SIZE_SHIFT', 'SQ_HWREG_SIZE_SIZE', 'SQ_HW_REG_FLUSH_IB', + 'SQ_HW_REG_GPR_ALLOC', 'SQ_HW_REG_HW_ID', 'SQ_HW_REG_IB_DBG0', + 'SQ_HW_REG_IB_DBG1', 'SQ_HW_REG_IB_STS', 'SQ_HW_REG_INST_DW0', + 'SQ_HW_REG_INST_DW1', 'SQ_HW_REG_LDS_ALLOC', 'SQ_HW_REG_MODE', + 'SQ_HW_REG_PC_HI', 'SQ_HW_REG_PC_LO', 'SQ_HW_REG_SH_MEM_BASES', + 'SQ_HW_REG_SQ_SHADER_TBA_HI', 'SQ_HW_REG_SQ_SHADER_TBA_LO', + 'SQ_HW_REG_SQ_SHADER_TMA_HI', 'SQ_HW_REG_SQ_SHADER_TMA_LO', + 'SQ_HW_REG_STATUS', 'SQ_HW_REG_TRAPSTS', 'SQ_IBUF_IB_DRET', + 'SQ_IBUF_IB_EMPTY_WAIT_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_GNT', + 'SQ_IBUF_IB_IDLE', 'SQ_IBUF_IB_INI_WAIT_DRET', + 'SQ_IBUF_IB_INI_WAIT_GNT', 'SQ_IBUF_IB_LE_4DW', + 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', 'SQ_IMAGE_ATOMIC_ADD', + 'SQ_IMAGE_ATOMIC_AND', 'SQ_IMAGE_ATOMIC_CMPSWAP', + 'SQ_IMAGE_ATOMIC_DEC', 'SQ_IMAGE_ATOMIC_INC', + 'SQ_IMAGE_ATOMIC_OR', 'SQ_IMAGE_ATOMIC_SMAX', + 'SQ_IMAGE_ATOMIC_SMIN', 'SQ_IMAGE_ATOMIC_SUB', + 'SQ_IMAGE_ATOMIC_SWAP', 'SQ_IMAGE_ATOMIC_UMAX', + 'SQ_IMAGE_ATOMIC_UMIN', 'SQ_IMAGE_ATOMIC_XOR', 'SQ_IMAGE_GATHER4', + 'SQ_IMAGE_GATHER4H', 'SQ_IMAGE_GATHER4H_PCK', + 'SQ_IMAGE_GATHER4_B', 'SQ_IMAGE_GATHER4_B_CL', + 'SQ_IMAGE_GATHER4_B_CL_O', 'SQ_IMAGE_GATHER4_B_O', + 'SQ_IMAGE_GATHER4_C', 'SQ_IMAGE_GATHER4_CL', + 'SQ_IMAGE_GATHER4_CL_O', 'SQ_IMAGE_GATHER4_C_B', + 'SQ_IMAGE_GATHER4_C_B_CL', 'SQ_IMAGE_GATHER4_C_B_CL_O', + 'SQ_IMAGE_GATHER4_C_B_O', 'SQ_IMAGE_GATHER4_C_CL', + 'SQ_IMAGE_GATHER4_C_CL_O', 'SQ_IMAGE_GATHER4_C_L', + 'SQ_IMAGE_GATHER4_C_LZ', 'SQ_IMAGE_GATHER4_C_LZ_O', + 'SQ_IMAGE_GATHER4_C_L_O', 'SQ_IMAGE_GATHER4_C_O', + 'SQ_IMAGE_GATHER4_L', 'SQ_IMAGE_GATHER4_LZ', + 'SQ_IMAGE_GATHER4_LZ_O', 'SQ_IMAGE_GATHER4_L_O', + 'SQ_IMAGE_GATHER4_O', 'SQ_IMAGE_GATHER8H_PCK', 'SQ_IMAGE_GET_LOD', + 'SQ_IMAGE_GET_RESINFO', 'SQ_IMAGE_LOAD', 'SQ_IMAGE_LOAD_MIP', + 'SQ_IMAGE_LOAD_MIP_PCK', 'SQ_IMAGE_LOAD_MIP_PCK_SGN', + 'SQ_IMAGE_LOAD_PCK', 'SQ_IMAGE_LOAD_PCK_SGN', 'SQ_IMAGE_RSRC256', + 'SQ_IMAGE_SAMPLE', 'SQ_IMAGE_SAMPLER', 'SQ_IMAGE_SAMPLE_B', + 'SQ_IMAGE_SAMPLE_B_CL', 'SQ_IMAGE_SAMPLE_B_CL_O', + 'SQ_IMAGE_SAMPLE_B_O', 'SQ_IMAGE_SAMPLE_C', 'SQ_IMAGE_SAMPLE_CD', + 'SQ_IMAGE_SAMPLE_CD_CL', 'SQ_IMAGE_SAMPLE_CD_CL_O', + 'SQ_IMAGE_SAMPLE_CD_O', 'SQ_IMAGE_SAMPLE_CL', + 'SQ_IMAGE_SAMPLE_CL_O', 'SQ_IMAGE_SAMPLE_C_B', + 'SQ_IMAGE_SAMPLE_C_B_CL', 'SQ_IMAGE_SAMPLE_C_B_CL_O', + 'SQ_IMAGE_SAMPLE_C_B_O', 'SQ_IMAGE_SAMPLE_C_CD', + 'SQ_IMAGE_SAMPLE_C_CD_CL', 'SQ_IMAGE_SAMPLE_C_CD_CL_O', + 'SQ_IMAGE_SAMPLE_C_CD_O', 'SQ_IMAGE_SAMPLE_C_CL', + 'SQ_IMAGE_SAMPLE_C_CL_O', 'SQ_IMAGE_SAMPLE_C_D', + 'SQ_IMAGE_SAMPLE_C_D_CL', 'SQ_IMAGE_SAMPLE_C_D_CL_O', + 'SQ_IMAGE_SAMPLE_C_D_O', 'SQ_IMAGE_SAMPLE_C_L', + 'SQ_IMAGE_SAMPLE_C_LZ', 'SQ_IMAGE_SAMPLE_C_LZ_O', + 'SQ_IMAGE_SAMPLE_C_L_O', 'SQ_IMAGE_SAMPLE_C_O', + 'SQ_IMAGE_SAMPLE_D', 'SQ_IMAGE_SAMPLE_D_CL', + 'SQ_IMAGE_SAMPLE_D_CL_O', 'SQ_IMAGE_SAMPLE_D_O', + 'SQ_IMAGE_SAMPLE_L', 'SQ_IMAGE_SAMPLE_LZ', 'SQ_IMAGE_SAMPLE_LZ_O', + 'SQ_IMAGE_SAMPLE_L_O', 'SQ_IMAGE_SAMPLE_O', 'SQ_IMAGE_STORE', + 'SQ_IMAGE_STORE_MIP', 'SQ_IMAGE_STORE_MIP_PCK', + 'SQ_IMAGE_STORE_PCK', 'SQ_IMG_FILTER_MODE_BLEND', + 'SQ_IMG_FILTER_MODE_MAX', 'SQ_IMG_FILTER_MODE_MIN', + 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', 'SQ_IND_CMD_CMD_DEBUG', + 'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL', + 'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT', + 'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SPI_PRIO', + 'SQ_IND_CMD_CMD_TRAP', 'SQ_IND_CMD_MODE', + 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', + 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', + 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', + 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', + 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST0', + 'SQ_INST_STR_IB_WAVE_SETVSKIP_ST1', 'SQ_INST_STR_ST', + 'SQ_INTERRUPT_WORD_ENCODING', 'SQ_INTERRUPT_WORD_ENCODING_AUTO', + 'SQ_INTERRUPT_WORD_ENCODING_ERROR', + 'SQ_INTERRUPT_WORD_ENCODING_INST', 'SQ_L1', 'SQ_L10', 'SQ_L11', + 'SQ_L12', 'SQ_L13', 'SQ_L14', 'SQ_L15', 'SQ_L2', 'SQ_L3', 'SQ_L4', + 'SQ_L5', 'SQ_L6', 'SQ_L7', 'SQ_L8', 'SQ_L9', + 'SQ_LB_CTR_SEL_ALU_CYCLES', 'SQ_LB_CTR_SEL_ALU_STALLS', + 'SQ_LB_CTR_SEL_DCACHE_STALLS', 'SQ_LB_CTR_SEL_ICACHE_STALLS', + 'SQ_LB_CTR_SEL_RESERVED0', 'SQ_LB_CTR_SEL_RESERVED1', + 'SQ_LB_CTR_SEL_RESERVED2', 'SQ_LB_CTR_SEL_RESERVED3', + 'SQ_LB_CTR_SEL_RESERVED4', 'SQ_LB_CTR_SEL_RESERVED5', + 'SQ_LB_CTR_SEL_RESERVED6', 'SQ_LB_CTR_SEL_SALU_CYCLES', + 'SQ_LB_CTR_SEL_SCALAR_STALLS', 'SQ_LB_CTR_SEL_SMEM_CYCLES', + 'SQ_LB_CTR_SEL_TEX_CYCLES', 'SQ_LB_CTR_SEL_TEX_STALLS', + 'SQ_LB_CTR_SEL_VALUES', 'SQ_LE', 'SQ_LG', 'SQ_LT', 'SQ_M0', + 'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', + 'SQ_MSG_EARLY_PRIM_DEALLOC', 'SQ_MSG_GS', 'SQ_MSG_GS_ALLOC_REQ', + 'SQ_MSG_GS_DONE', 'SQ_MSG_HALT_WAVES', 'SQ_MSG_INTERRUPT', + 'SQ_MSG_ORDERED_PS_DONE', 'SQ_MSG_SAVEWAVE', + 'SQ_MSG_STALL_WAVE_GEN', 'SQ_MSG_SYSMSG', 'SQ_NE', 'SQ_NEQ', + 'SQ_NGE', 'SQ_NGT', 'SQ_NLE', 'SQ_NLG', 'SQ_NLT', 'SQ_NON_EVENT', + 'SQ_NUM_ATTR', 'SQ_NUM_SGPR', 'SQ_NUM_TTMP', 'SQ_NUM_VGPR', + 'SQ_O', 'SQ_OMOD_D2', 'SQ_OMOD_M2', 'SQ_OMOD_M4', 'SQ_OMOD_OFF', + 'SQ_PARAM_P0', 'SQ_PARAM_P10', 'SQ_PARAM_P20', 'SQ_PERF_SEL', + 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_ACCUM_PREV_HIRES', + 'SQ_PERF_SEL_ACTIVE_INST_ANY', 'SQ_PERF_SEL_ACTIVE_INST_EXP_GDS', + 'SQ_PERF_SEL_ACTIVE_INST_FLAT', 'SQ_PERF_SEL_ACTIVE_INST_LDS', + 'SQ_PERF_SEL_ACTIVE_INST_MISC', 'SQ_PERF_SEL_ACTIVE_INST_SCA', + 'SQ_PERF_SEL_ACTIVE_INST_VALU', 'SQ_PERF_SEL_ACTIVE_INST_VMEM', + 'SQ_PERF_SEL_ATC_INSTS_SMEM', 'SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY', + 'SQ_PERF_SEL_ATC_INSTS_VMEM', 'SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY', + 'SQ_PERF_SEL_ATC_INST_LEVEL_SMEM', + 'SQ_PERF_SEL_ATC_INST_LEVEL_VMEM', 'SQ_PERF_SEL_ATC_XNACK_ALL', + 'SQ_PERF_SEL_ATC_XNACK_FIFO_FULL', 'SQ_PERF_SEL_ATC_XNACK_FIRST', + 'SQ_PERF_SEL_BUSY_CU_CYCLES', 'SQ_PERF_SEL_BUSY_CYCLES', + 'SQ_PERF_SEL_CBRANCH_FORK', 'SQ_PERF_SEL_CBRANCH_FORK_SPLIT', + 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', + 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', + 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 'SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT', 'SQ_PERF_SEL_IFETCH', + 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_XNACK', + 'SQ_PERF_SEL_INSTS', 'SQ_PERF_SEL_INSTS_BRANCH', + 'SQ_PERF_SEL_INSTS_EXP', 'SQ_PERF_SEL_INSTS_EXP_GDS', + 'SQ_PERF_SEL_INSTS_FLAT', 'SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY', + 'SQ_PERF_SEL_INSTS_FLAT_REPLAY', 'SQ_PERF_SEL_INSTS_GDS', + 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_SALU', + 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', + 'SQ_PERF_SEL_INSTS_SMEM_NORM', + 'SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY', + 'SQ_PERF_SEL_INSTS_SMEM_REPLAY', 'SQ_PERF_SEL_INSTS_VALU', + 'SQ_PERF_SEL_INSTS_VMEM', 'SQ_PERF_SEL_INSTS_VMEM_RD', + 'SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY', + 'SQ_PERF_SEL_INSTS_VMEM_REPLAY', 'SQ_PERF_SEL_INSTS_VMEM_WR', + 'SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY', 'SQ_PERF_SEL_INSTS_VSKIPPED', + 'SQ_PERF_SEL_INST_CYCLES_EXP', 'SQ_PERF_SEL_INST_CYCLES_GDS', + 'SQ_PERF_SEL_INST_CYCLES_SALU', 'SQ_PERF_SEL_INST_CYCLES_SMEM', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_CMD', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_DATA', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_RD', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_WR', 'SQ_PERF_SEL_INST_LEVEL_EXP', + 'SQ_PERF_SEL_INST_LEVEL_GDS', 'SQ_PERF_SEL_INST_LEVEL_LDS', + 'SQ_PERF_SEL_INST_LEVEL_SMEM', 'SQ_PERF_SEL_INST_LEVEL_VMEM', + 'SQ_PERF_SEL_ITEMS', 'SQ_PERF_SEL_LDS_ADDR_CONFLICT', + 'SQ_PERF_SEL_LDS_ATOMIC_RETURN', 'SQ_PERF_SEL_LDS_BANK_CONFLICT', + 'SQ_PERF_SEL_LDS_CMD_FIFO_FULL', 'SQ_PERF_SEL_LDS_DATA_FIFO_FULL', + 'SQ_PERF_SEL_LDS_IDX_ACTIVE', 'SQ_PERF_SEL_LDS_MEM_VIOLATIONS', + 'SQ_PERF_SEL_LDS_SRC_CD_CONFLICT', + 'SQ_PERF_SEL_LDS_UNALIGNED_STALL', 'SQ_PERF_SEL_LEVEL_WAVES', + 'SQ_PERF_SEL_LEVEL_WAVES_CU', 'SQ_PERF_SEL_MSG_CNTR', + 'SQ_PERF_SEL_MSG_GSCNT', 'SQ_PERF_SEL_MSG_INTERRUPT', + 'SQ_PERF_SEL_MSG_PERF', 'SQ_PERF_SEL_NONE', + 'SQ_PERF_SEL_POWER_ALU_BUSY', 'SQ_PERF_SEL_POWER_GPR_RD', + 'SQ_PERF_SEL_POWER_GPR_WR', 'SQ_PERF_SEL_POWER_LDS_BUSY', + 'SQ_PERF_SEL_POWER_TEX_BUSY', 'SQ_PERF_SEL_POWER_VALU', + 'SQ_PERF_SEL_POWER_VALU0', 'SQ_PERF_SEL_POWER_VALU1', + 'SQ_PERF_SEL_POWER_VALU2', 'SQ_PERF_SEL_PT_POWER_STALL', + 'SQ_PERF_SEL_QUADS', 'SQ_PERF_SEL_SRC_CD_BUSY', + 'SQ_PERF_SEL_SURF_SYNCS', 'SQ_PERF_SEL_THREAD_CYCLES_VALU', + 'SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX', 'SQ_PERF_SEL_TLB_SHOOTDOWN', + 'SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES', + 'SQ_PERF_SEL_TTRACE_INFLIGHT_REQS', 'SQ_PERF_SEL_TTRACE_REQS', + 'SQ_PERF_SEL_TTRACE_STALL', 'SQ_PERF_SEL_USER0', + 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', + 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', + 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', + 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', + 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', + 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', + 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', + 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', + 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', + 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', + 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', + 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', + 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', + 'SQ_PERF_SEL_UTCL1_LFIFO_FULL', + 'SQ_PERF_SEL_UTCL1_PERMISSION_MISS', 'SQ_PERF_SEL_UTCL1_REQUEST', + 'SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 'SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 'SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 'SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 'SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 'SQ_PERF_SEL_UTCL1_TRANSLATION_MISS', + 'SQ_PERF_SEL_VALU_DEP_STALL', 'SQ_PERF_SEL_VALU_LDS_DIRECT_RD', + 'SQ_PERF_SEL_VALU_LDS_INTERP_OP', + 'SQ_PERF_SEL_VALU_SRC_C_CONFLICT', 'SQ_PERF_SEL_VALU_STARVE', + 'SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY', + 'SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT', + 'SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT', + 'SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL', 'SQ_PERF_SEL_WAIT_ANY', + 'SQ_PERF_SEL_WAIT_BARRIER', 'SQ_PERF_SEL_WAIT_CNT_ANY', + 'SQ_PERF_SEL_WAIT_CNT_EXP', 'SQ_PERF_SEL_WAIT_CNT_LGKM', + 'SQ_PERF_SEL_WAIT_CNT_VM', 'SQ_PERF_SEL_WAIT_EXP_ALLOC', + 'SQ_PERF_SEL_WAIT_IFETCH', 'SQ_PERF_SEL_WAIT_INST_ANY', + 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', 'SQ_PERF_SEL_WAIT_INST_FLAT', + 'SQ_PERF_SEL_WAIT_INST_LDS', 'SQ_PERF_SEL_WAIT_INST_MISC', + 'SQ_PERF_SEL_WAIT_INST_SCA', 'SQ_PERF_SEL_WAIT_INST_VALU', + 'SQ_PERF_SEL_WAIT_INST_VMEM', 'SQ_PERF_SEL_WAIT_OTHER', + 'SQ_PERF_SEL_WAIT_SLEEP', 'SQ_PERF_SEL_WAIT_SLEEP_XNACK', + 'SQ_PERF_SEL_WAIT_TTRACE', 'SQ_PERF_SEL_WAVES', + 'SQ_PERF_SEL_WAVES_CU', 'SQ_PERF_SEL_WAVES_EQ_64', + 'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32', + 'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64', + 'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED', + 'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY', 'SQ_R1', + 'SQ_R10', 'SQ_R11', 'SQ_R12', 'SQ_R13', 'SQ_R14', 'SQ_R15', + 'SQ_R2', 'SQ_R3', 'SQ_R4', 'SQ_R5', 'SQ_R6', 'SQ_R7', 'SQ_R8', + 'SQ_R9', 'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE', + 'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY', + 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1', + 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE', + 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2', + 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D', + 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY', + 'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY', + 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0', + 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3', + 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6', + 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SCRATCH', + 'SQ_SCRATCH_LOAD_DWORD', 'SQ_SCRATCH_LOAD_DWORDX2', + 'SQ_SCRATCH_LOAD_DWORDX3', 'SQ_SCRATCH_LOAD_DWORDX4', + 'SQ_SCRATCH_LOAD_SBYTE', 'SQ_SCRATCH_LOAD_SSHORT', + 'SQ_SCRATCH_LOAD_UBYTE', 'SQ_SCRATCH_LOAD_USHORT', + 'SQ_SCRATCH_STORE_BYTE', 'SQ_SCRATCH_STORE_DWORD', + 'SQ_SCRATCH_STORE_DWORDX2', 'SQ_SCRATCH_STORE_DWORDX3', + 'SQ_SCRATCH_STORE_DWORDX4', 'SQ_SCRATCH_STORE_SHORT', + 'SQ_SDWA_BYTE_0', 'SQ_SDWA_BYTE_1', 'SQ_SDWA_BYTE_2', + 'SQ_SDWA_BYTE_3', 'SQ_SDWA_DWORD', 'SQ_SDWA_UNUSED_PAD', + 'SQ_SDWA_UNUSED_PRESERVE', 'SQ_SDWA_UNUSED_SEXT', + 'SQ_SDWA_WORD_0', 'SQ_SDWA_WORD_1', 'SQ_SEL_0', 'SQ_SEL_1', + 'SQ_SEL_RESERVED_0', 'SQ_SEL_RESERVED_1', 'SQ_SEL_W', 'SQ_SEL_X', + 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', 'SQ_SENDMSG_GSOP_SHIFT', + 'SQ_SENDMSG_GSOP_SIZE', 'SQ_SENDMSG_MSG_SHIFT', + 'SQ_SENDMSG_MSG_SIZE', 'SQ_SENDMSG_STREAMID_SHIFT', + 'SQ_SENDMSG_STREAMID_SIZE', 'SQ_SENDMSG_SYSTEM_SHIFT', + 'SQ_SENDMSG_SYSTEM_SIZE', 'SQ_SGPR0', 'SQ_SRC_0', 'SQ_SRC_0_5', + 'SQ_SRC_1', 'SQ_SRC_10_INT', 'SQ_SRC_11_INT', 'SQ_SRC_12_INT', + 'SQ_SRC_13_INT', 'SQ_SRC_14_INT', 'SQ_SRC_15_INT', + 'SQ_SRC_16_INT', 'SQ_SRC_17_INT', 'SQ_SRC_18_INT', + 'SQ_SRC_19_INT', 'SQ_SRC_1_INT', 'SQ_SRC_2', 'SQ_SRC_20_INT', + 'SQ_SRC_21_INT', 'SQ_SRC_22_INT', 'SQ_SRC_23_INT', + 'SQ_SRC_24_INT', 'SQ_SRC_25_INT', 'SQ_SRC_26_INT', + 'SQ_SRC_27_INT', 'SQ_SRC_28_INT', 'SQ_SRC_29_INT', 'SQ_SRC_2_INT', + 'SQ_SRC_30_INT', 'SQ_SRC_31_INT', 'SQ_SRC_32_INT', + 'SQ_SRC_33_INT', 'SQ_SRC_34_INT', 'SQ_SRC_35_INT', + 'SQ_SRC_36_INT', 'SQ_SRC_37_INT', 'SQ_SRC_38_INT', + 'SQ_SRC_39_INT', 'SQ_SRC_3_INT', 'SQ_SRC_4', 'SQ_SRC_40_INT', + 'SQ_SRC_41_INT', 'SQ_SRC_42_INT', 'SQ_SRC_43_INT', + 'SQ_SRC_44_INT', 'SQ_SRC_45_INT', 'SQ_SRC_46_INT', + 'SQ_SRC_47_INT', 'SQ_SRC_48_INT', 'SQ_SRC_49_INT', 'SQ_SRC_4_INT', + 'SQ_SRC_50_INT', 'SQ_SRC_51_INT', 'SQ_SRC_52_INT', + 'SQ_SRC_53_INT', 'SQ_SRC_54_INT', 'SQ_SRC_55_INT', + 'SQ_SRC_56_INT', 'SQ_SRC_57_INT', 'SQ_SRC_58_INT', + 'SQ_SRC_59_INT', 'SQ_SRC_5_INT', 'SQ_SRC_60_INT', 'SQ_SRC_61_INT', + 'SQ_SRC_62_INT', 'SQ_SRC_63_INT', 'SQ_SRC_64_INT', 'SQ_SRC_6_INT', + 'SQ_SRC_7_INT', 'SQ_SRC_8_INT', 'SQ_SRC_9_INT', 'SQ_SRC_DPP', + 'SQ_SRC_EXECZ', 'SQ_SRC_INV_2PI', 'SQ_SRC_LDS_DIRECT', + 'SQ_SRC_LITERAL', 'SQ_SRC_M_0_5', 'SQ_SRC_M_1', 'SQ_SRC_M_10_INT', + 'SQ_SRC_M_11_INT', 'SQ_SRC_M_12_INT', 'SQ_SRC_M_13_INT', + 'SQ_SRC_M_14_INT', 'SQ_SRC_M_15_INT', 'SQ_SRC_M_16_INT', + 'SQ_SRC_M_1_INT', 'SQ_SRC_M_2', 'SQ_SRC_M_2_INT', + 'SQ_SRC_M_3_INT', 'SQ_SRC_M_4', 'SQ_SRC_M_4_INT', + 'SQ_SRC_M_5_INT', 'SQ_SRC_M_6_INT', 'SQ_SRC_M_7_INT', + 'SQ_SRC_M_8_INT', 'SQ_SRC_M_9_INT', 'SQ_SRC_POPS_EXITING_WAVE_ID', + 'SQ_SRC_PRIVATE_BASE', 'SQ_SRC_PRIVATE_LIMIT', 'SQ_SRC_SCC', + 'SQ_SRC_SDWA', 'SQ_SRC_SHARED_BASE', 'SQ_SRC_SHARED_LIMIT', + 'SQ_SRC_VCCZ', 'SQ_SRC_VGPR0', 'SQ_SRC_VGPR_BIT', + 'SQ_SYSMSG_OP_ECC_ERR_INTERRUPT', 'SQ_SYSMSG_OP_HOST_TRAP_ACK', + 'SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT', + 'SQ_SYSMSG_OP_MEMVIOL_INTERRUPT', 'SQ_SYSMSG_OP_REG_RD', + 'SQ_SYSMSG_OP_TTRACE_PC', 'SQ_S_ABSDIFF_I32', 'SQ_S_ABS_I32', + 'SQ_S_ADDC_U32', 'SQ_S_ADDK_I32', 'SQ_S_ADD_I32', 'SQ_S_ADD_U32', + 'SQ_S_ANDN1_SAVEEXEC_B64', 'SQ_S_ANDN1_WREXEC_B64', + 'SQ_S_ANDN2_B32', 'SQ_S_ANDN2_B64', 'SQ_S_ANDN2_SAVEEXEC_B64', + 'SQ_S_ANDN2_WREXEC_B64', 'SQ_S_AND_B32', 'SQ_S_AND_B64', + 'SQ_S_AND_SAVEEXEC_B64', 'SQ_S_ASHR_I32', 'SQ_S_ASHR_I64', + 'SQ_S_ATC_PROBE', 'SQ_S_ATC_PROBE_BUFFER', 'SQ_S_ATOMIC_ADD', + 'SQ_S_ATOMIC_ADD_X2', 'SQ_S_ATOMIC_AND', 'SQ_S_ATOMIC_AND_X2', + 'SQ_S_ATOMIC_CMPSWAP', 'SQ_S_ATOMIC_CMPSWAP_X2', + 'SQ_S_ATOMIC_DEC', 'SQ_S_ATOMIC_DEC_X2', 'SQ_S_ATOMIC_INC', + 'SQ_S_ATOMIC_INC_X2', 'SQ_S_ATOMIC_OR', 'SQ_S_ATOMIC_OR_X2', + 'SQ_S_ATOMIC_SMAX', 'SQ_S_ATOMIC_SMAX_X2', 'SQ_S_ATOMIC_SMIN', + 'SQ_S_ATOMIC_SMIN_X2', 'SQ_S_ATOMIC_SUB', 'SQ_S_ATOMIC_SUB_X2', + 'SQ_S_ATOMIC_SWAP', 'SQ_S_ATOMIC_SWAP_X2', 'SQ_S_ATOMIC_UMAX', + 'SQ_S_ATOMIC_UMAX_X2', 'SQ_S_ATOMIC_UMIN', 'SQ_S_ATOMIC_UMIN_X2', + 'SQ_S_ATOMIC_XOR', 'SQ_S_ATOMIC_XOR_X2', 'SQ_S_BARRIER', + 'SQ_S_BCNT0_I32_B32', 'SQ_S_BCNT0_I32_B64', 'SQ_S_BCNT1_I32_B32', + 'SQ_S_BCNT1_I32_B64', 'SQ_S_BFE_I32', 'SQ_S_BFE_I64', + 'SQ_S_BFE_U32', 'SQ_S_BFE_U64', 'SQ_S_BFM_B32', 'SQ_S_BFM_B64', + 'SQ_S_BITCMP0_B32', 'SQ_S_BITCMP0_B64', 'SQ_S_BITCMP1_B32', + 'SQ_S_BITCMP1_B64', 'SQ_S_BITREPLICATE_B64_B32', + 'SQ_S_BITSET0_B32', 'SQ_S_BITSET0_B64', 'SQ_S_BITSET1_B32', + 'SQ_S_BITSET1_B64', 'SQ_S_BRANCH', 'SQ_S_BREV_B32', + 'SQ_S_BREV_B64', 'SQ_S_BUFFER_ATOMIC_ADD', + 'SQ_S_BUFFER_ATOMIC_ADD_X2', 'SQ_S_BUFFER_ATOMIC_AND', + 'SQ_S_BUFFER_ATOMIC_AND_X2', 'SQ_S_BUFFER_ATOMIC_CMPSWAP', + 'SQ_S_BUFFER_ATOMIC_CMPSWAP_X2', 'SQ_S_BUFFER_ATOMIC_DEC', + 'SQ_S_BUFFER_ATOMIC_DEC_X2', 'SQ_S_BUFFER_ATOMIC_INC', + 'SQ_S_BUFFER_ATOMIC_INC_X2', 'SQ_S_BUFFER_ATOMIC_OR', + 'SQ_S_BUFFER_ATOMIC_OR_X2', 'SQ_S_BUFFER_ATOMIC_SMAX', + 'SQ_S_BUFFER_ATOMIC_SMAX_X2', 'SQ_S_BUFFER_ATOMIC_SMIN', + 'SQ_S_BUFFER_ATOMIC_SMIN_X2', 'SQ_S_BUFFER_ATOMIC_SUB', + 'SQ_S_BUFFER_ATOMIC_SUB_X2', 'SQ_S_BUFFER_ATOMIC_SWAP', + 'SQ_S_BUFFER_ATOMIC_SWAP_X2', 'SQ_S_BUFFER_ATOMIC_UMAX', + 'SQ_S_BUFFER_ATOMIC_UMAX_X2', 'SQ_S_BUFFER_ATOMIC_UMIN', + 'SQ_S_BUFFER_ATOMIC_UMIN_X2', 'SQ_S_BUFFER_ATOMIC_XOR', + 'SQ_S_BUFFER_ATOMIC_XOR_X2', 'SQ_S_BUFFER_LOAD_DWORD', + 'SQ_S_BUFFER_LOAD_DWORDX16', 'SQ_S_BUFFER_LOAD_DWORDX2', + 'SQ_S_BUFFER_LOAD_DWORDX4', 'SQ_S_BUFFER_LOAD_DWORDX8', + 'SQ_S_BUFFER_STORE_DWORD', 'SQ_S_BUFFER_STORE_DWORDX2', + 'SQ_S_BUFFER_STORE_DWORDX4', 'SQ_S_CALL_B64', + 'SQ_S_CBRANCH_CDBGSYS', 'SQ_S_CBRANCH_CDBGSYS_AND_USER', + 'SQ_S_CBRANCH_CDBGSYS_OR_USER', 'SQ_S_CBRANCH_CDBGUSER', + 'SQ_S_CBRANCH_EXECNZ', 'SQ_S_CBRANCH_EXECZ', + 'SQ_S_CBRANCH_G_FORK', 'SQ_S_CBRANCH_I_FORK', 'SQ_S_CBRANCH_JOIN', + 'SQ_S_CBRANCH_SCC0', 'SQ_S_CBRANCH_SCC1', 'SQ_S_CBRANCH_VCCNZ', + 'SQ_S_CBRANCH_VCCZ', 'SQ_S_CMOVK_I32', 'SQ_S_CMOV_B32', + 'SQ_S_CMOV_B64', 'SQ_S_CMPK_EQ_I32', 'SQ_S_CMPK_EQ_U32', + 'SQ_S_CMPK_GE_I32', 'SQ_S_CMPK_GE_U32', 'SQ_S_CMPK_GT_I32', + 'SQ_S_CMPK_GT_U32', 'SQ_S_CMPK_LE_I32', 'SQ_S_CMPK_LE_U32', + 'SQ_S_CMPK_LG_I32', 'SQ_S_CMPK_LG_U32', 'SQ_S_CMPK_LT_I32', + 'SQ_S_CMPK_LT_U32', 'SQ_S_CMP_EQ_I32', 'SQ_S_CMP_EQ_U32', + 'SQ_S_CMP_EQ_U64', 'SQ_S_CMP_GE_I32', 'SQ_S_CMP_GE_U32', + 'SQ_S_CMP_GT_I32', 'SQ_S_CMP_GT_U32', 'SQ_S_CMP_LE_I32', + 'SQ_S_CMP_LE_U32', 'SQ_S_CMP_LG_I32', 'SQ_S_CMP_LG_U32', + 'SQ_S_CMP_LG_U64', 'SQ_S_CMP_LT_I32', 'SQ_S_CMP_LT_U32', + 'SQ_S_CSELECT_B32', 'SQ_S_CSELECT_B64', 'SQ_S_DCACHE_INV', + 'SQ_S_DCACHE_INV_VOL', 'SQ_S_DCACHE_WB', 'SQ_S_DCACHE_WB_VOL', + 'SQ_S_DECPERFLEVEL', 'SQ_S_ENDPGM', 'SQ_S_ENDPGM_ORDERED_PS_DONE', + 'SQ_S_ENDPGM_SAVED', 'SQ_S_FF0_I32_B32', 'SQ_S_FF0_I32_B64', + 'SQ_S_FF1_I32_B32', 'SQ_S_FF1_I32_B64', 'SQ_S_FLBIT_I32', + 'SQ_S_FLBIT_I32_B32', 'SQ_S_FLBIT_I32_B64', 'SQ_S_FLBIT_I32_I64', + 'SQ_S_GETPC_B64', 'SQ_S_GETREG_B32', 'SQ_S_GETREG_REGRD_B32', + 'SQ_S_ICACHE_INV', 'SQ_S_INCPERFLEVEL', 'SQ_S_LOAD_DWORD', + 'SQ_S_LOAD_DWORDX16', 'SQ_S_LOAD_DWORDX2', 'SQ_S_LOAD_DWORDX4', + 'SQ_S_LOAD_DWORDX8', 'SQ_S_LSHL1_ADD_U32', 'SQ_S_LSHL2_ADD_U32', + 'SQ_S_LSHL3_ADD_U32', 'SQ_S_LSHL4_ADD_U32', 'SQ_S_LSHL_B32', + 'SQ_S_LSHL_B64', 'SQ_S_LSHR_B32', 'SQ_S_LSHR_B64', 'SQ_S_MAX_I32', + 'SQ_S_MAX_U32', 'SQ_S_MEMREALTIME', 'SQ_S_MEMTIME', + 'SQ_S_MIN_I32', 'SQ_S_MIN_U32', 'SQ_S_MOVK_I32', + 'SQ_S_MOVRELD_B32', 'SQ_S_MOVRELD_B64', 'SQ_S_MOVRELS_B32', + 'SQ_S_MOVRELS_B64', 'SQ_S_MOV_B32', 'SQ_S_MOV_B64', + 'SQ_S_MOV_FED_B32', 'SQ_S_MOV_REGRD_B32', 'SQ_S_MULK_I32', + 'SQ_S_MUL_HI_I32', 'SQ_S_MUL_HI_U32', 'SQ_S_MUL_I32', + 'SQ_S_NAND_B32', 'SQ_S_NAND_B64', 'SQ_S_NAND_SAVEEXEC_B64', + 'SQ_S_NOP', 'SQ_S_NOR_B32', 'SQ_S_NOR_B64', + 'SQ_S_NOR_SAVEEXEC_B64', 'SQ_S_NOT_B32', 'SQ_S_NOT_B64', + 'SQ_S_ORN1_SAVEEXEC_B64', 'SQ_S_ORN2_B32', 'SQ_S_ORN2_B64', + 'SQ_S_ORN2_SAVEEXEC_B64', 'SQ_S_OR_B32', 'SQ_S_OR_B64', + 'SQ_S_OR_SAVEEXEC_B64', 'SQ_S_PACK_HH_B32_B16', + 'SQ_S_PACK_LH_B32_B16', 'SQ_S_PACK_LL_B32_B16', + 'SQ_S_QUADMASK_B32', 'SQ_S_QUADMASK_B64', 'SQ_S_RFE_B64', + 'SQ_S_RFE_RESTORE_B64', 'SQ_S_SCRATCH_LOAD_DWORD', + 'SQ_S_SCRATCH_LOAD_DWORDX2', 'SQ_S_SCRATCH_LOAD_DWORDX4', + 'SQ_S_SCRATCH_STORE_DWORD', 'SQ_S_SCRATCH_STORE_DWORDX2', + 'SQ_S_SCRATCH_STORE_DWORDX4', 'SQ_S_SENDMSG', 'SQ_S_SENDMSGHALT', + 'SQ_S_SETHALT', 'SQ_S_SETKILL', 'SQ_S_SETPC_B64', 'SQ_S_SETPRIO', + 'SQ_S_SETREG_B32', 'SQ_S_SETREG_IMM32_B32', 'SQ_S_SETVSKIP', + 'SQ_S_SET_GPR_IDX_IDX', 'SQ_S_SET_GPR_IDX_MODE', + 'SQ_S_SET_GPR_IDX_OFF', 'SQ_S_SET_GPR_IDX_ON', + 'SQ_S_SEXT_I32_I16', 'SQ_S_SEXT_I32_I8', 'SQ_S_SLEEP', + 'SQ_S_STORE_DWORD', 'SQ_S_STORE_DWORDX2', 'SQ_S_STORE_DWORDX4', + 'SQ_S_SUBB_U32', 'SQ_S_SUB_I32', 'SQ_S_SUB_U32', + 'SQ_S_SWAPPC_B64', 'SQ_S_TRAP', 'SQ_S_TTRACEDATA', 'SQ_S_WAITCNT', + 'SQ_S_WAKEUP', 'SQ_S_WQM_B32', 'SQ_S_WQM_B64', 'SQ_S_XNOR_B32', + 'SQ_S_XNOR_B64', 'SQ_S_XNOR_SAVEEXEC_B64', 'SQ_S_XOR_B32', + 'SQ_S_XOR_B64', 'SQ_S_XOR_SAVEEXEC_B64', 'SQ_T', + 'SQ_TBUFFER_LOAD_FORMAT_D16_X', 'SQ_TBUFFER_LOAD_FORMAT_D16_XY', + 'SQ_TBUFFER_LOAD_FORMAT_D16_XYZ', + 'SQ_TBUFFER_LOAD_FORMAT_D16_XYZW', 'SQ_TBUFFER_LOAD_FORMAT_X', + 'SQ_TBUFFER_LOAD_FORMAT_XY', 'SQ_TBUFFER_LOAD_FORMAT_XYZ', + 'SQ_TBUFFER_LOAD_FORMAT_XYZW', 'SQ_TBUFFER_STORE_FORMAT_D16_X', + 'SQ_TBUFFER_STORE_FORMAT_D16_XY', + 'SQ_TBUFFER_STORE_FORMAT_D16_XYZ', + 'SQ_TBUFFER_STORE_FORMAT_D16_XYZW', 'SQ_TBUFFER_STORE_FORMAT_X', + 'SQ_TBUFFER_STORE_FORMAT_XY', 'SQ_TBUFFER_STORE_FORMAT_XYZ', + 'SQ_TBUFFER_STORE_FORMAT_XYZW', 'SQ_TEX_ANISO_RATIO', + 'SQ_TEX_ANISO_RATIO_1', 'SQ_TEX_ANISO_RATIO_16', + 'SQ_TEX_ANISO_RATIO_2', 'SQ_TEX_ANISO_RATIO_4', + 'SQ_TEX_ANISO_RATIO_8', 'SQ_TEX_BORDER_COLOR', + 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', + 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', + 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 'SQ_TEX_DEPTH_COMPARE_GREATER', + 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', + 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', + 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', + 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', + 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', + 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', + 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', + 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', + 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', + 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', + 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', + 'SQ_THREAD_TRACE_CAPTURE_MODE', + 'SQ_THREAD_TRACE_CAPTURE_MODE_ALL', + 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT', + 'SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL', + 'SQ_THREAD_TRACE_INST_TYPE', + 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL', + 'SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS', + 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS', + 'SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX', + 'SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT', + 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD', + 'SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY', + 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR', + 'SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY', + 'SQ_THREAD_TRACE_INST_TYPE_JUMP', 'SQ_THREAD_TRACE_INST_TYPE_LDS', + 'SQ_THREAD_TRACE_INST_TYPE_NEXT', + 'SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG', + 'SQ_THREAD_TRACE_INST_TYPE_PC', + 'SQ_THREAD_TRACE_INST_TYPE_SALU_32', + 'SQ_THREAD_TRACE_INST_TYPE_SALU_64', + 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD', + 'SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY', + 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR', + 'SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY', + 'SQ_THREAD_TRACE_INST_TYPE_VALU_32', + 'SQ_THREAD_TRACE_INST_TYPE_VALU_64', + 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD', + 'SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY', + 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR', + 'SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY', + 'SQ_THREAD_TRACE_ISSUE', 'SQ_THREAD_TRACE_ISSUE_IMMED', + 'SQ_THREAD_TRACE_ISSUE_INST', 'SQ_THREAD_TRACE_ISSUE_MASK', + 'SQ_THREAD_TRACE_ISSUE_MASK_ALL', + 'SQ_THREAD_TRACE_ISSUE_MASK_IMMED', + 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED', + 'SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED', + 'SQ_THREAD_TRACE_ISSUE_NULL', 'SQ_THREAD_TRACE_ISSUE_STALL', + 'SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST', + 'SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX', + 'SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN', + 'SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC', + 'SQ_THREAD_TRACE_MISC_TOKEN_TIME', + 'SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET', + 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN', + 'SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END', + 'SQ_THREAD_TRACE_MISC_TOKEN_TYPE', 'SQ_THREAD_TRACE_MODE_OFF', + 'SQ_THREAD_TRACE_MODE_ON', 'SQ_THREAD_TRACE_MODE_SEL', + 'SQ_THREAD_TRACE_REG_OP', 'SQ_THREAD_TRACE_REG_OP_READ', + 'SQ_THREAD_TRACE_REG_OP_WRITE', 'SQ_THREAD_TRACE_REG_TYPE', + 'SQ_THREAD_TRACE_REG_TYPE_DISPATCH', + 'SQ_THREAD_TRACE_REG_TYPE_DRAW', 'SQ_THREAD_TRACE_REG_TYPE_EVENT', + 'SQ_THREAD_TRACE_REG_TYPE_GFXDEC', + 'SQ_THREAD_TRACE_REG_TYPE_MARKER', + 'SQ_THREAD_TRACE_REG_TYPE_OTHER', + 'SQ_THREAD_TRACE_REG_TYPE_SHDEC', + 'SQ_THREAD_TRACE_REG_TYPE_USERDATA', 'SQ_THREAD_TRACE_TIME_UNIT', + 'SQ_THREAD_TRACE_TOKEN_EVENT', 'SQ_THREAD_TRACE_TOKEN_EVENT_CS', + 'SQ_THREAD_TRACE_TOKEN_EVENT_GFX1', 'SQ_THREAD_TRACE_TOKEN_INST', + 'SQ_THREAD_TRACE_TOKEN_INST_PC', + 'SQ_THREAD_TRACE_TOKEN_INST_USERDATA', + 'SQ_THREAD_TRACE_TOKEN_ISSUE', 'SQ_THREAD_TRACE_TOKEN_MISC', + 'SQ_THREAD_TRACE_TOKEN_PERF', 'SQ_THREAD_TRACE_TOKEN_REG', + 'SQ_THREAD_TRACE_TOKEN_REG_CS', + 'SQ_THREAD_TRACE_TOKEN_REG_CSPRIV', + 'SQ_THREAD_TRACE_TOKEN_TIMESTAMP', 'SQ_THREAD_TRACE_TOKEN_TYPE', + 'SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC', + 'SQ_THREAD_TRACE_TOKEN_WAVE_END', + 'SQ_THREAD_TRACE_TOKEN_WAVE_START', 'SQ_THREAD_TRACE_VM_ID_MASK', + 'SQ_THREAD_TRACE_VM_ID_MASK_ALL', + 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE', + 'SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL', + 'SQ_THREAD_TRACE_WAVE_MASK', 'SQ_THREAD_TRACE_WAVE_MASK_ALL', + 'SQ_THREAD_TRACE_WAVE_MASK_NONE', + 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX', + 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE', + 'SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC', 'SQ_TRU', + 'SQ_TTMP0', 'SQ_TTMP1', 'SQ_TTMP10', 'SQ_TTMP11', 'SQ_TTMP12', + 'SQ_TTMP13', 'SQ_TTMP14', 'SQ_TTMP15', 'SQ_TTMP2', 'SQ_TTMP3', + 'SQ_TTMP4', 'SQ_TTMP5', 'SQ_TTMP6', 'SQ_TTMP7', 'SQ_TTMP8', + 'SQ_TTMP9', 'SQ_U', 'SQ_VCC_ALL', 'SQ_VCC_HI', 'SQ_VCC_LO', + 'SQ_VGPR0', 'SQ_V_ADD3_U32', 'SQ_V_ADDC_CO_U32', + 'SQ_V_ADD_CO_U32', 'SQ_V_ADD_F16', 'SQ_V_ADD_F32', 'SQ_V_ADD_F64', + 'SQ_V_ADD_I16', 'SQ_V_ADD_I32', 'SQ_V_ADD_LSHL_U32', + 'SQ_V_ADD_U16', 'SQ_V_ADD_U32', 'SQ_V_ALIGNBIT_B32', + 'SQ_V_ALIGNBYTE_B32', 'SQ_V_AND_B32', 'SQ_V_AND_OR_B32', + 'SQ_V_ASHRREV_I16', 'SQ_V_ASHRREV_I32', 'SQ_V_ASHRREV_I64', + 'SQ_V_BCNT_U32_B32', 'SQ_V_BFE_I32', 'SQ_V_BFE_U32', + 'SQ_V_BFI_B32', 'SQ_V_BFM_B32', 'SQ_V_BFREV_B32', 'SQ_V_CEIL_F16', + 'SQ_V_CEIL_F32', 'SQ_V_CEIL_F64', 'SQ_V_CLREXCP', + 'SQ_V_CMPX_CLASS_F16', 'SQ_V_CMPX_CLASS_F32', + 'SQ_V_CMPX_CLASS_F64', 'SQ_V_CMPX_EQ_F16', 'SQ_V_CMPX_EQ_F32', + 'SQ_V_CMPX_EQ_F64', 'SQ_V_CMPX_EQ_I16', 'SQ_V_CMPX_EQ_I32', + 'SQ_V_CMPX_EQ_I64', 'SQ_V_CMPX_EQ_U16', 'SQ_V_CMPX_EQ_U32', + 'SQ_V_CMPX_EQ_U64', 'SQ_V_CMPX_F_F16', 'SQ_V_CMPX_F_F32', + 'SQ_V_CMPX_F_F64', 'SQ_V_CMPX_F_I16', 'SQ_V_CMPX_F_I32', + 'SQ_V_CMPX_F_I64', 'SQ_V_CMPX_F_U16', 'SQ_V_CMPX_F_U32', + 'SQ_V_CMPX_F_U64', 'SQ_V_CMPX_GE_F16', 'SQ_V_CMPX_GE_F32', + 'SQ_V_CMPX_GE_F64', 'SQ_V_CMPX_GE_I16', 'SQ_V_CMPX_GE_I32', + 'SQ_V_CMPX_GE_I64', 'SQ_V_CMPX_GE_U16', 'SQ_V_CMPX_GE_U32', + 'SQ_V_CMPX_GE_U64', 'SQ_V_CMPX_GT_F16', 'SQ_V_CMPX_GT_F32', + 'SQ_V_CMPX_GT_F64', 'SQ_V_CMPX_GT_I16', 'SQ_V_CMPX_GT_I32', + 'SQ_V_CMPX_GT_I64', 'SQ_V_CMPX_GT_U16', 'SQ_V_CMPX_GT_U32', + 'SQ_V_CMPX_GT_U64', 'SQ_V_CMPX_LE_F16', 'SQ_V_CMPX_LE_F32', + 'SQ_V_CMPX_LE_F64', 'SQ_V_CMPX_LE_I16', 'SQ_V_CMPX_LE_I32', + 'SQ_V_CMPX_LE_I64', 'SQ_V_CMPX_LE_U16', 'SQ_V_CMPX_LE_U32', + 'SQ_V_CMPX_LE_U64', 'SQ_V_CMPX_LG_F16', 'SQ_V_CMPX_LG_F32', + 'SQ_V_CMPX_LG_F64', 'SQ_V_CMPX_LT_F16', 'SQ_V_CMPX_LT_F32', + 'SQ_V_CMPX_LT_F64', 'SQ_V_CMPX_LT_I16', 'SQ_V_CMPX_LT_I32', + 'SQ_V_CMPX_LT_I64', 'SQ_V_CMPX_LT_U16', 'SQ_V_CMPX_LT_U32', + 'SQ_V_CMPX_LT_U64', 'SQ_V_CMPX_NEQ_F16', 'SQ_V_CMPX_NEQ_F32', + 'SQ_V_CMPX_NEQ_F64', 'SQ_V_CMPX_NE_I16', 'SQ_V_CMPX_NE_I32', + 'SQ_V_CMPX_NE_I64', 'SQ_V_CMPX_NE_U16', 'SQ_V_CMPX_NE_U32', + 'SQ_V_CMPX_NE_U64', 'SQ_V_CMPX_NGE_F16', 'SQ_V_CMPX_NGE_F32', + 'SQ_V_CMPX_NGE_F64', 'SQ_V_CMPX_NGT_F16', 'SQ_V_CMPX_NGT_F32', + 'SQ_V_CMPX_NGT_F64', 'SQ_V_CMPX_NLE_F16', 'SQ_V_CMPX_NLE_F32', + 'SQ_V_CMPX_NLE_F64', 'SQ_V_CMPX_NLG_F16', 'SQ_V_CMPX_NLG_F32', + 'SQ_V_CMPX_NLG_F64', 'SQ_V_CMPX_NLT_F16', 'SQ_V_CMPX_NLT_F32', + 'SQ_V_CMPX_NLT_F64', 'SQ_V_CMPX_O_F16', 'SQ_V_CMPX_O_F32', + 'SQ_V_CMPX_O_F64', 'SQ_V_CMPX_TRU_F16', 'SQ_V_CMPX_TRU_F32', + 'SQ_V_CMPX_TRU_F64', 'SQ_V_CMPX_T_I16', 'SQ_V_CMPX_T_I32', + 'SQ_V_CMPX_T_I64', 'SQ_V_CMPX_T_U16', 'SQ_V_CMPX_T_U32', + 'SQ_V_CMPX_T_U64', 'SQ_V_CMPX_U_F16', 'SQ_V_CMPX_U_F32', + 'SQ_V_CMPX_U_F64', 'SQ_V_CMP_CLASS_F16', 'SQ_V_CMP_CLASS_F32', + 'SQ_V_CMP_CLASS_F64', 'SQ_V_CMP_EQ_F16', 'SQ_V_CMP_EQ_F32', + 'SQ_V_CMP_EQ_F64', 'SQ_V_CMP_EQ_I16', 'SQ_V_CMP_EQ_I32', + 'SQ_V_CMP_EQ_I64', 'SQ_V_CMP_EQ_U16', 'SQ_V_CMP_EQ_U32', + 'SQ_V_CMP_EQ_U64', 'SQ_V_CMP_F_F16', 'SQ_V_CMP_F_F32', + 'SQ_V_CMP_F_F64', 'SQ_V_CMP_F_I16', 'SQ_V_CMP_F_I32', + 'SQ_V_CMP_F_I64', 'SQ_V_CMP_F_U16', 'SQ_V_CMP_F_U32', + 'SQ_V_CMP_F_U64', 'SQ_V_CMP_GE_F16', 'SQ_V_CMP_GE_F32', + 'SQ_V_CMP_GE_F64', 'SQ_V_CMP_GE_I16', 'SQ_V_CMP_GE_I32', + 'SQ_V_CMP_GE_I64', 'SQ_V_CMP_GE_U16', 'SQ_V_CMP_GE_U32', + 'SQ_V_CMP_GE_U64', 'SQ_V_CMP_GT_F16', 'SQ_V_CMP_GT_F32', + 'SQ_V_CMP_GT_F64', 'SQ_V_CMP_GT_I16', 'SQ_V_CMP_GT_I32', + 'SQ_V_CMP_GT_I64', 'SQ_V_CMP_GT_U16', 'SQ_V_CMP_GT_U32', + 'SQ_V_CMP_GT_U64', 'SQ_V_CMP_LE_F16', 'SQ_V_CMP_LE_F32', + 'SQ_V_CMP_LE_F64', 'SQ_V_CMP_LE_I16', 'SQ_V_CMP_LE_I32', + 'SQ_V_CMP_LE_I64', 'SQ_V_CMP_LE_U16', 'SQ_V_CMP_LE_U32', + 'SQ_V_CMP_LE_U64', 'SQ_V_CMP_LG_F16', 'SQ_V_CMP_LG_F32', + 'SQ_V_CMP_LG_F64', 'SQ_V_CMP_LT_F16', 'SQ_V_CMP_LT_F32', + 'SQ_V_CMP_LT_F64', 'SQ_V_CMP_LT_I16', 'SQ_V_CMP_LT_I32', + 'SQ_V_CMP_LT_I64', 'SQ_V_CMP_LT_U16', 'SQ_V_CMP_LT_U32', + 'SQ_V_CMP_LT_U64', 'SQ_V_CMP_NEQ_F16', 'SQ_V_CMP_NEQ_F32', + 'SQ_V_CMP_NEQ_F64', 'SQ_V_CMP_NE_I16', 'SQ_V_CMP_NE_I32', + 'SQ_V_CMP_NE_I64', 'SQ_V_CMP_NE_U16', 'SQ_V_CMP_NE_U32', + 'SQ_V_CMP_NE_U64', 'SQ_V_CMP_NGE_F16', 'SQ_V_CMP_NGE_F32', + 'SQ_V_CMP_NGE_F64', 'SQ_V_CMP_NGT_F16', 'SQ_V_CMP_NGT_F32', + 'SQ_V_CMP_NGT_F64', 'SQ_V_CMP_NLE_F16', 'SQ_V_CMP_NLE_F32', + 'SQ_V_CMP_NLE_F64', 'SQ_V_CMP_NLG_F16', 'SQ_V_CMP_NLG_F32', + 'SQ_V_CMP_NLG_F64', 'SQ_V_CMP_NLT_F16', 'SQ_V_CMP_NLT_F32', + 'SQ_V_CMP_NLT_F64', 'SQ_V_CMP_O_F16', 'SQ_V_CMP_O_F32', + 'SQ_V_CMP_O_F64', 'SQ_V_CMP_TRU_F16', 'SQ_V_CMP_TRU_F32', + 'SQ_V_CMP_TRU_F64', 'SQ_V_CMP_T_I16', 'SQ_V_CMP_T_I32', + 'SQ_V_CMP_T_I64', 'SQ_V_CMP_T_U16', 'SQ_V_CMP_T_U32', + 'SQ_V_CMP_T_U64', 'SQ_V_CMP_U_F16', 'SQ_V_CMP_U_F32', + 'SQ_V_CMP_U_F64', 'SQ_V_CNDMASK_B32', 'SQ_V_COS_F16', + 'SQ_V_COS_F32', 'SQ_V_CUBEID_F32', 'SQ_V_CUBEMA_F32', + 'SQ_V_CUBESC_F32', 'SQ_V_CUBETC_F32', 'SQ_V_CVT_F16_F32', + 'SQ_V_CVT_F16_I16', 'SQ_V_CVT_F16_U16', 'SQ_V_CVT_F32_F16', + 'SQ_V_CVT_F32_F64', 'SQ_V_CVT_F32_I32', 'SQ_V_CVT_F32_U32', + 'SQ_V_CVT_F32_UBYTE0', 'SQ_V_CVT_F32_UBYTE1', + 'SQ_V_CVT_F32_UBYTE2', 'SQ_V_CVT_F32_UBYTE3', 'SQ_V_CVT_F64_F32', + 'SQ_V_CVT_F64_I32', 'SQ_V_CVT_F64_U32', 'SQ_V_CVT_FLR_I32_F32', + 'SQ_V_CVT_I16_F16', 'SQ_V_CVT_I32_F32', 'SQ_V_CVT_I32_F64', + 'SQ_V_CVT_NORM_I16_F16', 'SQ_V_CVT_NORM_U16_F16', + 'SQ_V_CVT_OFF_F32_I4', 'SQ_V_CVT_PKACCUM_U8_F32', + 'SQ_V_CVT_PKNORM_I16_F16', 'SQ_V_CVT_PKNORM_I16_F32', + 'SQ_V_CVT_PKNORM_U16_F16', 'SQ_V_CVT_PKNORM_U16_F32', + 'SQ_V_CVT_PKRTZ_F16_F32', 'SQ_V_CVT_PK_I16_I32', + 'SQ_V_CVT_PK_U16_U32', 'SQ_V_CVT_PK_U8_F32', + 'SQ_V_CVT_RPI_I32_F32', 'SQ_V_CVT_U16_F16', 'SQ_V_CVT_U32_F32', + 'SQ_V_CVT_U32_F64', 'SQ_V_DIV_FIXUP_F16', 'SQ_V_DIV_FIXUP_F32', + 'SQ_V_DIV_FIXUP_F64', 'SQ_V_DIV_FIXUP_LEGACY_F16', + 'SQ_V_DIV_FMAS_F32', 'SQ_V_DIV_FMAS_F64', 'SQ_V_DIV_SCALE_F32', + 'SQ_V_DIV_SCALE_F64', 'SQ_V_EXP_F16', 'SQ_V_EXP_F32', + 'SQ_V_EXP_LEGACY_F32', 'SQ_V_FFBH_I32', 'SQ_V_FFBH_U32', + 'SQ_V_FFBL_B32', 'SQ_V_FLOOR_F16', 'SQ_V_FLOOR_F32', + 'SQ_V_FLOOR_F64', 'SQ_V_FMA_F16', 'SQ_V_FMA_F32', 'SQ_V_FMA_F64', + 'SQ_V_FMA_LEGACY_F16', 'SQ_V_FRACT_F16', 'SQ_V_FRACT_F32', + 'SQ_V_FRACT_F64', 'SQ_V_FREXP_EXP_I16_F16', + 'SQ_V_FREXP_EXP_I32_F32', 'SQ_V_FREXP_EXP_I32_F64', + 'SQ_V_FREXP_MANT_F16', 'SQ_V_FREXP_MANT_F32', + 'SQ_V_FREXP_MANT_F64', 'SQ_V_INTERP_MOV_F32', + 'SQ_V_INTERP_P1LL_F16', 'SQ_V_INTERP_P1LV_F16', + 'SQ_V_INTERP_P1_F32', 'SQ_V_INTERP_P2_F16', 'SQ_V_INTERP_P2_F32', + 'SQ_V_INTERP_P2_LEGACY_F16', 'SQ_V_INTRP_COUNT', + 'SQ_V_INTRP_OFFSET', 'SQ_V_LDEXP_F16', 'SQ_V_LDEXP_F32', + 'SQ_V_LDEXP_F64', 'SQ_V_LERP_U8', 'SQ_V_LOG_F16', 'SQ_V_LOG_F32', + 'SQ_V_LOG_LEGACY_F32', 'SQ_V_LSHLREV_B16', 'SQ_V_LSHLREV_B32', + 'SQ_V_LSHLREV_B64', 'SQ_V_LSHL_ADD_U32', 'SQ_V_LSHL_OR_B32', + 'SQ_V_LSHRREV_B16', 'SQ_V_LSHRREV_B32', 'SQ_V_LSHRREV_B64', + 'SQ_V_MAC_F16', 'SQ_V_MAC_F32', 'SQ_V_MAC_LEGACY_F32', + 'SQ_V_MADAK_F16', 'SQ_V_MADAK_F32', 'SQ_V_MADMK_F16', + 'SQ_V_MADMK_F32', 'SQ_V_MAD_F16', 'SQ_V_MAD_F32', 'SQ_V_MAD_I16', + 'SQ_V_MAD_I32_I16', 'SQ_V_MAD_I32_I24', 'SQ_V_MAD_I64_I32', + 'SQ_V_MAD_LEGACY_F16', 'SQ_V_MAD_LEGACY_F32', + 'SQ_V_MAD_LEGACY_I16', 'SQ_V_MAD_LEGACY_U16', + 'SQ_V_MAD_MIXHI_F16', 'SQ_V_MAD_MIXLO_F16', 'SQ_V_MAD_MIX_F32', + 'SQ_V_MAD_U16', 'SQ_V_MAD_U32_U16', 'SQ_V_MAD_U32_U24', + 'SQ_V_MAD_U64_U32', 'SQ_V_MAX3_F16', 'SQ_V_MAX3_F32', + 'SQ_V_MAX3_I16', 'SQ_V_MAX3_I32', 'SQ_V_MAX3_U16', + 'SQ_V_MAX3_U32', 'SQ_V_MAX_F16', 'SQ_V_MAX_F32', 'SQ_V_MAX_F64', + 'SQ_V_MAX_I16', 'SQ_V_MAX_I32', 'SQ_V_MAX_U16', 'SQ_V_MAX_U32', + 'SQ_V_MBCNT_HI_U32_B32', 'SQ_V_MBCNT_LO_U32_B32', 'SQ_V_MED3_F16', + 'SQ_V_MED3_F32', 'SQ_V_MED3_I16', 'SQ_V_MED3_I32', + 'SQ_V_MED3_U16', 'SQ_V_MED3_U32', 'SQ_V_MIN3_F16', + 'SQ_V_MIN3_F32', 'SQ_V_MIN3_I16', 'SQ_V_MIN3_I32', + 'SQ_V_MIN3_U16', 'SQ_V_MIN3_U32', 'SQ_V_MIN_F16', 'SQ_V_MIN_F32', + 'SQ_V_MIN_F64', 'SQ_V_MIN_I16', 'SQ_V_MIN_I32', 'SQ_V_MIN_U16', + 'SQ_V_MIN_U32', 'SQ_V_MOV_B32', 'SQ_V_MOV_FED_B32', + 'SQ_V_MOV_PRSV_B32', 'SQ_V_MQSAD_PK_U16_U8', 'SQ_V_MQSAD_U32_U8', + 'SQ_V_MSAD_U8', 'SQ_V_MUL_F16', 'SQ_V_MUL_F32', 'SQ_V_MUL_F64', + 'SQ_V_MUL_HI_I32', 'SQ_V_MUL_HI_I32_I24', 'SQ_V_MUL_HI_U32', + 'SQ_V_MUL_HI_U32_U24', 'SQ_V_MUL_I32_I24', 'SQ_V_MUL_LEGACY_F32', + 'SQ_V_MUL_LO_U16', 'SQ_V_MUL_LO_U32', 'SQ_V_MUL_U32_U24', + 'SQ_V_NOP', 'SQ_V_NOT_B32', 'SQ_V_OP1_COUNT', 'SQ_V_OP1_OFFSET', + 'SQ_V_OP2_COUNT', 'SQ_V_OP2_OFFSET', 'SQ_V_OP3P_COUNT', + 'SQ_V_OP3P_OFFSET', 'SQ_V_OP3_2IN_COUNT', 'SQ_V_OP3_2IN_OFFSET', + 'SQ_V_OP3_3IN_COUNT', 'SQ_V_OP3_3IN_OFFSET', + 'SQ_V_OP3_INTRP_COUNT', 'SQ_V_OP3_INTRP_OFFSET', 'SQ_V_OPC_COUNT', + 'SQ_V_OPC_OFFSET', 'SQ_V_OR3_B32', 'SQ_V_OR_B32', + 'SQ_V_PACK_B32_F16', 'SQ_V_PERM_B32', 'SQ_V_PK_ADD_F16', + 'SQ_V_PK_ADD_I16', 'SQ_V_PK_ADD_U16', 'SQ_V_PK_ASHRREV_I16', + 'SQ_V_PK_LSHLREV_B16', 'SQ_V_PK_LSHRREV_B16', 'SQ_V_PK_MAD_F16', + 'SQ_V_PK_MAD_I16', 'SQ_V_PK_MAD_U16', 'SQ_V_PK_MAX_F16', + 'SQ_V_PK_MAX_I16', 'SQ_V_PK_MAX_U16', 'SQ_V_PK_MIN_F16', + 'SQ_V_PK_MIN_I16', 'SQ_V_PK_MIN_U16', 'SQ_V_PK_MUL_F16', + 'SQ_V_PK_MUL_LO_U16', 'SQ_V_PK_SUB_I16', 'SQ_V_PK_SUB_U16', + 'SQ_V_QSAD_PK_U16_U8', 'SQ_V_RCP_F16', 'SQ_V_RCP_F32', + 'SQ_V_RCP_F64', 'SQ_V_RCP_IFLAG_F32', 'SQ_V_READFIRSTLANE_B32', + 'SQ_V_READLANE_B32', 'SQ_V_READLANE_REGRD_B32', 'SQ_V_RNDNE_F16', + 'SQ_V_RNDNE_F32', 'SQ_V_RNDNE_F64', 'SQ_V_RSQ_F16', + 'SQ_V_RSQ_F32', 'SQ_V_RSQ_F64', 'SQ_V_SAD_HI_U8', 'SQ_V_SAD_U16', + 'SQ_V_SAD_U32', 'SQ_V_SAD_U8', 'SQ_V_SAT_PK_U8_I16', + 'SQ_V_SIN_F16', 'SQ_V_SIN_F32', 'SQ_V_SQRT_F16', 'SQ_V_SQRT_F32', + 'SQ_V_SQRT_F64', 'SQ_V_SUBBREV_CO_U32', 'SQ_V_SUBB_CO_U32', + 'SQ_V_SUBREV_CO_U32', 'SQ_V_SUBREV_F16', 'SQ_V_SUBREV_F32', + 'SQ_V_SUBREV_U16', 'SQ_V_SUBREV_U32', 'SQ_V_SUB_CO_U32', + 'SQ_V_SUB_F16', 'SQ_V_SUB_F32', 'SQ_V_SUB_I16', 'SQ_V_SUB_I32', + 'SQ_V_SUB_U16', 'SQ_V_SUB_U32', 'SQ_V_SWAP_B32', + 'SQ_V_TRIG_PREOP_F64', 'SQ_V_TRUNC_F16', 'SQ_V_TRUNC_F32', + 'SQ_V_TRUNC_F64', 'SQ_V_WRITELANE_B32', 'SQ_V_WRITELANE_IMM32', + 'SQ_V_XAD_U32', 'SQ_V_XOR_B32', 'SQ_WAITCNT_EXP_SHIFT', + 'SQ_WAITCNT_EXP_SIZE', 'SQ_WAITCNT_LGKM_SHIFT', + 'SQ_WAITCNT_LGKM_SIZE', 'SQ_WAITCNT_VM_SHIFT', + 'SQ_WAITCNT_VM_SIZE', 'SQ_WAVE_IB_ECC_CLEAN', + 'SQ_WAVE_IB_ECC_ERR_CONTINUE', 'SQ_WAVE_IB_ECC_ERR_HALT', + 'SQ_WAVE_IB_ECC_ST', 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', + 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', 'SQ_WAVE_TYPE_ES', + 'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_LS', + 'SQ_WAVE_TYPE_PS', 'SQ_WAVE_TYPE_PS0', 'SQ_WAVE_TYPE_PS1', + 'SQ_WAVE_TYPE_VS', 'SQ_XLATE_VOP3_TO_VINTRP_COUNT', + 'SQ_XLATE_VOP3_TO_VINTRP_OFFSET', 'SQ_XLATE_VOP3_TO_VOP1_COUNT', + 'SQ_XLATE_VOP3_TO_VOP1_OFFSET', 'SQ_XLATE_VOP3_TO_VOP2_COUNT', + 'SQ_XLATE_VOP3_TO_VOP2_OFFSET', 'SQ_XLATE_VOP3_TO_VOP3P_COUNT', + 'SQ_XLATE_VOP3_TO_VOP3P_OFFSET', 'SQ_XLATE_VOP3_TO_VOPC_COUNT', + 'SQ_XLATE_VOP3_TO_VOPC_OFFSET', 'SQ_XNACK_MASK_HI', + 'SQ_XNACK_MASK_LO', 'STATIC_SCREEN_SMU_INTR', + 'STATIC_SCREEN_SMU_INTR_NOOP', 'STENCIL_8', 'STENCIL_ADD_CLAMP', + 'STENCIL_ADD_WRAP', 'STENCIL_AND', 'STENCIL_INVALID', + 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', + 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', + 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', + 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', + 'STREAM_0_SYNCHRONIZATION', + 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_10_SYNCHRONIZATION', + 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION', + 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION', + 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION', + 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION', + 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION', + 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_1_SYNCHRONIZATION', + 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_2_SYNCHRONIZATION', + 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_3_SYNCHRONIZATION', + 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_4_SYNCHRONIZATION', + 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_5_SYNCHRONIZATION', + 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_6_SYNCHRONIZATION', + 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION', + 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION', + 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION', + 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'STRM_PERFMON_STATE_RESERVED_3', + 'STRM_PERFMON_STATE_START_COUNTING', + 'STRM_PERFMON_STATE_STOP_COUNTING', 'SU_PERFCNT_SEL', 'SWAP_ALT', + 'SWAP_ALT_REV', 'SWAP_STD', 'SWAP_STD_REV', 'SWIZZLE_MODE_ENUM', + 'SWIZZLE_TYPE_ENUM', 'SW_256B_D', 'SW_256B_R', 'SW_256B_S', + 'SW_4KB_D', 'SW_4KB_D_X', 'SW_4KB_R', 'SW_4KB_R_X', 'SW_4KB_S', + 'SW_4KB_S_X', 'SW_4KB_Z', 'SW_4KB_Z_X', 'SW_64KB_D', + 'SW_64KB_D_X', 'SW_64KB_R', 'SW_64KB_R_X', 'SW_64KB_S', + 'SW_64KB_S_X', 'SW_64KB_Z', 'SW_64KB_Z_X', 'SW_D', 'SW_L', + 'SW_LINEAR', 'SW_R', 'SW_RESERVED_12', 'SW_RESERVED_13', + 'SW_RESERVED_14', 'SW_RESERVED_15', 'SW_RESERVED_16', + 'SW_RESERVED_17', 'SW_RESERVED_18', 'SW_RESERVED_19', 'SW_S', + 'SW_VAR_D', 'SW_VAR_D_X', 'SW_VAR_R', 'SW_VAR_R_X', 'SW_VAR_S', + 'SW_VAR_S_X', 'SW_VAR_Z', 'SW_VAR_Z_X', 'SW_Z', 'SX_BLEND_OPT', + 'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT', + 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK', + 'SX_PERF_SEL_COL_BUSY', 'SX_PERF_SEL_DB0_A2M_DISCARD_QUADS', + 'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT0_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT1_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT2_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT3_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT4_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT5_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT6_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS', + 'SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT7_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', + 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', + 'SX_PERF_SEL_DB0_PRED_PIXELS', + 'SX_PERF_SEL_DB1_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB1_HALF_QUADS', + 'SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT0_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT1_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT2_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT3_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT4_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT5_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT6_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS', + 'SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT7_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', + 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', + 'SX_PERF_SEL_DB1_PRED_PIXELS', + 'SX_PERF_SEL_DB2_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB2_HALF_QUADS', + 'SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT0_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT1_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT2_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT3_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT4_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT5_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT6_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS', + 'SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT7_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', + 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', + 'SX_PERF_SEL_DB2_PRED_PIXELS', + 'SX_PERF_SEL_DB3_A2M_DISCARD_QUADS', 'SX_PERF_SEL_DB3_HALF_QUADS', + 'SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT0_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT1_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT2_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT3_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT4_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT5_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT6_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS', + 'SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT7_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', + 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', + 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_GATE_EN1', + 'SX_PERF_SEL_GATE_EN2', 'SX_PERF_SEL_GATE_EN3', + 'SX_PERF_SEL_GATE_EN4', 'SX_PERF_SEL_PA_IDLE_CYCLES', + 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_REQ', + 'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_SH_COLOR_STALL', + 'SX_PERF_SEL_SH_COLOR_STARVE', 'SX_PERF_SEL_SH_POS_STALL', + 'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11', + 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', + 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', + 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', + 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', + 'SX_RT_EXPORT_NO_CONVERSION', 'SYMCLK_FE_FORCE_EN', + 'SYMCLK_FE_FORCE_EN_DISABLE', 'SYMCLK_FE_FORCE_EN_ENABLE', + 'SYMCLK_FE_FORCE_SRC', 'SYMCLK_FE_FORCE_SRC_UNIPHYA', + 'SYMCLK_FE_FORCE_SRC_UNIPHYB', 'SYMCLK_FE_FORCE_SRC_UNIPHYC', + 'SYMCLK_FE_FORCE_SRC_UNIPHYD', 'SYMCLK_FE_FORCE_SRC_UNIPHYE', + 'SYMCLK_FE_FORCE_SRC_UNIPHYF', 'SYMCLK_FE_FORCE_SRC_UNIPHYG', + 'SYNC_DURATION_128', 'SYNC_DURATION_16', 'SYNC_DURATION_32', + 'SYNC_DURATION_64', 'SYNC_RESET_SEL2_VBLANK', + 'SYNC_RESET_SEL2_VSYNC', 'SampleSplit', 'SampleSplitBytes', + 'ScMap', 'ScXsel', 'ScYsel', 'SeEnable', 'SeMap', 'SePairMap', + 'SePairXsel', 'SePairYsel', 'SeXsel', 'SeYsel', + 'ShaderEngineTileSize', 'SourceFormat', 'StencilFormat', + 'StencilOp', 'SurfaceArray', 'SurfaceEndian', 'SurfaceFormat', + 'SurfaceNumber', 'SurfaceSwap', 'SurfaceTiling', + 'TA_PERFCOUNT_SEL', 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_RESERVED_28', + 'TA_PERF_SEL_RESERVED_29', 'TA_PERF_SEL_RESERVED_41', + 'TA_PERF_SEL_RESERVED_42', 'TA_PERF_SEL_RESERVED_43', + 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', + 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 'TA_PERF_SEL_addresser_stalled_cycles', + 'TA_PERF_SEL_aligner_busy', 'TA_PERF_SEL_aligner_cycles', + 'TA_PERF_SEL_aniso_10_cycle_quads', + 'TA_PERF_SEL_aniso_12_cycle_quads', + 'TA_PERF_SEL_aniso_14_cycle_quads', + 'TA_PERF_SEL_aniso_16_cycle_quads', + 'TA_PERF_SEL_aniso_1_cycle_quads', + 'TA_PERF_SEL_aniso_2_cycle_quads', + 'TA_PERF_SEL_aniso_4_cycle_quads', + 'TA_PERF_SEL_aniso_6_cycle_quads', + 'TA_PERF_SEL_aniso_8_cycle_quads', + 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 'TA_PERF_SEL_aniso_stalled_cycles', + 'TA_PERF_SEL_bilin_point_1_cycle_pixels', + 'TA_PERF_SEL_buffer_atomic_wavefronts', + 'TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles', + 'TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles', + 'TA_PERF_SEL_buffer_coalescable_wavefronts', + 'TA_PERF_SEL_buffer_coalesced_read_cycles', + 'TA_PERF_SEL_buffer_coalesced_write_cycles', + 'TA_PERF_SEL_buffer_read_wavefronts', + 'TA_PERF_SEL_buffer_total_cycles', + 'TA_PERF_SEL_buffer_wavefronts', + 'TA_PERF_SEL_buffer_write_wavefronts', + 'TA_PERF_SEL_color_1_cycle_pixels', + 'TA_PERF_SEL_color_2_cycle_pixels', + 'TA_PERF_SEL_color_3_cycle_pixels', + 'TA_PERF_SEL_color_4_cycle_pixels', + 'TA_PERF_SEL_data_stalled_by_tc_cycles', + 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 'TA_PERF_SEL_deriv_stalled_cycles', + 'TA_PERF_SEL_first_xnack_on_phase0', + 'TA_PERF_SEL_first_xnack_on_phase1', + 'TA_PERF_SEL_first_xnack_on_phase2', + 'TA_PERF_SEL_first_xnack_on_phase3', + 'TA_PERF_SEL_flat_atomic_wavefronts', + 'TA_PERF_SEL_flat_coalesceable_wavefronts', + 'TA_PERF_SEL_flat_read_wavefronts', 'TA_PERF_SEL_flat_wavefronts', + 'TA_PERF_SEL_flat_write_wavefronts', 'TA_PERF_SEL_gradient_busy', + 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', + 'TA_PERF_SEL_image_atomic_wavefronts', + 'TA_PERF_SEL_image_read_wavefronts', + 'TA_PERF_SEL_image_total_cycles', 'TA_PERF_SEL_image_wavefronts', + 'TA_PERF_SEL_image_write_wavefronts', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp0_en', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_en', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp4_en', + 'TA_PERF_SEL_local_cg_dyn_sclk_grp5_en', 'TA_PERF_SEL_lod_busy', + 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_pixels', + 'TA_PERF_SEL_mip_2_cycle_pixels', + 'TA_PERF_SEL_mipmap_invalid_samples', + 'TA_PERF_SEL_mipmap_lod_0_samples', + 'TA_PERF_SEL_mipmap_lod_10_samples', + 'TA_PERF_SEL_mipmap_lod_11_samples', + 'TA_PERF_SEL_mipmap_lod_12_samples', + 'TA_PERF_SEL_mipmap_lod_13_samples', + 'TA_PERF_SEL_mipmap_lod_14_samples', + 'TA_PERF_SEL_mipmap_lod_1_samples', + 'TA_PERF_SEL_mipmap_lod_2_samples', + 'TA_PERF_SEL_mipmap_lod_3_samples', + 'TA_PERF_SEL_mipmap_lod_4_samples', + 'TA_PERF_SEL_mipmap_lod_5_samples', + 'TA_PERF_SEL_mipmap_lod_6_samples', + 'TA_PERF_SEL_mipmap_lod_7_samples', + 'TA_PERF_SEL_mipmap_lod_8_samples', + 'TA_PERF_SEL_mipmap_lod_9_samples', 'TA_PERF_SEL_reg_sclk_vld', + 'TA_PERF_SEL_sh_fifo_addr_busy', + 'TA_PERF_SEL_sh_fifo_addr_cycles', + 'TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles', + 'TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles', + 'TA_PERF_SEL_sh_fifo_busy', 'TA_PERF_SEL_sh_fifo_cmd_busy', + 'TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles', + 'TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles', + 'TA_PERF_SEL_sh_fifo_data_busy', + 'TA_PERF_SEL_sh_fifo_data_cycles', + 'TA_PERF_SEL_sh_fifo_data_sfifo_busy', + 'TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles', + 'TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles', + 'TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles', + 'TA_PERF_SEL_sh_fifo_data_tfifo_busy', + 'TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles', + 'TA_PERF_SEL_sp_ta_addr_cycles', 'TA_PERF_SEL_sp_ta_data_cycles', + 'TA_PERF_SEL_sq_ta_cmd_cycles', 'TA_PERF_SEL_ta_busy', + 'TA_PERF_SEL_ta_fa_data_state_cycles', + 'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vol_1_cycle_pixels', + 'TA_PERF_SEL_vol_2_cycle_pixels', 'TA_PERF_SEL_walker_cycles', + 'TA_PERF_SEL_write_path_busy', + 'TA_PERF_SEL_write_path_input_cycles', + 'TA_PERF_SEL_write_path_output_cycles', + 'TA_PERF_SEL_xnack_on_phase0', 'TA_PERF_SEL_xnack_on_phase1', + 'TA_PERF_SEL_xnack_on_phase2', 'TA_PERF_SEL_xnack_on_phase3', + 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', + 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', + 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', + 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', + 'TCA_PERF_SEL', 'TCA_PERF_SEL_BUSY', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6', + 'TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC0', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC1', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC2', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC3', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC4', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC5', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC6', + 'TCA_PERF_SEL_CROSSBAR_STALL_TCC7', 'TCA_PERF_SEL_CYCLE', + 'TCA_PERF_SEL_FORCED_HOLE_TCC0', 'TCA_PERF_SEL_FORCED_HOLE_TCC1', + 'TCA_PERF_SEL_FORCED_HOLE_TCC2', 'TCA_PERF_SEL_FORCED_HOLE_TCC3', + 'TCA_PERF_SEL_FORCED_HOLE_TCC4', 'TCA_PERF_SEL_FORCED_HOLE_TCC5', + 'TCA_PERF_SEL_FORCED_HOLE_TCC6', 'TCA_PERF_SEL_FORCED_HOLE_TCC7', + 'TCA_PERF_SEL_NONE', 'TCA_PERF_SEL_REQ_TCC0', + 'TCA_PERF_SEL_REQ_TCC1', 'TCA_PERF_SEL_REQ_TCC2', + 'TCA_PERF_SEL_REQ_TCC3', 'TCA_PERF_SEL_REQ_TCC4', + 'TCA_PERF_SEL_REQ_TCC5', 'TCA_PERF_SEL_REQ_TCC6', + 'TCA_PERF_SEL_REQ_TCC7', 'TCC_CACHE_POLICIES', + 'TCC_CACHE_POLICY_LRU', 'TCC_CACHE_POLICY_STREAM', 'TCC_PERF_SEL', + 'TCC_PERF_SEL_ALL_TC_OP_INV_EVICT', + 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE', + 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH', + 'TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 'TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK', 'TCC_PERF_SEL_ATOMIC', + 'TCC_PERF_SEL_BUBBLE', 'TCC_PERF_SEL_BUSY', + 'TCC_PERF_SEL_CC_PHYSICAL_REQ', 'TCC_PERF_SEL_CLIENT0_REQ', + 'TCC_PERF_SEL_CLIENT100_REQ', 'TCC_PERF_SEL_CLIENT101_REQ', + 'TCC_PERF_SEL_CLIENT102_REQ', 'TCC_PERF_SEL_CLIENT103_REQ', + 'TCC_PERF_SEL_CLIENT104_REQ', 'TCC_PERF_SEL_CLIENT105_REQ', + 'TCC_PERF_SEL_CLIENT106_REQ', 'TCC_PERF_SEL_CLIENT107_REQ', + 'TCC_PERF_SEL_CLIENT108_REQ', 'TCC_PERF_SEL_CLIENT109_REQ', + 'TCC_PERF_SEL_CLIENT10_REQ', 'TCC_PERF_SEL_CLIENT110_REQ', + 'TCC_PERF_SEL_CLIENT111_REQ', 'TCC_PERF_SEL_CLIENT112_REQ', + 'TCC_PERF_SEL_CLIENT113_REQ', 'TCC_PERF_SEL_CLIENT114_REQ', + 'TCC_PERF_SEL_CLIENT115_REQ', 'TCC_PERF_SEL_CLIENT116_REQ', + 'TCC_PERF_SEL_CLIENT117_REQ', 'TCC_PERF_SEL_CLIENT118_REQ', + 'TCC_PERF_SEL_CLIENT119_REQ', 'TCC_PERF_SEL_CLIENT11_REQ', + 'TCC_PERF_SEL_CLIENT120_REQ', 'TCC_PERF_SEL_CLIENT121_REQ', + 'TCC_PERF_SEL_CLIENT122_REQ', 'TCC_PERF_SEL_CLIENT123_REQ', + 'TCC_PERF_SEL_CLIENT124_REQ', 'TCC_PERF_SEL_CLIENT125_REQ', + 'TCC_PERF_SEL_CLIENT126_REQ', 'TCC_PERF_SEL_CLIENT127_REQ', + 'TCC_PERF_SEL_CLIENT12_REQ', 'TCC_PERF_SEL_CLIENT13_REQ', + 'TCC_PERF_SEL_CLIENT14_REQ', 'TCC_PERF_SEL_CLIENT15_REQ', + 'TCC_PERF_SEL_CLIENT16_REQ', 'TCC_PERF_SEL_CLIENT17_REQ', + 'TCC_PERF_SEL_CLIENT18_REQ', 'TCC_PERF_SEL_CLIENT19_REQ', + 'TCC_PERF_SEL_CLIENT1_REQ', 'TCC_PERF_SEL_CLIENT20_REQ', + 'TCC_PERF_SEL_CLIENT21_REQ', 'TCC_PERF_SEL_CLIENT22_REQ', + 'TCC_PERF_SEL_CLIENT23_REQ', 'TCC_PERF_SEL_CLIENT24_REQ', + 'TCC_PERF_SEL_CLIENT25_REQ', 'TCC_PERF_SEL_CLIENT26_REQ', + 'TCC_PERF_SEL_CLIENT27_REQ', 'TCC_PERF_SEL_CLIENT28_REQ', + 'TCC_PERF_SEL_CLIENT29_REQ', 'TCC_PERF_SEL_CLIENT2_REQ', + 'TCC_PERF_SEL_CLIENT30_REQ', 'TCC_PERF_SEL_CLIENT31_REQ', + 'TCC_PERF_SEL_CLIENT32_REQ', 'TCC_PERF_SEL_CLIENT33_REQ', + 'TCC_PERF_SEL_CLIENT34_REQ', 'TCC_PERF_SEL_CLIENT35_REQ', + 'TCC_PERF_SEL_CLIENT36_REQ', 'TCC_PERF_SEL_CLIENT37_REQ', + 'TCC_PERF_SEL_CLIENT38_REQ', 'TCC_PERF_SEL_CLIENT39_REQ', + 'TCC_PERF_SEL_CLIENT3_REQ', 'TCC_PERF_SEL_CLIENT40_REQ', + 'TCC_PERF_SEL_CLIENT41_REQ', 'TCC_PERF_SEL_CLIENT42_REQ', + 'TCC_PERF_SEL_CLIENT43_REQ', 'TCC_PERF_SEL_CLIENT44_REQ', + 'TCC_PERF_SEL_CLIENT45_REQ', 'TCC_PERF_SEL_CLIENT46_REQ', + 'TCC_PERF_SEL_CLIENT47_REQ', 'TCC_PERF_SEL_CLIENT48_REQ', + 'TCC_PERF_SEL_CLIENT49_REQ', 'TCC_PERF_SEL_CLIENT4_REQ', + 'TCC_PERF_SEL_CLIENT50_REQ', 'TCC_PERF_SEL_CLIENT51_REQ', + 'TCC_PERF_SEL_CLIENT52_REQ', 'TCC_PERF_SEL_CLIENT53_REQ', + 'TCC_PERF_SEL_CLIENT54_REQ', 'TCC_PERF_SEL_CLIENT55_REQ', + 'TCC_PERF_SEL_CLIENT56_REQ', 'TCC_PERF_SEL_CLIENT57_REQ', + 'TCC_PERF_SEL_CLIENT58_REQ', 'TCC_PERF_SEL_CLIENT59_REQ', + 'TCC_PERF_SEL_CLIENT5_REQ', 'TCC_PERF_SEL_CLIENT60_REQ', + 'TCC_PERF_SEL_CLIENT61_REQ', 'TCC_PERF_SEL_CLIENT62_REQ', + 'TCC_PERF_SEL_CLIENT63_REQ', 'TCC_PERF_SEL_CLIENT64_REQ', + 'TCC_PERF_SEL_CLIENT65_REQ', 'TCC_PERF_SEL_CLIENT66_REQ', + 'TCC_PERF_SEL_CLIENT67_REQ', 'TCC_PERF_SEL_CLIENT68_REQ', + 'TCC_PERF_SEL_CLIENT69_REQ', 'TCC_PERF_SEL_CLIENT6_REQ', + 'TCC_PERF_SEL_CLIENT70_REQ', 'TCC_PERF_SEL_CLIENT71_REQ', + 'TCC_PERF_SEL_CLIENT72_REQ', 'TCC_PERF_SEL_CLIENT73_REQ', + 'TCC_PERF_SEL_CLIENT74_REQ', 'TCC_PERF_SEL_CLIENT75_REQ', + 'TCC_PERF_SEL_CLIENT76_REQ', 'TCC_PERF_SEL_CLIENT77_REQ', + 'TCC_PERF_SEL_CLIENT78_REQ', 'TCC_PERF_SEL_CLIENT79_REQ', + 'TCC_PERF_SEL_CLIENT7_REQ', 'TCC_PERF_SEL_CLIENT80_REQ', + 'TCC_PERF_SEL_CLIENT81_REQ', 'TCC_PERF_SEL_CLIENT82_REQ', + 'TCC_PERF_SEL_CLIENT83_REQ', 'TCC_PERF_SEL_CLIENT84_REQ', + 'TCC_PERF_SEL_CLIENT85_REQ', 'TCC_PERF_SEL_CLIENT86_REQ', + 'TCC_PERF_SEL_CLIENT87_REQ', 'TCC_PERF_SEL_CLIENT88_REQ', + 'TCC_PERF_SEL_CLIENT89_REQ', 'TCC_PERF_SEL_CLIENT8_REQ', + 'TCC_PERF_SEL_CLIENT90_REQ', 'TCC_PERF_SEL_CLIENT91_REQ', + 'TCC_PERF_SEL_CLIENT92_REQ', 'TCC_PERF_SEL_CLIENT93_REQ', + 'TCC_PERF_SEL_CLIENT94_REQ', 'TCC_PERF_SEL_CLIENT95_REQ', + 'TCC_PERF_SEL_CLIENT96_REQ', 'TCC_PERF_SEL_CLIENT97_REQ', + 'TCC_PERF_SEL_CLIENT98_REQ', 'TCC_PERF_SEL_CLIENT99_REQ', + 'TCC_PERF_SEL_CLIENT9_REQ', 'TCC_PERF_SEL_COMPRESSED_0_REQ', + 'TCC_PERF_SEL_COMPRESSED_REQ', 'TCC_PERF_SEL_CYCLE', + 'TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'TCC_PERF_SEL_EA_ATOMIC', + 'TCC_PERF_SEL_EA_ATOMIC_LEVEL', 'TCC_PERF_SEL_EA_RDREQ', + 'TCC_PERF_SEL_EA_RDREQ_32B', 'TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL', + 'TCC_PERF_SEL_EA_RDREQ_LEVEL', + 'TCC_PERF_SEL_EA_RD_COMPRESSED_32B', 'TCC_PERF_SEL_EA_RD_MDC_32B', + 'TCC_PERF_SEL_EA_RD_UNCACHED_32B', 'TCC_PERF_SEL_EA_WRREQ', + 'TCC_PERF_SEL_EA_WRREQ_64B', 'TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL', + 'TCC_PERF_SEL_EA_WRREQ_LEVEL', + 'TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND', + 'TCC_PERF_SEL_EA_WRREQ_STALL', 'TCC_PERF_SEL_EA_WR_UNCACHED_32B', + 'TCC_PERF_SEL_EXE_REQ', 'TCC_PERF_SEL_FULLY_WRITTEN_HIT', + 'TCC_PERF_SEL_HIT', 'TCC_PERF_SEL_HOLE_FIFO_FULL', + 'TCC_PERF_SEL_HOLE_LEVEL', 'TCC_PERF_SEL_IB_MDC_STALL', + 'TCC_PERF_SEL_IB_REQ', 'TCC_PERF_SEL_IB_STALL', + 'TCC_PERF_SEL_IB_TAG_STALL', 'TCC_PERF_SEL_LATENCY_FIFO_FULL', + 'TCC_PERF_SEL_MDC_LEVEL', 'TCC_PERF_SEL_MDC_REQ', + 'TCC_PERF_SEL_MDC_SECTOR_HIT', 'TCC_PERF_SEL_MDC_SECTOR_MISS', + 'TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', + 'TCC_PERF_SEL_MDC_TAG_HIT', + 'TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', + 'TCC_PERF_SEL_MDC_TAG_STALL', + 'TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', + 'TCC_PERF_SEL_METADATA_REQ', 'TCC_PERF_SEL_MISS', + 'TCC_PERF_SEL_NC_VIRTUAL_REQ', 'TCC_PERF_SEL_NONE', + 'TCC_PERF_SEL_NORMAL_EVICT', 'TCC_PERF_SEL_NORMAL_WRITEBACK', + 'TCC_PERF_SEL_PROBE', 'TCC_PERF_SEL_PROBE_ALL', + 'TCC_PERF_SEL_PROBE_EVICT', 'TCC_PERF_SEL_PROBE_FILTER_DISABLED', + 'TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', + 'TCC_PERF_SEL_READ', 'TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 'TCC_PERF_SEL_READ_RETURN_TIMEOUT', 'TCC_PERF_SEL_REQ', + 'TCC_PERF_SEL_RETURN_ACK', 'TCC_PERF_SEL_RETURN_ACK_HOLE', + 'TCC_PERF_SEL_RETURN_DATA', 'TCC_PERF_SEL_RETURN_HOLE', + 'TCC_PERF_SEL_SECTOR_HIT', 'TCC_PERF_SEL_SRC_FIFO_FULL', + 'TCC_PERF_SEL_STREAMING_REQ', + 'TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 'TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 'TCC_PERF_SEL_TAG_PROBE_FILTER_STALL', + 'TCC_PERF_SEL_TAG_PROBE_STALL', 'TCC_PERF_SEL_TAG_STALL', + 'TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 'TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 'TCC_PERF_SEL_TCA_LEVEL', 'TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE', + 'TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT', + 'TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH', + 'TCC_PERF_SEL_TC_OP_INVL2_NC_START', + 'TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE', + 'TCC_PERF_SEL_TC_OP_WBINVL2_EVICT', + 'TCC_PERF_SEL_TC_OP_WBINVL2_FINISH', + 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE', + 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT', + 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH', + 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_START', + 'TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK', + 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE', + 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT', + 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH', + 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_START', + 'TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK', + 'TCC_PERF_SEL_TC_OP_WBINVL2_START', + 'TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK', + 'TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE', + 'TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT', + 'TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH', + 'TCC_PERF_SEL_TC_OP_WBL2_NC_START', + 'TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK', + 'TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE', + 'TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT', + 'TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH', + 'TCC_PERF_SEL_TC_OP_WBL2_WC_START', + 'TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK', + 'TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', + 'TCC_PERF_SEL_UC_VIRTUAL_REQ', 'TCC_PERF_SEL_WRITE', + 'TCC_PERF_SEL_WRITEBACK', 'TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT', + 'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT', + 'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES', + 'TCP_CACHE_STORE_POLICY_WT_EVICT', + 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL', + 'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0', + 'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2', + 'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1', + 'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE', + 'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN', + 'TCP_PERFCOUNT_SELECT', 'TCP_PERF_SEL_ALLOC_STALL_CYCLES', + 'TCP_PERF_SEL_ARR_1D_THICK', 'TCP_PERF_SEL_ARR_1D_THIN1', + 'TCP_PERF_SEL_ARR_2D_THICK', 'TCP_PERF_SEL_ARR_2D_THIN1', + 'TCP_PERF_SEL_ARR_2D_XTHICK', 'TCP_PERF_SEL_ARR_3D_THICK', + 'TCP_PERF_SEL_ARR_3D_THIN1', 'TCP_PERF_SEL_ARR_3D_XTHICK', + 'TCP_PERF_SEL_ARR_LINEAR_ALIGNED', + 'TCP_PERF_SEL_ARR_LINEAR_GENERAL', + 'TCP_PERF_SEL_ARR_PRT_2D_THICK', 'TCP_PERF_SEL_ARR_PRT_2D_THIN1', + 'TCP_PERF_SEL_ARR_PRT_3D_THICK', 'TCP_PERF_SEL_ARR_PRT_3D_THIN1', + 'TCP_PERF_SEL_ARR_PRT_THICK', 'TCP_PERF_SEL_ARR_PRT_THIN1', + 'TCP_PERF_SEL_ATC', + 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES', + 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32', + 'TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64', + 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32', + 'TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64', + 'TCP_PERF_SEL_BUF_READ_FMT_16', 'TCP_PERF_SEL_BUF_READ_FMT_32', + 'TCP_PERF_SEL_BUF_READ_FMT_8', 'TCP_PERF_SEL_BUF_WRITE_FMT_16', + 'TCP_PERF_SEL_BUF_WRITE_FMT_32', 'TCP_PERF_SEL_BUF_WRITE_FMT_8', + 'TCP_PERF_SEL_CORE_REG_SCLK_VLD', + 'TCP_PERF_SEL_CP_TCP_INVALIDATE', + 'TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL', + 'TCP_PERF_SEL_DEPTH_MICROTILING', 'TCP_PERF_SEL_DIM_1D', + 'TCP_PERF_SEL_DIM_1D_ARRAY', 'TCP_PERF_SEL_DIM_2D', + 'TCP_PERF_SEL_DIM_2D_ARRAY', 'TCP_PERF_SEL_DIM_2D_ARRAY_MSAA', + 'TCP_PERF_SEL_DIM_2D_MSAA', 'TCP_PERF_SEL_DIM_3D', + 'TCP_PERF_SEL_DIM_CUBE_ARRAY', 'TCP_PERF_SEL_DISPLAY_MICROTILING', + 'TCP_PERF_SEL_GATE_EN1', 'TCP_PERF_SEL_GATE_EN2', + 'TCP_PERF_SEL_HOLE_READ_STALL', + 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32', + 'TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64', + 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32', + 'TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64', + 'TCP_PERF_SEL_IMG_READ_FMT_1', + 'TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE', + 'TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE', + 'TCP_PERF_SEL_IMG_READ_FMT_16', + 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_128', + 'TCP_PERF_SEL_IMG_READ_FMT_16_AS_64', + 'TCP_PERF_SEL_IMG_READ_FMT_32', + 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_128', + 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_16', + 'TCP_PERF_SEL_IMG_READ_FMT_32_AS_8', + 'TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE', + 'TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE', + 'TCP_PERF_SEL_IMG_READ_FMT_8', + 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_32', + 'TCP_PERF_SEL_IMG_READ_FMT_8_AS_64', + 'TCP_PERF_SEL_IMG_READ_FMT_96', 'TCP_PERF_SEL_IMG_READ_FMT_BC1', + 'TCP_PERF_SEL_IMG_READ_FMT_BC2', 'TCP_PERF_SEL_IMG_READ_FMT_BC3', + 'TCP_PERF_SEL_IMG_READ_FMT_BC4', 'TCP_PERF_SEL_IMG_READ_FMT_BC5', + 'TCP_PERF_SEL_IMG_READ_FMT_BC6', 'TCP_PERF_SEL_IMG_READ_FMT_BC7', + 'TCP_PERF_SEL_IMG_READ_FMT_D16', 'TCP_PERF_SEL_IMG_READ_FMT_D32', + 'TCP_PERF_SEL_IMG_READ_FMT_D8', + 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_R', + 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG', + 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB', + 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA', + 'TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1', + 'TCP_PERF_SEL_IMG_READ_FMT_I16', 'TCP_PERF_SEL_IMG_READ_FMT_I32', + 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16', + 'TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8', + 'TCP_PERF_SEL_IMG_READ_FMT_I8', 'TCP_PERF_SEL_IMG_WRITE_FMT_128', + 'TCP_PERF_SEL_IMG_WRITE_FMT_16', + 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128', + 'TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64', + 'TCP_PERF_SEL_IMG_WRITE_FMT_32', 'TCP_PERF_SEL_IMG_WRITE_FMT_64', + 'TCP_PERF_SEL_IMG_WRITE_FMT_8', + 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32', + 'TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64', + 'TCP_PERF_SEL_IMG_WRITE_FMT_D16', + 'TCP_PERF_SEL_IMG_WRITE_FMT_D32', 'TCP_PERF_SEL_IMG_WRITE_FMT_D8', + 'TCP_PERF_SEL_LFIFO_STALL_CYCLES', + 'TCP_PERF_SEL_LOD_STALL_CYCLES', + 'TCP_PERF_SEL_PENDING_STALL_CYCLES', 'TCP_PERF_SEL_POWER_STALL', + 'TCP_PERF_SEL_READCONFLICT_STALL_CYCLES', + 'TCP_PERF_SEL_READFIFO_STALL_CYCLES', + 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES', + 'TCP_PERF_SEL_RESERVED_154', 'TCP_PERF_SEL_RFIFO_STALL_CYCLES', + 'TCP_PERF_SEL_ROTATED_MICROTILING', 'TCP_PERF_SEL_SHOOTDOWN', + 'TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL', 'TCP_PERF_SEL_TAGRAM0_REQ', + 'TCP_PERF_SEL_TAGRAM1_REQ', 'TCP_PERF_SEL_TAGRAM2_REQ', + 'TCP_PERF_SEL_TAGRAM3_REQ', + 'TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES', + 'TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES', + 'TCP_PERF_SEL_TA_TCP_STATE_READ', 'TCP_PERF_SEL_TCC_ATOMIC_REQ', + 'TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ', + 'TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ', + 'TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ', + 'TCP_PERF_SEL_TCC_BYPASS_READ_REQ', + 'TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ', + 'TCP_PERF_SEL_TCC_CC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_CC_READ_REQ', + 'TCP_PERF_SEL_TCC_CC_WRITE_REQ', 'TCP_PERF_SEL_TCC_DATA_BUS_BUSY', + 'TCP_PERF_SEL_TCC_DCC_REQ', 'TCP_PERF_SEL_TCC_LRU_REQ', + 'TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ', + 'TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ', + 'TCP_PERF_SEL_TCC_NC_ATOMIC_REQ', 'TCP_PERF_SEL_TCC_NC_READ_REQ', + 'TCP_PERF_SEL_TCC_NC_WRITE_REQ', 'TCP_PERF_SEL_TCC_NON_READ_REQ', + 'TCP_PERF_SEL_TCC_PHYSICAL_REQ', 'TCP_PERF_SEL_TCC_READ_REQ', + 'TCP_PERF_SEL_TCC_READ_REQ_LATENCY', 'TCP_PERF_SEL_TCC_REQ', + 'TCP_PERF_SEL_TCC_STREAM_REQ', 'TCP_PERF_SEL_TCC_UC_ATOMIC_REQ', + 'TCP_PERF_SEL_TCC_UC_READ_REQ', 'TCP_PERF_SEL_TCC_UC_WRITE_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_READ_REQ', + 'TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ', + 'TCP_PERF_SEL_TCC_WRITE_REQ', + 'TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY', + 'TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY', 'TCP_PERF_SEL_TCP_LATENCY', + 'TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES', + 'TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES', + 'TCP_PERF_SEL_TCR_RDRET_STALL', + 'TCP_PERF_SEL_TCR_TCP_STALL_CYCLES', + 'TCP_PERF_SEL_TC_TA_XNACK_STALL', + 'TCP_PERF_SEL_TD_TCP_STALL_CYCLES', + 'TCP_PERF_SEL_THICK_MICROTILING', 'TCP_PERF_SEL_THIN_MICROTILING', + 'TCP_PERF_SEL_TOTAL_ACCESSES', + 'TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET', + 'TCP_PERF_SEL_TOTAL_GLOBAL_READ', + 'TCP_PERF_SEL_TOTAL_GLOBAL_WRITE', + 'TCP_PERF_SEL_TOTAL_HIT_EVICT_READ', + 'TCP_PERF_SEL_TOTAL_HIT_LRU_READ', + 'TCP_PERF_SEL_TOTAL_LOCAL_READ', 'TCP_PERF_SEL_TOTAL_LOCAL_WRITE', + 'TCP_PERF_SEL_TOTAL_MISS_EVICT_READ', + 'TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE', + 'TCP_PERF_SEL_TOTAL_MISS_LRU_READ', + 'TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE', + 'TCP_PERF_SEL_TOTAL_NON_READ', 'TCP_PERF_SEL_TOTAL_READ', + 'TCP_PERF_SEL_TOTAL_WBINVL1', 'TCP_PERF_SEL_TOTAL_WBINVL1_VOL', + 'TCP_PERF_SEL_TOTAL_WRITE', + 'TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES', + 'TCP_PERF_SEL_UNALIGNED', 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', + 'TCP_PERF_SEL_UTCL1_LFIFO_FULL', + 'TCP_PERF_SEL_UTCL1_PERMISSION_MISS', + 'TCP_PERF_SEL_UTCL1_REQUEST', + 'TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL', + 'TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX', + 'TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES', + 'TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT', + 'TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL', + 'TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS', + 'TCP_PERF_SEL_UTCL1_TRANSLATION_MISS', + 'TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT', 'TCP_PERF_SEL_VOLATILE', + 'TCP_PERF_SEL_WRITE_CONFLICT_STALL', + 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES', 'TCP_WATCH_MODES', + 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', + 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', + 'TC_CHUB_REQ_CREDITS', 'TC_CHUB_REQ_CREDITS_ENUM', 'TC_EA_CID', + 'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', + 'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', + 'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', + 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', + 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', + 'TC_MICRO_TILE_MODE', 'TC_NACKS', 'TC_NACK_DATA_ERROR', + 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', + 'TC_NACK_PROTECTION_FAULT', 'TC_ONLY', 'TC_OP', + 'TC_OP_ATOMIC_ADD_32', 'TC_OP_ATOMIC_ADD_64', + 'TC_OP_ATOMIC_ADD_RTN_32', 'TC_OP_ATOMIC_ADD_RTN_64', + 'TC_OP_ATOMIC_AND_32', 'TC_OP_ATOMIC_AND_64', + 'TC_OP_ATOMIC_AND_RTN_32', 'TC_OP_ATOMIC_AND_RTN_64', + 'TC_OP_ATOMIC_CMPSWAP_32', 'TC_OP_ATOMIC_CMPSWAP_64', + 'TC_OP_ATOMIC_CMPSWAP_RTN_32', 'TC_OP_ATOMIC_CMPSWAP_RTN_64', + 'TC_OP_ATOMIC_DEC_32', 'TC_OP_ATOMIC_DEC_64', + 'TC_OP_ATOMIC_DEC_RTN_32', 'TC_OP_ATOMIC_DEC_RTN_64', + 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', + 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', + 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', + 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', + 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', + 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', + 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', + 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', + 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', + 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', + 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', + 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', + 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', + 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', + 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', + 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', + 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', + 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', + 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', + 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', + 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', + 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', + 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', + 'TC_OP_READ', 'TC_OP_RESERVED_FOP_32_0', + 'TC_OP_RESERVED_FOP_32_1', 'TC_OP_RESERVED_FOP_32_2', + 'TC_OP_RESERVED_FOP_64_0', 'TC_OP_RESERVED_FOP_64_1', + 'TC_OP_RESERVED_FOP_64_2', 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_1', + 'TC_OP_RESERVED_FOP_RTN_32_2', 'TC_OP_RESERVED_FOP_RTN_64_0', + 'TC_OP_RESERVED_FOP_RTN_64_1', 'TC_OP_RESERVED_FOP_RTN_64_2', + 'TC_OP_RESERVED_NON_FLOAT_32_1', 'TC_OP_RESERVED_NON_FLOAT_32_2', + 'TC_OP_RESERVED_NON_FLOAT_32_3', 'TC_OP_RESERVED_NON_FLOAT_32_4', + 'TC_OP_RESERVED_NON_FLOAT_64_1', 'TC_OP_RESERVED_NON_FLOAT_64_2', + 'TC_OP_RESERVED_NON_FLOAT_64_3', 'TC_OP_RESERVED_NON_FLOAT_64_4', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', + 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', + 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', + 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', + 'TD_PERF_SEL_RESERVED_14', 'TD_PERF_SEL_RESERVED_18', + 'TD_PERF_SEL_RESERVED_19', 'TD_PERF_SEL_RESERVED_39', + 'TD_PERF_SEL_RESERVED_43', 'TD_PERF_SEL_RESERVED_44', + 'TD_PERF_SEL_addresscmd_poison', 'TD_PERF_SEL_atomic_wavefront', + 'TD_PERF_SEL_bypass_filter_wavefront', + 'TD_PERF_SEL_coalescable_wavefront', + 'TD_PERF_SEL_coalesced_phase', 'TD_PERF_SEL_constant_state_full', + 'TD_PERF_SEL_consume_gds_traffic', 'TD_PERF_SEL_d16_data_packed', + 'TD_PERF_SEL_d16_en_wavefront', 'TD_PERF_SEL_data_poison', + 'TD_PERF_SEL_eight_phase_wavefront', + 'TD_PERF_SEL_four_phase_forward_wavefront', + 'TD_PERF_SEL_four_phase_wavefront', + 'TD_PERF_SEL_gather4_wavefront', + 'TD_PERF_SEL_gather4h_packed_wavefront', + 'TD_PERF_SEL_gather4h_wavefront', + 'TD_PERF_SEL_gather8h_packed_wavefront', 'TD_PERF_SEL_gds_stall', + 'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_ldfptr_wavefront', + 'TD_PERF_SEL_lerp_busy', 'TD_PERF_SEL_load_wavefront', + 'TD_PERF_SEL_local_cg_dyn_sclk_grp0_en', + 'TD_PERF_SEL_local_cg_dyn_sclk_grp1_en', + 'TD_PERF_SEL_local_cg_dyn_sclk_grp4_en', + 'TD_PERF_SEL_local_cg_dyn_sclk_grp5_en', + 'TD_PERF_SEL_min_max_filter_wavefront', 'TD_PERF_SEL_nack', + 'TD_PERF_SEL_none', 'TD_PERF_SEL_null_cycle_output', + 'TD_PERF_SEL_opaque_black_border', 'TD_PERF_SEL_output_busy', + 'TD_PERF_SEL_output_fifo_full', 'TD_PERF_SEL_pc_stall', + 'TD_PERF_SEL_reg_sclk_vld', 'TD_PERF_SEL_sample_c_wavefront', + 'TD_PERF_SEL_sample_state_full', + 'TD_PERF_SEL_sixteen_phase_wavefront', + 'TD_PERF_SEL_start_cycle_0', 'TD_PERF_SEL_start_cycle_1', + 'TD_PERF_SEL_start_cycle_2', 'TD_PERF_SEL_start_cycle_3', + 'TD_PERF_SEL_store_wavefront', 'TD_PERF_SEL_tc_stall', + 'TD_PERF_SEL_tc_td_fifo_full', 'TD_PERF_SEL_td_busy', + 'TD_PERF_SEL_td_sp_traffic', + 'TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt', + 'TD_PERF_SEL_user_defined_border', 'TD_PERF_SEL_white_border', + 'TD_PERF_SEL_write_ack_wavefront', 'TESS_ISOLINE', 'TESS_QUAD', + 'TESS_TRIANGLE', 'TEX_BORDER_COLOR_TYPE', + 'TEX_BorderColor_OpaqueBlack', 'TEX_BorderColor_OpaqueWhite', + 'TEX_BorderColor_Register', 'TEX_BorderColor_TransparentBlack', + 'TEX_CHROMA_KEY', 'TEX_CLAMP', 'TEX_COORD_TYPE', + 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', + 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', + 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', + 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', + 'TEX_Clamp_MirrorOnceHalfToBorder', + 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', + 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', + 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', + 'TEX_DIM', 'TEX_DepthCompareFunction_Always', + 'TEX_DepthCompareFunction_Equal', + 'TEX_DepthCompareFunction_Greater', + 'TEX_DepthCompareFunction_GreaterEqual', + 'TEX_DepthCompareFunction_Less', + 'TEX_DepthCompareFunction_LessEqual', + 'TEX_DepthCompareFunction_Never', + 'TEX_DepthCompareFunction_NotEqual', 'TEX_Dim_1D', + 'TEX_Dim_1DArray', 'TEX_Dim_2D', 'TEX_Dim_2DArray', + 'TEX_Dim_2DArray_MSAA', 'TEX_Dim_2D_MSAA', 'TEX_Dim_3D', + 'TEX_Dim_CubeMap', 'TEX_FORMAT_COMP', 'TEX_FormatComp_RESERVED_3', + 'TEX_FormatComp_Signed', 'TEX_FormatComp_Unsigned', + 'TEX_FormatComp_UnsignedBiased', 'TEX_MAX_ANISO_RATIO', + 'TEX_MIP_FILTER', 'TEX_MaxAnisoRatio_16to1', + 'TEX_MaxAnisoRatio_1to1', 'TEX_MaxAnisoRatio_2to1', + 'TEX_MaxAnisoRatio_4to1', 'TEX_MaxAnisoRatio_8to1', + 'TEX_MaxAnisoRatio_RESERVED_5', 'TEX_MaxAnisoRatio_RESERVED_6', + 'TEX_MaxAnisoRatio_RESERVED_7', 'TEX_MipFilter_Linear', + 'TEX_MipFilter_None', 'TEX_MipFilter_Point', + 'TEX_MipFilter_Point_Aniso_Adj', 'TEX_REQUEST_SIZE', + 'TEX_RequestSize_128B', 'TEX_RequestSize_2X64B', + 'TEX_RequestSize_32B', 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', + 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', + 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', + 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', + 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', + 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', + 'THREAD_TRACE_FINISH', 'THREAD_TRACE_FLUSH', + 'THREAD_TRACE_MARKER', 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', + 'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP', + 'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', + 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', + 'TMDS_CTL0_DATA_MODULATION_BIT1', + 'TMDS_CTL0_DATA_MODULATION_BIT2', + 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', + 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', + 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', + 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', + 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', + 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', + 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', + 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', + 'TMDS_CTL1_DATA_MODULATION_BIT0', + 'TMDS_CTL1_DATA_MODULATION_BIT1', + 'TMDS_CTL1_DATA_MODULATION_BIT2', + 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', + 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', + 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', + 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', + 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', + 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', + 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', + 'TMDS_CTL2_DATA_MODULATION_BIT0', + 'TMDS_CTL2_DATA_MODULATION_BIT1', + 'TMDS_CTL2_DATA_MODULATION_BIT2', + 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', + 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', + 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', + 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', + 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', + 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', + 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', + 'TMDS_CTL3_DATA_MODULATION_BIT0', + 'TMDS_CTL3_DATA_MODULATION_BIT1', + 'TMDS_CTL3_DATA_MODULATION_BIT2', + 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', + 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', + 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', + 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', + 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', + 'TMDS_CTL3_PATTERN_OUT_ENABLE', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', + 'TMDS_DVO_MUX_SELECT', 'TMDS_DVO_MUX_SELECT_B', + 'TMDS_DVO_MUX_SELECT_G', 'TMDS_DVO_MUX_SELECT_R', + 'TMDS_DVO_MUX_SELECT_RESERVED', + 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', 'TMDS_PIXEL_ENCODING', + 'TMDS_PIXEL_ENCODING_422', 'TMDS_PIXEL_ENCODING_444_OR_420', + 'TMDS_REG_TEST_OUTPUTA_CNTLA', 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', + 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', + 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', + 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', + 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', + 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', + 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', + 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', + 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', + 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', + 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', + 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', + 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', + 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', + 'TRISTRIP', 'TVX_DATA_FORMAT', 'TVX_DST_SEL', 'TVX_DstSel_0f', + 'TVX_DstSel_1f', 'TVX_DstSel_Mask', 'TVX_DstSel_RESERVED_6', + 'TVX_DstSel_W', 'TVX_DstSel_X', 'TVX_DstSel_Y', 'TVX_DstSel_Z', + 'TVX_ENDIAN_SWAP', 'TVX_EndianSwap_8in16', 'TVX_EndianSwap_8in32', + 'TVX_EndianSwap_8in64', 'TVX_EndianSwap_None', 'TVX_FMT_1', + 'TVX_FMT_10_10_10_2', 'TVX_FMT_10_11_11', + 'TVX_FMT_10_11_11_FLOAT', 'TVX_FMT_11_11_10', + 'TVX_FMT_11_11_10_FLOAT', 'TVX_FMT_16', 'TVX_FMT_16_16', + 'TVX_FMT_16_16_16', 'TVX_FMT_16_16_16_16', + 'TVX_FMT_16_16_16_16_FLOAT', 'TVX_FMT_16_16_16_FLOAT', + 'TVX_FMT_16_16_FLOAT', 'TVX_FMT_16_FLOAT', 'TVX_FMT_1_5_5_5', + 'TVX_FMT_1_REVERSED', 'TVX_FMT_24_8', 'TVX_FMT_24_8_FLOAT', + 'TVX_FMT_2_10_10_10', 'TVX_FMT_32', 'TVX_FMT_32_32', + 'TVX_FMT_32_32_32', 'TVX_FMT_32_32_32_32', + 'TVX_FMT_32_32_32_32_FLOAT', 'TVX_FMT_32_32_32_FLOAT', + 'TVX_FMT_32_32_FLOAT', 'TVX_FMT_32_AS_8', 'TVX_FMT_32_AS_8_8', + 'TVX_FMT_32_FLOAT', 'TVX_FMT_3_3_2', 'TVX_FMT_4_4', + 'TVX_FMT_4_4_4_4', 'TVX_FMT_5_5_5_1', 'TVX_FMT_5_6_5', + 'TVX_FMT_5_9_9_9_SHAREDEXP', 'TVX_FMT_6_5_5', 'TVX_FMT_8', + 'TVX_FMT_8_24', 'TVX_FMT_8_24_FLOAT', 'TVX_FMT_8_8', + 'TVX_FMT_8_8_8', 'TVX_FMT_8_8_8_8', 'TVX_FMT_APC0', + 'TVX_FMT_APC1', 'TVX_FMT_APC2', 'TVX_FMT_APC3', 'TVX_FMT_APC4', + 'TVX_FMT_APC5', 'TVX_FMT_APC6', 'TVX_FMT_APC7', 'TVX_FMT_BC1', + 'TVX_FMT_BC2', 'TVX_FMT_BC3', 'TVX_FMT_BC4', 'TVX_FMT_BC5', + 'TVX_FMT_BG_RG', 'TVX_FMT_CTX1', 'TVX_FMT_GB_GR', + 'TVX_FMT_INVALID', 'TVX_FMT_RESERVED_33', 'TVX_FMT_RESERVED_36', + 'TVX_FMT_RESERVED_4', 'TVX_FMT_RESERVED_63', + 'TVX_FMT_X24_8_32_FLOAT', 'TVX_INST', 'TVX_Inst_Gather4', + 'TVX_Inst_Gather4_C', 'TVX_Inst_Gather4_C_O', + 'TVX_Inst_Gather4_O', 'TVX_Inst_GetBufferResInfo', + 'TVX_Inst_GetGradientsH', 'TVX_Inst_GetGradientsV', + 'TVX_Inst_GetLOD', 'TVX_Inst_GetNumberOfSamples', + 'TVX_Inst_GetTextureResInfo', 'TVX_Inst_KeepGradients', + 'TVX_Inst_LD', 'TVX_Inst_NormalVertexFetch', 'TVX_Inst_Pass', + 'TVX_Inst_RESERVED_15', 'TVX_Inst_RESERVED_2', 'TVX_Inst_Sample', + 'TVX_Inst_Sample_C', 'TVX_Inst_Sample_C_G', + 'TVX_Inst_Sample_C_G_LB', 'TVX_Inst_Sample_C_L', + 'TVX_Inst_Sample_C_LB', 'TVX_Inst_Sample_C_LZ', + 'TVX_Inst_Sample_G', 'TVX_Inst_Sample_G_LB', 'TVX_Inst_Sample_L', + 'TVX_Inst_Sample_LB', 'TVX_Inst_Sample_LZ', + 'TVX_Inst_SemanticVertexFetch', 'TVX_Inst_SetGradientsH', + 'TVX_Inst_SetGradientsV', 'TVX_Inst_SetTextureOffsets', + 'TVX_NUM_FORMAT_ALL', 'TVX_NumFormatAll_Int', + 'TVX_NumFormatAll_Norm', 'TVX_NumFormatAll_RESERVED_3', + 'TVX_NumFormatAll_Scaled', 'TVX_SRC_SEL', 'TVX_SRFModeAll_NZ', + 'TVX_SRFModeAll_ZCMO', 'TVX_SRF_MODE_ALL', 'TVX_SrcSel_0f', + 'TVX_SrcSel_1f', 'TVX_SrcSel_W', 'TVX_SrcSel_X', 'TVX_SrcSel_Y', + 'TVX_SrcSel_Z', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', + 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', + 'TVX_Type_ValidVertexBuffer', 'TileSplit', 'TileType', + 'UCONFIG_SPACE_END', 'UCONFIG_SPACE_START', 'UNDEF', + 'UNP_ADDR_SURF_MACRO_ASPECT_1', 'UNP_ADDR_SURF_MACRO_ASPECT_2', + 'UNP_ADDR_SURF_MACRO_ASPECT_4', 'UNP_ADDR_SURF_MACRO_ASPECT_8', + 'UNP_ADDR_SURF_TILE_SPLIT_128B', 'UNP_ADDR_SURF_TILE_SPLIT_1KB', + 'UNP_ADDR_SURF_TILE_SPLIT_256B', 'UNP_ADDR_SURF_TILE_SPLIT_2KB', + 'UNP_ADDR_SURF_TILE_SPLIT_4KB', 'UNP_ADDR_SURF_TILE_SPLIT_512B', + 'UNP_ADDR_SURF_TILE_SPLIT_64B', 'UNP_BUFFER_MODE', + 'UNP_BUFFER_MODE_LUMA', 'UNP_BUFFER_MODE_LUMA_CHROMA', + 'UNP_CRC_LINE_SEL', 'UNP_CRC_LINE_SEL_EVEN_ONLY', + 'UNP_CRC_LINE_SEL_ODD_EVEN', 'UNP_CRC_LINE_SEL_ODD_ONLY', + 'UNP_CRC_LINE_SEL_RESERVED', 'UNP_CRC_SOURCE_SEL', + 'UNP_CRC_SOURCE_SEL_LOWER16', 'UNP_CRC_SOURCE_SEL_LOWER32', + 'UNP_CRC_SOURCE_SEL_NP_TO_LBV', 'UNP_CRC_SOURCE_SEL_RESERVED', + 'UNP_CRC_SOURCE_SEL_UNP_TO_LBV', 'UNP_GRPH_16BPP', + 'UNP_GRPH_32BPP', 'UNP_GRPH_8BPP', + 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE', + 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0', + 'UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1', + 'UNP_GRPH_ADDR_SURF_16_BANK', 'UNP_GRPH_ADDR_SURF_2_BANK', + 'UNP_GRPH_ADDR_SURF_4_BANK', 'UNP_GRPH_ADDR_SURF_8_BANK', + 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1', + 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2', + 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4', + 'UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8', + 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_1', + 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_2', + 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_4', + 'UNP_GRPH_ADDR_SURF_BANK_WIDTH_8', 'UNP_GRPH_BANK_HEIGHT', + 'UNP_GRPH_BANK_WIDTH', 'UNP_GRPH_BLUE_CROSSBAR', + 'UNP_GRPH_BLUE_CROSSBAR_A', 'UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C', + 'UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y', 'UNP_GRPH_BLUE_CROSSBAR_R_Cr', + 'UNP_GRPH_COLOR_EXPANSION_MODE', 'UNP_GRPH_DEPTH', + 'UNP_GRPH_DISABLED', 'UNP_GRPH_DYNAMIC_EXPANSION', 'UNP_GRPH_EN', + 'UNP_GRPH_ENABLED', 'UNP_GRPH_ENDIAN_SWAP', + 'UNP_GRPH_ENDIAN_SWAP_8IN16', 'UNP_GRPH_ENDIAN_SWAP_8IN32', + 'UNP_GRPH_ENDIAN_SWAP_8IN43', 'UNP_GRPH_ENDIAN_SWAP_NONE', + 'UNP_GRPH_GREEN_CROSSBAR', 'UNP_GRPH_MACRO_TILE_ASPECT', + 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE', + 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0', + 'UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1', + 'UNP_GRPH_MODE_UPDATE_LOCKG', 'UNP_GRPH_NUM_BANKS', + 'UNP_GRPH_RED_CROSSBAR', 'UNP_GRPH_RED_CROSSBAR_A', + 'UNP_GRPH_RED_CROSSBAR_B_Cb', 'UNP_GRPH_RED_CROSSBAR_G_Y', + 'UNP_GRPH_RED_CROSSBAR_R_Cr', + 'UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE', + 'UNP_GRPH_STACK_INTERLACE_FLIP_EN', + 'UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE', + 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE', + 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0', + 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1', + 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2', + 'UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3', + 'UNP_GRPH_STEREOSYNC_FLIP_DISABLE', 'UNP_GRPH_STEREOSYNC_FLIP_EN', + 'UNP_GRPH_STEREOSYNC_FLIP_ENABLE', + 'UNP_GRPH_STEREOSYNC_FLIP_MODE', + 'UNP_GRPH_STEREOSYNC_FLIP_MODE_0', + 'UNP_GRPH_STEREOSYNC_FLIP_MODE_1', + 'UNP_GRPH_STEREOSYNC_FLIP_MODE_2', + 'UNP_GRPH_STEREOSYNC_FLIP_MODE_3', + 'UNP_GRPH_STEREOSYNC_SELECT_DIS', + 'UNP_GRPH_STEREOSYNC_SELECT_DISABLE', + 'UNP_GRPH_STEREOSYNC_SELECT_EN', + 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE', + 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0', + 'UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1', + 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK', + 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0', + 'UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1', 'UNP_GRPH_TILE_SPLIT', + 'UNP_GRPH_UPDATE_LOCK_0', 'UNP_GRPH_UPDATE_LOCK_1', + 'UNP_GRPH_ZERO_EXPANSION', 'UNP_PIXEL_DROP', 'UNP_PIXEL_DROPPING', + 'UNP_PIXEL_NO_DROP', 'UNP_ROTATION_ANGLE', 'UNP_ROTATION_ANGLE_0', + 'UNP_ROTATION_ANGLE_0m', 'UNP_ROTATION_ANGLE_180', + 'UNP_ROTATION_ANGLE_180m', 'UNP_ROTATION_ANGLE_270', + 'UNP_ROTATION_ANGLE_270m', 'UNP_ROTATION_ANGLE_90', + 'UNP_ROTATION_ANGLE_90m', 'UNP_UNP_GRPH_GREEN_CROSSBAR_A', + 'UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C', + 'UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y', + 'UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr', 'UNP_VIDEO_FORMAT', + 'UNP_VIDEO_FORMAT0', 'UNP_VIDEO_FORMAT1', + 'UNP_VIDEO_FORMAT_YUV420_YCbCr', 'UNP_VIDEO_FORMAT_YUV420_YCrCb', + 'UNP_VIDEO_FORMAT_YUV422_CbY', 'UNP_VIDEO_FORMAT_YUV422_CrY', + 'UNP_VIDEO_FORMAT_YUV422_YCb', 'UNP_VIDEO_FORMAT_YUV422_YCr', + 'UPDATE_LOCKED', 'UPDATE_UNLOCKED', 'UTCL1FaultType', + 'UTCL1RequestType', 'UTCL1_TYPE_BYPASS', 'UTCL1_TYPE_NORMAL', + 'UTCL1_TYPE_SHOOTDOWN', 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', + 'UTCL1_XNACK_RETRY', 'UTCL1_XNACK_SUCCESS', 'VC_AND_TC', + 'VC_ONLY', 'VGT_CACHE_INVALID_MODE', 'VGT_DIST_MODE', + 'VGT_DI_INDEX_SIZE', 'VGT_DI_MAJOR_MODE_SELECT', + 'VGT_DI_PRIM_TYPE', 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', + 'VGT_DMA_BUF_RING', 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', + 'VGT_DMA_PTR_UPDATE', 'VGT_DMA_SWAP_16_BIT', + 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', 'VGT_DMA_SWAP_NONE', + 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', 'VGT_FLUSH', + 'VGT_GROUP_CONV_SEL', 'VGT_GRP_2D_COPY_RECT_V0', + 'VGT_GRP_2D_COPY_RECT_V1', 'VGT_GRP_2D_COPY_RECT_V2', + 'VGT_GRP_2D_COPY_RECT_V3', 'VGT_GRP_2D_FILL_RECT', + 'VGT_GRP_2D_LINE', 'VGT_GRP_2D_RECT', 'VGT_GRP_2D_TRI', + 'VGT_GRP_3D_LINE', 'VGT_GRP_3D_LINE_ADJ', 'VGT_GRP_3D_PATCH', + 'VGT_GRP_3D_POINT', 'VGT_GRP_3D_QUAD', 'VGT_GRP_3D_RECT', + 'VGT_GRP_3D_TRI', 'VGT_GRP_3D_TRI_ADJ', 'VGT_GRP_AUTO_PRIM', + 'VGT_GRP_FAN', 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', + 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_LIST', + 'VGT_GRP_LOOP', 'VGT_GRP_POLYGON', 'VGT_GRP_PRIM_INDEX_LINE', + 'VGT_GRP_PRIM_INDEX_QUAD', 'VGT_GRP_PRIM_INDEX_TRI', + 'VGT_GRP_PRIM_ORDER', 'VGT_GRP_PRIM_TYPE', 'VGT_GRP_SINT_16', + 'VGT_GRP_SINT_32', 'VGT_GRP_STRIP', 'VGT_GRP_UINT_16', + 'VGT_GRP_UINT_32', 'VGT_GS_CUT_MODE', 'VGT_GS_MODE_TYPE', + 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', 'VGT_INDEX_32', + 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', 'VGT_OUTPATH_GS_BLOCK', + 'VGT_OUTPATH_HS_BLOCK', 'VGT_OUTPATH_PASSTHRU', + 'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT', + 'VGT_OUTPATH_TESS_EN', 'VGT_OUTPATH_VTX_REUSE', 'VGT_OUT_2D_RECT', + 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ', 'VGT_OUT_PATCH', + 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE', 'VGT_OUT_RECT_V0', + 'VGT_OUT_RECT_V1', 'VGT_OUT_RECT_V2', 'VGT_OUT_RECT_V3', + 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ', 'VGT_PERFCOUNT_SELECT', + 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM', 'VGT_RDREQ_POLICY', + 'VGT_STAGES_ES_EN', 'VGT_STAGES_GS_EN', 'VGT_STAGES_HS_EN', + 'VGT_STAGES_LS_EN', 'VGT_STAGES_VS_EN', 'VGT_STREAMOUT_RESET', + 'VGT_STREAMOUT_SYNC', 'VGT_TESS_PARTITION', 'VGT_TESS_TOPOLOGY', + 'VGT_TESS_TYPE', 'VGT_TE_PRIM_INDEX_LINE', + 'VGT_TE_PRIM_INDEX_QUAD', 'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD', + 'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE', + 'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK', + 'VMID_SZ', 'VS_PARTIAL_FLUSH', 'VS_STAGE_COPY_SHADER', + 'VS_STAGE_DS', 'VS_STAGE_REAL', 'VTX_CLAMP', + 'VTX_Clamp_ClampToNAN', 'VTX_Clamp_ClampToZero', 'VTX_FETCH_TYPE', + 'VTX_FORMAT_COMP_ALL', 'VTX_FetchType_InstanceData', + 'VTX_FetchType_NoIndexOffset', 'VTX_FetchType_RESERVED_3', + 'VTX_FetchType_VertexData', 'VTX_FormatCompAll_Signed', + 'VTX_FormatCompAll_Unsigned', 'VTX_MEM_REQUEST_SIZE', + 'VTX_MemRequestSize_32B', 'VTX_MemRequestSize_64B', + 'WD_IA_DRAW_REG_XFER', 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', + 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', + 'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO', + 'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD', + 'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE', + 'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA', + 'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX', + 'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER', + 'WD_PERFCOUNT_SELECT', 'XDMA_LOCAL_SW_MODE_SW_256B_D', + 'XDMA_LOCAL_SW_MODE_SW_64KB_D', 'XDMA_LOCAL_SW_MODE_SW_64KB_D_X', + 'XDMA_MSTR_ALPHA_POSITION_15_8', 'XDMA_MSTR_ALPHA_POSITION_23_16', + 'XDMA_MSTR_ALPHA_POSITION_31_24', 'XDMA_MSTR_ALPHA_POSITION_7_0', + 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0', + 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1', + 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2', + 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3', + 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4', + 'XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5', + 'XDMA_SLV_ALPHA_POSITION_15_8', 'XDMA_SLV_ALPHA_POSITION_23_16', + 'XDMA_SLV_ALPHA_POSITION_31_24', 'XDMA_SLV_ALPHA_POSITION_7_0', + 'XTAL_REF_CLOCK_SOURCE_SEL', 'XTAL_REF_CLOCK_SOURCE_SEL_PPLL', + 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', + 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'ZFormat', 'ZLimitSumm', + 'ZModeForce', 'ZOrder', 'ZPASS_DISABLE', 'ZPASS_DONE', + 'ZPASS_PIXELS', 'ZPASS_SAMPLES', 'ZSamplePosition', 'Z_16', + 'Z_24', 'Z_32_FLOAT', 'Z_INVALID', 'Z_SAMPLE_CENTER', + 'Z_SAMPLE_CENTROID', 'ZpassControl', '_vega10_ENUM_HEADER', + 'ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE', 'ia_perf_MC_LAT_BIN_0', + 'ia_perf_MC_LAT_BIN_1', 'ia_perf_MC_LAT_BIN_2', + 'ia_perf_MC_LAT_BIN_3', 'ia_perf_MC_LAT_BIN_4', + 'ia_perf_MC_LAT_BIN_5', 'ia_perf_MC_LAT_BIN_6', + 'ia_perf_MC_LAT_BIN_7', 'ia_perf_RESERVED1', 'ia_perf_RESERVED2', + 'ia_perf_RESERVED3', 'ia_perf_RESERVED4', 'ia_perf_RESERVED5', + 'ia_perf_RESERVED6', 'ia_perf_RESERVED7', + 'ia_perf_dma_data_fifo_full', 'ia_perf_ia_busy', + 'ia_perf_ia_dma_return', 'ia_perf_ia_sclk_core_vld_event', + 'ia_perf_ia_sclk_reg_vld_event', 'ia_perf_ia_stalled', + 'ia_perf_shift_starved_pipe0_event', + 'ia_perf_shift_starved_pipe1_event', 'vgt_perf_VGT_PA_CLIPP_EOP', + 'vgt_perf_VGT_PA_CLIPP_IS_EVENT', + 'vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT', + 'vgt_perf_VGT_PA_CLIPP_NULL_PRIM', 'vgt_perf_VGT_PA_CLIPP_SEND', + 'vgt_perf_VGT_PA_CLIPP_STALLED', + 'vgt_perf_VGT_PA_CLIPP_STARVED_BUSY', + 'vgt_perf_VGT_PA_CLIPP_STARVED_IDLE', + 'vgt_perf_VGT_PA_CLIPP_STATIC', 'vgt_perf_VGT_PA_CLIPS_SEND', + 'vgt_perf_VGT_PA_CLIPS_STALLED', + 'vgt_perf_VGT_PA_CLIPS_STARVED_BUSY', + 'vgt_perf_VGT_PA_CLIPS_STARVED_IDLE', + 'vgt_perf_VGT_PA_CLIPS_STATIC', 'vgt_perf_VGT_PA_CLIPV_FIRSTVERT', + 'vgt_perf_VGT_PA_CLIPV_SEND', 'vgt_perf_VGT_PA_CLIPV_STALLED', + 'vgt_perf_VGT_PA_CLIPV_STARVED_BUSY', + 'vgt_perf_VGT_PA_CLIPV_STARVED_IDLE', + 'vgt_perf_VGT_PA_CLIPV_STATIC', + 'vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE', + 'vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE', + 'vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT', + 'vgt_perf_VGT_SPI_ESTHREAD_SEND', 'vgt_perf_VGT_SPI_ESVERT_EOV', + 'vgt_perf_VGT_SPI_ESVERT_STALLED', + 'vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY', + 'vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE', + 'vgt_perf_VGT_SPI_ESVERT_STATIC', 'vgt_perf_VGT_SPI_ESVERT_VALID', + 'vgt_perf_VGT_SPI_GSPRIM_CONT', 'vgt_perf_VGT_SPI_GSPRIM_EOV', + 'vgt_perf_VGT_SPI_GSPRIM_STALLED', + 'vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY', + 'vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE', + 'vgt_perf_VGT_SPI_GSPRIM_STATIC', 'vgt_perf_VGT_SPI_GSPRIM_VALID', + 'vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE', + 'vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT', + 'vgt_perf_VGT_SPI_GSTHREAD_SEND', 'vgt_perf_VGT_SPI_HSVERT_EOV', + 'vgt_perf_VGT_SPI_HSVERT_STALLED', + 'vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY', + 'vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE', + 'vgt_perf_VGT_SPI_HSVERT_STATIC', 'vgt_perf_VGT_SPI_HSVERT_VALID', + 'vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE', + 'vgt_perf_VGT_SPI_HSWAVE_IS_EVENT', + 'vgt_perf_VGT_SPI_HSWAVE_SEND', 'vgt_perf_VGT_SPI_LSVERT_EOV', + 'vgt_perf_VGT_SPI_LSVERT_STALLED', + 'vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY', + 'vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE', + 'vgt_perf_VGT_SPI_LSVERT_STATIC', 'vgt_perf_VGT_SPI_LSVERT_VALID', + 'vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE', + 'vgt_perf_VGT_SPI_LSWAVE_IS_EVENT', + 'vgt_perf_VGT_SPI_LSWAVE_SEND', + 'vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE', + 'vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT', + 'vgt_perf_VGT_SPI_VSTHREAD_SEND', 'vgt_perf_VGT_SPI_VSVERT_EOV', + 'vgt_perf_VGT_SPI_VSVERT_SEND', 'vgt_perf_VGT_SPI_VSVERT_STALLED', + 'vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY', + 'vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE', + 'vgt_perf_VGT_SPI_VSVERT_STATIC', 'vgt_perf_cm_reading_stalled', + 'vgt_perf_cm_stalled_by_gog', + 'vgt_perf_cm_stalled_by_gsfetch_done', + 'vgt_perf_counters_avail_stalled', + 'vgt_perf_cut_mem_flush_stalled', 'vgt_perf_ds_RESERVED', + 'vgt_perf_ds_cache_hits', 'vgt_perf_ds_prims', 'vgt_perf_es_done', + 'vgt_perf_es_done_latency', 'vgt_perf_es_flush', + 'vgt_perf_es_ring_high_water_mark', 'vgt_perf_es_thread_groups', + 'vgt_perf_esthread_stalled_es_rb_full', + 'vgt_perf_esthread_stalled_spi_bp', + 'vgt_perf_esvert_stalled_es_tbl', + 'vgt_perf_esvert_stalled_gs_event', + 'vgt_perf_esvert_stalled_gs_tbl', + 'vgt_perf_esvert_stalled_gsprim', 'vgt_perf_gog_busy', + 'vgt_perf_gog_out_indx_stalled', 'vgt_perf_gog_out_prim_stalled', + 'vgt_perf_gog_vs_tbl_stalled', 'vgt_perf_gs_cache_hits', + 'vgt_perf_gs_done', 'vgt_perf_gs_done_latency', + 'vgt_perf_gs_done_received', 'vgt_perf_gs_event_stall', + 'vgt_perf_gs_issue_rtr_stalled', + 'vgt_perf_gs_rb_space_avail_stalled', + 'vgt_perf_gs_ring_high_water_mark', + 'vgt_perf_gsprim_stalled_es_tbl', + 'vgt_perf_gsprim_stalled_esvert', + 'vgt_perf_gsprim_stalled_gs_event', + 'vgt_perf_gsprim_stalled_gs_tbl', 'vgt_perf_gsthread_stalled', + 'vgt_perf_hs_done', 'vgt_perf_hs_done_latency', + 'vgt_perf_hs_flush', 'vgt_perf_hs_input_stall', + 'vgt_perf_hs_interface_stall', 'vgt_perf_hs_tfm_stall', + 'vgt_perf_hs_tgs_active_high_water_mark', + 'vgt_perf_hs_thread_groups', 'vgt_perf_hs_tif_stall', + 'vgt_perf_hs_waiting_on_ls_done_stall', 'vgt_perf_hswave_stalled', + 'vgt_perf_ls_done', 'vgt_perf_ls_done_latency', + 'vgt_perf_ls_flush', 'vgt_perf_ls_thread_groups', + 'vgt_perf_pa_clipp_dealloc', 'vgt_perf_reused_es_indices', + 'vgt_perf_reused_vs_indices', 'vgt_perf_sclk_core_vld_event', + 'vgt_perf_sclk_gs_vld_event', 'vgt_perf_sclk_reg_vld_event', + 'vgt_perf_strmout_stalled', + 'vgt_perf_te11_con_starved_after_work', 'vgt_perf_te11_starved', + 'vgt_perf_total_cache_hits', 'vgt_perf_vgt_busy', + 'vgt_perf_vgt_gs_busy', 'vgt_perf_vgt_hs_busy', + 'vgt_perf_vgt_pa_clipp_eopg', + 'vgt_perf_vgt_pa_clipp_send_not_event', + 'vgt_perf_vgt_pa_clipp_starved_after_work', + 'vgt_perf_vgt_pa_clipp_valid_prim', 'vgt_perf_vgt_te11_busy', + 'vgt_perf_vs_cache_hits', 'vgt_perf_vs_conflicting_indices', + 'vgt_perf_vs_table_high_water_mark', 'vgt_perf_vs_thread_groups', + 'vgt_perf_vsfetch_done', 'vgt_perf_vsvert_api_send', + 'vgt_perf_vsvert_ds_send', 'vgt_perf_vsvert_work_received', + 'vgt_perf_wait_for_es_done_stalled', 'vgt_perf_waveid_stalled', + 'vgt_spi_vsvert_valid', 'wd_perf_RBIU_DI_FIFO_STALLED', + 'wd_perf_RBIU_DI_FIFO_STARVED', 'wd_perf_RBIU_DR_FIFO_STALLED', + 'wd_perf_RBIU_DR_FIFO_STARVED', + 'wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE', 'wd_perf_hs_done_se0', + 'wd_perf_hs_done_se1', 'wd_perf_hs_done_se2', + 'wd_perf_hs_done_se3', 'wd_perf_inside_tf_bin_0', + 'wd_perf_inside_tf_bin_1', 'wd_perf_inside_tf_bin_2', + 'wd_perf_inside_tf_bin_3', 'wd_perf_inside_tf_bin_4', + 'wd_perf_inside_tf_bin_5', 'wd_perf_inside_tf_bin_6', + 'wd_perf_inside_tf_bin_7', 'wd_perf_inside_tf_bin_8', + 'wd_perf_null_patches', 'wd_perf_se0_hs_done_latency', + 'wd_perf_se1_hs_done_latency', 'wd_perf_se2_hs_done_latency', + 'wd_perf_se3_hs_done_latency', 'wd_perf_tfreq_lat_bin_0', + 'wd_perf_tfreq_lat_bin_1', 'wd_perf_tfreq_lat_bin_2', + 'wd_perf_tfreq_lat_bin_3', 'wd_perf_tfreq_lat_bin_4', + 'wd_perf_tfreq_lat_bin_5', 'wd_perf_tfreq_lat_bin_6', + 'wd_perf_tfreq_lat_bin_7', 'wd_perf_wd_busy', + 'wd_perf_wd_sclk_core_vld_event', + 'wd_perf_wd_sclk_input_vld_event', + 'wd_perf_wd_sclk_reg_vld_event', 'wd_perf_wd_stalled', + 'wd_starved_on_hs_done'] diff --git a/tinygrad_repo/tinygrad/runtime/autogen/amd_gpu.py b/tinygrad_repo/tinygrad/runtime/autogen/amd_gpu.py index 5ced4e01f..9ea5e6d9f 100644 --- a/tinygrad_repo/tinygrad/runtime/autogen/amd_gpu.py +++ b/tinygrad_repo/tinygrad/runtime/autogen/amd_gpu.py @@ -120,17 +120,17 @@ class Union(ctypes.Union, AsDictMixin): HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_ = True # macro -SDMA_OP_COPY = 1 # Variable ctypes.c_uint32 -SDMA_OP_FENCE = 5 # Variable ctypes.c_uint32 -SDMA_OP_TRAP = 6 # Variable ctypes.c_uint32 -SDMA_OP_POLL_REGMEM = 8 # Variable ctypes.c_uint32 -SDMA_OP_ATOMIC = 10 # Variable ctypes.c_uint32 -SDMA_OP_CONST_FILL = 11 # Variable ctypes.c_uint32 -SDMA_OP_TIMESTAMP = 13 # Variable ctypes.c_uint32 +SDMA_OP_COPY = 1 # macro +SDMA_OP_FENCE = 5 # macro +SDMA_OP_TRAP = 6 # macro +SDMA_OP_POLL_REGMEM = 8 # macro +SDMA_OP_ATOMIC = 10 # macro +SDMA_OP_CONST_FILL = 11 # macro +SDMA_OP_TIMESTAMP = 13 # macro SDMA_OP_GCR = 17 # Variable ctypes.c_uint32 -SDMA_SUBOP_COPY_LINEAR = 0 # Variable ctypes.c_uint32 +SDMA_SUBOP_COPY_LINEAR = 0 # macro SDMA_SUBOP_COPY_LINEAR_RECT = 4 # Variable ctypes.c_uint32 -SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # Variable ctypes.c_uint32 +SDMA_SUBOP_TIMESTAMP_GET_GLOBAL = 2 # macro SDMA_SUBOP_USER_GCR = 1 # Variable ctypes.c_uint32 SDMA_ATOMIC_ADD64 = 47 # Variable ctypes.c_uint32 class struct_SDMA_PKT_COPY_LINEAR_TAG(Structure): @@ -1638,6 +1638,35015 @@ PACKET3_SET_Q_PREEMPTION_MODE = 0xF0 # macro def PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x): # macro return ((x)<<0) PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM = (1<<0) # macro +F32_MES_PM4_PACKETS_H = True # macro +uint32_t = True # macro +int32_t = True # macro +PM4_MES_HEADER_DEFINED = True # macro +PM4_MEC_RELEASE_MEM_DEFINED = True # macro +PM4_MEC_WRITE_DATA_DEFINED = True # macro +class union_PM4_MES_TYPE_3_HEADER(Union): + pass + +class struct_PM4_MES_TYPE_3_HEADER_0(Structure): + pass + +struct_PM4_MES_TYPE_3_HEADER_0._pack_ = 1 # source:False +struct_PM4_MES_TYPE_3_HEADER_0._fields_ = [ + ('reserved1', ctypes.c_uint32, 8), + ('opcode', ctypes.c_uint32, 8), + ('count', ctypes.c_uint32, 14), + ('type', ctypes.c_uint32, 2), +] + +union_PM4_MES_TYPE_3_HEADER._pack_ = 1 # source:False +union_PM4_MES_TYPE_3_HEADER._anonymous_ = ('_0',) +union_PM4_MES_TYPE_3_HEADER._fields_ = [ + ('_0', struct_PM4_MES_TYPE_3_HEADER_0), + ('u32All', ctypes.c_uint32), +] + + +# values for enumeration 'c_uint32' +c_uint32__enumvalues = { + 5: 'event_index__mec_release_mem__end_of_pipe', + 6: 'event_index__mec_release_mem__shader_done', +} +event_index__mec_release_mem__end_of_pipe = 5 +event_index__mec_release_mem__shader_done = 6 +c_uint32 = ctypes.c_uint32 # enum + +# values for enumeration 'c_uint32' +c_uint32__enumvalues = { + 0: 'cache_policy__mec_release_mem__lru', + 1: 'cache_policy__mec_release_mem__stream', +} +cache_policy__mec_release_mem__lru = 0 +cache_policy__mec_release_mem__stream = 1 +c_uint32 = ctypes.c_uint32 # enum + +# values for enumeration 'c_uint32' +c_uint32__enumvalues = { + 0: 'pq_exe_status__mec_release_mem__default', + 1: 'pq_exe_status__mec_release_mem__phase_update', +} +pq_exe_status__mec_release_mem__default = 0 +pq_exe_status__mec_release_mem__phase_update = 1 +c_uint32 = ctypes.c_uint32 # enum + +# values for enumeration 'c_uint32' +c_uint32__enumvalues = { + 0: 'dst_sel__mec_release_mem__memory_controller', + 1: 'dst_sel__mec_release_mem__tc_l2', + 2: 'dst_sel__mec_release_mem__queue_write_pointer_register', + 3: 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', +} +dst_sel__mec_release_mem__memory_controller = 0 +dst_sel__mec_release_mem__tc_l2 = 1 +dst_sel__mec_release_mem__queue_write_pointer_register = 2 +dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit = 3 +c_uint32 = ctypes.c_uint32 # enum + +# values for enumeration 'c_uint32' +c_uint32__enumvalues = { + 0: 'int_sel__mec_release_mem__none', + 1: 'int_sel__mec_release_mem__send_interrupt_only', + 2: 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', + 3: 'int_sel__mec_release_mem__send_data_after_write_confirm', + 4: 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', + 5: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', + 6: 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', +} +int_sel__mec_release_mem__none = 0 +int_sel__mec_release_mem__send_interrupt_only = 1 +int_sel__mec_release_mem__send_interrupt_after_write_confirm = 2 +int_sel__mec_release_mem__send_data_after_write_confirm = 3 +int_sel__mec_release_mem__unconditionally_send_int_ctxid = 4 +int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare = 5 +int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare = 6 +c_uint32 = ctypes.c_uint32 # enum + +# values for enumeration 'c_uint32' +c_uint32__enumvalues = { + 0: 'data_sel__mec_release_mem__none', + 1: 'data_sel__mec_release_mem__send_32_bit_low', + 2: 'data_sel__mec_release_mem__send_64_bit_data', + 3: 'data_sel__mec_release_mem__send_gpu_clock_counter', + 4: 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', + 5: 'data_sel__mec_release_mem__store_gds_data_to_memory', +} +data_sel__mec_release_mem__none = 0 +data_sel__mec_release_mem__send_32_bit_low = 1 +data_sel__mec_release_mem__send_64_bit_data = 2 +data_sel__mec_release_mem__send_gpu_clock_counter = 3 +data_sel__mec_release_mem__send_cp_perfcounter_hi_lo = 4 +data_sel__mec_release_mem__store_gds_data_to_memory = 5 +c_uint32 = ctypes.c_uint32 # enum +class struct_pm4_mec_release_mem(Structure): + pass + +class union_pm4_mec_release_mem_0(Union): + pass + +union_pm4_mec_release_mem_0._pack_ = 1 # source:False +union_pm4_mec_release_mem_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', ctypes.c_uint32), +] + +class union_pm4_mec_release_mem_1(Union): + pass + +class struct_pm4_mec_release_mem_1_bitfields2(Structure): + pass + +struct_pm4_mec_release_mem_1_bitfields2._pack_ = 1 # source:False +struct_pm4_mec_release_mem_1_bitfields2._fields_ = [ + ('event_type', ctypes.c_uint32, 6), + ('reserved1', ctypes.c_uint32, 2), + ('event_index', c_uint32, 4), + ('tcl1_vol_action_ena', ctypes.c_uint32, 1), + ('tc_vol_action_ena', ctypes.c_uint32, 1), + ('reserved2', ctypes.c_uint32, 1), + ('tc_wb_action_ena', ctypes.c_uint32, 1), + ('tcl1_action_ena', ctypes.c_uint32, 1), + ('tc_action_ena', ctypes.c_uint32, 1), + ('reserved3', ctypes.c_uint32, 1), + ('tc_nc_action_ena', ctypes.c_uint32, 1), + ('tc_wc_action_ena', ctypes.c_uint32, 1), + ('tc_md_action_ena', ctypes.c_uint32, 1), + ('reserved4', ctypes.c_uint32, 3), + ('cache_policy', c_uint32, 2), + ('reserved5', ctypes.c_uint32, 2), + ('pq_exe_status', c_uint32, 1), + ('reserved6', ctypes.c_uint32, 2), +] + +union_pm4_mec_release_mem_1._pack_ = 1 # source:False +union_pm4_mec_release_mem_1._fields_ = [ + ('bitfields2', struct_pm4_mec_release_mem_1_bitfields2), + ('ordinal2', ctypes.c_uint32), +] + +class union_pm4_mec_release_mem_2(Union): + pass + +class struct_pm4_mec_release_mem_2_bitfields3(Structure): + pass + +struct_pm4_mec_release_mem_2_bitfields3._pack_ = 1 # source:False +struct_pm4_mec_release_mem_2_bitfields3._fields_ = [ + ('reserved7', ctypes.c_uint32, 16), + ('dst_sel', c_uint32, 2), + ('reserved8', ctypes.c_uint32, 6), + ('int_sel', c_uint32, 3), + ('reserved9', ctypes.c_uint32, 2), + ('data_sel', c_uint32, 3), +] + +union_pm4_mec_release_mem_2._pack_ = 1 # source:False +union_pm4_mec_release_mem_2._fields_ = [ + ('bitfields3', struct_pm4_mec_release_mem_2_bitfields3), + ('ordinal3', ctypes.c_uint32), +] + +class union_pm4_mec_release_mem_3(Union): + pass + +class struct_pm4_mec_release_mem_3_bitfields4(Structure): + pass + +struct_pm4_mec_release_mem_3_bitfields4._pack_ = 1 # source:False +struct_pm4_mec_release_mem_3_bitfields4._fields_ = [ + ('reserved10', ctypes.c_uint32, 2), + ('address_lo_32b', ctypes.c_uint32, 30), +] + +class struct_pm4_mec_release_mem_3_bitfields4b(Structure): + pass + +struct_pm4_mec_release_mem_3_bitfields4b._pack_ = 1 # source:False +struct_pm4_mec_release_mem_3_bitfields4b._fields_ = [ + ('reserved11', ctypes.c_uint32, 3), + ('address_lo_64b', ctypes.c_uint32, 29), +] + +union_pm4_mec_release_mem_3._pack_ = 1 # source:False +union_pm4_mec_release_mem_3._fields_ = [ + ('bitfields4', struct_pm4_mec_release_mem_3_bitfields4), + ('bitfields4b', struct_pm4_mec_release_mem_3_bitfields4b), + ('reserved12', ctypes.c_uint32), + ('ordinal4', ctypes.c_uint32), +] + +class union_pm4_mec_release_mem_4(Union): + pass + +union_pm4_mec_release_mem_4._pack_ = 1 # source:False +union_pm4_mec_release_mem_4._fields_ = [ + ('address_hi', ctypes.c_uint32), + ('reserved13', ctypes.c_uint32), + ('ordinal5', ctypes.c_uint32), +] + +class union_pm4_mec_release_mem_5(Union): + pass + +class struct_pm4_mec_release_mem_5_bitfields6c(Structure): + pass + +struct_pm4_mec_release_mem_5_bitfields6c._pack_ = 1 # source:False +struct_pm4_mec_release_mem_5_bitfields6c._fields_ = [ + ('dw_offset', ctypes.c_uint32, 16), + ('num_dwords', ctypes.c_uint32, 16), +] + +union_pm4_mec_release_mem_5._pack_ = 1 # source:False +union_pm4_mec_release_mem_5._fields_ = [ + ('data_lo', ctypes.c_uint32), + ('cmp_data_lo', ctypes.c_uint32), + ('bitfields6c', struct_pm4_mec_release_mem_5_bitfields6c), + ('reserved14', ctypes.c_uint32), + ('ordinal6', ctypes.c_uint32), +] + +class union_pm4_mec_release_mem_6(Union): + pass + +union_pm4_mec_release_mem_6._pack_ = 1 # source:False +union_pm4_mec_release_mem_6._fields_ = [ + ('data_hi', ctypes.c_uint32), + ('cmp_data_hi', ctypes.c_uint32), + ('reserved15', ctypes.c_uint32), + ('reserved16', ctypes.c_uint32), + ('ordinal7', ctypes.c_uint32), +] + +struct_pm4_mec_release_mem._pack_ = 1 # source:False +struct_pm4_mec_release_mem._anonymous_ = ('_0', '_1', '_2', '_3', '_4', '_5', '_6',) +struct_pm4_mec_release_mem._fields_ = [ + ('_0', union_pm4_mec_release_mem_0), + ('_1', union_pm4_mec_release_mem_1), + ('_2', union_pm4_mec_release_mem_2), + ('_3', union_pm4_mec_release_mem_3), + ('_4', union_pm4_mec_release_mem_4), + ('_5', union_pm4_mec_release_mem_5), + ('_6', union_pm4_mec_release_mem_6), + ('int_ctxid', ctypes.c_uint32), +] + + +# values for enumeration 'WRITE_DATA_dst_sel_enum' +WRITE_DATA_dst_sel_enum__enumvalues = { + 0: 'dst_sel___write_data__mem_mapped_register', + 2: 'dst_sel___write_data__tc_l2', + 3: 'dst_sel___write_data__gds', + 5: 'dst_sel___write_data__memory', + 6: 'dst_sel___write_data__memory_mapped_adc_persistent_state', +} +dst_sel___write_data__mem_mapped_register = 0 +dst_sel___write_data__tc_l2 = 2 +dst_sel___write_data__gds = 3 +dst_sel___write_data__memory = 5 +dst_sel___write_data__memory_mapped_adc_persistent_state = 6 +WRITE_DATA_dst_sel_enum = ctypes.c_uint32 # enum + +# values for enumeration 'WRITE_DATA_addr_incr_enum' +WRITE_DATA_addr_incr_enum__enumvalues = { + 0: 'addr_incr___write_data__increment_address', + 1: 'addr_incr___write_data__do_not_increment_address', +} +addr_incr___write_data__increment_address = 0 +addr_incr___write_data__do_not_increment_address = 1 +WRITE_DATA_addr_incr_enum = ctypes.c_uint32 # enum + +# values for enumeration 'WRITE_DATA_wr_confirm_enum' +WRITE_DATA_wr_confirm_enum__enumvalues = { + 0: 'wr_confirm___write_data__do_not_wait_for_write_confirmation', + 1: 'wr_confirm___write_data__wait_for_write_confirmation', +} +wr_confirm___write_data__do_not_wait_for_write_confirmation = 0 +wr_confirm___write_data__wait_for_write_confirmation = 1 +WRITE_DATA_wr_confirm_enum = ctypes.c_uint32 # enum + +# values for enumeration 'WRITE_DATA_cache_policy_enum' +WRITE_DATA_cache_policy_enum__enumvalues = { + 0: 'cache_policy___write_data__lru', + 1: 'cache_policy___write_data__stream', +} +cache_policy___write_data__lru = 0 +cache_policy___write_data__stream = 1 +WRITE_DATA_cache_policy_enum = ctypes.c_uint32 # enum +class struct_pm4_mec_write_data_mmio(Structure): + pass + +class union_pm4_mec_write_data_mmio_0(Union): + pass + +union_pm4_mec_write_data_mmio_0._pack_ = 1 # source:False +union_pm4_mec_write_data_mmio_0._fields_ = [ + ('header', union_PM4_MES_TYPE_3_HEADER), + ('ordinal1', ctypes.c_uint32), +] + +class union_pm4_mec_write_data_mmio_1(Union): + pass + +class struct_pm4_mec_write_data_mmio_1_bitfields2(Structure): + pass + +struct_pm4_mec_write_data_mmio_1_bitfields2._pack_ = 1 # source:False +struct_pm4_mec_write_data_mmio_1_bitfields2._fields_ = [ + ('reserved1', ctypes.c_uint32, 8), + ('dst_sel', ctypes.c_uint32, 4), + ('reserved2', ctypes.c_uint32, 4), + ('addr_incr', ctypes.c_uint32, 1), + ('reserved3', ctypes.c_uint32, 2), + ('resume_vf', ctypes.c_uint32, 1), + ('wr_confirm', ctypes.c_uint32, 1), + ('reserved4', ctypes.c_uint32, 4), + ('cache_policy', ctypes.c_uint32, 2), + ('reserved5', ctypes.c_uint32, 5), +] + +union_pm4_mec_write_data_mmio_1._pack_ = 1 # source:False +union_pm4_mec_write_data_mmio_1._fields_ = [ + ('bitfields2', struct_pm4_mec_write_data_mmio_1_bitfields2), + ('ordinal2', ctypes.c_uint32), +] + +class union_pm4_mec_write_data_mmio_2(Union): + pass + +class struct_pm4_mec_write_data_mmio_2_bitfields3(Structure): + pass + +struct_pm4_mec_write_data_mmio_2_bitfields3._pack_ = 1 # source:False +struct_pm4_mec_write_data_mmio_2_bitfields3._fields_ = [ + ('dst_mmreg_addr', ctypes.c_uint32, 18), + ('reserved6', ctypes.c_uint32, 14), +] + +union_pm4_mec_write_data_mmio_2._pack_ = 1 # source:False +union_pm4_mec_write_data_mmio_2._fields_ = [ + ('bitfields3', struct_pm4_mec_write_data_mmio_2_bitfields3), + ('ordinal3', ctypes.c_uint32), +] + +struct_pm4_mec_write_data_mmio._pack_ = 1 # source:False +struct_pm4_mec_write_data_mmio._anonymous_ = ('_0', '_1', '_2',) +struct_pm4_mec_write_data_mmio._fields_ = [ + ('_0', union_pm4_mec_write_data_mmio_0), + ('_1', union_pm4_mec_write_data_mmio_1), + ('_2', union_pm4_mec_write_data_mmio_2), + ('reserved7', ctypes.c_uint32), + ('data', ctypes.c_uint32), +] + + +# values for enumeration 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT' +c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT__enumvalues = { + 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', +} +CACHE_FLUSH_AND_INV_TS_EVENT = 20 +c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT = ctypes.c_uint32 # enum +_soc21_ENUM_HEADER = True # macro +SQ_WAVE_TYPE_PS0 = 0x00000000 # macro +SQIND_GLOBAL_REGS_OFFSET = 0x00000000 # macro +SQIND_GLOBAL_REGS_SIZE = 0x00000008 # macro +SQIND_LOCAL_REGS_OFFSET = 0x00000008 # macro +SQIND_LOCAL_REGS_SIZE = 0x00000008 # macro +SQIND_WAVE_HWREGS_OFFSET = 0x00000100 # macro +SQIND_WAVE_HWREGS_SIZE = 0x00000100 # macro +SQIND_WAVE_SGPRS_OFFSET = 0x00000200 # macro +SQIND_WAVE_SGPRS_SIZE = 0x00000200 # macro +SQIND_WAVE_VGPRS_OFFSET = 0x00000400 # macro +SQIND_WAVE_VGPRS_SIZE = 0x00000400 # macro +SQ_GFXDEC_BEGIN = 0x0000a000 # macro +SQ_GFXDEC_END = 0x0000c000 # macro +SQ_GFXDEC_STATE_ID_SHIFT = 0x0000000a # macro +SQDEC_BEGIN = 0x00002300 # macro +SQDEC_END = 0x000023ff # macro +SQPERFSDEC_BEGIN = 0x0000d9c0 # macro +SQPERFSDEC_END = 0x0000da40 # macro +SQPERFDDEC_BEGIN = 0x0000d1c0 # macro +SQPERFDDEC_END = 0x0000d240 # macro +SQGFXUDEC_BEGIN = 0x0000c330 # macro +SQGFXUDEC_END = 0x0000c380 # macro +SQPWRDEC_BEGIN = 0x0000f08c # macro +SQPWRDEC_END = 0x0000f094 # macro +SQ_DISPATCHER_GFX_MIN = 0x00000010 # macro +SQ_DISPATCHER_GFX_CNT_PER_RING = 0x00000008 # macro +SQ_MAX_PGM_SGPRS = 0x00000068 # macro +SQ_MAX_PGM_VGPRS = 0x00000100 # macro +SQ_EX_MODE_EXCP_VALU_BASE = 0x00000000 # macro +SQ_EX_MODE_EXCP_VALU_SIZE = 0x00000007 # macro +SQ_EX_MODE_EXCP_INVALID = 0x00000000 # macro +SQ_EX_MODE_EXCP_INPUT_DENORM = 0x00000001 # macro +SQ_EX_MODE_EXCP_DIV0 = 0x00000002 # macro +SQ_EX_MODE_EXCP_OVERFLOW = 0x00000003 # macro +SQ_EX_MODE_EXCP_UNDERFLOW = 0x00000004 # macro +SQ_EX_MODE_EXCP_INEXACT = 0x00000005 # macro +SQ_EX_MODE_EXCP_INT_DIV0 = 0x00000006 # macro +SQ_EX_MODE_EXCP_ADDR_WATCH0 = 0x00000007 # macro +SQ_EX_MODE_EXCP_MEM_VIOL = 0x00000008 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 = 0x00000000 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 = 0x00000001 # macro +SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 = 0x00000002 # macro +INST_ID_PRIV_START = 0x80000000 # macro +INST_ID_ECC_INTERRUPT_MSG = 0xfffffff0 # macro +INST_ID_TTRACE_NEW_PC_MSG = 0xfffffff1 # macro +INST_ID_HW_TRAP = 0xfffffff2 # macro +INST_ID_KILL_SEQ = 0xfffffff3 # macro +INST_ID_SPI_WREXEC = 0xfffffff4 # macro +INST_ID_HW_TRAP_GET_TBA = 0xfffffff5 # macro +INST_ID_HOST_REG_TRAP_MSG = 0xfffffffe # macro +SIMM16_WAITCNT_EXP_CNT_START = 0x00000000 # macro +SIMM16_WAITCNT_EXP_CNT_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_LGKM_CNT_START = 0x00000004 # macro +SIMM16_WAITCNT_LGKM_CNT_SIZE = 0x00000006 # macro +SIMM16_WAITCNT_VM_CNT_START = 0x0000000a # macro +SIMM16_WAITCNT_VM_CNT_SIZE = 0x00000006 # macro +SIMM16_WAITCNT_DEPCTR_SA_SDST_START = 0x00000000 # macro +SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_VCC_START = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VM_VSRC_START = 0x00000002 # macro +SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START = 0x00000006 # macro +SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_SSRC_START = 0x00000007 # macro +SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE = 0x00000001 # macro +SIMM16_WAITCNT_DEPCTR_VA_SDST_START = 0x00000008 # macro +SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE = 0x00000003 # macro +SIMM16_WAITCNT_DEPCTR_VA_VDST_START = 0x0000000b # macro +SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE = 0x00000005 # macro +SIMM16_WAIT_EVENT_EXP_RDY_START = 0x00000000 # macro +SIMM16_WAIT_EVENT_EXP_RDY_SIZE = 0x00000001 # macro +SQ_WAVE_IB_DEP_SA_SDST_SIZE = 0x00000004 # macro +SQ_WAVE_IB_DEP_SA_EXEC_SIZE = 0x00000002 # macro +SQ_WAVE_IB_DEP_SA_M0_SIZE = 0x00000001 # macro +SQ_WAVE_IB_DEP_VM_VSRC_SIZE = 0x00000004 # macro +SQ_WAVE_IB_DEP_HOLD_CNT_SIZE = 0x00000001 # macro +SQ_WAVE_IB_DEP_VA_SSRC_SIZE = 0x00000003 # macro +SQ_WAVE_IB_DEP_VA_SDST_SIZE = 0x00000004 # macro +SQ_WAVE_IB_DEP_VA_VCC_SIZE = 0x00000003 # macro +SQ_WAVE_IB_DEP_VA_EXEC_SIZE = 0x00000002 # macro +SQ_WAVE_IB_DEP_VA_VDST_SIZE = 0x00000005 # macro +SQ_WAVE_IB_DEP_LDS_DIR_SIZE = 0x00000003 # macro +SQ_EDC_FUE_CNTL_SIMD0 = 0x00000000 # macro +SQ_EDC_FUE_CNTL_SIMD1 = 0x00000001 # macro +SQ_EDC_FUE_CNTL_SIMD2 = 0x00000002 # macro +SQ_EDC_FUE_CNTL_SIMD3 = 0x00000003 # macro +SQ_EDC_FUE_CNTL_SQ = 0x00000004 # macro +SQ_EDC_FUE_CNTL_LDS = 0x00000005 # macro +SQ_EDC_FUE_CNTL_TD = 0x00000006 # macro +SQ_EDC_FUE_CNTL_TA = 0x00000007 # macro +SQ_EDC_FUE_CNTL_TCP = 0x00000008 # macro +CSDATA_TYPE_WIDTH = 0x00000002 # macro +CSDATA_ADDR_WIDTH = 0x00000007 # macro +CSDATA_DATA_WIDTH = 0x00000020 # macro +CSCNTL_TYPE_WIDTH = 0x00000002 # macro +CSCNTL_ADDR_WIDTH = 0x00000007 # macro +CSCNTL_DATA_WIDTH = 0x00000020 # macro +GSTHREADID_SIZE = 0x00000002 # macro +GB_TILING_CONFIG_TABLE_SIZE = 0x00000020 # macro +GB_TILING_CONFIG_MACROTABLE_SIZE = 0x00000010 # macro +SEM_ECC_ERROR = 0x00000000 # macro +SEM_TRANS_ERROR = 0x00000001 # macro +SEM_RESP_FAILED = 0x00000002 # macro +SEM_RESP_PASSED = 0x00000003 # macro +IQ_QUEUE_SLEEP = 0x00000000 # macro +IQ_OFFLOAD_RETRY = 0x00000001 # macro +IQ_SCH_WAVE_MSG = 0x00000002 # macro +IQ_SEM_REARM = 0x00000003 # macro +IQ_DEQUEUE_RETRY = 0x00000004 # macro +IQ_INTR_TYPE_PQ = 0x00000000 # macro +IQ_INTR_TYPE_IB = 0x00000001 # macro +IQ_INTR_TYPE_MQD = 0x00000002 # macro +VMID_SZ = 0x00000004 # macro +SRCID_RLC = 0x00000000 # macro +SRCID_RLCV = 0x00000006 # macro +SRCID_SECURE_CP = 0x00000007 # macro +SRCID_NONSECURE_CP = 0x00000001 # macro +SRCID_SECURE_CP_RCIU = 0x00000007 # macro +SRCID_NONSECURE_CP_RCIU = 0x00000001 # macro +CONFIG_SPACE_START = 0x00002000 # macro +CONFIG_SPACE_END = 0x00009fff # macro +CONFIG_SPACE1_START = 0x00002000 # macro +CONFIG_SPACE1_END = 0x00002bff # macro +CONFIG_SPACE2_START = 0x00003000 # macro +CONFIG_SPACE2_END = 0x00009fff # macro +UCONFIG_SPACE_START = 0x0000c000 # macro +UCONFIG_SPACE_END = 0x0000ffff # macro +PERSISTENT_SPACE_START = 0x00002c00 # macro +PERSISTENT_SPACE_END = 0x00002fff # macro +CONTEXT_SPACE_START = 0x0000a000 # macro +CONTEXT_SPACE_END = 0x0000a3ff # macro +ROM_SIGNATURE = 0x0000aa55 # macro + +# values for enumeration 'DSM_DATA_SEL' +DSM_DATA_SEL__enumvalues = { + 0: 'DSM_DATA_SEL_DISABLE', + 1: 'DSM_DATA_SEL_0', + 2: 'DSM_DATA_SEL_1', + 3: 'DSM_DATA_SEL_BOTH', +} +DSM_DATA_SEL_DISABLE = 0 +DSM_DATA_SEL_0 = 1 +DSM_DATA_SEL_1 = 2 +DSM_DATA_SEL_BOTH = 3 +DSM_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_ENABLE_ERROR_INJECT' +DSM_ENABLE_ERROR_INJECT__enumvalues = { + 0: 'DSM_ENABLE_ERROR_INJECT_FED_IN', + 1: 'DSM_ENABLE_ERROR_INJECT_SINGLE', + 2: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', + 3: 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', +} +DSM_ENABLE_ERROR_INJECT_FED_IN = 0 +DSM_ENABLE_ERROR_INJECT_SINGLE = 1 +DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 2 +DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 3 +DSM_ENABLE_ERROR_INJECT = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_SELECT_INJECT_DELAY' +DSM_SELECT_INJECT_DELAY__enumvalues = { + 0: 'DSM_SELECT_INJECT_DELAY_NO_DELAY', + 1: 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', +} +DSM_SELECT_INJECT_DELAY_NO_DELAY = 0 +DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 1 +DSM_SELECT_INJECT_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DSM_SINGLE_WRITE' +DSM_SINGLE_WRITE__enumvalues = { + 0: 'DSM_SINGLE_WRITE_DIS', + 1: 'DSM_SINGLE_WRITE_EN', +} +DSM_SINGLE_WRITE_DIS = 0 +DSM_SINGLE_WRITE_EN = 1 +DSM_SINGLE_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_NUM_SIMD_PER_CU' +ENUM_NUM_SIMD_PER_CU__enumvalues = { + 2: 'NUM_SIMD_PER_CU', +} +NUM_SIMD_PER_CU = 2 +ENUM_NUM_SIMD_PER_CU = ctypes.c_uint32 # enum + +# values for enumeration 'GATCL1RequestType' +GATCL1RequestType__enumvalues = { + 0: 'GATCL1_TYPE_NORMAL', + 1: 'GATCL1_TYPE_SHOOTDOWN', + 2: 'GATCL1_TYPE_BYPASS', +} +GATCL1_TYPE_NORMAL = 0 +GATCL1_TYPE_SHOOTDOWN = 1 +GATCL1_TYPE_BYPASS = 2 +GATCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'GL0V_CACHE_POLICIES' +GL0V_CACHE_POLICIES__enumvalues = { + 0: 'GL0V_CACHE_POLICY_MISS_LRU', + 1: 'GL0V_CACHE_POLICY_MISS_EVICT', + 2: 'GL0V_CACHE_POLICY_HIT_LRU', + 3: 'GL0V_CACHE_POLICY_HIT_EVICT', +} +GL0V_CACHE_POLICY_MISS_LRU = 0 +GL0V_CACHE_POLICY_MISS_EVICT = 1 +GL0V_CACHE_POLICY_HIT_LRU = 2 +GL0V_CACHE_POLICY_HIT_EVICT = 3 +GL0V_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL1_CACHE_POLICIES' +GL1_CACHE_POLICIES__enumvalues = { + 0: 'GL1_CACHE_POLICY_MISS_LRU', + 1: 'GL1_CACHE_POLICY_MISS_EVICT', + 2: 'GL1_CACHE_POLICY_HIT_LRU', + 3: 'GL1_CACHE_POLICY_HIT_EVICT', +} +GL1_CACHE_POLICY_MISS_LRU = 0 +GL1_CACHE_POLICY_MISS_EVICT = 1 +GL1_CACHE_POLICY_HIT_LRU = 2 +GL1_CACHE_POLICY_HIT_EVICT = 3 +GL1_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL1_CACHE_STORE_POLICIES' +GL1_CACHE_STORE_POLICIES__enumvalues = { + 0: 'GL1_CACHE_STORE_POLICY_BYPASS', +} +GL1_CACHE_STORE_POLICY_BYPASS = 0 +GL1_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_CACHE_POLICIES' +GL2_CACHE_POLICIES__enumvalues = { + 0: 'GL2_CACHE_POLICY_LRU', + 1: 'GL2_CACHE_POLICY_STREAM', + 2: 'GL2_CACHE_POLICY_NOA', + 3: 'GL2_CACHE_POLICY_BYPASS', +} +GL2_CACHE_POLICY_LRU = 0 +GL2_CACHE_POLICY_STREAM = 1 +GL2_CACHE_POLICY_NOA = 2 +GL2_CACHE_POLICY_BYPASS = 3 +GL2_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'Hdp_SurfaceEndian' +Hdp_SurfaceEndian__enumvalues = { + 0: 'HDP_ENDIAN_NONE', + 1: 'HDP_ENDIAN_8IN16', + 2: 'HDP_ENDIAN_8IN32', + 3: 'HDP_ENDIAN_8IN64', +} +HDP_ENDIAN_NONE = 0 +HDP_ENDIAN_8IN16 = 1 +HDP_ENDIAN_8IN32 = 2 +HDP_ENDIAN_8IN64 = 3 +Hdp_SurfaceEndian = ctypes.c_uint32 # enum + +# values for enumeration 'MTYPE' +MTYPE__enumvalues = { + 0: 'MTYPE_C_RW_US', + 1: 'MTYPE_RESERVED_1', + 2: 'MTYPE_C_RO_S', + 3: 'MTYPE_UC', + 4: 'MTYPE_C_RW_S', + 5: 'MTYPE_RESERVED_5', + 6: 'MTYPE_C_RO_US', + 7: 'MTYPE_RESERVED_7', +} +MTYPE_C_RW_US = 0 +MTYPE_RESERVED_1 = 1 +MTYPE_C_RO_S = 2 +MTYPE_UC = 3 +MTYPE_C_RW_S = 4 +MTYPE_RESERVED_5 = 5 +MTYPE_C_RO_US = 6 +MTYPE_RESERVED_7 = 7 +MTYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_COUNTER_MODE' +PERFMON_COUNTER_MODE__enumvalues = { + 0: 'PERFMON_COUNTER_MODE_ACCUM', + 1: 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 2: 'PERFMON_COUNTER_MODE_MAX', + 3: 'PERFMON_COUNTER_MODE_DIRTY', + 4: 'PERFMON_COUNTER_MODE_SAMPLE', + 5: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 6: 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 7: 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 8: 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 9: 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 15: 'PERFMON_COUNTER_MODE_RESERVED', +} +PERFMON_COUNTER_MODE_ACCUM = 0 +PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 1 +PERFMON_COUNTER_MODE_MAX = 2 +PERFMON_COUNTER_MODE_DIRTY = 3 +PERFMON_COUNTER_MODE_SAMPLE = 4 +PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 5 +PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 6 +PERFMON_COUNTER_MODE_CYCLES_GE_HI = 7 +PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 8 +PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 9 +PERFMON_COUNTER_MODE_RESERVED = 15 +PERFMON_COUNTER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_SPM_MODE' +PERFMON_SPM_MODE__enumvalues = { + 0: 'PERFMON_SPM_MODE_OFF', + 1: 'PERFMON_SPM_MODE_16BIT_CLAMP', + 2: 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 3: 'PERFMON_SPM_MODE_32BIT_CLAMP', + 4: 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 5: 'PERFMON_SPM_MODE_RESERVED_5', + 6: 'PERFMON_SPM_MODE_RESERVED_6', + 7: 'PERFMON_SPM_MODE_RESERVED_7', + 8: 'PERFMON_SPM_MODE_TEST_MODE_0', + 9: 'PERFMON_SPM_MODE_TEST_MODE_1', + 10: 'PERFMON_SPM_MODE_TEST_MODE_2', +} +PERFMON_SPM_MODE_OFF = 0 +PERFMON_SPM_MODE_16BIT_CLAMP = 1 +PERFMON_SPM_MODE_16BIT_NO_CLAMP = 2 +PERFMON_SPM_MODE_32BIT_CLAMP = 3 +PERFMON_SPM_MODE_32BIT_NO_CLAMP = 4 +PERFMON_SPM_MODE_RESERVED_5 = 5 +PERFMON_SPM_MODE_RESERVED_6 = 6 +PERFMON_SPM_MODE_RESERVED_7 = 7 +PERFMON_SPM_MODE_TEST_MODE_0 = 8 +PERFMON_SPM_MODE_TEST_MODE_1 = 9 +PERFMON_SPM_MODE_TEST_MODE_2 = 10 +PERFMON_SPM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'RMI_CID' +RMI_CID__enumvalues = { + 0: 'RMI_CID_CC', + 1: 'RMI_CID_FC', + 2: 'RMI_CID_CM', + 3: 'RMI_CID_DC', + 4: 'RMI_CID_Z', + 5: 'RMI_CID_S', + 6: 'RMI_CID_TILE', + 7: 'RMI_CID_ZPCPSD', +} +RMI_CID_CC = 0 +RMI_CID_FC = 1 +RMI_CID_CM = 2 +RMI_CID_DC = 3 +RMI_CID_Z = 4 +RMI_CID_S = 5 +RMI_CID_TILE = 6 +RMI_CID_ZPCPSD = 7 +RMI_CID = ctypes.c_uint32 # enum + +# values for enumeration 'ReadPolicy' +ReadPolicy__enumvalues = { + 0: 'CACHE_LRU_RD', + 1: 'CACHE_STREAM_RD', + 2: 'CACHE_NOA', + 3: 'RESERVED_RDPOLICY', +} +CACHE_LRU_RD = 0 +CACHE_STREAM_RD = 1 +CACHE_NOA = 2 +RESERVED_RDPOLICY = 3 +ReadPolicy = ctypes.c_uint32 # enum + +# values for enumeration 'SDMA_PERFMON_SEL' +SDMA_PERFMON_SEL__enumvalues = { + 0: 'SDMA_PERFMON_SEL_CYCLE', + 1: 'SDMA_PERFMON_SEL_IDLE', + 2: 'SDMA_PERFMON_SEL_REG_IDLE', + 3: 'SDMA_PERFMON_SEL_RB_EMPTY', + 4: 'SDMA_PERFMON_SEL_RB_FULL', + 5: 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', + 6: 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', + 7: 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', + 8: 'SDMA_PERFMON_SEL_RB_RPTR_WB', + 9: 'SDMA_PERFMON_SEL_RB_CMD_IDLE', + 10: 'SDMA_PERFMON_SEL_RB_CMD_FULL', + 11: 'SDMA_PERFMON_SEL_IB_CMD_IDLE', + 12: 'SDMA_PERFMON_SEL_IB_CMD_FULL', + 13: 'SDMA_PERFMON_SEL_EX_IDLE', + 14: 'SDMA_PERFMON_SEL_SRBM_REG_SEND', + 15: 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'SDMA_PERFMON_SEL_WR_BA_RTR', + 17: 'SDMA_PERFMON_SEL_MC_WR_IDLE', + 18: 'SDMA_PERFMON_SEL_MC_WR_COUNT', + 19: 'SDMA_PERFMON_SEL_RD_BA_RTR', + 20: 'SDMA_PERFMON_SEL_MC_RD_IDLE', + 21: 'SDMA_PERFMON_SEL_MC_RD_COUNT', + 22: 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', + 23: 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', + 26: 'SDMA_PERFMON_SEL_SEM_IDLE', + 27: 'SDMA_PERFMON_SEL_SEM_REQ_STALL', + 28: 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', + 29: 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', + 30: 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', + 31: 'SDMA_PERFMON_SEL_SEM_RESP_PASS', + 32: 'SDMA_PERFMON_SEL_INT_IDLE', + 33: 'SDMA_PERFMON_SEL_INT_REQ_STALL', + 34: 'SDMA_PERFMON_SEL_INT_REQ_COUNT', + 35: 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', + 36: 'SDMA_PERFMON_SEL_INT_RESP_RETRY', + 37: 'SDMA_PERFMON_SEL_NUM_PACKET', + 39: 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', + 40: 'SDMA_PERFMON_SEL_CE_WR_IDLE', + 41: 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', + 42: 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', + 43: 'SDMA_PERFMON_SEL_CE_OUT_IDLE', + 44: 'SDMA_PERFMON_SEL_CE_IN_IDLE', + 45: 'SDMA_PERFMON_SEL_CE_DST_IDLE', + 48: 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', + 51: 'SDMA_PERFMON_SEL_CE_INFO_FULL', + 52: 'SDMA_PERFMON_SEL_CE_INFO1_FULL', + 53: 'SDMA_PERFMON_SEL_CE_RD_STALL', + 54: 'SDMA_PERFMON_SEL_CE_WR_STALL', + 55: 'SDMA_PERFMON_SEL_GFX_SELECT', + 56: 'SDMA_PERFMON_SEL_RLC0_SELECT', + 57: 'SDMA_PERFMON_SEL_RLC1_SELECT', + 58: 'SDMA_PERFMON_SEL_PAGE_SELECT', + 59: 'SDMA_PERFMON_SEL_CTX_CHANGE', + 60: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', + 61: 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', + 62: 'SDMA_PERFMON_SEL_DOORBELL', + 63: 'SDMA_PERFMON_SEL_F32_L1_WR_VLD', + 64: 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', + 65: 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', + 66: 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', + 67: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', + 68: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', + 69: 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', + 70: 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', + 71: 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', + 72: 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', + 73: 'SDMA_PERFMON_SEL_UTCL2_FREE', + 74: 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', + 75: 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', + 76: 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', + 77: 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', + 78: 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', + 79: 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', + 80: 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', + 81: 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', + 82: 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', + 83: 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', + 84: 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', + 85: 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', + 86: 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', + 87: 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', + 88: 'SDMA_PERFMON_SEL_L2_META_RET_VLD', + 89: 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', + 90: 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', + 91: 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', + 92: 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', + 93: 'SDMA_PERFMON_SEL_META_REQ_SEND', + 94: 'SDMA_PERFMON_SEL_META_RTN_VLD', + 95: 'SDMA_PERFMON_SEL_TLBI_SEND', + 96: 'SDMA_PERFMON_SEL_TLBI_RTN', + 97: 'SDMA_PERFMON_SEL_GCR_SEND', + 98: 'SDMA_PERFMON_SEL_GCR_RTN', + 99: 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', + 100: 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', +} +SDMA_PERFMON_SEL_CYCLE = 0 +SDMA_PERFMON_SEL_IDLE = 1 +SDMA_PERFMON_SEL_REG_IDLE = 2 +SDMA_PERFMON_SEL_RB_EMPTY = 3 +SDMA_PERFMON_SEL_RB_FULL = 4 +SDMA_PERFMON_SEL_RB_WPTR_WRAP = 5 +SDMA_PERFMON_SEL_RB_RPTR_WRAP = 6 +SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 7 +SDMA_PERFMON_SEL_RB_RPTR_WB = 8 +SDMA_PERFMON_SEL_RB_CMD_IDLE = 9 +SDMA_PERFMON_SEL_RB_CMD_FULL = 10 +SDMA_PERFMON_SEL_IB_CMD_IDLE = 11 +SDMA_PERFMON_SEL_IB_CMD_FULL = 12 +SDMA_PERFMON_SEL_EX_IDLE = 13 +SDMA_PERFMON_SEL_SRBM_REG_SEND = 14 +SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +SDMA_PERFMON_SEL_WR_BA_RTR = 16 +SDMA_PERFMON_SEL_MC_WR_IDLE = 17 +SDMA_PERFMON_SEL_MC_WR_COUNT = 18 +SDMA_PERFMON_SEL_RD_BA_RTR = 19 +SDMA_PERFMON_SEL_MC_RD_IDLE = 20 +SDMA_PERFMON_SEL_MC_RD_COUNT = 21 +SDMA_PERFMON_SEL_MC_RD_RET_STALL = 22 +SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 23 +SDMA_PERFMON_SEL_SEM_IDLE = 26 +SDMA_PERFMON_SEL_SEM_REQ_STALL = 27 +SDMA_PERFMON_SEL_SEM_REQ_COUNT = 28 +SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 29 +SDMA_PERFMON_SEL_SEM_RESP_FAIL = 30 +SDMA_PERFMON_SEL_SEM_RESP_PASS = 31 +SDMA_PERFMON_SEL_INT_IDLE = 32 +SDMA_PERFMON_SEL_INT_REQ_STALL = 33 +SDMA_PERFMON_SEL_INT_REQ_COUNT = 34 +SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 35 +SDMA_PERFMON_SEL_INT_RESP_RETRY = 36 +SDMA_PERFMON_SEL_NUM_PACKET = 37 +SDMA_PERFMON_SEL_CE_WREQ_IDLE = 39 +SDMA_PERFMON_SEL_CE_WR_IDLE = 40 +SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 41 +SDMA_PERFMON_SEL_CE_RREQ_IDLE = 42 +SDMA_PERFMON_SEL_CE_OUT_IDLE = 43 +SDMA_PERFMON_SEL_CE_IN_IDLE = 44 +SDMA_PERFMON_SEL_CE_DST_IDLE = 45 +SDMA_PERFMON_SEL_CE_AFIFO_FULL = 48 +SDMA_PERFMON_SEL_CE_INFO_FULL = 51 +SDMA_PERFMON_SEL_CE_INFO1_FULL = 52 +SDMA_PERFMON_SEL_CE_RD_STALL = 53 +SDMA_PERFMON_SEL_CE_WR_STALL = 54 +SDMA_PERFMON_SEL_GFX_SELECT = 55 +SDMA_PERFMON_SEL_RLC0_SELECT = 56 +SDMA_PERFMON_SEL_RLC1_SELECT = 57 +SDMA_PERFMON_SEL_PAGE_SELECT = 58 +SDMA_PERFMON_SEL_CTX_CHANGE = 59 +SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 60 +SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 61 +SDMA_PERFMON_SEL_DOORBELL = 62 +SDMA_PERFMON_SEL_F32_L1_WR_VLD = 63 +SDMA_PERFMON_SEL_CE_L1_WR_VLD = 64 +SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 65 +SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 66 +SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 67 +SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 68 +SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 69 +SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 70 +SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 71 +SDMA_PERFMON_SEL_UTCL2_RET_ACK = 72 +SDMA_PERFMON_SEL_UTCL2_FREE = 73 +SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 74 +SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 75 +SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 76 +SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 77 +SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 78 +SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 79 +SDMA_PERFMON_SEL_GPUVM_INV_LOW = 80 +SDMA_PERFMON_SEL_L1_WRL2_IDLE = 81 +SDMA_PERFMON_SEL_L1_RDL2_IDLE = 82 +SDMA_PERFMON_SEL_L1_WRMC_IDLE = 83 +SDMA_PERFMON_SEL_L1_RDMC_IDLE = 84 +SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 85 +SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 86 +SDMA_PERFMON_SEL_META_L2_REQ_SEND = 87 +SDMA_PERFMON_SEL_L2_META_RET_VLD = 88 +SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 89 +SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 90 +SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 91 +SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 92 +SDMA_PERFMON_SEL_META_REQ_SEND = 93 +SDMA_PERFMON_SEL_META_RTN_VLD = 94 +SDMA_PERFMON_SEL_TLBI_SEND = 95 +SDMA_PERFMON_SEL_TLBI_RTN = 96 +SDMA_PERFMON_SEL_GCR_SEND = 97 +SDMA_PERFMON_SEL_GCR_RTN = 98 +SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 99 +SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 100 +SDMA_PERFMON_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SDMA_PERF_SEL' +SDMA_PERF_SEL__enumvalues = { + 0: 'SDMA_PERF_SEL_CYCLE', + 1: 'SDMA_PERF_SEL_IDLE', + 2: 'SDMA_PERF_SEL_REG_IDLE', + 3: 'SDMA_PERF_SEL_RB_EMPTY', + 4: 'SDMA_PERF_SEL_RB_FULL', + 5: 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 6: 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 7: 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', + 8: 'SDMA_PERF_SEL_RB_RPTR_WB', + 9: 'SDMA_PERF_SEL_RB_CMD_IDLE', + 10: 'SDMA_PERF_SEL_RB_CMD_FULL', + 11: 'SDMA_PERF_SEL_IB_CMD_IDLE', + 12: 'SDMA_PERF_SEL_IB_CMD_FULL', + 13: 'SDMA_PERF_SEL_EX_IDLE', + 14: 'SDMA_PERF_SEL_SRBM_REG_SEND', + 15: 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'SDMA_PERF_SEL_MC_WR_IDLE', + 17: 'SDMA_PERF_SEL_MC_WR_COUNT', + 18: 'SDMA_PERF_SEL_MC_RD_IDLE', + 19: 'SDMA_PERF_SEL_MC_RD_COUNT', + 20: 'SDMA_PERF_SEL_MC_RD_RET_STALL', + 21: 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 24: 'SDMA_PERF_SEL_SEM_IDLE', + 25: 'SDMA_PERF_SEL_SEM_REQ_STALL', + 26: 'SDMA_PERF_SEL_SEM_REQ_COUNT', + 27: 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 28: 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 29: 'SDMA_PERF_SEL_SEM_RESP_PASS', + 30: 'SDMA_PERF_SEL_INT_IDLE', + 31: 'SDMA_PERF_SEL_INT_REQ_STALL', + 32: 'SDMA_PERF_SEL_INT_REQ_COUNT', + 33: 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', + 34: 'SDMA_PERF_SEL_INT_RESP_RETRY', + 35: 'SDMA_PERF_SEL_NUM_PACKET', + 37: 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 38: 'SDMA_PERF_SEL_CE_WR_IDLE', + 39: 'SDMA_PERF_SEL_CE_SPLIT_IDLE', + 40: 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 41: 'SDMA_PERF_SEL_CE_OUT_IDLE', + 42: 'SDMA_PERF_SEL_CE_IN_IDLE', + 43: 'SDMA_PERF_SEL_CE_DST_IDLE', + 46: 'SDMA_PERF_SEL_CE_AFIFO_FULL', + 49: 'SDMA_PERF_SEL_CE_INFO_FULL', + 50: 'SDMA_PERF_SEL_CE_INFO1_FULL', + 51: 'SDMA_PERF_SEL_CE_RD_STALL', + 52: 'SDMA_PERF_SEL_CE_WR_STALL', + 53: 'SDMA_PERF_SEL_GFX_SELECT', + 54: 'SDMA_PERF_SEL_RLC0_SELECT', + 55: 'SDMA_PERF_SEL_RLC1_SELECT', + 56: 'SDMA_PERF_SEL_PAGE_SELECT', + 57: 'SDMA_PERF_SEL_CTX_CHANGE', + 58: 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', + 59: 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 60: 'SDMA_PERF_SEL_DOORBELL', + 61: 'SDMA_PERF_SEL_RD_BA_RTR', + 62: 'SDMA_PERF_SEL_WR_BA_RTR', + 63: 'SDMA_PERF_SEL_F32_L1_WR_VLD', + 64: 'SDMA_PERF_SEL_CE_L1_WR_VLD', + 65: 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', + 66: 'SDMA_PERF_SEL_SDMA_CPF_INVACK', + 67: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', + 68: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', + 69: 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', + 70: 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', + 71: 'SDMA_PERF_SEL_UTCL2_RET_XNACK', + 72: 'SDMA_PERF_SEL_UTCL2_RET_ACK', + 73: 'SDMA_PERF_SEL_UTCL2_FREE', + 74: 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', + 75: 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 76: 'SDMA_PERF_SEL_DMA_L1_RD_SEND', + 77: 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 78: 'SDMA_PERF_SEL_DMA_MC_RD_SEND', + 79: 'SDMA_PERF_SEL_GPUVM_INV_HIGH', + 80: 'SDMA_PERF_SEL_GPUVM_INV_LOW', + 81: 'SDMA_PERF_SEL_L1_WRL2_IDLE', + 82: 'SDMA_PERF_SEL_L1_RDL2_IDLE', + 83: 'SDMA_PERF_SEL_L1_WRMC_IDLE', + 84: 'SDMA_PERF_SEL_L1_RDMC_IDLE', + 85: 'SDMA_PERF_SEL_L1_WR_INV_IDLE', + 86: 'SDMA_PERF_SEL_L1_RD_INV_IDLE', + 87: 'SDMA_PERF_SEL_META_L2_REQ_SEND', + 88: 'SDMA_PERF_SEL_L2_META_RET_VLD', + 89: 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', + 90: 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', + 91: 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', + 92: 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', + 93: 'SDMA_PERF_SEL_META_REQ_SEND', + 94: 'SDMA_PERF_SEL_META_RTN_VLD', + 95: 'SDMA_PERF_SEL_TLBI_SEND', + 96: 'SDMA_PERF_SEL_TLBI_RTN', + 97: 'SDMA_PERF_SEL_GCR_SEND', + 98: 'SDMA_PERF_SEL_GCR_RTN', + 99: 'SDMA_PERF_SEL_CGCG_FENCE', + 100: 'SDMA_PERF_SEL_CE_CH_WR_REQ', + 101: 'SDMA_PERF_SEL_CE_CH_WR_RET', + 102: 'SDMA_PERF_SEL_F32_CH_WR_REQ', + 103: 'SDMA_PERF_SEL_F32_CH_WR_RET', + 104: 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ', + 105: 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET', + 106: 'SDMA_PERF_SEL_RB_CH_RD_REQ', + 107: 'SDMA_PERF_SEL_RB_CH_RD_RET', + 108: 'SDMA_PERF_SEL_IB_CH_RD_REQ', + 109: 'SDMA_PERF_SEL_IB_CH_RD_RET', + 110: 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', + 111: 'SDMA_PERF_SEL_WPTR_CH_RD_RET', + 112: 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', + 113: 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', + 114: 'SDMA_PERF_SEL_CMD_OP_MATCH', + 115: 'SDMA_PERF_SEL_CMD_OP_START', + 116: 'SDMA_PERF_SEL_CMD_OP_END', + 117: 'SDMA_PERF_SEL_CE_BUSY', + 118: 'SDMA_PERF_SEL_CE_BUSY_START', + 119: 'SDMA_PERF_SEL_CE_BUSY_END', + 120: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 121: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 122: 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 123: 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', + 124: 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', + 125: 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', + 126: 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', +} +SDMA_PERF_SEL_CYCLE = 0 +SDMA_PERF_SEL_IDLE = 1 +SDMA_PERF_SEL_REG_IDLE = 2 +SDMA_PERF_SEL_RB_EMPTY = 3 +SDMA_PERF_SEL_RB_FULL = 4 +SDMA_PERF_SEL_RB_WPTR_WRAP = 5 +SDMA_PERF_SEL_RB_RPTR_WRAP = 6 +SDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 +SDMA_PERF_SEL_RB_RPTR_WB = 8 +SDMA_PERF_SEL_RB_CMD_IDLE = 9 +SDMA_PERF_SEL_RB_CMD_FULL = 10 +SDMA_PERF_SEL_IB_CMD_IDLE = 11 +SDMA_PERF_SEL_IB_CMD_FULL = 12 +SDMA_PERF_SEL_EX_IDLE = 13 +SDMA_PERF_SEL_SRBM_REG_SEND = 14 +SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +SDMA_PERF_SEL_MC_WR_IDLE = 16 +SDMA_PERF_SEL_MC_WR_COUNT = 17 +SDMA_PERF_SEL_MC_RD_IDLE = 18 +SDMA_PERF_SEL_MC_RD_COUNT = 19 +SDMA_PERF_SEL_MC_RD_RET_STALL = 20 +SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 +SDMA_PERF_SEL_SEM_IDLE = 24 +SDMA_PERF_SEL_SEM_REQ_STALL = 25 +SDMA_PERF_SEL_SEM_REQ_COUNT = 26 +SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 +SDMA_PERF_SEL_SEM_RESP_FAIL = 28 +SDMA_PERF_SEL_SEM_RESP_PASS = 29 +SDMA_PERF_SEL_INT_IDLE = 30 +SDMA_PERF_SEL_INT_REQ_STALL = 31 +SDMA_PERF_SEL_INT_REQ_COUNT = 32 +SDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 +SDMA_PERF_SEL_INT_RESP_RETRY = 34 +SDMA_PERF_SEL_NUM_PACKET = 35 +SDMA_PERF_SEL_CE_WREQ_IDLE = 37 +SDMA_PERF_SEL_CE_WR_IDLE = 38 +SDMA_PERF_SEL_CE_SPLIT_IDLE = 39 +SDMA_PERF_SEL_CE_RREQ_IDLE = 40 +SDMA_PERF_SEL_CE_OUT_IDLE = 41 +SDMA_PERF_SEL_CE_IN_IDLE = 42 +SDMA_PERF_SEL_CE_DST_IDLE = 43 +SDMA_PERF_SEL_CE_AFIFO_FULL = 46 +SDMA_PERF_SEL_CE_INFO_FULL = 49 +SDMA_PERF_SEL_CE_INFO1_FULL = 50 +SDMA_PERF_SEL_CE_RD_STALL = 51 +SDMA_PERF_SEL_CE_WR_STALL = 52 +SDMA_PERF_SEL_GFX_SELECT = 53 +SDMA_PERF_SEL_RLC0_SELECT = 54 +SDMA_PERF_SEL_RLC1_SELECT = 55 +SDMA_PERF_SEL_PAGE_SELECT = 56 +SDMA_PERF_SEL_CTX_CHANGE = 57 +SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 +SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 +SDMA_PERF_SEL_DOORBELL = 60 +SDMA_PERF_SEL_RD_BA_RTR = 61 +SDMA_PERF_SEL_WR_BA_RTR = 62 +SDMA_PERF_SEL_F32_L1_WR_VLD = 63 +SDMA_PERF_SEL_CE_L1_WR_VLD = 64 +SDMA_PERF_SEL_CPF_SDMA_INVREQ = 65 +SDMA_PERF_SEL_SDMA_CPF_INVACK = 66 +SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 67 +SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 68 +SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 69 +SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 70 +SDMA_PERF_SEL_UTCL2_RET_XNACK = 71 +SDMA_PERF_SEL_UTCL2_RET_ACK = 72 +SDMA_PERF_SEL_UTCL2_FREE = 73 +SDMA_PERF_SEL_SDMA_UTCL2_SEND = 74 +SDMA_PERF_SEL_DMA_L1_WR_SEND = 75 +SDMA_PERF_SEL_DMA_L1_RD_SEND = 76 +SDMA_PERF_SEL_DMA_MC_WR_SEND = 77 +SDMA_PERF_SEL_DMA_MC_RD_SEND = 78 +SDMA_PERF_SEL_GPUVM_INV_HIGH = 79 +SDMA_PERF_SEL_GPUVM_INV_LOW = 80 +SDMA_PERF_SEL_L1_WRL2_IDLE = 81 +SDMA_PERF_SEL_L1_RDL2_IDLE = 82 +SDMA_PERF_SEL_L1_WRMC_IDLE = 83 +SDMA_PERF_SEL_L1_RDMC_IDLE = 84 +SDMA_PERF_SEL_L1_WR_INV_IDLE = 85 +SDMA_PERF_SEL_L1_RD_INV_IDLE = 86 +SDMA_PERF_SEL_META_L2_REQ_SEND = 87 +SDMA_PERF_SEL_L2_META_RET_VLD = 88 +SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 89 +SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 90 +SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 91 +SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 92 +SDMA_PERF_SEL_META_REQ_SEND = 93 +SDMA_PERF_SEL_META_RTN_VLD = 94 +SDMA_PERF_SEL_TLBI_SEND = 95 +SDMA_PERF_SEL_TLBI_RTN = 96 +SDMA_PERF_SEL_GCR_SEND = 97 +SDMA_PERF_SEL_GCR_RTN = 98 +SDMA_PERF_SEL_CGCG_FENCE = 99 +SDMA_PERF_SEL_CE_CH_WR_REQ = 100 +SDMA_PERF_SEL_CE_CH_WR_RET = 101 +SDMA_PERF_SEL_F32_CH_WR_REQ = 102 +SDMA_PERF_SEL_F32_CH_WR_RET = 103 +SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ = 104 +SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET = 105 +SDMA_PERF_SEL_RB_CH_RD_REQ = 106 +SDMA_PERF_SEL_RB_CH_RD_RET = 107 +SDMA_PERF_SEL_IB_CH_RD_REQ = 108 +SDMA_PERF_SEL_IB_CH_RD_RET = 109 +SDMA_PERF_SEL_WPTR_CH_RD_REQ = 110 +SDMA_PERF_SEL_WPTR_CH_RD_RET = 111 +SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 112 +SDMA_PERF_SEL_UTCL1_UTCL2_RET = 113 +SDMA_PERF_SEL_CMD_OP_MATCH = 114 +SDMA_PERF_SEL_CMD_OP_START = 115 +SDMA_PERF_SEL_CMD_OP_END = 116 +SDMA_PERF_SEL_CE_BUSY = 117 +SDMA_PERF_SEL_CE_BUSY_START = 118 +SDMA_PERF_SEL_CE_BUSY_END = 119 +SDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 120 +SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 121 +SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 122 +SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 123 +SDMA_PERF_SEL_CH_CE_WRRET_VALID = 124 +SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 125 +SDMA_PERF_SEL_CH_CE_RDRET_VALID = 126 +SDMA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_CACHE_POLICIES' +TCC_CACHE_POLICIES__enumvalues = { + 0: 'TCC_CACHE_POLICY_LRU', + 1: 'TCC_CACHE_POLICY_STREAM', +} +TCC_CACHE_POLICY_LRU = 0 +TCC_CACHE_POLICY_STREAM = 1 +TCC_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCC_MTYPE' +TCC_MTYPE__enumvalues = { + 0: 'MTYPE_NC', + 1: 'MTYPE_WC', + 2: 'MTYPE_CC', +} +MTYPE_NC = 0 +MTYPE_WC = 1 +MTYPE_CC = 2 +TCC_MTYPE = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL0FaultType' +UTCL0FaultType__enumvalues = { + 0: 'UTCL0_XNACK_SUCCESS', + 1: 'UTCL0_XNACK_RETRY', + 2: 'UTCL0_XNACK_PRT', + 3: 'UTCL0_XNACK_NO_RETRY', +} +UTCL0_XNACK_SUCCESS = 0 +UTCL0_XNACK_RETRY = 1 +UTCL0_XNACK_PRT = 2 +UTCL0_XNACK_NO_RETRY = 3 +UTCL0FaultType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL0RequestType' +UTCL0RequestType__enumvalues = { + 0: 'UTCL0_TYPE_NORMAL', + 1: 'UTCL0_TYPE_SHOOTDOWN', + 2: 'UTCL0_TYPE_BYPASS', +} +UTCL0_TYPE_NORMAL = 0 +UTCL0_TYPE_SHOOTDOWN = 1 +UTCL0_TYPE_BYPASS = 2 +UTCL0RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1FaultType' +UTCL1FaultType__enumvalues = { + 0: 'UTCL1_XNACK_SUCCESS', + 1: 'UTCL1_XNACK_RETRY', + 2: 'UTCL1_XNACK_PRT', + 3: 'UTCL1_XNACK_NO_RETRY', +} +UTCL1_XNACK_SUCCESS = 0 +UTCL1_XNACK_RETRY = 1 +UTCL1_XNACK_PRT = 2 +UTCL1_XNACK_NO_RETRY = 3 +UTCL1FaultType = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1RequestType' +UTCL1RequestType__enumvalues = { + 0: 'UTCL1_TYPE_NORMAL', + 1: 'UTCL1_TYPE_SHOOTDOWN', + 2: 'UTCL1_TYPE_BYPASS', +} +UTCL1_TYPE_NORMAL = 0 +UTCL1_TYPE_SHOOTDOWN = 1 +UTCL1_TYPE_BYPASS = 2 +UTCL1RequestType = ctypes.c_uint32 # enum + +# values for enumeration 'VMEMCMD_RETURN_ORDER' +VMEMCMD_RETURN_ORDER__enumvalues = { + 0: 'VMEMCMD_RETURN_OUT_OF_ORDER', + 1: 'VMEMCMD_RETURN_IN_ORDER', + 2: 'VMEMCMD_RETURN_IN_ORDER_READ', +} +VMEMCMD_RETURN_OUT_OF_ORDER = 0 +VMEMCMD_RETURN_IN_ORDER = 1 +VMEMCMD_RETURN_IN_ORDER_READ = 2 +VMEMCMD_RETURN_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'WritePolicy' +WritePolicy__enumvalues = { + 0: 'CACHE_LRU_WR', + 1: 'CACHE_STREAM', + 2: 'CACHE_NOA_WR', + 3: 'CACHE_BYPASS', +} +CACHE_LRU_WR = 0 +CACHE_STREAM = 1 +CACHE_NOA_WR = 2 +CACHE_BYPASS = 3 +WritePolicy = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_BYPASS' +CNVC_BYPASS__enumvalues = { + 0: 'CNVC_BYPASS_DISABLE', + 1: 'CNVC_BYPASS_EN', +} +CNVC_BYPASS_DISABLE = 0 +CNVC_BYPASS_EN = 1 +CNVC_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_COEF_FORMAT_ENUM' +CNVC_COEF_FORMAT_ENUM__enumvalues = { + 0: 'CNVC_FIX_S2_13', + 1: 'CNVC_FIX_S3_12', +} +CNVC_FIX_S2_13 = 0 +CNVC_FIX_S3_12 = 1 +CNVC_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_ENABLE' +CNVC_ENABLE__enumvalues = { + 0: 'CNVC_DIS', + 1: 'CNVC_EN', +} +CNVC_DIS = 0 +CNVC_EN = 1 +CNVC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CNVC_PENDING' +CNVC_PENDING__enumvalues = { + 0: 'CNVC_NOT_PENDING', + 1: 'CNVC_YES_PENDING', +} +CNVC_NOT_PENDING = 0 +CNVC_YES_PENDING = 1 +CNVC_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'COLOR_KEYER_MODE' +COLOR_KEYER_MODE__enumvalues = { + 0: 'FORCE_00', + 1: 'FORCE_FF', + 2: 'RANGE_00', + 3: 'RANGE_FF', +} +FORCE_00 = 0 +FORCE_FF = 1 +RANGE_00 = 2 +RANGE_FF = 3 +COLOR_KEYER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DENORM_TRUNCATE' +DENORM_TRUNCATE__enumvalues = { + 0: 'CNVC_ROUND', + 1: 'CNVC_TRUNCATE', +} +CNVC_ROUND = 0 +CNVC_TRUNCATE = 1 +DENORM_TRUNCATE = ctypes.c_uint32 # enum + +# values for enumeration 'FORMAT_CROSSBAR' +FORMAT_CROSSBAR__enumvalues = { + 0: 'FORMAT_CROSSBAR_R', + 1: 'FORMAT_CROSSBAR_G', + 2: 'FORMAT_CROSSBAR_B', +} +FORMAT_CROSSBAR_R = 0 +FORMAT_CROSSBAR_G = 1 +FORMAT_CROSSBAR_B = 2 +FORMAT_CROSSBAR = ctypes.c_uint32 # enum + +# values for enumeration 'PIX_EXPAND_MODE' +PIX_EXPAND_MODE__enumvalues = { + 0: 'PIX_DYNAMIC_EXPANSION', + 1: 'PIX_ZERO_EXPANSION', +} +PIX_DYNAMIC_EXPANSION = 0 +PIX_ZERO_EXPANSION = 1 +PIX_EXPAND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PRE_CSC_MODE_ENUM' +PRE_CSC_MODE_ENUM__enumvalues = { + 0: 'PRE_CSC_BYPASS', + 1: 'PRE_CSC_SET_A', + 2: 'PRE_CSC_SET_B', +} +PRE_CSC_BYPASS = 0 +PRE_CSC_SET_A = 1 +PRE_CSC_SET_B = 2 +PRE_CSC_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'PRE_DEGAM_MODE' +PRE_DEGAM_MODE__enumvalues = { + 0: 'PRE_DEGAM_BYPASS', + 1: 'PRE_DEGAM_ENABLE', +} +PRE_DEGAM_BYPASS = 0 +PRE_DEGAM_ENABLE = 1 +PRE_DEGAM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PRE_DEGAM_SELECT' +PRE_DEGAM_SELECT__enumvalues = { + 0: 'PRE_DEGAM_SRGB', + 1: 'PRE_DEGAM_GAMMA_22', + 2: 'PRE_DEGAM_GAMMA_24', + 3: 'PRE_DEGAM_GAMMA_26', + 4: 'PRE_DEGAM_BT2020', + 5: 'PRE_DEGAM_BT2100PQ', + 6: 'PRE_DEGAM_BT2100HLG', +} +PRE_DEGAM_SRGB = 0 +PRE_DEGAM_GAMMA_22 = 1 +PRE_DEGAM_GAMMA_24 = 2 +PRE_DEGAM_GAMMA_26 = 3 +PRE_DEGAM_BT2020 = 4 +PRE_DEGAM_BT2100PQ = 5 +PRE_DEGAM_BT2100HLG = 6 +PRE_DEGAM_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_PIXEL_FORMAT' +SURFACE_PIXEL_FORMAT__enumvalues = { + 1: 'ARGB1555', + 2: 'RGBA5551', + 3: 'RGB565', + 4: 'BGR565', + 5: 'ARGB4444', + 6: 'RGBA4444', + 8: 'ARGB8888', + 9: 'RGBA8888', + 10: 'ARGB2101010', + 11: 'RGBA1010102', + 12: 'AYCrCb8888', + 13: 'YCrCbA8888', + 14: 'ACrYCb8888', + 15: 'CrYCbA8888', + 16: 'ARGB16161616_10MSB', + 17: 'RGBA16161616_10MSB', + 18: 'ARGB16161616_10LSB', + 19: 'RGBA16161616_10LSB', + 20: 'ARGB16161616_12MSB', + 21: 'RGBA16161616_12MSB', + 22: 'ARGB16161616_12LSB', + 23: 'RGBA16161616_12LSB', + 24: 'ARGB16161616_FLOAT', + 25: 'RGBA16161616_FLOAT', + 26: 'ARGB16161616_UNORM', + 27: 'RGBA16161616_UNORM', + 28: 'ARGB16161616_SNORM', + 29: 'RGBA16161616_SNORM', + 32: 'AYCrCb16161616_10MSB', + 33: 'AYCrCb16161616_10LSB', + 34: 'YCrCbA16161616_10MSB', + 35: 'YCrCbA16161616_10LSB', + 36: 'ACrYCb16161616_10MSB', + 37: 'ACrYCb16161616_10LSB', + 38: 'CrYCbA16161616_10MSB', + 39: 'CrYCbA16161616_10LSB', + 40: 'AYCrCb16161616_12MSB', + 41: 'AYCrCb16161616_12LSB', + 42: 'YCrCbA16161616_12MSB', + 43: 'YCrCbA16161616_12LSB', + 44: 'ACrYCb16161616_12MSB', + 45: 'ACrYCb16161616_12LSB', + 46: 'CrYCbA16161616_12MSB', + 47: 'CrYCbA16161616_12LSB', + 64: 'Y8_CrCb88_420_PLANAR', + 65: 'Y8_CbCr88_420_PLANAR', + 66: 'Y10_CrCb1010_420_PLANAR', + 67: 'Y10_CbCr1010_420_PLANAR', + 68: 'Y12_CrCb1212_420_PLANAR', + 69: 'Y12_CbCr1212_420_PLANAR', + 72: 'YCrYCb8888_422_PACKED', + 73: 'YCbYCr8888_422_PACKED', + 74: 'CrYCbY8888_422_PACKED', + 75: 'CbYCrY8888_422_PACKED', + 76: 'YCrYCb10101010_422_PACKED', + 77: 'YCbYCr10101010_422_PACKED', + 78: 'CrYCbY10101010_422_PACKED', + 79: 'CbYCrY10101010_422_PACKED', + 80: 'YCrYCb12121212_422_PACKED', + 81: 'YCbYCr12121212_422_PACKED', + 82: 'CrYCbY12121212_422_PACKED', + 83: 'CbYCrY12121212_422_PACKED', + 112: 'RGB111110_FIX', + 113: 'BGR101111_FIX', + 114: 'ACrYCb2101010', + 115: 'CrYCbA1010102', + 116: 'RGBE', + 118: 'RGB111110_FLOAT', + 119: 'BGR101111_FLOAT', + 120: 'MONO_8', + 121: 'MONO_10MSB', + 122: 'MONO_10LSB', + 123: 'MONO_12MSB', + 124: 'MONO_12LSB', + 125: 'MONO_16', +} +ARGB1555 = 1 +RGBA5551 = 2 +RGB565 = 3 +BGR565 = 4 +ARGB4444 = 5 +RGBA4444 = 6 +ARGB8888 = 8 +RGBA8888 = 9 +ARGB2101010 = 10 +RGBA1010102 = 11 +AYCrCb8888 = 12 +YCrCbA8888 = 13 +ACrYCb8888 = 14 +CrYCbA8888 = 15 +ARGB16161616_10MSB = 16 +RGBA16161616_10MSB = 17 +ARGB16161616_10LSB = 18 +RGBA16161616_10LSB = 19 +ARGB16161616_12MSB = 20 +RGBA16161616_12MSB = 21 +ARGB16161616_12LSB = 22 +RGBA16161616_12LSB = 23 +ARGB16161616_FLOAT = 24 +RGBA16161616_FLOAT = 25 +ARGB16161616_UNORM = 26 +RGBA16161616_UNORM = 27 +ARGB16161616_SNORM = 28 +RGBA16161616_SNORM = 29 +AYCrCb16161616_10MSB = 32 +AYCrCb16161616_10LSB = 33 +YCrCbA16161616_10MSB = 34 +YCrCbA16161616_10LSB = 35 +ACrYCb16161616_10MSB = 36 +ACrYCb16161616_10LSB = 37 +CrYCbA16161616_10MSB = 38 +CrYCbA16161616_10LSB = 39 +AYCrCb16161616_12MSB = 40 +AYCrCb16161616_12LSB = 41 +YCrCbA16161616_12MSB = 42 +YCrCbA16161616_12LSB = 43 +ACrYCb16161616_12MSB = 44 +ACrYCb16161616_12LSB = 45 +CrYCbA16161616_12MSB = 46 +CrYCbA16161616_12LSB = 47 +Y8_CrCb88_420_PLANAR = 64 +Y8_CbCr88_420_PLANAR = 65 +Y10_CrCb1010_420_PLANAR = 66 +Y10_CbCr1010_420_PLANAR = 67 +Y12_CrCb1212_420_PLANAR = 68 +Y12_CbCr1212_420_PLANAR = 69 +YCrYCb8888_422_PACKED = 72 +YCbYCr8888_422_PACKED = 73 +CrYCbY8888_422_PACKED = 74 +CbYCrY8888_422_PACKED = 75 +YCrYCb10101010_422_PACKED = 76 +YCbYCr10101010_422_PACKED = 77 +CrYCbY10101010_422_PACKED = 78 +CbYCrY10101010_422_PACKED = 79 +YCrYCb12121212_422_PACKED = 80 +YCbYCr12121212_422_PACKED = 81 +CrYCbY12121212_422_PACKED = 82 +CbYCrY12121212_422_PACKED = 83 +RGB111110_FIX = 112 +BGR101111_FIX = 113 +ACrYCb2101010 = 114 +CrYCbA1010102 = 115 +RGBE = 116 +RGB111110_FLOAT = 118 +BGR101111_FLOAT = 119 +MONO_8 = 120 +MONO_10MSB = 121 +MONO_10LSB = 122 +MONO_12MSB = 123 +MONO_12LSB = 124 +MONO_16 = 125 +SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'XNORM' +XNORM__enumvalues = { + 0: 'XNORM_A', + 1: 'XNORM_B', +} +XNORM_A = 0 +XNORM_B = 1 +XNORM = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_ENABLE' +CUR_ENABLE__enumvalues = { + 0: 'CUR_DIS', + 1: 'CUR_EN', +} +CUR_DIS = 0 +CUR_EN = 1 +CUR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_EXPAND_MODE' +CUR_EXPAND_MODE__enumvalues = { + 0: 'CUR_DYNAMIC_EXPANSION', + 1: 'CUR_ZERO_EXPANSION', +} +CUR_DYNAMIC_EXPANSION = 0 +CUR_ZERO_EXPANSION = 1 +CUR_EXPAND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_INV_CLAMP' +CUR_INV_CLAMP__enumvalues = { + 0: 'CUR_CLAMP_DIS', + 1: 'CUR_CLAMP_EN', +} +CUR_CLAMP_DIS = 0 +CUR_CLAMP_EN = 1 +CUR_INV_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_MODE' +CUR_MODE__enumvalues = { + 0: 'MONO_2BIT', + 1: 'COLOR_24BIT_1BIT_AND', + 2: 'COLOR_24BIT_8BIT_ALPHA_PREMULT', + 3: 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 4: 'COLOR_64BIT_FP_PREMULT', + 5: 'COLOR_64BIT_FP_UNPREMULT', +} +MONO_2BIT = 0 +COLOR_24BIT_1BIT_AND = 1 +COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 +COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 +COLOR_64BIT_FP_PREMULT = 4 +COLOR_64BIT_FP_UNPREMULT = 5 +CUR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_PENDING' +CUR_PENDING__enumvalues = { + 0: 'CUR_NOT_PENDING', + 1: 'CUR_YES_PENDING', +} +CUR_NOT_PENDING = 0 +CUR_YES_PENDING = 1 +CUR_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'CUR_ROM_EN' +CUR_ROM_EN__enumvalues = { + 0: 'CUR_FP_NO_ROM', + 1: 'CUR_FP_USE_ROM', +} +CUR_FP_NO_ROM = 0 +CUR_FP_USE_ROM = 1 +CUR_ROM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'COEF_RAM_SELECT_RD' +COEF_RAM_SELECT_RD__enumvalues = { + 0: 'COEF_RAM_SELECT_BACK', + 1: 'COEF_RAM_SELECT_CURRENT', +} +COEF_RAM_SELECT_BACK = 0 +COEF_RAM_SELECT_CURRENT = 1 +COEF_RAM_SELECT_RD = ctypes.c_uint32 # enum + +# values for enumeration 'DSCL_MODE_SEL' +DSCL_MODE_SEL__enumvalues = { + 0: 'DSCL_MODE_SCALING_444_BYPASS', + 1: 'DSCL_MODE_SCALING_444_RGB_ENABLE', + 2: 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', + 3: 'DSCL_MODE_SCALING_YCBCR_ENABLE', + 4: 'DSCL_MODE_LUMA_SCALING_BYPASS', + 5: 'DSCL_MODE_CHROMA_SCALING_BYPASS', + 6: 'DSCL_MODE_DSCL_BYPASS', +} +DSCL_MODE_SCALING_444_BYPASS = 0 +DSCL_MODE_SCALING_444_RGB_ENABLE = 1 +DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2 +DSCL_MODE_SCALING_YCBCR_ENABLE = 3 +DSCL_MODE_LUMA_SCALING_BYPASS = 4 +DSCL_MODE_CHROMA_SCALING_BYPASS = 5 +DSCL_MODE_DSCL_BYPASS = 6 +DSCL_MODE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'LB_ALPHA_EN' +LB_ALPHA_EN__enumvalues = { + 0: 'LB_ALPHA_DISABLE', + 1: 'LB_ALPHA_ENABLE', +} +LB_ALPHA_DISABLE = 0 +LB_ALPHA_ENABLE = 1 +LB_ALPHA_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_INTERLEAVE_EN' +LB_INTERLEAVE_EN__enumvalues = { + 0: 'LB_INTERLEAVE_DISABLE', + 1: 'LB_INTERLEAVE_ENABLE', +} +LB_INTERLEAVE_DISABLE = 0 +LB_INTERLEAVE_ENABLE = 1 +LB_INTERLEAVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LB_MEMORY_CONFIG' +LB_MEMORY_CONFIG__enumvalues = { + 0: 'LB_MEMORY_CONFIG_0', + 1: 'LB_MEMORY_CONFIG_1', + 2: 'LB_MEMORY_CONFIG_2', + 3: 'LB_MEMORY_CONFIG_3', +} +LB_MEMORY_CONFIG_0 = 0 +LB_MEMORY_CONFIG_1 = 1 +LB_MEMORY_CONFIG_2 = 2 +LB_MEMORY_CONFIG_3 = 3 +LB_MEMORY_CONFIG = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_BYPASS_SEL' +OBUF_BYPASS_SEL__enumvalues = { + 0: 'OBUF_BYPASS_DIS', + 1: 'OBUF_BYPASS_EN', +} +OBUF_BYPASS_DIS = 0 +OBUF_BYPASS_EN = 1 +OBUF_BYPASS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_IS_HALF_RECOUT_WIDTH_SEL' +OBUF_IS_HALF_RECOUT_WIDTH_SEL__enumvalues = { + 0: 'OBUF_FULL_RECOUT', + 1: 'OBUF_HALF_RECOUT', +} +OBUF_FULL_RECOUT = 0 +OBUF_HALF_RECOUT = 1 +OBUF_IS_HALF_RECOUT_WIDTH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OBUF_USE_FULL_BUFFER_SEL' +OBUF_USE_FULL_BUFFER_SEL__enumvalues = { + 0: 'OBUF_RECOUT', + 1: 'OBUF_FULL', +} +OBUF_RECOUT = 0 +OBUF_FULL = 1 +OBUF_USE_FULL_BUFFER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_2TAP_HARDCODE' +SCL_2TAP_HARDCODE__enumvalues = { + 0: 'SCL_COEF_2TAP_HARDCODE_OFF', + 1: 'SCL_COEF_2TAP_HARDCODE_ON', +} +SCL_COEF_2TAP_HARDCODE_OFF = 0 +SCL_COEF_2TAP_HARDCODE_ON = 1 +SCL_2TAP_HARDCODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_ALPHA_COEF' +SCL_ALPHA_COEF__enumvalues = { + 0: 'SCL_ALPHA_COEF_FIRST', + 1: 'SCL_ALPHA_COEF_SECOND', +} +SCL_ALPHA_COEF_FIRST = 0 +SCL_ALPHA_COEF_SECOND = 1 +SCL_ALPHA_COEF = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_AUTOCAL_MODE' +SCL_AUTOCAL_MODE__enumvalues = { + 0: 'AUTOCAL_MODE_OFF', + 1: 'AUTOCAL_MODE_AUTOSCALE', + 2: 'AUTOCAL_MODE_AUTOCENTER', + 3: 'AUTOCAL_MODE_AUTOREPLICATE', +} +AUTOCAL_MODE_OFF = 0 +AUTOCAL_MODE_AUTOSCALE = 1 +AUTOCAL_MODE_AUTOCENTER = 2 +AUTOCAL_MODE_AUTOREPLICATE = 3 +SCL_AUTOCAL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_BOUNDARY' +SCL_BOUNDARY__enumvalues = { + 0: 'SCL_BOUNDARY_EDGE', + 1: 'SCL_BOUNDARY_BLACK', +} +SCL_BOUNDARY_EDGE = 0 +SCL_BOUNDARY_BLACK = 1 +SCL_BOUNDARY = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_CHROMA_COEF' +SCL_CHROMA_COEF__enumvalues = { + 0: 'SCL_CHROMA_COEF_FIRST', + 1: 'SCL_CHROMA_COEF_SECOND', +} +SCL_CHROMA_COEF_FIRST = 0 +SCL_CHROMA_COEF_SECOND = 1 +SCL_CHROMA_COEF = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_COEF_FILTER_TYPE_SEL' +SCL_COEF_FILTER_TYPE_SEL__enumvalues = { + 0: 'SCL_COEF_LUMA_VERT_FILTER', + 1: 'SCL_COEF_LUMA_HORZ_FILTER', + 2: 'SCL_COEF_CHROMA_VERT_FILTER', + 3: 'SCL_COEF_CHROMA_HORZ_FILTER', +} +SCL_COEF_LUMA_VERT_FILTER = 0 +SCL_COEF_LUMA_HORZ_FILTER = 1 +SCL_COEF_CHROMA_VERT_FILTER = 2 +SCL_COEF_CHROMA_HORZ_FILTER = 3 +SCL_COEF_FILTER_TYPE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_COEF_RAM_SEL' +SCL_COEF_RAM_SEL__enumvalues = { + 0: 'SCL_COEF_RAM_SEL_0', + 1: 'SCL_COEF_RAM_SEL_1', +} +SCL_COEF_RAM_SEL_0 = 0 +SCL_COEF_RAM_SEL_1 = 1 +SCL_COEF_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SCL_SHARP_EN' +SCL_SHARP_EN__enumvalues = { + 0: 'SCL_SHARP_DISABLE', + 1: 'SCL_SHARP_ENABLE', +} +SCL_SHARP_DISABLE = 0 +SCL_SHARP_ENABLE = 1 +SCL_SHARP_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_30BIT_ENUM' +CMC_3DLUT_30BIT_ENUM__enumvalues = { + 0: 'CMC_3DLUT_36BIT', + 1: 'CMC_3DLUT_30BIT', +} +CMC_3DLUT_36BIT = 0 +CMC_3DLUT_30BIT = 1 +CMC_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_RAM_SEL' +CMC_3DLUT_RAM_SEL__enumvalues = { + 0: 'CMC_RAM0_ACCESS', + 1: 'CMC_RAM1_ACCESS', + 2: 'CMC_RAM2_ACCESS', + 3: 'CMC_RAM3_ACCESS', +} +CMC_RAM0_ACCESS = 0 +CMC_RAM1_ACCESS = 1 +CMC_RAM2_ACCESS = 2 +CMC_RAM3_ACCESS = 3 +CMC_3DLUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_3DLUT_SIZE_ENUM' +CMC_3DLUT_SIZE_ENUM__enumvalues = { + 0: 'CMC_3DLUT_17CUBE', + 1: 'CMC_3DLUT_9CUBE', +} +CMC_3DLUT_17CUBE = 0 +CMC_3DLUT_9CUBE = 1 +CMC_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_2_CONFIG_ENUM' +CMC_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'CMC_LUT_2CFG_NO_MEMORY', + 1: 'CMC_LUT_2CFG_MEMORY_A', + 2: 'CMC_LUT_2CFG_MEMORY_B', +} +CMC_LUT_2CFG_NO_MEMORY = 0 +CMC_LUT_2CFG_MEMORY_A = 1 +CMC_LUT_2CFG_MEMORY_B = 2 +CMC_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_2_MODE_ENUM' +CMC_LUT_2_MODE_ENUM__enumvalues = { + 0: 'CMC_LUT_2_MODE_BYPASS', + 1: 'CMC_LUT_2_MODE_RAMA_LUT', + 2: 'CMC_LUT_2_MODE_RAMB_LUT', +} +CMC_LUT_2_MODE_BYPASS = 0 +CMC_LUT_2_MODE_RAMA_LUT = 1 +CMC_LUT_2_MODE_RAMB_LUT = 2 +CMC_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_NUM_SEG' +CMC_LUT_NUM_SEG__enumvalues = { + 0: 'CMC_SEGMENTS_1', + 1: 'CMC_SEGMENTS_2', + 2: 'CMC_SEGMENTS_4', + 3: 'CMC_SEGMENTS_8', + 4: 'CMC_SEGMENTS_16', + 5: 'CMC_SEGMENTS_32', + 6: 'CMC_SEGMENTS_64', + 7: 'CMC_SEGMENTS_128', +} +CMC_SEGMENTS_1 = 0 +CMC_SEGMENTS_2 = 1 +CMC_SEGMENTS_4 = 2 +CMC_SEGMENTS_8 = 3 +CMC_SEGMENTS_16 = 4 +CMC_SEGMENTS_32 = 5 +CMC_SEGMENTS_64 = 6 +CMC_SEGMENTS_128 = 7 +CMC_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'CMC_LUT_RAM_SEL' +CMC_LUT_RAM_SEL__enumvalues = { + 0: 'CMC_RAMA_ACCESS', + 1: 'CMC_RAMB_ACCESS', +} +CMC_RAMA_ACCESS = 0 +CMC_RAMB_ACCESS = 1 +CMC_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_BYPASS' +CM_BYPASS__enumvalues = { + 0: 'NON_BYPASS', + 1: 'BYPASS_EN', +} +NON_BYPASS = 0 +BYPASS_EN = 1 +CM_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'CM_COEF_FORMAT_ENUM' +CM_COEF_FORMAT_ENUM__enumvalues = { + 0: 'FIX_S2_13', + 1: 'FIX_S3_12', +} +FIX_S2_13 = 0 +FIX_S3_12 = 1 +CM_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_DATA_SIGNED' +CM_DATA_SIGNED__enumvalues = { + 0: 'UNSIGNED', + 1: 'SIGNED', +} +UNSIGNED = 0 +SIGNED = 1 +CM_DATA_SIGNED = ctypes.c_uint32 # enum + +# values for enumeration 'CM_EN' +CM_EN__enumvalues = { + 0: 'CM_DISABLE', + 1: 'CM_ENABLE', +} +CM_DISABLE = 0 +CM_ENABLE = 1 +CM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMMA_LUT_MODE_ENUM' +CM_GAMMA_LUT_MODE_ENUM__enumvalues = { + 0: 'BYPASS', + 1: 'RESERVED_1', + 2: 'RAM_LUT', + 3: 'RESERVED_3', +} +BYPASS = 0 +RESERVED_1 = 1 +RAM_LUT = 2 +RESERVED_3 = 3 +CM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMMA_LUT_PWL_DISABLE_ENUM' +CM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { + 0: 'ENABLE_PWL', + 1: 'DISABLE_PWL', +} +ENABLE_PWL = 0 +DISABLE_PWL = 1 +CM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMMA_LUT_SEL_ENUM' +CM_GAMMA_LUT_SEL_ENUM__enumvalues = { + 0: 'RAMA', + 1: 'RAMB', +} +RAMA = 0 +RAMB = 1 +CM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_GAMUT_REMAP_MODE_ENUM' +CM_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'BYPASS_GAMUT', + 1: 'GAMUT_COEF', + 2: 'GAMUT_COEF_B', +} +BYPASS_GAMUT = 0 +GAMUT_COEF = 1 +GAMUT_COEF_B = 2 +CM_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_2_CONFIG_ENUM' +CM_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'LUT_2CFG_NO_MEMORY', + 1: 'LUT_2CFG_MEMORY_A', + 2: 'LUT_2CFG_MEMORY_B', +} +LUT_2CFG_NO_MEMORY = 0 +LUT_2CFG_MEMORY_A = 1 +LUT_2CFG_MEMORY_B = 2 +CM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_2_MODE_ENUM' +CM_LUT_2_MODE_ENUM__enumvalues = { + 0: 'LUT_2_MODE_BYPASS', + 1: 'LUT_2_MODE_RAMA_LUT', + 2: 'LUT_2_MODE_RAMB_LUT', +} +LUT_2_MODE_BYPASS = 0 +LUT_2_MODE_RAMA_LUT = 1 +LUT_2_MODE_RAMB_LUT = 2 +CM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_4_CONFIG_ENUM' +CM_LUT_4_CONFIG_ENUM__enumvalues = { + 0: 'LUT_4CFG_NO_MEMORY', + 1: 'LUT_4CFG_ROM_A', + 2: 'LUT_4CFG_ROM_B', + 3: 'LUT_4CFG_MEMORY_A', + 4: 'LUT_4CFG_MEMORY_B', +} +LUT_4CFG_NO_MEMORY = 0 +LUT_4CFG_ROM_A = 1 +LUT_4CFG_ROM_B = 2 +LUT_4CFG_MEMORY_A = 3 +LUT_4CFG_MEMORY_B = 4 +CM_LUT_4_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_4_MODE_ENUM' +CM_LUT_4_MODE_ENUM__enumvalues = { + 0: 'LUT_4_MODE_BYPASS', + 1: 'LUT_4_MODE_ROMA_LUT', + 2: 'LUT_4_MODE_ROMB_LUT', + 3: 'LUT_4_MODE_RAMA_LUT', + 4: 'LUT_4_MODE_RAMB_LUT', +} +LUT_4_MODE_BYPASS = 0 +LUT_4_MODE_ROMA_LUT = 1 +LUT_4_MODE_ROMB_LUT = 2 +LUT_4_MODE_RAMA_LUT = 3 +LUT_4_MODE_RAMB_LUT = 4 +CM_LUT_4_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_CONFIG_MODE' +CM_LUT_CONFIG_MODE__enumvalues = { + 0: 'DIFFERENT_RGB', + 1: 'ALL_USE_R', +} +DIFFERENT_RGB = 0 +ALL_USE_R = 1 +CM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_NUM_SEG' +CM_LUT_NUM_SEG__enumvalues = { + 0: 'SEGMENTS_1', + 1: 'SEGMENTS_2', + 2: 'SEGMENTS_4', + 3: 'SEGMENTS_8', + 4: 'SEGMENTS_16', + 5: 'SEGMENTS_32', + 6: 'SEGMENTS_64', + 7: 'SEGMENTS_128', +} +SEGMENTS_1 = 0 +SEGMENTS_2 = 1 +SEGMENTS_4 = 2 +SEGMENTS_8 = 3 +SEGMENTS_16 = 4 +SEGMENTS_32 = 5 +SEGMENTS_64 = 6 +SEGMENTS_128 = 7 +CM_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_RAM_SEL' +CM_LUT_RAM_SEL__enumvalues = { + 0: 'RAMA_ACCESS', + 1: 'RAMB_ACCESS', +} +RAMA_ACCESS = 0 +RAMB_ACCESS = 1 +CM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_READ_COLOR_SEL' +CM_LUT_READ_COLOR_SEL__enumvalues = { + 0: 'BLUE_LUT', + 1: 'GREEN_LUT', + 2: 'RED_LUT', +} +BLUE_LUT = 0 +GREEN_LUT = 1 +RED_LUT = 2 +CM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CM_LUT_READ_DBG' +CM_LUT_READ_DBG__enumvalues = { + 0: 'DISABLE_DEBUG', + 1: 'ENABLE_DEBUG', +} +DISABLE_DEBUG = 0 +ENABLE_DEBUG = 1 +CM_LUT_READ_DBG = ctypes.c_uint32 # enum + +# values for enumeration 'CM_PENDING' +CM_PENDING__enumvalues = { + 0: 'CM_NOT_PENDING', + 1: 'CM_YES_PENDING', +} +CM_NOT_PENDING = 0 +CM_YES_PENDING = 1 +CM_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'CM_POST_CSC_MODE_ENUM' +CM_POST_CSC_MODE_ENUM__enumvalues = { + 0: 'BYPASS_POST_CSC', + 1: 'COEF_POST_CSC', + 2: 'COEF_POST_CSC_B', +} +BYPASS_POST_CSC = 0 +COEF_POST_CSC = 1 +COEF_POST_CSC_B = 2 +CM_POST_CSC_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CM_WRITE_BASE_ONLY' +CM_WRITE_BASE_ONLY__enumvalues = { + 0: 'WRITE_BOTH', + 1: 'WRITE_BASE_ONLY', +} +WRITE_BOTH = 0 +WRITE_BASE_ONLY = 1 +CM_WRITE_BASE_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_CUR_SEL' +CRC_CUR_SEL__enumvalues = { + 0: 'CRC_CUR_0', + 1: 'CRC_CUR_1', +} +CRC_CUR_0 = 0 +CRC_CUR_1 = 1 +CRC_CUR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_INTERLACE_SEL' +CRC_INTERLACE_SEL__enumvalues = { + 0: 'CRC_INTERLACE_0', + 1: 'CRC_INTERLACE_1', + 2: 'CRC_INTERLACE_2', + 3: 'CRC_INTERLACE_3', +} +CRC_INTERLACE_0 = 0 +CRC_INTERLACE_1 = 1 +CRC_INTERLACE_2 = 2 +CRC_INTERLACE_3 = 3 +CRC_INTERLACE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_IN_CUR_SEL' +CRC_IN_CUR_SEL__enumvalues = { + 0: 'CRC_IN_CUR_0', + 1: 'CRC_IN_CUR_1', + 2: 'CRC_IN_CUR_2', + 3: 'CRC_IN_CUR_3', +} +CRC_IN_CUR_0 = 0 +CRC_IN_CUR_1 = 1 +CRC_IN_CUR_2 = 2 +CRC_IN_CUR_3 = 3 +CRC_IN_CUR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_IN_PIX_SEL' +CRC_IN_PIX_SEL__enumvalues = { + 0: 'CRC_IN_PIX_0', + 1: 'CRC_IN_PIX_1', + 2: 'CRC_IN_PIX_2', + 3: 'CRC_IN_PIX_3', + 4: 'CRC_IN_PIX_4', + 5: 'CRC_IN_PIX_5', + 6: 'CRC_IN_PIX_6', + 7: 'CRC_IN_PIX_7', +} +CRC_IN_PIX_0 = 0 +CRC_IN_PIX_1 = 1 +CRC_IN_PIX_2 = 2 +CRC_IN_PIX_3 = 3 +CRC_IN_PIX_4 = 4 +CRC_IN_PIX_5 = 5 +CRC_IN_PIX_6 = 6 +CRC_IN_PIX_7 = 7 +CRC_IN_PIX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_SRC_SEL' +CRC_SRC_SEL__enumvalues = { + 0: 'CRC_SRC_0', + 1: 'CRC_SRC_1', + 2: 'CRC_SRC_2', + 3: 'CRC_SRC_3', +} +CRC_SRC_0 = 0 +CRC_SRC_1 = 1 +CRC_SRC_2 = 2 +CRC_SRC_3 = 3 +CRC_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CRC_STEREO_SEL' +CRC_STEREO_SEL__enumvalues = { + 0: 'CRC_STEREO_0', + 1: 'CRC_STEREO_1', + 2: 'CRC_STEREO_2', + 3: 'CRC_STEREO_3', +} +CRC_STEREO_0 = 0 +CRC_STEREO_1 = 1 +CRC_STEREO_2 = 2 +CRC_STEREO_3 = 3 +CRC_STEREO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLK_SEL' +TEST_CLK_SEL__enumvalues = { + 0: 'TEST_CLK_SEL_0', + 1: 'TEST_CLK_SEL_1', + 2: 'TEST_CLK_SEL_2', + 3: 'TEST_CLK_SEL_3', + 4: 'TEST_CLK_SEL_4', + 5: 'TEST_CLK_SEL_5', + 6: 'TEST_CLK_SEL_6', + 7: 'TEST_CLK_SEL_7', +} +TEST_CLK_SEL_0 = 0 +TEST_CLK_SEL_1 = 1 +TEST_CLK_SEL_2 = 2 +TEST_CLK_SEL_3 = 3 +TEST_CLK_SEL_4 = 4 +TEST_CLK_SEL_5 = 5 +TEST_CLK_SEL_6 = 6 +TEST_CLK_SEL_7 = 7 +TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_ACTIVE' +PERFCOUNTER_ACTIVE__enumvalues = { + 0: 'PERFCOUNTER_IS_IDLE', + 1: 'PERFCOUNTER_IS_ACTIVE', +} +PERFCOUNTER_IS_IDLE = 0 +PERFCOUNTER_IS_ACTIVE = 1 +PERFCOUNTER_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT0_STATE' +PERFCOUNTER_CNT0_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT0_STATE_RESET', + 1: 'PERFCOUNTER_CNT0_STATE_START', + 2: 'PERFCOUNTER_CNT0_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT0_STATE_HW', +} +PERFCOUNTER_CNT0_STATE_RESET = 0 +PERFCOUNTER_CNT0_STATE_START = 1 +PERFCOUNTER_CNT0_STATE_FREEZE = 2 +PERFCOUNTER_CNT0_STATE_HW = 3 +PERFCOUNTER_CNT0_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT1_STATE' +PERFCOUNTER_CNT1_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT1_STATE_RESET', + 1: 'PERFCOUNTER_CNT1_STATE_START', + 2: 'PERFCOUNTER_CNT1_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT1_STATE_HW', +} +PERFCOUNTER_CNT1_STATE_RESET = 0 +PERFCOUNTER_CNT1_STATE_START = 1 +PERFCOUNTER_CNT1_STATE_FREEZE = 2 +PERFCOUNTER_CNT1_STATE_HW = 3 +PERFCOUNTER_CNT1_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT2_STATE' +PERFCOUNTER_CNT2_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT2_STATE_RESET', + 1: 'PERFCOUNTER_CNT2_STATE_START', + 2: 'PERFCOUNTER_CNT2_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT2_STATE_HW', +} +PERFCOUNTER_CNT2_STATE_RESET = 0 +PERFCOUNTER_CNT2_STATE_START = 1 +PERFCOUNTER_CNT2_STATE_FREEZE = 2 +PERFCOUNTER_CNT2_STATE_HW = 3 +PERFCOUNTER_CNT2_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT3_STATE' +PERFCOUNTER_CNT3_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT3_STATE_RESET', + 1: 'PERFCOUNTER_CNT3_STATE_START', + 2: 'PERFCOUNTER_CNT3_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT3_STATE_HW', +} +PERFCOUNTER_CNT3_STATE_RESET = 0 +PERFCOUNTER_CNT3_STATE_START = 1 +PERFCOUNTER_CNT3_STATE_FREEZE = 2 +PERFCOUNTER_CNT3_STATE_HW = 3 +PERFCOUNTER_CNT3_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT4_STATE' +PERFCOUNTER_CNT4_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT4_STATE_RESET', + 1: 'PERFCOUNTER_CNT4_STATE_START', + 2: 'PERFCOUNTER_CNT4_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT4_STATE_HW', +} +PERFCOUNTER_CNT4_STATE_RESET = 0 +PERFCOUNTER_CNT4_STATE_START = 1 +PERFCOUNTER_CNT4_STATE_FREEZE = 2 +PERFCOUNTER_CNT4_STATE_HW = 3 +PERFCOUNTER_CNT4_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT5_STATE' +PERFCOUNTER_CNT5_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT5_STATE_RESET', + 1: 'PERFCOUNTER_CNT5_STATE_START', + 2: 'PERFCOUNTER_CNT5_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT5_STATE_HW', +} +PERFCOUNTER_CNT5_STATE_RESET = 0 +PERFCOUNTER_CNT5_STATE_START = 1 +PERFCOUNTER_CNT5_STATE_FREEZE = 2 +PERFCOUNTER_CNT5_STATE_HW = 3 +PERFCOUNTER_CNT5_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT6_STATE' +PERFCOUNTER_CNT6_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT6_STATE_RESET', + 1: 'PERFCOUNTER_CNT6_STATE_START', + 2: 'PERFCOUNTER_CNT6_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT6_STATE_HW', +} +PERFCOUNTER_CNT6_STATE_RESET = 0 +PERFCOUNTER_CNT6_STATE_START = 1 +PERFCOUNTER_CNT6_STATE_FREEZE = 2 +PERFCOUNTER_CNT6_STATE_HW = 3 +PERFCOUNTER_CNT6_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNT7_STATE' +PERFCOUNTER_CNT7_STATE__enumvalues = { + 0: 'PERFCOUNTER_CNT7_STATE_RESET', + 1: 'PERFCOUNTER_CNT7_STATE_START', + 2: 'PERFCOUNTER_CNT7_STATE_FREEZE', + 3: 'PERFCOUNTER_CNT7_STATE_HW', +} +PERFCOUNTER_CNT7_STATE_RESET = 0 +PERFCOUNTER_CNT7_STATE_START = 1 +PERFCOUNTER_CNT7_STATE_FREEZE = 2 +PERFCOUNTER_CNT7_STATE_HW = 3 +PERFCOUNTER_CNT7_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTL_SEL' +PERFCOUNTER_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_CNTL_SEL_0', + 1: 'PERFCOUNTER_CNTL_SEL_1', + 2: 'PERFCOUNTER_CNTL_SEL_2', + 3: 'PERFCOUNTER_CNTL_SEL_3', + 4: 'PERFCOUNTER_CNTL_SEL_4', + 5: 'PERFCOUNTER_CNTL_SEL_5', + 6: 'PERFCOUNTER_CNTL_SEL_6', + 7: 'PERFCOUNTER_CNTL_SEL_7', +} +PERFCOUNTER_CNTL_SEL_0 = 0 +PERFCOUNTER_CNTL_SEL_1 = 1 +PERFCOUNTER_CNTL_SEL_2 = 2 +PERFCOUNTER_CNTL_SEL_3 = 3 +PERFCOUNTER_CNTL_SEL_4 = 4 +PERFCOUNTER_CNTL_SEL_5 = 5 +PERFCOUNTER_CNTL_SEL_6 = 6 +PERFCOUNTER_CNTL_SEL_7 = 7 +PERFCOUNTER_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CNTOFF_START_DIS' +PERFCOUNTER_CNTOFF_START_DIS__enumvalues = { + 0: 'PERFCOUNTER_CNTOFF_START_ENABLE', + 1: 'PERFCOUNTER_CNTOFF_START_DISABLE', +} +PERFCOUNTER_CNTOFF_START_ENABLE = 0 +PERFCOUNTER_CNTOFF_START_DISABLE = 1 +PERFCOUNTER_CNTOFF_START_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_COUNTED_VALUE_TYPE' +PERFCOUNTER_COUNTED_VALUE_TYPE__enumvalues = { + 0: 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 1: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 2: 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', +} +PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0 +PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 1 +PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 2 +PERFCOUNTER_COUNTED_VALUE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_CVALUE_SEL' +PERFCOUNTER_CVALUE_SEL__enumvalues = { + 0: 'PERFCOUNTER_CVALUE_SEL_47_0', + 1: 'PERFCOUNTER_CVALUE_SEL_15_0', + 2: 'PERFCOUNTER_CVALUE_SEL_31_16', + 3: 'PERFCOUNTER_CVALUE_SEL_47_32', + 4: 'PERFCOUNTER_CVALUE_SEL_11_0', + 5: 'PERFCOUNTER_CVALUE_SEL_23_12', + 6: 'PERFCOUNTER_CVALUE_SEL_35_24', + 7: 'PERFCOUNTER_CVALUE_SEL_47_36', +} +PERFCOUNTER_CVALUE_SEL_47_0 = 0 +PERFCOUNTER_CVALUE_SEL_15_0 = 1 +PERFCOUNTER_CVALUE_SEL_31_16 = 2 +PERFCOUNTER_CVALUE_SEL_47_32 = 3 +PERFCOUNTER_CVALUE_SEL_11_0 = 4 +PERFCOUNTER_CVALUE_SEL_23_12 = 5 +PERFCOUNTER_CVALUE_SEL_35_24 = 6 +PERFCOUNTER_CVALUE_SEL_47_36 = 7 +PERFCOUNTER_CVALUE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_CNTL_SEL' +PERFCOUNTER_HW_CNTL_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', + 1: 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', +} +PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0 +PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 1 +PERFCOUNTER_HW_CNTL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_STOP1_SEL' +PERFCOUNTER_HW_STOP1_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_STOP1_0', + 1: 'PERFCOUNTER_HW_STOP1_1', +} +PERFCOUNTER_HW_STOP1_0 = 0 +PERFCOUNTER_HW_STOP1_1 = 1 +PERFCOUNTER_HW_STOP1_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_HW_STOP2_SEL' +PERFCOUNTER_HW_STOP2_SEL__enumvalues = { + 0: 'PERFCOUNTER_HW_STOP2_0', + 1: 'PERFCOUNTER_HW_STOP2_1', +} +PERFCOUNTER_HW_STOP2_0 = 0 +PERFCOUNTER_HW_STOP2_1 = 1 +PERFCOUNTER_HW_STOP2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INC_MODE' +PERFCOUNTER_INC_MODE__enumvalues = { + 0: 'PERFCOUNTER_INC_MODE_MULTI_BIT', + 1: 'PERFCOUNTER_INC_MODE_BOTH_EDGE', + 2: 'PERFCOUNTER_INC_MODE_LSB', + 3: 'PERFCOUNTER_INC_MODE_POS_EDGE', + 4: 'PERFCOUNTER_INC_MODE_NEG_EDGE', +} +PERFCOUNTER_INC_MODE_MULTI_BIT = 0 +PERFCOUNTER_INC_MODE_BOTH_EDGE = 1 +PERFCOUNTER_INC_MODE_LSB = 2 +PERFCOUNTER_INC_MODE_POS_EDGE = 3 +PERFCOUNTER_INC_MODE_NEG_EDGE = 4 +PERFCOUNTER_INC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_EN' +PERFCOUNTER_INT_EN__enumvalues = { + 0: 'PERFCOUNTER_INT_DISABLE', + 1: 'PERFCOUNTER_INT_ENABLE', +} +PERFCOUNTER_INT_DISABLE = 0 +PERFCOUNTER_INT_ENABLE = 1 +PERFCOUNTER_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_INT_TYPE' +PERFCOUNTER_INT_TYPE__enumvalues = { + 0: 'PERFCOUNTER_INT_TYPE_LEVEL', + 1: 'PERFCOUNTER_INT_TYPE_PULSE', +} +PERFCOUNTER_INT_TYPE_LEVEL = 0 +PERFCOUNTER_INT_TYPE_PULSE = 1 +PERFCOUNTER_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_OFF_MASK' +PERFCOUNTER_OFF_MASK__enumvalues = { + 0: 'PERFCOUNTER_OFF_MASK_DISABLE', + 1: 'PERFCOUNTER_OFF_MASK_ENABLE', +} +PERFCOUNTER_OFF_MASK_DISABLE = 0 +PERFCOUNTER_OFF_MASK_ENABLE = 1 +PERFCOUNTER_OFF_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RESTART_EN' +PERFCOUNTER_RESTART_EN__enumvalues = { + 0: 'PERFCOUNTER_RESTART_DISABLE', + 1: 'PERFCOUNTER_RESTART_ENABLE', +} +PERFCOUNTER_RESTART_DISABLE = 0 +PERFCOUNTER_RESTART_ENABLE = 1 +PERFCOUNTER_RESTART_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_RUNEN_MODE' +PERFCOUNTER_RUNEN_MODE__enumvalues = { + 0: 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 1: 'PERFCOUNTER_RUNEN_MODE_EDGE', +} +PERFCOUNTER_RUNEN_MODE_LEVEL = 0 +PERFCOUNTER_RUNEN_MODE_EDGE = 1 +PERFCOUNTER_RUNEN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL0' +PERFCOUNTER_STATE_SEL0__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL0_LOCAL', +} +PERFCOUNTER_STATE_SEL0_GLOBAL = 0 +PERFCOUNTER_STATE_SEL0_LOCAL = 1 +PERFCOUNTER_STATE_SEL0 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL1' +PERFCOUNTER_STATE_SEL1__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL1_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL1_LOCAL', +} +PERFCOUNTER_STATE_SEL1_GLOBAL = 0 +PERFCOUNTER_STATE_SEL1_LOCAL = 1 +PERFCOUNTER_STATE_SEL1 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL2' +PERFCOUNTER_STATE_SEL2__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL2_LOCAL', +} +PERFCOUNTER_STATE_SEL2_GLOBAL = 0 +PERFCOUNTER_STATE_SEL2_LOCAL = 1 +PERFCOUNTER_STATE_SEL2 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL3' +PERFCOUNTER_STATE_SEL3__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL3_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL3_LOCAL', +} +PERFCOUNTER_STATE_SEL3_GLOBAL = 0 +PERFCOUNTER_STATE_SEL3_LOCAL = 1 +PERFCOUNTER_STATE_SEL3 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL4' +PERFCOUNTER_STATE_SEL4__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL4_LOCAL', +} +PERFCOUNTER_STATE_SEL4_GLOBAL = 0 +PERFCOUNTER_STATE_SEL4_LOCAL = 1 +PERFCOUNTER_STATE_SEL4 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL5' +PERFCOUNTER_STATE_SEL5__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL5_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL5_LOCAL', +} +PERFCOUNTER_STATE_SEL5_GLOBAL = 0 +PERFCOUNTER_STATE_SEL5_LOCAL = 1 +PERFCOUNTER_STATE_SEL5 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL6' +PERFCOUNTER_STATE_SEL6__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL6_LOCAL', +} +PERFCOUNTER_STATE_SEL6_GLOBAL = 0 +PERFCOUNTER_STATE_SEL6_LOCAL = 1 +PERFCOUNTER_STATE_SEL6 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFCOUNTER_STATE_SEL7' +PERFCOUNTER_STATE_SEL7__enumvalues = { + 0: 'PERFCOUNTER_STATE_SEL7_GLOBAL', + 1: 'PERFCOUNTER_STATE_SEL7_LOCAL', +} +PERFCOUNTER_STATE_SEL7_GLOBAL = 0 +PERFCOUNTER_STATE_SEL7_LOCAL = 1 +PERFCOUNTER_STATE_SEL7 = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_AND_OR' +PERFMON_CNTOFF_AND_OR__enumvalues = { + 0: 'PERFMON_CNTOFF_OR', + 1: 'PERFMON_CNTOFF_AND', +} +PERFMON_CNTOFF_OR = 0 +PERFMON_CNTOFF_AND = 1 +PERFMON_CNTOFF_AND_OR = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_EN' +PERFMON_CNTOFF_INT_EN__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_DISABLE', + 1: 'PERFMON_CNTOFF_INT_ENABLE', +} +PERFMON_CNTOFF_INT_DISABLE = 0 +PERFMON_CNTOFF_INT_ENABLE = 1 +PERFMON_CNTOFF_INT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_CNTOFF_INT_TYPE' +PERFMON_CNTOFF_INT_TYPE__enumvalues = { + 0: 'PERFMON_CNTOFF_INT_TYPE_LEVEL', + 1: 'PERFMON_CNTOFF_INT_TYPE_PULSE', +} +PERFMON_CNTOFF_INT_TYPE_LEVEL = 0 +PERFMON_CNTOFF_INT_TYPE_PULSE = 1 +PERFMON_CNTOFF_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'PERFMON_STATE' +PERFMON_STATE__enumvalues = { + 0: 'PERFMON_STATE_RESET', + 1: 'PERFMON_STATE_START', + 2: 'PERFMON_STATE_FREEZE', + 3: 'PERFMON_STATE_HW', +} +PERFMON_STATE_RESET = 0 +PERFMON_STATE_START = 1 +PERFMON_STATE_FREEZE = 2 +PERFMON_STATE_HW = 3 +PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'BIGK_FRAGMENT_SIZE' +BIGK_FRAGMENT_SIZE__enumvalues = { + 0: 'VM_PG_SIZE_4KB', + 1: 'VM_PG_SIZE_8KB', + 2: 'VM_PG_SIZE_16KB', + 3: 'VM_PG_SIZE_32KB', + 4: 'VM_PG_SIZE_64KB', + 5: 'VM_PG_SIZE_128KB', + 6: 'VM_PG_SIZE_256KB', + 7: 'VM_PG_SIZE_512KB', + 8: 'VM_PG_SIZE_1024KB', + 9: 'VM_PG_SIZE_2048KB', +} +VM_PG_SIZE_4KB = 0 +VM_PG_SIZE_8KB = 1 +VM_PG_SIZE_16KB = 2 +VM_PG_SIZE_32KB = 3 +VM_PG_SIZE_64KB = 4 +VM_PG_SIZE_128KB = 5 +VM_PG_SIZE_256KB = 6 +VM_PG_SIZE_512KB = 7 +VM_PG_SIZE_1024KB = 8 +VM_PG_SIZE_2048KB = 9 +BIGK_FRAGMENT_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'CHUNK_SIZE' +CHUNK_SIZE__enumvalues = { + 0: 'CHUNK_SIZE_1KB', + 1: 'CHUNK_SIZE_2KB', + 2: 'CHUNK_SIZE_4KB', + 3: 'CHUNK_SIZE_8KB', + 4: 'CHUNK_SIZE_16KB', + 5: 'CHUNK_SIZE_32KB', + 6: 'CHUNK_SIZE_64KB', +} +CHUNK_SIZE_1KB = 0 +CHUNK_SIZE_2KB = 1 +CHUNK_SIZE_4KB = 2 +CHUNK_SIZE_8KB = 3 +CHUNK_SIZE_16KB = 4 +CHUNK_SIZE_32KB = 5 +CHUNK_SIZE_64KB = 6 +CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'COMPAT_LEVEL' +COMPAT_LEVEL__enumvalues = { + 0: 'ADDR_GEN_ZERO', + 1: 'ADDR_GEN_ONE', + 2: 'ADDR_GEN_TWO', + 3: 'ADDR_RESERVED', +} +ADDR_GEN_ZERO = 0 +ADDR_GEN_ONE = 1 +ADDR_GEN_TWO = 2 +ADDR_RESERVED = 3 +COMPAT_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPTE_GROUP_SIZE' +DPTE_GROUP_SIZE__enumvalues = { + 0: 'DPTE_GROUP_SIZE_64B', + 1: 'DPTE_GROUP_SIZE_128B', + 2: 'DPTE_GROUP_SIZE_256B', + 3: 'DPTE_GROUP_SIZE_512B', + 4: 'DPTE_GROUP_SIZE_1024B', + 5: 'DPTE_GROUP_SIZE_2048B', +} +DPTE_GROUP_SIZE_64B = 0 +DPTE_GROUP_SIZE_128B = 1 +DPTE_GROUP_SIZE_256B = 2 +DPTE_GROUP_SIZE_512B = 3 +DPTE_GROUP_SIZE_1024B = 4 +DPTE_GROUP_SIZE_2048B = 5 +DPTE_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'FORCE_ONE_ROW_FOR_FRAME' +FORCE_ONE_ROW_FOR_FRAME__enumvalues = { + 0: 'FORCE_ONE_ROW_FOR_FRAME_0', + 1: 'FORCE_ONE_ROW_FOR_FRAME_1', +} +FORCE_ONE_ROW_FOR_FRAME_0 = 0 +FORCE_ONE_ROW_FOR_FRAME_1 = 1 +FORCE_ONE_ROW_FOR_FRAME = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_BLANK_EN' +HUBP_BLANK_EN__enumvalues = { + 0: 'HUBP_BLANK_SW_DEASSERT', + 1: 'HUBP_BLANK_SW_ASSERT', +} +HUBP_BLANK_SW_DEASSERT = 0 +HUBP_BLANK_SW_ASSERT = 1 +HUBP_BLANK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_IN_BLANK' +HUBP_IN_BLANK__enumvalues = { + 0: 'HUBP_IN_ACTIVE', + 1: 'HUBP_IN_VBLANK', +} +HUBP_IN_ACTIVE = 0 +HUBP_IN_VBLANK = 1 +HUBP_IN_BLANK = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_MEASURE_WIN_MODE_DCFCLK' +HUBP_MEASURE_WIN_MODE_DCFCLK__enumvalues = { + 0: 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', + 1: 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', + 2: 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', + 3: 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', +} +HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0 +HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 1 +HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 2 +HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 3 +HUBP_MEASURE_WIN_MODE_DCFCLK = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_NO_OUTSTANDING_REQ' +HUBP_NO_OUTSTANDING_REQ__enumvalues = { + 0: 'OUTSTANDING_REQ', + 1: 'NO_OUTSTANDING_REQ', +} +OUTSTANDING_REQ = 0 +NO_OUTSTANDING_REQ = 1 +HUBP_NO_OUTSTANDING_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_SOFT_RESET' +HUBP_SOFT_RESET__enumvalues = { + 0: 'HUBP_SOFT_RESET_ON', + 1: 'HUBP_SOFT_RESET_OFF', +} +HUBP_SOFT_RESET_ON = 0 +HUBP_SOFT_RESET_OFF = 1 +HUBP_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_TTU_DISABLE' +HUBP_TTU_DISABLE__enumvalues = { + 0: 'HUBP_TTU_ENABLED', + 1: 'HUBP_TTU_DISABLED', +} +HUBP_TTU_ENABLED = 0 +HUBP_TTU_DISABLED = 1 +HUBP_TTU_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_VREADY_AT_OR_AFTER_VSYNC' +HUBP_VREADY_AT_OR_AFTER_VSYNC__enumvalues = { + 0: 'VREADY_BEFORE_VSYNC', + 1: 'VREADY_AT_OR_AFTER_VSYNC', +} +VREADY_BEFORE_VSYNC = 0 +VREADY_AT_OR_AFTER_VSYNC = 1 +HUBP_VREADY_AT_OR_AFTER_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'HUBP_VTG_SEL' +HUBP_VTG_SEL__enumvalues = { + 0: 'VTG_SEL_0', + 1: 'VTG_SEL_1', + 2: 'VTG_SEL_2', + 3: 'VTG_SEL_3', + 4: 'VTG_SEL_4', + 5: 'VTG_SEL_5', +} +VTG_SEL_0 = 0 +VTG_SEL_1 = 1 +VTG_SEL_2 = 2 +VTG_SEL_3 = 3 +VTG_SEL_4 = 4 +VTG_SEL_5 = 5 +HUBP_VTG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'H_MIRROR_EN' +H_MIRROR_EN__enumvalues = { + 0: 'HW_MIRRORING_DISABLE', + 1: 'HW_MIRRORING_ENABLE', +} +HW_MIRRORING_DISABLE = 0 +HW_MIRRORING_ENABLE = 1 +H_MIRROR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'LEGACY_PIPE_INTERLEAVE' +LEGACY_PIPE_INTERLEAVE__enumvalues = { + 0: 'LEGACY_PIPE_INTERLEAVE_256B', + 1: 'LEGACY_PIPE_INTERLEAVE_512B', +} +LEGACY_PIPE_INTERLEAVE_256B = 0 +LEGACY_PIPE_INTERLEAVE_512B = 1 +LEGACY_PIPE_INTERLEAVE = ctypes.c_uint32 # enum + +# values for enumeration 'META_CHUNK_SIZE' +META_CHUNK_SIZE__enumvalues = { + 0: 'META_CHUNK_SIZE_1KB', + 1: 'META_CHUNK_SIZE_2KB', + 2: 'META_CHUNK_SIZE_4KB', + 3: 'META_CHUNK_SIZE_8KB', +} +META_CHUNK_SIZE_1KB = 0 +META_CHUNK_SIZE_2KB = 1 +META_CHUNK_SIZE_4KB = 2 +META_CHUNK_SIZE_8KB = 3 +META_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'META_LINEAR' +META_LINEAR__enumvalues = { + 0: 'META_SURF_TILED', + 1: 'META_SURF_LINEAR', +} +META_SURF_TILED = 0 +META_SURF_LINEAR = 1 +META_LINEAR = ctypes.c_uint32 # enum + +# values for enumeration 'MIN_CHUNK_SIZE' +MIN_CHUNK_SIZE__enumvalues = { + 0: 'NO_MIN_CHUNK_SIZE', + 1: 'MIN_CHUNK_SIZE_256B', + 2: 'MIN_CHUNK_SIZE_512B', + 3: 'MIN_CHUNK_SIZE_1024B', +} +NO_MIN_CHUNK_SIZE = 0 +MIN_CHUNK_SIZE_256B = 1 +MIN_CHUNK_SIZE_512B = 2 +MIN_CHUNK_SIZE_1024B = 3 +MIN_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'MIN_META_CHUNK_SIZE' +MIN_META_CHUNK_SIZE__enumvalues = { + 0: 'NO_MIN_META_CHUNK_SIZE', + 1: 'MIN_META_CHUNK_SIZE_64B', + 2: 'MIN_META_CHUNK_SIZE_128B', + 3: 'MIN_META_CHUNK_SIZE_256B', +} +NO_MIN_META_CHUNK_SIZE = 0 +MIN_META_CHUNK_SIZE_64B = 1 +MIN_META_CHUNK_SIZE_128B = 2 +MIN_META_CHUNK_SIZE_256B = 3 +MIN_META_CHUNK_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_ALIGNED' +PIPE_ALIGNED__enumvalues = { + 0: 'PIPE_UNALIGNED_SURF', + 1: 'PIPE_ALIGNED_SURF', +} +PIPE_UNALIGNED_SURF = 0 +PIPE_ALIGNED_SURF = 1 +PIPE_ALIGNED = ctypes.c_uint32 # enum + +# values for enumeration 'PTE_BUFFER_MODE' +PTE_BUFFER_MODE__enumvalues = { + 0: 'PTE_BUFFER_MODE_0', + 1: 'PTE_BUFFER_MODE_1', +} +PTE_BUFFER_MODE_0 = 0 +PTE_BUFFER_MODE_1 = 1 +PTE_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PTE_ROW_HEIGHT_LINEAR' +PTE_ROW_HEIGHT_LINEAR__enumvalues = { + 0: 'PTE_ROW_HEIGHT_LINEAR_8L', + 1: 'PTE_ROW_HEIGHT_LINEAR_16L', + 2: 'PTE_ROW_HEIGHT_LINEAR_32L', + 3: 'PTE_ROW_HEIGHT_LINEAR_64L', + 4: 'PTE_ROW_HEIGHT_LINEAR_128L', + 5: 'PTE_ROW_HEIGHT_LINEAR_256L', + 6: 'PTE_ROW_HEIGHT_LINEAR_512L', + 7: 'PTE_ROW_HEIGHT_LINEAR_1024L', +} +PTE_ROW_HEIGHT_LINEAR_8L = 0 +PTE_ROW_HEIGHT_LINEAR_16L = 1 +PTE_ROW_HEIGHT_LINEAR_32L = 2 +PTE_ROW_HEIGHT_LINEAR_64L = 3 +PTE_ROW_HEIGHT_LINEAR_128L = 4 +PTE_ROW_HEIGHT_LINEAR_256L = 5 +PTE_ROW_HEIGHT_LINEAR_512L = 6 +PTE_ROW_HEIGHT_LINEAR_1024L = 7 +PTE_ROW_HEIGHT_LINEAR = ctypes.c_uint32 # enum + +# values for enumeration 'ROTATION_ANGLE' +ROTATION_ANGLE__enumvalues = { + 0: 'ROTATE_0_DEGREES', + 1: 'ROTATE_90_DEGREES', + 2: 'ROTATE_180_DEGREES', + 3: 'ROTATE_270_DEGREES', +} +ROTATE_0_DEGREES = 0 +ROTATE_90_DEGREES = 1 +ROTATE_180_DEGREES = 2 +ROTATE_270_DEGREES = 3 +ROTATION_ANGLE = ctypes.c_uint32 # enum + +# values for enumeration 'SWATH_HEIGHT' +SWATH_HEIGHT__enumvalues = { + 0: 'SWATH_HEIGHT_1L', + 1: 'SWATH_HEIGHT_2L', + 2: 'SWATH_HEIGHT_4L', + 3: 'SWATH_HEIGHT_8L', + 4: 'SWATH_HEIGHT_16L', +} +SWATH_HEIGHT_1L = 0 +SWATH_HEIGHT_2L = 1 +SWATH_HEIGHT_4L = 2 +SWATH_HEIGHT_8L = 3 +SWATH_HEIGHT_16L = 4 +SWATH_HEIGHT = ctypes.c_uint32 # enum + +# values for enumeration 'USE_MALL_FOR_CURSOR' +USE_MALL_FOR_CURSOR__enumvalues = { + 0: 'USE_MALL_FOR_CURSOR_0', + 1: 'USE_MALL_FOR_CURSOR_1', +} +USE_MALL_FOR_CURSOR_0 = 0 +USE_MALL_FOR_CURSOR_1 = 1 +USE_MALL_FOR_CURSOR = ctypes.c_uint32 # enum + +# values for enumeration 'USE_MALL_FOR_PSTATE_CHANGE' +USE_MALL_FOR_PSTATE_CHANGE__enumvalues = { + 0: 'USE_MALL_FOR_PSTATE_CHANGE_0', + 1: 'USE_MALL_FOR_PSTATE_CHANGE_1', +} +USE_MALL_FOR_PSTATE_CHANGE_0 = 0 +USE_MALL_FOR_PSTATE_CHANGE_1 = 1 +USE_MALL_FOR_PSTATE_CHANGE = ctypes.c_uint32 # enum + +# values for enumeration 'USE_MALL_FOR_STATIC_SCREEN' +USE_MALL_FOR_STATIC_SCREEN__enumvalues = { + 0: 'USE_MALL_FOR_STATIC_SCREEN_0', + 1: 'USE_MALL_FOR_STATIC_SCREEN_1', +} +USE_MALL_FOR_STATIC_SCREEN_0 = 0 +USE_MALL_FOR_STATIC_SCREEN_1 = 1 +USE_MALL_FOR_STATIC_SCREEN = ctypes.c_uint32 # enum + +# values for enumeration 'VMPG_SIZE' +VMPG_SIZE__enumvalues = { + 0: 'VMPG_SIZE_4KB', + 1: 'VMPG_SIZE_64KB', +} +VMPG_SIZE_4KB = 0 +VMPG_SIZE_64KB = 1 +VMPG_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'VM_GROUP_SIZE' +VM_GROUP_SIZE__enumvalues = { + 0: 'VM_GROUP_SIZE_64B', + 1: 'VM_GROUP_SIZE_128B', + 2: 'VM_GROUP_SIZE_256B', + 3: 'VM_GROUP_SIZE_512B', + 4: 'VM_GROUP_SIZE_1024B', + 5: 'VM_GROUP_SIZE_2048B', +} +VM_GROUP_SIZE_64B = 0 +VM_GROUP_SIZE_128B = 1 +VM_GROUP_SIZE_256B = 2 +VM_GROUP_SIZE_512B = 3 +VM_GROUP_SIZE_1024B = 4 +VM_GROUP_SIZE_2048B = 5 +VM_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_MIN_FREE_ENTRIES' +DFQ_MIN_FREE_ENTRIES__enumvalues = { + 0: 'DFQ_MIN_FREE_ENTRIES_0', + 1: 'DFQ_MIN_FREE_ENTRIES_1', + 2: 'DFQ_MIN_FREE_ENTRIES_2', + 3: 'DFQ_MIN_FREE_ENTRIES_3', + 4: 'DFQ_MIN_FREE_ENTRIES_4', + 5: 'DFQ_MIN_FREE_ENTRIES_5', + 6: 'DFQ_MIN_FREE_ENTRIES_6', + 7: 'DFQ_MIN_FREE_ENTRIES_7', +} +DFQ_MIN_FREE_ENTRIES_0 = 0 +DFQ_MIN_FREE_ENTRIES_1 = 1 +DFQ_MIN_FREE_ENTRIES_2 = 2 +DFQ_MIN_FREE_ENTRIES_3 = 3 +DFQ_MIN_FREE_ENTRIES_4 = 4 +DFQ_MIN_FREE_ENTRIES_5 = 5 +DFQ_MIN_FREE_ENTRIES_6 = 6 +DFQ_MIN_FREE_ENTRIES_7 = 7 +DFQ_MIN_FREE_ENTRIES = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_NUM_ENTRIES' +DFQ_NUM_ENTRIES__enumvalues = { + 0: 'DFQ_NUM_ENTRIES_0', + 1: 'DFQ_NUM_ENTRIES_1', + 2: 'DFQ_NUM_ENTRIES_2', + 3: 'DFQ_NUM_ENTRIES_3', + 4: 'DFQ_NUM_ENTRIES_4', + 5: 'DFQ_NUM_ENTRIES_5', + 6: 'DFQ_NUM_ENTRIES_6', + 7: 'DFQ_NUM_ENTRIES_7', + 8: 'DFQ_NUM_ENTRIES_8', +} +DFQ_NUM_ENTRIES_0 = 0 +DFQ_NUM_ENTRIES_1 = 1 +DFQ_NUM_ENTRIES_2 = 2 +DFQ_NUM_ENTRIES_3 = 3 +DFQ_NUM_ENTRIES_4 = 4 +DFQ_NUM_ENTRIES_5 = 5 +DFQ_NUM_ENTRIES_6 = 6 +DFQ_NUM_ENTRIES_7 = 7 +DFQ_NUM_ENTRIES_8 = 8 +DFQ_NUM_ENTRIES = ctypes.c_uint32 # enum + +# values for enumeration 'DFQ_SIZE' +DFQ_SIZE__enumvalues = { + 0: 'DFQ_SIZE_0', + 1: 'DFQ_SIZE_1', + 2: 'DFQ_SIZE_2', + 3: 'DFQ_SIZE_3', + 4: 'DFQ_SIZE_4', + 5: 'DFQ_SIZE_5', + 6: 'DFQ_SIZE_6', + 7: 'DFQ_SIZE_7', +} +DFQ_SIZE_0 = 0 +DFQ_SIZE_1 = 1 +DFQ_SIZE_2 = 2 +DFQ_SIZE_3 = 3 +DFQ_SIZE_4 = 4 +DFQ_SIZE_5 = 5 +DFQ_SIZE_6 = 6 +DFQ_SIZE_7 = 7 +DFQ_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_VM_DONE' +DMDATA_VM_DONE__enumvalues = { + 0: 'DMDATA_VM_IS_NOT_DONE', + 1: 'DMDATA_VM_IS_DONE', +} +DMDATA_VM_IS_NOT_DONE = 0 +DMDATA_VM_IS_DONE = 1 +DMDATA_VM_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'EXPANSION_MODE' +EXPANSION_MODE__enumvalues = { + 0: 'EXPANSION_MODE_ZERO', + 1: 'EXPANSION_MODE_CONSERVATIVE', + 2: 'EXPANSION_MODE_OPTIMAL', +} +EXPANSION_MODE_ZERO = 0 +EXPANSION_MODE_CONSERVATIVE = 1 +EXPANSION_MODE_OPTIMAL = 2 +EXPANSION_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FLIP_RATE' +FLIP_RATE__enumvalues = { + 0: 'FLIP_RATE_0', + 1: 'FLIP_RATE_1', + 2: 'FLIP_RATE_2', + 3: 'FLIP_RATE_3', + 4: 'FLIP_RATE_4', + 5: 'FLIP_RATE_5', + 6: 'FLIP_RATE_6', + 7: 'FLIP_RATE_7', +} +FLIP_RATE_0 = 0 +FLIP_RATE_1 = 1 +FLIP_RATE_2 = 2 +FLIP_RATE_3 = 3 +FLIP_RATE_4 = 4 +FLIP_RATE_5 = 5 +FLIP_RATE_6 = 6 +FLIP_RATE_7 = 7 +FLIP_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'INT_MASK' +INT_MASK__enumvalues = { + 0: 'INT_DISABLED', + 1: 'INT_ENABLED', +} +INT_DISABLED = 0 +INT_ENABLED = 1 +INT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_IN_FLUSH_URGENT' +PIPE_IN_FLUSH_URGENT__enumvalues = { + 0: 'PIPE_IN_FLUSH_URGENT_ENABLE', + 1: 'PIPE_IN_FLUSH_URGENT_DISABLE', +} +PIPE_IN_FLUSH_URGENT_ENABLE = 0 +PIPE_IN_FLUSH_URGENT_DISABLE = 1 +PIPE_IN_FLUSH_URGENT = ctypes.c_uint32 # enum + +# values for enumeration 'PRQ_MRQ_FLUSH_URGENT' +PRQ_MRQ_FLUSH_URGENT__enumvalues = { + 0: 'PRQ_MRQ_FLUSH_URGENT_ENABLE', + 1: 'PRQ_MRQ_FLUSH_URGENT_DISABLE', +} +PRQ_MRQ_FLUSH_URGENT_ENABLE = 0 +PRQ_MRQ_FLUSH_URGENT_DISABLE = 1 +PRQ_MRQ_FLUSH_URGENT = ctypes.c_uint32 # enum + +# values for enumeration 'ROW_TTU_MODE' +ROW_TTU_MODE__enumvalues = { + 0: 'END_OF_ROW_MODE', + 1: 'WATERMARK_MODE', +} +END_OF_ROW_MODE = 0 +WATERMARK_MODE = 1 +ROW_TTU_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC' +SURFACE_DCC__enumvalues = { + 0: 'SURFACE_IS_NOT_DCC', + 1: 'SURFACE_IS_DCC', +} +SURFACE_IS_NOT_DCC = 0 +SURFACE_IS_DCC = 1 +SURFACE_DCC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_128B' +SURFACE_DCC_IND_128B__enumvalues = { + 0: 'SURFACE_DCC_IS_NOT_IND_128B', + 1: 'SURFACE_DCC_IS_IND_128B', +} +SURFACE_DCC_IS_NOT_IND_128B = 0 +SURFACE_DCC_IS_IND_128B = 1 +SURFACE_DCC_IND_128B = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_64B' +SURFACE_DCC_IND_64B__enumvalues = { + 0: 'SURFACE_DCC_IS_NOT_IND_64B', + 1: 'SURFACE_DCC_IS_IND_64B', +} +SURFACE_DCC_IS_NOT_IND_64B = 0 +SURFACE_DCC_IS_IND_64B = 1 +SURFACE_DCC_IND_64B = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_DCC_IND_BLK' +SURFACE_DCC_IND_BLK__enumvalues = { + 0: 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', + 1: 'SURFACE_DCC_BLOCK_IS_IND_64B', + 2: 'SURFACE_DCC_BLOCK_IS_IND_128B', + 3: 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', +} +SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0 +SURFACE_DCC_BLOCK_IS_IND_64B = 1 +SURFACE_DCC_BLOCK_IS_IND_128B = 2 +SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 3 +SURFACE_DCC_IND_BLK = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_AWAY_INT_TYPE' +SURFACE_FLIP_AWAY_INT_TYPE__enumvalues = { + 0: 'SURFACE_FLIP_AWAY_INT_LEVEL', + 1: 'SURFACE_FLIP_AWAY_INT_PULSE', +} +SURFACE_FLIP_AWAY_INT_LEVEL = 0 +SURFACE_FLIP_AWAY_INT_PULSE = 1 +SURFACE_FLIP_AWAY_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_EXEC_DEBUG_MODE' +SURFACE_FLIP_EXEC_DEBUG_MODE__enumvalues = { + 0: 'SURFACE_FLIP_EXEC_NORMAL_MODE', + 1: 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', +} +SURFACE_FLIP_EXEC_NORMAL_MODE = 0 +SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 1 +SURFACE_FLIP_EXEC_DEBUG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_INT_TYPE' +SURFACE_FLIP_INT_TYPE__enumvalues = { + 0: 'SURFACE_FLIP_INT_LEVEL', + 1: 'SURFACE_FLIP_INT_PULSE', +} +SURFACE_FLIP_INT_LEVEL = 0 +SURFACE_FLIP_INT_PULSE = 1 +SURFACE_FLIP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_IN_STEREOSYNC' +SURFACE_FLIP_IN_STEREOSYNC__enumvalues = { + 0: 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', + 1: 'SURFACE_FLIP_IN_STEREOSYNC_MODE', +} +SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0 +SURFACE_FLIP_IN_STEREOSYNC_MODE = 1 +SURFACE_FLIP_IN_STEREOSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_MODE_FOR_STEREOSYNC' +SURFACE_FLIP_MODE_FOR_STEREOSYNC__enumvalues = { + 0: 'FLIP_ANY_FRAME', + 1: 'FLIP_LEFT_EYE', + 2: 'FLIP_RIGHT_EYE', + 3: 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', +} +FLIP_ANY_FRAME = 0 +FLIP_LEFT_EYE = 1 +FLIP_RIGHT_EYE = 2 +SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 3 +SURFACE_FLIP_MODE_FOR_STEREOSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_DISABLE' +SURFACE_FLIP_STEREO_SELECT_DISABLE__enumvalues = { + 0: 'SURFACE_FLIP_STEREO_SELECT_ENABLED', + 1: 'SURFACE_FLIP_STEREO_SELECT_DISABLED', +} +SURFACE_FLIP_STEREO_SELECT_ENABLED = 0 +SURFACE_FLIP_STEREO_SELECT_DISABLED = 1 +SURFACE_FLIP_STEREO_SELECT_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_STEREO_SELECT_POLARITY' +SURFACE_FLIP_STEREO_SELECT_POLARITY__enumvalues = { + 0: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', + 1: 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', +} +SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0 +SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 1 +SURFACE_FLIP_STEREO_SELECT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_TYPE' +SURFACE_FLIP_TYPE__enumvalues = { + 0: 'SURFACE_V_FLIP', + 1: 'SURFACE_I_FLIP', +} +SURFACE_V_FLIP = 0 +SURFACE_I_FLIP = 1 +SURFACE_FLIP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_FLIP_VUPDATE_SKIP_NUM' +SURFACE_FLIP_VUPDATE_SKIP_NUM__enumvalues = { + 0: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', + 1: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', + 2: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', + 3: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', + 4: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', + 5: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', + 6: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', + 7: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', + 8: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', + 9: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', + 10: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', + 11: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', + 12: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', + 13: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', + 14: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', + 15: 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', +} +SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0 +SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 1 +SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 2 +SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 3 +SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 4 +SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 5 +SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 6 +SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 7 +SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 8 +SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 9 +SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 10 +SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 11 +SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 12 +SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 13 +SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 14 +SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 15 +SURFACE_FLIP_VUPDATE_SKIP_NUM = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_INUSE_RAED_NO_LATCH' +SURFACE_INUSE_RAED_NO_LATCH__enumvalues = { + 0: 'SURFACE_INUSE_IS_LATCHED', + 1: 'SURFACE_INUSE_IS_NOT_LATCHED', +} +SURFACE_INUSE_IS_LATCHED = 0 +SURFACE_INUSE_IS_NOT_LATCHED = 1 +SURFACE_INUSE_RAED_NO_LATCH = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_TMZ' +SURFACE_TMZ__enumvalues = { + 0: 'SURFACE_IS_NOT_TMZ', + 1: 'SURFACE_IS_TMZ', +} +SURFACE_IS_NOT_TMZ = 0 +SURFACE_IS_TMZ = 1 +SURFACE_TMZ = ctypes.c_uint32 # enum + +# values for enumeration 'SURFACE_UPDATE_LOCK' +SURFACE_UPDATE_LOCK__enumvalues = { + 0: 'SURFACE_UPDATE_IS_UNLOCKED', + 1: 'SURFACE_UPDATE_IS_LOCKED', +} +SURFACE_UPDATE_IS_UNLOCKED = 0 +SURFACE_UPDATE_IS_LOCKED = 1 +SURFACE_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_ALPHA' +CROSSBAR_FOR_ALPHA__enumvalues = { + 0: 'ALPHA_DATA_ONTO_ALPHA_PORT', + 1: 'Y_G_DATA_ONTO_ALPHA_PORT', + 2: 'CB_B_DATA_ONTO_ALPHA_PORT', + 3: 'CR_R_DATA_ONTO_ALPHA_PORT', +} +ALPHA_DATA_ONTO_ALPHA_PORT = 0 +Y_G_DATA_ONTO_ALPHA_PORT = 1 +CB_B_DATA_ONTO_ALPHA_PORT = 2 +CR_R_DATA_ONTO_ALPHA_PORT = 3 +CROSSBAR_FOR_ALPHA = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_CB_B' +CROSSBAR_FOR_CB_B__enumvalues = { + 0: 'ALPHA_DATA_ONTO_CB_B_PORT', + 1: 'Y_G_DATA_ONTO_CB_B_PORT', + 2: 'CB_B_DATA_ONTO_CB_B_PORT', + 3: 'CR_R_DATA_ONTO_CB_B_PORT', +} +ALPHA_DATA_ONTO_CB_B_PORT = 0 +Y_G_DATA_ONTO_CB_B_PORT = 1 +CB_B_DATA_ONTO_CB_B_PORT = 2 +CR_R_DATA_ONTO_CB_B_PORT = 3 +CROSSBAR_FOR_CB_B = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_CR_R' +CROSSBAR_FOR_CR_R__enumvalues = { + 0: 'ALPHA_DATA_ONTO_CR_R_PORT', + 1: 'Y_G_DATA_ONTO_CR_R_PORT', + 2: 'CB_B_DATA_ONTO_CR_R_PORT', + 3: 'CR_R_DATA_ONTO_CR_R_PORT', +} +ALPHA_DATA_ONTO_CR_R_PORT = 0 +Y_G_DATA_ONTO_CR_R_PORT = 1 +CB_B_DATA_ONTO_CR_R_PORT = 2 +CR_R_DATA_ONTO_CR_R_PORT = 3 +CROSSBAR_FOR_CR_R = ctypes.c_uint32 # enum + +# values for enumeration 'CROSSBAR_FOR_Y_G' +CROSSBAR_FOR_Y_G__enumvalues = { + 0: 'ALPHA_DATA_ONTO_Y_G_PORT', + 1: 'Y_G_DATA_ONTO_Y_G_PORT', + 2: 'CB_B_DATA_ONTO_Y_G_PORT', + 3: 'CR_R_DATA_ONTO_Y_G_PORT', +} +ALPHA_DATA_ONTO_Y_G_PORT = 0 +Y_G_DATA_ONTO_Y_G_PORT = 1 +CB_B_DATA_ONTO_Y_G_PORT = 2 +CR_R_DATA_ONTO_Y_G_PORT = 3 +CROSSBAR_FOR_Y_G = ctypes.c_uint32 # enum + +# values for enumeration 'DETILE_BUFFER_PACKER_ENABLE' +DETILE_BUFFER_PACKER_ENABLE__enumvalues = { + 0: 'DETILE_BUFFER_PACKER_IS_DISABLE', + 1: 'DETILE_BUFFER_PACKER_IS_ENABLE', +} +DETILE_BUFFER_PACKER_IS_DISABLE = 0 +DETILE_BUFFER_PACKER_IS_ENABLE = 1 +DETILE_BUFFER_PACKER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_DIS_MODE' +MEM_PWR_DIS_MODE__enumvalues = { + 0: 'MEM_POWER_DIS_MODE_ENABLE', + 1: 'MEM_POWER_DIS_MODE_DISABLE', +} +MEM_POWER_DIS_MODE_ENABLE = 0 +MEM_POWER_DIS_MODE_DISABLE = 1 +MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_MODE' +MEM_PWR_FORCE_MODE__enumvalues = { + 0: 'MEM_POWER_FORCE_MODE_OFF', + 1: 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', + 2: 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', + 3: 'MEM_POWER_FORCE_MODE_SHUT_DOWN', +} +MEM_POWER_FORCE_MODE_OFF = 0 +MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 1 +MEM_POWER_FORCE_MODE_DEEP_SLEEP = 2 +MEM_POWER_FORCE_MODE_SHUT_DOWN = 3 +MEM_PWR_FORCE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_STATUS' +MEM_PWR_STATUS__enumvalues = { + 0: 'MEM_POWER_STATUS_ON', + 1: 'MEM_POWER_STATUS_LIGHT_SLEEP', + 2: 'MEM_POWER_STATUS_DEEP_SLEEP', + 3: 'MEM_POWER_STATUS_SHUT_DOWN', +} +MEM_POWER_STATUS_ON = 0 +MEM_POWER_STATUS_LIGHT_SLEEP = 1 +MEM_POWER_STATUS_DEEP_SLEEP = 2 +MEM_POWER_STATUS_SHUT_DOWN = 3 +MEM_PWR_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_INT_MASK_MODE' +PIPE_INT_MASK_MODE__enumvalues = { + 0: 'PIPE_INT_MASK_MODE_DISABLE', + 1: 'PIPE_INT_MASK_MODE_ENABLE', +} +PIPE_INT_MASK_MODE_DISABLE = 0 +PIPE_INT_MASK_MODE_ENABLE = 1 +PIPE_INT_MASK_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_INT_TYPE_MODE' +PIPE_INT_TYPE_MODE__enumvalues = { + 0: 'PIPE_INT_TYPE_MODE_DISABLE', + 1: 'PIPE_INT_TYPE_MODE_ENABLE', +} +PIPE_INT_TYPE_MODE_DISABLE = 0 +PIPE_INT_TYPE_MODE_ENABLE = 1 +PIPE_INT_TYPE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE' +PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', +} +PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CROB_MEM_PWR_LIGHT_SLEEP_MODE' +CROB_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', + 2: 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', +} +CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 +CROB_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_2X_MAGNIFY' +CURSOR_2X_MAGNIFY__enumvalues = { + 0: 'CURSOR_2X_MAGNIFY_IS_DISABLE', + 1: 'CURSOR_2X_MAGNIFY_IS_ENABLE', +} +CURSOR_2X_MAGNIFY_IS_DISABLE = 0 +CURSOR_2X_MAGNIFY_IS_ENABLE = 1 +CURSOR_2X_MAGNIFY = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_ENABLE' +CURSOR_ENABLE__enumvalues = { + 0: 'CURSOR_IS_DISABLE', + 1: 'CURSOR_IS_ENABLE', +} +CURSOR_IS_DISABLE = 0 +CURSOR_IS_ENABLE = 1 +CURSOR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_LINES_PER_CHUNK' +CURSOR_LINES_PER_CHUNK__enumvalues = { + 0: 'CURSOR_LINE_PER_CHUNK_1', + 1: 'CURSOR_LINE_PER_CHUNK_2', + 2: 'CURSOR_LINE_PER_CHUNK_4', + 3: 'CURSOR_LINE_PER_CHUNK_8', + 4: 'CURSOR_LINE_PER_CHUNK_16', +} +CURSOR_LINE_PER_CHUNK_1 = 0 +CURSOR_LINE_PER_CHUNK_2 = 1 +CURSOR_LINE_PER_CHUNK_4 = 2 +CURSOR_LINE_PER_CHUNK_8 = 3 +CURSOR_LINE_PER_CHUNK_16 = 4 +CURSOR_LINES_PER_CHUNK = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_MODE' +CURSOR_MODE__enumvalues = { + 0: 'CURSOR_MONO_2BIT', + 1: 'CURSOR_COLOR_24BIT_1BIT_AND', + 2: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', + 3: 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 4: 'CURSOR_COLOR_64BIT_FP_PREMULT', + 5: 'CURSOR_COLOR_64BIT_FP_UNPREMULT', +} +CURSOR_MONO_2BIT = 0 +CURSOR_COLOR_24BIT_1BIT_AND = 1 +CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 2 +CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 3 +CURSOR_COLOR_64BIT_FP_PREMULT = 4 +CURSOR_COLOR_64BIT_FP_UNPREMULT = 5 +CURSOR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_EN' +CURSOR_PERFMON_LATENCY_MEASURE_EN__enumvalues = { + 0: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', + 1: 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', +} +CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0 +CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 1 +CURSOR_PERFMON_LATENCY_MEASURE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PERFMON_LATENCY_MEASURE_SEL' +CURSOR_PERFMON_LATENCY_MEASURE_SEL__enumvalues = { + 0: 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', + 1: 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', +} +CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0 +CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 1 +CURSOR_PERFMON_LATENCY_MEASURE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_PITCH' +CURSOR_PITCH__enumvalues = { + 0: 'CURSOR_PITCH_64_PIXELS', + 1: 'CURSOR_PITCH_128_PIXELS', + 2: 'CURSOR_PITCH_256_PIXELS', +} +CURSOR_PITCH_64_PIXELS = 0 +CURSOR_PITCH_128_PIXELS = 1 +CURSOR_PITCH_256_PIXELS = 2 +CURSOR_PITCH = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_REQ_MODE' +CURSOR_REQ_MODE__enumvalues = { + 0: 'CURSOR_REQUEST_NORMALLY', + 1: 'CURSOR_REQUEST_EARLY', +} +CURSOR_REQUEST_NORMALLY = 0 +CURSOR_REQUEST_EARLY = 1 +CURSOR_REQ_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SNOOP' +CURSOR_SNOOP__enumvalues = { + 0: 'CURSOR_IS_NOT_SNOOP', + 1: 'CURSOR_IS_SNOOP', +} +CURSOR_IS_NOT_SNOOP = 0 +CURSOR_IS_SNOOP = 1 +CURSOR_SNOOP = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_STEREO_EN' +CURSOR_STEREO_EN__enumvalues = { + 0: 'CURSOR_STEREO_IS_DISABLED', + 1: 'CURSOR_STEREO_IS_ENABLED', +} +CURSOR_STEREO_IS_DISABLED = 0 +CURSOR_STEREO_IS_ENABLED = 1 +CURSOR_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SURFACE_TMZ' +CURSOR_SURFACE_TMZ__enumvalues = { + 0: 'CURSOR_SURFACE_IS_NOT_TMZ', + 1: 'CURSOR_SURFACE_IS_TMZ', +} +CURSOR_SURFACE_IS_NOT_TMZ = 0 +CURSOR_SURFACE_IS_TMZ = 1 +CURSOR_SURFACE_TMZ = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_SYSTEM' +CURSOR_SYSTEM__enumvalues = { + 0: 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', + 1: 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', +} +CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0 +CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 1 +CURSOR_SYSTEM = ctypes.c_uint32 # enum + +# values for enumeration 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS' +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__enumvalues = { + 0: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', + 1: 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', +} +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0 +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 1 +CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_DONE' +DMDATA_DONE__enumvalues = { + 0: 'DMDATA_NOT_SENT_TO_DIG', + 1: 'DMDATA_SENT_TO_DIG', +} +DMDATA_NOT_SENT_TO_DIG = 0 +DMDATA_SENT_TO_DIG = 1 +DMDATA_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_MODE' +DMDATA_MODE__enumvalues = { + 0: 'DMDATA_SOFTWARE_UPDATE_MODE', + 1: 'DMDATA_HARDWARE_UPDATE_MODE', +} +DMDATA_SOFTWARE_UPDATE_MODE = 0 +DMDATA_HARDWARE_UPDATE_MODE = 1 +DMDATA_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_QOS_MODE' +DMDATA_QOS_MODE__enumvalues = { + 0: 'DMDATA_QOS_LEVEL_FROM_TTU', + 1: 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', +} +DMDATA_QOS_LEVEL_FROM_TTU = 0 +DMDATA_QOS_LEVEL_FROM_SOFTWARE = 1 +DMDATA_QOS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_REPEAT' +DMDATA_REPEAT__enumvalues = { + 0: 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', + 1: 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', +} +DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0 +DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 1 +DMDATA_REPEAT = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UNDERFLOW' +DMDATA_UNDERFLOW__enumvalues = { + 0: 'DMDATA_NOT_UNDERFLOW', + 1: 'DMDATA_UNDERFLOWED', +} +DMDATA_NOT_UNDERFLOW = 0 +DMDATA_UNDERFLOWED = 1 +DMDATA_UNDERFLOW = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UNDERFLOW_CLEAR' +DMDATA_UNDERFLOW_CLEAR__enumvalues = { + 0: 'DMDATA_DONT_CLEAR', + 1: 'DMDATA_CLEAR_UNDERFLOW_STATUS', +} +DMDATA_DONT_CLEAR = 0 +DMDATA_CLEAR_UNDERFLOW_STATUS = 1 +DMDATA_UNDERFLOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'DMDATA_UPDATED' +DMDATA_UPDATED__enumvalues = { + 0: 'DMDATA_NOT_UPDATED', + 1: 'DMDATA_WAS_UPDATED', +} +DMDATA_NOT_UPDATED = 0 +DMDATA_WAS_UPDATED = 1 +DMDATA_UPDATED = ctypes.c_uint32 # enum + +# values for enumeration 'RESPONSE_STATUS' +RESPONSE_STATUS__enumvalues = { + 0: 'OKAY', + 1: 'EXOKAY', + 2: 'SLVERR', + 3: 'DECERR', + 4: 'EARLY', + 5: 'OKAY_NODATA', + 6: 'PROTVIOL', + 7: 'TRANSERR', + 8: 'CMPTO', + 12: 'CRS', +} +OKAY = 0 +EXOKAY = 1 +SLVERR = 2 +DECERR = 3 +EARLY = 4 +OKAY_NODATA = 5 +PROTVIOL = 6 +TRANSERR = 7 +CMPTO = 8 +CRS = 12 +RESPONSE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE' +DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE__enumvalues = { + 0: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 1: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', + 2: 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', +} +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0 +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 1 +DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 2 +DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCHUBBUB_MEM_PWR_DIS_MODE' +DCHUBBUB_MEM_PWR_DIS_MODE__enumvalues = { + 0: 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', + 1: 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', +} +DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0 +DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 1 +DCHUBBUB_MEM_PWR_DIS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCHUBBUB_MEM_PWR_MODE' +DCHUBBUB_MEM_PWR_MODE__enumvalues = { + 0: 'DCHUBBUB_MEM_POWER_MODE_OFF', + 1: 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', + 2: 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', + 3: 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', +} +DCHUBBUB_MEM_POWER_MODE_OFF = 0 +DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 1 +DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 2 +DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 3 +DCHUBBUB_MEM_PWR_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET' +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET' +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_ADR_VUPDATE_LOCK_SET' +MPC_CFG_ADR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_ADR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_CFG_VUPDATE_LOCK_SET' +MPC_CFG_CFG_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_CFG_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_CUR_VUPDATE_LOCK_SET' +MPC_CFG_CUR_VUPDATE_LOCK_SET__enumvalues = { + 0: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 1: 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', +} +MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0 +MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 1 +MPC_CFG_CUR_VUPDATE_LOCK_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_MPC_TEST_CLK_SEL' +MPC_CFG_MPC_TEST_CLK_SEL__enumvalues = { + 0: 'MPC_CFG_MPC_TEST_CLK_SEL_0', + 1: 'MPC_CFG_MPC_TEST_CLK_SEL_1', + 2: 'MPC_CFG_MPC_TEST_CLK_SEL_2', + 3: 'MPC_CFG_MPC_TEST_CLK_SEL_3', +} +MPC_CFG_MPC_TEST_CLK_SEL_0 = 0 +MPC_CFG_MPC_TEST_CLK_SEL_1 = 1 +MPC_CFG_MPC_TEST_CLK_SEL_2 = 2 +MPC_CFG_MPC_TEST_CLK_SEL_3 = 3 +MPC_CFG_MPC_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN' +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', +} +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_INTERLACE_MODE' +MPC_CRC_CALC_INTERLACE_MODE__enumvalues = { + 0: 'MPC_CRC_INTERLACE_MODE_TOP', + 1: 'MPC_CRC_INTERLACE_MODE_BOTTOM', + 2: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', + 3: 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', +} +MPC_CRC_INTERLACE_MODE_TOP = 0 +MPC_CRC_INTERLACE_MODE_BOTTOM = 1 +MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 2 +MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 3 +MPC_CRC_CALC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_MODE' +MPC_CRC_CALC_MODE__enumvalues = { + 0: 'MPC_CRC_ONE_SHOT_MODE', + 1: 'MPC_CRC_CONTINUOUS_MODE', +} +MPC_CRC_ONE_SHOT_MODE = 0 +MPC_CRC_CONTINUOUS_MODE = 1 +MPC_CRC_CALC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_CALC_STEREO_MODE' +MPC_CRC_CALC_STEREO_MODE__enumvalues = { + 0: 'MPC_CRC_STEREO_MODE_LEFT', + 1: 'MPC_CRC_STEREO_MODE_RIGHT', + 2: 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', + 3: 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', +} +MPC_CRC_STEREO_MODE_LEFT = 0 +MPC_CRC_STEREO_MODE_RIGHT = 1 +MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 2 +MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 3 +MPC_CRC_CALC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_CRC_SOURCE_SELECT' +MPC_CRC_SOURCE_SELECT__enumvalues = { + 0: 'MPC_CRC_SOURCE_SEL_DPP', + 1: 'MPC_CRC_SOURCE_SEL_OPP', + 2: 'MPC_CRC_SOURCE_SEL_DWB', + 3: 'MPC_CRC_SOURCE_SEL_OTHER', +} +MPC_CRC_SOURCE_SEL_DPP = 0 +MPC_CRC_SOURCE_SEL_OPP = 1 +MPC_CRC_SOURCE_SEL_DWB = 2 +MPC_CRC_SOURCE_SEL_OTHER = 3 +MPC_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_DEBUG_BUS1_DATA_SELECT' +MPC_DEBUG_BUS1_DATA_SELECT__enumvalues = { + 0: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG', + 1: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT', + 2: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1', + 3: 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV', +} +MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG = 0 +MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT = 1 +MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1 = 2 +MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV = 3 +MPC_DEBUG_BUS1_DATA_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_DEBUG_BUS2_DATA_SELECT' +MPC_DEBUG_BUS2_DATA_SELECT__enumvalues = { + 0: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC', + 1: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT', + 2: 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM', + 3: 'MPC_DEBUG_BUS2_DATA_SELECT_RES', +} +MPC_DEBUG_BUS2_DATA_SELECT_MPCC = 0 +MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT = 1 +MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM = 2 +MPC_DEBUG_BUS2_DATA_SELECT_RES = 3 +MPC_DEBUG_BUS2_DATA_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT' +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT__enumvalues = { + 0: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID', + 1: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID', + 2: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID', + 3: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID', + 4: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA', + 5: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA', + 6: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1', + 7: 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID', +} +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID = 0 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID = 1 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID = 2 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID = 3 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA = 4 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA = 5 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1 = 6 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID = 7 +MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_DEBUG_BUS_MPCC_BYTE_SELECT' +MPC_DEBUG_BUS_MPCC_BYTE_SELECT__enumvalues = { + 0: 'MPC_DEBUG_BUS_MPCC_BYTE0', + 1: 'MPC_DEBUG_BUS_MPCC_BYTE1', + 2: 'MPC_DEBUG_BUS_MPCC_BYTE2', + 3: 'MPC_DEBUG_BUS_MPCC_BYTE3', +} +MPC_DEBUG_BUS_MPCC_BYTE0 = 0 +MPC_DEBUG_BUS_MPCC_BYTE1 = 1 +MPC_DEBUG_BUS_MPCC_BYTE2 = 2 +MPC_DEBUG_BUS_MPCC_BYTE3 = 3 +MPC_DEBUG_BUS_MPCC_BYTE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OCSC_COEF_FORMAT' +MPC_OCSC_COEF_FORMAT__enumvalues = { + 0: 'MPC_OCSC_COEF_FORMAT_S2_13', + 1: 'MPC_OCSC_COEF_FORMAT_S3_12', +} +MPC_OCSC_COEF_FORMAT_S2_13 = 0 +MPC_OCSC_COEF_FORMAT_S3_12 = 1 +MPC_OCSC_COEF_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN' +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', +} +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_CSC_MODE' +MPC_OUT_CSC_MODE__enumvalues = { + 0: 'MPC_OUT_CSC_MODE_0', + 1: 'MPC_OUT_CSC_MODE_1', + 2: 'MPC_OUT_CSC_MODE_2', + 3: 'MPC_OUT_CSC_MODE_RSV', +} +MPC_OUT_CSC_MODE_0 = 0 +MPC_OUT_CSC_MODE_1 = 1 +MPC_OUT_CSC_MODE_2 = 2 +MPC_OUT_CSC_MODE_RSV = 3 +MPC_OUT_CSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE' +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE__enumvalues = { + 0: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', + 1: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', + 2: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', + 3: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', + 4: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', + 5: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', + 6: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', + 7: 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', +} +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 1 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 2 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 3 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 4 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 5 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 6 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 7 +MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPC_OUT_RATE_CONTROL_DISABLE_SET' +MPC_OUT_RATE_CONTROL_DISABLE_SET__enumvalues = { + 0: 'MPC_OUT_RATE_CONTROL_SET_ENABLE', + 1: 'MPC_OUT_RATE_CONTROL_SET_DISABLE', +} +MPC_OUT_RATE_CONTROL_SET_ENABLE = 0 +MPC_OUT_RATE_CONTROL_SET_DISABLE = 1 +MPC_OUT_RATE_CONTROL_DISABLE_SET = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_BG_COLOR_BPC' +MPCC_BG_COLOR_BPC__enumvalues = { + 0: 'MPCC_BG_COLOR_BPC_8bit', + 1: 'MPCC_BG_COLOR_BPC_9bit', + 2: 'MPCC_BG_COLOR_BPC_10bit', + 3: 'MPCC_BG_COLOR_BPC_11bit', + 4: 'MPCC_BG_COLOR_BPC_12bit', +} +MPCC_BG_COLOR_BPC_8bit = 0 +MPCC_BG_COLOR_BPC_9bit = 1 +MPCC_BG_COLOR_BPC_10bit = 2 +MPCC_BG_COLOR_BPC_11bit = 3 +MPCC_BG_COLOR_BPC_12bit = 4 +MPCC_BG_COLOR_BPC = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY' +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', + 1: 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', +} +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0 +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 1 +MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE' +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', + 1: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 2: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', + 3: 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', +} +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 1 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 2 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 3 +MPCC_CONTROL_MPCC_ALPHA_BLND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE' +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', + 1: 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', +} +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0 +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 1 +MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE' +MPCC_CONTROL_MPCC_BOT_GAIN_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', + 1: 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', +} +MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0 +MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 1 +MPCC_CONTROL_MPCC_BOT_GAIN_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_CONTROL_MPCC_MODE' +MPCC_CONTROL_MPCC_MODE__enumvalues = { + 0: 'MPCC_CONTROL_MPCC_MODE_BYPASS', + 1: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', + 2: 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', + 3: 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', +} +MPCC_CONTROL_MPCC_MODE_BYPASS = 0 +MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 1 +MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 2 +MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 3 +MPCC_CONTROL_MPCC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_EN' +MPCC_SM_CONTROL_MPCC_SM_EN__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT' +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL' +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', +} +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 1 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 2 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 3 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL' +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', + 2: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 3: 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', +} +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 1 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 2 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 3 +MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT' +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', + 1: 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', +} +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0 +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 1 +MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_SM_CONTROL_MPCC_SM_MODE' +MPCC_SM_CONTROL_MPCC_SM_MODE__enumvalues = { + 0: 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', + 2: 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', + 4: 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', + 6: 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', +} +MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0 +MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 2 +MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 4 +MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 6 +MPCC_SM_CONTROL_MPCC_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN' +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE', +} +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM' +MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { + 0: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', + 1: 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', +} +MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 +MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 +MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_GAMUT_REMAP_MODE_ENUM' +MPCC_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'MPCC_GAMUT_REMAP_MODE_0', + 1: 'MPCC_GAMUT_REMAP_MODE_1', + 2: 'MPCC_GAMUT_REMAP_MODE_2', + 3: 'MPCC_GAMUT_REMAP_MODE_RSV', +} +MPCC_GAMUT_REMAP_MODE_0 = 0 +MPCC_GAMUT_REMAP_MODE_1 = 1 +MPCC_GAMUT_REMAP_MODE_2 = 2 +MPCC_GAMUT_REMAP_MODE_RSV = 3 +MPCC_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_2_CONFIG_ENUM' +MPCC_OGAM_LUT_2_CONFIG_ENUM__enumvalues = { + 0: 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', + 1: 'MPCC_OGAM_LUT_2CFG_MEMORY_A', + 2: 'MPCC_OGAM_LUT_2CFG_MEMORY_B', +} +MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0 +MPCC_OGAM_LUT_2CFG_MEMORY_A = 1 +MPCC_OGAM_LUT_2CFG_MEMORY_B = 2 +MPCC_OGAM_LUT_2_CONFIG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_CONFIG_MODE' +MPCC_OGAM_LUT_CONFIG_MODE__enumvalues = { + 0: 'MPCC_OGAM_DIFFERENT_RGB', + 1: 'MPCC_OGAM_ALL_USE_R', +} +MPCC_OGAM_DIFFERENT_RGB = 0 +MPCC_OGAM_ALL_USE_R = 1 +MPCC_OGAM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM' +MPCC_OGAM_LUT_PWL_DISABLE_ENUM__enumvalues = { + 0: 'MPCC_OGAM_ENABLE_PWL', + 1: 'MPCC_OGAM_DISABLE_PWL', +} +MPCC_OGAM_ENABLE_PWL = 0 +MPCC_OGAM_DISABLE_PWL = 1 +MPCC_OGAM_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL' +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', + 1: 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', +} +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0 +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 1 +MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_RAM_SEL' +MPCC_OGAM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_OGAM_RAMA_ACCESS', + 1: 'MPCC_OGAM_RAMB_ACCESS', +} +MPCC_OGAM_RAMA_ACCESS = 0 +MPCC_OGAM_RAMB_ACCESS = 1 +MPCC_OGAM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_READ_COLOR_SEL' +MPCC_OGAM_LUT_READ_COLOR_SEL__enumvalues = { + 0: 'MPCC_OGAM_BLUE_LUT', + 1: 'MPCC_OGAM_GREEN_LUT', + 2: 'MPCC_OGAM_RED_LUT', +} +MPCC_OGAM_BLUE_LUT = 0 +MPCC_OGAM_GREEN_LUT = 1 +MPCC_OGAM_RED_LUT = 2 +MPCC_OGAM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_READ_DBG' +MPCC_OGAM_LUT_READ_DBG__enumvalues = { + 0: 'MPCC_OGAM_DISABLE_DEBUG', + 1: 'MPCC_OGAM_ENABLE_DEBUG', +} +MPCC_OGAM_DISABLE_DEBUG = 0 +MPCC_OGAM_ENABLE_DEBUG = 1 +MPCC_OGAM_LUT_READ_DBG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_LUT_SEL_ENUM' +MPCC_OGAM_LUT_SEL_ENUM__enumvalues = { + 0: 'MPCC_OGAM_RAMA', + 1: 'MPCC_OGAM_RAMB', +} +MPCC_OGAM_RAMA = 0 +MPCC_OGAM_RAMB = 1 +MPCC_OGAM_LUT_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM' +MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM__enumvalues = { + 0: 'MPCC_OGAM_MODE_0', + 1: 'MPCC_OGAM_MODE_RSV1', + 2: 'MPCC_OGAM_MODE_2', + 3: 'MPCC_OGAM_MODE_RSV', +} +MPCC_OGAM_MODE_0 = 0 +MPCC_OGAM_MODE_RSV1 = 1 +MPCC_OGAM_MODE_2 = 2 +MPCC_OGAM_MODE_RSV = 3 +MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_NUM_SEG' +MPCC_OGAM_NUM_SEG__enumvalues = { + 0: 'MPCC_OGAM_SEGMENTS_1', + 1: 'MPCC_OGAM_SEGMENTS_2', + 2: 'MPCC_OGAM_SEGMENTS_4', + 3: 'MPCC_OGAM_SEGMENTS_8', + 4: 'MPCC_OGAM_SEGMENTS_16', + 5: 'MPCC_OGAM_SEGMENTS_32', + 6: 'MPCC_OGAM_SEGMENTS_64', + 7: 'MPCC_OGAM_SEGMENTS_128', +} +MPCC_OGAM_SEGMENTS_1 = 0 +MPCC_OGAM_SEGMENTS_2 = 1 +MPCC_OGAM_SEGMENTS_4 = 2 +MPCC_OGAM_SEGMENTS_8 = 3 +MPCC_OGAM_SEGMENTS_16 = 4 +MPCC_OGAM_SEGMENTS_32 = 5 +MPCC_OGAM_SEGMENTS_64 = 6 +MPCC_OGAM_SEGMENTS_128 = 7 +MPCC_OGAM_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN' +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN__enumvalues = { + 0: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', + 1: 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', +} +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0 +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 1 +MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_3DLUT_30BIT_ENUM' +MPCC_MCM_3DLUT_30BIT_ENUM__enumvalues = { + 0: 'MPCC_MCM_3DLUT_36BIT', + 1: 'MPCC_MCM_3DLUT_30BIT', +} +MPCC_MCM_3DLUT_36BIT = 0 +MPCC_MCM_3DLUT_30BIT = 1 +MPCC_MCM_3DLUT_30BIT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_3DLUT_RAM_SEL' +MPCC_MCM_3DLUT_RAM_SEL__enumvalues = { + 0: 'MPCC_MCM_RAM0_ACCESS', + 1: 'MPCC_MCM_RAM1_ACCESS', + 2: 'MPCC_MCM_RAM2_ACCESS', + 3: 'MPCC_MCM_RAM3_ACCESS', +} +MPCC_MCM_RAM0_ACCESS = 0 +MPCC_MCM_RAM1_ACCESS = 1 +MPCC_MCM_RAM2_ACCESS = 2 +MPCC_MCM_RAM3_ACCESS = 3 +MPCC_MCM_3DLUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_3DLUT_SIZE_ENUM' +MPCC_MCM_3DLUT_SIZE_ENUM__enumvalues = { + 0: 'MPCC_MCM_3DLUT_17CUBE', + 1: 'MPCC_MCM_3DLUT_9CUBE', +} +MPCC_MCM_3DLUT_17CUBE = 0 +MPCC_MCM_3DLUT_9CUBE = 1 +MPCC_MCM_3DLUT_SIZE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMMA_LUT_MODE_ENUM' +MPCC_MCM_GAMMA_LUT_MODE_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMMA_LUT_BYPASS', + 1: 'MPCC_MCM_GAMMA_LUT_RESERVED_1', + 2: 'MPCC_MCM_GAMMA_LUT_RAM_LUT', + 3: 'MPCC_MCM_GAMMA_LUT_RESERVED_3', +} +MPCC_MCM_GAMMA_LUT_BYPASS = 0 +MPCC_MCM_GAMMA_LUT_RESERVED_1 = 1 +MPCC_MCM_GAMMA_LUT_RAM_LUT = 2 +MPCC_MCM_GAMMA_LUT_RESERVED_3 = 3 +MPCC_MCM_GAMMA_LUT_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM' +MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', + 1: 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', +} +MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0 +MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 1 +MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_GAMMA_LUT_SEL_ENUM' +MPCC_MCM_GAMMA_LUT_SEL_ENUM__enumvalues = { + 0: 'MPCC_MCM_GAMMA_LUT_RAMA', + 1: 'MPCC_MCM_GAMMA_LUT_RAMB', +} +MPCC_MCM_GAMMA_LUT_RAMA = 0 +MPCC_MCM_GAMMA_LUT_RAMB = 1 +MPCC_MCM_GAMMA_LUT_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_2_MODE_ENUM' +MPCC_MCM_LUT_2_MODE_ENUM__enumvalues = { + 0: 'MPCC_MCM_LUT_2_MODE_BYPASS', + 1: 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', + 2: 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', +} +MPCC_MCM_LUT_2_MODE_BYPASS = 0 +MPCC_MCM_LUT_2_MODE_RAMA_LUT = 1 +MPCC_MCM_LUT_2_MODE_RAMB_LUT = 2 +MPCC_MCM_LUT_2_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_CONFIG_MODE' +MPCC_MCM_LUT_CONFIG_MODE__enumvalues = { + 0: 'MPCC_MCM_LUT_DIFFERENT_RGB', + 1: 'MPCC_MCM_LUT_ALL_USE_R', +} +MPCC_MCM_LUT_DIFFERENT_RGB = 0 +MPCC_MCM_LUT_ALL_USE_R = 1 +MPCC_MCM_LUT_CONFIG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_NUM_SEG' +MPCC_MCM_LUT_NUM_SEG__enumvalues = { + 0: 'MPCC_MCM_LUT_SEGMENTS_1', + 1: 'MPCC_MCM_LUT_SEGMENTS_2', + 2: 'MPCC_MCM_LUT_SEGMENTS_4', + 3: 'MPCC_MCM_LUT_SEGMENTS_8', + 4: 'MPCC_MCM_LUT_SEGMENTS_16', + 5: 'MPCC_MCM_LUT_SEGMENTS_32', + 6: 'MPCC_MCM_LUT_SEGMENTS_64', + 7: 'MPCC_MCM_LUT_SEGMENTS_128', +} +MPCC_MCM_LUT_SEGMENTS_1 = 0 +MPCC_MCM_LUT_SEGMENTS_2 = 1 +MPCC_MCM_LUT_SEGMENTS_4 = 2 +MPCC_MCM_LUT_SEGMENTS_8 = 3 +MPCC_MCM_LUT_SEGMENTS_16 = 4 +MPCC_MCM_LUT_SEGMENTS_32 = 5 +MPCC_MCM_LUT_SEGMENTS_64 = 6 +MPCC_MCM_LUT_SEGMENTS_128 = 7 +MPCC_MCM_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_RAM_SEL' +MPCC_MCM_LUT_RAM_SEL__enumvalues = { + 0: 'MPCC_MCM_LUT_RAMA_ACCESS', + 1: 'MPCC_MCM_LUT_RAMB_ACCESS', +} +MPCC_MCM_LUT_RAMA_ACCESS = 0 +MPCC_MCM_LUT_RAMB_ACCESS = 1 +MPCC_MCM_LUT_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_READ_COLOR_SEL' +MPCC_MCM_LUT_READ_COLOR_SEL__enumvalues = { + 0: 'MPCC_MCM_LUT_BLUE_LUT', + 1: 'MPCC_MCM_LUT_GREEN_LUT', + 2: 'MPCC_MCM_LUT_RED_LUT', +} +MPCC_MCM_LUT_BLUE_LUT = 0 +MPCC_MCM_LUT_GREEN_LUT = 1 +MPCC_MCM_LUT_RED_LUT = 2 +MPCC_MCM_LUT_READ_COLOR_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_LUT_READ_DBG' +MPCC_MCM_LUT_READ_DBG__enumvalues = { + 0: 'MPCC_MCM_LUT_DISABLE_DEBUG', + 1: 'MPCC_MCM_LUT_ENABLE_DEBUG', +} +MPCC_MCM_LUT_DISABLE_DEBUG = 0 +MPCC_MCM_LUT_ENABLE_DEBUG = 1 +MPCC_MCM_LUT_READ_DBG = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_MEM_PWR_FORCE_ENUM' +MPCC_MCM_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'MPCC_MCM_MEM_PWR_FORCE_DIS', + 1: 'MPCC_MCM_MEM_PWR_FORCE_LS', + 2: 'MPCC_MCM_MEM_PWR_FORCE_DS', + 3: 'MPCC_MCM_MEM_PWR_FORCE_SD', +} +MPCC_MCM_MEM_PWR_FORCE_DIS = 0 +MPCC_MCM_MEM_PWR_FORCE_LS = 1 +MPCC_MCM_MEM_PWR_FORCE_DS = 2 +MPCC_MCM_MEM_PWR_FORCE_SD = 3 +MPCC_MCM_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'MPCC_MCM_MEM_PWR_STATE_ENUM' +MPCC_MCM_MEM_PWR_STATE_ENUM__enumvalues = { + 0: 'MPCC_MCM_MEM_PWR_STATE_ON', + 1: 'MPCC_MCM_MEM_PWR_STATE_LS', + 2: 'MPCC_MCM_MEM_PWR_STATE_DS', + 3: 'MPCC_MCM_MEM_PWR_STATE_SD', +} +MPCC_MCM_MEM_PWR_STATE_ON = 0 +MPCC_MCM_MEM_PWR_STATE_LS = 1 +MPCC_MCM_MEM_PWR_STATE_DS = 2 +MPCC_MCM_MEM_PWR_STATE_SD = 3 +MPCC_MCM_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_BIT_DEPTH' +ENUM_DPG_BIT_DEPTH__enumvalues = { + 0: 'ENUM_DPG_BIT_DEPTH_6BPC', + 1: 'ENUM_DPG_BIT_DEPTH_8BPC', + 2: 'ENUM_DPG_BIT_DEPTH_10BPC', + 3: 'ENUM_DPG_BIT_DEPTH_12BPC', +} +ENUM_DPG_BIT_DEPTH_6BPC = 0 +ENUM_DPG_BIT_DEPTH_8BPC = 1 +ENUM_DPG_BIT_DEPTH_10BPC = 2 +ENUM_DPG_BIT_DEPTH_12BPC = 3 +ENUM_DPG_BIT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_DYNAMIC_RANGE' +ENUM_DPG_DYNAMIC_RANGE__enumvalues = { + 0: 'ENUM_DPG_DYNAMIC_RANGE_VESA', + 1: 'ENUM_DPG_DYNAMIC_RANGE_CEA', +} +ENUM_DPG_DYNAMIC_RANGE_VESA = 0 +ENUM_DPG_DYNAMIC_RANGE_CEA = 1 +ENUM_DPG_DYNAMIC_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_EN' +ENUM_DPG_EN__enumvalues = { + 0: 'ENUM_DPG_DISABLE', + 1: 'ENUM_DPG_ENABLE', +} +ENUM_DPG_DISABLE = 0 +ENUM_DPG_ENABLE = 1 +ENUM_DPG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_FIELD_POLARITY' +ENUM_DPG_FIELD_POLARITY__enumvalues = { + 0: 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', + 1: 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', +} +ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0 +ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 1 +ENUM_DPG_FIELD_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DPG_MODE' +ENUM_DPG_MODE__enumvalues = { + 0: 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', + 1: 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', + 2: 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', + 3: 'ENUM_DPG_MODE_VERTICAL_BAR', + 4: 'ENUM_DPG_MODE_HORIZONTAL_BAR', + 5: 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', + 6: 'ENUM_DPG_MODE_RGB_DUAL_RAMP', + 7: 'ENUM_DPG_MODE_RGB_XR_BIAS', +} +ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0 +ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 1 +ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 2 +ENUM_DPG_MODE_VERTICAL_BAR = 3 +ENUM_DPG_MODE_HORIZONTAL_BAR = 4 +ENUM_DPG_MODE_RGB_SINGLE_RAMP = 5 +ENUM_DPG_MODE_RGB_DUAL_RAMP = 6 +ENUM_DPG_MODE_RGB_XR_BIAS = 7 +ENUM_DPG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMTMEM_PWR_DIS_CTRL' +FMTMEM_PWR_DIS_CTRL__enumvalues = { + 0: 'FMTMEM_ENABLE_MEM_PWR_CTRL', + 1: 'FMTMEM_DISABLE_MEM_PWR_CTRL', +} +FMTMEM_ENABLE_MEM_PWR_CTRL = 0 +FMTMEM_DISABLE_MEM_PWR_CTRL = 1 +FMTMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'FMTMEM_PWR_FORCE_CTRL' +FMTMEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'FMTMEM_NO_FORCE_REQUEST', + 1: 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', +} +FMTMEM_NO_FORCE_REQUEST = 0 +FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 2 +FMTMEM_FORCE_SHUT_DOWN_REQUEST = 3 +FMTMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL' +FMT_BIT_DEPTH_CONTROL_25FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 1: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 2: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 3: 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 1 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 2 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_25FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL' +FMT_BIT_DEPTH_CONTROL_50FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 1: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 2: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 3: 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', +} +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 1 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 2 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 3 +FMT_BIT_DEPTH_CONTROL_50FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL' +FMT_BIT_DEPTH_CONTROL_75FRC_SEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 1: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 2: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 3: 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', +} +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 1 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 2 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 3 +FMT_BIT_DEPTH_CONTROL_75FRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL' +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 1: 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', +} +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 1 +FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 2: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 2 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE' +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE__enumvalues = { + 0: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 1: 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', +} +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 1 +FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CLAMP_CNTL_COLOR_FORMAT' +FMT_CLAMP_CNTL_COLOR_FORMAT__enumvalues = { + 0: 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 1: 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 2: 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 3: 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 4: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 5: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 6: 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 7: 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', +} +FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0 +FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 1 +FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 2 +FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 3 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 4 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 5 +FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 6 +FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 7 +FMT_CLAMP_CNTL_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS' +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS__enumvalues = { + 0: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 1: 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', +} +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 1 +FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_PIXEL_ENCODING' +FMT_CONTROL_PIXEL_ENCODING__enumvalues = { + 0: 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 1: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 2: 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 3: 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', +} +FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0 +FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 1 +FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 2 +FMT_CONTROL_PIXEL_ENCODING_RESERVED = 3 +FMT_CONTROL_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_MODE' +FMT_CONTROL_SUBSAMPLING_MODE__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 1: 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 2: 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 3: 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', +} +FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0 +FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 1 +FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 2 +FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 3 +FMT_CONTROL_SUBSAMPLING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_CONTROL_SUBSAMPLING_ORDER' +FMT_CONTROL_SUBSAMPLING_ORDER__enumvalues = { + 0: 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 1: 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', +} +FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0 +FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 1 +FMT_CONTROL_SUBSAMPLING_ORDER = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DEBUG_CNTL_COLOR_SELECT' +FMT_DEBUG_CNTL_COLOR_SELECT__enumvalues = { + 0: 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', + 1: 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', + 2: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', + 3: 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', +} +FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0 +FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 1 +FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 2 +FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 3 +FMT_DEBUG_CNTL_COLOR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_DYNAMIC_EXP_MODE' +FMT_DYNAMIC_EXP_MODE__enumvalues = { + 0: 'FMT_DYNAMIC_EXP_MODE_10to12', + 1: 'FMT_DYNAMIC_EXP_MODE_8to12', +} +FMT_DYNAMIC_EXP_MODE_10to12 = 0 +FMT_DYNAMIC_EXP_MODE_8to12 = 1 +FMT_DYNAMIC_EXP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_FRAME_RANDOM_ENABLE_CONTROL' +FMT_FRAME_RANDOM_ENABLE_CONTROL__enumvalues = { + 0: 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', + 1: 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', +} +FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0 +FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 1 +FMT_FRAME_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_POWER_STATE_ENUM' +FMT_POWER_STATE_ENUM__enumvalues = { + 0: 'FMT_POWER_STATE_ENUM_ON', + 1: 'FMT_POWER_STATE_ENUM_LS', + 2: 'FMT_POWER_STATE_ENUM_DS', + 3: 'FMT_POWER_STATE_ENUM_SD', +} +FMT_POWER_STATE_ENUM_ON = 0 +FMT_POWER_STATE_ENUM_LS = 1 +FMT_POWER_STATE_ENUM_DS = 2 +FMT_POWER_STATE_ENUM_SD = 3 +FMT_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_RGB_RANDOM_ENABLE_CONTROL' +FMT_RGB_RANDOM_ENABLE_CONTROL__enumvalues = { + 0: 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', + 1: 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', +} +FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0 +FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 1 +FMT_RGB_RANDOM_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL' +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL__enumvalues = { + 0: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', + 1: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', + 2: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', + 3: 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', +} +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 1 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 2 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 3 +FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_SPATIAL_DITHER_MODE' +FMT_SPATIAL_DITHER_MODE__enumvalues = { + 0: 'FMT_SPATIAL_DITHER_MODE_0', + 1: 'FMT_SPATIAL_DITHER_MODE_1', + 2: 'FMT_SPATIAL_DITHER_MODE_2', + 3: 'FMT_SPATIAL_DITHER_MODE_3', +} +FMT_SPATIAL_DITHER_MODE_0 = 0 +FMT_SPATIAL_DITHER_MODE_1 = 1 +FMT_SPATIAL_DITHER_MODE_2 = 2 +FMT_SPATIAL_DITHER_MODE_3 = 3 +FMT_SPATIAL_DITHER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_STEREOSYNC_OVERRIDE_CONTROL' +FMT_STEREOSYNC_OVERRIDE_CONTROL__enumvalues = { + 0: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', + 1: 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', +} +FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0 +FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 1 +FMT_STEREOSYNC_OVERRIDE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0' +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0__enumvalues = { + 0: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 1: 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', +} +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 1 +FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 = ctypes.c_uint32 # enum + +# values for enumeration 'OPPBUF_DISPLAY_SEGMENTATION' +OPPBUF_DISPLAY_SEGMENTATION__enumvalues = { + 0: 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', + 1: 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', + 2: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', + 3: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', + 4: 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', +} +OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0 +OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1 +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2 +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3 +OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4 +OPPBUF_DISPLAY_SEGMENTATION = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CLOCK_ENABLE_CONTROL' +OPP_PIPE_CLOCK_ENABLE_CONTROL__enumvalues = { + 0: 'OPP_PIPE_CLOCK_DISABLE', + 1: 'OPP_PIPE_CLOCK_ENABLE', +} +OPP_PIPE_CLOCK_DISABLE = 0 +OPP_PIPE_CLOCK_ENABLE = 1 +OPP_PIPE_CLOCK_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL' +OPP_PIPE_DIGTIAL_BYPASS_CONTROL__enumvalues = { + 0: 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', + 1: 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', +} +OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0 +OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 1 +OPP_PIPE_DIGTIAL_BYPASS_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_CONT_EN' +OPP_PIPE_CRC_CONT_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_MODE_ONE_SHOT', + 1: 'OPP_PIPE_CRC_MODE_CONTINUOUS', +} +OPP_PIPE_CRC_MODE_ONE_SHOT = 0 +OPP_PIPE_CRC_MODE_CONTINUOUS = 1 +OPP_PIPE_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_EN' +OPP_PIPE_CRC_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_DISABLE', + 1: 'OPP_PIPE_CRC_ENABLE', +} +OPP_PIPE_CRC_DISABLE = 0 +OPP_PIPE_CRC_ENABLE = 1 +OPP_PIPE_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_INTERLACE_EN' +OPP_PIPE_CRC_INTERLACE_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', + 1: 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', +} +OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0 +OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 1 +OPP_PIPE_CRC_INTERLACE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_INTERLACE_MODE' +OPP_PIPE_CRC_INTERLACE_MODE__enumvalues = { + 0: 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', + 1: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', + 2: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', + 3: 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', +} +OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0 +OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 1 +OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 2 +OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 3 +OPP_PIPE_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_ONE_SHOT_PENDING' +OPP_PIPE_CRC_ONE_SHOT_PENDING__enumvalues = { + 0: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', + 1: 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', +} +OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0 +OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 1 +OPP_PIPE_CRC_ONE_SHOT_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_PIXEL_SELECT' +OPP_PIPE_CRC_PIXEL_SELECT__enumvalues = { + 0: 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', + 1: 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', + 2: 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', + 3: 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', +} +OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0 +OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 1 +OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 2 +OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 3 +OPP_PIPE_CRC_PIXEL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_SOURCE_SELECT' +OPP_PIPE_CRC_SOURCE_SELECT__enumvalues = { + 0: 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', + 1: 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', +} +OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0 +OPP_PIPE_CRC_SOURCE_SELECT_SFT = 1 +OPP_PIPE_CRC_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_STEREO_EN' +OPP_PIPE_CRC_STEREO_EN__enumvalues = { + 0: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', + 1: 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', +} +OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0 +OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 1 +OPP_PIPE_CRC_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_PIPE_CRC_STEREO_MODE' +OPP_PIPE_CRC_STEREO_MODE__enumvalues = { + 0: 'OPP_PIPE_CRC_STEREO_MODE_LEFT', + 1: 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', + 2: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', + 3: 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', +} +OPP_PIPE_CRC_STEREO_MODE_LEFT = 0 +OPP_PIPE_CRC_STEREO_MODE_RIGHT = 1 +OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 2 +OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 3 +OPP_PIPE_CRC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_ABM_DEBUG_BUS_SELECT_CONTROL' +OPP_ABM_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_ABM0', + 1: 'DEBUG_BUS_SELECT_ABM1', + 2: 'DEBUG_BUS_SELECT_ABM2', + 3: 'DEBUG_BUS_SELECT_ABM3', + 4: 'DEBUG_BUS_SELECT_ABM_RESERVED0', + 5: 'DEBUG_BUS_SELECT_ABM_RESERVED1', +} +DEBUG_BUS_SELECT_ABM0 = 0 +DEBUG_BUS_SELECT_ABM1 = 1 +DEBUG_BUS_SELECT_ABM2 = 2 +DEBUG_BUS_SELECT_ABM3 = 3 +DEBUG_BUS_SELECT_ABM_RESERVED0 = 4 +DEBUG_BUS_SELECT_ABM_RESERVED1 = 5 +OPP_ABM_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_DPG_DEBUG_BUS_SELECT_CONTROL' +OPP_DPG_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_DPG0', + 1: 'DEBUG_BUS_SELECT_DPG1', + 2: 'DEBUG_BUS_SELECT_DPG2', + 3: 'DEBUG_BUS_SELECT_DPG3', + 4: 'DEBUG_BUS_SELECT_DPG_RESERVED0', + 5: 'DEBUG_BUS_SELECT_DPG_RESERVED1', +} +DEBUG_BUS_SELECT_DPG0 = 0 +DEBUG_BUS_SELECT_DPG1 = 1 +DEBUG_BUS_SELECT_DPG2 = 2 +DEBUG_BUS_SELECT_DPG3 = 3 +DEBUG_BUS_SELECT_DPG_RESERVED0 = 4 +DEBUG_BUS_SELECT_DPG_RESERVED1 = 5 +OPP_DPG_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_FMT_DEBUG_BUS_SELECT_CONTROL' +OPP_FMT_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_FMT0', + 1: 'DEBUG_BUS_SELECT_FMT1', + 2: 'DEBUG_BUS_SELECT_FMT2', + 3: 'DEBUG_BUS_SELECT_FMT3', + 4: 'DEBUG_BUS_SELECT_FMT_RESERVED0', + 5: 'DEBUG_BUS_SELECT_FMT_RESERVED1', +} +DEBUG_BUS_SELECT_FMT0 = 0 +DEBUG_BUS_SELECT_FMT1 = 1 +DEBUG_BUS_SELECT_FMT2 = 2 +DEBUG_BUS_SELECT_FMT3 = 3 +DEBUG_BUS_SELECT_FMT_RESERVED0 = 4 +DEBUG_BUS_SELECT_FMT_RESERVED1 = 5 +OPP_FMT_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL' +OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_OPPBUF0', + 1: 'DEBUG_BUS_SELECT_OPPBUF1', + 2: 'DEBUG_BUS_SELECT_OPPBUF2', + 3: 'DEBUG_BUS_SELECT_OPPBUF3', + 4: 'DEBUG_BUS_SELECT_OPPBUF_RESERVED0', + 5: 'DEBUG_BUS_SELECT_OPPBUF_RESERVED1', +} +DEBUG_BUS_SELECT_OPPBUF0 = 0 +DEBUG_BUS_SELECT_OPPBUF1 = 1 +DEBUG_BUS_SELECT_OPPBUF2 = 2 +DEBUG_BUS_SELECT_OPPBUF3 = 3 +DEBUG_BUS_SELECT_OPPBUF_RESERVED0 = 4 +DEBUG_BUS_SELECT_OPPBUF_RESERVED1 = 5 +OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL' +OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL__enumvalues = { + 0: 'DEBUG_BUS_SELECT_OPP_PIPE0', + 1: 'DEBUG_BUS_SELECT_OPP_PIPE1', + 2: 'DEBUG_BUS_SELECT_OPP_PIPE2', + 3: 'DEBUG_BUS_SELECT_OPP_PIPE3', + 4: 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0', + 5: 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1', +} +DEBUG_BUS_SELECT_OPP_PIPE0 = 0 +DEBUG_BUS_SELECT_OPP_PIPE1 = 1 +DEBUG_BUS_SELECT_OPP_PIPE2 = 2 +DEBUG_BUS_SELECT_OPP_PIPE3 = 3 +DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0 = 4 +DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1 = 5 +OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TEST_CLK_SEL_CONTROL' +OPP_TEST_CLK_SEL_CONTROL__enumvalues = { + 0: 'OPP_TEST_CLK_SEL_DISPCLK_P', + 1: 'OPP_TEST_CLK_SEL_DISPCLK_R', + 2: 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', + 3: 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', + 4: 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', + 5: 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', + 6: 'OPP_TEST_CLK_SEL_RESERVED0', + 7: 'OPP_TEST_CLK_SEL_RESERVED1', + 8: 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', + 9: 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', + 10: 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', + 11: 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', + 12: 'OPP_TEST_CLK_SEL_RESERVED2', + 13: 'OPP_TEST_CLK_SEL_RESERVED3', +} +OPP_TEST_CLK_SEL_DISPCLK_P = 0 +OPP_TEST_CLK_SEL_DISPCLK_R = 1 +OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 2 +OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 3 +OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 4 +OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 5 +OPP_TEST_CLK_SEL_RESERVED0 = 6 +OPP_TEST_CLK_SEL_RESERVED1 = 7 +OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 8 +OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 9 +OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 10 +OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 11 +OPP_TEST_CLK_SEL_RESERVED2 = 12 +OPP_TEST_CLK_SEL_RESERVED3 = 13 +OPP_TEST_CLK_SEL_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TOP_CLOCK_ENABLE_STATUS' +OPP_TOP_CLOCK_ENABLE_STATUS__enumvalues = { + 0: 'OPP_TOP_CLOCK_DISABLED_STATUS', + 1: 'OPP_TOP_CLOCK_ENABLED_STATUS', +} +OPP_TOP_CLOCK_DISABLED_STATUS = 0 +OPP_TOP_CLOCK_ENABLED_STATUS = 1 +OPP_TOP_CLOCK_ENABLE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'OPP_TOP_CLOCK_GATING_CONTROL' +OPP_TOP_CLOCK_GATING_CONTROL__enumvalues = { + 0: 'OPP_TOP_CLOCK_GATING_ENABLED', + 1: 'OPP_TOP_CLOCK_GATING_DISABLED', +} +OPP_TOP_CLOCK_GATING_ENABLED = 0 +OPP_TOP_CLOCK_GATING_DISABLED = 1 +OPP_TOP_CLOCK_GATING_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DSCRM_EN' +ENUM_DSCRM_EN__enumvalues = { + 0: 'ENUM_DSCRM_DISABLE', + 1: 'ENUM_DSCRM_ENABLE', +} +ENUM_DSCRM_DISABLE = 0 +ENUM_DSCRM_ENABLE = 1 +ENUM_DSCRM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK' +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 1: 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', +} +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 1 +MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_LOCK_SEL' +MASTER_UPDATE_LOCK_SEL__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_SEL_0', + 1: 'MASTER_UPDATE_LOCK_SEL_1', + 2: 'MASTER_UPDATE_LOCK_SEL_2', + 3: 'MASTER_UPDATE_LOCK_SEL_3', + 4: 'MASTER_UPDATE_LOCK_SEL_RESERVED4', + 5: 'MASTER_UPDATE_LOCK_SEL_RESERVED5', +} +MASTER_UPDATE_LOCK_SEL_0 = 0 +MASTER_UPDATE_LOCK_SEL_1 = 1 +MASTER_UPDATE_LOCK_SEL_2 = 2 +MASTER_UPDATE_LOCK_SEL_3 = 3 +MASTER_UPDATE_LOCK_SEL_RESERVED4 = 4 +MASTER_UPDATE_LOCK_SEL_RESERVED5 = 5 +MASTER_UPDATE_LOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE' +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE__enumvalues = { + 0: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 1: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', + 2: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', + 3: 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', +} +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 1 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 2 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 3 +MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE' +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE__enumvalues = { + 0: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 1: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 2: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 3: 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', +} +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 1 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 2 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 3 +OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL' +OTG_CONTROL_OTG_DISABLE_POINT_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', + 1: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 2: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', + 3: 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', +} +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 1 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 2 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 3 +OTG_CONTROL_OTG_DISABLE_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL' +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', + 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', +} +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0 +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 1 +OTG_CONTROL_OTG_FIELD_NUMBER_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY' +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY__enumvalues = { + 0: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', + 1: 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', +} +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0 +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 1 +OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_MASTER_EN' +OTG_CONTROL_OTG_MASTER_EN__enumvalues = { + 0: 'OTG_CONTROL_OTG_MASTER_EN_FALSE', + 1: 'OTG_CONTROL_OTG_MASTER_EN_TRUE', +} +OTG_CONTROL_OTG_MASTER_EN_FALSE = 0 +OTG_CONTROL_OTG_MASTER_EN_TRUE = 1 +OTG_CONTROL_OTG_MASTER_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_OUT_MUX' +OTG_CONTROL_OTG_OUT_MUX__enumvalues = { + 0: 'OTG_CONTROL_OTG_OUT_MUX_0', + 1: 'OTG_CONTROL_OTG_OUT_MUX_1', + 2: 'OTG_CONTROL_OTG_OUT_MUX_2', +} +OTG_CONTROL_OTG_OUT_MUX_0 = 0 +OTG_CONTROL_OTG_OUT_MUX_1 = 1 +OTG_CONTROL_OTG_OUT_MUX_2 = 2 +OTG_CONTROL_OTG_OUT_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CONTROL_OTG_START_POINT_CNTL' +OTG_CONTROL_OTG_START_POINT_CNTL__enumvalues = { + 0: 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', + 1: 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', +} +OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0 +OTG_CONTROL_OTG_START_POINT_CNTL_DP = 1 +OTG_CONTROL_OTG_START_POINT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN' +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN__enumvalues = { + 0: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', + 1: 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', +} +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0 +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 1 +OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC1_EN' +OTG_CRC_CNTL_OTG_CRC1_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC1_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_EN' +OTG_CRC_CNTL_OTG_CRC_CONT_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE' +OTG_CRC_CNTL_OTG_CRC_CONT_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', + 1: 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', +} +OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0 +OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 1 +OTG_CRC_CNTL_OTG_CRC_CONT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_EN' +OTG_CRC_CNTL_OTG_CRC_EN__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE' +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', + 1: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', + 2: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 3: 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', +} +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 1 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 2 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 3 +OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE' +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', + 1: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', + 2: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', + 3: 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', +} +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 1 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 2 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 3 +OTG_CRC_CNTL_OTG_CRC_STEREO_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS' +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 1: 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', +} +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0 +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 1 +OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT' +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', + 1: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', + 2: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', + 3: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', + 4: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', + 5: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', + 6: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', + 7: 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', +} +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 1 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 2 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 3 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 4 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 5 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 6 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 7 +OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT' +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT__enumvalues = { + 0: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', + 1: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', + 2: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', + 3: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', + 4: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', + 5: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', + 6: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', + 7: 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', +} +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 1 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 2 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 3 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 4 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 5 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 6 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 7 +OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DIG_UPDATE_VCOUNT_MODE' +OTG_DIG_UPDATE_VCOUNT_MODE__enumvalues = { + 0: 'OTG_DIG_UPDATE_VCOUNT_0', + 1: 'OTG_DIG_UPDATE_VCOUNT_1', +} +OTG_DIG_UPDATE_VCOUNT_0 = 0 +OTG_DIG_UPDATE_VCOUNT_1 = 1 +OTG_DIG_UPDATE_VCOUNT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE' +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE__enumvalues = { + 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', + 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', + 2: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', + 3: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', +} +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 1 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 2 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 3 +OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY' +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY__enumvalues = { + 0: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', + 1: 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', +} +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0 +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 1 +OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME' +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME__enumvalues = { + 0: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', + 1: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', + 2: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', + 3: 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', +} +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 1 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 2 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 3 +OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN' +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN__enumvalues = { + 0: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', + 1: 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', +} +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0 +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 1 +OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT' +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT__enumvalues = { + 0: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 1: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 2: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 3: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 4: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', + 5: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 6: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 7: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 8: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 9: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 10: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 11: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 12: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 13: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 14: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 15: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', + 16: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', + 17: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', + 18: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', + 19: 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', +} +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 1 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 2 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 3 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 4 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 5 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 6 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 7 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 8 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 9 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 10 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 11 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 12 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 13 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 14 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 15 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 16 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 17 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 18 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 19 +OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', + 2: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 3: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 2 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 3 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL' +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL__enumvalues = { + 0: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 1: 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', +} +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 1 +OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL' +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL__enumvalues = { + 0: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', + 1: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', + 2: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', + 3: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', + 4: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', + 5: 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', +} +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 1 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 2 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 3 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 4 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 5 +OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL' +OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL__enumvalues = { + 0: 'DIG_UPDATE_EYE_SEL_BOTH', + 1: 'DIG_UPDATE_EYE_SEL_LEFT', + 2: 'DIG_UPDATE_EYE_SEL_RIGHT', +} +DIG_UPDATE_EYE_SEL_BOTH = 0 +DIG_UPDATE_EYE_SEL_LEFT = 1 +DIG_UPDATE_EYE_SEL_RIGHT = 2 +OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL' +OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL__enumvalues = { + 0: 'DIG_UPDATE_FIELD_SEL_BOTH', + 1: 'DIG_UPDATE_FIELD_SEL_TOP', + 2: 'DIG_UPDATE_FIELD_SEL_BOTTOM', + 3: 'DIG_UPDATE_FIELD_SEL_RESERVED', +} +DIG_UPDATE_FIELD_SEL_BOTH = 0 +DIG_UPDATE_FIELD_SEL_TOP = 1 +DIG_UPDATE_FIELD_SEL_BOTTOM = 2 +DIG_UPDATE_FIELD_SEL_RESERVED = 3 +OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD' +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', + 1: 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', + 2: 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', + 3: 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', +} +MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0 +MASTER_UPDATE_LOCK_DB_FIELD_TOP = 1 +MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 2 +MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 3 +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL' +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL__enumvalues = { + 0: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', + 1: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', + 2: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', + 3: 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', +} +MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 1 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 2 +MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 3 +OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GLOBAL_UPDATE_LOCK_EN' +OTG_GLOBAL_UPDATE_LOCK_EN__enumvalues = { + 0: 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', + 1: 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', +} +OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0 +OTG_GLOBAL_UPDATE_LOCK_ENABLE = 1 +OTG_GLOBAL_UPDATE_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_GSL_MASTER_MODE' +OTG_GSL_MASTER_MODE__enumvalues = { + 0: 'OTG_GSL_MASTER_MODE_0', + 1: 'OTG_GSL_MASTER_MODE_1', + 2: 'OTG_GSL_MASTER_MODE_2', + 3: 'OTG_GSL_MASTER_MODE_3', +} +OTG_GSL_MASTER_MODE_0 = 0 +OTG_GSL_MASTER_MODE_1 = 1 +OTG_GSL_MASTER_MODE_2 = 2 +OTG_GSL_MASTER_MODE_3 = 3 +OTG_GSL_MASTER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_HORZ_REPETITION_COUNT' +OTG_HORZ_REPETITION_COUNT__enumvalues = { + 0: 'OTG_HORZ_REPETITION_COUNT_0', + 1: 'OTG_HORZ_REPETITION_COUNT_1', + 2: 'OTG_HORZ_REPETITION_COUNT_2', + 3: 'OTG_HORZ_REPETITION_COUNT_3', + 4: 'OTG_HORZ_REPETITION_COUNT_4', + 5: 'OTG_HORZ_REPETITION_COUNT_5', + 6: 'OTG_HORZ_REPETITION_COUNT_6', + 7: 'OTG_HORZ_REPETITION_COUNT_7', + 8: 'OTG_HORZ_REPETITION_COUNT_8', + 9: 'OTG_HORZ_REPETITION_COUNT_9', + 10: 'OTG_HORZ_REPETITION_COUNT_10', + 11: 'OTG_HORZ_REPETITION_COUNT_11', + 12: 'OTG_HORZ_REPETITION_COUNT_12', + 13: 'OTG_HORZ_REPETITION_COUNT_13', + 14: 'OTG_HORZ_REPETITION_COUNT_14', + 15: 'OTG_HORZ_REPETITION_COUNT_15', +} +OTG_HORZ_REPETITION_COUNT_0 = 0 +OTG_HORZ_REPETITION_COUNT_1 = 1 +OTG_HORZ_REPETITION_COUNT_2 = 2 +OTG_HORZ_REPETITION_COUNT_3 = 3 +OTG_HORZ_REPETITION_COUNT_4 = 4 +OTG_HORZ_REPETITION_COUNT_5 = 5 +OTG_HORZ_REPETITION_COUNT_6 = 6 +OTG_HORZ_REPETITION_COUNT_7 = 7 +OTG_HORZ_REPETITION_COUNT_8 = 8 +OTG_HORZ_REPETITION_COUNT_9 = 9 +OTG_HORZ_REPETITION_COUNT_10 = 10 +OTG_HORZ_REPETITION_COUNT_11 = 11 +OTG_HORZ_REPETITION_COUNT_12 = 12 +OTG_HORZ_REPETITION_COUNT_13 = 13 +OTG_HORZ_REPETITION_COUNT_14 = 14 +OTG_HORZ_REPETITION_COUNT_15 = 15 +OTG_HORZ_REPETITION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_SYNC_A_POL' +OTG_H_SYNC_A_POL__enumvalues = { + 0: 'OTG_H_SYNC_A_POL_HIGH', + 1: 'OTG_H_SYNC_A_POL_LOW', +} +OTG_H_SYNC_A_POL_HIGH = 0 +OTG_H_SYNC_A_POL_LOW = 1 +OTG_H_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_TIMING_DIV_MODE' +OTG_H_TIMING_DIV_MODE__enumvalues = { + 0: 'OTG_H_TIMING_DIV_MODE_NO_DIV', + 1: 'OTG_H_TIMING_DIV_MODE_DIV_BY2', + 2: 'OTG_H_TIMING_DIV_MODE_RESERVED', + 3: 'OTG_H_TIMING_DIV_MODE_DIV_BY4', +} +OTG_H_TIMING_DIV_MODE_NO_DIV = 0 +OTG_H_TIMING_DIV_MODE_DIV_BY2 = 1 +OTG_H_TIMING_DIV_MODE_RESERVED = 2 +OTG_H_TIMING_DIV_MODE_DIV_BY4 = 3 +OTG_H_TIMING_DIV_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_H_TIMING_DIV_MODE_MANUAL' +OTG_H_TIMING_DIV_MODE_MANUAL__enumvalues = { + 0: 'OTG_H_TIMING_DIV_MODE_AUTO', + 1: 'OTG_H_TIMING_DIV_MODE_NOAUTO', +} +OTG_H_TIMING_DIV_MODE_AUTO = 0 +OTG_H_TIMING_DIV_MODE_NOAUTO = 1 +OTG_H_TIMING_DIV_MODE_MANUAL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE' +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE__enumvalues = { + 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', + 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', +} +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 1 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD' +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD__enumvalues = { + 0: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', + 1: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', + 2: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', + 3: 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', +} +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 1 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 2 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 3 +OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK' +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE' +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE__enumvalues = { + 0: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', + 1: 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', +} +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 1 +OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE' +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__enumvalues = { + 0: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 1: 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', +} +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0 +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 1 +OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_DB_EN' +OTG_MASTER_UPDATE_LOCK_DB_EN__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_DISABLE', + 1: 'OTG_MASTER_UPDATE_LOCK_ENABLE', +} +OTG_MASTER_UPDATE_LOCK_DISABLE = 0 +OTG_MASTER_UPDATE_LOCK_ENABLE = 1 +OTG_MASTER_UPDATE_LOCK_DB_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_GSL_EN' +OTG_MASTER_UPDATE_LOCK_GSL_EN__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', + 1: 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', +} +OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0 +OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 1 +OTG_MASTER_UPDATE_LOCK_GSL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE' +OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE__enumvalues = { + 0: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', + 1: 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', +} +OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0 +OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 1 +OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL' +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL__enumvalues = { + 0: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 1: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 2: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 3: 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', +} +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 1 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 2 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 3 +OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR' +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR__enumvalues = { + 0: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', + 1: 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', +} +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0 +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 1 +OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE' +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE' +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', +} +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE' +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE__enumvalues = { + 0: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 1: 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', +} +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 1 +OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL' +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', +} +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0 +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 1 +OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EN' +OTG_STEREO_CONTROL_OTG_STEREO_EN__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY' +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY' +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY__enumvalues = { + 0: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 1: 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', +} +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0 +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 1 +OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE' +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE__enumvalues = { + 0: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', + 1: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', + 2: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', + 3: 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', +} +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 1 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 2 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 3 +OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR' +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', +} +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', + 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', + 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', +} +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 6 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 7 +OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN' +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', +} +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', +} +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT' +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT__enumvalues = { + 0: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', + 1: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', + 2: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', + 3: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', + 4: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', + 5: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', + 6: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', + 7: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', + 8: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', + 9: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', + 10: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', + 11: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', + 12: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', + 13: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', + 14: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', + 15: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', + 16: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', + 17: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', + 18: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', + 19: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', + 20: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', + 21: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 22: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 23: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', + 24: 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', +} +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 1 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 2 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 3 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 4 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 5 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 6 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 7 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 8 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 9 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 11 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 12 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 13 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 14 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 15 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 17 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 18 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 19 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 20 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 23 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 24 +OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL' +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_FREQUENCY_SELECT' +OTG_TRIGA_FREQUENCY_SELECT__enumvalues = { + 0: 'OTG_TRIGA_FREQUENCY_SELECT_0', + 1: 'OTG_TRIGA_FREQUENCY_SELECT_1', + 2: 'OTG_TRIGA_FREQUENCY_SELECT_2', + 3: 'OTG_TRIGA_FREQUENCY_SELECT_3', +} +OTG_TRIGA_FREQUENCY_SELECT_0 = 0 +OTG_TRIGA_FREQUENCY_SELECT_1 = 1 +OTG_TRIGA_FREQUENCY_SELECT_2 = 2 +OTG_TRIGA_FREQUENCY_SELECT_3 = 3 +OTG_TRIGA_FREQUENCY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL' +OTG_TRIGA_RISING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGA_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR' +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', +} +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', + 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', + 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', +} +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 6 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 7 +OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN' +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', +} +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', +} +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT' +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT__enumvalues = { + 0: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', + 1: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', + 2: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', + 3: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', + 4: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', + 5: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', + 6: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', + 7: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', + 8: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', + 9: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', + 10: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', + 11: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', + 12: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', + 13: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', + 14: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', + 15: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', + 16: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', + 17: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', + 18: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', + 19: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', + 20: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', + 21: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 22: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 23: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', + 24: 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', +} +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 1 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 2 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 3 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 4 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 5 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 6 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 7 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 8 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 9 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 10 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 11 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 12 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 13 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 14 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 15 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 16 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 17 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 18 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 19 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 20 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 21 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 22 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 23 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 24 +OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL' +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGB_FALLING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_FREQUENCY_SELECT' +OTG_TRIGB_FREQUENCY_SELECT__enumvalues = { + 0: 'OTG_TRIGB_FREQUENCY_SELECT_0', + 1: 'OTG_TRIGB_FREQUENCY_SELECT_1', + 2: 'OTG_TRIGB_FREQUENCY_SELECT_2', + 3: 'OTG_TRIGB_FREQUENCY_SELECT_3', +} +OTG_TRIGB_FREQUENCY_SELECT_0 = 0 +OTG_TRIGB_FREQUENCY_SELECT_1 = 1 +OTG_TRIGB_FREQUENCY_SELECT_2 = 2 +OTG_TRIGB_FREQUENCY_SELECT_3 = 3 +OTG_TRIGB_FREQUENCY_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL' +OTG_TRIGB_RISING_EDGE_DETECT_CNTL__enumvalues = { + 0: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', + 1: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', + 2: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', + 3: 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', +} +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 1 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 2 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 3 +OTG_TRIGB_RISING_EDGE_DETECT_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK' +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK__enumvalues = { + 0: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', + 1: 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', +} +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0 +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 1 +OTG_UPDATE_LOCK_OTG_UPDATE_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY' +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', +} +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 1 +OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE' +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE' +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE__enumvalues = { + 0: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 1: 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', +} +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 1 +OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE' +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE__enumvalues = { + 0: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', + 1: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 2: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 3: 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', +} +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 1 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 2 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 3 +OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR' +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__enumvalues = { + 0: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 1: 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', +} +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0 +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 1 +OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR' +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR__enumvalues = { + 0: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', + 1: 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', +} +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0 +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 1 +OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_VUPDATE_BLOCK_DISABLE' +OTG_VUPDATE_BLOCK_DISABLE__enumvalues = { + 0: 'OTG_VUPDATE_BLOCK_DISABLE_OFF', + 1: 'OTG_VUPDATE_BLOCK_DISABLE_ON', +} +OTG_VUPDATE_BLOCK_DISABLE_OFF = 0 +OTG_VUPDATE_BLOCK_DISABLE_ON = 1 +OTG_VUPDATE_BLOCK_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_SYNC_A_POL' +OTG_V_SYNC_A_POL__enumvalues = { + 0: 'OTG_V_SYNC_A_POL_HIGH', + 1: 'OTG_V_SYNC_A_POL_LOW', +} +OTG_V_SYNC_A_POL_HIGH = 0 +OTG_V_SYNC_A_POL_LOW = 1 +OTG_V_SYNC_A_POL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_SYNC_MODE' +OTG_V_SYNC_MODE__enumvalues = { + 0: 'OTG_V_SYNC_MODE_HSYNC', + 1: 'OTG_V_SYNC_MODE_HBLANK', +} +OTG_V_SYNC_MODE_HSYNC = 0 +OTG_V_SYNC_MODE_HBLANK = 1 +OTG_V_SYNC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD' +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', + 1: 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', +} +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0 +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 1 +OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT' +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', +} +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 1 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC' +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', +} +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 1 +OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL' +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', +} +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 1 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL' +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL__enumvalues = { + 0: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', + 1: 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', +} +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 1 +OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK' +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__enumvalues = { + 0: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', + 1: 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', +} +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0 +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 1 +OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL' +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL__enumvalues = { + 0: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', + 1: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', + 2: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', + 3: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', + 4: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', + 5: 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', +} +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 1 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 2 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 3 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 4 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 5 +OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DC_DMCUB_INT_TYPE' +DC_DMCUB_INT_TYPE__enumvalues = { + 0: 'INT_LEVEL', + 1: 'INT_PULSE', +} +INT_LEVEL = 0 +INT_PULSE = 1 +DC_DMCUB_INT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DC_DMCUB_TIMER_WINDOW' +DC_DMCUB_TIMER_WINDOW__enumvalues = { + 0: 'BITS_31_0', + 1: 'BITS_32_1', + 2: 'BITS_33_2', + 3: 'BITS_34_3', + 4: 'BITS_35_4', + 5: 'BITS_36_5', + 6: 'BITS_37_6', + 7: 'BITS_38_7', +} +BITS_31_0 = 0 +BITS_32_1 = 1 +BITS_33_2 = 2 +BITS_34_3 = 3 +BITS_35_4 = 4 +BITS_36_5 = 5 +BITS_37_6 = 6 +BITS_38_7 = 7 +DC_DMCUB_TIMER_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'INVALID_REG_ACCESS_TYPE' +INVALID_REG_ACCESS_TYPE__enumvalues = { + 0: 'REG_UNALLOCATED_ADDR_WRITE', + 1: 'REG_UNALLOCATED_ADDR_READ', + 2: 'REG_VIRTUAL_WRITE', + 3: 'REG_VIRTUAL_READ', + 4: 'REG_SECURE_VIOLATE_WRITE', + 5: 'REG_SECURE_VIOLATE_READ', +} +REG_UNALLOCATED_ADDR_WRITE = 0 +REG_UNALLOCATED_ADDR_READ = 1 +REG_VIRTUAL_WRITE = 2 +REG_VIRTUAL_READ = 3 +REG_SECURE_VIOLATE_WRITE = 4 +REG_SECURE_VIOLATE_READ = 5 +INVALID_REG_ACCESS_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_DC_GPU_TIMER_READ_SELECT' +DMU_DC_GPU_TIMER_READ_SELECT__enumvalues = { + 0: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', + 1: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', + 2: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', + 3: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', + 4: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', + 5: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', + 6: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', + 7: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', + 8: 'RESERVED_8', + 9: 'RESERVED_9', + 10: 'RESERVED_10', + 11: 'RESERVED_11', + 12: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', + 13: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', + 14: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', + 15: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', + 16: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', + 17: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', + 18: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', + 19: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', + 20: 'RESERVED_20', + 21: 'RESERVED_21', + 22: 'RESERVED_22', + 23: 'RESERVED_23', + 24: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', + 25: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', + 26: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', + 27: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', + 28: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', + 29: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', + 30: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', + 31: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', + 32: 'RESERVED_32', + 33: 'RESERVED_33', + 34: 'RESERVED_34', + 35: 'RESERVED_35', + 36: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', + 37: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', + 38: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', + 39: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', + 40: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', + 41: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', + 42: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', + 43: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', + 44: 'RESERVED_44', + 45: 'RESERVED_45', + 46: 'RESERVED_46', + 47: 'RESERVED_47', + 48: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', + 49: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', + 50: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', + 51: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', + 52: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', + 53: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', + 54: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', + 55: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', + 56: 'RESERVED_56', + 57: 'RESERVED_57', + 58: 'RESERVED_58', + 59: 'RESERVED_59', + 60: 'RESERVED_60', + 61: 'RESERVED_61', + 62: 'RESERVED_62', + 63: 'RESERVED_63', + 64: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', + 65: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', + 66: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', + 67: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', + 68: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', + 69: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', + 70: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', + 71: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', + 72: 'RESERVED_72', + 73: 'RESERVED_73', + 74: 'RESERVED_74', + 75: 'RESERVED_75', + 76: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', + 77: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', + 78: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', + 79: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', + 80: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', + 81: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', + 82: 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', + 83: 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', + 84: 'RESERVED_84', + 85: 'RESERVED_85', + 86: 'RESERVED_86', + 87: 'RESERVED_87', + 88: 'RESERVED_88', + 89: 'RESERVED_89', + 90: 'RESERVED_90', + 91: 'RESERVED_91', +} +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 1 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 2 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 3 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 4 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 5 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 6 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 7 +RESERVED_8 = 8 +RESERVED_9 = 9 +RESERVED_10 = 10 +RESERVED_11 = 11 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 12 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 13 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 14 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 15 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 16 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 17 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 18 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 19 +RESERVED_20 = 20 +RESERVED_21 = 21 +RESERVED_22 = 22 +RESERVED_23 = 23 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 24 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 25 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 26 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 27 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 28 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 29 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 30 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 31 +RESERVED_32 = 32 +RESERVED_33 = 33 +RESERVED_34 = 34 +RESERVED_35 = 35 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 36 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 37 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 38 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 39 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 40 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 41 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 42 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 43 +RESERVED_44 = 44 +RESERVED_45 = 45 +RESERVED_46 = 46 +RESERVED_47 = 47 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 48 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 49 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 50 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 51 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 52 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 53 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 54 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 55 +RESERVED_56 = 56 +RESERVED_57 = 57 +RESERVED_58 = 58 +RESERVED_59 = 59 +RESERVED_60 = 60 +RESERVED_61 = 61 +RESERVED_62 = 62 +RESERVED_63 = 63 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 64 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 65 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 66 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 67 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 68 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 69 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 70 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 71 +RESERVED_72 = 72 +RESERVED_73 = 73 +RESERVED_74 = 74 +RESERVED_75 = 75 +DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 76 +DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 77 +DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 78 +DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 79 +DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 80 +DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 81 +DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 82 +DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 83 +RESERVED_84 = 84 +RESERVED_85 = 85 +RESERVED_86 = 86 +RESERVED_87 = 87 +RESERVED_88 = 88 +RESERVED_89 = 89 +RESERVED_90 = 90 +RESERVED_91 = 91 +DMU_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_DC_GPU_TIMER_START_POSITION' +DMU_DC_GPU_TIMER_START_POSITION__enumvalues = { + 0: 'DMU_GPU_TIMER_START_0_END_27', + 1: 'DMU_GPU_TIMER_START_1_END_28', + 2: 'DMU_GPU_TIMER_START_2_END_29', + 3: 'DMU_GPU_TIMER_START_3_END_30', + 4: 'DMU_GPU_TIMER_START_4_END_31', + 5: 'DMU_GPU_TIMER_START_6_END_33', + 6: 'DMU_GPU_TIMER_START_8_END_35', + 7: 'DMU_GPU_TIMER_START_10_END_37', +} +DMU_GPU_TIMER_START_0_END_27 = 0 +DMU_GPU_TIMER_START_1_END_28 = 1 +DMU_GPU_TIMER_START_2_END_29 = 2 +DMU_GPU_TIMER_START_3_END_30 = 3 +DMU_GPU_TIMER_START_4_END_31 = 4 +DMU_GPU_TIMER_START_6_END_33 = 5 +DMU_GPU_TIMER_START_8_END_35 = 6 +DMU_GPU_TIMER_START_10_END_37 = 7 +DMU_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'IHC_INTERRUPT_DEST' +IHC_INTERRUPT_DEST__enumvalues = { + 0: 'INTERRUPT_SENT_TO_IH', + 1: 'INTERRUPT_SENT_TO_DMCUB', +} +INTERRUPT_SENT_TO_IH = 0 +INTERRUPT_SENT_TO_DMCUB = 1 +IHC_INTERRUPT_DEST = ctypes.c_uint32 # enum + +# values for enumeration 'IHC_INTERRUPT_LINE_STATUS' +IHC_INTERRUPT_LINE_STATUS__enumvalues = { + 0: 'INTERRUPT_LINE_NOT_ASSERTED', + 1: 'INTERRUPT_LINE_ASSERTED', +} +INTERRUPT_LINE_NOT_ASSERTED = 0 +INTERRUPT_LINE_ASSERTED = 1 +IHC_INTERRUPT_LINE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DC_SMU_INTERRUPT_ENABLE' +DC_SMU_INTERRUPT_ENABLE__enumvalues = { + 0: 'DISABLE_THE_INTERRUPT', + 1: 'ENABLE_THE_INTERRUPT', +} +DISABLE_THE_INTERRUPT = 0 +ENABLE_THE_INTERRUPT = 1 +DC_SMU_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DMU_CLOCK_ON' +DMU_CLOCK_ON__enumvalues = { + 0: 'DMU_CLOCK_STATUS_ON', + 1: 'DMU_CLOCK_STATUS_OFF', +} +DMU_CLOCK_STATUS_ON = 0 +DMU_CLOCK_STATUS_OFF = 1 +DMU_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'SMU_INTR' +SMU_INTR__enumvalues = { + 0: 'SMU_MSG_INTR_NOOP', + 1: 'SET_SMU_MSG_INTR', +} +SMU_MSG_INTR_NOOP = 0 +SET_SMU_MSG_INTR = 1 +SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'ALLOW_SR_ON_TRANS_REQ' +ALLOW_SR_ON_TRANS_REQ__enumvalues = { + 0: 'ALLOW_SR_ON_TRANS_REQ_ENABLE', + 1: 'ALLOW_SR_ON_TRANS_REQ_DISABLE', +} +ALLOW_SR_ON_TRANS_REQ_ENABLE = 0 +ALLOW_SR_ON_TRANS_REQ_DISABLE = 1 +ALLOW_SR_ON_TRANS_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'AMCLOCK_ENABLE' +AMCLOCK_ENABLE__enumvalues = { + 0: 'ENABLE_AMCLK0', + 1: 'ENABLE_AMCLK1', +} +ENABLE_AMCLK0 = 0 +ENABLE_AMCLK1 = 1 +AMCLOCK_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'CLEAR_SMU_INTR' +CLEAR_SMU_INTR__enumvalues = { + 0: 'SMU_INTR_STATUS_NOOP', + 1: 'SMU_INTR_STATUS_CLEAR', +} +SMU_INTR_STATUS_NOOP = 0 +SMU_INTR_STATUS_CLEAR = 1 +CLEAR_SMU_INTR = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_BRANCH_SOFT_RESET' +CLOCK_BRANCH_SOFT_RESET__enumvalues = { + 0: 'CLOCK_BRANCH_SOFT_RESET_NOOP', + 1: 'CLOCK_BRANCH_SOFT_RESET_FORCE', +} +CLOCK_BRANCH_SOFT_RESET_NOOP = 0 +CLOCK_BRANCH_SOFT_RESET_FORCE = 1 +CLOCK_BRANCH_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO0_SOURCE_SEL' +DCCG_AUDIO_DTO0_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', + 1: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', + 2: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', + 3: 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', + 4: 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', +} +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 1 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 2 +DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 3 +DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 4 +DCCG_AUDIO_DTO0_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO2_SOURCE_SEL' +DCCG_AUDIO_DTO2_SOURCE_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 1: 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', +} +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0 +DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 1 +DCCG_AUDIO_DTO2_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_SEL' +DCCG_AUDIO_DTO_SEL__enumvalues = { + 0: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', + 1: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 2: 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', + 3: 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK', +} +DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0 +DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 1 +DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 2 +DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK = 3 +DCCG_AUDIO_DTO_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_AUDIO_DTO_USE_512FBR_DTO' +DCCG_AUDIO_DTO_USE_512FBR_DTO__enumvalues = { + 0: 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 1: 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', +} +DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0 +DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 1 +DCCG_AUDIO_DTO_USE_512FBR_DTO = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DBG_BLOCK_SEL' +DCCG_DBG_BLOCK_SEL__enumvalues = { + 0: 'DCCG_DBG_BLOCK_SEL_DCCG', + 1: 'DCCG_DBG_BLOCK_SEL_PMON', + 2: 'DCCG_DBG_BLOCK_SEL_PMON2', +} +DCCG_DBG_BLOCK_SEL_DCCG = 0 +DCCG_DBG_BLOCK_SEL_PMON = 1 +DCCG_DBG_BLOCK_SEL_PMON2 = 2 +DCCG_DBG_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DBG_EN' +DCCG_DBG_EN__enumvalues = { + 0: 'DCCG_DBG_EN_DISABLE', + 1: 'DCCG_DBG_EN_ENABLE', +} +DCCG_DBG_EN_DISABLE = 0 +DCCG_DBG_EN_ENABLE = 1 +DCCG_DBG_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_DEEP_COLOR_CNTL' +DCCG_DEEP_COLOR_CNTL__enumvalues = { + 0: 'DCCG_DEEP_COLOR_DTO_DISABLE', + 1: 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', + 2: 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 3: 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', +} +DCCG_DEEP_COLOR_DTO_DISABLE = 0 +DCCG_DEEP_COLOR_DTO_5_4_RATIO = 1 +DCCG_DEEP_COLOR_DTO_3_2_RATIO = 2 +DCCG_DEEP_COLOR_DTO_2_1_RATIO = 3 +DCCG_DEEP_COLOR_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_OVR_EN' +DCCG_FIFO_ERRDET_OVR_EN__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_OVR_DISABLE', + 1: 'DCCG_FIFO_ERRDET_OVR_ENABLE', +} +DCCG_FIFO_ERRDET_OVR_DISABLE = 0 +DCCG_FIFO_ERRDET_OVR_ENABLE = 1 +DCCG_FIFO_ERRDET_OVR_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_RESET' +DCCG_FIFO_ERRDET_RESET__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_RESET_NOOP', + 1: 'DCCG_FIFO_ERRDET_RESET_FORCE', +} +DCCG_FIFO_ERRDET_RESET_NOOP = 0 +DCCG_FIFO_ERRDET_RESET_FORCE = 1 +DCCG_FIFO_ERRDET_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_FIFO_ERRDET_STATE' +DCCG_FIFO_ERRDET_STATE__enumvalues = { + 0: 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', + 1: 'DCCG_FIFO_ERRDET_STATE_DETECTION', +} +DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0 +DCCG_FIFO_ERRDET_STATE_DETECTION = 1 +DCCG_FIFO_ERRDET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_HSYNC' +DCCG_PERF_MODE_HSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_HSYNC_NOOP', + 1: 'DCCG_PERF_MODE_HSYNC_START', +} +DCCG_PERF_MODE_HSYNC_NOOP = 0 +DCCG_PERF_MODE_HSYNC_START = 1 +DCCG_PERF_MODE_HSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_MODE_VSYNC' +DCCG_PERF_MODE_VSYNC__enumvalues = { + 0: 'DCCG_PERF_MODE_VSYNC_NOOP', + 1: 'DCCG_PERF_MODE_VSYNC_START', +} +DCCG_PERF_MODE_VSYNC_NOOP = 0 +DCCG_PERF_MODE_VSYNC_START = 1 +DCCG_PERF_MODE_VSYNC = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_OTG_SELECT' +DCCG_PERF_OTG_SELECT__enumvalues = { + 0: 'DCCG_PERF_SEL_OTG0', + 1: 'DCCG_PERF_SEL_OTG1', + 2: 'DCCG_PERF_SEL_OTG2', + 3: 'DCCG_PERF_SEL_OTG3', + 4: 'DCCG_PERF_SEL_RESERVED', +} +DCCG_PERF_SEL_OTG0 = 0 +DCCG_PERF_SEL_OTG1 = 1 +DCCG_PERF_SEL_OTG2 = 2 +DCCG_PERF_SEL_OTG3 = 3 +DCCG_PERF_SEL_RESERVED = 4 +DCCG_PERF_OTG_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCCG_PERF_RUN' +DCCG_PERF_RUN__enumvalues = { + 0: 'DCCG_PERF_RUN_NOOP', + 1: 'DCCG_PERF_RUN_START', +} +DCCG_PERF_RUN_NOOP = 0 +DCCG_PERF_RUN_START = 1 +DCCG_PERF_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'DC_MEM_GLOBAL_PWR_REQ_DIS' +DC_MEM_GLOBAL_PWR_REQ_DIS__enumvalues = { + 0: 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 1: 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', +} +DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0 +DC_MEM_GLOBAL_PWR_REQ_DISABLE = 1 +DC_MEM_GLOBAL_PWR_REQ_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_FIFO_ERROR' +DIO_FIFO_ERROR__enumvalues = { + 0: 'DIO_FIFO_ERROR_00', + 1: 'DIO_FIFO_ERROR_01', + 2: 'DIO_FIFO_ERROR_10', + 3: 'DIO_FIFO_ERROR_11', +} +DIO_FIFO_ERROR_00 = 0 +DIO_FIFO_ERROR_01 = 1 +DIO_FIFO_ERROR_10 = 2 +DIO_FIFO_ERROR_11 = 3 +DIO_FIFO_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING' +DISABLE_CLOCK_GATING__enumvalues = { + 0: 'CLOCK_GATING_ENABLED', + 1: 'CLOCK_GATING_DISABLED', +} +CLOCK_GATING_ENABLED = 0 +CLOCK_GATING_DISABLED = 1 +DISABLE_CLOCK_GATING = ctypes.c_uint32 # enum + +# values for enumeration 'DISABLE_CLOCK_GATING_IN_DCO' +DISABLE_CLOCK_GATING_IN_DCO__enumvalues = { + 0: 'CLOCK_GATING_ENABLED_IN_DCO', + 1: 'CLOCK_GATING_DISABLED_IN_DCO', +} +CLOCK_GATING_ENABLED_IN_DCO = 0 +CLOCK_GATING_DISABLED_IN_DCO = 1 +DISABLE_CLOCK_GATING_IN_DCO = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_CHG_FWD_CORR_DISABLE' +DISPCLK_CHG_FWD_CORR_DISABLE__enumvalues = { + 0: 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 1: 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', +} +DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0 +DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 1 +DISPCLK_CHG_FWD_CORR_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DISPCLK_FREQ_RAMP_DONE' +DISPCLK_FREQ_RAMP_DONE__enumvalues = { + 0: 'DISPCLK_FREQ_RAMP_IN_PROGRESS', + 1: 'DISPCLK_FREQ_RAMP_COMPLETED', +} +DISPCLK_FREQ_RAMP_IN_PROGRESS = 0 +DISPCLK_FREQ_RAMP_COMPLETED = 1 +DISPCLK_FREQ_RAMP_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DPREFCLK_SRC_SEL' +DPREFCLK_SRC_SEL__enumvalues = { + 0: 'DPREFCLK_SRC_SEL_CK', + 1: 'DPREFCLK_SRC_SEL_P0PLL', + 2: 'DPREFCLK_SRC_SEL_P1PLL', + 3: 'DPREFCLK_SRC_SEL_P2PLL', +} +DPREFCLK_SRC_SEL_CK = 0 +DPREFCLK_SRC_SEL_P0PLL = 1 +DPREFCLK_SRC_SEL_P1PLL = 2 +DPREFCLK_SRC_SEL_P2PLL = 3 +DPREFCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DTO_DS_DISABLE' +DP_DTO_DS_DISABLE__enumvalues = { + 0: 'DP_DTO_DESPREAD_DISABLE', + 1: 'DP_DTO_DESPREAD_ENABLE', +} +DP_DTO_DESPREAD_DISABLE = 0 +DP_DTO_DESPREAD_ENABLE = 1 +DP_DTO_DS_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DS_HW_CAL_ENABLE' +DS_HW_CAL_ENABLE__enumvalues = { + 0: 'DS_HW_CAL_DIS', + 1: 'DS_HW_CAL_EN', +} +DS_HW_CAL_DIS = 0 +DS_HW_CAL_EN = 1 +DS_HW_CAL_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DS_JITTER_COUNT_SRC_SEL' +DS_JITTER_COUNT_SRC_SEL__enumvalues = { + 0: 'DS_JITTER_COUNT_SRC_SEL0', + 1: 'DS_JITTER_COUNT_SRC_SEL1', +} +DS_JITTER_COUNT_SRC_SEL0 = 0 +DS_JITTER_COUNT_SRC_SEL1 = 1 +DS_JITTER_COUNT_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DS_REF_SRC' +DS_REF_SRC__enumvalues = { + 0: 'DS_REF_IS_XTALIN', + 1: 'DS_REF_IS_EXT_GENLOCK', + 2: 'DS_REF_IS_PCIE', +} +DS_REF_IS_XTALIN = 0 +DS_REF_IS_EXT_GENLOCK = 1 +DS_REF_IS_PCIE = 2 +DS_REF_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_IN_PHASE' +DVOACLKC_IN_PHASE__enumvalues = { + 0: 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKC_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_MVP_IN_PHASE' +DVOACLKC_MVP_IN_PHASE__enumvalues = { + 0: 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKC_MVP_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE' +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__enumvalues = { + 0: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', + 1: 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', +} +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0 +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 1 +DVOACLKC_MVP_SKEW_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLKD_IN_PHASE' +DVOACLKD_IN_PHASE__enumvalues = { + 0: 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 1: 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', +} +DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0 +DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 1 +DVOACLKD_IN_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLK_COARSE_SKEW_CNTL' +DVOACLK_COARSE_SKEW_CNTL__enumvalues = { + 0: 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', + 1: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', + 2: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', + 3: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', + 4: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', + 5: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', + 6: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', + 7: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', + 8: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', + 9: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', + 10: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', + 11: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', + 12: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', + 13: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', + 14: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', + 15: 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', + 16: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', + 17: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', + 18: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', + 19: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', + 20: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', + 21: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', + 22: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', + 23: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', + 24: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', + 25: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', + 26: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', + 27: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', + 28: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', + 29: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', + 30: 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', +} +DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0 +DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 1 +DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 2 +DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 3 +DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 4 +DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 5 +DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 6 +DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 7 +DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 8 +DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 9 +DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 10 +DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 11 +DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 12 +DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 13 +DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 14 +DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 15 +DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 16 +DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 17 +DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 18 +DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 19 +DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 20 +DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 21 +DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 22 +DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 23 +DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 24 +DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 25 +DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 26 +DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 27 +DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 28 +DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 29 +DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 30 +DVOACLK_COARSE_SKEW_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DVOACLK_FINE_SKEW_CNTL' +DVOACLK_FINE_SKEW_CNTL__enumvalues = { + 0: 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', + 1: 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', + 2: 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', + 3: 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', + 4: 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', + 5: 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', + 6: 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', + 7: 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', +} +DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0 +DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 1 +DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 2 +DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 3 +DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 4 +DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 5 +DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 6 +DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 7 +DVOACLK_FINE_SKEW_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'DVO_ENABLE_RST' +DVO_ENABLE_RST__enumvalues = { + 0: 'DVO_ENABLE_RST_DISABLE', + 1: 'DVO_ENABLE_RST_ENABLE', +} +DVO_ENABLE_RST_DISABLE = 0 +DVO_ENABLE_RST_ENABLE = 1 +DVO_ENABLE_RST = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE' +ENABLE__enumvalues = { + 0: 'DISABLE_THE_FEATURE', + 1: 'ENABLE_THE_FEATURE', +} +DISABLE_THE_FEATURE = 0 +ENABLE_THE_FEATURE = 1 +ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE_CLOCK' +ENABLE_CLOCK__enumvalues = { + 0: 'ENABLE_THE_REFCLK', + 1: 'ENABLE_THE_FUNC_CLOCK', +} +ENABLE_THE_REFCLK = 0 +ENABLE_THE_FUNC_CLOCK = 1 +ENABLE_CLOCK = ctypes.c_uint32 # enum + +# values for enumeration 'FORCE_DISABLE_CLOCK' +FORCE_DISABLE_CLOCK__enumvalues = { + 0: 'NOT_FORCE_THE_CLOCK_DISABLED', + 1: 'FORCE_THE_CLOCK_DISABLED', +} +NOT_FORCE_THE_CLOCK_DISABLED = 0 +FORCE_THE_CLOCK_DISABLED = 1 +FORCE_DISABLE_CLOCK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMICHARCLK_SRC_SEL' +HDMICHARCLK_SRC_SEL__enumvalues = { + 0: 'HDMICHARCLK_SRC_SEL_UNIPHYA', + 1: 'HDMICHARCLK_SRC_SEL_UNIPHYB', + 2: 'HDMICHARCLK_SRC_SEL_UNIPHYC', + 3: 'HDMICHARCLK_SRC_SEL_UNIPHYD', + 4: 'HDMICHARCLK_SRC_SEL_UNIPHYE', + 5: 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', +} +HDMICHARCLK_SRC_SEL_UNIPHYA = 0 +HDMICHARCLK_SRC_SEL_UNIPHYB = 1 +HDMICHARCLK_SRC_SEL_UNIPHYC = 2 +HDMICHARCLK_SRC_SEL_UNIPHYD = 3 +HDMICHARCLK_SRC_SEL_UNIPHYE = 4 +HDMICHARCLK_SRC_SEL_SRC_RESERVED = 5 +HDMICHARCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMISTREAMCLK_DTO_FORCE_DIS' +HDMISTREAMCLK_DTO_FORCE_DIS__enumvalues = { + 0: 'DTO_FORCE_NO_BYPASS', + 1: 'DTO_FORCE_BYPASS', +} +DTO_FORCE_NO_BYPASS = 0 +DTO_FORCE_BYPASS = 1 +HDMISTREAMCLK_DTO_FORCE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'HDMISTREAMCLK_SRC_SEL' +HDMISTREAMCLK_SRC_SEL__enumvalues = { + 0: 'SEL_REFCLK0', + 1: 'SEL_DTBCLK0', + 2: 'SEL_DTBCLK1', +} +SEL_REFCLK0 = 0 +SEL_DTBCLK0 = 1 +SEL_DTBCLK1 = 2 +HDMISTREAMCLK_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'JITTER_REMOVE_DISABLE' +JITTER_REMOVE_DISABLE__enumvalues = { + 0: 'ENABLE_JITTER_REMOVAL', + 1: 'DISABLE_JITTER_REMOVAL', +} +ENABLE_JITTER_REMOVAL = 0 +DISABLE_JITTER_REMOVAL = 1 +JITTER_REMOVE_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', +} +MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 +MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL' +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 1: 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', +} +MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0 +MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 1 +MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_ADD_PIXEL' +OTG_ADD_PIXEL__enumvalues = { + 0: 'OTG_ADD_PIXEL_NOOP', + 1: 'OTG_ADD_PIXEL_FORCE', +} +OTG_ADD_PIXEL_NOOP = 0 +OTG_ADD_PIXEL_FORCE = 1 +OTG_ADD_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'OTG_DROP_PIXEL' +OTG_DROP_PIXEL__enumvalues = { + 0: 'OTG_DROP_PIXEL_NOOP', + 1: 'OTG_DROP_PIXEL_FORCE', +} +OTG_DROP_PIXEL_NOOP = 0 +OTG_DROP_PIXEL_FORCE = 1 +OTG_DROP_PIXEL = ctypes.c_uint32 # enum + +# values for enumeration 'PHYSYMCLK_FORCE_EN' +PHYSYMCLK_FORCE_EN__enumvalues = { + 0: 'PHYSYMCLK_FORCE_EN_DISABLE', + 1: 'PHYSYMCLK_FORCE_EN_ENABLE', +} +PHYSYMCLK_FORCE_EN_DISABLE = 0 +PHYSYMCLK_FORCE_EN_ENABLE = 1 +PHYSYMCLK_FORCE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PHYSYMCLK_FORCE_SRC_SEL' +PHYSYMCLK_FORCE_SRC_SEL__enumvalues = { + 0: 'PHYSYMCLK_FORCE_SRC_SYMCLK', + 1: 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', + 2: 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', +} +PHYSYMCLK_FORCE_SRC_SYMCLK = 0 +PHYSYMCLK_FORCE_SRC_PHYD18CLK = 1 +PHYSYMCLK_FORCE_SRC_PHYD32CLK = 2 +PHYSYMCLK_FORCE_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PHYPLL_PIXEL_RATE_SOURCE' +PIPE_PHYPLL_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 1: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 2: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 3: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 4: 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', +} +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 1 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 2 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 3 +PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 4 +PIPE_PHYPLL_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_PLL_SOURCE' +PIPE_PIXEL_RATE_PLL_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', + 1: 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', +} +PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0 +PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 1 +PIPE_PIXEL_RATE_PLL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_PIXEL_RATE_SOURCE' +PIPE_PIXEL_RATE_SOURCE__enumvalues = { + 0: 'PIPE_PIXEL_RATE_SOURCE_P0PLL', + 1: 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 2: 'PIPE_PIXEL_RATE_SOURCE_P2PLL', +} +PIPE_PIXEL_RATE_SOURCE_P0PLL = 0 +PIPE_PIXEL_RATE_SOURCE_P1PLL = 1 +PIPE_PIXEL_RATE_SOURCE_P2PLL = 2 +PIPE_PIXEL_RATE_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'PLL_CFG_IF_SOFT_RESET' +PLL_CFG_IF_SOFT_RESET__enumvalues = { + 0: 'PLL_CFG_IF_SOFT_RESET_NOOP', + 1: 'PLL_CFG_IF_SOFT_RESET_FORCE', +} +PLL_CFG_IF_SOFT_RESET_NOOP = 0 +PLL_CFG_IF_SOFT_RESET_FORCE = 1 +PLL_CFG_IF_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_FORCE_EN' +SYMCLK_FE_FORCE_EN__enumvalues = { + 0: 'SYMCLK_FE_FORCE_EN_DISABLE', + 1: 'SYMCLK_FE_FORCE_EN_ENABLE', +} +SYMCLK_FE_FORCE_EN_DISABLE = 0 +SYMCLK_FE_FORCE_EN_ENABLE = 1 +SYMCLK_FE_FORCE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'SYMCLK_FE_FORCE_SRC' +SYMCLK_FE_FORCE_SRC__enumvalues = { + 0: 'SYMCLK_FE_FORCE_SRC_UNIPHYA', + 1: 'SYMCLK_FE_FORCE_SRC_UNIPHYB', + 2: 'SYMCLK_FE_FORCE_SRC_UNIPHYC', + 3: 'SYMCLK_FE_FORCE_SRC_UNIPHYD', + 4: 'SYMCLK_FE_FORCE_SRC_RESERVED', +} +SYMCLK_FE_FORCE_SRC_UNIPHYA = 0 +SYMCLK_FE_FORCE_SRC_UNIPHYB = 1 +SYMCLK_FE_FORCE_SRC_UNIPHYC = 2 +SYMCLK_FE_FORCE_SRC_UNIPHYD = 3 +SYMCLK_FE_FORCE_SRC_RESERVED = 4 +SYMCLK_FE_FORCE_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLK_DIV_SEL' +TEST_CLK_DIV_SEL__enumvalues = { + 0: 'NO_DIV', + 1: 'DIV_2', + 2: 'DIV_4', + 3: 'DIV_8', +} +NO_DIV = 0 +DIV_2 = 1 +DIV_4 = 2 +DIV_8 = 3 +TEST_CLK_DIV_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VSYNC_CNT_LATCH_MASK' +VSYNC_CNT_LATCH_MASK__enumvalues = { + 0: 'VSYNC_CNT_LATCH_MASK_0', + 1: 'VSYNC_CNT_LATCH_MASK_1', +} +VSYNC_CNT_LATCH_MASK_0 = 0 +VSYNC_CNT_LATCH_MASK_1 = 1 +VSYNC_CNT_LATCH_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'VSYNC_CNT_RESET_SEL' +VSYNC_CNT_RESET_SEL__enumvalues = { + 0: 'VSYNC_CNT_RESET_SEL_0', + 1: 'VSYNC_CNT_RESET_SEL_1', +} +VSYNC_CNT_RESET_SEL_0 = 0 +VSYNC_CNT_RESET_SEL_1 = 1 +VSYNC_CNT_RESET_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_CLOCK_SOURCE_SEL' +XTAL_REF_CLOCK_SOURCE_SEL__enumvalues = { + 0: 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', + 1: 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', +} +XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0 +XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 1 +XTAL_REF_CLOCK_SOURCE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'XTAL_REF_SEL' +XTAL_REF_SEL__enumvalues = { + 0: 'XTAL_REF_SEL_1X', + 1: 'XTAL_REF_SEL_2X', +} +XTAL_REF_SEL_1X = 0 +XTAL_REF_SEL_2X = 1 +XTAL_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_ACK' +HPD_INT_CONTROL_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_ACK_0', + 1: 'HPD_INT_CONTROL_ACK_1', +} +HPD_INT_CONTROL_ACK_0 = 0 +HPD_INT_CONTROL_ACK_1 = 1 +HPD_INT_CONTROL_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_POLARITY' +HPD_INT_CONTROL_POLARITY__enumvalues = { + 0: 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', + 1: 'HPD_INT_CONTROL_GEN_INT_ON_CON', +} +HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0 +HPD_INT_CONTROL_GEN_INT_ON_CON = 1 +HPD_INT_CONTROL_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'HPD_INT_CONTROL_RX_INT_ACK' +HPD_INT_CONTROL_RX_INT_ACK__enumvalues = { + 0: 'HPD_INT_CONTROL_RX_INT_ACK_0', + 1: 'HPD_INT_CONTROL_RX_INT_ACK_1', +} +HPD_INT_CONTROL_RX_INT_ACK_0 = 0 +HPD_INT_CONTROL_RX_INT_ACK_1 = 1 +HPD_INT_CONTROL_RX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_CUR_DISP' +DPHY_8B10B_CUR_DISP__enumvalues = { + 0: 'DPHY_8B10B_CUR_DISP_ZERO', + 1: 'DPHY_8B10B_CUR_DISP_ONE', +} +DPHY_8B10B_CUR_DISP_ZERO = 0 +DPHY_8B10B_CUR_DISP_ONE = 1 +DPHY_8B10B_CUR_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_8B10B_RESET' +DPHY_8B10B_RESET__enumvalues = { + 0: 'DPHY_8B10B_NOT_RESET', + 1: 'DPHY_8B10B_RESETET', +} +DPHY_8B10B_NOT_RESET = 0 +DPHY_8B10B_RESETET = 1 +DPHY_8B10B_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_EN' +DPHY_ALT_SCRAMBLER_RESET_EN__enumvalues = { + 0: 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', + 1: 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', +} +DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0 +DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 1 +DPHY_ALT_SCRAMBLER_RESET_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ALT_SCRAMBLER_RESET_SEL' +DPHY_ALT_SCRAMBLER_RESET_SEL__enumvalues = { + 0: 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', + 1: 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', +} +DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0 +DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 1 +DPHY_ALT_SCRAMBLER_RESET_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE0' +DPHY_ATEST_SEL_LANE0__enumvalues = { + 0: 'DPHY_ATEST_LANE0_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE0_REG_PATTERN', +} +DPHY_ATEST_LANE0_PRBS_PATTERN = 0 +DPHY_ATEST_LANE0_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE0 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE1' +DPHY_ATEST_SEL_LANE1__enumvalues = { + 0: 'DPHY_ATEST_LANE1_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE1_REG_PATTERN', +} +DPHY_ATEST_LANE1_PRBS_PATTERN = 0 +DPHY_ATEST_LANE1_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE1 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE2' +DPHY_ATEST_SEL_LANE2__enumvalues = { + 0: 'DPHY_ATEST_LANE2_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE2_REG_PATTERN', +} +DPHY_ATEST_LANE2_PRBS_PATTERN = 0 +DPHY_ATEST_LANE2_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE2 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_ATEST_SEL_LANE3' +DPHY_ATEST_SEL_LANE3__enumvalues = { + 0: 'DPHY_ATEST_LANE3_PRBS_PATTERN', + 1: 'DPHY_ATEST_LANE3_REG_PATTERN', +} +DPHY_ATEST_LANE3_PRBS_PATTERN = 0 +DPHY_ATEST_LANE3_REG_PATTERN = 1 +DPHY_ATEST_SEL_LANE3 = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_BYPASS' +DPHY_BYPASS__enumvalues = { + 0: 'DPHY_8B10B_OUTPUT', + 1: 'DPHY_DBG_OUTPUT', +} +DPHY_8B10B_OUTPUT = 0 +DPHY_DBG_OUTPUT = 1 +DPHY_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_CONT_EN' +DPHY_CRC_CONT_EN__enumvalues = { + 0: 'DPHY_CRC_ONE_SHOT', + 1: 'DPHY_CRC_CONTINUOUS', +} +DPHY_CRC_ONE_SHOT = 0 +DPHY_CRC_CONTINUOUS = 1 +DPHY_CRC_CONT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_EN' +DPHY_CRC_EN__enumvalues = { + 0: 'DPHY_CRC_DISABLED', + 1: 'DPHY_CRC_ENABLED', +} +DPHY_CRC_DISABLED = 0 +DPHY_CRC_ENABLED = 1 +DPHY_CRC_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_FIELD' +DPHY_CRC_FIELD__enumvalues = { + 0: 'DPHY_CRC_START_FROM_TOP_FIELD', + 1: 'DPHY_CRC_START_FROM_BOTTOM_FIELD', +} +DPHY_CRC_START_FROM_TOP_FIELD = 0 +DPHY_CRC_START_FROM_BOTTOM_FIELD = 1 +DPHY_CRC_FIELD = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_MST_PHASE_ERROR_ACK' +DPHY_CRC_MST_PHASE_ERROR_ACK__enumvalues = { + 0: 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', + 1: 'DPHY_CRC_MST_PHASE_ERROR_ACKED', +} +DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0 +DPHY_CRC_MST_PHASE_ERROR_ACKED = 1 +DPHY_CRC_MST_PHASE_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_CRC_SEL' +DPHY_CRC_SEL__enumvalues = { + 0: 'DPHY_CRC_LANE0_SELECTED', + 1: 'DPHY_CRC_LANE1_SELECTED', + 2: 'DPHY_CRC_LANE2_SELECTED', + 3: 'DPHY_CRC_LANE3_SELECTED', +} +DPHY_CRC_LANE0_SELECTED = 0 +DPHY_CRC_LANE1_SELECTED = 1 +DPHY_CRC_LANE2_SELECTED = 2 +DPHY_CRC_LANE3_SELECTED = 3 +DPHY_CRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_FEC_ENABLE' +DPHY_FEC_ENABLE__enumvalues = { + 0: 'DPHY_FEC_DISABLED', + 1: 'DPHY_FEC_ENABLED', +} +DPHY_FEC_DISABLED = 0 +DPHY_FEC_ENABLED = 1 +DPHY_FEC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_FEC_READY' +DPHY_FEC_READY__enumvalues = { + 0: 'DPHY_FEC_READY_EN', + 1: 'DPHY_FEC_READY_DIS', +} +DPHY_FEC_READY_EN = 0 +DPHY_FEC_READY_DIS = 1 +DPHY_FEC_READY = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_LOAD_BS_COUNT_START' +DPHY_LOAD_BS_COUNT_START__enumvalues = { + 0: 'DPHY_LOAD_BS_COUNT_STARTED', + 1: 'DPHY_LOAD_BS_COUNT_NOT_STARTED', +} +DPHY_LOAD_BS_COUNT_STARTED = 0 +DPHY_LOAD_BS_COUNT_NOT_STARTED = 1 +DPHY_LOAD_BS_COUNT_START = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_EN' +DPHY_PRBS_EN__enumvalues = { + 0: 'DPHY_PRBS_DISABLE', + 1: 'DPHY_PRBS_ENABLE', +} +DPHY_PRBS_DISABLE = 0 +DPHY_PRBS_ENABLE = 1 +DPHY_PRBS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_PRBS_SEL' +DPHY_PRBS_SEL__enumvalues = { + 0: 'DPHY_PRBS7_SELECTED', + 1: 'DPHY_PRBS23_SELECTED', + 2: 'DPHY_PRBS11_SELECTED', +} +DPHY_PRBS7_SELECTED = 0 +DPHY_PRBS23_SELECTED = 1 +DPHY_PRBS11_SELECTED = 2 +DPHY_PRBS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_RX_FAST_TRAINING_CAPABLE' +DPHY_RX_FAST_TRAINING_CAPABLE__enumvalues = { + 0: 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 1: 'DPHY_FAST_TRAINING_CAPABLE', +} +DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0 +DPHY_FAST_TRAINING_CAPABLE = 1 +DPHY_RX_FAST_TRAINING_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_ADVANCE' +DPHY_SCRAMBLER_ADVANCE__enumvalues = { + 0: 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', + 1: 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', +} +DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0 +DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 1 +DPHY_SCRAMBLER_ADVANCE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_DIS' +DPHY_SCRAMBLER_DIS__enumvalues = { + 0: 'DPHY_SCR_ENABLED', + 1: 'DPHY_SCR_DISABLED', +} +DPHY_SCR_ENABLED = 0 +DPHY_SCR_DISABLED = 1 +DPHY_SCRAMBLER_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_KCODE' +DPHY_SCRAMBLER_KCODE__enumvalues = { + 0: 'DPHY_SCRAMBLER_KCODE_DISABLED', + 1: 'DPHY_SCRAMBLER_KCODE_ENABLED', +} +DPHY_SCRAMBLER_KCODE_DISABLED = 0 +DPHY_SCRAMBLER_KCODE_ENABLED = 1 +DPHY_SCRAMBLER_KCODE = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SCRAMBLER_SEL' +DPHY_SCRAMBLER_SEL__enumvalues = { + 0: 'DPHY_SCRAMBLER_SEL_LANE_DATA', + 1: 'DPHY_SCRAMBLER_SEL_DBG_DATA', +} +DPHY_SCRAMBLER_SEL_LANE_DATA = 0 +DPHY_SCRAMBLER_SEL_DBG_DATA = 1 +DPHY_SCRAMBLER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SKEW_BYPASS' +DPHY_SKEW_BYPASS__enumvalues = { + 0: 'DPHY_WITH_SKEW', + 1: 'DPHY_NO_SKEW', +} +DPHY_WITH_SKEW = 0 +DPHY_NO_SKEW = 1 +DPHY_SKEW_BYPASS = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM' +DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM__enumvalues = { + 0: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', + 1: 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', +} +DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0 +DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 1 +DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_SW_FAST_TRAINING_START' +DPHY_SW_FAST_TRAINING_START__enumvalues = { + 0: 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 1: 'DPHY_SW_FAST_TRAINING_STARTED', +} +DPHY_SW_FAST_TRAINING_NOT_STARTED = 0 +DPHY_SW_FAST_TRAINING_STARTED = 1 +DPHY_SW_FAST_TRAINING_START = ctypes.c_uint32 # enum + +# values for enumeration 'DPHY_TRAINING_PATTERN_SEL' +DPHY_TRAINING_PATTERN_SEL__enumvalues = { + 0: 'DPHY_TRAINING_PATTERN_1', + 1: 'DPHY_TRAINING_PATTERN_2', + 2: 'DPHY_TRAINING_PATTERN_3', + 3: 'DPHY_TRAINING_PATTERN_4', +} +DPHY_TRAINING_PATTERN_1 = 0 +DPHY_TRAINING_PATTERN_2 = 1 +DPHY_TRAINING_PATTERN_3 = 2 +DPHY_TRAINING_PATTERN_4 = 3 +DPHY_TRAINING_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_COMPONENT_DEPTH' +DP_COMPONENT_DEPTH__enumvalues = { + 0: 'DP_COMPONENT_DEPTH_6BPC', + 1: 'DP_COMPONENT_DEPTH_8BPC', + 2: 'DP_COMPONENT_DEPTH_10BPC', + 3: 'DP_COMPONENT_DEPTH_12BPC', + 4: 'DP_COMPONENT_DEPTH_16BPC', +} +DP_COMPONENT_DEPTH_6BPC = 0 +DP_COMPONENT_DEPTH_8BPC = 1 +DP_COMPONENT_DEPTH_10BPC = 2 +DP_COMPONENT_DEPTH_12BPC = 3 +DP_COMPONENT_DEPTH_16BPC = 4 +DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'DP_CP_ENCRYPTION_TYPE' +DP_CP_ENCRYPTION_TYPE__enumvalues = { + 0: 'DP_CP_ENCRYPTION_TYPE_0', + 1: 'DP_CP_ENCRYPTION_TYPE_1', +} +DP_CP_ENCRYPTION_TYPE_0 = 0 +DP_CP_ENCRYPTION_TYPE_1 = 1 +DP_CP_ENCRYPTION_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_8B10B_EXT_DISP' +DP_DPHY_8B10B_EXT_DISP__enumvalues = { + 0: 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 1: 'DP_DPHY_8B10B_EXT_DISP_ONE', +} +DP_DPHY_8B10B_EXT_DISP_ZERO = 0 +DP_DPHY_8B10B_EXT_DISP_ONE = 1 +DP_DPHY_8B10B_EXT_DISP = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK' +DP_DPHY_FAST_TRAINING_COMPLETE_ACK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK' +DP_DPHY_FAST_TRAINING_COMPLETE_MASK__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 1: 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', +} +DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0 +DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 1 +DP_DPHY_FAST_TRAINING_COMPLETE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN' +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__enumvalues = { + 0: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 1: 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', +} +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 1 +DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE' +DP_DPHY_HBR2_PATTERN_CONTROL_MODE__enumvalues = { + 0: 'DP_DPHY_HBR2_PASS_THROUGH', + 1: 'DP_DPHY_HBR2_PATTERN_1', + 2: 'DP_DPHY_HBR2_PATTERN_2_NEG', + 3: 'DP_DPHY_HBR2_PATTERN_3', + 6: 'DP_DPHY_HBR2_PATTERN_2_POS', +} +DP_DPHY_HBR2_PASS_THROUGH = 0 +DP_DPHY_HBR2_PATTERN_1 = 1 +DP_DPHY_HBR2_PATTERN_2_NEG = 2 +DP_DPHY_HBR2_PATTERN_3 = 3 +DP_DPHY_HBR2_PATTERN_2_POS = 6 +DP_DPHY_HBR2_PATTERN_CONTROL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_DSC_MODE' +DP_DSC_MODE__enumvalues = { + 0: 'DP_DSC_DISABLE', + 1: 'DP_DSC_444_SIMPLE_422', + 2: 'DP_DSC_NATIVE_422_420', +} +DP_DSC_DISABLE = 0 +DP_DSC_444_SIMPLE_422 = 1 +DP_DSC_NATIVE_422_420 = 2 +DP_DSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_EMBEDDED_PANEL_MODE' +DP_EMBEDDED_PANEL_MODE__enumvalues = { + 0: 'DP_EXTERNAL_PANEL', + 1: 'DP_EMBEDDED_PANEL', +} +DP_EXTERNAL_PANEL = 0 +DP_EMBEDDED_PANEL = 1 +DP_EMBEDDED_PANEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_LINK_TRAINING_COMPLETE' +DP_LINK_TRAINING_COMPLETE__enumvalues = { + 0: 'DP_LINK_TRAINING_NOT_COMPLETE', + 1: 'DP_LINK_TRAINING_ALREADY_COMPLETE', +} +DP_LINK_TRAINING_NOT_COMPLETE = 0 +DP_LINK_TRAINING_ALREADY_COMPLETE = 1 +DP_LINK_TRAINING_COMPLETE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_LINK_TRAINING_SWITCH_MODE' +DP_LINK_TRAINING_SWITCH_MODE__enumvalues = { + 0: 'DP_LINK_TRAINING_SWITCH_TO_IDLE', + 1: 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', +} +DP_LINK_TRAINING_SWITCH_TO_IDLE = 0 +DP_LINK_TRAINING_SWITCH_TO_VIDEO = 1 +DP_LINK_TRAINING_SWITCH_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_ML_PHY_SEQ_MODE' +DP_ML_PHY_SEQ_MODE__enumvalues = { + 0: 'DP_ML_PHY_SEQ_LINE_NUM', + 1: 'DP_ML_PHY_SEQ_IMMEDIATE', +} +DP_ML_PHY_SEQ_LINE_NUM = 0 +DP_ML_PHY_SEQ_IMMEDIATE = 1 +DP_ML_PHY_SEQ_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSA_V_TIMING_OVERRIDE_EN' +DP_MSA_V_TIMING_OVERRIDE_EN__enumvalues = { + 0: 'MSA_V_TIMING_OVERRIDE_DISABLED', + 1: 'MSA_V_TIMING_OVERRIDE_ENABLED', +} +MSA_V_TIMING_OVERRIDE_DISABLED = 0 +MSA_V_TIMING_OVERRIDE_ENABLED = 1 +DP_MSA_V_TIMING_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_BLANK_CODE' +DP_MSE_BLANK_CODE__enumvalues = { + 0: 'DP_MSE_BLANK_CODE_SF_FILLED', + 1: 'DP_MSE_BLANK_CODE_ZERO_FILLED', +} +DP_MSE_BLANK_CODE_SF_FILLED = 0 +DP_MSE_BLANK_CODE_ZERO_FILLED = 1 +DP_MSE_BLANK_CODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_LINK_LINE' +DP_MSE_LINK_LINE__enumvalues = { + 0: 'DP_MSE_LINK_LINE_32_MTP_LONG', + 1: 'DP_MSE_LINK_LINE_64_MTP_LONG', + 2: 'DP_MSE_LINK_LINE_128_MTP_LONG', + 3: 'DP_MSE_LINK_LINE_256_MTP_LONG', +} +DP_MSE_LINK_LINE_32_MTP_LONG = 0 +DP_MSE_LINK_LINE_64_MTP_LONG = 1 +DP_MSE_LINK_LINE_128_MTP_LONG = 2 +DP_MSE_LINK_LINE_256_MTP_LONG = 3 +DP_MSE_LINK_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT0' +DP_MSE_SAT_ENCRYPT0__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT0_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT0_ENABLED', +} +DP_MSE_SAT_ENCRYPT0_DISABLED = 0 +DP_MSE_SAT_ENCRYPT0_ENABLED = 1 +DP_MSE_SAT_ENCRYPT0 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT1' +DP_MSE_SAT_ENCRYPT1__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT1_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT1_ENABLED', +} +DP_MSE_SAT_ENCRYPT1_DISABLED = 0 +DP_MSE_SAT_ENCRYPT1_ENABLED = 1 +DP_MSE_SAT_ENCRYPT1 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT2' +DP_MSE_SAT_ENCRYPT2__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT2_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT2_ENABLED', +} +DP_MSE_SAT_ENCRYPT2_DISABLED = 0 +DP_MSE_SAT_ENCRYPT2_ENABLED = 1 +DP_MSE_SAT_ENCRYPT2 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT3' +DP_MSE_SAT_ENCRYPT3__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT3_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT3_ENABLED', +} +DP_MSE_SAT_ENCRYPT3_DISABLED = 0 +DP_MSE_SAT_ENCRYPT3_ENABLED = 1 +DP_MSE_SAT_ENCRYPT3 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT4' +DP_MSE_SAT_ENCRYPT4__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT4_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT4_ENABLED', +} +DP_MSE_SAT_ENCRYPT4_DISABLED = 0 +DP_MSE_SAT_ENCRYPT4_ENABLED = 1 +DP_MSE_SAT_ENCRYPT4 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_ENCRYPT5' +DP_MSE_SAT_ENCRYPT5__enumvalues = { + 0: 'DP_MSE_SAT_ENCRYPT5_DISABLED', + 1: 'DP_MSE_SAT_ENCRYPT5_ENABLED', +} +DP_MSE_SAT_ENCRYPT5_DISABLED = 0 +DP_MSE_SAT_ENCRYPT5_ENABLED = 1 +DP_MSE_SAT_ENCRYPT5 = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_SAT_UPDATE_ACT' +DP_MSE_SAT_UPDATE_ACT__enumvalues = { + 0: 'DP_MSE_SAT_UPDATE_NO_ACTION', + 1: 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', + 2: 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', +} +DP_MSE_SAT_UPDATE_NO_ACTION = 0 +DP_MSE_SAT_UPDATE_WITH_TRIGGER = 1 +DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 2 +DP_MSE_SAT_UPDATE_ACT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_TIMESTAMP_MODE' +DP_MSE_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 1: 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', +} +DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0 +DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 1 +DP_MSE_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSE_ZERO_ENCODER' +DP_MSE_ZERO_ENCODER__enumvalues = { + 0: 'DP_MSE_NOT_ZERO_FE_ENCODER', + 1: 'DP_MSE_ZERO_FE_ENCODER', +} +DP_MSE_NOT_ZERO_FE_ENCODER = 0 +DP_MSE_ZERO_FE_ENCODER = 1 +DP_MSE_ZERO_ENCODER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_MSO_NUM_OF_SST_LINKS' +DP_MSO_NUM_OF_SST_LINKS__enumvalues = { + 0: 'DP_MSO_ONE_SSTLINK', + 1: 'DP_MSO_TWO_SSTLINK', + 2: 'DP_MSO_FOUR_SSTLINK', +} +DP_MSO_ONE_SSTLINK = 0 +DP_MSO_TWO_SSTLINK = 1 +DP_MSO_FOUR_SSTLINK = 2 +DP_MSO_NUM_OF_SST_LINKS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_PIXEL_ENCODING' +DP_PIXEL_ENCODING__enumvalues = { + 0: 'DP_PIXEL_ENCODING_RGB444', + 1: 'DP_PIXEL_ENCODING_YCBCR422', + 2: 'DP_PIXEL_ENCODING_YCBCR444', + 3: 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', + 4: 'DP_PIXEL_ENCODING_Y_ONLY', + 5: 'DP_PIXEL_ENCODING_YCBCR420', +} +DP_PIXEL_ENCODING_RGB444 = 0 +DP_PIXEL_ENCODING_YCBCR422 = 1 +DP_PIXEL_ENCODING_YCBCR444 = 2 +DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 3 +DP_PIXEL_ENCODING_Y_ONLY = 4 +DP_PIXEL_ENCODING_YCBCR420 = 5 +DP_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'DP_PIXEL_PER_CYCLE_PROCESSING_NUM' +DP_PIXEL_PER_CYCLE_PROCESSING_NUM__enumvalues = { + 0: 'DP_ONE_PIXEL_PER_CYCLE', + 1: 'DP_TWO_PIXEL_PER_CYCLE', +} +DP_ONE_PIXEL_PER_CYCLE = 0 +DP_TWO_PIXEL_PER_CYCLE = 1 +DP_PIXEL_PER_CYCLE_PROCESSING_NUM = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE' +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { + 0: 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 1: 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', +} +DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 +DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_ASP_PRIORITY' +DP_SEC_ASP_PRIORITY__enumvalues = { + 0: 'DP_SEC_ASP_LOW_PRIORITY', + 1: 'DP_SEC_ASP_HIGH_PRIORITY', +} +DP_SEC_ASP_LOW_PRIORITY = 0 +DP_SEC_ASP_HIGH_PRIORITY = 1 +DP_SEC_ASP_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_AUDIO_MUTE' +DP_SEC_AUDIO_MUTE__enumvalues = { + 0: 'DP_SEC_AUDIO_MUTE_HW_CTRL', + 1: 'DP_SEC_AUDIO_MUTE_SW_CTRL', +} +DP_SEC_AUDIO_MUTE_HW_CTRL = 0 +DP_SEC_AUDIO_MUTE_SW_CTRL = 1 +DP_SEC_AUDIO_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_COLLISION_ACK' +DP_SEC_COLLISION_ACK__enumvalues = { + 0: 'DP_SEC_COLLISION_ACK_NO_EFFECT', + 1: 'DP_SEC_COLLISION_ACK_CLR_FLAG', +} +DP_SEC_COLLISION_ACK_NO_EFFECT = 0 +DP_SEC_COLLISION_ACK_CLR_FLAG = 1 +DP_SEC_COLLISION_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP0_PRIORITY' +DP_SEC_GSP0_PRIORITY__enumvalues = { + 0: 'SEC_GSP0_PRIORITY_LOW', + 1: 'SEC_GSP0_PRIORITY_HIGH', +} +SEC_GSP0_PRIORITY_LOW = 0 +SEC_GSP0_PRIORITY_HIGH = 1 +DP_SEC_GSP0_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND' +DP_SEC_GSP_SEND__enumvalues = { + 0: 'NOT_SENT', + 1: 'FORCE_SENT', +} +NOT_SENT = 0 +FORCE_SENT = 1 +DP_SEC_GSP_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND_ANY_LINE' +DP_SEC_GSP_SEND_ANY_LINE__enumvalues = { + 0: 'SEND_AT_LINK_NUMBER', + 1: 'SEND_AT_EARLIEST_TIME', +} +SEND_AT_LINK_NUMBER = 0 +SEND_AT_EARLIEST_TIME = 1 +DP_SEC_GSP_SEND_ANY_LINE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_GSP_SEND_PPS' +DP_SEC_GSP_SEND_PPS__enumvalues = { + 0: 'SEND_NORMAL_PACKET', + 1: 'SEND_PPS_PACKET', +} +SEND_NORMAL_PACKET = 0 +SEND_PPS_PACKET = 1 +DP_SEC_GSP_SEND_PPS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_LINE_REFERENCE' +DP_SEC_LINE_REFERENCE__enumvalues = { + 0: 'REFER_TO_DP_SOF', + 1: 'REFER_TO_OTG_SOF', +} +REFER_TO_DP_SOF = 0 +REFER_TO_OTG_SOF = 1 +DP_SEC_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SEC_TIMESTAMP_MODE' +DP_SEC_TIMESTAMP_MODE__enumvalues = { + 0: 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', + 1: 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', +} +DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0 +DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 1 +DP_SEC_TIMESTAMP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_ACK' +DP_STEER_OVERFLOW_ACK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0 +DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_STEER_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STEER_OVERFLOW_MASK' +DP_STEER_OVERFLOW_MASK__enumvalues = { + 0: 'DP_STEER_OVERFLOW_MASKED', + 1: 'DP_STEER_OVERFLOW_UNMASK', +} +DP_STEER_OVERFLOW_MASKED = 0 +DP_STEER_OVERFLOW_UNMASK = 1 +DP_STEER_OVERFLOW_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_SYNC_POLARITY' +DP_SYNC_POLARITY__enumvalues = { + 0: 'DP_SYNC_POLARITY_ACTIVE_HIGH', + 1: 'DP_SYNC_POLARITY_ACTIVE_LOW', +} +DP_SYNC_POLARITY_ACTIVE_HIGH = 0 +DP_SYNC_POLARITY_ACTIVE_LOW = 1 +DP_SYNC_POLARITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_TU_OVERFLOW_ACK' +DP_TU_OVERFLOW_ACK__enumvalues = { + 0: 'DP_TU_OVERFLOW_ACK_NO_EFFECT', + 1: 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', +} +DP_TU_OVERFLOW_ACK_NO_EFFECT = 0 +DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 1 +DP_TU_OVERFLOW_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_UDI_LANES' +DP_UDI_LANES__enumvalues = { + 0: 'DP_UDI_1_LANE', + 1: 'DP_UDI_2_LANES', + 2: 'DP_UDI_LANES_RESERVED', + 3: 'DP_UDI_4_LANES', +} +DP_UDI_1_LANE = 0 +DP_UDI_2_LANES = 1 +DP_UDI_LANES_RESERVED = 2 +DP_UDI_4_LANES = 3 +DP_UDI_LANES = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_ENHANCED_FRAME_MODE' +DP_VID_ENHANCED_FRAME_MODE__enumvalues = { + 0: 'VID_NORMAL_FRAME_MODE', + 1: 'VID_ENHANCED_MODE', +} +VID_NORMAL_FRAME_MODE = 0 +VID_ENHANCED_MODE = 1 +DP_VID_ENHANCED_FRAME_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_DOUBLE_BUFFER_MODE' +DP_VID_M_N_DOUBLE_BUFFER_MODE__enumvalues = { + 0: 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 1: 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', +} +DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0 +DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 1 +DP_VID_M_N_DOUBLE_BUFFER_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_M_N_GEN_EN' +DP_VID_M_N_GEN_EN__enumvalues = { + 0: 'DP_VID_M_N_PROGRAMMED_VIA_REG', + 1: 'DP_VID_M_N_CALC_AUTO', +} +DP_VID_M_N_PROGRAMMED_VIA_REG = 0 +DP_VID_M_N_CALC_AUTO = 1 +DP_VID_M_N_GEN_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_N_MUL' +DP_VID_N_MUL__enumvalues = { + 0: 'DP_VID_M_1X_INPUT_PIXEL_RATE', + 1: 'DP_VID_M_2X_INPUT_PIXEL_RATE', + 2: 'DP_VID_M_4X_INPUT_PIXEL_RATE', + 3: 'DP_VID_M_8X_INPUT_PIXEL_RATE', +} +DP_VID_M_1X_INPUT_PIXEL_RATE = 0 +DP_VID_M_2X_INPUT_PIXEL_RATE = 1 +DP_VID_M_4X_INPUT_PIXEL_RATE = 2 +DP_VID_M_8X_INPUT_PIXEL_RATE = 3 +DP_VID_N_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_ACK' +DP_VID_STREAM_DISABLE_ACK__enumvalues = { + 0: 'ID_STREAM_DISABLE_NO_ACK', + 1: 'ID_STREAM_DISABLE_ACKED', +} +ID_STREAM_DISABLE_NO_ACK = 0 +ID_STREAM_DISABLE_ACKED = 1 +DP_VID_STREAM_DISABLE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DISABLE_MASK' +DP_VID_STREAM_DISABLE_MASK__enumvalues = { + 0: 'VID_STREAM_DISABLE_MASKED', + 1: 'VID_STREAM_DISABLE_UNMASK', +} +VID_STREAM_DISABLE_MASKED = 0 +VID_STREAM_DISABLE_UNMASK = 1 +DP_VID_STREAM_DISABLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_STREAM_DIS_DEFER' +DP_VID_STREAM_DIS_DEFER__enumvalues = { + 0: 'DP_VID_STREAM_DIS_NO_DEFER', + 1: 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 2: 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', +} +DP_VID_STREAM_DIS_NO_DEFER = 0 +DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 1 +DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 2 +DP_VID_STREAM_DIS_DEFER = ctypes.c_uint32 # enum + +# values for enumeration 'DP_VID_VBID_FIELD_POL' +DP_VID_VBID_FIELD_POL__enumvalues = { + 0: 'DP_VID_VBID_FIELD_POL_NORMAL', + 1: 'DP_VID_VBID_FIELD_POL_INV', +} +DP_VID_VBID_FIELD_POL_NORMAL = 0 +DP_VID_VBID_FIELD_POL_INV = 1 +DP_VID_VBID_FIELD_POL = ctypes.c_uint32 # enum + +# values for enumeration 'FEC_ACTIVE_STATUS' +FEC_ACTIVE_STATUS__enumvalues = { + 0: 'DPHY_FEC_NOT_ACTIVE', + 1: 'DPHY_FEC_ACTIVE', +} +DPHY_FEC_NOT_ACTIVE = 0 +DPHY_FEC_ACTIVE = 1 +FEC_ACTIVE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_HPD_SELECT' +DIG_BE_CNTL_HPD_SELECT__enumvalues = { + 0: 'DIG_BE_CNTL_HPD1', + 1: 'DIG_BE_CNTL_HPD2', + 2: 'DIG_BE_CNTL_HPD3', + 3: 'DIG_BE_CNTL_HPD4', + 4: 'DIG_BE_CNTL_HPD5', + 5: 'DIG_BE_CNTL_NO_HPD', +} +DIG_BE_CNTL_HPD1 = 0 +DIG_BE_CNTL_HPD2 = 1 +DIG_BE_CNTL_HPD3 = 2 +DIG_BE_CNTL_HPD4 = 3 +DIG_BE_CNTL_HPD5 = 4 +DIG_BE_CNTL_NO_HPD = 5 +DIG_BE_CNTL_HPD_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_BE_CNTL_MODE' +DIG_BE_CNTL_MODE__enumvalues = { + 0: 'DIG_BE_DP_SST_MODE', + 1: 'DIG_BE_RESERVED1', + 2: 'DIG_BE_TMDS_DVI_MODE', + 3: 'DIG_BE_TMDS_HDMI_MODE', + 4: 'DIG_BE_RESERVED4', + 5: 'DIG_BE_DP_MST_MODE', + 6: 'DIG_BE_RESERVED2', + 7: 'DIG_BE_RESERVED3', +} +DIG_BE_DP_SST_MODE = 0 +DIG_BE_RESERVED1 = 1 +DIG_BE_TMDS_DVI_MODE = 2 +DIG_BE_TMDS_HDMI_MODE = 3 +DIG_BE_RESERVED4 = 4 +DIG_BE_DP_MST_MODE = 5 +DIG_BE_RESERVED2 = 6 +DIG_BE_RESERVED3 = 7 +DIG_BE_CNTL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_DIGITAL_BYPASS_ENABLE' +DIG_DIGITAL_BYPASS_ENABLE__enumvalues = { + 0: 'DIG_DIGITAL_BYPASS_OFF', + 1: 'DIG_DIGITAL_BYPASS_ON', +} +DIG_DIGITAL_BYPASS_OFF = 0 +DIG_DIGITAL_BYPASS_ON = 1 +DIG_DIGITAL_BYPASS_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_DIGITAL_BYPASS_SEL' +DIG_DIGITAL_BYPASS_SEL__enumvalues = { + 0: 'DIG_DIGITAL_BYPASS_SEL_BYPASS', + 1: 'DIG_DIGITAL_BYPASS_SEL_36BPP', + 2: 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', + 3: 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', + 4: 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', + 5: 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', + 6: 'DIG_DIGITAL_BYPASS_SEL_ALPHA', +} +DIG_DIGITAL_BYPASS_SEL_BYPASS = 0 +DIG_DIGITAL_BYPASS_SEL_36BPP = 1 +DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 2 +DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 3 +DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 4 +DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 5 +DIG_DIGITAL_BYPASS_SEL_ALPHA = 6 +DIG_DIGITAL_BYPASS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_SOURCE_SELECT' +DIG_FE_CNTL_SOURCE_SELECT__enumvalues = { + 0: 'DIG_FE_SOURCE_FROM_OTG0', + 1: 'DIG_FE_SOURCE_FROM_OTG1', + 2: 'DIG_FE_SOURCE_FROM_OTG2', + 3: 'DIG_FE_SOURCE_FROM_OTG3', + 4: 'DIG_FE_SOURCE_RESERVED', +} +DIG_FE_SOURCE_FROM_OTG0 = 0 +DIG_FE_SOURCE_FROM_OTG1 = 1 +DIG_FE_SOURCE_FROM_OTG2 = 2 +DIG_FE_SOURCE_FROM_OTG3 = 3 +DIG_FE_SOURCE_RESERVED = 4 +DIG_FE_CNTL_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FE_CNTL_STEREOSYNC_SELECT' +DIG_FE_CNTL_STEREOSYNC_SELECT__enumvalues = { + 0: 'DIG_FE_STEREOSYNC_FROM_OTG0', + 1: 'DIG_FE_STEREOSYNC_FROM_OTG1', + 2: 'DIG_FE_STEREOSYNC_FROM_OTG2', + 3: 'DIG_FE_STEREOSYNC_FROM_OTG3', + 4: 'DIG_FE_STEREOSYNC_RESERVED', +} +DIG_FE_STEREOSYNC_FROM_OTG0 = 0 +DIG_FE_STEREOSYNC_FROM_OTG1 = 1 +DIG_FE_STEREOSYNC_FROM_OTG2 = 2 +DIG_FE_STEREOSYNC_FROM_OTG3 = 3 +DIG_FE_STEREOSYNC_RESERVED = 4 +DIG_FE_CNTL_STEREOSYNC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX' +DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', + 1: 'DIG_FIFO_FORCE_RECOMP_MINMAX', +} +DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0 +DIG_FIFO_FORCE_RECOMP_MINMAX = 1 +DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL' +DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL__enumvalues = { + 0: 'DIG_FIFO_USE_OVERWRITE_LEVEL', + 1: 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', +} +DIG_FIFO_USE_OVERWRITE_LEVEL = 0 +DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 1 +DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_FORCE_RECAL_AVERAGE' +DIG_FIFO_FORCE_RECAL_AVERAGE__enumvalues = { + 0: 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 1: 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', +} +DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0 +DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 1 +DIG_FIFO_FORCE_RECAL_AVERAGE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_OUTPUT_PROCESSING_MODE' +DIG_FIFO_OUTPUT_PROCESSING_MODE__enumvalues = { + 0: 'DIG_FIFO_1_PIX_PER_CYCLE', + 1: 'DIG_FIFO_2_PIX_PER_CYCLE', +} +DIG_FIFO_1_PIX_PER_CYCLE = 0 +DIG_FIFO_2_PIX_PER_CYCLE = 1 +DIG_FIFO_OUTPUT_PROCESSING_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR' +DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { + 0: 'DIG_FIFO_NO_ERROR_OCCURRED', + 1: 'DIG_FIFO_UNDERFLOW_OCCURRED', + 2: 'DIG_FIFO_OVERFLOW_OCCURRED', +} +DIG_FIFO_NO_ERROR_OCCURRED = 0 +DIG_FIFO_UNDERFLOW_OCCURRED = 1 +DIG_FIFO_OVERFLOW_OCCURRED = 2 +DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_FIFO_READ_CLOCK_SRC' +DIG_FIFO_READ_CLOCK_SRC__enumvalues = { + 0: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 1: 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', +} +DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0 +DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 1 +DIG_FIFO_READ_CLOCK_SRC = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_INPUT_PIXEL_SEL' +DIG_INPUT_PIXEL_SEL__enumvalues = { + 0: 'DIG_ALL_PIXEL', + 1: 'DIG_EVEN_PIXEL_ONLY', + 2: 'DIG_ODD_PIXEL_ONLY', +} +DIG_ALL_PIXEL = 0 +DIG_EVEN_PIXEL_ONLY = 1 +DIG_ODD_PIXEL_ONLY = 2 +DIG_INPUT_PIXEL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_CNTL_LINK_SEL' +DIG_OUTPUT_CRC_CNTL_LINK_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_ON_LINK0', + 1: 'DIG_OUTPUT_CRC_ON_LINK1', +} +DIG_OUTPUT_CRC_ON_LINK0 = 0 +DIG_OUTPUT_CRC_ON_LINK1 = 1 +DIG_OUTPUT_CRC_CNTL_LINK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_OUTPUT_CRC_DATA_SEL' +DIG_OUTPUT_CRC_DATA_SEL__enumvalues = { + 0: 'DIG_OUTPUT_CRC_FOR_FULLFRAME', + 1: 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', + 2: 'DIG_OUTPUT_CRC_FOR_VBI', + 3: 'DIG_OUTPUT_CRC_FOR_AUDIO', +} +DIG_OUTPUT_CRC_FOR_FULLFRAME = 0 +DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 1 +DIG_OUTPUT_CRC_FOR_VBI = 2 +DIG_OUTPUT_CRC_FOR_AUDIO = 3 +DIG_OUTPUT_CRC_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_RANDOM_PATTERN_SEED_RAN_PAT' +DIG_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 1: 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', +} +DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0 +DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 1 +DIG_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_SL_PIXEL_GROUPING' +DIG_SL_PIXEL_GROUPING__enumvalues = { + 0: 'DIG_SINGLETON_PIXELS', + 1: 'DIG_PAIR_PIXELS', +} +DIG_SINGLETON_PIXELS = 0 +DIG_PAIR_PIXELS = 1 +DIG_SL_PIXEL_GROUPING = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN' +DIG_TEST_PATTERN_EXTERNAL_RESET_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 1: 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', +} +DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0 +DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 1 +DIG_TEST_PATTERN_EXTERNAL_RESET_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL' +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL__enumvalues = { + 0: 'DIG_10BIT_TEST_PATTERN', + 1: 'DIG_ALTERNATING_TEST_PATTERN', +} +DIG_10BIT_TEST_PATTERN = 0 +DIG_ALTERNATING_TEST_PATTERN = 1 +DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN' +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_TEST_PATTERN_NORMAL', + 1: 'DIG_TEST_PATTERN_RANDOM', +} +DIG_TEST_PATTERN_NORMAL = 0 +DIG_TEST_PATTERN_RANDOM = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET' +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET__enumvalues = { + 0: 'DIG_RANDOM_PATTERN_ENABLED', + 1: 'DIG_RANDOM_PATTERN_RESETED', +} +DIG_RANDOM_PATTERN_ENABLED = 0 +DIG_RANDOM_PATTERN_RESETED = 1 +DIG_TEST_PATTERN_RANDOM_PATTERN_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN' +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN__enumvalues = { + 0: 'DIG_IN_NORMAL_OPERATION', + 1: 'DIG_IN_DEBUG_MODE', +} +DIG_IN_NORMAL_OPERATION = 0 +DIG_IN_DEBUG_MODE = 1 +DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOLBY_VISION_ENABLE' +DOLBY_VISION_ENABLE__enumvalues = { + 0: 'DOLBY_VISION_DISABLED', + 1: 'DOLBY_VISION_ENABLED', +} +DOLBY_VISION_DISABLED = 0 +DOLBY_VISION_ENABLED = 1 +DOLBY_VISION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACP_SEND' +HDMI_ACP_SEND__enumvalues = { + 0: 'HDMI_ACP_NOT_SEND', + 1: 'HDMI_ACP_PKT_SEND', +} +HDMI_ACP_NOT_SEND = 0 +HDMI_ACP_PKT_SEND = 1 +HDMI_ACP_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_AUDIO_PRIORITY' +HDMI_ACR_AUDIO_PRIORITY__enumvalues = { + 0: 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 1: 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', +} +HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 +HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 +HDMI_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_CONT' +HDMI_ACR_CONT__enumvalues = { + 0: 'HDMI_ACR_CONT_DISABLE', + 1: 'HDMI_ACR_CONT_ENABLE', +} +HDMI_ACR_CONT_DISABLE = 0 +HDMI_ACR_CONT_ENABLE = 1 +HDMI_ACR_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_N_MULTIPLE' +HDMI_ACR_N_MULTIPLE__enumvalues = { + 0: 'HDMI_ACR_0_MULTIPLE_RESERVED', + 1: 'HDMI_ACR_1_MULTIPLE', + 2: 'HDMI_ACR_2_MULTIPLE', + 3: 'HDMI_ACR_3_MULTIPLE_RESERVED', + 4: 'HDMI_ACR_4_MULTIPLE', + 5: 'HDMI_ACR_5_MULTIPLE_RESERVED', + 6: 'HDMI_ACR_6_MULTIPLE_RESERVED', + 7: 'HDMI_ACR_7_MULTIPLE_RESERVED', +} +HDMI_ACR_0_MULTIPLE_RESERVED = 0 +HDMI_ACR_1_MULTIPLE = 1 +HDMI_ACR_2_MULTIPLE = 2 +HDMI_ACR_3_MULTIPLE_RESERVED = 3 +HDMI_ACR_4_MULTIPLE = 4 +HDMI_ACR_5_MULTIPLE_RESERVED = 5 +HDMI_ACR_6_MULTIPLE_RESERVED = 6 +HDMI_ACR_7_MULTIPLE_RESERVED = 7 +HDMI_ACR_N_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SELECT' +HDMI_ACR_SELECT__enumvalues = { + 0: 'HDMI_ACR_SELECT_HW', + 1: 'HDMI_ACR_SELECT_32K', + 2: 'HDMI_ACR_SELECT_44K', + 3: 'HDMI_ACR_SELECT_48K', +} +HDMI_ACR_SELECT_HW = 0 +HDMI_ACR_SELECT_32K = 1 +HDMI_ACR_SELECT_44K = 2 +HDMI_ACR_SELECT_48K = 3 +HDMI_ACR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SEND' +HDMI_ACR_SEND__enumvalues = { + 0: 'HDMI_ACR_NOT_SEND', + 1: 'HDMI_ACR_PKT_SEND', +} +HDMI_ACR_NOT_SEND = 0 +HDMI_ACR_PKT_SEND = 1 +HDMI_ACR_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ACR_SOURCE' +HDMI_ACR_SOURCE__enumvalues = { + 0: 'HDMI_ACR_SOURCE_HW', + 1: 'HDMI_ACR_SOURCE_SW', +} +HDMI_ACR_SOURCE_HW = 0 +HDMI_ACR_SOURCE_SW = 1 +HDMI_ACR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_DELAY_EN' +HDMI_AUDIO_DELAY_EN__enumvalues = { + 0: 'HDMI_AUDIO_DELAY_DISABLE', + 1: 'HDMI_AUDIO_DELAY_58CLK', + 2: 'HDMI_AUDIO_DELAY_56CLK', + 3: 'HDMI_AUDIO_DELAY_RESERVED', +} +HDMI_AUDIO_DELAY_DISABLE = 0 +HDMI_AUDIO_DELAY_58CLK = 1 +HDMI_AUDIO_DELAY_56CLK = 2 +HDMI_AUDIO_DELAY_RESERVED = 3 +HDMI_AUDIO_DELAY_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_CONT' +HDMI_AUDIO_INFO_CONT__enumvalues = { + 0: 'HDMI_AUDIO_INFO_CONT_DISABLE', + 1: 'HDMI_AUDIO_INFO_CONT_ENABLE', +} +HDMI_AUDIO_INFO_CONT_DISABLE = 0 +HDMI_AUDIO_INFO_CONT_ENABLE = 1 +HDMI_AUDIO_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_AUDIO_INFO_SEND' +HDMI_AUDIO_INFO_SEND__enumvalues = { + 0: 'HDMI_AUDIO_INFO_NOT_SEND', + 1: 'HDMI_AUDIO_INFO_PKT_SEND', +} +HDMI_AUDIO_INFO_NOT_SEND = 0 +HDMI_AUDIO_INFO_PKT_SEND = 1 +HDMI_AUDIO_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_CLOCK_CHANNEL_RATE' +HDMI_CLOCK_CHANNEL_RATE__enumvalues = { + 0: 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 1: 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', +} +HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0 +HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 1 +HDMI_CLOCK_CHANNEL_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DATA_SCRAMBLE_EN' +HDMI_DATA_SCRAMBLE_EN__enumvalues = { + 0: 'HDMI_DATA_SCRAMBLE_DISABLE', + 1: 'HDMI_DATA_SCRAMBLE_ENABLE', +} +HDMI_DATA_SCRAMBLE_DISABLE = 0 +HDMI_DATA_SCRAMBLE_ENABLE = 1 +HDMI_DATA_SCRAMBLE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEEP_COLOR_DEPTH' +HDMI_DEEP_COLOR_DEPTH__enumvalues = { + 0: 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 1: 'HDMI_DEEP_COLOR_DEPTH_30BPP', + 2: 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 3: 'HDMI_DEEP_COLOR_DEPTH_48BPP', +} +HDMI_DEEP_COLOR_DEPTH_24BPP = 0 +HDMI_DEEP_COLOR_DEPTH_30BPP = 1 +HDMI_DEEP_COLOR_DEPTH_36BPP = 2 +HDMI_DEEP_COLOR_DEPTH_48BPP = 3 +HDMI_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_DEFAULT_PAHSE' +HDMI_DEFAULT_PAHSE__enumvalues = { + 0: 'HDMI_DEFAULT_PHASE_IS_0', + 1: 'HDMI_DEFAULT_PHASE_IS_1', +} +HDMI_DEFAULT_PHASE_IS_0 = 0 +HDMI_DEFAULT_PHASE_IS_1 = 1 +HDMI_DEFAULT_PAHSE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_ACK' +HDMI_ERROR_ACK__enumvalues = { + 0: 'HDMI_ERROR_ACK_INT', + 1: 'HDMI_ERROR_NOT_ACK', +} +HDMI_ERROR_ACK_INT = 0 +HDMI_ERROR_NOT_ACK = 1 +HDMI_ERROR_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ERROR_MASK' +HDMI_ERROR_MASK__enumvalues = { + 0: 'HDMI_ERROR_MASK_INT', + 1: 'HDMI_ERROR_NOT_MASK', +} +HDMI_ERROR_MASK_INT = 0 +HDMI_ERROR_NOT_MASK = 1 +HDMI_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE' +HDMI_GC_AVMUTE__enumvalues = { + 0: 'HDMI_GC_AVMUTE_SET', + 1: 'HDMI_GC_AVMUTE_UNSET', +} +HDMI_GC_AVMUTE_SET = 0 +HDMI_GC_AVMUTE_UNSET = 1 +HDMI_GC_AVMUTE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_AVMUTE_CONT' +HDMI_GC_AVMUTE_CONT__enumvalues = { + 0: 'HDMI_GC_AVMUTE_CONT_DISABLE', + 1: 'HDMI_GC_AVMUTE_CONT_ENABLE', +} +HDMI_GC_AVMUTE_CONT_DISABLE = 0 +HDMI_GC_AVMUTE_CONT_ENABLE = 1 +HDMI_GC_AVMUTE_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_CONT' +HDMI_GC_CONT__enumvalues = { + 0: 'HDMI_GC_CONT_DISABLE', + 1: 'HDMI_GC_CONT_ENABLE', +} +HDMI_GC_CONT_DISABLE = 0 +HDMI_GC_CONT_ENABLE = 1 +HDMI_GC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GC_SEND' +HDMI_GC_SEND__enumvalues = { + 0: 'HDMI_GC_NOT_SEND', + 1: 'HDMI_GC_PKT_SEND', +} +HDMI_GC_NOT_SEND = 0 +HDMI_GC_PKT_SEND = 1 +HDMI_GC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC_CONT' +HDMI_GENERIC_CONT__enumvalues = { + 0: 'HDMI_GENERIC_CONT_DISABLE', + 1: 'HDMI_GENERIC_CONT_ENABLE', +} +HDMI_GENERIC_CONT_DISABLE = 0 +HDMI_GENERIC_CONT_ENABLE = 1 +HDMI_GENERIC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_GENERIC_SEND' +HDMI_GENERIC_SEND__enumvalues = { + 0: 'HDMI_GENERIC_NOT_SEND', + 1: 'HDMI_GENERIC_PKT_SEND', +} +HDMI_GENERIC_NOT_SEND = 0 +HDMI_GENERIC_PKT_SEND = 1 +HDMI_GENERIC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_CONT' +HDMI_ISRC_CONT__enumvalues = { + 0: 'HDMI_ISRC_CONT_DISABLE', + 1: 'HDMI_ISRC_CONT_ENABLE', +} +HDMI_ISRC_CONT_DISABLE = 0 +HDMI_ISRC_CONT_ENABLE = 1 +HDMI_ISRC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_ISRC_SEND' +HDMI_ISRC_SEND__enumvalues = { + 0: 'HDMI_ISRC_NOT_SEND', + 1: 'HDMI_ISRC_PKT_SEND', +} +HDMI_ISRC_NOT_SEND = 0 +HDMI_ISRC_PKT_SEND = 1 +HDMI_ISRC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_KEEPOUT_MODE' +HDMI_KEEPOUT_MODE__enumvalues = { + 0: 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 1: 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', +} +HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0 +HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 1 +HDMI_KEEPOUT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_METADATA_ENABLE' +HDMI_METADATA_ENABLE__enumvalues = { + 0: 'HDMI_METADATA_NOT_SEND', + 1: 'HDMI_METADATA_PKT_SEND', +} +HDMI_METADATA_NOT_SEND = 0 +HDMI_METADATA_PKT_SEND = 1 +HDMI_METADATA_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_CONT' +HDMI_MPEG_INFO_CONT__enumvalues = { + 0: 'HDMI_MPEG_INFO_CONT_DISABLE', + 1: 'HDMI_MPEG_INFO_CONT_ENABLE', +} +HDMI_MPEG_INFO_CONT_DISABLE = 0 +HDMI_MPEG_INFO_CONT_ENABLE = 1 +HDMI_MPEG_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_MPEG_INFO_SEND' +HDMI_MPEG_INFO_SEND__enumvalues = { + 0: 'HDMI_MPEG_INFO_NOT_SEND', + 1: 'HDMI_MPEG_INFO_PKT_SEND', +} +HDMI_MPEG_INFO_NOT_SEND = 0 +HDMI_MPEG_INFO_PKT_SEND = 1 +HDMI_MPEG_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NO_EXTRA_NULL_PACKET_FILLED' +HDMI_NO_EXTRA_NULL_PACKET_FILLED__enumvalues = { + 0: 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', + 1: 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', +} +HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0 +HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 1 +HDMI_NO_EXTRA_NULL_PACKET_FILLED = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_NULL_SEND' +HDMI_NULL_SEND__enumvalues = { + 0: 'HDMI_NULL_NOT_SEND', + 1: 'HDMI_NULL_PKT_SEND', +} +HDMI_NULL_NOT_SEND = 0 +HDMI_NULL_PKT_SEND = 1 +HDMI_NULL_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKET_GEN_VERSION' +HDMI_PACKET_GEN_VERSION__enumvalues = { + 0: 'HDMI_PACKET_GEN_VERSION_OLD', + 1: 'HDMI_PACKET_GEN_VERSION_NEW', +} +HDMI_PACKET_GEN_VERSION_OLD = 0 +HDMI_PACKET_GEN_VERSION_NEW = 1 +HDMI_PACKET_GEN_VERSION = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKET_LINE_REFERENCE' +HDMI_PACKET_LINE_REFERENCE__enumvalues = { + 0: 'HDMI_PKT_LINE_REF_VSYNC', + 1: 'HDMI_PKT_LINE_REF_OTGSOF', +} +HDMI_PKT_LINE_REF_VSYNC = 0 +HDMI_PKT_LINE_REF_OTGSOF = 1 +HDMI_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_PACKING_PHASE_OVERRIDE' +HDMI_PACKING_PHASE_OVERRIDE__enumvalues = { + 0: 'HDMI_PACKING_PHASE_SET_BY_HW', + 1: 'HDMI_PACKING_PHASE_SET_BY_SW', +} +HDMI_PACKING_PHASE_SET_BY_HW = 0 +HDMI_PACKING_PHASE_SET_BY_SW = 1 +HDMI_PACKING_PHASE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT' +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT__enumvalues = { + 0: 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 1: 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', +} +LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0 +LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 1 +LVTMA_RANDOM_PATTERN_SEED_RAN_PAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_COLOR_FORMAT' +TMDS_COLOR_FORMAT__enumvalues = { + 0: 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 1: 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 2: 'TMDS_COLOR_FORMAT_DUAL30BPP', + 3: 'TMDS_COLOR_FORMAT_RESERVED', +} +TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0 +TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 1 +TMDS_COLOR_FORMAT_DUAL30BPP = 2 +TMDS_COLOR_FORMAT_RESERVED = 3 +TMDS_COLOR_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_INVERT' +TMDS_CTL0_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL0_DATA_NORMAL', + 1: 'TMDS_CTL0_DATA_INVERT_EN', +} +TMDS_CTL0_DATA_NORMAL = 0 +TMDS_CTL0_DATA_INVERT_EN = 1 +TMDS_CTL0_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_MODULATION' +TMDS_CTL0_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL0_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL0_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL0_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL0_DATA_MODULATION_BIT2', +} +TMDS_CTL0_DATA_MODULATION_DISABLE = 0 +TMDS_CTL0_DATA_MODULATION_BIT0 = 1 +TMDS_CTL0_DATA_MODULATION_BIT1 = 2 +TMDS_CTL0_DATA_MODULATION_BIT2 = 3 +TMDS_CTL0_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_DATA_SEL' +TMDS_CTL0_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL0_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL0_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL0_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL0_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 7: 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', +} +TMDS_CTL0_DATA_SEL0_RESERVED = 0 +TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL0_DATA_SEL2_VSYNC = 2 +TMDS_CTL0_DATA_SEL3_RESERVED = 3 +TMDS_CTL0_DATA_SEL4_HSYNC = 4 +TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 6 +TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 7 +TMDS_CTL0_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL0_PATTERN_OUT_EN' +TMDS_CTL0_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL0_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL0_PATTERN_OUT_ENABLE', +} +TMDS_CTL0_PATTERN_OUT_DISABLE = 0 +TMDS_CTL0_PATTERN_OUT_ENABLE = 1 +TMDS_CTL0_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_INVERT' +TMDS_CTL1_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL1_DATA_NORMAL', + 1: 'TMDS_CTL1_DATA_INVERT_EN', +} +TMDS_CTL1_DATA_NORMAL = 0 +TMDS_CTL1_DATA_INVERT_EN = 1 +TMDS_CTL1_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_MODULATION' +TMDS_CTL1_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL1_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL1_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL1_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL1_DATA_MODULATION_BIT2', +} +TMDS_CTL1_DATA_MODULATION_DISABLE = 0 +TMDS_CTL1_DATA_MODULATION_BIT0 = 1 +TMDS_CTL1_DATA_MODULATION_BIT1 = 2 +TMDS_CTL1_DATA_MODULATION_BIT2 = 3 +TMDS_CTL1_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_DATA_SEL' +TMDS_CTL1_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL1_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL1_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL1_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL1_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL1_DATA_SEL0_RESERVED = 0 +TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL1_DATA_SEL2_VSYNC = 2 +TMDS_CTL1_DATA_SEL3_RESERVED = 3 +TMDS_CTL1_DATA_SEL4_HSYNC = 4 +TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL1_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL1_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL1_PATTERN_OUT_EN' +TMDS_CTL1_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL1_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL1_PATTERN_OUT_ENABLE', +} +TMDS_CTL1_PATTERN_OUT_DISABLE = 0 +TMDS_CTL1_PATTERN_OUT_ENABLE = 1 +TMDS_CTL1_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_INVERT' +TMDS_CTL2_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL2_DATA_NORMAL', + 1: 'TMDS_CTL2_DATA_INVERT_EN', +} +TMDS_CTL2_DATA_NORMAL = 0 +TMDS_CTL2_DATA_INVERT_EN = 1 +TMDS_CTL2_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_MODULATION' +TMDS_CTL2_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL2_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL2_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL2_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL2_DATA_MODULATION_BIT2', +} +TMDS_CTL2_DATA_MODULATION_DISABLE = 0 +TMDS_CTL2_DATA_MODULATION_BIT0 = 1 +TMDS_CTL2_DATA_MODULATION_BIT1 = 2 +TMDS_CTL2_DATA_MODULATION_BIT2 = 3 +TMDS_CTL2_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_DATA_SEL' +TMDS_CTL2_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL2_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL2_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL2_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL2_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL2_DATA_SEL0_RESERVED = 0 +TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL2_DATA_SEL2_VSYNC = 2 +TMDS_CTL2_DATA_SEL3_RESERVED = 3 +TMDS_CTL2_DATA_SEL4_HSYNC = 4 +TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL2_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL2_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL2_PATTERN_OUT_EN' +TMDS_CTL2_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL2_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL2_PATTERN_OUT_ENABLE', +} +TMDS_CTL2_PATTERN_OUT_DISABLE = 0 +TMDS_CTL2_PATTERN_OUT_ENABLE = 1 +TMDS_CTL2_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_INVERT' +TMDS_CTL3_DATA_INVERT__enumvalues = { + 0: 'TMDS_CTL3_DATA_NORMAL', + 1: 'TMDS_CTL3_DATA_INVERT_EN', +} +TMDS_CTL3_DATA_NORMAL = 0 +TMDS_CTL3_DATA_INVERT_EN = 1 +TMDS_CTL3_DATA_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_MODULATION' +TMDS_CTL3_DATA_MODULATION__enumvalues = { + 0: 'TMDS_CTL3_DATA_MODULATION_DISABLE', + 1: 'TMDS_CTL3_DATA_MODULATION_BIT0', + 2: 'TMDS_CTL3_DATA_MODULATION_BIT1', + 3: 'TMDS_CTL3_DATA_MODULATION_BIT2', +} +TMDS_CTL3_DATA_MODULATION_DISABLE = 0 +TMDS_CTL3_DATA_MODULATION_BIT0 = 1 +TMDS_CTL3_DATA_MODULATION_BIT1 = 2 +TMDS_CTL3_DATA_MODULATION_BIT2 = 3 +TMDS_CTL3_DATA_MODULATION = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_DATA_SEL' +TMDS_CTL3_DATA_SEL__enumvalues = { + 0: 'TMDS_CTL3_DATA_SEL0_RESERVED', + 1: 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', + 2: 'TMDS_CTL3_DATA_SEL2_VSYNC', + 3: 'TMDS_CTL3_DATA_SEL3_RESERVED', + 4: 'TMDS_CTL3_DATA_SEL4_HSYNC', + 5: 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 6: 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 7: 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', +} +TMDS_CTL3_DATA_SEL0_RESERVED = 0 +TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 1 +TMDS_CTL3_DATA_SEL2_VSYNC = 2 +TMDS_CTL3_DATA_SEL3_RESERVED = 3 +TMDS_CTL3_DATA_SEL4_HSYNC = 4 +TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 5 +TMDS_CTL3_DATA_SEL8_BLANK_TIME = 6 +TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 7 +TMDS_CTL3_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_CTL3_PATTERN_OUT_EN' +TMDS_CTL3_PATTERN_OUT_EN__enumvalues = { + 0: 'TMDS_CTL3_PATTERN_OUT_DISABLE', + 1: 'TMDS_CTL3_PATTERN_OUT_ENABLE', +} +TMDS_CTL3_PATTERN_OUT_DISABLE = 0 +TMDS_CTL3_PATTERN_OUT_ENABLE = 1 +TMDS_CTL3_PATTERN_OUT_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL' +TMDS_DATA_SYNCHRONIZATION_DSINTSEL__enumvalues = { + 0: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 1: 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', +} +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 1 +TMDS_DATA_SYNCHRONIZATION_DSINTSEL = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_PIXEL_ENCODING' +TMDS_PIXEL_ENCODING__enumvalues = { + 0: 'TMDS_PIXEL_ENCODING_444_OR_420', + 1: 'TMDS_PIXEL_ENCODING_422', +} +TMDS_PIXEL_ENCODING_444_OR_420 = 0 +TMDS_PIXEL_ENCODING_422 = 1 +TMDS_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTA_CNTLA' +TMDS_REG_TEST_OUTPUTA_CNTLA__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 1: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 2: 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 3: 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', +} +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 1 +TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 2 +TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 3 +TMDS_REG_TEST_OUTPUTA_CNTLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_REG_TEST_OUTPUTB_CNTLB' +TMDS_REG_TEST_OUTPUTB_CNTLB__enumvalues = { + 0: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 1: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 2: 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', + 3: 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', +} +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 1 +TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 2 +TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 3 +TMDS_REG_TEST_OUTPUTB_CNTLB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_STEREOSYNC_CTL_SEL_REG' +TMDS_STEREOSYNC_CTL_SEL_REG__enumvalues = { + 0: 'TMDS_STEREOSYNC_CTL0', + 1: 'TMDS_STEREOSYNC_CTL1', + 2: 'TMDS_STEREOSYNC_CTL2', + 3: 'TMDS_STEREOSYNC_CTL3', +} +TMDS_STEREOSYNC_CTL0 = 0 +TMDS_STEREOSYNC_CTL1 = 1 +TMDS_STEREOSYNC_CTL2 = 2 +TMDS_STEREOSYNC_CTL3 = 3 +TMDS_STEREOSYNC_CTL_SEL_REG = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_SYNC_PHASE' +TMDS_SYNC_PHASE__enumvalues = { + 0: 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', + 1: 'TMDS_SYNC_PHASE_ON_FRAME_START', +} +TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0 +TMDS_SYNC_PHASE_ON_FRAME_START = 1 +TMDS_SYNC_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB' +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB__enumvalues = { + 0: 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 1: 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', +} +TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0 +TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 1 +TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA' +TMDS_TRANSMITTER_CONTROL_IDSCKSELA__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELA = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB' +TMDS_TRANSMITTER_CONTROL_IDSCKSELB__enumvalues = { + 0: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 1: 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', +} +TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0 +TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 1 +TMDS_TRANSMITTER_CONTROL_IDSCKSELB = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN' +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 1: 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', +} +TMDS_TRANSMITTER_PLLSEL_BY_HW = 0 +TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 1 +TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 1: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 2: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 3: 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', +} +TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 1 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 2 +TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 3 +TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN' +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 1: 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', +} +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0 +TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 1 +TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK' +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 1: 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', +} +TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0 +TMDS_TRANSMITTER_PLL_RST_ON_HPD = 1 +TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 1: 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0 +TMDS_TRANSMITTER_TDCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS' +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS__enumvalues = { + 0: 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', + 1: 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', +} +TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0 +TMDS_TRANSMITTER_TMCLK_FROM_PADS = 1 +TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK' +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK__enumvalues = { + 0: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 1: 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', +} +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0 +TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 1 +TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_ARB_PRIORITY' +DP_AUX_ARB_CONTROL_ARB_PRIORITY__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 1: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 2: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 3: 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', +} +DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 1 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 2 +DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 3 +DP_AUX_ARB_CONTROL_ARB_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG' +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 1: 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', +} +DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0 +DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 1 +DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ' +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ__enumvalues = { + 0: 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 1: 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', +} +DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0 +DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 1 +DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ARB_STATUS' +DP_AUX_ARB_STATUS__enumvalues = { + 0: 'DP_AUX_IDLE', + 1: 'DP_AUX_IN_USE_LS', + 2: 'DP_AUX_IN_USE_GTC', + 3: 'DP_AUX_IN_USE_SW', + 4: 'DP_AUX_IN_USE_PHYWAKE', +} +DP_AUX_IDLE = 0 +DP_AUX_IN_USE_LS = 1 +DP_AUX_IN_USE_GTC = 2 +DP_AUX_IN_USE_SW = 3 +DP_AUX_IN_USE_PHYWAKE = 4 +DP_AUX_ARB_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_HPD_SEL' +DP_AUX_CONTROL_HPD_SEL__enumvalues = { + 0: 'DP_AUX_CONTROL_HPD1_SELECTED', + 1: 'DP_AUX_CONTROL_HPD2_SELECTED', + 2: 'DP_AUX_CONTROL_HPD3_SELECTED', + 3: 'DP_AUX_CONTROL_HPD4_SELECTED', + 4: 'DP_AUX_CONTROL_HPD5_SELECTED', + 5: 'DP_AUX_CONTROL_NO_HPD_SELECTED', +} +DP_AUX_CONTROL_HPD1_SELECTED = 0 +DP_AUX_CONTROL_HPD2_SELECTED = 1 +DP_AUX_CONTROL_HPD3_SELECTED = 2 +DP_AUX_CONTROL_HPD4_SELECTED = 3 +DP_AUX_CONTROL_HPD5_SELECTED = 4 +DP_AUX_CONTROL_NO_HPD_SELECTED = 5 +DP_AUX_CONTROL_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_CONTROL_TEST_MODE' +DP_AUX_CONTROL_TEST_MODE__enumvalues = { + 0: 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 1: 'DP_AUX_CONTROL_TEST_MODE_ENABLE', +} +DP_AUX_CONTROL_TEST_MODE_DISABLE = 0 +DP_AUX_CONTROL_TEST_MODE_ENABLE = 1 +DP_AUX_CONTROL_TEST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DEFINITE_ERR_REACHED_ACK' +DP_AUX_DEFINITE_ERR_REACHED_ACK__enumvalues = { + 0: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', + 1: 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', +} +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0 +ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 1 +DP_AUX_DEFINITE_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP' +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 1: 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', +} +DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0 +DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 1 +DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 1: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 2: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 3: 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', +} +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 1 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 2 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 3 +DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN' +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 1: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 2: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 3: 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', +} +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 1 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 2 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 3 +DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW' +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW' +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__enumvalues = { + 0: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 1: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 2: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 3: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 4: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 5: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 6: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 7: 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', +} +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 1 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 2 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 3 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 4 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 5 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 6 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 7 +DP_AUX_DPHY_RX_CONTROL_START_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD' +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__enumvalues = { + 0: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 1: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 2: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 3: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 4: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 5: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 6: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 7: 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', +} +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 1 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 2 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 3 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 4 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 5 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 6 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 7 +DP_AUX_DPHY_RX_DETECTION_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY' +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__enumvalues = { + 0: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 1: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 2: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 3: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 4: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 5: 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', +} +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 1 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 2 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 3 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 4 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 5 +DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE' +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 2: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 3: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 2 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 3 +DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL' +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__enumvalues = { + 0: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 1: 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', +} +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 1 +DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_ERR_OCCURRED_ACK' +DP_AUX_ERR_OCCURRED_ACK__enumvalues = { + 0: 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 1: 'DP_AUX_ERR_OCCURRED__ACK', +} +DP_AUX_ERR_OCCURRED__NOT_ACK = 0 +DP_AUX_ERR_OCCURRED__ACK = 1 +DP_AUX_ERR_OCCURRED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ' +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 1: 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', +} +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 1 +DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW' +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 1: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 2: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 3: 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', +} +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 1 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 2 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 3 +DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT' +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 1: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 2: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 3: 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', +} +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 1 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 2 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 3 +DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN' +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__enumvalues = { + 0: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 1: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 2: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 3: 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', +} +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 1 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 2 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 3 +DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_INT_ACK' +DP_AUX_INT_ACK__enumvalues = { + 0: 'DP_AUX_INT__NOT_ACK', + 1: 'DP_AUX_INT__ACK', +} +DP_AUX_INT__NOT_ACK = 0 +DP_AUX_INT__ACK = 1 +DP_AUX_INT_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_LS_UPDATE_ACK' +DP_AUX_LS_UPDATE_ACK__enumvalues = { + 0: 'DP_AUX_INT_LS_UPDATE_NOT_ACK', + 1: 'DP_AUX_INT_LS_UPDATE_ACK', +} +DP_AUX_INT_LS_UPDATE_NOT_ACK = 0 +DP_AUX_INT_LS_UPDATE_ACK = 1 +DP_AUX_LS_UPDATE_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_PHY_WAKE_PRIORITY' +DP_AUX_PHY_WAKE_PRIORITY__enumvalues = { + 0: 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', + 1: 'DP_AUX_PHY_WAKE_LOW_PRIORITY', +} +DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0 +DP_AUX_PHY_WAKE_LOW_PRIORITY = 1 +DP_AUX_PHY_WAKE_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_POTENTIAL_ERR_REACHED_ACK' +DP_AUX_POTENTIAL_ERR_REACHED_ACK__enumvalues = { + 0: 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', + 1: 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', +} +DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0 +DP_AUX_POTENTIAL_ERR_REACHED__ACK = 1 +DP_AUX_POTENTIAL_ERR_REACHED_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET' +DP_AUX_RESET__enumvalues = { + 0: 'DP_AUX_RESET_DEASSERTED', + 1: 'DP_AUX_RESET_ASSERTED', +} +DP_AUX_RESET_DEASSERTED = 0 +DP_AUX_RESET_ASSERTED = 1 +DP_AUX_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RESET_DONE' +DP_AUX_RESET_DONE__enumvalues = { + 0: 'DP_AUX_RESET_SEQUENCE_NOT_DONE', + 1: 'DP_AUX_RESET_SEQUENCE_DONE', +} +DP_AUX_RESET_SEQUENCE_NOT_DONE = 0 +DP_AUX_RESET_SEQUENCE_DONE = 1 +DP_AUX_RESET_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_RX_TIMEOUT_LEN_MUL' +DP_AUX_RX_TIMEOUT_LEN_MUL__enumvalues = { + 0: 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', + 1: 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', + 2: 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', + 3: 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', +} +DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0 +DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 1 +DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 2 +DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 3 +DP_AUX_RX_TIMEOUT_LEN_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_LS_READ_TRIG' +DP_AUX_SW_CONTROL_LS_READ_TRIG__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 1: 'DP_AUX_SW_CONTROL_LS_READ__TRIG', +} +DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0 +DP_AUX_SW_CONTROL_LS_READ__TRIG = 1 +DP_AUX_SW_CONTROL_LS_READ_TRIG = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_SW_CONTROL_SW_GO' +DP_AUX_SW_CONTROL_SW_GO__enumvalues = { + 0: 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 1: 'DP_AUX_SW_CONTROL_SW__GO', +} +DP_AUX_SW_CONTROL_SW__NOT_GO = 0 +DP_AUX_SW_CONTROL_SW__GO = 1 +DP_AUX_SW_CONTROL_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DP_AUX_TX_PRECHARGE_LEN_MUL' +DP_AUX_TX_PRECHARGE_LEN_MUL__enumvalues = { + 0: 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', + 1: 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', + 2: 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', + 3: 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', +} +DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0 +DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 1 +DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 2 +DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 3 +DP_AUX_TX_PRECHARGE_LEN_MUL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ACK' +DOUT_I2C_ACK__enumvalues = { + 0: 'DOUT_I2C_NO_ACK', + 1: 'DOUT_I2C_ACK_TO_CLEAN', +} +DOUT_I2C_NO_ACK = 0 +DOUT_I2C_ACK_TO_CLEAN = 1 +DOUT_I2C_ACK = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_ABORT_XFER' +DOUT_I2C_ARBITRATION_ABORT_XFER__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 1: 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', +} +DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0 +DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 1 +DOUT_I2C_ARBITRATION_ABORT_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG' +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 1: 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', +} +DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0 +DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 1 +DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO' +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 1: 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', +} +DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0 +DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 1 +DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_SW_PRIORITY' +DOUT_I2C_ARBITRATION_SW_PRIORITY__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 1: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 2: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 3: 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', +} +DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0 +DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 1 +DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 2 +DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 3 +DOUT_I2C_ARBITRATION_SW_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ' +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ__enumvalues = { + 0: 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 1: 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', +} +DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0 +DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 1 +DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DBG_REF_SEL' +DOUT_I2C_CONTROL_DBG_REF_SEL__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NORMAL_DEBUG', + 1: 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', +} +DOUT_I2C_CONTROL_NORMAL_DEBUG = 0 +DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 1 +DOUT_I2C_CONTROL_DBG_REF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_DDC_SELECT' +DOUT_I2C_CONTROL_DDC_SELECT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_SELECT_DDC1', + 1: 'DOUT_I2C_CONTROL_SELECT_DDC2', + 2: 'DOUT_I2C_CONTROL_SELECT_DDC3', + 3: 'DOUT_I2C_CONTROL_SELECT_DDC4', + 4: 'DOUT_I2C_CONTROL_SELECT_DDC5', + 5: 'DOUT_I2C_CONTROL_SELECT_DDCVGA', +} +DOUT_I2C_CONTROL_SELECT_DDC1 = 0 +DOUT_I2C_CONTROL_SELECT_DDC2 = 1 +DOUT_I2C_CONTROL_SELECT_DDC3 = 2 +DOUT_I2C_CONTROL_SELECT_DDC4 = 3 +DOUT_I2C_CONTROL_SELECT_DDC5 = 4 +DOUT_I2C_CONTROL_SELECT_DDCVGA = 5 +DOUT_I2C_CONTROL_DDC_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_GO' +DOUT_I2C_CONTROL_GO__enumvalues = { + 0: 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 1: 'DOUT_I2C_CONTROL_START_TRANSFER', +} +DOUT_I2C_CONTROL_STOP_TRANSFER = 0 +DOUT_I2C_CONTROL_START_TRANSFER = 1 +DOUT_I2C_CONTROL_GO = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET' +DOUT_I2C_CONTROL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 1: 'DOUT_I2C_CONTROL__SEND_RESET', +} +DOUT_I2C_CONTROL__NOT_SEND_RESET = 0 +DOUT_I2C_CONTROL__SEND_RESET = 1 +DOUT_I2C_CONTROL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH' +DOUT_I2C_CONTROL_SEND_RESET_LENGTH__enumvalues = { + 0: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', + 1: 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', +} +DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0 +DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 1 +DOUT_I2C_CONTROL_SEND_RESET_LENGTH = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SOFT_RESET' +DOUT_I2C_CONTROL_SOFT_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 1: 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', +} +DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0 +DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 1 +DOUT_I2C_CONTROL_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_SW_STATUS_RESET' +DOUT_I2C_CONTROL_SW_STATUS_RESET__enumvalues = { + 0: 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 1: 'DOUT_I2C_CONTROL_RESET_SW_STATUS', +} +DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0 +DOUT_I2C_CONTROL_RESET_SW_STATUS = 1 +DOUT_I2C_CONTROL_SW_STATUS_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_CONTROL_TRANSACTION_COUNT' +DOUT_I2C_CONTROL_TRANSACTION_COUNT__enumvalues = { + 0: 'DOUT_I2C_CONTROL_TRANS0', + 1: 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 2: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 3: 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', +} +DOUT_I2C_CONTROL_TRANS0 = 0 +DOUT_I2C_CONTROL_TRANS0_TRANS1 = 1 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 2 +DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 3 +DOUT_I2C_CONTROL_TRANSACTION_COUNT = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DATA_INDEX_WRITE' +DOUT_I2C_DATA_INDEX_WRITE__enumvalues = { + 0: 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 1: 'DOUT_I2C_DATA__INDEX_WRITE', +} +DOUT_I2C_DATA__NOT_INDEX_WRITE = 0 +DOUT_I2C_DATA__INDEX_WRITE = 1 +DOUT_I2C_DATA_INDEX_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN' +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', +} +DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 1 +DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 1: 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0 +DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL' +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 1: 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', +} +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 1 +DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE' +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE__enumvalues = { + 0: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 1: 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', +} +DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0 +DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 1 +DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_DDC_SPEED_THRESHOLD' +DOUT_I2C_DDC_SPEED_THRESHOLD__enumvalues = { + 0: 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 1: 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 2: 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 3: 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', +} +DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0 +DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 1 +DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 2 +DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 3 +DOUT_I2C_DDC_SPEED_THRESHOLD = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET' +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET__enumvalues = { + 0: 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 1: 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', +} +DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0 +DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 1 +DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE' +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__enumvalues = { + 0: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 1: 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', +} +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 1 +DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DOUT_I2C_TRANSACTION_STOP_ON_NACK' +DOUT_I2C_TRANSACTION_STOP_ON_NACK__enumvalues = { + 0: 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 1: 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', +} +DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0 +DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 1 +DOUT_I2C_TRANSACTION_STOP_ON_NACK = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_GATING_EN' +CLOCK_GATING_EN__enumvalues = { + 0: 'CLOCK_GATING_ENABLE', + 1: 'CLOCK_GATING_DISABLE', +} +CLOCK_GATING_ENABLE = 0 +CLOCK_GATING_DISABLE = 1 +CLOCK_GATING_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DAC_MUX_SELECT' +DAC_MUX_SELECT__enumvalues = { + 0: 'DAC_MUX_SELECT_DACA', + 1: 'DAC_MUX_SELECT_DACB', +} +DAC_MUX_SELECT_DACA = 0 +DAC_MUX_SELECT_DACB = 1 +DAC_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_DIS_CTRL' +DIOMEM_PWR_DIS_CTRL__enumvalues = { + 0: 'DIOMEM_ENABLE_MEM_PWR_CTRL', + 1: 'DIOMEM_DISABLE_MEM_PWR_CTRL', +} +DIOMEM_ENABLE_MEM_PWR_CTRL = 0 +DIOMEM_DISABLE_MEM_PWR_CTRL = 1 +DIOMEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_FORCE_CTRL' +DIOMEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'DIOMEM_NO_FORCE_REQUEST', + 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', +} +DIOMEM_NO_FORCE_REQUEST = 0 +DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 2 +DIOMEM_FORCE_SHUT_DOWN_REQUEST = 3 +DIOMEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_FORCE_CTRL2' +DIOMEM_PWR_FORCE_CTRL2__enumvalues = { + 0: 'DIOMEM_NO_FORCE_REQ', + 1: 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', +} +DIOMEM_NO_FORCE_REQ = 0 +DIOMEM_FORCE_LIGHT_SLEEP_REQ = 1 +DIOMEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_SEL_CTRL' +DIOMEM_PWR_SEL_CTRL__enumvalues = { + 0: 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', + 1: 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', + 2: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', +} +DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0 +DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 1 +DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 2 +DIOMEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DIOMEM_PWR_SEL_CTRL2' +DIOMEM_PWR_SEL_CTRL2__enumvalues = { + 0: 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', + 1: 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', +} +DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0 +DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 1 +DIOMEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_DBG_BLOCK_SEL' +DIO_DBG_BLOCK_SEL__enumvalues = { + 0: 'DIO_DBG_BLOCK_SEL_DIO', + 11: 'DIO_DBG_BLOCK_SEL_DIGFE_A', + 12: 'DIO_DBG_BLOCK_SEL_DIGFE_B', + 13: 'DIO_DBG_BLOCK_SEL_DIGFE_C', + 14: 'DIO_DBG_BLOCK_SEL_DIGFE_D', + 15: 'DIO_DBG_BLOCK_SEL_DIGFE_E', + 18: 'DIO_DBG_BLOCK_SEL_DIGA', + 19: 'DIO_DBG_BLOCK_SEL_DIGB', + 20: 'DIO_DBG_BLOCK_SEL_DIGC', + 21: 'DIO_DBG_BLOCK_SEL_DIGD', + 22: 'DIO_DBG_BLOCK_SEL_DIGE', + 25: 'DIO_DBG_BLOCK_SEL_DPFE_A', + 26: 'DIO_DBG_BLOCK_SEL_DPFE_B', + 27: 'DIO_DBG_BLOCK_SEL_DPFE_C', + 28: 'DIO_DBG_BLOCK_SEL_DPFE_D', + 29: 'DIO_DBG_BLOCK_SEL_DPFE_E', + 32: 'DIO_DBG_BLOCK_SEL_DPA', + 33: 'DIO_DBG_BLOCK_SEL_DPB', + 34: 'DIO_DBG_BLOCK_SEL_DPC', + 35: 'DIO_DBG_BLOCK_SEL_DPD', + 36: 'DIO_DBG_BLOCK_SEL_DPE', + 39: 'DIO_DBG_BLOCK_SEL_AUX0', + 40: 'DIO_DBG_BLOCK_SEL_AUX1', + 41: 'DIO_DBG_BLOCK_SEL_AUX2', + 42: 'DIO_DBG_BLOCK_SEL_AUX3', + 43: 'DIO_DBG_BLOCK_SEL_AUX4', + 45: 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', + 46: 'DIO_DBG_BLOCK_SEL_RESERVED', +} +DIO_DBG_BLOCK_SEL_DIO = 0 +DIO_DBG_BLOCK_SEL_DIGFE_A = 11 +DIO_DBG_BLOCK_SEL_DIGFE_B = 12 +DIO_DBG_BLOCK_SEL_DIGFE_C = 13 +DIO_DBG_BLOCK_SEL_DIGFE_D = 14 +DIO_DBG_BLOCK_SEL_DIGFE_E = 15 +DIO_DBG_BLOCK_SEL_DIGA = 18 +DIO_DBG_BLOCK_SEL_DIGB = 19 +DIO_DBG_BLOCK_SEL_DIGC = 20 +DIO_DBG_BLOCK_SEL_DIGD = 21 +DIO_DBG_BLOCK_SEL_DIGE = 22 +DIO_DBG_BLOCK_SEL_DPFE_A = 25 +DIO_DBG_BLOCK_SEL_DPFE_B = 26 +DIO_DBG_BLOCK_SEL_DPFE_C = 27 +DIO_DBG_BLOCK_SEL_DPFE_D = 28 +DIO_DBG_BLOCK_SEL_DPFE_E = 29 +DIO_DBG_BLOCK_SEL_DPA = 32 +DIO_DBG_BLOCK_SEL_DPB = 33 +DIO_DBG_BLOCK_SEL_DPC = 34 +DIO_DBG_BLOCK_SEL_DPD = 35 +DIO_DBG_BLOCK_SEL_DPE = 36 +DIO_DBG_BLOCK_SEL_AUX0 = 39 +DIO_DBG_BLOCK_SEL_AUX1 = 40 +DIO_DBG_BLOCK_SEL_AUX2 = 41 +DIO_DBG_BLOCK_SEL_AUX3 = 42 +DIO_DBG_BLOCK_SEL_AUX4 = 43 +DIO_DBG_BLOCK_SEL_PERFMON_DIO = 45 +DIO_DBG_BLOCK_SEL_RESERVED = 46 +DIO_DBG_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE' +DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE__enumvalues = { + 0: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 1: 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', +} +DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0 +DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 1 +DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE' +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE__enumvalues = { + 0: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', + 1: 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', +} +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0 +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 1 +DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DIO_DCN_ACTIVE_STATUS' +ENUM_DIO_DCN_ACTIVE_STATUS__enumvalues = { + 0: 'ENUM_DCN_NOT_ACTIVE', + 1: 'ENUM_DCN_ACTIVE', +} +ENUM_DCN_NOT_ACTIVE = 0 +ENUM_DCN_ACTIVE = 1 +ENUM_DIO_DCN_ACTIVE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_STEREOSYNC_SEL' +GENERIC_STEREOSYNC_SEL__enumvalues = { + 0: 'GENERIC_STEREOSYNC_SEL_D1', + 1: 'GENERIC_STEREOSYNC_SEL_D2', + 2: 'GENERIC_STEREOSYNC_SEL_D3', + 3: 'GENERIC_STEREOSYNC_SEL_D4', + 4: 'GENERIC_STEREOSYNC_SEL_RESERVED', +} +GENERIC_STEREOSYNC_SEL_D1 = 0 +GENERIC_STEREOSYNC_SEL_D2 = 1 +GENERIC_STEREOSYNC_SEL_D3 = 2 +GENERIC_STEREOSYNC_SEL_D4 = 3 +GENERIC_STEREOSYNC_SEL_RESERVED = 4 +GENERIC_STEREOSYNC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PM_ASSERT_RESET' +PM_ASSERT_RESET__enumvalues = { + 0: 'PM_ASSERT_RESET_0', + 1: 'PM_ASSERT_RESET_1', +} +PM_ASSERT_RESET_0 = 0 +PM_ASSERT_RESET_1 = 1 +PM_ASSERT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'SOFT_RESET' +SOFT_RESET__enumvalues = { + 0: 'SOFT_RESET_0', + 1: 'SOFT_RESET_1', +} +SOFT_RESET_0 = 0 +SOFT_RESET_1 = 1 +SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'TMDS_MUX_SELECT' +TMDS_MUX_SELECT__enumvalues = { + 0: 'TMDS_MUX_SELECT_B', + 1: 'TMDS_MUX_SELECT_G', + 2: 'TMDS_MUX_SELECT_R', + 3: 'TMDS_MUX_SELECT_RESERVED', +} +TMDS_MUX_SELECT_B = 0 +TMDS_MUX_SELECT_G = 1 +TMDS_MUX_SELECT_R = 2 +TMDS_MUX_SELECT_RESERVED = 3 +TMDS_MUX_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DME_MEM_POWER_STATE_ENUM' +DME_MEM_POWER_STATE_ENUM__enumvalues = { + 0: 'DME_MEM_POWER_STATE_ENUM_ON', + 1: 'DME_MEM_POWER_STATE_ENUM_LS', + 2: 'DME_MEM_POWER_STATE_ENUM_DS', + 3: 'DME_MEM_POWER_STATE_ENUM_SD', +} +DME_MEM_POWER_STATE_ENUM_ON = 0 +DME_MEM_POWER_STATE_ENUM_LS = 1 +DME_MEM_POWER_STATE_ENUM_DS = 2 +DME_MEM_POWER_STATE_ENUM_SD = 3 +DME_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DME_MEM_PWR_DIS_CTRL' +DME_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'DME_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'DME_MEM_DISABLE_MEM_PWR_CTRL', +} +DME_MEM_ENABLE_MEM_PWR_CTRL = 0 +DME_MEM_DISABLE_MEM_PWR_CTRL = 1 +DME_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'DME_MEM_PWR_FORCE_CTRL' +DME_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'DME_MEM_NO_FORCE_REQUEST', + 1: 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', +} +DME_MEM_NO_FORCE_REQUEST = 0 +DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 +DME_MEM_FORCE_SHUT_DOWN_REQUEST = 3 +DME_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'METADATA_HUBP_SEL' +METADATA_HUBP_SEL__enumvalues = { + 0: 'METADATA_HUBP_SEL_0', + 1: 'METADATA_HUBP_SEL_1', + 2: 'METADATA_HUBP_SEL_2', + 3: 'METADATA_HUBP_SEL_3', + 4: 'METADATA_HUBP_SEL_RESERVED', +} +METADATA_HUBP_SEL_0 = 0 +METADATA_HUBP_SEL_1 = 1 +METADATA_HUBP_SEL_2 = 2 +METADATA_HUBP_SEL_3 = 3 +METADATA_HUBP_SEL_RESERVED = 4 +METADATA_HUBP_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'METADATA_STREAM_TYPE_SEL' +METADATA_STREAM_TYPE_SEL__enumvalues = { + 0: 'METADATA_STREAM_DP', + 1: 'METADATA_STREAM_DVE', +} +METADATA_STREAM_DP = 0 +METADATA_STREAM_DVE = 1 +METADATA_STREAM_TYPE_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VPG_MEM_PWR_DIS_CTRL' +VPG_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'VPG_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'VPG_MEM_DISABLE_MEM_PWR_CTRL', +} +VPG_MEM_ENABLE_MEM_PWR_CTRL = 0 +VPG_MEM_DISABLE_MEM_PWR_CTRL = 1 +VPG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'VPG_MEM_PWR_FORCE_CTRL' +VPG_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'VPG_MEM_NO_FORCE_REQ', + 1: 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', +} +VPG_MEM_NO_FORCE_REQ = 0 +VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 1 +VPG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_ACP_TYPE' +AFMT_ACP_TYPE__enumvalues = { + 0: 'ACP_TYPE_GENERIC_AUDIO', + 1: 'ACP_TYPE_ICE60958_AUDIO', + 2: 'ACP_TYPE_DVD_AUDIO', + 3: 'ACP_TYPE_SUPER_AUDIO_CD', +} +ACP_TYPE_GENERIC_AUDIO = 0 +ACP_TYPE_ICE60958_AUDIO = 1 +ACP_TYPE_DVD_AUDIO = 2 +ACP_TYPE_SUPER_AUDIO_CD = 3 +AFMT_ACP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CH_SEL' +AFMT_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { + 0: 'AFMT_AUDIO_CRC_CH0_SIG', + 1: 'AFMT_AUDIO_CRC_CH1_SIG', + 2: 'AFMT_AUDIO_CRC_CH2_SIG', + 3: 'AFMT_AUDIO_CRC_CH3_SIG', + 4: 'AFMT_AUDIO_CRC_CH4_SIG', + 5: 'AFMT_AUDIO_CRC_CH5_SIG', + 6: 'AFMT_AUDIO_CRC_CH6_SIG', + 7: 'AFMT_AUDIO_CRC_CH7_SIG', + 8: 'AFMT_AUDIO_CRC_RESERVED_8', + 9: 'AFMT_AUDIO_CRC_RESERVED_9', + 10: 'AFMT_AUDIO_CRC_RESERVED_10', + 11: 'AFMT_AUDIO_CRC_RESERVED_11', + 12: 'AFMT_AUDIO_CRC_RESERVED_12', + 13: 'AFMT_AUDIO_CRC_RESERVED_13', + 14: 'AFMT_AUDIO_CRC_RESERVED_14', + 15: 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', +} +AFMT_AUDIO_CRC_CH0_SIG = 0 +AFMT_AUDIO_CRC_CH1_SIG = 1 +AFMT_AUDIO_CRC_CH2_SIG = 2 +AFMT_AUDIO_CRC_CH3_SIG = 3 +AFMT_AUDIO_CRC_CH4_SIG = 4 +AFMT_AUDIO_CRC_CH5_SIG = 5 +AFMT_AUDIO_CRC_CH6_SIG = 6 +AFMT_AUDIO_CRC_CH7_SIG = 7 +AFMT_AUDIO_CRC_RESERVED_8 = 8 +AFMT_AUDIO_CRC_RESERVED_9 = 9 +AFMT_AUDIO_CRC_RESERVED_10 = 10 +AFMT_AUDIO_CRC_RESERVED_11 = 11 +AFMT_AUDIO_CRC_RESERVED_12 = 12 +AFMT_AUDIO_CRC_RESERVED_13 = 13 +AFMT_AUDIO_CRC_RESERVED_14 = 14 +AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 15 +AFMT_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_CONT' +AFMT_AUDIO_CRC_CONTROL_CONT__enumvalues = { + 0: 'AFMT_AUDIO_CRC_ONESHOT', + 1: 'AFMT_AUDIO_CRC_AUTO_RESTART', +} +AFMT_AUDIO_CRC_ONESHOT = 0 +AFMT_AUDIO_CRC_AUTO_RESTART = 1 +AFMT_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_CRC_CONTROL_SOURCE' +AFMT_AUDIO_CRC_CONTROL_SOURCE__enumvalues = { + 0: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 1: 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', +} +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0 +AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 1 +AFMT_AUDIO_CRC_CONTROL_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD' +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD__enumvalues = { + 0: 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 1: 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', +} +AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0 +AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 1 +AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND' +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND__enumvalues = { + 0: 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 1: 'AFMT_AUDIO_PACKET_SENT_ENABLED', +} +AFMT_AUDIO_PACKET_SENT_DISABLED = 0 +AFMT_AUDIO_PACKET_SENT_ENABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS' +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS__enumvalues = { + 0: 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 1: 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', +} +AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0 +AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 1 +AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_AUDIO_SRC_CONTROL_SELECT' +AFMT_AUDIO_SRC_CONTROL_SELECT__enumvalues = { + 0: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 1: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 2: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 3: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 4: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 5: 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', +} +AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0 +AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 1 +AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 2 +AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 3 +AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 4 +AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 5 +AFMT_AUDIO_SRC_CONTROL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS' +AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__enumvalues = { + 0: 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 1: 'HDMI_SEND_MAX_AUDIO_PACKETS', +} +HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0 +HDMI_SEND_MAX_AUDIO_PACKETS = 1 +AFMT_HDMI_AUDIO_SEND_MAX_PACKETS = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE' +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE__enumvalues = { + 0: 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 1: 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', +} +AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0 +AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 1 +AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_INTERRUPT_STATUS_CHG_MASK' +AFMT_INTERRUPT_STATUS_CHG_MASK__enumvalues = { + 0: 'AFMT_INTERRUPT_DISABLE', + 1: 'AFMT_INTERRUPT_ENABLE', +} +AFMT_INTERRUPT_DISABLE = 0 +AFMT_INTERRUPT_ENABLE = 1 +AFMT_INTERRUPT_STATUS_CHG_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_MEM_PWR_DIS_CTRL' +AFMT_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', +} +AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0 +AFMT_MEM_DISABLE_MEM_PWR_CTRL = 1 +AFMT_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_MEM_PWR_FORCE_CTRL' +AFMT_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'AFMT_MEM_NO_FORCE_REQUEST', + 1: 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', +} +AFMT_MEM_NO_FORCE_REQUEST = 0 +AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 +AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 3 +AFMT_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_RAMP_CONTROL0_SIGN' +AFMT_RAMP_CONTROL0_SIGN__enumvalues = { + 0: 'AFMT_RAMP_SIGNED', + 1: 'AFMT_RAMP_UNSIGNED', +} +AFMT_RAMP_SIGNED = 0 +AFMT_RAMP_UNSIGNED = 1 +AFMT_RAMP_CONTROL0_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE' +AFMT_VBI_PACKET_CONTROL_ACP_SOURCE__enumvalues = { + 0: 'AFMT_ACP_SOURCE_FROM_AZALIA', + 1: 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', +} +AFMT_ACP_SOURCE_FROM_AZALIA = 0 +AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 1 +AFMT_VBI_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'AUDIO_LAYOUT_SELECT' +AUDIO_LAYOUT_SELECT__enumvalues = { + 0: 'AUDIO_LAYOUT_0', + 1: 'AUDIO_LAYOUT_1', +} +AUDIO_LAYOUT_0 = 0 +AUDIO_LAYOUT_1 = 1 +AUDIO_LAYOUT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HPO_TOP_CLOCK_GATING_DISABLE' +HPO_TOP_CLOCK_GATING_DISABLE__enumvalues = { + 0: 'HPO_TOP_CLOCK_GATING_EN', + 1: 'HPO_TOP_CLOCK_GATING_DIS', +} +HPO_TOP_CLOCK_GATING_EN = 0 +HPO_TOP_CLOCK_GATING_DIS = 1 +HPO_TOP_CLOCK_GATING_DISABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HPO_TOP_TEST_CLK_SEL' +HPO_TOP_TEST_CLK_SEL__enumvalues = { + 0: 'HPO_TOP_PERMANENT_DISPCLK', + 1: 'HPO_TOP_REGISTER_GATED_DISPCLK', + 2: 'HPO_TOP_PERMANENT_SOCCLK', + 3: 'HPO_TOP_TEST_CLOCK_RESERVED', + 4: 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', + 5: 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', + 6: 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', + 7: 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', + 8: 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', + 9: 'HPO_TOP_PERMANENT_HDMICHARCLK0', + 10: 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', + 11: 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', +} +HPO_TOP_PERMANENT_DISPCLK = 0 +HPO_TOP_REGISTER_GATED_DISPCLK = 1 +HPO_TOP_PERMANENT_SOCCLK = 2 +HPO_TOP_TEST_CLOCK_RESERVED = 3 +HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 4 +HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 5 +HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 6 +HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 7 +HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 8 +HPO_TOP_PERMANENT_HDMICHARCLK0 = 9 +HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 10 +HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 11 +HPO_TOP_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET' +DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET__enumvalues = { + 0: 'DP_STREAM_MAPPER_LINK0', + 1: 'DP_STREAM_MAPPER_LINK1', + 2: 'DP_STREAM_MAPPER_RESERVED', +} +DP_STREAM_MAPPER_LINK0 = 0 +DP_STREAM_MAPPER_LINK1 = 1 +DP_STREAM_MAPPER_RESERVED = 2 +DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_DB_DISABLE_CONTROL' +HDMI_STREAM_ENC_DB_DISABLE_CONTROL__enumvalues = { + 0: 'HDMI_STREAM_ENC_DB_ENABLE', + 1: 'HDMI_STREAM_ENC_DB_DISABLE', +} +HDMI_STREAM_ENC_DB_ENABLE = 0 +HDMI_STREAM_ENC_DB_DISABLE = 1 +HDMI_STREAM_ENC_DB_DISABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_DSC_MODE' +HDMI_STREAM_ENC_DSC_MODE__enumvalues = { + 0: 'STREAM_DSC_DISABLE', + 1: 'STREAM_DSC_444_RGB', + 2: 'STREAM_DSC_NATIVE_422_420', +} +STREAM_DSC_DISABLE = 0 +STREAM_DSC_444_RGB = 1 +STREAM_DSC_NATIVE_422_420 = 2 +HDMI_STREAM_ENC_DSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_ENABLE_CONTROL' +HDMI_STREAM_ENC_ENABLE_CONTROL__enumvalues = { + 0: 'HDMI_STREAM_ENC_DISABLE', + 1: 'HDMI_STREAM_ENC_ENABLE', +} +HDMI_STREAM_ENC_DISABLE = 0 +HDMI_STREAM_ENC_ENABLE = 1 +HDMI_STREAM_ENC_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_ODM_COMBINE_MODE' +HDMI_STREAM_ENC_ODM_COMBINE_MODE__enumvalues = { + 0: 'STREAM_ODM_COMBINE_1_SEGMENT', + 1: 'STREAM_ODM_COMBINE_2_SEGMENT', + 2: 'STREAM_ODM_COMBINE_RESERVED', + 3: 'STREAM_ODM_COMBINE_4_SEGMENT', +} +STREAM_ODM_COMBINE_1_SEGMENT = 0 +STREAM_ODM_COMBINE_2_SEGMENT = 1 +STREAM_ODM_COMBINE_RESERVED = 2 +STREAM_ODM_COMBINE_4_SEGMENT = 3 +HDMI_STREAM_ENC_ODM_COMBINE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR' +HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { + 0: 'HDMI_STREAM_ENC_NO_ERROR_OCCURRED', + 1: 'HDMI_STREAM_ENC_UNDERFLOW_OCCURRED', + 2: 'HDMI_STREAM_ENC_OVERFLOW_OCCURRED', +} +HDMI_STREAM_ENC_NO_ERROR_OCCURRED = 0 +HDMI_STREAM_ENC_UNDERFLOW_OCCURRED = 1 +HDMI_STREAM_ENC_OVERFLOW_OCCURRED = 2 +HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT' +HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = { + 0: 'HDMI_STREAM_ENC_HARDWARE', + 1: 'HDMI_STREAM_ENC_PROGRAMMABLE', +} +HDMI_STREAM_ENC_HARDWARE = 0 +HDMI_STREAM_ENC_PROGRAMMABLE = 1 +HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_PIXEL_ENCODING' +HDMI_STREAM_ENC_PIXEL_ENCODING__enumvalues = { + 0: 'STREAM_PIXEL_ENCODING_444_RGB', + 1: 'STREAM_PIXEL_ENCODING_422', + 2: 'STREAM_PIXEL_ENCODING_420', +} +STREAM_PIXEL_ENCODING_444_RGB = 0 +STREAM_PIXEL_ENCODING_422 = 1 +STREAM_PIXEL_ENCODING_420 = 2 +HDMI_STREAM_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_READ_CLOCK_CONTROL' +HDMI_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = { + 0: 'HDMI_STREAM_ENC_DCCG', + 1: 'HDMI_STREAM_ENC_DISPLAY_PIPE', +} +HDMI_STREAM_ENC_DCCG = 0 +HDMI_STREAM_ENC_DISPLAY_PIPE = 1 +HDMI_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_RESET_CONTROL' +HDMI_STREAM_ENC_RESET_CONTROL__enumvalues = { + 0: 'HDMI_STREAM_ENC_NOT_RESET', + 1: 'HDMI_STREAM_ENC_RESET', +} +HDMI_STREAM_ENC_NOT_RESET = 0 +HDMI_STREAM_ENC_RESET = 1 +HDMI_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_STREAM_ENC_STREAM_ACTIVE' +HDMI_STREAM_ENC_STREAM_ACTIVE__enumvalues = { + 0: 'HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', + 1: 'HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE', +} +HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0 +HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1 +HDMI_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'BORROWBUFFER_MEM_POWER_STATE_ENUM' +BORROWBUFFER_MEM_POWER_STATE_ENUM__enumvalues = { + 0: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_ON', + 1: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_LS', + 2: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_DS', + 3: 'BORROWBUFFER_MEM_POWER_STATE_ENUM_SD', +} +BORROWBUFFER_MEM_POWER_STATE_ENUM_ON = 0 +BORROWBUFFER_MEM_POWER_STATE_ENUM_LS = 1 +BORROWBUFFER_MEM_POWER_STATE_ENUM_DS = 2 +BORROWBUFFER_MEM_POWER_STATE_ENUM_SD = 3 +BORROWBUFFER_MEM_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_BORROW_MODE' +HDMI_BORROW_MODE__enumvalues = { + 0: 'TB_BORROW_MODE_NONE', + 1: 'TB_BORROW_MODE_ACTIVE', + 2: 'TB_BORROW_MODE_BLANK', + 3: 'TB_BORROW_MODE_RESERVED', +} +TB_BORROW_MODE_NONE = 0 +TB_BORROW_MODE_ACTIVE = 1 +TB_BORROW_MODE_BLANK = 2 +TB_BORROW_MODE_RESERVED = 3 +HDMI_BORROW_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACP_SEND' +HDMI_TB_ENC_ACP_SEND__enumvalues = { + 0: 'TB_ACP_NOT_SEND', + 1: 'TB_ACP_PKT_SEND', +} +TB_ACP_NOT_SEND = 0 +TB_ACP_PKT_SEND = 1 +HDMI_TB_ENC_ACP_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_AUDIO_PRIORITY' +HDMI_TB_ENC_ACR_AUDIO_PRIORITY__enumvalues = { + 0: 'TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 1: 'TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', +} +TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0 +TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 1 +HDMI_TB_ENC_ACR_AUDIO_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_CONT' +HDMI_TB_ENC_ACR_CONT__enumvalues = { + 0: 'TB_ACR_CONT_DISABLE', + 1: 'TB_ACR_CONT_ENABLE', +} +TB_ACR_CONT_DISABLE = 0 +TB_ACR_CONT_ENABLE = 1 +HDMI_TB_ENC_ACR_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_N_MULTIPLE' +HDMI_TB_ENC_ACR_N_MULTIPLE__enumvalues = { + 0: 'TB_ACR_0_MULTIPLE_RESERVED', + 1: 'TB_ACR_1_MULTIPLE', + 2: 'TB_ACR_2_MULTIPLE', + 3: 'TB_ACR_3_MULTIPLE_RESERVED', + 4: 'TB_ACR_4_MULTIPLE', + 5: 'TB_ACR_5_MULTIPLE_RESERVED', + 6: 'TB_ACR_6_MULTIPLE_RESERVED', + 7: 'TB_ACR_7_MULTIPLE_RESERVED', +} +TB_ACR_0_MULTIPLE_RESERVED = 0 +TB_ACR_1_MULTIPLE = 1 +TB_ACR_2_MULTIPLE = 2 +TB_ACR_3_MULTIPLE_RESERVED = 3 +TB_ACR_4_MULTIPLE = 4 +TB_ACR_5_MULTIPLE_RESERVED = 5 +TB_ACR_6_MULTIPLE_RESERVED = 6 +TB_ACR_7_MULTIPLE_RESERVED = 7 +HDMI_TB_ENC_ACR_N_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_SELECT' +HDMI_TB_ENC_ACR_SELECT__enumvalues = { + 0: 'TB_ACR_SELECT_HW', + 1: 'TB_ACR_SELECT_32K', + 2: 'TB_ACR_SELECT_44K', + 3: 'TB_ACR_SELECT_48K', +} +TB_ACR_SELECT_HW = 0 +TB_ACR_SELECT_32K = 1 +TB_ACR_SELECT_44K = 2 +TB_ACR_SELECT_48K = 3 +HDMI_TB_ENC_ACR_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_SEND' +HDMI_TB_ENC_ACR_SEND__enumvalues = { + 0: 'TB_ACR_NOT_SEND', + 1: 'TB_ACR_PKT_SEND', +} +TB_ACR_NOT_SEND = 0 +TB_ACR_PKT_SEND = 1 +HDMI_TB_ENC_ACR_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ACR_SOURCE' +HDMI_TB_ENC_ACR_SOURCE__enumvalues = { + 0: 'TB_ACR_SOURCE_HW', + 1: 'TB_ACR_SOURCE_SW', +} +TB_ACR_SOURCE_HW = 0 +TB_ACR_SOURCE_SW = 1 +HDMI_TB_ENC_ACR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_AUDIO_INFO_CONT' +HDMI_TB_ENC_AUDIO_INFO_CONT__enumvalues = { + 0: 'TB_AUDIO_INFO_CONT_DISABLE', + 1: 'TB_AUDIO_INFO_CONT_ENABLE', +} +TB_AUDIO_INFO_CONT_DISABLE = 0 +TB_AUDIO_INFO_CONT_ENABLE = 1 +HDMI_TB_ENC_AUDIO_INFO_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_AUDIO_INFO_SEND' +HDMI_TB_ENC_AUDIO_INFO_SEND__enumvalues = { + 0: 'TB_AUDIO_INFO_NOT_SEND', + 1: 'TB_AUDIO_INFO_PKT_SEND', +} +TB_AUDIO_INFO_NOT_SEND = 0 +TB_AUDIO_INFO_PKT_SEND = 1 +HDMI_TB_ENC_AUDIO_INFO_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_CRC_SRC_SEL' +HDMI_TB_ENC_CRC_SRC_SEL__enumvalues = { + 0: 'TB_CRC_TB_ENC_INPUT', + 1: 'TB_CRC_DSC_PACKER', + 2: 'TB_CRC_DEEP_COLOR_PACKER', + 3: 'TB_CRC_ENCRYPTOR_INPUT', +} +TB_CRC_TB_ENC_INPUT = 0 +TB_CRC_DSC_PACKER = 1 +TB_CRC_DEEP_COLOR_PACKER = 2 +TB_CRC_ENCRYPTOR_INPUT = 3 +HDMI_TB_ENC_CRC_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_CRC_TYPE' +HDMI_TB_ENC_CRC_TYPE__enumvalues = { + 0: 'TB_CRC_ALL_TRIBYTES', + 1: 'TB_CRC_ACTIVE_TRIBYTES', + 2: 'TB_CRC_DATAISLAND_TRIBYTES', + 3: 'TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES', +} +TB_CRC_ALL_TRIBYTES = 0 +TB_CRC_ACTIVE_TRIBYTES = 1 +TB_CRC_DATAISLAND_TRIBYTES = 2 +TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES = 3 +HDMI_TB_ENC_CRC_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_DEEP_COLOR_DEPTH' +HDMI_TB_ENC_DEEP_COLOR_DEPTH__enumvalues = { + 0: 'TB_DEEP_COLOR_DEPTH_24BPP', + 1: 'TB_DEEP_COLOR_DEPTH_30BPP', + 2: 'TB_DEEP_COLOR_DEPTH_36BPP', + 3: 'TB_DEEP_COLOR_DEPTH_RESERVED', +} +TB_DEEP_COLOR_DEPTH_24BPP = 0 +TB_DEEP_COLOR_DEPTH_30BPP = 1 +TB_DEEP_COLOR_DEPTH_36BPP = 2 +TB_DEEP_COLOR_DEPTH_RESERVED = 3 +HDMI_TB_ENC_DEEP_COLOR_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_DEFAULT_PAHSE' +HDMI_TB_ENC_DEFAULT_PAHSE__enumvalues = { + 0: 'TB_DEFAULT_PHASE_IS_0', + 1: 'TB_DEFAULT_PHASE_IS_1', +} +TB_DEFAULT_PHASE_IS_0 = 0 +TB_DEFAULT_PHASE_IS_1 = 1 +HDMI_TB_ENC_DEFAULT_PAHSE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_DSC_MODE' +HDMI_TB_ENC_DSC_MODE__enumvalues = { + 0: 'TB_DSC_DISABLE', + 1: 'TB_DSC_444_RGB', + 2: 'TB_DSC_NATIVE_422_420', +} +TB_DSC_DISABLE = 0 +TB_DSC_444_RGB = 1 +TB_DSC_NATIVE_422_420 = 2 +HDMI_TB_ENC_DSC_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ENABLE' +HDMI_TB_ENC_ENABLE__enumvalues = { + 0: 'TB_DISABLE', + 1: 'TB_ENABLE', +} +TB_DISABLE = 0 +TB_ENABLE = 1 +HDMI_TB_ENC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GC_AVMUTE' +HDMI_TB_ENC_GC_AVMUTE__enumvalues = { + 0: 'TB_GC_AVMUTE_SET', + 1: 'TB_GC_AVMUTE_UNSET', +} +TB_GC_AVMUTE_SET = 0 +TB_GC_AVMUTE_UNSET = 1 +HDMI_TB_ENC_GC_AVMUTE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GC_AVMUTE_CONT' +HDMI_TB_ENC_GC_AVMUTE_CONT__enumvalues = { + 0: 'TB_GC_AVMUTE_CONT_DISABLE', + 1: 'TB_GC_AVMUTE_CONT_ENABLE', +} +TB_GC_AVMUTE_CONT_DISABLE = 0 +TB_GC_AVMUTE_CONT_ENABLE = 1 +HDMI_TB_ENC_GC_AVMUTE_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GC_CONT' +HDMI_TB_ENC_GC_CONT__enumvalues = { + 0: 'TB_GC_CONT_DISABLE', + 1: 'TB_GC_CONT_ENABLE', +} +TB_GC_CONT_DISABLE = 0 +TB_GC_CONT_ENABLE = 1 +HDMI_TB_ENC_GC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GC_SEND' +HDMI_TB_ENC_GC_SEND__enumvalues = { + 0: 'TB_GC_NOT_SEND', + 1: 'TB_GC_PKT_SEND', +} +TB_GC_NOT_SEND = 0 +TB_GC_PKT_SEND = 1 +HDMI_TB_ENC_GC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GENERIC_CONT' +HDMI_TB_ENC_GENERIC_CONT__enumvalues = { + 0: 'TB_GENERIC_CONT_DISABLE', + 1: 'TB_GENERIC_CONT_ENABLE', +} +TB_GENERIC_CONT_DISABLE = 0 +TB_GENERIC_CONT_ENABLE = 1 +HDMI_TB_ENC_GENERIC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GENERIC_LOCK_EN' +HDMI_TB_ENC_GENERIC_LOCK_EN__enumvalues = { + 0: 'HDMI_TB_ENC_GENERIC_LOCK_DISABLE', + 1: 'HDMI_TB_ENC_GENERIC_LOCK_ENABLE', +} +HDMI_TB_ENC_GENERIC_LOCK_DISABLE = 0 +HDMI_TB_ENC_GENERIC_LOCK_ENABLE = 1 +HDMI_TB_ENC_GENERIC_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_GENERIC_SEND' +HDMI_TB_ENC_GENERIC_SEND__enumvalues = { + 0: 'TB_GENERIC_NOT_SEND', + 1: 'TB_GENERIC_PKT_SEND', +} +TB_GENERIC_NOT_SEND = 0 +TB_GENERIC_PKT_SEND = 1 +HDMI_TB_ENC_GENERIC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ISRC_CONT' +HDMI_TB_ENC_ISRC_CONT__enumvalues = { + 0: 'TB_ISRC_CONT_DISABLE', + 1: 'TB_ISRC_CONT_ENABLE', +} +TB_ISRC_CONT_DISABLE = 0 +TB_ISRC_CONT_ENABLE = 1 +HDMI_TB_ENC_ISRC_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_ISRC_SEND' +HDMI_TB_ENC_ISRC_SEND__enumvalues = { + 0: 'TB_ISRC_NOT_SEND', + 1: 'TB_ISRC_PKT_SEND', +} +TB_ISRC_NOT_SEND = 0 +TB_ISRC_PKT_SEND = 1 +HDMI_TB_ENC_ISRC_SEND = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_METADATA_ENABLE' +HDMI_TB_ENC_METADATA_ENABLE__enumvalues = { + 0: 'TB_METADATA_NOT_SEND', + 1: 'TB_METADATA_PKT_SEND', +} +TB_METADATA_NOT_SEND = 0 +TB_METADATA_PKT_SEND = 1 +HDMI_TB_ENC_METADATA_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_PACKET_LINE_REFERENCE' +HDMI_TB_ENC_PACKET_LINE_REFERENCE__enumvalues = { + 0: 'TB_PKT_LINE_REF_END_OF_ACTIVE', + 1: 'TB_PKT_LINE_REF_OTGSOF', +} +TB_PKT_LINE_REF_END_OF_ACTIVE = 0 +TB_PKT_LINE_REF_OTGSOF = 1 +HDMI_TB_ENC_PACKET_LINE_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_PIXEL_ENCODING' +HDMI_TB_ENC_PIXEL_ENCODING__enumvalues = { + 0: 'TB_PIXEL_ENCODING_444_RGB', + 1: 'TB_PIXEL_ENCODING_422', + 2: 'TB_PIXEL_ENCODING_420', +} +TB_PIXEL_ENCODING_444_RGB = 0 +TB_PIXEL_ENCODING_422 = 1 +TB_PIXEL_ENCODING_420 = 2 +HDMI_TB_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_RESET' +HDMI_TB_ENC_RESET__enumvalues = { + 0: 'TB_NOT_RESET', + 1: 'TB_RESET', +} +TB_NOT_RESET = 0 +TB_RESET = 1 +HDMI_TB_ENC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'HDMI_TB_ENC_SYNC_PHASE' +HDMI_TB_ENC_SYNC_PHASE__enumvalues = { + 0: 'TB_NOT_SYNC_PHASE_ON_FRAME_START', + 1: 'TB_SYNC_PHASE_ON_FRAME_START', +} +TB_NOT_SYNC_PHASE_ON_FRAME_START = 0 +TB_SYNC_PHASE_ON_FRAME_START = 1 +HDMI_TB_ENC_SYNC_PHASE = ctypes.c_uint32 # enum + +# values for enumeration 'INPUT_FIFO_ERROR_TYPE' +INPUT_FIFO_ERROR_TYPE__enumvalues = { + 0: 'TB_NO_ERROR_OCCURRED', + 1: 'TB_OVERFLOW_OCCURRED', +} +TB_NO_ERROR_OCCURRED = 0 +TB_OVERFLOW_OCCURRED = 1 +INPUT_FIFO_ERROR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR' +DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR__enumvalues = { + 0: 'DP_STREAM_ENC_NO_ERROR_OCCURRED', + 1: 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', + 2: 'DP_STREAM_ENC_OVERFLOW_OCCURRED', +} +DP_STREAM_ENC_NO_ERROR_OCCURRED = 0 +DP_STREAM_ENC_UNDERFLOW_OCCURRED = 1 +DP_STREAM_ENC_OVERFLOW_OCCURRED = 2 +DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT' +DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT__enumvalues = { + 0: 'DP_STREAM_ENC_HARDWARE', + 1: 'DP_STREAM_ENC_PROGRAMMABLE', +} +DP_STREAM_ENC_HARDWARE = 0 +DP_STREAM_ENC_PROGRAMMABLE = 1 +DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_READ_CLOCK_CONTROL' +DP_STREAM_ENC_READ_CLOCK_CONTROL__enumvalues = { + 0: 'DP_STREAM_ENC_DCCG', + 1: 'DP_STREAM_ENC_DISPLAY_PIPE', +} +DP_STREAM_ENC_DCCG = 0 +DP_STREAM_ENC_DISPLAY_PIPE = 1 +DP_STREAM_ENC_READ_CLOCK_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_RESET_CONTROL' +DP_STREAM_ENC_RESET_CONTROL__enumvalues = { + 0: 'DP_STREAM_ENC_NOT_RESET', + 1: 'DP_STREAM_ENC_RESET', +} +DP_STREAM_ENC_NOT_RESET = 0 +DP_STREAM_ENC_RESET = 1 +DP_STREAM_ENC_RESET_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'DP_STREAM_ENC_STREAM_ACTIVE' +DP_STREAM_ENC_STREAM_ACTIVE__enumvalues = { + 0: 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', + 1: 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', +} +DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0 +DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 1 +DP_STREAM_ENC_STREAM_ACTIVE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_AUDIO_MUTE' +ENUM_DP_SYM32_ENC_AUDIO_MUTE__enumvalues = { + 0: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', + 1: 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', +} +DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0 +DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 1 +ENUM_DP_SYM32_ENC_AUDIO_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE' +ENUM_DP_SYM32_ENC_CONTINUOUS_MODE__enumvalues = { + 0: 'DP_SYM32_ENC_ONE_SHOT_MODE', + 1: 'DP_SYM32_ENC_CONTINUOUS_MODE', +} +DP_SYM32_ENC_ONE_SHOT_MODE = 0 +DP_SYM32_ENC_CONTINUOUS_MODE = 1 +ENUM_DP_SYM32_ENC_CONTINUOUS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_CRC_VALID' +ENUM_DP_SYM32_ENC_CRC_VALID__enumvalues = { + 0: 'DP_SYM32_ENC_CRC_NOT_VALID', + 1: 'DP_SYM32_ENC_CRC_VALID', +} +DP_SYM32_ENC_CRC_NOT_VALID = 0 +DP_SYM32_ENC_CRC_VALID = 1 +ENUM_DP_SYM32_ENC_CRC_VALID = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH' +ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH__enumvalues = { + 0: 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', + 1: 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', + 2: 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', + 3: 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', +} +DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0 +DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 1 +DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 2 +DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 3 +ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_ENABLE' +ENUM_DP_SYM32_ENC_ENABLE__enumvalues = { + 0: 'DP_SYM32_ENC_DISABLE', + 1: 'DP_SYM32_ENC_ENABLE', +} +DP_SYM32_ENC_DISABLE = 0 +DP_SYM32_ENC_ENABLE = 1 +ENUM_DP_SYM32_ENC_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED' +ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', + 1: 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', +} +DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0 +DP_SYM32_ENC_GSP_DEADLINE_MISSED = 1 +ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION' +ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', + 1: 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', +} +DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0 +DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 1 +ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE' +ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', + 1: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', + 2: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', + 3: 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', +} +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0 +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 1 +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 2 +DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 3 +ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING' +ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING__enumvalues = { + 0: 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', + 1: 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', +} +DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0 +DP_SYM32_ENC_GSP_TRIGGER_PENDING = 1 +ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM' +ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', + 1: 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', +} +DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0 +DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 1 +DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 2 +DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 3 +ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS' +ENUM_DP_SYM32_ENC_OVERFLOW_STATUS__enumvalues = { + 0: 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', + 1: 'DP_SYM32_ENC_OVERFLOW_OCCURRED', +} +DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0 +DP_SYM32_ENC_OVERFLOW_OCCURRED = 1 +ENUM_DP_SYM32_ENC_OVERFLOW_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_PENDING' +ENUM_DP_SYM32_ENC_PENDING__enumvalues = { + 0: 'DP_SYM32_ENC_NOT_PENDING', + 1: 'DP_SYM32_ENC_PENDING', +} +DP_SYM32_ENC_NOT_PENDING = 0 +DP_SYM32_ENC_PENDING = 1 +ENUM_DP_SYM32_ENC_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING' +ENUM_DP_SYM32_ENC_PIXEL_ENCODING__enumvalues = { + 0: 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', + 1: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', + 2: 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', + 3: 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', +} +DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0 +DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 1 +DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 2 +DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 3 +ENUM_DP_SYM32_ENC_PIXEL_ENCODING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE' +ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE__enumvalues = { + 0: 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', + 1: 'DP_SYM32_ENC_COMPRESSED_FORMAT', +} +DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0 +DP_SYM32_ENC_COMPRESSED_FORMAT = 1 +ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM' +ENUM_DP_SYM32_ENC_POWER_STATE_ENUM__enumvalues = { + 0: 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', + 1: 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', + 2: 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', + 3: 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', +} +DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0 +DP_SYM32_ENC_POWER_STATE_ENUM_LS = 1 +DP_SYM32_ENC_POWER_STATE_ENUM_DS = 2 +DP_SYM32_ENC_POWER_STATE_ENUM_SD = 3 +ENUM_DP_SYM32_ENC_POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_RESET' +ENUM_DP_SYM32_ENC_RESET__enumvalues = { + 0: 'DP_SYM32_ENC_NOT_RESET', + 1: 'DP_SYM32_ENC_RESET', +} +DP_SYM32_ENC_NOT_RESET = 0 +DP_SYM32_ENC_RESET = 1 +ENUM_DP_SYM32_ENC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_SDP_PRIORITY' +ENUM_DP_SYM32_ENC_SDP_PRIORITY__enumvalues = { + 0: 'DP_SYM32_ENC_SDP_LOW_PRIORITY', + 1: 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', +} +DP_SYM32_ENC_SDP_LOW_PRIORITY = 0 +DP_SYM32_ENC_SDP_HIGH_PRIORITY = 1 +ENUM_DP_SYM32_ENC_SDP_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_SOF_REFERENCE' +ENUM_DP_SYM32_ENC_SOF_REFERENCE__enumvalues = { + 0: 'DP_SYM32_ENC_DP_SOF', + 1: 'DP_SYM32_ENC_OTG_SOF', +} +DP_SYM32_ENC_DP_SOF = 0 +DP_SYM32_ENC_OTG_SOF = 1 +ENUM_DP_SYM32_ENC_SOF_REFERENCE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER' +ENUM_DP_SYM32_ENC_VID_STREAM_DEFER__enumvalues = { + 0: 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', + 1: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', + 2: 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', +} +DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0 +DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 1 +DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 2 +ENUM_DP_SYM32_ENC_VID_STREAM_DEFER = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT' +ENUM_DP_DPHY_SYM32_CRC_END_EVENT__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_END_LLCP', + 1: 'DP_DPHY_SYM32_CRC_END_PS_ONLY', + 2: 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', + 3: 'DP_DPHY_SYM32_CRC_END_PS_ANY', +} +DP_DPHY_SYM32_CRC_END_LLCP = 0 +DP_DPHY_SYM32_CRC_END_PS_ONLY = 1 +DP_DPHY_SYM32_CRC_END_PS_LT_SR = 2 +DP_DPHY_SYM32_CRC_END_PS_ANY = 3 +ENUM_DP_DPHY_SYM32_CRC_END_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT' +ENUM_DP_DPHY_SYM32_CRC_START_EVENT__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_START_LLCP', + 1: 'DP_DPHY_SYM32_CRC_START_PS_ONLY', + 2: 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', + 3: 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', + 4: 'DP_DPHY_SYM32_CRC_START_TP_START', +} +DP_DPHY_SYM32_CRC_START_LLCP = 0 +DP_DPHY_SYM32_CRC_START_PS_ONLY = 1 +DP_DPHY_SYM32_CRC_START_PS_LT_SR = 2 +DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 3 +DP_DPHY_SYM32_CRC_START_TP_START = 4 +ENUM_DP_DPHY_SYM32_CRC_START_EVENT = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE' +ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', + 1: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', + 2: 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', +} +DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0 +DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 1 +DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 2 +ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS' +ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS__enumvalues = { + 0: 'DP_DPHY_SYM32_CRC_USE_END_EVENT', + 1: 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', +} +DP_DPHY_SYM32_CRC_USE_END_EVENT = 0 +DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 1 +ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_ENABLE' +ENUM_DP_DPHY_SYM32_ENABLE__enumvalues = { + 0: 'DP_DPHY_SYM32_DISABLE', + 1: 'DP_DPHY_SYM32_ENABLE', +} +DP_DPHY_SYM32_DISABLE = 0 +DP_DPHY_SYM32_ENABLE = 1 +ENUM_DP_DPHY_SYM32_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE' +ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE__enumvalues = { + 0: 'DP_DPHY_SYM32_ENCRYPT_TYPE0', + 1: 'DP_DPHY_SYM32_ENCRYPT_TYPE1', +} +DP_DPHY_SYM32_ENCRYPT_TYPE0 = 0 +DP_DPHY_SYM32_ENCRYPT_TYPE1 = 1 +ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_MODE' +ENUM_DP_DPHY_SYM32_MODE__enumvalues = { + 0: 'DP_DPHY_SYM32_LT_TPS1', + 1: 'DP_DPHY_SYM32_LT_TPS2', + 2: 'DP_DPHY_SYM32_ACTIVE', + 3: 'DP_DPHY_SYM32_TEST', +} +DP_DPHY_SYM32_LT_TPS1 = 0 +DP_DPHY_SYM32_LT_TPS2 = 1 +DP_DPHY_SYM32_ACTIVE = 2 +DP_DPHY_SYM32_TEST = 3 +ENUM_DP_DPHY_SYM32_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_NUM_LANES' +ENUM_DP_DPHY_SYM32_NUM_LANES__enumvalues = { + 0: 'DP_DPHY_SYM32_1LANE', + 1: 'DP_DPHY_SYM32_2LANE', + 2: 'DP_DPHY_SYM32_RESERVED', + 3: 'DP_DPHY_SYM32_4LANE', +} +DP_DPHY_SYM32_1LANE = 0 +DP_DPHY_SYM32_2LANE = 1 +DP_DPHY_SYM32_RESERVED = 2 +DP_DPHY_SYM32_4LANE = 3 +ENUM_DP_DPHY_SYM32_NUM_LANES = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING' +ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING__enumvalues = { + 0: 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', + 1: 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', +} +DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0 +DP_DPHY_SYM32_RATE_UPDATE_PENDING = 1 +ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET' +ENUM_DP_DPHY_SYM32_RESET__enumvalues = { + 0: 'DP_DPHY_SYM32_NOT_RESET', + 1: 'DP_DPHY_SYM32_RESET', +} +DP_DPHY_SYM32_NOT_RESET = 0 +DP_DPHY_SYM32_RESET = 1 +ENUM_DP_DPHY_SYM32_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_RESET_STATUS' +ENUM_DP_DPHY_SYM32_RESET_STATUS__enumvalues = { + 0: 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', + 1: 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', +} +DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0 +DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 1 +ENUM_DP_DPHY_SYM32_RESET_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE' +ENUM_DP_DPHY_SYM32_SAT_UPDATE__enumvalues = { + 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE', + 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', + 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', +} +DP_DPHY_SYM32_SAT_NO_UPDATE = 0 +DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 1 +DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 2 +ENUM_DP_DPHY_SYM32_SAT_UPDATE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING' +ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING__enumvalues = { + 0: 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', + 1: 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', + 2: 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', +} +DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0 +DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 1 +DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 2 +ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_STATUS' +ENUM_DP_DPHY_SYM32_STATUS__enumvalues = { + 0: 'DP_DPHY_SYM32_STATUS_IDLE', + 1: 'DP_DPHY_SYM32_STATUS_ENABLED', +} +DP_DPHY_SYM32_STATUS_IDLE = 0 +DP_DPHY_SYM32_STATUS_ENABLED = 1 +ENUM_DP_DPHY_SYM32_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE' +ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE__enumvalues = { + 0: 'DP_DPHY_SYM32_STREAM_OVR_NONE', + 1: 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', + 2: 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', +} +DP_DPHY_SYM32_STREAM_OVR_NONE = 0 +DP_DPHY_SYM32_STREAM_OVR_REPLACE = 1 +DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 2 +ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE' +ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE__enumvalues = { + 0: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', + 1: 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', +} +DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0 +DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 1 +ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL' +ENUM_DP_DPHY_SYM32_TP_PRBS_SEL__enumvalues = { + 0: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', + 1: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', + 2: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', + 3: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', + 4: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', + 5: 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', +} +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 1 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 2 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 3 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 4 +DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 5 +ENUM_DP_DPHY_SYM32_TP_PRBS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ENUM_DP_DPHY_SYM32_TP_SELECT' +ENUM_DP_DPHY_SYM32_TP_SELECT__enumvalues = { + 0: 'DP_DPHY_SYM32_TP_SELECT_TPS1', + 1: 'DP_DPHY_SYM32_TP_SELECT_TPS2', + 2: 'DP_DPHY_SYM32_TP_SELECT_PRBS', + 3: 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', + 4: 'DP_DPHY_SYM32_TP_SELECT_SQUARE', +} +DP_DPHY_SYM32_TP_SELECT_TPS1 = 0 +DP_DPHY_SYM32_TP_SELECT_TPS2 = 1 +DP_DPHY_SYM32_TP_SELECT_PRBS = 2 +DP_DPHY_SYM32_TP_SELECT_CUSTOM = 3 +DP_DPHY_SYM32_TP_SELECT_SQUARE = 4 +ENUM_DP_DPHY_SYM32_TP_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'APG_AUDIO_CRC_CONTROL_CH_SEL' +APG_AUDIO_CRC_CONTROL_CH_SEL__enumvalues = { + 0: 'APG_AUDIO_CRC_CH0_SIG', + 1: 'APG_AUDIO_CRC_CH1_SIG', + 2: 'APG_AUDIO_CRC_CH2_SIG', + 3: 'APG_AUDIO_CRC_CH3_SIG', + 4: 'APG_AUDIO_CRC_CH4_SIG', + 5: 'APG_AUDIO_CRC_CH5_SIG', + 6: 'APG_AUDIO_CRC_CH6_SIG', + 7: 'APG_AUDIO_CRC_CH7_SIG', + 8: 'APG_AUDIO_CRC_RESERVED_8', + 9: 'APG_AUDIO_CRC_RESERVED_9', + 10: 'APG_AUDIO_CRC_RESERVED_10', + 11: 'APG_AUDIO_CRC_RESERVED_11', + 12: 'APG_AUDIO_CRC_RESERVED_12', + 13: 'APG_AUDIO_CRC_RESERVED_13', + 14: 'APG_AUDIO_CRC_RESERVED_14', + 15: 'APG_AUDIO_CRC_RESERVED_15', +} +APG_AUDIO_CRC_CH0_SIG = 0 +APG_AUDIO_CRC_CH1_SIG = 1 +APG_AUDIO_CRC_CH2_SIG = 2 +APG_AUDIO_CRC_CH3_SIG = 3 +APG_AUDIO_CRC_CH4_SIG = 4 +APG_AUDIO_CRC_CH5_SIG = 5 +APG_AUDIO_CRC_CH6_SIG = 6 +APG_AUDIO_CRC_CH7_SIG = 7 +APG_AUDIO_CRC_RESERVED_8 = 8 +APG_AUDIO_CRC_RESERVED_9 = 9 +APG_AUDIO_CRC_RESERVED_10 = 10 +APG_AUDIO_CRC_RESERVED_11 = 11 +APG_AUDIO_CRC_RESERVED_12 = 12 +APG_AUDIO_CRC_RESERVED_13 = 13 +APG_AUDIO_CRC_RESERVED_14 = 14 +APG_AUDIO_CRC_RESERVED_15 = 15 +APG_AUDIO_CRC_CONTROL_CH_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_AUDIO_CRC_CONTROL_CONT' +APG_AUDIO_CRC_CONTROL_CONT__enumvalues = { + 0: 'APG_AUDIO_CRC_ONESHOT', + 1: 'APG_AUDIO_CRC_CONTINUOUS', +} +APG_AUDIO_CRC_ONESHOT = 0 +APG_AUDIO_CRC_CONTINUOUS = 1 +APG_AUDIO_CRC_CONTROL_CONT = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_ACP_TYPE' +APG_DBG_ACP_TYPE__enumvalues = { + 0: 'APG_ACP_TYPE_GENERIC_AUDIO', + 1: 'APG_ACP_TYPE_ICE60958_AUDIO', + 2: 'APG_ACP_TYPE_DVD_AUDIO', + 3: 'APG_ACP_TYPE_SUPER_AUDIO_CD', +} +APG_ACP_TYPE_GENERIC_AUDIO = 0 +APG_ACP_TYPE_ICE60958_AUDIO = 1 +APG_ACP_TYPE_DVD_AUDIO = 2 +APG_ACP_TYPE_SUPER_AUDIO_CD = 3 +APG_DBG_ACP_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_AUDIO_DTO_BASE' +APG_DBG_AUDIO_DTO_BASE__enumvalues = { + 0: 'BASE_RATE_48KHZ', + 1: 'BASE_RATE_44P1KHZ', +} +BASE_RATE_48KHZ = 0 +BASE_RATE_44P1KHZ = 1 +APG_DBG_AUDIO_DTO_BASE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_AUDIO_DTO_DIV' +APG_DBG_AUDIO_DTO_DIV__enumvalues = { + 0: 'DIVISOR_BY1', + 1: 'DIVISOR_BY2_RESERVED', + 2: 'DIVISOR_BY3', + 3: 'DIVISOR_BY4_RESERVED', + 4: 'DIVISOR_BY5_RESERVED', + 5: 'DIVISOR_BY6_RESERVED', + 6: 'DIVISOR_BY7_RESERVED', + 7: 'DIVISOR_BY8_RESERVED', +} +DIVISOR_BY1 = 0 +DIVISOR_BY2_RESERVED = 1 +DIVISOR_BY3 = 2 +DIVISOR_BY4_RESERVED = 3 +DIVISOR_BY5_RESERVED = 4 +DIVISOR_BY6_RESERVED = 5 +DIVISOR_BY7_RESERVED = 6 +DIVISOR_BY8_RESERVED = 7 +APG_DBG_AUDIO_DTO_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_AUDIO_DTO_MULTI' +APG_DBG_AUDIO_DTO_MULTI__enumvalues = { + 0: 'MULTIPLE_BY1', + 1: 'MULTIPLE_BY2', + 2: 'MULTIPLE_BY3_RESERVED', + 3: 'MULTIPLE_BY4', + 4: 'MULTIPLE_RESERVED', +} +MULTIPLE_BY1 = 0 +MULTIPLE_BY2 = 1 +MULTIPLE_BY3_RESERVED = 2 +MULTIPLE_BY4 = 3 +MULTIPLE_RESERVED = 4 +APG_DBG_AUDIO_DTO_MULTI = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DBG_MUX_SEL' +APG_DBG_MUX_SEL__enumvalues = { + 0: 'APG_FUNCTIONAL_MODE', + 1: 'APG_DEBUG_AUDIO_MODE', +} +APG_FUNCTIONAL_MODE = 0 +APG_DEBUG_AUDIO_MODE = 1 +APG_DBG_MUX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE' +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__enumvalues = { + 0: 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', + 1: 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', +} +APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0 +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 1 +APG_DP_ASP_CHANNEL_COUNT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_MEM_POWER_STATE' +APG_MEM_POWER_STATE__enumvalues = { + 0: 'APG_MEM_POWER_STATE_ON', + 1: 'APG_MEM_POWER_STATE_LS', + 2: 'APG_MEM_POWER_STATE_DS', + 3: 'APG_MEM_POWER_STATE_SD', +} +APG_MEM_POWER_STATE_ON = 0 +APG_MEM_POWER_STATE_LS = 1 +APG_MEM_POWER_STATE_DS = 2 +APG_MEM_POWER_STATE_SD = 3 +APG_MEM_POWER_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_MEM_PWR_DIS_CTRL' +APG_MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'APG_MEM_ENABLE_MEM_PWR_CTRL', + 1: 'APG_MEM_DISABLE_MEM_PWR_CTRL', +} +APG_MEM_ENABLE_MEM_PWR_CTRL = 0 +APG_MEM_DISABLE_MEM_PWR_CTRL = 1 +APG_MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_MEM_PWR_FORCE_CTRL' +APG_MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'APG_MEM_NO_FORCE_REQUEST', + 1: 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', +} +APG_MEM_NO_FORCE_REQUEST = 0 +APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 1 +APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 2 +APG_MEM_FORCE_SHUT_DOWN_REQUEST = 3 +APG_MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'APG_PACKET_CONTROL_ACP_SOURCE' +APG_PACKET_CONTROL_ACP_SOURCE__enumvalues = { + 0: 'APG_ACP_SOURCE_NO_OVERRIDE', + 1: 'APG_ACP_OVERRIDE', +} +APG_ACP_SOURCE_NO_OVERRIDE = 0 +APG_ACP_OVERRIDE = 1 +APG_PACKET_CONTROL_ACP_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE' +APG_PACKET_CONTROL_AUDIO_INFO_SOURCE__enumvalues = { + 0: 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', + 1: 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', +} +APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0 +APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 1 +APG_PACKET_CONTROL_AUDIO_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'APG_RAMP_CONTROL_SIGN' +APG_RAMP_CONTROL_SIGN__enumvalues = { + 0: 'APG_RAMP_SIGNED', + 1: 'APG_RAMP_UNSIGNED', +} +APG_RAMP_SIGNED = 0 +APG_RAMP_UNSIGNED = 1 +APG_RAMP_CONTROL_SIGN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL' +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL__enumvalues = { + 0: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 1: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 2: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 3: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 4: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 5: 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', +} +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 1 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 2 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 3 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 4 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 5 +DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL' +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL__enumvalues = { + 0: 'DCIO_TEST_CLK_SEL_DISPCLK', + 1: 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', + 2: 'DCIO_TEST_CLK_SEL_SOCCLK', +} +DCIO_TEST_CLK_SEL_DISPCLK = 0 +DCIO_TEST_CLK_SEL_GATED_DISPCLK = 1 +DCIO_TEST_CLK_SEL_SOCCLK = 2 +DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS' +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS__enumvalues = { + 0: 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 1: 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', +} +DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0 +DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 1 +DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DBG_ASYNC_4BIT_SEL' +DCIO_DBG_ASYNC_4BIT_SEL__enumvalues = { + 0: 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', + 1: 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', + 2: 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', + 3: 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', + 4: 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', + 5: 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', + 6: 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', + 7: 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', +} +DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0 +DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 1 +DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 2 +DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 3 +DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 4 +DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 5 +DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 6 +DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 7 +DCIO_DBG_ASYNC_4BIT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DBG_ASYNC_BLOCK_SEL' +DCIO_DBG_ASYNC_BLOCK_SEL__enumvalues = { + 0: 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', + 1: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', + 2: 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', + 3: 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', +} +DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0 +DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 1 +DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 2 +DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 3 +DCIO_DBG_ASYNC_BLOCK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DCRXPHY_SOFT_RESET' +DCIO_DCRXPHY_SOFT_RESET__enumvalues = { + 0: 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', + 1: 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', +} +DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0 +DCIO_DCRXPHY_SOFT_RESET_ASSERT = 1 +DCIO_DCRXPHY_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICA_SEL' +DCIO_DC_GENERICA_SEL__enumvalues = { + 1: 'DCIO_GENERICA_SEL_STEREOSYNC', + 10: 'DCIO_GENERICA_SEL_GENERICA_DCCG', + 11: 'DCIO_GENERICA_SEL_SYNCEN', +} +DCIO_GENERICA_SEL_STEREOSYNC = 1 +DCIO_GENERICA_SEL_GENERICA_DCCG = 10 +DCIO_GENERICA_SEL_SYNCEN = 11 +DCIO_DC_GENERICA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERICB_SEL' +DCIO_DC_GENERICB_SEL__enumvalues = { + 1: 'DCIO_GENERICB_SEL_STEREOSYNC', + 10: 'DCIO_GENERICB_SEL_GENERICB_DCCG', + 11: 'DCIO_GENERICB_SEL_SYNCEN', +} +DCIO_GENERICB_SEL_STEREOSYNC = 1 +DCIO_GENERICB_SEL_GENERICB_DCCG = 10 +DCIO_GENERICB_SEL_SYNCEN = 11 +DCIO_DC_GENERICB_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 1: 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 2: 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 3: 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 4: 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 5: 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 6: 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', +} +DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0 +DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 1 +DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 2 +DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 3 +DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 4 +DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 5 +DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_CLK', +} +DCIO_UNIPHYA_FBDIV_CLK = 0 +DCIO_UNIPHYB_FBDIV_CLK = 1 +DCIO_UNIPHYC_FBDIV_CLK = 2 +DCIO_UNIPHYD_FBDIV_CLK = 3 +DCIO_UNIPHYE_FBDIV_CLK = 4 +DCIO_UNIPHYF_FBDIV_CLK = 5 +DCIO_UNIPHYG_FBDIV_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 1: 'DCIO_UNIPHYB_FBDIV_SSC_CLK', + 2: 'DCIO_UNIPHYC_FBDIV_SSC_CLK', + 3: 'DCIO_UNIPHYD_FBDIV_SSC_CLK', + 4: 'DCIO_UNIPHYE_FBDIV_SSC_CLK', + 5: 'DCIO_UNIPHYF_FBDIV_SSC_CLK', + 6: 'DCIO_UNIPHYG_FBDIV_SSC_CLK', +} +DCIO_UNIPHYA_FBDIV_SSC_CLK = 0 +DCIO_UNIPHYB_FBDIV_SSC_CLK = 1 +DCIO_UNIPHYC_FBDIV_SSC_CLK = 2 +DCIO_UNIPHYD_FBDIV_SSC_CLK = 3 +DCIO_UNIPHYE_FBDIV_SSC_CLK = 4 +DCIO_UNIPHYF_FBDIV_SSC_CLK = 5 +DCIO_UNIPHYG_FBDIV_SSC_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL' +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL__enumvalues = { + 0: 'DCIO_UNIPHYA_TEST_REFDIV_CLK', + 1: 'DCIO_UNIPHYB_TEST_REFDIV_CLK', + 2: 'DCIO_UNIPHYC_TEST_REFDIV_CLK', + 3: 'DCIO_UNIPHYD_TEST_REFDIV_CLK', + 4: 'DCIO_UNIPHYE_TEST_REFDIV_CLK', + 5: 'DCIO_UNIPHYF_TEST_REFDIV_CLK', + 6: 'DCIO_UNIPHYG_TEST_REFDIV_CLK', +} +DCIO_UNIPHYA_TEST_REFDIV_CLK = 0 +DCIO_UNIPHYB_TEST_REFDIV_CLK = 1 +DCIO_UNIPHYC_TEST_REFDIV_CLK = 2 +DCIO_UNIPHYD_TEST_REFDIV_CLK = 3 +DCIO_UNIPHYE_TEST_REFDIV_CLK = 4 +DCIO_UNIPHYF_TEST_REFDIV_CLK = 5 +DCIO_UNIPHYG_TEST_REFDIV_CLK = 6 +DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE' +DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE__enumvalues = { + 0: 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', + 1: 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', +} +DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0 +DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 1 +DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_READ_SELECT' +DCIO_DC_GPU_TIMER_READ_SELECT__enumvalues = { + 0: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 1: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 2: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 3: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 4: 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 5: 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', +} +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 1 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 2 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 3 +DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 4 +DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 5 +DCIO_DC_GPU_TIMER_READ_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_GPU_TIMER_START_POSITION' +DCIO_DC_GPU_TIMER_START_POSITION__enumvalues = { + 0: 'DCIO_GPU_TIMER_START_0_END_27', + 1: 'DCIO_GPU_TIMER_START_1_END_28', + 2: 'DCIO_GPU_TIMER_START_2_END_29', + 3: 'DCIO_GPU_TIMER_START_3_END_30', + 4: 'DCIO_GPU_TIMER_START_4_END_31', + 5: 'DCIO_GPU_TIMER_START_6_END_33', + 6: 'DCIO_GPU_TIMER_START_8_END_35', + 7: 'DCIO_GPU_TIMER_START_10_END_37', +} +DCIO_GPU_TIMER_START_0_END_27 = 0 +DCIO_GPU_TIMER_START_1_END_28 = 1 +DCIO_GPU_TIMER_START_2_END_29 = 2 +DCIO_GPU_TIMER_START_3_END_30 = 3 +DCIO_GPU_TIMER_START_4_END_31 = 4 +DCIO_GPU_TIMER_START_6_END_33 = 5 +DCIO_GPU_TIMER_START_8_END_35 = 6 +DCIO_GPU_TIMER_START_10_END_37 = 7 +DCIO_DC_GPU_TIMER_START_POSITION = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 1: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 2: 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 3: 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', +} +DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 1 +DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 2 +DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 3 +DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL' +DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL__enumvalues = { + 0: 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', + 1: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', + 2: 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', + 3: 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', +} +DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0 +DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 1 +DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 2 +DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 3 +DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DIO_EXT_VSYNC_MASK' +DCIO_DIO_EXT_VSYNC_MASK__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MASK_NONE', + 1: 'DCIO_EXT_VSYNC_MASK_PIPE0', + 2: 'DCIO_EXT_VSYNC_MASK_PIPE1', + 3: 'DCIO_EXT_VSYNC_MASK_PIPE2', + 4: 'DCIO_EXT_VSYNC_MASK_PIPE3', + 5: 'DCIO_EXT_VSYNC_MASK_PIPE4', + 6: 'DCIO_EXT_VSYNC_MASK_PIPE5', + 7: 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', +} +DCIO_EXT_VSYNC_MASK_NONE = 0 +DCIO_EXT_VSYNC_MASK_PIPE0 = 1 +DCIO_EXT_VSYNC_MASK_PIPE1 = 2 +DCIO_EXT_VSYNC_MASK_PIPE2 = 3 +DCIO_EXT_VSYNC_MASK_PIPE3 = 4 +DCIO_EXT_VSYNC_MASK_PIPE4 = 5 +DCIO_EXT_VSYNC_MASK_PIPE5 = 6 +DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 7 +DCIO_DIO_EXT_VSYNC_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DIO_OTG_EXT_VSYNC_MUX' +DCIO_DIO_OTG_EXT_VSYNC_MUX__enumvalues = { + 0: 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 1: 'DCIO_EXT_VSYNC_MUX_OTG0', + 2: 'DCIO_EXT_VSYNC_MUX_OTG1', + 3: 'DCIO_EXT_VSYNC_MUX_OTG2', + 4: 'DCIO_EXT_VSYNC_MUX_OTG3', + 5: 'DCIO_EXT_VSYNC_MUX_OTG4', + 6: 'DCIO_EXT_VSYNC_MUX_OTG5', + 7: 'DCIO_EXT_VSYNC_MUX_GENERICB', +} +DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0 +DCIO_EXT_VSYNC_MUX_OTG0 = 1 +DCIO_EXT_VSYNC_MUX_OTG1 = 2 +DCIO_EXT_VSYNC_MUX_OTG2 = 3 +DCIO_EXT_VSYNC_MUX_OTG3 = 4 +DCIO_EXT_VSYNC_MUX_OTG4 = 5 +DCIO_EXT_VSYNC_MUX_OTG5 = 6 +DCIO_EXT_VSYNC_MUX_GENERICB = 7 +DCIO_DIO_OTG_EXT_VSYNC_MUX = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_MASK' +DCIO_DPCS_INTERRUPT_MASK__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_DISABLE', + 1: 'DCIO_DPCS_INTERRUPT_ENABLE', +} +DCIO_DPCS_INTERRUPT_DISABLE = 0 +DCIO_DPCS_INTERRUPT_ENABLE = 1 +DCIO_DPCS_INTERRUPT_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DPCS_INTERRUPT_TYPE' +DCIO_DPCS_INTERRUPT_TYPE__enumvalues = { + 0: 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 1: 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', +} +DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0 +DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 1 +DCIO_DPCS_INTERRUPT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_DSYNC_SOFT_RESET' +DCIO_DSYNC_SOFT_RESET__enumvalues = { + 0: 'DCIO_DSYNC_SOFT_RESET_DEASSERT', + 1: 'DCIO_DSYNC_SOFT_RESET_ASSERT', +} +DCIO_DSYNC_SOFT_RESET_DEASSERT = 0 +DCIO_DSYNC_SOFT_RESET_ASSERT = 1 +DCIO_DSYNC_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_CLK_GSL_MASK' +DCIO_GENLK_CLK_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_CLK_GSL_MASK_NO', + 1: 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_CLK_GSL_MASK_STEREO', +} +DCIO_GENLK_CLK_GSL_MASK_NO = 0 +DCIO_GENLK_CLK_GSL_MASK_TIMING = 1 +DCIO_GENLK_CLK_GSL_MASK_STEREO = 2 +DCIO_GENLK_CLK_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GENLK_VSYNC_GSL_MASK' +DCIO_GENLK_VSYNC_GSL_MASK__enumvalues = { + 0: 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 1: 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 2: 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', +} +DCIO_GENLK_VSYNC_GSL_MASK_NO = 0 +DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 1 +DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 2 +DCIO_GENLK_VSYNC_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_GSL_SEL' +DCIO_GSL_SEL__enumvalues = { + 0: 'DCIO_GSL_SEL_GROUP_0', + 1: 'DCIO_GSL_SEL_GROUP_1', + 2: 'DCIO_GSL_SEL_GROUP_2', +} +DCIO_GSL_SEL_GROUP_0 = 0 +DCIO_GSL_SEL_GROUP_1 = 1 +DCIO_GSL_SEL_GROUP_2 = 2 +DCIO_GSL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_PHY_HPO_ENC_SRC_SEL' +DCIO_PHY_HPO_ENC_SRC_SEL__enumvalues = { + 0: 'HPO_SRC0', + 1: 'HPO_SRC_RESERVED', +} +HPO_SRC0 = 0 +HPO_SRC_RESERVED = 1 +DCIO_PHY_HPO_ENC_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_A_GSL_MASK' +DCIO_SWAPLOCK_A_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_A_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_A_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_A_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_SWAPLOCK_B_GSL_MASK' +DCIO_SWAPLOCK_B_GSL_MASK__enumvalues = { + 0: 'DCIO_SWAPLOCK_B_GSL_MASK_NO', + 1: 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', + 2: 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', +} +DCIO_SWAPLOCK_B_GSL_MASK_NO = 0 +DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 1 +DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 2 +DCIO_SWAPLOCK_B_GSL_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE' +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 1: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 2: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 3: 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', +} +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 1 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 2 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 3 +DCIO_UNIPHY_CHANNEL_XBAR_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_IMPCAL_SEL' +DCIO_UNIPHY_IMPCAL_SEL__enumvalues = { + 0: 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 1: 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', +} +DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0 +DCIO_UNIPHY_IMPCAL_SEL_BINARY = 1 +DCIO_UNIPHY_IMPCAL_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT' +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT__enumvalues = { + 0: 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 1: 'DCIO_UNIPHY_CHANNEL_INVERTED', +} +DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0 +DCIO_UNIPHY_CHANNEL_INVERTED = 1 +DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK' +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK__enumvalues = { + 0: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', + 1: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 2: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 3: 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', +} +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 1 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 2 +DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 3 +DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_ALL_PWR_OK' +DCIOCHIP_AUX_ALL_PWR_OK__enumvalues = { + 0: 'DCIOCHIP_AUX_ALL_PWR_OK_0', + 1: 'DCIOCHIP_AUX_ALL_PWR_OK_1', +} +DCIOCHIP_AUX_ALL_PWR_OK_0 = 0 +DCIOCHIP_AUX_ALL_PWR_OK_1 = 1 +DCIOCHIP_AUX_ALL_PWR_OK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL0P9' +DCIOCHIP_AUX_CSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_CSEL_DEC0P9', +} +DCIOCHIP_AUX_CSEL_DEC1P0 = 0 +DCIOCHIP_AUX_CSEL_DEC0P9 = 1 +DCIOCHIP_AUX_CSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_CSEL1P1' +DCIOCHIP_AUX_CSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_CSEL_INC1P0', + 1: 'DCIOCHIP_AUX_CSEL_INC1P1', +} +DCIOCHIP_AUX_CSEL_INC1P0 = 0 +DCIOCHIP_AUX_CSEL_INC1P1 = 1 +DCIOCHIP_AUX_CSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_FALLSLEWSEL' +DCIOCHIP_AUX_FALLSLEWSEL__enumvalues = { + 0: 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 1: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 2: 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', + 3: 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', +} +DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 1 +DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 2 +DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 3 +DCIOCHIP_AUX_FALLSLEWSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_HYS_TUNE' +DCIOCHIP_AUX_HYS_TUNE__enumvalues = { + 0: 'DCIOCHIP_AUX_HYS_TUNE_0', + 1: 'DCIOCHIP_AUX_HYS_TUNE_1', + 2: 'DCIOCHIP_AUX_HYS_TUNE_2', + 3: 'DCIOCHIP_AUX_HYS_TUNE_3', +} +DCIOCHIP_AUX_HYS_TUNE_0 = 0 +DCIOCHIP_AUX_HYS_TUNE_1 = 1 +DCIOCHIP_AUX_HYS_TUNE_2 = 2 +DCIOCHIP_AUX_HYS_TUNE_3 = 3 +DCIOCHIP_AUX_HYS_TUNE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RECEIVER_SEL' +DCIOCHIP_AUX_RECEIVER_SEL__enumvalues = { + 0: 'DCIOCHIP_AUX_RECEIVER_SEL_0', + 1: 'DCIOCHIP_AUX_RECEIVER_SEL_1', + 2: 'DCIOCHIP_AUX_RECEIVER_SEL_2', + 3: 'DCIOCHIP_AUX_RECEIVER_SEL_3', +} +DCIOCHIP_AUX_RECEIVER_SEL_0 = 0 +DCIOCHIP_AUX_RECEIVER_SEL_1 = 1 +DCIOCHIP_AUX_RECEIVER_SEL_2 = 2 +DCIOCHIP_AUX_RECEIVER_SEL_3 = 3 +DCIOCHIP_AUX_RECEIVER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL0P9' +DCIOCHIP_AUX_RSEL0P9__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_DEC1P0', + 1: 'DCIOCHIP_AUX_RSEL_DEC0P9', +} +DCIOCHIP_AUX_RSEL_DEC1P0 = 0 +DCIOCHIP_AUX_RSEL_DEC0P9 = 1 +DCIOCHIP_AUX_RSEL0P9 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_RSEL1P1' +DCIOCHIP_AUX_RSEL1P1__enumvalues = { + 0: 'DCIOCHIP_AUX_RSEL_INC1P0', + 1: 'DCIOCHIP_AUX_RSEL_INC1P1', +} +DCIOCHIP_AUX_RSEL_INC1P0 = 0 +DCIOCHIP_AUX_RSEL_INC1P1 = 1 +DCIOCHIP_AUX_RSEL1P1 = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_SPIKESEL' +DCIOCHIP_AUX_SPIKESEL__enumvalues = { + 0: 'DCIOCHIP_AUX_SPIKESEL_50NS', + 1: 'DCIOCHIP_AUX_SPIKESEL_10NS', +} +DCIOCHIP_AUX_SPIKESEL_50NS = 0 +DCIOCHIP_AUX_SPIKESEL_10NS = 1 +DCIOCHIP_AUX_SPIKESEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_AUX_VOD_TUNE' +DCIOCHIP_AUX_VOD_TUNE__enumvalues = { + 0: 'DCIOCHIP_AUX_VOD_TUNE_0', + 1: 'DCIOCHIP_AUX_VOD_TUNE_1', + 2: 'DCIOCHIP_AUX_VOD_TUNE_2', + 3: 'DCIOCHIP_AUX_VOD_TUNE_3', +} +DCIOCHIP_AUX_VOD_TUNE_0 = 0 +DCIOCHIP_AUX_VOD_TUNE_1 = 1 +DCIOCHIP_AUX_VOD_TUNE_2 = 2 +DCIOCHIP_AUX_VOD_TUNE_3 = 3 +DCIOCHIP_AUX_VOD_TUNE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_GPIO_MASK_EN' +DCIOCHIP_GPIO_MASK_EN__enumvalues = { + 0: 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 1: 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', +} +DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0 +DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 1 +DCIOCHIP_GPIO_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_HPD_SEL' +DCIOCHIP_HPD_SEL__enumvalues = { + 0: 'DCIOCHIP_HPD_SEL_ASYNC', + 1: 'DCIOCHIP_HPD_SEL_CLOCKED', +} +DCIOCHIP_HPD_SEL_ASYNC = 0 +DCIOCHIP_HPD_SEL_CLOCKED = 1 +DCIOCHIP_HPD_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_COMPSEL' +DCIOCHIP_I2C_COMPSEL__enumvalues = { + 0: 'DCIOCHIP_I2C_REC_SCHMIT', + 1: 'DCIOCHIP_I2C_REC_COMPARATOR', +} +DCIOCHIP_I2C_REC_SCHMIT = 0 +DCIOCHIP_I2C_REC_COMPARATOR = 1 +DCIOCHIP_I2C_COMPSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_FALLSLEWSEL' +DCIOCHIP_I2C_FALLSLEWSEL__enumvalues = { + 0: 'DCIOCHIP_I2C_FALLSLEWSEL_00', + 1: 'DCIOCHIP_I2C_FALLSLEWSEL_01', + 2: 'DCIOCHIP_I2C_FALLSLEWSEL_10', + 3: 'DCIOCHIP_I2C_FALLSLEWSEL_11', +} +DCIOCHIP_I2C_FALLSLEWSEL_00 = 0 +DCIOCHIP_I2C_FALLSLEWSEL_01 = 1 +DCIOCHIP_I2C_FALLSLEWSEL_10 = 2 +DCIOCHIP_I2C_FALLSLEWSEL_11 = 3 +DCIOCHIP_I2C_FALLSLEWSEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_RECEIVER_SEL' +DCIOCHIP_I2C_RECEIVER_SEL__enumvalues = { + 0: 'DCIOCHIP_I2C_RECEIVER_SEL_0', + 1: 'DCIOCHIP_I2C_RECEIVER_SEL_1', + 2: 'DCIOCHIP_I2C_RECEIVER_SEL_2', + 3: 'DCIOCHIP_I2C_RECEIVER_SEL_3', +} +DCIOCHIP_I2C_RECEIVER_SEL_0 = 0 +DCIOCHIP_I2C_RECEIVER_SEL_1 = 1 +DCIOCHIP_I2C_RECEIVER_SEL_2 = 2 +DCIOCHIP_I2C_RECEIVER_SEL_3 = 3 +DCIOCHIP_I2C_RECEIVER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_I2C_VPH_1V2_EN' +DCIOCHIP_I2C_VPH_1V2_EN__enumvalues = { + 0: 'DCIOCHIP_I2C_VPH_1V2_EN_0', + 1: 'DCIOCHIP_I2C_VPH_1V2_EN_1', +} +DCIOCHIP_I2C_VPH_1V2_EN_0 = 0 +DCIOCHIP_I2C_VPH_1V2_EN_1 = 1 +DCIOCHIP_I2C_VPH_1V2_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_INVERT' +DCIOCHIP_INVERT__enumvalues = { + 0: 'DCIOCHIP_POL_NON_INVERT', + 1: 'DCIOCHIP_POL_INVERT', +} +DCIOCHIP_POL_NON_INVERT = 0 +DCIOCHIP_POL_INVERT = 1 +DCIOCHIP_INVERT = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_MASK' +DCIOCHIP_MASK__enumvalues = { + 0: 'DCIOCHIP_MASK_DISABLE', + 1: 'DCIOCHIP_MASK_ENABLE', +} +DCIOCHIP_MASK_DISABLE = 0 +DCIOCHIP_MASK_ENABLE = 1 +DCIOCHIP_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PAD_MODE' +DCIOCHIP_PAD_MODE__enumvalues = { + 0: 'DCIOCHIP_PAD_MODE_DDC', + 1: 'DCIOCHIP_PAD_MODE_DP', +} +DCIOCHIP_PAD_MODE_DDC = 0 +DCIOCHIP_PAD_MODE_DP = 1 +DCIOCHIP_PAD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_PD_EN' +DCIOCHIP_PD_EN__enumvalues = { + 0: 'DCIOCHIP_PD_EN_NOTALLOW', + 1: 'DCIOCHIP_PD_EN_ALLOW', +} +DCIOCHIP_PD_EN_NOTALLOW = 0 +DCIOCHIP_PD_EN_ALLOW = 1 +DCIOCHIP_PD_EN = ctypes.c_uint32 # enum + +# values for enumeration 'DCIOCHIP_REF_27_SRC_SEL' +DCIOCHIP_REF_27_SRC_SEL__enumvalues = { + 0: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', + 1: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 2: 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 3: 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', +} +DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 1 +DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 2 +DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 3 +DCIOCHIP_REF_27_SRC_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE' +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE__enumvalues = { + 0: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 1: 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', +} +PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0 +PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 1 +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN' +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', + 1: 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', +} +PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0 +PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 1 +PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT' +PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT__enumvalues = { + 0: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', + 1: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', + 2: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', + 3: 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', +} +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0 +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 1 +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 2 +PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 3 +PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN' +PWRSEQ_BL_PWM_CNTL_BL_PWM_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_DISABLE', + 1: 'PWRSEQ_BL_PWM_ENABLE', +} +PWRSEQ_BL_PWM_DISABLE = 0 +PWRSEQ_BL_PWM_ENABLE = 1 +PWRSEQ_BL_PWM_CNTL_BL_PWM_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN' +PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', + 1: 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', +} +PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0 +PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 1 +PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN' +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 1: 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', +} +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0 +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 1 +PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN' +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 1: 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', +} +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0 +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 1 +PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_REG_LOCK' +PWRSEQ_BL_PWM_GRP1_REG_LOCK__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', + 1: 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', +} +PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0 +PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 1 +PWRSEQ_BL_PWM_GRP1_REG_LOCK = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START' +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START__enumvalues = { + 0: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 1: 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', +} +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0 +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 1 +PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_GPIO_MASK_EN' +PWRSEQ_GPIO_MASK_EN__enumvalues = { + 0: 'PWRSEQ_GPIO_MASK_EN_HARDWARE', + 1: 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', +} +PWRSEQ_GPIO_MASK_EN_HARDWARE = 0 +PWRSEQ_GPIO_MASK_EN_SOFTWARE = 1 +PWRSEQ_GPIO_MASK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON__enumvalues = { + 0: 'PWRSEQ_PANEL_BLON_OFF', + 1: 'PWRSEQ_PANEL_BLON_ON', +} +PWRSEQ_PANEL_BLON_OFF = 0 +PWRSEQ_PANEL_BLON_ON = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL__enumvalues = { + 0: 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', + 1: 'PWRSEQ_PANEL_BLON_POL_INVERT', +} +PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0 +PWRSEQ_PANEL_BLON_POL_INVERT = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON__enumvalues = { + 0: 'PWRSEQ_PANEL_DIGON_OFF', + 1: 'PWRSEQ_PANEL_DIGON_ON', +} +PWRSEQ_PANEL_DIGON_OFF = 0 +PWRSEQ_PANEL_DIGON_ON = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL__enumvalues = { + 0: 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', + 1: 'PWRSEQ_PANEL_DIGON_POL_INVERT', +} +PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0 +PWRSEQ_PANEL_DIGON_POL_INVERT = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL' +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL__enumvalues = { + 0: 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', + 1: 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', +} +PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0 +PWRSEQ_PANEL_SYNCEN_POL_INVERT = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE' +PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE__enumvalues = { + 0: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', + 1: 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', +} +PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0 +PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 1 +PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN' +PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN__enumvalues = { + 0: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', + 1: 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', +} +PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0 +PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 1 +PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_CORB_SIZE' +AZ_CORB_SIZE__enumvalues = { + 0: 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_CORB_SIZE_256ENTRIES', + 3: 'AZ_CORB_SIZE_RESERVED', +} +AZ_CORB_SIZE_2ENTRIES_RESERVED = 0 +AZ_CORB_SIZE_16ENTRIES_RESERVED = 1 +AZ_CORB_SIZE_256ENTRIES = 2 +AZ_CORB_SIZE_RESERVED = 3 +AZ_CORB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_GLOBAL_CAPABILITIES' +AZ_GLOBAL_CAPABILITIES__enumvalues = { + 0: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 1: 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', +} +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0 +AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 1 +AZ_GLOBAL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_SIZE' +AZ_RIRB_SIZE__enumvalues = { + 0: 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', + 1: 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', + 2: 'AZ_RIRB_SIZE_256ENTRIES', + 3: 'AZ_RIRB_SIZE_UNDEFINED', +} +AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0 +AZ_RIRB_SIZE_16ENTRIES_RESERVED = 1 +AZ_RIRB_SIZE_256ENTRIES = 2 +AZ_RIRB_SIZE_UNDEFINED = 3 +AZ_RIRB_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_RIRB_WRITE_POINTER_RESET' +AZ_RIRB_WRITE_POINTER_RESET__enumvalues = { + 0: 'AZ_RIRB_WRITE_POINTER_NOT_RESET', + 1: 'AZ_RIRB_WRITE_POINTER_DO_RESET', +} +AZ_RIRB_WRITE_POINTER_NOT_RESET = 0 +AZ_RIRB_WRITE_POINTER_DO_RESET = 1 +AZ_RIRB_WRITE_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_STATE_CHANGE_STATUS' +AZ_STATE_CHANGE_STATUS__enumvalues = { + 0: 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 1: 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', +} +AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0 +AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 1 +AZ_STATE_CHANGE_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'CORB_READ_POINTER_RESET' +CORB_READ_POINTER_RESET__enumvalues = { + 0: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 1: 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', +} +CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0 +CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 1 +CORB_READ_POINTER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE' +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE__enumvalues = { + 0: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 1: 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', +} +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 1 +DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED' +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED__enumvalues = { + 0: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 1: 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', +} +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 1 +GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE' +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE__enumvalues = { + 0: 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', + 1: 'ACCEPT_UNSOLICITED_RESPONSE_ENABLE', +} +ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0 +ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 1 +GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_CONTROLLER_RESET' +GLOBAL_CONTROL_CONTROLLER_RESET__enumvalues = { + 0: 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 1: 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', +} +CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0 +CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 1 +GLOBAL_CONTROL_CONTROLLER_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_CONTROL_FLUSH_CONTROL' +GLOBAL_CONTROL_FLUSH_CONTROL__enumvalues = { + 0: 'FLUSH_CONTROL_FLUSH_NOT_STARTED', + 1: 'FLUSH_CONTROL_FLUSH_STARTED', +} +FLUSH_CONTROL_FLUSH_NOT_STARTED = 0 +FLUSH_CONTROL_FLUSH_STARTED = 1 +GLOBAL_CONTROL_FLUSH_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'GLOBAL_STATUS_FLUSH_STATUS' +GLOBAL_STATUS_FLUSH_STATUS__enumvalues = { + 0: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 1: 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', +} +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0 +GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 1 +GLOBAL_STATUS_FLUSH_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY = ctypes.c_uint32 # enum + +# values for enumeration 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID' +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID__enumvalues = { + 0: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 1: 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', +} +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 1 +IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL' +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL__enumvalues = { + 0: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 1: 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', +} +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 1 +RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_0_SYNCHRONIZATION' +STREAM_0_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_0_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_10_SYNCHRONIZATION' +STREAM_10_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_10_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_11_SYNCHRONIZATION' +STREAM_11_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_11_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_12_SYNCHRONIZATION' +STREAM_12_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_12_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_13_SYNCHRONIZATION' +STREAM_13_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_13_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_14_SYNCHRONIZATION' +STREAM_14_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_14_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_15_SYNCHRONIZATION' +STREAM_15_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_15_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_1_SYNCHRONIZATION' +STREAM_1_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_1_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_2_SYNCHRONIZATION' +STREAM_2_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_2_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_3_SYNCHRONIZATION' +STREAM_3_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 1: 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', +} +STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0 +STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 1 +STREAM_3_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_4_SYNCHRONIZATION' +STREAM_4_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_4_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_5_SYNCHRONIZATION' +STREAM_5_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_5_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_6_SYNCHRONIZATION' +STREAM_6_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_6_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_7_SYNCHRONIZATION' +STREAM_7_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_7_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_8_SYNCHRONIZATION' +STREAM_8_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_8_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'STREAM_9_SYNCHRONIZATION' +STREAM_9_SYNCHRONIZATION__enumvalues = { + 0: 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 1: 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', +} +STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0 +STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 1 +STREAM_9_SYNCHRONIZATION = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG' +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG__enumvalues = { + 0: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 1: 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', +} +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 1 +AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE' +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', + 2: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', + 3: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', + 4: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', + 5: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', + 6: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', + 7: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', + 8: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', + 9: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', + 10: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', + 11: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', + 12: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', + 13: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', + 14: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', + 15: 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', +} +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 1 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 2 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 3 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 4 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 5 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 6 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 7 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 8 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 9 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 10 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 11 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 12 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 13 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 14 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 15 +AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT' +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE' +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET' +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET__enumvalues = { + 0: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 1: 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', +} +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 1 +AZALIA_SOFT_RESET_REFCLK_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_DIS_CTRL' +MEM_PWR_DIS_CTRL__enumvalues = { + 0: 'ENABLE_MEM_PWR_CTRL', + 1: 'DISABLE_MEM_PWR_CTRL', +} +ENABLE_MEM_PWR_CTRL = 0 +DISABLE_MEM_PWR_CTRL = 1 +MEM_PWR_DIS_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL' +MEM_PWR_FORCE_CTRL__enumvalues = { + 0: 'NO_FORCE_REQUEST', + 1: 'FORCE_LIGHT_SLEEP_REQUEST', + 2: 'FORCE_DEEP_SLEEP_REQUEST', + 3: 'FORCE_SHUT_DOWN_REQUEST', +} +NO_FORCE_REQUEST = 0 +FORCE_LIGHT_SLEEP_REQUEST = 1 +FORCE_DEEP_SLEEP_REQUEST = 2 +FORCE_SHUT_DOWN_REQUEST = 3 +MEM_PWR_FORCE_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_FORCE_CTRL2' +MEM_PWR_FORCE_CTRL2__enumvalues = { + 0: 'NO_FORCE_REQ', + 1: 'FORCE_LIGHT_SLEEP_REQ', +} +NO_FORCE_REQ = 0 +FORCE_LIGHT_SLEEP_REQ = 1 +MEM_PWR_FORCE_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL' +MEM_PWR_SEL_CTRL__enumvalues = { + 0: 'DYNAMIC_SHUT_DOWN_ENABLE', + 1: 'DYNAMIC_DEEP_SLEEP_ENABLE', + 2: 'DYNAMIC_LIGHT_SLEEP_ENABLE', +} +DYNAMIC_SHUT_DOWN_ENABLE = 0 +DYNAMIC_DEEP_SLEEP_ENABLE = 1 +DYNAMIC_LIGHT_SLEEP_ENABLE = 2 +MEM_PWR_SEL_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'MEM_PWR_SEL_CTRL2' +MEM_PWR_SEL_CTRL2__enumvalues = { + 0: 'DYNAMIC_DEEP_SLEEP_EN', + 1: 'DYNAMIC_LIGHT_SLEEP_EN', +} +DYNAMIC_DEEP_SLEEP_EN = 0 +DYNAMIC_LIGHT_SLEEP_EN = 1 +MEM_PWR_SEL_CTRL2 = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY' +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY__enumvalues = { + 0: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 1: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 2: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 3: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 4: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 5: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 6: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 7: 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', +} +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 1 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 2 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 3 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 4 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 5 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 6 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 7 +CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 8 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN' +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', +} +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE' +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE__enumvalues = { + 0: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 1: 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', +} +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 1 +AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET' +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET__enumvalues = { + 0: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 1: 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', +} +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 1 +AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'AZ_LATENCY_COUNTER_CONTROL' +AZ_LATENCY_COUNTER_CONTROL__enumvalues = { + 0: 'AZ_LATENCY_COUNTER_NO_RESET', + 1: 'AZ_LATENCY_COUNTER_RESET_DONE', +} +AZ_LATENCY_COUNTER_NO_RESET = 0 +AZ_LATENCY_COUNTER_RESET_DONE = 1 +AZ_LATENCY_COUNTER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY' +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 1: 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', +} +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 1 +OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 8: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 9: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 10: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 11: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 12: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 13: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 14: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 15: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 8 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 9 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 10 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 11 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 12 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 13 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 14 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 15 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 5: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 6: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 7: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 5 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 6 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 7 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 2: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 3: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 4: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 2 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 3 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 4 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE = ctypes.c_uint32 # enum + +# values for enumeration 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE' +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE__enumvalues = { + 0: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 1: 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', +} +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 1 +OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE' +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', +} +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 1 +AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 1: 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', +} +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 1 +AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 9: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 8 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 2: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 3: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 4: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 5: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 6: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 7: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 8: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 9: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 2 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 3 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 4 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 5 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 6 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 7 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 8 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 9 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE = ctypes.c_uint32 # enum + +# values for enumeration 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED' +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED__enumvalues = { + 0: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 1: 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', +} +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 1 +AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_BITS_PER_COMPONENT_ENUM' +DSCC_BITS_PER_COMPONENT_ENUM__enumvalues = { + 8: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 10: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 12: 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', +} +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 +DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 +DSCC_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_DSC_VERSION_MAJOR_ENUM' +DSCC_DSC_VERSION_MAJOR_ENUM__enumvalues = { + 1: 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', +} +DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 1 +DSCC_DSC_VERSION_MAJOR_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_DSC_VERSION_MINOR_ENUM' +DSCC_DSC_VERSION_MINOR_ENUM__enumvalues = { + 1: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', + 2: 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', +} +DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 1 +DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 2 +DSCC_DSC_VERSION_MINOR_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_ENABLE_ENUM' +DSCC_ENABLE_ENUM__enumvalues = { + 0: 'DSCC_ENABLE_ENUM_DISABLED', + 1: 'DSCC_ENABLE_ENUM_ENABLED', +} +DSCC_ENABLE_ENUM_DISABLED = 0 +DSCC_ENABLE_ENUM_ENABLED = 1 +DSCC_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_ICH_RESET_ENUM' +DSCC_ICH_RESET_ENUM__enumvalues = { + 1: 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', + 2: 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', + 4: 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', + 8: 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', +} +DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 1 +DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 2 +DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 4 +DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 8 +DSCC_ICH_RESET_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_LINEBUF_DEPTH_ENUM' +DSCC_LINEBUF_DEPTH_ENUM__enumvalues = { + 8: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', + 9: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', + 10: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', + 11: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', + 12: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', + 13: 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', +} +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 8 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 9 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 10 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 11 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 12 +DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 13 +DSCC_LINEBUF_DEPTH_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_MEM_PWR_DIS_ENUM' +DSCC_MEM_PWR_DIS_ENUM__enumvalues = { + 0: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', + 1: 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', +} +DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0 +DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 1 +DSCC_MEM_PWR_DIS_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCC_MEM_PWR_FORCE_ENUM' +DSCC_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', + 1: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', + 2: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', + 3: 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', +} +DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 1 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 2 +DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 3 +DSCC_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'POWER_STATE_ENUM' +POWER_STATE_ENUM__enumvalues = { + 0: 'POWER_STATE_ENUM_ON', + 1: 'POWER_STATE_ENUM_LS', + 2: 'POWER_STATE_ENUM_DS', + 3: 'POWER_STATE_ENUM_SD', +} +POWER_STATE_ENUM_ON = 0 +POWER_STATE_ENUM_LS = 1 +POWER_STATE_ENUM_DS = 2 +POWER_STATE_ENUM_SD = 3 +POWER_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_BITS_PER_COMPONENT_ENUM' +DSCCIF_BITS_PER_COMPONENT_ENUM__enumvalues = { + 8: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 10: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 12: 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', +} +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 8 +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 10 +DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 12 +DSCCIF_BITS_PER_COMPONENT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_ENABLE_ENUM' +DSCCIF_ENABLE_ENUM__enumvalues = { + 0: 'DSCCIF_ENABLE_ENUM_DISABLED', + 1: 'DSCCIF_ENABLE_ENUM_ENABLED', +} +DSCCIF_ENABLE_ENUM_DISABLED = 0 +DSCCIF_ENABLE_ENUM_ENABLED = 1 +DSCCIF_ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM' +DSCCIF_INPUT_PIXEL_FORMAT_ENUM__enumvalues = { + 0: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', + 1: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', + 2: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', + 3: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', + 4: 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', +} +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 1 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 2 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 3 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 4 +DSCCIF_INPUT_PIXEL_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'CLOCK_GATING_DISABLE_ENUM' +CLOCK_GATING_DISABLE_ENUM__enumvalues = { + 0: 'CLOCK_GATING_DISABLE_ENUM_ENABLED', + 1: 'CLOCK_GATING_DISABLE_ENUM_DISABLED', +} +CLOCK_GATING_DISABLE_ENUM_ENABLED = 0 +CLOCK_GATING_DISABLE_ENUM_DISABLED = 1 +CLOCK_GATING_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'ENABLE_ENUM' +ENABLE_ENUM__enumvalues = { + 0: 'ENABLE_ENUM_DISABLED', + 1: 'ENABLE_ENUM_ENABLED', +} +ENABLE_ENUM_DISABLED = 0 +ENABLE_ENUM_ENABLED = 1 +ENABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'TEST_CLOCK_MUX_SELECT_ENUM' +TEST_CLOCK_MUX_SELECT_ENUM__enumvalues = { + 0: 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', + 1: 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', + 2: 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', + 3: 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', + 4: 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', + 5: 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', +} +TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0 +TEST_CLOCK_MUX_SELECT_DISPCLK_G = 1 +TEST_CLOCK_MUX_SELECT_DISPCLK_R = 2 +TEST_CLOCK_MUX_SELECT_DSCCLK_P = 3 +TEST_CLOCK_MUX_SELECT_DSCCLK_G = 4 +TEST_CLOCK_MUX_SELECT_DSCCLK_R = 5 +TEST_CLOCK_MUX_SELECT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_CRC_CONT_EN_ENUM' +DWB_CRC_CONT_EN_ENUM__enumvalues = { + 0: 'DWB_CRC_CONT_EN_ONE_SHOT', + 1: 'DWB_CRC_CONT_EN_CONT', +} +DWB_CRC_CONT_EN_ONE_SHOT = 0 +DWB_CRC_CONT_EN_CONT = 1 +DWB_CRC_CONT_EN_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_CRC_SRC_SEL_ENUM' +DWB_CRC_SRC_SEL_ENUM__enumvalues = { + 0: 'DWB_CRC_SRC_SEL_DWB_IN', + 1: 'DWB_CRC_SRC_SEL_OGAM_OUT', + 2: 'DWB_CRC_SRC_SEL_DWB_OUT', +} +DWB_CRC_SRC_SEL_DWB_IN = 0 +DWB_CRC_SRC_SEL_OGAM_OUT = 1 +DWB_CRC_SRC_SEL_DWB_OUT = 2 +DWB_CRC_SRC_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM' +DWB_DATA_OVERFLOW_INT_TYPE_ENUM__enumvalues = { + 0: 'DWB_DATA_OVERFLOW_INT_TYPE_0', + 1: 'DWB_DATA_OVERFLOW_INT_TYPE_1', +} +DWB_DATA_OVERFLOW_INT_TYPE_0 = 0 +DWB_DATA_OVERFLOW_INT_TYPE_1 = 1 +DWB_DATA_OVERFLOW_INT_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DATA_OVERFLOW_TYPE_ENUM' +DWB_DATA_OVERFLOW_TYPE_ENUM__enumvalues = { + 0: 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', + 1: 'DWB_DATA_OVERFLOW_TYPE_BUFFER', + 2: 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', + 3: 'DWB_DATA_OVERFLOW_TYPE_VREADY', +} +DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0 +DWB_DATA_OVERFLOW_TYPE_BUFFER = 1 +DWB_DATA_OVERFLOW_TYPE_VUPDATE = 2 +DWB_DATA_OVERFLOW_TYPE_VREADY = 3 +DWB_DATA_OVERFLOW_TYPE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_DEBUG_SEL_ENUM' +DWB_DEBUG_SEL_ENUM__enumvalues = { + 0: 'DWB_DEBUG_SEL_FC', + 1: 'DWB_DEBUG_SEL_RESERVED', + 2: 'DWB_DEBUG_SEL_DWBCP', + 3: 'DWB_DEBUG_SEL_PERFMON', +} +DWB_DEBUG_SEL_FC = 0 +DWB_DEBUG_SEL_RESERVED = 1 +DWB_DEBUG_SEL_DWBCP = 2 +DWB_DEBUG_SEL_PERFMON = 3 +DWB_DEBUG_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_MEM_PWR_FORCE_ENUM' +DWB_MEM_PWR_FORCE_ENUM__enumvalues = { + 0: 'DWB_MEM_PWR_FORCE_DIS', + 1: 'DWB_MEM_PWR_FORCE_LS', + 2: 'DWB_MEM_PWR_FORCE_DS', + 3: 'DWB_MEM_PWR_FORCE_SD', +} +DWB_MEM_PWR_FORCE_DIS = 0 +DWB_MEM_PWR_FORCE_LS = 1 +DWB_MEM_PWR_FORCE_DS = 2 +DWB_MEM_PWR_FORCE_SD = 3 +DWB_MEM_PWR_FORCE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_MEM_PWR_STATE_ENUM' +DWB_MEM_PWR_STATE_ENUM__enumvalues = { + 0: 'DWB_MEM_PWR_STATE_ON', + 1: 'DWB_MEM_PWR_STATE_LS', + 2: 'DWB_MEM_PWR_STATE_DS', + 3: 'DWB_MEM_PWR_STATE_SD', +} +DWB_MEM_PWR_STATE_ON = 0 +DWB_MEM_PWR_STATE_LS = 1 +DWB_MEM_PWR_STATE_DS = 2 +DWB_MEM_PWR_STATE_SD = 3 +DWB_MEM_PWR_STATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_TEST_CLK_SEL_ENUM' +DWB_TEST_CLK_SEL_ENUM__enumvalues = { + 0: 'DWB_TEST_CLK_SEL_R', + 1: 'DWB_TEST_CLK_SEL_G', + 2: 'DWB_TEST_CLK_SEL_P', +} +DWB_TEST_CLK_SEL_R = 0 +DWB_TEST_CLK_SEL_G = 1 +DWB_TEST_CLK_SEL_P = 2 +DWB_TEST_CLK_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FC_EYE_SELECTION_ENUM' +FC_EYE_SELECTION_ENUM__enumvalues = { + 0: 'FC_EYE_SELECTION_STEREO_DIS', + 1: 'FC_EYE_SELECTION_LEFT_EYE', + 2: 'FC_EYE_SELECTION_RIGHT_EYE', +} +FC_EYE_SELECTION_STEREO_DIS = 0 +FC_EYE_SELECTION_LEFT_EYE = 1 +FC_EYE_SELECTION_RIGHT_EYE = 2 +FC_EYE_SELECTION_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FC_FRAME_CAPTURE_RATE_ENUM' +FC_FRAME_CAPTURE_RATE_ENUM__enumvalues = { + 0: 'FC_FRAME_CAPTURE_RATE_FULL', + 1: 'FC_FRAME_CAPTURE_RATE_HALF', + 2: 'FC_FRAME_CAPTURE_RATE_THIRD', + 3: 'FC_FRAME_CAPTURE_RATE_QUARTER', +} +FC_FRAME_CAPTURE_RATE_FULL = 0 +FC_FRAME_CAPTURE_RATE_HALF = 1 +FC_FRAME_CAPTURE_RATE_THIRD = 2 +FC_FRAME_CAPTURE_RATE_QUARTER = 3 +FC_FRAME_CAPTURE_RATE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'FC_STEREO_EYE_POLARITY_ENUM' +FC_STEREO_EYE_POLARITY_ENUM__enumvalues = { + 0: 'FC_STEREO_EYE_POLARITY_LEFT', + 1: 'FC_STEREO_EYE_POLARITY_RIGHT', +} +FC_STEREO_EYE_POLARITY_LEFT = 0 +FC_STEREO_EYE_POLARITY_RIGHT = 1 +FC_STEREO_EYE_POLARITY_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM' +DWB_GAMUT_REMAP_COEF_FORMAT_ENUM__enumvalues = { + 0: 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', + 1: 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', +} +DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0 +DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 +DWB_GAMUT_REMAP_COEF_FORMAT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_GAMUT_REMAP_MODE_ENUM' +DWB_GAMUT_REMAP_MODE_ENUM__enumvalues = { + 0: 'DWB_GAMUT_REMAP_MODE_BYPASS', + 1: 'DWB_GAMUT_REMAP_MODE_COEF_A', + 2: 'DWB_GAMUT_REMAP_MODE_COEF_B', + 3: 'DWB_GAMUT_REMAP_MODE_RESERVED', +} +DWB_GAMUT_REMAP_MODE_BYPASS = 0 +DWB_GAMUT_REMAP_MODE_COEF_A = 1 +DWB_GAMUT_REMAP_MODE_COEF_B = 2 +DWB_GAMUT_REMAP_MODE_RESERVED = 3 +DWB_GAMUT_REMAP_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_LUT_NUM_SEG' +DWB_LUT_NUM_SEG__enumvalues = { + 0: 'DWB_SEGMENTS_1', + 1: 'DWB_SEGMENTS_2', + 2: 'DWB_SEGMENTS_4', + 3: 'DWB_SEGMENTS_8', + 4: 'DWB_SEGMENTS_16', + 5: 'DWB_SEGMENTS_32', + 6: 'DWB_SEGMENTS_64', + 7: 'DWB_SEGMENTS_128', +} +DWB_SEGMENTS_1 = 0 +DWB_SEGMENTS_2 = 1 +DWB_SEGMENTS_4 = 2 +DWB_SEGMENTS_8 = 3 +DWB_SEGMENTS_16 = 4 +DWB_SEGMENTS_32 = 5 +DWB_SEGMENTS_64 = 6 +DWB_SEGMENTS_128 = 7 +DWB_LUT_NUM_SEG = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_CONFIG_MODE_ENUM' +DWB_OGAM_LUT_CONFIG_MODE_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', + 1: 'DWB_OGAM_LUT_CONFIG_MODE_SAME', +} +DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0 +DWB_OGAM_LUT_CONFIG_MODE_SAME = 1 +DWB_OGAM_LUT_CONFIG_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_HOST_SEL_ENUM' +DWB_OGAM_LUT_HOST_SEL_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_HOST_SEL_RAMA', + 1: 'DWB_OGAM_LUT_HOST_SEL_RAMB', +} +DWB_OGAM_LUT_HOST_SEL_RAMA = 0 +DWB_OGAM_LUT_HOST_SEL_RAMB = 1 +DWB_OGAM_LUT_HOST_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM' +DWB_OGAM_LUT_READ_COLOR_SEL_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_READ_COLOR_SEL_B', + 1: 'DWB_OGAM_LUT_READ_COLOR_SEL_G', + 2: 'DWB_OGAM_LUT_READ_COLOR_SEL_R', + 3: 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', +} +DWB_OGAM_LUT_READ_COLOR_SEL_B = 0 +DWB_OGAM_LUT_READ_COLOR_SEL_G = 1 +DWB_OGAM_LUT_READ_COLOR_SEL_R = 2 +DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 3 +DWB_OGAM_LUT_READ_COLOR_SEL_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_LUT_READ_DBG_ENUM' +DWB_OGAM_LUT_READ_DBG_ENUM__enumvalues = { + 0: 'DWB_OGAM_LUT_READ_DBG_DISABLE', + 1: 'DWB_OGAM_LUT_READ_DBG_ENABLE', +} +DWB_OGAM_LUT_READ_DBG_DISABLE = 0 +DWB_OGAM_LUT_READ_DBG_ENABLE = 1 +DWB_OGAM_LUT_READ_DBG_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_MODE_ENUM' +DWB_OGAM_MODE_ENUM__enumvalues = { + 0: 'DWB_OGAM_MODE_BYPASS', + 1: 'DWB_OGAM_MODE_RESERVED', + 2: 'DWB_OGAM_MODE_RAM_LUT_ENABLED', +} +DWB_OGAM_MODE_BYPASS = 0 +DWB_OGAM_MODE_RESERVED = 1 +DWB_OGAM_MODE_RAM_LUT_ENABLED = 2 +DWB_OGAM_MODE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_PWL_DISABLE_ENUM' +DWB_OGAM_PWL_DISABLE_ENUM__enumvalues = { + 0: 'DWB_OGAM_PWL_DISABLE_FALSE', + 1: 'DWB_OGAM_PWL_DISABLE_TRUE', +} +DWB_OGAM_PWL_DISABLE_FALSE = 0 +DWB_OGAM_PWL_DISABLE_TRUE = 1 +DWB_OGAM_PWL_DISABLE_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'DWB_OGAM_SELECT_ENUM' +DWB_OGAM_SELECT_ENUM__enumvalues = { + 0: 'DWB_OGAM_SELECT_A', + 1: 'DWB_OGAM_SELECT_B', +} +DWB_OGAM_SELECT_A = 0 +DWB_OGAM_SELECT_B = 1 +DWB_OGAM_SELECT_ENUM = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN' +RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN__enumvalues = { + 0: 'RDPCSPIPE_EXT_PCLK_EN_DISABLE', + 1: 'RDPCSPIPE_EXT_PCLK_EN_ENABLE', +} +RDPCSPIPE_EXT_PCLK_EN_DISABLE = 0 +RDPCSPIPE_EXT_PCLK_EN_ENABLE = 1 +RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN' +RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN__enumvalues = { + 0: 'RDPCSPIPE_APBCLK_DISABLE', + 1: 'RDPCSPIPE_APBCLK_ENABLE', +} +RDPCSPIPE_APBCLK_DISABLE = 0 +RDPCSPIPE_APBCLK_ENABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON' +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON__enumvalues = { + 0: 'RDPCS_PIPE_CLK_CLOCK_OFF', + 1: 'RDPCS_PIPE_CLK_CLOCK_ON', +} +RDPCS_PIPE_CLK_CLOCK_OFF = 0 +RDPCS_PIPE_CLK_CLOCK_ON = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN' +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN__enumvalues = { + 0: 'RDPCS_PIPE_CLK_DISABLE', + 1: 'RDPCS_PIPE_CLK_ENABLE', +} +RDPCS_PIPE_CLK_DISABLE = 0 +RDPCS_PIPE_CLK_ENABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS' +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS__enumvalues = { + 0: 'RDPCS_PIPE_CLK_GATE_ENABLE', + 1: 'RDPCS_PIPE_CLK_GATE_DISABLE', +} +RDPCS_PIPE_CLK_GATE_ENABLE = 0 +RDPCS_PIPE_CLK_GATE_DISABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON' +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON__enumvalues = { + 0: 'RDPCS_PIPE_PHYD32CLK_CLOCK_OFF', + 1: 'RDPCS_PIPE_PHYD32CLK_CLOCK_ON', +} +RDPCS_PIPE_PHYD32CLK_CLOCK_OFF = 0 +RDPCS_PIPE_PHYD32CLK_CLOCK_ON = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON' +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON__enumvalues = { + 0: 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF', + 1: 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON', +} +RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF = 0 +RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN' +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN__enumvalues = { + 0: 'RDPCSPIPE_SRAMCLK_DISABLE', + 1: 'RDPCSPIPE_SRAMCLK_ENABLE', +} +RDPCSPIPE_SRAMCLK_DISABLE = 0 +RDPCSPIPE_SRAMCLK_ENABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS' +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS__enumvalues = { + 0: 'RDPCSPIPE_SRAMCLK_GATE_ENABLE', + 1: 'RDPCSPIPE_SRAMCLK_GATE_DISABLE', +} +RDPCSPIPE_SRAMCLK_GATE_ENABLE = 0 +RDPCSPIPE_SRAMCLK_GATE_DISABLE = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS' +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS__enumvalues = { + 0: 'RDPCSPIPE_SRAMCLK_NOT_PASS', + 1: 'RDPCSPIPE_SRAMCLK_PASS', +} +RDPCSPIPE_SRAMCLK_NOT_PASS = 0 +RDPCSPIPE_SRAMCLK_PASS = 1 +RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN' +RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN__enumvalues = { + 0: 'RDPCS_PIPE_FIFO_DISABLE', + 1: 'RDPCS_PIPE_FIFO_ENABLE', +} +RDPCS_PIPE_FIFO_DISABLE = 0 +RDPCS_PIPE_FIFO_ENABLE = 1 +RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN' +RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN__enumvalues = { + 0: 'RDPCS_PIPE_FIFO_LANE_DISABLE', + 1: 'RDPCS_PIPE_FIFO_LANE_ENABLE', +} +RDPCS_PIPE_FIFO_LANE_DISABLE = 0 +RDPCS_PIPE_FIFO_LANE_ENABLE = 1 +RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET' +RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET__enumvalues = { + 0: 'RDPCS_PIPE_SOFT_RESET_DISABLE', + 1: 'RDPCS_PIPE_SOFT_RESET_ENABLE', +} +RDPCS_PIPE_SOFT_RESET_DISABLE = 0 +RDPCS_PIPE_SOFT_RESET_ENABLE = 1 +RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET' +RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET__enumvalues = { + 0: 'RDPCSPIPE_SRAM_SRAM_RESET_DISABLE', + 1: 'RDPCSPIPE_SRAM_SRAM_RESET_ENABLE', +} +RDPCSPIPE_SRAM_SRAM_RESET_DISABLE = 0 +RDPCSPIPE_SRAM_SRAM_RESET_ENABLE = 1 +RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK' +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK__enumvalues = { + 0: 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE', + 1: 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE', +} +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE = 0 +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE = 1 +RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_DBG_OCLA_SEL' +RDPCSPIPE_DBG_OCLA_SEL__enumvalues = { + 0: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0', + 1: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8', + 2: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16', + 3: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24', + 4: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32', + 5: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40', + 6: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48', + 7: 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56', +} +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0 = 0 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8 = 1 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16 = 2 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24 = 3 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32 = 4 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40 = 5 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48 = 6 +RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56 = 7 +RDPCSPIPE_DBG_OCLA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_ENC_TYPE' +RDPCSPIPE_ENC_TYPE__enumvalues = { + 0: 'HDMI_TMDS_OR_DP_8B10B', + 1: 'HDMI_FRL', + 2: 'DP_128B132B', +} +HDMI_TMDS_OR_DP_8B10B = 0 +HDMI_FRL = 1 +DP_128B132B = 2 +RDPCSPIPE_ENC_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_FIFO_EMPTY' +RDPCSPIPE_FIFO_EMPTY__enumvalues = { + 0: 'RDPCSPIPE_FIFO_NOT_EMPTY', + 1: 'RDPCSPIPE_FIFO_IS_EMPTY', +} +RDPCSPIPE_FIFO_NOT_EMPTY = 0 +RDPCSPIPE_FIFO_IS_EMPTY = 1 +RDPCSPIPE_FIFO_EMPTY = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_FIFO_FULL' +RDPCSPIPE_FIFO_FULL__enumvalues = { + 0: 'RDPCSPIPE_FIFO_NOT_FULL', + 1: 'RDPCSPIPE_FIFO_IS_FULL', +} +RDPCSPIPE_FIFO_NOT_FULL = 0 +RDPCSPIPE_FIFO_IS_FULL = 1 +RDPCSPIPE_FIFO_FULL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK__enumvalues = { + 0: 'RDPCSPIPE_APB_PSLVERR_MASK_DISABLE', + 1: 'RDPCSPIPE_APB_PSLVERR_MASK_ENABLE', +} +RDPCSPIPE_APB_PSLVERR_MASK_DISABLE = 0 +RDPCSPIPE_APB_PSLVERR_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE__enumvalues = { + 0: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE', + 1: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE', +} +RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE = 0 +RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK__enumvalues = { + 0: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE', + 1: 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE', +} +RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0 +RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE__enumvalues = { + 0: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE', + 1: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE', +} +RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE = 0 +RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK__enumvalues = { + 0: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE', + 1: 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE', +} +RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0 +RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK__enumvalues = { + 0: 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE', + 1: 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE', +} +RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE = 0 +RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK' +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK__enumvalues = { + 0: 'RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE', + 1: 'RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE', +} +RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE = 0 +RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE = 1 +RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK' +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK__enumvalues = { + 0: 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE', + 1: 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE', +} +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE = 0 +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE = 1 +RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PACK_MODE' +RDPCSPIPE_PACK_MODE__enumvalues = { + 0: 'TIGHT_PACK', + 1: 'LOOSE_PACK', +} +TIGHT_PACK = 0 +LOOSE_PACK = 1 +RDPCSPIPE_PACK_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL' +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL__enumvalues = { + 0: 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB', + 1: 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC', +} +RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB = 0 +RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC = 1 +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL' +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL__enumvalues = { + 0: 'RDPCSPIPE_PHY_CR_PARA_SEL_JTAG', + 1: 'RDPCSPIPE_PHY_CR_PARA_SEL_CR', +} +RDPCSPIPE_PHY_CR_PARA_SEL_JTAG = 0 +RDPCSPIPE_PHY_CR_PARA_SEL_CR = 1 +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE' +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE__enumvalues = { + 0: 'RDPCSPIPE_PHY_REF_RANGE_0', + 1: 'RDPCSPIPE_PHY_REF_RANGE_1', + 2: 'RDPCSPIPE_PHY_REF_RANGE_2', + 3: 'RDPCSPIPE_PHY_REF_RANGE_3', + 4: 'RDPCSPIPE_PHY_REF_RANGE_4', + 5: 'RDPCSPIPE_PHY_REF_RANGE_5', + 6: 'RDPCSPIPE_PHY_REF_RANGE_6', + 7: 'RDPCSPIPE_PHY_REF_RANGE_7', +} +RDPCSPIPE_PHY_REF_RANGE_0 = 0 +RDPCSPIPE_PHY_REF_RANGE_1 = 1 +RDPCSPIPE_PHY_REF_RANGE_2 = 2 +RDPCSPIPE_PHY_REF_RANGE_3 = 3 +RDPCSPIPE_PHY_REF_RANGE_4 = 4 +RDPCSPIPE_PHY_REF_RANGE_5 = 5 +RDPCSPIPE_PHY_REF_RANGE_6 = 6 +RDPCSPIPE_PHY_REF_RANGE_7 = 7 +RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE' +RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE__enumvalues = { + 0: 'RDPCSPIPE_SRAM_EXT_LD_NOT_DONE', + 1: 'RDPCSPIPE_SRAM_EXT_LD_DONE', +} +RDPCSPIPE_SRAM_EXT_LD_NOT_DONE = 0 +RDPCSPIPE_SRAM_EXT_LD_DONE = 1 +RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE' +RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE__enumvalues = { + 0: 'RDPCSPIPE_SRAM_INIT_NOT_DONE', + 1: 'RDPCSPIPE_SRAM_INIT_DONE', +} +RDPCSPIPE_SRAM_INIT_NOT_DONE = 0 +RDPCSPIPE_SRAM_INIT_DONE = 1 +RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV' +RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1', + 1: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2', + 2: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3', + 3: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8', + 4: 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16', +} +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1 = 0 +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2 = 1 +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3 = 2 +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8 = 3 +RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16 = 4 +RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV' +RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__enumvalues = { + 0: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', + 1: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', + 2: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', + 3: 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', +} +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0 +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 1 +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 2 +RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 3 +RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV' +RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV', + 1: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2', + 2: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4', + 3: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8', + 4: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3', + 5: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5', + 6: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6', + 7: 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10', +} +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV = 0 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2 = 1 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4 = 2 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8 = 3 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3 = 4 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5 = 5 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6 = 6 +RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10 = 7 +RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL' +RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54', + 1: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52', + 2: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50', + 3: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48', + 4: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46', + 5: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44', + 6: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42', + 7: 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40', +} +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54 = 0 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52 = 1 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50 = 2 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48 = 3 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46 = 4 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44 = 5 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42 = 6 +RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40 = 7 +RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT' +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT', + 1: 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT', +} +RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0 +RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT = 1 +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE' +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_TX_RATE', + 1: 'RDPCSPIPE_PHY_DP_TX_RATE_DIV2', + 2: 'RDPCSPIPE_PHY_DP_TX_RATE_DIV4', +} +RDPCSPIPE_PHY_DP_TX_RATE = 0 +RDPCSPIPE_PHY_DP_TX_RATE_DIV2 = 1 +RDPCSPIPE_PHY_DP_TX_RATE_DIV4 = 2 +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH' +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH__enumvalues = { + 0: 'RDPCSPIPE_PHY_DP_TX_WIDTH_8', + 1: 'RDPCSPIPE_PHY_DP_TX_WIDTH_10', + 2: 'RDPCSPIPE_PHY_DP_TX_WIDTH_16', + 3: 'RDPCSPIPE_PHY_DP_TX_WIDTH_20', +} +RDPCSPIPE_PHY_DP_TX_WIDTH_8 = 0 +RDPCSPIPE_PHY_DP_TX_WIDTH_10 = 1 +RDPCSPIPE_PHY_DP_TX_WIDTH_16 = 2 +RDPCSPIPE_PHY_DP_TX_WIDTH_20 = 3 +RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE' +RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE__enumvalues = { + 0: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP', + 1: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD', + 2: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF', + 3: 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN', +} +RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP = 0 +RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD = 1 +RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF = 2 +RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN = 3 +RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_IF_WIDTH' +RDPCSPIPE_PHY_IF_WIDTH__enumvalues = { + 0: 'PHY_IF_WIDTH_10BIT', + 1: 'PHY_IF_WIDTH_20BIT', + 2: 'PHY_IF_WIDTH_40BIT', + 3: 'PHY_IF_WIDTH_80BIT', +} +PHY_IF_WIDTH_10BIT = 0 +PHY_IF_WIDTH_20BIT = 1 +PHY_IF_WIDTH_40BIT = 2 +PHY_IF_WIDTH_80BIT = 3 +RDPCSPIPE_PHY_IF_WIDTH = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_RATE' +RDPCSPIPE_PHY_RATE__enumvalues = { + 0: 'PHY_DP_RATE_1P62', + 1: 'PHY_DP_RATE_2P7', + 2: 'PHY_DP_RATE_5P4', + 3: 'PHY_DP_RATE_8P1', + 4: 'PHY_DP_RATE_2P16', + 5: 'PHY_DP_RATE_2P43', + 6: 'PHY_DP_RATE_3P24', + 7: 'PHY_DP_RATE_4P32', + 8: 'PHY_DP_RATE_10P', + 9: 'PHY_DP_RATE_13P5', + 10: 'PHY_DP_RATE_20P', + 15: 'PHY_CUSTOM_RATE', +} +PHY_DP_RATE_1P62 = 0 +PHY_DP_RATE_2P7 = 1 +PHY_DP_RATE_5P4 = 2 +PHY_DP_RATE_8P1 = 3 +PHY_DP_RATE_2P16 = 4 +PHY_DP_RATE_2P43 = 5 +PHY_DP_RATE_3P24 = 6 +PHY_DP_RATE_4P32 = 7 +PHY_DP_RATE_10P = 8 +PHY_DP_RATE_13P5 = 9 +PHY_DP_RATE_20P = 10 +PHY_CUSTOM_RATE = 15 +RDPCSPIPE_PHY_RATE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_PHY_REF_ALT_CLK_EN' +RDPCSPIPE_PHY_REF_ALT_CLK_EN__enumvalues = { + 0: 'RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE', + 1: 'RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE', +} +RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE = 0 +RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE = 1 +RDPCSPIPE_PHY_REF_ALT_CLK_EN = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCSPIPE_TEST_CLK_SEL' +RDPCSPIPE_TEST_CLK_SEL__enumvalues = { + 0: 'RDPCSPIPE_TEST_CLK_SEL_NONE', + 1: 'RDPCSPIPE_TEST_CLK_SEL_CFGCLK', + 2: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', + 3: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', + 4: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', + 5: 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', + 6: 'RDPCSPIPE_TEST_CLK_SEL_SRAMCLK', + 7: 'RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK', + 8: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK', + 9: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK', + 10: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK', + 11: 'RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK', + 12: 'RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', + 13: 'RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', + 14: 'RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK', + 15: 'RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk', + 16: 'RDPCSPIPE_TEST_CLK_SEL_dtb_out0', + 17: 'RDPCSPIPE_TEST_CLK_SEL_dtb_out1', +} +RDPCSPIPE_TEST_CLK_SEL_NONE = 0 +RDPCSPIPE_TEST_CLK_SEL_CFGCLK = 1 +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 2 +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 3 +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 4 +RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 5 +RDPCSPIPE_TEST_CLK_SEL_SRAMCLK = 6 +RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK = 7 +RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK = 8 +RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK = 9 +RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK = 10 +RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK = 11 +RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 12 +RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 13 +RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK = 14 +RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk = 15 +RDPCSPIPE_TEST_CLK_SEL_dtb_out0 = 16 +RDPCSPIPE_TEST_CLK_SEL_dtb_out1 = 17 +RDPCSPIPE_TEST_CLK_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB' +RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB__enumvalues = { + 0: 'RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE', + 1: 'RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE', +} +RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE = 0 +RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE = 1 +RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE' +RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE__enumvalues = { + 0: 'RDPCSPIPE_MEM_PWR_NO_FORCE', + 1: 'RDPCSPIPE_MEM_PWR_LIGHT_SLEEP', + 2: 'RDPCSPIPE_MEM_PWR_DEEP_SLEEP', + 3: 'RDPCSPIPE_MEM_PWR_SHUT_DOWN', +} +RDPCSPIPE_MEM_PWR_NO_FORCE = 0 +RDPCSPIPE_MEM_PWR_LIGHT_SLEEP = 1 +RDPCSPIPE_MEM_PWR_DEEP_SLEEP = 2 +RDPCSPIPE_MEM_PWR_SHUT_DOWN = 3 +RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE = ctypes.c_uint32 # enum + +# values for enumeration 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE' +RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE__enumvalues = { + 0: 'RDPCSPIPE_MEM_PWR_PWR_STATE_ON', + 1: 'RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP', + 2: 'RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP', + 3: 'RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN', +} +RDPCSPIPE_MEM_PWR_PWR_STATE_ON = 0 +RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 1 +RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP = 2 +RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN = 3 +RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK' +RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK__enumvalues = { + 0: 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE', + 1: 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE', +} +RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE = 0 +RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE = 1 +RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK = ctypes.c_uint32 # enum + +# values for enumeration 'GDS_PERFCOUNT_SELECT' +GDS_PERFCOUNT_SELECT__enumvalues = { + 0: 'GDS_PERF_SEL_WR_COMP', + 1: 'GDS_PERF_SEL_WBUF_WR', + 2: 'GDS_PERF_SEL_SE0_NORET', + 3: 'GDS_PERF_SEL_SE0_RET', + 4: 'GDS_PERF_SEL_SE0_ORD_CNT', + 5: 'GDS_PERF_SEL_SE0_2COMP_REQ', + 6: 'GDS_PERF_SEL_SE0_ORD_WAVE_VALID', + 7: 'GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD', + 8: 'GDS_PERF_SEL_SE0_GDS_WR_OP', + 9: 'GDS_PERF_SEL_SE0_GDS_RD_OP', + 10: 'GDS_PERF_SEL_SE0_GDS_ATOM_OP', + 11: 'GDS_PERF_SEL_SE0_GDS_REL_OP', + 12: 'GDS_PERF_SEL_SE0_GDS_CMPXCH_OP', + 13: 'GDS_PERF_SEL_SE0_GDS_BYTE_OP', + 14: 'GDS_PERF_SEL_SE0_GDS_SHORT_OP', + 15: 'GDS_PERF_SEL_SE1_NORET', + 16: 'GDS_PERF_SEL_SE1_RET', + 17: 'GDS_PERF_SEL_SE1_ORD_CNT', + 18: 'GDS_PERF_SEL_SE1_2COMP_REQ', + 19: 'GDS_PERF_SEL_SE1_ORD_WAVE_VALID', + 20: 'GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD', + 21: 'GDS_PERF_SEL_SE1_GDS_WR_OP', + 22: 'GDS_PERF_SEL_SE1_GDS_RD_OP', + 23: 'GDS_PERF_SEL_SE1_GDS_ATOM_OP', + 24: 'GDS_PERF_SEL_SE1_GDS_REL_OP', + 25: 'GDS_PERF_SEL_SE1_GDS_CMPXCH_OP', + 26: 'GDS_PERF_SEL_SE1_GDS_BYTE_OP', + 27: 'GDS_PERF_SEL_SE1_GDS_SHORT_OP', + 28: 'GDS_PERF_SEL_SE2_NORET', + 29: 'GDS_PERF_SEL_SE2_RET', + 30: 'GDS_PERF_SEL_SE2_ORD_CNT', + 31: 'GDS_PERF_SEL_SE2_2COMP_REQ', + 32: 'GDS_PERF_SEL_SE2_ORD_WAVE_VALID', + 33: 'GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD', + 34: 'GDS_PERF_SEL_SE2_GDS_WR_OP', + 35: 'GDS_PERF_SEL_SE2_GDS_RD_OP', + 36: 'GDS_PERF_SEL_SE2_GDS_ATOM_OP', + 37: 'GDS_PERF_SEL_SE2_GDS_REL_OP', + 38: 'GDS_PERF_SEL_SE2_GDS_CMPXCH_OP', + 39: 'GDS_PERF_SEL_SE2_GDS_BYTE_OP', + 40: 'GDS_PERF_SEL_SE2_GDS_SHORT_OP', + 41: 'GDS_PERF_SEL_SE3_NORET', + 42: 'GDS_PERF_SEL_SE3_RET', + 43: 'GDS_PERF_SEL_SE3_ORD_CNT', + 44: 'GDS_PERF_SEL_SE3_2COMP_REQ', + 45: 'GDS_PERF_SEL_SE3_ORD_WAVE_VALID', + 46: 'GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD', + 47: 'GDS_PERF_SEL_SE3_GDS_WR_OP', + 48: 'GDS_PERF_SEL_SE3_GDS_RD_OP', + 49: 'GDS_PERF_SEL_SE3_GDS_ATOM_OP', + 50: 'GDS_PERF_SEL_SE3_GDS_REL_OP', + 51: 'GDS_PERF_SEL_SE3_GDS_CMPXCH_OP', + 52: 'GDS_PERF_SEL_SE3_GDS_BYTE_OP', + 53: 'GDS_PERF_SEL_SE3_GDS_SHORT_OP', + 54: 'GDS_PERF_SEL_SE4_NORET', + 55: 'GDS_PERF_SEL_SE4_RET', + 56: 'GDS_PERF_SEL_SE4_ORD_CNT', + 57: 'GDS_PERF_SEL_SE4_2COMP_REQ', + 58: 'GDS_PERF_SEL_SE4_ORD_WAVE_VALID', + 59: 'GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD', + 60: 'GDS_PERF_SEL_SE4_GDS_WR_OP', + 61: 'GDS_PERF_SEL_SE4_GDS_RD_OP', + 62: 'GDS_PERF_SEL_SE4_GDS_ATOM_OP', + 63: 'GDS_PERF_SEL_SE4_GDS_REL_OP', + 64: 'GDS_PERF_SEL_SE4_GDS_CMPXCH_OP', + 65: 'GDS_PERF_SEL_SE4_GDS_BYTE_OP', + 66: 'GDS_PERF_SEL_SE4_GDS_SHORT_OP', + 67: 'GDS_PERF_SEL_SE5_NORET', + 68: 'GDS_PERF_SEL_SE5_RET', + 69: 'GDS_PERF_SEL_SE5_ORD_CNT', + 70: 'GDS_PERF_SEL_SE5_2COMP_REQ', + 71: 'GDS_PERF_SEL_SE5_ORD_WAVE_VALID', + 72: 'GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD', + 73: 'GDS_PERF_SEL_SE5_GDS_WR_OP', + 74: 'GDS_PERF_SEL_SE5_GDS_RD_OP', + 75: 'GDS_PERF_SEL_SE5_GDS_ATOM_OP', + 76: 'GDS_PERF_SEL_SE5_GDS_REL_OP', + 77: 'GDS_PERF_SEL_SE5_GDS_CMPXCH_OP', + 78: 'GDS_PERF_SEL_SE5_GDS_BYTE_OP', + 79: 'GDS_PERF_SEL_SE5_GDS_SHORT_OP', + 80: 'GDS_PERF_SEL_SE6_NORET', + 81: 'GDS_PERF_SEL_SE6_RET', + 82: 'GDS_PERF_SEL_SE6_ORD_CNT', + 83: 'GDS_PERF_SEL_SE6_2COMP_REQ', + 84: 'GDS_PERF_SEL_SE6_ORD_WAVE_VALID', + 85: 'GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD', + 86: 'GDS_PERF_SEL_SE6_GDS_WR_OP', + 87: 'GDS_PERF_SEL_SE6_GDS_RD_OP', + 88: 'GDS_PERF_SEL_SE6_GDS_ATOM_OP', + 89: 'GDS_PERF_SEL_SE6_GDS_REL_OP', + 90: 'GDS_PERF_SEL_SE6_GDS_CMPXCH_OP', + 91: 'GDS_PERF_SEL_SE6_GDS_BYTE_OP', + 92: 'GDS_PERF_SEL_SE6_GDS_SHORT_OP', + 93: 'GDS_PERF_SEL_SE7_NORET', + 94: 'GDS_PERF_SEL_SE7_RET', + 95: 'GDS_PERF_SEL_SE7_ORD_CNT', + 96: 'GDS_PERF_SEL_SE7_2COMP_REQ', + 97: 'GDS_PERF_SEL_SE7_ORD_WAVE_VALID', + 98: 'GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD', + 99: 'GDS_PERF_SEL_SE7_GDS_WR_OP', + 100: 'GDS_PERF_SEL_SE7_GDS_RD_OP', + 101: 'GDS_PERF_SEL_SE7_GDS_ATOM_OP', + 102: 'GDS_PERF_SEL_SE7_GDS_REL_OP', + 103: 'GDS_PERF_SEL_SE7_GDS_CMPXCH_OP', + 104: 'GDS_PERF_SEL_SE7_GDS_BYTE_OP', + 105: 'GDS_PERF_SEL_SE7_GDS_SHORT_OP', + 106: 'GDS_PERF_SEL_GWS_RELEASED', + 107: 'GDS_PERF_SEL_GWS_BYPASS', +} +GDS_PERF_SEL_WR_COMP = 0 +GDS_PERF_SEL_WBUF_WR = 1 +GDS_PERF_SEL_SE0_NORET = 2 +GDS_PERF_SEL_SE0_RET = 3 +GDS_PERF_SEL_SE0_ORD_CNT = 4 +GDS_PERF_SEL_SE0_2COMP_REQ = 5 +GDS_PERF_SEL_SE0_ORD_WAVE_VALID = 6 +GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD = 7 +GDS_PERF_SEL_SE0_GDS_WR_OP = 8 +GDS_PERF_SEL_SE0_GDS_RD_OP = 9 +GDS_PERF_SEL_SE0_GDS_ATOM_OP = 10 +GDS_PERF_SEL_SE0_GDS_REL_OP = 11 +GDS_PERF_SEL_SE0_GDS_CMPXCH_OP = 12 +GDS_PERF_SEL_SE0_GDS_BYTE_OP = 13 +GDS_PERF_SEL_SE0_GDS_SHORT_OP = 14 +GDS_PERF_SEL_SE1_NORET = 15 +GDS_PERF_SEL_SE1_RET = 16 +GDS_PERF_SEL_SE1_ORD_CNT = 17 +GDS_PERF_SEL_SE1_2COMP_REQ = 18 +GDS_PERF_SEL_SE1_ORD_WAVE_VALID = 19 +GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD = 20 +GDS_PERF_SEL_SE1_GDS_WR_OP = 21 +GDS_PERF_SEL_SE1_GDS_RD_OP = 22 +GDS_PERF_SEL_SE1_GDS_ATOM_OP = 23 +GDS_PERF_SEL_SE1_GDS_REL_OP = 24 +GDS_PERF_SEL_SE1_GDS_CMPXCH_OP = 25 +GDS_PERF_SEL_SE1_GDS_BYTE_OP = 26 +GDS_PERF_SEL_SE1_GDS_SHORT_OP = 27 +GDS_PERF_SEL_SE2_NORET = 28 +GDS_PERF_SEL_SE2_RET = 29 +GDS_PERF_SEL_SE2_ORD_CNT = 30 +GDS_PERF_SEL_SE2_2COMP_REQ = 31 +GDS_PERF_SEL_SE2_ORD_WAVE_VALID = 32 +GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD = 33 +GDS_PERF_SEL_SE2_GDS_WR_OP = 34 +GDS_PERF_SEL_SE2_GDS_RD_OP = 35 +GDS_PERF_SEL_SE2_GDS_ATOM_OP = 36 +GDS_PERF_SEL_SE2_GDS_REL_OP = 37 +GDS_PERF_SEL_SE2_GDS_CMPXCH_OP = 38 +GDS_PERF_SEL_SE2_GDS_BYTE_OP = 39 +GDS_PERF_SEL_SE2_GDS_SHORT_OP = 40 +GDS_PERF_SEL_SE3_NORET = 41 +GDS_PERF_SEL_SE3_RET = 42 +GDS_PERF_SEL_SE3_ORD_CNT = 43 +GDS_PERF_SEL_SE3_2COMP_REQ = 44 +GDS_PERF_SEL_SE3_ORD_WAVE_VALID = 45 +GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD = 46 +GDS_PERF_SEL_SE3_GDS_WR_OP = 47 +GDS_PERF_SEL_SE3_GDS_RD_OP = 48 +GDS_PERF_SEL_SE3_GDS_ATOM_OP = 49 +GDS_PERF_SEL_SE3_GDS_REL_OP = 50 +GDS_PERF_SEL_SE3_GDS_CMPXCH_OP = 51 +GDS_PERF_SEL_SE3_GDS_BYTE_OP = 52 +GDS_PERF_SEL_SE3_GDS_SHORT_OP = 53 +GDS_PERF_SEL_SE4_NORET = 54 +GDS_PERF_SEL_SE4_RET = 55 +GDS_PERF_SEL_SE4_ORD_CNT = 56 +GDS_PERF_SEL_SE4_2COMP_REQ = 57 +GDS_PERF_SEL_SE4_ORD_WAVE_VALID = 58 +GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD = 59 +GDS_PERF_SEL_SE4_GDS_WR_OP = 60 +GDS_PERF_SEL_SE4_GDS_RD_OP = 61 +GDS_PERF_SEL_SE4_GDS_ATOM_OP = 62 +GDS_PERF_SEL_SE4_GDS_REL_OP = 63 +GDS_PERF_SEL_SE4_GDS_CMPXCH_OP = 64 +GDS_PERF_SEL_SE4_GDS_BYTE_OP = 65 +GDS_PERF_SEL_SE4_GDS_SHORT_OP = 66 +GDS_PERF_SEL_SE5_NORET = 67 +GDS_PERF_SEL_SE5_RET = 68 +GDS_PERF_SEL_SE5_ORD_CNT = 69 +GDS_PERF_SEL_SE5_2COMP_REQ = 70 +GDS_PERF_SEL_SE5_ORD_WAVE_VALID = 71 +GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD = 72 +GDS_PERF_SEL_SE5_GDS_WR_OP = 73 +GDS_PERF_SEL_SE5_GDS_RD_OP = 74 +GDS_PERF_SEL_SE5_GDS_ATOM_OP = 75 +GDS_PERF_SEL_SE5_GDS_REL_OP = 76 +GDS_PERF_SEL_SE5_GDS_CMPXCH_OP = 77 +GDS_PERF_SEL_SE5_GDS_BYTE_OP = 78 +GDS_PERF_SEL_SE5_GDS_SHORT_OP = 79 +GDS_PERF_SEL_SE6_NORET = 80 +GDS_PERF_SEL_SE6_RET = 81 +GDS_PERF_SEL_SE6_ORD_CNT = 82 +GDS_PERF_SEL_SE6_2COMP_REQ = 83 +GDS_PERF_SEL_SE6_ORD_WAVE_VALID = 84 +GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD = 85 +GDS_PERF_SEL_SE6_GDS_WR_OP = 86 +GDS_PERF_SEL_SE6_GDS_RD_OP = 87 +GDS_PERF_SEL_SE6_GDS_ATOM_OP = 88 +GDS_PERF_SEL_SE6_GDS_REL_OP = 89 +GDS_PERF_SEL_SE6_GDS_CMPXCH_OP = 90 +GDS_PERF_SEL_SE6_GDS_BYTE_OP = 91 +GDS_PERF_SEL_SE6_GDS_SHORT_OP = 92 +GDS_PERF_SEL_SE7_NORET = 93 +GDS_PERF_SEL_SE7_RET = 94 +GDS_PERF_SEL_SE7_ORD_CNT = 95 +GDS_PERF_SEL_SE7_2COMP_REQ = 96 +GDS_PERF_SEL_SE7_ORD_WAVE_VALID = 97 +GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD = 98 +GDS_PERF_SEL_SE7_GDS_WR_OP = 99 +GDS_PERF_SEL_SE7_GDS_RD_OP = 100 +GDS_PERF_SEL_SE7_GDS_ATOM_OP = 101 +GDS_PERF_SEL_SE7_GDS_REL_OP = 102 +GDS_PERF_SEL_SE7_GDS_CMPXCH_OP = 103 +GDS_PERF_SEL_SE7_GDS_BYTE_OP = 104 +GDS_PERF_SEL_SE7_GDS_SHORT_OP = 105 +GDS_PERF_SEL_GWS_RELEASED = 106 +GDS_PERF_SEL_GWS_BYPASS = 107 +GDS_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'BlendOp' +BlendOp__enumvalues = { + 0: 'BLEND_ZERO', + 1: 'BLEND_ONE', + 2: 'BLEND_SRC_COLOR', + 3: 'BLEND_ONE_MINUS_SRC_COLOR', + 4: 'BLEND_SRC_ALPHA', + 5: 'BLEND_ONE_MINUS_SRC_ALPHA', + 6: 'BLEND_DST_ALPHA', + 7: 'BLEND_ONE_MINUS_DST_ALPHA', + 8: 'BLEND_DST_COLOR', + 9: 'BLEND_ONE_MINUS_DST_COLOR', + 10: 'BLEND_SRC_ALPHA_SATURATE', + 11: 'BLEND_CONSTANT_COLOR', + 12: 'BLEND_ONE_MINUS_CONSTANT_COLOR', + 13: 'BLEND_SRC1_COLOR', + 14: 'BLEND_INV_SRC1_COLOR', + 15: 'BLEND_SRC1_ALPHA', + 16: 'BLEND_INV_SRC1_ALPHA', + 17: 'BLEND_CONSTANT_ALPHA', + 18: 'BLEND_ONE_MINUS_CONSTANT_ALPHA', +} +BLEND_ZERO = 0 +BLEND_ONE = 1 +BLEND_SRC_COLOR = 2 +BLEND_ONE_MINUS_SRC_COLOR = 3 +BLEND_SRC_ALPHA = 4 +BLEND_ONE_MINUS_SRC_ALPHA = 5 +BLEND_DST_ALPHA = 6 +BLEND_ONE_MINUS_DST_ALPHA = 7 +BLEND_DST_COLOR = 8 +BLEND_ONE_MINUS_DST_COLOR = 9 +BLEND_SRC_ALPHA_SATURATE = 10 +BLEND_CONSTANT_COLOR = 11 +BLEND_ONE_MINUS_CONSTANT_COLOR = 12 +BLEND_SRC1_COLOR = 13 +BLEND_INV_SRC1_COLOR = 14 +BLEND_SRC1_ALPHA = 15 +BLEND_INV_SRC1_ALPHA = 16 +BLEND_CONSTANT_ALPHA = 17 +BLEND_ONE_MINUS_CONSTANT_ALPHA = 18 +BlendOp = ctypes.c_uint32 # enum +GL__ZERO = BLEND_ZERO # macro +GL__ONE = BLEND_ONE # macro +GL__SRC_COLOR = BLEND_SRC_COLOR # macro +GL__ONE_MINUS_SRC_COLOR = BLEND_ONE_MINUS_SRC_COLOR # macro +GL__DST_COLOR = BLEND_DST_COLOR # macro +GL__ONE_MINUS_DST_COLOR = BLEND_ONE_MINUS_DST_COLOR # macro +GL__SRC_ALPHA = BLEND_SRC_ALPHA # macro +GL__ONE_MINUS_SRC_ALPHA = BLEND_ONE_MINUS_SRC_ALPHA # macro +GL__DST_ALPHA = BLEND_DST_ALPHA # macro +GL__ONE_MINUS_DST_ALPHA = BLEND_ONE_MINUS_DST_ALPHA # macro +GL__SRC_ALPHA_SATURATE = BLEND_SRC_ALPHA_SATURATE # macro +GL__CONSTANT_COLOR = BLEND_CONSTANT_COLOR # macro +GL__ONE_MINUS_CONSTANT_COLOR = BLEND_ONE_MINUS_CONSTANT_COLOR # macro +GL__CONSTANT_ALPHA = BLEND_CONSTANT_ALPHA # macro +GL__ONE_MINUS_CONSTANT_ALPHA = BLEND_ONE_MINUS_CONSTANT_ALPHA # macro + +# values for enumeration 'BlendOpt' +BlendOpt__enumvalues = { + 0: 'FORCE_OPT_AUTO', + 1: 'FORCE_OPT_DISABLE', + 2: 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 3: 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 4: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 5: 'FORCE_OPT_ENABLE_IF_SRC_A_1', + 6: 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', + 7: 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', +} +FORCE_OPT_AUTO = 0 +FORCE_OPT_DISABLE = 1 +FORCE_OPT_ENABLE_IF_SRC_A_0 = 2 +FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 3 +FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 4 +FORCE_OPT_ENABLE_IF_SRC_A_1 = 5 +FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 6 +FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 7 +BlendOpt = ctypes.c_uint32 # enum + +# values for enumeration 'CBMode' +CBMode__enumvalues = { + 0: 'CB_DISABLE', + 1: 'CB_NORMAL', + 2: 'CB_ELIMINATE_FAST_CLEAR', + 3: 'CB_DCC_DECOMPRESS', + 4: 'CB_RESERVED', +} +CB_DISABLE = 0 +CB_NORMAL = 1 +CB_ELIMINATE_FAST_CLEAR = 2 +CB_DCC_DECOMPRESS = 3 +CB_RESERVED = 4 +CBMode = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfClearFilterSel' +CBPerfClearFilterSel__enumvalues = { + 0: 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 1: 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', +} +CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0 +CB_PERF_CLEAR_FILTER_SEL_CLEAR = 1 +CBPerfClearFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfOpFilterSel' +CBPerfOpFilterSel__enumvalues = { + 0: 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 1: 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 2: 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 3: 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 4: 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 5: 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', +} +CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0 +CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 1 +CB_PERF_OP_FILTER_SEL_RESOLVE = 2 +CB_PERF_OP_FILTER_SEL_DECOMPRESS = 3 +CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 4 +CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 5 +CBPerfOpFilterSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBPerfSel' +CBPerfSel__enumvalues = { + 0: 'CB_PERF_SEL_NONE', + 1: 'CB_PERF_SEL_DRAWN_PIXEL', + 2: 'CB_PERF_SEL_DRAWN_QUAD', + 3: 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', + 4: 'CB_PERF_SEL_DRAWN_TILE', + 5: 'CB_PERF_SEL_FILTER_DRAWN_PIXEL', + 6: 'CB_PERF_SEL_FILTER_DRAWN_QUAD', + 7: 'CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT', + 8: 'CB_PERF_SEL_FILTER_DRAWN_TILE', + 9: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN', + 10: 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT', + 11: 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN', + 12: 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT', + 13: 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', + 14: 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', + 15: 'CB_PERF_SEL_CC_MC_READ_REQUEST', + 16: 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', + 17: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', + 18: 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', + 19: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', + 20: 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', + 21: 'CB_PERF_SEL_RESERVED_21', + 22: 'CB_PERF_SEL_RESERVED_22', + 23: 'CB_PERF_SEL_RESERVED_23', + 24: 'CB_PERF_SEL_RESERVED_24', + 25: 'CB_PERF_SEL_RESERVED_25', + 26: 'CB_PERF_SEL_RESERVED_26', + 27: 'CB_PERF_SEL_RESERVED_27', + 28: 'CB_PERF_SEL_RESERVED_28', + 29: 'CB_PERF_SEL_RESERVED_29', + 30: 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY', + 31: 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB', + 32: 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY', + 33: 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB', + 34: 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY', + 35: 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB', + 36: 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY', + 37: 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB', + 38: 'CB_PERF_SEL_RESERVED_38', + 39: 'CB_PERF_SEL_RESERVED_39', + 40: 'CB_PERF_SEL_RESERVED_40', + 41: 'CB_PERF_SEL_RESERVED_41', + 42: 'CB_PERF_SEL_RESERVED_42', + 43: 'CB_PERF_SEL_RESERVED_43', + 44: 'CB_PERF_SEL_RESERVED_44', + 45: 'CB_PERF_SEL_RESERVED_45', + 46: 'CB_PERF_SEL_RESERVED_46', + 47: 'CB_PERF_SEL_RESERVED_47', + 48: 'CB_PERF_SEL_RESERVED_48', + 49: 'CB_PERF_SEL_RESERVED_49', + 50: 'CB_PERF_SEL_STATIC_CLOCK_EN', + 51: 'CB_PERF_SEL_PERFMON_CLOCK_EN', + 52: 'CB_PERF_SEL_BLEND_CLOCK_EN', + 53: 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', + 54: 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', + 55: 'CB_PERF_SEL_GRBM_CLOCK_EN', + 56: 'CB_PERF_SEL_MEMARB_CLOCK_EN', + 57: 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', + 58: 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', + 59: 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', + 60: 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', + 61: 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', + 62: 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', + 63: 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', + 64: 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', + 65: 'CB_PERF_SEL_RESERVED_65', + 66: 'CB_PERF_SEL_RESERVED_66', + 67: 'CB_PERF_SEL_RESERVED_67', + 68: 'CB_PERF_SEL_RESERVED_68', + 69: 'CB_PERF_SEL_RESERVED_69', + 70: 'CB_PERF_SEL_RESERVED_70', + 71: 'CB_PERF_SEL_RESERVED_71', + 72: 'CB_PERF_SEL_RESERVED_72', + 73: 'CB_PERF_SEL_RESERVED_73', + 74: 'CB_PERF_SEL_RESERVED_74', + 75: 'CB_PERF_SEL_RESERVED_75', + 76: 'CB_PERF_SEL_RESERVED_76', + 77: 'CB_PERF_SEL_RESERVED_77', + 78: 'CB_PERF_SEL_RESERVED_78', + 79: 'CB_PERF_SEL_RESERVED_79', + 80: 'CB_PERF_SEL_RESERVED_80', + 81: 'CB_PERF_SEL_RESERVED_81', + 82: 'CB_PERF_SEL_RESERVED_82', + 83: 'CB_PERF_SEL_RESERVED_83', + 84: 'CB_PERF_SEL_RESERVED_84', + 85: 'CB_PERF_SEL_RESERVED_85', + 86: 'CB_PERF_SEL_RESERVED_86', + 87: 'CB_PERF_SEL_RESERVED_87', + 88: 'CB_PERF_SEL_RESERVED_88', + 89: 'CB_PERF_SEL_RESERVED_89', + 90: 'CB_PERF_SEL_RESERVED_90', + 91: 'CB_PERF_SEL_RESERVED_91', + 92: 'CB_PERF_SEL_RESERVED_92', + 93: 'CB_PERF_SEL_RESERVED_93', + 94: 'CB_PERF_SEL_RESERVED_94', + 95: 'CB_PERF_SEL_RESERVED_95', + 96: 'CB_PERF_SEL_RESERVED_96', + 97: 'CB_PERF_SEL_RESERVED_97', + 98: 'CB_PERF_SEL_RESERVED_98', + 99: 'CB_PERF_SEL_RESERVED_99', + 100: 'CB_PERF_SEL_CC_TAG_HIT', + 101: 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 102: 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', + 103: 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', + 104: 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', + 105: 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 106: 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', + 107: 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 108: 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 109: 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 110: 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 111: 'CB_PERF_SEL_CC_CACHE_STALL', + 112: 'CB_PERF_SEL_CC_CACHE_FLUSH', + 113: 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', + 114: 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 115: 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 116: 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', + 117: 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 118: 'CB_PERF_SEL_RESERVED_118', + 119: 'CB_PERF_SEL_RESERVED_119', + 120: 'CB_PERF_SEL_RESERVED_120', + 121: 'CB_PERF_SEL_RESERVED_121', + 122: 'CB_PERF_SEL_RESERVED_122', + 123: 'CB_PERF_SEL_RESERVED_123', + 124: 'CB_PERF_SEL_RESERVED_124', + 125: 'CB_PERF_SEL_RESERVED_125', + 126: 'CB_PERF_SEL_RESERVED_126', + 127: 'CB_PERF_SEL_RESERVED_127', + 128: 'CB_PERF_SEL_RESERVED_128', + 129: 'CB_PERF_SEL_RESERVED_129', + 130: 'CB_PERF_SEL_RESERVED_130', + 131: 'CB_PERF_SEL_RESERVED_131', + 132: 'CB_PERF_SEL_RESERVED_132', + 133: 'CB_PERF_SEL_RESERVED_133', + 134: 'CB_PERF_SEL_RESERVED_134', + 135: 'CB_PERF_SEL_RESERVED_135', + 136: 'CB_PERF_SEL_RESERVED_136', + 137: 'CB_PERF_SEL_RESERVED_137', + 138: 'CB_PERF_SEL_RESERVED_138', + 139: 'CB_PERF_SEL_RESERVED_139', + 140: 'CB_PERF_SEL_RESERVED_140', + 141: 'CB_PERF_SEL_RESERVED_141', + 142: 'CB_PERF_SEL_RESERVED_142', + 143: 'CB_PERF_SEL_RESERVED_143', + 144: 'CB_PERF_SEL_RESERVED_144', + 145: 'CB_PERF_SEL_RESERVED_145', + 146: 'CB_PERF_SEL_RESERVED_146', + 147: 'CB_PERF_SEL_RESERVED_147', + 148: 'CB_PERF_SEL_RESERVED_148', + 149: 'CB_PERF_SEL_RESERVED_149', + 150: 'CB_PERF_SEL_DCC_CACHE_PERF_HIT', + 151: 'CB_PERF_SEL_DCC_CACHE_TAG_MISS', + 152: 'CB_PERF_SEL_DCC_CACHE_SECTOR_MISS', + 153: 'CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL', + 154: 'CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 155: 'CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', + 156: 'CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 157: 'CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL', + 158: 'CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL', + 159: 'CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL', + 160: 'CB_PERF_SEL_DCC_CACHE_STALL', + 161: 'CB_PERF_SEL_DCC_CACHE_FLUSH', + 162: 'CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED', + 163: 'CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED', + 164: 'CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED', + 165: 'CB_PERF_SEL_RESERVED_165', + 166: 'CB_PERF_SEL_RESERVED_166', + 167: 'CB_PERF_SEL_RESERVED_167', + 168: 'CB_PERF_SEL_RESERVED_168', + 169: 'CB_PERF_SEL_RESERVED_169', + 170: 'CB_PERF_SEL_RESERVED_170', + 171: 'CB_PERF_SEL_RESERVED_171', + 172: 'CB_PERF_SEL_RESERVED_172', + 173: 'CB_PERF_SEL_RESERVED_173', + 174: 'CB_PERF_SEL_RESERVED_174', + 175: 'CB_PERF_SEL_RESERVED_175', + 176: 'CB_PERF_SEL_RESERVED_176', + 177: 'CB_PERF_SEL_RESERVED_177', + 178: 'CB_PERF_SEL_RESERVED_178', + 179: 'CB_PERF_SEL_RESERVED_179', + 180: 'CB_PERF_SEL_RESERVED_180', + 181: 'CB_PERF_SEL_RESERVED_181', + 182: 'CB_PERF_SEL_RESERVED_182', + 183: 'CB_PERF_SEL_RESERVED_183', + 184: 'CB_PERF_SEL_RESERVED_184', + 185: 'CB_PERF_SEL_RESERVED_185', + 186: 'CB_PERF_SEL_RESERVED_186', + 187: 'CB_PERF_SEL_RESERVED_187', + 188: 'CB_PERF_SEL_RESERVED_188', + 189: 'CB_PERF_SEL_RESERVED_189', + 190: 'CB_PERF_SEL_RESERVED_190', + 191: 'CB_PERF_SEL_RESERVED_191', + 192: 'CB_PERF_SEL_RESERVED_192', + 193: 'CB_PERF_SEL_RESERVED_193', + 194: 'CB_PERF_SEL_RESERVED_194', + 195: 'CB_PERF_SEL_RESERVED_195', + 196: 'CB_PERF_SEL_RESERVED_196', + 197: 'CB_PERF_SEL_RESERVED_197', + 198: 'CB_PERF_SEL_RESERVED_198', + 199: 'CB_PERF_SEL_RESERVED_199', + 200: 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 201: 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 202: 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', + 203: 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', + 204: 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', + 205: 'CB_PERF_SEL_RESERVED_205', + 206: 'CB_PERF_SEL_RESERVED_206', + 207: 'CB_PERF_SEL_RESERVED_207', + 208: 'CB_PERF_SEL_RESERVED_208', + 209: 'CB_PERF_SEL_RESERVED_209', + 210: 'CB_PERF_SEL_RESERVED_210', + 211: 'CB_PERF_SEL_RESERVED_211', + 212: 'CB_PERF_SEL_RESERVED_212', + 213: 'CB_PERF_SEL_RESERVED_213', + 214: 'CB_PERF_SEL_RESERVED_214', + 215: 'CB_PERF_SEL_RESERVED_215', + 216: 'CB_PERF_SEL_RESERVED_216', + 217: 'CB_PERF_SEL_RESERVED_217', + 218: 'CB_PERF_SEL_RESERVED_218', + 219: 'CB_PERF_SEL_RESERVED_219', + 220: 'CB_PERF_SEL_RESERVED_220', + 221: 'CB_PERF_SEL_RESERVED_221', + 222: 'CB_PERF_SEL_RESERVED_222', + 223: 'CB_PERF_SEL_RESERVED_223', + 224: 'CB_PERF_SEL_RESERVED_224', + 225: 'CB_PERF_SEL_RESERVED_225', + 226: 'CB_PERF_SEL_RESERVED_226', + 227: 'CB_PERF_SEL_RESERVED_227', + 228: 'CB_PERF_SEL_RESERVED_228', + 229: 'CB_PERF_SEL_RESERVED_229', + 230: 'CB_PERF_SEL_RESERVED_230', + 231: 'CB_PERF_SEL_RESERVED_231', + 232: 'CB_PERF_SEL_RESERVED_232', + 233: 'CB_PERF_SEL_RESERVED_233', + 234: 'CB_PERF_SEL_RESERVED_234', + 235: 'CB_PERF_SEL_RESERVED_235', + 236: 'CB_PERF_SEL_RESERVED_236', + 237: 'CB_PERF_SEL_RESERVED_237', + 238: 'CB_PERF_SEL_RESERVED_238', + 239: 'CB_PERF_SEL_RESERVED_239', + 240: 'CB_PERF_SEL_RESERVED_240', + 241: 'CB_PERF_SEL_RESERVED_241', + 242: 'CB_PERF_SEL_RESERVED_242', + 243: 'CB_PERF_SEL_RESERVED_243', + 244: 'CB_PERF_SEL_RESERVED_244', + 245: 'CB_PERF_SEL_RESERVED_245', + 246: 'CB_PERF_SEL_RESERVED_246', + 247: 'CB_PERF_SEL_RESERVED_247', + 248: 'CB_PERF_SEL_RESERVED_248', + 249: 'CB_PERF_SEL_RESERVED_249', + 250: 'CB_PERF_SEL_EVENT', + 251: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 252: 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 253: 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 254: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 255: 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 256: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 257: 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 258: 'CB_PERF_SEL_CC_SURFACE_SYNC', + 259: 'CB_PERF_SEL_RESERVED_259', + 260: 'CB_PERF_SEL_RESERVED_260', + 261: 'CB_PERF_SEL_RESERVED_261', + 262: 'CB_PERF_SEL_RESERVED_262', + 263: 'CB_PERF_SEL_RESERVED_263', + 264: 'CB_PERF_SEL_RESERVED_264', + 265: 'CB_PERF_SEL_RESERVED_265', + 266: 'CB_PERF_SEL_RESERVED_266', + 267: 'CB_PERF_SEL_RESERVED_267', + 268: 'CB_PERF_SEL_RESERVED_268', + 269: 'CB_PERF_SEL_RESERVED_269', + 270: 'CB_PERF_SEL_RESERVED_270', + 271: 'CB_PERF_SEL_RESERVED_271', + 272: 'CB_PERF_SEL_RESERVED_272', + 273: 'CB_PERF_SEL_RESERVED_273', + 274: 'CB_PERF_SEL_RESERVED_274', + 275: 'CB_PERF_SEL_RESERVED_275', + 276: 'CB_PERF_SEL_RESERVED_276', + 277: 'CB_PERF_SEL_RESERVED_277', + 278: 'CB_PERF_SEL_RESERVED_278', + 279: 'CB_PERF_SEL_RESERVED_279', + 280: 'CB_PERF_SEL_RESERVED_280', + 281: 'CB_PERF_SEL_RESERVED_281', + 282: 'CB_PERF_SEL_RESERVED_282', + 283: 'CB_PERF_SEL_RESERVED_283', + 284: 'CB_PERF_SEL_RESERVED_284', + 285: 'CB_PERF_SEL_RESERVED_285', + 286: 'CB_PERF_SEL_RESERVED_286', + 287: 'CB_PERF_SEL_RESERVED_287', + 288: 'CB_PERF_SEL_RESERVED_288', + 289: 'CB_PERF_SEL_RESERVED_289', + 290: 'CB_PERF_SEL_RESERVED_290', + 291: 'CB_PERF_SEL_RESERVED_291', + 292: 'CB_PERF_SEL_RESERVED_292', + 293: 'CB_PERF_SEL_RESERVED_293', + 294: 'CB_PERF_SEL_RESERVED_294', + 295: 'CB_PERF_SEL_RESERVED_295', + 296: 'CB_PERF_SEL_RESERVED_296', + 297: 'CB_PERF_SEL_RESERVED_297', + 298: 'CB_PERF_SEL_RESERVED_298', + 299: 'CB_PERF_SEL_RESERVED_299', + 300: 'CB_PERF_SEL_NACK_CC_READ', + 301: 'CB_PERF_SEL_NACK_CC_WRITE', + 302: 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', + 303: 'CB_PERF_SEL_RESERVED_303', + 304: 'CB_PERF_SEL_RESERVED_304', + 305: 'CB_PERF_SEL_RESERVED_305', + 306: 'CB_PERF_SEL_RESERVED_306', + 307: 'CB_PERF_SEL_RESERVED_307', + 308: 'CB_PERF_SEL_RESERVED_308', + 309: 'CB_PERF_SEL_RESERVED_309', + 310: 'CB_PERF_SEL_RESERVED_310', + 311: 'CB_PERF_SEL_RESERVED_311', + 312: 'CB_PERF_SEL_RESERVED_312', + 313: 'CB_PERF_SEL_RESERVED_313', + 314: 'CB_PERF_SEL_RESERVED_314', + 315: 'CB_PERF_SEL_RESERVED_315', + 316: 'CB_PERF_SEL_RESERVED_316', + 317: 'CB_PERF_SEL_RESERVED_317', + 318: 'CB_PERF_SEL_RESERVED_318', + 319: 'CB_PERF_SEL_RESERVED_319', + 320: 'CB_PERF_SEL_RESERVED_320', + 321: 'CB_PERF_SEL_RESERVED_321', + 322: 'CB_PERF_SEL_RESERVED_322', + 323: 'CB_PERF_SEL_RESERVED_323', + 324: 'CB_PERF_SEL_RESERVED_324', + 325: 'CB_PERF_SEL_RESERVED_325', + 326: 'CB_PERF_SEL_RESERVED_326', + 327: 'CB_PERF_SEL_RESERVED_327', + 328: 'CB_PERF_SEL_RESERVED_328', + 329: 'CB_PERF_SEL_RESERVED_329', + 330: 'CB_PERF_SEL_RESERVED_330', + 331: 'CB_PERF_SEL_RESERVED_331', + 332: 'CB_PERF_SEL_RESERVED_332', + 333: 'CB_PERF_SEL_RESERVED_333', + 334: 'CB_PERF_SEL_RESERVED_334', + 335: 'CB_PERF_SEL_RESERVED_335', + 336: 'CB_PERF_SEL_RESERVED_336', + 337: 'CB_PERF_SEL_RESERVED_337', + 338: 'CB_PERF_SEL_RESERVED_338', + 339: 'CB_PERF_SEL_RESERVED_339', + 340: 'CB_PERF_SEL_RESERVED_340', + 341: 'CB_PERF_SEL_RESERVED_341', + 342: 'CB_PERF_SEL_RESERVED_342', + 343: 'CB_PERF_SEL_RESERVED_343', + 344: 'CB_PERF_SEL_RESERVED_344', + 345: 'CB_PERF_SEL_RESERVED_345', + 346: 'CB_PERF_SEL_RESERVED_346', + 347: 'CB_PERF_SEL_RESERVED_347', + 348: 'CB_PERF_SEL_RESERVED_348', + 349: 'CB_PERF_SEL_RESERVED_349', + 350: 'CB_PERF_SEL_RESERVED_350', + 351: 'CB_PERF_SEL_RESERVED_351', + 352: 'CB_PERF_SEL_RESERVED_352', + 353: 'CB_PERF_SEL_RESERVED_353', + 354: 'CB_PERF_SEL_RESERVED_354', + 355: 'CB_PERF_SEL_RESERVED_355', + 356: 'CB_PERF_SEL_RESERVED_356', + 357: 'CB_PERF_SEL_RESERVED_357', + 358: 'CB_PERF_SEL_RESERVED_358', + 359: 'CB_PERF_SEL_RESERVED_359', + 360: 'CB_PERF_SEL_RESERVED_360', + 361: 'CB_PERF_SEL_RESERVED_361', + 362: 'CB_PERF_SEL_RESERVED_362', + 363: 'CB_PERF_SEL_RESERVED_363', + 364: 'CB_PERF_SEL_RESERVED_364', + 365: 'CB_PERF_SEL_RESERVED_365', + 366: 'CB_PERF_SEL_RESERVED_366', + 367: 'CB_PERF_SEL_RESERVED_367', + 368: 'CB_PERF_SEL_RESERVED_368', + 369: 'CB_PERF_SEL_RESERVED_369', + 370: 'CB_PERF_SEL_RESERVED_370', + 371: 'CB_PERF_SEL_RESERVED_371', + 372: 'CB_PERF_SEL_RESERVED_372', + 373: 'CB_PERF_SEL_RESERVED_373', + 374: 'CB_PERF_SEL_RESERVED_374', + 375: 'CB_PERF_SEL_RESERVED_375', + 376: 'CB_PERF_SEL_RESERVED_376', + 377: 'CB_PERF_SEL_RESERVED_377', + 378: 'CB_PERF_SEL_RESERVED_378', + 379: 'CB_PERF_SEL_RESERVED_379', + 380: 'CB_PERF_SEL_RESERVED_380', + 381: 'CB_PERF_SEL_RESERVED_381', + 382: 'CB_PERF_SEL_RESERVED_382', + 383: 'CB_PERF_SEL_RESERVED_383', + 384: 'CB_PERF_SEL_RESERVED_384', + 385: 'CB_PERF_SEL_RESERVED_385', + 386: 'CB_PERF_SEL_RESERVED_386', + 387: 'CB_PERF_SEL_RESERVED_387', + 388: 'CB_PERF_SEL_RESERVED_388', + 389: 'CB_PERF_SEL_RESERVED_389', + 390: 'CB_PERF_SEL_RESERVED_390', + 391: 'CB_PERF_SEL_RESERVED_391', + 392: 'CB_PERF_SEL_RESERVED_392', + 393: 'CB_PERF_SEL_RESERVED_393', + 394: 'CB_PERF_SEL_RESERVED_394', + 395: 'CB_PERF_SEL_RESERVED_395', + 396: 'CB_PERF_SEL_RESERVED_396', + 397: 'CB_PERF_SEL_RESERVED_397', + 398: 'CB_PERF_SEL_RESERVED_398', + 399: 'CB_PERF_SEL_RESERVED_399', + 400: 'CB_PERF_SEL_RESERVED_400', + 401: 'CB_PERF_SEL_RESERVED_401', + 402: 'CB_PERF_SEL_RESERVED_402', + 403: 'CB_PERF_SEL_RESERVED_403', + 404: 'CB_PERF_SEL_RESERVED_404', + 405: 'CB_PERF_SEL_RESERVED_405', + 406: 'CB_PERF_SEL_RESERVED_406', + 407: 'CB_PERF_SEL_RESERVED_407', + 408: 'CB_PERF_SEL_RESERVED_408', + 409: 'CB_PERF_SEL_RESERVED_409', + 410: 'CB_PERF_SEL_RESERVED_410', + 411: 'CB_PERF_SEL_RESERVED_411', + 412: 'CB_PERF_SEL_RESERVED_412', + 413: 'CB_PERF_SEL_RESERVED_413', + 414: 'CB_PERF_SEL_RESERVED_414', + 415: 'CB_PERF_SEL_RESERVED_415', + 416: 'CB_PERF_SEL_RESERVED_416', + 417: 'CB_PERF_SEL_RESERVED_417', + 418: 'CB_PERF_SEL_RESERVED_418', + 419: 'CB_PERF_SEL_RESERVED_419', + 420: 'CB_PERF_SEL_RESERVED_420', + 421: 'CB_PERF_SEL_RESERVED_421', + 422: 'CB_PERF_SEL_RESERVED_422', + 423: 'CB_PERF_SEL_RESERVED_423', + 424: 'CB_PERF_SEL_RESERVED_424', + 425: 'CB_PERF_SEL_RESERVED_425', + 426: 'CB_PERF_SEL_RESERVED_426', + 427: 'CB_PERF_SEL_RESERVED_427', + 428: 'CB_PERF_SEL_RESERVED_428', + 429: 'CB_PERF_SEL_RESERVED_429', + 430: 'CB_PERF_SEL_RESERVED_430', + 431: 'CB_PERF_SEL_RESERVED_431', + 432: 'CB_PERF_SEL_RESERVED_432', + 433: 'CB_PERF_SEL_RESERVED_433', + 434: 'CB_PERF_SEL_RESERVED_434', + 435: 'CB_PERF_SEL_RESERVED_435', + 436: 'CB_PERF_SEL_RESERVED_436', + 437: 'CB_PERF_SEL_RESERVED_437', + 438: 'CB_PERF_SEL_RESERVED_438', + 439: 'CB_PERF_SEL_RESERVED_439', + 440: 'CB_PERF_SEL_RESERVED_440', + 441: 'CB_PERF_SEL_RESERVED_441', + 442: 'CB_PERF_SEL_RESERVED_442', + 443: 'CB_PERF_SEL_RESERVED_443', + 444: 'CB_PERF_SEL_RESERVED_444', + 445: 'CB_PERF_SEL_RESERVED_445', + 446: 'CB_PERF_SEL_RESERVED_446', + 447: 'CB_PERF_SEL_RESERVED_447', + 448: 'CB_PERF_SEL_RESERVED_448', + 449: 'CB_PERF_SEL_RESERVED_449', + 450: 'CB_PERF_SEL_RESERVED_450', + 451: 'CB_PERF_SEL_RESERVED_451', + 452: 'CB_PERF_SEL_RESERVED_452', + 453: 'CB_PERF_SEL_RESERVED_453', + 454: 'CB_PERF_SEL_RESERVED_454', + 455: 'CB_PERF_SEL_RESERVED_455', + 456: 'CB_PERF_SEL_RESERVED_456', + 457: 'CB_PERF_SEL_RESERVED_457', + 458: 'CB_PERF_SEL_RESERVED_458', + 459: 'CB_PERF_SEL_RESERVED_459', + 460: 'CB_PERF_SEL_RESERVED_460', + 461: 'CB_PERF_SEL_RESERVED_461', + 462: 'CB_PERF_SEL_RESERVED_462', + 463: 'CB_PERF_SEL_RESERVED_463', + 464: 'CB_PERF_SEL_RESERVED_464', + 465: 'CB_PERF_SEL_RESERVED_465', +} +CB_PERF_SEL_NONE = 0 +CB_PERF_SEL_DRAWN_PIXEL = 1 +CB_PERF_SEL_DRAWN_QUAD = 2 +CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 3 +CB_PERF_SEL_DRAWN_TILE = 4 +CB_PERF_SEL_FILTER_DRAWN_PIXEL = 5 +CB_PERF_SEL_FILTER_DRAWN_QUAD = 6 +CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT = 7 +CB_PERF_SEL_FILTER_DRAWN_TILE = 8 +CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN = 9 +CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT = 10 +CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN = 11 +CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT = 12 +CB_PERF_SEL_CC_MC_WRITE_REQUEST = 13 +CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 14 +CB_PERF_SEL_CC_MC_READ_REQUEST = 15 +CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 16 +CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 17 +CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 18 +CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 19 +CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 20 +CB_PERF_SEL_RESERVED_21 = 21 +CB_PERF_SEL_RESERVED_22 = 22 +CB_PERF_SEL_RESERVED_23 = 23 +CB_PERF_SEL_RESERVED_24 = 24 +CB_PERF_SEL_RESERVED_25 = 25 +CB_PERF_SEL_RESERVED_26 = 26 +CB_PERF_SEL_RESERVED_27 = 27 +CB_PERF_SEL_RESERVED_28 = 28 +CB_PERF_SEL_RESERVED_29 = 29 +CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY = 30 +CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB = 31 +CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY = 32 +CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB = 33 +CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY = 34 +CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB = 35 +CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY = 36 +CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB = 37 +CB_PERF_SEL_RESERVED_38 = 38 +CB_PERF_SEL_RESERVED_39 = 39 +CB_PERF_SEL_RESERVED_40 = 40 +CB_PERF_SEL_RESERVED_41 = 41 +CB_PERF_SEL_RESERVED_42 = 42 +CB_PERF_SEL_RESERVED_43 = 43 +CB_PERF_SEL_RESERVED_44 = 44 +CB_PERF_SEL_RESERVED_45 = 45 +CB_PERF_SEL_RESERVED_46 = 46 +CB_PERF_SEL_RESERVED_47 = 47 +CB_PERF_SEL_RESERVED_48 = 48 +CB_PERF_SEL_RESERVED_49 = 49 +CB_PERF_SEL_STATIC_CLOCK_EN = 50 +CB_PERF_SEL_PERFMON_CLOCK_EN = 51 +CB_PERF_SEL_BLEND_CLOCK_EN = 52 +CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 53 +CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 54 +CB_PERF_SEL_GRBM_CLOCK_EN = 55 +CB_PERF_SEL_MEMARB_CLOCK_EN = 56 +CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 57 +CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 58 +CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 59 +CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 60 +CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 61 +CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 62 +CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 63 +CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 64 +CB_PERF_SEL_RESERVED_65 = 65 +CB_PERF_SEL_RESERVED_66 = 66 +CB_PERF_SEL_RESERVED_67 = 67 +CB_PERF_SEL_RESERVED_68 = 68 +CB_PERF_SEL_RESERVED_69 = 69 +CB_PERF_SEL_RESERVED_70 = 70 +CB_PERF_SEL_RESERVED_71 = 71 +CB_PERF_SEL_RESERVED_72 = 72 +CB_PERF_SEL_RESERVED_73 = 73 +CB_PERF_SEL_RESERVED_74 = 74 +CB_PERF_SEL_RESERVED_75 = 75 +CB_PERF_SEL_RESERVED_76 = 76 +CB_PERF_SEL_RESERVED_77 = 77 +CB_PERF_SEL_RESERVED_78 = 78 +CB_PERF_SEL_RESERVED_79 = 79 +CB_PERF_SEL_RESERVED_80 = 80 +CB_PERF_SEL_RESERVED_81 = 81 +CB_PERF_SEL_RESERVED_82 = 82 +CB_PERF_SEL_RESERVED_83 = 83 +CB_PERF_SEL_RESERVED_84 = 84 +CB_PERF_SEL_RESERVED_85 = 85 +CB_PERF_SEL_RESERVED_86 = 86 +CB_PERF_SEL_RESERVED_87 = 87 +CB_PERF_SEL_RESERVED_88 = 88 +CB_PERF_SEL_RESERVED_89 = 89 +CB_PERF_SEL_RESERVED_90 = 90 +CB_PERF_SEL_RESERVED_91 = 91 +CB_PERF_SEL_RESERVED_92 = 92 +CB_PERF_SEL_RESERVED_93 = 93 +CB_PERF_SEL_RESERVED_94 = 94 +CB_PERF_SEL_RESERVED_95 = 95 +CB_PERF_SEL_RESERVED_96 = 96 +CB_PERF_SEL_RESERVED_97 = 97 +CB_PERF_SEL_RESERVED_98 = 98 +CB_PERF_SEL_RESERVED_99 = 99 +CB_PERF_SEL_CC_TAG_HIT = 100 +CB_PERF_SEL_CC_CACHE_TAG_MISS = 101 +CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 102 +CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 103 +CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 104 +CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 105 +CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 106 +CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 107 +CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 108 +CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 109 +CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 110 +CB_PERF_SEL_CC_CACHE_STALL = 111 +CB_PERF_SEL_CC_CACHE_FLUSH = 112 +CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 113 +CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 114 +CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 115 +CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 116 +CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 117 +CB_PERF_SEL_RESERVED_118 = 118 +CB_PERF_SEL_RESERVED_119 = 119 +CB_PERF_SEL_RESERVED_120 = 120 +CB_PERF_SEL_RESERVED_121 = 121 +CB_PERF_SEL_RESERVED_122 = 122 +CB_PERF_SEL_RESERVED_123 = 123 +CB_PERF_SEL_RESERVED_124 = 124 +CB_PERF_SEL_RESERVED_125 = 125 +CB_PERF_SEL_RESERVED_126 = 126 +CB_PERF_SEL_RESERVED_127 = 127 +CB_PERF_SEL_RESERVED_128 = 128 +CB_PERF_SEL_RESERVED_129 = 129 +CB_PERF_SEL_RESERVED_130 = 130 +CB_PERF_SEL_RESERVED_131 = 131 +CB_PERF_SEL_RESERVED_132 = 132 +CB_PERF_SEL_RESERVED_133 = 133 +CB_PERF_SEL_RESERVED_134 = 134 +CB_PERF_SEL_RESERVED_135 = 135 +CB_PERF_SEL_RESERVED_136 = 136 +CB_PERF_SEL_RESERVED_137 = 137 +CB_PERF_SEL_RESERVED_138 = 138 +CB_PERF_SEL_RESERVED_139 = 139 +CB_PERF_SEL_RESERVED_140 = 140 +CB_PERF_SEL_RESERVED_141 = 141 +CB_PERF_SEL_RESERVED_142 = 142 +CB_PERF_SEL_RESERVED_143 = 143 +CB_PERF_SEL_RESERVED_144 = 144 +CB_PERF_SEL_RESERVED_145 = 145 +CB_PERF_SEL_RESERVED_146 = 146 +CB_PERF_SEL_RESERVED_147 = 147 +CB_PERF_SEL_RESERVED_148 = 148 +CB_PERF_SEL_RESERVED_149 = 149 +CB_PERF_SEL_DCC_CACHE_PERF_HIT = 150 +CB_PERF_SEL_DCC_CACHE_TAG_MISS = 151 +CB_PERF_SEL_DCC_CACHE_SECTOR_MISS = 152 +CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL = 153 +CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 154 +CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 155 +CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 156 +CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL = 157 +CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL = 158 +CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL = 159 +CB_PERF_SEL_DCC_CACHE_STALL = 160 +CB_PERF_SEL_DCC_CACHE_FLUSH = 161 +CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED = 162 +CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 163 +CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED = 164 +CB_PERF_SEL_RESERVED_165 = 165 +CB_PERF_SEL_RESERVED_166 = 166 +CB_PERF_SEL_RESERVED_167 = 167 +CB_PERF_SEL_RESERVED_168 = 168 +CB_PERF_SEL_RESERVED_169 = 169 +CB_PERF_SEL_RESERVED_170 = 170 +CB_PERF_SEL_RESERVED_171 = 171 +CB_PERF_SEL_RESERVED_172 = 172 +CB_PERF_SEL_RESERVED_173 = 173 +CB_PERF_SEL_RESERVED_174 = 174 +CB_PERF_SEL_RESERVED_175 = 175 +CB_PERF_SEL_RESERVED_176 = 176 +CB_PERF_SEL_RESERVED_177 = 177 +CB_PERF_SEL_RESERVED_178 = 178 +CB_PERF_SEL_RESERVED_179 = 179 +CB_PERF_SEL_RESERVED_180 = 180 +CB_PERF_SEL_RESERVED_181 = 181 +CB_PERF_SEL_RESERVED_182 = 182 +CB_PERF_SEL_RESERVED_183 = 183 +CB_PERF_SEL_RESERVED_184 = 184 +CB_PERF_SEL_RESERVED_185 = 185 +CB_PERF_SEL_RESERVED_186 = 186 +CB_PERF_SEL_RESERVED_187 = 187 +CB_PERF_SEL_RESERVED_188 = 188 +CB_PERF_SEL_RESERVED_189 = 189 +CB_PERF_SEL_RESERVED_190 = 190 +CB_PERF_SEL_RESERVED_191 = 191 +CB_PERF_SEL_RESERVED_192 = 192 +CB_PERF_SEL_RESERVED_193 = 193 +CB_PERF_SEL_RESERVED_194 = 194 +CB_PERF_SEL_RESERVED_195 = 195 +CB_PERF_SEL_RESERVED_196 = 196 +CB_PERF_SEL_RESERVED_197 = 197 +CB_PERF_SEL_RESERVED_198 = 198 +CB_PERF_SEL_RESERVED_199 = 199 +CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 200 +CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 201 +CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 202 +CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 203 +CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 204 +CB_PERF_SEL_RESERVED_205 = 205 +CB_PERF_SEL_RESERVED_206 = 206 +CB_PERF_SEL_RESERVED_207 = 207 +CB_PERF_SEL_RESERVED_208 = 208 +CB_PERF_SEL_RESERVED_209 = 209 +CB_PERF_SEL_RESERVED_210 = 210 +CB_PERF_SEL_RESERVED_211 = 211 +CB_PERF_SEL_RESERVED_212 = 212 +CB_PERF_SEL_RESERVED_213 = 213 +CB_PERF_SEL_RESERVED_214 = 214 +CB_PERF_SEL_RESERVED_215 = 215 +CB_PERF_SEL_RESERVED_216 = 216 +CB_PERF_SEL_RESERVED_217 = 217 +CB_PERF_SEL_RESERVED_218 = 218 +CB_PERF_SEL_RESERVED_219 = 219 +CB_PERF_SEL_RESERVED_220 = 220 +CB_PERF_SEL_RESERVED_221 = 221 +CB_PERF_SEL_RESERVED_222 = 222 +CB_PERF_SEL_RESERVED_223 = 223 +CB_PERF_SEL_RESERVED_224 = 224 +CB_PERF_SEL_RESERVED_225 = 225 +CB_PERF_SEL_RESERVED_226 = 226 +CB_PERF_SEL_RESERVED_227 = 227 +CB_PERF_SEL_RESERVED_228 = 228 +CB_PERF_SEL_RESERVED_229 = 229 +CB_PERF_SEL_RESERVED_230 = 230 +CB_PERF_SEL_RESERVED_231 = 231 +CB_PERF_SEL_RESERVED_232 = 232 +CB_PERF_SEL_RESERVED_233 = 233 +CB_PERF_SEL_RESERVED_234 = 234 +CB_PERF_SEL_RESERVED_235 = 235 +CB_PERF_SEL_RESERVED_236 = 236 +CB_PERF_SEL_RESERVED_237 = 237 +CB_PERF_SEL_RESERVED_238 = 238 +CB_PERF_SEL_RESERVED_239 = 239 +CB_PERF_SEL_RESERVED_240 = 240 +CB_PERF_SEL_RESERVED_241 = 241 +CB_PERF_SEL_RESERVED_242 = 242 +CB_PERF_SEL_RESERVED_243 = 243 +CB_PERF_SEL_RESERVED_244 = 244 +CB_PERF_SEL_RESERVED_245 = 245 +CB_PERF_SEL_RESERVED_246 = 246 +CB_PERF_SEL_RESERVED_247 = 247 +CB_PERF_SEL_RESERVED_248 = 248 +CB_PERF_SEL_RESERVED_249 = 249 +CB_PERF_SEL_EVENT = 250 +CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 251 +CB_PERF_SEL_EVENT_CONTEXT_DONE = 252 +CB_PERF_SEL_EVENT_CACHE_FLUSH = 253 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 254 +CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 255 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 256 +CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 257 +CB_PERF_SEL_CC_SURFACE_SYNC = 258 +CB_PERF_SEL_RESERVED_259 = 259 +CB_PERF_SEL_RESERVED_260 = 260 +CB_PERF_SEL_RESERVED_261 = 261 +CB_PERF_SEL_RESERVED_262 = 262 +CB_PERF_SEL_RESERVED_263 = 263 +CB_PERF_SEL_RESERVED_264 = 264 +CB_PERF_SEL_RESERVED_265 = 265 +CB_PERF_SEL_RESERVED_266 = 266 +CB_PERF_SEL_RESERVED_267 = 267 +CB_PERF_SEL_RESERVED_268 = 268 +CB_PERF_SEL_RESERVED_269 = 269 +CB_PERF_SEL_RESERVED_270 = 270 +CB_PERF_SEL_RESERVED_271 = 271 +CB_PERF_SEL_RESERVED_272 = 272 +CB_PERF_SEL_RESERVED_273 = 273 +CB_PERF_SEL_RESERVED_274 = 274 +CB_PERF_SEL_RESERVED_275 = 275 +CB_PERF_SEL_RESERVED_276 = 276 +CB_PERF_SEL_RESERVED_277 = 277 +CB_PERF_SEL_RESERVED_278 = 278 +CB_PERF_SEL_RESERVED_279 = 279 +CB_PERF_SEL_RESERVED_280 = 280 +CB_PERF_SEL_RESERVED_281 = 281 +CB_PERF_SEL_RESERVED_282 = 282 +CB_PERF_SEL_RESERVED_283 = 283 +CB_PERF_SEL_RESERVED_284 = 284 +CB_PERF_SEL_RESERVED_285 = 285 +CB_PERF_SEL_RESERVED_286 = 286 +CB_PERF_SEL_RESERVED_287 = 287 +CB_PERF_SEL_RESERVED_288 = 288 +CB_PERF_SEL_RESERVED_289 = 289 +CB_PERF_SEL_RESERVED_290 = 290 +CB_PERF_SEL_RESERVED_291 = 291 +CB_PERF_SEL_RESERVED_292 = 292 +CB_PERF_SEL_RESERVED_293 = 293 +CB_PERF_SEL_RESERVED_294 = 294 +CB_PERF_SEL_RESERVED_295 = 295 +CB_PERF_SEL_RESERVED_296 = 296 +CB_PERF_SEL_RESERVED_297 = 297 +CB_PERF_SEL_RESERVED_298 = 298 +CB_PERF_SEL_RESERVED_299 = 299 +CB_PERF_SEL_NACK_CC_READ = 300 +CB_PERF_SEL_NACK_CC_WRITE = 301 +CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 302 +CB_PERF_SEL_RESERVED_303 = 303 +CB_PERF_SEL_RESERVED_304 = 304 +CB_PERF_SEL_RESERVED_305 = 305 +CB_PERF_SEL_RESERVED_306 = 306 +CB_PERF_SEL_RESERVED_307 = 307 +CB_PERF_SEL_RESERVED_308 = 308 +CB_PERF_SEL_RESERVED_309 = 309 +CB_PERF_SEL_RESERVED_310 = 310 +CB_PERF_SEL_RESERVED_311 = 311 +CB_PERF_SEL_RESERVED_312 = 312 +CB_PERF_SEL_RESERVED_313 = 313 +CB_PERF_SEL_RESERVED_314 = 314 +CB_PERF_SEL_RESERVED_315 = 315 +CB_PERF_SEL_RESERVED_316 = 316 +CB_PERF_SEL_RESERVED_317 = 317 +CB_PERF_SEL_RESERVED_318 = 318 +CB_PERF_SEL_RESERVED_319 = 319 +CB_PERF_SEL_RESERVED_320 = 320 +CB_PERF_SEL_RESERVED_321 = 321 +CB_PERF_SEL_RESERVED_322 = 322 +CB_PERF_SEL_RESERVED_323 = 323 +CB_PERF_SEL_RESERVED_324 = 324 +CB_PERF_SEL_RESERVED_325 = 325 +CB_PERF_SEL_RESERVED_326 = 326 +CB_PERF_SEL_RESERVED_327 = 327 +CB_PERF_SEL_RESERVED_328 = 328 +CB_PERF_SEL_RESERVED_329 = 329 +CB_PERF_SEL_RESERVED_330 = 330 +CB_PERF_SEL_RESERVED_331 = 331 +CB_PERF_SEL_RESERVED_332 = 332 +CB_PERF_SEL_RESERVED_333 = 333 +CB_PERF_SEL_RESERVED_334 = 334 +CB_PERF_SEL_RESERVED_335 = 335 +CB_PERF_SEL_RESERVED_336 = 336 +CB_PERF_SEL_RESERVED_337 = 337 +CB_PERF_SEL_RESERVED_338 = 338 +CB_PERF_SEL_RESERVED_339 = 339 +CB_PERF_SEL_RESERVED_340 = 340 +CB_PERF_SEL_RESERVED_341 = 341 +CB_PERF_SEL_RESERVED_342 = 342 +CB_PERF_SEL_RESERVED_343 = 343 +CB_PERF_SEL_RESERVED_344 = 344 +CB_PERF_SEL_RESERVED_345 = 345 +CB_PERF_SEL_RESERVED_346 = 346 +CB_PERF_SEL_RESERVED_347 = 347 +CB_PERF_SEL_RESERVED_348 = 348 +CB_PERF_SEL_RESERVED_349 = 349 +CB_PERF_SEL_RESERVED_350 = 350 +CB_PERF_SEL_RESERVED_351 = 351 +CB_PERF_SEL_RESERVED_352 = 352 +CB_PERF_SEL_RESERVED_353 = 353 +CB_PERF_SEL_RESERVED_354 = 354 +CB_PERF_SEL_RESERVED_355 = 355 +CB_PERF_SEL_RESERVED_356 = 356 +CB_PERF_SEL_RESERVED_357 = 357 +CB_PERF_SEL_RESERVED_358 = 358 +CB_PERF_SEL_RESERVED_359 = 359 +CB_PERF_SEL_RESERVED_360 = 360 +CB_PERF_SEL_RESERVED_361 = 361 +CB_PERF_SEL_RESERVED_362 = 362 +CB_PERF_SEL_RESERVED_363 = 363 +CB_PERF_SEL_RESERVED_364 = 364 +CB_PERF_SEL_RESERVED_365 = 365 +CB_PERF_SEL_RESERVED_366 = 366 +CB_PERF_SEL_RESERVED_367 = 367 +CB_PERF_SEL_RESERVED_368 = 368 +CB_PERF_SEL_RESERVED_369 = 369 +CB_PERF_SEL_RESERVED_370 = 370 +CB_PERF_SEL_RESERVED_371 = 371 +CB_PERF_SEL_RESERVED_372 = 372 +CB_PERF_SEL_RESERVED_373 = 373 +CB_PERF_SEL_RESERVED_374 = 374 +CB_PERF_SEL_RESERVED_375 = 375 +CB_PERF_SEL_RESERVED_376 = 376 +CB_PERF_SEL_RESERVED_377 = 377 +CB_PERF_SEL_RESERVED_378 = 378 +CB_PERF_SEL_RESERVED_379 = 379 +CB_PERF_SEL_RESERVED_380 = 380 +CB_PERF_SEL_RESERVED_381 = 381 +CB_PERF_SEL_RESERVED_382 = 382 +CB_PERF_SEL_RESERVED_383 = 383 +CB_PERF_SEL_RESERVED_384 = 384 +CB_PERF_SEL_RESERVED_385 = 385 +CB_PERF_SEL_RESERVED_386 = 386 +CB_PERF_SEL_RESERVED_387 = 387 +CB_PERF_SEL_RESERVED_388 = 388 +CB_PERF_SEL_RESERVED_389 = 389 +CB_PERF_SEL_RESERVED_390 = 390 +CB_PERF_SEL_RESERVED_391 = 391 +CB_PERF_SEL_RESERVED_392 = 392 +CB_PERF_SEL_RESERVED_393 = 393 +CB_PERF_SEL_RESERVED_394 = 394 +CB_PERF_SEL_RESERVED_395 = 395 +CB_PERF_SEL_RESERVED_396 = 396 +CB_PERF_SEL_RESERVED_397 = 397 +CB_PERF_SEL_RESERVED_398 = 398 +CB_PERF_SEL_RESERVED_399 = 399 +CB_PERF_SEL_RESERVED_400 = 400 +CB_PERF_SEL_RESERVED_401 = 401 +CB_PERF_SEL_RESERVED_402 = 402 +CB_PERF_SEL_RESERVED_403 = 403 +CB_PERF_SEL_RESERVED_404 = 404 +CB_PERF_SEL_RESERVED_405 = 405 +CB_PERF_SEL_RESERVED_406 = 406 +CB_PERF_SEL_RESERVED_407 = 407 +CB_PERF_SEL_RESERVED_408 = 408 +CB_PERF_SEL_RESERVED_409 = 409 +CB_PERF_SEL_RESERVED_410 = 410 +CB_PERF_SEL_RESERVED_411 = 411 +CB_PERF_SEL_RESERVED_412 = 412 +CB_PERF_SEL_RESERVED_413 = 413 +CB_PERF_SEL_RESERVED_414 = 414 +CB_PERF_SEL_RESERVED_415 = 415 +CB_PERF_SEL_RESERVED_416 = 416 +CB_PERF_SEL_RESERVED_417 = 417 +CB_PERF_SEL_RESERVED_418 = 418 +CB_PERF_SEL_RESERVED_419 = 419 +CB_PERF_SEL_RESERVED_420 = 420 +CB_PERF_SEL_RESERVED_421 = 421 +CB_PERF_SEL_RESERVED_422 = 422 +CB_PERF_SEL_RESERVED_423 = 423 +CB_PERF_SEL_RESERVED_424 = 424 +CB_PERF_SEL_RESERVED_425 = 425 +CB_PERF_SEL_RESERVED_426 = 426 +CB_PERF_SEL_RESERVED_427 = 427 +CB_PERF_SEL_RESERVED_428 = 428 +CB_PERF_SEL_RESERVED_429 = 429 +CB_PERF_SEL_RESERVED_430 = 430 +CB_PERF_SEL_RESERVED_431 = 431 +CB_PERF_SEL_RESERVED_432 = 432 +CB_PERF_SEL_RESERVED_433 = 433 +CB_PERF_SEL_RESERVED_434 = 434 +CB_PERF_SEL_RESERVED_435 = 435 +CB_PERF_SEL_RESERVED_436 = 436 +CB_PERF_SEL_RESERVED_437 = 437 +CB_PERF_SEL_RESERVED_438 = 438 +CB_PERF_SEL_RESERVED_439 = 439 +CB_PERF_SEL_RESERVED_440 = 440 +CB_PERF_SEL_RESERVED_441 = 441 +CB_PERF_SEL_RESERVED_442 = 442 +CB_PERF_SEL_RESERVED_443 = 443 +CB_PERF_SEL_RESERVED_444 = 444 +CB_PERF_SEL_RESERVED_445 = 445 +CB_PERF_SEL_RESERVED_446 = 446 +CB_PERF_SEL_RESERVED_447 = 447 +CB_PERF_SEL_RESERVED_448 = 448 +CB_PERF_SEL_RESERVED_449 = 449 +CB_PERF_SEL_RESERVED_450 = 450 +CB_PERF_SEL_RESERVED_451 = 451 +CB_PERF_SEL_RESERVED_452 = 452 +CB_PERF_SEL_RESERVED_453 = 453 +CB_PERF_SEL_RESERVED_454 = 454 +CB_PERF_SEL_RESERVED_455 = 455 +CB_PERF_SEL_RESERVED_456 = 456 +CB_PERF_SEL_RESERVED_457 = 457 +CB_PERF_SEL_RESERVED_458 = 458 +CB_PERF_SEL_RESERVED_459 = 459 +CB_PERF_SEL_RESERVED_460 = 460 +CB_PERF_SEL_RESERVED_461 = 461 +CB_PERF_SEL_RESERVED_462 = 462 +CB_PERF_SEL_RESERVED_463 = 463 +CB_PERF_SEL_RESERVED_464 = 464 +CB_PERF_SEL_RESERVED_465 = 465 +CBPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'CBRamList' +CBRamList__enumvalues = { + 0: 'CB_DCG_CCC_CAS_TAG_ARRAY', + 1: 'CB_DCG_CCC_CAS_FRAG_PTR', + 2: 'CB_DCG_CCC_CAS_COLOR_PTR', + 3: 'CB_DCG_CCC_CAS_SURF_PARAM', + 4: 'CB_DCG_CCC_CAS_KEYID', + 5: 'CB_DCG_BACKEND_RDLAT_FIFO', + 6: 'CB_DCG_FRONTEND_RDLAT_FIFO', + 7: 'CB_DCG_SRC_FIFO', + 8: 'CB_DCG_COLOR_STORE', + 9: 'CB_DCG_COLOR_STORE_DIRTY_BYTE', + 10: 'CB_DCG_FMASK_CACHE_STORE', + 11: 'CB_DCG_READ_SKID_FIFO', + 12: 'CB_DCG_QUAD_PTR_FIFO', + 13: 'CB_DCG_OUTPUT_FIFO', + 14: 'CB_DCG_DCC_CACHE', + 15: 'CB_DCG_DCC_DIRTY_BITS', + 16: 'CB_DCG_QBLOCK_ALLOC', +} +CB_DCG_CCC_CAS_TAG_ARRAY = 0 +CB_DCG_CCC_CAS_FRAG_PTR = 1 +CB_DCG_CCC_CAS_COLOR_PTR = 2 +CB_DCG_CCC_CAS_SURF_PARAM = 3 +CB_DCG_CCC_CAS_KEYID = 4 +CB_DCG_BACKEND_RDLAT_FIFO = 5 +CB_DCG_FRONTEND_RDLAT_FIFO = 6 +CB_DCG_SRC_FIFO = 7 +CB_DCG_COLOR_STORE = 8 +CB_DCG_COLOR_STORE_DIRTY_BYTE = 9 +CB_DCG_FMASK_CACHE_STORE = 10 +CB_DCG_READ_SKID_FIFO = 11 +CB_DCG_QUAD_PTR_FIFO = 12 +CB_DCG_OUTPUT_FIFO = 13 +CB_DCG_DCC_CACHE = 14 +CB_DCG_DCC_DIRTY_BITS = 15 +CB_DCG_QBLOCK_ALLOC = 16 +CBRamList = ctypes.c_uint32 # enum + +# values for enumeration 'CmaskCode' +CmaskCode__enumvalues = { + 0: 'CMASK_CLR00_F0', + 1: 'CMASK_CLR00_F1', + 2: 'CMASK_CLR00_F2', + 3: 'CMASK_CLR00_FX', + 4: 'CMASK_CLR01_F0', + 5: 'CMASK_CLR01_F1', + 6: 'CMASK_CLR01_F2', + 7: 'CMASK_CLR01_FX', + 8: 'CMASK_CLR10_F0', + 9: 'CMASK_CLR10_F1', + 10: 'CMASK_CLR10_F2', + 11: 'CMASK_CLR10_FX', + 12: 'CMASK_CLR11_F0', + 13: 'CMASK_CLR11_F1', + 14: 'CMASK_CLR11_F2', + 15: 'CMASK_CLR11_FX', +} +CMASK_CLR00_F0 = 0 +CMASK_CLR00_F1 = 1 +CMASK_CLR00_F2 = 2 +CMASK_CLR00_FX = 3 +CMASK_CLR01_F0 = 4 +CMASK_CLR01_F1 = 5 +CMASK_CLR01_F2 = 6 +CMASK_CLR01_FX = 7 +CMASK_CLR10_F0 = 8 +CMASK_CLR10_F1 = 9 +CMASK_CLR10_F2 = 10 +CMASK_CLR10_FX = 11 +CMASK_CLR11_F0 = 12 +CMASK_CLR11_F1 = 13 +CMASK_CLR11_F2 = 14 +CMASK_CLR11_FX = 15 +CmaskCode = ctypes.c_uint32 # enum + +# values for enumeration 'CombFunc' +CombFunc__enumvalues = { + 0: 'COMB_DST_PLUS_SRC', + 1: 'COMB_SRC_MINUS_DST', + 2: 'COMB_MIN_DST_SRC', + 3: 'COMB_MAX_DST_SRC', + 4: 'COMB_DST_MINUS_SRC', +} +COMB_DST_PLUS_SRC = 0 +COMB_SRC_MINUS_DST = 1 +COMB_MIN_DST_SRC = 2 +COMB_MAX_DST_SRC = 3 +COMB_DST_MINUS_SRC = 4 +CombFunc = ctypes.c_uint32 # enum + +# values for enumeration 'MemArbMode' +MemArbMode__enumvalues = { + 0: 'MEM_ARB_MODE_FIXED', + 1: 'MEM_ARB_MODE_AGE', + 2: 'MEM_ARB_MODE_WEIGHT', + 3: 'MEM_ARB_MODE_BOTH', +} +MEM_ARB_MODE_FIXED = 0 +MEM_ARB_MODE_AGE = 1 +MEM_ARB_MODE_WEIGHT = 2 +MEM_ARB_MODE_BOTH = 3 +MemArbMode = ctypes.c_uint32 # enum + +# values for enumeration 'SourceFormat' +SourceFormat__enumvalues = { + 0: 'EXPORT_4C_32BPC', + 1: 'EXPORT_4C_16BPC', + 2: 'EXPORT_2C_32BPC_GR', + 3: 'EXPORT_2C_32BPC_AR', +} +EXPORT_4C_32BPC = 0 +EXPORT_4C_16BPC = 1 +EXPORT_2C_32BPC_GR = 2 +EXPORT_2C_32BPC_AR = 3 +SourceFormat = ctypes.c_uint32 # enum + +# values for enumeration 'BinEventCntl' +BinEventCntl__enumvalues = { + 0: 'BINNER_BREAK_BATCH', + 1: 'BINNER_PIPELINE', + 2: 'BINNER_DROP', + 3: 'BINNER_PIPELINE_BREAK', +} +BINNER_BREAK_BATCH = 0 +BINNER_PIPELINE = 1 +BINNER_DROP = 2 +BINNER_PIPELINE_BREAK = 3 +BinEventCntl = ctypes.c_uint32 # enum + +# values for enumeration 'BinMapMode' +BinMapMode__enumvalues = { + 0: 'BIN_MAP_MODE_NONE', + 1: 'BIN_MAP_MODE_RTA_INDEX', + 2: 'BIN_MAP_MODE_POPS', +} +BIN_MAP_MODE_NONE = 0 +BIN_MAP_MODE_RTA_INDEX = 1 +BIN_MAP_MODE_POPS = 2 +BinMapMode = ctypes.c_uint32 # enum + +# values for enumeration 'BinSizeExtend' +BinSizeExtend__enumvalues = { + 0: 'BIN_SIZE_32_PIXELS', + 1: 'BIN_SIZE_64_PIXELS', + 2: 'BIN_SIZE_128_PIXELS', + 3: 'BIN_SIZE_256_PIXELS', + 4: 'BIN_SIZE_512_PIXELS', +} +BIN_SIZE_32_PIXELS = 0 +BIN_SIZE_64_PIXELS = 1 +BIN_SIZE_128_PIXELS = 2 +BIN_SIZE_256_PIXELS = 3 +BIN_SIZE_512_PIXELS = 4 +BinSizeExtend = ctypes.c_uint32 # enum + +# values for enumeration 'BinningMode' +BinningMode__enumvalues = { + 0: 'BINNING_ALLOWED', + 1: 'FORCE_BINNING_ON', + 2: 'DISABLE_BINNING_USE_NEW_SC', + 3: 'DISABLE_BINNING_USE_LEGACY_SC', +} +BINNING_ALLOWED = 0 +FORCE_BINNING_ON = 1 +DISABLE_BINNING_USE_NEW_SC = 2 +DISABLE_BINNING_USE_LEGACY_SC = 3 +BinningMode = ctypes.c_uint32 # enum + +# values for enumeration 'CovToShaderSel' +CovToShaderSel__enumvalues = { + 0: 'INPUT_COVERAGE', + 1: 'INPUT_INNER_COVERAGE', + 2: 'INPUT_DEPTH_COVERAGE', + 3: 'RAW', +} +INPUT_COVERAGE = 0 +INPUT_INNER_COVERAGE = 1 +INPUT_DEPTH_COVERAGE = 2 +RAW = 3 +CovToShaderSel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrMap' +PkrMap__enumvalues = { + 0: 'RASTER_CONFIG_PKR_MAP_0', + 1: 'RASTER_CONFIG_PKR_MAP_1', + 2: 'RASTER_CONFIG_PKR_MAP_2', + 3: 'RASTER_CONFIG_PKR_MAP_3', +} +RASTER_CONFIG_PKR_MAP_0 = 0 +RASTER_CONFIG_PKR_MAP_1 = 1 +RASTER_CONFIG_PKR_MAP_2 = 2 +RASTER_CONFIG_PKR_MAP_3 = 3 +PkrMap = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel' +PkrXsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL_0', + 1: 'RASTER_CONFIG_PKR_XSEL_1', + 2: 'RASTER_CONFIG_PKR_XSEL_2', + 3: 'RASTER_CONFIG_PKR_XSEL_3', +} +RASTER_CONFIG_PKR_XSEL_0 = 0 +RASTER_CONFIG_PKR_XSEL_1 = 1 +RASTER_CONFIG_PKR_XSEL_2 = 2 +RASTER_CONFIG_PKR_XSEL_3 = 3 +PkrXsel = ctypes.c_uint32 # enum + +# values for enumeration 'PkrXsel2' +PkrXsel2__enumvalues = { + 0: 'RASTER_CONFIG_PKR_XSEL2_0', + 1: 'RASTER_CONFIG_PKR_XSEL2_1', + 2: 'RASTER_CONFIG_PKR_XSEL2_2', + 3: 'RASTER_CONFIG_PKR_XSEL2_3', +} +RASTER_CONFIG_PKR_XSEL2_0 = 0 +RASTER_CONFIG_PKR_XSEL2_1 = 1 +RASTER_CONFIG_PKR_XSEL2_2 = 2 +RASTER_CONFIG_PKR_XSEL2_3 = 3 +PkrXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'PkrYsel' +PkrYsel__enumvalues = { + 0: 'RASTER_CONFIG_PKR_YSEL_0', + 1: 'RASTER_CONFIG_PKR_YSEL_1', + 2: 'RASTER_CONFIG_PKR_YSEL_2', + 3: 'RASTER_CONFIG_PKR_YSEL_3', +} +RASTER_CONFIG_PKR_YSEL_0 = 0 +RASTER_CONFIG_PKR_YSEL_1 = 1 +RASTER_CONFIG_PKR_YSEL_2 = 2 +RASTER_CONFIG_PKR_YSEL_3 = 3 +PkrYsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbMap' +RbMap__enumvalues = { + 0: 'RASTER_CONFIG_RB_MAP_0', + 1: 'RASTER_CONFIG_RB_MAP_1', + 2: 'RASTER_CONFIG_RB_MAP_2', + 3: 'RASTER_CONFIG_RB_MAP_3', +} +RASTER_CONFIG_RB_MAP_0 = 0 +RASTER_CONFIG_RB_MAP_1 = 1 +RASTER_CONFIG_RB_MAP_2 = 2 +RASTER_CONFIG_RB_MAP_3 = 3 +RbMap = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel' +RbXsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL_0', + 1: 'RASTER_CONFIG_RB_XSEL_1', +} +RASTER_CONFIG_RB_XSEL_0 = 0 +RASTER_CONFIG_RB_XSEL_1 = 1 +RbXsel = ctypes.c_uint32 # enum + +# values for enumeration 'RbXsel2' +RbXsel2__enumvalues = { + 0: 'RASTER_CONFIG_RB_XSEL2_0', + 1: 'RASTER_CONFIG_RB_XSEL2_1', + 2: 'RASTER_CONFIG_RB_XSEL2_2', + 3: 'RASTER_CONFIG_RB_XSEL2_3', +} +RASTER_CONFIG_RB_XSEL2_0 = 0 +RASTER_CONFIG_RB_XSEL2_1 = 1 +RASTER_CONFIG_RB_XSEL2_2 = 2 +RASTER_CONFIG_RB_XSEL2_3 = 3 +RbXsel2 = ctypes.c_uint32 # enum + +# values for enumeration 'RbYsel' +RbYsel__enumvalues = { + 0: 'RASTER_CONFIG_RB_YSEL_0', + 1: 'RASTER_CONFIG_RB_YSEL_1', +} +RASTER_CONFIG_RB_YSEL_0 = 0 +RASTER_CONFIG_RB_YSEL_1 = 1 +RbYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SC_PERFCNT_SEL' +SC_PERFCNT_SEL__enumvalues = { + 0: 'SC_SRPS_WINDOW_VALID', + 1: 'SC_PSSW_WINDOW_VALID', + 2: 'SC_TPQZ_WINDOW_VALID', + 3: 'SC_QZQP_WINDOW_VALID', + 4: 'SC_TRPK_WINDOW_VALID', + 5: 'SC_SRPS_WINDOW_VALID_BUSY', + 6: 'SC_PSSW_WINDOW_VALID_BUSY', + 7: 'SC_TPQZ_WINDOW_VALID_BUSY', + 8: 'SC_QZQP_WINDOW_VALID_BUSY', + 9: 'SC_TRPK_WINDOW_VALID_BUSY', + 10: 'SC_STARVED_BY_PA', + 11: 'SC_STALLED_BY_PRIMFIFO', + 12: 'SC_STALLED_BY_DB_TILE', + 13: 'SC_STARVED_BY_DB_TILE', + 14: 'SC_STALLED_BY_TILEORDERFIFO', + 15: 'SC_STALLED_BY_TILEFIFO', + 16: 'SC_STALLED_BY_DB_QUAD', + 17: 'SC_STARVED_BY_DB_QUAD', + 18: 'SC_STALLED_BY_QUADFIFO', + 19: 'SC_STALLED_BY_BCI', + 20: 'SC_STALLED_BY_SPI', + 21: 'SC_SCISSOR_DISCARD', + 22: 'SC_BB_DISCARD', + 23: 'SC_SUPERTILE_COUNT', + 24: 'SC_SUPERTILE_PER_PRIM_H0', + 25: 'SC_SUPERTILE_PER_PRIM_H1', + 26: 'SC_SUPERTILE_PER_PRIM_H2', + 27: 'SC_SUPERTILE_PER_PRIM_H3', + 28: 'SC_SUPERTILE_PER_PRIM_H4', + 29: 'SC_SUPERTILE_PER_PRIM_H5', + 30: 'SC_SUPERTILE_PER_PRIM_H6', + 31: 'SC_SUPERTILE_PER_PRIM_H7', + 32: 'SC_SUPERTILE_PER_PRIM_H8', + 33: 'SC_SUPERTILE_PER_PRIM_H9', + 34: 'SC_SUPERTILE_PER_PRIM_H10', + 35: 'SC_SUPERTILE_PER_PRIM_H11', + 36: 'SC_SUPERTILE_PER_PRIM_H12', + 37: 'SC_SUPERTILE_PER_PRIM_H13', + 38: 'SC_SUPERTILE_PER_PRIM_H14', + 39: 'SC_SUPERTILE_PER_PRIM_H15', + 40: 'SC_SUPERTILE_PER_PRIM_H16', + 41: 'SC_TILE_PER_PRIM_H0', + 42: 'SC_TILE_PER_PRIM_H1', + 43: 'SC_TILE_PER_PRIM_H2', + 44: 'SC_TILE_PER_PRIM_H3', + 45: 'SC_TILE_PER_PRIM_H4', + 46: 'SC_TILE_PER_PRIM_H5', + 47: 'SC_TILE_PER_PRIM_H6', + 48: 'SC_TILE_PER_PRIM_H7', + 49: 'SC_TILE_PER_PRIM_H8', + 50: 'SC_TILE_PER_PRIM_H9', + 51: 'SC_TILE_PER_PRIM_H10', + 52: 'SC_TILE_PER_PRIM_H11', + 53: 'SC_TILE_PER_PRIM_H12', + 54: 'SC_TILE_PER_PRIM_H13', + 55: 'SC_TILE_PER_PRIM_H14', + 56: 'SC_TILE_PER_PRIM_H15', + 57: 'SC_TILE_PER_PRIM_H16', + 58: 'SC_TILE_PER_SUPERTILE_H0', + 59: 'SC_TILE_PER_SUPERTILE_H1', + 60: 'SC_TILE_PER_SUPERTILE_H2', + 61: 'SC_TILE_PER_SUPERTILE_H3', + 62: 'SC_TILE_PER_SUPERTILE_H4', + 63: 'SC_TILE_PER_SUPERTILE_H5', + 64: 'SC_TILE_PER_SUPERTILE_H6', + 65: 'SC_TILE_PER_SUPERTILE_H7', + 66: 'SC_TILE_PER_SUPERTILE_H8', + 67: 'SC_TILE_PER_SUPERTILE_H9', + 68: 'SC_TILE_PER_SUPERTILE_H10', + 69: 'SC_TILE_PER_SUPERTILE_H11', + 70: 'SC_TILE_PER_SUPERTILE_H12', + 71: 'SC_TILE_PER_SUPERTILE_H13', + 72: 'SC_TILE_PER_SUPERTILE_H14', + 73: 'SC_TILE_PER_SUPERTILE_H15', + 74: 'SC_TILE_PER_SUPERTILE_H16', + 75: 'SC_TILE_PICKED_H1', + 76: 'SC_TILE_PICKED_H2', + 77: 'SC_TILE_PICKED_H3', + 78: 'SC_TILE_PICKED_H4', + 79: 'SC_QZ0_TILE_COUNT', + 80: 'SC_QZ1_TILE_COUNT', + 81: 'SC_QZ2_TILE_COUNT', + 82: 'SC_QZ3_TILE_COUNT', + 83: 'SC_QZ0_TILE_COVERED_COUNT', + 84: 'SC_QZ1_TILE_COVERED_COUNT', + 85: 'SC_QZ2_TILE_COVERED_COUNT', + 86: 'SC_QZ3_TILE_COVERED_COUNT', + 87: 'SC_QZ0_TILE_NOT_COVERED_COUNT', + 88: 'SC_QZ1_TILE_NOT_COVERED_COUNT', + 89: 'SC_QZ2_TILE_NOT_COVERED_COUNT', + 90: 'SC_QZ3_TILE_NOT_COVERED_COUNT', + 91: 'SC_QZ0_QUAD_PER_TILE_H0', + 92: 'SC_QZ0_QUAD_PER_TILE_H1', + 93: 'SC_QZ0_QUAD_PER_TILE_H2', + 94: 'SC_QZ0_QUAD_PER_TILE_H3', + 95: 'SC_QZ0_QUAD_PER_TILE_H4', + 96: 'SC_QZ0_QUAD_PER_TILE_H5', + 97: 'SC_QZ0_QUAD_PER_TILE_H6', + 98: 'SC_QZ0_QUAD_PER_TILE_H7', + 99: 'SC_QZ0_QUAD_PER_TILE_H8', + 100: 'SC_QZ0_QUAD_PER_TILE_H9', + 101: 'SC_QZ0_QUAD_PER_TILE_H10', + 102: 'SC_QZ0_QUAD_PER_TILE_H11', + 103: 'SC_QZ0_QUAD_PER_TILE_H12', + 104: 'SC_QZ0_QUAD_PER_TILE_H13', + 105: 'SC_QZ0_QUAD_PER_TILE_H14', + 106: 'SC_QZ0_QUAD_PER_TILE_H15', + 107: 'SC_QZ0_QUAD_PER_TILE_H16', + 108: 'SC_QZ1_QUAD_PER_TILE_H0', + 109: 'SC_QZ1_QUAD_PER_TILE_H1', + 110: 'SC_QZ1_QUAD_PER_TILE_H2', + 111: 'SC_QZ1_QUAD_PER_TILE_H3', + 112: 'SC_QZ1_QUAD_PER_TILE_H4', + 113: 'SC_QZ1_QUAD_PER_TILE_H5', + 114: 'SC_QZ1_QUAD_PER_TILE_H6', + 115: 'SC_QZ1_QUAD_PER_TILE_H7', + 116: 'SC_QZ1_QUAD_PER_TILE_H8', + 117: 'SC_QZ1_QUAD_PER_TILE_H9', + 118: 'SC_QZ1_QUAD_PER_TILE_H10', + 119: 'SC_QZ1_QUAD_PER_TILE_H11', + 120: 'SC_QZ1_QUAD_PER_TILE_H12', + 121: 'SC_QZ1_QUAD_PER_TILE_H13', + 122: 'SC_QZ1_QUAD_PER_TILE_H14', + 123: 'SC_QZ1_QUAD_PER_TILE_H15', + 124: 'SC_QZ1_QUAD_PER_TILE_H16', + 125: 'SC_QZ2_QUAD_PER_TILE_H0', + 126: 'SC_QZ2_QUAD_PER_TILE_H1', + 127: 'SC_QZ2_QUAD_PER_TILE_H2', + 128: 'SC_QZ2_QUAD_PER_TILE_H3', + 129: 'SC_QZ2_QUAD_PER_TILE_H4', + 130: 'SC_QZ2_QUAD_PER_TILE_H5', + 131: 'SC_QZ2_QUAD_PER_TILE_H6', + 132: 'SC_QZ2_QUAD_PER_TILE_H7', + 133: 'SC_QZ2_QUAD_PER_TILE_H8', + 134: 'SC_QZ2_QUAD_PER_TILE_H9', + 135: 'SC_QZ2_QUAD_PER_TILE_H10', + 136: 'SC_QZ2_QUAD_PER_TILE_H11', + 137: 'SC_QZ2_QUAD_PER_TILE_H12', + 138: 'SC_QZ2_QUAD_PER_TILE_H13', + 139: 'SC_QZ2_QUAD_PER_TILE_H14', + 140: 'SC_QZ2_QUAD_PER_TILE_H15', + 141: 'SC_QZ2_QUAD_PER_TILE_H16', + 142: 'SC_QZ3_QUAD_PER_TILE_H0', + 143: 'SC_QZ3_QUAD_PER_TILE_H1', + 144: 'SC_QZ3_QUAD_PER_TILE_H2', + 145: 'SC_QZ3_QUAD_PER_TILE_H3', + 146: 'SC_QZ3_QUAD_PER_TILE_H4', + 147: 'SC_QZ3_QUAD_PER_TILE_H5', + 148: 'SC_QZ3_QUAD_PER_TILE_H6', + 149: 'SC_QZ3_QUAD_PER_TILE_H7', + 150: 'SC_QZ3_QUAD_PER_TILE_H8', + 151: 'SC_QZ3_QUAD_PER_TILE_H9', + 152: 'SC_QZ3_QUAD_PER_TILE_H10', + 153: 'SC_QZ3_QUAD_PER_TILE_H11', + 154: 'SC_QZ3_QUAD_PER_TILE_H12', + 155: 'SC_QZ3_QUAD_PER_TILE_H13', + 156: 'SC_QZ3_QUAD_PER_TILE_H14', + 157: 'SC_QZ3_QUAD_PER_TILE_H15', + 158: 'SC_QZ3_QUAD_PER_TILE_H16', + 159: 'SC_QZ0_QUAD_COUNT', + 160: 'SC_QZ1_QUAD_COUNT', + 161: 'SC_QZ2_QUAD_COUNT', + 162: 'SC_QZ3_QUAD_COUNT', + 163: 'SC_P0_HIZ_TILE_COUNT', + 164: 'SC_P1_HIZ_TILE_COUNT', + 165: 'SC_P2_HIZ_TILE_COUNT', + 166: 'SC_P3_HIZ_TILE_COUNT', + 167: 'SC_P0_HIZ_QUAD_PER_TILE_H0', + 168: 'SC_P0_HIZ_QUAD_PER_TILE_H1', + 169: 'SC_P0_HIZ_QUAD_PER_TILE_H2', + 170: 'SC_P0_HIZ_QUAD_PER_TILE_H3', + 171: 'SC_P0_HIZ_QUAD_PER_TILE_H4', + 172: 'SC_P0_HIZ_QUAD_PER_TILE_H5', + 173: 'SC_P0_HIZ_QUAD_PER_TILE_H6', + 174: 'SC_P0_HIZ_QUAD_PER_TILE_H7', + 175: 'SC_P0_HIZ_QUAD_PER_TILE_H8', + 176: 'SC_P0_HIZ_QUAD_PER_TILE_H9', + 177: 'SC_P0_HIZ_QUAD_PER_TILE_H10', + 178: 'SC_P0_HIZ_QUAD_PER_TILE_H11', + 179: 'SC_P0_HIZ_QUAD_PER_TILE_H12', + 180: 'SC_P0_HIZ_QUAD_PER_TILE_H13', + 181: 'SC_P0_HIZ_QUAD_PER_TILE_H14', + 182: 'SC_P0_HIZ_QUAD_PER_TILE_H15', + 183: 'SC_P0_HIZ_QUAD_PER_TILE_H16', + 184: 'SC_P1_HIZ_QUAD_PER_TILE_H0', + 185: 'SC_P1_HIZ_QUAD_PER_TILE_H1', + 186: 'SC_P1_HIZ_QUAD_PER_TILE_H2', + 187: 'SC_P1_HIZ_QUAD_PER_TILE_H3', + 188: 'SC_P1_HIZ_QUAD_PER_TILE_H4', + 189: 'SC_P1_HIZ_QUAD_PER_TILE_H5', + 190: 'SC_P1_HIZ_QUAD_PER_TILE_H6', + 191: 'SC_P1_HIZ_QUAD_PER_TILE_H7', + 192: 'SC_P1_HIZ_QUAD_PER_TILE_H8', + 193: 'SC_P1_HIZ_QUAD_PER_TILE_H9', + 194: 'SC_P1_HIZ_QUAD_PER_TILE_H10', + 195: 'SC_P1_HIZ_QUAD_PER_TILE_H11', + 196: 'SC_P1_HIZ_QUAD_PER_TILE_H12', + 197: 'SC_P1_HIZ_QUAD_PER_TILE_H13', + 198: 'SC_P1_HIZ_QUAD_PER_TILE_H14', + 199: 'SC_P1_HIZ_QUAD_PER_TILE_H15', + 200: 'SC_P1_HIZ_QUAD_PER_TILE_H16', + 201: 'SC_P2_HIZ_QUAD_PER_TILE_H0', + 202: 'SC_P2_HIZ_QUAD_PER_TILE_H1', + 203: 'SC_P2_HIZ_QUAD_PER_TILE_H2', + 204: 'SC_P2_HIZ_QUAD_PER_TILE_H3', + 205: 'SC_P2_HIZ_QUAD_PER_TILE_H4', + 206: 'SC_P2_HIZ_QUAD_PER_TILE_H5', + 207: 'SC_P2_HIZ_QUAD_PER_TILE_H6', + 208: 'SC_P2_HIZ_QUAD_PER_TILE_H7', + 209: 'SC_P2_HIZ_QUAD_PER_TILE_H8', + 210: 'SC_P2_HIZ_QUAD_PER_TILE_H9', + 211: 'SC_P2_HIZ_QUAD_PER_TILE_H10', + 212: 'SC_P2_HIZ_QUAD_PER_TILE_H11', + 213: 'SC_P2_HIZ_QUAD_PER_TILE_H12', + 214: 'SC_P2_HIZ_QUAD_PER_TILE_H13', + 215: 'SC_P2_HIZ_QUAD_PER_TILE_H14', + 216: 'SC_P2_HIZ_QUAD_PER_TILE_H15', + 217: 'SC_P2_HIZ_QUAD_PER_TILE_H16', + 218: 'SC_P3_HIZ_QUAD_PER_TILE_H0', + 219: 'SC_P3_HIZ_QUAD_PER_TILE_H1', + 220: 'SC_P3_HIZ_QUAD_PER_TILE_H2', + 221: 'SC_P3_HIZ_QUAD_PER_TILE_H3', + 222: 'SC_P3_HIZ_QUAD_PER_TILE_H4', + 223: 'SC_P3_HIZ_QUAD_PER_TILE_H5', + 224: 'SC_P3_HIZ_QUAD_PER_TILE_H6', + 225: 'SC_P3_HIZ_QUAD_PER_TILE_H7', + 226: 'SC_P3_HIZ_QUAD_PER_TILE_H8', + 227: 'SC_P3_HIZ_QUAD_PER_TILE_H9', + 228: 'SC_P3_HIZ_QUAD_PER_TILE_H10', + 229: 'SC_P3_HIZ_QUAD_PER_TILE_H11', + 230: 'SC_P3_HIZ_QUAD_PER_TILE_H12', + 231: 'SC_P3_HIZ_QUAD_PER_TILE_H13', + 232: 'SC_P3_HIZ_QUAD_PER_TILE_H14', + 233: 'SC_P3_HIZ_QUAD_PER_TILE_H15', + 234: 'SC_P3_HIZ_QUAD_PER_TILE_H16', + 235: 'SC_P0_HIZ_QUAD_COUNT', + 236: 'SC_P1_HIZ_QUAD_COUNT', + 237: 'SC_P2_HIZ_QUAD_COUNT', + 238: 'SC_P3_HIZ_QUAD_COUNT', + 239: 'SC_P0_DETAIL_QUAD_COUNT', + 240: 'SC_P1_DETAIL_QUAD_COUNT', + 241: 'SC_P2_DETAIL_QUAD_COUNT', + 242: 'SC_P3_DETAIL_QUAD_COUNT', + 243: 'SC_P0_DETAIL_QUAD_WITH_1_PIX', + 244: 'SC_P0_DETAIL_QUAD_WITH_2_PIX', + 245: 'SC_P0_DETAIL_QUAD_WITH_3_PIX', + 246: 'SC_P0_DETAIL_QUAD_WITH_4_PIX', + 247: 'SC_P1_DETAIL_QUAD_WITH_1_PIX', + 248: 'SC_P1_DETAIL_QUAD_WITH_2_PIX', + 249: 'SC_P1_DETAIL_QUAD_WITH_3_PIX', + 250: 'SC_P1_DETAIL_QUAD_WITH_4_PIX', + 251: 'SC_P2_DETAIL_QUAD_WITH_1_PIX', + 252: 'SC_P2_DETAIL_QUAD_WITH_2_PIX', + 253: 'SC_P2_DETAIL_QUAD_WITH_3_PIX', + 254: 'SC_P2_DETAIL_QUAD_WITH_4_PIX', + 255: 'SC_P3_DETAIL_QUAD_WITH_1_PIX', + 256: 'SC_P3_DETAIL_QUAD_WITH_2_PIX', + 257: 'SC_P3_DETAIL_QUAD_WITH_3_PIX', + 258: 'SC_P3_DETAIL_QUAD_WITH_4_PIX', + 259: 'SC_EARLYZ_QUAD_COUNT', + 260: 'SC_EARLYZ_QUAD_WITH_1_PIX', + 261: 'SC_EARLYZ_QUAD_WITH_2_PIX', + 262: 'SC_EARLYZ_QUAD_WITH_3_PIX', + 263: 'SC_EARLYZ_QUAD_WITH_4_PIX', + 264: 'SC_PKR_QUAD_PER_ROW_H1', + 265: 'SC_PKR_QUAD_PER_ROW_H2', + 266: 'SC_PKR_4X2_QUAD_SPLIT', + 267: 'SC_PKR_4X2_FILL_QUAD', + 268: 'SC_PKR_END_OF_VECTOR', + 269: 'SC_PKR_CONTROL_XFER', + 270: 'SC_PKR_DBHANG_FORCE_EOV', + 271: 'SC_REG_SCLK_BUSY', + 272: 'SC_GRP0_DYN_SCLK_BUSY', + 273: 'SC_GRP1_DYN_SCLK_BUSY', + 274: 'SC_GRP2_DYN_SCLK_BUSY', + 275: 'SC_GRP3_DYN_SCLK_BUSY', + 276: 'SC_GRP4_DYN_SCLK_BUSY', + 277: 'SC_PA0_SC_DATA_FIFO_RD', + 278: 'SC_PA0_SC_DATA_FIFO_WE', + 279: 'SC_PA1_SC_DATA_FIFO_RD', + 280: 'SC_PA1_SC_DATA_FIFO_WE', + 281: 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 282: 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', + 283: 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 284: 'SC_PS_ARB_STALLED_FROM_BELOW', + 285: 'SC_PS_ARB_STARVED_FROM_ABOVE', + 286: 'SC_PS_ARB_SC_BUSY', + 287: 'SC_PS_ARB_PA_SC_BUSY', + 288: 'SC_PA2_SC_DATA_FIFO_RD', + 289: 'SC_PA2_SC_DATA_FIFO_WE', + 290: 'SC_PA3_SC_DATA_FIFO_RD', + 291: 'SC_PA3_SC_DATA_FIFO_WE', + 292: 'SC_PA_SC_DEALLOC_0_0_WE', + 293: 'SC_PA_SC_DEALLOC_0_1_WE', + 294: 'SC_PA_SC_DEALLOC_1_0_WE', + 295: 'SC_PA_SC_DEALLOC_1_1_WE', + 296: 'SC_PA_SC_DEALLOC_2_0_WE', + 297: 'SC_PA_SC_DEALLOC_2_1_WE', + 298: 'SC_PA_SC_DEALLOC_3_0_WE', + 299: 'SC_PA_SC_DEALLOC_3_1_WE', + 300: 'SC_PA0_SC_EOP_WE', + 301: 'SC_PA0_SC_EOPG_WE', + 302: 'SC_PA0_SC_EVENT_WE', + 303: 'SC_PA1_SC_EOP_WE', + 304: 'SC_PA1_SC_EOPG_WE', + 305: 'SC_PA1_SC_EVENT_WE', + 306: 'SC_PA2_SC_EOP_WE', + 307: 'SC_PA2_SC_EOPG_WE', + 308: 'SC_PA2_SC_EVENT_WE', + 309: 'SC_PA3_SC_EOP_WE', + 310: 'SC_PA3_SC_EOPG_WE', + 311: 'SC_PA3_SC_EVENT_WE', + 312: 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', + 313: 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', + 314: 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', + 315: 'SC_PS_ARB_EOP_POP_SYNC_POP', + 316: 'SC_PS_ARB_EVENT_SYNC_POP', + 317: 'SC_PS_ENG_MULTICYCLE_BUBBLE', + 318: 'SC_PA0_SC_FPOV_WE', + 319: 'SC_PA1_SC_FPOV_WE', + 320: 'SC_PA2_SC_FPOV_WE', + 321: 'SC_PA3_SC_FPOV_WE', + 322: 'SC_PA0_SC_LPOV_WE', + 323: 'SC_PA1_SC_LPOV_WE', + 324: 'SC_PA2_SC_LPOV_WE', + 325: 'SC_PA3_SC_LPOV_WE', + 326: 'SC_SPI_DEALLOC_0_0', + 327: 'SC_SPI_DEALLOC_0_1', + 328: 'SC_SPI_DEALLOC_0_2', + 329: 'SC_SPI_DEALLOC_1_0', + 330: 'SC_SPI_DEALLOC_1_1', + 331: 'SC_SPI_DEALLOC_1_2', + 332: 'SC_SPI_DEALLOC_2_0', + 333: 'SC_SPI_DEALLOC_2_1', + 334: 'SC_SPI_DEALLOC_2_2', + 335: 'SC_SPI_DEALLOC_3_0', + 336: 'SC_SPI_DEALLOC_3_1', + 337: 'SC_SPI_DEALLOC_3_2', + 338: 'SC_SPI_FPOV_0', + 339: 'SC_SPI_FPOV_1', + 340: 'SC_SPI_FPOV_2', + 341: 'SC_SPI_FPOV_3', + 342: 'SC_SPI_EVENT', + 343: 'SC_PS_TS_EVENT_FIFO_PUSH', + 344: 'SC_PS_TS_EVENT_FIFO_POP', + 345: 'SC_PS_CTX_DONE_FIFO_PUSH', + 346: 'SC_PS_CTX_DONE_FIFO_POP', + 347: 'SC_MULTICYCLE_BUBBLE_FREEZE', + 348: 'SC_EOP_SYNC_WINDOW', + 349: 'SC_PA0_SC_NULL_WE', + 350: 'SC_PA0_SC_NULL_DEALLOC_WE', + 351: 'SC_PA0_SC_DATA_FIFO_EOPG_RD', + 352: 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 353: 'SC_PA0_SC_DEALLOC_0_RD', + 354: 'SC_PA0_SC_DEALLOC_1_RD', + 355: 'SC_PA1_SC_DATA_FIFO_EOPG_RD', + 356: 'SC_PA1_SC_DATA_FIFO_EOP_RD', + 357: 'SC_PA1_SC_DEALLOC_0_RD', + 358: 'SC_PA1_SC_DEALLOC_1_RD', + 359: 'SC_PA1_SC_NULL_WE', + 360: 'SC_PA1_SC_NULL_DEALLOC_WE', + 361: 'SC_PA2_SC_DATA_FIFO_EOPG_RD', + 362: 'SC_PA2_SC_DATA_FIFO_EOP_RD', + 363: 'SC_PA2_SC_DEALLOC_0_RD', + 364: 'SC_PA2_SC_DEALLOC_1_RD', + 365: 'SC_PA2_SC_NULL_WE', + 366: 'SC_PA2_SC_NULL_DEALLOC_WE', + 367: 'SC_PA3_SC_DATA_FIFO_EOPG_RD', + 368: 'SC_PA3_SC_DATA_FIFO_EOP_RD', + 369: 'SC_PA3_SC_DEALLOC_0_RD', + 370: 'SC_PA3_SC_DEALLOC_1_RD', + 371: 'SC_PA3_SC_NULL_WE', + 372: 'SC_PA3_SC_NULL_DEALLOC_WE', + 373: 'SC_PS_PA0_SC_FIFO_EMPTY', + 374: 'SC_PS_PA0_SC_FIFO_FULL', + 375: 'SC_RESERVED_0', + 376: 'SC_PS_PA1_SC_FIFO_EMPTY', + 377: 'SC_PS_PA1_SC_FIFO_FULL', + 378: 'SC_RESERVED_1', + 379: 'SC_PS_PA2_SC_FIFO_EMPTY', + 380: 'SC_PS_PA2_SC_FIFO_FULL', + 381: 'SC_RESERVED_2', + 382: 'SC_PS_PA3_SC_FIFO_EMPTY', + 383: 'SC_PS_PA3_SC_FIFO_FULL', + 384: 'SC_RESERVED_3', + 385: 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', + 386: 'SC_BUSY_CNT_NOT_ZERO', + 387: 'SC_BM_BUSY', + 388: 'SC_BACKEND_BUSY', + 389: 'SC_SCF_SCB_INTERFACE_BUSY', + 390: 'SC_SCB_BUSY', + 391: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 392: 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 393: 'SC_PBB_BIN_HIST_NUM_PRIMS', + 394: 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 395: 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 396: 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 397: 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 398: 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 399: 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 400: 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 401: 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 402: 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 403: 'SC_PBB_BUSY', + 404: 'SC_PBB_BUSY_AND_NO_SENDS', + 405: 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 406: 'SC_PBB_NUM_BINS', + 407: 'SC_PBB_END_OF_BIN', + 408: 'SC_PBB_END_OF_BATCH', + 409: 'SC_PBB_PRIMBIN_PROCESSED', + 410: 'SC_PBB_PRIM_ADDED_TO_BATCH', + 411: 'SC_PBB_NONBINNED_PRIM', + 412: 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', + 413: 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 414: 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 415: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 416: 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 417: 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 418: 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 419: 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 420: 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 421: 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 422: 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 423: 'SC_POPS_INTRA_WAVE_OVERLAPS', + 424: 'SC_POPS_FORCE_EOV', + 425: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', + 426: 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', + 427: 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', + 428: 'SC_FULL_FULL_QUAD', + 429: 'SC_FULL_HALF_QUAD', + 430: 'SC_FULL_QTR_QUAD', + 431: 'SC_HALF_FULL_QUAD', + 432: 'SC_HALF_HALF_QUAD', + 433: 'SC_HALF_QTR_QUAD', + 434: 'SC_QTR_FULL_QUAD', + 435: 'SC_QTR_HALF_QUAD', + 436: 'SC_QTR_QTR_QUAD', + 437: 'SC_GRP5_DYN_SCLK_BUSY', + 438: 'SC_GRP6_DYN_SCLK_BUSY', + 439: 'SC_GRP7_DYN_SCLK_BUSY', + 440: 'SC_GRP8_DYN_SCLK_BUSY', + 441: 'SC_GRP9_DYN_SCLK_BUSY', + 442: 'SC_PS_TO_BE_SCLK_GATE_STALL', + 443: 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', + 444: 'SC_PK_BUSY', + 445: 'SC_PK_MAX_DEALLOC_FORCE_EOV', + 446: 'SC_PK_DEALLOC_WAVE_BREAK', + 447: 'SC_SPI_SEND', + 448: 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 449: 'SC_SPI_CREDIT_AT_MAX', + 450: 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', + 451: 'SC_BCI_SEND', + 452: 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 453: 'SC_BCI_CREDIT_AT_MAX', + 454: 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', + 455: 'SC_SPIBC_FULL_FREEZE', + 456: 'SC_PW_BM_PASS_EMPTY_PRIM', + 457: 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', + 458: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', + 459: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', + 460: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', + 461: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', + 462: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', + 463: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', + 464: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', + 465: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', + 466: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', + 467: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', + 468: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', + 469: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', + 470: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', + 471: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', + 472: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', + 473: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', + 474: 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', + 475: 'SC_DB0_TILE_INTERFACE_BUSY', + 476: 'SC_DB0_TILE_INTERFACE_SEND', + 477: 'SC_DB0_TILE_INTERFACE_SEND_EVENT', + 478: 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 479: 'SC_DB0_TILE_INTERFACE_SEND_SOP', + 480: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 481: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', + 482: 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 483: 'SC_DB1_TILE_INTERFACE_BUSY', + 484: 'SC_DB1_TILE_INTERFACE_SEND', + 485: 'SC_DB1_TILE_INTERFACE_SEND_EVENT', + 486: 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 487: 'SC_DB1_TILE_INTERFACE_SEND_SOP', + 488: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 489: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', + 490: 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 491: 'SC_BACKEND_PRIM_FIFO_FULL', + 492: 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', + 493: 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', + 494: 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', + 495: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', + 496: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', + 497: 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', + 498: 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', + 499: 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', + 500: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', + 501: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', + 502: 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', + 503: 'SC_STALLED_BY_DB0_TILEFIFO', + 504: 'SC_DB0_QUAD_INTF_SEND', + 505: 'SC_DB0_QUAD_INTF_BUSY', + 506: 'SC_DB0_QUAD_INTF_STALLED_BY_DB', + 507: 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', + 508: 'SC_DB0_QUAD_INTF_IDLE', + 509: 'SC_DB1_QUAD_INTF_SEND', + 510: 'SC_STALLED_BY_DB1_TILEFIFO', + 511: 'SC_DB1_QUAD_INTF_BUSY', + 512: 'SC_DB1_QUAD_INTF_STALLED_BY_DB', + 513: 'SC_DB1_QUAD_INTF_CREDIT_AT_MAX', + 514: 'SC_DB1_QUAD_INTF_IDLE', + 515: 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', + 516: 'SC_PKR_WAVE_BREAK_FULL_TILE', + 517: 'SC_FSR_WALKED', + 518: 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', + 519: 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', + 520: 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', + 521: 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 522: 'SC_DB0_TILE_MASK_FIFO_FULL', + 523: 'SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL', + 524: 'SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 525: 'SC_DB1_TILE_MASK_FIFO_FULL', + 526: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', + 527: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', + 528: 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', + 529: 'SC_PS_PM_PFF_PW_FULL', + 530: 'SC_PS_PM_ZFF_PW_FULL', + 531: 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', + 532: 'SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H', + 533: 'SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 534: 'SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 535: 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', + 536: 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', + 537: 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', + 538: 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', + 539: 'SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H', + 540: 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', + 541: 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 542: 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', + 543: 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 544: 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', + 545: 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', + 546: 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', + 547: 'SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H', + 548: 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', + 549: 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', + 550: 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', + 551: 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', + 552: 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', + 553: 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', + 554: 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', + 555: 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', + 556: 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', + 557: 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', + 558: 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', + 559: 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', + 560: 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', + 561: 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', + 562: 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', + 563: 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', + 564: 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', + 565: 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', + 566: 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', + 567: 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', + 568: 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE', + 569: 'SC_PBB_RESERVED', + 570: 'SC_BM_BE0_STALLED', + 571: 'SC_BM_BE1_STALLED', + 572: 'SC_BM_BE2_STALLED', + 573: 'SC_BM_BE3_STALLED', + 574: 'SC_BM_MULTI_ACCUM_1_BE_STALLED', + 575: 'SC_BM_MULTI_ACCUM_2_BE_STALLED', + 576: 'SC_BM_MULTI_ACCUM_3_BE_STALLED', + 577: 'SC_BM_MULTI_ACCUM_4_BE_STALLED', +} +SC_SRPS_WINDOW_VALID = 0 +SC_PSSW_WINDOW_VALID = 1 +SC_TPQZ_WINDOW_VALID = 2 +SC_QZQP_WINDOW_VALID = 3 +SC_TRPK_WINDOW_VALID = 4 +SC_SRPS_WINDOW_VALID_BUSY = 5 +SC_PSSW_WINDOW_VALID_BUSY = 6 +SC_TPQZ_WINDOW_VALID_BUSY = 7 +SC_QZQP_WINDOW_VALID_BUSY = 8 +SC_TRPK_WINDOW_VALID_BUSY = 9 +SC_STARVED_BY_PA = 10 +SC_STALLED_BY_PRIMFIFO = 11 +SC_STALLED_BY_DB_TILE = 12 +SC_STARVED_BY_DB_TILE = 13 +SC_STALLED_BY_TILEORDERFIFO = 14 +SC_STALLED_BY_TILEFIFO = 15 +SC_STALLED_BY_DB_QUAD = 16 +SC_STARVED_BY_DB_QUAD = 17 +SC_STALLED_BY_QUADFIFO = 18 +SC_STALLED_BY_BCI = 19 +SC_STALLED_BY_SPI = 20 +SC_SCISSOR_DISCARD = 21 +SC_BB_DISCARD = 22 +SC_SUPERTILE_COUNT = 23 +SC_SUPERTILE_PER_PRIM_H0 = 24 +SC_SUPERTILE_PER_PRIM_H1 = 25 +SC_SUPERTILE_PER_PRIM_H2 = 26 +SC_SUPERTILE_PER_PRIM_H3 = 27 +SC_SUPERTILE_PER_PRIM_H4 = 28 +SC_SUPERTILE_PER_PRIM_H5 = 29 +SC_SUPERTILE_PER_PRIM_H6 = 30 +SC_SUPERTILE_PER_PRIM_H7 = 31 +SC_SUPERTILE_PER_PRIM_H8 = 32 +SC_SUPERTILE_PER_PRIM_H9 = 33 +SC_SUPERTILE_PER_PRIM_H10 = 34 +SC_SUPERTILE_PER_PRIM_H11 = 35 +SC_SUPERTILE_PER_PRIM_H12 = 36 +SC_SUPERTILE_PER_PRIM_H13 = 37 +SC_SUPERTILE_PER_PRIM_H14 = 38 +SC_SUPERTILE_PER_PRIM_H15 = 39 +SC_SUPERTILE_PER_PRIM_H16 = 40 +SC_TILE_PER_PRIM_H0 = 41 +SC_TILE_PER_PRIM_H1 = 42 +SC_TILE_PER_PRIM_H2 = 43 +SC_TILE_PER_PRIM_H3 = 44 +SC_TILE_PER_PRIM_H4 = 45 +SC_TILE_PER_PRIM_H5 = 46 +SC_TILE_PER_PRIM_H6 = 47 +SC_TILE_PER_PRIM_H7 = 48 +SC_TILE_PER_PRIM_H8 = 49 +SC_TILE_PER_PRIM_H9 = 50 +SC_TILE_PER_PRIM_H10 = 51 +SC_TILE_PER_PRIM_H11 = 52 +SC_TILE_PER_PRIM_H12 = 53 +SC_TILE_PER_PRIM_H13 = 54 +SC_TILE_PER_PRIM_H14 = 55 +SC_TILE_PER_PRIM_H15 = 56 +SC_TILE_PER_PRIM_H16 = 57 +SC_TILE_PER_SUPERTILE_H0 = 58 +SC_TILE_PER_SUPERTILE_H1 = 59 +SC_TILE_PER_SUPERTILE_H2 = 60 +SC_TILE_PER_SUPERTILE_H3 = 61 +SC_TILE_PER_SUPERTILE_H4 = 62 +SC_TILE_PER_SUPERTILE_H5 = 63 +SC_TILE_PER_SUPERTILE_H6 = 64 +SC_TILE_PER_SUPERTILE_H7 = 65 +SC_TILE_PER_SUPERTILE_H8 = 66 +SC_TILE_PER_SUPERTILE_H9 = 67 +SC_TILE_PER_SUPERTILE_H10 = 68 +SC_TILE_PER_SUPERTILE_H11 = 69 +SC_TILE_PER_SUPERTILE_H12 = 70 +SC_TILE_PER_SUPERTILE_H13 = 71 +SC_TILE_PER_SUPERTILE_H14 = 72 +SC_TILE_PER_SUPERTILE_H15 = 73 +SC_TILE_PER_SUPERTILE_H16 = 74 +SC_TILE_PICKED_H1 = 75 +SC_TILE_PICKED_H2 = 76 +SC_TILE_PICKED_H3 = 77 +SC_TILE_PICKED_H4 = 78 +SC_QZ0_TILE_COUNT = 79 +SC_QZ1_TILE_COUNT = 80 +SC_QZ2_TILE_COUNT = 81 +SC_QZ3_TILE_COUNT = 82 +SC_QZ0_TILE_COVERED_COUNT = 83 +SC_QZ1_TILE_COVERED_COUNT = 84 +SC_QZ2_TILE_COVERED_COUNT = 85 +SC_QZ3_TILE_COVERED_COUNT = 86 +SC_QZ0_TILE_NOT_COVERED_COUNT = 87 +SC_QZ1_TILE_NOT_COVERED_COUNT = 88 +SC_QZ2_TILE_NOT_COVERED_COUNT = 89 +SC_QZ3_TILE_NOT_COVERED_COUNT = 90 +SC_QZ0_QUAD_PER_TILE_H0 = 91 +SC_QZ0_QUAD_PER_TILE_H1 = 92 +SC_QZ0_QUAD_PER_TILE_H2 = 93 +SC_QZ0_QUAD_PER_TILE_H3 = 94 +SC_QZ0_QUAD_PER_TILE_H4 = 95 +SC_QZ0_QUAD_PER_TILE_H5 = 96 +SC_QZ0_QUAD_PER_TILE_H6 = 97 +SC_QZ0_QUAD_PER_TILE_H7 = 98 +SC_QZ0_QUAD_PER_TILE_H8 = 99 +SC_QZ0_QUAD_PER_TILE_H9 = 100 +SC_QZ0_QUAD_PER_TILE_H10 = 101 +SC_QZ0_QUAD_PER_TILE_H11 = 102 +SC_QZ0_QUAD_PER_TILE_H12 = 103 +SC_QZ0_QUAD_PER_TILE_H13 = 104 +SC_QZ0_QUAD_PER_TILE_H14 = 105 +SC_QZ0_QUAD_PER_TILE_H15 = 106 +SC_QZ0_QUAD_PER_TILE_H16 = 107 +SC_QZ1_QUAD_PER_TILE_H0 = 108 +SC_QZ1_QUAD_PER_TILE_H1 = 109 +SC_QZ1_QUAD_PER_TILE_H2 = 110 +SC_QZ1_QUAD_PER_TILE_H3 = 111 +SC_QZ1_QUAD_PER_TILE_H4 = 112 +SC_QZ1_QUAD_PER_TILE_H5 = 113 +SC_QZ1_QUAD_PER_TILE_H6 = 114 +SC_QZ1_QUAD_PER_TILE_H7 = 115 +SC_QZ1_QUAD_PER_TILE_H8 = 116 +SC_QZ1_QUAD_PER_TILE_H9 = 117 +SC_QZ1_QUAD_PER_TILE_H10 = 118 +SC_QZ1_QUAD_PER_TILE_H11 = 119 +SC_QZ1_QUAD_PER_TILE_H12 = 120 +SC_QZ1_QUAD_PER_TILE_H13 = 121 +SC_QZ1_QUAD_PER_TILE_H14 = 122 +SC_QZ1_QUAD_PER_TILE_H15 = 123 +SC_QZ1_QUAD_PER_TILE_H16 = 124 +SC_QZ2_QUAD_PER_TILE_H0 = 125 +SC_QZ2_QUAD_PER_TILE_H1 = 126 +SC_QZ2_QUAD_PER_TILE_H2 = 127 +SC_QZ2_QUAD_PER_TILE_H3 = 128 +SC_QZ2_QUAD_PER_TILE_H4 = 129 +SC_QZ2_QUAD_PER_TILE_H5 = 130 +SC_QZ2_QUAD_PER_TILE_H6 = 131 +SC_QZ2_QUAD_PER_TILE_H7 = 132 +SC_QZ2_QUAD_PER_TILE_H8 = 133 +SC_QZ2_QUAD_PER_TILE_H9 = 134 +SC_QZ2_QUAD_PER_TILE_H10 = 135 +SC_QZ2_QUAD_PER_TILE_H11 = 136 +SC_QZ2_QUAD_PER_TILE_H12 = 137 +SC_QZ2_QUAD_PER_TILE_H13 = 138 +SC_QZ2_QUAD_PER_TILE_H14 = 139 +SC_QZ2_QUAD_PER_TILE_H15 = 140 +SC_QZ2_QUAD_PER_TILE_H16 = 141 +SC_QZ3_QUAD_PER_TILE_H0 = 142 +SC_QZ3_QUAD_PER_TILE_H1 = 143 +SC_QZ3_QUAD_PER_TILE_H2 = 144 +SC_QZ3_QUAD_PER_TILE_H3 = 145 +SC_QZ3_QUAD_PER_TILE_H4 = 146 +SC_QZ3_QUAD_PER_TILE_H5 = 147 +SC_QZ3_QUAD_PER_TILE_H6 = 148 +SC_QZ3_QUAD_PER_TILE_H7 = 149 +SC_QZ3_QUAD_PER_TILE_H8 = 150 +SC_QZ3_QUAD_PER_TILE_H9 = 151 +SC_QZ3_QUAD_PER_TILE_H10 = 152 +SC_QZ3_QUAD_PER_TILE_H11 = 153 +SC_QZ3_QUAD_PER_TILE_H12 = 154 +SC_QZ3_QUAD_PER_TILE_H13 = 155 +SC_QZ3_QUAD_PER_TILE_H14 = 156 +SC_QZ3_QUAD_PER_TILE_H15 = 157 +SC_QZ3_QUAD_PER_TILE_H16 = 158 +SC_QZ0_QUAD_COUNT = 159 +SC_QZ1_QUAD_COUNT = 160 +SC_QZ2_QUAD_COUNT = 161 +SC_QZ3_QUAD_COUNT = 162 +SC_P0_HIZ_TILE_COUNT = 163 +SC_P1_HIZ_TILE_COUNT = 164 +SC_P2_HIZ_TILE_COUNT = 165 +SC_P3_HIZ_TILE_COUNT = 166 +SC_P0_HIZ_QUAD_PER_TILE_H0 = 167 +SC_P0_HIZ_QUAD_PER_TILE_H1 = 168 +SC_P0_HIZ_QUAD_PER_TILE_H2 = 169 +SC_P0_HIZ_QUAD_PER_TILE_H3 = 170 +SC_P0_HIZ_QUAD_PER_TILE_H4 = 171 +SC_P0_HIZ_QUAD_PER_TILE_H5 = 172 +SC_P0_HIZ_QUAD_PER_TILE_H6 = 173 +SC_P0_HIZ_QUAD_PER_TILE_H7 = 174 +SC_P0_HIZ_QUAD_PER_TILE_H8 = 175 +SC_P0_HIZ_QUAD_PER_TILE_H9 = 176 +SC_P0_HIZ_QUAD_PER_TILE_H10 = 177 +SC_P0_HIZ_QUAD_PER_TILE_H11 = 178 +SC_P0_HIZ_QUAD_PER_TILE_H12 = 179 +SC_P0_HIZ_QUAD_PER_TILE_H13 = 180 +SC_P0_HIZ_QUAD_PER_TILE_H14 = 181 +SC_P0_HIZ_QUAD_PER_TILE_H15 = 182 +SC_P0_HIZ_QUAD_PER_TILE_H16 = 183 +SC_P1_HIZ_QUAD_PER_TILE_H0 = 184 +SC_P1_HIZ_QUAD_PER_TILE_H1 = 185 +SC_P1_HIZ_QUAD_PER_TILE_H2 = 186 +SC_P1_HIZ_QUAD_PER_TILE_H3 = 187 +SC_P1_HIZ_QUAD_PER_TILE_H4 = 188 +SC_P1_HIZ_QUAD_PER_TILE_H5 = 189 +SC_P1_HIZ_QUAD_PER_TILE_H6 = 190 +SC_P1_HIZ_QUAD_PER_TILE_H7 = 191 +SC_P1_HIZ_QUAD_PER_TILE_H8 = 192 +SC_P1_HIZ_QUAD_PER_TILE_H9 = 193 +SC_P1_HIZ_QUAD_PER_TILE_H10 = 194 +SC_P1_HIZ_QUAD_PER_TILE_H11 = 195 +SC_P1_HIZ_QUAD_PER_TILE_H12 = 196 +SC_P1_HIZ_QUAD_PER_TILE_H13 = 197 +SC_P1_HIZ_QUAD_PER_TILE_H14 = 198 +SC_P1_HIZ_QUAD_PER_TILE_H15 = 199 +SC_P1_HIZ_QUAD_PER_TILE_H16 = 200 +SC_P2_HIZ_QUAD_PER_TILE_H0 = 201 +SC_P2_HIZ_QUAD_PER_TILE_H1 = 202 +SC_P2_HIZ_QUAD_PER_TILE_H2 = 203 +SC_P2_HIZ_QUAD_PER_TILE_H3 = 204 +SC_P2_HIZ_QUAD_PER_TILE_H4 = 205 +SC_P2_HIZ_QUAD_PER_TILE_H5 = 206 +SC_P2_HIZ_QUAD_PER_TILE_H6 = 207 +SC_P2_HIZ_QUAD_PER_TILE_H7 = 208 +SC_P2_HIZ_QUAD_PER_TILE_H8 = 209 +SC_P2_HIZ_QUAD_PER_TILE_H9 = 210 +SC_P2_HIZ_QUAD_PER_TILE_H10 = 211 +SC_P2_HIZ_QUAD_PER_TILE_H11 = 212 +SC_P2_HIZ_QUAD_PER_TILE_H12 = 213 +SC_P2_HIZ_QUAD_PER_TILE_H13 = 214 +SC_P2_HIZ_QUAD_PER_TILE_H14 = 215 +SC_P2_HIZ_QUAD_PER_TILE_H15 = 216 +SC_P2_HIZ_QUAD_PER_TILE_H16 = 217 +SC_P3_HIZ_QUAD_PER_TILE_H0 = 218 +SC_P3_HIZ_QUAD_PER_TILE_H1 = 219 +SC_P3_HIZ_QUAD_PER_TILE_H2 = 220 +SC_P3_HIZ_QUAD_PER_TILE_H3 = 221 +SC_P3_HIZ_QUAD_PER_TILE_H4 = 222 +SC_P3_HIZ_QUAD_PER_TILE_H5 = 223 +SC_P3_HIZ_QUAD_PER_TILE_H6 = 224 +SC_P3_HIZ_QUAD_PER_TILE_H7 = 225 +SC_P3_HIZ_QUAD_PER_TILE_H8 = 226 +SC_P3_HIZ_QUAD_PER_TILE_H9 = 227 +SC_P3_HIZ_QUAD_PER_TILE_H10 = 228 +SC_P3_HIZ_QUAD_PER_TILE_H11 = 229 +SC_P3_HIZ_QUAD_PER_TILE_H12 = 230 +SC_P3_HIZ_QUAD_PER_TILE_H13 = 231 +SC_P3_HIZ_QUAD_PER_TILE_H14 = 232 +SC_P3_HIZ_QUAD_PER_TILE_H15 = 233 +SC_P3_HIZ_QUAD_PER_TILE_H16 = 234 +SC_P0_HIZ_QUAD_COUNT = 235 +SC_P1_HIZ_QUAD_COUNT = 236 +SC_P2_HIZ_QUAD_COUNT = 237 +SC_P3_HIZ_QUAD_COUNT = 238 +SC_P0_DETAIL_QUAD_COUNT = 239 +SC_P1_DETAIL_QUAD_COUNT = 240 +SC_P2_DETAIL_QUAD_COUNT = 241 +SC_P3_DETAIL_QUAD_COUNT = 242 +SC_P0_DETAIL_QUAD_WITH_1_PIX = 243 +SC_P0_DETAIL_QUAD_WITH_2_PIX = 244 +SC_P0_DETAIL_QUAD_WITH_3_PIX = 245 +SC_P0_DETAIL_QUAD_WITH_4_PIX = 246 +SC_P1_DETAIL_QUAD_WITH_1_PIX = 247 +SC_P1_DETAIL_QUAD_WITH_2_PIX = 248 +SC_P1_DETAIL_QUAD_WITH_3_PIX = 249 +SC_P1_DETAIL_QUAD_WITH_4_PIX = 250 +SC_P2_DETAIL_QUAD_WITH_1_PIX = 251 +SC_P2_DETAIL_QUAD_WITH_2_PIX = 252 +SC_P2_DETAIL_QUAD_WITH_3_PIX = 253 +SC_P2_DETAIL_QUAD_WITH_4_PIX = 254 +SC_P3_DETAIL_QUAD_WITH_1_PIX = 255 +SC_P3_DETAIL_QUAD_WITH_2_PIX = 256 +SC_P3_DETAIL_QUAD_WITH_3_PIX = 257 +SC_P3_DETAIL_QUAD_WITH_4_PIX = 258 +SC_EARLYZ_QUAD_COUNT = 259 +SC_EARLYZ_QUAD_WITH_1_PIX = 260 +SC_EARLYZ_QUAD_WITH_2_PIX = 261 +SC_EARLYZ_QUAD_WITH_3_PIX = 262 +SC_EARLYZ_QUAD_WITH_4_PIX = 263 +SC_PKR_QUAD_PER_ROW_H1 = 264 +SC_PKR_QUAD_PER_ROW_H2 = 265 +SC_PKR_4X2_QUAD_SPLIT = 266 +SC_PKR_4X2_FILL_QUAD = 267 +SC_PKR_END_OF_VECTOR = 268 +SC_PKR_CONTROL_XFER = 269 +SC_PKR_DBHANG_FORCE_EOV = 270 +SC_REG_SCLK_BUSY = 271 +SC_GRP0_DYN_SCLK_BUSY = 272 +SC_GRP1_DYN_SCLK_BUSY = 273 +SC_GRP2_DYN_SCLK_BUSY = 274 +SC_GRP3_DYN_SCLK_BUSY = 275 +SC_GRP4_DYN_SCLK_BUSY = 276 +SC_PA0_SC_DATA_FIFO_RD = 277 +SC_PA0_SC_DATA_FIFO_WE = 278 +SC_PA1_SC_DATA_FIFO_RD = 279 +SC_PA1_SC_DATA_FIFO_WE = 280 +SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 281 +SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 282 +SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 283 +SC_PS_ARB_STALLED_FROM_BELOW = 284 +SC_PS_ARB_STARVED_FROM_ABOVE = 285 +SC_PS_ARB_SC_BUSY = 286 +SC_PS_ARB_PA_SC_BUSY = 287 +SC_PA2_SC_DATA_FIFO_RD = 288 +SC_PA2_SC_DATA_FIFO_WE = 289 +SC_PA3_SC_DATA_FIFO_RD = 290 +SC_PA3_SC_DATA_FIFO_WE = 291 +SC_PA_SC_DEALLOC_0_0_WE = 292 +SC_PA_SC_DEALLOC_0_1_WE = 293 +SC_PA_SC_DEALLOC_1_0_WE = 294 +SC_PA_SC_DEALLOC_1_1_WE = 295 +SC_PA_SC_DEALLOC_2_0_WE = 296 +SC_PA_SC_DEALLOC_2_1_WE = 297 +SC_PA_SC_DEALLOC_3_0_WE = 298 +SC_PA_SC_DEALLOC_3_1_WE = 299 +SC_PA0_SC_EOP_WE = 300 +SC_PA0_SC_EOPG_WE = 301 +SC_PA0_SC_EVENT_WE = 302 +SC_PA1_SC_EOP_WE = 303 +SC_PA1_SC_EOPG_WE = 304 +SC_PA1_SC_EVENT_WE = 305 +SC_PA2_SC_EOP_WE = 306 +SC_PA2_SC_EOPG_WE = 307 +SC_PA2_SC_EVENT_WE = 308 +SC_PA3_SC_EOP_WE = 309 +SC_PA3_SC_EOPG_WE = 310 +SC_PA3_SC_EVENT_WE = 311 +SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 312 +SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 313 +SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 314 +SC_PS_ARB_EOP_POP_SYNC_POP = 315 +SC_PS_ARB_EVENT_SYNC_POP = 316 +SC_PS_ENG_MULTICYCLE_BUBBLE = 317 +SC_PA0_SC_FPOV_WE = 318 +SC_PA1_SC_FPOV_WE = 319 +SC_PA2_SC_FPOV_WE = 320 +SC_PA3_SC_FPOV_WE = 321 +SC_PA0_SC_LPOV_WE = 322 +SC_PA1_SC_LPOV_WE = 323 +SC_PA2_SC_LPOV_WE = 324 +SC_PA3_SC_LPOV_WE = 325 +SC_SPI_DEALLOC_0_0 = 326 +SC_SPI_DEALLOC_0_1 = 327 +SC_SPI_DEALLOC_0_2 = 328 +SC_SPI_DEALLOC_1_0 = 329 +SC_SPI_DEALLOC_1_1 = 330 +SC_SPI_DEALLOC_1_2 = 331 +SC_SPI_DEALLOC_2_0 = 332 +SC_SPI_DEALLOC_2_1 = 333 +SC_SPI_DEALLOC_2_2 = 334 +SC_SPI_DEALLOC_3_0 = 335 +SC_SPI_DEALLOC_3_1 = 336 +SC_SPI_DEALLOC_3_2 = 337 +SC_SPI_FPOV_0 = 338 +SC_SPI_FPOV_1 = 339 +SC_SPI_FPOV_2 = 340 +SC_SPI_FPOV_3 = 341 +SC_SPI_EVENT = 342 +SC_PS_TS_EVENT_FIFO_PUSH = 343 +SC_PS_TS_EVENT_FIFO_POP = 344 +SC_PS_CTX_DONE_FIFO_PUSH = 345 +SC_PS_CTX_DONE_FIFO_POP = 346 +SC_MULTICYCLE_BUBBLE_FREEZE = 347 +SC_EOP_SYNC_WINDOW = 348 +SC_PA0_SC_NULL_WE = 349 +SC_PA0_SC_NULL_DEALLOC_WE = 350 +SC_PA0_SC_DATA_FIFO_EOPG_RD = 351 +SC_PA0_SC_DATA_FIFO_EOP_RD = 352 +SC_PA0_SC_DEALLOC_0_RD = 353 +SC_PA0_SC_DEALLOC_1_RD = 354 +SC_PA1_SC_DATA_FIFO_EOPG_RD = 355 +SC_PA1_SC_DATA_FIFO_EOP_RD = 356 +SC_PA1_SC_DEALLOC_0_RD = 357 +SC_PA1_SC_DEALLOC_1_RD = 358 +SC_PA1_SC_NULL_WE = 359 +SC_PA1_SC_NULL_DEALLOC_WE = 360 +SC_PA2_SC_DATA_FIFO_EOPG_RD = 361 +SC_PA2_SC_DATA_FIFO_EOP_RD = 362 +SC_PA2_SC_DEALLOC_0_RD = 363 +SC_PA2_SC_DEALLOC_1_RD = 364 +SC_PA2_SC_NULL_WE = 365 +SC_PA2_SC_NULL_DEALLOC_WE = 366 +SC_PA3_SC_DATA_FIFO_EOPG_RD = 367 +SC_PA3_SC_DATA_FIFO_EOP_RD = 368 +SC_PA3_SC_DEALLOC_0_RD = 369 +SC_PA3_SC_DEALLOC_1_RD = 370 +SC_PA3_SC_NULL_WE = 371 +SC_PA3_SC_NULL_DEALLOC_WE = 372 +SC_PS_PA0_SC_FIFO_EMPTY = 373 +SC_PS_PA0_SC_FIFO_FULL = 374 +SC_RESERVED_0 = 375 +SC_PS_PA1_SC_FIFO_EMPTY = 376 +SC_PS_PA1_SC_FIFO_FULL = 377 +SC_RESERVED_1 = 378 +SC_PS_PA2_SC_FIFO_EMPTY = 379 +SC_PS_PA2_SC_FIFO_FULL = 380 +SC_RESERVED_2 = 381 +SC_PS_PA3_SC_FIFO_EMPTY = 382 +SC_PS_PA3_SC_FIFO_FULL = 383 +SC_RESERVED_3 = 384 +SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 385 +SC_BUSY_CNT_NOT_ZERO = 386 +SC_BM_BUSY = 387 +SC_BACKEND_BUSY = 388 +SC_SCF_SCB_INTERFACE_BUSY = 389 +SC_SCB_BUSY = 390 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 391 +SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 392 +SC_PBB_BIN_HIST_NUM_PRIMS = 393 +SC_PBB_BATCH_HIST_NUM_PRIMS = 394 +SC_PBB_BIN_HIST_NUM_CONTEXTS = 395 +SC_PBB_BATCH_HIST_NUM_CONTEXTS = 396 +SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 397 +SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 398 +SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 399 +SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 400 +SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 401 +SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 402 +SC_PBB_BUSY = 403 +SC_PBB_BUSY_AND_NO_SENDS = 404 +SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 405 +SC_PBB_NUM_BINS = 406 +SC_PBB_END_OF_BIN = 407 +SC_PBB_END_OF_BATCH = 408 +SC_PBB_PRIMBIN_PROCESSED = 409 +SC_PBB_PRIM_ADDED_TO_BATCH = 410 +SC_PBB_NONBINNED_PRIM = 411 +SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 412 +SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 413 +SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 414 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 415 +SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 416 +SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 417 +SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 418 +SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 419 +SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 420 +SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 421 +SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 422 +SC_POPS_INTRA_WAVE_OVERLAPS = 423 +SC_POPS_FORCE_EOV = 424 +SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 425 +SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 426 +SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 427 +SC_FULL_FULL_QUAD = 428 +SC_FULL_HALF_QUAD = 429 +SC_FULL_QTR_QUAD = 430 +SC_HALF_FULL_QUAD = 431 +SC_HALF_HALF_QUAD = 432 +SC_HALF_QTR_QUAD = 433 +SC_QTR_FULL_QUAD = 434 +SC_QTR_HALF_QUAD = 435 +SC_QTR_QTR_QUAD = 436 +SC_GRP5_DYN_SCLK_BUSY = 437 +SC_GRP6_DYN_SCLK_BUSY = 438 +SC_GRP7_DYN_SCLK_BUSY = 439 +SC_GRP8_DYN_SCLK_BUSY = 440 +SC_GRP9_DYN_SCLK_BUSY = 441 +SC_PS_TO_BE_SCLK_GATE_STALL = 442 +SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 443 +SC_PK_BUSY = 444 +SC_PK_MAX_DEALLOC_FORCE_EOV = 445 +SC_PK_DEALLOC_WAVE_BREAK = 446 +SC_SPI_SEND = 447 +SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 448 +SC_SPI_CREDIT_AT_MAX = 449 +SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 450 +SC_BCI_SEND = 451 +SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 452 +SC_BCI_CREDIT_AT_MAX = 453 +SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 454 +SC_SPIBC_FULL_FREEZE = 455 +SC_PW_BM_PASS_EMPTY_PRIM = 456 +SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 457 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 458 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 459 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 460 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 461 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 462 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 463 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 464 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 465 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 466 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 467 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 468 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 469 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 470 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 471 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 472 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 473 +SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 474 +SC_DB0_TILE_INTERFACE_BUSY = 475 +SC_DB0_TILE_INTERFACE_SEND = 476 +SC_DB0_TILE_INTERFACE_SEND_EVENT = 477 +SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 478 +SC_DB0_TILE_INTERFACE_SEND_SOP = 479 +SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 480 +SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 481 +SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 482 +SC_DB1_TILE_INTERFACE_BUSY = 483 +SC_DB1_TILE_INTERFACE_SEND = 484 +SC_DB1_TILE_INTERFACE_SEND_EVENT = 485 +SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 486 +SC_DB1_TILE_INTERFACE_SEND_SOP = 487 +SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 488 +SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 489 +SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 490 +SC_BACKEND_PRIM_FIFO_FULL = 491 +SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 492 +SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 493 +SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 494 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 495 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 496 +SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 497 +SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 498 +SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 499 +SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 500 +SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 501 +SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 502 +SC_STALLED_BY_DB0_TILEFIFO = 503 +SC_DB0_QUAD_INTF_SEND = 504 +SC_DB0_QUAD_INTF_BUSY = 505 +SC_DB0_QUAD_INTF_STALLED_BY_DB = 506 +SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 507 +SC_DB0_QUAD_INTF_IDLE = 508 +SC_DB1_QUAD_INTF_SEND = 509 +SC_STALLED_BY_DB1_TILEFIFO = 510 +SC_DB1_QUAD_INTF_BUSY = 511 +SC_DB1_QUAD_INTF_STALLED_BY_DB = 512 +SC_DB1_QUAD_INTF_CREDIT_AT_MAX = 513 +SC_DB1_QUAD_INTF_IDLE = 514 +SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 515 +SC_PKR_WAVE_BREAK_FULL_TILE = 516 +SC_FSR_WALKED = 517 +SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 518 +SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 519 +SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 520 +SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 521 +SC_DB0_TILE_MASK_FIFO_FULL = 522 +SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL = 523 +SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 524 +SC_DB1_TILE_MASK_FIFO_FULL = 525 +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 526 +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 527 +SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 528 +SC_PS_PM_PFF_PW_FULL = 529 +SC_PS_PM_ZFF_PW_FULL = 530 +SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 531 +SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H = 532 +SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 533 +SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 534 +SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 535 +SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 536 +SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 537 +SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 538 +SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H = 539 +SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 540 +SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 541 +SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 542 +SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 543 +SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 544 +SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 545 +SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 546 +SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H = 547 +SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 548 +SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 549 +SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 550 +SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 551 +SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 552 +SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 553 +SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 554 +SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 555 +SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 556 +SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 557 +SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 558 +SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 559 +SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 560 +SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 561 +SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 562 +SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 563 +SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 564 +SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 565 +SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 566 +SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 567 +SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE = 568 +SC_PBB_RESERVED = 569 +SC_BM_BE0_STALLED = 570 +SC_BM_BE1_STALLED = 571 +SC_BM_BE2_STALLED = 572 +SC_BM_BE3_STALLED = 573 +SC_BM_MULTI_ACCUM_1_BE_STALLED = 574 +SC_BM_MULTI_ACCUM_2_BE_STALLED = 575 +SC_BM_MULTI_ACCUM_3_BE_STALLED = 576 +SC_BM_MULTI_ACCUM_4_BE_STALLED = 577 +SC_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'ScMap' +ScMap__enumvalues = { + 0: 'RASTER_CONFIG_SC_MAP_0', + 1: 'RASTER_CONFIG_SC_MAP_1', + 2: 'RASTER_CONFIG_SC_MAP_2', + 3: 'RASTER_CONFIG_SC_MAP_3', +} +RASTER_CONFIG_SC_MAP_0 = 0 +RASTER_CONFIG_SC_MAP_1 = 1 +RASTER_CONFIG_SC_MAP_2 = 2 +RASTER_CONFIG_SC_MAP_3 = 3 +ScMap = ctypes.c_uint32 # enum + +# values for enumeration 'ScUncertaintyRegionMode' +ScUncertaintyRegionMode__enumvalues = { + 0: 'SC_HALF_LSB', + 1: 'SC_LSB_ONE_SIDED', + 2: 'SC_LSB_TWO_SIDED', +} +SC_HALF_LSB = 0 +SC_LSB_ONE_SIDED = 1 +SC_LSB_TWO_SIDED = 2 +ScUncertaintyRegionMode = ctypes.c_uint32 # enum + +# values for enumeration 'ScUncertaintyRegionMult' +ScUncertaintyRegionMult__enumvalues = { + 0: 'SC_UR_1X', + 1: 'SC_UR_2X', + 2: 'SC_UR_4X', + 3: 'SC_UR_8X', +} +SC_UR_1X = 0 +SC_UR_2X = 1 +SC_UR_4X = 2 +SC_UR_8X = 3 +ScUncertaintyRegionMult = ctypes.c_uint32 # enum + +# values for enumeration 'ScXsel' +ScXsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 3 +ScXsel = ctypes.c_uint32 # enum + +# values for enumeration 'ScYsel' +ScYsel__enumvalues = { + 0: 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 3 +ScYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeMap' +SeMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_MAP_0', + 1: 'RASTER_CONFIG_SE_MAP_1', + 2: 'RASTER_CONFIG_SE_MAP_2', + 3: 'RASTER_CONFIG_SE_MAP_3', +} +RASTER_CONFIG_SE_MAP_0 = 0 +RASTER_CONFIG_SE_MAP_1 = 1 +RASTER_CONFIG_SE_MAP_2 = 2 +RASTER_CONFIG_SE_MAP_3 = 3 +SeMap = ctypes.c_uint32 # enum + +# values for enumeration 'SePairMap' +SePairMap__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_MAP_0', + 1: 'RASTER_CONFIG_SE_PAIR_MAP_1', + 2: 'RASTER_CONFIG_SE_PAIR_MAP_2', + 3: 'RASTER_CONFIG_SE_PAIR_MAP_3', +} +RASTER_CONFIG_SE_PAIR_MAP_0 = 0 +RASTER_CONFIG_SE_PAIR_MAP_1 = 1 +RASTER_CONFIG_SE_PAIR_MAP_2 = 2 +RASTER_CONFIG_SE_PAIR_MAP_3 = 3 +SePairMap = ctypes.c_uint32 # enum + +# values for enumeration 'SePairXsel' +SePairXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 3 +SePairXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SePairYsel' +SePairYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 3 +SePairYsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeXsel' +SeXsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 3 +SeXsel = ctypes.c_uint32 # enum + +# values for enumeration 'SeYsel' +SeYsel__enumvalues = { + 0: 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', + 1: 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 2: 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 3: 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', +} +RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0 +RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 1 +RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 2 +RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 3 +SeYsel = ctypes.c_uint32 # enum + +# values for enumeration 'VRSCombinerModeSC' +VRSCombinerModeSC__enumvalues = { + 0: 'SC_VRS_COMB_MODE_PASSTHRU', + 1: 'SC_VRS_COMB_MODE_OVERRIDE', + 2: 'SC_VRS_COMB_MODE_MIN', + 3: 'SC_VRS_COMB_MODE_MAX', + 4: 'SC_VRS_COMB_MODE_SATURATE', +} +SC_VRS_COMB_MODE_PASSTHRU = 0 +SC_VRS_COMB_MODE_OVERRIDE = 1 +SC_VRS_COMB_MODE_MIN = 2 +SC_VRS_COMB_MODE_MAX = 3 +SC_VRS_COMB_MODE_SATURATE = 4 +VRSCombinerModeSC = ctypes.c_uint32 # enum + +# values for enumeration 'VRSrate' +VRSrate__enumvalues = { + 0: 'VRS_SHADING_RATE_1X1', + 1: 'VRS_SHADING_RATE_1X2', + 2: 'VRS_SHADING_RATE_UNDEFINED0', + 3: 'VRS_SHADING_RATE_UNDEFINED1', + 4: 'VRS_SHADING_RATE_2X1', + 5: 'VRS_SHADING_RATE_2X2', + 6: 'VRS_SHADING_RATE_2X4', + 7: 'VRS_SHADING_RATE_UNDEFINED2', + 8: 'VRS_SHADING_RATE_UNDEFINED3', + 9: 'VRS_SHADING_RATE_4X2', + 10: 'VRS_SHADING_RATE_4X4', + 11: 'VRS_SHADING_RATE_UNDEFINED4', + 12: 'VRS_SHADING_RATE_16X_SSAA', + 13: 'VRS_SHADING_RATE_8X_SSAA', + 14: 'VRS_SHADING_RATE_4X_SSAA', + 15: 'VRS_SHADING_RATE_2X_SSAA', +} +VRS_SHADING_RATE_1X1 = 0 +VRS_SHADING_RATE_1X2 = 1 +VRS_SHADING_RATE_UNDEFINED0 = 2 +VRS_SHADING_RATE_UNDEFINED1 = 3 +VRS_SHADING_RATE_2X1 = 4 +VRS_SHADING_RATE_2X2 = 5 +VRS_SHADING_RATE_2X4 = 6 +VRS_SHADING_RATE_UNDEFINED2 = 7 +VRS_SHADING_RATE_UNDEFINED3 = 8 +VRS_SHADING_RATE_4X2 = 9 +VRS_SHADING_RATE_4X4 = 10 +VRS_SHADING_RATE_UNDEFINED4 = 11 +VRS_SHADING_RATE_16X_SSAA = 12 +VRS_SHADING_RATE_8X_SSAA = 13 +VRS_SHADING_RATE_4X_SSAA = 14 +VRS_SHADING_RATE_2X_SSAA = 15 +VRSrate = ctypes.c_uint32 # enum + +# values for enumeration 'TC_EA_CID' +TC_EA_CID__enumvalues = { + 0: 'TC_EA_CID_RT', + 1: 'TC_EA_CID_FMASK', + 2: 'TC_EA_CID_DCC', + 3: 'TC_EA_CID_TCPMETA', + 4: 'TC_EA_CID_Z', + 5: 'TC_EA_CID_STENCIL', + 6: 'TC_EA_CID_HTILE', + 7: 'TC_EA_CID_MISC', + 8: 'TC_EA_CID_TCP', + 9: 'TC_EA_CID_SQC', + 10: 'TC_EA_CID_CPF', + 11: 'TC_EA_CID_CPG', + 12: 'TC_EA_CID_IA', + 13: 'TC_EA_CID_WD', + 14: 'TC_EA_CID_PA', + 15: 'TC_EA_CID_UTCL2_TPI', +} +TC_EA_CID_RT = 0 +TC_EA_CID_FMASK = 1 +TC_EA_CID_DCC = 2 +TC_EA_CID_TCPMETA = 3 +TC_EA_CID_Z = 4 +TC_EA_CID_STENCIL = 5 +TC_EA_CID_HTILE = 6 +TC_EA_CID_MISC = 7 +TC_EA_CID_TCP = 8 +TC_EA_CID_SQC = 9 +TC_EA_CID_CPF = 10 +TC_EA_CID_CPG = 11 +TC_EA_CID_IA = 12 +TC_EA_CID_WD = 13 +TC_EA_CID_PA = 14 +TC_EA_CID_UTCL2_TPI = 15 +TC_EA_CID = ctypes.c_uint32 # enum + +# values for enumeration 'TC_NACKS' +TC_NACKS__enumvalues = { + 0: 'TC_NACK_NO_FAULT', + 1: 'TC_NACK_PAGE_FAULT', + 2: 'TC_NACK_PROTECTION_FAULT', + 3: 'TC_NACK_DATA_ERROR', +} +TC_NACK_NO_FAULT = 0 +TC_NACK_PAGE_FAULT = 1 +TC_NACK_PROTECTION_FAULT = 2 +TC_NACK_DATA_ERROR = 3 +TC_NACKS = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP' +TC_OP__enumvalues = { + 0: 'TC_OP_READ', + 1: 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', + 2: 'TC_OP_ATOMIC_FMIN_RTN_32', + 3: 'TC_OP_ATOMIC_FMAX_RTN_32', + 4: 'TC_OP_RESERVED_FOP_RTN_32_0', + 5: 'TC_OP_RESERVED_FADD_RTN_32', + 6: 'TC_OP_RESERVED_FOP_RTN_32_2', + 7: 'TC_OP_ATOMIC_SWAP_RTN_32', + 8: 'TC_OP_ATOMIC_CMPSWAP_RTN_32', + 9: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 10: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 11: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 12: 'TC_OP_PROBE_FILTER', + 13: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 14: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 15: 'TC_OP_ATOMIC_ADD_RTN_32', + 16: 'TC_OP_ATOMIC_SUB_RTN_32', + 17: 'TC_OP_ATOMIC_SMIN_RTN_32', + 18: 'TC_OP_ATOMIC_UMIN_RTN_32', + 19: 'TC_OP_ATOMIC_SMAX_RTN_32', + 20: 'TC_OP_ATOMIC_UMAX_RTN_32', + 21: 'TC_OP_ATOMIC_AND_RTN_32', + 22: 'TC_OP_ATOMIC_OR_RTN_32', + 23: 'TC_OP_ATOMIC_XOR_RTN_32', + 24: 'TC_OP_ATOMIC_INC_RTN_32', + 25: 'TC_OP_ATOMIC_DEC_RTN_32', + 26: 'TC_OP_WBINVL1_VOL', + 27: 'TC_OP_WBINVL1_SD', + 28: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 29: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 30: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 31: 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 32: 'TC_OP_WRITE', + 33: 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 34: 'TC_OP_ATOMIC_FMIN_RTN_64', + 35: 'TC_OP_ATOMIC_FMAX_RTN_64', + 36: 'TC_OP_RESERVED_FOP_RTN_64_0', + 37: 'TC_OP_RESERVED_FOP_RTN_64_1', + 38: 'TC_OP_RESERVED_FOP_RTN_64_2', + 39: 'TC_OP_ATOMIC_SWAP_RTN_64', + 40: 'TC_OP_ATOMIC_CMPSWAP_RTN_64', + 41: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 42: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 43: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 44: 'TC_OP_WBINVL2_SD', + 45: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 46: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 47: 'TC_OP_ATOMIC_ADD_RTN_64', + 48: 'TC_OP_ATOMIC_SUB_RTN_64', + 49: 'TC_OP_ATOMIC_SMIN_RTN_64', + 50: 'TC_OP_ATOMIC_UMIN_RTN_64', + 51: 'TC_OP_ATOMIC_SMAX_RTN_64', + 52: 'TC_OP_ATOMIC_UMAX_RTN_64', + 53: 'TC_OP_ATOMIC_AND_RTN_64', + 54: 'TC_OP_ATOMIC_OR_RTN_64', + 55: 'TC_OP_ATOMIC_XOR_RTN_64', + 56: 'TC_OP_ATOMIC_INC_RTN_64', + 57: 'TC_OP_ATOMIC_DEC_RTN_64', + 58: 'TC_OP_WBL2_NC', + 59: 'TC_OP_WBL2_WC', + 60: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 61: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 62: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 63: 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', + 64: 'TC_OP_WBINVL1', + 65: 'TC_OP_ATOMIC_FCMPSWAP_32', + 66: 'TC_OP_ATOMIC_FMIN_32', + 67: 'TC_OP_ATOMIC_FMAX_32', + 68: 'TC_OP_RESERVED_FOP_32_0', + 69: 'TC_OP_RESERVED_FADD_32', + 70: 'TC_OP_RESERVED_FOP_32_2', + 71: 'TC_OP_ATOMIC_SWAP_32', + 72: 'TC_OP_ATOMIC_CMPSWAP_32', + 73: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 74: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 75: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 76: 'TC_OP_INV_METADATA', + 77: 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 78: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 79: 'TC_OP_ATOMIC_ADD_32', + 80: 'TC_OP_ATOMIC_SUB_32', + 81: 'TC_OP_ATOMIC_SMIN_32', + 82: 'TC_OP_ATOMIC_UMIN_32', + 83: 'TC_OP_ATOMIC_SMAX_32', + 84: 'TC_OP_ATOMIC_UMAX_32', + 85: 'TC_OP_ATOMIC_AND_32', + 86: 'TC_OP_ATOMIC_OR_32', + 87: 'TC_OP_ATOMIC_XOR_32', + 88: 'TC_OP_ATOMIC_INC_32', + 89: 'TC_OP_ATOMIC_DEC_32', + 90: 'TC_OP_INVL2_NC', + 91: 'TC_OP_NOP_RTN0', + 92: 'TC_OP_RESERVED_NON_FLOAT_32_1', + 93: 'TC_OP_RESERVED_NON_FLOAT_32_2', + 94: 'TC_OP_RESERVED_NON_FLOAT_32_3', + 95: 'TC_OP_RESERVED_NON_FLOAT_32_4', + 96: 'TC_OP_WBINVL2', + 97: 'TC_OP_ATOMIC_FCMPSWAP_64', + 98: 'TC_OP_ATOMIC_FMIN_64', + 99: 'TC_OP_ATOMIC_FMAX_64', + 100: 'TC_OP_RESERVED_FOP_64_0', + 101: 'TC_OP_RESERVED_FOP_64_1', + 102: 'TC_OP_RESERVED_FOP_64_2', + 103: 'TC_OP_ATOMIC_SWAP_64', + 104: 'TC_OP_ATOMIC_CMPSWAP_64', + 105: 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 106: 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 107: 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 108: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 109: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 110: 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 111: 'TC_OP_ATOMIC_ADD_64', + 112: 'TC_OP_ATOMIC_SUB_64', + 113: 'TC_OP_ATOMIC_SMIN_64', + 114: 'TC_OP_ATOMIC_UMIN_64', + 115: 'TC_OP_ATOMIC_SMAX_64', + 116: 'TC_OP_ATOMIC_UMAX_64', + 117: 'TC_OP_ATOMIC_AND_64', + 118: 'TC_OP_ATOMIC_OR_64', + 119: 'TC_OP_ATOMIC_XOR_64', + 120: 'TC_OP_ATOMIC_INC_64', + 121: 'TC_OP_ATOMIC_DEC_64', + 122: 'TC_OP_WBINVL2_NC', + 123: 'TC_OP_NOP_ACK', + 124: 'TC_OP_RESERVED_NON_FLOAT_64_1', + 125: 'TC_OP_RESERVED_NON_FLOAT_64_2', + 126: 'TC_OP_RESERVED_NON_FLOAT_64_3', + 127: 'TC_OP_RESERVED_NON_FLOAT_64_4', +} +TC_OP_READ = 0 +TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 +TC_OP_ATOMIC_FMIN_RTN_32 = 2 +TC_OP_ATOMIC_FMAX_RTN_32 = 3 +TC_OP_RESERVED_FOP_RTN_32_0 = 4 +TC_OP_RESERVED_FADD_RTN_32 = 5 +TC_OP_RESERVED_FOP_RTN_32_2 = 6 +TC_OP_ATOMIC_SWAP_RTN_32 = 7 +TC_OP_ATOMIC_CMPSWAP_RTN_32 = 8 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 +TC_OP_PROBE_FILTER = 12 +TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 +TC_OP_ATOMIC_ADD_RTN_32 = 15 +TC_OP_ATOMIC_SUB_RTN_32 = 16 +TC_OP_ATOMIC_SMIN_RTN_32 = 17 +TC_OP_ATOMIC_UMIN_RTN_32 = 18 +TC_OP_ATOMIC_SMAX_RTN_32 = 19 +TC_OP_ATOMIC_UMAX_RTN_32 = 20 +TC_OP_ATOMIC_AND_RTN_32 = 21 +TC_OP_ATOMIC_OR_RTN_32 = 22 +TC_OP_ATOMIC_XOR_RTN_32 = 23 +TC_OP_ATOMIC_INC_RTN_32 = 24 +TC_OP_ATOMIC_DEC_RTN_32 = 25 +TC_OP_WBINVL1_VOL = 26 +TC_OP_WBINVL1_SD = 27 +TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 28 +TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 29 +TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 30 +TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 31 +TC_OP_WRITE = 32 +TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 +TC_OP_ATOMIC_FMIN_RTN_64 = 34 +TC_OP_ATOMIC_FMAX_RTN_64 = 35 +TC_OP_RESERVED_FOP_RTN_64_0 = 36 +TC_OP_RESERVED_FOP_RTN_64_1 = 37 +TC_OP_RESERVED_FOP_RTN_64_2 = 38 +TC_OP_ATOMIC_SWAP_RTN_64 = 39 +TC_OP_ATOMIC_CMPSWAP_RTN_64 = 40 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 +TC_OP_WBINVL2_SD = 44 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 45 +TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 46 +TC_OP_ATOMIC_ADD_RTN_64 = 47 +TC_OP_ATOMIC_SUB_RTN_64 = 48 +TC_OP_ATOMIC_SMIN_RTN_64 = 49 +TC_OP_ATOMIC_UMIN_RTN_64 = 50 +TC_OP_ATOMIC_SMAX_RTN_64 = 51 +TC_OP_ATOMIC_UMAX_RTN_64 = 52 +TC_OP_ATOMIC_AND_RTN_64 = 53 +TC_OP_ATOMIC_OR_RTN_64 = 54 +TC_OP_ATOMIC_XOR_RTN_64 = 55 +TC_OP_ATOMIC_INC_RTN_64 = 56 +TC_OP_ATOMIC_DEC_RTN_64 = 57 +TC_OP_WBL2_NC = 58 +TC_OP_WBL2_WC = 59 +TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 60 +TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 61 +TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 62 +TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 63 +TC_OP_WBINVL1 = 64 +TC_OP_ATOMIC_FCMPSWAP_32 = 65 +TC_OP_ATOMIC_FMIN_32 = 66 +TC_OP_ATOMIC_FMAX_32 = 67 +TC_OP_RESERVED_FOP_32_0 = 68 +TC_OP_RESERVED_FADD_32 = 69 +TC_OP_RESERVED_FOP_32_2 = 70 +TC_OP_ATOMIC_SWAP_32 = 71 +TC_OP_ATOMIC_CMPSWAP_32 = 72 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 +TC_OP_INV_METADATA = 76 +TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 +TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 78 +TC_OP_ATOMIC_ADD_32 = 79 +TC_OP_ATOMIC_SUB_32 = 80 +TC_OP_ATOMIC_SMIN_32 = 81 +TC_OP_ATOMIC_UMIN_32 = 82 +TC_OP_ATOMIC_SMAX_32 = 83 +TC_OP_ATOMIC_UMAX_32 = 84 +TC_OP_ATOMIC_AND_32 = 85 +TC_OP_ATOMIC_OR_32 = 86 +TC_OP_ATOMIC_XOR_32 = 87 +TC_OP_ATOMIC_INC_32 = 88 +TC_OP_ATOMIC_DEC_32 = 89 +TC_OP_INVL2_NC = 90 +TC_OP_NOP_RTN0 = 91 +TC_OP_RESERVED_NON_FLOAT_32_1 = 92 +TC_OP_RESERVED_NON_FLOAT_32_2 = 93 +TC_OP_RESERVED_NON_FLOAT_32_3 = 94 +TC_OP_RESERVED_NON_FLOAT_32_4 = 95 +TC_OP_WBINVL2 = 96 +TC_OP_ATOMIC_FCMPSWAP_64 = 97 +TC_OP_ATOMIC_FMIN_64 = 98 +TC_OP_ATOMIC_FMAX_64 = 99 +TC_OP_RESERVED_FOP_64_0 = 100 +TC_OP_RESERVED_FOP_64_1 = 101 +TC_OP_RESERVED_FOP_64_2 = 102 +TC_OP_ATOMIC_SWAP_64 = 103 +TC_OP_ATOMIC_CMPSWAP_64 = 104 +TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 +TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 +TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 108 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 109 +TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 110 +TC_OP_ATOMIC_ADD_64 = 111 +TC_OP_ATOMIC_SUB_64 = 112 +TC_OP_ATOMIC_SMIN_64 = 113 +TC_OP_ATOMIC_UMIN_64 = 114 +TC_OP_ATOMIC_SMAX_64 = 115 +TC_OP_ATOMIC_UMAX_64 = 116 +TC_OP_ATOMIC_AND_64 = 117 +TC_OP_ATOMIC_OR_64 = 118 +TC_OP_ATOMIC_XOR_64 = 119 +TC_OP_ATOMIC_INC_64 = 120 +TC_OP_ATOMIC_DEC_64 = 121 +TC_OP_WBINVL2_NC = 122 +TC_OP_NOP_ACK = 123 +TC_OP_RESERVED_NON_FLOAT_64_1 = 124 +TC_OP_RESERVED_NON_FLOAT_64_2 = 125 +TC_OP_RESERVED_NON_FLOAT_64_3 = 126 +TC_OP_RESERVED_NON_FLOAT_64_4 = 127 +TC_OP = ctypes.c_uint32 # enum + +# values for enumeration 'TC_OP_MASKS' +TC_OP_MASKS__enumvalues = { + 8: 'TC_OP_MASK_FLUSH_DENROM', + 32: 'TC_OP_MASK_64', + 64: 'TC_OP_MASK_NO_RTN', +} +TC_OP_MASK_FLUSH_DENROM = 8 +TC_OP_MASK_64 = 32 +TC_OP_MASK_NO_RTN = 64 +TC_OP_MASKS = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_EA_CID' +GL2_EA_CID__enumvalues = { + 0: 'GL2_EA_CID_CLIENT', + 1: 'GL2_EA_CID_SDMA', + 2: 'GL2_EA_CID_RLC', + 3: 'GL2_EA_CID_SQC', + 4: 'GL2_EA_CID_CP', + 5: 'GL2_EA_CID_CPDMA', + 6: 'GL2_EA_CID_UTCL2', + 7: 'GL2_EA_CID_RT', + 8: 'GL2_EA_CID_FMASK', + 9: 'GL2_EA_CID_DCC', + 10: 'GL2_EA_CID_Z_STENCIL', + 11: 'GL2_EA_CID_ZPCPSD', + 12: 'GL2_EA_CID_HTILE', + 13: 'GL2_EA_CID_MES', + 15: 'GL2_EA_CID_TCPMETA', +} +GL2_EA_CID_CLIENT = 0 +GL2_EA_CID_SDMA = 1 +GL2_EA_CID_RLC = 2 +GL2_EA_CID_SQC = 3 +GL2_EA_CID_CP = 4 +GL2_EA_CID_CPDMA = 5 +GL2_EA_CID_UTCL2 = 6 +GL2_EA_CID_RT = 7 +GL2_EA_CID_FMASK = 8 +GL2_EA_CID_DCC = 9 +GL2_EA_CID_Z_STENCIL = 10 +GL2_EA_CID_ZPCPSD = 11 +GL2_EA_CID_HTILE = 12 +GL2_EA_CID_MES = 13 +GL2_EA_CID_TCPMETA = 15 +GL2_EA_CID = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_NACKS' +GL2_NACKS__enumvalues = { + 0: 'GL2_NACK_NO_FAULT', + 1: 'GL2_NACK_PAGE_FAULT', + 2: 'GL2_NACK_PROTECTION_FAULT', + 3: 'GL2_NACK_DATA_ERROR', +} +GL2_NACK_NO_FAULT = 0 +GL2_NACK_PAGE_FAULT = 1 +GL2_NACK_PROTECTION_FAULT = 2 +GL2_NACK_DATA_ERROR = 3 +GL2_NACKS = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_OP' +GL2_OP__enumvalues = { + 0: 'GL2_OP_READ', + 1: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', + 2: 'GL2_OP_ATOMIC_FMIN_RTN_32', + 3: 'GL2_OP_ATOMIC_FMAX_RTN_32', + 7: 'GL2_OP_ATOMIC_SWAP_RTN_32', + 8: 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', + 9: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 10: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 11: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 12: 'GL2_OP_PROBE_FILTER', + 13: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 14: 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 15: 'GL2_OP_ATOMIC_ADD_RTN_32', + 16: 'GL2_OP_ATOMIC_SUB_RTN_32', + 17: 'GL2_OP_ATOMIC_SMIN_RTN_32', + 18: 'GL2_OP_ATOMIC_UMIN_RTN_32', + 19: 'GL2_OP_ATOMIC_SMAX_RTN_32', + 20: 'GL2_OP_ATOMIC_UMAX_RTN_32', + 21: 'GL2_OP_ATOMIC_AND_RTN_32', + 22: 'GL2_OP_ATOMIC_OR_RTN_32', + 23: 'GL2_OP_ATOMIC_XOR_RTN_32', + 24: 'GL2_OP_ATOMIC_INC_RTN_32', + 25: 'GL2_OP_ATOMIC_DEC_RTN_32', + 26: 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', + 32: 'GL2_OP_WRITE', + 33: 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', + 34: 'GL2_OP_ATOMIC_FMIN_RTN_64', + 35: 'GL2_OP_ATOMIC_FMAX_RTN_64', + 39: 'GL2_OP_ATOMIC_SWAP_RTN_64', + 40: 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', + 41: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 42: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 43: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 47: 'GL2_OP_ATOMIC_ADD_RTN_64', + 48: 'GL2_OP_ATOMIC_SUB_RTN_64', + 49: 'GL2_OP_ATOMIC_SMIN_RTN_64', + 50: 'GL2_OP_ATOMIC_UMIN_RTN_64', + 51: 'GL2_OP_ATOMIC_SMAX_RTN_64', + 52: 'GL2_OP_ATOMIC_UMAX_RTN_64', + 53: 'GL2_OP_ATOMIC_AND_RTN_64', + 54: 'GL2_OP_ATOMIC_OR_RTN_64', + 55: 'GL2_OP_ATOMIC_XOR_RTN_64', + 56: 'GL2_OP_ATOMIC_INC_RTN_64', + 57: 'GL2_OP_ATOMIC_DEC_RTN_64', + 64: 'GL2_OP_GL1_INV', + 65: 'GL2_OP_ATOMIC_FCMPSWAP_32', + 66: 'GL2_OP_ATOMIC_FMIN_32', + 67: 'GL2_OP_ATOMIC_FMAX_32', + 71: 'GL2_OP_ATOMIC_SWAP_32', + 72: 'GL2_OP_ATOMIC_CMPSWAP_32', + 73: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 74: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 75: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 76: 'GL2_OP_ATOMIC_UMIN_8', + 77: 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 79: 'GL2_OP_ATOMIC_ADD_32', + 80: 'GL2_OP_ATOMIC_SUB_32', + 81: 'GL2_OP_ATOMIC_SMIN_32', + 82: 'GL2_OP_ATOMIC_UMIN_32', + 83: 'GL2_OP_ATOMIC_SMAX_32', + 84: 'GL2_OP_ATOMIC_UMAX_32', + 85: 'GL2_OP_ATOMIC_AND_32', + 86: 'GL2_OP_ATOMIC_OR_32', + 87: 'GL2_OP_ATOMIC_XOR_32', + 88: 'GL2_OP_ATOMIC_INC_32', + 89: 'GL2_OP_ATOMIC_DEC_32', + 91: 'GL2_OP_NOP_RTN0', + 97: 'GL2_OP_ATOMIC_FCMPSWAP_64', + 98: 'GL2_OP_ATOMIC_FMIN_64', + 99: 'GL2_OP_ATOMIC_FMAX_64', + 103: 'GL2_OP_ATOMIC_SWAP_64', + 104: 'GL2_OP_ATOMIC_CMPSWAP_64', + 105: 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 106: 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 107: 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 111: 'GL2_OP_ATOMIC_ADD_64', + 112: 'GL2_OP_ATOMIC_SUB_64', + 113: 'GL2_OP_ATOMIC_SMIN_64', + 114: 'GL2_OP_ATOMIC_UMIN_64', + 115: 'GL2_OP_ATOMIC_SMAX_64', + 116: 'GL2_OP_ATOMIC_UMAX_64', + 117: 'GL2_OP_ATOMIC_AND_64', + 118: 'GL2_OP_ATOMIC_OR_64', + 119: 'GL2_OP_ATOMIC_XOR_64', + 120: 'GL2_OP_ATOMIC_INC_64', + 121: 'GL2_OP_ATOMIC_DEC_64', + 122: 'GL2_OP_ATOMIC_UMAX_8', + 123: 'GL2_OP_NOP_ACK', +} +GL2_OP_READ = 0 +GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 1 +GL2_OP_ATOMIC_FMIN_RTN_32 = 2 +GL2_OP_ATOMIC_FMAX_RTN_32 = 3 +GL2_OP_ATOMIC_SWAP_RTN_32 = 7 +GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 8 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 9 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 10 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 11 +GL2_OP_PROBE_FILTER = 12 +GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 13 +GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 14 +GL2_OP_ATOMIC_ADD_RTN_32 = 15 +GL2_OP_ATOMIC_SUB_RTN_32 = 16 +GL2_OP_ATOMIC_SMIN_RTN_32 = 17 +GL2_OP_ATOMIC_UMIN_RTN_32 = 18 +GL2_OP_ATOMIC_SMAX_RTN_32 = 19 +GL2_OP_ATOMIC_UMAX_RTN_32 = 20 +GL2_OP_ATOMIC_AND_RTN_32 = 21 +GL2_OP_ATOMIC_OR_RTN_32 = 22 +GL2_OP_ATOMIC_XOR_RTN_32 = 23 +GL2_OP_ATOMIC_INC_RTN_32 = 24 +GL2_OP_ATOMIC_DEC_RTN_32 = 25 +GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 26 +GL2_OP_WRITE = 32 +GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 33 +GL2_OP_ATOMIC_FMIN_RTN_64 = 34 +GL2_OP_ATOMIC_FMAX_RTN_64 = 35 +GL2_OP_ATOMIC_SWAP_RTN_64 = 39 +GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 40 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 41 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 42 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 43 +GL2_OP_ATOMIC_ADD_RTN_64 = 47 +GL2_OP_ATOMIC_SUB_RTN_64 = 48 +GL2_OP_ATOMIC_SMIN_RTN_64 = 49 +GL2_OP_ATOMIC_UMIN_RTN_64 = 50 +GL2_OP_ATOMIC_SMAX_RTN_64 = 51 +GL2_OP_ATOMIC_UMAX_RTN_64 = 52 +GL2_OP_ATOMIC_AND_RTN_64 = 53 +GL2_OP_ATOMIC_OR_RTN_64 = 54 +GL2_OP_ATOMIC_XOR_RTN_64 = 55 +GL2_OP_ATOMIC_INC_RTN_64 = 56 +GL2_OP_ATOMIC_DEC_RTN_64 = 57 +GL2_OP_GL1_INV = 64 +GL2_OP_ATOMIC_FCMPSWAP_32 = 65 +GL2_OP_ATOMIC_FMIN_32 = 66 +GL2_OP_ATOMIC_FMAX_32 = 67 +GL2_OP_ATOMIC_SWAP_32 = 71 +GL2_OP_ATOMIC_CMPSWAP_32 = 72 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 73 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 74 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 75 +GL2_OP_ATOMIC_UMIN_8 = 76 +GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 77 +GL2_OP_ATOMIC_ADD_32 = 79 +GL2_OP_ATOMIC_SUB_32 = 80 +GL2_OP_ATOMIC_SMIN_32 = 81 +GL2_OP_ATOMIC_UMIN_32 = 82 +GL2_OP_ATOMIC_SMAX_32 = 83 +GL2_OP_ATOMIC_UMAX_32 = 84 +GL2_OP_ATOMIC_AND_32 = 85 +GL2_OP_ATOMIC_OR_32 = 86 +GL2_OP_ATOMIC_XOR_32 = 87 +GL2_OP_ATOMIC_INC_32 = 88 +GL2_OP_ATOMIC_DEC_32 = 89 +GL2_OP_NOP_RTN0 = 91 +GL2_OP_ATOMIC_FCMPSWAP_64 = 97 +GL2_OP_ATOMIC_FMIN_64 = 98 +GL2_OP_ATOMIC_FMAX_64 = 99 +GL2_OP_ATOMIC_SWAP_64 = 103 +GL2_OP_ATOMIC_CMPSWAP_64 = 104 +GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 105 +GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 106 +GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 107 +GL2_OP_ATOMIC_ADD_64 = 111 +GL2_OP_ATOMIC_SUB_64 = 112 +GL2_OP_ATOMIC_SMIN_64 = 113 +GL2_OP_ATOMIC_UMIN_64 = 114 +GL2_OP_ATOMIC_SMAX_64 = 115 +GL2_OP_ATOMIC_UMAX_64 = 116 +GL2_OP_ATOMIC_AND_64 = 117 +GL2_OP_ATOMIC_OR_64 = 118 +GL2_OP_ATOMIC_XOR_64 = 119 +GL2_OP_ATOMIC_INC_64 = 120 +GL2_OP_ATOMIC_DEC_64 = 121 +GL2_OP_ATOMIC_UMAX_8 = 122 +GL2_OP_NOP_ACK = 123 +GL2_OP = ctypes.c_uint32 # enum + +# values for enumeration 'GL2_OP_MASKS' +GL2_OP_MASKS__enumvalues = { + 8: 'GL2_OP_MASK_FLUSH_DENROM', + 32: 'GL2_OP_MASK_64', + 64: 'GL2_OP_MASK_NO_RTN', +} +GL2_OP_MASK_FLUSH_DENROM = 8 +GL2_OP_MASK_64 = 32 +GL2_OP_MASK_NO_RTN = 64 +GL2_OP_MASKS = ctypes.c_uint32 # enum + +# values for enumeration 'RLC_DOORBELL_MODE' +RLC_DOORBELL_MODE__enumvalues = { + 0: 'RLC_DOORBELL_MODE_DISABLE', + 1: 'RLC_DOORBELL_MODE_ENABLE', + 2: 'RLC_DOORBELL_MODE_ENABLE_PF', + 3: 'RLC_DOORBELL_MODE_ENABLE_PF_VF', +} +RLC_DOORBELL_MODE_DISABLE = 0 +RLC_DOORBELL_MODE_ENABLE = 1 +RLC_DOORBELL_MODE_ENABLE_PF = 2 +RLC_DOORBELL_MODE_ENABLE_PF_VF = 3 +RLC_DOORBELL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'RLC_PERFCOUNTER_SEL' +RLC_PERFCOUNTER_SEL__enumvalues = { + 0: 'RLC_PERF_SEL_POWER_FEATURE_0', + 1: 'RLC_PERF_SEL_POWER_FEATURE_1', + 2: 'RLC_PERF_SEL_CP_INTERRUPT', + 3: 'RLC_PERF_SEL_GRBM_INTERRUPT', + 4: 'RLC_PERF_SEL_SPM_INTERRUPT', + 5: 'RLC_PERF_SEL_IH_INTERRUPT', + 6: 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', +} +RLC_PERF_SEL_POWER_FEATURE_0 = 0 +RLC_PERF_SEL_POWER_FEATURE_1 = 1 +RLC_PERF_SEL_CP_INTERRUPT = 2 +RLC_PERF_SEL_GRBM_INTERRUPT = 3 +RLC_PERF_SEL_SPM_INTERRUPT = 4 +RLC_PERF_SEL_IH_INTERRUPT = 5 +RLC_PERF_SEL_SERDES_COMMAND_WRITE = 6 +RLC_PERFCOUNTER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'RLC_PERFMON_STATE' +RLC_PERFMON_STATE__enumvalues = { + 0: 'RLC_PERFMON_STATE_RESET', + 1: 'RLC_PERFMON_STATE_ENABLE', + 2: 'RLC_PERFMON_STATE_DISABLE', + 3: 'RLC_PERFMON_STATE_RESERVED_3', + 4: 'RLC_PERFMON_STATE_RESERVED_4', + 5: 'RLC_PERFMON_STATE_RESERVED_5', + 6: 'RLC_PERFMON_STATE_RESERVED_6', + 7: 'RLC_PERFMON_STATE_ROLLOVER', +} +RLC_PERFMON_STATE_RESET = 0 +RLC_PERFMON_STATE_ENABLE = 1 +RLC_PERFMON_STATE_DISABLE = 2 +RLC_PERFMON_STATE_RESERVED_3 = 3 +RLC_PERFMON_STATE_RESERVED_4 = 4 +RLC_PERFMON_STATE_RESERVED_5 = 5 +RLC_PERFMON_STATE_RESERVED_6 = 6 +RLC_PERFMON_STATE_ROLLOVER = 7 +RLC_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'RSPM_CMD' +RSPM_CMD__enumvalues = { + 0: 'RSPM_CMD_INVALID', + 1: 'RSPM_CMD_IDLE', + 2: 'RSPM_CMD_CALIBRATE', + 3: 'RSPM_CMD_SPM_RESET', + 4: 'RSPM_CMD_SPM_START', + 5: 'RSPM_CMD_SPM_STOP', + 6: 'RSPM_CMD_PERF_RESET', + 7: 'RSPM_CMD_PERF_SAMPLE', + 8: 'RSPM_CMD_PROF_START', + 9: 'RSPM_CMD_PROF_STOP', + 10: 'RSPM_CMD_FORCE_SAMPLE', +} +RSPM_CMD_INVALID = 0 +RSPM_CMD_IDLE = 1 +RSPM_CMD_CALIBRATE = 2 +RSPM_CMD_SPM_RESET = 3 +RSPM_CMD_SPM_START = 4 +RSPM_CMD_SPM_STOP = 5 +RSPM_CMD_PERF_RESET = 6 +RSPM_CMD_PERF_SAMPLE = 7 +RSPM_CMD_PROF_START = 8 +RSPM_CMD_PROF_STOP = 9 +RSPM_CMD_FORCE_SAMPLE = 10 +RSPM_CMD = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_BASE_MODE' +CLKGATE_BASE_MODE__enumvalues = { + 0: 'MULT_8', + 1: 'MULT_16', +} +MULT_8 = 0 +MULT_16 = 1 +CLKGATE_BASE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CLKGATE_SM_MODE' +CLKGATE_SM_MODE__enumvalues = { + 0: 'ON_SEQ', + 1: 'OFF_SEQ', + 2: 'PROG_SEQ', + 3: 'READ_SEQ', + 4: 'SM_MODE_RESERVED', +} +ON_SEQ = 0 +OFF_SEQ = 1 +PROG_SEQ = 2 +READ_SEQ = 3 +SM_MODE_RESERVED = 4 +CLKGATE_SM_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_FOG_MODE' +SPI_FOG_MODE__enumvalues = { + 0: 'SPI_FOG_NONE', + 1: 'SPI_FOG_EXP', + 2: 'SPI_FOG_EXP2', + 3: 'SPI_FOG_LINEAR', +} +SPI_FOG_NONE = 0 +SPI_FOG_EXP = 1 +SPI_FOG_EXP2 = 2 +SPI_FOG_LINEAR = 3 +SPI_FOG_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_LB_WAVES_SELECT' +SPI_LB_WAVES_SELECT__enumvalues = { + 0: 'HS_GS', + 1: 'PS', + 2: 'CS_NA', + 3: 'SPI_LB_WAVES_RSVD', +} +HS_GS = 0 +PS = 1 +CS_NA = 2 +SPI_LB_WAVES_RSVD = 3 +SPI_LB_WAVES_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PERFCNT_SEL' +SPI_PERFCNT_SEL__enumvalues = { + 1: 'SPI_PERF_GS_WINDOW_VALID', + 2: 'SPI_PERF_GS_BUSY', + 3: 'SPI_PERF_GS_CRAWLER_STALL', + 4: 'SPI_PERF_GS_EVENT_WAVE', + 5: 'SPI_PERF_GS_WAVE', + 6: 'SPI_PERF_GS_PERS_UPD_FULL0', + 7: 'SPI_PERF_GS_PERS_UPD_FULL1', + 8: 'SPI_PERF_GS_FIRST_SUBGRP', + 9: 'SPI_PERF_GS_HS_DEALLOC', + 10: 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', + 11: 'SPI_PERF_GS_POS0_STALL', + 12: 'SPI_PERF_GS_POS1_STALL', + 13: 'SPI_PERF_GS_INDX0_STALL', + 14: 'SPI_PERF_GS_INDX1_STALL', + 15: 'SPI_PERF_GS_PWS_STALL', + 21: 'SPI_PERF_HS_WINDOW_VALID', + 22: 'SPI_PERF_HS_BUSY', + 23: 'SPI_PERF_HS_CRAWLER_STALL', + 24: 'SPI_PERF_HS_FIRST_WAVE', + 25: 'SPI_PERF_HS_OFFCHIP_LDS_STALL', + 26: 'SPI_PERF_HS_EVENT_WAVE', + 27: 'SPI_PERF_HS_WAVE', + 28: 'SPI_PERF_HS_PERS_UPD_FULL0', + 29: 'SPI_PERF_HS_PERS_UPD_FULL1', + 30: 'SPI_PERF_HS_PWS_STALL', + 37: 'SPI_PERF_CSGN_WINDOW_VALID', + 38: 'SPI_PERF_CSGN_BUSY', + 39: 'SPI_PERF_CSGN_NUM_THREADGROUPS', + 40: 'SPI_PERF_CSGN_CRAWLER_STALL', + 41: 'SPI_PERF_CSGN_EVENT_WAVE', + 42: 'SPI_PERF_CSGN_WAVE', + 43: 'SPI_PERF_CSGN_PWS_STALL', + 44: 'SPI_PERF_CSN_WINDOW_VALID', + 45: 'SPI_PERF_CSN_BUSY', + 46: 'SPI_PERF_CSN_NUM_THREADGROUPS', + 47: 'SPI_PERF_CSN_CRAWLER_STALL', + 48: 'SPI_PERF_CSN_EVENT_WAVE', + 49: 'SPI_PERF_CSN_WAVE', + 53: 'SPI_PERF_PS0_WINDOW_VALID', + 54: 'SPI_PERF_PS1_WINDOW_VALID', + 55: 'SPI_PERF_PS2_WINDOW_VALID', + 56: 'SPI_PERF_PS3_WINDOW_VALID', + 57: 'SPI_PERF_PS0_BUSY', + 58: 'SPI_PERF_PS1_BUSY', + 59: 'SPI_PERF_PS2_BUSY', + 60: 'SPI_PERF_PS3_BUSY', + 61: 'SPI_PERF_PS0_ACTIVE', + 62: 'SPI_PERF_PS1_ACTIVE', + 63: 'SPI_PERF_PS2_ACTIVE', + 64: 'SPI_PERF_PS3_ACTIVE', + 65: 'SPI_PERF_PS0_DEALLOC', + 66: 'SPI_PERF_PS1_DEALLOC', + 67: 'SPI_PERF_PS2_DEALLOC', + 68: 'SPI_PERF_PS3_DEALLOC', + 69: 'SPI_PERF_PS0_EVENT_WAVE', + 70: 'SPI_PERF_PS1_EVENT_WAVE', + 71: 'SPI_PERF_PS2_EVENT_WAVE', + 72: 'SPI_PERF_PS3_EVENT_WAVE', + 73: 'SPI_PERF_PS0_WAVE', + 74: 'SPI_PERF_PS1_WAVE', + 75: 'SPI_PERF_PS2_WAVE', + 76: 'SPI_PERF_PS3_WAVE', + 77: 'SPI_PERF_PS0_OPT_WAVE', + 78: 'SPI_PERF_PS1_OPT_WAVE', + 79: 'SPI_PERF_PS2_OPT_WAVE', + 80: 'SPI_PERF_PS3_OPT_WAVE', + 81: 'SPI_PERF_PS0_PRIM_BIN0', + 82: 'SPI_PERF_PS1_PRIM_BIN0', + 83: 'SPI_PERF_PS2_PRIM_BIN0', + 84: 'SPI_PERF_PS3_PRIM_BIN0', + 85: 'SPI_PERF_PS0_PRIM_BIN1', + 86: 'SPI_PERF_PS1_PRIM_BIN1', + 87: 'SPI_PERF_PS2_PRIM_BIN1', + 88: 'SPI_PERF_PS3_PRIM_BIN1', + 89: 'SPI_PERF_PS0_CRAWLER_STALL', + 90: 'SPI_PERF_PS1_CRAWLER_STALL', + 91: 'SPI_PERF_PS2_CRAWLER_STALL', + 92: 'SPI_PERF_PS3_CRAWLER_STALL', + 93: 'SPI_PERF_PS_PERS_UPD_FULL0', + 94: 'SPI_PERF_PS_PERS_UPD_FULL1', + 95: 'SPI_PERF_PS0_2_WAVE_GROUPS', + 96: 'SPI_PERF_PS1_2_WAVE_GROUPS', + 97: 'SPI_PERF_PS2_2_WAVE_GROUPS', + 98: 'SPI_PERF_PS3_2_WAVE_GROUPS', + 99: 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', + 100: 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', + 101: 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', + 102: 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', + 103: 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', + 104: 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', + 105: 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', + 106: 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', + 107: 'SPI_PERF_PS_PWS_STALL', + 141: 'SPI_PERF_RA_PIPE_REQ_BIN2', + 142: 'SPI_PERF_RA_TASK_REQ_BIN3', + 143: 'SPI_PERF_RA_WR_CTL_FULL', + 144: 'SPI_PERF_RA_REQ_NO_ALLOC', + 145: 'SPI_PERF_RA_REQ_NO_ALLOC_PS', + 146: 'SPI_PERF_RA_REQ_NO_ALLOC_GS', + 147: 'SPI_PERF_RA_REQ_NO_ALLOC_HS', + 148: 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', + 149: 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', + 150: 'SPI_PERF_RA_RES_STALL_PS', + 151: 'SPI_PERF_RA_RES_STALL_GS', + 152: 'SPI_PERF_RA_RES_STALL_HS', + 153: 'SPI_PERF_RA_RES_STALL_CSG', + 154: 'SPI_PERF_RA_RES_STALL_CSN', + 155: 'SPI_PERF_RA_TMP_STALL_PS', + 156: 'SPI_PERF_RA_TMP_STALL_GS', + 157: 'SPI_PERF_RA_TMP_STALL_HS', + 158: 'SPI_PERF_RA_TMP_STALL_CSG', + 159: 'SPI_PERF_RA_TMP_STALL_CSN', + 160: 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 161: 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', + 162: 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', + 163: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 164: 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', + 165: 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 166: 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', + 167: 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', + 168: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 169: 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', + 170: 'SPI_PERF_RA_LDS_CU_FULL_PS', + 171: 'SPI_PERF_RA_LDS_CU_FULL_HS', + 172: 'SPI_PERF_RA_LDS_CU_FULL_GS', + 173: 'SPI_PERF_RA_LDS_CU_FULL_CSG', + 174: 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 175: 'SPI_PERF_RA_BAR_CU_FULL_HS', + 176: 'SPI_PERF_RA_BAR_CU_FULL_CSG', + 177: 'SPI_PERF_RA_BAR_CU_FULL_CSN', + 178: 'SPI_PERF_RA_BULKY_CU_FULL_CSG', + 179: 'SPI_PERF_RA_BULKY_CU_FULL_CSN', + 180: 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', + 181: 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 182: 'SPI_PERF_RA_WVLIM_STALL_PS', + 183: 'SPI_PERF_RA_WVLIM_STALL_GS', + 184: 'SPI_PERF_RA_WVLIM_STALL_HS', + 185: 'SPI_PERF_RA_WVLIM_STALL_CSG', + 186: 'SPI_PERF_RA_WVLIM_STALL_CSN', + 187: 'SPI_PERF_RA_GS_LOCK', + 188: 'SPI_PERF_RA_HS_LOCK', + 189: 'SPI_PERF_RA_CSG_LOCK', + 190: 'SPI_PERF_RA_CSN_LOCK', + 191: 'SPI_PERF_RA_RSV_UPD', + 192: 'SPI_PERF_RA_PRE_ALLOC_STALL', + 193: 'SPI_PERF_RA_GFX_UNDER_TUNNEL', + 194: 'SPI_PERF_RA_CSC_UNDER_TUNNEL', + 195: 'SPI_PERF_RA_WVALLOC_STALL', + 196: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', + 197: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', + 198: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', + 199: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', + 200: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', + 201: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', + 202: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', + 203: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', + 204: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', + 205: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', + 206: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', + 207: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', + 208: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', + 209: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', + 210: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', + 211: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', + 212: 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', + 213: 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', + 214: 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', + 215: 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', + 216: 'SPI_PERF_EXP_ARB_COL_CNT', + 217: 'SPI_PERF_EXP_ARB_POS_CNT', + 218: 'SPI_PERF_EXP_ARB_GDS_CNT', + 219: 'SPI_PERF_EXP_ARB_IDX_CNT', + 220: 'SPI_PERF_EXP_WITH_CONFLICT', + 221: 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', + 222: 'SPI_PERF_GS_EXP_DONE', + 223: 'SPI_PERF_PS_EXP_DONE', + 224: 'SPI_PERF_PS_EXP_ARB_CONFLICT', + 225: 'SPI_PERF_PS_EXP_ALLOC', + 226: 'SPI_PERF_PS0_WAVEID_STARVED', + 227: 'SPI_PERF_PS1_WAVEID_STARVED', + 228: 'SPI_PERF_PS2_WAVEID_STARVED', + 229: 'SPI_PERF_PS3_WAVEID_STARVED', + 230: 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', + 231: 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', + 232: 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', + 233: 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', + 234: 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', + 235: 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', + 236: 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', + 237: 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', + 238: 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', + 239: 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', + 240: 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', + 241: 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', + 242: 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', + 243: 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', + 244: 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', + 245: 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', + 246: 'SPI_PERF_NUM_EXPGRANT_EXPORTS', + 253: 'SPI_PERF_PIX_ALLOC_PEND_CNT', + 254: 'SPI_PERF_EXPORT_SCB0_STALL', + 255: 'SPI_PERF_EXPORT_SCB1_STALL', + 256: 'SPI_PERF_EXPORT_SCB2_STALL', + 257: 'SPI_PERF_EXPORT_SCB3_STALL', + 258: 'SPI_PERF_EXPORT_DB0_STALL', + 259: 'SPI_PERF_EXPORT_DB1_STALL', + 260: 'SPI_PERF_EXPORT_DB2_STALL', + 261: 'SPI_PERF_EXPORT_DB3_STALL', + 262: 'SPI_PERF_EXPORT_DB4_STALL', + 263: 'SPI_PERF_EXPORT_DB5_STALL', + 264: 'SPI_PERF_EXPORT_DB6_STALL', + 265: 'SPI_PERF_EXPORT_DB7_STALL', + 266: 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', + 267: 'SPI_PERF_GS_NGG_STALL_MSG_VAL', + 268: 'SPI_PERF_SWC_PS_WR', + 269: 'SPI_PERF_SWC_GS_WR', + 270: 'SPI_PERF_SWC_HS_WR', + 271: 'SPI_PERF_SWC_CSGN_WR', + 272: 'SPI_PERF_SWC_CSN_WR', + 273: 'SPI_PERF_VWC_PS_WR', + 274: 'SPI_PERF_VWC_ES_WR', + 275: 'SPI_PERF_VWC_GS_WR', + 276: 'SPI_PERF_VWC_LS_WR', + 277: 'SPI_PERF_VWC_HS_WR', + 278: 'SPI_PERF_VWC_CSGN_WR', + 279: 'SPI_PERF_VWC_CSN_WR', + 280: 'SPI_PERF_EXP_THROT_UPSTEP', + 281: 'SPI_PERF_EXP_THROT_DOWNSTEP', + 282: 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', + 283: 'SPI_PERF_BUSY', +} +SPI_PERF_GS_WINDOW_VALID = 1 +SPI_PERF_GS_BUSY = 2 +SPI_PERF_GS_CRAWLER_STALL = 3 +SPI_PERF_GS_EVENT_WAVE = 4 +SPI_PERF_GS_WAVE = 5 +SPI_PERF_GS_PERS_UPD_FULL0 = 6 +SPI_PERF_GS_PERS_UPD_FULL1 = 7 +SPI_PERF_GS_FIRST_SUBGRP = 8 +SPI_PERF_GS_HS_DEALLOC = 9 +SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 10 +SPI_PERF_GS_POS0_STALL = 11 +SPI_PERF_GS_POS1_STALL = 12 +SPI_PERF_GS_INDX0_STALL = 13 +SPI_PERF_GS_INDX1_STALL = 14 +SPI_PERF_GS_PWS_STALL = 15 +SPI_PERF_HS_WINDOW_VALID = 21 +SPI_PERF_HS_BUSY = 22 +SPI_PERF_HS_CRAWLER_STALL = 23 +SPI_PERF_HS_FIRST_WAVE = 24 +SPI_PERF_HS_OFFCHIP_LDS_STALL = 25 +SPI_PERF_HS_EVENT_WAVE = 26 +SPI_PERF_HS_WAVE = 27 +SPI_PERF_HS_PERS_UPD_FULL0 = 28 +SPI_PERF_HS_PERS_UPD_FULL1 = 29 +SPI_PERF_HS_PWS_STALL = 30 +SPI_PERF_CSGN_WINDOW_VALID = 37 +SPI_PERF_CSGN_BUSY = 38 +SPI_PERF_CSGN_NUM_THREADGROUPS = 39 +SPI_PERF_CSGN_CRAWLER_STALL = 40 +SPI_PERF_CSGN_EVENT_WAVE = 41 +SPI_PERF_CSGN_WAVE = 42 +SPI_PERF_CSGN_PWS_STALL = 43 +SPI_PERF_CSN_WINDOW_VALID = 44 +SPI_PERF_CSN_BUSY = 45 +SPI_PERF_CSN_NUM_THREADGROUPS = 46 +SPI_PERF_CSN_CRAWLER_STALL = 47 +SPI_PERF_CSN_EVENT_WAVE = 48 +SPI_PERF_CSN_WAVE = 49 +SPI_PERF_PS0_WINDOW_VALID = 53 +SPI_PERF_PS1_WINDOW_VALID = 54 +SPI_PERF_PS2_WINDOW_VALID = 55 +SPI_PERF_PS3_WINDOW_VALID = 56 +SPI_PERF_PS0_BUSY = 57 +SPI_PERF_PS1_BUSY = 58 +SPI_PERF_PS2_BUSY = 59 +SPI_PERF_PS3_BUSY = 60 +SPI_PERF_PS0_ACTIVE = 61 +SPI_PERF_PS1_ACTIVE = 62 +SPI_PERF_PS2_ACTIVE = 63 +SPI_PERF_PS3_ACTIVE = 64 +SPI_PERF_PS0_DEALLOC = 65 +SPI_PERF_PS1_DEALLOC = 66 +SPI_PERF_PS2_DEALLOC = 67 +SPI_PERF_PS3_DEALLOC = 68 +SPI_PERF_PS0_EVENT_WAVE = 69 +SPI_PERF_PS1_EVENT_WAVE = 70 +SPI_PERF_PS2_EVENT_WAVE = 71 +SPI_PERF_PS3_EVENT_WAVE = 72 +SPI_PERF_PS0_WAVE = 73 +SPI_PERF_PS1_WAVE = 74 +SPI_PERF_PS2_WAVE = 75 +SPI_PERF_PS3_WAVE = 76 +SPI_PERF_PS0_OPT_WAVE = 77 +SPI_PERF_PS1_OPT_WAVE = 78 +SPI_PERF_PS2_OPT_WAVE = 79 +SPI_PERF_PS3_OPT_WAVE = 80 +SPI_PERF_PS0_PRIM_BIN0 = 81 +SPI_PERF_PS1_PRIM_BIN0 = 82 +SPI_PERF_PS2_PRIM_BIN0 = 83 +SPI_PERF_PS3_PRIM_BIN0 = 84 +SPI_PERF_PS0_PRIM_BIN1 = 85 +SPI_PERF_PS1_PRIM_BIN1 = 86 +SPI_PERF_PS2_PRIM_BIN1 = 87 +SPI_PERF_PS3_PRIM_BIN1 = 88 +SPI_PERF_PS0_CRAWLER_STALL = 89 +SPI_PERF_PS1_CRAWLER_STALL = 90 +SPI_PERF_PS2_CRAWLER_STALL = 91 +SPI_PERF_PS3_CRAWLER_STALL = 92 +SPI_PERF_PS_PERS_UPD_FULL0 = 93 +SPI_PERF_PS_PERS_UPD_FULL1 = 94 +SPI_PERF_PS0_2_WAVE_GROUPS = 95 +SPI_PERF_PS1_2_WAVE_GROUPS = 96 +SPI_PERF_PS2_2_WAVE_GROUPS = 97 +SPI_PERF_PS3_2_WAVE_GROUPS = 98 +SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 99 +SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 100 +SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 101 +SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 102 +SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 103 +SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 104 +SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 105 +SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 106 +SPI_PERF_PS_PWS_STALL = 107 +SPI_PERF_RA_PIPE_REQ_BIN2 = 141 +SPI_PERF_RA_TASK_REQ_BIN3 = 142 +SPI_PERF_RA_WR_CTL_FULL = 143 +SPI_PERF_RA_REQ_NO_ALLOC = 144 +SPI_PERF_RA_REQ_NO_ALLOC_PS = 145 +SPI_PERF_RA_REQ_NO_ALLOC_GS = 146 +SPI_PERF_RA_REQ_NO_ALLOC_HS = 147 +SPI_PERF_RA_REQ_NO_ALLOC_CSG = 148 +SPI_PERF_RA_REQ_NO_ALLOC_CSN = 149 +SPI_PERF_RA_RES_STALL_PS = 150 +SPI_PERF_RA_RES_STALL_GS = 151 +SPI_PERF_RA_RES_STALL_HS = 152 +SPI_PERF_RA_RES_STALL_CSG = 153 +SPI_PERF_RA_RES_STALL_CSN = 154 +SPI_PERF_RA_TMP_STALL_PS = 155 +SPI_PERF_RA_TMP_STALL_GS = 156 +SPI_PERF_RA_TMP_STALL_HS = 157 +SPI_PERF_RA_TMP_STALL_CSG = 158 +SPI_PERF_RA_TMP_STALL_CSN = 159 +SPI_PERF_RA_WAVE_SIMD_FULL_PS = 160 +SPI_PERF_RA_WAVE_SIMD_FULL_GS = 161 +SPI_PERF_RA_WAVE_SIMD_FULL_HS = 162 +SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 163 +SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 164 +SPI_PERF_RA_VGPR_SIMD_FULL_PS = 165 +SPI_PERF_RA_VGPR_SIMD_FULL_GS = 166 +SPI_PERF_RA_VGPR_SIMD_FULL_HS = 167 +SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 168 +SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 169 +SPI_PERF_RA_LDS_CU_FULL_PS = 170 +SPI_PERF_RA_LDS_CU_FULL_HS = 171 +SPI_PERF_RA_LDS_CU_FULL_GS = 172 +SPI_PERF_RA_LDS_CU_FULL_CSG = 173 +SPI_PERF_RA_LDS_CU_FULL_CSN = 174 +SPI_PERF_RA_BAR_CU_FULL_HS = 175 +SPI_PERF_RA_BAR_CU_FULL_CSG = 176 +SPI_PERF_RA_BAR_CU_FULL_CSN = 177 +SPI_PERF_RA_BULKY_CU_FULL_CSG = 178 +SPI_PERF_RA_BULKY_CU_FULL_CSN = 179 +SPI_PERF_RA_TGLIM_CU_FULL_CSG = 180 +SPI_PERF_RA_TGLIM_CU_FULL_CSN = 181 +SPI_PERF_RA_WVLIM_STALL_PS = 182 +SPI_PERF_RA_WVLIM_STALL_GS = 183 +SPI_PERF_RA_WVLIM_STALL_HS = 184 +SPI_PERF_RA_WVLIM_STALL_CSG = 185 +SPI_PERF_RA_WVLIM_STALL_CSN = 186 +SPI_PERF_RA_GS_LOCK = 187 +SPI_PERF_RA_HS_LOCK = 188 +SPI_PERF_RA_CSG_LOCK = 189 +SPI_PERF_RA_CSN_LOCK = 190 +SPI_PERF_RA_RSV_UPD = 191 +SPI_PERF_RA_PRE_ALLOC_STALL = 192 +SPI_PERF_RA_GFX_UNDER_TUNNEL = 193 +SPI_PERF_RA_CSC_UNDER_TUNNEL = 194 +SPI_PERF_RA_WVALLOC_STALL = 195 +SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 196 +SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 197 +SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 198 +SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 199 +SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 200 +SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 201 +SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 202 +SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 203 +SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 204 +SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 205 +SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 206 +SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 207 +SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 208 +SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 209 +SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 210 +SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 211 +SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 212 +SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 213 +SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 214 +SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 215 +SPI_PERF_EXP_ARB_COL_CNT = 216 +SPI_PERF_EXP_ARB_POS_CNT = 217 +SPI_PERF_EXP_ARB_GDS_CNT = 218 +SPI_PERF_EXP_ARB_IDX_CNT = 219 +SPI_PERF_EXP_WITH_CONFLICT = 220 +SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 221 +SPI_PERF_GS_EXP_DONE = 222 +SPI_PERF_PS_EXP_DONE = 223 +SPI_PERF_PS_EXP_ARB_CONFLICT = 224 +SPI_PERF_PS_EXP_ALLOC = 225 +SPI_PERF_PS0_WAVEID_STARVED = 226 +SPI_PERF_PS1_WAVEID_STARVED = 227 +SPI_PERF_PS2_WAVEID_STARVED = 228 +SPI_PERF_PS3_WAVEID_STARVED = 229 +SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 230 +SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 231 +SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 232 +SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 233 +SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 234 +SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 235 +SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 236 +SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 237 +SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 238 +SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 239 +SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 240 +SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 241 +SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 242 +SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 243 +SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 244 +SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 245 +SPI_PERF_NUM_EXPGRANT_EXPORTS = 246 +SPI_PERF_PIX_ALLOC_PEND_CNT = 253 +SPI_PERF_EXPORT_SCB0_STALL = 254 +SPI_PERF_EXPORT_SCB1_STALL = 255 +SPI_PERF_EXPORT_SCB2_STALL = 256 +SPI_PERF_EXPORT_SCB3_STALL = 257 +SPI_PERF_EXPORT_DB0_STALL = 258 +SPI_PERF_EXPORT_DB1_STALL = 259 +SPI_PERF_EXPORT_DB2_STALL = 260 +SPI_PERF_EXPORT_DB3_STALL = 261 +SPI_PERF_EXPORT_DB4_STALL = 262 +SPI_PERF_EXPORT_DB5_STALL = 263 +SPI_PERF_EXPORT_DB6_STALL = 264 +SPI_PERF_EXPORT_DB7_STALL = 265 +SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 266 +SPI_PERF_GS_NGG_STALL_MSG_VAL = 267 +SPI_PERF_SWC_PS_WR = 268 +SPI_PERF_SWC_GS_WR = 269 +SPI_PERF_SWC_HS_WR = 270 +SPI_PERF_SWC_CSGN_WR = 271 +SPI_PERF_SWC_CSN_WR = 272 +SPI_PERF_VWC_PS_WR = 273 +SPI_PERF_VWC_ES_WR = 274 +SPI_PERF_VWC_GS_WR = 275 +SPI_PERF_VWC_LS_WR = 276 +SPI_PERF_VWC_HS_WR = 277 +SPI_PERF_VWC_CSGN_WR = 278 +SPI_PERF_VWC_CSN_WR = 279 +SPI_PERF_EXP_THROT_UPSTEP = 280 +SPI_PERF_EXP_THROT_DOWNSTEP = 281 +SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 282 +SPI_PERF_BUSY = 283 +SPI_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PNT_SPRITE_OVERRIDE' +SPI_PNT_SPRITE_OVERRIDE__enumvalues = { + 0: 'SPI_PNT_SPRITE_SEL_0', + 1: 'SPI_PNT_SPRITE_SEL_1', + 2: 'SPI_PNT_SPRITE_SEL_S', + 3: 'SPI_PNT_SPRITE_SEL_T', + 4: 'SPI_PNT_SPRITE_SEL_NONE', +} +SPI_PNT_SPRITE_SEL_0 = 0 +SPI_PNT_SPRITE_SEL_1 = 1 +SPI_PNT_SPRITE_SEL_S = 2 +SPI_PNT_SPRITE_SEL_T = 3 +SPI_PNT_SPRITE_SEL_NONE = 4 +SPI_PNT_SPRITE_OVERRIDE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_PS_LDS_GROUP_SIZE' +SPI_PS_LDS_GROUP_SIZE__enumvalues = { + 0: 'SPI_PS_LDS_GROUP_1', + 1: 'SPI_PS_LDS_GROUP_2', + 2: 'SPI_PS_LDS_GROUP_4', +} +SPI_PS_LDS_GROUP_1 = 0 +SPI_PS_LDS_GROUP_2 = 1 +SPI_PS_LDS_GROUP_4 = 2 +SPI_PS_LDS_GROUP_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SAMPLE_CNTL' +SPI_SAMPLE_CNTL__enumvalues = { + 0: 'CENTROIDS_ONLY', + 1: 'CENTERS_ONLY', + 2: 'CENTROIDS_AND_CENTERS', + 3: 'UNDEF', +} +CENTROIDS_ONLY = 0 +CENTERS_ONLY = 1 +CENTROIDS_AND_CENTERS = 2 +UNDEF = 3 +SPI_SAMPLE_CNTL = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_EX_FORMAT' +SPI_SHADER_EX_FORMAT__enumvalues = { + 0: 'SPI_SHADER_ZERO', + 1: 'SPI_SHADER_32_R', + 2: 'SPI_SHADER_32_GR', + 3: 'SPI_SHADER_32_AR', + 4: 'SPI_SHADER_FP16_ABGR', + 5: 'SPI_SHADER_UNORM16_ABGR', + 6: 'SPI_SHADER_SNORM16_ABGR', + 7: 'SPI_SHADER_UINT16_ABGR', + 8: 'SPI_SHADER_SINT16_ABGR', + 9: 'SPI_SHADER_32_ABGR', +} +SPI_SHADER_ZERO = 0 +SPI_SHADER_32_R = 1 +SPI_SHADER_32_GR = 2 +SPI_SHADER_32_AR = 3 +SPI_SHADER_FP16_ABGR = 4 +SPI_SHADER_UNORM16_ABGR = 5 +SPI_SHADER_SNORM16_ABGR = 6 +SPI_SHADER_UINT16_ABGR = 7 +SPI_SHADER_SINT16_ABGR = 8 +SPI_SHADER_32_ABGR = 9 +SPI_SHADER_EX_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SPI_SHADER_FORMAT' +SPI_SHADER_FORMAT__enumvalues = { + 0: 'SPI_SHADER_NONE', + 1: 'SPI_SHADER_1COMP', + 2: 'SPI_SHADER_2COMP', + 3: 'SPI_SHADER_4COMPRESS', + 4: 'SPI_SHADER_4COMP', +} +SPI_SHADER_NONE = 0 +SPI_SHADER_1COMP = 1 +SPI_SHADER_2COMP = 2 +SPI_SHADER_4COMPRESS = 3 +SPI_SHADER_4COMP = 4 +SPI_SHADER_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ADDRESS_MODE' +SH_MEM_ADDRESS_MODE__enumvalues = { + 0: 'SH_MEM_ADDRESS_MODE_64', + 1: 'SH_MEM_ADDRESS_MODE_32', +} +SH_MEM_ADDRESS_MODE_64 = 0 +SH_MEM_ADDRESS_MODE_32 = 1 +SH_MEM_ADDRESS_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SH_MEM_ALIGNMENT_MODE' +SH_MEM_ALIGNMENT_MODE__enumvalues = { + 0: 'SH_MEM_ALIGNMENT_MODE_DWORD', + 1: 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 2: 'SH_MEM_ALIGNMENT_MODE_STRICT', + 3: 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', +} +SH_MEM_ALIGNMENT_MODE_DWORD = 0 +SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 1 +SH_MEM_ALIGNMENT_MODE_STRICT = 2 +SH_MEM_ALIGNMENT_MODE_UNALIGNED = 3 +SH_MEM_ALIGNMENT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQG_PERF_SEL' +SQG_PERF_SEL__enumvalues = { + 0: 'SQG_PERF_SEL_NONE', + 1: 'SQG_PERF_SEL_MSG_BUS_BUSY', + 2: 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', + 3: 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', + 4: 'SQG_PERF_SEL_EXP_BUS0_BUSY', + 5: 'SQG_PERF_SEL_EXP_BUS1_BUSY', + 6: 'SQG_PERF_SEL_TTRACE_REQS', + 7: 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', + 8: 'SQG_PERF_SEL_TTRACE_STALL', + 9: 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', + 10: 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', + 11: 'SQG_PERF_SEL_EVENTS', + 12: 'SQG_PERF_SEL_WAVES_RESTORED', + 13: 'SQG_PERF_SEL_WAVES_SAVED', + 14: 'SQG_PERF_SEL_ACCUM_PREV', + 15: 'SQG_PERF_SEL_CYCLES', + 16: 'SQG_PERF_SEL_BUSY_CYCLES', + 17: 'SQG_PERF_SEL_WAVE_CYCLES', + 18: 'SQG_PERF_SEL_MSG', + 19: 'SQG_PERF_SEL_MSG_INTERRUPT', + 20: 'SQG_PERF_SEL_WAVES', + 21: 'SQG_PERF_SEL_WAVES_32', + 22: 'SQG_PERF_SEL_WAVES_64', + 23: 'SQG_PERF_SEL_LEVEL_WAVES', + 24: 'SQG_PERF_SEL_ITEMS', + 25: 'SQG_PERF_SEL_WAVE32_ITEMS', + 26: 'SQG_PERF_SEL_WAVE64_ITEMS', + 27: 'SQG_PERF_SEL_PS_QUADS', + 28: 'SQG_PERF_SEL_WAVES_EQ_64', + 29: 'SQG_PERF_SEL_WAVES_EQ_32', + 30: 'SQG_PERF_SEL_WAVES_LT_64', + 31: 'SQG_PERF_SEL_WAVES_LT_48', + 32: 'SQG_PERF_SEL_WAVES_LT_32', + 33: 'SQG_PERF_SEL_WAVES_LT_16', + 34: 'SQG_PERF_SEL_DUMMY_LAST', +} +SQG_PERF_SEL_NONE = 0 +SQG_PERF_SEL_MSG_BUS_BUSY = 1 +SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 2 +SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 3 +SQG_PERF_SEL_EXP_BUS0_BUSY = 4 +SQG_PERF_SEL_EXP_BUS1_BUSY = 5 +SQG_PERF_SEL_TTRACE_REQS = 6 +SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 7 +SQG_PERF_SEL_TTRACE_STALL = 8 +SQG_PERF_SEL_TTRACE_LOST_PACKETS = 9 +SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 10 +SQG_PERF_SEL_EVENTS = 11 +SQG_PERF_SEL_WAVES_RESTORED = 12 +SQG_PERF_SEL_WAVES_SAVED = 13 +SQG_PERF_SEL_ACCUM_PREV = 14 +SQG_PERF_SEL_CYCLES = 15 +SQG_PERF_SEL_BUSY_CYCLES = 16 +SQG_PERF_SEL_WAVE_CYCLES = 17 +SQG_PERF_SEL_MSG = 18 +SQG_PERF_SEL_MSG_INTERRUPT = 19 +SQG_PERF_SEL_WAVES = 20 +SQG_PERF_SEL_WAVES_32 = 21 +SQG_PERF_SEL_WAVES_64 = 22 +SQG_PERF_SEL_LEVEL_WAVES = 23 +SQG_PERF_SEL_ITEMS = 24 +SQG_PERF_SEL_WAVE32_ITEMS = 25 +SQG_PERF_SEL_WAVE64_ITEMS = 26 +SQG_PERF_SEL_PS_QUADS = 27 +SQG_PERF_SEL_WAVES_EQ_64 = 28 +SQG_PERF_SEL_WAVES_EQ_32 = 29 +SQG_PERF_SEL_WAVES_LT_64 = 30 +SQG_PERF_SEL_WAVES_LT_48 = 31 +SQG_PERF_SEL_WAVES_LT_32 = 32 +SQG_PERF_SEL_WAVES_LT_16 = 33 +SQG_PERF_SEL_DUMMY_LAST = 34 +SQG_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_CAC_POWER_SEL' +SQ_CAC_POWER_SEL__enumvalues = { + 0: 'SQ_CAC_POWER_VALU', + 1: 'SQ_CAC_POWER_VALU0', + 2: 'SQ_CAC_POWER_VALU1', + 3: 'SQ_CAC_POWER_VALU2', + 4: 'SQ_CAC_POWER_GPR_RD', + 5: 'SQ_CAC_POWER_GPR_WR', + 6: 'SQ_CAC_POWER_LDS_BUSY', + 7: 'SQ_CAC_POWER_ALU_BUSY', + 8: 'SQ_CAC_POWER_TEX_BUSY', +} +SQ_CAC_POWER_VALU = 0 +SQ_CAC_POWER_VALU0 = 1 +SQ_CAC_POWER_VALU1 = 2 +SQ_CAC_POWER_VALU2 = 3 +SQ_CAC_POWER_GPR_RD = 4 +SQ_CAC_POWER_GPR_WR = 5 +SQ_CAC_POWER_LDS_BUSY = 6 +SQ_CAC_POWER_ALU_BUSY = 7 +SQ_CAC_POWER_TEX_BUSY = 8 +SQ_CAC_POWER_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_EDC_INFO_SOURCE' +SQ_EDC_INFO_SOURCE__enumvalues = { + 0: 'SQ_EDC_INFO_SOURCE_INVALID', + 1: 'SQ_EDC_INFO_SOURCE_INST', + 2: 'SQ_EDC_INFO_SOURCE_SGPR', + 3: 'SQ_EDC_INFO_SOURCE_VGPR', + 4: 'SQ_EDC_INFO_SOURCE_LDS', + 5: 'SQ_EDC_INFO_SOURCE_GDS', + 6: 'SQ_EDC_INFO_SOURCE_TA', +} +SQ_EDC_INFO_SOURCE_INVALID = 0 +SQ_EDC_INFO_SOURCE_INST = 1 +SQ_EDC_INFO_SOURCE_SGPR = 2 +SQ_EDC_INFO_SOURCE_VGPR = 3 +SQ_EDC_INFO_SOURCE_LDS = 4 +SQ_EDC_INFO_SOURCE_GDS = 5 +SQ_EDC_INFO_SOURCE_TA = 6 +SQ_EDC_INFO_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IBUF_ST' +SQ_IBUF_ST__enumvalues = { + 0: 'SQ_IBUF_IB_IDLE', + 1: 'SQ_IBUF_IB_INI_WAIT_GNT', + 2: 'SQ_IBUF_IB_INI_WAIT_DRET', + 3: 'SQ_IBUF_IB_LE_4DW', + 4: 'SQ_IBUF_IB_WAIT_DRET', + 5: 'SQ_IBUF_IB_EMPTY_WAIT_DRET', + 6: 'SQ_IBUF_IB_DRET', + 7: 'SQ_IBUF_IB_EMPTY_WAIT_GNT', +} +SQ_IBUF_IB_IDLE = 0 +SQ_IBUF_IB_INI_WAIT_GNT = 1 +SQ_IBUF_IB_INI_WAIT_DRET = 2 +SQ_IBUF_IB_LE_4DW = 3 +SQ_IBUF_IB_WAIT_DRET = 4 +SQ_IBUF_IB_EMPTY_WAIT_DRET = 5 +SQ_IBUF_IB_DRET = 6 +SQ_IBUF_IB_EMPTY_WAIT_GNT = 7 +SQ_IBUF_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IMG_FILTER_TYPE' +SQ_IMG_FILTER_TYPE__enumvalues = { + 0: 'SQ_IMG_FILTER_MODE_BLEND', + 1: 'SQ_IMG_FILTER_MODE_MIN', + 2: 'SQ_IMG_FILTER_MODE_MAX', +} +SQ_IMG_FILTER_MODE_BLEND = 0 +SQ_IMG_FILTER_MODE_MIN = 1 +SQ_IMG_FILTER_MODE_MAX = 2 +SQ_IMG_FILTER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_CMD' +SQ_IND_CMD_CMD__enumvalues = { + 0: 'SQ_IND_CMD_CMD_NULL', + 1: 'SQ_IND_CMD_CMD_SETHALT', + 2: 'SQ_IND_CMD_CMD_SAVECTX', + 3: 'SQ_IND_CMD_CMD_KILL', + 4: 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', + 5: 'SQ_IND_CMD_CMD_TRAP', + 6: 'SQ_IND_CMD_CMD_SET_SPI_PRIO', + 7: 'SQ_IND_CMD_CMD_SETFATALHALT', + 8: 'SQ_IND_CMD_CMD_SINGLE_STEP', +} +SQ_IND_CMD_CMD_NULL = 0 +SQ_IND_CMD_CMD_SETHALT = 1 +SQ_IND_CMD_CMD_SAVECTX = 2 +SQ_IND_CMD_CMD_KILL = 3 +SQ_IND_CMD_CMD_TRAP_AFTER_INST = 4 +SQ_IND_CMD_CMD_TRAP = 5 +SQ_IND_CMD_CMD_SET_SPI_PRIO = 6 +SQ_IND_CMD_CMD_SETFATALHALT = 7 +SQ_IND_CMD_CMD_SINGLE_STEP = 8 +SQ_IND_CMD_CMD = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_IND_CMD_MODE' +SQ_IND_CMD_MODE__enumvalues = { + 0: 'SQ_IND_CMD_MODE_SINGLE', + 1: 'SQ_IND_CMD_MODE_BROADCAST', + 2: 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', + 3: 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 4: 'SQ_IND_CMD_MODE_BROADCAST_ME', +} +SQ_IND_CMD_MODE_SINGLE = 0 +SQ_IND_CMD_MODE_BROADCAST = 1 +SQ_IND_CMD_MODE_BROADCAST_QUEUE = 2 +SQ_IND_CMD_MODE_BROADCAST_PIPE = 3 +SQ_IND_CMD_MODE_BROADCAST_ME = 4 +SQ_IND_CMD_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INST_STR_ST' +SQ_INST_STR_ST__enumvalues = { + 0: 'SQ_INST_STR_IB_WAVE_NORML', + 1: 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 2: 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 3: 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 4: 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', + 5: 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', +} +SQ_INST_STR_IB_WAVE_NORML = 0 +SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 1 +SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 2 +SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 3 +SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 4 +SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 5 +SQ_INST_STR_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_INST_TYPE' +SQ_INST_TYPE__enumvalues = { + 0: 'SQ_INST_TYPE_VALU', + 1: 'SQ_INST_TYPE_SCALAR', + 2: 'SQ_INST_TYPE_TEX', + 3: 'SQ_INST_TYPE_LDS', + 4: 'SQ_INST_TYPE_LDS_DIRECT', + 5: 'SQ_INST_TYPE_EXP', + 6: 'SQ_INST_TYPE_MSG', + 7: 'SQ_INST_TYPE_BARRIER', + 8: 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', + 9: 'SQ_INST_TYPE_BRANCH_TAKEN', + 10: 'SQ_INST_TYPE_JUMP', + 11: 'SQ_INST_TYPE_OTHER', + 12: 'SQ_INST_TYPE_NONE', +} +SQ_INST_TYPE_VALU = 0 +SQ_INST_TYPE_SCALAR = 1 +SQ_INST_TYPE_TEX = 2 +SQ_INST_TYPE_LDS = 3 +SQ_INST_TYPE_LDS_DIRECT = 4 +SQ_INST_TYPE_EXP = 5 +SQ_INST_TYPE_MSG = 6 +SQ_INST_TYPE_BARRIER = 7 +SQ_INST_TYPE_BRANCH_NOT_TAKEN = 8 +SQ_INST_TYPE_BRANCH_TAKEN = 9 +SQ_INST_TYPE_JUMP = 10 +SQ_INST_TYPE_OTHER = 11 +SQ_INST_TYPE_NONE = 12 +SQ_INST_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_LLC_CTL' +SQ_LLC_CTL__enumvalues = { + 0: 'SQ_LLC_0', + 1: 'SQ_LLC_1', + 2: 'SQ_LLC_RSVD_2', + 3: 'SQ_LLC_BYPASS', +} +SQ_LLC_0 = 0 +SQ_LLC_1 = 1 +SQ_LLC_RSVD_2 = 2 +SQ_LLC_BYPASS = 3 +SQ_LLC_CTL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_NO_INST_ISSUE' +SQ_NO_INST_ISSUE__enumvalues = { + 0: 'SQ_NO_INST_ISSUE_NO_INSTS', + 1: 'SQ_NO_INST_ISSUE_ALU_DEP', + 2: 'SQ_NO_INST_ISSUE_S_WAITCNT', + 3: 'SQ_NO_INST_ISSUE_NO_ARB_WIN', + 4: 'SQ_NO_INST_ISSUE_SLEEP_WAIT', + 5: 'SQ_NO_INST_ISSUE_BARRIER_WAIT', + 6: 'SQ_NO_INST_ISSUE_OTHER', +} +SQ_NO_INST_ISSUE_NO_INSTS = 0 +SQ_NO_INST_ISSUE_ALU_DEP = 1 +SQ_NO_INST_ISSUE_S_WAITCNT = 2 +SQ_NO_INST_ISSUE_NO_ARB_WIN = 3 +SQ_NO_INST_ISSUE_SLEEP_WAIT = 4 +SQ_NO_INST_ISSUE_BARRIER_WAIT = 5 +SQ_NO_INST_ISSUE_OTHER = 6 +SQ_NO_INST_ISSUE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_OOB_SELECT' +SQ_OOB_SELECT__enumvalues = { + 0: 'SQ_OOB_INDEX_AND_OFFSET', + 1: 'SQ_OOB_INDEX_ONLY', + 2: 'SQ_OOB_NUM_RECORDS_0', + 3: 'SQ_OOB_COMPLETE', +} +SQ_OOB_INDEX_AND_OFFSET = 0 +SQ_OOB_INDEX_ONLY = 1 +SQ_OOB_NUM_RECORDS_0 = 2 +SQ_OOB_COMPLETE = 3 +SQ_OOB_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_PERF_SEL' +SQ_PERF_SEL__enumvalues = { + 0: 'SQ_PERF_SEL_NONE', + 1: 'SQ_PERF_SEL_ACCUM_PREV', + 2: 'SQ_PERF_SEL_CYCLES', + 3: 'SQ_PERF_SEL_BUSY_CYCLES', + 4: 'SQ_PERF_SEL_WAVES', + 5: 'SQ_PERF_SEL_WAVES_32', + 6: 'SQ_PERF_SEL_WAVES_64', + 7: 'SQ_PERF_SEL_LEVEL_WAVES', + 8: 'SQ_PERF_SEL_ITEMS', + 9: 'SQ_PERF_SEL_WAVE32_ITEMS', + 10: 'SQ_PERF_SEL_WAVE64_ITEMS', + 11: 'SQ_PERF_SEL_PS_QUADS', + 12: 'SQ_PERF_SEL_EVENTS', + 13: 'SQ_PERF_SEL_WAVES_EQ_32', + 14: 'SQ_PERF_SEL_WAVES_EQ_64', + 15: 'SQ_PERF_SEL_WAVES_LT_64', + 16: 'SQ_PERF_SEL_WAVES_LT_48', + 17: 'SQ_PERF_SEL_WAVES_LT_32', + 18: 'SQ_PERF_SEL_WAVES_LT_16', + 19: 'SQ_PERF_SEL_WAVES_RESTORED', + 20: 'SQ_PERF_SEL_WAVES_SAVED', + 21: 'SQ_PERF_SEL_MSG', + 22: 'SQ_PERF_SEL_MSG_INTERRUPT', + 23: 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', + 24: 'SQ_PERF_SEL_WAVE_CYCLES', + 25: 'SQ_PERF_SEL_WAVE_READY', + 26: 'SQ_PERF_SEL_WAIT_INST_ANY', + 27: 'SQ_PERF_SEL_WAIT_INST_VALU', + 28: 'SQ_PERF_SEL_WAIT_INST_SCA', + 29: 'SQ_PERF_SEL_WAIT_INST_LDS', + 30: 'SQ_PERF_SEL_WAIT_INST_TEX', + 31: 'SQ_PERF_SEL_WAIT_INST_FLAT', + 32: 'SQ_PERF_SEL_WAIT_INST_VMEM', + 33: 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', + 34: 'SQ_PERF_SEL_WAIT_INST_BR_MSG', + 35: 'SQ_PERF_SEL_WAIT_ANY', + 36: 'SQ_PERF_SEL_WAIT_CNT_ANY', + 37: 'SQ_PERF_SEL_WAIT_CNT_VMVS', + 38: 'SQ_PERF_SEL_WAIT_CNT_LGKM', + 39: 'SQ_PERF_SEL_WAIT_CNT_EXP', + 40: 'SQ_PERF_SEL_WAIT_TTRACE', + 41: 'SQ_PERF_SEL_WAIT_IFETCH', + 42: 'SQ_PERF_SEL_WAIT_BARRIER', + 43: 'SQ_PERF_SEL_WAIT_EXP_ALLOC', + 44: 'SQ_PERF_SEL_WAIT_SLEEP', + 45: 'SQ_PERF_SEL_WAIT_DELAY_ALU', + 46: 'SQ_PERF_SEL_WAIT_DEPCTR', + 47: 'SQ_PERF_SEL_WAIT_OTHER', + 48: 'SQ_PERF_SEL_INSTS_ALL', + 49: 'SQ_PERF_SEL_INSTS_BRANCH', + 50: 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', + 51: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', + 52: 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', + 53: 'SQ_PERF_SEL_INSTS_EXP_GDS', + 54: 'SQ_PERF_SEL_INSTS_GDS', + 55: 'SQ_PERF_SEL_INSTS_EXP', + 56: 'SQ_PERF_SEL_INSTS_FLAT', + 57: 'SQ_PERF_SEL_INSTS_LDS', + 58: 'SQ_PERF_SEL_INSTS_SALU', + 59: 'SQ_PERF_SEL_INSTS_SMEM', + 60: 'SQ_PERF_SEL_INSTS_SMEM_NORM', + 61: 'SQ_PERF_SEL_INSTS_SENDMSG', + 62: 'SQ_PERF_SEL_INSTS_VALU', + 63: 'SQ_PERF_SEL_INSTS_VALU_TRANS32', + 64: 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', + 65: 'SQ_PERF_SEL_INSTS_TEX', + 66: 'SQ_PERF_SEL_INSTS_TEX_LOAD', + 67: 'SQ_PERF_SEL_INSTS_TEX_STORE', + 68: 'SQ_PERF_SEL_INSTS_DELAY_ALU', + 69: 'SQ_PERF_SEL_INSTS_INTERNAL', + 70: 'SQ_PERF_SEL_INSTS_WAVE32', + 71: 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', + 72: 'SQ_PERF_SEL_INSTS_WAVE32_LDS', + 73: 'SQ_PERF_SEL_INSTS_WAVE32_VALU', + 74: 'SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS', + 75: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', + 76: 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', + 77: 'SQ_PERF_SEL_INSTS_WAVE32_TEX', + 78: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', + 79: 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', + 80: 'SQ_PERF_SEL_ITEM_CYCLES_VALU', + 81: 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', + 82: 'SQ_PERF_SEL_WAVE32_INSTS', + 83: 'SQ_PERF_SEL_WAVE64_INSTS', + 84: 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', + 85: 'SQ_PERF_SEL_WAVE64_HALF_SKIP', + 86: 'SQ_PERF_SEL_INST_LEVEL_EXP', + 87: 'SQ_PERF_SEL_INST_LEVEL_GDS', + 88: 'SQ_PERF_SEL_INST_LEVEL_LDS', + 89: 'SQ_PERF_SEL_INST_LEVEL_SMEM', + 90: 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', + 91: 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', + 92: 'SQ_PERF_SEL_IFETCH_REQS', + 93: 'SQ_PERF_SEL_IFETCH_LEVEL', + 94: 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', + 95: 'SQ_PERF_SEL_VALU_SGATHER_STALL', + 96: 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', + 97: 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', + 98: 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', + 99: 'SQ_PERF_SEL_SALU_SGATHER_STALL', + 100: 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', + 101: 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', + 102: 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', + 103: 'SQ_PERF_SEL_INST_CYCLES_VALU', + 104: 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', + 105: 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', + 106: 'SQ_PERF_SEL_INST_CYCLES_VMEM', + 107: 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', + 108: 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', + 109: 'SQ_PERF_SEL_INST_CYCLES_LDS', + 110: 'SQ_PERF_SEL_INST_CYCLES_TEX', + 111: 'SQ_PERF_SEL_INST_CYCLES_FLAT', + 112: 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', + 113: 'SQ_PERF_SEL_INST_CYCLES_EXP', + 114: 'SQ_PERF_SEL_INST_CYCLES_GDS', + 115: 'SQ_PERF_SEL_VALU_STARVE', + 116: 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', + 117: 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', + 118: 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 119: 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', + 120: 'SQ_PERF_SEL_VMEM_BUS_STALL', + 121: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', + 122: 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', + 123: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', + 124: 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', + 125: 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', + 126: 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', + 127: 'SQ_PERF_SEL_SALU_PIPE_STALL', + 128: 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', + 129: 'SQ_PERF_SEL_MSG_BUS_BUSY', + 130: 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', + 131: 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', + 132: 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', + 133: 'SQ_PERF_SEL_EXP_BUS0_BUSY', + 134: 'SQ_PERF_SEL_EXP_BUS1_BUSY', + 135: 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', + 136: 'SQ_PERF_SEL_USER0', + 137: 'SQ_PERF_SEL_USER1', + 138: 'SQ_PERF_SEL_USER2', + 139: 'SQ_PERF_SEL_USER3', + 140: 'SQ_PERF_SEL_USER4', + 141: 'SQ_PERF_SEL_USER5', + 142: 'SQ_PERF_SEL_USER6', + 143: 'SQ_PERF_SEL_USER7', + 144: 'SQ_PERF_SEL_USER8', + 145: 'SQ_PERF_SEL_USER9', + 146: 'SQ_PERF_SEL_USER10', + 147: 'SQ_PERF_SEL_USER11', + 148: 'SQ_PERF_SEL_USER12', + 149: 'SQ_PERF_SEL_USER13', + 150: 'SQ_PERF_SEL_USER14', + 151: 'SQ_PERF_SEL_USER15', + 152: 'SQ_PERF_SEL_USER_LEVEL0', + 153: 'SQ_PERF_SEL_USER_LEVEL1', + 154: 'SQ_PERF_SEL_USER_LEVEL2', + 155: 'SQ_PERF_SEL_USER_LEVEL3', + 156: 'SQ_PERF_SEL_USER_LEVEL4', + 157: 'SQ_PERF_SEL_USER_LEVEL5', + 158: 'SQ_PERF_SEL_USER_LEVEL6', + 159: 'SQ_PERF_SEL_USER_LEVEL7', + 160: 'SQ_PERF_SEL_USER_LEVEL8', + 161: 'SQ_PERF_SEL_USER_LEVEL9', + 162: 'SQ_PERF_SEL_USER_LEVEL10', + 163: 'SQ_PERF_SEL_USER_LEVEL11', + 164: 'SQ_PERF_SEL_USER_LEVEL12', + 165: 'SQ_PERF_SEL_USER_LEVEL13', + 166: 'SQ_PERF_SEL_USER_LEVEL14', + 167: 'SQ_PERF_SEL_USER_LEVEL15', + 168: 'SQ_PERF_SEL_VALU_RETURN_SDST', + 169: 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', + 170: 'SQ_PERF_SEL_INSTS_VALU_TRANS', + 171: 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', + 172: 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', + 173: 'SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD', + 174: 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', + 175: 'SQ_PERF_SEL_INSTS_VALU_VINTERP', + 176: 'SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP', + 177: 'SQ_PERF_SEL_OVERFLOW_PREV', + 178: 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', + 179: 'SQ_PERF_SEL_INSTS_VALU_1_PASS', + 180: 'SQ_PERF_SEL_INSTS_VALU_2_PASS', + 181: 'SQ_PERF_SEL_INSTS_VALU_4_PASS', + 182: 'SQ_PERF_SEL_INSTS_VALU_DP', + 183: 'SQ_PERF_SEL_SP_CONST_CYCLES', + 184: 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', + 185: 'SQ_PERF_SEL_ITEMS_VALU', + 186: 'SQ_PERF_SEL_ITEMS_MAX_VALU', + 187: 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', + 188: 'SQ_PERF_SEL_DUMMY_END', + 255: 'SQ_PERF_SEL_DUMMY_LAST', + 256: 'SQC_PERF_SEL_LDS_BANK_CONFLICT', + 257: 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', + 258: 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', + 259: 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', + 260: 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', + 261: 'SQC_PERF_SEL_LDS_IDX_ACTIVE', + 262: 'SQC_PERF_SEL_LDS_ADDR_STALL', + 263: 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', + 264: 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', + 265: 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', + 266: 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', + 267: 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', + 268: 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 269: 'SQC_PERF_SEL_ICACHE_REQ', + 270: 'SQC_PERF_SEL_ICACHE_HITS', + 271: 'SQC_PERF_SEL_ICACHE_MISSES', + 272: 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', + 273: 'SQC_PERF_SEL_ICACHE_INVAL_INST', + 274: 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 275: 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 276: 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 277: 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', + 278: 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 279: 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 280: 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 281: 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 282: 'SQC_PERF_SEL_TC_REQ', + 283: 'SQC_PERF_SEL_TC_INST_REQ', + 284: 'SQC_PERF_SEL_TC_DATA_READ_REQ', + 285: 'SQC_PERF_SEL_TC_STALL', + 286: 'SQC_PERF_SEL_TC_STARVE', + 287: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 288: 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 289: 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 290: 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 291: 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 292: 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 293: 'SQC_PERF_SEL_DCACHE_REQ', + 294: 'SQC_PERF_SEL_DCACHE_HITS', + 295: 'SQC_PERF_SEL_DCACHE_MISSES', + 296: 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', + 297: 'SQC_PERF_SEL_DCACHE_INVAL_INST', + 298: 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 299: 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 300: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 301: 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 302: 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 303: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 304: 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 305: 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 306: 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 307: 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 308: 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 309: 'SQC_PERF_SEL_DCACHE_REQ_READ_8', + 310: 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 311: 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 312: 'SQC_PERF_SEL_SQ_DCACHE_REQS', + 313: 'SQC_PERF_SEL_DCACHE_FLAT_REQ', + 314: 'SQC_PERF_SEL_TD_VGPR_BUSY', + 315: 'SQC_PERF_SEL_LDS_VGPR_BUSY', + 316: 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', + 317: 'SQC_PERF_SEL_ICACHE_GCR', + 318: 'SQC_PERF_SEL_ICACHE_GCR_HITS', + 319: 'SQC_PERF_SEL_DCACHE_GCR', + 320: 'SQC_PERF_SEL_DCACHE_GCR_HITS', + 321: 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', + 322: 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', + 323: 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', + 324: 'SQC_PERF_SEL_DUMMY_LAST', + 448: 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', + 449: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', + 450: 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', + 451: 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', + 452: 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', + 453: 'SP_PERF_SEL_SRC_CACHE_HIT_B0', + 454: 'SP_PERF_SEL_SRC_CACHE_HIT_B1', + 455: 'SP_PERF_SEL_SRC_CACHE_HIT_B2', + 456: 'SP_PERF_SEL_SRC_CACHE_HIT_B3', + 457: 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', + 458: 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', + 459: 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', + 460: 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', + 461: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', + 462: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', + 463: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', + 464: 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', + 465: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', + 466: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', + 467: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', + 468: 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', + 469: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', + 470: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', + 471: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', + 472: 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', + 473: 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', + 474: 'SP_PERF_SEL_VALU_OPERAND', + 475: 'SP_PERF_SEL_VALU_VGPR_OPERAND', + 476: 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', + 477: 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', + 478: 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', + 479: 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', + 480: 'SP_PERF_SEL_VALU_STALL', + 481: 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', + 482: 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', + 483: 'SP_PERF_SEL_VALU_STALL_VDST_FWD', + 484: 'SP_PERF_SEL_VALU_STALL_SDST_FWD', + 485: 'SP_PERF_SEL_VALU_STALL_DST_STALL', + 486: 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', + 487: 'SP_PERF_SEL_VGPR_VMEM_RD', + 488: 'SP_PERF_SEL_VGPR_EXP_RD', + 489: 'SP_PERF_SEL_VGPR_SPI_WR', + 490: 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', + 491: 'SP_PERF_SEL_VGPR_WR', + 492: 'SP_PERF_SEL_VGPR_RD', + 493: 'SP_PERF_SEL_DUMMY_LAST', + 511: 'SQ_PERF_SEL_NONE2', +} +SQ_PERF_SEL_NONE = 0 +SQ_PERF_SEL_ACCUM_PREV = 1 +SQ_PERF_SEL_CYCLES = 2 +SQ_PERF_SEL_BUSY_CYCLES = 3 +SQ_PERF_SEL_WAVES = 4 +SQ_PERF_SEL_WAVES_32 = 5 +SQ_PERF_SEL_WAVES_64 = 6 +SQ_PERF_SEL_LEVEL_WAVES = 7 +SQ_PERF_SEL_ITEMS = 8 +SQ_PERF_SEL_WAVE32_ITEMS = 9 +SQ_PERF_SEL_WAVE64_ITEMS = 10 +SQ_PERF_SEL_PS_QUADS = 11 +SQ_PERF_SEL_EVENTS = 12 +SQ_PERF_SEL_WAVES_EQ_32 = 13 +SQ_PERF_SEL_WAVES_EQ_64 = 14 +SQ_PERF_SEL_WAVES_LT_64 = 15 +SQ_PERF_SEL_WAVES_LT_48 = 16 +SQ_PERF_SEL_WAVES_LT_32 = 17 +SQ_PERF_SEL_WAVES_LT_16 = 18 +SQ_PERF_SEL_WAVES_RESTORED = 19 +SQ_PERF_SEL_WAVES_SAVED = 20 +SQ_PERF_SEL_MSG = 21 +SQ_PERF_SEL_MSG_INTERRUPT = 22 +SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 23 +SQ_PERF_SEL_WAVE_CYCLES = 24 +SQ_PERF_SEL_WAVE_READY = 25 +SQ_PERF_SEL_WAIT_INST_ANY = 26 +SQ_PERF_SEL_WAIT_INST_VALU = 27 +SQ_PERF_SEL_WAIT_INST_SCA = 28 +SQ_PERF_SEL_WAIT_INST_LDS = 29 +SQ_PERF_SEL_WAIT_INST_TEX = 30 +SQ_PERF_SEL_WAIT_INST_FLAT = 31 +SQ_PERF_SEL_WAIT_INST_VMEM = 32 +SQ_PERF_SEL_WAIT_INST_EXP_GDS = 33 +SQ_PERF_SEL_WAIT_INST_BR_MSG = 34 +SQ_PERF_SEL_WAIT_ANY = 35 +SQ_PERF_SEL_WAIT_CNT_ANY = 36 +SQ_PERF_SEL_WAIT_CNT_VMVS = 37 +SQ_PERF_SEL_WAIT_CNT_LGKM = 38 +SQ_PERF_SEL_WAIT_CNT_EXP = 39 +SQ_PERF_SEL_WAIT_TTRACE = 40 +SQ_PERF_SEL_WAIT_IFETCH = 41 +SQ_PERF_SEL_WAIT_BARRIER = 42 +SQ_PERF_SEL_WAIT_EXP_ALLOC = 43 +SQ_PERF_SEL_WAIT_SLEEP = 44 +SQ_PERF_SEL_WAIT_DELAY_ALU = 45 +SQ_PERF_SEL_WAIT_DEPCTR = 46 +SQ_PERF_SEL_WAIT_OTHER = 47 +SQ_PERF_SEL_INSTS_ALL = 48 +SQ_PERF_SEL_INSTS_BRANCH = 49 +SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 50 +SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 51 +SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 52 +SQ_PERF_SEL_INSTS_EXP_GDS = 53 +SQ_PERF_SEL_INSTS_GDS = 54 +SQ_PERF_SEL_INSTS_EXP = 55 +SQ_PERF_SEL_INSTS_FLAT = 56 +SQ_PERF_SEL_INSTS_LDS = 57 +SQ_PERF_SEL_INSTS_SALU = 58 +SQ_PERF_SEL_INSTS_SMEM = 59 +SQ_PERF_SEL_INSTS_SMEM_NORM = 60 +SQ_PERF_SEL_INSTS_SENDMSG = 61 +SQ_PERF_SEL_INSTS_VALU = 62 +SQ_PERF_SEL_INSTS_VALU_TRANS32 = 63 +SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 64 +SQ_PERF_SEL_INSTS_TEX = 65 +SQ_PERF_SEL_INSTS_TEX_LOAD = 66 +SQ_PERF_SEL_INSTS_TEX_STORE = 67 +SQ_PERF_SEL_INSTS_DELAY_ALU = 68 +SQ_PERF_SEL_INSTS_INTERNAL = 69 +SQ_PERF_SEL_INSTS_WAVE32 = 70 +SQ_PERF_SEL_INSTS_WAVE32_FLAT = 71 +SQ_PERF_SEL_INSTS_WAVE32_LDS = 72 +SQ_PERF_SEL_INSTS_WAVE32_VALU = 73 +SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS = 74 +SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 75 +SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 76 +SQ_PERF_SEL_INSTS_WAVE32_TEX = 77 +SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 78 +SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 79 +SQ_PERF_SEL_ITEM_CYCLES_VALU = 80 +SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 81 +SQ_PERF_SEL_WAVE32_INSTS = 82 +SQ_PERF_SEL_WAVE64_INSTS = 83 +SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 84 +SQ_PERF_SEL_WAVE64_HALF_SKIP = 85 +SQ_PERF_SEL_INST_LEVEL_EXP = 86 +SQ_PERF_SEL_INST_LEVEL_GDS = 87 +SQ_PERF_SEL_INST_LEVEL_LDS = 88 +SQ_PERF_SEL_INST_LEVEL_SMEM = 89 +SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 90 +SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 91 +SQ_PERF_SEL_IFETCH_REQS = 92 +SQ_PERF_SEL_IFETCH_LEVEL = 93 +SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 94 +SQ_PERF_SEL_VALU_SGATHER_STALL = 95 +SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 96 +SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 97 +SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 98 +SQ_PERF_SEL_SALU_SGATHER_STALL = 99 +SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 100 +SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 101 +SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 102 +SQ_PERF_SEL_INST_CYCLES_VALU = 103 +SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 104 +SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 105 +SQ_PERF_SEL_INST_CYCLES_VMEM = 106 +SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 107 +SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 108 +SQ_PERF_SEL_INST_CYCLES_LDS = 109 +SQ_PERF_SEL_INST_CYCLES_TEX = 110 +SQ_PERF_SEL_INST_CYCLES_FLAT = 111 +SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 112 +SQ_PERF_SEL_INST_CYCLES_EXP = 113 +SQ_PERF_SEL_INST_CYCLES_GDS = 114 +SQ_PERF_SEL_VALU_STARVE = 115 +SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 116 +SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 117 +SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 118 +SQ_PERF_SEL_VMEM_BUS_ACTIVE = 119 +SQ_PERF_SEL_VMEM_BUS_STALL = 120 +SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 121 +SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 122 +SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 123 +SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 124 +SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 125 +SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 126 +SQ_PERF_SEL_SALU_PIPE_STALL = 127 +SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 128 +SQ_PERF_SEL_MSG_BUS_BUSY = 129 +SQ_PERF_SEL_EXP_REQ_BUS_STALL = 130 +SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 131 +SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 132 +SQ_PERF_SEL_EXP_BUS0_BUSY = 133 +SQ_PERF_SEL_EXP_BUS1_BUSY = 134 +SQ_PERF_SEL_INST_CACHE_REQ_STALL = 135 +SQ_PERF_SEL_USER0 = 136 +SQ_PERF_SEL_USER1 = 137 +SQ_PERF_SEL_USER2 = 138 +SQ_PERF_SEL_USER3 = 139 +SQ_PERF_SEL_USER4 = 140 +SQ_PERF_SEL_USER5 = 141 +SQ_PERF_SEL_USER6 = 142 +SQ_PERF_SEL_USER7 = 143 +SQ_PERF_SEL_USER8 = 144 +SQ_PERF_SEL_USER9 = 145 +SQ_PERF_SEL_USER10 = 146 +SQ_PERF_SEL_USER11 = 147 +SQ_PERF_SEL_USER12 = 148 +SQ_PERF_SEL_USER13 = 149 +SQ_PERF_SEL_USER14 = 150 +SQ_PERF_SEL_USER15 = 151 +SQ_PERF_SEL_USER_LEVEL0 = 152 +SQ_PERF_SEL_USER_LEVEL1 = 153 +SQ_PERF_SEL_USER_LEVEL2 = 154 +SQ_PERF_SEL_USER_LEVEL3 = 155 +SQ_PERF_SEL_USER_LEVEL4 = 156 +SQ_PERF_SEL_USER_LEVEL5 = 157 +SQ_PERF_SEL_USER_LEVEL6 = 158 +SQ_PERF_SEL_USER_LEVEL7 = 159 +SQ_PERF_SEL_USER_LEVEL8 = 160 +SQ_PERF_SEL_USER_LEVEL9 = 161 +SQ_PERF_SEL_USER_LEVEL10 = 162 +SQ_PERF_SEL_USER_LEVEL11 = 163 +SQ_PERF_SEL_USER_LEVEL12 = 164 +SQ_PERF_SEL_USER_LEVEL13 = 165 +SQ_PERF_SEL_USER_LEVEL14 = 166 +SQ_PERF_SEL_USER_LEVEL15 = 167 +SQ_PERF_SEL_VALU_RETURN_SDST = 168 +SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 169 +SQ_PERF_SEL_INSTS_VALU_TRANS = 170 +SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 171 +SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 172 +SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD = 173 +SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 174 +SQ_PERF_SEL_INSTS_VALU_VINTERP = 175 +SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP = 176 +SQ_PERF_SEL_OVERFLOW_PREV = 177 +SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 178 +SQ_PERF_SEL_INSTS_VALU_1_PASS = 179 +SQ_PERF_SEL_INSTS_VALU_2_PASS = 180 +SQ_PERF_SEL_INSTS_VALU_4_PASS = 181 +SQ_PERF_SEL_INSTS_VALU_DP = 182 +SQ_PERF_SEL_SP_CONST_CYCLES = 183 +SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 184 +SQ_PERF_SEL_ITEMS_VALU = 185 +SQ_PERF_SEL_ITEMS_MAX_VALU = 186 +SQ_PERF_SEL_ITEM_CYCLES_VMEM = 187 +SQ_PERF_SEL_DUMMY_END = 188 +SQ_PERF_SEL_DUMMY_LAST = 255 +SQC_PERF_SEL_LDS_BANK_CONFLICT = 256 +SQC_PERF_SEL_LDS_ADDR_CONFLICT = 257 +SQC_PERF_SEL_LDS_UNALIGNED_STALL = 258 +SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 259 +SQC_PERF_SEL_LDS_ATOMIC_RETURN = 260 +SQC_PERF_SEL_LDS_IDX_ACTIVE = 261 +SQC_PERF_SEL_LDS_ADDR_STALL = 262 +SQC_PERF_SEL_LDS_ADDR_ACTIVE = 263 +SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 264 +SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 265 +SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 266 +SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 267 +SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 268 +SQC_PERF_SEL_ICACHE_REQ = 269 +SQC_PERF_SEL_ICACHE_HITS = 270 +SQC_PERF_SEL_ICACHE_MISSES = 271 +SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 272 +SQC_PERF_SEL_ICACHE_INVAL_INST = 273 +SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 274 +SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 275 +SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 276 +SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 277 +SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 278 +SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 279 +SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 280 +SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 281 +SQC_PERF_SEL_TC_REQ = 282 +SQC_PERF_SEL_TC_INST_REQ = 283 +SQC_PERF_SEL_TC_DATA_READ_REQ = 284 +SQC_PERF_SEL_TC_STALL = 285 +SQC_PERF_SEL_TC_STARVE = 286 +SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 287 +SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 288 +SQC_PERF_SEL_ICACHE_CACHE_STALLED = 289 +SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 290 +SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 291 +SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 292 +SQC_PERF_SEL_DCACHE_REQ = 293 +SQC_PERF_SEL_DCACHE_HITS = 294 +SQC_PERF_SEL_DCACHE_MISSES = 295 +SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 296 +SQC_PERF_SEL_DCACHE_INVAL_INST = 297 +SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 298 +SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 299 +SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 300 +SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 301 +SQC_PERF_SEL_DCACHE_CACHE_STALLED = 302 +SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 303 +SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 304 +SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 305 +SQC_PERF_SEL_DCACHE_REQ_READ_1 = 306 +SQC_PERF_SEL_DCACHE_REQ_READ_2 = 307 +SQC_PERF_SEL_DCACHE_REQ_READ_4 = 308 +SQC_PERF_SEL_DCACHE_REQ_READ_8 = 309 +SQC_PERF_SEL_DCACHE_REQ_READ_16 = 310 +SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 311 +SQC_PERF_SEL_SQ_DCACHE_REQS = 312 +SQC_PERF_SEL_DCACHE_FLAT_REQ = 313 +SQC_PERF_SEL_TD_VGPR_BUSY = 314 +SQC_PERF_SEL_LDS_VGPR_BUSY = 315 +SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 316 +SQC_PERF_SEL_ICACHE_GCR = 317 +SQC_PERF_SEL_ICACHE_GCR_HITS = 318 +SQC_PERF_SEL_DCACHE_GCR = 319 +SQC_PERF_SEL_DCACHE_GCR_HITS = 320 +SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 321 +SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 322 +SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 323 +SQC_PERF_SEL_DUMMY_LAST = 324 +SP_PERF_SEL_DST_BUF_ALLOC_STALL = 448 +SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 449 +SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 450 +SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 451 +SP_PERF_SEL_DST_BUF_ODD_DIRTY = 452 +SP_PERF_SEL_SRC_CACHE_HIT_B0 = 453 +SP_PERF_SEL_SRC_CACHE_HIT_B1 = 454 +SP_PERF_SEL_SRC_CACHE_HIT_B2 = 455 +SP_PERF_SEL_SRC_CACHE_HIT_B3 = 456 +SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 457 +SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 458 +SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 459 +SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 460 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 461 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 462 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 463 +SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 464 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 465 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 466 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 467 +SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 468 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 469 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 470 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 471 +SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 472 +SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 473 +SP_PERF_SEL_VALU_OPERAND = 474 +SP_PERF_SEL_VALU_VGPR_OPERAND = 475 +SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 476 +SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 477 +SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 478 +SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 479 +SP_PERF_SEL_VALU_STALL = 480 +SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 481 +SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 482 +SP_PERF_SEL_VALU_STALL_VDST_FWD = 483 +SP_PERF_SEL_VALU_STALL_SDST_FWD = 484 +SP_PERF_SEL_VALU_STALL_DST_STALL = 485 +SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 486 +SP_PERF_SEL_VGPR_VMEM_RD = 487 +SP_PERF_SEL_VGPR_EXP_RD = 488 +SP_PERF_SEL_VGPR_SPI_WR = 489 +SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 490 +SP_PERF_SEL_VGPR_WR = 491 +SP_PERF_SEL_VGPR_RD = 492 +SP_PERF_SEL_DUMMY_LAST = 493 +SQ_PERF_SEL_NONE2 = 511 +SQ_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_ROUND_MODE' +SQ_ROUND_MODE__enumvalues = { + 0: 'SQ_ROUND_NEAREST_EVEN', + 1: 'SQ_ROUND_PLUS_INFINITY', + 2: 'SQ_ROUND_MINUS_INFINITY', + 3: 'SQ_ROUND_TO_ZERO', +} +SQ_ROUND_NEAREST_EVEN = 0 +SQ_ROUND_PLUS_INFINITY = 1 +SQ_ROUND_MINUS_INFINITY = 2 +SQ_ROUND_TO_ZERO = 3 +SQ_ROUND_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_BUF_TYPE' +SQ_RSRC_BUF_TYPE__enumvalues = { + 0: 'SQ_RSRC_BUF', + 1: 'SQ_RSRC_BUF_RSVD_1', + 2: 'SQ_RSRC_BUF_RSVD_2', + 3: 'SQ_RSRC_BUF_RSVD_3', +} +SQ_RSRC_BUF = 0 +SQ_RSRC_BUF_RSVD_1 = 1 +SQ_RSRC_BUF_RSVD_2 = 2 +SQ_RSRC_BUF_RSVD_3 = 3 +SQ_RSRC_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_FLAT_TYPE' +SQ_RSRC_FLAT_TYPE__enumvalues = { + 0: 'SQ_RSRC_FLAT_RSVD_0', + 1: 'SQ_RSRC_FLAT', + 2: 'SQ_RSRC_FLAT_RSVD_2', + 3: 'SQ_RSRC_FLAT_RSVD_3', +} +SQ_RSRC_FLAT_RSVD_0 = 0 +SQ_RSRC_FLAT = 1 +SQ_RSRC_FLAT_RSVD_2 = 2 +SQ_RSRC_FLAT_RSVD_3 = 3 +SQ_RSRC_FLAT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_RSRC_IMG_TYPE' +SQ_RSRC_IMG_TYPE__enumvalues = { + 0: 'SQ_RSRC_IMG_RSVD_0', + 1: 'SQ_RSRC_IMG_RSVD_1', + 2: 'SQ_RSRC_IMG_RSVD_2', + 3: 'SQ_RSRC_IMG_RSVD_3', + 4: 'SQ_RSRC_IMG_RSVD_4', + 5: 'SQ_RSRC_IMG_RSVD_5', + 6: 'SQ_RSRC_IMG_RSVD_6', + 7: 'SQ_RSRC_IMG_RSVD_7', + 8: 'SQ_RSRC_IMG_1D', + 9: 'SQ_RSRC_IMG_2D', + 10: 'SQ_RSRC_IMG_3D', + 11: 'SQ_RSRC_IMG_CUBE', + 12: 'SQ_RSRC_IMG_1D_ARRAY', + 13: 'SQ_RSRC_IMG_2D_ARRAY', + 14: 'SQ_RSRC_IMG_2D_MSAA', + 15: 'SQ_RSRC_IMG_2D_MSAA_ARRAY', +} +SQ_RSRC_IMG_RSVD_0 = 0 +SQ_RSRC_IMG_RSVD_1 = 1 +SQ_RSRC_IMG_RSVD_2 = 2 +SQ_RSRC_IMG_RSVD_3 = 3 +SQ_RSRC_IMG_RSVD_4 = 4 +SQ_RSRC_IMG_RSVD_5 = 5 +SQ_RSRC_IMG_RSVD_6 = 6 +SQ_RSRC_IMG_RSVD_7 = 7 +SQ_RSRC_IMG_1D = 8 +SQ_RSRC_IMG_2D = 9 +SQ_RSRC_IMG_3D = 10 +SQ_RSRC_IMG_CUBE = 11 +SQ_RSRC_IMG_1D_ARRAY = 12 +SQ_RSRC_IMG_2D_ARRAY = 13 +SQ_RSRC_IMG_2D_MSAA = 14 +SQ_RSRC_IMG_2D_MSAA_ARRAY = 15 +SQ_RSRC_IMG_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_SEL_XYZW01' +SQ_SEL_XYZW01__enumvalues = { + 0: 'SQ_SEL_0', + 1: 'SQ_SEL_1', + 2: 'SQ_SEL_N_BC_1', + 3: 'SQ_SEL_RESERVED_1', + 4: 'SQ_SEL_X', + 5: 'SQ_SEL_Y', + 6: 'SQ_SEL_Z', + 7: 'SQ_SEL_W', +} +SQ_SEL_0 = 0 +SQ_SEL_1 = 1 +SQ_SEL_N_BC_1 = 2 +SQ_SEL_RESERVED_1 = 3 +SQ_SEL_X = 4 +SQ_SEL_Y = 5 +SQ_SEL_Z = 6 +SQ_SEL_W = 7 +SQ_SEL_XYZW01 = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_ANISO_RATIO' +SQ_TEX_ANISO_RATIO__enumvalues = { + 0: 'SQ_TEX_ANISO_RATIO_1', + 1: 'SQ_TEX_ANISO_RATIO_2', + 2: 'SQ_TEX_ANISO_RATIO_4', + 3: 'SQ_TEX_ANISO_RATIO_8', + 4: 'SQ_TEX_ANISO_RATIO_16', +} +SQ_TEX_ANISO_RATIO_1 = 0 +SQ_TEX_ANISO_RATIO_2 = 1 +SQ_TEX_ANISO_RATIO_4 = 2 +SQ_TEX_ANISO_RATIO_8 = 3 +SQ_TEX_ANISO_RATIO_16 = 4 +SQ_TEX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_BORDER_COLOR' +SQ_TEX_BORDER_COLOR__enumvalues = { + 0: 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 1: 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 2: 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 3: 'SQ_TEX_BORDER_COLOR_REGISTER', +} +SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0 +SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 1 +SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 2 +SQ_TEX_BORDER_COLOR_REGISTER = 3 +SQ_TEX_BORDER_COLOR = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_CLAMP' +SQ_TEX_CLAMP__enumvalues = { + 0: 'SQ_TEX_WRAP', + 1: 'SQ_TEX_MIRROR', + 2: 'SQ_TEX_CLAMP_LAST_TEXEL', + 3: 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 4: 'SQ_TEX_CLAMP_HALF_BORDER', + 5: 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', + 6: 'SQ_TEX_CLAMP_BORDER', + 7: 'SQ_TEX_MIRROR_ONCE_BORDER', +} +SQ_TEX_WRAP = 0 +SQ_TEX_MIRROR = 1 +SQ_TEX_CLAMP_LAST_TEXEL = 2 +SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3 +SQ_TEX_CLAMP_HALF_BORDER = 4 +SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5 +SQ_TEX_CLAMP_BORDER = 6 +SQ_TEX_MIRROR_ONCE_BORDER = 7 +SQ_TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_DEPTH_COMPARE' +SQ_TEX_DEPTH_COMPARE__enumvalues = { + 0: 'SQ_TEX_DEPTH_COMPARE_NEVER', + 1: 'SQ_TEX_DEPTH_COMPARE_LESS', + 2: 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 3: 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', + 4: 'SQ_TEX_DEPTH_COMPARE_GREATER', + 5: 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', + 6: 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', + 7: 'SQ_TEX_DEPTH_COMPARE_ALWAYS', +} +SQ_TEX_DEPTH_COMPARE_NEVER = 0 +SQ_TEX_DEPTH_COMPARE_LESS = 1 +SQ_TEX_DEPTH_COMPARE_EQUAL = 2 +SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 3 +SQ_TEX_DEPTH_COMPARE_GREATER = 4 +SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 5 +SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 6 +SQ_TEX_DEPTH_COMPARE_ALWAYS = 7 +SQ_TEX_DEPTH_COMPARE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_MIP_FILTER' +SQ_TEX_MIP_FILTER__enumvalues = { + 0: 'SQ_TEX_MIP_FILTER_NONE', + 1: 'SQ_TEX_MIP_FILTER_POINT', + 2: 'SQ_TEX_MIP_FILTER_LINEAR', + 3: 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', +} +SQ_TEX_MIP_FILTER_NONE = 0 +SQ_TEX_MIP_FILTER_POINT = 1 +SQ_TEX_MIP_FILTER_LINEAR = 2 +SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 3 +SQ_TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_XY_FILTER' +SQ_TEX_XY_FILTER__enumvalues = { + 0: 'SQ_TEX_XY_FILTER_POINT', + 1: 'SQ_TEX_XY_FILTER_BILINEAR', + 2: 'SQ_TEX_XY_FILTER_ANISO_POINT', + 3: 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', +} +SQ_TEX_XY_FILTER_POINT = 0 +SQ_TEX_XY_FILTER_BILINEAR = 1 +SQ_TEX_XY_FILTER_ANISO_POINT = 2 +SQ_TEX_XY_FILTER_ANISO_BILINEAR = 3 +SQ_TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TEX_Z_FILTER' +SQ_TEX_Z_FILTER__enumvalues = { + 0: 'SQ_TEX_Z_FILTER_NONE', + 1: 'SQ_TEX_Z_FILTER_POINT', + 2: 'SQ_TEX_Z_FILTER_LINEAR', +} +SQ_TEX_Z_FILTER_NONE = 0 +SQ_TEX_Z_FILTER_POINT = 1 +SQ_TEX_Z_FILTER_LINEAR = 2 +SQ_TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_MODE' +SQ_TT_MODE__enumvalues = { + 0: 'SQ_TT_MODE_OFF', + 1: 'SQ_TT_MODE_ON', + 2: 'SQ_TT_MODE_GLOBAL', + 3: 'SQ_TT_MODE_DETAIL', +} +SQ_TT_MODE_OFF = 0 +SQ_TT_MODE_ON = 1 +SQ_TT_MODE_GLOBAL = 2 +SQ_TT_MODE_DETAIL = 3 +SQ_TT_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_RT_FREQ' +SQ_TT_RT_FREQ__enumvalues = { + 0: 'SQ_TT_RT_FREQ_NEVER', + 1: 'SQ_TT_RT_FREQ_1024_CLK', + 2: 'SQ_TT_RT_FREQ_4096_CLK', +} +SQ_TT_RT_FREQ_NEVER = 0 +SQ_TT_RT_FREQ_1024_CLK = 1 +SQ_TT_RT_FREQ_4096_CLK = 2 +SQ_TT_RT_FREQ = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE' +SQ_TT_TOKEN_MASK_INST_EXCLUDE__enumvalues = { + 1: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT', + 2: 'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT', +} +SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT = 1 +SQ_TT_INST_EXCLUDE_EXPGNT234_BIT = 2 +SQ_TT_TOKEN_MASK_INST_EXCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT', + 1: 'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT', +} +SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT = 0 +SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT = 1 +SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_EXCLUDE' +SQ_TT_TOKEN_MASK_REG_EXCLUDE__enumvalues = { + 1: 'SQ_TT_REG_EXCLUDE_USER_DATA_BIT', + 2: 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT', + 4: 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT', +} +SQ_TT_REG_EXCLUDE_USER_DATA_BIT = 1 +SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT = 2 +SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT = 4 +SQ_TT_TOKEN_MASK_REG_EXCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT', + 1: 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT', + 2: 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT', +} +SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT = 0 +SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT = 1 +SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT = 2 +SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE' +SQ_TT_TOKEN_MASK_REG_INCLUDE__enumvalues = { + 1: 'SQ_TT_TOKEN_MASK_SQDEC_BIT', + 2: 'SQ_TT_TOKEN_MASK_SHDEC_BIT', + 4: 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', + 8: 'SQ_TT_TOKEN_MASK_COMP_BIT', + 16: 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', + 32: 'SQ_TT_TOKEN_MASK_CONFIG_BIT', + 64: 'SQ_TT_TOKEN_MASK_ALL_BIT', + 128: 'SQ_TT_TOKEN_MASK_RSVD_BIT', +} +SQ_TT_TOKEN_MASK_SQDEC_BIT = 1 +SQ_TT_TOKEN_MASK_SHDEC_BIT = 2 +SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 4 +SQ_TT_TOKEN_MASK_COMP_BIT = 8 +SQ_TT_TOKEN_MASK_CONTEXT_BIT = 16 +SQ_TT_TOKEN_MASK_CONFIG_BIT = 32 +SQ_TT_TOKEN_MASK_ALL_BIT = 64 +SQ_TT_TOKEN_MASK_RSVD_BIT = 128 +SQ_TT_TOKEN_MASK_REG_INCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', + 1: 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', + 2: 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', + 3: 'SQ_TT_TOKEN_MASK_COMP_SHIFT', + 4: 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', + 5: 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', + 6: 'SQ_TT_TOKEN_MASK_ALL_SHIFT', + 7: 'SQ_TT_TOKEN_MASK_RSVD_SHIFT', +} +SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0 +SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 1 +SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 2 +SQ_TT_TOKEN_MASK_COMP_SHIFT = 3 +SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 4 +SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 5 +SQ_TT_TOKEN_MASK_ALL_SHIFT = 6 +SQ_TT_TOKEN_MASK_RSVD_SHIFT = 7 +SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT' +SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', + 1: 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', + 2: 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', + 3: 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', + 4: 'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT', + 5: 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', + 6: 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', + 7: 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', + 8: 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', + 9: 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', + 10: 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', + 11: 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', +} +SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0 +SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 1 +SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 2 +SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 3 +SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT = 4 +SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 5 +SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 6 +SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 7 +SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 8 +SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 9 +SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 10 +SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 11 +SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_UTIL_TIMER' +SQ_TT_UTIL_TIMER__enumvalues = { + 0: 'SQ_TT_UTIL_TIMER_100_CLK', + 1: 'SQ_TT_UTIL_TIMER_250_CLK', +} +SQ_TT_UTIL_TIMER_100_CLK = 0 +SQ_TT_UTIL_TIMER_250_CLK = 1 +SQ_TT_UTIL_TIMER = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_WAVESTART_MODE' +SQ_TT_WAVESTART_MODE__enumvalues = { + 0: 'SQ_TT_WAVESTART_MODE_SHORT', + 1: 'SQ_TT_WAVESTART_MODE_ALLOC', + 2: 'SQ_TT_WAVESTART_MODE_PBB_ID', +} +SQ_TT_WAVESTART_MODE_SHORT = 0 +SQ_TT_WAVESTART_MODE_ALLOC = 1 +SQ_TT_WAVESTART_MODE_PBB_ID = 2 +SQ_TT_WAVESTART_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_WTYPE_INCLUDE' +SQ_TT_WTYPE_INCLUDE__enumvalues = { + 1: 'SQ_TT_WTYPE_INCLUDE_PS_BIT', + 2: 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT', + 4: 'SQ_TT_WTYPE_INCLUDE_GS_BIT', + 8: 'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT', + 16: 'SQ_TT_WTYPE_INCLUDE_HS_BIT', + 32: 'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT', + 64: 'SQ_TT_WTYPE_INCLUDE_CS_BIT', +} +SQ_TT_WTYPE_INCLUDE_PS_BIT = 1 +SQ_TT_WTYPE_INCLUDE_RSVD0_BIT = 2 +SQ_TT_WTYPE_INCLUDE_GS_BIT = 4 +SQ_TT_WTYPE_INCLUDE_RSVD1_BIT = 8 +SQ_TT_WTYPE_INCLUDE_HS_BIT = 16 +SQ_TT_WTYPE_INCLUDE_RSVD2_BIT = 32 +SQ_TT_WTYPE_INCLUDE_CS_BIT = 64 +SQ_TT_WTYPE_INCLUDE = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_TT_WTYPE_INCLUDE_SHIFT' +SQ_TT_WTYPE_INCLUDE_SHIFT__enumvalues = { + 0: 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', + 1: 'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT', + 2: 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', + 3: 'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT', + 4: 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', + 5: 'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT', + 6: 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', +} +SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0 +SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT = 1 +SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 2 +SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT = 3 +SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 4 +SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT = 5 +SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 6 +SQ_TT_WTYPE_INCLUDE_SHIFT = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WATCH_MODES' +SQ_WATCH_MODES__enumvalues = { + 0: 'SQ_WATCH_MODE_READ', + 1: 'SQ_WATCH_MODE_NONREAD', + 2: 'SQ_WATCH_MODE_ATOMIC', + 3: 'SQ_WATCH_MODE_ALL', +} +SQ_WATCH_MODE_READ = 0 +SQ_WATCH_MODE_NONREAD = 1 +SQ_WATCH_MODE_ATOMIC = 2 +SQ_WATCH_MODE_ALL = 3 +SQ_WATCH_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_FWD_PROG_INTERVAL' +SQ_WAVE_FWD_PROG_INTERVAL__enumvalues = { + 0: 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', + 1: 'SQ_WAVE_FWD_PROG_INTERVAL_256', + 2: 'SQ_WAVE_FWD_PROG_INTERVAL_1024', + 3: 'SQ_WAVE_FWD_PROG_INTERVAL_4096', +} +SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0 +SQ_WAVE_FWD_PROG_INTERVAL_256 = 1 +SQ_WAVE_FWD_PROG_INTERVAL_1024 = 2 +SQ_WAVE_FWD_PROG_INTERVAL_4096 = 3 +SQ_WAVE_FWD_PROG_INTERVAL = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_IB_ECC_ST' +SQ_WAVE_IB_ECC_ST__enumvalues = { + 0: 'SQ_WAVE_IB_ECC_CLEAN', + 1: 'SQ_WAVE_IB_ECC_ERR_CONTINUE', + 2: 'SQ_WAVE_IB_ECC_ERR_HALT', + 3: 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', +} +SQ_WAVE_IB_ECC_CLEAN = 0 +SQ_WAVE_IB_ECC_ERR_CONTINUE = 1 +SQ_WAVE_IB_ECC_ERR_HALT = 2 +SQ_WAVE_IB_ECC_WITH_ERR_MSG = 3 +SQ_WAVE_IB_ECC_ST = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_SCHED_MODES' +SQ_WAVE_SCHED_MODES__enumvalues = { + 0: 'SQ_WAVE_SCHED_MODE_NORMAL', + 1: 'SQ_WAVE_SCHED_MODE_EXPERT', + 2: 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', +} +SQ_WAVE_SCHED_MODE_NORMAL = 0 +SQ_WAVE_SCHED_MODE_EXPERT = 1 +SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 2 +SQ_WAVE_SCHED_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'SQ_WAVE_TYPE' +SQ_WAVE_TYPE__enumvalues = { + 0: 'SQ_WAVE_TYPE_PS', + 1: 'SQ_WAVE_TYPE_RSVD0', + 2: 'SQ_WAVE_TYPE_GS', + 3: 'SQ_WAVE_TYPE_RSVD1', + 4: 'SQ_WAVE_TYPE_HS', + 5: 'SQ_WAVE_TYPE_RSVD2', + 6: 'SQ_WAVE_TYPE_CS', + 7: 'SQ_WAVE_TYPE_PS1', + 8: 'SQ_WAVE_TYPE_PS2', + 9: 'SQ_WAVE_TYPE_PS3', +} +SQ_WAVE_TYPE_PS = 0 +SQ_WAVE_TYPE_RSVD0 = 1 +SQ_WAVE_TYPE_GS = 2 +SQ_WAVE_TYPE_RSVD1 = 3 +SQ_WAVE_TYPE_HS = 4 +SQ_WAVE_TYPE_RSVD2 = 5 +SQ_WAVE_TYPE_CS = 6 +SQ_WAVE_TYPE_PS1 = 7 +SQ_WAVE_TYPE_PS2 = 8 +SQ_WAVE_TYPE_PS3 = 9 +SQ_WAVE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CSCNTL_TYPE' +CSCNTL_TYPE__enumvalues = { + 0: 'CSCNTL_TYPE_TG', + 1: 'CSCNTL_TYPE_STATE', + 2: 'CSCNTL_TYPE_EVENT', + 3: 'CSCNTL_TYPE_PRIVATE', +} +CSCNTL_TYPE_TG = 0 +CSCNTL_TYPE_STATE = 1 +CSCNTL_TYPE_EVENT = 2 +CSCNTL_TYPE_PRIVATE = 3 +CSCNTL_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'CSDATA_TYPE' +CSDATA_TYPE__enumvalues = { + 0: 'CSDATA_TYPE_TG', + 1: 'CSDATA_TYPE_STATE', + 2: 'CSDATA_TYPE_EVENT', + 3: 'CSDATA_TYPE_PRIVATE', +} +CSDATA_TYPE_TG = 0 +CSDATA_TYPE_STATE = 1 +CSDATA_TYPE_EVENT = 2 +CSDATA_TYPE_PRIVATE = 3 +CSDATA_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'GE1_PERFCOUNT_SELECT' +GE1_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge1_assembler_busy', + 1: 'ge1_assembler_stalled', + 2: 'ge1_dma_busy', + 3: 'ge1_dma_lat_bin_0', + 4: 'ge1_dma_lat_bin_1', + 5: 'ge1_dma_lat_bin_2', + 6: 'ge1_dma_lat_bin_3', + 7: 'ge1_dma_lat_bin_4', + 8: 'ge1_dma_lat_bin_5', + 9: 'ge1_dma_lat_bin_6', + 10: 'ge1_dma_lat_bin_7', + 11: 'ge1_dma_return_cl0', + 12: 'ge1_dma_return_cl1', + 13: 'ge1_dma_utcl1_consecutive_retry_event', + 14: 'ge1_dma_utcl1_request_event', + 15: 'ge1_dma_utcl1_retry_event', + 16: 'ge1_dma_utcl1_stall_event', + 17: 'ge1_dma_utcl1_stall_utcl2_event', + 18: 'ge1_dma_utcl1_translation_hit_event', + 19: 'ge1_dma_utcl1_translation_miss_event', + 20: 'ge1_assembler_dma_starved', + 21: 'ge1_rbiu_di_fifo_stalled_p0', + 22: 'ge1_rbiu_di_fifo_starved_p0', + 23: 'ge1_rbiu_dr_fifo_stalled_p0', + 24: 'ge1_rbiu_dr_fifo_starved_p0', + 25: 'ge1_sclk_reg_vld', + 26: 'ge1_stat_busy', + 27: 'ge1_stat_no_dma_busy', + 28: 'ge1_pipe0_to_pipe1', + 29: 'ge1_pipe1_to_pipe0', + 30: 'ge1_dma_return_size_cl0', + 31: 'ge1_dma_return_size_cl1', + 32: 'ge1_small_draws_one_instance', + 33: 'ge1_sclk_input_vld', + 34: 'ge1_prim_group_limit_hit', + 35: 'ge1_unopt_multi_instance_draws', + 36: 'ge1_rbiu_di_fifo_stalled_p1', + 37: 'ge1_rbiu_di_fifo_starved_p1', + 38: 'ge1_rbiu_dr_fifo_stalled_p1', + 39: 'ge1_rbiu_dr_fifo_starved_p1', +} +ge1_assembler_busy = 0 +ge1_assembler_stalled = 1 +ge1_dma_busy = 2 +ge1_dma_lat_bin_0 = 3 +ge1_dma_lat_bin_1 = 4 +ge1_dma_lat_bin_2 = 5 +ge1_dma_lat_bin_3 = 6 +ge1_dma_lat_bin_4 = 7 +ge1_dma_lat_bin_5 = 8 +ge1_dma_lat_bin_6 = 9 +ge1_dma_lat_bin_7 = 10 +ge1_dma_return_cl0 = 11 +ge1_dma_return_cl1 = 12 +ge1_dma_utcl1_consecutive_retry_event = 13 +ge1_dma_utcl1_request_event = 14 +ge1_dma_utcl1_retry_event = 15 +ge1_dma_utcl1_stall_event = 16 +ge1_dma_utcl1_stall_utcl2_event = 17 +ge1_dma_utcl1_translation_hit_event = 18 +ge1_dma_utcl1_translation_miss_event = 19 +ge1_assembler_dma_starved = 20 +ge1_rbiu_di_fifo_stalled_p0 = 21 +ge1_rbiu_di_fifo_starved_p0 = 22 +ge1_rbiu_dr_fifo_stalled_p0 = 23 +ge1_rbiu_dr_fifo_starved_p0 = 24 +ge1_sclk_reg_vld = 25 +ge1_stat_busy = 26 +ge1_stat_no_dma_busy = 27 +ge1_pipe0_to_pipe1 = 28 +ge1_pipe1_to_pipe0 = 29 +ge1_dma_return_size_cl0 = 30 +ge1_dma_return_size_cl1 = 31 +ge1_small_draws_one_instance = 32 +ge1_sclk_input_vld = 33 +ge1_prim_group_limit_hit = 34 +ge1_unopt_multi_instance_draws = 35 +ge1_rbiu_di_fifo_stalled_p1 = 36 +ge1_rbiu_di_fifo_starved_p1 = 37 +ge1_rbiu_dr_fifo_stalled_p1 = 38 +ge1_rbiu_dr_fifo_starved_p1 = 39 +GE1_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'GE2_DIST_PERFCOUNT_SELECT' +GE2_DIST_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge_dist_hs_done', + 1: 'ge_dist_hs_done_latency_se0', + 2: 'ge_dist_hs_done_latency_se1', + 3: 'ge_dist_hs_done_latency_se2', + 4: 'ge_dist_hs_done_latency_se3', + 5: 'ge_dist_hs_done_latency_se4', + 6: 'ge_dist_hs_done_latency_se5', + 7: 'ge_dist_hs_done_latency_se6', + 8: 'ge_dist_hs_done_latency_se7', + 9: 'ge_dist_inside_tf_bin_0', + 10: 'ge_dist_inside_tf_bin_1', + 11: 'ge_dist_inside_tf_bin_2', + 12: 'ge_dist_inside_tf_bin_3', + 13: 'ge_dist_inside_tf_bin_4', + 14: 'ge_dist_inside_tf_bin_5', + 15: 'ge_dist_inside_tf_bin_6', + 16: 'ge_dist_inside_tf_bin_7', + 17: 'ge_dist_inside_tf_bin_8', + 18: 'ge_dist_null_patch', + 19: 'ge_dist_sclk_core_vld', + 20: 'ge_dist_sclk_wd_te11_vld', + 21: 'ge_dist_tfreq_lat_bin_0', + 22: 'ge_dist_tfreq_lat_bin_1', + 23: 'ge_dist_tfreq_lat_bin_2', + 24: 'ge_dist_tfreq_lat_bin_3', + 25: 'ge_dist_tfreq_lat_bin_4', + 26: 'ge_dist_tfreq_lat_bin_5', + 27: 'ge_dist_tfreq_lat_bin_6', + 28: 'ge_dist_tfreq_lat_bin_7', + 29: 'ge_dist_tfreq_utcl1_consecutive_retry_event', + 30: 'ge_dist_tfreq_utcl1_request_event', + 31: 'ge_dist_tfreq_utcl1_retry_event', + 32: 'ge_dist_tfreq_utcl1_stall_event', + 33: 'ge_dist_tfreq_utcl1_stall_utcl2_event', + 34: 'ge_dist_tfreq_utcl1_translation_hit_event', + 35: 'ge_dist_tfreq_utcl1_translation_miss_event', + 36: 'ge_dist_vs_pc_stall', + 37: 'ge_dist_pc_feorder_fifo_full', + 38: 'ge_dist_pc_ge_manager_busy', + 39: 'ge_dist_pc_req_stall_se0', + 40: 'ge_dist_pc_req_stall_se1', + 41: 'ge_dist_pc_req_stall_se2', + 42: 'ge_dist_pc_req_stall_se3', + 43: 'ge_dist_pc_req_stall_se4', + 44: 'ge_dist_pc_req_stall_se5', + 45: 'ge_dist_pc_req_stall_se6', + 46: 'ge_dist_pc_req_stall_se7', + 47: 'ge_dist_pc_space_zero', + 48: 'ge_dist_sclk_input_vld', + 49: 'ge_dist_reserved', + 50: 'ge_dist_wd_te11_busy', + 51: 'ge_dist_te11_starved', + 52: 'ge_dist_switch_mode_stall', + 53: 'ge_all_tf_eq', + 54: 'ge_all_tf2', + 55: 'ge_all_tf3', + 56: 'ge_all_tf4', + 57: 'ge_all_tf5', + 58: 'ge_all_tf6', + 59: 'ge_se0_te11_starved_on_hs_done', + 60: 'ge_se1_te11_starved_on_hs_done', + 61: 'ge_se2_te11_starved_on_hs_done', + 62: 'ge_se3_te11_starved_on_hs_done', + 63: 'ge_se4_te11_starved_on_hs_done', + 64: 'ge_se5_te11_starved_on_hs_done', + 65: 'ge_se6_te11_starved_on_hs_done', + 66: 'ge_se7_te11_starved_on_hs_done', + 67: 'ge_dist_op_fifo_full_starve', + 68: 'ge_dist_hs_done_se0', + 69: 'ge_dist_hs_done_se1', + 70: 'ge_dist_hs_done_se2', + 71: 'ge_dist_hs_done_se3', + 72: 'ge_dist_hs_done_se4', + 73: 'ge_dist_hs_done_se5', + 74: 'ge_dist_hs_done_se6', + 75: 'ge_dist_hs_done_se7', + 76: 'ge_dist_hs_done_latency', + 77: 'ge_dist_distributer_busy', + 78: 'ge_tf_ret_data_stalling_hs_done', + 79: 'ge_num_of_no_dist_patches', + 80: 'ge_num_of_donut_dist_patches', + 81: 'ge_num_of_patch_dist_patches', + 82: 'ge_num_of_se_switches_due_to_patch_accum', + 83: 'ge_num_of_se_switches_due_to_donut', + 84: 'ge_num_of_se_switches_due_to_trap', + 85: 'ge_num_of_hs_alloc_events', + 86: 'ge_agm_gcr_req', + 87: 'ge_agm_gcr_tag_stall', + 88: 'ge_agm_gcr_crd_stall', + 89: 'ge_agm_gcr_stall', + 90: 'ge_agm_gcr_latency', + 91: 'ge_distclk_vld', +} +ge_dist_hs_done = 0 +ge_dist_hs_done_latency_se0 = 1 +ge_dist_hs_done_latency_se1 = 2 +ge_dist_hs_done_latency_se2 = 3 +ge_dist_hs_done_latency_se3 = 4 +ge_dist_hs_done_latency_se4 = 5 +ge_dist_hs_done_latency_se5 = 6 +ge_dist_hs_done_latency_se6 = 7 +ge_dist_hs_done_latency_se7 = 8 +ge_dist_inside_tf_bin_0 = 9 +ge_dist_inside_tf_bin_1 = 10 +ge_dist_inside_tf_bin_2 = 11 +ge_dist_inside_tf_bin_3 = 12 +ge_dist_inside_tf_bin_4 = 13 +ge_dist_inside_tf_bin_5 = 14 +ge_dist_inside_tf_bin_6 = 15 +ge_dist_inside_tf_bin_7 = 16 +ge_dist_inside_tf_bin_8 = 17 +ge_dist_null_patch = 18 +ge_dist_sclk_core_vld = 19 +ge_dist_sclk_wd_te11_vld = 20 +ge_dist_tfreq_lat_bin_0 = 21 +ge_dist_tfreq_lat_bin_1 = 22 +ge_dist_tfreq_lat_bin_2 = 23 +ge_dist_tfreq_lat_bin_3 = 24 +ge_dist_tfreq_lat_bin_4 = 25 +ge_dist_tfreq_lat_bin_5 = 26 +ge_dist_tfreq_lat_bin_6 = 27 +ge_dist_tfreq_lat_bin_7 = 28 +ge_dist_tfreq_utcl1_consecutive_retry_event = 29 +ge_dist_tfreq_utcl1_request_event = 30 +ge_dist_tfreq_utcl1_retry_event = 31 +ge_dist_tfreq_utcl1_stall_event = 32 +ge_dist_tfreq_utcl1_stall_utcl2_event = 33 +ge_dist_tfreq_utcl1_translation_hit_event = 34 +ge_dist_tfreq_utcl1_translation_miss_event = 35 +ge_dist_vs_pc_stall = 36 +ge_dist_pc_feorder_fifo_full = 37 +ge_dist_pc_ge_manager_busy = 38 +ge_dist_pc_req_stall_se0 = 39 +ge_dist_pc_req_stall_se1 = 40 +ge_dist_pc_req_stall_se2 = 41 +ge_dist_pc_req_stall_se3 = 42 +ge_dist_pc_req_stall_se4 = 43 +ge_dist_pc_req_stall_se5 = 44 +ge_dist_pc_req_stall_se6 = 45 +ge_dist_pc_req_stall_se7 = 46 +ge_dist_pc_space_zero = 47 +ge_dist_sclk_input_vld = 48 +ge_dist_reserved = 49 +ge_dist_wd_te11_busy = 50 +ge_dist_te11_starved = 51 +ge_dist_switch_mode_stall = 52 +ge_all_tf_eq = 53 +ge_all_tf2 = 54 +ge_all_tf3 = 55 +ge_all_tf4 = 56 +ge_all_tf5 = 57 +ge_all_tf6 = 58 +ge_se0_te11_starved_on_hs_done = 59 +ge_se1_te11_starved_on_hs_done = 60 +ge_se2_te11_starved_on_hs_done = 61 +ge_se3_te11_starved_on_hs_done = 62 +ge_se4_te11_starved_on_hs_done = 63 +ge_se5_te11_starved_on_hs_done = 64 +ge_se6_te11_starved_on_hs_done = 65 +ge_se7_te11_starved_on_hs_done = 66 +ge_dist_op_fifo_full_starve = 67 +ge_dist_hs_done_se0 = 68 +ge_dist_hs_done_se1 = 69 +ge_dist_hs_done_se2 = 70 +ge_dist_hs_done_se3 = 71 +ge_dist_hs_done_se4 = 72 +ge_dist_hs_done_se5 = 73 +ge_dist_hs_done_se6 = 74 +ge_dist_hs_done_se7 = 75 +ge_dist_hs_done_latency = 76 +ge_dist_distributer_busy = 77 +ge_tf_ret_data_stalling_hs_done = 78 +ge_num_of_no_dist_patches = 79 +ge_num_of_donut_dist_patches = 80 +ge_num_of_patch_dist_patches = 81 +ge_num_of_se_switches_due_to_patch_accum = 82 +ge_num_of_se_switches_due_to_donut = 83 +ge_num_of_se_switches_due_to_trap = 84 +ge_num_of_hs_alloc_events = 85 +ge_agm_gcr_req = 86 +ge_agm_gcr_tag_stall = 87 +ge_agm_gcr_crd_stall = 88 +ge_agm_gcr_stall = 89 +ge_agm_gcr_latency = 90 +ge_distclk_vld = 91 +GE2_DIST_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'GE2_SE_PERFCOUNT_SELECT' +GE2_SE_PERFCOUNT_SELECT__enumvalues = { + 0: 'ge_se_ds_prims', + 1: 'ge_se_es_thread_groups', + 2: 'ge_se_esvert_stalled_gsprim', + 3: 'ge_se_hs_tfm_stall', + 4: 'ge_se_hs_tgs_active_high_water_mark', + 5: 'ge_se_hs_thread_groups', + 6: 'ge_se_reused_es_indices', + 7: 'ge_se_sclk_ngg_vld', + 8: 'ge_se_sclk_te11_vld', + 9: 'ge_se_spi_esvert_eov', + 10: 'ge_se_spi_esvert_stalled', + 11: 'ge_se_spi_esvert_starved_busy', + 12: 'ge_se_spi_esvert_valid', + 13: 'ge_se_spi_gsprim_cont', + 14: 'ge_se_spi_gsprim_eov', + 15: 'ge_se_spi_gsprim_stalled', + 16: 'ge_se_spi_gsprim_starved_busy', + 17: 'ge_se_spi_gsprim_valid', + 18: 'ge_se_spi_gssubgrp_is_event', + 19: 'ge_se_spi_gssubgrp_send', + 20: 'ge_se_spi_hsvert_eov', + 21: 'ge_se_spi_hsvert_stalled', + 22: 'ge_se_spi_hsvert_starved_busy', + 23: 'ge_se_spi_hsvert_valid', + 24: 'ge_se_spi_hswave_is_event', + 25: 'ge_se_spi_hswave_send', + 26: 'ge_se_spi_lsvert_eov', + 27: 'ge_se_spi_lsvert_stalled', + 28: 'ge_se_spi_lsvert_starved_busy', + 29: 'ge_se_spi_lsvert_valid', + 30: 'ge_se_spi_hsvert_fifo_full_stall', + 31: 'ge_se_spi_tgrp_fifo_stall', + 32: 'ge_spi_hsgrp_spi_stall', + 33: 'ge_se_spi_gssubgrp_event_window_active', + 34: 'ge_se_hs_input_stall', + 35: 'ge_se_sending_vert_or_prim', + 36: 'ge_se_sclk_input_vld', + 37: 'ge_spi_lswave_fifo_full_stall', + 38: 'ge_spi_hswave_fifo_full_stall', + 39: 'ge_hs_tif_stall', + 40: 'ge_csb_spi_bp', + 41: 'ge_ngg_starving_for_pc_grant', + 42: 'ge_pa0_csb_eop', + 43: 'ge_pa1_csb_eop', + 44: 'ge_ngg_starved_idle', + 45: 'ge_gsprim_send', + 46: 'ge_esvert_send', + 47: 'ge_ngg_starved_after_work', + 48: 'ge_ngg_subgrp_fifo_stall', + 49: 'ge_ngg_ord_id_req_stall', + 50: 'ge_ngg_indx_bus_stall', + 51: 'ge_hs_stall_tfmm_fifo_full', + 52: 'ge_gs_issue_rtr_stalled', + 53: 'ge_gsprim_stalled_esvert', + 54: 'ge_gsthread_stalled', + 55: 'ge_te11_stall_prim_funnel', + 56: 'ge_te11_stall_vert_funnel', + 57: 'ge_ngg_attr_grp_alloc', + 58: 'ge_ngg_attr_discard_alloc', + 59: 'ge_ngg_pc_space_not_avail', + 60: 'ge_ngg_agm_req_stall', + 61: 'ge_ngg_spi_esvert_partial_eov', + 62: 'ge_ngg_spi_gsprim_partial_eov', + 63: 'ge_spi_gsgrp_valid', + 64: 'ge_ngg_attr_grp_latency', + 65: 'ge_ngg_reuse_prim_limit_hit', + 66: 'ge_ngg_reuse_vert_limit_hit', + 67: 'ge_te11_con_stall', + 68: 'ge_te11_compactor_starved', + 69: 'ge_ngg_stall_tess_off_tess_on', + 70: 'ge_ngg_stall_tess_on_tess_off', +} +ge_se_ds_prims = 0 +ge_se_es_thread_groups = 1 +ge_se_esvert_stalled_gsprim = 2 +ge_se_hs_tfm_stall = 3 +ge_se_hs_tgs_active_high_water_mark = 4 +ge_se_hs_thread_groups = 5 +ge_se_reused_es_indices = 6 +ge_se_sclk_ngg_vld = 7 +ge_se_sclk_te11_vld = 8 +ge_se_spi_esvert_eov = 9 +ge_se_spi_esvert_stalled = 10 +ge_se_spi_esvert_starved_busy = 11 +ge_se_spi_esvert_valid = 12 +ge_se_spi_gsprim_cont = 13 +ge_se_spi_gsprim_eov = 14 +ge_se_spi_gsprim_stalled = 15 +ge_se_spi_gsprim_starved_busy = 16 +ge_se_spi_gsprim_valid = 17 +ge_se_spi_gssubgrp_is_event = 18 +ge_se_spi_gssubgrp_send = 19 +ge_se_spi_hsvert_eov = 20 +ge_se_spi_hsvert_stalled = 21 +ge_se_spi_hsvert_starved_busy = 22 +ge_se_spi_hsvert_valid = 23 +ge_se_spi_hswave_is_event = 24 +ge_se_spi_hswave_send = 25 +ge_se_spi_lsvert_eov = 26 +ge_se_spi_lsvert_stalled = 27 +ge_se_spi_lsvert_starved_busy = 28 +ge_se_spi_lsvert_valid = 29 +ge_se_spi_hsvert_fifo_full_stall = 30 +ge_se_spi_tgrp_fifo_stall = 31 +ge_spi_hsgrp_spi_stall = 32 +ge_se_spi_gssubgrp_event_window_active = 33 +ge_se_hs_input_stall = 34 +ge_se_sending_vert_or_prim = 35 +ge_se_sclk_input_vld = 36 +ge_spi_lswave_fifo_full_stall = 37 +ge_spi_hswave_fifo_full_stall = 38 +ge_hs_tif_stall = 39 +ge_csb_spi_bp = 40 +ge_ngg_starving_for_pc_grant = 41 +ge_pa0_csb_eop = 42 +ge_pa1_csb_eop = 43 +ge_ngg_starved_idle = 44 +ge_gsprim_send = 45 +ge_esvert_send = 46 +ge_ngg_starved_after_work = 47 +ge_ngg_subgrp_fifo_stall = 48 +ge_ngg_ord_id_req_stall = 49 +ge_ngg_indx_bus_stall = 50 +ge_hs_stall_tfmm_fifo_full = 51 +ge_gs_issue_rtr_stalled = 52 +ge_gsprim_stalled_esvert = 53 +ge_gsthread_stalled = 54 +ge_te11_stall_prim_funnel = 55 +ge_te11_stall_vert_funnel = 56 +ge_ngg_attr_grp_alloc = 57 +ge_ngg_attr_discard_alloc = 58 +ge_ngg_pc_space_not_avail = 59 +ge_ngg_agm_req_stall = 60 +ge_ngg_spi_esvert_partial_eov = 61 +ge_ngg_spi_gsprim_partial_eov = 62 +ge_spi_gsgrp_valid = 63 +ge_ngg_attr_grp_latency = 64 +ge_ngg_reuse_prim_limit_hit = 65 +ge_ngg_reuse_vert_limit_hit = 66 +ge_te11_con_stall = 67 +ge_te11_compactor_starved = 68 +ge_ngg_stall_tess_off_tess_on = 69 +ge_ngg_stall_tess_on_tess_off = 70 +GE2_SE_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DETECT_ONE' +VGT_DETECT_ONE__enumvalues = { + 0: 'ENABLE_TF1_OPT', + 1: 'DISABLE_TF1_OPT', +} +ENABLE_TF1_OPT = 0 +DISABLE_TF1_OPT = 1 +VGT_DETECT_ONE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DETECT_ZERO' +VGT_DETECT_ZERO__enumvalues = { + 0: 'ENABLE_TF0_OPT', + 1: 'DISABLE_TF0_OPT', +} +ENABLE_TF0_OPT = 0 +DISABLE_TF0_OPT = 1 +VGT_DETECT_ZERO = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DIST_MODE' +VGT_DIST_MODE__enumvalues = { + 0: 'NO_DIST', + 1: 'PATCHES', + 2: 'DONUTS', + 3: 'TRAPEZOIDS', +} +NO_DIST = 0 +PATCHES = 1 +DONUTS = 2 +TRAPEZOIDS = 3 +VGT_DIST_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_INDEX_SIZE' +VGT_DI_INDEX_SIZE__enumvalues = { + 0: 'DI_INDEX_SIZE_16_BIT', + 1: 'DI_INDEX_SIZE_32_BIT', + 2: 'DI_INDEX_SIZE_8_BIT', +} +DI_INDEX_SIZE_16_BIT = 0 +DI_INDEX_SIZE_32_BIT = 1 +DI_INDEX_SIZE_8_BIT = 2 +VGT_DI_INDEX_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_MAJOR_MODE_SELECT' +VGT_DI_MAJOR_MODE_SELECT__enumvalues = { + 0: 'DI_MAJOR_MODE_0', + 1: 'DI_MAJOR_MODE_1', +} +DI_MAJOR_MODE_0 = 0 +DI_MAJOR_MODE_1 = 1 +VGT_DI_MAJOR_MODE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_PRIM_TYPE' +VGT_DI_PRIM_TYPE__enumvalues = { + 0: 'DI_PT_NONE', + 1: 'DI_PT_POINTLIST', + 2: 'DI_PT_LINELIST', + 3: 'DI_PT_LINESTRIP', + 4: 'DI_PT_TRILIST', + 5: 'DI_PT_TRIFAN', + 6: 'DI_PT_TRISTRIP', + 7: 'DI_PT_2D_RECTANGLE', + 8: 'DI_PT_UNUSED_1', + 9: 'DI_PT_PATCH', + 10: 'DI_PT_LINELIST_ADJ', + 11: 'DI_PT_LINESTRIP_ADJ', + 12: 'DI_PT_TRILIST_ADJ', + 13: 'DI_PT_TRISTRIP_ADJ', + 14: 'DI_PT_UNUSED_3', + 15: 'DI_PT_UNUSED_4', + 16: 'DI_PT_UNUSED_5', + 17: 'DI_PT_RECTLIST', + 18: 'DI_PT_LINELOOP', + 19: 'DI_PT_QUADLIST', + 20: 'DI_PT_QUADSTRIP', + 21: 'DI_PT_POLYGON', +} +DI_PT_NONE = 0 +DI_PT_POINTLIST = 1 +DI_PT_LINELIST = 2 +DI_PT_LINESTRIP = 3 +DI_PT_TRILIST = 4 +DI_PT_TRIFAN = 5 +DI_PT_TRISTRIP = 6 +DI_PT_2D_RECTANGLE = 7 +DI_PT_UNUSED_1 = 8 +DI_PT_PATCH = 9 +DI_PT_LINELIST_ADJ = 10 +DI_PT_LINESTRIP_ADJ = 11 +DI_PT_TRILIST_ADJ = 12 +DI_PT_TRISTRIP_ADJ = 13 +DI_PT_UNUSED_3 = 14 +DI_PT_UNUSED_4 = 15 +DI_PT_UNUSED_5 = 16 +DI_PT_RECTLIST = 17 +DI_PT_LINELOOP = 18 +DI_PT_QUADLIST = 19 +DI_PT_QUADSTRIP = 20 +DI_PT_POLYGON = 21 +VGT_DI_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DI_SOURCE_SELECT' +VGT_DI_SOURCE_SELECT__enumvalues = { + 0: 'DI_SRC_SEL_DMA', + 1: 'DI_SRC_SEL_IMMEDIATE', + 2: 'DI_SRC_SEL_AUTO_INDEX', + 3: 'DI_SRC_SEL_RESERVED', +} +DI_SRC_SEL_DMA = 0 +DI_SRC_SEL_IMMEDIATE = 1 +DI_SRC_SEL_AUTO_INDEX = 2 +DI_SRC_SEL_RESERVED = 3 +VGT_DI_SOURCE_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_BUF_TYPE' +VGT_DMA_BUF_TYPE__enumvalues = { + 0: 'VGT_DMA_BUF_MEM', + 1: 'VGT_DMA_BUF_RING', + 2: 'VGT_DMA_BUF_SETUP', + 3: 'VGT_DMA_PTR_UPDATE', +} +VGT_DMA_BUF_MEM = 0 +VGT_DMA_BUF_RING = 1 +VGT_DMA_BUF_SETUP = 2 +VGT_DMA_PTR_UPDATE = 3 +VGT_DMA_BUF_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_DMA_SWAP_MODE' +VGT_DMA_SWAP_MODE__enumvalues = { + 0: 'VGT_DMA_SWAP_NONE', + 1: 'VGT_DMA_SWAP_16_BIT', + 2: 'VGT_DMA_SWAP_32_BIT', + 3: 'VGT_DMA_SWAP_WORD', +} +VGT_DMA_SWAP_NONE = 0 +VGT_DMA_SWAP_16_BIT = 1 +VGT_DMA_SWAP_32_BIT = 2 +VGT_DMA_SWAP_WORD = 3 +VGT_DMA_SWAP_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_EVENT_TYPE' +VGT_EVENT_TYPE__enumvalues = { + 0: 'Reserved_0x00', + 1: 'SAMPLE_STREAMOUTSTATS1', + 2: 'SAMPLE_STREAMOUTSTATS2', + 3: 'SAMPLE_STREAMOUTSTATS3', + 4: 'CACHE_FLUSH_TS', + 5: 'CONTEXT_DONE', + 6: 'CACHE_FLUSH', + 7: 'CS_PARTIAL_FLUSH', + 8: 'VGT_STREAMOUT_SYNC', + 9: 'Reserved_0x09', + 10: 'VGT_STREAMOUT_RESET', + 11: 'END_OF_PIPE_INCR_DE', + 12: 'END_OF_PIPE_IB_END', + 13: 'RST_PIX_CNT', + 14: 'BREAK_BATCH', + 15: 'VS_PARTIAL_FLUSH', + 16: 'PS_PARTIAL_FLUSH', + 17: 'FLUSH_HS_OUTPUT', + 18: 'FLUSH_DFSM', + 19: 'RESET_TO_LOWEST_VGT', + 20: 'CACHE_FLUSH_AND_INV_TS_EVENT', + 21: 'WAIT_SYNC', + 22: 'CACHE_FLUSH_AND_INV_EVENT', + 23: 'PERFCOUNTER_START', + 24: 'PERFCOUNTER_STOP', + 25: 'PIPELINESTAT_START', + 26: 'PIPELINESTAT_STOP', + 27: 'PERFCOUNTER_SAMPLE', + 28: 'FLUSH_ES_OUTPUT', + 29: 'BIN_CONF_OVERRIDE_CHECK', + 30: 'SAMPLE_PIPELINESTAT', + 31: 'SO_VGTSTREAMOUT_FLUSH', + 32: 'SAMPLE_STREAMOUTSTATS', + 33: 'RESET_VTX_CNT', + 34: 'BLOCK_CONTEXT_DONE', + 35: 'CS_CONTEXT_DONE', + 36: 'VGT_FLUSH', + 37: 'TGID_ROLLOVER', + 38: 'SQ_NON_EVENT', + 39: 'SC_SEND_DB_VPZ', + 40: 'BOTTOM_OF_PIPE_TS', + 41: 'FLUSH_SX_TS', + 42: 'DB_CACHE_FLUSH_AND_INV', + 43: 'FLUSH_AND_INV_DB_DATA_TS', + 44: 'FLUSH_AND_INV_DB_META', + 45: 'FLUSH_AND_INV_CB_DATA_TS', + 46: 'FLUSH_AND_INV_CB_META', + 47: 'CS_DONE', + 48: 'PS_DONE', + 49: 'FLUSH_AND_INV_CB_PIXEL_DATA', + 50: 'SX_CB_RAT_ACK_REQUEST', + 51: 'THREAD_TRACE_START', + 52: 'THREAD_TRACE_STOP', + 53: 'THREAD_TRACE_MARKER', + 54: 'THREAD_TRACE_DRAW', + 55: 'THREAD_TRACE_FINISH', + 56: 'PIXEL_PIPE_STAT_CONTROL', + 57: 'PIXEL_PIPE_STAT_DUMP', + 58: 'PIXEL_PIPE_STAT_RESET', + 59: 'CONTEXT_SUSPEND', + 60: 'OFFCHIP_HS_DEALLOC', + 61: 'ENABLE_NGG_PIPELINE', + 62: 'ENABLE_LEGACY_PIPELINE', + 63: 'DRAW_DONE', +} +Reserved_0x00 = 0 +SAMPLE_STREAMOUTSTATS1 = 1 +SAMPLE_STREAMOUTSTATS2 = 2 +SAMPLE_STREAMOUTSTATS3 = 3 +CACHE_FLUSH_TS = 4 +CONTEXT_DONE = 5 +CACHE_FLUSH = 6 +CS_PARTIAL_FLUSH = 7 +VGT_STREAMOUT_SYNC = 8 +Reserved_0x09 = 9 +VGT_STREAMOUT_RESET = 10 +END_OF_PIPE_INCR_DE = 11 +END_OF_PIPE_IB_END = 12 +RST_PIX_CNT = 13 +BREAK_BATCH = 14 +VS_PARTIAL_FLUSH = 15 +PS_PARTIAL_FLUSH = 16 +FLUSH_HS_OUTPUT = 17 +FLUSH_DFSM = 18 +RESET_TO_LOWEST_VGT = 19 +CACHE_FLUSH_AND_INV_TS_EVENT = 20 +WAIT_SYNC = 21 +CACHE_FLUSH_AND_INV_EVENT = 22 +PERFCOUNTER_START = 23 +PERFCOUNTER_STOP = 24 +PIPELINESTAT_START = 25 +PIPELINESTAT_STOP = 26 +PERFCOUNTER_SAMPLE = 27 +FLUSH_ES_OUTPUT = 28 +BIN_CONF_OVERRIDE_CHECK = 29 +SAMPLE_PIPELINESTAT = 30 +SO_VGTSTREAMOUT_FLUSH = 31 +SAMPLE_STREAMOUTSTATS = 32 +RESET_VTX_CNT = 33 +BLOCK_CONTEXT_DONE = 34 +CS_CONTEXT_DONE = 35 +VGT_FLUSH = 36 +TGID_ROLLOVER = 37 +SQ_NON_EVENT = 38 +SC_SEND_DB_VPZ = 39 +BOTTOM_OF_PIPE_TS = 40 +FLUSH_SX_TS = 41 +DB_CACHE_FLUSH_AND_INV = 42 +FLUSH_AND_INV_DB_DATA_TS = 43 +FLUSH_AND_INV_DB_META = 44 +FLUSH_AND_INV_CB_DATA_TS = 45 +FLUSH_AND_INV_CB_META = 46 +CS_DONE = 47 +PS_DONE = 48 +FLUSH_AND_INV_CB_PIXEL_DATA = 49 +SX_CB_RAT_ACK_REQUEST = 50 +THREAD_TRACE_START = 51 +THREAD_TRACE_STOP = 52 +THREAD_TRACE_MARKER = 53 +THREAD_TRACE_DRAW = 54 +THREAD_TRACE_FINISH = 55 +PIXEL_PIPE_STAT_CONTROL = 56 +PIXEL_PIPE_STAT_DUMP = 57 +PIXEL_PIPE_STAT_RESET = 58 +CONTEXT_SUSPEND = 59 +OFFCHIP_HS_DEALLOC = 60 +ENABLE_NGG_PIPELINE = 61 +ENABLE_LEGACY_PIPELINE = 62 +DRAW_DONE = 63 +VGT_EVENT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GROUP_CONV_SEL' +VGT_GROUP_CONV_SEL__enumvalues = { + 0: 'VGT_GRP_INDEX_16', + 1: 'VGT_GRP_INDEX_32', + 2: 'VGT_GRP_UINT_16', + 3: 'VGT_GRP_UINT_32', + 4: 'VGT_GRP_SINT_16', + 5: 'VGT_GRP_SINT_32', + 6: 'VGT_GRP_FLOAT_32', + 7: 'VGT_GRP_AUTO_PRIM', + 8: 'VGT_GRP_FIX_1_23_TO_FLOAT', +} +VGT_GRP_INDEX_16 = 0 +VGT_GRP_INDEX_32 = 1 +VGT_GRP_UINT_16 = 2 +VGT_GRP_UINT_32 = 3 +VGT_GRP_SINT_16 = 4 +VGT_GRP_SINT_32 = 5 +VGT_GRP_FLOAT_32 = 6 +VGT_GRP_AUTO_PRIM = 7 +VGT_GRP_FIX_1_23_TO_FLOAT = 8 +VGT_GROUP_CONV_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_MODE_TYPE' +VGT_GS_MODE_TYPE__enumvalues = { + 0: 'GS_OFF', + 1: 'GS_SCENARIO_A', + 2: 'GS_SCENARIO_B', + 3: 'GS_SCENARIO_G', + 4: 'GS_SCENARIO_C', + 5: 'SPRITE_EN', +} +GS_OFF = 0 +GS_SCENARIO_A = 1 +GS_SCENARIO_B = 2 +GS_SCENARIO_G = 3 +GS_SCENARIO_C = 4 +SPRITE_EN = 5 +VGT_GS_MODE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_GS_OUTPRIM_TYPE' +VGT_GS_OUTPRIM_TYPE__enumvalues = { + 0: 'POINTLIST', + 1: 'LINESTRIP', + 2: 'TRISTRIP', + 3: 'RECT_2D', + 4: 'RECTLIST', +} +POINTLIST = 0 +LINESTRIP = 1 +TRISTRIP = 2 +RECT_2D = 3 +RECTLIST = 4 +VGT_GS_OUTPRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_INDEX_TYPE_MODE' +VGT_INDEX_TYPE_MODE__enumvalues = { + 0: 'VGT_INDEX_16', + 1: 'VGT_INDEX_32', + 2: 'VGT_INDEX_8', +} +VGT_INDEX_16 = 0 +VGT_INDEX_32 = 1 +VGT_INDEX_8 = 2 +VGT_INDEX_TYPE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUTPATH_SELECT' +VGT_OUTPATH_SELECT__enumvalues = { + 0: 'VGT_OUTPATH_VTX_REUSE', + 1: 'VGT_OUTPATH_GS_BLOCK', + 2: 'VGT_OUTPATH_HS_BLOCK', + 3: 'VGT_OUTPATH_PRIM_GEN', + 4: 'VGT_OUTPATH_TE_PRIM_GEN', + 5: 'VGT_OUTPATH_TE_GS_BLOCK', + 6: 'VGT_OUTPATH_TE_OUTPUT', +} +VGT_OUTPATH_VTX_REUSE = 0 +VGT_OUTPATH_GS_BLOCK = 1 +VGT_OUTPATH_HS_BLOCK = 2 +VGT_OUTPATH_PRIM_GEN = 3 +VGT_OUTPATH_TE_PRIM_GEN = 4 +VGT_OUTPATH_TE_GS_BLOCK = 5 +VGT_OUTPATH_TE_OUTPUT = 6 +VGT_OUTPATH_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_OUT_PRIM_TYPE' +VGT_OUT_PRIM_TYPE__enumvalues = { + 0: 'VGT_OUT_POINT', + 1: 'VGT_OUT_LINE', + 2: 'VGT_OUT_TRI', + 3: 'VGT_OUT_RECT_V0', + 4: 'VGT_OUT_RECT_V1', + 5: 'VGT_OUT_RECT_V2', + 6: 'VGT_OUT_RECT_V3', + 7: 'VGT_OUT_2D_RECT', + 8: 'VGT_TE_QUAD', + 9: 'VGT_TE_PRIM_INDEX_LINE', + 10: 'VGT_TE_PRIM_INDEX_TRI', + 11: 'VGT_TE_PRIM_INDEX_QUAD', + 12: 'VGT_OUT_LINE_ADJ', + 13: 'VGT_OUT_TRI_ADJ', + 14: 'VGT_OUT_PATCH', +} +VGT_OUT_POINT = 0 +VGT_OUT_LINE = 1 +VGT_OUT_TRI = 2 +VGT_OUT_RECT_V0 = 3 +VGT_OUT_RECT_V1 = 4 +VGT_OUT_RECT_V2 = 5 +VGT_OUT_RECT_V3 = 6 +VGT_OUT_2D_RECT = 7 +VGT_TE_QUAD = 8 +VGT_TE_PRIM_INDEX_LINE = 9 +VGT_TE_PRIM_INDEX_TRI = 10 +VGT_TE_PRIM_INDEX_QUAD = 11 +VGT_OUT_LINE_ADJ = 12 +VGT_OUT_TRI_ADJ = 13 +VGT_OUT_PATCH = 14 +VGT_OUT_PRIM_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_RDREQ_POLICY' +VGT_RDREQ_POLICY__enumvalues = { + 0: 'VGT_POLICY_LRU', + 1: 'VGT_POLICY_STREAM', + 2: 'VGT_POLICY_BYPASS', +} +VGT_POLICY_LRU = 0 +VGT_POLICY_STREAM = 1 +VGT_POLICY_BYPASS = 2 +VGT_RDREQ_POLICY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_ES_EN' +VGT_STAGES_ES_EN__enumvalues = { + 0: 'ES_STAGE_OFF', + 1: 'ES_STAGE_DS', + 2: 'ES_STAGE_REAL', + 3: 'RESERVED_ES', +} +ES_STAGE_OFF = 0 +ES_STAGE_DS = 1 +ES_STAGE_REAL = 2 +RESERVED_ES = 3 +VGT_STAGES_ES_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_GS_EN' +VGT_STAGES_GS_EN__enumvalues = { + 0: 'GS_STAGE_OFF', + 1: 'GS_STAGE_ON', +} +GS_STAGE_OFF = 0 +GS_STAGE_ON = 1 +VGT_STAGES_GS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_HS_EN' +VGT_STAGES_HS_EN__enumvalues = { + 0: 'HS_STAGE_OFF', + 1: 'HS_STAGE_ON', +} +HS_STAGE_OFF = 0 +HS_STAGE_ON = 1 +VGT_STAGES_HS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_LS_EN' +VGT_STAGES_LS_EN__enumvalues = { + 0: 'LS_STAGE_OFF', + 1: 'LS_STAGE_ON', + 2: 'CS_STAGE_ON', + 3: 'RESERVED_LS', +} +LS_STAGE_OFF = 0 +LS_STAGE_ON = 1 +CS_STAGE_ON = 2 +RESERVED_LS = 3 +VGT_STAGES_LS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_STAGES_VS_EN' +VGT_STAGES_VS_EN__enumvalues = { + 0: 'VS_STAGE_REAL', + 1: 'VS_STAGE_DS', + 2: 'VS_STAGE_COPY_SHADER', + 3: 'RESERVED_VS', +} +VS_STAGE_REAL = 0 +VS_STAGE_DS = 1 +VS_STAGE_COPY_SHADER = 2 +RESERVED_VS = 3 +VGT_STAGES_VS_EN = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_PARTITION' +VGT_TESS_PARTITION__enumvalues = { + 0: 'PART_INTEGER', + 1: 'PART_POW2', + 2: 'PART_FRAC_ODD', + 3: 'PART_FRAC_EVEN', +} +PART_INTEGER = 0 +PART_POW2 = 1 +PART_FRAC_ODD = 2 +PART_FRAC_EVEN = 3 +VGT_TESS_PARTITION = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TOPOLOGY' +VGT_TESS_TOPOLOGY__enumvalues = { + 0: 'OUTPUT_POINT', + 1: 'OUTPUT_LINE', + 2: 'OUTPUT_TRIANGLE_CW', + 3: 'OUTPUT_TRIANGLE_CCW', +} +OUTPUT_POINT = 0 +OUTPUT_LINE = 1 +OUTPUT_TRIANGLE_CW = 2 +OUTPUT_TRIANGLE_CCW = 3 +VGT_TESS_TOPOLOGY = ctypes.c_uint32 # enum + +# values for enumeration 'VGT_TESS_TYPE' +VGT_TESS_TYPE__enumvalues = { + 0: 'TESS_ISOLINE', + 1: 'TESS_TRIANGLE', + 2: 'TESS_QUAD', +} +TESS_ISOLINE = 0 +TESS_TRIANGLE = 1 +TESS_QUAD = 2 +VGT_TESS_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_REG_XFER' +WD_IA_DRAW_REG_XFER__enumvalues = { + 0: 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', + 1: 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', + 2: 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', + 3: 'WD_IA_DRAW_REG_XFER_GE_CNTL', + 4: 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', + 5: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', + 6: 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', + 7: 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', + 8: 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', +} +WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0 +WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 1 +WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 2 +WD_IA_DRAW_REG_XFER_GE_CNTL = 3 +WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 4 +WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 5 +WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 6 +WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 7 +WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 8 +WD_IA_DRAW_REG_XFER = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_SOURCE' +WD_IA_DRAW_SOURCE__enumvalues = { + 0: 'WD_IA_DRAW_SOURCE_DMA', + 1: 'WD_IA_DRAW_SOURCE_IMMD', + 2: 'WD_IA_DRAW_SOURCE_AUTO', + 3: 'WD_IA_DRAW_SOURCE_OPAQ', +} +WD_IA_DRAW_SOURCE_DMA = 0 +WD_IA_DRAW_SOURCE_IMMD = 1 +WD_IA_DRAW_SOURCE_AUTO = 2 +WD_IA_DRAW_SOURCE_OPAQ = 3 +WD_IA_DRAW_SOURCE = ctypes.c_uint32 # enum + +# values for enumeration 'WD_IA_DRAW_TYPE' +WD_IA_DRAW_TYPE__enumvalues = { + 0: 'WD_IA_DRAW_TYPE_DI_MM0', + 1: 'WD_IA_DRAW_TYPE_REG_XFER', + 2: 'WD_IA_DRAW_TYPE_EVENT_INIT', + 3: 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 4: 'WD_IA_DRAW_TYPE_MIN_INDX', + 5: 'WD_IA_DRAW_TYPE_MAX_INDX', + 6: 'WD_IA_DRAW_TYPE_INDX_OFF', + 7: 'WD_IA_DRAW_TYPE_IMM_DATA', +} +WD_IA_DRAW_TYPE_DI_MM0 = 0 +WD_IA_DRAW_TYPE_REG_XFER = 1 +WD_IA_DRAW_TYPE_EVENT_INIT = 2 +WD_IA_DRAW_TYPE_EVENT_ADDR = 3 +WD_IA_DRAW_TYPE_MIN_INDX = 4 +WD_IA_DRAW_TYPE_MAX_INDX = 5 +WD_IA_DRAW_TYPE_INDX_OFF = 6 +WD_IA_DRAW_TYPE_IMM_DATA = 7 +WD_IA_DRAW_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'GB_EDC_DED_MODE' +GB_EDC_DED_MODE__enumvalues = { + 0: 'GB_EDC_DED_MODE_LOG', + 1: 'GB_EDC_DED_MODE_HALT', + 2: 'GB_EDC_DED_MODE_INT_HALT', +} +GB_EDC_DED_MODE_LOG = 0 +GB_EDC_DED_MODE_HALT = 1 +GB_EDC_DED_MODE_INT_HALT = 2 +GB_EDC_DED_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CHA_PERF_SEL' +CHA_PERF_SEL__enumvalues = { + 0: 'CHA_PERF_SEL_BUSY', + 1: 'CHA_PERF_SEL_STALL_CHC0', + 2: 'CHA_PERF_SEL_STALL_CHC1', + 3: 'CHA_PERF_SEL_STALL_CHC2', + 4: 'CHA_PERF_SEL_STALL_CHC3', + 5: 'CHA_PERF_SEL_STALL_CHC4', + 6: 'CHA_PERF_SEL_STALL_CHC5', + 7: 'CHA_PERF_SEL_REQUEST_CHC0', + 8: 'CHA_PERF_SEL_REQUEST_CHC1', + 9: 'CHA_PERF_SEL_REQUEST_CHC2', + 10: 'CHA_PERF_SEL_REQUEST_CHC3', + 11: 'CHA_PERF_SEL_REQUEST_CHC4', + 12: 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', + 13: 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', + 14: 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', + 15: 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', + 16: 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', + 17: 'CHA_PERF_SEL_IO_32B_WDS_CHC0', + 18: 'CHA_PERF_SEL_IO_32B_WDS_CHC1', + 19: 'CHA_PERF_SEL_IO_32B_WDS_CHC2', + 20: 'CHA_PERF_SEL_IO_32B_WDS_CHC3', + 21: 'CHA_PERF_SEL_IO_32B_WDS_CHC4', + 22: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', + 23: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', + 24: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', + 25: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', + 26: 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', + 27: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', + 28: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', + 29: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', + 30: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', + 31: 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', + 32: 'CHA_PERF_SEL_ARB_REQUESTS', + 33: 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', + 34: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', + 35: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', + 36: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', + 37: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', + 38: 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', + 39: 'CHA_PERF_SEL_CYCLE', +} +CHA_PERF_SEL_BUSY = 0 +CHA_PERF_SEL_STALL_CHC0 = 1 +CHA_PERF_SEL_STALL_CHC1 = 2 +CHA_PERF_SEL_STALL_CHC2 = 3 +CHA_PERF_SEL_STALL_CHC3 = 4 +CHA_PERF_SEL_STALL_CHC4 = 5 +CHA_PERF_SEL_STALL_CHC5 = 6 +CHA_PERF_SEL_REQUEST_CHC0 = 7 +CHA_PERF_SEL_REQUEST_CHC1 = 8 +CHA_PERF_SEL_REQUEST_CHC2 = 9 +CHA_PERF_SEL_REQUEST_CHC3 = 10 +CHA_PERF_SEL_REQUEST_CHC4 = 11 +CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 12 +CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 13 +CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 14 +CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 15 +CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 16 +CHA_PERF_SEL_IO_32B_WDS_CHC0 = 17 +CHA_PERF_SEL_IO_32B_WDS_CHC1 = 18 +CHA_PERF_SEL_IO_32B_WDS_CHC2 = 19 +CHA_PERF_SEL_IO_32B_WDS_CHC3 = 20 +CHA_PERF_SEL_IO_32B_WDS_CHC4 = 21 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 22 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 23 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 24 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 25 +CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 26 +CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 27 +CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 28 +CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 29 +CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 30 +CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 31 +CHA_PERF_SEL_ARB_REQUESTS = 32 +CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 33 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 34 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 35 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 36 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 37 +CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 38 +CHA_PERF_SEL_CYCLE = 39 +CHA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CHCG_PERF_SEL' +CHCG_PERF_SEL__enumvalues = { + 0: 'CHCG_PERF_SEL_CYCLE', + 1: 'CHCG_PERF_SEL_BUSY', + 2: 'CHCG_PERF_SEL_STARVE', + 3: 'CHCG_PERF_SEL_ARB_RET_LEVEL', + 4: 'CHCG_PERF_SEL_GL2_REQ_READ_LATENCY', + 5: 'CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY', + 6: 'CHCG_PERF_SEL_REQ', + 7: 'CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET', + 8: 'CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 9: 'CHCG_PERF_SEL_REQ_NOP_ACK', + 10: 'CHCG_PERF_SEL_REQ_NOP_RTN0', + 11: 'CHCG_PERF_SEL_REQ_READ', + 12: 'CHCG_PERF_SEL_REQ_READ_128B', + 13: 'CHCG_PERF_SEL_REQ_READ_32B', + 14: 'CHCG_PERF_SEL_REQ_READ_64B', + 15: 'CHCG_PERF_SEL_REQ_WRITE', + 16: 'CHCG_PERF_SEL_REQ_WRITE_32B', + 17: 'CHCG_PERF_SEL_REQ_WRITE_64B', + 18: 'CHCG_PERF_SEL_STALL_GUS_GL1', + 19: 'CHCG_PERF_SEL_STALL_BUFFER_FULL', + 20: 'CHCG_PERF_SEL_REQ_CLIENT0', + 21: 'CHCG_PERF_SEL_REQ_CLIENT1', + 22: 'CHCG_PERF_SEL_REQ_CLIENT2', + 23: 'CHCG_PERF_SEL_REQ_CLIENT3', + 24: 'CHCG_PERF_SEL_REQ_CLIENT4', + 25: 'CHCG_PERF_SEL_REQ_CLIENT5', + 26: 'CHCG_PERF_SEL_REQ_CLIENT6', + 27: 'CHCG_PERF_SEL_REQ_CLIENT7', + 28: 'CHCG_PERF_SEL_REQ_CLIENT8', + 29: 'CHCG_PERF_SEL_REQ_CLIENT9', + 30: 'CHCG_PERF_SEL_REQ_CLIENT10', + 31: 'CHCG_PERF_SEL_REQ_CLIENT11', + 32: 'CHCG_PERF_SEL_REQ_CLIENT12', + 33: 'CHCG_PERF_SEL_REQ_CLIENT13', + 34: 'CHCG_PERF_SEL_REQ_CLIENT14', + 35: 'CHCG_PERF_SEL_REQ_CLIENT15', + 36: 'CHCG_PERF_SEL_REQ_CLIENT16', + 37: 'CHCG_PERF_SEL_REQ_CLIENT17', + 38: 'CHCG_PERF_SEL_REQ_CLIENT18', + 39: 'CHCG_PERF_SEL_REQ_CLIENT19', + 40: 'CHCG_PERF_SEL_REQ_CLIENT20', + 41: 'CHCG_PERF_SEL_REQ_CLIENT21', + 42: 'CHCG_PERF_SEL_REQ_CLIENT22', + 43: 'CHCG_PERF_SEL_REQ_CLIENT23', +} +CHCG_PERF_SEL_CYCLE = 0 +CHCG_PERF_SEL_BUSY = 1 +CHCG_PERF_SEL_STARVE = 2 +CHCG_PERF_SEL_ARB_RET_LEVEL = 3 +CHCG_PERF_SEL_GL2_REQ_READ_LATENCY = 4 +CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 +CHCG_PERF_SEL_REQ = 6 +CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 +CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 +CHCG_PERF_SEL_REQ_NOP_ACK = 9 +CHCG_PERF_SEL_REQ_NOP_RTN0 = 10 +CHCG_PERF_SEL_REQ_READ = 11 +CHCG_PERF_SEL_REQ_READ_128B = 12 +CHCG_PERF_SEL_REQ_READ_32B = 13 +CHCG_PERF_SEL_REQ_READ_64B = 14 +CHCG_PERF_SEL_REQ_WRITE = 15 +CHCG_PERF_SEL_REQ_WRITE_32B = 16 +CHCG_PERF_SEL_REQ_WRITE_64B = 17 +CHCG_PERF_SEL_STALL_GUS_GL1 = 18 +CHCG_PERF_SEL_STALL_BUFFER_FULL = 19 +CHCG_PERF_SEL_REQ_CLIENT0 = 20 +CHCG_PERF_SEL_REQ_CLIENT1 = 21 +CHCG_PERF_SEL_REQ_CLIENT2 = 22 +CHCG_PERF_SEL_REQ_CLIENT3 = 23 +CHCG_PERF_SEL_REQ_CLIENT4 = 24 +CHCG_PERF_SEL_REQ_CLIENT5 = 25 +CHCG_PERF_SEL_REQ_CLIENT6 = 26 +CHCG_PERF_SEL_REQ_CLIENT7 = 27 +CHCG_PERF_SEL_REQ_CLIENT8 = 28 +CHCG_PERF_SEL_REQ_CLIENT9 = 29 +CHCG_PERF_SEL_REQ_CLIENT10 = 30 +CHCG_PERF_SEL_REQ_CLIENT11 = 31 +CHCG_PERF_SEL_REQ_CLIENT12 = 32 +CHCG_PERF_SEL_REQ_CLIENT13 = 33 +CHCG_PERF_SEL_REQ_CLIENT14 = 34 +CHCG_PERF_SEL_REQ_CLIENT15 = 35 +CHCG_PERF_SEL_REQ_CLIENT16 = 36 +CHCG_PERF_SEL_REQ_CLIENT17 = 37 +CHCG_PERF_SEL_REQ_CLIENT18 = 38 +CHCG_PERF_SEL_REQ_CLIENT19 = 39 +CHCG_PERF_SEL_REQ_CLIENT20 = 40 +CHCG_PERF_SEL_REQ_CLIENT21 = 41 +CHCG_PERF_SEL_REQ_CLIENT22 = 42 +CHCG_PERF_SEL_REQ_CLIENT23 = 43 +CHCG_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CHC_PERF_SEL' +CHC_PERF_SEL__enumvalues = { + 0: 'CHC_PERF_SEL_CYCLE', + 1: 'CHC_PERF_SEL_BUSY', + 2: 'CHC_PERF_SEL_STARVE', + 3: 'CHC_PERF_SEL_ARB_RET_LEVEL', + 4: 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', + 5: 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', + 6: 'CHC_PERF_SEL_REQ', + 7: 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', + 8: 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 9: 'CHC_PERF_SEL_REQ_NOP_ACK', + 10: 'CHC_PERF_SEL_REQ_NOP_RTN0', + 11: 'CHC_PERF_SEL_REQ_READ', + 12: 'CHC_PERF_SEL_REQ_READ_128B', + 13: 'CHC_PERF_SEL_REQ_READ_32B', + 14: 'CHC_PERF_SEL_REQ_READ_64B', + 15: 'CHC_PERF_SEL_REQ_WRITE', + 16: 'CHC_PERF_SEL_REQ_WRITE_32B', + 17: 'CHC_PERF_SEL_REQ_WRITE_64B', + 18: 'CHC_PERF_SEL_STALL_GL2_GL1', + 19: 'CHC_PERF_SEL_STALL_BUFFER_FULL', + 20: 'CHC_PERF_SEL_REQ_CLIENT0', + 21: 'CHC_PERF_SEL_REQ_CLIENT1', + 22: 'CHC_PERF_SEL_REQ_CLIENT2', + 23: 'CHC_PERF_SEL_REQ_CLIENT3', + 24: 'CHC_PERF_SEL_REQ_CLIENT4', + 25: 'CHC_PERF_SEL_REQ_CLIENT5', + 26: 'CHC_PERF_SEL_REQ_CLIENT6', + 27: 'CHC_PERF_SEL_REQ_CLIENT7', + 28: 'CHC_PERF_SEL_REQ_CLIENT8', + 29: 'CHC_PERF_SEL_REQ_CLIENT9', + 30: 'CHC_PERF_SEL_REQ_CLIENT10', + 31: 'CHC_PERF_SEL_REQ_CLIENT11', + 32: 'CHC_PERF_SEL_REQ_CLIENT12', + 33: 'CHC_PERF_SEL_REQ_CLIENT13', + 34: 'CHC_PERF_SEL_REQ_CLIENT14', + 35: 'CHC_PERF_SEL_REQ_CLIENT15', + 36: 'CHC_PERF_SEL_REQ_CLIENT16', + 37: 'CHC_PERF_SEL_REQ_CLIENT17', + 38: 'CHC_PERF_SEL_REQ_CLIENT18', + 39: 'CHC_PERF_SEL_REQ_CLIENT19', + 40: 'CHC_PERF_SEL_REQ_CLIENT20', + 41: 'CHC_PERF_SEL_REQ_CLIENT21', + 42: 'CHC_PERF_SEL_REQ_CLIENT22', + 43: 'CHC_PERF_SEL_REQ_CLIENT23', +} +CHC_PERF_SEL_CYCLE = 0 +CHC_PERF_SEL_BUSY = 1 +CHC_PERF_SEL_STARVE = 2 +CHC_PERF_SEL_ARB_RET_LEVEL = 3 +CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 4 +CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 5 +CHC_PERF_SEL_REQ = 6 +CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 7 +CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 8 +CHC_PERF_SEL_REQ_NOP_ACK = 9 +CHC_PERF_SEL_REQ_NOP_RTN0 = 10 +CHC_PERF_SEL_REQ_READ = 11 +CHC_PERF_SEL_REQ_READ_128B = 12 +CHC_PERF_SEL_REQ_READ_32B = 13 +CHC_PERF_SEL_REQ_READ_64B = 14 +CHC_PERF_SEL_REQ_WRITE = 15 +CHC_PERF_SEL_REQ_WRITE_32B = 16 +CHC_PERF_SEL_REQ_WRITE_64B = 17 +CHC_PERF_SEL_STALL_GL2_GL1 = 18 +CHC_PERF_SEL_STALL_BUFFER_FULL = 19 +CHC_PERF_SEL_REQ_CLIENT0 = 20 +CHC_PERF_SEL_REQ_CLIENT1 = 21 +CHC_PERF_SEL_REQ_CLIENT2 = 22 +CHC_PERF_SEL_REQ_CLIENT3 = 23 +CHC_PERF_SEL_REQ_CLIENT4 = 24 +CHC_PERF_SEL_REQ_CLIENT5 = 25 +CHC_PERF_SEL_REQ_CLIENT6 = 26 +CHC_PERF_SEL_REQ_CLIENT7 = 27 +CHC_PERF_SEL_REQ_CLIENT8 = 28 +CHC_PERF_SEL_REQ_CLIENT9 = 29 +CHC_PERF_SEL_REQ_CLIENT10 = 30 +CHC_PERF_SEL_REQ_CLIENT11 = 31 +CHC_PERF_SEL_REQ_CLIENT12 = 32 +CHC_PERF_SEL_REQ_CLIENT13 = 33 +CHC_PERF_SEL_REQ_CLIENT14 = 34 +CHC_PERF_SEL_REQ_CLIENT15 = 35 +CHC_PERF_SEL_REQ_CLIENT16 = 36 +CHC_PERF_SEL_REQ_CLIENT17 = 37 +CHC_PERF_SEL_REQ_CLIENT18 = 38 +CHC_PERF_SEL_REQ_CLIENT19 = 39 +CHC_PERF_SEL_REQ_CLIENT20 = 40 +CHC_PERF_SEL_REQ_CLIENT21 = 41 +CHC_PERF_SEL_REQ_CLIENT22 = 42 +CHC_PERF_SEL_REQ_CLIENT23 = 43 +CHC_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1A_PERF_SEL' +GL1A_PERF_SEL__enumvalues = { + 0: 'GL1A_PERF_SEL_BUSY', + 1: 'GL1A_PERF_SEL_STALL_GL1C0', + 2: 'GL1A_PERF_SEL_STALL_GL1C1', + 3: 'GL1A_PERF_SEL_STALL_GL1C2', + 4: 'GL1A_PERF_SEL_STALL_GL1C3', + 5: 'GL1A_PERF_SEL_REQUEST_GL1C0', + 6: 'GL1A_PERF_SEL_REQUEST_GL1C1', + 7: 'GL1A_PERF_SEL_REQUEST_GL1C2', + 8: 'GL1A_PERF_SEL_REQUEST_GL1C3', + 9: 'GL1A_PERF_SEL_WDS_32B_GL1C0', + 10: 'GL1A_PERF_SEL_WDS_32B_GL1C1', + 11: 'GL1A_PERF_SEL_WDS_32B_GL1C2', + 12: 'GL1A_PERF_SEL_WDS_32B_GL1C3', + 13: 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', + 14: 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', + 15: 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', + 16: 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', + 17: 'GL1A_PERF_SEL_ARB_REQUESTS', + 18: 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', + 19: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', + 20: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', + 21: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', + 22: 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', + 23: 'GL1A_PERF_SEL_CYCLE', +} +GL1A_PERF_SEL_BUSY = 0 +GL1A_PERF_SEL_STALL_GL1C0 = 1 +GL1A_PERF_SEL_STALL_GL1C1 = 2 +GL1A_PERF_SEL_STALL_GL1C2 = 3 +GL1A_PERF_SEL_STALL_GL1C3 = 4 +GL1A_PERF_SEL_REQUEST_GL1C0 = 5 +GL1A_PERF_SEL_REQUEST_GL1C1 = 6 +GL1A_PERF_SEL_REQUEST_GL1C2 = 7 +GL1A_PERF_SEL_REQUEST_GL1C3 = 8 +GL1A_PERF_SEL_WDS_32B_GL1C0 = 9 +GL1A_PERF_SEL_WDS_32B_GL1C1 = 10 +GL1A_PERF_SEL_WDS_32B_GL1C2 = 11 +GL1A_PERF_SEL_WDS_32B_GL1C3 = 12 +GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 13 +GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 14 +GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 15 +GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 16 +GL1A_PERF_SEL_ARB_REQUESTS = 17 +GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 18 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 19 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 20 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 21 +GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 22 +GL1A_PERF_SEL_CYCLE = 23 +GL1A_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1C_PERF_SEL' +GL1C_PERF_SEL__enumvalues = { + 0: 'GL1C_PERF_SEL_CYCLE', + 1: 'GL1C_PERF_SEL_BUSY', + 2: 'GL1C_PERF_SEL_STARVE', + 3: 'GL1C_PERF_SEL_ARB_RET_LEVEL', + 4: 'GL1C_PERF_SEL_GL2_REQ_READ', + 5: 'GL1C_PERF_SEL_GL2_REQ_READ_128B', + 6: 'GL1C_PERF_SEL_GL2_REQ_READ_32B', + 7: 'GL1C_PERF_SEL_GL2_REQ_READ_64B', + 8: 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', + 9: 'GL1C_PERF_SEL_GL2_REQ_WRITE', + 10: 'GL1C_PERF_SEL_GL2_REQ_WRITE_32B', + 11: 'GL1C_PERF_SEL_GL2_REQ_WRITE_64B', + 12: 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', + 13: 'GL1C_PERF_SEL_GL2_REQ_PREFETCH', + 14: 'GL1C_PERF_SEL_REQ', + 15: 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', + 16: 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 17: 'GL1C_PERF_SEL_REQ_SHADER_INV', + 18: 'GL1C_PERF_SEL_REQ_MISS', + 19: 'GL1C_PERF_SEL_REQ_NOP_ACK', + 20: 'GL1C_PERF_SEL_REQ_NOP_RTN0', + 21: 'GL1C_PERF_SEL_REQ_READ', + 22: 'GL1C_PERF_SEL_REQ_READ_128B', + 23: 'GL1C_PERF_SEL_REQ_READ_32B', + 24: 'GL1C_PERF_SEL_REQ_READ_64B', + 25: 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT', + 26: 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU', + 27: 'GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT', + 28: 'GL1C_PERF_SEL_REQ_WRITE', + 29: 'GL1C_PERF_SEL_REQ_WRITE_32B', + 30: 'GL1C_PERF_SEL_REQ_WRITE_64B', + 31: 'GL1C_PERF_SEL_STALL_GL2_GL1', + 32: 'GL1C_PERF_SEL_STALL_LFIFO_FULL', + 33: 'GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC', + 34: 'GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE', + 35: 'GL1C_PERF_SEL_STALL_GCR_INV', + 36: 'GL1C_PERF_SEL_STALL_VM', + 37: 'GL1C_PERF_SEL_REQ_CLIENT0', + 38: 'GL1C_PERF_SEL_REQ_CLIENT1', + 39: 'GL1C_PERF_SEL_REQ_CLIENT2', + 40: 'GL1C_PERF_SEL_REQ_CLIENT3', + 41: 'GL1C_PERF_SEL_REQ_CLIENT4', + 42: 'GL1C_PERF_SEL_REQ_CLIENT5', + 43: 'GL1C_PERF_SEL_REQ_CLIENT6', + 44: 'GL1C_PERF_SEL_REQ_CLIENT7', + 45: 'GL1C_PERF_SEL_REQ_CLIENT8', + 46: 'GL1C_PERF_SEL_REQ_CLIENT9', + 47: 'GL1C_PERF_SEL_REQ_CLIENT10', + 48: 'GL1C_PERF_SEL_REQ_CLIENT11', + 49: 'GL1C_PERF_SEL_REQ_CLIENT12', + 50: 'GL1C_PERF_SEL_REQ_CLIENT13', + 51: 'GL1C_PERF_SEL_REQ_CLIENT14', + 52: 'GL1C_PERF_SEL_REQ_CLIENT15', + 53: 'GL1C_PERF_SEL_REQ_CLIENT16', + 54: 'GL1C_PERF_SEL_REQ_CLIENT17', + 55: 'GL1C_PERF_SEL_REQ_CLIENT18', + 56: 'GL1C_PERF_SEL_REQ_CLIENT19', + 57: 'GL1C_PERF_SEL_REQ_CLIENT20', + 58: 'GL1C_PERF_SEL_REQ_CLIENT21', + 59: 'GL1C_PERF_SEL_REQ_CLIENT22', + 60: 'GL1C_PERF_SEL_REQ_CLIENT23', + 61: 'GL1C_PERF_SEL_REQ_CLIENT24', + 62: 'GL1C_PERF_SEL_REQ_CLIENT25', + 63: 'GL1C_PERF_SEL_REQ_CLIENT26', + 64: 'GL1C_PERF_SEL_REQ_CLIENT27', + 65: 'GL1C_PERF_SEL_UTCL0_REQUEST', + 66: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', + 67: 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', + 68: 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', + 69: 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', + 70: 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', + 71: 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 72: 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 73: 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 74: 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 75: 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', + 76: 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 77: 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', + 78: 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', + 79: 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', + 80: 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', + 81: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', + 82: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', + 83: 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', +} +GL1C_PERF_SEL_CYCLE = 0 +GL1C_PERF_SEL_BUSY = 1 +GL1C_PERF_SEL_STARVE = 2 +GL1C_PERF_SEL_ARB_RET_LEVEL = 3 +GL1C_PERF_SEL_GL2_REQ_READ = 4 +GL1C_PERF_SEL_GL2_REQ_READ_128B = 5 +GL1C_PERF_SEL_GL2_REQ_READ_32B = 6 +GL1C_PERF_SEL_GL2_REQ_READ_64B = 7 +GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 8 +GL1C_PERF_SEL_GL2_REQ_WRITE = 9 +GL1C_PERF_SEL_GL2_REQ_WRITE_32B = 10 +GL1C_PERF_SEL_GL2_REQ_WRITE_64B = 11 +GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 12 +GL1C_PERF_SEL_GL2_REQ_PREFETCH = 13 +GL1C_PERF_SEL_REQ = 14 +GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 15 +GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 16 +GL1C_PERF_SEL_REQ_SHADER_INV = 17 +GL1C_PERF_SEL_REQ_MISS = 18 +GL1C_PERF_SEL_REQ_NOP_ACK = 19 +GL1C_PERF_SEL_REQ_NOP_RTN0 = 20 +GL1C_PERF_SEL_REQ_READ = 21 +GL1C_PERF_SEL_REQ_READ_128B = 22 +GL1C_PERF_SEL_REQ_READ_32B = 23 +GL1C_PERF_SEL_REQ_READ_64B = 24 +GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT = 25 +GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU = 26 +GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT = 27 +GL1C_PERF_SEL_REQ_WRITE = 28 +GL1C_PERF_SEL_REQ_WRITE_32B = 29 +GL1C_PERF_SEL_REQ_WRITE_64B = 30 +GL1C_PERF_SEL_STALL_GL2_GL1 = 31 +GL1C_PERF_SEL_STALL_LFIFO_FULL = 32 +GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC = 33 +GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE = 34 +GL1C_PERF_SEL_STALL_GCR_INV = 35 +GL1C_PERF_SEL_STALL_VM = 36 +GL1C_PERF_SEL_REQ_CLIENT0 = 37 +GL1C_PERF_SEL_REQ_CLIENT1 = 38 +GL1C_PERF_SEL_REQ_CLIENT2 = 39 +GL1C_PERF_SEL_REQ_CLIENT3 = 40 +GL1C_PERF_SEL_REQ_CLIENT4 = 41 +GL1C_PERF_SEL_REQ_CLIENT5 = 42 +GL1C_PERF_SEL_REQ_CLIENT6 = 43 +GL1C_PERF_SEL_REQ_CLIENT7 = 44 +GL1C_PERF_SEL_REQ_CLIENT8 = 45 +GL1C_PERF_SEL_REQ_CLIENT9 = 46 +GL1C_PERF_SEL_REQ_CLIENT10 = 47 +GL1C_PERF_SEL_REQ_CLIENT11 = 48 +GL1C_PERF_SEL_REQ_CLIENT12 = 49 +GL1C_PERF_SEL_REQ_CLIENT13 = 50 +GL1C_PERF_SEL_REQ_CLIENT14 = 51 +GL1C_PERF_SEL_REQ_CLIENT15 = 52 +GL1C_PERF_SEL_REQ_CLIENT16 = 53 +GL1C_PERF_SEL_REQ_CLIENT17 = 54 +GL1C_PERF_SEL_REQ_CLIENT18 = 55 +GL1C_PERF_SEL_REQ_CLIENT19 = 56 +GL1C_PERF_SEL_REQ_CLIENT20 = 57 +GL1C_PERF_SEL_REQ_CLIENT21 = 58 +GL1C_PERF_SEL_REQ_CLIENT22 = 59 +GL1C_PERF_SEL_REQ_CLIENT23 = 60 +GL1C_PERF_SEL_REQ_CLIENT24 = 61 +GL1C_PERF_SEL_REQ_CLIENT25 = 62 +GL1C_PERF_SEL_REQ_CLIENT26 = 63 +GL1C_PERF_SEL_REQ_CLIENT27 = 64 +GL1C_PERF_SEL_UTCL0_REQUEST = 65 +GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 66 +GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 67 +GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 68 +GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 69 +GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 70 +GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 71 +GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 72 +GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 73 +GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 74 +GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 75 +GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 76 +GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 77 +GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 78 +GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 79 +GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 80 +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 81 +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 82 +GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 83 +GL1C_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL1H_REQ_PERF_SEL' +GL1H_REQ_PERF_SEL__enumvalues = { + 0: 'GL1H_REQ_PERF_SEL_BUSY', + 1: 'GL1H_REQ_PERF_SEL_STALL_GL1_0', + 2: 'GL1H_REQ_PERF_SEL_STALL_GL1_1', + 3: 'GL1H_REQ_PERF_SEL_REQUEST_GL1_0', + 4: 'GL1H_REQ_PERF_SEL_REQUEST_GL1_1', + 5: 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_0', + 6: 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_1', + 7: 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0', + 8: 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1', + 9: 'GL1H_REQ_PERF_SEL_ARB_REQUESTS', + 10: 'GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL', + 11: 'GL1H_REQ_PERF_SEL_CYCLE', +} +GL1H_REQ_PERF_SEL_BUSY = 0 +GL1H_REQ_PERF_SEL_STALL_GL1_0 = 1 +GL1H_REQ_PERF_SEL_STALL_GL1_1 = 2 +GL1H_REQ_PERF_SEL_REQUEST_GL1_0 = 3 +GL1H_REQ_PERF_SEL_REQUEST_GL1_1 = 4 +GL1H_REQ_PERF_SEL_WDS_32B_GL1_0 = 5 +GL1H_REQ_PERF_SEL_WDS_32B_GL1_1 = 6 +GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0 = 7 +GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1 = 8 +GL1H_REQ_PERF_SEL_ARB_REQUESTS = 9 +GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL = 10 +GL1H_REQ_PERF_SEL_CYCLE = 11 +GL1H_REQ_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TA_PERFCOUNT_SEL' +TA_PERFCOUNT_SEL__enumvalues = { + 0: 'TA_PERF_SEL_NULL', + 1: 'TA_PERF_SEL_image_sampler_has_offset_instructions', + 2: 'TA_PERF_SEL_image_sampler_has_bias_instructions', + 3: 'TA_PERF_SEL_image_sampler_has_reference_instructions', + 4: 'TA_PERF_SEL_image_sampler_has_ds_instructions', + 5: 'TA_PERF_SEL_image_sampler_has_dt_instructions', + 6: 'TA_PERF_SEL_image_sampler_has_dr_instructions', + 7: 'TA_PERF_SEL_gradient_busy', + 8: 'TA_PERF_SEL_gradient_fifo_busy', + 9: 'TA_PERF_SEL_lod_busy', + 10: 'TA_PERF_SEL_lod_fifo_busy', + 11: 'TA_PERF_SEL_addresser_busy', + 12: 'TA_PERF_SEL_addresser_fifo_busy', + 13: 'TA_PERF_SEL_aligner_busy', + 14: 'TA_PERF_SEL_write_path_busy', + 15: 'TA_PERF_SEL_ta_busy', + 16: 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', + 17: 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', + 18: 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', + 19: 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', + 20: 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', + 21: 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', + 22: 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', + 23: 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', + 24: 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', + 25: 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', + 26: 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', + 27: 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', + 28: 'TA_PERF_SEL_image_sampler_has_t_instructions', + 29: 'TA_PERF_SEL_image_sampler_has_r_instructions', + 30: 'TA_PERF_SEL_image_sampler_has_q_instructions', + 32: 'TA_PERF_SEL_total_wavefronts', + 33: 'TA_PERF_SEL_gradient_cycles', + 34: 'TA_PERF_SEL_walker_cycles', + 35: 'TA_PERF_SEL_aligner_cycles', + 36: 'TA_PERF_SEL_image_wavefronts', + 37: 'TA_PERF_SEL_image_read_wavefronts', + 38: 'TA_PERF_SEL_image_store_wavefronts', + 39: 'TA_PERF_SEL_image_atomic_wavefronts', + 40: 'TA_PERF_SEL_image_sampler_total_cycles', + 41: 'TA_PERF_SEL_image_nosampler_total_cycles', + 42: 'TA_PERF_SEL_flat_total_cycles', + 43: 'TA_PERF_SEL_bvh_total_cycles', + 44: 'TA_PERF_SEL_buffer_wavefronts', + 45: 'TA_PERF_SEL_buffer_load_wavefronts', + 46: 'TA_PERF_SEL_buffer_store_wavefronts', + 47: 'TA_PERF_SEL_buffer_atomic_wavefronts', + 49: 'TA_PERF_SEL_buffer_total_cycles', + 50: 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', + 51: 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', + 52: 'TA_PERF_SEL_buffer_has_index_instructions', + 53: 'TA_PERF_SEL_buffer_has_offset_instructions', + 54: 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 55: 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 56: 'TA_PERF_SEL_image_sampler_wavefronts', + 57: 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 58: 'TA_PERF_SEL_addresser_stalled_cycles', + 59: 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 60: 'TA_PERF_SEL_aniso_stalled_cycles', + 61: 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 62: 'TA_PERF_SEL_deriv_stalled_cycles', + 63: 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 64: 'TA_PERF_SEL_color_1_cycle_quads', + 65: 'TA_PERF_SEL_color_2_cycle_quads', + 66: 'TA_PERF_SEL_color_3_cycle_quads', + 68: 'TA_PERF_SEL_mip_1_cycle_quads', + 69: 'TA_PERF_SEL_mip_2_cycle_quads', + 70: 'TA_PERF_SEL_vol_1_cycle_quads', + 71: 'TA_PERF_SEL_vol_2_cycle_quads', + 72: 'TA_PERF_SEL_sampler_op_quads', + 73: 'TA_PERF_SEL_mipmap_lod_0_samples', + 74: 'TA_PERF_SEL_mipmap_lod_1_samples', + 75: 'TA_PERF_SEL_mipmap_lod_2_samples', + 76: 'TA_PERF_SEL_mipmap_lod_3_samples', + 77: 'TA_PERF_SEL_mipmap_lod_4_samples', + 78: 'TA_PERF_SEL_mipmap_lod_5_samples', + 79: 'TA_PERF_SEL_mipmap_lod_6_samples', + 80: 'TA_PERF_SEL_mipmap_lod_7_samples', + 81: 'TA_PERF_SEL_mipmap_lod_8_samples', + 82: 'TA_PERF_SEL_mipmap_lod_9_samples', + 83: 'TA_PERF_SEL_mipmap_lod_10_samples', + 84: 'TA_PERF_SEL_mipmap_lod_11_samples', + 85: 'TA_PERF_SEL_mipmap_lod_12_samples', + 86: 'TA_PERF_SEL_mipmap_lod_13_samples', + 87: 'TA_PERF_SEL_mipmap_lod_14_samples', + 88: 'TA_PERF_SEL_mipmap_invalid_samples', + 89: 'TA_PERF_SEL_aniso_1_cycle_quads', + 90: 'TA_PERF_SEL_aniso_2_cycle_quads', + 91: 'TA_PERF_SEL_aniso_4_cycle_quads', + 92: 'TA_PERF_SEL_aniso_6_cycle_quads', + 93: 'TA_PERF_SEL_aniso_8_cycle_quads', + 94: 'TA_PERF_SEL_aniso_10_cycle_quads', + 95: 'TA_PERF_SEL_aniso_12_cycle_quads', + 96: 'TA_PERF_SEL_aniso_14_cycle_quads', + 97: 'TA_PERF_SEL_aniso_16_cycle_quads', + 98: 'TA_PERF_SEL_store_write_data_input_cycles', + 99: 'TA_PERF_SEL_store_write_data_output_cycles', + 100: 'TA_PERF_SEL_flat_wavefronts', + 101: 'TA_PERF_SEL_flat_load_wavefronts', + 102: 'TA_PERF_SEL_flat_store_wavefronts', + 103: 'TA_PERF_SEL_flat_atomic_wavefronts', + 104: 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', + 105: 'TA_PERF_SEL_register_clk_valid_cycles', + 106: 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', + 107: 'TA_PERF_SEL_harvestable_clk_enabled_cycles', + 108: 'TA_PERF_SEL_harvestable_register_clk_enabled_cycles', + 109: 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', + 110: 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', + 114: 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', + 115: 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', + 116: 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', + 117: 'TA_PERF_SEL_store_has_x_instructions', + 118: 'TA_PERF_SEL_store_has_y_instructions', + 119: 'TA_PERF_SEL_store_has_z_instructions', + 120: 'TA_PERF_SEL_store_has_w_instructions', + 121: 'TA_PERF_SEL_image_nosampler_has_t_instructions', + 122: 'TA_PERF_SEL_image_nosampler_has_r_instructions', + 123: 'TA_PERF_SEL_image_nosampler_has_q_instructions', + 124: 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', + 125: 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', + 126: 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', + 127: 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', + 128: 'TA_PERF_SEL_in_busy', + 129: 'TA_PERF_SEL_in_fifos_busy', + 130: 'TA_PERF_SEL_in_cfifo_busy', + 131: 'TA_PERF_SEL_in_qfifo_busy', + 132: 'TA_PERF_SEL_in_wfifo_busy', + 133: 'TA_PERF_SEL_in_rfifo_busy', + 134: 'TA_PERF_SEL_bf_busy', + 135: 'TA_PERF_SEL_ns_busy', + 136: 'TA_PERF_SEL_smp_busy_ns_idle', + 137: 'TA_PERF_SEL_smp_idle_ns_busy', + 144: 'TA_PERF_SEL_vmemcmd_cycles', + 145: 'TA_PERF_SEL_vmemreq_cycles', + 146: 'TA_PERF_SEL_in_waiting_on_req_cycles', + 150: 'TA_PERF_SEL_in_addr_cycles', + 151: 'TA_PERF_SEL_in_data_cycles', + 154: 'TA_PERF_SEL_latency_ram_weights_written_cycles', + 155: 'TA_PERF_SEL_latency_ram_ws_required_quads', + 156: 'TA_PERF_SEL_latency_ram_whv_required_quads', + 157: 'TA_PERF_SEL_latency_ram_ws_required_instructions', + 158: 'TA_PERF_SEL_latency_ram_whv_required_instructions', + 159: 'TA_PERF_SEL_latency_ram_ref_required_instructions', + 160: 'TA_PERF_SEL_point_sampled_quads', + 162: 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', + 163: 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', + 164: 'TA_PERF_SEL_atomic_write_data_input_cycles', + 165: 'TA_PERF_SEL_atomic_write_data_output_cycles', + 173: 'TA_PERF_SEL_num_unlit_nodes_ta_opt', + 174: 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', + 175: 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', + 176: 'TA_PERF_SEL_num_of_bvh_valid_first_tri', + 177: 'TA_PERF_SEL_num_of_bvh_valid_second_tri', + 178: 'TA_PERF_SEL_num_of_bvh_valid_third_tri', + 179: 'TA_PERF_SEL_num_of_bvh_valid_fourth_tri', + 180: 'TA_PERF_SEL_num_of_bvh_valid_fp16_box', + 181: 'TA_PERF_SEL_num_of_bvh_valid_fp32_box', + 182: 'TA_PERF_SEL_num_of_bvh_invalidated_first_tri', + 183: 'TA_PERF_SEL_num_of_bvh_invalidated_second_tri', + 184: 'TA_PERF_SEL_num_of_bvh_invalidated_third_tri', + 185: 'TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri', + 186: 'TA_PERF_SEL_num_of_bvh_invalidated_fp16_box', + 187: 'TA_PERF_SEL_num_of_bvh_invalidated_fp32_box', + 188: 'TA_PERF_SEL_image_bvh_8_input_vgpr_instructions', + 189: 'TA_PERF_SEL_image_bvh_9_input_vgpr_instructions', + 190: 'TA_PERF_SEL_image_bvh_11_input_vgpr_instructions', + 191: 'TA_PERF_SEL_image_bvh_12_input_vgpr_instructions', + 192: 'TA_PERF_SEL_image_sampler_1_op_burst', + 193: 'TA_PERF_SEL_image_sampler_2to3_op_burst', + 194: 'TA_PERF_SEL_image_sampler_4to7_op_burst', + 195: 'TA_PERF_SEL_image_sampler_ge8_op_burst', + 196: 'TA_PERF_SEL_image_linked_1_op_burst', + 197: 'TA_PERF_SEL_image_linked_2to3_op_burst', + 198: 'TA_PERF_SEL_image_linked_4to7_op_burst', + 199: 'TA_PERF_SEL_image_linked_ge8_op_burst', + 200: 'TA_PERF_SEL_image_bvh_1_op_burst', + 201: 'TA_PERF_SEL_image_bvh_2to3_op_burst', + 202: 'TA_PERF_SEL_image_bvh_4to7_op_burst', + 203: 'TA_PERF_SEL_image_bvh_ge8_op_burst', + 204: 'TA_PERF_SEL_image_nosampler_1_op_burst', + 205: 'TA_PERF_SEL_image_nosampler_2to3_op_burst', + 206: 'TA_PERF_SEL_image_nosampler_4to31_op_burst', + 207: 'TA_PERF_SEL_image_nosampler_ge32_op_burst', + 208: 'TA_PERF_SEL_buffer_flat_1_op_burst', + 209: 'TA_PERF_SEL_buffer_flat_2to3_op_burst', + 210: 'TA_PERF_SEL_buffer_flat_4to31_op_burst', + 211: 'TA_PERF_SEL_buffer_flat_ge32_op_burst', + 212: 'TA_PERF_SEL_write_1_op_burst', + 213: 'TA_PERF_SEL_write_2to3_op_burst', + 214: 'TA_PERF_SEL_write_4to31_op_burst', + 215: 'TA_PERF_SEL_write_ge32_op_burst', + 216: 'TA_PERF_SEL_ibubble_1_cycle_burst', + 217: 'TA_PERF_SEL_ibubble_2to3_cycle_burst', + 218: 'TA_PERF_SEL_ibubble_4to15_cycle_burst', + 219: 'TA_PERF_SEL_ibubble_16to31_cycle_burst', + 220: 'TA_PERF_SEL_ibubble_32to63_cycle_burst', + 221: 'TA_PERF_SEL_ibubble_ge64_cycle_burst', + 224: 'TA_PERF_SEL_sampler_clk_valid_cycles', + 225: 'TA_PERF_SEL_nonsampler_clk_valid_cycles', + 226: 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', + 227: 'TA_PERF_SEL_write_data_clk_valid_cycles', + 228: 'TA_PERF_SEL_gradient_clk_valid_cycles', + 229: 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', + 230: 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', + 231: 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', + 232: 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', + 233: 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', + 234: 'TA_PERF_SEL_aligner_clk_valid_cycles', + 235: 'TA_PERF_SEL_tcreq_clk_valid_cycles', +} +TA_PERF_SEL_NULL = 0 +TA_PERF_SEL_image_sampler_has_offset_instructions = 1 +TA_PERF_SEL_image_sampler_has_bias_instructions = 2 +TA_PERF_SEL_image_sampler_has_reference_instructions = 3 +TA_PERF_SEL_image_sampler_has_ds_instructions = 4 +TA_PERF_SEL_image_sampler_has_dt_instructions = 5 +TA_PERF_SEL_image_sampler_has_dr_instructions = 6 +TA_PERF_SEL_gradient_busy = 7 +TA_PERF_SEL_gradient_fifo_busy = 8 +TA_PERF_SEL_lod_busy = 9 +TA_PERF_SEL_lod_fifo_busy = 10 +TA_PERF_SEL_addresser_busy = 11 +TA_PERF_SEL_addresser_fifo_busy = 12 +TA_PERF_SEL_aligner_busy = 13 +TA_PERF_SEL_write_path_busy = 14 +TA_PERF_SEL_ta_busy = 15 +TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 16 +TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 17 +TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 18 +TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 19 +TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 20 +TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 21 +TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 22 +TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 23 +TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 24 +TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 25 +TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 26 +TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 27 +TA_PERF_SEL_image_sampler_has_t_instructions = 28 +TA_PERF_SEL_image_sampler_has_r_instructions = 29 +TA_PERF_SEL_image_sampler_has_q_instructions = 30 +TA_PERF_SEL_total_wavefronts = 32 +TA_PERF_SEL_gradient_cycles = 33 +TA_PERF_SEL_walker_cycles = 34 +TA_PERF_SEL_aligner_cycles = 35 +TA_PERF_SEL_image_wavefronts = 36 +TA_PERF_SEL_image_read_wavefronts = 37 +TA_PERF_SEL_image_store_wavefronts = 38 +TA_PERF_SEL_image_atomic_wavefronts = 39 +TA_PERF_SEL_image_sampler_total_cycles = 40 +TA_PERF_SEL_image_nosampler_total_cycles = 41 +TA_PERF_SEL_flat_total_cycles = 42 +TA_PERF_SEL_bvh_total_cycles = 43 +TA_PERF_SEL_buffer_wavefronts = 44 +TA_PERF_SEL_buffer_load_wavefronts = 45 +TA_PERF_SEL_buffer_store_wavefronts = 46 +TA_PERF_SEL_buffer_atomic_wavefronts = 47 +TA_PERF_SEL_buffer_total_cycles = 49 +TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 50 +TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 51 +TA_PERF_SEL_buffer_has_index_instructions = 52 +TA_PERF_SEL_buffer_has_offset_instructions = 53 +TA_PERF_SEL_addr_stalled_by_tc_cycles = 54 +TA_PERF_SEL_addr_stalled_by_td_cycles = 55 +TA_PERF_SEL_image_sampler_wavefronts = 56 +TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 57 +TA_PERF_SEL_addresser_stalled_cycles = 58 +TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 59 +TA_PERF_SEL_aniso_stalled_cycles = 60 +TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 61 +TA_PERF_SEL_deriv_stalled_cycles = 62 +TA_PERF_SEL_aniso_gt1_cycle_quads = 63 +TA_PERF_SEL_color_1_cycle_quads = 64 +TA_PERF_SEL_color_2_cycle_quads = 65 +TA_PERF_SEL_color_3_cycle_quads = 66 +TA_PERF_SEL_mip_1_cycle_quads = 68 +TA_PERF_SEL_mip_2_cycle_quads = 69 +TA_PERF_SEL_vol_1_cycle_quads = 70 +TA_PERF_SEL_vol_2_cycle_quads = 71 +TA_PERF_SEL_sampler_op_quads = 72 +TA_PERF_SEL_mipmap_lod_0_samples = 73 +TA_PERF_SEL_mipmap_lod_1_samples = 74 +TA_PERF_SEL_mipmap_lod_2_samples = 75 +TA_PERF_SEL_mipmap_lod_3_samples = 76 +TA_PERF_SEL_mipmap_lod_4_samples = 77 +TA_PERF_SEL_mipmap_lod_5_samples = 78 +TA_PERF_SEL_mipmap_lod_6_samples = 79 +TA_PERF_SEL_mipmap_lod_7_samples = 80 +TA_PERF_SEL_mipmap_lod_8_samples = 81 +TA_PERF_SEL_mipmap_lod_9_samples = 82 +TA_PERF_SEL_mipmap_lod_10_samples = 83 +TA_PERF_SEL_mipmap_lod_11_samples = 84 +TA_PERF_SEL_mipmap_lod_12_samples = 85 +TA_PERF_SEL_mipmap_lod_13_samples = 86 +TA_PERF_SEL_mipmap_lod_14_samples = 87 +TA_PERF_SEL_mipmap_invalid_samples = 88 +TA_PERF_SEL_aniso_1_cycle_quads = 89 +TA_PERF_SEL_aniso_2_cycle_quads = 90 +TA_PERF_SEL_aniso_4_cycle_quads = 91 +TA_PERF_SEL_aniso_6_cycle_quads = 92 +TA_PERF_SEL_aniso_8_cycle_quads = 93 +TA_PERF_SEL_aniso_10_cycle_quads = 94 +TA_PERF_SEL_aniso_12_cycle_quads = 95 +TA_PERF_SEL_aniso_14_cycle_quads = 96 +TA_PERF_SEL_aniso_16_cycle_quads = 97 +TA_PERF_SEL_store_write_data_input_cycles = 98 +TA_PERF_SEL_store_write_data_output_cycles = 99 +TA_PERF_SEL_flat_wavefronts = 100 +TA_PERF_SEL_flat_load_wavefronts = 101 +TA_PERF_SEL_flat_store_wavefronts = 102 +TA_PERF_SEL_flat_atomic_wavefronts = 103 +TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 104 +TA_PERF_SEL_register_clk_valid_cycles = 105 +TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 106 +TA_PERF_SEL_harvestable_clk_enabled_cycles = 107 +TA_PERF_SEL_harvestable_register_clk_enabled_cycles = 108 +TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 109 +TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 110 +TA_PERF_SEL_store_2_write_data_vgpr_instructions = 114 +TA_PERF_SEL_store_3_write_data_vgpr_instructions = 115 +TA_PERF_SEL_store_4_write_data_vgpr_instructions = 116 +TA_PERF_SEL_store_has_x_instructions = 117 +TA_PERF_SEL_store_has_y_instructions = 118 +TA_PERF_SEL_store_has_z_instructions = 119 +TA_PERF_SEL_store_has_w_instructions = 120 +TA_PERF_SEL_image_nosampler_has_t_instructions = 121 +TA_PERF_SEL_image_nosampler_has_r_instructions = 122 +TA_PERF_SEL_image_nosampler_has_q_instructions = 123 +TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 124 +TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 125 +TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 126 +TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 127 +TA_PERF_SEL_in_busy = 128 +TA_PERF_SEL_in_fifos_busy = 129 +TA_PERF_SEL_in_cfifo_busy = 130 +TA_PERF_SEL_in_qfifo_busy = 131 +TA_PERF_SEL_in_wfifo_busy = 132 +TA_PERF_SEL_in_rfifo_busy = 133 +TA_PERF_SEL_bf_busy = 134 +TA_PERF_SEL_ns_busy = 135 +TA_PERF_SEL_smp_busy_ns_idle = 136 +TA_PERF_SEL_smp_idle_ns_busy = 137 +TA_PERF_SEL_vmemcmd_cycles = 144 +TA_PERF_SEL_vmemreq_cycles = 145 +TA_PERF_SEL_in_waiting_on_req_cycles = 146 +TA_PERF_SEL_in_addr_cycles = 150 +TA_PERF_SEL_in_data_cycles = 151 +TA_PERF_SEL_latency_ram_weights_written_cycles = 154 +TA_PERF_SEL_latency_ram_ws_required_quads = 155 +TA_PERF_SEL_latency_ram_whv_required_quads = 156 +TA_PERF_SEL_latency_ram_ws_required_instructions = 157 +TA_PERF_SEL_latency_ram_whv_required_instructions = 158 +TA_PERF_SEL_latency_ram_ref_required_instructions = 159 +TA_PERF_SEL_point_sampled_quads = 160 +TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 162 +TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 163 +TA_PERF_SEL_atomic_write_data_input_cycles = 164 +TA_PERF_SEL_atomic_write_data_output_cycles = 165 +TA_PERF_SEL_num_unlit_nodes_ta_opt = 173 +TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 174 +TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 175 +TA_PERF_SEL_num_of_bvh_valid_first_tri = 176 +TA_PERF_SEL_num_of_bvh_valid_second_tri = 177 +TA_PERF_SEL_num_of_bvh_valid_third_tri = 178 +TA_PERF_SEL_num_of_bvh_valid_fourth_tri = 179 +TA_PERF_SEL_num_of_bvh_valid_fp16_box = 180 +TA_PERF_SEL_num_of_bvh_valid_fp32_box = 181 +TA_PERF_SEL_num_of_bvh_invalidated_first_tri = 182 +TA_PERF_SEL_num_of_bvh_invalidated_second_tri = 183 +TA_PERF_SEL_num_of_bvh_invalidated_third_tri = 184 +TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri = 185 +TA_PERF_SEL_num_of_bvh_invalidated_fp16_box = 186 +TA_PERF_SEL_num_of_bvh_invalidated_fp32_box = 187 +TA_PERF_SEL_image_bvh_8_input_vgpr_instructions = 188 +TA_PERF_SEL_image_bvh_9_input_vgpr_instructions = 189 +TA_PERF_SEL_image_bvh_11_input_vgpr_instructions = 190 +TA_PERF_SEL_image_bvh_12_input_vgpr_instructions = 191 +TA_PERF_SEL_image_sampler_1_op_burst = 192 +TA_PERF_SEL_image_sampler_2to3_op_burst = 193 +TA_PERF_SEL_image_sampler_4to7_op_burst = 194 +TA_PERF_SEL_image_sampler_ge8_op_burst = 195 +TA_PERF_SEL_image_linked_1_op_burst = 196 +TA_PERF_SEL_image_linked_2to3_op_burst = 197 +TA_PERF_SEL_image_linked_4to7_op_burst = 198 +TA_PERF_SEL_image_linked_ge8_op_burst = 199 +TA_PERF_SEL_image_bvh_1_op_burst = 200 +TA_PERF_SEL_image_bvh_2to3_op_burst = 201 +TA_PERF_SEL_image_bvh_4to7_op_burst = 202 +TA_PERF_SEL_image_bvh_ge8_op_burst = 203 +TA_PERF_SEL_image_nosampler_1_op_burst = 204 +TA_PERF_SEL_image_nosampler_2to3_op_burst = 205 +TA_PERF_SEL_image_nosampler_4to31_op_burst = 206 +TA_PERF_SEL_image_nosampler_ge32_op_burst = 207 +TA_PERF_SEL_buffer_flat_1_op_burst = 208 +TA_PERF_SEL_buffer_flat_2to3_op_burst = 209 +TA_PERF_SEL_buffer_flat_4to31_op_burst = 210 +TA_PERF_SEL_buffer_flat_ge32_op_burst = 211 +TA_PERF_SEL_write_1_op_burst = 212 +TA_PERF_SEL_write_2to3_op_burst = 213 +TA_PERF_SEL_write_4to31_op_burst = 214 +TA_PERF_SEL_write_ge32_op_burst = 215 +TA_PERF_SEL_ibubble_1_cycle_burst = 216 +TA_PERF_SEL_ibubble_2to3_cycle_burst = 217 +TA_PERF_SEL_ibubble_4to15_cycle_burst = 218 +TA_PERF_SEL_ibubble_16to31_cycle_burst = 219 +TA_PERF_SEL_ibubble_32to63_cycle_burst = 220 +TA_PERF_SEL_ibubble_ge64_cycle_burst = 221 +TA_PERF_SEL_sampler_clk_valid_cycles = 224 +TA_PERF_SEL_nonsampler_clk_valid_cycles = 225 +TA_PERF_SEL_buffer_flat_clk_valid_cycles = 226 +TA_PERF_SEL_write_data_clk_valid_cycles = 227 +TA_PERF_SEL_gradient_clk_valid_cycles = 228 +TA_PERF_SEL_lod_aniso_clk_valid_cycles = 229 +TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 230 +TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 231 +TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 232 +TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 233 +TA_PERF_SEL_aligner_clk_valid_cycles = 234 +TA_PERF_SEL_tcreq_clk_valid_cycles = 235 +TA_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_BC_SWIZZLE' +TEX_BC_SWIZZLE__enumvalues = { + 0: 'TEX_BC_Swizzle_XYZW', + 1: 'TEX_BC_Swizzle_XWYZ', + 2: 'TEX_BC_Swizzle_WZYX', + 3: 'TEX_BC_Swizzle_WXYZ', + 4: 'TEX_BC_Swizzle_ZYXW', + 5: 'TEX_BC_Swizzle_YXWZ', +} +TEX_BC_Swizzle_XYZW = 0 +TEX_BC_Swizzle_XWYZ = 1 +TEX_BC_Swizzle_WZYX = 2 +TEX_BC_Swizzle_WXYZ = 3 +TEX_BC_Swizzle_ZYXW = 4 +TEX_BC_Swizzle_YXWZ = 5 +TEX_BC_SWIZZLE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_BORDER_COLOR_TYPE' +TEX_BORDER_COLOR_TYPE__enumvalues = { + 0: 'TEX_BorderColor_TransparentBlack', + 1: 'TEX_BorderColor_OpaqueBlack', + 2: 'TEX_BorderColor_OpaqueWhite', + 3: 'TEX_BorderColor_Register', +} +TEX_BorderColor_TransparentBlack = 0 +TEX_BorderColor_OpaqueBlack = 1 +TEX_BorderColor_OpaqueWhite = 2 +TEX_BorderColor_Register = 3 +TEX_BORDER_COLOR_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CHROMA_KEY' +TEX_CHROMA_KEY__enumvalues = { + 0: 'TEX_ChromaKey_Disabled', + 1: 'TEX_ChromaKey_Kill', + 2: 'TEX_ChromaKey_Blend', + 3: 'TEX_ChromaKey_RESERVED_3', +} +TEX_ChromaKey_Disabled = 0 +TEX_ChromaKey_Kill = 1 +TEX_ChromaKey_Blend = 2 +TEX_ChromaKey_RESERVED_3 = 3 +TEX_CHROMA_KEY = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_CLAMP' +TEX_CLAMP__enumvalues = { + 0: 'TEX_Clamp_Repeat', + 1: 'TEX_Clamp_Mirror', + 2: 'TEX_Clamp_ClampToLast', + 3: 'TEX_Clamp_MirrorOnceToLast', + 4: 'TEX_Clamp_ClampHalfToBorder', + 5: 'TEX_Clamp_MirrorOnceHalfToBorder', + 6: 'TEX_Clamp_ClampToBorder', + 7: 'TEX_Clamp_MirrorOnceToBorder', +} +TEX_Clamp_Repeat = 0 +TEX_Clamp_Mirror = 1 +TEX_Clamp_ClampToLast = 2 +TEX_Clamp_MirrorOnceToLast = 3 +TEX_Clamp_ClampHalfToBorder = 4 +TEX_Clamp_MirrorOnceHalfToBorder = 5 +TEX_Clamp_ClampToBorder = 6 +TEX_Clamp_MirrorOnceToBorder = 7 +TEX_CLAMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_COORD_TYPE' +TEX_COORD_TYPE__enumvalues = { + 0: 'TEX_CoordType_Unnormalized', + 1: 'TEX_CoordType_Normalized', +} +TEX_CoordType_Unnormalized = 0 +TEX_CoordType_Normalized = 1 +TEX_COORD_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_DEPTH_COMPARE_FUNCTION' +TEX_DEPTH_COMPARE_FUNCTION__enumvalues = { + 0: 'TEX_DepthCompareFunction_Never', + 1: 'TEX_DepthCompareFunction_Less', + 2: 'TEX_DepthCompareFunction_Equal', + 3: 'TEX_DepthCompareFunction_LessEqual', + 4: 'TEX_DepthCompareFunction_Greater', + 5: 'TEX_DepthCompareFunction_NotEqual', + 6: 'TEX_DepthCompareFunction_GreaterEqual', + 7: 'TEX_DepthCompareFunction_Always', +} +TEX_DepthCompareFunction_Never = 0 +TEX_DepthCompareFunction_Less = 1 +TEX_DepthCompareFunction_Equal = 2 +TEX_DepthCompareFunction_LessEqual = 3 +TEX_DepthCompareFunction_Greater = 4 +TEX_DepthCompareFunction_NotEqual = 5 +TEX_DepthCompareFunction_GreaterEqual = 6 +TEX_DepthCompareFunction_Always = 7 +TEX_DEPTH_COMPARE_FUNCTION = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_FORMAT_COMP' +TEX_FORMAT_COMP__enumvalues = { + 0: 'TEX_FormatComp_Unsigned', + 1: 'TEX_FormatComp_Signed', + 2: 'TEX_FormatComp_UnsignedBiased', + 3: 'TEX_FormatComp_RESERVED_3', +} +TEX_FormatComp_Unsigned = 0 +TEX_FormatComp_Signed = 1 +TEX_FormatComp_UnsignedBiased = 2 +TEX_FormatComp_RESERVED_3 = 3 +TEX_FORMAT_COMP = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MAX_ANISO_RATIO' +TEX_MAX_ANISO_RATIO__enumvalues = { + 0: 'TEX_MaxAnisoRatio_1to1', + 1: 'TEX_MaxAnisoRatio_2to1', + 2: 'TEX_MaxAnisoRatio_4to1', + 3: 'TEX_MaxAnisoRatio_8to1', + 4: 'TEX_MaxAnisoRatio_16to1', + 5: 'TEX_MaxAnisoRatio_RESERVED_5', + 6: 'TEX_MaxAnisoRatio_RESERVED_6', + 7: 'TEX_MaxAnisoRatio_RESERVED_7', +} +TEX_MaxAnisoRatio_1to1 = 0 +TEX_MaxAnisoRatio_2to1 = 1 +TEX_MaxAnisoRatio_4to1 = 2 +TEX_MaxAnisoRatio_8to1 = 3 +TEX_MaxAnisoRatio_16to1 = 4 +TEX_MaxAnisoRatio_RESERVED_5 = 5 +TEX_MaxAnisoRatio_RESERVED_6 = 6 +TEX_MaxAnisoRatio_RESERVED_7 = 7 +TEX_MAX_ANISO_RATIO = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_MIP_FILTER' +TEX_MIP_FILTER__enumvalues = { + 0: 'TEX_MipFilter_None', + 1: 'TEX_MipFilter_Point', + 2: 'TEX_MipFilter_Linear', + 3: 'TEX_MipFilter_Point_Aniso_Adj', +} +TEX_MipFilter_None = 0 +TEX_MipFilter_Point = 1 +TEX_MipFilter_Linear = 2 +TEX_MipFilter_Point_Aniso_Adj = 3 +TEX_MIP_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_REQUEST_SIZE' +TEX_REQUEST_SIZE__enumvalues = { + 0: 'TEX_RequestSize_32B', + 1: 'TEX_RequestSize_64B', + 2: 'TEX_RequestSize_128B', + 3: 'TEX_RequestSize_2X64B', +} +TEX_RequestSize_32B = 0 +TEX_RequestSize_64B = 1 +TEX_RequestSize_128B = 2 +TEX_RequestSize_2X64B = 3 +TEX_REQUEST_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_SAMPLER_TYPE' +TEX_SAMPLER_TYPE__enumvalues = { + 0: 'TEX_SamplerType_Invalid', + 1: 'TEX_SamplerType_Valid', +} +TEX_SamplerType_Invalid = 0 +TEX_SamplerType_Valid = 1 +TEX_SAMPLER_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_XY_FILTER' +TEX_XY_FILTER__enumvalues = { + 0: 'TEX_XYFilter_Point', + 1: 'TEX_XYFilter_Linear', + 2: 'TEX_XYFilter_AnisoPoint', + 3: 'TEX_XYFilter_AnisoLinear', +} +TEX_XYFilter_Point = 0 +TEX_XYFilter_Linear = 1 +TEX_XYFilter_AnisoPoint = 2 +TEX_XYFilter_AnisoLinear = 3 +TEX_XY_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TEX_Z_FILTER' +TEX_Z_FILTER__enumvalues = { + 0: 'TEX_ZFilter_None', + 1: 'TEX_ZFilter_Point', + 2: 'TEX_ZFilter_Linear', + 3: 'TEX_ZFilter_RESERVED_3', +} +TEX_ZFilter_None = 0 +TEX_ZFilter_Point = 1 +TEX_ZFilter_Linear = 2 +TEX_ZFilter_RESERVED_3 = 3 +TEX_Z_FILTER = ctypes.c_uint32 # enum + +# values for enumeration 'TVX_TYPE' +TVX_TYPE__enumvalues = { + 0: 'TVX_Type_InvalidTextureResource', + 1: 'TVX_Type_InvalidVertexBuffer', + 2: 'TVX_Type_ValidTextureResource', + 3: 'TVX_Type_ValidVertexBuffer', +} +TVX_Type_InvalidTextureResource = 0 +TVX_Type_InvalidVertexBuffer = 1 +TVX_Type_ValidTextureResource = 2 +TVX_Type_ValidVertexBuffer = 3 +TVX_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TA_TC_ADDR_MODES' +TA_TC_ADDR_MODES__enumvalues = { + 0: 'TA_TC_ADDR_MODE_DEFAULT', + 1: 'TA_TC_ADDR_MODE_COMP0', + 2: 'TA_TC_ADDR_MODE_COMP1', + 3: 'TA_TC_ADDR_MODE_COMP2', + 4: 'TA_TC_ADDR_MODE_COMP3', + 5: 'TA_TC_ADDR_MODE_UNALIGNED', + 6: 'TA_TC_ADDR_MODE_BORDER_COLOR', +} +TA_TC_ADDR_MODE_DEFAULT = 0 +TA_TC_ADDR_MODE_COMP0 = 1 +TA_TC_ADDR_MODE_COMP1 = 2 +TA_TC_ADDR_MODE_COMP2 = 3 +TA_TC_ADDR_MODE_COMP3 = 4 +TA_TC_ADDR_MODE_UNALIGNED = 5 +TA_TC_ADDR_MODE_BORDER_COLOR = 6 +TA_TC_ADDR_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TA_TC_REQ_MODES' +TA_TC_REQ_MODES__enumvalues = { + 0: 'TA_TC_REQ_MODE_BORDER', + 1: 'TA_TC_REQ_MODE_TEX2', + 2: 'TA_TC_REQ_MODE_TEX1', + 3: 'TA_TC_REQ_MODE_TEX0', + 4: 'TA_TC_REQ_MODE_NORMAL', + 5: 'TA_TC_REQ_MODE_DWORD', + 6: 'TA_TC_REQ_MODE_BYTE', + 7: 'TA_TC_REQ_MODE_BYTE_NV', +} +TA_TC_REQ_MODE_BORDER = 0 +TA_TC_REQ_MODE_TEX2 = 1 +TA_TC_REQ_MODE_TEX1 = 2 +TA_TC_REQ_MODE_TEX0 = 3 +TA_TC_REQ_MODE_NORMAL = 4 +TA_TC_REQ_MODE_DWORD = 5 +TA_TC_REQ_MODE_BYTE = 6 +TA_TC_REQ_MODE_BYTE_NV = 7 +TA_TC_REQ_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_POLICIES' +TCP_CACHE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_POLICY_MISS_LRU', + 1: 'TCP_CACHE_POLICY_MISS_EVICT', + 2: 'TCP_CACHE_POLICY_HIT_LRU', + 3: 'TCP_CACHE_POLICY_HIT_EVICT', +} +TCP_CACHE_POLICY_MISS_LRU = 0 +TCP_CACHE_POLICY_MISS_EVICT = 1 +TCP_CACHE_POLICY_HIT_LRU = 2 +TCP_CACHE_POLICY_HIT_EVICT = 3 +TCP_CACHE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_CACHE_STORE_POLICIES' +TCP_CACHE_STORE_POLICIES__enumvalues = { + 0: 'TCP_CACHE_STORE_POLICY_WT_LRU', + 1: 'TCP_CACHE_STORE_POLICY_WT_EVICT', +} +TCP_CACHE_STORE_POLICY_WT_LRU = 0 +TCP_CACHE_STORE_POLICY_WT_EVICT = 1 +TCP_CACHE_STORE_POLICIES = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_DATA_SEL' +TCP_DSM_DATA_SEL__enumvalues = { + 0: 'TCP_DSM_DISABLE', + 1: 'TCP_DSM_SEL0', + 2: 'TCP_DSM_SEL1', + 3: 'TCP_DSM_SEL_BOTH', +} +TCP_DSM_DISABLE = 0 +TCP_DSM_SEL0 = 1 +TCP_DSM_SEL1 = 2 +TCP_DSM_SEL_BOTH = 3 +TCP_DSM_DATA_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_INJECT_SEL' +TCP_DSM_INJECT_SEL__enumvalues = { + 0: 'TCP_DSM_INJECT_SEL0', + 1: 'TCP_DSM_INJECT_SEL1', + 2: 'TCP_DSM_INJECT_SEL2', + 3: 'TCP_DSM_INJECT_SEL3', +} +TCP_DSM_INJECT_SEL0 = 0 +TCP_DSM_INJECT_SEL1 = 1 +TCP_DSM_INJECT_SEL2 = 2 +TCP_DSM_INJECT_SEL3 = 3 +TCP_DSM_INJECT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_DSM_SINGLE_WRITE' +TCP_DSM_SINGLE_WRITE__enumvalues = { + 0: 'TCP_DSM_SINGLE_WRITE_DIS', + 1: 'TCP_DSM_SINGLE_WRITE_EN', +} +TCP_DSM_SINGLE_WRITE_DIS = 0 +TCP_DSM_SINGLE_WRITE_EN = 1 +TCP_DSM_SINGLE_WRITE = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_OPCODE_TYPE' +TCP_OPCODE_TYPE__enumvalues = { + 0: 'TCP_OPCODE_READ', + 1: 'TCP_OPCODE_WRITE', + 2: 'TCP_OPCODE_ATOMIC', + 3: 'TCP_OPCODE_INV', + 4: 'TCP_OPCODE_ATOMIC_CMPSWAP', + 5: 'TCP_OPCODE_SAMPLER', + 6: 'TCP_OPCODE_LOAD', + 7: 'TCP_OPCODE_GATHERH', +} +TCP_OPCODE_READ = 0 +TCP_OPCODE_WRITE = 1 +TCP_OPCODE_ATOMIC = 2 +TCP_OPCODE_INV = 3 +TCP_OPCODE_ATOMIC_CMPSWAP = 4 +TCP_OPCODE_SAMPLER = 5 +TCP_OPCODE_LOAD = 6 +TCP_OPCODE_GATHERH = 7 +TCP_OPCODE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_PERFCOUNT_SELECT' +TCP_PERFCOUNT_SELECT__enumvalues = { + 0: 'TCP_PERF_SEL_GATE_EN1', + 1: 'TCP_PERF_SEL_GATE_EN2', + 2: 'TCP_PERF_SEL_TA_REQ', + 3: 'TCP_PERF_SEL_TA_REQ_STATE_READ', + 4: 'TCP_PERF_SEL_TA_REQ_READ', + 5: 'TCP_PERF_SEL_TA_REQ_WRITE', + 6: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', + 7: 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', + 8: 'TCP_PERF_SEL_TA_REQ_GL0_INV', + 9: 'TCP_PERF_SEL_REQ', + 10: 'TCP_PERF_SEL_REQ_READ', + 11: 'TCP_PERF_SEL_REQ_READ_HIT_EVICT', + 12: 'TCP_PERF_SEL_REQ_READ_HIT_LRU', + 13: 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', + 14: 'TCP_PERF_SEL_REQ_WRITE', + 15: 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', + 16: 'TCP_PERF_SEL_REQ_WRITE_MISS_LRU', + 17: 'TCP_PERF_SEL_REQ_NON_READ', + 18: 'TCP_PERF_SEL_REQ_MISS', + 19: 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', + 20: 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', + 21: 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', + 22: 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', + 23: 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', + 24: 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', + 25: 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', + 26: 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', + 27: 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', + 28: 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', + 29: 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', + 30: 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', + 31: 'TCP_PERF_SEL_GL1_REQ_READ', + 32: 'TCP_PERF_SEL_GL1_REQ_READ_128B', + 33: 'TCP_PERF_SEL_GL1_REQ_READ_64B', + 34: 'TCP_PERF_SEL_GL1_REQ_WRITE', + 35: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', + 36: 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', + 37: 'TCP_PERF_SEL_GL1_READ_LATENCY', + 38: 'TCP_PERF_SEL_GL1_WRITE_LATENCY', + 39: 'TCP_PERF_SEL_TCP_LATENCY', + 40: 'TCP_PERF_SEL_TCP_TA_REQ_STALL', + 41: 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', + 42: 'TCP_PERF_SEL_DATA_FIFO_STALL', + 43: 'TCP_PERF_SEL_LOD_STALL', + 44: 'TCP_PERF_SEL_POWER_STALL', + 45: 'TCP_PERF_SEL_ALLOC_STALL', + 46: 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', + 47: 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', + 48: 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', + 49: 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', + 50: 'TCP_PERF_SEL_LFIFO_STALL', + 51: 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', + 52: 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', + 53: 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', + 54: 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', + 55: 'TCP_PERF_SEL_GL1_PENDING_STALL', + 56: 'TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL', + 57: 'TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL', + 58: 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', + 59: 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', + 60: 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', + 61: 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', + 62: 'TCP_PERF_SEL_TD_TCP_STALL', +} +TCP_PERF_SEL_GATE_EN1 = 0 +TCP_PERF_SEL_GATE_EN2 = 1 +TCP_PERF_SEL_TA_REQ = 2 +TCP_PERF_SEL_TA_REQ_STATE_READ = 3 +TCP_PERF_SEL_TA_REQ_READ = 4 +TCP_PERF_SEL_TA_REQ_WRITE = 5 +TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 6 +TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 7 +TCP_PERF_SEL_TA_REQ_GL0_INV = 8 +TCP_PERF_SEL_REQ = 9 +TCP_PERF_SEL_REQ_READ = 10 +TCP_PERF_SEL_REQ_READ_HIT_EVICT = 11 +TCP_PERF_SEL_REQ_READ_HIT_LRU = 12 +TCP_PERF_SEL_REQ_READ_MISS_EVICT = 13 +TCP_PERF_SEL_REQ_WRITE = 14 +TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 15 +TCP_PERF_SEL_REQ_WRITE_MISS_LRU = 16 +TCP_PERF_SEL_REQ_NON_READ = 17 +TCP_PERF_SEL_REQ_MISS = 18 +TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 19 +TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 20 +TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 21 +TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 22 +TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 23 +TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 24 +TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 25 +TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 26 +TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 27 +TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 28 +TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 29 +TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 30 +TCP_PERF_SEL_GL1_REQ_READ = 31 +TCP_PERF_SEL_GL1_REQ_READ_128B = 32 +TCP_PERF_SEL_GL1_REQ_READ_64B = 33 +TCP_PERF_SEL_GL1_REQ_WRITE = 34 +TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 35 +TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 36 +TCP_PERF_SEL_GL1_READ_LATENCY = 37 +TCP_PERF_SEL_GL1_WRITE_LATENCY = 38 +TCP_PERF_SEL_TCP_LATENCY = 39 +TCP_PERF_SEL_TCP_TA_REQ_STALL = 40 +TCP_PERF_SEL_TA_TCP_REQ_STARVE = 41 +TCP_PERF_SEL_DATA_FIFO_STALL = 42 +TCP_PERF_SEL_LOD_STALL = 43 +TCP_PERF_SEL_POWER_STALL = 44 +TCP_PERF_SEL_ALLOC_STALL = 45 +TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 46 +TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 47 +TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 48 +TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 49 +TCP_PERF_SEL_LFIFO_STALL = 50 +TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 51 +TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 52 +TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 53 +TCP_PERF_SEL_GL1_GRANT_READ_STALL = 54 +TCP_PERF_SEL_GL1_PENDING_STALL = 55 +TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL = 56 +TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL = 57 +TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 58 +TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 59 +TCP_PERF_SEL_READ_DATACONFLICT_STALL = 60 +TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 61 +TCP_PERF_SEL_TD_TCP_STALL = 62 +TCP_PERFCOUNT_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'TCP_WATCH_MODES' +TCP_WATCH_MODES__enumvalues = { + 0: 'TCP_WATCH_MODE_READ', + 1: 'TCP_WATCH_MODE_NONREAD', + 2: 'TCP_WATCH_MODE_ATOMIC', + 3: 'TCP_WATCH_MODE_ALL', +} +TCP_WATCH_MODE_READ = 0 +TCP_WATCH_MODE_NONREAD = 1 +TCP_WATCH_MODE_ATOMIC = 2 +TCP_WATCH_MODE_ALL = 3 +TCP_WATCH_MODES = ctypes.c_uint32 # enum + +# values for enumeration 'TD_PERFCOUNT_SEL' +TD_PERFCOUNT_SEL__enumvalues = { + 0: 'TD_PERF_SEL_none', + 1: 'TD_PERF_SEL_td_busy', + 2: 'TD_PERF_SEL_input_busy', + 3: 'TD_PERF_SEL_sampler_lerp_busy', + 4: 'TD_PERF_SEL_sampler_out_busy', + 5: 'TD_PERF_SEL_nofilter_busy', + 6: 'TD_PERF_SEL_ray_tracing_bvh4_busy', + 7: 'TD_PERF_SEL_sampler_core_sclk_en', + 8: 'TD_PERF_SEL_sampler_preformatter_sclk_en', + 9: 'TD_PERF_SEL_sampler_bilerp_sclk_en', + 10: 'TD_PERF_SEL_sampler_bypass_sclk_en', + 11: 'TD_PERF_SEL_sampler_minmax_sclk_en', + 12: 'TD_PERF_SEL_sampler_accum_sclk_en', + 13: 'TD_PERF_SEL_sampler_format_flt_sclk_en', + 14: 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', + 15: 'TD_PERF_SEL_sampler_out_sclk_en', + 16: 'TD_PERF_SEL_nofilter_sclk_en', + 17: 'TD_PERF_SEL_nofilter_d32_sclk_en', + 18: 'TD_PERF_SEL_nofilter_d16_sclk_en', + 22: 'TD_PERF_SEL_ray_tracing_bvh4_sclk_en', + 23: 'TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en', + 24: 'TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en', + 25: 'TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en', + 26: 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', + 27: 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', + 28: 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', + 29: 'TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off', + 30: 'TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off', + 31: 'TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off', + 32: 'TD_PERF_SEL_core_state_ram_max_cnt', + 33: 'TD_PERF_SEL_core_state_rams_read', + 34: 'TD_PERF_SEL_weight_data_rams_read', + 35: 'TD_PERF_SEL_reference_data_rams_read', + 36: 'TD_PERF_SEL_tc_td_ram_fifo_full', + 37: 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', + 38: 'TD_PERF_SEL_tc_td_data_fifo_full', + 39: 'TD_PERF_SEL_input_state_fifo_full', + 40: 'TD_PERF_SEL_ta_data_stall', + 41: 'TD_PERF_SEL_tc_data_stall', + 42: 'TD_PERF_SEL_tc_ram_stall', + 43: 'TD_PERF_SEL_lds_stall', + 44: 'TD_PERF_SEL_sampler_pkr_full', + 45: 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', + 46: 'TD_PERF_SEL_nofilter_pkr_full', + 47: 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', + 48: 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full', + 49: 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb', + 50: 'TD_PERF_SEL_gather4_instr', + 51: 'TD_PERF_SEL_gather4h_instr', + 54: 'TD_PERF_SEL_sample_instr', + 55: 'TD_PERF_SEL_sample_c_instr', + 56: 'TD_PERF_SEL_load_instr', + 57: 'TD_PERF_SEL_ldfptr_instr', + 58: 'TD_PERF_SEL_write_ack_instr', + 59: 'TD_PERF_SEL_d16_en_instr', + 60: 'TD_PERF_SEL_bypassLerp_instr', + 61: 'TD_PERF_SEL_min_max_filter_instr', + 62: 'TD_PERF_SEL_one_comp_return_instr', + 63: 'TD_PERF_SEL_two_comp_return_instr', + 64: 'TD_PERF_SEL_three_comp_return_instr', + 65: 'TD_PERF_SEL_four_comp_return_instr', + 66: 'TD_PERF_SEL_user_defined_border', + 67: 'TD_PERF_SEL_white_border', + 68: 'TD_PERF_SEL_opaque_black_border', + 69: 'TD_PERF_SEL_lod_warn_from_ta', + 70: 'TD_PERF_SEL_instruction_dest_is_lds', + 71: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', + 72: 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', + 73: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', + 74: 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', + 75: 'TD_PERF_SEL_out_of_order_instr', + 76: 'TD_PERF_SEL_total_num_instr', + 77: 'TD_PERF_SEL_total_num_instr_with_perf_wdw', + 78: 'TD_PERF_SEL_total_num_sampler_instr', + 79: 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', + 80: 'TD_PERF_SEL_total_num_nofilter_instr', + 81: 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', + 82: 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr', + 83: 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw', + 84: 'TD_PERF_SEL_mixmode_instr', + 85: 'TD_PERF_SEL_mixmode_resource', + 86: 'TD_PERF_SEL_status_packet', + 87: 'TD_PERF_SEL_address_cmd_poison', + 88: 'TD_PERF_SEL_data_poison', + 89: 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', + 90: 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', + 91: 'TD_PERF_SEL_done_scoreboard_not_empty', + 92: 'TD_PERF_SEL_done_scoreboard_is_full', + 93: 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', + 94: 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', + 95: 'TD_PERF_SEL_nofilter_formatters_turned_on', + 96: 'TD_PERF_SEL_nofilter_insert_extra_comps', + 97: 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', + 98: 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', + 99: 'TD_PERF_SEL_msaa_load_instr', + 100: 'TD_PERF_SEL_blend_prt_with_prt_default_0', + 101: 'TD_PERF_SEL_blend_prt_with_prt_default_1', + 102: 'TD_PERF_SEL_resmap_instr', + 103: 'TD_PERF_SEL_prt_ack_instr', + 104: 'TD_PERF_SEL_resmap_with_volume_filtering', + 105: 'TD_PERF_SEL_resmap_with_aniso_filtering', + 106: 'TD_PERF_SEL_resmap_with_no_more_filtering', + 107: 'TD_PERF_SEL_resmap_with_cubemap_corner', + 108: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0', + 109: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1', + 110: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2', + 111: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4', + 112: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8', + 113: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16', + 114: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31', + 115: 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32', + 116: 'TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node', + 117: 'TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node', + 118: 'TD_PERF_SEL_ray_tracing_bvh4_tri_node', + 119: 'TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node', + 120: 'TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node', + 121: 'TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node', + 122: 'TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node', + 123: 'TD_PERF_SEL_ray_tracing_bvh4_box_sort_en', + 124: 'TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero', + 125: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx', + 126: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx', + 127: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan', + 128: 'TD_PERF_SEL_ray_tracing_bvh4_num_box_misses', + 129: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses', + 130: 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers', + 131: 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', + 132: 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', + 133: 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', + 134: 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', + 135: 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', + 136: 'TD_PERF_SEL_burst_bin_sampler_1', + 137: 'TD_PERF_SEL_burst_bin_sampler_2to8', + 138: 'TD_PERF_SEL_burst_bin_sampler_9to16', + 139: 'TD_PERF_SEL_burst_bin_sampler_gt16', + 140: 'TD_PERF_SEL_burst_bin_gather_1', + 141: 'TD_PERF_SEL_burst_bin_gather_2to8', + 142: 'TD_PERF_SEL_burst_bin_gather_9to16', + 143: 'TD_PERF_SEL_burst_bin_gather_gt16', + 144: 'TD_PERF_SEL_burst_bin_nofilter_1', + 145: 'TD_PERF_SEL_burst_bin_nofilter_2to4', + 146: 'TD_PERF_SEL_burst_bin_nofilter_5to7', + 147: 'TD_PERF_SEL_burst_bin_nofilter_8to16', + 148: 'TD_PERF_SEL_burst_bin_nofilter_gt16', + 149: 'TD_PERF_SEL_burst_bin_bvh4_1', + 150: 'TD_PERF_SEL_burst_bin_bvh4_2to8', + 151: 'TD_PERF_SEL_burst_bin_bvh4_9to16', + 152: 'TD_PERF_SEL_burst_bin_bvh4_gt16', + 153: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_1', + 154: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4', + 155: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7', + 156: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16', + 157: 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16', + 158: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1', + 159: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8', + 160: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16', + 161: 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16', + 162: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1', + 163: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8', + 164: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16', + 165: 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16', + 166: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1', + 167: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8', + 168: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16', + 169: 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16', + 170: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', + 171: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', + 172: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', + 173: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', + 174: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', + 175: 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', + 176: 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', + 177: 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', + 178: 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', + 179: 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', + 180: 'TD_PERF_SEL_preempting_nofilter_max_cnt', + 181: 'TD_PERF_SEL_sampler_lerp0_active', + 182: 'TD_PERF_SEL_sampler_lerp1_active', + 183: 'TD_PERF_SEL_sampler_lerp2_active', + 184: 'TD_PERF_SEL_sampler_lerp3_active', + 185: 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', + 186: 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', + 187: 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', + 188: 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', + 189: 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', + 190: 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', + 191: 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', + 192: 'TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt', +} +TD_PERF_SEL_none = 0 +TD_PERF_SEL_td_busy = 1 +TD_PERF_SEL_input_busy = 2 +TD_PERF_SEL_sampler_lerp_busy = 3 +TD_PERF_SEL_sampler_out_busy = 4 +TD_PERF_SEL_nofilter_busy = 5 +TD_PERF_SEL_ray_tracing_bvh4_busy = 6 +TD_PERF_SEL_sampler_core_sclk_en = 7 +TD_PERF_SEL_sampler_preformatter_sclk_en = 8 +TD_PERF_SEL_sampler_bilerp_sclk_en = 9 +TD_PERF_SEL_sampler_bypass_sclk_en = 10 +TD_PERF_SEL_sampler_minmax_sclk_en = 11 +TD_PERF_SEL_sampler_accum_sclk_en = 12 +TD_PERF_SEL_sampler_format_flt_sclk_en = 13 +TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 14 +TD_PERF_SEL_sampler_out_sclk_en = 15 +TD_PERF_SEL_nofilter_sclk_en = 16 +TD_PERF_SEL_nofilter_d32_sclk_en = 17 +TD_PERF_SEL_nofilter_d16_sclk_en = 18 +TD_PERF_SEL_ray_tracing_bvh4_sclk_en = 22 +TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en = 23 +TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en = 24 +TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en = 25 +TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 26 +TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 27 +TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 28 +TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off = 29 +TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off = 30 +TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off = 31 +TD_PERF_SEL_core_state_ram_max_cnt = 32 +TD_PERF_SEL_core_state_rams_read = 33 +TD_PERF_SEL_weight_data_rams_read = 34 +TD_PERF_SEL_reference_data_rams_read = 35 +TD_PERF_SEL_tc_td_ram_fifo_full = 36 +TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 37 +TD_PERF_SEL_tc_td_data_fifo_full = 38 +TD_PERF_SEL_input_state_fifo_full = 39 +TD_PERF_SEL_ta_data_stall = 40 +TD_PERF_SEL_tc_data_stall = 41 +TD_PERF_SEL_tc_ram_stall = 42 +TD_PERF_SEL_lds_stall = 43 +TD_PERF_SEL_sampler_pkr_full = 44 +TD_PERF_SEL_sampler_pkr_full_due_to_arb = 45 +TD_PERF_SEL_nofilter_pkr_full = 46 +TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 47 +TD_PERF_SEL_ray_tracing_bvh4_pkr_full = 48 +TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb = 49 +TD_PERF_SEL_gather4_instr = 50 +TD_PERF_SEL_gather4h_instr = 51 +TD_PERF_SEL_sample_instr = 54 +TD_PERF_SEL_sample_c_instr = 55 +TD_PERF_SEL_load_instr = 56 +TD_PERF_SEL_ldfptr_instr = 57 +TD_PERF_SEL_write_ack_instr = 58 +TD_PERF_SEL_d16_en_instr = 59 +TD_PERF_SEL_bypassLerp_instr = 60 +TD_PERF_SEL_min_max_filter_instr = 61 +TD_PERF_SEL_one_comp_return_instr = 62 +TD_PERF_SEL_two_comp_return_instr = 63 +TD_PERF_SEL_three_comp_return_instr = 64 +TD_PERF_SEL_four_comp_return_instr = 65 +TD_PERF_SEL_user_defined_border = 66 +TD_PERF_SEL_white_border = 67 +TD_PERF_SEL_opaque_black_border = 68 +TD_PERF_SEL_lod_warn_from_ta = 69 +TD_PERF_SEL_instruction_dest_is_lds = 70 +TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 71 +TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 72 +TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 73 +TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 74 +TD_PERF_SEL_out_of_order_instr = 75 +TD_PERF_SEL_total_num_instr = 76 +TD_PERF_SEL_total_num_instr_with_perf_wdw = 77 +TD_PERF_SEL_total_num_sampler_instr = 78 +TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 79 +TD_PERF_SEL_total_num_nofilter_instr = 80 +TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 81 +TD_PERF_SEL_total_num_ray_tracing_bvh4_instr = 82 +TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw = 83 +TD_PERF_SEL_mixmode_instr = 84 +TD_PERF_SEL_mixmode_resource = 85 +TD_PERF_SEL_status_packet = 86 +TD_PERF_SEL_address_cmd_poison = 87 +TD_PERF_SEL_data_poison = 88 +TD_PERF_SEL_done_scoreboard_max_stored_cnt = 89 +TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 90 +TD_PERF_SEL_done_scoreboard_not_empty = 91 +TD_PERF_SEL_done_scoreboard_is_full = 92 +TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 93 +TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 94 +TD_PERF_SEL_nofilter_formatters_turned_on = 95 +TD_PERF_SEL_nofilter_insert_extra_comps = 96 +TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 97 +TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 98 +TD_PERF_SEL_msaa_load_instr = 99 +TD_PERF_SEL_blend_prt_with_prt_default_0 = 100 +TD_PERF_SEL_blend_prt_with_prt_default_1 = 101 +TD_PERF_SEL_resmap_instr = 102 +TD_PERF_SEL_prt_ack_instr = 103 +TD_PERF_SEL_resmap_with_volume_filtering = 104 +TD_PERF_SEL_resmap_with_aniso_filtering = 105 +TD_PERF_SEL_resmap_with_no_more_filtering = 106 +TD_PERF_SEL_resmap_with_cubemap_corner = 107 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0 = 108 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1 = 109 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2 = 110 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4 = 111 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8 = 112 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16 = 113 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31 = 114 +TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32 = 115 +TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node = 116 +TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node = 117 +TD_PERF_SEL_ray_tracing_bvh4_tri_node = 118 +TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node = 119 +TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node = 120 +TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node = 121 +TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node = 122 +TD_PERF_SEL_ray_tracing_bvh4_box_sort_en = 123 +TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero = 124 +TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx = 125 +TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx = 126 +TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan = 127 +TD_PERF_SEL_ray_tracing_bvh4_num_box_misses = 128 +TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses = 129 +TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers = 130 +TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 131 +TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 132 +TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 133 +TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 134 +TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 135 +TD_PERF_SEL_burst_bin_sampler_1 = 136 +TD_PERF_SEL_burst_bin_sampler_2to8 = 137 +TD_PERF_SEL_burst_bin_sampler_9to16 = 138 +TD_PERF_SEL_burst_bin_sampler_gt16 = 139 +TD_PERF_SEL_burst_bin_gather_1 = 140 +TD_PERF_SEL_burst_bin_gather_2to8 = 141 +TD_PERF_SEL_burst_bin_gather_9to16 = 142 +TD_PERF_SEL_burst_bin_gather_gt16 = 143 +TD_PERF_SEL_burst_bin_nofilter_1 = 144 +TD_PERF_SEL_burst_bin_nofilter_2to4 = 145 +TD_PERF_SEL_burst_bin_nofilter_5to7 = 146 +TD_PERF_SEL_burst_bin_nofilter_8to16 = 147 +TD_PERF_SEL_burst_bin_nofilter_gt16 = 148 +TD_PERF_SEL_burst_bin_bvh4_1 = 149 +TD_PERF_SEL_burst_bin_bvh4_2to8 = 150 +TD_PERF_SEL_burst_bin_bvh4_9to16 = 151 +TD_PERF_SEL_burst_bin_bvh4_gt16 = 152 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_1 = 153 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4 = 154 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7 = 155 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16 = 156 +TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16 = 157 +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1 = 158 +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8 = 159 +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16 = 160 +TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16 = 161 +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1 = 162 +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8 = 163 +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16 = 164 +TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16 = 165 +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1 = 166 +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8 = 167 +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16 = 168 +TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16 = 169 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 170 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 171 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 172 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 173 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 174 +TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 175 +TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 176 +TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 177 +TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 178 +TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 179 +TD_PERF_SEL_preempting_nofilter_max_cnt = 180 +TD_PERF_SEL_sampler_lerp0_active = 181 +TD_PERF_SEL_sampler_lerp1_active = 182 +TD_PERF_SEL_sampler_lerp2_active = 183 +TD_PERF_SEL_sampler_lerp3_active = 184 +TD_PERF_SEL_nofilter_total_num_comps_to_lds = 185 +TD_PERF_SEL_nofilter_byte_cycling_4cycles = 186 +TD_PERF_SEL_nofilter_byte_cycling_8cycles = 187 +TD_PERF_SEL_nofilter_byte_cycling_16cycles = 188 +TD_PERF_SEL_nofilter_dword_cycling_2cycles = 189 +TD_PERF_SEL_nofilter_dword_cycling_4cycles = 190 +TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 191 +TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt = 192 +TD_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL2A_PERF_SEL' +GL2A_PERF_SEL__enumvalues = { + 0: 'GL2A_PERF_SEL_NONE', + 1: 'GL2A_PERF_SEL_CYCLE', + 2: 'GL2A_PERF_SEL_BUSY', + 3: 'GL2A_PERF_SEL_REQ_GL2C0', + 4: 'GL2A_PERF_SEL_REQ_GL2C1', + 5: 'GL2A_PERF_SEL_REQ_GL2C2', + 6: 'GL2A_PERF_SEL_REQ_GL2C3', + 7: 'GL2A_PERF_SEL_REQ_GL2C4', + 8: 'GL2A_PERF_SEL_REQ_GL2C5', + 9: 'GL2A_PERF_SEL_REQ_GL2C6', + 10: 'GL2A_PERF_SEL_REQ_GL2C7', + 11: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', + 12: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', + 13: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', + 14: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', + 15: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', + 16: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', + 17: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', + 18: 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', + 19: 'GL2A_PERF_SEL_REQ_BURST_GL2C0', + 20: 'GL2A_PERF_SEL_REQ_BURST_GL2C1', + 21: 'GL2A_PERF_SEL_REQ_BURST_GL2C2', + 22: 'GL2A_PERF_SEL_REQ_BURST_GL2C3', + 23: 'GL2A_PERF_SEL_REQ_BURST_GL2C4', + 24: 'GL2A_PERF_SEL_REQ_BURST_GL2C5', + 25: 'GL2A_PERF_SEL_REQ_BURST_GL2C6', + 26: 'GL2A_PERF_SEL_REQ_BURST_GL2C7', + 27: 'GL2A_PERF_SEL_REQ_STALL_GL2C0', + 28: 'GL2A_PERF_SEL_REQ_STALL_GL2C1', + 29: 'GL2A_PERF_SEL_REQ_STALL_GL2C2', + 30: 'GL2A_PERF_SEL_REQ_STALL_GL2C3', + 31: 'GL2A_PERF_SEL_REQ_STALL_GL2C4', + 32: 'GL2A_PERF_SEL_REQ_STALL_GL2C5', + 33: 'GL2A_PERF_SEL_REQ_STALL_GL2C6', + 34: 'GL2A_PERF_SEL_REQ_STALL_GL2C7', + 35: 'GL2A_PERF_SEL_RTN_STALL_GL2C0', + 36: 'GL2A_PERF_SEL_RTN_STALL_GL2C1', + 37: 'GL2A_PERF_SEL_RTN_STALL_GL2C2', + 38: 'GL2A_PERF_SEL_RTN_STALL_GL2C3', + 39: 'GL2A_PERF_SEL_RTN_STALL_GL2C4', + 40: 'GL2A_PERF_SEL_RTN_STALL_GL2C5', + 41: 'GL2A_PERF_SEL_RTN_STALL_GL2C6', + 42: 'GL2A_PERF_SEL_RTN_STALL_GL2C7', + 43: 'GL2A_PERF_SEL_RTN_CLIENT0', + 44: 'GL2A_PERF_SEL_RTN_CLIENT1', + 45: 'GL2A_PERF_SEL_RTN_CLIENT2', + 46: 'GL2A_PERF_SEL_RTN_CLIENT3', + 47: 'GL2A_PERF_SEL_RTN_CLIENT4', + 48: 'GL2A_PERF_SEL_RTN_CLIENT5', + 49: 'GL2A_PERF_SEL_RTN_CLIENT6', + 50: 'GL2A_PERF_SEL_RTN_CLIENT7', + 51: 'GL2A_PERF_SEL_RTN_CLIENT8', + 52: 'GL2A_PERF_SEL_RTN_CLIENT9', + 53: 'GL2A_PERF_SEL_RTN_CLIENT10', + 54: 'GL2A_PERF_SEL_RTN_CLIENT11', + 55: 'GL2A_PERF_SEL_RTN_CLIENT12', + 56: 'GL2A_PERF_SEL_RTN_CLIENT13', + 57: 'GL2A_PERF_SEL_RTN_CLIENT14', + 58: 'GL2A_PERF_SEL_RTN_CLIENT15', + 59: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', + 60: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', + 61: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', + 62: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', + 63: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', + 64: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', + 65: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', + 66: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', + 67: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', + 68: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', + 69: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', + 70: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', + 71: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', + 72: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', + 73: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', + 74: 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', + 75: 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', + 76: 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', + 77: 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', + 78: 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', + 79: 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', + 80: 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', + 81: 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', + 82: 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', + 83: 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', + 84: 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', + 85: 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', + 86: 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', + 87: 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', + 88: 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', + 89: 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', + 90: 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', + 91: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', + 92: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', + 93: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', + 94: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', + 95: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', + 96: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', + 97: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', + 98: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', + 99: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', + 100: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', + 101: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', + 103: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', + 104: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', + 105: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', + 106: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', + 107: 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', +} +GL2A_PERF_SEL_NONE = 0 +GL2A_PERF_SEL_CYCLE = 1 +GL2A_PERF_SEL_BUSY = 2 +GL2A_PERF_SEL_REQ_GL2C0 = 3 +GL2A_PERF_SEL_REQ_GL2C1 = 4 +GL2A_PERF_SEL_REQ_GL2C2 = 5 +GL2A_PERF_SEL_REQ_GL2C3 = 6 +GL2A_PERF_SEL_REQ_GL2C4 = 7 +GL2A_PERF_SEL_REQ_GL2C5 = 8 +GL2A_PERF_SEL_REQ_GL2C6 = 9 +GL2A_PERF_SEL_REQ_GL2C7 = 10 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 11 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 12 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 13 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 14 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 15 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 16 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 17 +GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 18 +GL2A_PERF_SEL_REQ_BURST_GL2C0 = 19 +GL2A_PERF_SEL_REQ_BURST_GL2C1 = 20 +GL2A_PERF_SEL_REQ_BURST_GL2C2 = 21 +GL2A_PERF_SEL_REQ_BURST_GL2C3 = 22 +GL2A_PERF_SEL_REQ_BURST_GL2C4 = 23 +GL2A_PERF_SEL_REQ_BURST_GL2C5 = 24 +GL2A_PERF_SEL_REQ_BURST_GL2C6 = 25 +GL2A_PERF_SEL_REQ_BURST_GL2C7 = 26 +GL2A_PERF_SEL_REQ_STALL_GL2C0 = 27 +GL2A_PERF_SEL_REQ_STALL_GL2C1 = 28 +GL2A_PERF_SEL_REQ_STALL_GL2C2 = 29 +GL2A_PERF_SEL_REQ_STALL_GL2C3 = 30 +GL2A_PERF_SEL_REQ_STALL_GL2C4 = 31 +GL2A_PERF_SEL_REQ_STALL_GL2C5 = 32 +GL2A_PERF_SEL_REQ_STALL_GL2C6 = 33 +GL2A_PERF_SEL_REQ_STALL_GL2C7 = 34 +GL2A_PERF_SEL_RTN_STALL_GL2C0 = 35 +GL2A_PERF_SEL_RTN_STALL_GL2C1 = 36 +GL2A_PERF_SEL_RTN_STALL_GL2C2 = 37 +GL2A_PERF_SEL_RTN_STALL_GL2C3 = 38 +GL2A_PERF_SEL_RTN_STALL_GL2C4 = 39 +GL2A_PERF_SEL_RTN_STALL_GL2C5 = 40 +GL2A_PERF_SEL_RTN_STALL_GL2C6 = 41 +GL2A_PERF_SEL_RTN_STALL_GL2C7 = 42 +GL2A_PERF_SEL_RTN_CLIENT0 = 43 +GL2A_PERF_SEL_RTN_CLIENT1 = 44 +GL2A_PERF_SEL_RTN_CLIENT2 = 45 +GL2A_PERF_SEL_RTN_CLIENT3 = 46 +GL2A_PERF_SEL_RTN_CLIENT4 = 47 +GL2A_PERF_SEL_RTN_CLIENT5 = 48 +GL2A_PERF_SEL_RTN_CLIENT6 = 49 +GL2A_PERF_SEL_RTN_CLIENT7 = 50 +GL2A_PERF_SEL_RTN_CLIENT8 = 51 +GL2A_PERF_SEL_RTN_CLIENT9 = 52 +GL2A_PERF_SEL_RTN_CLIENT10 = 53 +GL2A_PERF_SEL_RTN_CLIENT11 = 54 +GL2A_PERF_SEL_RTN_CLIENT12 = 55 +GL2A_PERF_SEL_RTN_CLIENT13 = 56 +GL2A_PERF_SEL_RTN_CLIENT14 = 57 +GL2A_PERF_SEL_RTN_CLIENT15 = 58 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 59 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 60 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 61 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 62 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 63 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 64 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 65 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 66 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 67 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 68 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 69 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 70 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 71 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 72 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 73 +GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 74 +GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 75 +GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 76 +GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 77 +GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 78 +GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 79 +GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 80 +GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 81 +GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 82 +GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 83 +GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 84 +GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 85 +GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 86 +GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 87 +GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 88 +GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 89 +GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 90 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 91 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 92 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 93 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 94 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 95 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 96 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 97 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 98 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 99 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 100 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 101 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 103 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 104 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 105 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 106 +GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 107 +GL2A_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GL2C_PERF_SEL' +GL2C_PERF_SEL__enumvalues = { + 0: 'GL2C_PERF_SEL_NONE', + 1: 'GL2C_PERF_SEL_CYCLE', + 2: 'GL2C_PERF_SEL_BUSY', + 3: 'GL2C_PERF_SEL_REQ', + 4: 'GL2C_PERF_SEL_VOL_REQ', + 5: 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', + 6: 'GL2C_PERF_SEL_READ', + 7: 'GL2C_PERF_SEL_WRITE', + 8: 'GL2C_PERF_SEL_ATOMIC', + 9: 'GL2C_PERF_SEL_NOP_ACK', + 10: 'GL2C_PERF_SEL_NOP_RTN0', + 11: 'GL2C_PERF_SEL_PROBE', + 12: 'GL2C_PERF_SEL_PROBE_ALL', + 13: 'GL2C_PERF_SEL_INTERNAL_PROBE', + 14: 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', + 15: 'GL2C_PERF_SEL_METADATA_READ_REQ', + 16: 'GL2C_PERF_SEL_CLIENT0_REQ', + 17: 'GL2C_PERF_SEL_CLIENT1_REQ', + 18: 'GL2C_PERF_SEL_CLIENT2_REQ', + 19: 'GL2C_PERF_SEL_CLIENT3_REQ', + 20: 'GL2C_PERF_SEL_CLIENT4_REQ', + 21: 'GL2C_PERF_SEL_CLIENT5_REQ', + 22: 'GL2C_PERF_SEL_CLIENT6_REQ', + 23: 'GL2C_PERF_SEL_CLIENT7_REQ', + 24: 'GL2C_PERF_SEL_CLIENT8_REQ', + 25: 'GL2C_PERF_SEL_CLIENT9_REQ', + 26: 'GL2C_PERF_SEL_CLIENT10_REQ', + 27: 'GL2C_PERF_SEL_CLIENT11_REQ', + 28: 'GL2C_PERF_SEL_CLIENT12_REQ', + 29: 'GL2C_PERF_SEL_CLIENT13_REQ', + 30: 'GL2C_PERF_SEL_CLIENT14_REQ', + 31: 'GL2C_PERF_SEL_CLIENT15_REQ', + 32: 'GL2C_PERF_SEL_C_RW_S_REQ', + 33: 'GL2C_PERF_SEL_C_RW_US_REQ', + 34: 'GL2C_PERF_SEL_C_RO_S_REQ', + 35: 'GL2C_PERF_SEL_C_RO_US_REQ', + 36: 'GL2C_PERF_SEL_UC_REQ', + 37: 'GL2C_PERF_SEL_LRU_REQ', + 38: 'GL2C_PERF_SEL_STREAM_REQ', + 39: 'GL2C_PERF_SEL_BYPASS_REQ', + 40: 'GL2C_PERF_SEL_NOA_REQ', + 41: 'GL2C_PERF_SEL_SHARED_REQ', + 42: 'GL2C_PERF_SEL_HIT', + 43: 'GL2C_PERF_SEL_MISS', + 44: 'GL2C_PERF_SEL_FULL_HIT', + 45: 'GL2C_PERF_SEL_PARTIAL_32B_HIT', + 46: 'GL2C_PERF_SEL_PARTIAL_64B_HIT', + 47: 'GL2C_PERF_SEL_PARTIAL_96B_HIT', + 48: 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', + 49: 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', + 50: 'GL2C_PERF_SEL_UNCACHED_WRITE', + 51: 'GL2C_PERF_SEL_WRITEBACK', + 52: 'GL2C_PERF_SEL_NORMAL_WRITEBACK', + 53: 'GL2C_PERF_SEL_EVICT', + 54: 'GL2C_PERF_SEL_NORMAL_EVICT', + 55: 'GL2C_PERF_SEL_PROBE_EVICT', + 56: 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', + 57: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', + 58: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', + 59: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', + 60: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', + 61: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', + 62: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', + 63: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', + 64: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', + 65: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', + 66: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', + 67: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', + 68: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', + 69: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', + 70: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', + 71: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', + 72: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', + 73: 'GL2C_PERF_SEL_READ_32_REQ', + 74: 'GL2C_PERF_SEL_READ_64_REQ', + 75: 'GL2C_PERF_SEL_READ_128_REQ', + 76: 'GL2C_PERF_SEL_WRITE_32_REQ', + 77: 'GL2C_PERF_SEL_WRITE_64_REQ', + 78: 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', + 79: 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', + 80: 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', + 81: 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', + 82: 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', + 83: 'GL2C_PERF_SEL_MC_WRREQ', + 84: 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', + 85: 'GL2C_PERF_SEL_EA_WRREQ_64B', + 86: 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', + 87: 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', + 88: 'GL2C_PERF_SEL_MC_WRREQ_STALL', + 89: 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', + 90: 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', + 91: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', + 92: 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', + 93: 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', + 94: 'GL2C_PERF_SEL_EA_ATOMIC', + 95: 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', + 96: 'GL2C_PERF_SEL_MC_RDREQ', + 97: 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', + 98: 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', + 99: 'GL2C_PERF_SEL_EA_RDREQ_32B', + 100: 'GL2C_PERF_SEL_EA_RDREQ_64B', + 101: 'GL2C_PERF_SEL_EA_RDREQ_96B', + 102: 'GL2C_PERF_SEL_EA_RDREQ_128B', + 103: 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', + 104: 'GL2C_PERF_SEL_EA_RD_MDC_32B', + 105: 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', + 106: 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', + 107: 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', + 108: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', + 109: 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', + 110: 'GL2C_PERF_SEL_EA_RDREQ_DRAM', + 111: 'GL2C_PERF_SEL_EA_WRREQ_DRAM', + 112: 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', + 113: 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', + 114: 'GL2C_PERF_SEL_ONION_READ', + 115: 'GL2C_PERF_SEL_ONION_WRITE', + 116: 'GL2C_PERF_SEL_IO_READ', + 117: 'GL2C_PERF_SEL_IO_WRITE', + 118: 'GL2C_PERF_SEL_GARLIC_READ', + 119: 'GL2C_PERF_SEL_GARLIC_WRITE', + 120: 'GL2C_PERF_SEL_EA_OUTSTANDING', + 121: 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', + 122: 'GL2C_PERF_SEL_SRC_FIFO_FULL', + 123: 'GL2C_PERF_SEL_TAG_STALL', + 124: 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 125: 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 126: 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 127: 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 128: 'GL2C_PERF_SEL_TAG_PROBE_STALL', + 129: 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', + 130: 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', + 131: 'GL2C_PERF_SEL_TAG_READ_DST_STALL', + 132: 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', + 133: 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 134: 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 135: 'GL2C_PERF_SEL_BUBBLE', + 136: 'GL2C_PERF_SEL_IB_REQ', + 137: 'GL2C_PERF_SEL_IB_STALL', + 138: 'GL2C_PERF_SEL_IB_TAG_STALL', + 139: 'GL2C_PERF_SEL_IB_CM_STALL', + 140: 'GL2C_PERF_SEL_RETURN_ACK', + 141: 'GL2C_PERF_SEL_RETURN_DATA', + 142: 'GL2C_PERF_SEL_EA_RDRET_NACK', + 143: 'GL2C_PERF_SEL_EA_WRRET_NACK', + 144: 'GL2C_PERF_SEL_GL2A_LEVEL', + 145: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', + 146: 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', + 147: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 148: 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', + 149: 'GL2C_PERF_SEL_GCR_INV', + 150: 'GL2C_PERF_SEL_GCR_WB', + 151: 'GL2C_PERF_SEL_GCR_DISCARD', + 152: 'GL2C_PERF_SEL_GCR_RANGE', + 153: 'GL2C_PERF_SEL_GCR_ALL', + 154: 'GL2C_PERF_SEL_GCR_VOL', + 155: 'GL2C_PERF_SEL_GCR_UNSHARED', + 156: 'GL2C_PERF_SEL_GCR_MDC_INV', + 157: 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', + 158: 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', + 159: 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', + 160: 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', + 161: 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', + 162: 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', + 163: 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', + 164: 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', + 165: 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', + 166: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', + 167: 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', + 168: 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', + 169: 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', + 170: 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', + 171: 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', + 172: 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', + 173: 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', + 174: 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', + 175: 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', + 176: 'GL2C_PERF_SEL_GCR_WBINVL2_START', + 177: 'GL2C_PERF_SEL_MDC_INV_METADATA', + 178: 'GL2C_PERF_SEL_MDC_REQ', + 179: 'GL2C_PERF_SEL_MDC_LEVEL', + 180: 'GL2C_PERF_SEL_MDC_TAG_HIT', + 181: 'GL2C_PERF_SEL_MDC_SECTOR_HIT', + 182: 'GL2C_PERF_SEL_MDC_SECTOR_MISS', + 183: 'GL2C_PERF_SEL_MDC_TAG_STALL', + 184: 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', + 185: 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', + 186: 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', + 187: 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', + 188: 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', + 189: 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', + 190: 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', + 191: 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', + 192: 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', + 193: 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', + 194: 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', + 195: 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', + 196: 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', + 197: 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', + 198: 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', + 199: 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', + 200: 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', + 201: 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', + 202: 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', + 203: 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', + 204: 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', + 205: 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', + 206: 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', + 207: 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', + 208: 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', + 209: 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', + 210: 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', + 211: 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', + 212: 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', + 213: 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', + 214: 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', + 215: 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', + 216: 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', + 217: 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', + 218: 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', + 219: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', + 220: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', + 221: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', + 222: 'GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ', + 223: 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', + 224: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', + 225: 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', + 226: 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', + 227: 'GL2C_PERF_SEL_CM_COMP_READ_REQ', + 228: 'GL2C_PERF_SEL_CM_READ_BACK_REQ', + 229: 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', + 230: 'GL2C_PERF_SEL_CM_WR_ACK_REQ', + 231: 'GL2C_PERF_SEL_CM_NO_ACK_REQ', + 232: 'GL2C_PERF_SEL_CM_NOOP_REQ', + 233: 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', + 234: 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', + 235: 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', + 236: 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', + 237: 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', + 238: 'GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ', + 239: 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', + 240: 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', + 241: 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', + 242: 'GL2C_PERF_SEL_CM_RVF_FULL', + 243: 'GL2C_PERF_SEL_CM_SDR_FULL', + 244: 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', + 245: 'GL2C_PERF_SEL_CM_DCC_STALL', + 246: 'GL2C_PERF_SEL_CM_DCC_IN_XFC', + 247: 'GL2C_PERF_SEL_CM_DCC_OUT_XFC', + 248: 'GL2C_PERF_SEL_CM_DCC_OUT_1x1', + 249: 'GL2C_PERF_SEL_CM_DCC_OUT_1x2', + 250: 'GL2C_PERF_SEL_CM_DCC_OUT_2x1', + 251: 'GL2C_PERF_SEL_CM_DCC_OUT_2x2', + 252: 'GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP', + 253: 'GL2C_PERF_SEL_CM_DCC_OUT_CONST', + 254: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', + 255: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', + 256: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', + 257: 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', +} +GL2C_PERF_SEL_NONE = 0 +GL2C_PERF_SEL_CYCLE = 1 +GL2C_PERF_SEL_BUSY = 2 +GL2C_PERF_SEL_REQ = 3 +GL2C_PERF_SEL_VOL_REQ = 4 +GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 5 +GL2C_PERF_SEL_READ = 6 +GL2C_PERF_SEL_WRITE = 7 +GL2C_PERF_SEL_ATOMIC = 8 +GL2C_PERF_SEL_NOP_ACK = 9 +GL2C_PERF_SEL_NOP_RTN0 = 10 +GL2C_PERF_SEL_PROBE = 11 +GL2C_PERF_SEL_PROBE_ALL = 12 +GL2C_PERF_SEL_INTERNAL_PROBE = 13 +GL2C_PERF_SEL_COMPRESSED_READ_REQ = 14 +GL2C_PERF_SEL_METADATA_READ_REQ = 15 +GL2C_PERF_SEL_CLIENT0_REQ = 16 +GL2C_PERF_SEL_CLIENT1_REQ = 17 +GL2C_PERF_SEL_CLIENT2_REQ = 18 +GL2C_PERF_SEL_CLIENT3_REQ = 19 +GL2C_PERF_SEL_CLIENT4_REQ = 20 +GL2C_PERF_SEL_CLIENT5_REQ = 21 +GL2C_PERF_SEL_CLIENT6_REQ = 22 +GL2C_PERF_SEL_CLIENT7_REQ = 23 +GL2C_PERF_SEL_CLIENT8_REQ = 24 +GL2C_PERF_SEL_CLIENT9_REQ = 25 +GL2C_PERF_SEL_CLIENT10_REQ = 26 +GL2C_PERF_SEL_CLIENT11_REQ = 27 +GL2C_PERF_SEL_CLIENT12_REQ = 28 +GL2C_PERF_SEL_CLIENT13_REQ = 29 +GL2C_PERF_SEL_CLIENT14_REQ = 30 +GL2C_PERF_SEL_CLIENT15_REQ = 31 +GL2C_PERF_SEL_C_RW_S_REQ = 32 +GL2C_PERF_SEL_C_RW_US_REQ = 33 +GL2C_PERF_SEL_C_RO_S_REQ = 34 +GL2C_PERF_SEL_C_RO_US_REQ = 35 +GL2C_PERF_SEL_UC_REQ = 36 +GL2C_PERF_SEL_LRU_REQ = 37 +GL2C_PERF_SEL_STREAM_REQ = 38 +GL2C_PERF_SEL_BYPASS_REQ = 39 +GL2C_PERF_SEL_NOA_REQ = 40 +GL2C_PERF_SEL_SHARED_REQ = 41 +GL2C_PERF_SEL_HIT = 42 +GL2C_PERF_SEL_MISS = 43 +GL2C_PERF_SEL_FULL_HIT = 44 +GL2C_PERF_SEL_PARTIAL_32B_HIT = 45 +GL2C_PERF_SEL_PARTIAL_64B_HIT = 46 +GL2C_PERF_SEL_PARTIAL_96B_HIT = 47 +GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 48 +GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 49 +GL2C_PERF_SEL_UNCACHED_WRITE = 50 +GL2C_PERF_SEL_WRITEBACK = 51 +GL2C_PERF_SEL_NORMAL_WRITEBACK = 52 +GL2C_PERF_SEL_EVICT = 53 +GL2C_PERF_SEL_NORMAL_EVICT = 54 +GL2C_PERF_SEL_PROBE_EVICT = 55 +GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 56 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 57 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 58 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 59 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 60 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 61 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 62 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 63 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 64 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 65 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 66 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 67 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 68 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 69 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 70 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 71 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 72 +GL2C_PERF_SEL_READ_32_REQ = 73 +GL2C_PERF_SEL_READ_64_REQ = 74 +GL2C_PERF_SEL_READ_128_REQ = 75 +GL2C_PERF_SEL_WRITE_32_REQ = 76 +GL2C_PERF_SEL_WRITE_64_REQ = 77 +GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 78 +GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 79 +GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 80 +GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 81 +GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 82 +GL2C_PERF_SEL_MC_WRREQ = 83 +GL2C_PERF_SEL_EA_WRREQ_SNOOP = 84 +GL2C_PERF_SEL_EA_WRREQ_64B = 85 +GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 86 +GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 87 +GL2C_PERF_SEL_MC_WRREQ_STALL = 88 +GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 89 +GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 90 +GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 91 +GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 92 +GL2C_PERF_SEL_MC_WRREQ_LEVEL = 93 +GL2C_PERF_SEL_EA_ATOMIC = 94 +GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 95 +GL2C_PERF_SEL_MC_RDREQ = 96 +GL2C_PERF_SEL_EA_RDREQ_SNOOP = 97 +GL2C_PERF_SEL_EA_RDREQ_SPLIT = 98 +GL2C_PERF_SEL_EA_RDREQ_32B = 99 +GL2C_PERF_SEL_EA_RDREQ_64B = 100 +GL2C_PERF_SEL_EA_RDREQ_96B = 101 +GL2C_PERF_SEL_EA_RDREQ_128B = 102 +GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 103 +GL2C_PERF_SEL_EA_RD_MDC_32B = 104 +GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 105 +GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 106 +GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 107 +GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 108 +GL2C_PERF_SEL_MC_RDREQ_LEVEL = 109 +GL2C_PERF_SEL_EA_RDREQ_DRAM = 110 +GL2C_PERF_SEL_EA_WRREQ_DRAM = 111 +GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 112 +GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 113 +GL2C_PERF_SEL_ONION_READ = 114 +GL2C_PERF_SEL_ONION_WRITE = 115 +GL2C_PERF_SEL_IO_READ = 116 +GL2C_PERF_SEL_IO_WRITE = 117 +GL2C_PERF_SEL_GARLIC_READ = 118 +GL2C_PERF_SEL_GARLIC_WRITE = 119 +GL2C_PERF_SEL_EA_OUTSTANDING = 120 +GL2C_PERF_SEL_LATENCY_FIFO_FULL = 121 +GL2C_PERF_SEL_SRC_FIFO_FULL = 122 +GL2C_PERF_SEL_TAG_STALL = 123 +GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 124 +GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 125 +GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 126 +GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 127 +GL2C_PERF_SEL_TAG_PROBE_STALL = 128 +GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 129 +GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 130 +GL2C_PERF_SEL_TAG_READ_DST_STALL = 131 +GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 132 +GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 133 +GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 134 +GL2C_PERF_SEL_BUBBLE = 135 +GL2C_PERF_SEL_IB_REQ = 136 +GL2C_PERF_SEL_IB_STALL = 137 +GL2C_PERF_SEL_IB_TAG_STALL = 138 +GL2C_PERF_SEL_IB_CM_STALL = 139 +GL2C_PERF_SEL_RETURN_ACK = 140 +GL2C_PERF_SEL_RETURN_DATA = 141 +GL2C_PERF_SEL_EA_RDRET_NACK = 142 +GL2C_PERF_SEL_EA_WRRET_NACK = 143 +GL2C_PERF_SEL_GL2A_LEVEL = 144 +GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 145 +GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 146 +GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 147 +GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 148 +GL2C_PERF_SEL_GCR_INV = 149 +GL2C_PERF_SEL_GCR_WB = 150 +GL2C_PERF_SEL_GCR_DISCARD = 151 +GL2C_PERF_SEL_GCR_RANGE = 152 +GL2C_PERF_SEL_GCR_ALL = 153 +GL2C_PERF_SEL_GCR_VOL = 154 +GL2C_PERF_SEL_GCR_UNSHARED = 155 +GL2C_PERF_SEL_GCR_MDC_INV = 156 +GL2C_PERF_SEL_GCR_GL2_INV_ALL = 157 +GL2C_PERF_SEL_GCR_GL2_WB_ALL = 158 +GL2C_PERF_SEL_GCR_MDC_INV_ALL = 159 +GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 160 +GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 161 +GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 162 +GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 163 +GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 164 +GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 165 +GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 166 +GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 167 +GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 168 +GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 169 +GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 170 +GL2C_PERF_SEL_GCR_INVL2_VOL_START = 171 +GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 172 +GL2C_PERF_SEL_GCR_WBL2_VOL_START = 173 +GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 174 +GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 175 +GL2C_PERF_SEL_GCR_WBINVL2_START = 176 +GL2C_PERF_SEL_MDC_INV_METADATA = 177 +GL2C_PERF_SEL_MDC_REQ = 178 +GL2C_PERF_SEL_MDC_LEVEL = 179 +GL2C_PERF_SEL_MDC_TAG_HIT = 180 +GL2C_PERF_SEL_MDC_SECTOR_HIT = 181 +GL2C_PERF_SEL_MDC_SECTOR_MISS = 182 +GL2C_PERF_SEL_MDC_TAG_STALL = 183 +GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 184 +GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 185 +GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 186 +GL2C_PERF_SEL_CM_CHANNEL0_REQ = 187 +GL2C_PERF_SEL_CM_CHANNEL1_REQ = 188 +GL2C_PERF_SEL_CM_CHANNEL2_REQ = 189 +GL2C_PERF_SEL_CM_CHANNEL3_REQ = 190 +GL2C_PERF_SEL_CM_CHANNEL4_REQ = 191 +GL2C_PERF_SEL_CM_CHANNEL5_REQ = 192 +GL2C_PERF_SEL_CM_CHANNEL6_REQ = 193 +GL2C_PERF_SEL_CM_CHANNEL7_REQ = 194 +GL2C_PERF_SEL_CM_CHANNEL8_REQ = 195 +GL2C_PERF_SEL_CM_CHANNEL9_REQ = 196 +GL2C_PERF_SEL_CM_CHANNEL10_REQ = 197 +GL2C_PERF_SEL_CM_CHANNEL11_REQ = 198 +GL2C_PERF_SEL_CM_CHANNEL12_REQ = 199 +GL2C_PERF_SEL_CM_CHANNEL13_REQ = 200 +GL2C_PERF_SEL_CM_CHANNEL14_REQ = 201 +GL2C_PERF_SEL_CM_CHANNEL15_REQ = 202 +GL2C_PERF_SEL_CM_CHANNEL16_REQ = 203 +GL2C_PERF_SEL_CM_CHANNEL17_REQ = 204 +GL2C_PERF_SEL_CM_CHANNEL18_REQ = 205 +GL2C_PERF_SEL_CM_CHANNEL19_REQ = 206 +GL2C_PERF_SEL_CM_CHANNEL20_REQ = 207 +GL2C_PERF_SEL_CM_CHANNEL21_REQ = 208 +GL2C_PERF_SEL_CM_CHANNEL22_REQ = 209 +GL2C_PERF_SEL_CM_CHANNEL23_REQ = 210 +GL2C_PERF_SEL_CM_CHANNEL24_REQ = 211 +GL2C_PERF_SEL_CM_CHANNEL25_REQ = 212 +GL2C_PERF_SEL_CM_CHANNEL26_REQ = 213 +GL2C_PERF_SEL_CM_CHANNEL27_REQ = 214 +GL2C_PERF_SEL_CM_CHANNEL28_REQ = 215 +GL2C_PERF_SEL_CM_CHANNEL29_REQ = 216 +GL2C_PERF_SEL_CM_CHANNEL30_REQ = 217 +GL2C_PERF_SEL_CM_CHANNEL31_REQ = 218 +GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 219 +GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 220 +GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 221 +GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ = 222 +GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 223 +GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 224 +GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 225 +GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 226 +GL2C_PERF_SEL_CM_COMP_READ_REQ = 227 +GL2C_PERF_SEL_CM_READ_BACK_REQ = 228 +GL2C_PERF_SEL_CM_METADATA_WR_REQ = 229 +GL2C_PERF_SEL_CM_WR_ACK_REQ = 230 +GL2C_PERF_SEL_CM_NO_ACK_REQ = 231 +GL2C_PERF_SEL_CM_NOOP_REQ = 232 +GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 233 +GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 234 +GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 235 +GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 236 +GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 237 +GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ = 238 +GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 239 +GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 240 +GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 241 +GL2C_PERF_SEL_CM_RVF_FULL = 242 +GL2C_PERF_SEL_CM_SDR_FULL = 243 +GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 244 +GL2C_PERF_SEL_CM_DCC_STALL = 245 +GL2C_PERF_SEL_CM_DCC_IN_XFC = 246 +GL2C_PERF_SEL_CM_DCC_OUT_XFC = 247 +GL2C_PERF_SEL_CM_DCC_OUT_1x1 = 248 +GL2C_PERF_SEL_CM_DCC_OUT_1x2 = 249 +GL2C_PERF_SEL_CM_DCC_OUT_2x1 = 250 +GL2C_PERF_SEL_CM_DCC_OUT_2x2 = 251 +GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP = 252 +GL2C_PERF_SEL_CM_DCC_OUT_CONST = 253 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 254 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 255 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 256 +GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 257 +GL2C_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_PERF_SEL' +GRBM_PERF_SEL__enumvalues = { + 0: 'GRBM_PERF_SEL_COUNT', + 1: 'GRBM_PERF_SEL_USER_DEFINED', + 2: 'GRBM_PERF_SEL_GUI_ACTIVE', + 3: 'GRBM_PERF_SEL_CP_BUSY', + 4: 'GRBM_PERF_SEL_CP_COHER_BUSY', + 5: 'GRBM_PERF_SEL_CP_DMA_BUSY', + 6: 'GRBM_PERF_SEL_CB_BUSY', + 7: 'GRBM_PERF_SEL_DB_BUSY', + 8: 'GRBM_PERF_SEL_PA_BUSY', + 9: 'GRBM_PERF_SEL_SC_BUSY', + 11: 'GRBM_PERF_SEL_SPI_BUSY', + 12: 'GRBM_PERF_SEL_SX_BUSY', + 13: 'GRBM_PERF_SEL_TA_BUSY', + 14: 'GRBM_PERF_SEL_CB_CLEAN', + 15: 'GRBM_PERF_SEL_DB_CLEAN', + 25: 'GRBM_PERF_SEL_GDS_BUSY', + 26: 'GRBM_PERF_SEL_BCI_BUSY', + 27: 'GRBM_PERF_SEL_RLC_BUSY', + 28: 'GRBM_PERF_SEL_TCP_BUSY', + 29: 'GRBM_PERF_SEL_CPG_BUSY', + 30: 'GRBM_PERF_SEL_CPC_BUSY', + 31: 'GRBM_PERF_SEL_CPF_BUSY', + 32: 'GRBM_PERF_SEL_GE_BUSY', + 33: 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', + 34: 'GRBM_PERF_SEL_UTCL2_BUSY', + 35: 'GRBM_PERF_SEL_EA_BUSY', + 36: 'GRBM_PERF_SEL_RMI_BUSY', + 37: 'GRBM_PERF_SEL_CPAXI_BUSY', + 39: 'GRBM_PERF_SEL_UTCL1_BUSY', + 40: 'GRBM_PERF_SEL_GL2CC_BUSY', + 41: 'GRBM_PERF_SEL_SDMA_BUSY', + 42: 'GRBM_PERF_SEL_CH_BUSY', + 43: 'GRBM_PERF_SEL_PH_BUSY', + 44: 'GRBM_PERF_SEL_PMM_BUSY', + 45: 'GRBM_PERF_SEL_GUS_BUSY', + 46: 'GRBM_PERF_SEL_GL1CC_BUSY', + 47: 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', + 48: 'GRBM_PERF_SEL_GL1H_BUSY', + 49: 'GRBM_PERF_SEL_PC_BUSY', +} +GRBM_PERF_SEL_COUNT = 0 +GRBM_PERF_SEL_USER_DEFINED = 1 +GRBM_PERF_SEL_GUI_ACTIVE = 2 +GRBM_PERF_SEL_CP_BUSY = 3 +GRBM_PERF_SEL_CP_COHER_BUSY = 4 +GRBM_PERF_SEL_CP_DMA_BUSY = 5 +GRBM_PERF_SEL_CB_BUSY = 6 +GRBM_PERF_SEL_DB_BUSY = 7 +GRBM_PERF_SEL_PA_BUSY = 8 +GRBM_PERF_SEL_SC_BUSY = 9 +GRBM_PERF_SEL_SPI_BUSY = 11 +GRBM_PERF_SEL_SX_BUSY = 12 +GRBM_PERF_SEL_TA_BUSY = 13 +GRBM_PERF_SEL_CB_CLEAN = 14 +GRBM_PERF_SEL_DB_CLEAN = 15 +GRBM_PERF_SEL_GDS_BUSY = 25 +GRBM_PERF_SEL_BCI_BUSY = 26 +GRBM_PERF_SEL_RLC_BUSY = 27 +GRBM_PERF_SEL_TCP_BUSY = 28 +GRBM_PERF_SEL_CPG_BUSY = 29 +GRBM_PERF_SEL_CPC_BUSY = 30 +GRBM_PERF_SEL_CPF_BUSY = 31 +GRBM_PERF_SEL_GE_BUSY = 32 +GRBM_PERF_SEL_GE_NO_DMA_BUSY = 33 +GRBM_PERF_SEL_UTCL2_BUSY = 34 +GRBM_PERF_SEL_EA_BUSY = 35 +GRBM_PERF_SEL_RMI_BUSY = 36 +GRBM_PERF_SEL_CPAXI_BUSY = 37 +GRBM_PERF_SEL_UTCL1_BUSY = 39 +GRBM_PERF_SEL_GL2CC_BUSY = 40 +GRBM_PERF_SEL_SDMA_BUSY = 41 +GRBM_PERF_SEL_CH_BUSY = 42 +GRBM_PERF_SEL_PH_BUSY = 43 +GRBM_PERF_SEL_PMM_BUSY = 44 +GRBM_PERF_SEL_GUS_BUSY = 45 +GRBM_PERF_SEL_GL1CC_BUSY = 46 +GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 47 +GRBM_PERF_SEL_GL1H_BUSY = 48 +GRBM_PERF_SEL_PC_BUSY = 49 +GRBM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE0_PERF_SEL' +GRBM_SE0_PERF_SEL__enumvalues = { + 0: 'GRBM_SE0_PERF_SEL_COUNT', + 1: 'GRBM_SE0_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE0_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE0_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE0_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE0_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE0_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE0_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE0_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE0_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE0_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE0_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE0_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE0_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE0_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE0_PERF_SEL_PC_BUSY', +} +GRBM_SE0_PERF_SEL_COUNT = 0 +GRBM_SE0_PERF_SEL_USER_DEFINED = 1 +GRBM_SE0_PERF_SEL_CB_BUSY = 2 +GRBM_SE0_PERF_SEL_DB_BUSY = 3 +GRBM_SE0_PERF_SEL_SC_BUSY = 4 +GRBM_SE0_PERF_SEL_SPI_BUSY = 6 +GRBM_SE0_PERF_SEL_SX_BUSY = 7 +GRBM_SE0_PERF_SEL_TA_BUSY = 8 +GRBM_SE0_PERF_SEL_CB_CLEAN = 9 +GRBM_SE0_PERF_SEL_DB_CLEAN = 10 +GRBM_SE0_PERF_SEL_PA_BUSY = 12 +GRBM_SE0_PERF_SEL_BCI_BUSY = 14 +GRBM_SE0_PERF_SEL_RMI_BUSY = 15 +GRBM_SE0_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE0_PERF_SEL_TCP_BUSY = 17 +GRBM_SE0_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE0_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE0_PERF_SEL_PC_BUSY = 20 +GRBM_SE0_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE1_PERF_SEL' +GRBM_SE1_PERF_SEL__enumvalues = { + 0: 'GRBM_SE1_PERF_SEL_COUNT', + 1: 'GRBM_SE1_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE1_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE1_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE1_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE1_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE1_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE1_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE1_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE1_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE1_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE1_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE1_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE1_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE1_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE1_PERF_SEL_PC_BUSY', +} +GRBM_SE1_PERF_SEL_COUNT = 0 +GRBM_SE1_PERF_SEL_USER_DEFINED = 1 +GRBM_SE1_PERF_SEL_CB_BUSY = 2 +GRBM_SE1_PERF_SEL_DB_BUSY = 3 +GRBM_SE1_PERF_SEL_SC_BUSY = 4 +GRBM_SE1_PERF_SEL_SPI_BUSY = 6 +GRBM_SE1_PERF_SEL_SX_BUSY = 7 +GRBM_SE1_PERF_SEL_TA_BUSY = 8 +GRBM_SE1_PERF_SEL_CB_CLEAN = 9 +GRBM_SE1_PERF_SEL_DB_CLEAN = 10 +GRBM_SE1_PERF_SEL_PA_BUSY = 12 +GRBM_SE1_PERF_SEL_BCI_BUSY = 14 +GRBM_SE1_PERF_SEL_RMI_BUSY = 15 +GRBM_SE1_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE1_PERF_SEL_TCP_BUSY = 17 +GRBM_SE1_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE1_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE1_PERF_SEL_PC_BUSY = 20 +GRBM_SE1_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE2_PERF_SEL' +GRBM_SE2_PERF_SEL__enumvalues = { + 0: 'GRBM_SE2_PERF_SEL_COUNT', + 1: 'GRBM_SE2_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE2_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE2_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE2_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE2_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE2_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE2_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE2_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE2_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE2_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE2_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE2_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE2_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE2_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE2_PERF_SEL_PC_BUSY', +} +GRBM_SE2_PERF_SEL_COUNT = 0 +GRBM_SE2_PERF_SEL_USER_DEFINED = 1 +GRBM_SE2_PERF_SEL_CB_BUSY = 2 +GRBM_SE2_PERF_SEL_DB_BUSY = 3 +GRBM_SE2_PERF_SEL_SC_BUSY = 4 +GRBM_SE2_PERF_SEL_SPI_BUSY = 6 +GRBM_SE2_PERF_SEL_SX_BUSY = 7 +GRBM_SE2_PERF_SEL_TA_BUSY = 8 +GRBM_SE2_PERF_SEL_CB_CLEAN = 9 +GRBM_SE2_PERF_SEL_DB_CLEAN = 10 +GRBM_SE2_PERF_SEL_PA_BUSY = 12 +GRBM_SE2_PERF_SEL_BCI_BUSY = 14 +GRBM_SE2_PERF_SEL_RMI_BUSY = 15 +GRBM_SE2_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE2_PERF_SEL_TCP_BUSY = 17 +GRBM_SE2_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE2_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE2_PERF_SEL_PC_BUSY = 20 +GRBM_SE2_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE3_PERF_SEL' +GRBM_SE3_PERF_SEL__enumvalues = { + 0: 'GRBM_SE3_PERF_SEL_COUNT', + 1: 'GRBM_SE3_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE3_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE3_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE3_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE3_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE3_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE3_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE3_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE3_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE3_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE3_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE3_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE3_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE3_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE3_PERF_SEL_PC_BUSY', +} +GRBM_SE3_PERF_SEL_COUNT = 0 +GRBM_SE3_PERF_SEL_USER_DEFINED = 1 +GRBM_SE3_PERF_SEL_CB_BUSY = 2 +GRBM_SE3_PERF_SEL_DB_BUSY = 3 +GRBM_SE3_PERF_SEL_SC_BUSY = 4 +GRBM_SE3_PERF_SEL_SPI_BUSY = 6 +GRBM_SE3_PERF_SEL_SX_BUSY = 7 +GRBM_SE3_PERF_SEL_TA_BUSY = 8 +GRBM_SE3_PERF_SEL_CB_CLEAN = 9 +GRBM_SE3_PERF_SEL_DB_CLEAN = 10 +GRBM_SE3_PERF_SEL_PA_BUSY = 12 +GRBM_SE3_PERF_SEL_BCI_BUSY = 14 +GRBM_SE3_PERF_SEL_RMI_BUSY = 15 +GRBM_SE3_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE3_PERF_SEL_TCP_BUSY = 17 +GRBM_SE3_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE3_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE3_PERF_SEL_PC_BUSY = 20 +GRBM_SE3_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE4_PERF_SEL' +GRBM_SE4_PERF_SEL__enumvalues = { + 0: 'GRBM_SE4_PERF_SEL_COUNT', + 1: 'GRBM_SE4_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE4_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE4_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE4_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE4_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE4_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE4_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE4_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE4_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE4_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE4_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE4_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE4_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE4_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE4_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE4_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE4_PERF_SEL_PC_BUSY', +} +GRBM_SE4_PERF_SEL_COUNT = 0 +GRBM_SE4_PERF_SEL_USER_DEFINED = 1 +GRBM_SE4_PERF_SEL_CB_BUSY = 2 +GRBM_SE4_PERF_SEL_DB_BUSY = 3 +GRBM_SE4_PERF_SEL_SC_BUSY = 4 +GRBM_SE4_PERF_SEL_SPI_BUSY = 6 +GRBM_SE4_PERF_SEL_SX_BUSY = 7 +GRBM_SE4_PERF_SEL_TA_BUSY = 8 +GRBM_SE4_PERF_SEL_CB_CLEAN = 9 +GRBM_SE4_PERF_SEL_DB_CLEAN = 10 +GRBM_SE4_PERF_SEL_PA_BUSY = 12 +GRBM_SE4_PERF_SEL_BCI_BUSY = 14 +GRBM_SE4_PERF_SEL_RMI_BUSY = 15 +GRBM_SE4_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE4_PERF_SEL_TCP_BUSY = 17 +GRBM_SE4_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE4_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE4_PERF_SEL_PC_BUSY = 20 +GRBM_SE4_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE5_PERF_SEL' +GRBM_SE5_PERF_SEL__enumvalues = { + 0: 'GRBM_SE5_PERF_SEL_COUNT', + 1: 'GRBM_SE5_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE5_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE5_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE5_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE5_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE5_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE5_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE5_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE5_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE5_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE5_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE5_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE5_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE5_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE5_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE5_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE5_PERF_SEL_PC_BUSY', +} +GRBM_SE5_PERF_SEL_COUNT = 0 +GRBM_SE5_PERF_SEL_USER_DEFINED = 1 +GRBM_SE5_PERF_SEL_CB_BUSY = 2 +GRBM_SE5_PERF_SEL_DB_BUSY = 3 +GRBM_SE5_PERF_SEL_SC_BUSY = 4 +GRBM_SE5_PERF_SEL_SPI_BUSY = 6 +GRBM_SE5_PERF_SEL_SX_BUSY = 7 +GRBM_SE5_PERF_SEL_TA_BUSY = 8 +GRBM_SE5_PERF_SEL_CB_CLEAN = 9 +GRBM_SE5_PERF_SEL_DB_CLEAN = 10 +GRBM_SE5_PERF_SEL_PA_BUSY = 12 +GRBM_SE5_PERF_SEL_BCI_BUSY = 14 +GRBM_SE5_PERF_SEL_RMI_BUSY = 15 +GRBM_SE5_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE5_PERF_SEL_TCP_BUSY = 17 +GRBM_SE5_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE5_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE5_PERF_SEL_PC_BUSY = 20 +GRBM_SE5_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE6_PERF_SEL' +GRBM_SE6_PERF_SEL__enumvalues = { + 0: 'GRBM_SE6_PERF_SEL_COUNT', + 1: 'GRBM_SE6_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE6_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE6_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE6_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE6_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE6_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE6_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE6_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE6_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE6_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE6_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE6_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE6_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE6_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE6_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE6_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE6_PERF_SEL_PC_BUSY', +} +GRBM_SE6_PERF_SEL_COUNT = 0 +GRBM_SE6_PERF_SEL_USER_DEFINED = 1 +GRBM_SE6_PERF_SEL_CB_BUSY = 2 +GRBM_SE6_PERF_SEL_DB_BUSY = 3 +GRBM_SE6_PERF_SEL_SC_BUSY = 4 +GRBM_SE6_PERF_SEL_SPI_BUSY = 6 +GRBM_SE6_PERF_SEL_SX_BUSY = 7 +GRBM_SE6_PERF_SEL_TA_BUSY = 8 +GRBM_SE6_PERF_SEL_CB_CLEAN = 9 +GRBM_SE6_PERF_SEL_DB_CLEAN = 10 +GRBM_SE6_PERF_SEL_PA_BUSY = 12 +GRBM_SE6_PERF_SEL_BCI_BUSY = 14 +GRBM_SE6_PERF_SEL_RMI_BUSY = 15 +GRBM_SE6_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE6_PERF_SEL_TCP_BUSY = 17 +GRBM_SE6_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE6_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE6_PERF_SEL_PC_BUSY = 20 +GRBM_SE6_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'GRBM_SE7_PERF_SEL' +GRBM_SE7_PERF_SEL__enumvalues = { + 0: 'GRBM_SE7_PERF_SEL_COUNT', + 1: 'GRBM_SE7_PERF_SEL_USER_DEFINED', + 2: 'GRBM_SE7_PERF_SEL_CB_BUSY', + 3: 'GRBM_SE7_PERF_SEL_DB_BUSY', + 4: 'GRBM_SE7_PERF_SEL_SC_BUSY', + 6: 'GRBM_SE7_PERF_SEL_SPI_BUSY', + 7: 'GRBM_SE7_PERF_SEL_SX_BUSY', + 8: 'GRBM_SE7_PERF_SEL_TA_BUSY', + 9: 'GRBM_SE7_PERF_SEL_CB_CLEAN', + 10: 'GRBM_SE7_PERF_SEL_DB_CLEAN', + 12: 'GRBM_SE7_PERF_SEL_PA_BUSY', + 14: 'GRBM_SE7_PERF_SEL_BCI_BUSY', + 15: 'GRBM_SE7_PERF_SEL_RMI_BUSY', + 16: 'GRBM_SE7_PERF_SEL_UTCL1_BUSY', + 17: 'GRBM_SE7_PERF_SEL_TCP_BUSY', + 18: 'GRBM_SE7_PERF_SEL_GL1CC_BUSY', + 19: 'GRBM_SE7_PERF_SEL_GL1H_BUSY', + 20: 'GRBM_SE7_PERF_SEL_PC_BUSY', +} +GRBM_SE7_PERF_SEL_COUNT = 0 +GRBM_SE7_PERF_SEL_USER_DEFINED = 1 +GRBM_SE7_PERF_SEL_CB_BUSY = 2 +GRBM_SE7_PERF_SEL_DB_BUSY = 3 +GRBM_SE7_PERF_SEL_SC_BUSY = 4 +GRBM_SE7_PERF_SEL_SPI_BUSY = 6 +GRBM_SE7_PERF_SEL_SX_BUSY = 7 +GRBM_SE7_PERF_SEL_TA_BUSY = 8 +GRBM_SE7_PERF_SEL_CB_CLEAN = 9 +GRBM_SE7_PERF_SEL_DB_CLEAN = 10 +GRBM_SE7_PERF_SEL_PA_BUSY = 12 +GRBM_SE7_PERF_SEL_BCI_BUSY = 14 +GRBM_SE7_PERF_SEL_RMI_BUSY = 15 +GRBM_SE7_PERF_SEL_UTCL1_BUSY = 16 +GRBM_SE7_PERF_SEL_TCP_BUSY = 17 +GRBM_SE7_PERF_SEL_GL1CC_BUSY = 18 +GRBM_SE7_PERF_SEL_GL1H_BUSY = 19 +GRBM_SE7_PERF_SEL_PC_BUSY = 20 +GRBM_SE7_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PIPE_COMPAT_LEVEL' +PIPE_COMPAT_LEVEL__enumvalues = { + 0: 'GEN_ZERO', + 1: 'GEN_ONE', + 2: 'GEN_TWO', + 3: 'GEN_RESERVED', +} +GEN_ZERO = 0 +GEN_ONE = 1 +GEN_TWO = 2 +GEN_RESERVED = 3 +PIPE_COMPAT_LEVEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPC_LATENCY_STATS_SEL' +CPC_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPC_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPC_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPC_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPC_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPC_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPC_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPC_LATENCY_STATS_SEL_INVAL_MAX', + 7: 'CPC_LATENCY_STATS_SEL_INVAL_MIN', + 8: 'CPC_LATENCY_STATS_SEL_INVAL_LAST', +} +CPC_LATENCY_STATS_SEL_XACK_MAX = 0 +CPC_LATENCY_STATS_SEL_XACK_MIN = 1 +CPC_LATENCY_STATS_SEL_XACK_LAST = 2 +CPC_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPC_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPC_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPC_LATENCY_STATS_SEL_INVAL_MAX = 6 +CPC_LATENCY_STATS_SEL_INVAL_MIN = 7 +CPC_LATENCY_STATS_SEL_INVAL_LAST = 8 +CPC_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPC_PERFCOUNT_SEL' +CPC_PERFCOUNT_SEL__enumvalues = { + 0: 'CPC_PERF_SEL_ALWAYS_COUNT', + 1: 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 2: 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 5: 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 6: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 7: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 8: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 9: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', + 10: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', + 11: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 12: 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 13: 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 14: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 15: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 16: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 17: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', + 18: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', + 19: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 20: 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 21: 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 22: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 23: 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 24: 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 25: 'CPC_PERF_SEL_CPC_STAT_BUSY', + 26: 'CPC_PERF_SEL_CPC_STAT_IDLE', + 27: 'CPC_PERF_SEL_CPC_STAT_STALL', + 28: 'CPC_PERF_SEL_CPC_TCIU_BUSY', + 29: 'CPC_PERF_SEL_CPC_TCIU_IDLE', + 30: 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', + 31: 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', + 32: 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', + 33: 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', + 34: 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', + 35: 'CPC_PERF_SEL_CPC_GCRIU_BUSY', + 36: 'CPC_PERF_SEL_CPC_GCRIU_IDLE', + 37: 'CPC_PERF_SEL_CPC_GCRIU_STALL', + 38: 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 39: 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', + 40: 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', + 41: 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', + 42: 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', + 43: 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', + 44: 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', + 45: 'CPC_PERF_SEL_MES_THREAD0', + 46: 'CPC_PERF_SEL_MES_THREAD1', +} +CPC_PERF_SEL_ALWAYS_COUNT = 0 +CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 1 +CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 2 +CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 5 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 6 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 7 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 8 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 9 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 10 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 11 +CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 12 +CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 13 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 14 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 15 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 16 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 17 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 18 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 19 +CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 20 +CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 21 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 22 +CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 23 +CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 24 +CPC_PERF_SEL_CPC_STAT_BUSY = 25 +CPC_PERF_SEL_CPC_STAT_IDLE = 26 +CPC_PERF_SEL_CPC_STAT_STALL = 27 +CPC_PERF_SEL_CPC_TCIU_BUSY = 28 +CPC_PERF_SEL_CPC_TCIU_IDLE = 29 +CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 30 +CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 31 +CPC_PERF_SEL_CPC_UTCL2IU_STALL = 32 +CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 33 +CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 34 +CPC_PERF_SEL_CPC_GCRIU_BUSY = 35 +CPC_PERF_SEL_CPC_GCRIU_IDLE = 36 +CPC_PERF_SEL_CPC_GCRIU_STALL = 37 +CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 38 +CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 39 +CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 40 +CPC_PERF_SEL_CPC_UTCL2IU_XACK = 41 +CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 42 +CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 43 +CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 44 +CPC_PERF_SEL_MES_THREAD0 = 45 +CPC_PERF_SEL_MES_THREAD1 = 46 +CPC_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_LATENCY_STATS_SEL' +CPF_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPF_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPF_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPF_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPF_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPF_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPF_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPF_LATENCY_STATS_SEL_READ_MAX', + 7: 'CPF_LATENCY_STATS_SEL_READ_MIN', + 8: 'CPF_LATENCY_STATS_SEL_READ_LAST', + 9: 'CPF_LATENCY_STATS_SEL_INVAL_MAX', + 10: 'CPF_LATENCY_STATS_SEL_INVAL_MIN', + 11: 'CPF_LATENCY_STATS_SEL_INVAL_LAST', +} +CPF_LATENCY_STATS_SEL_XACK_MAX = 0 +CPF_LATENCY_STATS_SEL_XACK_MIN = 1 +CPF_LATENCY_STATS_SEL_XACK_LAST = 2 +CPF_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPF_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPF_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPF_LATENCY_STATS_SEL_READ_MAX = 6 +CPF_LATENCY_STATS_SEL_READ_MIN = 7 +CPF_LATENCY_STATS_SEL_READ_LAST = 8 +CPF_LATENCY_STATS_SEL_INVAL_MAX = 9 +CPF_LATENCY_STATS_SEL_INVAL_MIN = 10 +CPF_LATENCY_STATS_SEL_INVAL_LAST = 11 +CPF_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_PERFCOUNTWINDOW_SEL' +CPF_PERFCOUNTWINDOW_SEL__enumvalues = { + 0: 'CPF_PERFWINDOW_SEL_CSF', + 1: 'CPF_PERFWINDOW_SEL_HQD1', + 2: 'CPF_PERFWINDOW_SEL_HQD2', + 3: 'CPF_PERFWINDOW_SEL_RDMA', + 4: 'CPF_PERFWINDOW_SEL_RWPP', +} +CPF_PERFWINDOW_SEL_CSF = 0 +CPF_PERFWINDOW_SEL_HQD1 = 1 +CPF_PERFWINDOW_SEL_HQD2 = 2 +CPF_PERFWINDOW_SEL_RDMA = 3 +CPF_PERFWINDOW_SEL_RWPP = 4 +CPF_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_PERFCOUNT_SEL' +CPF_PERFCOUNT_SEL__enumvalues = { + 0: 'CPF_PERF_SEL_ALWAYS_COUNT', + 2: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 3: 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 4: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 5: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 6: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 7: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', + 10: 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 11: 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 12: 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 13: 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 14: 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 15: 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 16: 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', + 17: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 18: 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 19: 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', + 20: 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', + 21: 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 22: 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 23: 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', + 24: 'CPF_PERF_SEL_CPF_STAT_BUSY', + 25: 'CPF_PERF_SEL_CPF_STAT_IDLE', + 26: 'CPF_PERF_SEL_CPF_STAT_STALL', + 27: 'CPF_PERF_SEL_CPF_TCIU_BUSY', + 28: 'CPF_PERF_SEL_CPF_TCIU_IDLE', + 29: 'CPF_PERF_SEL_CPF_TCIU_STALL', + 30: 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', + 31: 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', + 32: 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', + 33: 'CPF_PERF_SEL_CPF_GCRIU_BUSY', + 34: 'CPF_PERF_SEL_CPF_GCRIU_IDLE', + 35: 'CPF_PERF_SEL_CPF_GCRIU_STALL', + 36: 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 37: 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', + 38: 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', + 39: 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', + 40: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', + 41: 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', + 42: 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', + 43: 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', +} +CPF_PERF_SEL_ALWAYS_COUNT = 0 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 2 +CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 3 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 4 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 5 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 6 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 7 +CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 10 +CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 11 +CPF_PERF_SEL_GRBM_DWORDS_SENT = 12 +CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 13 +CPF_PERF_SEL_REGISTER_CLOCK_VALID = 14 +CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 15 +CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 16 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 17 +CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 18 +CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 19 +CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 20 +CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 21 +CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 22 +CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 23 +CPF_PERF_SEL_CPF_STAT_BUSY = 24 +CPF_PERF_SEL_CPF_STAT_IDLE = 25 +CPF_PERF_SEL_CPF_STAT_STALL = 26 +CPF_PERF_SEL_CPF_TCIU_BUSY = 27 +CPF_PERF_SEL_CPF_TCIU_IDLE = 28 +CPF_PERF_SEL_CPF_TCIU_STALL = 29 +CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 30 +CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 31 +CPF_PERF_SEL_CPF_UTCL2IU_STALL = 32 +CPF_PERF_SEL_CPF_GCRIU_BUSY = 33 +CPF_PERF_SEL_CPF_GCRIU_IDLE = 34 +CPF_PERF_SEL_CPF_GCRIU_STALL = 35 +CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 36 +CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 37 +CPF_PERF_SEL_CPF_UTCL2IU_XACK = 38 +CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 39 +CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 40 +CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 41 +CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 42 +CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 43 +CPF_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPF_SCRATCH_REG_ATOMIC_OP' +CPF_SCRATCH_REG_ATOMIC_OP__enumvalues = { + 0: 'CPF_SCRATCH_REG_ATOMIC_ADD', + 1: 'CPF_SCRATCH_REG_ATOMIC_SUB', + 2: 'CPF_SCRATCH_REG_ATOMIC_OR', + 3: 'CPF_SCRATCH_REG_ATOMIC_AND', + 4: 'CPF_SCRATCH_REG_ATOMIC_NOT', + 5: 'CPF_SCRATCH_REG_ATOMIC_MIN', + 6: 'CPF_SCRATCH_REG_ATOMIC_MAX', + 7: 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', +} +CPF_SCRATCH_REG_ATOMIC_ADD = 0 +CPF_SCRATCH_REG_ATOMIC_SUB = 1 +CPF_SCRATCH_REG_ATOMIC_OR = 2 +CPF_SCRATCH_REG_ATOMIC_AND = 3 +CPF_SCRATCH_REG_ATOMIC_NOT = 4 +CPF_SCRATCH_REG_ATOMIC_MIN = 5 +CPF_SCRATCH_REG_ATOMIC_MAX = 6 +CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 7 +CPF_SCRATCH_REG_ATOMIC_OP = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_LATENCY_STATS_SEL' +CPG_LATENCY_STATS_SEL__enumvalues = { + 0: 'CPG_LATENCY_STATS_SEL_XACK_MAX', + 1: 'CPG_LATENCY_STATS_SEL_XACK_MIN', + 2: 'CPG_LATENCY_STATS_SEL_XACK_LAST', + 3: 'CPG_LATENCY_STATS_SEL_XNACK_MAX', + 4: 'CPG_LATENCY_STATS_SEL_XNACK_MIN', + 5: 'CPG_LATENCY_STATS_SEL_XNACK_LAST', + 6: 'CPG_LATENCY_STATS_SEL_WRITE_MAX', + 7: 'CPG_LATENCY_STATS_SEL_WRITE_MIN', + 8: 'CPG_LATENCY_STATS_SEL_WRITE_LAST', + 9: 'CPG_LATENCY_STATS_SEL_READ_MAX', + 10: 'CPG_LATENCY_STATS_SEL_READ_MIN', + 11: 'CPG_LATENCY_STATS_SEL_READ_LAST', + 12: 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', + 13: 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', + 14: 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', + 15: 'CPG_LATENCY_STATS_SEL_INVAL_MAX', + 16: 'CPG_LATENCY_STATS_SEL_INVAL_MIN', + 17: 'CPG_LATENCY_STATS_SEL_INVAL_LAST', +} +CPG_LATENCY_STATS_SEL_XACK_MAX = 0 +CPG_LATENCY_STATS_SEL_XACK_MIN = 1 +CPG_LATENCY_STATS_SEL_XACK_LAST = 2 +CPG_LATENCY_STATS_SEL_XNACK_MAX = 3 +CPG_LATENCY_STATS_SEL_XNACK_MIN = 4 +CPG_LATENCY_STATS_SEL_XNACK_LAST = 5 +CPG_LATENCY_STATS_SEL_WRITE_MAX = 6 +CPG_LATENCY_STATS_SEL_WRITE_MIN = 7 +CPG_LATENCY_STATS_SEL_WRITE_LAST = 8 +CPG_LATENCY_STATS_SEL_READ_MAX = 9 +CPG_LATENCY_STATS_SEL_READ_MIN = 10 +CPG_LATENCY_STATS_SEL_READ_LAST = 11 +CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 12 +CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 13 +CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 14 +CPG_LATENCY_STATS_SEL_INVAL_MAX = 15 +CPG_LATENCY_STATS_SEL_INVAL_MIN = 16 +CPG_LATENCY_STATS_SEL_INVAL_LAST = 17 +CPG_LATENCY_STATS_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_PERFCOUNTWINDOW_SEL' +CPG_PERFCOUNTWINDOW_SEL__enumvalues = { + 0: 'CPG_PERFWINDOW_SEL_PFP', + 1: 'CPG_PERFWINDOW_SEL_ME', + 2: 'CPG_PERFWINDOW_SEL_CE', + 3: 'CPG_PERFWINDOW_SEL_MES', + 4: 'CPG_PERFWINDOW_SEL_MEC1', + 5: 'CPG_PERFWINDOW_SEL_MEC2', + 6: 'CPG_PERFWINDOW_SEL_DFY', + 7: 'CPG_PERFWINDOW_SEL_DMA', + 8: 'CPG_PERFWINDOW_SEL_SHADOW', + 9: 'CPG_PERFWINDOW_SEL_RB', + 10: 'CPG_PERFWINDOW_SEL_CEDMA', + 11: 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', + 12: 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', + 13: 'CPG_PERFWINDOW_SEL_PQ1', + 14: 'CPG_PERFWINDOW_SEL_PQ2', + 15: 'CPG_PERFWINDOW_SEL_PQ3', + 16: 'CPG_PERFWINDOW_SEL_MEMWR', + 17: 'CPG_PERFWINDOW_SEL_MEMRD', + 18: 'CPG_PERFWINDOW_SEL_VGT0', + 19: 'CPG_PERFWINDOW_SEL_VGT1', + 20: 'CPG_PERFWINDOW_SEL_APPEND', + 21: 'CPG_PERFWINDOW_SEL_QURD', + 22: 'CPG_PERFWINDOW_SEL_DDID', + 23: 'CPG_PERFWINDOW_SEL_SR', + 24: 'CPG_PERFWINDOW_SEL_QU_EOP', + 25: 'CPG_PERFWINDOW_SEL_QU_STRM', + 26: 'CPG_PERFWINDOW_SEL_QU_PIPE', + 27: 'CPG_PERFWINDOW_SEL_RESERVED1', + 28: 'CPG_PERFWINDOW_SEL_CPC_IC', + 29: 'CPG_PERFWINDOW_SEL_RESERVED2', + 30: 'CPG_PERFWINDOW_SEL_CPG_IC', +} +CPG_PERFWINDOW_SEL_PFP = 0 +CPG_PERFWINDOW_SEL_ME = 1 +CPG_PERFWINDOW_SEL_CE = 2 +CPG_PERFWINDOW_SEL_MES = 3 +CPG_PERFWINDOW_SEL_MEC1 = 4 +CPG_PERFWINDOW_SEL_MEC2 = 5 +CPG_PERFWINDOW_SEL_DFY = 6 +CPG_PERFWINDOW_SEL_DMA = 7 +CPG_PERFWINDOW_SEL_SHADOW = 8 +CPG_PERFWINDOW_SEL_RB = 9 +CPG_PERFWINDOW_SEL_CEDMA = 10 +CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 11 +CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 12 +CPG_PERFWINDOW_SEL_PQ1 = 13 +CPG_PERFWINDOW_SEL_PQ2 = 14 +CPG_PERFWINDOW_SEL_PQ3 = 15 +CPG_PERFWINDOW_SEL_MEMWR = 16 +CPG_PERFWINDOW_SEL_MEMRD = 17 +CPG_PERFWINDOW_SEL_VGT0 = 18 +CPG_PERFWINDOW_SEL_VGT1 = 19 +CPG_PERFWINDOW_SEL_APPEND = 20 +CPG_PERFWINDOW_SEL_QURD = 21 +CPG_PERFWINDOW_SEL_DDID = 22 +CPG_PERFWINDOW_SEL_SR = 23 +CPG_PERFWINDOW_SEL_QU_EOP = 24 +CPG_PERFWINDOW_SEL_QU_STRM = 25 +CPG_PERFWINDOW_SEL_QU_PIPE = 26 +CPG_PERFWINDOW_SEL_RESERVED1 = 27 +CPG_PERFWINDOW_SEL_CPC_IC = 28 +CPG_PERFWINDOW_SEL_RESERVED2 = 29 +CPG_PERFWINDOW_SEL_CPG_IC = 30 +CPG_PERFCOUNTWINDOW_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CPG_PERFCOUNT_SEL' +CPG_PERFCOUNT_SEL__enumvalues = { + 0: 'CPG_PERF_SEL_ALWAYS_COUNT', + 1: 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 4: 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 5: 'CPG_PERF_SEL_ME_PARSER_BUSY', + 6: 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 7: 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', + 9: 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 10: 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 11: 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 12: 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 13: 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 14: 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 15: 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 16: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 17: 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 18: 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 19: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 20: 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 21: 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 22: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 23: 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 24: 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 25: 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 26: 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 27: 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 28: 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 29: 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 31: 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 32: 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 33: 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 34: 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 35: 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', + 36: 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 37: 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 38: 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 39: 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 41: 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 42: 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 43: 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 44: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 45: 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 46: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 47: 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 48: 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 49: 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 50: 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', + 51: 'CPG_PERF_SEL_CPG_STAT_BUSY', + 52: 'CPG_PERF_SEL_CPG_STAT_IDLE', + 53: 'CPG_PERF_SEL_CPG_STAT_STALL', + 54: 'CPG_PERF_SEL_CPG_TCIU_BUSY', + 55: 'CPG_PERF_SEL_CPG_TCIU_IDLE', + 56: 'CPG_PERF_SEL_CPG_TCIU_STALL', + 57: 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', + 58: 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', + 59: 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', + 60: 'CPG_PERF_SEL_CPG_GCRIU_BUSY', + 61: 'CPG_PERF_SEL_CPG_GCRIU_IDLE', + 62: 'CPG_PERF_SEL_CPG_GCRIU_STALL', + 63: 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 64: 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', + 65: 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', + 66: 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', + 67: 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', + 68: 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', + 69: 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', + 70: 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', + 71: 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', + 72: 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', + 73: 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', + 74: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', + 75: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', + 76: 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', + 77: 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', + 78: 'CPG_PERF_SEL_DMA_BUSY', + 79: 'CPG_PERF_SEL_DMA_STARVED', + 80: 'CPG_PERF_SEL_DMA_STALLED', + 81: 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', + 82: 'CPG_PERF_SEL_PFP_PWS_STALLED0', + 83: 'CPG_PERF_SEL_ME_PWS_STALLED0', + 84: 'CPG_PERF_SEL_PFP_PWS_STALLED1', + 85: 'CPG_PERF_SEL_ME_PWS_STALLED1', +} +CPG_PERF_SEL_ALWAYS_COUNT = 0 +CPG_PERF_SEL_RBIU_FIFO_FULL = 1 +CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 4 +CPG_PERF_SEL_ME_PARSER_BUSY = 5 +CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 6 +CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 7 +CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 9 +CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 10 +CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 11 +CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 12 +CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 13 +CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 14 +CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 15 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 16 +CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 17 +CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 18 +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 19 +CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 20 +CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 21 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 22 +CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 23 +CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 24 +CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 25 +CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 26 +CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 27 +CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 28 +CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 29 +CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 31 +CPG_PERF_SEL_DYNAMIC_CLK_VALID = 32 +CPG_PERF_SEL_REGISTER_CLK_VALID = 33 +CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 34 +CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 35 +CPG_PERF_SEL_CE_STALL_RAM_DUMP = 36 +CPG_PERF_SEL_CE_STALL_RAM_WRITE = 37 +CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 38 +CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 39 +CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 41 +CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 42 +CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 43 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 44 +CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 45 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 46 +CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 47 +CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 48 +CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 49 +CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 50 +CPG_PERF_SEL_CPG_STAT_BUSY = 51 +CPG_PERF_SEL_CPG_STAT_IDLE = 52 +CPG_PERF_SEL_CPG_STAT_STALL = 53 +CPG_PERF_SEL_CPG_TCIU_BUSY = 54 +CPG_PERF_SEL_CPG_TCIU_IDLE = 55 +CPG_PERF_SEL_CPG_TCIU_STALL = 56 +CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 57 +CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 58 +CPG_PERF_SEL_CPG_UTCL2IU_STALL = 59 +CPG_PERF_SEL_CPG_GCRIU_BUSY = 60 +CPG_PERF_SEL_CPG_GCRIU_IDLE = 61 +CPG_PERF_SEL_CPG_GCRIU_STALL = 62 +CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 63 +CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 64 +CPG_PERF_SEL_CPG_UTCL2IU_XACK = 65 +CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 66 +CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 67 +CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 68 +CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 69 +CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 70 +CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 71 +CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 72 +CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 73 +CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 74 +CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 75 +CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 76 +CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 77 +CPG_PERF_SEL_DMA_BUSY = 78 +CPG_PERF_SEL_DMA_STARVED = 79 +CPG_PERF_SEL_DMA_STALLED = 80 +CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 81 +CPG_PERF_SEL_PFP_PWS_STALLED0 = 82 +CPG_PERF_SEL_ME_PWS_STALLED0 = 83 +CPG_PERF_SEL_PFP_PWS_STALLED1 = 84 +CPG_PERF_SEL_ME_PWS_STALLED1 = 85 +CPG_PERFCOUNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ALPHA_TAG_RAM_SEL' +CP_ALPHA_TAG_RAM_SEL__enumvalues = { + 0: 'CPG_TAG_RAM', + 1: 'CPC_TAG_RAM', + 2: 'CPF_TAG_RAM', + 3: 'RSV_TAG_RAM', +} +CPG_TAG_RAM = 0 +CPC_TAG_RAM = 1 +CPF_TAG_RAM = 2 +RSV_TAG_RAM = 3 +CP_ALPHA_TAG_RAM_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_MODE' +CP_DDID_CNTL_MODE__enumvalues = { + 0: 'STALL', + 1: 'OVERRUN', +} +STALL = 0 +OVERRUN = 1 +CP_DDID_CNTL_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_SIZE' +CP_DDID_CNTL_SIZE__enumvalues = { + 0: 'SIZE_8K', + 1: 'SIZE_16K', +} +SIZE_8K = 0 +SIZE_16K = 1 +CP_DDID_CNTL_SIZE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_DDID_CNTL_VMID_SEL' +CP_DDID_CNTL_VMID_SEL__enumvalues = { + 0: 'DDID_VMID_PIPE', + 1: 'DDID_VMID_CNTL', +} +DDID_VMID_PIPE = 0 +DDID_VMID_CNTL = 1 +CP_DDID_CNTL_VMID_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'CP_ME_ID' +CP_ME_ID__enumvalues = { + 0: 'ME_ID0', + 1: 'ME_ID1', + 2: 'ME_ID2', + 3: 'ME_ID3', +} +ME_ID0 = 0 +ME_ID1 = 1 +ME_ID2 = 2 +ME_ID3 = 3 +CP_ME_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_ENABLE_MODE' +CP_PERFMON_ENABLE_MODE__enumvalues = { + 0: 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 1: 'CP_PERFMON_ENABLE_MODE_RESERVED_1', + 2: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 3: 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', +} +CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0 +CP_PERFMON_ENABLE_MODE_RESERVED_1 = 1 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 2 +CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 3 +CP_PERFMON_ENABLE_MODE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PERFMON_STATE' +CP_PERFMON_STATE__enumvalues = { + 0: 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'CP_PERFMON_STATE_START_COUNTING', + 2: 'CP_PERFMON_STATE_STOP_COUNTING', + 3: 'CP_PERFMON_STATE_RESERVED_3', + 4: 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +CP_PERFMON_STATE_DISABLE_AND_RESET = 0 +CP_PERFMON_STATE_START_COUNTING = 1 +CP_PERFMON_STATE_STOP_COUNTING = 2 +CP_PERFMON_STATE_RESERVED_3 = 3 +CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +CP_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'CP_PIPE_ID' +CP_PIPE_ID__enumvalues = { + 0: 'PIPE_ID0', + 1: 'PIPE_ID1', + 2: 'PIPE_ID2', + 3: 'PIPE_ID3', +} +PIPE_ID0 = 0 +PIPE_ID1 = 1 +PIPE_ID2 = 2 +PIPE_ID3 = 3 +CP_PIPE_ID = ctypes.c_uint32 # enum + +# values for enumeration 'CP_RING_ID' +CP_RING_ID__enumvalues = { + 0: 'RINGID0', + 1: 'RINGID1', + 2: 'RINGID2', + 3: 'RINGID3', +} +RINGID0 = 0 +RINGID1 = 1 +RINGID2 = 2 +RINGID3 = 3 +CP_RING_ID = ctypes.c_uint32 # enum + +# values for enumeration 'SPM_PERFMON_STATE' +SPM_PERFMON_STATE__enumvalues = { + 0: 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 1: 'STRM_PERFMON_STATE_START_COUNTING', + 2: 'STRM_PERFMON_STATE_STOP_COUNTING', + 3: 'STRM_PERFMON_STATE_RESERVED_3', + 4: 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 5: 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', +} +STRM_PERFMON_STATE_DISABLE_AND_RESET = 0 +STRM_PERFMON_STATE_START_COUNTING = 1 +STRM_PERFMON_STATE_STOP_COUNTING = 2 +STRM_PERFMON_STATE_RESERVED_3 = 3 +STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 4 +STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 5 +SPM_PERFMON_STATE = ctypes.c_uint32 # enum + +# values for enumeration 'SX_BLEND_OPT' +SX_BLEND_OPT__enumvalues = { + 0: 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 1: 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 2: 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 3: 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 4: 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 5: 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 6: 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 7: 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', +} +BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0 +BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 1 +BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 2 +BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 3 +BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 4 +BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 5 +BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 6 +BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 7 +SX_BLEND_OPT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_DOWNCONVERT_FORMAT' +SX_DOWNCONVERT_FORMAT__enumvalues = { + 0: 'SX_RT_EXPORT_NO_CONVERSION', + 1: 'SX_RT_EXPORT_32_R', + 2: 'SX_RT_EXPORT_32_A', + 3: 'SX_RT_EXPORT_10_11_11', + 4: 'SX_RT_EXPORT_2_10_10_10', + 5: 'SX_RT_EXPORT_8_8_8_8', + 6: 'SX_RT_EXPORT_5_6_5', + 7: 'SX_RT_EXPORT_1_5_5_5', + 8: 'SX_RT_EXPORT_4_4_4_4', + 9: 'SX_RT_EXPORT_16_16_GR', + 10: 'SX_RT_EXPORT_16_16_AR', + 11: 'SX_RT_EXPORT_9_9_9_E5', + 12: 'SX_RT_EXPORT_2_10_10_10_7E3', + 13: 'SX_RT_EXPORT_2_10_10_10_6E4', +} +SX_RT_EXPORT_NO_CONVERSION = 0 +SX_RT_EXPORT_32_R = 1 +SX_RT_EXPORT_32_A = 2 +SX_RT_EXPORT_10_11_11 = 3 +SX_RT_EXPORT_2_10_10_10 = 4 +SX_RT_EXPORT_8_8_8_8 = 5 +SX_RT_EXPORT_5_6_5 = 6 +SX_RT_EXPORT_1_5_5_5 = 7 +SX_RT_EXPORT_4_4_4_4 = 8 +SX_RT_EXPORT_16_16_GR = 9 +SX_RT_EXPORT_16_16_AR = 10 +SX_RT_EXPORT_9_9_9_E5 = 11 +SX_RT_EXPORT_2_10_10_10_7E3 = 12 +SX_RT_EXPORT_2_10_10_10_6E4 = 13 +SX_DOWNCONVERT_FORMAT = ctypes.c_uint32 # enum + +# values for enumeration 'SX_OPT_COMB_FCN' +SX_OPT_COMB_FCN__enumvalues = { + 0: 'OPT_COMB_NONE', + 1: 'OPT_COMB_ADD', + 2: 'OPT_COMB_SUBTRACT', + 3: 'OPT_COMB_MIN', + 4: 'OPT_COMB_MAX', + 5: 'OPT_COMB_REVSUBTRACT', + 6: 'OPT_COMB_BLEND_DISABLED', + 7: 'OPT_COMB_SAFE_ADD', +} +OPT_COMB_NONE = 0 +OPT_COMB_ADD = 1 +OPT_COMB_SUBTRACT = 2 +OPT_COMB_MIN = 3 +OPT_COMB_MAX = 4 +OPT_COMB_REVSUBTRACT = 5 +OPT_COMB_BLEND_DISABLED = 6 +OPT_COMB_SAFE_ADD = 7 +SX_OPT_COMB_FCN = ctypes.c_uint32 # enum + +# values for enumeration 'SX_PERFCOUNTER_VALS' +SX_PERFCOUNTER_VALS__enumvalues = { + 0: 'SX_PERF_SEL_PA_IDLE_CYCLES', + 1: 'SX_PERF_SEL_PA_REQ', + 2: 'SX_PERF_SEL_PA_POS', + 3: 'SX_PERF_SEL_CLOCK', + 4: 'SX_PERF_SEL_GATE_EN1', + 5: 'SX_PERF_SEL_GATE_EN2', + 6: 'SX_PERF_SEL_GATE_EN3', + 7: 'SX_PERF_SEL_GATE_EN4', + 8: 'SX_PERF_SEL_SH_POS_STARVE', + 9: 'SX_PERF_SEL_SH_COLOR_STARVE', + 10: 'SX_PERF_SEL_SH_POS_STALL', + 11: 'SX_PERF_SEL_SH_COLOR_STALL', + 12: 'SX_PERF_SEL_DB0_PIXELS', + 13: 'SX_PERF_SEL_DB0_HALF_QUADS', + 14: 'SX_PERF_SEL_DB0_PIXEL_STALL', + 15: 'SX_PERF_SEL_DB0_PIXEL_IDLE', + 16: 'SX_PERF_SEL_DB0_PRED_PIXELS', + 17: 'SX_PERF_SEL_DB1_PIXELS', + 18: 'SX_PERF_SEL_DB1_HALF_QUADS', + 19: 'SX_PERF_SEL_DB1_PIXEL_STALL', + 20: 'SX_PERF_SEL_DB1_PIXEL_IDLE', + 21: 'SX_PERF_SEL_DB1_PRED_PIXELS', + 22: 'SX_PERF_SEL_DB2_PIXELS', + 23: 'SX_PERF_SEL_DB2_HALF_QUADS', + 24: 'SX_PERF_SEL_DB2_PIXEL_STALL', + 25: 'SX_PERF_SEL_DB2_PIXEL_IDLE', + 26: 'SX_PERF_SEL_DB2_PRED_PIXELS', + 27: 'SX_PERF_SEL_DB3_PIXELS', + 28: 'SX_PERF_SEL_DB3_HALF_QUADS', + 29: 'SX_PERF_SEL_DB3_PIXEL_STALL', + 30: 'SX_PERF_SEL_DB3_PIXEL_IDLE', + 31: 'SX_PERF_SEL_DB3_PRED_PIXELS', + 32: 'SX_PERF_SEL_COL_BUSY', + 33: 'SX_PERF_SEL_POS_BUSY', + 34: 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', + 35: 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', + 36: 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', + 37: 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', + 38: 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', + 39: 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', + 40: 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', + 41: 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', + 42: 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', + 43: 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', + 44: 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', + 45: 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', + 46: 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', + 47: 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', + 48: 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', + 49: 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', + 50: 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', + 51: 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', + 52: 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', + 53: 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', + 54: 'SX_PERF_SEL_PA_REQ_LATENCY', + 55: 'SX_PERF_SEL_POS_SCBD_STALL', + 56: 'SX_PERF_SEL_CLOCK_DROP_STALL', + 57: 'SX_PERF_SEL_GATE_EN5', + 58: 'SX_PERF_SEL_GATE_EN6', + 59: 'SX_PERF_SEL_DB0_SIZE', + 60: 'SX_PERF_SEL_DB1_SIZE', + 61: 'SX_PERF_SEL_DB2_SIZE', + 62: 'SX_PERF_SEL_DB3_SIZE', + 63: 'SX_PERF_SEL_IDX_STALL_CYCLES', + 64: 'SX_PERF_SEL_IDX_IDLE_CYCLES', + 65: 'SX_PERF_SEL_IDX_REQ', + 66: 'SX_PERF_SEL_IDX_RET', + 67: 'SX_PERF_SEL_IDX_REQ_LATENCY', + 68: 'SX_PERF_SEL_IDX_SCBD_STALL', + 69: 'SX_PERF_SEL_GATE_EN7', + 70: 'SX_PERF_SEL_GATE_EN8', + 71: 'SX_PERF_SEL_SH_IDX_STARVE', + 72: 'SX_PERF_SEL_IDX_BUSY', + 73: 'SX_PERF_SEL_PA_POS_BANK_CONF', + 74: 'SX_PERF_SEL_DB0_END_OF_WAVE', + 75: 'SX_PERF_SEL_DB0_4X2_DISCARD', + 76: 'SX_PERF_SEL_DB1_END_OF_WAVE', + 77: 'SX_PERF_SEL_DB1_4X2_DISCARD', + 78: 'SX_PERF_SEL_DB2_END_OF_WAVE', + 79: 'SX_PERF_SEL_DB2_4X2_DISCARD', + 80: 'SX_PERF_SEL_DB3_END_OF_WAVE', + 81: 'SX_PERF_SEL_DB3_4X2_DISCARD', +} +SX_PERF_SEL_PA_IDLE_CYCLES = 0 +SX_PERF_SEL_PA_REQ = 1 +SX_PERF_SEL_PA_POS = 2 +SX_PERF_SEL_CLOCK = 3 +SX_PERF_SEL_GATE_EN1 = 4 +SX_PERF_SEL_GATE_EN2 = 5 +SX_PERF_SEL_GATE_EN3 = 6 +SX_PERF_SEL_GATE_EN4 = 7 +SX_PERF_SEL_SH_POS_STARVE = 8 +SX_PERF_SEL_SH_COLOR_STARVE = 9 +SX_PERF_SEL_SH_POS_STALL = 10 +SX_PERF_SEL_SH_COLOR_STALL = 11 +SX_PERF_SEL_DB0_PIXELS = 12 +SX_PERF_SEL_DB0_HALF_QUADS = 13 +SX_PERF_SEL_DB0_PIXEL_STALL = 14 +SX_PERF_SEL_DB0_PIXEL_IDLE = 15 +SX_PERF_SEL_DB0_PRED_PIXELS = 16 +SX_PERF_SEL_DB1_PIXELS = 17 +SX_PERF_SEL_DB1_HALF_QUADS = 18 +SX_PERF_SEL_DB1_PIXEL_STALL = 19 +SX_PERF_SEL_DB1_PIXEL_IDLE = 20 +SX_PERF_SEL_DB1_PRED_PIXELS = 21 +SX_PERF_SEL_DB2_PIXELS = 22 +SX_PERF_SEL_DB2_HALF_QUADS = 23 +SX_PERF_SEL_DB2_PIXEL_STALL = 24 +SX_PERF_SEL_DB2_PIXEL_IDLE = 25 +SX_PERF_SEL_DB2_PRED_PIXELS = 26 +SX_PERF_SEL_DB3_PIXELS = 27 +SX_PERF_SEL_DB3_HALF_QUADS = 28 +SX_PERF_SEL_DB3_PIXEL_STALL = 29 +SX_PERF_SEL_DB3_PIXEL_IDLE = 30 +SX_PERF_SEL_DB3_PRED_PIXELS = 31 +SX_PERF_SEL_COL_BUSY = 32 +SX_PERF_SEL_POS_BUSY = 33 +SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 34 +SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 35 +SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 36 +SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 37 +SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 38 +SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 39 +SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 40 +SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 41 +SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 42 +SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 43 +SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 44 +SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 45 +SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 46 +SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 47 +SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 48 +SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 49 +SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 50 +SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 51 +SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 52 +SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 53 +SX_PERF_SEL_PA_REQ_LATENCY = 54 +SX_PERF_SEL_POS_SCBD_STALL = 55 +SX_PERF_SEL_CLOCK_DROP_STALL = 56 +SX_PERF_SEL_GATE_EN5 = 57 +SX_PERF_SEL_GATE_EN6 = 58 +SX_PERF_SEL_DB0_SIZE = 59 +SX_PERF_SEL_DB1_SIZE = 60 +SX_PERF_SEL_DB2_SIZE = 61 +SX_PERF_SEL_DB3_SIZE = 62 +SX_PERF_SEL_IDX_STALL_CYCLES = 63 +SX_PERF_SEL_IDX_IDLE_CYCLES = 64 +SX_PERF_SEL_IDX_REQ = 65 +SX_PERF_SEL_IDX_RET = 66 +SX_PERF_SEL_IDX_REQ_LATENCY = 67 +SX_PERF_SEL_IDX_SCBD_STALL = 68 +SX_PERF_SEL_GATE_EN7 = 69 +SX_PERF_SEL_GATE_EN8 = 70 +SX_PERF_SEL_SH_IDX_STARVE = 71 +SX_PERF_SEL_IDX_BUSY = 72 +SX_PERF_SEL_PA_POS_BANK_CONF = 73 +SX_PERF_SEL_DB0_END_OF_WAVE = 74 +SX_PERF_SEL_DB0_4X2_DISCARD = 75 +SX_PERF_SEL_DB1_END_OF_WAVE = 76 +SX_PERF_SEL_DB1_4X2_DISCARD = 77 +SX_PERF_SEL_DB2_END_OF_WAVE = 78 +SX_PERF_SEL_DB2_4X2_DISCARD = 79 +SX_PERF_SEL_DB3_END_OF_WAVE = 80 +SX_PERF_SEL_DB3_4X2_DISCARD = 81 +SX_PERFCOUNTER_VALS = ctypes.c_uint32 # enum + +# values for enumeration 'CompareFrag' +CompareFrag__enumvalues = { + 0: 'FRAG_NEVER', + 1: 'FRAG_LESS', + 2: 'FRAG_EQUAL', + 3: 'FRAG_LEQUAL', + 4: 'FRAG_GREATER', + 5: 'FRAG_NOTEQUAL', + 6: 'FRAG_GEQUAL', + 7: 'FRAG_ALWAYS', +} +FRAG_NEVER = 0 +FRAG_LESS = 1 +FRAG_EQUAL = 2 +FRAG_LEQUAL = 3 +FRAG_GREATER = 4 +FRAG_NOTEQUAL = 5 +FRAG_GEQUAL = 6 +FRAG_ALWAYS = 7 +CompareFrag = ctypes.c_uint32 # enum + +# values for enumeration 'ConservativeZExport' +ConservativeZExport__enumvalues = { + 0: 'EXPORT_ANY_Z', + 1: 'EXPORT_LESS_THAN_Z', + 2: 'EXPORT_GREATER_THAN_Z', + 3: 'EXPORT_RESERVED', +} +EXPORT_ANY_Z = 0 +EXPORT_LESS_THAN_Z = 1 +EXPORT_GREATER_THAN_Z = 2 +EXPORT_RESERVED = 3 +ConservativeZExport = ctypes.c_uint32 # enum + +# values for enumeration 'DFSMFlushEvents' +DFSMFlushEvents__enumvalues = { + 0: 'DB_FLUSH_AND_INV_DB_DATA_TS', + 1: 'DB_FLUSH_AND_INV_DB_META', + 2: 'DB_CACHE_FLUSH', + 3: 'DB_CACHE_FLUSH_TS', + 4: 'DB_CACHE_FLUSH_AND_INV_EVENT', + 5: 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', + 6: 'DB_VPORT_CHANGED_EVENT', + 7: 'DB_CONTEXT_DONE_EVENT', + 8: 'DB_BREAK_BATCH_EVENT', + 9: 'DB_INVOKE_CHANGE_EVENT', + 10: 'DB_CONTEXT_SUSPEND_EVENT', +} +DB_FLUSH_AND_INV_DB_DATA_TS = 0 +DB_FLUSH_AND_INV_DB_META = 1 +DB_CACHE_FLUSH = 2 +DB_CACHE_FLUSH_TS = 3 +DB_CACHE_FLUSH_AND_INV_EVENT = 4 +DB_CACHE_FLUSH_AND_INV_TS_EVENT = 5 +DB_VPORT_CHANGED_EVENT = 6 +DB_CONTEXT_DONE_EVENT = 7 +DB_BREAK_BATCH_EVENT = 8 +DB_INVOKE_CHANGE_EVENT = 9 +DB_CONTEXT_SUSPEND_EVENT = 10 +DFSMFlushEvents = ctypes.c_uint32 # enum + +# values for enumeration 'DbMemArbWatermarks' +DbMemArbWatermarks__enumvalues = { + 0: 'TRANSFERRED_64_BYTES', + 1: 'TRANSFERRED_128_BYTES', + 2: 'TRANSFERRED_256_BYTES', + 3: 'TRANSFERRED_512_BYTES', + 4: 'TRANSFERRED_1024_BYTES', + 5: 'TRANSFERRED_2048_BYTES', + 6: 'TRANSFERRED_4096_BYTES', + 7: 'TRANSFERRED_8192_BYTES', +} +TRANSFERRED_64_BYTES = 0 +TRANSFERRED_128_BYTES = 1 +TRANSFERRED_256_BYTES = 2 +TRANSFERRED_512_BYTES = 3 +TRANSFERRED_1024_BYTES = 4 +TRANSFERRED_2048_BYTES = 5 +TRANSFERRED_4096_BYTES = 6 +TRANSFERRED_8192_BYTES = 7 +DbMemArbWatermarks = ctypes.c_uint32 # enum + +# values for enumeration 'DbPRTFaultBehavior' +DbPRTFaultBehavior__enumvalues = { + 0: 'FAULT_ZERO', + 1: 'FAULT_ONE', + 2: 'FAULT_FAIL', + 3: 'FAULT_PASS', +} +FAULT_ZERO = 0 +FAULT_ONE = 1 +FAULT_FAIL = 2 +FAULT_PASS = 3 +DbPRTFaultBehavior = ctypes.c_uint32 # enum + +# values for enumeration 'DbPSLControl' +DbPSLControl__enumvalues = { + 0: 'PSLC_AUTO', + 1: 'PSLC_ON_HANG_ONLY', + 2: 'PSLC_ASAP', + 3: 'PSLC_COUNTDOWN', +} +PSLC_AUTO = 0 +PSLC_ON_HANG_ONLY = 1 +PSLC_ASAP = 2 +PSLC_COUNTDOWN = 3 +DbPSLControl = ctypes.c_uint32 # enum + +# values for enumeration 'ForceControl' +ForceControl__enumvalues = { + 0: 'FORCE_OFF', + 1: 'FORCE_ENABLE', + 2: 'FORCE_DISABLE', + 3: 'FORCE_RESERVED', +} +FORCE_OFF = 0 +FORCE_ENABLE = 1 +FORCE_DISABLE = 2 +FORCE_RESERVED = 3 +ForceControl = ctypes.c_uint32 # enum + +# values for enumeration 'OreoMode' +OreoMode__enumvalues = { + 0: 'OMODE_BLEND', + 1: 'OMODE_O_THEN_B', + 2: 'OMODE_P_THEN_O_THEN_B', + 3: 'OMODE_RESERVED_3', +} +OMODE_BLEND = 0 +OMODE_O_THEN_B = 1 +OMODE_P_THEN_O_THEN_B = 2 +OMODE_RESERVED_3 = 3 +OreoMode = ctypes.c_uint32 # enum + +# values for enumeration 'PerfCounter_Vals' +PerfCounter_Vals__enumvalues = { + 0: 'DB_PERF_SEL_SC_DB_tile_sends', + 1: 'DB_PERF_SEL_SC_DB_tile_busy', + 2: 'DB_PERF_SEL_SC_DB_tile_stalls', + 3: 'DB_PERF_SEL_SC_DB_tile_events', + 4: 'DB_PERF_SEL_SC_DB_tile_tiles', + 5: 'DB_PERF_SEL_SC_DB_tile_covered', + 6: 'DB_PERF_SEL_hiz_tc_read_starved', + 7: 'DB_PERF_SEL_hiz_tc_write_stall', + 8: 'DB_PERF_SEL_hiz_tile_culled', + 9: 'DB_PERF_SEL_his_tile_culled', + 10: 'DB_PERF_SEL_DB_SC_tile_sends', + 11: 'DB_PERF_SEL_DB_SC_tile_busy', + 12: 'DB_PERF_SEL_DB_SC_tile_stalls', + 13: 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 14: 'DB_PERF_SEL_DB_SC_tile_tiles', + 15: 'DB_PERF_SEL_DB_SC_tile_culled', + 16: 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 17: 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 18: 'DB_PERF_SEL_DB_SC_tile_no_ops', + 19: 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 20: 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 21: 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 22: 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 23: 'DB_PERF_SEL_SC_DB_quad_sends', + 24: 'DB_PERF_SEL_SC_DB_quad_busy', + 25: 'DB_PERF_SEL_SC_DB_quad_squads', + 26: 'DB_PERF_SEL_SC_DB_quad_tiles', + 27: 'DB_PERF_SEL_SC_DB_quad_pixels', + 28: 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 29: 'DB_PERF_SEL_DB_SC_quad_sends', + 30: 'DB_PERF_SEL_DB_SC_quad_busy', + 31: 'DB_PERF_SEL_DB_SC_quad_stalls', + 32: 'DB_PERF_SEL_DB_SC_quad_tiles', + 33: 'DB_PERF_SEL_DB_SC_quad_lit_quad', + 34: 'DB_PERF_SEL_DB_CB_tile_sends', + 35: 'DB_PERF_SEL_DB_CB_tile_busy', + 36: 'DB_PERF_SEL_DB_CB_tile_stalls', + 37: 'DB_PERF_SEL_SX_DB_quad_sends', + 38: 'DB_PERF_SEL_SX_DB_quad_busy', + 39: 'DB_PERF_SEL_SX_DB_quad_stalls', + 40: 'DB_PERF_SEL_SX_DB_quad_quads', + 41: 'DB_PERF_SEL_SX_DB_quad_pixels', + 42: 'DB_PERF_SEL_SX_DB_quad_exports', + 43: 'DB_PERF_SEL_SH_quads_outstanding_sum', + 44: 'DB_PERF_SEL_DB_CB_lquad_sends', + 45: 'DB_PERF_SEL_DB_CB_lquad_busy', + 46: 'DB_PERF_SEL_DB_CB_lquad_stalls', + 47: 'DB_PERF_SEL_DB_CB_lquad_quads', + 48: 'DB_PERF_SEL_tile_rd_sends', + 49: 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 50: 'DB_PERF_SEL_quad_rd_sends', + 51: 'DB_PERF_SEL_quad_rd_busy', + 52: 'DB_PERF_SEL_quad_rd_mi_stall', + 53: 'DB_PERF_SEL_quad_rd_rw_collision', + 54: 'DB_PERF_SEL_quad_rd_tag_stall', + 55: 'DB_PERF_SEL_quad_rd_32byte_reqs', + 56: 'DB_PERF_SEL_quad_rd_panic', + 57: 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 58: 'DB_PERF_SEL_quad_rdret_sends', + 59: 'DB_PERF_SEL_quad_rdret_busy', + 60: 'DB_PERF_SEL_tile_wr_sends', + 61: 'DB_PERF_SEL_tile_wr_acks', + 62: 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 63: 'DB_PERF_SEL_quad_wr_sends', + 64: 'DB_PERF_SEL_quad_wr_busy', + 65: 'DB_PERF_SEL_quad_wr_mi_stall', + 66: 'DB_PERF_SEL_quad_wr_coherency_stall', + 67: 'DB_PERF_SEL_quad_wr_acks', + 68: 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 69: 'DB_PERF_SEL_Tile_Cache_misses', + 70: 'DB_PERF_SEL_Tile_Cache_hits', + 71: 'DB_PERF_SEL_Tile_Cache_flushes', + 72: 'DB_PERF_SEL_Tile_Cache_surface_stall', + 73: 'DB_PERF_SEL_Tile_Cache_starves', + 74: 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 75: 'DB_PERF_SEL_tcp_dispatcher_reads', + 76: 'DB_PERF_SEL_tcp_prefetcher_reads', + 77: 'DB_PERF_SEL_tcp_preloader_reads', + 78: 'DB_PERF_SEL_tcp_dispatcher_flushes', + 79: 'DB_PERF_SEL_tcp_prefetcher_flushes', + 80: 'DB_PERF_SEL_tcp_preloader_flushes', + 81: 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 82: 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 83: 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 84: 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 85: 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 86: 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 87: 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 88: 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 89: 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 90: 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 91: 'DB_PERF_SEL_Depth_Tile_Cache_event', + 92: 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 93: 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 94: 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 95: 'DB_PERF_SEL_Stencil_Cache_misses', + 96: 'DB_PERF_SEL_Stencil_Cache_hits', + 97: 'DB_PERF_SEL_Stencil_Cache_flushes', + 98: 'DB_PERF_SEL_Stencil_Cache_starves', + 99: 'DB_PERF_SEL_Stencil_Cache_frees', + 100: 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 101: 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 102: 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 103: 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 104: 'DB_PERF_SEL_Z_Cache_pmask_misses', + 105: 'DB_PERF_SEL_Z_Cache_pmask_hits', + 106: 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 107: 'DB_PERF_SEL_Z_Cache_pmask_starves', + 108: 'DB_PERF_SEL_Z_Cache_frees', + 109: 'DB_PERF_SEL_Plane_Cache_misses', + 110: 'DB_PERF_SEL_Plane_Cache_hits', + 111: 'DB_PERF_SEL_Plane_Cache_flushes', + 112: 'DB_PERF_SEL_Plane_Cache_starves', + 113: 'DB_PERF_SEL_Plane_Cache_frees', + 114: 'DB_PERF_SEL_flush_expanded_stencil', + 115: 'DB_PERF_SEL_flush_compressed_stencil', + 116: 'DB_PERF_SEL_flush_single_stencil', + 117: 'DB_PERF_SEL_planes_flushed', + 118: 'DB_PERF_SEL_flush_1plane', + 119: 'DB_PERF_SEL_flush_2plane', + 120: 'DB_PERF_SEL_flush_3plane', + 121: 'DB_PERF_SEL_flush_4plane', + 122: 'DB_PERF_SEL_flush_5plane', + 123: 'DB_PERF_SEL_flush_6plane', + 124: 'DB_PERF_SEL_flush_7plane', + 125: 'DB_PERF_SEL_flush_8plane', + 126: 'DB_PERF_SEL_flush_9plane', + 127: 'DB_PERF_SEL_flush_10plane', + 128: 'DB_PERF_SEL_flush_11plane', + 129: 'DB_PERF_SEL_flush_12plane', + 130: 'DB_PERF_SEL_flush_13plane', + 131: 'DB_PERF_SEL_flush_14plane', + 132: 'DB_PERF_SEL_flush_15plane', + 133: 'DB_PERF_SEL_flush_16plane', + 134: 'DB_PERF_SEL_flush_expanded_z', + 135: 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 136: 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 137: 'DB_PERF_SEL_dk_tile_sends', + 138: 'DB_PERF_SEL_dk_tile_busy', + 139: 'DB_PERF_SEL_dk_tile_quad_starves', + 140: 'DB_PERF_SEL_dk_tile_stalls', + 141: 'DB_PERF_SEL_dk_squad_sends', + 142: 'DB_PERF_SEL_dk_squad_busy', + 143: 'DB_PERF_SEL_dk_squad_stalls', + 144: 'DB_PERF_SEL_Op_Pipe_Busy', + 145: 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 146: 'DB_PERF_SEL_qc_busy', + 147: 'DB_PERF_SEL_qc_xfc', + 148: 'DB_PERF_SEL_qc_conflicts', + 149: 'DB_PERF_SEL_qc_full_stall', + 150: 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', + 151: 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 152: 'DB_PERF_SEL_tsc_insert_summarize_stall', + 153: 'DB_PERF_SEL_tl_busy', + 154: 'DB_PERF_SEL_tl_dtc_read_starved', + 155: 'DB_PERF_SEL_tl_z_fetch_stall', + 156: 'DB_PERF_SEL_tl_stencil_stall', + 157: 'DB_PERF_SEL_tl_z_decompress_stall', + 158: 'DB_PERF_SEL_tl_stencil_locked_stall', + 159: 'DB_PERF_SEL_tl_events', + 160: 'DB_PERF_SEL_tl_summarize_squads', + 161: 'DB_PERF_SEL_tl_flush_expand_squads', + 162: 'DB_PERF_SEL_tl_expand_squads', + 163: 'DB_PERF_SEL_tl_preZ_squads', + 164: 'DB_PERF_SEL_tl_postZ_squads', + 165: 'DB_PERF_SEL_tl_preZ_noop_squads', + 166: 'DB_PERF_SEL_tl_postZ_noop_squads', + 167: 'DB_PERF_SEL_tl_tile_ops', + 168: 'DB_PERF_SEL_tl_in_xfc', + 169: 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 170: 'DB_PERF_SEL_tl_in_fast_z_stall', + 171: 'DB_PERF_SEL_tl_out_xfc', + 172: 'DB_PERF_SEL_tl_out_squads', + 173: 'DB_PERF_SEL_zf_plane_multicycle', + 174: 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 175: 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 176: 'DB_PERF_SEL_PostZ_Samples_failing_S', + 177: 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 178: 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 179: 'DB_PERF_SEL_PreZ_Samples_failing_S', + 180: 'DB_PERF_SEL_ts_tc_update_stall', + 181: 'DB_PERF_SEL_sc_kick_start', + 182: 'DB_PERF_SEL_sc_kick_end', + 183: 'DB_PERF_SEL_clock_reg_active', + 184: 'DB_PERF_SEL_clock_main_active', + 185: 'DB_PERF_SEL_clock_mem_export_active', + 186: 'DB_PERF_SEL_esr_ps_out_busy', + 187: 'DB_PERF_SEL_esr_ps_lqf_busy', + 188: 'DB_PERF_SEL_esr_ps_lqf_stall', + 189: 'DB_PERF_SEL_etr_out_send', + 190: 'DB_PERF_SEL_etr_out_busy', + 191: 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 192: 'DB_PERF_SEL_etr_out_cb_tile_stall', + 193: 'DB_PERF_SEL_etr_out_esr_stall', + 194: 'DB_PERF_SEL_esr_ps_vic_busy', + 195: 'DB_PERF_SEL_esr_ps_vic_stall', + 196: 'DB_PERF_SEL_esr_eot_fwd_busy', + 197: 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 198: 'DB_PERF_SEL_esr_eot_fwd_forward', + 199: 'DB_PERF_SEL_esr_sqq_zi_busy', + 200: 'DB_PERF_SEL_esr_sqq_zi_stall', + 201: 'DB_PERF_SEL_postzl_sq_pt_busy', + 202: 'DB_PERF_SEL_postzl_sq_pt_stall', + 203: 'DB_PERF_SEL_postzl_se_busy', + 204: 'DB_PERF_SEL_postzl_se_stall', + 205: 'DB_PERF_SEL_postzl_partial_launch', + 206: 'DB_PERF_SEL_postzl_full_launch', + 207: 'DB_PERF_SEL_postzl_partial_waiting', + 208: 'DB_PERF_SEL_postzl_tile_mem_stall', + 209: 'DB_PERF_SEL_postzl_tile_init_stall', + 210: 'DB_PERF_SEL_prezl_tile_mem_stall', + 211: 'DB_PERF_SEL_prezl_tile_init_stall', + 212: 'DB_PERF_SEL_dtt_sm_clash_stall', + 213: 'DB_PERF_SEL_dtt_sm_slot_stall', + 214: 'DB_PERF_SEL_dtt_sm_miss_stall', + 215: 'DB_PERF_SEL_mi_rdreq_busy', + 216: 'DB_PERF_SEL_mi_rdreq_stall', + 217: 'DB_PERF_SEL_mi_wrreq_busy', + 218: 'DB_PERF_SEL_mi_wrreq_stall', + 219: 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 220: 'DB_PERF_SEL_dkg_tile_rate_tile', + 221: 'DB_PERF_SEL_prezl_src_in_sends', + 222: 'DB_PERF_SEL_prezl_src_in_stall', + 223: 'DB_PERF_SEL_prezl_src_in_squads', + 224: 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 225: 'DB_PERF_SEL_prezl_src_in_tile_rate', + 226: 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 227: 'DB_PERF_SEL_prezl_src_out_stall', + 228: 'DB_PERF_SEL_postzl_src_in_sends', + 229: 'DB_PERF_SEL_postzl_src_in_stall', + 230: 'DB_PERF_SEL_postzl_src_in_squads', + 231: 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 232: 'DB_PERF_SEL_postzl_src_in_tile_rate', + 233: 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 234: 'DB_PERF_SEL_postzl_src_out_stall', + 235: 'DB_PERF_SEL_esr_ps_src_in_sends', + 236: 'DB_PERF_SEL_esr_ps_src_in_stall', + 237: 'DB_PERF_SEL_esr_ps_src_in_squads', + 238: 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 239: 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 240: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 241: 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 242: 'DB_PERF_SEL_esr_ps_src_out_stall', + 243: 'DB_PERF_SEL_depth_bounds_tile_culled', + 244: 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 245: 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 246: 'DB_PERF_SEL_flush_compressed', + 247: 'DB_PERF_SEL_flush_plane_le4', + 248: 'DB_PERF_SEL_tiles_z_fully_summarized', + 249: 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 250: 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 251: 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 252: 'DB_PERF_SEL_tiles_decomp_on_expclear', + 253: 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 254: 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 255: 'DB_PERF_SEL_Op_Pipe_Postz_Busy', + 256: 'DB_PERF_SEL_di_dt_stall', + 257: 'Spare_257', + 258: 'DB_PERF_SEL_DB_SC_s_tile_rate', + 259: 'DB_PERF_SEL_DB_SC_c_tile_rate', + 260: 'DB_PERF_SEL_DB_SC_z_tile_rate', + 261: 'DB_PERF_SEL_DB_CB_lquad_export_quads', + 262: 'DB_PERF_SEL_DB_CB_lquad_double_format', + 263: 'DB_PERF_SEL_DB_CB_lquad_fast_format', + 264: 'DB_PERF_SEL_DB_CB_lquad_slow_format', + 265: 'DB_PERF_SEL_CB_DB_rdreq_sends', + 266: 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 267: 'DB_PERF_SEL_CB_DB_wrreq_sends', + 268: 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 269: 'DB_PERF_SEL_DB_CB_rdret_ack', + 270: 'DB_PERF_SEL_DB_CB_rdret_nack', + 271: 'DB_PERF_SEL_DB_CB_wrret_ack', + 272: 'DB_PERF_SEL_DB_CB_wrret_nack', + 273: 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', + 274: 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', + 275: 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', + 276: 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', + 277: 'DB_PERF_SEL_unmapped_z_tile_culled', + 278: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', + 279: 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', + 280: 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', + 281: 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', + 282: 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', + 283: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', + 284: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', + 285: 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', + 286: 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', + 287: 'DB_PERF_SEL_DB_CB_context_dones', + 288: 'DB_PERF_SEL_DB_CB_eop_dones', + 289: 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', + 290: 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', + 291: 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', + 292: 'DB_PERF_SEL_SC_DB_tile_backface', + 293: 'DB_PERF_SEL_SC_DB_quad_quads', + 294: 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', + 295: 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', + 296: 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', + 297: 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', + 298: 'DB_PERF_SEL_DB_SC_quad_double_quad', + 299: 'DB_PERF_SEL_SX_DB_quad_export_quads', + 300: 'DB_PERF_SEL_SX_DB_quad_double_format', + 301: 'DB_PERF_SEL_SX_DB_quad_fast_format', + 302: 'DB_PERF_SEL_SX_DB_quad_slow_format', + 303: 'DB_PERF_SEL_quad_rd_sends_unc', + 304: 'DB_PERF_SEL_quad_rd_mi_stall_unc', + 305: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', + 306: 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', + 307: 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', + 308: 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', + 309: 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', + 310: 'DB_PERF_SEL_noz_waiting_for_postz_done', + 311: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1', + 312: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1', + 313: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2', + 314: 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2', + 315: 'DB_PERF_SEL_RMI_rd_tile_32byte_req', + 316: 'DB_PERF_SEL_RMI_rd_z_32byte_req', + 317: 'DB_PERF_SEL_RMI_rd_s_32byte_req', + 318: 'DB_PERF_SEL_RMI_wr_tile_32byte_req', + 319: 'DB_PERF_SEL_RMI_wr_z_32byte_req', + 320: 'DB_PERF_SEL_RMI_wr_s_32byte_req', + 321: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', + 322: 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', + 323: 'DB_PERF_SEL_RMI_rd_z_32byte_ret', + 324: 'DB_PERF_SEL_RMI_rd_s_32byte_ret', + 325: 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', + 326: 'DB_PERF_SEL_RMI_wr_z_32byte_ack', + 327: 'DB_PERF_SEL_RMI_wr_s_32byte_ack', + 328: 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', + 329: 'DB_PERF_SEL_esr_vic_sqq_busy', + 330: 'DB_PERF_SEL_esr_vic_sqq_stall', + 331: 'DB_PERF_SEL_esr_psi_vic_tile_rate', + 332: 'DB_PERF_SEL_esr_vic_footprint_match_2x2', + 333: 'DB_PERF_SEL_esr_vic_footprint_match_2x1', + 334: 'DB_PERF_SEL_esr_vic_footprint_match_1x2', + 335: 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', + 336: 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', + 337: 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', + 338: 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', + 339: 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', + 340: 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', + 341: 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', + 342: 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', + 343: 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', + 344: 'DB_PERF_SEL_ts_events_pws_enable', + 345: 'DB_PERF_SEL_ps_events_pws_enable', + 346: 'DB_PERF_SEL_cs_events_pws_enable', + 347: 'DB_PERF_SEL_DB_SC_quad_noz_tiles', + 348: 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', +} +DB_PERF_SEL_SC_DB_tile_sends = 0 +DB_PERF_SEL_SC_DB_tile_busy = 1 +DB_PERF_SEL_SC_DB_tile_stalls = 2 +DB_PERF_SEL_SC_DB_tile_events = 3 +DB_PERF_SEL_SC_DB_tile_tiles = 4 +DB_PERF_SEL_SC_DB_tile_covered = 5 +DB_PERF_SEL_hiz_tc_read_starved = 6 +DB_PERF_SEL_hiz_tc_write_stall = 7 +DB_PERF_SEL_hiz_tile_culled = 8 +DB_PERF_SEL_his_tile_culled = 9 +DB_PERF_SEL_DB_SC_tile_sends = 10 +DB_PERF_SEL_DB_SC_tile_busy = 11 +DB_PERF_SEL_DB_SC_tile_stalls = 12 +DB_PERF_SEL_DB_SC_tile_df_stalls = 13 +DB_PERF_SEL_DB_SC_tile_tiles = 14 +DB_PERF_SEL_DB_SC_tile_culled = 15 +DB_PERF_SEL_DB_SC_tile_hier_kill = 16 +DB_PERF_SEL_DB_SC_tile_fast_ops = 17 +DB_PERF_SEL_DB_SC_tile_no_ops = 18 +DB_PERF_SEL_DB_SC_tile_tile_rate = 19 +DB_PERF_SEL_DB_SC_tile_ssaa_kill = 20 +DB_PERF_SEL_DB_SC_tile_fast_z_ops = 21 +DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 22 +DB_PERF_SEL_SC_DB_quad_sends = 23 +DB_PERF_SEL_SC_DB_quad_busy = 24 +DB_PERF_SEL_SC_DB_quad_squads = 25 +DB_PERF_SEL_SC_DB_quad_tiles = 26 +DB_PERF_SEL_SC_DB_quad_pixels = 27 +DB_PERF_SEL_SC_DB_quad_killed_tiles = 28 +DB_PERF_SEL_DB_SC_quad_sends = 29 +DB_PERF_SEL_DB_SC_quad_busy = 30 +DB_PERF_SEL_DB_SC_quad_stalls = 31 +DB_PERF_SEL_DB_SC_quad_tiles = 32 +DB_PERF_SEL_DB_SC_quad_lit_quad = 33 +DB_PERF_SEL_DB_CB_tile_sends = 34 +DB_PERF_SEL_DB_CB_tile_busy = 35 +DB_PERF_SEL_DB_CB_tile_stalls = 36 +DB_PERF_SEL_SX_DB_quad_sends = 37 +DB_PERF_SEL_SX_DB_quad_busy = 38 +DB_PERF_SEL_SX_DB_quad_stalls = 39 +DB_PERF_SEL_SX_DB_quad_quads = 40 +DB_PERF_SEL_SX_DB_quad_pixels = 41 +DB_PERF_SEL_SX_DB_quad_exports = 42 +DB_PERF_SEL_SH_quads_outstanding_sum = 43 +DB_PERF_SEL_DB_CB_lquad_sends = 44 +DB_PERF_SEL_DB_CB_lquad_busy = 45 +DB_PERF_SEL_DB_CB_lquad_stalls = 46 +DB_PERF_SEL_DB_CB_lquad_quads = 47 +DB_PERF_SEL_tile_rd_sends = 48 +DB_PERF_SEL_mi_tile_rd_outstanding_sum = 49 +DB_PERF_SEL_quad_rd_sends = 50 +DB_PERF_SEL_quad_rd_busy = 51 +DB_PERF_SEL_quad_rd_mi_stall = 52 +DB_PERF_SEL_quad_rd_rw_collision = 53 +DB_PERF_SEL_quad_rd_tag_stall = 54 +DB_PERF_SEL_quad_rd_32byte_reqs = 55 +DB_PERF_SEL_quad_rd_panic = 56 +DB_PERF_SEL_mi_quad_rd_outstanding_sum = 57 +DB_PERF_SEL_quad_rdret_sends = 58 +DB_PERF_SEL_quad_rdret_busy = 59 +DB_PERF_SEL_tile_wr_sends = 60 +DB_PERF_SEL_tile_wr_acks = 61 +DB_PERF_SEL_mi_tile_wr_outstanding_sum = 62 +DB_PERF_SEL_quad_wr_sends = 63 +DB_PERF_SEL_quad_wr_busy = 64 +DB_PERF_SEL_quad_wr_mi_stall = 65 +DB_PERF_SEL_quad_wr_coherency_stall = 66 +DB_PERF_SEL_quad_wr_acks = 67 +DB_PERF_SEL_mi_quad_wr_outstanding_sum = 68 +DB_PERF_SEL_Tile_Cache_misses = 69 +DB_PERF_SEL_Tile_Cache_hits = 70 +DB_PERF_SEL_Tile_Cache_flushes = 71 +DB_PERF_SEL_Tile_Cache_surface_stall = 72 +DB_PERF_SEL_Tile_Cache_starves = 73 +DB_PERF_SEL_Tile_Cache_mem_return_starve = 74 +DB_PERF_SEL_tcp_dispatcher_reads = 75 +DB_PERF_SEL_tcp_prefetcher_reads = 76 +DB_PERF_SEL_tcp_preloader_reads = 77 +DB_PERF_SEL_tcp_dispatcher_flushes = 78 +DB_PERF_SEL_tcp_prefetcher_flushes = 79 +DB_PERF_SEL_tcp_preloader_flushes = 80 +DB_PERF_SEL_Depth_Tile_Cache_sends = 81 +DB_PERF_SEL_Depth_Tile_Cache_busy = 82 +DB_PERF_SEL_Depth_Tile_Cache_starves = 83 +DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 84 +DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 85 +DB_PERF_SEL_Depth_Tile_Cache_misses = 86 +DB_PERF_SEL_Depth_Tile_Cache_hits = 87 +DB_PERF_SEL_Depth_Tile_Cache_flushes = 88 +DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 89 +DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 90 +DB_PERF_SEL_Depth_Tile_Cache_event = 91 +DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 92 +DB_PERF_SEL_Depth_Tile_Cache_data_frees = 93 +DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 94 +DB_PERF_SEL_Stencil_Cache_misses = 95 +DB_PERF_SEL_Stencil_Cache_hits = 96 +DB_PERF_SEL_Stencil_Cache_flushes = 97 +DB_PERF_SEL_Stencil_Cache_starves = 98 +DB_PERF_SEL_Stencil_Cache_frees = 99 +DB_PERF_SEL_Z_Cache_separate_Z_misses = 100 +DB_PERF_SEL_Z_Cache_separate_Z_hits = 101 +DB_PERF_SEL_Z_Cache_separate_Z_flushes = 102 +DB_PERF_SEL_Z_Cache_separate_Z_starves = 103 +DB_PERF_SEL_Z_Cache_pmask_misses = 104 +DB_PERF_SEL_Z_Cache_pmask_hits = 105 +DB_PERF_SEL_Z_Cache_pmask_flushes = 106 +DB_PERF_SEL_Z_Cache_pmask_starves = 107 +DB_PERF_SEL_Z_Cache_frees = 108 +DB_PERF_SEL_Plane_Cache_misses = 109 +DB_PERF_SEL_Plane_Cache_hits = 110 +DB_PERF_SEL_Plane_Cache_flushes = 111 +DB_PERF_SEL_Plane_Cache_starves = 112 +DB_PERF_SEL_Plane_Cache_frees = 113 +DB_PERF_SEL_flush_expanded_stencil = 114 +DB_PERF_SEL_flush_compressed_stencil = 115 +DB_PERF_SEL_flush_single_stencil = 116 +DB_PERF_SEL_planes_flushed = 117 +DB_PERF_SEL_flush_1plane = 118 +DB_PERF_SEL_flush_2plane = 119 +DB_PERF_SEL_flush_3plane = 120 +DB_PERF_SEL_flush_4plane = 121 +DB_PERF_SEL_flush_5plane = 122 +DB_PERF_SEL_flush_6plane = 123 +DB_PERF_SEL_flush_7plane = 124 +DB_PERF_SEL_flush_8plane = 125 +DB_PERF_SEL_flush_9plane = 126 +DB_PERF_SEL_flush_10plane = 127 +DB_PERF_SEL_flush_11plane = 128 +DB_PERF_SEL_flush_12plane = 129 +DB_PERF_SEL_flush_13plane = 130 +DB_PERF_SEL_flush_14plane = 131 +DB_PERF_SEL_flush_15plane = 132 +DB_PERF_SEL_flush_16plane = 133 +DB_PERF_SEL_flush_expanded_z = 134 +DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 135 +DB_PERF_SEL_reZ_waiting_for_postZ_done = 136 +DB_PERF_SEL_dk_tile_sends = 137 +DB_PERF_SEL_dk_tile_busy = 138 +DB_PERF_SEL_dk_tile_quad_starves = 139 +DB_PERF_SEL_dk_tile_stalls = 140 +DB_PERF_SEL_dk_squad_sends = 141 +DB_PERF_SEL_dk_squad_busy = 142 +DB_PERF_SEL_dk_squad_stalls = 143 +DB_PERF_SEL_Op_Pipe_Busy = 144 +DB_PERF_SEL_Op_Pipe_MC_Read_stall = 145 +DB_PERF_SEL_qc_busy = 146 +DB_PERF_SEL_qc_xfc = 147 +DB_PERF_SEL_qc_conflicts = 148 +DB_PERF_SEL_qc_full_stall = 149 +DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 150 +DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 151 +DB_PERF_SEL_tsc_insert_summarize_stall = 152 +DB_PERF_SEL_tl_busy = 153 +DB_PERF_SEL_tl_dtc_read_starved = 154 +DB_PERF_SEL_tl_z_fetch_stall = 155 +DB_PERF_SEL_tl_stencil_stall = 156 +DB_PERF_SEL_tl_z_decompress_stall = 157 +DB_PERF_SEL_tl_stencil_locked_stall = 158 +DB_PERF_SEL_tl_events = 159 +DB_PERF_SEL_tl_summarize_squads = 160 +DB_PERF_SEL_tl_flush_expand_squads = 161 +DB_PERF_SEL_tl_expand_squads = 162 +DB_PERF_SEL_tl_preZ_squads = 163 +DB_PERF_SEL_tl_postZ_squads = 164 +DB_PERF_SEL_tl_preZ_noop_squads = 165 +DB_PERF_SEL_tl_postZ_noop_squads = 166 +DB_PERF_SEL_tl_tile_ops = 167 +DB_PERF_SEL_tl_in_xfc = 168 +DB_PERF_SEL_tl_in_single_stencil_expand_stall = 169 +DB_PERF_SEL_tl_in_fast_z_stall = 170 +DB_PERF_SEL_tl_out_xfc = 171 +DB_PERF_SEL_tl_out_squads = 172 +DB_PERF_SEL_zf_plane_multicycle = 173 +DB_PERF_SEL_PostZ_Samples_passing_Z = 174 +DB_PERF_SEL_PostZ_Samples_failing_Z = 175 +DB_PERF_SEL_PostZ_Samples_failing_S = 176 +DB_PERF_SEL_PreZ_Samples_passing_Z = 177 +DB_PERF_SEL_PreZ_Samples_failing_Z = 178 +DB_PERF_SEL_PreZ_Samples_failing_S = 179 +DB_PERF_SEL_ts_tc_update_stall = 180 +DB_PERF_SEL_sc_kick_start = 181 +DB_PERF_SEL_sc_kick_end = 182 +DB_PERF_SEL_clock_reg_active = 183 +DB_PERF_SEL_clock_main_active = 184 +DB_PERF_SEL_clock_mem_export_active = 185 +DB_PERF_SEL_esr_ps_out_busy = 186 +DB_PERF_SEL_esr_ps_lqf_busy = 187 +DB_PERF_SEL_esr_ps_lqf_stall = 188 +DB_PERF_SEL_etr_out_send = 189 +DB_PERF_SEL_etr_out_busy = 190 +DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 191 +DB_PERF_SEL_etr_out_cb_tile_stall = 192 +DB_PERF_SEL_etr_out_esr_stall = 193 +DB_PERF_SEL_esr_ps_vic_busy = 194 +DB_PERF_SEL_esr_ps_vic_stall = 195 +DB_PERF_SEL_esr_eot_fwd_busy = 196 +DB_PERF_SEL_esr_eot_fwd_holding_squad = 197 +DB_PERF_SEL_esr_eot_fwd_forward = 198 +DB_PERF_SEL_esr_sqq_zi_busy = 199 +DB_PERF_SEL_esr_sqq_zi_stall = 200 +DB_PERF_SEL_postzl_sq_pt_busy = 201 +DB_PERF_SEL_postzl_sq_pt_stall = 202 +DB_PERF_SEL_postzl_se_busy = 203 +DB_PERF_SEL_postzl_se_stall = 204 +DB_PERF_SEL_postzl_partial_launch = 205 +DB_PERF_SEL_postzl_full_launch = 206 +DB_PERF_SEL_postzl_partial_waiting = 207 +DB_PERF_SEL_postzl_tile_mem_stall = 208 +DB_PERF_SEL_postzl_tile_init_stall = 209 +DB_PERF_SEL_prezl_tile_mem_stall = 210 +DB_PERF_SEL_prezl_tile_init_stall = 211 +DB_PERF_SEL_dtt_sm_clash_stall = 212 +DB_PERF_SEL_dtt_sm_slot_stall = 213 +DB_PERF_SEL_dtt_sm_miss_stall = 214 +DB_PERF_SEL_mi_rdreq_busy = 215 +DB_PERF_SEL_mi_rdreq_stall = 216 +DB_PERF_SEL_mi_wrreq_busy = 217 +DB_PERF_SEL_mi_wrreq_stall = 218 +DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 219 +DB_PERF_SEL_dkg_tile_rate_tile = 220 +DB_PERF_SEL_prezl_src_in_sends = 221 +DB_PERF_SEL_prezl_src_in_stall = 222 +DB_PERF_SEL_prezl_src_in_squads = 223 +DB_PERF_SEL_prezl_src_in_squads_unrolled = 224 +DB_PERF_SEL_prezl_src_in_tile_rate = 225 +DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 226 +DB_PERF_SEL_prezl_src_out_stall = 227 +DB_PERF_SEL_postzl_src_in_sends = 228 +DB_PERF_SEL_postzl_src_in_stall = 229 +DB_PERF_SEL_postzl_src_in_squads = 230 +DB_PERF_SEL_postzl_src_in_squads_unrolled = 231 +DB_PERF_SEL_postzl_src_in_tile_rate = 232 +DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 233 +DB_PERF_SEL_postzl_src_out_stall = 234 +DB_PERF_SEL_esr_ps_src_in_sends = 235 +DB_PERF_SEL_esr_ps_src_in_stall = 236 +DB_PERF_SEL_esr_ps_src_in_squads = 237 +DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 238 +DB_PERF_SEL_esr_ps_src_in_tile_rate = 239 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 240 +DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 241 +DB_PERF_SEL_esr_ps_src_out_stall = 242 +DB_PERF_SEL_depth_bounds_tile_culled = 243 +DB_PERF_SEL_PreZ_Samples_failing_DB = 244 +DB_PERF_SEL_PostZ_Samples_failing_DB = 245 +DB_PERF_SEL_flush_compressed = 246 +DB_PERF_SEL_flush_plane_le4 = 247 +DB_PERF_SEL_tiles_z_fully_summarized = 248 +DB_PERF_SEL_tiles_stencil_fully_summarized = 249 +DB_PERF_SEL_tiles_z_clear_on_expclear = 250 +DB_PERF_SEL_tiles_s_clear_on_expclear = 251 +DB_PERF_SEL_tiles_decomp_on_expclear = 252 +DB_PERF_SEL_tiles_compressed_to_decompressed = 253 +DB_PERF_SEL_Op_Pipe_Prez_Busy = 254 +DB_PERF_SEL_Op_Pipe_Postz_Busy = 255 +DB_PERF_SEL_di_dt_stall = 256 +Spare_257 = 257 +DB_PERF_SEL_DB_SC_s_tile_rate = 258 +DB_PERF_SEL_DB_SC_c_tile_rate = 259 +DB_PERF_SEL_DB_SC_z_tile_rate = 260 +DB_PERF_SEL_DB_CB_lquad_export_quads = 261 +DB_PERF_SEL_DB_CB_lquad_double_format = 262 +DB_PERF_SEL_DB_CB_lquad_fast_format = 263 +DB_PERF_SEL_DB_CB_lquad_slow_format = 264 +DB_PERF_SEL_CB_DB_rdreq_sends = 265 +DB_PERF_SEL_CB_DB_rdreq_prt_sends = 266 +DB_PERF_SEL_CB_DB_wrreq_sends = 267 +DB_PERF_SEL_CB_DB_wrreq_prt_sends = 268 +DB_PERF_SEL_DB_CB_rdret_ack = 269 +DB_PERF_SEL_DB_CB_rdret_nack = 270 +DB_PERF_SEL_DB_CB_wrret_ack = 271 +DB_PERF_SEL_DB_CB_wrret_nack = 272 +DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 273 +DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 274 +DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 275 +DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 276 +DB_PERF_SEL_unmapped_z_tile_culled = 277 +DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 278 +DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 279 +DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 280 +DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 281 +DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 282 +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 283 +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 284 +DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 285 +DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 286 +DB_PERF_SEL_DB_CB_context_dones = 287 +DB_PERF_SEL_DB_CB_eop_dones = 288 +DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 289 +DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 290 +DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 291 +DB_PERF_SEL_SC_DB_tile_backface = 292 +DB_PERF_SEL_SC_DB_quad_quads = 293 +DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 294 +DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 295 +DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 296 +DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 297 +DB_PERF_SEL_DB_SC_quad_double_quad = 298 +DB_PERF_SEL_SX_DB_quad_export_quads = 299 +DB_PERF_SEL_SX_DB_quad_double_format = 300 +DB_PERF_SEL_SX_DB_quad_fast_format = 301 +DB_PERF_SEL_SX_DB_quad_slow_format = 302 +DB_PERF_SEL_quad_rd_sends_unc = 303 +DB_PERF_SEL_quad_rd_mi_stall_unc = 304 +DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 305 +DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 306 +DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 307 +DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 308 +DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 309 +DB_PERF_SEL_noz_waiting_for_postz_done = 310 +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1 = 311 +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1 = 312 +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2 = 313 +DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2 = 314 +DB_PERF_SEL_RMI_rd_tile_32byte_req = 315 +DB_PERF_SEL_RMI_rd_z_32byte_req = 316 +DB_PERF_SEL_RMI_rd_s_32byte_req = 317 +DB_PERF_SEL_RMI_wr_tile_32byte_req = 318 +DB_PERF_SEL_RMI_wr_z_32byte_req = 319 +DB_PERF_SEL_RMI_wr_s_32byte_req = 320 +DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 321 +DB_PERF_SEL_RMI_rd_tile_32byte_ret = 322 +DB_PERF_SEL_RMI_rd_z_32byte_ret = 323 +DB_PERF_SEL_RMI_rd_s_32byte_ret = 324 +DB_PERF_SEL_RMI_wr_tile_32byte_ack = 325 +DB_PERF_SEL_RMI_wr_z_32byte_ack = 326 +DB_PERF_SEL_RMI_wr_s_32byte_ack = 327 +DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 328 +DB_PERF_SEL_esr_vic_sqq_busy = 329 +DB_PERF_SEL_esr_vic_sqq_stall = 330 +DB_PERF_SEL_esr_psi_vic_tile_rate = 331 +DB_PERF_SEL_esr_vic_footprint_match_2x2 = 332 +DB_PERF_SEL_esr_vic_footprint_match_2x1 = 333 +DB_PERF_SEL_esr_vic_footprint_match_1x2 = 334 +DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 335 +DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 336 +DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 337 +DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 338 +DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 339 +DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 340 +DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 341 +DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 342 +DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 343 +DB_PERF_SEL_ts_events_pws_enable = 344 +DB_PERF_SEL_ps_events_pws_enable = 345 +DB_PERF_SEL_cs_events_pws_enable = 346 +DB_PERF_SEL_DB_SC_quad_noz_tiles = 347 +DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 348 +PerfCounter_Vals = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeCounterId' +PixelPipeCounterId__enumvalues = { + 0: 'PIXEL_PIPE_OCCLUSION_COUNT_0', + 1: 'PIXEL_PIPE_OCCLUSION_COUNT_1', + 2: 'PIXEL_PIPE_OCCLUSION_COUNT_2', + 3: 'PIXEL_PIPE_OCCLUSION_COUNT_3', + 4: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 5: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 6: 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', + 7: 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', +} +PIXEL_PIPE_OCCLUSION_COUNT_0 = 0 +PIXEL_PIPE_OCCLUSION_COUNT_1 = 1 +PIXEL_PIPE_OCCLUSION_COUNT_2 = 2 +PIXEL_PIPE_OCCLUSION_COUNT_3 = 3 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 4 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 5 +PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 6 +PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 7 +PixelPipeCounterId = ctypes.c_uint32 # enum + +# values for enumeration 'PixelPipeStride' +PixelPipeStride__enumvalues = { + 0: 'PIXEL_PIPE_STRIDE_32_BITS', + 1: 'PIXEL_PIPE_STRIDE_64_BITS', + 2: 'PIXEL_PIPE_STRIDE_128_BITS', + 3: 'PIXEL_PIPE_STRIDE_256_BITS', +} +PIXEL_PIPE_STRIDE_32_BITS = 0 +PIXEL_PIPE_STRIDE_64_BITS = 1 +PIXEL_PIPE_STRIDE_128_BITS = 2 +PIXEL_PIPE_STRIDE_256_BITS = 3 +PixelPipeStride = ctypes.c_uint32 # enum + +# values for enumeration 'RingCounterControl' +RingCounterControl__enumvalues = { + 0: 'COUNTER_RING_SPLIT', + 1: 'COUNTER_RING_0', + 2: 'COUNTER_RING_1', +} +COUNTER_RING_SPLIT = 0 +COUNTER_RING_0 = 1 +COUNTER_RING_1 = 2 +RingCounterControl = ctypes.c_uint32 # enum + +# values for enumeration 'StencilOp' +StencilOp__enumvalues = { + 0: 'STENCIL_KEEP', + 1: 'STENCIL_ZERO', + 2: 'STENCIL_ONES', + 3: 'STENCIL_REPLACE_TEST', + 4: 'STENCIL_REPLACE_OP', + 5: 'STENCIL_ADD_CLAMP', + 6: 'STENCIL_SUB_CLAMP', + 7: 'STENCIL_INVERT', + 8: 'STENCIL_ADD_WRAP', + 9: 'STENCIL_SUB_WRAP', + 10: 'STENCIL_AND', + 11: 'STENCIL_OR', + 12: 'STENCIL_XOR', + 13: 'STENCIL_NAND', + 14: 'STENCIL_NOR', + 15: 'STENCIL_XNOR', +} +STENCIL_KEEP = 0 +STENCIL_ZERO = 1 +STENCIL_ONES = 2 +STENCIL_REPLACE_TEST = 3 +STENCIL_REPLACE_OP = 4 +STENCIL_ADD_CLAMP = 5 +STENCIL_SUB_CLAMP = 6 +STENCIL_INVERT = 7 +STENCIL_ADD_WRAP = 8 +STENCIL_SUB_WRAP = 9 +STENCIL_AND = 10 +STENCIL_OR = 11 +STENCIL_XOR = 12 +STENCIL_NAND = 13 +STENCIL_NOR = 14 +STENCIL_XNOR = 15 +StencilOp = ctypes.c_uint32 # enum + +# values for enumeration 'ZLimitSumm' +ZLimitSumm__enumvalues = { + 0: 'FORCE_SUMM_OFF', + 1: 'FORCE_SUMM_MINZ', + 2: 'FORCE_SUMM_MAXZ', + 3: 'FORCE_SUMM_BOTH', +} +FORCE_SUMM_OFF = 0 +FORCE_SUMM_MINZ = 1 +FORCE_SUMM_MAXZ = 2 +FORCE_SUMM_BOTH = 3 +ZLimitSumm = ctypes.c_uint32 # enum + +# values for enumeration 'ZModeForce' +ZModeForce__enumvalues = { + 0: 'NO_FORCE', + 1: 'FORCE_EARLY_Z', + 2: 'FORCE_LATE_Z', + 3: 'FORCE_RE_Z', +} +NO_FORCE = 0 +FORCE_EARLY_Z = 1 +FORCE_LATE_Z = 2 +FORCE_RE_Z = 3 +ZModeForce = ctypes.c_uint32 # enum + +# values for enumeration 'ZOrder' +ZOrder__enumvalues = { + 0: 'LATE_Z', + 1: 'EARLY_Z_THEN_LATE_Z', + 2: 'RE_Z', + 3: 'EARLY_Z_THEN_RE_Z', +} +LATE_Z = 0 +EARLY_Z_THEN_LATE_Z = 1 +RE_Z = 2 +EARLY_Z_THEN_RE_Z = 3 +ZOrder = ctypes.c_uint32 # enum + +# values for enumeration 'ZSamplePosition' +ZSamplePosition__enumvalues = { + 0: 'Z_SAMPLE_CENTER', + 1: 'Z_SAMPLE_CENTROID', +} +Z_SAMPLE_CENTER = 0 +Z_SAMPLE_CENTROID = 1 +ZSamplePosition = ctypes.c_uint32 # enum + +# values for enumeration 'ZpassControl' +ZpassControl__enumvalues = { + 0: 'ZPASS_DISABLE', + 1: 'ZPASS_SAMPLES', + 2: 'ZPASS_PIXELS', +} +ZPASS_DISABLE = 0 +ZPASS_SAMPLES = 1 +ZPASS_PIXELS = 2 +ZpassControl = ctypes.c_uint32 # enum + +# values for enumeration 'SU_PERFCNT_SEL' +SU_PERFCNT_SEL__enumvalues = { + 0: 'PERF_PAPC_PASX_REQ', + 1: 'PERF_PAPC_PASX_DISABLE_PIPE', + 2: 'PERF_PAPC_PASX_FIRST_VECTOR', + 3: 'PERF_PAPC_PASX_SECOND_VECTOR', + 4: 'PERF_PAPC_PASX_FIRST_DEAD', + 5: 'PERF_PAPC_PASX_SECOND_DEAD', + 6: 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 7: 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 8: 'PERF_PAPC_PA_INPUT_PRIM', + 9: 'PERF_PAPC_PA_INPUT_NULL_PRIM', + 10: 'PERF_PAPC_PA_INPUT_EVENT_FLAG', + 11: 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', + 12: 'PERF_PAPC_PA_INPUT_END_OF_PACKET', + 13: 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', + 14: 'PERF_PAPC_CLPR_CULL_PRIM', + 15: 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', + 16: 'PERF_PAPC_CLPR_VV_CULL_PRIM', + 17: 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 18: 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 19: 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 20: 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 21: 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 22: 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 23: 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', + 24: 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 25: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 26: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 27: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 28: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 29: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 30: 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', + 31: 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 32: 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', + 33: 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 34: 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 35: 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', + 36: 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 37: 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', + 38: 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 39: 'PERF_PAPC_CLSM_NULL_PRIM', + 40: 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 41: 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', + 42: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', + 43: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 44: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', + 45: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 46: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 47: 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', + 48: 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', + 49: 'PERF_PAPC_SU_INPUT_PRIM', + 50: 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 51: 'PERF_PAPC_SU_INPUT_NULL_PRIM', + 52: 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 53: 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 54: 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 55: 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 56: 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 57: 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 58: 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 59: 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 60: 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 61: 'PERF_PAPC_SU_OUTPUT_PRIM', + 62: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 63: 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 64: 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 65: 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 66: 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', + 67: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 68: 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 69: 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', + 70: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 71: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 72: 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 73: 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 74: 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 75: 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 76: 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 77: 'PERF_PAPC_PASX_REQ_IDLE', + 78: 'PERF_PAPC_PASX_REQ_BUSY', + 79: 'PERF_PAPC_PASX_REQ_STALLED', + 80: 'PERF_PAPC_PASX_REC_IDLE', + 81: 'PERF_PAPC_PASX_REC_BUSY', + 82: 'PERF_PAPC_PASX_REC_STARVED_SX', + 83: 'PERF_PAPC_PASX_REC_STALLED', + 84: 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 85: 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 86: 'PERF_PAPC_CCGSM_IDLE', + 87: 'PERF_PAPC_CCGSM_BUSY', + 88: 'PERF_PAPC_CCGSM_STALLED', + 89: 'PERF_PAPC_CLPRIM_IDLE', + 90: 'PERF_PAPC_CLPRIM_BUSY', + 91: 'PERF_PAPC_CLPRIM_STALLED', + 92: 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 93: 'PERF_PAPC_CLIPSM_IDLE', + 94: 'PERF_PAPC_CLIPSM_BUSY', + 95: 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 96: 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', + 97: 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 98: 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 99: 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 100: 'PERF_PAPC_CLIPGA_IDLE', + 101: 'PERF_PAPC_CLIPGA_BUSY', + 102: 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 103: 'PERF_PAPC_CLIPGA_STALLED', + 104: 'PERF_PAPC_CLIP_IDLE', + 105: 'PERF_PAPC_CLIP_BUSY', + 106: 'PERF_PAPC_SU_IDLE', + 107: 'PERF_PAPC_SU_BUSY', + 108: 'PERF_PAPC_SU_STARVED_CLIP', + 109: 'PERF_PAPC_SU_STALLED_SC', + 110: 'PERF_PAPC_CL_DYN_SCLK_VLD', + 111: 'PERF_PAPC_SU_DYN_SCLK_VLD', + 112: 'PERF_PAPC_PA_REG_SCLK_VLD', + 113: 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', + 114: 'PERF_PAPC_PASX_SE0_REQ', + 115: 'PERF_PAPC_PASX_SE1_REQ', + 116: 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', + 117: 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', + 118: 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', + 119: 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', + 120: 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 121: 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 122: 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', + 123: 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 124: 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 125: 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', + 126: 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 127: 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 128: 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', + 129: 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', + 130: 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', + 131: 'PERF_PAPC_SU_SE0_STALLED_SC', + 132: 'PERF_PAPC_SU_SE1_STALLED_SC', + 133: 'PERF_PAPC_SU_SE01_STALLED_SC', + 134: 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 135: 'PERF_PAPC_SU_CULLED_PRIM', + 136: 'PERF_PAPC_SU_OUTPUT_EOPG', + 137: 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 138: 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 139: 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 140: 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 141: 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 142: 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 143: 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', + 144: 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', + 145: 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', + 146: 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', + 147: 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', + 148: 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', + 149: 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', + 150: 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', + 151: 'PERF_PAPC_SU_SE2_STALLED_SC', + 152: 'PERF_PAPC_SU_SE3_STALLED_SC', + 153: 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', + 154: 'PERF_SMALL_PRIM_CULL_PRIM_1X1', + 155: 'PERF_SMALL_PRIM_CULL_PRIM_2X1', + 156: 'PERF_SMALL_PRIM_CULL_PRIM_1X2', + 157: 'PERF_SMALL_PRIM_CULL_PRIM_2X2', + 158: 'PERF_SMALL_PRIM_CULL_PRIM_3X1', + 159: 'PERF_SMALL_PRIM_CULL_PRIM_1X3', + 160: 'PERF_SMALL_PRIM_CULL_PRIM_3X2', + 161: 'PERF_SMALL_PRIM_CULL_PRIM_2X3', + 162: 'PERF_SMALL_PRIM_CULL_PRIM_NX1', + 163: 'PERF_SMALL_PRIM_CULL_PRIM_1XN', + 164: 'PERF_SMALL_PRIM_CULL_PRIM_NX2', + 165: 'PERF_SMALL_PRIM_CULL_PRIM_2XN', + 166: 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', + 167: 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', + 168: 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', + 170: 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', + 171: 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', + 172: 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', + 173: 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', + 174: 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', + 175: 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', + 176: 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', + 177: 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', + 179: 'PERF_PA_VERTEX_FIFO_FULL', + 180: 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', + 182: 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', + 183: 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', + 185: 'PERF_PA_PIPE0_SWITCHED_GEN', + 186: 'PERF_PA_PIPE1_SWITCHED_GEN', + 188: 'PERF_ENGG_CSB_MACHINE_IS_STARVED', + 189: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', + 190: 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', + 191: 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', + 192: 'PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL', + 193: 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', + 194: 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', + 195: 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', + 196: 'PERF_ENGG_CSB_NULL_SUBGROUP', + 197: 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', + 198: 'PERF_ENGG_CSB_GE_MEMORY_FULL', + 199: 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', + 200: 'PERF_ENGG_CSB_SPI_MEMORY_FULL', + 201: 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', + 202: 'PERF_ENGG_CSB_DELAY_BIN00', + 203: 'PERF_ENGG_CSB_DELAY_BIN01', + 204: 'PERF_ENGG_CSB_DELAY_BIN02', + 205: 'PERF_ENGG_CSB_DELAY_BIN03', + 206: 'PERF_ENGG_CSB_DELAY_BIN04', + 207: 'PERF_ENGG_CSB_DELAY_BIN05', + 208: 'PERF_ENGG_CSB_DELAY_BIN06', + 209: 'PERF_ENGG_CSB_DELAY_BIN07', + 210: 'PERF_ENGG_CSB_DELAY_BIN08', + 211: 'PERF_ENGG_CSB_DELAY_BIN09', + 212: 'PERF_ENGG_CSB_DELAY_BIN10', + 213: 'PERF_ENGG_CSB_DELAY_BIN11', + 214: 'PERF_ENGG_CSB_DELAY_BIN12', + 215: 'PERF_ENGG_CSB_DELAY_BIN13', + 216: 'PERF_ENGG_CSB_DELAY_BIN14', + 217: 'PERF_ENGG_CSB_DELAY_BIN15', + 218: 'PERF_ENGG_CSB_SPI_DELAY_BIN00', + 219: 'PERF_ENGG_CSB_SPI_DELAY_BIN01', + 220: 'PERF_ENGG_CSB_SPI_DELAY_BIN02', + 221: 'PERF_ENGG_CSB_SPI_DELAY_BIN03', + 222: 'PERF_ENGG_CSB_SPI_DELAY_BIN04', + 223: 'PERF_ENGG_CSB_SPI_DELAY_BIN05', + 224: 'PERF_ENGG_CSB_SPI_DELAY_BIN06', + 225: 'PERF_ENGG_CSB_SPI_DELAY_BIN07', + 226: 'PERF_ENGG_CSB_SPI_DELAY_BIN08', + 227: 'PERF_ENGG_CSB_SPI_DELAY_BIN09', + 228: 'PERF_ENGG_CSB_SPI_DELAY_BIN10', + 229: 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', + 230: 'PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM', + 231: 'PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM', + 232: 'PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM', + 233: 'PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM', + 234: 'PERF_ENGG_INDEX_REQ_STARVED', + 235: 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 236: 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 237: 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', + 238: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', + 239: 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', + 240: 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', + 241: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', + 242: 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', + 243: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', + 244: 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', + 245: 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', + 246: 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', + 247: 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', + 248: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', + 249: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', + 250: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', + 251: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', + 252: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', + 253: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', + 254: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', + 255: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', + 256: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', + 257: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', + 258: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS', + 259: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS', + 260: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS', + 261: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS', + 262: 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS', + 263: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', + 264: 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', + 265: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', + 266: 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', + 267: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', + 268: 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', + 269: 'PERF_ENGG_POS_REQ_STARVED', + 270: 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', + 271: 'PERF_ENGG_BUSY', + 272: 'PERF_CLIPSM_CULL_PRIMS_CNT', + 273: 'PERF_PH_SEND_1_SC', + 274: 'PERF_PH_SEND_2_SC', + 275: 'PERF_PH_SEND_3_SC', + 276: 'PERF_PH_SEND_4_SC', + 277: 'PERF_OUTPUT_PRIM_1_SC', + 278: 'PERF_OUTPUT_PRIM_2_SC', + 279: 'PERF_OUTPUT_PRIM_3_SC', + 280: 'PERF_OUTPUT_PRIM_4_SC', +} +PERF_PAPC_PASX_REQ = 0 +PERF_PAPC_PASX_DISABLE_PIPE = 1 +PERF_PAPC_PASX_FIRST_VECTOR = 2 +PERF_PAPC_PASX_SECOND_VECTOR = 3 +PERF_PAPC_PASX_FIRST_DEAD = 4 +PERF_PAPC_PASX_SECOND_DEAD = 5 +PERF_PAPC_PASX_VTX_KILL_DISCARD = 6 +PERF_PAPC_PASX_VTX_NAN_DISCARD = 7 +PERF_PAPC_PA_INPUT_PRIM = 8 +PERF_PAPC_PA_INPUT_NULL_PRIM = 9 +PERF_PAPC_PA_INPUT_EVENT_FLAG = 10 +PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11 +PERF_PAPC_PA_INPUT_END_OF_PACKET = 12 +PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 13 +PERF_PAPC_CLPR_CULL_PRIM = 14 +PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 15 +PERF_PAPC_CLPR_VV_CULL_PRIM = 16 +PERF_PAPC_CLPR_UCP_CULL_PRIM = 17 +PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 18 +PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 19 +PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 20 +PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 21 +PERF_PAPC_CLPR_VV_CLIP_PRIM = 22 +PERF_PAPC_CLPR_UCP_CLIP_PRIM = 23 +PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 24 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 25 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 26 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 27 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 28 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 29 +PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 30 +PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 31 +PERF_PAPC_CLPR_CLIP_PLANE_FAR = 32 +PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 33 +PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 34 +PERF_PAPC_CLPR_CLIP_PLANE_TOP = 35 +PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 36 +PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 37 +PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 38 +PERF_PAPC_CLSM_NULL_PRIM = 39 +PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 40 +PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 41 +PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 42 +PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 43 +PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 44 +PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 45 +PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 46 +PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 47 +PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 48 +PERF_PAPC_SU_INPUT_PRIM = 49 +PERF_PAPC_SU_INPUT_CLIP_PRIM = 50 +PERF_PAPC_SU_INPUT_NULL_PRIM = 51 +PERF_PAPC_SU_INPUT_PRIM_DUAL = 52 +PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 53 +PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 54 +PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 55 +PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 56 +PERF_PAPC_SU_POLYMODE_FACE_CULL = 57 +PERF_PAPC_SU_POLYMODE_BACK_CULL = 58 +PERF_PAPC_SU_POLYMODE_FRONT_CULL = 59 +PERF_PAPC_SU_POLYMODE_INVALID_FILL = 60 +PERF_PAPC_SU_OUTPUT_PRIM = 61 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 62 +PERF_PAPC_SU_OUTPUT_NULL_PRIM = 63 +PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 64 +PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 65 +PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 66 +PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 67 +PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 68 +PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 69 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 70 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 71 +PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 72 +PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 73 +PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 74 +PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 75 +PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 76 +PERF_PAPC_PASX_REQ_IDLE = 77 +PERF_PAPC_PASX_REQ_BUSY = 78 +PERF_PAPC_PASX_REQ_STALLED = 79 +PERF_PAPC_PASX_REC_IDLE = 80 +PERF_PAPC_PASX_REC_BUSY = 81 +PERF_PAPC_PASX_REC_STARVED_SX = 82 +PERF_PAPC_PASX_REC_STALLED = 83 +PERF_PAPC_PASX_REC_STALLED_POS_MEM = 84 +PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 85 +PERF_PAPC_CCGSM_IDLE = 86 +PERF_PAPC_CCGSM_BUSY = 87 +PERF_PAPC_CCGSM_STALLED = 88 +PERF_PAPC_CLPRIM_IDLE = 89 +PERF_PAPC_CLPRIM_BUSY = 90 +PERF_PAPC_CLPRIM_STALLED = 91 +PERF_PAPC_CLPRIM_STARVED_CCGSM = 92 +PERF_PAPC_CLIPSM_IDLE = 93 +PERF_PAPC_CLIPSM_BUSY = 94 +PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 95 +PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 96 +PERF_PAPC_CLIPSM_WAIT_CLIPGA = 97 +PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 98 +PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 99 +PERF_PAPC_CLIPGA_IDLE = 100 +PERF_PAPC_CLIPGA_BUSY = 101 +PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 102 +PERF_PAPC_CLIPGA_STALLED = 103 +PERF_PAPC_CLIP_IDLE = 104 +PERF_PAPC_CLIP_BUSY = 105 +PERF_PAPC_SU_IDLE = 106 +PERF_PAPC_SU_BUSY = 107 +PERF_PAPC_SU_STARVED_CLIP = 108 +PERF_PAPC_SU_STALLED_SC = 109 +PERF_PAPC_CL_DYN_SCLK_VLD = 110 +PERF_PAPC_SU_DYN_SCLK_VLD = 111 +PERF_PAPC_PA_REG_SCLK_VLD = 112 +PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 113 +PERF_PAPC_PASX_SE0_REQ = 114 +PERF_PAPC_PASX_SE1_REQ = 115 +PERF_PAPC_PASX_SE0_FIRST_VECTOR = 116 +PERF_PAPC_PASX_SE0_SECOND_VECTOR = 117 +PERF_PAPC_PASX_SE1_FIRST_VECTOR = 118 +PERF_PAPC_PASX_SE1_SECOND_VECTOR = 119 +PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 120 +PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 121 +PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 122 +PERF_PAPC_SU_SE0_OUTPUT_PRIM = 123 +PERF_PAPC_SU_SE1_OUTPUT_PRIM = 124 +PERF_PAPC_SU_SE01_OUTPUT_PRIM = 125 +PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 126 +PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 127 +PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 128 +PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 129 +PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 130 +PERF_PAPC_SU_SE0_STALLED_SC = 131 +PERF_PAPC_SU_SE1_STALLED_SC = 132 +PERF_PAPC_SU_SE01_STALLED_SC = 133 +PERF_PAPC_CLSM_CLIPPING_PRIM = 134 +PERF_PAPC_SU_CULLED_PRIM = 135 +PERF_PAPC_SU_OUTPUT_EOPG = 136 +PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 137 +PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 138 +PERF_PAPC_SU_SE2_OUTPUT_PRIM = 139 +PERF_PAPC_SU_SE3_OUTPUT_PRIM = 140 +PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 141 +PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 142 +PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 143 +PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 144 +PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 145 +PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 146 +PERF_PAPC_SU_SE0_OUTPUT_EOPG = 147 +PERF_PAPC_SU_SE1_OUTPUT_EOPG = 148 +PERF_PAPC_SU_SE2_OUTPUT_EOPG = 149 +PERF_PAPC_SU_SE3_OUTPUT_EOPG = 150 +PERF_PAPC_SU_SE2_STALLED_SC = 151 +PERF_PAPC_SU_SE3_STALLED_SC = 152 +PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 153 +PERF_SMALL_PRIM_CULL_PRIM_1X1 = 154 +PERF_SMALL_PRIM_CULL_PRIM_2X1 = 155 +PERF_SMALL_PRIM_CULL_PRIM_1X2 = 156 +PERF_SMALL_PRIM_CULL_PRIM_2X2 = 157 +PERF_SMALL_PRIM_CULL_PRIM_3X1 = 158 +PERF_SMALL_PRIM_CULL_PRIM_1X3 = 159 +PERF_SMALL_PRIM_CULL_PRIM_3X2 = 160 +PERF_SMALL_PRIM_CULL_PRIM_2X3 = 161 +PERF_SMALL_PRIM_CULL_PRIM_NX1 = 162 +PERF_SMALL_PRIM_CULL_PRIM_1XN = 163 +PERF_SMALL_PRIM_CULL_PRIM_NX2 = 164 +PERF_SMALL_PRIM_CULL_PRIM_2XN = 165 +PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 166 +PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 167 +PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 168 +PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 170 +PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 171 +PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 172 +PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 173 +PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 174 +PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 175 +PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 176 +PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 177 +PERF_PA_VERTEX_FIFO_FULL = 179 +PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 180 +PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 182 +PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 183 +PERF_PA_PIPE0_SWITCHED_GEN = 185 +PERF_PA_PIPE1_SWITCHED_GEN = 186 +PERF_ENGG_CSB_MACHINE_IS_STARVED = 188 +PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 189 +PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 190 +PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 191 +PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL = 192 +PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 193 +PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 194 +PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 195 +PERF_ENGG_CSB_NULL_SUBGROUP = 196 +PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 197 +PERF_ENGG_CSB_GE_MEMORY_FULL = 198 +PERF_ENGG_CSB_GE_MEMORY_EMPTY = 199 +PERF_ENGG_CSB_SPI_MEMORY_FULL = 200 +PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 201 +PERF_ENGG_CSB_DELAY_BIN00 = 202 +PERF_ENGG_CSB_DELAY_BIN01 = 203 +PERF_ENGG_CSB_DELAY_BIN02 = 204 +PERF_ENGG_CSB_DELAY_BIN03 = 205 +PERF_ENGG_CSB_DELAY_BIN04 = 206 +PERF_ENGG_CSB_DELAY_BIN05 = 207 +PERF_ENGG_CSB_DELAY_BIN06 = 208 +PERF_ENGG_CSB_DELAY_BIN07 = 209 +PERF_ENGG_CSB_DELAY_BIN08 = 210 +PERF_ENGG_CSB_DELAY_BIN09 = 211 +PERF_ENGG_CSB_DELAY_BIN10 = 212 +PERF_ENGG_CSB_DELAY_BIN11 = 213 +PERF_ENGG_CSB_DELAY_BIN12 = 214 +PERF_ENGG_CSB_DELAY_BIN13 = 215 +PERF_ENGG_CSB_DELAY_BIN14 = 216 +PERF_ENGG_CSB_DELAY_BIN15 = 217 +PERF_ENGG_CSB_SPI_DELAY_BIN00 = 218 +PERF_ENGG_CSB_SPI_DELAY_BIN01 = 219 +PERF_ENGG_CSB_SPI_DELAY_BIN02 = 220 +PERF_ENGG_CSB_SPI_DELAY_BIN03 = 221 +PERF_ENGG_CSB_SPI_DELAY_BIN04 = 222 +PERF_ENGG_CSB_SPI_DELAY_BIN05 = 223 +PERF_ENGG_CSB_SPI_DELAY_BIN06 = 224 +PERF_ENGG_CSB_SPI_DELAY_BIN07 = 225 +PERF_ENGG_CSB_SPI_DELAY_BIN08 = 226 +PERF_ENGG_CSB_SPI_DELAY_BIN09 = 227 +PERF_ENGG_CSB_SPI_DELAY_BIN10 = 228 +PERF_ENGG_INDEX_REQ_NULL_REQUEST = 229 +PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM = 230 +PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM = 231 +PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM = 232 +PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM = 233 +PERF_ENGG_INDEX_REQ_STARVED = 234 +PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 235 +PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 236 +PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 237 +PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 238 +PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 239 +PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 240 +PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 241 +PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 242 +PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 243 +PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 244 +PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 245 +PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 246 +PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 247 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 248 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 249 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 250 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 251 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 252 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 253 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 254 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 255 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 256 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 257 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS = 258 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS = 259 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS = 260 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS = 261 +PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS = 262 +PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 263 +PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 264 +PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 265 +PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 266 +PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 267 +PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 268 +PERF_ENGG_POS_REQ_STARVED = 269 +PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 270 +PERF_ENGG_BUSY = 271 +PERF_CLIPSM_CULL_PRIMS_CNT = 272 +PERF_PH_SEND_1_SC = 273 +PERF_PH_SEND_2_SC = 274 +PERF_PH_SEND_3_SC = 275 +PERF_PH_SEND_4_SC = 276 +PERF_OUTPUT_PRIM_1_SC = 277 +PERF_OUTPUT_PRIM_2_SC = 278 +PERF_OUTPUT_PRIM_3_SC = 279 +PERF_OUTPUT_PRIM_4_SC = 280 +SU_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PH_PERFCNT_SEL' +PH_PERFCNT_SEL__enumvalues = { + 0: 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', + 1: 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 2: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', + 3: 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 4: 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', + 5: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', + 6: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 7: 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 8: 'PH_PERF_SEL_SC0_ARB_BUSY', + 9: 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', + 10: 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', + 11: 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', + 12: 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', + 13: 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', + 14: 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', + 15: 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', + 16: 'PH_PERF_SEL_SC0_SEND', + 17: 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 18: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', + 19: 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', + 20: 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', + 21: 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', + 22: 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', + 23: 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 24: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', + 25: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', + 26: 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', + 27: 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', + 28: 'PH_PERF_SEL_SC0_PA0_NULL_WE', + 29: 'PH_PERF_SEL_SC0_PA0_EVENT_WE', + 30: 'PH_PERF_SEL_SC0_PA0_FPOV_WE', + 31: 'PH_PERF_SEL_SC0_PA0_LPOV_WE', + 32: 'PH_PERF_SEL_SC0_PA0_EOP_WE', + 33: 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', + 34: 'PH_PERF_SEL_SC0_PA0_EOPG_WE', + 35: 'PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD', + 36: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', + 37: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', + 38: 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', + 39: 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', + 40: 'PH_PERF_SEL_SC0_PA1_NULL_WE', + 41: 'PH_PERF_SEL_SC0_PA1_EVENT_WE', + 42: 'PH_PERF_SEL_SC0_PA1_FPOV_WE', + 43: 'PH_PERF_SEL_SC0_PA1_LPOV_WE', + 44: 'PH_PERF_SEL_SC0_PA1_EOP_WE', + 45: 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', + 46: 'PH_PERF_SEL_SC0_PA1_EOPG_WE', + 47: 'PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD', + 48: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', + 49: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', + 50: 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', + 51: 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', + 52: 'PH_PERF_SEL_SC0_PA2_NULL_WE', + 53: 'PH_PERF_SEL_SC0_PA2_EVENT_WE', + 54: 'PH_PERF_SEL_SC0_PA2_FPOV_WE', + 55: 'PH_PERF_SEL_SC0_PA2_LPOV_WE', + 56: 'PH_PERF_SEL_SC0_PA2_EOP_WE', + 57: 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', + 58: 'PH_PERF_SEL_SC0_PA2_EOPG_WE', + 59: 'PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD', + 60: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', + 61: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', + 62: 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', + 63: 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', + 64: 'PH_PERF_SEL_SC0_PA3_NULL_WE', + 65: 'PH_PERF_SEL_SC0_PA3_EVENT_WE', + 66: 'PH_PERF_SEL_SC0_PA3_FPOV_WE', + 67: 'PH_PERF_SEL_SC0_PA3_LPOV_WE', + 68: 'PH_PERF_SEL_SC0_PA3_EOP_WE', + 69: 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', + 70: 'PH_PERF_SEL_SC0_PA3_EOPG_WE', + 71: 'PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD', + 72: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', + 73: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', + 74: 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', + 75: 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', + 76: 'PH_PERF_SEL_SC0_PA4_NULL_WE', + 77: 'PH_PERF_SEL_SC0_PA4_EVENT_WE', + 78: 'PH_PERF_SEL_SC0_PA4_FPOV_WE', + 79: 'PH_PERF_SEL_SC0_PA4_LPOV_WE', + 80: 'PH_PERF_SEL_SC0_PA4_EOP_WE', + 81: 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', + 82: 'PH_PERF_SEL_SC0_PA4_EOPG_WE', + 83: 'PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD', + 84: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', + 85: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', + 86: 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', + 87: 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', + 88: 'PH_PERF_SEL_SC0_PA5_NULL_WE', + 89: 'PH_PERF_SEL_SC0_PA5_EVENT_WE', + 90: 'PH_PERF_SEL_SC0_PA5_FPOV_WE', + 91: 'PH_PERF_SEL_SC0_PA5_LPOV_WE', + 92: 'PH_PERF_SEL_SC0_PA5_EOP_WE', + 93: 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', + 94: 'PH_PERF_SEL_SC0_PA5_EOPG_WE', + 95: 'PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD', + 96: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', + 97: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', + 98: 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', + 99: 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', + 100: 'PH_PERF_SEL_SC0_PA6_NULL_WE', + 101: 'PH_PERF_SEL_SC0_PA6_EVENT_WE', + 102: 'PH_PERF_SEL_SC0_PA6_FPOV_WE', + 103: 'PH_PERF_SEL_SC0_PA6_LPOV_WE', + 104: 'PH_PERF_SEL_SC0_PA6_EOP_WE', + 105: 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', + 106: 'PH_PERF_SEL_SC0_PA6_EOPG_WE', + 107: 'PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD', + 108: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', + 109: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', + 110: 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', + 111: 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', + 112: 'PH_PERF_SEL_SC0_PA7_NULL_WE', + 113: 'PH_PERF_SEL_SC0_PA7_EVENT_WE', + 114: 'PH_PERF_SEL_SC0_PA7_FPOV_WE', + 115: 'PH_PERF_SEL_SC0_PA7_LPOV_WE', + 116: 'PH_PERF_SEL_SC0_PA7_EOP_WE', + 117: 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', + 118: 'PH_PERF_SEL_SC0_PA7_EOPG_WE', + 119: 'PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD', + 120: 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', + 121: 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 122: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', + 123: 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 124: 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', + 125: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', + 126: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 127: 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 128: 'PH_PERF_SEL_SC1_ARB_BUSY', + 129: 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', + 130: 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', + 131: 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', + 132: 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', + 133: 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', + 134: 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', + 135: 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', + 136: 'PH_PERF_SEL_SC1_SEND', + 137: 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 138: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', + 139: 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', + 140: 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', + 141: 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', + 142: 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 143: 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 144: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', + 145: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', + 146: 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', + 147: 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', + 148: 'PH_PERF_SEL_SC1_PA0_NULL_WE', + 149: 'PH_PERF_SEL_SC1_PA0_EVENT_WE', + 150: 'PH_PERF_SEL_SC1_PA0_FPOV_WE', + 151: 'PH_PERF_SEL_SC1_PA0_LPOV_WE', + 152: 'PH_PERF_SEL_SC1_PA0_EOP_WE', + 153: 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', + 154: 'PH_PERF_SEL_SC1_PA0_EOPG_WE', + 155: 'PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD', + 156: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', + 157: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', + 158: 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', + 159: 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', + 160: 'PH_PERF_SEL_SC1_PA1_NULL_WE', + 161: 'PH_PERF_SEL_SC1_PA1_EVENT_WE', + 162: 'PH_PERF_SEL_SC1_PA1_FPOV_WE', + 163: 'PH_PERF_SEL_SC1_PA1_LPOV_WE', + 164: 'PH_PERF_SEL_SC1_PA1_EOP_WE', + 165: 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', + 166: 'PH_PERF_SEL_SC1_PA1_EOPG_WE', + 167: 'PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD', + 168: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', + 169: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', + 170: 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', + 171: 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', + 172: 'PH_PERF_SEL_SC1_PA2_NULL_WE', + 173: 'PH_PERF_SEL_SC1_PA2_EVENT_WE', + 174: 'PH_PERF_SEL_SC1_PA2_FPOV_WE', + 175: 'PH_PERF_SEL_SC1_PA2_LPOV_WE', + 176: 'PH_PERF_SEL_SC1_PA2_EOP_WE', + 177: 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', + 178: 'PH_PERF_SEL_SC1_PA2_EOPG_WE', + 179: 'PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD', + 180: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', + 181: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', + 182: 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', + 183: 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', + 184: 'PH_PERF_SEL_SC1_PA3_NULL_WE', + 185: 'PH_PERF_SEL_SC1_PA3_EVENT_WE', + 186: 'PH_PERF_SEL_SC1_PA3_FPOV_WE', + 187: 'PH_PERF_SEL_SC1_PA3_LPOV_WE', + 188: 'PH_PERF_SEL_SC1_PA3_EOP_WE', + 189: 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', + 190: 'PH_PERF_SEL_SC1_PA3_EOPG_WE', + 191: 'PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD', + 192: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', + 193: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', + 194: 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', + 195: 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', + 196: 'PH_PERF_SEL_SC1_PA4_NULL_WE', + 197: 'PH_PERF_SEL_SC1_PA4_EVENT_WE', + 198: 'PH_PERF_SEL_SC1_PA4_FPOV_WE', + 199: 'PH_PERF_SEL_SC1_PA4_LPOV_WE', + 200: 'PH_PERF_SEL_SC1_PA4_EOP_WE', + 201: 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', + 202: 'PH_PERF_SEL_SC1_PA4_EOPG_WE', + 203: 'PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD', + 204: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', + 205: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', + 206: 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', + 207: 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', + 208: 'PH_PERF_SEL_SC1_PA5_NULL_WE', + 209: 'PH_PERF_SEL_SC1_PA5_EVENT_WE', + 210: 'PH_PERF_SEL_SC1_PA5_FPOV_WE', + 211: 'PH_PERF_SEL_SC1_PA5_LPOV_WE', + 212: 'PH_PERF_SEL_SC1_PA5_EOP_WE', + 213: 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', + 214: 'PH_PERF_SEL_SC1_PA5_EOPG_WE', + 215: 'PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD', + 216: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', + 217: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', + 218: 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', + 219: 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', + 220: 'PH_PERF_SEL_SC1_PA6_NULL_WE', + 221: 'PH_PERF_SEL_SC1_PA6_EVENT_WE', + 222: 'PH_PERF_SEL_SC1_PA6_FPOV_WE', + 223: 'PH_PERF_SEL_SC1_PA6_LPOV_WE', + 224: 'PH_PERF_SEL_SC1_PA6_EOP_WE', + 225: 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', + 226: 'PH_PERF_SEL_SC1_PA6_EOPG_WE', + 227: 'PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD', + 228: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', + 229: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', + 230: 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', + 231: 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', + 232: 'PH_PERF_SEL_SC1_PA7_NULL_WE', + 233: 'PH_PERF_SEL_SC1_PA7_EVENT_WE', + 234: 'PH_PERF_SEL_SC1_PA7_FPOV_WE', + 235: 'PH_PERF_SEL_SC1_PA7_LPOV_WE', + 236: 'PH_PERF_SEL_SC1_PA7_EOP_WE', + 237: 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', + 238: 'PH_PERF_SEL_SC1_PA7_EOPG_WE', + 239: 'PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD', + 240: 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', + 241: 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 242: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', + 243: 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 244: 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', + 245: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', + 246: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 247: 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 248: 'PH_PERF_SEL_SC2_ARB_BUSY', + 249: 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', + 250: 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', + 251: 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', + 252: 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', + 253: 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', + 254: 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', + 255: 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', + 256: 'PH_PERF_SEL_SC2_SEND', + 257: 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 258: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', + 259: 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', + 260: 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', + 261: 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', + 262: 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 263: 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 264: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', + 265: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', + 266: 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', + 267: 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', + 268: 'PH_PERF_SEL_SC2_PA0_NULL_WE', + 269: 'PH_PERF_SEL_SC2_PA0_EVENT_WE', + 270: 'PH_PERF_SEL_SC2_PA0_FPOV_WE', + 271: 'PH_PERF_SEL_SC2_PA0_LPOV_WE', + 272: 'PH_PERF_SEL_SC2_PA0_EOP_WE', + 273: 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', + 274: 'PH_PERF_SEL_SC2_PA0_EOPG_WE', + 275: 'PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD', + 276: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', + 277: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', + 278: 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', + 279: 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', + 280: 'PH_PERF_SEL_SC2_PA1_NULL_WE', + 281: 'PH_PERF_SEL_SC2_PA1_EVENT_WE', + 282: 'PH_PERF_SEL_SC2_PA1_FPOV_WE', + 283: 'PH_PERF_SEL_SC2_PA1_LPOV_WE', + 284: 'PH_PERF_SEL_SC2_PA1_EOP_WE', + 285: 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', + 286: 'PH_PERF_SEL_SC2_PA1_EOPG_WE', + 287: 'PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD', + 288: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', + 289: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', + 290: 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', + 291: 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', + 292: 'PH_PERF_SEL_SC2_PA2_NULL_WE', + 293: 'PH_PERF_SEL_SC2_PA2_EVENT_WE', + 294: 'PH_PERF_SEL_SC2_PA2_FPOV_WE', + 295: 'PH_PERF_SEL_SC2_PA2_LPOV_WE', + 296: 'PH_PERF_SEL_SC2_PA2_EOP_WE', + 297: 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', + 298: 'PH_PERF_SEL_SC2_PA2_EOPG_WE', + 299: 'PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD', + 300: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', + 301: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', + 302: 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', + 303: 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', + 304: 'PH_PERF_SEL_SC2_PA3_NULL_WE', + 305: 'PH_PERF_SEL_SC2_PA3_EVENT_WE', + 306: 'PH_PERF_SEL_SC2_PA3_FPOV_WE', + 307: 'PH_PERF_SEL_SC2_PA3_LPOV_WE', + 308: 'PH_PERF_SEL_SC2_PA3_EOP_WE', + 309: 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', + 310: 'PH_PERF_SEL_SC2_PA3_EOPG_WE', + 311: 'PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD', + 312: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', + 313: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', + 314: 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', + 315: 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', + 316: 'PH_PERF_SEL_SC2_PA4_NULL_WE', + 317: 'PH_PERF_SEL_SC2_PA4_EVENT_WE', + 318: 'PH_PERF_SEL_SC2_PA4_FPOV_WE', + 319: 'PH_PERF_SEL_SC2_PA4_LPOV_WE', + 320: 'PH_PERF_SEL_SC2_PA4_EOP_WE', + 321: 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', + 322: 'PH_PERF_SEL_SC2_PA4_EOPG_WE', + 323: 'PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD', + 324: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', + 325: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', + 326: 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', + 327: 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', + 328: 'PH_PERF_SEL_SC2_PA5_NULL_WE', + 329: 'PH_PERF_SEL_SC2_PA5_EVENT_WE', + 330: 'PH_PERF_SEL_SC2_PA5_FPOV_WE', + 331: 'PH_PERF_SEL_SC2_PA5_LPOV_WE', + 332: 'PH_PERF_SEL_SC2_PA5_EOP_WE', + 333: 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', + 334: 'PH_PERF_SEL_SC2_PA5_EOPG_WE', + 335: 'PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD', + 336: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', + 337: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', + 338: 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', + 339: 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', + 340: 'PH_PERF_SEL_SC2_PA6_NULL_WE', + 341: 'PH_PERF_SEL_SC2_PA6_EVENT_WE', + 342: 'PH_PERF_SEL_SC2_PA6_FPOV_WE', + 343: 'PH_PERF_SEL_SC2_PA6_LPOV_WE', + 344: 'PH_PERF_SEL_SC2_PA6_EOP_WE', + 345: 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', + 346: 'PH_PERF_SEL_SC2_PA6_EOPG_WE', + 347: 'PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD', + 348: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', + 349: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', + 350: 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', + 351: 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', + 352: 'PH_PERF_SEL_SC2_PA7_NULL_WE', + 353: 'PH_PERF_SEL_SC2_PA7_EVENT_WE', + 354: 'PH_PERF_SEL_SC2_PA7_FPOV_WE', + 355: 'PH_PERF_SEL_SC2_PA7_LPOV_WE', + 356: 'PH_PERF_SEL_SC2_PA7_EOP_WE', + 357: 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', + 358: 'PH_PERF_SEL_SC2_PA7_EOPG_WE', + 359: 'PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD', + 360: 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', + 361: 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 362: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', + 363: 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 364: 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', + 365: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', + 366: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 367: 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 368: 'PH_PERF_SEL_SC3_ARB_BUSY', + 369: 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', + 370: 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', + 371: 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', + 372: 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', + 373: 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', + 374: 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', + 375: 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', + 376: 'PH_PERF_SEL_SC3_SEND', + 377: 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 378: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', + 379: 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', + 380: 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', + 381: 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', + 382: 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 383: 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 384: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', + 385: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', + 386: 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', + 387: 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', + 388: 'PH_PERF_SEL_SC3_PA0_NULL_WE', + 389: 'PH_PERF_SEL_SC3_PA0_EVENT_WE', + 390: 'PH_PERF_SEL_SC3_PA0_FPOV_WE', + 391: 'PH_PERF_SEL_SC3_PA0_LPOV_WE', + 392: 'PH_PERF_SEL_SC3_PA0_EOP_WE', + 393: 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', + 394: 'PH_PERF_SEL_SC3_PA0_EOPG_WE', + 395: 'PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD', + 396: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', + 397: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', + 398: 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', + 399: 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', + 400: 'PH_PERF_SEL_SC3_PA1_NULL_WE', + 401: 'PH_PERF_SEL_SC3_PA1_EVENT_WE', + 402: 'PH_PERF_SEL_SC3_PA1_FPOV_WE', + 403: 'PH_PERF_SEL_SC3_PA1_LPOV_WE', + 404: 'PH_PERF_SEL_SC3_PA1_EOP_WE', + 405: 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', + 406: 'PH_PERF_SEL_SC3_PA1_EOPG_WE', + 407: 'PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD', + 408: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', + 409: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', + 410: 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', + 411: 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', + 412: 'PH_PERF_SEL_SC3_PA2_NULL_WE', + 413: 'PH_PERF_SEL_SC3_PA2_EVENT_WE', + 414: 'PH_PERF_SEL_SC3_PA2_FPOV_WE', + 415: 'PH_PERF_SEL_SC3_PA2_LPOV_WE', + 416: 'PH_PERF_SEL_SC3_PA2_EOP_WE', + 417: 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', + 418: 'PH_PERF_SEL_SC3_PA2_EOPG_WE', + 419: 'PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD', + 420: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', + 421: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', + 422: 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', + 423: 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', + 424: 'PH_PERF_SEL_SC3_PA3_NULL_WE', + 425: 'PH_PERF_SEL_SC3_PA3_EVENT_WE', + 426: 'PH_PERF_SEL_SC3_PA3_FPOV_WE', + 427: 'PH_PERF_SEL_SC3_PA3_LPOV_WE', + 428: 'PH_PERF_SEL_SC3_PA3_EOP_WE', + 429: 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', + 430: 'PH_PERF_SEL_SC3_PA3_EOPG_WE', + 431: 'PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD', + 432: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', + 433: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', + 434: 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', + 435: 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', + 436: 'PH_PERF_SEL_SC3_PA4_NULL_WE', + 437: 'PH_PERF_SEL_SC3_PA4_EVENT_WE', + 438: 'PH_PERF_SEL_SC3_PA4_FPOV_WE', + 439: 'PH_PERF_SEL_SC3_PA4_LPOV_WE', + 440: 'PH_PERF_SEL_SC3_PA4_EOP_WE', + 441: 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', + 442: 'PH_PERF_SEL_SC3_PA4_EOPG_WE', + 443: 'PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD', + 444: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', + 445: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', + 446: 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', + 447: 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', + 448: 'PH_PERF_SEL_SC3_PA5_NULL_WE', + 449: 'PH_PERF_SEL_SC3_PA5_EVENT_WE', + 450: 'PH_PERF_SEL_SC3_PA5_FPOV_WE', + 451: 'PH_PERF_SEL_SC3_PA5_LPOV_WE', + 452: 'PH_PERF_SEL_SC3_PA5_EOP_WE', + 453: 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', + 454: 'PH_PERF_SEL_SC3_PA5_EOPG_WE', + 455: 'PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD', + 456: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', + 457: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', + 458: 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', + 459: 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', + 460: 'PH_PERF_SEL_SC3_PA6_NULL_WE', + 461: 'PH_PERF_SEL_SC3_PA6_EVENT_WE', + 462: 'PH_PERF_SEL_SC3_PA6_FPOV_WE', + 463: 'PH_PERF_SEL_SC3_PA6_LPOV_WE', + 464: 'PH_PERF_SEL_SC3_PA6_EOP_WE', + 465: 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', + 466: 'PH_PERF_SEL_SC3_PA6_EOPG_WE', + 467: 'PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD', + 468: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', + 469: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', + 470: 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', + 471: 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', + 472: 'PH_PERF_SEL_SC3_PA7_NULL_WE', + 473: 'PH_PERF_SEL_SC3_PA7_EVENT_WE', + 474: 'PH_PERF_SEL_SC3_PA7_FPOV_WE', + 475: 'PH_PERF_SEL_SC3_PA7_LPOV_WE', + 476: 'PH_PERF_SEL_SC3_PA7_EOP_WE', + 477: 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', + 478: 'PH_PERF_SEL_SC3_PA7_EOPG_WE', + 479: 'PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD', + 480: 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', + 481: 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 482: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', + 483: 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 484: 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', + 485: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', + 486: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 487: 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 488: 'PH_PERF_SEL_SC4_ARB_BUSY', + 489: 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', + 490: 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', + 491: 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', + 492: 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', + 493: 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', + 494: 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', + 495: 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', + 496: 'PH_PERF_SEL_SC4_SEND', + 497: 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 498: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', + 499: 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', + 500: 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', + 501: 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', + 502: 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 503: 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 504: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', + 505: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', + 506: 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', + 507: 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', + 508: 'PH_PERF_SEL_SC4_PA0_NULL_WE', + 509: 'PH_PERF_SEL_SC4_PA0_EVENT_WE', + 510: 'PH_PERF_SEL_SC4_PA0_FPOV_WE', + 511: 'PH_PERF_SEL_SC4_PA0_LPOV_WE', + 512: 'PH_PERF_SEL_SC4_PA0_EOP_WE', + 513: 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', + 514: 'PH_PERF_SEL_SC4_PA0_EOPG_WE', + 515: 'PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD', + 516: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', + 517: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', + 518: 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', + 519: 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', + 520: 'PH_PERF_SEL_SC4_PA1_NULL_WE', + 521: 'PH_PERF_SEL_SC4_PA1_EVENT_WE', + 522: 'PH_PERF_SEL_SC4_PA1_FPOV_WE', + 523: 'PH_PERF_SEL_SC4_PA1_LPOV_WE', + 524: 'PH_PERF_SEL_SC4_PA1_EOP_WE', + 525: 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', + 526: 'PH_PERF_SEL_SC4_PA1_EOPG_WE', + 527: 'PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD', + 528: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', + 529: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', + 530: 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', + 531: 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', + 532: 'PH_PERF_SEL_SC4_PA2_NULL_WE', + 533: 'PH_PERF_SEL_SC4_PA2_EVENT_WE', + 534: 'PH_PERF_SEL_SC4_PA2_FPOV_WE', + 535: 'PH_PERF_SEL_SC4_PA2_LPOV_WE', + 536: 'PH_PERF_SEL_SC4_PA2_EOP_WE', + 537: 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', + 538: 'PH_PERF_SEL_SC4_PA2_EOPG_WE', + 539: 'PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD', + 540: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', + 541: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', + 542: 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', + 543: 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', + 544: 'PH_PERF_SEL_SC4_PA3_NULL_WE', + 545: 'PH_PERF_SEL_SC4_PA3_EVENT_WE', + 546: 'PH_PERF_SEL_SC4_PA3_FPOV_WE', + 547: 'PH_PERF_SEL_SC4_PA3_LPOV_WE', + 548: 'PH_PERF_SEL_SC4_PA3_EOP_WE', + 549: 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', + 550: 'PH_PERF_SEL_SC4_PA3_EOPG_WE', + 551: 'PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD', + 552: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', + 553: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', + 554: 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', + 555: 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', + 556: 'PH_PERF_SEL_SC4_PA4_NULL_WE', + 557: 'PH_PERF_SEL_SC4_PA4_EVENT_WE', + 558: 'PH_PERF_SEL_SC4_PA4_FPOV_WE', + 559: 'PH_PERF_SEL_SC4_PA4_LPOV_WE', + 560: 'PH_PERF_SEL_SC4_PA4_EOP_WE', + 561: 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', + 562: 'PH_PERF_SEL_SC4_PA4_EOPG_WE', + 563: 'PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD', + 564: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', + 565: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', + 566: 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', + 567: 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', + 568: 'PH_PERF_SEL_SC4_PA5_NULL_WE', + 569: 'PH_PERF_SEL_SC4_PA5_EVENT_WE', + 570: 'PH_PERF_SEL_SC4_PA5_FPOV_WE', + 571: 'PH_PERF_SEL_SC4_PA5_LPOV_WE', + 572: 'PH_PERF_SEL_SC4_PA5_EOP_WE', + 573: 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', + 574: 'PH_PERF_SEL_SC4_PA5_EOPG_WE', + 575: 'PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD', + 576: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', + 577: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', + 578: 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', + 579: 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', + 580: 'PH_PERF_SEL_SC4_PA6_NULL_WE', + 581: 'PH_PERF_SEL_SC4_PA6_EVENT_WE', + 582: 'PH_PERF_SEL_SC4_PA6_FPOV_WE', + 583: 'PH_PERF_SEL_SC4_PA6_LPOV_WE', + 584: 'PH_PERF_SEL_SC4_PA6_EOP_WE', + 585: 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', + 586: 'PH_PERF_SEL_SC4_PA6_EOPG_WE', + 587: 'PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD', + 588: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', + 589: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', + 590: 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', + 591: 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', + 592: 'PH_PERF_SEL_SC4_PA7_NULL_WE', + 593: 'PH_PERF_SEL_SC4_PA7_EVENT_WE', + 594: 'PH_PERF_SEL_SC4_PA7_FPOV_WE', + 595: 'PH_PERF_SEL_SC4_PA7_LPOV_WE', + 596: 'PH_PERF_SEL_SC4_PA7_EOP_WE', + 597: 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', + 598: 'PH_PERF_SEL_SC4_PA7_EOPG_WE', + 599: 'PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD', + 600: 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', + 601: 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 602: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', + 603: 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 604: 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', + 605: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', + 606: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 607: 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 608: 'PH_PERF_SEL_SC5_ARB_BUSY', + 609: 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', + 610: 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', + 611: 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', + 612: 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', + 613: 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', + 614: 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', + 615: 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', + 616: 'PH_PERF_SEL_SC5_SEND', + 617: 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 618: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', + 619: 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', + 620: 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', + 621: 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', + 622: 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 623: 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 624: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', + 625: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', + 626: 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', + 627: 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', + 628: 'PH_PERF_SEL_SC5_PA0_NULL_WE', + 629: 'PH_PERF_SEL_SC5_PA0_EVENT_WE', + 630: 'PH_PERF_SEL_SC5_PA0_FPOV_WE', + 631: 'PH_PERF_SEL_SC5_PA0_LPOV_WE', + 632: 'PH_PERF_SEL_SC5_PA0_EOP_WE', + 633: 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', + 634: 'PH_PERF_SEL_SC5_PA0_EOPG_WE', + 635: 'PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD', + 636: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', + 637: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', + 638: 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', + 639: 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', + 640: 'PH_PERF_SEL_SC5_PA1_NULL_WE', + 641: 'PH_PERF_SEL_SC5_PA1_EVENT_WE', + 642: 'PH_PERF_SEL_SC5_PA1_FPOV_WE', + 643: 'PH_PERF_SEL_SC5_PA1_LPOV_WE', + 644: 'PH_PERF_SEL_SC5_PA1_EOP_WE', + 645: 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', + 646: 'PH_PERF_SEL_SC5_PA1_EOPG_WE', + 647: 'PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD', + 648: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', + 649: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', + 650: 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', + 651: 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', + 652: 'PH_PERF_SEL_SC5_PA2_NULL_WE', + 653: 'PH_PERF_SEL_SC5_PA2_EVENT_WE', + 654: 'PH_PERF_SEL_SC5_PA2_FPOV_WE', + 655: 'PH_PERF_SEL_SC5_PA2_LPOV_WE', + 656: 'PH_PERF_SEL_SC5_PA2_EOP_WE', + 657: 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', + 658: 'PH_PERF_SEL_SC5_PA2_EOPG_WE', + 659: 'PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD', + 660: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', + 661: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', + 662: 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', + 663: 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', + 664: 'PH_PERF_SEL_SC5_PA3_NULL_WE', + 665: 'PH_PERF_SEL_SC5_PA3_EVENT_WE', + 666: 'PH_PERF_SEL_SC5_PA3_FPOV_WE', + 667: 'PH_PERF_SEL_SC5_PA3_LPOV_WE', + 668: 'PH_PERF_SEL_SC5_PA3_EOP_WE', + 669: 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', + 670: 'PH_PERF_SEL_SC5_PA3_EOPG_WE', + 671: 'PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD', + 672: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', + 673: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', + 674: 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', + 675: 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', + 676: 'PH_PERF_SEL_SC5_PA4_NULL_WE', + 677: 'PH_PERF_SEL_SC5_PA4_EVENT_WE', + 678: 'PH_PERF_SEL_SC5_PA4_FPOV_WE', + 679: 'PH_PERF_SEL_SC5_PA4_LPOV_WE', + 680: 'PH_PERF_SEL_SC5_PA4_EOP_WE', + 681: 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', + 682: 'PH_PERF_SEL_SC5_PA4_EOPG_WE', + 683: 'PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD', + 684: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', + 685: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', + 686: 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', + 687: 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', + 688: 'PH_PERF_SEL_SC5_PA5_NULL_WE', + 689: 'PH_PERF_SEL_SC5_PA5_EVENT_WE', + 690: 'PH_PERF_SEL_SC5_PA5_FPOV_WE', + 691: 'PH_PERF_SEL_SC5_PA5_LPOV_WE', + 692: 'PH_PERF_SEL_SC5_PA5_EOP_WE', + 693: 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', + 694: 'PH_PERF_SEL_SC5_PA5_EOPG_WE', + 695: 'PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD', + 696: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', + 697: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', + 698: 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', + 699: 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', + 700: 'PH_PERF_SEL_SC5_PA6_NULL_WE', + 701: 'PH_PERF_SEL_SC5_PA6_EVENT_WE', + 702: 'PH_PERF_SEL_SC5_PA6_FPOV_WE', + 703: 'PH_PERF_SEL_SC5_PA6_LPOV_WE', + 704: 'PH_PERF_SEL_SC5_PA6_EOP_WE', + 705: 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', + 706: 'PH_PERF_SEL_SC5_PA6_EOPG_WE', + 707: 'PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD', + 708: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', + 709: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', + 710: 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', + 711: 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', + 712: 'PH_PERF_SEL_SC5_PA7_NULL_WE', + 713: 'PH_PERF_SEL_SC5_PA7_EVENT_WE', + 714: 'PH_PERF_SEL_SC5_PA7_FPOV_WE', + 715: 'PH_PERF_SEL_SC5_PA7_LPOV_WE', + 716: 'PH_PERF_SEL_SC5_PA7_EOP_WE', + 717: 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', + 718: 'PH_PERF_SEL_SC5_PA7_EOPG_WE', + 719: 'PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD', + 720: 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', + 721: 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 722: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', + 723: 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 724: 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', + 725: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', + 726: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 727: 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 728: 'PH_PERF_SEL_SC6_ARB_BUSY', + 729: 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', + 730: 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', + 731: 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', + 732: 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', + 733: 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', + 734: 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', + 735: 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', + 736: 'PH_PERF_SEL_SC6_SEND', + 737: 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 738: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', + 739: 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', + 740: 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', + 741: 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', + 742: 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 743: 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 744: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', + 745: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', + 746: 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', + 747: 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', + 748: 'PH_PERF_SEL_SC6_PA0_NULL_WE', + 749: 'PH_PERF_SEL_SC6_PA0_EVENT_WE', + 750: 'PH_PERF_SEL_SC6_PA0_FPOV_WE', + 751: 'PH_PERF_SEL_SC6_PA0_LPOV_WE', + 752: 'PH_PERF_SEL_SC6_PA0_EOP_WE', + 753: 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', + 754: 'PH_PERF_SEL_SC6_PA0_EOPG_WE', + 755: 'PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD', + 756: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', + 757: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', + 758: 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', + 759: 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', + 760: 'PH_PERF_SEL_SC6_PA1_NULL_WE', + 761: 'PH_PERF_SEL_SC6_PA1_EVENT_WE', + 762: 'PH_PERF_SEL_SC6_PA1_FPOV_WE', + 763: 'PH_PERF_SEL_SC6_PA1_LPOV_WE', + 764: 'PH_PERF_SEL_SC6_PA1_EOP_WE', + 765: 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', + 766: 'PH_PERF_SEL_SC6_PA1_EOPG_WE', + 767: 'PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD', + 768: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', + 769: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', + 770: 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', + 771: 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', + 772: 'PH_PERF_SEL_SC6_PA2_NULL_WE', + 773: 'PH_PERF_SEL_SC6_PA2_EVENT_WE', + 774: 'PH_PERF_SEL_SC6_PA2_FPOV_WE', + 775: 'PH_PERF_SEL_SC6_PA2_LPOV_WE', + 776: 'PH_PERF_SEL_SC6_PA2_EOP_WE', + 777: 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', + 778: 'PH_PERF_SEL_SC6_PA2_EOPG_WE', + 779: 'PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD', + 780: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', + 781: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', + 782: 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', + 783: 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', + 784: 'PH_PERF_SEL_SC6_PA3_NULL_WE', + 785: 'PH_PERF_SEL_SC6_PA3_EVENT_WE', + 786: 'PH_PERF_SEL_SC6_PA3_FPOV_WE', + 787: 'PH_PERF_SEL_SC6_PA3_LPOV_WE', + 788: 'PH_PERF_SEL_SC6_PA3_EOP_WE', + 789: 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', + 790: 'PH_PERF_SEL_SC6_PA3_EOPG_WE', + 791: 'PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD', + 792: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', + 793: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', + 794: 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', + 795: 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', + 796: 'PH_PERF_SEL_SC6_PA4_NULL_WE', + 797: 'PH_PERF_SEL_SC6_PA4_EVENT_WE', + 798: 'PH_PERF_SEL_SC6_PA4_FPOV_WE', + 799: 'PH_PERF_SEL_SC6_PA4_LPOV_WE', + 800: 'PH_PERF_SEL_SC6_PA4_EOP_WE', + 801: 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', + 802: 'PH_PERF_SEL_SC6_PA4_EOPG_WE', + 803: 'PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD', + 804: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', + 805: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', + 806: 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', + 807: 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', + 808: 'PH_PERF_SEL_SC6_PA5_NULL_WE', + 809: 'PH_PERF_SEL_SC6_PA5_EVENT_WE', + 810: 'PH_PERF_SEL_SC6_PA5_FPOV_WE', + 811: 'PH_PERF_SEL_SC6_PA5_LPOV_WE', + 812: 'PH_PERF_SEL_SC6_PA5_EOP_WE', + 813: 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', + 814: 'PH_PERF_SEL_SC6_PA5_EOPG_WE', + 815: 'PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD', + 816: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', + 817: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', + 818: 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', + 819: 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', + 820: 'PH_PERF_SEL_SC6_PA6_NULL_WE', + 821: 'PH_PERF_SEL_SC6_PA6_EVENT_WE', + 822: 'PH_PERF_SEL_SC6_PA6_FPOV_WE', + 823: 'PH_PERF_SEL_SC6_PA6_LPOV_WE', + 824: 'PH_PERF_SEL_SC6_PA6_EOP_WE', + 825: 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', + 826: 'PH_PERF_SEL_SC6_PA6_EOPG_WE', + 827: 'PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD', + 828: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', + 829: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', + 830: 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', + 831: 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', + 832: 'PH_PERF_SEL_SC6_PA7_NULL_WE', + 833: 'PH_PERF_SEL_SC6_PA7_EVENT_WE', + 834: 'PH_PERF_SEL_SC6_PA7_FPOV_WE', + 835: 'PH_PERF_SEL_SC6_PA7_LPOV_WE', + 836: 'PH_PERF_SEL_SC6_PA7_EOP_WE', + 837: 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', + 838: 'PH_PERF_SEL_SC6_PA7_EOPG_WE', + 839: 'PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD', + 840: 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', + 841: 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 842: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', + 843: 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 844: 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', + 845: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', + 846: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 847: 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 848: 'PH_PERF_SEL_SC7_ARB_BUSY', + 849: 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', + 850: 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', + 851: 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', + 852: 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', + 853: 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', + 854: 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', + 855: 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', + 856: 'PH_PERF_SEL_SC7_SEND', + 857: 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 858: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', + 859: 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', + 860: 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', + 861: 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', + 862: 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 863: 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 864: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', + 865: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', + 866: 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', + 867: 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', + 868: 'PH_PERF_SEL_SC7_PA0_NULL_WE', + 869: 'PH_PERF_SEL_SC7_PA0_EVENT_WE', + 870: 'PH_PERF_SEL_SC7_PA0_FPOV_WE', + 871: 'PH_PERF_SEL_SC7_PA0_LPOV_WE', + 872: 'PH_PERF_SEL_SC7_PA0_EOP_WE', + 873: 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', + 874: 'PH_PERF_SEL_SC7_PA0_EOPG_WE', + 875: 'PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD', + 876: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', + 877: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', + 878: 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', + 879: 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', + 880: 'PH_PERF_SEL_SC7_PA1_NULL_WE', + 881: 'PH_PERF_SEL_SC7_PA1_EVENT_WE', + 882: 'PH_PERF_SEL_SC7_PA1_FPOV_WE', + 883: 'PH_PERF_SEL_SC7_PA1_LPOV_WE', + 884: 'PH_PERF_SEL_SC7_PA1_EOP_WE', + 885: 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', + 886: 'PH_PERF_SEL_SC7_PA1_EOPG_WE', + 887: 'PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD', + 888: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', + 889: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', + 890: 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', + 891: 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', + 892: 'PH_PERF_SEL_SC7_PA2_NULL_WE', + 893: 'PH_PERF_SEL_SC7_PA2_EVENT_WE', + 894: 'PH_PERF_SEL_SC7_PA2_FPOV_WE', + 895: 'PH_PERF_SEL_SC7_PA2_LPOV_WE', + 896: 'PH_PERF_SEL_SC7_PA2_EOP_WE', + 897: 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', + 898: 'PH_PERF_SEL_SC7_PA2_EOPG_WE', + 899: 'PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD', + 900: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', + 901: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', + 902: 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', + 903: 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', + 904: 'PH_PERF_SEL_SC7_PA3_NULL_WE', + 905: 'PH_PERF_SEL_SC7_PA3_EVENT_WE', + 906: 'PH_PERF_SEL_SC7_PA3_FPOV_WE', + 907: 'PH_PERF_SEL_SC7_PA3_LPOV_WE', + 908: 'PH_PERF_SEL_SC7_PA3_EOP_WE', + 909: 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', + 910: 'PH_PERF_SEL_SC7_PA3_EOPG_WE', + 911: 'PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD', + 912: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', + 913: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', + 914: 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', + 915: 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', + 916: 'PH_PERF_SEL_SC7_PA4_NULL_WE', + 917: 'PH_PERF_SEL_SC7_PA4_EVENT_WE', + 918: 'PH_PERF_SEL_SC7_PA4_FPOV_WE', + 919: 'PH_PERF_SEL_SC7_PA4_LPOV_WE', + 920: 'PH_PERF_SEL_SC7_PA4_EOP_WE', + 921: 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', + 922: 'PH_PERF_SEL_SC7_PA4_EOPG_WE', + 923: 'PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD', + 924: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', + 925: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', + 926: 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', + 927: 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', + 928: 'PH_PERF_SEL_SC7_PA5_NULL_WE', + 929: 'PH_PERF_SEL_SC7_PA5_EVENT_WE', + 930: 'PH_PERF_SEL_SC7_PA5_FPOV_WE', + 931: 'PH_PERF_SEL_SC7_PA5_LPOV_WE', + 932: 'PH_PERF_SEL_SC7_PA5_EOP_WE', + 933: 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', + 934: 'PH_PERF_SEL_SC7_PA5_EOPG_WE', + 935: 'PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD', + 936: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', + 937: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', + 938: 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', + 939: 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', + 940: 'PH_PERF_SEL_SC7_PA6_NULL_WE', + 941: 'PH_PERF_SEL_SC7_PA6_EVENT_WE', + 942: 'PH_PERF_SEL_SC7_PA6_FPOV_WE', + 943: 'PH_PERF_SEL_SC7_PA6_LPOV_WE', + 944: 'PH_PERF_SEL_SC7_PA6_EOP_WE', + 945: 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', + 946: 'PH_PERF_SEL_SC7_PA6_EOPG_WE', + 947: 'PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD', + 948: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', + 949: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', + 950: 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', + 951: 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', + 952: 'PH_PERF_SEL_SC7_PA7_NULL_WE', + 953: 'PH_PERF_SEL_SC7_PA7_EVENT_WE', + 954: 'PH_PERF_SEL_SC7_PA7_FPOV_WE', + 955: 'PH_PERF_SEL_SC7_PA7_LPOV_WE', + 956: 'PH_PERF_SEL_SC7_PA7_EOP_WE', + 957: 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', + 958: 'PH_PERF_SEL_SC7_PA7_EOPG_WE', + 959: 'PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD', + 960: 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', + 961: 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', + 962: 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', + 963: 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', + 964: 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', + 965: 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', + 966: 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', + 967: 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', + 968: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', + 969: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', + 970: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', + 971: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', + 972: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', + 973: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', + 974: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', + 975: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', + 976: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 977: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 978: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 979: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 980: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 981: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 982: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 983: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 984: 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 985: 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 986: 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 987: 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 988: 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 989: 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 990: 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 991: 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 992: 'PH_PERF_SC0_FIFO_STATUS_0', + 993: 'PH_PERF_SC0_FIFO_STATUS_1', + 994: 'PH_PERF_SC0_FIFO_STATUS_2', + 995: 'PH_PERF_SC0_FIFO_STATUS_3', + 996: 'PH_PERF_SC1_FIFO_STATUS_0', + 997: 'PH_PERF_SC1_FIFO_STATUS_1', + 998: 'PH_PERF_SC1_FIFO_STATUS_2', + 999: 'PH_PERF_SC1_FIFO_STATUS_3', + 1000: 'PH_PERF_SC2_FIFO_STATUS_0', + 1001: 'PH_PERF_SC2_FIFO_STATUS_1', + 1002: 'PH_PERF_SC2_FIFO_STATUS_2', + 1003: 'PH_PERF_SC2_FIFO_STATUS_3', + 1004: 'PH_PERF_SC3_FIFO_STATUS_0', + 1005: 'PH_PERF_SC3_FIFO_STATUS_1', + 1006: 'PH_PERF_SC3_FIFO_STATUS_2', + 1007: 'PH_PERF_SC3_FIFO_STATUS_3', + 1008: 'PH_PERF_SC4_FIFO_STATUS_0', + 1009: 'PH_PERF_SC4_FIFO_STATUS_1', + 1010: 'PH_PERF_SC4_FIFO_STATUS_2', + 1011: 'PH_PERF_SC4_FIFO_STATUS_3', + 1012: 'PH_PERF_SC5_FIFO_STATUS_0', + 1013: 'PH_PERF_SC5_FIFO_STATUS_1', + 1014: 'PH_PERF_SC5_FIFO_STATUS_2', + 1015: 'PH_PERF_SC5_FIFO_STATUS_3', + 1016: 'PH_PERF_SC6_FIFO_STATUS_0', + 1017: 'PH_PERF_SC6_FIFO_STATUS_1', + 1018: 'PH_PERF_SC6_FIFO_STATUS_2', + 1019: 'PH_PERF_SC6_FIFO_STATUS_3', + 1020: 'PH_PERF_SC7_FIFO_STATUS_0', + 1021: 'PH_PERF_SC7_FIFO_STATUS_1', + 1022: 'PH_PERF_SC7_FIFO_STATUS_2', + 1023: 'PH_PERF_SC7_FIFO_STATUS_3', +} +PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0 +PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 1 +PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 2 +PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 3 +PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 4 +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 5 +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 6 +PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 7 +PH_PERF_SEL_SC0_ARB_BUSY = 8 +PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 9 +PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 10 +PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 11 +PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 12 +PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 13 +PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 14 +PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 15 +PH_PERF_SEL_SC0_SEND = 16 +PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 17 +PH_PERF_SEL_SC0_CREDIT_AT_MAX = 18 +PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 19 +PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 20 +PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 21 +PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 22 +PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 23 +PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 24 +PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 25 +PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 26 +PH_PERF_SEL_SC0_PA0_FIFO_FULL = 27 +PH_PERF_SEL_SC0_PA0_NULL_WE = 28 +PH_PERF_SEL_SC0_PA0_EVENT_WE = 29 +PH_PERF_SEL_SC0_PA0_FPOV_WE = 30 +PH_PERF_SEL_SC0_PA0_LPOV_WE = 31 +PH_PERF_SEL_SC0_PA0_EOP_WE = 32 +PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 33 +PH_PERF_SEL_SC0_PA0_EOPG_WE = 34 +PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD = 35 +PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 36 +PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 37 +PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 38 +PH_PERF_SEL_SC0_PA1_FIFO_FULL = 39 +PH_PERF_SEL_SC0_PA1_NULL_WE = 40 +PH_PERF_SEL_SC0_PA1_EVENT_WE = 41 +PH_PERF_SEL_SC0_PA1_FPOV_WE = 42 +PH_PERF_SEL_SC0_PA1_LPOV_WE = 43 +PH_PERF_SEL_SC0_PA1_EOP_WE = 44 +PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 45 +PH_PERF_SEL_SC0_PA1_EOPG_WE = 46 +PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD = 47 +PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 48 +PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 49 +PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 50 +PH_PERF_SEL_SC0_PA2_FIFO_FULL = 51 +PH_PERF_SEL_SC0_PA2_NULL_WE = 52 +PH_PERF_SEL_SC0_PA2_EVENT_WE = 53 +PH_PERF_SEL_SC0_PA2_FPOV_WE = 54 +PH_PERF_SEL_SC0_PA2_LPOV_WE = 55 +PH_PERF_SEL_SC0_PA2_EOP_WE = 56 +PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 57 +PH_PERF_SEL_SC0_PA2_EOPG_WE = 58 +PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD = 59 +PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 60 +PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 61 +PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 62 +PH_PERF_SEL_SC0_PA3_FIFO_FULL = 63 +PH_PERF_SEL_SC0_PA3_NULL_WE = 64 +PH_PERF_SEL_SC0_PA3_EVENT_WE = 65 +PH_PERF_SEL_SC0_PA3_FPOV_WE = 66 +PH_PERF_SEL_SC0_PA3_LPOV_WE = 67 +PH_PERF_SEL_SC0_PA3_EOP_WE = 68 +PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 69 +PH_PERF_SEL_SC0_PA3_EOPG_WE = 70 +PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD = 71 +PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 72 +PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 73 +PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 74 +PH_PERF_SEL_SC0_PA4_FIFO_FULL = 75 +PH_PERF_SEL_SC0_PA4_NULL_WE = 76 +PH_PERF_SEL_SC0_PA4_EVENT_WE = 77 +PH_PERF_SEL_SC0_PA4_FPOV_WE = 78 +PH_PERF_SEL_SC0_PA4_LPOV_WE = 79 +PH_PERF_SEL_SC0_PA4_EOP_WE = 80 +PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 81 +PH_PERF_SEL_SC0_PA4_EOPG_WE = 82 +PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD = 83 +PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 84 +PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 85 +PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 86 +PH_PERF_SEL_SC0_PA5_FIFO_FULL = 87 +PH_PERF_SEL_SC0_PA5_NULL_WE = 88 +PH_PERF_SEL_SC0_PA5_EVENT_WE = 89 +PH_PERF_SEL_SC0_PA5_FPOV_WE = 90 +PH_PERF_SEL_SC0_PA5_LPOV_WE = 91 +PH_PERF_SEL_SC0_PA5_EOP_WE = 92 +PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 93 +PH_PERF_SEL_SC0_PA5_EOPG_WE = 94 +PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD = 95 +PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 96 +PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 97 +PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 98 +PH_PERF_SEL_SC0_PA6_FIFO_FULL = 99 +PH_PERF_SEL_SC0_PA6_NULL_WE = 100 +PH_PERF_SEL_SC0_PA6_EVENT_WE = 101 +PH_PERF_SEL_SC0_PA6_FPOV_WE = 102 +PH_PERF_SEL_SC0_PA6_LPOV_WE = 103 +PH_PERF_SEL_SC0_PA6_EOP_WE = 104 +PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 105 +PH_PERF_SEL_SC0_PA6_EOPG_WE = 106 +PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD = 107 +PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 108 +PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 109 +PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 110 +PH_PERF_SEL_SC0_PA7_FIFO_FULL = 111 +PH_PERF_SEL_SC0_PA7_NULL_WE = 112 +PH_PERF_SEL_SC0_PA7_EVENT_WE = 113 +PH_PERF_SEL_SC0_PA7_FPOV_WE = 114 +PH_PERF_SEL_SC0_PA7_LPOV_WE = 115 +PH_PERF_SEL_SC0_PA7_EOP_WE = 116 +PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 117 +PH_PERF_SEL_SC0_PA7_EOPG_WE = 118 +PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD = 119 +PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 120 +PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 121 +PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 122 +PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 123 +PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 124 +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 125 +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 126 +PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 127 +PH_PERF_SEL_SC1_ARB_BUSY = 128 +PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 129 +PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 130 +PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 131 +PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 132 +PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 133 +PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 134 +PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 135 +PH_PERF_SEL_SC1_SEND = 136 +PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 137 +PH_PERF_SEL_SC1_CREDIT_AT_MAX = 138 +PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 139 +PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 140 +PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 141 +PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 142 +PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 143 +PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 144 +PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 145 +PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 146 +PH_PERF_SEL_SC1_PA0_FIFO_FULL = 147 +PH_PERF_SEL_SC1_PA0_NULL_WE = 148 +PH_PERF_SEL_SC1_PA0_EVENT_WE = 149 +PH_PERF_SEL_SC1_PA0_FPOV_WE = 150 +PH_PERF_SEL_SC1_PA0_LPOV_WE = 151 +PH_PERF_SEL_SC1_PA0_EOP_WE = 152 +PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 153 +PH_PERF_SEL_SC1_PA0_EOPG_WE = 154 +PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD = 155 +PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 156 +PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 157 +PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 158 +PH_PERF_SEL_SC1_PA1_FIFO_FULL = 159 +PH_PERF_SEL_SC1_PA1_NULL_WE = 160 +PH_PERF_SEL_SC1_PA1_EVENT_WE = 161 +PH_PERF_SEL_SC1_PA1_FPOV_WE = 162 +PH_PERF_SEL_SC1_PA1_LPOV_WE = 163 +PH_PERF_SEL_SC1_PA1_EOP_WE = 164 +PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 165 +PH_PERF_SEL_SC1_PA1_EOPG_WE = 166 +PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD = 167 +PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 168 +PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 169 +PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 170 +PH_PERF_SEL_SC1_PA2_FIFO_FULL = 171 +PH_PERF_SEL_SC1_PA2_NULL_WE = 172 +PH_PERF_SEL_SC1_PA2_EVENT_WE = 173 +PH_PERF_SEL_SC1_PA2_FPOV_WE = 174 +PH_PERF_SEL_SC1_PA2_LPOV_WE = 175 +PH_PERF_SEL_SC1_PA2_EOP_WE = 176 +PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 177 +PH_PERF_SEL_SC1_PA2_EOPG_WE = 178 +PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD = 179 +PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 180 +PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 181 +PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 182 +PH_PERF_SEL_SC1_PA3_FIFO_FULL = 183 +PH_PERF_SEL_SC1_PA3_NULL_WE = 184 +PH_PERF_SEL_SC1_PA3_EVENT_WE = 185 +PH_PERF_SEL_SC1_PA3_FPOV_WE = 186 +PH_PERF_SEL_SC1_PA3_LPOV_WE = 187 +PH_PERF_SEL_SC1_PA3_EOP_WE = 188 +PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 189 +PH_PERF_SEL_SC1_PA3_EOPG_WE = 190 +PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD = 191 +PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 192 +PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 193 +PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 194 +PH_PERF_SEL_SC1_PA4_FIFO_FULL = 195 +PH_PERF_SEL_SC1_PA4_NULL_WE = 196 +PH_PERF_SEL_SC1_PA4_EVENT_WE = 197 +PH_PERF_SEL_SC1_PA4_FPOV_WE = 198 +PH_PERF_SEL_SC1_PA4_LPOV_WE = 199 +PH_PERF_SEL_SC1_PA4_EOP_WE = 200 +PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 201 +PH_PERF_SEL_SC1_PA4_EOPG_WE = 202 +PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD = 203 +PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 204 +PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 205 +PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 206 +PH_PERF_SEL_SC1_PA5_FIFO_FULL = 207 +PH_PERF_SEL_SC1_PA5_NULL_WE = 208 +PH_PERF_SEL_SC1_PA5_EVENT_WE = 209 +PH_PERF_SEL_SC1_PA5_FPOV_WE = 210 +PH_PERF_SEL_SC1_PA5_LPOV_WE = 211 +PH_PERF_SEL_SC1_PA5_EOP_WE = 212 +PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 213 +PH_PERF_SEL_SC1_PA5_EOPG_WE = 214 +PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD = 215 +PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 216 +PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 217 +PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 218 +PH_PERF_SEL_SC1_PA6_FIFO_FULL = 219 +PH_PERF_SEL_SC1_PA6_NULL_WE = 220 +PH_PERF_SEL_SC1_PA6_EVENT_WE = 221 +PH_PERF_SEL_SC1_PA6_FPOV_WE = 222 +PH_PERF_SEL_SC1_PA6_LPOV_WE = 223 +PH_PERF_SEL_SC1_PA6_EOP_WE = 224 +PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 225 +PH_PERF_SEL_SC1_PA6_EOPG_WE = 226 +PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD = 227 +PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 228 +PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 229 +PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 230 +PH_PERF_SEL_SC1_PA7_FIFO_FULL = 231 +PH_PERF_SEL_SC1_PA7_NULL_WE = 232 +PH_PERF_SEL_SC1_PA7_EVENT_WE = 233 +PH_PERF_SEL_SC1_PA7_FPOV_WE = 234 +PH_PERF_SEL_SC1_PA7_LPOV_WE = 235 +PH_PERF_SEL_SC1_PA7_EOP_WE = 236 +PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 237 +PH_PERF_SEL_SC1_PA7_EOPG_WE = 238 +PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD = 239 +PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 240 +PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 241 +PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 242 +PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 243 +PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 244 +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 245 +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 246 +PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 247 +PH_PERF_SEL_SC2_ARB_BUSY = 248 +PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 249 +PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 250 +PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 251 +PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 252 +PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 253 +PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 254 +PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 255 +PH_PERF_SEL_SC2_SEND = 256 +PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 257 +PH_PERF_SEL_SC2_CREDIT_AT_MAX = 258 +PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 259 +PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 260 +PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 261 +PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 262 +PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 263 +PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 264 +PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 265 +PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 266 +PH_PERF_SEL_SC2_PA0_FIFO_FULL = 267 +PH_PERF_SEL_SC2_PA0_NULL_WE = 268 +PH_PERF_SEL_SC2_PA0_EVENT_WE = 269 +PH_PERF_SEL_SC2_PA0_FPOV_WE = 270 +PH_PERF_SEL_SC2_PA0_LPOV_WE = 271 +PH_PERF_SEL_SC2_PA0_EOP_WE = 272 +PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 273 +PH_PERF_SEL_SC2_PA0_EOPG_WE = 274 +PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD = 275 +PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 276 +PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 277 +PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 278 +PH_PERF_SEL_SC2_PA1_FIFO_FULL = 279 +PH_PERF_SEL_SC2_PA1_NULL_WE = 280 +PH_PERF_SEL_SC2_PA1_EVENT_WE = 281 +PH_PERF_SEL_SC2_PA1_FPOV_WE = 282 +PH_PERF_SEL_SC2_PA1_LPOV_WE = 283 +PH_PERF_SEL_SC2_PA1_EOP_WE = 284 +PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 285 +PH_PERF_SEL_SC2_PA1_EOPG_WE = 286 +PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD = 287 +PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 288 +PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 289 +PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 290 +PH_PERF_SEL_SC2_PA2_FIFO_FULL = 291 +PH_PERF_SEL_SC2_PA2_NULL_WE = 292 +PH_PERF_SEL_SC2_PA2_EVENT_WE = 293 +PH_PERF_SEL_SC2_PA2_FPOV_WE = 294 +PH_PERF_SEL_SC2_PA2_LPOV_WE = 295 +PH_PERF_SEL_SC2_PA2_EOP_WE = 296 +PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 297 +PH_PERF_SEL_SC2_PA2_EOPG_WE = 298 +PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD = 299 +PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 300 +PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 301 +PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 302 +PH_PERF_SEL_SC2_PA3_FIFO_FULL = 303 +PH_PERF_SEL_SC2_PA3_NULL_WE = 304 +PH_PERF_SEL_SC2_PA3_EVENT_WE = 305 +PH_PERF_SEL_SC2_PA3_FPOV_WE = 306 +PH_PERF_SEL_SC2_PA3_LPOV_WE = 307 +PH_PERF_SEL_SC2_PA3_EOP_WE = 308 +PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 309 +PH_PERF_SEL_SC2_PA3_EOPG_WE = 310 +PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD = 311 +PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 312 +PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 313 +PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 314 +PH_PERF_SEL_SC2_PA4_FIFO_FULL = 315 +PH_PERF_SEL_SC2_PA4_NULL_WE = 316 +PH_PERF_SEL_SC2_PA4_EVENT_WE = 317 +PH_PERF_SEL_SC2_PA4_FPOV_WE = 318 +PH_PERF_SEL_SC2_PA4_LPOV_WE = 319 +PH_PERF_SEL_SC2_PA4_EOP_WE = 320 +PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 321 +PH_PERF_SEL_SC2_PA4_EOPG_WE = 322 +PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD = 323 +PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 324 +PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 325 +PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 326 +PH_PERF_SEL_SC2_PA5_FIFO_FULL = 327 +PH_PERF_SEL_SC2_PA5_NULL_WE = 328 +PH_PERF_SEL_SC2_PA5_EVENT_WE = 329 +PH_PERF_SEL_SC2_PA5_FPOV_WE = 330 +PH_PERF_SEL_SC2_PA5_LPOV_WE = 331 +PH_PERF_SEL_SC2_PA5_EOP_WE = 332 +PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 333 +PH_PERF_SEL_SC2_PA5_EOPG_WE = 334 +PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD = 335 +PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 336 +PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 337 +PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 338 +PH_PERF_SEL_SC2_PA6_FIFO_FULL = 339 +PH_PERF_SEL_SC2_PA6_NULL_WE = 340 +PH_PERF_SEL_SC2_PA6_EVENT_WE = 341 +PH_PERF_SEL_SC2_PA6_FPOV_WE = 342 +PH_PERF_SEL_SC2_PA6_LPOV_WE = 343 +PH_PERF_SEL_SC2_PA6_EOP_WE = 344 +PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 345 +PH_PERF_SEL_SC2_PA6_EOPG_WE = 346 +PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD = 347 +PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 348 +PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 349 +PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 350 +PH_PERF_SEL_SC2_PA7_FIFO_FULL = 351 +PH_PERF_SEL_SC2_PA7_NULL_WE = 352 +PH_PERF_SEL_SC2_PA7_EVENT_WE = 353 +PH_PERF_SEL_SC2_PA7_FPOV_WE = 354 +PH_PERF_SEL_SC2_PA7_LPOV_WE = 355 +PH_PERF_SEL_SC2_PA7_EOP_WE = 356 +PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 357 +PH_PERF_SEL_SC2_PA7_EOPG_WE = 358 +PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD = 359 +PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 360 +PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 361 +PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 362 +PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 363 +PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 364 +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 365 +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 366 +PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 367 +PH_PERF_SEL_SC3_ARB_BUSY = 368 +PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 369 +PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 370 +PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 371 +PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 372 +PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 373 +PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 374 +PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 375 +PH_PERF_SEL_SC3_SEND = 376 +PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 377 +PH_PERF_SEL_SC3_CREDIT_AT_MAX = 378 +PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 379 +PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 380 +PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 381 +PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 382 +PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 383 +PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 384 +PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 385 +PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 386 +PH_PERF_SEL_SC3_PA0_FIFO_FULL = 387 +PH_PERF_SEL_SC3_PA0_NULL_WE = 388 +PH_PERF_SEL_SC3_PA0_EVENT_WE = 389 +PH_PERF_SEL_SC3_PA0_FPOV_WE = 390 +PH_PERF_SEL_SC3_PA0_LPOV_WE = 391 +PH_PERF_SEL_SC3_PA0_EOP_WE = 392 +PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 393 +PH_PERF_SEL_SC3_PA0_EOPG_WE = 394 +PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD = 395 +PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 396 +PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 397 +PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 398 +PH_PERF_SEL_SC3_PA1_FIFO_FULL = 399 +PH_PERF_SEL_SC3_PA1_NULL_WE = 400 +PH_PERF_SEL_SC3_PA1_EVENT_WE = 401 +PH_PERF_SEL_SC3_PA1_FPOV_WE = 402 +PH_PERF_SEL_SC3_PA1_LPOV_WE = 403 +PH_PERF_SEL_SC3_PA1_EOP_WE = 404 +PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 405 +PH_PERF_SEL_SC3_PA1_EOPG_WE = 406 +PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD = 407 +PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 408 +PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 409 +PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 410 +PH_PERF_SEL_SC3_PA2_FIFO_FULL = 411 +PH_PERF_SEL_SC3_PA2_NULL_WE = 412 +PH_PERF_SEL_SC3_PA2_EVENT_WE = 413 +PH_PERF_SEL_SC3_PA2_FPOV_WE = 414 +PH_PERF_SEL_SC3_PA2_LPOV_WE = 415 +PH_PERF_SEL_SC3_PA2_EOP_WE = 416 +PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 417 +PH_PERF_SEL_SC3_PA2_EOPG_WE = 418 +PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD = 419 +PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 420 +PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 421 +PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 422 +PH_PERF_SEL_SC3_PA3_FIFO_FULL = 423 +PH_PERF_SEL_SC3_PA3_NULL_WE = 424 +PH_PERF_SEL_SC3_PA3_EVENT_WE = 425 +PH_PERF_SEL_SC3_PA3_FPOV_WE = 426 +PH_PERF_SEL_SC3_PA3_LPOV_WE = 427 +PH_PERF_SEL_SC3_PA3_EOP_WE = 428 +PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 429 +PH_PERF_SEL_SC3_PA3_EOPG_WE = 430 +PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD = 431 +PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 432 +PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 433 +PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 434 +PH_PERF_SEL_SC3_PA4_FIFO_FULL = 435 +PH_PERF_SEL_SC3_PA4_NULL_WE = 436 +PH_PERF_SEL_SC3_PA4_EVENT_WE = 437 +PH_PERF_SEL_SC3_PA4_FPOV_WE = 438 +PH_PERF_SEL_SC3_PA4_LPOV_WE = 439 +PH_PERF_SEL_SC3_PA4_EOP_WE = 440 +PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 441 +PH_PERF_SEL_SC3_PA4_EOPG_WE = 442 +PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD = 443 +PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 444 +PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 445 +PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 446 +PH_PERF_SEL_SC3_PA5_FIFO_FULL = 447 +PH_PERF_SEL_SC3_PA5_NULL_WE = 448 +PH_PERF_SEL_SC3_PA5_EVENT_WE = 449 +PH_PERF_SEL_SC3_PA5_FPOV_WE = 450 +PH_PERF_SEL_SC3_PA5_LPOV_WE = 451 +PH_PERF_SEL_SC3_PA5_EOP_WE = 452 +PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 453 +PH_PERF_SEL_SC3_PA5_EOPG_WE = 454 +PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD = 455 +PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 456 +PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 457 +PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 458 +PH_PERF_SEL_SC3_PA6_FIFO_FULL = 459 +PH_PERF_SEL_SC3_PA6_NULL_WE = 460 +PH_PERF_SEL_SC3_PA6_EVENT_WE = 461 +PH_PERF_SEL_SC3_PA6_FPOV_WE = 462 +PH_PERF_SEL_SC3_PA6_LPOV_WE = 463 +PH_PERF_SEL_SC3_PA6_EOP_WE = 464 +PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 465 +PH_PERF_SEL_SC3_PA6_EOPG_WE = 466 +PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD = 467 +PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 468 +PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 469 +PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 470 +PH_PERF_SEL_SC3_PA7_FIFO_FULL = 471 +PH_PERF_SEL_SC3_PA7_NULL_WE = 472 +PH_PERF_SEL_SC3_PA7_EVENT_WE = 473 +PH_PERF_SEL_SC3_PA7_FPOV_WE = 474 +PH_PERF_SEL_SC3_PA7_LPOV_WE = 475 +PH_PERF_SEL_SC3_PA7_EOP_WE = 476 +PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 477 +PH_PERF_SEL_SC3_PA7_EOPG_WE = 478 +PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD = 479 +PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 480 +PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 481 +PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 482 +PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 483 +PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 484 +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 485 +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 486 +PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 487 +PH_PERF_SEL_SC4_ARB_BUSY = 488 +PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 489 +PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 490 +PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 491 +PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 492 +PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 493 +PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 494 +PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 495 +PH_PERF_SEL_SC4_SEND = 496 +PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 497 +PH_PERF_SEL_SC4_CREDIT_AT_MAX = 498 +PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 499 +PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 500 +PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 501 +PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 502 +PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 503 +PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 504 +PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 505 +PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 506 +PH_PERF_SEL_SC4_PA0_FIFO_FULL = 507 +PH_PERF_SEL_SC4_PA0_NULL_WE = 508 +PH_PERF_SEL_SC4_PA0_EVENT_WE = 509 +PH_PERF_SEL_SC4_PA0_FPOV_WE = 510 +PH_PERF_SEL_SC4_PA0_LPOV_WE = 511 +PH_PERF_SEL_SC4_PA0_EOP_WE = 512 +PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 513 +PH_PERF_SEL_SC4_PA0_EOPG_WE = 514 +PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD = 515 +PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 516 +PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 517 +PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 518 +PH_PERF_SEL_SC4_PA1_FIFO_FULL = 519 +PH_PERF_SEL_SC4_PA1_NULL_WE = 520 +PH_PERF_SEL_SC4_PA1_EVENT_WE = 521 +PH_PERF_SEL_SC4_PA1_FPOV_WE = 522 +PH_PERF_SEL_SC4_PA1_LPOV_WE = 523 +PH_PERF_SEL_SC4_PA1_EOP_WE = 524 +PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 525 +PH_PERF_SEL_SC4_PA1_EOPG_WE = 526 +PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD = 527 +PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 528 +PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 529 +PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 530 +PH_PERF_SEL_SC4_PA2_FIFO_FULL = 531 +PH_PERF_SEL_SC4_PA2_NULL_WE = 532 +PH_PERF_SEL_SC4_PA2_EVENT_WE = 533 +PH_PERF_SEL_SC4_PA2_FPOV_WE = 534 +PH_PERF_SEL_SC4_PA2_LPOV_WE = 535 +PH_PERF_SEL_SC4_PA2_EOP_WE = 536 +PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 537 +PH_PERF_SEL_SC4_PA2_EOPG_WE = 538 +PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD = 539 +PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 540 +PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 541 +PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 542 +PH_PERF_SEL_SC4_PA3_FIFO_FULL = 543 +PH_PERF_SEL_SC4_PA3_NULL_WE = 544 +PH_PERF_SEL_SC4_PA3_EVENT_WE = 545 +PH_PERF_SEL_SC4_PA3_FPOV_WE = 546 +PH_PERF_SEL_SC4_PA3_LPOV_WE = 547 +PH_PERF_SEL_SC4_PA3_EOP_WE = 548 +PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 549 +PH_PERF_SEL_SC4_PA3_EOPG_WE = 550 +PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD = 551 +PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 552 +PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 553 +PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 554 +PH_PERF_SEL_SC4_PA4_FIFO_FULL = 555 +PH_PERF_SEL_SC4_PA4_NULL_WE = 556 +PH_PERF_SEL_SC4_PA4_EVENT_WE = 557 +PH_PERF_SEL_SC4_PA4_FPOV_WE = 558 +PH_PERF_SEL_SC4_PA4_LPOV_WE = 559 +PH_PERF_SEL_SC4_PA4_EOP_WE = 560 +PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 561 +PH_PERF_SEL_SC4_PA4_EOPG_WE = 562 +PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD = 563 +PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 564 +PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 565 +PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 566 +PH_PERF_SEL_SC4_PA5_FIFO_FULL = 567 +PH_PERF_SEL_SC4_PA5_NULL_WE = 568 +PH_PERF_SEL_SC4_PA5_EVENT_WE = 569 +PH_PERF_SEL_SC4_PA5_FPOV_WE = 570 +PH_PERF_SEL_SC4_PA5_LPOV_WE = 571 +PH_PERF_SEL_SC4_PA5_EOP_WE = 572 +PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 573 +PH_PERF_SEL_SC4_PA5_EOPG_WE = 574 +PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD = 575 +PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 576 +PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 577 +PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 578 +PH_PERF_SEL_SC4_PA6_FIFO_FULL = 579 +PH_PERF_SEL_SC4_PA6_NULL_WE = 580 +PH_PERF_SEL_SC4_PA6_EVENT_WE = 581 +PH_PERF_SEL_SC4_PA6_FPOV_WE = 582 +PH_PERF_SEL_SC4_PA6_LPOV_WE = 583 +PH_PERF_SEL_SC4_PA6_EOP_WE = 584 +PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 585 +PH_PERF_SEL_SC4_PA6_EOPG_WE = 586 +PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD = 587 +PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 588 +PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 589 +PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 590 +PH_PERF_SEL_SC4_PA7_FIFO_FULL = 591 +PH_PERF_SEL_SC4_PA7_NULL_WE = 592 +PH_PERF_SEL_SC4_PA7_EVENT_WE = 593 +PH_PERF_SEL_SC4_PA7_FPOV_WE = 594 +PH_PERF_SEL_SC4_PA7_LPOV_WE = 595 +PH_PERF_SEL_SC4_PA7_EOP_WE = 596 +PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 597 +PH_PERF_SEL_SC4_PA7_EOPG_WE = 598 +PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD = 599 +PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 600 +PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 601 +PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 602 +PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 603 +PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 604 +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 605 +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 606 +PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 607 +PH_PERF_SEL_SC5_ARB_BUSY = 608 +PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 609 +PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 610 +PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 611 +PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 612 +PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 613 +PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 614 +PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 615 +PH_PERF_SEL_SC5_SEND = 616 +PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 617 +PH_PERF_SEL_SC5_CREDIT_AT_MAX = 618 +PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 619 +PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 620 +PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 621 +PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 622 +PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 623 +PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 624 +PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 625 +PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 626 +PH_PERF_SEL_SC5_PA0_FIFO_FULL = 627 +PH_PERF_SEL_SC5_PA0_NULL_WE = 628 +PH_PERF_SEL_SC5_PA0_EVENT_WE = 629 +PH_PERF_SEL_SC5_PA0_FPOV_WE = 630 +PH_PERF_SEL_SC5_PA0_LPOV_WE = 631 +PH_PERF_SEL_SC5_PA0_EOP_WE = 632 +PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 633 +PH_PERF_SEL_SC5_PA0_EOPG_WE = 634 +PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD = 635 +PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 636 +PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 637 +PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 638 +PH_PERF_SEL_SC5_PA1_FIFO_FULL = 639 +PH_PERF_SEL_SC5_PA1_NULL_WE = 640 +PH_PERF_SEL_SC5_PA1_EVENT_WE = 641 +PH_PERF_SEL_SC5_PA1_FPOV_WE = 642 +PH_PERF_SEL_SC5_PA1_LPOV_WE = 643 +PH_PERF_SEL_SC5_PA1_EOP_WE = 644 +PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 645 +PH_PERF_SEL_SC5_PA1_EOPG_WE = 646 +PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD = 647 +PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 648 +PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 649 +PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 650 +PH_PERF_SEL_SC5_PA2_FIFO_FULL = 651 +PH_PERF_SEL_SC5_PA2_NULL_WE = 652 +PH_PERF_SEL_SC5_PA2_EVENT_WE = 653 +PH_PERF_SEL_SC5_PA2_FPOV_WE = 654 +PH_PERF_SEL_SC5_PA2_LPOV_WE = 655 +PH_PERF_SEL_SC5_PA2_EOP_WE = 656 +PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 657 +PH_PERF_SEL_SC5_PA2_EOPG_WE = 658 +PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD = 659 +PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 660 +PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 661 +PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 662 +PH_PERF_SEL_SC5_PA3_FIFO_FULL = 663 +PH_PERF_SEL_SC5_PA3_NULL_WE = 664 +PH_PERF_SEL_SC5_PA3_EVENT_WE = 665 +PH_PERF_SEL_SC5_PA3_FPOV_WE = 666 +PH_PERF_SEL_SC5_PA3_LPOV_WE = 667 +PH_PERF_SEL_SC5_PA3_EOP_WE = 668 +PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 669 +PH_PERF_SEL_SC5_PA3_EOPG_WE = 670 +PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD = 671 +PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 672 +PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 673 +PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 674 +PH_PERF_SEL_SC5_PA4_FIFO_FULL = 675 +PH_PERF_SEL_SC5_PA4_NULL_WE = 676 +PH_PERF_SEL_SC5_PA4_EVENT_WE = 677 +PH_PERF_SEL_SC5_PA4_FPOV_WE = 678 +PH_PERF_SEL_SC5_PA4_LPOV_WE = 679 +PH_PERF_SEL_SC5_PA4_EOP_WE = 680 +PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 681 +PH_PERF_SEL_SC5_PA4_EOPG_WE = 682 +PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD = 683 +PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 684 +PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 685 +PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 686 +PH_PERF_SEL_SC5_PA5_FIFO_FULL = 687 +PH_PERF_SEL_SC5_PA5_NULL_WE = 688 +PH_PERF_SEL_SC5_PA5_EVENT_WE = 689 +PH_PERF_SEL_SC5_PA5_FPOV_WE = 690 +PH_PERF_SEL_SC5_PA5_LPOV_WE = 691 +PH_PERF_SEL_SC5_PA5_EOP_WE = 692 +PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 693 +PH_PERF_SEL_SC5_PA5_EOPG_WE = 694 +PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD = 695 +PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 696 +PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 697 +PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 698 +PH_PERF_SEL_SC5_PA6_FIFO_FULL = 699 +PH_PERF_SEL_SC5_PA6_NULL_WE = 700 +PH_PERF_SEL_SC5_PA6_EVENT_WE = 701 +PH_PERF_SEL_SC5_PA6_FPOV_WE = 702 +PH_PERF_SEL_SC5_PA6_LPOV_WE = 703 +PH_PERF_SEL_SC5_PA6_EOP_WE = 704 +PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 705 +PH_PERF_SEL_SC5_PA6_EOPG_WE = 706 +PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD = 707 +PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 708 +PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 709 +PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 710 +PH_PERF_SEL_SC5_PA7_FIFO_FULL = 711 +PH_PERF_SEL_SC5_PA7_NULL_WE = 712 +PH_PERF_SEL_SC5_PA7_EVENT_WE = 713 +PH_PERF_SEL_SC5_PA7_FPOV_WE = 714 +PH_PERF_SEL_SC5_PA7_LPOV_WE = 715 +PH_PERF_SEL_SC5_PA7_EOP_WE = 716 +PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 717 +PH_PERF_SEL_SC5_PA7_EOPG_WE = 718 +PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD = 719 +PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 720 +PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 721 +PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 722 +PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 723 +PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 724 +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 725 +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 726 +PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 727 +PH_PERF_SEL_SC6_ARB_BUSY = 728 +PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 729 +PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 730 +PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 731 +PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 732 +PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 733 +PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 734 +PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 735 +PH_PERF_SEL_SC6_SEND = 736 +PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 737 +PH_PERF_SEL_SC6_CREDIT_AT_MAX = 738 +PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 739 +PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 740 +PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 741 +PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 742 +PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 743 +PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 744 +PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 745 +PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 746 +PH_PERF_SEL_SC6_PA0_FIFO_FULL = 747 +PH_PERF_SEL_SC6_PA0_NULL_WE = 748 +PH_PERF_SEL_SC6_PA0_EVENT_WE = 749 +PH_PERF_SEL_SC6_PA0_FPOV_WE = 750 +PH_PERF_SEL_SC6_PA0_LPOV_WE = 751 +PH_PERF_SEL_SC6_PA0_EOP_WE = 752 +PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 753 +PH_PERF_SEL_SC6_PA0_EOPG_WE = 754 +PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD = 755 +PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 756 +PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 757 +PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 758 +PH_PERF_SEL_SC6_PA1_FIFO_FULL = 759 +PH_PERF_SEL_SC6_PA1_NULL_WE = 760 +PH_PERF_SEL_SC6_PA1_EVENT_WE = 761 +PH_PERF_SEL_SC6_PA1_FPOV_WE = 762 +PH_PERF_SEL_SC6_PA1_LPOV_WE = 763 +PH_PERF_SEL_SC6_PA1_EOP_WE = 764 +PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 765 +PH_PERF_SEL_SC6_PA1_EOPG_WE = 766 +PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD = 767 +PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 768 +PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 769 +PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 770 +PH_PERF_SEL_SC6_PA2_FIFO_FULL = 771 +PH_PERF_SEL_SC6_PA2_NULL_WE = 772 +PH_PERF_SEL_SC6_PA2_EVENT_WE = 773 +PH_PERF_SEL_SC6_PA2_FPOV_WE = 774 +PH_PERF_SEL_SC6_PA2_LPOV_WE = 775 +PH_PERF_SEL_SC6_PA2_EOP_WE = 776 +PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 777 +PH_PERF_SEL_SC6_PA2_EOPG_WE = 778 +PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD = 779 +PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 780 +PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 781 +PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 782 +PH_PERF_SEL_SC6_PA3_FIFO_FULL = 783 +PH_PERF_SEL_SC6_PA3_NULL_WE = 784 +PH_PERF_SEL_SC6_PA3_EVENT_WE = 785 +PH_PERF_SEL_SC6_PA3_FPOV_WE = 786 +PH_PERF_SEL_SC6_PA3_LPOV_WE = 787 +PH_PERF_SEL_SC6_PA3_EOP_WE = 788 +PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 789 +PH_PERF_SEL_SC6_PA3_EOPG_WE = 790 +PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD = 791 +PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 792 +PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 793 +PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 794 +PH_PERF_SEL_SC6_PA4_FIFO_FULL = 795 +PH_PERF_SEL_SC6_PA4_NULL_WE = 796 +PH_PERF_SEL_SC6_PA4_EVENT_WE = 797 +PH_PERF_SEL_SC6_PA4_FPOV_WE = 798 +PH_PERF_SEL_SC6_PA4_LPOV_WE = 799 +PH_PERF_SEL_SC6_PA4_EOP_WE = 800 +PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 801 +PH_PERF_SEL_SC6_PA4_EOPG_WE = 802 +PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD = 803 +PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 804 +PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 805 +PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 806 +PH_PERF_SEL_SC6_PA5_FIFO_FULL = 807 +PH_PERF_SEL_SC6_PA5_NULL_WE = 808 +PH_PERF_SEL_SC6_PA5_EVENT_WE = 809 +PH_PERF_SEL_SC6_PA5_FPOV_WE = 810 +PH_PERF_SEL_SC6_PA5_LPOV_WE = 811 +PH_PERF_SEL_SC6_PA5_EOP_WE = 812 +PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 813 +PH_PERF_SEL_SC6_PA5_EOPG_WE = 814 +PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD = 815 +PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 816 +PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 817 +PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 818 +PH_PERF_SEL_SC6_PA6_FIFO_FULL = 819 +PH_PERF_SEL_SC6_PA6_NULL_WE = 820 +PH_PERF_SEL_SC6_PA6_EVENT_WE = 821 +PH_PERF_SEL_SC6_PA6_FPOV_WE = 822 +PH_PERF_SEL_SC6_PA6_LPOV_WE = 823 +PH_PERF_SEL_SC6_PA6_EOP_WE = 824 +PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 825 +PH_PERF_SEL_SC6_PA6_EOPG_WE = 826 +PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD = 827 +PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 828 +PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 829 +PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 830 +PH_PERF_SEL_SC6_PA7_FIFO_FULL = 831 +PH_PERF_SEL_SC6_PA7_NULL_WE = 832 +PH_PERF_SEL_SC6_PA7_EVENT_WE = 833 +PH_PERF_SEL_SC6_PA7_FPOV_WE = 834 +PH_PERF_SEL_SC6_PA7_LPOV_WE = 835 +PH_PERF_SEL_SC6_PA7_EOP_WE = 836 +PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 837 +PH_PERF_SEL_SC6_PA7_EOPG_WE = 838 +PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD = 839 +PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 840 +PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 841 +PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 842 +PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 843 +PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 844 +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 845 +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 846 +PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 847 +PH_PERF_SEL_SC7_ARB_BUSY = 848 +PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 849 +PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 850 +PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 851 +PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 852 +PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 853 +PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 854 +PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 855 +PH_PERF_SEL_SC7_SEND = 856 +PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 857 +PH_PERF_SEL_SC7_CREDIT_AT_MAX = 858 +PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 859 +PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 860 +PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 861 +PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 862 +PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 863 +PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 864 +PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 865 +PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 866 +PH_PERF_SEL_SC7_PA0_FIFO_FULL = 867 +PH_PERF_SEL_SC7_PA0_NULL_WE = 868 +PH_PERF_SEL_SC7_PA0_EVENT_WE = 869 +PH_PERF_SEL_SC7_PA0_FPOV_WE = 870 +PH_PERF_SEL_SC7_PA0_LPOV_WE = 871 +PH_PERF_SEL_SC7_PA0_EOP_WE = 872 +PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 873 +PH_PERF_SEL_SC7_PA0_EOPG_WE = 874 +PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD = 875 +PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 876 +PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 877 +PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 878 +PH_PERF_SEL_SC7_PA1_FIFO_FULL = 879 +PH_PERF_SEL_SC7_PA1_NULL_WE = 880 +PH_PERF_SEL_SC7_PA1_EVENT_WE = 881 +PH_PERF_SEL_SC7_PA1_FPOV_WE = 882 +PH_PERF_SEL_SC7_PA1_LPOV_WE = 883 +PH_PERF_SEL_SC7_PA1_EOP_WE = 884 +PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 885 +PH_PERF_SEL_SC7_PA1_EOPG_WE = 886 +PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD = 887 +PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 888 +PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 889 +PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 890 +PH_PERF_SEL_SC7_PA2_FIFO_FULL = 891 +PH_PERF_SEL_SC7_PA2_NULL_WE = 892 +PH_PERF_SEL_SC7_PA2_EVENT_WE = 893 +PH_PERF_SEL_SC7_PA2_FPOV_WE = 894 +PH_PERF_SEL_SC7_PA2_LPOV_WE = 895 +PH_PERF_SEL_SC7_PA2_EOP_WE = 896 +PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 897 +PH_PERF_SEL_SC7_PA2_EOPG_WE = 898 +PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD = 899 +PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 900 +PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 901 +PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 902 +PH_PERF_SEL_SC7_PA3_FIFO_FULL = 903 +PH_PERF_SEL_SC7_PA3_NULL_WE = 904 +PH_PERF_SEL_SC7_PA3_EVENT_WE = 905 +PH_PERF_SEL_SC7_PA3_FPOV_WE = 906 +PH_PERF_SEL_SC7_PA3_LPOV_WE = 907 +PH_PERF_SEL_SC7_PA3_EOP_WE = 908 +PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 909 +PH_PERF_SEL_SC7_PA3_EOPG_WE = 910 +PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD = 911 +PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 912 +PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 913 +PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 914 +PH_PERF_SEL_SC7_PA4_FIFO_FULL = 915 +PH_PERF_SEL_SC7_PA4_NULL_WE = 916 +PH_PERF_SEL_SC7_PA4_EVENT_WE = 917 +PH_PERF_SEL_SC7_PA4_FPOV_WE = 918 +PH_PERF_SEL_SC7_PA4_LPOV_WE = 919 +PH_PERF_SEL_SC7_PA4_EOP_WE = 920 +PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 921 +PH_PERF_SEL_SC7_PA4_EOPG_WE = 922 +PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD = 923 +PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 924 +PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 925 +PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 926 +PH_PERF_SEL_SC7_PA5_FIFO_FULL = 927 +PH_PERF_SEL_SC7_PA5_NULL_WE = 928 +PH_PERF_SEL_SC7_PA5_EVENT_WE = 929 +PH_PERF_SEL_SC7_PA5_FPOV_WE = 930 +PH_PERF_SEL_SC7_PA5_LPOV_WE = 931 +PH_PERF_SEL_SC7_PA5_EOP_WE = 932 +PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 933 +PH_PERF_SEL_SC7_PA5_EOPG_WE = 934 +PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD = 935 +PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 936 +PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 937 +PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 938 +PH_PERF_SEL_SC7_PA6_FIFO_FULL = 939 +PH_PERF_SEL_SC7_PA6_NULL_WE = 940 +PH_PERF_SEL_SC7_PA6_EVENT_WE = 941 +PH_PERF_SEL_SC7_PA6_FPOV_WE = 942 +PH_PERF_SEL_SC7_PA6_LPOV_WE = 943 +PH_PERF_SEL_SC7_PA6_EOP_WE = 944 +PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 945 +PH_PERF_SEL_SC7_PA6_EOPG_WE = 946 +PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD = 947 +PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 948 +PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 949 +PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 950 +PH_PERF_SEL_SC7_PA7_FIFO_FULL = 951 +PH_PERF_SEL_SC7_PA7_NULL_WE = 952 +PH_PERF_SEL_SC7_PA7_EVENT_WE = 953 +PH_PERF_SEL_SC7_PA7_FPOV_WE = 954 +PH_PERF_SEL_SC7_PA7_LPOV_WE = 955 +PH_PERF_SEL_SC7_PA7_EOP_WE = 956 +PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 957 +PH_PERF_SEL_SC7_PA7_EOPG_WE = 958 +PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD = 959 +PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 960 +PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 961 +PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 962 +PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 963 +PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 964 +PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 965 +PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 966 +PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 967 +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 968 +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 969 +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 970 +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 971 +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 972 +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 973 +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 974 +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 975 +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 976 +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 977 +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 978 +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 979 +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 980 +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 981 +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 982 +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 983 +PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 984 +PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 985 +PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 986 +PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 987 +PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 988 +PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 989 +PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 990 +PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 991 +PH_PERF_SC0_FIFO_STATUS_0 = 992 +PH_PERF_SC0_FIFO_STATUS_1 = 993 +PH_PERF_SC0_FIFO_STATUS_2 = 994 +PH_PERF_SC0_FIFO_STATUS_3 = 995 +PH_PERF_SC1_FIFO_STATUS_0 = 996 +PH_PERF_SC1_FIFO_STATUS_1 = 997 +PH_PERF_SC1_FIFO_STATUS_2 = 998 +PH_PERF_SC1_FIFO_STATUS_3 = 999 +PH_PERF_SC2_FIFO_STATUS_0 = 1000 +PH_PERF_SC2_FIFO_STATUS_1 = 1001 +PH_PERF_SC2_FIFO_STATUS_2 = 1002 +PH_PERF_SC2_FIFO_STATUS_3 = 1003 +PH_PERF_SC3_FIFO_STATUS_0 = 1004 +PH_PERF_SC3_FIFO_STATUS_1 = 1005 +PH_PERF_SC3_FIFO_STATUS_2 = 1006 +PH_PERF_SC3_FIFO_STATUS_3 = 1007 +PH_PERF_SC4_FIFO_STATUS_0 = 1008 +PH_PERF_SC4_FIFO_STATUS_1 = 1009 +PH_PERF_SC4_FIFO_STATUS_2 = 1010 +PH_PERF_SC4_FIFO_STATUS_3 = 1011 +PH_PERF_SC5_FIFO_STATUS_0 = 1012 +PH_PERF_SC5_FIFO_STATUS_1 = 1013 +PH_PERF_SC5_FIFO_STATUS_2 = 1014 +PH_PERF_SC5_FIFO_STATUS_3 = 1015 +PH_PERF_SC6_FIFO_STATUS_0 = 1016 +PH_PERF_SC6_FIFO_STATUS_1 = 1017 +PH_PERF_SC6_FIFO_STATUS_2 = 1018 +PH_PERF_SC6_FIFO_STATUS_3 = 1019 +PH_PERF_SC7_FIFO_STATUS_0 = 1020 +PH_PERF_SC7_FIFO_STATUS_1 = 1021 +PH_PERF_SC7_FIFO_STATUS_2 = 1022 +PH_PERF_SC7_FIFO_STATUS_3 = 1023 +PH_PERFCNT_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'PhSPIstatusMode' +PhSPIstatusMode__enumvalues = { + 0: 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', + 1: 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', + 2: 'PH_SPI_MODE_DISABLED', +} +PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0 +PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 1 +PH_SPI_MODE_DISABLED = 2 +PhSPIstatusMode = ctypes.c_uint32 # enum + +# values for enumeration 'RMIPerfSel' +RMIPerfSel__enumvalues = { + 0: 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', + 1: 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', +} +RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0 +RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 1 +RMIPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'GCRPerfSel' +GCRPerfSel__enumvalues = { + 0: 'GCR_PERF_SEL_NONE', + 1: 'GCR_PERF_SEL_SDMA0_ALL_REQ', + 2: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', + 3: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', + 4: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', + 5: 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', + 6: 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', + 7: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', + 8: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', + 9: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', + 10: 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', + 11: 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', + 12: 'GCR_PERF_SEL_SDMA0_METADATA_REQ', + 13: 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', + 14: 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', + 15: 'GCR_PERF_SEL_SDMA0_TCP_REQ', + 16: 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', + 17: 'GCR_PERF_SEL_SDMA1_ALL_REQ', + 18: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', + 19: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', + 20: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', + 21: 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', + 22: 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', + 23: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', + 24: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', + 25: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', + 26: 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', + 27: 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', + 28: 'GCR_PERF_SEL_SDMA1_METADATA_REQ', + 29: 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', + 30: 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', + 31: 'GCR_PERF_SEL_SDMA1_TCP_REQ', + 32: 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', + 33: 'GCR_PERF_SEL_CPC_ALL_REQ', + 34: 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', + 35: 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', + 36: 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', + 37: 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', + 38: 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', + 39: 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', + 40: 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', + 41: 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', + 42: 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', + 43: 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', + 44: 'GCR_PERF_SEL_CPC_METADATA_REQ', + 45: 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', + 46: 'GCR_PERF_SEL_CPC_SQC_INST_REQ', + 47: 'GCR_PERF_SEL_CPC_TCP_REQ', + 48: 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', + 49: 'GCR_PERF_SEL_CPG_ALL_REQ', + 50: 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', + 51: 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', + 52: 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', + 53: 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', + 54: 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', + 55: 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', + 56: 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', + 57: 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', + 58: 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', + 59: 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', + 60: 'GCR_PERF_SEL_CPG_METADATA_REQ', + 61: 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', + 62: 'GCR_PERF_SEL_CPG_SQC_INST_REQ', + 63: 'GCR_PERF_SEL_CPG_TCP_REQ', + 64: 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', + 65: 'GCR_PERF_SEL_CPF_ALL_REQ', + 66: 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', + 67: 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', + 68: 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', + 69: 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', + 70: 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', + 71: 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', + 72: 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', + 73: 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', + 74: 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', + 75: 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', + 76: 'GCR_PERF_SEL_CPF_METADATA_REQ', + 77: 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', + 78: 'GCR_PERF_SEL_CPF_SQC_INST_REQ', + 79: 'GCR_PERF_SEL_CPF_TCP_REQ', + 80: 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', + 81: 'GCR_PERF_SEL_VIRT_REQ', + 82: 'GCR_PERF_SEL_PHY_REQ', + 83: 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', + 84: 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', + 85: 'GCR_PERF_SEL_ALL_REQ', + 86: 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', + 87: 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', + 88: 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', + 89: 'GCR_PERF_SEL_UTCL2_REQ', + 90: 'GCR_PERF_SEL_UTCL2_RET', + 91: 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', + 92: 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', + 93: 'GCR_PERF_SEL_UTCL2_FILTERED_RET', + 94: 'GCR_PERF_SEL_RLC_ALL_REQ', + 95: 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', + 96: 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', + 97: 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', + 98: 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', + 99: 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', + 100: 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', + 101: 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', + 102: 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', + 103: 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', + 104: 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', + 105: 'GCR_PERF_SEL_RLC_METADATA_REQ', + 106: 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', + 107: 'GCR_PERF_SEL_RLC_SQC_INST_REQ', + 108: 'GCR_PERF_SEL_RLC_TCP_REQ', + 109: 'GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ', + 110: 'GCR_PERF_SEL_PM_ALL_REQ', + 111: 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', + 112: 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', + 113: 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', + 114: 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', + 115: 'GCR_PERF_SEL_PM_GL2_ALL_REQ', + 116: 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', + 117: 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', + 118: 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', + 119: 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', + 120: 'GCR_PERF_SEL_PM_GL1_ALL_REQ', + 121: 'GCR_PERF_SEL_PM_METADATA_REQ', + 122: 'GCR_PERF_SEL_PM_SQC_DATA_REQ', + 123: 'GCR_PERF_SEL_PM_SQC_INST_REQ', + 124: 'GCR_PERF_SEL_PM_TCP_REQ', + 125: 'GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ', + 126: 'GCR_PERF_SEL_PIO_ALL_REQ', + 127: 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', + 128: 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', + 129: 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', + 130: 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', + 131: 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', + 132: 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', + 133: 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', + 134: 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', + 135: 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', + 136: 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', + 137: 'GCR_PERF_SEL_PIO_METADATA_REQ', + 138: 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', + 139: 'GCR_PERF_SEL_PIO_SQC_INST_REQ', + 140: 'GCR_PERF_SEL_PIO_TCP_REQ', + 141: 'GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ', +} +GCR_PERF_SEL_NONE = 0 +GCR_PERF_SEL_SDMA0_ALL_REQ = 1 +GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 2 +GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 3 +GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 4 +GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 5 +GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 6 +GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 7 +GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 8 +GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 9 +GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 10 +GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 11 +GCR_PERF_SEL_SDMA0_METADATA_REQ = 12 +GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 13 +GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 14 +GCR_PERF_SEL_SDMA0_TCP_REQ = 15 +GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 16 +GCR_PERF_SEL_SDMA1_ALL_REQ = 17 +GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 18 +GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 19 +GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 20 +GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 21 +GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 22 +GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 23 +GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 24 +GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 25 +GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 26 +GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 27 +GCR_PERF_SEL_SDMA1_METADATA_REQ = 28 +GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 29 +GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 30 +GCR_PERF_SEL_SDMA1_TCP_REQ = 31 +GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 32 +GCR_PERF_SEL_CPC_ALL_REQ = 33 +GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 34 +GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 35 +GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 36 +GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 37 +GCR_PERF_SEL_CPC_GL2_ALL_REQ = 38 +GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 39 +GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 40 +GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 41 +GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 42 +GCR_PERF_SEL_CPC_GL1_ALL_REQ = 43 +GCR_PERF_SEL_CPC_METADATA_REQ = 44 +GCR_PERF_SEL_CPC_SQC_DATA_REQ = 45 +GCR_PERF_SEL_CPC_SQC_INST_REQ = 46 +GCR_PERF_SEL_CPC_TCP_REQ = 47 +GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 48 +GCR_PERF_SEL_CPG_ALL_REQ = 49 +GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 50 +GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 51 +GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 52 +GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 53 +GCR_PERF_SEL_CPG_GL2_ALL_REQ = 54 +GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 55 +GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 56 +GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 57 +GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 58 +GCR_PERF_SEL_CPG_GL1_ALL_REQ = 59 +GCR_PERF_SEL_CPG_METADATA_REQ = 60 +GCR_PERF_SEL_CPG_SQC_DATA_REQ = 61 +GCR_PERF_SEL_CPG_SQC_INST_REQ = 62 +GCR_PERF_SEL_CPG_TCP_REQ = 63 +GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 64 +GCR_PERF_SEL_CPF_ALL_REQ = 65 +GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 66 +GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 67 +GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 68 +GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 69 +GCR_PERF_SEL_CPF_GL2_ALL_REQ = 70 +GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 71 +GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 72 +GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 73 +GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 74 +GCR_PERF_SEL_CPF_GL1_ALL_REQ = 75 +GCR_PERF_SEL_CPF_METADATA_REQ = 76 +GCR_PERF_SEL_CPF_SQC_DATA_REQ = 77 +GCR_PERF_SEL_CPF_SQC_INST_REQ = 78 +GCR_PERF_SEL_CPF_TCP_REQ = 79 +GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 80 +GCR_PERF_SEL_VIRT_REQ = 81 +GCR_PERF_SEL_PHY_REQ = 82 +GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 83 +GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 84 +GCR_PERF_SEL_ALL_REQ = 85 +GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 86 +GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 87 +GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 88 +GCR_PERF_SEL_UTCL2_REQ = 89 +GCR_PERF_SEL_UTCL2_RET = 90 +GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 91 +GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 92 +GCR_PERF_SEL_UTCL2_FILTERED_RET = 93 +GCR_PERF_SEL_RLC_ALL_REQ = 94 +GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 95 +GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 96 +GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 97 +GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 98 +GCR_PERF_SEL_RLC_GL2_ALL_REQ = 99 +GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 100 +GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 101 +GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 102 +GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 103 +GCR_PERF_SEL_RLC_GL1_ALL_REQ = 104 +GCR_PERF_SEL_RLC_METADATA_REQ = 105 +GCR_PERF_SEL_RLC_SQC_DATA_REQ = 106 +GCR_PERF_SEL_RLC_SQC_INST_REQ = 107 +GCR_PERF_SEL_RLC_TCP_REQ = 108 +GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ = 109 +GCR_PERF_SEL_PM_ALL_REQ = 110 +GCR_PERF_SEL_PM_GL2_RANGE_REQ = 111 +GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 112 +GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 113 +GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 114 +GCR_PERF_SEL_PM_GL2_ALL_REQ = 115 +GCR_PERF_SEL_PM_GL1_RANGE_REQ = 116 +GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 117 +GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 118 +GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 119 +GCR_PERF_SEL_PM_GL1_ALL_REQ = 120 +GCR_PERF_SEL_PM_METADATA_REQ = 121 +GCR_PERF_SEL_PM_SQC_DATA_REQ = 122 +GCR_PERF_SEL_PM_SQC_INST_REQ = 123 +GCR_PERF_SEL_PM_TCP_REQ = 124 +GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ = 125 +GCR_PERF_SEL_PIO_ALL_REQ = 126 +GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 127 +GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 128 +GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 129 +GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 130 +GCR_PERF_SEL_PIO_GL2_ALL_REQ = 131 +GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 132 +GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 133 +GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 134 +GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 135 +GCR_PERF_SEL_PIO_GL1_ALL_REQ = 136 +GCR_PERF_SEL_PIO_METADATA_REQ = 137 +GCR_PERF_SEL_PIO_SQC_DATA_REQ = 138 +GCR_PERF_SEL_PIO_SQC_INST_REQ = 139 +GCR_PERF_SEL_PIO_TCP_REQ = 140 +GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ = 141 +GCRPerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'UTCL1PerfSel' +UTCL1PerfSel__enumvalues = { + 0: 'UTCL1_PERF_SEL_NONE', + 1: 'UTCL1_PERF_SEL_REQS', + 2: 'UTCL1_PERF_SEL_HITS', + 3: 'UTCL1_PERF_SEL_MISSES', + 4: 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', + 5: 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', + 6: 'UTCL1_PERF_SEL_UTCL2_REQS', + 7: 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', + 8: 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', + 9: 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', + 10: 'UTCL1_PERF_SEL_STALL_MH_FULL', + 11: 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', + 12: 'UTCL1_PERF_SEL_UTCL2_RET_CNT', + 13: 'UTCL1_PERF_SEL_RTNS', + 14: 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', + 15: 'UTCL1_PERF_SEL_BYPASS_REQS', + 16: 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', + 17: 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', + 18: 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', + 19: 'UTCL1_PERF_SEL_CP_INVREQS', + 20: 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', + 21: 'UTCL1_PERF_SEL_RANGE_INVREQS', + 22: 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', +} +UTCL1_PERF_SEL_NONE = 0 +UTCL1_PERF_SEL_REQS = 1 +UTCL1_PERF_SEL_HITS = 2 +UTCL1_PERF_SEL_MISSES = 3 +UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 4 +UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 5 +UTCL1_PERF_SEL_UTCL2_REQS = 6 +UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 7 +UTCL1_PERF_SEL_UTCL2_RET_FAULT = 8 +UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 9 +UTCL1_PERF_SEL_STALL_MH_FULL = 10 +UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 11 +UTCL1_PERF_SEL_UTCL2_RET_CNT = 12 +UTCL1_PERF_SEL_RTNS = 13 +UTCL1_PERF_SEL_XLAT_REQ_BUSY = 14 +UTCL1_PERF_SEL_BYPASS_REQS = 15 +UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 16 +UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 17 +UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 18 +UTCL1_PERF_SEL_CP_INVREQS = 19 +UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 20 +UTCL1_PERF_SEL_RANGE_INVREQS = 21 +UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 22 +UTCL1PerfSel = ctypes.c_uint32 # enum + +# values for enumeration 'IH_CLIENT_TYPE' +IH_CLIENT_TYPE__enumvalues = { + 0: 'IH_GFX_VMID_CLIENT', + 1: 'IH_MM_VMID_CLIENT', + 2: 'IH_MULTI_VMID_CLIENT', + 3: 'IH_CLIENT_TYPE_RESERVED', +} +IH_GFX_VMID_CLIENT = 0 +IH_MM_VMID_CLIENT = 1 +IH_MULTI_VMID_CLIENT = 2 +IH_CLIENT_TYPE_RESERVED = 3 +IH_CLIENT_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'IH_INTERFACE_TYPE' +IH_INTERFACE_TYPE__enumvalues = { + 0: 'IH_LEGACY_INTERFACE', + 1: 'IH_REGISTER_WRITE_INTERFACE', +} +IH_LEGACY_INTERFACE = 0 +IH_REGISTER_WRITE_INTERFACE = 1 +IH_INTERFACE_TYPE = ctypes.c_uint32 # enum + +# values for enumeration 'IH_PERF_SEL' +IH_PERF_SEL__enumvalues = { + 0: 'IH_PERF_SEL_CYCLE', + 1: 'IH_PERF_SEL_IDLE', + 2: 'IH_PERF_SEL_INPUT_IDLE', + 3: 'IH_PERF_SEL_BUFFER_IDLE', + 4: 'IH_PERF_SEL_RB0_FULL', + 5: 'IH_PERF_SEL_RB0_OVERFLOW', + 6: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', + 7: 'IH_PERF_SEL_RB0_WPTR_WRAP', + 8: 'IH_PERF_SEL_RB0_RPTR_WRAP', + 9: 'IH_PERF_SEL_MC_WR_IDLE', + 10: 'IH_PERF_SEL_MC_WR_COUNT', + 11: 'IH_PERF_SEL_MC_WR_STALL', + 12: 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', + 13: 'IH_PERF_SEL_MC_WR_CLEAN_STALL', + 14: 'IH_PERF_SEL_BIF_LINE0_RISING', + 15: 'IH_PERF_SEL_BIF_LINE0_FALLING', + 16: 'IH_PERF_SEL_RB1_FULL', + 17: 'IH_PERF_SEL_RB1_OVERFLOW', + 18: 'IH_PERF_SEL_COOKIE_REC_ERROR', + 19: 'IH_PERF_SEL_RB1_WPTR_WRAP', + 20: 'IH_PERF_SEL_RB1_RPTR_WRAP', + 21: 'IH_PERF_SEL_RB2_FULL', + 22: 'IH_PERF_SEL_RB2_OVERFLOW', + 23: 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', + 24: 'IH_PERF_SEL_RB2_WPTR_WRAP', + 25: 'IH_PERF_SEL_RB2_RPTR_WRAP', + 26: 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', + 27: 'IH_PERF_SEL_SELF_IV_VALID', + 28: 'IH_PERF_SEL_BUFFER_FIFO_FULL', + 29: 'IH_PERF_SEL_RB0_FULL_VF0', + 30: 'IH_PERF_SEL_RB0_FULL_VF1', + 31: 'IH_PERF_SEL_RB0_FULL_VF2', + 32: 'IH_PERF_SEL_RB0_FULL_VF3', + 33: 'IH_PERF_SEL_RB0_FULL_VF4', + 34: 'IH_PERF_SEL_RB0_FULL_VF5', + 35: 'IH_PERF_SEL_RB0_FULL_VF6', + 36: 'IH_PERF_SEL_RB0_FULL_VF7', + 37: 'IH_PERF_SEL_RB0_FULL_VF8', + 38: 'IH_PERF_SEL_RB0_FULL_VF9', + 39: 'IH_PERF_SEL_RB0_FULL_VF10', + 40: 'IH_PERF_SEL_RB0_FULL_VF11', + 41: 'IH_PERF_SEL_RB0_FULL_VF12', + 42: 'IH_PERF_SEL_RB0_FULL_VF13', + 43: 'IH_PERF_SEL_RB0_FULL_VF14', + 44: 'IH_PERF_SEL_RB0_FULL_VF15', + 45: 'IH_PERF_SEL_RB0_OVERFLOW_VF0', + 46: 'IH_PERF_SEL_RB0_OVERFLOW_VF1', + 47: 'IH_PERF_SEL_RB0_OVERFLOW_VF2', + 48: 'IH_PERF_SEL_RB0_OVERFLOW_VF3', + 49: 'IH_PERF_SEL_RB0_OVERFLOW_VF4', + 50: 'IH_PERF_SEL_RB0_OVERFLOW_VF5', + 51: 'IH_PERF_SEL_RB0_OVERFLOW_VF6', + 52: 'IH_PERF_SEL_RB0_OVERFLOW_VF7', + 53: 'IH_PERF_SEL_RB0_OVERFLOW_VF8', + 54: 'IH_PERF_SEL_RB0_OVERFLOW_VF9', + 55: 'IH_PERF_SEL_RB0_OVERFLOW_VF10', + 56: 'IH_PERF_SEL_RB0_OVERFLOW_VF11', + 57: 'IH_PERF_SEL_RB0_OVERFLOW_VF12', + 58: 'IH_PERF_SEL_RB0_OVERFLOW_VF13', + 59: 'IH_PERF_SEL_RB0_OVERFLOW_VF14', + 60: 'IH_PERF_SEL_RB0_OVERFLOW_VF15', + 61: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', + 62: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', + 63: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', + 64: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', + 65: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', + 66: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', + 67: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', + 68: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', + 69: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', + 70: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', + 71: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', + 72: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', + 73: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', + 74: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', + 75: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', + 76: 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', + 77: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', + 78: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', + 79: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', + 80: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', + 81: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', + 82: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', + 83: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', + 84: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', + 85: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', + 86: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', + 87: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', + 88: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', + 89: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', + 90: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', + 91: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', + 92: 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', + 93: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', + 94: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', + 95: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', + 96: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', + 97: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', + 98: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', + 99: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', + 100: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', + 101: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', + 102: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', + 103: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', + 104: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', + 105: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', + 106: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', + 107: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', + 108: 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', + 109: 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', + 110: 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', + 111: 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', + 112: 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', + 113: 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', + 114: 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', + 115: 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', + 116: 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', + 117: 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', + 118: 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', + 119: 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', + 120: 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', + 121: 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', + 122: 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', + 123: 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', + 124: 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', + 125: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', + 126: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', + 127: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', + 128: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', + 129: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', + 130: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', + 131: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', + 132: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', + 133: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', + 134: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', + 135: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', + 136: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', + 137: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', + 138: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', + 139: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', + 140: 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', + 141: 'IH_PERF_SEL_CLIENT0_INT', + 142: 'IH_PERF_SEL_CLIENT1_INT', + 143: 'IH_PERF_SEL_CLIENT2_INT', + 144: 'IH_PERF_SEL_CLIENT3_INT', + 145: 'IH_PERF_SEL_CLIENT4_INT', + 146: 'IH_PERF_SEL_CLIENT5_INT', + 147: 'IH_PERF_SEL_CLIENT6_INT', + 148: 'IH_PERF_SEL_CLIENT7_INT', + 149: 'IH_PERF_SEL_CLIENT8_INT', + 150: 'IH_PERF_SEL_CLIENT9_INT', + 151: 'IH_PERF_SEL_CLIENT10_INT', + 152: 'IH_PERF_SEL_CLIENT11_INT', + 153: 'IH_PERF_SEL_CLIENT12_INT', + 154: 'IH_PERF_SEL_CLIENT13_INT', + 155: 'IH_PERF_SEL_CLIENT14_INT', + 156: 'IH_PERF_SEL_CLIENT15_INT', + 157: 'IH_PERF_SEL_CLIENT16_INT', + 158: 'IH_PERF_SEL_CLIENT17_INT', + 159: 'IH_PERF_SEL_CLIENT18_INT', + 160: 'IH_PERF_SEL_CLIENT19_INT', + 161: 'IH_PERF_SEL_CLIENT20_INT', + 162: 'IH_PERF_SEL_CLIENT21_INT', + 163: 'IH_PERF_SEL_CLIENT22_INT', + 164: 'IH_PERF_SEL_CLIENT23_INT', + 165: 'IH_PERF_SEL_CLIENT24_INT', + 166: 'IH_PERF_SEL_CLIENT25_INT', + 167: 'IH_PERF_SEL_CLIENT26_INT', + 168: 'IH_PERF_SEL_CLIENT27_INT', + 169: 'IH_PERF_SEL_CLIENT28_INT', + 170: 'IH_PERF_SEL_CLIENT29_INT', + 171: 'IH_PERF_SEL_CLIENT30_INT', + 172: 'IH_PERF_SEL_CLIENT31_INT', + 173: 'IH_PERF_SEL_RB1_FULL_VF0', + 174: 'IH_PERF_SEL_RB1_FULL_VF1', + 175: 'IH_PERF_SEL_RB1_FULL_VF2', + 176: 'IH_PERF_SEL_RB1_FULL_VF3', + 177: 'IH_PERF_SEL_RB1_FULL_VF4', + 178: 'IH_PERF_SEL_RB1_FULL_VF5', + 179: 'IH_PERF_SEL_RB1_FULL_VF6', + 180: 'IH_PERF_SEL_RB1_FULL_VF7', + 181: 'IH_PERF_SEL_RB1_FULL_VF8', + 182: 'IH_PERF_SEL_RB1_FULL_VF9', + 183: 'IH_PERF_SEL_RB1_FULL_VF10', + 184: 'IH_PERF_SEL_RB1_FULL_VF11', + 185: 'IH_PERF_SEL_RB1_FULL_VF12', + 186: 'IH_PERF_SEL_RB1_FULL_VF13', + 187: 'IH_PERF_SEL_RB1_FULL_VF14', + 188: 'IH_PERF_SEL_RB1_FULL_VF15', + 189: 'IH_PERF_SEL_RB1_OVERFLOW_VF0', + 190: 'IH_PERF_SEL_RB1_OVERFLOW_VF1', + 191: 'IH_PERF_SEL_RB1_OVERFLOW_VF2', + 192: 'IH_PERF_SEL_RB1_OVERFLOW_VF3', + 193: 'IH_PERF_SEL_RB1_OVERFLOW_VF4', + 194: 'IH_PERF_SEL_RB1_OVERFLOW_VF5', + 195: 'IH_PERF_SEL_RB1_OVERFLOW_VF6', + 196: 'IH_PERF_SEL_RB1_OVERFLOW_VF7', + 197: 'IH_PERF_SEL_RB1_OVERFLOW_VF8', + 198: 'IH_PERF_SEL_RB1_OVERFLOW_VF9', + 199: 'IH_PERF_SEL_RB1_OVERFLOW_VF10', + 200: 'IH_PERF_SEL_RB1_OVERFLOW_VF11', + 201: 'IH_PERF_SEL_RB1_OVERFLOW_VF12', + 202: 'IH_PERF_SEL_RB1_OVERFLOW_VF13', + 203: 'IH_PERF_SEL_RB1_OVERFLOW_VF14', + 204: 'IH_PERF_SEL_RB1_OVERFLOW_VF15', + 205: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', + 206: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', + 207: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', + 208: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', + 209: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', + 210: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', + 211: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', + 212: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', + 213: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', + 214: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', + 215: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', + 216: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', + 217: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', + 218: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', + 219: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', + 220: 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', + 221: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', + 222: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', + 223: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', + 224: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', + 225: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', + 226: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', + 227: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', + 228: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', + 229: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', + 230: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', + 231: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', + 232: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', + 233: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', + 234: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', + 235: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', + 236: 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', + 237: 'IH_PERF_SEL_RB2_FULL_VF0', + 238: 'IH_PERF_SEL_RB2_FULL_VF1', + 239: 'IH_PERF_SEL_RB2_FULL_VF2', + 240: 'IH_PERF_SEL_RB2_FULL_VF3', + 241: 'IH_PERF_SEL_RB2_FULL_VF4', + 242: 'IH_PERF_SEL_RB2_FULL_VF5', + 243: 'IH_PERF_SEL_RB2_FULL_VF6', + 244: 'IH_PERF_SEL_RB2_FULL_VF7', + 245: 'IH_PERF_SEL_RB2_FULL_VF8', + 246: 'IH_PERF_SEL_RB2_FULL_VF9', + 247: 'IH_PERF_SEL_RB2_FULL_VF10', + 248: 'IH_PERF_SEL_RB2_FULL_VF11', + 249: 'IH_PERF_SEL_RB2_FULL_VF12', + 250: 'IH_PERF_SEL_RB2_FULL_VF13', + 251: 'IH_PERF_SEL_RB2_FULL_VF14', + 252: 'IH_PERF_SEL_RB2_FULL_VF15', + 253: 'IH_PERF_SEL_RB2_OVERFLOW_VF0', + 254: 'IH_PERF_SEL_RB2_OVERFLOW_VF1', + 255: 'IH_PERF_SEL_RB2_OVERFLOW_VF2', + 256: 'IH_PERF_SEL_RB2_OVERFLOW_VF3', + 257: 'IH_PERF_SEL_RB2_OVERFLOW_VF4', + 258: 'IH_PERF_SEL_RB2_OVERFLOW_VF5', + 259: 'IH_PERF_SEL_RB2_OVERFLOW_VF6', + 260: 'IH_PERF_SEL_RB2_OVERFLOW_VF7', + 261: 'IH_PERF_SEL_RB2_OVERFLOW_VF8', + 262: 'IH_PERF_SEL_RB2_OVERFLOW_VF9', + 263: 'IH_PERF_SEL_RB2_OVERFLOW_VF10', + 264: 'IH_PERF_SEL_RB2_OVERFLOW_VF11', + 265: 'IH_PERF_SEL_RB2_OVERFLOW_VF12', + 266: 'IH_PERF_SEL_RB2_OVERFLOW_VF13', + 267: 'IH_PERF_SEL_RB2_OVERFLOW_VF14', + 268: 'IH_PERF_SEL_RB2_OVERFLOW_VF15', + 269: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', + 270: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', + 271: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', + 272: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', + 273: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', + 274: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', + 275: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', + 276: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', + 277: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', + 278: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', + 279: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', + 280: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', + 281: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', + 282: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', + 283: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', + 284: 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', + 285: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', + 286: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', + 287: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', + 288: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', + 289: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', + 290: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', + 291: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', + 292: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', + 293: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', + 294: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', + 295: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', + 296: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', + 297: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', + 298: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', + 299: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', + 300: 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', + 301: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', + 302: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', + 303: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', + 304: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', + 305: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', + 306: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', + 307: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', + 308: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', + 309: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', + 310: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', + 311: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', + 312: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', + 313: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', + 314: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', + 315: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', + 316: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', + 317: 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', + 318: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', + 319: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', + 320: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', + 321: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', + 322: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', + 323: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', + 324: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', + 325: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', + 326: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', + 327: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', + 328: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', + 329: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', + 330: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', + 331: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', + 332: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', + 333: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', + 334: 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', + 335: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', + 336: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', + 337: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', + 338: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', + 339: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', + 340: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', + 341: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', + 342: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', + 343: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', + 344: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', + 345: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', + 346: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', + 347: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', + 348: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', + 349: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', + 350: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', + 351: 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', + 352: 'IH_PERF_SEL_RB0_LOAD_RPTR', + 353: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', + 354: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', + 355: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', + 356: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', + 357: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', + 358: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', + 359: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', + 360: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', + 361: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', + 362: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', + 363: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', + 364: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', + 365: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', + 366: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', + 367: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', + 368: 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', + 369: 'IH_PERF_SEL_RB1_LOAD_RPTR', + 370: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', + 371: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', + 372: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', + 373: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', + 374: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', + 375: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', + 376: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', + 377: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', + 378: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', + 379: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', + 380: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', + 381: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', + 382: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', + 383: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', + 384: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', + 385: 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', + 386: 'IH_PERF_SEL_RB2_LOAD_RPTR', + 387: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', + 388: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', + 389: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', + 390: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', + 391: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', + 392: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', + 393: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', + 394: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', + 395: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', + 396: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', + 397: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', + 398: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', + 399: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', + 400: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', + 401: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', + 402: 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', +} +IH_PERF_SEL_CYCLE = 0 +IH_PERF_SEL_IDLE = 1 +IH_PERF_SEL_INPUT_IDLE = 2 +IH_PERF_SEL_BUFFER_IDLE = 3 +IH_PERF_SEL_RB0_FULL = 4 +IH_PERF_SEL_RB0_OVERFLOW = 5 +IH_PERF_SEL_RB0_WPTR_WRITEBACK = 6 +IH_PERF_SEL_RB0_WPTR_WRAP = 7 +IH_PERF_SEL_RB0_RPTR_WRAP = 8 +IH_PERF_SEL_MC_WR_IDLE = 9 +IH_PERF_SEL_MC_WR_COUNT = 10 +IH_PERF_SEL_MC_WR_STALL = 11 +IH_PERF_SEL_MC_WR_CLEAN_PENDING = 12 +IH_PERF_SEL_MC_WR_CLEAN_STALL = 13 +IH_PERF_SEL_BIF_LINE0_RISING = 14 +IH_PERF_SEL_BIF_LINE0_FALLING = 15 +IH_PERF_SEL_RB1_FULL = 16 +IH_PERF_SEL_RB1_OVERFLOW = 17 +IH_PERF_SEL_COOKIE_REC_ERROR = 18 +IH_PERF_SEL_RB1_WPTR_WRAP = 19 +IH_PERF_SEL_RB1_RPTR_WRAP = 20 +IH_PERF_SEL_RB2_FULL = 21 +IH_PERF_SEL_RB2_OVERFLOW = 22 +IH_PERF_SEL_CLIENT_CREDIT_ERROR = 23 +IH_PERF_SEL_RB2_WPTR_WRAP = 24 +IH_PERF_SEL_RB2_RPTR_WRAP = 25 +IH_PERF_SEL_STORM_CLIENT_INT_DROP = 26 +IH_PERF_SEL_SELF_IV_VALID = 27 +IH_PERF_SEL_BUFFER_FIFO_FULL = 28 +IH_PERF_SEL_RB0_FULL_VF0 = 29 +IH_PERF_SEL_RB0_FULL_VF1 = 30 +IH_PERF_SEL_RB0_FULL_VF2 = 31 +IH_PERF_SEL_RB0_FULL_VF3 = 32 +IH_PERF_SEL_RB0_FULL_VF4 = 33 +IH_PERF_SEL_RB0_FULL_VF5 = 34 +IH_PERF_SEL_RB0_FULL_VF6 = 35 +IH_PERF_SEL_RB0_FULL_VF7 = 36 +IH_PERF_SEL_RB0_FULL_VF8 = 37 +IH_PERF_SEL_RB0_FULL_VF9 = 38 +IH_PERF_SEL_RB0_FULL_VF10 = 39 +IH_PERF_SEL_RB0_FULL_VF11 = 40 +IH_PERF_SEL_RB0_FULL_VF12 = 41 +IH_PERF_SEL_RB0_FULL_VF13 = 42 +IH_PERF_SEL_RB0_FULL_VF14 = 43 +IH_PERF_SEL_RB0_FULL_VF15 = 44 +IH_PERF_SEL_RB0_OVERFLOW_VF0 = 45 +IH_PERF_SEL_RB0_OVERFLOW_VF1 = 46 +IH_PERF_SEL_RB0_OVERFLOW_VF2 = 47 +IH_PERF_SEL_RB0_OVERFLOW_VF3 = 48 +IH_PERF_SEL_RB0_OVERFLOW_VF4 = 49 +IH_PERF_SEL_RB0_OVERFLOW_VF5 = 50 +IH_PERF_SEL_RB0_OVERFLOW_VF6 = 51 +IH_PERF_SEL_RB0_OVERFLOW_VF7 = 52 +IH_PERF_SEL_RB0_OVERFLOW_VF8 = 53 +IH_PERF_SEL_RB0_OVERFLOW_VF9 = 54 +IH_PERF_SEL_RB0_OVERFLOW_VF10 = 55 +IH_PERF_SEL_RB0_OVERFLOW_VF11 = 56 +IH_PERF_SEL_RB0_OVERFLOW_VF12 = 57 +IH_PERF_SEL_RB0_OVERFLOW_VF13 = 58 +IH_PERF_SEL_RB0_OVERFLOW_VF14 = 59 +IH_PERF_SEL_RB0_OVERFLOW_VF15 = 60 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 61 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 62 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 63 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 64 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 65 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 66 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 67 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 68 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 69 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 70 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 71 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 72 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 73 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 74 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 75 +IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 76 +IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 77 +IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 78 +IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 79 +IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 80 +IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 81 +IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 82 +IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 83 +IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 84 +IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 85 +IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 86 +IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 87 +IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 88 +IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 89 +IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 90 +IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 91 +IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 92 +IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 93 +IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 94 +IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 95 +IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 96 +IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 97 +IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 98 +IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 99 +IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 100 +IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 101 +IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 102 +IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 103 +IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 104 +IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 105 +IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 106 +IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 107 +IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 108 +IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 109 +IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 110 +IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 111 +IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 112 +IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 113 +IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 114 +IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 115 +IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 116 +IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 117 +IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 118 +IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 119 +IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 120 +IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 121 +IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 122 +IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 123 +IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 124 +IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 125 +IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 126 +IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 127 +IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 128 +IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 129 +IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 130 +IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 131 +IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 132 +IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 133 +IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 134 +IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 135 +IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 136 +IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 137 +IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 138 +IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 139 +IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 140 +IH_PERF_SEL_CLIENT0_INT = 141 +IH_PERF_SEL_CLIENT1_INT = 142 +IH_PERF_SEL_CLIENT2_INT = 143 +IH_PERF_SEL_CLIENT3_INT = 144 +IH_PERF_SEL_CLIENT4_INT = 145 +IH_PERF_SEL_CLIENT5_INT = 146 +IH_PERF_SEL_CLIENT6_INT = 147 +IH_PERF_SEL_CLIENT7_INT = 148 +IH_PERF_SEL_CLIENT8_INT = 149 +IH_PERF_SEL_CLIENT9_INT = 150 +IH_PERF_SEL_CLIENT10_INT = 151 +IH_PERF_SEL_CLIENT11_INT = 152 +IH_PERF_SEL_CLIENT12_INT = 153 +IH_PERF_SEL_CLIENT13_INT = 154 +IH_PERF_SEL_CLIENT14_INT = 155 +IH_PERF_SEL_CLIENT15_INT = 156 +IH_PERF_SEL_CLIENT16_INT = 157 +IH_PERF_SEL_CLIENT17_INT = 158 +IH_PERF_SEL_CLIENT18_INT = 159 +IH_PERF_SEL_CLIENT19_INT = 160 +IH_PERF_SEL_CLIENT20_INT = 161 +IH_PERF_SEL_CLIENT21_INT = 162 +IH_PERF_SEL_CLIENT22_INT = 163 +IH_PERF_SEL_CLIENT23_INT = 164 +IH_PERF_SEL_CLIENT24_INT = 165 +IH_PERF_SEL_CLIENT25_INT = 166 +IH_PERF_SEL_CLIENT26_INT = 167 +IH_PERF_SEL_CLIENT27_INT = 168 +IH_PERF_SEL_CLIENT28_INT = 169 +IH_PERF_SEL_CLIENT29_INT = 170 +IH_PERF_SEL_CLIENT30_INT = 171 +IH_PERF_SEL_CLIENT31_INT = 172 +IH_PERF_SEL_RB1_FULL_VF0 = 173 +IH_PERF_SEL_RB1_FULL_VF1 = 174 +IH_PERF_SEL_RB1_FULL_VF2 = 175 +IH_PERF_SEL_RB1_FULL_VF3 = 176 +IH_PERF_SEL_RB1_FULL_VF4 = 177 +IH_PERF_SEL_RB1_FULL_VF5 = 178 +IH_PERF_SEL_RB1_FULL_VF6 = 179 +IH_PERF_SEL_RB1_FULL_VF7 = 180 +IH_PERF_SEL_RB1_FULL_VF8 = 181 +IH_PERF_SEL_RB1_FULL_VF9 = 182 +IH_PERF_SEL_RB1_FULL_VF10 = 183 +IH_PERF_SEL_RB1_FULL_VF11 = 184 +IH_PERF_SEL_RB1_FULL_VF12 = 185 +IH_PERF_SEL_RB1_FULL_VF13 = 186 +IH_PERF_SEL_RB1_FULL_VF14 = 187 +IH_PERF_SEL_RB1_FULL_VF15 = 188 +IH_PERF_SEL_RB1_OVERFLOW_VF0 = 189 +IH_PERF_SEL_RB1_OVERFLOW_VF1 = 190 +IH_PERF_SEL_RB1_OVERFLOW_VF2 = 191 +IH_PERF_SEL_RB1_OVERFLOW_VF3 = 192 +IH_PERF_SEL_RB1_OVERFLOW_VF4 = 193 +IH_PERF_SEL_RB1_OVERFLOW_VF5 = 194 +IH_PERF_SEL_RB1_OVERFLOW_VF6 = 195 +IH_PERF_SEL_RB1_OVERFLOW_VF7 = 196 +IH_PERF_SEL_RB1_OVERFLOW_VF8 = 197 +IH_PERF_SEL_RB1_OVERFLOW_VF9 = 198 +IH_PERF_SEL_RB1_OVERFLOW_VF10 = 199 +IH_PERF_SEL_RB1_OVERFLOW_VF11 = 200 +IH_PERF_SEL_RB1_OVERFLOW_VF12 = 201 +IH_PERF_SEL_RB1_OVERFLOW_VF13 = 202 +IH_PERF_SEL_RB1_OVERFLOW_VF14 = 203 +IH_PERF_SEL_RB1_OVERFLOW_VF15 = 204 +IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 205 +IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 206 +IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 207 +IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 208 +IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 209 +IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 210 +IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 211 +IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 212 +IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 213 +IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 214 +IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 215 +IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 216 +IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 217 +IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 218 +IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 219 +IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 220 +IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 221 +IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 222 +IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 223 +IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 224 +IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 225 +IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 226 +IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 227 +IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 228 +IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 229 +IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 230 +IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 231 +IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 232 +IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 233 +IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 234 +IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 235 +IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 236 +IH_PERF_SEL_RB2_FULL_VF0 = 237 +IH_PERF_SEL_RB2_FULL_VF1 = 238 +IH_PERF_SEL_RB2_FULL_VF2 = 239 +IH_PERF_SEL_RB2_FULL_VF3 = 240 +IH_PERF_SEL_RB2_FULL_VF4 = 241 +IH_PERF_SEL_RB2_FULL_VF5 = 242 +IH_PERF_SEL_RB2_FULL_VF6 = 243 +IH_PERF_SEL_RB2_FULL_VF7 = 244 +IH_PERF_SEL_RB2_FULL_VF8 = 245 +IH_PERF_SEL_RB2_FULL_VF9 = 246 +IH_PERF_SEL_RB2_FULL_VF10 = 247 +IH_PERF_SEL_RB2_FULL_VF11 = 248 +IH_PERF_SEL_RB2_FULL_VF12 = 249 +IH_PERF_SEL_RB2_FULL_VF13 = 250 +IH_PERF_SEL_RB2_FULL_VF14 = 251 +IH_PERF_SEL_RB2_FULL_VF15 = 252 +IH_PERF_SEL_RB2_OVERFLOW_VF0 = 253 +IH_PERF_SEL_RB2_OVERFLOW_VF1 = 254 +IH_PERF_SEL_RB2_OVERFLOW_VF2 = 255 +IH_PERF_SEL_RB2_OVERFLOW_VF3 = 256 +IH_PERF_SEL_RB2_OVERFLOW_VF4 = 257 +IH_PERF_SEL_RB2_OVERFLOW_VF5 = 258 +IH_PERF_SEL_RB2_OVERFLOW_VF6 = 259 +IH_PERF_SEL_RB2_OVERFLOW_VF7 = 260 +IH_PERF_SEL_RB2_OVERFLOW_VF8 = 261 +IH_PERF_SEL_RB2_OVERFLOW_VF9 = 262 +IH_PERF_SEL_RB2_OVERFLOW_VF10 = 263 +IH_PERF_SEL_RB2_OVERFLOW_VF11 = 264 +IH_PERF_SEL_RB2_OVERFLOW_VF12 = 265 +IH_PERF_SEL_RB2_OVERFLOW_VF13 = 266 +IH_PERF_SEL_RB2_OVERFLOW_VF14 = 267 +IH_PERF_SEL_RB2_OVERFLOW_VF15 = 268 +IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 269 +IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 270 +IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 271 +IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 272 +IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 273 +IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 274 +IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 275 +IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 276 +IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 277 +IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 278 +IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 279 +IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 280 +IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 281 +IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 282 +IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 283 +IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 284 +IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 285 +IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 286 +IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 287 +IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 288 +IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 289 +IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 290 +IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 291 +IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 292 +IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 293 +IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 294 +IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 295 +IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 296 +IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 297 +IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 298 +IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 299 +IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 300 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 301 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 302 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 303 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 304 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 305 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 306 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 307 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 308 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 309 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 310 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 311 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 312 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 313 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 314 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 315 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 316 +IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 317 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 318 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 319 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 320 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 321 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 322 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 323 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 324 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 325 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 326 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 327 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 328 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 329 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 330 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 331 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 332 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 333 +IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 334 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 335 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 336 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 337 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 338 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 339 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 340 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 341 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 342 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 343 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 344 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 345 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 346 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 347 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 348 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 349 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 350 +IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 351 +IH_PERF_SEL_RB0_LOAD_RPTR = 352 +IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 353 +IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 354 +IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 355 +IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 356 +IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 357 +IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 358 +IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 359 +IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 360 +IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 361 +IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 362 +IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 363 +IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 364 +IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 365 +IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 366 +IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 367 +IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 368 +IH_PERF_SEL_RB1_LOAD_RPTR = 369 +IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 370 +IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 371 +IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 372 +IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 373 +IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 374 +IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 375 +IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 376 +IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 377 +IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 378 +IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 379 +IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 380 +IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 381 +IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 382 +IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 383 +IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 384 +IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 385 +IH_PERF_SEL_RB2_LOAD_RPTR = 386 +IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 387 +IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 388 +IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 389 +IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 390 +IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 391 +IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 392 +IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 393 +IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 394 +IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 395 +IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 396 +IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 397 +IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 398 +IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 399 +IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 400 +IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 401 +IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 402 +IH_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'IH_RING_ID' +IH_RING_ID__enumvalues = { + 0: 'IH_RING_ID_INTERRUPT', + 1: 'IH_RING_ID_REQUEST', + 2: 'IH_RING_ID_TRANSLATION', + 3: 'IH_RING_ID_RESERVED', +} +IH_RING_ID_INTERRUPT = 0 +IH_RING_ID_REQUEST = 1 +IH_RING_ID_TRANSLATION = 2 +IH_RING_ID_RESERVED = 3 +IH_RING_ID = ctypes.c_uint32 # enum + +# values for enumeration 'IH_VF_RB_SELECT' +IH_VF_RB_SELECT__enumvalues = { + 0: 'IH_VF_RB_SELECT_CLIENT_FCN_ID', + 1: 'IH_VF_RB_SELECT_IH_FCN_ID', + 2: 'IH_VF_RB_SELECT_PF', + 3: 'IH_VF_RB_SELECT_RESERVED', +} +IH_VF_RB_SELECT_CLIENT_FCN_ID = 0 +IH_VF_RB_SELECT_IH_FCN_ID = 1 +IH_VF_RB_SELECT_PF = 2 +IH_VF_RB_SELECT_RESERVED = 3 +IH_VF_RB_SELECT = ctypes.c_uint32 # enum + +# values for enumeration 'SEM_PERF_SEL' +SEM_PERF_SEL__enumvalues = { + 0: 'SEM_PERF_SEL_CYCLE', + 1: 'SEM_PERF_SEL_IDLE', + 2: 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', + 3: 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', + 4: 'SEM_PERF_SEL_SDMA2_REQ_SIGNAL', + 5: 'SEM_PERF_SEL_SDMA3_REQ_SIGNAL', + 6: 'SEM_PERF_SEL_UVD_REQ_SIGNAL', + 7: 'SEM_PERF_SEL_UVD1_REQ_SIGNAL', + 8: 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', + 9: 'SEM_PERF_SEL_ACP_REQ_SIGNAL', + 10: 'SEM_PERF_SEL_ISP_REQ_SIGNAL', + 11: 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', + 12: 'SEM_PERF_SEL_VP8_REQ_SIGNAL', + 13: 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', + 14: 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', + 15: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', + 16: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', + 17: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', + 18: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', + 19: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', + 20: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', + 21: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', + 22: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', + 23: 'SEM_PERF_SEL_SDMA0_REQ_WAIT', + 24: 'SEM_PERF_SEL_SDMA1_REQ_WAIT', + 25: 'SEM_PERF_SEL_SDMA2_REQ_WAIT', + 26: 'SEM_PERF_SEL_SDMA3_REQ_WAIT', + 27: 'SEM_PERF_SEL_UVD_REQ_WAIT', + 28: 'SEM_PERF_SEL_UVD1_REQ_WAIT', + 29: 'SEM_PERF_SEL_VCE0_REQ_WAIT', + 30: 'SEM_PERF_SEL_ACP_REQ_WAIT', + 31: 'SEM_PERF_SEL_ISP_REQ_WAIT', + 32: 'SEM_PERF_SEL_VCE1_REQ_WAIT', + 33: 'SEM_PERF_SEL_VP8_REQ_WAIT', + 34: 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', + 35: 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', + 36: 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', + 37: 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', + 38: 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', + 39: 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', + 40: 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', + 41: 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', + 42: 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', + 43: 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', + 44: 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', + 45: 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', + 46: 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', + 47: 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', + 48: 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', + 49: 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', + 50: 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', + 51: 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', + 52: 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', + 53: 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', + 54: 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', + 55: 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', + 56: 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', + 57: 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', + 58: 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', + 59: 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', + 60: 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', + 61: 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', + 62: 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', + 63: 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', + 64: 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', + 65: 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', + 66: 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', + 67: 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', + 68: 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', + 69: 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', + 70: 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', + 71: 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', + 72: 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', + 73: 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', + 74: 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', + 75: 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', + 76: 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', + 77: 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', + 78: 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', + 79: 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', + 80: 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', + 81: 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', + 82: 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', + 83: 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', + 84: 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', + 85: 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', + 86: 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', + 87: 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', + 88: 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', + 89: 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', + 90: 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', + 91: 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', + 92: 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', + 93: 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', + 94: 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', + 95: 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', + 96: 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', + 97: 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', + 98: 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', + 99: 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', + 100: 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', + 101: 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', + 102: 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', + 103: 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', + 104: 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', + 105: 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', + 106: 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', + 107: 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', + 108: 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', + 109: 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', + 110: 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', + 111: 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', + 112: 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', + 113: 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', + 114: 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', + 115: 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', + 116: 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', + 117: 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', + 118: 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', + 119: 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', + 120: 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', + 121: 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', + 122: 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', + 123: 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', + 124: 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', + 125: 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', + 126: 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', + 127: 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', + 128: 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', + 129: 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', + 130: 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', + 131: 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', + 132: 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', + 133: 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', + 134: 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', + 135: 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', + 136: 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', + 137: 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', + 138: 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', + 139: 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', + 140: 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', + 141: 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', + 142: 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', + 143: 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', + 144: 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', + 145: 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', + 146: 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', + 147: 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', + 148: 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', + 149: 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', + 150: 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', + 151: 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', + 152: 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', + 153: 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', + 154: 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', + 155: 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', + 156: 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', + 157: 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', + 158: 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', + 159: 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', + 160: 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', + 161: 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', + 162: 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', + 163: 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', + 164: 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', + 165: 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', + 166: 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', + 167: 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', + 168: 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', + 169: 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', + 170: 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', + 171: 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', + 172: 'SEM_PERF_SEL_MC_RD_REQ', + 173: 'SEM_PERF_SEL_MC_RD_RET', + 174: 'SEM_PERF_SEL_MC_WR_REQ', + 175: 'SEM_PERF_SEL_MC_WR_RET', + 176: 'SEM_PERF_SEL_ATC_REQ', + 177: 'SEM_PERF_SEL_ATC_RET', + 178: 'SEM_PERF_SEL_ATC_XNACK', + 179: 'SEM_PERF_SEL_ATC_INVALIDATION', + 180: 'SEM_PERF_SEL_ATC_VM_INVALIDATION', +} +SEM_PERF_SEL_CYCLE = 0 +SEM_PERF_SEL_IDLE = 1 +SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 2 +SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 3 +SEM_PERF_SEL_SDMA2_REQ_SIGNAL = 4 +SEM_PERF_SEL_SDMA3_REQ_SIGNAL = 5 +SEM_PERF_SEL_UVD_REQ_SIGNAL = 6 +SEM_PERF_SEL_UVD1_REQ_SIGNAL = 7 +SEM_PERF_SEL_VCE0_REQ_SIGNAL = 8 +SEM_PERF_SEL_ACP_REQ_SIGNAL = 9 +SEM_PERF_SEL_ISP_REQ_SIGNAL = 10 +SEM_PERF_SEL_VCE1_REQ_SIGNAL = 11 +SEM_PERF_SEL_VP8_REQ_SIGNAL = 12 +SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 13 +SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 14 +SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 15 +SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 16 +SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 17 +SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 18 +SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 19 +SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 20 +SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 21 +SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 22 +SEM_PERF_SEL_SDMA0_REQ_WAIT = 23 +SEM_PERF_SEL_SDMA1_REQ_WAIT = 24 +SEM_PERF_SEL_SDMA2_REQ_WAIT = 25 +SEM_PERF_SEL_SDMA3_REQ_WAIT = 26 +SEM_PERF_SEL_UVD_REQ_WAIT = 27 +SEM_PERF_SEL_UVD1_REQ_WAIT = 28 +SEM_PERF_SEL_VCE0_REQ_WAIT = 29 +SEM_PERF_SEL_ACP_REQ_WAIT = 30 +SEM_PERF_SEL_ISP_REQ_WAIT = 31 +SEM_PERF_SEL_VCE1_REQ_WAIT = 32 +SEM_PERF_SEL_VP8_REQ_WAIT = 33 +SEM_PERF_SEL_CPG_E0_REQ_WAIT = 34 +SEM_PERF_SEL_CPG_E1_REQ_WAIT = 35 +SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 36 +SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 37 +SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 38 +SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 39 +SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 40 +SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 41 +SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 42 +SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 43 +SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 44 +SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 45 +SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 46 +SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 47 +SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 48 +SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 49 +SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 50 +SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 51 +SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 52 +SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 53 +SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 54 +SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 55 +SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 56 +SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 57 +SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 58 +SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 59 +SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 60 +SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 61 +SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 62 +SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 63 +SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 64 +SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 65 +SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 66 +SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 67 +SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 68 +SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 69 +SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 70 +SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 71 +SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 72 +SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 73 +SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 74 +SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 75 +SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 76 +SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 77 +SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 78 +SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 79 +SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 80 +SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 81 +SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 82 +SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 83 +SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 84 +SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 85 +SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 86 +SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 87 +SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 88 +SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 89 +SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 90 +SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 91 +SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 92 +SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 93 +SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 94 +SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 95 +SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 96 +SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 97 +SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 98 +SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 99 +SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 100 +SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 101 +SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 102 +SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 103 +SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 104 +SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 105 +SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 106 +SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 107 +SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 108 +SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 109 +SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 110 +SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 111 +SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 112 +SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 113 +SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 114 +SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 115 +SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 116 +SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 117 +SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 118 +SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 119 +SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 120 +SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 121 +SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 122 +SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 123 +SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 124 +SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 125 +SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 126 +SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 127 +SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 128 +SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 129 +SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 130 +SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 131 +SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 132 +SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 133 +SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 134 +SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 135 +SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 136 +SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 137 +SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 138 +SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 139 +SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 140 +SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 141 +SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 142 +SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 143 +SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 144 +SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 145 +SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 146 +SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 147 +SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 148 +SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 149 +SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 150 +SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 151 +SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 152 +SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 153 +SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 154 +SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 155 +SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 156 +SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 157 +SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 158 +SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 159 +SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 160 +SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 161 +SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 162 +SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 163 +SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 164 +SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 165 +SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 166 +SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 167 +SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 168 +SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 169 +SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 170 +SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 171 +SEM_PERF_SEL_MC_RD_REQ = 172 +SEM_PERF_SEL_MC_RD_RET = 173 +SEM_PERF_SEL_MC_WR_REQ = 174 +SEM_PERF_SEL_MC_WR_RET = 175 +SEM_PERF_SEL_ATC_REQ = 176 +SEM_PERF_SEL_ATC_RET = 177 +SEM_PERF_SEL_ATC_XNACK = 178 +SEM_PERF_SEL_ATC_INVALIDATION = 179 +SEM_PERF_SEL_ATC_VM_INVALIDATION = 180 +SEM_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'LSDMA_PERF_SEL' +LSDMA_PERF_SEL__enumvalues = { + 0: 'LSDMA_PERF_SEL_CYCLE', + 1: 'LSDMA_PERF_SEL_IDLE', + 2: 'LSDMA_PERF_SEL_REG_IDLE', + 3: 'LSDMA_PERF_SEL_RB_EMPTY', + 4: 'LSDMA_PERF_SEL_RB_FULL', + 5: 'LSDMA_PERF_SEL_RB_WPTR_WRAP', + 6: 'LSDMA_PERF_SEL_RB_RPTR_WRAP', + 7: 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', + 8: 'LSDMA_PERF_SEL_RB_RPTR_WB', + 9: 'LSDMA_PERF_SEL_RB_CMD_IDLE', + 10: 'LSDMA_PERF_SEL_RB_CMD_FULL', + 11: 'LSDMA_PERF_SEL_IB_CMD_IDLE', + 12: 'LSDMA_PERF_SEL_IB_CMD_FULL', + 13: 'LSDMA_PERF_SEL_EX_IDLE', + 14: 'LSDMA_PERF_SEL_SRBM_REG_SEND', + 15: 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 16: 'LSDMA_PERF_SEL_MC_WR_IDLE', + 17: 'LSDMA_PERF_SEL_MC_WR_COUNT', + 18: 'LSDMA_PERF_SEL_MC_RD_IDLE', + 19: 'LSDMA_PERF_SEL_MC_RD_COUNT', + 20: 'LSDMA_PERF_SEL_MC_RD_RET_STALL', + 21: 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 24: 'LSDMA_PERF_SEL_SEM_IDLE', + 25: 'LSDMA_PERF_SEL_SEM_REQ_STALL', + 26: 'LSDMA_PERF_SEL_SEM_REQ_COUNT', + 27: 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 28: 'LSDMA_PERF_SEL_SEM_RESP_FAIL', + 29: 'LSDMA_PERF_SEL_SEM_RESP_PASS', + 30: 'LSDMA_PERF_SEL_INT_IDLE', + 31: 'LSDMA_PERF_SEL_INT_REQ_STALL', + 32: 'LSDMA_PERF_SEL_INT_REQ_COUNT', + 33: 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', + 34: 'LSDMA_PERF_SEL_INT_RESP_RETRY', + 35: 'LSDMA_PERF_SEL_NUM_PACKET', + 37: 'LSDMA_PERF_SEL_CE_WREQ_IDLE', + 38: 'LSDMA_PERF_SEL_CE_WR_IDLE', + 39: 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', + 40: 'LSDMA_PERF_SEL_CE_RREQ_IDLE', + 41: 'LSDMA_PERF_SEL_CE_OUT_IDLE', + 42: 'LSDMA_PERF_SEL_CE_IN_IDLE', + 43: 'LSDMA_PERF_SEL_CE_DST_IDLE', + 46: 'LSDMA_PERF_SEL_CE_AFIFO_FULL', + 49: 'LSDMA_PERF_SEL_CE_INFO_FULL', + 50: 'LSDMA_PERF_SEL_CE_INFO1_FULL', + 51: 'LSDMA_PERF_SEL_CE_RD_STALL', + 52: 'LSDMA_PERF_SEL_CE_WR_STALL', + 53: 'LSDMA_PERF_SEL_GFX_SELECT', + 54: 'LSDMA_PERF_SEL_RLC0_SELECT', + 55: 'LSDMA_PERF_SEL_RLC1_SELECT', + 56: 'LSDMA_PERF_SEL_PAGE_SELECT', + 57: 'LSDMA_PERF_SEL_CTX_CHANGE', + 58: 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', + 59: 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 60: 'LSDMA_PERF_SEL_DOORBELL', + 61: 'LSDMA_PERF_SEL_RD_BA_RTR', + 62: 'LSDMA_PERF_SEL_WR_BA_RTR', + 63: 'LSDMA_PERF_SEL_F32_L1_WR_VLD', + 64: 'LSDMA_PERF_SEL_CE_L1_WR_VLD', + 65: 'LSDMA_PERF_SEL_CE_L1_STALL', + 66: 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', + 67: 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', + 68: 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', + 69: 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', + 70: 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', + 71: 'LSDMA_PERF_SEL_ATCL2_RET_ACK', + 72: 'LSDMA_PERF_SEL_ATCL2_FREE', + 73: 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', + 74: 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', + 75: 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', + 76: 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', + 77: 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', + 78: 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', + 79: 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', + 80: 'LSDMA_PERF_SEL_L1_WRL2_IDLE', + 81: 'LSDMA_PERF_SEL_L1_RDL2_IDLE', + 82: 'LSDMA_PERF_SEL_L1_WRMC_IDLE', + 83: 'LSDMA_PERF_SEL_L1_RDMC_IDLE', + 84: 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', + 85: 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', + 86: 'LSDMA_PERF_SEL_L1_WR_INV_EN', + 87: 'LSDMA_PERF_SEL_L1_RD_INV_EN', + 88: 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', + 89: 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', + 90: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', + 91: 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', + 92: 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', + 93: 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', + 94: 'LSDMA_PERF_SEL_L1_INV_MIDDLE', + 95: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', + 96: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', + 97: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', + 98: 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', + 99: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', + 100: 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', + 101: 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', + 102: 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', + 103: 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', + 104: 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', + 105: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', + 106: 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', + 107: 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', + 108: 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', + 109: 'LSDMA_PERF_SEL_CMD_OP_MATCH', + 110: 'LSDMA_PERF_SEL_CMD_OP_START', + 111: 'LSDMA_PERF_SEL_CMD_OP_END', + 112: 'LSDMA_PERF_SEL_CE_BUSY', + 113: 'LSDMA_PERF_SEL_CE_BUSY_START', + 114: 'LSDMA_PERF_SEL_CE_BUSY_END', + 115: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 116: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 117: 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 118: 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', + 119: 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', + 120: 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', + 121: 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', + 122: 'LSDMA_PERF_SEL_DRAM_ECC', + 123: 'LSDMA_PERF_SEL_NACK_GEN_ERR', +} +LSDMA_PERF_SEL_CYCLE = 0 +LSDMA_PERF_SEL_IDLE = 1 +LSDMA_PERF_SEL_REG_IDLE = 2 +LSDMA_PERF_SEL_RB_EMPTY = 3 +LSDMA_PERF_SEL_RB_FULL = 4 +LSDMA_PERF_SEL_RB_WPTR_WRAP = 5 +LSDMA_PERF_SEL_RB_RPTR_WRAP = 6 +LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 7 +LSDMA_PERF_SEL_RB_RPTR_WB = 8 +LSDMA_PERF_SEL_RB_CMD_IDLE = 9 +LSDMA_PERF_SEL_RB_CMD_FULL = 10 +LSDMA_PERF_SEL_IB_CMD_IDLE = 11 +LSDMA_PERF_SEL_IB_CMD_FULL = 12 +LSDMA_PERF_SEL_EX_IDLE = 13 +LSDMA_PERF_SEL_SRBM_REG_SEND = 14 +LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 15 +LSDMA_PERF_SEL_MC_WR_IDLE = 16 +LSDMA_PERF_SEL_MC_WR_COUNT = 17 +LSDMA_PERF_SEL_MC_RD_IDLE = 18 +LSDMA_PERF_SEL_MC_RD_COUNT = 19 +LSDMA_PERF_SEL_MC_RD_RET_STALL = 20 +LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 21 +LSDMA_PERF_SEL_SEM_IDLE = 24 +LSDMA_PERF_SEL_SEM_REQ_STALL = 25 +LSDMA_PERF_SEL_SEM_REQ_COUNT = 26 +LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 27 +LSDMA_PERF_SEL_SEM_RESP_FAIL = 28 +LSDMA_PERF_SEL_SEM_RESP_PASS = 29 +LSDMA_PERF_SEL_INT_IDLE = 30 +LSDMA_PERF_SEL_INT_REQ_STALL = 31 +LSDMA_PERF_SEL_INT_REQ_COUNT = 32 +LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 33 +LSDMA_PERF_SEL_INT_RESP_RETRY = 34 +LSDMA_PERF_SEL_NUM_PACKET = 35 +LSDMA_PERF_SEL_CE_WREQ_IDLE = 37 +LSDMA_PERF_SEL_CE_WR_IDLE = 38 +LSDMA_PERF_SEL_CE_SPLIT_IDLE = 39 +LSDMA_PERF_SEL_CE_RREQ_IDLE = 40 +LSDMA_PERF_SEL_CE_OUT_IDLE = 41 +LSDMA_PERF_SEL_CE_IN_IDLE = 42 +LSDMA_PERF_SEL_CE_DST_IDLE = 43 +LSDMA_PERF_SEL_CE_AFIFO_FULL = 46 +LSDMA_PERF_SEL_CE_INFO_FULL = 49 +LSDMA_PERF_SEL_CE_INFO1_FULL = 50 +LSDMA_PERF_SEL_CE_RD_STALL = 51 +LSDMA_PERF_SEL_CE_WR_STALL = 52 +LSDMA_PERF_SEL_GFX_SELECT = 53 +LSDMA_PERF_SEL_RLC0_SELECT = 54 +LSDMA_PERF_SEL_RLC1_SELECT = 55 +LSDMA_PERF_SEL_PAGE_SELECT = 56 +LSDMA_PERF_SEL_CTX_CHANGE = 57 +LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 58 +LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 59 +LSDMA_PERF_SEL_DOORBELL = 60 +LSDMA_PERF_SEL_RD_BA_RTR = 61 +LSDMA_PERF_SEL_WR_BA_RTR = 62 +LSDMA_PERF_SEL_F32_L1_WR_VLD = 63 +LSDMA_PERF_SEL_CE_L1_WR_VLD = 64 +LSDMA_PERF_SEL_CE_L1_STALL = 65 +LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 66 +LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 67 +LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 68 +LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 69 +LSDMA_PERF_SEL_ATCL2_RET_XNACK = 70 +LSDMA_PERF_SEL_ATCL2_RET_ACK = 71 +LSDMA_PERF_SEL_ATCL2_FREE = 72 +LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 73 +LSDMA_PERF_SEL_DMA_L1_WR_SEND = 74 +LSDMA_PERF_SEL_DMA_L1_RD_SEND = 75 +LSDMA_PERF_SEL_DMA_MC_WR_SEND = 76 +LSDMA_PERF_SEL_DMA_MC_RD_SEND = 77 +LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 78 +LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 79 +LSDMA_PERF_SEL_L1_WRL2_IDLE = 80 +LSDMA_PERF_SEL_L1_RDL2_IDLE = 81 +LSDMA_PERF_SEL_L1_WRMC_IDLE = 82 +LSDMA_PERF_SEL_L1_RDMC_IDLE = 83 +LSDMA_PERF_SEL_L1_WR_INV_IDLE = 84 +LSDMA_PERF_SEL_L1_RD_INV_IDLE = 85 +LSDMA_PERF_SEL_L1_WR_INV_EN = 86 +LSDMA_PERF_SEL_L1_RD_INV_EN = 87 +LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 88 +LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 89 +LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 90 +LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 91 +LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 92 +LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 93 +LSDMA_PERF_SEL_L1_INV_MIDDLE = 94 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 95 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 96 +LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 97 +LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 98 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 99 +LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 100 +LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 101 +LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 102 +LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 103 +LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 104 +LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 105 +LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 106 +LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 107 +LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 108 +LSDMA_PERF_SEL_CMD_OP_MATCH = 109 +LSDMA_PERF_SEL_CMD_OP_START = 110 +LSDMA_PERF_SEL_CMD_OP_END = 111 +LSDMA_PERF_SEL_CE_BUSY = 112 +LSDMA_PERF_SEL_CE_BUSY_START = 113 +LSDMA_PERF_SEL_CE_BUSY_END = 114 +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 115 +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 116 +LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 117 +LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 118 +LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 119 +LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 120 +LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 121 +LSDMA_PERF_SEL_DRAM_ECC = 122 +LSDMA_PERF_SEL_NACK_GEN_ERR = 123 +LSDMA_PERF_SEL = ctypes.c_uint32 # enum + +# values for enumeration 'EFC_SURFACE_PIXEL_FORMAT' +EFC_SURFACE_PIXEL_FORMAT__enumvalues = { + 1: 'EFC_ARGB1555', + 2: 'EFC_RGBA5551', + 3: 'EFC_RGB565', + 4: 'EFC_BGR565', + 5: 'EFC_ARGB4444', + 6: 'EFC_RGBA4444', + 8: 'EFC_ARGB8888', + 9: 'EFC_RGBA8888', + 10: 'EFC_ARGB2101010', + 11: 'EFC_RGBA1010102', + 12: 'EFC_AYCrCb8888', + 13: 'EFC_YCrCbA8888', + 14: 'EFC_ACrYCb8888', + 15: 'EFC_CrYCbA8888', + 16: 'EFC_ARGB16161616_10MSB', + 17: 'EFC_RGBA16161616_10MSB', + 18: 'EFC_ARGB16161616_10LSB', + 19: 'EFC_RGBA16161616_10LSB', + 20: 'EFC_ARGB16161616_12MSB', + 21: 'EFC_RGBA16161616_12MSB', + 22: 'EFC_ARGB16161616_12LSB', + 23: 'EFC_RGBA16161616_12LSB', + 24: 'EFC_ARGB16161616_FLOAT', + 25: 'EFC_RGBA16161616_FLOAT', + 26: 'EFC_ARGB16161616_UNORM', + 27: 'EFC_RGBA16161616_UNORM', + 28: 'EFC_ARGB16161616_SNORM', + 29: 'EFC_RGBA16161616_SNORM', + 32: 'EFC_AYCrCb16161616_10MSB', + 33: 'EFC_AYCrCb16161616_10LSB', + 34: 'EFC_YCrCbA16161616_10MSB', + 35: 'EFC_YCrCbA16161616_10LSB', + 36: 'EFC_ACrYCb16161616_10MSB', + 37: 'EFC_ACrYCb16161616_10LSB', + 38: 'EFC_CrYCbA16161616_10MSB', + 39: 'EFC_CrYCbA16161616_10LSB', + 40: 'EFC_AYCrCb16161616_12MSB', + 41: 'EFC_AYCrCb16161616_12LSB', + 42: 'EFC_YCrCbA16161616_12MSB', + 43: 'EFC_YCrCbA16161616_12LSB', + 44: 'EFC_ACrYCb16161616_12MSB', + 45: 'EFC_ACrYCb16161616_12LSB', + 46: 'EFC_CrYCbA16161616_12MSB', + 47: 'EFC_CrYCbA16161616_12LSB', + 64: 'EFC_Y8_CrCb88_420_PLANAR', + 65: 'EFC_Y8_CbCr88_420_PLANAR', + 66: 'EFC_Y10_CrCb1010_420_PLANAR', + 67: 'EFC_Y10_CbCr1010_420_PLANAR', + 68: 'EFC_Y12_CrCb1212_420_PLANAR', + 69: 'EFC_Y12_CbCr1212_420_PLANAR', + 72: 'EFC_YCrYCb8888_422_PACKED', + 73: 'EFC_YCbYCr8888_422_PACKED', + 74: 'EFC_CrYCbY8888_422_PACKED', + 75: 'EFC_CbYCrY8888_422_PACKED', + 76: 'EFC_YCrYCb10101010_422_PACKED', + 77: 'EFC_YCbYCr10101010_422_PACKED', + 78: 'EFC_CrYCbY10101010_422_PACKED', + 79: 'EFC_CbYCrY10101010_422_PACKED', + 80: 'EFC_YCrYCb12121212_422_PACKED', + 81: 'EFC_YCbYCr12121212_422_PACKED', + 82: 'EFC_CrYCbY12121212_422_PACKED', + 83: 'EFC_CbYCrY12121212_422_PACKED', + 112: 'EFC_RGB111110_FIX', + 113: 'EFC_BGR101111_FIX', + 114: 'EFC_ACrYCb2101010', + 115: 'EFC_CrYCbA1010102', + 118: 'EFC_RGB111110_FLOAT', + 119: 'EFC_BGR101111_FLOAT', + 120: 'EFC_MONO_8', + 121: 'EFC_MONO_10MSB', + 122: 'EFC_MONO_10LSB', + 123: 'EFC_MONO_12MSB', + 124: 'EFC_MONO_12LSB', + 125: 'EFC_MONO_16', +} +EFC_ARGB1555 = 1 +EFC_RGBA5551 = 2 +EFC_RGB565 = 3 +EFC_BGR565 = 4 +EFC_ARGB4444 = 5 +EFC_RGBA4444 = 6 +EFC_ARGB8888 = 8 +EFC_RGBA8888 = 9 +EFC_ARGB2101010 = 10 +EFC_RGBA1010102 = 11 +EFC_AYCrCb8888 = 12 +EFC_YCrCbA8888 = 13 +EFC_ACrYCb8888 = 14 +EFC_CrYCbA8888 = 15 +EFC_ARGB16161616_10MSB = 16 +EFC_RGBA16161616_10MSB = 17 +EFC_ARGB16161616_10LSB = 18 +EFC_RGBA16161616_10LSB = 19 +EFC_ARGB16161616_12MSB = 20 +EFC_RGBA16161616_12MSB = 21 +EFC_ARGB16161616_12LSB = 22 +EFC_RGBA16161616_12LSB = 23 +EFC_ARGB16161616_FLOAT = 24 +EFC_RGBA16161616_FLOAT = 25 +EFC_ARGB16161616_UNORM = 26 +EFC_RGBA16161616_UNORM = 27 +EFC_ARGB16161616_SNORM = 28 +EFC_RGBA16161616_SNORM = 29 +EFC_AYCrCb16161616_10MSB = 32 +EFC_AYCrCb16161616_10LSB = 33 +EFC_YCrCbA16161616_10MSB = 34 +EFC_YCrCbA16161616_10LSB = 35 +EFC_ACrYCb16161616_10MSB = 36 +EFC_ACrYCb16161616_10LSB = 37 +EFC_CrYCbA16161616_10MSB = 38 +EFC_CrYCbA16161616_10LSB = 39 +EFC_AYCrCb16161616_12MSB = 40 +EFC_AYCrCb16161616_12LSB = 41 +EFC_YCrCbA16161616_12MSB = 42 +EFC_YCrCbA16161616_12LSB = 43 +EFC_ACrYCb16161616_12MSB = 44 +EFC_ACrYCb16161616_12LSB = 45 +EFC_CrYCbA16161616_12MSB = 46 +EFC_CrYCbA16161616_12LSB = 47 +EFC_Y8_CrCb88_420_PLANAR = 64 +EFC_Y8_CbCr88_420_PLANAR = 65 +EFC_Y10_CrCb1010_420_PLANAR = 66 +EFC_Y10_CbCr1010_420_PLANAR = 67 +EFC_Y12_CrCb1212_420_PLANAR = 68 +EFC_Y12_CbCr1212_420_PLANAR = 69 +EFC_YCrYCb8888_422_PACKED = 72 +EFC_YCbYCr8888_422_PACKED = 73 +EFC_CrYCbY8888_422_PACKED = 74 +EFC_CbYCrY8888_422_PACKED = 75 +EFC_YCrYCb10101010_422_PACKED = 76 +EFC_YCbYCr10101010_422_PACKED = 77 +EFC_CrYCbY10101010_422_PACKED = 78 +EFC_CbYCrY10101010_422_PACKED = 79 +EFC_YCrYCb12121212_422_PACKED = 80 +EFC_YCbYCr12121212_422_PACKED = 81 +EFC_CrYCbY12121212_422_PACKED = 82 +EFC_CbYCrY12121212_422_PACKED = 83 +EFC_RGB111110_FIX = 112 +EFC_BGR101111_FIX = 113 +EFC_ACrYCb2101010 = 114 +EFC_CrYCbA1010102 = 115 +EFC_RGB111110_FLOAT = 118 +EFC_BGR101111_FLOAT = 119 +EFC_MONO_8 = 120 +EFC_MONO_10MSB = 121 +EFC_MONO_10LSB = 122 +EFC_MONO_12MSB = 123 +EFC_MONO_12LSB = 124 +EFC_MONO_16 = 125 +EFC_SURFACE_PIXEL_FORMAT = ctypes.c_uint32 # enum +__SDMA_V6_0_0_PKT_OPEN_H_ = True # macro +SDMA_OP_NOP = 0 # macro +SDMA_OP_WRITE = 2 # macro +SDMA_OP_INDIRECT = 4 # macro +SDMA_OP_SEM = 7 # macro +SDMA_OP_COND_EXE = 9 # macro +SDMA_OP_PTEPDE = 12 # macro +SDMA_OP_SRBM_WRITE = 14 # macro +SDMA_OP_PRE_EXE = 15 # macro +SDMA_OP_GPUVM_INV = 16 # macro +SDMA_OP_GCR_REQ = 17 # macro +SDMA_OP_DUMMY_TRAP = 32 # macro +SDMA_SUBOP_TIMESTAMP_SET = 0 # macro +SDMA_SUBOP_TIMESTAMP_GET = 1 # macro +SDMA_SUBOP_COPY_LINEAR_SUB_WIND = 4 # macro +SDMA_SUBOP_COPY_TILED = 1 # macro +SDMA_SUBOP_COPY_TILED_SUB_WIND = 5 # macro +SDMA_SUBOP_COPY_T2T_SUB_WIND = 6 # macro +SDMA_SUBOP_COPY_SOA = 3 # macro +SDMA_SUBOP_COPY_DIRTY_PAGE = 7 # macro +SDMA_SUBOP_COPY_LINEAR_PHY = 8 # macro +SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE = 36 # macro +SDMA_SUBOP_COPY_LINEAR_BC = 16 # macro +SDMA_SUBOP_COPY_TILED_BC = 17 # macro +SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC = 20 # macro +SDMA_SUBOP_COPY_TILED_SUB_WIND_BC = 21 # macro +SDMA_SUBOP_COPY_T2T_SUB_WIND_BC = 22 # macro +SDMA_SUBOP_WRITE_LINEAR = 0 # macro +SDMA_SUBOP_WRITE_TILED = 1 # macro +SDMA_SUBOP_WRITE_TILED_BC = 17 # macro +SDMA_SUBOP_PTEPDE_GEN = 0 # macro +SDMA_SUBOP_PTEPDE_COPY = 1 # macro +SDMA_SUBOP_PTEPDE_RMW = 2 # macro +SDMA_SUBOP_PTEPDE_COPY_BACKWARDS = 3 # macro +SDMA_SUBOP_MEM_INCR = 1 # macro +SDMA_SUBOP_DATA_FILL_MULTI = 1 # macro +SDMA_SUBOP_POLL_REG_WRITE_MEM = 1 # macro +SDMA_SUBOP_POLL_DBIT_WRITE_MEM = 2 # macro +SDMA_SUBOP_POLL_MEM_VERIFY = 3 # macro +SDMA_SUBOP_VM_INVALIDATION = 4 # macro +HEADER_AGENT_DISPATCH = 4 # macro +HEADER_BARRIER = 5 # macro +SDMA_OP_AQL_COPY = 0 # macro +SDMA_OP_AQL_BARRIER_OR = 0 # macro +SDMA_GCR_RANGE_IS_PA = (1<<18) # macro +def SDMA_GCR_SEQ(x): # macro + return (((x)&0x3)<<16) +SDMA_GCR_GL2_WB = (1<<15) # macro +SDMA_GCR_GL2_INV = (1<<14) # macro +SDMA_GCR_GL2_DISCARD = (1<<13) # macro +def SDMA_GCR_GL2_RANGE(x): # macro + return (((x)&0x3)<<11) +SDMA_GCR_GL2_US = (1<<10) # macro +SDMA_GCR_GL1_INV = (1<<9) # macro +SDMA_GCR_GLV_INV = (1<<8) # macro +SDMA_GCR_GLK_INV = (1<<7) # macro +SDMA_GCR_GLK_WB = (1<<6) # macro +SDMA_GCR_GLM_INV = (1<<5) # macro +SDMA_GCR_GLM_WB = (1<<4) # macro +def SDMA_GCR_GL1_RANGE(x): # macro + return (((x)&0x3)<<2) +def SDMA_GCR_GLI_INV(x): # macro + return (((x)&0x3)<<0) +SDMA_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift = 19 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift = 25 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x): # macro + return (((x)&0x00000001)<<25) +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift = 27 # macro +def SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_LINEAR_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_LINEAR_COUNT_count_mask = 0x3FFFFFFF # macro +SDMA_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro + return (((x)&0x3FFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift = 18 # macro +def SDMA_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<18) +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro +def SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<26) +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift = 19 # macro +def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift = 27 # macro +def SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift = 19 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset = 0 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift = 31 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask = 0x00000007 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift = 3 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x): # macro + return (((x)&0x00000007)<<3) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift = 6 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x): # macro + return (((x)&0x00000003)<<6) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift = 8 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_LLC(x): # macro + return (((x)&0x00000001)<<8) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask = 0x00000007 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift = 11 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x): # macro + return (((x)&0x00000007)<<11) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask = 0x00000003 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift = 14 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x): # macro + return (((x)&0x00000003)<<14) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift = 16 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_LLC(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift = 17 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<17) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift = 19 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift = 20 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x): # macro + return (((x)&0x00000001)<<20) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift = 22 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x): # macro + return (((x)&0x00000001)<<22) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift = 23 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x): # macro + return (((x)&0x00000001)<<23) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift = 28 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift = 30 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x): # macro + return (((x)&0x00000001)<<30) +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset = 2 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask = 0x00000001 # macro +SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift = 31 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset = 0 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift = 19 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask = 0x003FFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset = 1 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask = 0x000000FF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift = 24 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_ADDR_PAIR_NUM(x): # macro + return (((x)&0x000000FF)<<24) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask = 0x00000007 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift = 3 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x): # macro + return (((x)&0x00000007)<<3) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask = 0x00000003 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift = 6 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x): # macro + return (((x)&0x00000003)<<6) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift = 8 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LLC(x): # macro + return (((x)&0x00000001)<<8) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask = 0x00000007 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift = 11 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x): # macro + return (((x)&0x00000007)<<11) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask = 0x00000003 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift = 14 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x): # macro + return (((x)&0x00000003)<<14) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift = 16 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_LLC(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift = 17 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<17) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift = 19 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift = 20 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x): # macro + return (((x)&0x00000001)<<20) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift = 21 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x): # macro + return (((x)&0x00000001)<<21) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift = 22 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x): # macro + return (((x)&0x00000001)<<22) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift = 23 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x): # macro + return (((x)&0x00000001)<<23) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift = 27 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift = 28 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift = 30 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x): # macro + return (((x)&0x00000001)<<30) +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset = 2 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask = 0x00000001 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift = 31 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift = 19 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset = 0 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask = 0x00000001 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift = 27 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset = 1 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask = 0x3FFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x): # macro + return (((x)&0x3FFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset = 2 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift = 8 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x): # macro + return (((x)&0x00000003)<<8) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset = 2 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift = 10 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<10) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset = 2 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift = 16 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset = 2 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift = 18 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<18) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset = 2 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset = 2 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<26) +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 3 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 4 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset = 5 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset = 6 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset = 7 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset = 8 # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift = 19 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask = 0x00000007 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift = 29 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x): # macro + return (((x)&0x00000007)<<29) +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask = 0x00001FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift = 13 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x): # macro + return (((x)&0x0007FFFF)<<13) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset = 5 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset = 8 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset = 8 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset = 9 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask = 0x00001FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset = 9 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift = 13 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x): # macro + return (((x)&0x0007FFFF)<<13) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset = 10 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset = 11 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset = 11 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask = 0x00001FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift = 18 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<18) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift = 26 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<26) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift = 19 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_SRC_X(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_SRC_Y(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset = 5 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_SRC_Z(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset = 6 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_SRC_PITCH(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset = 7 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_SRC_SLICE_PITCH_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset = 8 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask = 0x0000FFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_SRC_SLICE_PITCH_47_32(x): # macro + return (((x)&0x0000FFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset = 9 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset = 10 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset = 11 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_DST_X(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_DST_Y(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset = 13 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_DST_Z(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset = 14 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_DST_PITCH(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset = 15 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_DST_SLICE_PITCH_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset = 16 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask = 0x0000FFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SLICE_PITCH_47_32(x): # macro + return (((x)&0x0000FFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset = 16 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset = 16 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift = 18 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_POLICY(x): # macro + return (((x)&0x00000007)<<18) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset = 16 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset = 16 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift = 26 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_POLICY(x): # macro + return (((x)&0x00000007)<<26) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset = 17 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_RECT_X(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset = 18 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_RECT_Y(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset = 19 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_RECT_Z(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset = 0 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask = 0x00000007 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift = 29 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x): # macro + return (((x)&0x00000007)<<29) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset = 3 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset = 4 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift = 13 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x): # macro + return (((x)&0x00003FFF)<<13) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset = 5 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask = 0x0FFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset = 6 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset = 7 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset = 8 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset = 8 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset = 9 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset = 9 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift = 13 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x): # macro + return (((x)&0x00003FFF)<<13) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset = 10 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask = 0x0FFFFFFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset = 11 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset = 11 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift = 19 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset = 12 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask = 0x00000001 # macro +SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift = 27 # macro +def SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_TILED_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_TILED_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_TILED_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_TILED_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_TILED_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_TILED_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_TILED_HEADER_cpv_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_HEADER_cpv_shift = 19 # macro +def SDMA_PKT_COPY_TILED_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_TILED_HEADER_detile_offset = 0 # macro +SDMA_PKT_COPY_TILED_HEADER_detile_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_HEADER_detile_shift = 31 # macro +def SDMA_PKT_COPY_TILED_HEADER_DETILE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_DW_3_width_offset = 3 # macro +SDMA_PKT_COPY_TILED_DW_3_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_DW_3_width_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_3_WIDTH(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_DW_4_height_offset = 4 # macro +SDMA_PKT_COPY_TILED_DW_4_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_DW_4_height_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_DW_4_depth_offset = 4 # macro +SDMA_PKT_COPY_TILED_DW_4_depth_mask = 0x00001FFF # macro +SDMA_PKT_COPY_TILED_DW_4_depth_shift = 16 # macro +def SDMA_PKT_COPY_TILED_DW_4_DEPTH(x): # macro + return (((x)&0x00001FFF)<<16) +SDMA_PKT_COPY_TILED_DW_5_element_size_offset = 5 # macro +SDMA_PKT_COPY_TILED_DW_5_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_DW_5_element_size_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset = 5 # macro +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_TILED_DW_5_dimension_offset = 5 # macro +SDMA_PKT_COPY_TILED_DW_5_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_DW_5_dimension_shift = 9 # macro +def SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_TILED_DW_5_mip_max_offset = 5 # macro +SDMA_PKT_COPY_TILED_DW_5_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_TILED_DW_5_mip_max_shift = 16 # macro +def SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_PKT_COPY_TILED_DW_6_x_offset = 6 # macro +SDMA_PKT_COPY_TILED_DW_6_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_DW_6_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_6_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_DW_6_y_offset = 6 # macro +SDMA_PKT_COPY_TILED_DW_6_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_DW_6_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_DW_6_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_DW_7_z_offset = 7 # macro +SDMA_PKT_COPY_TILED_DW_7_z_mask = 0x00001FFF # macro +SDMA_PKT_COPY_TILED_DW_7_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_DW_7_Z(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset = 7 # macro +SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset = 7 # macro +SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift = 18 # macro +def SDMA_PKT_COPY_TILED_DW_7_LINEAR_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<18) +SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset = 7 # macro +SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift = 24 # macro +def SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset = 7 # macro +SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift = 26 # macro +def SDMA_PKT_COPY_TILED_DW_7_TILE_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<26) +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset = 10 # macro +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift = 0 # macro +def SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_COUNT_count_offset = 12 # macro +SDMA_PKT_COPY_TILED_COUNT_count_mask = 0x3FFFFFFF # macro +SDMA_PKT_COPY_TILED_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_TILED_COUNT_COUNT(x): # macro + return (((x)&0x3FFFFFFF)<<0) +SDMA_PKT_COPY_TILED_BC_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_BC_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_BC_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_TILED_BC_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset = 0 # macro +SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift = 31 # macro +def SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_BC_DW_3_width_offset = 3 # macro +SDMA_PKT_COPY_TILED_BC_DW_3_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_BC_DW_3_width_shift = 0 # macro +def SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_BC_DW_4_height_offset = 4 # macro +SDMA_PKT_COPY_TILED_BC_DW_4_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_BC_DW_4_height_shift = 0 # macro +def SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset = 4 # macro +SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift = 16 # macro +def SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset = 5 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift = 0 # macro +def SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset = 5 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro +SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift = 3 # macro +def SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x): # macro + return (((x)&0x0000000F)<<3) +SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset = 5 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift = 8 # macro +def SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x): # macro + return (((x)&0x00000007)<<8) +SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro +def SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro + return (((x)&0x00000007)<<11) +SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset = 5 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift = 15 # macro +def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x): # macro + return (((x)&0x00000003)<<15) +SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset = 5 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift = 18 # macro +def SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x): # macro + return (((x)&0x00000003)<<18) +SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset = 5 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift = 21 # macro +def SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x): # macro + return (((x)&0x00000003)<<21) +SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset = 5 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift = 24 # macro +def SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset = 5 # macro +SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro +SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift = 26 # macro +def SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x): # macro + return (((x)&0x0000001F)<<26) +SDMA_PKT_COPY_TILED_BC_DW_6_x_offset = 6 # macro +SDMA_PKT_COPY_TILED_BC_DW_6_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_BC_DW_6_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_BC_DW_6_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_BC_DW_6_y_offset = 6 # macro +SDMA_PKT_COPY_TILED_BC_DW_6_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_BC_DW_6_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_BC_DW_6_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_BC_DW_7_z_offset = 7 # macro +SDMA_PKT_COPY_TILED_BC_DW_7_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_BC_DW_7_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_BC_DW_7_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset = 7 # macro +SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset = 7 # macro +SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift = 24 # macro +def SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 8 # macro +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 9 # macro +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset = 10 # macro +SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift = 0 # macro +def SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 11 # macro +SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_BC_COUNT_count_offset = 12 # macro +SDMA_PKT_COPY_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro +SDMA_PKT_COPY_TILED_BC_COUNT_count_shift = 2 # macro +def SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x): # macro + return (((x)&0x000FFFFF)<<2) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift = 19 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift = 26 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x): # macro + return (((x)&0x00000001)<<26) +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset = 0 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask = 0x00000001 # macro +SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift = 27 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x): # macro + return (((x)&0x00000001)<<27) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset = 1 # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset = 2 # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset = 3 # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset = 4 # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset = 5 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset = 6 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset = 6 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask = 0x00001FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x): # macro + return (((x)&0x00001FFF)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset = 7 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset = 7 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset = 7 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift = 9 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset = 7 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset = 8 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset = 8 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset = 9 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask = 0x00001FFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset = 10 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift = 8 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x): # macro + return (((x)&0x00000003)<<8) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset = 10 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift = 10 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<10) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset = 10 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset = 10 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift = 18 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<18) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset = 10 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift = 24 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset = 10 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift = 26 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<26) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset = 11 # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset = 12 # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset = 13 # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask = 0x0007FFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset = 14 # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset = 15 # macro +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask = 0x3FFFFFFF # macro +SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x): # macro + return (((x)&0x3FFFFFFF)<<0) +SDMA_PKT_COPY_T2T_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_T2T_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_T2T_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_T2T_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_T2T_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_T2T_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_T2T_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_T2T_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_T2T_HEADER_dcc_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_dcc_mask = 0x00000001 # macro +SDMA_PKT_COPY_T2T_HEADER_dcc_shift = 19 # macro +def SDMA_PKT_COPY_T2T_HEADER_DCC(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_T2T_HEADER_cpv_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_COPY_T2T_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_COPY_T2T_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset = 0 # macro +SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask = 0x00000001 # macro +SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift = 31 # macro +def SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_DW_3_src_x_offset = 3 # macro +SDMA_PKT_COPY_T2T_DW_3_src_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_3_src_x_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_3_SRC_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_3_src_y_offset = 3 # macro +SDMA_PKT_COPY_T2T_DW_3_src_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_3_src_y_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_4_src_z_offset = 4 # macro +SDMA_PKT_COPY_T2T_DW_4_src_z_mask = 0x00001FFF # macro +SDMA_PKT_COPY_T2T_DW_4_src_z_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_COPY_T2T_DW_4_src_width_offset = 4 # macro +SDMA_PKT_COPY_T2T_DW_4_src_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_4_src_width_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_5_src_height_offset = 5 # macro +SDMA_PKT_COPY_T2T_DW_5_src_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_5_src_height_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_5_src_depth_offset = 5 # macro +SDMA_PKT_COPY_T2T_DW_5_src_depth_mask = 0x00001FFF # macro +SDMA_PKT_COPY_T2T_DW_5_src_depth_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x): # macro + return (((x)&0x00001FFF)<<16) +SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift = 9 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset = 6 # macro +SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask = 0x0000000F # macro +SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift = 20 # macro +def SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_DW_9_dst_x_offset = 9 # macro +SDMA_PKT_COPY_T2T_DW_9_dst_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_9_dst_x_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_9_DST_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_9_dst_y_offset = 9 # macro +SDMA_PKT_COPY_T2T_DW_9_dst_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_9_dst_y_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_9_DST_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_10_dst_z_offset = 10 # macro +SDMA_PKT_COPY_T2T_DW_10_dst_z_mask = 0x00001FFF # macro +SDMA_PKT_COPY_T2T_DW_10_dst_z_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_10_DST_Z(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_COPY_T2T_DW_10_dst_width_offset = 10 # macro +SDMA_PKT_COPY_T2T_DW_10_dst_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_10_dst_width_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_11_dst_height_offset = 11 # macro +SDMA_PKT_COPY_T2T_DW_11_dst_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_11_dst_height_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset = 11 # macro +SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask = 0x00001FFF # macro +SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x): # macro + return (((x)&0x00001FFF)<<16) +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift = 9 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset = 12 # macro +SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask = 0x0000000F # macro +SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift = 20 # macro +def SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_COPY_T2T_DW_13_rect_x_offset = 13 # macro +SDMA_PKT_COPY_T2T_DW_13_rect_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_13_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_13_RECT_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_DW_13_rect_y_offset = 13 # macro +SDMA_PKT_COPY_T2T_DW_13_rect_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_DW_13_rect_y_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_DW_14_rect_z_offset = 14 # macro +SDMA_PKT_COPY_T2T_DW_14_rect_z_mask = 0x00001FFF # macro +SDMA_PKT_COPY_T2T_DW_14_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset = 14 # macro +SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_T2T_DW_14_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset = 14 # macro +SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift = 18 # macro +def SDMA_PKT_COPY_T2T_DW_14_DST_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<18) +SDMA_PKT_COPY_T2T_DW_14_src_sw_offset = 14 # macro +SDMA_PKT_COPY_T2T_DW_14_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_DW_14_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset = 14 # macro +SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift = 26 # macro +def SDMA_PKT_COPY_T2T_DW_14_SRC_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<26) +SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset = 15 # macro +SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset = 16 # macro +SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset = 17 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask = 0x0000007F # macro +SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift = 0 # macro +def SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x): # macro + return (((x)&0x0000007F)<<0) +SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset = 17 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift = 7 # macro +def SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro + return (((x)&0x00000001)<<7) +SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset = 17 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift = 8 # macro +def SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro + return (((x)&0x00000001)<<8) +SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset = 17 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift = 9 # macro +def SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x): # macro + return (((x)&0x00000007)<<9) +SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset = 17 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift = 12 # macro +def SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x): # macro + return (((x)&0x00000003)<<12) +SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset = 17 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask = 0x00000001 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift = 14 # macro +def SDMA_PKT_COPY_T2T_META_CONFIG_META_LLC(x): # macro + return (((x)&0x00000001)<<14) +SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset = 17 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift = 24 # macro +def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset = 17 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift = 26 # macro +def SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro + return (((x)&0x00000003)<<26) +SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset = 17 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift = 28 # macro +def SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset = 17 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift = 29 # macro +def SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x): # macro + return (((x)&0x00000001)<<29) +SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset = 17 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask = 0x00000001 # macro +SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift = 31 # macro +def SDMA_PKT_COPY_T2T_META_CONFIG_PIPE_ALIGNED(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_T2T_BC_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_T2T_BC_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_T2T_BC_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset = 3 # macro +SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset = 3 # macro +SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift = 16 # macro +def SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset = 4 # macro +SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset = 4 # macro +SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift = 16 # macro +def SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset = 5 # macro +SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset = 5 # macro +SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift = 16 # macro +def SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset = 6 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset = 6 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask = 0x0000000F # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift = 3 # macro +def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x): # macro + return (((x)&0x0000000F)<<3) +SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset = 6 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift = 8 # macro +def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x): # macro + return (((x)&0x00000007)<<8) +SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset = 6 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift = 11 # macro +def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x): # macro + return (((x)&0x00000007)<<11) +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset = 6 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift = 15 # macro +def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x): # macro + return (((x)&0x00000003)<<15) +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset = 6 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift = 18 # macro +def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x): # macro + return (((x)&0x00000003)<<18) +SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset = 6 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift = 21 # macro +def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x): # macro + return (((x)&0x00000003)<<21) +SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset = 6 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift = 24 # macro +def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset = 6 # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask = 0x0000001F # macro +SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift = 26 # macro +def SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x): # macro + return (((x)&0x0000001F)<<26) +SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset = 7 # macro +SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset = 8 # macro +SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset = 9 # macro +SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset = 9 # macro +SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift = 16 # macro +def SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset = 10 # macro +SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset = 10 # macro +SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift = 16 # macro +def SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset = 11 # macro +SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset = 11 # macro +SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask = 0x00000FFF # macro +SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift = 16 # macro +def SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x): # macro + return (((x)&0x00000FFF)<<16) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset = 12 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset = 12 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask = 0x0000000F # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift = 3 # macro +def SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x): # macro + return (((x)&0x0000000F)<<3) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset = 12 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift = 8 # macro +def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x): # macro + return (((x)&0x00000007)<<8) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset = 12 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift = 11 # macro +def SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x): # macro + return (((x)&0x00000007)<<11) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset = 12 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift = 15 # macro +def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x): # macro + return (((x)&0x00000003)<<15) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset = 12 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift = 18 # macro +def SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x): # macro + return (((x)&0x00000003)<<18) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset = 12 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift = 21 # macro +def SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x): # macro + return (((x)&0x00000003)<<21) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset = 12 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift = 24 # macro +def SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset = 12 # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask = 0x0000001F # macro +SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift = 26 # macro +def SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x): # macro + return (((x)&0x0000001F)<<26) +SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset = 13 # macro +SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset = 13 # macro +SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift = 16 # macro +def SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset = 14 # macro +SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset = 14 # macro +SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift = 16 # macro +def SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset = 14 # macro +SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift = 24 # macro +def SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift = 19 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift = 31 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset = 3 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset = 3 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset = 4 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask = 0x00001FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset = 4 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset = 5 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset = 5 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask = 0x00001FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x): # macro + return (((x)&0x00001FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift = 3 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift = 9 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask = 0x0000000F # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask = 0x0000000F # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift = 20 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x): # macro + return (((x)&0x0000000F)<<20) +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset = 9 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset = 9 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset = 10 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask = 0x00001FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset = 10 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset = 11 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset = 12 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset = 12 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask = 0x00001FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift = 18 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<18) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift = 24 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift = 26 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<26) +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset = 14 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset = 15 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset = 16 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask = 0x0000007F # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x): # macro + return (((x)&0x0000007F)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset = 16 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift = 7 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x): # macro + return (((x)&0x00000001)<<7) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset = 16 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift = 8 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x): # macro + return (((x)&0x00000001)<<8) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset = 16 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift = 9 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x): # macro + return (((x)&0x00000007)<<9) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset = 16 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift = 12 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x): # macro + return (((x)&0x00000003)<<12) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset = 16 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift = 14 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_LLC(x): # macro + return (((x)&0x00000001)<<14) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset = 16 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift = 24 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset = 16 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift = 26 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x): # macro + return (((x)&0x00000003)<<26) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset = 16 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift = 28 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset = 16 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift = 29 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x): # macro + return (((x)&0x00000001)<<29) +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset = 16 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift = 31 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_PIPE_ALIGNED(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset = 0 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask = 0x00000001 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift = 31 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset = 3 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset = 3 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset = 4 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset = 4 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset = 5 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset = 5 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask = 0x0000000F # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift = 3 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x): # macro + return (((x)&0x0000000F)<<3) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift = 8 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x): # macro + return (((x)&0x00000007)<<8) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask = 0x00000007 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift = 11 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x): # macro + return (((x)&0x00000007)<<11) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift = 15 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x): # macro + return (((x)&0x00000003)<<15) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift = 18 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x): # macro + return (((x)&0x00000003)<<18) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift = 21 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x): # macro + return (((x)&0x00000003)<<21) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift = 24 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset = 6 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask = 0x0000001F # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift = 26 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x): # macro + return (((x)&0x0000001F)<<26) +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset = 7 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset = 8 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset = 9 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset = 9 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset = 10 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset = 10 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset = 11 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask = 0x0FFFFFFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset = 12 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset = 12 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask = 0x00003FFF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask = 0x000007FF # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift = 0 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset = 13 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift = 24 # macro +def SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_STRUCT_HEADER_op_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_STRUCT_HEADER_op_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_COPY_STRUCT_HEADER_detile_offset = 0 # macro +SDMA_PKT_COPY_STRUCT_HEADER_detile_mask = 0x00000001 # macro +SDMA_PKT_COPY_STRUCT_HEADER_detile_shift = 31 # macro +def SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset = 1 # macro +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset = 2 # macro +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset = 3 # macro +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_COUNT_count_offset = 4 # macro +SDMA_PKT_COPY_STRUCT_COUNT_count_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_COUNT_count_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_DW_5_stride_offset = 5 # macro +SDMA_PKT_COPY_STRUCT_DW_5_stride_mask = 0x000007FF # macro +SDMA_PKT_COPY_STRUCT_DW_5_stride_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset = 5 # macro +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift = 16 # macro +def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset = 5 # macro +SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift = 18 # macro +def SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<18) +SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset = 5 # macro +SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask = 0x00000003 # macro +SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift = 24 # macro +def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset = 5 # macro +SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift = 26 # macro +def SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<26) +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset = 6 # macro +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset = 7 # macro +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift = 0 # macro +def SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_UNTILED_HEADER_op_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_UNTILED_HEADER_op_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset = 0 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_WRITE_UNTILED_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_UNTILED_DW_3_count_offset = 3 # macro +SDMA_PKT_WRITE_UNTILED_DW_3_count_mask = 0x000FFFFF # macro +SDMA_PKT_WRITE_UNTILED_DW_3_count_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset = 3 # macro +SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask = 0x00000003 # macro +SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift = 24 # macro +def SDMA_PKT_WRITE_UNTILED_DW_3_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset = 3 # macro +SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift = 26 # macro +def SDMA_PKT_WRITE_UNTILED_DW_3_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<26) +SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset = 4 # macro +SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift = 0 # macro +def SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_TILED_HEADER_op_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_TILED_HEADER_op_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask = 0x00000001 # macro +SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_WRITE_TILED_HEADER_tmz_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_WRITE_TILED_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_WRITE_TILED_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_WRITE_TILED_HEADER_cpv_offset = 0 # macro +SDMA_PKT_WRITE_TILED_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_WRITE_TILED_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_WRITE_TILED_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_TILED_DW_3_width_offset = 3 # macro +SDMA_PKT_WRITE_TILED_DW_3_width_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_DW_3_width_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_WRITE_TILED_DW_4_height_offset = 4 # macro +SDMA_PKT_WRITE_TILED_DW_4_height_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_DW_4_height_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_WRITE_TILED_DW_4_depth_offset = 4 # macro +SDMA_PKT_WRITE_TILED_DW_4_depth_mask = 0x00001FFF # macro +SDMA_PKT_WRITE_TILED_DW_4_depth_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x): # macro + return (((x)&0x00001FFF)<<16) +SDMA_PKT_WRITE_TILED_DW_5_element_size_offset = 5 # macro +SDMA_PKT_WRITE_TILED_DW_5_element_size_mask = 0x00000007 # macro +SDMA_PKT_WRITE_TILED_DW_5_element_size_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset = 5 # macro +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask = 0x0000001F # macro +SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift = 3 # macro +def SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x): # macro + return (((x)&0x0000001F)<<3) +SDMA_PKT_WRITE_TILED_DW_5_dimension_offset = 5 # macro +SDMA_PKT_WRITE_TILED_DW_5_dimension_mask = 0x00000003 # macro +SDMA_PKT_WRITE_TILED_DW_5_dimension_shift = 9 # macro +def SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x): # macro + return (((x)&0x00000003)<<9) +SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset = 5 # macro +SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask = 0x0000000F # macro +SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_PKT_WRITE_TILED_DW_6_x_offset = 6 # macro +SDMA_PKT_WRITE_TILED_DW_6_x_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_DW_6_x_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_6_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_WRITE_TILED_DW_6_y_offset = 6 # macro +SDMA_PKT_WRITE_TILED_DW_6_y_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_DW_6_y_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_DW_6_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_WRITE_TILED_DW_7_z_offset = 7 # macro +SDMA_PKT_WRITE_TILED_DW_7_z_mask = 0x00001FFF # macro +SDMA_PKT_WRITE_TILED_DW_7_z_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DW_7_Z(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_WRITE_TILED_DW_7_sw_offset = 7 # macro +SDMA_PKT_WRITE_TILED_DW_7_sw_mask = 0x00000003 # macro +SDMA_PKT_WRITE_TILED_DW_7_sw_shift = 24 # macro +def SDMA_PKT_WRITE_TILED_DW_7_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset = 7 # macro +SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift = 26 # macro +def SDMA_PKT_WRITE_TILED_DW_7_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<26) +SDMA_PKT_WRITE_TILED_COUNT_count_offset = 8 # macro +SDMA_PKT_WRITE_TILED_COUNT_count_mask = 0x000FFFFF # macro +SDMA_PKT_WRITE_TILED_COUNT_count_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_COUNT_COUNT(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_WRITE_TILED_DATA0_data0_offset = 9 # macro +SDMA_PKT_WRITE_TILED_DATA0_data0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_TILED_DATA0_data0_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_DATA0_DATA0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset = 0 # macro +SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset = 3 # macro +SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset = 4 # macro +SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset = 4 # macro +SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask = 0x000007FF # macro +SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x): # macro + return (((x)&0x000007FF)<<16) +SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset = 5 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask = 0x00000007 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset = 5 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask = 0x0000000F # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift = 3 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x): # macro + return (((x)&0x0000000F)<<3) +SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset = 5 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask = 0x00000007 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift = 8 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x): # macro + return (((x)&0x00000007)<<8) +SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset = 5 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask = 0x00000007 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift = 11 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x): # macro + return (((x)&0x00000007)<<11) +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset = 5 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask = 0x00000003 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift = 15 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x): # macro + return (((x)&0x00000003)<<15) +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset = 5 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask = 0x00000003 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift = 18 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x): # macro + return (((x)&0x00000003)<<18) +SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset = 5 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask = 0x00000003 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift = 21 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x): # macro + return (((x)&0x00000003)<<21) +SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset = 5 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask = 0x00000003 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift = 24 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset = 5 # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask = 0x0000001F # macro +SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift = 26 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x): # macro + return (((x)&0x0000001F)<<26) +SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset = 6 # macro +SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_6_X(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset = 6 # macro +SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask = 0x00003FFF # macro +SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift = 16 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset = 7 # macro +SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask = 0x000007FF # macro +SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x): # macro + return (((x)&0x000007FF)<<0) +SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset = 7 # macro +SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask = 0x00000003 # macro +SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift = 24 # macro +def SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset = 8 # macro +SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask = 0x000FFFFF # macro +SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift = 2 # macro +def SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x): # macro + return (((x)&0x000FFFFF)<<2) +SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset = 9 # macro +SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift = 0 # macro +def SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_HEADER_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_HEADER_op_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_PTEPDE_COPY_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_PTEPDE_COPY_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift = 31 # macro +def SDMA_PKT_PTEPDE_COPY_HEADER_PTEPDE_OP(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset = 5 # macro +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset = 6 # macro +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_COUNT_count_offset = 7 # macro +SDMA_PKT_PTEPDE_COPY_COUNT_count_mask = 0x0007FFFF # macro +SDMA_PKT_PTEPDE_COPY_COUNT_count_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset = 7 # macro +SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift = 22 # macro +def SDMA_PKT_PTEPDE_COPY_COUNT_DST_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<22) +SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset = 7 # macro +SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift = 29 # macro +def SDMA_PKT_PTEPDE_COPY_COUNT_SRC_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<29) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask = 0x00000003 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift = 28 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x): # macro + return (((x)&0x00000003)<<28) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift = 30 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x): # macro + return (((x)&0x00000001)<<30) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset = 0 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift = 31 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset = 1 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset = 2 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset = 5 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset = 5 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift = 8 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset = 6 # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask = 0x0001FFFF # macro +SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift = 0 # macro +def SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x): # macro + return (((x)&0x0001FFFF)<<0) +SDMA_PKT_PTEPDE_RMW_HEADER_op_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_RMW_HEADER_op_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask = 0x00000007 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift = 16 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x): # macro + return (((x)&0x00000007)<<16) +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift = 19 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift = 20 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x): # macro + return (((x)&0x00000001)<<20) +SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift = 22 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x): # macro + return (((x)&0x00000001)<<22) +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift = 23 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x): # macro + return (((x)&0x00000001)<<23) +SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask = 0x00000003 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift = 24 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift = 26 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_LLC_POLICY(x): # macro + return (((x)&0x00000001)<<26) +SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset = 0 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_PTEPDE_RMW_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset = 3 # macro +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset = 4 # macro +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset = 5 # macro +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset = 6 # macro +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset = 7 # macro +SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask = 0xFFFFFFFF # macro +SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift = 0 # macro +def SDMA_PKT_PTEPDE_RMW_COUNT_NUM_OF_PTE(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_REGISTER_RMW_HEADER_op_offset = 0 # macro +SDMA_PKT_REGISTER_RMW_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_REGISTER_RMW_HEADER_op_shift = 0 # macro +def SDMA_PKT_REGISTER_RMW_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_REGISTER_RMW_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_REGISTER_RMW_ADDR_addr_offset = 1 # macro +SDMA_PKT_REGISTER_RMW_ADDR_addr_mask = 0x000FFFFF # macro +SDMA_PKT_REGISTER_RMW_ADDR_addr_shift = 0 # macro +def SDMA_PKT_REGISTER_RMW_ADDR_ADDR(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset = 1 # macro +SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask = 0x00000FFF # macro +SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift = 20 # macro +def SDMA_PKT_REGISTER_RMW_ADDR_APERTURE_ID(x): # macro + return (((x)&0x00000FFF)<<20) +SDMA_PKT_REGISTER_RMW_MASK_mask_offset = 2 # macro +SDMA_PKT_REGISTER_RMW_MASK_mask_mask = 0xFFFFFFFF # macro +SDMA_PKT_REGISTER_RMW_MASK_mask_shift = 0 # macro +def SDMA_PKT_REGISTER_RMW_MASK_MASK(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_REGISTER_RMW_VALUE_value_offset = 3 # macro +SDMA_PKT_REGISTER_RMW_VALUE_value_mask = 0xFFFFFFFF # macro +SDMA_PKT_REGISTER_RMW_VALUE_value_shift = 0 # macro +def SDMA_PKT_REGISTER_RMW_VALUE_VALUE(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_REGISTER_RMW_MISC_stride_offset = 4 # macro +SDMA_PKT_REGISTER_RMW_MISC_stride_mask = 0x000FFFFF # macro +SDMA_PKT_REGISTER_RMW_MISC_stride_shift = 0 # macro +def SDMA_PKT_REGISTER_RMW_MISC_STRIDE(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset = 4 # macro +SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask = 0x00000FFF # macro +SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift = 20 # macro +def SDMA_PKT_REGISTER_RMW_MISC_NUM_OF_REG(x): # macro + return (((x)&0x00000FFF)<<20) +SDMA_PKT_WRITE_INCR_HEADER_op_offset = 0 # macro +SDMA_PKT_WRITE_INCR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_INCR_HEADER_op_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset = 0 # macro +SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift = 24 # macro +def SDMA_PKT_WRITE_INCR_HEADER_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<24) +SDMA_PKT_WRITE_INCR_HEADER_cpv_offset = 0 # macro +SDMA_PKT_WRITE_INCR_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_WRITE_INCR_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_WRITE_INCR_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset = 3 # macro +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset = 4 # macro +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset = 5 # macro +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset = 6 # macro +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset = 7 # macro +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset = 8 # macro +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask = 0xFFFFFFFF # macro +SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_WRITE_INCR_COUNT_count_offset = 9 # macro +SDMA_PKT_WRITE_INCR_COUNT_count_mask = 0x0007FFFF # macro +SDMA_PKT_WRITE_INCR_COUNT_count_shift = 0 # macro +def SDMA_PKT_WRITE_INCR_COUNT_COUNT(x): # macro + return (((x)&0x0007FFFF)<<0) +SDMA_PKT_INDIRECT_HEADER_op_offset = 0 # macro +SDMA_PKT_INDIRECT_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_INDIRECT_HEADER_op_shift = 0 # macro +def SDMA_PKT_INDIRECT_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_INDIRECT_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_INDIRECT_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_INDIRECT_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_INDIRECT_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_INDIRECT_HEADER_vmid_offset = 0 # macro +SDMA_PKT_INDIRECT_HEADER_vmid_mask = 0x0000000F # macro +SDMA_PKT_INDIRECT_HEADER_vmid_shift = 16 # macro +def SDMA_PKT_INDIRECT_HEADER_VMID(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_PKT_INDIRECT_HEADER_priv_offset = 0 # macro +SDMA_PKT_INDIRECT_HEADER_priv_mask = 0x00000001 # macro +SDMA_PKT_INDIRECT_HEADER_priv_shift = 31 # macro +def SDMA_PKT_INDIRECT_HEADER_PRIV(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset = 1 # macro +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift = 0 # macro +def SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset = 2 # macro +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift = 0 # macro +def SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset = 3 # macro +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask = 0x000FFFFF # macro +SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift = 0 # macro +def SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x): # macro + return (((x)&0x000FFFFF)<<0) +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset = 4 # macro +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift = 0 # macro +def SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset = 5 # macro +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift = 0 # macro +def SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_SEMAPHORE_HEADER_op_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_SEMAPHORE_HEADER_op_shift = 0 # macro +def SDMA_PKT_SEMAPHORE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_SEMAPHORE_HEADER_write_one_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_write_one_mask = 0x00000001 # macro +SDMA_PKT_SEMAPHORE_HEADER_write_one_shift = 29 # macro +def SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x): # macro + return (((x)&0x00000001)<<29) +SDMA_PKT_SEMAPHORE_HEADER_signal_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_signal_mask = 0x00000001 # macro +SDMA_PKT_SEMAPHORE_HEADER_signal_shift = 30 # macro +def SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x): # macro + return (((x)&0x00000001)<<30) +SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset = 0 # macro +SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask = 0x00000001 # macro +SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift = 31 # macro +def SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_MEM_INCR_HEADER_op_offset = 0 # macro +SDMA_PKT_MEM_INCR_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_MEM_INCR_HEADER_op_shift = 0 # macro +def SDMA_PKT_MEM_INCR_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_MEM_INCR_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_MEM_INCR_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_MEM_INCR_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_MEM_INCR_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset = 0 # macro +SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask = 0x00000003 # macro +SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift = 24 # macro +def SDMA_PKT_MEM_INCR_HEADER_L2_POLICY(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset = 0 # macro +SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask = 0x00000001 # macro +SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift = 26 # macro +def SDMA_PKT_MEM_INCR_HEADER_LLC_POLICY(x): # macro + return (((x)&0x00000001)<<26) +SDMA_PKT_MEM_INCR_HEADER_cpv_offset = 0 # macro +SDMA_PKT_MEM_INCR_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_MEM_INCR_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_MEM_INCR_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_MEM_INCR_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_MEM_INCR_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_VM_INVALIDATION_HEADER_op_offset = 0 # macro +SDMA_PKT_VM_INVALIDATION_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_VM_INVALIDATION_HEADER_op_shift = 0 # macro +def SDMA_PKT_VM_INVALIDATION_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset = 0 # macro +SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask = 0x0000001F # macro +SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift = 16 # macro +def SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x): # macro + return (((x)&0x0000001F)<<16) +SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset = 0 # macro +SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask = 0x0000001F # macro +SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift = 24 # macro +def SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x): # macro + return (((x)&0x0000001F)<<24) +SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset = 1 # macro +SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask = 0xFFFFFFFF # macro +SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift = 0 # macro +def SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset = 2 # macro +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask = 0xFFFFFFFF # macro +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift = 0 # macro +def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset = 3 # macro +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask = 0x0000FFFF # macro +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift = 0 # macro +def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x): # macro + return (((x)&0x0000FFFF)<<0) +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset = 3 # macro +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask = 0x0000001F # macro +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift = 16 # macro +def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x): # macro + return (((x)&0x0000001F)<<16) +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset = 3 # macro +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask = 0x000001FF # macro +SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift = 23 # macro +def SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x): # macro + return (((x)&0x000001FF)<<23) +SDMA_PKT_FENCE_HEADER_op_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_FENCE_HEADER_op_shift = 0 # macro +def SDMA_PKT_FENCE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_FENCE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_FENCE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_FENCE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_FENCE_HEADER_mtype_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_mtype_mask = 0x00000007 # macro +SDMA_PKT_FENCE_HEADER_mtype_shift = 16 # macro +def SDMA_PKT_FENCE_HEADER_MTYPE(x): # macro + return (((x)&0x00000007)<<16) +SDMA_PKT_FENCE_HEADER_gcc_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_gcc_mask = 0x00000001 # macro +SDMA_PKT_FENCE_HEADER_gcc_shift = 19 # macro +def SDMA_PKT_FENCE_HEADER_GCC(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_FENCE_HEADER_sys_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_sys_mask = 0x00000001 # macro +SDMA_PKT_FENCE_HEADER_sys_shift = 20 # macro +def SDMA_PKT_FENCE_HEADER_SYS(x): # macro + return (((x)&0x00000001)<<20) +SDMA_PKT_FENCE_HEADER_snp_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_snp_mask = 0x00000001 # macro +SDMA_PKT_FENCE_HEADER_snp_shift = 22 # macro +def SDMA_PKT_FENCE_HEADER_SNP(x): # macro + return (((x)&0x00000001)<<22) +SDMA_PKT_FENCE_HEADER_gpa_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_gpa_mask = 0x00000001 # macro +SDMA_PKT_FENCE_HEADER_gpa_shift = 23 # macro +def SDMA_PKT_FENCE_HEADER_GPA(x): # macro + return (((x)&0x00000001)<<23) +SDMA_PKT_FENCE_HEADER_l2_policy_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_l2_policy_mask = 0x00000003 # macro +SDMA_PKT_FENCE_HEADER_l2_policy_shift = 24 # macro +def SDMA_PKT_FENCE_HEADER_L2_POLICY(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_FENCE_HEADER_llc_policy_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_llc_policy_mask = 0x00000001 # macro +SDMA_PKT_FENCE_HEADER_llc_policy_shift = 26 # macro +def SDMA_PKT_FENCE_HEADER_LLC_POLICY(x): # macro + return (((x)&0x00000001)<<26) +SDMA_PKT_FENCE_HEADER_cpv_offset = 0 # macro +SDMA_PKT_FENCE_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_FENCE_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_FENCE_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_FENCE_DATA_data_offset = 3 # macro +SDMA_PKT_FENCE_DATA_data_mask = 0xFFFFFFFF # macro +SDMA_PKT_FENCE_DATA_data_shift = 0 # macro +def SDMA_PKT_FENCE_DATA_DATA(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_SRBM_WRITE_HEADER_op_offset = 0 # macro +SDMA_PKT_SRBM_WRITE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_SRBM_WRITE_HEADER_op_shift = 0 # macro +def SDMA_PKT_SRBM_WRITE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset = 0 # macro +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask = 0x0000000F # macro +SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift = 28 # macro +def SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x): # macro + return (((x)&0x0000000F)<<28) +SDMA_PKT_SRBM_WRITE_ADDR_addr_offset = 1 # macro +SDMA_PKT_SRBM_WRITE_ADDR_addr_mask = 0x0003FFFF # macro +SDMA_PKT_SRBM_WRITE_ADDR_addr_shift = 0 # macro +def SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x): # macro + return (((x)&0x0003FFFF)<<0) +SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset = 1 # macro +SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask = 0x00000FFF # macro +SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift = 20 # macro +def SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x): # macro + return (((x)&0x00000FFF)<<20) +SDMA_PKT_SRBM_WRITE_DATA_data_offset = 2 # macro +SDMA_PKT_SRBM_WRITE_DATA_data_mask = 0xFFFFFFFF # macro +SDMA_PKT_SRBM_WRITE_DATA_data_shift = 0 # macro +def SDMA_PKT_SRBM_WRITE_DATA_DATA(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_PRE_EXE_HEADER_op_offset = 0 # macro +SDMA_PKT_PRE_EXE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_PRE_EXE_HEADER_op_shift = 0 # macro +def SDMA_PKT_PRE_EXE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_PRE_EXE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_PRE_EXE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_PRE_EXE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset = 0 # macro +SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask = 0x000000FF # macro +SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift = 16 # macro +def SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x): # macro + return (((x)&0x000000FF)<<16) +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset = 1 # macro +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro +SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift = 0 # macro +def SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_COND_EXE_HEADER_op_offset = 0 # macro +SDMA_PKT_COND_EXE_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_COND_EXE_HEADER_op_shift = 0 # macro +def SDMA_PKT_COND_EXE_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_COND_EXE_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_COND_EXE_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_COND_EXE_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_COND_EXE_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_COND_EXE_HEADER_cache_policy_offset = 0 # macro +SDMA_PKT_COND_EXE_HEADER_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_COND_EXE_HEADER_cache_policy_shift = 24 # macro +def SDMA_PKT_COND_EXE_HEADER_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<24) +SDMA_PKT_COND_EXE_HEADER_cpv_offset = 0 # macro +SDMA_PKT_COND_EXE_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_COND_EXE_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_COND_EXE_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COND_EXE_REFERENCE_reference_offset = 3 # macro +SDMA_PKT_COND_EXE_REFERENCE_reference_mask = 0xFFFFFFFF # macro +SDMA_PKT_COND_EXE_REFERENCE_reference_shift = 0 # macro +def SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset = 4 # macro +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask = 0x00003FFF # macro +SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift = 0 # macro +def SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x): # macro + return (((x)&0x00003FFF)<<0) +SDMA_PKT_CONSTANT_FILL_HEADER_op_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_CONSTANT_FILL_HEADER_op_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask = 0x00000003 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift = 16 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift = 24 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<24) +SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset = 0 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask = 0x00000003 # macro +SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift = 30 # macro +def SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x): # macro + return (((x)&0x00000003)<<30) +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset = 1 # macro +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset = 2 # macro +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset = 3 # macro +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_CONSTANT_FILL_COUNT_count_offset = 4 # macro +SDMA_PKT_CONSTANT_FILL_COUNT_count_mask = 0x3FFFFFFF # macro +SDMA_PKT_CONSTANT_FILL_COUNT_count_shift = 0 # macro +def SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x): # macro + return (((x)&0x3FFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset = 0 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset = 0 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift = 24 # macro +def SDMA_PKT_DATA_FILL_MULTI_HEADER_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<24) +SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset = 0 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_DATA_FILL_MULTI_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset = 0 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask = 0x00000001 # macro +SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift = 31 # macro +def SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset = 1 # macro +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask = 0xFFFFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset = 2 # macro +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask = 0xFFFFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset = 3 # macro +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset = 4 # macro +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset = 5 # macro +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask = 0x03FFFFFF # macro +SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift = 0 # macro +def SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x): # macro + return (((x)&0x03FFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_HEADER_op_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_REGMEM_HEADER_op_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift = 20 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<20) +SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift = 24 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<24) +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask = 0x00000001 # macro +SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift = 26 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x): # macro + return (((x)&0x00000001)<<26) +SDMA_PKT_POLL_REGMEM_HEADER_func_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_func_mask = 0x00000007 # macro +SDMA_PKT_POLL_REGMEM_HEADER_func_shift = 28 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x): # macro + return (((x)&0x00000007)<<28) +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset = 0 # macro +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask = 0x00000001 # macro +SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift = 31 # macro +def SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_VALUE_value_offset = 3 # macro +SDMA_PKT_POLL_REGMEM_VALUE_value_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REGMEM_VALUE_value_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_MASK_mask_offset = 4 # macro +SDMA_PKT_POLL_REGMEM_MASK_mask_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REGMEM_MASK_mask_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_MASK_MASK(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REGMEM_DW5_interval_offset = 5 # macro +SDMA_PKT_POLL_REGMEM_DW5_interval_mask = 0x0000FFFF # macro +SDMA_PKT_POLL_REGMEM_DW5_interval_shift = 0 # macro +def SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x): # macro + return (((x)&0x0000FFFF)<<0) +SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset = 5 # macro +SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask = 0x00000FFF # macro +SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift = 16 # macro +def SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x): # macro + return (((x)&0x00000FFF)<<16) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset = 0 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift = 0 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset = 0 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift = 24 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<24) +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset = 0 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset = 1 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask = 0x3FFFFFFF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift = 2 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x): # macro + return (((x)&0x3FFFFFFF)<<2) +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 2 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 3 # macro +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset = 0 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift = 0 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset = 0 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask = 0x00000003 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift = 16 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x): # macro + return (((x)&0x00000003)<<16) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset = 0 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift = 24 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<24) +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset = 0 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset = 3 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask = 0x0FFFFFFF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift = 4 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x): # macro + return (((x)&0x0FFFFFFF)<<4) +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset = 4 # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift = 0 # macro +def SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset = 0 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset = 0 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift = 24 # macro +def SDMA_PKT_POLL_MEM_VERIFY_HEADER_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<24) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset = 0 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_POLL_MEM_VERIFY_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset = 0 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask = 0x00000001 # macro +SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift = 31 # macro +def SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x): # macro + return (((x)&0x00000001)<<31) +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset = 1 # macro +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset = 2 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset = 3 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset = 4 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP0_END_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset = 5 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP0_END_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset = 6 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset = 7 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset = 8 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset = 9 # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset = 10 # macro +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset = 11 # macro +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset = 12 # macro +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask = 0xFFFFFFFF # macro +SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift = 0 # macro +def SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_HEADER_op_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_ATOMIC_HEADER_op_shift = 0 # macro +def SDMA_PKT_ATOMIC_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_ATOMIC_HEADER_loop_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_loop_mask = 0x00000001 # macro +SDMA_PKT_ATOMIC_HEADER_loop_shift = 16 # macro +def SDMA_PKT_ATOMIC_HEADER_LOOP(x): # macro + return (((x)&0x00000001)<<16) +SDMA_PKT_ATOMIC_HEADER_tmz_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_tmz_mask = 0x00000001 # macro +SDMA_PKT_ATOMIC_HEADER_tmz_shift = 18 # macro +def SDMA_PKT_ATOMIC_HEADER_TMZ(x): # macro + return (((x)&0x00000001)<<18) +SDMA_PKT_ATOMIC_HEADER_cache_policy_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_cache_policy_mask = 0x00000007 # macro +SDMA_PKT_ATOMIC_HEADER_cache_policy_shift = 20 # macro +def SDMA_PKT_ATOMIC_HEADER_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<20) +SDMA_PKT_ATOMIC_HEADER_cpv_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_ATOMIC_HEADER_cpv_shift = 24 # macro +def SDMA_PKT_ATOMIC_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<24) +SDMA_PKT_ATOMIC_HEADER_atomic_op_offset = 0 # macro +SDMA_PKT_ATOMIC_HEADER_atomic_op_mask = 0x0000007F # macro +SDMA_PKT_ATOMIC_HEADER_atomic_op_shift = 25 # macro +def SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x): # macro + return (((x)&0x0000007F)<<25) +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset = 1 # macro +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift = 0 # macro +def SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset = 2 # macro +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift = 0 # macro +def SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset = 3 # macro +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift = 0 # macro +def SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset = 4 # macro +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift = 0 # macro +def SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset = 5 # macro +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift = 0 # macro +def SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset = 6 # macro +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift = 0 # macro +def SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset = 7 # macro +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask = 0x00001FFF # macro +SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift = 0 # macro +def SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x): # macro + return (((x)&0x00001FFF)<<0) +SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset = 1 # macro +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask = 0xFFFFFFFF # macro +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset = 2 # macro +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask = 0x00000003 # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift = 24 # macro +def SDMA_PKT_TIMESTAMP_GET_HEADER_L2_POLICY(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask = 0x00000001 # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift = 26 # macro +def SDMA_PKT_TIMESTAMP_GET_HEADER_LLC_POLICY(x): # macro + return (((x)&0x00000001)<<26) +SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_TIMESTAMP_GET_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro +def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro + return (((x)&0x1FFFFFFF)<<3) +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask = 0x00000003 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift = 24 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_L2_POLICY(x): # macro + return (((x)&0x00000003)<<24) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask = 0x00000001 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift = 26 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_LLC_POLICY(x): # macro + return (((x)&0x00000001)<<26) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset = 0 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask = 0x00000001 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift = 28 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset = 1 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask = 0x1FFFFFFF # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift = 3 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x): # macro + return (((x)&0x1FFFFFFF)<<3) +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset = 2 # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift = 0 # macro +def SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_PKT_TRAP_HEADER_op_offset = 0 # macro +SDMA_PKT_TRAP_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_TRAP_HEADER_op_shift = 0 # macro +def SDMA_PKT_TRAP_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_TRAP_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_TRAP_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_TRAP_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_TRAP_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset = 1 # macro +SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro +SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift = 0 # macro +def SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_DUMMY_TRAP_HEADER_op_offset = 0 # macro +SDMA_PKT_DUMMY_TRAP_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_DUMMY_TRAP_HEADER_op_shift = 0 # macro +def SDMA_PKT_DUMMY_TRAP_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset = 1 # macro +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask = 0x0FFFFFFF # macro +SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift = 0 # macro +def SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x): # macro + return (((x)&0x0FFFFFFF)<<0) +SDMA_PKT_GPUVM_INV_HEADER_op_offset = 0 # macro +SDMA_PKT_GPUVM_INV_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_GPUVM_INV_HEADER_op_shift = 0 # macro +def SDMA_PKT_GPUVM_INV_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset = 1 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask = 0x0000FFFF # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift = 0 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x): # macro + return (((x)&0x0000FFFF)<<0) +SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset = 1 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask = 0x00000007 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift = 16 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x): # macro + return (((x)&0x00000007)<<16) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset = 1 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask = 0x00000001 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift = 19 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x): # macro + return (((x)&0x00000001)<<19) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset = 1 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask = 0x00000001 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift = 20 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x): # macro + return (((x)&0x00000001)<<20) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset = 1 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask = 0x00000001 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift = 21 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x): # macro + return (((x)&0x00000001)<<21) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset = 1 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask = 0x00000001 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift = 22 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x): # macro + return (((x)&0x00000001)<<22) +SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset = 1 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask = 0x00000001 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift = 23 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x): # macro + return (((x)&0x00000001)<<23) +SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset = 1 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask = 0x00000001 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift = 24 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x): # macro + return (((x)&0x00000001)<<24) +SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset = 1 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask = 0x00000001 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift = 25 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x): # macro + return (((x)&0x00000001)<<25) +SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset = 1 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask = 0x00000001 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift = 26 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x): # macro + return (((x)&0x00000001)<<26) +SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset = 2 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask = 0x00000001 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift = 0 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x): # macro + return (((x)&0x00000001)<<0) +SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset = 2 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask = 0x7FFFFFFF # macro +SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift = 1 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x): # macro + return (((x)&0x7FFFFFFF)<<1) +SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset = 3 # macro +SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask = 0x0000003F # macro +SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift = 0 # macro +def SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x): # macro + return (((x)&0x0000003F)<<0) +SDMA_PKT_GCR_REQ_HEADER_op_offset = 0 # macro +SDMA_PKT_GCR_REQ_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_GCR_REQ_HEADER_op_shift = 0 # macro +def SDMA_PKT_GCR_REQ_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_GCR_REQ_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_GCR_REQ_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_GCR_REQ_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset = 1 # macro +SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask = 0x01FFFFFF # macro +SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift = 7 # macro +def SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x): # macro + return (((x)&0x01FFFFFF)<<7) +SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset = 2 # macro +SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask = 0x0000FFFF # macro +SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift = 0 # macro +def SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(x): # macro + return (((x)&0x0000FFFF)<<0) +SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset = 2 # macro +SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask = 0x0000FFFF # macro +SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift = 16 # macro +def SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(x): # macro + return (((x)&0x0000FFFF)<<16) +SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset = 3 # macro +SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask = 0x00000007 # macro +SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift = 0 # macro +def SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(x): # macro + return (((x)&0x00000007)<<0) +SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset = 3 # macro +SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask = 0x01FFFFFF # macro +SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift = 7 # macro +def SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(x): # macro + return (((x)&0x01FFFFFF)<<7) +SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset = 4 # macro +SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask = 0x0000FFFF # macro +SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift = 0 # macro +def SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(x): # macro + return (((x)&0x0000FFFF)<<0) +SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset = 4 # macro +SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask = 0x0000000F # macro +SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift = 24 # macro +def SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(x): # macro + return (((x)&0x0000000F)<<24) +SDMA_PKT_NOP_HEADER_op_offset = 0 # macro +SDMA_PKT_NOP_HEADER_op_mask = 0x000000FF # macro +SDMA_PKT_NOP_HEADER_op_shift = 0 # macro +def SDMA_PKT_NOP_HEADER_OP(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_PKT_NOP_HEADER_sub_op_offset = 0 # macro +SDMA_PKT_NOP_HEADER_sub_op_mask = 0x000000FF # macro +SDMA_PKT_NOP_HEADER_sub_op_shift = 8 # macro +def SDMA_PKT_NOP_HEADER_SUB_OP(x): # macro + return (((x)&0x000000FF)<<8) +SDMA_PKT_NOP_HEADER_count_offset = 0 # macro +SDMA_PKT_NOP_HEADER_count_mask = 0x00003FFF # macro +SDMA_PKT_NOP_HEADER_count_shift = 16 # macro +def SDMA_PKT_NOP_HEADER_COUNT(x): # macro + return (((x)&0x00003FFF)<<16) +SDMA_PKT_NOP_DATA0_data0_offset = 1 # macro +SDMA_PKT_NOP_DATA0_data0_mask = 0xFFFFFFFF # macro +SDMA_PKT_NOP_DATA0_data0_shift = 0 # macro +def SDMA_PKT_NOP_DATA0_DATA0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_HEADER_HEADER_format_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_format_mask = 0x000000FF # macro +SDMA_AQL_PKT_HEADER_HEADER_format_shift = 0 # macro +def SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_AQL_PKT_HEADER_HEADER_barrier_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_barrier_mask = 0x00000001 # macro +SDMA_AQL_PKT_HEADER_HEADER_barrier_shift = 8 # macro +def SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x): # macro + return (((x)&0x00000001)<<8) +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift = 9 # macro +def SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<9) +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift = 11 # macro +def SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<11) +SDMA_AQL_PKT_HEADER_HEADER_reserved_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_reserved_mask = 0x00000007 # macro +SDMA_AQL_PKT_HEADER_HEADER_reserved_shift = 13 # macro +def SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x): # macro + return (((x)&0x00000007)<<13) +SDMA_AQL_PKT_HEADER_HEADER_op_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_op_mask = 0x0000000F # macro +SDMA_AQL_PKT_HEADER_HEADER_op_shift = 16 # macro +def SDMA_AQL_PKT_HEADER_HEADER_OP(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_AQL_PKT_HEADER_HEADER_subop_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_subop_mask = 0x00000007 # macro +SDMA_AQL_PKT_HEADER_HEADER_subop_shift = 20 # macro +def SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x): # macro + return (((x)&0x00000007)<<20) +SDMA_AQL_PKT_HEADER_HEADER_cpv_offset = 0 # macro +SDMA_AQL_PKT_HEADER_HEADER_cpv_mask = 0x00000001 # macro +SDMA_AQL_PKT_HEADER_HEADER_cpv_shift = 28 # macro +def SDMA_AQL_PKT_HEADER_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask = 0x000000FF # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask = 0x00000001 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift = 8 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x): # macro + return (((x)&0x00000001)<<8) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift = 9 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<9) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift = 11 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<11) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask = 0x00000007 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift = 13 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x): # macro + return (((x)&0x00000007)<<13) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask = 0x0000000F # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift = 16 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask = 0x00000007 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift = 20 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x): # macro + return (((x)&0x00000007)<<20) +SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset = 0 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask = 0x00000001 # macro +SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift = 28 # macro +def SDMA_AQL_PKT_COPY_LINEAR_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset = 1 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset = 2 # macro +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset = 3 # macro +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset = 4 # macro +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask = 0x003FFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x): # macro + return (((x)&0x003FFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset = 5 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask = 0x00000003 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift = 16 # macro +def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x): # macro + return (((x)&0x00000003)<<16) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset = 5 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask = 0x00000007 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift = 18 # macro +def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<18) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset = 5 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask = 0x00000003 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift = 24 # macro +def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x): # macro + return (((x)&0x00000003)<<24) +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset = 5 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask = 0x00000007 # macro +SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift = 26 # macro +def SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x): # macro + return (((x)&0x00000007)<<26) +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset = 6 # macro +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset = 7 # macro +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset = 8 # macro +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset = 9 # macro +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset = 10 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset = 11 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset = 12 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset = 13 # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro +def SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask = 0x000000FF # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x): # macro + return (((x)&0x000000FF)<<0) +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask = 0x00000001 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift = 8 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x): # macro + return (((x)&0x00000001)<<8) +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift = 9 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<9) +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask = 0x00000003 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift = 11 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x): # macro + return (((x)&0x00000003)<<11) +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask = 0x00000007 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift = 13 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x): # macro + return (((x)&0x00000007)<<13) +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask = 0x0000000F # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift = 16 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x): # macro + return (((x)&0x0000000F)<<16) +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask = 0x00000007 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift = 20 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x): # macro + return (((x)&0x00000007)<<20) +SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset = 0 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask = 0x00000001 # macro +SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift = 28 # macro +def SDMA_AQL_PKT_BARRIER_OR_HEADER_CPV(x): # macro + return (((x)&0x00000001)<<28) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset = 1 # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset = 2 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset = 3 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset = 4 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset = 5 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset = 6 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset = 7 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset = 8 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset = 9 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset = 10 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset = 11 # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset = 12 # macro +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask = 0x00000007 # macro +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY0(x): # macro + return (((x)&0x00000007)<<0) +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset = 12 # macro +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask = 0x00000007 # macro +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift = 5 # macro +def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY1(x): # macro + return (((x)&0x00000007)<<5) +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset = 12 # macro +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask = 0x00000007 # macro +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift = 10 # macro +def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY2(x): # macro + return (((x)&0x00000007)<<10) +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset = 12 # macro +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask = 0x00000007 # macro +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift = 15 # macro +def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY3(x): # macro + return (((x)&0x00000007)<<15) +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset = 12 # macro +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask = 0x00000007 # macro +SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift = 20 # macro +def SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY4(x): # macro + return (((x)&0x00000007)<<20) +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset = 13 # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset = 14 # macro +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x): # macro + return (((x)&0xFFFFFFFF)<<0) +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset = 15 # macro +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask = 0xFFFFFFFF # macro +SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift = 0 # macro +def SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x): # macro + return (((x)&0xFFFFFFFF)<<0) _gc_11_0_0_OFFSET_HEADER = True # macro regSDMA0_DEC_START = 0x0000 # macro regSDMA0_DEC_START_BASE_IDX = 0 # macro @@ -12626,119 +47635,119 @@ regGFX_IMU_I_RAM_ADDR = 0x5f90 # macro regGFX_IMU_I_RAM_ADDR_BASE_IDX = 1 # macro regGFX_IMU_I_RAM_DATA = 0x5f91 # macro regGFX_IMU_I_RAM_DATA_BASE_IDX = 1 # macro -ixGC_CAC_ID = 0x0000 # macro -ixGC_CAC_CNTL = 0x0001 # macro -ixGC_CAC_ACC_CP0 = 0x0010 # macro -ixGC_CAC_ACC_CP1 = 0x0011 # macro -ixGC_CAC_ACC_CP2 = 0x0012 # macro -ixGC_CAC_ACC_EA0 = 0x0013 # macro -ixGC_CAC_ACC_EA1 = 0x0014 # macro -ixGC_CAC_ACC_EA2 = 0x0015 # macro -ixGC_CAC_ACC_EA3 = 0x0016 # macro -ixGC_CAC_ACC_EA4 = 0x0017 # macro -ixGC_CAC_ACC_EA5 = 0x0018 # macro -ixGC_CAC_ACC_UTCL2_ROUTER0 = 0x0019 # macro -ixGC_CAC_ACC_UTCL2_ROUTER1 = 0x001a # macro -ixGC_CAC_ACC_UTCL2_ROUTER2 = 0x001b # macro -ixGC_CAC_ACC_UTCL2_ROUTER3 = 0x001c # macro -ixGC_CAC_ACC_UTCL2_ROUTER4 = 0x001d # macro -ixGC_CAC_ACC_UTCL2_ROUTER5 = 0x001e # macro -ixGC_CAC_ACC_UTCL2_ROUTER6 = 0x001f # macro -ixGC_CAC_ACC_UTCL2_ROUTER7 = 0x0020 # macro -ixGC_CAC_ACC_UTCL2_ROUTER8 = 0x0021 # macro -ixGC_CAC_ACC_UTCL2_ROUTER9 = 0x0022 # macro -ixGC_CAC_ACC_UTCL2_VML20 = 0x0023 # macro -ixGC_CAC_ACC_UTCL2_VML21 = 0x0024 # macro -ixGC_CAC_ACC_UTCL2_VML22 = 0x0025 # macro -ixGC_CAC_ACC_UTCL2_VML23 = 0x0026 # macro -ixGC_CAC_ACC_UTCL2_VML24 = 0x0027 # macro -ixGC_CAC_ACC_UTCL2_WALKER0 = 0x0028 # macro -ixGC_CAC_ACC_UTCL2_WALKER1 = 0x0029 # macro -ixGC_CAC_ACC_UTCL2_WALKER2 = 0x002a # macro -ixGC_CAC_ACC_UTCL2_WALKER3 = 0x002b # macro -ixGC_CAC_ACC_UTCL2_WALKER4 = 0x002c # macro -ixGC_CAC_ACC_GDS0 = 0x002d # macro -ixGC_CAC_ACC_GDS1 = 0x002e # macro -ixGC_CAC_ACC_GDS2 = 0x002f # macro -ixGC_CAC_ACC_GDS3 = 0x0030 # macro -ixGC_CAC_ACC_GDS4 = 0x0031 # macro -ixGC_CAC_ACC_GE0 = 0x0032 # macro -ixGC_CAC_ACC_GE1 = 0x0033 # macro -ixGC_CAC_ACC_GE2 = 0x0034 # macro -ixGC_CAC_ACC_GE3 = 0x0035 # macro -ixGC_CAC_ACC_GE4 = 0x0036 # macro -ixGC_CAC_ACC_GE5 = 0x0037 # macro -ixGC_CAC_ACC_GE6 = 0x0038 # macro -ixGC_CAC_ACC_GE7 = 0x0039 # macro -ixGC_CAC_ACC_GE8 = 0x003a # macro -ixGC_CAC_ACC_GE9 = 0x003b # macro -ixGC_CAC_ACC_GE10 = 0x003c # macro -ixGC_CAC_ACC_GE11 = 0x003d # macro -ixGC_CAC_ACC_GE12 = 0x003e # macro -ixGC_CAC_ACC_GE13 = 0x003f # macro -ixGC_CAC_ACC_GE14 = 0x0040 # macro -ixGC_CAC_ACC_GE15 = 0x0041 # macro -ixGC_CAC_ACC_GE16 = 0x0042 # macro -ixGC_CAC_ACC_GE17 = 0x0043 # macro -ixGC_CAC_ACC_GE18 = 0x0044 # macro -ixGC_CAC_ACC_GE19 = 0x0045 # macro -ixGC_CAC_ACC_GE20 = 0x0046 # macro -ixGC_CAC_ACC_PMM0 = 0x0047 # macro -ixGC_CAC_ACC_GL2C0 = 0x0048 # macro -ixGC_CAC_ACC_GL2C1 = 0x0049 # macro -ixGC_CAC_ACC_GL2C2 = 0x004a # macro -ixGC_CAC_ACC_GL2C3 = 0x004b # macro -ixGC_CAC_ACC_GL2C4 = 0x004c # macro -ixGC_CAC_ACC_PH0 = 0x004d # macro -ixGC_CAC_ACC_PH1 = 0x004e # macro -ixGC_CAC_ACC_PH2 = 0x004f # macro -ixGC_CAC_ACC_PH3 = 0x0050 # macro -ixGC_CAC_ACC_PH4 = 0x0051 # macro -ixGC_CAC_ACC_PH5 = 0x0052 # macro -ixGC_CAC_ACC_PH6 = 0x0053 # macro -ixGC_CAC_ACC_PH7 = 0x0054 # macro -ixGC_CAC_ACC_SDMA0 = 0x0055 # macro -ixGC_CAC_ACC_SDMA1 = 0x0056 # macro -ixGC_CAC_ACC_SDMA2 = 0x0057 # macro -ixGC_CAC_ACC_SDMA3 = 0x0058 # macro -ixGC_CAC_ACC_SDMA4 = 0x0059 # macro -ixGC_CAC_ACC_SDMA5 = 0x005a # macro -ixGC_CAC_ACC_SDMA6 = 0x005b # macro -ixGC_CAC_ACC_SDMA7 = 0x005c # macro -ixGC_CAC_ACC_SDMA8 = 0x005d # macro -ixGC_CAC_ACC_SDMA9 = 0x005e # macro -ixGC_CAC_ACC_SDMA10 = 0x005f # macro -ixGC_CAC_ACC_SDMA11 = 0x0060 # macro -ixGC_CAC_ACC_CHC0 = 0x0061 # macro -ixGC_CAC_ACC_CHC1 = 0x0062 # macro -ixGC_CAC_ACC_CHC2 = 0x0063 # macro -ixGC_CAC_ACC_GUS0 = 0x0064 # macro -ixGC_CAC_ACC_GUS1 = 0x0065 # macro -ixGC_CAC_ACC_GUS2 = 0x0066 # macro -ixGC_CAC_ACC_RLC0 = 0x0067 # macro -ixRELEASE_TO_STALL_LUT_1_8 = 0x0100 # macro -ixRELEASE_TO_STALL_LUT_9_16 = 0x0101 # macro -ixRELEASE_TO_STALL_LUT_17_20 = 0x0102 # macro -ixSTALL_TO_RELEASE_LUT_1_4 = 0x0103 # macro -ixSTALL_TO_RELEASE_LUT_5_7 = 0x0104 # macro -ixSTALL_TO_PWRBRK_LUT_1_4 = 0x0105 # macro -ixSTALL_TO_PWRBRK_LUT_5_7 = 0x0106 # macro -ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 = 0x0107 # macro -ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 = 0x0108 # macro -ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 = 0x0109 # macro -ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 = 0x010a # macro -ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 = 0x010b # macro -ixFIXED_PATTERN_PERF_COUNTER_1 = 0x010c # macro -ixFIXED_PATTERN_PERF_COUNTER_2 = 0x010d # macro -ixFIXED_PATTERN_PERF_COUNTER_3 = 0x010e # macro -ixFIXED_PATTERN_PERF_COUNTER_4 = 0x010f # macro -ixFIXED_PATTERN_PERF_COUNTER_5 = 0x0110 # macro -ixFIXED_PATTERN_PERF_COUNTER_6 = 0x0111 # macro -ixFIXED_PATTERN_PERF_COUNTER_7 = 0x0112 # macro -ixFIXED_PATTERN_PERF_COUNTER_8 = 0x0113 # macro -ixFIXED_PATTERN_PERF_COUNTER_9 = 0x0114 # macro -ixFIXED_PATTERN_PERF_COUNTER_10 = 0x0115 # macro -ixHW_LUT_UPDATE_STATUS = 0x0116 # macro +ixGC_CAC_ID = 0x0020 # macro +ixGC_CAC_CNTL = 0x0021 # macro +ixGC_CAC_ACC_CP0 = 0x0115 # macro +ixGC_CAC_ACC_CP1 = 0x0116 # macro +ixGC_CAC_ACC_CP2 = 0x0117 # macro +ixGC_CAC_ACC_EA0 = 0x016c # macro +ixGC_CAC_ACC_EA1 = 0x016d # macro +ixGC_CAC_ACC_EA2 = 0x016e # macro +ixGC_CAC_ACC_EA3 = 0x016f # macro +ixGC_CAC_ACC_EA4 = 0x0170 # macro +ixGC_CAC_ACC_EA5 = 0x0171 # macro +ixGC_CAC_ACC_UTCL2_ROUTER0 = 0x0177 # macro +ixGC_CAC_ACC_UTCL2_ROUTER1 = 0x0178 # macro +ixGC_CAC_ACC_UTCL2_ROUTER2 = 0x0179 # macro +ixGC_CAC_ACC_UTCL2_ROUTER3 = 0x017a # macro +ixGC_CAC_ACC_UTCL2_ROUTER4 = 0x017b # macro +ixGC_CAC_ACC_UTCL2_ROUTER5 = 0x017c # macro +ixGC_CAC_ACC_UTCL2_ROUTER6 = 0x017d # macro +ixGC_CAC_ACC_UTCL2_ROUTER7 = 0x017e # macro +ixGC_CAC_ACC_UTCL2_ROUTER8 = 0x017f # macro +ixGC_CAC_ACC_UTCL2_ROUTER9 = 0x0180 # macro +ixGC_CAC_ACC_UTCL2_VML20 = 0x0181 # macro +ixGC_CAC_ACC_UTCL2_VML21 = 0x0182 # macro +ixGC_CAC_ACC_UTCL2_VML22 = 0x0183 # macro +ixGC_CAC_ACC_UTCL2_VML23 = 0x0184 # macro +ixGC_CAC_ACC_UTCL2_VML24 = 0x0185 # macro +ixGC_CAC_ACC_UTCL2_WALKER0 = 0x0186 # macro +ixGC_CAC_ACC_UTCL2_WALKER1 = 0x0187 # macro +ixGC_CAC_ACC_UTCL2_WALKER2 = 0x0188 # macro +ixGC_CAC_ACC_UTCL2_WALKER3 = 0x0189 # macro +ixGC_CAC_ACC_UTCL2_WALKER4 = 0x018a # macro +ixGC_CAC_ACC_GDS0 = 0x0122 # macro +ixGC_CAC_ACC_GDS1 = 0x0123 # macro +ixGC_CAC_ACC_GDS2 = 0x0124 # macro +ixGC_CAC_ACC_GDS3 = 0x0125 # macro +ixGC_CAC_ACC_GDS4 = 0x0126 # macro +ixGC_CAC_ACC_GE0 = 0x0190 # macro +ixGC_CAC_ACC_GE1 = 0x0191 # macro +ixGC_CAC_ACC_GE2 = 0x0192 # macro +ixGC_CAC_ACC_GE3 = 0x0193 # macro +ixGC_CAC_ACC_GE4 = 0x0194 # macro +ixGC_CAC_ACC_GE5 = 0x0195 # macro +ixGC_CAC_ACC_GE6 = 0x0196 # macro +ixGC_CAC_ACC_GE7 = 0x0197 # macro +ixGC_CAC_ACC_GE8 = 0x0198 # macro +ixGC_CAC_ACC_GE9 = 0x0199 # macro +ixGC_CAC_ACC_GE10 = 0x019a # macro +ixGC_CAC_ACC_GE11 = 0x019b # macro +ixGC_CAC_ACC_GE12 = 0x019c # macro +ixGC_CAC_ACC_GE13 = 0x019d # macro +ixGC_CAC_ACC_GE14 = 0x019e # macro +ixGC_CAC_ACC_GE15 = 0x019f # macro +ixGC_CAC_ACC_GE16 = 0x01a0 # macro +ixGC_CAC_ACC_GE17 = 0x01a1 # macro +ixGC_CAC_ACC_GE18 = 0x01a2 # macro +ixGC_CAC_ACC_GE19 = 0x01a3 # macro +ixGC_CAC_ACC_GE20 = 0x01a4 # macro +ixGC_CAC_ACC_PMM0 = 0x01a5 # macro +ixGC_CAC_ACC_GL2C0 = 0x01a6 # macro +ixGC_CAC_ACC_GL2C1 = 0x01a7 # macro +ixGC_CAC_ACC_GL2C2 = 0x01a8 # macro +ixGC_CAC_ACC_GL2C3 = 0x01a9 # macro +ixGC_CAC_ACC_GL2C4 = 0x01aa # macro +ixGC_CAC_ACC_PH0 = 0x01ae # macro +ixGC_CAC_ACC_PH1 = 0x01af # macro +ixGC_CAC_ACC_PH2 = 0x01b0 # macro +ixGC_CAC_ACC_PH3 = 0x01b1 # macro +ixGC_CAC_ACC_PH4 = 0x01b2 # macro +ixGC_CAC_ACC_PH5 = 0x01b3 # macro +ixGC_CAC_ACC_PH6 = 0x01b4 # macro +ixGC_CAC_ACC_PH7 = 0x01b5 # macro +ixGC_CAC_ACC_SDMA0 = 0x01b6 # macro +ixGC_CAC_ACC_SDMA1 = 0x01b7 # macro +ixGC_CAC_ACC_SDMA2 = 0x01b8 # macro +ixGC_CAC_ACC_SDMA3 = 0x01b9 # macro +ixGC_CAC_ACC_SDMA4 = 0x01ba # macro +ixGC_CAC_ACC_SDMA5 = 0x01bb # macro +ixGC_CAC_ACC_SDMA6 = 0x01bc # macro +ixGC_CAC_ACC_SDMA7 = 0x01bd # macro +ixGC_CAC_ACC_SDMA8 = 0x01be # macro +ixGC_CAC_ACC_SDMA9 = 0x01bf # macro +ixGC_CAC_ACC_SDMA10 = 0x01c0 # macro +ixGC_CAC_ACC_SDMA11 = 0x01c1 # macro +ixGC_CAC_ACC_CHC0 = 0x018d # macro +ixGC_CAC_ACC_CHC1 = 0x018e # macro +ixGC_CAC_ACC_CHC2 = 0x018f # macro +ixGC_CAC_ACC_GUS0 = 0x01ab # macro +ixGC_CAC_ACC_GUS1 = 0x01ac # macro +ixGC_CAC_ACC_GUS2 = 0x01ad # macro +ixGC_CAC_ACC_RLC0 = 0x01d0 # macro +ixRELEASE_TO_STALL_LUT_1_8 = 0x0230 # macro +ixRELEASE_TO_STALL_LUT_9_16 = 0x0231 # macro +ixRELEASE_TO_STALL_LUT_17_20 = 0x0232 # macro +ixSTALL_TO_RELEASE_LUT_1_4 = 0x0233 # macro +ixSTALL_TO_RELEASE_LUT_5_7 = 0x0234 # macro +ixSTALL_TO_PWRBRK_LUT_1_4 = 0x0235 # macro +ixSTALL_TO_PWRBRK_LUT_5_7 = 0x0236 # macro +ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 = 0x0237 # macro +ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 = 0x0238 # macro +ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 = 0x0239 # macro +ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 = 0x023a # macro +ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 = 0x023b # macro +ixFIXED_PATTERN_PERF_COUNTER_1 = 0x023c # macro +ixFIXED_PATTERN_PERF_COUNTER_2 = 0x023d # macro +ixFIXED_PATTERN_PERF_COUNTER_3 = 0x023e # macro +ixFIXED_PATTERN_PERF_COUNTER_4 = 0x023f # macro +ixFIXED_PATTERN_PERF_COUNTER_5 = 0x0240 # macro +ixFIXED_PATTERN_PERF_COUNTER_6 = 0x0241 # macro +ixFIXED_PATTERN_PERF_COUNTER_7 = 0x0242 # macro +ixFIXED_PATTERN_PERF_COUNTER_8 = 0x0243 # macro +ixFIXED_PATTERN_PERF_COUNTER_9 = 0x0244 # macro +ixFIXED_PATTERN_PERF_COUNTER_10 = 0x0245 # macro +ixHW_LUT_UPDATE_STATUS = 0x0246 # macro ixSE_CAC_ID = 0x0000 # macro ixSE_CAC_CNTL = 0x0001 # macro ixRTAVFS_REG0 = 0x0000 # macro @@ -12973,9 +47982,12967 @@ ixSQ_WAVE_TTMP12 = 0x0278 # macro ixSQ_WAVE_TTMP13 = 0x0279 # macro ixSQ_WAVE_TTMP14 = 0x027a # macro ixSQ_WAVE_TTMP15 = 0x027b # macro -ixSQ_WAVE_M0 = 0x027d # macro +ixSQ_WAVE_M0 = 0x027c # macro ixSQ_WAVE_EXEC_LO = 0x027e # macro ixSQ_WAVE_EXEC_HI = 0x027f # macro +_gc_10_3_0_OFFSET_HEADER = True # macro +mmSQ_DEBUG_STS_GLOBAL = 0x10A9 # macro +mmSQ_DEBUG_STS_GLOBAL_BASE_IDX = 0 # macro +mmSQ_DEBUG_STS_GLOBAL2 = 0x10B0 # macro +mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX = 0 # macro +mmSQ_DEBUG = 0x10B1 # macro +mmSQ_DEBUG_BASE_IDX = 0 # macro +mmSDMA0_DEC_START = 0x0000 # macro +mmSDMA0_DEC_START_BASE_IDX = 0 # macro +mmSDMA0_GLOBAL_TIMESTAMP_LO = 0x000f # macro +mmSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro +mmSDMA0_GLOBAL_TIMESTAMP_HI = 0x0010 # macro +mmSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro +mmSDMA0_PG_CNTL = 0x0016 # macro +mmSDMA0_PG_CNTL_BASE_IDX = 0 # macro +mmSDMA0_PG_CTX_LO = 0x0017 # macro +mmSDMA0_PG_CTX_LO_BASE_IDX = 0 # macro +mmSDMA0_PG_CTX_HI = 0x0018 # macro +mmSDMA0_PG_CTX_HI_BASE_IDX = 0 # macro +mmSDMA0_PG_CTX_CNTL = 0x0019 # macro +mmSDMA0_PG_CTX_CNTL_BASE_IDX = 0 # macro +mmSDMA0_POWER_CNTL = 0x001a # macro +mmSDMA0_POWER_CNTL_BASE_IDX = 0 # macro +mmSDMA0_CLK_CTRL = 0x001b # macro +mmSDMA0_CLK_CTRL_BASE_IDX = 0 # macro +mmSDMA0_CNTL = 0x001c # macro +mmSDMA0_CNTL_BASE_IDX = 0 # macro +mmSDMA0_CHICKEN_BITS = 0x001d # macro +mmSDMA0_CHICKEN_BITS_BASE_IDX = 0 # macro +mmSDMA0_GB_ADDR_CONFIG = 0x001e # macro +mmSDMA0_GB_ADDR_CONFIG_BASE_IDX = 0 # macro +mmSDMA0_GB_ADDR_CONFIG_READ = 0x001f # macro +mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro +mmSDMA0_RB_RPTR_FETCH_HI = 0x0020 # macro +mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro +mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL = 0x0021 # macro +mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RB_RPTR_FETCH = 0x0022 # macro +mmSDMA0_RB_RPTR_FETCH_BASE_IDX = 0 # macro +mmSDMA0_IB_OFFSET_FETCH = 0x0023 # macro +mmSDMA0_IB_OFFSET_FETCH_BASE_IDX = 0 # macro +mmSDMA0_PROGRAM = 0x0024 # macro +mmSDMA0_PROGRAM_BASE_IDX = 0 # macro +mmSDMA0_STATUS_REG = 0x0025 # macro +mmSDMA0_STATUS_REG_BASE_IDX = 0 # macro +mmSDMA0_STATUS1_REG = 0x0026 # macro +mmSDMA0_STATUS1_REG_BASE_IDX = 0 # macro +mmSDMA0_RD_BURST_CNTL = 0x0027 # macro +mmSDMA0_RD_BURST_CNTL_BASE_IDX = 0 # macro +mmSDMA0_HBM_PAGE_CONFIG = 0x0028 # macro +mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro +mmSDMA0_UCODE_CHECKSUM = 0x0029 # macro +mmSDMA0_UCODE_CHECKSUM_BASE_IDX = 0 # macro +mmSDMA0_F32_CNTL = 0x002a # macro +mmSDMA0_F32_CNTL_BASE_IDX = 0 # macro +mmSDMA0_FREEZE = 0x002b # macro +mmSDMA0_FREEZE_BASE_IDX = 0 # macro +mmSDMA0_PHASE0_QUANTUM = 0x002c # macro +mmSDMA0_PHASE0_QUANTUM_BASE_IDX = 0 # macro +mmSDMA0_PHASE1_QUANTUM = 0x002d # macro +mmSDMA0_PHASE1_QUANTUM_BASE_IDX = 0 # macro +mmSDMA0_EDC_CONFIG = 0x0032 # macro +mmSDMA0_EDC_CONFIG_BASE_IDX = 0 # macro +mmSDMA0_BA_THRESHOLD = 0x0033 # macro +mmSDMA0_BA_THRESHOLD_BASE_IDX = 0 # macro +mmSDMA0_ID = 0x0034 # macro +mmSDMA0_ID_BASE_IDX = 0 # macro +mmSDMA0_VERSION = 0x0035 # macro +mmSDMA0_VERSION_BASE_IDX = 0 # macro +mmSDMA0_EDC_COUNTER = 0x0036 # macro +mmSDMA0_EDC_COUNTER_BASE_IDX = 0 # macro +mmSDMA0_EDC_COUNTER_CLEAR = 0x0037 # macro +mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro +mmSDMA0_STATUS2_REG = 0x0038 # macro +mmSDMA0_STATUS2_REG_BASE_IDX = 0 # macro +mmSDMA0_ATOMIC_CNTL = 0x0039 # macro +mmSDMA0_ATOMIC_CNTL_BASE_IDX = 0 # macro +mmSDMA0_ATOMIC_PREOP_LO = 0x003a # macro +mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro +mmSDMA0_ATOMIC_PREOP_HI = 0x003b # macro +mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_CNTL = 0x003c # macro +mmSDMA0_UTCL1_CNTL_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_WATERMK = 0x003d # macro +mmSDMA0_UTCL1_WATERMK_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_RD_STATUS = 0x003e # macro +mmSDMA0_UTCL1_RD_STATUS_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_WR_STATUS = 0x003f # macro +mmSDMA0_UTCL1_WR_STATUS_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_INV0 = 0x0040 # macro +mmSDMA0_UTCL1_INV0_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_INV1 = 0x0041 # macro +mmSDMA0_UTCL1_INV1_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_INV2 = 0x0042 # macro +mmSDMA0_UTCL1_INV2_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_RD_XNACK0 = 0x0043 # macro +mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_RD_XNACK1 = 0x0044 # macro +mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_WR_XNACK0 = 0x0045 # macro +mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_WR_XNACK1 = 0x0046 # macro +mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_TIMEOUT = 0x0047 # macro +mmSDMA0_UTCL1_TIMEOUT_BASE_IDX = 0 # macro +mmSDMA0_UTCL1_PAGE = 0x0048 # macro +mmSDMA0_UTCL1_PAGE_BASE_IDX = 0 # macro +mmSDMA0_RELAX_ORDERING_LUT = 0x004a # macro +mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro +mmSDMA0_CHICKEN_BITS_2 = 0x004b # macro +mmSDMA0_CHICKEN_BITS_2_BASE_IDX = 0 # macro +mmSDMA0_STATUS3_REG = 0x004c # macro +mmSDMA0_STATUS3_REG_BASE_IDX = 0 # macro +mmSDMA0_PHYSICAL_ADDR_LO = 0x004d # macro +mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_PHYSICAL_ADDR_HI = 0x004e # macro +mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_PHASE2_QUANTUM = 0x004f # macro +mmSDMA0_PHASE2_QUANTUM_BASE_IDX = 0 # macro +mmSDMA0_ERROR_LOG = 0x0050 # macro +mmSDMA0_ERROR_LOG_BASE_IDX = 0 # macro +mmSDMA0_PUB_DUMMY_REG0 = 0x0051 # macro +mmSDMA0_PUB_DUMMY_REG0_BASE_IDX = 0 # macro +mmSDMA0_PUB_DUMMY_REG1 = 0x0052 # macro +mmSDMA0_PUB_DUMMY_REG1_BASE_IDX = 0 # macro +mmSDMA0_PUB_DUMMY_REG2 = 0x0053 # macro +mmSDMA0_PUB_DUMMY_REG2_BASE_IDX = 0 # macro +mmSDMA0_PUB_DUMMY_REG3 = 0x0054 # macro +mmSDMA0_PUB_DUMMY_REG3_BASE_IDX = 0 # macro +mmSDMA0_F32_COUNTER = 0x0055 # macro +mmSDMA0_F32_COUNTER_BASE_IDX = 0 # macro +mmSDMA0_CRD_CNTL = 0x005b # macro +mmSDMA0_CRD_CNTL_BASE_IDX = 0 # macro +mmSDMA0_AQL_STATUS = 0x005f # macro +mmSDMA0_AQL_STATUS_BASE_IDX = 0 # macro +mmSDMA0_EA_DBIT_ADDR_DATA = 0x0060 # macro +mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro +mmSDMA0_EA_DBIT_ADDR_INDEX = 0x0061 # macro +mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro +mmSDMA0_TLBI_GCR_CNTL = 0x0062 # macro +mmSDMA0_TLBI_GCR_CNTL_BASE_IDX = 0 # macro +mmSDMA0_TILING_CONFIG = 0x0063 # macro +mmSDMA0_TILING_CONFIG_BASE_IDX = 0 # macro +mmSDMA0_INT_STATUS = 0x0070 # macro +mmSDMA0_INT_STATUS_BASE_IDX = 0 # macro +mmSDMA0_HOLE_ADDR_LO = 0x0072 # macro +mmSDMA0_HOLE_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_HOLE_ADDR_HI = 0x0073 # macro +mmSDMA0_HOLE_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_CLOCK_GATING_REG = 0x0075 # macro +mmSDMA0_CLOCK_GATING_REG_BASE_IDX = 0 # macro +mmSDMA0_STATUS4_REG = 0x0076 # macro +mmSDMA0_STATUS4_REG_BASE_IDX = 0 # macro +mmSDMA0_SCRATCH_RAM_DATA = 0x0077 # macro +mmSDMA0_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro +mmSDMA0_SCRATCH_RAM_ADDR = 0x0078 # macro +mmSDMA0_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro +mmSDMA0_TIMESTAMP_CNTL = 0x0079 # macro +mmSDMA0_TIMESTAMP_CNTL_BASE_IDX = 0 # macro +mmSDMA0_STATUS5_REG = 0x007a # macro +mmSDMA0_STATUS5_REG_BASE_IDX = 0 # macro +mmSDMA0_QUEUE_RESET_REQ = 0x007b # macro +mmSDMA0_QUEUE_RESET_REQ_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_CNTL = 0x0080 # macro +mmSDMA0_GFX_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_BASE = 0x0081 # macro +mmSDMA0_GFX_RB_BASE_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_BASE_HI = 0x0082 # macro +mmSDMA0_GFX_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_RPTR = 0x0083 # macro +mmSDMA0_GFX_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_RPTR_HI = 0x0084 # macro +mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_WPTR = 0x0085 # macro +mmSDMA0_GFX_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_WPTR_HI = 0x0086 # macro +mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_WPTR_POLL_CNTL = 0x0087 # macro +mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_RPTR_ADDR_HI = 0x0088 # macro +mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_RPTR_ADDR_LO = 0x0089 # macro +mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_GFX_IB_CNTL = 0x008a # macro +mmSDMA0_GFX_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_GFX_IB_RPTR = 0x008b # macro +mmSDMA0_GFX_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_GFX_IB_OFFSET = 0x008c # macro +mmSDMA0_GFX_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_GFX_IB_BASE_LO = 0x008d # macro +mmSDMA0_GFX_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA0_GFX_IB_BASE_HI = 0x008e # macro +mmSDMA0_GFX_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_GFX_IB_SIZE = 0x008f # macro +mmSDMA0_GFX_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA0_GFX_SKIP_CNTL = 0x0090 # macro +mmSDMA0_GFX_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA0_GFX_CONTEXT_STATUS = 0x0091 # macro +mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA0_GFX_DOORBELL = 0x0092 # macro +mmSDMA0_GFX_DOORBELL_BASE_IDX = 0 # macro +mmSDMA0_GFX_CONTEXT_CNTL = 0x0093 # macro +mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX = 0 # macro +mmSDMA0_GFX_STATUS = 0x00a8 # macro +mmSDMA0_GFX_STATUS_BASE_IDX = 0 # macro +mmSDMA0_GFX_DOORBELL_LOG = 0x00a9 # macro +mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA0_GFX_WATERMARK = 0x00aa # macro +mmSDMA0_GFX_WATERMARK_BASE_IDX = 0 # macro +mmSDMA0_GFX_DOORBELL_OFFSET = 0x00ab # macro +mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_GFX_CSA_ADDR_LO = 0x00ac # macro +mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_GFX_CSA_ADDR_HI = 0x00ad # macro +mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_GFX_IB_SUB_REMAIN = 0x00af # macro +mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA0_GFX_PREEMPT = 0x00b0 # macro +mmSDMA0_GFX_PREEMPT_BASE_IDX = 0 # macro +mmSDMA0_GFX_DUMMY_REG = 0x00b1 # macro +mmSDMA0_GFX_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI = 0x00b2 # macro +mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO = 0x00b3 # macro +mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_GFX_RB_AQL_CNTL = 0x00b4 # macro +mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_GFX_MINOR_PTR_UPDATE = 0x00b5 # macro +mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA0_GFX_MIDCMD_DATA0 = 0x00c0 # macro +mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA0_GFX_MIDCMD_DATA1 = 0x00c1 # macro +mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA0_GFX_MIDCMD_DATA2 = 0x00c2 # macro +mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA0_GFX_MIDCMD_DATA3 = 0x00c3 # macro +mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA0_GFX_MIDCMD_DATA4 = 0x00c4 # macro +mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA0_GFX_MIDCMD_DATA5 = 0x00c5 # macro +mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA0_GFX_MIDCMD_DATA6 = 0x00c6 # macro +mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA0_GFX_MIDCMD_DATA7 = 0x00c7 # macro +mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA0_GFX_MIDCMD_DATA8 = 0x00c8 # macro +mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA0_GFX_MIDCMD_DATA9 = 0x00c9 # macro +mmSDMA0_GFX_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA0_GFX_MIDCMD_DATA10 = 0x00ca # macro +mmSDMA0_GFX_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA0_GFX_MIDCMD_CNTL = 0x00cb # macro +mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_CNTL = 0x00d8 # macro +mmSDMA0_PAGE_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_BASE = 0x00d9 # macro +mmSDMA0_PAGE_RB_BASE_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_BASE_HI = 0x00da # macro +mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_RPTR = 0x00db # macro +mmSDMA0_PAGE_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_RPTR_HI = 0x00dc # macro +mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_WPTR = 0x00dd # macro +mmSDMA0_PAGE_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_WPTR_HI = 0x00de # macro +mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_WPTR_POLL_CNTL = 0x00df # macro +mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_RPTR_ADDR_HI = 0x00e0 # macro +mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_RPTR_ADDR_LO = 0x00e1 # macro +mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_PAGE_IB_CNTL = 0x00e2 # macro +mmSDMA0_PAGE_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_PAGE_IB_RPTR = 0x00e3 # macro +mmSDMA0_PAGE_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_PAGE_IB_OFFSET = 0x00e4 # macro +mmSDMA0_PAGE_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_PAGE_IB_BASE_LO = 0x00e5 # macro +mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA0_PAGE_IB_BASE_HI = 0x00e6 # macro +mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_PAGE_IB_SIZE = 0x00e7 # macro +mmSDMA0_PAGE_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA0_PAGE_SKIP_CNTL = 0x00e8 # macro +mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA0_PAGE_CONTEXT_STATUS = 0x00e9 # macro +mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA0_PAGE_DOORBELL = 0x00ea # macro +mmSDMA0_PAGE_DOORBELL_BASE_IDX = 0 # macro +mmSDMA0_PAGE_STATUS = 0x0100 # macro +mmSDMA0_PAGE_STATUS_BASE_IDX = 0 # macro +mmSDMA0_PAGE_DOORBELL_LOG = 0x0101 # macro +mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA0_PAGE_WATERMARK = 0x0102 # macro +mmSDMA0_PAGE_WATERMARK_BASE_IDX = 0 # macro +mmSDMA0_PAGE_DOORBELL_OFFSET = 0x0103 # macro +mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_PAGE_CSA_ADDR_LO = 0x0104 # macro +mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_PAGE_CSA_ADDR_HI = 0x0105 # macro +mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_PAGE_IB_SUB_REMAIN = 0x0107 # macro +mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA0_PAGE_PREEMPT = 0x0108 # macro +mmSDMA0_PAGE_PREEMPT_BASE_IDX = 0 # macro +mmSDMA0_PAGE_DUMMY_REG = 0x0109 # macro +mmSDMA0_PAGE_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI = 0x010a # macro +mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO = 0x010b # macro +mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_PAGE_RB_AQL_CNTL = 0x010c # macro +mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MINOR_PTR_UPDATE = 0x010d # macro +mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MIDCMD_DATA0 = 0x0118 # macro +mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MIDCMD_DATA1 = 0x0119 # macro +mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MIDCMD_DATA2 = 0x011a # macro +mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MIDCMD_DATA3 = 0x011b # macro +mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MIDCMD_DATA4 = 0x011c # macro +mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MIDCMD_DATA5 = 0x011d # macro +mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MIDCMD_DATA6 = 0x011e # macro +mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MIDCMD_DATA7 = 0x011f # macro +mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MIDCMD_DATA8 = 0x0120 # macro +mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MIDCMD_DATA9 = 0x0121 # macro +mmSDMA0_PAGE_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MIDCMD_DATA10 = 0x0122 # macro +mmSDMA0_PAGE_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA0_PAGE_MIDCMD_CNTL = 0x0123 # macro +mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_CNTL = 0x0130 # macro +mmSDMA0_RLC0_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_BASE = 0x0131 # macro +mmSDMA0_RLC0_RB_BASE_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_BASE_HI = 0x0132 # macro +mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_RPTR = 0x0133 # macro +mmSDMA0_RLC0_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_RPTR_HI = 0x0134 # macro +mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_WPTR = 0x0135 # macro +mmSDMA0_RLC0_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_WPTR_HI = 0x0136 # macro +mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_WPTR_POLL_CNTL = 0x0137 # macro +mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_RPTR_ADDR_HI = 0x0138 # macro +mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_RPTR_ADDR_LO = 0x0139 # macro +mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC0_IB_CNTL = 0x013a # macro +mmSDMA0_RLC0_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC0_IB_RPTR = 0x013b # macro +mmSDMA0_RLC0_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC0_IB_OFFSET = 0x013c # macro +mmSDMA0_RLC0_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC0_IB_BASE_LO = 0x013d # macro +mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC0_IB_BASE_HI = 0x013e # macro +mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC0_IB_SIZE = 0x013f # macro +mmSDMA0_RLC0_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA0_RLC0_SKIP_CNTL = 0x0140 # macro +mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC0_CONTEXT_STATUS = 0x0141 # macro +mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC0_DOORBELL = 0x0142 # macro +mmSDMA0_RLC0_DOORBELL_BASE_IDX = 0 # macro +mmSDMA0_RLC0_STATUS = 0x0158 # macro +mmSDMA0_RLC0_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC0_DOORBELL_LOG = 0x0159 # macro +mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA0_RLC0_WATERMARK = 0x015a # macro +mmSDMA0_RLC0_WATERMARK_BASE_IDX = 0 # macro +mmSDMA0_RLC0_DOORBELL_OFFSET = 0x015b # macro +mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC0_CSA_ADDR_LO = 0x015c # macro +mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC0_CSA_ADDR_HI = 0x015d # macro +mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC0_IB_SUB_REMAIN = 0x015f # macro +mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA0_RLC0_PREEMPT = 0x0160 # macro +mmSDMA0_RLC0_PREEMPT_BASE_IDX = 0 # macro +mmSDMA0_RLC0_DUMMY_REG = 0x0161 # macro +mmSDMA0_RLC0_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI = 0x0162 # macro +mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO = 0x0163 # macro +mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC0_RB_AQL_CNTL = 0x0164 # macro +mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MINOR_PTR_UPDATE = 0x0165 # macro +mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MIDCMD_DATA0 = 0x0170 # macro +mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MIDCMD_DATA1 = 0x0171 # macro +mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MIDCMD_DATA2 = 0x0172 # macro +mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MIDCMD_DATA3 = 0x0173 # macro +mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MIDCMD_DATA4 = 0x0174 # macro +mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MIDCMD_DATA5 = 0x0175 # macro +mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MIDCMD_DATA6 = 0x0176 # macro +mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MIDCMD_DATA7 = 0x0177 # macro +mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MIDCMD_DATA8 = 0x0178 # macro +mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MIDCMD_DATA9 = 0x0179 # macro +mmSDMA0_RLC0_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MIDCMD_DATA10 = 0x017a # macro +mmSDMA0_RLC0_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA0_RLC0_MIDCMD_CNTL = 0x017b # macro +mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_CNTL = 0x0188 # macro +mmSDMA0_RLC1_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_BASE = 0x0189 # macro +mmSDMA0_RLC1_RB_BASE_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_BASE_HI = 0x018a # macro +mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_RPTR = 0x018b # macro +mmSDMA0_RLC1_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_RPTR_HI = 0x018c # macro +mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_WPTR = 0x018d # macro +mmSDMA0_RLC1_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_WPTR_HI = 0x018e # macro +mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_WPTR_POLL_CNTL = 0x018f # macro +mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_RPTR_ADDR_HI = 0x0190 # macro +mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_RPTR_ADDR_LO = 0x0191 # macro +mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC1_IB_CNTL = 0x0192 # macro +mmSDMA0_RLC1_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC1_IB_RPTR = 0x0193 # macro +mmSDMA0_RLC1_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC1_IB_OFFSET = 0x0194 # macro +mmSDMA0_RLC1_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC1_IB_BASE_LO = 0x0195 # macro +mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC1_IB_BASE_HI = 0x0196 # macro +mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC1_IB_SIZE = 0x0197 # macro +mmSDMA0_RLC1_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA0_RLC1_SKIP_CNTL = 0x0198 # macro +mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC1_CONTEXT_STATUS = 0x0199 # macro +mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC1_DOORBELL = 0x019a # macro +mmSDMA0_RLC1_DOORBELL_BASE_IDX = 0 # macro +mmSDMA0_RLC1_STATUS = 0x01b0 # macro +mmSDMA0_RLC1_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC1_DOORBELL_LOG = 0x01b1 # macro +mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA0_RLC1_WATERMARK = 0x01b2 # macro +mmSDMA0_RLC1_WATERMARK_BASE_IDX = 0 # macro +mmSDMA0_RLC1_DOORBELL_OFFSET = 0x01b3 # macro +mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC1_CSA_ADDR_LO = 0x01b4 # macro +mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC1_CSA_ADDR_HI = 0x01b5 # macro +mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC1_IB_SUB_REMAIN = 0x01b7 # macro +mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA0_RLC1_PREEMPT = 0x01b8 # macro +mmSDMA0_RLC1_PREEMPT_BASE_IDX = 0 # macro +mmSDMA0_RLC1_DUMMY_REG = 0x01b9 # macro +mmSDMA0_RLC1_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI = 0x01ba # macro +mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO = 0x01bb # macro +mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC1_RB_AQL_CNTL = 0x01bc # macro +mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MINOR_PTR_UPDATE = 0x01bd # macro +mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MIDCMD_DATA0 = 0x01c8 # macro +mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MIDCMD_DATA1 = 0x01c9 # macro +mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MIDCMD_DATA2 = 0x01ca # macro +mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MIDCMD_DATA3 = 0x01cb # macro +mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MIDCMD_DATA4 = 0x01cc # macro +mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MIDCMD_DATA5 = 0x01cd # macro +mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MIDCMD_DATA6 = 0x01ce # macro +mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MIDCMD_DATA7 = 0x01cf # macro +mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MIDCMD_DATA8 = 0x01d0 # macro +mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MIDCMD_DATA9 = 0x01d1 # macro +mmSDMA0_RLC1_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MIDCMD_DATA10 = 0x01d2 # macro +mmSDMA0_RLC1_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA0_RLC1_MIDCMD_CNTL = 0x01d3 # macro +mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_CNTL = 0x01e0 # macro +mmSDMA0_RLC2_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_BASE = 0x01e1 # macro +mmSDMA0_RLC2_RB_BASE_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_BASE_HI = 0x01e2 # macro +mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_RPTR = 0x01e3 # macro +mmSDMA0_RLC2_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_RPTR_HI = 0x01e4 # macro +mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_WPTR = 0x01e5 # macro +mmSDMA0_RLC2_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_WPTR_HI = 0x01e6 # macro +mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_WPTR_POLL_CNTL = 0x01e7 # macro +mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_RPTR_ADDR_HI = 0x01e8 # macro +mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_RPTR_ADDR_LO = 0x01e9 # macro +mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC2_IB_CNTL = 0x01ea # macro +mmSDMA0_RLC2_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC2_IB_RPTR = 0x01eb # macro +mmSDMA0_RLC2_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC2_IB_OFFSET = 0x01ec # macro +mmSDMA0_RLC2_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC2_IB_BASE_LO = 0x01ed # macro +mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC2_IB_BASE_HI = 0x01ee # macro +mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC2_IB_SIZE = 0x01ef # macro +mmSDMA0_RLC2_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA0_RLC2_SKIP_CNTL = 0x01f0 # macro +mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC2_CONTEXT_STATUS = 0x01f1 # macro +mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC2_DOORBELL = 0x01f2 # macro +mmSDMA0_RLC2_DOORBELL_BASE_IDX = 0 # macro +mmSDMA0_RLC2_STATUS = 0x0208 # macro +mmSDMA0_RLC2_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC2_DOORBELL_LOG = 0x0209 # macro +mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA0_RLC2_WATERMARK = 0x020a # macro +mmSDMA0_RLC2_WATERMARK_BASE_IDX = 0 # macro +mmSDMA0_RLC2_DOORBELL_OFFSET = 0x020b # macro +mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC2_CSA_ADDR_LO = 0x020c # macro +mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC2_CSA_ADDR_HI = 0x020d # macro +mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC2_IB_SUB_REMAIN = 0x020f # macro +mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA0_RLC2_PREEMPT = 0x0210 # macro +mmSDMA0_RLC2_PREEMPT_BASE_IDX = 0 # macro +mmSDMA0_RLC2_DUMMY_REG = 0x0211 # macro +mmSDMA0_RLC2_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI = 0x0212 # macro +mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO = 0x0213 # macro +mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC2_RB_AQL_CNTL = 0x0214 # macro +mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MINOR_PTR_UPDATE = 0x0215 # macro +mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MIDCMD_DATA0 = 0x0220 # macro +mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MIDCMD_DATA1 = 0x0221 # macro +mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MIDCMD_DATA2 = 0x0222 # macro +mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MIDCMD_DATA3 = 0x0223 # macro +mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MIDCMD_DATA4 = 0x0224 # macro +mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MIDCMD_DATA5 = 0x0225 # macro +mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MIDCMD_DATA6 = 0x0226 # macro +mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MIDCMD_DATA7 = 0x0227 # macro +mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MIDCMD_DATA8 = 0x0228 # macro +mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MIDCMD_DATA9 = 0x0229 # macro +mmSDMA0_RLC2_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MIDCMD_DATA10 = 0x022a # macro +mmSDMA0_RLC2_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA0_RLC2_MIDCMD_CNTL = 0x022b # macro +mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_CNTL = 0x0238 # macro +mmSDMA0_RLC3_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_BASE = 0x0239 # macro +mmSDMA0_RLC3_RB_BASE_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_BASE_HI = 0x023a # macro +mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_RPTR = 0x023b # macro +mmSDMA0_RLC3_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_RPTR_HI = 0x023c # macro +mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_WPTR = 0x023d # macro +mmSDMA0_RLC3_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_WPTR_HI = 0x023e # macro +mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_WPTR_POLL_CNTL = 0x023f # macro +mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_RPTR_ADDR_HI = 0x0240 # macro +mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_RPTR_ADDR_LO = 0x0241 # macro +mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC3_IB_CNTL = 0x0242 # macro +mmSDMA0_RLC3_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC3_IB_RPTR = 0x0243 # macro +mmSDMA0_RLC3_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC3_IB_OFFSET = 0x0244 # macro +mmSDMA0_RLC3_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC3_IB_BASE_LO = 0x0245 # macro +mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC3_IB_BASE_HI = 0x0246 # macro +mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC3_IB_SIZE = 0x0247 # macro +mmSDMA0_RLC3_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA0_RLC3_SKIP_CNTL = 0x0248 # macro +mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC3_CONTEXT_STATUS = 0x0249 # macro +mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC3_DOORBELL = 0x024a # macro +mmSDMA0_RLC3_DOORBELL_BASE_IDX = 0 # macro +mmSDMA0_RLC3_STATUS = 0x0260 # macro +mmSDMA0_RLC3_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC3_DOORBELL_LOG = 0x0261 # macro +mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA0_RLC3_WATERMARK = 0x0262 # macro +mmSDMA0_RLC3_WATERMARK_BASE_IDX = 0 # macro +mmSDMA0_RLC3_DOORBELL_OFFSET = 0x0263 # macro +mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC3_CSA_ADDR_LO = 0x0264 # macro +mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC3_CSA_ADDR_HI = 0x0265 # macro +mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC3_IB_SUB_REMAIN = 0x0267 # macro +mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA0_RLC3_PREEMPT = 0x0268 # macro +mmSDMA0_RLC3_PREEMPT_BASE_IDX = 0 # macro +mmSDMA0_RLC3_DUMMY_REG = 0x0269 # macro +mmSDMA0_RLC3_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI = 0x026a # macro +mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO = 0x026b # macro +mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC3_RB_AQL_CNTL = 0x026c # macro +mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MINOR_PTR_UPDATE = 0x026d # macro +mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MIDCMD_DATA0 = 0x0278 # macro +mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MIDCMD_DATA1 = 0x0279 # macro +mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MIDCMD_DATA2 = 0x027a # macro +mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MIDCMD_DATA3 = 0x027b # macro +mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MIDCMD_DATA4 = 0x027c # macro +mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MIDCMD_DATA5 = 0x027d # macro +mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MIDCMD_DATA6 = 0x027e # macro +mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MIDCMD_DATA7 = 0x027f # macro +mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MIDCMD_DATA8 = 0x0280 # macro +mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MIDCMD_DATA9 = 0x0281 # macro +mmSDMA0_RLC3_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MIDCMD_DATA10 = 0x0282 # macro +mmSDMA0_RLC3_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA0_RLC3_MIDCMD_CNTL = 0x0283 # macro +mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_CNTL = 0x0290 # macro +mmSDMA0_RLC4_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_BASE = 0x0291 # macro +mmSDMA0_RLC4_RB_BASE_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_BASE_HI = 0x0292 # macro +mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_RPTR = 0x0293 # macro +mmSDMA0_RLC4_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_RPTR_HI = 0x0294 # macro +mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_WPTR = 0x0295 # macro +mmSDMA0_RLC4_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_WPTR_HI = 0x0296 # macro +mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_WPTR_POLL_CNTL = 0x0297 # macro +mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_RPTR_ADDR_HI = 0x0298 # macro +mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_RPTR_ADDR_LO = 0x0299 # macro +mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC4_IB_CNTL = 0x029a # macro +mmSDMA0_RLC4_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC4_IB_RPTR = 0x029b # macro +mmSDMA0_RLC4_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC4_IB_OFFSET = 0x029c # macro +mmSDMA0_RLC4_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC4_IB_BASE_LO = 0x029d # macro +mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC4_IB_BASE_HI = 0x029e # macro +mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC4_IB_SIZE = 0x029f # macro +mmSDMA0_RLC4_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA0_RLC4_SKIP_CNTL = 0x02a0 # macro +mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC4_CONTEXT_STATUS = 0x02a1 # macro +mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC4_DOORBELL = 0x02a2 # macro +mmSDMA0_RLC4_DOORBELL_BASE_IDX = 0 # macro +mmSDMA0_RLC4_STATUS = 0x02b8 # macro +mmSDMA0_RLC4_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC4_DOORBELL_LOG = 0x02b9 # macro +mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA0_RLC4_WATERMARK = 0x02ba # macro +mmSDMA0_RLC4_WATERMARK_BASE_IDX = 0 # macro +mmSDMA0_RLC4_DOORBELL_OFFSET = 0x02bb # macro +mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC4_CSA_ADDR_LO = 0x02bc # macro +mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC4_CSA_ADDR_HI = 0x02bd # macro +mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC4_IB_SUB_REMAIN = 0x02bf # macro +mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA0_RLC4_PREEMPT = 0x02c0 # macro +mmSDMA0_RLC4_PREEMPT_BASE_IDX = 0 # macro +mmSDMA0_RLC4_DUMMY_REG = 0x02c1 # macro +mmSDMA0_RLC4_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI = 0x02c2 # macro +mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO = 0x02c3 # macro +mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC4_RB_AQL_CNTL = 0x02c4 # macro +mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MINOR_PTR_UPDATE = 0x02c5 # macro +mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MIDCMD_DATA0 = 0x02d0 # macro +mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MIDCMD_DATA1 = 0x02d1 # macro +mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MIDCMD_DATA2 = 0x02d2 # macro +mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MIDCMD_DATA3 = 0x02d3 # macro +mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MIDCMD_DATA4 = 0x02d4 # macro +mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MIDCMD_DATA5 = 0x02d5 # macro +mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MIDCMD_DATA6 = 0x02d6 # macro +mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MIDCMD_DATA7 = 0x02d7 # macro +mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MIDCMD_DATA8 = 0x02d8 # macro +mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MIDCMD_DATA9 = 0x02d9 # macro +mmSDMA0_RLC4_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MIDCMD_DATA10 = 0x02da # macro +mmSDMA0_RLC4_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA0_RLC4_MIDCMD_CNTL = 0x02db # macro +mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_CNTL = 0x02e8 # macro +mmSDMA0_RLC5_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_BASE = 0x02e9 # macro +mmSDMA0_RLC5_RB_BASE_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_BASE_HI = 0x02ea # macro +mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_RPTR = 0x02eb # macro +mmSDMA0_RLC5_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_RPTR_HI = 0x02ec # macro +mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_WPTR = 0x02ed # macro +mmSDMA0_RLC5_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_WPTR_HI = 0x02ee # macro +mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_WPTR_POLL_CNTL = 0x02ef # macro +mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_RPTR_ADDR_HI = 0x02f0 # macro +mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_RPTR_ADDR_LO = 0x02f1 # macro +mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC5_IB_CNTL = 0x02f2 # macro +mmSDMA0_RLC5_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC5_IB_RPTR = 0x02f3 # macro +mmSDMA0_RLC5_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC5_IB_OFFSET = 0x02f4 # macro +mmSDMA0_RLC5_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC5_IB_BASE_LO = 0x02f5 # macro +mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC5_IB_BASE_HI = 0x02f6 # macro +mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC5_IB_SIZE = 0x02f7 # macro +mmSDMA0_RLC5_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA0_RLC5_SKIP_CNTL = 0x02f8 # macro +mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC5_CONTEXT_STATUS = 0x02f9 # macro +mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC5_DOORBELL = 0x02fa # macro +mmSDMA0_RLC5_DOORBELL_BASE_IDX = 0 # macro +mmSDMA0_RLC5_STATUS = 0x0310 # macro +mmSDMA0_RLC5_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC5_DOORBELL_LOG = 0x0311 # macro +mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA0_RLC5_WATERMARK = 0x0312 # macro +mmSDMA0_RLC5_WATERMARK_BASE_IDX = 0 # macro +mmSDMA0_RLC5_DOORBELL_OFFSET = 0x0313 # macro +mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC5_CSA_ADDR_LO = 0x0314 # macro +mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC5_CSA_ADDR_HI = 0x0315 # macro +mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC5_IB_SUB_REMAIN = 0x0317 # macro +mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA0_RLC5_PREEMPT = 0x0318 # macro +mmSDMA0_RLC5_PREEMPT_BASE_IDX = 0 # macro +mmSDMA0_RLC5_DUMMY_REG = 0x0319 # macro +mmSDMA0_RLC5_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI = 0x031a # macro +mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO = 0x031b # macro +mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC5_RB_AQL_CNTL = 0x031c # macro +mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MINOR_PTR_UPDATE = 0x031d # macro +mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MIDCMD_DATA0 = 0x0328 # macro +mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MIDCMD_DATA1 = 0x0329 # macro +mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MIDCMD_DATA2 = 0x032a # macro +mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MIDCMD_DATA3 = 0x032b # macro +mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MIDCMD_DATA4 = 0x032c # macro +mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MIDCMD_DATA5 = 0x032d # macro +mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MIDCMD_DATA6 = 0x032e # macro +mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MIDCMD_DATA7 = 0x032f # macro +mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MIDCMD_DATA8 = 0x0330 # macro +mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MIDCMD_DATA9 = 0x0331 # macro +mmSDMA0_RLC5_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MIDCMD_DATA10 = 0x0332 # macro +mmSDMA0_RLC5_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA0_RLC5_MIDCMD_CNTL = 0x0333 # macro +mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_CNTL = 0x0340 # macro +mmSDMA0_RLC6_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_BASE = 0x0341 # macro +mmSDMA0_RLC6_RB_BASE_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_BASE_HI = 0x0342 # macro +mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_RPTR = 0x0343 # macro +mmSDMA0_RLC6_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_RPTR_HI = 0x0344 # macro +mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_WPTR = 0x0345 # macro +mmSDMA0_RLC6_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_WPTR_HI = 0x0346 # macro +mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_WPTR_POLL_CNTL = 0x0347 # macro +mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_RPTR_ADDR_HI = 0x0348 # macro +mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_RPTR_ADDR_LO = 0x0349 # macro +mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC6_IB_CNTL = 0x034a # macro +mmSDMA0_RLC6_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC6_IB_RPTR = 0x034b # macro +mmSDMA0_RLC6_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC6_IB_OFFSET = 0x034c # macro +mmSDMA0_RLC6_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC6_IB_BASE_LO = 0x034d # macro +mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC6_IB_BASE_HI = 0x034e # macro +mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC6_IB_SIZE = 0x034f # macro +mmSDMA0_RLC6_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA0_RLC6_SKIP_CNTL = 0x0350 # macro +mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC6_CONTEXT_STATUS = 0x0351 # macro +mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC6_DOORBELL = 0x0352 # macro +mmSDMA0_RLC6_DOORBELL_BASE_IDX = 0 # macro +mmSDMA0_RLC6_STATUS = 0x0368 # macro +mmSDMA0_RLC6_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC6_DOORBELL_LOG = 0x0369 # macro +mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA0_RLC6_WATERMARK = 0x036a # macro +mmSDMA0_RLC6_WATERMARK_BASE_IDX = 0 # macro +mmSDMA0_RLC6_DOORBELL_OFFSET = 0x036b # macro +mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC6_CSA_ADDR_LO = 0x036c # macro +mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC6_CSA_ADDR_HI = 0x036d # macro +mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC6_IB_SUB_REMAIN = 0x036f # macro +mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA0_RLC6_PREEMPT = 0x0370 # macro +mmSDMA0_RLC6_PREEMPT_BASE_IDX = 0 # macro +mmSDMA0_RLC6_DUMMY_REG = 0x0371 # macro +mmSDMA0_RLC6_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI = 0x0372 # macro +mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO = 0x0373 # macro +mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC6_RB_AQL_CNTL = 0x0374 # macro +mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MINOR_PTR_UPDATE = 0x0375 # macro +mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MIDCMD_DATA0 = 0x0380 # macro +mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MIDCMD_DATA1 = 0x0381 # macro +mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MIDCMD_DATA2 = 0x0382 # macro +mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MIDCMD_DATA3 = 0x0383 # macro +mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MIDCMD_DATA4 = 0x0384 # macro +mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MIDCMD_DATA5 = 0x0385 # macro +mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MIDCMD_DATA6 = 0x0386 # macro +mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MIDCMD_DATA7 = 0x0387 # macro +mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MIDCMD_DATA8 = 0x0388 # macro +mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MIDCMD_DATA9 = 0x0389 # macro +mmSDMA0_RLC6_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MIDCMD_DATA10 = 0x038a # macro +mmSDMA0_RLC6_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA0_RLC6_MIDCMD_CNTL = 0x038b # macro +mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_CNTL = 0x0398 # macro +mmSDMA0_RLC7_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_BASE = 0x0399 # macro +mmSDMA0_RLC7_RB_BASE_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_BASE_HI = 0x039a # macro +mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_RPTR = 0x039b # macro +mmSDMA0_RLC7_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_RPTR_HI = 0x039c # macro +mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_WPTR = 0x039d # macro +mmSDMA0_RLC7_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_WPTR_HI = 0x039e # macro +mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_WPTR_POLL_CNTL = 0x039f # macro +mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_RPTR_ADDR_HI = 0x03a0 # macro +mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_RPTR_ADDR_LO = 0x03a1 # macro +mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC7_IB_CNTL = 0x03a2 # macro +mmSDMA0_RLC7_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC7_IB_RPTR = 0x03a3 # macro +mmSDMA0_RLC7_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA0_RLC7_IB_OFFSET = 0x03a4 # macro +mmSDMA0_RLC7_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC7_IB_BASE_LO = 0x03a5 # macro +mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC7_IB_BASE_HI = 0x03a6 # macro +mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC7_IB_SIZE = 0x03a7 # macro +mmSDMA0_RLC7_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA0_RLC7_SKIP_CNTL = 0x03a8 # macro +mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC7_CONTEXT_STATUS = 0x03a9 # macro +mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC7_DOORBELL = 0x03aa # macro +mmSDMA0_RLC7_DOORBELL_BASE_IDX = 0 # macro +mmSDMA0_RLC7_STATUS = 0x03c0 # macro +mmSDMA0_RLC7_STATUS_BASE_IDX = 0 # macro +mmSDMA0_RLC7_DOORBELL_LOG = 0x03c1 # macro +mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA0_RLC7_WATERMARK = 0x03c2 # macro +mmSDMA0_RLC7_WATERMARK_BASE_IDX = 0 # macro +mmSDMA0_RLC7_DOORBELL_OFFSET = 0x03c3 # macro +mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA0_RLC7_CSA_ADDR_LO = 0x03c4 # macro +mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC7_CSA_ADDR_HI = 0x03c5 # macro +mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC7_IB_SUB_REMAIN = 0x03c7 # macro +mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA0_RLC7_PREEMPT = 0x03c8 # macro +mmSDMA0_RLC7_PREEMPT_BASE_IDX = 0 # macro +mmSDMA0_RLC7_DUMMY_REG = 0x03c9 # macro +mmSDMA0_RLC7_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI = 0x03ca # macro +mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO = 0x03cb # macro +mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA0_RLC7_RB_AQL_CNTL = 0x03cc # macro +mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MINOR_PTR_UPDATE = 0x03cd # macro +mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MIDCMD_DATA0 = 0x03d8 # macro +mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MIDCMD_DATA1 = 0x03d9 # macro +mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MIDCMD_DATA2 = 0x03da # macro +mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MIDCMD_DATA3 = 0x03db # macro +mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MIDCMD_DATA4 = 0x03dc # macro +mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MIDCMD_DATA5 = 0x03dd # macro +mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MIDCMD_DATA6 = 0x03de # macro +mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MIDCMD_DATA7 = 0x03df # macro +mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MIDCMD_DATA8 = 0x03e0 # macro +mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MIDCMD_DATA9 = 0x03e1 # macro +mmSDMA0_RLC7_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MIDCMD_DATA10 = 0x03e2 # macro +mmSDMA0_RLC7_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA0_RLC7_MIDCMD_CNTL = 0x03e3 # macro +mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA1_DEC_START = 0x0600 # macro +mmSDMA1_DEC_START_BASE_IDX = 0 # macro +mmSDMA1_GLOBAL_TIMESTAMP_LO = 0x060f # macro +mmSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX = 0 # macro +mmSDMA1_GLOBAL_TIMESTAMP_HI = 0x0610 # macro +mmSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX = 0 # macro +mmSDMA1_PG_CNTL = 0x0616 # macro +mmSDMA1_PG_CNTL_BASE_IDX = 0 # macro +mmSDMA1_PG_CTX_LO = 0x0617 # macro +mmSDMA1_PG_CTX_LO_BASE_IDX = 0 # macro +mmSDMA1_PG_CTX_HI = 0x0618 # macro +mmSDMA1_PG_CTX_HI_BASE_IDX = 0 # macro +mmSDMA1_PG_CTX_CNTL = 0x0619 # macro +mmSDMA1_PG_CTX_CNTL_BASE_IDX = 0 # macro +mmSDMA1_POWER_CNTL = 0x061a # macro +mmSDMA1_POWER_CNTL_BASE_IDX = 0 # macro +mmSDMA1_CLK_CTRL = 0x061b # macro +mmSDMA1_CLK_CTRL_BASE_IDX = 0 # macro +mmSDMA1_CNTL = 0x061c # macro +mmSDMA1_CNTL_BASE_IDX = 0 # macro +mmSDMA1_CHICKEN_BITS = 0x061d # macro +mmSDMA1_CHICKEN_BITS_BASE_IDX = 0 # macro +mmSDMA1_GB_ADDR_CONFIG = 0x061e # macro +mmSDMA1_GB_ADDR_CONFIG_BASE_IDX = 0 # macro +mmSDMA1_GB_ADDR_CONFIG_READ = 0x061f # macro +mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro +mmSDMA1_RB_RPTR_FETCH_HI = 0x0620 # macro +mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX = 0 # macro +mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL = 0x0621 # macro +mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RB_RPTR_FETCH = 0x0622 # macro +mmSDMA1_RB_RPTR_FETCH_BASE_IDX = 0 # macro +mmSDMA1_IB_OFFSET_FETCH = 0x0623 # macro +mmSDMA1_IB_OFFSET_FETCH_BASE_IDX = 0 # macro +mmSDMA1_PROGRAM = 0x0624 # macro +mmSDMA1_PROGRAM_BASE_IDX = 0 # macro +mmSDMA1_STATUS_REG = 0x0625 # macro +mmSDMA1_STATUS_REG_BASE_IDX = 0 # macro +mmSDMA1_STATUS1_REG = 0x0626 # macro +mmSDMA1_STATUS1_REG_BASE_IDX = 0 # macro +mmSDMA1_RD_BURST_CNTL = 0x0627 # macro +mmSDMA1_RD_BURST_CNTL_BASE_IDX = 0 # macro +mmSDMA1_HBM_PAGE_CONFIG = 0x0628 # macro +mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX = 0 # macro +mmSDMA1_UCODE_CHECKSUM = 0x0629 # macro +mmSDMA1_UCODE_CHECKSUM_BASE_IDX = 0 # macro +mmSDMA1_F32_CNTL = 0x062a # macro +mmSDMA1_F32_CNTL_BASE_IDX = 0 # macro +mmSDMA1_FREEZE = 0x062b # macro +mmSDMA1_FREEZE_BASE_IDX = 0 # macro +mmSDMA1_PHASE0_QUANTUM = 0x062c # macro +mmSDMA1_PHASE0_QUANTUM_BASE_IDX = 0 # macro +mmSDMA1_PHASE1_QUANTUM = 0x062d # macro +mmSDMA1_PHASE1_QUANTUM_BASE_IDX = 0 # macro +mmSDMA1_EDC_CONFIG = 0x0632 # macro +mmSDMA1_EDC_CONFIG_BASE_IDX = 0 # macro +mmSDMA1_BA_THRESHOLD = 0x0633 # macro +mmSDMA1_BA_THRESHOLD_BASE_IDX = 0 # macro +mmSDMA1_ID = 0x0634 # macro +mmSDMA1_ID_BASE_IDX = 0 # macro +mmSDMA1_VERSION = 0x0635 # macro +mmSDMA1_VERSION_BASE_IDX = 0 # macro +mmSDMA1_EDC_COUNTER = 0x0636 # macro +mmSDMA1_EDC_COUNTER_BASE_IDX = 0 # macro +mmSDMA1_EDC_COUNTER_CLEAR = 0x0637 # macro +mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX = 0 # macro +mmSDMA1_STATUS2_REG = 0x0638 # macro +mmSDMA1_STATUS2_REG_BASE_IDX = 0 # macro +mmSDMA1_ATOMIC_CNTL = 0x0639 # macro +mmSDMA1_ATOMIC_CNTL_BASE_IDX = 0 # macro +mmSDMA1_ATOMIC_PREOP_LO = 0x063a # macro +mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX = 0 # macro +mmSDMA1_ATOMIC_PREOP_HI = 0x063b # macro +mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_CNTL = 0x063c # macro +mmSDMA1_UTCL1_CNTL_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_WATERMK = 0x063d # macro +mmSDMA1_UTCL1_WATERMK_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_RD_STATUS = 0x063e # macro +mmSDMA1_UTCL1_RD_STATUS_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_WR_STATUS = 0x063f # macro +mmSDMA1_UTCL1_WR_STATUS_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_INV0 = 0x0640 # macro +mmSDMA1_UTCL1_INV0_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_INV1 = 0x0641 # macro +mmSDMA1_UTCL1_INV1_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_INV2 = 0x0642 # macro +mmSDMA1_UTCL1_INV2_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_RD_XNACK0 = 0x0643 # macro +mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_RD_XNACK1 = 0x0644 # macro +mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_WR_XNACK0 = 0x0645 # macro +mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_WR_XNACK1 = 0x0646 # macro +mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_TIMEOUT = 0x0647 # macro +mmSDMA1_UTCL1_TIMEOUT_BASE_IDX = 0 # macro +mmSDMA1_UTCL1_PAGE = 0x0648 # macro +mmSDMA1_UTCL1_PAGE_BASE_IDX = 0 # macro +mmSDMA1_RELAX_ORDERING_LUT = 0x064a # macro +mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX = 0 # macro +mmSDMA1_CHICKEN_BITS_2 = 0x064b # macro +mmSDMA1_CHICKEN_BITS_2_BASE_IDX = 0 # macro +mmSDMA1_STATUS3_REG = 0x064c # macro +mmSDMA1_STATUS3_REG_BASE_IDX = 0 # macro +mmSDMA1_PHYSICAL_ADDR_LO = 0x064d # macro +mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_PHYSICAL_ADDR_HI = 0x064e # macro +mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_PHASE2_QUANTUM = 0x064f # macro +mmSDMA1_PHASE2_QUANTUM_BASE_IDX = 0 # macro +mmSDMA1_ERROR_LOG = 0x0650 # macro +mmSDMA1_ERROR_LOG_BASE_IDX = 0 # macro +mmSDMA1_PUB_DUMMY_REG0 = 0x0651 # macro +mmSDMA1_PUB_DUMMY_REG0_BASE_IDX = 0 # macro +mmSDMA1_PUB_DUMMY_REG1 = 0x0652 # macro +mmSDMA1_PUB_DUMMY_REG1_BASE_IDX = 0 # macro +mmSDMA1_PUB_DUMMY_REG2 = 0x0653 # macro +mmSDMA1_PUB_DUMMY_REG2_BASE_IDX = 0 # macro +mmSDMA1_PUB_DUMMY_REG3 = 0x0654 # macro +mmSDMA1_PUB_DUMMY_REG3_BASE_IDX = 0 # macro +mmSDMA1_F32_COUNTER = 0x0655 # macro +mmSDMA1_F32_COUNTER_BASE_IDX = 0 # macro +mmSDMA1_CRD_CNTL = 0x065b # macro +mmSDMA1_CRD_CNTL_BASE_IDX = 0 # macro +mmSDMA1_AQL_STATUS = 0x065f # macro +mmSDMA1_AQL_STATUS_BASE_IDX = 0 # macro +mmSDMA1_EA_DBIT_ADDR_DATA = 0x0660 # macro +mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX = 0 # macro +mmSDMA1_EA_DBIT_ADDR_INDEX = 0x0661 # macro +mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX = 0 # macro +mmSDMA1_TLBI_GCR_CNTL = 0x0662 # macro +mmSDMA1_TLBI_GCR_CNTL_BASE_IDX = 0 # macro +mmSDMA1_TILING_CONFIG = 0x0663 # macro +mmSDMA1_TILING_CONFIG_BASE_IDX = 0 # macro +mmSDMA1_INT_STATUS = 0x0670 # macro +mmSDMA1_INT_STATUS_BASE_IDX = 0 # macro +mmSDMA1_HOLE_ADDR_LO = 0x0672 # macro +mmSDMA1_HOLE_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_HOLE_ADDR_HI = 0x0673 # macro +mmSDMA1_HOLE_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_CLOCK_GATING_REG = 0x0675 # macro +mmSDMA1_CLOCK_GATING_REG_BASE_IDX = 0 # macro +mmSDMA1_STATUS4_REG = 0x0676 # macro +mmSDMA1_STATUS4_REG_BASE_IDX = 0 # macro +mmSDMA1_SCRATCH_RAM_DATA = 0x0677 # macro +mmSDMA1_SCRATCH_RAM_DATA_BASE_IDX = 0 # macro +mmSDMA1_SCRATCH_RAM_ADDR = 0x0678 # macro +mmSDMA1_SCRATCH_RAM_ADDR_BASE_IDX = 0 # macro +mmSDMA1_TIMESTAMP_CNTL = 0x0679 # macro +mmSDMA1_TIMESTAMP_CNTL_BASE_IDX = 0 # macro +mmSDMA1_STATUS5_REG = 0x067a # macro +mmSDMA1_STATUS5_REG_BASE_IDX = 0 # macro +mmSDMA1_QUEUE_RESET_REQ = 0x067b # macro +mmSDMA1_QUEUE_RESET_REQ_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_CNTL = 0x0680 # macro +mmSDMA1_GFX_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_BASE = 0x0681 # macro +mmSDMA1_GFX_RB_BASE_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_BASE_HI = 0x0682 # macro +mmSDMA1_GFX_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_RPTR = 0x0683 # macro +mmSDMA1_GFX_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_RPTR_HI = 0x0684 # macro +mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_WPTR = 0x0685 # macro +mmSDMA1_GFX_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_WPTR_HI = 0x0686 # macro +mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_WPTR_POLL_CNTL = 0x0687 # macro +mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_RPTR_ADDR_HI = 0x0688 # macro +mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_RPTR_ADDR_LO = 0x0689 # macro +mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_GFX_IB_CNTL = 0x068a # macro +mmSDMA1_GFX_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_GFX_IB_RPTR = 0x068b # macro +mmSDMA1_GFX_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_GFX_IB_OFFSET = 0x068c # macro +mmSDMA1_GFX_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_GFX_IB_BASE_LO = 0x068d # macro +mmSDMA1_GFX_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA1_GFX_IB_BASE_HI = 0x068e # macro +mmSDMA1_GFX_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_GFX_IB_SIZE = 0x068f # macro +mmSDMA1_GFX_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA1_GFX_SKIP_CNTL = 0x0690 # macro +mmSDMA1_GFX_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA1_GFX_CONTEXT_STATUS = 0x0691 # macro +mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA1_GFX_DOORBELL = 0x0692 # macro +mmSDMA1_GFX_DOORBELL_BASE_IDX = 0 # macro +mmSDMA1_GFX_CONTEXT_CNTL = 0x0693 # macro +mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX = 0 # macro +mmSDMA1_GFX_STATUS = 0x06a8 # macro +mmSDMA1_GFX_STATUS_BASE_IDX = 0 # macro +mmSDMA1_GFX_DOORBELL_LOG = 0x06a9 # macro +mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA1_GFX_WATERMARK = 0x06aa # macro +mmSDMA1_GFX_WATERMARK_BASE_IDX = 0 # macro +mmSDMA1_GFX_DOORBELL_OFFSET = 0x06ab # macro +mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_GFX_CSA_ADDR_LO = 0x06ac # macro +mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_GFX_CSA_ADDR_HI = 0x06ad # macro +mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_GFX_IB_SUB_REMAIN = 0x06af # macro +mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA1_GFX_PREEMPT = 0x06b0 # macro +mmSDMA1_GFX_PREEMPT_BASE_IDX = 0 # macro +mmSDMA1_GFX_DUMMY_REG = 0x06b1 # macro +mmSDMA1_GFX_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI = 0x06b2 # macro +mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO = 0x06b3 # macro +mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_GFX_RB_AQL_CNTL = 0x06b4 # macro +mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_GFX_MINOR_PTR_UPDATE = 0x06b5 # macro +mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA1_GFX_MIDCMD_DATA0 = 0x06c0 # macro +mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA1_GFX_MIDCMD_DATA1 = 0x06c1 # macro +mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA1_GFX_MIDCMD_DATA2 = 0x06c2 # macro +mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA1_GFX_MIDCMD_DATA3 = 0x06c3 # macro +mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA1_GFX_MIDCMD_DATA4 = 0x06c4 # macro +mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA1_GFX_MIDCMD_DATA5 = 0x06c5 # macro +mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA1_GFX_MIDCMD_DATA6 = 0x06c6 # macro +mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA1_GFX_MIDCMD_DATA7 = 0x06c7 # macro +mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA1_GFX_MIDCMD_DATA8 = 0x06c8 # macro +mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA1_GFX_MIDCMD_DATA9 = 0x06c9 # macro +mmSDMA1_GFX_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA1_GFX_MIDCMD_DATA10 = 0x06ca # macro +mmSDMA1_GFX_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA1_GFX_MIDCMD_CNTL = 0x06cb # macro +mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_CNTL = 0x06d8 # macro +mmSDMA1_PAGE_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_BASE = 0x06d9 # macro +mmSDMA1_PAGE_RB_BASE_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_BASE_HI = 0x06da # macro +mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_RPTR = 0x06db # macro +mmSDMA1_PAGE_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_RPTR_HI = 0x06dc # macro +mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_WPTR = 0x06dd # macro +mmSDMA1_PAGE_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_WPTR_HI = 0x06de # macro +mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_WPTR_POLL_CNTL = 0x06df # macro +mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_RPTR_ADDR_HI = 0x06e0 # macro +mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_RPTR_ADDR_LO = 0x06e1 # macro +mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_PAGE_IB_CNTL = 0x06e2 # macro +mmSDMA1_PAGE_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_PAGE_IB_RPTR = 0x06e3 # macro +mmSDMA1_PAGE_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_PAGE_IB_OFFSET = 0x06e4 # macro +mmSDMA1_PAGE_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_PAGE_IB_BASE_LO = 0x06e5 # macro +mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA1_PAGE_IB_BASE_HI = 0x06e6 # macro +mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_PAGE_IB_SIZE = 0x06e7 # macro +mmSDMA1_PAGE_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA1_PAGE_SKIP_CNTL = 0x06e8 # macro +mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA1_PAGE_CONTEXT_STATUS = 0x06e9 # macro +mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA1_PAGE_DOORBELL = 0x06ea # macro +mmSDMA1_PAGE_DOORBELL_BASE_IDX = 0 # macro +mmSDMA1_PAGE_STATUS = 0x0700 # macro +mmSDMA1_PAGE_STATUS_BASE_IDX = 0 # macro +mmSDMA1_PAGE_DOORBELL_LOG = 0x0701 # macro +mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA1_PAGE_WATERMARK = 0x0702 # macro +mmSDMA1_PAGE_WATERMARK_BASE_IDX = 0 # macro +mmSDMA1_PAGE_DOORBELL_OFFSET = 0x0703 # macro +mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_PAGE_CSA_ADDR_LO = 0x0704 # macro +mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_PAGE_CSA_ADDR_HI = 0x0705 # macro +mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_PAGE_IB_SUB_REMAIN = 0x0707 # macro +mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA1_PAGE_PREEMPT = 0x0708 # macro +mmSDMA1_PAGE_PREEMPT_BASE_IDX = 0 # macro +mmSDMA1_PAGE_DUMMY_REG = 0x0709 # macro +mmSDMA1_PAGE_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI = 0x070a # macro +mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO = 0x070b # macro +mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_PAGE_RB_AQL_CNTL = 0x070c # macro +mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MINOR_PTR_UPDATE = 0x070d # macro +mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MIDCMD_DATA0 = 0x0718 # macro +mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MIDCMD_DATA1 = 0x0719 # macro +mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MIDCMD_DATA2 = 0x071a # macro +mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MIDCMD_DATA3 = 0x071b # macro +mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MIDCMD_DATA4 = 0x071c # macro +mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MIDCMD_DATA5 = 0x071d # macro +mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MIDCMD_DATA6 = 0x071e # macro +mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MIDCMD_DATA7 = 0x071f # macro +mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MIDCMD_DATA8 = 0x0720 # macro +mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MIDCMD_DATA9 = 0x0721 # macro +mmSDMA1_PAGE_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MIDCMD_DATA10 = 0x0722 # macro +mmSDMA1_PAGE_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA1_PAGE_MIDCMD_CNTL = 0x0723 # macro +mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_CNTL = 0x0730 # macro +mmSDMA1_RLC0_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_BASE = 0x0731 # macro +mmSDMA1_RLC0_RB_BASE_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_BASE_HI = 0x0732 # macro +mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_RPTR = 0x0733 # macro +mmSDMA1_RLC0_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_RPTR_HI = 0x0734 # macro +mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_WPTR = 0x0735 # macro +mmSDMA1_RLC0_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_WPTR_HI = 0x0736 # macro +mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_WPTR_POLL_CNTL = 0x0737 # macro +mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_RPTR_ADDR_HI = 0x0738 # macro +mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_RPTR_ADDR_LO = 0x0739 # macro +mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC0_IB_CNTL = 0x073a # macro +mmSDMA1_RLC0_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC0_IB_RPTR = 0x073b # macro +mmSDMA1_RLC0_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC0_IB_OFFSET = 0x073c # macro +mmSDMA1_RLC0_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC0_IB_BASE_LO = 0x073d # macro +mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC0_IB_BASE_HI = 0x073e # macro +mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC0_IB_SIZE = 0x073f # macro +mmSDMA1_RLC0_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA1_RLC0_SKIP_CNTL = 0x0740 # macro +mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC0_CONTEXT_STATUS = 0x0741 # macro +mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC0_DOORBELL = 0x0742 # macro +mmSDMA1_RLC0_DOORBELL_BASE_IDX = 0 # macro +mmSDMA1_RLC0_STATUS = 0x0758 # macro +mmSDMA1_RLC0_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC0_DOORBELL_LOG = 0x0759 # macro +mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA1_RLC0_WATERMARK = 0x075a # macro +mmSDMA1_RLC0_WATERMARK_BASE_IDX = 0 # macro +mmSDMA1_RLC0_DOORBELL_OFFSET = 0x075b # macro +mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC0_CSA_ADDR_LO = 0x075c # macro +mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC0_CSA_ADDR_HI = 0x075d # macro +mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC0_IB_SUB_REMAIN = 0x075f # macro +mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA1_RLC0_PREEMPT = 0x0760 # macro +mmSDMA1_RLC0_PREEMPT_BASE_IDX = 0 # macro +mmSDMA1_RLC0_DUMMY_REG = 0x0761 # macro +mmSDMA1_RLC0_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI = 0x0762 # macro +mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO = 0x0763 # macro +mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC0_RB_AQL_CNTL = 0x0764 # macro +mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MINOR_PTR_UPDATE = 0x0765 # macro +mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MIDCMD_DATA0 = 0x0770 # macro +mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MIDCMD_DATA1 = 0x0771 # macro +mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MIDCMD_DATA2 = 0x0772 # macro +mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MIDCMD_DATA3 = 0x0773 # macro +mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MIDCMD_DATA4 = 0x0774 # macro +mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MIDCMD_DATA5 = 0x0775 # macro +mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MIDCMD_DATA6 = 0x0776 # macro +mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MIDCMD_DATA7 = 0x0777 # macro +mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MIDCMD_DATA8 = 0x0778 # macro +mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MIDCMD_DATA9 = 0x0779 # macro +mmSDMA1_RLC0_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MIDCMD_DATA10 = 0x077a # macro +mmSDMA1_RLC0_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA1_RLC0_MIDCMD_CNTL = 0x077b # macro +mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_CNTL = 0x0788 # macro +mmSDMA1_RLC1_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_BASE = 0x0789 # macro +mmSDMA1_RLC1_RB_BASE_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_BASE_HI = 0x078a # macro +mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_RPTR = 0x078b # macro +mmSDMA1_RLC1_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_RPTR_HI = 0x078c # macro +mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_WPTR = 0x078d # macro +mmSDMA1_RLC1_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_WPTR_HI = 0x078e # macro +mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_WPTR_POLL_CNTL = 0x078f # macro +mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_RPTR_ADDR_HI = 0x0790 # macro +mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_RPTR_ADDR_LO = 0x0791 # macro +mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC1_IB_CNTL = 0x0792 # macro +mmSDMA1_RLC1_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC1_IB_RPTR = 0x0793 # macro +mmSDMA1_RLC1_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC1_IB_OFFSET = 0x0794 # macro +mmSDMA1_RLC1_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC1_IB_BASE_LO = 0x0795 # macro +mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC1_IB_BASE_HI = 0x0796 # macro +mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC1_IB_SIZE = 0x0797 # macro +mmSDMA1_RLC1_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA1_RLC1_SKIP_CNTL = 0x0798 # macro +mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC1_CONTEXT_STATUS = 0x0799 # macro +mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC1_DOORBELL = 0x079a # macro +mmSDMA1_RLC1_DOORBELL_BASE_IDX = 0 # macro +mmSDMA1_RLC1_STATUS = 0x07b0 # macro +mmSDMA1_RLC1_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC1_DOORBELL_LOG = 0x07b1 # macro +mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA1_RLC1_WATERMARK = 0x07b2 # macro +mmSDMA1_RLC1_WATERMARK_BASE_IDX = 0 # macro +mmSDMA1_RLC1_DOORBELL_OFFSET = 0x07b3 # macro +mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC1_CSA_ADDR_LO = 0x07b4 # macro +mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC1_CSA_ADDR_HI = 0x07b5 # macro +mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC1_IB_SUB_REMAIN = 0x07b7 # macro +mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA1_RLC1_PREEMPT = 0x07b8 # macro +mmSDMA1_RLC1_PREEMPT_BASE_IDX = 0 # macro +mmSDMA1_RLC1_DUMMY_REG = 0x07b9 # macro +mmSDMA1_RLC1_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI = 0x07ba # macro +mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO = 0x07bb # macro +mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC1_RB_AQL_CNTL = 0x07bc # macro +mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MINOR_PTR_UPDATE = 0x07bd # macro +mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MIDCMD_DATA0 = 0x07c8 # macro +mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MIDCMD_DATA1 = 0x07c9 # macro +mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MIDCMD_DATA2 = 0x07ca # macro +mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MIDCMD_DATA3 = 0x07cb # macro +mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MIDCMD_DATA4 = 0x07cc # macro +mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MIDCMD_DATA5 = 0x07cd # macro +mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MIDCMD_DATA6 = 0x07ce # macro +mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MIDCMD_DATA7 = 0x07cf # macro +mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MIDCMD_DATA8 = 0x07d0 # macro +mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MIDCMD_DATA9 = 0x07d1 # macro +mmSDMA1_RLC1_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MIDCMD_DATA10 = 0x07d2 # macro +mmSDMA1_RLC1_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA1_RLC1_MIDCMD_CNTL = 0x07d3 # macro +mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_CNTL = 0x07e0 # macro +mmSDMA1_RLC2_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_BASE = 0x07e1 # macro +mmSDMA1_RLC2_RB_BASE_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_BASE_HI = 0x07e2 # macro +mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_RPTR = 0x07e3 # macro +mmSDMA1_RLC2_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_RPTR_HI = 0x07e4 # macro +mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_WPTR = 0x07e5 # macro +mmSDMA1_RLC2_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_WPTR_HI = 0x07e6 # macro +mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_WPTR_POLL_CNTL = 0x07e7 # macro +mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_RPTR_ADDR_HI = 0x07e8 # macro +mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_RPTR_ADDR_LO = 0x07e9 # macro +mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC2_IB_CNTL = 0x07ea # macro +mmSDMA1_RLC2_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC2_IB_RPTR = 0x07eb # macro +mmSDMA1_RLC2_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC2_IB_OFFSET = 0x07ec # macro +mmSDMA1_RLC2_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC2_IB_BASE_LO = 0x07ed # macro +mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC2_IB_BASE_HI = 0x07ee # macro +mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC2_IB_SIZE = 0x07ef # macro +mmSDMA1_RLC2_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA1_RLC2_SKIP_CNTL = 0x07f0 # macro +mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC2_CONTEXT_STATUS = 0x07f1 # macro +mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC2_DOORBELL = 0x07f2 # macro +mmSDMA1_RLC2_DOORBELL_BASE_IDX = 0 # macro +mmSDMA1_RLC2_STATUS = 0x0808 # macro +mmSDMA1_RLC2_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC2_DOORBELL_LOG = 0x0809 # macro +mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA1_RLC2_WATERMARK = 0x080a # macro +mmSDMA1_RLC2_WATERMARK_BASE_IDX = 0 # macro +mmSDMA1_RLC2_DOORBELL_OFFSET = 0x080b # macro +mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC2_CSA_ADDR_LO = 0x080c # macro +mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC2_CSA_ADDR_HI = 0x080d # macro +mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC2_IB_SUB_REMAIN = 0x080f # macro +mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA1_RLC2_PREEMPT = 0x0810 # macro +mmSDMA1_RLC2_PREEMPT_BASE_IDX = 0 # macro +mmSDMA1_RLC2_DUMMY_REG = 0x0811 # macro +mmSDMA1_RLC2_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI = 0x0812 # macro +mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO = 0x0813 # macro +mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC2_RB_AQL_CNTL = 0x0814 # macro +mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MINOR_PTR_UPDATE = 0x0815 # macro +mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MIDCMD_DATA0 = 0x0820 # macro +mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MIDCMD_DATA1 = 0x0821 # macro +mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MIDCMD_DATA2 = 0x0822 # macro +mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MIDCMD_DATA3 = 0x0823 # macro +mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MIDCMD_DATA4 = 0x0824 # macro +mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MIDCMD_DATA5 = 0x0825 # macro +mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MIDCMD_DATA6 = 0x0826 # macro +mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MIDCMD_DATA7 = 0x0827 # macro +mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MIDCMD_DATA8 = 0x0828 # macro +mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MIDCMD_DATA9 = 0x0829 # macro +mmSDMA1_RLC2_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MIDCMD_DATA10 = 0x082a # macro +mmSDMA1_RLC2_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA1_RLC2_MIDCMD_CNTL = 0x082b # macro +mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_CNTL = 0x0838 # macro +mmSDMA1_RLC3_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_BASE = 0x0839 # macro +mmSDMA1_RLC3_RB_BASE_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_BASE_HI = 0x083a # macro +mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_RPTR = 0x083b # macro +mmSDMA1_RLC3_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_RPTR_HI = 0x083c # macro +mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_WPTR = 0x083d # macro +mmSDMA1_RLC3_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_WPTR_HI = 0x083e # macro +mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_WPTR_POLL_CNTL = 0x083f # macro +mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_RPTR_ADDR_HI = 0x0840 # macro +mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_RPTR_ADDR_LO = 0x0841 # macro +mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC3_IB_CNTL = 0x0842 # macro +mmSDMA1_RLC3_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC3_IB_RPTR = 0x0843 # macro +mmSDMA1_RLC3_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC3_IB_OFFSET = 0x0844 # macro +mmSDMA1_RLC3_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC3_IB_BASE_LO = 0x0845 # macro +mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC3_IB_BASE_HI = 0x0846 # macro +mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC3_IB_SIZE = 0x0847 # macro +mmSDMA1_RLC3_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA1_RLC3_SKIP_CNTL = 0x0848 # macro +mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC3_CONTEXT_STATUS = 0x0849 # macro +mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC3_DOORBELL = 0x084a # macro +mmSDMA1_RLC3_DOORBELL_BASE_IDX = 0 # macro +mmSDMA1_RLC3_STATUS = 0x0860 # macro +mmSDMA1_RLC3_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC3_DOORBELL_LOG = 0x0861 # macro +mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA1_RLC3_WATERMARK = 0x0862 # macro +mmSDMA1_RLC3_WATERMARK_BASE_IDX = 0 # macro +mmSDMA1_RLC3_DOORBELL_OFFSET = 0x0863 # macro +mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC3_CSA_ADDR_LO = 0x0864 # macro +mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC3_CSA_ADDR_HI = 0x0865 # macro +mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC3_IB_SUB_REMAIN = 0x0867 # macro +mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA1_RLC3_PREEMPT = 0x0868 # macro +mmSDMA1_RLC3_PREEMPT_BASE_IDX = 0 # macro +mmSDMA1_RLC3_DUMMY_REG = 0x0869 # macro +mmSDMA1_RLC3_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI = 0x086a # macro +mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO = 0x086b # macro +mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC3_RB_AQL_CNTL = 0x086c # macro +mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MINOR_PTR_UPDATE = 0x086d # macro +mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MIDCMD_DATA0 = 0x0878 # macro +mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MIDCMD_DATA1 = 0x0879 # macro +mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MIDCMD_DATA2 = 0x087a # macro +mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MIDCMD_DATA3 = 0x087b # macro +mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MIDCMD_DATA4 = 0x087c # macro +mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MIDCMD_DATA5 = 0x087d # macro +mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MIDCMD_DATA6 = 0x087e # macro +mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MIDCMD_DATA7 = 0x087f # macro +mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MIDCMD_DATA8 = 0x0880 # macro +mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MIDCMD_DATA9 = 0x0881 # macro +mmSDMA1_RLC3_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MIDCMD_DATA10 = 0x0882 # macro +mmSDMA1_RLC3_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA1_RLC3_MIDCMD_CNTL = 0x0883 # macro +mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_CNTL = 0x0890 # macro +mmSDMA1_RLC4_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_BASE = 0x0891 # macro +mmSDMA1_RLC4_RB_BASE_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_BASE_HI = 0x0892 # macro +mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_RPTR = 0x0893 # macro +mmSDMA1_RLC4_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_RPTR_HI = 0x0894 # macro +mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_WPTR = 0x0895 # macro +mmSDMA1_RLC4_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_WPTR_HI = 0x0896 # macro +mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_WPTR_POLL_CNTL = 0x0897 # macro +mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_RPTR_ADDR_HI = 0x0898 # macro +mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_RPTR_ADDR_LO = 0x0899 # macro +mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC4_IB_CNTL = 0x089a # macro +mmSDMA1_RLC4_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC4_IB_RPTR = 0x089b # macro +mmSDMA1_RLC4_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC4_IB_OFFSET = 0x089c # macro +mmSDMA1_RLC4_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC4_IB_BASE_LO = 0x089d # macro +mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC4_IB_BASE_HI = 0x089e # macro +mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC4_IB_SIZE = 0x089f # macro +mmSDMA1_RLC4_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA1_RLC4_SKIP_CNTL = 0x08a0 # macro +mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC4_CONTEXT_STATUS = 0x08a1 # macro +mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC4_DOORBELL = 0x08a2 # macro +mmSDMA1_RLC4_DOORBELL_BASE_IDX = 0 # macro +mmSDMA1_RLC4_STATUS = 0x08b8 # macro +mmSDMA1_RLC4_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC4_DOORBELL_LOG = 0x08b9 # macro +mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA1_RLC4_WATERMARK = 0x08ba # macro +mmSDMA1_RLC4_WATERMARK_BASE_IDX = 0 # macro +mmSDMA1_RLC4_DOORBELL_OFFSET = 0x08bb # macro +mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC4_CSA_ADDR_LO = 0x08bc # macro +mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC4_CSA_ADDR_HI = 0x08bd # macro +mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC4_IB_SUB_REMAIN = 0x08bf # macro +mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA1_RLC4_PREEMPT = 0x08c0 # macro +mmSDMA1_RLC4_PREEMPT_BASE_IDX = 0 # macro +mmSDMA1_RLC4_DUMMY_REG = 0x08c1 # macro +mmSDMA1_RLC4_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI = 0x08c2 # macro +mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO = 0x08c3 # macro +mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC4_RB_AQL_CNTL = 0x08c4 # macro +mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MINOR_PTR_UPDATE = 0x08c5 # macro +mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MIDCMD_DATA0 = 0x08d0 # macro +mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MIDCMD_DATA1 = 0x08d1 # macro +mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MIDCMD_DATA2 = 0x08d2 # macro +mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MIDCMD_DATA3 = 0x08d3 # macro +mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MIDCMD_DATA4 = 0x08d4 # macro +mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MIDCMD_DATA5 = 0x08d5 # macro +mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MIDCMD_DATA6 = 0x08d6 # macro +mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MIDCMD_DATA7 = 0x08d7 # macro +mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MIDCMD_DATA8 = 0x08d8 # macro +mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MIDCMD_DATA9 = 0x08d9 # macro +mmSDMA1_RLC4_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MIDCMD_DATA10 = 0x08da # macro +mmSDMA1_RLC4_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA1_RLC4_MIDCMD_CNTL = 0x08db # macro +mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_CNTL = 0x08e8 # macro +mmSDMA1_RLC5_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_BASE = 0x08e9 # macro +mmSDMA1_RLC5_RB_BASE_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_BASE_HI = 0x08ea # macro +mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_RPTR = 0x08eb # macro +mmSDMA1_RLC5_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_RPTR_HI = 0x08ec # macro +mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_WPTR = 0x08ed # macro +mmSDMA1_RLC5_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_WPTR_HI = 0x08ee # macro +mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_WPTR_POLL_CNTL = 0x08ef # macro +mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_RPTR_ADDR_HI = 0x08f0 # macro +mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_RPTR_ADDR_LO = 0x08f1 # macro +mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC5_IB_CNTL = 0x08f2 # macro +mmSDMA1_RLC5_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC5_IB_RPTR = 0x08f3 # macro +mmSDMA1_RLC5_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC5_IB_OFFSET = 0x08f4 # macro +mmSDMA1_RLC5_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC5_IB_BASE_LO = 0x08f5 # macro +mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC5_IB_BASE_HI = 0x08f6 # macro +mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC5_IB_SIZE = 0x08f7 # macro +mmSDMA1_RLC5_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA1_RLC5_SKIP_CNTL = 0x08f8 # macro +mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC5_CONTEXT_STATUS = 0x08f9 # macro +mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC5_DOORBELL = 0x08fa # macro +mmSDMA1_RLC5_DOORBELL_BASE_IDX = 0 # macro +mmSDMA1_RLC5_STATUS = 0x0910 # macro +mmSDMA1_RLC5_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC5_DOORBELL_LOG = 0x0911 # macro +mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA1_RLC5_WATERMARK = 0x0912 # macro +mmSDMA1_RLC5_WATERMARK_BASE_IDX = 0 # macro +mmSDMA1_RLC5_DOORBELL_OFFSET = 0x0913 # macro +mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC5_CSA_ADDR_LO = 0x0914 # macro +mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC5_CSA_ADDR_HI = 0x0915 # macro +mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC5_IB_SUB_REMAIN = 0x0917 # macro +mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA1_RLC5_PREEMPT = 0x0918 # macro +mmSDMA1_RLC5_PREEMPT_BASE_IDX = 0 # macro +mmSDMA1_RLC5_DUMMY_REG = 0x0919 # macro +mmSDMA1_RLC5_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI = 0x091a # macro +mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO = 0x091b # macro +mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC5_RB_AQL_CNTL = 0x091c # macro +mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MINOR_PTR_UPDATE = 0x091d # macro +mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MIDCMD_DATA0 = 0x0928 # macro +mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MIDCMD_DATA1 = 0x0929 # macro +mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MIDCMD_DATA2 = 0x092a # macro +mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MIDCMD_DATA3 = 0x092b # macro +mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MIDCMD_DATA4 = 0x092c # macro +mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MIDCMD_DATA5 = 0x092d # macro +mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MIDCMD_DATA6 = 0x092e # macro +mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MIDCMD_DATA7 = 0x092f # macro +mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MIDCMD_DATA8 = 0x0930 # macro +mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MIDCMD_DATA9 = 0x0931 # macro +mmSDMA1_RLC5_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MIDCMD_DATA10 = 0x0932 # macro +mmSDMA1_RLC5_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA1_RLC5_MIDCMD_CNTL = 0x0933 # macro +mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_CNTL = 0x0940 # macro +mmSDMA1_RLC6_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_BASE = 0x0941 # macro +mmSDMA1_RLC6_RB_BASE_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_BASE_HI = 0x0942 # macro +mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_RPTR = 0x0943 # macro +mmSDMA1_RLC6_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_RPTR_HI = 0x0944 # macro +mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_WPTR = 0x0945 # macro +mmSDMA1_RLC6_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_WPTR_HI = 0x0946 # macro +mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_WPTR_POLL_CNTL = 0x0947 # macro +mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_RPTR_ADDR_HI = 0x0948 # macro +mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_RPTR_ADDR_LO = 0x0949 # macro +mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC6_IB_CNTL = 0x094a # macro +mmSDMA1_RLC6_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC6_IB_RPTR = 0x094b # macro +mmSDMA1_RLC6_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC6_IB_OFFSET = 0x094c # macro +mmSDMA1_RLC6_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC6_IB_BASE_LO = 0x094d # macro +mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC6_IB_BASE_HI = 0x094e # macro +mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC6_IB_SIZE = 0x094f # macro +mmSDMA1_RLC6_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA1_RLC6_SKIP_CNTL = 0x0950 # macro +mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC6_CONTEXT_STATUS = 0x0951 # macro +mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC6_DOORBELL = 0x0952 # macro +mmSDMA1_RLC6_DOORBELL_BASE_IDX = 0 # macro +mmSDMA1_RLC6_STATUS = 0x0968 # macro +mmSDMA1_RLC6_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC6_DOORBELL_LOG = 0x0969 # macro +mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA1_RLC6_WATERMARK = 0x096a # macro +mmSDMA1_RLC6_WATERMARK_BASE_IDX = 0 # macro +mmSDMA1_RLC6_DOORBELL_OFFSET = 0x096b # macro +mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC6_CSA_ADDR_LO = 0x096c # macro +mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC6_CSA_ADDR_HI = 0x096d # macro +mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC6_IB_SUB_REMAIN = 0x096f # macro +mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA1_RLC6_PREEMPT = 0x0970 # macro +mmSDMA1_RLC6_PREEMPT_BASE_IDX = 0 # macro +mmSDMA1_RLC6_DUMMY_REG = 0x0971 # macro +mmSDMA1_RLC6_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI = 0x0972 # macro +mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO = 0x0973 # macro +mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC6_RB_AQL_CNTL = 0x0974 # macro +mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MINOR_PTR_UPDATE = 0x0975 # macro +mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MIDCMD_DATA0 = 0x0980 # macro +mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MIDCMD_DATA1 = 0x0981 # macro +mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MIDCMD_DATA2 = 0x0982 # macro +mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MIDCMD_DATA3 = 0x0983 # macro +mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MIDCMD_DATA4 = 0x0984 # macro +mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MIDCMD_DATA5 = 0x0985 # macro +mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MIDCMD_DATA6 = 0x0986 # macro +mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MIDCMD_DATA7 = 0x0987 # macro +mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MIDCMD_DATA8 = 0x0988 # macro +mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MIDCMD_DATA9 = 0x0989 # macro +mmSDMA1_RLC6_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MIDCMD_DATA10 = 0x098a # macro +mmSDMA1_RLC6_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA1_RLC6_MIDCMD_CNTL = 0x098b # macro +mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_CNTL = 0x0998 # macro +mmSDMA1_RLC7_RB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_BASE = 0x0999 # macro +mmSDMA1_RLC7_RB_BASE_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_BASE_HI = 0x099a # macro +mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_RPTR = 0x099b # macro +mmSDMA1_RLC7_RB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_RPTR_HI = 0x099c # macro +mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_WPTR = 0x099d # macro +mmSDMA1_RLC7_RB_WPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_WPTR_HI = 0x099e # macro +mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_WPTR_POLL_CNTL = 0x099f # macro +mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_RPTR_ADDR_HI = 0x09a0 # macro +mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_RPTR_ADDR_LO = 0x09a1 # macro +mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC7_IB_CNTL = 0x09a2 # macro +mmSDMA1_RLC7_IB_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC7_IB_RPTR = 0x09a3 # macro +mmSDMA1_RLC7_IB_RPTR_BASE_IDX = 0 # macro +mmSDMA1_RLC7_IB_OFFSET = 0x09a4 # macro +mmSDMA1_RLC7_IB_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC7_IB_BASE_LO = 0x09a5 # macro +mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC7_IB_BASE_HI = 0x09a6 # macro +mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC7_IB_SIZE = 0x09a7 # macro +mmSDMA1_RLC7_IB_SIZE_BASE_IDX = 0 # macro +mmSDMA1_RLC7_SKIP_CNTL = 0x09a8 # macro +mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC7_CONTEXT_STATUS = 0x09a9 # macro +mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC7_DOORBELL = 0x09aa # macro +mmSDMA1_RLC7_DOORBELL_BASE_IDX = 0 # macro +mmSDMA1_RLC7_STATUS = 0x09c0 # macro +mmSDMA1_RLC7_STATUS_BASE_IDX = 0 # macro +mmSDMA1_RLC7_DOORBELL_LOG = 0x09c1 # macro +mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX = 0 # macro +mmSDMA1_RLC7_WATERMARK = 0x09c2 # macro +mmSDMA1_RLC7_WATERMARK_BASE_IDX = 0 # macro +mmSDMA1_RLC7_DOORBELL_OFFSET = 0x09c3 # macro +mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX = 0 # macro +mmSDMA1_RLC7_CSA_ADDR_LO = 0x09c4 # macro +mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC7_CSA_ADDR_HI = 0x09c5 # macro +mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC7_IB_SUB_REMAIN = 0x09c7 # macro +mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX = 0 # macro +mmSDMA1_RLC7_PREEMPT = 0x09c8 # macro +mmSDMA1_RLC7_PREEMPT_BASE_IDX = 0 # macro +mmSDMA1_RLC7_DUMMY_REG = 0x09c9 # macro +mmSDMA1_RLC7_DUMMY_REG_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI = 0x09ca # macro +mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO = 0x09cb # macro +mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmSDMA1_RLC7_RB_AQL_CNTL = 0x09cc # macro +mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MINOR_PTR_UPDATE = 0x09cd # macro +mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MIDCMD_DATA0 = 0x09d8 # macro +mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MIDCMD_DATA1 = 0x09d9 # macro +mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MIDCMD_DATA2 = 0x09da # macro +mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MIDCMD_DATA3 = 0x09db # macro +mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MIDCMD_DATA4 = 0x09dc # macro +mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MIDCMD_DATA5 = 0x09dd # macro +mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MIDCMD_DATA6 = 0x09de # macro +mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MIDCMD_DATA7 = 0x09df # macro +mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MIDCMD_DATA8 = 0x09e0 # macro +mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MIDCMD_DATA9 = 0x09e1 # macro +mmSDMA1_RLC7_MIDCMD_DATA9_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MIDCMD_DATA10 = 0x09e2 # macro +mmSDMA1_RLC7_MIDCMD_DATA10_BASE_IDX = 0 # macro +mmSDMA1_RLC7_MIDCMD_CNTL = 0x09e3 # macro +mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX = 0 # macro +mmGRBM_CNTL = 0x0da0 # macro +mmGRBM_CNTL_BASE_IDX = 0 # macro +mmGRBM_SKEW_CNTL = 0x0da1 # macro +mmGRBM_SKEW_CNTL_BASE_IDX = 0 # macro +mmGRBM_STATUS2 = 0x0da2 # macro +mmGRBM_STATUS2_BASE_IDX = 0 # macro +mmGRBM_PWR_CNTL = 0x0da3 # macro +mmGRBM_PWR_CNTL_BASE_IDX = 0 # macro +mmGRBM_STATUS = 0x0da4 # macro +mmGRBM_STATUS_BASE_IDX = 0 # macro +mmGRBM_STATUS_SE0 = 0x0da5 # macro +mmGRBM_STATUS_SE0_BASE_IDX = 0 # macro +mmGRBM_STATUS_SE1 = 0x0da6 # macro +mmGRBM_STATUS_SE1_BASE_IDX = 0 # macro +mmGRBM_STATUS3 = 0x0da7 # macro +mmGRBM_STATUS3_BASE_IDX = 0 # macro +mmGRBM_SOFT_RESET = 0x0da8 # macro +mmGRBM_SOFT_RESET_BASE_IDX = 0 # macro +mmGRBM_GFX_CLKEN_CNTL = 0x0dac # macro +mmGRBM_GFX_CLKEN_CNTL_BASE_IDX = 0 # macro +mmGRBM_WAIT_IDLE_CLOCKS = 0x0dad # macro +mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX = 0 # macro +mmGRBM_STATUS_SE2 = 0x0dae # macro +mmGRBM_STATUS_SE2_BASE_IDX = 0 # macro +mmGRBM_STATUS_SE3 = 0x0daf # macro +mmGRBM_STATUS_SE3_BASE_IDX = 0 # macro +mmGRBM_READ_ERROR = 0x0db6 # macro +mmGRBM_READ_ERROR_BASE_IDX = 0 # macro +mmGRBM_READ_ERROR2 = 0x0db7 # macro +mmGRBM_READ_ERROR2_BASE_IDX = 0 # macro +mmGRBM_INT_CNTL = 0x0db8 # macro +mmGRBM_INT_CNTL_BASE_IDX = 0 # macro +mmGRBM_TRAP_OP = 0x0db9 # macro +mmGRBM_TRAP_OP_BASE_IDX = 0 # macro +mmGRBM_TRAP_ADDR = 0x0dba # macro +mmGRBM_TRAP_ADDR_BASE_IDX = 0 # macro +mmGRBM_TRAP_ADDR_MSK = 0x0dbb # macro +mmGRBM_TRAP_ADDR_MSK_BASE_IDX = 0 # macro +mmGRBM_TRAP_WD = 0x0dbc # macro +mmGRBM_TRAP_WD_BASE_IDX = 0 # macro +mmGRBM_TRAP_WD_MSK = 0x0dbd # macro +mmGRBM_TRAP_WD_MSK_BASE_IDX = 0 # macro +mmGRBM_DSM_BYPASS = 0x0dbe # macro +mmGRBM_DSM_BYPASS_BASE_IDX = 0 # macro +mmGRBM_WRITE_ERROR = 0x0dbf # macro +mmGRBM_WRITE_ERROR_BASE_IDX = 0 # macro +mmGRBM_CHIP_REVISION = 0x0dc1 # macro +mmGRBM_CHIP_REVISION_BASE_IDX = 0 # macro +mmGRBM_GFX_CNTL = 0x0dc2 # macro +mmGRBM_GFX_CNTL_BASE_IDX = 0 # macro +mmGRBM_IH_CREDIT = 0x0dc4 # macro +mmGRBM_IH_CREDIT_BASE_IDX = 0 # macro +mmGRBM_PWR_CNTL2 = 0x0dc5 # macro +mmGRBM_PWR_CNTL2_BASE_IDX = 0 # macro +mmGRBM_UTCL2_INVAL_RANGE_START = 0x0dc6 # macro +mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX = 0 # macro +mmGRBM_UTCL2_INVAL_RANGE_END = 0x0dc7 # macro +mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX = 0 # macro +mmGRBM_FENCE_RANGE0 = 0x0dca # macro +mmGRBM_FENCE_RANGE0_BASE_IDX = 0 # macro +mmGRBM_FENCE_RANGE1 = 0x0dcb # macro +mmGRBM_FENCE_RANGE1_BASE_IDX = 0 # macro +mmGRBM_NOWHERE = 0x0ddf # macro +mmGRBM_NOWHERE_BASE_IDX = 0 # macro +mmGRBM_SCRATCH_REG0 = 0x0de0 # macro +mmGRBM_SCRATCH_REG0_BASE_IDX = 0 # macro +mmGRBM_SCRATCH_REG1 = 0x0de1 # macro +mmGRBM_SCRATCH_REG1_BASE_IDX = 0 # macro +mmGRBM_SCRATCH_REG2 = 0x0de2 # macro +mmGRBM_SCRATCH_REG2_BASE_IDX = 0 # macro +mmGRBM_SCRATCH_REG3 = 0x0de3 # macro +mmGRBM_SCRATCH_REG3_BASE_IDX = 0 # macro +mmGRBM_SCRATCH_REG4 = 0x0de4 # macro +mmGRBM_SCRATCH_REG4_BASE_IDX = 0 # macro +mmGRBM_SCRATCH_REG5 = 0x0de5 # macro +mmGRBM_SCRATCH_REG5_BASE_IDX = 0 # macro +mmGRBM_SCRATCH_REG6 = 0x0de6 # macro +mmGRBM_SCRATCH_REG6_BASE_IDX = 0 # macro +mmGRBM_SCRATCH_REG7 = 0x0de7 # macro +mmGRBM_SCRATCH_REG7_BASE_IDX = 0 # macro +mmVIOLATION_DATA_ASYNC_VF_PROG = 0x0df1 # macro +mmVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX = 0 # macro +mmCP_CPC_STATUS = 0x0e24 # macro +mmCP_CPC_STATUS_BASE_IDX = 0 # macro +mmCP_CPC_BUSY_STAT = 0x0e25 # macro +mmCP_CPC_BUSY_STAT_BASE_IDX = 0 # macro +mmCP_CPC_STALLED_STAT1 = 0x0e26 # macro +mmCP_CPC_STALLED_STAT1_BASE_IDX = 0 # macro +mmCP_CPF_STATUS = 0x0e27 # macro +mmCP_CPF_STATUS_BASE_IDX = 0 # macro +mmCP_CPF_BUSY_STAT = 0x0e28 # macro +mmCP_CPF_BUSY_STAT_BASE_IDX = 0 # macro +mmCP_CPF_STALLED_STAT1 = 0x0e29 # macro +mmCP_CPF_STALLED_STAT1_BASE_IDX = 0 # macro +mmCP_CPC_BUSY_STAT2 = 0x0e2a # macro +mmCP_CPC_BUSY_STAT2_BASE_IDX = 0 # macro +mmCP_CPC_GRBM_FREE_COUNT = 0x0e2b # macro +mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX = 0 # macro +mmCP_CPC_PRIV_VIOLATION_ADDR = 0x0e2c # macro +mmCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro +mmCP_MEC_ME1_HEADER_DUMP = 0x0e2e # macro +mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX = 0 # macro +mmCP_MEC_ME2_HEADER_DUMP = 0x0e2f # macro +mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX = 0 # macro +mmCP_CPC_SCRATCH_INDEX = 0x0e30 # macro +mmCP_CPC_SCRATCH_INDEX_BASE_IDX = 0 # macro +mmCP_CPC_SCRATCH_DATA = 0x0e31 # macro +mmCP_CPC_SCRATCH_DATA_BASE_IDX = 0 # macro +mmCP_CPF_GRBM_FREE_COUNT = 0x0e32 # macro +mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX = 0 # macro +mmCP_CPF_BUSY_STAT2 = 0x0e33 # macro +mmCP_CPF_BUSY_STAT2_BASE_IDX = 0 # macro +mmCONFIG_RESERVED_REG0 = 0x0e34 # macro +mmCONFIG_RESERVED_REG0_BASE_IDX = 0 # macro +mmCONFIG_RESERVED_REG1 = 0x0e35 # macro +mmCONFIG_RESERVED_REG1_BASE_IDX = 0 # macro +mmCP_CPC_HALT_HYST_COUNT = 0x0e47 # macro +mmCP_CPC_HALT_HYST_COUNT_BASE_IDX = 0 # macro +mmCP_CE_COMPARE_COUNT = 0x0e60 # macro +mmCP_CE_COMPARE_COUNT_BASE_IDX = 0 # macro +mmCP_CE_DE_COUNT = 0x0e61 # macro +mmCP_CE_DE_COUNT_BASE_IDX = 0 # macro +mmCP_DE_CE_COUNT = 0x0e62 # macro +mmCP_DE_CE_COUNT_BASE_IDX = 0 # macro +mmCP_DE_LAST_INVAL_COUNT = 0x0e63 # macro +mmCP_DE_LAST_INVAL_COUNT_BASE_IDX = 0 # macro +mmCP_DE_DE_COUNT = 0x0e64 # macro +mmCP_DE_DE_COUNT_BASE_IDX = 0 # macro +mmCP_STALLED_STAT3 = 0x0f3c # macro +mmCP_STALLED_STAT3_BASE_IDX = 0 # macro +mmCP_STALLED_STAT1 = 0x0f3d # macro +mmCP_STALLED_STAT1_BASE_IDX = 0 # macro +mmCP_STALLED_STAT2 = 0x0f3e # macro +mmCP_STALLED_STAT2_BASE_IDX = 0 # macro +mmCP_BUSY_STAT = 0x0f3f # macro +mmCP_BUSY_STAT_BASE_IDX = 0 # macro +mmCP_STAT = 0x0f40 # macro +mmCP_STAT_BASE_IDX = 0 # macro +mmCP_ME_HEADER_DUMP = 0x0f41 # macro +mmCP_ME_HEADER_DUMP_BASE_IDX = 0 # macro +mmCP_PFP_HEADER_DUMP = 0x0f42 # macro +mmCP_PFP_HEADER_DUMP_BASE_IDX = 0 # macro +mmCP_GRBM_FREE_COUNT = 0x0f43 # macro +mmCP_GRBM_FREE_COUNT_BASE_IDX = 0 # macro +mmCP_CE_HEADER_DUMP = 0x0f44 # macro +mmCP_CE_HEADER_DUMP_BASE_IDX = 0 # macro +mmCP_PFP_INSTR_PNTR = 0x0f45 # macro +mmCP_PFP_INSTR_PNTR_BASE_IDX = 0 # macro +mmCP_ME_INSTR_PNTR = 0x0f46 # macro +mmCP_ME_INSTR_PNTR_BASE_IDX = 0 # macro +mmCP_CE_INSTR_PNTR = 0x0f47 # macro +mmCP_CE_INSTR_PNTR_BASE_IDX = 0 # macro +mmCP_MEC1_INSTR_PNTR = 0x0f48 # macro +mmCP_MEC1_INSTR_PNTR_BASE_IDX = 0 # macro +mmCP_MEC2_INSTR_PNTR = 0x0f49 # macro +mmCP_MEC2_INSTR_PNTR_BASE_IDX = 0 # macro +mmCP_CSF_STAT = 0x0f54 # macro +mmCP_CSF_STAT_BASE_IDX = 0 # macro +mmCP_MEC_CNTL = 0x0f55 # macro +mmCP_MEC_CNTL_BASE_IDX = 0 # macro +mmCP_ME_CNTL = 0x0f56 # macro +mmCP_ME_CNTL_BASE_IDX = 0 # macro +mmCP_CNTX_STAT = 0x0f58 # macro +mmCP_CNTX_STAT_BASE_IDX = 0 # macro +mmCP_ME_PREEMPTION = 0x0f59 # macro +mmCP_ME_PREEMPTION_BASE_IDX = 0 # macro +mmCP_ROQ_THRESHOLDS = 0x0f5c # macro +mmCP_ROQ_THRESHOLDS_BASE_IDX = 0 # macro +mmCP_MEQ_STQ_THRESHOLD = 0x0f5d # macro +mmCP_MEQ_STQ_THRESHOLD_BASE_IDX = 0 # macro +mmCP_RB2_RPTR = 0x0f5e # macro +mmCP_RB2_RPTR_BASE_IDX = 0 # macro +mmCP_RB1_RPTR = 0x0f5f # macro +mmCP_RB1_RPTR_BASE_IDX = 0 # macro +mmCP_RB0_RPTR = 0x0f60 # macro +mmCP_RB0_RPTR_BASE_IDX = 0 # macro +mmCP_RB_RPTR = 0x0f60 # macro +mmCP_RB_RPTR_BASE_IDX = 0 # macro +mmCP_RB_WPTR_DELAY = 0x0f61 # macro +mmCP_RB_WPTR_DELAY_BASE_IDX = 0 # macro +mmCP_RB_WPTR_POLL_CNTL = 0x0f62 # macro +mmCP_RB_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmCP_ROQ1_THRESHOLDS = 0x0f75 # macro +mmCP_ROQ1_THRESHOLDS_BASE_IDX = 0 # macro +mmCP_ROQ2_THRESHOLDS = 0x0f76 # macro +mmCP_ROQ2_THRESHOLDS_BASE_IDX = 0 # macro +mmCP_STQ_THRESHOLDS = 0x0f77 # macro +mmCP_STQ_THRESHOLDS_BASE_IDX = 0 # macro +mmCP_QUEUE_THRESHOLDS = 0x0f78 # macro +mmCP_QUEUE_THRESHOLDS_BASE_IDX = 0 # macro +mmCP_MEQ_THRESHOLDS = 0x0f79 # macro +mmCP_MEQ_THRESHOLDS_BASE_IDX = 0 # macro +mmCP_ROQ_AVAIL = 0x0f7a # macro +mmCP_ROQ_AVAIL_BASE_IDX = 0 # macro +mmCP_STQ_AVAIL = 0x0f7b # macro +mmCP_STQ_AVAIL_BASE_IDX = 0 # macro +mmCP_ROQ2_AVAIL = 0x0f7c # macro +mmCP_ROQ2_AVAIL_BASE_IDX = 0 # macro +mmCP_MEQ_AVAIL = 0x0f7d # macro +mmCP_MEQ_AVAIL_BASE_IDX = 0 # macro +mmCP_CMD_INDEX = 0x0f7e # macro +mmCP_CMD_INDEX_BASE_IDX = 0 # macro +mmCP_CMD_DATA = 0x0f7f # macro +mmCP_CMD_DATA_BASE_IDX = 0 # macro +mmCP_ROQ_RB_STAT = 0x0f80 # macro +mmCP_ROQ_RB_STAT_BASE_IDX = 0 # macro +mmCP_ROQ_IB1_STAT = 0x0f81 # macro +mmCP_ROQ_IB1_STAT_BASE_IDX = 0 # macro +mmCP_ROQ_IB2_STAT = 0x0f82 # macro +mmCP_ROQ_IB2_STAT_BASE_IDX = 0 # macro +mmCP_STQ_STAT = 0x0f83 # macro +mmCP_STQ_STAT_BASE_IDX = 0 # macro +mmCP_STQ_WR_STAT = 0x0f84 # macro +mmCP_STQ_WR_STAT_BASE_IDX = 0 # macro +mmCP_MEQ_STAT = 0x0f85 # macro +mmCP_MEQ_STAT_BASE_IDX = 0 # macro +mmCP_CEQ1_AVAIL = 0x0f86 # macro +mmCP_CEQ1_AVAIL_BASE_IDX = 0 # macro +mmCP_CEQ2_AVAIL = 0x0f87 # macro +mmCP_CEQ2_AVAIL_BASE_IDX = 0 # macro +mmCP_CE_ROQ_RB_STAT = 0x0f88 # macro +mmCP_CE_ROQ_RB_STAT_BASE_IDX = 0 # macro +mmCP_CE_ROQ_IB1_STAT = 0x0f89 # macro +mmCP_CE_ROQ_IB1_STAT_BASE_IDX = 0 # macro +mmCP_CE_ROQ_IB2_STAT = 0x0f8a # macro +mmCP_CE_ROQ_IB2_STAT_BASE_IDX = 0 # macro +mmCP_CE_ROQ_DB_STAT = 0x0f8b # macro +mmCP_CE_ROQ_DB_STAT_BASE_IDX = 0 # macro +mmCP_ROQ3_THRESHOLDS = 0x0f8c # macro +mmCP_ROQ3_THRESHOLDS_BASE_IDX = 0 # macro +mmCP_ROQ_DB_STAT = 0x0f8d # macro +mmCP_ROQ_DB_STAT_BASE_IDX = 0 # macro +mmCP_PRIV_VIOLATION_ADDR = 0x0f9a # macro +mmCP_PRIV_VIOLATION_ADDR_BASE_IDX = 0 # macro +mmVGT_CACHE_INVALIDATION = 0x0fc0 # macro +mmVGT_CACHE_INVALIDATION_BASE_IDX = 0 # macro +mmVGT_ESGS_RING_SIZE = 0x0fc1 # macro +mmVGT_ESGS_RING_SIZE_BASE_IDX = 0 # macro +mmVGT_GSVS_RING_SIZE = 0x0fc2 # macro +mmVGT_GSVS_RING_SIZE_BASE_IDX = 0 # macro +mmVGT_TF_RING_SIZE = 0x0fc3 # macro +mmVGT_TF_RING_SIZE_BASE_IDX = 0 # macro +mmVGT_HS_OFFCHIP_PARAM = 0x0fc4 # macro +mmVGT_HS_OFFCHIP_PARAM_BASE_IDX = 0 # macro +mmVGT_TF_MEMORY_BASE = 0x0fc5 # macro +mmVGT_TF_MEMORY_BASE_BASE_IDX = 0 # macro +mmVGT_TF_MEMORY_BASE_HI = 0x0fc6 # macro +mmVGT_TF_MEMORY_BASE_HI_BASE_IDX = 0 # macro +mmVGT_VTX_VECT_EJECT_REG = 0x0fcc # macro +mmVGT_VTX_VECT_EJECT_REG_BASE_IDX = 0 # macro +mmVGT_DMA_DATA_FIFO_DEPTH = 0x0fcd # macro +mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX = 0 # macro +mmVGT_DMA_REQ_FIFO_DEPTH = 0x0fce # macro +mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX = 0 # macro +mmVGT_DRAW_INIT_FIFO_DEPTH = 0x0fcf # macro +mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX = 0 # macro +mmVGT_LAST_COPY_STATE = 0x0fd0 # macro +mmVGT_LAST_COPY_STATE_BASE_IDX = 0 # macro +mmVGT_FIFO_DEPTHS = 0x0fd4 # macro +mmVGT_FIFO_DEPTHS_BASE_IDX = 0 # macro +mmVGT_GS_VERTEX_REUSE = 0x0fd5 # macro +mmVGT_GS_VERTEX_REUSE_BASE_IDX = 0 # macro +mmVGT_MC_LAT_CNTL = 0x0fd6 # macro +mmVGT_MC_LAT_CNTL_BASE_IDX = 0 # macro +mmIA_UTCL1_STATUS_2 = 0x0fd7 # macro +mmIA_UTCL1_STATUS_2_BASE_IDX = 0 # macro +mmWD_CNTL_STATUS = 0x0fdf # macro +mmWD_CNTL_STATUS_BASE_IDX = 0 # macro +mmCC_GC_PRIM_CONFIG = 0x0fe0 # macro +mmCC_GC_PRIM_CONFIG_BASE_IDX = 0 # macro +mmGC_USER_PRIM_CONFIG = 0x0fe1 # macro +mmGC_USER_PRIM_CONFIG_BASE_IDX = 0 # macro +mmWD_QOS = 0x0fe2 # macro +mmWD_QOS_BASE_IDX = 0 # macro +mmWD_UTCL1_CNTL = 0x0fe3 # macro +mmWD_UTCL1_CNTL_BASE_IDX = 0 # macro +mmWD_UTCL1_STATUS = 0x0fe4 # macro +mmWD_UTCL1_STATUS_BASE_IDX = 0 # macro +mmGE_PC_CNTL = 0x0fe5 # macro +mmGE_PC_CNTL_BASE_IDX = 0 # macro +mmIA_UTCL1_CNTL = 0x0fe6 # macro +mmIA_UTCL1_CNTL_BASE_IDX = 0 # macro +mmIA_UTCL1_STATUS = 0x0fe7 # macro +mmIA_UTCL1_STATUS_BASE_IDX = 0 # macro +mmCC_GC_SA_UNIT_DISABLE = 0x0fe9 # macro +mmCC_GC_SA_UNIT_DISABLE_BASE_IDX = 0 # macro +mmGC_USER_SA_UNIT_DISABLE = 0x0fea # macro +mmGC_USER_SA_UNIT_DISABLE_BASE_IDX = 0 # macro +mmVGT_SYS_CONFIG = 0x1003 # macro +mmVGT_SYS_CONFIG_BASE_IDX = 0 # macro +mmGE_PRIV_CONTROL = 0x1004 # macro +mmGE_PRIV_CONTROL_BASE_IDX = 0 # macro +mmGE_STATUS = 0x1005 # macro +mmGE_STATUS_BASE_IDX = 0 # macro +mmVGT_VS_MAX_WAVE_ID = 0x1008 # macro +mmVGT_VS_MAX_WAVE_ID_BASE_IDX = 0 # macro +mmVGT_GS_MAX_WAVE_ID = 0x1009 # macro +mmVGT_GS_MAX_WAVE_ID_BASE_IDX = 0 # macro +mmCC_GC_SHADER_ARRAY_CONFIG_GEN1 = 0x100a # macro +mmCC_GC_SHADER_ARRAY_CONFIG_GEN1_BASE_IDX = 0 # macro +mmCC_GC_SHADER_ARRAY_CONFIG_GEN0 = 0x100b # macro +mmCC_GC_SHADER_ARRAY_CONFIG_GEN0_BASE_IDX = 0 # macro +mmGFX_PIPE_CONTROL = 0x100d # macro +mmGFX_PIPE_CONTROL_BASE_IDX = 0 # macro +mmCC_GC_SHADER_ARRAY_CONFIG = 0x100f # macro +mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro +mmGC_USER_SHADER_ARRAY_CONFIG = 0x1010 # macro +mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX = 0 # macro +mmVGT_DMA_PRIMITIVE_TYPE = 0x1011 # macro +mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX = 0 # macro +mmVGT_DMA_CONTROL = 0x1012 # macro +mmVGT_DMA_CONTROL_BASE_IDX = 0 # macro +mmVGT_DMA_LS_HS_CONFIG = 0x1013 # macro +mmVGT_DMA_LS_HS_CONFIG_BASE_IDX = 0 # macro +mmVGT_STRMOUT_DELAY = 0x1015 # macro +mmVGT_STRMOUT_DELAY_BASE_IDX = 0 # macro +mmWD_BUF_RESOURCE_1 = 0x1016 # macro +mmWD_BUF_RESOURCE_1_BASE_IDX = 0 # macro +mmWD_BUF_RESOURCE_2 = 0x1017 # macro +mmWD_BUF_RESOURCE_2_BASE_IDX = 0 # macro +mmPA_CL_CNTL_STATUS = 0x1024 # macro +mmPA_CL_CNTL_STATUS_BASE_IDX = 0 # macro +mmPA_CL_ENHANCE = 0x1025 # macro +mmPA_CL_ENHANCE_BASE_IDX = 0 # macro +mmPA_SU_CNTL_STATUS = 0x1034 # macro +mmPA_SU_CNTL_STATUS_BASE_IDX = 0 # macro +mmPA_SC_FIFO_DEPTH_CNTL = 0x1035 # macro +mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX = 0 # macro +mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK = 0x1060 # macro +mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 0 # macro +mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK = 0x1061 # macro +mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX = 0 # macro +mmPA_SC_TRAP_SCREEN_HV_LOCK = 0x1062 # macro +mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX = 0 # macro +mmPA_SC_FORCE_EOV_MAX_CNTS = 0x1069 # macro +mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX = 0 # macro +mmPA_SC_BINNER_EVENT_CNTL_0 = 0x106c # macro +mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX = 0 # macro +mmPA_SC_BINNER_EVENT_CNTL_1 = 0x106d # macro +mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX = 0 # macro +mmPA_SC_BINNER_EVENT_CNTL_2 = 0x106e # macro +mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX = 0 # macro +mmPA_SC_BINNER_EVENT_CNTL_3 = 0x106f # macro +mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX = 0 # macro +mmPA_SC_BINNER_TIMEOUT_COUNTER = 0x1070 # macro +mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX = 0 # macro +mmPA_SC_BINNER_PERF_CNTL_0 = 0x1071 # macro +mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX = 0 # macro +mmPA_SC_BINNER_PERF_CNTL_1 = 0x1072 # macro +mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX = 0 # macro +mmPA_SC_BINNER_PERF_CNTL_2 = 0x1073 # macro +mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX = 0 # macro +mmPA_SC_BINNER_PERF_CNTL_3 = 0x1074 # macro +mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX = 0 # macro +mmPA_SC_ENHANCE_2 = 0x107c # macro +mmPA_SC_ENHANCE_2_BASE_IDX = 0 # macro +mmPA_SC_ENHANCE_INTERNAL = 0x107d # macro +mmPA_SC_ENHANCE_INTERNAL_BASE_IDX = 0 # macro +mmPA_SC_BINNER_CNTL_OVERRIDE = 0x107e # macro +mmPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX = 0 # macro +mmPA_SC_PBB_OVERRIDE_FLAG = 0x107f # macro +mmPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX = 0 # macro +mmPA_PH_INTERFACE_FIFO_SIZE = 0x1080 # macro +mmPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX = 0 # macro +mmPA_PH_ENHANCE = 0x1081 # macro +mmPA_PH_ENHANCE_BASE_IDX = 0 # macro +mmPA_SC_BC_WAVE_BREAK = 0x1084 # macro +mmPA_SC_BC_WAVE_BREAK_BASE_IDX = 0 # macro +mmPA_SC_ENHANCE_3 = 0x1085 # macro +mmPA_SC_ENHANCE_3_BASE_IDX = 0 # macro +mmPA_SC_FIFO_SIZE = 0x1093 # macro +mmPA_SC_FIFO_SIZE_BASE_IDX = 0 # macro +mmPA_SC_IF_FIFO_SIZE = 0x1095 # macro +mmPA_SC_IF_FIFO_SIZE_BASE_IDX = 0 # macro +mmPA_SC_PKR_WAVE_TABLE_CNTL = 0x1098 # macro +mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX = 0 # macro +mmPA_SIDEBAND_REQUEST_DELAYS = 0x109b # macro +mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX = 0 # macro +mmPA_SC_ENHANCE = 0x109c # macro +mmPA_SC_ENHANCE_BASE_IDX = 0 # macro +mmPA_SC_ENHANCE_1 = 0x109d # macro +mmPA_SC_ENHANCE_1_BASE_IDX = 0 # macro +mmPA_SC_DSM_CNTL = 0x109e # macro +mmPA_SC_DSM_CNTL_BASE_IDX = 0 # macro +mmPA_SC_TILE_STEERING_CREST_OVERRIDE = 0x109f # macro +mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX = 0 # macro +mmSQ_CONFIG = 0x10a0 # macro +mmSQ_CONFIG_BASE_IDX = 0 # macro +mmSQC_CONFIG = 0x10a1 # macro +mmSQC_CONFIG_BASE_IDX = 0 # macro +mmLDS_CONFIG = 0x10a2 # macro +mmLDS_CONFIG_BASE_IDX = 0 # macro +mmSQ_RANDOM_WAVE_PRI = 0x10a3 # macro +mmSQ_RANDOM_WAVE_PRI_BASE_IDX = 0 # macro +mmSQG_STATUS = 0x10a4 # macro +mmSQG_STATUS_BASE_IDX = 0 # macro +mmSQ_FIFO_SIZES = 0x10a5 # macro +mmSQ_FIFO_SIZES_BASE_IDX = 0 # macro +mmSQ_DSM_CNTL = 0x10a6 # macro +mmSQ_DSM_CNTL_BASE_IDX = 0 # macro +mmSQ_DSM_CNTL2 = 0x10a7 # macro +mmSQ_DSM_CNTL2_BASE_IDX = 0 # macro +mmSQ_RUNTIME_CONFIG = 0x10a8 # macro +mmSQ_RUNTIME_CONFIG_BASE_IDX = 0 # macro +mmSH_MEM_BASES = 0x10aa # macro +mmSH_MEM_BASES_BASE_IDX = 0 # macro +mmSP_CONFIG = 0x10ab # macro +mmSP_CONFIG_BASE_IDX = 0 # macro +mmSQ_ARB_CONFIG = 0x10ac # macro +mmSQ_ARB_CONFIG_BASE_IDX = 0 # macro +mmSH_MEM_CONFIG = 0x10ad # macro +mmSH_MEM_CONFIG_BASE_IDX = 0 # macro +mmSQ_SHADER_TBA_LO = 0x10b2 # macro +mmSQ_SHADER_TBA_LO_BASE_IDX = 0 # macro +mmSQ_SHADER_TBA_HI = 0x10b3 # macro +mmSQ_SHADER_TBA_HI_BASE_IDX = 0 # macro +mmSQ_SHADER_TMA_LO = 0x10b4 # macro +mmSQ_SHADER_TMA_LO_BASE_IDX = 0 # macro +mmSQ_SHADER_TMA_HI = 0x10b5 # macro +mmSQ_SHADER_TMA_HI_BASE_IDX = 0 # macro +mmSQG_UTCL0_CNTL1 = 0x10b7 # macro +mmSQG_UTCL0_CNTL1_BASE_IDX = 0 # macro +mmSQG_UTCL0_CNTL2 = 0x10b8 # macro +mmSQG_UTCL0_CNTL2_BASE_IDX = 0 # macro +mmSQG_UTCL0_STATUS = 0x10b9 # macro +mmSQG_UTCL0_STATUS_BASE_IDX = 0 # macro +mmSQG_CONFIG = 0x10ba # macro +mmSQG_CONFIG_BASE_IDX = 0 # macro +mmCC_GC_SHADER_RATE_CONFIG = 0x10bc # macro +mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro +mmGC_USER_SHADER_RATE_CONFIG = 0x10bd # macro +mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX = 0 # macro +mmSQ_INTERRUPT_AUTO_MASK = 0x10be # macro +mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX = 0 # macro +mmSQ_INTERRUPT_MSG_CTRL = 0x10bf # macro +mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX = 0 # macro +mmSQ_WATCH0_ADDR_H = 0x10d0 # macro +mmSQ_WATCH0_ADDR_H_BASE_IDX = 0 # macro +mmSQ_WATCH0_ADDR_L = 0x10d1 # macro +mmSQ_WATCH0_ADDR_L_BASE_IDX = 0 # macro +mmSQ_WATCH0_CNTL = 0x10d2 # macro +mmSQ_WATCH0_CNTL_BASE_IDX = 0 # macro +mmSQ_WATCH1_ADDR_H = 0x10d3 # macro +mmSQ_WATCH1_ADDR_H_BASE_IDX = 0 # macro +mmSQ_WATCH1_ADDR_L = 0x10d4 # macro +mmSQ_WATCH1_ADDR_L_BASE_IDX = 0 # macro +mmSQ_WATCH1_CNTL = 0x10d5 # macro +mmSQ_WATCH1_CNTL_BASE_IDX = 0 # macro +mmSQ_WATCH2_ADDR_H = 0x10d6 # macro +mmSQ_WATCH2_ADDR_H_BASE_IDX = 0 # macro +mmSQ_WATCH2_ADDR_L = 0x10d7 # macro +mmSQ_WATCH2_ADDR_L_BASE_IDX = 0 # macro +mmSQ_WATCH2_CNTL = 0x10d8 # macro +mmSQ_WATCH2_CNTL_BASE_IDX = 0 # macro +mmSQ_WATCH3_ADDR_H = 0x10d9 # macro +mmSQ_WATCH3_ADDR_H_BASE_IDX = 0 # macro +mmSQ_WATCH3_ADDR_L = 0x10da # macro +mmSQ_WATCH3_ADDR_L_BASE_IDX = 0 # macro +mmSQ_WATCH3_CNTL = 0x10db # macro +mmSQ_WATCH3_CNTL_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_BUF0_BASE = 0x10e0 # macro +mmSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_BUF0_SIZE = 0x10e1 # macro +mmSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_BUF1_BASE = 0x10e2 # macro +mmSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_BUF1_SIZE = 0x10e3 # macro +mmSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_WPTR = 0x10e4 # macro +mmSQ_THREAD_TRACE_WPTR_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_MASK = 0x10e5 # macro +mmSQ_THREAD_TRACE_MASK_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_TOKEN_MASK = 0x10e6 # macro +mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_CTRL = 0x10e7 # macro +mmSQ_THREAD_TRACE_CTRL_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_STATUS = 0x10e8 # macro +mmSQ_THREAD_TRACE_STATUS_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_DROPPED_CNTR = 0x10e9 # macro +mmSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_GFX_DRAW_CNTR = 0x10eb # macro +mmSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_GFX_MARKER_CNTR = 0x10ec # macro +mmSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR = 0x10ed # macro +mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR = 0x10ee # macro +mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX = 0 # macro +mmSQ_THREAD_TRACE_STATUS2 = 0x10ef # macro +mmSQ_THREAD_TRACE_STATUS2_BASE_IDX = 0 # macro +mmSQ_IND_INDEX = 0x1118 # macro +mmSQ_IND_INDEX_BASE_IDX = 0 # macro +mmSQ_IND_DATA = 0x1119 # macro +mmSQ_IND_DATA_BASE_IDX = 0 # macro +mmSQ_CMD = 0x111b # macro +mmSQ_CMD_BASE_IDX = 0 # macro +mmSQ_TIME_HI = 0x111c # macro +mmSQ_TIME_HI_BASE_IDX = 0 # macro +mmSQ_TIME_LO = 0x111d # macro +mmSQ_TIME_LO_BASE_IDX = 0 # macro +mmSQ_LB_CTR_CTRL = 0x1138 # macro +mmSQ_LB_CTR_CTRL_BASE_IDX = 0 # macro +mmSQ_LB_DATA0 = 0x1139 # macro +mmSQ_LB_DATA0_BASE_IDX = 0 # macro +mmSQ_LB_DATA1 = 0x113a # macro +mmSQ_LB_DATA1_BASE_IDX = 0 # macro +mmSQ_LB_DATA2 = 0x113b # macro +mmSQ_LB_DATA2_BASE_IDX = 0 # macro +mmSQ_LB_DATA3 = 0x113c # macro +mmSQ_LB_DATA3_BASE_IDX = 0 # macro +mmSQ_LB_CTR_SEL0 = 0x113d # macro +mmSQ_LB_CTR_SEL0_BASE_IDX = 0 # macro +mmSQ_LB_CTR_SEL1 = 0x113e # macro +mmSQ_LB_CTR_SEL1_BASE_IDX = 0 # macro +mmSQ_EDC_CNT = 0x1146 # macro +mmSQ_EDC_CNT_BASE_IDX = 0 # macro +mmSQ_EDC_FUE_CNTL = 0x1147 # macro +mmSQ_EDC_FUE_CNTL_BASE_IDX = 0 # macro +mmSQ_WREXEC_EXEC_HI = 0x1151 # macro +mmSQ_WREXEC_EXEC_HI_BASE_IDX = 0 # macro +mmSQ_WREXEC_EXEC_LO = 0x1151 # macro +mmSQ_WREXEC_EXEC_LO_BASE_IDX = 0 # macro +mmSQC_ICACHE_UTCL0_CNTL1 = 0x1173 # macro +mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX = 0 # macro +mmSQC_ICACHE_UTCL0_CNTL2 = 0x1174 # macro +mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX = 0 # macro +mmSQC_DCACHE_UTCL0_CNTL1 = 0x1175 # macro +mmSQC_DCACHE_UTCL0_CNTL1_BASE_IDX = 0 # macro +mmSQC_DCACHE_UTCL0_CNTL2 = 0x1176 # macro +mmSQC_DCACHE_UTCL0_CNTL2_BASE_IDX = 0 # macro +mmSQC_ICACHE_UTCL0_STATUS = 0x1177 # macro +mmSQC_ICACHE_UTCL0_STATUS_BASE_IDX = 0 # macro +mmSQC_DCACHE_UTCL0_STATUS = 0x1178 # macro +mmSQC_DCACHE_UTCL0_STATUS_BASE_IDX = 0 # macro +mmSX_DEBUG_1 = 0x11b8 # macro +mmSX_DEBUG_1_BASE_IDX = 0 # macro +mmSPI_PS_MAX_WAVE_ID = 0x11da # macro +mmSPI_PS_MAX_WAVE_ID_BASE_IDX = 0 # macro +mmSPI_START_PHASE = 0x11db # macro +mmSPI_START_PHASE_BASE_IDX = 0 # macro +mmSPI_GFX_CNTL = 0x11dc # macro +mmSPI_GFX_CNTL_BASE_IDX = 0 # macro +mmSPI_DSM_CNTL = 0x11e3 # macro +mmSPI_DSM_CNTL_BASE_IDX = 0 # macro +mmSPI_DSM_CNTL2 = 0x11e4 # macro +mmSPI_DSM_CNTL2_BASE_IDX = 0 # macro +mmSPI_EDC_CNT = 0x11e5 # macro +mmSPI_EDC_CNT_BASE_IDX = 0 # macro +mmSPI_USER_ACCUM_VMID_CNTL = 0x11eb # macro +mmSPI_USER_ACCUM_VMID_CNTL_BASE_IDX = 0 # macro +mmSPI_CONFIG_CNTL = 0x11ec # macro +mmSPI_CONFIG_CNTL_BASE_IDX = 0 # macro +mmSPI_WAVE_LIMIT_CNTL = 0x11ed # macro +mmSPI_WAVE_LIMIT_CNTL_BASE_IDX = 0 # macro +mmSPI_CONFIG_CNTL_2 = 0x11ee # macro +mmSPI_CONFIG_CNTL_2_BASE_IDX = 0 # macro +mmSPI_CONFIG_CNTL_1 = 0x11ef # macro +mmSPI_CONFIG_CNTL_1_BASE_IDX = 0 # macro +mmSPI_CONFIG_PS_CU_EN = 0x11f2 # macro +mmSPI_CONFIG_PS_CU_EN_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_CNTL = 0x124a # macro +mmSPI_WF_LIFETIME_CNTL_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_LIMIT_0 = 0x124b # macro +mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_LIMIT_1 = 0x124c # macro +mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_LIMIT_2 = 0x124d # macro +mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_LIMIT_3 = 0x124e # macro +mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_LIMIT_4 = 0x124f # macro +mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_LIMIT_5 = 0x1250 # macro +mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_0 = 0x1255 # macro +mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_1 = 0x1256 # macro +mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_2 = 0x1257 # macro +mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_4 = 0x1259 # macro +mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_6 = 0x125b # macro +mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_7 = 0x125c # macro +mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_8 = 0x125d # macro +mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_9 = 0x125e # macro +mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_11 = 0x1260 # macro +mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_13 = 0x1262 # macro +mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_14 = 0x1263 # macro +mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_15 = 0x1264 # macro +mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_16 = 0x1265 # macro +mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_17 = 0x1266 # macro +mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_18 = 0x1267 # macro +mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_19 = 0x1268 # macro +mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_20 = 0x1269 # macro +mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX = 0 # macro +mmSPI_WF_LIFETIME_STATUS_21 = 0x126b # macro +mmSPI_WF_LIFETIME_STATUS_21_BASE_IDX = 0 # macro +mmSPI_LB_CTR_CTRL = 0x1274 # macro +mmSPI_LB_CTR_CTRL_BASE_IDX = 0 # macro +mmSPI_LB_WGP_MASK = 0x1275 # macro +mmSPI_LB_WGP_MASK_BASE_IDX = 0 # macro +mmSPI_LB_DATA_REG = 0x1276 # macro +mmSPI_LB_DATA_REG_BASE_IDX = 0 # macro +mmSPI_PG_ENABLE_STATIC_WGP_MASK = 0x1277 # macro +mmSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX = 0 # macro +mmSPI_GDS_CREDITS = 0x1278 # macro +mmSPI_GDS_CREDITS_BASE_IDX = 0 # macro +mmSPI_SX_EXPORT_BUFFER_SIZES = 0x1279 # macro +mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX = 0 # macro +mmSPI_SX_SCOREBOARD_BUFFER_SIZES = 0x127a # macro +mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX = 0 # macro +mmSPI_CSQ_WF_ACTIVE_STATUS = 0x127b # macro +mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX = 0 # macro +mmSPI_CSQ_WF_ACTIVE_COUNT_0 = 0x127c # macro +mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX = 0 # macro +mmSPI_CSQ_WF_ACTIVE_COUNT_1 = 0x127d # macro +mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX = 0 # macro +mmSPI_CSQ_WF_ACTIVE_COUNT_2 = 0x127e # macro +mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX = 0 # macro +mmSPI_CSQ_WF_ACTIVE_COUNT_3 = 0x127f # macro +mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX = 0 # macro +mmSPI_LB_DATA_WAVES = 0x1284 # macro +mmSPI_LB_DATA_WAVES_BASE_IDX = 0 # macro +mmSPI_LB_DATA_PERWGP_WAVE_HSGS = 0x1285 # macro +mmSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX = 0 # macro +mmSPI_LB_DATA_PERWGP_WAVE_VSPS = 0x1286 # macro +mmSPI_LB_DATA_PERWGP_WAVE_VSPS_BASE_IDX = 0 # macro +mmSPI_LB_DATA_PERWGP_WAVE_CS = 0x1287 # macro +mmSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX = 0 # macro +mmSPI_P0_TRAP_SCREEN_PSBA_LO = 0x128c # macro +mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro +mmSPI_P0_TRAP_SCREEN_PSBA_HI = 0x128d # macro +mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro +mmSPI_P0_TRAP_SCREEN_PSMA_LO = 0x128e # macro +mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro +mmSPI_P0_TRAP_SCREEN_PSMA_HI = 0x128f # macro +mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro +mmSPI_P0_TRAP_SCREEN_GPR_MIN = 0x1290 # macro +mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro +mmSPI_P1_TRAP_SCREEN_PSBA_LO = 0x1291 # macro +mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX = 0 # macro +mmSPI_P1_TRAP_SCREEN_PSBA_HI = 0x1292 # macro +mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX = 0 # macro +mmSPI_P1_TRAP_SCREEN_PSMA_LO = 0x1293 # macro +mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX = 0 # macro +mmSPI_P1_TRAP_SCREEN_PSMA_HI = 0x1294 # macro +mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX = 0 # macro +mmSPI_P1_TRAP_SCREEN_GPR_MIN = 0x1295 # macro +mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX = 0 # macro +mmTD_STATUS = 0x12c6 # macro +mmTD_STATUS_BASE_IDX = 0 # macro +mmTD_DSM_CNTL = 0x12cf # macro +mmTD_DSM_CNTL_BASE_IDX = 0 # macro +mmTD_DSM_CNTL2 = 0x12d0 # macro +mmTD_DSM_CNTL2_BASE_IDX = 0 # macro +mmTD_SCRATCH = 0x12d3 # macro +mmTD_SCRATCH_BASE_IDX = 0 # macro +mmTA_CNTL = 0x12e1 # macro +mmTA_CNTL_BASE_IDX = 0 # macro +mmTA_RESERVED_010C = 0x12e3 # macro +mmTA_RESERVED_010C_BASE_IDX = 0 # macro +mmTA_STATUS = 0x12e8 # macro +mmTA_STATUS_BASE_IDX = 0 # macro +mmTA_SCRATCH = 0x1304 # macro +mmTA_SCRATCH_BASE_IDX = 0 # macro +mmGDS_CONFIG = 0x1360 # macro +mmGDS_CONFIG_BASE_IDX = 0 # macro +mmGDS_CNTL_STATUS = 0x1361 # macro +mmGDS_CNTL_STATUS_BASE_IDX = 0 # macro +mmGDS_ENHANCE = 0x1362 # macro +mmGDS_ENHANCE_BASE_IDX = 0 # macro +mmGDS_PROTECTION_FAULT = 0x1363 # macro +mmGDS_PROTECTION_FAULT_BASE_IDX = 0 # macro +mmGDS_VM_PROTECTION_FAULT = 0x1364 # macro +mmGDS_VM_PROTECTION_FAULT_BASE_IDX = 0 # macro +mmGDS_EDC_CNT = 0x1365 # macro +mmGDS_EDC_CNT_BASE_IDX = 0 # macro +mmGDS_EDC_GRBM_CNT = 0x1366 # macro +mmGDS_EDC_GRBM_CNT_BASE_IDX = 0 # macro +mmGDS_EDC_OA_DED = 0x1367 # macro +mmGDS_EDC_OA_DED_BASE_IDX = 0 # macro +mmGDS_DSM_CNTL = 0x136a # macro +mmGDS_DSM_CNTL_BASE_IDX = 0 # macro +mmGDS_EDC_OA_PHY_CNT = 0x136b # macro +mmGDS_EDC_OA_PHY_CNT_BASE_IDX = 0 # macro +mmGDS_EDC_OA_PIPE_CNT = 0x136c # macro +mmGDS_EDC_OA_PIPE_CNT_BASE_IDX = 0 # macro +mmGDS_DSM_CNTL2 = 0x136d # macro +mmGDS_DSM_CNTL2_BASE_IDX = 0 # macro +mmGDS_WD_GDS_CSB = 0x136e # macro +mmGDS_WD_GDS_CSB_BASE_IDX = 0 # macro +mmDB_DEBUG = 0x13ac # macro +mmDB_DEBUG_BASE_IDX = 0 # macro +mmDB_DEBUG2 = 0x13ad # macro +mmDB_DEBUG2_BASE_IDX = 0 # macro +mmDB_DEBUG3 = 0x13ae # macro +mmDB_DEBUG3_BASE_IDX = 0 # macro +mmDB_DEBUG4 = 0x13af # macro +mmDB_DEBUG4_BASE_IDX = 0 # macro +mmDB_ETILE_STUTTER_CONTROL = 0x13b0 # macro +mmDB_ETILE_STUTTER_CONTROL_BASE_IDX = 0 # macro +mmDB_LTILE_STUTTER_CONTROL = 0x13b1 # macro +mmDB_LTILE_STUTTER_CONTROL_BASE_IDX = 0 # macro +mmDB_EQUAD_STUTTER_CONTROL = 0x13b2 # macro +mmDB_EQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro +mmDB_LQUAD_STUTTER_CONTROL = 0x13b3 # macro +mmDB_LQUAD_STUTTER_CONTROL_BASE_IDX = 0 # macro +mmDB_CREDIT_LIMIT = 0x13b4 # macro +mmDB_CREDIT_LIMIT_BASE_IDX = 0 # macro +mmDB_WATERMARKS = 0x13b5 # macro +mmDB_WATERMARKS_BASE_IDX = 0 # macro +mmDB_SUBTILE_CONTROL = 0x13b6 # macro +mmDB_SUBTILE_CONTROL_BASE_IDX = 0 # macro +mmDB_FREE_CACHELINES = 0x13b7 # macro +mmDB_FREE_CACHELINES_BASE_IDX = 0 # macro +mmDB_FIFO_DEPTH1 = 0x13b8 # macro +mmDB_FIFO_DEPTH1_BASE_IDX = 0 # macro +mmDB_FIFO_DEPTH2 = 0x13b9 # macro +mmDB_FIFO_DEPTH2_BASE_IDX = 0 # macro +mmDB_LAST_OF_BURST_CONFIG = 0x13ba # macro +mmDB_LAST_OF_BURST_CONFIG_BASE_IDX = 0 # macro +mmDB_RING_CONTROL = 0x13bb # macro +mmDB_RING_CONTROL_BASE_IDX = 0 # macro +mmDB_MEM_ARB_WATERMARKS = 0x13bc # macro +mmDB_MEM_ARB_WATERMARKS_BASE_IDX = 0 # macro +mmDB_FIFO_DEPTH3 = 0x13bd # macro +mmDB_FIFO_DEPTH3_BASE_IDX = 0 # macro +mmDB_RMI_BC_GL2_CACHE_CONTROL = 0x13be # macro +mmDB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX = 0 # macro +mmDB_EXCEPTION_CONTROL = 0x13bf # macro +mmDB_EXCEPTION_CONTROL_BASE_IDX = 0 # macro +mmDB_DFSM_CONFIG = 0x13d0 # macro +mmDB_DFSM_CONFIG_BASE_IDX = 0 # macro +mmDB_DEBUG5 = 0x13d1 # macro +mmDB_DEBUG5_BASE_IDX = 0 # macro +mmDB_DFSM_TILES_IN_FLIGHT = 0x13d2 # macro +mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX = 0 # macro +mmDB_DFSM_PRIMS_IN_FLIGHT = 0x13d3 # macro +mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX = 0 # macro +mmDB_DFSM_WATCHDOG = 0x13d4 # macro +mmDB_DFSM_WATCHDOG_BASE_IDX = 0 # macro +mmDB_DFSM_FLUSH_ENABLE = 0x13d5 # macro +mmDB_DFSM_FLUSH_ENABLE_BASE_IDX = 0 # macro +mmDB_DFSM_FLUSH_AUX_EVENT = 0x13d6 # macro +mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX = 0 # macro +mmDB_FGCG_SRAMS_CLK_CTRL = 0x13d7 # macro +mmDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX = 0 # macro +mmDB_FGCG_INTERFACES_CLK_CTRL = 0x13d8 # macro +mmDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX = 0 # macro +mmCC_RB_REDUNDANCY = 0x13dc # macro +mmCC_RB_REDUNDANCY_BASE_IDX = 0 # macro +mmCC_RB_BACKEND_DISABLE = 0x13dd # macro +mmCC_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro +mmGB_ADDR_CONFIG = 0x13de # macro +mmGB_ADDR_CONFIG_BASE_IDX = 0 # macro +mmGB_BACKEND_MAP = 0x13df # macro +mmGB_BACKEND_MAP_BASE_IDX = 0 # macro +mmGB_GPU_ID = 0x13e0 # macro +mmGB_GPU_ID_BASE_IDX = 0 # macro +mmCC_RB_DAISY_CHAIN = 0x13e1 # macro +mmCC_RB_DAISY_CHAIN_BASE_IDX = 0 # macro +mmGB_ADDR_CONFIG_READ = 0x13e2 # macro +mmGB_ADDR_CONFIG_READ_BASE_IDX = 0 # macro +mmCB_HW_CONTROL_4 = 0x1422 # macro +mmCB_HW_CONTROL_4_BASE_IDX = 0 # macro +mmCB_HW_CONTROL_3 = 0x1423 # macro +mmCB_HW_CONTROL_3_BASE_IDX = 0 # macro +mmCB_HW_CONTROL = 0x1424 # macro +mmCB_HW_CONTROL_BASE_IDX = 0 # macro +mmCB_HW_CONTROL_1 = 0x1425 # macro +mmCB_HW_CONTROL_1_BASE_IDX = 0 # macro +mmCB_HW_CONTROL_2 = 0x1426 # macro +mmCB_HW_CONTROL_2_BASE_IDX = 0 # macro +mmCB_DCC_CONFIG = 0x1427 # macro +mmCB_DCC_CONFIG_BASE_IDX = 0 # macro +mmCB_HW_MEM_ARBITER_RD = 0x1428 # macro +mmCB_HW_MEM_ARBITER_RD_BASE_IDX = 0 # macro +mmCB_HW_MEM_ARBITER_WR = 0x1429 # macro +mmCB_HW_MEM_ARBITER_WR_BASE_IDX = 0 # macro +mmCB_RMI_BC_GL2_CACHE_CONTROL = 0x142a # macro +mmCB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX = 0 # macro +mmCB_STUTTER_CONTROL_CMASK_RDLAT = 0x142b # macro +mmCB_STUTTER_CONTROL_CMASK_RDLAT_BASE_IDX = 0 # macro +mmCB_STUTTER_CONTROL_FMASK_RDLAT = 0x142c # macro +mmCB_STUTTER_CONTROL_FMASK_RDLAT_BASE_IDX = 0 # macro +mmCB_STUTTER_CONTROL_COLOR_RDLAT = 0x142d # macro +mmCB_STUTTER_CONTROL_COLOR_RDLAT_BASE_IDX = 0 # macro +mmCB_CACHE_EVICT_POINTS = 0x142e # macro +mmCB_CACHE_EVICT_POINTS_BASE_IDX = 0 # macro +mmGC_USER_RB_REDUNDANCY = 0x147e # macro +mmGC_USER_RB_REDUNDANCY_BASE_IDX = 0 # macro +mmGC_USER_RB_BACKEND_DISABLE = 0x147f # macro +mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX = 0 # macro +mmGCEA_MISC = 0x14a2 # macro +mmGCEA_MISC_BASE_IDX = 0 # macro +mmGCEA_LATENCY_SAMPLING = 0x14a3 # macro +mmGCEA_LATENCY_SAMPLING_BASE_IDX = 0 # macro +mmGCEA_DSM_CNTL = 0x14b4 # macro +mmGCEA_DSM_CNTL_BASE_IDX = 0 # macro +mmGCEA_DSM_CNTLA = 0x14b5 # macro +mmGCEA_DSM_CNTLA_BASE_IDX = 0 # macro +mmGCEA_DSM_CNTLB = 0x14b6 # macro +mmGCEA_DSM_CNTLB_BASE_IDX = 0 # macro +mmGCEA_DSM_CNTL2 = 0x14b7 # macro +mmGCEA_DSM_CNTL2_BASE_IDX = 0 # macro +mmGCEA_DSM_CNTL2A = 0x14b8 # macro +mmGCEA_DSM_CNTL2A_BASE_IDX = 0 # macro +mmGCEA_DSM_CNTL2B = 0x14b9 # macro +mmGCEA_DSM_CNTL2B_BASE_IDX = 0 # macro +mmGCEA_GL2C_XBR_CREDITS = 0x14ba # macro +mmGCEA_GL2C_XBR_CREDITS_BASE_IDX = 0 # macro +mmGCEA_GL2C_XBR_MAXBURST = 0x14bb # macro +mmGCEA_GL2C_XBR_MAXBURST_BASE_IDX = 0 # macro +mmGCEA_PROBE_CNTL = 0x14bc # macro +mmGCEA_PROBE_CNTL_BASE_IDX = 0 # macro +mmGCEA_PROBE_MAP = 0x14bd # macro +mmGCEA_PROBE_MAP_BASE_IDX = 0 # macro +mmGCEA_ERR_STATUS = 0x14be # macro +mmGCEA_ERR_STATUS_BASE_IDX = 0 # macro +mmGCEA_MISC2 = 0x14bf # macro +mmGCEA_MISC2_BASE_IDX = 0 # macro +mmSPI_PQEV_CTRL = 0x14c0 # macro +mmSPI_PQEV_CTRL_BASE_IDX = 0 # macro +mmSPI_EXP_THROTTLE_CTRL = 0x14c3 # macro +mmSPI_EXP_THROTTLE_CTRL_BASE_IDX = 0 # macro +mmGCEA_RRET_MEM_RESERVE = 0x1518 # macro +mmGCEA_RRET_MEM_RESERVE_BASE_IDX = 0 # macro +mmRMI_GENERAL_CNTL = 0x1520 # macro +mmRMI_GENERAL_CNTL_BASE_IDX = 0 # macro +mmRMI_GENERAL_CNTL1 = 0x1521 # macro +mmRMI_GENERAL_CNTL1_BASE_IDX = 0 # macro +mmRMI_GENERAL_STATUS = 0x1522 # macro +mmRMI_GENERAL_STATUS_BASE_IDX = 0 # macro +mmRMI_SUBBLOCK_STATUS0 = 0x1523 # macro +mmRMI_SUBBLOCK_STATUS0_BASE_IDX = 0 # macro +mmRMI_SUBBLOCK_STATUS1 = 0x1524 # macro +mmRMI_SUBBLOCK_STATUS1_BASE_IDX = 0 # macro +mmRMI_SUBBLOCK_STATUS2 = 0x1525 # macro +mmRMI_SUBBLOCK_STATUS2_BASE_IDX = 0 # macro +mmRMI_SUBBLOCK_STATUS3 = 0x1526 # macro +mmRMI_SUBBLOCK_STATUS3_BASE_IDX = 0 # macro +mmRMI_XBAR_CONFIG = 0x1527 # macro +mmRMI_XBAR_CONFIG_BASE_IDX = 0 # macro +mmRMI_PROBE_POP_LOGIC_CNTL = 0x1528 # macro +mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX = 0 # macro +mmRMI_UTC_XNACK_N_MISC_CNTL = 0x1529 # macro +mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX = 0 # macro +mmRMI_DEMUX_CNTL = 0x152a # macro +mmRMI_DEMUX_CNTL_BASE_IDX = 0 # macro +mmRMI_UTCL1_CNTL1 = 0x152b # macro +mmRMI_UTCL1_CNTL1_BASE_IDX = 0 # macro +mmRMI_UTCL1_CNTL2 = 0x152c # macro +mmRMI_UTCL1_CNTL2_BASE_IDX = 0 # macro +mmRMI_UTC_UNIT_CONFIG = 0x152d # macro +mmRMI_UTC_UNIT_CONFIG_BASE_IDX = 0 # macro +mmRMI_TCIW_FORMATTER0_CNTL = 0x152e # macro +mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX = 0 # macro +mmRMI_TCIW_FORMATTER1_CNTL = 0x152f # macro +mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX = 0 # macro +mmRMI_SCOREBOARD_CNTL = 0x1530 # macro +mmRMI_SCOREBOARD_CNTL_BASE_IDX = 0 # macro +mmRMI_SCOREBOARD_STATUS0 = 0x1531 # macro +mmRMI_SCOREBOARD_STATUS0_BASE_IDX = 0 # macro +mmRMI_SCOREBOARD_STATUS1 = 0x1532 # macro +mmRMI_SCOREBOARD_STATUS1_BASE_IDX = 0 # macro +mmRMI_SCOREBOARD_STATUS2 = 0x1533 # macro +mmRMI_SCOREBOARD_STATUS2_BASE_IDX = 0 # macro +mmRMI_XBAR_ARBITER_CONFIG = 0x1534 # macro +mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX = 0 # macro +mmRMI_XBAR_ARBITER_CONFIG_1 = 0x1535 # macro +mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX = 0 # macro +mmRMI_CLOCK_CNTRL = 0x1536 # macro +mmRMI_CLOCK_CNTRL_BASE_IDX = 0 # macro +mmRMI_UTCL1_STATUS = 0x1537 # macro +mmRMI_UTCL1_STATUS_BASE_IDX = 0 # macro +mmRMI_RB_GLX_CID_MAP = 0x1538 # macro +mmRMI_RB_GLX_CID_MAP_BASE_IDX = 0 # macro +mmRMI_SPARE = 0x153f # macro +mmRMI_SPARE_BASE_IDX = 0 # macro +mmRMI_SPARE_1 = 0x1540 # macro +mmRMI_SPARE_1_BASE_IDX = 0 # macro +mmRMI_SPARE_2 = 0x1541 # macro +mmRMI_SPARE_2_BASE_IDX = 0 # macro +mmCC_RMI_REDUNDANCY = 0x1542 # macro +mmCC_RMI_REDUNDANCY_BASE_IDX = 0 # macro +mmGC_USER_RMI_REDUNDANCY = 0x1543 # macro +mmGC_USER_RMI_REDUNDANCY_BASE_IDX = 0 # macro +mmGCR_GENERAL_CNTL = 0x1580 # macro +mmGCR_GENERAL_CNTL_BASE_IDX = 0 # macro +mmGCR_CMD_STATUS = 0x1582 # macro +mmGCR_CMD_STATUS_BASE_IDX = 0 # macro +mmGCR_SPARE = 0x1583 # macro +mmGCR_SPARE_BASE_IDX = 0 # macro +mmPMM_GENERAL_CNTL = 0x1585 # macro +mmPMM_GENERAL_CNTL_BASE_IDX = 0 # macro +mmGCR_PIO_CNTL = 0x1586 # macro +mmGCR_PIO_CNTL_BASE_IDX = 0 # macro +mmGCR_PIO_DATA = 0x1587 # macro +mmGCR_PIO_DATA_BASE_IDX = 0 # macro +mmUTCL1_CTRL = 0x1588 # macro +mmUTCL1_CTRL_BASE_IDX = 0 # macro +mmUTCL1_ALOG = 0x1589 # macro +mmUTCL1_ALOG_BASE_IDX = 0 # macro +mmUTCL1_UTCL0_INVREQ_DISABLE = 0x158a # macro +mmUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX = 0 # macro +mmGCRD_SA_TARGETS_DISABLE = 0x158b # macro +mmGCRD_SA_TARGETS_DISABLE_BASE_IDX = 0 # macro +mmUTCL1_STATUS = 0x158c # macro +mmUTCL1_STATUS_BASE_IDX = 0 # macro +mmGCVM_L2_CNTL = 0x15bc # macro +mmGCVM_L2_CNTL_BASE_IDX = 0 # macro +mmGCVM_L2_CNTL2 = 0x15bd # macro +mmGCVM_L2_CNTL2_BASE_IDX = 0 # macro +mmGCVM_L2_CNTL3 = 0x15be # macro +mmGCVM_L2_CNTL3_BASE_IDX = 0 # macro +mmGCVM_L2_STATUS = 0x15bf # macro +mmGCVM_L2_STATUS_BASE_IDX = 0 # macro +mmGCVM_DUMMY_PAGE_FAULT_CNTL = 0x15c0 # macro +mmGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX = 0 # macro +mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 = 0x15c1 # macro +mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 = 0x15c2 # macro +mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_CNTL = 0x15c3 # macro +mmGCVM_INVALIDATE_CNTL_BASE_IDX = 0 # macro +mmGCVM_L2_PROTECTION_FAULT_CNTL = 0x15c4 # macro +mmGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX = 0 # macro +mmGCVM_L2_PROTECTION_FAULT_CNTL2 = 0x15c5 # macro +mmGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX = 0 # macro +mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3 = 0x15c6 # macro +mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX = 0 # macro +mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4 = 0x15c7 # macro +mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX = 0 # macro +mmGCVM_L2_PROTECTION_FAULT_STATUS = 0x15c8 # macro +mmGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX = 0 # macro +mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32 = 0x15c9 # macro +mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32 = 0x15ca # macro +mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 = 0x15cb # macro +mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 = 0x15cc # macro +mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_DEBUG = 0x15cd # macro +mmGCVM_DEBUG_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 = 0x15ce # macro +mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 = 0x15cf # macro +mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 = 0x15d0 # macro +mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 = 0x15d1 # macro +mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 = 0x15d2 # macro +mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 = 0x15d3 # macro +mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX = 0 # macro +mmGCVM_L2_CNTL4 = 0x15d4 # macro +mmGCVM_L2_CNTL4_BASE_IDX = 0 # macro +mmGCVM_L2_MM_GROUP_RT_CLASSES = 0x15d5 # macro +mmGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX = 0 # macro +mmGCVM_L2_BANK_SELECT_RESERVED_CID = 0x15d6 # macro +mmGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX = 0 # macro +mmGCVM_L2_BANK_SELECT_RESERVED_CID2 = 0x15d7 # macro +mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX = 0 # macro +mmGCVM_L2_CACHE_PARITY_CNTL = 0x15d8 # macro +mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX = 0 # macro +mmGCVM_L2_IH_LOG_CNTL = 0x15d9 # macro +mmGCVM_L2_IH_LOG_CNTL_BASE_IDX = 0 # macro +mmGCVM_L2_CNTL5 = 0x15dc # macro +mmGCVM_L2_CNTL5_BASE_IDX = 0 # macro +mmGCVM_L2_GCR_CNTL = 0x15dd # macro +mmGCVM_L2_GCR_CNTL_BASE_IDX = 0 # macro +mmGCVML2_WALKER_MACRO_THROTTLE_TIME = 0x15de # macro +mmGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX = 0 # macro +mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT = 0x15df # macro +mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro +mmGCVML2_WALKER_MICRO_THROTTLE_TIME = 0x15e0 # macro +mmGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX = 0 # macro +mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT = 0x15e1 # macro +mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX = 0 # macro +mmGCVM_L2_PTE_CACHE_DUMP_CNTL = 0x15e3 # macro +mmGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX = 0 # macro +mmGCVM_L2_PTE_CACHE_DUMP_READ = 0x15e4 # macro +mmGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX = 0 # macro +mmGCVM_CONTEXT0_CNTL = 0x15fc # macro +mmGCVM_CONTEXT0_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT1_CNTL = 0x15fd # macro +mmGCVM_CONTEXT1_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT2_CNTL = 0x15fe # macro +mmGCVM_CONTEXT2_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT3_CNTL = 0x15ff # macro +mmGCVM_CONTEXT3_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT4_CNTL = 0x1600 # macro +mmGCVM_CONTEXT4_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT5_CNTL = 0x1601 # macro +mmGCVM_CONTEXT5_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT6_CNTL = 0x1602 # macro +mmGCVM_CONTEXT6_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT7_CNTL = 0x1603 # macro +mmGCVM_CONTEXT7_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT8_CNTL = 0x1604 # macro +mmGCVM_CONTEXT8_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT9_CNTL = 0x1605 # macro +mmGCVM_CONTEXT9_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT10_CNTL = 0x1606 # macro +mmGCVM_CONTEXT10_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT11_CNTL = 0x1607 # macro +mmGCVM_CONTEXT11_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT12_CNTL = 0x1608 # macro +mmGCVM_CONTEXT12_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT13_CNTL = 0x1609 # macro +mmGCVM_CONTEXT13_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT14_CNTL = 0x160a # macro +mmGCVM_CONTEXT14_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXT15_CNTL = 0x160b # macro +mmGCVM_CONTEXT15_CNTL_BASE_IDX = 0 # macro +mmGCVM_CONTEXTS_DISABLE = 0x160c # macro +mmGCVM_CONTEXTS_DISABLE_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG0_SEM = 0x160d # macro +mmGCVM_INVALIDATE_ENG0_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG1_SEM = 0x160e # macro +mmGCVM_INVALIDATE_ENG1_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG2_SEM = 0x160f # macro +mmGCVM_INVALIDATE_ENG2_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG3_SEM = 0x1610 # macro +mmGCVM_INVALIDATE_ENG3_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG4_SEM = 0x1611 # macro +mmGCVM_INVALIDATE_ENG4_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG5_SEM = 0x1612 # macro +mmGCVM_INVALIDATE_ENG5_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG6_SEM = 0x1613 # macro +mmGCVM_INVALIDATE_ENG6_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG7_SEM = 0x1614 # macro +mmGCVM_INVALIDATE_ENG7_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG8_SEM = 0x1615 # macro +mmGCVM_INVALIDATE_ENG8_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG9_SEM = 0x1616 # macro +mmGCVM_INVALIDATE_ENG9_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG10_SEM = 0x1617 # macro +mmGCVM_INVALIDATE_ENG10_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG11_SEM = 0x1618 # macro +mmGCVM_INVALIDATE_ENG11_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG12_SEM = 0x1619 # macro +mmGCVM_INVALIDATE_ENG12_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG13_SEM = 0x161a # macro +mmGCVM_INVALIDATE_ENG13_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG14_SEM = 0x161b # macro +mmGCVM_INVALIDATE_ENG14_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG15_SEM = 0x161c # macro +mmGCVM_INVALIDATE_ENG15_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG16_SEM = 0x161d # macro +mmGCVM_INVALIDATE_ENG16_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG17_SEM = 0x161e # macro +mmGCVM_INVALIDATE_ENG17_SEM_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG0_REQ = 0x161f # macro +mmGCVM_INVALIDATE_ENG0_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG1_REQ = 0x1620 # macro +mmGCVM_INVALIDATE_ENG1_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG2_REQ = 0x1621 # macro +mmGCVM_INVALIDATE_ENG2_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG3_REQ = 0x1622 # macro +mmGCVM_INVALIDATE_ENG3_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG4_REQ = 0x1623 # macro +mmGCVM_INVALIDATE_ENG4_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG5_REQ = 0x1624 # macro +mmGCVM_INVALIDATE_ENG5_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG6_REQ = 0x1625 # macro +mmGCVM_INVALIDATE_ENG6_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG7_REQ = 0x1626 # macro +mmGCVM_INVALIDATE_ENG7_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG8_REQ = 0x1627 # macro +mmGCVM_INVALIDATE_ENG8_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG9_REQ = 0x1628 # macro +mmGCVM_INVALIDATE_ENG9_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG10_REQ = 0x1629 # macro +mmGCVM_INVALIDATE_ENG10_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG11_REQ = 0x162a # macro +mmGCVM_INVALIDATE_ENG11_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG12_REQ = 0x162b # macro +mmGCVM_INVALIDATE_ENG12_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG13_REQ = 0x162c # macro +mmGCVM_INVALIDATE_ENG13_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG14_REQ = 0x162d # macro +mmGCVM_INVALIDATE_ENG14_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG15_REQ = 0x162e # macro +mmGCVM_INVALIDATE_ENG15_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG16_REQ = 0x162f # macro +mmGCVM_INVALIDATE_ENG16_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG17_REQ = 0x1630 # macro +mmGCVM_INVALIDATE_ENG17_REQ_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG0_ACK = 0x1631 # macro +mmGCVM_INVALIDATE_ENG0_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG1_ACK = 0x1632 # macro +mmGCVM_INVALIDATE_ENG1_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG2_ACK = 0x1633 # macro +mmGCVM_INVALIDATE_ENG2_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG3_ACK = 0x1634 # macro +mmGCVM_INVALIDATE_ENG3_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG4_ACK = 0x1635 # macro +mmGCVM_INVALIDATE_ENG4_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG5_ACK = 0x1636 # macro +mmGCVM_INVALIDATE_ENG5_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG6_ACK = 0x1637 # macro +mmGCVM_INVALIDATE_ENG6_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG7_ACK = 0x1638 # macro +mmGCVM_INVALIDATE_ENG7_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG8_ACK = 0x1639 # macro +mmGCVM_INVALIDATE_ENG8_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG9_ACK = 0x163a # macro +mmGCVM_INVALIDATE_ENG9_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG10_ACK = 0x163b # macro +mmGCVM_INVALIDATE_ENG10_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG11_ACK = 0x163c # macro +mmGCVM_INVALIDATE_ENG11_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG12_ACK = 0x163d # macro +mmGCVM_INVALIDATE_ENG12_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG13_ACK = 0x163e # macro +mmGCVM_INVALIDATE_ENG13_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG14_ACK = 0x163f # macro +mmGCVM_INVALIDATE_ENG14_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG15_ACK = 0x1640 # macro +mmGCVM_INVALIDATE_ENG15_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG16_ACK = 0x1641 # macro +mmGCVM_INVALIDATE_ENG16_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG17_ACK = 0x1642 # macro +mmGCVM_INVALIDATE_ENG17_ACK_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 = 0x1643 # macro +mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 = 0x1644 # macro +mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 = 0x1645 # macro +mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 = 0x1646 # macro +mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 = 0x1647 # macro +mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 = 0x1648 # macro +mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 = 0x1649 # macro +mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 = 0x164a # macro +mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 = 0x164b # macro +mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 = 0x164c # macro +mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 = 0x164d # macro +mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 = 0x164e # macro +mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 = 0x164f # macro +mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 = 0x1650 # macro +mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 = 0x1651 # macro +mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 = 0x1652 # macro +mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 = 0x1653 # macro +mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 = 0x1654 # macro +mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 = 0x1655 # macro +mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 = 0x1656 # macro +mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 = 0x1657 # macro +mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 = 0x1658 # macro +mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 = 0x1659 # macro +mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 = 0x165a # macro +mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 = 0x165b # macro +mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 = 0x165c # macro +mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 = 0x165d # macro +mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 = 0x165e # macro +mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 = 0x165f # macro +mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 = 0x1660 # macro +mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 = 0x1661 # macro +mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 = 0x1662 # macro +mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 = 0x1663 # macro +mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 = 0x1664 # macro +mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 = 0x1665 # macro +mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX = 0 # macro +mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 = 0x1666 # macro +mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 = 0x1667 # macro +mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 = 0x1668 # macro +mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 = 0x1669 # macro +mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 = 0x166a # macro +mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 = 0x166b # macro +mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 = 0x166c # macro +mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 = 0x166d # macro +mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 = 0x166e # macro +mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 = 0x166f # macro +mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 = 0x1670 # macro +mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 = 0x1671 # macro +mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 = 0x1672 # macro +mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 = 0x1673 # macro +mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 = 0x1674 # macro +mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 = 0x1675 # macro +mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 = 0x1676 # macro +mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 = 0x1677 # macro +mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 = 0x1678 # macro +mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 = 0x1679 # macro +mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 = 0x167a # macro +mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 = 0x167b # macro +mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 = 0x167c # macro +mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 = 0x167d # macro +mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 = 0x167e # macro +mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 = 0x167f # macro +mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 = 0x1680 # macro +mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 = 0x1681 # macro +mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 = 0x1682 # macro +mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 = 0x1683 # macro +mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 = 0x1684 # macro +mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 = 0x1685 # macro +mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 = 0x1686 # macro +mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 = 0x1687 # macro +mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 = 0x1688 # macro +mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 = 0x1689 # macro +mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 = 0x168a # macro +mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 = 0x168b # macro +mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 = 0x168c # macro +mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 = 0x168d # macro +mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 = 0x168e # macro +mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 = 0x168f # macro +mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 = 0x1690 # macro +mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 = 0x1691 # macro +mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 = 0x1692 # macro +mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 = 0x1693 # macro +mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 = 0x1694 # macro +mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 = 0x1695 # macro +mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 = 0x1696 # macro +mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 = 0x1697 # macro +mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 = 0x1698 # macro +mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 = 0x1699 # macro +mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 = 0x169a # macro +mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 = 0x169b # macro +mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 = 0x169c # macro +mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 = 0x169d # macro +mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 = 0x169e # macro +mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 = 0x169f # macro +mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 = 0x16a0 # macro +mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 = 0x16a1 # macro +mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 = 0x16a2 # macro +mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 = 0x16a3 # macro +mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 = 0x16a4 # macro +mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 = 0x16a5 # macro +mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 = 0x16a6 # macro +mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 = 0x16a7 # macro +mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 = 0x16a8 # macro +mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 = 0x16a9 # macro +mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 = 0x16aa # macro +mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 = 0x16ab # macro +mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 = 0x16ac # macro +mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 = 0x16ad # macro +mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 = 0x16ae # macro +mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 = 0x16af # macro +mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 = 0x16b0 # macro +mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 = 0x16b1 # macro +mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 = 0x16b2 # macro +mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 = 0x16b3 # macro +mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 = 0x16b4 # macro +mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 = 0x16b5 # macro +mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 = 0x16b6 # macro +mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 = 0x16b7 # macro +mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 = 0x16b8 # macro +mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 = 0x16b9 # macro +mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 = 0x16ba # macro +mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 = 0x16bb # macro +mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 = 0x16bc # macro +mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 = 0x16bd # macro +mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 = 0x16be # macro +mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 = 0x16bf # macro +mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 = 0x16c0 # macro +mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 = 0x16c1 # macro +mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 = 0x16c2 # macro +mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 = 0x16c3 # macro +mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 = 0x16c4 # macro +mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 = 0x16c5 # macro +mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX = 0 # macro +mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 = 0x16c6 # macro +mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX = 0 # macro +mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16c7 # macro +mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16c8 # macro +mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16c9 # macro +mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16ca # macro +mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16cb # macro +mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16cc # macro +mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16cd # macro +mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16ce # macro +mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16cf # macro +mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d0 # macro +mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d1 # macro +mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d2 # macro +mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d3 # macro +mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d4 # macro +mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d5 # macro +mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d6 # macro +mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES = 0x16d7 # macro +mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX = 0 # macro +mmGCMC_VM_NB_MMIOBASE = 0x16e0 # macro +mmGCMC_VM_NB_MMIOBASE_BASE_IDX = 0 # macro +mmGCMC_VM_NB_MMIOLIMIT = 0x16e1 # macro +mmGCMC_VM_NB_MMIOLIMIT_BASE_IDX = 0 # macro +mmGCMC_VM_NB_PCI_CTRL = 0x16e2 # macro +mmGCMC_VM_NB_PCI_CTRL_BASE_IDX = 0 # macro +mmGCMC_VM_NB_PCI_ARB = 0x16e3 # macro +mmGCMC_VM_NB_PCI_ARB_BASE_IDX = 0 # macro +mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1 = 0x16e4 # macro +mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX = 0 # macro +mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2 = 0x16e5 # macro +mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX = 0 # macro +mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2 = 0x16e6 # macro +mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX = 0 # macro +mmGCMC_VM_FB_OFFSET = 0x16e7 # macro +mmGCMC_VM_FB_OFFSET_BASE_IDX = 0 # macro +mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x16e8 # macro +mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX = 0 # macro +mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x16e9 # macro +mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX = 0 # macro +mmGCMC_VM_STEERING = 0x16ea # macro +mmGCMC_VM_STEERING_BASE_IDX = 0 # macro +mmGCMC_SHARED_VIRT_RESET_REQ = 0x16eb # macro +mmGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX = 0 # macro +mmGCMC_MEM_POWER_LS = 0x16ec # macro +mmGCMC_MEM_POWER_LS_BASE_IDX = 0 # macro +mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START = 0x16ed # macro +mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX = 0 # macro +mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END = 0x16ee # macro +mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX = 0 # macro +mmGCMC_VM_APT_CNTL = 0x16ef # macro +mmGCMC_VM_APT_CNTL_BASE_IDX = 0 # macro +mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL = 0x16f0 # macro +mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX = 0 # macro +mmGCMC_VM_LOCAL_HBM_ADDRESS_START = 0x16f1 # macro +mmGCMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX = 0 # macro +mmGCMC_VM_LOCAL_HBM_ADDRESS_END = 0x16f2 # macro +mmGCMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX = 0 # macro +mmGCMC_SHARED_ACTIVE_FCN_ID = 0x16f4 # macro +mmGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX = 0 # macro +mmGCMC_SHARED_VIRT_RESET_REQ2 = 0x16f5 # macro +mmGCMC_SHARED_VIRT_RESET_REQ2_BASE_IDX = 0 # macro +mmGCMC_VM_XGMI_LFB_CNTL = 0x16f7 # macro +mmGCMC_VM_XGMI_LFB_CNTL_BASE_IDX = 0 # macro +mmGCMC_VM_XGMI_LFB_SIZE = 0x16f8 # macro +mmGCMC_VM_XGMI_LFB_SIZE_BASE_IDX = 0 # macro +mmGCMC_VM_FB_NOALLOC_CNTL = 0x16f9 # macro +mmGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX = 0 # macro +mmGCUTCL2_HARVEST_BYPASS_GROUPS = 0x16fa # macro +mmGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX = 0 # macro +mmGCMC_VM_FB_LOCATION_BASE = 0x16fc # macro +mmGCMC_VM_FB_LOCATION_BASE_BASE_IDX = 0 # macro +mmGCMC_VM_FB_LOCATION_TOP = 0x16fd # macro +mmGCMC_VM_FB_LOCATION_TOP_BASE_IDX = 0 # macro +mmGCMC_VM_AGP_TOP = 0x16fe # macro +mmGCMC_VM_AGP_TOP_BASE_IDX = 0 # macro +mmGCMC_VM_AGP_BOT = 0x16ff # macro +mmGCMC_VM_AGP_BOT_BASE_IDX = 0 # macro +mmGCMC_VM_AGP_BASE = 0x1700 # macro +mmGCMC_VM_AGP_BASE_BASE_IDX = 0 # macro +mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x1701 # macro +mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX = 0 # macro +mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x1702 # macro +mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX = 0 # macro +mmGCMC_VM_MX_L1_TLB_CNTL = 0x1703 # macro +mmGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX = 0 # macro +mmGCEA_DRAM_RD_CLI2GRP_MAP0 = 0x17a0 # macro +mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro +mmGCEA_DRAM_RD_CLI2GRP_MAP1 = 0x17a1 # macro +mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro +mmGCEA_DRAM_WR_CLI2GRP_MAP0 = 0x17a2 # macro +mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro +mmGCEA_DRAM_WR_CLI2GRP_MAP1 = 0x17a3 # macro +mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro +mmGCEA_DRAM_RD_GRP2VC_MAP = 0x17a4 # macro +mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX = 0 # macro +mmGCEA_DRAM_WR_GRP2VC_MAP = 0x17a5 # macro +mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX = 0 # macro +mmGCEA_DRAM_RD_LAZY = 0x17a6 # macro +mmGCEA_DRAM_RD_LAZY_BASE_IDX = 0 # macro +mmGCEA_DRAM_WR_LAZY = 0x17a7 # macro +mmGCEA_DRAM_WR_LAZY_BASE_IDX = 0 # macro +mmGCEA_DRAM_RD_CAM_CNTL = 0x17a8 # macro +mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX = 0 # macro +mmGCEA_DRAM_WR_CAM_CNTL = 0x17a9 # macro +mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX = 0 # macro +mmGCEA_DRAM_PAGE_BURST = 0x17aa # macro +mmGCEA_DRAM_PAGE_BURST_BASE_IDX = 0 # macro +mmGCEA_DRAM_RD_PRI_AGE = 0x17ab # macro +mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX = 0 # macro +mmGCEA_DRAM_WR_PRI_AGE = 0x17ac # macro +mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX = 0 # macro +mmGCEA_DRAM_RD_PRI_QUEUING = 0x17ad # macro +mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX = 0 # macro +mmGCEA_DRAM_WR_PRI_QUEUING = 0x17ae # macro +mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX = 0 # macro +mmGCEA_DRAM_RD_PRI_FIXED = 0x17af # macro +mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX = 0 # macro +mmGCEA_DRAM_WR_PRI_FIXED = 0x17b0 # macro +mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX = 0 # macro +mmGCEA_DRAM_RD_PRI_URGENCY = 0x17b1 # macro +mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX = 0 # macro +mmGCEA_DRAM_WR_PRI_URGENCY = 0x17b2 # macro +mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX = 0 # macro +mmGCEA_DRAM_RD_PRI_QUANT_PRI1 = 0x17b3 # macro +mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro +mmGCEA_DRAM_RD_PRI_QUANT_PRI2 = 0x17b4 # macro +mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro +mmGCEA_DRAM_RD_PRI_QUANT_PRI3 = 0x17b5 # macro +mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro +mmGCEA_DRAM_WR_PRI_QUANT_PRI1 = 0x17b6 # macro +mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro +mmGCEA_DRAM_WR_PRI_QUANT_PRI2 = 0x17b7 # macro +mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro +mmGCEA_DRAM_WR_PRI_QUANT_PRI3 = 0x17b8 # macro +mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro +mmGCEA_IO_RD_CLI2GRP_MAP0 = 0x187d # macro +mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX = 0 # macro +mmGCEA_IO_RD_CLI2GRP_MAP1 = 0x187e # macro +mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX = 0 # macro +mmGCEA_IO_WR_CLI2GRP_MAP0 = 0x187f # macro +mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX = 0 # macro +mmGCEA_IO_WR_CLI2GRP_MAP1 = 0x1880 # macro +mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX = 0 # macro +mmGCEA_IO_RD_COMBINE_FLUSH = 0x1881 # macro +mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX = 0 # macro +mmGCEA_IO_WR_COMBINE_FLUSH = 0x1882 # macro +mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX = 0 # macro +mmGCEA_IO_GROUP_BURST = 0x1883 # macro +mmGCEA_IO_GROUP_BURST_BASE_IDX = 0 # macro +mmGCEA_IO_RD_PRI_AGE = 0x1884 # macro +mmGCEA_IO_RD_PRI_AGE_BASE_IDX = 0 # macro +mmGCEA_IO_WR_PRI_AGE = 0x1885 # macro +mmGCEA_IO_WR_PRI_AGE_BASE_IDX = 0 # macro +mmGCEA_IO_RD_PRI_QUEUING = 0x1886 # macro +mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX = 0 # macro +mmGCEA_IO_WR_PRI_QUEUING = 0x1887 # macro +mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX = 0 # macro +mmGCEA_IO_RD_PRI_FIXED = 0x1888 # macro +mmGCEA_IO_RD_PRI_FIXED_BASE_IDX = 0 # macro +mmGCEA_IO_WR_PRI_FIXED = 0x1889 # macro +mmGCEA_IO_WR_PRI_FIXED_BASE_IDX = 0 # macro +mmGCEA_IO_RD_PRI_URGENCY = 0x188a # macro +mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX = 0 # macro +mmGCEA_IO_WR_PRI_URGENCY = 0x188b # macro +mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX = 0 # macro +mmGCEA_IO_RD_PRI_URGENCY_MASKING = 0x188c # macro +mmGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro +mmGCEA_IO_WR_PRI_URGENCY_MASKING = 0x188d # macro +mmGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX = 0 # macro +mmGCEA_IO_RD_PRI_QUANT_PRI1 = 0x188e # macro +mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 0 # macro +mmGCEA_IO_RD_PRI_QUANT_PRI2 = 0x188f # macro +mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 0 # macro +mmGCEA_IO_RD_PRI_QUANT_PRI3 = 0x1890 # macro +mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 0 # macro +mmGCEA_IO_WR_PRI_QUANT_PRI1 = 0x1891 # macro +mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 0 # macro +mmGCEA_IO_WR_PRI_QUANT_PRI2 = 0x1892 # macro +mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 0 # macro +mmGCEA_IO_WR_PRI_QUANT_PRI3 = 0x1893 # macro +mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 0 # macro +mmTCP_INVALIDATE = 0x18a0 # macro +mmTCP_INVALIDATE_BASE_IDX = 0 # macro +mmTCP_STATUS = 0x18a1 # macro +mmTCP_STATUS_BASE_IDX = 0 # macro +mmTCP_EDC_CNT = 0x18b7 # macro +mmTCP_EDC_CNT_BASE_IDX = 0 # macro +mmTCI_STATUS = 0x1901 # macro +mmTCI_STATUS_BASE_IDX = 0 # macro +mmTCI_CNTL_1 = 0x1902 # macro +mmTCI_CNTL_1_BASE_IDX = 0 # macro +mmTCI_CNTL_2 = 0x1903 # macro +mmTCI_CNTL_2_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC4_PS = 0x19a1 # macro +mmSPI_SHADER_PGM_RSRC4_PS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_CHKSUM_PS = 0x19a6 # macro +mmSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC3_PS = 0x19a7 # macro +mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_LO_PS = 0x19a8 # macro +mmSPI_SHADER_PGM_LO_PS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_HI_PS = 0x19a9 # macro +mmSPI_SHADER_PGM_HI_PS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC1_PS = 0x19aa # macro +mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC2_PS = 0x19ab # macro +mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_0 = 0x19ac # macro +mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_1 = 0x19ad # macro +mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_2 = 0x19ae # macro +mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_3 = 0x19af # macro +mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_4 = 0x19b0 # macro +mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_5 = 0x19b1 # macro +mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_6 = 0x19b2 # macro +mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_7 = 0x19b3 # macro +mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_8 = 0x19b4 # macro +mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_9 = 0x19b5 # macro +mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_10 = 0x19b6 # macro +mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_11 = 0x19b7 # macro +mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_12 = 0x19b8 # macro +mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_13 = 0x19b9 # macro +mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_14 = 0x19ba # macro +mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_15 = 0x19bb # macro +mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_16 = 0x19bc # macro +mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_17 = 0x19bd # macro +mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_18 = 0x19be # macro +mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_19 = 0x19bf # macro +mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_20 = 0x19c0 # macro +mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_21 = 0x19c1 # macro +mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_22 = 0x19c2 # macro +mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_23 = 0x19c3 # macro +mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_24 = 0x19c4 # macro +mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_25 = 0x19c5 # macro +mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_26 = 0x19c6 # macro +mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_27 = 0x19c7 # macro +mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_28 = 0x19c8 # macro +mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_29 = 0x19c9 # macro +mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_30 = 0x19ca # macro +mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_PS_31 = 0x19cb # macro +mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX = 0 # macro +mmSPI_SHADER_REQ_CTRL_PS = 0x19d0 # macro +mmSPI_SHADER_REQ_CTRL_PS_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_PS_0 = 0x19d2 # macro +mmSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_PS_1 = 0x19d3 # macro +mmSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_PS_2 = 0x19d4 # macro +mmSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_PS_3 = 0x19d5 # macro +mmSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC4_VS = 0x19e1 # macro +mmSPI_SHADER_PGM_RSRC4_VS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_CHKSUM_VS = 0x19e5 # macro +mmSPI_SHADER_PGM_CHKSUM_VS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC3_VS = 0x19e6 # macro +mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX = 0 # macro +mmSPI_SHADER_LATE_ALLOC_VS = 0x19e7 # macro +mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_LO_VS = 0x19e8 # macro +mmSPI_SHADER_PGM_LO_VS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_HI_VS = 0x19e9 # macro +mmSPI_SHADER_PGM_HI_VS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC1_VS = 0x19ea # macro +mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC2_VS = 0x19eb # macro +mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_0 = 0x19ec # macro +mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_1 = 0x19ed # macro +mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_2 = 0x19ee # macro +mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_3 = 0x19ef # macro +mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_4 = 0x19f0 # macro +mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_5 = 0x19f1 # macro +mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_6 = 0x19f2 # macro +mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_7 = 0x19f3 # macro +mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_8 = 0x19f4 # macro +mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_9 = 0x19f5 # macro +mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_10 = 0x19f6 # macro +mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_11 = 0x19f7 # macro +mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_12 = 0x19f8 # macro +mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_13 = 0x19f9 # macro +mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_14 = 0x19fa # macro +mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_15 = 0x19fb # macro +mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_16 = 0x19fc # macro +mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_17 = 0x19fd # macro +mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_18 = 0x19fe # macro +mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_19 = 0x19ff # macro +mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_20 = 0x1a00 # macro +mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_21 = 0x1a01 # macro +mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_22 = 0x1a02 # macro +mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_23 = 0x1a03 # macro +mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_24 = 0x1a04 # macro +mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_25 = 0x1a05 # macro +mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_26 = 0x1a06 # macro +mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_27 = 0x1a07 # macro +mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_28 = 0x1a08 # macro +mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_29 = 0x1a09 # macro +mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_30 = 0x1a0a # macro +mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_VS_31 = 0x1a0b # macro +mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX = 0 # macro +mmSPI_SHADER_REQ_CTRL_VS = 0x1a10 # macro +mmSPI_SHADER_REQ_CTRL_VS_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_VS_0 = 0x1a12 # macro +mmSPI_SHADER_USER_ACCUM_VS_0_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_VS_1 = 0x1a13 # macro +mmSPI_SHADER_USER_ACCUM_VS_1_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_VS_2 = 0x1a14 # macro +mmSPI_SHADER_USER_ACCUM_VS_2_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_VS_3 = 0x1a15 # macro +mmSPI_SHADER_USER_ACCUM_VS_3_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC2_GS_VS = 0x1a1b # macro +mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_CHKSUM_GS = 0x1a20 # macro +mmSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC4_GS = 0x1a21 # macro +mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_ADDR_LO_GS = 0x1a22 # macro +mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_ADDR_HI_GS = 0x1a23 # macro +mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_LO_ES_GS = 0x1a24 # macro +mmSPI_SHADER_PGM_LO_ES_GS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_HI_ES_GS = 0x1a25 # macro +mmSPI_SHADER_PGM_HI_ES_GS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC3_GS = 0x1a27 # macro +mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_LO_GS = 0x1a28 # macro +mmSPI_SHADER_PGM_LO_GS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_HI_GS = 0x1a29 # macro +mmSPI_SHADER_PGM_HI_GS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC1_GS = 0x1a2a # macro +mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC2_GS = 0x1a2b # macro +mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_0 = 0x1a2c # macro +mmSPI_SHADER_USER_DATA_GS_0_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_1 = 0x1a2d # macro +mmSPI_SHADER_USER_DATA_GS_1_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_2 = 0x1a2e # macro +mmSPI_SHADER_USER_DATA_GS_2_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_3 = 0x1a2f # macro +mmSPI_SHADER_USER_DATA_GS_3_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_4 = 0x1a30 # macro +mmSPI_SHADER_USER_DATA_GS_4_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_5 = 0x1a31 # macro +mmSPI_SHADER_USER_DATA_GS_5_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_6 = 0x1a32 # macro +mmSPI_SHADER_USER_DATA_GS_6_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_7 = 0x1a33 # macro +mmSPI_SHADER_USER_DATA_GS_7_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_8 = 0x1a34 # macro +mmSPI_SHADER_USER_DATA_GS_8_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_9 = 0x1a35 # macro +mmSPI_SHADER_USER_DATA_GS_9_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_10 = 0x1a36 # macro +mmSPI_SHADER_USER_DATA_GS_10_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_11 = 0x1a37 # macro +mmSPI_SHADER_USER_DATA_GS_11_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_12 = 0x1a38 # macro +mmSPI_SHADER_USER_DATA_GS_12_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_13 = 0x1a39 # macro +mmSPI_SHADER_USER_DATA_GS_13_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_14 = 0x1a3a # macro +mmSPI_SHADER_USER_DATA_GS_14_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_15 = 0x1a3b # macro +mmSPI_SHADER_USER_DATA_GS_15_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_16 = 0x1a3c # macro +mmSPI_SHADER_USER_DATA_GS_16_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_17 = 0x1a3d # macro +mmSPI_SHADER_USER_DATA_GS_17_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_18 = 0x1a3e # macro +mmSPI_SHADER_USER_DATA_GS_18_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_19 = 0x1a3f # macro +mmSPI_SHADER_USER_DATA_GS_19_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_20 = 0x1a40 # macro +mmSPI_SHADER_USER_DATA_GS_20_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_21 = 0x1a41 # macro +mmSPI_SHADER_USER_DATA_GS_21_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_22 = 0x1a42 # macro +mmSPI_SHADER_USER_DATA_GS_22_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_23 = 0x1a43 # macro +mmSPI_SHADER_USER_DATA_GS_23_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_24 = 0x1a44 # macro +mmSPI_SHADER_USER_DATA_GS_24_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_25 = 0x1a45 # macro +mmSPI_SHADER_USER_DATA_GS_25_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_26 = 0x1a46 # macro +mmSPI_SHADER_USER_DATA_GS_26_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_27 = 0x1a47 # macro +mmSPI_SHADER_USER_DATA_GS_27_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_28 = 0x1a48 # macro +mmSPI_SHADER_USER_DATA_GS_28_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_29 = 0x1a49 # macro +mmSPI_SHADER_USER_DATA_GS_29_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_30 = 0x1a4a # macro +mmSPI_SHADER_USER_DATA_GS_30_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_GS_31 = 0x1a4b # macro +mmSPI_SHADER_USER_DATA_GS_31_BASE_IDX = 0 # macro +mmSPI_SHADER_REQ_CTRL_ESGS = 0x1a50 # macro +mmSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_ESGS_0 = 0x1a52 # macro +mmSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_ESGS_1 = 0x1a53 # macro +mmSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_ESGS_2 = 0x1a54 # macro +mmSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_ESGS_3 = 0x1a55 # macro +mmSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_LO_ES = 0x1a68 # macro +mmSPI_SHADER_PGM_LO_ES_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_HI_ES = 0x1a69 # macro +mmSPI_SHADER_PGM_HI_ES_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_CHKSUM_HS = 0x1aa0 # macro +mmSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC4_HS = 0x1aa1 # macro +mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_ADDR_LO_HS = 0x1aa2 # macro +mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_ADDR_HI_HS = 0x1aa3 # macro +mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_LO_LS_HS = 0x1aa4 # macro +mmSPI_SHADER_PGM_LO_LS_HS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_HI_LS_HS = 0x1aa5 # macro +mmSPI_SHADER_PGM_HI_LS_HS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC3_HS = 0x1aa7 # macro +mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_LO_HS = 0x1aa8 # macro +mmSPI_SHADER_PGM_LO_HS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_HI_HS = 0x1aa9 # macro +mmSPI_SHADER_PGM_HI_HS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC1_HS = 0x1aaa # macro +mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_RSRC2_HS = 0x1aab # macro +mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_0 = 0x1aac # macro +mmSPI_SHADER_USER_DATA_HS_0_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_1 = 0x1aad # macro +mmSPI_SHADER_USER_DATA_HS_1_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_2 = 0x1aae # macro +mmSPI_SHADER_USER_DATA_HS_2_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_3 = 0x1aaf # macro +mmSPI_SHADER_USER_DATA_HS_3_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_4 = 0x1ab0 # macro +mmSPI_SHADER_USER_DATA_HS_4_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_5 = 0x1ab1 # macro +mmSPI_SHADER_USER_DATA_HS_5_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_6 = 0x1ab2 # macro +mmSPI_SHADER_USER_DATA_HS_6_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_7 = 0x1ab3 # macro +mmSPI_SHADER_USER_DATA_HS_7_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_8 = 0x1ab4 # macro +mmSPI_SHADER_USER_DATA_HS_8_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_9 = 0x1ab5 # macro +mmSPI_SHADER_USER_DATA_HS_9_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_10 = 0x1ab6 # macro +mmSPI_SHADER_USER_DATA_HS_10_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_11 = 0x1ab7 # macro +mmSPI_SHADER_USER_DATA_HS_11_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_12 = 0x1ab8 # macro +mmSPI_SHADER_USER_DATA_HS_12_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_13 = 0x1ab9 # macro +mmSPI_SHADER_USER_DATA_HS_13_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_14 = 0x1aba # macro +mmSPI_SHADER_USER_DATA_HS_14_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_15 = 0x1abb # macro +mmSPI_SHADER_USER_DATA_HS_15_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_16 = 0x1abc # macro +mmSPI_SHADER_USER_DATA_HS_16_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_17 = 0x1abd # macro +mmSPI_SHADER_USER_DATA_HS_17_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_18 = 0x1abe # macro +mmSPI_SHADER_USER_DATA_HS_18_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_19 = 0x1abf # macro +mmSPI_SHADER_USER_DATA_HS_19_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_20 = 0x1ac0 # macro +mmSPI_SHADER_USER_DATA_HS_20_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_21 = 0x1ac1 # macro +mmSPI_SHADER_USER_DATA_HS_21_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_22 = 0x1ac2 # macro +mmSPI_SHADER_USER_DATA_HS_22_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_23 = 0x1ac3 # macro +mmSPI_SHADER_USER_DATA_HS_23_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_24 = 0x1ac4 # macro +mmSPI_SHADER_USER_DATA_HS_24_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_25 = 0x1ac5 # macro +mmSPI_SHADER_USER_DATA_HS_25_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_26 = 0x1ac6 # macro +mmSPI_SHADER_USER_DATA_HS_26_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_27 = 0x1ac7 # macro +mmSPI_SHADER_USER_DATA_HS_27_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_28 = 0x1ac8 # macro +mmSPI_SHADER_USER_DATA_HS_28_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_29 = 0x1ac9 # macro +mmSPI_SHADER_USER_DATA_HS_29_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_30 = 0x1aca # macro +mmSPI_SHADER_USER_DATA_HS_30_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_DATA_HS_31 = 0x1acb # macro +mmSPI_SHADER_USER_DATA_HS_31_BASE_IDX = 0 # macro +mmSPI_SHADER_REQ_CTRL_LSHS = 0x1ad0 # macro +mmSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_LSHS_0 = 0x1ad2 # macro +mmSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_LSHS_1 = 0x1ad3 # macro +mmSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_LSHS_2 = 0x1ad4 # macro +mmSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX = 0 # macro +mmSPI_SHADER_USER_ACCUM_LSHS_3 = 0x1ad5 # macro +mmSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_LO_LS = 0x1ae8 # macro +mmSPI_SHADER_PGM_LO_LS_BASE_IDX = 0 # macro +mmSPI_SHADER_PGM_HI_LS = 0x1ae9 # macro +mmSPI_SHADER_PGM_HI_LS_BASE_IDX = 0 # macro +mmCOMPUTE_DISPATCH_INITIATOR = 0x1ba0 # macro +mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX = 0 # macro +mmCOMPUTE_DIM_X = 0x1ba1 # macro +mmCOMPUTE_DIM_X_BASE_IDX = 0 # macro +mmCOMPUTE_DIM_Y = 0x1ba2 # macro +mmCOMPUTE_DIM_Y_BASE_IDX = 0 # macro +mmCOMPUTE_DIM_Z = 0x1ba3 # macro +mmCOMPUTE_DIM_Z_BASE_IDX = 0 # macro +mmCOMPUTE_START_X = 0x1ba4 # macro +mmCOMPUTE_START_X_BASE_IDX = 0 # macro +mmCOMPUTE_START_Y = 0x1ba5 # macro +mmCOMPUTE_START_Y_BASE_IDX = 0 # macro +mmCOMPUTE_START_Z = 0x1ba6 # macro +mmCOMPUTE_START_Z_BASE_IDX = 0 # macro +mmCOMPUTE_NUM_THREAD_X = 0x1ba7 # macro +mmCOMPUTE_NUM_THREAD_X_BASE_IDX = 0 # macro +mmCOMPUTE_NUM_THREAD_Y = 0x1ba8 # macro +mmCOMPUTE_NUM_THREAD_Y_BASE_IDX = 0 # macro +mmCOMPUTE_NUM_THREAD_Z = 0x1ba9 # macro +mmCOMPUTE_NUM_THREAD_Z_BASE_IDX = 0 # macro +mmCOMPUTE_PIPELINESTAT_ENABLE = 0x1baa # macro +mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX = 0 # macro +mmCOMPUTE_PERFCOUNT_ENABLE = 0x1bab # macro +mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX = 0 # macro +mmCOMPUTE_PGM_LO = 0x1bac # macro +mmCOMPUTE_PGM_LO_BASE_IDX = 0 # macro +mmCOMPUTE_PGM_HI = 0x1bad # macro +mmCOMPUTE_PGM_HI_BASE_IDX = 0 # macro +mmCOMPUTE_DISPATCH_PKT_ADDR_LO = 0x1bae # macro +mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX = 0 # macro +mmCOMPUTE_DISPATCH_PKT_ADDR_HI = 0x1baf # macro +mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX = 0 # macro +mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO = 0x1bb0 # macro +mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX = 0 # macro +mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI = 0x1bb1 # macro +mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX = 0 # macro +mmCOMPUTE_PGM_RSRC1 = 0x1bb2 # macro +mmCOMPUTE_PGM_RSRC1_BASE_IDX = 0 # macro +mmCOMPUTE_PGM_RSRC2 = 0x1bb3 # macro +mmCOMPUTE_PGM_RSRC2_BASE_IDX = 0 # macro +mmCOMPUTE_VMID = 0x1bb4 # macro +mmCOMPUTE_VMID_BASE_IDX = 0 # macro +mmCOMPUTE_RESOURCE_LIMITS = 0x1bb5 # macro +mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX = 0 # macro +mmCOMPUTE_DESTINATION_EN_SE0 = 0x1bb6 # macro +mmCOMPUTE_DESTINATION_EN_SE0_BASE_IDX = 0 # macro +mmCOMPUTE_STATIC_THREAD_MGMT_SE0 = 0x1bb6 # macro +mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX = 0 # macro +mmCOMPUTE_DESTINATION_EN_SE1 = 0x1bb7 # macro +mmCOMPUTE_DESTINATION_EN_SE1_BASE_IDX = 0 # macro +mmCOMPUTE_STATIC_THREAD_MGMT_SE1 = 0x1bb7 # macro +mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX = 0 # macro +mmCOMPUTE_TMPRING_SIZE = 0x1bb8 # macro +mmCOMPUTE_TMPRING_SIZE_BASE_IDX = 0 # macro +mmCOMPUTE_DESTINATION_EN_SE2 = 0x1bb9 # macro +mmCOMPUTE_DESTINATION_EN_SE2_BASE_IDX = 0 # macro +mmCOMPUTE_STATIC_THREAD_MGMT_SE2 = 0x1bb9 # macro +mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX = 0 # macro +mmCOMPUTE_DESTINATION_EN_SE3 = 0x1bba # macro +mmCOMPUTE_DESTINATION_EN_SE3_BASE_IDX = 0 # macro +mmCOMPUTE_STATIC_THREAD_MGMT_SE3 = 0x1bba # macro +mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX = 0 # macro +mmCOMPUTE_RESTART_X = 0x1bbb # macro +mmCOMPUTE_RESTART_X_BASE_IDX = 0 # macro +mmCOMPUTE_RESTART_Y = 0x1bbc # macro +mmCOMPUTE_RESTART_Y_BASE_IDX = 0 # macro +mmCOMPUTE_RESTART_Z = 0x1bbd # macro +mmCOMPUTE_RESTART_Z_BASE_IDX = 0 # macro +mmCOMPUTE_THREAD_TRACE_ENABLE = 0x1bbe # macro +mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX = 0 # macro +mmCOMPUTE_MISC_RESERVED = 0x1bbf # macro +mmCOMPUTE_MISC_RESERVED_BASE_IDX = 0 # macro +mmCOMPUTE_DISPATCH_ID = 0x1bc0 # macro +mmCOMPUTE_DISPATCH_ID_BASE_IDX = 0 # macro +mmCOMPUTE_THREADGROUP_ID = 0x1bc1 # macro +mmCOMPUTE_THREADGROUP_ID_BASE_IDX = 0 # macro +mmCOMPUTE_REQ_CTRL = 0x1bc2 # macro +mmCOMPUTE_REQ_CTRL_BASE_IDX = 0 # macro +mmCOMPUTE_USER_ACCUM_0 = 0x1bc4 # macro +mmCOMPUTE_USER_ACCUM_0_BASE_IDX = 0 # macro +mmCOMPUTE_USER_ACCUM_1 = 0x1bc5 # macro +mmCOMPUTE_USER_ACCUM_1_BASE_IDX = 0 # macro +mmCOMPUTE_USER_ACCUM_2 = 0x1bc6 # macro +mmCOMPUTE_USER_ACCUM_2_BASE_IDX = 0 # macro +mmCOMPUTE_USER_ACCUM_3 = 0x1bc7 # macro +mmCOMPUTE_USER_ACCUM_3_BASE_IDX = 0 # macro +mmCOMPUTE_PGM_RSRC3 = 0x1bc8 # macro +mmCOMPUTE_PGM_RSRC3_BASE_IDX = 0 # macro +mmCOMPUTE_DDID_INDEX = 0x1bc9 # macro +mmCOMPUTE_DDID_INDEX_BASE_IDX = 0 # macro +mmCOMPUTE_SHADER_CHKSUM = 0x1bca # macro +mmCOMPUTE_SHADER_CHKSUM_BASE_IDX = 0 # macro +mmCOMPUTE_RELAUNCH = 0x1bcb # macro +mmCOMPUTE_RELAUNCH_BASE_IDX = 0 # macro +mmCOMPUTE_WAVE_RESTORE_ADDR_LO = 0x1bcc # macro +mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX = 0 # macro +mmCOMPUTE_WAVE_RESTORE_ADDR_HI = 0x1bcd # macro +mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX = 0 # macro +mmCOMPUTE_RELAUNCH2 = 0x1bce # macro +mmCOMPUTE_RELAUNCH2_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_0 = 0x1be0 # macro +mmCOMPUTE_USER_DATA_0_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_1 = 0x1be1 # macro +mmCOMPUTE_USER_DATA_1_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_2 = 0x1be2 # macro +mmCOMPUTE_USER_DATA_2_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_3 = 0x1be3 # macro +mmCOMPUTE_USER_DATA_3_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_4 = 0x1be4 # macro +mmCOMPUTE_USER_DATA_4_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_5 = 0x1be5 # macro +mmCOMPUTE_USER_DATA_5_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_6 = 0x1be6 # macro +mmCOMPUTE_USER_DATA_6_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_7 = 0x1be7 # macro +mmCOMPUTE_USER_DATA_7_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_8 = 0x1be8 # macro +mmCOMPUTE_USER_DATA_8_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_9 = 0x1be9 # macro +mmCOMPUTE_USER_DATA_9_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_10 = 0x1bea # macro +mmCOMPUTE_USER_DATA_10_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_11 = 0x1beb # macro +mmCOMPUTE_USER_DATA_11_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_12 = 0x1bec # macro +mmCOMPUTE_USER_DATA_12_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_13 = 0x1bed # macro +mmCOMPUTE_USER_DATA_13_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_14 = 0x1bee # macro +mmCOMPUTE_USER_DATA_14_BASE_IDX = 0 # macro +mmCOMPUTE_USER_DATA_15 = 0x1bef # macro +mmCOMPUTE_USER_DATA_15_BASE_IDX = 0 # macro +mmCOMPUTE_DISPATCH_TUNNEL = 0x1c1d # macro +mmCOMPUTE_DISPATCH_TUNNEL_BASE_IDX = 0 # macro +mmCOMPUTE_DISPATCH_END = 0x1c1e # macro +mmCOMPUTE_DISPATCH_END_BASE_IDX = 0 # macro +mmCOMPUTE_NOWHERE = 0x1c1f # macro +mmCOMPUTE_NOWHERE_BASE_IDX = 0 # macro +mmSH_RESERVED_REG0 = 0x1c20 # macro +mmSH_RESERVED_REG0_BASE_IDX = 0 # macro +mmSH_RESERVED_REG1 = 0x1c21 # macro +mmSH_RESERVED_REG1_BASE_IDX = 0 # macro +mmCP_EOPQ_WAIT_TIME = 0x1dd5 # macro +mmCP_EOPQ_WAIT_TIME_BASE_IDX = 0 # macro +mmCP_CPC_MGCG_SYNC_CNTL = 0x1dd6 # macro +mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX = 0 # macro +mmCPC_INT_INFO = 0x1dd7 # macro +mmCPC_INT_INFO_BASE_IDX = 0 # macro +mmCP_VIRT_STATUS = 0x1dd8 # macro +mmCP_VIRT_STATUS_BASE_IDX = 0 # macro +mmCPC_INT_ADDR = 0x1dd9 # macro +mmCPC_INT_ADDR_BASE_IDX = 0 # macro +mmCPC_INT_PASID = 0x1dda # macro +mmCPC_INT_PASID_BASE_IDX = 0 # macro +mmCP_GFX_ERROR = 0x1ddb # macro +mmCP_GFX_ERROR_BASE_IDX = 0 # macro +mmCPG_UTCL1_CNTL = 0x1ddc # macro +mmCPG_UTCL1_CNTL_BASE_IDX = 0 # macro +mmCPC_UTCL1_CNTL = 0x1ddd # macro +mmCPC_UTCL1_CNTL_BASE_IDX = 0 # macro +mmCPF_UTCL1_CNTL = 0x1dde # macro +mmCPF_UTCL1_CNTL_BASE_IDX = 0 # macro +mmCP_AQL_SMM_STATUS = 0x1ddf # macro +mmCP_AQL_SMM_STATUS_BASE_IDX = 0 # macro +mmCP_RB0_BASE = 0x1de0 # macro +mmCP_RB0_BASE_BASE_IDX = 0 # macro +mmCP_RB_BASE = 0x1de0 # macro +mmCP_RB_BASE_BASE_IDX = 0 # macro +mmCP_RB0_CNTL = 0x1de1 # macro +mmCP_RB0_CNTL_BASE_IDX = 0 # macro +mmCP_RB_CNTL = 0x1de1 # macro +mmCP_RB_CNTL_BASE_IDX = 0 # macro +mmCP_RB_RPTR_WR = 0x1de2 # macro +mmCP_RB_RPTR_WR_BASE_IDX = 0 # macro +mmCP_RB0_RPTR_ADDR = 0x1de3 # macro +mmCP_RB0_RPTR_ADDR_BASE_IDX = 0 # macro +mmCP_RB_RPTR_ADDR = 0x1de3 # macro +mmCP_RB_RPTR_ADDR_BASE_IDX = 0 # macro +mmCP_RB0_RPTR_ADDR_HI = 0x1de4 # macro +mmCP_RB0_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmCP_RB_RPTR_ADDR_HI = 0x1de4 # macro +mmCP_RB_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmCP_RB0_BUFSZ_MASK = 0x1de5 # macro +mmCP_RB0_BUFSZ_MASK_BASE_IDX = 0 # macro +mmCP_RB_BUFSZ_MASK = 0x1de5 # macro +mmCP_RB_BUFSZ_MASK_BASE_IDX = 0 # macro +mmCP_INT_CNTL = 0x1de9 # macro +mmCP_INT_CNTL_BASE_IDX = 0 # macro +mmCP_INT_STATUS = 0x1dea # macro +mmCP_INT_STATUS_BASE_IDX = 0 # macro +mmCP_DEVICE_ID = 0x1deb # macro +mmCP_DEVICE_ID_BASE_IDX = 0 # macro +mmCP_ME0_PIPE_PRIORITY_CNTS = 0x1dec # macro +mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro +mmCP_RING_PRIORITY_CNTS = 0x1dec # macro +mmCP_RING_PRIORITY_CNTS_BASE_IDX = 0 # macro +mmCP_ME0_PIPE0_PRIORITY = 0x1ded # macro +mmCP_ME0_PIPE0_PRIORITY_BASE_IDX = 0 # macro +mmCP_RING0_PRIORITY = 0x1ded # macro +mmCP_RING0_PRIORITY_BASE_IDX = 0 # macro +mmCP_ME0_PIPE1_PRIORITY = 0x1dee # macro +mmCP_ME0_PIPE1_PRIORITY_BASE_IDX = 0 # macro +mmCP_RING1_PRIORITY = 0x1dee # macro +mmCP_RING1_PRIORITY_BASE_IDX = 0 # macro +mmCP_ME0_PIPE2_PRIORITY = 0x1def # macro +mmCP_ME0_PIPE2_PRIORITY_BASE_IDX = 0 # macro +mmCP_RING2_PRIORITY = 0x1def # macro +mmCP_RING2_PRIORITY_BASE_IDX = 0 # macro +mmCP_FATAL_ERROR = 0x1df0 # macro +mmCP_FATAL_ERROR_BASE_IDX = 0 # macro +mmCP_RB_VMID = 0x1df1 # macro +mmCP_RB_VMID_BASE_IDX = 0 # macro +mmCP_ME0_PIPE0_VMID = 0x1df2 # macro +mmCP_ME0_PIPE0_VMID_BASE_IDX = 0 # macro +mmCP_ME0_PIPE1_VMID = 0x1df3 # macro +mmCP_ME0_PIPE1_VMID_BASE_IDX = 0 # macro +mmCP_RB0_WPTR = 0x1df4 # macro +mmCP_RB0_WPTR_BASE_IDX = 0 # macro +mmCP_RB_WPTR = 0x1df4 # macro +mmCP_RB_WPTR_BASE_IDX = 0 # macro +mmCP_RB0_WPTR_HI = 0x1df5 # macro +mmCP_RB0_WPTR_HI_BASE_IDX = 0 # macro +mmCP_RB_WPTR_HI = 0x1df5 # macro +mmCP_RB_WPTR_HI_BASE_IDX = 0 # macro +mmCP_RB1_WPTR = 0x1df6 # macro +mmCP_RB1_WPTR_BASE_IDX = 0 # macro +mmCP_RB1_WPTR_HI = 0x1df7 # macro +mmCP_RB1_WPTR_HI_BASE_IDX = 0 # macro +mmCP_RB2_WPTR = 0x1df8 # macro +mmCP_RB2_WPTR_BASE_IDX = 0 # macro +mmCP_PROCESS_QUANTUM = 0x1df9 # macro +mmCP_PROCESS_QUANTUM_BASE_IDX = 0 # macro +mmCP_RB_DOORBELL_RANGE_LOWER = 0x1dfa # macro +mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro +mmCP_RB_DOORBELL_RANGE_UPPER = 0x1dfb # macro +mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro +mmCP_MEC_DOORBELL_RANGE_LOWER = 0x1dfc # macro +mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX = 0 # macro +mmCP_MEC_DOORBELL_RANGE_UPPER = 0x1dfd # macro +mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX = 0 # macro +mmCPG_UTCL1_ERROR = 0x1dfe # macro +mmCPG_UTCL1_ERROR_BASE_IDX = 0 # macro +mmCPC_UTCL1_ERROR = 0x1dff # macro +mmCPC_UTCL1_ERROR_BASE_IDX = 0 # macro +mmCP_RB1_BASE = 0x1e00 # macro +mmCP_RB1_BASE_BASE_IDX = 0 # macro +mmCP_RB1_CNTL = 0x1e01 # macro +mmCP_RB1_CNTL_BASE_IDX = 0 # macro +mmCP_RB1_RPTR_ADDR = 0x1e02 # macro +mmCP_RB1_RPTR_ADDR_BASE_IDX = 0 # macro +mmCP_RB1_RPTR_ADDR_HI = 0x1e03 # macro +mmCP_RB1_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmCP_RB1_BUFSZ_MASK = 0x1e04 # macro +mmCP_RB1_BUFSZ_MASK_BASE_IDX = 0 # macro +mmCP_RB2_BASE = 0x1e05 # macro +mmCP_RB2_BASE_BASE_IDX = 0 # macro +mmCP_RB2_CNTL = 0x1e06 # macro +mmCP_RB2_CNTL_BASE_IDX = 0 # macro +mmCP_RB2_RPTR_ADDR = 0x1e07 # macro +mmCP_RB2_RPTR_ADDR_BASE_IDX = 0 # macro +mmCP_RB2_RPTR_ADDR_HI = 0x1e08 # macro +mmCP_RB2_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmCP_INT_CNTL_RING0 = 0x1e0a # macro +mmCP_INT_CNTL_RING0_BASE_IDX = 0 # macro +mmCP_INT_CNTL_RING1 = 0x1e0b # macro +mmCP_INT_CNTL_RING1_BASE_IDX = 0 # macro +mmCP_INT_CNTL_RING2 = 0x1e0c # macro +mmCP_INT_CNTL_RING2_BASE_IDX = 0 # macro +mmCP_INT_STATUS_RING0 = 0x1e0d # macro +mmCP_INT_STATUS_RING0_BASE_IDX = 0 # macro +mmCP_INT_STATUS_RING1 = 0x1e0e # macro +mmCP_INT_STATUS_RING1_BASE_IDX = 0 # macro +mmCP_INT_STATUS_RING2 = 0x1e0f # macro +mmCP_INT_STATUS_RING2_BASE_IDX = 0 # macro +mmCP_ME_F32_INTERRUPT = 0x1e13 # macro +mmCP_ME_F32_INTERRUPT_BASE_IDX = 0 # macro +mmCP_PFP_F32_INTERRUPT = 0x1e14 # macro +mmCP_PFP_F32_INTERRUPT_BASE_IDX = 0 # macro +mmCP_CE_F32_INTERRUPT = 0x1e15 # macro +mmCP_CE_F32_INTERRUPT_BASE_IDX = 0 # macro +mmCP_MEC1_F32_INTERRUPT = 0x1e16 # macro +mmCP_MEC1_F32_INTERRUPT_BASE_IDX = 0 # macro +mmCP_MEC2_F32_INTERRUPT = 0x1e17 # macro +mmCP_MEC2_F32_INTERRUPT_BASE_IDX = 0 # macro +mmCP_PWR_CNTL = 0x1e18 # macro +mmCP_PWR_CNTL_BASE_IDX = 0 # macro +mmCP_MEM_SLP_CNTL = 0x1e19 # macro +mmCP_MEM_SLP_CNTL_BASE_IDX = 0 # macro +mmCP_ECC_FIRSTOCCURRENCE = 0x1e1a # macro +mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX = 0 # macro +mmCP_ECC_FIRSTOCCURRENCE_RING0 = 0x1e1b # macro +mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX = 0 # macro +mmCP_ECC_FIRSTOCCURRENCE_RING1 = 0x1e1c # macro +mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX = 0 # macro +mmCP_ECC_FIRSTOCCURRENCE_RING2 = 0x1e1d # macro +mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX = 0 # macro +mmGB_EDC_MODE = 0x1e1e # macro +mmGB_EDC_MODE_BASE_IDX = 0 # macro +mmCP_PQ_WPTR_POLL_CNTL = 0x1e23 # macro +mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX = 0 # macro +mmCP_PQ_WPTR_POLL_CNTL1 = 0x1e24 # macro +mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX = 0 # macro +mmCP_ME1_PIPE0_INT_CNTL = 0x1e25 # macro +mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX = 0 # macro +mmCP_ME1_PIPE1_INT_CNTL = 0x1e26 # macro +mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX = 0 # macro +mmCP_ME1_PIPE2_INT_CNTL = 0x1e27 # macro +mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX = 0 # macro +mmCP_ME1_PIPE3_INT_CNTL = 0x1e28 # macro +mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX = 0 # macro +mmCP_ME2_PIPE0_INT_CNTL = 0x1e29 # macro +mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX = 0 # macro +mmCP_ME2_PIPE1_INT_CNTL = 0x1e2a # macro +mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX = 0 # macro +mmCP_ME2_PIPE2_INT_CNTL = 0x1e2b # macro +mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX = 0 # macro +mmCP_ME2_PIPE3_INT_CNTL = 0x1e2c # macro +mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX = 0 # macro +mmCP_ME1_PIPE0_INT_STATUS = 0x1e2d # macro +mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX = 0 # macro +mmCP_ME1_PIPE1_INT_STATUS = 0x1e2e # macro +mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX = 0 # macro +mmCP_ME1_PIPE2_INT_STATUS = 0x1e2f # macro +mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX = 0 # macro +mmCP_ME1_PIPE3_INT_STATUS = 0x1e30 # macro +mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX = 0 # macro +mmCP_ME2_PIPE0_INT_STATUS = 0x1e31 # macro +mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX = 0 # macro +mmCP_ME2_PIPE1_INT_STATUS = 0x1e32 # macro +mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX = 0 # macro +mmCP_ME2_PIPE2_INT_STATUS = 0x1e33 # macro +mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX = 0 # macro +mmCP_ME2_PIPE3_INT_STATUS = 0x1e34 # macro +mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX = 0 # macro +mmCP_GFX_QUEUE_INDEX = 0x1e37 # macro +mmCP_GFX_QUEUE_INDEX_BASE_IDX = 0 # macro +mmCC_GC_EDC_CONFIG = 0x1e38 # macro +mmCC_GC_EDC_CONFIG_BASE_IDX = 0 # macro +mmCP_ME1_INT_STAT_DEBUG = 0x1e35 # macro +mmCP_ME1_INT_STAT_DEBUG_BASE_IDX = 0 # macro +mmCP_ME2_INT_STAT_DEBUG = 0x1e36 # macro +mmCP_ME2_INT_STAT_DEBUG_BASE_IDX = 0 # macro +mmCP_ME1_PIPE_PRIORITY_CNTS = 0x1e39 # macro +mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro +mmCP_ME1_PIPE0_PRIORITY = 0x1e3a # macro +mmCP_ME1_PIPE0_PRIORITY_BASE_IDX = 0 # macro +mmCP_ME1_PIPE1_PRIORITY = 0x1e3b # macro +mmCP_ME1_PIPE1_PRIORITY_BASE_IDX = 0 # macro +mmCP_ME1_PIPE2_PRIORITY = 0x1e3c # macro +mmCP_ME1_PIPE2_PRIORITY_BASE_IDX = 0 # macro +mmCP_ME1_PIPE3_PRIORITY = 0x1e3d # macro +mmCP_ME1_PIPE3_PRIORITY_BASE_IDX = 0 # macro +mmCP_ME2_PIPE_PRIORITY_CNTS = 0x1e3e # macro +mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX = 0 # macro +mmCP_ME2_PIPE0_PRIORITY = 0x1e3f # macro +mmCP_ME2_PIPE0_PRIORITY_BASE_IDX = 0 # macro +mmCP_ME2_PIPE1_PRIORITY = 0x1e40 # macro +mmCP_ME2_PIPE1_PRIORITY_BASE_IDX = 0 # macro +mmCP_ME2_PIPE2_PRIORITY = 0x1e41 # macro +mmCP_ME2_PIPE2_PRIORITY_BASE_IDX = 0 # macro +mmCP_ME2_PIPE3_PRIORITY = 0x1e42 # macro +mmCP_ME2_PIPE3_PRIORITY_BASE_IDX = 0 # macro +mmCP_CE_PRGRM_CNTR_START = 0x1e43 # macro +mmCP_CE_PRGRM_CNTR_START_BASE_IDX = 0 # macro +mmCP_PFP_PRGRM_CNTR_START = 0x1e44 # macro +mmCP_PFP_PRGRM_CNTR_START_BASE_IDX = 0 # macro +mmCP_ME_PRGRM_CNTR_START = 0x1e45 # macro +mmCP_ME_PRGRM_CNTR_START_BASE_IDX = 0 # macro +mmCP_MEC1_PRGRM_CNTR_START = 0x1e46 # macro +mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX = 0 # macro +mmCP_MEC2_PRGRM_CNTR_START = 0x1e47 # macro +mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX = 0 # macro +mmCP_CE_INTR_ROUTINE_START = 0x1e48 # macro +mmCP_CE_INTR_ROUTINE_START_BASE_IDX = 0 # macro +mmCP_PFP_INTR_ROUTINE_START = 0x1e49 # macro +mmCP_PFP_INTR_ROUTINE_START_BASE_IDX = 0 # macro +mmCP_ME_INTR_ROUTINE_START = 0x1e4a # macro +mmCP_ME_INTR_ROUTINE_START_BASE_IDX = 0 # macro +mmCP_MEC1_INTR_ROUTINE_START = 0x1e4b # macro +mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX = 0 # macro +mmCP_MEC2_INTR_ROUTINE_START = 0x1e4c # macro +mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX = 0 # macro +mmCP_CONTEXT_CNTL = 0x1e4d # macro +mmCP_CONTEXT_CNTL_BASE_IDX = 0 # macro +mmCP_MAX_CONTEXT = 0x1e4e # macro +mmCP_MAX_CONTEXT_BASE_IDX = 0 # macro +mmCP_IQ_WAIT_TIME1 = 0x1e4f # macro +mmCP_IQ_WAIT_TIME1_BASE_IDX = 0 # macro +mmCP_IQ_WAIT_TIME2 = 0x1e50 # macro +mmCP_IQ_WAIT_TIME2_BASE_IDX = 0 # macro +mmCP_RB0_BASE_HI = 0x1e51 # macro +mmCP_RB0_BASE_HI_BASE_IDX = 0 # macro +mmCP_RB1_BASE_HI = 0x1e52 # macro +mmCP_RB1_BASE_HI_BASE_IDX = 0 # macro +mmCP_VMID_RESET = 0x1e53 # macro +mmCP_VMID_RESET_BASE_IDX = 0 # macro +mmCPC_INT_CNTL = 0x1e54 # macro +mmCPC_INT_CNTL_BASE_IDX = 0 # macro +mmCPC_INT_STATUS = 0x1e55 # macro +mmCPC_INT_STATUS_BASE_IDX = 0 # macro +mmCP_VMID_PREEMPT = 0x1e56 # macro +mmCP_VMID_PREEMPT_BASE_IDX = 0 # macro +mmCPC_INT_CNTX_ID = 0x1e57 # macro +mmCPC_INT_CNTX_ID_BASE_IDX = 0 # macro +mmCP_PQ_STATUS = 0x1e58 # macro +mmCP_PQ_STATUS_BASE_IDX = 0 # macro +mmCP_MEC1_F32_INT_DIS = 0x1e5d # macro +mmCP_MEC1_F32_INT_DIS_BASE_IDX = 0 # macro +mmCP_MEC2_F32_INT_DIS = 0x1e5e # macro +mmCP_MEC2_F32_INT_DIS_BASE_IDX = 0 # macro +mmCP_VMID_STATUS = 0x1e5f # macro +mmCP_VMID_STATUS_BASE_IDX = 0 # macro +mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO = 0x1e60 # macro +mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro +mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI = 0x1e61 # macro +mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro +mmCPC_SUSPEND_CTX_SAVE_CONTROL = 0x1e62 # macro +mmCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro +mmCPC_SUSPEND_CNTL_STACK_OFFSET = 0x1e63 # macro +mmCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro +mmCPC_SUSPEND_CNTL_STACK_SIZE = 0x1e64 # macro +mmCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX = 0 # macro +mmCPC_SUSPEND_WG_STATE_OFFSET = 0x1e65 # macro +mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro +mmCPC_SUSPEND_CTX_SAVE_SIZE = 0x1e66 # macro +mmCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX = 0 # macro +mmCPC_OS_PIPES = 0x1e67 # macro +mmCPC_OS_PIPES_BASE_IDX = 0 # macro +mmCP_SUSPEND_RESUME_REQ = 0x1e68 # macro +mmCP_SUSPEND_RESUME_REQ_BASE_IDX = 0 # macro +mmCP_SUSPEND_CNTL = 0x1e69 # macro +mmCP_SUSPEND_CNTL_BASE_IDX = 0 # macro +mmCP_IQ_WAIT_TIME3 = 0x1e6a # macro +mmCP_IQ_WAIT_TIME3_BASE_IDX = 0 # macro +mmCPC_DDID_BASE_ADDR_LO = 0x1e6b # macro +mmCPC_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro +mmCP_DDID_BASE_ADDR_LO = 0x1e6b # macro +mmCP_DDID_BASE_ADDR_LO_BASE_IDX = 0 # macro +mmCPC_DDID_BASE_ADDR_HI = 0x1e6c # macro +mmCPC_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro +mmCP_DDID_BASE_ADDR_HI = 0x1e6c # macro +mmCP_DDID_BASE_ADDR_HI_BASE_IDX = 0 # macro +mmCPC_DDID_CNTL = 0x1e6d # macro +mmCPC_DDID_CNTL_BASE_IDX = 0 # macro +mmCP_DDID_CNTL = 0x1e6d # macro +mmCP_DDID_CNTL_BASE_IDX = 0 # macro +mmCP_GFX_DDID_INFLIGHT_COUNT = 0x1e6e # macro +mmCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro +mmCP_GFX_DDID_WPTR = 0x1e6f # macro +mmCP_GFX_DDID_WPTR_BASE_IDX = 0 # macro +mmCP_GFX_DDID_RPTR = 0x1e70 # macro +mmCP_GFX_DDID_RPTR_BASE_IDX = 0 # macro +mmCP_GFX_DDID_DELTA_RPT_COUNT = 0x1e71 # macro +mmCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro +mmCP_GFX_HPD_STATUS0 = 0x1e72 # macro +mmCP_GFX_HPD_STATUS0_BASE_IDX = 0 # macro +mmCP_GFX_HPD_CONTROL0 = 0x1e73 # macro +mmCP_GFX_HPD_CONTROL0_BASE_IDX = 0 # macro +mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO = 0x1e74 # macro +mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX = 0 # macro +mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI = 0x1e75 # macro +mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX = 0 # macro +mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO = 0x1e76 # macro +mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX = 0 # macro +mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI = 0x1e77 # macro +mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX = 0 # macro +mmCP_GFX_INDEX_MUTEX = 0x1e78 # macro +mmCP_GFX_INDEX_MUTEX_BASE_IDX = 0 # macro +mmCP_GFX_MQD_BASE_ADDR = 0x1e7e # macro +mmCP_GFX_MQD_BASE_ADDR_BASE_IDX = 0 # macro +mmCP_GFX_MQD_BASE_ADDR_HI = 0x1e7f # macro +mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro +mmCP_GFX_HQD_ACTIVE = 0x1e80 # macro +mmCP_GFX_HQD_ACTIVE_BASE_IDX = 0 # macro +mmCP_GFX_HQD_VMID = 0x1e81 # macro +mmCP_GFX_HQD_VMID_BASE_IDX = 0 # macro +mmCP_GFX_HQD_QUEUE_PRIORITY = 0x1e84 # macro +mmCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro +mmCP_GFX_HQD_QUANTUM = 0x1e85 # macro +mmCP_GFX_HQD_QUANTUM_BASE_IDX = 0 # macro +mmCP_GFX_HQD_BASE = 0x1e86 # macro +mmCP_GFX_HQD_BASE_BASE_IDX = 0 # macro +mmCP_GFX_HQD_BASE_HI = 0x1e87 # macro +mmCP_GFX_HQD_BASE_HI_BASE_IDX = 0 # macro +mmCP_GFX_HQD_RPTR = 0x1e88 # macro +mmCP_GFX_HQD_RPTR_BASE_IDX = 0 # macro +mmCP_GFX_HQD_RPTR_ADDR = 0x1e89 # macro +mmCP_GFX_HQD_RPTR_ADDR_BASE_IDX = 0 # macro +mmCP_GFX_HQD_RPTR_ADDR_HI = 0x1e8a # macro +mmCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmCP_RB_WPTR_POLL_ADDR_LO = 0x1e8b # macro +mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmCP_RB_WPTR_POLL_ADDR_HI = 0x1e8c # macro +mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmCP_RB_DOORBELL_CONTROL = 0x1e8d # macro +mmCP_RB_DOORBELL_CONTROL_BASE_IDX = 0 # macro +mmCP_GFX_HQD_OFFSET = 0x1e8e # macro +mmCP_GFX_HQD_OFFSET_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CNTL = 0x1e8f # macro +mmCP_GFX_HQD_CNTL_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CSMD_RPTR = 0x1e90 # macro +mmCP_GFX_HQD_CSMD_RPTR_BASE_IDX = 0 # macro +mmCP_GFX_HQD_WPTR = 0x1e91 # macro +mmCP_GFX_HQD_WPTR_BASE_IDX = 0 # macro +mmCP_GFX_HQD_WPTR_HI = 0x1e92 # macro +mmCP_GFX_HQD_WPTR_HI_BASE_IDX = 0 # macro +mmCP_GFX_HQD_DEQUEUE_REQUEST = 0x1e93 # macro +mmCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro +mmCP_GFX_HQD_MAPPED = 0x1e94 # macro +mmCP_GFX_HQD_MAPPED_BASE_IDX = 0 # macro +mmCP_GFX_HQD_QUE_MGR_CONTROL = 0x1e95 # macro +mmCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX = 0 # macro +mmCP_GFX_HQD_HQ_STATUS0 = 0x1e98 # macro +mmCP_GFX_HQD_HQ_STATUS0_BASE_IDX = 0 # macro +mmCP_GFX_HQD_HQ_CONTROL0 = 0x1e99 # macro +mmCP_GFX_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro +mmCP_GFX_MQD_CONTROL = 0x1e9a # macro +mmCP_GFX_MQD_CONTROL_BASE_IDX = 0 # macro +mmCP_HQD_GFX_CONTROL = 0x1e9f # macro +mmCP_HQD_GFX_CONTROL_BASE_IDX = 0 # macro +mmCP_HQD_GFX_STATUS = 0x1ea0 # macro +mmCP_HQD_GFX_STATUS_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_RPTR_WR = 0x1ea1 # macro +mmCP_GFX_HQD_CE_RPTR_WR_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_BASE = 0x1ea2 # macro +mmCP_GFX_HQD_CE_BASE_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_BASE_HI = 0x1ea3 # macro +mmCP_GFX_HQD_CE_BASE_HI_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_RPTR = 0x1ea4 # macro +mmCP_GFX_HQD_CE_RPTR_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_RPTR_ADDR = 0x1ea5 # macro +mmCP_GFX_HQD_CE_RPTR_ADDR_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_RPTR_ADDR_HI = 0x1ea6 # macro +mmCP_GFX_HQD_CE_RPTR_ADDR_HI_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO = 0x1ea7 # macro +mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI = 0x1ea8 # macro +mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_OFFSET = 0x1ea9 # macro +mmCP_GFX_HQD_CE_OFFSET_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_CNTL = 0x1eaa # macro +mmCP_GFX_HQD_CE_CNTL_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_CSMD_RPTR = 0x1eab # macro +mmCP_GFX_HQD_CE_CSMD_RPTR_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_WPTR = 0x1eac # macro +mmCP_GFX_HQD_CE_WPTR_BASE_IDX = 0 # macro +mmCP_GFX_HQD_CE_WPTR_HI = 0x1ead # macro +mmCP_GFX_HQD_CE_WPTR_HI_BASE_IDX = 0 # macro +mmCP_CE_DOORBELL_CONTROL = 0x1eae # macro +mmCP_CE_DOORBELL_CONTROL_BASE_IDX = 0 # macro +mmCP_DMA_WATCH0_ADDR_LO = 0x1ec0 # macro +mmCP_DMA_WATCH0_ADDR_LO_BASE_IDX = 0 # macro +mmCP_DMA_WATCH0_ADDR_HI = 0x1ec1 # macro +mmCP_DMA_WATCH0_ADDR_HI_BASE_IDX = 0 # macro +mmCP_DMA_WATCH0_MASK = 0x1ec2 # macro +mmCP_DMA_WATCH0_MASK_BASE_IDX = 0 # macro +mmCP_DMA_WATCH0_CNTL = 0x1ec3 # macro +mmCP_DMA_WATCH0_CNTL_BASE_IDX = 0 # macro +mmCP_DMA_WATCH1_ADDR_LO = 0x1ec4 # macro +mmCP_DMA_WATCH1_ADDR_LO_BASE_IDX = 0 # macro +mmCP_DMA_WATCH1_ADDR_HI = 0x1ec5 # macro +mmCP_DMA_WATCH1_ADDR_HI_BASE_IDX = 0 # macro +mmCP_DMA_WATCH1_MASK = 0x1ec6 # macro +mmCP_DMA_WATCH1_MASK_BASE_IDX = 0 # macro +mmCP_DMA_WATCH1_CNTL = 0x1ec7 # macro +mmCP_DMA_WATCH1_CNTL_BASE_IDX = 0 # macro +mmCP_DMA_WATCH2_ADDR_LO = 0x1ec8 # macro +mmCP_DMA_WATCH2_ADDR_LO_BASE_IDX = 0 # macro +mmCP_DMA_WATCH2_ADDR_HI = 0x1ec9 # macro +mmCP_DMA_WATCH2_ADDR_HI_BASE_IDX = 0 # macro +mmCP_DMA_WATCH2_MASK = 0x1eca # macro +mmCP_DMA_WATCH2_MASK_BASE_IDX = 0 # macro +mmCP_DMA_WATCH2_CNTL = 0x1ecb # macro +mmCP_DMA_WATCH2_CNTL_BASE_IDX = 0 # macro +mmCP_DMA_WATCH3_ADDR_LO = 0x1ecc # macro +mmCP_DMA_WATCH3_ADDR_LO_BASE_IDX = 0 # macro +mmCP_DMA_WATCH3_ADDR_HI = 0x1ecd # macro +mmCP_DMA_WATCH3_ADDR_HI_BASE_IDX = 0 # macro +mmCP_DMA_WATCH3_MASK = 0x1ece # macro +mmCP_DMA_WATCH3_MASK_BASE_IDX = 0 # macro +mmCP_DMA_WATCH3_CNTL = 0x1ecf # macro +mmCP_DMA_WATCH3_CNTL_BASE_IDX = 0 # macro +mmCP_DMA_WATCH_STAT_ADDR_LO = 0x1ed0 # macro +mmCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX = 0 # macro +mmCP_DMA_WATCH_STAT_ADDR_HI = 0x1ed1 # macro +mmCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX = 0 # macro +mmCP_DMA_WATCH_STAT = 0x1ed2 # macro +mmCP_DMA_WATCH_STAT_BASE_IDX = 0 # macro +mmCP_PFP_JT_STAT = 0x1ed3 # macro +mmCP_PFP_JT_STAT_BASE_IDX = 0 # macro +mmCP_CE_JT_STAT = 0x1ed4 # macro +mmCP_CE_JT_STAT_BASE_IDX = 0 # macro +mmCP_MEC_JT_STAT = 0x1ed5 # macro +mmCP_MEC_JT_STAT_BASE_IDX = 0 # macro +mmCP_FETCHER_SOURCE = 0x1f1e # macro +mmCP_FETCHER_SOURCE_BASE_IDX = 0 # macro +mmCP_CE_CS_PARTITION_INDEX = 0x1f1f # macro +mmCP_CE_CS_PARTITION_INDEX_BASE_IDX = 0 # macro +mmCP_RB_DOORBELL_CLEAR = 0x1f28 # macro +mmCP_RB_DOORBELL_CLEAR_BASE_IDX = 0 # macro +mmCP_RB0_ACTIVE = 0x1f40 # macro +mmCP_RB0_ACTIVE_BASE_IDX = 0 # macro +mmCP_RB_ACTIVE = 0x1f40 # macro +mmCP_RB_ACTIVE_BASE_IDX = 0 # macro +mmCP_RB1_ACTIVE = 0x1f41 # macro +mmCP_RB1_ACTIVE_BASE_IDX = 0 # macro +mmCP_RB_STATUS = 0x1f43 # macro +mmCP_RB_STATUS_BASE_IDX = 0 # macro +mmCPG_RCIU_CAM_INDEX = 0x1f44 # macro +mmCPG_RCIU_CAM_INDEX_BASE_IDX = 0 # macro +mmCPG_RCIU_CAM_DATA = 0x1f45 # macro +mmCPG_RCIU_CAM_DATA_BASE_IDX = 0 # macro +mmCPG_RCIU_CAM_DATA_PHASE0 = 0x1f45 # macro +mmCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX = 0 # macro +mmCPG_RCIU_CAM_DATA_PHASE1 = 0x1f45 # macro +mmCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX = 0 # macro +mmCPG_RCIU_CAM_DATA_PHASE2 = 0x1f45 # macro +mmCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX = 0 # macro +mmCP_GPU_TIMESTAMP_OFFSET_LO = 0x1f4c # macro +mmCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX = 0 # macro +mmCP_GPU_TIMESTAMP_OFFSET_HI = 0x1f4d # macro +mmCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX = 0 # macro +mmCPF_GCR_CNTL = 0x1f53 # macro +mmCPF_GCR_CNTL_BASE_IDX = 0 # macro +mmCPG_UTCL1_STATUS = 0x1f54 # macro +mmCPG_UTCL1_STATUS_BASE_IDX = 0 # macro +mmCPC_UTCL1_STATUS = 0x1f55 # macro +mmCPC_UTCL1_STATUS_BASE_IDX = 0 # macro +mmCPF_UTCL1_STATUS = 0x1f56 # macro +mmCPF_UTCL1_STATUS_BASE_IDX = 0 # macro +mmCP_SD_CNTL = 0x1f57 # macro +mmCP_SD_CNTL_BASE_IDX = 0 # macro +mmCP_SOFT_RESET_CNTL = 0x1f59 # macro +mmCP_SOFT_RESET_CNTL_BASE_IDX = 0 # macro +mmCP_CPC_GFX_CNTL = 0x1f5a # macro +mmCP_CPC_GFX_CNTL_BASE_IDX = 0 # macro +mmSPI_ARB_PRIORITY = 0x1f60 # macro +mmSPI_ARB_PRIORITY_BASE_IDX = 0 # macro +mmSPI_ARB_CYCLES_0 = 0x1f61 # macro +mmSPI_ARB_CYCLES_0_BASE_IDX = 0 # macro +mmSPI_ARB_CYCLES_1 = 0x1f62 # macro +mmSPI_ARB_CYCLES_1_BASE_IDX = 0 # macro +mmSPI_WCL_PIPE_PERCENT_GFX = 0x1f67 # macro +mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX = 0 # macro +mmSPI_WCL_PIPE_PERCENT_HP3D = 0x1f68 # macro +mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX = 0 # macro +mmSPI_WCL_PIPE_PERCENT_CS0 = 0x1f69 # macro +mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX = 0 # macro +mmSPI_WCL_PIPE_PERCENT_CS1 = 0x1f6a # macro +mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX = 0 # macro +mmSPI_WCL_PIPE_PERCENT_CS2 = 0x1f6b # macro +mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX = 0 # macro +mmSPI_WCL_PIPE_PERCENT_CS3 = 0x1f6c # macro +mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX = 0 # macro +mmSPI_GDBG_WAVE_CNTL = 0x1f71 # macro +mmSPI_GDBG_WAVE_CNTL_BASE_IDX = 0 # macro +mmSPI_GDBG_TRAP_CONFIG = 0x1f72 # macro +mmSPI_GDBG_TRAP_CONFIG_BASE_IDX = 0 # macro +mmSPI_GDBG_TRAP_MASK = 0x1f73 # macro +mmSPI_GDBG_TRAP_MASK_BASE_IDX = 0 # macro +mmSPI_GDBG_WAVE_CNTL2 = 0x1f74 # macro +mmSPI_GDBG_WAVE_CNTL2_BASE_IDX = 0 # macro +mmSPI_GDBG_WAVE_CNTL3 = 0x1f75 # macro +mmSPI_GDBG_WAVE_CNTL3_BASE_IDX = 0 # macro +mmSPI_GDBG_TRAP_DATA0 = 0x1f78 # macro +mmSPI_GDBG_TRAP_DATA0_BASE_IDX = 0 # macro +mmSPI_GDBG_TRAP_DATA1 = 0x1f79 # macro +mmSPI_GDBG_TRAP_DATA1_BASE_IDX = 0 # macro +mmSPI_COMPUTE_QUEUE_RESET = 0x1f7b # macro +mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_CU_0 = 0x1f7c # macro +mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_CU_1 = 0x1f7d # macro +mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_CU_2 = 0x1f7e # macro +mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_CU_3 = 0x1f7f # macro +mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_CU_4 = 0x1f80 # macro +mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_CU_5 = 0x1f81 # macro +mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_CU_6 = 0x1f82 # macro +mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_CU_7 = 0x1f83 # macro +mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_CU_8 = 0x1f84 # macro +mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_CU_9 = 0x1f85 # macro +mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_0 = 0x1f86 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_1 = 0x1f87 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_2 = 0x1f88 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_3 = 0x1f89 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_4 = 0x1f8a # macro +mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_5 = 0x1f8b # macro +mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_6 = 0x1f8c # macro +mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_7 = 0x1f8d # macro +mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_8 = 0x1f8e # macro +mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX = 0 # macro +mmSPI_RESOURCE_RESERVE_EN_CU_9 = 0x1f8f # macro +mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX = 0 # macro +mmSPI_COMPUTE_WF_CTX_SAVE = 0x1f9c # macro +mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX = 0 # macro +mmSPI_ARB_CNTL_0 = 0x1f9d # macro +mmSPI_ARB_CNTL_0_BASE_IDX = 0 # macro +mmSPI_FEATURE_CTRL = 0x1f9e # macro +mmSPI_FEATURE_CTRL_BASE_IDX = 0 # macro +mmSPI_SHADER_RSRC_LIMIT_CTRL = 0x1f9f # macro +mmSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX = 0 # macro +mmCP_HPD_MES_ROQ_OFFSETS = 0x1fa4 # macro +mmCP_HPD_MES_ROQ_OFFSETS_BASE_IDX = 0 # macro +mmCP_HPD_ROQ_OFFSETS = 0x1fa4 # macro +mmCP_HPD_ROQ_OFFSETS_BASE_IDX = 0 # macro +mmCP_HPD_STATUS0 = 0x1fa5 # macro +mmCP_HPD_STATUS0_BASE_IDX = 0 # macro +mmCP_HPD_UTCL1_CNTL = 0x1fa6 # macro +mmCP_HPD_UTCL1_CNTL_BASE_IDX = 0 # macro +mmCP_HPD_UTCL1_ERROR = 0x1fa7 # macro +mmCP_HPD_UTCL1_ERROR_BASE_IDX = 0 # macro +mmCP_HPD_UTCL1_ERROR_ADDR = 0x1fa8 # macro +mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX = 0 # macro +mmCP_MQD_BASE_ADDR = 0x1fa9 # macro +mmCP_MQD_BASE_ADDR_BASE_IDX = 0 # macro +mmCP_MQD_BASE_ADDR_HI = 0x1faa # macro +mmCP_MQD_BASE_ADDR_HI_BASE_IDX = 0 # macro +mmCP_HQD_ACTIVE = 0x1fab # macro +mmCP_HQD_ACTIVE_BASE_IDX = 0 # macro +mmCP_HQD_VMID = 0x1fac # macro +mmCP_HQD_VMID_BASE_IDX = 0 # macro +mmCP_HQD_PERSISTENT_STATE = 0x1fad # macro +mmCP_HQD_PERSISTENT_STATE_BASE_IDX = 0 # macro +mmCP_HQD_PIPE_PRIORITY = 0x1fae # macro +mmCP_HQD_PIPE_PRIORITY_BASE_IDX = 0 # macro +mmCP_HQD_QUEUE_PRIORITY = 0x1faf # macro +mmCP_HQD_QUEUE_PRIORITY_BASE_IDX = 0 # macro +mmCP_HQD_QUANTUM = 0x1fb0 # macro +mmCP_HQD_QUANTUM_BASE_IDX = 0 # macro +mmCP_HQD_PQ_BASE = 0x1fb1 # macro +mmCP_HQD_PQ_BASE_BASE_IDX = 0 # macro +mmCP_HQD_PQ_BASE_HI = 0x1fb2 # macro +mmCP_HQD_PQ_BASE_HI_BASE_IDX = 0 # macro +mmCP_HQD_PQ_RPTR = 0x1fb3 # macro +mmCP_HQD_PQ_RPTR_BASE_IDX = 0 # macro +mmCP_HQD_PQ_RPTR_REPORT_ADDR = 0x1fb4 # macro +mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX = 0 # macro +mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI = 0x1fb5 # macro +mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX = 0 # macro +mmCP_HQD_PQ_WPTR_POLL_ADDR = 0x1fb6 # macro +mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX = 0 # macro +mmCP_HQD_PQ_WPTR_POLL_ADDR_HI = 0x1fb7 # macro +mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX = 0 # macro +mmCP_HQD_PQ_DOORBELL_CONTROL = 0x1fb8 # macro +mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX = 0 # macro +mmCP_HQD_PQ_CONTROL = 0x1fba # macro +mmCP_HQD_PQ_CONTROL_BASE_IDX = 0 # macro +mmCP_HQD_IB_BASE_ADDR = 0x1fbb # macro +mmCP_HQD_IB_BASE_ADDR_BASE_IDX = 0 # macro +mmCP_HQD_IB_BASE_ADDR_HI = 0x1fbc # macro +mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX = 0 # macro +mmCP_HQD_IB_RPTR = 0x1fbd # macro +mmCP_HQD_IB_RPTR_BASE_IDX = 0 # macro +mmCP_HQD_IB_CONTROL = 0x1fbe # macro +mmCP_HQD_IB_CONTROL_BASE_IDX = 0 # macro +mmCP_HQD_IQ_TIMER = 0x1fbf # macro +mmCP_HQD_IQ_TIMER_BASE_IDX = 0 # macro +mmCP_HQD_IQ_RPTR = 0x1fc0 # macro +mmCP_HQD_IQ_RPTR_BASE_IDX = 0 # macro +mmCP_HQD_DEQUEUE_REQUEST = 0x1fc1 # macro +mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX = 0 # macro +mmCP_HQD_DMA_OFFLOAD = 0x1fc2 # macro +mmCP_HQD_DMA_OFFLOAD_BASE_IDX = 0 # macro +mmCP_HQD_OFFLOAD = 0x1fc2 # macro +mmCP_HQD_OFFLOAD_BASE_IDX = 0 # macro +mmCP_HQD_SEMA_CMD = 0x1fc3 # macro +mmCP_HQD_SEMA_CMD_BASE_IDX = 0 # macro +mmCP_HQD_MSG_TYPE = 0x1fc4 # macro +mmCP_HQD_MSG_TYPE_BASE_IDX = 0 # macro +mmCP_HQD_ATOMIC0_PREOP_LO = 0x1fc5 # macro +mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX = 0 # macro +mmCP_HQD_ATOMIC0_PREOP_HI = 0x1fc6 # macro +mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX = 0 # macro +mmCP_HQD_ATOMIC1_PREOP_LO = 0x1fc7 # macro +mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX = 0 # macro +mmCP_HQD_ATOMIC1_PREOP_HI = 0x1fc8 # macro +mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX = 0 # macro +mmCP_HQD_HQ_SCHEDULER0 = 0x1fc9 # macro +mmCP_HQD_HQ_SCHEDULER0_BASE_IDX = 0 # macro +mmCP_HQD_HQ_STATUS0 = 0x1fc9 # macro +mmCP_HQD_HQ_STATUS0_BASE_IDX = 0 # macro +mmCP_HQD_HQ_CONTROL0 = 0x1fca # macro +mmCP_HQD_HQ_CONTROL0_BASE_IDX = 0 # macro +mmCP_HQD_HQ_SCHEDULER1 = 0x1fca # macro +mmCP_HQD_HQ_SCHEDULER1_BASE_IDX = 0 # macro +mmCP_MQD_CONTROL = 0x1fcb # macro +mmCP_MQD_CONTROL_BASE_IDX = 0 # macro +mmCP_HQD_HQ_STATUS1 = 0x1fcc # macro +mmCP_HQD_HQ_STATUS1_BASE_IDX = 0 # macro +mmCP_HQD_HQ_CONTROL1 = 0x1fcd # macro +mmCP_HQD_HQ_CONTROL1_BASE_IDX = 0 # macro +mmCP_HQD_EOP_BASE_ADDR = 0x1fce # macro +mmCP_HQD_EOP_BASE_ADDR_BASE_IDX = 0 # macro +mmCP_HQD_EOP_BASE_ADDR_HI = 0x1fcf # macro +mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX = 0 # macro +mmCP_HQD_EOP_CONTROL = 0x1fd0 # macro +mmCP_HQD_EOP_CONTROL_BASE_IDX = 0 # macro +mmCP_HQD_EOP_RPTR = 0x1fd1 # macro +mmCP_HQD_EOP_RPTR_BASE_IDX = 0 # macro +mmCP_HQD_EOP_WPTR = 0x1fd2 # macro +mmCP_HQD_EOP_WPTR_BASE_IDX = 0 # macro +mmCP_HQD_EOP_EVENTS = 0x1fd3 # macro +mmCP_HQD_EOP_EVENTS_BASE_IDX = 0 # macro +mmCP_HQD_CTX_SAVE_BASE_ADDR_LO = 0x1fd4 # macro +mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX = 0 # macro +mmCP_HQD_CTX_SAVE_BASE_ADDR_HI = 0x1fd5 # macro +mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX = 0 # macro +mmCP_HQD_CTX_SAVE_CONTROL = 0x1fd6 # macro +mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX = 0 # macro +mmCP_HQD_CNTL_STACK_OFFSET = 0x1fd7 # macro +mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro +mmCP_HQD_CNTL_STACK_SIZE = 0x1fd8 # macro +mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX = 0 # macro +mmCP_HQD_WG_STATE_OFFSET = 0x1fd9 # macro +mmCP_HQD_WG_STATE_OFFSET_BASE_IDX = 0 # macro +mmCP_HQD_CTX_SAVE_SIZE = 0x1fda # macro +mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX = 0 # macro +mmCP_HQD_GDS_RESOURCE_STATE = 0x1fdb # macro +mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX = 0 # macro +mmCP_HQD_ERROR = 0x1fdc # macro +mmCP_HQD_ERROR_BASE_IDX = 0 # macro +mmCP_HQD_EOP_WPTR_MEM = 0x1fdd # macro +mmCP_HQD_EOP_WPTR_MEM_BASE_IDX = 0 # macro +mmCP_HQD_AQL_CONTROL = 0x1fde # macro +mmCP_HQD_AQL_CONTROL_BASE_IDX = 0 # macro +mmCP_HQD_PQ_WPTR_LO = 0x1fdf # macro +mmCP_HQD_PQ_WPTR_LO_BASE_IDX = 0 # macro +mmCP_HQD_PQ_WPTR_HI = 0x1fe0 # macro +mmCP_HQD_PQ_WPTR_HI_BASE_IDX = 0 # macro +mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET = 0x1fe1 # macro +mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX = 0 # macro +mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT = 0x1fe2 # macro +mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX = 0 # macro +mmCP_HQD_SUSPEND_WG_STATE_OFFSET = 0x1fe3 # macro +mmCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX = 0 # macro +mmCP_HQD_DDID_RPTR = 0x1fe4 # macro +mmCP_HQD_DDID_RPTR_BASE_IDX = 0 # macro +mmCP_HQD_DDID_WPTR = 0x1fe5 # macro +mmCP_HQD_DDID_WPTR_BASE_IDX = 0 # macro +mmCP_HQD_DDID_INFLIGHT_COUNT = 0x1fe6 # macro +mmCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX = 0 # macro +mmCP_HQD_DDID_DELTA_RPT_COUNT = 0x1fe7 # macro +mmCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX = 0 # macro +mmCP_HQD_DEQUEUE_STATUS = 0x1fe8 # macro +mmCP_HQD_DEQUEUE_STATUS_BASE_IDX = 0 # macro +mmDIDT_IND_INDEX = 0x2020 # macro +mmDIDT_IND_INDEX_BASE_IDX = 0 # macro +mmDIDT_IND_DATA = 0x2021 # macro +mmDIDT_IND_DATA_BASE_IDX = 0 # macro +mmDIDT_INDEX_AUTO_INCR_EN = 0x2022 # macro +mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX = 0 # macro +mmGC_CAC_CTRL_1 = 0x2024 # macro +mmGC_CAC_CTRL_1_BASE_IDX = 0 # macro +mmGC_CAC_CTRL_2 = 0x2025 # macro +mmGC_CAC_CTRL_2_BASE_IDX = 0 # macro +mmGC_CAC_AGGR_LOWER = 0x2026 # macro +mmGC_CAC_AGGR_LOWER_BASE_IDX = 0 # macro +mmGC_CAC_AGGR_UPPER = 0x2027 # macro +mmGC_CAC_AGGR_UPPER_BASE_IDX = 0 # macro +mmGC_CAC_SOFT_CTRL = 0x202a # macro +mmGC_CAC_SOFT_CTRL_BASE_IDX = 0 # macro +mmGC_EDC_CTRL = 0x202b # macro +mmGC_EDC_CTRL_BASE_IDX = 0 # macro +mmGC_EDC_THRESHOLD = 0x202c # macro +mmGC_EDC_THRESHOLD_BASE_IDX = 0 # macro +mmGC_EDC_STATUS = 0x202d # macro +mmGC_EDC_STATUS_BASE_IDX = 0 # macro +mmGC_EDC_OVERFLOW = 0x202e # macro +mmGC_EDC_OVERFLOW_BASE_IDX = 0 # macro +mmGC_EDC_ROLLING_POWER_DELTA = 0x202f # macro +mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX = 0 # macro +mmGC_THROTTLE_CTRL = 0x2030 # macro +mmGC_THROTTLE_CTRL_BASE_IDX = 0 # macro +mmGC_THROTTLE_CTRL1 = 0x2031 # macro +mmGC_THROTTLE_CTRL1_BASE_IDX = 0 # macro +mmGC_THROTTLE_STATUS = 0x2032 # macro +mmGC_THROTTLE_STATUS_BASE_IDX = 0 # macro +mmEDC_PERF_COUNTER = 0x2033 # macro +mmEDC_PERF_COUNTER_BASE_IDX = 0 # macro +mmPCC_PERF_COUNTER = 0x2034 # macro +mmPCC_PERF_COUNTER_BASE_IDX = 0 # macro +mmPWRBRK_PERF_COUNTER = 0x2035 # macro +mmPWRBRK_PERF_COUNTER_BASE_IDX = 0 # macro +mmGC_EDC_STRETCH_CTRL = 0x2036 # macro +mmGC_EDC_STRETCH_CTRL_BASE_IDX = 0 # macro +mmGC_EDC_STRETCH_THRESHOLD = 0x2037 # macro +mmGC_EDC_STRETCH_THRESHOLD_BASE_IDX = 0 # macro +mmEDC_HYSTERESIS_CNTL = 0x2038 # macro +mmEDC_HYSTERESIS_CNTL_BASE_IDX = 0 # macro +mmEDC_HYSTERESIS_STAT = 0x2039 # macro +mmEDC_HYSTERESIS_STAT_BASE_IDX = 0 # macro +mmGC_CAC_IND_INDEX = 0x203c # macro +mmGC_CAC_IND_INDEX_BASE_IDX = 0 # macro +mmGC_CAC_IND_DATA = 0x203d # macro +mmGC_CAC_IND_DATA_BASE_IDX = 0 # macro +mmSE_CAC_IND_INDEX = 0x203e # macro +mmSE_CAC_IND_INDEX_BASE_IDX = 0 # macro +mmSE_CAC_IND_DATA = 0x203f # macro +mmSE_CAC_IND_DATA_BASE_IDX = 0 # macro +mmTCP_WATCH0_ADDR_H = 0x2040 # macro +mmTCP_WATCH0_ADDR_H_BASE_IDX = 0 # macro +mmTCP_WATCH0_ADDR_L = 0x2041 # macro +mmTCP_WATCH0_ADDR_L_BASE_IDX = 0 # macro +mmTCP_WATCH0_CNTL = 0x2042 # macro +mmTCP_WATCH0_CNTL_BASE_IDX = 0 # macro +mmTCP_WATCH1_ADDR_H = 0x2043 # macro +mmTCP_WATCH1_ADDR_H_BASE_IDX = 0 # macro +mmTCP_WATCH1_ADDR_L = 0x2044 # macro +mmTCP_WATCH1_ADDR_L_BASE_IDX = 0 # macro +mmTCP_WATCH1_CNTL = 0x2045 # macro +mmTCP_WATCH1_CNTL_BASE_IDX = 0 # macro +mmTCP_WATCH2_ADDR_H = 0x2046 # macro +mmTCP_WATCH2_ADDR_H_BASE_IDX = 0 # macro +mmTCP_WATCH2_ADDR_L = 0x2047 # macro +mmTCP_WATCH2_ADDR_L_BASE_IDX = 0 # macro +mmTCP_WATCH2_CNTL = 0x2048 # macro +mmTCP_WATCH2_CNTL_BASE_IDX = 0 # macro +mmTCP_WATCH3_ADDR_H = 0x2049 # macro +mmTCP_WATCH3_ADDR_H_BASE_IDX = 0 # macro +mmTCP_WATCH3_ADDR_L = 0x204a # macro +mmTCP_WATCH3_ADDR_L_BASE_IDX = 0 # macro +mmTCP_WATCH3_CNTL = 0x204b # macro +mmTCP_WATCH3_CNTL_BASE_IDX = 0 # macro +mmTCP_PERFCOUNTER_FILTER = 0x2059 # macro +mmTCP_PERFCOUNTER_FILTER_BASE_IDX = 0 # macro +mmTCP_PERFCOUNTER_FILTER_EN = 0x205a # macro +mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX = 0 # macro +mmTCP_PERFCOUNTER_FILTER2 = 0x205b # macro +mmTCP_PERFCOUNTER_FILTER2_BASE_IDX = 0 # macro +mmGDS_VMID0_BASE = 0x20a0 # macro +mmGDS_VMID0_BASE_BASE_IDX = 0 # macro +mmGDS_VMID0_SIZE = 0x20a1 # macro +mmGDS_VMID0_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID1_BASE = 0x20a2 # macro +mmGDS_VMID1_BASE_BASE_IDX = 0 # macro +mmGDS_VMID1_SIZE = 0x20a3 # macro +mmGDS_VMID1_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID2_BASE = 0x20a4 # macro +mmGDS_VMID2_BASE_BASE_IDX = 0 # macro +mmGDS_VMID2_SIZE = 0x20a5 # macro +mmGDS_VMID2_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID3_BASE = 0x20a6 # macro +mmGDS_VMID3_BASE_BASE_IDX = 0 # macro +mmGDS_VMID3_SIZE = 0x20a7 # macro +mmGDS_VMID3_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID4_BASE = 0x20a8 # macro +mmGDS_VMID4_BASE_BASE_IDX = 0 # macro +mmGDS_VMID4_SIZE = 0x20a9 # macro +mmGDS_VMID4_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID5_BASE = 0x20aa # macro +mmGDS_VMID5_BASE_BASE_IDX = 0 # macro +mmGDS_VMID5_SIZE = 0x20ab # macro +mmGDS_VMID5_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID6_BASE = 0x20ac # macro +mmGDS_VMID6_BASE_BASE_IDX = 0 # macro +mmGDS_VMID6_SIZE = 0x20ad # macro +mmGDS_VMID6_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID7_BASE = 0x20ae # macro +mmGDS_VMID7_BASE_BASE_IDX = 0 # macro +mmGDS_VMID7_SIZE = 0x20af # macro +mmGDS_VMID7_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID8_BASE = 0x20b0 # macro +mmGDS_VMID8_BASE_BASE_IDX = 0 # macro +mmGDS_VMID8_SIZE = 0x20b1 # macro +mmGDS_VMID8_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID9_BASE = 0x20b2 # macro +mmGDS_VMID9_BASE_BASE_IDX = 0 # macro +mmGDS_VMID9_SIZE = 0x20b3 # macro +mmGDS_VMID9_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID10_BASE = 0x20b4 # macro +mmGDS_VMID10_BASE_BASE_IDX = 0 # macro +mmGDS_VMID10_SIZE = 0x20b5 # macro +mmGDS_VMID10_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID11_BASE = 0x20b6 # macro +mmGDS_VMID11_BASE_BASE_IDX = 0 # macro +mmGDS_VMID11_SIZE = 0x20b7 # macro +mmGDS_VMID11_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID12_BASE = 0x20b8 # macro +mmGDS_VMID12_BASE_BASE_IDX = 0 # macro +mmGDS_VMID12_SIZE = 0x20b9 # macro +mmGDS_VMID12_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID13_BASE = 0x20ba # macro +mmGDS_VMID13_BASE_BASE_IDX = 0 # macro +mmGDS_VMID13_SIZE = 0x20bb # macro +mmGDS_VMID13_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID14_BASE = 0x20bc # macro +mmGDS_VMID14_BASE_BASE_IDX = 0 # macro +mmGDS_VMID14_SIZE = 0x20bd # macro +mmGDS_VMID14_SIZE_BASE_IDX = 0 # macro +mmGDS_VMID15_BASE = 0x20be # macro +mmGDS_VMID15_BASE_BASE_IDX = 0 # macro +mmGDS_VMID15_SIZE = 0x20bf # macro +mmGDS_VMID15_SIZE_BASE_IDX = 0 # macro +mmGDS_GWS_VMID0 = 0x20c0 # macro +mmGDS_GWS_VMID0_BASE_IDX = 0 # macro +mmGDS_GWS_VMID1 = 0x20c1 # macro +mmGDS_GWS_VMID1_BASE_IDX = 0 # macro +mmGDS_GWS_VMID2 = 0x20c2 # macro +mmGDS_GWS_VMID2_BASE_IDX = 0 # macro +mmGDS_GWS_VMID3 = 0x20c3 # macro +mmGDS_GWS_VMID3_BASE_IDX = 0 # macro +mmGDS_GWS_VMID4 = 0x20c4 # macro +mmGDS_GWS_VMID4_BASE_IDX = 0 # macro +mmGDS_GWS_VMID5 = 0x20c5 # macro +mmGDS_GWS_VMID5_BASE_IDX = 0 # macro +mmGDS_GWS_VMID6 = 0x20c6 # macro +mmGDS_GWS_VMID6_BASE_IDX = 0 # macro +mmGDS_GWS_VMID7 = 0x20c7 # macro +mmGDS_GWS_VMID7_BASE_IDX = 0 # macro +mmGDS_GWS_VMID8 = 0x20c8 # macro +mmGDS_GWS_VMID8_BASE_IDX = 0 # macro +mmGDS_GWS_VMID9 = 0x20c9 # macro +mmGDS_GWS_VMID9_BASE_IDX = 0 # macro +mmGDS_GWS_VMID10 = 0x20ca # macro +mmGDS_GWS_VMID10_BASE_IDX = 0 # macro +mmGDS_GWS_VMID11 = 0x20cb # macro +mmGDS_GWS_VMID11_BASE_IDX = 0 # macro +mmGDS_GWS_VMID12 = 0x20cc # macro +mmGDS_GWS_VMID12_BASE_IDX = 0 # macro +mmGDS_GWS_VMID13 = 0x20cd # macro +mmGDS_GWS_VMID13_BASE_IDX = 0 # macro +mmGDS_GWS_VMID14 = 0x20ce # macro +mmGDS_GWS_VMID14_BASE_IDX = 0 # macro +mmGDS_GWS_VMID15 = 0x20cf # macro +mmGDS_GWS_VMID15_BASE_IDX = 0 # macro +mmGDS_OA_VMID0 = 0x20d0 # macro +mmGDS_OA_VMID0_BASE_IDX = 0 # macro +mmGDS_OA_VMID1 = 0x20d1 # macro +mmGDS_OA_VMID1_BASE_IDX = 0 # macro +mmGDS_OA_VMID2 = 0x20d2 # macro +mmGDS_OA_VMID2_BASE_IDX = 0 # macro +mmGDS_OA_VMID3 = 0x20d3 # macro +mmGDS_OA_VMID3_BASE_IDX = 0 # macro +mmGDS_OA_VMID4 = 0x20d4 # macro +mmGDS_OA_VMID4_BASE_IDX = 0 # macro +mmGDS_OA_VMID5 = 0x20d5 # macro +mmGDS_OA_VMID5_BASE_IDX = 0 # macro +mmGDS_OA_VMID6 = 0x20d6 # macro +mmGDS_OA_VMID6_BASE_IDX = 0 # macro +mmGDS_OA_VMID7 = 0x20d7 # macro +mmGDS_OA_VMID7_BASE_IDX = 0 # macro +mmGDS_OA_VMID8 = 0x20d8 # macro +mmGDS_OA_VMID8_BASE_IDX = 0 # macro +mmGDS_OA_VMID9 = 0x20d9 # macro +mmGDS_OA_VMID9_BASE_IDX = 0 # macro +mmGDS_OA_VMID10 = 0x20da # macro +mmGDS_OA_VMID10_BASE_IDX = 0 # macro +mmGDS_OA_VMID11 = 0x20db # macro +mmGDS_OA_VMID11_BASE_IDX = 0 # macro +mmGDS_OA_VMID12 = 0x20dc # macro +mmGDS_OA_VMID12_BASE_IDX = 0 # macro +mmGDS_OA_VMID13 = 0x20dd # macro +mmGDS_OA_VMID13_BASE_IDX = 0 # macro +mmGDS_OA_VMID14 = 0x20de # macro +mmGDS_OA_VMID14_BASE_IDX = 0 # macro +mmGDS_OA_VMID15 = 0x20df # macro +mmGDS_OA_VMID15_BASE_IDX = 0 # macro +mmGDS_GWS_RESET0 = 0x20e4 # macro +mmGDS_GWS_RESET0_BASE_IDX = 0 # macro +mmGDS_GWS_RESET1 = 0x20e5 # macro +mmGDS_GWS_RESET1_BASE_IDX = 0 # macro +mmGDS_GWS_RESOURCE_RESET = 0x20e6 # macro +mmGDS_GWS_RESOURCE_RESET_BASE_IDX = 0 # macro +mmGDS_COMPUTE_MAX_WAVE_ID = 0x20e8 # macro +mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX = 0 # macro +mmGDS_OA_RESET_MASK = 0x20e9 # macro +mmGDS_OA_RESET_MASK_BASE_IDX = 0 # macro +mmGDS_OA_RESET = 0x20ea # macro +mmGDS_OA_RESET_BASE_IDX = 0 # macro +mmGDS_ENHANCE2 = 0x20eb # macro +mmGDS_ENHANCE2_BASE_IDX = 0 # macro +mmGDS_OA_CGPG_RESTORE = 0x20ec # macro +mmGDS_OA_CGPG_RESTORE_BASE_IDX = 0 # macro +mmGDS_CS_CTXSW_STATUS = 0x20ed # macro +mmGDS_CS_CTXSW_STATUS_BASE_IDX = 0 # macro +mmGDS_CS_CTXSW_CNT0 = 0x20ee # macro +mmGDS_CS_CTXSW_CNT0_BASE_IDX = 0 # macro +mmGDS_CS_CTXSW_CNT1 = 0x20ef # macro +mmGDS_CS_CTXSW_CNT1_BASE_IDX = 0 # macro +mmGDS_CS_CTXSW_CNT2 = 0x20f0 # macro +mmGDS_CS_CTXSW_CNT2_BASE_IDX = 0 # macro +mmGDS_CS_CTXSW_CNT3 = 0x20f1 # macro +mmGDS_CS_CTXSW_CNT3_BASE_IDX = 0 # macro +mmGDS_GFX_CTXSW_STATUS = 0x20f2 # macro +mmGDS_GFX_CTXSW_STATUS_BASE_IDX = 0 # macro +mmGDS_VS_CTXSW_CNT0 = 0x20f3 # macro +mmGDS_VS_CTXSW_CNT0_BASE_IDX = 0 # macro +mmGDS_VS_CTXSW_CNT1 = 0x20f4 # macro +mmGDS_VS_CTXSW_CNT1_BASE_IDX = 0 # macro +mmGDS_VS_CTXSW_CNT2 = 0x20f5 # macro +mmGDS_VS_CTXSW_CNT2_BASE_IDX = 0 # macro +mmGDS_VS_CTXSW_CNT3 = 0x20f6 # macro +mmGDS_VS_CTXSW_CNT3_BASE_IDX = 0 # macro +mmGDS_PS_CTXSW_CNT0 = 0x20f7 # macro +mmGDS_PS_CTXSW_CNT0_BASE_IDX = 0 # macro +mmGDS_PS_CTXSW_CNT1 = 0x20f8 # macro +mmGDS_PS_CTXSW_CNT1_BASE_IDX = 0 # macro +mmGDS_PS_CTXSW_CNT2 = 0x20f9 # macro +mmGDS_PS_CTXSW_CNT2_BASE_IDX = 0 # macro +mmGDS_PS_CTXSW_CNT3 = 0x20fa # macro +mmGDS_PS_CTXSW_CNT3_BASE_IDX = 0 # macro +mmGDS_PS_CTXSW_IDX = 0x20fb # macro +mmGDS_PS_CTXSW_IDX_BASE_IDX = 0 # macro +mmGDS_GS_CTXSW_CNT0 = 0x2117 # macro +mmGDS_GS_CTXSW_CNT0_BASE_IDX = 0 # macro +mmGDS_GS_CTXSW_CNT1 = 0x2118 # macro +mmGDS_GS_CTXSW_CNT1_BASE_IDX = 0 # macro +mmGDS_GS_CTXSW_CNT2 = 0x2119 # macro +mmGDS_GS_CTXSW_CNT2_BASE_IDX = 0 # macro +mmGDS_GS_CTXSW_CNT3 = 0x211a # macro +mmGDS_GS_CTXSW_CNT3_BASE_IDX = 0 # macro +mmGDS_MEMORY_CLEAN = 0x211f # macro +mmGDS_MEMORY_CLEAN_BASE_IDX = 0 # macro +mmDB_RENDER_CONTROL = 0x0000 # macro +mmDB_RENDER_CONTROL_BASE_IDX = 1 # macro +mmDB_COUNT_CONTROL = 0x0001 # macro +mmDB_COUNT_CONTROL_BASE_IDX = 1 # macro +mmDB_DEPTH_VIEW = 0x0002 # macro +mmDB_DEPTH_VIEW_BASE_IDX = 1 # macro +mmDB_RENDER_OVERRIDE = 0x0003 # macro +mmDB_RENDER_OVERRIDE_BASE_IDX = 1 # macro +mmDB_RENDER_OVERRIDE2 = 0x0004 # macro +mmDB_RENDER_OVERRIDE2_BASE_IDX = 1 # macro +mmDB_HTILE_DATA_BASE = 0x0005 # macro +mmDB_HTILE_DATA_BASE_BASE_IDX = 1 # macro +mmDB_DEPTH_SIZE_XY = 0x0007 # macro +mmDB_DEPTH_SIZE_XY_BASE_IDX = 1 # macro +mmDB_DEPTH_BOUNDS_MIN = 0x0008 # macro +mmDB_DEPTH_BOUNDS_MIN_BASE_IDX = 1 # macro +mmDB_DEPTH_BOUNDS_MAX = 0x0009 # macro +mmDB_DEPTH_BOUNDS_MAX_BASE_IDX = 1 # macro +mmDB_STENCIL_CLEAR = 0x000a # macro +mmDB_STENCIL_CLEAR_BASE_IDX = 1 # macro +mmDB_DEPTH_CLEAR = 0x000b # macro +mmDB_DEPTH_CLEAR_BASE_IDX = 1 # macro +mmPA_SC_SCREEN_SCISSOR_TL = 0x000c # macro +mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX = 1 # macro +mmPA_SC_SCREEN_SCISSOR_BR = 0x000d # macro +mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX = 1 # macro +mmDB_DFSM_CONTROL = 0x000e # macro +mmDB_DFSM_CONTROL_BASE_IDX = 1 # macro +mmDB_RESERVED_REG_2 = 0x000f # macro +mmDB_RESERVED_REG_2_BASE_IDX = 1 # macro +mmDB_Z_INFO = 0x0010 # macro +mmDB_Z_INFO_BASE_IDX = 1 # macro +mmDB_STENCIL_INFO = 0x0011 # macro +mmDB_STENCIL_INFO_BASE_IDX = 1 # macro +mmDB_Z_READ_BASE = 0x0012 # macro +mmDB_Z_READ_BASE_BASE_IDX = 1 # macro +mmDB_STENCIL_READ_BASE = 0x0013 # macro +mmDB_STENCIL_READ_BASE_BASE_IDX = 1 # macro +mmDB_Z_WRITE_BASE = 0x0014 # macro +mmDB_Z_WRITE_BASE_BASE_IDX = 1 # macro +mmDB_STENCIL_WRITE_BASE = 0x0015 # macro +mmDB_STENCIL_WRITE_BASE_BASE_IDX = 1 # macro +mmDB_RESERVED_REG_1 = 0x0016 # macro +mmDB_RESERVED_REG_1_BASE_IDX = 1 # macro +mmDB_RESERVED_REG_3 = 0x0017 # macro +mmDB_RESERVED_REG_3_BASE_IDX = 1 # macro +mmDB_VRS_OVERRIDE_CNTL = 0x0019 # macro +mmDB_VRS_OVERRIDE_CNTL_BASE_IDX = 1 # macro +mmDB_Z_READ_BASE_HI = 0x001a # macro +mmDB_Z_READ_BASE_HI_BASE_IDX = 1 # macro +mmDB_STENCIL_READ_BASE_HI = 0x001b # macro +mmDB_STENCIL_READ_BASE_HI_BASE_IDX = 1 # macro +mmDB_Z_WRITE_BASE_HI = 0x001c # macro +mmDB_Z_WRITE_BASE_HI_BASE_IDX = 1 # macro +mmDB_STENCIL_WRITE_BASE_HI = 0x001d # macro +mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX = 1 # macro +mmDB_HTILE_DATA_BASE_HI = 0x001e # macro +mmDB_HTILE_DATA_BASE_HI_BASE_IDX = 1 # macro +mmDB_RMI_L2_CACHE_CONTROL = 0x001f # macro +mmDB_RMI_L2_CACHE_CONTROL_BASE_IDX = 1 # macro +mmTA_BC_BASE_ADDR = 0x0020 # macro +mmTA_BC_BASE_ADDR_BASE_IDX = 1 # macro +mmTA_BC_BASE_ADDR_HI = 0x0021 # macro +mmTA_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro +mmCOHER_DEST_BASE_HI_0 = 0x007a # macro +mmCOHER_DEST_BASE_HI_0_BASE_IDX = 1 # macro +mmCOHER_DEST_BASE_HI_1 = 0x007b # macro +mmCOHER_DEST_BASE_HI_1_BASE_IDX = 1 # macro +mmCOHER_DEST_BASE_HI_2 = 0x007c # macro +mmCOHER_DEST_BASE_HI_2_BASE_IDX = 1 # macro +mmCOHER_DEST_BASE_HI_3 = 0x007d # macro +mmCOHER_DEST_BASE_HI_3_BASE_IDX = 1 # macro +mmCOHER_DEST_BASE_2 = 0x007e # macro +mmCOHER_DEST_BASE_2_BASE_IDX = 1 # macro +mmCOHER_DEST_BASE_3 = 0x007f # macro +mmCOHER_DEST_BASE_3_BASE_IDX = 1 # macro +mmPA_SC_WINDOW_OFFSET = 0x0080 # macro +mmPA_SC_WINDOW_OFFSET_BASE_IDX = 1 # macro +mmPA_SC_WINDOW_SCISSOR_TL = 0x0081 # macro +mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX = 1 # macro +mmPA_SC_WINDOW_SCISSOR_BR = 0x0082 # macro +mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX = 1 # macro +mmPA_SC_CLIPRECT_RULE = 0x0083 # macro +mmPA_SC_CLIPRECT_RULE_BASE_IDX = 1 # macro +mmPA_SC_CLIPRECT_0_TL = 0x0084 # macro +mmPA_SC_CLIPRECT_0_TL_BASE_IDX = 1 # macro +mmPA_SC_CLIPRECT_0_BR = 0x0085 # macro +mmPA_SC_CLIPRECT_0_BR_BASE_IDX = 1 # macro +mmPA_SC_CLIPRECT_1_TL = 0x0086 # macro +mmPA_SC_CLIPRECT_1_TL_BASE_IDX = 1 # macro +mmPA_SC_CLIPRECT_1_BR = 0x0087 # macro +mmPA_SC_CLIPRECT_1_BR_BASE_IDX = 1 # macro +mmPA_SC_CLIPRECT_2_TL = 0x0088 # macro +mmPA_SC_CLIPRECT_2_TL_BASE_IDX = 1 # macro +mmPA_SC_CLIPRECT_2_BR = 0x0089 # macro +mmPA_SC_CLIPRECT_2_BR_BASE_IDX = 1 # macro +mmPA_SC_CLIPRECT_3_TL = 0x008a # macro +mmPA_SC_CLIPRECT_3_TL_BASE_IDX = 1 # macro +mmPA_SC_CLIPRECT_3_BR = 0x008b # macro +mmPA_SC_CLIPRECT_3_BR_BASE_IDX = 1 # macro +mmPA_SC_EDGERULE = 0x008c # macro +mmPA_SC_EDGERULE_BASE_IDX = 1 # macro +mmPA_SU_HARDWARE_SCREEN_OFFSET = 0x008d # macro +mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX = 1 # macro +mmCB_TARGET_MASK = 0x008e # macro +mmCB_TARGET_MASK_BASE_IDX = 1 # macro +mmCB_SHADER_MASK = 0x008f # macro +mmCB_SHADER_MASK_BASE_IDX = 1 # macro +mmPA_SC_GENERIC_SCISSOR_TL = 0x0090 # macro +mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX = 1 # macro +mmPA_SC_GENERIC_SCISSOR_BR = 0x0091 # macro +mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX = 1 # macro +mmCOHER_DEST_BASE_0 = 0x0092 # macro +mmCOHER_DEST_BASE_0_BASE_IDX = 1 # macro +mmCOHER_DEST_BASE_1 = 0x0093 # macro +mmCOHER_DEST_BASE_1_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_0_TL = 0x0094 # macro +mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_0_BR = 0x0095 # macro +mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_1_TL = 0x0096 # macro +mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_1_BR = 0x0097 # macro +mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_2_TL = 0x0098 # macro +mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_2_BR = 0x0099 # macro +mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_3_TL = 0x009a # macro +mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_3_BR = 0x009b # macro +mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_4_TL = 0x009c # macro +mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_4_BR = 0x009d # macro +mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_5_TL = 0x009e # macro +mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_5_BR = 0x009f # macro +mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_6_TL = 0x00a0 # macro +mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_6_BR = 0x00a1 # macro +mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_7_TL = 0x00a2 # macro +mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_7_BR = 0x00a3 # macro +mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_8_TL = 0x00a4 # macro +mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_8_BR = 0x00a5 # macro +mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_9_TL = 0x00a6 # macro +mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_9_BR = 0x00a7 # macro +mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_10_TL = 0x00a8 # macro +mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_10_BR = 0x00a9 # macro +mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_11_TL = 0x00aa # macro +mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_11_BR = 0x00ab # macro +mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_12_TL = 0x00ac # macro +mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_12_BR = 0x00ad # macro +mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_13_TL = 0x00ae # macro +mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_13_BR = 0x00af # macro +mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_14_TL = 0x00b0 # macro +mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_14_BR = 0x00b1 # macro +mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_15_TL = 0x00b2 # macro +mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX = 1 # macro +mmPA_SC_VPORT_SCISSOR_15_BR = 0x00b3 # macro +mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_0 = 0x00b4 # macro +mmPA_SC_VPORT_ZMIN_0_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_0 = 0x00b5 # macro +mmPA_SC_VPORT_ZMAX_0_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_1 = 0x00b6 # macro +mmPA_SC_VPORT_ZMIN_1_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_1 = 0x00b7 # macro +mmPA_SC_VPORT_ZMAX_1_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_2 = 0x00b8 # macro +mmPA_SC_VPORT_ZMIN_2_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_2 = 0x00b9 # macro +mmPA_SC_VPORT_ZMAX_2_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_3 = 0x00ba # macro +mmPA_SC_VPORT_ZMIN_3_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_3 = 0x00bb # macro +mmPA_SC_VPORT_ZMAX_3_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_4 = 0x00bc # macro +mmPA_SC_VPORT_ZMIN_4_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_4 = 0x00bd # macro +mmPA_SC_VPORT_ZMAX_4_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_5 = 0x00be # macro +mmPA_SC_VPORT_ZMIN_5_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_5 = 0x00bf # macro +mmPA_SC_VPORT_ZMAX_5_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_6 = 0x00c0 # macro +mmPA_SC_VPORT_ZMIN_6_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_6 = 0x00c1 # macro +mmPA_SC_VPORT_ZMAX_6_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_7 = 0x00c2 # macro +mmPA_SC_VPORT_ZMIN_7_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_7 = 0x00c3 # macro +mmPA_SC_VPORT_ZMAX_7_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_8 = 0x00c4 # macro +mmPA_SC_VPORT_ZMIN_8_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_8 = 0x00c5 # macro +mmPA_SC_VPORT_ZMAX_8_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_9 = 0x00c6 # macro +mmPA_SC_VPORT_ZMIN_9_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_9 = 0x00c7 # macro +mmPA_SC_VPORT_ZMAX_9_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_10 = 0x00c8 # macro +mmPA_SC_VPORT_ZMIN_10_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_10 = 0x00c9 # macro +mmPA_SC_VPORT_ZMAX_10_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_11 = 0x00ca # macro +mmPA_SC_VPORT_ZMIN_11_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_11 = 0x00cb # macro +mmPA_SC_VPORT_ZMAX_11_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_12 = 0x00cc # macro +mmPA_SC_VPORT_ZMIN_12_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_12 = 0x00cd # macro +mmPA_SC_VPORT_ZMAX_12_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_13 = 0x00ce # macro +mmPA_SC_VPORT_ZMIN_13_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_13 = 0x00cf # macro +mmPA_SC_VPORT_ZMAX_13_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_14 = 0x00d0 # macro +mmPA_SC_VPORT_ZMIN_14_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_14 = 0x00d1 # macro +mmPA_SC_VPORT_ZMAX_14_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMIN_15 = 0x00d2 # macro +mmPA_SC_VPORT_ZMIN_15_BASE_IDX = 1 # macro +mmPA_SC_VPORT_ZMAX_15 = 0x00d3 # macro +mmPA_SC_VPORT_ZMAX_15_BASE_IDX = 1 # macro +mmPA_SC_RASTER_CONFIG = 0x00d4 # macro +mmPA_SC_RASTER_CONFIG_BASE_IDX = 1 # macro +mmPA_SC_RASTER_CONFIG_1 = 0x00d5 # macro +mmPA_SC_RASTER_CONFIG_1_BASE_IDX = 1 # macro +mmPA_SC_SCREEN_EXTENT_CONTROL = 0x00d6 # macro +mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX = 1 # macro +mmPA_SC_TILE_STEERING_OVERRIDE = 0x00d7 # macro +mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX = 1 # macro +mmCP_PERFMON_CNTX_CNTL = 0x00d8 # macro +mmCP_PERFMON_CNTX_CNTL_BASE_IDX = 1 # macro +mmCP_PIPEID = 0x00d9 # macro +mmCP_PIPEID_BASE_IDX = 1 # macro +mmCP_RINGID = 0x00d9 # macro +mmCP_RINGID_BASE_IDX = 1 # macro +mmCP_VMID = 0x00da # macro +mmCP_VMID_BASE_IDX = 1 # macro +mmCONTEXT_RESERVED_REG0 = 0x00db # macro +mmCONTEXT_RESERVED_REG0_BASE_IDX = 1 # macro +mmCONTEXT_RESERVED_REG1 = 0x00dc # macro +mmCONTEXT_RESERVED_REG1_BASE_IDX = 1 # macro +mmVGT_MAX_VTX_INDX = 0x0100 # macro +mmVGT_MAX_VTX_INDX_BASE_IDX = 1 # macro +mmVGT_MIN_VTX_INDX = 0x0101 # macro +mmVGT_MIN_VTX_INDX_BASE_IDX = 1 # macro +mmVGT_INDX_OFFSET = 0x0102 # macro +mmVGT_INDX_OFFSET_BASE_IDX = 1 # macro +mmVGT_MULTI_PRIM_IB_RESET_INDX = 0x0103 # macro +mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX = 1 # macro +mmCB_RMI_GL2_CACHE_CONTROL = 0x0104 # macro +mmCB_RMI_GL2_CACHE_CONTROL_BASE_IDX = 1 # macro +mmCB_BLEND_RED = 0x0105 # macro +mmCB_BLEND_RED_BASE_IDX = 1 # macro +mmCB_BLEND_GREEN = 0x0106 # macro +mmCB_BLEND_GREEN_BASE_IDX = 1 # macro +mmCB_BLEND_BLUE = 0x0107 # macro +mmCB_BLEND_BLUE_BASE_IDX = 1 # macro +mmCB_BLEND_ALPHA = 0x0108 # macro +mmCB_BLEND_ALPHA_BASE_IDX = 1 # macro +mmCB_DCC_CONTROL = 0x0109 # macro +mmCB_DCC_CONTROL_BASE_IDX = 1 # macro +mmCB_COVERAGE_OUT_CONTROL = 0x010a # macro +mmCB_COVERAGE_OUT_CONTROL_BASE_IDX = 1 # macro +mmDB_STENCIL_CONTROL = 0x010b # macro +mmDB_STENCIL_CONTROL_BASE_IDX = 1 # macro +mmDB_STENCILREFMASK = 0x010c # macro +mmDB_STENCILREFMASK_BASE_IDX = 1 # macro +mmDB_STENCILREFMASK_BF = 0x010d # macro +mmDB_STENCILREFMASK_BF_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE = 0x010f # macro +mmPA_CL_VPORT_XSCALE_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET = 0x0110 # macro +mmPA_CL_VPORT_XOFFSET_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE = 0x0111 # macro +mmPA_CL_VPORT_YSCALE_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET = 0x0112 # macro +mmPA_CL_VPORT_YOFFSET_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE = 0x0113 # macro +mmPA_CL_VPORT_ZSCALE_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET = 0x0114 # macro +mmPA_CL_VPORT_ZOFFSET_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_1 = 0x0115 # macro +mmPA_CL_VPORT_XSCALE_1_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_1 = 0x0116 # macro +mmPA_CL_VPORT_XOFFSET_1_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_1 = 0x0117 # macro +mmPA_CL_VPORT_YSCALE_1_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_1 = 0x0118 # macro +mmPA_CL_VPORT_YOFFSET_1_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_1 = 0x0119 # macro +mmPA_CL_VPORT_ZSCALE_1_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_1 = 0x011a # macro +mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_2 = 0x011b # macro +mmPA_CL_VPORT_XSCALE_2_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_2 = 0x011c # macro +mmPA_CL_VPORT_XOFFSET_2_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_2 = 0x011d # macro +mmPA_CL_VPORT_YSCALE_2_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_2 = 0x011e # macro +mmPA_CL_VPORT_YOFFSET_2_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_2 = 0x011f # macro +mmPA_CL_VPORT_ZSCALE_2_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_2 = 0x0120 # macro +mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_3 = 0x0121 # macro +mmPA_CL_VPORT_XSCALE_3_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_3 = 0x0122 # macro +mmPA_CL_VPORT_XOFFSET_3_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_3 = 0x0123 # macro +mmPA_CL_VPORT_YSCALE_3_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_3 = 0x0124 # macro +mmPA_CL_VPORT_YOFFSET_3_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_3 = 0x0125 # macro +mmPA_CL_VPORT_ZSCALE_3_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_3 = 0x0126 # macro +mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_4 = 0x0127 # macro +mmPA_CL_VPORT_XSCALE_4_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_4 = 0x0128 # macro +mmPA_CL_VPORT_XOFFSET_4_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_4 = 0x0129 # macro +mmPA_CL_VPORT_YSCALE_4_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_4 = 0x012a # macro +mmPA_CL_VPORT_YOFFSET_4_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_4 = 0x012b # macro +mmPA_CL_VPORT_ZSCALE_4_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_4 = 0x012c # macro +mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_5 = 0x012d # macro +mmPA_CL_VPORT_XSCALE_5_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_5 = 0x012e # macro +mmPA_CL_VPORT_XOFFSET_5_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_5 = 0x012f # macro +mmPA_CL_VPORT_YSCALE_5_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_5 = 0x0130 # macro +mmPA_CL_VPORT_YOFFSET_5_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_5 = 0x0131 # macro +mmPA_CL_VPORT_ZSCALE_5_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_5 = 0x0132 # macro +mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_6 = 0x0133 # macro +mmPA_CL_VPORT_XSCALE_6_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_6 = 0x0134 # macro +mmPA_CL_VPORT_XOFFSET_6_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_6 = 0x0135 # macro +mmPA_CL_VPORT_YSCALE_6_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_6 = 0x0136 # macro +mmPA_CL_VPORT_YOFFSET_6_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_6 = 0x0137 # macro +mmPA_CL_VPORT_ZSCALE_6_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_6 = 0x0138 # macro +mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_7 = 0x0139 # macro +mmPA_CL_VPORT_XSCALE_7_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_7 = 0x013a # macro +mmPA_CL_VPORT_XOFFSET_7_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_7 = 0x013b # macro +mmPA_CL_VPORT_YSCALE_7_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_7 = 0x013c # macro +mmPA_CL_VPORT_YOFFSET_7_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_7 = 0x013d # macro +mmPA_CL_VPORT_ZSCALE_7_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_7 = 0x013e # macro +mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_8 = 0x013f # macro +mmPA_CL_VPORT_XSCALE_8_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_8 = 0x0140 # macro +mmPA_CL_VPORT_XOFFSET_8_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_8 = 0x0141 # macro +mmPA_CL_VPORT_YSCALE_8_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_8 = 0x0142 # macro +mmPA_CL_VPORT_YOFFSET_8_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_8 = 0x0143 # macro +mmPA_CL_VPORT_ZSCALE_8_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_8 = 0x0144 # macro +mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_9 = 0x0145 # macro +mmPA_CL_VPORT_XSCALE_9_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_9 = 0x0146 # macro +mmPA_CL_VPORT_XOFFSET_9_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_9 = 0x0147 # macro +mmPA_CL_VPORT_YSCALE_9_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_9 = 0x0148 # macro +mmPA_CL_VPORT_YOFFSET_9_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_9 = 0x0149 # macro +mmPA_CL_VPORT_ZSCALE_9_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_9 = 0x014a # macro +mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_10 = 0x014b # macro +mmPA_CL_VPORT_XSCALE_10_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_10 = 0x014c # macro +mmPA_CL_VPORT_XOFFSET_10_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_10 = 0x014d # macro +mmPA_CL_VPORT_YSCALE_10_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_10 = 0x014e # macro +mmPA_CL_VPORT_YOFFSET_10_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_10 = 0x014f # macro +mmPA_CL_VPORT_ZSCALE_10_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_10 = 0x0150 # macro +mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_11 = 0x0151 # macro +mmPA_CL_VPORT_XSCALE_11_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_11 = 0x0152 # macro +mmPA_CL_VPORT_XOFFSET_11_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_11 = 0x0153 # macro +mmPA_CL_VPORT_YSCALE_11_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_11 = 0x0154 # macro +mmPA_CL_VPORT_YOFFSET_11_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_11 = 0x0155 # macro +mmPA_CL_VPORT_ZSCALE_11_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_11 = 0x0156 # macro +mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_12 = 0x0157 # macro +mmPA_CL_VPORT_XSCALE_12_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_12 = 0x0158 # macro +mmPA_CL_VPORT_XOFFSET_12_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_12 = 0x0159 # macro +mmPA_CL_VPORT_YSCALE_12_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_12 = 0x015a # macro +mmPA_CL_VPORT_YOFFSET_12_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_12 = 0x015b # macro +mmPA_CL_VPORT_ZSCALE_12_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_12 = 0x015c # macro +mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_13 = 0x015d # macro +mmPA_CL_VPORT_XSCALE_13_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_13 = 0x015e # macro +mmPA_CL_VPORT_XOFFSET_13_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_13 = 0x015f # macro +mmPA_CL_VPORT_YSCALE_13_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_13 = 0x0160 # macro +mmPA_CL_VPORT_YOFFSET_13_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_13 = 0x0161 # macro +mmPA_CL_VPORT_ZSCALE_13_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_13 = 0x0162 # macro +mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_14 = 0x0163 # macro +mmPA_CL_VPORT_XSCALE_14_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_14 = 0x0164 # macro +mmPA_CL_VPORT_XOFFSET_14_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_14 = 0x0165 # macro +mmPA_CL_VPORT_YSCALE_14_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_14 = 0x0166 # macro +mmPA_CL_VPORT_YOFFSET_14_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_14 = 0x0167 # macro +mmPA_CL_VPORT_ZSCALE_14_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_14 = 0x0168 # macro +mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XSCALE_15 = 0x0169 # macro +mmPA_CL_VPORT_XSCALE_15_BASE_IDX = 1 # macro +mmPA_CL_VPORT_XOFFSET_15 = 0x016a # macro +mmPA_CL_VPORT_XOFFSET_15_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YSCALE_15 = 0x016b # macro +mmPA_CL_VPORT_YSCALE_15_BASE_IDX = 1 # macro +mmPA_CL_VPORT_YOFFSET_15 = 0x016c # macro +mmPA_CL_VPORT_YOFFSET_15_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZSCALE_15 = 0x016d # macro +mmPA_CL_VPORT_ZSCALE_15_BASE_IDX = 1 # macro +mmPA_CL_VPORT_ZOFFSET_15 = 0x016e # macro +mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX = 1 # macro +mmPA_CL_UCP_0_X = 0x016f # macro +mmPA_CL_UCP_0_X_BASE_IDX = 1 # macro +mmPA_CL_UCP_0_Y = 0x0170 # macro +mmPA_CL_UCP_0_Y_BASE_IDX = 1 # macro +mmPA_CL_UCP_0_Z = 0x0171 # macro +mmPA_CL_UCP_0_Z_BASE_IDX = 1 # macro +mmPA_CL_UCP_0_W = 0x0172 # macro +mmPA_CL_UCP_0_W_BASE_IDX = 1 # macro +mmPA_CL_UCP_1_X = 0x0173 # macro +mmPA_CL_UCP_1_X_BASE_IDX = 1 # macro +mmPA_CL_UCP_1_Y = 0x0174 # macro +mmPA_CL_UCP_1_Y_BASE_IDX = 1 # macro +mmPA_CL_UCP_1_Z = 0x0175 # macro +mmPA_CL_UCP_1_Z_BASE_IDX = 1 # macro +mmPA_CL_UCP_1_W = 0x0176 # macro +mmPA_CL_UCP_1_W_BASE_IDX = 1 # macro +mmPA_CL_UCP_2_X = 0x0177 # macro +mmPA_CL_UCP_2_X_BASE_IDX = 1 # macro +mmPA_CL_UCP_2_Y = 0x0178 # macro +mmPA_CL_UCP_2_Y_BASE_IDX = 1 # macro +mmPA_CL_UCP_2_Z = 0x0179 # macro +mmPA_CL_UCP_2_Z_BASE_IDX = 1 # macro +mmPA_CL_UCP_2_W = 0x017a # macro +mmPA_CL_UCP_2_W_BASE_IDX = 1 # macro +mmPA_CL_UCP_3_X = 0x017b # macro +mmPA_CL_UCP_3_X_BASE_IDX = 1 # macro +mmPA_CL_UCP_3_Y = 0x017c # macro +mmPA_CL_UCP_3_Y_BASE_IDX = 1 # macro +mmPA_CL_UCP_3_Z = 0x017d # macro +mmPA_CL_UCP_3_Z_BASE_IDX = 1 # macro +mmPA_CL_UCP_3_W = 0x017e # macro +mmPA_CL_UCP_3_W_BASE_IDX = 1 # macro +mmPA_CL_UCP_4_X = 0x017f # macro +mmPA_CL_UCP_4_X_BASE_IDX = 1 # macro +mmPA_CL_UCP_4_Y = 0x0180 # macro +mmPA_CL_UCP_4_Y_BASE_IDX = 1 # macro +mmPA_CL_UCP_4_Z = 0x0181 # macro +mmPA_CL_UCP_4_Z_BASE_IDX = 1 # macro +mmPA_CL_UCP_4_W = 0x0182 # macro +mmPA_CL_UCP_4_W_BASE_IDX = 1 # macro +mmPA_CL_UCP_5_X = 0x0183 # macro +mmPA_CL_UCP_5_X_BASE_IDX = 1 # macro +mmPA_CL_UCP_5_Y = 0x0184 # macro +mmPA_CL_UCP_5_Y_BASE_IDX = 1 # macro +mmPA_CL_UCP_5_Z = 0x0185 # macro +mmPA_CL_UCP_5_Z_BASE_IDX = 1 # macro +mmPA_CL_UCP_5_W = 0x0186 # macro +mmPA_CL_UCP_5_W_BASE_IDX = 1 # macro +mmPA_CL_PROG_NEAR_CLIP_Z = 0x0187 # macro +mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_0 = 0x0191 # macro +mmSPI_PS_INPUT_CNTL_0_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_1 = 0x0192 # macro +mmSPI_PS_INPUT_CNTL_1_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_2 = 0x0193 # macro +mmSPI_PS_INPUT_CNTL_2_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_3 = 0x0194 # macro +mmSPI_PS_INPUT_CNTL_3_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_4 = 0x0195 # macro +mmSPI_PS_INPUT_CNTL_4_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_5 = 0x0196 # macro +mmSPI_PS_INPUT_CNTL_5_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_6 = 0x0197 # macro +mmSPI_PS_INPUT_CNTL_6_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_7 = 0x0198 # macro +mmSPI_PS_INPUT_CNTL_7_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_8 = 0x0199 # macro +mmSPI_PS_INPUT_CNTL_8_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_9 = 0x019a # macro +mmSPI_PS_INPUT_CNTL_9_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_10 = 0x019b # macro +mmSPI_PS_INPUT_CNTL_10_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_11 = 0x019c # macro +mmSPI_PS_INPUT_CNTL_11_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_12 = 0x019d # macro +mmSPI_PS_INPUT_CNTL_12_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_13 = 0x019e # macro +mmSPI_PS_INPUT_CNTL_13_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_14 = 0x019f # macro +mmSPI_PS_INPUT_CNTL_14_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_15 = 0x01a0 # macro +mmSPI_PS_INPUT_CNTL_15_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_16 = 0x01a1 # macro +mmSPI_PS_INPUT_CNTL_16_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_17 = 0x01a2 # macro +mmSPI_PS_INPUT_CNTL_17_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_18 = 0x01a3 # macro +mmSPI_PS_INPUT_CNTL_18_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_19 = 0x01a4 # macro +mmSPI_PS_INPUT_CNTL_19_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_20 = 0x01a5 # macro +mmSPI_PS_INPUT_CNTL_20_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_21 = 0x01a6 # macro +mmSPI_PS_INPUT_CNTL_21_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_22 = 0x01a7 # macro +mmSPI_PS_INPUT_CNTL_22_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_23 = 0x01a8 # macro +mmSPI_PS_INPUT_CNTL_23_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_24 = 0x01a9 # macro +mmSPI_PS_INPUT_CNTL_24_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_25 = 0x01aa # macro +mmSPI_PS_INPUT_CNTL_25_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_26 = 0x01ab # macro +mmSPI_PS_INPUT_CNTL_26_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_27 = 0x01ac # macro +mmSPI_PS_INPUT_CNTL_27_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_28 = 0x01ad # macro +mmSPI_PS_INPUT_CNTL_28_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_29 = 0x01ae # macro +mmSPI_PS_INPUT_CNTL_29_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_30 = 0x01af # macro +mmSPI_PS_INPUT_CNTL_30_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_CNTL_31 = 0x01b0 # macro +mmSPI_PS_INPUT_CNTL_31_BASE_IDX = 1 # macro +mmSPI_VS_OUT_CONFIG = 0x01b1 # macro +mmSPI_VS_OUT_CONFIG_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_ENA = 0x01b3 # macro +mmSPI_PS_INPUT_ENA_BASE_IDX = 1 # macro +mmSPI_PS_INPUT_ADDR = 0x01b4 # macro +mmSPI_PS_INPUT_ADDR_BASE_IDX = 1 # macro +mmSPI_INTERP_CONTROL_0 = 0x01b5 # macro +mmSPI_INTERP_CONTROL_0_BASE_IDX = 1 # macro +mmSPI_PS_IN_CONTROL = 0x01b6 # macro +mmSPI_PS_IN_CONTROL_BASE_IDX = 1 # macro +mmSPI_BARYC_CNTL = 0x01b8 # macro +mmSPI_BARYC_CNTL_BASE_IDX = 1 # macro +mmSPI_TMPRING_SIZE = 0x01ba # macro +mmSPI_TMPRING_SIZE_BASE_IDX = 1 # macro +mmSPI_SHADER_IDX_FORMAT = 0x01c2 # macro +mmSPI_SHADER_IDX_FORMAT_BASE_IDX = 1 # macro +mmSPI_SHADER_POS_FORMAT = 0x01c3 # macro +mmSPI_SHADER_POS_FORMAT_BASE_IDX = 1 # macro +mmSPI_SHADER_Z_FORMAT = 0x01c4 # macro +mmSPI_SHADER_Z_FORMAT_BASE_IDX = 1 # macro +mmSPI_SHADER_COL_FORMAT = 0x01c5 # macro +mmSPI_SHADER_COL_FORMAT_BASE_IDX = 1 # macro +mmSX_PS_DOWNCONVERT_CONTROL = 0x01d4 # macro +mmSX_PS_DOWNCONVERT_CONTROL_BASE_IDX = 1 # macro +mmSX_PS_DOWNCONVERT = 0x01d5 # macro +mmSX_PS_DOWNCONVERT_BASE_IDX = 1 # macro +mmSX_BLEND_OPT_EPSILON = 0x01d6 # macro +mmSX_BLEND_OPT_EPSILON_BASE_IDX = 1 # macro +mmSX_BLEND_OPT_CONTROL = 0x01d7 # macro +mmSX_BLEND_OPT_CONTROL_BASE_IDX = 1 # macro +mmSX_MRT0_BLEND_OPT = 0x01d8 # macro +mmSX_MRT0_BLEND_OPT_BASE_IDX = 1 # macro +mmSX_MRT1_BLEND_OPT = 0x01d9 # macro +mmSX_MRT1_BLEND_OPT_BASE_IDX = 1 # macro +mmSX_MRT2_BLEND_OPT = 0x01da # macro +mmSX_MRT2_BLEND_OPT_BASE_IDX = 1 # macro +mmSX_MRT3_BLEND_OPT = 0x01db # macro +mmSX_MRT3_BLEND_OPT_BASE_IDX = 1 # macro +mmSX_MRT4_BLEND_OPT = 0x01dc # macro +mmSX_MRT4_BLEND_OPT_BASE_IDX = 1 # macro +mmSX_MRT5_BLEND_OPT = 0x01dd # macro +mmSX_MRT5_BLEND_OPT_BASE_IDX = 1 # macro +mmSX_MRT6_BLEND_OPT = 0x01de # macro +mmSX_MRT6_BLEND_OPT_BASE_IDX = 1 # macro +mmSX_MRT7_BLEND_OPT = 0x01df # macro +mmSX_MRT7_BLEND_OPT_BASE_IDX = 1 # macro +mmCB_BLEND0_CONTROL = 0x01e0 # macro +mmCB_BLEND0_CONTROL_BASE_IDX = 1 # macro +mmCB_BLEND1_CONTROL = 0x01e1 # macro +mmCB_BLEND1_CONTROL_BASE_IDX = 1 # macro +mmCB_BLEND2_CONTROL = 0x01e2 # macro +mmCB_BLEND2_CONTROL_BASE_IDX = 1 # macro +mmCB_BLEND3_CONTROL = 0x01e3 # macro +mmCB_BLEND3_CONTROL_BASE_IDX = 1 # macro +mmCB_BLEND4_CONTROL = 0x01e4 # macro +mmCB_BLEND4_CONTROL_BASE_IDX = 1 # macro +mmCB_BLEND5_CONTROL = 0x01e5 # macro +mmCB_BLEND5_CONTROL_BASE_IDX = 1 # macro +mmCB_BLEND6_CONTROL = 0x01e6 # macro +mmCB_BLEND6_CONTROL_BASE_IDX = 1 # macro +mmCB_BLEND7_CONTROL = 0x01e7 # macro +mmCB_BLEND7_CONTROL_BASE_IDX = 1 # macro +mmCS_COPY_STATE = 0x01f3 # macro +mmCS_COPY_STATE_BASE_IDX = 1 # macro +mmGFX_COPY_STATE = 0x01f4 # macro +mmGFX_COPY_STATE_BASE_IDX = 1 # macro +mmPA_CL_POINT_X_RAD = 0x01f5 # macro +mmPA_CL_POINT_X_RAD_BASE_IDX = 1 # macro +mmPA_CL_POINT_Y_RAD = 0x01f6 # macro +mmPA_CL_POINT_Y_RAD_BASE_IDX = 1 # macro +mmPA_CL_POINT_SIZE = 0x01f7 # macro +mmPA_CL_POINT_SIZE_BASE_IDX = 1 # macro +mmPA_CL_POINT_CULL_RAD = 0x01f8 # macro +mmPA_CL_POINT_CULL_RAD_BASE_IDX = 1 # macro +mmVGT_DMA_BASE_HI = 0x01f9 # macro +mmVGT_DMA_BASE_HI_BASE_IDX = 1 # macro +mmVGT_DMA_BASE = 0x01fa # macro +mmVGT_DMA_BASE_BASE_IDX = 1 # macro +mmVGT_DRAW_INITIATOR = 0x01fc # macro +mmVGT_DRAW_INITIATOR_BASE_IDX = 1 # macro +mmVGT_IMMED_DATA = 0x01fd # macro +mmVGT_IMMED_DATA_BASE_IDX = 1 # macro +mmVGT_EVENT_ADDRESS_REG = 0x01fe # macro +mmVGT_EVENT_ADDRESS_REG_BASE_IDX = 1 # macro +mmGE_MAX_OUTPUT_PER_SUBGROUP = 0x01ff # macro +mmGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX = 1 # macro +mmDB_DEPTH_CONTROL = 0x0200 # macro +mmDB_DEPTH_CONTROL_BASE_IDX = 1 # macro +mmDB_EQAA = 0x0201 # macro +mmDB_EQAA_BASE_IDX = 1 # macro +mmCB_COLOR_CONTROL = 0x0202 # macro +mmCB_COLOR_CONTROL_BASE_IDX = 1 # macro +mmDB_SHADER_CONTROL = 0x0203 # macro +mmDB_SHADER_CONTROL_BASE_IDX = 1 # macro +mmPA_CL_CLIP_CNTL = 0x0204 # macro +mmPA_CL_CLIP_CNTL_BASE_IDX = 1 # macro +mmPA_SU_SC_MODE_CNTL = 0x0205 # macro +mmPA_SU_SC_MODE_CNTL_BASE_IDX = 1 # macro +mmPA_CL_VTE_CNTL = 0x0206 # macro +mmPA_CL_VTE_CNTL_BASE_IDX = 1 # macro +mmPA_CL_VS_OUT_CNTL = 0x0207 # macro +mmPA_CL_VS_OUT_CNTL_BASE_IDX = 1 # macro +mmPA_CL_NANINF_CNTL = 0x0208 # macro +mmPA_CL_NANINF_CNTL_BASE_IDX = 1 # macro +mmPA_SU_LINE_STIPPLE_CNTL = 0x0209 # macro +mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX = 1 # macro +mmPA_SU_LINE_STIPPLE_SCALE = 0x020a # macro +mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX = 1 # macro +mmPA_SU_PRIM_FILTER_CNTL = 0x020b # macro +mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro +mmPA_SU_SMALL_PRIM_FILTER_CNTL = 0x020c # macro +mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX = 1 # macro +mmPA_CL_NGG_CNTL = 0x020e # macro +mmPA_CL_NGG_CNTL_BASE_IDX = 1 # macro +mmPA_SU_OVER_RASTERIZATION_CNTL = 0x020f # macro +mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX = 1 # macro +mmPA_STEREO_CNTL = 0x0210 # macro +mmPA_STEREO_CNTL_BASE_IDX = 1 # macro +mmPA_STATE_STEREO_X = 0x0211 # macro +mmPA_STATE_STEREO_X_BASE_IDX = 1 # macro +mmPA_CL_VRS_CNTL = 0x0212 # macro +mmPA_CL_VRS_CNTL_BASE_IDX = 1 # macro +mmPA_SU_POINT_SIZE = 0x0280 # macro +mmPA_SU_POINT_SIZE_BASE_IDX = 1 # macro +mmPA_SU_POINT_MINMAX = 0x0281 # macro +mmPA_SU_POINT_MINMAX_BASE_IDX = 1 # macro +mmPA_SU_LINE_CNTL = 0x0282 # macro +mmPA_SU_LINE_CNTL_BASE_IDX = 1 # macro +mmPA_SC_LINE_STIPPLE = 0x0283 # macro +mmPA_SC_LINE_STIPPLE_BASE_IDX = 1 # macro +mmVGT_OUTPUT_PATH_CNTL = 0x0284 # macro +mmVGT_OUTPUT_PATH_CNTL_BASE_IDX = 1 # macro +mmVGT_HOS_CNTL = 0x0285 # macro +mmVGT_HOS_CNTL_BASE_IDX = 1 # macro +mmVGT_HOS_MAX_TESS_LEVEL = 0x0286 # macro +mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX = 1 # macro +mmVGT_HOS_MIN_TESS_LEVEL = 0x0287 # macro +mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX = 1 # macro +mmVGT_HOS_REUSE_DEPTH = 0x0288 # macro +mmVGT_HOS_REUSE_DEPTH_BASE_IDX = 1 # macro +mmVGT_GROUP_PRIM_TYPE = 0x0289 # macro +mmVGT_GROUP_PRIM_TYPE_BASE_IDX = 1 # macro +mmVGT_GROUP_FIRST_DECR = 0x028a # macro +mmVGT_GROUP_FIRST_DECR_BASE_IDX = 1 # macro +mmVGT_GROUP_DECR = 0x028b # macro +mmVGT_GROUP_DECR_BASE_IDX = 1 # macro +mmVGT_GROUP_VECT_0_CNTL = 0x028c # macro +mmVGT_GROUP_VECT_0_CNTL_BASE_IDX = 1 # macro +mmVGT_GROUP_VECT_1_CNTL = 0x028d # macro +mmVGT_GROUP_VECT_1_CNTL_BASE_IDX = 1 # macro +mmVGT_GROUP_VECT_0_FMT_CNTL = 0x028e # macro +mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX = 1 # macro +mmVGT_GROUP_VECT_1_FMT_CNTL = 0x028f # macro +mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX = 1 # macro +mmVGT_GS_MODE = 0x0290 # macro +mmVGT_GS_MODE_BASE_IDX = 1 # macro +mmVGT_GS_ONCHIP_CNTL = 0x0291 # macro +mmVGT_GS_ONCHIP_CNTL_BASE_IDX = 1 # macro +mmPA_SC_MODE_CNTL_0 = 0x0292 # macro +mmPA_SC_MODE_CNTL_0_BASE_IDX = 1 # macro +mmPA_SC_MODE_CNTL_1 = 0x0293 # macro +mmPA_SC_MODE_CNTL_1_BASE_IDX = 1 # macro +mmVGT_ENHANCE = 0x0294 # macro +mmVGT_ENHANCE_BASE_IDX = 1 # macro +mmVGT_GS_PER_ES = 0x0295 # macro +mmVGT_GS_PER_ES_BASE_IDX = 1 # macro +mmVGT_ES_PER_GS = 0x0296 # macro +mmVGT_ES_PER_GS_BASE_IDX = 1 # macro +mmVGT_GS_PER_VS = 0x0297 # macro +mmVGT_GS_PER_VS_BASE_IDX = 1 # macro +mmVGT_GSVS_RING_OFFSET_1 = 0x0298 # macro +mmVGT_GSVS_RING_OFFSET_1_BASE_IDX = 1 # macro +mmVGT_GSVS_RING_OFFSET_2 = 0x0299 # macro +mmVGT_GSVS_RING_OFFSET_2_BASE_IDX = 1 # macro +mmVGT_GSVS_RING_OFFSET_3 = 0x029a # macro +mmVGT_GSVS_RING_OFFSET_3_BASE_IDX = 1 # macro +mmVGT_GS_OUT_PRIM_TYPE = 0x029b # macro +mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX = 1 # macro +mmIA_ENHANCE = 0x029c # macro +mmIA_ENHANCE_BASE_IDX = 1 # macro +mmVGT_DMA_SIZE = 0x029d # macro +mmVGT_DMA_SIZE_BASE_IDX = 1 # macro +mmVGT_DMA_MAX_SIZE = 0x029e # macro +mmVGT_DMA_MAX_SIZE_BASE_IDX = 1 # macro +mmVGT_DMA_INDEX_TYPE = 0x029f # macro +mmVGT_DMA_INDEX_TYPE_BASE_IDX = 1 # macro +mmWD_ENHANCE = 0x02a0 # macro +mmWD_ENHANCE_BASE_IDX = 1 # macro +mmVGT_PRIMITIVEID_EN = 0x02a1 # macro +mmVGT_PRIMITIVEID_EN_BASE_IDX = 1 # macro +mmVGT_DMA_NUM_INSTANCES = 0x02a2 # macro +mmVGT_DMA_NUM_INSTANCES_BASE_IDX = 1 # macro +mmVGT_PRIMITIVEID_RESET = 0x02a3 # macro +mmVGT_PRIMITIVEID_RESET_BASE_IDX = 1 # macro +mmVGT_EVENT_INITIATOR = 0x02a4 # macro +mmVGT_EVENT_INITIATOR_BASE_IDX = 1 # macro +mmVGT_MULTI_PRIM_IB_RESET_EN = 0x02a5 # macro +mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 # macro +mmVGT_DRAW_PAYLOAD_CNTL = 0x02a6 # macro +mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX = 1 # macro +mmVGT_INSTANCE_STEP_RATE_0 = 0x02a8 # macro +mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX = 1 # macro +mmVGT_INSTANCE_STEP_RATE_1 = 0x02a9 # macro +mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX = 1 # macro +mmIA_MULTI_VGT_PARAM = 0x02aa # macro +mmIA_MULTI_VGT_PARAM_BASE_IDX = 1 # macro +mmVGT_ESGS_RING_ITEMSIZE = 0x02ab # macro +mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX = 1 # macro +mmVGT_GSVS_RING_ITEMSIZE = 0x02ac # macro +mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX = 1 # macro +mmVGT_REUSE_OFF = 0x02ad # macro +mmVGT_REUSE_OFF_BASE_IDX = 1 # macro +mmVGT_VTX_CNT_EN = 0x02ae # macro +mmVGT_VTX_CNT_EN_BASE_IDX = 1 # macro +mmDB_HTILE_SURFACE = 0x02af # macro +mmDB_HTILE_SURFACE_BASE_IDX = 1 # macro +mmDB_SRESULTS_COMPARE_STATE0 = 0x02b0 # macro +mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX = 1 # macro +mmDB_SRESULTS_COMPARE_STATE1 = 0x02b1 # macro +mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX = 1 # macro +mmDB_PRELOAD_CONTROL = 0x02b2 # macro +mmDB_PRELOAD_CONTROL_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_SIZE_0 = 0x02b4 # macro +mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX = 1 # macro +mmVGT_STRMOUT_VTX_STRIDE_0 = 0x02b5 # macro +mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_OFFSET_0 = 0x02b7 # macro +mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_SIZE_1 = 0x02b8 # macro +mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX = 1 # macro +mmVGT_STRMOUT_VTX_STRIDE_1 = 0x02b9 # macro +mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_OFFSET_1 = 0x02bb # macro +mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_SIZE_2 = 0x02bc # macro +mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX = 1 # macro +mmVGT_STRMOUT_VTX_STRIDE_2 = 0x02bd # macro +mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_OFFSET_2 = 0x02bf # macro +mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_SIZE_3 = 0x02c0 # macro +mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX = 1 # macro +mmVGT_STRMOUT_VTX_STRIDE_3 = 0x02c1 # macro +mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_OFFSET_3 = 0x02c3 # macro +mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX = 1 # macro +mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x02ca # macro +mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX = 1 # macro +mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x02cb # macro +mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX = 1 # macro +mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x02cc # macro +mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX = 1 # macro +mmVGT_GS_MAX_VERT_OUT = 0x02ce # macro +mmVGT_GS_MAX_VERT_OUT_BASE_IDX = 1 # macro +mmGE_NGG_SUBGRP_CNTL = 0x02d3 # macro +mmGE_NGG_SUBGRP_CNTL_BASE_IDX = 1 # macro +mmVGT_TESS_DISTRIBUTION = 0x02d4 # macro +mmVGT_TESS_DISTRIBUTION_BASE_IDX = 1 # macro +mmVGT_SHADER_STAGES_EN = 0x02d5 # macro +mmVGT_SHADER_STAGES_EN_BASE_IDX = 1 # macro +mmVGT_LS_HS_CONFIG = 0x02d6 # macro +mmVGT_LS_HS_CONFIG_BASE_IDX = 1 # macro +mmVGT_GS_VERT_ITEMSIZE = 0x02d7 # macro +mmVGT_GS_VERT_ITEMSIZE_BASE_IDX = 1 # macro +mmVGT_GS_VERT_ITEMSIZE_1 = 0x02d8 # macro +mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX = 1 # macro +mmVGT_GS_VERT_ITEMSIZE_2 = 0x02d9 # macro +mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX = 1 # macro +mmVGT_GS_VERT_ITEMSIZE_3 = 0x02da # macro +mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX = 1 # macro +mmVGT_TF_PARAM = 0x02db # macro +mmVGT_TF_PARAM_BASE_IDX = 1 # macro +mmDB_ALPHA_TO_MASK = 0x02dc # macro +mmDB_ALPHA_TO_MASK_BASE_IDX = 1 # macro +mmVGT_DISPATCH_DRAW_INDEX = 0x02dd # macro +mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX = 1 # macro +mmPA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x02de # macro +mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX = 1 # macro +mmPA_SU_POLY_OFFSET_CLAMP = 0x02df # macro +mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX = 1 # macro +mmPA_SU_POLY_OFFSET_FRONT_SCALE = 0x02e0 # macro +mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX = 1 # macro +mmPA_SU_POLY_OFFSET_FRONT_OFFSET = 0x02e1 # macro +mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX = 1 # macro +mmPA_SU_POLY_OFFSET_BACK_SCALE = 0x02e2 # macro +mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX = 1 # macro +mmPA_SU_POLY_OFFSET_BACK_OFFSET = 0x02e3 # macro +mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX = 1 # macro +mmVGT_GS_INSTANCE_CNT = 0x02e4 # macro +mmVGT_GS_INSTANCE_CNT_BASE_IDX = 1 # macro +mmVGT_STRMOUT_CONFIG = 0x02e5 # macro +mmVGT_STRMOUT_CONFIG_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_CONFIG = 0x02e6 # macro +mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX = 1 # macro +mmVGT_DMA_EVENT_INITIATOR = 0x02e7 # macro +mmVGT_DMA_EVENT_INITIATOR_BASE_IDX = 1 # macro +mmPA_SC_CENTROID_PRIORITY_0 = 0x02f5 # macro +mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX = 1 # macro +mmPA_SC_CENTROID_PRIORITY_1 = 0x02f6 # macro +mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX = 1 # macro +mmPA_SC_LINE_CNTL = 0x02f7 # macro +mmPA_SC_LINE_CNTL_BASE_IDX = 1 # macro +mmPA_SC_AA_CONFIG = 0x02f8 # macro +mmPA_SC_AA_CONFIG_BASE_IDX = 1 # macro +mmPA_SU_VTX_CNTL = 0x02f9 # macro +mmPA_SU_VTX_CNTL_BASE_IDX = 1 # macro +mmPA_CL_GB_VERT_CLIP_ADJ = 0x02fa # macro +mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX = 1 # macro +mmPA_CL_GB_VERT_DISC_ADJ = 0x02fb # macro +mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX = 1 # macro +mmPA_CL_GB_HORZ_CLIP_ADJ = 0x02fc # macro +mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX = 1 # macro +mmPA_CL_GB_HORZ_DISC_ADJ = 0x02fd # macro +mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x02fe # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0x02ff # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0x0300 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0x0301 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0x0302 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0x0303 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0x0304 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0x0305 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0x0306 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0x0307 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0x0308 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0x0309 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0x030a # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0x030b # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0x030c # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX = 1 # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0x030d # macro +mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX = 1 # macro +mmPA_SC_AA_MASK_X0Y0_X1Y0 = 0x030e # macro +mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX = 1 # macro +mmPA_SC_AA_MASK_X0Y1_X1Y1 = 0x030f # macro +mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX = 1 # macro +mmPA_SC_SHADER_CONTROL = 0x0310 # macro +mmPA_SC_SHADER_CONTROL_BASE_IDX = 1 # macro +mmPA_SC_BINNER_CNTL_0 = 0x0311 # macro +mmPA_SC_BINNER_CNTL_0_BASE_IDX = 1 # macro +mmPA_SC_BINNER_CNTL_1 = 0x0312 # macro +mmPA_SC_BINNER_CNTL_1_BASE_IDX = 1 # macro +mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x0313 # macro +mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX = 1 # macro +mmPA_SC_NGG_MODE_CNTL = 0x0314 # macro +mmPA_SC_NGG_MODE_CNTL_BASE_IDX = 1 # macro +mmVGT_VERTEX_REUSE_BLOCK_CNTL = 0x0316 # macro +mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX = 1 # macro +mmVGT_OUT_DEALLOC_CNTL = 0x0317 # macro +mmVGT_OUT_DEALLOC_CNTL_BASE_IDX = 1 # macro +mmCB_COLOR0_BASE = 0x0318 # macro +mmCB_COLOR0_BASE_BASE_IDX = 1 # macro +mmCB_COLOR0_PITCH = 0x0319 # macro +mmCB_COLOR0_PITCH_BASE_IDX = 1 # macro +mmCB_COLOR0_SLICE = 0x031a # macro +mmCB_COLOR0_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR0_VIEW = 0x031b # macro +mmCB_COLOR0_VIEW_BASE_IDX = 1 # macro +mmCB_COLOR0_INFO = 0x031c # macro +mmCB_COLOR0_INFO_BASE_IDX = 1 # macro +mmCB_COLOR0_ATTRIB = 0x031d # macro +mmCB_COLOR0_ATTRIB_BASE_IDX = 1 # macro +mmCB_COLOR0_DCC_CONTROL = 0x031e # macro +mmCB_COLOR0_DCC_CONTROL_BASE_IDX = 1 # macro +mmCB_COLOR0_CMASK = 0x031f # macro +mmCB_COLOR0_CMASK_BASE_IDX = 1 # macro +mmCB_COLOR0_CMASK_SLICE = 0x0320 # macro +mmCB_COLOR0_CMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR0_FMASK = 0x0321 # macro +mmCB_COLOR0_FMASK_BASE_IDX = 1 # macro +mmCB_COLOR0_FMASK_SLICE = 0x0322 # macro +mmCB_COLOR0_FMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR0_CLEAR_WORD0 = 0x0323 # macro +mmCB_COLOR0_CLEAR_WORD0_BASE_IDX = 1 # macro +mmCB_COLOR0_CLEAR_WORD1 = 0x0324 # macro +mmCB_COLOR0_CLEAR_WORD1_BASE_IDX = 1 # macro +mmCB_COLOR0_DCC_BASE = 0x0325 # macro +mmCB_COLOR0_DCC_BASE_BASE_IDX = 1 # macro +mmCB_COLOR1_BASE = 0x0327 # macro +mmCB_COLOR1_BASE_BASE_IDX = 1 # macro +mmCB_COLOR1_PITCH = 0x0328 # macro +mmCB_COLOR1_PITCH_BASE_IDX = 1 # macro +mmCB_COLOR1_SLICE = 0x0329 # macro +mmCB_COLOR1_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR1_VIEW = 0x032a # macro +mmCB_COLOR1_VIEW_BASE_IDX = 1 # macro +mmCB_COLOR1_INFO = 0x032b # macro +mmCB_COLOR1_INFO_BASE_IDX = 1 # macro +mmCB_COLOR1_ATTRIB = 0x032c # macro +mmCB_COLOR1_ATTRIB_BASE_IDX = 1 # macro +mmCB_COLOR1_DCC_CONTROL = 0x032d # macro +mmCB_COLOR1_DCC_CONTROL_BASE_IDX = 1 # macro +mmCB_COLOR1_CMASK = 0x032e # macro +mmCB_COLOR1_CMASK_BASE_IDX = 1 # macro +mmCB_COLOR1_CMASK_SLICE = 0x032f # macro +mmCB_COLOR1_CMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR1_FMASK = 0x0330 # macro +mmCB_COLOR1_FMASK_BASE_IDX = 1 # macro +mmCB_COLOR1_FMASK_SLICE = 0x0331 # macro +mmCB_COLOR1_FMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR1_CLEAR_WORD0 = 0x0332 # macro +mmCB_COLOR1_CLEAR_WORD0_BASE_IDX = 1 # macro +mmCB_COLOR1_CLEAR_WORD1 = 0x0333 # macro +mmCB_COLOR1_CLEAR_WORD1_BASE_IDX = 1 # macro +mmCB_COLOR1_DCC_BASE = 0x0334 # macro +mmCB_COLOR1_DCC_BASE_BASE_IDX = 1 # macro +mmCB_COLOR2_BASE = 0x0336 # macro +mmCB_COLOR2_BASE_BASE_IDX = 1 # macro +mmCB_COLOR2_PITCH = 0x0337 # macro +mmCB_COLOR2_PITCH_BASE_IDX = 1 # macro +mmCB_COLOR2_SLICE = 0x0338 # macro +mmCB_COLOR2_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR2_VIEW = 0x0339 # macro +mmCB_COLOR2_VIEW_BASE_IDX = 1 # macro +mmCB_COLOR2_INFO = 0x033a # macro +mmCB_COLOR2_INFO_BASE_IDX = 1 # macro +mmCB_COLOR2_ATTRIB = 0x033b # macro +mmCB_COLOR2_ATTRIB_BASE_IDX = 1 # macro +mmCB_COLOR2_DCC_CONTROL = 0x033c # macro +mmCB_COLOR2_DCC_CONTROL_BASE_IDX = 1 # macro +mmCB_COLOR2_CMASK = 0x033d # macro +mmCB_COLOR2_CMASK_BASE_IDX = 1 # macro +mmCB_COLOR2_CMASK_SLICE = 0x033e # macro +mmCB_COLOR2_CMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR2_FMASK = 0x033f # macro +mmCB_COLOR2_FMASK_BASE_IDX = 1 # macro +mmCB_COLOR2_FMASK_SLICE = 0x0340 # macro +mmCB_COLOR2_FMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR2_CLEAR_WORD0 = 0x0341 # macro +mmCB_COLOR2_CLEAR_WORD0_BASE_IDX = 1 # macro +mmCB_COLOR2_CLEAR_WORD1 = 0x0342 # macro +mmCB_COLOR2_CLEAR_WORD1_BASE_IDX = 1 # macro +mmCB_COLOR2_DCC_BASE = 0x0343 # macro +mmCB_COLOR2_DCC_BASE_BASE_IDX = 1 # macro +mmCB_COLOR3_BASE = 0x0345 # macro +mmCB_COLOR3_BASE_BASE_IDX = 1 # macro +mmCB_COLOR3_PITCH = 0x0346 # macro +mmCB_COLOR3_PITCH_BASE_IDX = 1 # macro +mmCB_COLOR3_SLICE = 0x0347 # macro +mmCB_COLOR3_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR3_VIEW = 0x0348 # macro +mmCB_COLOR3_VIEW_BASE_IDX = 1 # macro +mmCB_COLOR3_INFO = 0x0349 # macro +mmCB_COLOR3_INFO_BASE_IDX = 1 # macro +mmCB_COLOR3_ATTRIB = 0x034a # macro +mmCB_COLOR3_ATTRIB_BASE_IDX = 1 # macro +mmCB_COLOR3_DCC_CONTROL = 0x034b # macro +mmCB_COLOR3_DCC_CONTROL_BASE_IDX = 1 # macro +mmCB_COLOR3_CMASK = 0x034c # macro +mmCB_COLOR3_CMASK_BASE_IDX = 1 # macro +mmCB_COLOR3_CMASK_SLICE = 0x034d # macro +mmCB_COLOR3_CMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR3_FMASK = 0x034e # macro +mmCB_COLOR3_FMASK_BASE_IDX = 1 # macro +mmCB_COLOR3_FMASK_SLICE = 0x034f # macro +mmCB_COLOR3_FMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR3_CLEAR_WORD0 = 0x0350 # macro +mmCB_COLOR3_CLEAR_WORD0_BASE_IDX = 1 # macro +mmCB_COLOR3_CLEAR_WORD1 = 0x0351 # macro +mmCB_COLOR3_CLEAR_WORD1_BASE_IDX = 1 # macro +mmCB_COLOR3_DCC_BASE = 0x0352 # macro +mmCB_COLOR3_DCC_BASE_BASE_IDX = 1 # macro +mmCB_COLOR4_BASE = 0x0354 # macro +mmCB_COLOR4_BASE_BASE_IDX = 1 # macro +mmCB_COLOR4_PITCH = 0x0355 # macro +mmCB_COLOR4_PITCH_BASE_IDX = 1 # macro +mmCB_COLOR4_SLICE = 0x0356 # macro +mmCB_COLOR4_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR4_VIEW = 0x0357 # macro +mmCB_COLOR4_VIEW_BASE_IDX = 1 # macro +mmCB_COLOR4_INFO = 0x0358 # macro +mmCB_COLOR4_INFO_BASE_IDX = 1 # macro +mmCB_COLOR4_ATTRIB = 0x0359 # macro +mmCB_COLOR4_ATTRIB_BASE_IDX = 1 # macro +mmCB_COLOR4_DCC_CONTROL = 0x035a # macro +mmCB_COLOR4_DCC_CONTROL_BASE_IDX = 1 # macro +mmCB_COLOR4_CMASK = 0x035b # macro +mmCB_COLOR4_CMASK_BASE_IDX = 1 # macro +mmCB_COLOR4_CMASK_SLICE = 0x035c # macro +mmCB_COLOR4_CMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR4_FMASK = 0x035d # macro +mmCB_COLOR4_FMASK_BASE_IDX = 1 # macro +mmCB_COLOR4_FMASK_SLICE = 0x035e # macro +mmCB_COLOR4_FMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR4_CLEAR_WORD0 = 0x035f # macro +mmCB_COLOR4_CLEAR_WORD0_BASE_IDX = 1 # macro +mmCB_COLOR4_CLEAR_WORD1 = 0x0360 # macro +mmCB_COLOR4_CLEAR_WORD1_BASE_IDX = 1 # macro +mmCB_COLOR4_DCC_BASE = 0x0361 # macro +mmCB_COLOR4_DCC_BASE_BASE_IDX = 1 # macro +mmCB_COLOR5_BASE = 0x0363 # macro +mmCB_COLOR5_BASE_BASE_IDX = 1 # macro +mmCB_COLOR5_PITCH = 0x0364 # macro +mmCB_COLOR5_PITCH_BASE_IDX = 1 # macro +mmCB_COLOR5_SLICE = 0x0365 # macro +mmCB_COLOR5_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR5_VIEW = 0x0366 # macro +mmCB_COLOR5_VIEW_BASE_IDX = 1 # macro +mmCB_COLOR5_INFO = 0x0367 # macro +mmCB_COLOR5_INFO_BASE_IDX = 1 # macro +mmCB_COLOR5_ATTRIB = 0x0368 # macro +mmCB_COLOR5_ATTRIB_BASE_IDX = 1 # macro +mmCB_COLOR5_DCC_CONTROL = 0x0369 # macro +mmCB_COLOR5_DCC_CONTROL_BASE_IDX = 1 # macro +mmCB_COLOR5_CMASK = 0x036a # macro +mmCB_COLOR5_CMASK_BASE_IDX = 1 # macro +mmCB_COLOR5_CMASK_SLICE = 0x036b # macro +mmCB_COLOR5_CMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR5_FMASK = 0x036c # macro +mmCB_COLOR5_FMASK_BASE_IDX = 1 # macro +mmCB_COLOR5_FMASK_SLICE = 0x036d # macro +mmCB_COLOR5_FMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR5_CLEAR_WORD0 = 0x036e # macro +mmCB_COLOR5_CLEAR_WORD0_BASE_IDX = 1 # macro +mmCB_COLOR5_CLEAR_WORD1 = 0x036f # macro +mmCB_COLOR5_CLEAR_WORD1_BASE_IDX = 1 # macro +mmCB_COLOR5_DCC_BASE = 0x0370 # macro +mmCB_COLOR5_DCC_BASE_BASE_IDX = 1 # macro +mmCB_COLOR6_BASE = 0x0372 # macro +mmCB_COLOR6_BASE_BASE_IDX = 1 # macro +mmCB_COLOR6_PITCH = 0x0373 # macro +mmCB_COLOR6_PITCH_BASE_IDX = 1 # macro +mmCB_COLOR6_SLICE = 0x0374 # macro +mmCB_COLOR6_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR6_VIEW = 0x0375 # macro +mmCB_COLOR6_VIEW_BASE_IDX = 1 # macro +mmCB_COLOR6_INFO = 0x0376 # macro +mmCB_COLOR6_INFO_BASE_IDX = 1 # macro +mmCB_COLOR6_ATTRIB = 0x0377 # macro +mmCB_COLOR6_ATTRIB_BASE_IDX = 1 # macro +mmCB_COLOR6_DCC_CONTROL = 0x0378 # macro +mmCB_COLOR6_DCC_CONTROL_BASE_IDX = 1 # macro +mmCB_COLOR6_CMASK = 0x0379 # macro +mmCB_COLOR6_CMASK_BASE_IDX = 1 # macro +mmCB_COLOR6_CMASK_SLICE = 0x037a # macro +mmCB_COLOR6_CMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR6_FMASK = 0x037b # macro +mmCB_COLOR6_FMASK_BASE_IDX = 1 # macro +mmCB_COLOR6_FMASK_SLICE = 0x037c # macro +mmCB_COLOR6_FMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR6_CLEAR_WORD0 = 0x037d # macro +mmCB_COLOR6_CLEAR_WORD0_BASE_IDX = 1 # macro +mmCB_COLOR6_CLEAR_WORD1 = 0x037e # macro +mmCB_COLOR6_CLEAR_WORD1_BASE_IDX = 1 # macro +mmCB_COLOR6_DCC_BASE = 0x037f # macro +mmCB_COLOR6_DCC_BASE_BASE_IDX = 1 # macro +mmCB_COLOR7_BASE = 0x0381 # macro +mmCB_COLOR7_BASE_BASE_IDX = 1 # macro +mmCB_COLOR7_PITCH = 0x0382 # macro +mmCB_COLOR7_PITCH_BASE_IDX = 1 # macro +mmCB_COLOR7_SLICE = 0x0383 # macro +mmCB_COLOR7_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR7_VIEW = 0x0384 # macro +mmCB_COLOR7_VIEW_BASE_IDX = 1 # macro +mmCB_COLOR7_INFO = 0x0385 # macro +mmCB_COLOR7_INFO_BASE_IDX = 1 # macro +mmCB_COLOR7_ATTRIB = 0x0386 # macro +mmCB_COLOR7_ATTRIB_BASE_IDX = 1 # macro +mmCB_COLOR7_DCC_CONTROL = 0x0387 # macro +mmCB_COLOR7_DCC_CONTROL_BASE_IDX = 1 # macro +mmCB_COLOR7_CMASK = 0x0388 # macro +mmCB_COLOR7_CMASK_BASE_IDX = 1 # macro +mmCB_COLOR7_CMASK_SLICE = 0x0389 # macro +mmCB_COLOR7_CMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR7_FMASK = 0x038a # macro +mmCB_COLOR7_FMASK_BASE_IDX = 1 # macro +mmCB_COLOR7_FMASK_SLICE = 0x038b # macro +mmCB_COLOR7_FMASK_SLICE_BASE_IDX = 1 # macro +mmCB_COLOR7_CLEAR_WORD0 = 0x038c # macro +mmCB_COLOR7_CLEAR_WORD0_BASE_IDX = 1 # macro +mmCB_COLOR7_CLEAR_WORD1 = 0x038d # macro +mmCB_COLOR7_CLEAR_WORD1_BASE_IDX = 1 # macro +mmCB_COLOR7_DCC_BASE = 0x038e # macro +mmCB_COLOR7_DCC_BASE_BASE_IDX = 1 # macro +mmCB_COLOR0_BASE_EXT = 0x0390 # macro +mmCB_COLOR0_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR1_BASE_EXT = 0x0391 # macro +mmCB_COLOR1_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR2_BASE_EXT = 0x0392 # macro +mmCB_COLOR2_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR3_BASE_EXT = 0x0393 # macro +mmCB_COLOR3_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR4_BASE_EXT = 0x0394 # macro +mmCB_COLOR4_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR5_BASE_EXT = 0x0395 # macro +mmCB_COLOR5_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR6_BASE_EXT = 0x0396 # macro +mmCB_COLOR6_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR7_BASE_EXT = 0x0397 # macro +mmCB_COLOR7_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR0_CMASK_BASE_EXT = 0x0398 # macro +mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR1_CMASK_BASE_EXT = 0x0399 # macro +mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR2_CMASK_BASE_EXT = 0x039a # macro +mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR3_CMASK_BASE_EXT = 0x039b # macro +mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR4_CMASK_BASE_EXT = 0x039c # macro +mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR5_CMASK_BASE_EXT = 0x039d # macro +mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR6_CMASK_BASE_EXT = 0x039e # macro +mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR7_CMASK_BASE_EXT = 0x039f # macro +mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR0_FMASK_BASE_EXT = 0x03a0 # macro +mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR1_FMASK_BASE_EXT = 0x03a1 # macro +mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR2_FMASK_BASE_EXT = 0x03a2 # macro +mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR3_FMASK_BASE_EXT = 0x03a3 # macro +mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR4_FMASK_BASE_EXT = 0x03a4 # macro +mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR5_FMASK_BASE_EXT = 0x03a5 # macro +mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR6_FMASK_BASE_EXT = 0x03a6 # macro +mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR7_FMASK_BASE_EXT = 0x03a7 # macro +mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR0_DCC_BASE_EXT = 0x03a8 # macro +mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR1_DCC_BASE_EXT = 0x03a9 # macro +mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR2_DCC_BASE_EXT = 0x03aa # macro +mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR3_DCC_BASE_EXT = 0x03ab # macro +mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR4_DCC_BASE_EXT = 0x03ac # macro +mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR5_DCC_BASE_EXT = 0x03ad # macro +mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR6_DCC_BASE_EXT = 0x03ae # macro +mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR7_DCC_BASE_EXT = 0x03af # macro +mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX = 1 # macro +mmCB_COLOR0_ATTRIB2 = 0x03b0 # macro +mmCB_COLOR0_ATTRIB2_BASE_IDX = 1 # macro +mmCB_COLOR1_ATTRIB2 = 0x03b1 # macro +mmCB_COLOR1_ATTRIB2_BASE_IDX = 1 # macro +mmCB_COLOR2_ATTRIB2 = 0x03b2 # macro +mmCB_COLOR2_ATTRIB2_BASE_IDX = 1 # macro +mmCB_COLOR3_ATTRIB2 = 0x03b3 # macro +mmCB_COLOR3_ATTRIB2_BASE_IDX = 1 # macro +mmCB_COLOR4_ATTRIB2 = 0x03b4 # macro +mmCB_COLOR4_ATTRIB2_BASE_IDX = 1 # macro +mmCB_COLOR5_ATTRIB2 = 0x03b5 # macro +mmCB_COLOR5_ATTRIB2_BASE_IDX = 1 # macro +mmCB_COLOR6_ATTRIB2 = 0x03b6 # macro +mmCB_COLOR6_ATTRIB2_BASE_IDX = 1 # macro +mmCB_COLOR7_ATTRIB2 = 0x03b7 # macro +mmCB_COLOR7_ATTRIB2_BASE_IDX = 1 # macro +mmCB_COLOR0_ATTRIB3 = 0x03b8 # macro +mmCB_COLOR0_ATTRIB3_BASE_IDX = 1 # macro +mmCB_COLOR1_ATTRIB3 = 0x03b9 # macro +mmCB_COLOR1_ATTRIB3_BASE_IDX = 1 # macro +mmCB_COLOR2_ATTRIB3 = 0x03ba # macro +mmCB_COLOR2_ATTRIB3_BASE_IDX = 1 # macro +mmCB_COLOR3_ATTRIB3 = 0x03bb # macro +mmCB_COLOR3_ATTRIB3_BASE_IDX = 1 # macro +mmCB_COLOR4_ATTRIB3 = 0x03bc # macro +mmCB_COLOR4_ATTRIB3_BASE_IDX = 1 # macro +mmCB_COLOR5_ATTRIB3 = 0x03bd # macro +mmCB_COLOR5_ATTRIB3_BASE_IDX = 1 # macro +mmCB_COLOR6_ATTRIB3 = 0x03be # macro +mmCB_COLOR6_ATTRIB3_BASE_IDX = 1 # macro +mmCB_COLOR7_ATTRIB3 = 0x03bf # macro +mmCB_COLOR7_ATTRIB3_BASE_IDX = 1 # macro +mmCP_EOP_DONE_ADDR_LO = 0x2000 # macro +mmCP_EOP_DONE_ADDR_LO_BASE_IDX = 1 # macro +mmCP_EOP_DONE_ADDR_HI = 0x2001 # macro +mmCP_EOP_DONE_ADDR_HI_BASE_IDX = 1 # macro +mmCP_EOP_DONE_DATA_LO = 0x2002 # macro +mmCP_EOP_DONE_DATA_LO_BASE_IDX = 1 # macro +mmCP_EOP_DONE_DATA_HI = 0x2003 # macro +mmCP_EOP_DONE_DATA_HI_BASE_IDX = 1 # macro +mmCP_EOP_LAST_FENCE_LO = 0x2004 # macro +mmCP_EOP_LAST_FENCE_LO_BASE_IDX = 1 # macro +mmCP_EOP_LAST_FENCE_HI = 0x2005 # macro +mmCP_EOP_LAST_FENCE_HI_BASE_IDX = 1 # macro +mmCP_STREAM_OUT_ADDR_LO = 0x2006 # macro +mmCP_STREAM_OUT_ADDR_LO_BASE_IDX = 1 # macro +mmCP_STREAM_OUT_ADDR_HI = 0x2007 # macro +mmCP_STREAM_OUT_ADDR_HI_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT0_LO = 0x2008 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT0_HI = 0x2009 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_NEEDED_COUNT0_LO = 0x200a # macro +mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_NEEDED_COUNT0_HI = 0x200b # macro +mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT1_LO = 0x200c # macro +mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT1_HI = 0x200d # macro +mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_NEEDED_COUNT1_LO = 0x200e # macro +mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_NEEDED_COUNT1_HI = 0x200f # macro +mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT2_LO = 0x2010 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT2_HI = 0x2011 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_NEEDED_COUNT2_LO = 0x2012 # macro +mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_NEEDED_COUNT2_HI = 0x2013 # macro +mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT3_LO = 0x2014 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT3_HI = 0x2015 # macro +mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_NEEDED_COUNT3_LO = 0x2016 # macro +mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX = 1 # macro +mmCP_NUM_PRIM_NEEDED_COUNT3_HI = 0x2017 # macro +mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX = 1 # macro +mmCP_PIPE_STATS_ADDR_LO = 0x2018 # macro +mmCP_PIPE_STATS_ADDR_LO_BASE_IDX = 1 # macro +mmCP_PIPE_STATS_ADDR_HI = 0x2019 # macro +mmCP_PIPE_STATS_ADDR_HI_BASE_IDX = 1 # macro +mmCP_VGT_IAVERT_COUNT_LO = 0x201a # macro +mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX = 1 # macro +mmCP_VGT_IAVERT_COUNT_HI = 0x201b # macro +mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX = 1 # macro +mmCP_VGT_IAPRIM_COUNT_LO = 0x201c # macro +mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX = 1 # macro +mmCP_VGT_IAPRIM_COUNT_HI = 0x201d # macro +mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX = 1 # macro +mmCP_VGT_GSPRIM_COUNT_LO = 0x201e # macro +mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX = 1 # macro +mmCP_VGT_GSPRIM_COUNT_HI = 0x201f # macro +mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX = 1 # macro +mmCP_VGT_VSINVOC_COUNT_LO = 0x2020 # macro +mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX = 1 # macro +mmCP_VGT_VSINVOC_COUNT_HI = 0x2021 # macro +mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX = 1 # macro +mmCP_VGT_GSINVOC_COUNT_LO = 0x2022 # macro +mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX = 1 # macro +mmCP_VGT_GSINVOC_COUNT_HI = 0x2023 # macro +mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX = 1 # macro +mmCP_VGT_HSINVOC_COUNT_LO = 0x2024 # macro +mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX = 1 # macro +mmCP_VGT_HSINVOC_COUNT_HI = 0x2025 # macro +mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX = 1 # macro +mmCP_VGT_DSINVOC_COUNT_LO = 0x2026 # macro +mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX = 1 # macro +mmCP_VGT_DSINVOC_COUNT_HI = 0x2027 # macro +mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX = 1 # macro +mmCP_PA_CINVOC_COUNT_LO = 0x2028 # macro +mmCP_PA_CINVOC_COUNT_LO_BASE_IDX = 1 # macro +mmCP_PA_CINVOC_COUNT_HI = 0x2029 # macro +mmCP_PA_CINVOC_COUNT_HI_BASE_IDX = 1 # macro +mmCP_PA_CPRIM_COUNT_LO = 0x202a # macro +mmCP_PA_CPRIM_COUNT_LO_BASE_IDX = 1 # macro +mmCP_PA_CPRIM_COUNT_HI = 0x202b # macro +mmCP_PA_CPRIM_COUNT_HI_BASE_IDX = 1 # macro +mmCP_SC_PSINVOC_COUNT0_LO = 0x202c # macro +mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX = 1 # macro +mmCP_SC_PSINVOC_COUNT0_HI = 0x202d # macro +mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX = 1 # macro +mmCP_SC_PSINVOC_COUNT1_LO = 0x202e # macro +mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX = 1 # macro +mmCP_SC_PSINVOC_COUNT1_HI = 0x202f # macro +mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX = 1 # macro +mmCP_VGT_CSINVOC_COUNT_LO = 0x2030 # macro +mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX = 1 # macro +mmCP_VGT_CSINVOC_COUNT_HI = 0x2031 # macro +mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX = 1 # macro +mmCP_PIPE_STATS_CONTROL = 0x203d # macro +mmCP_PIPE_STATS_CONTROL_BASE_IDX = 1 # macro +mmCP_STREAM_OUT_CONTROL = 0x203e # macro +mmCP_STREAM_OUT_CONTROL_BASE_IDX = 1 # macro +mmCP_STRMOUT_CNTL = 0x203f # macro +mmCP_STRMOUT_CNTL_BASE_IDX = 1 # macro +mmSCRATCH_REG0 = 0x2040 # macro +mmSCRATCH_REG0_BASE_IDX = 1 # macro +mmSCRATCH_REG1 = 0x2041 # macro +mmSCRATCH_REG1_BASE_IDX = 1 # macro +mmSCRATCH_REG2 = 0x2042 # macro +mmSCRATCH_REG2_BASE_IDX = 1 # macro +mmSCRATCH_REG3 = 0x2043 # macro +mmSCRATCH_REG3_BASE_IDX = 1 # macro +mmSCRATCH_REG4 = 0x2044 # macro +mmSCRATCH_REG4_BASE_IDX = 1 # macro +mmSCRATCH_REG5 = 0x2045 # macro +mmSCRATCH_REG5_BASE_IDX = 1 # macro +mmSCRATCH_REG6 = 0x2046 # macro +mmSCRATCH_REG6_BASE_IDX = 1 # macro +mmSCRATCH_REG7 = 0x2047 # macro +mmSCRATCH_REG7_BASE_IDX = 1 # macro +mmSCRATCH_REG_ATOMIC = 0x2048 # macro +mmSCRATCH_REG_ATOMIC_BASE_IDX = 1 # macro +mmSCRATCH_REG_CMPSWAP_ATOMIC = 0x2048 # macro +mmSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX = 1 # macro +mmCP_APPEND_DDID_CNT = 0x204b # macro +mmCP_APPEND_DDID_CNT_BASE_IDX = 1 # macro +mmCP_APPEND_DATA_HI = 0x204c # macro +mmCP_APPEND_DATA_HI_BASE_IDX = 1 # macro +mmCP_APPEND_LAST_CS_FENCE_HI = 0x204d # macro +mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX = 1 # macro +mmCP_APPEND_LAST_PS_FENCE_HI = 0x204e # macro +mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX = 1 # macro +mmSCRATCH_UMSK = 0x2050 # macro +mmSCRATCH_UMSK_BASE_IDX = 1 # macro +mmSCRATCH_ADDR = 0x2051 # macro +mmSCRATCH_ADDR_BASE_IDX = 1 # macro +mmCP_PFP_ATOMIC_PREOP_LO = 0x2052 # macro +mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro +mmCP_PFP_ATOMIC_PREOP_HI = 0x2053 # macro +mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro +mmCP_PFP_GDS_ATOMIC0_PREOP_LO = 0x2054 # macro +mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro +mmCP_PFP_GDS_ATOMIC0_PREOP_HI = 0x2055 # macro +mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro +mmCP_PFP_GDS_ATOMIC1_PREOP_LO = 0x2056 # macro +mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro +mmCP_PFP_GDS_ATOMIC1_PREOP_HI = 0x2057 # macro +mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro +mmCP_APPEND_ADDR_LO = 0x2058 # macro +mmCP_APPEND_ADDR_LO_BASE_IDX = 1 # macro +mmCP_APPEND_ADDR_HI = 0x2059 # macro +mmCP_APPEND_ADDR_HI_BASE_IDX = 1 # macro +mmCP_APPEND_DATA = 0x205a # macro +mmCP_APPEND_DATA_BASE_IDX = 1 # macro +mmCP_APPEND_DATA_LO = 0x205a # macro +mmCP_APPEND_DATA_LO_BASE_IDX = 1 # macro +mmCP_APPEND_LAST_CS_FENCE = 0x205b # macro +mmCP_APPEND_LAST_CS_FENCE_BASE_IDX = 1 # macro +mmCP_APPEND_LAST_CS_FENCE_LO = 0x205b # macro +mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX = 1 # macro +mmCP_APPEND_LAST_PS_FENCE = 0x205c # macro +mmCP_APPEND_LAST_PS_FENCE_BASE_IDX = 1 # macro +mmCP_APPEND_LAST_PS_FENCE_LO = 0x205c # macro +mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX = 1 # macro +mmCP_ATOMIC_PREOP_LO = 0x205d # macro +mmCP_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro +mmCP_ME_ATOMIC_PREOP_LO = 0x205d # macro +mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro +mmCP_ATOMIC_PREOP_HI = 0x205e # macro +mmCP_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro +mmCP_ME_ATOMIC_PREOP_HI = 0x205e # macro +mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro +mmCP_GDS_ATOMIC0_PREOP_LO = 0x205f # macro +mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro +mmCP_ME_GDS_ATOMIC0_PREOP_LO = 0x205f # macro +mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro +mmCP_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro +mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro +mmCP_ME_GDS_ATOMIC0_PREOP_HI = 0x2060 # macro +mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro +mmCP_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro +mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro +mmCP_ME_GDS_ATOMIC1_PREOP_LO = 0x2061 # macro +mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro +mmCP_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro +mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro +mmCP_ME_GDS_ATOMIC1_PREOP_HI = 0x2062 # macro +mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro +mmCP_ME_MC_WADDR_LO = 0x2069 # macro +mmCP_ME_MC_WADDR_LO_BASE_IDX = 1 # macro +mmCP_ME_MC_WADDR_HI = 0x206a # macro +mmCP_ME_MC_WADDR_HI_BASE_IDX = 1 # macro +mmCP_ME_MC_WDATA_LO = 0x206b # macro +mmCP_ME_MC_WDATA_LO_BASE_IDX = 1 # macro +mmCP_ME_MC_WDATA_HI = 0x206c # macro +mmCP_ME_MC_WDATA_HI_BASE_IDX = 1 # macro +mmCP_ME_MC_RADDR_LO = 0x206d # macro +mmCP_ME_MC_RADDR_LO_BASE_IDX = 1 # macro +mmCP_ME_MC_RADDR_HI = 0x206e # macro +mmCP_ME_MC_RADDR_HI_BASE_IDX = 1 # macro +mmCP_SEM_WAIT_TIMER = 0x206f # macro +mmCP_SEM_WAIT_TIMER_BASE_IDX = 1 # macro +mmCP_SIG_SEM_ADDR_LO = 0x2070 # macro +mmCP_SIG_SEM_ADDR_LO_BASE_IDX = 1 # macro +mmCP_SIG_SEM_ADDR_HI = 0x2071 # macro +mmCP_SIG_SEM_ADDR_HI_BASE_IDX = 1 # macro +mmCP_WAIT_REG_MEM_TIMEOUT = 0x2074 # macro +mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX = 1 # macro +mmCP_WAIT_SEM_ADDR_LO = 0x2075 # macro +mmCP_WAIT_SEM_ADDR_LO_BASE_IDX = 1 # macro +mmCP_WAIT_SEM_ADDR_HI = 0x2076 # macro +mmCP_WAIT_SEM_ADDR_HI_BASE_IDX = 1 # macro +mmCP_DMA_PFP_CONTROL = 0x2077 # macro +mmCP_DMA_PFP_CONTROL_BASE_IDX = 1 # macro +mmCP_DMA_ME_CONTROL = 0x2078 # macro +mmCP_DMA_ME_CONTROL_BASE_IDX = 1 # macro +mmCP_COHER_BASE_HI = 0x2079 # macro +mmCP_COHER_BASE_HI_BASE_IDX = 1 # macro +mmCP_COHER_START_DELAY = 0x207b # macro +mmCP_COHER_START_DELAY_BASE_IDX = 1 # macro +mmCP_COHER_CNTL = 0x207c # macro +mmCP_COHER_CNTL_BASE_IDX = 1 # macro +mmCP_COHER_SIZE = 0x207d # macro +mmCP_COHER_SIZE_BASE_IDX = 1 # macro +mmCP_COHER_BASE = 0x207e # macro +mmCP_COHER_BASE_BASE_IDX = 1 # macro +mmCP_COHER_STATUS = 0x207f # macro +mmCP_COHER_STATUS_BASE_IDX = 1 # macro +mmCP_DMA_ME_SRC_ADDR = 0x2080 # macro +mmCP_DMA_ME_SRC_ADDR_BASE_IDX = 1 # macro +mmCP_DMA_ME_SRC_ADDR_HI = 0x2081 # macro +mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX = 1 # macro +mmCP_DMA_ME_DST_ADDR = 0x2082 # macro +mmCP_DMA_ME_DST_ADDR_BASE_IDX = 1 # macro +mmCP_DMA_ME_DST_ADDR_HI = 0x2083 # macro +mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX = 1 # macro +mmCP_DMA_ME_COMMAND = 0x2084 # macro +mmCP_DMA_ME_COMMAND_BASE_IDX = 1 # macro +mmCP_DMA_PFP_SRC_ADDR = 0x2085 # macro +mmCP_DMA_PFP_SRC_ADDR_BASE_IDX = 1 # macro +mmCP_DMA_PFP_SRC_ADDR_HI = 0x2086 # macro +mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX = 1 # macro +mmCP_DMA_PFP_DST_ADDR = 0x2087 # macro +mmCP_DMA_PFP_DST_ADDR_BASE_IDX = 1 # macro +mmCP_DMA_PFP_DST_ADDR_HI = 0x2088 # macro +mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX = 1 # macro +mmCP_DMA_PFP_COMMAND = 0x2089 # macro +mmCP_DMA_PFP_COMMAND_BASE_IDX = 1 # macro +mmCP_DMA_CNTL = 0x208a # macro +mmCP_DMA_CNTL_BASE_IDX = 1 # macro +mmCP_DMA_READ_TAGS = 0x208b # macro +mmCP_DMA_READ_TAGS_BASE_IDX = 1 # macro +mmCP_COHER_SIZE_HI = 0x208c # macro +mmCP_COHER_SIZE_HI_BASE_IDX = 1 # macro +mmCP_PFP_IB_CONTROL = 0x208d # macro +mmCP_PFP_IB_CONTROL_BASE_IDX = 1 # macro +mmCP_PFP_LOAD_CONTROL = 0x208e # macro +mmCP_PFP_LOAD_CONTROL_BASE_IDX = 1 # macro +mmCP_SCRATCH_INDEX = 0x208f # macro +mmCP_SCRATCH_INDEX_BASE_IDX = 1 # macro +mmCP_SCRATCH_DATA = 0x2090 # macro +mmCP_SCRATCH_DATA_BASE_IDX = 1 # macro +mmCP_RB_OFFSET = 0x2091 # macro +mmCP_RB_OFFSET_BASE_IDX = 1 # macro +mmCP_IB2_OFFSET = 0x2093 # macro +mmCP_IB2_OFFSET_BASE_IDX = 1 # macro +mmCP_IB2_PREAMBLE_BEGIN = 0x2096 # macro +mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX = 1 # macro +mmCP_IB2_PREAMBLE_END = 0x2097 # macro +mmCP_IB2_PREAMBLE_END_BASE_IDX = 1 # macro +mmCP_CE_IB1_OFFSET = 0x2098 # macro +mmCP_CE_IB1_OFFSET_BASE_IDX = 1 # macro +mmCP_CE_IB2_OFFSET = 0x2099 # macro +mmCP_CE_IB2_OFFSET_BASE_IDX = 1 # macro +mmCP_CE_COUNTER = 0x209a # macro +mmCP_CE_COUNTER_BASE_IDX = 1 # macro +mmCP_DMA_ME_CMD_ADDR_LO = 0x209c # macro +mmCP_DMA_ME_CMD_ADDR_LO_BASE_IDX = 1 # macro +mmCP_DMA_ME_CMD_ADDR_HI = 0x209d # macro +mmCP_DMA_ME_CMD_ADDR_HI_BASE_IDX = 1 # macro +mmCP_DMA_PFP_CMD_ADDR_LO = 0x209e # macro +mmCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX = 1 # macro +mmCP_DMA_PFP_CMD_ADDR_HI = 0x209f # macro +mmCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX = 1 # macro +mmCP_APPEND_CMD_ADDR_LO = 0x20a0 # macro +mmCP_APPEND_CMD_ADDR_LO_BASE_IDX = 1 # macro +mmCP_APPEND_CMD_ADDR_HI = 0x20a1 # macro +mmCP_APPEND_CMD_ADDR_HI_BASE_IDX = 1 # macro +mmUCONFIG_RESERVED_REG0 = 0x20a2 # macro +mmUCONFIG_RESERVED_REG0_BASE_IDX = 1 # macro +mmUCONFIG_RESERVED_REG1 = 0x20a3 # macro +mmUCONFIG_RESERVED_REG1_BASE_IDX = 1 # macro +mmCP_CE_ATOMIC_PREOP_LO = 0x20a8 # macro +mmCP_CE_ATOMIC_PREOP_LO_BASE_IDX = 1 # macro +mmCP_CE_ATOMIC_PREOP_HI = 0x20a9 # macro +mmCP_CE_ATOMIC_PREOP_HI_BASE_IDX = 1 # macro +mmCP_CE_GDS_ATOMIC0_PREOP_LO = 0x20aa # macro +mmCP_CE_GDS_ATOMIC0_PREOP_LO_BASE_IDX = 1 # macro +mmCP_CE_GDS_ATOMIC0_PREOP_HI = 0x20ab # macro +mmCP_CE_GDS_ATOMIC0_PREOP_HI_BASE_IDX = 1 # macro +mmCP_CE_GDS_ATOMIC1_PREOP_LO = 0x20ac # macro +mmCP_CE_GDS_ATOMIC1_PREOP_LO_BASE_IDX = 1 # macro +mmCP_CE_GDS_ATOMIC1_PREOP_HI = 0x20ad # macro +mmCP_CE_GDS_ATOMIC1_PREOP_HI_BASE_IDX = 1 # macro +mmCP_CE_INIT_CMD_BUFSZ = 0x20bd # macro +mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX = 1 # macro +mmCP_CE_IB1_CMD_BUFSZ = 0x20be # macro +mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX = 1 # macro +mmCP_CE_IB2_CMD_BUFSZ = 0x20bf # macro +mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro +mmCP_IB2_CMD_BUFSZ = 0x20c1 # macro +mmCP_IB2_CMD_BUFSZ_BASE_IDX = 1 # macro +mmCP_ST_CMD_BUFSZ = 0x20c2 # macro +mmCP_ST_CMD_BUFSZ_BASE_IDX = 1 # macro +mmCP_CE_INIT_BASE_LO = 0x20c3 # macro +mmCP_CE_INIT_BASE_LO_BASE_IDX = 1 # macro +mmCP_CE_INIT_BASE_HI = 0x20c4 # macro +mmCP_CE_INIT_BASE_HI_BASE_IDX = 1 # macro +mmCP_CE_INIT_BUFSZ = 0x20c5 # macro +mmCP_CE_INIT_BUFSZ_BASE_IDX = 1 # macro +mmCP_CE_IB1_BASE_LO = 0x20c6 # macro +mmCP_CE_IB1_BASE_LO_BASE_IDX = 1 # macro +mmCP_CE_IB1_BASE_HI = 0x20c7 # macro +mmCP_CE_IB1_BASE_HI_BASE_IDX = 1 # macro +mmCP_CE_IB1_BUFSZ = 0x20c8 # macro +mmCP_CE_IB1_BUFSZ_BASE_IDX = 1 # macro +mmCP_CE_IB2_BASE_LO = 0x20c9 # macro +mmCP_CE_IB2_BASE_LO_BASE_IDX = 1 # macro +mmCP_CE_IB2_BASE_HI = 0x20ca # macro +mmCP_CE_IB2_BASE_HI_BASE_IDX = 1 # macro +mmCP_CE_IB2_BUFSZ = 0x20cb # macro +mmCP_CE_IB2_BUFSZ_BASE_IDX = 1 # macro +mmCP_IB1_BASE_LO = 0x20cc # macro +mmCP_IB1_BASE_LO_BASE_IDX = 1 # macro +mmCP_IB1_BASE_HI = 0x20cd # macro +mmCP_IB1_BASE_HI_BASE_IDX = 1 # macro +mmCP_IB1_BUFSZ = 0x20ce # macro +mmCP_IB1_BUFSZ_BASE_IDX = 1 # macro +mmCP_IB2_BASE_LO = 0x20cf # macro +mmCP_IB2_BASE_LO_BASE_IDX = 1 # macro +mmCP_IB2_BASE_HI = 0x20d0 # macro +mmCP_IB2_BASE_HI_BASE_IDX = 1 # macro +mmCP_IB2_BUFSZ = 0x20d1 # macro +mmCP_IB2_BUFSZ_BASE_IDX = 1 # macro +mmCP_ST_BASE_LO = 0x20d2 # macro +mmCP_ST_BASE_LO_BASE_IDX = 1 # macro +mmCP_ST_BASE_HI = 0x20d3 # macro +mmCP_ST_BASE_HI_BASE_IDX = 1 # macro +mmCP_ST_BUFSZ = 0x20d4 # macro +mmCP_ST_BUFSZ_BASE_IDX = 1 # macro +mmCP_EOP_DONE_EVENT_CNTL = 0x20d5 # macro +mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX = 1 # macro +mmCP_EOP_DONE_DATA_CNTL = 0x20d6 # macro +mmCP_EOP_DONE_DATA_CNTL_BASE_IDX = 1 # macro +mmCP_EOP_DONE_CNTX_ID = 0x20d7 # macro +mmCP_EOP_DONE_CNTX_ID_BASE_IDX = 1 # macro +mmCP_DB_BASE_LO = 0x20d8 # macro +mmCP_DB_BASE_LO_BASE_IDX = 1 # macro +mmCP_DB_BASE_HI = 0x20d9 # macro +mmCP_DB_BASE_HI_BASE_IDX = 1 # macro +mmCP_DB_BUFSZ = 0x20da # macro +mmCP_DB_BUFSZ_BASE_IDX = 1 # macro +mmCP_DB_CMD_BUFSZ = 0x20db # macro +mmCP_DB_CMD_BUFSZ_BASE_IDX = 1 # macro +mmCP_CE_DB_BASE_LO = 0x20dc # macro +mmCP_CE_DB_BASE_LO_BASE_IDX = 1 # macro +mmCP_CE_DB_BASE_HI = 0x20dd # macro +mmCP_CE_DB_BASE_HI_BASE_IDX = 1 # macro +mmCP_CE_DB_BUFSZ = 0x20de # macro +mmCP_CE_DB_BUFSZ_BASE_IDX = 1 # macro +mmCP_CE_DB_CMD_BUFSZ = 0x20df # macro +mmCP_CE_DB_CMD_BUFSZ_BASE_IDX = 1 # macro +mmCP_PFP_COMPLETION_STATUS = 0x20ec # macro +mmCP_PFP_COMPLETION_STATUS_BASE_IDX = 1 # macro +mmCP_CE_COMPLETION_STATUS = 0x20ed # macro +mmCP_CE_COMPLETION_STATUS_BASE_IDX = 1 # macro +mmCP_PRED_NOT_VISIBLE = 0x20ee # macro +mmCP_PRED_NOT_VISIBLE_BASE_IDX = 1 # macro +mmCP_PFP_METADATA_BASE_ADDR = 0x20f0 # macro +mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX = 1 # macro +mmCP_PFP_METADATA_BASE_ADDR_HI = 0x20f1 # macro +mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro +mmCP_CE_METADATA_BASE_ADDR = 0x20f2 # macro +mmCP_CE_METADATA_BASE_ADDR_BASE_IDX = 1 # macro +mmCP_CE_METADATA_BASE_ADDR_HI = 0x20f3 # macro +mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX = 1 # macro +mmCP_DRAW_INDX_INDR_ADDR = 0x20f4 # macro +mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX = 1 # macro +mmCP_DRAW_INDX_INDR_ADDR_HI = 0x20f5 # macro +mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX = 1 # macro +mmCP_DISPATCH_INDR_ADDR = 0x20f6 # macro +mmCP_DISPATCH_INDR_ADDR_BASE_IDX = 1 # macro +mmCP_DISPATCH_INDR_ADDR_HI = 0x20f7 # macro +mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX = 1 # macro +mmCP_INDEX_BASE_ADDR = 0x20f8 # macro +mmCP_INDEX_BASE_ADDR_BASE_IDX = 1 # macro +mmCP_INDEX_BASE_ADDR_HI = 0x20f9 # macro +mmCP_INDEX_BASE_ADDR_HI_BASE_IDX = 1 # macro +mmCP_INDEX_TYPE = 0x20fa # macro +mmCP_INDEX_TYPE_BASE_IDX = 1 # macro +mmCP_GDS_BKUP_ADDR = 0x20fb # macro +mmCP_GDS_BKUP_ADDR_BASE_IDX = 1 # macro +mmCP_GDS_BKUP_ADDR_HI = 0x20fc # macro +mmCP_GDS_BKUP_ADDR_HI_BASE_IDX = 1 # macro +mmCP_SAMPLE_STATUS = 0x20fd # macro +mmCP_SAMPLE_STATUS_BASE_IDX = 1 # macro +mmCP_ME_COHER_CNTL = 0x20fe # macro +mmCP_ME_COHER_CNTL_BASE_IDX = 1 # macro +mmCP_ME_COHER_SIZE = 0x20ff # macro +mmCP_ME_COHER_SIZE_BASE_IDX = 1 # macro +mmCP_ME_COHER_SIZE_HI = 0x2100 # macro +mmCP_ME_COHER_SIZE_HI_BASE_IDX = 1 # macro +mmCP_ME_COHER_BASE = 0x2101 # macro +mmCP_ME_COHER_BASE_BASE_IDX = 1 # macro +mmCP_ME_COHER_BASE_HI = 0x2102 # macro +mmCP_ME_COHER_BASE_HI_BASE_IDX = 1 # macro +mmCP_ME_COHER_STATUS = 0x2103 # macro +mmCP_ME_COHER_STATUS_BASE_IDX = 1 # macro +mmRLC_GPM_PERF_COUNT_0 = 0x2140 # macro +mmRLC_GPM_PERF_COUNT_0_BASE_IDX = 1 # macro +mmRLC_GPM_PERF_COUNT_1 = 0x2141 # macro +mmRLC_GPM_PERF_COUNT_1_BASE_IDX = 1 # macro +mmGRBM_GFX_INDEX = 0x2200 # macro +mmGRBM_GFX_INDEX_BASE_IDX = 1 # macro +mmVGT_ESGS_RING_SIZE_UMD = 0x2240 # macro +mmVGT_ESGS_RING_SIZE_UMD_BASE_IDX = 1 # macro +mmVGT_GSVS_RING_SIZE_UMD = 0x2241 # macro +mmVGT_GSVS_RING_SIZE_UMD_BASE_IDX = 1 # macro +mmVGT_PRIMITIVE_TYPE = 0x2242 # macro +mmVGT_PRIMITIVE_TYPE_BASE_IDX = 1 # macro +mmVGT_INDEX_TYPE = 0x2243 # macro +mmVGT_INDEX_TYPE_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x2244 # macro +mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x2245 # macro +mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x2246 # macro +mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX = 1 # macro +mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x2247 # macro +mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX = 1 # macro +mmGE_MIN_VTX_INDX = 0x2249 # macro +mmGE_MIN_VTX_INDX_BASE_IDX = 1 # macro +mmGE_INDX_OFFSET = 0x224a # macro +mmGE_INDX_OFFSET_BASE_IDX = 1 # macro +mmGE_MULTI_PRIM_IB_RESET_EN = 0x224b # macro +mmGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX = 1 # macro +mmVGT_NUM_INDICES = 0x224c # macro +mmVGT_NUM_INDICES_BASE_IDX = 1 # macro +mmVGT_NUM_INSTANCES = 0x224d # macro +mmVGT_NUM_INSTANCES_BASE_IDX = 1 # macro +mmVGT_TF_RING_SIZE_UMD = 0x224e # macro +mmVGT_TF_RING_SIZE_UMD_BASE_IDX = 1 # macro +mmVGT_HS_OFFCHIP_PARAM_UMD = 0x224f # macro +mmVGT_HS_OFFCHIP_PARAM_UMD_BASE_IDX = 1 # macro +mmVGT_TF_MEMORY_BASE_UMD = 0x2250 # macro +mmVGT_TF_MEMORY_BASE_UMD_BASE_IDX = 1 # macro +mmGE_DMA_FIRST_INDEX = 0x2251 # macro +mmGE_DMA_FIRST_INDEX_BASE_IDX = 1 # macro +mmWD_POS_BUF_BASE = 0x2252 # macro +mmWD_POS_BUF_BASE_BASE_IDX = 1 # macro +mmWD_POS_BUF_BASE_HI = 0x2253 # macro +mmWD_POS_BUF_BASE_HI_BASE_IDX = 1 # macro +mmWD_CNTL_SB_BUF_BASE = 0x2254 # macro +mmWD_CNTL_SB_BUF_BASE_BASE_IDX = 1 # macro +mmWD_CNTL_SB_BUF_BASE_HI = 0x2255 # macro +mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX = 1 # macro +mmWD_INDEX_BUF_BASE = 0x2256 # macro +mmWD_INDEX_BUF_BASE_BASE_IDX = 1 # macro +mmWD_INDEX_BUF_BASE_HI = 0x2257 # macro +mmWD_INDEX_BUF_BASE_HI_BASE_IDX = 1 # macro +mmIA_MULTI_VGT_PARAM_PIPED = 0x2258 # macro +mmIA_MULTI_VGT_PARAM_PIPED_BASE_IDX = 1 # macro +mmGE_MAX_VTX_INDX = 0x2259 # macro +mmGE_MAX_VTX_INDX_BASE_IDX = 1 # macro +mmVGT_INSTANCE_BASE_ID = 0x225a # macro +mmVGT_INSTANCE_BASE_ID_BASE_IDX = 1 # macro +mmGE_CNTL = 0x225b # macro +mmGE_CNTL_BASE_IDX = 1 # macro +mmGE_USER_VGPR1 = 0x225c # macro +mmGE_USER_VGPR1_BASE_IDX = 1 # macro +mmGE_USER_VGPR2 = 0x225d # macro +mmGE_USER_VGPR2_BASE_IDX = 1 # macro +mmGE_USER_VGPR3 = 0x225e # macro +mmGE_USER_VGPR3_BASE_IDX = 1 # macro +mmGE_STEREO_CNTL = 0x225f # macro +mmGE_STEREO_CNTL_BASE_IDX = 1 # macro +mmGE_PC_ALLOC = 0x2260 # macro +mmGE_PC_ALLOC_BASE_IDX = 1 # macro +mmVGT_TF_MEMORY_BASE_HI_UMD = 0x2261 # macro +mmVGT_TF_MEMORY_BASE_HI_UMD_BASE_IDX = 1 # macro +mmGE_USER_VGPR_EN = 0x2262 # macro +mmGE_USER_VGPR_EN_BASE_IDX = 1 # macro +mmPA_SU_LINE_STIPPLE_VALUE = 0x2280 # macro +mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX = 1 # macro +mmPA_SC_LINE_STIPPLE_STATE = 0x2281 # macro +mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX = 1 # macro +mmPA_SC_SCREEN_EXTENT_MIN_0 = 0x2284 # macro +mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX = 1 # macro +mmPA_SC_SCREEN_EXTENT_MAX_0 = 0x2285 # macro +mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX = 1 # macro +mmPA_SC_SCREEN_EXTENT_MIN_1 = 0x2286 # macro +mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX = 1 # macro +mmPA_SC_SCREEN_EXTENT_MAX_1 = 0x228b # macro +mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX = 1 # macro +mmPA_SC_P3D_TRAP_SCREEN_HV_EN = 0x22a0 # macro +mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro +mmPA_SC_P3D_TRAP_SCREEN_H = 0x22a1 # macro +mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro +mmPA_SC_P3D_TRAP_SCREEN_V = 0x22a2 # macro +mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro +mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE = 0x22a3 # macro +mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro +mmPA_SC_P3D_TRAP_SCREEN_COUNT = 0x22a4 # macro +mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro +mmPA_SC_HP3D_TRAP_SCREEN_HV_EN = 0x22a8 # macro +mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro +mmPA_SC_HP3D_TRAP_SCREEN_H = 0x22a9 # macro +mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX = 1 # macro +mmPA_SC_HP3D_TRAP_SCREEN_V = 0x22aa # macro +mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX = 1 # macro +mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE = 0x22ab # macro +mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro +mmPA_SC_HP3D_TRAP_SCREEN_COUNT = 0x22ac # macro +mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro +mmPA_SC_TRAP_SCREEN_HV_EN = 0x22b0 # macro +mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX = 1 # macro +mmPA_SC_TRAP_SCREEN_H = 0x22b1 # macro +mmPA_SC_TRAP_SCREEN_H_BASE_IDX = 1 # macro +mmPA_SC_TRAP_SCREEN_V = 0x22b2 # macro +mmPA_SC_TRAP_SCREEN_V_BASE_IDX = 1 # macro +mmPA_SC_TRAP_SCREEN_OCCURRENCE = 0x22b3 # macro +mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX = 1 # macro +mmPA_SC_TRAP_SCREEN_COUNT = 0x22b4 # macro +mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX = 1 # macro +mmSQ_THREAD_TRACE_USERDATA_0 = 0x2340 # macro +mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX = 1 # macro +mmSQ_THREAD_TRACE_USERDATA_1 = 0x2341 # macro +mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX = 1 # macro +mmSQ_THREAD_TRACE_USERDATA_2 = 0x2342 # macro +mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX = 1 # macro +mmSQ_THREAD_TRACE_USERDATA_3 = 0x2343 # macro +mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX = 1 # macro +mmSQ_THREAD_TRACE_USERDATA_4 = 0x2344 # macro +mmSQ_THREAD_TRACE_USERDATA_4_BASE_IDX = 1 # macro +mmSQ_THREAD_TRACE_USERDATA_5 = 0x2345 # macro +mmSQ_THREAD_TRACE_USERDATA_5_BASE_IDX = 1 # macro +mmSQ_THREAD_TRACE_USERDATA_6 = 0x2346 # macro +mmSQ_THREAD_TRACE_USERDATA_6_BASE_IDX = 1 # macro +mmSQ_THREAD_TRACE_USERDATA_7 = 0x2347 # macro +mmSQ_THREAD_TRACE_USERDATA_7_BASE_IDX = 1 # macro +mmSQC_CACHES = 0x2348 # macro +mmSQC_CACHES_BASE_IDX = 1 # macro +mmTA_CS_BC_BASE_ADDR = 0x2380 # macro +mmTA_CS_BC_BASE_ADDR_BASE_IDX = 1 # macro +mmTA_CS_BC_BASE_ADDR_HI = 0x2381 # macro +mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX = 1 # macro +mmDB_OCCLUSION_COUNT0_LOW = 0x23c0 # macro +mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX = 1 # macro +mmDB_OCCLUSION_COUNT0_HI = 0x23c1 # macro +mmDB_OCCLUSION_COUNT0_HI_BASE_IDX = 1 # macro +mmDB_OCCLUSION_COUNT1_LOW = 0x23c2 # macro +mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX = 1 # macro +mmDB_OCCLUSION_COUNT1_HI = 0x23c3 # macro +mmDB_OCCLUSION_COUNT1_HI_BASE_IDX = 1 # macro +mmDB_OCCLUSION_COUNT2_LOW = 0x23c4 # macro +mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX = 1 # macro +mmDB_OCCLUSION_COUNT2_HI = 0x23c5 # macro +mmDB_OCCLUSION_COUNT2_HI_BASE_IDX = 1 # macro +mmDB_OCCLUSION_COUNT3_LOW = 0x23c6 # macro +mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX = 1 # macro +mmDB_OCCLUSION_COUNT3_HI = 0x23c7 # macro +mmDB_OCCLUSION_COUNT3_HI_BASE_IDX = 1 # macro +mmDB_ZPASS_COUNT_LOW = 0x23fe # macro +mmDB_ZPASS_COUNT_LOW_BASE_IDX = 1 # macro +mmDB_ZPASS_COUNT_HI = 0x23ff # macro +mmDB_ZPASS_COUNT_HI_BASE_IDX = 1 # macro +mmGDS_RD_ADDR = 0x2400 # macro +mmGDS_RD_ADDR_BASE_IDX = 1 # macro +mmGDS_RD_DATA = 0x2401 # macro +mmGDS_RD_DATA_BASE_IDX = 1 # macro +mmGDS_RD_BURST_ADDR = 0x2402 # macro +mmGDS_RD_BURST_ADDR_BASE_IDX = 1 # macro +mmGDS_RD_BURST_COUNT = 0x2403 # macro +mmGDS_RD_BURST_COUNT_BASE_IDX = 1 # macro +mmGDS_RD_BURST_DATA = 0x2404 # macro +mmGDS_RD_BURST_DATA_BASE_IDX = 1 # macro +mmGDS_WR_ADDR = 0x2405 # macro +mmGDS_WR_ADDR_BASE_IDX = 1 # macro +mmGDS_WR_DATA = 0x2406 # macro +mmGDS_WR_DATA_BASE_IDX = 1 # macro +mmGDS_WR_BURST_ADDR = 0x2407 # macro +mmGDS_WR_BURST_ADDR_BASE_IDX = 1 # macro +mmGDS_WR_BURST_DATA = 0x2408 # macro +mmGDS_WR_BURST_DATA_BASE_IDX = 1 # macro +mmGDS_WRITE_COMPLETE = 0x2409 # macro +mmGDS_WRITE_COMPLETE_BASE_IDX = 1 # macro +mmGDS_ATOM_CNTL = 0x240a # macro +mmGDS_ATOM_CNTL_BASE_IDX = 1 # macro +mmGDS_ATOM_COMPLETE = 0x240b # macro +mmGDS_ATOM_COMPLETE_BASE_IDX = 1 # macro +mmGDS_ATOM_BASE = 0x240c # macro +mmGDS_ATOM_BASE_BASE_IDX = 1 # macro +mmGDS_ATOM_SIZE = 0x240d # macro +mmGDS_ATOM_SIZE_BASE_IDX = 1 # macro +mmGDS_ATOM_OFFSET0 = 0x240e # macro +mmGDS_ATOM_OFFSET0_BASE_IDX = 1 # macro +mmGDS_ATOM_OFFSET1 = 0x240f # macro +mmGDS_ATOM_OFFSET1_BASE_IDX = 1 # macro +mmGDS_ATOM_DST = 0x2410 # macro +mmGDS_ATOM_DST_BASE_IDX = 1 # macro +mmGDS_ATOM_OP = 0x2411 # macro +mmGDS_ATOM_OP_BASE_IDX = 1 # macro +mmGDS_ATOM_SRC0 = 0x2412 # macro +mmGDS_ATOM_SRC0_BASE_IDX = 1 # macro +mmGDS_ATOM_SRC0_U = 0x2413 # macro +mmGDS_ATOM_SRC0_U_BASE_IDX = 1 # macro +mmGDS_ATOM_SRC1 = 0x2414 # macro +mmGDS_ATOM_SRC1_BASE_IDX = 1 # macro +mmGDS_ATOM_SRC1_U = 0x2415 # macro +mmGDS_ATOM_SRC1_U_BASE_IDX = 1 # macro +mmGDS_ATOM_READ0 = 0x2416 # macro +mmGDS_ATOM_READ0_BASE_IDX = 1 # macro +mmGDS_ATOM_READ0_U = 0x2417 # macro +mmGDS_ATOM_READ0_U_BASE_IDX = 1 # macro +mmGDS_ATOM_READ1 = 0x2418 # macro +mmGDS_ATOM_READ1_BASE_IDX = 1 # macro +mmGDS_ATOM_READ1_U = 0x2419 # macro +mmGDS_ATOM_READ1_U_BASE_IDX = 1 # macro +mmGDS_GWS_RESOURCE_CNTL = 0x241a # macro +mmGDS_GWS_RESOURCE_CNTL_BASE_IDX = 1 # macro +mmGDS_GWS_RESOURCE = 0x241b # macro +mmGDS_GWS_RESOURCE_BASE_IDX = 1 # macro +mmGDS_GWS_RESOURCE_CNT = 0x241c # macro +mmGDS_GWS_RESOURCE_CNT_BASE_IDX = 1 # macro +mmGDS_OA_CNTL = 0x241d # macro +mmGDS_OA_CNTL_BASE_IDX = 1 # macro +mmGDS_OA_COUNTER = 0x241e # macro +mmGDS_OA_COUNTER_BASE_IDX = 1 # macro +mmGDS_OA_ADDRESS = 0x241f # macro +mmGDS_OA_ADDRESS_BASE_IDX = 1 # macro +mmGDS_OA_INCDEC = 0x2420 # macro +mmGDS_OA_INCDEC_BASE_IDX = 1 # macro +mmGDS_OA_RING_SIZE = 0x2421 # macro +mmGDS_OA_RING_SIZE_BASE_IDX = 1 # macro +mmSPI_CONFIG_CNTL_REMAP = 0x2440 # macro +mmSPI_CONFIG_CNTL_REMAP_BASE_IDX = 1 # macro +mmSPI_CONFIG_CNTL_1_REMAP = 0x2441 # macro +mmSPI_CONFIG_CNTL_1_REMAP_BASE_IDX = 1 # macro +mmSPI_CONFIG_CNTL_2_REMAP = 0x2442 # macro +mmSPI_CONFIG_CNTL_2_REMAP_BASE_IDX = 1 # macro +mmSPI_WAVE_LIMIT_CNTL_REMAP = 0x2443 # macro +mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX = 1 # macro +mmCP_MES_PRGRM_CNTR_START = 0x2800 # macro +mmCP_MES_PRGRM_CNTR_START_BASE_IDX = 1 # macro +mmCP_MES_INTR_ROUTINE_START = 0x2801 # macro +mmCP_MES_INTR_ROUTINE_START_BASE_IDX = 1 # macro +mmCP_MES_MTVEC_LO = 0x2801 # macro +mmCP_MES_MTVEC_LO_BASE_IDX = 1 # macro +mmCP_MES_MTVEC_HI = 0x2802 # macro +mmCP_MES_MTVEC_HI_BASE_IDX = 1 # macro +mmCP_MES_CNTL = 0x2807 # macro +mmCP_MES_CNTL_BASE_IDX = 1 # macro +mmCP_MES_PIPE_PRIORITY_CNTS = 0x2808 # macro +mmCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX = 1 # macro +mmCP_MES_PIPE0_PRIORITY = 0x2809 # macro +mmCP_MES_PIPE0_PRIORITY_BASE_IDX = 1 # macro +mmCP_MES_PIPE1_PRIORITY = 0x280a # macro +mmCP_MES_PIPE1_PRIORITY_BASE_IDX = 1 # macro +mmCP_MES_PIPE2_PRIORITY = 0x280b # macro +mmCP_MES_PIPE2_PRIORITY_BASE_IDX = 1 # macro +mmCP_MES_PIPE3_PRIORITY = 0x280c # macro +mmCP_MES_PIPE3_PRIORITY_BASE_IDX = 1 # macro +mmCP_MES_HEADER_DUMP = 0x280d # macro +mmCP_MES_HEADER_DUMP_BASE_IDX = 1 # macro +mmCP_MES_MIE_LO = 0x280e # macro +mmCP_MES_MIE_LO_BASE_IDX = 1 # macro +mmCP_MES_MIE_HI = 0x280f # macro +mmCP_MES_MIE_HI_BASE_IDX = 1 # macro +mmCP_MES_INTERRUPT = 0x2810 # macro +mmCP_MES_INTERRUPT_BASE_IDX = 1 # macro +mmCP_MES_SCRATCH_INDEX = 0x2811 # macro +mmCP_MES_SCRATCH_INDEX_BASE_IDX = 1 # macro +mmCP_MES_SCRATCH_DATA = 0x2812 # macro +mmCP_MES_SCRATCH_DATA_BASE_IDX = 1 # macro +mmCP_MES_INSTR_PNTR = 0x2813 # macro +mmCP_MES_INSTR_PNTR_BASE_IDX = 1 # macro +mmCP_MES_MSCRATCH_HI = 0x2814 # macro +mmCP_MES_MSCRATCH_HI_BASE_IDX = 1 # macro +mmCP_MES_MSCRATCH_LO = 0x2815 # macro +mmCP_MES_MSCRATCH_LO_BASE_IDX = 1 # macro +mmCP_MES_MSTATUS_LO = 0x2816 # macro +mmCP_MES_MSTATUS_LO_BASE_IDX = 1 # macro +mmCP_MES_MSTATUS_HI = 0x2817 # macro +mmCP_MES_MSTATUS_HI_BASE_IDX = 1 # macro +mmCP_MES_MEPC_LO = 0x2818 # macro +mmCP_MES_MEPC_LO_BASE_IDX = 1 # macro +mmCP_MES_MEPC_HI = 0x2819 # macro +mmCP_MES_MEPC_HI_BASE_IDX = 1 # macro +mmCP_MES_MCAUSE_LO = 0x281a # macro +mmCP_MES_MCAUSE_LO_BASE_IDX = 1 # macro +mmCP_MES_MCAUSE_HI = 0x281b # macro +mmCP_MES_MCAUSE_HI_BASE_IDX = 1 # macro +mmCP_MES_MBADADDR_LO = 0x281c # macro +mmCP_MES_MBADADDR_LO_BASE_IDX = 1 # macro +mmCP_MES_MBADADDR_HI = 0x281d # macro +mmCP_MES_MBADADDR_HI_BASE_IDX = 1 # macro +mmCP_MES_MIP_LO = 0x281e # macro +mmCP_MES_MIP_LO_BASE_IDX = 1 # macro +mmCP_MES_MIP_HI = 0x281f # macro +mmCP_MES_MIP_HI_BASE_IDX = 1 # macro +mmCP_MES_IC_OP_CNTL = 0x2820 # macro +mmCP_MES_IC_OP_CNTL_BASE_IDX = 1 # macro +mmCP_MES_MCYCLE_LO = 0x2826 # macro +mmCP_MES_MCYCLE_LO_BASE_IDX = 1 # macro +mmCP_MES_MCYCLE_HI = 0x2827 # macro +mmCP_MES_MCYCLE_HI_BASE_IDX = 1 # macro +mmCP_MES_MTIME_LO = 0x2828 # macro +mmCP_MES_MTIME_LO_BASE_IDX = 1 # macro +mmCP_MES_MTIME_HI = 0x2829 # macro +mmCP_MES_MTIME_HI_BASE_IDX = 1 # macro +mmCP_MES_MINSTRET_LO = 0x282a # macro +mmCP_MES_MINSTRET_LO_BASE_IDX = 1 # macro +mmCP_MES_MINSTRET_HI = 0x282b # macro +mmCP_MES_MINSTRET_HI_BASE_IDX = 1 # macro +mmCP_MES_MISA_LO = 0x282c # macro +mmCP_MES_MISA_LO_BASE_IDX = 1 # macro +mmCP_MES_MISA_HI = 0x282d # macro +mmCP_MES_MISA_HI_BASE_IDX = 1 # macro +mmCP_MES_MVENDORID_LO = 0x282e # macro +mmCP_MES_MVENDORID_LO_BASE_IDX = 1 # macro +mmCP_MES_MVENDORID_HI = 0x282f # macro +mmCP_MES_MVENDORID_HI_BASE_IDX = 1 # macro +mmCP_MES_MARCHID_LO = 0x2830 # macro +mmCP_MES_MARCHID_LO_BASE_IDX = 1 # macro +mmCP_MES_MARCHID_HI = 0x2831 # macro +mmCP_MES_MARCHID_HI_BASE_IDX = 1 # macro +mmCP_MES_MIMPID_LO = 0x2832 # macro +mmCP_MES_MIMPID_LO_BASE_IDX = 1 # macro +mmCP_MES_MIMPID_HI = 0x2833 # macro +mmCP_MES_MIMPID_HI_BASE_IDX = 1 # macro +mmCP_MES_MHARTID_LO = 0x2834 # macro +mmCP_MES_MHARTID_LO_BASE_IDX = 1 # macro +mmCP_MES_MHARTID_HI = 0x2835 # macro +mmCP_MES_MHARTID_HI_BASE_IDX = 1 # macro +mmCP_MES_DC_BASE_CNTL = 0x2836 # macro +mmCP_MES_DC_BASE_CNTL_BASE_IDX = 1 # macro +mmCP_MES_DC_OP_CNTL = 0x2837 # macro +mmCP_MES_DC_OP_CNTL_BASE_IDX = 1 # macro +mmCP_MES_MTIMECMP_LO = 0x2838 # macro +mmCP_MES_MTIMECMP_LO_BASE_IDX = 1 # macro +mmCP_MES_MTIMECMP_HI = 0x2839 # macro +mmCP_MES_MTIMECMP_HI_BASE_IDX = 1 # macro +mmCP_MES_PROCESS_QUANTUM_PIPE0 = 0x283a # macro +mmCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX = 1 # macro +mmCP_MES_PROCESS_QUANTUM_PIPE1 = 0x283b # macro +mmCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX = 1 # macro +mmCP_MES_DOORBELL_CONTROL1 = 0x283c # macro +mmCP_MES_DOORBELL_CONTROL1_BASE_IDX = 1 # macro +mmCP_MES_DOORBELL_CONTROL2 = 0x283d # macro +mmCP_MES_DOORBELL_CONTROL2_BASE_IDX = 1 # macro +mmCP_MES_DOORBELL_CONTROL3 = 0x283e # macro +mmCP_MES_DOORBELL_CONTROL3_BASE_IDX = 1 # macro +mmCP_MES_DOORBELL_CONTROL4 = 0x283f # macro +mmCP_MES_DOORBELL_CONTROL4_BASE_IDX = 1 # macro +mmCP_MES_DOORBELL_CONTROL5 = 0x2840 # macro +mmCP_MES_DOORBELL_CONTROL5_BASE_IDX = 1 # macro +mmCP_MES_DOORBELL_CONTROL6 = 0x2841 # macro +mmCP_MES_DOORBELL_CONTROL6_BASE_IDX = 1 # macro +mmCP_MES_GP0_LO = 0x2843 # macro +mmCP_MES_GP0_LO_BASE_IDX = 1 # macro +mmCP_MES_GP0_HI = 0x2844 # macro +mmCP_MES_GP0_HI_BASE_IDX = 1 # macro +mmCP_MES_GP1_LO = 0x2845 # macro +mmCP_MES_GP1_LO_BASE_IDX = 1 # macro +mmCP_MES_GP1_HI = 0x2846 # macro +mmCP_MES_GP1_HI_BASE_IDX = 1 # macro +mmCP_MES_GP2_LO = 0x2847 # macro +mmCP_MES_GP2_LO_BASE_IDX = 1 # macro +mmCP_MES_GP2_HI = 0x2848 # macro +mmCP_MES_GP2_HI_BASE_IDX = 1 # macro +mmCP_MES_GP3_LO = 0x2849 # macro +mmCP_MES_GP3_LO_BASE_IDX = 1 # macro +mmCP_MES_GP3_HI = 0x284a # macro +mmCP_MES_GP3_HI_BASE_IDX = 1 # macro +mmCP_MES_GP4_LO = 0x284b # macro +mmCP_MES_GP4_LO_BASE_IDX = 1 # macro +mmCP_MES_GP4_HI = 0x284c # macro +mmCP_MES_GP4_HI_BASE_IDX = 1 # macro +mmCP_MES_GP5_LO = 0x284d # macro +mmCP_MES_GP5_LO_BASE_IDX = 1 # macro +mmCP_MES_GP5_HI = 0x284e # macro +mmCP_MES_GP5_HI_BASE_IDX = 1 # macro +mmCP_MES_GP6_LO = 0x284f # macro +mmCP_MES_GP6_LO_BASE_IDX = 1 # macro +mmCP_MES_GP6_HI = 0x2850 # macro +mmCP_MES_GP6_HI_BASE_IDX = 1 # macro +mmCP_MES_GP7_LO = 0x2851 # macro +mmCP_MES_GP7_LO_BASE_IDX = 1 # macro +mmCP_MES_GP7_HI = 0x2852 # macro +mmCP_MES_GP7_HI_BASE_IDX = 1 # macro +mmCP_MES_GP8_LO = 0x2853 # macro +mmCP_MES_GP8_LO_BASE_IDX = 1 # macro +mmCP_MES_GP8_HI = 0x2854 # macro +mmCP_MES_GP8_HI_BASE_IDX = 1 # macro +mmCP_MES_GP9_LO = 0x2855 # macro +mmCP_MES_GP9_LO_BASE_IDX = 1 # macro +mmCP_MES_GP9_HI = 0x2856 # macro +mmCP_MES_GP9_HI_BASE_IDX = 1 # macro +mmCP_MES_DM_INDEX_ADDR = 0x2880 # macro +mmCP_MES_DM_INDEX_ADDR_BASE_IDX = 1 # macro +mmCP_MES_DM_INDEX_DATA = 0x2881 # macro +mmCP_MES_DM_INDEX_DATA_BASE_IDX = 1 # macro +mmCP_MES_PERFCOUNT_CNTL = 0x2899 # macro +mmCP_MES_PERFCOUNT_CNTL_BASE_IDX = 1 # macro +mmCP_MES_PENDING_INTERRUPT = 0x289a # macro +mmCP_MES_PENDING_INTERRUPT_BASE_IDX = 1 # macro +mmGUS_IO_RD_COMBINE_FLUSH = 0x2c00 # macro +mmGUS_IO_RD_COMBINE_FLUSH_BASE_IDX = 1 # macro +mmGUS_IO_WR_COMBINE_FLUSH = 0x2c01 # macro +mmGUS_IO_WR_COMBINE_FLUSH_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_AGE_RATE = 0x2c02 # macro +mmGUS_IO_RD_PRI_AGE_RATE_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_AGE_RATE = 0x2c03 # macro +mmGUS_IO_WR_PRI_AGE_RATE_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_AGE_COEFF = 0x2c04 # macro +mmGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_AGE_COEFF = 0x2c05 # macro +mmGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_QUEUING = 0x2c06 # macro +mmGUS_IO_RD_PRI_QUEUING_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_QUEUING = 0x2c07 # macro +mmGUS_IO_WR_PRI_QUEUING_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_FIXED = 0x2c08 # macro +mmGUS_IO_RD_PRI_FIXED_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_FIXED = 0x2c09 # macro +mmGUS_IO_WR_PRI_FIXED_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_URGENCY_COEFF = 0x2c0a # macro +mmGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_URGENCY_COEFF = 0x2c0b # macro +mmGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_URGENCY_MODE = 0x2c0c # macro +mmGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_URGENCY_MODE = 0x2c0d # macro +mmGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_QUANT_PRI1 = 0x2c0e # macro +mmGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_QUANT_PRI2 = 0x2c0f # macro +mmGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_QUANT_PRI3 = 0x2c10 # macro +mmGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_QUANT_PRI4 = 0x2c11 # macro +mmGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_QUANT_PRI1 = 0x2c12 # macro +mmGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_QUANT_PRI2 = 0x2c13 # macro +mmGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_QUANT_PRI3 = 0x2c14 # macro +mmGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_QUANT_PRI4 = 0x2c15 # macro +mmGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_QUANT1_PRI1 = 0x2c16 # macro +mmGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_QUANT1_PRI2 = 0x2c17 # macro +mmGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_QUANT1_PRI3 = 0x2c18 # macro +mmGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro +mmGUS_IO_RD_PRI_QUANT1_PRI4 = 0x2c19 # macro +mmGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_QUANT1_PRI1 = 0x2c1a # macro +mmGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_QUANT1_PRI2 = 0x2c1b # macro +mmGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_QUANT1_PRI3 = 0x2c1c # macro +mmGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro +mmGUS_IO_WR_PRI_QUANT1_PRI4 = 0x2c1d # macro +mmGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro +mmGUS_DRAM_COMBINE_FLUSH = 0x2c1e # macro +mmGUS_DRAM_COMBINE_FLUSH_BASE_IDX = 1 # macro +mmGUS_DRAM_COMBINE_RD_WR_EN = 0x2c1f # macro +mmGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_AGE_RATE = 0x2c20 # macro +mmGUS_DRAM_PRI_AGE_RATE_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_AGE_COEFF = 0x2c21 # macro +mmGUS_DRAM_PRI_AGE_COEFF_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_QUEUING = 0x2c22 # macro +mmGUS_DRAM_PRI_QUEUING_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_FIXED = 0x2c23 # macro +mmGUS_DRAM_PRI_FIXED_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_URGENCY_COEFF = 0x2c24 # macro +mmGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_URGENCY_MODE = 0x2c25 # macro +mmGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_QUANT_PRI1 = 0x2c26 # macro +mmGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_QUANT_PRI2 = 0x2c27 # macro +mmGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_QUANT_PRI3 = 0x2c28 # macro +mmGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_QUANT_PRI4 = 0x2c29 # macro +mmGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_QUANT_PRI5 = 0x2c2a # macro +mmGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_QUANT1_PRI1 = 0x2c2b # macro +mmGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_QUANT1_PRI2 = 0x2c2c # macro +mmGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_QUANT1_PRI3 = 0x2c2d # macro +mmGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_QUANT1_PRI4 = 0x2c2e # macro +mmGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX = 1 # macro +mmGUS_DRAM_PRI_QUANT1_PRI5 = 0x2c2f # macro +mmGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX = 1 # macro +mmGUS_IO_GROUP_BURST = 0x2c30 # macro +mmGUS_IO_GROUP_BURST_BASE_IDX = 1 # macro +mmGUS_DRAM_GROUP_BURST = 0x2c31 # macro +mmGUS_DRAM_GROUP_BURST_BASE_IDX = 1 # macro +mmGUS_SDP_ARB_FINAL = 0x2c32 # macro +mmGUS_SDP_ARB_FINAL_BASE_IDX = 1 # macro +mmGUS_SDP_QOS_VC_PRIORITY = 0x2c33 # macro +mmGUS_SDP_QOS_VC_PRIORITY_BASE_IDX = 1 # macro +mmGUS_SDP_CREDITS = 0x2c34 # macro +mmGUS_SDP_CREDITS_BASE_IDX = 1 # macro +mmGUS_SDP_TAG_RESERVE0 = 0x2c35 # macro +mmGUS_SDP_TAG_RESERVE0_BASE_IDX = 1 # macro +mmGUS_SDP_TAG_RESERVE1 = 0x2c36 # macro +mmGUS_SDP_TAG_RESERVE1_BASE_IDX = 1 # macro +mmGUS_SDP_VCC_RESERVE0 = 0x2c37 # macro +mmGUS_SDP_VCC_RESERVE0_BASE_IDX = 1 # macro +mmGUS_SDP_VCC_RESERVE1 = 0x2c38 # macro +mmGUS_SDP_VCC_RESERVE1_BASE_IDX = 1 # macro +mmGUS_SDP_VCD_RESERVE0 = 0x2c39 # macro +mmGUS_SDP_VCD_RESERVE0_BASE_IDX = 1 # macro +mmGUS_SDP_VCD_RESERVE1 = 0x2c3a # macro +mmGUS_SDP_VCD_RESERVE1_BASE_IDX = 1 # macro +mmGUS_SDP_REQ_CNTL = 0x2c3b # macro +mmGUS_SDP_REQ_CNTL_BASE_IDX = 1 # macro +mmGUS_MISC = 0x2c3c # macro +mmGUS_MISC_BASE_IDX = 1 # macro +mmGUS_LATENCY_SAMPLING = 0x2c3d # macro +mmGUS_LATENCY_SAMPLING_BASE_IDX = 1 # macro +mmGUS_ERR_STATUS = 0x2c3e # macro +mmGUS_ERR_STATUS_BASE_IDX = 1 # macro +mmGUS_MISC2 = 0x2c3f # macro +mmGUS_MISC2_BASE_IDX = 1 # macro +mmGUS_SDP_ENABLE = 0x2c45 # macro +mmGUS_SDP_ENABLE_BASE_IDX = 1 # macro +mmGUS_L1_CH0_CMD_IN = 0x2c46 # macro +mmGUS_L1_CH0_CMD_IN_BASE_IDX = 1 # macro +mmGUS_L1_CH0_CMD_OUT = 0x2c47 # macro +mmGUS_L1_CH0_CMD_OUT_BASE_IDX = 1 # macro +mmGUS_L1_CH0_DATA_IN = 0x2c48 # macro +mmGUS_L1_CH0_DATA_IN_BASE_IDX = 1 # macro +mmGUS_L1_CH0_DATA_OUT = 0x2c49 # macro +mmGUS_L1_CH0_DATA_OUT_BASE_IDX = 1 # macro +mmGUS_L1_CH0_DATA_U_IN = 0x2c4a # macro +mmGUS_L1_CH0_DATA_U_IN_BASE_IDX = 1 # macro +mmGUS_L1_CH0_DATA_U_OUT = 0x2c4b # macro +mmGUS_L1_CH0_DATA_U_OUT_BASE_IDX = 1 # macro +mmGUS_L1_CH1_CMD_IN = 0x2c4c # macro +mmGUS_L1_CH1_CMD_IN_BASE_IDX = 1 # macro +mmGUS_L1_CH1_CMD_OUT = 0x2c4d # macro +mmGUS_L1_CH1_CMD_OUT_BASE_IDX = 1 # macro +mmGUS_L1_CH1_DATA_IN = 0x2c4e # macro +mmGUS_L1_CH1_DATA_IN_BASE_IDX = 1 # macro +mmGUS_L1_CH1_DATA_OUT = 0x2c4f # macro +mmGUS_L1_CH1_DATA_OUT_BASE_IDX = 1 # macro +mmGUS_L1_CH1_DATA_U_IN = 0x2c50 # macro +mmGUS_L1_CH1_DATA_U_IN_BASE_IDX = 1 # macro +mmGUS_L1_CH1_DATA_U_OUT = 0x2c51 # macro +mmGUS_L1_CH1_DATA_U_OUT_BASE_IDX = 1 # macro +mmGUS_L1_SA0_CMD_IN = 0x2c52 # macro +mmGUS_L1_SA0_CMD_IN_BASE_IDX = 1 # macro +mmGUS_L1_SA0_CMD_OUT = 0x2c53 # macro +mmGUS_L1_SA0_CMD_OUT_BASE_IDX = 1 # macro +mmGUS_L1_SA0_DATA_IN = 0x2c54 # macro +mmGUS_L1_SA0_DATA_IN_BASE_IDX = 1 # macro +mmGUS_L1_SA0_DATA_OUT = 0x2c55 # macro +mmGUS_L1_SA0_DATA_OUT_BASE_IDX = 1 # macro +mmGUS_L1_SA0_DATA_U_IN = 0x2c56 # macro +mmGUS_L1_SA0_DATA_U_IN_BASE_IDX = 1 # macro +mmGUS_L1_SA0_DATA_U_OUT = 0x2c57 # macro +mmGUS_L1_SA0_DATA_U_OUT_BASE_IDX = 1 # macro +mmGUS_L1_SA1_CMD_IN = 0x2c58 # macro +mmGUS_L1_SA1_CMD_IN_BASE_IDX = 1 # macro +mmGUS_L1_SA1_CMD_OUT = 0x2c59 # macro +mmGUS_L1_SA1_CMD_OUT_BASE_IDX = 1 # macro +mmGUS_L1_SA1_DATA_IN = 0x2c5a # macro +mmGUS_L1_SA1_DATA_IN_BASE_IDX = 1 # macro +mmGUS_L1_SA1_DATA_OUT = 0x2c5b # macro +mmGUS_L1_SA1_DATA_OUT_BASE_IDX = 1 # macro +mmGUS_L1_SA1_DATA_U_IN = 0x2c5c # macro +mmGUS_L1_SA1_DATA_U_IN_BASE_IDX = 1 # macro +mmGUS_L1_SA1_DATA_U_OUT = 0x2c5d # macro +mmGUS_L1_SA1_DATA_U_OUT_BASE_IDX = 1 # macro +mmGUS_L1_SA2_CMD_IN = 0x2c5e # macro +mmGUS_L1_SA2_CMD_IN_BASE_IDX = 1 # macro +mmGUS_L1_SA2_CMD_OUT = 0x2c5f # macro +mmGUS_L1_SA2_CMD_OUT_BASE_IDX = 1 # macro +mmGUS_L1_SA2_DATA_IN = 0x2c60 # macro +mmGUS_L1_SA2_DATA_IN_BASE_IDX = 1 # macro +mmGUS_L1_SA2_DATA_OUT = 0x2c61 # macro +mmGUS_L1_SA2_DATA_OUT_BASE_IDX = 1 # macro +mmGUS_L1_SA2_DATA_U_IN = 0x2c62 # macro +mmGUS_L1_SA2_DATA_U_IN_BASE_IDX = 1 # macro +mmGUS_L1_SA2_DATA_U_OUT = 0x2c63 # macro +mmGUS_L1_SA2_DATA_U_OUT_BASE_IDX = 1 # macro +mmGUS_L1_SA3_CMD_IN = 0x2c64 # macro +mmGUS_L1_SA3_CMD_IN_BASE_IDX = 1 # macro +mmGUS_L1_SA3_CMD_OUT = 0x2c65 # macro +mmGUS_L1_SA3_CMD_OUT_BASE_IDX = 1 # macro +mmGUS_L1_SA3_DATA_IN = 0x2c66 # macro +mmGUS_L1_SA3_DATA_IN_BASE_IDX = 1 # macro +mmGUS_L1_SA3_DATA_OUT = 0x2c67 # macro +mmGUS_L1_SA3_DATA_OUT_BASE_IDX = 1 # macro +mmGUS_L1_SA3_DATA_U_IN = 0x2c68 # macro +mmGUS_L1_SA3_DATA_U_IN_BASE_IDX = 1 # macro +mmGUS_L1_SA3_DATA_U_OUT = 0x2c69 # macro +mmGUS_L1_SA3_DATA_U_OUT_BASE_IDX = 1 # macro +mmGUS_MISC3 = 0x2c6a # macro +mmGUS_MISC3_BASE_IDX = 1 # macro +mmGUS_WRRSP_FIFO_CNTL = 0x2c6b # macro +mmGUS_WRRSP_FIFO_CNTL_BASE_IDX = 1 # macro +mmGL1_DRAM_BURST_MASK = 0x2d02 # macro +mmGL1_DRAM_BURST_MASK_BASE_IDX = 1 # macro +mmGL1_ARB_STATUS = 0x2d03 # macro +mmGL1_ARB_STATUS_BASE_IDX = 1 # macro +mmGL1_PIPE_STEER = 0x2d10 # macro +mmGL1_PIPE_STEER_BASE_IDX = 1 # macro +mmGL1C_STATUS = 0x2d41 # macro +mmGL1C_STATUS_BASE_IDX = 1 # macro +mmGL1C_UTCL0_CNTL2 = 0x2d43 # macro +mmGL1C_UTCL0_CNTL2_BASE_IDX = 1 # macro +mmGL1C_UTCL0_STATUS = 0x2d44 # macro +mmGL1C_UTCL0_STATUS_BASE_IDX = 1 # macro +mmGL1C_UTCL0_RETRY = 0x2d45 # macro +mmGL1C_UTCL0_RETRY_BASE_IDX = 1 # macro +mmCH_ARB_CTRL = 0x2d80 # macro +mmCH_ARB_CTRL_BASE_IDX = 1 # macro +mmCH_DRAM_BURST_MASK = 0x2d82 # macro +mmCH_DRAM_BURST_MASK_BASE_IDX = 1 # macro +mmCH_ARB_STATUS = 0x2d83 # macro +mmCH_ARB_STATUS_BASE_IDX = 1 # macro +mmCH_DRAM_BURST_CTRL = 0x2d84 # macro +mmCH_DRAM_BURST_CTRL_BASE_IDX = 1 # macro +mmCHA_CHC_CREDITS = 0x2d88 # macro +mmCHA_CHC_CREDITS_BASE_IDX = 1 # macro +mmCHA_CLIENT_FREE_DELAY = 0x2d89 # macro +mmCHA_CLIENT_FREE_DELAY_BASE_IDX = 1 # macro +mmCH_PIPE_STEER = 0x2d90 # macro +mmCH_PIPE_STEER_BASE_IDX = 1 # macro +mmCH_VC5_ENABLE = 0x2d94 # macro +mmCH_VC5_ENABLE_BASE_IDX = 1 # macro +mmCHC_CTRL = 0x2dc0 # macro +mmCHC_CTRL_BASE_IDX = 1 # macro +mmCHC_STATUS = 0x2dc1 # macro +mmCHC_STATUS_BASE_IDX = 1 # macro +mmCHCG_CTRL = 0x2dc2 # macro +mmCHCG_CTRL_BASE_IDX = 1 # macro +mmCHCG_STATUS = 0x2dc3 # macro +mmCHCG_STATUS_BASE_IDX = 1 # macro +mmGL2C_CTRL = 0x2e00 # macro +mmGL2C_CTRL_BASE_IDX = 1 # macro +mmGL2C_CTRL2 = 0x2e01 # macro +mmGL2C_CTRL2_BASE_IDX = 1 # macro +mmGL2C_ADDR_MATCH_MASK = 0x2e03 # macro +mmGL2C_ADDR_MATCH_MASK_BASE_IDX = 1 # macro +mmGL2C_ADDR_MATCH_SIZE = 0x2e04 # macro +mmGL2C_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro +mmGL2C_WBINVL2 = 0x2e05 # macro +mmGL2C_WBINVL2_BASE_IDX = 1 # macro +mmGL2C_SOFT_RESET = 0x2e06 # macro +mmGL2C_SOFT_RESET_BASE_IDX = 1 # macro +mmGL2C_CM_CTRL0 = 0x2e07 # macro +mmGL2C_CM_CTRL0_BASE_IDX = 1 # macro +mmGL2C_CM_CTRL1 = 0x2e08 # macro +mmGL2C_CM_CTRL1_BASE_IDX = 1 # macro +mmGL2C_CM_STALL = 0x2e09 # macro +mmGL2C_CM_STALL_BASE_IDX = 1 # macro +mmGL2C_MDC_PF_FLAG_CTRL = 0x2e0a # macro +mmGL2C_MDC_PF_FLAG_CTRL_BASE_IDX = 1 # macro +mmGL2C_LB_CTR_CTRL = 0x2e0d # macro +mmGL2C_LB_CTR_CTRL_BASE_IDX = 1 # macro +mmGL2C_LB_DATA0 = 0x2e0e # macro +mmGL2C_LB_DATA0_BASE_IDX = 1 # macro +mmGL2C_LB_DATA1 = 0x2e0f # macro +mmGL2C_LB_DATA1_BASE_IDX = 1 # macro +mmGL2C_LB_DATA2 = 0x2e10 # macro +mmGL2C_LB_DATA2_BASE_IDX = 1 # macro +mmGL2C_LB_DATA3 = 0x2e11 # macro +mmGL2C_LB_DATA3_BASE_IDX = 1 # macro +mmGL2C_LB_CTR_SEL0 = 0x2e12 # macro +mmGL2C_LB_CTR_SEL0_BASE_IDX = 1 # macro +mmGL2C_LB_CTR_SEL1 = 0x2e13 # macro +mmGL2C_LB_CTR_SEL1_BASE_IDX = 1 # macro +mmGL2A_ADDR_MATCH_CTRL = 0x2e20 # macro +mmGL2A_ADDR_MATCH_CTRL_BASE_IDX = 1 # macro +mmGL2A_ADDR_MATCH_MASK = 0x2e21 # macro +mmGL2A_ADDR_MATCH_MASK_BASE_IDX = 1 # macro +mmGL2A_ADDR_MATCH_SIZE = 0x2e22 # macro +mmGL2A_ADDR_MATCH_SIZE_BASE_IDX = 1 # macro +mmGL2A_PRIORITY_CTRL = 0x2e23 # macro +mmGL2A_PRIORITY_CTRL_BASE_IDX = 1 # macro +mmGL2_PIPE_STEER_0 = 0x2e25 # macro +mmGL2_PIPE_STEER_0_BASE_IDX = 1 # macro +mmGL2_PIPE_STEER_1 = 0x2e26 # macro +mmGL2_PIPE_STEER_1_BASE_IDX = 1 # macro +mmCPG_PERFCOUNTER1_LO = 0x3000 # macro +mmCPG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmCPG_PERFCOUNTER1_HI = 0x3001 # macro +mmCPG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmCPG_PERFCOUNTER0_LO = 0x3002 # macro +mmCPG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmCPG_PERFCOUNTER0_HI = 0x3003 # macro +mmCPG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmCPC_PERFCOUNTER1_LO = 0x3004 # macro +mmCPC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmCPC_PERFCOUNTER1_HI = 0x3005 # macro +mmCPC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmCPC_PERFCOUNTER0_LO = 0x3006 # macro +mmCPC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmCPC_PERFCOUNTER0_HI = 0x3007 # macro +mmCPC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmCPF_PERFCOUNTER1_LO = 0x3008 # macro +mmCPF_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmCPF_PERFCOUNTER1_HI = 0x3009 # macro +mmCPF_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmCPF_PERFCOUNTER0_LO = 0x300a # macro +mmCPF_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmCPF_PERFCOUNTER0_HI = 0x300b # macro +mmCPF_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmCPF_LATENCY_STATS_DATA = 0x300c # macro +mmCPF_LATENCY_STATS_DATA_BASE_IDX = 1 # macro +mmCPG_LATENCY_STATS_DATA = 0x300d # macro +mmCPG_LATENCY_STATS_DATA_BASE_IDX = 1 # macro +mmCPC_LATENCY_STATS_DATA = 0x300e # macro +mmCPC_LATENCY_STATS_DATA_BASE_IDX = 1 # macro +mmGRBM_PERFCOUNTER0_LO = 0x3040 # macro +mmGRBM_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmGRBM_PERFCOUNTER0_HI = 0x3041 # macro +mmGRBM_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmGRBM_PERFCOUNTER1_LO = 0x3043 # macro +mmGRBM_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmGRBM_PERFCOUNTER1_HI = 0x3044 # macro +mmGRBM_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmGRBM_SE0_PERFCOUNTER_LO = 0x3045 # macro +mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX = 1 # macro +mmGRBM_SE0_PERFCOUNTER_HI = 0x3046 # macro +mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX = 1 # macro +mmGRBM_SE1_PERFCOUNTER_LO = 0x3047 # macro +mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX = 1 # macro +mmGRBM_SE1_PERFCOUNTER_HI = 0x3048 # macro +mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX = 1 # macro +mmGRBM_SE2_PERFCOUNTER_LO = 0x3049 # macro +mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX = 1 # macro +mmGRBM_SE2_PERFCOUNTER_HI = 0x304a # macro +mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX = 1 # macro +mmGRBM_SE3_PERFCOUNTER_LO = 0x304b # macro +mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX = 1 # macro +mmGRBM_SE3_PERFCOUNTER_HI = 0x304c # macro +mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER0_LO = 0x30a4 # macro +mmGE1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER0_HI = 0x30a5 # macro +mmGE1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER1_LO = 0x30a6 # macro +mmGE1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER1_HI = 0x30a7 # macro +mmGE1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER2_LO = 0x30a8 # macro +mmGE1_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER2_HI = 0x30a9 # macro +mmGE1_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER3_LO = 0x30aa # macro +mmGE1_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER3_HI = 0x30ab # macro +mmGE1_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER0_LO = 0x30ac # macro +mmGE2_DIST_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER0_HI = 0x30ad # macro +mmGE2_DIST_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER1_LO = 0x30ae # macro +mmGE2_DIST_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER1_HI = 0x30af # macro +mmGE2_DIST_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER2_LO = 0x30b0 # macro +mmGE2_DIST_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER2_HI = 0x30b1 # macro +mmGE2_DIST_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER3_LO = 0x30b2 # macro +mmGE2_DIST_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER3_HI = 0x30b3 # macro +mmGE2_DIST_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER0_LO = 0x30b4 # macro +mmGE2_SE_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER0_HI = 0x30b5 # macro +mmGE2_SE_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER1_LO = 0x30b6 # macro +mmGE2_SE_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER1_HI = 0x30b7 # macro +mmGE2_SE_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER2_LO = 0x30b8 # macro +mmGE2_SE_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER2_HI = 0x30b9 # macro +mmGE2_SE_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER3_LO = 0x30ba # macro +mmGE2_SE_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER3_HI = 0x30bb # macro +mmGE2_SE_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER0_LO = 0x3100 # macro +mmPA_SU_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER0_HI = 0x3101 # macro +mmPA_SU_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER1_LO = 0x3102 # macro +mmPA_SU_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER1_HI = 0x3103 # macro +mmPA_SU_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER2_LO = 0x3104 # macro +mmPA_SU_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER2_HI = 0x3105 # macro +mmPA_SU_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER3_LO = 0x3106 # macro +mmPA_SU_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER3_HI = 0x3107 # macro +mmPA_SU_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER0_LO = 0x3140 # macro +mmPA_SC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER0_HI = 0x3141 # macro +mmPA_SC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER1_LO = 0x3142 # macro +mmPA_SC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER1_HI = 0x3143 # macro +mmPA_SC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER2_LO = 0x3144 # macro +mmPA_SC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER2_HI = 0x3145 # macro +mmPA_SC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER3_LO = 0x3146 # macro +mmPA_SC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER3_HI = 0x3147 # macro +mmPA_SC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER4_LO = 0x3148 # macro +mmPA_SC_PERFCOUNTER4_LO_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER4_HI = 0x3149 # macro +mmPA_SC_PERFCOUNTER4_HI_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER5_LO = 0x314a # macro +mmPA_SC_PERFCOUNTER5_LO_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER5_HI = 0x314b # macro +mmPA_SC_PERFCOUNTER5_HI_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER6_LO = 0x314c # macro +mmPA_SC_PERFCOUNTER6_LO_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER6_HI = 0x314d # macro +mmPA_SC_PERFCOUNTER6_HI_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER7_LO = 0x314e # macro +mmPA_SC_PERFCOUNTER7_LO_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER7_HI = 0x314f # macro +mmPA_SC_PERFCOUNTER7_HI_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER0_HI = 0x3180 # macro +mmSPI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER0_LO = 0x3181 # macro +mmSPI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER1_HI = 0x3182 # macro +mmSPI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER1_LO = 0x3183 # macro +mmSPI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER2_HI = 0x3184 # macro +mmSPI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER2_LO = 0x3185 # macro +mmSPI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER3_HI = 0x3186 # macro +mmSPI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER3_LO = 0x3187 # macro +mmSPI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER4_HI = 0x3188 # macro +mmSPI_PERFCOUNTER4_HI_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER4_LO = 0x3189 # macro +mmSPI_PERFCOUNTER4_LO_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER5_HI = 0x318a # macro +mmSPI_PERFCOUNTER5_HI_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER5_LO = 0x318b # macro +mmSPI_PERFCOUNTER5_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER0_LO = 0x31c0 # macro +mmSQ_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER0_HI = 0x31c1 # macro +mmSQ_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER1_LO = 0x31c2 # macro +mmSQ_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER1_HI = 0x31c3 # macro +mmSQ_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER2_LO = 0x31c4 # macro +mmSQ_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER2_HI = 0x31c5 # macro +mmSQ_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER3_LO = 0x31c6 # macro +mmSQ_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER3_HI = 0x31c7 # macro +mmSQ_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER4_LO = 0x31c8 # macro +mmSQ_PERFCOUNTER4_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER4_HI = 0x31c9 # macro +mmSQ_PERFCOUNTER4_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER5_LO = 0x31ca # macro +mmSQ_PERFCOUNTER5_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER5_HI = 0x31cb # macro +mmSQ_PERFCOUNTER5_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER6_LO = 0x31cc # macro +mmSQ_PERFCOUNTER6_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER6_HI = 0x31cd # macro +mmSQ_PERFCOUNTER6_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER7_LO = 0x31ce # macro +mmSQ_PERFCOUNTER7_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER7_HI = 0x31cf # macro +mmSQ_PERFCOUNTER7_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER8_LO = 0x31d0 # macro +mmSQ_PERFCOUNTER8_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER8_HI = 0x31d1 # macro +mmSQ_PERFCOUNTER8_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER9_LO = 0x31d2 # macro +mmSQ_PERFCOUNTER9_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER9_HI = 0x31d3 # macro +mmSQ_PERFCOUNTER9_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER10_LO = 0x31d4 # macro +mmSQ_PERFCOUNTER10_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER10_HI = 0x31d5 # macro +mmSQ_PERFCOUNTER10_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER11_LO = 0x31d6 # macro +mmSQ_PERFCOUNTER11_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER11_HI = 0x31d7 # macro +mmSQ_PERFCOUNTER11_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER12_LO = 0x31d8 # macro +mmSQ_PERFCOUNTER12_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER12_HI = 0x31d9 # macro +mmSQ_PERFCOUNTER12_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER13_LO = 0x31da # macro +mmSQ_PERFCOUNTER13_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER13_HI = 0x31db # macro +mmSQ_PERFCOUNTER13_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER14_LO = 0x31dc # macro +mmSQ_PERFCOUNTER14_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER14_HI = 0x31dd # macro +mmSQ_PERFCOUNTER14_HI_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER15_LO = 0x31de # macro +mmSQ_PERFCOUNTER15_LO_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER15_HI = 0x31df # macro +mmSQ_PERFCOUNTER15_HI_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER0_LO = 0x3240 # macro +mmSX_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER0_HI = 0x3241 # macro +mmSX_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER1_LO = 0x3242 # macro +mmSX_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER1_HI = 0x3243 # macro +mmSX_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER2_LO = 0x3244 # macro +mmSX_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER2_HI = 0x3245 # macro +mmSX_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER3_LO = 0x3246 # macro +mmSX_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER3_HI = 0x3247 # macro +mmSX_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmGCEA_PERFCOUNTER2_LO = 0x3260 # macro +mmGCEA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmGCEA_PERFCOUNTER2_HI = 0x3261 # macro +mmGCEA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmGCEA_PERFCOUNTER_LO = 0x3262 # macro +mmGCEA_PERFCOUNTER_LO_BASE_IDX = 1 # macro +mmGCEA_PERFCOUNTER_HI = 0x3263 # macro +mmGCEA_PERFCOUNTER_HI_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER0_LO = 0x3280 # macro +mmGDS_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER0_HI = 0x3281 # macro +mmGDS_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER1_LO = 0x3282 # macro +mmGDS_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER1_HI = 0x3283 # macro +mmGDS_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER2_LO = 0x3284 # macro +mmGDS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER2_HI = 0x3285 # macro +mmGDS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER3_LO = 0x3286 # macro +mmGDS_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER3_HI = 0x3287 # macro +mmGDS_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmTA_PERFCOUNTER0_LO = 0x32c0 # macro +mmTA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmTA_PERFCOUNTER0_HI = 0x32c1 # macro +mmTA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmTA_PERFCOUNTER1_LO = 0x32c2 # macro +mmTA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmTA_PERFCOUNTER1_HI = 0x32c3 # macro +mmTA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmTD_PERFCOUNTER0_LO = 0x3300 # macro +mmTD_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmTD_PERFCOUNTER0_HI = 0x3301 # macro +mmTD_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmTD_PERFCOUNTER1_LO = 0x3302 # macro +mmTD_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmTD_PERFCOUNTER1_HI = 0x3303 # macro +mmTD_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER0_LO = 0x3340 # macro +mmTCP_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER0_HI = 0x3341 # macro +mmTCP_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER1_LO = 0x3342 # macro +mmTCP_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER1_HI = 0x3343 # macro +mmTCP_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER2_LO = 0x3344 # macro +mmTCP_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER2_HI = 0x3345 # macro +mmTCP_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER3_LO = 0x3346 # macro +mmTCP_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER3_HI = 0x3347 # macro +mmTCP_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER0_LO = 0x3380 # macro +mmGL2C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER0_HI = 0x3381 # macro +mmGL2C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER1_LO = 0x3382 # macro +mmGL2C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER1_HI = 0x3383 # macro +mmGL2C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER2_LO = 0x3384 # macro +mmGL2C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER2_HI = 0x3385 # macro +mmGL2C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER3_LO = 0x3386 # macro +mmGL2C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER3_HI = 0x3387 # macro +mmGL2C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER0_LO = 0x3390 # macro +mmGL2A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER0_HI = 0x3391 # macro +mmGL2A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER1_LO = 0x3392 # macro +mmGL2A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER1_HI = 0x3393 # macro +mmGL2A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER2_LO = 0x3394 # macro +mmGL2A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER2_HI = 0x3395 # macro +mmGL2A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER3_LO = 0x3396 # macro +mmGL2A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER3_HI = 0x3397 # macro +mmGL2A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER0_LO = 0x33a0 # macro +mmGL1C_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER0_HI = 0x33a1 # macro +mmGL1C_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER1_LO = 0x33a2 # macro +mmGL1C_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER1_HI = 0x33a3 # macro +mmGL1C_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER2_LO = 0x33a4 # macro +mmGL1C_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER2_HI = 0x33a5 # macro +mmGL1C_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER3_LO = 0x33a6 # macro +mmGL1C_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER3_HI = 0x33a7 # macro +mmGL1C_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER0_LO = 0x33c0 # macro +mmCHC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER0_HI = 0x33c1 # macro +mmCHC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER1_LO = 0x33c2 # macro +mmCHC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER1_HI = 0x33c3 # macro +mmCHC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER2_LO = 0x33c4 # macro +mmCHC_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER2_HI = 0x33c5 # macro +mmCHC_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER3_LO = 0x33c6 # macro +mmCHC_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER3_HI = 0x33c7 # macro +mmCHC_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER0_LO = 0x33c8 # macro +mmCHCG_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER0_HI = 0x33c9 # macro +mmCHCG_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER1_LO = 0x33ca # macro +mmCHCG_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER1_HI = 0x33cb # macro +mmCHCG_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER2_LO = 0x33cc # macro +mmCHCG_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER2_HI = 0x33cd # macro +mmCHCG_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER3_LO = 0x33ce # macro +mmCHCG_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER3_HI = 0x33cf # macro +mmCHCG_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER0_LO = 0x3406 # macro +mmCB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER0_HI = 0x3407 # macro +mmCB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER1_LO = 0x3408 # macro +mmCB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER1_HI = 0x3409 # macro +mmCB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER2_LO = 0x340a # macro +mmCB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER2_HI = 0x340b # macro +mmCB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER3_LO = 0x340c # macro +mmCB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER3_HI = 0x340d # macro +mmCB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER0_LO = 0x3440 # macro +mmDB_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER0_HI = 0x3441 # macro +mmDB_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER1_LO = 0x3442 # macro +mmDB_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER1_HI = 0x3443 # macro +mmDB_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER2_LO = 0x3444 # macro +mmDB_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER2_HI = 0x3445 # macro +mmDB_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER3_LO = 0x3446 # macro +mmDB_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER3_HI = 0x3447 # macro +mmDB_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmRLC_PERFCOUNTER0_LO = 0x3480 # macro +mmRLC_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmRLC_PERFCOUNTER0_HI = 0x3481 # macro +mmRLC_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmRLC_PERFCOUNTER1_LO = 0x3482 # macro +mmRLC_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmRLC_PERFCOUNTER1_HI = 0x3483 # macro +mmRLC_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER0_LO = 0x34c0 # macro +mmRMI_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER0_HI = 0x34c1 # macro +mmRMI_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER1_LO = 0x34c2 # macro +mmRMI_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER1_HI = 0x34c3 # macro +mmRMI_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER2_LO = 0x34c4 # macro +mmRMI_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER2_HI = 0x34c5 # macro +mmRMI_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER3_LO = 0x34c6 # macro +mmRMI_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER3_HI = 0x34c7 # macro +mmRMI_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmUTCL1_PERFCOUNTER0_LO = 0x351c # macro +mmUTCL1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmUTCL1_PERFCOUNTER0_HI = 0x351d # macro +mmUTCL1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmUTCL1_PERFCOUNTER1_LO = 0x351e # macro +mmUTCL1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmUTCL1_PERFCOUNTER1_HI = 0x351f # macro +mmUTCL1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmGCR_PERFCOUNTER0_LO = 0x3520 # macro +mmGCR_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmGCR_PERFCOUNTER0_HI = 0x3521 # macro +mmGCR_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmGCR_PERFCOUNTER1_LO = 0x3522 # macro +mmGCR_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmGCR_PERFCOUNTER1_HI = 0x3523 # macro +mmGCR_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER0_LO = 0x3580 # macro +mmPA_PH_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER0_HI = 0x3581 # macro +mmPA_PH_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER1_LO = 0x3582 # macro +mmPA_PH_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER1_HI = 0x3583 # macro +mmPA_PH_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER2_LO = 0x3584 # macro +mmPA_PH_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER2_HI = 0x3585 # macro +mmPA_PH_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER3_LO = 0x3586 # macro +mmPA_PH_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER3_HI = 0x3587 # macro +mmPA_PH_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER4_LO = 0x3588 # macro +mmPA_PH_PERFCOUNTER4_LO_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER4_HI = 0x3589 # macro +mmPA_PH_PERFCOUNTER4_HI_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER5_LO = 0x358a # macro +mmPA_PH_PERFCOUNTER5_LO_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER5_HI = 0x358b # macro +mmPA_PH_PERFCOUNTER5_HI_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER6_LO = 0x358c # macro +mmPA_PH_PERFCOUNTER6_LO_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER6_HI = 0x358d # macro +mmPA_PH_PERFCOUNTER6_HI_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER7_LO = 0x358e # macro +mmPA_PH_PERFCOUNTER7_LO_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER7_HI = 0x358f # macro +mmPA_PH_PERFCOUNTER7_HI_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER0_LO = 0x35c0 # macro +mmGL1A_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER0_HI = 0x35c1 # macro +mmGL1A_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER1_LO = 0x35c2 # macro +mmGL1A_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER1_HI = 0x35c3 # macro +mmGL1A_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER2_LO = 0x35c4 # macro +mmGL1A_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER2_HI = 0x35c5 # macro +mmGL1A_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER3_LO = 0x35c6 # macro +mmGL1A_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER3_HI = 0x35c7 # macro +mmGL1A_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER0_LO = 0x3600 # macro +mmCHA_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER0_HI = 0x3601 # macro +mmCHA_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER1_LO = 0x3602 # macro +mmCHA_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER1_HI = 0x3603 # macro +mmCHA_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER2_LO = 0x3604 # macro +mmCHA_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER2_HI = 0x3605 # macro +mmCHA_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER3_LO = 0x3606 # macro +mmCHA_PERFCOUNTER3_LO_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER3_HI = 0x3607 # macro +mmCHA_PERFCOUNTER3_HI_BASE_IDX = 1 # macro +mmGUS_PERFCOUNTER2_LO = 0x3640 # macro +mmGUS_PERFCOUNTER2_LO_BASE_IDX = 1 # macro +mmGUS_PERFCOUNTER2_HI = 0x3641 # macro +mmGUS_PERFCOUNTER2_HI_BASE_IDX = 1 # macro +mmGUS_PERFCOUNTER_LO = 0x3642 # macro +mmGUS_PERFCOUNTER_LO_BASE_IDX = 1 # macro +mmGUS_PERFCOUNTER_HI = 0x3643 # macro +mmGUS_PERFCOUNTER_HI_BASE_IDX = 1 # macro +mmGCMC_VM_L2_PERFCOUNTER_LO = 0x34e8 # macro +mmGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX = 1 # macro +mmGCMC_VM_L2_PERFCOUNTER_HI = 0x34e9 # macro +mmGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX = 1 # macro +mmGCUTCL2_PERFCOUNTER_LO = 0x34ea # macro +mmGCUTCL2_PERFCOUNTER_LO_BASE_IDX = 1 # macro +mmGCUTCL2_PERFCOUNTER_HI = 0x34eb # macro +mmGCUTCL2_PERFCOUNTER_HI_BASE_IDX = 1 # macro +mmGCVML2_PERFCOUNTER2_0_LO = 0x34f8 # macro +mmGCVML2_PERFCOUNTER2_0_LO_BASE_IDX = 1 # macro +mmGCVML2_PERFCOUNTER2_1_LO = 0x34f9 # macro +mmGCVML2_PERFCOUNTER2_1_LO_BASE_IDX = 1 # macro +mmGCVML2_PERFCOUNTER2_0_HI = 0x34fa # macro +mmGCVML2_PERFCOUNTER2_0_HI_BASE_IDX = 1 # macro +mmGCVML2_PERFCOUNTER2_1_HI = 0x34fb # macro +mmGCVML2_PERFCOUNTER2_1_HI_BASE_IDX = 1 # macro +mmSDMA0_PERFCNT_PERFCOUNTER_LO = 0x3660 # macro +mmSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro +mmSDMA0_PERFCNT_PERFCOUNTER_HI = 0x3661 # macro +mmSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro +mmSDMA0_PERFCOUNTER0_LO = 0x3662 # macro +mmSDMA0_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmSDMA0_PERFCOUNTER0_HI = 0x3663 # macro +mmSDMA0_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmSDMA0_PERFCOUNTER1_LO = 0x3664 # macro +mmSDMA0_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmSDMA0_PERFCOUNTER1_HI = 0x3665 # macro +mmSDMA0_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmSDMA1_PERFCNT_PERFCOUNTER_LO = 0x366c # macro +mmSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro +mmSDMA1_PERFCNT_PERFCOUNTER_HI = 0x366d # macro +mmSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro +mmSDMA1_PERFCOUNTER0_LO = 0x366e # macro +mmSDMA1_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmSDMA1_PERFCOUNTER0_HI = 0x366f # macro +mmSDMA1_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmSDMA1_PERFCOUNTER1_LO = 0x3670 # macro +mmSDMA1_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmSDMA1_PERFCOUNTER1_HI = 0x3671 # macro +mmSDMA1_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmSDMA2_PERFCNT_PERFCOUNTER_LO = 0x3678 # macro +mmSDMA2_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro +mmSDMA2_PERFCNT_PERFCOUNTER_HI = 0x3679 # macro +mmSDMA2_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro +mmSDMA2_PERFCOUNTER0_LO = 0x367a # macro +mmSDMA2_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmSDMA2_PERFCOUNTER0_HI = 0x367b # macro +mmSDMA2_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmSDMA2_PERFCOUNTER1_LO = 0x367c # macro +mmSDMA2_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmSDMA2_PERFCOUNTER1_HI = 0x367d # macro +mmSDMA2_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmSDMA3_PERFCNT_PERFCOUNTER_LO = 0x3684 # macro +mmSDMA3_PERFCNT_PERFCOUNTER_LO_BASE_IDX = 1 # macro +mmSDMA3_PERFCNT_PERFCOUNTER_HI = 0x3685 # macro +mmSDMA3_PERFCNT_PERFCOUNTER_HI_BASE_IDX = 1 # macro +mmSDMA3_PERFCOUNTER0_LO = 0x3686 # macro +mmSDMA3_PERFCOUNTER0_LO_BASE_IDX = 1 # macro +mmSDMA3_PERFCOUNTER0_HI = 0x3687 # macro +mmSDMA3_PERFCOUNTER0_HI_BASE_IDX = 1 # macro +mmSDMA3_PERFCOUNTER1_LO = 0x3688 # macro +mmSDMA3_PERFCOUNTER1_LO_BASE_IDX = 1 # macro +mmSDMA3_PERFCOUNTER1_HI = 0x3689 # macro +mmSDMA3_PERFCOUNTER1_HI_BASE_IDX = 1 # macro +mmCPG_PERFCOUNTER1_SELECT = 0x3800 # macro +mmCPG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmCPG_PERFCOUNTER0_SELECT1 = 0x3801 # macro +mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmCPG_PERFCOUNTER0_SELECT = 0x3802 # macro +mmCPG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmCPC_PERFCOUNTER1_SELECT = 0x3803 # macro +mmCPC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmCPC_PERFCOUNTER0_SELECT1 = 0x3804 # macro +mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmCPF_PERFCOUNTER1_SELECT = 0x3805 # macro +mmCPF_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmCPF_PERFCOUNTER0_SELECT1 = 0x3806 # macro +mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmCPF_PERFCOUNTER0_SELECT = 0x3807 # macro +mmCPF_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmCP_PERFMON_CNTL = 0x3808 # macro +mmCP_PERFMON_CNTL_BASE_IDX = 1 # macro +mmCPC_PERFCOUNTER0_SELECT = 0x3809 # macro +mmCPC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmCPF_TC_PERF_COUNTER_WINDOW_SELECT = 0x380a # macro +mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro +mmCPG_TC_PERF_COUNTER_WINDOW_SELECT = 0x380b # macro +mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX = 1 # macro +mmCPF_LATENCY_STATS_SELECT = 0x380c # macro +mmCPF_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro +mmCPG_LATENCY_STATS_SELECT = 0x380d # macro +mmCPG_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro +mmCPC_LATENCY_STATS_SELECT = 0x380e # macro +mmCPC_LATENCY_STATS_SELECT_BASE_IDX = 1 # macro +mmCP_DRAW_OBJECT = 0x3810 # macro +mmCP_DRAW_OBJECT_BASE_IDX = 1 # macro +mmCP_DRAW_OBJECT_COUNTER = 0x3811 # macro +mmCP_DRAW_OBJECT_COUNTER_BASE_IDX = 1 # macro +mmCP_DRAW_WINDOW_MASK_HI = 0x3812 # macro +mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX = 1 # macro +mmCP_DRAW_WINDOW_HI = 0x3813 # macro +mmCP_DRAW_WINDOW_HI_BASE_IDX = 1 # macro +mmCP_DRAW_WINDOW_LO = 0x3814 # macro +mmCP_DRAW_WINDOW_LO_BASE_IDX = 1 # macro +mmCP_DRAW_WINDOW_CNTL = 0x3815 # macro +mmCP_DRAW_WINDOW_CNTL_BASE_IDX = 1 # macro +mmGRBM_PERFCOUNTER0_SELECT = 0x3840 # macro +mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmGRBM_PERFCOUNTER1_SELECT = 0x3841 # macro +mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmGRBM_SE0_PERFCOUNTER_SELECT = 0x3842 # macro +mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +mmGRBM_SE1_PERFCOUNTER_SELECT = 0x3843 # macro +mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +mmGRBM_SE2_PERFCOUNTER_SELECT = 0x3844 # macro +mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +mmGRBM_SE3_PERFCOUNTER_SELECT = 0x3845 # macro +mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX = 1 # macro +mmGRBM_PERFCOUNTER0_SELECT_HI = 0x384d # macro +mmGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX = 1 # macro +mmGRBM_PERFCOUNTER1_SELECT_HI = 0x384e # macro +mmGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER0_SELECT = 0x38a4 # macro +mmGE1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER0_SELECT1 = 0x38a5 # macro +mmGE1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER1_SELECT = 0x38a6 # macro +mmGE1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER1_SELECT1 = 0x38a7 # macro +mmGE1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER2_SELECT = 0x38a8 # macro +mmGE1_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER2_SELECT1 = 0x38a9 # macro +mmGE1_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER3_SELECT = 0x38aa # macro +mmGE1_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmGE1_PERFCOUNTER3_SELECT1 = 0x38ab # macro +mmGE1_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER0_SELECT = 0x38ac # macro +mmGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER0_SELECT1 = 0x38ad # macro +mmGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER1_SELECT = 0x38ae # macro +mmGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER1_SELECT1 = 0x38af # macro +mmGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER2_SELECT = 0x38b0 # macro +mmGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER2_SELECT1 = 0x38b1 # macro +mmGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER3_SELECT = 0x38b2 # macro +mmGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmGE2_DIST_PERFCOUNTER3_SELECT1 = 0x38b3 # macro +mmGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER0_SELECT = 0x38b4 # macro +mmGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER0_SELECT1 = 0x38b5 # macro +mmGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER1_SELECT = 0x38b6 # macro +mmGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER1_SELECT1 = 0x38b7 # macro +mmGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER2_SELECT = 0x38b8 # macro +mmGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER2_SELECT1 = 0x38b9 # macro +mmGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER3_SELECT = 0x38ba # macro +mmGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmGE2_SE_PERFCOUNTER3_SELECT1 = 0x38bb # macro +mmGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER0_SELECT = 0x3900 # macro +mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER0_SELECT1 = 0x3901 # macro +mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER1_SELECT = 0x3902 # macro +mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER1_SELECT1 = 0x3903 # macro +mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER2_SELECT = 0x3904 # macro +mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER2_SELECT1 = 0x3905 # macro +mmPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER3_SELECT = 0x3906 # macro +mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmPA_SU_PERFCOUNTER3_SELECT1 = 0x3907 # macro +mmPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER0_SELECT = 0x3940 # macro +mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER0_SELECT1 = 0x3941 # macro +mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER1_SELECT = 0x3942 # macro +mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER2_SELECT = 0x3943 # macro +mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER3_SELECT = 0x3944 # macro +mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER4_SELECT = 0x3945 # macro +mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER5_SELECT = 0x3946 # macro +mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER6_SELECT = 0x3947 # macro +mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro +mmPA_SC_PERFCOUNTER7_SELECT = 0x3948 # macro +mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER0_SELECT = 0x3980 # macro +mmSPI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER1_SELECT = 0x3981 # macro +mmSPI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER2_SELECT = 0x3982 # macro +mmSPI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER3_SELECT = 0x3983 # macro +mmSPI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER0_SELECT1 = 0x3984 # macro +mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER1_SELECT1 = 0x3985 # macro +mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER2_SELECT1 = 0x3986 # macro +mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER3_SELECT1 = 0x3987 # macro +mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER4_SELECT = 0x3988 # macro +mmSPI_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER5_SELECT = 0x3989 # macro +mmSPI_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro +mmSPI_PERFCOUNTER_BINS = 0x398a # macro +mmSPI_PERFCOUNTER_BINS_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER0_SELECT = 0x39c0 # macro +mmSQ_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER1_SELECT = 0x39c1 # macro +mmSQ_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER2_SELECT = 0x39c2 # macro +mmSQ_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER3_SELECT = 0x39c3 # macro +mmSQ_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER4_SELECT = 0x39c4 # macro +mmSQ_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER5_SELECT = 0x39c5 # macro +mmSQ_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER6_SELECT = 0x39c6 # macro +mmSQ_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER7_SELECT = 0x39c7 # macro +mmSQ_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER8_SELECT = 0x39c8 # macro +mmSQ_PERFCOUNTER8_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER9_SELECT = 0x39c9 # macro +mmSQ_PERFCOUNTER9_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER10_SELECT = 0x39ca # macro +mmSQ_PERFCOUNTER10_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER11_SELECT = 0x39cb # macro +mmSQ_PERFCOUNTER11_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER12_SELECT = 0x39cc # macro +mmSQ_PERFCOUNTER12_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER13_SELECT = 0x39cd # macro +mmSQ_PERFCOUNTER13_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER14_SELECT = 0x39ce # macro +mmSQ_PERFCOUNTER14_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER15_SELECT = 0x39cf # macro +mmSQ_PERFCOUNTER15_SELECT_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER_CTRL = 0x39e0 # macro +mmSQ_PERFCOUNTER_CTRL_BASE_IDX = 1 # macro +mmSQ_PERFCOUNTER_CTRL2 = 0x39e2 # macro +mmSQ_PERFCOUNTER_CTRL2_BASE_IDX = 1 # macro +mmGCEA_PERFCOUNTER2_SELECT = 0x3a00 # macro +mmGCEA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmGCEA_PERFCOUNTER2_SELECT1 = 0x3a01 # macro +mmGCEA_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +mmGCEA_PERFCOUNTER2_MODE = 0x3a02 # macro +mmGCEA_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro +mmGCEA_PERFCOUNTER0_CFG = 0x3a03 # macro +mmGCEA_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +mmGCEA_PERFCOUNTER1_CFG = 0x3a04 # macro +mmGCEA_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +mmGCEA_PERFCOUNTER_RSLT_CNTL = 0x3a05 # macro +mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER0_SELECT = 0x3a40 # macro +mmSX_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER1_SELECT = 0x3a41 # macro +mmSX_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER2_SELECT = 0x3a42 # macro +mmSX_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER3_SELECT = 0x3a43 # macro +mmSX_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER0_SELECT1 = 0x3a44 # macro +mmSX_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmSX_PERFCOUNTER1_SELECT1 = 0x3a45 # macro +mmSX_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER0_SELECT = 0x3a80 # macro +mmGDS_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER1_SELECT = 0x3a81 # macro +mmGDS_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER2_SELECT = 0x3a82 # macro +mmGDS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER3_SELECT = 0x3a83 # macro +mmGDS_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER0_SELECT1 = 0x3a84 # macro +mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER1_SELECT1 = 0x3a85 # macro +mmGDS_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER2_SELECT1 = 0x3a86 # macro +mmGDS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +mmGDS_PERFCOUNTER3_SELECT1 = 0x3a87 # macro +mmGDS_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +mmTA_PERFCOUNTER0_SELECT = 0x3ac0 # macro +mmTA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmTA_PERFCOUNTER0_SELECT1 = 0x3ac1 # macro +mmTA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmTA_PERFCOUNTER1_SELECT = 0x3ac2 # macro +mmTA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmTD_PERFCOUNTER0_SELECT = 0x3b00 # macro +mmTD_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmTD_PERFCOUNTER0_SELECT1 = 0x3b01 # macro +mmTD_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmTD_PERFCOUNTER1_SELECT = 0x3b02 # macro +mmTD_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER0_SELECT = 0x3b40 # macro +mmTCP_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER0_SELECT1 = 0x3b41 # macro +mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER1_SELECT = 0x3b42 # macro +mmTCP_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER1_SELECT1 = 0x3b43 # macro +mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER2_SELECT = 0x3b44 # macro +mmTCP_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmTCP_PERFCOUNTER3_SELECT = 0x3b45 # macro +mmTCP_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER0_SELECT = 0x3b80 # macro +mmGL2C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER0_SELECT1 = 0x3b81 # macro +mmGL2C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER1_SELECT = 0x3b82 # macro +mmGL2C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER1_SELECT1 = 0x3b83 # macro +mmGL2C_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER2_SELECT = 0x3b84 # macro +mmGL2C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmGL2C_PERFCOUNTER3_SELECT = 0x3b85 # macro +mmGL2C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER0_SELECT = 0x3b90 # macro +mmGL2A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER0_SELECT1 = 0x3b91 # macro +mmGL2A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER1_SELECT = 0x3b92 # macro +mmGL2A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER1_SELECT1 = 0x3b93 # macro +mmGL2A_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER2_SELECT = 0x3b94 # macro +mmGL2A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmGL2A_PERFCOUNTER3_SELECT = 0x3b95 # macro +mmGL2A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER0_SELECT = 0x3ba0 # macro +mmGL1C_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER0_SELECT1 = 0x3ba1 # macro +mmGL1C_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER1_SELECT = 0x3ba2 # macro +mmGL1C_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER2_SELECT = 0x3ba3 # macro +mmGL1C_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmGL1C_PERFCOUNTER3_SELECT = 0x3ba4 # macro +mmGL1C_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER0_SELECT = 0x3bc0 # macro +mmCHC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER0_SELECT1 = 0x3bc1 # macro +mmCHC_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER1_SELECT = 0x3bc2 # macro +mmCHC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER2_SELECT = 0x3bc3 # macro +mmCHC_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmCHC_PERFCOUNTER3_SELECT = 0x3bc4 # macro +mmCHC_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER0_SELECT = 0x3bc6 # macro +mmCHCG_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER0_SELECT1 = 0x3bc7 # macro +mmCHCG_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER1_SELECT = 0x3bc8 # macro +mmCHCG_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER2_SELECT = 0x3bc9 # macro +mmCHCG_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmCHCG_PERFCOUNTER3_SELECT = 0x3bca # macro +mmCHCG_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER_FILTER = 0x3c00 # macro +mmCB_PERFCOUNTER_FILTER_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER0_SELECT = 0x3c01 # macro +mmCB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER0_SELECT1 = 0x3c02 # macro +mmCB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER1_SELECT = 0x3c03 # macro +mmCB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER2_SELECT = 0x3c04 # macro +mmCB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmCB_PERFCOUNTER3_SELECT = 0x3c05 # macro +mmCB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER0_SELECT = 0x3c40 # macro +mmDB_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER0_SELECT1 = 0x3c41 # macro +mmDB_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER1_SELECT = 0x3c42 # macro +mmDB_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER1_SELECT1 = 0x3c43 # macro +mmDB_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER2_SELECT = 0x3c44 # macro +mmDB_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmDB_PERFCOUNTER3_SELECT = 0x3c46 # macro +mmDB_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmRLC_SPM_PERFMON_CNTL = 0x3c80 # macro +mmRLC_SPM_PERFMON_CNTL_BASE_IDX = 1 # macro +mmRLC_SPM_PERFMON_RING_BASE_LO = 0x3c81 # macro +mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX = 1 # macro +mmRLC_SPM_PERFMON_RING_BASE_HI = 0x3c82 # macro +mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX = 1 # macro +mmRLC_SPM_PERFMON_RING_SIZE = 0x3c83 # macro +mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX = 1 # macro +mmRLC_SPM_PERFMON_SEGMENT_SIZE = 0x3c84 # macro +mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX = 1 # macro +mmRLC_SPM_RING_RDPTR = 0x3c85 # macro +mmRLC_SPM_RING_RDPTR_BASE_IDX = 1 # macro +mmRLC_SPM_SEGMENT_THRESHOLD = 0x3c86 # macro +mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX = 1 # macro +mmRLC_SPM_SE_MUXSEL_ADDR = 0x3c87 # macro +mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX = 1 # macro +mmRLC_SPM_SE_MUXSEL_DATA = 0x3c88 # macro +mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX = 1 # macro +mmRLC_SPM_GLOBAL_MUXSEL_ADDR = 0x3c89 # macro +mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX = 1 # macro +mmRLC_SPM_GLOBAL_MUXSEL_DATA = 0x3c8a # macro +mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX = 1 # macro +mmRLC_SPM_DESER_START_SKEW = 0x3c8b # macro +mmRLC_SPM_DESER_START_SKEW_BASE_IDX = 1 # macro +mmRLC_SPM_GLOBALS_SAMPLE_SKEW = 0x3c8c # macro +mmRLC_SPM_GLOBALS_SAMPLE_SKEW_BASE_IDX = 1 # macro +mmRLC_SPM_GLOBALS_MUXSEL_SKEW = 0x3c8d # macro +mmRLC_SPM_GLOBALS_MUXSEL_SKEW_BASE_IDX = 1 # macro +mmRLC_SPM_SE_SAMPLE_SKEW = 0x3c8e # macro +mmRLC_SPM_SE_SAMPLE_SKEW_BASE_IDX = 1 # macro +mmRLC_SPM_SE_MUXSEL_SKEW = 0x3c8f # macro +mmRLC_SPM_SE_MUXSEL_SKEW_BASE_IDX = 1 # macro +mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR = 0x3c90 # macro +mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR_BASE_IDX = 1 # macro +mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA = 0x3c91 # macro +mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA_BASE_IDX = 1 # macro +mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR = 0x3c92 # macro +mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR_BASE_IDX = 1 # macro +mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA = 0x3c93 # macro +mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA_BASE_IDX = 1 # macro +mmRLC_SPM_RING_WRPTR = 0x3c94 # macro +mmRLC_SPM_RING_WRPTR_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_DATARAM_ADDR = 0x3c95 # macro +mmRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_DATARAM_DATA = 0x3c96 # macro +mmRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_CTRLRAM_ADDR = 0x3c97 # macro +mmRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_CTRLRAM_DATA = 0x3c98 # macro +mmRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_STATUS = 0x3c99 # macro +mmRLC_SPM_ACCUM_STATUS_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_CTRL = 0x3c9a # macro +mmRLC_SPM_ACCUM_CTRL_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_MODE = 0x3c9b # macro +mmRLC_SPM_ACCUM_MODE_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_THRESHOLD = 0x3c9c # macro +mmRLC_SPM_ACCUM_THRESHOLD_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_SAMPLES_REQUESTED = 0x3c9d # macro +mmRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_DATARAM_WRCOUNT = 0x3c9e # macro +mmRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX = 1 # macro +mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE = 0x3c9f # macro +mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE_BASE_IDX = 1 # macro +mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE = 0x3ca0 # macro +mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE_BASE_IDX = 1 # macro +mmRLC_SPM_VIRT_CTRL = 0x3ca1 # macro +mmRLC_SPM_VIRT_CTRL_BASE_IDX = 1 # macro +mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE = 0x3ca2 # macro +mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE_BASE_IDX = 1 # macro +mmRLC_SPM_VIRT_STATUS = 0x3ca3 # macro +mmRLC_SPM_VIRT_STATUS_BASE_IDX = 1 # macro +mmRLC_SPM_GFXCLOCK_HIGHCOUNT = 0x3ca4 # macro +mmRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX = 1 # macro +mmRLC_SPM_GFXCLOCK_LOWCOUNT = 0x3ca5 # macro +mmRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX = 1 # macro +mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE = 0x3ca6 # macro +mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE_BASE_IDX = 1 # macro +mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET = 0x3ca7 # macro +mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET_BASE_IDX = 1 # macro +mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET = 0x3ca8 # macro +mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR = 0x3ca9 # macro +mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_SWA_DATARAM_DATA = 0x3caa # macro +mmRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET = 0x3cab # macro +mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX = 1 # macro +mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE = 0x3cac # macro +mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE_BASE_IDX = 1 # macro +mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS = 0x3cad # macro +mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX = 1 # macro +mmRLC_PERFMON_CNTL = 0x3cc0 # macro +mmRLC_PERFMON_CNTL_BASE_IDX = 1 # macro +mmRLC_PERFCOUNTER0_SELECT = 0x3cc1 # macro +mmRLC_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmRLC_PERFCOUNTER1_SELECT = 0x3cc2 # macro +mmRLC_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_PERF_CNT_CNTL = 0x3cc3 # macro +mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_PERF_CNT_WR_ADDR = 0x3cc4 # macro +mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_PERF_CNT_WR_DATA = 0x3cc5 # macro +mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_PERF_CNT_RD_ADDR = 0x3cc6 # macro +mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_PERF_CNT_RD_DATA = 0x3cc7 # macro +mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX = 1 # macro +mmRLC_PERFMON_CLK_CNTL = 0x3ce4 # macro +mmRLC_PERFMON_CLK_CNTL_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER0_SELECT = 0x3d00 # macro +mmRMI_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER0_SELECT1 = 0x3d01 # macro +mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER1_SELECT = 0x3d02 # macro +mmRMI_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER2_SELECT = 0x3d03 # macro +mmRMI_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER2_SELECT1 = 0x3d04 # macro +mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +mmRMI_PERFCOUNTER3_SELECT = 0x3d05 # macro +mmRMI_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmRMI_PERF_COUNTER_CNTL = 0x3d06 # macro +mmRMI_PERF_COUNTER_CNTL_BASE_IDX = 1 # macro +mmGCR_PERFCOUNTER0_SELECT = 0x3d60 # macro +mmGCR_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmGCR_PERFCOUNTER0_SELECT1 = 0x3d61 # macro +mmGCR_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmGCR_PERFCOUNTER1_SELECT = 0x3d62 # macro +mmGCR_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmUTCL1_PERFCOUNTER0_SELECT = 0x3d63 # macro +mmUTCL1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmUTCL1_PERFCOUNTER1_SELECT = 0x3d64 # macro +mmUTCL1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER0_SELECT = 0x3d80 # macro +mmPA_PH_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER0_SELECT1 = 0x3d81 # macro +mmPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER1_SELECT = 0x3d82 # macro +mmPA_PH_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER2_SELECT = 0x3d83 # macro +mmPA_PH_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER3_SELECT = 0x3d84 # macro +mmPA_PH_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER4_SELECT = 0x3d85 # macro +mmPA_PH_PERFCOUNTER4_SELECT_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER5_SELECT = 0x3d86 # macro +mmPA_PH_PERFCOUNTER5_SELECT_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER6_SELECT = 0x3d87 # macro +mmPA_PH_PERFCOUNTER6_SELECT_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER7_SELECT = 0x3d88 # macro +mmPA_PH_PERFCOUNTER7_SELECT_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER1_SELECT1 = 0x3d90 # macro +mmPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER2_SELECT1 = 0x3d91 # macro +mmPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +mmPA_PH_PERFCOUNTER3_SELECT1 = 0x3d92 # macro +mmPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER0_SELECT = 0x3dc0 # macro +mmGL1A_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER0_SELECT1 = 0x3dc1 # macro +mmGL1A_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER1_SELECT = 0x3dc2 # macro +mmGL1A_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER2_SELECT = 0x3dc3 # macro +mmGL1A_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmGL1A_PERFCOUNTER3_SELECT = 0x3dc4 # macro +mmGL1A_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER0_SELECT = 0x3de0 # macro +mmCHA_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER0_SELECT1 = 0x3de1 # macro +mmCHA_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER1_SELECT = 0x3de2 # macro +mmCHA_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER2_SELECT = 0x3de3 # macro +mmCHA_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmCHA_PERFCOUNTER3_SELECT = 0x3de4 # macro +mmCHA_PERFCOUNTER3_SELECT_BASE_IDX = 1 # macro +mmGUS_PERFCOUNTER2_SELECT = 0x3e00 # macro +mmGUS_PERFCOUNTER2_SELECT_BASE_IDX = 1 # macro +mmGUS_PERFCOUNTER2_SELECT1 = 0x3e01 # macro +mmGUS_PERFCOUNTER2_SELECT1_BASE_IDX = 1 # macro +mmGUS_PERFCOUNTER2_MODE = 0x3e02 # macro +mmGUS_PERFCOUNTER2_MODE_BASE_IDX = 1 # macro +mmGUS_PERFCOUNTER0_CFG = 0x3e03 # macro +mmGUS_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +mmGUS_PERFCOUNTER1_CFG = 0x3e04 # macro +mmGUS_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +mmGUS_PERFCOUNTER_RSLT_CNTL = 0x3e05 # macro +mmGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +mmGCMC_VM_L2_PERFCOUNTER0_CFG = 0x3d2c # macro +mmGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +mmGCMC_VM_L2_PERFCOUNTER1_CFG = 0x3d2d # macro +mmGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +mmGCMC_VM_L2_PERFCOUNTER2_CFG = 0x3d2e # macro +mmGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro +mmGCMC_VM_L2_PERFCOUNTER3_CFG = 0x3d2f # macro +mmGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro +mmGCMC_VM_L2_PERFCOUNTER4_CFG = 0x3d30 # macro +mmGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX = 1 # macro +mmGCMC_VM_L2_PERFCOUNTER5_CFG = 0x3d31 # macro +mmGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX = 1 # macro +mmGCMC_VM_L2_PERFCOUNTER6_CFG = 0x3d32 # macro +mmGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX = 1 # macro +mmGCMC_VM_L2_PERFCOUNTER7_CFG = 0x3d33 # macro +mmGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX = 1 # macro +mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL = 0x3d34 # macro +mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +mmGCUTCL2_PERFCOUNTER0_CFG = 0x3d35 # macro +mmGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +mmGCUTCL2_PERFCOUNTER1_CFG = 0x3d36 # macro +mmGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +mmGCUTCL2_PERFCOUNTER2_CFG = 0x3d37 # macro +mmGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX = 1 # macro +mmGCUTCL2_PERFCOUNTER3_CFG = 0x3d38 # macro +mmGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX = 1 # macro +mmGCUTCL2_PERFCOUNTER_RSLT_CNTL = 0x3d39 # macro +mmGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +mmGCVML2_PERFCOUNTER2_0_SELECT = 0x3d3c # macro +mmGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX = 1 # macro +mmGCVML2_PERFCOUNTER2_1_SELECT = 0x3d3d # macro +mmGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX = 1 # macro +mmGCVML2_PERFCOUNTER2_0_SELECT1 = 0x3d3e # macro +mmGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX = 1 # macro +mmGCVML2_PERFCOUNTER2_1_SELECT1 = 0x3d3f # macro +mmGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX = 1 # macro +mmGCVML2_PERFCOUNTER2_0_MODE = 0x3d40 # macro +mmGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX = 1 # macro +mmGCVML2_PERFCOUNTER2_1_MODE = 0x3d41 # macro +mmGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX = 1 # macro +mmSDMA0_PERFCNT_PERFCOUNTER0_CFG = 0x3e20 # macro +mmSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +mmSDMA0_PERFCNT_PERFCOUNTER1_CFG = 0x3e21 # macro +mmSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e22 # macro +mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +mmSDMA0_PERFCNT_MISC_CNTL = 0x3e23 # macro +mmSDMA0_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro +mmSDMA0_PERFCOUNTER0_SELECT = 0x3e24 # macro +mmSDMA0_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmSDMA0_PERFCOUNTER0_SELECT1 = 0x3e25 # macro +mmSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmSDMA0_PERFCOUNTER1_SELECT = 0x3e26 # macro +mmSDMA0_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmSDMA0_PERFCOUNTER1_SELECT1 = 0x3e27 # macro +mmSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmSDMA1_PERFCNT_PERFCOUNTER0_CFG = 0x3e2c # macro +mmSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +mmSDMA1_PERFCNT_PERFCOUNTER1_CFG = 0x3e2d # macro +mmSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e2e # macro +mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +mmSDMA1_PERFCNT_MISC_CNTL = 0x3e2f # macro +mmSDMA1_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro +mmSDMA1_PERFCOUNTER0_SELECT = 0x3e30 # macro +mmSDMA1_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmSDMA1_PERFCOUNTER0_SELECT1 = 0x3e31 # macro +mmSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmSDMA1_PERFCOUNTER1_SELECT = 0x3e32 # macro +mmSDMA1_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmSDMA1_PERFCOUNTER1_SELECT1 = 0x3e33 # macro +mmSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmSDMA2_PERFCNT_PERFCOUNTER0_CFG = 0x3e38 # macro +mmSDMA2_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +mmSDMA2_PERFCNT_PERFCOUNTER1_CFG = 0x3e39 # macro +mmSDMA2_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e3a # macro +mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +mmSDMA2_PERFCNT_MISC_CNTL = 0x3e3b # macro +mmSDMA2_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro +mmSDMA2_PERFCOUNTER0_SELECT = 0x3e3c # macro +mmSDMA2_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmSDMA2_PERFCOUNTER0_SELECT1 = 0x3e3d # macro +mmSDMA2_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmSDMA2_PERFCOUNTER1_SELECT = 0x3e3e # macro +mmSDMA2_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmSDMA2_PERFCOUNTER1_SELECT1 = 0x3e3f # macro +mmSDMA2_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmSDMA3_PERFCNT_PERFCOUNTER0_CFG = 0x3e44 # macro +mmSDMA3_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX = 1 # macro +mmSDMA3_PERFCNT_PERFCOUNTER1_CFG = 0x3e45 # macro +mmSDMA3_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX = 1 # macro +mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL = 0x3e46 # macro +mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX = 1 # macro +mmSDMA3_PERFCNT_MISC_CNTL = 0x3e47 # macro +mmSDMA3_PERFCNT_MISC_CNTL_BASE_IDX = 1 # macro +mmSDMA3_PERFCOUNTER0_SELECT = 0x3e48 # macro +mmSDMA3_PERFCOUNTER0_SELECT_BASE_IDX = 1 # macro +mmSDMA3_PERFCOUNTER0_SELECT1 = 0x3e49 # macro +mmSDMA3_PERFCOUNTER0_SELECT1_BASE_IDX = 1 # macro +mmSDMA3_PERFCOUNTER1_SELECT = 0x3e4a # macro +mmSDMA3_PERFCOUNTER1_SELECT_BASE_IDX = 1 # macro +mmSDMA3_PERFCOUNTER1_SELECT1 = 0x3e4b # macro +mmSDMA3_PERFCOUNTER1_SELECT1_BASE_IDX = 1 # macro +mmGRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro +mmGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro +mmRTAVFS_RTAVFS_REG_ADDR = 0x4b00 # macro +mmRTAVFS_RTAVFS_REG_ADDR_BASE_IDX = 1 # macro +mmGRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro +mmGRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro +mmRTAVFS_RTAVFS_WR_DATA = 0x4b01 # macro +mmRTAVFS_RTAVFS_WR_DATA_BASE_IDX = 1 # macro +mmGRTAVFS_GENERAL_0 = 0x4b02 # macro +mmGRTAVFS_GENERAL_0_BASE_IDX = 1 # macro +mmGRTAVFS_RTAVFS_RD_DATA = 0x4b03 # macro +mmGRTAVFS_RTAVFS_RD_DATA_BASE_IDX = 1 # macro +mmGRTAVFS_RTAVFS_REG_CTRL = 0x4b04 # macro +mmGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX = 1 # macro +mmGRTAVFS_RTAVFS_REG_STATUS = 0x4b05 # macro +mmGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX = 1 # macro +mmGRTAVFS_TARG_FREQ = 0x4b06 # macro +mmGRTAVFS_TARG_FREQ_BASE_IDX = 1 # macro +mmGRTAVFS_TARG_VOLT = 0x4b07 # macro +mmGRTAVFS_TARG_VOLT_BASE_IDX = 1 # macro +mmGRTAVFS_SOFT_RESET = 0x4b0f # macro +mmGRTAVFS_SOFT_RESET_BASE_IDX = 1 # macro +mmGRTAVFS_PSM_CNTL = 0x4b10 # macro +mmGRTAVFS_PSM_CNTL_BASE_IDX = 1 # macro +mmGRTAVFS_CLK_CNTL = 0x4b11 # macro +mmGRTAVFS_CLK_CNTL_BASE_IDX = 1 # macro +mmRLC_CNTL = 0x4c00 # macro +mmRLC_CNTL_BASE_IDX = 1 # macro +mmRLC_F32_UCODE_VERSION = 0x4c03 # macro +mmRLC_F32_UCODE_VERSION_BASE_IDX = 1 # macro +mmRLC_STAT = 0x4c04 # macro +mmRLC_STAT_BASE_IDX = 1 # macro +mmRLC_MEM_SLP_CNTL = 0x4c06 # macro +mmRLC_MEM_SLP_CNTL_BASE_IDX = 1 # macro +mmSMU_RLC_RESPONSE = 0x4c07 # macro +mmSMU_RLC_RESPONSE_BASE_IDX = 1 # macro +mmRLC_RLCV_SAFE_MODE = 0x4c08 # macro +mmRLC_RLCV_SAFE_MODE_BASE_IDX = 1 # macro +mmRLC_SMU_SAFE_MODE = 0x4c09 # macro +mmRLC_SMU_SAFE_MODE_BASE_IDX = 1 # macro +mmRLC_RLCV_COMMAND = 0x4c0a # macro +mmRLC_RLCV_COMMAND_BASE_IDX = 1 # macro +mmRLC_REFCLOCK_TIMESTAMP_LSB = 0x4c0c # macro +mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX = 1 # macro +mmRLC_REFCLOCK_TIMESTAMP_MSB = 0x4c0d # macro +mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX = 1 # macro +mmRLC_GPM_TIMER_INT_0 = 0x4c0e # macro +mmRLC_GPM_TIMER_INT_0_BASE_IDX = 1 # macro +mmRLC_GPM_TIMER_INT_1 = 0x4c0f # macro +mmRLC_GPM_TIMER_INT_1_BASE_IDX = 1 # macro +mmRLC_GPM_TIMER_INT_2 = 0x4c10 # macro +mmRLC_GPM_TIMER_INT_2_BASE_IDX = 1 # macro +mmRLC_GPM_TIMER_CTRL = 0x4c11 # macro +mmRLC_GPM_TIMER_CTRL_BASE_IDX = 1 # macro +mmRLC_LB_CNTR_MAX_1 = 0x4c12 # macro +mmRLC_LB_CNTR_MAX_1_BASE_IDX = 1 # macro +mmRLC_GPM_TIMER_STAT = 0x4c13 # macro +mmRLC_GPM_TIMER_STAT_BASE_IDX = 1 # macro +mmRLC_GPM_TIMER_INT_3 = 0x4c15 # macro +mmRLC_GPM_TIMER_INT_3_BASE_IDX = 1 # macro +mmRLC_GPM_LEGACY_INT_STAT = 0x4c16 # macro +mmRLC_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro +mmRLC_GPM_LEGACY_INT_CLEAR = 0x4c17 # macro +mmRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX = 1 # macro +mmRLC_INT_STAT = 0x4c18 # macro +mmRLC_INT_STAT_BASE_IDX = 1 # macro +mmRLC_LB_CNTL = 0x4c19 # macro +mmRLC_LB_CNTL_BASE_IDX = 1 # macro +mmRLC_MGCG_CTRL = 0x4c1a # macro +mmRLC_MGCG_CTRL_BASE_IDX = 1 # macro +mmRLC_LB_CNTR_INIT_1 = 0x4c1b # macro +mmRLC_LB_CNTR_INIT_1_BASE_IDX = 1 # macro +mmRLC_LB_CNTR_1 = 0x4c1c # macro +mmRLC_LB_CNTR_1_BASE_IDX = 1 # macro +mmRLC_JUMP_TABLE_RESTORE = 0x4c1e # macro +mmRLC_JUMP_TABLE_RESTORE_BASE_IDX = 1 # macro +mmRLC_PG_DELAY_2 = 0x4c1f # macro +mmRLC_PG_DELAY_2_BASE_IDX = 1 # macro +mmRLC_GPU_CLOCK_COUNT_LSB = 0x4c24 # macro +mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX = 1 # macro +mmRLC_GPU_CLOCK_COUNT_MSB = 0x4c25 # macro +mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX = 1 # macro +mmRLC_CAPTURE_GPU_CLOCK_COUNT = 0x4c26 # macro +mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX = 1 # macro +mmRLC_UCODE_CNTL = 0x4c27 # macro +mmRLC_UCODE_CNTL_BASE_IDX = 1 # macro +mmRLC_GPM_THREAD_RESET = 0x4c28 # macro +mmRLC_GPM_THREAD_RESET_BASE_IDX = 1 # macro +mmRLC_GPM_CP_DMA_COMPLETE_T0 = 0x4c29 # macro +mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX = 1 # macro +mmRLC_GPM_CP_DMA_COMPLETE_T1 = 0x4c2a # macro +mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX = 1 # macro +mmRLC_LB_CNTR_INIT_2 = 0x4c2b # macro +mmRLC_LB_CNTR_INIT_2_BASE_IDX = 1 # macro +mmRLC_LB_CNTR_MAX_2 = 0x4c2c # macro +mmRLC_LB_CNTR_MAX_2_BASE_IDX = 1 # macro +mmRLC_LB_CONFIG_5 = 0x4c2e # macro +mmRLC_LB_CONFIG_5_BASE_IDX = 1 # macro +mmRLC_GPM_TIMER_INT_4 = 0x4c2f # macro +mmRLC_GPM_TIMER_INT_4_BASE_IDX = 1 # macro +mmRLC_CLK_COUNT_GFXCLK_LSB = 0x4c30 # macro +mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX = 1 # macro +mmRLC_CLK_COUNT_GFXCLK_MSB = 0x4c31 # macro +mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX = 1 # macro +mmRLC_CLK_COUNT_REFCLK_LSB = 0x4c32 # macro +mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX = 1 # macro +mmRLC_CLK_COUNT_REFCLK_MSB = 0x4c33 # macro +mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX = 1 # macro +mmRLC_CLK_COUNT_CTRL = 0x4c34 # macro +mmRLC_CLK_COUNT_CTRL_BASE_IDX = 1 # macro +mmRLC_CLK_COUNT_STAT = 0x4c35 # macro +mmRLC_CLK_COUNT_STAT_BASE_IDX = 1 # macro +mmRLC_RLCG_DOORBELL_CNTL = 0x4c36 # macro +mmRLC_RLCG_DOORBELL_CNTL_BASE_IDX = 1 # macro +mmRLC_RLCG_DOORBELL_STAT = 0x4c37 # macro +mmRLC_RLCG_DOORBELL_STAT_BASE_IDX = 1 # macro +mmRLC_RLCG_DOORBELL_0_DATA_LO = 0x4c38 # macro +mmRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro +mmRLC_RLCG_DOORBELL_0_DATA_HI = 0x4c39 # macro +mmRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro +mmRLC_RLCG_DOORBELL_1_DATA_LO = 0x4c3a # macro +mmRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro +mmRLC_RLCG_DOORBELL_1_DATA_HI = 0x4c3b # macro +mmRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro +mmRLC_RLCG_DOORBELL_2_DATA_LO = 0x4c3c # macro +mmRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro +mmRLC_RLCG_DOORBELL_2_DATA_HI = 0x4c3d # macro +mmRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro +mmRLC_RLCG_DOORBELL_3_DATA_LO = 0x4c3e # macro +mmRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro +mmRLC_RLCG_DOORBELL_3_DATA_HI = 0x4c3f # macro +mmRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro +mmRLC_GPU_CLOCK_32_RES_SEL = 0x4c41 # macro +mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX = 1 # macro +mmRLC_GPU_CLOCK_32 = 0x4c42 # macro +mmRLC_GPU_CLOCK_32_BASE_IDX = 1 # macro +mmRLC_PG_CNTL = 0x4c43 # macro +mmRLC_PG_CNTL_BASE_IDX = 1 # macro +mmRLC_GPM_THREAD_PRIORITY = 0x4c44 # macro +mmRLC_GPM_THREAD_PRIORITY_BASE_IDX = 1 # macro +mmRLC_GPM_THREAD_ENABLE = 0x4c45 # macro +mmRLC_GPM_THREAD_ENABLE_BASE_IDX = 1 # macro +mmRLC_RLCG_DOORBELL_RANGE = 0x4c47 # macro +mmRLC_RLCG_DOORBELL_RANGE_BASE_IDX = 1 # macro +mmRLC_CGTT_MGCG_OVERRIDE = 0x4c48 # macro +mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX = 1 # macro +mmRLC_CGCG_CGLS_CTRL = 0x4c49 # macro +mmRLC_CGCG_CGLS_CTRL_BASE_IDX = 1 # macro +mmRLC_CGCG_RAMP_CTRL = 0x4c4a # macro +mmRLC_CGCG_RAMP_CTRL_BASE_IDX = 1 # macro +mmRLC_DYN_PG_STATUS = 0x4c4b # macro +mmRLC_DYN_PG_STATUS_BASE_IDX = 1 # macro +mmRLC_DYN_PG_REQUEST = 0x4c4c # macro +mmRLC_DYN_PG_REQUEST_BASE_IDX = 1 # macro +mmRLC_PG_DELAY = 0x4c4d # macro +mmRLC_PG_DELAY_BASE_IDX = 1 # macro +mmRLC_WGP_STATUS = 0x4c4e # macro +mmRLC_WGP_STATUS_BASE_IDX = 1 # macro +mmRLC_LB_INIT_WGP_MASK = 0x4c4f # macro +mmRLC_LB_INIT_WGP_MASK_BASE_IDX = 1 # macro +mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK = 0x4c50 # macro +mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK_BASE_IDX = 1 # macro +mmRLC_LB_PARAMS = 0x4c51 # macro +mmRLC_LB_PARAMS_BASE_IDX = 1 # macro +mmRLC_LB_DELAY = 0x4c52 # macro +mmRLC_LB_DELAY_BASE_IDX = 1 # macro +mmRLC_PG_ALWAYS_ON_WGP_MASK = 0x4c53 # macro +mmRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX = 1 # macro +mmRLC_MAX_PG_WGP = 0x4c54 # macro +mmRLC_MAX_PG_WGP_BASE_IDX = 1 # macro +mmRLC_AUTO_PG_CTRL = 0x4c55 # macro +mmRLC_AUTO_PG_CTRL_BASE_IDX = 1 # macro +mmRLC_SMU_GRBM_REG_SAVE_CTRL = 0x4c56 # macro +mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX = 1 # macro +mmRLC_SERDES_RD_INDEX = 0x4c59 # macro +mmRLC_SERDES_RD_INDEX_BASE_IDX = 1 # macro +mmRLC_SERDES_RD_DATA_0 = 0x4c5a # macro +mmRLC_SERDES_RD_DATA_0_BASE_IDX = 1 # macro +mmRLC_SERDES_RD_DATA_1 = 0x4c5b # macro +mmRLC_SERDES_RD_DATA_1_BASE_IDX = 1 # macro +mmRLC_SERDES_RD_DATA_2 = 0x4c5c # macro +mmRLC_SERDES_RD_DATA_2_BASE_IDX = 1 # macro +mmRLC_SERDES_RD_DATA_3 = 0x4c5d # macro +mmRLC_SERDES_RD_DATA_3_BASE_IDX = 1 # macro +mmRLC_SERDES_MASK = 0x4c5e # macro +mmRLC_SERDES_MASK_BASE_IDX = 1 # macro +mmRLC_SERDES_CTRL = 0x4c5f # macro +mmRLC_SERDES_CTRL_BASE_IDX = 1 # macro +mmRLC_SERDES_DATA = 0x4c60 # macro +mmRLC_SERDES_DATA_BASE_IDX = 1 # macro +mmRLC_SERDES_BUSY = 0x4c61 # macro +mmRLC_SERDES_BUSY_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_0 = 0x4c63 # macro +mmRLC_GPM_GENERAL_0_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_1 = 0x4c64 # macro +mmRLC_GPM_GENERAL_1_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_2 = 0x4c65 # macro +mmRLC_GPM_GENERAL_2_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_3 = 0x4c66 # macro +mmRLC_GPM_GENERAL_3_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_4 = 0x4c67 # macro +mmRLC_GPM_GENERAL_4_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_5 = 0x4c68 # macro +mmRLC_GPM_GENERAL_5_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_6 = 0x4c69 # macro +mmRLC_GPM_GENERAL_6_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_7 = 0x4c6a # macro +mmRLC_GPM_GENERAL_7_BASE_IDX = 1 # macro +mmRLC_STATIC_PG_STATUS = 0x4c6e # macro +mmRLC_STATIC_PG_STATUS_BASE_IDX = 1 # macro +mmRLC_SPM_INT_INFO_1 = 0x4c6f # macro +mmRLC_SPM_INT_INFO_1_BASE_IDX = 1 # macro +mmRLC_SPM_INT_INFO_2 = 0x4c70 # macro +mmRLC_SPM_INT_INFO_2_BASE_IDX = 1 # macro +mmRLC_SPM_MC_CNTL = 0x4c71 # macro +mmRLC_SPM_MC_CNTL_BASE_IDX = 1 # macro +mmRLC_SPM_INT_CNTL = 0x4c72 # macro +mmRLC_SPM_INT_CNTL_BASE_IDX = 1 # macro +mmRLC_SPM_INT_STATUS = 0x4c73 # macro +mmRLC_SPM_INT_STATUS_BASE_IDX = 1 # macro +mmRLC_SMU_MESSAGE = 0x4c76 # macro +mmRLC_SMU_MESSAGE_BASE_IDX = 1 # macro +mmRLC_GPM_LOG_SIZE = 0x4c77 # macro +mmRLC_GPM_LOG_SIZE_BASE_IDX = 1 # macro +mmRLC_PG_DELAY_3 = 0x4c78 # macro +mmRLC_PG_DELAY_3_BASE_IDX = 1 # macro +mmRLC_GPR_REG1 = 0x4c79 # macro +mmRLC_GPR_REG1_BASE_IDX = 1 # macro +mmRLC_GPR_REG2 = 0x4c7a # macro +mmRLC_GPR_REG2_BASE_IDX = 1 # macro +mmRLC_GPM_LOG_CONT = 0x4c7b # macro +mmRLC_GPM_LOG_CONT_BASE_IDX = 1 # macro +mmRLC_GPM_INT_DISABLE_TH0 = 0x4c7c # macro +mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX = 1 # macro +mmRLC_GPM_LEGACY_INT_DISABLE = 0x4c7d # macro +mmRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro +mmRLC_GPM_INT_FORCE_TH0 = 0x4c7e # macro +mmRLC_GPM_INT_FORCE_TH0_BASE_IDX = 1 # macro +mmRLC_SRM_CNTL = 0x4c80 # macro +mmRLC_SRM_CNTL_BASE_IDX = 1 # macro +mmRLC_SRM_GPM_COMMAND = 0x4c87 # macro +mmRLC_SRM_GPM_COMMAND_BASE_IDX = 1 # macro +mmRLC_SRM_GPM_COMMAND_STATUS = 0x4c88 # macro +mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX = 1 # macro +mmRLC_SRM_RLCV_COMMAND = 0x4c89 # macro +mmRLC_SRM_RLCV_COMMAND_BASE_IDX = 1 # macro +mmRLC_SRM_RLCV_COMMAND_STATUS = 0x4c8a # macro +mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_ADDR_0 = 0x4c8b # macro +mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_ADDR_1 = 0x4c8c # macro +mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_ADDR_2 = 0x4c8d # macro +mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_ADDR_3 = 0x4c8e # macro +mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_ADDR_4 = 0x4c8f # macro +mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_ADDR_5 = 0x4c90 # macro +mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_ADDR_6 = 0x4c91 # macro +mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_ADDR_7 = 0x4c92 # macro +mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_DATA_0 = 0x4c93 # macro +mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_DATA_1 = 0x4c94 # macro +mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_DATA_2 = 0x4c95 # macro +mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_DATA_3 = 0x4c96 # macro +mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_DATA_4 = 0x4c97 # macro +mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_DATA_5 = 0x4c98 # macro +mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_DATA_6 = 0x4c99 # macro +mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX = 1 # macro +mmRLC_SRM_INDEX_CNTL_DATA_7 = 0x4c9a # macro +mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX = 1 # macro +mmRLC_SRM_STAT = 0x4c9b # macro +mmRLC_SRM_STAT_BASE_IDX = 1 # macro +mmRLC_SRM_GPM_ABORT = 0x4c9c # macro +mmRLC_SRM_GPM_ABORT_BASE_IDX = 1 # macro +mmRLC_SPARE_INT_2 = 0x4c9d # macro +mmRLC_SPARE_INT_2_BASE_IDX = 1 # macro +mmRLC_RLCV_SPARE_INT_1 = 0x4c9e # macro +mmRLC_RLCV_SPARE_INT_1_BASE_IDX = 1 # macro +mmRLC_PACE_SPARE_INT_1 = 0x4c9f # macro +mmRLC_PACE_SPARE_INT_1_BASE_IDX = 1 # macro +mmRLC_SAFE_MODE = 0x4ca0 # macro +mmRLC_SAFE_MODE_BASE_IDX = 1 # macro +mmRLC_CP_SCHEDULERS = 0x4ca1 # macro +mmRLC_CP_SCHEDULERS_BASE_IDX = 1 # macro +mmRLC_CSIB_ADDR_LO = 0x4ca2 # macro +mmRLC_CSIB_ADDR_LO_BASE_IDX = 1 # macro +mmRLC_CSIB_ADDR_HI = 0x4ca3 # macro +mmRLC_CSIB_ADDR_HI_BASE_IDX = 1 # macro +mmRLC_CSIB_LENGTH = 0x4ca4 # macro +mmRLC_CSIB_LENGTH_BASE_IDX = 1 # macro +mmRLC_SPARE_INT_0 = 0x4ca5 # macro +mmRLC_SPARE_INT_0_BASE_IDX = 1 # macro +mmRLC_CP_EOF_INT_CNT = 0x4ca6 # macro +mmRLC_CP_EOF_INT_CNT_BASE_IDX = 1 # macro +mmRLC_CP_EOF_INT = 0x4ca7 # macro +mmRLC_CP_EOF_INT_BASE_IDX = 1 # macro +mmRLC_SMU_COMMAND = 0x4ca9 # macro +mmRLC_SMU_COMMAND_BASE_IDX = 1 # macro +mmRLC_SMU_ARGUMENT_1 = 0x4cab # macro +mmRLC_SMU_ARGUMENT_1_BASE_IDX = 1 # macro +mmRLC_SMU_ARGUMENT_2 = 0x4cac # macro +mmRLC_SMU_ARGUMENT_2_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_8 = 0x4cad # macro +mmRLC_GPM_GENERAL_8_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_9 = 0x4cae # macro +mmRLC_GPM_GENERAL_9_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_10 = 0x4caf # macro +mmRLC_GPM_GENERAL_10_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_11 = 0x4cb0 # macro +mmRLC_GPM_GENERAL_11_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_12 = 0x4cb1 # macro +mmRLC_GPM_GENERAL_12_BASE_IDX = 1 # macro +mmRLC_GPM_UTCL1_CNTL_0 = 0x4cb2 # macro +mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX = 1 # macro +mmRLC_GPM_UTCL1_CNTL_1 = 0x4cb3 # macro +mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX = 1 # macro +mmRLC_GPM_UTCL1_CNTL_2 = 0x4cb4 # macro +mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX = 1 # macro +mmRLC_SPM_UTCL1_CNTL = 0x4cb5 # macro +mmRLC_SPM_UTCL1_CNTL_BASE_IDX = 1 # macro +mmRLC_UTCL1_STATUS_2 = 0x4cb6 # macro +mmRLC_UTCL1_STATUS_2_BASE_IDX = 1 # macro +mmRLC_LB_CONFIG_2 = 0x4cb8 # macro +mmRLC_LB_CONFIG_2_BASE_IDX = 1 # macro +mmRLC_LB_CONFIG_3 = 0x4cb9 # macro +mmRLC_LB_CONFIG_3_BASE_IDX = 1 # macro +mmRLC_LB_CONFIG_4 = 0x4cba # macro +mmRLC_LB_CONFIG_4_BASE_IDX = 1 # macro +mmRLC_SPM_UTCL1_ERROR_1 = 0x4cbc # macro +mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX = 1 # macro +mmRLC_SPM_UTCL1_ERROR_2 = 0x4cbd # macro +mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX = 1 # macro +mmRLC_GPM_UTCL1_TH0_ERROR_1 = 0x4cbe # macro +mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX = 1 # macro +mmRLC_LB_CONFIG_1 = 0x4cbf # macro +mmRLC_LB_CONFIG_1_BASE_IDX = 1 # macro +mmRLC_GPM_UTCL1_TH0_ERROR_2 = 0x4cc0 # macro +mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX = 1 # macro +mmRLC_GPM_UTCL1_TH1_ERROR_1 = 0x4cc1 # macro +mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX = 1 # macro +mmRLC_GPM_UTCL1_TH1_ERROR_2 = 0x4cc2 # macro +mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX = 1 # macro +mmRLC_GPM_UTCL1_TH2_ERROR_1 = 0x4cc3 # macro +mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX = 1 # macro +mmRLC_GPM_UTCL1_TH2_ERROR_2 = 0x4cc4 # macro +mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX = 1 # macro +mmRLC_CGCG_CGLS_CTRL_3D = 0x4cc5 # macro +mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX = 1 # macro +mmRLC_CGCG_RAMP_CTRL_3D = 0x4cc6 # macro +mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX = 1 # macro +mmRLC_SEMAPHORE_0 = 0x4cc7 # macro +mmRLC_SEMAPHORE_0_BASE_IDX = 1 # macro +mmRLC_SEMAPHORE_1 = 0x4cc8 # macro +mmRLC_SEMAPHORE_1_BASE_IDX = 1 # macro +mmRLC_PACE_INT_STAT = 0x4ccc # macro +mmRLC_PACE_INT_STAT_BASE_IDX = 1 # macro +mmRLC_PREWALKER_UTCL1_CNTL = 0x4ccd # macro +mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX = 1 # macro +mmRLC_PREWALKER_UTCL1_TRIG = 0x4cce # macro +mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX = 1 # macro +mmRLC_PREWALKER_UTCL1_ADDR_LSB = 0x4ccf # macro +mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX = 1 # macro +mmRLC_PREWALKER_UTCL1_ADDR_MSB = 0x4cd0 # macro +mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX = 1 # macro +mmRLC_PREWALKER_UTCL1_SIZE_LSB = 0x4cd1 # macro +mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX = 1 # macro +mmRLC_PREWALKER_UTCL1_SIZE_MSB = 0x4cd2 # macro +mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX = 1 # macro +mmRLC_UTCL1_STATUS = 0x4cd4 # macro +mmRLC_UTCL1_STATUS_BASE_IDX = 1 # macro +mmRLC_R2I_CNTL_0 = 0x4cd5 # macro +mmRLC_R2I_CNTL_0_BASE_IDX = 1 # macro +mmRLC_R2I_CNTL_1 = 0x4cd6 # macro +mmRLC_R2I_CNTL_1_BASE_IDX = 1 # macro +mmRLC_R2I_CNTL_2 = 0x4cd7 # macro +mmRLC_R2I_CNTL_2_BASE_IDX = 1 # macro +mmRLC_R2I_CNTL_3 = 0x4cd8 # macro +mmRLC_R2I_CNTL_3_BASE_IDX = 1 # macro +mmRLC_LB_WGP_STAT = 0x4cda # macro +mmRLC_LB_WGP_STAT_BASE_IDX = 1 # macro +mmRLC_GPM_INT_STAT_TH0 = 0x4cdc # macro +mmRLC_GPM_INT_STAT_TH0_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_13 = 0x4cdd # macro +mmRLC_GPM_GENERAL_13_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_14 = 0x4cde # macro +mmRLC_GPM_GENERAL_14_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_15 = 0x4cdf # macro +mmRLC_GPM_GENERAL_15_BASE_IDX = 1 # macro +mmRLC_SPARE_INT_1 = 0x4ce0 # macro +mmRLC_SPARE_INT_1_BASE_IDX = 1 # macro +mmRLC_SEMAPHORE_2 = 0x4ce3 # macro +mmRLC_SEMAPHORE_2_BASE_IDX = 1 # macro +mmRLC_SEMAPHORE_3 = 0x4ce4 # macro +mmRLC_SEMAPHORE_3_BASE_IDX = 1 # macro +mmRLC_SMU_ARGUMENT_3 = 0x4ce5 # macro +mmRLC_SMU_ARGUMENT_3_BASE_IDX = 1 # macro +mmRLC_SMU_ARGUMENT_4 = 0x4ce6 # macro +mmRLC_SMU_ARGUMENT_4_BASE_IDX = 1 # macro +mmRLC_GPU_CLOCK_COUNT_LSB_1 = 0x4ce8 # macro +mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX = 1 # macro +mmRLC_GPU_CLOCK_COUNT_MSB_1 = 0x4ce9 # macro +mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX = 1 # macro +mmRLC_CAPTURE_GPU_CLOCK_COUNT_1 = 0x4cea # macro +mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX = 1 # macro +mmRLC_GPU_CLOCK_COUNT_LSB_2 = 0x4ceb # macro +mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX = 1 # macro +mmRLC_GPU_CLOCK_COUNT_MSB_2 = 0x4cec # macro +mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX = 1 # macro +mmRLC_PACE_INT_DISABLE = 0x4ced # macro +mmRLC_PACE_INT_DISABLE_BASE_IDX = 1 # macro +mmRLC_CAPTURE_GPU_CLOCK_COUNT_2 = 0x4cef # macro +mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX = 1 # macro +mmRLC_RLCV_DOORBELL_RANGE = 0x4cf0 # macro +mmRLC_RLCV_DOORBELL_RANGE_BASE_IDX = 1 # macro +mmRLC_RLCV_DOORBELL_CNTL = 0x4cf1 # macro +mmRLC_RLCV_DOORBELL_CNTL_BASE_IDX = 1 # macro +mmRLC_RLCV_DOORBELL_STAT = 0x4cf2 # macro +mmRLC_RLCV_DOORBELL_STAT_BASE_IDX = 1 # macro +mmRLC_RLCV_DOORBELL_0_DATA_LO = 0x4cf3 # macro +mmRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro +mmRLC_RLCV_DOORBELL_0_DATA_HI = 0x4cf4 # macro +mmRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro +mmRLC_RLCV_DOORBELL_1_DATA_LO = 0x4cf5 # macro +mmRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro +mmRLC_RLCV_DOORBELL_1_DATA_HI = 0x4cf6 # macro +mmRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro +mmRLC_RLCV_DOORBELL_2_DATA_LO = 0x4cf7 # macro +mmRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro +mmRLC_RLCV_DOORBELL_2_DATA_HI = 0x4cf8 # macro +mmRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro +mmRLC_RLCV_DOORBELL_3_DATA_LO = 0x4cf9 # macro +mmRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro +mmRLC_RLCV_DOORBELL_3_DATA_HI = 0x4cfa # macro +mmRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro +mmRLC_RLCV_SPARE_INT = 0x4d00 # macro +mmRLC_RLCV_SPARE_INT_BASE_IDX = 1 # macro +mmRLC_PACE_TIMER_INT_0 = 0x4d04 # macro +mmRLC_PACE_TIMER_INT_0_BASE_IDX = 1 # macro +mmRLC_PACE_TIMER_CTRL = 0x4d05 # macro +mmRLC_PACE_TIMER_CTRL_BASE_IDX = 1 # macro +mmRLC_PACE_TIMER_INT_1 = 0x4d06 # macro +mmRLC_PACE_TIMER_INT_1_BASE_IDX = 1 # macro +mmRLC_PACE_SPARE_INT = 0x4d07 # macro +mmRLC_PACE_SPARE_INT_BASE_IDX = 1 # macro +mmRLC_SMU_CLK_REQ = 0x4d08 # macro +mmRLC_SMU_CLK_REQ_BASE_IDX = 1 # macro +mmRLC_CP_STAT_INVAL_STAT = 0x4d09 # macro +mmRLC_CP_STAT_INVAL_STAT_BASE_IDX = 1 # macro +mmRLC_CP_STAT_INVAL_CTRL = 0x4d0a # macro +mmRLC_CP_STAT_INVAL_CTRL_BASE_IDX = 1 # macro +mmRLC_CLK_STATUS = 0x4d0b # macro +mmRLC_CLK_STATUS_BASE_IDX = 1 # macro +mmRLC_SPP_CTRL = 0x4d0c # macro +mmRLC_SPP_CTRL_BASE_IDX = 1 # macro +mmRLC_SPP_SHADER_PROFILE_EN = 0x4d0d # macro +mmRLC_SPP_SHADER_PROFILE_EN_BASE_IDX = 1 # macro +mmRLC_SPP_SSF_CAPTURE_EN = 0x4d0e # macro +mmRLC_SPP_SSF_CAPTURE_EN_BASE_IDX = 1 # macro +mmRLC_SPP_SSF_THRESHOLD_0 = 0x4d0f # macro +mmRLC_SPP_SSF_THRESHOLD_0_BASE_IDX = 1 # macro +mmRLC_SPP_SSF_THRESHOLD_1 = 0x4d10 # macro +mmRLC_SPP_SSF_THRESHOLD_1_BASE_IDX = 1 # macro +mmRLC_SPP_SSF_THRESHOLD_2 = 0x4d11 # macro +mmRLC_SPP_SSF_THRESHOLD_2_BASE_IDX = 1 # macro +mmRLC_SPP_INFLIGHT_RD_ADDR = 0x4d12 # macro +mmRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX = 1 # macro +mmRLC_SPP_INFLIGHT_RD_DATA = 0x4d13 # macro +mmRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX = 1 # macro +mmRLC_GPM_GENERAL_16 = 0x4d14 # macro +mmRLC_GPM_GENERAL_16_BASE_IDX = 1 # macro +mmRLC_SPP_PROF_INFO_1 = 0x4d18 # macro +mmRLC_SPP_PROF_INFO_1_BASE_IDX = 1 # macro +mmRLC_SPP_PROF_INFO_2 = 0x4d19 # macro +mmRLC_SPP_PROF_INFO_2_BASE_IDX = 1 # macro +mmRLC_SPP_GLOBAL_SH_ID = 0x4d1a # macro +mmRLC_SPP_GLOBAL_SH_ID_BASE_IDX = 1 # macro +mmRLC_SPP_GLOBAL_SH_ID_VALID = 0x4d1b # macro +mmRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX = 1 # macro +mmRLC_SPP_STATUS = 0x4d1c # macro +mmRLC_SPP_STATUS_BASE_IDX = 1 # macro +mmRLC_SPP_PVT_STAT_0 = 0x4d1d # macro +mmRLC_SPP_PVT_STAT_0_BASE_IDX = 1 # macro +mmRLC_SPP_PVT_STAT_1 = 0x4d1e # macro +mmRLC_SPP_PVT_STAT_1_BASE_IDX = 1 # macro +mmRLC_SPP_PVT_STAT_2 = 0x4d1f # macro +mmRLC_SPP_PVT_STAT_2_BASE_IDX = 1 # macro +mmRLC_SPP_PVT_STAT_3 = 0x4d20 # macro +mmRLC_SPP_PVT_STAT_3_BASE_IDX = 1 # macro +mmRLC_SPP_PVT_LEVEL_MAX = 0x4d21 # macro +mmRLC_SPP_PVT_LEVEL_MAX_BASE_IDX = 1 # macro +mmRLC_SPP_STALL_STATE_UPDATE = 0x4d22 # macro +mmRLC_SPP_STALL_STATE_UPDATE_BASE_IDX = 1 # macro +mmRLC_SPP_PBB_INFO = 0x4d23 # macro +mmRLC_SPP_PBB_INFO_BASE_IDX = 1 # macro +mmRLC_SPP_RESET = 0x4d24 # macro +mmRLC_SPP_RESET_BASE_IDX = 1 # macro +mmRLC_SPM_SAMPLE_CNT = 0x4d25 # macro +mmRLC_SPM_SAMPLE_CNT_BASE_IDX = 1 # macro +mmRLC_RLCP_DOORBELL_RANGE = 0x4d26 # macro +mmRLC_RLCP_DOORBELL_RANGE_BASE_IDX = 1 # macro +mmRLC_RLCP_DOORBELL_CNTL = 0x4d27 # macro +mmRLC_RLCP_DOORBELL_CNTL_BASE_IDX = 1 # macro +mmRLC_RLCP_DOORBELL_STAT = 0x4d28 # macro +mmRLC_RLCP_DOORBELL_STAT_BASE_IDX = 1 # macro +mmRLC_RLCP_DOORBELL_0_DATA_LO = 0x4d29 # macro +mmRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro +mmRLC_RLCP_DOORBELL_0_DATA_HI = 0x4d2a # macro +mmRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro +mmRLC_RLCP_DOORBELL_1_DATA_LO = 0x4d2b # macro +mmRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro +mmRLC_RLCP_DOORBELL_1_DATA_HI = 0x4d2c # macro +mmRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro +mmRLC_RLCP_DOORBELL_2_DATA_LO = 0x4d2d # macro +mmRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro +mmRLC_RLCP_DOORBELL_2_DATA_HI = 0x4d2e # macro +mmRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro +mmRLC_RLCP_DOORBELL_3_DATA_LO = 0x4d2f # macro +mmRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro +mmRLC_RLCP_DOORBELL_3_DATA_HI = 0x4d30 # macro +mmRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro +mmRLC_PCC_STRETCH_HYSTERESIS_CNTL = 0x4d44 # macro +mmRLC_PCC_STRETCH_HYSTERESIS_CNTL_BASE_IDX = 1 # macro +mmRLC_CAC_MASK_CNTL = 0x4d45 # macro +mmRLC_CAC_MASK_CNTL_BASE_IDX = 1 # macro +mmRLC_GPU_CLOCK_COUNT_SPM_LSB = 0x4de4 # macro +mmRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX = 1 # macro +mmRLC_GPU_CLOCK_COUNT_SPM_MSB = 0x4de5 # macro +mmRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX = 1 # macro +mmRLC_SPM_THREAD_TRACE_CTRL = 0x4de6 # macro +mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX = 1 # macro +mmRLC_LB_CNTR_2 = 0x4de7 # macro +mmRLC_LB_CNTR_2_BASE_IDX = 1 # macro +mmRLC_CPAXI_DOORBELL_MON_CTRL = 0x4df1 # macro +mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX = 1 # macro +mmRLC_CPAXI_DOORBELL_MON_STAT = 0x4df2 # macro +mmRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX = 1 # macro +mmRLC_CPAXI_DOORBELL_MON_DATA_LSB = 0x4df3 # macro +mmRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX = 1 # macro +mmRLC_CPAXI_DOORBELL_MON_DATA_MSB = 0x4df4 # macro +mmRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX = 1 # macro +mmRLC_XT_DOORBELL_RANGE = 0x4df5 # macro +mmRLC_XT_DOORBELL_RANGE_BASE_IDX = 1 # macro +mmRLC_XT_DOORBELL_CNTL = 0x4df6 # macro +mmRLC_XT_DOORBELL_CNTL_BASE_IDX = 1 # macro +mmRLC_XT_DOORBELL_STAT = 0x4df7 # macro +mmRLC_XT_DOORBELL_STAT_BASE_IDX = 1 # macro +mmRLC_XT_DOORBELL_0_DATA_LO = 0x4df8 # macro +mmRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX = 1 # macro +mmRLC_XT_DOORBELL_0_DATA_HI = 0x4df9 # macro +mmRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX = 1 # macro +mmRLC_XT_DOORBELL_1_DATA_LO = 0x4dfa # macro +mmRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX = 1 # macro +mmRLC_XT_DOORBELL_1_DATA_HI = 0x4dfb # macro +mmRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX = 1 # macro +mmRLC_XT_DOORBELL_2_DATA_LO = 0x4dfc # macro +mmRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX = 1 # macro +mmRLC_XT_DOORBELL_2_DATA_HI = 0x4dfd # macro +mmRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX = 1 # macro +mmRLC_XT_DOORBELL_3_DATA_LO = 0x4dfe # macro +mmRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX = 1 # macro +mmRLC_XT_DOORBELL_3_DATA_HI = 0x4dff # macro +mmRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX = 1 # macro +mmRLC_SPP_CAM_ADDR = 0x4e00 # macro +mmRLC_SPP_CAM_ADDR_BASE_IDX = 1 # macro +mmRLC_SPP_CAM_DATA = 0x4e01 # macro +mmRLC_SPP_CAM_DATA_BASE_IDX = 1 # macro +mmRLC_SPP_CAM_EXT_ADDR = 0x4e02 # macro +mmRLC_SPP_CAM_EXT_ADDR_BASE_IDX = 1 # macro +mmRLC_SPP_CAM_EXT_DATA = 0x4e03 # macro +mmRLC_SPP_CAM_EXT_DATA_BASE_IDX = 1 # macro +mmRLC_PACE_SCRATCH_ADDR = 0x4e04 # macro +mmRLC_PACE_SCRATCH_ADDR_BASE_IDX = 1 # macro +mmRLC_PACE_SCRATCH_DATA = 0x4e05 # macro +mmRLC_PACE_SCRATCH_DATA_BASE_IDX = 1 # macro +mmRLC_RLCS_DEC_START = 0x4e60 # macro +mmRLC_RLCS_DEC_START_BASE_IDX = 1 # macro +mmRLC_RLCS_DEC_DUMP_ADDR = 0x4e61 # macro +mmRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX = 1 # macro +mmRLC_RLCS_EXCEPTION_REG_1 = 0x4e62 # macro +mmRLC_RLCS_EXCEPTION_REG_1_BASE_IDX = 1 # macro +mmRLC_RLCS_EXCEPTION_REG_2 = 0x4e63 # macro +mmRLC_RLCS_EXCEPTION_REG_2_BASE_IDX = 1 # macro +mmRLC_RLCS_EXCEPTION_REG_3 = 0x4e64 # macro +mmRLC_RLCS_EXCEPTION_REG_3_BASE_IDX = 1 # macro +mmRLC_RLCS_EXCEPTION_REG_4 = 0x4e65 # macro +mmRLC_RLCS_EXCEPTION_REG_4_BASE_IDX = 1 # macro +mmRLC_RLCS_GENERAL_6 = 0x4e66 # macro +mmRLC_RLCS_GENERAL_6_BASE_IDX = 1 # macro +mmRLC_RLCS_GENERAL_7 = 0x4e67 # macro +mmRLC_RLCS_GENERAL_7_BASE_IDX = 1 # macro +mmRLC_RLCS_CGCG_REQUEST = 0x4e68 # macro +mmRLC_RLCS_CGCG_REQUEST_BASE_IDX = 1 # macro +mmRLC_RLCS_CGCG_STATUS = 0x4e69 # macro +mmRLC_RLCS_CGCG_STATUS_BASE_IDX = 1 # macro +mmRLC_RLCS_SMU_GFXCLK_STATUS = 0x4e6a # macro +mmRLC_RLCS_SMU_GFXCLK_STATUS_BASE_IDX = 1 # macro +mmRLC_RLCS_SMU_GFXCLK_CONTROL = 0x4e6b # macro +mmRLC_RLCS_SMU_GFXCLK_CONTROL_BASE_IDX = 1 # macro +mmRLC_RLCS_SOC_DS_CNTL = 0x4e6c # macro +mmRLC_RLCS_SOC_DS_CNTL_BASE_IDX = 1 # macro +mmRLC_RLCS_GFX_DS_CNTL = 0x4e6d # macro +mmRLC_RLCS_GFX_DS_CNTL_BASE_IDX = 1 # macro +mmRLC_GPM_STAT = 0x4e6e # macro +mmRLC_GPM_STAT_BASE_IDX = 1 # macro +mmRLC_RLCS_GPM_STAT = 0x4e6e # macro +mmRLC_RLCS_GPM_STAT_BASE_IDX = 1 # macro +mmRLC_RLCS_ABORTED_PD_SEQUENCE = 0x4e6f # macro +mmRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX = 1 # macro +mmRLC_RLCS_DIDT_FORCE_STALL = 0x4e70 # macro +mmRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX = 1 # macro +mmRLC_RLCS_IOV_CMD_STATUS = 0x4e71 # macro +mmRLC_RLCS_IOV_CMD_STATUS_BASE_IDX = 1 # macro +mmRLC_RLCS_IOV_CNTX_LOC_SIZE = 0x4e72 # macro +mmRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX = 1 # macro +mmRLC_RLCS_IOV_SCH_BLOCK = 0x4e73 # macro +mmRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX = 1 # macro +mmRLC_RLCS_IOV_VM_BUSY_STATUS = 0x4e74 # macro +mmRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_RLCS_GPM_STAT_2 = 0x4e75 # macro +mmRLC_RLCS_GPM_STAT_2_BASE_IDX = 1 # macro +mmRLC_RLCS_GRBM_SOFT_RESET = 0x4e76 # macro +mmRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX = 1 # macro +mmRLC_RLCS_PG_CHANGE_STATUS = 0x4e77 # macro +mmRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX = 1 # macro +mmRLC_RLCS_PG_CHANGE_READ = 0x4e78 # macro +mmRLC_RLCS_PG_CHANGE_READ_BASE_IDX = 1 # macro +mmRLC_RLCS_LB_STATUS = 0x4e79 # macro +mmRLC_RLCS_LB_STATUS_BASE_IDX = 1 # macro +mmRLC_RLCS_LB_READ = 0x4e7a # macro +mmRLC_RLCS_LB_READ_BASE_IDX = 1 # macro +mmRLC_RLCS_LB_CONTROL = 0x4e7b # macro +mmRLC_RLCS_LB_CONTROL_BASE_IDX = 1 # macro +mmRLC_RLCS_IH_SEMAPHORE = 0x4e7c # macro +mmRLC_RLCS_IH_SEMAPHORE_BASE_IDX = 1 # macro +mmRLC_RLCS_IH_COOKIE_SEMAPHORE = 0x4e7d # macro +mmRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX = 1 # macro +mmRLC_RLCS_IH_CTRL_1 = 0x4e7e # macro +mmRLC_RLCS_IH_CTRL_1_BASE_IDX = 1 # macro +mmRLC_RLCS_IH_CTRL_2 = 0x4e7f # macro +mmRLC_RLCS_IH_CTRL_2_BASE_IDX = 1 # macro +mmRLC_RLCS_IH_CTRL_3 = 0x4e80 # macro +mmRLC_RLCS_IH_CTRL_3_BASE_IDX = 1 # macro +mmRLC_RLCS_IH_STATUS = 0x4e81 # macro +mmRLC_RLCS_IH_STATUS_BASE_IDX = 1 # macro +mmRLC_RLCS_WGP_STATUS = 0x4e82 # macro +mmRLC_RLCS_WGP_STATUS_BASE_IDX = 1 # macro +mmRLC_RLCS_WGP_READ = 0x4e83 # macro +mmRLC_RLCS_WGP_READ_BASE_IDX = 1 # macro +mmRLC_RLCS_CP_INT_CTRL_1 = 0x4e84 # macro +mmRLC_RLCS_CP_INT_CTRL_1_BASE_IDX = 1 # macro +mmRLC_RLCS_CP_INT_CTRL_2 = 0x4e85 # macro +mmRLC_RLCS_CP_INT_CTRL_2_BASE_IDX = 1 # macro +mmRLC_RLCS_CP_INT_INFO_1 = 0x4e86 # macro +mmRLC_RLCS_CP_INT_INFO_1_BASE_IDX = 1 # macro +mmRLC_RLCS_CP_INT_INFO_2 = 0x4e87 # macro +mmRLC_RLCS_CP_INT_INFO_2_BASE_IDX = 1 # macro +mmRLC_RLCS_SPM_INT_CTRL = 0x4e88 # macro +mmRLC_RLCS_SPM_INT_CTRL_BASE_IDX = 1 # macro +mmRLC_RLCS_SPM_INT_INFO_1 = 0x4e89 # macro +mmRLC_RLCS_SPM_INT_INFO_1_BASE_IDX = 1 # macro +mmRLC_RLCS_SPM_INT_INFO_2 = 0x4e8a # macro +mmRLC_RLCS_SPM_INT_INFO_2_BASE_IDX = 1 # macro +mmRLC_RLCS_DSM_TRIG = 0x4e8b # macro +mmRLC_RLCS_DSM_TRIG_BASE_IDX = 1 # macro +mmRLC_RLCS_BOOTLOAD_STATUS = 0x4e8d # macro +mmRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX = 1 # macro +mmRLC_RLCS_POWER_BRAKE_CNTL = 0x4e8e # macro +mmRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX = 1 # macro +mmRLC_RLCS_GENERAL_0 = 0x4e8f # macro +mmRLC_RLCS_GENERAL_0_BASE_IDX = 1 # macro +mmRLC_RLCS_GENERAL_1 = 0x4e90 # macro +mmRLC_RLCS_GENERAL_1_BASE_IDX = 1 # macro +mmRLC_RLCS_GENERAL_2 = 0x4e91 # macro +mmRLC_RLCS_GENERAL_2_BASE_IDX = 1 # macro +mmRLC_RLCS_GENERAL_3 = 0x4e92 # macro +mmRLC_RLCS_GENERAL_3_BASE_IDX = 1 # macro +mmRLC_RLCS_GENERAL_4 = 0x4e93 # macro +mmRLC_RLCS_GENERAL_4_BASE_IDX = 1 # macro +mmRLC_RLCS_GENERAL_5 = 0x4e94 # macro +mmRLC_RLCS_GENERAL_5_BASE_IDX = 1 # macro +mmRLC_RLCS_GRBM_IDLE_BUSY_STAT = 0x4ec1 # macro +mmRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX = 1 # macro +mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL = 0x4ec2 # macro +mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX = 1 # macro +mmRLC_RLCS_CMP_IDLE_CNTL = 0x4ec3 # macro +mmRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX = 1 # macro +mmRLC_RLCS_POWER_BRAKE_CNTL_TH1 = 0x4ec4 # macro +mmRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX = 1 # macro +mmRLC_RLCS_AUXILIARY_REG_1 = 0x4ec5 # macro +mmRLC_RLCS_AUXILIARY_REG_1_BASE_IDX = 1 # macro +mmRLC_RLCS_AUXILIARY_REG_2 = 0x4ec6 # macro +mmRLC_RLCS_AUXILIARY_REG_2_BASE_IDX = 1 # macro +mmRLC_RLCS_AUXILIARY_REG_3 = 0x4ec7 # macro +mmRLC_RLCS_AUXILIARY_REG_3_BASE_IDX = 1 # macro +mmRLC_RLCS_AUXILIARY_REG_4 = 0x4ec8 # macro +mmRLC_RLCS_AUXILIARY_REG_4_BASE_IDX = 1 # macro +mmRLC_RLCS_SPM_SQTT_MODE = 0x4ee0 # macro +mmRLC_RLCS_SPM_SQTT_MODE_BASE_IDX = 1 # macro +mmRLC_RLCS_CP_DMA_SRCID_OVER = 0x4ee4 # macro +mmRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX = 1 # macro +mmRLC_RLCS_UTCL2_CNTL = 0x4ee6 # macro +mmRLC_RLCS_UTCL2_CNTL_BASE_IDX = 1 # macro +mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL = 0x4ee8 # macro +mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL_BASE_IDX = 1 # macro +mmRLC_RLCS_BOOTLOAD_ID_STATUS1 = 0x4eec # macro +mmRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX = 1 # macro +mmRLC_RLCS_BOOTLOAD_ID_STATUS2 = 0x4eed # macro +mmRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX = 1 # macro +mmRLC_RLCS_SMUIO_VIDCHG_CTRL = 0x4eee # macro +mmRLC_RLCS_SMUIO_VIDCHG_CTRL_BASE_IDX = 1 # macro +mmRLC_RLCS_EDC_INT_CNTL = 0x4eef # macro +mmRLC_RLCS_EDC_INT_CNTL_BASE_IDX = 1 # macro +mmRLC_RLCS_KMD_LOG_CNTL1 = 0x4ef1 # macro +mmRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX = 1 # macro +mmRLC_RLCS_KMD_LOG_CNTL2 = 0x4ef2 # macro +mmRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX = 1 # macro +mmRLC_RLCS_GPM_LEGACY_INT_STAT = 0x4ef3 # macro +mmRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX = 1 # macro +mmRLC_RLCS_GPM_LEGACY_INT_DISABLE = 0x4ef4 # macro +mmRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX = 1 # macro +mmRLC_RLCS_SRM_SRCID_CNTL = 0x4efd # macro +mmRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX = 1 # macro +mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE = 0x4f03 # macro +mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX = 1 # macro +mmRLC_RLCS_DEC_END = 0x4fff # macro +mmRLC_RLCS_DEC_END_BASE_IDX = 1 # macro +mmCGTS_RD_CTRL_REG = 0x5004 # macro +mmCGTS_RD_CTRL_REG_BASE_IDX = 1 # macro +mmCGTS_RD_REG = 0x5005 # macro +mmCGTS_RD_REG_BASE_IDX = 1 # macro +mmCGTS_TCC_DISABLE = 0x5006 # macro +mmCGTS_TCC_DISABLE_BASE_IDX = 1 # macro +mmCGTS_USER_TCC_DISABLE = 0x5007 # macro +mmCGTS_USER_TCC_DISABLE_BASE_IDX = 1 # macro +mmCGTS_STATUS_REG = 0x5008 # macro +mmCGTS_STATUS_REG_BASE_IDX = 1 # macro +mmCGTT_SPI_CGTSSM_CLK_CTRL = 0x5009 # macro +mmCGTT_SPI_CGTSSM_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_SPI_PS_CLK_CTRL = 0x507d # macro +mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_SPIS_CLK_CTRL = 0x507e # macro +mmCGTT_SPIS_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_SPI_CLK_CTRL = 0x5080 # macro +mmCGTT_SPI_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_PC_CLK_CTRL = 0x5081 # macro +mmCGTT_PC_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_BCI_CLK_CTRL = 0x5082 # macro +mmCGTT_BCI_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_VGT_CLK_CTRL = 0x5084 # macro +mmCGTT_VGT_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_IA_CLK_CTRL = 0x5085 # macro +mmCGTT_IA_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_WD_CLK_CTRL = 0x5086 # macro +mmCGTT_WD_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_GS_NGG_CLK_CTRL = 0x5087 # macro +mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_PA_CLK_CTRL = 0x5088 # macro +mmCGTT_PA_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_SC_CLK_CTRL0 = 0x5089 # macro +mmCGTT_SC_CLK_CTRL0_BASE_IDX = 1 # macro +mmCGTT_SC_CLK_CTRL1 = 0x508a # macro +mmCGTT_SC_CLK_CTRL1_BASE_IDX = 1 # macro +mmCGTT_SC_CLK_CTRL2 = 0x508b # macro +mmCGTT_SC_CLK_CTRL2_BASE_IDX = 1 # macro +mmCGTT_SQ_CLK_CTRL = 0x508c # macro +mmCGTT_SQ_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_SQG_CLK_CTRL = 0x508d # macro +mmCGTT_SQG_CLK_CTRL_BASE_IDX = 1 # macro +mmSQ_ALU_CLK_CTRL = 0x508e # macro +mmSQ_ALU_CLK_CTRL_BASE_IDX = 1 # macro +mmSQ_TEX_CLK_CTRL = 0x508f # macro +mmSQ_TEX_CLK_CTRL_BASE_IDX = 1 # macro +mmSQ_LDS_CLK_CTRL = 0x5090 # macro +mmSQ_LDS_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_SX_CLK_CTRL0 = 0x5094 # macro +mmCGTT_SX_CLK_CTRL0_BASE_IDX = 1 # macro +mmCGTT_SX_CLK_CTRL1 = 0x5095 # macro +mmCGTT_SX_CLK_CTRL1_BASE_IDX = 1 # macro +mmCGTT_SX_CLK_CTRL2 = 0x5096 # macro +mmCGTT_SX_CLK_CTRL2_BASE_IDX = 1 # macro +mmCGTT_SX_CLK_CTRL3 = 0x5097 # macro +mmCGTT_SX_CLK_CTRL3_BASE_IDX = 1 # macro +mmCGTT_SX_CLK_CTRL4 = 0x5098 # macro +mmCGTT_SX_CLK_CTRL4_BASE_IDX = 1 # macro +mmTD_CGTT_CTRL = 0x509c # macro +mmTD_CGTT_CTRL_BASE_IDX = 1 # macro +mmTA_CGTT_CTRL = 0x509d # macro +mmTA_CGTT_CTRL_BASE_IDX = 1 # macro +mmCGTT_TCPI_CLK_CTRL = 0x5109 # macro +mmCGTT_TCPI_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_GDS_CLK_CTRL = 0x50a0 # macro +mmCGTT_GDS_CLK_CTRL_BASE_IDX = 1 # macro +mmDB_CGTT_CLK_CTRL_0 = 0x50a4 # macro +mmDB_CGTT_CLK_CTRL_0_BASE_IDX = 1 # macro +mmCB_CGTT_SCLK_CTRL = 0x50a8 # macro +mmCB_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro +mmGL2C_CGTT_SCLK_CTRL = 0x50fc # macro +mmGL2C_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro +mmGL2A_CGTT_SCLK_CTRL = 0x50ac # macro +mmGL2A_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro +mmGL2A_CGTT_SCLK_CTRL_1 = 0x50ad # macro +mmGL2A_CGTT_SCLK_CTRL_1_BASE_IDX = 1 # macro +mmCGTT_CP_CLK_CTRL = 0x50b0 # macro +mmCGTT_CP_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_CPF_CLK_CTRL = 0x50b1 # macro +mmCGTT_CPF_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_CPC_CLK_CTRL = 0x50b2 # macro +mmCGTT_CPC_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_RLC_CLK_CTRL = 0x50b5 # macro +mmCGTT_RLC_CLK_CTRL_BASE_IDX = 1 # macro +mmRLC_GFX_RM_CNTL = 0x50b6 # macro +mmRLC_GFX_RM_CNTL_BASE_IDX = 1 # macro +mmRMI_CGTT_SCLK_CTRL = 0x50c0 # macro +mmRMI_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_TCPF_CLK_CTRL = 0x5111 # macro +mmCGTT_TCPF_CLK_CTRL_BASE_IDX = 1 # macro +mmGCR_CGTT_SCLK_CTRL = 0x50c2 # macro +mmGCR_CGTT_SCLK_CTRL_BASE_IDX = 1 # macro +mmUTCL1_CGTT_CLK_CTRL = 0x50c3 # macro +mmUTCL1_CGTT_CLK_CTRL_BASE_IDX = 1 # macro +mmGCEA_CGTT_CLK_CTRL = 0x50c4 # macro +mmGCEA_CGTT_CLK_CTRL_BASE_IDX = 1 # macro +mmSE_CAC_CGTT_CLK_CTRL = 0x50d0 # macro +mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX = 1 # macro +mmGC_CAC_CGTT_CLK_CTRL = 0x50d8 # macro +mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX = 1 # macro +mmGRBM_CGTT_CLK_CNTL = 0x50e0 # macro +mmGRBM_CGTT_CLK_CNTL_BASE_IDX = 1 # macro +mmGUS_CGTT_CLK_CTRL = 0x50f4 # macro +mmGUS_CGTT_CLK_CTRL_BASE_IDX = 1 # macro +mmCGTT_PH_CLK_CTRL0 = 0x50f8 # macro +mmCGTT_PH_CLK_CTRL0_BASE_IDX = 1 # macro +mmCGTT_PH_CLK_CTRL1 = 0x50f9 # macro +mmCGTT_PH_CLK_CTRL1_BASE_IDX = 1 # macro +mmCGTT_PH_CLK_CTRL2 = 0x50fa # macro +mmCGTT_PH_CLK_CTRL2_BASE_IDX = 1 # macro +mmCGTT_PH_CLK_CTRL3 = 0x50fb # macro +mmCGTT_PH_CLK_CTRL3_BASE_IDX = 1 # macro +mmCP_HYP_PFP_UCODE_ADDR = 0x5814 # macro +mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro +mmCP_PFP_UCODE_ADDR = 0x5814 # macro +mmCP_PFP_UCODE_ADDR_BASE_IDX = 1 # macro +mmCP_HYP_PFP_UCODE_DATA = 0x5815 # macro +mmCP_HYP_PFP_UCODE_DATA_BASE_IDX = 1 # macro +mmCP_PFP_UCODE_DATA = 0x5815 # macro +mmCP_PFP_UCODE_DATA_BASE_IDX = 1 # macro +mmCP_HYP_ME_UCODE_ADDR = 0x5816 # macro +mmCP_HYP_ME_UCODE_ADDR_BASE_IDX = 1 # macro +mmCP_ME_RAM_RADDR = 0x5816 # macro +mmCP_ME_RAM_RADDR_BASE_IDX = 1 # macro +mmCP_ME_RAM_WADDR = 0x5816 # macro +mmCP_ME_RAM_WADDR_BASE_IDX = 1 # macro +mmCP_HYP_ME_UCODE_DATA = 0x5817 # macro +mmCP_HYP_ME_UCODE_DATA_BASE_IDX = 1 # macro +mmCP_ME_RAM_DATA = 0x5817 # macro +mmCP_ME_RAM_DATA_BASE_IDX = 1 # macro +mmCP_CE_UCODE_ADDR = 0x5818 # macro +mmCP_CE_UCODE_ADDR_BASE_IDX = 1 # macro +mmCP_HYP_CE_UCODE_ADDR = 0x5818 # macro +mmCP_HYP_CE_UCODE_ADDR_BASE_IDX = 1 # macro +mmCP_CE_UCODE_DATA = 0x5819 # macro +mmCP_CE_UCODE_DATA_BASE_IDX = 1 # macro +mmCP_HYP_CE_UCODE_DATA = 0x5819 # macro +mmCP_HYP_CE_UCODE_DATA_BASE_IDX = 1 # macro +mmCP_HYP_MEC1_UCODE_ADDR = 0x581a # macro +mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX = 1 # macro +mmCP_MEC_ME1_UCODE_ADDR = 0x581a # macro +mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX = 1 # macro +mmCP_HYP_MEC1_UCODE_DATA = 0x581b # macro +mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX = 1 # macro +mmCP_MEC_ME1_UCODE_DATA = 0x581b # macro +mmCP_MEC_ME1_UCODE_DATA_BASE_IDX = 1 # macro +mmCP_HYP_MEC2_UCODE_ADDR = 0x581c # macro +mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX = 1 # macro +mmCP_MEC_ME2_UCODE_ADDR = 0x581c # macro +mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX = 1 # macro +mmCP_HYP_MEC2_UCODE_DATA = 0x581d # macro +mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX = 1 # macro +mmCP_MEC_ME2_UCODE_DATA = 0x581d # macro +mmCP_MEC_ME2_UCODE_DATA_BASE_IDX = 1 # macro +mmCP_PFP_IC_BASE_LO = 0x5840 # macro +mmCP_PFP_IC_BASE_LO_BASE_IDX = 1 # macro +mmCP_PFP_IC_BASE_HI = 0x5841 # macro +mmCP_PFP_IC_BASE_HI_BASE_IDX = 1 # macro +mmCP_PFP_IC_BASE_CNTL = 0x5842 # macro +mmCP_PFP_IC_BASE_CNTL_BASE_IDX = 1 # macro +mmCP_PFP_IC_OP_CNTL = 0x5843 # macro +mmCP_PFP_IC_OP_CNTL_BASE_IDX = 1 # macro +mmCP_ME_IC_BASE_LO = 0x5844 # macro +mmCP_ME_IC_BASE_LO_BASE_IDX = 1 # macro +mmCP_ME_IC_BASE_HI = 0x5845 # macro +mmCP_ME_IC_BASE_HI_BASE_IDX = 1 # macro +mmCP_ME_IC_BASE_CNTL = 0x5846 # macro +mmCP_ME_IC_BASE_CNTL_BASE_IDX = 1 # macro +mmCP_ME_IC_OP_CNTL = 0x5847 # macro +mmCP_ME_IC_OP_CNTL_BASE_IDX = 1 # macro +mmCP_CE_IC_BASE_LO = 0x5848 # macro +mmCP_CE_IC_BASE_LO_BASE_IDX = 1 # macro +mmCP_CE_IC_BASE_HI = 0x5849 # macro +mmCP_CE_IC_BASE_HI_BASE_IDX = 1 # macro +mmCP_CE_IC_BASE_CNTL = 0x584a # macro +mmCP_CE_IC_BASE_CNTL_BASE_IDX = 1 # macro +mmCP_CE_IC_OP_CNTL = 0x584b # macro +mmCP_CE_IC_OP_CNTL_BASE_IDX = 1 # macro +mmCP_CPC_IC_BASE_LO = 0x584c # macro +mmCP_CPC_IC_BASE_LO_BASE_IDX = 1 # macro +mmCP_CPC_IC_BASE_HI = 0x584d # macro +mmCP_CPC_IC_BASE_HI_BASE_IDX = 1 # macro +mmCP_CPC_IC_BASE_CNTL = 0x584e # macro +mmCP_CPC_IC_BASE_CNTL_BASE_IDX = 1 # macro +mmCP_CPC_IC_OP_CNTL = 0x584f # macro +mmCP_CPC_IC_OP_CNTL_BASE_IDX = 1 # macro +mmCP_MES_IC_BASE_LO = 0x5850 # macro +mmCP_MES_IC_BASE_LO_BASE_IDX = 1 # macro +mmCP_MES_MIBASE_LO = 0x5850 # macro +mmCP_MES_MIBASE_LO_BASE_IDX = 1 # macro +mmCP_MES_IC_BASE_HI = 0x5851 # macro +mmCP_MES_IC_BASE_HI_BASE_IDX = 1 # macro +mmCP_MES_MIBASE_HI = 0x5851 # macro +mmCP_MES_MIBASE_HI_BASE_IDX = 1 # macro +mmCP_MES_IC_BASE_CNTL = 0x5852 # macro +mmCP_MES_IC_BASE_CNTL_BASE_IDX = 1 # macro +mmCP_MES_DC_BASE_LO = 0x5854 # macro +mmCP_MES_DC_BASE_LO_BASE_IDX = 1 # macro +mmCP_MES_MDBASE_LO = 0x5854 # macro +mmCP_MES_MDBASE_LO_BASE_IDX = 1 # macro +mmCP_MES_DC_BASE_HI = 0x5855 # macro +mmCP_MES_DC_BASE_HI_BASE_IDX = 1 # macro +mmCP_MES_MDBASE_HI = 0x5855 # macro +mmCP_MES_MDBASE_HI_BASE_IDX = 1 # macro +mmCP_MES_LOCAL_BASE0_LO = 0x5856 # macro +mmCP_MES_LOCAL_BASE0_LO_BASE_IDX = 1 # macro +mmCP_MES_LOCAL_BASE0_HI = 0x5857 # macro +mmCP_MES_LOCAL_BASE0_HI_BASE_IDX = 1 # macro +mmCP_MES_LOCAL_MASK0_LO = 0x5858 # macro +mmCP_MES_LOCAL_MASK0_LO_BASE_IDX = 1 # macro +mmCP_MES_LOCAL_MASK0_HI = 0x5859 # macro +mmCP_MES_LOCAL_MASK0_HI_BASE_IDX = 1 # macro +mmCP_MES_LOCAL_APERTURE = 0x585a # macro +mmCP_MES_LOCAL_APERTURE_BASE_IDX = 1 # macro +mmCP_MES_MIBOUND_LO = 0x585b # macro +mmCP_MES_MIBOUND_LO_BASE_IDX = 1 # macro +mmCP_MES_MIBOUND_HI = 0x585c # macro +mmCP_MES_MIBOUND_HI_BASE_IDX = 1 # macro +mmCP_MES_MDBOUND_LO = 0x585d # macro +mmCP_MES_MDBOUND_LO_BASE_IDX = 1 # macro +mmCP_MES_MDBOUND_HI = 0x585e # macro +mmCP_MES_MDBOUND_HI_BASE_IDX = 1 # macro +mmGFX_PIPE_PRIORITY = 0x587f # macro +mmGFX_PIPE_PRIORITY_BASE_IDX = 1 # macro +mmGRBM_GFX_INDEX_SR_SELECT = 0x5a00 # macro +mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX = 1 # macro +mmGRBM_GFX_INDEX_SR_DATA = 0x5a01 # macro +mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX = 1 # macro +mmGRBM_GFX_CNTL_SR_SELECT = 0x5a02 # macro +mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX = 1 # macro +mmGRBM_GFX_CNTL_SR_DATA = 0x5a03 # macro +mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX = 1 # macro +mmGRBM_CAM_INDEX = 0x5a04 # macro +mmGRBM_CAM_INDEX_BASE_IDX = 1 # macro +mmGRBM_HYP_CAM_INDEX = 0x5a04 # macro +mmGRBM_HYP_CAM_INDEX_BASE_IDX = 1 # macro +mmGRBM_CAM_DATA = 0x5a05 # macro +mmGRBM_CAM_DATA_BASE_IDX = 1 # macro +mmGRBM_HYP_CAM_DATA = 0x5a05 # macro +mmGRBM_HYP_CAM_DATA_BASE_IDX = 1 # macro +mmGRBM_CAM_DATA_UPPER = 0x5a06 # macro +mmGRBM_CAM_DATA_UPPER_BASE_IDX = 1 # macro +mmGRBM_HYP_CAM_DATA_UPPER = 0x5a06 # macro +mmGRBM_HYP_CAM_DATA_UPPER_BASE_IDX = 1 # macro +mmGC_IH_COOKIE_0_PTR = 0x5a07 # macro +mmGC_IH_COOKIE_0_PTR_BASE_IDX = 1 # macro +mmGRBM_SE_REMAP_CNTL = 0x5a08 # macro +mmGRBM_SE_REMAP_CNTL_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_VF_ENABLE = 0x5b00 # macro +mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_CFG_REG6 = 0x5b06 # macro +mmRLC_GPU_IOV_CFG_REG6_BASE_IDX = 1 # macro +mmRLC_SDMA0_STATUS = 0x5b12 # macro +mmRLC_SDMA0_STATUS_BASE_IDX = 1 # macro +mmRLC_SDMA1_STATUS = 0x5b13 # macro +mmRLC_SDMA1_STATUS_BASE_IDX = 1 # macro +mmRLC_SDMA2_STATUS = 0x5b14 # macro +mmRLC_SDMA2_STATUS_BASE_IDX = 1 # macro +mmRLC_SDMA3_STATUS = 0x5b15 # macro +mmRLC_SDMA3_STATUS_BASE_IDX = 1 # macro +mmRLC_SDMA0_BUSY_STATUS = 0x5b16 # macro +mmRLC_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_SDMA1_BUSY_STATUS = 0x5b17 # macro +mmRLC_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_SDMA2_BUSY_STATUS = 0x5b18 # macro +mmRLC_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_SDMA3_BUSY_STATUS = 0x5b19 # macro +mmRLC_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_CFG_REG8 = 0x5b20 # macro +mmRLC_GPU_IOV_CFG_REG8_BASE_IDX = 1 # macro +mmRLC_RLCV_TIMER_INT_0 = 0x5b25 # macro +mmRLC_RLCV_TIMER_INT_0_BASE_IDX = 1 # macro +mmRLC_RLCV_TIMER_CTRL = 0x5b26 # macro +mmRLC_RLCV_TIMER_CTRL_BASE_IDX = 1 # macro +mmRLC_RLCV_TIMER_STAT = 0x5b27 # macro +mmRLC_RLCV_TIMER_STAT_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_VF_DOORBELL_STATUS = 0x5b2a # macro +mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET = 0x5b2b # macro +mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR = 0x5b2c # macro +mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_VF_MASK = 0x5b2d # macro +mmRLC_GPU_IOV_VF_MASK_BASE_IDX = 1 # macro +mmRLC_HYP_SEMAPHORE_0 = 0x5b2e # macro +mmRLC_HYP_SEMAPHORE_0_BASE_IDX = 1 # macro +mmRLC_HYP_SEMAPHORE_1 = 0x5b2f # macro +mmRLC_HYP_SEMAPHORE_1_BASE_IDX = 1 # macro +mmRLC_BUSY_CLK_CNTL = 0x5b30 # macro +mmRLC_BUSY_CLK_CNTL_BASE_IDX = 1 # macro +mmRLC_CLK_CNTL = 0x5b31 # macro +mmRLC_CLK_CNTL_BASE_IDX = 1 # macro +mmRLC_PACE_TIMER_STAT = 0x5b33 # macro +mmRLC_PACE_TIMER_STAT_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SCH_BLOCK = 0x5b34 # macro +mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_CFG_REG1 = 0x5b35 # macro +mmRLC_GPU_IOV_CFG_REG1_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_CFG_REG2 = 0x5b36 # macro +mmRLC_GPU_IOV_CFG_REG2_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_VM_BUSY_STATUS = 0x5b37 # macro +mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SCH_0 = 0x5b38 # macro +mmRLC_GPU_IOV_SCH_0_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_ACTIVE_FCN_ID = 0x5b39 # macro +mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SCH_3 = 0x5b3a # macro +mmRLC_GPU_IOV_SCH_3_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SCH_1 = 0x5b3b # macro +mmRLC_GPU_IOV_SCH_1_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SCH_2 = 0x5b3c # macro +mmRLC_GPU_IOV_SCH_2_BASE_IDX = 1 # macro +mmRLC_PACE_INT_FORCE = 0x5b3d # macro +mmRLC_PACE_INT_FORCE_BASE_IDX = 1 # macro +mmRLC_PACE_INT_CLEAR = 0x5b3e # macro +mmRLC_PACE_INT_CLEAR_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_INT_STAT = 0x5b3f # macro +mmRLC_GPU_IOV_INT_STAT_BASE_IDX = 1 # macro +mmRLC_RLCV_TIMER_INT_1 = 0x5b40 # macro +mmRLC_RLCV_TIMER_INT_1_BASE_IDX = 1 # macro +mmRLC_IH_COOKIE = 0x5b41 # macro +mmRLC_IH_COOKIE_BASE_IDX = 1 # macro +mmRLC_IH_COOKIE_CNTL = 0x5b42 # macro +mmRLC_IH_COOKIE_CNTL_BASE_IDX = 1 # macro +mmRLC_HYP_RLCG_UCODE_CHKSUM = 0x5b43 # macro +mmRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX = 1 # macro +mmRLC_HYP_RLCP_UCODE_CHKSUM = 0x5b44 # macro +mmRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX = 1 # macro +mmRLC_HYP_RLCV_UCODE_CHKSUM = 0x5b45 # macro +mmRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_F32_CNTL = 0x5b46 # macro +mmRLC_GPU_IOV_F32_CNTL_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_F32_RESET = 0x5b47 # macro +mmRLC_GPU_IOV_F32_RESET_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SMU_RESPONSE = 0x5b4a # macro +mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_VIRT_RESET_REQ = 0x5b4c # macro +mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_RLC_RESPONSE = 0x5b4d # macro +mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_INT_DISABLE = 0x5b4e # macro +mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_INT_FORCE = 0x5b4f # macro +mmRLC_GPU_IOV_INT_FORCE_BASE_IDX = 1 # macro +mmRLC_HYP_SEMAPHORE_2 = 0x5b52 # macro +mmRLC_HYP_SEMAPHORE_2_BASE_IDX = 1 # macro +mmRLC_HYP_SEMAPHORE_3 = 0x5b53 # macro +mmRLC_HYP_SEMAPHORE_3_BASE_IDX = 1 # macro +mmRLC_HYP_RESET_VECTOR = 0x5b54 # macro +mmRLC_HYP_RESET_VECTOR_BASE_IDX = 1 # macro +mmRLC_HYP_BOOTLOAD_SIZE = 0x5b5c # macro +mmRLC_HYP_BOOTLOAD_SIZE_BASE_IDX = 1 # macro +mmRLC_HYP_BOOTLOAD_ADDR_LO = 0x5b5d # macro +mmRLC_HYP_BOOTLOAD_ADDR_LO_BASE_IDX = 1 # macro +mmRLC_HYP_BOOTLOAD_ADDR_HI = 0x5b5e # macro +mmRLC_HYP_BOOTLOAD_ADDR_HI_BASE_IDX = 1 # macro +mmRLC_GPM_IRAM_ADDR = 0x5b5f # macro +mmRLC_GPM_IRAM_ADDR_BASE_IDX = 1 # macro +mmRLC_GPM_IRAM_DATA = 0x5b60 # macro +mmRLC_GPM_IRAM_DATA_BASE_IDX = 1 # macro +mmRLC_GPM_UCODE_ADDR = 0x5b61 # macro +mmRLC_GPM_UCODE_ADDR_BASE_IDX = 1 # macro +mmRLC_GPM_UCODE_DATA = 0x5b62 # macro +mmRLC_GPM_UCODE_DATA_BASE_IDX = 1 # macro +mmRLC_PACE_UCODE_ADDR = 0x5b63 # macro +mmRLC_PACE_UCODE_ADDR_BASE_IDX = 1 # macro +mmRLC_PACE_UCODE_DATA = 0x5b64 # macro +mmRLC_PACE_UCODE_DATA_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_UCODE_ADDR = 0x5b65 # macro +mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_UCODE_DATA = 0x5b66 # macro +mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SCRATCH_ADDR = 0x5b67 # macro +mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SCRATCH_DATA = 0x5b68 # macro +mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX = 1 # macro +mmRLC_RLCV_IRAM_ADDR = 0x5b69 # macro +mmRLC_RLCV_IRAM_ADDR_BASE_IDX = 1 # macro +mmRLC_RLCV_IRAM_DATA = 0x5b6a # macro +mmRLC_RLCV_IRAM_DATA_BASE_IDX = 1 # macro +mmRLC_RLCP_IRAM_ADDR = 0x5b6b # macro +mmRLC_RLCP_IRAM_ADDR_BASE_IDX = 1 # macro +mmRLC_RLCP_IRAM_DATA = 0x5b6c # macro +mmRLC_RLCP_IRAM_DATA_BASE_IDX = 1 # macro +mmRLC_SRM_DRAM_ADDR = 0x5b71 # macro +mmRLC_SRM_DRAM_ADDR_BASE_IDX = 1 # macro +mmRLC_SRM_DRAM_DATA = 0x5b72 # macro +mmRLC_SRM_DRAM_DATA_BASE_IDX = 1 # macro +mmRLC_SRM_ARAM_ADDR = 0x5b73 # macro +mmRLC_SRM_ARAM_ADDR_BASE_IDX = 1 # macro +mmRLC_SRM_ARAM_DATA = 0x5b74 # macro +mmRLC_SRM_ARAM_DATA_BASE_IDX = 1 # macro +mmRLC_GPM_SCRATCH_ADDR = 0x5b75 # macro +mmRLC_GPM_SCRATCH_ADDR_BASE_IDX = 1 # macro +mmRLC_GPM_SCRATCH_DATA = 0x5b76 # macro +mmRLC_GPM_SCRATCH_DATA_BASE_IDX = 1 # macro +mmRLC_GTS_OFFSET_LSB = 0x5b79 # macro +mmRLC_GTS_OFFSET_LSB_BASE_IDX = 1 # macro +mmRLC_GTS_OFFSET_MSB = 0x5b7a # macro +mmRLC_GTS_OFFSET_MSB_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA0_STATUS = 0x5bc0 # macro +mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA1_STATUS = 0x5bc1 # macro +mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA2_STATUS = 0x5bc2 # macro +mmRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA3_STATUS = 0x5bc3 # macro +mmRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA4_STATUS = 0x5bc4 # macro +mmRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA5_STATUS = 0x5bc5 # macro +mmRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA6_STATUS = 0x5bc6 # macro +mmRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA7_STATUS = 0x5bc7 # macro +mmRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA0_BUSY_STATUS = 0x5bc8 # macro +mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA1_BUSY_STATUS = 0x5bc9 # macro +mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA2_BUSY_STATUS = 0x5bca # macro +mmRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA3_BUSY_STATUS = 0x5bcb # macro +mmRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA4_BUSY_STATUS = 0x5bcc # macro +mmRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA5_BUSY_STATUS = 0x5bcd # macro +mmRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA6_BUSY_STATUS = 0x5bce # macro +mmRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX = 1 # macro +mmRLC_GPU_IOV_SDMA7_BUSY_STATUS = 0x5bcf # macro +mmRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX = 1 # macro +mmSDMA0_UCODE_ADDR = 0x5880 # macro +mmSDMA0_UCODE_ADDR_BASE_IDX = 1 # macro +mmSDMA0_UCODE_DATA = 0x5881 # macro +mmSDMA0_UCODE_DATA_BASE_IDX = 1 # macro +mmSDMA0_VM_CTX_LO = 0x5882 # macro +mmSDMA0_VM_CTX_LO_BASE_IDX = 1 # macro +mmSDMA0_VM_CTX_HI = 0x5883 # macro +mmSDMA0_VM_CTX_HI_BASE_IDX = 1 # macro +mmSDMA0_ACTIVE_FCN_ID = 0x5884 # macro +mmSDMA0_ACTIVE_FCN_ID_BASE_IDX = 1 # macro +mmSDMA0_VM_CTX_CNTL = 0x5885 # macro +mmSDMA0_VM_CTX_CNTL_BASE_IDX = 1 # macro +mmSDMA0_VIRT_RESET_REQ = 0x5886 # macro +mmSDMA0_VIRT_RESET_REQ_BASE_IDX = 1 # macro +mmSDMA0_VF_ENABLE = 0x5887 # macro +mmSDMA0_VF_ENABLE_BASE_IDX = 1 # macro +mmSDMA0_CONTEXT_REG_TYPE0 = 0x5888 # macro +mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX = 1 # macro +mmSDMA0_CONTEXT_REG_TYPE1 = 0x5889 # macro +mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX = 1 # macro +mmSDMA0_CONTEXT_REG_TYPE2 = 0x588a # macro +mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX = 1 # macro +mmSDMA0_CONTEXT_REG_TYPE3 = 0x588b # macro +mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX = 1 # macro +mmSDMA0_PUB_REG_TYPE0 = 0x588c # macro +mmSDMA0_PUB_REG_TYPE0_BASE_IDX = 1 # macro +mmSDMA0_PUB_REG_TYPE1 = 0x588d # macro +mmSDMA0_PUB_REG_TYPE1_BASE_IDX = 1 # macro +mmSDMA0_PUB_REG_TYPE2 = 0x588e # macro +mmSDMA0_PUB_REG_TYPE2_BASE_IDX = 1 # macro +mmSDMA0_PUB_REG_TYPE3 = 0x588f # macro +mmSDMA0_PUB_REG_TYPE3_BASE_IDX = 1 # macro +mmSDMA0_VM_CNTL = 0x5893 # macro +mmSDMA0_VM_CNTL_BASE_IDX = 1 # macro +mmSDMA0_BROADCAST_UCODE_ADDR = 0x589c # macro +mmSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX = 1 # macro +mmSDMA0_BROADCAST_UCODE_DATA = 0x589d # macro +mmSDMA0_BROADCAST_UCODE_DATA_BASE_IDX = 1 # macro +mmSDMA1_UCODE_ADDR = 0x58a0 # macro +mmSDMA1_UCODE_ADDR_BASE_IDX = 1 # macro +mmSDMA1_UCODE_DATA = 0x58a1 # macro +mmSDMA1_UCODE_DATA_BASE_IDX = 1 # macro +mmSDMA1_VM_CTX_LO = 0x58a2 # macro +mmSDMA1_VM_CTX_LO_BASE_IDX = 1 # macro +mmSDMA1_VM_CTX_HI = 0x58a3 # macro +mmSDMA1_VM_CTX_HI_BASE_IDX = 1 # macro +mmSDMA1_ACTIVE_FCN_ID = 0x58a4 # macro +mmSDMA1_ACTIVE_FCN_ID_BASE_IDX = 1 # macro +mmSDMA1_VM_CTX_CNTL = 0x58a5 # macro +mmSDMA1_VM_CTX_CNTL_BASE_IDX = 1 # macro +mmSDMA1_VIRT_RESET_REQ = 0x58a6 # macro +mmSDMA1_VIRT_RESET_REQ_BASE_IDX = 1 # macro +mmSDMA1_VF_ENABLE = 0x58a7 # macro +mmSDMA1_VF_ENABLE_BASE_IDX = 1 # macro +mmSDMA1_CONTEXT_REG_TYPE0 = 0x58a8 # macro +mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX = 1 # macro +mmSDMA1_CONTEXT_REG_TYPE1 = 0x58a9 # macro +mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX = 1 # macro +mmSDMA1_CONTEXT_REG_TYPE2 = 0x58aa # macro +mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX = 1 # macro +mmSDMA1_CONTEXT_REG_TYPE3 = 0x58ab # macro +mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX = 1 # macro +mmSDMA1_PUB_REG_TYPE0 = 0x58ac # macro +mmSDMA1_PUB_REG_TYPE0_BASE_IDX = 1 # macro +mmSDMA1_PUB_REG_TYPE1 = 0x58ad # macro +mmSDMA1_PUB_REG_TYPE1_BASE_IDX = 1 # macro +mmSDMA1_PUB_REG_TYPE2 = 0x58ae # macro +mmSDMA1_PUB_REG_TYPE2_BASE_IDX = 1 # macro +mmSDMA1_PUB_REG_TYPE3 = 0x58af # macro +mmSDMA1_PUB_REG_TYPE3_BASE_IDX = 1 # macro +mmSDMA1_VM_CNTL = 0x58b3 # macro +mmSDMA1_VM_CNTL_BASE_IDX = 1 # macro +mmSDMA2_UCODE_ADDR = 0x58c0 # macro +mmSDMA2_UCODE_ADDR_BASE_IDX = 1 # macro +mmSDMA2_UCODE_DATA = 0x58c1 # macro +mmSDMA2_UCODE_DATA_BASE_IDX = 1 # macro +mmSDMA2_VM_CTX_LO = 0x58c2 # macro +mmSDMA2_VM_CTX_LO_BASE_IDX = 1 # macro +mmSDMA2_VM_CTX_HI = 0x58c3 # macro +mmSDMA2_VM_CTX_HI_BASE_IDX = 1 # macro +mmSDMA2_ACTIVE_FCN_ID = 0x58c4 # macro +mmSDMA2_ACTIVE_FCN_ID_BASE_IDX = 1 # macro +mmSDMA2_VM_CTX_CNTL = 0x58c5 # macro +mmSDMA2_VM_CTX_CNTL_BASE_IDX = 1 # macro +mmSDMA2_VIRT_RESET_REQ = 0x58c6 # macro +mmSDMA2_VIRT_RESET_REQ_BASE_IDX = 1 # macro +mmSDMA2_VF_ENABLE = 0x58c7 # macro +mmSDMA2_VF_ENABLE_BASE_IDX = 1 # macro +mmSDMA2_CONTEXT_REG_TYPE0 = 0x58c8 # macro +mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX = 1 # macro +mmSDMA2_CONTEXT_REG_TYPE1 = 0x58c9 # macro +mmSDMA2_CONTEXT_REG_TYPE1_BASE_IDX = 1 # macro +mmSDMA2_CONTEXT_REG_TYPE2 = 0x58ca # macro +mmSDMA2_CONTEXT_REG_TYPE2_BASE_IDX = 1 # macro +mmSDMA2_CONTEXT_REG_TYPE3 = 0x58cb # macro +mmSDMA2_CONTEXT_REG_TYPE3_BASE_IDX = 1 # macro +mmSDMA2_PUB_REG_TYPE0 = 0x58cc # macro +mmSDMA2_PUB_REG_TYPE0_BASE_IDX = 1 # macro +mmSDMA2_PUB_REG_TYPE1 = 0x58cd # macro +mmSDMA2_PUB_REG_TYPE1_BASE_IDX = 1 # macro +mmSDMA2_PUB_REG_TYPE2 = 0x58ce # macro +mmSDMA2_PUB_REG_TYPE2_BASE_IDX = 1 # macro +mmSDMA2_PUB_REG_TYPE3 = 0x58cf # macro +mmSDMA2_PUB_REG_TYPE3_BASE_IDX = 1 # macro +mmSDMA2_VM_CNTL = 0x58d3 # macro +mmSDMA2_VM_CNTL_BASE_IDX = 1 # macro +mmSDMA3_UCODE_ADDR = 0x58e0 # macro +mmSDMA3_UCODE_ADDR_BASE_IDX = 1 # macro +mmSDMA3_UCODE_DATA = 0x58e1 # macro +mmSDMA3_UCODE_DATA_BASE_IDX = 1 # macro +mmSDMA3_VM_CTX_LO = 0x58e2 # macro +mmSDMA3_VM_CTX_LO_BASE_IDX = 1 # macro +mmSDMA3_VM_CTX_HI = 0x58e3 # macro +mmSDMA3_VM_CTX_HI_BASE_IDX = 1 # macro +mmSDMA3_ACTIVE_FCN_ID = 0x58e4 # macro +mmSDMA3_ACTIVE_FCN_ID_BASE_IDX = 1 # macro +mmSDMA3_VM_CTX_CNTL = 0x58e5 # macro +mmSDMA3_VM_CTX_CNTL_BASE_IDX = 1 # macro +mmSDMA3_VIRT_RESET_REQ = 0x58e6 # macro +mmSDMA3_VIRT_RESET_REQ_BASE_IDX = 1 # macro +mmSDMA3_VF_ENABLE = 0x58e7 # macro +mmSDMA3_VF_ENABLE_BASE_IDX = 1 # macro +mmSDMA3_CONTEXT_REG_TYPE0 = 0x58e8 # macro +mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX = 1 # macro +mmSDMA3_CONTEXT_REG_TYPE1 = 0x58e9 # macro +mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX = 1 # macro +mmSDMA3_CONTEXT_REG_TYPE2 = 0x58ea # macro +mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX = 1 # macro +mmSDMA3_CONTEXT_REG_TYPE3 = 0x58eb # macro +mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX = 1 # macro +mmSDMA3_PUB_REG_TYPE0 = 0x58ec # macro +mmSDMA3_PUB_REG_TYPE0_BASE_IDX = 1 # macro +mmSDMA3_PUB_REG_TYPE1 = 0x58ed # macro +mmSDMA3_PUB_REG_TYPE1_BASE_IDX = 1 # macro +mmSDMA3_PUB_REG_TYPE2 = 0x58ee # macro +mmSDMA3_PUB_REG_TYPE2_BASE_IDX = 1 # macro +mmSDMA3_PUB_REG_TYPE3 = 0x58ef # macro +mmSDMA3_PUB_REG_TYPE3_BASE_IDX = 1 # macro +mmSDMA3_VM_CNTL = 0x58f3 # macro +mmSDMA3_VM_CNTL_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF0 = 0x5a80 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF1 = 0x5a81 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF2 = 0x5a82 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF3 = 0x5a83 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF4 = 0x5a84 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF5 = 0x5a85 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF6 = 0x5a86 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF7 = 0x5a87 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF8 = 0x5a88 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF9 = 0x5a89 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF10 = 0x5a8a # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF11 = 0x5a8b # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF12 = 0x5a8c # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF13 = 0x5a8d # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF14 = 0x5a8e # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF15 = 0x5a8f # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF16 = 0x5a90 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF17 = 0x5a91 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF18 = 0x5a92 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF19 = 0x5a93 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF20 = 0x5a94 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF21 = 0x5a95 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF22 = 0x5a96 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF23 = 0x5a97 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF24 = 0x5a98 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF25 = 0x5a99 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF26 = 0x5a9a # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF27 = 0x5a9b # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF28 = 0x5a9c # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF29 = 0x5a9d # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF30 = 0x5a9e # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX = 1 # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF31 = 0x5a9f # macro +mmGCMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX = 1 # macro +mmGCVM_IOMMU_MMIO_CNTRL_1 = 0x5aa0 # macro +mmGCVM_IOMMU_MMIO_CNTRL_1_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_BASE_LO_0 = 0x5aa1 # macro +mmGCMC_VM_MARC_BASE_LO_0_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_BASE_LO_1 = 0x5aa2 # macro +mmGCMC_VM_MARC_BASE_LO_1_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_BASE_LO_2 = 0x5aa3 # macro +mmGCMC_VM_MARC_BASE_LO_2_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_BASE_LO_3 = 0x5aa4 # macro +mmGCMC_VM_MARC_BASE_LO_3_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_BASE_HI_0 = 0x5aa5 # macro +mmGCMC_VM_MARC_BASE_HI_0_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_BASE_HI_1 = 0x5aa6 # macro +mmGCMC_VM_MARC_BASE_HI_1_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_BASE_HI_2 = 0x5aa7 # macro +mmGCMC_VM_MARC_BASE_HI_2_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_BASE_HI_3 = 0x5aa8 # macro +mmGCMC_VM_MARC_BASE_HI_3_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_RELOC_LO_0 = 0x5aa9 # macro +mmGCMC_VM_MARC_RELOC_LO_0_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_RELOC_LO_1 = 0x5aaa # macro +mmGCMC_VM_MARC_RELOC_LO_1_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_RELOC_LO_2 = 0x5aab # macro +mmGCMC_VM_MARC_RELOC_LO_2_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_RELOC_LO_3 = 0x5aac # macro +mmGCMC_VM_MARC_RELOC_LO_3_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_RELOC_HI_0 = 0x5aad # macro +mmGCMC_VM_MARC_RELOC_HI_0_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_RELOC_HI_1 = 0x5aae # macro +mmGCMC_VM_MARC_RELOC_HI_1_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_RELOC_HI_2 = 0x5aaf # macro +mmGCMC_VM_MARC_RELOC_HI_2_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_RELOC_HI_3 = 0x5ab0 # macro +mmGCMC_VM_MARC_RELOC_HI_3_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_LEN_LO_0 = 0x5ab1 # macro +mmGCMC_VM_MARC_LEN_LO_0_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_LEN_LO_1 = 0x5ab2 # macro +mmGCMC_VM_MARC_LEN_LO_1_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_LEN_LO_2 = 0x5ab3 # macro +mmGCMC_VM_MARC_LEN_LO_2_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_LEN_LO_3 = 0x5ab4 # macro +mmGCMC_VM_MARC_LEN_LO_3_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_LEN_HI_0 = 0x5ab5 # macro +mmGCMC_VM_MARC_LEN_HI_0_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_LEN_HI_1 = 0x5ab6 # macro +mmGCMC_VM_MARC_LEN_HI_1_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_LEN_HI_2 = 0x5ab7 # macro +mmGCMC_VM_MARC_LEN_HI_2_BASE_IDX = 1 # macro +mmGCMC_VM_MARC_LEN_HI_3 = 0x5ab8 # macro +mmGCMC_VM_MARC_LEN_HI_3_BASE_IDX = 1 # macro +mmGCVM_IOMMU_CONTROL_REGISTER = 0x5ab9 # macro +mmGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX = 1 # macro +mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER = 0x5aba # macro +mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX = 1 # macro +mmGCMC_VM_XGMI_GPUIOV_ENABLE = 0x5abb # macro +mmGCMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX = 1 # macro +mmCPG_PSP_DEBUG = 0x5c10 # macro +mmCPG_PSP_DEBUG_BASE_IDX = 1 # macro +mmCPC_PSP_DEBUG = 0x5c11 # macro +mmCPC_PSP_DEBUG_BASE_IDX = 1 # macro +mmGRBM_SEC_CNTL = 0x5e0d # macro +mmGRBM_SEC_CNTL_BASE_IDX = 1 # macro +mmRLC_FWL_FIRST_VIOL_ADDR = 0x5f12 # macro +mmRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 # macro +mmRLC_SRM_FWL_FIRST_VIOL_ADDR = 0x5f3d # macro +mmRLC_SRM_FWL_FIRST_VIOL_ADDR_BASE_IDX = 1 # macro +mmGCVM_L2_ID_CTRL0 = 0x5dc0 # macro +mmGCVM_L2_ID_CTRL0_BASE_IDX = 1 # macro +mmGCVM_L2_ID_CTRL1 = 0x5dc1 # macro +mmGCVM_L2_ID_CTRL1_BASE_IDX = 1 # macro +mmGCVM_L2_ID_CTRL2 = 0x5dc2 # macro +mmGCVM_L2_ID_CTRL2_BASE_IDX = 1 # macro +mmGCVM_L2_ID_CTRL3 = 0x5dc3 # macro +mmGCVM_L2_ID_CTRL3_BASE_IDX = 1 # macro +mmGCVM_L2_ID_CTRL4 = 0x5dc4 # macro +mmGCVM_L2_ID_CTRL4_BASE_IDX = 1 # macro +mmGCVM_L2_ID_CTRL5 = 0x5dc5 # macro +mmGCVM_L2_ID_CTRL5_BASE_IDX = 1 # macro +mmGCVM_L2_ID_CTRL6 = 0x5dc6 # macro +mmGCVM_L2_ID_CTRL6_BASE_IDX = 1 # macro +mmGCVM_L2_ID_CTRL7 = 0x5dc7 # macro +mmGCVM_L2_ID_CTRL7_BASE_IDX = 1 # macro +mmGCVM_L2_ID_CTRL_HI = 0x5dc8 # macro +mmGCVM_L2_ID_CTRL_HI_BASE_IDX = 1 # macro +mmGCVM_L2_ID_STATUS = 0x5dc9 # macro +mmGCVM_L2_ID_STATUS_BASE_IDX = 1 # macro +mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID = 0x5dcb # macro +mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX = 1 # macro +mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE = 0x5dcd # macro +mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX = 1 # macro +mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO = 0x5dce # macro +mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX = 1 # macro +mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI = 0x5dcf # macro +mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX = 1 # macro +mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO = 0x5dd0 # macro +mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX = 1 # macro +mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI = 0x5dd1 # macro +mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX = 1 # macro +mmSDMA2_DEC_START = 0x0000 # macro +mmSDMA2_DEC_START_BASE_IDX = 2 # macro +mmSDMA2_GLOBAL_TIMESTAMP_LO = 0x000f # macro +mmSDMA2_GLOBAL_TIMESTAMP_LO_BASE_IDX = 2 # macro +mmSDMA2_GLOBAL_TIMESTAMP_HI = 0x0010 # macro +mmSDMA2_GLOBAL_TIMESTAMP_HI_BASE_IDX = 2 # macro +mmSDMA2_PG_CNTL = 0x0016 # macro +mmSDMA2_PG_CNTL_BASE_IDX = 2 # macro +mmSDMA2_PG_CTX_LO = 0x0017 # macro +mmSDMA2_PG_CTX_LO_BASE_IDX = 2 # macro +mmSDMA2_PG_CTX_HI = 0x0018 # macro +mmSDMA2_PG_CTX_HI_BASE_IDX = 2 # macro +mmSDMA2_PG_CTX_CNTL = 0x0019 # macro +mmSDMA2_PG_CTX_CNTL_BASE_IDX = 2 # macro +mmSDMA2_POWER_CNTL = 0x001a # macro +mmSDMA2_POWER_CNTL_BASE_IDX = 2 # macro +mmSDMA2_CLK_CTRL = 0x001b # macro +mmSDMA2_CLK_CTRL_BASE_IDX = 2 # macro +mmSDMA2_CNTL = 0x001c # macro +mmSDMA2_CNTL_BASE_IDX = 2 # macro +mmSDMA2_CHICKEN_BITS = 0x001d # macro +mmSDMA2_CHICKEN_BITS_BASE_IDX = 2 # macro +mmSDMA2_GB_ADDR_CONFIG = 0x001e # macro +mmSDMA2_GB_ADDR_CONFIG_BASE_IDX = 2 # macro +mmSDMA2_GB_ADDR_CONFIG_READ = 0x001f # macro +mmSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX = 2 # macro +mmSDMA2_RB_RPTR_FETCH_HI = 0x0020 # macro +mmSDMA2_RB_RPTR_FETCH_HI_BASE_IDX = 2 # macro +mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL = 0x0021 # macro +mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RB_RPTR_FETCH = 0x0022 # macro +mmSDMA2_RB_RPTR_FETCH_BASE_IDX = 2 # macro +mmSDMA2_IB_OFFSET_FETCH = 0x0023 # macro +mmSDMA2_IB_OFFSET_FETCH_BASE_IDX = 2 # macro +mmSDMA2_PROGRAM = 0x0024 # macro +mmSDMA2_PROGRAM_BASE_IDX = 2 # macro +mmSDMA2_STATUS_REG = 0x0025 # macro +mmSDMA2_STATUS_REG_BASE_IDX = 2 # macro +mmSDMA2_STATUS1_REG = 0x0026 # macro +mmSDMA2_STATUS1_REG_BASE_IDX = 2 # macro +mmSDMA2_RD_BURST_CNTL = 0x0027 # macro +mmSDMA2_RD_BURST_CNTL_BASE_IDX = 2 # macro +mmSDMA2_HBM_PAGE_CONFIG = 0x0028 # macro +mmSDMA2_HBM_PAGE_CONFIG_BASE_IDX = 2 # macro +mmSDMA2_UCODE_CHECKSUM = 0x0029 # macro +mmSDMA2_UCODE_CHECKSUM_BASE_IDX = 2 # macro +mmSDMA2_F32_CNTL = 0x002a # macro +mmSDMA2_F32_CNTL_BASE_IDX = 2 # macro +mmSDMA2_FREEZE = 0x002b # macro +mmSDMA2_FREEZE_BASE_IDX = 2 # macro +mmSDMA2_PHASE0_QUANTUM = 0x002c # macro +mmSDMA2_PHASE0_QUANTUM_BASE_IDX = 2 # macro +mmSDMA2_PHASE1_QUANTUM = 0x002d # macro +mmSDMA2_PHASE1_QUANTUM_BASE_IDX = 2 # macro +mmSDMA2_EDC_CONFIG = 0x0032 # macro +mmSDMA2_EDC_CONFIG_BASE_IDX = 2 # macro +mmSDMA2_BA_THRESHOLD = 0x0033 # macro +mmSDMA2_BA_THRESHOLD_BASE_IDX = 2 # macro +mmSDMA2_ID = 0x0034 # macro +mmSDMA2_ID_BASE_IDX = 2 # macro +mmSDMA2_VERSION = 0x0035 # macro +mmSDMA2_VERSION_BASE_IDX = 2 # macro +mmSDMA2_EDC_COUNTER = 0x0036 # macro +mmSDMA2_EDC_COUNTER_BASE_IDX = 2 # macro +mmSDMA2_EDC_COUNTER_CLEAR = 0x0037 # macro +mmSDMA2_EDC_COUNTER_CLEAR_BASE_IDX = 2 # macro +mmSDMA2_STATUS2_REG = 0x0038 # macro +mmSDMA2_STATUS2_REG_BASE_IDX = 2 # macro +mmSDMA2_ATOMIC_CNTL = 0x0039 # macro +mmSDMA2_ATOMIC_CNTL_BASE_IDX = 2 # macro +mmSDMA2_ATOMIC_PREOP_LO = 0x003a # macro +mmSDMA2_ATOMIC_PREOP_LO_BASE_IDX = 2 # macro +mmSDMA2_ATOMIC_PREOP_HI = 0x003b # macro +mmSDMA2_ATOMIC_PREOP_HI_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_CNTL = 0x003c # macro +mmSDMA2_UTCL1_CNTL_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_WATERMK = 0x003d # macro +mmSDMA2_UTCL1_WATERMK_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_RD_STATUS = 0x003e # macro +mmSDMA2_UTCL1_RD_STATUS_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_WR_STATUS = 0x003f # macro +mmSDMA2_UTCL1_WR_STATUS_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_INV0 = 0x0040 # macro +mmSDMA2_UTCL1_INV0_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_INV1 = 0x0041 # macro +mmSDMA2_UTCL1_INV1_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_INV2 = 0x0042 # macro +mmSDMA2_UTCL1_INV2_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_RD_XNACK0 = 0x0043 # macro +mmSDMA2_UTCL1_RD_XNACK0_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_RD_XNACK1 = 0x0044 # macro +mmSDMA2_UTCL1_RD_XNACK1_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_WR_XNACK0 = 0x0045 # macro +mmSDMA2_UTCL1_WR_XNACK0_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_WR_XNACK1 = 0x0046 # macro +mmSDMA2_UTCL1_WR_XNACK1_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_TIMEOUT = 0x0047 # macro +mmSDMA2_UTCL1_TIMEOUT_BASE_IDX = 2 # macro +mmSDMA2_UTCL1_PAGE = 0x0048 # macro +mmSDMA2_UTCL1_PAGE_BASE_IDX = 2 # macro +mmSDMA2_RELAX_ORDERING_LUT = 0x004a # macro +mmSDMA2_RELAX_ORDERING_LUT_BASE_IDX = 2 # macro +mmSDMA2_CHICKEN_BITS_2 = 0x004b # macro +mmSDMA2_CHICKEN_BITS_2_BASE_IDX = 2 # macro +mmSDMA2_STATUS3_REG = 0x004c # macro +mmSDMA2_STATUS3_REG_BASE_IDX = 2 # macro +mmSDMA2_PHYSICAL_ADDR_LO = 0x004d # macro +mmSDMA2_PHYSICAL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_PHYSICAL_ADDR_HI = 0x004e # macro +mmSDMA2_PHYSICAL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_PHASE2_QUANTUM = 0x004f # macro +mmSDMA2_PHASE2_QUANTUM_BASE_IDX = 2 # macro +mmSDMA2_ERROR_LOG = 0x0050 # macro +mmSDMA2_ERROR_LOG_BASE_IDX = 2 # macro +mmSDMA2_PUB_DUMMY_REG0 = 0x0051 # macro +mmSDMA2_PUB_DUMMY_REG0_BASE_IDX = 2 # macro +mmSDMA2_PUB_DUMMY_REG1 = 0x0052 # macro +mmSDMA2_PUB_DUMMY_REG1_BASE_IDX = 2 # macro +mmSDMA2_PUB_DUMMY_REG2 = 0x0053 # macro +mmSDMA2_PUB_DUMMY_REG2_BASE_IDX = 2 # macro +mmSDMA2_PUB_DUMMY_REG3 = 0x0054 # macro +mmSDMA2_PUB_DUMMY_REG3_BASE_IDX = 2 # macro +mmSDMA2_F32_COUNTER = 0x0055 # macro +mmSDMA2_F32_COUNTER_BASE_IDX = 2 # macro +mmSDMA2_CRD_CNTL = 0x005b # macro +mmSDMA2_CRD_CNTL_BASE_IDX = 2 # macro +mmSDMA2_AQL_STATUS = 0x005f # macro +mmSDMA2_AQL_STATUS_BASE_IDX = 2 # macro +mmSDMA2_EA_DBIT_ADDR_DATA = 0x0060 # macro +mmSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX = 2 # macro +mmSDMA2_EA_DBIT_ADDR_INDEX = 0x0061 # macro +mmSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX = 2 # macro +mmSDMA2_TLBI_GCR_CNTL = 0x0062 # macro +mmSDMA2_TLBI_GCR_CNTL_BASE_IDX = 2 # macro +mmSDMA2_TILING_CONFIG = 0x0063 # macro +mmSDMA2_TILING_CONFIG_BASE_IDX = 2 # macro +mmSDMA2_INT_STATUS = 0x0070 # macro +mmSDMA2_INT_STATUS_BASE_IDX = 2 # macro +mmSDMA2_HOLE_ADDR_LO = 0x0072 # macro +mmSDMA2_HOLE_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_HOLE_ADDR_HI = 0x0073 # macro +mmSDMA2_HOLE_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_CLOCK_GATING_REG = 0x0075 # macro +mmSDMA2_CLOCK_GATING_REG_BASE_IDX = 2 # macro +mmSDMA2_STATUS4_REG = 0x0076 # macro +mmSDMA2_STATUS4_REG_BASE_IDX = 2 # macro +mmSDMA2_SCRATCH_RAM_DATA = 0x0077 # macro +mmSDMA2_SCRATCH_RAM_DATA_BASE_IDX = 2 # macro +mmSDMA2_SCRATCH_RAM_ADDR = 0x0078 # macro +mmSDMA2_SCRATCH_RAM_ADDR_BASE_IDX = 2 # macro +mmSDMA2_TIMESTAMP_CNTL = 0x0079 # macro +mmSDMA2_TIMESTAMP_CNTL_BASE_IDX = 2 # macro +mmSDMA2_STATUS5_REG = 0x007a # macro +mmSDMA2_STATUS5_REG_BASE_IDX = 2 # macro +mmSDMA2_QUEUE_RESET_REQ = 0x007b # macro +mmSDMA2_QUEUE_RESET_REQ_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_CNTL = 0x0080 # macro +mmSDMA2_GFX_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_BASE = 0x0081 # macro +mmSDMA2_GFX_RB_BASE_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_BASE_HI = 0x0082 # macro +mmSDMA2_GFX_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_RPTR = 0x0083 # macro +mmSDMA2_GFX_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_RPTR_HI = 0x0084 # macro +mmSDMA2_GFX_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_WPTR = 0x0085 # macro +mmSDMA2_GFX_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_WPTR_HI = 0x0086 # macro +mmSDMA2_GFX_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_WPTR_POLL_CNTL = 0x0087 # macro +mmSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_RPTR_ADDR_HI = 0x0088 # macro +mmSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_RPTR_ADDR_LO = 0x0089 # macro +mmSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_GFX_IB_CNTL = 0x008a # macro +mmSDMA2_GFX_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_GFX_IB_RPTR = 0x008b # macro +mmSDMA2_GFX_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_GFX_IB_OFFSET = 0x008c # macro +mmSDMA2_GFX_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_GFX_IB_BASE_LO = 0x008d # macro +mmSDMA2_GFX_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA2_GFX_IB_BASE_HI = 0x008e # macro +mmSDMA2_GFX_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_GFX_IB_SIZE = 0x008f # macro +mmSDMA2_GFX_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA2_GFX_SKIP_CNTL = 0x0090 # macro +mmSDMA2_GFX_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA2_GFX_CONTEXT_STATUS = 0x0091 # macro +mmSDMA2_GFX_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA2_GFX_DOORBELL = 0x0092 # macro +mmSDMA2_GFX_DOORBELL_BASE_IDX = 2 # macro +mmSDMA2_GFX_CONTEXT_CNTL = 0x0093 # macro +mmSDMA2_GFX_CONTEXT_CNTL_BASE_IDX = 2 # macro +mmSDMA2_GFX_STATUS = 0x00a8 # macro +mmSDMA2_GFX_STATUS_BASE_IDX = 2 # macro +mmSDMA2_GFX_DOORBELL_LOG = 0x00a9 # macro +mmSDMA2_GFX_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA2_GFX_WATERMARK = 0x00aa # macro +mmSDMA2_GFX_WATERMARK_BASE_IDX = 2 # macro +mmSDMA2_GFX_DOORBELL_OFFSET = 0x00ab # macro +mmSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_GFX_CSA_ADDR_LO = 0x00ac # macro +mmSDMA2_GFX_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_GFX_CSA_ADDR_HI = 0x00ad # macro +mmSDMA2_GFX_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_GFX_IB_SUB_REMAIN = 0x00af # macro +mmSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA2_GFX_PREEMPT = 0x00b0 # macro +mmSDMA2_GFX_PREEMPT_BASE_IDX = 2 # macro +mmSDMA2_GFX_DUMMY_REG = 0x00b1 # macro +mmSDMA2_GFX_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI = 0x00b2 # macro +mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO = 0x00b3 # macro +mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_GFX_RB_AQL_CNTL = 0x00b4 # macro +mmSDMA2_GFX_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_GFX_MINOR_PTR_UPDATE = 0x00b5 # macro +mmSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA2_GFX_MIDCMD_DATA0 = 0x00c0 # macro +mmSDMA2_GFX_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA2_GFX_MIDCMD_DATA1 = 0x00c1 # macro +mmSDMA2_GFX_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA2_GFX_MIDCMD_DATA2 = 0x00c2 # macro +mmSDMA2_GFX_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA2_GFX_MIDCMD_DATA3 = 0x00c3 # macro +mmSDMA2_GFX_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA2_GFX_MIDCMD_DATA4 = 0x00c4 # macro +mmSDMA2_GFX_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA2_GFX_MIDCMD_DATA5 = 0x00c5 # macro +mmSDMA2_GFX_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA2_GFX_MIDCMD_DATA6 = 0x00c6 # macro +mmSDMA2_GFX_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA2_GFX_MIDCMD_DATA7 = 0x00c7 # macro +mmSDMA2_GFX_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA2_GFX_MIDCMD_DATA8 = 0x00c8 # macro +mmSDMA2_GFX_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA2_GFX_MIDCMD_DATA9 = 0x00c9 # macro +mmSDMA2_GFX_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA2_GFX_MIDCMD_DATA10 = 0x00ca # macro +mmSDMA2_GFX_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA2_GFX_MIDCMD_CNTL = 0x00cb # macro +mmSDMA2_GFX_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_CNTL = 0x00d8 # macro +mmSDMA2_PAGE_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_BASE = 0x00d9 # macro +mmSDMA2_PAGE_RB_BASE_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_BASE_HI = 0x00da # macro +mmSDMA2_PAGE_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_RPTR = 0x00db # macro +mmSDMA2_PAGE_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_RPTR_HI = 0x00dc # macro +mmSDMA2_PAGE_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_WPTR = 0x00dd # macro +mmSDMA2_PAGE_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_WPTR_HI = 0x00de # macro +mmSDMA2_PAGE_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_WPTR_POLL_CNTL = 0x00df # macro +mmSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_RPTR_ADDR_HI = 0x00e0 # macro +mmSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_RPTR_ADDR_LO = 0x00e1 # macro +mmSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_PAGE_IB_CNTL = 0x00e2 # macro +mmSDMA2_PAGE_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_PAGE_IB_RPTR = 0x00e3 # macro +mmSDMA2_PAGE_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_PAGE_IB_OFFSET = 0x00e4 # macro +mmSDMA2_PAGE_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_PAGE_IB_BASE_LO = 0x00e5 # macro +mmSDMA2_PAGE_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA2_PAGE_IB_BASE_HI = 0x00e6 # macro +mmSDMA2_PAGE_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_PAGE_IB_SIZE = 0x00e7 # macro +mmSDMA2_PAGE_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA2_PAGE_SKIP_CNTL = 0x00e8 # macro +mmSDMA2_PAGE_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA2_PAGE_CONTEXT_STATUS = 0x00e9 # macro +mmSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA2_PAGE_DOORBELL = 0x00ea # macro +mmSDMA2_PAGE_DOORBELL_BASE_IDX = 2 # macro +mmSDMA2_PAGE_STATUS = 0x0100 # macro +mmSDMA2_PAGE_STATUS_BASE_IDX = 2 # macro +mmSDMA2_PAGE_DOORBELL_LOG = 0x0101 # macro +mmSDMA2_PAGE_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA2_PAGE_WATERMARK = 0x0102 # macro +mmSDMA2_PAGE_WATERMARK_BASE_IDX = 2 # macro +mmSDMA2_PAGE_DOORBELL_OFFSET = 0x0103 # macro +mmSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_PAGE_CSA_ADDR_LO = 0x0104 # macro +mmSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_PAGE_CSA_ADDR_HI = 0x0105 # macro +mmSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_PAGE_IB_SUB_REMAIN = 0x0107 # macro +mmSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA2_PAGE_PREEMPT = 0x0108 # macro +mmSDMA2_PAGE_PREEMPT_BASE_IDX = 2 # macro +mmSDMA2_PAGE_DUMMY_REG = 0x0109 # macro +mmSDMA2_PAGE_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI = 0x010a # macro +mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO = 0x010b # macro +mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_PAGE_RB_AQL_CNTL = 0x010c # macro +mmSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MINOR_PTR_UPDATE = 0x010d # macro +mmSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MIDCMD_DATA0 = 0x0118 # macro +mmSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MIDCMD_DATA1 = 0x0119 # macro +mmSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MIDCMD_DATA2 = 0x011a # macro +mmSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MIDCMD_DATA3 = 0x011b # macro +mmSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MIDCMD_DATA4 = 0x011c # macro +mmSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MIDCMD_DATA5 = 0x011d # macro +mmSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MIDCMD_DATA6 = 0x011e # macro +mmSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MIDCMD_DATA7 = 0x011f # macro +mmSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MIDCMD_DATA8 = 0x0120 # macro +mmSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MIDCMD_DATA9 = 0x0121 # macro +mmSDMA2_PAGE_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MIDCMD_DATA10 = 0x0122 # macro +mmSDMA2_PAGE_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA2_PAGE_MIDCMD_CNTL = 0x0123 # macro +mmSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_CNTL = 0x0130 # macro +mmSDMA2_RLC0_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_BASE = 0x0131 # macro +mmSDMA2_RLC0_RB_BASE_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_BASE_HI = 0x0132 # macro +mmSDMA2_RLC0_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_RPTR = 0x0133 # macro +mmSDMA2_RLC0_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_RPTR_HI = 0x0134 # macro +mmSDMA2_RLC0_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_WPTR = 0x0135 # macro +mmSDMA2_RLC0_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_WPTR_HI = 0x0136 # macro +mmSDMA2_RLC0_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_WPTR_POLL_CNTL = 0x0137 # macro +mmSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_RPTR_ADDR_HI = 0x0138 # macro +mmSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_RPTR_ADDR_LO = 0x0139 # macro +mmSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC0_IB_CNTL = 0x013a # macro +mmSDMA2_RLC0_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC0_IB_RPTR = 0x013b # macro +mmSDMA2_RLC0_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC0_IB_OFFSET = 0x013c # macro +mmSDMA2_RLC0_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC0_IB_BASE_LO = 0x013d # macro +mmSDMA2_RLC0_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC0_IB_BASE_HI = 0x013e # macro +mmSDMA2_RLC0_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC0_IB_SIZE = 0x013f # macro +mmSDMA2_RLC0_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA2_RLC0_SKIP_CNTL = 0x0140 # macro +mmSDMA2_RLC0_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC0_CONTEXT_STATUS = 0x0141 # macro +mmSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC0_DOORBELL = 0x0142 # macro +mmSDMA2_RLC0_DOORBELL_BASE_IDX = 2 # macro +mmSDMA2_RLC0_STATUS = 0x0158 # macro +mmSDMA2_RLC0_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC0_DOORBELL_LOG = 0x0159 # macro +mmSDMA2_RLC0_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA2_RLC0_WATERMARK = 0x015a # macro +mmSDMA2_RLC0_WATERMARK_BASE_IDX = 2 # macro +mmSDMA2_RLC0_DOORBELL_OFFSET = 0x015b # macro +mmSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC0_CSA_ADDR_LO = 0x015c # macro +mmSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC0_CSA_ADDR_HI = 0x015d # macro +mmSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC0_IB_SUB_REMAIN = 0x015f # macro +mmSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA2_RLC0_PREEMPT = 0x0160 # macro +mmSDMA2_RLC0_PREEMPT_BASE_IDX = 2 # macro +mmSDMA2_RLC0_DUMMY_REG = 0x0161 # macro +mmSDMA2_RLC0_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI = 0x0162 # macro +mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO = 0x0163 # macro +mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC0_RB_AQL_CNTL = 0x0164 # macro +mmSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MINOR_PTR_UPDATE = 0x0165 # macro +mmSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MIDCMD_DATA0 = 0x0170 # macro +mmSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MIDCMD_DATA1 = 0x0171 # macro +mmSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MIDCMD_DATA2 = 0x0172 # macro +mmSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MIDCMD_DATA3 = 0x0173 # macro +mmSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MIDCMD_DATA4 = 0x0174 # macro +mmSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MIDCMD_DATA5 = 0x0175 # macro +mmSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MIDCMD_DATA6 = 0x0176 # macro +mmSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MIDCMD_DATA7 = 0x0177 # macro +mmSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MIDCMD_DATA8 = 0x0178 # macro +mmSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MIDCMD_DATA9 = 0x0179 # macro +mmSDMA2_RLC0_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MIDCMD_DATA10 = 0x017a # macro +mmSDMA2_RLC0_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA2_RLC0_MIDCMD_CNTL = 0x017b # macro +mmSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_CNTL = 0x0188 # macro +mmSDMA2_RLC1_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_BASE = 0x0189 # macro +mmSDMA2_RLC1_RB_BASE_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_BASE_HI = 0x018a # macro +mmSDMA2_RLC1_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_RPTR = 0x018b # macro +mmSDMA2_RLC1_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_RPTR_HI = 0x018c # macro +mmSDMA2_RLC1_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_WPTR = 0x018d # macro +mmSDMA2_RLC1_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_WPTR_HI = 0x018e # macro +mmSDMA2_RLC1_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_WPTR_POLL_CNTL = 0x018f # macro +mmSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_RPTR_ADDR_HI = 0x0190 # macro +mmSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_RPTR_ADDR_LO = 0x0191 # macro +mmSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC1_IB_CNTL = 0x0192 # macro +mmSDMA2_RLC1_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC1_IB_RPTR = 0x0193 # macro +mmSDMA2_RLC1_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC1_IB_OFFSET = 0x0194 # macro +mmSDMA2_RLC1_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC1_IB_BASE_LO = 0x0195 # macro +mmSDMA2_RLC1_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC1_IB_BASE_HI = 0x0196 # macro +mmSDMA2_RLC1_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC1_IB_SIZE = 0x0197 # macro +mmSDMA2_RLC1_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA2_RLC1_SKIP_CNTL = 0x0198 # macro +mmSDMA2_RLC1_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC1_CONTEXT_STATUS = 0x0199 # macro +mmSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC1_DOORBELL = 0x019a # macro +mmSDMA2_RLC1_DOORBELL_BASE_IDX = 2 # macro +mmSDMA2_RLC1_STATUS = 0x01b0 # macro +mmSDMA2_RLC1_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC1_DOORBELL_LOG = 0x01b1 # macro +mmSDMA2_RLC1_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA2_RLC1_WATERMARK = 0x01b2 # macro +mmSDMA2_RLC1_WATERMARK_BASE_IDX = 2 # macro +mmSDMA2_RLC1_DOORBELL_OFFSET = 0x01b3 # macro +mmSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC1_CSA_ADDR_LO = 0x01b4 # macro +mmSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC1_CSA_ADDR_HI = 0x01b5 # macro +mmSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC1_IB_SUB_REMAIN = 0x01b7 # macro +mmSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA2_RLC1_PREEMPT = 0x01b8 # macro +mmSDMA2_RLC1_PREEMPT_BASE_IDX = 2 # macro +mmSDMA2_RLC1_DUMMY_REG = 0x01b9 # macro +mmSDMA2_RLC1_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI = 0x01ba # macro +mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO = 0x01bb # macro +mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC1_RB_AQL_CNTL = 0x01bc # macro +mmSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MINOR_PTR_UPDATE = 0x01bd # macro +mmSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MIDCMD_DATA0 = 0x01c8 # macro +mmSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MIDCMD_DATA1 = 0x01c9 # macro +mmSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MIDCMD_DATA2 = 0x01ca # macro +mmSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MIDCMD_DATA3 = 0x01cb # macro +mmSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MIDCMD_DATA4 = 0x01cc # macro +mmSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MIDCMD_DATA5 = 0x01cd # macro +mmSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MIDCMD_DATA6 = 0x01ce # macro +mmSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MIDCMD_DATA7 = 0x01cf # macro +mmSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MIDCMD_DATA8 = 0x01d0 # macro +mmSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MIDCMD_DATA9 = 0x01d1 # macro +mmSDMA2_RLC1_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MIDCMD_DATA10 = 0x01d2 # macro +mmSDMA2_RLC1_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA2_RLC1_MIDCMD_CNTL = 0x01d3 # macro +mmSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_CNTL = 0x01e0 # macro +mmSDMA2_RLC2_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_BASE = 0x01e1 # macro +mmSDMA2_RLC2_RB_BASE_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_BASE_HI = 0x01e2 # macro +mmSDMA2_RLC2_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_RPTR = 0x01e3 # macro +mmSDMA2_RLC2_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_RPTR_HI = 0x01e4 # macro +mmSDMA2_RLC2_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_WPTR = 0x01e5 # macro +mmSDMA2_RLC2_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_WPTR_HI = 0x01e6 # macro +mmSDMA2_RLC2_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_WPTR_POLL_CNTL = 0x01e7 # macro +mmSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_RPTR_ADDR_HI = 0x01e8 # macro +mmSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_RPTR_ADDR_LO = 0x01e9 # macro +mmSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC2_IB_CNTL = 0x01ea # macro +mmSDMA2_RLC2_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC2_IB_RPTR = 0x01eb # macro +mmSDMA2_RLC2_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC2_IB_OFFSET = 0x01ec # macro +mmSDMA2_RLC2_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC2_IB_BASE_LO = 0x01ed # macro +mmSDMA2_RLC2_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC2_IB_BASE_HI = 0x01ee # macro +mmSDMA2_RLC2_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC2_IB_SIZE = 0x01ef # macro +mmSDMA2_RLC2_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA2_RLC2_SKIP_CNTL = 0x01f0 # macro +mmSDMA2_RLC2_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC2_CONTEXT_STATUS = 0x01f1 # macro +mmSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC2_DOORBELL = 0x01f2 # macro +mmSDMA2_RLC2_DOORBELL_BASE_IDX = 2 # macro +mmSDMA2_RLC2_STATUS = 0x0208 # macro +mmSDMA2_RLC2_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC2_DOORBELL_LOG = 0x0209 # macro +mmSDMA2_RLC2_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA2_RLC2_WATERMARK = 0x020a # macro +mmSDMA2_RLC2_WATERMARK_BASE_IDX = 2 # macro +mmSDMA2_RLC2_DOORBELL_OFFSET = 0x020b # macro +mmSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC2_CSA_ADDR_LO = 0x020c # macro +mmSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC2_CSA_ADDR_HI = 0x020d # macro +mmSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC2_IB_SUB_REMAIN = 0x020f # macro +mmSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA2_RLC2_PREEMPT = 0x0210 # macro +mmSDMA2_RLC2_PREEMPT_BASE_IDX = 2 # macro +mmSDMA2_RLC2_DUMMY_REG = 0x0211 # macro +mmSDMA2_RLC2_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI = 0x0212 # macro +mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO = 0x0213 # macro +mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC2_RB_AQL_CNTL = 0x0214 # macro +mmSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MINOR_PTR_UPDATE = 0x0215 # macro +mmSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MIDCMD_DATA0 = 0x0220 # macro +mmSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MIDCMD_DATA1 = 0x0221 # macro +mmSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MIDCMD_DATA2 = 0x0222 # macro +mmSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MIDCMD_DATA3 = 0x0223 # macro +mmSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MIDCMD_DATA4 = 0x0224 # macro +mmSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MIDCMD_DATA5 = 0x0225 # macro +mmSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MIDCMD_DATA6 = 0x0226 # macro +mmSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MIDCMD_DATA7 = 0x0227 # macro +mmSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MIDCMD_DATA8 = 0x0228 # macro +mmSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MIDCMD_DATA9 = 0x0229 # macro +mmSDMA2_RLC2_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MIDCMD_DATA10 = 0x022a # macro +mmSDMA2_RLC2_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA2_RLC2_MIDCMD_CNTL = 0x022b # macro +mmSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_CNTL = 0x0238 # macro +mmSDMA2_RLC3_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_BASE = 0x0239 # macro +mmSDMA2_RLC3_RB_BASE_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_BASE_HI = 0x023a # macro +mmSDMA2_RLC3_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_RPTR = 0x023b # macro +mmSDMA2_RLC3_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_RPTR_HI = 0x023c # macro +mmSDMA2_RLC3_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_WPTR = 0x023d # macro +mmSDMA2_RLC3_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_WPTR_HI = 0x023e # macro +mmSDMA2_RLC3_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_WPTR_POLL_CNTL = 0x023f # macro +mmSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_RPTR_ADDR_HI = 0x0240 # macro +mmSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_RPTR_ADDR_LO = 0x0241 # macro +mmSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC3_IB_CNTL = 0x0242 # macro +mmSDMA2_RLC3_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC3_IB_RPTR = 0x0243 # macro +mmSDMA2_RLC3_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC3_IB_OFFSET = 0x0244 # macro +mmSDMA2_RLC3_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC3_IB_BASE_LO = 0x0245 # macro +mmSDMA2_RLC3_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC3_IB_BASE_HI = 0x0246 # macro +mmSDMA2_RLC3_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC3_IB_SIZE = 0x0247 # macro +mmSDMA2_RLC3_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA2_RLC3_SKIP_CNTL = 0x0248 # macro +mmSDMA2_RLC3_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC3_CONTEXT_STATUS = 0x0249 # macro +mmSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC3_DOORBELL = 0x024a # macro +mmSDMA2_RLC3_DOORBELL_BASE_IDX = 2 # macro +mmSDMA2_RLC3_STATUS = 0x0260 # macro +mmSDMA2_RLC3_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC3_DOORBELL_LOG = 0x0261 # macro +mmSDMA2_RLC3_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA2_RLC3_WATERMARK = 0x0262 # macro +mmSDMA2_RLC3_WATERMARK_BASE_IDX = 2 # macro +mmSDMA2_RLC3_DOORBELL_OFFSET = 0x0263 # macro +mmSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC3_CSA_ADDR_LO = 0x0264 # macro +mmSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC3_CSA_ADDR_HI = 0x0265 # macro +mmSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC3_IB_SUB_REMAIN = 0x0267 # macro +mmSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA2_RLC3_PREEMPT = 0x0268 # macro +mmSDMA2_RLC3_PREEMPT_BASE_IDX = 2 # macro +mmSDMA2_RLC3_DUMMY_REG = 0x0269 # macro +mmSDMA2_RLC3_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI = 0x026a # macro +mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO = 0x026b # macro +mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC3_RB_AQL_CNTL = 0x026c # macro +mmSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MINOR_PTR_UPDATE = 0x026d # macro +mmSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MIDCMD_DATA0 = 0x0278 # macro +mmSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MIDCMD_DATA1 = 0x0279 # macro +mmSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MIDCMD_DATA2 = 0x027a # macro +mmSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MIDCMD_DATA3 = 0x027b # macro +mmSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MIDCMD_DATA4 = 0x027c # macro +mmSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MIDCMD_DATA5 = 0x027d # macro +mmSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MIDCMD_DATA6 = 0x027e # macro +mmSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MIDCMD_DATA7 = 0x027f # macro +mmSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MIDCMD_DATA8 = 0x0280 # macro +mmSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MIDCMD_DATA9 = 0x0281 # macro +mmSDMA2_RLC3_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MIDCMD_DATA10 = 0x0282 # macro +mmSDMA2_RLC3_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA2_RLC3_MIDCMD_CNTL = 0x0283 # macro +mmSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_CNTL = 0x0290 # macro +mmSDMA2_RLC4_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_BASE = 0x0291 # macro +mmSDMA2_RLC4_RB_BASE_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_BASE_HI = 0x0292 # macro +mmSDMA2_RLC4_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_RPTR = 0x0293 # macro +mmSDMA2_RLC4_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_RPTR_HI = 0x0294 # macro +mmSDMA2_RLC4_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_WPTR = 0x0295 # macro +mmSDMA2_RLC4_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_WPTR_HI = 0x0296 # macro +mmSDMA2_RLC4_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_WPTR_POLL_CNTL = 0x0297 # macro +mmSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_RPTR_ADDR_HI = 0x0298 # macro +mmSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_RPTR_ADDR_LO = 0x0299 # macro +mmSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC4_IB_CNTL = 0x029a # macro +mmSDMA2_RLC4_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC4_IB_RPTR = 0x029b # macro +mmSDMA2_RLC4_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC4_IB_OFFSET = 0x029c # macro +mmSDMA2_RLC4_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC4_IB_BASE_LO = 0x029d # macro +mmSDMA2_RLC4_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC4_IB_BASE_HI = 0x029e # macro +mmSDMA2_RLC4_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC4_IB_SIZE = 0x029f # macro +mmSDMA2_RLC4_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA2_RLC4_SKIP_CNTL = 0x02a0 # macro +mmSDMA2_RLC4_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC4_CONTEXT_STATUS = 0x02a1 # macro +mmSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC4_DOORBELL = 0x02a2 # macro +mmSDMA2_RLC4_DOORBELL_BASE_IDX = 2 # macro +mmSDMA2_RLC4_STATUS = 0x02b8 # macro +mmSDMA2_RLC4_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC4_DOORBELL_LOG = 0x02b9 # macro +mmSDMA2_RLC4_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA2_RLC4_WATERMARK = 0x02ba # macro +mmSDMA2_RLC4_WATERMARK_BASE_IDX = 2 # macro +mmSDMA2_RLC4_DOORBELL_OFFSET = 0x02bb # macro +mmSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC4_CSA_ADDR_LO = 0x02bc # macro +mmSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC4_CSA_ADDR_HI = 0x02bd # macro +mmSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC4_IB_SUB_REMAIN = 0x02bf # macro +mmSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA2_RLC4_PREEMPT = 0x02c0 # macro +mmSDMA2_RLC4_PREEMPT_BASE_IDX = 2 # macro +mmSDMA2_RLC4_DUMMY_REG = 0x02c1 # macro +mmSDMA2_RLC4_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI = 0x02c2 # macro +mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO = 0x02c3 # macro +mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC4_RB_AQL_CNTL = 0x02c4 # macro +mmSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MINOR_PTR_UPDATE = 0x02c5 # macro +mmSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MIDCMD_DATA0 = 0x02d0 # macro +mmSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MIDCMD_DATA1 = 0x02d1 # macro +mmSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MIDCMD_DATA2 = 0x02d2 # macro +mmSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MIDCMD_DATA3 = 0x02d3 # macro +mmSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MIDCMD_DATA4 = 0x02d4 # macro +mmSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MIDCMD_DATA5 = 0x02d5 # macro +mmSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MIDCMD_DATA6 = 0x02d6 # macro +mmSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MIDCMD_DATA7 = 0x02d7 # macro +mmSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MIDCMD_DATA8 = 0x02d8 # macro +mmSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MIDCMD_DATA9 = 0x02d9 # macro +mmSDMA2_RLC4_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MIDCMD_DATA10 = 0x02da # macro +mmSDMA2_RLC4_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA2_RLC4_MIDCMD_CNTL = 0x02db # macro +mmSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_CNTL = 0x02e8 # macro +mmSDMA2_RLC5_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_BASE = 0x02e9 # macro +mmSDMA2_RLC5_RB_BASE_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_BASE_HI = 0x02ea # macro +mmSDMA2_RLC5_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_RPTR = 0x02eb # macro +mmSDMA2_RLC5_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_RPTR_HI = 0x02ec # macro +mmSDMA2_RLC5_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_WPTR = 0x02ed # macro +mmSDMA2_RLC5_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_WPTR_HI = 0x02ee # macro +mmSDMA2_RLC5_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_WPTR_POLL_CNTL = 0x02ef # macro +mmSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_RPTR_ADDR_HI = 0x02f0 # macro +mmSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_RPTR_ADDR_LO = 0x02f1 # macro +mmSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC5_IB_CNTL = 0x02f2 # macro +mmSDMA2_RLC5_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC5_IB_RPTR = 0x02f3 # macro +mmSDMA2_RLC5_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC5_IB_OFFSET = 0x02f4 # macro +mmSDMA2_RLC5_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC5_IB_BASE_LO = 0x02f5 # macro +mmSDMA2_RLC5_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC5_IB_BASE_HI = 0x02f6 # macro +mmSDMA2_RLC5_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC5_IB_SIZE = 0x02f7 # macro +mmSDMA2_RLC5_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA2_RLC5_SKIP_CNTL = 0x02f8 # macro +mmSDMA2_RLC5_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC5_CONTEXT_STATUS = 0x02f9 # macro +mmSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC5_DOORBELL = 0x02fa # macro +mmSDMA2_RLC5_DOORBELL_BASE_IDX = 2 # macro +mmSDMA2_RLC5_STATUS = 0x0310 # macro +mmSDMA2_RLC5_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC5_DOORBELL_LOG = 0x0311 # macro +mmSDMA2_RLC5_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA2_RLC5_WATERMARK = 0x0312 # macro +mmSDMA2_RLC5_WATERMARK_BASE_IDX = 2 # macro +mmSDMA2_RLC5_DOORBELL_OFFSET = 0x0313 # macro +mmSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC5_CSA_ADDR_LO = 0x0314 # macro +mmSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC5_CSA_ADDR_HI = 0x0315 # macro +mmSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC5_IB_SUB_REMAIN = 0x0317 # macro +mmSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA2_RLC5_PREEMPT = 0x0318 # macro +mmSDMA2_RLC5_PREEMPT_BASE_IDX = 2 # macro +mmSDMA2_RLC5_DUMMY_REG = 0x0319 # macro +mmSDMA2_RLC5_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI = 0x031a # macro +mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO = 0x031b # macro +mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC5_RB_AQL_CNTL = 0x031c # macro +mmSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MINOR_PTR_UPDATE = 0x031d # macro +mmSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MIDCMD_DATA0 = 0x0328 # macro +mmSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MIDCMD_DATA1 = 0x0329 # macro +mmSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MIDCMD_DATA2 = 0x032a # macro +mmSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MIDCMD_DATA3 = 0x032b # macro +mmSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MIDCMD_DATA4 = 0x032c # macro +mmSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MIDCMD_DATA5 = 0x032d # macro +mmSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MIDCMD_DATA6 = 0x032e # macro +mmSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MIDCMD_DATA7 = 0x032f # macro +mmSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MIDCMD_DATA8 = 0x0330 # macro +mmSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MIDCMD_DATA9 = 0x0331 # macro +mmSDMA2_RLC5_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MIDCMD_DATA10 = 0x0332 # macro +mmSDMA2_RLC5_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA2_RLC5_MIDCMD_CNTL = 0x0333 # macro +mmSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_CNTL = 0x0340 # macro +mmSDMA2_RLC6_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_BASE = 0x0341 # macro +mmSDMA2_RLC6_RB_BASE_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_BASE_HI = 0x0342 # macro +mmSDMA2_RLC6_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_RPTR = 0x0343 # macro +mmSDMA2_RLC6_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_RPTR_HI = 0x0344 # macro +mmSDMA2_RLC6_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_WPTR = 0x0345 # macro +mmSDMA2_RLC6_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_WPTR_HI = 0x0346 # macro +mmSDMA2_RLC6_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_WPTR_POLL_CNTL = 0x0347 # macro +mmSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_RPTR_ADDR_HI = 0x0348 # macro +mmSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_RPTR_ADDR_LO = 0x0349 # macro +mmSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC6_IB_CNTL = 0x034a # macro +mmSDMA2_RLC6_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC6_IB_RPTR = 0x034b # macro +mmSDMA2_RLC6_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC6_IB_OFFSET = 0x034c # macro +mmSDMA2_RLC6_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC6_IB_BASE_LO = 0x034d # macro +mmSDMA2_RLC6_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC6_IB_BASE_HI = 0x034e # macro +mmSDMA2_RLC6_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC6_IB_SIZE = 0x034f # macro +mmSDMA2_RLC6_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA2_RLC6_SKIP_CNTL = 0x0350 # macro +mmSDMA2_RLC6_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC6_CONTEXT_STATUS = 0x0351 # macro +mmSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC6_DOORBELL = 0x0352 # macro +mmSDMA2_RLC6_DOORBELL_BASE_IDX = 2 # macro +mmSDMA2_RLC6_STATUS = 0x0368 # macro +mmSDMA2_RLC6_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC6_DOORBELL_LOG = 0x0369 # macro +mmSDMA2_RLC6_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA2_RLC6_WATERMARK = 0x036a # macro +mmSDMA2_RLC6_WATERMARK_BASE_IDX = 2 # macro +mmSDMA2_RLC6_DOORBELL_OFFSET = 0x036b # macro +mmSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC6_CSA_ADDR_LO = 0x036c # macro +mmSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC6_CSA_ADDR_HI = 0x036d # macro +mmSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC6_IB_SUB_REMAIN = 0x036f # macro +mmSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA2_RLC6_PREEMPT = 0x0370 # macro +mmSDMA2_RLC6_PREEMPT_BASE_IDX = 2 # macro +mmSDMA2_RLC6_DUMMY_REG = 0x0371 # macro +mmSDMA2_RLC6_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI = 0x0372 # macro +mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO = 0x0373 # macro +mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC6_RB_AQL_CNTL = 0x0374 # macro +mmSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MINOR_PTR_UPDATE = 0x0375 # macro +mmSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MIDCMD_DATA0 = 0x0380 # macro +mmSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MIDCMD_DATA1 = 0x0381 # macro +mmSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MIDCMD_DATA2 = 0x0382 # macro +mmSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MIDCMD_DATA3 = 0x0383 # macro +mmSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MIDCMD_DATA4 = 0x0384 # macro +mmSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MIDCMD_DATA5 = 0x0385 # macro +mmSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MIDCMD_DATA6 = 0x0386 # macro +mmSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MIDCMD_DATA7 = 0x0387 # macro +mmSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MIDCMD_DATA8 = 0x0388 # macro +mmSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MIDCMD_DATA9 = 0x0389 # macro +mmSDMA2_RLC6_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MIDCMD_DATA10 = 0x038a # macro +mmSDMA2_RLC6_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA2_RLC6_MIDCMD_CNTL = 0x038b # macro +mmSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_CNTL = 0x0398 # macro +mmSDMA2_RLC7_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_BASE = 0x0399 # macro +mmSDMA2_RLC7_RB_BASE_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_BASE_HI = 0x039a # macro +mmSDMA2_RLC7_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_RPTR = 0x039b # macro +mmSDMA2_RLC7_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_RPTR_HI = 0x039c # macro +mmSDMA2_RLC7_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_WPTR = 0x039d # macro +mmSDMA2_RLC7_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_WPTR_HI = 0x039e # macro +mmSDMA2_RLC7_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_WPTR_POLL_CNTL = 0x039f # macro +mmSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_RPTR_ADDR_HI = 0x03a0 # macro +mmSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_RPTR_ADDR_LO = 0x03a1 # macro +mmSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC7_IB_CNTL = 0x03a2 # macro +mmSDMA2_RLC7_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC7_IB_RPTR = 0x03a3 # macro +mmSDMA2_RLC7_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA2_RLC7_IB_OFFSET = 0x03a4 # macro +mmSDMA2_RLC7_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC7_IB_BASE_LO = 0x03a5 # macro +mmSDMA2_RLC7_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC7_IB_BASE_HI = 0x03a6 # macro +mmSDMA2_RLC7_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC7_IB_SIZE = 0x03a7 # macro +mmSDMA2_RLC7_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA2_RLC7_SKIP_CNTL = 0x03a8 # macro +mmSDMA2_RLC7_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC7_CONTEXT_STATUS = 0x03a9 # macro +mmSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC7_DOORBELL = 0x03aa # macro +mmSDMA2_RLC7_DOORBELL_BASE_IDX = 2 # macro +mmSDMA2_RLC7_STATUS = 0x03c0 # macro +mmSDMA2_RLC7_STATUS_BASE_IDX = 2 # macro +mmSDMA2_RLC7_DOORBELL_LOG = 0x03c1 # macro +mmSDMA2_RLC7_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA2_RLC7_WATERMARK = 0x03c2 # macro +mmSDMA2_RLC7_WATERMARK_BASE_IDX = 2 # macro +mmSDMA2_RLC7_DOORBELL_OFFSET = 0x03c3 # macro +mmSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA2_RLC7_CSA_ADDR_LO = 0x03c4 # macro +mmSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC7_CSA_ADDR_HI = 0x03c5 # macro +mmSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC7_IB_SUB_REMAIN = 0x03c7 # macro +mmSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA2_RLC7_PREEMPT = 0x03c8 # macro +mmSDMA2_RLC7_PREEMPT_BASE_IDX = 2 # macro +mmSDMA2_RLC7_DUMMY_REG = 0x03c9 # macro +mmSDMA2_RLC7_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI = 0x03ca # macro +mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO = 0x03cb # macro +mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA2_RLC7_RB_AQL_CNTL = 0x03cc # macro +mmSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MINOR_PTR_UPDATE = 0x03cd # macro +mmSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MIDCMD_DATA0 = 0x03d8 # macro +mmSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MIDCMD_DATA1 = 0x03d9 # macro +mmSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MIDCMD_DATA2 = 0x03da # macro +mmSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MIDCMD_DATA3 = 0x03db # macro +mmSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MIDCMD_DATA4 = 0x03dc # macro +mmSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MIDCMD_DATA5 = 0x03dd # macro +mmSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MIDCMD_DATA6 = 0x03de # macro +mmSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MIDCMD_DATA7 = 0x03df # macro +mmSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MIDCMD_DATA8 = 0x03e0 # macro +mmSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MIDCMD_DATA9 = 0x03e1 # macro +mmSDMA2_RLC7_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MIDCMD_DATA10 = 0x03e2 # macro +mmSDMA2_RLC7_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA2_RLC7_MIDCMD_CNTL = 0x03e3 # macro +mmSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA3_DEC_START = 0x0400 # macro +mmSDMA3_DEC_START_BASE_IDX = 2 # macro +mmSDMA3_GLOBAL_TIMESTAMP_LO = 0x040f # macro +mmSDMA3_GLOBAL_TIMESTAMP_LO_BASE_IDX = 2 # macro +mmSDMA3_GLOBAL_TIMESTAMP_HI = 0x0410 # macro +mmSDMA3_GLOBAL_TIMESTAMP_HI_BASE_IDX = 2 # macro +mmSDMA3_PG_CNTL = 0x0416 # macro +mmSDMA3_PG_CNTL_BASE_IDX = 2 # macro +mmSDMA3_PG_CTX_LO = 0x0417 # macro +mmSDMA3_PG_CTX_LO_BASE_IDX = 2 # macro +mmSDMA3_PG_CTX_HI = 0x0418 # macro +mmSDMA3_PG_CTX_HI_BASE_IDX = 2 # macro +mmSDMA3_PG_CTX_CNTL = 0x0419 # macro +mmSDMA3_PG_CTX_CNTL_BASE_IDX = 2 # macro +mmSDMA3_POWER_CNTL = 0x041a # macro +mmSDMA3_POWER_CNTL_BASE_IDX = 2 # macro +mmSDMA3_CLK_CTRL = 0x041b # macro +mmSDMA3_CLK_CTRL_BASE_IDX = 2 # macro +mmSDMA3_CNTL = 0x041c # macro +mmSDMA3_CNTL_BASE_IDX = 2 # macro +mmSDMA3_CHICKEN_BITS = 0x041d # macro +mmSDMA3_CHICKEN_BITS_BASE_IDX = 2 # macro +mmSDMA3_GB_ADDR_CONFIG = 0x041e # macro +mmSDMA3_GB_ADDR_CONFIG_BASE_IDX = 2 # macro +mmSDMA3_GB_ADDR_CONFIG_READ = 0x041f # macro +mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX = 2 # macro +mmSDMA3_RB_RPTR_FETCH_HI = 0x0420 # macro +mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX = 2 # macro +mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL = 0x0421 # macro +mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RB_RPTR_FETCH = 0x0422 # macro +mmSDMA3_RB_RPTR_FETCH_BASE_IDX = 2 # macro +mmSDMA3_IB_OFFSET_FETCH = 0x0423 # macro +mmSDMA3_IB_OFFSET_FETCH_BASE_IDX = 2 # macro +mmSDMA3_PROGRAM = 0x0424 # macro +mmSDMA3_PROGRAM_BASE_IDX = 2 # macro +mmSDMA3_STATUS_REG = 0x0425 # macro +mmSDMA3_STATUS_REG_BASE_IDX = 2 # macro +mmSDMA3_STATUS1_REG = 0x0426 # macro +mmSDMA3_STATUS1_REG_BASE_IDX = 2 # macro +mmSDMA3_RD_BURST_CNTL = 0x0427 # macro +mmSDMA3_RD_BURST_CNTL_BASE_IDX = 2 # macro +mmSDMA3_HBM_PAGE_CONFIG = 0x0428 # macro +mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX = 2 # macro +mmSDMA3_UCODE_CHECKSUM = 0x0429 # macro +mmSDMA3_UCODE_CHECKSUM_BASE_IDX = 2 # macro +mmSDMA3_F32_CNTL = 0x042a # macro +mmSDMA3_F32_CNTL_BASE_IDX = 2 # macro +mmSDMA3_FREEZE = 0x042b # macro +mmSDMA3_FREEZE_BASE_IDX = 2 # macro +mmSDMA3_PHASE0_QUANTUM = 0x042c # macro +mmSDMA3_PHASE0_QUANTUM_BASE_IDX = 2 # macro +mmSDMA3_PHASE1_QUANTUM = 0x042d # macro +mmSDMA3_PHASE1_QUANTUM_BASE_IDX = 2 # macro +mmSDMA3_EDC_CONFIG = 0x0432 # macro +mmSDMA3_EDC_CONFIG_BASE_IDX = 2 # macro +mmSDMA3_BA_THRESHOLD = 0x0433 # macro +mmSDMA3_BA_THRESHOLD_BASE_IDX = 2 # macro +mmSDMA3_ID = 0x0434 # macro +mmSDMA3_ID_BASE_IDX = 2 # macro +mmSDMA3_VERSION = 0x0435 # macro +mmSDMA3_VERSION_BASE_IDX = 2 # macro +mmSDMA3_EDC_COUNTER = 0x0436 # macro +mmSDMA3_EDC_COUNTER_BASE_IDX = 2 # macro +mmSDMA3_EDC_COUNTER_CLEAR = 0x0437 # macro +mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX = 2 # macro +mmSDMA3_STATUS2_REG = 0x0438 # macro +mmSDMA3_STATUS2_REG_BASE_IDX = 2 # macro +mmSDMA3_ATOMIC_CNTL = 0x0439 # macro +mmSDMA3_ATOMIC_CNTL_BASE_IDX = 2 # macro +mmSDMA3_ATOMIC_PREOP_LO = 0x043a # macro +mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX = 2 # macro +mmSDMA3_ATOMIC_PREOP_HI = 0x043b # macro +mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_CNTL = 0x043c # macro +mmSDMA3_UTCL1_CNTL_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_WATERMK = 0x043d # macro +mmSDMA3_UTCL1_WATERMK_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_RD_STATUS = 0x043e # macro +mmSDMA3_UTCL1_RD_STATUS_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_WR_STATUS = 0x043f # macro +mmSDMA3_UTCL1_WR_STATUS_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_INV0 = 0x0440 # macro +mmSDMA3_UTCL1_INV0_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_INV1 = 0x0441 # macro +mmSDMA3_UTCL1_INV1_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_INV2 = 0x0442 # macro +mmSDMA3_UTCL1_INV2_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_RD_XNACK0 = 0x0443 # macro +mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_RD_XNACK1 = 0x0444 # macro +mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_WR_XNACK0 = 0x0445 # macro +mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_WR_XNACK1 = 0x0446 # macro +mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_TIMEOUT = 0x0447 # macro +mmSDMA3_UTCL1_TIMEOUT_BASE_IDX = 2 # macro +mmSDMA3_UTCL1_PAGE = 0x0448 # macro +mmSDMA3_UTCL1_PAGE_BASE_IDX = 2 # macro +mmSDMA3_RELAX_ORDERING_LUT = 0x044a # macro +mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX = 2 # macro +mmSDMA3_CHICKEN_BITS_2 = 0x044b # macro +mmSDMA3_CHICKEN_BITS_2_BASE_IDX = 2 # macro +mmSDMA3_STATUS3_REG = 0x044c # macro +mmSDMA3_STATUS3_REG_BASE_IDX = 2 # macro +mmSDMA3_PHYSICAL_ADDR_LO = 0x044d # macro +mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_PHYSICAL_ADDR_HI = 0x044e # macro +mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_PHASE2_QUANTUM = 0x044f # macro +mmSDMA3_PHASE2_QUANTUM_BASE_IDX = 2 # macro +mmSDMA3_ERROR_LOG = 0x0450 # macro +mmSDMA3_ERROR_LOG_BASE_IDX = 2 # macro +mmSDMA3_PUB_DUMMY_REG0 = 0x0451 # macro +mmSDMA3_PUB_DUMMY_REG0_BASE_IDX = 2 # macro +mmSDMA3_PUB_DUMMY_REG1 = 0x0452 # macro +mmSDMA3_PUB_DUMMY_REG1_BASE_IDX = 2 # macro +mmSDMA3_PUB_DUMMY_REG2 = 0x0453 # macro +mmSDMA3_PUB_DUMMY_REG2_BASE_IDX = 2 # macro +mmSDMA3_PUB_DUMMY_REG3 = 0x0454 # macro +mmSDMA3_PUB_DUMMY_REG3_BASE_IDX = 2 # macro +mmSDMA3_F32_COUNTER = 0x0455 # macro +mmSDMA3_F32_COUNTER_BASE_IDX = 2 # macro +mmSDMA3_CRD_CNTL = 0x045b # macro +mmSDMA3_CRD_CNTL_BASE_IDX = 2 # macro +mmSDMA3_AQL_STATUS = 0x045f # macro +mmSDMA3_AQL_STATUS_BASE_IDX = 2 # macro +mmSDMA3_EA_DBIT_ADDR_DATA = 0x0460 # macro +mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX = 2 # macro +mmSDMA3_EA_DBIT_ADDR_INDEX = 0x0461 # macro +mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX = 2 # macro +mmSDMA3_TLBI_GCR_CNTL = 0x0462 # macro +mmSDMA3_TLBI_GCR_CNTL_BASE_IDX = 2 # macro +mmSDMA3_TILING_CONFIG = 0x0463 # macro +mmSDMA3_TILING_CONFIG_BASE_IDX = 2 # macro +mmSDMA3_INT_STATUS = 0x0470 # macro +mmSDMA3_INT_STATUS_BASE_IDX = 2 # macro +mmSDMA3_HOLE_ADDR_LO = 0x0472 # macro +mmSDMA3_HOLE_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_HOLE_ADDR_HI = 0x0473 # macro +mmSDMA3_HOLE_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_CLOCK_GATING_REG = 0x0475 # macro +mmSDMA3_CLOCK_GATING_REG_BASE_IDX = 2 # macro +mmSDMA3_STATUS4_REG = 0x0476 # macro +mmSDMA3_STATUS4_REG_BASE_IDX = 2 # macro +mmSDMA3_SCRATCH_RAM_DATA = 0x0477 # macro +mmSDMA3_SCRATCH_RAM_DATA_BASE_IDX = 2 # macro +mmSDMA3_SCRATCH_RAM_ADDR = 0x0478 # macro +mmSDMA3_SCRATCH_RAM_ADDR_BASE_IDX = 2 # macro +mmSDMA3_TIMESTAMP_CNTL = 0x0479 # macro +mmSDMA3_TIMESTAMP_CNTL_BASE_IDX = 2 # macro +mmSDMA3_STATUS5_REG = 0x047a # macro +mmSDMA3_STATUS5_REG_BASE_IDX = 2 # macro +mmSDMA3_QUEUE_RESET_REQ = 0x047b # macro +mmSDMA3_QUEUE_RESET_REQ_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_CNTL = 0x0480 # macro +mmSDMA3_GFX_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_BASE = 0x0481 # macro +mmSDMA3_GFX_RB_BASE_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_BASE_HI = 0x0482 # macro +mmSDMA3_GFX_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_RPTR = 0x0483 # macro +mmSDMA3_GFX_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_RPTR_HI = 0x0484 # macro +mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_WPTR = 0x0485 # macro +mmSDMA3_GFX_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_WPTR_HI = 0x0486 # macro +mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_WPTR_POLL_CNTL = 0x0487 # macro +mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_RPTR_ADDR_HI = 0x0488 # macro +mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_RPTR_ADDR_LO = 0x0489 # macro +mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_GFX_IB_CNTL = 0x048a # macro +mmSDMA3_GFX_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_GFX_IB_RPTR = 0x048b # macro +mmSDMA3_GFX_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_GFX_IB_OFFSET = 0x048c # macro +mmSDMA3_GFX_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_GFX_IB_BASE_LO = 0x048d # macro +mmSDMA3_GFX_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA3_GFX_IB_BASE_HI = 0x048e # macro +mmSDMA3_GFX_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_GFX_IB_SIZE = 0x048f # macro +mmSDMA3_GFX_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA3_GFX_SKIP_CNTL = 0x0490 # macro +mmSDMA3_GFX_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA3_GFX_CONTEXT_STATUS = 0x0491 # macro +mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA3_GFX_DOORBELL = 0x0492 # macro +mmSDMA3_GFX_DOORBELL_BASE_IDX = 2 # macro +mmSDMA3_GFX_CONTEXT_CNTL = 0x0493 # macro +mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX = 2 # macro +mmSDMA3_GFX_STATUS = 0x04a8 # macro +mmSDMA3_GFX_STATUS_BASE_IDX = 2 # macro +mmSDMA3_GFX_DOORBELL_LOG = 0x04a9 # macro +mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA3_GFX_WATERMARK = 0x04aa # macro +mmSDMA3_GFX_WATERMARK_BASE_IDX = 2 # macro +mmSDMA3_GFX_DOORBELL_OFFSET = 0x04ab # macro +mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_GFX_CSA_ADDR_LO = 0x04ac # macro +mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_GFX_CSA_ADDR_HI = 0x04ad # macro +mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_GFX_IB_SUB_REMAIN = 0x04af # macro +mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA3_GFX_PREEMPT = 0x04b0 # macro +mmSDMA3_GFX_PREEMPT_BASE_IDX = 2 # macro +mmSDMA3_GFX_DUMMY_REG = 0x04b1 # macro +mmSDMA3_GFX_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI = 0x04b2 # macro +mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO = 0x04b3 # macro +mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_GFX_RB_AQL_CNTL = 0x04b4 # macro +mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_GFX_MINOR_PTR_UPDATE = 0x04b5 # macro +mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA3_GFX_MIDCMD_DATA0 = 0x04c0 # macro +mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA3_GFX_MIDCMD_DATA1 = 0x04c1 # macro +mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA3_GFX_MIDCMD_DATA2 = 0x04c2 # macro +mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA3_GFX_MIDCMD_DATA3 = 0x04c3 # macro +mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA3_GFX_MIDCMD_DATA4 = 0x04c4 # macro +mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA3_GFX_MIDCMD_DATA5 = 0x04c5 # macro +mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA3_GFX_MIDCMD_DATA6 = 0x04c6 # macro +mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA3_GFX_MIDCMD_DATA7 = 0x04c7 # macro +mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA3_GFX_MIDCMD_DATA8 = 0x04c8 # macro +mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA3_GFX_MIDCMD_DATA9 = 0x04c9 # macro +mmSDMA3_GFX_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA3_GFX_MIDCMD_DATA10 = 0x04ca # macro +mmSDMA3_GFX_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA3_GFX_MIDCMD_CNTL = 0x04cb # macro +mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_CNTL = 0x04d8 # macro +mmSDMA3_PAGE_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_BASE = 0x04d9 # macro +mmSDMA3_PAGE_RB_BASE_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_BASE_HI = 0x04da # macro +mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_RPTR = 0x04db # macro +mmSDMA3_PAGE_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_RPTR_HI = 0x04dc # macro +mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_WPTR = 0x04dd # macro +mmSDMA3_PAGE_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_WPTR_HI = 0x04de # macro +mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_WPTR_POLL_CNTL = 0x04df # macro +mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_RPTR_ADDR_HI = 0x04e0 # macro +mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_RPTR_ADDR_LO = 0x04e1 # macro +mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_PAGE_IB_CNTL = 0x04e2 # macro +mmSDMA3_PAGE_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_PAGE_IB_RPTR = 0x04e3 # macro +mmSDMA3_PAGE_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_PAGE_IB_OFFSET = 0x04e4 # macro +mmSDMA3_PAGE_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_PAGE_IB_BASE_LO = 0x04e5 # macro +mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA3_PAGE_IB_BASE_HI = 0x04e6 # macro +mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_PAGE_IB_SIZE = 0x04e7 # macro +mmSDMA3_PAGE_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA3_PAGE_SKIP_CNTL = 0x04e8 # macro +mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA3_PAGE_CONTEXT_STATUS = 0x04e9 # macro +mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA3_PAGE_DOORBELL = 0x04ea # macro +mmSDMA3_PAGE_DOORBELL_BASE_IDX = 2 # macro +mmSDMA3_PAGE_STATUS = 0x0500 # macro +mmSDMA3_PAGE_STATUS_BASE_IDX = 2 # macro +mmSDMA3_PAGE_DOORBELL_LOG = 0x0501 # macro +mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA3_PAGE_WATERMARK = 0x0502 # macro +mmSDMA3_PAGE_WATERMARK_BASE_IDX = 2 # macro +mmSDMA3_PAGE_DOORBELL_OFFSET = 0x0503 # macro +mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_PAGE_CSA_ADDR_LO = 0x0504 # macro +mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_PAGE_CSA_ADDR_HI = 0x0505 # macro +mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_PAGE_IB_SUB_REMAIN = 0x0507 # macro +mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA3_PAGE_PREEMPT = 0x0508 # macro +mmSDMA3_PAGE_PREEMPT_BASE_IDX = 2 # macro +mmSDMA3_PAGE_DUMMY_REG = 0x0509 # macro +mmSDMA3_PAGE_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI = 0x050a # macro +mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO = 0x050b # macro +mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_PAGE_RB_AQL_CNTL = 0x050c # macro +mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MINOR_PTR_UPDATE = 0x050d # macro +mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MIDCMD_DATA0 = 0x0518 # macro +mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MIDCMD_DATA1 = 0x0519 # macro +mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MIDCMD_DATA2 = 0x051a # macro +mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MIDCMD_DATA3 = 0x051b # macro +mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MIDCMD_DATA4 = 0x051c # macro +mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MIDCMD_DATA5 = 0x051d # macro +mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MIDCMD_DATA6 = 0x051e # macro +mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MIDCMD_DATA7 = 0x051f # macro +mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MIDCMD_DATA8 = 0x0520 # macro +mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MIDCMD_DATA9 = 0x0521 # macro +mmSDMA3_PAGE_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MIDCMD_DATA10 = 0x0522 # macro +mmSDMA3_PAGE_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA3_PAGE_MIDCMD_CNTL = 0x0523 # macro +mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_CNTL = 0x0530 # macro +mmSDMA3_RLC0_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_BASE = 0x0531 # macro +mmSDMA3_RLC0_RB_BASE_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_BASE_HI = 0x0532 # macro +mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_RPTR = 0x0533 # macro +mmSDMA3_RLC0_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_RPTR_HI = 0x0534 # macro +mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_WPTR = 0x0535 # macro +mmSDMA3_RLC0_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_WPTR_HI = 0x0536 # macro +mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_WPTR_POLL_CNTL = 0x0537 # macro +mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_RPTR_ADDR_HI = 0x0538 # macro +mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_RPTR_ADDR_LO = 0x0539 # macro +mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC0_IB_CNTL = 0x053a # macro +mmSDMA3_RLC0_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC0_IB_RPTR = 0x053b # macro +mmSDMA3_RLC0_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC0_IB_OFFSET = 0x053c # macro +mmSDMA3_RLC0_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC0_IB_BASE_LO = 0x053d # macro +mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC0_IB_BASE_HI = 0x053e # macro +mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC0_IB_SIZE = 0x053f # macro +mmSDMA3_RLC0_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA3_RLC0_SKIP_CNTL = 0x0540 # macro +mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC0_CONTEXT_STATUS = 0x0541 # macro +mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC0_DOORBELL = 0x0542 # macro +mmSDMA3_RLC0_DOORBELL_BASE_IDX = 2 # macro +mmSDMA3_RLC0_STATUS = 0x0558 # macro +mmSDMA3_RLC0_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC0_DOORBELL_LOG = 0x0559 # macro +mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA3_RLC0_WATERMARK = 0x055a # macro +mmSDMA3_RLC0_WATERMARK_BASE_IDX = 2 # macro +mmSDMA3_RLC0_DOORBELL_OFFSET = 0x055b # macro +mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC0_CSA_ADDR_LO = 0x055c # macro +mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC0_CSA_ADDR_HI = 0x055d # macro +mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC0_IB_SUB_REMAIN = 0x055f # macro +mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA3_RLC0_PREEMPT = 0x0560 # macro +mmSDMA3_RLC0_PREEMPT_BASE_IDX = 2 # macro +mmSDMA3_RLC0_DUMMY_REG = 0x0561 # macro +mmSDMA3_RLC0_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI = 0x0562 # macro +mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO = 0x0563 # macro +mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC0_RB_AQL_CNTL = 0x0564 # macro +mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MINOR_PTR_UPDATE = 0x0565 # macro +mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MIDCMD_DATA0 = 0x0570 # macro +mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MIDCMD_DATA1 = 0x0571 # macro +mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MIDCMD_DATA2 = 0x0572 # macro +mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MIDCMD_DATA3 = 0x0573 # macro +mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MIDCMD_DATA4 = 0x0574 # macro +mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MIDCMD_DATA5 = 0x0575 # macro +mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MIDCMD_DATA6 = 0x0576 # macro +mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MIDCMD_DATA7 = 0x0577 # macro +mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MIDCMD_DATA8 = 0x0578 # macro +mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MIDCMD_DATA9 = 0x0579 # macro +mmSDMA3_RLC0_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MIDCMD_DATA10 = 0x057a # macro +mmSDMA3_RLC0_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA3_RLC0_MIDCMD_CNTL = 0x057b # macro +mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_CNTL = 0x0588 # macro +mmSDMA3_RLC1_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_BASE = 0x0589 # macro +mmSDMA3_RLC1_RB_BASE_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_BASE_HI = 0x058a # macro +mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_RPTR = 0x058b # macro +mmSDMA3_RLC1_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_RPTR_HI = 0x058c # macro +mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_WPTR = 0x058d # macro +mmSDMA3_RLC1_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_WPTR_HI = 0x058e # macro +mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_WPTR_POLL_CNTL = 0x058f # macro +mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_RPTR_ADDR_HI = 0x0590 # macro +mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_RPTR_ADDR_LO = 0x0591 # macro +mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC1_IB_CNTL = 0x0592 # macro +mmSDMA3_RLC1_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC1_IB_RPTR = 0x0593 # macro +mmSDMA3_RLC1_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC1_IB_OFFSET = 0x0594 # macro +mmSDMA3_RLC1_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC1_IB_BASE_LO = 0x0595 # macro +mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC1_IB_BASE_HI = 0x0596 # macro +mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC1_IB_SIZE = 0x0597 # macro +mmSDMA3_RLC1_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA3_RLC1_SKIP_CNTL = 0x0598 # macro +mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC1_CONTEXT_STATUS = 0x0599 # macro +mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC1_DOORBELL = 0x059a # macro +mmSDMA3_RLC1_DOORBELL_BASE_IDX = 2 # macro +mmSDMA3_RLC1_STATUS = 0x05b0 # macro +mmSDMA3_RLC1_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC1_DOORBELL_LOG = 0x05b1 # macro +mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA3_RLC1_WATERMARK = 0x05b2 # macro +mmSDMA3_RLC1_WATERMARK_BASE_IDX = 2 # macro +mmSDMA3_RLC1_DOORBELL_OFFSET = 0x05b3 # macro +mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC1_CSA_ADDR_LO = 0x05b4 # macro +mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC1_CSA_ADDR_HI = 0x05b5 # macro +mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC1_IB_SUB_REMAIN = 0x05b7 # macro +mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA3_RLC1_PREEMPT = 0x05b8 # macro +mmSDMA3_RLC1_PREEMPT_BASE_IDX = 2 # macro +mmSDMA3_RLC1_DUMMY_REG = 0x05b9 # macro +mmSDMA3_RLC1_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI = 0x05ba # macro +mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO = 0x05bb # macro +mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC1_RB_AQL_CNTL = 0x05bc # macro +mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MINOR_PTR_UPDATE = 0x05bd # macro +mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MIDCMD_DATA0 = 0x05c8 # macro +mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MIDCMD_DATA1 = 0x05c9 # macro +mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MIDCMD_DATA2 = 0x05ca # macro +mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MIDCMD_DATA3 = 0x05cb # macro +mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MIDCMD_DATA4 = 0x05cc # macro +mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MIDCMD_DATA5 = 0x05cd # macro +mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MIDCMD_DATA6 = 0x05ce # macro +mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MIDCMD_DATA7 = 0x05cf # macro +mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MIDCMD_DATA8 = 0x05d0 # macro +mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MIDCMD_DATA9 = 0x05d1 # macro +mmSDMA3_RLC1_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MIDCMD_DATA10 = 0x05d2 # macro +mmSDMA3_RLC1_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA3_RLC1_MIDCMD_CNTL = 0x05d3 # macro +mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_CNTL = 0x05e0 # macro +mmSDMA3_RLC2_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_BASE = 0x05e1 # macro +mmSDMA3_RLC2_RB_BASE_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_BASE_HI = 0x05e2 # macro +mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_RPTR = 0x05e3 # macro +mmSDMA3_RLC2_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_RPTR_HI = 0x05e4 # macro +mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_WPTR = 0x05e5 # macro +mmSDMA3_RLC2_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_WPTR_HI = 0x05e6 # macro +mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_WPTR_POLL_CNTL = 0x05e7 # macro +mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_RPTR_ADDR_HI = 0x05e8 # macro +mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_RPTR_ADDR_LO = 0x05e9 # macro +mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC2_IB_CNTL = 0x05ea # macro +mmSDMA3_RLC2_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC2_IB_RPTR = 0x05eb # macro +mmSDMA3_RLC2_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC2_IB_OFFSET = 0x05ec # macro +mmSDMA3_RLC2_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC2_IB_BASE_LO = 0x05ed # macro +mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC2_IB_BASE_HI = 0x05ee # macro +mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC2_IB_SIZE = 0x05ef # macro +mmSDMA3_RLC2_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA3_RLC2_SKIP_CNTL = 0x05f0 # macro +mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC2_CONTEXT_STATUS = 0x05f1 # macro +mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC2_DOORBELL = 0x05f2 # macro +mmSDMA3_RLC2_DOORBELL_BASE_IDX = 2 # macro +mmSDMA3_RLC2_STATUS = 0x0608 # macro +mmSDMA3_RLC2_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC2_DOORBELL_LOG = 0x0609 # macro +mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA3_RLC2_WATERMARK = 0x060a # macro +mmSDMA3_RLC2_WATERMARK_BASE_IDX = 2 # macro +mmSDMA3_RLC2_DOORBELL_OFFSET = 0x060b # macro +mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC2_CSA_ADDR_LO = 0x060c # macro +mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC2_CSA_ADDR_HI = 0x060d # macro +mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC2_IB_SUB_REMAIN = 0x060f # macro +mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA3_RLC2_PREEMPT = 0x0610 # macro +mmSDMA3_RLC2_PREEMPT_BASE_IDX = 2 # macro +mmSDMA3_RLC2_DUMMY_REG = 0x0611 # macro +mmSDMA3_RLC2_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI = 0x0612 # macro +mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO = 0x0613 # macro +mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC2_RB_AQL_CNTL = 0x0614 # macro +mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MINOR_PTR_UPDATE = 0x0615 # macro +mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MIDCMD_DATA0 = 0x0620 # macro +mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MIDCMD_DATA1 = 0x0621 # macro +mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MIDCMD_DATA2 = 0x0622 # macro +mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MIDCMD_DATA3 = 0x0623 # macro +mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MIDCMD_DATA4 = 0x0624 # macro +mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MIDCMD_DATA5 = 0x0625 # macro +mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MIDCMD_DATA6 = 0x0626 # macro +mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MIDCMD_DATA7 = 0x0627 # macro +mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MIDCMD_DATA8 = 0x0628 # macro +mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MIDCMD_DATA9 = 0x0629 # macro +mmSDMA3_RLC2_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MIDCMD_DATA10 = 0x062a # macro +mmSDMA3_RLC2_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA3_RLC2_MIDCMD_CNTL = 0x062b # macro +mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_CNTL = 0x0638 # macro +mmSDMA3_RLC3_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_BASE = 0x0639 # macro +mmSDMA3_RLC3_RB_BASE_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_BASE_HI = 0x063a # macro +mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_RPTR = 0x063b # macro +mmSDMA3_RLC3_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_RPTR_HI = 0x063c # macro +mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_WPTR = 0x063d # macro +mmSDMA3_RLC3_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_WPTR_HI = 0x063e # macro +mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_WPTR_POLL_CNTL = 0x063f # macro +mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_RPTR_ADDR_HI = 0x0640 # macro +mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_RPTR_ADDR_LO = 0x0641 # macro +mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC3_IB_CNTL = 0x0642 # macro +mmSDMA3_RLC3_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC3_IB_RPTR = 0x0643 # macro +mmSDMA3_RLC3_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC3_IB_OFFSET = 0x0644 # macro +mmSDMA3_RLC3_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC3_IB_BASE_LO = 0x0645 # macro +mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC3_IB_BASE_HI = 0x0646 # macro +mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC3_IB_SIZE = 0x0647 # macro +mmSDMA3_RLC3_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA3_RLC3_SKIP_CNTL = 0x0648 # macro +mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC3_CONTEXT_STATUS = 0x0649 # macro +mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC3_DOORBELL = 0x064a # macro +mmSDMA3_RLC3_DOORBELL_BASE_IDX = 2 # macro +mmSDMA3_RLC3_STATUS = 0x0660 # macro +mmSDMA3_RLC3_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC3_DOORBELL_LOG = 0x0661 # macro +mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA3_RLC3_WATERMARK = 0x0662 # macro +mmSDMA3_RLC3_WATERMARK_BASE_IDX = 2 # macro +mmSDMA3_RLC3_DOORBELL_OFFSET = 0x0663 # macro +mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC3_CSA_ADDR_LO = 0x0664 # macro +mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC3_CSA_ADDR_HI = 0x0665 # macro +mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC3_IB_SUB_REMAIN = 0x0667 # macro +mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA3_RLC3_PREEMPT = 0x0668 # macro +mmSDMA3_RLC3_PREEMPT_BASE_IDX = 2 # macro +mmSDMA3_RLC3_DUMMY_REG = 0x0669 # macro +mmSDMA3_RLC3_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI = 0x066a # macro +mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO = 0x066b # macro +mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC3_RB_AQL_CNTL = 0x066c # macro +mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MINOR_PTR_UPDATE = 0x066d # macro +mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MIDCMD_DATA0 = 0x0678 # macro +mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MIDCMD_DATA1 = 0x0679 # macro +mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MIDCMD_DATA2 = 0x067a # macro +mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MIDCMD_DATA3 = 0x067b # macro +mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MIDCMD_DATA4 = 0x067c # macro +mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MIDCMD_DATA5 = 0x067d # macro +mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MIDCMD_DATA6 = 0x067e # macro +mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MIDCMD_DATA7 = 0x067f # macro +mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MIDCMD_DATA8 = 0x0680 # macro +mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MIDCMD_DATA9 = 0x0681 # macro +mmSDMA3_RLC3_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MIDCMD_DATA10 = 0x0682 # macro +mmSDMA3_RLC3_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA3_RLC3_MIDCMD_CNTL = 0x0683 # macro +mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_CNTL = 0x0690 # macro +mmSDMA3_RLC4_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_BASE = 0x0691 # macro +mmSDMA3_RLC4_RB_BASE_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_BASE_HI = 0x0692 # macro +mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_RPTR = 0x0693 # macro +mmSDMA3_RLC4_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_RPTR_HI = 0x0694 # macro +mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_WPTR = 0x0695 # macro +mmSDMA3_RLC4_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_WPTR_HI = 0x0696 # macro +mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_WPTR_POLL_CNTL = 0x0697 # macro +mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_RPTR_ADDR_HI = 0x0698 # macro +mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_RPTR_ADDR_LO = 0x0699 # macro +mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC4_IB_CNTL = 0x069a # macro +mmSDMA3_RLC4_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC4_IB_RPTR = 0x069b # macro +mmSDMA3_RLC4_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC4_IB_OFFSET = 0x069c # macro +mmSDMA3_RLC4_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC4_IB_BASE_LO = 0x069d # macro +mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC4_IB_BASE_HI = 0x069e # macro +mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC4_IB_SIZE = 0x069f # macro +mmSDMA3_RLC4_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA3_RLC4_SKIP_CNTL = 0x06a0 # macro +mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC4_CONTEXT_STATUS = 0x06a1 # macro +mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC4_DOORBELL = 0x06a2 # macro +mmSDMA3_RLC4_DOORBELL_BASE_IDX = 2 # macro +mmSDMA3_RLC4_STATUS = 0x06b8 # macro +mmSDMA3_RLC4_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC4_DOORBELL_LOG = 0x06b9 # macro +mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA3_RLC4_WATERMARK = 0x06ba # macro +mmSDMA3_RLC4_WATERMARK_BASE_IDX = 2 # macro +mmSDMA3_RLC4_DOORBELL_OFFSET = 0x06bb # macro +mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC4_CSA_ADDR_LO = 0x06bc # macro +mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC4_CSA_ADDR_HI = 0x06bd # macro +mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC4_IB_SUB_REMAIN = 0x06bf # macro +mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA3_RLC4_PREEMPT = 0x06c0 # macro +mmSDMA3_RLC4_PREEMPT_BASE_IDX = 2 # macro +mmSDMA3_RLC4_DUMMY_REG = 0x06c1 # macro +mmSDMA3_RLC4_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI = 0x06c2 # macro +mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO = 0x06c3 # macro +mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC4_RB_AQL_CNTL = 0x06c4 # macro +mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MINOR_PTR_UPDATE = 0x06c5 # macro +mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MIDCMD_DATA0 = 0x06d0 # macro +mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MIDCMD_DATA1 = 0x06d1 # macro +mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MIDCMD_DATA2 = 0x06d2 # macro +mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MIDCMD_DATA3 = 0x06d3 # macro +mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MIDCMD_DATA4 = 0x06d4 # macro +mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MIDCMD_DATA5 = 0x06d5 # macro +mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MIDCMD_DATA6 = 0x06d6 # macro +mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MIDCMD_DATA7 = 0x06d7 # macro +mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MIDCMD_DATA8 = 0x06d8 # macro +mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MIDCMD_DATA9 = 0x06d9 # macro +mmSDMA3_RLC4_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MIDCMD_DATA10 = 0x06da # macro +mmSDMA3_RLC4_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA3_RLC4_MIDCMD_CNTL = 0x06db # macro +mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_CNTL = 0x06e8 # macro +mmSDMA3_RLC5_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_BASE = 0x06e9 # macro +mmSDMA3_RLC5_RB_BASE_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_BASE_HI = 0x06ea # macro +mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_RPTR = 0x06eb # macro +mmSDMA3_RLC5_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_RPTR_HI = 0x06ec # macro +mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_WPTR = 0x06ed # macro +mmSDMA3_RLC5_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_WPTR_HI = 0x06ee # macro +mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_WPTR_POLL_CNTL = 0x06ef # macro +mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_RPTR_ADDR_HI = 0x06f0 # macro +mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_RPTR_ADDR_LO = 0x06f1 # macro +mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC5_IB_CNTL = 0x06f2 # macro +mmSDMA3_RLC5_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC5_IB_RPTR = 0x06f3 # macro +mmSDMA3_RLC5_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC5_IB_OFFSET = 0x06f4 # macro +mmSDMA3_RLC5_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC5_IB_BASE_LO = 0x06f5 # macro +mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC5_IB_BASE_HI = 0x06f6 # macro +mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC5_IB_SIZE = 0x06f7 # macro +mmSDMA3_RLC5_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA3_RLC5_SKIP_CNTL = 0x06f8 # macro +mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC5_CONTEXT_STATUS = 0x06f9 # macro +mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC5_DOORBELL = 0x06fa # macro +mmSDMA3_RLC5_DOORBELL_BASE_IDX = 2 # macro +mmSDMA3_RLC5_STATUS = 0x0710 # macro +mmSDMA3_RLC5_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC5_DOORBELL_LOG = 0x0711 # macro +mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA3_RLC5_WATERMARK = 0x0712 # macro +mmSDMA3_RLC5_WATERMARK_BASE_IDX = 2 # macro +mmSDMA3_RLC5_DOORBELL_OFFSET = 0x0713 # macro +mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC5_CSA_ADDR_LO = 0x0714 # macro +mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC5_CSA_ADDR_HI = 0x0715 # macro +mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC5_IB_SUB_REMAIN = 0x0717 # macro +mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA3_RLC5_PREEMPT = 0x0718 # macro +mmSDMA3_RLC5_PREEMPT_BASE_IDX = 2 # macro +mmSDMA3_RLC5_DUMMY_REG = 0x0719 # macro +mmSDMA3_RLC5_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI = 0x071a # macro +mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO = 0x071b # macro +mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC5_RB_AQL_CNTL = 0x071c # macro +mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MINOR_PTR_UPDATE = 0x071d # macro +mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MIDCMD_DATA0 = 0x0728 # macro +mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MIDCMD_DATA1 = 0x0729 # macro +mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MIDCMD_DATA2 = 0x072a # macro +mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MIDCMD_DATA3 = 0x072b # macro +mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MIDCMD_DATA4 = 0x072c # macro +mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MIDCMD_DATA5 = 0x072d # macro +mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MIDCMD_DATA6 = 0x072e # macro +mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MIDCMD_DATA7 = 0x072f # macro +mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MIDCMD_DATA8 = 0x0730 # macro +mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MIDCMD_DATA9 = 0x0731 # macro +mmSDMA3_RLC5_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MIDCMD_DATA10 = 0x0732 # macro +mmSDMA3_RLC5_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA3_RLC5_MIDCMD_CNTL = 0x0733 # macro +mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_CNTL = 0x0740 # macro +mmSDMA3_RLC6_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_BASE = 0x0741 # macro +mmSDMA3_RLC6_RB_BASE_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_BASE_HI = 0x0742 # macro +mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_RPTR = 0x0743 # macro +mmSDMA3_RLC6_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_RPTR_HI = 0x0744 # macro +mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_WPTR = 0x0745 # macro +mmSDMA3_RLC6_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_WPTR_HI = 0x0746 # macro +mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_WPTR_POLL_CNTL = 0x0747 # macro +mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_RPTR_ADDR_HI = 0x0748 # macro +mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_RPTR_ADDR_LO = 0x0749 # macro +mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC6_IB_CNTL = 0x074a # macro +mmSDMA3_RLC6_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC6_IB_RPTR = 0x074b # macro +mmSDMA3_RLC6_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC6_IB_OFFSET = 0x074c # macro +mmSDMA3_RLC6_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC6_IB_BASE_LO = 0x074d # macro +mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC6_IB_BASE_HI = 0x074e # macro +mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC6_IB_SIZE = 0x074f # macro +mmSDMA3_RLC6_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA3_RLC6_SKIP_CNTL = 0x0750 # macro +mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC6_CONTEXT_STATUS = 0x0751 # macro +mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC6_DOORBELL = 0x0752 # macro +mmSDMA3_RLC6_DOORBELL_BASE_IDX = 2 # macro +mmSDMA3_RLC6_STATUS = 0x0768 # macro +mmSDMA3_RLC6_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC6_DOORBELL_LOG = 0x0769 # macro +mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA3_RLC6_WATERMARK = 0x076a # macro +mmSDMA3_RLC6_WATERMARK_BASE_IDX = 2 # macro +mmSDMA3_RLC6_DOORBELL_OFFSET = 0x076b # macro +mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC6_CSA_ADDR_LO = 0x076c # macro +mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC6_CSA_ADDR_HI = 0x076d # macro +mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC6_IB_SUB_REMAIN = 0x076f # macro +mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA3_RLC6_PREEMPT = 0x0770 # macro +mmSDMA3_RLC6_PREEMPT_BASE_IDX = 2 # macro +mmSDMA3_RLC6_DUMMY_REG = 0x0771 # macro +mmSDMA3_RLC6_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI = 0x0772 # macro +mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO = 0x0773 # macro +mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC6_RB_AQL_CNTL = 0x0774 # macro +mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MINOR_PTR_UPDATE = 0x0775 # macro +mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MIDCMD_DATA0 = 0x0780 # macro +mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MIDCMD_DATA1 = 0x0781 # macro +mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MIDCMD_DATA2 = 0x0782 # macro +mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MIDCMD_DATA3 = 0x0783 # macro +mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MIDCMD_DATA4 = 0x0784 # macro +mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MIDCMD_DATA5 = 0x0785 # macro +mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MIDCMD_DATA6 = 0x0786 # macro +mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MIDCMD_DATA7 = 0x0787 # macro +mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MIDCMD_DATA8 = 0x0788 # macro +mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MIDCMD_DATA9 = 0x0789 # macro +mmSDMA3_RLC6_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MIDCMD_DATA10 = 0x078a # macro +mmSDMA3_RLC6_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA3_RLC6_MIDCMD_CNTL = 0x078b # macro +mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_CNTL = 0x0798 # macro +mmSDMA3_RLC7_RB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_BASE = 0x0799 # macro +mmSDMA3_RLC7_RB_BASE_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_BASE_HI = 0x079a # macro +mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_RPTR = 0x079b # macro +mmSDMA3_RLC7_RB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_RPTR_HI = 0x079c # macro +mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_WPTR = 0x079d # macro +mmSDMA3_RLC7_RB_WPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_WPTR_HI = 0x079e # macro +mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_WPTR_POLL_CNTL = 0x079f # macro +mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_RPTR_ADDR_HI = 0x07a0 # macro +mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_RPTR_ADDR_LO = 0x07a1 # macro +mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC7_IB_CNTL = 0x07a2 # macro +mmSDMA3_RLC7_IB_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC7_IB_RPTR = 0x07a3 # macro +mmSDMA3_RLC7_IB_RPTR_BASE_IDX = 2 # macro +mmSDMA3_RLC7_IB_OFFSET = 0x07a4 # macro +mmSDMA3_RLC7_IB_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC7_IB_BASE_LO = 0x07a5 # macro +mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC7_IB_BASE_HI = 0x07a6 # macro +mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC7_IB_SIZE = 0x07a7 # macro +mmSDMA3_RLC7_IB_SIZE_BASE_IDX = 2 # macro +mmSDMA3_RLC7_SKIP_CNTL = 0x07a8 # macro +mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC7_CONTEXT_STATUS = 0x07a9 # macro +mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC7_DOORBELL = 0x07aa # macro +mmSDMA3_RLC7_DOORBELL_BASE_IDX = 2 # macro +mmSDMA3_RLC7_STATUS = 0x07c0 # macro +mmSDMA3_RLC7_STATUS_BASE_IDX = 2 # macro +mmSDMA3_RLC7_DOORBELL_LOG = 0x07c1 # macro +mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX = 2 # macro +mmSDMA3_RLC7_WATERMARK = 0x07c2 # macro +mmSDMA3_RLC7_WATERMARK_BASE_IDX = 2 # macro +mmSDMA3_RLC7_DOORBELL_OFFSET = 0x07c3 # macro +mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX = 2 # macro +mmSDMA3_RLC7_CSA_ADDR_LO = 0x07c4 # macro +mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC7_CSA_ADDR_HI = 0x07c5 # macro +mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC7_IB_SUB_REMAIN = 0x07c7 # macro +mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX = 2 # macro +mmSDMA3_RLC7_PREEMPT = 0x07c8 # macro +mmSDMA3_RLC7_PREEMPT_BASE_IDX = 2 # macro +mmSDMA3_RLC7_DUMMY_REG = 0x07c9 # macro +mmSDMA3_RLC7_DUMMY_REG_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI = 0x07ca # macro +mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO = 0x07cb # macro +mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX = 2 # macro +mmSDMA3_RLC7_RB_AQL_CNTL = 0x07cc # macro +mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MINOR_PTR_UPDATE = 0x07cd # macro +mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MIDCMD_DATA0 = 0x07d8 # macro +mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MIDCMD_DATA1 = 0x07d9 # macro +mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MIDCMD_DATA2 = 0x07da # macro +mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MIDCMD_DATA3 = 0x07db # macro +mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MIDCMD_DATA4 = 0x07dc # macro +mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MIDCMD_DATA5 = 0x07dd # macro +mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MIDCMD_DATA6 = 0x07de # macro +mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MIDCMD_DATA7 = 0x07df # macro +mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MIDCMD_DATA8 = 0x07e0 # macro +mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MIDCMD_DATA9 = 0x07e1 # macro +mmSDMA3_RLC7_MIDCMD_DATA9_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MIDCMD_DATA10 = 0x07e2 # macro +mmSDMA3_RLC7_MIDCMD_DATA10_BASE_IDX = 2 # macro +mmSDMA3_RLC7_MIDCMD_CNTL = 0x07e3 # macro +mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX = 2 # macro +ixPCC_STALL_PATTERN_CTRL = 0x0000 # macro +ixPWRBRK_STALL_PATTERN_CTRL = 0x0001 # macro +ixPCC_STALL_PATTERN_1_2 = 0x0006 # macro +ixPCC_STALL_PATTERN_3_4 = 0x0007 # macro +ixPCC_STALL_PATTERN_5_6 = 0x0008 # macro +ixPCC_STALL_PATTERN_7 = 0x0009 # macro +ixPWRBRK_STALL_PATTERN_1_2 = 0x000a # macro +ixPWRBRK_STALL_PATTERN_3_4 = 0x000b # macro +ixPWRBRK_STALL_PATTERN_5_6 = 0x000c # macro +ixPWRBRK_STALL_PATTERN_7 = 0x000d # macro +ixPCC_PWRBRK_HYSTERESIS_CTRL = 0x000e # macro +ixEDC_STRETCH_PERF_COUNTER = 0x000f # macro +ixEDC_UNSTRETCH_PERF_COUNTER = 0x0010 # macro +ixEDC_STRETCH_NUM_PERF_COUNTER = 0x0011 # macro +ixGC_CAC_OVR_SEL = 0x0022 # macro +ixGC_CAC_OVR_VAL = 0x0023 # macro +ixGC_CAC_WEIGHT_BCI_0 = 0x0024 # macro +ixGC_CAC_WEIGHT_CB_0 = 0x0025 # macro +ixGC_CAC_WEIGHT_CB_1 = 0x0026 # macro +ixGC_CAC_WEIGHT_CB_2 = 0x0027 # macro +ixGC_CAC_WEIGHT_CB_3 = 0x0028 # macro +ixGC_CAC_WEIGHT_CB_4 = 0x0029 # macro +ixGC_CAC_WEIGHT_CP_0 = 0x002a # macro +ixGC_CAC_WEIGHT_CP_1 = 0x002b # macro +ixGC_CAC_WEIGHT_DB_0 = 0x002c # macro +ixGC_CAC_WEIGHT_DB_1 = 0x002d # macro +ixGC_CAC_WEIGHT_DB_2 = 0x002e # macro +ixGC_CAC_WEIGHT_DB_3 = 0x002f # macro +ixGC_CAC_WEIGHT_DB_4 = 0x0030 # macro +ixGC_CAC_WEIGHT_GDS_0 = 0x0031 # macro +ixGC_CAC_WEIGHT_GDS_1 = 0x0032 # macro +ixGC_CAC_WEIGHT_GDS_2 = 0x0033 # macro +ixGC_CAC_WEIGHT_LDS_0 = 0x0034 # macro +ixGC_CAC_WEIGHT_LDS_1 = 0x0035 # macro +ixGC_CAC_WEIGHT_LDS_2 = 0x0036 # macro +ixGC_CAC_WEIGHT_LDS_3 = 0x0037 # macro +ixGC_CAC_WEIGHT_LDS_4 = 0x0038 # macro +ixGC_CAC_WEIGHT_PA_0 = 0x0039 # macro +ixGC_CAC_WEIGHT_PA_1 = 0x003a # macro +ixGC_CAC_WEIGHT_PA_2 = 0x003b # macro +ixGC_CAC_WEIGHT_PA_3 = 0x003c # macro +ixGC_CAC_WEIGHT_PC_0 = 0x003d # macro +ixGC_CAC_WEIGHT_SC_0 = 0x003e # macro +ixGC_CAC_WEIGHT_SC_1 = 0x003f # macro +ixGC_CAC_WEIGHT_SC_2 = 0x0040 # macro +ixGC_CAC_WEIGHT_SC_3 = 0x0041 # macro +ixGC_CAC_WEIGHT_SPI_0 = 0x0042 # macro +ixGC_CAC_WEIGHT_SPI_1 = 0x0043 # macro +ixGC_CAC_WEIGHT_SPI_2 = 0x0044 # macro +ixGC_CAC_WEIGHT_SQ_0 = 0x0045 # macro +ixGC_CAC_WEIGHT_SQ_1 = 0x0046 # macro +ixGC_CAC_WEIGHT_SQ_2 = 0x0047 # macro +ixGC_CAC_WEIGHT_SQ_3 = 0x0048 # macro +ixGC_CAC_WEIGHT_SX_0 = 0x0049 # macro +ixGC_CAC_WEIGHT_SXRB_0 = 0x004a # macro +ixGC_CAC_WEIGHT_TA_0 = 0x004b # macro +ixGC_CAC_WEIGHT_TCP_0 = 0x004c # macro +ixGC_CAC_WEIGHT_TCP_1 = 0x004d # macro +ixGC_CAC_WEIGHT_TCP_2 = 0x004e # macro +ixGC_CAC_WEIGHT_TCP_3 = 0x004f # macro +ixGC_CAC_WEIGHT_TD_0 = 0x0050 # macro +ixGC_CAC_WEIGHT_TD_1 = 0x0051 # macro +ixGC_CAC_WEIGHT_TD_2 = 0x0052 # macro +ixGC_CAC_WEIGHT_TD_3 = 0x0053 # macro +ixGC_CAC_WEIGHT_TD_4 = 0x0054 # macro +ixGC_CAC_WEIGHT_TD_5 = 0x0055 # macro +ixGC_CAC_WEIGHT_RMI_0 = 0x0056 # macro +ixGC_CAC_WEIGHT_RMI_1 = 0x0057 # macro +ixGC_CAC_WEIGHT_EA_0 = 0x0058 # macro +ixGC_CAC_WEIGHT_EA_1 = 0x0059 # macro +ixGC_CAC_WEIGHT_EA_2 = 0x005a # macro +ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 = 0x005b # macro +ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 = 0x005c # macro +ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 = 0x005d # macro +ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 = 0x005e # macro +ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 = 0x005f # macro +ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 = 0x0060 # macro +ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 = 0x0061 # macro +ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 = 0x0062 # macro +ixGC_CAC_WEIGHT_UTCL2_VML2_0 = 0x0063 # macro +ixGC_CAC_WEIGHT_UTCL2_VML2_1 = 0x0064 # macro +ixGC_CAC_WEIGHT_UTCL2_VML2_2 = 0x0065 # macro +ixGC_CAC_WEIGHT_UTCL2_WALKER_0 = 0x0066 # macro +ixGC_CAC_WEIGHT_UTCL2_WALKER_1 = 0x0067 # macro +ixGC_CAC_WEIGHT_UTCL2_WALKER_2 = 0x0068 # macro +ixGC_CAC_WEIGHT_CU_0 = 0x0069 # macro +ixGC_CAC_WEIGHT_UTCL1_0 = 0x006a # macro +ixGC_CAC_WEIGHT_GE_0 = 0x006b # macro +ixGC_CAC_WEIGHT_GE_1 = 0x006c # macro +ixGC_CAC_WEIGHT_GE_2 = 0x006d # macro +ixGC_CAC_WEIGHT_GE_3 = 0x006e # macro +ixGC_CAC_WEIGHT_GE_4 = 0x006f # macro +ixGC_CAC_WEIGHT_GE_5 = 0x0070 # macro +ixGC_CAC_WEIGHT_GE_6 = 0x0071 # macro +ixGC_CAC_WEIGHT_GE_7 = 0x0072 # macro +ixGC_CAC_WEIGHT_GE_8 = 0x0073 # macro +ixGC_CAC_WEIGHT_GE_9 = 0x0074 # macro +ixGC_CAC_WEIGHT_GE_10 = 0x0075 # macro +ixGC_CAC_WEIGHT_PMM_0 = 0x0076 # macro +ixGC_CAC_WEIGHT_GL2C_0 = 0x0077 # macro +ixGC_CAC_WEIGHT_GL2C_1 = 0x0078 # macro +ixGC_CAC_WEIGHT_GL2C_2 = 0x0079 # macro +ixGC_CAC_WEIGHT_GUS_0 = 0x007a # macro +ixGC_CAC_WEIGHT_GUS_1 = 0x007b # macro +ixGC_CAC_WEIGHT_PH_0 = 0x007c # macro +ixGC_CAC_WEIGHT_PH_1 = 0x007d # macro +ixGC_CAC_WEIGHT_PH_2 = 0x007e # macro +ixGC_CAC_WEIGHT_PH_3 = 0x007f # macro +ixGC_CAC_WEIGHT_SDMA_0 = 0x0080 # macro +ixGC_CAC_WEIGHT_SDMA_1 = 0x0081 # macro +ixGC_CAC_WEIGHT_SDMA_2 = 0x0082 # macro +ixGC_CAC_WEIGHT_SDMA_3 = 0x0083 # macro +ixGC_CAC_WEIGHT_SDMA_4 = 0x0084 # macro +ixGC_CAC_WEIGHT_SDMA_5 = 0x0085 # macro +ixGC_CAC_WEIGHT_SP_0 = 0x0086 # macro +ixGC_CAC_WEIGHT_SP_1 = 0x0087 # macro +ixGC_CAC_WEIGHT_GL1C_0 = 0x0088 # macro +ixGC_CAC_WEIGHT_GL1C_1 = 0x0089 # macro +ixGC_CAC_WEIGHT_GL1C_2 = 0x008a # macro +ixGC_CAC_WEIGHT_CHC_0 = 0x008b # macro +ixGC_CAC_WEIGHT_CHC_1 = 0x008c # macro +ixGC_CAC_WEIGHT_SQC_0 = 0x008d # macro +ixGC_CAC_WEIGHT_SQC_1 = 0x008e # macro +ixGC_CAC_WEIGHT_RLC_0 = 0x008f # macro +ixGC_CAC_ACC_LDS0 = 0x0100 # macro +ixGC_CAC_ACC_LDS1 = 0x0101 # macro +ixGC_CAC_ACC_LDS2 = 0x0102 # macro +ixGC_CAC_ACC_LDS3 = 0x0103 # macro +ixGC_CAC_ACC_LDS4 = 0x0104 # macro +ixGC_CAC_ACC_LDS5 = 0x0105 # macro +ixGC_CAC_ACC_LDS6 = 0x0106 # macro +ixGC_CAC_ACC_LDS7 = 0x0107 # macro +ixGC_CAC_ACC_LDS8 = 0x0108 # macro +ixGC_CAC_ACC_BCI0 = 0x0109 # macro +ixGC_CAC_ACC_BCI1 = 0x010a # macro +ixGC_CAC_ACC_CB0 = 0x010b # macro +ixGC_CAC_ACC_CB1 = 0x010c # macro +ixGC_CAC_ACC_CB2 = 0x010d # macro +ixGC_CAC_ACC_CB3 = 0x010e # macro +ixGC_CAC_ACC_CB4 = 0x010f # macro +ixGC_CAC_ACC_CB5 = 0x0110 # macro +ixGC_CAC_ACC_CB6 = 0x0111 # macro +ixGC_CAC_ACC_CB7 = 0x0112 # macro +ixGC_CAC_ACC_CB8 = 0x0113 # macro +ixGC_CAC_ACC_CB9 = 0x0114 # macro +ixGC_CAC_ACC_DB0 = 0x0118 # macro +ixGC_CAC_ACC_DB1 = 0x0119 # macro +ixGC_CAC_ACC_DB2 = 0x011a # macro +ixGC_CAC_ACC_DB3 = 0x011b # macro +ixGC_CAC_ACC_DB4 = 0x011c # macro +ixGC_CAC_ACC_DB5 = 0x011d # macro +ixGC_CAC_ACC_DB6 = 0x011e # macro +ixGC_CAC_ACC_DB7 = 0x011f # macro +ixGC_CAC_ACC_DB8 = 0x0120 # macro +ixGC_CAC_ACC_DB9 = 0x0121 # macro +ixGC_CAC_ACC_GDS5 = 0x0127 # macro +ixGC_CAC_ACC_GDS6 = 0x0128 # macro +ixGC_CAC_ACC_PA0 = 0x0129 # macro +ixGC_CAC_ACC_PA1 = 0x012a # macro +ixGC_CAC_ACC_PA2 = 0x012b # macro +ixGC_CAC_ACC_PA3 = 0x012c # macro +ixGC_CAC_ACC_PA4 = 0x012d # macro +ixGC_CAC_ACC_PA5 = 0x012e # macro +ixGC_CAC_ACC_PA6 = 0x012f # macro +ixGC_CAC_ACC_PA7 = 0x0130 # macro +ixGC_CAC_ACC_PC0 = 0x0131 # macro +ixGC_CAC_ACC_SC0 = 0x0132 # macro +ixGC_CAC_ACC_SC1 = 0x0133 # macro +ixGC_CAC_ACC_SC2 = 0x0134 # macro +ixGC_CAC_ACC_SC3 = 0x0135 # macro +ixGC_CAC_ACC_SC4 = 0x0136 # macro +ixGC_CAC_ACC_SC5 = 0x0137 # macro +ixGC_CAC_ACC_SC6 = 0x0138 # macro +ixGC_CAC_ACC_SC7 = 0x0139 # macro +ixGC_CAC_ACC_SPI0 = 0x013a # macro +ixGC_CAC_ACC_SPI1 = 0x013b # macro +ixGC_CAC_ACC_SPI2 = 0x013c # macro +ixGC_CAC_ACC_SPI3 = 0x013d # macro +ixGC_CAC_ACC_SPI4 = 0x013e # macro +ixGC_CAC_ACC_SPI5 = 0x013f # macro +ixGC_CAC_ACC_SQ0_LOWER = 0x0140 # macro +ixGC_CAC_ACC_SQ0_UPPER = 0x0141 # macro +ixGC_CAC_ACC_SQ1_LOWER = 0x0142 # macro +ixGC_CAC_ACC_SQ1_UPPER = 0x0143 # macro +ixGC_CAC_ACC_SQ2_LOWER = 0x0144 # macro +ixGC_CAC_ACC_SQ2_UPPER = 0x0145 # macro +ixGC_CAC_ACC_SQ3_LOWER = 0x0146 # macro +ixGC_CAC_ACC_SQ3_UPPER = 0x0147 # macro +ixGC_CAC_ACC_SQ4_LOWER = 0x0148 # macro +ixGC_CAC_ACC_SQ4_UPPER = 0x0149 # macro +ixGC_CAC_ACC_SQ5_LOWER = 0x014a # macro +ixGC_CAC_ACC_SQ5_UPPER = 0x014b # macro +ixGC_CAC_ACC_SQ6_LOWER = 0x014c # macro +ixGC_CAC_ACC_SQ6_UPPER = 0x014d # macro +ixGC_CAC_ACC_SQ7_LOWER = 0x014e # macro +ixGC_CAC_ACC_SQ7_UPPER = 0x014f # macro +ixGC_CAC_ACC_SQ8_LOWER = 0x0150 # macro +ixGC_CAC_ACC_SQ8_UPPER = 0x0151 # macro +ixGC_CAC_ACC_SX0 = 0x0152 # macro +ixGC_CAC_ACC_SXRB0 = 0x0153 # macro +ixGC_CAC_ACC_TA0 = 0x0154 # macro +ixGC_CAC_ACC_TCP0 = 0x0155 # macro +ixGC_CAC_ACC_TCP1 = 0x0156 # macro +ixGC_CAC_ACC_TCP2 = 0x0157 # macro +ixGC_CAC_ACC_TCP3 = 0x0158 # macro +ixGC_CAC_ACC_TCP4 = 0x0159 # macro +ixGC_CAC_ACC_TCP5 = 0x015a # macro +ixGC_CAC_ACC_TCP6 = 0x015b # macro +ixGC_CAC_ACC_TCP7 = 0x015c # macro +ixGC_CAC_ACC_TD0 = 0x015d # macro +ixGC_CAC_ACC_TD1 = 0x015e # macro +ixGC_CAC_ACC_TD2 = 0x015f # macro +ixGC_CAC_ACC_TD3 = 0x0160 # macro +ixGC_CAC_ACC_TD4 = 0x0161 # macro +ixGC_CAC_ACC_TD5 = 0x0162 # macro +ixGC_CAC_ACC_TD6 = 0x0163 # macro +ixGC_CAC_ACC_TD7 = 0x0164 # macro +ixGC_CAC_ACC_TD8 = 0x0165 # macro +ixGC_CAC_ACC_TD9 = 0x0166 # macro +ixGC_CAC_ACC_TD10 = 0x0167 # macro +ixGC_CAC_ACC_RMI0 = 0x0168 # macro +ixGC_CAC_ACC_RMI1 = 0x0169 # macro +ixGC_CAC_ACC_RMI2 = 0x016a # macro +ixGC_CAC_ACC_RMI3 = 0x016b # macro +ixGC_CAC_ACC_UTCL2_ATCL20 = 0x0172 # macro +ixGC_CAC_ACC_UTCL2_ATCL21 = 0x0173 # macro +ixGC_CAC_ACC_UTCL2_ATCL22 = 0x0174 # macro +ixGC_CAC_ACC_UTCL2_ATCL23 = 0x0175 # macro +ixGC_CAC_ACC_UTCL2_ATCL24 = 0x0176 # macro +ixGC_CAC_ACC_CU0 = 0x018b # macro +ixGC_CAC_ACC_UTCL10 = 0x018c # macro +ixGC_CAC_ACC_SP0_LOWER = 0x01c2 # macro +ixGC_CAC_ACC_SP0_UPPER = 0x01c3 # macro +ixGC_CAC_ACC_SP1_LOWER = 0x01c4 # macro +ixGC_CAC_ACC_SP1_UPPER = 0x01c5 # macro +ixGC_CAC_ACC_SP2_LOWER = 0x01c6 # macro +ixGC_CAC_ACC_SP2_UPPER = 0x01c7 # macro +ixGC_CAC_ACC_GL1C0 = 0x01c8 # macro +ixGC_CAC_ACC_GL1C1 = 0x01c9 # macro +ixGC_CAC_ACC_GL1C2 = 0x01ca # macro +ixGC_CAC_ACC_GL1C3 = 0x01cb # macro +ixGC_CAC_ACC_GL1C4 = 0x01cc # macro +ixGC_CAC_ACC_SQC0 = 0x01cd # macro +ixGC_CAC_ACC_SQC1 = 0x01ce # macro +ixGC_CAC_ACC_SQC2 = 0x01cf # macro +ixGC_CAC_OVRD_BCI = 0x0200 # macro +ixGC_CAC_OVRD_CB = 0x0201 # macro +ixGC_CAC_OVRD_CP = 0x0203 # macro +ixGC_CAC_OVRD_DB = 0x0204 # macro +ixGC_CAC_OVRD_GDS = 0x0206 # macro +ixGC_CAC_OVRD_LDS = 0x0207 # macro +ixGC_CAC_OVRD_PA = 0x0208 # macro +ixGC_CAC_OVRD_PC = 0x0209 # macro +ixGC_CAC_OVRD_SC = 0x020a # macro +ixGC_CAC_OVRD_SPI = 0x020b # macro +ixGC_CAC_OVRD_CU = 0x020c # macro +ixGC_CAC_OVRD_SQ = 0x020d # macro +ixGC_CAC_OVRD_SX = 0x020e # macro +ixGC_CAC_OVRD_SXRB = 0x020f # macro +ixGC_CAC_OVRD_TA = 0x0210 # macro +ixGC_CAC_OVRD_TCP = 0x0211 # macro +ixGC_CAC_OVRD_TD = 0x0212 # macro +ixGC_CAC_OVRD_RMI = 0x0213 # macro +ixGC_CAC_OVRD_EA = 0x0214 # macro +ixGC_CAC_OVRD_UTCL2_ATCL2 = 0x0215 # macro +ixGC_CAC_OVRD_UTCL2_ROUTER = 0x0216 # macro +ixGC_CAC_OVRD_UTCL2_VML2 = 0x0217 # macro +ixGC_CAC_OVRD_UTCL2_WALKER = 0x0218 # macro +ixGC_CAC_OVRD_SP = 0x0219 # macro +ixGC_CAC_OVRD_UTCL1 = 0x021a # macro +ixGC_CAC_OVRD_CHC = 0x021b # macro +ixGC_CAC_OVRD_GE = 0x021c # macro +ixGC_CAC_OVRD_PMM = 0x021d # macro +ixGC_CAC_OVRD_GL2C = 0x021e # macro +ixGC_CAC_OVRD_GUS = 0x021f # macro +ixGC_CAC_OVRD_PH = 0x0220 # macro +ixGC_CAC_OVRD_SDMA = 0x0221 # macro +ixGC_CAC_OVRD_GL1C = 0x0222 # macro +ixGC_CAC_OVRD_SQC = 0x0223 # macro +ixGC_CAC_OVRD_RLC = 0x0224 # macro +ixGC_CAC_OVRD_GE_HI = 0x0225 # macro +ixSE_CAC_OVR_SEL = 0x0002 # macro +ixSE_CAC_OVR_VAL = 0x0003 # macro +ixGLB_CPG_SAMPLEDELAY = 0x0000 # macro +ixGLB_CPC_SAMPLEDELAY = 0x0001 # macro +ixGLB_CPF_SAMPLEDELAY = 0x0002 # macro +ixGLB_GDS_SAMPLEDELAY = 0x0003 # macro +ixGLB_GCR_SAMPLEDELAY = 0x0004 # macro +ixGLB_PH_SAMPLEDELAY = 0x0005 # macro +ixGLB_GE1_SAMPLEDELAY = 0x0006 # macro +ixGLB_GE2DIST_SAMPLEDELAY = 0x0007 # macro +ixGLB_GUS_SAMPLEDELAY = 0x0008 # macro +ixGLB_CHA_SAMPLEDELAY = 0x0009 # macro +ixGLB_CHCG_SAMPLEDELAY = 0x000a # macro +ixGLB_ATCL2_SAMPLEDELAY = 0x000b # macro +ixGLB_VML2_SAMPLEDELAY = 0x000c # macro +ixGLB_SDMA0_SAMPLEDELAY = 0x000d # macro +ixGLB_SDMA1_SAMPLEDELAY = 0x000e # macro +ixGLB_SDMA2_SAMPLEDELAY = 0x000f # macro +ixGLB_SDMA3_SAMPLEDELAY = 0x0010 # macro +ixGLB_GL2A0_SAMPLEDELAY = 0x0011 # macro +ixGLB_GL2A1_SAMPLEDELAY = 0x0012 # macro +ixGLB_GL2A2_SAMPLEDELAY = 0x0013 # macro +ixGLB_GL2A3_SAMPLEDELAY = 0x0014 # macro +ixGLB_GL2C0_SAMPLEDELAY = 0x0015 # macro +ixGLB_GL2C1_SAMPLEDELAY = 0x0016 # macro +ixGLB_GL2C2_SAMPLEDELAY = 0x0017 # macro +ixGLB_GL2C3_SAMPLEDELAY = 0x0018 # macro +ixGLB_GL2C4_SAMPLEDELAY = 0x0019 # macro +ixGLB_GL2C5_SAMPLEDELAY = 0x001a # macro +ixGLB_GL2C6_SAMPLEDELAY = 0x001b # macro +ixGLB_GL2C7_SAMPLEDELAY = 0x001c # macro +ixGLB_GL2C8_SAMPLEDELAY = 0x001d # macro +ixGLB_GL2C9_SAMPLEDELAY = 0x001e # macro +ixGLB_GL2C10_SAMPLEDELAY = 0x001f # macro +ixGLB_GL2C11_SAMPLEDELAY = 0x0020 # macro +ixGLB_GL2C12_SAMPLEDELAY = 0x0021 # macro +ixGLB_GL2C13_SAMPLEDELAY = 0x0022 # macro +ixGLB_GL2C14_SAMPLEDELAY = 0x0023 # macro +ixGLB_GL2C15_SAMPLEDELAY = 0x0024 # macro +ixGLB_EA0_SAMPLEDELAY = 0x0025 # macro +ixGLB_EA1_SAMPLEDELAY = 0x0026 # macro +ixGLB_EA2_SAMPLEDELAY = 0x0027 # macro +ixGLB_EA3_SAMPLEDELAY = 0x0028 # macro +ixGLB_EA4_SAMPLEDELAY = 0x0029 # macro +ixGLB_EA5_SAMPLEDELAY = 0x002a # macro +ixGLB_EA6_SAMPLEDELAY = 0x002b # macro +ixGLB_EA7_SAMPLEDELAY = 0x002c # macro +ixGLB_EA8_SAMPLEDELAY = 0x002d # macro +ixGLB_EA9_SAMPLEDELAY = 0x002e # macro +ixGLB_EA10_SAMPLEDELAY = 0x002f # macro +ixGLB_EA11_SAMPLEDELAY = 0x0030 # macro +ixGLB_EA12_SAMPLEDELAY = 0x0031 # macro +ixGLB_EA13_SAMPLEDELAY = 0x0032 # macro +ixGLB_EA14_SAMPLEDELAY = 0x0033 # macro +ixGLB_EA15_SAMPLEDELAY = 0x0034 # macro +ixGLB_CHC0_SAMPLEDELAY = 0x0035 # macro +ixGLB_CHC1_SAMPLEDELAY = 0x0036 # macro +ixGLB_CHC2_SAMPLEDELAY = 0x0037 # macro +ixGLB_CHC3_SAMPLEDELAY = 0x0038 # macro +ixGLB_GE2SE0_SAMPLEDELAY = 0x0039 # macro +ixGLB_GE2SE1_SAMPLEDELAY = 0x003a # macro +ixGLB_GE2SE2_SAMPLEDELAY = 0x003b # macro +ixGLB_GE2SE3_SAMPLEDELAY = 0x003c # macro +ixSE_SPI_SAMPLEDELAY = 0x0000 # macro +ixSE_SQG_SAMPLEDELAY = 0x0001 # macro +ixSE_CBR_SAMPLEDELAY = 0x0002 # macro +ixSE_DBR_SAMPLEDELAY = 0x0003 # macro +ixSE_PA_SAMPLEDELAY = 0x0004 # macro +ixSE_SA0SX_SAMPLEDELAY = 0x0005 # macro +ixSE_SA0GL1A_SAMPLEDELAY = 0x0006 # macro +ixSE_SA0GL1CG_SAMPLEDELAY = 0x0007 # macro +ixSE_SA0CB0_SAMPLEDELAY = 0x0008 # macro +ixSE_SA0CB1_SAMPLEDELAY = 0x0009 # macro +ixSE_SA0DB0_SAMPLEDELAY = 0x000a # macro +ixSE_SA0DB1_SAMPLEDELAY = 0x000b # macro +ixSE_SA0SC0_SAMPLEDELAY = 0x000c # macro +ixSE_SA0SC1_SAMPLEDELAY = 0x000d # macro +ixSE_SA0RMI0_SAMPLEDELAY = 0x000e # macro +ixSE_SA0RMI1_SAMPLEDELAY = 0x000f # macro +ixSE_SA0GL1C0_SAMPLEDELAY = 0x0010 # macro +ixSE_SA0GL1C1_SAMPLEDELAY = 0x0011 # macro +ixSE_SA0GL1C2_SAMPLEDELAY = 0x0012 # macro +ixSE_SA0GL1C3_SAMPLEDELAY = 0x0013 # macro +ixSE_SA0WGP00TA0_SAMPLEDELAY = 0x0014 # macro +ixSE_SA0WGP00TA1_SAMPLEDELAY = 0x0015 # macro +ixSE_SA0WGP00TD0_SAMPLEDELAY = 0x0016 # macro +ixSE_SA0WGP00TD1_SAMPLEDELAY = 0x0017 # macro +ixSE_SA0WGP00TCP0_SAMPLEDELAY = 0x0018 # macro +ixSE_SA0WGP00TCP1_SAMPLEDELAY = 0x0019 # macro +ixSE_SA0WGP01TA0_SAMPLEDELAY = 0x001a # macro +ixSE_SA0WGP01TA1_SAMPLEDELAY = 0x001b # macro +ixSE_SA0WGP01TD0_SAMPLEDELAY = 0x001c # macro +ixSE_SA0WGP01TD1_SAMPLEDELAY = 0x001d # macro +ixSE_SA0WGP01TCP0_SAMPLEDELAY = 0x001e # macro +ixSE_SA0WGP01TCP1_SAMPLEDELAY = 0x001f # macro +ixSE_SA0WGP02TA0_SAMPLEDELAY = 0x0020 # macro +ixSE_SA0WGP02TA1_SAMPLEDELAY = 0x0021 # macro +ixSE_SA0WGP02TD0_SAMPLEDELAY = 0x0022 # macro +ixSE_SA0WGP02TD1_SAMPLEDELAY = 0x0023 # macro +ixSE_SA0WGP02TCP0_SAMPLEDELAY = 0x0024 # macro +ixSE_SA0WGP02TCP1_SAMPLEDELAY = 0x0025 # macro +ixSE_SA0WGP03TA0_SAMPLEDELAY = 0x0026 # macro +ixSE_SA0WGP03TA1_SAMPLEDELAY = 0x0027 # macro +ixSE_SA0WGP03TD0_SAMPLEDELAY = 0x0028 # macro +ixSE_SA0WGP03TD1_SAMPLEDELAY = 0x0029 # macro +ixSE_SA0WGP03TCP0_SAMPLEDELAY = 0x002a # macro +ixSE_SA0WGP03TCP1_SAMPLEDELAY = 0x002b # macro +ixSE_SA0WGP04TA0_SAMPLEDELAY = 0x002c # macro +ixSE_SA0WGP04TA1_SAMPLEDELAY = 0x002d # macro +ixSE_SA0WGP04TD0_SAMPLEDELAY = 0x002e # macro +ixSE_SA0WGP04TD1_SAMPLEDELAY = 0x002f # macro +ixSE_SA0WGP04TCP0_SAMPLEDELAY = 0x0030 # macro +ixSE_SA0WGP04TCP1_SAMPLEDELAY = 0x0031 # macro +ixSE_SA1SX_SAMPLEDELAY = 0x0032 # macro +ixSE_SA1GL1A_SAMPLEDELAY = 0x0033 # macro +ixSE_SA1GL1CG_SAMPLEDELAY = 0x0034 # macro +ixSE_SA1CB0_SAMPLEDELAY = 0x0035 # macro +ixSE_SA1CB1_SAMPLEDELAY = 0x0036 # macro +ixSE_SA1DB0_SAMPLEDELAY = 0x0037 # macro +ixSE_SA1DB1_SAMPLEDELAY = 0x0038 # macro +ixSE_SA1SC0_SAMPLEDELAY = 0x0039 # macro +ixSE_SA1SC1_SAMPLEDELAY = 0x003a # macro +ixSE_SA1RMI0_SAMPLEDELAY = 0x003b # macro +ixSE_SA1RMI1_SAMPLEDELAY = 0x003c # macro +ixSE_SA1GL1C0_SAMPLEDELAY = 0x003d # macro +ixSE_SA1GL1C1_SAMPLEDELAY = 0x003e # macro +ixSE_SA1GL1C2_SAMPLEDELAY = 0x003f # macro +ixSE_SA1GL1C3_SAMPLEDELAY = 0x0040 # macro +ixSE_SA1WGP00TA0_SAMPLEDELAY = 0x0041 # macro +ixSE_SA1WGP00TA1_SAMPLEDELAY = 0x0042 # macro +ixSE_SA1WGP00TD0_SAMPLEDELAY = 0x0043 # macro +ixSE_SA1WGP00TD1_SAMPLEDELAY = 0x0044 # macro +ixSE_SA1WGP00TCP0_SAMPLEDELAY = 0x0045 # macro +ixSE_SA1WGP00TCP1_SAMPLEDELAY = 0x0046 # macro +ixSE_SA1WGP01TA0_SAMPLEDELAY = 0x0047 # macro +ixSE_SA1WGP01TA1_SAMPLEDELAY = 0x0048 # macro +ixSE_SA1WGP01TD0_SAMPLEDELAY = 0x0049 # macro +ixSE_SA1WGP01TD1_SAMPLEDELAY = 0x004a # macro +ixSE_SA1WGP01TCP0_SAMPLEDELAY = 0x004b # macro +ixSE_SA1WGP01TCP1_SAMPLEDELAY = 0x004c # macro +ixSE_SA1WGP02TA0_SAMPLEDELAY = 0x004d # macro +ixSE_SA1WGP02TA1_SAMPLEDELAY = 0x004e # macro +ixSE_SA1WGP02TD0_SAMPLEDELAY = 0x004f # macro +ixSE_SA1WGP02TD1_SAMPLEDELAY = 0x0050 # macro +ixSE_SA1WGP02TCP0_SAMPLEDELAY = 0x0051 # macro +ixSE_SA1WGP02TCP1_SAMPLEDELAY = 0x0052 # macro +ixSE_SA1WGP03TA0_SAMPLEDELAY = 0x0053 # macro +ixSE_SA1WGP03TA1_SAMPLEDELAY = 0x0054 # macro +ixSE_SA1WGP03TD0_SAMPLEDELAY = 0x0055 # macro +ixSE_SA1WGP03TD1_SAMPLEDELAY = 0x0056 # macro +ixSE_SA1WGP03TCP0_SAMPLEDELAY = 0x0057 # macro +ixSE_SA1WGP03TCP1_SAMPLEDELAY = 0x0058 # macro +ixSE_SA1WGP04TA0_SAMPLEDELAY = 0x0059 # macro +ixSE_SA1WGP04TA1_SAMPLEDELAY = 0x005a # macro +ixSE_SA1WGP04TD0_SAMPLEDELAY = 0x005b # macro +ixSE_SA1WGP04TD1_SAMPLEDELAY = 0x005c # macro +ixSE_SA1WGP04TCP0_SAMPLEDELAY = 0x005d # macro +ixSE_SA1WGP04TCP1_SAMPLEDELAY = 0x005e # macro +ixSA_WGP_BLK_ID = 0x0000 # macro +ixSQ_WAVE_HW_ID_LEGACY = 0x0104 # macro +ixSQ_WAVE_INST_DW0 = 0x010a # macro +ixSQ_WAVE_VGPR_OFFSET = 0x011b # macro +ixSQ_WAVE_TTMP2 = 0x026e # macro +ixSQ_INTERRUPT_WORD_AUTO = 0x20c0 # macro +ixSQ_INTERRUPT_WORD_ERROR = 0x20c0 # macro +ixSQ_INTERRUPT_WORD_WAVE = 0x20c0 # macro +ixDIDT_SQ_CTRL0 = 0x0000 # macro +ixDIDT_SQ_CTRL1 = 0x0001 # macro +ixDIDT_SQ_CTRL2 = 0x0002 # macro +ixDIDT_SQ_CTRL_OCP = 0x0003 # macro +ixDIDT_SQ_STALL_CTRL = 0x0004 # macro +ixDIDT_SQ_TUNING_CTRL = 0x0005 # macro +ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL = 0x0006 # macro +ixDIDT_SQ_CTRL3 = 0x0007 # macro +ixDIDT_SQ_STALL_PATTERN_1_2 = 0x0008 # macro +ixDIDT_SQ_STALL_PATTERN_3_4 = 0x0009 # macro +ixDIDT_SQ_STALL_PATTERN_5_6 = 0x000a # macro +ixDIDT_SQ_STALL_PATTERN_7 = 0x000b # macro +ixDIDT_SQ_MPD_SCALE_FACTOR = 0x000c # macro +ixDIDT_SQ_STALL_RELEASE_CNTL0 = 0x000d # macro +ixDIDT_SQ_STALL_RELEASE_CNTL1 = 0x000e # macro +ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS = 0x000f # macro +ixDIDT_SQ_WEIGHT0_3 = 0x0010 # macro +ixDIDT_SQ_WEIGHT4_7 = 0x0011 # macro +ixDIDT_SQ_WEIGHT8_11 = 0x0012 # macro +ixDIDT_SQ_EDC_CTRL = 0x0013 # macro +ixDIDT_SQ_EDC_THRESHOLD = 0x0014 # macro +ixDIDT_SQ_EDC_STALL_PATTERN_1_2 = 0x0015 # macro +ixDIDT_SQ_EDC_STALL_PATTERN_3_4 = 0x0016 # macro +ixDIDT_SQ_EDC_STALL_PATTERN_5_6 = 0x0017 # macro +ixDIDT_SQ_EDC_STALL_PATTERN_7 = 0x0018 # macro +ixDIDT_SQ_EDC_TIMER_PERIOD = 0x0019 # macro +ixDIDT_SQ_THROTTLE_CTRL = 0x001a # macro +ixDIDT_SQ_EDC_STALL_DELAY_1 = 0x001b # macro +ixDIDT_SQ_EDC_STALL_DELAY_2 = 0x001c # macro +ixDIDT_SQ_EDC_STALL_DELAY_3 = 0x001d # macro +ixDIDT_SQ_EDC_STATUS = 0x001f # macro +ixDIDT_SQ_EDC_OVERFLOW = 0x0020 # macro +ixDIDT_SQ_EDC_ROLLING_POWER_DELTA = 0x0021 # macro +ixDIDT_SQ_EDC_PCC_PERF_COUNTER = 0x0022 # macro +ixDIDT_DB_CTRL0 = 0x0030 # macro +ixDIDT_DB_CTRL1 = 0x0031 # macro +ixDIDT_DB_CTRL2 = 0x0032 # macro +ixDIDT_DB_CTRL_OCP = 0x0033 # macro +ixDIDT_DB_STALL_CTRL = 0x0034 # macro +ixDIDT_DB_TUNING_CTRL = 0x0035 # macro +ixDIDT_DB_STALL_AUTO_RELEASE_CTRL = 0x0036 # macro +ixDIDT_DB_CTRL3 = 0x0037 # macro +ixDIDT_DB_STALL_PATTERN_1_2 = 0x0038 # macro +ixDIDT_DB_STALL_PATTERN_3_4 = 0x0039 # macro +ixDIDT_DB_STALL_PATTERN_5_6 = 0x003a # macro +ixDIDT_DB_STALL_PATTERN_7 = 0x003b # macro +ixDIDT_DB_MPD_SCALE_FACTOR = 0x003c # macro +ixDIDT_DB_STALL_RELEASE_CNTL0 = 0x003d # macro +ixDIDT_DB_STALL_RELEASE_CNTL1 = 0x003e # macro +ixDIDT_DB_STALL_RELEASE_CNTL_STATUS = 0x003f # macro +ixDIDT_DB_WEIGHT0_3 = 0x0040 # macro +ixDIDT_DB_WEIGHT4_7 = 0x0041 # macro +ixDIDT_DB_WEIGHT8_11 = 0x0042 # macro +ixDIDT_DB_EDC_CTRL = 0x0043 # macro +ixDIDT_DB_EDC_THRESHOLD = 0x0044 # macro +ixDIDT_DB_EDC_STALL_PATTERN_1_2 = 0x0045 # macro +ixDIDT_DB_EDC_STALL_PATTERN_3_4 = 0x0046 # macro +ixDIDT_DB_EDC_STALL_PATTERN_5_6 = 0x0047 # macro +ixDIDT_DB_EDC_STALL_PATTERN_7 = 0x0048 # macro +ixDIDT_DB_EDC_TIMER_PERIOD = 0x0049 # macro +ixDIDT_DB_THROTTLE_CTRL = 0x004a # macro +ixDIDT_DB_EDC_STALL_DELAY_1 = 0x004b # macro +ixDIDT_DB_EDC_STATUS = 0x004f # macro +ixDIDT_DB_EDC_OVERFLOW = 0x0050 # macro +ixDIDT_DB_EDC_ROLLING_POWER_DELTA = 0x0051 # macro +ixDIDT_DB_EDC_PCC_PERF_COUNTER = 0x0052 # macro +ixDIDT_TD_CTRL0 = 0x0060 # macro +ixDIDT_TD_CTRL1 = 0x0061 # macro +ixDIDT_TD_CTRL2 = 0x0062 # macro +ixDIDT_TD_CTRL_OCP = 0x0063 # macro +ixDIDT_TD_STALL_CTRL = 0x0064 # macro +ixDIDT_TD_TUNING_CTRL = 0x0065 # macro +ixDIDT_TD_STALL_AUTO_RELEASE_CTRL = 0x0066 # macro +ixDIDT_TD_CTRL3 = 0x0067 # macro +ixDIDT_TD_STALL_PATTERN_1_2 = 0x0068 # macro +ixDIDT_TD_STALL_PATTERN_3_4 = 0x0069 # macro +ixDIDT_TD_STALL_PATTERN_5_6 = 0x006a # macro +ixDIDT_TD_STALL_PATTERN_7 = 0x006b # macro +ixDIDT_TD_MPD_SCALE_FACTOR = 0x006c # macro +ixDIDT_TD_STALL_RELEASE_CNTL0 = 0x006d # macro +ixDIDT_TD_STALL_RELEASE_CNTL1 = 0x006e # macro +ixDIDT_TD_STALL_RELEASE_CNTL_STATUS = 0x006f # macro +ixDIDT_TD_WEIGHT0_3 = 0x0070 # macro +ixDIDT_TD_WEIGHT4_7 = 0x0071 # macro +ixDIDT_TD_WEIGHT8_11 = 0x0072 # macro +ixDIDT_TD_EDC_CTRL = 0x0073 # macro +ixDIDT_TD_EDC_THRESHOLD = 0x0074 # macro +ixDIDT_TD_EDC_STALL_PATTERN_1_2 = 0x0075 # macro +ixDIDT_TD_EDC_STALL_PATTERN_3_4 = 0x0076 # macro +ixDIDT_TD_EDC_STALL_PATTERN_5_6 = 0x0077 # macro +ixDIDT_TD_EDC_STALL_PATTERN_7 = 0x0078 # macro +ixDIDT_TD_EDC_TIMER_PERIOD = 0x0079 # macro +ixDIDT_TD_THROTTLE_CTRL = 0x007a # macro +ixDIDT_TD_EDC_STALL_DELAY_1 = 0x007b # macro +ixDIDT_TD_EDC_STALL_DELAY_2 = 0x007c # macro +ixDIDT_TD_EDC_STALL_DELAY_3 = 0x007d # macro +ixDIDT_TD_EDC_STATUS = 0x007f # macro +ixDIDT_TD_EDC_OVERFLOW = 0x0080 # macro +ixDIDT_TD_EDC_ROLLING_POWER_DELTA = 0x0081 # macro +ixDIDT_TD_EDC_PCC_PERF_COUNTER = 0x0082 # macro +ixDIDT_TCP_CTRL0 = 0x0090 # macro +ixDIDT_TCP_CTRL1 = 0x0091 # macro +ixDIDT_TCP_CTRL2 = 0x0092 # macro +ixDIDT_TCP_CTRL_OCP = 0x0093 # macro +ixDIDT_TCP_STALL_CTRL = 0x0094 # macro +ixDIDT_TCP_TUNING_CTRL = 0x0095 # macro +ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL = 0x0096 # macro +ixDIDT_TCP_CTRL3 = 0x0097 # macro +ixDIDT_TCP_STALL_PATTERN_1_2 = 0x0098 # macro +ixDIDT_TCP_STALL_PATTERN_3_4 = 0x0099 # macro +ixDIDT_TCP_STALL_PATTERN_5_6 = 0x009a # macro +ixDIDT_TCP_STALL_PATTERN_7 = 0x009b # macro +ixDIDT_TCP_MPD_SCALE_FACTOR = 0x009c # macro +ixDIDT_TCP_STALL_RELEASE_CNTL0 = 0x009d # macro +ixDIDT_TCP_STALL_RELEASE_CNTL1 = 0x009e # macro +ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS = 0x009f # macro +ixDIDT_TCP_WEIGHT0_3 = 0x00a0 # macro +ixDIDT_TCP_WEIGHT4_7 = 0x00a1 # macro +ixDIDT_TCP_WEIGHT8_11 = 0x00a2 # macro +ixDIDT_TCP_EDC_CTRL = 0x00a3 # macro +ixDIDT_TCP_EDC_THRESHOLD = 0x00a4 # macro +ixDIDT_TCP_EDC_STALL_PATTERN_1_2 = 0x00a5 # macro +ixDIDT_TCP_EDC_STALL_PATTERN_3_4 = 0x00a6 # macro +ixDIDT_TCP_EDC_STALL_PATTERN_5_6 = 0x00a7 # macro +ixDIDT_TCP_EDC_STALL_PATTERN_7 = 0x00a8 # macro +ixDIDT_TCP_EDC_TIMER_PERIOD = 0x00a9 # macro +ixDIDT_TCP_THROTTLE_CTRL = 0x00aa # macro +ixDIDT_TCP_EDC_STALL_DELAY_1 = 0x00ab # macro +ixDIDT_TCP_EDC_STALL_DELAY_2 = 0x00ac # macro +ixDIDT_TCP_EDC_STALL_DELAY_3 = 0x00ad # macro +ixDIDT_TCP_EDC_STATUS = 0x00af # macro +ixDIDT_TCP_EDC_OVERFLOW = 0x00b0 # macro +ixDIDT_TCP_EDC_ROLLING_POWER_DELTA = 0x00b1 # macro +ixDIDT_TCP_EDC_PCC_PERF_COUNTER = 0x00b2 # macro +ixDIDT_SQ_STALL_EVENT_COUNTER = 0x00c0 # macro +ixDIDT_DB_STALL_EVENT_COUNTER = 0x00c1 # macro +ixDIDT_TD_STALL_EVENT_COUNTER = 0x00c2 # macro +ixDIDT_TCP_STALL_EVENT_COUNTER = 0x00c3 # macro _sienna_cichlid_ip_offset_HEADER = True # macro MAX_INSTANCE = 7 # macro MAX_SEGMENT = 5 # macro @@ -13823,7 +61790,97 @@ UMC_BASE = struct_IP_BASE # Variable struct_IP_BASE USB0_BASE = struct_IP_BASE # Variable struct_IP_BASE VCN_BASE = struct_IP_BASE # Variable struct_IP_BASE __all__ = \ - ['ATHUB_BASE', 'ATHUB_BASE__INST0_SEG0', 'ATHUB_BASE__INST0_SEG1', + ['ACCEPT_UNSOLICITED_RESPONSE_ENABLE', + 'ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE', 'ACP_TYPE_DVD_AUDIO', + 'ACP_TYPE_GENERIC_AUDIO', 'ACP_TYPE_ICE60958_AUDIO', + 'ACP_TYPE_SUPER_AUDIO_CD', 'ACrYCb16161616_10LSB', + 'ACrYCb16161616_10MSB', 'ACrYCb16161616_12LSB', + 'ACrYCb16161616_12MSB', 'ACrYCb2101010', 'ACrYCb8888', + 'ADDR_GEN_ONE', 'ADDR_GEN_TWO', 'ADDR_GEN_ZERO', 'ADDR_RESERVED', + 'AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS', + 'AFMT_ACP_SOURCE_FROM_AZALIA', 'AFMT_ACP_TYPE', + 'AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT', + 'AFMT_AUDIO_CRC_AUTO_RESTART', 'AFMT_AUDIO_CRC_CH0_SIG', + 'AFMT_AUDIO_CRC_CH1_SIG', 'AFMT_AUDIO_CRC_CH2_SIG', + 'AFMT_AUDIO_CRC_CH3_SIG', 'AFMT_AUDIO_CRC_CH4_SIG', + 'AFMT_AUDIO_CRC_CH5_SIG', 'AFMT_AUDIO_CRC_CH6_SIG', + 'AFMT_AUDIO_CRC_CH7_SIG', 'AFMT_AUDIO_CRC_CONTROL_CH_SEL', + 'AFMT_AUDIO_CRC_CONTROL_CONT', 'AFMT_AUDIO_CRC_CONTROL_SOURCE', + 'AFMT_AUDIO_CRC_ONESHOT', 'AFMT_AUDIO_CRC_RESERVED_10', + 'AFMT_AUDIO_CRC_RESERVED_11', 'AFMT_AUDIO_CRC_RESERVED_12', + 'AFMT_AUDIO_CRC_RESERVED_13', 'AFMT_AUDIO_CRC_RESERVED_14', + 'AFMT_AUDIO_CRC_RESERVED_8', 'AFMT_AUDIO_CRC_RESERVED_9', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT', + 'AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT', + 'AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS', + 'AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER', + 'AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD', + 'AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND', + 'AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS', + 'AFMT_AUDIO_PACKET_SENT_DISABLED', + 'AFMT_AUDIO_PACKET_SENT_ENABLED', 'AFMT_AUDIO_SRC_CONTROL_SELECT', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM0', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM1', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM2', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM3', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM4', + 'AFMT_AUDIO_SRC_FROM_AZ_STREAM5', + 'AFMT_HDMI_AUDIO_SEND_MAX_PACKETS', + 'AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE', + 'AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS', + 'AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK', + 'AFMT_INTERRUPT_DISABLE', 'AFMT_INTERRUPT_ENABLE', + 'AFMT_INTERRUPT_STATUS_CHG_MASK', 'AFMT_MEM_DISABLE_MEM_PWR_CTRL', + 'AFMT_MEM_ENABLE_MEM_PWR_CTRL', + 'AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST', + 'AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 'AFMT_MEM_FORCE_SHUT_DOWN_REQUEST', 'AFMT_MEM_NO_FORCE_REQUEST', + 'AFMT_MEM_PWR_DIS_CTRL', 'AFMT_MEM_PWR_FORCE_CTRL', + 'AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED', + 'AFMT_RAMP_CONTROL0_SIGN', 'AFMT_RAMP_SIGNED', + 'AFMT_RAMP_UNSIGNED', 'AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED', + 'AFMT_VBI_PACKET_CONTROL_ACP_SOURCE', 'ALLOW_SR_ON_TRANS_REQ', + 'ALLOW_SR_ON_TRANS_REQ_DISABLE', 'ALLOW_SR_ON_TRANS_REQ_ENABLE', + 'ALL_USE_R', 'ALPHA_DATA_ONTO_ALPHA_PORT', + 'ALPHA_DATA_ONTO_CB_B_PORT', 'ALPHA_DATA_ONTO_CR_R_PORT', + 'ALPHA_DATA_ONTO_Y_G_PORT', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK', 'AMCLOCK_ENABLE', + 'APG_ACP_OVERRIDE', 'APG_ACP_SOURCE_NO_OVERRIDE', + 'APG_ACP_TYPE_DVD_AUDIO', 'APG_ACP_TYPE_GENERIC_AUDIO', + 'APG_ACP_TYPE_ICE60958_AUDIO', 'APG_ACP_TYPE_SUPER_AUDIO_CD', + 'APG_AUDIO_CRC_CH0_SIG', 'APG_AUDIO_CRC_CH1_SIG', + 'APG_AUDIO_CRC_CH2_SIG', 'APG_AUDIO_CRC_CH3_SIG', + 'APG_AUDIO_CRC_CH4_SIG', 'APG_AUDIO_CRC_CH5_SIG', + 'APG_AUDIO_CRC_CH6_SIG', 'APG_AUDIO_CRC_CH7_SIG', + 'APG_AUDIO_CRC_CONTINUOUS', 'APG_AUDIO_CRC_CONTROL_CH_SEL', + 'APG_AUDIO_CRC_CONTROL_CONT', 'APG_AUDIO_CRC_ONESHOT', + 'APG_AUDIO_CRC_RESERVED_10', 'APG_AUDIO_CRC_RESERVED_11', + 'APG_AUDIO_CRC_RESERVED_12', 'APG_AUDIO_CRC_RESERVED_13', + 'APG_AUDIO_CRC_RESERVED_14', 'APG_AUDIO_CRC_RESERVED_15', + 'APG_AUDIO_CRC_RESERVED_8', 'APG_AUDIO_CRC_RESERVED_9', + 'APG_DBG_ACP_TYPE', 'APG_DBG_AUDIO_DTO_BASE', + 'APG_DBG_AUDIO_DTO_DIV', 'APG_DBG_AUDIO_DTO_MULTI', + 'APG_DBG_MUX_SEL', 'APG_DEBUG_AUDIO_MODE', + 'APG_DP_ASP_CHANNEL_COUNT_FROM_AZ', + 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE', + 'APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', + 'APG_FUNCTIONAL_MODE', 'APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS', + 'APG_INFOFRAME_SOURCE_NO_OVERRIDE', + 'APG_MEM_DISABLE_MEM_PWR_CTRL', 'APG_MEM_ENABLE_MEM_PWR_CTRL', + 'APG_MEM_FORCE_DEEP_SLEEP_REQUEST', + 'APG_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 'APG_MEM_FORCE_SHUT_DOWN_REQUEST', 'APG_MEM_NO_FORCE_REQUEST', + 'APG_MEM_POWER_STATE', 'APG_MEM_POWER_STATE_DS', + 'APG_MEM_POWER_STATE_LS', 'APG_MEM_POWER_STATE_ON', + 'APG_MEM_POWER_STATE_SD', 'APG_MEM_PWR_DIS_CTRL', + 'APG_MEM_PWR_FORCE_CTRL', 'APG_PACKET_CONTROL_ACP_SOURCE', + 'APG_PACKET_CONTROL_AUDIO_INFO_SOURCE', 'APG_RAMP_CONTROL_SIGN', + 'APG_RAMP_SIGNED', 'APG_RAMP_UNSIGNED', 'ARGB1555', + 'ARGB16161616_10LSB', 'ARGB16161616_10MSB', 'ARGB16161616_12LSB', + 'ARGB16161616_12MSB', 'ARGB16161616_FLOAT', 'ARGB16161616_SNORM', + 'ARGB16161616_UNORM', 'ARGB2101010', 'ARGB4444', 'ARGB8888', + 'ATHUB_BASE', 'ATHUB_BASE__INST0_SEG0', 'ATHUB_BASE__INST0_SEG1', 'ATHUB_BASE__INST0_SEG2', 'ATHUB_BASE__INST0_SEG3', 'ATHUB_BASE__INST0_SEG4', 'ATHUB_BASE__INST1_SEG0', 'ATHUB_BASE__INST1_SEG1', 'ATHUB_BASE__INST1_SEG2', @@ -13840,8 +61897,885 @@ __all__ = \ 'ATHUB_BASE__INST5_SEG3', 'ATHUB_BASE__INST5_SEG4', 'ATHUB_BASE__INST6_SEG0', 'ATHUB_BASE__INST6_SEG1', 'ATHUB_BASE__INST6_SEG2', 'ATHUB_BASE__INST6_SEG3', - 'ATHUB_BASE__INST6_SEG4', 'CE_PARTITION_BASE', 'CLK_BASE', - 'CLK_BASE__INST0_SEG0', 'CLK_BASE__INST0_SEG1', + 'ATHUB_BASE__INST6_SEG4', 'AUDIO_LAYOUT_0', 'AUDIO_LAYOUT_1', + 'AUDIO_LAYOUT_SELECT', 'AUTOCAL_MODE_AUTOCENTER', + 'AUTOCAL_MODE_AUTOREPLICATE', 'AUTOCAL_MODE_AUTOSCALE', + 'AUTOCAL_MODE_OFF', 'AYCrCb16161616_10LSB', + 'AYCrCb16161616_10MSB', 'AYCrCb16161616_12LSB', + 'AYCrCb16161616_12MSB', 'AYCrCb8888', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE', + 'AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED', + 'AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE', + 'AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET', + 'AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED', + 'AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8', + 'AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT', + 'AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN', + 'AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET', + 'AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC', + 'AZ_CORB_SIZE', 'AZ_CORB_SIZE_16ENTRIES_RESERVED', + 'AZ_CORB_SIZE_256ENTRIES', 'AZ_CORB_SIZE_2ENTRIES_RESERVED', + 'AZ_CORB_SIZE_RESERVED', 'AZ_GLOBAL_CAPABILITIES', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED', + 'AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED', + 'AZ_LATENCY_COUNTER_CONTROL', 'AZ_LATENCY_COUNTER_NO_RESET', + 'AZ_LATENCY_COUNTER_RESET_DONE', 'AZ_RIRB_SIZE', + 'AZ_RIRB_SIZE_16ENTRIES_RESERVED', 'AZ_RIRB_SIZE_256ENTRIES', + 'AZ_RIRB_SIZE_2ENTRIES_RESERVED', 'AZ_RIRB_SIZE_UNDEFINED', + 'AZ_RIRB_WRITE_POINTER_DO_RESET', + 'AZ_RIRB_WRITE_POINTER_NOT_RESET', 'AZ_RIRB_WRITE_POINTER_RESET', + 'AZ_STATE_CHANGE_STATUS', + 'AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT', + 'AZ_STATE_CHANGE_STATUS_CODEC_PRESENT', 'BASE_RATE_44P1KHZ', + 'BASE_RATE_48KHZ', 'BGR101111_FIX', 'BGR101111_FLOAT', 'BGR565', + 'BIGK_FRAGMENT_SIZE', 'BINNER_BREAK_BATCH', 'BINNER_DROP', + 'BINNER_PIPELINE', 'BINNER_PIPELINE_BREAK', 'BINNING_ALLOWED', + 'BIN_CONF_OVERRIDE_CHECK', 'BIN_MAP_MODE_NONE', + 'BIN_MAP_MODE_POPS', 'BIN_MAP_MODE_RTA_INDEX', + 'BIN_SIZE_128_PIXELS', 'BIN_SIZE_256_PIXELS', + 'BIN_SIZE_32_PIXELS', 'BIN_SIZE_512_PIXELS', 'BIN_SIZE_64_PIXELS', + 'BITS_31_0', 'BITS_32_1', 'BITS_33_2', 'BITS_34_3', 'BITS_35_4', + 'BITS_36_5', 'BITS_37_6', 'BITS_38_7', 'BLEND_CONSTANT_ALPHA', + 'BLEND_CONSTANT_COLOR', 'BLEND_DST_ALPHA', 'BLEND_DST_COLOR', + 'BLEND_INV_SRC1_ALPHA', 'BLEND_INV_SRC1_COLOR', 'BLEND_ONE', + 'BLEND_ONE_MINUS_CONSTANT_ALPHA', + 'BLEND_ONE_MINUS_CONSTANT_COLOR', 'BLEND_ONE_MINUS_DST_ALPHA', + 'BLEND_ONE_MINUS_DST_COLOR', 'BLEND_ONE_MINUS_SRC_ALPHA', + 'BLEND_ONE_MINUS_SRC_COLOR', 'BLEND_OPT_PRESERVE_A0_IGNORE_A1', + 'BLEND_OPT_PRESERVE_A1_IGNORE_A0', + 'BLEND_OPT_PRESERVE_ALL_IGNORE_NONE', + 'BLEND_OPT_PRESERVE_C0_IGNORE_C1', + 'BLEND_OPT_PRESERVE_C1_IGNORE_C0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_A0', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_ALL', + 'BLEND_OPT_PRESERVE_NONE_IGNORE_NONE', 'BLEND_SRC1_ALPHA', + 'BLEND_SRC1_COLOR', 'BLEND_SRC_ALPHA', 'BLEND_SRC_ALPHA_SATURATE', + 'BLEND_SRC_COLOR', 'BLEND_ZERO', 'BLOCK_CONTEXT_DONE', 'BLUE_LUT', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM_DS', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM_LS', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM_ON', + 'BORROWBUFFER_MEM_POWER_STATE_ENUM_SD', 'BOTTOM_OF_PIPE_TS', + 'BREAK_BATCH', 'BYPASS', 'BYPASS_EN', 'BYPASS_GAMUT', + 'BYPASS_POST_CSC', 'BinEventCntl', 'BinMapMode', 'BinSizeExtend', + 'BinningMode', 'BlendOp', 'BlendOpt', 'CACHE_BYPASS', + 'CACHE_FLUSH', 'CACHE_FLUSH_AND_INV_EVENT', + 'CACHE_FLUSH_AND_INV_TS_EVENT', 'CACHE_FLUSH_AND_INV_TS_EVENT', + 'CACHE_FLUSH_TS', 'CACHE_LRU_RD', 'CACHE_LRU_WR', 'CACHE_NOA', + 'CACHE_NOA_WR', 'CACHE_STREAM', 'CACHE_STREAM_RD', 'CBMode', + 'CBPerfClearFilterSel', 'CBPerfOpFilterSel', 'CBPerfSel', + 'CBRamList', 'CB_B_DATA_ONTO_ALPHA_PORT', + 'CB_B_DATA_ONTO_CB_B_PORT', 'CB_B_DATA_ONTO_CR_R_PORT', + 'CB_B_DATA_ONTO_Y_G_PORT', 'CB_DCC_DECOMPRESS', + 'CB_DCG_BACKEND_RDLAT_FIFO', 'CB_DCG_CCC_CAS_COLOR_PTR', + 'CB_DCG_CCC_CAS_FRAG_PTR', 'CB_DCG_CCC_CAS_KEYID', + 'CB_DCG_CCC_CAS_SURF_PARAM', 'CB_DCG_CCC_CAS_TAG_ARRAY', + 'CB_DCG_COLOR_STORE', 'CB_DCG_COLOR_STORE_DIRTY_BYTE', + 'CB_DCG_DCC_CACHE', 'CB_DCG_DCC_DIRTY_BITS', + 'CB_DCG_FMASK_CACHE_STORE', 'CB_DCG_FRONTEND_RDLAT_FIFO', + 'CB_DCG_OUTPUT_FIFO', 'CB_DCG_QBLOCK_ALLOC', + 'CB_DCG_QUAD_PTR_FIFO', 'CB_DCG_READ_SKID_FIFO', + 'CB_DCG_SRC_FIFO', 'CB_DISABLE', 'CB_ELIMINATE_FAST_CLEAR', + 'CB_NORMAL', 'CB_PERF_CLEAR_FILTER_SEL_CLEAR', + 'CB_PERF_CLEAR_FILTER_SEL_NONCLEAR', + 'CB_PERF_OP_FILTER_SEL_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR', + 'CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS', + 'CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION', + 'CB_PERF_OP_FILTER_SEL_RESOLVE', + 'CB_PERF_OP_FILTER_SEL_WRITE_ONLY', + 'CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_READ_CLOCK_EN', + 'CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN', + 'CB_PERF_SEL_BLEND_CLOCK_EN', + 'CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST', + 'CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED', + 'CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED', + 'CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED', + 'CB_PERF_SEL_BLEND_STALL_AT_OUTPUT', + 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY', + 'CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB', + 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY', + 'CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB', + 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY', + 'CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB', + 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY', + 'CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB', + 'CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_CC_CACHE_FLUSH', + 'CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC', + 'CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_CC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_SECTOR_HIT', + 'CB_PERF_SEL_CC_CACHE_SECTOR_MISS', 'CB_PERF_SEL_CC_CACHE_STALL', + 'CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_CC_CACHE_TAG_MISS', + 'CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION', + 'CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN', + 'CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT', + 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN', + 'CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT', + 'CB_PERF_SEL_CC_MC_READ_REQUEST', + 'CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_MC_WRITE_REQUEST', + 'CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT', + 'CB_PERF_SEL_CC_SURFACE_SYNC', 'CB_PERF_SEL_CC_TAG_HIT', + 'CB_PERF_SEL_COLOR_STORE_CLOCK_EN', + 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY', + 'CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB', + 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READY', + 'CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB', + 'CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL', + 'CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED', + 'CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL', + 'CB_PERF_SEL_DCC_CACHE_FLUSH', + 'CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL', + 'CB_PERF_SEL_DCC_CACHE_PERF_HIT', + 'CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL', + 'CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL', + 'CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL', + 'CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED', + 'CB_PERF_SEL_DCC_CACHE_SECTOR_MISS', + 'CB_PERF_SEL_DCC_CACHE_STALL', + 'CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED', + 'CB_PERF_SEL_DCC_CACHE_TAG_MISS', + 'CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL', + 'CB_PERF_SEL_DRAWN_PIXEL', 'CB_PERF_SEL_DRAWN_QUAD', + 'CB_PERF_SEL_DRAWN_QUAD_FRAGMENT', 'CB_PERF_SEL_DRAWN_TILE', + 'CB_PERF_SEL_EVENT', 'CB_PERF_SEL_EVENT_CACHE_FLUSH', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT', + 'CB_PERF_SEL_EVENT_CACHE_FLUSH_TS', + 'CB_PERF_SEL_EVENT_CONTEXT_DONE', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS', + 'CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META', + 'CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT', + 'CB_PERF_SEL_FILTER_DRAWN_PIXEL', 'CB_PERF_SEL_FILTER_DRAWN_QUAD', + 'CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT', + 'CB_PERF_SEL_FILTER_DRAWN_TILE', + 'CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN', + 'CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN', + 'CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN', + 'CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN', + 'CB_PERF_SEL_GRBM_CLOCK_EN', 'CB_PERF_SEL_MEMARB_CLOCK_EN', + 'CB_PERF_SEL_NACK_CC_READ', 'CB_PERF_SEL_NACK_CC_WRITE', + 'CB_PERF_SEL_NONE', 'CB_PERF_SEL_PERFMON_CLOCK_EN', + 'CB_PERF_SEL_RESERVED_118', 'CB_PERF_SEL_RESERVED_119', + 'CB_PERF_SEL_RESERVED_120', 'CB_PERF_SEL_RESERVED_121', + 'CB_PERF_SEL_RESERVED_122', 'CB_PERF_SEL_RESERVED_123', + 'CB_PERF_SEL_RESERVED_124', 'CB_PERF_SEL_RESERVED_125', + 'CB_PERF_SEL_RESERVED_126', 'CB_PERF_SEL_RESERVED_127', + 'CB_PERF_SEL_RESERVED_128', 'CB_PERF_SEL_RESERVED_129', + 'CB_PERF_SEL_RESERVED_130', 'CB_PERF_SEL_RESERVED_131', + 'CB_PERF_SEL_RESERVED_132', 'CB_PERF_SEL_RESERVED_133', + 'CB_PERF_SEL_RESERVED_134', 'CB_PERF_SEL_RESERVED_135', + 'CB_PERF_SEL_RESERVED_136', 'CB_PERF_SEL_RESERVED_137', + 'CB_PERF_SEL_RESERVED_138', 'CB_PERF_SEL_RESERVED_139', + 'CB_PERF_SEL_RESERVED_140', 'CB_PERF_SEL_RESERVED_141', + 'CB_PERF_SEL_RESERVED_142', 'CB_PERF_SEL_RESERVED_143', + 'CB_PERF_SEL_RESERVED_144', 'CB_PERF_SEL_RESERVED_145', + 'CB_PERF_SEL_RESERVED_146', 'CB_PERF_SEL_RESERVED_147', + 'CB_PERF_SEL_RESERVED_148', 'CB_PERF_SEL_RESERVED_149', + 'CB_PERF_SEL_RESERVED_165', 'CB_PERF_SEL_RESERVED_166', + 'CB_PERF_SEL_RESERVED_167', 'CB_PERF_SEL_RESERVED_168', + 'CB_PERF_SEL_RESERVED_169', 'CB_PERF_SEL_RESERVED_170', + 'CB_PERF_SEL_RESERVED_171', 'CB_PERF_SEL_RESERVED_172', + 'CB_PERF_SEL_RESERVED_173', 'CB_PERF_SEL_RESERVED_174', + 'CB_PERF_SEL_RESERVED_175', 'CB_PERF_SEL_RESERVED_176', + 'CB_PERF_SEL_RESERVED_177', 'CB_PERF_SEL_RESERVED_178', + 'CB_PERF_SEL_RESERVED_179', 'CB_PERF_SEL_RESERVED_180', + 'CB_PERF_SEL_RESERVED_181', 'CB_PERF_SEL_RESERVED_182', + 'CB_PERF_SEL_RESERVED_183', 'CB_PERF_SEL_RESERVED_184', + 'CB_PERF_SEL_RESERVED_185', 'CB_PERF_SEL_RESERVED_186', + 'CB_PERF_SEL_RESERVED_187', 'CB_PERF_SEL_RESERVED_188', + 'CB_PERF_SEL_RESERVED_189', 'CB_PERF_SEL_RESERVED_190', + 'CB_PERF_SEL_RESERVED_191', 'CB_PERF_SEL_RESERVED_192', + 'CB_PERF_SEL_RESERVED_193', 'CB_PERF_SEL_RESERVED_194', + 'CB_PERF_SEL_RESERVED_195', 'CB_PERF_SEL_RESERVED_196', + 'CB_PERF_SEL_RESERVED_197', 'CB_PERF_SEL_RESERVED_198', + 'CB_PERF_SEL_RESERVED_199', 'CB_PERF_SEL_RESERVED_205', + 'CB_PERF_SEL_RESERVED_206', 'CB_PERF_SEL_RESERVED_207', + 'CB_PERF_SEL_RESERVED_208', 'CB_PERF_SEL_RESERVED_209', + 'CB_PERF_SEL_RESERVED_21', 'CB_PERF_SEL_RESERVED_210', + 'CB_PERF_SEL_RESERVED_211', 'CB_PERF_SEL_RESERVED_212', + 'CB_PERF_SEL_RESERVED_213', 'CB_PERF_SEL_RESERVED_214', + 'CB_PERF_SEL_RESERVED_215', 'CB_PERF_SEL_RESERVED_216', + 'CB_PERF_SEL_RESERVED_217', 'CB_PERF_SEL_RESERVED_218', + 'CB_PERF_SEL_RESERVED_219', 'CB_PERF_SEL_RESERVED_22', + 'CB_PERF_SEL_RESERVED_220', 'CB_PERF_SEL_RESERVED_221', + 'CB_PERF_SEL_RESERVED_222', 'CB_PERF_SEL_RESERVED_223', + 'CB_PERF_SEL_RESERVED_224', 'CB_PERF_SEL_RESERVED_225', + 'CB_PERF_SEL_RESERVED_226', 'CB_PERF_SEL_RESERVED_227', + 'CB_PERF_SEL_RESERVED_228', 'CB_PERF_SEL_RESERVED_229', + 'CB_PERF_SEL_RESERVED_23', 'CB_PERF_SEL_RESERVED_230', + 'CB_PERF_SEL_RESERVED_231', 'CB_PERF_SEL_RESERVED_232', + 'CB_PERF_SEL_RESERVED_233', 'CB_PERF_SEL_RESERVED_234', + 'CB_PERF_SEL_RESERVED_235', 'CB_PERF_SEL_RESERVED_236', + 'CB_PERF_SEL_RESERVED_237', 'CB_PERF_SEL_RESERVED_238', + 'CB_PERF_SEL_RESERVED_239', 'CB_PERF_SEL_RESERVED_24', + 'CB_PERF_SEL_RESERVED_240', 'CB_PERF_SEL_RESERVED_241', + 'CB_PERF_SEL_RESERVED_242', 'CB_PERF_SEL_RESERVED_243', + 'CB_PERF_SEL_RESERVED_244', 'CB_PERF_SEL_RESERVED_245', + 'CB_PERF_SEL_RESERVED_246', 'CB_PERF_SEL_RESERVED_247', + 'CB_PERF_SEL_RESERVED_248', 'CB_PERF_SEL_RESERVED_249', + 'CB_PERF_SEL_RESERVED_25', 'CB_PERF_SEL_RESERVED_259', + 'CB_PERF_SEL_RESERVED_26', 'CB_PERF_SEL_RESERVED_260', + 'CB_PERF_SEL_RESERVED_261', 'CB_PERF_SEL_RESERVED_262', + 'CB_PERF_SEL_RESERVED_263', 'CB_PERF_SEL_RESERVED_264', + 'CB_PERF_SEL_RESERVED_265', 'CB_PERF_SEL_RESERVED_266', + 'CB_PERF_SEL_RESERVED_267', 'CB_PERF_SEL_RESERVED_268', + 'CB_PERF_SEL_RESERVED_269', 'CB_PERF_SEL_RESERVED_27', + 'CB_PERF_SEL_RESERVED_270', 'CB_PERF_SEL_RESERVED_271', + 'CB_PERF_SEL_RESERVED_272', 'CB_PERF_SEL_RESERVED_273', + 'CB_PERF_SEL_RESERVED_274', 'CB_PERF_SEL_RESERVED_275', + 'CB_PERF_SEL_RESERVED_276', 'CB_PERF_SEL_RESERVED_277', + 'CB_PERF_SEL_RESERVED_278', 'CB_PERF_SEL_RESERVED_279', + 'CB_PERF_SEL_RESERVED_28', 'CB_PERF_SEL_RESERVED_280', + 'CB_PERF_SEL_RESERVED_281', 'CB_PERF_SEL_RESERVED_282', + 'CB_PERF_SEL_RESERVED_283', 'CB_PERF_SEL_RESERVED_284', + 'CB_PERF_SEL_RESERVED_285', 'CB_PERF_SEL_RESERVED_286', + 'CB_PERF_SEL_RESERVED_287', 'CB_PERF_SEL_RESERVED_288', + 'CB_PERF_SEL_RESERVED_289', 'CB_PERF_SEL_RESERVED_29', + 'CB_PERF_SEL_RESERVED_290', 'CB_PERF_SEL_RESERVED_291', + 'CB_PERF_SEL_RESERVED_292', 'CB_PERF_SEL_RESERVED_293', + 'CB_PERF_SEL_RESERVED_294', 'CB_PERF_SEL_RESERVED_295', + 'CB_PERF_SEL_RESERVED_296', 'CB_PERF_SEL_RESERVED_297', + 'CB_PERF_SEL_RESERVED_298', 'CB_PERF_SEL_RESERVED_299', + 'CB_PERF_SEL_RESERVED_303', 'CB_PERF_SEL_RESERVED_304', + 'CB_PERF_SEL_RESERVED_305', 'CB_PERF_SEL_RESERVED_306', + 'CB_PERF_SEL_RESERVED_307', 'CB_PERF_SEL_RESERVED_308', + 'CB_PERF_SEL_RESERVED_309', 'CB_PERF_SEL_RESERVED_310', + 'CB_PERF_SEL_RESERVED_311', 'CB_PERF_SEL_RESERVED_312', + 'CB_PERF_SEL_RESERVED_313', 'CB_PERF_SEL_RESERVED_314', + 'CB_PERF_SEL_RESERVED_315', 'CB_PERF_SEL_RESERVED_316', + 'CB_PERF_SEL_RESERVED_317', 'CB_PERF_SEL_RESERVED_318', + 'CB_PERF_SEL_RESERVED_319', 'CB_PERF_SEL_RESERVED_320', + 'CB_PERF_SEL_RESERVED_321', 'CB_PERF_SEL_RESERVED_322', + 'CB_PERF_SEL_RESERVED_323', 'CB_PERF_SEL_RESERVED_324', + 'CB_PERF_SEL_RESERVED_325', 'CB_PERF_SEL_RESERVED_326', + 'CB_PERF_SEL_RESERVED_327', 'CB_PERF_SEL_RESERVED_328', + 'CB_PERF_SEL_RESERVED_329', 'CB_PERF_SEL_RESERVED_330', + 'CB_PERF_SEL_RESERVED_331', 'CB_PERF_SEL_RESERVED_332', + 'CB_PERF_SEL_RESERVED_333', 'CB_PERF_SEL_RESERVED_334', + 'CB_PERF_SEL_RESERVED_335', 'CB_PERF_SEL_RESERVED_336', + 'CB_PERF_SEL_RESERVED_337', 'CB_PERF_SEL_RESERVED_338', + 'CB_PERF_SEL_RESERVED_339', 'CB_PERF_SEL_RESERVED_340', + 'CB_PERF_SEL_RESERVED_341', 'CB_PERF_SEL_RESERVED_342', + 'CB_PERF_SEL_RESERVED_343', 'CB_PERF_SEL_RESERVED_344', + 'CB_PERF_SEL_RESERVED_345', 'CB_PERF_SEL_RESERVED_346', + 'CB_PERF_SEL_RESERVED_347', 'CB_PERF_SEL_RESERVED_348', + 'CB_PERF_SEL_RESERVED_349', 'CB_PERF_SEL_RESERVED_350', + 'CB_PERF_SEL_RESERVED_351', 'CB_PERF_SEL_RESERVED_352', + 'CB_PERF_SEL_RESERVED_353', 'CB_PERF_SEL_RESERVED_354', + 'CB_PERF_SEL_RESERVED_355', 'CB_PERF_SEL_RESERVED_356', + 'CB_PERF_SEL_RESERVED_357', 'CB_PERF_SEL_RESERVED_358', + 'CB_PERF_SEL_RESERVED_359', 'CB_PERF_SEL_RESERVED_360', + 'CB_PERF_SEL_RESERVED_361', 'CB_PERF_SEL_RESERVED_362', + 'CB_PERF_SEL_RESERVED_363', 'CB_PERF_SEL_RESERVED_364', + 'CB_PERF_SEL_RESERVED_365', 'CB_PERF_SEL_RESERVED_366', + 'CB_PERF_SEL_RESERVED_367', 'CB_PERF_SEL_RESERVED_368', + 'CB_PERF_SEL_RESERVED_369', 'CB_PERF_SEL_RESERVED_370', + 'CB_PERF_SEL_RESERVED_371', 'CB_PERF_SEL_RESERVED_372', + 'CB_PERF_SEL_RESERVED_373', 'CB_PERF_SEL_RESERVED_374', + 'CB_PERF_SEL_RESERVED_375', 'CB_PERF_SEL_RESERVED_376', + 'CB_PERF_SEL_RESERVED_377', 'CB_PERF_SEL_RESERVED_378', + 'CB_PERF_SEL_RESERVED_379', 'CB_PERF_SEL_RESERVED_38', + 'CB_PERF_SEL_RESERVED_380', 'CB_PERF_SEL_RESERVED_381', + 'CB_PERF_SEL_RESERVED_382', 'CB_PERF_SEL_RESERVED_383', + 'CB_PERF_SEL_RESERVED_384', 'CB_PERF_SEL_RESERVED_385', + 'CB_PERF_SEL_RESERVED_386', 'CB_PERF_SEL_RESERVED_387', + 'CB_PERF_SEL_RESERVED_388', 'CB_PERF_SEL_RESERVED_389', + 'CB_PERF_SEL_RESERVED_39', 'CB_PERF_SEL_RESERVED_390', + 'CB_PERF_SEL_RESERVED_391', 'CB_PERF_SEL_RESERVED_392', + 'CB_PERF_SEL_RESERVED_393', 'CB_PERF_SEL_RESERVED_394', + 'CB_PERF_SEL_RESERVED_395', 'CB_PERF_SEL_RESERVED_396', + 'CB_PERF_SEL_RESERVED_397', 'CB_PERF_SEL_RESERVED_398', + 'CB_PERF_SEL_RESERVED_399', 'CB_PERF_SEL_RESERVED_40', + 'CB_PERF_SEL_RESERVED_400', 'CB_PERF_SEL_RESERVED_401', + 'CB_PERF_SEL_RESERVED_402', 'CB_PERF_SEL_RESERVED_403', + 'CB_PERF_SEL_RESERVED_404', 'CB_PERF_SEL_RESERVED_405', + 'CB_PERF_SEL_RESERVED_406', 'CB_PERF_SEL_RESERVED_407', + 'CB_PERF_SEL_RESERVED_408', 'CB_PERF_SEL_RESERVED_409', + 'CB_PERF_SEL_RESERVED_41', 'CB_PERF_SEL_RESERVED_410', + 'CB_PERF_SEL_RESERVED_411', 'CB_PERF_SEL_RESERVED_412', + 'CB_PERF_SEL_RESERVED_413', 'CB_PERF_SEL_RESERVED_414', + 'CB_PERF_SEL_RESERVED_415', 'CB_PERF_SEL_RESERVED_416', + 'CB_PERF_SEL_RESERVED_417', 'CB_PERF_SEL_RESERVED_418', + 'CB_PERF_SEL_RESERVED_419', 'CB_PERF_SEL_RESERVED_42', + 'CB_PERF_SEL_RESERVED_420', 'CB_PERF_SEL_RESERVED_421', + 'CB_PERF_SEL_RESERVED_422', 'CB_PERF_SEL_RESERVED_423', + 'CB_PERF_SEL_RESERVED_424', 'CB_PERF_SEL_RESERVED_425', + 'CB_PERF_SEL_RESERVED_426', 'CB_PERF_SEL_RESERVED_427', + 'CB_PERF_SEL_RESERVED_428', 'CB_PERF_SEL_RESERVED_429', + 'CB_PERF_SEL_RESERVED_43', 'CB_PERF_SEL_RESERVED_430', + 'CB_PERF_SEL_RESERVED_431', 'CB_PERF_SEL_RESERVED_432', + 'CB_PERF_SEL_RESERVED_433', 'CB_PERF_SEL_RESERVED_434', + 'CB_PERF_SEL_RESERVED_435', 'CB_PERF_SEL_RESERVED_436', + 'CB_PERF_SEL_RESERVED_437', 'CB_PERF_SEL_RESERVED_438', + 'CB_PERF_SEL_RESERVED_439', 'CB_PERF_SEL_RESERVED_44', + 'CB_PERF_SEL_RESERVED_440', 'CB_PERF_SEL_RESERVED_441', + 'CB_PERF_SEL_RESERVED_442', 'CB_PERF_SEL_RESERVED_443', + 'CB_PERF_SEL_RESERVED_444', 'CB_PERF_SEL_RESERVED_445', + 'CB_PERF_SEL_RESERVED_446', 'CB_PERF_SEL_RESERVED_447', + 'CB_PERF_SEL_RESERVED_448', 'CB_PERF_SEL_RESERVED_449', + 'CB_PERF_SEL_RESERVED_45', 'CB_PERF_SEL_RESERVED_450', + 'CB_PERF_SEL_RESERVED_451', 'CB_PERF_SEL_RESERVED_452', + 'CB_PERF_SEL_RESERVED_453', 'CB_PERF_SEL_RESERVED_454', + 'CB_PERF_SEL_RESERVED_455', 'CB_PERF_SEL_RESERVED_456', + 'CB_PERF_SEL_RESERVED_457', 'CB_PERF_SEL_RESERVED_458', + 'CB_PERF_SEL_RESERVED_459', 'CB_PERF_SEL_RESERVED_46', + 'CB_PERF_SEL_RESERVED_460', 'CB_PERF_SEL_RESERVED_461', + 'CB_PERF_SEL_RESERVED_462', 'CB_PERF_SEL_RESERVED_463', + 'CB_PERF_SEL_RESERVED_464', 'CB_PERF_SEL_RESERVED_465', + 'CB_PERF_SEL_RESERVED_47', 'CB_PERF_SEL_RESERVED_48', + 'CB_PERF_SEL_RESERVED_49', 'CB_PERF_SEL_RESERVED_65', + 'CB_PERF_SEL_RESERVED_66', 'CB_PERF_SEL_RESERVED_67', + 'CB_PERF_SEL_RESERVED_68', 'CB_PERF_SEL_RESERVED_69', + 'CB_PERF_SEL_RESERVED_70', 'CB_PERF_SEL_RESERVED_71', + 'CB_PERF_SEL_RESERVED_72', 'CB_PERF_SEL_RESERVED_73', + 'CB_PERF_SEL_RESERVED_74', 'CB_PERF_SEL_RESERVED_75', + 'CB_PERF_SEL_RESERVED_76', 'CB_PERF_SEL_RESERVED_77', + 'CB_PERF_SEL_RESERVED_78', 'CB_PERF_SEL_RESERVED_79', + 'CB_PERF_SEL_RESERVED_80', 'CB_PERF_SEL_RESERVED_81', + 'CB_PERF_SEL_RESERVED_82', 'CB_PERF_SEL_RESERVED_83', + 'CB_PERF_SEL_RESERVED_84', 'CB_PERF_SEL_RESERVED_85', + 'CB_PERF_SEL_RESERVED_86', 'CB_PERF_SEL_RESERVED_87', + 'CB_PERF_SEL_RESERVED_88', 'CB_PERF_SEL_RESERVED_89', + 'CB_PERF_SEL_RESERVED_90', 'CB_PERF_SEL_RESERVED_91', + 'CB_PERF_SEL_RESERVED_92', 'CB_PERF_SEL_RESERVED_93', + 'CB_PERF_SEL_RESERVED_94', 'CB_PERF_SEL_RESERVED_95', + 'CB_PERF_SEL_RESERVED_96', 'CB_PERF_SEL_RESERVED_97', + 'CB_PERF_SEL_RESERVED_98', 'CB_PERF_SEL_RESERVED_99', + 'CB_PERF_SEL_STATIC_CLOCK_EN', 'CB_RESERVED', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6', + 'CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL', + 'CENTERS_ONLY', 'CENTROIDS_AND_CENTERS', 'CENTROIDS_ONLY', + 'CE_PARTITION_BASE', 'CHA_PERF_SEL', 'CHA_PERF_SEL_ARB_REQUESTS', + 'CHA_PERF_SEL_BUSY', 'CHA_PERF_SEL_CYCLE', + 'CHA_PERF_SEL_IO_32B_WDS_CHC0', 'CHA_PERF_SEL_IO_32B_WDS_CHC1', + 'CHA_PERF_SEL_IO_32B_WDS_CHC2', 'CHA_PERF_SEL_IO_32B_WDS_CHC3', + 'CHA_PERF_SEL_IO_32B_WDS_CHC4', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC0', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC1', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC2', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC3', + 'CHA_PERF_SEL_IO_BURST_COUNT_CHC4', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC0', 'CHA_PERF_SEL_MEM_32B_WDS_CHC1', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC2', 'CHA_PERF_SEL_MEM_32B_WDS_CHC3', + 'CHA_PERF_SEL_MEM_32B_WDS_CHC4', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC0', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC1', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC2', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC3', + 'CHA_PERF_SEL_MEM_BURST_COUNT_CHC4', 'CHA_PERF_SEL_REQUEST_CHC0', + 'CHA_PERF_SEL_REQUEST_CHC1', 'CHA_PERF_SEL_REQUEST_CHC2', + 'CHA_PERF_SEL_REQUEST_CHC3', 'CHA_PERF_SEL_REQUEST_CHC4', + 'CHA_PERF_SEL_REQ_INFLIGHT_LEVEL', 'CHA_PERF_SEL_STALL_CHC0', + 'CHA_PERF_SEL_STALL_CHC1', 'CHA_PERF_SEL_STALL_CHC2', + 'CHA_PERF_SEL_STALL_CHC3', 'CHA_PERF_SEL_STALL_CHC4', + 'CHA_PERF_SEL_STALL_CHC5', 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3', + 'CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4', 'CHCG_PERF_SEL', + 'CHCG_PERF_SEL_ARB_RET_LEVEL', 'CHCG_PERF_SEL_BUSY', + 'CHCG_PERF_SEL_CYCLE', 'CHCG_PERF_SEL_GL2_REQ_READ_LATENCY', + 'CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHCG_PERF_SEL_REQ', + 'CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 'CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHCG_PERF_SEL_REQ_CLIENT0', + 'CHCG_PERF_SEL_REQ_CLIENT1', 'CHCG_PERF_SEL_REQ_CLIENT10', + 'CHCG_PERF_SEL_REQ_CLIENT11', 'CHCG_PERF_SEL_REQ_CLIENT12', + 'CHCG_PERF_SEL_REQ_CLIENT13', 'CHCG_PERF_SEL_REQ_CLIENT14', + 'CHCG_PERF_SEL_REQ_CLIENT15', 'CHCG_PERF_SEL_REQ_CLIENT16', + 'CHCG_PERF_SEL_REQ_CLIENT17', 'CHCG_PERF_SEL_REQ_CLIENT18', + 'CHCG_PERF_SEL_REQ_CLIENT19', 'CHCG_PERF_SEL_REQ_CLIENT2', + 'CHCG_PERF_SEL_REQ_CLIENT20', 'CHCG_PERF_SEL_REQ_CLIENT21', + 'CHCG_PERF_SEL_REQ_CLIENT22', 'CHCG_PERF_SEL_REQ_CLIENT23', + 'CHCG_PERF_SEL_REQ_CLIENT3', 'CHCG_PERF_SEL_REQ_CLIENT4', + 'CHCG_PERF_SEL_REQ_CLIENT5', 'CHCG_PERF_SEL_REQ_CLIENT6', + 'CHCG_PERF_SEL_REQ_CLIENT7', 'CHCG_PERF_SEL_REQ_CLIENT8', + 'CHCG_PERF_SEL_REQ_CLIENT9', 'CHCG_PERF_SEL_REQ_NOP_ACK', + 'CHCG_PERF_SEL_REQ_NOP_RTN0', 'CHCG_PERF_SEL_REQ_READ', + 'CHCG_PERF_SEL_REQ_READ_128B', 'CHCG_PERF_SEL_REQ_READ_32B', + 'CHCG_PERF_SEL_REQ_READ_64B', 'CHCG_PERF_SEL_REQ_WRITE', + 'CHCG_PERF_SEL_REQ_WRITE_32B', 'CHCG_PERF_SEL_REQ_WRITE_64B', + 'CHCG_PERF_SEL_STALL_BUFFER_FULL', 'CHCG_PERF_SEL_STALL_GUS_GL1', + 'CHCG_PERF_SEL_STARVE', 'CHC_PERF_SEL', + 'CHC_PERF_SEL_ARB_RET_LEVEL', 'CHC_PERF_SEL_BUSY', + 'CHC_PERF_SEL_CYCLE', 'CHC_PERF_SEL_GL2_REQ_READ_LATENCY', + 'CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'CHC_PERF_SEL_REQ', + 'CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 'CHC_PERF_SEL_REQ_ATOMIC_WITH_RET', 'CHC_PERF_SEL_REQ_CLIENT0', + 'CHC_PERF_SEL_REQ_CLIENT1', 'CHC_PERF_SEL_REQ_CLIENT10', + 'CHC_PERF_SEL_REQ_CLIENT11', 'CHC_PERF_SEL_REQ_CLIENT12', + 'CHC_PERF_SEL_REQ_CLIENT13', 'CHC_PERF_SEL_REQ_CLIENT14', + 'CHC_PERF_SEL_REQ_CLIENT15', 'CHC_PERF_SEL_REQ_CLIENT16', + 'CHC_PERF_SEL_REQ_CLIENT17', 'CHC_PERF_SEL_REQ_CLIENT18', + 'CHC_PERF_SEL_REQ_CLIENT19', 'CHC_PERF_SEL_REQ_CLIENT2', + 'CHC_PERF_SEL_REQ_CLIENT20', 'CHC_PERF_SEL_REQ_CLIENT21', + 'CHC_PERF_SEL_REQ_CLIENT22', 'CHC_PERF_SEL_REQ_CLIENT23', + 'CHC_PERF_SEL_REQ_CLIENT3', 'CHC_PERF_SEL_REQ_CLIENT4', + 'CHC_PERF_SEL_REQ_CLIENT5', 'CHC_PERF_SEL_REQ_CLIENT6', + 'CHC_PERF_SEL_REQ_CLIENT7', 'CHC_PERF_SEL_REQ_CLIENT8', + 'CHC_PERF_SEL_REQ_CLIENT9', 'CHC_PERF_SEL_REQ_NOP_ACK', + 'CHC_PERF_SEL_REQ_NOP_RTN0', 'CHC_PERF_SEL_REQ_READ', + 'CHC_PERF_SEL_REQ_READ_128B', 'CHC_PERF_SEL_REQ_READ_32B', + 'CHC_PERF_SEL_REQ_READ_64B', 'CHC_PERF_SEL_REQ_WRITE', + 'CHC_PERF_SEL_REQ_WRITE_32B', 'CHC_PERF_SEL_REQ_WRITE_64B', + 'CHC_PERF_SEL_STALL_BUFFER_FULL', 'CHC_PERF_SEL_STALL_GL2_GL1', + 'CHC_PERF_SEL_STARVE', 'CHUNK_SIZE', 'CHUNK_SIZE_16KB', + 'CHUNK_SIZE_1KB', 'CHUNK_SIZE_2KB', 'CHUNK_SIZE_32KB', + 'CHUNK_SIZE_4KB', 'CHUNK_SIZE_64KB', 'CHUNK_SIZE_8KB', + 'CLEAR_SMU_INTR', 'CLKGATE_BASE_MODE', 'CLKGATE_SM_MODE', + 'CLK_BASE', 'CLK_BASE__INST0_SEG0', 'CLK_BASE__INST0_SEG1', 'CLK_BASE__INST0_SEG2', 'CLK_BASE__INST0_SEG3', 'CLK_BASE__INST0_SEG4', 'CLK_BASE__INST1_SEG0', 'CLK_BASE__INST1_SEG1', 'CLK_BASE__INST1_SEG2', @@ -13858,7 +62792,806 @@ __all__ = \ 'CLK_BASE__INST5_SEG3', 'CLK_BASE__INST5_SEG4', 'CLK_BASE__INST6_SEG0', 'CLK_BASE__INST6_SEG1', 'CLK_BASE__INST6_SEG2', 'CLK_BASE__INST6_SEG3', - 'CLK_BASE__INST6_SEG4', 'CP_PACKET2', 'DCN_BASE', + 'CLK_BASE__INST6_SEG4', 'CLOCK_BRANCH_SOFT_RESET', + 'CLOCK_BRANCH_SOFT_RESET_FORCE', 'CLOCK_BRANCH_SOFT_RESET_NOOP', + 'CLOCK_GATING_DISABLE', 'CLOCK_GATING_DISABLED', + 'CLOCK_GATING_DISABLED_IN_DCO', 'CLOCK_GATING_DISABLE_ENUM', + 'CLOCK_GATING_DISABLE_ENUM_DISABLED', + 'CLOCK_GATING_DISABLE_ENUM_ENABLED', 'CLOCK_GATING_EN', + 'CLOCK_GATING_ENABLE', 'CLOCK_GATING_ENABLED', + 'CLOCK_GATING_ENABLED_IN_DCO', 'CMASK_CLR00_F0', 'CMASK_CLR00_F1', + 'CMASK_CLR00_F2', 'CMASK_CLR00_FX', 'CMASK_CLR01_F0', + 'CMASK_CLR01_F1', 'CMASK_CLR01_F2', 'CMASK_CLR01_FX', + 'CMASK_CLR10_F0', 'CMASK_CLR10_F1', 'CMASK_CLR10_F2', + 'CMASK_CLR10_FX', 'CMASK_CLR11_F0', 'CMASK_CLR11_F1', + 'CMASK_CLR11_F2', 'CMASK_CLR11_FX', 'CMC_3DLUT_17CUBE', + 'CMC_3DLUT_30BIT', 'CMC_3DLUT_30BIT_ENUM', 'CMC_3DLUT_36BIT', + 'CMC_3DLUT_9CUBE', 'CMC_3DLUT_RAM_SEL', 'CMC_3DLUT_SIZE_ENUM', + 'CMC_LUT_2CFG_MEMORY_A', 'CMC_LUT_2CFG_MEMORY_B', + 'CMC_LUT_2CFG_NO_MEMORY', 'CMC_LUT_2_CONFIG_ENUM', + 'CMC_LUT_2_MODE_BYPASS', 'CMC_LUT_2_MODE_ENUM', + 'CMC_LUT_2_MODE_RAMA_LUT', 'CMC_LUT_2_MODE_RAMB_LUT', + 'CMC_LUT_NUM_SEG', 'CMC_LUT_RAM_SEL', 'CMC_RAM0_ACCESS', + 'CMC_RAM1_ACCESS', 'CMC_RAM2_ACCESS', 'CMC_RAM3_ACCESS', + 'CMC_RAMA_ACCESS', 'CMC_RAMB_ACCESS', 'CMC_SEGMENTS_1', + 'CMC_SEGMENTS_128', 'CMC_SEGMENTS_16', 'CMC_SEGMENTS_2', + 'CMC_SEGMENTS_32', 'CMC_SEGMENTS_4', 'CMC_SEGMENTS_64', + 'CMC_SEGMENTS_8', 'CMPTO', 'CM_BYPASS', 'CM_COEF_FORMAT_ENUM', + 'CM_DATA_SIGNED', 'CM_DISABLE', 'CM_EN', 'CM_ENABLE', + 'CM_GAMMA_LUT_MODE_ENUM', 'CM_GAMMA_LUT_PWL_DISABLE_ENUM', + 'CM_GAMMA_LUT_SEL_ENUM', 'CM_GAMUT_REMAP_MODE_ENUM', + 'CM_LUT_2_CONFIG_ENUM', 'CM_LUT_2_MODE_ENUM', + 'CM_LUT_4_CONFIG_ENUM', 'CM_LUT_4_MODE_ENUM', + 'CM_LUT_CONFIG_MODE', 'CM_LUT_NUM_SEG', 'CM_LUT_RAM_SEL', + 'CM_LUT_READ_COLOR_SEL', 'CM_LUT_READ_DBG', 'CM_NOT_PENDING', + 'CM_PENDING', 'CM_POST_CSC_MODE_ENUM', 'CM_WRITE_BASE_ONLY', + 'CM_YES_PENDING', 'CNVC_BYPASS', 'CNVC_BYPASS_DISABLE', + 'CNVC_BYPASS_EN', 'CNVC_COEF_FORMAT_ENUM', 'CNVC_DIS', 'CNVC_EN', + 'CNVC_ENABLE', 'CNVC_FIX_S2_13', 'CNVC_FIX_S3_12', + 'CNVC_NOT_PENDING', 'CNVC_PENDING', 'CNVC_ROUND', 'CNVC_TRUNCATE', + 'CNVC_YES_PENDING', 'COEF_POST_CSC', 'COEF_POST_CSC_B', + 'COEF_RAM_SELECT_BACK', 'COEF_RAM_SELECT_CURRENT', + 'COEF_RAM_SELECT_RD', 'COLOR_24BIT_1BIT_AND', + 'COLOR_24BIT_8BIT_ALPHA_PREMULT', + 'COLOR_24BIT_8BIT_ALPHA_UNPREMULT', 'COLOR_64BIT_FP_PREMULT', + 'COLOR_64BIT_FP_UNPREMULT', 'COLOR_KEYER_MODE', + 'COMB_DST_MINUS_SRC', 'COMB_DST_PLUS_SRC', 'COMB_MAX_DST_SRC', + 'COMB_MIN_DST_SRC', 'COMB_SRC_MINUS_DST', 'COMPAT_LEVEL', + 'CONFIG_SPACE1_END', 'CONFIG_SPACE1_START', 'CONFIG_SPACE2_END', + 'CONFIG_SPACE2_START', 'CONFIG_SPACE_END', 'CONFIG_SPACE_START', + 'CONTEXT_DONE', 'CONTEXT_SPACE_END', 'CONTEXT_SPACE_START', + 'CONTEXT_SUSPEND', 'CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET', + 'CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET', + 'CORB_READ_POINTER_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET', + 'CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET', 'COUNTER_RING_0', + 'COUNTER_RING_1', 'COUNTER_RING_SPLIT', 'CPC_LATENCY_STATS_SEL', + 'CPC_LATENCY_STATS_SEL_INVAL_LAST', + 'CPC_LATENCY_STATS_SEL_INVAL_MAX', + 'CPC_LATENCY_STATS_SEL_INVAL_MIN', + 'CPC_LATENCY_STATS_SEL_XACK_LAST', + 'CPC_LATENCY_STATS_SEL_XACK_MAX', + 'CPC_LATENCY_STATS_SEL_XACK_MIN', + 'CPC_LATENCY_STATS_SEL_XNACK_LAST', + 'CPC_LATENCY_STATS_SEL_XNACK_MAX', + 'CPC_LATENCY_STATS_SEL_XNACK_MIN', 'CPC_PERFCOUNT_SEL', + 'CPC_PERF_SEL_ALWAYS_COUNT', 'CPC_PERF_SEL_CPC_GCRIU_BUSY', + 'CPC_PERF_SEL_CPC_GCRIU_IDLE', 'CPC_PERF_SEL_CPC_GCRIU_STALL', + 'CPC_PERF_SEL_CPC_STAT_BUSY', 'CPC_PERF_SEL_CPC_STAT_IDLE', + 'CPC_PERF_SEL_CPC_STAT_STALL', 'CPC_PERF_SEL_CPC_TCIU_BUSY', + 'CPC_PERF_SEL_CPC_TCIU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_BUSY', + 'CPC_PERF_SEL_CPC_UTCL2IU_IDLE', 'CPC_PERF_SEL_CPC_UTCL2IU_STALL', + 'CPC_PERF_SEL_CPC_UTCL2IU_XACK', 'CPC_PERF_SEL_CPC_UTCL2IU_XNACK', + 'CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME1_DC0_SPI_BUSY', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ', + 'CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE', + 'CPC_PERF_SEL_ME2_DC1_SPI_BUSY', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ', + 'CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF', + 'CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ', + 'CPC_PERF_SEL_MEC_INSTR_CACHE_HIT', + 'CPC_PERF_SEL_MEC_INSTR_CACHE_MISS', 'CPC_PERF_SEL_MES_THREAD0', + 'CPC_PERF_SEL_MES_THREAD1', + 'CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION', + 'CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPC_TAG_RAM', + 'CPF_LATENCY_STATS_SEL', 'CPF_LATENCY_STATS_SEL_INVAL_LAST', + 'CPF_LATENCY_STATS_SEL_INVAL_MAX', + 'CPF_LATENCY_STATS_SEL_INVAL_MIN', + 'CPF_LATENCY_STATS_SEL_READ_LAST', + 'CPF_LATENCY_STATS_SEL_READ_MAX', + 'CPF_LATENCY_STATS_SEL_READ_MIN', + 'CPF_LATENCY_STATS_SEL_XACK_LAST', + 'CPF_LATENCY_STATS_SEL_XACK_MAX', + 'CPF_LATENCY_STATS_SEL_XACK_MIN', + 'CPF_LATENCY_STATS_SEL_XNACK_LAST', + 'CPF_LATENCY_STATS_SEL_XNACK_MAX', + 'CPF_LATENCY_STATS_SEL_XNACK_MIN', 'CPF_PERFCOUNTWINDOW_SEL', + 'CPF_PERFCOUNT_SEL', 'CPF_PERFWINDOW_SEL_CSF', + 'CPF_PERFWINDOW_SEL_HQD1', 'CPF_PERFWINDOW_SEL_HQD2', + 'CPF_PERFWINDOW_SEL_RDMA', 'CPF_PERFWINDOW_SEL_RWPP', + 'CPF_PERF_SEL_ALWAYS_COUNT', + 'CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION', + 'CPF_PERF_SEL_CPF_GCRIU_BUSY', 'CPF_PERF_SEL_CPF_GCRIU_IDLE', + 'CPF_PERF_SEL_CPF_GCRIU_STALL', 'CPF_PERF_SEL_CPF_STAT_BUSY', + 'CPF_PERF_SEL_CPF_STAT_IDLE', 'CPF_PERF_SEL_CPF_STAT_STALL', + 'CPF_PERF_SEL_CPF_TCIU_BUSY', 'CPF_PERF_SEL_CPF_TCIU_IDLE', + 'CPF_PERF_SEL_CPF_TCIU_STALL', 'CPF_PERF_SEL_CPF_UTCL2IU_BUSY', + 'CPF_PERF_SEL_CPF_UTCL2IU_IDLE', 'CPF_PERF_SEL_CPF_UTCL2IU_STALL', + 'CPF_PERF_SEL_CPF_UTCL2IU_XACK', 'CPF_PERF_SEL_CPF_UTCL2IU_XNACK', + 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE', + 'CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ', + 'CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY', + 'CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING', + 'CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE', + 'CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS', + 'CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR', + 'CPF_PERF_SEL_DYNAMIC_CLOCK_VALID', + 'CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION', + 'CPF_PERF_SEL_GRBM_DWORDS_SENT', + 'CPF_PERF_SEL_GUS_READ_REQUEST_SENT', + 'CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 'CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_REGISTER_CLOCK_VALID', + 'CPF_PERF_SEL_TCIU_READ_REQUEST_SENT', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE', + 'CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS', + 'CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', + 'CPF_SCRATCH_REG_ATOMIC_ADD', 'CPF_SCRATCH_REG_ATOMIC_AND', + 'CPF_SCRATCH_REG_ATOMIC_CMPSWAP', 'CPF_SCRATCH_REG_ATOMIC_MAX', + 'CPF_SCRATCH_REG_ATOMIC_MIN', 'CPF_SCRATCH_REG_ATOMIC_NOT', + 'CPF_SCRATCH_REG_ATOMIC_OP', 'CPF_SCRATCH_REG_ATOMIC_OR', + 'CPF_SCRATCH_REG_ATOMIC_SUB', 'CPF_TAG_RAM', + 'CPG_LATENCY_STATS_SEL', 'CPG_LATENCY_STATS_SEL_ATOMIC_LAST', + 'CPG_LATENCY_STATS_SEL_ATOMIC_MAX', + 'CPG_LATENCY_STATS_SEL_ATOMIC_MIN', + 'CPG_LATENCY_STATS_SEL_INVAL_LAST', + 'CPG_LATENCY_STATS_SEL_INVAL_MAX', + 'CPG_LATENCY_STATS_SEL_INVAL_MIN', + 'CPG_LATENCY_STATS_SEL_READ_LAST', + 'CPG_LATENCY_STATS_SEL_READ_MAX', + 'CPG_LATENCY_STATS_SEL_READ_MIN', + 'CPG_LATENCY_STATS_SEL_WRITE_LAST', + 'CPG_LATENCY_STATS_SEL_WRITE_MAX', + 'CPG_LATENCY_STATS_SEL_WRITE_MIN', + 'CPG_LATENCY_STATS_SEL_XACK_LAST', + 'CPG_LATENCY_STATS_SEL_XACK_MAX', + 'CPG_LATENCY_STATS_SEL_XACK_MIN', + 'CPG_LATENCY_STATS_SEL_XNACK_LAST', + 'CPG_LATENCY_STATS_SEL_XNACK_MAX', + 'CPG_LATENCY_STATS_SEL_XNACK_MIN', 'CPG_PERFCOUNTWINDOW_SEL', + 'CPG_PERFCOUNT_SEL', 'CPG_PERFWINDOW_SEL_APPEND', + 'CPG_PERFWINDOW_SEL_CE', 'CPG_PERFWINDOW_SEL_CEDMA', + 'CPG_PERFWINDOW_SEL_CPC_IC', 'CPG_PERFWINDOW_SEL_CPG_IC', + 'CPG_PERFWINDOW_SEL_DDID', 'CPG_PERFWINDOW_SEL_DFY', + 'CPG_PERFWINDOW_SEL_DMA', 'CPG_PERFWINDOW_SEL_ME', + 'CPG_PERFWINDOW_SEL_MEC1', 'CPG_PERFWINDOW_SEL_MEC2', + 'CPG_PERFWINDOW_SEL_MEMRD', 'CPG_PERFWINDOW_SEL_MEMWR', + 'CPG_PERFWINDOW_SEL_MES', 'CPG_PERFWINDOW_SEL_PFP', + 'CPG_PERFWINDOW_SEL_PQ1', 'CPG_PERFWINDOW_SEL_PQ2', + 'CPG_PERFWINDOW_SEL_PQ3', 'CPG_PERFWINDOW_SEL_PRT_HDR_RPTR', + 'CPG_PERFWINDOW_SEL_PRT_SMP_RPTR', 'CPG_PERFWINDOW_SEL_QURD', + 'CPG_PERFWINDOW_SEL_QU_EOP', 'CPG_PERFWINDOW_SEL_QU_PIPE', + 'CPG_PERFWINDOW_SEL_QU_STRM', 'CPG_PERFWINDOW_SEL_RB', + 'CPG_PERFWINDOW_SEL_RESERVED1', 'CPG_PERFWINDOW_SEL_RESERVED2', + 'CPG_PERFWINDOW_SEL_SHADOW', 'CPG_PERFWINDOW_SEL_SR', + 'CPG_PERFWINDOW_SEL_VGT0', 'CPG_PERFWINDOW_SEL_VGT1', + 'CPG_PERF_SEL_ALL_GFX_PIPES_BUSY', 'CPG_PERF_SEL_ALWAYS_COUNT', + 'CPG_PERF_SEL_CE_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_CE_INSTR_CACHE_MISS', + 'CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG', + 'CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ', + 'CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER', + 'CPG_PERF_SEL_CE_STALL_ON_INC_FIFO', + 'CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO', + 'CPG_PERF_SEL_CE_STALL_RAM_DUMP', + 'CPG_PERF_SEL_CE_STALL_RAM_WRITE', + 'CPG_PERF_SEL_COUNT_TYPE0_PACKETS', + 'CPG_PERF_SEL_COUNT_TYPE3_PACKETS', 'CPG_PERF_SEL_CPG_GCRIU_BUSY', + 'CPG_PERF_SEL_CPG_GCRIU_IDLE', 'CPG_PERF_SEL_CPG_GCRIU_STALL', + 'CPG_PERF_SEL_CPG_STAT_BUSY', 'CPG_PERF_SEL_CPG_STAT_IDLE', + 'CPG_PERF_SEL_CPG_STAT_STALL', 'CPG_PERF_SEL_CPG_TCIU_BUSY', + 'CPG_PERF_SEL_CPG_TCIU_IDLE', 'CPG_PERF_SEL_CPG_TCIU_STALL', + 'CPG_PERF_SEL_CPG_UTCL2IU_BUSY', 'CPG_PERF_SEL_CPG_UTCL2IU_IDLE', + 'CPG_PERF_SEL_CPG_UTCL2IU_STALL', 'CPG_PERF_SEL_CPG_UTCL2IU_XACK', + 'CPG_PERF_SEL_CPG_UTCL2IU_XNACK', + 'CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_GRBM_DWORDS_SENT', + 'CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS', + 'CPG_PERF_SEL_DMA_BUSY', + 'CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL', + 'CPG_PERF_SEL_DMA_STALLED', 'CPG_PERF_SEL_DMA_STARVED', + 'CPG_PERF_SEL_DYNAMIC_CLK_VALID', + 'CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_GUS_READ_REQUEST_SENT', + 'CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT', + 'CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY', + 'CPG_PERF_SEL_ME_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_ME_INSTR_CACHE_MISS', 'CPG_PERF_SEL_ME_PARSER_BUSY', + 'CPG_PERF_SEL_ME_PWS_STALLED0', 'CPG_PERF_SEL_ME_PWS_STALLED1', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP', + 'CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ', + 'CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX', + 'CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH', + 'CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS', + 'CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU', + 'CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER', + 'CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER', + 'CPG_PERF_SEL_PFP_INSTR_CACHE_HIT', + 'CPG_PERF_SEL_PFP_INSTR_CACHE_MISS', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1', + 'CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2', + 'CPG_PERF_SEL_PFP_PWS_STALLED0', 'CPG_PERF_SEL_PFP_PWS_STALLED1', + 'CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ', + 'CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY', + 'CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE', + 'CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM', + 'CPG_PERF_SEL_RBIU_FIFO_FULL', + 'CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ', + 'CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ', + 'CPG_PERF_SEL_REGISTER_CLK_VALID', + 'CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX', + 'CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS', + 'CPG_PERF_SEL_TCIU_READ_REQUEST_SENT', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS', + 'CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT', + 'CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE', + 'CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS', 'CPG_TAG_RAM', + 'CP_ALPHA_TAG_RAM_SEL', 'CP_DDID_CNTL_MODE', 'CP_DDID_CNTL_SIZE', + 'CP_DDID_CNTL_VMID_SEL', 'CP_ME_ID', 'CP_PACKET2', + 'CP_PERFMON_ENABLE_MODE', 'CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE', + 'CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE', + 'CP_PERFMON_ENABLE_MODE_RESERVED_1', 'CP_PERFMON_STATE', + 'CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'CP_PERFMON_STATE_DISABLE_AND_RESET', + 'CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'CP_PERFMON_STATE_RESERVED_3', 'CP_PERFMON_STATE_START_COUNTING', + 'CP_PERFMON_STATE_STOP_COUNTING', 'CP_PIPE_ID', 'CP_RING_ID', + 'CRC_CUR_0', 'CRC_CUR_1', 'CRC_CUR_SEL', 'CRC_INTERLACE_0', + 'CRC_INTERLACE_1', 'CRC_INTERLACE_2', 'CRC_INTERLACE_3', + 'CRC_INTERLACE_SEL', 'CRC_IN_CUR_0', 'CRC_IN_CUR_1', + 'CRC_IN_CUR_2', 'CRC_IN_CUR_3', 'CRC_IN_CUR_SEL', 'CRC_IN_PIX_0', + 'CRC_IN_PIX_1', 'CRC_IN_PIX_2', 'CRC_IN_PIX_3', 'CRC_IN_PIX_4', + 'CRC_IN_PIX_5', 'CRC_IN_PIX_6', 'CRC_IN_PIX_7', 'CRC_IN_PIX_SEL', + 'CRC_SRC_0', 'CRC_SRC_1', 'CRC_SRC_2', 'CRC_SRC_3', 'CRC_SRC_SEL', + 'CRC_STEREO_0', 'CRC_STEREO_1', 'CRC_STEREO_2', 'CRC_STEREO_3', + 'CRC_STEREO_SEL', 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_2', + 'CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'CROB_MEM_PWR_LIGHT_SLEEP_MODE', 'CROSSBAR_FOR_ALPHA', + 'CROSSBAR_FOR_CB_B', 'CROSSBAR_FOR_CR_R', 'CROSSBAR_FOR_Y_G', + 'CRS', 'CR_R_DATA_ONTO_ALPHA_PORT', 'CR_R_DATA_ONTO_CB_B_PORT', + 'CR_R_DATA_ONTO_CR_R_PORT', 'CR_R_DATA_ONTO_Y_G_PORT', + 'CSCNTL_ADDR_WIDTH', 'CSCNTL_DATA_WIDTH', 'CSCNTL_TYPE', + 'CSCNTL_TYPE_EVENT', 'CSCNTL_TYPE_PRIVATE', 'CSCNTL_TYPE_STATE', + 'CSCNTL_TYPE_TG', 'CSCNTL_TYPE_WIDTH', 'CSDATA_ADDR_WIDTH', + 'CSDATA_DATA_WIDTH', 'CSDATA_TYPE', 'CSDATA_TYPE_EVENT', + 'CSDATA_TYPE_PRIVATE', 'CSDATA_TYPE_STATE', 'CSDATA_TYPE_TG', + 'CSDATA_TYPE_WIDTH', 'CS_CONTEXT_DONE', 'CS_DONE', 'CS_NA', + 'CS_PARTIAL_FLUSH', 'CS_STAGE_ON', 'CURSOR_2X_MAGNIFY', + 'CURSOR_2X_MAGNIFY_IS_DISABLE', 'CURSOR_2X_MAGNIFY_IS_ENABLE', + 'CURSOR_COLOR_24BIT_1BIT_AND', + 'CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT', + 'CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT', + 'CURSOR_COLOR_64BIT_FP_PREMULT', + 'CURSOR_COLOR_64BIT_FP_UNPREMULT', 'CURSOR_ENABLE', + 'CURSOR_IN_GUEST_PHYSICAL_ADDRESS', + 'CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS', 'CURSOR_IS_DISABLE', + 'CURSOR_IS_ENABLE', 'CURSOR_IS_NOT_SNOOP', 'CURSOR_IS_SNOOP', + 'CURSOR_LINES_PER_CHUNK', 'CURSOR_LINE_PER_CHUNK_1', + 'CURSOR_LINE_PER_CHUNK_16', 'CURSOR_LINE_PER_CHUNK_2', + 'CURSOR_LINE_PER_CHUNK_4', 'CURSOR_LINE_PER_CHUNK_8', + 'CURSOR_MODE', 'CURSOR_MONO_2BIT', + 'CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY', + 'CURSOR_PERFMON_LATENCY_MEASURE_EN', + 'CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED', + 'CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED', + 'CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY', + 'CURSOR_PERFMON_LATENCY_MEASURE_SEL', 'CURSOR_PITCH', + 'CURSOR_PITCH_128_PIXELS', 'CURSOR_PITCH_256_PIXELS', + 'CURSOR_PITCH_64_PIXELS', 'CURSOR_REQUEST_EARLY', + 'CURSOR_REQUEST_NORMALLY', 'CURSOR_REQ_MODE', 'CURSOR_SNOOP', + 'CURSOR_STEREO_EN', 'CURSOR_STEREO_IS_DISABLED', + 'CURSOR_STEREO_IS_ENABLED', 'CURSOR_SURFACE_IS_NOT_TMZ', + 'CURSOR_SURFACE_IS_TMZ', 'CURSOR_SURFACE_TMZ', 'CURSOR_SYSTEM', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0', + 'CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1', + 'CUR_CLAMP_DIS', 'CUR_CLAMP_EN', 'CUR_DIS', + 'CUR_DYNAMIC_EXPANSION', 'CUR_EN', 'CUR_ENABLE', + 'CUR_EXPAND_MODE', 'CUR_FP_NO_ROM', 'CUR_FP_USE_ROM', + 'CUR_INV_CLAMP', 'CUR_MODE', 'CUR_NOT_PENDING', 'CUR_PENDING', + 'CUR_ROM_EN', 'CUR_YES_PENDING', 'CUR_ZERO_EXPANSION', + 'CbYCrY10101010_422_PACKED', 'CbYCrY12121212_422_PACKED', + 'CbYCrY8888_422_PACKED', 'CmaskCode', 'CombFunc', 'CompareFrag', + 'ConservativeZExport', 'CovToShaderSel', 'CrYCbA1010102', + 'CrYCbA16161616_10LSB', 'CrYCbA16161616_10MSB', + 'CrYCbA16161616_12LSB', 'CrYCbA16161616_12MSB', 'CrYCbA8888', + 'CrYCbY10101010_422_PACKED', 'CrYCbY12121212_422_PACKED', + 'CrYCbY8888_422_PACKED', 'DAC_MUX_SELECT', 'DAC_MUX_SELECT_DACA', + 'DAC_MUX_SELECT_DACB', 'DB_BREAK_BATCH_EVENT', 'DB_CACHE_FLUSH', + 'DB_CACHE_FLUSH_AND_INV', 'DB_CACHE_FLUSH_AND_INV_EVENT', + 'DB_CACHE_FLUSH_AND_INV_TS_EVENT', 'DB_CACHE_FLUSH_TS', + 'DB_CONTEXT_DONE_EVENT', 'DB_CONTEXT_SUSPEND_EVENT', + 'DB_FLUSH_AND_INV_DB_DATA_TS', 'DB_FLUSH_AND_INV_DB_META', + 'DB_INVOKE_CHANGE_EVENT', 'DB_PERF_SEL_CB_DB_rdreq_prt_sends', + 'DB_PERF_SEL_CB_DB_rdreq_sends', + 'DB_PERF_SEL_CB_DB_wrreq_prt_sends', + 'DB_PERF_SEL_CB_DB_wrreq_sends', + 'DB_PERF_SEL_DB_CB_context_dones', 'DB_PERF_SEL_DB_CB_eop_dones', + 'DB_PERF_SEL_DB_CB_lquad_busy', + 'DB_PERF_SEL_DB_CB_lquad_double_format', + 'DB_PERF_SEL_DB_CB_lquad_export_quads', + 'DB_PERF_SEL_DB_CB_lquad_fast_format', + 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix', + 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix', + 'DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix', + 'DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix', + 'DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending', + 'DB_PERF_SEL_DB_CB_lquad_quads', + 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1', + 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2', + 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1', + 'DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2', + 'DB_PERF_SEL_DB_CB_lquad_sends', + 'DB_PERF_SEL_DB_CB_lquad_slow_format', + 'DB_PERF_SEL_DB_CB_lquad_stalls', 'DB_PERF_SEL_DB_CB_rdret_ack', + 'DB_PERF_SEL_DB_CB_rdret_nack', 'DB_PERF_SEL_DB_CB_tile_busy', + 'DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS', + 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA', + 'DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS', + 'DB_PERF_SEL_DB_CB_tile_sends', 'DB_PERF_SEL_DB_CB_tile_stalls', + 'DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event', + 'DB_PERF_SEL_DB_CB_wrret_ack', 'DB_PERF_SEL_DB_CB_wrret_nack', + 'DB_PERF_SEL_DB_SC_c_tile_rate', 'DB_PERF_SEL_DB_SC_quad_busy', + 'DB_PERF_SEL_DB_SC_quad_double_quad', + 'DB_PERF_SEL_DB_SC_quad_lit_noz_quad', + 'DB_PERF_SEL_DB_SC_quad_lit_quad', + 'DB_PERF_SEL_DB_SC_quad_noz_tiles', + 'DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels', + 'DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels', + 'DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel', + 'DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels', + 'DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels', + 'DB_PERF_SEL_DB_SC_quad_sends', 'DB_PERF_SEL_DB_SC_quad_stalls', + 'DB_PERF_SEL_DB_SC_quad_tiles', 'DB_PERF_SEL_DB_SC_s_tile_rate', + 'DB_PERF_SEL_DB_SC_tile_busy', 'DB_PERF_SEL_DB_SC_tile_culled', + 'DB_PERF_SEL_DB_SC_tile_df_stalls', + 'DB_PERF_SEL_DB_SC_tile_fast_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_stencil_ops', + 'DB_PERF_SEL_DB_SC_tile_fast_z_ops', + 'DB_PERF_SEL_DB_SC_tile_hier_kill', + 'DB_PERF_SEL_DB_SC_tile_no_ops', 'DB_PERF_SEL_DB_SC_tile_sends', + 'DB_PERF_SEL_DB_SC_tile_ssaa_kill', + 'DB_PERF_SEL_DB_SC_tile_stalls', + 'DB_PERF_SEL_DB_SC_tile_tile_rate', + 'DB_PERF_SEL_DB_SC_tile_tiles', 'DB_PERF_SEL_DB_SC_z_tile_rate', + 'DB_PERF_SEL_Depth_Tile_Cache_alloc_stall', + 'DB_PERF_SEL_Depth_Tile_Cache_busy', + 'DB_PERF_SEL_Depth_Tile_Cache_data_frees', + 'DB_PERF_SEL_Depth_Tile_Cache_detailed_noop', + 'DB_PERF_SEL_Depth_Tile_Cache_dtile_locked', + 'DB_PERF_SEL_Depth_Tile_Cache_event', + 'DB_PERF_SEL_Depth_Tile_Cache_flushes', + 'DB_PERF_SEL_Depth_Tile_Cache_hits', + 'DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Depth_Tile_Cache_misses', + 'DB_PERF_SEL_Depth_Tile_Cache_noop_tile', + 'DB_PERF_SEL_Depth_Tile_Cache_sends', + 'DB_PERF_SEL_Depth_Tile_Cache_starves', + 'DB_PERF_SEL_Depth_Tile_Cache_tile_frees', + 'DB_PERF_SEL_MI_psd_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_quad_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_tile_req_wrack_counter_stall', + 'DB_PERF_SEL_MI_zpc_req_wrack_counter_stall', + 'DB_PERF_SEL_Op_Pipe_Busy', 'DB_PERF_SEL_Op_Pipe_MC_Read_stall', + 'DB_PERF_SEL_Op_Pipe_Postz_Busy', 'DB_PERF_SEL_Op_Pipe_Prez_Busy', + 'DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits', + 'DB_PERF_SEL_Plane_Cache_flushes', + 'DB_PERF_SEL_Plane_Cache_frees', 'DB_PERF_SEL_Plane_Cache_hits', + 'DB_PERF_SEL_Plane_Cache_misses', + 'DB_PERF_SEL_Plane_Cache_starves', + 'DB_PERF_SEL_PostZ_Samples_failing_DB', + 'DB_PERF_SEL_PostZ_Samples_failing_S', + 'DB_PERF_SEL_PostZ_Samples_failing_Z', + 'DB_PERF_SEL_PostZ_Samples_passing_Z', + 'DB_PERF_SEL_PreZ_Samples_failing_DB', + 'DB_PERF_SEL_PreZ_Samples_failing_S', + 'DB_PERF_SEL_PreZ_Samples_failing_Z', + 'DB_PERF_SEL_PreZ_Samples_passing_Z', + 'DB_PERF_SEL_RMI_rd_s_32byte_req', + 'DB_PERF_SEL_RMI_rd_s_32byte_ret', + 'DB_PERF_SEL_RMI_rd_tile_32byte_req', + 'DB_PERF_SEL_RMI_rd_tile_32byte_ret', + 'DB_PERF_SEL_RMI_rd_z_32byte_req', + 'DB_PERF_SEL_RMI_rd_z_32byte_ret', + 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack', + 'DB_PERF_SEL_RMI_wr_psdzpc_32byte_req', + 'DB_PERF_SEL_RMI_wr_s_32byte_ack', + 'DB_PERF_SEL_RMI_wr_s_32byte_req', + 'DB_PERF_SEL_RMI_wr_tile_32byte_ack', + 'DB_PERF_SEL_RMI_wr_tile_32byte_req', + 'DB_PERF_SEL_RMI_wr_z_32byte_ack', + 'DB_PERF_SEL_RMI_wr_z_32byte_req', 'DB_PERF_SEL_SC_DB_quad_busy', + 'DB_PERF_SEL_SC_DB_quad_killed_tiles', + 'DB_PERF_SEL_SC_DB_quad_pixels', 'DB_PERF_SEL_SC_DB_quad_quads', + 'DB_PERF_SEL_SC_DB_quad_quads_pipe0', + 'DB_PERF_SEL_SC_DB_quad_quads_pipe1', + 'DB_PERF_SEL_SC_DB_quad_sends', 'DB_PERF_SEL_SC_DB_quad_squads', + 'DB_PERF_SEL_SC_DB_quad_tiles', 'DB_PERF_SEL_SC_DB_tile_backface', + 'DB_PERF_SEL_SC_DB_tile_busy', 'DB_PERF_SEL_SC_DB_tile_covered', + 'DB_PERF_SEL_SC_DB_tile_events', 'DB_PERF_SEL_SC_DB_tile_sends', + 'DB_PERF_SEL_SC_DB_tile_stalls', 'DB_PERF_SEL_SC_DB_tile_tiles', + 'DB_PERF_SEL_SC_DB_tile_tiles_pipe0', + 'DB_PERF_SEL_SC_DB_tile_tiles_pipe1', + 'DB_PERF_SEL_SH_quads_outstanding_sum', + 'DB_PERF_SEL_SX_DB_quad_all_pixels_enabled', + 'DB_PERF_SEL_SX_DB_quad_all_pixels_killed', + 'DB_PERF_SEL_SX_DB_quad_busy', + 'DB_PERF_SEL_SX_DB_quad_double_format', + 'DB_PERF_SEL_SX_DB_quad_export_quads', + 'DB_PERF_SEL_SX_DB_quad_exports', + 'DB_PERF_SEL_SX_DB_quad_fast_format', + 'DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read', + 'DB_PERF_SEL_SX_DB_quad_pixels', 'DB_PERF_SEL_SX_DB_quad_quads', + 'DB_PERF_SEL_SX_DB_quad_sends', + 'DB_PERF_SEL_SX_DB_quad_slow_format', + 'DB_PERF_SEL_SX_DB_quad_stalls', + 'DB_PERF_SEL_Stencil_Cache_flushes', + 'DB_PERF_SEL_Stencil_Cache_frees', + 'DB_PERF_SEL_Stencil_Cache_hits', + 'DB_PERF_SEL_Stencil_Cache_misses', + 'DB_PERF_SEL_Stencil_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_flushes', 'DB_PERF_SEL_Tile_Cache_hits', + 'DB_PERF_SEL_Tile_Cache_mem_return_starve', + 'DB_PERF_SEL_Tile_Cache_misses', 'DB_PERF_SEL_Tile_Cache_starves', + 'DB_PERF_SEL_Tile_Cache_surface_stall', + 'DB_PERF_SEL_Z_Cache_frees', 'DB_PERF_SEL_Z_Cache_pmask_flushes', + 'DB_PERF_SEL_Z_Cache_pmask_hits', + 'DB_PERF_SEL_Z_Cache_pmask_misses', + 'DB_PERF_SEL_Z_Cache_pmask_starves', + 'DB_PERF_SEL_Z_Cache_separate_Z_flushes', + 'DB_PERF_SEL_Z_Cache_separate_Z_hits', + 'DB_PERF_SEL_Z_Cache_separate_Z_misses', + 'DB_PERF_SEL_Z_Cache_separate_Z_starves', + 'DB_PERF_SEL_clock_main_active', + 'DB_PERF_SEL_clock_mem_export_active', + 'DB_PERF_SEL_clock_reg_active', + 'DB_PERF_SEL_cs_events_pws_enable', + 'DB_PERF_SEL_depth_bounds_tile_culled', 'DB_PERF_SEL_di_dt_stall', + 'DB_PERF_SEL_dk_squad_busy', 'DB_PERF_SEL_dk_squad_sends', + 'DB_PERF_SEL_dk_squad_stalls', 'DB_PERF_SEL_dk_tile_busy', + 'DB_PERF_SEL_dk_tile_quad_starves', 'DB_PERF_SEL_dk_tile_sends', + 'DB_PERF_SEL_dk_tile_stalls', 'DB_PERF_SEL_dkg_tile_rate_tile', + 'DB_PERF_SEL_dtt_sm_clash_stall', 'DB_PERF_SEL_dtt_sm_miss_stall', + 'DB_PERF_SEL_dtt_sm_slot_stall', + 'DB_PERF_SEL_earlyZ_waiting_for_postZ_done', + 'DB_PERF_SEL_esr_eot_fwd_busy', 'DB_PERF_SEL_esr_eot_fwd_forward', + 'DB_PERF_SEL_esr_eot_fwd_holding_squad', + 'DB_PERF_SEL_esr_ps_lqf_busy', 'DB_PERF_SEL_esr_ps_lqf_stall', + 'DB_PERF_SEL_esr_ps_out_busy', 'DB_PERF_SEL_esr_ps_src_in_sends', + 'DB_PERF_SEL_esr_ps_src_in_squads', + 'DB_PERF_SEL_esr_ps_src_in_squads_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_stall', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate', + 'DB_PERF_SEL_esr_ps_src_out_stall', 'DB_PERF_SEL_esr_ps_vic_busy', + 'DB_PERF_SEL_esr_ps_vic_stall', + 'DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut', + 'DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut', + 'DB_PERF_SEL_esr_psi_vic_tile_rate', + 'DB_PERF_SEL_esr_sqq_zi_busy', 'DB_PERF_SEL_esr_sqq_zi_stall', + 'DB_PERF_SEL_esr_vic_footprint_match_1x2', + 'DB_PERF_SEL_esr_vic_footprint_match_2x1', + 'DB_PERF_SEL_esr_vic_footprint_match_2x2', + 'DB_PERF_SEL_esr_vic_sqq_busy', 'DB_PERF_SEL_esr_vic_sqq_stall', + 'DB_PERF_SEL_etr_out_busy', 'DB_PERF_SEL_etr_out_cb_tile_stall', + 'DB_PERF_SEL_etr_out_esr_stall', + 'DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall', + 'DB_PERF_SEL_etr_out_send', 'DB_PERF_SEL_flush_10plane', + 'DB_PERF_SEL_flush_11plane', 'DB_PERF_SEL_flush_12plane', + 'DB_PERF_SEL_flush_13plane', 'DB_PERF_SEL_flush_14plane', + 'DB_PERF_SEL_flush_15plane', 'DB_PERF_SEL_flush_16plane', + 'DB_PERF_SEL_flush_1plane', 'DB_PERF_SEL_flush_2plane', + 'DB_PERF_SEL_flush_3plane', 'DB_PERF_SEL_flush_4plane', + 'DB_PERF_SEL_flush_5plane', 'DB_PERF_SEL_flush_6plane', + 'DB_PERF_SEL_flush_7plane', 'DB_PERF_SEL_flush_8plane', + 'DB_PERF_SEL_flush_9plane', 'DB_PERF_SEL_flush_compressed', + 'DB_PERF_SEL_flush_compressed_stencil', + 'DB_PERF_SEL_flush_expanded_stencil', + 'DB_PERF_SEL_flush_expanded_z', 'DB_PERF_SEL_flush_plane_le4', + 'DB_PERF_SEL_flush_single_stencil', + 'DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1', + 'DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1', + 'DB_PERF_SEL_his_tile_culled', 'DB_PERF_SEL_hiz_tc_read_starved', + 'DB_PERF_SEL_hiz_tc_write_stall', 'DB_PERF_SEL_hiz_tile_culled', + 'DB_PERF_SEL_mi_quad_rd_outstanding_sum', + 'DB_PERF_SEL_mi_quad_wr_outstanding_sum', + 'DB_PERF_SEL_mi_rdreq_busy', 'DB_PERF_SEL_mi_rdreq_stall', + 'DB_PERF_SEL_mi_tile_rd_outstanding_sum', + 'DB_PERF_SEL_mi_tile_wr_outstanding_sum', + 'DB_PERF_SEL_mi_wrreq_busy', 'DB_PERF_SEL_mi_wrreq_stall', + 'DB_PERF_SEL_noz_waiting_for_postz_done', + 'DB_PERF_SEL_planes_flushed', + 'DB_PERF_SEL_postz_ps_invoked_pixel_cnt', + 'DB_PERF_SEL_postzl_full_launch', + 'DB_PERF_SEL_postzl_partial_launch', + 'DB_PERF_SEL_postzl_partial_waiting', + 'DB_PERF_SEL_postzl_se_busy', 'DB_PERF_SEL_postzl_se_stall', + 'DB_PERF_SEL_postzl_sq_pt_busy', 'DB_PERF_SEL_postzl_sq_pt_stall', + 'DB_PERF_SEL_postzl_src_in_sends', + 'DB_PERF_SEL_postzl_src_in_squads', + 'DB_PERF_SEL_postzl_src_in_squads_unrolled', + 'DB_PERF_SEL_postzl_src_in_stall', + 'DB_PERF_SEL_postzl_src_in_tile_rate', + 'DB_PERF_SEL_postzl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_postzl_src_out_stall', + 'DB_PERF_SEL_postzl_tile_init_stall', + 'DB_PERF_SEL_postzl_tile_mem_stall', + 'DB_PERF_SEL_prez_ps_invoked_pixel_cnt', + 'DB_PERF_SEL_prezl_src_in_sends', + 'DB_PERF_SEL_prezl_src_in_squads', + 'DB_PERF_SEL_prezl_src_in_squads_unrolled', + 'DB_PERF_SEL_prezl_src_in_stall', + 'DB_PERF_SEL_prezl_src_in_tile_rate', + 'DB_PERF_SEL_prezl_src_in_tile_rate_unrolled', + 'DB_PERF_SEL_prezl_src_out_stall', + 'DB_PERF_SEL_prezl_tile_init_stall', + 'DB_PERF_SEL_prezl_tile_mem_stall', + 'DB_PERF_SEL_ps_events_pws_enable', 'DB_PERF_SEL_qc_busy', + 'DB_PERF_SEL_qc_conflicts', 'DB_PERF_SEL_qc_full_stall', + 'DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ', + 'DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ', 'DB_PERF_SEL_qc_xfc', + 'DB_PERF_SEL_quad_rd_32byte_reqs', 'DB_PERF_SEL_quad_rd_busy', + 'DB_PERF_SEL_quad_rd_mi_stall', + 'DB_PERF_SEL_quad_rd_mi_stall_unc', 'DB_PERF_SEL_quad_rd_panic', + 'DB_PERF_SEL_quad_rd_rw_collision', 'DB_PERF_SEL_quad_rd_sends', + 'DB_PERF_SEL_quad_rd_sends_unc', 'DB_PERF_SEL_quad_rd_tag_stall', + 'DB_PERF_SEL_quad_rdret_busy', 'DB_PERF_SEL_quad_rdret_sends', + 'DB_PERF_SEL_quad_wr_acks', 'DB_PERF_SEL_quad_wr_busy', + 'DB_PERF_SEL_quad_wr_coherency_stall', + 'DB_PERF_SEL_quad_wr_mi_stall', 'DB_PERF_SEL_quad_wr_sends', + 'DB_PERF_SEL_reZ_waiting_for_postZ_done', + 'DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop', + 'DB_PERF_SEL_sc_kick_end', 'DB_PERF_SEL_sc_kick_start', + 'DB_PERF_SEL_tcp_dispatcher_flushes', + 'DB_PERF_SEL_tcp_dispatcher_reads', + 'DB_PERF_SEL_tcp_prefetcher_flushes', + 'DB_PERF_SEL_tcp_prefetcher_reads', + 'DB_PERF_SEL_tcp_preloader_flushes', + 'DB_PERF_SEL_tcp_preloader_reads', 'DB_PERF_SEL_tile_rd_sends', + 'DB_PERF_SEL_tile_wr_acks', 'DB_PERF_SEL_tile_wr_sends', + 'DB_PERF_SEL_tiles_compressed_to_decompressed', + 'DB_PERF_SEL_tiles_decomp_on_expclear', + 'DB_PERF_SEL_tiles_s_clear_on_expclear', + 'DB_PERF_SEL_tiles_stencil_fully_summarized', + 'DB_PERF_SEL_tiles_z_clear_on_expclear', + 'DB_PERF_SEL_tiles_z_fully_summarized', 'DB_PERF_SEL_tl_busy', + 'DB_PERF_SEL_tl_dtc_read_starved', 'DB_PERF_SEL_tl_events', + 'DB_PERF_SEL_tl_expand_squads', + 'DB_PERF_SEL_tl_flush_expand_squads', + 'DB_PERF_SEL_tl_in_fast_z_stall', + 'DB_PERF_SEL_tl_in_single_stencil_expand_stall', + 'DB_PERF_SEL_tl_in_xfc', 'DB_PERF_SEL_tl_out_squads', + 'DB_PERF_SEL_tl_out_xfc', 'DB_PERF_SEL_tl_postZ_noop_squads', + 'DB_PERF_SEL_tl_postZ_squads', 'DB_PERF_SEL_tl_preZ_noop_squads', + 'DB_PERF_SEL_tl_preZ_squads', + 'DB_PERF_SEL_tl_stencil_locked_stall', + 'DB_PERF_SEL_tl_stencil_stall', 'DB_PERF_SEL_tl_summarize_squads', + 'DB_PERF_SEL_tl_tile_ops', 'DB_PERF_SEL_tl_z_decompress_stall', + 'DB_PERF_SEL_tl_z_fetch_stall', + 'DB_PERF_SEL_ts_events_pws_enable', + 'DB_PERF_SEL_ts_tc_update_stall', + 'DB_PERF_SEL_tsc_insert_summarize_stall', + 'DB_PERF_SEL_unmapped_z_tile_culled', + 'DB_PERF_SEL_zf_plane_multicycle', 'DB_VPORT_CHANGED_EVENT', + 'DCCG_AUDIO_DTO0_SOURCE_SEL', 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3', + 'DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED', + 'DCCG_AUDIO_DTO2_SOURCE_SEL', 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0', + 'DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2', 'DCCG_AUDIO_DTO_SEL', + 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO0', 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO1', + 'DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK', + 'DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO', + 'DCCG_AUDIO_DTO_USE_128FBR_FOR_DP', + 'DCCG_AUDIO_DTO_USE_512FBR_DTO', + 'DCCG_AUDIO_DTO_USE_512FBR_FOR_DP', 'DCCG_DBG_BLOCK_SEL', + 'DCCG_DBG_BLOCK_SEL_DCCG', 'DCCG_DBG_BLOCK_SEL_PMON', + 'DCCG_DBG_BLOCK_SEL_PMON2', 'DCCG_DBG_EN', 'DCCG_DBG_EN_DISABLE', + 'DCCG_DBG_EN_ENABLE', 'DCCG_DEEP_COLOR_CNTL', + 'DCCG_DEEP_COLOR_DTO_2_1_RATIO', 'DCCG_DEEP_COLOR_DTO_3_2_RATIO', + 'DCCG_DEEP_COLOR_DTO_5_4_RATIO', 'DCCG_DEEP_COLOR_DTO_DISABLE', + 'DCCG_FIFO_ERRDET_OVR_DISABLE', 'DCCG_FIFO_ERRDET_OVR_EN', + 'DCCG_FIFO_ERRDET_OVR_ENABLE', 'DCCG_FIFO_ERRDET_RESET', + 'DCCG_FIFO_ERRDET_RESET_FORCE', 'DCCG_FIFO_ERRDET_RESET_NOOP', + 'DCCG_FIFO_ERRDET_STATE', 'DCCG_FIFO_ERRDET_STATE_CALIBRATION', + 'DCCG_FIFO_ERRDET_STATE_DETECTION', 'DCCG_PERF_MODE_HSYNC', + 'DCCG_PERF_MODE_HSYNC_NOOP', 'DCCG_PERF_MODE_HSYNC_START', + 'DCCG_PERF_MODE_VSYNC', 'DCCG_PERF_MODE_VSYNC_NOOP', + 'DCCG_PERF_MODE_VSYNC_START', 'DCCG_PERF_OTG_SELECT', + 'DCCG_PERF_RUN', 'DCCG_PERF_RUN_NOOP', 'DCCG_PERF_RUN_START', + 'DCCG_PERF_SEL_OTG0', 'DCCG_PERF_SEL_OTG1', 'DCCG_PERF_SEL_OTG2', + 'DCCG_PERF_SEL_OTG3', 'DCCG_PERF_SEL_RESERVED', + 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2', + 'DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE', + 'DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE', + 'DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE', + 'DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP', + 'DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP', + 'DCHUBBUB_MEM_POWER_MODE_OFF', + 'DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN', 'DCHUBBUB_MEM_PWR_DIS_MODE', + 'DCHUBBUB_MEM_PWR_MODE', 'DCIOCHIP_AUX_ALL_PWR_OK', + 'DCIOCHIP_AUX_ALL_PWR_OK_0', 'DCIOCHIP_AUX_ALL_PWR_OK_1', + 'DCIOCHIP_AUX_CSEL0P9', 'DCIOCHIP_AUX_CSEL1P1', + 'DCIOCHIP_AUX_CSEL_DEC0P9', 'DCIOCHIP_AUX_CSEL_DEC1P0', + 'DCIOCHIP_AUX_CSEL_INC1P0', 'DCIOCHIP_AUX_CSEL_INC1P1', + 'DCIOCHIP_AUX_FALLSLEWSEL', 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH0', + 'DCIOCHIP_AUX_FALLSLEWSEL_HIGH1', 'DCIOCHIP_AUX_FALLSLEWSEL_LOW', + 'DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH', 'DCIOCHIP_AUX_HYS_TUNE', + 'DCIOCHIP_AUX_HYS_TUNE_0', 'DCIOCHIP_AUX_HYS_TUNE_1', + 'DCIOCHIP_AUX_HYS_TUNE_2', 'DCIOCHIP_AUX_HYS_TUNE_3', + 'DCIOCHIP_AUX_RECEIVER_SEL', 'DCIOCHIP_AUX_RECEIVER_SEL_0', + 'DCIOCHIP_AUX_RECEIVER_SEL_1', 'DCIOCHIP_AUX_RECEIVER_SEL_2', + 'DCIOCHIP_AUX_RECEIVER_SEL_3', 'DCIOCHIP_AUX_RSEL0P9', + 'DCIOCHIP_AUX_RSEL1P1', 'DCIOCHIP_AUX_RSEL_DEC0P9', + 'DCIOCHIP_AUX_RSEL_DEC1P0', 'DCIOCHIP_AUX_RSEL_INC1P0', + 'DCIOCHIP_AUX_RSEL_INC1P1', 'DCIOCHIP_AUX_SPIKESEL', + 'DCIOCHIP_AUX_SPIKESEL_10NS', 'DCIOCHIP_AUX_SPIKESEL_50NS', + 'DCIOCHIP_AUX_VOD_TUNE', 'DCIOCHIP_AUX_VOD_TUNE_0', + 'DCIOCHIP_AUX_VOD_TUNE_1', 'DCIOCHIP_AUX_VOD_TUNE_2', + 'DCIOCHIP_AUX_VOD_TUNE_3', 'DCIOCHIP_GPIO_MASK_EN', + 'DCIOCHIP_GPIO_MASK_EN_HARDWARE', + 'DCIOCHIP_GPIO_MASK_EN_SOFTWARE', 'DCIOCHIP_HPD_SEL', + 'DCIOCHIP_HPD_SEL_ASYNC', 'DCIOCHIP_HPD_SEL_CLOCKED', + 'DCIOCHIP_I2C_COMPSEL', 'DCIOCHIP_I2C_FALLSLEWSEL', + 'DCIOCHIP_I2C_FALLSLEWSEL_00', 'DCIOCHIP_I2C_FALLSLEWSEL_01', + 'DCIOCHIP_I2C_FALLSLEWSEL_10', 'DCIOCHIP_I2C_FALLSLEWSEL_11', + 'DCIOCHIP_I2C_RECEIVER_SEL', 'DCIOCHIP_I2C_RECEIVER_SEL_0', + 'DCIOCHIP_I2C_RECEIVER_SEL_1', 'DCIOCHIP_I2C_RECEIVER_SEL_2', + 'DCIOCHIP_I2C_RECEIVER_SEL_3', 'DCIOCHIP_I2C_REC_COMPARATOR', + 'DCIOCHIP_I2C_REC_SCHMIT', 'DCIOCHIP_I2C_VPH_1V2_EN', + 'DCIOCHIP_I2C_VPH_1V2_EN_0', 'DCIOCHIP_I2C_VPH_1V2_EN_1', + 'DCIOCHIP_INVERT', 'DCIOCHIP_MASK', 'DCIOCHIP_MASK_DISABLE', + 'DCIOCHIP_MASK_ENABLE', 'DCIOCHIP_PAD_MODE', + 'DCIOCHIP_PAD_MODE_DDC', 'DCIOCHIP_PAD_MODE_DP', 'DCIOCHIP_PD_EN', + 'DCIOCHIP_PD_EN_ALLOW', 'DCIOCHIP_PD_EN_NOTALLOW', + 'DCIOCHIP_POL_INVERT', 'DCIOCHIP_POL_NON_INVERT', + 'DCIOCHIP_REF_27_SRC_SEL', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS', + 'DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5', + 'DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6', + 'DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL', + 'DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS', + 'DCIO_DBG_ASYNC_4BIT_SEL', 'DCIO_DBG_ASYNC_4BIT_SEL_11TO8', + 'DCIO_DBG_ASYNC_4BIT_SEL_15TO12', + 'DCIO_DBG_ASYNC_4BIT_SEL_19TO16', + 'DCIO_DBG_ASYNC_4BIT_SEL_23TO20', + 'DCIO_DBG_ASYNC_4BIT_SEL_27TO24', + 'DCIO_DBG_ASYNC_4BIT_SEL_31TO28', 'DCIO_DBG_ASYNC_4BIT_SEL_3TO0', + 'DCIO_DBG_ASYNC_4BIT_SEL_7TO4', 'DCIO_DBG_ASYNC_BLOCK_SEL', + 'DCIO_DBG_ASYNC_BLOCK_SEL_DCCG', 'DCIO_DBG_ASYNC_BLOCK_SEL_DCIO', + 'DCIO_DBG_ASYNC_BLOCK_SEL_DIO', + 'DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE', 'DCIO_DCRXPHY_SOFT_RESET', + 'DCIO_DCRXPHY_SOFT_RESET_ASSERT', + 'DCIO_DCRXPHY_SOFT_RESET_DEASSERT', 'DCIO_DC_GENERICA_SEL', + 'DCIO_DC_GENERICB_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL', + 'DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL', + 'DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE', + 'DCIO_DC_GPU_TIMER_READ_SELECT', + 'DCIO_DC_GPU_TIMER_START_POSITION', + 'DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL', + 'DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL', + 'DCIO_DIO_EXT_VSYNC_MASK', 'DCIO_DIO_OTG_EXT_VSYNC_MUX', + 'DCIO_DISPCLK_R_DCIO_GATE_DISABLE', + 'DCIO_DISPCLK_R_DCIO_GATE_ENABLE', 'DCIO_DPCS_INTERRUPT_DISABLE', + 'DCIO_DPCS_INTERRUPT_ENABLE', 'DCIO_DPCS_INTERRUPT_MASK', + 'DCIO_DPCS_INTERRUPT_TYPE', + 'DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED', + 'DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED', + 'DCIO_DPRX_LOOPBACK_ENABLE_LOOP', + 'DCIO_DPRX_LOOPBACK_ENABLE_NORMAL', 'DCIO_DSYNC_SOFT_RESET', + 'DCIO_DSYNC_SOFT_RESET_ASSERT', 'DCIO_DSYNC_SOFT_RESET_DEASSERT', + 'DCIO_EXT_VSYNC_MASK_NONE', 'DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE', + 'DCIO_EXT_VSYNC_MASK_PIPE0', 'DCIO_EXT_VSYNC_MASK_PIPE1', + 'DCIO_EXT_VSYNC_MASK_PIPE2', 'DCIO_EXT_VSYNC_MASK_PIPE3', + 'DCIO_EXT_VSYNC_MASK_PIPE4', 'DCIO_EXT_VSYNC_MASK_PIPE5', + 'DCIO_EXT_VSYNC_MUX_GENERICB', 'DCIO_EXT_VSYNC_MUX_OTG0', + 'DCIO_EXT_VSYNC_MUX_OTG1', 'DCIO_EXT_VSYNC_MUX_OTG2', + 'DCIO_EXT_VSYNC_MUX_OTG3', 'DCIO_EXT_VSYNC_MUX_OTG4', + 'DCIO_EXT_VSYNC_MUX_OTG5', 'DCIO_EXT_VSYNC_MUX_SWAPLOCKB', + 'DCIO_GENERICA_SEL_GENERICA_DCCG', 'DCIO_GENERICA_SEL_STEREOSYNC', + 'DCIO_GENERICA_SEL_SYNCEN', 'DCIO_GENERICB_SEL_GENERICB_DCCG', + 'DCIO_GENERICB_SEL_STEREOSYNC', 'DCIO_GENERICB_SEL_SYNCEN', + 'DCIO_GENLK_CLK_GSL_MASK', 'DCIO_GENLK_CLK_GSL_MASK_NO', + 'DCIO_GENLK_CLK_GSL_MASK_STEREO', + 'DCIO_GENLK_CLK_GSL_MASK_TIMING', + 'DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1', + 'DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2', + 'DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3', + 'DCIO_GENLK_VSYNC_GSL_MASK', 'DCIO_GENLK_VSYNC_GSL_MASK_NO', + 'DCIO_GENLK_VSYNC_GSL_MASK_STEREO', + 'DCIO_GENLK_VSYNC_GSL_MASK_TIMING', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM', + 'DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE', + 'DCIO_GPU_TIMER_START_0_END_27', 'DCIO_GPU_TIMER_START_10_END_37', + 'DCIO_GPU_TIMER_START_1_END_28', 'DCIO_GPU_TIMER_START_2_END_29', + 'DCIO_GPU_TIMER_START_3_END_30', 'DCIO_GPU_TIMER_START_4_END_31', + 'DCIO_GPU_TIMER_START_6_END_33', 'DCIO_GPU_TIMER_START_8_END_35', + 'DCIO_GSL_SEL', 'DCIO_GSL_SEL_GROUP_0', 'DCIO_GSL_SEL_GROUP_1', + 'DCIO_GSL_SEL_GROUP_2', 'DCIO_HSYNCA_OUTPUT_SEL_DISABLE', + 'DCIO_HSYNCA_OUTPUT_SEL_PPLL1', 'DCIO_HSYNCA_OUTPUT_SEL_PPLL2', + 'DCIO_HSYNCA_OUTPUT_SEL_RESERVED', 'DCIO_PHY_HPO_ENC_SRC_SEL', + 'DCIO_SWAPLOCK_A_GSL_MASK', 'DCIO_SWAPLOCK_A_GSL_MASK_NO', + 'DCIO_SWAPLOCK_A_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_A_GSL_MASK_TIMING', 'DCIO_SWAPLOCK_B_GSL_MASK', + 'DCIO_SWAPLOCK_B_GSL_MASK_NO', 'DCIO_SWAPLOCK_B_GSL_MASK_STEREO', + 'DCIO_SWAPLOCK_B_GSL_MASK_TIMING', 'DCIO_TEST_CLK_SEL_DISPCLK', + 'DCIO_TEST_CLK_SEL_GATED_DISPCLK', 'DCIO_TEST_CLK_SEL_SOCCLK', + 'DCIO_UNIPHYA_FBDIV_CLK', 'DCIO_UNIPHYA_FBDIV_SSC_CLK', + 'DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYA_TEST_REFDIV_CLK', 'DCIO_UNIPHYB_FBDIV_CLK', + 'DCIO_UNIPHYB_FBDIV_SSC_CLK', 'DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYB_TEST_REFDIV_CLK', 'DCIO_UNIPHYC_FBDIV_CLK', + 'DCIO_UNIPHYC_FBDIV_SSC_CLK', 'DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYC_TEST_REFDIV_CLK', 'DCIO_UNIPHYD_FBDIV_CLK', + 'DCIO_UNIPHYD_FBDIV_SSC_CLK', 'DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYD_TEST_REFDIV_CLK', 'DCIO_UNIPHYE_FBDIV_CLK', + 'DCIO_UNIPHYE_FBDIV_SSC_CLK', 'DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYE_TEST_REFDIV_CLK', 'DCIO_UNIPHYF_FBDIV_CLK', + 'DCIO_UNIPHYF_FBDIV_SSC_CLK', 'DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYF_TEST_REFDIV_CLK', 'DCIO_UNIPHYG_FBDIV_CLK', + 'DCIO_UNIPHYG_FBDIV_SSC_CLK', 'DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2', + 'DCIO_UNIPHYG_TEST_REFDIV_CLK', 'DCIO_UNIPHY_CHANNEL_INVERTED', + 'DCIO_UNIPHY_CHANNEL_NO_INVERSION', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2', + 'DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3', 'DCIO_UNIPHY_IMPCAL_SEL', + 'DCIO_UNIPHY_IMPCAL_SEL_BINARY', + 'DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE', + 'DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT', + 'DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED', + 'DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW', 'DCN_BASE', 'DCN_BASE__INST0_SEG0', 'DCN_BASE__INST0_SEG1', 'DCN_BASE__INST0_SEG2', 'DCN_BASE__INST0_SEG3', 'DCN_BASE__INST0_SEG4', 'DCN_BASE__INST1_SEG0', @@ -13876,24 +63609,125 @@ __all__ = \ 'DCN_BASE__INST5_SEG3', 'DCN_BASE__INST5_SEG4', 'DCN_BASE__INST6_SEG0', 'DCN_BASE__INST6_SEG1', 'DCN_BASE__INST6_SEG2', 'DCN_BASE__INST6_SEG3', - 'DCN_BASE__INST6_SEG4', 'DF_BASE', 'DF_BASE__INST0_SEG0', - 'DF_BASE__INST0_SEG1', 'DF_BASE__INST0_SEG2', - 'DF_BASE__INST0_SEG3', 'DF_BASE__INST0_SEG4', - 'DF_BASE__INST1_SEG0', 'DF_BASE__INST1_SEG1', - 'DF_BASE__INST1_SEG2', 'DF_BASE__INST1_SEG3', - 'DF_BASE__INST1_SEG4', 'DF_BASE__INST2_SEG0', - 'DF_BASE__INST2_SEG1', 'DF_BASE__INST2_SEG2', - 'DF_BASE__INST2_SEG3', 'DF_BASE__INST2_SEG4', - 'DF_BASE__INST3_SEG0', 'DF_BASE__INST3_SEG1', - 'DF_BASE__INST3_SEG2', 'DF_BASE__INST3_SEG3', - 'DF_BASE__INST3_SEG4', 'DF_BASE__INST4_SEG0', - 'DF_BASE__INST4_SEG1', 'DF_BASE__INST4_SEG2', - 'DF_BASE__INST4_SEG3', 'DF_BASE__INST4_SEG4', - 'DF_BASE__INST5_SEG0', 'DF_BASE__INST5_SEG1', - 'DF_BASE__INST5_SEG2', 'DF_BASE__INST5_SEG3', - 'DF_BASE__INST5_SEG4', 'DF_BASE__INST6_SEG0', - 'DF_BASE__INST6_SEG1', 'DF_BASE__INST6_SEG2', - 'DF_BASE__INST6_SEG3', 'DF_BASE__INST6_SEG4', 'DIO_BASE', + 'DCN_BASE__INST6_SEG4', 'DC_DMCUB_INT_TYPE', + 'DC_DMCUB_TIMER_WINDOW', 'DC_MEM_GLOBAL_PWR_REQ_DIS', + 'DC_MEM_GLOBAL_PWR_REQ_DISABLE', 'DC_MEM_GLOBAL_PWR_REQ_ENABLE', + 'DC_SMU_INTERRUPT_ENABLE', 'DDID_VMID_CNTL', 'DDID_VMID_PIPE', + 'DEBUG_BUS_SELECT_ABM0', 'DEBUG_BUS_SELECT_ABM1', + 'DEBUG_BUS_SELECT_ABM2', 'DEBUG_BUS_SELECT_ABM3', + 'DEBUG_BUS_SELECT_ABM_RESERVED0', + 'DEBUG_BUS_SELECT_ABM_RESERVED1', 'DEBUG_BUS_SELECT_DPG0', + 'DEBUG_BUS_SELECT_DPG1', 'DEBUG_BUS_SELECT_DPG2', + 'DEBUG_BUS_SELECT_DPG3', 'DEBUG_BUS_SELECT_DPG_RESERVED0', + 'DEBUG_BUS_SELECT_DPG_RESERVED1', 'DEBUG_BUS_SELECT_FMT0', + 'DEBUG_BUS_SELECT_FMT1', 'DEBUG_BUS_SELECT_FMT2', + 'DEBUG_BUS_SELECT_FMT3', 'DEBUG_BUS_SELECT_FMT_RESERVED0', + 'DEBUG_BUS_SELECT_FMT_RESERVED1', 'DEBUG_BUS_SELECT_OPPBUF0', + 'DEBUG_BUS_SELECT_OPPBUF1', 'DEBUG_BUS_SELECT_OPPBUF2', + 'DEBUG_BUS_SELECT_OPPBUF3', 'DEBUG_BUS_SELECT_OPPBUF_RESERVED0', + 'DEBUG_BUS_SELECT_OPPBUF_RESERVED1', 'DEBUG_BUS_SELECT_OPP_PIPE0', + 'DEBUG_BUS_SELECT_OPP_PIPE1', 'DEBUG_BUS_SELECT_OPP_PIPE2', + 'DEBUG_BUS_SELECT_OPP_PIPE3', + 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0', + 'DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1', 'DECERR', + 'DENORM_TRUNCATE', 'DETILE_BUFFER_PACKER_ENABLE', + 'DETILE_BUFFER_PACKER_IS_DISABLE', + 'DETILE_BUFFER_PACKER_IS_ENABLE', 'DFQ_MIN_FREE_ENTRIES', + 'DFQ_MIN_FREE_ENTRIES_0', 'DFQ_MIN_FREE_ENTRIES_1', + 'DFQ_MIN_FREE_ENTRIES_2', 'DFQ_MIN_FREE_ENTRIES_3', + 'DFQ_MIN_FREE_ENTRIES_4', 'DFQ_MIN_FREE_ENTRIES_5', + 'DFQ_MIN_FREE_ENTRIES_6', 'DFQ_MIN_FREE_ENTRIES_7', + 'DFQ_NUM_ENTRIES', 'DFQ_NUM_ENTRIES_0', 'DFQ_NUM_ENTRIES_1', + 'DFQ_NUM_ENTRIES_2', 'DFQ_NUM_ENTRIES_3', 'DFQ_NUM_ENTRIES_4', + 'DFQ_NUM_ENTRIES_5', 'DFQ_NUM_ENTRIES_6', 'DFQ_NUM_ENTRIES_7', + 'DFQ_NUM_ENTRIES_8', 'DFQ_SIZE', 'DFQ_SIZE_0', 'DFQ_SIZE_1', + 'DFQ_SIZE_2', 'DFQ_SIZE_3', 'DFQ_SIZE_4', 'DFQ_SIZE_5', + 'DFQ_SIZE_6', 'DFQ_SIZE_7', 'DFSMFlushEvents', 'DF_BASE', + 'DF_BASE__INST0_SEG0', 'DF_BASE__INST0_SEG1', + 'DF_BASE__INST0_SEG2', 'DF_BASE__INST0_SEG3', + 'DF_BASE__INST0_SEG4', 'DF_BASE__INST1_SEG0', + 'DF_BASE__INST1_SEG1', 'DF_BASE__INST1_SEG2', + 'DF_BASE__INST1_SEG3', 'DF_BASE__INST1_SEG4', + 'DF_BASE__INST2_SEG0', 'DF_BASE__INST2_SEG1', + 'DF_BASE__INST2_SEG2', 'DF_BASE__INST2_SEG3', + 'DF_BASE__INST2_SEG4', 'DF_BASE__INST3_SEG0', + 'DF_BASE__INST3_SEG1', 'DF_BASE__INST3_SEG2', + 'DF_BASE__INST3_SEG3', 'DF_BASE__INST3_SEG4', + 'DF_BASE__INST4_SEG0', 'DF_BASE__INST4_SEG1', + 'DF_BASE__INST4_SEG2', 'DF_BASE__INST4_SEG3', + 'DF_BASE__INST4_SEG4', 'DF_BASE__INST5_SEG0', + 'DF_BASE__INST5_SEG1', 'DF_BASE__INST5_SEG2', + 'DF_BASE__INST5_SEG3', 'DF_BASE__INST5_SEG4', + 'DF_BASE__INST6_SEG0', 'DF_BASE__INST6_SEG1', + 'DF_BASE__INST6_SEG2', 'DF_BASE__INST6_SEG3', + 'DF_BASE__INST6_SEG4', 'DIFFERENT_RGB', 'DIG_10BIT_TEST_PATTERN', + 'DIG_ALL_PIXEL', 'DIG_ALTERNATING_TEST_PATTERN', + 'DIG_BE_CNTL_HPD1', 'DIG_BE_CNTL_HPD2', 'DIG_BE_CNTL_HPD3', + 'DIG_BE_CNTL_HPD4', 'DIG_BE_CNTL_HPD5', 'DIG_BE_CNTL_HPD_SELECT', + 'DIG_BE_CNTL_MODE', 'DIG_BE_CNTL_NO_HPD', 'DIG_BE_DP_MST_MODE', + 'DIG_BE_DP_SST_MODE', 'DIG_BE_RESERVED1', 'DIG_BE_RESERVED2', + 'DIG_BE_RESERVED3', 'DIG_BE_RESERVED4', 'DIG_BE_TMDS_DVI_MODE', + 'DIG_BE_TMDS_HDMI_MODE', 'DIG_DIGITAL_BYPASS_ENABLE', + 'DIG_DIGITAL_BYPASS_OFF', 'DIG_DIGITAL_BYPASS_ON', + 'DIG_DIGITAL_BYPASS_SEL', 'DIG_DIGITAL_BYPASS_SEL_10BPP_LSB', + 'DIG_DIGITAL_BYPASS_SEL_12BPC_LSB', + 'DIG_DIGITAL_BYPASS_SEL_36BPP', + 'DIG_DIGITAL_BYPASS_SEL_48BPP_LSB', + 'DIG_DIGITAL_BYPASS_SEL_48BPP_MSB', + 'DIG_DIGITAL_BYPASS_SEL_ALPHA', 'DIG_DIGITAL_BYPASS_SEL_BYPASS', + 'DIG_EVEN_PIXEL_ONLY', 'DIG_FE_CNTL_SOURCE_SELECT', + 'DIG_FE_CNTL_STEREOSYNC_SELECT', 'DIG_FE_SOURCE_FROM_OTG0', + 'DIG_FE_SOURCE_FROM_OTG1', 'DIG_FE_SOURCE_FROM_OTG2', + 'DIG_FE_SOURCE_FROM_OTG3', 'DIG_FE_SOURCE_RESERVED', + 'DIG_FE_STEREOSYNC_FROM_OTG0', 'DIG_FE_STEREOSYNC_FROM_OTG1', + 'DIG_FE_STEREOSYNC_FROM_OTG2', 'DIG_FE_STEREOSYNC_FROM_OTG3', + 'DIG_FE_STEREOSYNC_RESERVED', 'DIG_FIFO_1_PIX_PER_CYCLE', + 'DIG_FIFO_2_PIX_PER_CYCLE', 'DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL', + 'DIG_FIFO_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL', + 'DIG_FIFO_FORCE_RECOMP_MINMAX', + 'DIG_FIFO_NOT_FORCE_RECAL_AVERAGE', + 'DIG_FIFO_NOT_FORCE_RECOMP_MINMAX', 'DIG_FIFO_NO_ERROR_OCCURRED', + 'DIG_FIFO_OUTPUT_PROCESSING_MODE', 'DIG_FIFO_OVERFLOW_OCCURRED', + 'DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR', 'DIG_FIFO_READ_CLOCK_SRC', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG', + 'DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE', + 'DIG_FIFO_UNDERFLOW_OCCURRED', 'DIG_FIFO_USE_CAL_AVERAGE_LEVEL', + 'DIG_FIFO_USE_OVERWRITE_LEVEL', 'DIG_INPUT_PIXEL_SEL', + 'DIG_IN_DEBUG_MODE', 'DIG_IN_NORMAL_OPERATION', + 'DIG_ODD_PIXEL_ONLY', 'DIG_OUTPUT_CRC_CNTL_LINK_SEL', + 'DIG_OUTPUT_CRC_DATA_SEL', 'DIG_OUTPUT_CRC_FOR_ACTIVEONLY', + 'DIG_OUTPUT_CRC_FOR_AUDIO', 'DIG_OUTPUT_CRC_FOR_FULLFRAME', + 'DIG_OUTPUT_CRC_FOR_VBI', 'DIG_OUTPUT_CRC_ON_LINK0', + 'DIG_OUTPUT_CRC_ON_LINK1', 'DIG_PAIR_PIXELS', + 'DIG_RANDOM_PATTERN_ENABLED', 'DIG_RANDOM_PATTERN_RESETED', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS', + 'DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH', 'DIG_SINGLETON_PIXELS', + 'DIG_SL_PIXEL_GROUPING', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_EN', + 'DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE', + 'DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL', + 'DIG_TEST_PATTERN_NORMAL', 'DIG_TEST_PATTERN_RANDOM', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN', + 'DIG_TEST_PATTERN_RANDOM_PATTERN_RESET', + 'DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN', 'DIG_UPDATE_EYE_SEL_BOTH', + 'DIG_UPDATE_EYE_SEL_LEFT', 'DIG_UPDATE_EYE_SEL_RIGHT', + 'DIG_UPDATE_FIELD_SEL_BOTH', 'DIG_UPDATE_FIELD_SEL_BOTTOM', + 'DIG_UPDATE_FIELD_SEL_RESERVED', 'DIG_UPDATE_FIELD_SEL_TOP', + 'DIOMEM_DISABLE_MEM_PWR_CTRL', 'DIOMEM_DYNAMIC_DEEP_SLEEP_EN', + 'DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE', + 'DIOMEM_DYNAMIC_LIGHT_SLEEP_EN', + 'DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE', + 'DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE', 'DIOMEM_ENABLE_MEM_PWR_CTRL', + 'DIOMEM_FORCE_DEEP_SLEEP_REQUEST', 'DIOMEM_FORCE_LIGHT_SLEEP_REQ', + 'DIOMEM_FORCE_LIGHT_SLEEP_REQUEST', + 'DIOMEM_FORCE_SHUT_DOWN_REQUEST', 'DIOMEM_NO_FORCE_REQ', + 'DIOMEM_NO_FORCE_REQUEST', 'DIOMEM_PWR_DIS_CTRL', + 'DIOMEM_PWR_FORCE_CTRL', 'DIOMEM_PWR_FORCE_CTRL2', + 'DIOMEM_PWR_SEL_CTRL', 'DIOMEM_PWR_SEL_CTRL2', 'DIO_BASE', 'DIO_BASE__INST0_SEG0', 'DIO_BASE__INST0_SEG1', 'DIO_BASE__INST0_SEG2', 'DIO_BASE__INST0_SEG3', 'DIO_BASE__INST0_SEG4', 'DIO_BASE__INST1_SEG0', @@ -13911,42 +63745,1078 @@ __all__ = \ 'DIO_BASE__INST5_SEG3', 'DIO_BASE__INST5_SEG4', 'DIO_BASE__INST6_SEG0', 'DIO_BASE__INST6_SEG1', 'DIO_BASE__INST6_SEG2', 'DIO_BASE__INST6_SEG3', - 'DIO_BASE__INST6_SEG4', 'DPCS_BASE', 'DPCS_BASE__INST0_SEG0', - 'DPCS_BASE__INST0_SEG1', 'DPCS_BASE__INST0_SEG2', - 'DPCS_BASE__INST0_SEG3', 'DPCS_BASE__INST0_SEG4', - 'DPCS_BASE__INST1_SEG0', 'DPCS_BASE__INST1_SEG1', - 'DPCS_BASE__INST1_SEG2', 'DPCS_BASE__INST1_SEG3', - 'DPCS_BASE__INST1_SEG4', 'DPCS_BASE__INST2_SEG0', - 'DPCS_BASE__INST2_SEG1', 'DPCS_BASE__INST2_SEG2', - 'DPCS_BASE__INST2_SEG3', 'DPCS_BASE__INST2_SEG4', - 'DPCS_BASE__INST3_SEG0', 'DPCS_BASE__INST3_SEG1', - 'DPCS_BASE__INST3_SEG2', 'DPCS_BASE__INST3_SEG3', - 'DPCS_BASE__INST3_SEG4', 'DPCS_BASE__INST4_SEG0', - 'DPCS_BASE__INST4_SEG1', 'DPCS_BASE__INST4_SEG2', - 'DPCS_BASE__INST4_SEG3', 'DPCS_BASE__INST4_SEG4', - 'DPCS_BASE__INST5_SEG0', 'DPCS_BASE__INST5_SEG1', - 'DPCS_BASE__INST5_SEG2', 'DPCS_BASE__INST5_SEG3', - 'DPCS_BASE__INST5_SEG4', 'DPCS_BASE__INST6_SEG0', - 'DPCS_BASE__INST6_SEG1', 'DPCS_BASE__INST6_SEG2', - 'DPCS_BASE__INST6_SEG3', 'DPCS_BASE__INST6_SEG4', 'FRAME_TMZ', - 'FUSE_BASE', 'FUSE_BASE__INST0_SEG0', 'FUSE_BASE__INST0_SEG1', - 'FUSE_BASE__INST0_SEG2', 'FUSE_BASE__INST0_SEG3', - 'FUSE_BASE__INST0_SEG4', 'FUSE_BASE__INST1_SEG0', - 'FUSE_BASE__INST1_SEG1', 'FUSE_BASE__INST1_SEG2', - 'FUSE_BASE__INST1_SEG3', 'FUSE_BASE__INST1_SEG4', - 'FUSE_BASE__INST2_SEG0', 'FUSE_BASE__INST2_SEG1', - 'FUSE_BASE__INST2_SEG2', 'FUSE_BASE__INST2_SEG3', - 'FUSE_BASE__INST2_SEG4', 'FUSE_BASE__INST3_SEG0', - 'FUSE_BASE__INST3_SEG1', 'FUSE_BASE__INST3_SEG2', - 'FUSE_BASE__INST3_SEG3', 'FUSE_BASE__INST3_SEG4', - 'FUSE_BASE__INST4_SEG0', 'FUSE_BASE__INST4_SEG1', - 'FUSE_BASE__INST4_SEG2', 'FUSE_BASE__INST4_SEG3', - 'FUSE_BASE__INST4_SEG4', 'FUSE_BASE__INST5_SEG0', - 'FUSE_BASE__INST5_SEG1', 'FUSE_BASE__INST5_SEG2', - 'FUSE_BASE__INST5_SEG3', 'FUSE_BASE__INST5_SEG4', - 'FUSE_BASE__INST6_SEG0', 'FUSE_BASE__INST6_SEG1', - 'FUSE_BASE__INST6_SEG2', 'FUSE_BASE__INST6_SEG3', - 'FUSE_BASE__INST6_SEG4', 'GC_BASE', 'GC_BASE__INST0_SEG0', + 'DIO_BASE__INST6_SEG4', 'DIO_DBG_BLOCK_SEL', + 'DIO_DBG_BLOCK_SEL_AUX0', 'DIO_DBG_BLOCK_SEL_AUX1', + 'DIO_DBG_BLOCK_SEL_AUX2', 'DIO_DBG_BLOCK_SEL_AUX3', + 'DIO_DBG_BLOCK_SEL_AUX4', 'DIO_DBG_BLOCK_SEL_DIGA', + 'DIO_DBG_BLOCK_SEL_DIGB', 'DIO_DBG_BLOCK_SEL_DIGC', + 'DIO_DBG_BLOCK_SEL_DIGD', 'DIO_DBG_BLOCK_SEL_DIGE', + 'DIO_DBG_BLOCK_SEL_DIGFE_A', 'DIO_DBG_BLOCK_SEL_DIGFE_B', + 'DIO_DBG_BLOCK_SEL_DIGFE_C', 'DIO_DBG_BLOCK_SEL_DIGFE_D', + 'DIO_DBG_BLOCK_SEL_DIGFE_E', 'DIO_DBG_BLOCK_SEL_DIO', + 'DIO_DBG_BLOCK_SEL_DPA', 'DIO_DBG_BLOCK_SEL_DPB', + 'DIO_DBG_BLOCK_SEL_DPC', 'DIO_DBG_BLOCK_SEL_DPD', + 'DIO_DBG_BLOCK_SEL_DPE', 'DIO_DBG_BLOCK_SEL_DPFE_A', + 'DIO_DBG_BLOCK_SEL_DPFE_B', 'DIO_DBG_BLOCK_SEL_DPFE_C', + 'DIO_DBG_BLOCK_SEL_DPFE_D', 'DIO_DBG_BLOCK_SEL_DPFE_E', + 'DIO_DBG_BLOCK_SEL_PERFMON_DIO', 'DIO_DBG_BLOCK_SEL_RESERVED', + 'DIO_FIFO_ERROR', 'DIO_FIFO_ERROR_00', 'DIO_FIFO_ERROR_01', + 'DIO_FIFO_ERROR_10', 'DIO_FIFO_ERROR_11', + 'DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE', + 'DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL', + 'DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE', + 'DISABLE_BINNING_USE_LEGACY_SC', 'DISABLE_BINNING_USE_NEW_SC', + 'DISABLE_CLOCK_GATING', 'DISABLE_CLOCK_GATING_IN_DCO', + 'DISABLE_DEBUG', 'DISABLE_JITTER_REMOVAL', 'DISABLE_MEM_PWR_CTRL', + 'DISABLE_PWL', 'DISABLE_TF0_OPT', 'DISABLE_TF1_OPT', + 'DISABLE_THE_FEATURE', 'DISABLE_THE_INTERRUPT', + 'DISPCLK_CHG_FWD_CORR_DISABLE', + 'DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING', + 'DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING', + 'DISPCLK_FREQ_RAMP_COMPLETED', 'DISPCLK_FREQ_RAMP_DONE', + 'DISPCLK_FREQ_RAMP_IN_PROGRESS', 'DIVISOR_BY1', + 'DIVISOR_BY2_RESERVED', 'DIVISOR_BY3', 'DIVISOR_BY4_RESERVED', + 'DIVISOR_BY5_RESERVED', 'DIVISOR_BY6_RESERVED', + 'DIVISOR_BY7_RESERVED', 'DIVISOR_BY8_RESERVED', 'DIV_2', 'DIV_4', + 'DIV_8', 'DI_INDEX_SIZE_16_BIT', 'DI_INDEX_SIZE_32_BIT', + 'DI_INDEX_SIZE_8_BIT', 'DI_MAJOR_MODE_0', 'DI_MAJOR_MODE_1', + 'DI_PT_2D_RECTANGLE', 'DI_PT_LINELIST', 'DI_PT_LINELIST_ADJ', + 'DI_PT_LINELOOP', 'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', + 'DI_PT_NONE', 'DI_PT_PATCH', 'DI_PT_POINTLIST', 'DI_PT_POLYGON', + 'DI_PT_QUADLIST', 'DI_PT_QUADSTRIP', 'DI_PT_RECTLIST', + 'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRILIST_ADJ', + 'DI_PT_TRISTRIP', 'DI_PT_TRISTRIP_ADJ', 'DI_PT_UNUSED_1', + 'DI_PT_UNUSED_3', 'DI_PT_UNUSED_4', 'DI_PT_UNUSED_5', + 'DI_SRC_SEL_AUTO_INDEX', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE', + 'DI_SRC_SEL_RESERVED', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE', + 'DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE', + 'DMDATA_CLEAR_UNDERFLOW_STATUS', 'DMDATA_DONE', + 'DMDATA_DONT_CLEAR', 'DMDATA_HARDWARE_UPDATE_MODE', 'DMDATA_MODE', + 'DMDATA_NOT_SENT_TO_DIG', 'DMDATA_NOT_UNDERFLOW', + 'DMDATA_NOT_UPDATED', 'DMDATA_QOS_LEVEL_FROM_SOFTWARE', + 'DMDATA_QOS_LEVEL_FROM_TTU', 'DMDATA_QOS_MODE', 'DMDATA_REPEAT', + 'DMDATA_SENT_TO_DIG', 'DMDATA_SOFTWARE_UPDATE_MODE', + 'DMDATA_UNDERFLOW', 'DMDATA_UNDERFLOWED', + 'DMDATA_UNDERFLOW_CLEAR', 'DMDATA_UPDATED', + 'DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES', + 'DMDATA_USE_FOR_CURRENT_FRAME_ONLY', 'DMDATA_VM_DONE', + 'DMDATA_VM_IS_DONE', 'DMDATA_VM_IS_NOT_DONE', + 'DMDATA_WAS_UPDATED', 'DME_MEM_DISABLE_MEM_PWR_CTRL', + 'DME_MEM_ENABLE_MEM_PWR_CTRL', 'DME_MEM_FORCE_DEEP_SLEEP_REQUEST', + 'DME_MEM_FORCE_LIGHT_SLEEP_REQUEST', + 'DME_MEM_FORCE_SHUT_DOWN_REQUEST', 'DME_MEM_NO_FORCE_REQUEST', + 'DME_MEM_POWER_STATE_ENUM', 'DME_MEM_POWER_STATE_ENUM_DS', + 'DME_MEM_POWER_STATE_ENUM_LS', 'DME_MEM_POWER_STATE_ENUM_ON', + 'DME_MEM_POWER_STATE_ENUM_SD', 'DME_MEM_PWR_DIS_CTRL', + 'DME_MEM_PWR_FORCE_CTRL', 'DMU_CLOCK_ON', 'DMU_CLOCK_STATUS_OFF', + 'DMU_CLOCK_STATUS_ON', 'DMU_DC_GPU_TIMER_READ_SELECT', + 'DMU_DC_GPU_TIMER_START_POSITION', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6', + 'DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7', + 'DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71', + 'DMU_GPU_TIMER_START_0_END_27', 'DMU_GPU_TIMER_START_10_END_37', + 'DMU_GPU_TIMER_START_1_END_28', 'DMU_GPU_TIMER_START_2_END_29', + 'DMU_GPU_TIMER_START_3_END_30', 'DMU_GPU_TIMER_START_4_END_31', + 'DMU_GPU_TIMER_START_6_END_33', 'DMU_GPU_TIMER_START_8_END_35', + 'DOLBY_VISION_DISABLED', 'DOLBY_VISION_ENABLE', + 'DOLBY_VISION_ENABLED', 'DONUTS', 'DOUT_I2C_ACK', + 'DOUT_I2C_ACK_TO_CLEAN', + 'DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_ABORT_XFER', + 'DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG', + 'DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER', + 'DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH', + 'DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED', + 'DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED', + 'DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ', + 'DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ', + 'DOUT_I2C_CONTROL_DBG_REF_SEL', 'DOUT_I2C_CONTROL_DDC_SELECT', + 'DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG', 'DOUT_I2C_CONTROL_GO', + 'DOUT_I2C_CONTROL_NORMAL_DEBUG', + 'DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER', + 'DOUT_I2C_CONTROL_RESET_SW_STATUS', + 'DOUT_I2C_CONTROL_SELECT_DDC1', 'DOUT_I2C_CONTROL_SELECT_DDC2', + 'DOUT_I2C_CONTROL_SELECT_DDC3', 'DOUT_I2C_CONTROL_SELECT_DDC4', + 'DOUT_I2C_CONTROL_SELECT_DDC5', 'DOUT_I2C_CONTROL_SELECT_DDCVGA', + 'DOUT_I2C_CONTROL_SEND_RESET', + 'DOUT_I2C_CONTROL_SEND_RESET_LENGTH', + 'DOUT_I2C_CONTROL_SOFT_RESET', 'DOUT_I2C_CONTROL_START_TRANSFER', + 'DOUT_I2C_CONTROL_STOP_TRANSFER', + 'DOUT_I2C_CONTROL_SW_STATUS_RESET', 'DOUT_I2C_CONTROL_TRANS0', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2', + 'DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3', + 'DOUT_I2C_CONTROL_TRANSACTION_COUNT', + 'DOUT_I2C_CONTROL__NOT_SEND_RESET', + 'DOUT_I2C_CONTROL__SEND_RESET', + 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10', + 'DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9', + 'DOUT_I2C_DATA_INDEX_WRITE', 'DOUT_I2C_DATA__INDEX_WRITE', + 'DOUT_I2C_DATA__NOT_INDEX_WRITE', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS', + 'DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT', + 'DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL', + 'DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA', + 'DOUT_I2C_DDC_SPEED_THRESHOLD', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE', + 'DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE', + 'DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET', + 'DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION', + 'DOUT_I2C_NO_ACK', 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL', + 'DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE', + 'DOUT_I2C_TRANSACTION_STOP_ALL_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS', + 'DOUT_I2C_TRANSACTION_STOP_ON_NACK', 'DPCS_BASE', + 'DPCS_BASE__INST0_SEG0', 'DPCS_BASE__INST0_SEG1', + 'DPCS_BASE__INST0_SEG2', 'DPCS_BASE__INST0_SEG3', + 'DPCS_BASE__INST0_SEG4', 'DPCS_BASE__INST1_SEG0', + 'DPCS_BASE__INST1_SEG1', 'DPCS_BASE__INST1_SEG2', + 'DPCS_BASE__INST1_SEG3', 'DPCS_BASE__INST1_SEG4', + 'DPCS_BASE__INST2_SEG0', 'DPCS_BASE__INST2_SEG1', + 'DPCS_BASE__INST2_SEG2', 'DPCS_BASE__INST2_SEG3', + 'DPCS_BASE__INST2_SEG4', 'DPCS_BASE__INST3_SEG0', + 'DPCS_BASE__INST3_SEG1', 'DPCS_BASE__INST3_SEG2', + 'DPCS_BASE__INST3_SEG3', 'DPCS_BASE__INST3_SEG4', + 'DPCS_BASE__INST4_SEG0', 'DPCS_BASE__INST4_SEG1', + 'DPCS_BASE__INST4_SEG2', 'DPCS_BASE__INST4_SEG3', + 'DPCS_BASE__INST4_SEG4', 'DPCS_BASE__INST5_SEG0', + 'DPCS_BASE__INST5_SEG1', 'DPCS_BASE__INST5_SEG2', + 'DPCS_BASE__INST5_SEG3', 'DPCS_BASE__INST5_SEG4', + 'DPCS_BASE__INST6_SEG0', 'DPCS_BASE__INST6_SEG1', + 'DPCS_BASE__INST6_SEG2', 'DPCS_BASE__INST6_SEG3', + 'DPCS_BASE__INST6_SEG4', 'DPHY_8B10B_CUR_DISP', + 'DPHY_8B10B_CUR_DISP_ONE', 'DPHY_8B10B_CUR_DISP_ZERO', + 'DPHY_8B10B_NOT_RESET', 'DPHY_8B10B_OUTPUT', 'DPHY_8B10B_RESET', + 'DPHY_8B10B_RESETET', + 'DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION', + 'DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE', + 'DPHY_ALT_SCRAMBLER_RESET_EN', 'DPHY_ALT_SCRAMBLER_RESET_SEL', + 'DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE', + 'DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE', + 'DPHY_ATEST_LANE0_PRBS_PATTERN', 'DPHY_ATEST_LANE0_REG_PATTERN', + 'DPHY_ATEST_LANE1_PRBS_PATTERN', 'DPHY_ATEST_LANE1_REG_PATTERN', + 'DPHY_ATEST_LANE2_PRBS_PATTERN', 'DPHY_ATEST_LANE2_REG_PATTERN', + 'DPHY_ATEST_LANE3_PRBS_PATTERN', 'DPHY_ATEST_LANE3_REG_PATTERN', + 'DPHY_ATEST_SEL_LANE0', 'DPHY_ATEST_SEL_LANE1', + 'DPHY_ATEST_SEL_LANE2', 'DPHY_ATEST_SEL_LANE3', 'DPHY_BYPASS', + 'DPHY_CRC_CONTINUOUS', 'DPHY_CRC_CONT_EN', 'DPHY_CRC_DISABLED', + 'DPHY_CRC_EN', 'DPHY_CRC_ENABLED', 'DPHY_CRC_FIELD', + 'DPHY_CRC_LANE0_SELECTED', 'DPHY_CRC_LANE1_SELECTED', + 'DPHY_CRC_LANE2_SELECTED', 'DPHY_CRC_LANE3_SELECTED', + 'DPHY_CRC_MST_PHASE_ERROR_ACK', 'DPHY_CRC_MST_PHASE_ERROR_ACKED', + 'DPHY_CRC_MST_PHASE_ERROR_NO_ACK', 'DPHY_CRC_ONE_SHOT', + 'DPHY_CRC_SEL', 'DPHY_CRC_START_FROM_BOTTOM_FIELD', + 'DPHY_CRC_START_FROM_TOP_FIELD', 'DPHY_DBG_OUTPUT', + 'DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY', + 'DPHY_FAST_TRAINING_CAPABLE', 'DPHY_FAST_TRAINING_NOT_CAPABLE_0', + 'DPHY_FEC_ACTIVE', 'DPHY_FEC_DISABLED', 'DPHY_FEC_ENABLE', + 'DPHY_FEC_ENABLED', 'DPHY_FEC_NOT_ACTIVE', 'DPHY_FEC_READY', + 'DPHY_FEC_READY_DIS', 'DPHY_FEC_READY_EN', + 'DPHY_LOAD_BS_COUNT_NOT_STARTED', 'DPHY_LOAD_BS_COUNT_START', + 'DPHY_LOAD_BS_COUNT_STARTED', 'DPHY_NO_SKEW', + 'DPHY_PRBS11_SELECTED', 'DPHY_PRBS23_SELECTED', + 'DPHY_PRBS7_SELECTED', 'DPHY_PRBS_DISABLE', 'DPHY_PRBS_EN', + 'DPHY_PRBS_ENABLE', 'DPHY_PRBS_SEL', + 'DPHY_RX_FAST_TRAINING_CAPABLE', 'DPHY_SCRAMBLER_ADVANCE', + 'DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL', + 'DPHY_SCRAMBLER_DIS', 'DPHY_SCRAMBLER_KCODE', + 'DPHY_SCRAMBLER_KCODE_DISABLED', 'DPHY_SCRAMBLER_KCODE_ENABLED', + 'DPHY_SCRAMBLER_SEL', 'DPHY_SCRAMBLER_SEL_DBG_DATA', + 'DPHY_SCRAMBLER_SEL_LANE_DATA', 'DPHY_SCR_DISABLED', + 'DPHY_SCR_ENABLED', 'DPHY_SKEW_BYPASS', + 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM', + 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET', + 'DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET', + 'DPHY_SW_FAST_TRAINING_NOT_STARTED', + 'DPHY_SW_FAST_TRAINING_START', 'DPHY_SW_FAST_TRAINING_STARTED', + 'DPHY_TRAINING_PATTERN_1', 'DPHY_TRAINING_PATTERN_2', + 'DPHY_TRAINING_PATTERN_3', 'DPHY_TRAINING_PATTERN_4', + 'DPHY_TRAINING_PATTERN_SEL', 'DPHY_WITH_SKEW', 'DPREFCLK_SRC_SEL', + 'DPREFCLK_SRC_SEL_CK', 'DPREFCLK_SRC_SEL_P0PLL', + 'DPREFCLK_SRC_SEL_P1PLL', 'DPREFCLK_SRC_SEL_P2PLL', + 'DPTE_GROUP_SIZE', 'DPTE_GROUP_SIZE_1024B', + 'DPTE_GROUP_SIZE_128B', 'DPTE_GROUP_SIZE_2048B', + 'DPTE_GROUP_SIZE_256B', 'DPTE_GROUP_SIZE_512B', + 'DPTE_GROUP_SIZE_64B', 'DP_128B132B', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS', + 'DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC', + 'DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG', + 'DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ', + 'DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ', 'DP_AUX_ARB_STATUS', + 'DP_AUX_CONTROL_HPD1_SELECTED', 'DP_AUX_CONTROL_HPD2_SELECTED', + 'DP_AUX_CONTROL_HPD3_SELECTED', 'DP_AUX_CONTROL_HPD4_SELECTED', + 'DP_AUX_CONTROL_HPD5_SELECTED', 'DP_AUX_CONTROL_HPD_SEL', + 'DP_AUX_CONTROL_NO_HPD_SELECTED', 'DP_AUX_CONTROL_TEST_MODE', + 'DP_AUX_CONTROL_TEST_MODE_DISABLE', + 'DP_AUX_CONTROL_TEST_MODE_ENABLE', + 'DP_AUX_DEFINITE_ERR_REACHED_ACK', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES', + 'DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START', + 'DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64', + 'DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US', + 'DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK', + 'DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF', + 'DP_AUX_ERR_OCCURRED_ACK', 'DP_AUX_ERR_OCCURRED__ACK', + 'DP_AUX_ERR_OCCURRED__NOT_ACK', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ', + 'DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US', + 'DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS', + 'DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256', + 'DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64', + 'DP_AUX_IDLE', 'DP_AUX_INT_ACK', 'DP_AUX_INT_LS_UPDATE_ACK', + 'DP_AUX_INT_LS_UPDATE_NOT_ACK', 'DP_AUX_INT__ACK', + 'DP_AUX_INT__NOT_ACK', 'DP_AUX_IN_USE_GTC', 'DP_AUX_IN_USE_LS', + 'DP_AUX_IN_USE_PHYWAKE', 'DP_AUX_IN_USE_SW', + 'DP_AUX_LS_UPDATE_ACK', 'DP_AUX_PHY_WAKE_HIGH_PRIORITY', + 'DP_AUX_PHY_WAKE_LOW_PRIORITY', 'DP_AUX_PHY_WAKE_PRIORITY', + 'DP_AUX_POTENTIAL_ERR_REACHED_ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__ACK', + 'DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK', 'DP_AUX_RESET', + 'DP_AUX_RESET_ASSERTED', 'DP_AUX_RESET_DEASSERTED', + 'DP_AUX_RESET_DONE', 'DP_AUX_RESET_SEQUENCE_DONE', + 'DP_AUX_RESET_SEQUENCE_NOT_DONE', 'DP_AUX_RX_TIMEOUT_LEN_MUL', + 'DP_AUX_RX_TIMEOUT_LEN_MUL_2', 'DP_AUX_RX_TIMEOUT_LEN_MUL_4', + 'DP_AUX_RX_TIMEOUT_LEN_MUL_8', 'DP_AUX_RX_TIMEOUT_LEN_NO_MUL', + 'DP_AUX_SW_CONTROL_LS_READ_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG', + 'DP_AUX_SW_CONTROL_LS_READ__TRIG', 'DP_AUX_SW_CONTROL_SW_GO', + 'DP_AUX_SW_CONTROL_SW__GO', 'DP_AUX_SW_CONTROL_SW__NOT_GO', + 'DP_AUX_TX_PRECHARGE_LEN_MUL', 'DP_AUX_TX_PRECHARGE_LEN_MUL_2', + 'DP_AUX_TX_PRECHARGE_LEN_MUL_4', 'DP_AUX_TX_PRECHARGE_LEN_MUL_8', + 'DP_AUX_TX_PRECHARGE_LEN_NO_MUL', 'DP_COMPONENT_DEPTH', + 'DP_COMPONENT_DEPTH_10BPC', 'DP_COMPONENT_DEPTH_12BPC', + 'DP_COMPONENT_DEPTH_16BPC', 'DP_COMPONENT_DEPTH_6BPC', + 'DP_COMPONENT_DEPTH_8BPC', 'DP_CP_ENCRYPTION_TYPE', + 'DP_CP_ENCRYPTION_TYPE_0', 'DP_CP_ENCRYPTION_TYPE_1', + 'DP_DPHY_8B10B_EXT_DISP', 'DP_DPHY_8B10B_EXT_DISP_ONE', + 'DP_DPHY_8B10B_EXT_DISP_ZERO', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASK', + 'DP_DPHY_FAST_TRAINING_COMPLETE_MASKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED', + 'DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN', + 'DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED', + 'DP_DPHY_HBR2_PASS_THROUGH', 'DP_DPHY_HBR2_PATTERN_1', + 'DP_DPHY_HBR2_PATTERN_2_NEG', 'DP_DPHY_HBR2_PATTERN_2_POS', + 'DP_DPHY_HBR2_PATTERN_3', 'DP_DPHY_HBR2_PATTERN_CONTROL_MODE', + 'DP_DPHY_SYM32_1LANE', 'DP_DPHY_SYM32_2LANE', + 'DP_DPHY_SYM32_4LANE', 'DP_DPHY_SYM32_ACTIVE', + 'DP_DPHY_SYM32_CRC_END_LLCP', 'DP_DPHY_SYM32_CRC_END_PS_ANY', + 'DP_DPHY_SYM32_CRC_END_PS_LT_SR', 'DP_DPHY_SYM32_CRC_END_PS_ONLY', + 'DP_DPHY_SYM32_CRC_START_LLCP', + 'DP_DPHY_SYM32_CRC_START_PS_LT_SR', + 'DP_DPHY_SYM32_CRC_START_PS_ONLY', + 'DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR', + 'DP_DPHY_SYM32_CRC_START_TP_START', + 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER', + 'DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER', + 'DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX', + 'DP_DPHY_SYM32_CRC_USE_END_EVENT', + 'DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', 'DP_DPHY_SYM32_DISABLE', + 'DP_DPHY_SYM32_ENABLE', 'DP_DPHY_SYM32_ENCRYPT_TYPE0', + 'DP_DPHY_SYM32_ENCRYPT_TYPE1', 'DP_DPHY_SYM32_LT_TPS1', + 'DP_DPHY_SYM32_LT_TPS2', 'DP_DPHY_SYM32_NOT_RESET', + 'DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING', + 'DP_DPHY_SYM32_RATE_UPDATE_PENDING', 'DP_DPHY_SYM32_RESERVED', + 'DP_DPHY_SYM32_RESET', 'DP_DPHY_SYM32_RESET_STATUS_ASSERTED', + 'DP_DPHY_SYM32_RESET_STATUS_DEASSERTED', + 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE', + 'DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING', + 'DP_DPHY_SYM32_SAT_NO_UPDATE', + 'DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING', + 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE', + 'DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING', + 'DP_DPHY_SYM32_STATUS_ENABLED', 'DP_DPHY_SYM32_STATUS_IDLE', + 'DP_DPHY_SYM32_STREAM_OVR_ALWAYS', + 'DP_DPHY_SYM32_STREAM_OVR_NONE', + 'DP_DPHY_SYM32_STREAM_OVR_REPLACE', + 'DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL', + 'DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA', 'DP_DPHY_SYM32_TEST', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7', + 'DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9', + 'DP_DPHY_SYM32_TP_SELECT_CUSTOM', 'DP_DPHY_SYM32_TP_SELECT_PRBS', + 'DP_DPHY_SYM32_TP_SELECT_SQUARE', 'DP_DPHY_SYM32_TP_SELECT_TPS1', + 'DP_DPHY_SYM32_TP_SELECT_TPS2', 'DP_DSC_444_SIMPLE_422', + 'DP_DSC_DISABLE', 'DP_DSC_MODE', 'DP_DSC_NATIVE_422_420', + 'DP_DTO_DESPREAD_DISABLE', 'DP_DTO_DESPREAD_ENABLE', + 'DP_DTO_DS_DISABLE', 'DP_EMBEDDED_PANEL', + 'DP_EMBEDDED_PANEL_MODE', 'DP_EXTERNAL_PANEL', + 'DP_LINK_TRAINING_ALREADY_COMPLETE', 'DP_LINK_TRAINING_COMPLETE', + 'DP_LINK_TRAINING_NOT_COMPLETE', 'DP_LINK_TRAINING_SWITCH_MODE', + 'DP_LINK_TRAINING_SWITCH_TO_IDLE', + 'DP_LINK_TRAINING_SWITCH_TO_VIDEO', 'DP_ML_PHY_SEQ_IMMEDIATE', + 'DP_ML_PHY_SEQ_LINE_NUM', 'DP_ML_PHY_SEQ_MODE', + 'DP_MSA_V_TIMING_OVERRIDE_EN', 'DP_MSE_BLANK_CODE', + 'DP_MSE_BLANK_CODE_SF_FILLED', 'DP_MSE_BLANK_CODE_ZERO_FILLED', + 'DP_MSE_LINK_LINE', 'DP_MSE_LINK_LINE_128_MTP_LONG', + 'DP_MSE_LINK_LINE_256_MTP_LONG', 'DP_MSE_LINK_LINE_32_MTP_LONG', + 'DP_MSE_LINK_LINE_64_MTP_LONG', 'DP_MSE_NOT_ZERO_FE_ENCODER', + 'DP_MSE_SAT_ENCRYPT0', 'DP_MSE_SAT_ENCRYPT0_DISABLED', + 'DP_MSE_SAT_ENCRYPT0_ENABLED', 'DP_MSE_SAT_ENCRYPT1', + 'DP_MSE_SAT_ENCRYPT1_DISABLED', 'DP_MSE_SAT_ENCRYPT1_ENABLED', + 'DP_MSE_SAT_ENCRYPT2', 'DP_MSE_SAT_ENCRYPT2_DISABLED', + 'DP_MSE_SAT_ENCRYPT2_ENABLED', 'DP_MSE_SAT_ENCRYPT3', + 'DP_MSE_SAT_ENCRYPT3_DISABLED', 'DP_MSE_SAT_ENCRYPT3_ENABLED', + 'DP_MSE_SAT_ENCRYPT4', 'DP_MSE_SAT_ENCRYPT4_DISABLED', + 'DP_MSE_SAT_ENCRYPT4_ENABLED', 'DP_MSE_SAT_ENCRYPT5', + 'DP_MSE_SAT_ENCRYPT5_DISABLED', 'DP_MSE_SAT_ENCRYPT5_ENABLED', + 'DP_MSE_SAT_UPDATE_ACT', 'DP_MSE_SAT_UPDATE_NO_ACTION', + 'DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER', + 'DP_MSE_SAT_UPDATE_WITH_TRIGGER', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE', + 'DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE', 'DP_MSE_TIMESTAMP_MODE', + 'DP_MSE_ZERO_ENCODER', 'DP_MSE_ZERO_FE_ENCODER', + 'DP_MSO_FOUR_SSTLINK', 'DP_MSO_NUM_OF_SST_LINKS', + 'DP_MSO_ONE_SSTLINK', 'DP_MSO_TWO_SSTLINK', + 'DP_ONE_PIXEL_PER_CYCLE', 'DP_PIXEL_ENCODING', + 'DP_PIXEL_ENCODING_RGB444', 'DP_PIXEL_ENCODING_RGB_WIDE_GAMUT', + 'DP_PIXEL_ENCODING_YCBCR420', 'DP_PIXEL_ENCODING_YCBCR422', + 'DP_PIXEL_ENCODING_YCBCR444', 'DP_PIXEL_ENCODING_Y_ONLY', + 'DP_PIXEL_PER_CYCLE_PROCESSING_NUM', + 'DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE', + 'DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED', + 'DP_SEC_ASP_HIGH_PRIORITY', 'DP_SEC_ASP_LOW_PRIORITY', + 'DP_SEC_ASP_PRIORITY', 'DP_SEC_AUDIO_MUTE', + 'DP_SEC_AUDIO_MUTE_HW_CTRL', 'DP_SEC_AUDIO_MUTE_SW_CTRL', + 'DP_SEC_COLLISION_ACK', 'DP_SEC_COLLISION_ACK_CLR_FLAG', + 'DP_SEC_COLLISION_ACK_NO_EFFECT', 'DP_SEC_GSP0_PRIORITY', + 'DP_SEC_GSP_SEND', 'DP_SEC_GSP_SEND_ANY_LINE', + 'DP_SEC_GSP_SEND_PPS', 'DP_SEC_LINE_REFERENCE', + 'DP_SEC_TIMESTAMP_AUTO_CALC_MODE', 'DP_SEC_TIMESTAMP_MODE', + 'DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE', 'DP_STEER_OVERFLOW_ACK', + 'DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_STEER_OVERFLOW_ACK_NO_EFFECT', 'DP_STEER_OVERFLOW_MASK', + 'DP_STEER_OVERFLOW_MASKED', 'DP_STEER_OVERFLOW_UNMASK', + 'DP_STREAM_ENC_DCCG', 'DP_STREAM_ENC_DISPLAY_PIPE', + 'DP_STREAM_ENC_HARDWARE', 'DP_STREAM_ENC_NOT_RESET', + 'DP_STREAM_ENC_NO_ERROR_OCCURRED', + 'DP_STREAM_ENC_OVERFLOW_OCCURRED', + 'DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR', + 'DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT', + 'DP_STREAM_ENC_PROGRAMMABLE', 'DP_STREAM_ENC_READ_CLOCK_CONTROL', + 'DP_STREAM_ENC_RESET', 'DP_STREAM_ENC_RESET_CONTROL', + 'DP_STREAM_ENC_STREAM_ACTIVE', 'DP_STREAM_ENC_UNDERFLOW_OCCURRED', + 'DP_STREAM_ENC_VIDEO_STREAM_ACTIVE', + 'DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', + 'DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET', + 'DP_STREAM_MAPPER_LINK0', 'DP_STREAM_MAPPER_LINK1', + 'DP_STREAM_MAPPER_RESERVED', 'DP_SYM32_ENC_COMPONENT_DEPTH_10BPC', + 'DP_SYM32_ENC_COMPONENT_DEPTH_12BPC', + 'DP_SYM32_ENC_COMPONENT_DEPTH_6BPC', + 'DP_SYM32_ENC_COMPONENT_DEPTH_8BPC', + 'DP_SYM32_ENC_COMPRESSED_FORMAT', 'DP_SYM32_ENC_CONTINUOUS_MODE', + 'DP_SYM32_ENC_CRC_NOT_VALID', 'DP_SYM32_ENC_CRC_VALID', + 'DP_SYM32_ENC_DISABLE', 'DP_SYM32_ENC_DP_SOF', + 'DP_SYM32_ENC_ENABLE', 'DP_SYM32_ENC_GSP_DEADLINE_MISSED', + 'DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0', + 'DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1', + 'DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME', + 'DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER', + 'DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING', + 'DP_SYM32_ENC_GSP_TRIGGER_PENDING', + 'DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST', + 'DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST', + 'DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST', + 'DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST', + 'DP_SYM32_ENC_NOT_PENDING', 'DP_SYM32_ENC_NOT_RESET', + 'DP_SYM32_ENC_NO_OVERFLOW_OCCURRED', 'DP_SYM32_ENC_ONE_SHOT_MODE', + 'DP_SYM32_ENC_OTG_SOF', 'DP_SYM32_ENC_OVERFLOW_OCCURRED', + 'DP_SYM32_ENC_PENDING', + 'DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444', + 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420', + 'DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422', + 'DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY', + 'DP_SYM32_ENC_POWER_STATE_ENUM_DS', + 'DP_SYM32_ENC_POWER_STATE_ENUM_LS', + 'DP_SYM32_ENC_POWER_STATE_ENUM_ON', + 'DP_SYM32_ENC_POWER_STATE_ENUM_SD', 'DP_SYM32_ENC_RESET', + 'DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED', + 'DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED', + 'DP_SYM32_ENC_SDP_HIGH_PRIORITY', 'DP_SYM32_ENC_SDP_LOW_PRIORITY', + 'DP_SYM32_ENC_UNCOMPRESSED_FORMAT', + 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK', + 'DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK', + 'DP_SYM32_ENC_VID_STREAM_NO_DEFER', 'DP_SYNC_POLARITY', + 'DP_SYNC_POLARITY_ACTIVE_HIGH', 'DP_SYNC_POLARITY_ACTIVE_LOW', + 'DP_TU_OVERFLOW_ACK', 'DP_TU_OVERFLOW_ACK_CLR_INTERRUPT', + 'DP_TU_OVERFLOW_ACK_NO_EFFECT', 'DP_TWO_PIXEL_PER_CYCLE', + 'DP_UDI_1_LANE', 'DP_UDI_2_LANES', 'DP_UDI_4_LANES', + 'DP_UDI_LANES', 'DP_UDI_LANES_RESERVED', + 'DP_VID_ENHANCED_FRAME_MODE', 'DP_VID_M_1X_INPUT_PIXEL_RATE', + 'DP_VID_M_2X_INPUT_PIXEL_RATE', 'DP_VID_M_4X_INPUT_PIXEL_RATE', + 'DP_VID_M_8X_INPUT_PIXEL_RATE', 'DP_VID_M_N_CALC_AUTO', + 'DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE', + 'DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START', + 'DP_VID_M_N_DOUBLE_BUFFER_MODE', 'DP_VID_M_N_GEN_EN', + 'DP_VID_M_N_PROGRAMMED_VIA_REG', 'DP_VID_N_MUL', + 'DP_VID_STREAM_DISABLE_ACK', 'DP_VID_STREAM_DISABLE_MASK', + 'DP_VID_STREAM_DIS_DEFER', 'DP_VID_STREAM_DIS_DEFER_TO_HBLANK', + 'DP_VID_STREAM_DIS_DEFER_TO_VBLANK', 'DP_VID_STREAM_DIS_NO_DEFER', + 'DP_VID_VBID_FIELD_POL', 'DP_VID_VBID_FIELD_POL_INV', + 'DP_VID_VBID_FIELD_POL_NORMAL', 'DRAW_DONE', + 'DSCCIF_BITS_PER_COMPONENT_ENUM', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', + 'DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 'DSCCIF_ENABLE_ENUM', 'DSCCIF_ENABLE_ENUM_DISABLED', + 'DSCCIF_ENABLE_ENUM_ENABLED', 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422', + 'DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444', + 'DSCC_BITS_PER_COMPONENT_ENUM', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT', + 'DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT', + 'DSCC_DSC_VERSION_MAJOR_ENUM', + 'DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION', + 'DSCC_DSC_VERSION_MINOR_ENUM', + 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION', + 'DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION', + 'DSCC_ENABLE_ENUM', 'DSCC_ENABLE_ENUM_DISABLED', + 'DSCC_ENABLE_ENUM_ENABLED', 'DSCC_ICH_RESET_ENUM', + 'DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET', + 'DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET', 'DSCC_LINEBUF_DEPTH_ENUM', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT', + 'DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT', + 'DSCC_MEM_PWR_DIS_ENUM', 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS', + 'DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN', 'DSCC_MEM_PWR_FORCE_ENUM', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST', + 'DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST', + 'DSCL_MODE_CHROMA_SCALING_BYPASS', 'DSCL_MODE_DSCL_BYPASS', + 'DSCL_MODE_LUMA_SCALING_BYPASS', 'DSCL_MODE_SCALING_444_BYPASS', + 'DSCL_MODE_SCALING_444_RGB_ENABLE', + 'DSCL_MODE_SCALING_444_YCBCR_ENABLE', + 'DSCL_MODE_SCALING_YCBCR_ENABLE', 'DSCL_MODE_SEL', 'DSM_DATA_SEL', + 'DSM_DATA_SEL_0', 'DSM_DATA_SEL_1', 'DSM_DATA_SEL_BOTH', + 'DSM_DATA_SEL_DISABLE', 'DSM_ENABLE_ERROR_INJECT', + 'DSM_ENABLE_ERROR_INJECT_FED_IN', + 'DSM_ENABLE_ERROR_INJECT_SINGLE', + 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE', + 'DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED', + 'DSM_SELECT_INJECT_DELAY', 'DSM_SELECT_INJECT_DELAY_DELAY_ERROR', + 'DSM_SELECT_INJECT_DELAY_NO_DELAY', 'DSM_SINGLE_WRITE', + 'DSM_SINGLE_WRITE_DIS', 'DSM_SINGLE_WRITE_EN', 'DS_HW_CAL_DIS', + 'DS_HW_CAL_EN', 'DS_HW_CAL_ENABLE', 'DS_JITTER_COUNT_SRC_SEL', + 'DS_JITTER_COUNT_SRC_SEL0', 'DS_JITTER_COUNT_SRC_SEL1', + 'DS_REF_IS_EXT_GENLOCK', 'DS_REF_IS_PCIE', 'DS_REF_IS_XTALIN', + 'DS_REF_SRC', 'DTO_FORCE_BYPASS', 'DTO_FORCE_NO_BYPASS', + 'DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKC_IN_PHASE', + 'DVOACLKC_IN_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_IN_PHASE', 'DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE', + 'DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE', + 'DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO', 'DVOACLKD_IN_PHASE', + 'DVOACLKD_IN_PHASE_WITH_PCLK_DVO', 'DVOACLK_COARSE_SKEW_CNTL', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS', + 'DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT', + 'DVOACLK_FINE_SKEW_CNTL', 'DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP', + 'DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS', + 'DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT', 'DVO_ENABLE_RST', + 'DVO_ENABLE_RST_DISABLE', 'DVO_ENABLE_RST_ENABLE', + 'DWB_CRC_CONT_EN_CONT', 'DWB_CRC_CONT_EN_ENUM', + 'DWB_CRC_CONT_EN_ONE_SHOT', 'DWB_CRC_SRC_SEL_DWB_IN', + 'DWB_CRC_SRC_SEL_DWB_OUT', 'DWB_CRC_SRC_SEL_ENUM', + 'DWB_CRC_SRC_SEL_OGAM_OUT', 'DWB_DATA_OVERFLOW_INT_TYPE_0', + 'DWB_DATA_OVERFLOW_INT_TYPE_1', 'DWB_DATA_OVERFLOW_INT_TYPE_ENUM', + 'DWB_DATA_OVERFLOW_TYPE_BUFFER', 'DWB_DATA_OVERFLOW_TYPE_ENUM', + 'DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW', + 'DWB_DATA_OVERFLOW_TYPE_VREADY', 'DWB_DATA_OVERFLOW_TYPE_VUPDATE', + 'DWB_DEBUG_SEL_DWBCP', 'DWB_DEBUG_SEL_ENUM', 'DWB_DEBUG_SEL_FC', + 'DWB_DEBUG_SEL_PERFMON', 'DWB_DEBUG_SEL_RESERVED', + 'DWB_GAMUT_REMAP_COEF_FORMAT_ENUM', + 'DWB_GAMUT_REMAP_COEF_FORMAT_S2_13', + 'DWB_GAMUT_REMAP_COEF_FORMAT_S3_12', + 'DWB_GAMUT_REMAP_MODE_BYPASS', 'DWB_GAMUT_REMAP_MODE_COEF_A', + 'DWB_GAMUT_REMAP_MODE_COEF_B', 'DWB_GAMUT_REMAP_MODE_ENUM', + 'DWB_GAMUT_REMAP_MODE_RESERVED', 'DWB_LUT_NUM_SEG', + 'DWB_MEM_PWR_FORCE_DIS', 'DWB_MEM_PWR_FORCE_DS', + 'DWB_MEM_PWR_FORCE_ENUM', 'DWB_MEM_PWR_FORCE_LS', + 'DWB_MEM_PWR_FORCE_SD', 'DWB_MEM_PWR_STATE_DS', + 'DWB_MEM_PWR_STATE_ENUM', 'DWB_MEM_PWR_STATE_LS', + 'DWB_MEM_PWR_STATE_ON', 'DWB_MEM_PWR_STATE_SD', + 'DWB_OGAM_LUT_CONFIG_MODE_DIFF', 'DWB_OGAM_LUT_CONFIG_MODE_ENUM', + 'DWB_OGAM_LUT_CONFIG_MODE_SAME', 'DWB_OGAM_LUT_HOST_SEL_ENUM', + 'DWB_OGAM_LUT_HOST_SEL_RAMA', 'DWB_OGAM_LUT_HOST_SEL_RAMB', + 'DWB_OGAM_LUT_READ_COLOR_SEL_B', + 'DWB_OGAM_LUT_READ_COLOR_SEL_ENUM', + 'DWB_OGAM_LUT_READ_COLOR_SEL_G', 'DWB_OGAM_LUT_READ_COLOR_SEL_R', + 'DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED', + 'DWB_OGAM_LUT_READ_DBG_DISABLE', 'DWB_OGAM_LUT_READ_DBG_ENABLE', + 'DWB_OGAM_LUT_READ_DBG_ENUM', 'DWB_OGAM_MODE_BYPASS', + 'DWB_OGAM_MODE_ENUM', 'DWB_OGAM_MODE_RAM_LUT_ENABLED', + 'DWB_OGAM_MODE_RESERVED', 'DWB_OGAM_PWL_DISABLE_ENUM', + 'DWB_OGAM_PWL_DISABLE_FALSE', 'DWB_OGAM_PWL_DISABLE_TRUE', + 'DWB_OGAM_SELECT_A', 'DWB_OGAM_SELECT_B', 'DWB_OGAM_SELECT_ENUM', + 'DWB_SEGMENTS_1', 'DWB_SEGMENTS_128', 'DWB_SEGMENTS_16', + 'DWB_SEGMENTS_2', 'DWB_SEGMENTS_32', 'DWB_SEGMENTS_4', + 'DWB_SEGMENTS_64', 'DWB_SEGMENTS_8', 'DWB_TEST_CLK_SEL_ENUM', + 'DWB_TEST_CLK_SEL_G', 'DWB_TEST_CLK_SEL_P', 'DWB_TEST_CLK_SEL_R', + 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE', + 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0', + 'DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1', + 'DYNAMIC_DEEP_SLEEP_EN', 'DYNAMIC_DEEP_SLEEP_ENABLE', + 'DYNAMIC_LIGHT_SLEEP_EN', 'DYNAMIC_LIGHT_SLEEP_ENABLE', + 'DYNAMIC_SHUT_DOWN_ENABLE', 'DbMemArbWatermarks', + 'DbPRTFaultBehavior', 'DbPSLControl', 'EARLY', + 'EARLY_Z_THEN_LATE_Z', 'EARLY_Z_THEN_RE_Z', + 'EFC_ACrYCb16161616_10LSB', 'EFC_ACrYCb16161616_10MSB', + 'EFC_ACrYCb16161616_12LSB', 'EFC_ACrYCb16161616_12MSB', + 'EFC_ACrYCb2101010', 'EFC_ACrYCb8888', 'EFC_ARGB1555', + 'EFC_ARGB16161616_10LSB', 'EFC_ARGB16161616_10MSB', + 'EFC_ARGB16161616_12LSB', 'EFC_ARGB16161616_12MSB', + 'EFC_ARGB16161616_FLOAT', 'EFC_ARGB16161616_SNORM', + 'EFC_ARGB16161616_UNORM', 'EFC_ARGB2101010', 'EFC_ARGB4444', + 'EFC_ARGB8888', 'EFC_AYCrCb16161616_10LSB', + 'EFC_AYCrCb16161616_10MSB', 'EFC_AYCrCb16161616_12LSB', + 'EFC_AYCrCb16161616_12MSB', 'EFC_AYCrCb8888', 'EFC_BGR101111_FIX', + 'EFC_BGR101111_FLOAT', 'EFC_BGR565', + 'EFC_CbYCrY10101010_422_PACKED', 'EFC_CbYCrY12121212_422_PACKED', + 'EFC_CbYCrY8888_422_PACKED', 'EFC_CrYCbA1010102', + 'EFC_CrYCbA16161616_10LSB', 'EFC_CrYCbA16161616_10MSB', + 'EFC_CrYCbA16161616_12LSB', 'EFC_CrYCbA16161616_12MSB', + 'EFC_CrYCbA8888', 'EFC_CrYCbY10101010_422_PACKED', + 'EFC_CrYCbY12121212_422_PACKED', 'EFC_CrYCbY8888_422_PACKED', + 'EFC_MONO_10LSB', 'EFC_MONO_10MSB', 'EFC_MONO_12LSB', + 'EFC_MONO_12MSB', 'EFC_MONO_16', 'EFC_MONO_8', + 'EFC_RGB111110_FIX', 'EFC_RGB111110_FLOAT', 'EFC_RGB565', + 'EFC_RGBA1010102', 'EFC_RGBA16161616_10LSB', + 'EFC_RGBA16161616_10MSB', 'EFC_RGBA16161616_12LSB', + 'EFC_RGBA16161616_12MSB', 'EFC_RGBA16161616_FLOAT', + 'EFC_RGBA16161616_SNORM', 'EFC_RGBA16161616_UNORM', + 'EFC_RGBA4444', 'EFC_RGBA5551', 'EFC_RGBA8888', + 'EFC_SURFACE_PIXEL_FORMAT', 'EFC_Y10_CbCr1010_420_PLANAR', + 'EFC_Y10_CrCb1010_420_PLANAR', 'EFC_Y12_CbCr1212_420_PLANAR', + 'EFC_Y12_CrCb1212_420_PLANAR', 'EFC_Y8_CbCr88_420_PLANAR', + 'EFC_Y8_CrCb88_420_PLANAR', 'EFC_YCbYCr10101010_422_PACKED', + 'EFC_YCbYCr12121212_422_PACKED', 'EFC_YCbYCr8888_422_PACKED', + 'EFC_YCrCbA16161616_10LSB', 'EFC_YCrCbA16161616_10MSB', + 'EFC_YCrCbA16161616_12LSB', 'EFC_YCrCbA16161616_12MSB', + 'EFC_YCrCbA8888', 'EFC_YCrYCb10101010_422_PACKED', + 'EFC_YCrYCb12121212_422_PACKED', 'EFC_YCrYCb8888_422_PACKED', + 'ENABLE', 'ENABLE_AMCLK0', 'ENABLE_AMCLK1', 'ENABLE_CLOCK', + 'ENABLE_DEBUG', 'ENABLE_ENUM', 'ENABLE_ENUM_DISABLED', + 'ENABLE_ENUM_ENABLED', 'ENABLE_JITTER_REMOVAL', + 'ENABLE_LEGACY_PIPELINE', 'ENABLE_MEM_PWR_CTRL', + 'ENABLE_NGG_PIPELINE', 'ENABLE_PWL', 'ENABLE_TF0_OPT', + 'ENABLE_TF1_OPT', 'ENABLE_THE_FEATURE', 'ENABLE_THE_FUNC_CLOCK', + 'ENABLE_THE_INTERRUPT', 'ENABLE_THE_REFCLK', 'END_OF_PIPE_IB_END', + 'END_OF_PIPE_INCR_DE', 'END_OF_ROW_MODE', 'ENUM_DCN_ACTIVE', + 'ENUM_DCN_NOT_ACTIVE', 'ENUM_DIO_DCN_ACTIVE_STATUS', + 'ENUM_DPG_BIT_DEPTH', 'ENUM_DPG_BIT_DEPTH_10BPC', + 'ENUM_DPG_BIT_DEPTH_12BPC', 'ENUM_DPG_BIT_DEPTH_6BPC', + 'ENUM_DPG_BIT_DEPTH_8BPC', 'ENUM_DPG_DISABLE', + 'ENUM_DPG_DYNAMIC_RANGE', 'ENUM_DPG_DYNAMIC_RANGE_CEA', + 'ENUM_DPG_DYNAMIC_RANGE_VESA', 'ENUM_DPG_EN', 'ENUM_DPG_ENABLE', + 'ENUM_DPG_FIELD_POLARITY', + 'ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD', + 'ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN', 'ENUM_DPG_MODE', + 'ENUM_DPG_MODE_HORIZONTAL_BAR', 'ENUM_DPG_MODE_RGB_COLOUR_BLOCK', + 'ENUM_DPG_MODE_RGB_DUAL_RAMP', 'ENUM_DPG_MODE_RGB_SINGLE_RAMP', + 'ENUM_DPG_MODE_RGB_XR_BIAS', 'ENUM_DPG_MODE_VERTICAL_BAR', + 'ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK', + 'ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK', + 'ENUM_DP_DPHY_SYM32_CRC_END_EVENT', + 'ENUM_DP_DPHY_SYM32_CRC_START_EVENT', + 'ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE', + 'ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS', + 'ENUM_DP_DPHY_SYM32_ENABLE', 'ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE', + 'ENUM_DP_DPHY_SYM32_MODE', 'ENUM_DP_DPHY_SYM32_NUM_LANES', + 'ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING', + 'ENUM_DP_DPHY_SYM32_RESET', 'ENUM_DP_DPHY_SYM32_RESET_STATUS', + 'ENUM_DP_DPHY_SYM32_SAT_UPDATE', + 'ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING', + 'ENUM_DP_DPHY_SYM32_STATUS', + 'ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE', + 'ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE', + 'ENUM_DP_DPHY_SYM32_TP_PRBS_SEL', 'ENUM_DP_DPHY_SYM32_TP_SELECT', + 'ENUM_DP_SYM32_ENC_AUDIO_MUTE', + 'ENUM_DP_SYM32_ENC_CONTINUOUS_MODE', + 'ENUM_DP_SYM32_ENC_CRC_VALID', + 'ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH', + 'ENUM_DP_SYM32_ENC_ENABLE', + 'ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED', + 'ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION', + 'ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE', + 'ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING', + 'ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM', + 'ENUM_DP_SYM32_ENC_OVERFLOW_STATUS', 'ENUM_DP_SYM32_ENC_PENDING', + 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING', + 'ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE', + 'ENUM_DP_SYM32_ENC_POWER_STATE_ENUM', 'ENUM_DP_SYM32_ENC_RESET', + 'ENUM_DP_SYM32_ENC_SDP_PRIORITY', + 'ENUM_DP_SYM32_ENC_SOF_REFERENCE', + 'ENUM_DP_SYM32_ENC_VID_STREAM_DEFER', 'ENUM_DSCRM_DISABLE', + 'ENUM_DSCRM_EN', 'ENUM_DSCRM_ENABLE', 'ENUM_NUM_SIMD_PER_CU', + 'ES_STAGE_DS', 'ES_STAGE_OFF', 'ES_STAGE_REAL', 'EXOKAY', + 'EXPANSION_MODE', 'EXPANSION_MODE_CONSERVATIVE', + 'EXPANSION_MODE_OPTIMAL', 'EXPANSION_MODE_ZERO', + 'EXPORT_2C_32BPC_AR', 'EXPORT_2C_32BPC_GR', 'EXPORT_4C_16BPC', + 'EXPORT_4C_32BPC', 'EXPORT_ANY_Z', 'EXPORT_GREATER_THAN_Z', + 'EXPORT_LESS_THAN_Z', 'EXPORT_RESERVED', 'F32_MES_PM4_PACKETS_H', + 'FAULT_FAIL', 'FAULT_ONE', 'FAULT_PASS', 'FAULT_ZERO', + 'FC_EYE_SELECTION_ENUM', 'FC_EYE_SELECTION_LEFT_EYE', + 'FC_EYE_SELECTION_RIGHT_EYE', 'FC_EYE_SELECTION_STEREO_DIS', + 'FC_FRAME_CAPTURE_RATE_ENUM', 'FC_FRAME_CAPTURE_RATE_FULL', + 'FC_FRAME_CAPTURE_RATE_HALF', 'FC_FRAME_CAPTURE_RATE_QUARTER', + 'FC_FRAME_CAPTURE_RATE_THIRD', 'FC_STEREO_EYE_POLARITY_ENUM', + 'FC_STEREO_EYE_POLARITY_LEFT', 'FC_STEREO_EYE_POLARITY_RIGHT', + 'FEC_ACTIVE_STATUS', 'FIX_S2_13', 'FIX_S3_12', 'FLIP_ANY_FRAME', + 'FLIP_LEFT_EYE', 'FLIP_RATE', 'FLIP_RATE_0', 'FLIP_RATE_1', + 'FLIP_RATE_2', 'FLIP_RATE_3', 'FLIP_RATE_4', 'FLIP_RATE_5', + 'FLIP_RATE_6', 'FLIP_RATE_7', 'FLIP_RIGHT_EYE', + 'FLUSH_AND_INV_CB_DATA_TS', 'FLUSH_AND_INV_CB_META', + 'FLUSH_AND_INV_CB_PIXEL_DATA', 'FLUSH_AND_INV_DB_DATA_TS', + 'FLUSH_AND_INV_DB_META', 'FLUSH_CONTROL_FLUSH_NOT_STARTED', + 'FLUSH_CONTROL_FLUSH_STARTED', 'FLUSH_DFSM', 'FLUSH_ES_OUTPUT', + 'FLUSH_HS_OUTPUT', 'FLUSH_SX_TS', 'FMTMEM_DISABLE_MEM_PWR_CTRL', + 'FMTMEM_ENABLE_MEM_PWR_CTRL', 'FMTMEM_FORCE_DEEP_SLEEP_REQUEST', + 'FMTMEM_FORCE_LIGHT_SLEEP_REQUEST', + 'FMTMEM_FORCE_SHUT_DOWN_REQUEST', 'FMTMEM_NO_FORCE_REQUEST', + 'FMTMEM_PWR_DIS_CTRL', 'FMTMEM_PWR_FORCE_CTRL', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi', + 'FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C', + 'FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G', + 'FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2', + 'FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING', + 'FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION', + 'FMT_CLAMP_CNTL_COLOR_FORMAT', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2', + 'FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE', + 'FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE', + 'FMT_CONTROL_PIXEL_ENCODING', + 'FMT_CONTROL_PIXEL_ENCODING_RESERVED', + 'FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR420', + 'FMT_CONTROL_PIXEL_ENCODING_YCBCR422', + 'FMT_CONTROL_SUBSAMPLING_MODE', + 'FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE', + 'FMT_CONTROL_SUBSAMPLING_MODE_DROP', + 'FMT_CONTROL_SUBSAMPLING_MOME_3_TAP', + 'FMT_CONTROL_SUBSAMPLING_MOME_RESERVED', + 'FMT_CONTROL_SUBSAMPLING_ORDER', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR', + 'FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB', + 'FMT_DEBUG_CNTL_COLOR_SELECT', 'FMT_DEBUG_CNTL_COLOR_SELECT_BLUE', + 'FMT_DEBUG_CNTL_COLOR_SELECT_GREEN', + 'FMT_DEBUG_CNTL_COLOR_SELECT_RED1', + 'FMT_DEBUG_CNTL_COLOR_SELECT_RED2', 'FMT_DYNAMIC_EXP_MODE', + 'FMT_DYNAMIC_EXP_MODE_10to12', 'FMT_DYNAMIC_EXP_MODE_8to12', + 'FMT_FRAME_RANDOM_ENABLE_CONTROL', + 'FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME', + 'FMT_FRAME_RANDOM_ENABLE_RESET_ONCE', 'FMT_POWER_STATE_ENUM', + 'FMT_POWER_STATE_ENUM_DS', 'FMT_POWER_STATE_ENUM_LS', + 'FMT_POWER_STATE_ENUM_ON', 'FMT_POWER_STATE_ENUM_SD', + 'FMT_RGB_RANDOM_ENABLE_CONTROL', + 'FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE', + 'FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP', + 'FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED', + 'FMT_SPATIAL_DITHER_MODE', 'FMT_SPATIAL_DITHER_MODE_0', + 'FMT_SPATIAL_DITHER_MODE_1', 'FMT_SPATIAL_DITHER_MODE_2', + 'FMT_SPATIAL_DITHER_MODE_3', 'FMT_STEREOSYNC_OVERRIDE_CONTROL', + 'FMT_STEREOSYNC_OVERRIDE_CONTROL_0', + 'FMT_STEREOSYNC_OVERRIDE_CONTROL_1', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR', + 'FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB', 'FORCE_00', + 'FORCE_BINNING_ON', 'FORCE_DEEP_SLEEP_REQUEST', 'FORCE_DISABLE', + 'FORCE_DISABLE_CLOCK', 'FORCE_EARLY_Z', 'FORCE_ENABLE', + 'FORCE_FF', 'FORCE_LATE_Z', 'FORCE_LIGHT_SLEEP_REQ', + 'FORCE_LIGHT_SLEEP_REQUEST', 'FORCE_OFF', + 'FORCE_ONE_ROW_FOR_FRAME', 'FORCE_ONE_ROW_FOR_FRAME_0', + 'FORCE_ONE_ROW_FOR_FRAME_1', 'FORCE_OPT_AUTO', + 'FORCE_OPT_DISABLE', 'FORCE_OPT_ENABLE_IF_SRC_ARGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_ARGB_1', 'FORCE_OPT_ENABLE_IF_SRC_A_0', + 'FORCE_OPT_ENABLE_IF_SRC_A_1', 'FORCE_OPT_ENABLE_IF_SRC_RGB_0', + 'FORCE_OPT_ENABLE_IF_SRC_RGB_1', 'FORCE_RESERVED', 'FORCE_RE_Z', + 'FORCE_SENT', 'FORCE_SHUT_DOWN_REQUEST', 'FORCE_SUMM_BOTH', + 'FORCE_SUMM_MAXZ', 'FORCE_SUMM_MINZ', 'FORCE_SUMM_OFF', + 'FORCE_THE_CLOCK_DISABLED', 'FORMAT_CROSSBAR', + 'FORMAT_CROSSBAR_B', 'FORMAT_CROSSBAR_G', 'FORMAT_CROSSBAR_R', + 'FRAG_ALWAYS', 'FRAG_EQUAL', 'FRAG_GEQUAL', 'FRAG_GREATER', + 'FRAG_LEQUAL', 'FRAG_LESS', 'FRAG_NEVER', 'FRAG_NOTEQUAL', + 'FRAME_TMZ', 'FUSE_BASE', 'FUSE_BASE__INST0_SEG0', + 'FUSE_BASE__INST0_SEG1', 'FUSE_BASE__INST0_SEG2', + 'FUSE_BASE__INST0_SEG3', 'FUSE_BASE__INST0_SEG4', + 'FUSE_BASE__INST1_SEG0', 'FUSE_BASE__INST1_SEG1', + 'FUSE_BASE__INST1_SEG2', 'FUSE_BASE__INST1_SEG3', + 'FUSE_BASE__INST1_SEG4', 'FUSE_BASE__INST2_SEG0', + 'FUSE_BASE__INST2_SEG1', 'FUSE_BASE__INST2_SEG2', + 'FUSE_BASE__INST2_SEG3', 'FUSE_BASE__INST2_SEG4', + 'FUSE_BASE__INST3_SEG0', 'FUSE_BASE__INST3_SEG1', + 'FUSE_BASE__INST3_SEG2', 'FUSE_BASE__INST3_SEG3', + 'FUSE_BASE__INST3_SEG4', 'FUSE_BASE__INST4_SEG0', + 'FUSE_BASE__INST4_SEG1', 'FUSE_BASE__INST4_SEG2', + 'FUSE_BASE__INST4_SEG3', 'FUSE_BASE__INST4_SEG4', + 'FUSE_BASE__INST5_SEG0', 'FUSE_BASE__INST5_SEG1', + 'FUSE_BASE__INST5_SEG2', 'FUSE_BASE__INST5_SEG3', + 'FUSE_BASE__INST5_SEG4', 'FUSE_BASE__INST6_SEG0', + 'FUSE_BASE__INST6_SEG1', 'FUSE_BASE__INST6_SEG2', + 'FUSE_BASE__INST6_SEG3', 'FUSE_BASE__INST6_SEG4', 'ForceControl', + 'GAMUT_COEF', 'GAMUT_COEF_B', 'GATCL1RequestType', + 'GATCL1_TYPE_BYPASS', 'GATCL1_TYPE_NORMAL', + 'GATCL1_TYPE_SHOOTDOWN', 'GB_EDC_DED_MODE', + 'GB_EDC_DED_MODE_HALT', 'GB_EDC_DED_MODE_INT_HALT', + 'GB_EDC_DED_MODE_LOG', 'GB_TILING_CONFIG_MACROTABLE_SIZE', + 'GB_TILING_CONFIG_TABLE_SIZE', 'GCRPerfSel', + 'GCR_PERF_SEL_ALL_REQ', + 'GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ', + 'GCR_PERF_SEL_CPC_ALL_REQ', 'GCR_PERF_SEL_CPC_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPC_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPC_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPC_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPC_METADATA_REQ', + 'GCR_PERF_SEL_CPC_SQC_DATA_REQ', 'GCR_PERF_SEL_CPC_SQC_INST_REQ', + 'GCR_PERF_SEL_CPC_TCP_REQ', + 'GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_CPF_ALL_REQ', 'GCR_PERF_SEL_CPF_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPF_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPF_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPF_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPF_METADATA_REQ', + 'GCR_PERF_SEL_CPF_SQC_DATA_REQ', 'GCR_PERF_SEL_CPF_SQC_INST_REQ', + 'GCR_PERF_SEL_CPF_TCP_REQ', + 'GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_CPG_ALL_REQ', 'GCR_PERF_SEL_CPG_GL1_ALL_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPG_GL1_RANGE_REQ', 'GCR_PERF_SEL_CPG_GL2_ALL_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_CPG_GL2_RANGE_REQ', 'GCR_PERF_SEL_CPG_METADATA_REQ', + 'GCR_PERF_SEL_CPG_SQC_DATA_REQ', 'GCR_PERF_SEL_CPG_SQC_INST_REQ', + 'GCR_PERF_SEL_CPG_TCP_REQ', + 'GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ', 'GCR_PERF_SEL_NONE', + 'GCR_PERF_SEL_PHY_REQ', 'GCR_PERF_SEL_PIO_ALL_REQ', + 'GCR_PERF_SEL_PIO_GL1_ALL_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PIO_GL1_RANGE_REQ', 'GCR_PERF_SEL_PIO_GL2_ALL_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PIO_GL2_RANGE_REQ', 'GCR_PERF_SEL_PIO_METADATA_REQ', + 'GCR_PERF_SEL_PIO_SQC_DATA_REQ', 'GCR_PERF_SEL_PIO_SQC_INST_REQ', + 'GCR_PERF_SEL_PIO_TCP_REQ', + 'GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_PM_ALL_REQ', 'GCR_PERF_SEL_PM_GL1_ALL_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PM_GL1_RANGE_REQ', 'GCR_PERF_SEL_PM_GL2_ALL_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_PM_GL2_RANGE_REQ', 'GCR_PERF_SEL_PM_METADATA_REQ', + 'GCR_PERF_SEL_PM_SQC_DATA_REQ', 'GCR_PERF_SEL_PM_SQC_INST_REQ', + 'GCR_PERF_SEL_PM_TCP_REQ', + 'GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_RLC_ALL_REQ', 'GCR_PERF_SEL_RLC_GL1_ALL_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_RLC_GL1_RANGE_REQ', 'GCR_PERF_SEL_RLC_GL2_ALL_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_RLC_GL2_RANGE_REQ', 'GCR_PERF_SEL_RLC_METADATA_REQ', + 'GCR_PERF_SEL_RLC_SQC_DATA_REQ', 'GCR_PERF_SEL_RLC_SQC_INST_REQ', + 'GCR_PERF_SEL_RLC_TCP_REQ', + 'GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_SDMA0_ALL_REQ', 'GCR_PERF_SEL_SDMA0_GL1_ALL_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_ALL_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ', + 'GCR_PERF_SEL_SDMA0_METADATA_REQ', + 'GCR_PERF_SEL_SDMA0_SQC_DATA_REQ', + 'GCR_PERF_SEL_SDMA0_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA0_TCP_REQ', + 'GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_SDMA1_ALL_REQ', 'GCR_PERF_SEL_SDMA1_GL1_ALL_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_ALL_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ', + 'GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ', + 'GCR_PERF_SEL_SDMA1_METADATA_REQ', + 'GCR_PERF_SEL_SDMA1_SQC_DATA_REQ', + 'GCR_PERF_SEL_SDMA1_SQC_INST_REQ', 'GCR_PERF_SEL_SDMA1_TCP_REQ', + 'GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ', + 'GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ', + 'GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ', + 'GCR_PERF_SEL_UTCL2_FILTERED_RET', + 'GCR_PERF_SEL_UTCL2_INFLIGHT_REQ', + 'GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT', + 'GCR_PERF_SEL_UTCL2_REQ', 'GCR_PERF_SEL_UTCL2_RET', + 'GCR_PERF_SEL_VIRT_REQ', 'GC_BASE', 'GC_BASE__INST0_SEG0', 'GC_BASE__INST0_SEG1', 'GC_BASE__INST0_SEG2', 'GC_BASE__INST0_SEG3', 'GC_BASE__INST0_SEG4', 'GC_BASE__INST1_SEG0', 'GC_BASE__INST1_SEG1', @@ -13963,25 +64833,712 @@ __all__ = \ 'GC_BASE__INST5_SEG2', 'GC_BASE__INST5_SEG3', 'GC_BASE__INST5_SEG4', 'GC_BASE__INST6_SEG0', 'GC_BASE__INST6_SEG1', 'GC_BASE__INST6_SEG2', - 'GC_BASE__INST6_SEG3', 'GC_BASE__INST6_SEG4', 'HDA_BASE', - 'HDA_BASE__INST0_SEG0', 'HDA_BASE__INST0_SEG1', - 'HDA_BASE__INST0_SEG2', 'HDA_BASE__INST0_SEG3', - 'HDA_BASE__INST0_SEG4', 'HDA_BASE__INST1_SEG0', - 'HDA_BASE__INST1_SEG1', 'HDA_BASE__INST1_SEG2', - 'HDA_BASE__INST1_SEG3', 'HDA_BASE__INST1_SEG4', - 'HDA_BASE__INST2_SEG0', 'HDA_BASE__INST2_SEG1', - 'HDA_BASE__INST2_SEG2', 'HDA_BASE__INST2_SEG3', - 'HDA_BASE__INST2_SEG4', 'HDA_BASE__INST3_SEG0', - 'HDA_BASE__INST3_SEG1', 'HDA_BASE__INST3_SEG2', - 'HDA_BASE__INST3_SEG3', 'HDA_BASE__INST3_SEG4', - 'HDA_BASE__INST4_SEG0', 'HDA_BASE__INST4_SEG1', - 'HDA_BASE__INST4_SEG2', 'HDA_BASE__INST4_SEG3', - 'HDA_BASE__INST4_SEG4', 'HDA_BASE__INST5_SEG0', - 'HDA_BASE__INST5_SEG1', 'HDA_BASE__INST5_SEG2', - 'HDA_BASE__INST5_SEG3', 'HDA_BASE__INST5_SEG4', - 'HDA_BASE__INST6_SEG0', 'HDA_BASE__INST6_SEG1', - 'HDA_BASE__INST6_SEG2', 'HDA_BASE__INST6_SEG3', - 'HDA_BASE__INST6_SEG4', 'HDP_BASE', 'HDP_BASE__INST0_SEG0', + 'GC_BASE__INST6_SEG3', 'GC_BASE__INST6_SEG4', + 'GDS_PERFCOUNT_SELECT', 'GDS_PERF_SEL_GWS_BYPASS', + 'GDS_PERF_SEL_GWS_RELEASED', 'GDS_PERF_SEL_SE0_2COMP_REQ', + 'GDS_PERF_SEL_SE0_GDS_ATOM_OP', 'GDS_PERF_SEL_SE0_GDS_BYTE_OP', + 'GDS_PERF_SEL_SE0_GDS_CMPXCH_OP', 'GDS_PERF_SEL_SE0_GDS_RD_OP', + 'GDS_PERF_SEL_SE0_GDS_REL_OP', 'GDS_PERF_SEL_SE0_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE0_GDS_WR_OP', + 'GDS_PERF_SEL_SE0_NORET', 'GDS_PERF_SEL_SE0_ORD_CNT', + 'GDS_PERF_SEL_SE0_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE0_RET', + 'GDS_PERF_SEL_SE1_2COMP_REQ', 'GDS_PERF_SEL_SE1_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE1_GDS_BYTE_OP', 'GDS_PERF_SEL_SE1_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE1_GDS_RD_OP', 'GDS_PERF_SEL_SE1_GDS_REL_OP', + 'GDS_PERF_SEL_SE1_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE1_GDS_WR_OP', + 'GDS_PERF_SEL_SE1_NORET', 'GDS_PERF_SEL_SE1_ORD_CNT', + 'GDS_PERF_SEL_SE1_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE1_RET', + 'GDS_PERF_SEL_SE2_2COMP_REQ', 'GDS_PERF_SEL_SE2_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE2_GDS_BYTE_OP', 'GDS_PERF_SEL_SE2_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE2_GDS_RD_OP', 'GDS_PERF_SEL_SE2_GDS_REL_OP', + 'GDS_PERF_SEL_SE2_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE2_GDS_WR_OP', + 'GDS_PERF_SEL_SE2_NORET', 'GDS_PERF_SEL_SE2_ORD_CNT', + 'GDS_PERF_SEL_SE2_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE2_RET', + 'GDS_PERF_SEL_SE3_2COMP_REQ', 'GDS_PERF_SEL_SE3_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE3_GDS_BYTE_OP', 'GDS_PERF_SEL_SE3_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE3_GDS_RD_OP', 'GDS_PERF_SEL_SE3_GDS_REL_OP', + 'GDS_PERF_SEL_SE3_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE3_GDS_WR_OP', + 'GDS_PERF_SEL_SE3_NORET', 'GDS_PERF_SEL_SE3_ORD_CNT', + 'GDS_PERF_SEL_SE3_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE3_RET', + 'GDS_PERF_SEL_SE4_2COMP_REQ', 'GDS_PERF_SEL_SE4_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE4_GDS_BYTE_OP', 'GDS_PERF_SEL_SE4_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE4_GDS_RD_OP', 'GDS_PERF_SEL_SE4_GDS_REL_OP', + 'GDS_PERF_SEL_SE4_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE4_GDS_WR_OP', + 'GDS_PERF_SEL_SE4_NORET', 'GDS_PERF_SEL_SE4_ORD_CNT', + 'GDS_PERF_SEL_SE4_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE4_RET', + 'GDS_PERF_SEL_SE5_2COMP_REQ', 'GDS_PERF_SEL_SE5_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE5_GDS_BYTE_OP', 'GDS_PERF_SEL_SE5_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE5_GDS_RD_OP', 'GDS_PERF_SEL_SE5_GDS_REL_OP', + 'GDS_PERF_SEL_SE5_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE5_GDS_WR_OP', + 'GDS_PERF_SEL_SE5_NORET', 'GDS_PERF_SEL_SE5_ORD_CNT', + 'GDS_PERF_SEL_SE5_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE5_RET', + 'GDS_PERF_SEL_SE6_2COMP_REQ', 'GDS_PERF_SEL_SE6_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE6_GDS_BYTE_OP', 'GDS_PERF_SEL_SE6_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE6_GDS_RD_OP', 'GDS_PERF_SEL_SE6_GDS_REL_OP', + 'GDS_PERF_SEL_SE6_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE6_GDS_WR_OP', + 'GDS_PERF_SEL_SE6_NORET', 'GDS_PERF_SEL_SE6_ORD_CNT', + 'GDS_PERF_SEL_SE6_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE6_RET', + 'GDS_PERF_SEL_SE7_2COMP_REQ', 'GDS_PERF_SEL_SE7_GDS_ATOM_OP', + 'GDS_PERF_SEL_SE7_GDS_BYTE_OP', 'GDS_PERF_SEL_SE7_GDS_CMPXCH_OP', + 'GDS_PERF_SEL_SE7_GDS_RD_OP', 'GDS_PERF_SEL_SE7_GDS_REL_OP', + 'GDS_PERF_SEL_SE7_GDS_SHORT_OP', + 'GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD', 'GDS_PERF_SEL_SE7_GDS_WR_OP', + 'GDS_PERF_SEL_SE7_NORET', 'GDS_PERF_SEL_SE7_ORD_CNT', + 'GDS_PERF_SEL_SE7_ORD_WAVE_VALID', 'GDS_PERF_SEL_SE7_RET', + 'GDS_PERF_SEL_WBUF_WR', 'GDS_PERF_SEL_WR_COMP', + 'GE1_PERFCOUNT_SELECT', 'GE2_DIST_PERFCOUNT_SELECT', + 'GE2_SE_PERFCOUNT_SELECT', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET', + 'GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED', + 'GENERIC_STEREOSYNC_SEL', 'GENERIC_STEREOSYNC_SEL_D1', + 'GENERIC_STEREOSYNC_SEL_D2', 'GENERIC_STEREOSYNC_SEL_D3', + 'GENERIC_STEREOSYNC_SEL_D4', 'GENERIC_STEREOSYNC_SEL_RESERVED', + 'GEN_ONE', 'GEN_RESERVED', 'GEN_TWO', 'GEN_ZERO', + 'GL0V_CACHE_POLICIES', 'GL0V_CACHE_POLICY_HIT_EVICT', + 'GL0V_CACHE_POLICY_HIT_LRU', 'GL0V_CACHE_POLICY_MISS_EVICT', + 'GL0V_CACHE_POLICY_MISS_LRU', 'GL1A_PERF_SEL', + 'GL1A_PERF_SEL_ARB_REQUESTS', 'GL1A_PERF_SEL_BURST_COUNT_GL1C0', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C1', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C2', + 'GL1A_PERF_SEL_BURST_COUNT_GL1C3', 'GL1A_PERF_SEL_BUSY', + 'GL1A_PERF_SEL_CYCLE', 'GL1A_PERF_SEL_REQUEST_GL1C0', + 'GL1A_PERF_SEL_REQUEST_GL1C1', 'GL1A_PERF_SEL_REQUEST_GL1C2', + 'GL1A_PERF_SEL_REQUEST_GL1C3', 'GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL', + 'GL1A_PERF_SEL_STALL_GL1C0', 'GL1A_PERF_SEL_STALL_GL1C1', + 'GL1A_PERF_SEL_STALL_GL1C2', 'GL1A_PERF_SEL_STALL_GL1C3', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2', + 'GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3', + 'GL1A_PERF_SEL_WDS_32B_GL1C0', 'GL1A_PERF_SEL_WDS_32B_GL1C1', + 'GL1A_PERF_SEL_WDS_32B_GL1C2', 'GL1A_PERF_SEL_WDS_32B_GL1C3', + 'GL1C_PERF_SEL', 'GL1C_PERF_SEL_ARB_RET_LEVEL', + 'GL1C_PERF_SEL_BUSY', 'GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT', + 'GL1C_PERF_SEL_CYCLE', 'GL1C_PERF_SEL_GL2_REQ_PREFETCH', + 'GL1C_PERF_SEL_GL2_REQ_READ', 'GL1C_PERF_SEL_GL2_REQ_READ_128B', + 'GL1C_PERF_SEL_GL2_REQ_READ_32B', + 'GL1C_PERF_SEL_GL2_REQ_READ_64B', + 'GL1C_PERF_SEL_GL2_REQ_READ_LATENCY', + 'GL1C_PERF_SEL_GL2_REQ_WRITE', 'GL1C_PERF_SEL_GL2_REQ_WRITE_32B', + 'GL1C_PERF_SEL_GL2_REQ_WRITE_64B', + 'GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY', 'GL1C_PERF_SEL_REQ', + 'GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET', + 'GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET', 'GL1C_PERF_SEL_REQ_CLIENT0', + 'GL1C_PERF_SEL_REQ_CLIENT1', 'GL1C_PERF_SEL_REQ_CLIENT10', + 'GL1C_PERF_SEL_REQ_CLIENT11', 'GL1C_PERF_SEL_REQ_CLIENT12', + 'GL1C_PERF_SEL_REQ_CLIENT13', 'GL1C_PERF_SEL_REQ_CLIENT14', + 'GL1C_PERF_SEL_REQ_CLIENT15', 'GL1C_PERF_SEL_REQ_CLIENT16', + 'GL1C_PERF_SEL_REQ_CLIENT17', 'GL1C_PERF_SEL_REQ_CLIENT18', + 'GL1C_PERF_SEL_REQ_CLIENT19', 'GL1C_PERF_SEL_REQ_CLIENT2', + 'GL1C_PERF_SEL_REQ_CLIENT20', 'GL1C_PERF_SEL_REQ_CLIENT21', + 'GL1C_PERF_SEL_REQ_CLIENT22', 'GL1C_PERF_SEL_REQ_CLIENT23', + 'GL1C_PERF_SEL_REQ_CLIENT24', 'GL1C_PERF_SEL_REQ_CLIENT25', + 'GL1C_PERF_SEL_REQ_CLIENT26', 'GL1C_PERF_SEL_REQ_CLIENT27', + 'GL1C_PERF_SEL_REQ_CLIENT3', 'GL1C_PERF_SEL_REQ_CLIENT4', + 'GL1C_PERF_SEL_REQ_CLIENT5', 'GL1C_PERF_SEL_REQ_CLIENT6', + 'GL1C_PERF_SEL_REQ_CLIENT7', 'GL1C_PERF_SEL_REQ_CLIENT8', + 'GL1C_PERF_SEL_REQ_CLIENT9', 'GL1C_PERF_SEL_REQ_MISS', + 'GL1C_PERF_SEL_REQ_NOP_ACK', 'GL1C_PERF_SEL_REQ_NOP_RTN0', + 'GL1C_PERF_SEL_REQ_READ', 'GL1C_PERF_SEL_REQ_READ_128B', + 'GL1C_PERF_SEL_REQ_READ_32B', 'GL1C_PERF_SEL_REQ_READ_64B', + 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT', + 'GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU', + 'GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT', + 'GL1C_PERF_SEL_REQ_SHADER_INV', 'GL1C_PERF_SEL_REQ_WRITE', + 'GL1C_PERF_SEL_REQ_WRITE_32B', 'GL1C_PERF_SEL_REQ_WRITE_64B', + 'GL1C_PERF_SEL_STALL_GCR_INV', 'GL1C_PERF_SEL_STALL_GL2_GL1', + 'GL1C_PERF_SEL_STALL_LFIFO_FULL', + 'GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE', + 'GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC', + 'GL1C_PERF_SEL_STALL_VM', 'GL1C_PERF_SEL_STARVE', + 'GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ', + 'GL1C_PERF_SEL_UTCL0_LFIFO_FULL', + 'GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS', + 'GL1C_PERF_SEL_UTCL0_PERMISSION_MISS', + 'GL1C_PERF_SEL_UTCL0_REQUEST', + 'GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX', + 'GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES', + 'GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT', + 'GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL', + 'GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS', + 'GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS', + 'GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT', + 'GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS', + 'GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT', + 'GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT', + 'GL1H_REQ_PERF_SEL', 'GL1H_REQ_PERF_SEL_ARB_REQUESTS', + 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0', + 'GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1', 'GL1H_REQ_PERF_SEL_BUSY', + 'GL1H_REQ_PERF_SEL_CYCLE', 'GL1H_REQ_PERF_SEL_REQUEST_GL1_0', + 'GL1H_REQ_PERF_SEL_REQUEST_GL1_1', + 'GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL', + 'GL1H_REQ_PERF_SEL_STALL_GL1_0', 'GL1H_REQ_PERF_SEL_STALL_GL1_1', + 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_0', + 'GL1H_REQ_PERF_SEL_WDS_32B_GL1_1', 'GL1_CACHE_POLICIES', + 'GL1_CACHE_POLICY_HIT_EVICT', 'GL1_CACHE_POLICY_HIT_LRU', + 'GL1_CACHE_POLICY_MISS_EVICT', 'GL1_CACHE_POLICY_MISS_LRU', + 'GL1_CACHE_STORE_POLICIES', 'GL1_CACHE_STORE_POLICY_BYPASS', + 'GL2A_PERF_SEL', 'GL2A_PERF_SEL_BUSY', 'GL2A_PERF_SEL_CYCLE', + 'GL2A_PERF_SEL_NONE', 'GL2A_PERF_SEL_REQ_BURST_CLIENT0', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT1', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT10', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT11', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT12', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT13', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT14', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT15', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT2', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT3', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT4', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT5', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT6', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT7', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT8', + 'GL2A_PERF_SEL_REQ_BURST_CLIENT9', + 'GL2A_PERF_SEL_REQ_BURST_GL2C0', 'GL2A_PERF_SEL_REQ_BURST_GL2C1', + 'GL2A_PERF_SEL_REQ_BURST_GL2C2', 'GL2A_PERF_SEL_REQ_BURST_GL2C3', + 'GL2A_PERF_SEL_REQ_BURST_GL2C4', 'GL2A_PERF_SEL_REQ_BURST_GL2C5', + 'GL2A_PERF_SEL_REQ_BURST_GL2C6', 'GL2A_PERF_SEL_REQ_BURST_GL2C7', + 'GL2A_PERF_SEL_REQ_GL2C0', 'GL2A_PERF_SEL_REQ_GL2C1', + 'GL2A_PERF_SEL_REQ_GL2C2', 'GL2A_PERF_SEL_REQ_GL2C3', + 'GL2A_PERF_SEL_REQ_GL2C4', 'GL2A_PERF_SEL_REQ_GL2C5', + 'GL2A_PERF_SEL_REQ_GL2C6', 'GL2A_PERF_SEL_REQ_GL2C7', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6', + 'GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7', + 'GL2A_PERF_SEL_REQ_STALL_GL2C0', 'GL2A_PERF_SEL_REQ_STALL_GL2C1', + 'GL2A_PERF_SEL_REQ_STALL_GL2C2', 'GL2A_PERF_SEL_REQ_STALL_GL2C3', + 'GL2A_PERF_SEL_REQ_STALL_GL2C4', 'GL2A_PERF_SEL_REQ_STALL_GL2C5', + 'GL2A_PERF_SEL_REQ_STALL_GL2C6', 'GL2A_PERF_SEL_REQ_STALL_GL2C7', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8', + 'GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9', + 'GL2A_PERF_SEL_RTN_CLIENT0', 'GL2A_PERF_SEL_RTN_CLIENT1', + 'GL2A_PERF_SEL_RTN_CLIENT10', 'GL2A_PERF_SEL_RTN_CLIENT11', + 'GL2A_PERF_SEL_RTN_CLIENT12', 'GL2A_PERF_SEL_RTN_CLIENT13', + 'GL2A_PERF_SEL_RTN_CLIENT14', 'GL2A_PERF_SEL_RTN_CLIENT15', + 'GL2A_PERF_SEL_RTN_CLIENT2', 'GL2A_PERF_SEL_RTN_CLIENT3', + 'GL2A_PERF_SEL_RTN_CLIENT4', 'GL2A_PERF_SEL_RTN_CLIENT5', + 'GL2A_PERF_SEL_RTN_CLIENT6', 'GL2A_PERF_SEL_RTN_CLIENT7', + 'GL2A_PERF_SEL_RTN_CLIENT8', 'GL2A_PERF_SEL_RTN_CLIENT9', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8', + 'GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9', + 'GL2A_PERF_SEL_RTN_STALL_GL2C0', 'GL2A_PERF_SEL_RTN_STALL_GL2C1', + 'GL2A_PERF_SEL_RTN_STALL_GL2C2', 'GL2A_PERF_SEL_RTN_STALL_GL2C3', + 'GL2A_PERF_SEL_RTN_STALL_GL2C4', 'GL2A_PERF_SEL_RTN_STALL_GL2C5', + 'GL2A_PERF_SEL_RTN_STALL_GL2C6', 'GL2A_PERF_SEL_RTN_STALL_GL2C7', + 'GL2C_PERF_SEL', 'GL2C_PERF_SEL_ALL_GCR_INV_EVICT', + 'GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT', + 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE', + 'GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE', + 'GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK', + 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START', + 'GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START', + 'GL2C_PERF_SEL_ATOMIC', 'GL2C_PERF_SEL_BUBBLE', + 'GL2C_PERF_SEL_BUSY', 'GL2C_PERF_SEL_BYPASS_REQ', + 'GL2C_PERF_SEL_CLIENT0_REQ', 'GL2C_PERF_SEL_CLIENT10_REQ', + 'GL2C_PERF_SEL_CLIENT11_REQ', 'GL2C_PERF_SEL_CLIENT12_REQ', + 'GL2C_PERF_SEL_CLIENT13_REQ', 'GL2C_PERF_SEL_CLIENT14_REQ', + 'GL2C_PERF_SEL_CLIENT15_REQ', 'GL2C_PERF_SEL_CLIENT1_REQ', + 'GL2C_PERF_SEL_CLIENT2_REQ', 'GL2C_PERF_SEL_CLIENT3_REQ', + 'GL2C_PERF_SEL_CLIENT4_REQ', 'GL2C_PERF_SEL_CLIENT5_REQ', + 'GL2C_PERF_SEL_CLIENT6_REQ', 'GL2C_PERF_SEL_CLIENT7_REQ', + 'GL2C_PERF_SEL_CLIENT8_REQ', 'GL2C_PERF_SEL_CLIENT9_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL0_REQ', 'GL2C_PERF_SEL_CM_CHANNEL10_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL11_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL12_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL13_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL14_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL15_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL16_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL17_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL18_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL19_REQ', 'GL2C_PERF_SEL_CM_CHANNEL1_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL20_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL21_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL22_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL23_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL24_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL25_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL26_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL27_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL28_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL29_REQ', 'GL2C_PERF_SEL_CM_CHANNEL2_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL30_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL31_REQ', 'GL2C_PERF_SEL_CM_CHANNEL3_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL4_REQ', 'GL2C_PERF_SEL_CM_CHANNEL5_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL6_REQ', 'GL2C_PERF_SEL_CM_CHANNEL7_REQ', + 'GL2C_PERF_SEL_CM_CHANNEL8_REQ', 'GL2C_PERF_SEL_CM_CHANNEL9_REQ', + 'GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ', + 'GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ', + 'GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ', + 'GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ', + 'GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ', + 'GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ', + 'GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ', + 'GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ', + 'GL2C_PERF_SEL_CM_COMP_READ_REQ', + 'GL2C_PERF_SEL_CM_COMP_STENCIL_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ', + 'GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ', + 'GL2C_PERF_SEL_CM_DCC_IN_XFC', 'GL2C_PERF_SEL_CM_DCC_OUT_1x1', + 'GL2C_PERF_SEL_CM_DCC_OUT_1x2', 'GL2C_PERF_SEL_CM_DCC_OUT_2x1', + 'GL2C_PERF_SEL_CM_DCC_OUT_2x2', 'GL2C_PERF_SEL_CM_DCC_OUT_CONST', + 'GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP', 'GL2C_PERF_SEL_CM_DCC_OUT_XFC', + 'GL2C_PERF_SEL_CM_DCC_STALL', 'GL2C_PERF_SEL_CM_FULL_WRITE_REQ', + 'GL2C_PERF_SEL_CM_MERGE_BUF_FULL', + 'GL2C_PERF_SEL_CM_METADATA_WR_REQ', 'GL2C_PERF_SEL_CM_NOOP_REQ', + 'GL2C_PERF_SEL_CM_NO_ACK_REQ', 'GL2C_PERF_SEL_CM_READ_BACK_REQ', + 'GL2C_PERF_SEL_CM_RVF_FULL', 'GL2C_PERF_SEL_CM_SDR_FULL', + 'GL2C_PERF_SEL_CM_WR_ACK_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_0_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_128_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_32_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_64_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_96_REQ', + 'GL2C_PERF_SEL_COMPRESSED_READ_REQ', 'GL2C_PERF_SEL_CYCLE', + 'GL2C_PERF_SEL_C_RO_S_REQ', 'GL2C_PERF_SEL_C_RO_US_REQ', + 'GL2C_PERF_SEL_C_RW_S_REQ', 'GL2C_PERF_SEL_C_RW_US_REQ', + 'GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT', 'GL2C_PERF_SEL_EA_ATOMIC', + 'GL2C_PERF_SEL_EA_ATOMIC_LEVEL', 'GL2C_PERF_SEL_EA_OUTSTANDING', + 'GL2C_PERF_SEL_EA_RDREQ_128B', 'GL2C_PERF_SEL_EA_RDREQ_32B', + 'GL2C_PERF_SEL_EA_RDREQ_64B', 'GL2C_PERF_SEL_EA_RDREQ_96B', + 'GL2C_PERF_SEL_EA_RDREQ_DRAM', 'GL2C_PERF_SEL_EA_RDREQ_DRAM_32B', + 'GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_RDREQ_SNOOP', 'GL2C_PERF_SEL_EA_RDREQ_SPLIT', + 'GL2C_PERF_SEL_EA_RDRET_NACK', + 'GL2C_PERF_SEL_EA_RD_COMPRESSED_32B', + 'GL2C_PERF_SEL_EA_RD_MDC_32B', 'GL2C_PERF_SEL_EA_RD_UNCACHED_32B', + 'GL2C_PERF_SEL_EA_WRREQ_64B', 'GL2C_PERF_SEL_EA_WRREQ_DRAM', + 'GL2C_PERF_SEL_EA_WRREQ_DRAM_32B', + 'GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL', + 'GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND', + 'GL2C_PERF_SEL_EA_WRREQ_SNOOP', 'GL2C_PERF_SEL_EA_WRRET_NACK', + 'GL2C_PERF_SEL_EA_WR_UNCACHED_32B', 'GL2C_PERF_SEL_EVICT', + 'GL2C_PERF_SEL_FULLY_WRITTEN_HIT', 'GL2C_PERF_SEL_FULL_HIT', + 'GL2C_PERF_SEL_GARLIC_READ', 'GL2C_PERF_SEL_GARLIC_WRITE', + 'GL2C_PERF_SEL_GCR_ALL', 'GL2C_PERF_SEL_GCR_DISCARD', + 'GL2C_PERF_SEL_GCR_GL2_INV_ALL', + 'GL2C_PERF_SEL_GCR_GL2_INV_RANGE', 'GL2C_PERF_SEL_GCR_GL2_WB_ALL', + 'GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE', + 'GL2C_PERF_SEL_GCR_GL2_WB_RANGE', 'GL2C_PERF_SEL_GCR_INV', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT', + 'GL2C_PERF_SEL_GCR_INVL2_VOL_START', 'GL2C_PERF_SEL_GCR_MDC_INV', + 'GL2C_PERF_SEL_GCR_MDC_INV_ALL', + 'GL2C_PERF_SEL_GCR_MDC_INV_RANGE', 'GL2C_PERF_SEL_GCR_RANGE', + 'GL2C_PERF_SEL_GCR_UNSHARED', 'GL2C_PERF_SEL_GCR_VOL', + 'GL2C_PERF_SEL_GCR_WB', 'GL2C_PERF_SEL_GCR_WBINVL2_CYCLE', + 'GL2C_PERF_SEL_GCR_WBINVL2_EVICT', + 'GL2C_PERF_SEL_GCR_WBINVL2_START', + 'GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE', + 'GL2C_PERF_SEL_GCR_WBL2_VOL_START', 'GL2C_PERF_SEL_GL2A_LEVEL', + 'GL2C_PERF_SEL_HIGH_PRIORITY_REQ', 'GL2C_PERF_SEL_HIT', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8', + 'GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9', + 'GL2C_PERF_SEL_IB_CM_STALL', 'GL2C_PERF_SEL_IB_REQ', + 'GL2C_PERF_SEL_IB_STALL', 'GL2C_PERF_SEL_IB_TAG_STALL', + 'GL2C_PERF_SEL_INTERNAL_PROBE', 'GL2C_PERF_SEL_IO_READ', + 'GL2C_PERF_SEL_IO_WRITE', 'GL2C_PERF_SEL_LATENCY_FIFO_FULL', + 'GL2C_PERF_SEL_LRU_REQ', 'GL2C_PERF_SEL_MC_RDREQ', + 'GL2C_PERF_SEL_MC_RDREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ', + 'GL2C_PERF_SEL_MC_WRREQ_LEVEL', 'GL2C_PERF_SEL_MC_WRREQ_STALL', + 'GL2C_PERF_SEL_MDC_INV_METADATA', 'GL2C_PERF_SEL_MDC_LEVEL', + 'GL2C_PERF_SEL_MDC_REQ', 'GL2C_PERF_SEL_MDC_SECTOR_HIT', + 'GL2C_PERF_SEL_MDC_SECTOR_MISS', + 'GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_MDC_TAG_HIT', + 'GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL', + 'GL2C_PERF_SEL_MDC_TAG_STALL', + 'GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL', + 'GL2C_PERF_SEL_METADATA_READ_REQ', 'GL2C_PERF_SEL_MISS', + 'GL2C_PERF_SEL_NOA_REQ', 'GL2C_PERF_SEL_NONE', + 'GL2C_PERF_SEL_NOP_ACK', 'GL2C_PERF_SEL_NOP_RTN0', + 'GL2C_PERF_SEL_NORMAL_EVICT', 'GL2C_PERF_SEL_NORMAL_WRITEBACK', + 'GL2C_PERF_SEL_ONION_READ', 'GL2C_PERF_SEL_ONION_WRITE', + 'GL2C_PERF_SEL_PARTIAL_32B_HIT', 'GL2C_PERF_SEL_PARTIAL_64B_HIT', + 'GL2C_PERF_SEL_PARTIAL_96B_HIT', 'GL2C_PERF_SEL_PROBE', + 'GL2C_PERF_SEL_PROBE_ALL', 'GL2C_PERF_SEL_PROBE_EVICT', + 'GL2C_PERF_SEL_PROBE_FILTER_DISABLED', + 'GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION', + 'GL2C_PERF_SEL_READ', 'GL2C_PERF_SEL_READ_128_REQ', + 'GL2C_PERF_SEL_READ_32_REQ', 'GL2C_PERF_SEL_READ_64_REQ', + 'GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE', + 'GL2C_PERF_SEL_READ_RETURN_TIMEOUT', 'GL2C_PERF_SEL_REQ', + 'GL2C_PERF_SEL_REQ_TO_MISS_QUEUE', 'GL2C_PERF_SEL_RETURN_ACK', + 'GL2C_PERF_SEL_RETURN_DATA', 'GL2C_PERF_SEL_SHARED_REQ', + 'GL2C_PERF_SEL_SRC_FIFO_FULL', 'GL2C_PERF_SEL_STREAM_REQ', + 'GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL', + 'GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL', + 'GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL', + 'GL2C_PERF_SEL_TAG_PROBE_STALL', + 'GL2C_PERF_SEL_TAG_READ_DST_STALL', 'GL2C_PERF_SEL_TAG_STALL', + 'GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL', + 'GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL', 'GL2C_PERF_SEL_UC_REQ', + 'GL2C_PERF_SEL_UNCACHED_WRITE', 'GL2C_PERF_SEL_VOL_REQ', + 'GL2C_PERF_SEL_WRITE', 'GL2C_PERF_SEL_WRITEBACK', + 'GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT', + 'GL2C_PERF_SEL_WRITE_32_REQ', 'GL2C_PERF_SEL_WRITE_64_REQ', + 'GL2_CACHE_POLICIES', 'GL2_CACHE_POLICY_BYPASS', + 'GL2_CACHE_POLICY_LRU', 'GL2_CACHE_POLICY_NOA', + 'GL2_CACHE_POLICY_STREAM', 'GL2_EA_CID', 'GL2_EA_CID_CLIENT', + 'GL2_EA_CID_CP', 'GL2_EA_CID_CPDMA', 'GL2_EA_CID_DCC', + 'GL2_EA_CID_FMASK', 'GL2_EA_CID_HTILE', 'GL2_EA_CID_MES', + 'GL2_EA_CID_RLC', 'GL2_EA_CID_RT', 'GL2_EA_CID_SDMA', + 'GL2_EA_CID_SQC', 'GL2_EA_CID_TCPMETA', 'GL2_EA_CID_UTCL2', + 'GL2_EA_CID_ZPCPSD', 'GL2_EA_CID_Z_STENCIL', 'GL2_NACKS', + 'GL2_NACK_DATA_ERROR', 'GL2_NACK_NO_FAULT', 'GL2_NACK_PAGE_FAULT', + 'GL2_NACK_PROTECTION_FAULT', 'GL2_OP', 'GL2_OP_ATOMIC_ADD_32', + 'GL2_OP_ATOMIC_ADD_64', 'GL2_OP_ATOMIC_ADD_RTN_32', + 'GL2_OP_ATOMIC_ADD_RTN_64', 'GL2_OP_ATOMIC_AND_32', + 'GL2_OP_ATOMIC_AND_64', 'GL2_OP_ATOMIC_AND_RTN_32', + 'GL2_OP_ATOMIC_AND_RTN_64', 'GL2_OP_ATOMIC_CLAMP_SUB_RTN_32', + 'GL2_OP_ATOMIC_CMPSWAP_32', 'GL2_OP_ATOMIC_CMPSWAP_64', + 'GL2_OP_ATOMIC_CMPSWAP_RTN_32', 'GL2_OP_ATOMIC_CMPSWAP_RTN_64', + 'GL2_OP_ATOMIC_DEC_32', 'GL2_OP_ATOMIC_DEC_64', + 'GL2_OP_ATOMIC_DEC_RTN_32', 'GL2_OP_ATOMIC_DEC_RTN_64', + 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FCMPSWAP_32', 'GL2_OP_ATOMIC_FCMPSWAP_64', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FCMPSWAP_RTN_32', 'GL2_OP_ATOMIC_FCMPSWAP_RTN_64', + 'GL2_OP_ATOMIC_FMAX_32', 'GL2_OP_ATOMIC_FMAX_64', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FMAX_RTN_32', 'GL2_OP_ATOMIC_FMAX_RTN_64', + 'GL2_OP_ATOMIC_FMIN_32', 'GL2_OP_ATOMIC_FMIN_64', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 'GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 'GL2_OP_ATOMIC_FMIN_RTN_32', 'GL2_OP_ATOMIC_FMIN_RTN_64', + 'GL2_OP_ATOMIC_INC_32', 'GL2_OP_ATOMIC_INC_64', + 'GL2_OP_ATOMIC_INC_RTN_32', 'GL2_OP_ATOMIC_INC_RTN_64', + 'GL2_OP_ATOMIC_OR_32', 'GL2_OP_ATOMIC_OR_64', + 'GL2_OP_ATOMIC_OR_RTN_32', 'GL2_OP_ATOMIC_OR_RTN_64', + 'GL2_OP_ATOMIC_SMAX_32', 'GL2_OP_ATOMIC_SMAX_64', + 'GL2_OP_ATOMIC_SMAX_RTN_32', 'GL2_OP_ATOMIC_SMAX_RTN_64', + 'GL2_OP_ATOMIC_SMIN_32', 'GL2_OP_ATOMIC_SMIN_64', + 'GL2_OP_ATOMIC_SMIN_RTN_32', 'GL2_OP_ATOMIC_SMIN_RTN_64', + 'GL2_OP_ATOMIC_SUB_32', 'GL2_OP_ATOMIC_SUB_64', + 'GL2_OP_ATOMIC_SUB_RTN_32', 'GL2_OP_ATOMIC_SUB_RTN_64', + 'GL2_OP_ATOMIC_SWAP_32', 'GL2_OP_ATOMIC_SWAP_64', + 'GL2_OP_ATOMIC_SWAP_RTN_32', 'GL2_OP_ATOMIC_SWAP_RTN_64', + 'GL2_OP_ATOMIC_UMAX_32', 'GL2_OP_ATOMIC_UMAX_64', + 'GL2_OP_ATOMIC_UMAX_8', 'GL2_OP_ATOMIC_UMAX_RTN_32', + 'GL2_OP_ATOMIC_UMAX_RTN_64', 'GL2_OP_ATOMIC_UMIN_32', + 'GL2_OP_ATOMIC_UMIN_64', 'GL2_OP_ATOMIC_UMIN_8', + 'GL2_OP_ATOMIC_UMIN_RTN_32', 'GL2_OP_ATOMIC_UMIN_RTN_64', + 'GL2_OP_ATOMIC_XOR_32', 'GL2_OP_ATOMIC_XOR_64', + 'GL2_OP_ATOMIC_XOR_RTN_32', 'GL2_OP_ATOMIC_XOR_RTN_64', + 'GL2_OP_GL1_INV', 'GL2_OP_MASKS', 'GL2_OP_MASK_64', + 'GL2_OP_MASK_FLUSH_DENROM', 'GL2_OP_MASK_NO_RTN', + 'GL2_OP_NOP_ACK', 'GL2_OP_NOP_RTN0', 'GL2_OP_PROBE_FILTER', + 'GL2_OP_READ', 'GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 'GL2_OP_WRITE', 'GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE', + 'GLOBAL_CONTROL_CONTROLLER_RESET', 'GLOBAL_CONTROL_FLUSH_CONTROL', + 'GLOBAL_STATUS_FLUSH_STATUS', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED', + 'GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED', + 'GL__CONSTANT_ALPHA', 'GL__CONSTANT_COLOR', 'GL__DST_ALPHA', + 'GL__DST_COLOR', 'GL__ONE', 'GL__ONE_MINUS_CONSTANT_ALPHA', + 'GL__ONE_MINUS_CONSTANT_COLOR', 'GL__ONE_MINUS_DST_ALPHA', + 'GL__ONE_MINUS_DST_COLOR', 'GL__ONE_MINUS_SRC_ALPHA', + 'GL__ONE_MINUS_SRC_COLOR', 'GL__SRC_ALPHA', + 'GL__SRC_ALPHA_SATURATE', 'GL__SRC_COLOR', 'GL__ZERO', + 'GRBM_PERF_SEL', 'GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY', + 'GRBM_PERF_SEL_BCI_BUSY', 'GRBM_PERF_SEL_CB_BUSY', + 'GRBM_PERF_SEL_CB_CLEAN', 'GRBM_PERF_SEL_CH_BUSY', + 'GRBM_PERF_SEL_COUNT', 'GRBM_PERF_SEL_CPAXI_BUSY', + 'GRBM_PERF_SEL_CPC_BUSY', 'GRBM_PERF_SEL_CPF_BUSY', + 'GRBM_PERF_SEL_CPG_BUSY', 'GRBM_PERF_SEL_CP_BUSY', + 'GRBM_PERF_SEL_CP_COHER_BUSY', 'GRBM_PERF_SEL_CP_DMA_BUSY', + 'GRBM_PERF_SEL_DB_BUSY', 'GRBM_PERF_SEL_DB_CLEAN', + 'GRBM_PERF_SEL_EA_BUSY', 'GRBM_PERF_SEL_GDS_BUSY', + 'GRBM_PERF_SEL_GE_BUSY', 'GRBM_PERF_SEL_GE_NO_DMA_BUSY', + 'GRBM_PERF_SEL_GL1CC_BUSY', 'GRBM_PERF_SEL_GL1H_BUSY', + 'GRBM_PERF_SEL_GL2CC_BUSY', 'GRBM_PERF_SEL_GUI_ACTIVE', + 'GRBM_PERF_SEL_GUS_BUSY', 'GRBM_PERF_SEL_PA_BUSY', + 'GRBM_PERF_SEL_PC_BUSY', 'GRBM_PERF_SEL_PH_BUSY', + 'GRBM_PERF_SEL_PMM_BUSY', 'GRBM_PERF_SEL_RLC_BUSY', + 'GRBM_PERF_SEL_RMI_BUSY', 'GRBM_PERF_SEL_SC_BUSY', + 'GRBM_PERF_SEL_SDMA_BUSY', 'GRBM_PERF_SEL_SPI_BUSY', + 'GRBM_PERF_SEL_SX_BUSY', 'GRBM_PERF_SEL_TA_BUSY', + 'GRBM_PERF_SEL_TCP_BUSY', 'GRBM_PERF_SEL_USER_DEFINED', + 'GRBM_PERF_SEL_UTCL1_BUSY', 'GRBM_PERF_SEL_UTCL2_BUSY', + 'GRBM_SE0_PERF_SEL', 'GRBM_SE0_PERF_SEL_BCI_BUSY', + 'GRBM_SE0_PERF_SEL_CB_BUSY', 'GRBM_SE0_PERF_SEL_CB_CLEAN', + 'GRBM_SE0_PERF_SEL_COUNT', 'GRBM_SE0_PERF_SEL_DB_BUSY', + 'GRBM_SE0_PERF_SEL_DB_CLEAN', 'GRBM_SE0_PERF_SEL_GL1CC_BUSY', + 'GRBM_SE0_PERF_SEL_GL1H_BUSY', 'GRBM_SE0_PERF_SEL_PA_BUSY', + 'GRBM_SE0_PERF_SEL_PC_BUSY', 'GRBM_SE0_PERF_SEL_RMI_BUSY', + 'GRBM_SE0_PERF_SEL_SC_BUSY', 'GRBM_SE0_PERF_SEL_SPI_BUSY', + 'GRBM_SE0_PERF_SEL_SX_BUSY', 'GRBM_SE0_PERF_SEL_TA_BUSY', + 'GRBM_SE0_PERF_SEL_TCP_BUSY', 'GRBM_SE0_PERF_SEL_USER_DEFINED', + 'GRBM_SE0_PERF_SEL_UTCL1_BUSY', 'GRBM_SE1_PERF_SEL', + 'GRBM_SE1_PERF_SEL_BCI_BUSY', 'GRBM_SE1_PERF_SEL_CB_BUSY', + 'GRBM_SE1_PERF_SEL_CB_CLEAN', 'GRBM_SE1_PERF_SEL_COUNT', + 'GRBM_SE1_PERF_SEL_DB_BUSY', 'GRBM_SE1_PERF_SEL_DB_CLEAN', + 'GRBM_SE1_PERF_SEL_GL1CC_BUSY', 'GRBM_SE1_PERF_SEL_GL1H_BUSY', + 'GRBM_SE1_PERF_SEL_PA_BUSY', 'GRBM_SE1_PERF_SEL_PC_BUSY', + 'GRBM_SE1_PERF_SEL_RMI_BUSY', 'GRBM_SE1_PERF_SEL_SC_BUSY', + 'GRBM_SE1_PERF_SEL_SPI_BUSY', 'GRBM_SE1_PERF_SEL_SX_BUSY', + 'GRBM_SE1_PERF_SEL_TA_BUSY', 'GRBM_SE1_PERF_SEL_TCP_BUSY', + 'GRBM_SE1_PERF_SEL_USER_DEFINED', 'GRBM_SE1_PERF_SEL_UTCL1_BUSY', + 'GRBM_SE2_PERF_SEL', 'GRBM_SE2_PERF_SEL_BCI_BUSY', + 'GRBM_SE2_PERF_SEL_CB_BUSY', 'GRBM_SE2_PERF_SEL_CB_CLEAN', + 'GRBM_SE2_PERF_SEL_COUNT', 'GRBM_SE2_PERF_SEL_DB_BUSY', + 'GRBM_SE2_PERF_SEL_DB_CLEAN', 'GRBM_SE2_PERF_SEL_GL1CC_BUSY', + 'GRBM_SE2_PERF_SEL_GL1H_BUSY', 'GRBM_SE2_PERF_SEL_PA_BUSY', + 'GRBM_SE2_PERF_SEL_PC_BUSY', 'GRBM_SE2_PERF_SEL_RMI_BUSY', + 'GRBM_SE2_PERF_SEL_SC_BUSY', 'GRBM_SE2_PERF_SEL_SPI_BUSY', + 'GRBM_SE2_PERF_SEL_SX_BUSY', 'GRBM_SE2_PERF_SEL_TA_BUSY', + 'GRBM_SE2_PERF_SEL_TCP_BUSY', 'GRBM_SE2_PERF_SEL_USER_DEFINED', + 'GRBM_SE2_PERF_SEL_UTCL1_BUSY', 'GRBM_SE3_PERF_SEL', + 'GRBM_SE3_PERF_SEL_BCI_BUSY', 'GRBM_SE3_PERF_SEL_CB_BUSY', + 'GRBM_SE3_PERF_SEL_CB_CLEAN', 'GRBM_SE3_PERF_SEL_COUNT', + 'GRBM_SE3_PERF_SEL_DB_BUSY', 'GRBM_SE3_PERF_SEL_DB_CLEAN', + 'GRBM_SE3_PERF_SEL_GL1CC_BUSY', 'GRBM_SE3_PERF_SEL_GL1H_BUSY', + 'GRBM_SE3_PERF_SEL_PA_BUSY', 'GRBM_SE3_PERF_SEL_PC_BUSY', + 'GRBM_SE3_PERF_SEL_RMI_BUSY', 'GRBM_SE3_PERF_SEL_SC_BUSY', + 'GRBM_SE3_PERF_SEL_SPI_BUSY', 'GRBM_SE3_PERF_SEL_SX_BUSY', + 'GRBM_SE3_PERF_SEL_TA_BUSY', 'GRBM_SE3_PERF_SEL_TCP_BUSY', + 'GRBM_SE3_PERF_SEL_USER_DEFINED', 'GRBM_SE3_PERF_SEL_UTCL1_BUSY', + 'GRBM_SE4_PERF_SEL', 'GRBM_SE4_PERF_SEL_BCI_BUSY', + 'GRBM_SE4_PERF_SEL_CB_BUSY', 'GRBM_SE4_PERF_SEL_CB_CLEAN', + 'GRBM_SE4_PERF_SEL_COUNT', 'GRBM_SE4_PERF_SEL_DB_BUSY', + 'GRBM_SE4_PERF_SEL_DB_CLEAN', 'GRBM_SE4_PERF_SEL_GL1CC_BUSY', + 'GRBM_SE4_PERF_SEL_GL1H_BUSY', 'GRBM_SE4_PERF_SEL_PA_BUSY', + 'GRBM_SE4_PERF_SEL_PC_BUSY', 'GRBM_SE4_PERF_SEL_RMI_BUSY', + 'GRBM_SE4_PERF_SEL_SC_BUSY', 'GRBM_SE4_PERF_SEL_SPI_BUSY', + 'GRBM_SE4_PERF_SEL_SX_BUSY', 'GRBM_SE4_PERF_SEL_TA_BUSY', + 'GRBM_SE4_PERF_SEL_TCP_BUSY', 'GRBM_SE4_PERF_SEL_USER_DEFINED', + 'GRBM_SE4_PERF_SEL_UTCL1_BUSY', 'GRBM_SE5_PERF_SEL', + 'GRBM_SE5_PERF_SEL_BCI_BUSY', 'GRBM_SE5_PERF_SEL_CB_BUSY', + 'GRBM_SE5_PERF_SEL_CB_CLEAN', 'GRBM_SE5_PERF_SEL_COUNT', + 'GRBM_SE5_PERF_SEL_DB_BUSY', 'GRBM_SE5_PERF_SEL_DB_CLEAN', + 'GRBM_SE5_PERF_SEL_GL1CC_BUSY', 'GRBM_SE5_PERF_SEL_GL1H_BUSY', + 'GRBM_SE5_PERF_SEL_PA_BUSY', 'GRBM_SE5_PERF_SEL_PC_BUSY', + 'GRBM_SE5_PERF_SEL_RMI_BUSY', 'GRBM_SE5_PERF_SEL_SC_BUSY', + 'GRBM_SE5_PERF_SEL_SPI_BUSY', 'GRBM_SE5_PERF_SEL_SX_BUSY', + 'GRBM_SE5_PERF_SEL_TA_BUSY', 'GRBM_SE5_PERF_SEL_TCP_BUSY', + 'GRBM_SE5_PERF_SEL_USER_DEFINED', 'GRBM_SE5_PERF_SEL_UTCL1_BUSY', + 'GRBM_SE6_PERF_SEL', 'GRBM_SE6_PERF_SEL_BCI_BUSY', + 'GRBM_SE6_PERF_SEL_CB_BUSY', 'GRBM_SE6_PERF_SEL_CB_CLEAN', + 'GRBM_SE6_PERF_SEL_COUNT', 'GRBM_SE6_PERF_SEL_DB_BUSY', + 'GRBM_SE6_PERF_SEL_DB_CLEAN', 'GRBM_SE6_PERF_SEL_GL1CC_BUSY', + 'GRBM_SE6_PERF_SEL_GL1H_BUSY', 'GRBM_SE6_PERF_SEL_PA_BUSY', + 'GRBM_SE6_PERF_SEL_PC_BUSY', 'GRBM_SE6_PERF_SEL_RMI_BUSY', + 'GRBM_SE6_PERF_SEL_SC_BUSY', 'GRBM_SE6_PERF_SEL_SPI_BUSY', + 'GRBM_SE6_PERF_SEL_SX_BUSY', 'GRBM_SE6_PERF_SEL_TA_BUSY', + 'GRBM_SE6_PERF_SEL_TCP_BUSY', 'GRBM_SE6_PERF_SEL_USER_DEFINED', + 'GRBM_SE6_PERF_SEL_UTCL1_BUSY', 'GRBM_SE7_PERF_SEL', + 'GRBM_SE7_PERF_SEL_BCI_BUSY', 'GRBM_SE7_PERF_SEL_CB_BUSY', + 'GRBM_SE7_PERF_SEL_CB_CLEAN', 'GRBM_SE7_PERF_SEL_COUNT', + 'GRBM_SE7_PERF_SEL_DB_BUSY', 'GRBM_SE7_PERF_SEL_DB_CLEAN', + 'GRBM_SE7_PERF_SEL_GL1CC_BUSY', 'GRBM_SE7_PERF_SEL_GL1H_BUSY', + 'GRBM_SE7_PERF_SEL_PA_BUSY', 'GRBM_SE7_PERF_SEL_PC_BUSY', + 'GRBM_SE7_PERF_SEL_RMI_BUSY', 'GRBM_SE7_PERF_SEL_SC_BUSY', + 'GRBM_SE7_PERF_SEL_SPI_BUSY', 'GRBM_SE7_PERF_SEL_SX_BUSY', + 'GRBM_SE7_PERF_SEL_TA_BUSY', 'GRBM_SE7_PERF_SEL_TCP_BUSY', + 'GRBM_SE7_PERF_SEL_USER_DEFINED', 'GRBM_SE7_PERF_SEL_UTCL1_BUSY', + 'GREEN_LUT', 'GSTHREADID_SIZE', 'GS_OFF', 'GS_SCENARIO_A', + 'GS_SCENARIO_B', 'GS_SCENARIO_C', 'GS_SCENARIO_G', 'GS_STAGE_OFF', + 'GS_STAGE_ON', 'HDA_BASE', 'HDA_BASE__INST0_SEG0', + 'HDA_BASE__INST0_SEG1', 'HDA_BASE__INST0_SEG2', + 'HDA_BASE__INST0_SEG3', 'HDA_BASE__INST0_SEG4', + 'HDA_BASE__INST1_SEG0', 'HDA_BASE__INST1_SEG1', + 'HDA_BASE__INST1_SEG2', 'HDA_BASE__INST1_SEG3', + 'HDA_BASE__INST1_SEG4', 'HDA_BASE__INST2_SEG0', + 'HDA_BASE__INST2_SEG1', 'HDA_BASE__INST2_SEG2', + 'HDA_BASE__INST2_SEG3', 'HDA_BASE__INST2_SEG4', + 'HDA_BASE__INST3_SEG0', 'HDA_BASE__INST3_SEG1', + 'HDA_BASE__INST3_SEG2', 'HDA_BASE__INST3_SEG3', + 'HDA_BASE__INST3_SEG4', 'HDA_BASE__INST4_SEG0', + 'HDA_BASE__INST4_SEG1', 'HDA_BASE__INST4_SEG2', + 'HDA_BASE__INST4_SEG3', 'HDA_BASE__INST4_SEG4', + 'HDA_BASE__INST5_SEG0', 'HDA_BASE__INST5_SEG1', + 'HDA_BASE__INST5_SEG2', 'HDA_BASE__INST5_SEG3', + 'HDA_BASE__INST5_SEG4', 'HDA_BASE__INST6_SEG0', + 'HDA_BASE__INST6_SEG1', 'HDA_BASE__INST6_SEG2', + 'HDA_BASE__INST6_SEG3', 'HDA_BASE__INST6_SEG4', + 'HDMICHARCLK_SRC_SEL', 'HDMICHARCLK_SRC_SEL_SRC_RESERVED', + 'HDMICHARCLK_SRC_SEL_UNIPHYA', 'HDMICHARCLK_SRC_SEL_UNIPHYB', + 'HDMICHARCLK_SRC_SEL_UNIPHYC', 'HDMICHARCLK_SRC_SEL_UNIPHYD', + 'HDMICHARCLK_SRC_SEL_UNIPHYE', 'HDMISTREAMCLK_DTO_FORCE_DIS', + 'HDMISTREAMCLK_SRC_SEL', 'HDMI_ACP_NOT_SEND', 'HDMI_ACP_PKT_SEND', + 'HDMI_ACP_SEND', 'HDMI_ACR_0_MULTIPLE_RESERVED', + 'HDMI_ACR_1_MULTIPLE', 'HDMI_ACR_2_MULTIPLE', + 'HDMI_ACR_3_MULTIPLE_RESERVED', 'HDMI_ACR_4_MULTIPLE', + 'HDMI_ACR_5_MULTIPLE_RESERVED', 'HDMI_ACR_6_MULTIPLE_RESERVED', + 'HDMI_ACR_7_MULTIPLE_RESERVED', 'HDMI_ACR_AUDIO_PRIORITY', + 'HDMI_ACR_CONT', 'HDMI_ACR_CONT_DISABLE', 'HDMI_ACR_CONT_ENABLE', + 'HDMI_ACR_NOT_SEND', 'HDMI_ACR_N_MULTIPLE', + 'HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', + 'HDMI_ACR_PKT_SEND', 'HDMI_ACR_SELECT', 'HDMI_ACR_SELECT_32K', + 'HDMI_ACR_SELECT_44K', 'HDMI_ACR_SELECT_48K', + 'HDMI_ACR_SELECT_HW', 'HDMI_ACR_SEND', 'HDMI_ACR_SOURCE', + 'HDMI_ACR_SOURCE_HW', 'HDMI_ACR_SOURCE_SW', + 'HDMI_AUDIO_DELAY_56CLK', 'HDMI_AUDIO_DELAY_58CLK', + 'HDMI_AUDIO_DELAY_DISABLE', 'HDMI_AUDIO_DELAY_EN', + 'HDMI_AUDIO_DELAY_RESERVED', 'HDMI_AUDIO_INFO_CONT', + 'HDMI_AUDIO_INFO_CONT_DISABLE', 'HDMI_AUDIO_INFO_CONT_ENABLE', + 'HDMI_AUDIO_INFO_NOT_SEND', 'HDMI_AUDIO_INFO_PKT_SEND', + 'HDMI_AUDIO_INFO_SEND', + 'HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', + 'HDMI_BORROW_MODE', 'HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE', + 'HDMI_CLOCK_CHANNEL_RATE', 'HDMI_DATA_SCRAMBLE_DISABLE', + 'HDMI_DATA_SCRAMBLE_EN', 'HDMI_DATA_SCRAMBLE_ENABLE', + 'HDMI_DEEP_COLOR_DEPTH', 'HDMI_DEEP_COLOR_DEPTH_24BPP', + 'HDMI_DEEP_COLOR_DEPTH_30BPP', 'HDMI_DEEP_COLOR_DEPTH_36BPP', + 'HDMI_DEEP_COLOR_DEPTH_48BPP', 'HDMI_DEFAULT_PAHSE', + 'HDMI_DEFAULT_PHASE_IS_0', 'HDMI_DEFAULT_PHASE_IS_1', + 'HDMI_ERROR_ACK', 'HDMI_ERROR_ACK_INT', 'HDMI_ERROR_MASK', + 'HDMI_ERROR_MASK_INT', 'HDMI_ERROR_NOT_ACK', + 'HDMI_ERROR_NOT_MASK', 'HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE', + 'HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE', 'HDMI_FRL', + 'HDMI_GC_AVMUTE', 'HDMI_GC_AVMUTE_CONT', + 'HDMI_GC_AVMUTE_CONT_DISABLE', 'HDMI_GC_AVMUTE_CONT_ENABLE', + 'HDMI_GC_AVMUTE_SET', 'HDMI_GC_AVMUTE_UNSET', 'HDMI_GC_CONT', + 'HDMI_GC_CONT_DISABLE', 'HDMI_GC_CONT_ENABLE', 'HDMI_GC_NOT_SEND', + 'HDMI_GC_PKT_SEND', 'HDMI_GC_SEND', 'HDMI_GENERIC_CONT', + 'HDMI_GENERIC_CONT_DISABLE', 'HDMI_GENERIC_CONT_ENABLE', + 'HDMI_GENERIC_NOT_SEND', 'HDMI_GENERIC_PKT_SEND', + 'HDMI_GENERIC_SEND', 'HDMI_ISRC_CONT', 'HDMI_ISRC_CONT_DISABLE', + 'HDMI_ISRC_CONT_ENABLE', 'HDMI_ISRC_NOT_SEND', + 'HDMI_ISRC_PKT_SEND', 'HDMI_ISRC_SEND', + 'HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC', + 'HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC', 'HDMI_KEEPOUT_MODE', + 'HDMI_METADATA_ENABLE', 'HDMI_METADATA_NOT_SEND', + 'HDMI_METADATA_PKT_SEND', 'HDMI_MPEG_INFO_CONT', + 'HDMI_MPEG_INFO_CONT_DISABLE', 'HDMI_MPEG_INFO_CONT_ENABLE', + 'HDMI_MPEG_INFO_NOT_SEND', 'HDMI_MPEG_INFO_PKT_SEND', + 'HDMI_MPEG_INFO_SEND', 'HDMI_NOT_SEND_MAX_AUDIO_PACKETS', + 'HDMI_NO_EXTRA_NULL_PACKET_FILLED', 'HDMI_NULL_NOT_SEND', + 'HDMI_NULL_PKT_SEND', 'HDMI_NULL_SEND', 'HDMI_PACKET_GEN_VERSION', + 'HDMI_PACKET_GEN_VERSION_NEW', 'HDMI_PACKET_GEN_VERSION_OLD', + 'HDMI_PACKET_LINE_REFERENCE', 'HDMI_PACKING_PHASE_OVERRIDE', + 'HDMI_PACKING_PHASE_SET_BY_HW', 'HDMI_PACKING_PHASE_SET_BY_SW', + 'HDMI_PKT_LINE_REF_OTGSOF', 'HDMI_PKT_LINE_REF_VSYNC', + 'HDMI_SEND_MAX_AUDIO_PACKETS', 'HDMI_STREAM_ENC_DB_DISABLE', + 'HDMI_STREAM_ENC_DB_DISABLE_CONTROL', 'HDMI_STREAM_ENC_DB_ENABLE', + 'HDMI_STREAM_ENC_DCCG', 'HDMI_STREAM_ENC_DISABLE', + 'HDMI_STREAM_ENC_DISPLAY_PIPE', 'HDMI_STREAM_ENC_DSC_MODE', + 'HDMI_STREAM_ENC_ENABLE', 'HDMI_STREAM_ENC_ENABLE_CONTROL', + 'HDMI_STREAM_ENC_HARDWARE', 'HDMI_STREAM_ENC_NOT_RESET', + 'HDMI_STREAM_ENC_NO_ERROR_OCCURRED', + 'HDMI_STREAM_ENC_ODM_COMBINE_MODE', + 'HDMI_STREAM_ENC_OVERFLOW_OCCURRED', + 'HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR', + 'HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT', + 'HDMI_STREAM_ENC_PIXEL_ENCODING', 'HDMI_STREAM_ENC_PROGRAMMABLE', + 'HDMI_STREAM_ENC_READ_CLOCK_CONTROL', 'HDMI_STREAM_ENC_RESET', + 'HDMI_STREAM_ENC_RESET_CONTROL', 'HDMI_STREAM_ENC_STREAM_ACTIVE', + 'HDMI_STREAM_ENC_UNDERFLOW_OCCURRED', + 'HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE', + 'HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE', 'HDMI_TB_ENC_ACP_SEND', + 'HDMI_TB_ENC_ACR_AUDIO_PRIORITY', 'HDMI_TB_ENC_ACR_CONT', + 'HDMI_TB_ENC_ACR_N_MULTIPLE', 'HDMI_TB_ENC_ACR_SELECT', + 'HDMI_TB_ENC_ACR_SEND', 'HDMI_TB_ENC_ACR_SOURCE', + 'HDMI_TB_ENC_AUDIO_INFO_CONT', 'HDMI_TB_ENC_AUDIO_INFO_SEND', + 'HDMI_TB_ENC_CRC_SRC_SEL', 'HDMI_TB_ENC_CRC_TYPE', + 'HDMI_TB_ENC_DEEP_COLOR_DEPTH', 'HDMI_TB_ENC_DEFAULT_PAHSE', + 'HDMI_TB_ENC_DSC_MODE', 'HDMI_TB_ENC_ENABLE', + 'HDMI_TB_ENC_GC_AVMUTE', 'HDMI_TB_ENC_GC_AVMUTE_CONT', + 'HDMI_TB_ENC_GC_CONT', 'HDMI_TB_ENC_GC_SEND', + 'HDMI_TB_ENC_GENERIC_CONT', 'HDMI_TB_ENC_GENERIC_LOCK_DISABLE', + 'HDMI_TB_ENC_GENERIC_LOCK_EN', 'HDMI_TB_ENC_GENERIC_LOCK_ENABLE', + 'HDMI_TB_ENC_GENERIC_SEND', 'HDMI_TB_ENC_ISRC_CONT', + 'HDMI_TB_ENC_ISRC_SEND', 'HDMI_TB_ENC_METADATA_ENABLE', + 'HDMI_TB_ENC_PACKET_LINE_REFERENCE', 'HDMI_TB_ENC_PIXEL_ENCODING', + 'HDMI_TB_ENC_RESET', 'HDMI_TB_ENC_SYNC_PHASE', + 'HDMI_TMDS_OR_DP_8B10B', 'HDP_BASE', 'HDP_BASE__INST0_SEG0', 'HDP_BASE__INST0_SEG1', 'HDP_BASE__INST0_SEG2', 'HDP_BASE__INST0_SEG3', 'HDP_BASE__INST0_SEG4', 'HDP_BASE__INST1_SEG0', 'HDP_BASE__INST1_SEG1', @@ -13999,26 +65556,498 @@ __all__ = \ 'HDP_BASE__INST5_SEG4', 'HDP_BASE__INST6_SEG0', 'HDP_BASE__INST6_SEG1', 'HDP_BASE__INST6_SEG2', 'HDP_BASE__INST6_SEG3', 'HDP_BASE__INST6_SEG4', - 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', 'INDIRECT_BUFFER_VALID', - 'MAX_INSTANCE', 'MAX_SEGMENT', 'MMHUB_BASE', - 'MMHUB_BASE__INST0_SEG0', 'MMHUB_BASE__INST0_SEG1', - 'MMHUB_BASE__INST0_SEG2', 'MMHUB_BASE__INST0_SEG3', - 'MMHUB_BASE__INST0_SEG4', 'MMHUB_BASE__INST1_SEG0', - 'MMHUB_BASE__INST1_SEG1', 'MMHUB_BASE__INST1_SEG2', - 'MMHUB_BASE__INST1_SEG3', 'MMHUB_BASE__INST1_SEG4', - 'MMHUB_BASE__INST2_SEG0', 'MMHUB_BASE__INST2_SEG1', - 'MMHUB_BASE__INST2_SEG2', 'MMHUB_BASE__INST2_SEG3', - 'MMHUB_BASE__INST2_SEG4', 'MMHUB_BASE__INST3_SEG0', - 'MMHUB_BASE__INST3_SEG1', 'MMHUB_BASE__INST3_SEG2', - 'MMHUB_BASE__INST3_SEG3', 'MMHUB_BASE__INST3_SEG4', - 'MMHUB_BASE__INST4_SEG0', 'MMHUB_BASE__INST4_SEG1', - 'MMHUB_BASE__INST4_SEG2', 'MMHUB_BASE__INST4_SEG3', - 'MMHUB_BASE__INST4_SEG4', 'MMHUB_BASE__INST5_SEG0', - 'MMHUB_BASE__INST5_SEG1', 'MMHUB_BASE__INST5_SEG2', - 'MMHUB_BASE__INST5_SEG3', 'MMHUB_BASE__INST5_SEG4', - 'MMHUB_BASE__INST6_SEG0', 'MMHUB_BASE__INST6_SEG1', - 'MMHUB_BASE__INST6_SEG2', 'MMHUB_BASE__INST6_SEG3', - 'MMHUB_BASE__INST6_SEG4', 'MP0_BASE', 'MP0_BASE__INST0_SEG0', + 'HDP_ENDIAN_8IN16', 'HDP_ENDIAN_8IN32', 'HDP_ENDIAN_8IN64', + 'HDP_ENDIAN_NONE', 'HEADER_AGENT_DISPATCH', 'HEADER_BARRIER', + 'HPD_INT_CONTROL_ACK', 'HPD_INT_CONTROL_ACK_0', + 'HPD_INT_CONTROL_ACK_1', 'HPD_INT_CONTROL_GEN_INT_ON_CON', + 'HPD_INT_CONTROL_GEN_INT_ON_DISCON', 'HPD_INT_CONTROL_POLARITY', + 'HPD_INT_CONTROL_RX_INT_ACK', 'HPD_INT_CONTROL_RX_INT_ACK_0', + 'HPD_INT_CONTROL_RX_INT_ACK_1', 'HPO_SRC0', 'HPO_SRC_RESERVED', + 'HPO_TOP_CLOCK_GATING_DIS', 'HPO_TOP_CLOCK_GATING_DISABLE', + 'HPO_TOP_CLOCK_GATING_EN', + 'HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0', + 'HPO_TOP_FEATURE_GATED_HDMICHARCLK0', + 'HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0', + 'HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0', + 'HPO_TOP_PERMANENT_DISPCLK', 'HPO_TOP_PERMANENT_HDMICHARCLK0', + 'HPO_TOP_PERMANENT_HDMISTREAMCLK0', 'HPO_TOP_PERMANENT_SOCCLK', + 'HPO_TOP_REGISTER_GATED_DISPCLK', + 'HPO_TOP_REGISTER_GATED_HDMICHARCLK0', + 'HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0', 'HPO_TOP_TEST_CLK_SEL', + 'HPO_TOP_TEST_CLOCK_RESERVED', + 'HSA_RUNTIME_CORE_INC_SDMA_REGISTERS_H_', 'HS_GS', 'HS_STAGE_OFF', + 'HS_STAGE_ON', 'HUBP_BLANK_EN', 'HUBP_BLANK_SW_ASSERT', + 'HUBP_BLANK_SW_DEASSERT', 'HUBP_IN_ACTIVE', 'HUBP_IN_BLANK', + 'HUBP_IN_VBLANK', 'HUBP_MEASURE_WIN_MODE_DCFCLK', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_0', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_1', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_2', + 'HUBP_MEASURE_WIN_MODE_DCFCLK_3', 'HUBP_NO_OUTSTANDING_REQ', + 'HUBP_SOFT_RESET', 'HUBP_SOFT_RESET_OFF', 'HUBP_SOFT_RESET_ON', + 'HUBP_TTU_DISABLE', 'HUBP_TTU_DISABLED', 'HUBP_TTU_ENABLED', + 'HUBP_VREADY_AT_OR_AFTER_VSYNC', 'HUBP_VTG_SEL', + 'HW_MIRRORING_DISABLE', 'HW_MIRRORING_ENABLE', 'H_MIRROR_EN', + 'Hdp_SurfaceEndian', 'ID_STREAM_DISABLE_ACKED', + 'ID_STREAM_DISABLE_NO_ACK', 'IHC_INTERRUPT_DEST', + 'IHC_INTERRUPT_LINE_STATUS', 'IH_CLIENT_TYPE', + 'IH_CLIENT_TYPE_RESERVED', 'IH_GFX_VMID_CLIENT', + 'IH_INTERFACE_TYPE', 'IH_LEGACY_INTERFACE', 'IH_MM_VMID_CLIENT', + 'IH_MULTI_VMID_CLIENT', 'IH_PERF_SEL', + 'IH_PERF_SEL_BIF_LINE0_FALLING', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF0', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF1', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF10', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF11', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF12', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF13', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF14', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF15', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF2', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF3', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF4', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF5', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF6', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF7', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF8', + 'IH_PERF_SEL_BIF_LINE0_FALLING_VF9', + 'IH_PERF_SEL_BIF_LINE0_RISING', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF0', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF1', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF10', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF11', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF12', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF13', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF14', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF15', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF2', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF3', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF4', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF5', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF6', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF7', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF8', + 'IH_PERF_SEL_BIF_LINE0_RISING_VF9', + 'IH_PERF_SEL_BUFFER_FIFO_FULL', 'IH_PERF_SEL_BUFFER_IDLE', + 'IH_PERF_SEL_CLIENT0_INT', 'IH_PERF_SEL_CLIENT10_INT', + 'IH_PERF_SEL_CLIENT11_INT', 'IH_PERF_SEL_CLIENT12_INT', + 'IH_PERF_SEL_CLIENT13_INT', 'IH_PERF_SEL_CLIENT14_INT', + 'IH_PERF_SEL_CLIENT15_INT', 'IH_PERF_SEL_CLIENT16_INT', + 'IH_PERF_SEL_CLIENT17_INT', 'IH_PERF_SEL_CLIENT18_INT', + 'IH_PERF_SEL_CLIENT19_INT', 'IH_PERF_SEL_CLIENT1_INT', + 'IH_PERF_SEL_CLIENT20_INT', 'IH_PERF_SEL_CLIENT21_INT', + 'IH_PERF_SEL_CLIENT22_INT', 'IH_PERF_SEL_CLIENT23_INT', + 'IH_PERF_SEL_CLIENT24_INT', 'IH_PERF_SEL_CLIENT25_INT', + 'IH_PERF_SEL_CLIENT26_INT', 'IH_PERF_SEL_CLIENT27_INT', + 'IH_PERF_SEL_CLIENT28_INT', 'IH_PERF_SEL_CLIENT29_INT', + 'IH_PERF_SEL_CLIENT2_INT', 'IH_PERF_SEL_CLIENT30_INT', + 'IH_PERF_SEL_CLIENT31_INT', 'IH_PERF_SEL_CLIENT3_INT', + 'IH_PERF_SEL_CLIENT4_INT', 'IH_PERF_SEL_CLIENT5_INT', + 'IH_PERF_SEL_CLIENT6_INT', 'IH_PERF_SEL_CLIENT7_INT', + 'IH_PERF_SEL_CLIENT8_INT', 'IH_PERF_SEL_CLIENT9_INT', + 'IH_PERF_SEL_CLIENT_CREDIT_ERROR', 'IH_PERF_SEL_COOKIE_REC_ERROR', + 'IH_PERF_SEL_CYCLE', 'IH_PERF_SEL_IDLE', 'IH_PERF_SEL_INPUT_IDLE', + 'IH_PERF_SEL_MC_WR_CLEAN_PENDING', + 'IH_PERF_SEL_MC_WR_CLEAN_STALL', 'IH_PERF_SEL_MC_WR_COUNT', + 'IH_PERF_SEL_MC_WR_IDLE', 'IH_PERF_SEL_MC_WR_STALL', + 'IH_PERF_SEL_RB0_FULL', 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8', + 'IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB0_FULL_VF0', + 'IH_PERF_SEL_RB0_FULL_VF1', 'IH_PERF_SEL_RB0_FULL_VF10', + 'IH_PERF_SEL_RB0_FULL_VF11', 'IH_PERF_SEL_RB0_FULL_VF12', + 'IH_PERF_SEL_RB0_FULL_VF13', 'IH_PERF_SEL_RB0_FULL_VF14', + 'IH_PERF_SEL_RB0_FULL_VF15', 'IH_PERF_SEL_RB0_FULL_VF2', + 'IH_PERF_SEL_RB0_FULL_VF3', 'IH_PERF_SEL_RB0_FULL_VF4', + 'IH_PERF_SEL_RB0_FULL_VF5', 'IH_PERF_SEL_RB0_FULL_VF6', + 'IH_PERF_SEL_RB0_FULL_VF7', 'IH_PERF_SEL_RB0_FULL_VF8', + 'IH_PERF_SEL_RB0_FULL_VF9', 'IH_PERF_SEL_RB0_LOAD_RPTR', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF1', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF10', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF11', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF12', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF13', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF14', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF2', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF4', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF6', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB0_LOAD_RPTR_VF8', + 'IH_PERF_SEL_RB0_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB0_OVERFLOW', + 'IH_PERF_SEL_RB0_OVERFLOW_VF0', 'IH_PERF_SEL_RB0_OVERFLOW_VF1', + 'IH_PERF_SEL_RB0_OVERFLOW_VF10', 'IH_PERF_SEL_RB0_OVERFLOW_VF11', + 'IH_PERF_SEL_RB0_OVERFLOW_VF12', 'IH_PERF_SEL_RB0_OVERFLOW_VF13', + 'IH_PERF_SEL_RB0_OVERFLOW_VF14', 'IH_PERF_SEL_RB0_OVERFLOW_VF15', + 'IH_PERF_SEL_RB0_OVERFLOW_VF2', 'IH_PERF_SEL_RB0_OVERFLOW_VF3', + 'IH_PERF_SEL_RB0_OVERFLOW_VF4', 'IH_PERF_SEL_RB0_OVERFLOW_VF5', + 'IH_PERF_SEL_RB0_OVERFLOW_VF6', 'IH_PERF_SEL_RB0_OVERFLOW_VF7', + 'IH_PERF_SEL_RB0_OVERFLOW_VF8', 'IH_PERF_SEL_RB0_OVERFLOW_VF9', + 'IH_PERF_SEL_RB0_RPTR_WRAP', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF0', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB0_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRAP', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB0_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB0_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB0_WPTR_WRITEBACK', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8', + 'IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9', 'IH_PERF_SEL_RB1_FULL', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8', + 'IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB1_FULL_VF0', + 'IH_PERF_SEL_RB1_FULL_VF1', 'IH_PERF_SEL_RB1_FULL_VF10', + 'IH_PERF_SEL_RB1_FULL_VF11', 'IH_PERF_SEL_RB1_FULL_VF12', + 'IH_PERF_SEL_RB1_FULL_VF13', 'IH_PERF_SEL_RB1_FULL_VF14', + 'IH_PERF_SEL_RB1_FULL_VF15', 'IH_PERF_SEL_RB1_FULL_VF2', + 'IH_PERF_SEL_RB1_FULL_VF3', 'IH_PERF_SEL_RB1_FULL_VF4', + 'IH_PERF_SEL_RB1_FULL_VF5', 'IH_PERF_SEL_RB1_FULL_VF6', + 'IH_PERF_SEL_RB1_FULL_VF7', 'IH_PERF_SEL_RB1_FULL_VF8', + 'IH_PERF_SEL_RB1_FULL_VF9', 'IH_PERF_SEL_RB1_LOAD_RPTR', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF1', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF10', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF11', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF12', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF13', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF14', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF2', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF4', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF6', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB1_LOAD_RPTR_VF8', + 'IH_PERF_SEL_RB1_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB1_OVERFLOW', + 'IH_PERF_SEL_RB1_OVERFLOW_VF0', 'IH_PERF_SEL_RB1_OVERFLOW_VF1', + 'IH_PERF_SEL_RB1_OVERFLOW_VF10', 'IH_PERF_SEL_RB1_OVERFLOW_VF11', + 'IH_PERF_SEL_RB1_OVERFLOW_VF12', 'IH_PERF_SEL_RB1_OVERFLOW_VF13', + 'IH_PERF_SEL_RB1_OVERFLOW_VF14', 'IH_PERF_SEL_RB1_OVERFLOW_VF15', + 'IH_PERF_SEL_RB1_OVERFLOW_VF2', 'IH_PERF_SEL_RB1_OVERFLOW_VF3', + 'IH_PERF_SEL_RB1_OVERFLOW_VF4', 'IH_PERF_SEL_RB1_OVERFLOW_VF5', + 'IH_PERF_SEL_RB1_OVERFLOW_VF6', 'IH_PERF_SEL_RB1_OVERFLOW_VF7', + 'IH_PERF_SEL_RB1_OVERFLOW_VF8', 'IH_PERF_SEL_RB1_OVERFLOW_VF9', + 'IH_PERF_SEL_RB1_RPTR_WRAP', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF0', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB1_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB1_WPTR_WRAP', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB1_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB1_WPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_FULL', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8', + 'IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9', 'IH_PERF_SEL_RB2_FULL_VF0', + 'IH_PERF_SEL_RB2_FULL_VF1', 'IH_PERF_SEL_RB2_FULL_VF10', + 'IH_PERF_SEL_RB2_FULL_VF11', 'IH_PERF_SEL_RB2_FULL_VF12', + 'IH_PERF_SEL_RB2_FULL_VF13', 'IH_PERF_SEL_RB2_FULL_VF14', + 'IH_PERF_SEL_RB2_FULL_VF15', 'IH_PERF_SEL_RB2_FULL_VF2', + 'IH_PERF_SEL_RB2_FULL_VF3', 'IH_PERF_SEL_RB2_FULL_VF4', + 'IH_PERF_SEL_RB2_FULL_VF5', 'IH_PERF_SEL_RB2_FULL_VF6', + 'IH_PERF_SEL_RB2_FULL_VF7', 'IH_PERF_SEL_RB2_FULL_VF8', + 'IH_PERF_SEL_RB2_FULL_VF9', 'IH_PERF_SEL_RB2_LOAD_RPTR', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF0', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF1', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF10', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF11', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF12', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF13', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF14', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF15', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF2', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF3', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF4', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF5', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF6', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF7', 'IH_PERF_SEL_RB2_LOAD_RPTR_VF8', + 'IH_PERF_SEL_RB2_LOAD_RPTR_VF9', 'IH_PERF_SEL_RB2_OVERFLOW', + 'IH_PERF_SEL_RB2_OVERFLOW_VF0', 'IH_PERF_SEL_RB2_OVERFLOW_VF1', + 'IH_PERF_SEL_RB2_OVERFLOW_VF10', 'IH_PERF_SEL_RB2_OVERFLOW_VF11', + 'IH_PERF_SEL_RB2_OVERFLOW_VF12', 'IH_PERF_SEL_RB2_OVERFLOW_VF13', + 'IH_PERF_SEL_RB2_OVERFLOW_VF14', 'IH_PERF_SEL_RB2_OVERFLOW_VF15', + 'IH_PERF_SEL_RB2_OVERFLOW_VF2', 'IH_PERF_SEL_RB2_OVERFLOW_VF3', + 'IH_PERF_SEL_RB2_OVERFLOW_VF4', 'IH_PERF_SEL_RB2_OVERFLOW_VF5', + 'IH_PERF_SEL_RB2_OVERFLOW_VF6', 'IH_PERF_SEL_RB2_OVERFLOW_VF7', + 'IH_PERF_SEL_RB2_OVERFLOW_VF8', 'IH_PERF_SEL_RB2_OVERFLOW_VF9', + 'IH_PERF_SEL_RB2_RPTR_WRAP', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF0', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF1', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF10', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF11', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF12', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF13', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF14', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF2', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF4', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF6', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_RPTR_WRAP_VF8', + 'IH_PERF_SEL_RB2_RPTR_WRAP_VF9', 'IH_PERF_SEL_RB2_WPTR_WRAP', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF0', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF1', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF10', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF11', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF12', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF13', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF14', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF15', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF2', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF3', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF4', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF5', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF6', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF7', 'IH_PERF_SEL_RB2_WPTR_WRAP_VF8', + 'IH_PERF_SEL_RB2_WPTR_WRAP_VF9', 'IH_PERF_SEL_SELF_IV_VALID', + 'IH_PERF_SEL_STORM_CLIENT_INT_DROP', + 'IH_REGISTER_WRITE_INTERFACE', 'IH_RING_ID', + 'IH_RING_ID_INTERRUPT', 'IH_RING_ID_REQUEST', + 'IH_RING_ID_RESERVED', 'IH_RING_ID_TRANSLATION', + 'IH_VF_RB_SELECT', 'IH_VF_RB_SELECT_CLIENT_FCN_ID', + 'IH_VF_RB_SELECT_IH_FCN_ID', 'IH_VF_RB_SELECT_PF', + 'IH_VF_RB_SELECT_RESERVED', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID', + 'IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID', + 'INDIRECT_BUFFER_VALID', 'INPUT_COVERAGE', 'INPUT_DEPTH_COVERAGE', + 'INPUT_FIFO_ERROR_TYPE', 'INPUT_INNER_COVERAGE', + 'INST_ID_ECC_INTERRUPT_MSG', 'INST_ID_HOST_REG_TRAP_MSG', + 'INST_ID_HW_TRAP', 'INST_ID_HW_TRAP_GET_TBA', 'INST_ID_KILL_SEQ', + 'INST_ID_PRIV_START', 'INST_ID_SPI_WREXEC', + 'INST_ID_TTRACE_NEW_PC_MSG', 'INTERRUPT_LINE_ASSERTED', + 'INTERRUPT_LINE_NOT_ASSERTED', 'INTERRUPT_SENT_TO_DMCUB', + 'INTERRUPT_SENT_TO_IH', 'INT_DISABLED', 'INT_ENABLED', + 'INT_LEVEL', 'INT_MASK', 'INT_PULSE', 'INVALID_REG_ACCESS_TYPE', + 'IQ_DEQUEUE_RETRY', 'IQ_INTR_TYPE_IB', 'IQ_INTR_TYPE_MQD', + 'IQ_INTR_TYPE_PQ', 'IQ_OFFLOAD_RETRY', 'IQ_QUEUE_SLEEP', + 'IQ_SCH_WAVE_MSG', 'IQ_SEM_REARM', 'JITTER_REMOVE_DISABLE', + 'LATE_Z', 'LB_ALPHA_DISABLE', 'LB_ALPHA_EN', 'LB_ALPHA_ENABLE', + 'LB_INTERLEAVE_DISABLE', 'LB_INTERLEAVE_EN', + 'LB_INTERLEAVE_ENABLE', 'LB_MEMORY_CONFIG', 'LB_MEMORY_CONFIG_0', + 'LB_MEMORY_CONFIG_1', 'LB_MEMORY_CONFIG_2', 'LB_MEMORY_CONFIG_3', + 'LEGACY_PIPE_INTERLEAVE', 'LEGACY_PIPE_INTERLEAVE_256B', + 'LEGACY_PIPE_INTERLEAVE_512B', 'LINESTRIP', 'LOOSE_PACK', + 'LSDMA_PERF_SEL', 'LSDMA_PERF_SEL_ATCL2_FREE', + 'LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH', + 'LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH', + 'LSDMA_PERF_SEL_ATCL2_RET_ACK', 'LSDMA_PERF_SEL_ATCL2_RET_XNACK', + 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ', + 'LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET', + 'LSDMA_PERF_SEL_CE_AFIFO_FULL', 'LSDMA_PERF_SEL_CE_BUSY', + 'LSDMA_PERF_SEL_CE_BUSY_END', 'LSDMA_PERF_SEL_CE_BUSY_START', + 'LSDMA_PERF_SEL_CE_DST_IDLE', 'LSDMA_PERF_SEL_CE_INFO1_FULL', + 'LSDMA_PERF_SEL_CE_INFO_FULL', 'LSDMA_PERF_SEL_CE_IN_IDLE', + 'LSDMA_PERF_SEL_CE_L1_STALL', 'LSDMA_PERF_SEL_CE_L1_WR_VLD', + 'LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND', + 'LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ', + 'LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET', + 'LSDMA_PERF_SEL_CE_OUT_IDLE', 'LSDMA_PERF_SEL_CE_RD_STALL', + 'LSDMA_PERF_SEL_CE_RREQ_IDLE', 'LSDMA_PERF_SEL_CE_SPLIT_IDLE', + 'LSDMA_PERF_SEL_CE_WREQ_IDLE', 'LSDMA_PERF_SEL_CE_WR_IDLE', + 'LSDMA_PERF_SEL_CE_WR_STALL', 'LSDMA_PERF_SEL_CMD_OP_END', + 'LSDMA_PERF_SEL_CMD_OP_MATCH', 'LSDMA_PERF_SEL_CMD_OP_START', + 'LSDMA_PERF_SEL_CTX_CHANGE', + 'LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 'LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'LSDMA_PERF_SEL_CYCLE', + 'LSDMA_PERF_SEL_DMA_L1_RD_SEND', 'LSDMA_PERF_SEL_DMA_L1_WR_SEND', + 'LSDMA_PERF_SEL_DMA_MC_RD_SEND', 'LSDMA_PERF_SEL_DMA_MC_WR_SEND', + 'LSDMA_PERF_SEL_DOORBELL', 'LSDMA_PERF_SEL_DRAM_ECC', + 'LSDMA_PERF_SEL_EX_IDLE', + 'LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'LSDMA_PERF_SEL_F32_L1_WR_VLD', + 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 'LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 'LSDMA_PERF_SEL_GFX_SELECT', 'LSDMA_PERF_SEL_IB_CMD_FULL', + 'LSDMA_PERF_SEL_IB_CMD_IDLE', 'LSDMA_PERF_SEL_IB_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_IB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_IDLE', + 'LSDMA_PERF_SEL_INT_IDLE', 'LSDMA_PERF_SEL_INT_REQ_COUNT', + 'LSDMA_PERF_SEL_INT_REQ_STALL', + 'LSDMA_PERF_SEL_INT_RESP_ACCEPTED', + 'LSDMA_PERF_SEL_INT_RESP_RETRY', + 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD', + 'LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR', + 'LSDMA_PERF_SEL_L1_INV_MIDDLE', 'LSDMA_PERF_SEL_L1_RDL2_IDLE', + 'LSDMA_PERF_SEL_L1_RDMC_IDLE', 'LSDMA_PERF_SEL_L1_RD_FIFO_IDLE', + 'LSDMA_PERF_SEL_L1_RD_INV_EN', 'LSDMA_PERF_SEL_L1_RD_INV_IDLE', + 'LSDMA_PERF_SEL_L1_RD_WAIT_INVADR', + 'LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT', + 'LSDMA_PERF_SEL_L1_WRL2_IDLE', 'LSDMA_PERF_SEL_L1_WRMC_IDLE', + 'LSDMA_PERF_SEL_L1_WR_FIFO_IDLE', 'LSDMA_PERF_SEL_L1_WR_INV_EN', + 'LSDMA_PERF_SEL_L1_WR_INV_IDLE', + 'LSDMA_PERF_SEL_L1_WR_WAIT_INVADR', + 'LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT', + 'LSDMA_PERF_SEL_MC_RD_COUNT', 'LSDMA_PERF_SEL_MC_RD_IDLE', + 'LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 'LSDMA_PERF_SEL_MC_RD_RET_STALL', 'LSDMA_PERF_SEL_MC_WR_COUNT', + 'LSDMA_PERF_SEL_MC_WR_IDLE', + 'LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID', + 'LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID', + 'LSDMA_PERF_SEL_NACK_GEN_ERR', 'LSDMA_PERF_SEL_NUM_PACKET', + 'LSDMA_PERF_SEL_PAGE_SELECT', 'LSDMA_PERF_SEL_RB_CMD_FULL', + 'LSDMA_PERF_SEL_RB_CMD_IDLE', 'LSDMA_PERF_SEL_RB_EMPTY', + 'LSDMA_PERF_SEL_RB_FULL', 'LSDMA_PERF_SEL_RB_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_RB_MMHUB_RD_RET', 'LSDMA_PERF_SEL_RB_RPTR_WB', + 'LSDMA_PERF_SEL_RB_RPTR_WRAP', 'LSDMA_PERF_SEL_RB_WPTR_POLL_READ', + 'LSDMA_PERF_SEL_RB_WPTR_WRAP', 'LSDMA_PERF_SEL_RD_BA_RTR', + 'LSDMA_PERF_SEL_REG_IDLE', 'LSDMA_PERF_SEL_RLC0_SELECT', + 'LSDMA_PERF_SEL_RLC1_SELECT', 'LSDMA_PERF_SEL_SDMA_ATCL2_SEND', + 'LSDMA_PERF_SEL_SDMA_INVACK_FLUSH', + 'LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH', 'LSDMA_PERF_SEL_SEM_IDLE', + 'LSDMA_PERF_SEL_SEM_REQ_COUNT', 'LSDMA_PERF_SEL_SEM_REQ_STALL', + 'LSDMA_PERF_SEL_SEM_RESP_FAIL', + 'LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 'LSDMA_PERF_SEL_SEM_RESP_PASS', 'LSDMA_PERF_SEL_SRBM_REG_SEND', + 'LSDMA_PERF_SEL_UTCL1_UTCL2_REQ', + 'LSDMA_PERF_SEL_UTCL1_UTCL2_RET', + 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ', + 'LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET', 'LSDMA_PERF_SEL_WR_BA_RTR', + 'LS_STAGE_OFF', 'LS_STAGE_ON', 'LUT_2CFG_MEMORY_A', + 'LUT_2CFG_MEMORY_B', 'LUT_2CFG_NO_MEMORY', 'LUT_2_MODE_BYPASS', + 'LUT_2_MODE_RAMA_LUT', 'LUT_2_MODE_RAMB_LUT', 'LUT_4CFG_MEMORY_A', + 'LUT_4CFG_MEMORY_B', 'LUT_4CFG_NO_MEMORY', 'LUT_4CFG_ROM_A', + 'LUT_4CFG_ROM_B', 'LUT_4_MODE_BYPASS', 'LUT_4_MODE_RAMA_LUT', + 'LUT_4_MODE_RAMB_LUT', 'LUT_4_MODE_ROMA_LUT', + 'LUT_4_MODE_ROMB_LUT', 'LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS', + 'LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH', + 'LVTMA_RANDOM_PATTERN_SEED_RAN_PAT', + 'MASTER_UPDATE_LOCK_DB_FIELD_BOTH', + 'MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM', + 'MASTER_UPDATE_LOCK_DB_FIELD_RESERVED', + 'MASTER_UPDATE_LOCK_DB_FIELD_TOP', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED', + 'MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE', + 'MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE', + 'MASTER_UPDATE_LOCK_SEL', 'MASTER_UPDATE_LOCK_SEL_0', + 'MASTER_UPDATE_LOCK_SEL_1', 'MASTER_UPDATE_LOCK_SEL_2', + 'MASTER_UPDATE_LOCK_SEL_3', 'MASTER_UPDATE_LOCK_SEL_RESERVED4', + 'MASTER_UPDATE_LOCK_SEL_RESERVED5', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED', + 'MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP', + 'MAX_INSTANCE', 'MAX_SEGMENT', 'MEM_ARB_MODE_AGE', + 'MEM_ARB_MODE_BOTH', 'MEM_ARB_MODE_FIXED', 'MEM_ARB_MODE_WEIGHT', + 'MEM_POWER_DIS_MODE_DISABLE', 'MEM_POWER_DIS_MODE_ENABLE', + 'MEM_POWER_FORCE_MODE_DEEP_SLEEP', + 'MEM_POWER_FORCE_MODE_LIGHT_SLEEP', 'MEM_POWER_FORCE_MODE_OFF', + 'MEM_POWER_FORCE_MODE_SHUT_DOWN', 'MEM_POWER_STATUS_DEEP_SLEEP', + 'MEM_POWER_STATUS_LIGHT_SLEEP', 'MEM_POWER_STATUS_ON', + 'MEM_POWER_STATUS_SHUT_DOWN', 'MEM_PWR_DIS_CTRL', + 'MEM_PWR_DIS_MODE', 'MEM_PWR_FORCE_CTRL', 'MEM_PWR_FORCE_CTRL2', + 'MEM_PWR_FORCE_MODE', 'MEM_PWR_SEL_CTRL', 'MEM_PWR_SEL_CTRL2', + 'MEM_PWR_STATUS', 'METADATA_HUBP_SEL', 'METADATA_HUBP_SEL_0', + 'METADATA_HUBP_SEL_1', 'METADATA_HUBP_SEL_2', + 'METADATA_HUBP_SEL_3', 'METADATA_HUBP_SEL_RESERVED', + 'METADATA_STREAM_DP', 'METADATA_STREAM_DVE', + 'METADATA_STREAM_TYPE_SEL', 'META_CHUNK_SIZE', + 'META_CHUNK_SIZE_1KB', 'META_CHUNK_SIZE_2KB', + 'META_CHUNK_SIZE_4KB', 'META_CHUNK_SIZE_8KB', 'META_LINEAR', + 'META_SURF_LINEAR', 'META_SURF_TILED', 'ME_ID0', 'ME_ID1', + 'ME_ID2', 'ME_ID3', 'MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', + 'MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL', + 'MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK', + 'MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN', + 'MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL', 'MIN_CHUNK_SIZE', + 'MIN_CHUNK_SIZE_1024B', 'MIN_CHUNK_SIZE_256B', + 'MIN_CHUNK_SIZE_512B', 'MIN_META_CHUNK_SIZE', + 'MIN_META_CHUNK_SIZE_128B', 'MIN_META_CHUNK_SIZE_256B', + 'MIN_META_CHUNK_SIZE_64B', 'MMHUB_BASE', 'MMHUB_BASE__INST0_SEG0', + 'MMHUB_BASE__INST0_SEG1', 'MMHUB_BASE__INST0_SEG2', + 'MMHUB_BASE__INST0_SEG3', 'MMHUB_BASE__INST0_SEG4', + 'MMHUB_BASE__INST1_SEG0', 'MMHUB_BASE__INST1_SEG1', + 'MMHUB_BASE__INST1_SEG2', 'MMHUB_BASE__INST1_SEG3', + 'MMHUB_BASE__INST1_SEG4', 'MMHUB_BASE__INST2_SEG0', + 'MMHUB_BASE__INST2_SEG1', 'MMHUB_BASE__INST2_SEG2', + 'MMHUB_BASE__INST2_SEG3', 'MMHUB_BASE__INST2_SEG4', + 'MMHUB_BASE__INST3_SEG0', 'MMHUB_BASE__INST3_SEG1', + 'MMHUB_BASE__INST3_SEG2', 'MMHUB_BASE__INST3_SEG3', + 'MMHUB_BASE__INST3_SEG4', 'MMHUB_BASE__INST4_SEG0', + 'MMHUB_BASE__INST4_SEG1', 'MMHUB_BASE__INST4_SEG2', + 'MMHUB_BASE__INST4_SEG3', 'MMHUB_BASE__INST4_SEG4', + 'MMHUB_BASE__INST5_SEG0', 'MMHUB_BASE__INST5_SEG1', + 'MMHUB_BASE__INST5_SEG2', 'MMHUB_BASE__INST5_SEG3', + 'MMHUB_BASE__INST5_SEG4', 'MMHUB_BASE__INST6_SEG0', + 'MMHUB_BASE__INST6_SEG1', 'MMHUB_BASE__INST6_SEG2', + 'MMHUB_BASE__INST6_SEG3', 'MMHUB_BASE__INST6_SEG4', 'MONO_10LSB', + 'MONO_10MSB', 'MONO_12LSB', 'MONO_12MSB', 'MONO_16', 'MONO_2BIT', + 'MONO_8', 'MP0_BASE', 'MP0_BASE__INST0_SEG0', 'MP0_BASE__INST0_SEG1', 'MP0_BASE__INST0_SEG2', 'MP0_BASE__INST0_SEG3', 'MP0_BASE__INST0_SEG4', 'MP0_BASE__INST1_SEG0', 'MP0_BASE__INST1_SEG1', @@ -14053,7 +66082,189 @@ __all__ = \ 'MP1_BASE__INST5_SEG3', 'MP1_BASE__INST5_SEG4', 'MP1_BASE__INST6_SEG0', 'MP1_BASE__INST6_SEG1', 'MP1_BASE__INST6_SEG2', 'MP1_BASE__INST6_SEG3', - 'MP1_BASE__INST6_SEG4', 'NBIO_BASE', 'NBIO_BASE__INST0_SEG0', + 'MP1_BASE__INST6_SEG4', 'MPCC_BG_COLOR_BPC', + 'MPCC_BG_COLOR_BPC_10bit', 'MPCC_BG_COLOR_BPC_11bit', + 'MPCC_BG_COLOR_BPC_12bit', 'MPCC_BG_COLOR_BPC_8bit', + 'MPCC_BG_COLOR_BPC_9bit', 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE', + 'MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN', + 'MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE', + 'MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0', + 'MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1', 'MPCC_CONTROL_MPCC_MODE', + 'MPCC_CONTROL_MPCC_MODE_BYPASS', + 'MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING', + 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY', + 'MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH', + 'MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM', + 'MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13', + 'MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12', 'MPCC_GAMUT_REMAP_MODE_0', + 'MPCC_GAMUT_REMAP_MODE_1', 'MPCC_GAMUT_REMAP_MODE_2', + 'MPCC_GAMUT_REMAP_MODE_ENUM', 'MPCC_GAMUT_REMAP_MODE_RSV', + 'MPCC_MCM_3DLUT_17CUBE', 'MPCC_MCM_3DLUT_30BIT', + 'MPCC_MCM_3DLUT_30BIT_ENUM', 'MPCC_MCM_3DLUT_36BIT', + 'MPCC_MCM_3DLUT_9CUBE', 'MPCC_MCM_3DLUT_RAM_SEL', + 'MPCC_MCM_3DLUT_SIZE_ENUM', 'MPCC_MCM_GAMMA_LUT_BYPASS', + 'MPCC_MCM_GAMMA_LUT_DISABLE_PWL', 'MPCC_MCM_GAMMA_LUT_ENABLE_PWL', + 'MPCC_MCM_GAMMA_LUT_MODE_ENUM', + 'MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM', 'MPCC_MCM_GAMMA_LUT_RAMA', + 'MPCC_MCM_GAMMA_LUT_RAMB', 'MPCC_MCM_GAMMA_LUT_RAM_LUT', + 'MPCC_MCM_GAMMA_LUT_RESERVED_1', 'MPCC_MCM_GAMMA_LUT_RESERVED_3', + 'MPCC_MCM_GAMMA_LUT_SEL_ENUM', 'MPCC_MCM_LUT_2_MODE_BYPASS', + 'MPCC_MCM_LUT_2_MODE_ENUM', 'MPCC_MCM_LUT_2_MODE_RAMA_LUT', + 'MPCC_MCM_LUT_2_MODE_RAMB_LUT', 'MPCC_MCM_LUT_ALL_USE_R', + 'MPCC_MCM_LUT_BLUE_LUT', 'MPCC_MCM_LUT_CONFIG_MODE', + 'MPCC_MCM_LUT_DIFFERENT_RGB', 'MPCC_MCM_LUT_DISABLE_DEBUG', + 'MPCC_MCM_LUT_ENABLE_DEBUG', 'MPCC_MCM_LUT_GREEN_LUT', + 'MPCC_MCM_LUT_NUM_SEG', 'MPCC_MCM_LUT_RAMA_ACCESS', + 'MPCC_MCM_LUT_RAMB_ACCESS', 'MPCC_MCM_LUT_RAM_SEL', + 'MPCC_MCM_LUT_READ_COLOR_SEL', 'MPCC_MCM_LUT_READ_DBG', + 'MPCC_MCM_LUT_RED_LUT', 'MPCC_MCM_LUT_SEGMENTS_1', + 'MPCC_MCM_LUT_SEGMENTS_128', 'MPCC_MCM_LUT_SEGMENTS_16', + 'MPCC_MCM_LUT_SEGMENTS_2', 'MPCC_MCM_LUT_SEGMENTS_32', + 'MPCC_MCM_LUT_SEGMENTS_4', 'MPCC_MCM_LUT_SEGMENTS_64', + 'MPCC_MCM_LUT_SEGMENTS_8', 'MPCC_MCM_MEM_PWR_FORCE_DIS', + 'MPCC_MCM_MEM_PWR_FORCE_DS', 'MPCC_MCM_MEM_PWR_FORCE_ENUM', + 'MPCC_MCM_MEM_PWR_FORCE_LS', 'MPCC_MCM_MEM_PWR_FORCE_SD', + 'MPCC_MCM_MEM_PWR_STATE_DS', 'MPCC_MCM_MEM_PWR_STATE_ENUM', + 'MPCC_MCM_MEM_PWR_STATE_LS', 'MPCC_MCM_MEM_PWR_STATE_ON', + 'MPCC_MCM_MEM_PWR_STATE_SD', 'MPCC_MCM_RAM0_ACCESS', + 'MPCC_MCM_RAM1_ACCESS', 'MPCC_MCM_RAM2_ACCESS', + 'MPCC_MCM_RAM3_ACCESS', 'MPCC_OGAM_ALL_USE_R', + 'MPCC_OGAM_BLUE_LUT', 'MPCC_OGAM_DIFFERENT_RGB', + 'MPCC_OGAM_DISABLE_DEBUG', 'MPCC_OGAM_DISABLE_PWL', + 'MPCC_OGAM_ENABLE_DEBUG', 'MPCC_OGAM_ENABLE_PWL', + 'MPCC_OGAM_GREEN_LUT', 'MPCC_OGAM_LUT_2CFG_MEMORY_A', + 'MPCC_OGAM_LUT_2CFG_MEMORY_B', 'MPCC_OGAM_LUT_2CFG_NO_MEMORY', + 'MPCC_OGAM_LUT_2_CONFIG_ENUM', 'MPCC_OGAM_LUT_CONFIG_MODE', + 'MPCC_OGAM_LUT_PWL_DISABLE_ENUM', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA', + 'MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB', + 'MPCC_OGAM_LUT_RAM_SEL', 'MPCC_OGAM_LUT_READ_COLOR_SEL', + 'MPCC_OGAM_LUT_READ_DBG', 'MPCC_OGAM_LUT_SEL_ENUM', + 'MPCC_OGAM_MODE_0', 'MPCC_OGAM_MODE_2', + 'MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM', 'MPCC_OGAM_MODE_RSV', + 'MPCC_OGAM_MODE_RSV1', 'MPCC_OGAM_NUM_SEG', 'MPCC_OGAM_RAMA', + 'MPCC_OGAM_RAMA_ACCESS', 'MPCC_OGAM_RAMB', + 'MPCC_OGAM_RAMB_ACCESS', 'MPCC_OGAM_RED_LUT', + 'MPCC_OGAM_SEGMENTS_1', 'MPCC_OGAM_SEGMENTS_128', + 'MPCC_OGAM_SEGMENTS_16', 'MPCC_OGAM_SEGMENTS_2', + 'MPCC_OGAM_SEGMENTS_32', 'MPCC_OGAM_SEGMENTS_4', + 'MPCC_OGAM_SEGMENTS_64', 'MPCC_OGAM_SEGMENTS_8', + 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN', + 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE', + 'MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_EN', 'MPCC_SM_CONTROL_MPCC_SM_EN_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_EN_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE', + 'MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE', + 'MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE', + 'MPCC_SM_CONTROL_MPCC_SM_MODE', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING', + 'MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE', + 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN', + 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE', + 'MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE', + 'MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE', 'MPC_CFG_MPC_TEST_CLK_SEL', + 'MPC_CFG_MPC_TEST_CLK_SEL_0', 'MPC_CFG_MPC_TEST_CLK_SEL_1', + 'MPC_CFG_MPC_TEST_CLK_SEL_2', 'MPC_CFG_MPC_TEST_CLK_SEL_3', + 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN', + 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE', + 'MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE', + 'MPC_CRC_CALC_INTERLACE_MODE', 'MPC_CRC_CALC_MODE', + 'MPC_CRC_CALC_STEREO_MODE', 'MPC_CRC_CONTINUOUS_MODE', + 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM', + 'MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH', + 'MPC_CRC_INTERLACE_MODE_BOTTOM', 'MPC_CRC_INTERLACE_MODE_TOP', + 'MPC_CRC_ONE_SHOT_MODE', 'MPC_CRC_SOURCE_SELECT', + 'MPC_CRC_SOURCE_SEL_DPP', 'MPC_CRC_SOURCE_SEL_DWB', + 'MPC_CRC_SOURCE_SEL_OPP', 'MPC_CRC_SOURCE_SEL_OTHER', + 'MPC_CRC_STEREO_MODE_BOTH_RESET_EACH', + 'MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT', + 'MPC_CRC_STEREO_MODE_LEFT', 'MPC_CRC_STEREO_MODE_RIGHT', + 'MPC_DEBUG_BUS1_DATA_SELECT', + 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG', + 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT', + 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV', + 'MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1', + 'MPC_DEBUG_BUS2_DATA_SELECT', 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC', + 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT', + 'MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM', + 'MPC_DEBUG_BUS2_DATA_SELECT_RES', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA', + 'MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA', + 'MPC_DEBUG_BUS_MPCC_BYTE0', 'MPC_DEBUG_BUS_MPCC_BYTE1', + 'MPC_DEBUG_BUS_MPCC_BYTE2', 'MPC_DEBUG_BUS_MPCC_BYTE3', + 'MPC_DEBUG_BUS_MPCC_BYTE_SELECT', 'MPC_OCSC_COEF_FORMAT', + 'MPC_OCSC_COEF_FORMAT_S2_13', 'MPC_OCSC_COEF_FORMAT_S3_12', + 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN', + 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE', + 'MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE', + 'MPC_OUT_CSC_MODE', 'MPC_OUT_CSC_MODE_0', 'MPC_OUT_CSC_MODE_1', + 'MPC_OUT_CSC_MODE_2', 'MPC_OUT_CSC_MODE_RSV', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE', + 'MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH', + 'MPC_OUT_RATE_CONTROL_DISABLE_SET', + 'MPC_OUT_RATE_CONTROL_SET_DISABLE', + 'MPC_OUT_RATE_CONTROL_SET_ENABLE', + 'MSA_V_TIMING_OVERRIDE_DISABLED', 'MSA_V_TIMING_OVERRIDE_ENABLED', + 'MTYPE', 'MTYPE_CC', 'MTYPE_C_RO_S', 'MTYPE_C_RO_US', + 'MTYPE_C_RW_S', 'MTYPE_C_RW_US', 'MTYPE_NC', 'MTYPE_RESERVED_1', + 'MTYPE_RESERVED_5', 'MTYPE_RESERVED_7', 'MTYPE_UC', 'MTYPE_WC', + 'MULTIPLE_BY1', 'MULTIPLE_BY2', 'MULTIPLE_BY3_RESERVED', + 'MULTIPLE_BY4', 'MULTIPLE_RESERVED', 'MULT_16', 'MULT_8', + 'MemArbMode', 'NBIO_BASE', 'NBIO_BASE__INST0_SEG0', 'NBIO_BASE__INST0_SEG1', 'NBIO_BASE__INST0_SEG2', 'NBIO_BASE__INST0_SEG3', 'NBIO_BASE__INST0_SEG4', 'NBIO_BASE__INST1_SEG0', 'NBIO_BASE__INST1_SEG1', @@ -14070,28 +66281,621 @@ __all__ = \ 'NBIO_BASE__INST5_SEG2', 'NBIO_BASE__INST5_SEG3', 'NBIO_BASE__INST5_SEG4', 'NBIO_BASE__INST6_SEG0', 'NBIO_BASE__INST6_SEG1', 'NBIO_BASE__INST6_SEG2', - 'NBIO_BASE__INST6_SEG3', 'NBIO_BASE__INST6_SEG4', 'NVD_H', - 'OSSSYS_BASE', 'OSSSYS_BASE__INST0_SEG0', - 'OSSSYS_BASE__INST0_SEG1', 'OSSSYS_BASE__INST0_SEG2', - 'OSSSYS_BASE__INST0_SEG3', 'OSSSYS_BASE__INST0_SEG4', - 'OSSSYS_BASE__INST1_SEG0', 'OSSSYS_BASE__INST1_SEG1', - 'OSSSYS_BASE__INST1_SEG2', 'OSSSYS_BASE__INST1_SEG3', - 'OSSSYS_BASE__INST1_SEG4', 'OSSSYS_BASE__INST2_SEG0', - 'OSSSYS_BASE__INST2_SEG1', 'OSSSYS_BASE__INST2_SEG2', - 'OSSSYS_BASE__INST2_SEG3', 'OSSSYS_BASE__INST2_SEG4', - 'OSSSYS_BASE__INST3_SEG0', 'OSSSYS_BASE__INST3_SEG1', - 'OSSSYS_BASE__INST3_SEG2', 'OSSSYS_BASE__INST3_SEG3', - 'OSSSYS_BASE__INST3_SEG4', 'OSSSYS_BASE__INST4_SEG0', - 'OSSSYS_BASE__INST4_SEG1', 'OSSSYS_BASE__INST4_SEG2', - 'OSSSYS_BASE__INST4_SEG3', 'OSSSYS_BASE__INST4_SEG4', - 'OSSSYS_BASE__INST5_SEG0', 'OSSSYS_BASE__INST5_SEG1', - 'OSSSYS_BASE__INST5_SEG2', 'OSSSYS_BASE__INST5_SEG3', - 'OSSSYS_BASE__INST5_SEG4', 'OSSSYS_BASE__INST6_SEG0', - 'OSSSYS_BASE__INST6_SEG1', 'OSSSYS_BASE__INST6_SEG2', - 'OSSSYS_BASE__INST6_SEG3', 'OSSSYS_BASE__INST6_SEG4', - 'PACKET2_PAD_MASK', 'PACKET2_PAD_SHIFT', 'PACKET3_ACQUIRE_MEM', - 'PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA', 'PACKET3_AQL_PACKET', - 'PACKET3_ATOMIC_GDS', 'PACKET3_ATOMIC_MEM', + 'NBIO_BASE__INST6_SEG3', 'NBIO_BASE__INST6_SEG4', 'NON_BYPASS', + 'NOT_FORCE_THE_CLOCK_DISABLED', 'NOT_SENT', 'NO_DIST', 'NO_DIV', + 'NO_FORCE', 'NO_FORCE_REQ', 'NO_FORCE_REQUEST', + 'NO_MIN_CHUNK_SIZE', 'NO_MIN_META_CHUNK_SIZE', + 'NO_OUTSTANDING_REQ', 'NUM_SIMD_PER_CU', 'NVD_H', + 'OBUF_BYPASS_DIS', 'OBUF_BYPASS_EN', 'OBUF_BYPASS_SEL', + 'OBUF_FULL', 'OBUF_FULL_RECOUT', 'OBUF_HALF_RECOUT', + 'OBUF_IS_HALF_RECOUT_WIDTH_SEL', 'OBUF_RECOUT', + 'OBUF_USE_FULL_BUFFER_SEL', 'OFFCHIP_HS_DEALLOC', 'OFF_SEQ', + 'OKAY', 'OKAY_NODATA', 'OMODE_BLEND', 'OMODE_O_THEN_B', + 'OMODE_P_THEN_O_THEN_B', 'OMODE_RESERVED_3', 'ON_SEQ', + 'OPPBUF_DISPLAY_SEGMENTATION', + 'OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT', + 'OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT', + 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT', + 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT', + 'OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT', + 'OPP_ABM_DEBUG_BUS_SELECT_CONTROL', + 'OPP_DPG_DEBUG_BUS_SELECT_CONTROL', + 'OPP_FMT_DEBUG_BUS_SELECT_CONTROL', + 'OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL', + 'OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL', 'OPP_PIPE_CLOCK_DISABLE', + 'OPP_PIPE_CLOCK_ENABLE', 'OPP_PIPE_CLOCK_ENABLE_CONTROL', + 'OPP_PIPE_CRC_CONT_EN', 'OPP_PIPE_CRC_DISABLE', 'OPP_PIPE_CRC_EN', + 'OPP_PIPE_CRC_ENABLE', 'OPP_PIPE_CRC_INTERLACE_EN', + 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED', + 'OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE', + 'OPP_PIPE_CRC_INTERLACE_MODE', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD', + 'OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM', + 'OPP_PIPE_CRC_INTERLACE_MODE_TOP', 'OPP_PIPE_CRC_MODE_CONTINUOUS', + 'OPP_PIPE_CRC_MODE_ONE_SHOT', 'OPP_PIPE_CRC_ONE_SHOT_PENDING', + 'OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING', + 'OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING', + 'OPP_PIPE_CRC_PIXEL_SELECT', + 'OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS', + 'OPP_PIPE_CRC_PIXEL_SELECT_RESERVED', + 'OPP_PIPE_CRC_SOURCE_SELECT', 'OPP_PIPE_CRC_SOURCE_SELECT_FMT', + 'OPP_PIPE_CRC_SOURCE_SELECT_SFT', 'OPP_PIPE_CRC_STEREO_EN', + 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO', + 'OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO', + 'OPP_PIPE_CRC_STEREO_MODE', + 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE', + 'OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE', + 'OPP_PIPE_CRC_STEREO_MODE_LEFT', 'OPP_PIPE_CRC_STEREO_MODE_RIGHT', + 'OPP_PIPE_DIGTIAL_BYPASS_CONTROL', + 'OPP_PIPE_DIGTIAL_BYPASS_DISABLE', + 'OPP_PIPE_DIGTIAL_BYPASS_ENABLE', 'OPP_TEST_CLK_SEL_CONTROL', + 'OPP_TEST_CLK_SEL_DISPCLK_ABM0', 'OPP_TEST_CLK_SEL_DISPCLK_ABM1', + 'OPP_TEST_CLK_SEL_DISPCLK_ABM2', 'OPP_TEST_CLK_SEL_DISPCLK_ABM3', + 'OPP_TEST_CLK_SEL_DISPCLK_OPP0', 'OPP_TEST_CLK_SEL_DISPCLK_OPP1', + 'OPP_TEST_CLK_SEL_DISPCLK_OPP2', 'OPP_TEST_CLK_SEL_DISPCLK_OPP3', + 'OPP_TEST_CLK_SEL_DISPCLK_P', 'OPP_TEST_CLK_SEL_DISPCLK_R', + 'OPP_TEST_CLK_SEL_RESERVED0', 'OPP_TEST_CLK_SEL_RESERVED1', + 'OPP_TEST_CLK_SEL_RESERVED2', 'OPP_TEST_CLK_SEL_RESERVED3', + 'OPP_TOP_CLOCK_DISABLED_STATUS', 'OPP_TOP_CLOCK_ENABLED_STATUS', + 'OPP_TOP_CLOCK_ENABLE_STATUS', 'OPP_TOP_CLOCK_GATING_CONTROL', + 'OPP_TOP_CLOCK_GATING_DISABLED', 'OPP_TOP_CLOCK_GATING_ENABLED', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4', + 'OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5', + 'OPT_COMB_ADD', 'OPT_COMB_BLEND_DISABLED', 'OPT_COMB_MAX', + 'OPT_COMB_MIN', 'OPT_COMB_NONE', 'OPT_COMB_REVSUBTRACT', + 'OPT_COMB_SAFE_ADD', 'OPT_COMB_SUBTRACT', 'OSSSYS_BASE', + 'OSSSYS_BASE__INST0_SEG0', 'OSSSYS_BASE__INST0_SEG1', + 'OSSSYS_BASE__INST0_SEG2', 'OSSSYS_BASE__INST0_SEG3', + 'OSSSYS_BASE__INST0_SEG4', 'OSSSYS_BASE__INST1_SEG0', + 'OSSSYS_BASE__INST1_SEG1', 'OSSSYS_BASE__INST1_SEG2', + 'OSSSYS_BASE__INST1_SEG3', 'OSSSYS_BASE__INST1_SEG4', + 'OSSSYS_BASE__INST2_SEG0', 'OSSSYS_BASE__INST2_SEG1', + 'OSSSYS_BASE__INST2_SEG2', 'OSSSYS_BASE__INST2_SEG3', + 'OSSSYS_BASE__INST2_SEG4', 'OSSSYS_BASE__INST3_SEG0', + 'OSSSYS_BASE__INST3_SEG1', 'OSSSYS_BASE__INST3_SEG2', + 'OSSSYS_BASE__INST3_SEG3', 'OSSSYS_BASE__INST3_SEG4', + 'OSSSYS_BASE__INST4_SEG0', 'OSSSYS_BASE__INST4_SEG1', + 'OSSSYS_BASE__INST4_SEG2', 'OSSSYS_BASE__INST4_SEG3', + 'OSSSYS_BASE__INST4_SEG4', 'OSSSYS_BASE__INST5_SEG0', + 'OSSSYS_BASE__INST5_SEG1', 'OSSSYS_BASE__INST5_SEG2', + 'OSSSYS_BASE__INST5_SEG3', 'OSSSYS_BASE__INST5_SEG4', + 'OSSSYS_BASE__INST6_SEG0', 'OSSSYS_BASE__INST6_SEG1', + 'OSSSYS_BASE__INST6_SEG2', 'OSSSYS_BASE__INST6_SEG3', + 'OSSSYS_BASE__INST6_SEG4', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE', + 'OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED', + 'OTG_ADD_PIXEL', 'OTG_ADD_PIXEL_FORCE', 'OTG_ADD_PIXEL_NOOP', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST', + 'OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP', + 'OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE', + 'OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE', + 'OTG_CONTROL_OTG_MASTER_EN', 'OTG_CONTROL_OTG_MASTER_EN_FALSE', + 'OTG_CONTROL_OTG_MASTER_EN_TRUE', 'OTG_CONTROL_OTG_OUT_MUX', + 'OTG_CONTROL_OTG_OUT_MUX_0', 'OTG_CONTROL_OTG_OUT_MUX_1', + 'OTG_CONTROL_OTG_OUT_MUX_2', 'OTG_CONTROL_OTG_START_POINT_CNTL', + 'OTG_CONTROL_OTG_START_POINT_CNTL_DP', + 'OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE', + 'OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC1_EN', 'OTG_CRC_CNTL_OTG_CRC1_EN_FALSE', + 'OTG_CRC_CNTL_OTG_CRC1_EN_TRUE', 'OTG_CRC_CNTL_OTG_CRC_CONT_EN', + 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE', + 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET', + 'OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET', 'OTG_CRC_CNTL_OTG_CRC_EN', + 'OTG_CRC_CNTL_OTG_CRC_EN_FALSE', 'OTG_CRC_CNTL_OTG_CRC_EN_TRUE', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM', + 'OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT', + 'OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE', + 'OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB', + 'OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B', + 'OTG_DIG_UPDATE_VCOUNT_0', 'OTG_DIG_UPDATE_VCOUNT_1', + 'OTG_DIG_UPDATE_VCOUNT_MODE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE', + 'OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE', + 'OTG_DROP_PIXEL', 'OTG_DROP_PIXEL_FORCE', 'OTG_DROP_PIXEL_NOOP', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME', + 'OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE', + 'OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA', + 'OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE', + 'OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4', + 'OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5', + 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL', + 'OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL', + 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD', + 'OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL', + 'OTG_GLOBAL_UPDATE_LOCK_DISABLE', 'OTG_GLOBAL_UPDATE_LOCK_EN', + 'OTG_GLOBAL_UPDATE_LOCK_ENABLE', 'OTG_GSL_MASTER_MODE', + 'OTG_GSL_MASTER_MODE_0', 'OTG_GSL_MASTER_MODE_1', + 'OTG_GSL_MASTER_MODE_2', 'OTG_GSL_MASTER_MODE_3', + 'OTG_HORZ_REPETITION_COUNT', 'OTG_HORZ_REPETITION_COUNT_0', + 'OTG_HORZ_REPETITION_COUNT_1', 'OTG_HORZ_REPETITION_COUNT_10', + 'OTG_HORZ_REPETITION_COUNT_11', 'OTG_HORZ_REPETITION_COUNT_12', + 'OTG_HORZ_REPETITION_COUNT_13', 'OTG_HORZ_REPETITION_COUNT_14', + 'OTG_HORZ_REPETITION_COUNT_15', 'OTG_HORZ_REPETITION_COUNT_2', + 'OTG_HORZ_REPETITION_COUNT_3', 'OTG_HORZ_REPETITION_COUNT_4', + 'OTG_HORZ_REPETITION_COUNT_5', 'OTG_HORZ_REPETITION_COUNT_6', + 'OTG_HORZ_REPETITION_COUNT_7', 'OTG_HORZ_REPETITION_COUNT_8', + 'OTG_HORZ_REPETITION_COUNT_9', 'OTG_H_SYNC_A_POL', + 'OTG_H_SYNC_A_POL_HIGH', 'OTG_H_SYNC_A_POL_LOW', + 'OTG_H_TIMING_DIV_MODE', 'OTG_H_TIMING_DIV_MODE_AUTO', + 'OTG_H_TIMING_DIV_MODE_DIV_BY2', 'OTG_H_TIMING_DIV_MODE_DIV_BY4', + 'OTG_H_TIMING_DIV_MODE_MANUAL', 'OTG_H_TIMING_DIV_MODE_NOAUTO', + 'OTG_H_TIMING_DIV_MODE_NO_DIV', 'OTG_H_TIMING_DIV_MODE_RESERVED', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2', + 'OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE', + 'OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE', + 'OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE', + 'OTG_MASTER_UPDATE_LOCK_DB_EN', 'OTG_MASTER_UPDATE_LOCK_DISABLE', + 'OTG_MASTER_UPDATE_LOCK_ENABLE', 'OTG_MASTER_UPDATE_LOCK_GSL_EN', + 'OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE', + 'OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE', + 'OTG_MASTER_UPDATE_LOCK_VCOUNT_0', + 'OTG_MASTER_UPDATE_LOCK_VCOUNT_1', + 'OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA', + 'OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE', + 'OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF', + 'OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON', + 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL', + 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE', + 'OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE', + 'OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED', + 'OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING', + 'OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGA_FREQUENCY_SELECT', 'OTG_TRIGA_FREQUENCY_SELECT_0', + 'OTG_TRIGA_FREQUENCY_SELECT_1', 'OTG_TRIGA_FREQUENCY_SELECT_2', + 'OTG_TRIGA_FREQUENCY_SELECT_3', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING', + 'OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3', + 'OTG_TRIGB_FREQUENCY_SELECT', 'OTG_TRIGB_FREQUENCY_SELECT_0', + 'OTG_TRIGB_FREQUENCY_SELECT_1', 'OTG_TRIGB_FREQUENCY_SELECT_2', + 'OTG_TRIGB_FREQUENCY_SELECT_3', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2', + 'OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE', + 'OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE', + 'OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE', + 'OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA', + 'OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE', + 'OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE', + 'OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE', + 'OTG_VUPDATE_BLOCK_DISABLE', 'OTG_VUPDATE_BLOCK_DISABLE_OFF', + 'OTG_VUPDATE_BLOCK_DISABLE_ON', 'OTG_V_SYNC_A_POL', + 'OTG_V_SYNC_A_POL_HIGH', 'OTG_V_SYNC_A_POL_LOW', + 'OTG_V_SYNC_MODE', 'OTG_V_SYNC_MODE_HBLANK', + 'OTG_V_SYNC_MODE_HSYNC', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0', + 'OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE', + 'OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE', + 'OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE', + 'OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE', + 'OUTPUT_LINE', 'OUTPUT_POINT', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ', + 'OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ', + 'OUTPUT_TRIANGLE_CCW', 'OUTPUT_TRIANGLE_CW', 'OUTSTANDING_REQ', + 'OVERRUN', 'OreoMode', 'PACKET2_PAD_MASK', 'PACKET2_PAD_SHIFT', + 'PACKET3_ACQUIRE_MEM', 'PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA', + 'PACKET3_AQL_PACKET', 'PACKET3_ATOMIC_GDS', 'PACKET3_ATOMIC_MEM', 'PACKET3_BLK_CNTX_UPDATE', 'PACKET3_CLEAR_STATE', 'PACKET3_COND_EXEC', 'PACKET3_COND_INDIRECT_BUFFER', 'PACKET3_COND_INDIRECT_BUFFER_CNST', 'PACKET3_COND_PREEMPT', @@ -14171,7 +66975,8 @@ __all__ = \ 'PACKET3_WAIT_ON_DE_COUNTER_DIFF', 'PACKET3_WAIT_REG_MEM', 'PACKET3_WAIT_REG_MEM64', 'PACKET3_WRITE_CONST_RAM', 'PACKET3_WRITE_DATA', 'PACKET_TYPE0', 'PACKET_TYPE1', - 'PACKET_TYPE2', 'PACKET_TYPE3', 'PCIE0_BASE', + 'PACKET_TYPE2', 'PACKET_TYPE3', 'PART_FRAC_EVEN', 'PART_FRAC_ODD', + 'PART_INTEGER', 'PART_POW2', 'PATCHES', 'PCIE0_BASE', 'PCIE0_BASE__INST0_SEG0', 'PCIE0_BASE__INST0_SEG1', 'PCIE0_BASE__INST0_SEG2', 'PCIE0_BASE__INST0_SEG3', 'PCIE0_BASE__INST0_SEG4', 'PCIE0_BASE__INST1_SEG0', @@ -14189,103 +66994,6127 @@ __all__ = \ 'PCIE0_BASE__INST5_SEG3', 'PCIE0_BASE__INST5_SEG4', 'PCIE0_BASE__INST6_SEG0', 'PCIE0_BASE__INST6_SEG1', 'PCIE0_BASE__INST6_SEG2', 'PCIE0_BASE__INST6_SEG3', - 'PCIE0_BASE__INST6_SEG4', 'SDMA0_BASE', 'SDMA0_BASE__INST0_SEG0', - 'SDMA0_BASE__INST0_SEG1', 'SDMA0_BASE__INST0_SEG2', - 'SDMA0_BASE__INST0_SEG3', 'SDMA0_BASE__INST0_SEG4', - 'SDMA0_BASE__INST1_SEG0', 'SDMA0_BASE__INST1_SEG1', - 'SDMA0_BASE__INST1_SEG2', 'SDMA0_BASE__INST1_SEG3', - 'SDMA0_BASE__INST1_SEG4', 'SDMA0_BASE__INST2_SEG0', - 'SDMA0_BASE__INST2_SEG1', 'SDMA0_BASE__INST2_SEG2', - 'SDMA0_BASE__INST2_SEG3', 'SDMA0_BASE__INST2_SEG4', - 'SDMA0_BASE__INST3_SEG0', 'SDMA0_BASE__INST3_SEG1', - 'SDMA0_BASE__INST3_SEG2', 'SDMA0_BASE__INST3_SEG3', - 'SDMA0_BASE__INST3_SEG4', 'SDMA0_BASE__INST4_SEG0', - 'SDMA0_BASE__INST4_SEG1', 'SDMA0_BASE__INST4_SEG2', - 'SDMA0_BASE__INST4_SEG3', 'SDMA0_BASE__INST4_SEG4', - 'SDMA0_BASE__INST5_SEG0', 'SDMA0_BASE__INST5_SEG1', - 'SDMA0_BASE__INST5_SEG2', 'SDMA0_BASE__INST5_SEG3', - 'SDMA0_BASE__INST5_SEG4', 'SDMA0_BASE__INST6_SEG0', - 'SDMA0_BASE__INST6_SEG1', 'SDMA0_BASE__INST6_SEG2', - 'SDMA0_BASE__INST6_SEG3', 'SDMA0_BASE__INST6_SEG4', 'SDMA1_BASE', - 'SDMA1_BASE__INST0_SEG0', 'SDMA1_BASE__INST0_SEG1', - 'SDMA1_BASE__INST0_SEG2', 'SDMA1_BASE__INST0_SEG3', - 'SDMA1_BASE__INST0_SEG4', 'SDMA1_BASE__INST1_SEG0', - 'SDMA1_BASE__INST1_SEG1', 'SDMA1_BASE__INST1_SEG2', - 'SDMA1_BASE__INST1_SEG3', 'SDMA1_BASE__INST1_SEG4', - 'SDMA1_BASE__INST2_SEG0', 'SDMA1_BASE__INST2_SEG1', - 'SDMA1_BASE__INST2_SEG2', 'SDMA1_BASE__INST2_SEG3', - 'SDMA1_BASE__INST2_SEG4', 'SDMA1_BASE__INST3_SEG0', - 'SDMA1_BASE__INST3_SEG1', 'SDMA1_BASE__INST3_SEG2', - 'SDMA1_BASE__INST3_SEG3', 'SDMA1_BASE__INST3_SEG4', - 'SDMA1_BASE__INST4_SEG0', 'SDMA1_BASE__INST4_SEG1', - 'SDMA1_BASE__INST4_SEG2', 'SDMA1_BASE__INST4_SEG3', - 'SDMA1_BASE__INST4_SEG4', 'SDMA1_BASE__INST5_SEG0', - 'SDMA1_BASE__INST5_SEG1', 'SDMA1_BASE__INST5_SEG2', - 'SDMA1_BASE__INST5_SEG3', 'SDMA1_BASE__INST5_SEG4', - 'SDMA1_BASE__INST6_SEG0', 'SDMA1_BASE__INST6_SEG1', - 'SDMA1_BASE__INST6_SEG2', 'SDMA1_BASE__INST6_SEG3', - 'SDMA1_BASE__INST6_SEG4', 'SDMA_ATOMIC_ADD64', 'SDMA_OP_ATOMIC', - 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', 'SDMA_OP_FENCE', - 'SDMA_OP_GCR', 'SDMA_OP_POLL_REGMEM', 'SDMA_OP_TIMESTAMP', - 'SDMA_OP_TRAP', 'SDMA_PKT_ATOMIC', 'SDMA_PKT_CONSTANT_FILL', - 'SDMA_PKT_COPY_LINEAR', 'SDMA_PKT_COPY_LINEAR_RECT', - 'SDMA_PKT_FENCE', 'SDMA_PKT_GCR', 'SDMA_PKT_HDP_FLUSH', - 'SDMA_PKT_POLL_REGMEM', 'SDMA_PKT_TIMESTAMP', 'SDMA_PKT_TRAP', - 'SDMA_SUBOP_COPY_LINEAR', 'SDMA_SUBOP_COPY_LINEAR_RECT', - 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', 'SDMA_SUBOP_USER_GCR', - 'SMUIO_BASE', 'SMUIO_BASE__INST0_SEG0', 'SMUIO_BASE__INST0_SEG1', - 'SMUIO_BASE__INST0_SEG2', 'SMUIO_BASE__INST0_SEG3', - 'SMUIO_BASE__INST0_SEG4', 'SMUIO_BASE__INST1_SEG0', - 'SMUIO_BASE__INST1_SEG1', 'SMUIO_BASE__INST1_SEG2', - 'SMUIO_BASE__INST1_SEG3', 'SMUIO_BASE__INST1_SEG4', - 'SMUIO_BASE__INST2_SEG0', 'SMUIO_BASE__INST2_SEG1', - 'SMUIO_BASE__INST2_SEG2', 'SMUIO_BASE__INST2_SEG3', - 'SMUIO_BASE__INST2_SEG4', 'SMUIO_BASE__INST3_SEG0', - 'SMUIO_BASE__INST3_SEG1', 'SMUIO_BASE__INST3_SEG2', - 'SMUIO_BASE__INST3_SEG3', 'SMUIO_BASE__INST3_SEG4', - 'SMUIO_BASE__INST4_SEG0', 'SMUIO_BASE__INST4_SEG1', - 'SMUIO_BASE__INST4_SEG2', 'SMUIO_BASE__INST4_SEG3', - 'SMUIO_BASE__INST4_SEG4', 'SMUIO_BASE__INST5_SEG0', - 'SMUIO_BASE__INST5_SEG1', 'SMUIO_BASE__INST5_SEG2', - 'SMUIO_BASE__INST5_SEG3', 'SMUIO_BASE__INST5_SEG4', - 'SMUIO_BASE__INST6_SEG0', 'SMUIO_BASE__INST6_SEG1', - 'SMUIO_BASE__INST6_SEG2', 'SMUIO_BASE__INST6_SEG3', - 'SMUIO_BASE__INST6_SEG4', 'THM_BASE', 'THM_BASE__INST0_SEG0', - 'THM_BASE__INST0_SEG1', 'THM_BASE__INST0_SEG2', - 'THM_BASE__INST0_SEG3', 'THM_BASE__INST0_SEG4', - 'THM_BASE__INST1_SEG0', 'THM_BASE__INST1_SEG1', - 'THM_BASE__INST1_SEG2', 'THM_BASE__INST1_SEG3', - 'THM_BASE__INST1_SEG4', 'THM_BASE__INST2_SEG0', - 'THM_BASE__INST2_SEG1', 'THM_BASE__INST2_SEG2', - 'THM_BASE__INST2_SEG3', 'THM_BASE__INST2_SEG4', - 'THM_BASE__INST3_SEG0', 'THM_BASE__INST3_SEG1', - 'THM_BASE__INST3_SEG2', 'THM_BASE__INST3_SEG3', - 'THM_BASE__INST3_SEG4', 'THM_BASE__INST4_SEG0', - 'THM_BASE__INST4_SEG1', 'THM_BASE__INST4_SEG2', - 'THM_BASE__INST4_SEG3', 'THM_BASE__INST4_SEG4', - 'THM_BASE__INST5_SEG0', 'THM_BASE__INST5_SEG1', - 'THM_BASE__INST5_SEG2', 'THM_BASE__INST5_SEG3', - 'THM_BASE__INST5_SEG4', 'THM_BASE__INST6_SEG0', - 'THM_BASE__INST6_SEG1', 'THM_BASE__INST6_SEG2', - 'THM_BASE__INST6_SEG3', 'THM_BASE__INST6_SEG4', 'UMC_BASE', - 'UMC_BASE__INST0_SEG0', 'UMC_BASE__INST0_SEG1', - 'UMC_BASE__INST0_SEG2', 'UMC_BASE__INST0_SEG3', - 'UMC_BASE__INST0_SEG4', 'UMC_BASE__INST1_SEG0', - 'UMC_BASE__INST1_SEG1', 'UMC_BASE__INST1_SEG2', - 'UMC_BASE__INST1_SEG3', 'UMC_BASE__INST1_SEG4', - 'UMC_BASE__INST2_SEG0', 'UMC_BASE__INST2_SEG1', - 'UMC_BASE__INST2_SEG2', 'UMC_BASE__INST2_SEG3', - 'UMC_BASE__INST2_SEG4', 'UMC_BASE__INST3_SEG0', - 'UMC_BASE__INST3_SEG1', 'UMC_BASE__INST3_SEG2', - 'UMC_BASE__INST3_SEG3', 'UMC_BASE__INST3_SEG4', - 'UMC_BASE__INST4_SEG0', 'UMC_BASE__INST4_SEG1', - 'UMC_BASE__INST4_SEG2', 'UMC_BASE__INST4_SEG3', - 'UMC_BASE__INST4_SEG4', 'UMC_BASE__INST5_SEG0', - 'UMC_BASE__INST5_SEG1', 'UMC_BASE__INST5_SEG2', - 'UMC_BASE__INST5_SEG3', 'UMC_BASE__INST5_SEG4', - 'UMC_BASE__INST6_SEG0', 'UMC_BASE__INST6_SEG1', - 'UMC_BASE__INST6_SEG2', 'UMC_BASE__INST6_SEG3', - 'UMC_BASE__INST6_SEG4', 'USB0_BASE', 'USB0_BASE__INST0_SEG0', + 'PCIE0_BASE__INST6_SEG4', 'PERFCOUNTER_ACTIVE', + 'PERFCOUNTER_CNT0_STATE', 'PERFCOUNTER_CNT0_STATE_FREEZE', + 'PERFCOUNTER_CNT0_STATE_HW', 'PERFCOUNTER_CNT0_STATE_RESET', + 'PERFCOUNTER_CNT0_STATE_START', 'PERFCOUNTER_CNT1_STATE', + 'PERFCOUNTER_CNT1_STATE_FREEZE', 'PERFCOUNTER_CNT1_STATE_HW', + 'PERFCOUNTER_CNT1_STATE_RESET', 'PERFCOUNTER_CNT1_STATE_START', + 'PERFCOUNTER_CNT2_STATE', 'PERFCOUNTER_CNT2_STATE_FREEZE', + 'PERFCOUNTER_CNT2_STATE_HW', 'PERFCOUNTER_CNT2_STATE_RESET', + 'PERFCOUNTER_CNT2_STATE_START', 'PERFCOUNTER_CNT3_STATE', + 'PERFCOUNTER_CNT3_STATE_FREEZE', 'PERFCOUNTER_CNT3_STATE_HW', + 'PERFCOUNTER_CNT3_STATE_RESET', 'PERFCOUNTER_CNT3_STATE_START', + 'PERFCOUNTER_CNT4_STATE', 'PERFCOUNTER_CNT4_STATE_FREEZE', + 'PERFCOUNTER_CNT4_STATE_HW', 'PERFCOUNTER_CNT4_STATE_RESET', + 'PERFCOUNTER_CNT4_STATE_START', 'PERFCOUNTER_CNT5_STATE', + 'PERFCOUNTER_CNT5_STATE_FREEZE', 'PERFCOUNTER_CNT5_STATE_HW', + 'PERFCOUNTER_CNT5_STATE_RESET', 'PERFCOUNTER_CNT5_STATE_START', + 'PERFCOUNTER_CNT6_STATE', 'PERFCOUNTER_CNT6_STATE_FREEZE', + 'PERFCOUNTER_CNT6_STATE_HW', 'PERFCOUNTER_CNT6_STATE_RESET', + 'PERFCOUNTER_CNT6_STATE_START', 'PERFCOUNTER_CNT7_STATE', + 'PERFCOUNTER_CNT7_STATE_FREEZE', 'PERFCOUNTER_CNT7_STATE_HW', + 'PERFCOUNTER_CNT7_STATE_RESET', 'PERFCOUNTER_CNT7_STATE_START', + 'PERFCOUNTER_CNTL_SEL', 'PERFCOUNTER_CNTL_SEL_0', + 'PERFCOUNTER_CNTL_SEL_1', 'PERFCOUNTER_CNTL_SEL_2', + 'PERFCOUNTER_CNTL_SEL_3', 'PERFCOUNTER_CNTL_SEL_4', + 'PERFCOUNTER_CNTL_SEL_5', 'PERFCOUNTER_CNTL_SEL_6', + 'PERFCOUNTER_CNTL_SEL_7', 'PERFCOUNTER_CNTOFF_START_DIS', + 'PERFCOUNTER_CNTOFF_START_DISABLE', + 'PERFCOUNTER_CNTOFF_START_ENABLE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_ACC', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MAX', + 'PERFCOUNTER_COUNTED_VALUE_TYPE_MIN', 'PERFCOUNTER_CVALUE_SEL', + 'PERFCOUNTER_CVALUE_SEL_11_0', 'PERFCOUNTER_CVALUE_SEL_15_0', + 'PERFCOUNTER_CVALUE_SEL_23_12', 'PERFCOUNTER_CVALUE_SEL_31_16', + 'PERFCOUNTER_CVALUE_SEL_35_24', 'PERFCOUNTER_CVALUE_SEL_47_0', + 'PERFCOUNTER_CVALUE_SEL_47_32', 'PERFCOUNTER_CVALUE_SEL_47_36', + 'PERFCOUNTER_HW_CNTL_SEL', 'PERFCOUNTER_HW_CNTL_SEL_CNTOFF', + 'PERFCOUNTER_HW_CNTL_SEL_RUNEN', 'PERFCOUNTER_HW_STOP1_0', + 'PERFCOUNTER_HW_STOP1_1', 'PERFCOUNTER_HW_STOP1_SEL', + 'PERFCOUNTER_HW_STOP2_0', 'PERFCOUNTER_HW_STOP2_1', + 'PERFCOUNTER_HW_STOP2_SEL', 'PERFCOUNTER_INC_MODE', + 'PERFCOUNTER_INC_MODE_BOTH_EDGE', 'PERFCOUNTER_INC_MODE_LSB', + 'PERFCOUNTER_INC_MODE_MULTI_BIT', 'PERFCOUNTER_INC_MODE_NEG_EDGE', + 'PERFCOUNTER_INC_MODE_POS_EDGE', 'PERFCOUNTER_INT_DISABLE', + 'PERFCOUNTER_INT_EN', 'PERFCOUNTER_INT_ENABLE', + 'PERFCOUNTER_INT_TYPE', 'PERFCOUNTER_INT_TYPE_LEVEL', + 'PERFCOUNTER_INT_TYPE_PULSE', 'PERFCOUNTER_IS_ACTIVE', + 'PERFCOUNTER_IS_IDLE', 'PERFCOUNTER_OFF_MASK', + 'PERFCOUNTER_OFF_MASK_DISABLE', 'PERFCOUNTER_OFF_MASK_ENABLE', + 'PERFCOUNTER_RESTART_DISABLE', 'PERFCOUNTER_RESTART_EN', + 'PERFCOUNTER_RESTART_ENABLE', 'PERFCOUNTER_RUNEN_MODE', + 'PERFCOUNTER_RUNEN_MODE_EDGE', 'PERFCOUNTER_RUNEN_MODE_LEVEL', + 'PERFCOUNTER_SAMPLE', 'PERFCOUNTER_START', + 'PERFCOUNTER_STATE_SEL0', 'PERFCOUNTER_STATE_SEL0_GLOBAL', + 'PERFCOUNTER_STATE_SEL0_LOCAL', 'PERFCOUNTER_STATE_SEL1', + 'PERFCOUNTER_STATE_SEL1_GLOBAL', 'PERFCOUNTER_STATE_SEL1_LOCAL', + 'PERFCOUNTER_STATE_SEL2', 'PERFCOUNTER_STATE_SEL2_GLOBAL', + 'PERFCOUNTER_STATE_SEL2_LOCAL', 'PERFCOUNTER_STATE_SEL3', + 'PERFCOUNTER_STATE_SEL3_GLOBAL', 'PERFCOUNTER_STATE_SEL3_LOCAL', + 'PERFCOUNTER_STATE_SEL4', 'PERFCOUNTER_STATE_SEL4_GLOBAL', + 'PERFCOUNTER_STATE_SEL4_LOCAL', 'PERFCOUNTER_STATE_SEL5', + 'PERFCOUNTER_STATE_SEL5_GLOBAL', 'PERFCOUNTER_STATE_SEL5_LOCAL', + 'PERFCOUNTER_STATE_SEL6', 'PERFCOUNTER_STATE_SEL6_GLOBAL', + 'PERFCOUNTER_STATE_SEL6_LOCAL', 'PERFCOUNTER_STATE_SEL7', + 'PERFCOUNTER_STATE_SEL7_GLOBAL', 'PERFCOUNTER_STATE_SEL7_LOCAL', + 'PERFCOUNTER_STOP', 'PERFMON_CNTOFF_AND', 'PERFMON_CNTOFF_AND_OR', + 'PERFMON_CNTOFF_INT_DISABLE', 'PERFMON_CNTOFF_INT_EN', + 'PERFMON_CNTOFF_INT_ENABLE', 'PERFMON_CNTOFF_INT_TYPE', + 'PERFMON_CNTOFF_INT_TYPE_LEVEL', 'PERFMON_CNTOFF_INT_TYPE_PULSE', + 'PERFMON_CNTOFF_OR', 'PERFMON_COUNTER_MODE', + 'PERFMON_COUNTER_MODE_ACCUM', + 'PERFMON_COUNTER_MODE_ACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_CYCLES_EQ_HI', + 'PERFMON_COUNTER_MODE_CYCLES_GE_HI', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT', + 'PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT', + 'PERFMON_COUNTER_MODE_DIRTY', + 'PERFMON_COUNTER_MODE_INACTIVE_CYCLES', + 'PERFMON_COUNTER_MODE_MAX', 'PERFMON_COUNTER_MODE_RESERVED', + 'PERFMON_COUNTER_MODE_SAMPLE', 'PERFMON_SPM_MODE', + 'PERFMON_SPM_MODE_16BIT_CLAMP', 'PERFMON_SPM_MODE_16BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_32BIT_CLAMP', 'PERFMON_SPM_MODE_32BIT_NO_CLAMP', + 'PERFMON_SPM_MODE_OFF', 'PERFMON_SPM_MODE_RESERVED_5', + 'PERFMON_SPM_MODE_RESERVED_6', 'PERFMON_SPM_MODE_RESERVED_7', + 'PERFMON_SPM_MODE_TEST_MODE_0', 'PERFMON_SPM_MODE_TEST_MODE_1', + 'PERFMON_SPM_MODE_TEST_MODE_2', 'PERFMON_STATE', + 'PERFMON_STATE_FREEZE', 'PERFMON_STATE_HW', 'PERFMON_STATE_RESET', + 'PERFMON_STATE_START', 'PERF_CLIPSM_CULL_PRIMS_CNT', + 'PERF_ENGG_BUSY', 'PERF_ENGG_CSB_DELAY_BIN00', + 'PERF_ENGG_CSB_DELAY_BIN01', 'PERF_ENGG_CSB_DELAY_BIN02', + 'PERF_ENGG_CSB_DELAY_BIN03', 'PERF_ENGG_CSB_DELAY_BIN04', + 'PERF_ENGG_CSB_DELAY_BIN05', 'PERF_ENGG_CSB_DELAY_BIN06', + 'PERF_ENGG_CSB_DELAY_BIN07', 'PERF_ENGG_CSB_DELAY_BIN08', + 'PERF_ENGG_CSB_DELAY_BIN09', 'PERF_ENGG_CSB_DELAY_BIN10', + 'PERF_ENGG_CSB_DELAY_BIN11', 'PERF_ENGG_CSB_DELAY_BIN12', + 'PERF_ENGG_CSB_DELAY_BIN13', 'PERF_ENGG_CSB_DELAY_BIN14', + 'PERF_ENGG_CSB_DELAY_BIN15', 'PERF_ENGG_CSB_GE_INPUT_FIFO_FULL', + 'PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT', + 'PERF_ENGG_CSB_GE_MEMORY_EMPTY', 'PERF_ENGG_CSB_GE_MEMORY_FULL', + 'PERF_ENGG_CSB_GE_SENDING_SUBGROUP', + 'PERF_ENGG_CSB_MACHINE_IS_STARVED', + 'PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY', + 'PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI', + 'PERF_ENGG_CSB_NULL_SUBGROUP', + 'PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL', + 'PERF_ENGG_CSB_PRIM_COUNT_EQ0', 'PERF_ENGG_CSB_SPI_DELAY_BIN00', + 'PERF_ENGG_CSB_SPI_DELAY_BIN01', 'PERF_ENGG_CSB_SPI_DELAY_BIN02', + 'PERF_ENGG_CSB_SPI_DELAY_BIN03', 'PERF_ENGG_CSB_SPI_DELAY_BIN04', + 'PERF_ENGG_CSB_SPI_DELAY_BIN05', 'PERF_ENGG_CSB_SPI_DELAY_BIN06', + 'PERF_ENGG_CSB_SPI_DELAY_BIN07', 'PERF_ENGG_CSB_SPI_DELAY_BIN08', + 'PERF_ENGG_CSB_SPI_DELAY_BIN09', 'PERF_ENGG_CSB_SPI_DELAY_BIN10', + 'PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL', + 'PERF_ENGG_CSB_SPI_MEMORY_EMPTY', 'PERF_ENGG_CSB_SPI_MEMORY_FULL', + 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE', + 'PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE', + 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO', + 'PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO', + 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB', + 'PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM', + 'PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM', + 'PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 'PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL', + 'PERF_ENGG_INDEX_REQ_NULL_REQUEST', + 'PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS', + 'PERF_ENGG_INDEX_REQ_STARVED', + 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY', + 'PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL', + 'PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO', + 'PERF_ENGG_INDEX_RET_SXRX_READING_EVENT', + 'PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL', + 'PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0', + 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO', + 'PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO', + 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB', + 'PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS', + 'PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL', + 'PERF_ENGG_POS_REQ_STARVED', 'PERF_OUTPUT_PRIM_1_SC', + 'PERF_OUTPUT_PRIM_2_SC', 'PERF_OUTPUT_PRIM_3_SC', + 'PERF_OUTPUT_PRIM_4_SC', 'PERF_PAPC_CCGSM_BUSY', + 'PERF_PAPC_CCGSM_IDLE', 'PERF_PAPC_CCGSM_STALLED', + 'PERF_PAPC_CLIPGA_BUSY', 'PERF_PAPC_CLIPGA_IDLE', + 'PERF_PAPC_CLIPGA_STALLED', 'PERF_PAPC_CLIPGA_STARVED_VTE_CLIP', + 'PERF_PAPC_CLIPGA_VTE_KILL_PRIM', 'PERF_PAPC_CLIPSM_BUSY', + 'PERF_PAPC_CLIPSM_IDLE', 'PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP', + 'PERF_PAPC_CLIPSM_WAIT_CLIPGA', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM', + 'PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH', + 'PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ', 'PERF_PAPC_CLIP_BUSY', + 'PERF_PAPC_CLIP_IDLE', 'PERF_PAPC_CLPRIM_BUSY', + 'PERF_PAPC_CLPRIM_IDLE', 'PERF_PAPC_CLPRIM_STALLED', + 'PERF_PAPC_CLPRIM_STARVED_CCGSM', + 'PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_1', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_2', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_3', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_4', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8', + 'PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12', + 'PERF_PAPC_CLPR_CLIP_PLANE_FAR', 'PERF_PAPC_CLPR_CLIP_PLANE_LEFT', + 'PERF_PAPC_CLPR_CLIP_PLANE_NEAR', + 'PERF_PAPC_CLPR_CLIP_PLANE_RIGHT', + 'PERF_PAPC_CLPR_CLIP_PLANE_TOP', 'PERF_PAPC_CLPR_CULL_PRIM', + 'PERF_PAPC_CLPR_CULL_TO_NULL_PRIM', + 'PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE', + 'PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_UCP_CLIP_PRIM', 'PERF_PAPC_CLPR_UCP_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM', + 'PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CLIP_PRIM', + 'PERF_PAPC_CLPR_VVUCP_CULL_PRIM', 'PERF_PAPC_CLPR_VV_CLIP_PRIM', + 'PERF_PAPC_CLPR_VV_CULL_PRIM', 'PERF_PAPC_CLSM_CLIPPING_PRIM', + 'PERF_PAPC_CLSM_CULL_TO_NULL_PRIM', 'PERF_PAPC_CLSM_NULL_PRIM', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_1', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_2', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_3', 'PERF_PAPC_CLSM_OUT_PRIM_CNT_4', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8', + 'PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13', + 'PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM', + 'PERF_PAPC_CL_DYN_SCLK_VLD', 'PERF_PAPC_PASX_DISABLE_PIPE', + 'PERF_PAPC_PASX_FIRST_DEAD', 'PERF_PAPC_PASX_FIRST_VECTOR', + 'PERF_PAPC_PASX_REC_BUSY', 'PERF_PAPC_PASX_REC_IDLE', + 'PERF_PAPC_PASX_REC_STALLED', + 'PERF_PAPC_PASX_REC_STALLED_CCGSM_IN', + 'PERF_PAPC_PASX_REC_STALLED_POS_MEM', + 'PERF_PAPC_PASX_REC_STARVED_SX', 'PERF_PAPC_PASX_REQ', + 'PERF_PAPC_PASX_REQ_BUSY', 'PERF_PAPC_PASX_REQ_IDLE', + 'PERF_PAPC_PASX_REQ_STALLED', 'PERF_PAPC_PASX_SE0_FIRST_VECTOR', + 'PERF_PAPC_PASX_SE0_REQ', 'PERF_PAPC_PASX_SE0_SECOND_VECTOR', + 'PERF_PAPC_PASX_SE1_FIRST_VECTOR', 'PERF_PAPC_PASX_SE1_REQ', + 'PERF_PAPC_PASX_SE1_SECOND_VECTOR', 'PERF_PAPC_PASX_SECOND_DEAD', + 'PERF_PAPC_PASX_SECOND_VECTOR', 'PERF_PAPC_PASX_VTX_KILL_DISCARD', + 'PERF_PAPC_PASX_VTX_NAN_DISCARD', + 'PERF_PAPC_PA_INPUT_END_OF_PACKET', + 'PERF_PAPC_PA_INPUT_EVENT_FLAG', + 'PERF_PAPC_PA_INPUT_EXTENDED_EVENT', + 'PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_PA_INPUT_NULL_PRIM', 'PERF_PAPC_PA_INPUT_PRIM', + 'PERF_PAPC_PA_REG_SCLK_VLD', 'PERF_PAPC_SU_BACK_FACE_CULL_PRIM', + 'PERF_PAPC_SU_BUSY', 'PERF_PAPC_SU_CULLED_PRIM', + 'PERF_PAPC_SU_DYN_SCLK_VLD', 'PERF_PAPC_SU_FRONT_FACE_CULL_PRIM', + 'PERF_PAPC_SU_IDLE', 'PERF_PAPC_SU_INPUT_CLIP_PRIM', + 'PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_INPUT_NULL_PRIM', 'PERF_PAPC_SU_INPUT_PRIM', + 'PERF_PAPC_SU_INPUT_PRIM_DUAL', + 'PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM', + 'PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL', + 'PERF_PAPC_SU_OUTPUT_END_OF_PACKET', 'PERF_PAPC_SU_OUTPUT_EOPG', + 'PERF_PAPC_SU_OUTPUT_EVENT_FLAG', + 'PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_BACK', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FACE', + 'PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT', 'PERF_PAPC_SU_OUTPUT_PRIM', + 'PERF_PAPC_SU_OUTPUT_PRIM_DUAL', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE', + 'PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT', + 'PERF_PAPC_SU_POLYMODE_BACK_CULL', + 'PERF_PAPC_SU_POLYMODE_FACE_CULL', + 'PERF_PAPC_SU_POLYMODE_FRONT_CULL', + 'PERF_PAPC_SU_POLYMODE_INVALID_FILL', + 'PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE01_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE01_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE01_STALLED_SC', + 'PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE0_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE0_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE0_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE0_STALLED_SC', + 'PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE1_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT', + 'PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE1_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE1_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE1_STALLED_SC', + 'PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE2_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE2_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE2_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE2_STALLED_SC', + 'PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET', + 'PERF_PAPC_SU_SE3_OUTPUT_EOPG', + 'PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM', + 'PERF_PAPC_SU_SE3_OUTPUT_PRIM', + 'PERF_PAPC_SU_SE3_PRIM_FILTER_CULL', + 'PERF_PAPC_SU_SE3_STALLED_SC', 'PERF_PAPC_SU_STALLED_SC', + 'PERF_PAPC_SU_STARVED_CLIP', 'PERF_PAPC_SU_ZERO_AREA_CULL_PRIM', + 'PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL', + 'PERF_PA_FETCH_TO_SXIF_FIFO_FULL', 'PERF_PA_PIPE0_SWITCHED_GEN', + 'PERF_PA_PIPE1_SWITCHED_GEN', + 'PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL', 'PERF_PA_VERTEX_FIFO_FULL', + 'PERF_PH_SEND_1_SC', 'PERF_PH_SEND_2_SC', 'PERF_PH_SEND_3_SC', + 'PERF_PH_SEND_4_SC', 'PERF_SC0_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC1_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC2_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SC3_QUALIFIED_SEND_BUSY_EVENT', + 'PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT', + 'PERF_SMALL_PRIM_CULL_PRIM_1X1', 'PERF_SMALL_PRIM_CULL_PRIM_1X2', + 'PERF_SMALL_PRIM_CULL_PRIM_1X3', 'PERF_SMALL_PRIM_CULL_PRIM_1XN', + 'PERF_SMALL_PRIM_CULL_PRIM_2X1', 'PERF_SMALL_PRIM_CULL_PRIM_2X2', + 'PERF_SMALL_PRIM_CULL_PRIM_2X3', 'PERF_SMALL_PRIM_CULL_PRIM_2XN', + 'PERF_SMALL_PRIM_CULL_PRIM_3X1', 'PERF_SMALL_PRIM_CULL_PRIM_3X2', + 'PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT', + 'PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT', + 'PERF_SMALL_PRIM_CULL_PRIM_NX1', 'PERF_SMALL_PRIM_CULL_PRIM_NX2', + 'PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT', + 'PERF_SU_SMALL_PRIM_FILTER_CULL_CNT', 'PERSISTENT_SPACE_END', + 'PERSISTENT_SPACE_START', 'PHYSYMCLK_FORCE_EN', + 'PHYSYMCLK_FORCE_EN_DISABLE', 'PHYSYMCLK_FORCE_EN_ENABLE', + 'PHYSYMCLK_FORCE_SRC_PHYD18CLK', 'PHYSYMCLK_FORCE_SRC_PHYD32CLK', + 'PHYSYMCLK_FORCE_SRC_SEL', 'PHYSYMCLK_FORCE_SRC_SYMCLK', + 'PHY_CUSTOM_RATE', 'PHY_DP_RATE_10P', 'PHY_DP_RATE_13P5', + 'PHY_DP_RATE_1P62', 'PHY_DP_RATE_20P', 'PHY_DP_RATE_2P16', + 'PHY_DP_RATE_2P43', 'PHY_DP_RATE_2P7', 'PHY_DP_RATE_3P24', + 'PHY_DP_RATE_4P32', 'PHY_DP_RATE_5P4', 'PHY_DP_RATE_8P1', + 'PHY_IF_WIDTH_10BIT', 'PHY_IF_WIDTH_20BIT', 'PHY_IF_WIDTH_40BIT', + 'PHY_IF_WIDTH_80BIT', 'PH_PERFCNT_SEL', + 'PH_PERF_SC0_FIFO_STATUS_0', 'PH_PERF_SC0_FIFO_STATUS_1', + 'PH_PERF_SC0_FIFO_STATUS_2', 'PH_PERF_SC0_FIFO_STATUS_3', + 'PH_PERF_SC1_FIFO_STATUS_0', 'PH_PERF_SC1_FIFO_STATUS_1', + 'PH_PERF_SC1_FIFO_STATUS_2', 'PH_PERF_SC1_FIFO_STATUS_3', + 'PH_PERF_SC2_FIFO_STATUS_0', 'PH_PERF_SC2_FIFO_STATUS_1', + 'PH_PERF_SC2_FIFO_STATUS_2', 'PH_PERF_SC2_FIFO_STATUS_3', + 'PH_PERF_SC3_FIFO_STATUS_0', 'PH_PERF_SC3_FIFO_STATUS_1', + 'PH_PERF_SC3_FIFO_STATUS_2', 'PH_PERF_SC3_FIFO_STATUS_3', + 'PH_PERF_SC4_FIFO_STATUS_0', 'PH_PERF_SC4_FIFO_STATUS_1', + 'PH_PERF_SC4_FIFO_STATUS_2', 'PH_PERF_SC4_FIFO_STATUS_3', + 'PH_PERF_SC5_FIFO_STATUS_0', 'PH_PERF_SC5_FIFO_STATUS_1', + 'PH_PERF_SC5_FIFO_STATUS_2', 'PH_PERF_SC5_FIFO_STATUS_3', + 'PH_PERF_SC6_FIFO_STATUS_0', 'PH_PERF_SC6_FIFO_STATUS_1', + 'PH_PERF_SC6_FIFO_STATUS_2', 'PH_PERF_SC6_FIFO_STATUS_3', + 'PH_PERF_SC7_FIFO_STATUS_0', 'PH_PERF_SC7_FIFO_STATUS_1', + 'PH_PERF_SC7_FIFO_STATUS_2', 'PH_PERF_SC7_FIFO_STATUS_3', + 'PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC0_ARB_BUSY', + 'PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC0_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC0_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA0_EOPG_WE', 'PH_PERF_SEL_SC0_PA0_EOP_WE', + 'PH_PERF_SEL_SC0_PA0_EVENT_WE', 'PH_PERF_SEL_SC0_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA0_FIFO_FULL', 'PH_PERF_SEL_SC0_PA0_FPOV_WE', + 'PH_PERF_SEL_SC0_PA0_LPOV_WE', 'PH_PERF_SEL_SC0_PA0_NULL_WE', + 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA1_EOPG_WE', 'PH_PERF_SEL_SC0_PA1_EOP_WE', + 'PH_PERF_SEL_SC0_PA1_EVENT_WE', 'PH_PERF_SEL_SC0_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA1_FIFO_FULL', 'PH_PERF_SEL_SC0_PA1_FPOV_WE', + 'PH_PERF_SEL_SC0_PA1_LPOV_WE', 'PH_PERF_SEL_SC0_PA1_NULL_WE', + 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA2_EOPG_WE', 'PH_PERF_SEL_SC0_PA2_EOP_WE', + 'PH_PERF_SEL_SC0_PA2_EVENT_WE', 'PH_PERF_SEL_SC0_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA2_FIFO_FULL', 'PH_PERF_SEL_SC0_PA2_FPOV_WE', + 'PH_PERF_SEL_SC0_PA2_LPOV_WE', 'PH_PERF_SEL_SC0_PA2_NULL_WE', + 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA3_EOPG_WE', 'PH_PERF_SEL_SC0_PA3_EOP_WE', + 'PH_PERF_SEL_SC0_PA3_EVENT_WE', 'PH_PERF_SEL_SC0_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA3_FIFO_FULL', 'PH_PERF_SEL_SC0_PA3_FPOV_WE', + 'PH_PERF_SEL_SC0_PA3_LPOV_WE', 'PH_PERF_SEL_SC0_PA3_NULL_WE', + 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA4_EOPG_WE', 'PH_PERF_SEL_SC0_PA4_EOP_WE', + 'PH_PERF_SEL_SC0_PA4_EVENT_WE', 'PH_PERF_SEL_SC0_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA4_FIFO_FULL', 'PH_PERF_SEL_SC0_PA4_FPOV_WE', + 'PH_PERF_SEL_SC0_PA4_LPOV_WE', 'PH_PERF_SEL_SC0_PA4_NULL_WE', + 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA5_EOPG_WE', 'PH_PERF_SEL_SC0_PA5_EOP_WE', + 'PH_PERF_SEL_SC0_PA5_EVENT_WE', 'PH_PERF_SEL_SC0_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA5_FIFO_FULL', 'PH_PERF_SEL_SC0_PA5_FPOV_WE', + 'PH_PERF_SEL_SC0_PA5_LPOV_WE', 'PH_PERF_SEL_SC0_PA5_NULL_WE', + 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA6_EOPG_WE', 'PH_PERF_SEL_SC0_PA6_EOP_WE', + 'PH_PERF_SEL_SC0_PA6_EVENT_WE', 'PH_PERF_SEL_SC0_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA6_FIFO_FULL', 'PH_PERF_SEL_SC0_PA6_FPOV_WE', + 'PH_PERF_SEL_SC0_PA6_LPOV_WE', 'PH_PERF_SEL_SC0_PA6_NULL_WE', + 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC0_PA7_EOPG_WE', 'PH_PERF_SEL_SC0_PA7_EOP_WE', + 'PH_PERF_SEL_SC0_PA7_EVENT_WE', 'PH_PERF_SEL_SC0_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC0_PA7_FIFO_FULL', 'PH_PERF_SEL_SC0_PA7_FPOV_WE', + 'PH_PERF_SEL_SC0_PA7_LPOV_WE', 'PH_PERF_SEL_SC0_PA7_NULL_WE', + 'PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC0_SEND', 'PH_PERF_SEL_SC0_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC1_ARB_BUSY', + 'PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC1_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC1_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA0_EOPG_WE', 'PH_PERF_SEL_SC1_PA0_EOP_WE', + 'PH_PERF_SEL_SC1_PA0_EVENT_WE', 'PH_PERF_SEL_SC1_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA0_FIFO_FULL', 'PH_PERF_SEL_SC1_PA0_FPOV_WE', + 'PH_PERF_SEL_SC1_PA0_LPOV_WE', 'PH_PERF_SEL_SC1_PA0_NULL_WE', + 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA1_EOPG_WE', 'PH_PERF_SEL_SC1_PA1_EOP_WE', + 'PH_PERF_SEL_SC1_PA1_EVENT_WE', 'PH_PERF_SEL_SC1_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA1_FIFO_FULL', 'PH_PERF_SEL_SC1_PA1_FPOV_WE', + 'PH_PERF_SEL_SC1_PA1_LPOV_WE', 'PH_PERF_SEL_SC1_PA1_NULL_WE', + 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA2_EOPG_WE', 'PH_PERF_SEL_SC1_PA2_EOP_WE', + 'PH_PERF_SEL_SC1_PA2_EVENT_WE', 'PH_PERF_SEL_SC1_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA2_FIFO_FULL', 'PH_PERF_SEL_SC1_PA2_FPOV_WE', + 'PH_PERF_SEL_SC1_PA2_LPOV_WE', 'PH_PERF_SEL_SC1_PA2_NULL_WE', + 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA3_EOPG_WE', 'PH_PERF_SEL_SC1_PA3_EOP_WE', + 'PH_PERF_SEL_SC1_PA3_EVENT_WE', 'PH_PERF_SEL_SC1_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA3_FIFO_FULL', 'PH_PERF_SEL_SC1_PA3_FPOV_WE', + 'PH_PERF_SEL_SC1_PA3_LPOV_WE', 'PH_PERF_SEL_SC1_PA3_NULL_WE', + 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA4_EOPG_WE', 'PH_PERF_SEL_SC1_PA4_EOP_WE', + 'PH_PERF_SEL_SC1_PA4_EVENT_WE', 'PH_PERF_SEL_SC1_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA4_FIFO_FULL', 'PH_PERF_SEL_SC1_PA4_FPOV_WE', + 'PH_PERF_SEL_SC1_PA4_LPOV_WE', 'PH_PERF_SEL_SC1_PA4_NULL_WE', + 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA5_EOPG_WE', 'PH_PERF_SEL_SC1_PA5_EOP_WE', + 'PH_PERF_SEL_SC1_PA5_EVENT_WE', 'PH_PERF_SEL_SC1_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA5_FIFO_FULL', 'PH_PERF_SEL_SC1_PA5_FPOV_WE', + 'PH_PERF_SEL_SC1_PA5_LPOV_WE', 'PH_PERF_SEL_SC1_PA5_NULL_WE', + 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA6_EOPG_WE', 'PH_PERF_SEL_SC1_PA6_EOP_WE', + 'PH_PERF_SEL_SC1_PA6_EVENT_WE', 'PH_PERF_SEL_SC1_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA6_FIFO_FULL', 'PH_PERF_SEL_SC1_PA6_FPOV_WE', + 'PH_PERF_SEL_SC1_PA6_LPOV_WE', 'PH_PERF_SEL_SC1_PA6_NULL_WE', + 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC1_PA7_EOPG_WE', 'PH_PERF_SEL_SC1_PA7_EOP_WE', + 'PH_PERF_SEL_SC1_PA7_EVENT_WE', 'PH_PERF_SEL_SC1_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC1_PA7_FIFO_FULL', 'PH_PERF_SEL_SC1_PA7_FPOV_WE', + 'PH_PERF_SEL_SC1_PA7_LPOV_WE', 'PH_PERF_SEL_SC1_PA7_NULL_WE', + 'PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC1_SEND', 'PH_PERF_SEL_SC1_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC2_ARB_BUSY', + 'PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC2_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC2_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA0_EOPG_WE', 'PH_PERF_SEL_SC2_PA0_EOP_WE', + 'PH_PERF_SEL_SC2_PA0_EVENT_WE', 'PH_PERF_SEL_SC2_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA0_FIFO_FULL', 'PH_PERF_SEL_SC2_PA0_FPOV_WE', + 'PH_PERF_SEL_SC2_PA0_LPOV_WE', 'PH_PERF_SEL_SC2_PA0_NULL_WE', + 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA1_EOPG_WE', 'PH_PERF_SEL_SC2_PA1_EOP_WE', + 'PH_PERF_SEL_SC2_PA1_EVENT_WE', 'PH_PERF_SEL_SC2_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA1_FIFO_FULL', 'PH_PERF_SEL_SC2_PA1_FPOV_WE', + 'PH_PERF_SEL_SC2_PA1_LPOV_WE', 'PH_PERF_SEL_SC2_PA1_NULL_WE', + 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA2_EOPG_WE', 'PH_PERF_SEL_SC2_PA2_EOP_WE', + 'PH_PERF_SEL_SC2_PA2_EVENT_WE', 'PH_PERF_SEL_SC2_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA2_FIFO_FULL', 'PH_PERF_SEL_SC2_PA2_FPOV_WE', + 'PH_PERF_SEL_SC2_PA2_LPOV_WE', 'PH_PERF_SEL_SC2_PA2_NULL_WE', + 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA3_EOPG_WE', 'PH_PERF_SEL_SC2_PA3_EOP_WE', + 'PH_PERF_SEL_SC2_PA3_EVENT_WE', 'PH_PERF_SEL_SC2_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA3_FIFO_FULL', 'PH_PERF_SEL_SC2_PA3_FPOV_WE', + 'PH_PERF_SEL_SC2_PA3_LPOV_WE', 'PH_PERF_SEL_SC2_PA3_NULL_WE', + 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA4_EOPG_WE', 'PH_PERF_SEL_SC2_PA4_EOP_WE', + 'PH_PERF_SEL_SC2_PA4_EVENT_WE', 'PH_PERF_SEL_SC2_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA4_FIFO_FULL', 'PH_PERF_SEL_SC2_PA4_FPOV_WE', + 'PH_PERF_SEL_SC2_PA4_LPOV_WE', 'PH_PERF_SEL_SC2_PA4_NULL_WE', + 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA5_EOPG_WE', 'PH_PERF_SEL_SC2_PA5_EOP_WE', + 'PH_PERF_SEL_SC2_PA5_EVENT_WE', 'PH_PERF_SEL_SC2_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA5_FIFO_FULL', 'PH_PERF_SEL_SC2_PA5_FPOV_WE', + 'PH_PERF_SEL_SC2_PA5_LPOV_WE', 'PH_PERF_SEL_SC2_PA5_NULL_WE', + 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA6_EOPG_WE', 'PH_PERF_SEL_SC2_PA6_EOP_WE', + 'PH_PERF_SEL_SC2_PA6_EVENT_WE', 'PH_PERF_SEL_SC2_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA6_FIFO_FULL', 'PH_PERF_SEL_SC2_PA6_FPOV_WE', + 'PH_PERF_SEL_SC2_PA6_LPOV_WE', 'PH_PERF_SEL_SC2_PA6_NULL_WE', + 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC2_PA7_EOPG_WE', 'PH_PERF_SEL_SC2_PA7_EOP_WE', + 'PH_PERF_SEL_SC2_PA7_EVENT_WE', 'PH_PERF_SEL_SC2_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC2_PA7_FIFO_FULL', 'PH_PERF_SEL_SC2_PA7_FPOV_WE', + 'PH_PERF_SEL_SC2_PA7_LPOV_WE', 'PH_PERF_SEL_SC2_PA7_NULL_WE', + 'PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC2_SEND', 'PH_PERF_SEL_SC2_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC3_ARB_BUSY', + 'PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC3_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC3_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA0_EOPG_WE', 'PH_PERF_SEL_SC3_PA0_EOP_WE', + 'PH_PERF_SEL_SC3_PA0_EVENT_WE', 'PH_PERF_SEL_SC3_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA0_FIFO_FULL', 'PH_PERF_SEL_SC3_PA0_FPOV_WE', + 'PH_PERF_SEL_SC3_PA0_LPOV_WE', 'PH_PERF_SEL_SC3_PA0_NULL_WE', + 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA1_EOPG_WE', 'PH_PERF_SEL_SC3_PA1_EOP_WE', + 'PH_PERF_SEL_SC3_PA1_EVENT_WE', 'PH_PERF_SEL_SC3_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA1_FIFO_FULL', 'PH_PERF_SEL_SC3_PA1_FPOV_WE', + 'PH_PERF_SEL_SC3_PA1_LPOV_WE', 'PH_PERF_SEL_SC3_PA1_NULL_WE', + 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA2_EOPG_WE', 'PH_PERF_SEL_SC3_PA2_EOP_WE', + 'PH_PERF_SEL_SC3_PA2_EVENT_WE', 'PH_PERF_SEL_SC3_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA2_FIFO_FULL', 'PH_PERF_SEL_SC3_PA2_FPOV_WE', + 'PH_PERF_SEL_SC3_PA2_LPOV_WE', 'PH_PERF_SEL_SC3_PA2_NULL_WE', + 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA3_EOPG_WE', 'PH_PERF_SEL_SC3_PA3_EOP_WE', + 'PH_PERF_SEL_SC3_PA3_EVENT_WE', 'PH_PERF_SEL_SC3_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA3_FIFO_FULL', 'PH_PERF_SEL_SC3_PA3_FPOV_WE', + 'PH_PERF_SEL_SC3_PA3_LPOV_WE', 'PH_PERF_SEL_SC3_PA3_NULL_WE', + 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA4_EOPG_WE', 'PH_PERF_SEL_SC3_PA4_EOP_WE', + 'PH_PERF_SEL_SC3_PA4_EVENT_WE', 'PH_PERF_SEL_SC3_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA4_FIFO_FULL', 'PH_PERF_SEL_SC3_PA4_FPOV_WE', + 'PH_PERF_SEL_SC3_PA4_LPOV_WE', 'PH_PERF_SEL_SC3_PA4_NULL_WE', + 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA5_EOPG_WE', 'PH_PERF_SEL_SC3_PA5_EOP_WE', + 'PH_PERF_SEL_SC3_PA5_EVENT_WE', 'PH_PERF_SEL_SC3_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA5_FIFO_FULL', 'PH_PERF_SEL_SC3_PA5_FPOV_WE', + 'PH_PERF_SEL_SC3_PA5_LPOV_WE', 'PH_PERF_SEL_SC3_PA5_NULL_WE', + 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA6_EOPG_WE', 'PH_PERF_SEL_SC3_PA6_EOP_WE', + 'PH_PERF_SEL_SC3_PA6_EVENT_WE', 'PH_PERF_SEL_SC3_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA6_FIFO_FULL', 'PH_PERF_SEL_SC3_PA6_FPOV_WE', + 'PH_PERF_SEL_SC3_PA6_LPOV_WE', 'PH_PERF_SEL_SC3_PA6_NULL_WE', + 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC3_PA7_EOPG_WE', 'PH_PERF_SEL_SC3_PA7_EOP_WE', + 'PH_PERF_SEL_SC3_PA7_EVENT_WE', 'PH_PERF_SEL_SC3_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC3_PA7_FIFO_FULL', 'PH_PERF_SEL_SC3_PA7_FPOV_WE', + 'PH_PERF_SEL_SC3_PA7_LPOV_WE', 'PH_PERF_SEL_SC3_PA7_NULL_WE', + 'PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC3_SEND', 'PH_PERF_SEL_SC3_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC4_ARB_BUSY', + 'PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC4_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC4_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA0_EOPG_WE', 'PH_PERF_SEL_SC4_PA0_EOP_WE', + 'PH_PERF_SEL_SC4_PA0_EVENT_WE', 'PH_PERF_SEL_SC4_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA0_FIFO_FULL', 'PH_PERF_SEL_SC4_PA0_FPOV_WE', + 'PH_PERF_SEL_SC4_PA0_LPOV_WE', 'PH_PERF_SEL_SC4_PA0_NULL_WE', + 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA1_EOPG_WE', 'PH_PERF_SEL_SC4_PA1_EOP_WE', + 'PH_PERF_SEL_SC4_PA1_EVENT_WE', 'PH_PERF_SEL_SC4_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA1_FIFO_FULL', 'PH_PERF_SEL_SC4_PA1_FPOV_WE', + 'PH_PERF_SEL_SC4_PA1_LPOV_WE', 'PH_PERF_SEL_SC4_PA1_NULL_WE', + 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA2_EOPG_WE', 'PH_PERF_SEL_SC4_PA2_EOP_WE', + 'PH_PERF_SEL_SC4_PA2_EVENT_WE', 'PH_PERF_SEL_SC4_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA2_FIFO_FULL', 'PH_PERF_SEL_SC4_PA2_FPOV_WE', + 'PH_PERF_SEL_SC4_PA2_LPOV_WE', 'PH_PERF_SEL_SC4_PA2_NULL_WE', + 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA3_EOPG_WE', 'PH_PERF_SEL_SC4_PA3_EOP_WE', + 'PH_PERF_SEL_SC4_PA3_EVENT_WE', 'PH_PERF_SEL_SC4_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA3_FIFO_FULL', 'PH_PERF_SEL_SC4_PA3_FPOV_WE', + 'PH_PERF_SEL_SC4_PA3_LPOV_WE', 'PH_PERF_SEL_SC4_PA3_NULL_WE', + 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA4_EOPG_WE', 'PH_PERF_SEL_SC4_PA4_EOP_WE', + 'PH_PERF_SEL_SC4_PA4_EVENT_WE', 'PH_PERF_SEL_SC4_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA4_FIFO_FULL', 'PH_PERF_SEL_SC4_PA4_FPOV_WE', + 'PH_PERF_SEL_SC4_PA4_LPOV_WE', 'PH_PERF_SEL_SC4_PA4_NULL_WE', + 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA5_EOPG_WE', 'PH_PERF_SEL_SC4_PA5_EOP_WE', + 'PH_PERF_SEL_SC4_PA5_EVENT_WE', 'PH_PERF_SEL_SC4_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA5_FIFO_FULL', 'PH_PERF_SEL_SC4_PA5_FPOV_WE', + 'PH_PERF_SEL_SC4_PA5_LPOV_WE', 'PH_PERF_SEL_SC4_PA5_NULL_WE', + 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA6_EOPG_WE', 'PH_PERF_SEL_SC4_PA6_EOP_WE', + 'PH_PERF_SEL_SC4_PA6_EVENT_WE', 'PH_PERF_SEL_SC4_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA6_FIFO_FULL', 'PH_PERF_SEL_SC4_PA6_FPOV_WE', + 'PH_PERF_SEL_SC4_PA6_LPOV_WE', 'PH_PERF_SEL_SC4_PA6_NULL_WE', + 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC4_PA7_EOPG_WE', 'PH_PERF_SEL_SC4_PA7_EOP_WE', + 'PH_PERF_SEL_SC4_PA7_EVENT_WE', 'PH_PERF_SEL_SC4_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC4_PA7_FIFO_FULL', 'PH_PERF_SEL_SC4_PA7_FPOV_WE', + 'PH_PERF_SEL_SC4_PA7_LPOV_WE', 'PH_PERF_SEL_SC4_PA7_NULL_WE', + 'PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC4_SEND', 'PH_PERF_SEL_SC4_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC5_ARB_BUSY', + 'PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC5_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC5_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA0_EOPG_WE', 'PH_PERF_SEL_SC5_PA0_EOP_WE', + 'PH_PERF_SEL_SC5_PA0_EVENT_WE', 'PH_PERF_SEL_SC5_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA0_FIFO_FULL', 'PH_PERF_SEL_SC5_PA0_FPOV_WE', + 'PH_PERF_SEL_SC5_PA0_LPOV_WE', 'PH_PERF_SEL_SC5_PA0_NULL_WE', + 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA1_EOPG_WE', 'PH_PERF_SEL_SC5_PA1_EOP_WE', + 'PH_PERF_SEL_SC5_PA1_EVENT_WE', 'PH_PERF_SEL_SC5_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA1_FIFO_FULL', 'PH_PERF_SEL_SC5_PA1_FPOV_WE', + 'PH_PERF_SEL_SC5_PA1_LPOV_WE', 'PH_PERF_SEL_SC5_PA1_NULL_WE', + 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA2_EOPG_WE', 'PH_PERF_SEL_SC5_PA2_EOP_WE', + 'PH_PERF_SEL_SC5_PA2_EVENT_WE', 'PH_PERF_SEL_SC5_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA2_FIFO_FULL', 'PH_PERF_SEL_SC5_PA2_FPOV_WE', + 'PH_PERF_SEL_SC5_PA2_LPOV_WE', 'PH_PERF_SEL_SC5_PA2_NULL_WE', + 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA3_EOPG_WE', 'PH_PERF_SEL_SC5_PA3_EOP_WE', + 'PH_PERF_SEL_SC5_PA3_EVENT_WE', 'PH_PERF_SEL_SC5_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA3_FIFO_FULL', 'PH_PERF_SEL_SC5_PA3_FPOV_WE', + 'PH_PERF_SEL_SC5_PA3_LPOV_WE', 'PH_PERF_SEL_SC5_PA3_NULL_WE', + 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA4_EOPG_WE', 'PH_PERF_SEL_SC5_PA4_EOP_WE', + 'PH_PERF_SEL_SC5_PA4_EVENT_WE', 'PH_PERF_SEL_SC5_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA4_FIFO_FULL', 'PH_PERF_SEL_SC5_PA4_FPOV_WE', + 'PH_PERF_SEL_SC5_PA4_LPOV_WE', 'PH_PERF_SEL_SC5_PA4_NULL_WE', + 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA5_EOPG_WE', 'PH_PERF_SEL_SC5_PA5_EOP_WE', + 'PH_PERF_SEL_SC5_PA5_EVENT_WE', 'PH_PERF_SEL_SC5_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA5_FIFO_FULL', 'PH_PERF_SEL_SC5_PA5_FPOV_WE', + 'PH_PERF_SEL_SC5_PA5_LPOV_WE', 'PH_PERF_SEL_SC5_PA5_NULL_WE', + 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA6_EOPG_WE', 'PH_PERF_SEL_SC5_PA6_EOP_WE', + 'PH_PERF_SEL_SC5_PA6_EVENT_WE', 'PH_PERF_SEL_SC5_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA6_FIFO_FULL', 'PH_PERF_SEL_SC5_PA6_FPOV_WE', + 'PH_PERF_SEL_SC5_PA6_LPOV_WE', 'PH_PERF_SEL_SC5_PA6_NULL_WE', + 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC5_PA7_EOPG_WE', 'PH_PERF_SEL_SC5_PA7_EOP_WE', + 'PH_PERF_SEL_SC5_PA7_EVENT_WE', 'PH_PERF_SEL_SC5_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC5_PA7_FIFO_FULL', 'PH_PERF_SEL_SC5_PA7_FPOV_WE', + 'PH_PERF_SEL_SC5_PA7_LPOV_WE', 'PH_PERF_SEL_SC5_PA7_NULL_WE', + 'PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC5_SEND', 'PH_PERF_SEL_SC5_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC6_ARB_BUSY', + 'PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC6_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC6_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA0_EOPG_WE', 'PH_PERF_SEL_SC6_PA0_EOP_WE', + 'PH_PERF_SEL_SC6_PA0_EVENT_WE', 'PH_PERF_SEL_SC6_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA0_FIFO_FULL', 'PH_PERF_SEL_SC6_PA0_FPOV_WE', + 'PH_PERF_SEL_SC6_PA0_LPOV_WE', 'PH_PERF_SEL_SC6_PA0_NULL_WE', + 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA1_EOPG_WE', 'PH_PERF_SEL_SC6_PA1_EOP_WE', + 'PH_PERF_SEL_SC6_PA1_EVENT_WE', 'PH_PERF_SEL_SC6_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA1_FIFO_FULL', 'PH_PERF_SEL_SC6_PA1_FPOV_WE', + 'PH_PERF_SEL_SC6_PA1_LPOV_WE', 'PH_PERF_SEL_SC6_PA1_NULL_WE', + 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA2_EOPG_WE', 'PH_PERF_SEL_SC6_PA2_EOP_WE', + 'PH_PERF_SEL_SC6_PA2_EVENT_WE', 'PH_PERF_SEL_SC6_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA2_FIFO_FULL', 'PH_PERF_SEL_SC6_PA2_FPOV_WE', + 'PH_PERF_SEL_SC6_PA2_LPOV_WE', 'PH_PERF_SEL_SC6_PA2_NULL_WE', + 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA3_EOPG_WE', 'PH_PERF_SEL_SC6_PA3_EOP_WE', + 'PH_PERF_SEL_SC6_PA3_EVENT_WE', 'PH_PERF_SEL_SC6_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA3_FIFO_FULL', 'PH_PERF_SEL_SC6_PA3_FPOV_WE', + 'PH_PERF_SEL_SC6_PA3_LPOV_WE', 'PH_PERF_SEL_SC6_PA3_NULL_WE', + 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA4_EOPG_WE', 'PH_PERF_SEL_SC6_PA4_EOP_WE', + 'PH_PERF_SEL_SC6_PA4_EVENT_WE', 'PH_PERF_SEL_SC6_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA4_FIFO_FULL', 'PH_PERF_SEL_SC6_PA4_FPOV_WE', + 'PH_PERF_SEL_SC6_PA4_LPOV_WE', 'PH_PERF_SEL_SC6_PA4_NULL_WE', + 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA5_EOPG_WE', 'PH_PERF_SEL_SC6_PA5_EOP_WE', + 'PH_PERF_SEL_SC6_PA5_EVENT_WE', 'PH_PERF_SEL_SC6_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA5_FIFO_FULL', 'PH_PERF_SEL_SC6_PA5_FPOV_WE', + 'PH_PERF_SEL_SC6_PA5_LPOV_WE', 'PH_PERF_SEL_SC6_PA5_NULL_WE', + 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA6_EOPG_WE', 'PH_PERF_SEL_SC6_PA6_EOP_WE', + 'PH_PERF_SEL_SC6_PA6_EVENT_WE', 'PH_PERF_SEL_SC6_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA6_FIFO_FULL', 'PH_PERF_SEL_SC6_PA6_FPOV_WE', + 'PH_PERF_SEL_SC6_PA6_LPOV_WE', 'PH_PERF_SEL_SC6_PA6_NULL_WE', + 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC6_PA7_EOPG_WE', 'PH_PERF_SEL_SC6_PA7_EOP_WE', + 'PH_PERF_SEL_SC6_PA7_EVENT_WE', 'PH_PERF_SEL_SC6_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC6_PA7_FIFO_FULL', 'PH_PERF_SEL_SC6_PA7_FPOV_WE', + 'PH_PERF_SEL_SC6_PA7_LPOV_WE', 'PH_PERF_SEL_SC6_PA7_NULL_WE', + 'PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC6_SEND', 'PH_PERF_SEL_SC6_SRPS_WINDOW_VALID', + 'PH_PERF_SEL_SC7_ARB_BUSY', + 'PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP', + 'PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP', + 'PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP', + 'PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW', + 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE', + 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL', + 'PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY', + 'PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES', + 'PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO', + 'PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM', + 'PH_PERF_SEL_SC7_CREDIT_AT_MAX', + 'PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND', + 'PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'PH_PERF_SEL_SC7_EOP_SYNC_WINDOW', + 'PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION', + 'PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION', + 'PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION', + 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA0_EOPG_WE', 'PH_PERF_SEL_SC7_PA0_EOP_WE', + 'PH_PERF_SEL_SC7_PA0_EVENT_WE', 'PH_PERF_SEL_SC7_PA0_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA0_FIFO_FULL', 'PH_PERF_SEL_SC7_PA0_FPOV_WE', + 'PH_PERF_SEL_SC7_PA0_LPOV_WE', 'PH_PERF_SEL_SC7_PA0_NULL_WE', + 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA1_EOPG_WE', 'PH_PERF_SEL_SC7_PA1_EOP_WE', + 'PH_PERF_SEL_SC7_PA1_EVENT_WE', 'PH_PERF_SEL_SC7_PA1_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA1_FIFO_FULL', 'PH_PERF_SEL_SC7_PA1_FPOV_WE', + 'PH_PERF_SEL_SC7_PA1_LPOV_WE', 'PH_PERF_SEL_SC7_PA1_NULL_WE', + 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA2_EOPG_WE', 'PH_PERF_SEL_SC7_PA2_EOP_WE', + 'PH_PERF_SEL_SC7_PA2_EVENT_WE', 'PH_PERF_SEL_SC7_PA2_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA2_FIFO_FULL', 'PH_PERF_SEL_SC7_PA2_FPOV_WE', + 'PH_PERF_SEL_SC7_PA2_LPOV_WE', 'PH_PERF_SEL_SC7_PA2_NULL_WE', + 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA3_EOPG_WE', 'PH_PERF_SEL_SC7_PA3_EOP_WE', + 'PH_PERF_SEL_SC7_PA3_EVENT_WE', 'PH_PERF_SEL_SC7_PA3_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA3_FIFO_FULL', 'PH_PERF_SEL_SC7_PA3_FPOV_WE', + 'PH_PERF_SEL_SC7_PA3_LPOV_WE', 'PH_PERF_SEL_SC7_PA3_NULL_WE', + 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA4_EOPG_WE', 'PH_PERF_SEL_SC7_PA4_EOP_WE', + 'PH_PERF_SEL_SC7_PA4_EVENT_WE', 'PH_PERF_SEL_SC7_PA4_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA4_FIFO_FULL', 'PH_PERF_SEL_SC7_PA4_FPOV_WE', + 'PH_PERF_SEL_SC7_PA4_LPOV_WE', 'PH_PERF_SEL_SC7_PA4_NULL_WE', + 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA5_EOPG_WE', 'PH_PERF_SEL_SC7_PA5_EOP_WE', + 'PH_PERF_SEL_SC7_PA5_EVENT_WE', 'PH_PERF_SEL_SC7_PA5_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA5_FIFO_FULL', 'PH_PERF_SEL_SC7_PA5_FPOV_WE', + 'PH_PERF_SEL_SC7_PA5_LPOV_WE', 'PH_PERF_SEL_SC7_PA5_NULL_WE', + 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA6_EOPG_WE', 'PH_PERF_SEL_SC7_PA6_EOP_WE', + 'PH_PERF_SEL_SC7_PA6_EVENT_WE', 'PH_PERF_SEL_SC7_PA6_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA6_FIFO_FULL', 'PH_PERF_SEL_SC7_PA6_FPOV_WE', + 'PH_PERF_SEL_SC7_PA6_LPOV_WE', 'PH_PERF_SEL_SC7_PA6_NULL_WE', + 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD', + 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD', + 'PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE', + 'PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD', + 'PH_PERF_SEL_SC7_PA7_EOPG_WE', 'PH_PERF_SEL_SC7_PA7_EOP_WE', + 'PH_PERF_SEL_SC7_PA7_EVENT_WE', 'PH_PERF_SEL_SC7_PA7_FIFO_EMPTY', + 'PH_PERF_SEL_SC7_PA7_FIFO_FULL', 'PH_PERF_SEL_SC7_PA7_FPOV_WE', + 'PH_PERF_SEL_SC7_PA7_LPOV_WE', 'PH_PERF_SEL_SC7_PA7_NULL_WE', + 'PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE', + 'PH_PERF_SEL_SC7_SEND', 'PH_PERF_SEL_SC7_SRPS_WINDOW_VALID', + 'PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT', + 'PH_SPI_MODE_DISABLED', 'PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT', + 'PIPELINESTAT_START', 'PIPELINESTAT_STOP', 'PIPE_ALIGNED', + 'PIPE_ALIGNED_SURF', 'PIPE_COMPAT_LEVEL', 'PIPE_ID0', 'PIPE_ID1', + 'PIPE_ID2', 'PIPE_ID3', 'PIPE_INT_MASK_MODE', + 'PIPE_INT_MASK_MODE_DISABLE', 'PIPE_INT_MASK_MODE_ENABLE', + 'PIPE_INT_TYPE_MODE', 'PIPE_INT_TYPE_MODE_DISABLE', + 'PIPE_INT_TYPE_MODE_ENABLE', 'PIPE_IN_FLUSH_URGENT', + 'PIPE_IN_FLUSH_URGENT_DISABLE', 'PIPE_IN_FLUSH_URGENT_ENABLE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC', + 'PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD', + 'PIPE_PIXEL_RATE_PLL_SOURCE', + 'PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL', + 'PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL', 'PIPE_PIXEL_RATE_SOURCE', + 'PIPE_PIXEL_RATE_SOURCE_P0PLL', 'PIPE_PIXEL_RATE_SOURCE_P1PLL', + 'PIPE_PIXEL_RATE_SOURCE_P2PLL', 'PIPE_UNALIGNED_SURF', + 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1', + 'PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF', + 'PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE', 'PIXEL_PIPE_OCCLUSION_COUNT_0', + 'PIXEL_PIPE_OCCLUSION_COUNT_1', 'PIXEL_PIPE_OCCLUSION_COUNT_2', + 'PIXEL_PIPE_OCCLUSION_COUNT_3', 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MAX_EXTENTS_1', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_0', + 'PIXEL_PIPE_SCREEN_MIN_EXTENTS_1', 'PIXEL_PIPE_STAT_CONTROL', + 'PIXEL_PIPE_STAT_DUMP', 'PIXEL_PIPE_STAT_RESET', + 'PIXEL_PIPE_STRIDE_128_BITS', 'PIXEL_PIPE_STRIDE_256_BITS', + 'PIXEL_PIPE_STRIDE_32_BITS', 'PIXEL_PIPE_STRIDE_64_BITS', + 'PIX_DYNAMIC_EXPANSION', 'PIX_EXPAND_MODE', 'PIX_ZERO_EXPANSION', + 'PLL_CFG_IF_SOFT_RESET', 'PLL_CFG_IF_SOFT_RESET_FORCE', + 'PLL_CFG_IF_SOFT_RESET_NOOP', 'PM4_MEC_RELEASE_MEM_DEFINED', + 'PM4_MEC_WRITE_DATA_DEFINED', 'PM4_MES_HEADER_DEFINED', + 'PM_ASSERT_RESET', 'PM_ASSERT_RESET_0', 'PM_ASSERT_RESET_1', + 'POINTLIST', 'POWER_STATE_ENUM', 'POWER_STATE_ENUM_DS', + 'POWER_STATE_ENUM_LS', 'POWER_STATE_ENUM_ON', + 'POWER_STATE_ENUM_SD', 'PRE_CSC_BYPASS', 'PRE_CSC_MODE_ENUM', + 'PRE_CSC_SET_A', 'PRE_CSC_SET_B', 'PRE_DEGAM_BT2020', + 'PRE_DEGAM_BT2100HLG', 'PRE_DEGAM_BT2100PQ', 'PRE_DEGAM_BYPASS', + 'PRE_DEGAM_ENABLE', 'PRE_DEGAM_GAMMA_22', 'PRE_DEGAM_GAMMA_24', + 'PRE_DEGAM_GAMMA_26', 'PRE_DEGAM_MODE', 'PRE_DEGAM_SELECT', + 'PRE_DEGAM_SRGB', 'PROG_SEQ', 'PROTVIOL', 'PRQ_MRQ_FLUSH_URGENT', + 'PRQ_MRQ_FLUSH_URGENT_DISABLE', 'PRQ_MRQ_FLUSH_URGENT_ENABLE', + 'PS', 'PSLC_ASAP', 'PSLC_AUTO', 'PSLC_COUNTDOWN', + 'PSLC_ON_HANG_ONLY', 'PS_DONE', 'PS_PARTIAL_FLUSH', + 'PTE_BUFFER_MODE', 'PTE_BUFFER_MODE_0', 'PTE_BUFFER_MODE_1', + 'PTE_ROW_HEIGHT_LINEAR', 'PTE_ROW_HEIGHT_LINEAR_1024L', + 'PTE_ROW_HEIGHT_LINEAR_128L', 'PTE_ROW_HEIGHT_LINEAR_16L', + 'PTE_ROW_HEIGHT_LINEAR_256L', 'PTE_ROW_HEIGHT_LINEAR_32L', + 'PTE_ROW_HEIGHT_LINEAR_512L', 'PTE_ROW_HEIGHT_LINEAR_64L', + 'PTE_ROW_HEIGHT_LINEAR_8L', + 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN', + 'PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT', + 'PWRSEQ_BL_PWM_CNTL_BL_PWM_EN', + 'PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN', + 'PWRSEQ_BL_PWM_DISABLE', 'PWRSEQ_BL_PWM_ENABLE', + 'PWRSEQ_BL_PWM_FRACTIONAL_DISABLE', + 'PWRSEQ_BL_PWM_FRACTIONAL_ENABLE', + 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE', + 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN', + 'PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE', + 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN', + 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM', + 'PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM', + 'PWRSEQ_BL_PWM_GRP1_REG_LOCK', + 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE', + 'PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE', + 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START', + 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE', + 'PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE', + 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE', + 'PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE', + 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL', + 'PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3', + 'PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL', + 'PWRSEQ_GPIO_MASK_EN', 'PWRSEQ_GPIO_MASK_EN_HARDWARE', + 'PWRSEQ_GPIO_MASK_EN_SOFTWARE', 'PWRSEQ_PANEL_BLON_OFF', + 'PWRSEQ_PANEL_BLON_ON', 'PWRSEQ_PANEL_BLON_POL_INVERT', + 'PWRSEQ_PANEL_BLON_POL_NON_INVERT', 'PWRSEQ_PANEL_DIGON_OFF', + 'PWRSEQ_PANEL_DIGON_ON', 'PWRSEQ_PANEL_DIGON_POL_INVERT', + 'PWRSEQ_PANEL_DIGON_POL_NON_INVERT', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL', + 'PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE', + 'PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN', + 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF', + 'PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON', + 'PWRSEQ_PANEL_SYNCEN_POL_INVERT', + 'PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT', + 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON', + 'PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE', 'PerfCounter_Vals', + 'PhSPIstatusMode', 'PixelPipeCounterId', 'PixelPipeStride', + 'PkrMap', 'PkrXsel', 'PkrXsel2', 'PkrYsel', 'RAMA', 'RAMA_ACCESS', + 'RAMB', 'RAMB_ACCESS', 'RAM_LUT', 'RANGE_00', 'RANGE_FF', + 'RASTER_CONFIG_PKR_MAP_0', 'RASTER_CONFIG_PKR_MAP_1', + 'RASTER_CONFIG_PKR_MAP_2', 'RASTER_CONFIG_PKR_MAP_3', + 'RASTER_CONFIG_PKR_XSEL2_0', 'RASTER_CONFIG_PKR_XSEL2_1', + 'RASTER_CONFIG_PKR_XSEL2_2', 'RASTER_CONFIG_PKR_XSEL2_3', + 'RASTER_CONFIG_PKR_XSEL_0', 'RASTER_CONFIG_PKR_XSEL_1', + 'RASTER_CONFIG_PKR_XSEL_2', 'RASTER_CONFIG_PKR_XSEL_3', + 'RASTER_CONFIG_PKR_YSEL_0', 'RASTER_CONFIG_PKR_YSEL_1', + 'RASTER_CONFIG_PKR_YSEL_2', 'RASTER_CONFIG_PKR_YSEL_3', + 'RASTER_CONFIG_RB_MAP_0', 'RASTER_CONFIG_RB_MAP_1', + 'RASTER_CONFIG_RB_MAP_2', 'RASTER_CONFIG_RB_MAP_3', + 'RASTER_CONFIG_RB_XSEL2_0', 'RASTER_CONFIG_RB_XSEL2_1', + 'RASTER_CONFIG_RB_XSEL2_2', 'RASTER_CONFIG_RB_XSEL2_3', + 'RASTER_CONFIG_RB_XSEL_0', 'RASTER_CONFIG_RB_XSEL_1', + 'RASTER_CONFIG_RB_YSEL_0', 'RASTER_CONFIG_RB_YSEL_1', + 'RASTER_CONFIG_SC_MAP_0', 'RASTER_CONFIG_SC_MAP_1', + 'RASTER_CONFIG_SC_MAP_2', 'RASTER_CONFIG_SC_MAP_3', + 'RASTER_CONFIG_SC_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SC_YSEL_8_WIDE_TILE', 'RASTER_CONFIG_SE_MAP_0', + 'RASTER_CONFIG_SE_MAP_1', 'RASTER_CONFIG_SE_MAP_2', + 'RASTER_CONFIG_SE_MAP_3', 'RASTER_CONFIG_SE_PAIR_MAP_0', + 'RASTER_CONFIG_SE_PAIR_MAP_1', 'RASTER_CONFIG_SE_PAIR_MAP_2', + 'RASTER_CONFIG_SE_PAIR_MAP_3', + 'RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_XSEL_8_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_16_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_32_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_64_WIDE_TILE', + 'RASTER_CONFIG_SE_YSEL_8_WIDE_TILE', 'RAW', + 'RDPCSPIPE_APBCLK_DISABLE', 'RDPCSPIPE_APBCLK_ENABLE', + 'RDPCSPIPE_APB_PSLVERR_MASK_DISABLE', + 'RDPCSPIPE_APB_PSLVERR_MASK_ENABLE', + 'RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS', + 'RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS', + 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN', + 'RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN', + 'RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET', + 'RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET', + 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK', + 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE', + 'RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE', + 'RDPCSPIPE_DBG_OCLA_SEL', 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56', + 'RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0', + 'RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE', + 'RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE', + 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE', + 'RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE', + 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE', + 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE', + 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE', + 'RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE', + 'RDPCSPIPE_ENC_TYPE', 'RDPCSPIPE_EXT_PCLK_EN_DISABLE', + 'RDPCSPIPE_EXT_PCLK_EN_ENABLE', 'RDPCSPIPE_FIFO_EMPTY', + 'RDPCSPIPE_FIFO_FULL', 'RDPCSPIPE_FIFO_IS_EMPTY', + 'RDPCSPIPE_FIFO_IS_FULL', 'RDPCSPIPE_FIFO_NOT_EMPTY', + 'RDPCSPIPE_FIFO_NOT_FULL', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK', + 'RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK', + 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE', + 'RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE', + 'RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE', + 'RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE', + 'RDPCSPIPE_MEM_PWR_DEEP_SLEEP', 'RDPCSPIPE_MEM_PWR_LIGHT_SLEEP', + 'RDPCSPIPE_MEM_PWR_NO_FORCE', + 'RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP', + 'RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP', + 'RDPCSPIPE_MEM_PWR_PWR_STATE_ON', + 'RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN', + 'RDPCSPIPE_MEM_PWR_SHUT_DOWN', + 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK', + 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE', + 'RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE', + 'RDPCSPIPE_PACK_MODE', 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL', + 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL', + 'RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE', + 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE', + 'RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE', + 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV', + 'RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV', + 'RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV', + 'RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL', + 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT', + 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE', + 'RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH', + 'RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE', + 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC', + 'RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB', + 'RDPCSPIPE_PHY_CR_PARA_SEL_CR', 'RDPCSPIPE_PHY_CR_PARA_SEL_JTAG', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6', + 'RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3', + 'RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8', + 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT', + 'RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT', + 'RDPCSPIPE_PHY_DP_TX_RATE', 'RDPCSPIPE_PHY_DP_TX_RATE_DIV2', + 'RDPCSPIPE_PHY_DP_TX_RATE_DIV4', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52', + 'RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54', + 'RDPCSPIPE_PHY_DP_TX_WIDTH_10', 'RDPCSPIPE_PHY_DP_TX_WIDTH_16', + 'RDPCSPIPE_PHY_DP_TX_WIDTH_20', 'RDPCSPIPE_PHY_DP_TX_WIDTH_8', + 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0', + 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1', + 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2', + 'RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3', + 'RDPCSPIPE_PHY_IF_WIDTH', 'RDPCSPIPE_PHY_RATE', + 'RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE', + 'RDPCSPIPE_PHY_REF_ALT_CLK_EN', + 'RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE', 'RDPCSPIPE_PHY_REF_RANGE_0', + 'RDPCSPIPE_PHY_REF_RANGE_1', 'RDPCSPIPE_PHY_REF_RANGE_2', + 'RDPCSPIPE_PHY_REF_RANGE_3', 'RDPCSPIPE_PHY_REF_RANGE_4', + 'RDPCSPIPE_PHY_REF_RANGE_5', 'RDPCSPIPE_PHY_REF_RANGE_6', + 'RDPCSPIPE_PHY_REF_RANGE_7', + 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE', + 'RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE', + 'RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE', + 'RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE', + 'RDPCSPIPE_SRAMCLK_DISABLE', 'RDPCSPIPE_SRAMCLK_ENABLE', + 'RDPCSPIPE_SRAMCLK_GATE_DISABLE', 'RDPCSPIPE_SRAMCLK_GATE_ENABLE', + 'RDPCSPIPE_SRAMCLK_NOT_PASS', 'RDPCSPIPE_SRAMCLK_PASS', + 'RDPCSPIPE_SRAM_EXT_LD_DONE', 'RDPCSPIPE_SRAM_EXT_LD_NOT_DONE', + 'RDPCSPIPE_SRAM_INIT_DONE', 'RDPCSPIPE_SRAM_INIT_NOT_DONE', + 'RDPCSPIPE_SRAM_SRAM_RESET_DISABLE', + 'RDPCSPIPE_SRAM_SRAM_RESET_ENABLE', + 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF', + 'RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON', 'RDPCSPIPE_TEST_CLK_SEL', + 'RDPCSPIPE_TEST_CLK_SEL_CFGCLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_NONE', + 'RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK', + 'RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk', + 'RDPCSPIPE_TEST_CLK_SEL_SRAMCLK', + 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS', + 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4', + 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS', + 'RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4', + 'RDPCSPIPE_TEST_CLK_SEL_dtb_out0', + 'RDPCSPIPE_TEST_CLK_SEL_dtb_out1', 'RDPCS_PIPE_CLK_CLOCK_OFF', + 'RDPCS_PIPE_CLK_CLOCK_ON', 'RDPCS_PIPE_CLK_DISABLE', + 'RDPCS_PIPE_CLK_ENABLE', 'RDPCS_PIPE_CLK_GATE_DISABLE', + 'RDPCS_PIPE_CLK_GATE_ENABLE', + 'RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB', + 'RDPCS_PIPE_FIFO_DISABLE', 'RDPCS_PIPE_FIFO_ENABLE', + 'RDPCS_PIPE_FIFO_LANE_DISABLE', 'RDPCS_PIPE_FIFO_LANE_ENABLE', + 'RDPCS_PIPE_PHYD32CLK_CLOCK_OFF', 'RDPCS_PIPE_PHYD32CLK_CLOCK_ON', + 'RDPCS_PIPE_SOFT_RESET_DISABLE', 'RDPCS_PIPE_SOFT_RESET_ENABLE', + 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE', + 'RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE', 'READ_SEQ', + 'RECTLIST', 'RECT_2D', 'RED_LUT', 'REFER_TO_DP_SOF', + 'REFER_TO_OTG_SOF', 'REG_SECURE_VIOLATE_READ', + 'REG_SECURE_VIOLATE_WRITE', 'REG_UNALLOCATED_ADDR_READ', + 'REG_UNALLOCATED_ADDR_WRITE', 'REG_VIRTUAL_READ', + 'REG_VIRTUAL_WRITE', 'RESERVED_1', 'RESERVED_10', 'RESERVED_11', + 'RESERVED_20', 'RESERVED_21', 'RESERVED_22', 'RESERVED_23', + 'RESERVED_3', 'RESERVED_32', 'RESERVED_33', 'RESERVED_34', + 'RESERVED_35', 'RESERVED_44', 'RESERVED_45', 'RESERVED_46', + 'RESERVED_47', 'RESERVED_56', 'RESERVED_57', 'RESERVED_58', + 'RESERVED_59', 'RESERVED_60', 'RESERVED_61', 'RESERVED_62', + 'RESERVED_63', 'RESERVED_72', 'RESERVED_73', 'RESERVED_74', + 'RESERVED_75', 'RESERVED_8', 'RESERVED_84', 'RESERVED_85', + 'RESERVED_86', 'RESERVED_87', 'RESERVED_88', 'RESERVED_89', + 'RESERVED_9', 'RESERVED_90', 'RESERVED_91', 'RESERVED_ES', + 'RESERVED_LS', 'RESERVED_RDPOLICY', 'RESERVED_VS', + 'RESET_TO_LOWEST_VGT', 'RESET_VTX_CNT', 'RESPONSE_STATUS', 'RE_Z', + 'RGB111110_FIX', 'RGB111110_FLOAT', 'RGB565', 'RGBA1010102', + 'RGBA16161616_10LSB', 'RGBA16161616_10MSB', 'RGBA16161616_12LSB', + 'RGBA16161616_12MSB', 'RGBA16161616_FLOAT', 'RGBA16161616_SNORM', + 'RGBA16161616_UNORM', 'RGBA4444', 'RGBA5551', 'RGBA8888', 'RGBE', + 'RINGID0', 'RINGID1', 'RINGID2', 'RINGID3', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED', + 'RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED', + 'RLC_DOORBELL_MODE', 'RLC_DOORBELL_MODE_DISABLE', + 'RLC_DOORBELL_MODE_ENABLE', 'RLC_DOORBELL_MODE_ENABLE_PF', + 'RLC_DOORBELL_MODE_ENABLE_PF_VF', 'RLC_PERFCOUNTER_SEL', + 'RLC_PERFMON_STATE', 'RLC_PERFMON_STATE_DISABLE', + 'RLC_PERFMON_STATE_ENABLE', 'RLC_PERFMON_STATE_RESERVED_3', + 'RLC_PERFMON_STATE_RESERVED_4', 'RLC_PERFMON_STATE_RESERVED_5', + 'RLC_PERFMON_STATE_RESERVED_6', 'RLC_PERFMON_STATE_RESET', + 'RLC_PERFMON_STATE_ROLLOVER', 'RLC_PERF_SEL_CP_INTERRUPT', + 'RLC_PERF_SEL_GRBM_INTERRUPT', 'RLC_PERF_SEL_IH_INTERRUPT', + 'RLC_PERF_SEL_POWER_FEATURE_0', 'RLC_PERF_SEL_POWER_FEATURE_1', + 'RLC_PERF_SEL_SERDES_COMMAND_WRITE', 'RLC_PERF_SEL_SPM_INTERRUPT', + 'RMIPerfSel', 'RMI_CID', 'RMI_CID_CC', 'RMI_CID_CM', 'RMI_CID_DC', + 'RMI_CID_FC', 'RMI_CID_S', 'RMI_CID_TILE', 'RMI_CID_Z', + 'RMI_CID_ZPCPSD', 'RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID', + 'RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID', 'ROM_SIGNATURE', + 'ROTATE_0_DEGREES', 'ROTATE_180_DEGREES', 'ROTATE_270_DEGREES', + 'ROTATE_90_DEGREES', 'ROTATION_ANGLE', 'ROW_TTU_MODE', + 'RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK', + 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD', + 'RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF', + 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN', + 'RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP', 'RSPM_CMD', + 'RSPM_CMD_CALIBRATE', 'RSPM_CMD_FORCE_SAMPLE', 'RSPM_CMD_IDLE', + 'RSPM_CMD_INVALID', 'RSPM_CMD_PERF_RESET', 'RSPM_CMD_PERF_SAMPLE', + 'RSPM_CMD_PROF_START', 'RSPM_CMD_PROF_STOP', 'RSPM_CMD_SPM_RESET', + 'RSPM_CMD_SPM_START', 'RSPM_CMD_SPM_STOP', 'RST_PIX_CNT', + 'RSV_TAG_RAM', 'RbMap', 'RbXsel', 'RbXsel2', 'RbYsel', + 'ReadPolicy', 'Reserved_0x00', 'Reserved_0x09', + 'RingCounterControl', 'SAMPLE_PIPELINESTAT', + 'SAMPLE_STREAMOUTSTATS', 'SAMPLE_STREAMOUTSTATS1', + 'SAMPLE_STREAMOUTSTATS2', 'SAMPLE_STREAMOUTSTATS3', + 'SCL_2TAP_HARDCODE', 'SCL_ALPHA_COEF', 'SCL_ALPHA_COEF_FIRST', + 'SCL_ALPHA_COEF_SECOND', 'SCL_AUTOCAL_MODE', 'SCL_BOUNDARY', + 'SCL_BOUNDARY_BLACK', 'SCL_BOUNDARY_EDGE', 'SCL_CHROMA_COEF', + 'SCL_CHROMA_COEF_FIRST', 'SCL_CHROMA_COEF_SECOND', + 'SCL_COEF_2TAP_HARDCODE_OFF', 'SCL_COEF_2TAP_HARDCODE_ON', + 'SCL_COEF_CHROMA_HORZ_FILTER', 'SCL_COEF_CHROMA_VERT_FILTER', + 'SCL_COEF_FILTER_TYPE_SEL', 'SCL_COEF_LUMA_HORZ_FILTER', + 'SCL_COEF_LUMA_VERT_FILTER', 'SCL_COEF_RAM_SEL', + 'SCL_COEF_RAM_SEL_0', 'SCL_COEF_RAM_SEL_1', 'SCL_SHARP_DISABLE', + 'SCL_SHARP_EN', 'SCL_SHARP_ENABLE', 'SC_BACKEND_BUSY', + 'SC_BACKEND_PRIM_FIFO_FULL', 'SC_BB_DISCARD', + 'SC_BCI_CREDIT_AT_MAX', 'SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND', + 'SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_BCI_SEND', + 'SC_BM_BE0_STALLED', 'SC_BM_BE1_STALLED', 'SC_BM_BE2_STALLED', + 'SC_BM_BE3_STALLED', 'SC_BM_BUSY', + 'SC_BM_MULTI_ACCUM_1_BE_STALLED', + 'SC_BM_MULTI_ACCUM_2_BE_STALLED', + 'SC_BM_MULTI_ACCUM_3_BE_STALLED', + 'SC_BM_MULTI_ACCUM_4_BE_STALLED', 'SC_BUSY_CNT_NOT_ZERO', + 'SC_BUSY_PROCESSING_MULTICYCLE_PRIM', 'SC_DB0_QUAD_INTF_BUSY', + 'SC_DB0_QUAD_INTF_CREDIT_AT_MAX', 'SC_DB0_QUAD_INTF_IDLE', + 'SC_DB0_QUAD_INTF_SEND', 'SC_DB0_QUAD_INTF_STALLED_BY_DB', + 'SC_DB0_TILE_INTERFACE_BUSY', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 'SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'SC_DB0_TILE_INTERFACE_SEND', 'SC_DB0_TILE_INTERFACE_SEND_EVENT', + 'SC_DB0_TILE_INTERFACE_SEND_SOP', + 'SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 'SC_DB0_TILE_MASK_FIFO_FULL', + 'SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL', + 'SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 'SC_DB1_QUAD_INTF_BUSY', 'SC_DB1_QUAD_INTF_CREDIT_AT_MAX', + 'SC_DB1_QUAD_INTF_IDLE', 'SC_DB1_QUAD_INTF_SEND', + 'SC_DB1_QUAD_INTF_STALLED_BY_DB', 'SC_DB1_TILE_INTERFACE_BUSY', + 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX', + 'SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND', + 'SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND', + 'SC_DB1_TILE_INTERFACE_SEND', 'SC_DB1_TILE_INTERFACE_SEND_EVENT', + 'SC_DB1_TILE_INTERFACE_SEND_SOP', + 'SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT', + 'SC_DB1_TILE_MASK_FIFO_FULL', + 'SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL', + 'SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL', + 'SC_EARLYZ_QUAD_COUNT', 'SC_EARLYZ_QUAD_WITH_1_PIX', + 'SC_EARLYZ_QUAD_WITH_2_PIX', 'SC_EARLYZ_QUAD_WITH_3_PIX', + 'SC_EARLYZ_QUAD_WITH_4_PIX', 'SC_EOP_SYNC_WINDOW', + 'SC_FSR_WALKED', 'SC_FULL_FULL_QUAD', 'SC_FULL_HALF_QUAD', + 'SC_FULL_QTR_QUAD', 'SC_GRP0_DYN_SCLK_BUSY', + 'SC_GRP1_DYN_SCLK_BUSY', 'SC_GRP2_DYN_SCLK_BUSY', + 'SC_GRP3_DYN_SCLK_BUSY', 'SC_GRP4_DYN_SCLK_BUSY', + 'SC_GRP5_DYN_SCLK_BUSY', 'SC_GRP6_DYN_SCLK_BUSY', + 'SC_GRP7_DYN_SCLK_BUSY', 'SC_GRP8_DYN_SCLK_BUSY', + 'SC_GRP9_DYN_SCLK_BUSY', 'SC_HALF_FULL_QUAD', 'SC_HALF_HALF_QUAD', + 'SC_HALF_LSB', 'SC_HALF_QTR_QUAD', 'SC_LSB_ONE_SIDED', + 'SC_LSB_TWO_SIDED', 'SC_MULTICYCLE_BUBBLE_FREEZE', + 'SC_P0_DETAIL_QUAD_COUNT', 'SC_P0_DETAIL_QUAD_WITH_1_PIX', + 'SC_P0_DETAIL_QUAD_WITH_2_PIX', 'SC_P0_DETAIL_QUAD_WITH_3_PIX', + 'SC_P0_DETAIL_QUAD_WITH_4_PIX', 'SC_P0_HIZ_QUAD_COUNT', + 'SC_P0_HIZ_QUAD_PER_TILE_H0', 'SC_P0_HIZ_QUAD_PER_TILE_H1', + 'SC_P0_HIZ_QUAD_PER_TILE_H10', 'SC_P0_HIZ_QUAD_PER_TILE_H11', + 'SC_P0_HIZ_QUAD_PER_TILE_H12', 'SC_P0_HIZ_QUAD_PER_TILE_H13', + 'SC_P0_HIZ_QUAD_PER_TILE_H14', 'SC_P0_HIZ_QUAD_PER_TILE_H15', + 'SC_P0_HIZ_QUAD_PER_TILE_H16', 'SC_P0_HIZ_QUAD_PER_TILE_H2', + 'SC_P0_HIZ_QUAD_PER_TILE_H3', 'SC_P0_HIZ_QUAD_PER_TILE_H4', + 'SC_P0_HIZ_QUAD_PER_TILE_H5', 'SC_P0_HIZ_QUAD_PER_TILE_H6', + 'SC_P0_HIZ_QUAD_PER_TILE_H7', 'SC_P0_HIZ_QUAD_PER_TILE_H8', + 'SC_P0_HIZ_QUAD_PER_TILE_H9', 'SC_P0_HIZ_TILE_COUNT', + 'SC_P1_DETAIL_QUAD_COUNT', 'SC_P1_DETAIL_QUAD_WITH_1_PIX', + 'SC_P1_DETAIL_QUAD_WITH_2_PIX', 'SC_P1_DETAIL_QUAD_WITH_3_PIX', + 'SC_P1_DETAIL_QUAD_WITH_4_PIX', 'SC_P1_HIZ_QUAD_COUNT', + 'SC_P1_HIZ_QUAD_PER_TILE_H0', 'SC_P1_HIZ_QUAD_PER_TILE_H1', + 'SC_P1_HIZ_QUAD_PER_TILE_H10', 'SC_P1_HIZ_QUAD_PER_TILE_H11', + 'SC_P1_HIZ_QUAD_PER_TILE_H12', 'SC_P1_HIZ_QUAD_PER_TILE_H13', + 'SC_P1_HIZ_QUAD_PER_TILE_H14', 'SC_P1_HIZ_QUAD_PER_TILE_H15', + 'SC_P1_HIZ_QUAD_PER_TILE_H16', 'SC_P1_HIZ_QUAD_PER_TILE_H2', + 'SC_P1_HIZ_QUAD_PER_TILE_H3', 'SC_P1_HIZ_QUAD_PER_TILE_H4', + 'SC_P1_HIZ_QUAD_PER_TILE_H5', 'SC_P1_HIZ_QUAD_PER_TILE_H6', + 'SC_P1_HIZ_QUAD_PER_TILE_H7', 'SC_P1_HIZ_QUAD_PER_TILE_H8', + 'SC_P1_HIZ_QUAD_PER_TILE_H9', 'SC_P1_HIZ_TILE_COUNT', + 'SC_P2_DETAIL_QUAD_COUNT', 'SC_P2_DETAIL_QUAD_WITH_1_PIX', + 'SC_P2_DETAIL_QUAD_WITH_2_PIX', 'SC_P2_DETAIL_QUAD_WITH_3_PIX', + 'SC_P2_DETAIL_QUAD_WITH_4_PIX', 'SC_P2_HIZ_QUAD_COUNT', + 'SC_P2_HIZ_QUAD_PER_TILE_H0', 'SC_P2_HIZ_QUAD_PER_TILE_H1', + 'SC_P2_HIZ_QUAD_PER_TILE_H10', 'SC_P2_HIZ_QUAD_PER_TILE_H11', + 'SC_P2_HIZ_QUAD_PER_TILE_H12', 'SC_P2_HIZ_QUAD_PER_TILE_H13', + 'SC_P2_HIZ_QUAD_PER_TILE_H14', 'SC_P2_HIZ_QUAD_PER_TILE_H15', + 'SC_P2_HIZ_QUAD_PER_TILE_H16', 'SC_P2_HIZ_QUAD_PER_TILE_H2', + 'SC_P2_HIZ_QUAD_PER_TILE_H3', 'SC_P2_HIZ_QUAD_PER_TILE_H4', + 'SC_P2_HIZ_QUAD_PER_TILE_H5', 'SC_P2_HIZ_QUAD_PER_TILE_H6', + 'SC_P2_HIZ_QUAD_PER_TILE_H7', 'SC_P2_HIZ_QUAD_PER_TILE_H8', + 'SC_P2_HIZ_QUAD_PER_TILE_H9', 'SC_P2_HIZ_TILE_COUNT', + 'SC_P3_DETAIL_QUAD_COUNT', 'SC_P3_DETAIL_QUAD_WITH_1_PIX', + 'SC_P3_DETAIL_QUAD_WITH_2_PIX', 'SC_P3_DETAIL_QUAD_WITH_3_PIX', + 'SC_P3_DETAIL_QUAD_WITH_4_PIX', 'SC_P3_HIZ_QUAD_COUNT', + 'SC_P3_HIZ_QUAD_PER_TILE_H0', 'SC_P3_HIZ_QUAD_PER_TILE_H1', + 'SC_P3_HIZ_QUAD_PER_TILE_H10', 'SC_P3_HIZ_QUAD_PER_TILE_H11', + 'SC_P3_HIZ_QUAD_PER_TILE_H12', 'SC_P3_HIZ_QUAD_PER_TILE_H13', + 'SC_P3_HIZ_QUAD_PER_TILE_H14', 'SC_P3_HIZ_QUAD_PER_TILE_H15', + 'SC_P3_HIZ_QUAD_PER_TILE_H16', 'SC_P3_HIZ_QUAD_PER_TILE_H2', + 'SC_P3_HIZ_QUAD_PER_TILE_H3', 'SC_P3_HIZ_QUAD_PER_TILE_H4', + 'SC_P3_HIZ_QUAD_PER_TILE_H5', 'SC_P3_HIZ_QUAD_PER_TILE_H6', + 'SC_P3_HIZ_QUAD_PER_TILE_H7', 'SC_P3_HIZ_QUAD_PER_TILE_H8', + 'SC_P3_HIZ_QUAD_PER_TILE_H9', 'SC_P3_HIZ_TILE_COUNT', + 'SC_PA0_SC_DATA_FIFO_EOPG_RD', 'SC_PA0_SC_DATA_FIFO_EOP_RD', + 'SC_PA0_SC_DATA_FIFO_RD', 'SC_PA0_SC_DATA_FIFO_WE', + 'SC_PA0_SC_DEALLOC_0_RD', 'SC_PA0_SC_DEALLOC_1_RD', + 'SC_PA0_SC_EOPG_WE', 'SC_PA0_SC_EOP_WE', 'SC_PA0_SC_EVENT_WE', + 'SC_PA0_SC_FPOV_WE', 'SC_PA0_SC_LPOV_WE', + 'SC_PA0_SC_NULL_DEALLOC_WE', 'SC_PA0_SC_NULL_WE', + 'SC_PA1_SC_DATA_FIFO_EOPG_RD', 'SC_PA1_SC_DATA_FIFO_EOP_RD', + 'SC_PA1_SC_DATA_FIFO_RD', 'SC_PA1_SC_DATA_FIFO_WE', + 'SC_PA1_SC_DEALLOC_0_RD', 'SC_PA1_SC_DEALLOC_1_RD', + 'SC_PA1_SC_EOPG_WE', 'SC_PA1_SC_EOP_WE', 'SC_PA1_SC_EVENT_WE', + 'SC_PA1_SC_FPOV_WE', 'SC_PA1_SC_LPOV_WE', + 'SC_PA1_SC_NULL_DEALLOC_WE', 'SC_PA1_SC_NULL_WE', + 'SC_PA2_SC_DATA_FIFO_EOPG_RD', 'SC_PA2_SC_DATA_FIFO_EOP_RD', + 'SC_PA2_SC_DATA_FIFO_RD', 'SC_PA2_SC_DATA_FIFO_WE', + 'SC_PA2_SC_DEALLOC_0_RD', 'SC_PA2_SC_DEALLOC_1_RD', + 'SC_PA2_SC_EOPG_WE', 'SC_PA2_SC_EOP_WE', 'SC_PA2_SC_EVENT_WE', + 'SC_PA2_SC_FPOV_WE', 'SC_PA2_SC_LPOV_WE', + 'SC_PA2_SC_NULL_DEALLOC_WE', 'SC_PA2_SC_NULL_WE', + 'SC_PA3_SC_DATA_FIFO_EOPG_RD', 'SC_PA3_SC_DATA_FIFO_EOP_RD', + 'SC_PA3_SC_DATA_FIFO_RD', 'SC_PA3_SC_DATA_FIFO_WE', + 'SC_PA3_SC_DEALLOC_0_RD', 'SC_PA3_SC_DEALLOC_1_RD', + 'SC_PA3_SC_EOPG_WE', 'SC_PA3_SC_EOP_WE', 'SC_PA3_SC_EVENT_WE', + 'SC_PA3_SC_FPOV_WE', 'SC_PA3_SC_LPOV_WE', + 'SC_PA3_SC_NULL_DEALLOC_WE', 'SC_PA3_SC_NULL_WE', + 'SC_PA_SC_DEALLOC_0_0_WE', 'SC_PA_SC_DEALLOC_0_1_WE', + 'SC_PA_SC_DEALLOC_1_0_WE', 'SC_PA_SC_DEALLOC_1_1_WE', + 'SC_PA_SC_DEALLOC_2_0_WE', 'SC_PA_SC_DEALLOC_2_1_WE', + 'SC_PA_SC_DEALLOC_3_0_WE', 'SC_PA_SC_DEALLOC_3_1_WE', + 'SC_PA_TO_PBB_SCLK_GATE_STALL_STALL', + 'SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH', + 'SC_PBB_BATCH_BREAK_DUE_TO_EVENT', + 'SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT', + 'SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE', + 'SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH', + 'SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV', + 'SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT', + 'SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT', + 'SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE', + 'SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET', + 'SC_PBB_BATCH_BREAK_DUE_TO_PRIM', + 'SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER', + 'SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW', + 'SC_PBB_BATCH_HIST_NUM_CONTEXTS', + 'SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BATCH_HIST_NUM_PRIMS', + 'SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS', + 'SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM', + 'SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS', + 'SC_PBB_BIN_HIST_NUM_CONTEXTS', + 'SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES', + 'SC_PBB_BIN_HIST_NUM_PRIMS', 'SC_PBB_BUSY', + 'SC_PBB_BUSY_AND_NO_SENDS', + 'SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN', 'SC_PBB_END_OF_BATCH', + 'SC_PBB_END_OF_BIN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN', + 'SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW', + 'SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION', + 'SC_PBB_NONBINNED_PRIM', 'SC_PBB_NUM_BINS', + 'SC_PBB_PRIMBIN_PROCESSED', 'SC_PBB_PRIM_ADDED_TO_BATCH', + 'SC_PBB_RESERVED', 'SC_PBB_STALLS_PA_DUE_TO_NO_TILES', + 'SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB', + 'SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB', 'SC_PERFCNT_SEL', + 'SC_PKR_4X2_FILL_QUAD', 'SC_PKR_4X2_QUAD_SPLIT', + 'SC_PKR_CONTROL_XFER', 'SC_PKR_DBHANG_FORCE_EOV', + 'SC_PKR_END_OF_VECTOR', 'SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE', + 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP', + 'SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX', + 'SC_PKR_QUAD_PER_ROW_H1', 'SC_PKR_QUAD_PER_ROW_H2', + 'SC_PKR_WAVE_BREAK_FULL_TILE', 'SC_PKR_WAVE_BREAK_OUTSIDE_REGION', + 'SC_PK_BUSY', 'SC_PK_DEALLOC_WAVE_BREAK', + 'SC_PK_MAX_DEALLOC_FORCE_EOV', 'SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H', + 'SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H', + 'SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 'SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H', + 'SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H', + 'SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H', + 'SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H', + 'SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 'SC_PK_PM_FULL_TILE_WAVE_BRK_1H', + 'SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H', + 'SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H', + 'SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H', + 'SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H', + 'SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H', + 'SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H', + 'SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H', + 'SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD', + 'SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD', + 'SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H', + 'SC_POPS_FORCE_EOV', 'SC_POPS_INTRA_WAVE_OVERLAPS', + 'SC_PSSW_WINDOW_VALID', 'SC_PSSW_WINDOW_VALID_BUSY', + 'SC_PS_ARB_EOP_POP_SYNC_POP', 'SC_PS_ARB_EVENT_SYNC_POP', + 'SC_PS_ARB_NULL_PRIM_BUBBLE_POP', + 'SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH', + 'SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO', + 'SC_PS_ARB_PA_SC_BUSY', 'SC_PS_ARB_SC_BUSY', + 'SC_PS_ARB_STALLED_FROM_BELOW', 'SC_PS_ARB_STARVED_FROM_ABOVE', + 'SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES', + 'SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM', + 'SC_PS_ARB_XFC_ONLY_PRIM_CYCLES', 'SC_PS_CTX_DONE_FIFO_POP', + 'SC_PS_CTX_DONE_FIFO_PUSH', 'SC_PS_ENG_MULTICYCLE_BUBBLE', + 'SC_PS_PA0_SC_FIFO_EMPTY', 'SC_PS_PA0_SC_FIFO_FULL', + 'SC_PS_PA1_SC_FIFO_EMPTY', 'SC_PS_PA1_SC_FIFO_FULL', + 'SC_PS_PA2_SC_FIFO_EMPTY', 'SC_PS_PA2_SC_FIFO_FULL', + 'SC_PS_PA3_SC_FIFO_EMPTY', 'SC_PS_PA3_SC_FIFO_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL', + 'SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL', + 'SC_PS_PM_PFF_PW_FULL', 'SC_PS_PM_ZFF_PW_FULL', + 'SC_PS_TO_BE_SCLK_GATE_STALL', 'SC_PS_TS_EVENT_FIFO_POP', + 'SC_PS_TS_EVENT_FIFO_PUSH', 'SC_PW_BM_PASS_EMPTY_PRIM', + 'SC_QTR_FULL_QUAD', 'SC_QTR_HALF_QUAD', 'SC_QTR_QTR_QUAD', + 'SC_QZ0_QUAD_COUNT', 'SC_QZ0_QUAD_PER_TILE_H0', + 'SC_QZ0_QUAD_PER_TILE_H1', 'SC_QZ0_QUAD_PER_TILE_H10', + 'SC_QZ0_QUAD_PER_TILE_H11', 'SC_QZ0_QUAD_PER_TILE_H12', + 'SC_QZ0_QUAD_PER_TILE_H13', 'SC_QZ0_QUAD_PER_TILE_H14', + 'SC_QZ0_QUAD_PER_TILE_H15', 'SC_QZ0_QUAD_PER_TILE_H16', + 'SC_QZ0_QUAD_PER_TILE_H2', 'SC_QZ0_QUAD_PER_TILE_H3', + 'SC_QZ0_QUAD_PER_TILE_H4', 'SC_QZ0_QUAD_PER_TILE_H5', + 'SC_QZ0_QUAD_PER_TILE_H6', 'SC_QZ0_QUAD_PER_TILE_H7', + 'SC_QZ0_QUAD_PER_TILE_H8', 'SC_QZ0_QUAD_PER_TILE_H9', + 'SC_QZ0_TILE_COUNT', 'SC_QZ0_TILE_COVERED_COUNT', + 'SC_QZ0_TILE_NOT_COVERED_COUNT', 'SC_QZ1_QUAD_COUNT', + 'SC_QZ1_QUAD_PER_TILE_H0', 'SC_QZ1_QUAD_PER_TILE_H1', + 'SC_QZ1_QUAD_PER_TILE_H10', 'SC_QZ1_QUAD_PER_TILE_H11', + 'SC_QZ1_QUAD_PER_TILE_H12', 'SC_QZ1_QUAD_PER_TILE_H13', + 'SC_QZ1_QUAD_PER_TILE_H14', 'SC_QZ1_QUAD_PER_TILE_H15', + 'SC_QZ1_QUAD_PER_TILE_H16', 'SC_QZ1_QUAD_PER_TILE_H2', + 'SC_QZ1_QUAD_PER_TILE_H3', 'SC_QZ1_QUAD_PER_TILE_H4', + 'SC_QZ1_QUAD_PER_TILE_H5', 'SC_QZ1_QUAD_PER_TILE_H6', + 'SC_QZ1_QUAD_PER_TILE_H7', 'SC_QZ1_QUAD_PER_TILE_H8', + 'SC_QZ1_QUAD_PER_TILE_H9', 'SC_QZ1_TILE_COUNT', + 'SC_QZ1_TILE_COVERED_COUNT', 'SC_QZ1_TILE_NOT_COVERED_COUNT', + 'SC_QZ2_QUAD_COUNT', 'SC_QZ2_QUAD_PER_TILE_H0', + 'SC_QZ2_QUAD_PER_TILE_H1', 'SC_QZ2_QUAD_PER_TILE_H10', + 'SC_QZ2_QUAD_PER_TILE_H11', 'SC_QZ2_QUAD_PER_TILE_H12', + 'SC_QZ2_QUAD_PER_TILE_H13', 'SC_QZ2_QUAD_PER_TILE_H14', + 'SC_QZ2_QUAD_PER_TILE_H15', 'SC_QZ2_QUAD_PER_TILE_H16', + 'SC_QZ2_QUAD_PER_TILE_H2', 'SC_QZ2_QUAD_PER_TILE_H3', + 'SC_QZ2_QUAD_PER_TILE_H4', 'SC_QZ2_QUAD_PER_TILE_H5', + 'SC_QZ2_QUAD_PER_TILE_H6', 'SC_QZ2_QUAD_PER_TILE_H7', + 'SC_QZ2_QUAD_PER_TILE_H8', 'SC_QZ2_QUAD_PER_TILE_H9', + 'SC_QZ2_TILE_COUNT', 'SC_QZ2_TILE_COVERED_COUNT', + 'SC_QZ2_TILE_NOT_COVERED_COUNT', 'SC_QZ3_QUAD_COUNT', + 'SC_QZ3_QUAD_PER_TILE_H0', 'SC_QZ3_QUAD_PER_TILE_H1', + 'SC_QZ3_QUAD_PER_TILE_H10', 'SC_QZ3_QUAD_PER_TILE_H11', + 'SC_QZ3_QUAD_PER_TILE_H12', 'SC_QZ3_QUAD_PER_TILE_H13', + 'SC_QZ3_QUAD_PER_TILE_H14', 'SC_QZ3_QUAD_PER_TILE_H15', + 'SC_QZ3_QUAD_PER_TILE_H16', 'SC_QZ3_QUAD_PER_TILE_H2', + 'SC_QZ3_QUAD_PER_TILE_H3', 'SC_QZ3_QUAD_PER_TILE_H4', + 'SC_QZ3_QUAD_PER_TILE_H5', 'SC_QZ3_QUAD_PER_TILE_H6', + 'SC_QZ3_QUAD_PER_TILE_H7', 'SC_QZ3_QUAD_PER_TILE_H8', + 'SC_QZ3_QUAD_PER_TILE_H9', 'SC_QZ3_TILE_COUNT', + 'SC_QZ3_TILE_COVERED_COUNT', 'SC_QZ3_TILE_NOT_COVERED_COUNT', + 'SC_QZQP_WINDOW_VALID', 'SC_QZQP_WINDOW_VALID_BUSY', + 'SC_REG_SCLK_BUSY', 'SC_RESERVED_0', 'SC_RESERVED_1', + 'SC_RESERVED_2', 'SC_RESERVED_3', 'SC_SCB_BUSY', + 'SC_SCF_SCB_INTERFACE_BUSY', 'SC_SCISSOR_DISCARD', + 'SC_SEND_DB_VPZ', 'SC_SPIBC_FULL_FREEZE', 'SC_SPI_CREDIT_AT_MAX', + 'SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND', + 'SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND', 'SC_SPI_DEALLOC_0_0', + 'SC_SPI_DEALLOC_0_1', 'SC_SPI_DEALLOC_0_2', 'SC_SPI_DEALLOC_1_0', + 'SC_SPI_DEALLOC_1_1', 'SC_SPI_DEALLOC_1_2', 'SC_SPI_DEALLOC_2_0', + 'SC_SPI_DEALLOC_2_1', 'SC_SPI_DEALLOC_2_2', 'SC_SPI_DEALLOC_3_0', + 'SC_SPI_DEALLOC_3_1', 'SC_SPI_DEALLOC_3_2', 'SC_SPI_EVENT', + 'SC_SPI_FPOV_0', 'SC_SPI_FPOV_1', 'SC_SPI_FPOV_2', + 'SC_SPI_FPOV_3', 'SC_SPI_SEND', 'SC_SRPS_WINDOW_VALID', + 'SC_SRPS_WINDOW_VALID_BUSY', 'SC_STALLED_BY_BCI', + 'SC_STALLED_BY_DB0_TILEFIFO', 'SC_STALLED_BY_DB1_TILEFIFO', + 'SC_STALLED_BY_DB_QUAD', 'SC_STALLED_BY_DB_TILE', + 'SC_STALLED_BY_PRIMFIFO', 'SC_STALLED_BY_QUADFIFO', + 'SC_STALLED_BY_SPI', 'SC_STALLED_BY_TILEFIFO', + 'SC_STALLED_BY_TILEORDERFIFO', 'SC_STARVED_BY_DB_QUAD', + 'SC_STARVED_BY_DB_TILE', 'SC_STARVED_BY_PA', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL', + 'SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY', + 'SC_SUPERTILE_COUNT', + 'SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8', + 'SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9', + 'SC_SUPERTILE_PER_PRIM_H0', 'SC_SUPERTILE_PER_PRIM_H1', + 'SC_SUPERTILE_PER_PRIM_H10', 'SC_SUPERTILE_PER_PRIM_H11', + 'SC_SUPERTILE_PER_PRIM_H12', 'SC_SUPERTILE_PER_PRIM_H13', + 'SC_SUPERTILE_PER_PRIM_H14', 'SC_SUPERTILE_PER_PRIM_H15', + 'SC_SUPERTILE_PER_PRIM_H16', 'SC_SUPERTILE_PER_PRIM_H2', + 'SC_SUPERTILE_PER_PRIM_H3', 'SC_SUPERTILE_PER_PRIM_H4', + 'SC_SUPERTILE_PER_PRIM_H5', 'SC_SUPERTILE_PER_PRIM_H6', + 'SC_SUPERTILE_PER_PRIM_H7', 'SC_SUPERTILE_PER_PRIM_H8', + 'SC_SUPERTILE_PER_PRIM_H9', 'SC_TILE_PER_PRIM_H0', + 'SC_TILE_PER_PRIM_H1', 'SC_TILE_PER_PRIM_H10', + 'SC_TILE_PER_PRIM_H11', 'SC_TILE_PER_PRIM_H12', + 'SC_TILE_PER_PRIM_H13', 'SC_TILE_PER_PRIM_H14', + 'SC_TILE_PER_PRIM_H15', 'SC_TILE_PER_PRIM_H16', + 'SC_TILE_PER_PRIM_H2', 'SC_TILE_PER_PRIM_H3', + 'SC_TILE_PER_PRIM_H4', 'SC_TILE_PER_PRIM_H5', + 'SC_TILE_PER_PRIM_H6', 'SC_TILE_PER_PRIM_H7', + 'SC_TILE_PER_PRIM_H8', 'SC_TILE_PER_PRIM_H9', + 'SC_TILE_PER_SUPERTILE_H0', 'SC_TILE_PER_SUPERTILE_H1', + 'SC_TILE_PER_SUPERTILE_H10', 'SC_TILE_PER_SUPERTILE_H11', + 'SC_TILE_PER_SUPERTILE_H12', 'SC_TILE_PER_SUPERTILE_H13', + 'SC_TILE_PER_SUPERTILE_H14', 'SC_TILE_PER_SUPERTILE_H15', + 'SC_TILE_PER_SUPERTILE_H16', 'SC_TILE_PER_SUPERTILE_H2', + 'SC_TILE_PER_SUPERTILE_H3', 'SC_TILE_PER_SUPERTILE_H4', + 'SC_TILE_PER_SUPERTILE_H5', 'SC_TILE_PER_SUPERTILE_H6', + 'SC_TILE_PER_SUPERTILE_H7', 'SC_TILE_PER_SUPERTILE_H8', + 'SC_TILE_PER_SUPERTILE_H9', 'SC_TILE_PICKED_H1', + 'SC_TILE_PICKED_H2', 'SC_TILE_PICKED_H3', 'SC_TILE_PICKED_H4', + 'SC_TPQZ_WINDOW_VALID', 'SC_TPQZ_WINDOW_VALID_BUSY', + 'SC_TRPK_WINDOW_VALID', 'SC_TRPK_WINDOW_VALID_BUSY', 'SC_UR_1X', + 'SC_UR_2X', 'SC_UR_4X', 'SC_UR_8X', 'SC_VRS_COMB_MODE_MAX', + 'SC_VRS_COMB_MODE_MIN', 'SC_VRS_COMB_MODE_OVERRIDE', + 'SC_VRS_COMB_MODE_PASSTHRU', 'SC_VRS_COMB_MODE_SATURATE', + 'SDMA0_BASE', 'SDMA0_BASE__INST0_SEG0', 'SDMA0_BASE__INST0_SEG1', + 'SDMA0_BASE__INST0_SEG2', 'SDMA0_BASE__INST0_SEG3', + 'SDMA0_BASE__INST0_SEG4', 'SDMA0_BASE__INST1_SEG0', + 'SDMA0_BASE__INST1_SEG1', 'SDMA0_BASE__INST1_SEG2', + 'SDMA0_BASE__INST1_SEG3', 'SDMA0_BASE__INST1_SEG4', + 'SDMA0_BASE__INST2_SEG0', 'SDMA0_BASE__INST2_SEG1', + 'SDMA0_BASE__INST2_SEG2', 'SDMA0_BASE__INST2_SEG3', + 'SDMA0_BASE__INST2_SEG4', 'SDMA0_BASE__INST3_SEG0', + 'SDMA0_BASE__INST3_SEG1', 'SDMA0_BASE__INST3_SEG2', + 'SDMA0_BASE__INST3_SEG3', 'SDMA0_BASE__INST3_SEG4', + 'SDMA0_BASE__INST4_SEG0', 'SDMA0_BASE__INST4_SEG1', + 'SDMA0_BASE__INST4_SEG2', 'SDMA0_BASE__INST4_SEG3', + 'SDMA0_BASE__INST4_SEG4', 'SDMA0_BASE__INST5_SEG0', + 'SDMA0_BASE__INST5_SEG1', 'SDMA0_BASE__INST5_SEG2', + 'SDMA0_BASE__INST5_SEG3', 'SDMA0_BASE__INST5_SEG4', + 'SDMA0_BASE__INST6_SEG0', 'SDMA0_BASE__INST6_SEG1', + 'SDMA0_BASE__INST6_SEG2', 'SDMA0_BASE__INST6_SEG3', + 'SDMA0_BASE__INST6_SEG4', 'SDMA1_BASE', 'SDMA1_BASE__INST0_SEG0', + 'SDMA1_BASE__INST0_SEG1', 'SDMA1_BASE__INST0_SEG2', + 'SDMA1_BASE__INST0_SEG3', 'SDMA1_BASE__INST0_SEG4', + 'SDMA1_BASE__INST1_SEG0', 'SDMA1_BASE__INST1_SEG1', + 'SDMA1_BASE__INST1_SEG2', 'SDMA1_BASE__INST1_SEG3', + 'SDMA1_BASE__INST1_SEG4', 'SDMA1_BASE__INST2_SEG0', + 'SDMA1_BASE__INST2_SEG1', 'SDMA1_BASE__INST2_SEG2', + 'SDMA1_BASE__INST2_SEG3', 'SDMA1_BASE__INST2_SEG4', + 'SDMA1_BASE__INST3_SEG0', 'SDMA1_BASE__INST3_SEG1', + 'SDMA1_BASE__INST3_SEG2', 'SDMA1_BASE__INST3_SEG3', + 'SDMA1_BASE__INST3_SEG4', 'SDMA1_BASE__INST4_SEG0', + 'SDMA1_BASE__INST4_SEG1', 'SDMA1_BASE__INST4_SEG2', + 'SDMA1_BASE__INST4_SEG3', 'SDMA1_BASE__INST4_SEG4', + 'SDMA1_BASE__INST5_SEG0', 'SDMA1_BASE__INST5_SEG1', + 'SDMA1_BASE__INST5_SEG2', 'SDMA1_BASE__INST5_SEG3', + 'SDMA1_BASE__INST5_SEG4', 'SDMA1_BASE__INST6_SEG0', + 'SDMA1_BASE__INST6_SEG1', 'SDMA1_BASE__INST6_SEG2', + 'SDMA1_BASE__INST6_SEG3', 'SDMA1_BASE__INST6_SEG4', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset', + 'SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset', + 'SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset', + 'SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset', + 'SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_barrier_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_barrier_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_barrier_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_cpv_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_cpv_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_cpv_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_format_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_format_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_format_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_op_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_op_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_op_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_reserved_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_reserved_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_reserved_shift', + 'SDMA_AQL_PKT_HEADER_HEADER_subop_mask', + 'SDMA_AQL_PKT_HEADER_HEADER_subop_offset', + 'SDMA_AQL_PKT_HEADER_HEADER_subop_shift', 'SDMA_ATOMIC_ADD64', + 'SDMA_GCR_GL1_INV', 'SDMA_GCR_GL2_DISCARD', 'SDMA_GCR_GL2_INV', + 'SDMA_GCR_GL2_US', 'SDMA_GCR_GL2_WB', 'SDMA_GCR_GLK_INV', + 'SDMA_GCR_GLK_WB', 'SDMA_GCR_GLM_INV', 'SDMA_GCR_GLM_WB', + 'SDMA_GCR_GLV_INV', 'SDMA_GCR_RANGE_IS_PA', + 'SDMA_OP_AQL_BARRIER_OR', 'SDMA_OP_AQL_COPY', 'SDMA_OP_ATOMIC', + 'SDMA_OP_COND_EXE', 'SDMA_OP_CONST_FILL', 'SDMA_OP_COPY', + 'SDMA_OP_DUMMY_TRAP', 'SDMA_OP_FENCE', 'SDMA_OP_GCR', + 'SDMA_OP_GCR_REQ', 'SDMA_OP_GPUVM_INV', 'SDMA_OP_INDIRECT', + 'SDMA_OP_NOP', 'SDMA_OP_POLL_REGMEM', 'SDMA_OP_PRE_EXE', + 'SDMA_OP_PTEPDE', 'SDMA_OP_SEM', 'SDMA_OP_SRBM_WRITE', + 'SDMA_OP_TIMESTAMP', 'SDMA_OP_TRAP', 'SDMA_OP_WRITE', + 'SDMA_PERFMON_SEL', 'SDMA_PERFMON_SEL_CE_AFIFO_FULL', + 'SDMA_PERFMON_SEL_CE_DST_IDLE', 'SDMA_PERFMON_SEL_CE_INFO1_FULL', + 'SDMA_PERFMON_SEL_CE_INFO_FULL', 'SDMA_PERFMON_SEL_CE_IN_IDLE', + 'SDMA_PERFMON_SEL_CE_L1_WR_VLD', 'SDMA_PERFMON_SEL_CE_OUT_IDLE', + 'SDMA_PERFMON_SEL_CE_RD_STALL', 'SDMA_PERFMON_SEL_CE_RREQ_IDLE', + 'SDMA_PERFMON_SEL_CE_SPLIT_IDLE', 'SDMA_PERFMON_SEL_CE_WREQ_IDLE', + 'SDMA_PERFMON_SEL_CE_WR_IDLE', 'SDMA_PERFMON_SEL_CE_WR_STALL', + 'SDMA_PERFMON_SEL_CPF_SDMA_INVREQ', 'SDMA_PERFMON_SEL_CTX_CHANGE', + 'SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION', + 'SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERFMON_SEL_CYCLE', + 'SDMA_PERFMON_SEL_DMA_L1_RD_SEND', + 'SDMA_PERFMON_SEL_DMA_L1_WR_SEND', + 'SDMA_PERFMON_SEL_DMA_MC_RD_SEND', + 'SDMA_PERFMON_SEL_DMA_MC_WR_SEND', 'SDMA_PERFMON_SEL_DOORBELL', + 'SDMA_PERFMON_SEL_EX_IDLE', + 'SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'SDMA_PERFMON_SEL_F32_L1_WR_VLD', 'SDMA_PERFMON_SEL_GCR_RTN', + 'SDMA_PERFMON_SEL_GCR_SEND', 'SDMA_PERFMON_SEL_GFX_SELECT', + 'SDMA_PERFMON_SEL_GPUVM_INV_HIGH', + 'SDMA_PERFMON_SEL_GPUVM_INV_LOW', 'SDMA_PERFMON_SEL_IB_CMD_FULL', + 'SDMA_PERFMON_SEL_IB_CMD_IDLE', 'SDMA_PERFMON_SEL_IDLE', + 'SDMA_PERFMON_SEL_INT_IDLE', 'SDMA_PERFMON_SEL_INT_REQ_COUNT', + 'SDMA_PERFMON_SEL_INT_REQ_STALL', + 'SDMA_PERFMON_SEL_INT_RESP_ACCEPTED', + 'SDMA_PERFMON_SEL_INT_RESP_RETRY', + 'SDMA_PERFMON_SEL_L1_RDL2_IDLE', 'SDMA_PERFMON_SEL_L1_RDMC_IDLE', + 'SDMA_PERFMON_SEL_L1_RD_INV_IDLE', + 'SDMA_PERFMON_SEL_L1_WRL2_IDLE', 'SDMA_PERFMON_SEL_L1_WRMC_IDLE', + 'SDMA_PERFMON_SEL_L1_WR_INV_IDLE', + 'SDMA_PERFMON_SEL_L2_META_RET_VLD', + 'SDMA_PERFMON_SEL_MC_RD_COUNT', 'SDMA_PERFMON_SEL_MC_RD_IDLE', + 'SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE', + 'SDMA_PERFMON_SEL_MC_RD_RET_STALL', + 'SDMA_PERFMON_SEL_MC_WR_COUNT', 'SDMA_PERFMON_SEL_MC_WR_IDLE', + 'SDMA_PERFMON_SEL_META_L2_REQ_SEND', + 'SDMA_PERFMON_SEL_META_REQ_SEND', 'SDMA_PERFMON_SEL_META_RTN_VLD', + 'SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER', + 'SDMA_PERFMON_SEL_NUM_PACKET', 'SDMA_PERFMON_SEL_PAGE_SELECT', + 'SDMA_PERFMON_SEL_RB_CMD_FULL', 'SDMA_PERFMON_SEL_RB_CMD_IDLE', + 'SDMA_PERFMON_SEL_RB_EMPTY', 'SDMA_PERFMON_SEL_RB_FULL', + 'SDMA_PERFMON_SEL_RB_RPTR_WB', 'SDMA_PERFMON_SEL_RB_RPTR_WRAP', + 'SDMA_PERFMON_SEL_RB_WPTR_POLL_READ', + 'SDMA_PERFMON_SEL_RB_WPTR_WRAP', 'SDMA_PERFMON_SEL_RD_BA_RTR', + 'SDMA_PERFMON_SEL_REG_IDLE', 'SDMA_PERFMON_SEL_RLC0_SELECT', + 'SDMA_PERFMON_SEL_RLC1_SELECT', + 'SDMA_PERFMON_SEL_SDMA_CPF_INVACK', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_SEND', + 'SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND', + 'SDMA_PERFMON_SEL_SEM_IDLE', 'SDMA_PERFMON_SEL_SEM_REQ_COUNT', + 'SDMA_PERFMON_SEL_SEM_REQ_STALL', + 'SDMA_PERFMON_SEL_SEM_RESP_FAIL', + 'SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE', + 'SDMA_PERFMON_SEL_SEM_RESP_PASS', + 'SDMA_PERFMON_SEL_SRBM_REG_SEND', 'SDMA_PERFMON_SEL_TLBI_RTN', + 'SDMA_PERFMON_SEL_TLBI_SEND', + 'SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER', + 'SDMA_PERFMON_SEL_UTCL2_FREE', 'SDMA_PERFMON_SEL_UTCL2_RET_ACK', + 'SDMA_PERFMON_SEL_UTCL2_RET_XNACK', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN', + 'SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN', + 'SDMA_PERFMON_SEL_WR_BA_RTR', 'SDMA_PERF_SEL', + 'SDMA_PERF_SEL_CE_AFIFO_FULL', 'SDMA_PERF_SEL_CE_BUSY', + 'SDMA_PERF_SEL_CE_BUSY_END', 'SDMA_PERF_SEL_CE_BUSY_START', + 'SDMA_PERF_SEL_CE_CH_RDREQ_SEND', + 'SDMA_PERF_SEL_CE_CH_WRREQ_SEND', 'SDMA_PERF_SEL_CE_CH_WR_REQ', + 'SDMA_PERF_SEL_CE_CH_WR_RET', 'SDMA_PERF_SEL_CE_DST_IDLE', + 'SDMA_PERF_SEL_CE_INFO1_FULL', 'SDMA_PERF_SEL_CE_INFO_FULL', + 'SDMA_PERF_SEL_CE_IN_IDLE', 'SDMA_PERF_SEL_CE_L1_WR_VLD', + 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ', + 'SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET', 'SDMA_PERF_SEL_CE_OUT_IDLE', + 'SDMA_PERF_SEL_CE_RD_STALL', 'SDMA_PERF_SEL_CE_RREQ_IDLE', + 'SDMA_PERF_SEL_CE_SPLIT_IDLE', 'SDMA_PERF_SEL_CE_WREQ_IDLE', + 'SDMA_PERF_SEL_CE_WR_IDLE', 'SDMA_PERF_SEL_CE_WR_STALL', + 'SDMA_PERF_SEL_CGCG_FENCE', 'SDMA_PERF_SEL_CH_CE_RDRET_VALID', + 'SDMA_PERF_SEL_CH_CE_WRRET_VALID', 'SDMA_PERF_SEL_CMD_OP_END', + 'SDMA_PERF_SEL_CMD_OP_MATCH', 'SDMA_PERF_SEL_CMD_OP_START', + 'SDMA_PERF_SEL_CPF_SDMA_INVREQ', 'SDMA_PERF_SEL_CTX_CHANGE', + 'SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION', + 'SDMA_PERF_SEL_CTX_CHANGE_EXPIRED', 'SDMA_PERF_SEL_CYCLE', + 'SDMA_PERF_SEL_DMA_L1_RD_SEND', 'SDMA_PERF_SEL_DMA_L1_WR_SEND', + 'SDMA_PERF_SEL_DMA_MC_RD_SEND', 'SDMA_PERF_SEL_DMA_MC_WR_SEND', + 'SDMA_PERF_SEL_DOORBELL', 'SDMA_PERF_SEL_EX_IDLE', + 'SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE', + 'SDMA_PERF_SEL_F32_CH_WR_REQ', 'SDMA_PERF_SEL_F32_CH_WR_RET', + 'SDMA_PERF_SEL_F32_L1_WR_VLD', + 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER', + 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END', + 'SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START', + 'SDMA_PERF_SEL_GCR_RTN', 'SDMA_PERF_SEL_GCR_SEND', + 'SDMA_PERF_SEL_GFX_SELECT', 'SDMA_PERF_SEL_GPUVM_INV_HIGH', + 'SDMA_PERF_SEL_GPUVM_INV_LOW', 'SDMA_PERF_SEL_IB_CH_RD_REQ', + 'SDMA_PERF_SEL_IB_CH_RD_RET', 'SDMA_PERF_SEL_IB_CMD_FULL', + 'SDMA_PERF_SEL_IB_CMD_IDLE', 'SDMA_PERF_SEL_IDLE', + 'SDMA_PERF_SEL_INT_IDLE', 'SDMA_PERF_SEL_INT_REQ_COUNT', + 'SDMA_PERF_SEL_INT_REQ_STALL', 'SDMA_PERF_SEL_INT_RESP_ACCEPTED', + 'SDMA_PERF_SEL_INT_RESP_RETRY', 'SDMA_PERF_SEL_L1_RDL2_IDLE', + 'SDMA_PERF_SEL_L1_RDMC_IDLE', 'SDMA_PERF_SEL_L1_RD_INV_IDLE', + 'SDMA_PERF_SEL_L1_WRL2_IDLE', 'SDMA_PERF_SEL_L1_WRMC_IDLE', + 'SDMA_PERF_SEL_L1_WR_INV_IDLE', 'SDMA_PERF_SEL_L2_META_RET_VLD', + 'SDMA_PERF_SEL_MC_RD_COUNT', 'SDMA_PERF_SEL_MC_RD_IDLE', + 'SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE', + 'SDMA_PERF_SEL_MC_RD_RET_STALL', 'SDMA_PERF_SEL_MC_WR_COUNT', + 'SDMA_PERF_SEL_MC_WR_IDLE', 'SDMA_PERF_SEL_META_L2_REQ_SEND', + 'SDMA_PERF_SEL_META_REQ_SEND', 'SDMA_PERF_SEL_META_RTN_VLD', + 'SDMA_PERF_SEL_NUM_PACKET', 'SDMA_PERF_SEL_PAGE_SELECT', + 'SDMA_PERF_SEL_RB_CH_RD_REQ', 'SDMA_PERF_SEL_RB_CH_RD_RET', + 'SDMA_PERF_SEL_RB_CMD_FULL', 'SDMA_PERF_SEL_RB_CMD_IDLE', + 'SDMA_PERF_SEL_RB_EMPTY', 'SDMA_PERF_SEL_RB_FULL', + 'SDMA_PERF_SEL_RB_RPTR_WB', 'SDMA_PERF_SEL_RB_RPTR_WRAP', + 'SDMA_PERF_SEL_RB_WPTR_POLL_READ', 'SDMA_PERF_SEL_RB_WPTR_WRAP', + 'SDMA_PERF_SEL_RD_BA_RTR', 'SDMA_PERF_SEL_REG_IDLE', + 'SDMA_PERF_SEL_RLC0_SELECT', 'SDMA_PERF_SEL_RLC1_SELECT', + 'SDMA_PERF_SEL_SDMA_CPF_INVACK', + 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK', + 'SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL', + 'SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND', + 'SDMA_PERF_SEL_SDMA_UTCL2_SEND', + 'SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND', 'SDMA_PERF_SEL_SEM_IDLE', + 'SDMA_PERF_SEL_SEM_REQ_COUNT', 'SDMA_PERF_SEL_SEM_REQ_STALL', + 'SDMA_PERF_SEL_SEM_RESP_FAIL', + 'SDMA_PERF_SEL_SEM_RESP_INCOMPLETE', + 'SDMA_PERF_SEL_SEM_RESP_PASS', 'SDMA_PERF_SEL_SRBM_REG_SEND', + 'SDMA_PERF_SEL_TLBI_RTN', 'SDMA_PERF_SEL_TLBI_SEND', + 'SDMA_PERF_SEL_UTCL1_UTCL2_REQ', 'SDMA_PERF_SEL_UTCL1_UTCL2_RET', + 'SDMA_PERF_SEL_UTCL2_FREE', 'SDMA_PERF_SEL_UTCL2_RET_ACK', + 'SDMA_PERF_SEL_UTCL2_RET_XNACK', + 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ', + 'SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL', + 'SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN', + 'SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN', 'SDMA_PERF_SEL_WPTR_CH_RD_REQ', + 'SDMA_PERF_SEL_WPTR_CH_RD_RET', 'SDMA_PERF_SEL_WR_BA_RTR', + 'SDMA_PKT_ATOMIC', 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask', + 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset', + 'SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift', + 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask', + 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset', + 'SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift', + 'SDMA_PKT_ATOMIC_HEADER_atomic_op_mask', + 'SDMA_PKT_ATOMIC_HEADER_atomic_op_offset', + 'SDMA_PKT_ATOMIC_HEADER_atomic_op_shift', + 'SDMA_PKT_ATOMIC_HEADER_cache_policy_mask', + 'SDMA_PKT_ATOMIC_HEADER_cache_policy_offset', + 'SDMA_PKT_ATOMIC_HEADER_cache_policy_shift', + 'SDMA_PKT_ATOMIC_HEADER_cpv_mask', + 'SDMA_PKT_ATOMIC_HEADER_cpv_offset', + 'SDMA_PKT_ATOMIC_HEADER_cpv_shift', + 'SDMA_PKT_ATOMIC_HEADER_loop_mask', + 'SDMA_PKT_ATOMIC_HEADER_loop_offset', + 'SDMA_PKT_ATOMIC_HEADER_loop_shift', + 'SDMA_PKT_ATOMIC_HEADER_op_mask', + 'SDMA_PKT_ATOMIC_HEADER_op_offset', + 'SDMA_PKT_ATOMIC_HEADER_op_shift', + 'SDMA_PKT_ATOMIC_HEADER_tmz_mask', + 'SDMA_PKT_ATOMIC_HEADER_tmz_offset', + 'SDMA_PKT_ATOMIC_HEADER_tmz_shift', + 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask', + 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset', + 'SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift', + 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask', + 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset', + 'SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift', + 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask', + 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset', + 'SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift', + 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask', + 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset', + 'SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift', + 'SDMA_PKT_COND_EXE_HEADER_cache_policy_mask', + 'SDMA_PKT_COND_EXE_HEADER_cache_policy_offset', + 'SDMA_PKT_COND_EXE_HEADER_cache_policy_shift', + 'SDMA_PKT_COND_EXE_HEADER_cpv_mask', + 'SDMA_PKT_COND_EXE_HEADER_cpv_offset', + 'SDMA_PKT_COND_EXE_HEADER_cpv_shift', + 'SDMA_PKT_COND_EXE_HEADER_op_mask', + 'SDMA_PKT_COND_EXE_HEADER_op_offset', + 'SDMA_PKT_COND_EXE_HEADER_op_shift', + 'SDMA_PKT_COND_EXE_HEADER_sub_op_mask', + 'SDMA_PKT_COND_EXE_HEADER_sub_op_offset', + 'SDMA_PKT_COND_EXE_HEADER_sub_op_shift', + 'SDMA_PKT_COND_EXE_REFERENCE_reference_mask', + 'SDMA_PKT_COND_EXE_REFERENCE_reference_offset', + 'SDMA_PKT_COND_EXE_REFERENCE_reference_shift', + 'SDMA_PKT_CONSTANT_FILL', + 'SDMA_PKT_CONSTANT_FILL_COUNT_count_mask', + 'SDMA_PKT_CONSTANT_FILL_COUNT_count_offset', + 'SDMA_PKT_CONSTANT_FILL_COUNT_count_shift', + 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask', + 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset', + 'SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_op_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_op_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_op_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset', + 'SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset', + 'SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift', + 'SDMA_PKT_COPY_LINEAR', + 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask', + 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset', + 'SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift', + 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask', + 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset', + 'SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift', + 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask', + 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset', + 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift', + 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask', + 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset', + 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift', + 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask', + 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset', + 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift', + 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_COUNT_count_mask', + 'SDMA_PKT_COPY_LINEAR_COUNT_count_offset', + 'SDMA_PKT_COPY_LINEAR_COUNT_count_shift', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_cpv_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_cpv_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_cpv_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_op_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_op_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_op_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask', + 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset', + 'SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_LINEAR_RECT', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_STRUCT_COUNT_count_mask', + 'SDMA_PKT_COPY_STRUCT_COUNT_count_offset', + 'SDMA_PKT_COPY_STRUCT_COUNT_count_shift', + 'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask', + 'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset', + 'SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift', + 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask', + 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset', + 'SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift', + 'SDMA_PKT_COPY_STRUCT_DW_5_stride_mask', + 'SDMA_PKT_COPY_STRUCT_DW_5_stride_offset', + 'SDMA_PKT_COPY_STRUCT_DW_5_stride_shift', + 'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask', + 'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset', + 'SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift', + 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask', + 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset', + 'SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_detile_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_detile_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_detile_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_op_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_op_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_op_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask', + 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset', + 'SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset', + 'SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift', + 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask', + 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset', + 'SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift', + 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift', + 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask', + 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset', + 'SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift', + 'SDMA_PKT_COPY_T2T_BC_HEADER_op_mask', + 'SDMA_PKT_COPY_T2T_BC_HEADER_op_offset', + 'SDMA_PKT_COPY_T2T_BC_HEADER_op_shift', + 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_COPY_T2T_DW_10_dst_width_mask', + 'SDMA_PKT_COPY_T2T_DW_10_dst_width_offset', + 'SDMA_PKT_COPY_T2T_DW_10_dst_width_shift', + 'SDMA_PKT_COPY_T2T_DW_10_dst_z_mask', + 'SDMA_PKT_COPY_T2T_DW_10_dst_z_offset', + 'SDMA_PKT_COPY_T2T_DW_10_dst_z_shift', + 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask', + 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset', + 'SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift', + 'SDMA_PKT_COPY_T2T_DW_11_dst_height_mask', + 'SDMA_PKT_COPY_T2T_DW_11_dst_height_offset', + 'SDMA_PKT_COPY_T2T_DW_11_dst_height_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift', + 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask', + 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset', + 'SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift', + 'SDMA_PKT_COPY_T2T_DW_13_rect_x_mask', + 'SDMA_PKT_COPY_T2T_DW_13_rect_x_offset', + 'SDMA_PKT_COPY_T2T_DW_13_rect_x_shift', + 'SDMA_PKT_COPY_T2T_DW_13_rect_y_mask', + 'SDMA_PKT_COPY_T2T_DW_13_rect_y_offset', + 'SDMA_PKT_COPY_T2T_DW_13_rect_y_shift', + 'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask', + 'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset', + 'SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift', + 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask', + 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset', + 'SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift', + 'SDMA_PKT_COPY_T2T_DW_14_rect_z_mask', + 'SDMA_PKT_COPY_T2T_DW_14_rect_z_offset', + 'SDMA_PKT_COPY_T2T_DW_14_rect_z_shift', + 'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask', + 'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset', + 'SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift', + 'SDMA_PKT_COPY_T2T_DW_14_src_sw_mask', + 'SDMA_PKT_COPY_T2T_DW_14_src_sw_offset', + 'SDMA_PKT_COPY_T2T_DW_14_src_sw_shift', + 'SDMA_PKT_COPY_T2T_DW_3_src_x_mask', + 'SDMA_PKT_COPY_T2T_DW_3_src_x_offset', + 'SDMA_PKT_COPY_T2T_DW_3_src_x_shift', + 'SDMA_PKT_COPY_T2T_DW_3_src_y_mask', + 'SDMA_PKT_COPY_T2T_DW_3_src_y_offset', + 'SDMA_PKT_COPY_T2T_DW_3_src_y_shift', + 'SDMA_PKT_COPY_T2T_DW_4_src_width_mask', + 'SDMA_PKT_COPY_T2T_DW_4_src_width_offset', + 'SDMA_PKT_COPY_T2T_DW_4_src_width_shift', + 'SDMA_PKT_COPY_T2T_DW_4_src_z_mask', + 'SDMA_PKT_COPY_T2T_DW_4_src_z_offset', + 'SDMA_PKT_COPY_T2T_DW_4_src_z_shift', + 'SDMA_PKT_COPY_T2T_DW_5_src_depth_mask', + 'SDMA_PKT_COPY_T2T_DW_5_src_depth_offset', + 'SDMA_PKT_COPY_T2T_DW_5_src_depth_shift', + 'SDMA_PKT_COPY_T2T_DW_5_src_height_mask', + 'SDMA_PKT_COPY_T2T_DW_5_src_height_offset', + 'SDMA_PKT_COPY_T2T_DW_5_src_height_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift', + 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask', + 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset', + 'SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift', + 'SDMA_PKT_COPY_T2T_DW_9_dst_x_mask', + 'SDMA_PKT_COPY_T2T_DW_9_dst_x_offset', + 'SDMA_PKT_COPY_T2T_DW_9_dst_x_shift', + 'SDMA_PKT_COPY_T2T_DW_9_dst_y_mask', + 'SDMA_PKT_COPY_T2T_DW_9_dst_y_offset', + 'SDMA_PKT_COPY_T2T_DW_9_dst_y_shift', + 'SDMA_PKT_COPY_T2T_HEADER_cpv_mask', + 'SDMA_PKT_COPY_T2T_HEADER_cpv_offset', + 'SDMA_PKT_COPY_T2T_HEADER_cpv_shift', + 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask', + 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset', + 'SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift', + 'SDMA_PKT_COPY_T2T_HEADER_dcc_mask', + 'SDMA_PKT_COPY_T2T_HEADER_dcc_offset', + 'SDMA_PKT_COPY_T2T_HEADER_dcc_shift', + 'SDMA_PKT_COPY_T2T_HEADER_op_mask', + 'SDMA_PKT_COPY_T2T_HEADER_op_offset', + 'SDMA_PKT_COPY_T2T_HEADER_op_shift', + 'SDMA_PKT_COPY_T2T_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_T2T_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_T2T_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_T2T_HEADER_tmz_mask', + 'SDMA_PKT_COPY_T2T_HEADER_tmz_offset', + 'SDMA_PKT_COPY_T2T_HEADER_tmz_shift', + 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask', + 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset', + 'SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift', + 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask', + 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset', + 'SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift', + 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask', + 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset', + 'SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift', + 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask', + 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset', + 'SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift', + 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask', + 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset', + 'SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift', + 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask', + 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset', + 'SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift', + 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask', + 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset', + 'SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift', + 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask', + 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset', + 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift', + 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask', + 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset', + 'SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift', + 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask', + 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset', + 'SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift', + 'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask', + 'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset', + 'SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift', + 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask', + 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset', + 'SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift', + 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask', + 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset', + 'SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_BC_COUNT_count_mask', + 'SDMA_PKT_COPY_TILED_BC_COUNT_count_offset', + 'SDMA_PKT_COPY_TILED_BC_COUNT_count_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_3_width_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_3_width_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_3_width_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_4_height_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_4_height_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_4_height_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_6_x_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_6_x_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_6_x_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_6_y_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_6_y_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_6_y_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift', + 'SDMA_PKT_COPY_TILED_BC_DW_7_z_mask', + 'SDMA_PKT_COPY_TILED_BC_DW_7_z_offset', + 'SDMA_PKT_COPY_TILED_BC_DW_7_z_shift', + 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask', + 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset', + 'SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift', + 'SDMA_PKT_COPY_TILED_BC_HEADER_op_mask', + 'SDMA_PKT_COPY_TILED_BC_HEADER_op_offset', + 'SDMA_PKT_COPY_TILED_BC_HEADER_op_shift', + 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask', + 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset', + 'SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift', + 'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', + 'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', + 'SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', + 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_COUNT_count_mask', + 'SDMA_PKT_COPY_TILED_COUNT_count_offset', + 'SDMA_PKT_COPY_TILED_COUNT_count_shift', + 'SDMA_PKT_COPY_TILED_DW_3_width_mask', + 'SDMA_PKT_COPY_TILED_DW_3_width_offset', + 'SDMA_PKT_COPY_TILED_DW_3_width_shift', + 'SDMA_PKT_COPY_TILED_DW_4_depth_mask', + 'SDMA_PKT_COPY_TILED_DW_4_depth_offset', + 'SDMA_PKT_COPY_TILED_DW_4_depth_shift', + 'SDMA_PKT_COPY_TILED_DW_4_height_mask', + 'SDMA_PKT_COPY_TILED_DW_4_height_offset', + 'SDMA_PKT_COPY_TILED_DW_4_height_shift', + 'SDMA_PKT_COPY_TILED_DW_5_dimension_mask', + 'SDMA_PKT_COPY_TILED_DW_5_dimension_offset', + 'SDMA_PKT_COPY_TILED_DW_5_dimension_shift', + 'SDMA_PKT_COPY_TILED_DW_5_element_size_mask', + 'SDMA_PKT_COPY_TILED_DW_5_element_size_offset', + 'SDMA_PKT_COPY_TILED_DW_5_element_size_shift', + 'SDMA_PKT_COPY_TILED_DW_5_mip_max_mask', + 'SDMA_PKT_COPY_TILED_DW_5_mip_max_offset', + 'SDMA_PKT_COPY_TILED_DW_5_mip_max_shift', + 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask', + 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset', + 'SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift', + 'SDMA_PKT_COPY_TILED_DW_6_x_mask', + 'SDMA_PKT_COPY_TILED_DW_6_x_offset', + 'SDMA_PKT_COPY_TILED_DW_6_x_shift', + 'SDMA_PKT_COPY_TILED_DW_6_y_mask', + 'SDMA_PKT_COPY_TILED_DW_6_y_offset', + 'SDMA_PKT_COPY_TILED_DW_6_y_shift', + 'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask', + 'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset', + 'SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift', + 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask', + 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset', + 'SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift', + 'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask', + 'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset', + 'SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift', + 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask', + 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset', + 'SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift', + 'SDMA_PKT_COPY_TILED_DW_7_z_mask', + 'SDMA_PKT_COPY_TILED_DW_7_z_offset', + 'SDMA_PKT_COPY_TILED_DW_7_z_shift', + 'SDMA_PKT_COPY_TILED_HEADER_cpv_mask', + 'SDMA_PKT_COPY_TILED_HEADER_cpv_offset', + 'SDMA_PKT_COPY_TILED_HEADER_cpv_shift', + 'SDMA_PKT_COPY_TILED_HEADER_detile_mask', + 'SDMA_PKT_COPY_TILED_HEADER_detile_offset', + 'SDMA_PKT_COPY_TILED_HEADER_detile_shift', + 'SDMA_PKT_COPY_TILED_HEADER_encrypt_mask', + 'SDMA_PKT_COPY_TILED_HEADER_encrypt_offset', + 'SDMA_PKT_COPY_TILED_HEADER_encrypt_shift', + 'SDMA_PKT_COPY_TILED_HEADER_op_mask', + 'SDMA_PKT_COPY_TILED_HEADER_op_offset', + 'SDMA_PKT_COPY_TILED_HEADER_op_shift', + 'SDMA_PKT_COPY_TILED_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_TILED_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_TILED_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_TILED_HEADER_tmz_mask', + 'SDMA_PKT_COPY_TILED_HEADER_tmz_offset', + 'SDMA_PKT_COPY_TILED_HEADER_tmz_shift', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask', + 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset', + 'SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift', + 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask', + 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset', + 'SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset', + 'SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset', + 'SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift', + 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask', + 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset', + 'SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset', + 'SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift', + 'SDMA_PKT_DUMMY_TRAP_HEADER_op_mask', + 'SDMA_PKT_DUMMY_TRAP_HEADER_op_offset', + 'SDMA_PKT_DUMMY_TRAP_HEADER_op_shift', + 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask', + 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset', + 'SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift', + 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask', + 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset', + 'SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift', + 'SDMA_PKT_FENCE', 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_FENCE_DATA_data_mask', + 'SDMA_PKT_FENCE_DATA_data_offset', + 'SDMA_PKT_FENCE_DATA_data_shift', + 'SDMA_PKT_FENCE_HEADER_cpv_mask', + 'SDMA_PKT_FENCE_HEADER_cpv_offset', + 'SDMA_PKT_FENCE_HEADER_cpv_shift', + 'SDMA_PKT_FENCE_HEADER_gcc_mask', + 'SDMA_PKT_FENCE_HEADER_gcc_offset', + 'SDMA_PKT_FENCE_HEADER_gcc_shift', + 'SDMA_PKT_FENCE_HEADER_gpa_mask', + 'SDMA_PKT_FENCE_HEADER_gpa_offset', + 'SDMA_PKT_FENCE_HEADER_gpa_shift', + 'SDMA_PKT_FENCE_HEADER_l2_policy_mask', + 'SDMA_PKT_FENCE_HEADER_l2_policy_offset', + 'SDMA_PKT_FENCE_HEADER_l2_policy_shift', + 'SDMA_PKT_FENCE_HEADER_llc_policy_mask', + 'SDMA_PKT_FENCE_HEADER_llc_policy_offset', + 'SDMA_PKT_FENCE_HEADER_llc_policy_shift', + 'SDMA_PKT_FENCE_HEADER_mtype_mask', + 'SDMA_PKT_FENCE_HEADER_mtype_offset', + 'SDMA_PKT_FENCE_HEADER_mtype_shift', + 'SDMA_PKT_FENCE_HEADER_op_mask', + 'SDMA_PKT_FENCE_HEADER_op_offset', + 'SDMA_PKT_FENCE_HEADER_op_shift', + 'SDMA_PKT_FENCE_HEADER_snp_mask', + 'SDMA_PKT_FENCE_HEADER_snp_offset', + 'SDMA_PKT_FENCE_HEADER_snp_shift', + 'SDMA_PKT_FENCE_HEADER_sub_op_mask', + 'SDMA_PKT_FENCE_HEADER_sub_op_offset', + 'SDMA_PKT_FENCE_HEADER_sub_op_shift', + 'SDMA_PKT_FENCE_HEADER_sys_mask', + 'SDMA_PKT_FENCE_HEADER_sys_offset', + 'SDMA_PKT_FENCE_HEADER_sys_shift', 'SDMA_PKT_GCR', + 'SDMA_PKT_GCR_REQ_HEADER_op_mask', + 'SDMA_PKT_GCR_REQ_HEADER_op_offset', + 'SDMA_PKT_GCR_REQ_HEADER_op_shift', + 'SDMA_PKT_GCR_REQ_HEADER_sub_op_mask', + 'SDMA_PKT_GCR_REQ_HEADER_sub_op_offset', + 'SDMA_PKT_GCR_REQ_HEADER_sub_op_shift', + 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask', + 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset', + 'SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift', + 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_mask', + 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_offset', + 'SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_47_32_shift', + 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_mask', + 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_offset', + 'SDMA_PKT_GCR_REQ_PAYLOAD2_gcr_control_15_0_shift', + 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_mask', + 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_offset', + 'SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_16_shift', + 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_mask', + 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_offset', + 'SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_31_7_shift', + 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_mask', + 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_offset', + 'SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_32_shift', + 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_mask', + 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_offset', + 'SDMA_PKT_GCR_REQ_PAYLOAD4_vmid_shift', + 'SDMA_PKT_GPUVM_INV_HEADER_op_mask', + 'SDMA_PKT_GPUVM_INV_HEADER_op_offset', + 'SDMA_PKT_GPUVM_INV_HEADER_op_shift', + 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask', + 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset', + 'SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift', + 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask', + 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset', + 'SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift', + 'SDMA_PKT_HDP_FLUSH', + 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask', + 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset', + 'SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift', + 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask', + 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset', + 'SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift', + 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask', + 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset', + 'SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift', + 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask', + 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset', + 'SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift', + 'SDMA_PKT_INDIRECT_HEADER_op_mask', + 'SDMA_PKT_INDIRECT_HEADER_op_offset', + 'SDMA_PKT_INDIRECT_HEADER_op_shift', + 'SDMA_PKT_INDIRECT_HEADER_priv_mask', + 'SDMA_PKT_INDIRECT_HEADER_priv_offset', + 'SDMA_PKT_INDIRECT_HEADER_priv_shift', + 'SDMA_PKT_INDIRECT_HEADER_sub_op_mask', + 'SDMA_PKT_INDIRECT_HEADER_sub_op_offset', + 'SDMA_PKT_INDIRECT_HEADER_sub_op_shift', + 'SDMA_PKT_INDIRECT_HEADER_vmid_mask', + 'SDMA_PKT_INDIRECT_HEADER_vmid_offset', + 'SDMA_PKT_INDIRECT_HEADER_vmid_shift', + 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask', + 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset', + 'SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift', + 'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_MEM_INCR_HEADER_cpv_mask', + 'SDMA_PKT_MEM_INCR_HEADER_cpv_offset', + 'SDMA_PKT_MEM_INCR_HEADER_cpv_shift', + 'SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask', + 'SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset', + 'SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift', + 'SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask', + 'SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset', + 'SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift', + 'SDMA_PKT_MEM_INCR_HEADER_op_mask', + 'SDMA_PKT_MEM_INCR_HEADER_op_offset', + 'SDMA_PKT_MEM_INCR_HEADER_op_shift', + 'SDMA_PKT_MEM_INCR_HEADER_sub_op_mask', + 'SDMA_PKT_MEM_INCR_HEADER_sub_op_offset', + 'SDMA_PKT_MEM_INCR_HEADER_sub_op_shift', + 'SDMA_PKT_NOP_DATA0_data0_mask', + 'SDMA_PKT_NOP_DATA0_data0_offset', + 'SDMA_PKT_NOP_DATA0_data0_shift', + 'SDMA_PKT_NOP_HEADER_count_mask', + 'SDMA_PKT_NOP_HEADER_count_offset', + 'SDMA_PKT_NOP_HEADER_count_shift', 'SDMA_PKT_NOP_HEADER_op_mask', + 'SDMA_PKT_NOP_HEADER_op_offset', 'SDMA_PKT_NOP_HEADER_op_shift', + 'SDMA_PKT_NOP_HEADER_sub_op_mask', + 'SDMA_PKT_NOP_HEADER_sub_op_offset', + 'SDMA_PKT_NOP_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset', + 'SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift', + 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask', + 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset', + 'SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift', + 'SDMA_PKT_POLL_REGMEM', + 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_POLL_REGMEM_DW5_interval_mask', + 'SDMA_PKT_POLL_REGMEM_DW5_interval_offset', + 'SDMA_PKT_POLL_REGMEM_DW5_interval_shift', + 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask', + 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset', + 'SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_func_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_func_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_func_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_op_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_op_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_op_shift', + 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask', + 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset', + 'SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_REGMEM_MASK_mask_mask', + 'SDMA_PKT_POLL_REGMEM_MASK_mask_offset', + 'SDMA_PKT_POLL_REGMEM_MASK_mask_shift', + 'SDMA_PKT_POLL_REGMEM_VALUE_value_mask', + 'SDMA_PKT_POLL_REGMEM_VALUE_value_offset', + 'SDMA_PKT_POLL_REGMEM_VALUE_value_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift', + 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask', + 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset', + 'SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift', + 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask', + 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset', + 'SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift', + 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask', + 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset', + 'SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift', + 'SDMA_PKT_PRE_EXE_HEADER_op_mask', + 'SDMA_PKT_PRE_EXE_HEADER_op_offset', + 'SDMA_PKT_PRE_EXE_HEADER_op_shift', + 'SDMA_PKT_PRE_EXE_HEADER_sub_op_mask', + 'SDMA_PKT_PRE_EXE_HEADER_sub_op_offset', + 'SDMA_PKT_PRE_EXE_HEADER_sub_op_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_COPY_COUNT_count_mask', + 'SDMA_PKT_PTEPDE_COPY_COUNT_count_offset', + 'SDMA_PKT_PTEPDE_COPY_COUNT_count_shift', + 'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask', + 'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset', + 'SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift', + 'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask', + 'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset', + 'SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_mask', + 'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_offset', + 'SDMA_PKT_PTEPDE_COPY_HEADER_cpv_shift', + 'SDMA_PKT_PTEPDE_COPY_HEADER_op_mask', + 'SDMA_PKT_PTEPDE_COPY_HEADER_op_offset', + 'SDMA_PKT_PTEPDE_COPY_HEADER_op_shift', + 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_mask', + 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_offset', + 'SDMA_PKT_PTEPDE_COPY_HEADER_ptepde_op_shift', + 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask', + 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset', + 'SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift', + 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_mask', + 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_offset', + 'SDMA_PKT_PTEPDE_COPY_HEADER_tmz_shift', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset', + 'SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask', + 'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset', + 'SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_op_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_op_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_op_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset', + 'SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift', + 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask', + 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset', + 'SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift', + 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask', + 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset', + 'SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift', + 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask', + 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset', + 'SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift', + 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask', + 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset', + 'SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift', + 'SDMA_PKT_REGISTER_RMW_ADDR_addr_mask', + 'SDMA_PKT_REGISTER_RMW_ADDR_addr_offset', + 'SDMA_PKT_REGISTER_RMW_ADDR_addr_shift', + 'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask', + 'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset', + 'SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift', + 'SDMA_PKT_REGISTER_RMW_HEADER_op_mask', + 'SDMA_PKT_REGISTER_RMW_HEADER_op_offset', + 'SDMA_PKT_REGISTER_RMW_HEADER_op_shift', + 'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask', + 'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset', + 'SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift', + 'SDMA_PKT_REGISTER_RMW_MASK_mask_mask', + 'SDMA_PKT_REGISTER_RMW_MASK_mask_offset', + 'SDMA_PKT_REGISTER_RMW_MASK_mask_shift', + 'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask', + 'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset', + 'SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift', + 'SDMA_PKT_REGISTER_RMW_MISC_stride_mask', + 'SDMA_PKT_REGISTER_RMW_MISC_stride_offset', + 'SDMA_PKT_REGISTER_RMW_MISC_stride_shift', + 'SDMA_PKT_REGISTER_RMW_VALUE_value_mask', + 'SDMA_PKT_REGISTER_RMW_VALUE_value_offset', + 'SDMA_PKT_REGISTER_RMW_VALUE_value_shift', + 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask', + 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset', + 'SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift', + 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask', + 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset', + 'SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_op_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_op_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_op_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_signal_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_signal_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_signal_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift', + 'SDMA_PKT_SEMAPHORE_HEADER_write_one_mask', + 'SDMA_PKT_SEMAPHORE_HEADER_write_one_offset', + 'SDMA_PKT_SEMAPHORE_HEADER_write_one_shift', + 'SDMA_PKT_SRBM_WRITE_ADDR_addr_mask', + 'SDMA_PKT_SRBM_WRITE_ADDR_addr_offset', + 'SDMA_PKT_SRBM_WRITE_ADDR_addr_shift', + 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask', + 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset', + 'SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift', + 'SDMA_PKT_SRBM_WRITE_DATA_data_mask', + 'SDMA_PKT_SRBM_WRITE_DATA_data_offset', + 'SDMA_PKT_SRBM_WRITE_DATA_data_shift', + 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask', + 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset', + 'SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift', + 'SDMA_PKT_SRBM_WRITE_HEADER_op_mask', + 'SDMA_PKT_SRBM_WRITE_HEADER_op_offset', + 'SDMA_PKT_SRBM_WRITE_HEADER_op_shift', + 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask', + 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset', + 'SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift', 'SDMA_PKT_TIMESTAMP', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset', + 'SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset', + 'SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset', + 'SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset', + 'SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset', + 'SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift', + 'SDMA_PKT_TRAP', 'SDMA_PKT_TRAP_HEADER_op_mask', + 'SDMA_PKT_TRAP_HEADER_op_offset', 'SDMA_PKT_TRAP_HEADER_op_shift', + 'SDMA_PKT_TRAP_HEADER_sub_op_mask', + 'SDMA_PKT_TRAP_HEADER_sub_op_offset', + 'SDMA_PKT_TRAP_HEADER_sub_op_shift', + 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask', + 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset', + 'SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift', + 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask', + 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset', + 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift', + 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask', + 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset', + 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift', + 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask', + 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset', + 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift', + 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask', + 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset', + 'SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift', + 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask', + 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset', + 'SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift', + 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask', + 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset', + 'SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift', + 'SDMA_PKT_VM_INVALIDATION_HEADER_op_mask', + 'SDMA_PKT_VM_INVALIDATION_HEADER_op_offset', + 'SDMA_PKT_VM_INVALIDATION_HEADER_op_shift', + 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask', + 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset', + 'SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift', + 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask', + 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset', + 'SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift', + 'SDMA_PKT_WRITE_INCR_COUNT_count_mask', + 'SDMA_PKT_WRITE_INCR_COUNT_count_offset', + 'SDMA_PKT_WRITE_INCR_COUNT_count_shift', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask', + 'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset', + 'SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift', + 'SDMA_PKT_WRITE_INCR_HEADER_cpv_mask', + 'SDMA_PKT_WRITE_INCR_HEADER_cpv_offset', + 'SDMA_PKT_WRITE_INCR_HEADER_cpv_shift', + 'SDMA_PKT_WRITE_INCR_HEADER_op_mask', + 'SDMA_PKT_WRITE_INCR_HEADER_op_offset', + 'SDMA_PKT_WRITE_INCR_HEADER_op_shift', + 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask', + 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset', + 'SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift', + 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask', + 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset', + 'SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift', + 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask', + 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset', + 'SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift', + 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask', + 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset', + 'SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift', + 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask', + 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset', + 'SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift', + 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask', + 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset', + 'SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift', + 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask', + 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset', + 'SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift', + 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask', + 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset', + 'SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift', + 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask', + 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset', + 'SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift', + 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift', + 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask', + 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset', + 'SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift', + 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask', + 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset', + 'SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift', + 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask', + 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset', + 'SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift', + 'SDMA_PKT_WRITE_TILED_COUNT_count_mask', + 'SDMA_PKT_WRITE_TILED_COUNT_count_offset', + 'SDMA_PKT_WRITE_TILED_COUNT_count_shift', + 'SDMA_PKT_WRITE_TILED_DATA0_data0_mask', + 'SDMA_PKT_WRITE_TILED_DATA0_data0_offset', + 'SDMA_PKT_WRITE_TILED_DATA0_data0_shift', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_WRITE_TILED_DW_3_width_mask', + 'SDMA_PKT_WRITE_TILED_DW_3_width_offset', + 'SDMA_PKT_WRITE_TILED_DW_3_width_shift', + 'SDMA_PKT_WRITE_TILED_DW_4_depth_mask', + 'SDMA_PKT_WRITE_TILED_DW_4_depth_offset', + 'SDMA_PKT_WRITE_TILED_DW_4_depth_shift', + 'SDMA_PKT_WRITE_TILED_DW_4_height_mask', + 'SDMA_PKT_WRITE_TILED_DW_4_height_offset', + 'SDMA_PKT_WRITE_TILED_DW_4_height_shift', + 'SDMA_PKT_WRITE_TILED_DW_5_dimension_mask', + 'SDMA_PKT_WRITE_TILED_DW_5_dimension_offset', + 'SDMA_PKT_WRITE_TILED_DW_5_dimension_shift', + 'SDMA_PKT_WRITE_TILED_DW_5_element_size_mask', + 'SDMA_PKT_WRITE_TILED_DW_5_element_size_offset', + 'SDMA_PKT_WRITE_TILED_DW_5_element_size_shift', + 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask', + 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset', + 'SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift', + 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask', + 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset', + 'SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift', + 'SDMA_PKT_WRITE_TILED_DW_6_x_mask', + 'SDMA_PKT_WRITE_TILED_DW_6_x_offset', + 'SDMA_PKT_WRITE_TILED_DW_6_x_shift', + 'SDMA_PKT_WRITE_TILED_DW_6_y_mask', + 'SDMA_PKT_WRITE_TILED_DW_6_y_offset', + 'SDMA_PKT_WRITE_TILED_DW_6_y_shift', + 'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask', + 'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset', + 'SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift', + 'SDMA_PKT_WRITE_TILED_DW_7_sw_mask', + 'SDMA_PKT_WRITE_TILED_DW_7_sw_offset', + 'SDMA_PKT_WRITE_TILED_DW_7_sw_shift', + 'SDMA_PKT_WRITE_TILED_DW_7_z_mask', + 'SDMA_PKT_WRITE_TILED_DW_7_z_offset', + 'SDMA_PKT_WRITE_TILED_DW_7_z_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_cpv_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_cpv_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_cpv_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_op_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_op_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_op_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift', + 'SDMA_PKT_WRITE_TILED_HEADER_tmz_mask', + 'SDMA_PKT_WRITE_TILED_HEADER_tmz_offset', + 'SDMA_PKT_WRITE_TILED_HEADER_tmz_shift', + 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask', + 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset', + 'SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset', + 'SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift', + 'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask', + 'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset', + 'SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift', + 'SDMA_PKT_WRITE_UNTILED_DW_3_count_mask', + 'SDMA_PKT_WRITE_UNTILED_DW_3_count_offset', + 'SDMA_PKT_WRITE_UNTILED_DW_3_count_shift', + 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask', + 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset', + 'SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_op_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_op_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_op_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift', + 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask', + 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset', + 'SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift', + 'SDMA_SUBOP_COPY_DIRTY_PAGE', 'SDMA_SUBOP_COPY_LINEAR', + 'SDMA_SUBOP_COPY_LINEAR_BC', 'SDMA_SUBOP_COPY_LINEAR_PHY', + 'SDMA_SUBOP_COPY_LINEAR_RECT', 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND', + 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC', + 'SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE', 'SDMA_SUBOP_COPY_SOA', + 'SDMA_SUBOP_COPY_T2T_SUB_WIND', 'SDMA_SUBOP_COPY_T2T_SUB_WIND_BC', + 'SDMA_SUBOP_COPY_TILED', 'SDMA_SUBOP_COPY_TILED_BC', + 'SDMA_SUBOP_COPY_TILED_SUB_WIND', + 'SDMA_SUBOP_COPY_TILED_SUB_WIND_BC', 'SDMA_SUBOP_DATA_FILL_MULTI', + 'SDMA_SUBOP_MEM_INCR', 'SDMA_SUBOP_POLL_DBIT_WRITE_MEM', + 'SDMA_SUBOP_POLL_MEM_VERIFY', 'SDMA_SUBOP_POLL_REG_WRITE_MEM', + 'SDMA_SUBOP_PTEPDE_COPY', 'SDMA_SUBOP_PTEPDE_COPY_BACKWARDS', + 'SDMA_SUBOP_PTEPDE_GEN', 'SDMA_SUBOP_PTEPDE_RMW', + 'SDMA_SUBOP_TIMESTAMP_GET', 'SDMA_SUBOP_TIMESTAMP_GET_GLOBAL', + 'SDMA_SUBOP_TIMESTAMP_SET', 'SDMA_SUBOP_USER_GCR', + 'SDMA_SUBOP_VM_INVALIDATION', 'SDMA_SUBOP_WRITE_LINEAR', + 'SDMA_SUBOP_WRITE_TILED', 'SDMA_SUBOP_WRITE_TILED_BC', + 'SEC_GSP0_PRIORITY_HIGH', 'SEC_GSP0_PRIORITY_LOW', 'SEGMENTS_1', + 'SEGMENTS_128', 'SEGMENTS_16', 'SEGMENTS_2', 'SEGMENTS_32', + 'SEGMENTS_4', 'SEGMENTS_64', 'SEGMENTS_8', 'SEL_DTBCLK0', + 'SEL_DTBCLK1', 'SEL_REFCLK0', 'SEM_ECC_ERROR', 'SEM_PERF_SEL', + 'SEM_PERF_SEL_ACP_REQ_SIGNAL', 'SEM_PERF_SEL_ACP_REQ_WAIT', + 'SEM_PERF_SEL_ATC_INVALIDATION', 'SEM_PERF_SEL_ATC_REQ', + 'SEM_PERF_SEL_ATC_RET', 'SEM_PERF_SEL_ATC_VM_INVALIDATION', + 'SEM_PERF_SEL_ATC_XNACK', 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT', + 'SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL', + 'SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT', + 'SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT', + 'SEM_PERF_SEL_CPG_E0_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E0_REQ_WAIT', + 'SEM_PERF_SEL_CPG_E1_REQ_SIGNAL', 'SEM_PERF_SEL_CPG_E1_REQ_WAIT', + 'SEM_PERF_SEL_CYCLE', 'SEM_PERF_SEL_IDLE', + 'SEM_PERF_SEL_ISP_REQ_SIGNAL', 'SEM_PERF_SEL_ISP_REQ_WAIT', + 'SEM_PERF_SEL_MC_RD_REQ', 'SEM_PERF_SEL_MC_RD_RET', + 'SEM_PERF_SEL_MC_WR_REQ', 'SEM_PERF_SEL_MC_WR_RET', + 'SEM_PERF_SEL_SDMA0_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA0_REQ_WAIT', + 'SEM_PERF_SEL_SDMA1_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA1_REQ_WAIT', + 'SEM_PERF_SEL_SDMA2_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA2_REQ_WAIT', + 'SEM_PERF_SEL_SDMA3_REQ_SIGNAL', 'SEM_PERF_SEL_SDMA3_REQ_WAIT', + 'SEM_PERF_SEL_UVD1_REQ_SIGNAL', 'SEM_PERF_SEL_UVD1_REQ_WAIT', + 'SEM_PERF_SEL_UVD_REQ_SIGNAL', 'SEM_PERF_SEL_UVD_REQ_WAIT', + 'SEM_PERF_SEL_VCE0_REQ_SIGNAL', 'SEM_PERF_SEL_VCE0_REQ_WAIT', + 'SEM_PERF_SEL_VCE1_REQ_SIGNAL', 'SEM_PERF_SEL_VCE1_REQ_WAIT', + 'SEM_PERF_SEL_VP8_REQ_SIGNAL', 'SEM_PERF_SEL_VP8_REQ_WAIT', + 'SEM_RESP_FAILED', 'SEM_RESP_PASSED', 'SEM_TRANS_ERROR', + 'SEND_AT_EARLIEST_TIME', 'SEND_AT_LINK_NUMBER', + 'SEND_NORMAL_PACKET', 'SEND_PPS_PACKET', 'SET_SMU_MSG_INTR', + 'SH_MEM_ADDRESS_MODE', 'SH_MEM_ADDRESS_MODE_32', + 'SH_MEM_ADDRESS_MODE_64', 'SH_MEM_ALIGNMENT_MODE', + 'SH_MEM_ALIGNMENT_MODE_DWORD', + 'SH_MEM_ALIGNMENT_MODE_DWORD_STRICT', + 'SH_MEM_ALIGNMENT_MODE_STRICT', 'SH_MEM_ALIGNMENT_MODE_UNALIGNED', + 'SIGNED', 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE', + 'SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START', + 'SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_SA_SDST_START', + 'SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_SDST_START', + 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_SSRC_START', + 'SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_VCC_START', + 'SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VA_VDST_START', + 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE', + 'SIMM16_WAITCNT_DEPCTR_VM_VSRC_START', + 'SIMM16_WAITCNT_EXP_CNT_SIZE', 'SIMM16_WAITCNT_EXP_CNT_START', + 'SIMM16_WAITCNT_LGKM_CNT_SIZE', 'SIMM16_WAITCNT_LGKM_CNT_START', + 'SIMM16_WAITCNT_VM_CNT_SIZE', 'SIMM16_WAITCNT_VM_CNT_START', + 'SIMM16_WAIT_EVENT_EXP_RDY_SIZE', + 'SIMM16_WAIT_EVENT_EXP_RDY_START', 'SIZE_16K', 'SIZE_8K', + 'SLVERR', 'SMUIO_BASE', 'SMUIO_BASE__INST0_SEG0', + 'SMUIO_BASE__INST0_SEG1', 'SMUIO_BASE__INST0_SEG2', + 'SMUIO_BASE__INST0_SEG3', 'SMUIO_BASE__INST0_SEG4', + 'SMUIO_BASE__INST1_SEG0', 'SMUIO_BASE__INST1_SEG1', + 'SMUIO_BASE__INST1_SEG2', 'SMUIO_BASE__INST1_SEG3', + 'SMUIO_BASE__INST1_SEG4', 'SMUIO_BASE__INST2_SEG0', + 'SMUIO_BASE__INST2_SEG1', 'SMUIO_BASE__INST2_SEG2', + 'SMUIO_BASE__INST2_SEG3', 'SMUIO_BASE__INST2_SEG4', + 'SMUIO_BASE__INST3_SEG0', 'SMUIO_BASE__INST3_SEG1', + 'SMUIO_BASE__INST3_SEG2', 'SMUIO_BASE__INST3_SEG3', + 'SMUIO_BASE__INST3_SEG4', 'SMUIO_BASE__INST4_SEG0', + 'SMUIO_BASE__INST4_SEG1', 'SMUIO_BASE__INST4_SEG2', + 'SMUIO_BASE__INST4_SEG3', 'SMUIO_BASE__INST4_SEG4', + 'SMUIO_BASE__INST5_SEG0', 'SMUIO_BASE__INST5_SEG1', + 'SMUIO_BASE__INST5_SEG2', 'SMUIO_BASE__INST5_SEG3', + 'SMUIO_BASE__INST5_SEG4', 'SMUIO_BASE__INST6_SEG0', + 'SMUIO_BASE__INST6_SEG1', 'SMUIO_BASE__INST6_SEG2', + 'SMUIO_BASE__INST6_SEG3', 'SMUIO_BASE__INST6_SEG4', 'SMU_INTR', + 'SMU_INTR_STATUS_CLEAR', 'SMU_INTR_STATUS_NOOP', + 'SMU_MSG_INTR_NOOP', 'SM_MODE_RESERVED', 'SOFT_RESET', + 'SOFT_RESET_0', 'SOFT_RESET_1', 'SO_VGTSTREAMOUT_FLUSH', + 'SPI_FOG_EXP', 'SPI_FOG_EXP2', 'SPI_FOG_LINEAR', 'SPI_FOG_MODE', + 'SPI_FOG_NONE', 'SPI_LB_WAVES_RSVD', 'SPI_LB_WAVES_SELECT', + 'SPI_PERFCNT_SEL', 'SPI_PERF_BUSY', 'SPI_PERF_CSGN_BUSY', + 'SPI_PERF_CSGN_CRAWLER_STALL', 'SPI_PERF_CSGN_EVENT_WAVE', + 'SPI_PERF_CSGN_NUM_THREADGROUPS', 'SPI_PERF_CSGN_PWS_STALL', + 'SPI_PERF_CSGN_WAVE', 'SPI_PERF_CSGN_WINDOW_VALID', + 'SPI_PERF_CSN_BUSY', 'SPI_PERF_CSN_CRAWLER_STALL', + 'SPI_PERF_CSN_EVENT_WAVE', 'SPI_PERF_CSN_NUM_THREADGROUPS', + 'SPI_PERF_CSN_WAVE', 'SPI_PERF_CSN_WINDOW_VALID', + 'SPI_PERF_EXPORT_DB0_STALL', 'SPI_PERF_EXPORT_DB1_STALL', + 'SPI_PERF_EXPORT_DB2_STALL', 'SPI_PERF_EXPORT_DB3_STALL', + 'SPI_PERF_EXPORT_DB4_STALL', 'SPI_PERF_EXPORT_DB5_STALL', + 'SPI_PERF_EXPORT_DB6_STALL', 'SPI_PERF_EXPORT_DB7_STALL', + 'SPI_PERF_EXPORT_SCB0_STALL', 'SPI_PERF_EXPORT_SCB1_STALL', + 'SPI_PERF_EXPORT_SCB2_STALL', 'SPI_PERF_EXPORT_SCB3_STALL', + 'SPI_PERF_EXP_ARB_COL_CNT', 'SPI_PERF_EXP_ARB_GDS_CNT', + 'SPI_PERF_EXP_ARB_IDX_CNT', 'SPI_PERF_EXP_ARB_POS_CNT', + 'SPI_PERF_EXP_THROT_CAUSALITY_DETECTED', + 'SPI_PERF_EXP_THROT_DOWNSTEP', 'SPI_PERF_EXP_THROT_UPSTEP', + 'SPI_PERF_EXP_WITH_CONFLICT', 'SPI_PERF_EXP_WITH_CONFLICT_CLEAR', + 'SPI_PERF_GS_BUSY', 'SPI_PERF_GS_CRAWLER_STALL', + 'SPI_PERF_GS_EVENT_WAVE', 'SPI_PERF_GS_EXP_DONE', + 'SPI_PERF_GS_FIRST_SUBGRP', 'SPI_PERF_GS_HS_DEALLOC', + 'SPI_PERF_GS_INDX0_STALL', 'SPI_PERF_GS_INDX1_STALL', + 'SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT', + 'SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC', + 'SPI_PERF_GS_NGG_STALL_MSG_VAL', 'SPI_PERF_GS_PERS_UPD_FULL0', + 'SPI_PERF_GS_PERS_UPD_FULL1', 'SPI_PERF_GS_POS0_STALL', + 'SPI_PERF_GS_POS1_STALL', 'SPI_PERF_GS_PWS_STALL', + 'SPI_PERF_GS_WAVE', 'SPI_PERF_GS_WINDOW_VALID', + 'SPI_PERF_HS_BUSY', 'SPI_PERF_HS_CRAWLER_STALL', + 'SPI_PERF_HS_EVENT_WAVE', 'SPI_PERF_HS_FIRST_WAVE', + 'SPI_PERF_HS_OFFCHIP_LDS_STALL', 'SPI_PERF_HS_PERS_UPD_FULL0', + 'SPI_PERF_HS_PERS_UPD_FULL1', 'SPI_PERF_HS_PWS_STALL', + 'SPI_PERF_HS_WAVE', 'SPI_PERF_HS_WINDOW_VALID', + 'SPI_PERF_NUM_EXPGRANT_EXPORTS', + 'SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS', + 'SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS', + 'SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS', + 'SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS', + 'SPI_PERF_NUM_POS_SA0SQ0_EXPORTS', + 'SPI_PERF_NUM_POS_SA0SQ1_EXPORTS', + 'SPI_PERF_NUM_POS_SA1SQ0_EXPORTS', + 'SPI_PERF_NUM_POS_SA1SQ1_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS', + 'SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS', + 'SPI_PERF_PIX_ALLOC_PEND_CNT', 'SPI_PERF_PS0_2_WAVE_GROUPS', + 'SPI_PERF_PS0_ACTIVE', 'SPI_PERF_PS0_BUSY', + 'SPI_PERF_PS0_CRAWLER_STALL', 'SPI_PERF_PS0_DEALLOC', + 'SPI_PERF_PS0_EVENT_WAVE', 'SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT', + 'SPI_PERF_PS0_OPT_WAVE', 'SPI_PERF_PS0_PRIM_BIN0', + 'SPI_PERF_PS0_PRIM_BIN1', 'SPI_PERF_PS0_WAVE', + 'SPI_PERF_PS0_WAVEID_STARVED', + 'SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS0_WINDOW_VALID', + 'SPI_PERF_PS1_2_WAVE_GROUPS', 'SPI_PERF_PS1_ACTIVE', + 'SPI_PERF_PS1_BUSY', 'SPI_PERF_PS1_CRAWLER_STALL', + 'SPI_PERF_PS1_DEALLOC', 'SPI_PERF_PS1_EVENT_WAVE', + 'SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS1_OPT_WAVE', + 'SPI_PERF_PS1_PRIM_BIN0', 'SPI_PERF_PS1_PRIM_BIN1', + 'SPI_PERF_PS1_WAVE', 'SPI_PERF_PS1_WAVEID_STARVED', + 'SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS1_WINDOW_VALID', + 'SPI_PERF_PS2_2_WAVE_GROUPS', 'SPI_PERF_PS2_ACTIVE', + 'SPI_PERF_PS2_BUSY', 'SPI_PERF_PS2_CRAWLER_STALL', + 'SPI_PERF_PS2_DEALLOC', 'SPI_PERF_PS2_EVENT_WAVE', + 'SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS2_OPT_WAVE', + 'SPI_PERF_PS2_PRIM_BIN0', 'SPI_PERF_PS2_PRIM_BIN1', + 'SPI_PERF_PS2_WAVE', 'SPI_PERF_PS2_WAVEID_STARVED', + 'SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS2_WINDOW_VALID', + 'SPI_PERF_PS3_2_WAVE_GROUPS', 'SPI_PERF_PS3_ACTIVE', + 'SPI_PERF_PS3_BUSY', 'SPI_PERF_PS3_CRAWLER_STALL', + 'SPI_PERF_PS3_DEALLOC', 'SPI_PERF_PS3_EVENT_WAVE', + 'SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT', 'SPI_PERF_PS3_OPT_WAVE', + 'SPI_PERF_PS3_PRIM_BIN0', 'SPI_PERF_PS3_PRIM_BIN1', + 'SPI_PERF_PS3_WAVE', 'SPI_PERF_PS3_WAVEID_STARVED', + 'SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY', + 'SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS', 'SPI_PERF_PS3_WINDOW_VALID', + 'SPI_PERF_PS_EXP_ALLOC', 'SPI_PERF_PS_EXP_ARB_CONFLICT', + 'SPI_PERF_PS_EXP_DONE', 'SPI_PERF_PS_PERS_UPD_FULL0', + 'SPI_PERF_PS_PERS_UPD_FULL1', 'SPI_PERF_PS_PWS_STALL', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM0_SIMD_FULL_PS', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM1_SIMD_FULL_PS', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM2_SIMD_FULL_PS', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_GS', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_HS', + 'SPI_PERF_RA_ACCUM3_SIMD_FULL_PS', 'SPI_PERF_RA_BAR_CU_FULL_CSG', + 'SPI_PERF_RA_BAR_CU_FULL_CSN', 'SPI_PERF_RA_BAR_CU_FULL_HS', + 'SPI_PERF_RA_BULKY_CU_FULL_CSG', 'SPI_PERF_RA_BULKY_CU_FULL_CSN', + 'SPI_PERF_RA_CSC_UNDER_TUNNEL', 'SPI_PERF_RA_CSG_LOCK', + 'SPI_PERF_RA_CSN_LOCK', 'SPI_PERF_RA_GFX_UNDER_TUNNEL', + 'SPI_PERF_RA_GS_LOCK', 'SPI_PERF_RA_HS_LOCK', + 'SPI_PERF_RA_LDS_CU_FULL_CSG', 'SPI_PERF_RA_LDS_CU_FULL_CSN', + 'SPI_PERF_RA_LDS_CU_FULL_GS', 'SPI_PERF_RA_LDS_CU_FULL_HS', + 'SPI_PERF_RA_LDS_CU_FULL_PS', 'SPI_PERF_RA_PIPE_REQ_BIN2', + 'SPI_PERF_RA_PRE_ALLOC_STALL', 'SPI_PERF_RA_REQ_NO_ALLOC', + 'SPI_PERF_RA_REQ_NO_ALLOC_CSG', 'SPI_PERF_RA_REQ_NO_ALLOC_CSN', + 'SPI_PERF_RA_REQ_NO_ALLOC_GS', 'SPI_PERF_RA_REQ_NO_ALLOC_HS', + 'SPI_PERF_RA_REQ_NO_ALLOC_PS', 'SPI_PERF_RA_RES_STALL_CSG', + 'SPI_PERF_RA_RES_STALL_CSN', 'SPI_PERF_RA_RES_STALL_GS', + 'SPI_PERF_RA_RES_STALL_HS', 'SPI_PERF_RA_RES_STALL_PS', + 'SPI_PERF_RA_RSV_UPD', 'SPI_PERF_RA_TASK_REQ_BIN3', + 'SPI_PERF_RA_TGLIM_CU_FULL_CSG', 'SPI_PERF_RA_TGLIM_CU_FULL_CSN', + 'SPI_PERF_RA_TMP_STALL_CSG', 'SPI_PERF_RA_TMP_STALL_CSN', + 'SPI_PERF_RA_TMP_STALL_GS', 'SPI_PERF_RA_TMP_STALL_HS', + 'SPI_PERF_RA_TMP_STALL_PS', 'SPI_PERF_RA_VGPR_SIMD_FULL_CSG', + 'SPI_PERF_RA_VGPR_SIMD_FULL_CSN', 'SPI_PERF_RA_VGPR_SIMD_FULL_GS', + 'SPI_PERF_RA_VGPR_SIMD_FULL_HS', 'SPI_PERF_RA_VGPR_SIMD_FULL_PS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSG', + 'SPI_PERF_RA_WAVE_SIMD_FULL_CSN', 'SPI_PERF_RA_WAVE_SIMD_FULL_GS', + 'SPI_PERF_RA_WAVE_SIMD_FULL_HS', 'SPI_PERF_RA_WAVE_SIMD_FULL_PS', + 'SPI_PERF_RA_WR_CTL_FULL', 'SPI_PERF_RA_WVALLOC_STALL', + 'SPI_PERF_RA_WVLIM_STALL_CSG', 'SPI_PERF_RA_WVLIM_STALL_CSN', + 'SPI_PERF_RA_WVLIM_STALL_GS', 'SPI_PERF_RA_WVLIM_STALL_HS', + 'SPI_PERF_RA_WVLIM_STALL_PS', 'SPI_PERF_SWC_CSGN_WR', + 'SPI_PERF_SWC_CSN_WR', 'SPI_PERF_SWC_GS_WR', 'SPI_PERF_SWC_HS_WR', + 'SPI_PERF_SWC_PS_WR', 'SPI_PERF_VWC_CSGN_WR', + 'SPI_PERF_VWC_CSN_WR', 'SPI_PERF_VWC_ES_WR', 'SPI_PERF_VWC_GS_WR', + 'SPI_PERF_VWC_HS_WR', 'SPI_PERF_VWC_LS_WR', 'SPI_PERF_VWC_PS_WR', + 'SPI_PNT_SPRITE_OVERRIDE', 'SPI_PNT_SPRITE_SEL_0', + 'SPI_PNT_SPRITE_SEL_1', 'SPI_PNT_SPRITE_SEL_NONE', + 'SPI_PNT_SPRITE_SEL_S', 'SPI_PNT_SPRITE_SEL_T', + 'SPI_PS_LDS_GROUP_1', 'SPI_PS_LDS_GROUP_2', 'SPI_PS_LDS_GROUP_4', + 'SPI_PS_LDS_GROUP_SIZE', 'SPI_SAMPLE_CNTL', 'SPI_SHADER_1COMP', + 'SPI_SHADER_2COMP', 'SPI_SHADER_32_ABGR', 'SPI_SHADER_32_AR', + 'SPI_SHADER_32_GR', 'SPI_SHADER_32_R', 'SPI_SHADER_4COMP', + 'SPI_SHADER_4COMPRESS', 'SPI_SHADER_EX_FORMAT', + 'SPI_SHADER_FORMAT', 'SPI_SHADER_FP16_ABGR', 'SPI_SHADER_NONE', + 'SPI_SHADER_SINT16_ABGR', 'SPI_SHADER_SNORM16_ABGR', + 'SPI_SHADER_UINT16_ABGR', 'SPI_SHADER_UNORM16_ABGR', + 'SPI_SHADER_ZERO', 'SPM_PERFMON_STATE', 'SPRITE_EN', + 'SP_PERF_SEL_DST_BUF_ALLOC_STALL', + 'SP_PERF_SEL_DST_BUF_EVEN_DIRTY', 'SP_PERF_SEL_DST_BUF_ODD_DIRTY', + 'SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI', + 'SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS', 'SP_PERF_SEL_DUMMY_LAST', + 'SP_PERF_SEL_SRC_CACHE_HIT_B0', 'SP_PERF_SEL_SRC_CACHE_HIT_B1', + 'SP_PERF_SEL_SRC_CACHE_HIT_B2', 'SP_PERF_SEL_SRC_CACHE_HIT_B3', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B0', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B1', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B2', + 'SP_PERF_SEL_SRC_CACHE_PROBE_B3', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2', + 'SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2', + 'SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2', + 'SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3', + 'SP_PERF_SEL_VALU_COEXEC_WITH_TRANS', + 'SP_PERF_SEL_VALU_EXEC_MASK_CHANGE', + 'SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY', + 'SP_PERF_SEL_VALU_OPERAND', + 'SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF', + 'SP_PERF_SEL_VALU_PENDING_QUEUE_STALL', + 'SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL', 'SP_PERF_SEL_VALU_STALL', + 'SP_PERF_SEL_VALU_STALL_DST_STALL', + 'SP_PERF_SEL_VALU_STALL_SDST_FWD', + 'SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY', + 'SP_PERF_SEL_VALU_STALL_VDST_FWD', + 'SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY', + 'SP_PERF_SEL_VALU_VGPR_OPERAND', 'SP_PERF_SEL_VGPR_EXP_RD', + 'SP_PERF_SEL_VGPR_RD', 'SP_PERF_SEL_VGPR_SPI_WR', + 'SP_PERF_SEL_VGPR_TDLDS_DATA_WR', 'SP_PERF_SEL_VGPR_VMEM_RD', + 'SP_PERF_SEL_VGPR_WR', 'SQC_PERF_SEL_DCACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_DCACHE_CACHE_STALLED', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT', + 'SQC_PERF_SEL_DCACHE_FLAT_REQ', 'SQC_PERF_SEL_DCACHE_GCR', + 'SQC_PERF_SEL_DCACHE_GCR_HITS', + 'SQC_PERF_SEL_DCACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_DCACHE_HITS', + 'SQC_PERF_SEL_DCACHE_HIT_LRU_READ', + 'SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_DCACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_DCACHE_INVAL_INST', 'SQC_PERF_SEL_DCACHE_MISSES', + 'SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_DCACHE_REQ', + 'SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE', + 'SQC_PERF_SEL_DCACHE_REQ_READ_1', + 'SQC_PERF_SEL_DCACHE_REQ_READ_16', + 'SQC_PERF_SEL_DCACHE_REQ_READ_2', + 'SQC_PERF_SEL_DCACHE_REQ_READ_4', + 'SQC_PERF_SEL_DCACHE_REQ_READ_8', + 'SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL', + 'SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_DUMMY_LAST', 'SQC_PERF_SEL_ICACHE_BUSY_CYCLES', + 'SQC_PERF_SEL_ICACHE_CACHE_STALLED', + 'SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX', + 'SQC_PERF_SEL_ICACHE_GCR', 'SQC_PERF_SEL_ICACHE_GCR_HITS', + 'SQC_PERF_SEL_ICACHE_GCR_INVALIDATE', 'SQC_PERF_SEL_ICACHE_HITS', + 'SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB', + 'SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB', + 'SQC_PERF_SEL_ICACHE_INVAL_ASYNC', + 'SQC_PERF_SEL_ICACHE_INVAL_INST', 'SQC_PERF_SEL_ICACHE_MISSES', + 'SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE', 'SQC_PERF_SEL_ICACHE_REQ', + 'SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT', + 'SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL', + 'SQC_PERF_SEL_LDS_ADDR_ACTIVE', 'SQC_PERF_SEL_LDS_ADDR_CONFLICT', + 'SQC_PERF_SEL_LDS_ADDR_STALL', 'SQC_PERF_SEL_LDS_ATOMIC_RETURN', + 'SQC_PERF_SEL_LDS_BANK_CONFLICT', + 'SQC_PERF_SEL_LDS_FP_ADD_CYCLES', 'SQC_PERF_SEL_LDS_IDX_ACTIVE', + 'SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL', + 'SQC_PERF_SEL_LDS_MEM_VIOLATIONS', + 'SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD', + 'SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD', + 'SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL', + 'SQC_PERF_SEL_LDS_UNALIGNED_STALL', 'SQC_PERF_SEL_LDS_VGPR_BUSY', + 'SQC_PERF_SEL_SQ_DCACHE_REQS', 'SQC_PERF_SEL_TC_DATA_READ_REQ', + 'SQC_PERF_SEL_TC_INFLIGHT_LEVEL', 'SQC_PERF_SEL_TC_INST_REQ', + 'SQC_PERF_SEL_TC_REQ', 'SQC_PERF_SEL_TC_STALL', + 'SQC_PERF_SEL_TC_STARVE', 'SQC_PERF_SEL_TD_VGPR_BUSY', + 'SQDEC_BEGIN', 'SQDEC_END', 'SQGFXUDEC_BEGIN', 'SQGFXUDEC_END', + 'SQG_PERF_SEL', 'SQG_PERF_SEL_ACCUM_PREV', + 'SQG_PERF_SEL_BUSY_CYCLES', 'SQG_PERF_SEL_CYCLES', + 'SQG_PERF_SEL_DUMMY_LAST', 'SQG_PERF_SEL_EVENTS', + 'SQG_PERF_SEL_EXP_BUS0_BUSY', 'SQG_PERF_SEL_EXP_BUS1_BUSY', + 'SQG_PERF_SEL_EXP_REQ0_BUS_BUSY', + 'SQG_PERF_SEL_EXP_REQ1_BUS_BUSY', 'SQG_PERF_SEL_ITEMS', + 'SQG_PERF_SEL_LEVEL_WAVES', 'SQG_PERF_SEL_MSG', + 'SQG_PERF_SEL_MSG_BUS_BUSY', 'SQG_PERF_SEL_MSG_INTERRUPT', + 'SQG_PERF_SEL_NONE', 'SQG_PERF_SEL_PS_QUADS', + 'SQG_PERF_SEL_TTRACE_INFLIGHT_REQS', + 'SQG_PERF_SEL_TTRACE_LOST_PACKETS', 'SQG_PERF_SEL_TTRACE_REQS', + 'SQG_PERF_SEL_TTRACE_STALL', 'SQG_PERF_SEL_WAVE32_ITEMS', + 'SQG_PERF_SEL_WAVE64_ITEMS', 'SQG_PERF_SEL_WAVES', + 'SQG_PERF_SEL_WAVES_32', 'SQG_PERF_SEL_WAVES_64', + 'SQG_PERF_SEL_WAVES_EQ_32', 'SQG_PERF_SEL_WAVES_EQ_64', + 'SQG_PERF_SEL_WAVES_INITIAL_PREFETCH', 'SQG_PERF_SEL_WAVES_LT_16', + 'SQG_PERF_SEL_WAVES_LT_32', 'SQG_PERF_SEL_WAVES_LT_48', + 'SQG_PERF_SEL_WAVES_LT_64', 'SQG_PERF_SEL_WAVES_RESTORED', + 'SQG_PERF_SEL_WAVES_SAVED', 'SQG_PERF_SEL_WAVE_CYCLES', + 'SQIND_GLOBAL_REGS_OFFSET', 'SQIND_GLOBAL_REGS_SIZE', + 'SQIND_LOCAL_REGS_OFFSET', 'SQIND_LOCAL_REGS_SIZE', + 'SQIND_WAVE_HWREGS_OFFSET', 'SQIND_WAVE_HWREGS_SIZE', + 'SQIND_WAVE_SGPRS_OFFSET', 'SQIND_WAVE_SGPRS_SIZE', + 'SQIND_WAVE_VGPRS_OFFSET', 'SQIND_WAVE_VGPRS_SIZE', + 'SQPERFDDEC_BEGIN', 'SQPERFDDEC_END', 'SQPERFSDEC_BEGIN', + 'SQPERFSDEC_END', 'SQPWRDEC_BEGIN', 'SQPWRDEC_END', + 'SQ_CAC_POWER_ALU_BUSY', 'SQ_CAC_POWER_GPR_RD', + 'SQ_CAC_POWER_GPR_WR', 'SQ_CAC_POWER_LDS_BUSY', + 'SQ_CAC_POWER_SEL', 'SQ_CAC_POWER_TEX_BUSY', 'SQ_CAC_POWER_VALU', + 'SQ_CAC_POWER_VALU0', 'SQ_CAC_POWER_VALU1', 'SQ_CAC_POWER_VALU2', + 'SQ_DISPATCHER_GFX_CNT_PER_RING', 'SQ_DISPATCHER_GFX_MIN', + 'SQ_EDC_FUE_CNTL_LDS', 'SQ_EDC_FUE_CNTL_SIMD0', + 'SQ_EDC_FUE_CNTL_SIMD1', 'SQ_EDC_FUE_CNTL_SIMD2', + 'SQ_EDC_FUE_CNTL_SIMD3', 'SQ_EDC_FUE_CNTL_SQ', + 'SQ_EDC_FUE_CNTL_TA', 'SQ_EDC_FUE_CNTL_TCP', 'SQ_EDC_FUE_CNTL_TD', + 'SQ_EDC_INFO_SOURCE', 'SQ_EDC_INFO_SOURCE_GDS', + 'SQ_EDC_INFO_SOURCE_INST', 'SQ_EDC_INFO_SOURCE_INVALID', + 'SQ_EDC_INFO_SOURCE_LDS', 'SQ_EDC_INFO_SOURCE_SGPR', + 'SQ_EDC_INFO_SOURCE_TA', 'SQ_EDC_INFO_SOURCE_VGPR', + 'SQ_EX_MODE_EXCP_ADDR_WATCH0', 'SQ_EX_MODE_EXCP_DIV0', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH1', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH2', + 'SQ_EX_MODE_EXCP_HI_ADDR_WATCH3', 'SQ_EX_MODE_EXCP_INEXACT', + 'SQ_EX_MODE_EXCP_INPUT_DENORM', 'SQ_EX_MODE_EXCP_INT_DIV0', + 'SQ_EX_MODE_EXCP_INVALID', 'SQ_EX_MODE_EXCP_MEM_VIOL', + 'SQ_EX_MODE_EXCP_OVERFLOW', 'SQ_EX_MODE_EXCP_UNDERFLOW', + 'SQ_EX_MODE_EXCP_VALU_BASE', 'SQ_EX_MODE_EXCP_VALU_SIZE', + 'SQ_GFXDEC_BEGIN', 'SQ_GFXDEC_END', 'SQ_GFXDEC_STATE_ID_SHIFT', + 'SQ_IBUF_IB_DRET', 'SQ_IBUF_IB_EMPTY_WAIT_DRET', + 'SQ_IBUF_IB_EMPTY_WAIT_GNT', 'SQ_IBUF_IB_IDLE', + 'SQ_IBUF_IB_INI_WAIT_DRET', 'SQ_IBUF_IB_INI_WAIT_GNT', + 'SQ_IBUF_IB_LE_4DW', 'SQ_IBUF_IB_WAIT_DRET', 'SQ_IBUF_ST', + 'SQ_IMG_FILTER_MODE_BLEND', 'SQ_IMG_FILTER_MODE_MAX', + 'SQ_IMG_FILTER_MODE_MIN', 'SQ_IMG_FILTER_TYPE', 'SQ_IND_CMD_CMD', + 'SQ_IND_CMD_CMD_KILL', 'SQ_IND_CMD_CMD_NULL', + 'SQ_IND_CMD_CMD_SAVECTX', 'SQ_IND_CMD_CMD_SETFATALHALT', + 'SQ_IND_CMD_CMD_SETHALT', 'SQ_IND_CMD_CMD_SET_SPI_PRIO', + 'SQ_IND_CMD_CMD_SINGLE_STEP', 'SQ_IND_CMD_CMD_TRAP', + 'SQ_IND_CMD_CMD_TRAP_AFTER_INST', 'SQ_IND_CMD_MODE', + 'SQ_IND_CMD_MODE_BROADCAST', 'SQ_IND_CMD_MODE_BROADCAST_ME', + 'SQ_IND_CMD_MODE_BROADCAST_PIPE', + 'SQ_IND_CMD_MODE_BROADCAST_QUEUE', 'SQ_IND_CMD_MODE_SINGLE', + 'SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_INST_SKIP_AV', + 'SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV', + 'SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT', 'SQ_INST_STR_IB_WAVE_NORML', + 'SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT', 'SQ_INST_STR_ST', + 'SQ_INST_TYPE', 'SQ_INST_TYPE_BARRIER', + 'SQ_INST_TYPE_BRANCH_NOT_TAKEN', 'SQ_INST_TYPE_BRANCH_TAKEN', + 'SQ_INST_TYPE_EXP', 'SQ_INST_TYPE_JUMP', 'SQ_INST_TYPE_LDS', + 'SQ_INST_TYPE_LDS_DIRECT', 'SQ_INST_TYPE_MSG', + 'SQ_INST_TYPE_NONE', 'SQ_INST_TYPE_OTHER', 'SQ_INST_TYPE_SCALAR', + 'SQ_INST_TYPE_TEX', 'SQ_INST_TYPE_VALU', 'SQ_LLC_0', 'SQ_LLC_1', + 'SQ_LLC_BYPASS', 'SQ_LLC_CTL', 'SQ_LLC_RSVD_2', + 'SQ_MAX_PGM_SGPRS', 'SQ_MAX_PGM_VGPRS', 'SQ_NON_EVENT', + 'SQ_NO_INST_ISSUE', 'SQ_NO_INST_ISSUE_ALU_DEP', + 'SQ_NO_INST_ISSUE_BARRIER_WAIT', 'SQ_NO_INST_ISSUE_NO_ARB_WIN', + 'SQ_NO_INST_ISSUE_NO_INSTS', 'SQ_NO_INST_ISSUE_OTHER', + 'SQ_NO_INST_ISSUE_SLEEP_WAIT', 'SQ_NO_INST_ISSUE_S_WAITCNT', + 'SQ_OOB_COMPLETE', 'SQ_OOB_INDEX_AND_OFFSET', 'SQ_OOB_INDEX_ONLY', + 'SQ_OOB_NUM_RECORDS_0', 'SQ_OOB_SELECT', 'SQ_PERF_SEL', + 'SQ_PERF_SEL_ACCUM_PREV', 'SQ_PERF_SEL_BUSY_CYCLES', + 'SQ_PERF_SEL_CYCLES', 'SQ_PERF_SEL_DUMMY_END', + 'SQ_PERF_SEL_DUMMY_LAST', 'SQ_PERF_SEL_EVENTS', + 'SQ_PERF_SEL_EXP_BUS0_BUSY', 'SQ_PERF_SEL_EXP_BUS1_BUSY', + 'SQ_PERF_SEL_EXP_REQ0_BUS_BUSY', 'SQ_PERF_SEL_EXP_REQ1_BUS_BUSY', + 'SQ_PERF_SEL_EXP_REQ_BUS_STALL', 'SQ_PERF_SEL_EXP_REQ_FIFO_FULL', + 'SQ_PERF_SEL_IFETCH_LEVEL', 'SQ_PERF_SEL_IFETCH_REQS', + 'SQ_PERF_SEL_INSTS_ALL', 'SQ_PERF_SEL_INSTS_BRANCH', + 'SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN', + 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN', + 'SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS', + 'SQ_PERF_SEL_INSTS_DELAY_ALU', + 'SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32', 'SQ_PERF_SEL_INSTS_EXP', + 'SQ_PERF_SEL_INSTS_EXP_GDS', 'SQ_PERF_SEL_INSTS_FLAT', + 'SQ_PERF_SEL_INSTS_GDS', 'SQ_PERF_SEL_INSTS_INTERNAL', + 'SQ_PERF_SEL_INSTS_LDS', 'SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD', + 'SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD', 'SQ_PERF_SEL_INSTS_SALU', + 'SQ_PERF_SEL_INSTS_SENDMSG', 'SQ_PERF_SEL_INSTS_SMEM', + 'SQ_PERF_SEL_INSTS_SMEM_NORM', 'SQ_PERF_SEL_INSTS_TEX', + 'SQ_PERF_SEL_INSTS_TEX_LOAD', 'SQ_PERF_SEL_INSTS_TEX_STORE', + 'SQ_PERF_SEL_INSTS_VALU', 'SQ_PERF_SEL_INSTS_VALU_1_PASS', + 'SQ_PERF_SEL_INSTS_VALU_2_PASS', 'SQ_PERF_SEL_INSTS_VALU_4_PASS', + 'SQ_PERF_SEL_INSTS_VALU_DP', + 'SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED', + 'SQ_PERF_SEL_INSTS_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64', + 'SQ_PERF_SEL_INSTS_VALU_TRANS', 'SQ_PERF_SEL_INSTS_VALU_TRANS32', + 'SQ_PERF_SEL_INSTS_VALU_VINTERP', + 'SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP', + 'SQ_PERF_SEL_INSTS_WAVE32', 'SQ_PERF_SEL_INSTS_WAVE32_FLAT', + 'SQ_PERF_SEL_INSTS_WAVE32_LDS', + 'SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD', + 'SQ_PERF_SEL_INSTS_WAVE32_TEX', + 'SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD', + 'SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE', + 'SQ_PERF_SEL_INSTS_WAVE32_VALU', + 'SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32', + 'SQ_PERF_SEL_INST_CACHE_REQ_STALL', 'SQ_PERF_SEL_INST_CYCLES_EXP', + 'SQ_PERF_SEL_INST_CYCLES_EXP_GDS', 'SQ_PERF_SEL_INST_CYCLES_FLAT', + 'SQ_PERF_SEL_INST_CYCLES_GDS', 'SQ_PERF_SEL_INST_CYCLES_LDS', + 'SQ_PERF_SEL_INST_CYCLES_TEX', 'SQ_PERF_SEL_INST_CYCLES_VALU', + 'SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC', + 'SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32', + 'SQ_PERF_SEL_INST_CYCLES_VMEM', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD', + 'SQ_PERF_SEL_INST_CYCLES_VMEM_STORE', + 'SQ_PERF_SEL_INST_LEVEL_EXP', 'SQ_PERF_SEL_INST_LEVEL_GDS', + 'SQ_PERF_SEL_INST_LEVEL_LDS', 'SQ_PERF_SEL_INST_LEVEL_SMEM', + 'SQ_PERF_SEL_INST_LEVEL_TEX_LOAD', + 'SQ_PERF_SEL_INST_LEVEL_TEX_STORE', 'SQ_PERF_SEL_ITEMS', + 'SQ_PERF_SEL_ITEMS_MAX_VALU', 'SQ_PERF_SEL_ITEMS_VALU', + 'SQ_PERF_SEL_ITEM_CYCLES_VALU', 'SQ_PERF_SEL_ITEM_CYCLES_VMEM', + 'SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_LEVEL_WAVES', 'SQ_PERF_SEL_MSG', + 'SQ_PERF_SEL_MSG_BUS_BUSY', 'SQ_PERF_SEL_MSG_FIFO_FULL_STALL', + 'SQ_PERF_SEL_MSG_INTERRUPT', 'SQ_PERF_SEL_NONE', + 'SQ_PERF_SEL_NONE2', 'SQ_PERF_SEL_OVERFLOW_PREV', + 'SQ_PERF_SEL_PS_QUADS', 'SQ_PERF_SEL_SALU_GATHER_FULL_STALL', + 'SQ_PERF_SEL_SALU_PIPE_STALL', 'SQ_PERF_SEL_SALU_SGATHER_STALL', + 'SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL', + 'SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES', + 'SQ_PERF_SEL_SP_CONST_CYCLES', + 'SQ_PERF_SEL_SP_CONST_STALL_CYCLES', 'SQ_PERF_SEL_USER0', + 'SQ_PERF_SEL_USER1', 'SQ_PERF_SEL_USER10', 'SQ_PERF_SEL_USER11', + 'SQ_PERF_SEL_USER12', 'SQ_PERF_SEL_USER13', 'SQ_PERF_SEL_USER14', + 'SQ_PERF_SEL_USER15', 'SQ_PERF_SEL_USER2', 'SQ_PERF_SEL_USER3', + 'SQ_PERF_SEL_USER4', 'SQ_PERF_SEL_USER5', 'SQ_PERF_SEL_USER6', + 'SQ_PERF_SEL_USER7', 'SQ_PERF_SEL_USER8', 'SQ_PERF_SEL_USER9', + 'SQ_PERF_SEL_USER_LEVEL0', 'SQ_PERF_SEL_USER_LEVEL1', + 'SQ_PERF_SEL_USER_LEVEL10', 'SQ_PERF_SEL_USER_LEVEL11', + 'SQ_PERF_SEL_USER_LEVEL12', 'SQ_PERF_SEL_USER_LEVEL13', + 'SQ_PERF_SEL_USER_LEVEL14', 'SQ_PERF_SEL_USER_LEVEL15', + 'SQ_PERF_SEL_USER_LEVEL2', 'SQ_PERF_SEL_USER_LEVEL3', + 'SQ_PERF_SEL_USER_LEVEL4', 'SQ_PERF_SEL_USER_LEVEL5', + 'SQ_PERF_SEL_USER_LEVEL6', 'SQ_PERF_SEL_USER_LEVEL7', + 'SQ_PERF_SEL_USER_LEVEL8', 'SQ_PERF_SEL_USER_LEVEL9', + 'SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL', + 'SQ_PERF_SEL_VALU_READWRITELANE_CYCLES', + 'SQ_PERF_SEL_VALU_RETURN_SDST', + 'SQ_PERF_SEL_VALU_SGATHER_FULL_STALL', + 'SQ_PERF_SEL_VALU_SGATHER_STALL', + 'SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL', + 'SQ_PERF_SEL_VALU_STARVE', 'SQ_PERF_SEL_VMEM_ARB_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_ACTIVE', 'SQ_PERF_SEL_VMEM_BUS_STALL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL', + 'SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY', + 'SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY', + 'SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT', + 'SQ_PERF_SEL_WAIT_ANY', 'SQ_PERF_SEL_WAIT_BARRIER', + 'SQ_PERF_SEL_WAIT_CNT_ANY', 'SQ_PERF_SEL_WAIT_CNT_EXP', + 'SQ_PERF_SEL_WAIT_CNT_LGKM', 'SQ_PERF_SEL_WAIT_CNT_VMVS', + 'SQ_PERF_SEL_WAIT_DELAY_ALU', 'SQ_PERF_SEL_WAIT_DEPCTR', + 'SQ_PERF_SEL_WAIT_EXP_ALLOC', 'SQ_PERF_SEL_WAIT_IFETCH', + 'SQ_PERF_SEL_WAIT_INST_ANY', 'SQ_PERF_SEL_WAIT_INST_BR_MSG', + 'SQ_PERF_SEL_WAIT_INST_EXP_GDS', 'SQ_PERF_SEL_WAIT_INST_FLAT', + 'SQ_PERF_SEL_WAIT_INST_LDS', 'SQ_PERF_SEL_WAIT_INST_SCA', + 'SQ_PERF_SEL_WAIT_INST_TEX', 'SQ_PERF_SEL_WAIT_INST_VALU', + 'SQ_PERF_SEL_WAIT_INST_VMEM', 'SQ_PERF_SEL_WAIT_OTHER', + 'SQ_PERF_SEL_WAIT_SLEEP', 'SQ_PERF_SEL_WAIT_TTRACE', + 'SQ_PERF_SEL_WAVE32_INSTS', 'SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS', + 'SQ_PERF_SEL_WAVE32_ITEMS', 'SQ_PERF_SEL_WAVE64_HALF_SKIP', + 'SQ_PERF_SEL_WAVE64_INSTS', 'SQ_PERF_SEL_WAVE64_ITEMS', + 'SQ_PERF_SEL_WAVES', 'SQ_PERF_SEL_WAVES_32', + 'SQ_PERF_SEL_WAVES_64', 'SQ_PERF_SEL_WAVES_EQ_32', + 'SQ_PERF_SEL_WAVES_EQ_64', 'SQ_PERF_SEL_WAVES_INITIAL_PREFETCH', + 'SQ_PERF_SEL_WAVES_LT_16', 'SQ_PERF_SEL_WAVES_LT_32', + 'SQ_PERF_SEL_WAVES_LT_48', 'SQ_PERF_SEL_WAVES_LT_64', + 'SQ_PERF_SEL_WAVES_RESTORED', 'SQ_PERF_SEL_WAVES_SAVED', + 'SQ_PERF_SEL_WAVE_CYCLES', 'SQ_PERF_SEL_WAVE_READY', + 'SQ_ROUND_MINUS_INFINITY', 'SQ_ROUND_MODE', + 'SQ_ROUND_NEAREST_EVEN', 'SQ_ROUND_PLUS_INFINITY', + 'SQ_ROUND_TO_ZERO', 'SQ_RSRC_BUF', 'SQ_RSRC_BUF_RSVD_1', + 'SQ_RSRC_BUF_RSVD_2', 'SQ_RSRC_BUF_RSVD_3', 'SQ_RSRC_BUF_TYPE', + 'SQ_RSRC_FLAT', 'SQ_RSRC_FLAT_RSVD_0', 'SQ_RSRC_FLAT_RSVD_2', + 'SQ_RSRC_FLAT_RSVD_3', 'SQ_RSRC_FLAT_TYPE', 'SQ_RSRC_IMG_1D', + 'SQ_RSRC_IMG_1D_ARRAY', 'SQ_RSRC_IMG_2D', 'SQ_RSRC_IMG_2D_ARRAY', + 'SQ_RSRC_IMG_2D_MSAA', 'SQ_RSRC_IMG_2D_MSAA_ARRAY', + 'SQ_RSRC_IMG_3D', 'SQ_RSRC_IMG_CUBE', 'SQ_RSRC_IMG_RSVD_0', + 'SQ_RSRC_IMG_RSVD_1', 'SQ_RSRC_IMG_RSVD_2', 'SQ_RSRC_IMG_RSVD_3', + 'SQ_RSRC_IMG_RSVD_4', 'SQ_RSRC_IMG_RSVD_5', 'SQ_RSRC_IMG_RSVD_6', + 'SQ_RSRC_IMG_RSVD_7', 'SQ_RSRC_IMG_TYPE', 'SQ_SEL_0', 'SQ_SEL_1', + 'SQ_SEL_N_BC_1', 'SQ_SEL_RESERVED_1', 'SQ_SEL_W', 'SQ_SEL_X', + 'SQ_SEL_XYZW01', 'SQ_SEL_Y', 'SQ_SEL_Z', 'SQ_TEX_ANISO_RATIO', + 'SQ_TEX_ANISO_RATIO_1', 'SQ_TEX_ANISO_RATIO_16', + 'SQ_TEX_ANISO_RATIO_2', 'SQ_TEX_ANISO_RATIO_4', + 'SQ_TEX_ANISO_RATIO_8', 'SQ_TEX_BORDER_COLOR', + 'SQ_TEX_BORDER_COLOR_OPAQUE_BLACK', + 'SQ_TEX_BORDER_COLOR_OPAQUE_WHITE', + 'SQ_TEX_BORDER_COLOR_REGISTER', 'SQ_TEX_BORDER_COLOR_TRANS_BLACK', + 'SQ_TEX_CLAMP', 'SQ_TEX_CLAMP_BORDER', 'SQ_TEX_CLAMP_HALF_BORDER', + 'SQ_TEX_CLAMP_LAST_TEXEL', 'SQ_TEX_DEPTH_COMPARE', + 'SQ_TEX_DEPTH_COMPARE_ALWAYS', 'SQ_TEX_DEPTH_COMPARE_EQUAL', + 'SQ_TEX_DEPTH_COMPARE_GREATER', + 'SQ_TEX_DEPTH_COMPARE_GREATEREQUAL', 'SQ_TEX_DEPTH_COMPARE_LESS', + 'SQ_TEX_DEPTH_COMPARE_LESSEQUAL', 'SQ_TEX_DEPTH_COMPARE_NEVER', + 'SQ_TEX_DEPTH_COMPARE_NOTEQUAL', 'SQ_TEX_MIP_FILTER', + 'SQ_TEX_MIP_FILTER_LINEAR', 'SQ_TEX_MIP_FILTER_NONE', + 'SQ_TEX_MIP_FILTER_POINT', 'SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ', + 'SQ_TEX_MIRROR', 'SQ_TEX_MIRROR_ONCE_BORDER', + 'SQ_TEX_MIRROR_ONCE_HALF_BORDER', 'SQ_TEX_MIRROR_ONCE_LAST_TEXEL', + 'SQ_TEX_WRAP', 'SQ_TEX_XY_FILTER', + 'SQ_TEX_XY_FILTER_ANISO_BILINEAR', 'SQ_TEX_XY_FILTER_ANISO_POINT', + 'SQ_TEX_XY_FILTER_BILINEAR', 'SQ_TEX_XY_FILTER_POINT', + 'SQ_TEX_Z_FILTER', 'SQ_TEX_Z_FILTER_LINEAR', + 'SQ_TEX_Z_FILTER_NONE', 'SQ_TEX_Z_FILTER_POINT', + 'SQ_TT_INST_EXCLUDE_EXPGNT234_BIT', + 'SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT', + 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT', + 'SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT', 'SQ_TT_MODE', + 'SQ_TT_MODE_DETAIL', 'SQ_TT_MODE_GLOBAL', 'SQ_TT_MODE_OFF', + 'SQ_TT_MODE_ON', 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT', + 'SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT', + 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT', + 'SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT', + 'SQ_TT_REG_EXCLUDE_USER_DATA_BIT', + 'SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT', 'SQ_TT_RT_FREQ', + 'SQ_TT_RT_FREQ_1024_CLK', 'SQ_TT_RT_FREQ_4096_CLK', + 'SQ_TT_RT_FREQ_NEVER', 'SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_INST_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT', 'SQ_TT_TOKEN_EXCLUDE_REG_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT', + 'SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT', + 'SQ_TT_TOKEN_MASK_ALL_BIT', 'SQ_TT_TOKEN_MASK_ALL_SHIFT', + 'SQ_TT_TOKEN_MASK_COMP_BIT', 'SQ_TT_TOKEN_MASK_COMP_SHIFT', + 'SQ_TT_TOKEN_MASK_CONFIG_BIT', 'SQ_TT_TOKEN_MASK_CONFIG_SHIFT', + 'SQ_TT_TOKEN_MASK_CONTEXT_BIT', 'SQ_TT_TOKEN_MASK_CONTEXT_SHIFT', + 'SQ_TT_TOKEN_MASK_GFXUDEC_BIT', 'SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT', + 'SQ_TT_TOKEN_MASK_INST_EXCLUDE', + 'SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT', + 'SQ_TT_TOKEN_MASK_REG_EXCLUDE', + 'SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT', + 'SQ_TT_TOKEN_MASK_REG_INCLUDE', + 'SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT', 'SQ_TT_TOKEN_MASK_RSVD_BIT', + 'SQ_TT_TOKEN_MASK_RSVD_SHIFT', 'SQ_TT_TOKEN_MASK_SHDEC_BIT', + 'SQ_TT_TOKEN_MASK_SHDEC_SHIFT', 'SQ_TT_TOKEN_MASK_SQDEC_BIT', + 'SQ_TT_TOKEN_MASK_SQDEC_SHIFT', + 'SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT', 'SQ_TT_UTIL_TIMER', + 'SQ_TT_UTIL_TIMER_100_CLK', 'SQ_TT_UTIL_TIMER_250_CLK', + 'SQ_TT_WAVESTART_MODE', 'SQ_TT_WAVESTART_MODE_ALLOC', + 'SQ_TT_WAVESTART_MODE_PBB_ID', 'SQ_TT_WAVESTART_MODE_SHORT', + 'SQ_TT_WTYPE_INCLUDE', 'SQ_TT_WTYPE_INCLUDE_CS_BIT', + 'SQ_TT_WTYPE_INCLUDE_CS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_GS_BIT', + 'SQ_TT_WTYPE_INCLUDE_GS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_HS_BIT', + 'SQ_TT_WTYPE_INCLUDE_HS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_PS_BIT', + 'SQ_TT_WTYPE_INCLUDE_PS_SHIFT', 'SQ_TT_WTYPE_INCLUDE_RSVD0_BIT', + 'SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT', + 'SQ_TT_WTYPE_INCLUDE_RSVD1_BIT', + 'SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT', + 'SQ_TT_WTYPE_INCLUDE_RSVD2_BIT', + 'SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT', 'SQ_TT_WTYPE_INCLUDE_SHIFT', + 'SQ_WATCH_MODES', 'SQ_WATCH_MODE_ALL', 'SQ_WATCH_MODE_ATOMIC', + 'SQ_WATCH_MODE_NONREAD', 'SQ_WATCH_MODE_READ', + 'SQ_WAVE_FWD_PROG_INTERVAL', 'SQ_WAVE_FWD_PROG_INTERVAL_1024', + 'SQ_WAVE_FWD_PROG_INTERVAL_256', 'SQ_WAVE_FWD_PROG_INTERVAL_4096', + 'SQ_WAVE_FWD_PROG_INTERVAL_NEVER', 'SQ_WAVE_IB_DEP_HOLD_CNT_SIZE', + 'SQ_WAVE_IB_DEP_LDS_DIR_SIZE', 'SQ_WAVE_IB_DEP_SA_EXEC_SIZE', + 'SQ_WAVE_IB_DEP_SA_M0_SIZE', 'SQ_WAVE_IB_DEP_SA_SDST_SIZE', + 'SQ_WAVE_IB_DEP_VA_EXEC_SIZE', 'SQ_WAVE_IB_DEP_VA_SDST_SIZE', + 'SQ_WAVE_IB_DEP_VA_SSRC_SIZE', 'SQ_WAVE_IB_DEP_VA_VCC_SIZE', + 'SQ_WAVE_IB_DEP_VA_VDST_SIZE', 'SQ_WAVE_IB_DEP_VM_VSRC_SIZE', + 'SQ_WAVE_IB_ECC_CLEAN', 'SQ_WAVE_IB_ECC_ERR_CONTINUE', + 'SQ_WAVE_IB_ECC_ERR_HALT', 'SQ_WAVE_IB_ECC_ST', + 'SQ_WAVE_IB_ECC_WITH_ERR_MSG', 'SQ_WAVE_SCHED_MODES', + 'SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST', 'SQ_WAVE_SCHED_MODE_EXPERT', + 'SQ_WAVE_SCHED_MODE_NORMAL', 'SQ_WAVE_TYPE', 'SQ_WAVE_TYPE_CS', + 'SQ_WAVE_TYPE_GS', 'SQ_WAVE_TYPE_HS', 'SQ_WAVE_TYPE_PS', + 'SQ_WAVE_TYPE_PS0', 'SQ_WAVE_TYPE_PS1', 'SQ_WAVE_TYPE_PS2', + 'SQ_WAVE_TYPE_PS3', 'SQ_WAVE_TYPE_RSVD0', 'SQ_WAVE_TYPE_RSVD1', + 'SQ_WAVE_TYPE_RSVD2', 'SRCID_NONSECURE_CP', + 'SRCID_NONSECURE_CP_RCIU', 'SRCID_RLC', 'SRCID_RLCV', + 'SRCID_SECURE_CP', 'SRCID_SECURE_CP_RCIU', 'STALL', + 'STENCIL_ADD_CLAMP', 'STENCIL_ADD_WRAP', 'STENCIL_AND', + 'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_NAND', 'STENCIL_NOR', + 'STENCIL_ONES', 'STENCIL_OR', 'STENCIL_REPLACE_OP', + 'STENCIL_REPLACE_TEST', 'STENCIL_SUB_CLAMP', 'STENCIL_SUB_WRAP', + 'STENCIL_XNOR', 'STENCIL_XOR', 'STENCIL_ZERO', + 'STREAM_0_SYNCHRONIZATION', + 'STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_0_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_10_SYNCHRONIZATION', + 'STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION', + 'STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION', + 'STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION', + 'STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION', + 'STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION', + 'STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_1_SYNCHRONIZATION', + 'STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_1_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_2_SYNCHRONIZATION', + 'STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_2_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_3_SYNCHRONIZATION', + 'STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED', + 'STREAM_3_SYNCHRONIZATION_STEAM_STOPPED', + 'STREAM_4_SYNCHRONIZATION', + 'STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_5_SYNCHRONIZATION', + 'STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_6_SYNCHRONIZATION', + 'STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION', + 'STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION', + 'STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION', + 'STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED', + 'STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED', + 'STREAM_DSC_444_RGB', 'STREAM_DSC_DISABLE', + 'STREAM_DSC_NATIVE_422_420', 'STREAM_ODM_COMBINE_1_SEGMENT', + 'STREAM_ODM_COMBINE_2_SEGMENT', 'STREAM_ODM_COMBINE_4_SEGMENT', + 'STREAM_ODM_COMBINE_RESERVED', 'STREAM_PIXEL_ENCODING_420', + 'STREAM_PIXEL_ENCODING_422', 'STREAM_PIXEL_ENCODING_444_RGB', + 'STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET', + 'STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM', + 'STRM_PERFMON_STATE_RESERVED_3', + 'STRM_PERFMON_STATE_START_COUNTING', + 'STRM_PERFMON_STATE_STOP_COUNTING', 'SURFACE_DCC', + 'SURFACE_DCC_BLOCK_IS_IND_128B', 'SURFACE_DCC_BLOCK_IS_IND_64B', + 'SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL', + 'SURFACE_DCC_BLOCK_IS_UNCONSTRAINED', 'SURFACE_DCC_IND_128B', + 'SURFACE_DCC_IND_64B', 'SURFACE_DCC_IND_BLK', + 'SURFACE_DCC_IS_IND_128B', 'SURFACE_DCC_IS_IND_64B', + 'SURFACE_DCC_IS_NOT_IND_128B', 'SURFACE_DCC_IS_NOT_IND_64B', + 'SURFACE_FLIP_AWAY_INT_LEVEL', 'SURFACE_FLIP_AWAY_INT_PULSE', + 'SURFACE_FLIP_AWAY_INT_TYPE', 'SURFACE_FLIP_EXEC_DEBUG_MODE', + 'SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE', + 'SURFACE_FLIP_EXEC_NORMAL_MODE', 'SURFACE_FLIP_INT_LEVEL', + 'SURFACE_FLIP_INT_PULSE', 'SURFACE_FLIP_INT_TYPE', + 'SURFACE_FLIP_IN_STEREOSYNC', 'SURFACE_FLIP_IN_STEREOSYNC_MODE', + 'SURFACE_FLIP_MODE_FOR_STEREOSYNC', + 'SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED', + 'SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE', + 'SURFACE_FLIP_STEREO_SELECT_DISABLE', + 'SURFACE_FLIP_STEREO_SELECT_DISABLED', + 'SURFACE_FLIP_STEREO_SELECT_ENABLED', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT', + 'SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT', + 'SURFACE_FLIP_TYPE', 'SURFACE_FLIP_VUPDATE_SKIP_NUM', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_0', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_1', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_10', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_11', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_12', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_13', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_14', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_15', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_2', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_3', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_4', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_5', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_6', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_7', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_8', + 'SURFACE_FLIP_VUPDATE_SKIP_NUM_9', 'SURFACE_INUSE_IS_LATCHED', + 'SURFACE_INUSE_IS_NOT_LATCHED', 'SURFACE_INUSE_RAED_NO_LATCH', + 'SURFACE_IS_DCC', 'SURFACE_IS_NOT_DCC', 'SURFACE_IS_NOT_TMZ', + 'SURFACE_IS_TMZ', 'SURFACE_I_FLIP', 'SURFACE_PIXEL_FORMAT', + 'SURFACE_TMZ', 'SURFACE_UPDATE_IS_LOCKED', + 'SURFACE_UPDATE_IS_UNLOCKED', 'SURFACE_UPDATE_LOCK', + 'SURFACE_V_FLIP', 'SU_PERFCNT_SEL', 'SWATH_HEIGHT', + 'SWATH_HEIGHT_16L', 'SWATH_HEIGHT_1L', 'SWATH_HEIGHT_2L', + 'SWATH_HEIGHT_4L', 'SWATH_HEIGHT_8L', 'SX_BLEND_OPT', + 'SX_CB_RAT_ACK_REQUEST', 'SX_DOWNCONVERT_FORMAT', + 'SX_OPT_COMB_FCN', 'SX_PERFCOUNTER_VALS', 'SX_PERF_SEL_CLOCK', + 'SX_PERF_SEL_CLOCK_DROP_STALL', 'SX_PERF_SEL_COL_BUSY', + 'SX_PERF_SEL_DB0_4X2_DISCARD', 'SX_PERF_SEL_DB0_END_OF_WAVE', + 'SX_PERF_SEL_DB0_HALF_QUADS', 'SX_PERF_SEL_DB0_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB0_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB0_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB0_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB0_PIXELS', + 'SX_PERF_SEL_DB0_PIXEL_IDLE', 'SX_PERF_SEL_DB0_PIXEL_STALL', + 'SX_PERF_SEL_DB0_PRED_PIXELS', 'SX_PERF_SEL_DB0_SIZE', + 'SX_PERF_SEL_DB1_4X2_DISCARD', 'SX_PERF_SEL_DB1_END_OF_WAVE', + 'SX_PERF_SEL_DB1_HALF_QUADS', 'SX_PERF_SEL_DB1_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB1_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB1_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB1_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB1_PIXELS', + 'SX_PERF_SEL_DB1_PIXEL_IDLE', 'SX_PERF_SEL_DB1_PIXEL_STALL', + 'SX_PERF_SEL_DB1_PRED_PIXELS', 'SX_PERF_SEL_DB1_SIZE', + 'SX_PERF_SEL_DB2_4X2_DISCARD', 'SX_PERF_SEL_DB2_END_OF_WAVE', + 'SX_PERF_SEL_DB2_HALF_QUADS', 'SX_PERF_SEL_DB2_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB2_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB2_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB2_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB2_PIXELS', + 'SX_PERF_SEL_DB2_PIXEL_IDLE', 'SX_PERF_SEL_DB2_PIXEL_STALL', + 'SX_PERF_SEL_DB2_PRED_PIXELS', 'SX_PERF_SEL_DB2_SIZE', + 'SX_PERF_SEL_DB3_4X2_DISCARD', 'SX_PERF_SEL_DB3_END_OF_WAVE', + 'SX_PERF_SEL_DB3_HALF_QUADS', 'SX_PERF_SEL_DB3_MRT_BLEND_BYPASS', + 'SX_PERF_SEL_DB3_MRT_DISCARD_SRC', + 'SX_PERF_SEL_DB3_MRT_DONT_RD_DEST', + 'SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS', + 'SX_PERF_SEL_DB3_MRT_SINGLE_QUADS', 'SX_PERF_SEL_DB3_PIXELS', + 'SX_PERF_SEL_DB3_PIXEL_IDLE', 'SX_PERF_SEL_DB3_PIXEL_STALL', + 'SX_PERF_SEL_DB3_PRED_PIXELS', 'SX_PERF_SEL_DB3_SIZE', + 'SX_PERF_SEL_GATE_EN1', 'SX_PERF_SEL_GATE_EN2', + 'SX_PERF_SEL_GATE_EN3', 'SX_PERF_SEL_GATE_EN4', + 'SX_PERF_SEL_GATE_EN5', 'SX_PERF_SEL_GATE_EN6', + 'SX_PERF_SEL_GATE_EN7', 'SX_PERF_SEL_GATE_EN8', + 'SX_PERF_SEL_IDX_BUSY', 'SX_PERF_SEL_IDX_IDLE_CYCLES', + 'SX_PERF_SEL_IDX_REQ', 'SX_PERF_SEL_IDX_REQ_LATENCY', + 'SX_PERF_SEL_IDX_RET', 'SX_PERF_SEL_IDX_SCBD_STALL', + 'SX_PERF_SEL_IDX_STALL_CYCLES', 'SX_PERF_SEL_PA_IDLE_CYCLES', + 'SX_PERF_SEL_PA_POS', 'SX_PERF_SEL_PA_POS_BANK_CONF', + 'SX_PERF_SEL_PA_REQ', 'SX_PERF_SEL_PA_REQ_LATENCY', + 'SX_PERF_SEL_POS_BUSY', 'SX_PERF_SEL_POS_SCBD_STALL', + 'SX_PERF_SEL_SH_COLOR_STALL', 'SX_PERF_SEL_SH_COLOR_STARVE', + 'SX_PERF_SEL_SH_IDX_STARVE', 'SX_PERF_SEL_SH_POS_STALL', + 'SX_PERF_SEL_SH_POS_STARVE', 'SX_RT_EXPORT_10_11_11', + 'SX_RT_EXPORT_16_16_AR', 'SX_RT_EXPORT_16_16_GR', + 'SX_RT_EXPORT_1_5_5_5', 'SX_RT_EXPORT_2_10_10_10', + 'SX_RT_EXPORT_2_10_10_10_6E4', 'SX_RT_EXPORT_2_10_10_10_7E3', + 'SX_RT_EXPORT_32_A', 'SX_RT_EXPORT_32_R', 'SX_RT_EXPORT_4_4_4_4', + 'SX_RT_EXPORT_5_6_5', 'SX_RT_EXPORT_8_8_8_8', + 'SX_RT_EXPORT_9_9_9_E5', 'SX_RT_EXPORT_NO_CONVERSION', + 'SYMCLK_FE_FORCE_EN', 'SYMCLK_FE_FORCE_EN_DISABLE', + 'SYMCLK_FE_FORCE_EN_ENABLE', 'SYMCLK_FE_FORCE_SRC', + 'SYMCLK_FE_FORCE_SRC_RESERVED', 'SYMCLK_FE_FORCE_SRC_UNIPHYA', + 'SYMCLK_FE_FORCE_SRC_UNIPHYB', 'SYMCLK_FE_FORCE_SRC_UNIPHYC', + 'SYMCLK_FE_FORCE_SRC_UNIPHYD', 'ScMap', 'ScUncertaintyRegionMode', + 'ScUncertaintyRegionMult', 'ScXsel', 'ScYsel', 'SeMap', + 'SePairMap', 'SePairXsel', 'SePairYsel', 'SeXsel', 'SeYsel', + 'SourceFormat', 'Spare_257', 'StencilOp', 'TA_PERFCOUNT_SEL', + 'TA_PERF_SEL_NULL', 'TA_PERF_SEL_addr_stalled_by_tc_cycles', + 'TA_PERF_SEL_addr_stalled_by_td_cycles', + 'TA_PERF_SEL_addresser_busy', 'TA_PERF_SEL_addresser_fifo_busy', + 'TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles', + 'TA_PERF_SEL_addresser_stalled_cycles', + 'TA_PERF_SEL_aligner_busy', + 'TA_PERF_SEL_aligner_clk_valid_cycles', + 'TA_PERF_SEL_aligner_cycles', 'TA_PERF_SEL_aniso_10_cycle_quads', + 'TA_PERF_SEL_aniso_12_cycle_quads', + 'TA_PERF_SEL_aniso_14_cycle_quads', + 'TA_PERF_SEL_aniso_16_cycle_quads', + 'TA_PERF_SEL_aniso_1_cycle_quads', + 'TA_PERF_SEL_aniso_2_cycle_quads', + 'TA_PERF_SEL_aniso_4_cycle_quads', + 'TA_PERF_SEL_aniso_6_cycle_quads', + 'TA_PERF_SEL_aniso_8_cycle_quads', + 'TA_PERF_SEL_aniso_gt1_cycle_quads', + 'TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles', + 'TA_PERF_SEL_aniso_stalled_cycles', + 'TA_PERF_SEL_atomic_2_write_data_vgpr_instructions', + 'TA_PERF_SEL_atomic_4_write_data_vgpr_instructions', + 'TA_PERF_SEL_atomic_write_data_input_cycles', + 'TA_PERF_SEL_atomic_write_data_output_cycles', + 'TA_PERF_SEL_bf_busy', + 'TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_buffer_1_address_input_vgpr_instructions', + 'TA_PERF_SEL_buffer_2_address_input_vgpr_instructions', + 'TA_PERF_SEL_buffer_atomic_wavefronts', + 'TA_PERF_SEL_buffer_flat_1_op_burst', + 'TA_PERF_SEL_buffer_flat_2to3_op_burst', + 'TA_PERF_SEL_buffer_flat_4to31_op_burst', + 'TA_PERF_SEL_buffer_flat_clk_valid_cycles', + 'TA_PERF_SEL_buffer_flat_ge32_op_burst', + 'TA_PERF_SEL_buffer_has_index_instructions', + 'TA_PERF_SEL_buffer_has_offset_instructions', + 'TA_PERF_SEL_buffer_load_wavefronts', + 'TA_PERF_SEL_buffer_store_wavefronts', + 'TA_PERF_SEL_buffer_total_cycles', + 'TA_PERF_SEL_buffer_wavefronts', 'TA_PERF_SEL_bvh_total_cycles', + 'TA_PERF_SEL_color_1_cycle_quads', + 'TA_PERF_SEL_color_2_cycle_quads', + 'TA_PERF_SEL_color_3_cycle_quads', + 'TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles', + 'TA_PERF_SEL_deriv_stalled_cycles', + 'TA_PERF_SEL_flat_1_address_input_vgpr_instructions', + 'TA_PERF_SEL_flat_atomic_wavefronts', + 'TA_PERF_SEL_flat_load_wavefronts', + 'TA_PERF_SEL_flat_store_wavefronts', + 'TA_PERF_SEL_flat_total_cycles', 'TA_PERF_SEL_flat_wavefronts', + 'TA_PERF_SEL_gradient_busy', + 'TA_PERF_SEL_gradient_clk_valid_cycles', + 'TA_PERF_SEL_gradient_cycles', 'TA_PERF_SEL_gradient_fifo_busy', + 'TA_PERF_SEL_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_harvestable_register_clk_enabled_cycles', + 'TA_PERF_SEL_ibubble_16to31_cycle_burst', + 'TA_PERF_SEL_ibubble_1_cycle_burst', + 'TA_PERF_SEL_ibubble_2to3_cycle_burst', + 'TA_PERF_SEL_ibubble_32to63_cycle_burst', + 'TA_PERF_SEL_ibubble_4to15_cycle_burst', + 'TA_PERF_SEL_ibubble_ge64_cycle_burst', + 'TA_PERF_SEL_image_atomic_wavefronts', + 'TA_PERF_SEL_image_bvh_11_input_vgpr_instructions', + 'TA_PERF_SEL_image_bvh_12_input_vgpr_instructions', + 'TA_PERF_SEL_image_bvh_1_op_burst', + 'TA_PERF_SEL_image_bvh_2to3_op_burst', + 'TA_PERF_SEL_image_bvh_4to7_op_burst', + 'TA_PERF_SEL_image_bvh_8_input_vgpr_instructions', + 'TA_PERF_SEL_image_bvh_9_input_vgpr_instructions', + 'TA_PERF_SEL_image_bvh_ge8_op_burst', + 'TA_PERF_SEL_image_linked_1_op_burst', + 'TA_PERF_SEL_image_linked_2to3_op_burst', + 'TA_PERF_SEL_image_linked_4to7_op_burst', + 'TA_PERF_SEL_image_linked_ge8_op_burst', + 'TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_1_op_burst', + 'TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_2to3_op_burst', + 'TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions', + 'TA_PERF_SEL_image_nosampler_4to31_op_burst', + 'TA_PERF_SEL_image_nosampler_ge32_op_burst', + 'TA_PERF_SEL_image_nosampler_has_q_instructions', + 'TA_PERF_SEL_image_nosampler_has_r_instructions', + 'TA_PERF_SEL_image_nosampler_has_t_instructions', + 'TA_PERF_SEL_image_nosampler_total_cycles', + 'TA_PERF_SEL_image_read_wavefronts', + 'TA_PERF_SEL_image_sampler_10_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_11_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_12_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_1_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_1_op_burst', + 'TA_PERF_SEL_image_sampler_2_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_2to3_op_burst', + 'TA_PERF_SEL_image_sampler_3_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_4_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_4to7_op_burst', + 'TA_PERF_SEL_image_sampler_5_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_6_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_7_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_8_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_9_input_vgpr_instructions', + 'TA_PERF_SEL_image_sampler_ge8_op_burst', + 'TA_PERF_SEL_image_sampler_has_bias_instructions', + 'TA_PERF_SEL_image_sampler_has_dr_instructions', + 'TA_PERF_SEL_image_sampler_has_ds_instructions', + 'TA_PERF_SEL_image_sampler_has_dt_instructions', + 'TA_PERF_SEL_image_sampler_has_offset_instructions', + 'TA_PERF_SEL_image_sampler_has_q_instructions', + 'TA_PERF_SEL_image_sampler_has_r_instructions', + 'TA_PERF_SEL_image_sampler_has_reference_instructions', + 'TA_PERF_SEL_image_sampler_has_t_instructions', + 'TA_PERF_SEL_image_sampler_total_cycles', + 'TA_PERF_SEL_image_sampler_wavefronts', + 'TA_PERF_SEL_image_store_wavefronts', + 'TA_PERF_SEL_image_wavefronts', 'TA_PERF_SEL_in_addr_cycles', + 'TA_PERF_SEL_in_busy', 'TA_PERF_SEL_in_cfifo_busy', + 'TA_PERF_SEL_in_data_cycles', 'TA_PERF_SEL_in_fifos_busy', + 'TA_PERF_SEL_in_qfifo_busy', 'TA_PERF_SEL_in_rfifo_busy', + 'TA_PERF_SEL_in_waiting_on_req_cycles', + 'TA_PERF_SEL_in_wfifo_busy', + 'TA_PERF_SEL_latency_ram_ref_required_instructions', + 'TA_PERF_SEL_latency_ram_weights_written_cycles', + 'TA_PERF_SEL_latency_ram_whv_required_instructions', + 'TA_PERF_SEL_latency_ram_whv_required_quads', + 'TA_PERF_SEL_latency_ram_ws_required_instructions', + 'TA_PERF_SEL_latency_ram_ws_required_quads', + 'TA_PERF_SEL_lod_aniso_clk_valid_cycles', 'TA_PERF_SEL_lod_busy', + 'TA_PERF_SEL_lod_fifo_busy', 'TA_PERF_SEL_mip_1_cycle_quads', + 'TA_PERF_SEL_mip_2_cycle_quads', + 'TA_PERF_SEL_mipmap_invalid_samples', + 'TA_PERF_SEL_mipmap_lod_0_samples', + 'TA_PERF_SEL_mipmap_lod_10_samples', + 'TA_PERF_SEL_mipmap_lod_11_samples', + 'TA_PERF_SEL_mipmap_lod_12_samples', + 'TA_PERF_SEL_mipmap_lod_13_samples', + 'TA_PERF_SEL_mipmap_lod_14_samples', + 'TA_PERF_SEL_mipmap_lod_1_samples', + 'TA_PERF_SEL_mipmap_lod_2_samples', + 'TA_PERF_SEL_mipmap_lod_3_samples', + 'TA_PERF_SEL_mipmap_lod_4_samples', + 'TA_PERF_SEL_mipmap_lod_5_samples', + 'TA_PERF_SEL_mipmap_lod_6_samples', + 'TA_PERF_SEL_mipmap_lod_7_samples', + 'TA_PERF_SEL_mipmap_lod_8_samples', + 'TA_PERF_SEL_mipmap_lod_9_samples', + 'TA_PERF_SEL_non_harvestable_clk_enabled_cycles', + 'TA_PERF_SEL_nonsampler_clk_valid_cycles', 'TA_PERF_SEL_ns_busy', + 'TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input', + 'TA_PERF_SEL_num_nodes_invalidated_due_to_oob', + 'TA_PERF_SEL_num_of_bvh_invalidated_first_tri', + 'TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri', + 'TA_PERF_SEL_num_of_bvh_invalidated_fp16_box', + 'TA_PERF_SEL_num_of_bvh_invalidated_fp32_box', + 'TA_PERF_SEL_num_of_bvh_invalidated_second_tri', + 'TA_PERF_SEL_num_of_bvh_invalidated_third_tri', + 'TA_PERF_SEL_num_of_bvh_valid_first_tri', + 'TA_PERF_SEL_num_of_bvh_valid_fourth_tri', + 'TA_PERF_SEL_num_of_bvh_valid_fp16_box', + 'TA_PERF_SEL_num_of_bvh_valid_fp32_box', + 'TA_PERF_SEL_num_of_bvh_valid_second_tri', + 'TA_PERF_SEL_num_of_bvh_valid_third_tri', + 'TA_PERF_SEL_num_unlit_nodes_ta_opt', + 'TA_PERF_SEL_point_sampled_quads', + 'TA_PERF_SEL_register_clk_valid_cycles', + 'TA_PERF_SEL_sampler_addressing_clk_valid_cycles', + 'TA_PERF_SEL_sampler_clk_valid_cycles', + 'TA_PERF_SEL_sampler_op_quads', 'TA_PERF_SEL_smp_busy_ns_idle', + 'TA_PERF_SEL_smp_idle_ns_busy', + 'TA_PERF_SEL_store_2_write_data_vgpr_instructions', + 'TA_PERF_SEL_store_3_write_data_vgpr_instructions', + 'TA_PERF_SEL_store_4_write_data_vgpr_instructions', + 'TA_PERF_SEL_store_has_w_instructions', + 'TA_PERF_SEL_store_has_x_instructions', + 'TA_PERF_SEL_store_has_y_instructions', + 'TA_PERF_SEL_store_has_z_instructions', + 'TA_PERF_SEL_store_write_data_input_cycles', + 'TA_PERF_SEL_store_write_data_output_cycles', + 'TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles', + 'TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles', + 'TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles', + 'TA_PERF_SEL_ta_busy', 'TA_PERF_SEL_tcreq_clk_valid_cycles', + 'TA_PERF_SEL_total_wavefronts', 'TA_PERF_SEL_vmemcmd_cycles', + 'TA_PERF_SEL_vmemreq_cycles', 'TA_PERF_SEL_vol_1_cycle_quads', + 'TA_PERF_SEL_vol_2_cycle_quads', 'TA_PERF_SEL_walker_cycles', + 'TA_PERF_SEL_write_1_op_burst', 'TA_PERF_SEL_write_2to3_op_burst', + 'TA_PERF_SEL_write_4to31_op_burst', + 'TA_PERF_SEL_write_data_clk_valid_cycles', + 'TA_PERF_SEL_write_ge32_op_burst', 'TA_PERF_SEL_write_path_busy', + 'TA_TC_ADDR_MODES', 'TA_TC_ADDR_MODE_BORDER_COLOR', + 'TA_TC_ADDR_MODE_COMP0', 'TA_TC_ADDR_MODE_COMP1', + 'TA_TC_ADDR_MODE_COMP2', 'TA_TC_ADDR_MODE_COMP3', + 'TA_TC_ADDR_MODE_DEFAULT', 'TA_TC_ADDR_MODE_UNALIGNED', + 'TA_TC_REQ_MODES', 'TA_TC_REQ_MODE_BORDER', 'TA_TC_REQ_MODE_BYTE', + 'TA_TC_REQ_MODE_BYTE_NV', 'TA_TC_REQ_MODE_DWORD', + 'TA_TC_REQ_MODE_NORMAL', 'TA_TC_REQ_MODE_TEX0', + 'TA_TC_REQ_MODE_TEX1', 'TA_TC_REQ_MODE_TEX2', 'TB_ACP_NOT_SEND', + 'TB_ACP_PKT_SEND', 'TB_ACR_0_MULTIPLE_RESERVED', + 'TB_ACR_1_MULTIPLE', 'TB_ACR_2_MULTIPLE', + 'TB_ACR_3_MULTIPLE_RESERVED', 'TB_ACR_4_MULTIPLE', + 'TB_ACR_5_MULTIPLE_RESERVED', 'TB_ACR_6_MULTIPLE_RESERVED', + 'TB_ACR_7_MULTIPLE_RESERVED', 'TB_ACR_CONT_DISABLE', + 'TB_ACR_CONT_ENABLE', 'TB_ACR_NOT_SEND', + 'TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE', 'TB_ACR_PKT_SEND', + 'TB_ACR_SELECT_32K', 'TB_ACR_SELECT_44K', 'TB_ACR_SELECT_48K', + 'TB_ACR_SELECT_HW', 'TB_ACR_SOURCE_HW', 'TB_ACR_SOURCE_SW', + 'TB_AUDIO_INFO_CONT_DISABLE', 'TB_AUDIO_INFO_CONT_ENABLE', + 'TB_AUDIO_INFO_NOT_SEND', 'TB_AUDIO_INFO_PKT_SEND', + 'TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT', + 'TB_BORROW_MODE_ACTIVE', 'TB_BORROW_MODE_BLANK', + 'TB_BORROW_MODE_NONE', 'TB_BORROW_MODE_RESERVED', + 'TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES', 'TB_CRC_ACTIVE_TRIBYTES', + 'TB_CRC_ALL_TRIBYTES', 'TB_CRC_DATAISLAND_TRIBYTES', + 'TB_CRC_DEEP_COLOR_PACKER', 'TB_CRC_DSC_PACKER', + 'TB_CRC_ENCRYPTOR_INPUT', 'TB_CRC_TB_ENC_INPUT', + 'TB_DEEP_COLOR_DEPTH_24BPP', 'TB_DEEP_COLOR_DEPTH_30BPP', + 'TB_DEEP_COLOR_DEPTH_36BPP', 'TB_DEEP_COLOR_DEPTH_RESERVED', + 'TB_DEFAULT_PHASE_IS_0', 'TB_DEFAULT_PHASE_IS_1', 'TB_DISABLE', + 'TB_DSC_444_RGB', 'TB_DSC_DISABLE', 'TB_DSC_NATIVE_422_420', + 'TB_ENABLE', 'TB_GC_AVMUTE_CONT_DISABLE', + 'TB_GC_AVMUTE_CONT_ENABLE', 'TB_GC_AVMUTE_SET', + 'TB_GC_AVMUTE_UNSET', 'TB_GC_CONT_DISABLE', 'TB_GC_CONT_ENABLE', + 'TB_GC_NOT_SEND', 'TB_GC_PKT_SEND', 'TB_GENERIC_CONT_DISABLE', + 'TB_GENERIC_CONT_ENABLE', 'TB_GENERIC_NOT_SEND', + 'TB_GENERIC_PKT_SEND', 'TB_ISRC_CONT_DISABLE', + 'TB_ISRC_CONT_ENABLE', 'TB_ISRC_NOT_SEND', 'TB_ISRC_PKT_SEND', + 'TB_METADATA_NOT_SEND', 'TB_METADATA_PKT_SEND', 'TB_NOT_RESET', + 'TB_NOT_SYNC_PHASE_ON_FRAME_START', 'TB_NO_ERROR_OCCURRED', + 'TB_OVERFLOW_OCCURRED', 'TB_PIXEL_ENCODING_420', + 'TB_PIXEL_ENCODING_422', 'TB_PIXEL_ENCODING_444_RGB', + 'TB_PKT_LINE_REF_END_OF_ACTIVE', 'TB_PKT_LINE_REF_OTGSOF', + 'TB_RESET', 'TB_SYNC_PHASE_ON_FRAME_START', 'TCC_CACHE_POLICIES', + 'TCC_CACHE_POLICY_LRU', 'TCC_CACHE_POLICY_STREAM', 'TCC_MTYPE', + 'TCP_CACHE_POLICIES', 'TCP_CACHE_POLICY_HIT_EVICT', + 'TCP_CACHE_POLICY_HIT_LRU', 'TCP_CACHE_POLICY_MISS_EVICT', + 'TCP_CACHE_POLICY_MISS_LRU', 'TCP_CACHE_STORE_POLICIES', + 'TCP_CACHE_STORE_POLICY_WT_EVICT', + 'TCP_CACHE_STORE_POLICY_WT_LRU', 'TCP_DSM_DATA_SEL', + 'TCP_DSM_DISABLE', 'TCP_DSM_INJECT_SEL', 'TCP_DSM_INJECT_SEL0', + 'TCP_DSM_INJECT_SEL1', 'TCP_DSM_INJECT_SEL2', + 'TCP_DSM_INJECT_SEL3', 'TCP_DSM_SEL0', 'TCP_DSM_SEL1', + 'TCP_DSM_SEL_BOTH', 'TCP_DSM_SINGLE_WRITE', + 'TCP_DSM_SINGLE_WRITE_DIS', 'TCP_DSM_SINGLE_WRITE_EN', + 'TCP_OPCODE_ATOMIC', 'TCP_OPCODE_ATOMIC_CMPSWAP', + 'TCP_OPCODE_GATHERH', 'TCP_OPCODE_INV', 'TCP_OPCODE_LOAD', + 'TCP_OPCODE_READ', 'TCP_OPCODE_SAMPLER', 'TCP_OPCODE_TYPE', + 'TCP_OPCODE_WRITE', 'TCP_PERFCOUNT_SELECT', + 'TCP_PERF_SEL_ALLOC_STALL', + 'TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL', + 'TCP_PERF_SEL_COMP_TEX_LOAD_STALL', + 'TCP_PERF_SEL_DATA_FIFO_STALL', 'TCP_PERF_SEL_GATE_EN1', + 'TCP_PERF_SEL_GATE_EN2', 'TCP_PERF_SEL_GL1_GRANT_READ_STALL', + 'TCP_PERF_SEL_GL1_PENDING_STALL', 'TCP_PERF_SEL_GL1_READ_LATENCY', + 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET', + 'TCP_PERF_SEL_GL1_REQ_READ', 'TCP_PERF_SEL_GL1_REQ_READ_128B', + 'TCP_PERF_SEL_GL1_REQ_READ_64B', 'TCP_PERF_SEL_GL1_REQ_WRITE', + 'TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE', + 'TCP_PERF_SEL_GL1_TCP_RDRET_STALL', + 'TCP_PERF_SEL_GL1_WRITE_LATENCY', 'TCP_PERF_SEL_LFIFO_STALL', + 'TCP_PERF_SEL_LOD_STALL', 'TCP_PERF_SEL_MEM_REQ_FIFO_STALL', + 'TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL', + 'TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL', 'TCP_PERF_SEL_POWER_STALL', + 'TCP_PERF_SEL_READ_DATACONFLICT_STALL', + 'TCP_PERF_SEL_READ_TAGCONFLICT_STALL', 'TCP_PERF_SEL_REQ', + 'TCP_PERF_SEL_REQ_MISS', 'TCP_PERF_SEL_REQ_MISS_TAGBANK0', + 'TCP_PERF_SEL_REQ_MISS_TAGBANK1', + 'TCP_PERF_SEL_REQ_MISS_TAGBANK2', + 'TCP_PERF_SEL_REQ_MISS_TAGBANK3', 'TCP_PERF_SEL_REQ_NON_READ', + 'TCP_PERF_SEL_REQ_READ', 'TCP_PERF_SEL_REQ_READ_HIT_EVICT', + 'TCP_PERF_SEL_REQ_READ_HIT_LRU', + 'TCP_PERF_SEL_REQ_READ_MISS_EVICT', + 'TCP_PERF_SEL_REQ_TAGBANK0_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK0_SET1', + 'TCP_PERF_SEL_REQ_TAGBANK1_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK1_SET1', + 'TCP_PERF_SEL_REQ_TAGBANK2_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK2_SET1', + 'TCP_PERF_SEL_REQ_TAGBANK3_SET0', + 'TCP_PERF_SEL_REQ_TAGBANK3_SET1', 'TCP_PERF_SEL_REQ_WRITE', + 'TCP_PERF_SEL_REQ_WRITE_MISS_EVICT', + 'TCP_PERF_SEL_REQ_WRITE_MISS_LRU', 'TCP_PERF_SEL_TA_REQ', + 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET', + 'TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET', + 'TCP_PERF_SEL_TA_REQ_GL0_INV', 'TCP_PERF_SEL_TA_REQ_READ', + 'TCP_PERF_SEL_TA_REQ_STATE_READ', 'TCP_PERF_SEL_TA_REQ_WRITE', + 'TCP_PERF_SEL_TA_TCP_REQ_STARVE', 'TCP_PERF_SEL_TCP_LATENCY', + 'TCP_PERF_SEL_TCP_TA_REQ_STALL', + 'TCP_PERF_SEL_TD_DATA_CYCLE_STALL', 'TCP_PERF_SEL_TD_TCP_STALL', + 'TCP_PERF_SEL_UNORDERED_MTYPE_STALL', + 'TCP_PERF_SEL_WRITE_DATACONFLICT_STALL', + 'TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL', 'TCP_WATCH_MODES', + 'TCP_WATCH_MODE_ALL', 'TCP_WATCH_MODE_ATOMIC', + 'TCP_WATCH_MODE_NONREAD', 'TCP_WATCH_MODE_READ', 'TC_EA_CID', + 'TC_EA_CID_CPF', 'TC_EA_CID_CPG', 'TC_EA_CID_DCC', + 'TC_EA_CID_FMASK', 'TC_EA_CID_HTILE', 'TC_EA_CID_IA', + 'TC_EA_CID_MISC', 'TC_EA_CID_PA', 'TC_EA_CID_RT', 'TC_EA_CID_SQC', + 'TC_EA_CID_STENCIL', 'TC_EA_CID_TCP', 'TC_EA_CID_TCPMETA', + 'TC_EA_CID_UTCL2_TPI', 'TC_EA_CID_WD', 'TC_EA_CID_Z', 'TC_NACKS', + 'TC_NACK_DATA_ERROR', 'TC_NACK_NO_FAULT', 'TC_NACK_PAGE_FAULT', + 'TC_NACK_PROTECTION_FAULT', 'TC_OP', 'TC_OP_ATOMIC_ADD_32', + 'TC_OP_ATOMIC_ADD_64', 'TC_OP_ATOMIC_ADD_RTN_32', + 'TC_OP_ATOMIC_ADD_RTN_64', 'TC_OP_ATOMIC_AND_32', + 'TC_OP_ATOMIC_AND_64', 'TC_OP_ATOMIC_AND_RTN_32', + 'TC_OP_ATOMIC_AND_RTN_64', 'TC_OP_ATOMIC_CMPSWAP_32', + 'TC_OP_ATOMIC_CMPSWAP_64', 'TC_OP_ATOMIC_CMPSWAP_RTN_32', + 'TC_OP_ATOMIC_CMPSWAP_RTN_64', 'TC_OP_ATOMIC_DEC_32', + 'TC_OP_ATOMIC_DEC_64', 'TC_OP_ATOMIC_DEC_RTN_32', + 'TC_OP_ATOMIC_DEC_RTN_64', 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FCMPSWAP_32', 'TC_OP_ATOMIC_FCMPSWAP_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FCMPSWAP_RTN_32', 'TC_OP_ATOMIC_FCMPSWAP_RTN_64', + 'TC_OP_ATOMIC_FMAX_32', 'TC_OP_ATOMIC_FMAX_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMAX_RTN_32', 'TC_OP_ATOMIC_FMAX_RTN_64', + 'TC_OP_ATOMIC_FMIN_32', 'TC_OP_ATOMIC_FMIN_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32', + 'TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64', + 'TC_OP_ATOMIC_FMIN_RTN_32', 'TC_OP_ATOMIC_FMIN_RTN_64', + 'TC_OP_ATOMIC_INC_32', 'TC_OP_ATOMIC_INC_64', + 'TC_OP_ATOMIC_INC_RTN_32', 'TC_OP_ATOMIC_INC_RTN_64', + 'TC_OP_ATOMIC_OR_32', 'TC_OP_ATOMIC_OR_64', + 'TC_OP_ATOMIC_OR_RTN_32', 'TC_OP_ATOMIC_OR_RTN_64', + 'TC_OP_ATOMIC_SMAX_32', 'TC_OP_ATOMIC_SMAX_64', + 'TC_OP_ATOMIC_SMAX_RTN_32', 'TC_OP_ATOMIC_SMAX_RTN_64', + 'TC_OP_ATOMIC_SMIN_32', 'TC_OP_ATOMIC_SMIN_64', + 'TC_OP_ATOMIC_SMIN_RTN_32', 'TC_OP_ATOMIC_SMIN_RTN_64', + 'TC_OP_ATOMIC_SUB_32', 'TC_OP_ATOMIC_SUB_64', + 'TC_OP_ATOMIC_SUB_RTN_32', 'TC_OP_ATOMIC_SUB_RTN_64', + 'TC_OP_ATOMIC_SWAP_32', 'TC_OP_ATOMIC_SWAP_64', + 'TC_OP_ATOMIC_SWAP_RTN_32', 'TC_OP_ATOMIC_SWAP_RTN_64', + 'TC_OP_ATOMIC_UMAX_32', 'TC_OP_ATOMIC_UMAX_64', + 'TC_OP_ATOMIC_UMAX_RTN_32', 'TC_OP_ATOMIC_UMAX_RTN_64', + 'TC_OP_ATOMIC_UMIN_32', 'TC_OP_ATOMIC_UMIN_64', + 'TC_OP_ATOMIC_UMIN_RTN_32', 'TC_OP_ATOMIC_UMIN_RTN_64', + 'TC_OP_ATOMIC_XOR_32', 'TC_OP_ATOMIC_XOR_64', + 'TC_OP_ATOMIC_XOR_RTN_32', 'TC_OP_ATOMIC_XOR_RTN_64', + 'TC_OP_INVL2_NC', 'TC_OP_INV_METADATA', 'TC_OP_MASKS', + 'TC_OP_MASK_64', 'TC_OP_MASK_FLUSH_DENROM', 'TC_OP_MASK_NO_RTN', + 'TC_OP_NOP_ACK', 'TC_OP_NOP_RTN0', 'TC_OP_PROBE_FILTER', + 'TC_OP_READ', 'TC_OP_RESERVED_FADD_32', + 'TC_OP_RESERVED_FADD_RTN_32', 'TC_OP_RESERVED_FOP_32_0', + 'TC_OP_RESERVED_FOP_32_2', 'TC_OP_RESERVED_FOP_64_0', + 'TC_OP_RESERVED_FOP_64_1', 'TC_OP_RESERVED_FOP_64_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0', + 'TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1', + 'TC_OP_RESERVED_FOP_RTN_32_0', 'TC_OP_RESERVED_FOP_RTN_32_2', + 'TC_OP_RESERVED_FOP_RTN_64_0', 'TC_OP_RESERVED_FOP_RTN_64_1', + 'TC_OP_RESERVED_FOP_RTN_64_2', 'TC_OP_RESERVED_NON_FLOAT_32_1', + 'TC_OP_RESERVED_NON_FLOAT_32_2', 'TC_OP_RESERVED_NON_FLOAT_32_3', + 'TC_OP_RESERVED_NON_FLOAT_32_4', 'TC_OP_RESERVED_NON_FLOAT_64_1', + 'TC_OP_RESERVED_NON_FLOAT_64_2', 'TC_OP_RESERVED_NON_FLOAT_64_3', + 'TC_OP_RESERVED_NON_FLOAT_64_4', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_0', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_32_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_1', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_2', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_3', + 'TC_OP_RESERVED_NON_FLOAT_RTN_64_4', 'TC_OP_WBINVL1', + 'TC_OP_WBINVL1_SD', 'TC_OP_WBINVL1_VOL', 'TC_OP_WBINVL2', + 'TC_OP_WBINVL2_NC', 'TC_OP_WBINVL2_SD', 'TC_OP_WBL2_NC', + 'TC_OP_WBL2_WC', 'TC_OP_WRITE', 'TD_PERFCOUNT_SEL', + 'TD_PERF_SEL_address_cmd_poison', + 'TD_PERF_SEL_all_pipes_sclk_on_at_same_time', + 'TD_PERF_SEL_blend_prt_with_prt_default_0', + 'TD_PERF_SEL_blend_prt_with_prt_default_1', + 'TD_PERF_SEL_bubble_bin_lds_stall_1to3', + 'TD_PERF_SEL_bubble_bin_lds_stall_4to7', + 'TD_PERF_SEL_bubble_bin_lds_stall_8to15', + 'TD_PERF_SEL_bubble_bin_lds_stall_gt15', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127', + 'TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511', + 'TD_PERF_SEL_burst_bin_bvh4_1', 'TD_PERF_SEL_burst_bin_bvh4_2to8', + 'TD_PERF_SEL_burst_bin_bvh4_9to16', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_1', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16', + 'TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16', + 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1', + 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8', + 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16', + 'TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16', + 'TD_PERF_SEL_burst_bin_bvh4_gt16', + 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1', + 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8', + 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16', + 'TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16', + 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1', + 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8', + 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16', + 'TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16', + 'TD_PERF_SEL_burst_bin_gather_1', + 'TD_PERF_SEL_burst_bin_gather_2to8', + 'TD_PERF_SEL_burst_bin_gather_9to16', + 'TD_PERF_SEL_burst_bin_gather_gt16', + 'TD_PERF_SEL_burst_bin_nofilter_1', + 'TD_PERF_SEL_burst_bin_nofilter_2to4', + 'TD_PERF_SEL_burst_bin_nofilter_5to7', + 'TD_PERF_SEL_burst_bin_nofilter_8to16', + 'TD_PERF_SEL_burst_bin_nofilter_gt16', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_1', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_2to4', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_5to7', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_8to16', + 'TD_PERF_SEL_burst_bin_preempting_nofilter_gt16', + 'TD_PERF_SEL_burst_bin_sampler_1', + 'TD_PERF_SEL_burst_bin_sampler_2to8', + 'TD_PERF_SEL_burst_bin_sampler_9to16', + 'TD_PERF_SEL_burst_bin_sampler_gt16', + 'TD_PERF_SEL_bypassLerp_instr', + 'TD_PERF_SEL_core_state_ram_max_cnt', + 'TD_PERF_SEL_core_state_rams_read', 'TD_PERF_SEL_d16_en_instr', + 'TD_PERF_SEL_data_poison', + 'TD_PERF_SEL_done_scoreboard_bp_due_to_lds', + 'TD_PERF_SEL_done_scoreboard_bp_due_to_ooo', + 'TD_PERF_SEL_done_scoreboard_is_full', + 'TD_PERF_SEL_done_scoreboard_max_stored_cnt', + 'TD_PERF_SEL_done_scoreboard_max_waiting_cnt', + 'TD_PERF_SEL_done_scoreboard_not_empty', + 'TD_PERF_SEL_four_comp_return_instr', 'TD_PERF_SEL_gather4_instr', + 'TD_PERF_SEL_gather4h_instr', + 'TD_PERF_SEL_input_bp_due_to_done_scoreboard_full', + 'TD_PERF_SEL_input_busy', 'TD_PERF_SEL_input_state_fifo_full', + 'TD_PERF_SEL_instruction_dest_is_lds', 'TD_PERF_SEL_ldfptr_instr', + 'TD_PERF_SEL_lds_stall', 'TD_PERF_SEL_load_instr', + 'TD_PERF_SEL_lod_warn_from_ta', + 'TD_PERF_SEL_min_max_filter_instr', 'TD_PERF_SEL_mixmode_instr', + 'TD_PERF_SEL_mixmode_resource', 'TD_PERF_SEL_msaa_load_instr', + 'TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off', + 'TD_PERF_SEL_nofilter_busy', + 'TD_PERF_SEL_nofilter_byte_cycling_16cycles', + 'TD_PERF_SEL_nofilter_byte_cycling_4cycles', + 'TD_PERF_SEL_nofilter_byte_cycling_8cycles', + 'TD_PERF_SEL_nofilter_d16_sclk_en', + 'TD_PERF_SEL_nofilter_d32_sclk_en', + 'TD_PERF_SEL_nofilter_dword_cycling_2cycles', + 'TD_PERF_SEL_nofilter_dword_cycling_4cycles', + 'TD_PERF_SEL_nofilter_formatters_turned_on', + 'TD_PERF_SEL_nofilter_insert_extra_comps', + 'TD_PERF_SEL_nofilter_pkr_full', + 'TD_PERF_SEL_nofilter_pkr_full_due_to_arb', + 'TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt', + 'TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt', + 'TD_PERF_SEL_nofilter_sclk_en', + 'TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off', + 'TD_PERF_SEL_nofilter_total_num_comps_to_lds', 'TD_PERF_SEL_none', + 'TD_PERF_SEL_one_comp_return_instr', + 'TD_PERF_SEL_opaque_black_border', + 'TD_PERF_SEL_out_of_order_instr', + 'TD_PERF_SEL_preempting_nofilter_max_cnt', + 'TD_PERF_SEL_prt_ack_instr', + 'TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero', + 'TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en', + 'TD_PERF_SEL_ray_tracing_bvh4_box_sort_en', + 'TD_PERF_SEL_ray_tracing_bvh4_busy', + 'TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node', + 'TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node', + 'TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node', + 'TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node', + 'TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt', + 'TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node', + 'TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node', + 'TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en', + 'TD_PERF_SEL_ray_tracing_bvh4_num_box_misses', + 'TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan', + 'TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx', + 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses', + 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers', + 'TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx', + 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full', + 'TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb', + 'TD_PERF_SEL_ray_tracing_bvh4_sclk_en', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8', + 'TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16', + 'TD_PERF_SEL_ray_tracing_bvh4_tri_node', + 'TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en', + 'TD_PERF_SEL_reference_data_rams_read', + 'TD_PERF_SEL_resmap_instr', + 'TD_PERF_SEL_resmap_with_aniso_filtering', + 'TD_PERF_SEL_resmap_with_cubemap_corner', + 'TD_PERF_SEL_resmap_with_no_more_filtering', + 'TD_PERF_SEL_resmap_with_volume_filtering', + 'TD_PERF_SEL_sample_c_instr', 'TD_PERF_SEL_sample_instr', + 'TD_PERF_SEL_sampler_accum_sclk_en', + 'TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off', + 'TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off', + 'TD_PERF_SEL_sampler_bilerp_sclk_en', + 'TD_PERF_SEL_sampler_bypass_sclk_en', + 'TD_PERF_SEL_sampler_core_sclk_en', + 'TD_PERF_SEL_sampler_format_flt_sclk_en', + 'TD_PERF_SEL_sampler_format_fxdpt_sclk_en', + 'TD_PERF_SEL_sampler_lerp0_active', + 'TD_PERF_SEL_sampler_lerp1_active', + 'TD_PERF_SEL_sampler_lerp2_active', + 'TD_PERF_SEL_sampler_lerp3_active', + 'TD_PERF_SEL_sampler_lerp_busy', + 'TD_PERF_SEL_sampler_minmax_sclk_en', + 'TD_PERF_SEL_sampler_out_busy', 'TD_PERF_SEL_sampler_out_sclk_en', + 'TD_PERF_SEL_sampler_pkr_full', + 'TD_PERF_SEL_sampler_pkr_full_due_to_arb', + 'TD_PERF_SEL_sampler_preformatter_sclk_en', + 'TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off', + 'TD_PERF_SEL_status_packet', 'TD_PERF_SEL_ta_data_stall', + 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles', + 'TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles', + 'TD_PERF_SEL_tc_data_stall', 'TD_PERF_SEL_tc_ram_stall', + 'TD_PERF_SEL_tc_td_data_fifo_full', + 'TD_PERF_SEL_tc_td_ram_fifo_full', + 'TD_PERF_SEL_tc_td_ram_fifo_max_cnt', 'TD_PERF_SEL_td_busy', + 'TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles', + 'TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles', + 'TD_PERF_SEL_three_comp_return_instr', + 'TD_PERF_SEL_total_num_instr', + 'TD_PERF_SEL_total_num_instr_with_perf_wdw', + 'TD_PERF_SEL_total_num_nofilter_instr', + 'TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw', + 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr', + 'TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw', + 'TD_PERF_SEL_total_num_sampler_instr', + 'TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw', + 'TD_PERF_SEL_two_comp_return_instr', + 'TD_PERF_SEL_user_defined_border', + 'TD_PERF_SEL_weight_data_rams_read', 'TD_PERF_SEL_white_border', + 'TD_PERF_SEL_write_ack_instr', 'TESS_ISOLINE', 'TESS_QUAD', + 'TESS_TRIANGLE', 'TEST_CLK_DIV_SEL', 'TEST_CLK_SEL', + 'TEST_CLK_SEL_0', 'TEST_CLK_SEL_1', 'TEST_CLK_SEL_2', + 'TEST_CLK_SEL_3', 'TEST_CLK_SEL_4', 'TEST_CLK_SEL_5', + 'TEST_CLK_SEL_6', 'TEST_CLK_SEL_7', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_G', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_P', + 'TEST_CLOCK_MUX_SELECT_DISPCLK_R', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_G', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_P', + 'TEST_CLOCK_MUX_SELECT_DSCCLK_R', 'TEST_CLOCK_MUX_SELECT_ENUM', + 'TEX_BC_SWIZZLE', 'TEX_BC_Swizzle_WXYZ', 'TEX_BC_Swizzle_WZYX', + 'TEX_BC_Swizzle_XWYZ', 'TEX_BC_Swizzle_XYZW', + 'TEX_BC_Swizzle_YXWZ', 'TEX_BC_Swizzle_ZYXW', + 'TEX_BORDER_COLOR_TYPE', 'TEX_BorderColor_OpaqueBlack', + 'TEX_BorderColor_OpaqueWhite', 'TEX_BorderColor_Register', + 'TEX_BorderColor_TransparentBlack', 'TEX_CHROMA_KEY', 'TEX_CLAMP', + 'TEX_COORD_TYPE', 'TEX_ChromaKey_Blend', 'TEX_ChromaKey_Disabled', + 'TEX_ChromaKey_Kill', 'TEX_ChromaKey_RESERVED_3', + 'TEX_Clamp_ClampHalfToBorder', 'TEX_Clamp_ClampToBorder', + 'TEX_Clamp_ClampToLast', 'TEX_Clamp_Mirror', + 'TEX_Clamp_MirrorOnceHalfToBorder', + 'TEX_Clamp_MirrorOnceToBorder', 'TEX_Clamp_MirrorOnceToLast', + 'TEX_Clamp_Repeat', 'TEX_CoordType_Normalized', + 'TEX_CoordType_Unnormalized', 'TEX_DEPTH_COMPARE_FUNCTION', + 'TEX_DepthCompareFunction_Always', + 'TEX_DepthCompareFunction_Equal', + 'TEX_DepthCompareFunction_Greater', + 'TEX_DepthCompareFunction_GreaterEqual', + 'TEX_DepthCompareFunction_Less', + 'TEX_DepthCompareFunction_LessEqual', + 'TEX_DepthCompareFunction_Never', + 'TEX_DepthCompareFunction_NotEqual', 'TEX_FORMAT_COMP', + 'TEX_FormatComp_RESERVED_3', 'TEX_FormatComp_Signed', + 'TEX_FormatComp_Unsigned', 'TEX_FormatComp_UnsignedBiased', + 'TEX_MAX_ANISO_RATIO', 'TEX_MIP_FILTER', + 'TEX_MaxAnisoRatio_16to1', 'TEX_MaxAnisoRatio_1to1', + 'TEX_MaxAnisoRatio_2to1', 'TEX_MaxAnisoRatio_4to1', + 'TEX_MaxAnisoRatio_8to1', 'TEX_MaxAnisoRatio_RESERVED_5', + 'TEX_MaxAnisoRatio_RESERVED_6', 'TEX_MaxAnisoRatio_RESERVED_7', + 'TEX_MipFilter_Linear', 'TEX_MipFilter_None', + 'TEX_MipFilter_Point', 'TEX_MipFilter_Point_Aniso_Adj', + 'TEX_REQUEST_SIZE', 'TEX_RequestSize_128B', + 'TEX_RequestSize_2X64B', 'TEX_RequestSize_32B', + 'TEX_RequestSize_64B', 'TEX_SAMPLER_TYPE', + 'TEX_SamplerType_Invalid', 'TEX_SamplerType_Valid', + 'TEX_XYFilter_AnisoLinear', 'TEX_XYFilter_AnisoPoint', + 'TEX_XYFilter_Linear', 'TEX_XYFilter_Point', 'TEX_XY_FILTER', + 'TEX_ZFilter_Linear', 'TEX_ZFilter_None', 'TEX_ZFilter_Point', + 'TEX_ZFilter_RESERVED_3', 'TEX_Z_FILTER', 'TGID_ROLLOVER', + 'THM_BASE', 'THM_BASE__INST0_SEG0', 'THM_BASE__INST0_SEG1', + 'THM_BASE__INST0_SEG2', 'THM_BASE__INST0_SEG3', + 'THM_BASE__INST0_SEG4', 'THM_BASE__INST1_SEG0', + 'THM_BASE__INST1_SEG1', 'THM_BASE__INST1_SEG2', + 'THM_BASE__INST1_SEG3', 'THM_BASE__INST1_SEG4', + 'THM_BASE__INST2_SEG0', 'THM_BASE__INST2_SEG1', + 'THM_BASE__INST2_SEG2', 'THM_BASE__INST2_SEG3', + 'THM_BASE__INST2_SEG4', 'THM_BASE__INST3_SEG0', + 'THM_BASE__INST3_SEG1', 'THM_BASE__INST3_SEG2', + 'THM_BASE__INST3_SEG3', 'THM_BASE__INST3_SEG4', + 'THM_BASE__INST4_SEG0', 'THM_BASE__INST4_SEG1', + 'THM_BASE__INST4_SEG2', 'THM_BASE__INST4_SEG3', + 'THM_BASE__INST4_SEG4', 'THM_BASE__INST5_SEG0', + 'THM_BASE__INST5_SEG1', 'THM_BASE__INST5_SEG2', + 'THM_BASE__INST5_SEG3', 'THM_BASE__INST5_SEG4', + 'THM_BASE__INST6_SEG0', 'THM_BASE__INST6_SEG1', + 'THM_BASE__INST6_SEG2', 'THM_BASE__INST6_SEG3', + 'THM_BASE__INST6_SEG4', 'THREAD_TRACE_DRAW', + 'THREAD_TRACE_FINISH', 'THREAD_TRACE_MARKER', + 'THREAD_TRACE_START', 'THREAD_TRACE_STOP', 'TIGHT_PACK', + 'TMDS_COLOR_FORMAT', 'TMDS_COLOR_FORMAT_DUAL30BPP', + 'TMDS_COLOR_FORMAT_RESERVED', 'TMDS_COLOR_FORMAT_TWIN30BPP_LSB', + 'TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP', + 'TMDS_CTL0_DATA_INVERT', 'TMDS_CTL0_DATA_INVERT_EN', + 'TMDS_CTL0_DATA_MODULATION', 'TMDS_CTL0_DATA_MODULATION_BIT0', + 'TMDS_CTL0_DATA_MODULATION_BIT1', + 'TMDS_CTL0_DATA_MODULATION_BIT2', + 'TMDS_CTL0_DATA_MODULATION_DISABLE', 'TMDS_CTL0_DATA_NORMAL', + 'TMDS_CTL0_DATA_SEL', 'TMDS_CTL0_DATA_SEL0_RESERVED', + 'TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL0_DATA_SEL2_VSYNC', + 'TMDS_CTL0_DATA_SEL3_RESERVED', 'TMDS_CTL0_DATA_SEL4_HSYNC', + 'TMDS_CTL0_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL0_DATA_SEL8_RANDOM_DATA', + 'TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA', + 'TMDS_CTL0_PATTERN_OUT_DISABLE', 'TMDS_CTL0_PATTERN_OUT_EN', + 'TMDS_CTL0_PATTERN_OUT_ENABLE', 'TMDS_CTL1_DATA_INVERT', + 'TMDS_CTL1_DATA_INVERT_EN', 'TMDS_CTL1_DATA_MODULATION', + 'TMDS_CTL1_DATA_MODULATION_BIT0', + 'TMDS_CTL1_DATA_MODULATION_BIT1', + 'TMDS_CTL1_DATA_MODULATION_BIT2', + 'TMDS_CTL1_DATA_MODULATION_DISABLE', 'TMDS_CTL1_DATA_NORMAL', + 'TMDS_CTL1_DATA_SEL', 'TMDS_CTL1_DATA_SEL0_RESERVED', + 'TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL1_DATA_SEL2_VSYNC', + 'TMDS_CTL1_DATA_SEL3_RESERVED', 'TMDS_CTL1_DATA_SEL4_HSYNC', + 'TMDS_CTL1_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL1_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL1_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL1_PATTERN_OUT_DISABLE', 'TMDS_CTL1_PATTERN_OUT_EN', + 'TMDS_CTL1_PATTERN_OUT_ENABLE', 'TMDS_CTL2_DATA_INVERT', + 'TMDS_CTL2_DATA_INVERT_EN', 'TMDS_CTL2_DATA_MODULATION', + 'TMDS_CTL2_DATA_MODULATION_BIT0', + 'TMDS_CTL2_DATA_MODULATION_BIT1', + 'TMDS_CTL2_DATA_MODULATION_BIT2', + 'TMDS_CTL2_DATA_MODULATION_DISABLE', 'TMDS_CTL2_DATA_NORMAL', + 'TMDS_CTL2_DATA_SEL', 'TMDS_CTL2_DATA_SEL0_RESERVED', + 'TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL2_DATA_SEL2_VSYNC', + 'TMDS_CTL2_DATA_SEL3_RESERVED', 'TMDS_CTL2_DATA_SEL4_HSYNC', + 'TMDS_CTL2_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL2_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL2_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL2_PATTERN_OUT_DISABLE', 'TMDS_CTL2_PATTERN_OUT_EN', + 'TMDS_CTL2_PATTERN_OUT_ENABLE', 'TMDS_CTL3_DATA_INVERT', + 'TMDS_CTL3_DATA_INVERT_EN', 'TMDS_CTL3_DATA_MODULATION', + 'TMDS_CTL3_DATA_MODULATION_BIT0', + 'TMDS_CTL3_DATA_MODULATION_BIT1', + 'TMDS_CTL3_DATA_MODULATION_BIT2', + 'TMDS_CTL3_DATA_MODULATION_DISABLE', 'TMDS_CTL3_DATA_NORMAL', + 'TMDS_CTL3_DATA_SEL', 'TMDS_CTL3_DATA_SEL0_RESERVED', + 'TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE', 'TMDS_CTL3_DATA_SEL2_VSYNC', + 'TMDS_CTL3_DATA_SEL3_RESERVED', 'TMDS_CTL3_DATA_SEL4_HSYNC', + 'TMDS_CTL3_DATA_SEL5_SEL7_RESERVED', + 'TMDS_CTL3_DATA_SEL8_BLANK_TIME', + 'TMDS_CTL3_DATA_SEL9_SEL15_RESERVED', + 'TMDS_CTL3_PATTERN_OUT_DISABLE', 'TMDS_CTL3_PATTERN_OUT_EN', + 'TMDS_CTL3_PATTERN_OUT_ENABLE', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS', + 'TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL', 'TMDS_MUX_SELECT', + 'TMDS_MUX_SELECT_B', 'TMDS_MUX_SELECT_G', 'TMDS_MUX_SELECT_R', + 'TMDS_MUX_SELECT_RESERVED', 'TMDS_NOT_SYNC_PHASE_ON_FRAME_START', + 'TMDS_PIXEL_ENCODING', 'TMDS_PIXEL_ENCODING_422', + 'TMDS_PIXEL_ENCODING_444_OR_420', 'TMDS_REG_TEST_OUTPUTA_CNTLA', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_NA', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1', + 'TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2', + 'TMDS_REG_TEST_OUTPUTB_CNTLB', 'TMDS_REG_TEST_OUTPUTB_CNTLB_NA', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1', + 'TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2', 'TMDS_STEREOSYNC_CTL0', + 'TMDS_STEREOSYNC_CTL1', 'TMDS_STEREOSYNC_CTL2', + 'TMDS_STEREOSYNC_CTL3', 'TMDS_STEREOSYNC_CTL_SEL_REG', + 'TMDS_SYNC_PHASE', 'TMDS_SYNC_PHASE_ON_FRAME_START', + 'TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT', + 'TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA', + 'TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELA', + 'TMDS_TRANSMITTER_CONTROL_IDSCKSELB', + 'TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN', + 'TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK', + 'TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_ENABLE_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK', + 'TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK', + 'TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON', + 'TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK', + 'TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE', + 'TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE', + 'TMDS_TRANSMITTER_PLLSEL_BY_HW', + 'TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW', + 'TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE', + 'TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE', + 'TMDS_TRANSMITTER_PLL_RST_ON_HPD', + 'TMDS_TRANSMITTER_TDCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK', + 'TMDS_TRANSMITTER_TMCLK_FROM_PADS', + 'TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK', 'TRANSERR', + 'TRANSFERRED_1024_BYTES', 'TRANSFERRED_128_BYTES', + 'TRANSFERRED_2048_BYTES', 'TRANSFERRED_256_BYTES', + 'TRANSFERRED_4096_BYTES', 'TRANSFERRED_512_BYTES', + 'TRANSFERRED_64_BYTES', 'TRANSFERRED_8192_BYTES', 'TRAPEZOIDS', + 'TRISTRIP', 'TVX_TYPE', 'TVX_Type_InvalidTextureResource', + 'TVX_Type_InvalidVertexBuffer', 'TVX_Type_ValidTextureResource', + 'TVX_Type_ValidVertexBuffer', 'UCONFIG_SPACE_END', + 'UCONFIG_SPACE_START', 'UMC_BASE', 'UMC_BASE__INST0_SEG0', + 'UMC_BASE__INST0_SEG1', 'UMC_BASE__INST0_SEG2', + 'UMC_BASE__INST0_SEG3', 'UMC_BASE__INST0_SEG4', + 'UMC_BASE__INST1_SEG0', 'UMC_BASE__INST1_SEG1', + 'UMC_BASE__INST1_SEG2', 'UMC_BASE__INST1_SEG3', + 'UMC_BASE__INST1_SEG4', 'UMC_BASE__INST2_SEG0', + 'UMC_BASE__INST2_SEG1', 'UMC_BASE__INST2_SEG2', + 'UMC_BASE__INST2_SEG3', 'UMC_BASE__INST2_SEG4', + 'UMC_BASE__INST3_SEG0', 'UMC_BASE__INST3_SEG1', + 'UMC_BASE__INST3_SEG2', 'UMC_BASE__INST3_SEG3', + 'UMC_BASE__INST3_SEG4', 'UMC_BASE__INST4_SEG0', + 'UMC_BASE__INST4_SEG1', 'UMC_BASE__INST4_SEG2', + 'UMC_BASE__INST4_SEG3', 'UMC_BASE__INST4_SEG4', + 'UMC_BASE__INST5_SEG0', 'UMC_BASE__INST5_SEG1', + 'UMC_BASE__INST5_SEG2', 'UMC_BASE__INST5_SEG3', + 'UMC_BASE__INST5_SEG4', 'UMC_BASE__INST6_SEG0', + 'UMC_BASE__INST6_SEG1', 'UMC_BASE__INST6_SEG2', + 'UMC_BASE__INST6_SEG3', 'UMC_BASE__INST6_SEG4', 'UNDEF', + 'UNSIGNED', 'USB0_BASE', 'USB0_BASE__INST0_SEG0', 'USB0_BASE__INST0_SEG1', 'USB0_BASE__INST0_SEG2', 'USB0_BASE__INST0_SEG3', 'USB0_BASE__INST0_SEG4', 'USB0_BASE__INST1_SEG0', 'USB0_BASE__INST1_SEG1', @@ -14302,28 +73131,361 @@ __all__ = \ 'USB0_BASE__INST5_SEG2', 'USB0_BASE__INST5_SEG3', 'USB0_BASE__INST5_SEG4', 'USB0_BASE__INST6_SEG0', 'USB0_BASE__INST6_SEG1', 'USB0_BASE__INST6_SEG2', - 'USB0_BASE__INST6_SEG3', 'USB0_BASE__INST6_SEG4', 'VCN_BASE', - 'VCN_BASE__INST0_SEG0', 'VCN_BASE__INST0_SEG1', - 'VCN_BASE__INST0_SEG2', 'VCN_BASE__INST0_SEG3', - 'VCN_BASE__INST0_SEG4', 'VCN_BASE__INST1_SEG0', - 'VCN_BASE__INST1_SEG1', 'VCN_BASE__INST1_SEG2', - 'VCN_BASE__INST1_SEG3', 'VCN_BASE__INST1_SEG4', - 'VCN_BASE__INST2_SEG0', 'VCN_BASE__INST2_SEG1', - 'VCN_BASE__INST2_SEG2', 'VCN_BASE__INST2_SEG3', - 'VCN_BASE__INST2_SEG4', 'VCN_BASE__INST3_SEG0', - 'VCN_BASE__INST3_SEG1', 'VCN_BASE__INST3_SEG2', - 'VCN_BASE__INST3_SEG3', 'VCN_BASE__INST3_SEG4', - 'VCN_BASE__INST4_SEG0', 'VCN_BASE__INST4_SEG1', - 'VCN_BASE__INST4_SEG2', 'VCN_BASE__INST4_SEG3', - 'VCN_BASE__INST4_SEG4', 'VCN_BASE__INST5_SEG0', - 'VCN_BASE__INST5_SEG1', 'VCN_BASE__INST5_SEG2', - 'VCN_BASE__INST5_SEG3', 'VCN_BASE__INST5_SEG4', - 'VCN_BASE__INST6_SEG0', 'VCN_BASE__INST6_SEG1', - 'VCN_BASE__INST6_SEG2', 'VCN_BASE__INST6_SEG3', - 'VCN_BASE__INST6_SEG4', 'WR_CONFIRM', 'WR_ONE_ADDR', - '__maybe_unused', '_gc_11_0_0_OFFSET_HEADER', - '_sienna_cichlid_ip_offset_HEADER', 'hdp_flush_cmd', - 'ixFIXED_PATTERN_PERF_COUNTER_1', + 'USB0_BASE__INST6_SEG3', 'USB0_BASE__INST6_SEG4', + 'USE_MALL_FOR_CURSOR', 'USE_MALL_FOR_CURSOR_0', + 'USE_MALL_FOR_CURSOR_1', 'USE_MALL_FOR_PSTATE_CHANGE', + 'USE_MALL_FOR_PSTATE_CHANGE_0', 'USE_MALL_FOR_PSTATE_CHANGE_1', + 'USE_MALL_FOR_STATIC_SCREEN', 'USE_MALL_FOR_STATIC_SCREEN_0', + 'USE_MALL_FOR_STATIC_SCREEN_1', 'UTCL0FaultType', + 'UTCL0RequestType', 'UTCL0_TYPE_BYPASS', 'UTCL0_TYPE_NORMAL', + 'UTCL0_TYPE_SHOOTDOWN', 'UTCL0_XNACK_NO_RETRY', 'UTCL0_XNACK_PRT', + 'UTCL0_XNACK_RETRY', 'UTCL0_XNACK_SUCCESS', 'UTCL1FaultType', + 'UTCL1PerfSel', 'UTCL1RequestType', 'UTCL1_PERF_SEL_BYPASS_REQS', + 'UTCL1_PERF_SEL_CP_INVREQS', 'UTCL1_PERF_SEL_HITS', + 'UTCL1_PERF_SEL_HIT_INV_FILTER_REQS', + 'UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS', + 'UTCL1_PERF_SEL_MH_DUPLICATE_DETECT', + 'UTCL1_PERF_SEL_MH_RECENT_BUF_HIT', 'UTCL1_PERF_SEL_MISSES', + 'UTCL1_PERF_SEL_NONE', 'UTCL1_PERF_SEL_RANGE_INVREQS', + 'UTCL1_PERF_SEL_REQS', 'UTCL1_PERF_SEL_RTNS', + 'UTCL1_PERF_SEL_STALL_MH_FULL', + 'UTCL1_PERF_SEL_STALL_UTCL2_CREDITS', 'UTCL1_PERF_SEL_UTCL2_REQS', + 'UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM', + 'UTCL1_PERF_SEL_UTCL2_RET_CNT', 'UTCL1_PERF_SEL_UTCL2_RET_FAULT', + 'UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT', + 'UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT', + 'UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY', + 'UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS', + 'UTCL1_PERF_SEL_XLAT_REQ_BUSY', 'UTCL1_TYPE_BYPASS', + 'UTCL1_TYPE_NORMAL', 'UTCL1_TYPE_SHOOTDOWN', + 'UTCL1_XNACK_NO_RETRY', 'UTCL1_XNACK_PRT', 'UTCL1_XNACK_RETRY', + 'UTCL1_XNACK_SUCCESS', 'VCN_BASE', 'VCN_BASE__INST0_SEG0', + 'VCN_BASE__INST0_SEG1', 'VCN_BASE__INST0_SEG2', + 'VCN_BASE__INST0_SEG3', 'VCN_BASE__INST0_SEG4', + 'VCN_BASE__INST1_SEG0', 'VCN_BASE__INST1_SEG1', + 'VCN_BASE__INST1_SEG2', 'VCN_BASE__INST1_SEG3', + 'VCN_BASE__INST1_SEG4', 'VCN_BASE__INST2_SEG0', + 'VCN_BASE__INST2_SEG1', 'VCN_BASE__INST2_SEG2', + 'VCN_BASE__INST2_SEG3', 'VCN_BASE__INST2_SEG4', + 'VCN_BASE__INST3_SEG0', 'VCN_BASE__INST3_SEG1', + 'VCN_BASE__INST3_SEG2', 'VCN_BASE__INST3_SEG3', + 'VCN_BASE__INST3_SEG4', 'VCN_BASE__INST4_SEG0', + 'VCN_BASE__INST4_SEG1', 'VCN_BASE__INST4_SEG2', + 'VCN_BASE__INST4_SEG3', 'VCN_BASE__INST4_SEG4', + 'VCN_BASE__INST5_SEG0', 'VCN_BASE__INST5_SEG1', + 'VCN_BASE__INST5_SEG2', 'VCN_BASE__INST5_SEG3', + 'VCN_BASE__INST5_SEG4', 'VCN_BASE__INST6_SEG0', + 'VCN_BASE__INST6_SEG1', 'VCN_BASE__INST6_SEG2', + 'VCN_BASE__INST6_SEG3', 'VCN_BASE__INST6_SEG4', 'VGT_DETECT_ONE', + 'VGT_DETECT_ZERO', 'VGT_DIST_MODE', 'VGT_DI_INDEX_SIZE', + 'VGT_DI_MAJOR_MODE_SELECT', 'VGT_DI_PRIM_TYPE', + 'VGT_DI_SOURCE_SELECT', 'VGT_DMA_BUF_MEM', 'VGT_DMA_BUF_RING', + 'VGT_DMA_BUF_SETUP', 'VGT_DMA_BUF_TYPE', 'VGT_DMA_PTR_UPDATE', + 'VGT_DMA_SWAP_16_BIT', 'VGT_DMA_SWAP_32_BIT', 'VGT_DMA_SWAP_MODE', + 'VGT_DMA_SWAP_NONE', 'VGT_DMA_SWAP_WORD', 'VGT_EVENT_TYPE', + 'VGT_FLUSH', 'VGT_GROUP_CONV_SEL', 'VGT_GRP_AUTO_PRIM', + 'VGT_GRP_FIX_1_23_TO_FLOAT', 'VGT_GRP_FLOAT_32', + 'VGT_GRP_INDEX_16', 'VGT_GRP_INDEX_32', 'VGT_GRP_SINT_16', + 'VGT_GRP_SINT_32', 'VGT_GRP_UINT_16', 'VGT_GRP_UINT_32', + 'VGT_GS_MODE_TYPE', 'VGT_GS_OUTPRIM_TYPE', 'VGT_INDEX_16', + 'VGT_INDEX_32', 'VGT_INDEX_8', 'VGT_INDEX_TYPE_MODE', + 'VGT_OUTPATH_GS_BLOCK', 'VGT_OUTPATH_HS_BLOCK', + 'VGT_OUTPATH_PRIM_GEN', 'VGT_OUTPATH_SELECT', + 'VGT_OUTPATH_TE_GS_BLOCK', 'VGT_OUTPATH_TE_OUTPUT', + 'VGT_OUTPATH_TE_PRIM_GEN', 'VGT_OUTPATH_VTX_REUSE', + 'VGT_OUT_2D_RECT', 'VGT_OUT_LINE', 'VGT_OUT_LINE_ADJ', + 'VGT_OUT_PATCH', 'VGT_OUT_POINT', 'VGT_OUT_PRIM_TYPE', + 'VGT_OUT_RECT_V0', 'VGT_OUT_RECT_V1', 'VGT_OUT_RECT_V2', + 'VGT_OUT_RECT_V3', 'VGT_OUT_TRI', 'VGT_OUT_TRI_ADJ', + 'VGT_POLICY_BYPASS', 'VGT_POLICY_LRU', 'VGT_POLICY_STREAM', + 'VGT_RDREQ_POLICY', 'VGT_STAGES_ES_EN', 'VGT_STAGES_GS_EN', + 'VGT_STAGES_HS_EN', 'VGT_STAGES_LS_EN', 'VGT_STAGES_VS_EN', + 'VGT_STREAMOUT_RESET', 'VGT_STREAMOUT_SYNC', 'VGT_TESS_PARTITION', + 'VGT_TESS_TOPOLOGY', 'VGT_TESS_TYPE', 'VGT_TE_PRIM_INDEX_LINE', + 'VGT_TE_PRIM_INDEX_QUAD', 'VGT_TE_PRIM_INDEX_TRI', 'VGT_TE_QUAD', + 'VID_ENHANCED_MODE', 'VID_NORMAL_FRAME_MODE', + 'VID_STREAM_DISABLE_MASKED', 'VID_STREAM_DISABLE_UNMASK', + 'VMEMCMD_RETURN_IN_ORDER', 'VMEMCMD_RETURN_IN_ORDER_READ', + 'VMEMCMD_RETURN_ORDER', 'VMEMCMD_RETURN_OUT_OF_ORDER', 'VMID_SZ', + 'VMPG_SIZE', 'VMPG_SIZE_4KB', 'VMPG_SIZE_64KB', 'VM_GROUP_SIZE', + 'VM_GROUP_SIZE_1024B', 'VM_GROUP_SIZE_128B', + 'VM_GROUP_SIZE_2048B', 'VM_GROUP_SIZE_256B', 'VM_GROUP_SIZE_512B', + 'VM_GROUP_SIZE_64B', 'VM_PG_SIZE_1024KB', 'VM_PG_SIZE_128KB', + 'VM_PG_SIZE_16KB', 'VM_PG_SIZE_2048KB', 'VM_PG_SIZE_256KB', + 'VM_PG_SIZE_32KB', 'VM_PG_SIZE_4KB', 'VM_PG_SIZE_512KB', + 'VM_PG_SIZE_64KB', 'VM_PG_SIZE_8KB', + 'VPG_MEM_DISABLE_MEM_PWR_CTRL', 'VPG_MEM_ENABLE_MEM_PWR_CTRL', + 'VPG_MEM_FORCE_LIGHT_SLEEP_REQ', 'VPG_MEM_NO_FORCE_REQ', + 'VPG_MEM_PWR_DIS_CTRL', 'VPG_MEM_PWR_FORCE_CTRL', + 'VREADY_AT_OR_AFTER_VSYNC', 'VREADY_BEFORE_VSYNC', + 'VRSCombinerModeSC', 'VRS_SHADING_RATE_16X_SSAA', + 'VRS_SHADING_RATE_1X1', 'VRS_SHADING_RATE_1X2', + 'VRS_SHADING_RATE_2X1', 'VRS_SHADING_RATE_2X2', + 'VRS_SHADING_RATE_2X4', 'VRS_SHADING_RATE_2X_SSAA', + 'VRS_SHADING_RATE_4X2', 'VRS_SHADING_RATE_4X4', + 'VRS_SHADING_RATE_4X_SSAA', 'VRS_SHADING_RATE_8X_SSAA', + 'VRS_SHADING_RATE_UNDEFINED0', 'VRS_SHADING_RATE_UNDEFINED1', + 'VRS_SHADING_RATE_UNDEFINED2', 'VRS_SHADING_RATE_UNDEFINED3', + 'VRS_SHADING_RATE_UNDEFINED4', 'VRSrate', 'VSYNC_CNT_LATCH_MASK', + 'VSYNC_CNT_LATCH_MASK_0', 'VSYNC_CNT_LATCH_MASK_1', + 'VSYNC_CNT_RESET_SEL', 'VSYNC_CNT_RESET_SEL_0', + 'VSYNC_CNT_RESET_SEL_1', 'VS_PARTIAL_FLUSH', + 'VS_STAGE_COPY_SHADER', 'VS_STAGE_DS', 'VS_STAGE_REAL', + 'VTG_SEL_0', 'VTG_SEL_1', 'VTG_SEL_2', 'VTG_SEL_3', 'VTG_SEL_4', + 'VTG_SEL_5', 'WAIT_SYNC', 'WATERMARK_MODE', 'WD_IA_DRAW_REG_XFER', + 'WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC', + 'WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE', + 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM', + 'WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1', + 'WD_IA_DRAW_REG_XFER_GE_CNTL', + 'WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN', + 'WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM', + 'WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID', + 'WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN', + 'WD_IA_DRAW_SOURCE', 'WD_IA_DRAW_SOURCE_AUTO', + 'WD_IA_DRAW_SOURCE_DMA', 'WD_IA_DRAW_SOURCE_IMMD', + 'WD_IA_DRAW_SOURCE_OPAQ', 'WD_IA_DRAW_TYPE', + 'WD_IA_DRAW_TYPE_DI_MM0', 'WD_IA_DRAW_TYPE_EVENT_ADDR', + 'WD_IA_DRAW_TYPE_EVENT_INIT', 'WD_IA_DRAW_TYPE_IMM_DATA', + 'WD_IA_DRAW_TYPE_INDX_OFF', 'WD_IA_DRAW_TYPE_MAX_INDX', + 'WD_IA_DRAW_TYPE_MIN_INDX', 'WD_IA_DRAW_TYPE_REG_XFER', + 'WRITE_BASE_ONLY', 'WRITE_BOTH', 'WRITE_DATA_addr_incr_enum', + 'WRITE_DATA_cache_policy_enum', 'WRITE_DATA_dst_sel_enum', + 'WRITE_DATA_wr_confirm_enum', 'WR_CONFIRM', 'WR_ONE_ADDR', + 'WritePolicy', 'XNORM', 'XNORM_A', 'XNORM_B', + 'XTAL_REF_CLOCK_SOURCE_SEL', + 'XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK', + 'XTAL_REF_CLOCK_SOURCE_SEL_XTALIN', 'XTAL_REF_SEL', + 'XTAL_REF_SEL_1X', 'XTAL_REF_SEL_2X', 'Y10_CbCr1010_420_PLANAR', + 'Y10_CrCb1010_420_PLANAR', 'Y12_CbCr1212_420_PLANAR', + 'Y12_CrCb1212_420_PLANAR', 'Y8_CbCr88_420_PLANAR', + 'Y8_CrCb88_420_PLANAR', 'YCbYCr10101010_422_PACKED', + 'YCbYCr12121212_422_PACKED', 'YCbYCr8888_422_PACKED', + 'YCrCbA16161616_10LSB', 'YCrCbA16161616_10MSB', + 'YCrCbA16161616_12LSB', 'YCrCbA16161616_12MSB', 'YCrCbA8888', + 'YCrYCb10101010_422_PACKED', 'YCrYCb12121212_422_PACKED', + 'YCrYCb8888_422_PACKED', 'Y_G_DATA_ONTO_ALPHA_PORT', + 'Y_G_DATA_ONTO_CB_B_PORT', 'Y_G_DATA_ONTO_CR_R_PORT', + 'Y_G_DATA_ONTO_Y_G_PORT', 'ZLimitSumm', 'ZModeForce', 'ZOrder', + 'ZPASS_DISABLE', 'ZPASS_PIXELS', 'ZPASS_SAMPLES', + 'ZSamplePosition', 'Z_SAMPLE_CENTER', 'Z_SAMPLE_CENTROID', + 'ZpassControl', '__SDMA_V6_0_0_PKT_OPEN_H_', '__maybe_unused', + '_gc_10_3_0_OFFSET_HEADER', '_gc_11_0_0_OFFSET_HEADER', + '_sienna_cichlid_ip_offset_HEADER', '_soc21_ENUM_HEADER', + 'addr_incr___write_data__do_not_increment_address', + 'addr_incr___write_data__increment_address', + 'c__Ea_CACHE_FLUSH_AND_INV_TS_EVENT', 'c_uint32', 'c_uint32', + 'c_uint32', 'c_uint32', 'c_uint32', 'c_uint32', + 'cache_policy___write_data__lru', + 'cache_policy___write_data__stream', + 'cache_policy__mec_release_mem__lru', + 'cache_policy__mec_release_mem__stream', + 'data_sel__mec_release_mem__none', + 'data_sel__mec_release_mem__send_32_bit_low', + 'data_sel__mec_release_mem__send_64_bit_data', + 'data_sel__mec_release_mem__send_cp_perfcounter_hi_lo', + 'data_sel__mec_release_mem__send_gpu_clock_counter', + 'data_sel__mec_release_mem__store_gds_data_to_memory', + 'dst_sel___write_data__gds', + 'dst_sel___write_data__mem_mapped_register', + 'dst_sel___write_data__memory', + 'dst_sel___write_data__memory_mapped_adc_persistent_state', + 'dst_sel___write_data__tc_l2', + 'dst_sel__mec_release_mem__memory_controller', + 'dst_sel__mec_release_mem__queue_write_pointer_poll_mask_bit', + 'dst_sel__mec_release_mem__queue_write_pointer_register', + 'dst_sel__mec_release_mem__tc_l2', + 'event_index__mec_release_mem__end_of_pipe', + 'event_index__mec_release_mem__shader_done', 'ge1_assembler_busy', + 'ge1_assembler_dma_starved', 'ge1_assembler_stalled', + 'ge1_dma_busy', 'ge1_dma_lat_bin_0', 'ge1_dma_lat_bin_1', + 'ge1_dma_lat_bin_2', 'ge1_dma_lat_bin_3', 'ge1_dma_lat_bin_4', + 'ge1_dma_lat_bin_5', 'ge1_dma_lat_bin_6', 'ge1_dma_lat_bin_7', + 'ge1_dma_return_cl0', 'ge1_dma_return_cl1', + 'ge1_dma_return_size_cl0', 'ge1_dma_return_size_cl1', + 'ge1_dma_utcl1_consecutive_retry_event', + 'ge1_dma_utcl1_request_event', 'ge1_dma_utcl1_retry_event', + 'ge1_dma_utcl1_stall_event', 'ge1_dma_utcl1_stall_utcl2_event', + 'ge1_dma_utcl1_translation_hit_event', + 'ge1_dma_utcl1_translation_miss_event', 'ge1_pipe0_to_pipe1', + 'ge1_pipe1_to_pipe0', 'ge1_prim_group_limit_hit', + 'ge1_rbiu_di_fifo_stalled_p0', 'ge1_rbiu_di_fifo_stalled_p1', + 'ge1_rbiu_di_fifo_starved_p0', 'ge1_rbiu_di_fifo_starved_p1', + 'ge1_rbiu_dr_fifo_stalled_p0', 'ge1_rbiu_dr_fifo_stalled_p1', + 'ge1_rbiu_dr_fifo_starved_p0', 'ge1_rbiu_dr_fifo_starved_p1', + 'ge1_sclk_input_vld', 'ge1_sclk_reg_vld', + 'ge1_small_draws_one_instance', 'ge1_stat_busy', + 'ge1_stat_no_dma_busy', 'ge1_unopt_multi_instance_draws', + 'ge_agm_gcr_crd_stall', 'ge_agm_gcr_latency', 'ge_agm_gcr_req', + 'ge_agm_gcr_stall', 'ge_agm_gcr_tag_stall', 'ge_all_tf2', + 'ge_all_tf3', 'ge_all_tf4', 'ge_all_tf5', 'ge_all_tf6', + 'ge_all_tf_eq', 'ge_csb_spi_bp', 'ge_dist_distributer_busy', + 'ge_dist_hs_done', 'ge_dist_hs_done_latency', + 'ge_dist_hs_done_latency_se0', 'ge_dist_hs_done_latency_se1', + 'ge_dist_hs_done_latency_se2', 'ge_dist_hs_done_latency_se3', + 'ge_dist_hs_done_latency_se4', 'ge_dist_hs_done_latency_se5', + 'ge_dist_hs_done_latency_se6', 'ge_dist_hs_done_latency_se7', + 'ge_dist_hs_done_se0', 'ge_dist_hs_done_se1', + 'ge_dist_hs_done_se2', 'ge_dist_hs_done_se3', + 'ge_dist_hs_done_se4', 'ge_dist_hs_done_se5', + 'ge_dist_hs_done_se6', 'ge_dist_hs_done_se7', + 'ge_dist_inside_tf_bin_0', 'ge_dist_inside_tf_bin_1', + 'ge_dist_inside_tf_bin_2', 'ge_dist_inside_tf_bin_3', + 'ge_dist_inside_tf_bin_4', 'ge_dist_inside_tf_bin_5', + 'ge_dist_inside_tf_bin_6', 'ge_dist_inside_tf_bin_7', + 'ge_dist_inside_tf_bin_8', 'ge_dist_null_patch', + 'ge_dist_op_fifo_full_starve', 'ge_dist_pc_feorder_fifo_full', + 'ge_dist_pc_ge_manager_busy', 'ge_dist_pc_req_stall_se0', + 'ge_dist_pc_req_stall_se1', 'ge_dist_pc_req_stall_se2', + 'ge_dist_pc_req_stall_se3', 'ge_dist_pc_req_stall_se4', + 'ge_dist_pc_req_stall_se5', 'ge_dist_pc_req_stall_se6', + 'ge_dist_pc_req_stall_se7', 'ge_dist_pc_space_zero', + 'ge_dist_reserved', 'ge_dist_sclk_core_vld', + 'ge_dist_sclk_input_vld', 'ge_dist_sclk_wd_te11_vld', + 'ge_dist_switch_mode_stall', 'ge_dist_te11_starved', + 'ge_dist_tfreq_lat_bin_0', 'ge_dist_tfreq_lat_bin_1', + 'ge_dist_tfreq_lat_bin_2', 'ge_dist_tfreq_lat_bin_3', + 'ge_dist_tfreq_lat_bin_4', 'ge_dist_tfreq_lat_bin_5', + 'ge_dist_tfreq_lat_bin_6', 'ge_dist_tfreq_lat_bin_7', + 'ge_dist_tfreq_utcl1_consecutive_retry_event', + 'ge_dist_tfreq_utcl1_request_event', + 'ge_dist_tfreq_utcl1_retry_event', + 'ge_dist_tfreq_utcl1_stall_event', + 'ge_dist_tfreq_utcl1_stall_utcl2_event', + 'ge_dist_tfreq_utcl1_translation_hit_event', + 'ge_dist_tfreq_utcl1_translation_miss_event', + 'ge_dist_vs_pc_stall', 'ge_dist_wd_te11_busy', 'ge_distclk_vld', + 'ge_esvert_send', 'ge_gs_issue_rtr_stalled', 'ge_gsprim_send', + 'ge_gsprim_stalled_esvert', 'ge_gsthread_stalled', + 'ge_hs_stall_tfmm_fifo_full', 'ge_hs_tif_stall', + 'ge_ngg_agm_req_stall', 'ge_ngg_attr_discard_alloc', + 'ge_ngg_attr_grp_alloc', 'ge_ngg_attr_grp_latency', + 'ge_ngg_indx_bus_stall', 'ge_ngg_ord_id_req_stall', + 'ge_ngg_pc_space_not_avail', 'ge_ngg_reuse_prim_limit_hit', + 'ge_ngg_reuse_vert_limit_hit', 'ge_ngg_spi_esvert_partial_eov', + 'ge_ngg_spi_gsprim_partial_eov', 'ge_ngg_stall_tess_off_tess_on', + 'ge_ngg_stall_tess_on_tess_off', 'ge_ngg_starved_after_work', + 'ge_ngg_starved_idle', 'ge_ngg_starving_for_pc_grant', + 'ge_ngg_subgrp_fifo_stall', 'ge_num_of_donut_dist_patches', + 'ge_num_of_hs_alloc_events', 'ge_num_of_no_dist_patches', + 'ge_num_of_patch_dist_patches', + 'ge_num_of_se_switches_due_to_donut', + 'ge_num_of_se_switches_due_to_patch_accum', + 'ge_num_of_se_switches_due_to_trap', 'ge_pa0_csb_eop', + 'ge_pa1_csb_eop', 'ge_se0_te11_starved_on_hs_done', + 'ge_se1_te11_starved_on_hs_done', + 'ge_se2_te11_starved_on_hs_done', + 'ge_se3_te11_starved_on_hs_done', + 'ge_se4_te11_starved_on_hs_done', + 'ge_se5_te11_starved_on_hs_done', + 'ge_se6_te11_starved_on_hs_done', + 'ge_se7_te11_starved_on_hs_done', 'ge_se_ds_prims', + 'ge_se_es_thread_groups', 'ge_se_esvert_stalled_gsprim', + 'ge_se_hs_input_stall', 'ge_se_hs_tfm_stall', + 'ge_se_hs_tgs_active_high_water_mark', 'ge_se_hs_thread_groups', + 'ge_se_reused_es_indices', 'ge_se_sclk_input_vld', + 'ge_se_sclk_ngg_vld', 'ge_se_sclk_te11_vld', + 'ge_se_sending_vert_or_prim', 'ge_se_spi_esvert_eov', + 'ge_se_spi_esvert_stalled', 'ge_se_spi_esvert_starved_busy', + 'ge_se_spi_esvert_valid', 'ge_se_spi_gsprim_cont', + 'ge_se_spi_gsprim_eov', 'ge_se_spi_gsprim_stalled', + 'ge_se_spi_gsprim_starved_busy', 'ge_se_spi_gsprim_valid', + 'ge_se_spi_gssubgrp_event_window_active', + 'ge_se_spi_gssubgrp_is_event', 'ge_se_spi_gssubgrp_send', + 'ge_se_spi_hsvert_eov', 'ge_se_spi_hsvert_fifo_full_stall', + 'ge_se_spi_hsvert_stalled', 'ge_se_spi_hsvert_starved_busy', + 'ge_se_spi_hsvert_valid', 'ge_se_spi_hswave_is_event', + 'ge_se_spi_hswave_send', 'ge_se_spi_lsvert_eov', + 'ge_se_spi_lsvert_stalled', 'ge_se_spi_lsvert_starved_busy', + 'ge_se_spi_lsvert_valid', 'ge_se_spi_tgrp_fifo_stall', + 'ge_spi_gsgrp_valid', 'ge_spi_hsgrp_spi_stall', + 'ge_spi_hswave_fifo_full_stall', 'ge_spi_lswave_fifo_full_stall', + 'ge_te11_compactor_starved', 'ge_te11_con_stall', + 'ge_te11_stall_prim_funnel', 'ge_te11_stall_vert_funnel', + 'ge_tf_ret_data_stalling_hs_done', 'hdp_flush_cmd', 'int32_t', + 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_32_bit_compare', + 'int_sel__mec_release_mem__conditionally_send_int_ctxid_based_on_64_bit_compare', + 'int_sel__mec_release_mem__none', + 'int_sel__mec_release_mem__send_data_after_write_confirm', + 'int_sel__mec_release_mem__send_interrupt_after_write_confirm', + 'int_sel__mec_release_mem__send_interrupt_only', + 'int_sel__mec_release_mem__unconditionally_send_int_ctxid', + 'ixDIDT_DB_CTRL0', 'ixDIDT_DB_CTRL1', 'ixDIDT_DB_CTRL2', + 'ixDIDT_DB_CTRL3', 'ixDIDT_DB_CTRL_OCP', 'ixDIDT_DB_EDC_CTRL', + 'ixDIDT_DB_EDC_OVERFLOW', 'ixDIDT_DB_EDC_PCC_PERF_COUNTER', + 'ixDIDT_DB_EDC_ROLLING_POWER_DELTA', + 'ixDIDT_DB_EDC_STALL_DELAY_1', 'ixDIDT_DB_EDC_STALL_PATTERN_1_2', + 'ixDIDT_DB_EDC_STALL_PATTERN_3_4', + 'ixDIDT_DB_EDC_STALL_PATTERN_5_6', + 'ixDIDT_DB_EDC_STALL_PATTERN_7', 'ixDIDT_DB_EDC_STATUS', + 'ixDIDT_DB_EDC_THRESHOLD', 'ixDIDT_DB_EDC_TIMER_PERIOD', + 'ixDIDT_DB_MPD_SCALE_FACTOR', 'ixDIDT_DB_STALL_AUTO_RELEASE_CTRL', + 'ixDIDT_DB_STALL_CTRL', 'ixDIDT_DB_STALL_EVENT_COUNTER', + 'ixDIDT_DB_STALL_PATTERN_1_2', 'ixDIDT_DB_STALL_PATTERN_3_4', + 'ixDIDT_DB_STALL_PATTERN_5_6', 'ixDIDT_DB_STALL_PATTERN_7', + 'ixDIDT_DB_STALL_RELEASE_CNTL0', 'ixDIDT_DB_STALL_RELEASE_CNTL1', + 'ixDIDT_DB_STALL_RELEASE_CNTL_STATUS', 'ixDIDT_DB_THROTTLE_CTRL', + 'ixDIDT_DB_TUNING_CTRL', 'ixDIDT_DB_WEIGHT0_3', + 'ixDIDT_DB_WEIGHT4_7', 'ixDIDT_DB_WEIGHT8_11', 'ixDIDT_SQ_CTRL0', + 'ixDIDT_SQ_CTRL1', 'ixDIDT_SQ_CTRL2', 'ixDIDT_SQ_CTRL3', + 'ixDIDT_SQ_CTRL_OCP', 'ixDIDT_SQ_EDC_CTRL', + 'ixDIDT_SQ_EDC_OVERFLOW', 'ixDIDT_SQ_EDC_PCC_PERF_COUNTER', + 'ixDIDT_SQ_EDC_ROLLING_POWER_DELTA', + 'ixDIDT_SQ_EDC_STALL_DELAY_1', 'ixDIDT_SQ_EDC_STALL_DELAY_2', + 'ixDIDT_SQ_EDC_STALL_DELAY_3', 'ixDIDT_SQ_EDC_STALL_PATTERN_1_2', + 'ixDIDT_SQ_EDC_STALL_PATTERN_3_4', + 'ixDIDT_SQ_EDC_STALL_PATTERN_5_6', + 'ixDIDT_SQ_EDC_STALL_PATTERN_7', 'ixDIDT_SQ_EDC_STATUS', + 'ixDIDT_SQ_EDC_THRESHOLD', 'ixDIDT_SQ_EDC_TIMER_PERIOD', + 'ixDIDT_SQ_MPD_SCALE_FACTOR', 'ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL', + 'ixDIDT_SQ_STALL_CTRL', 'ixDIDT_SQ_STALL_EVENT_COUNTER', + 'ixDIDT_SQ_STALL_PATTERN_1_2', 'ixDIDT_SQ_STALL_PATTERN_3_4', + 'ixDIDT_SQ_STALL_PATTERN_5_6', 'ixDIDT_SQ_STALL_PATTERN_7', + 'ixDIDT_SQ_STALL_RELEASE_CNTL0', 'ixDIDT_SQ_STALL_RELEASE_CNTL1', + 'ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS', 'ixDIDT_SQ_THROTTLE_CTRL', + 'ixDIDT_SQ_TUNING_CTRL', 'ixDIDT_SQ_WEIGHT0_3', + 'ixDIDT_SQ_WEIGHT4_7', 'ixDIDT_SQ_WEIGHT8_11', 'ixDIDT_TCP_CTRL0', + 'ixDIDT_TCP_CTRL1', 'ixDIDT_TCP_CTRL2', 'ixDIDT_TCP_CTRL3', + 'ixDIDT_TCP_CTRL_OCP', 'ixDIDT_TCP_EDC_CTRL', + 'ixDIDT_TCP_EDC_OVERFLOW', 'ixDIDT_TCP_EDC_PCC_PERF_COUNTER', + 'ixDIDT_TCP_EDC_ROLLING_POWER_DELTA', + 'ixDIDT_TCP_EDC_STALL_DELAY_1', 'ixDIDT_TCP_EDC_STALL_DELAY_2', + 'ixDIDT_TCP_EDC_STALL_DELAY_3', + 'ixDIDT_TCP_EDC_STALL_PATTERN_1_2', + 'ixDIDT_TCP_EDC_STALL_PATTERN_3_4', + 'ixDIDT_TCP_EDC_STALL_PATTERN_5_6', + 'ixDIDT_TCP_EDC_STALL_PATTERN_7', 'ixDIDT_TCP_EDC_STATUS', + 'ixDIDT_TCP_EDC_THRESHOLD', 'ixDIDT_TCP_EDC_TIMER_PERIOD', + 'ixDIDT_TCP_MPD_SCALE_FACTOR', + 'ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL', 'ixDIDT_TCP_STALL_CTRL', + 'ixDIDT_TCP_STALL_EVENT_COUNTER', 'ixDIDT_TCP_STALL_PATTERN_1_2', + 'ixDIDT_TCP_STALL_PATTERN_3_4', 'ixDIDT_TCP_STALL_PATTERN_5_6', + 'ixDIDT_TCP_STALL_PATTERN_7', 'ixDIDT_TCP_STALL_RELEASE_CNTL0', + 'ixDIDT_TCP_STALL_RELEASE_CNTL1', + 'ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS', + 'ixDIDT_TCP_THROTTLE_CTRL', 'ixDIDT_TCP_TUNING_CTRL', + 'ixDIDT_TCP_WEIGHT0_3', 'ixDIDT_TCP_WEIGHT4_7', + 'ixDIDT_TCP_WEIGHT8_11', 'ixDIDT_TD_CTRL0', 'ixDIDT_TD_CTRL1', + 'ixDIDT_TD_CTRL2', 'ixDIDT_TD_CTRL3', 'ixDIDT_TD_CTRL_OCP', + 'ixDIDT_TD_EDC_CTRL', 'ixDIDT_TD_EDC_OVERFLOW', + 'ixDIDT_TD_EDC_PCC_PERF_COUNTER', + 'ixDIDT_TD_EDC_ROLLING_POWER_DELTA', + 'ixDIDT_TD_EDC_STALL_DELAY_1', 'ixDIDT_TD_EDC_STALL_DELAY_2', + 'ixDIDT_TD_EDC_STALL_DELAY_3', 'ixDIDT_TD_EDC_STALL_PATTERN_1_2', + 'ixDIDT_TD_EDC_STALL_PATTERN_3_4', + 'ixDIDT_TD_EDC_STALL_PATTERN_5_6', + 'ixDIDT_TD_EDC_STALL_PATTERN_7', 'ixDIDT_TD_EDC_STATUS', + 'ixDIDT_TD_EDC_THRESHOLD', 'ixDIDT_TD_EDC_TIMER_PERIOD', + 'ixDIDT_TD_MPD_SCALE_FACTOR', 'ixDIDT_TD_STALL_AUTO_RELEASE_CTRL', + 'ixDIDT_TD_STALL_CTRL', 'ixDIDT_TD_STALL_EVENT_COUNTER', + 'ixDIDT_TD_STALL_PATTERN_1_2', 'ixDIDT_TD_STALL_PATTERN_3_4', + 'ixDIDT_TD_STALL_PATTERN_5_6', 'ixDIDT_TD_STALL_PATTERN_7', + 'ixDIDT_TD_STALL_RELEASE_CNTL0', 'ixDIDT_TD_STALL_RELEASE_CNTL1', + 'ixDIDT_TD_STALL_RELEASE_CNTL_STATUS', 'ixDIDT_TD_THROTTLE_CTRL', + 'ixDIDT_TD_TUNING_CTRL', 'ixDIDT_TD_WEIGHT0_3', + 'ixDIDT_TD_WEIGHT4_7', 'ixDIDT_TD_WEIGHT8_11', + 'ixEDC_STRETCH_NUM_PERF_COUNTER', 'ixEDC_STRETCH_PERF_COUNTER', + 'ixEDC_UNSTRETCH_PERF_COUNTER', 'ixFIXED_PATTERN_PERF_COUNTER_1', 'ixFIXED_PATTERN_PERF_COUNTER_10', 'ixFIXED_PATTERN_PERF_COUNTER_2', 'ixFIXED_PATTERN_PERF_COUNTER_3', @@ -14332,44 +73494,196 @@ __all__ = \ 'ixFIXED_PATTERN_PERF_COUNTER_6', 'ixFIXED_PATTERN_PERF_COUNTER_7', 'ixFIXED_PATTERN_PERF_COUNTER_8', - 'ixFIXED_PATTERN_PERF_COUNTER_9', 'ixGC_CAC_ACC_CHC0', + 'ixFIXED_PATTERN_PERF_COUNTER_9', 'ixGC_CAC_ACC_BCI0', + 'ixGC_CAC_ACC_BCI1', 'ixGC_CAC_ACC_CB0', 'ixGC_CAC_ACC_CB1', + 'ixGC_CAC_ACC_CB2', 'ixGC_CAC_ACC_CB3', 'ixGC_CAC_ACC_CB4', + 'ixGC_CAC_ACC_CB5', 'ixGC_CAC_ACC_CB6', 'ixGC_CAC_ACC_CB7', + 'ixGC_CAC_ACC_CB8', 'ixGC_CAC_ACC_CB9', 'ixGC_CAC_ACC_CHC0', 'ixGC_CAC_ACC_CHC1', 'ixGC_CAC_ACC_CHC2', 'ixGC_CAC_ACC_CP0', - 'ixGC_CAC_ACC_CP1', 'ixGC_CAC_ACC_CP2', 'ixGC_CAC_ACC_EA0', - 'ixGC_CAC_ACC_EA1', 'ixGC_CAC_ACC_EA2', 'ixGC_CAC_ACC_EA3', - 'ixGC_CAC_ACC_EA4', 'ixGC_CAC_ACC_EA5', 'ixGC_CAC_ACC_GDS0', - 'ixGC_CAC_ACC_GDS1', 'ixGC_CAC_ACC_GDS2', 'ixGC_CAC_ACC_GDS3', - 'ixGC_CAC_ACC_GDS4', 'ixGC_CAC_ACC_GE0', 'ixGC_CAC_ACC_GE1', - 'ixGC_CAC_ACC_GE10', 'ixGC_CAC_ACC_GE11', 'ixGC_CAC_ACC_GE12', - 'ixGC_CAC_ACC_GE13', 'ixGC_CAC_ACC_GE14', 'ixGC_CAC_ACC_GE15', - 'ixGC_CAC_ACC_GE16', 'ixGC_CAC_ACC_GE17', 'ixGC_CAC_ACC_GE18', - 'ixGC_CAC_ACC_GE19', 'ixGC_CAC_ACC_GE2', 'ixGC_CAC_ACC_GE20', - 'ixGC_CAC_ACC_GE3', 'ixGC_CAC_ACC_GE4', 'ixGC_CAC_ACC_GE5', - 'ixGC_CAC_ACC_GE6', 'ixGC_CAC_ACC_GE7', 'ixGC_CAC_ACC_GE8', - 'ixGC_CAC_ACC_GE9', 'ixGC_CAC_ACC_GL2C0', 'ixGC_CAC_ACC_GL2C1', + 'ixGC_CAC_ACC_CP1', 'ixGC_CAC_ACC_CP2', 'ixGC_CAC_ACC_CU0', + 'ixGC_CAC_ACC_DB0', 'ixGC_CAC_ACC_DB1', 'ixGC_CAC_ACC_DB2', + 'ixGC_CAC_ACC_DB3', 'ixGC_CAC_ACC_DB4', 'ixGC_CAC_ACC_DB5', + 'ixGC_CAC_ACC_DB6', 'ixGC_CAC_ACC_DB7', 'ixGC_CAC_ACC_DB8', + 'ixGC_CAC_ACC_DB9', 'ixGC_CAC_ACC_EA0', 'ixGC_CAC_ACC_EA1', + 'ixGC_CAC_ACC_EA2', 'ixGC_CAC_ACC_EA3', 'ixGC_CAC_ACC_EA4', + 'ixGC_CAC_ACC_EA5', 'ixGC_CAC_ACC_GDS0', 'ixGC_CAC_ACC_GDS1', + 'ixGC_CAC_ACC_GDS2', 'ixGC_CAC_ACC_GDS3', 'ixGC_CAC_ACC_GDS4', + 'ixGC_CAC_ACC_GDS5', 'ixGC_CAC_ACC_GDS6', 'ixGC_CAC_ACC_GE0', + 'ixGC_CAC_ACC_GE1', 'ixGC_CAC_ACC_GE10', 'ixGC_CAC_ACC_GE11', + 'ixGC_CAC_ACC_GE12', 'ixGC_CAC_ACC_GE13', 'ixGC_CAC_ACC_GE14', + 'ixGC_CAC_ACC_GE15', 'ixGC_CAC_ACC_GE16', 'ixGC_CAC_ACC_GE17', + 'ixGC_CAC_ACC_GE18', 'ixGC_CAC_ACC_GE19', 'ixGC_CAC_ACC_GE2', + 'ixGC_CAC_ACC_GE20', 'ixGC_CAC_ACC_GE3', 'ixGC_CAC_ACC_GE4', + 'ixGC_CAC_ACC_GE5', 'ixGC_CAC_ACC_GE6', 'ixGC_CAC_ACC_GE7', + 'ixGC_CAC_ACC_GE8', 'ixGC_CAC_ACC_GE9', 'ixGC_CAC_ACC_GL1C0', + 'ixGC_CAC_ACC_GL1C1', 'ixGC_CAC_ACC_GL1C2', 'ixGC_CAC_ACC_GL1C3', + 'ixGC_CAC_ACC_GL1C4', 'ixGC_CAC_ACC_GL2C0', 'ixGC_CAC_ACC_GL2C1', 'ixGC_CAC_ACC_GL2C2', 'ixGC_CAC_ACC_GL2C3', 'ixGC_CAC_ACC_GL2C4', 'ixGC_CAC_ACC_GUS0', 'ixGC_CAC_ACC_GUS1', 'ixGC_CAC_ACC_GUS2', + 'ixGC_CAC_ACC_LDS0', 'ixGC_CAC_ACC_LDS1', 'ixGC_CAC_ACC_LDS2', + 'ixGC_CAC_ACC_LDS3', 'ixGC_CAC_ACC_LDS4', 'ixGC_CAC_ACC_LDS5', + 'ixGC_CAC_ACC_LDS6', 'ixGC_CAC_ACC_LDS7', 'ixGC_CAC_ACC_LDS8', + 'ixGC_CAC_ACC_PA0', 'ixGC_CAC_ACC_PA1', 'ixGC_CAC_ACC_PA2', + 'ixGC_CAC_ACC_PA3', 'ixGC_CAC_ACC_PA4', 'ixGC_CAC_ACC_PA5', + 'ixGC_CAC_ACC_PA6', 'ixGC_CAC_ACC_PA7', 'ixGC_CAC_ACC_PC0', 'ixGC_CAC_ACC_PH0', 'ixGC_CAC_ACC_PH1', 'ixGC_CAC_ACC_PH2', 'ixGC_CAC_ACC_PH3', 'ixGC_CAC_ACC_PH4', 'ixGC_CAC_ACC_PH5', 'ixGC_CAC_ACC_PH6', 'ixGC_CAC_ACC_PH7', 'ixGC_CAC_ACC_PMM0', - 'ixGC_CAC_ACC_RLC0', 'ixGC_CAC_ACC_SDMA0', 'ixGC_CAC_ACC_SDMA1', + 'ixGC_CAC_ACC_RLC0', 'ixGC_CAC_ACC_RMI0', 'ixGC_CAC_ACC_RMI1', + 'ixGC_CAC_ACC_RMI2', 'ixGC_CAC_ACC_RMI3', 'ixGC_CAC_ACC_SC0', + 'ixGC_CAC_ACC_SC1', 'ixGC_CAC_ACC_SC2', 'ixGC_CAC_ACC_SC3', + 'ixGC_CAC_ACC_SC4', 'ixGC_CAC_ACC_SC5', 'ixGC_CAC_ACC_SC6', + 'ixGC_CAC_ACC_SC7', 'ixGC_CAC_ACC_SDMA0', 'ixGC_CAC_ACC_SDMA1', 'ixGC_CAC_ACC_SDMA10', 'ixGC_CAC_ACC_SDMA11', 'ixGC_CAC_ACC_SDMA2', 'ixGC_CAC_ACC_SDMA3', 'ixGC_CAC_ACC_SDMA4', 'ixGC_CAC_ACC_SDMA5', 'ixGC_CAC_ACC_SDMA6', 'ixGC_CAC_ACC_SDMA7', 'ixGC_CAC_ACC_SDMA8', 'ixGC_CAC_ACC_SDMA9', - 'ixGC_CAC_ACC_UTCL2_ROUTER0', 'ixGC_CAC_ACC_UTCL2_ROUTER1', - 'ixGC_CAC_ACC_UTCL2_ROUTER2', 'ixGC_CAC_ACC_UTCL2_ROUTER3', - 'ixGC_CAC_ACC_UTCL2_ROUTER4', 'ixGC_CAC_ACC_UTCL2_ROUTER5', - 'ixGC_CAC_ACC_UTCL2_ROUTER6', 'ixGC_CAC_ACC_UTCL2_ROUTER7', - 'ixGC_CAC_ACC_UTCL2_ROUTER8', 'ixGC_CAC_ACC_UTCL2_ROUTER9', - 'ixGC_CAC_ACC_UTCL2_VML20', 'ixGC_CAC_ACC_UTCL2_VML21', - 'ixGC_CAC_ACC_UTCL2_VML22', 'ixGC_CAC_ACC_UTCL2_VML23', - 'ixGC_CAC_ACC_UTCL2_VML24', 'ixGC_CAC_ACC_UTCL2_WALKER0', - 'ixGC_CAC_ACC_UTCL2_WALKER1', 'ixGC_CAC_ACC_UTCL2_WALKER2', - 'ixGC_CAC_ACC_UTCL2_WALKER3', 'ixGC_CAC_ACC_UTCL2_WALKER4', - 'ixGC_CAC_CNTL', 'ixGC_CAC_ID', 'ixHW_LUT_UPDATE_STATUS', - 'ixPWRBRK_RELEASE_TO_STALL_LUT_17_20', + 'ixGC_CAC_ACC_SP0_LOWER', 'ixGC_CAC_ACC_SP0_UPPER', + 'ixGC_CAC_ACC_SP1_LOWER', 'ixGC_CAC_ACC_SP1_UPPER', + 'ixGC_CAC_ACC_SP2_LOWER', 'ixGC_CAC_ACC_SP2_UPPER', + 'ixGC_CAC_ACC_SPI0', 'ixGC_CAC_ACC_SPI1', 'ixGC_CAC_ACC_SPI2', + 'ixGC_CAC_ACC_SPI3', 'ixGC_CAC_ACC_SPI4', 'ixGC_CAC_ACC_SPI5', + 'ixGC_CAC_ACC_SQ0_LOWER', 'ixGC_CAC_ACC_SQ0_UPPER', + 'ixGC_CAC_ACC_SQ1_LOWER', 'ixGC_CAC_ACC_SQ1_UPPER', + 'ixGC_CAC_ACC_SQ2_LOWER', 'ixGC_CAC_ACC_SQ2_UPPER', + 'ixGC_CAC_ACC_SQ3_LOWER', 'ixGC_CAC_ACC_SQ3_UPPER', + 'ixGC_CAC_ACC_SQ4_LOWER', 'ixGC_CAC_ACC_SQ4_UPPER', + 'ixGC_CAC_ACC_SQ5_LOWER', 'ixGC_CAC_ACC_SQ5_UPPER', + 'ixGC_CAC_ACC_SQ6_LOWER', 'ixGC_CAC_ACC_SQ6_UPPER', + 'ixGC_CAC_ACC_SQ7_LOWER', 'ixGC_CAC_ACC_SQ7_UPPER', + 'ixGC_CAC_ACC_SQ8_LOWER', 'ixGC_CAC_ACC_SQ8_UPPER', + 'ixGC_CAC_ACC_SQC0', 'ixGC_CAC_ACC_SQC1', 'ixGC_CAC_ACC_SQC2', + 'ixGC_CAC_ACC_SX0', 'ixGC_CAC_ACC_SXRB0', 'ixGC_CAC_ACC_TA0', + 'ixGC_CAC_ACC_TCP0', 'ixGC_CAC_ACC_TCP1', 'ixGC_CAC_ACC_TCP2', + 'ixGC_CAC_ACC_TCP3', 'ixGC_CAC_ACC_TCP4', 'ixGC_CAC_ACC_TCP5', + 'ixGC_CAC_ACC_TCP6', 'ixGC_CAC_ACC_TCP7', 'ixGC_CAC_ACC_TD0', + 'ixGC_CAC_ACC_TD1', 'ixGC_CAC_ACC_TD10', 'ixGC_CAC_ACC_TD2', + 'ixGC_CAC_ACC_TD3', 'ixGC_CAC_ACC_TD4', 'ixGC_CAC_ACC_TD5', + 'ixGC_CAC_ACC_TD6', 'ixGC_CAC_ACC_TD7', 'ixGC_CAC_ACC_TD8', + 'ixGC_CAC_ACC_TD9', 'ixGC_CAC_ACC_UTCL10', + 'ixGC_CAC_ACC_UTCL2_ATCL20', 'ixGC_CAC_ACC_UTCL2_ATCL21', + 'ixGC_CAC_ACC_UTCL2_ATCL22', 'ixGC_CAC_ACC_UTCL2_ATCL23', + 'ixGC_CAC_ACC_UTCL2_ATCL24', 'ixGC_CAC_ACC_UTCL2_ROUTER0', + 'ixGC_CAC_ACC_UTCL2_ROUTER1', 'ixGC_CAC_ACC_UTCL2_ROUTER2', + 'ixGC_CAC_ACC_UTCL2_ROUTER3', 'ixGC_CAC_ACC_UTCL2_ROUTER4', + 'ixGC_CAC_ACC_UTCL2_ROUTER5', 'ixGC_CAC_ACC_UTCL2_ROUTER6', + 'ixGC_CAC_ACC_UTCL2_ROUTER7', 'ixGC_CAC_ACC_UTCL2_ROUTER8', + 'ixGC_CAC_ACC_UTCL2_ROUTER9', 'ixGC_CAC_ACC_UTCL2_VML20', + 'ixGC_CAC_ACC_UTCL2_VML21', 'ixGC_CAC_ACC_UTCL2_VML22', + 'ixGC_CAC_ACC_UTCL2_VML23', 'ixGC_CAC_ACC_UTCL2_VML24', + 'ixGC_CAC_ACC_UTCL2_WALKER0', 'ixGC_CAC_ACC_UTCL2_WALKER1', + 'ixGC_CAC_ACC_UTCL2_WALKER2', 'ixGC_CAC_ACC_UTCL2_WALKER3', + 'ixGC_CAC_ACC_UTCL2_WALKER4', 'ixGC_CAC_CNTL', 'ixGC_CAC_ID', + 'ixGC_CAC_OVRD_BCI', 'ixGC_CAC_OVRD_CB', 'ixGC_CAC_OVRD_CHC', + 'ixGC_CAC_OVRD_CP', 'ixGC_CAC_OVRD_CU', 'ixGC_CAC_OVRD_DB', + 'ixGC_CAC_OVRD_EA', 'ixGC_CAC_OVRD_GDS', 'ixGC_CAC_OVRD_GE', + 'ixGC_CAC_OVRD_GE_HI', 'ixGC_CAC_OVRD_GL1C', 'ixGC_CAC_OVRD_GL2C', + 'ixGC_CAC_OVRD_GUS', 'ixGC_CAC_OVRD_LDS', 'ixGC_CAC_OVRD_PA', + 'ixGC_CAC_OVRD_PC', 'ixGC_CAC_OVRD_PH', 'ixGC_CAC_OVRD_PMM', + 'ixGC_CAC_OVRD_RLC', 'ixGC_CAC_OVRD_RMI', 'ixGC_CAC_OVRD_SC', + 'ixGC_CAC_OVRD_SDMA', 'ixGC_CAC_OVRD_SP', 'ixGC_CAC_OVRD_SPI', + 'ixGC_CAC_OVRD_SQ', 'ixGC_CAC_OVRD_SQC', 'ixGC_CAC_OVRD_SX', + 'ixGC_CAC_OVRD_SXRB', 'ixGC_CAC_OVRD_TA', 'ixGC_CAC_OVRD_TCP', + 'ixGC_CAC_OVRD_TD', 'ixGC_CAC_OVRD_UTCL1', + 'ixGC_CAC_OVRD_UTCL2_ATCL2', 'ixGC_CAC_OVRD_UTCL2_ROUTER', + 'ixGC_CAC_OVRD_UTCL2_VML2', 'ixGC_CAC_OVRD_UTCL2_WALKER', + 'ixGC_CAC_OVR_SEL', 'ixGC_CAC_OVR_VAL', 'ixGC_CAC_WEIGHT_BCI_0', + 'ixGC_CAC_WEIGHT_CB_0', 'ixGC_CAC_WEIGHT_CB_1', + 'ixGC_CAC_WEIGHT_CB_2', 'ixGC_CAC_WEIGHT_CB_3', + 'ixGC_CAC_WEIGHT_CB_4', 'ixGC_CAC_WEIGHT_CHC_0', + 'ixGC_CAC_WEIGHT_CHC_1', 'ixGC_CAC_WEIGHT_CP_0', + 'ixGC_CAC_WEIGHT_CP_1', 'ixGC_CAC_WEIGHT_CU_0', + 'ixGC_CAC_WEIGHT_DB_0', 'ixGC_CAC_WEIGHT_DB_1', + 'ixGC_CAC_WEIGHT_DB_2', 'ixGC_CAC_WEIGHT_DB_3', + 'ixGC_CAC_WEIGHT_DB_4', 'ixGC_CAC_WEIGHT_EA_0', + 'ixGC_CAC_WEIGHT_EA_1', 'ixGC_CAC_WEIGHT_EA_2', + 'ixGC_CAC_WEIGHT_GDS_0', 'ixGC_CAC_WEIGHT_GDS_1', + 'ixGC_CAC_WEIGHT_GDS_2', 'ixGC_CAC_WEIGHT_GE_0', + 'ixGC_CAC_WEIGHT_GE_1', 'ixGC_CAC_WEIGHT_GE_10', + 'ixGC_CAC_WEIGHT_GE_2', 'ixGC_CAC_WEIGHT_GE_3', + 'ixGC_CAC_WEIGHT_GE_4', 'ixGC_CAC_WEIGHT_GE_5', + 'ixGC_CAC_WEIGHT_GE_6', 'ixGC_CAC_WEIGHT_GE_7', + 'ixGC_CAC_WEIGHT_GE_8', 'ixGC_CAC_WEIGHT_GE_9', + 'ixGC_CAC_WEIGHT_GL1C_0', 'ixGC_CAC_WEIGHT_GL1C_1', + 'ixGC_CAC_WEIGHT_GL1C_2', 'ixGC_CAC_WEIGHT_GL2C_0', + 'ixGC_CAC_WEIGHT_GL2C_1', 'ixGC_CAC_WEIGHT_GL2C_2', + 'ixGC_CAC_WEIGHT_GUS_0', 'ixGC_CAC_WEIGHT_GUS_1', + 'ixGC_CAC_WEIGHT_LDS_0', 'ixGC_CAC_WEIGHT_LDS_1', + 'ixGC_CAC_WEIGHT_LDS_2', 'ixGC_CAC_WEIGHT_LDS_3', + 'ixGC_CAC_WEIGHT_LDS_4', 'ixGC_CAC_WEIGHT_PA_0', + 'ixGC_CAC_WEIGHT_PA_1', 'ixGC_CAC_WEIGHT_PA_2', + 'ixGC_CAC_WEIGHT_PA_3', 'ixGC_CAC_WEIGHT_PC_0', + 'ixGC_CAC_WEIGHT_PH_0', 'ixGC_CAC_WEIGHT_PH_1', + 'ixGC_CAC_WEIGHT_PH_2', 'ixGC_CAC_WEIGHT_PH_3', + 'ixGC_CAC_WEIGHT_PMM_0', 'ixGC_CAC_WEIGHT_RLC_0', + 'ixGC_CAC_WEIGHT_RMI_0', 'ixGC_CAC_WEIGHT_RMI_1', + 'ixGC_CAC_WEIGHT_SC_0', 'ixGC_CAC_WEIGHT_SC_1', + 'ixGC_CAC_WEIGHT_SC_2', 'ixGC_CAC_WEIGHT_SC_3', + 'ixGC_CAC_WEIGHT_SDMA_0', 'ixGC_CAC_WEIGHT_SDMA_1', + 'ixGC_CAC_WEIGHT_SDMA_2', 'ixGC_CAC_WEIGHT_SDMA_3', + 'ixGC_CAC_WEIGHT_SDMA_4', 'ixGC_CAC_WEIGHT_SDMA_5', + 'ixGC_CAC_WEIGHT_SPI_0', 'ixGC_CAC_WEIGHT_SPI_1', + 'ixGC_CAC_WEIGHT_SPI_2', 'ixGC_CAC_WEIGHT_SP_0', + 'ixGC_CAC_WEIGHT_SP_1', 'ixGC_CAC_WEIGHT_SQC_0', + 'ixGC_CAC_WEIGHT_SQC_1', 'ixGC_CAC_WEIGHT_SQ_0', + 'ixGC_CAC_WEIGHT_SQ_1', 'ixGC_CAC_WEIGHT_SQ_2', + 'ixGC_CAC_WEIGHT_SQ_3', 'ixGC_CAC_WEIGHT_SXRB_0', + 'ixGC_CAC_WEIGHT_SX_0', 'ixGC_CAC_WEIGHT_TA_0', + 'ixGC_CAC_WEIGHT_TCP_0', 'ixGC_CAC_WEIGHT_TCP_1', + 'ixGC_CAC_WEIGHT_TCP_2', 'ixGC_CAC_WEIGHT_TCP_3', + 'ixGC_CAC_WEIGHT_TD_0', 'ixGC_CAC_WEIGHT_TD_1', + 'ixGC_CAC_WEIGHT_TD_2', 'ixGC_CAC_WEIGHT_TD_3', + 'ixGC_CAC_WEIGHT_TD_4', 'ixGC_CAC_WEIGHT_TD_5', + 'ixGC_CAC_WEIGHT_UTCL1_0', 'ixGC_CAC_WEIGHT_UTCL2_ATCL2_0', + 'ixGC_CAC_WEIGHT_UTCL2_ATCL2_1', 'ixGC_CAC_WEIGHT_UTCL2_ATCL2_2', + 'ixGC_CAC_WEIGHT_UTCL2_ROUTER_0', + 'ixGC_CAC_WEIGHT_UTCL2_ROUTER_1', + 'ixGC_CAC_WEIGHT_UTCL2_ROUTER_2', + 'ixGC_CAC_WEIGHT_UTCL2_ROUTER_3', + 'ixGC_CAC_WEIGHT_UTCL2_ROUTER_4', 'ixGC_CAC_WEIGHT_UTCL2_VML2_0', + 'ixGC_CAC_WEIGHT_UTCL2_VML2_1', 'ixGC_CAC_WEIGHT_UTCL2_VML2_2', + 'ixGC_CAC_WEIGHT_UTCL2_WALKER_0', + 'ixGC_CAC_WEIGHT_UTCL2_WALKER_1', + 'ixGC_CAC_WEIGHT_UTCL2_WALKER_2', 'ixGLB_ATCL2_SAMPLEDELAY', + 'ixGLB_CHA_SAMPLEDELAY', 'ixGLB_CHC0_SAMPLEDELAY', + 'ixGLB_CHC1_SAMPLEDELAY', 'ixGLB_CHC2_SAMPLEDELAY', + 'ixGLB_CHC3_SAMPLEDELAY', 'ixGLB_CHCG_SAMPLEDELAY', + 'ixGLB_CPC_SAMPLEDELAY', 'ixGLB_CPF_SAMPLEDELAY', + 'ixGLB_CPG_SAMPLEDELAY', 'ixGLB_EA0_SAMPLEDELAY', + 'ixGLB_EA10_SAMPLEDELAY', 'ixGLB_EA11_SAMPLEDELAY', + 'ixGLB_EA12_SAMPLEDELAY', 'ixGLB_EA13_SAMPLEDELAY', + 'ixGLB_EA14_SAMPLEDELAY', 'ixGLB_EA15_SAMPLEDELAY', + 'ixGLB_EA1_SAMPLEDELAY', 'ixGLB_EA2_SAMPLEDELAY', + 'ixGLB_EA3_SAMPLEDELAY', 'ixGLB_EA4_SAMPLEDELAY', + 'ixGLB_EA5_SAMPLEDELAY', 'ixGLB_EA6_SAMPLEDELAY', + 'ixGLB_EA7_SAMPLEDELAY', 'ixGLB_EA8_SAMPLEDELAY', + 'ixGLB_EA9_SAMPLEDELAY', 'ixGLB_GCR_SAMPLEDELAY', + 'ixGLB_GDS_SAMPLEDELAY', 'ixGLB_GE1_SAMPLEDELAY', + 'ixGLB_GE2DIST_SAMPLEDELAY', 'ixGLB_GE2SE0_SAMPLEDELAY', + 'ixGLB_GE2SE1_SAMPLEDELAY', 'ixGLB_GE2SE2_SAMPLEDELAY', + 'ixGLB_GE2SE3_SAMPLEDELAY', 'ixGLB_GL2A0_SAMPLEDELAY', + 'ixGLB_GL2A1_SAMPLEDELAY', 'ixGLB_GL2A2_SAMPLEDELAY', + 'ixGLB_GL2A3_SAMPLEDELAY', 'ixGLB_GL2C0_SAMPLEDELAY', + 'ixGLB_GL2C10_SAMPLEDELAY', 'ixGLB_GL2C11_SAMPLEDELAY', + 'ixGLB_GL2C12_SAMPLEDELAY', 'ixGLB_GL2C13_SAMPLEDELAY', + 'ixGLB_GL2C14_SAMPLEDELAY', 'ixGLB_GL2C15_SAMPLEDELAY', + 'ixGLB_GL2C1_SAMPLEDELAY', 'ixGLB_GL2C2_SAMPLEDELAY', + 'ixGLB_GL2C3_SAMPLEDELAY', 'ixGLB_GL2C4_SAMPLEDELAY', + 'ixGLB_GL2C5_SAMPLEDELAY', 'ixGLB_GL2C6_SAMPLEDELAY', + 'ixGLB_GL2C7_SAMPLEDELAY', 'ixGLB_GL2C8_SAMPLEDELAY', + 'ixGLB_GL2C9_SAMPLEDELAY', 'ixGLB_GUS_SAMPLEDELAY', + 'ixGLB_PH_SAMPLEDELAY', 'ixGLB_SDMA0_SAMPLEDELAY', + 'ixGLB_SDMA1_SAMPLEDELAY', 'ixGLB_SDMA2_SAMPLEDELAY', + 'ixGLB_SDMA3_SAMPLEDELAY', 'ixGLB_VML2_SAMPLEDELAY', + 'ixHW_LUT_UPDATE_STATUS', 'ixPCC_PWRBRK_HYSTERESIS_CTRL', + 'ixPCC_STALL_PATTERN_1_2', 'ixPCC_STALL_PATTERN_3_4', + 'ixPCC_STALL_PATTERN_5_6', 'ixPCC_STALL_PATTERN_7', + 'ixPCC_STALL_PATTERN_CTRL', 'ixPWRBRK_RELEASE_TO_STALL_LUT_17_20', 'ixPWRBRK_RELEASE_TO_STALL_LUT_1_8', 'ixPWRBRK_RELEASE_TO_STALL_LUT_9_16', + 'ixPWRBRK_STALL_PATTERN_1_2', 'ixPWRBRK_STALL_PATTERN_3_4', + 'ixPWRBRK_STALL_PATTERN_5_6', 'ixPWRBRK_STALL_PATTERN_7', + 'ixPWRBRK_STALL_PATTERN_CTRL', 'ixPWRBRK_STALL_TO_RELEASE_LUT_1_4', 'ixPWRBRK_STALL_TO_RELEASE_LUT_5_7', 'ixRELEASE_TO_STALL_LUT_17_20', 'ixRELEASE_TO_STALL_LUT_1_8', @@ -14438,24 +73752,7707 @@ __all__ = \ 'ixRTAVFS_REG90', 'ixRTAVFS_REG91', 'ixRTAVFS_REG92', 'ixRTAVFS_REG93', 'ixRTAVFS_REG94', 'ixRTAVFS_REG95', 'ixRTAVFS_REG96', 'ixRTAVFS_REG97', 'ixRTAVFS_REG98', - 'ixRTAVFS_REG99', 'ixSE_CAC_CNTL', 'ixSE_CAC_ID', - 'ixSQ_DEBUG_CTRL_LOCAL', 'ixSQ_DEBUG_STS_LOCAL', + 'ixRTAVFS_REG99', 'ixSA_WGP_BLK_ID', 'ixSE_CAC_CNTL', + 'ixSE_CAC_ID', 'ixSE_CAC_OVR_SEL', 'ixSE_CAC_OVR_VAL', + 'ixSE_CBR_SAMPLEDELAY', 'ixSE_DBR_SAMPLEDELAY', + 'ixSE_PA_SAMPLEDELAY', 'ixSE_SA0CB0_SAMPLEDELAY', + 'ixSE_SA0CB1_SAMPLEDELAY', 'ixSE_SA0DB0_SAMPLEDELAY', + 'ixSE_SA0DB1_SAMPLEDELAY', 'ixSE_SA0GL1A_SAMPLEDELAY', + 'ixSE_SA0GL1C0_SAMPLEDELAY', 'ixSE_SA0GL1C1_SAMPLEDELAY', + 'ixSE_SA0GL1C2_SAMPLEDELAY', 'ixSE_SA0GL1C3_SAMPLEDELAY', + 'ixSE_SA0GL1CG_SAMPLEDELAY', 'ixSE_SA0RMI0_SAMPLEDELAY', + 'ixSE_SA0RMI1_SAMPLEDELAY', 'ixSE_SA0SC0_SAMPLEDELAY', + 'ixSE_SA0SC1_SAMPLEDELAY', 'ixSE_SA0SX_SAMPLEDELAY', + 'ixSE_SA0WGP00TA0_SAMPLEDELAY', 'ixSE_SA0WGP00TA1_SAMPLEDELAY', + 'ixSE_SA0WGP00TCP0_SAMPLEDELAY', 'ixSE_SA0WGP00TCP1_SAMPLEDELAY', + 'ixSE_SA0WGP00TD0_SAMPLEDELAY', 'ixSE_SA0WGP00TD1_SAMPLEDELAY', + 'ixSE_SA0WGP01TA0_SAMPLEDELAY', 'ixSE_SA0WGP01TA1_SAMPLEDELAY', + 'ixSE_SA0WGP01TCP0_SAMPLEDELAY', 'ixSE_SA0WGP01TCP1_SAMPLEDELAY', + 'ixSE_SA0WGP01TD0_SAMPLEDELAY', 'ixSE_SA0WGP01TD1_SAMPLEDELAY', + 'ixSE_SA0WGP02TA0_SAMPLEDELAY', 'ixSE_SA0WGP02TA1_SAMPLEDELAY', + 'ixSE_SA0WGP02TCP0_SAMPLEDELAY', 'ixSE_SA0WGP02TCP1_SAMPLEDELAY', + 'ixSE_SA0WGP02TD0_SAMPLEDELAY', 'ixSE_SA0WGP02TD1_SAMPLEDELAY', + 'ixSE_SA0WGP03TA0_SAMPLEDELAY', 'ixSE_SA0WGP03TA1_SAMPLEDELAY', + 'ixSE_SA0WGP03TCP0_SAMPLEDELAY', 'ixSE_SA0WGP03TCP1_SAMPLEDELAY', + 'ixSE_SA0WGP03TD0_SAMPLEDELAY', 'ixSE_SA0WGP03TD1_SAMPLEDELAY', + 'ixSE_SA0WGP04TA0_SAMPLEDELAY', 'ixSE_SA0WGP04TA1_SAMPLEDELAY', + 'ixSE_SA0WGP04TCP0_SAMPLEDELAY', 'ixSE_SA0WGP04TCP1_SAMPLEDELAY', + 'ixSE_SA0WGP04TD0_SAMPLEDELAY', 'ixSE_SA0WGP04TD1_SAMPLEDELAY', + 'ixSE_SA1CB0_SAMPLEDELAY', 'ixSE_SA1CB1_SAMPLEDELAY', + 'ixSE_SA1DB0_SAMPLEDELAY', 'ixSE_SA1DB1_SAMPLEDELAY', + 'ixSE_SA1GL1A_SAMPLEDELAY', 'ixSE_SA1GL1C0_SAMPLEDELAY', + 'ixSE_SA1GL1C1_SAMPLEDELAY', 'ixSE_SA1GL1C2_SAMPLEDELAY', + 'ixSE_SA1GL1C3_SAMPLEDELAY', 'ixSE_SA1GL1CG_SAMPLEDELAY', + 'ixSE_SA1RMI0_SAMPLEDELAY', 'ixSE_SA1RMI1_SAMPLEDELAY', + 'ixSE_SA1SC0_SAMPLEDELAY', 'ixSE_SA1SC1_SAMPLEDELAY', + 'ixSE_SA1SX_SAMPLEDELAY', 'ixSE_SA1WGP00TA0_SAMPLEDELAY', + 'ixSE_SA1WGP00TA1_SAMPLEDELAY', 'ixSE_SA1WGP00TCP0_SAMPLEDELAY', + 'ixSE_SA1WGP00TCP1_SAMPLEDELAY', 'ixSE_SA1WGP00TD0_SAMPLEDELAY', + 'ixSE_SA1WGP00TD1_SAMPLEDELAY', 'ixSE_SA1WGP01TA0_SAMPLEDELAY', + 'ixSE_SA1WGP01TA1_SAMPLEDELAY', 'ixSE_SA1WGP01TCP0_SAMPLEDELAY', + 'ixSE_SA1WGP01TCP1_SAMPLEDELAY', 'ixSE_SA1WGP01TD0_SAMPLEDELAY', + 'ixSE_SA1WGP01TD1_SAMPLEDELAY', 'ixSE_SA1WGP02TA0_SAMPLEDELAY', + 'ixSE_SA1WGP02TA1_SAMPLEDELAY', 'ixSE_SA1WGP02TCP0_SAMPLEDELAY', + 'ixSE_SA1WGP02TCP1_SAMPLEDELAY', 'ixSE_SA1WGP02TD0_SAMPLEDELAY', + 'ixSE_SA1WGP02TD1_SAMPLEDELAY', 'ixSE_SA1WGP03TA0_SAMPLEDELAY', + 'ixSE_SA1WGP03TA1_SAMPLEDELAY', 'ixSE_SA1WGP03TCP0_SAMPLEDELAY', + 'ixSE_SA1WGP03TCP1_SAMPLEDELAY', 'ixSE_SA1WGP03TD0_SAMPLEDELAY', + 'ixSE_SA1WGP03TD1_SAMPLEDELAY', 'ixSE_SA1WGP04TA0_SAMPLEDELAY', + 'ixSE_SA1WGP04TA1_SAMPLEDELAY', 'ixSE_SA1WGP04TCP0_SAMPLEDELAY', + 'ixSE_SA1WGP04TCP1_SAMPLEDELAY', 'ixSE_SA1WGP04TD0_SAMPLEDELAY', + 'ixSE_SA1WGP04TD1_SAMPLEDELAY', 'ixSE_SPI_SAMPLEDELAY', + 'ixSE_SQG_SAMPLEDELAY', 'ixSQ_DEBUG_CTRL_LOCAL', + 'ixSQ_DEBUG_STS_LOCAL', 'ixSQ_INTERRUPT_WORD_AUTO', + 'ixSQ_INTERRUPT_WORD_ERROR', 'ixSQ_INTERRUPT_WORD_WAVE', 'ixSQ_WAVE_ACTIVE', 'ixSQ_WAVE_EXEC_HI', 'ixSQ_WAVE_EXEC_LO', 'ixSQ_WAVE_FLAT_SCRATCH_HI', 'ixSQ_WAVE_FLAT_SCRATCH_LO', 'ixSQ_WAVE_FLUSH_IB', 'ixSQ_WAVE_GPR_ALLOC', 'ixSQ_WAVE_HW_ID1', - 'ixSQ_WAVE_HW_ID2', 'ixSQ_WAVE_IB_DBG1', 'ixSQ_WAVE_IB_STS', - 'ixSQ_WAVE_IB_STS2', 'ixSQ_WAVE_LDS_ALLOC', 'ixSQ_WAVE_M0', - 'ixSQ_WAVE_MODE', 'ixSQ_WAVE_PC_HI', 'ixSQ_WAVE_PC_LO', - 'ixSQ_WAVE_POPS_PACKER', 'ixSQ_WAVE_SCHED_MODE', - 'ixSQ_WAVE_SHADER_CYCLES', 'ixSQ_WAVE_STATUS', - 'ixSQ_WAVE_TRAPSTS', 'ixSQ_WAVE_TTMP0', 'ixSQ_WAVE_TTMP1', - 'ixSQ_WAVE_TTMP10', 'ixSQ_WAVE_TTMP11', 'ixSQ_WAVE_TTMP12', - 'ixSQ_WAVE_TTMP13', 'ixSQ_WAVE_TTMP14', 'ixSQ_WAVE_TTMP15', - 'ixSQ_WAVE_TTMP3', 'ixSQ_WAVE_TTMP4', 'ixSQ_WAVE_TTMP5', - 'ixSQ_WAVE_TTMP6', 'ixSQ_WAVE_TTMP7', 'ixSQ_WAVE_TTMP8', - 'ixSQ_WAVE_TTMP9', 'ixSQ_WAVE_VALID_AND_IDLE', + 'ixSQ_WAVE_HW_ID2', 'ixSQ_WAVE_HW_ID_LEGACY', 'ixSQ_WAVE_IB_DBG1', + 'ixSQ_WAVE_IB_STS', 'ixSQ_WAVE_IB_STS2', 'ixSQ_WAVE_INST_DW0', + 'ixSQ_WAVE_LDS_ALLOC', 'ixSQ_WAVE_M0', 'ixSQ_WAVE_MODE', + 'ixSQ_WAVE_PC_HI', 'ixSQ_WAVE_PC_LO', 'ixSQ_WAVE_POPS_PACKER', + 'ixSQ_WAVE_SCHED_MODE', 'ixSQ_WAVE_SHADER_CYCLES', + 'ixSQ_WAVE_STATUS', 'ixSQ_WAVE_TRAPSTS', 'ixSQ_WAVE_TTMP0', + 'ixSQ_WAVE_TTMP1', 'ixSQ_WAVE_TTMP10', 'ixSQ_WAVE_TTMP11', + 'ixSQ_WAVE_TTMP12', 'ixSQ_WAVE_TTMP13', 'ixSQ_WAVE_TTMP14', + 'ixSQ_WAVE_TTMP15', 'ixSQ_WAVE_TTMP2', 'ixSQ_WAVE_TTMP3', + 'ixSQ_WAVE_TTMP4', 'ixSQ_WAVE_TTMP5', 'ixSQ_WAVE_TTMP6', + 'ixSQ_WAVE_TTMP7', 'ixSQ_WAVE_TTMP8', 'ixSQ_WAVE_TTMP9', + 'ixSQ_WAVE_VALID_AND_IDLE', 'ixSQ_WAVE_VGPR_OFFSET', 'ixSTALL_TO_PWRBRK_LUT_1_4', 'ixSTALL_TO_PWRBRK_LUT_5_7', 'ixSTALL_TO_RELEASE_LUT_1_4', 'ixSTALL_TO_RELEASE_LUT_5_7', + 'mmCB_BLEND0_CONTROL', 'mmCB_BLEND0_CONTROL_BASE_IDX', + 'mmCB_BLEND1_CONTROL', 'mmCB_BLEND1_CONTROL_BASE_IDX', + 'mmCB_BLEND2_CONTROL', 'mmCB_BLEND2_CONTROL_BASE_IDX', + 'mmCB_BLEND3_CONTROL', 'mmCB_BLEND3_CONTROL_BASE_IDX', + 'mmCB_BLEND4_CONTROL', 'mmCB_BLEND4_CONTROL_BASE_IDX', + 'mmCB_BLEND5_CONTROL', 'mmCB_BLEND5_CONTROL_BASE_IDX', + 'mmCB_BLEND6_CONTROL', 'mmCB_BLEND6_CONTROL_BASE_IDX', + 'mmCB_BLEND7_CONTROL', 'mmCB_BLEND7_CONTROL_BASE_IDX', + 'mmCB_BLEND_ALPHA', 'mmCB_BLEND_ALPHA_BASE_IDX', + 'mmCB_BLEND_BLUE', 'mmCB_BLEND_BLUE_BASE_IDX', 'mmCB_BLEND_GREEN', + 'mmCB_BLEND_GREEN_BASE_IDX', 'mmCB_BLEND_RED', + 'mmCB_BLEND_RED_BASE_IDX', 'mmCB_CACHE_EVICT_POINTS', + 'mmCB_CACHE_EVICT_POINTS_BASE_IDX', 'mmCB_CGTT_SCLK_CTRL', + 'mmCB_CGTT_SCLK_CTRL_BASE_IDX', 'mmCB_COLOR0_ATTRIB', + 'mmCB_COLOR0_ATTRIB2', 'mmCB_COLOR0_ATTRIB2_BASE_IDX', + 'mmCB_COLOR0_ATTRIB3', 'mmCB_COLOR0_ATTRIB3_BASE_IDX', + 'mmCB_COLOR0_ATTRIB_BASE_IDX', 'mmCB_COLOR0_BASE', + 'mmCB_COLOR0_BASE_BASE_IDX', 'mmCB_COLOR0_BASE_EXT', + 'mmCB_COLOR0_BASE_EXT_BASE_IDX', 'mmCB_COLOR0_CLEAR_WORD0', + 'mmCB_COLOR0_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR0_CLEAR_WORD1', + 'mmCB_COLOR0_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR0_CMASK', + 'mmCB_COLOR0_CMASK_BASE_EXT', + 'mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR0_CMASK_BASE_IDX', 'mmCB_COLOR0_CMASK_SLICE', + 'mmCB_COLOR0_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR0_DCC_BASE', + 'mmCB_COLOR0_DCC_BASE_BASE_IDX', 'mmCB_COLOR0_DCC_BASE_EXT', + 'mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR0_DCC_CONTROL', + 'mmCB_COLOR0_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR0_FMASK', + 'mmCB_COLOR0_FMASK_BASE_EXT', + 'mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR0_FMASK_BASE_IDX', 'mmCB_COLOR0_FMASK_SLICE', + 'mmCB_COLOR0_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR0_INFO', + 'mmCB_COLOR0_INFO_BASE_IDX', 'mmCB_COLOR0_PITCH', + 'mmCB_COLOR0_PITCH_BASE_IDX', 'mmCB_COLOR0_SLICE', + 'mmCB_COLOR0_SLICE_BASE_IDX', 'mmCB_COLOR0_VIEW', + 'mmCB_COLOR0_VIEW_BASE_IDX', 'mmCB_COLOR1_ATTRIB', + 'mmCB_COLOR1_ATTRIB2', 'mmCB_COLOR1_ATTRIB2_BASE_IDX', + 'mmCB_COLOR1_ATTRIB3', 'mmCB_COLOR1_ATTRIB3_BASE_IDX', + 'mmCB_COLOR1_ATTRIB_BASE_IDX', 'mmCB_COLOR1_BASE', + 'mmCB_COLOR1_BASE_BASE_IDX', 'mmCB_COLOR1_BASE_EXT', + 'mmCB_COLOR1_BASE_EXT_BASE_IDX', 'mmCB_COLOR1_CLEAR_WORD0', + 'mmCB_COLOR1_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR1_CLEAR_WORD1', + 'mmCB_COLOR1_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR1_CMASK', + 'mmCB_COLOR1_CMASK_BASE_EXT', + 'mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR1_CMASK_BASE_IDX', 'mmCB_COLOR1_CMASK_SLICE', + 'mmCB_COLOR1_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR1_DCC_BASE', + 'mmCB_COLOR1_DCC_BASE_BASE_IDX', 'mmCB_COLOR1_DCC_BASE_EXT', + 'mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR1_DCC_CONTROL', + 'mmCB_COLOR1_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR1_FMASK', + 'mmCB_COLOR1_FMASK_BASE_EXT', + 'mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR1_FMASK_BASE_IDX', 'mmCB_COLOR1_FMASK_SLICE', + 'mmCB_COLOR1_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR1_INFO', + 'mmCB_COLOR1_INFO_BASE_IDX', 'mmCB_COLOR1_PITCH', + 'mmCB_COLOR1_PITCH_BASE_IDX', 'mmCB_COLOR1_SLICE', + 'mmCB_COLOR1_SLICE_BASE_IDX', 'mmCB_COLOR1_VIEW', + 'mmCB_COLOR1_VIEW_BASE_IDX', 'mmCB_COLOR2_ATTRIB', + 'mmCB_COLOR2_ATTRIB2', 'mmCB_COLOR2_ATTRIB2_BASE_IDX', + 'mmCB_COLOR2_ATTRIB3', 'mmCB_COLOR2_ATTRIB3_BASE_IDX', + 'mmCB_COLOR2_ATTRIB_BASE_IDX', 'mmCB_COLOR2_BASE', + 'mmCB_COLOR2_BASE_BASE_IDX', 'mmCB_COLOR2_BASE_EXT', + 'mmCB_COLOR2_BASE_EXT_BASE_IDX', 'mmCB_COLOR2_CLEAR_WORD0', + 'mmCB_COLOR2_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR2_CLEAR_WORD1', + 'mmCB_COLOR2_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR2_CMASK', + 'mmCB_COLOR2_CMASK_BASE_EXT', + 'mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR2_CMASK_BASE_IDX', 'mmCB_COLOR2_CMASK_SLICE', + 'mmCB_COLOR2_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR2_DCC_BASE', + 'mmCB_COLOR2_DCC_BASE_BASE_IDX', 'mmCB_COLOR2_DCC_BASE_EXT', + 'mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR2_DCC_CONTROL', + 'mmCB_COLOR2_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR2_FMASK', + 'mmCB_COLOR2_FMASK_BASE_EXT', + 'mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR2_FMASK_BASE_IDX', 'mmCB_COLOR2_FMASK_SLICE', + 'mmCB_COLOR2_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR2_INFO', + 'mmCB_COLOR2_INFO_BASE_IDX', 'mmCB_COLOR2_PITCH', + 'mmCB_COLOR2_PITCH_BASE_IDX', 'mmCB_COLOR2_SLICE', + 'mmCB_COLOR2_SLICE_BASE_IDX', 'mmCB_COLOR2_VIEW', + 'mmCB_COLOR2_VIEW_BASE_IDX', 'mmCB_COLOR3_ATTRIB', + 'mmCB_COLOR3_ATTRIB2', 'mmCB_COLOR3_ATTRIB2_BASE_IDX', + 'mmCB_COLOR3_ATTRIB3', 'mmCB_COLOR3_ATTRIB3_BASE_IDX', + 'mmCB_COLOR3_ATTRIB_BASE_IDX', 'mmCB_COLOR3_BASE', + 'mmCB_COLOR3_BASE_BASE_IDX', 'mmCB_COLOR3_BASE_EXT', + 'mmCB_COLOR3_BASE_EXT_BASE_IDX', 'mmCB_COLOR3_CLEAR_WORD0', + 'mmCB_COLOR3_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR3_CLEAR_WORD1', + 'mmCB_COLOR3_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR3_CMASK', + 'mmCB_COLOR3_CMASK_BASE_EXT', + 'mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR3_CMASK_BASE_IDX', 'mmCB_COLOR3_CMASK_SLICE', + 'mmCB_COLOR3_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR3_DCC_BASE', + 'mmCB_COLOR3_DCC_BASE_BASE_IDX', 'mmCB_COLOR3_DCC_BASE_EXT', + 'mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR3_DCC_CONTROL', + 'mmCB_COLOR3_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR3_FMASK', + 'mmCB_COLOR3_FMASK_BASE_EXT', + 'mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR3_FMASK_BASE_IDX', 'mmCB_COLOR3_FMASK_SLICE', + 'mmCB_COLOR3_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR3_INFO', + 'mmCB_COLOR3_INFO_BASE_IDX', 'mmCB_COLOR3_PITCH', + 'mmCB_COLOR3_PITCH_BASE_IDX', 'mmCB_COLOR3_SLICE', + 'mmCB_COLOR3_SLICE_BASE_IDX', 'mmCB_COLOR3_VIEW', + 'mmCB_COLOR3_VIEW_BASE_IDX', 'mmCB_COLOR4_ATTRIB', + 'mmCB_COLOR4_ATTRIB2', 'mmCB_COLOR4_ATTRIB2_BASE_IDX', + 'mmCB_COLOR4_ATTRIB3', 'mmCB_COLOR4_ATTRIB3_BASE_IDX', + 'mmCB_COLOR4_ATTRIB_BASE_IDX', 'mmCB_COLOR4_BASE', + 'mmCB_COLOR4_BASE_BASE_IDX', 'mmCB_COLOR4_BASE_EXT', + 'mmCB_COLOR4_BASE_EXT_BASE_IDX', 'mmCB_COLOR4_CLEAR_WORD0', + 'mmCB_COLOR4_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR4_CLEAR_WORD1', + 'mmCB_COLOR4_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR4_CMASK', + 'mmCB_COLOR4_CMASK_BASE_EXT', + 'mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR4_CMASK_BASE_IDX', 'mmCB_COLOR4_CMASK_SLICE', + 'mmCB_COLOR4_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR4_DCC_BASE', + 'mmCB_COLOR4_DCC_BASE_BASE_IDX', 'mmCB_COLOR4_DCC_BASE_EXT', + 'mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR4_DCC_CONTROL', + 'mmCB_COLOR4_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR4_FMASK', + 'mmCB_COLOR4_FMASK_BASE_EXT', + 'mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR4_FMASK_BASE_IDX', 'mmCB_COLOR4_FMASK_SLICE', + 'mmCB_COLOR4_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR4_INFO', + 'mmCB_COLOR4_INFO_BASE_IDX', 'mmCB_COLOR4_PITCH', + 'mmCB_COLOR4_PITCH_BASE_IDX', 'mmCB_COLOR4_SLICE', + 'mmCB_COLOR4_SLICE_BASE_IDX', 'mmCB_COLOR4_VIEW', + 'mmCB_COLOR4_VIEW_BASE_IDX', 'mmCB_COLOR5_ATTRIB', + 'mmCB_COLOR5_ATTRIB2', 'mmCB_COLOR5_ATTRIB2_BASE_IDX', + 'mmCB_COLOR5_ATTRIB3', 'mmCB_COLOR5_ATTRIB3_BASE_IDX', + 'mmCB_COLOR5_ATTRIB_BASE_IDX', 'mmCB_COLOR5_BASE', + 'mmCB_COLOR5_BASE_BASE_IDX', 'mmCB_COLOR5_BASE_EXT', + 'mmCB_COLOR5_BASE_EXT_BASE_IDX', 'mmCB_COLOR5_CLEAR_WORD0', + 'mmCB_COLOR5_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR5_CLEAR_WORD1', + 'mmCB_COLOR5_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR5_CMASK', + 'mmCB_COLOR5_CMASK_BASE_EXT', + 'mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR5_CMASK_BASE_IDX', 'mmCB_COLOR5_CMASK_SLICE', + 'mmCB_COLOR5_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR5_DCC_BASE', + 'mmCB_COLOR5_DCC_BASE_BASE_IDX', 'mmCB_COLOR5_DCC_BASE_EXT', + 'mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR5_DCC_CONTROL', + 'mmCB_COLOR5_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR5_FMASK', + 'mmCB_COLOR5_FMASK_BASE_EXT', + 'mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR5_FMASK_BASE_IDX', 'mmCB_COLOR5_FMASK_SLICE', + 'mmCB_COLOR5_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR5_INFO', + 'mmCB_COLOR5_INFO_BASE_IDX', 'mmCB_COLOR5_PITCH', + 'mmCB_COLOR5_PITCH_BASE_IDX', 'mmCB_COLOR5_SLICE', + 'mmCB_COLOR5_SLICE_BASE_IDX', 'mmCB_COLOR5_VIEW', + 'mmCB_COLOR5_VIEW_BASE_IDX', 'mmCB_COLOR6_ATTRIB', + 'mmCB_COLOR6_ATTRIB2', 'mmCB_COLOR6_ATTRIB2_BASE_IDX', + 'mmCB_COLOR6_ATTRIB3', 'mmCB_COLOR6_ATTRIB3_BASE_IDX', + 'mmCB_COLOR6_ATTRIB_BASE_IDX', 'mmCB_COLOR6_BASE', + 'mmCB_COLOR6_BASE_BASE_IDX', 'mmCB_COLOR6_BASE_EXT', + 'mmCB_COLOR6_BASE_EXT_BASE_IDX', 'mmCB_COLOR6_CLEAR_WORD0', + 'mmCB_COLOR6_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR6_CLEAR_WORD1', + 'mmCB_COLOR6_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR6_CMASK', + 'mmCB_COLOR6_CMASK_BASE_EXT', + 'mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR6_CMASK_BASE_IDX', 'mmCB_COLOR6_CMASK_SLICE', + 'mmCB_COLOR6_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR6_DCC_BASE', + 'mmCB_COLOR6_DCC_BASE_BASE_IDX', 'mmCB_COLOR6_DCC_BASE_EXT', + 'mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR6_DCC_CONTROL', + 'mmCB_COLOR6_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR6_FMASK', + 'mmCB_COLOR6_FMASK_BASE_EXT', + 'mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR6_FMASK_BASE_IDX', 'mmCB_COLOR6_FMASK_SLICE', + 'mmCB_COLOR6_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR6_INFO', + 'mmCB_COLOR6_INFO_BASE_IDX', 'mmCB_COLOR6_PITCH', + 'mmCB_COLOR6_PITCH_BASE_IDX', 'mmCB_COLOR6_SLICE', + 'mmCB_COLOR6_SLICE_BASE_IDX', 'mmCB_COLOR6_VIEW', + 'mmCB_COLOR6_VIEW_BASE_IDX', 'mmCB_COLOR7_ATTRIB', + 'mmCB_COLOR7_ATTRIB2', 'mmCB_COLOR7_ATTRIB2_BASE_IDX', + 'mmCB_COLOR7_ATTRIB3', 'mmCB_COLOR7_ATTRIB3_BASE_IDX', + 'mmCB_COLOR7_ATTRIB_BASE_IDX', 'mmCB_COLOR7_BASE', + 'mmCB_COLOR7_BASE_BASE_IDX', 'mmCB_COLOR7_BASE_EXT', + 'mmCB_COLOR7_BASE_EXT_BASE_IDX', 'mmCB_COLOR7_CLEAR_WORD0', + 'mmCB_COLOR7_CLEAR_WORD0_BASE_IDX', 'mmCB_COLOR7_CLEAR_WORD1', + 'mmCB_COLOR7_CLEAR_WORD1_BASE_IDX', 'mmCB_COLOR7_CMASK', + 'mmCB_COLOR7_CMASK_BASE_EXT', + 'mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR7_CMASK_BASE_IDX', 'mmCB_COLOR7_CMASK_SLICE', + 'mmCB_COLOR7_CMASK_SLICE_BASE_IDX', 'mmCB_COLOR7_DCC_BASE', + 'mmCB_COLOR7_DCC_BASE_BASE_IDX', 'mmCB_COLOR7_DCC_BASE_EXT', + 'mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX', 'mmCB_COLOR7_DCC_CONTROL', + 'mmCB_COLOR7_DCC_CONTROL_BASE_IDX', 'mmCB_COLOR7_FMASK', + 'mmCB_COLOR7_FMASK_BASE_EXT', + 'mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX', + 'mmCB_COLOR7_FMASK_BASE_IDX', 'mmCB_COLOR7_FMASK_SLICE', + 'mmCB_COLOR7_FMASK_SLICE_BASE_IDX', 'mmCB_COLOR7_INFO', + 'mmCB_COLOR7_INFO_BASE_IDX', 'mmCB_COLOR7_PITCH', + 'mmCB_COLOR7_PITCH_BASE_IDX', 'mmCB_COLOR7_SLICE', + 'mmCB_COLOR7_SLICE_BASE_IDX', 'mmCB_COLOR7_VIEW', + 'mmCB_COLOR7_VIEW_BASE_IDX', 'mmCB_COLOR_CONTROL', + 'mmCB_COLOR_CONTROL_BASE_IDX', 'mmCB_COVERAGE_OUT_CONTROL', + 'mmCB_COVERAGE_OUT_CONTROL_BASE_IDX', 'mmCB_DCC_CONFIG', + 'mmCB_DCC_CONFIG_BASE_IDX', 'mmCB_DCC_CONTROL', + 'mmCB_DCC_CONTROL_BASE_IDX', 'mmCB_HW_CONTROL', + 'mmCB_HW_CONTROL_1', 'mmCB_HW_CONTROL_1_BASE_IDX', + 'mmCB_HW_CONTROL_2', 'mmCB_HW_CONTROL_2_BASE_IDX', + 'mmCB_HW_CONTROL_3', 'mmCB_HW_CONTROL_3_BASE_IDX', + 'mmCB_HW_CONTROL_4', 'mmCB_HW_CONTROL_4_BASE_IDX', + 'mmCB_HW_CONTROL_BASE_IDX', 'mmCB_HW_MEM_ARBITER_RD', + 'mmCB_HW_MEM_ARBITER_RD_BASE_IDX', 'mmCB_HW_MEM_ARBITER_WR', + 'mmCB_HW_MEM_ARBITER_WR_BASE_IDX', 'mmCB_PERFCOUNTER0_HI', + 'mmCB_PERFCOUNTER0_HI_BASE_IDX', 'mmCB_PERFCOUNTER0_LO', + 'mmCB_PERFCOUNTER0_LO_BASE_IDX', 'mmCB_PERFCOUNTER0_SELECT', + 'mmCB_PERFCOUNTER0_SELECT1', 'mmCB_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmCB_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCB_PERFCOUNTER1_HI', + 'mmCB_PERFCOUNTER1_HI_BASE_IDX', 'mmCB_PERFCOUNTER1_LO', + 'mmCB_PERFCOUNTER1_LO_BASE_IDX', 'mmCB_PERFCOUNTER1_SELECT', + 'mmCB_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCB_PERFCOUNTER2_HI', + 'mmCB_PERFCOUNTER2_HI_BASE_IDX', 'mmCB_PERFCOUNTER2_LO', + 'mmCB_PERFCOUNTER2_LO_BASE_IDX', 'mmCB_PERFCOUNTER2_SELECT', + 'mmCB_PERFCOUNTER2_SELECT_BASE_IDX', 'mmCB_PERFCOUNTER3_HI', + 'mmCB_PERFCOUNTER3_HI_BASE_IDX', 'mmCB_PERFCOUNTER3_LO', + 'mmCB_PERFCOUNTER3_LO_BASE_IDX', 'mmCB_PERFCOUNTER3_SELECT', + 'mmCB_PERFCOUNTER3_SELECT_BASE_IDX', 'mmCB_PERFCOUNTER_FILTER', + 'mmCB_PERFCOUNTER_FILTER_BASE_IDX', + 'mmCB_RMI_BC_GL2_CACHE_CONTROL', + 'mmCB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX', + 'mmCB_RMI_GL2_CACHE_CONTROL', + 'mmCB_RMI_GL2_CACHE_CONTROL_BASE_IDX', 'mmCB_SHADER_MASK', + 'mmCB_SHADER_MASK_BASE_IDX', 'mmCB_STUTTER_CONTROL_CMASK_RDLAT', + 'mmCB_STUTTER_CONTROL_CMASK_RDLAT_BASE_IDX', + 'mmCB_STUTTER_CONTROL_COLOR_RDLAT', + 'mmCB_STUTTER_CONTROL_COLOR_RDLAT_BASE_IDX', + 'mmCB_STUTTER_CONTROL_FMASK_RDLAT', + 'mmCB_STUTTER_CONTROL_FMASK_RDLAT_BASE_IDX', 'mmCB_TARGET_MASK', + 'mmCB_TARGET_MASK_BASE_IDX', 'mmCC_GC_EDC_CONFIG', + 'mmCC_GC_EDC_CONFIG_BASE_IDX', 'mmCC_GC_PRIM_CONFIG', + 'mmCC_GC_PRIM_CONFIG_BASE_IDX', 'mmCC_GC_SA_UNIT_DISABLE', + 'mmCC_GC_SA_UNIT_DISABLE_BASE_IDX', 'mmCC_GC_SHADER_ARRAY_CONFIG', + 'mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX', + 'mmCC_GC_SHADER_ARRAY_CONFIG_GEN0', + 'mmCC_GC_SHADER_ARRAY_CONFIG_GEN0_BASE_IDX', + 'mmCC_GC_SHADER_ARRAY_CONFIG_GEN1', + 'mmCC_GC_SHADER_ARRAY_CONFIG_GEN1_BASE_IDX', + 'mmCC_GC_SHADER_RATE_CONFIG', + 'mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX', 'mmCC_RB_BACKEND_DISABLE', + 'mmCC_RB_BACKEND_DISABLE_BASE_IDX', 'mmCC_RB_DAISY_CHAIN', + 'mmCC_RB_DAISY_CHAIN_BASE_IDX', 'mmCC_RB_REDUNDANCY', + 'mmCC_RB_REDUNDANCY_BASE_IDX', 'mmCC_RMI_REDUNDANCY', + 'mmCC_RMI_REDUNDANCY_BASE_IDX', 'mmCGTS_RD_CTRL_REG', + 'mmCGTS_RD_CTRL_REG_BASE_IDX', 'mmCGTS_RD_REG', + 'mmCGTS_RD_REG_BASE_IDX', 'mmCGTS_STATUS_REG', + 'mmCGTS_STATUS_REG_BASE_IDX', 'mmCGTS_TCC_DISABLE', + 'mmCGTS_TCC_DISABLE_BASE_IDX', 'mmCGTS_USER_TCC_DISABLE', + 'mmCGTS_USER_TCC_DISABLE_BASE_IDX', 'mmCGTT_BCI_CLK_CTRL', + 'mmCGTT_BCI_CLK_CTRL_BASE_IDX', 'mmCGTT_CPC_CLK_CTRL', + 'mmCGTT_CPC_CLK_CTRL_BASE_IDX', 'mmCGTT_CPF_CLK_CTRL', + 'mmCGTT_CPF_CLK_CTRL_BASE_IDX', 'mmCGTT_CP_CLK_CTRL', + 'mmCGTT_CP_CLK_CTRL_BASE_IDX', 'mmCGTT_GDS_CLK_CTRL', + 'mmCGTT_GDS_CLK_CTRL_BASE_IDX', 'mmCGTT_GS_NGG_CLK_CTRL', + 'mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX', 'mmCGTT_IA_CLK_CTRL', + 'mmCGTT_IA_CLK_CTRL_BASE_IDX', 'mmCGTT_PA_CLK_CTRL', + 'mmCGTT_PA_CLK_CTRL_BASE_IDX', 'mmCGTT_PC_CLK_CTRL', + 'mmCGTT_PC_CLK_CTRL_BASE_IDX', 'mmCGTT_PH_CLK_CTRL0', + 'mmCGTT_PH_CLK_CTRL0_BASE_IDX', 'mmCGTT_PH_CLK_CTRL1', + 'mmCGTT_PH_CLK_CTRL1_BASE_IDX', 'mmCGTT_PH_CLK_CTRL2', + 'mmCGTT_PH_CLK_CTRL2_BASE_IDX', 'mmCGTT_PH_CLK_CTRL3', + 'mmCGTT_PH_CLK_CTRL3_BASE_IDX', 'mmCGTT_RLC_CLK_CTRL', + 'mmCGTT_RLC_CLK_CTRL_BASE_IDX', 'mmCGTT_SC_CLK_CTRL0', + 'mmCGTT_SC_CLK_CTRL0_BASE_IDX', 'mmCGTT_SC_CLK_CTRL1', + 'mmCGTT_SC_CLK_CTRL1_BASE_IDX', 'mmCGTT_SC_CLK_CTRL2', + 'mmCGTT_SC_CLK_CTRL2_BASE_IDX', 'mmCGTT_SPIS_CLK_CTRL', + 'mmCGTT_SPIS_CLK_CTRL_BASE_IDX', 'mmCGTT_SPI_CGTSSM_CLK_CTRL', + 'mmCGTT_SPI_CGTSSM_CLK_CTRL_BASE_IDX', 'mmCGTT_SPI_CLK_CTRL', + 'mmCGTT_SPI_CLK_CTRL_BASE_IDX', 'mmCGTT_SPI_PS_CLK_CTRL', + 'mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX', 'mmCGTT_SQG_CLK_CTRL', + 'mmCGTT_SQG_CLK_CTRL_BASE_IDX', 'mmCGTT_SQ_CLK_CTRL', + 'mmCGTT_SQ_CLK_CTRL_BASE_IDX', 'mmCGTT_SX_CLK_CTRL0', + 'mmCGTT_SX_CLK_CTRL0_BASE_IDX', 'mmCGTT_SX_CLK_CTRL1', + 'mmCGTT_SX_CLK_CTRL1_BASE_IDX', 'mmCGTT_SX_CLK_CTRL2', + 'mmCGTT_SX_CLK_CTRL2_BASE_IDX', 'mmCGTT_SX_CLK_CTRL3', + 'mmCGTT_SX_CLK_CTRL3_BASE_IDX', 'mmCGTT_SX_CLK_CTRL4', + 'mmCGTT_SX_CLK_CTRL4_BASE_IDX', 'mmCGTT_TCPF_CLK_CTRL', + 'mmCGTT_TCPF_CLK_CTRL_BASE_IDX', 'mmCGTT_TCPI_CLK_CTRL', + 'mmCGTT_TCPI_CLK_CTRL_BASE_IDX', 'mmCGTT_VGT_CLK_CTRL', + 'mmCGTT_VGT_CLK_CTRL_BASE_IDX', 'mmCGTT_WD_CLK_CTRL', + 'mmCGTT_WD_CLK_CTRL_BASE_IDX', 'mmCHA_CHC_CREDITS', + 'mmCHA_CHC_CREDITS_BASE_IDX', 'mmCHA_CLIENT_FREE_DELAY', + 'mmCHA_CLIENT_FREE_DELAY_BASE_IDX', 'mmCHA_PERFCOUNTER0_HI', + 'mmCHA_PERFCOUNTER0_HI_BASE_IDX', 'mmCHA_PERFCOUNTER0_LO', + 'mmCHA_PERFCOUNTER0_LO_BASE_IDX', 'mmCHA_PERFCOUNTER0_SELECT', + 'mmCHA_PERFCOUNTER0_SELECT1', + 'mmCHA_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmCHA_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCHA_PERFCOUNTER1_HI', + 'mmCHA_PERFCOUNTER1_HI_BASE_IDX', 'mmCHA_PERFCOUNTER1_LO', + 'mmCHA_PERFCOUNTER1_LO_BASE_IDX', 'mmCHA_PERFCOUNTER1_SELECT', + 'mmCHA_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCHA_PERFCOUNTER2_HI', + 'mmCHA_PERFCOUNTER2_HI_BASE_IDX', 'mmCHA_PERFCOUNTER2_LO', + 'mmCHA_PERFCOUNTER2_LO_BASE_IDX', 'mmCHA_PERFCOUNTER2_SELECT', + 'mmCHA_PERFCOUNTER2_SELECT_BASE_IDX', 'mmCHA_PERFCOUNTER3_HI', + 'mmCHA_PERFCOUNTER3_HI_BASE_IDX', 'mmCHA_PERFCOUNTER3_LO', + 'mmCHA_PERFCOUNTER3_LO_BASE_IDX', 'mmCHA_PERFCOUNTER3_SELECT', + 'mmCHA_PERFCOUNTER3_SELECT_BASE_IDX', 'mmCHCG_CTRL', + 'mmCHCG_CTRL_BASE_IDX', 'mmCHCG_PERFCOUNTER0_HI', + 'mmCHCG_PERFCOUNTER0_HI_BASE_IDX', 'mmCHCG_PERFCOUNTER0_LO', + 'mmCHCG_PERFCOUNTER0_LO_BASE_IDX', 'mmCHCG_PERFCOUNTER0_SELECT', + 'mmCHCG_PERFCOUNTER0_SELECT1', + 'mmCHCG_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmCHCG_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCHCG_PERFCOUNTER1_HI', + 'mmCHCG_PERFCOUNTER1_HI_BASE_IDX', 'mmCHCG_PERFCOUNTER1_LO', + 'mmCHCG_PERFCOUNTER1_LO_BASE_IDX', 'mmCHCG_PERFCOUNTER1_SELECT', + 'mmCHCG_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCHCG_PERFCOUNTER2_HI', + 'mmCHCG_PERFCOUNTER2_HI_BASE_IDX', 'mmCHCG_PERFCOUNTER2_LO', + 'mmCHCG_PERFCOUNTER2_LO_BASE_IDX', 'mmCHCG_PERFCOUNTER2_SELECT', + 'mmCHCG_PERFCOUNTER2_SELECT_BASE_IDX', 'mmCHCG_PERFCOUNTER3_HI', + 'mmCHCG_PERFCOUNTER3_HI_BASE_IDX', 'mmCHCG_PERFCOUNTER3_LO', + 'mmCHCG_PERFCOUNTER3_LO_BASE_IDX', 'mmCHCG_PERFCOUNTER3_SELECT', + 'mmCHCG_PERFCOUNTER3_SELECT_BASE_IDX', 'mmCHCG_STATUS', + 'mmCHCG_STATUS_BASE_IDX', 'mmCHC_CTRL', 'mmCHC_CTRL_BASE_IDX', + 'mmCHC_PERFCOUNTER0_HI', 'mmCHC_PERFCOUNTER0_HI_BASE_IDX', + 'mmCHC_PERFCOUNTER0_LO', 'mmCHC_PERFCOUNTER0_LO_BASE_IDX', + 'mmCHC_PERFCOUNTER0_SELECT', 'mmCHC_PERFCOUNTER0_SELECT1', + 'mmCHC_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmCHC_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCHC_PERFCOUNTER1_HI', + 'mmCHC_PERFCOUNTER1_HI_BASE_IDX', 'mmCHC_PERFCOUNTER1_LO', + 'mmCHC_PERFCOUNTER1_LO_BASE_IDX', 'mmCHC_PERFCOUNTER1_SELECT', + 'mmCHC_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCHC_PERFCOUNTER2_HI', + 'mmCHC_PERFCOUNTER2_HI_BASE_IDX', 'mmCHC_PERFCOUNTER2_LO', + 'mmCHC_PERFCOUNTER2_LO_BASE_IDX', 'mmCHC_PERFCOUNTER2_SELECT', + 'mmCHC_PERFCOUNTER2_SELECT_BASE_IDX', 'mmCHC_PERFCOUNTER3_HI', + 'mmCHC_PERFCOUNTER3_HI_BASE_IDX', 'mmCHC_PERFCOUNTER3_LO', + 'mmCHC_PERFCOUNTER3_LO_BASE_IDX', 'mmCHC_PERFCOUNTER3_SELECT', + 'mmCHC_PERFCOUNTER3_SELECT_BASE_IDX', 'mmCHC_STATUS', + 'mmCHC_STATUS_BASE_IDX', 'mmCH_ARB_CTRL', + 'mmCH_ARB_CTRL_BASE_IDX', 'mmCH_ARB_STATUS', + 'mmCH_ARB_STATUS_BASE_IDX', 'mmCH_DRAM_BURST_CTRL', + 'mmCH_DRAM_BURST_CTRL_BASE_IDX', 'mmCH_DRAM_BURST_MASK', + 'mmCH_DRAM_BURST_MASK_BASE_IDX', 'mmCH_PIPE_STEER', + 'mmCH_PIPE_STEER_BASE_IDX', 'mmCH_VC5_ENABLE', + 'mmCH_VC5_ENABLE_BASE_IDX', 'mmCOHER_DEST_BASE_0', + 'mmCOHER_DEST_BASE_0_BASE_IDX', 'mmCOHER_DEST_BASE_1', + 'mmCOHER_DEST_BASE_1_BASE_IDX', 'mmCOHER_DEST_BASE_2', + 'mmCOHER_DEST_BASE_2_BASE_IDX', 'mmCOHER_DEST_BASE_3', + 'mmCOHER_DEST_BASE_3_BASE_IDX', 'mmCOHER_DEST_BASE_HI_0', + 'mmCOHER_DEST_BASE_HI_0_BASE_IDX', 'mmCOHER_DEST_BASE_HI_1', + 'mmCOHER_DEST_BASE_HI_1_BASE_IDX', 'mmCOHER_DEST_BASE_HI_2', + 'mmCOHER_DEST_BASE_HI_2_BASE_IDX', 'mmCOHER_DEST_BASE_HI_3', + 'mmCOHER_DEST_BASE_HI_3_BASE_IDX', 'mmCOMPUTE_DDID_INDEX', + 'mmCOMPUTE_DDID_INDEX_BASE_IDX', 'mmCOMPUTE_DESTINATION_EN_SE0', + 'mmCOMPUTE_DESTINATION_EN_SE0_BASE_IDX', + 'mmCOMPUTE_DESTINATION_EN_SE1', + 'mmCOMPUTE_DESTINATION_EN_SE1_BASE_IDX', + 'mmCOMPUTE_DESTINATION_EN_SE2', + 'mmCOMPUTE_DESTINATION_EN_SE2_BASE_IDX', + 'mmCOMPUTE_DESTINATION_EN_SE3', + 'mmCOMPUTE_DESTINATION_EN_SE3_BASE_IDX', 'mmCOMPUTE_DIM_X', + 'mmCOMPUTE_DIM_X_BASE_IDX', 'mmCOMPUTE_DIM_Y', + 'mmCOMPUTE_DIM_Y_BASE_IDX', 'mmCOMPUTE_DIM_Z', + 'mmCOMPUTE_DIM_Z_BASE_IDX', 'mmCOMPUTE_DISPATCH_END', + 'mmCOMPUTE_DISPATCH_END_BASE_IDX', 'mmCOMPUTE_DISPATCH_ID', + 'mmCOMPUTE_DISPATCH_ID_BASE_IDX', 'mmCOMPUTE_DISPATCH_INITIATOR', + 'mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX', + 'mmCOMPUTE_DISPATCH_PKT_ADDR_HI', + 'mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX', + 'mmCOMPUTE_DISPATCH_PKT_ADDR_LO', + 'mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX', + 'mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI', + 'mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX', + 'mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO', + 'mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX', + 'mmCOMPUTE_DISPATCH_TUNNEL', 'mmCOMPUTE_DISPATCH_TUNNEL_BASE_IDX', + 'mmCOMPUTE_MISC_RESERVED', 'mmCOMPUTE_MISC_RESERVED_BASE_IDX', + 'mmCOMPUTE_NOWHERE', 'mmCOMPUTE_NOWHERE_BASE_IDX', + 'mmCOMPUTE_NUM_THREAD_X', 'mmCOMPUTE_NUM_THREAD_X_BASE_IDX', + 'mmCOMPUTE_NUM_THREAD_Y', 'mmCOMPUTE_NUM_THREAD_Y_BASE_IDX', + 'mmCOMPUTE_NUM_THREAD_Z', 'mmCOMPUTE_NUM_THREAD_Z_BASE_IDX', + 'mmCOMPUTE_PERFCOUNT_ENABLE', + 'mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX', 'mmCOMPUTE_PGM_HI', + 'mmCOMPUTE_PGM_HI_BASE_IDX', 'mmCOMPUTE_PGM_LO', + 'mmCOMPUTE_PGM_LO_BASE_IDX', 'mmCOMPUTE_PGM_RSRC1', + 'mmCOMPUTE_PGM_RSRC1_BASE_IDX', 'mmCOMPUTE_PGM_RSRC2', + 'mmCOMPUTE_PGM_RSRC2_BASE_IDX', 'mmCOMPUTE_PGM_RSRC3', + 'mmCOMPUTE_PGM_RSRC3_BASE_IDX', 'mmCOMPUTE_PIPELINESTAT_ENABLE', + 'mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX', 'mmCOMPUTE_RELAUNCH', + 'mmCOMPUTE_RELAUNCH2', 'mmCOMPUTE_RELAUNCH2_BASE_IDX', + 'mmCOMPUTE_RELAUNCH_BASE_IDX', 'mmCOMPUTE_REQ_CTRL', + 'mmCOMPUTE_REQ_CTRL_BASE_IDX', 'mmCOMPUTE_RESOURCE_LIMITS', + 'mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX', 'mmCOMPUTE_RESTART_X', + 'mmCOMPUTE_RESTART_X_BASE_IDX', 'mmCOMPUTE_RESTART_Y', + 'mmCOMPUTE_RESTART_Y_BASE_IDX', 'mmCOMPUTE_RESTART_Z', + 'mmCOMPUTE_RESTART_Z_BASE_IDX', 'mmCOMPUTE_SHADER_CHKSUM', + 'mmCOMPUTE_SHADER_CHKSUM_BASE_IDX', 'mmCOMPUTE_START_X', + 'mmCOMPUTE_START_X_BASE_IDX', 'mmCOMPUTE_START_Y', + 'mmCOMPUTE_START_Y_BASE_IDX', 'mmCOMPUTE_START_Z', + 'mmCOMPUTE_START_Z_BASE_IDX', 'mmCOMPUTE_STATIC_THREAD_MGMT_SE0', + 'mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX', + 'mmCOMPUTE_STATIC_THREAD_MGMT_SE1', + 'mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX', + 'mmCOMPUTE_STATIC_THREAD_MGMT_SE2', + 'mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX', + 'mmCOMPUTE_STATIC_THREAD_MGMT_SE3', + 'mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX', + 'mmCOMPUTE_THREADGROUP_ID', 'mmCOMPUTE_THREADGROUP_ID_BASE_IDX', + 'mmCOMPUTE_THREAD_TRACE_ENABLE', + 'mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX', + 'mmCOMPUTE_TMPRING_SIZE', 'mmCOMPUTE_TMPRING_SIZE_BASE_IDX', + 'mmCOMPUTE_USER_ACCUM_0', 'mmCOMPUTE_USER_ACCUM_0_BASE_IDX', + 'mmCOMPUTE_USER_ACCUM_1', 'mmCOMPUTE_USER_ACCUM_1_BASE_IDX', + 'mmCOMPUTE_USER_ACCUM_2', 'mmCOMPUTE_USER_ACCUM_2_BASE_IDX', + 'mmCOMPUTE_USER_ACCUM_3', 'mmCOMPUTE_USER_ACCUM_3_BASE_IDX', + 'mmCOMPUTE_USER_DATA_0', 'mmCOMPUTE_USER_DATA_0_BASE_IDX', + 'mmCOMPUTE_USER_DATA_1', 'mmCOMPUTE_USER_DATA_10', + 'mmCOMPUTE_USER_DATA_10_BASE_IDX', 'mmCOMPUTE_USER_DATA_11', + 'mmCOMPUTE_USER_DATA_11_BASE_IDX', 'mmCOMPUTE_USER_DATA_12', + 'mmCOMPUTE_USER_DATA_12_BASE_IDX', 'mmCOMPUTE_USER_DATA_13', + 'mmCOMPUTE_USER_DATA_13_BASE_IDX', 'mmCOMPUTE_USER_DATA_14', + 'mmCOMPUTE_USER_DATA_14_BASE_IDX', 'mmCOMPUTE_USER_DATA_15', + 'mmCOMPUTE_USER_DATA_15_BASE_IDX', + 'mmCOMPUTE_USER_DATA_1_BASE_IDX', 'mmCOMPUTE_USER_DATA_2', + 'mmCOMPUTE_USER_DATA_2_BASE_IDX', 'mmCOMPUTE_USER_DATA_3', + 'mmCOMPUTE_USER_DATA_3_BASE_IDX', 'mmCOMPUTE_USER_DATA_4', + 'mmCOMPUTE_USER_DATA_4_BASE_IDX', 'mmCOMPUTE_USER_DATA_5', + 'mmCOMPUTE_USER_DATA_5_BASE_IDX', 'mmCOMPUTE_USER_DATA_6', + 'mmCOMPUTE_USER_DATA_6_BASE_IDX', 'mmCOMPUTE_USER_DATA_7', + 'mmCOMPUTE_USER_DATA_7_BASE_IDX', 'mmCOMPUTE_USER_DATA_8', + 'mmCOMPUTE_USER_DATA_8_BASE_IDX', 'mmCOMPUTE_USER_DATA_9', + 'mmCOMPUTE_USER_DATA_9_BASE_IDX', 'mmCOMPUTE_VMID', + 'mmCOMPUTE_VMID_BASE_IDX', 'mmCOMPUTE_WAVE_RESTORE_ADDR_HI', + 'mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX', + 'mmCOMPUTE_WAVE_RESTORE_ADDR_LO', + 'mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX', + 'mmCONFIG_RESERVED_REG0', 'mmCONFIG_RESERVED_REG0_BASE_IDX', + 'mmCONFIG_RESERVED_REG1', 'mmCONFIG_RESERVED_REG1_BASE_IDX', + 'mmCONTEXT_RESERVED_REG0', 'mmCONTEXT_RESERVED_REG0_BASE_IDX', + 'mmCONTEXT_RESERVED_REG1', 'mmCONTEXT_RESERVED_REG1_BASE_IDX', + 'mmCPC_DDID_BASE_ADDR_HI', 'mmCPC_DDID_BASE_ADDR_HI_BASE_IDX', + 'mmCPC_DDID_BASE_ADDR_LO', 'mmCPC_DDID_BASE_ADDR_LO_BASE_IDX', + 'mmCPC_DDID_CNTL', 'mmCPC_DDID_CNTL_BASE_IDX', 'mmCPC_INT_ADDR', + 'mmCPC_INT_ADDR_BASE_IDX', 'mmCPC_INT_CNTL', + 'mmCPC_INT_CNTL_BASE_IDX', 'mmCPC_INT_CNTX_ID', + 'mmCPC_INT_CNTX_ID_BASE_IDX', 'mmCPC_INT_INFO', + 'mmCPC_INT_INFO_BASE_IDX', 'mmCPC_INT_PASID', + 'mmCPC_INT_PASID_BASE_IDX', 'mmCPC_INT_STATUS', + 'mmCPC_INT_STATUS_BASE_IDX', 'mmCPC_LATENCY_STATS_DATA', + 'mmCPC_LATENCY_STATS_DATA_BASE_IDX', 'mmCPC_LATENCY_STATS_SELECT', + 'mmCPC_LATENCY_STATS_SELECT_BASE_IDX', 'mmCPC_OS_PIPES', + 'mmCPC_OS_PIPES_BASE_IDX', 'mmCPC_PERFCOUNTER0_HI', + 'mmCPC_PERFCOUNTER0_HI_BASE_IDX', 'mmCPC_PERFCOUNTER0_LO', + 'mmCPC_PERFCOUNTER0_LO_BASE_IDX', 'mmCPC_PERFCOUNTER0_SELECT', + 'mmCPC_PERFCOUNTER0_SELECT1', + 'mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmCPC_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCPC_PERFCOUNTER1_HI', + 'mmCPC_PERFCOUNTER1_HI_BASE_IDX', 'mmCPC_PERFCOUNTER1_LO', + 'mmCPC_PERFCOUNTER1_LO_BASE_IDX', 'mmCPC_PERFCOUNTER1_SELECT', + 'mmCPC_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCPC_PSP_DEBUG', + 'mmCPC_PSP_DEBUG_BASE_IDX', 'mmCPC_SUSPEND_CNTL_STACK_OFFSET', + 'mmCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX', + 'mmCPC_SUSPEND_CNTL_STACK_SIZE', + 'mmCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX', + 'mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI', + 'mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX', + 'mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO', + 'mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX', + 'mmCPC_SUSPEND_CTX_SAVE_CONTROL', + 'mmCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX', + 'mmCPC_SUSPEND_CTX_SAVE_SIZE', + 'mmCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX', + 'mmCPC_SUSPEND_WG_STATE_OFFSET', + 'mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX', 'mmCPC_UTCL1_CNTL', + 'mmCPC_UTCL1_CNTL_BASE_IDX', 'mmCPC_UTCL1_ERROR', + 'mmCPC_UTCL1_ERROR_BASE_IDX', 'mmCPC_UTCL1_STATUS', + 'mmCPC_UTCL1_STATUS_BASE_IDX', 'mmCPF_GCR_CNTL', + 'mmCPF_GCR_CNTL_BASE_IDX', 'mmCPF_LATENCY_STATS_DATA', + 'mmCPF_LATENCY_STATS_DATA_BASE_IDX', 'mmCPF_LATENCY_STATS_SELECT', + 'mmCPF_LATENCY_STATS_SELECT_BASE_IDX', 'mmCPF_PERFCOUNTER0_HI', + 'mmCPF_PERFCOUNTER0_HI_BASE_IDX', 'mmCPF_PERFCOUNTER0_LO', + 'mmCPF_PERFCOUNTER0_LO_BASE_IDX', 'mmCPF_PERFCOUNTER0_SELECT', + 'mmCPF_PERFCOUNTER0_SELECT1', + 'mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmCPF_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCPF_PERFCOUNTER1_HI', + 'mmCPF_PERFCOUNTER1_HI_BASE_IDX', 'mmCPF_PERFCOUNTER1_LO', + 'mmCPF_PERFCOUNTER1_LO_BASE_IDX', 'mmCPF_PERFCOUNTER1_SELECT', + 'mmCPF_PERFCOUNTER1_SELECT_BASE_IDX', + 'mmCPF_TC_PERF_COUNTER_WINDOW_SELECT', + 'mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', + 'mmCPF_UTCL1_CNTL', 'mmCPF_UTCL1_CNTL_BASE_IDX', + 'mmCPF_UTCL1_STATUS', 'mmCPF_UTCL1_STATUS_BASE_IDX', + 'mmCPG_LATENCY_STATS_DATA', 'mmCPG_LATENCY_STATS_DATA_BASE_IDX', + 'mmCPG_LATENCY_STATS_SELECT', + 'mmCPG_LATENCY_STATS_SELECT_BASE_IDX', 'mmCPG_PERFCOUNTER0_HI', + 'mmCPG_PERFCOUNTER0_HI_BASE_IDX', 'mmCPG_PERFCOUNTER0_LO', + 'mmCPG_PERFCOUNTER0_LO_BASE_IDX', 'mmCPG_PERFCOUNTER0_SELECT', + 'mmCPG_PERFCOUNTER0_SELECT1', + 'mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmCPG_PERFCOUNTER0_SELECT_BASE_IDX', 'mmCPG_PERFCOUNTER1_HI', + 'mmCPG_PERFCOUNTER1_HI_BASE_IDX', 'mmCPG_PERFCOUNTER1_LO', + 'mmCPG_PERFCOUNTER1_LO_BASE_IDX', 'mmCPG_PERFCOUNTER1_SELECT', + 'mmCPG_PERFCOUNTER1_SELECT_BASE_IDX', 'mmCPG_PSP_DEBUG', + 'mmCPG_PSP_DEBUG_BASE_IDX', 'mmCPG_RCIU_CAM_DATA', + 'mmCPG_RCIU_CAM_DATA_BASE_IDX', 'mmCPG_RCIU_CAM_DATA_PHASE0', + 'mmCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX', + 'mmCPG_RCIU_CAM_DATA_PHASE1', + 'mmCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX', + 'mmCPG_RCIU_CAM_DATA_PHASE2', + 'mmCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX', 'mmCPG_RCIU_CAM_INDEX', + 'mmCPG_RCIU_CAM_INDEX_BASE_IDX', + 'mmCPG_TC_PERF_COUNTER_WINDOW_SELECT', + 'mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX', + 'mmCPG_UTCL1_CNTL', 'mmCPG_UTCL1_CNTL_BASE_IDX', + 'mmCPG_UTCL1_ERROR', 'mmCPG_UTCL1_ERROR_BASE_IDX', + 'mmCPG_UTCL1_STATUS', 'mmCPG_UTCL1_STATUS_BASE_IDX', + 'mmCP_APPEND_ADDR_HI', 'mmCP_APPEND_ADDR_HI_BASE_IDX', + 'mmCP_APPEND_ADDR_LO', 'mmCP_APPEND_ADDR_LO_BASE_IDX', + 'mmCP_APPEND_CMD_ADDR_HI', 'mmCP_APPEND_CMD_ADDR_HI_BASE_IDX', + 'mmCP_APPEND_CMD_ADDR_LO', 'mmCP_APPEND_CMD_ADDR_LO_BASE_IDX', + 'mmCP_APPEND_DATA', 'mmCP_APPEND_DATA_BASE_IDX', + 'mmCP_APPEND_DATA_HI', 'mmCP_APPEND_DATA_HI_BASE_IDX', + 'mmCP_APPEND_DATA_LO', 'mmCP_APPEND_DATA_LO_BASE_IDX', + 'mmCP_APPEND_DDID_CNT', 'mmCP_APPEND_DDID_CNT_BASE_IDX', + 'mmCP_APPEND_LAST_CS_FENCE', 'mmCP_APPEND_LAST_CS_FENCE_BASE_IDX', + 'mmCP_APPEND_LAST_CS_FENCE_HI', + 'mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX', + 'mmCP_APPEND_LAST_CS_FENCE_LO', + 'mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX', + 'mmCP_APPEND_LAST_PS_FENCE', 'mmCP_APPEND_LAST_PS_FENCE_BASE_IDX', + 'mmCP_APPEND_LAST_PS_FENCE_HI', + 'mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX', + 'mmCP_APPEND_LAST_PS_FENCE_LO', + 'mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX', 'mmCP_AQL_SMM_STATUS', + 'mmCP_AQL_SMM_STATUS_BASE_IDX', 'mmCP_ATOMIC_PREOP_HI', + 'mmCP_ATOMIC_PREOP_HI_BASE_IDX', 'mmCP_ATOMIC_PREOP_LO', + 'mmCP_ATOMIC_PREOP_LO_BASE_IDX', 'mmCP_BUSY_STAT', + 'mmCP_BUSY_STAT_BASE_IDX', 'mmCP_CEQ1_AVAIL', + 'mmCP_CEQ1_AVAIL_BASE_IDX', 'mmCP_CEQ2_AVAIL', + 'mmCP_CEQ2_AVAIL_BASE_IDX', 'mmCP_CE_ATOMIC_PREOP_HI', + 'mmCP_CE_ATOMIC_PREOP_HI_BASE_IDX', 'mmCP_CE_ATOMIC_PREOP_LO', + 'mmCP_CE_ATOMIC_PREOP_LO_BASE_IDX', 'mmCP_CE_COMPARE_COUNT', + 'mmCP_CE_COMPARE_COUNT_BASE_IDX', 'mmCP_CE_COMPLETION_STATUS', + 'mmCP_CE_COMPLETION_STATUS_BASE_IDX', 'mmCP_CE_COUNTER', + 'mmCP_CE_COUNTER_BASE_IDX', 'mmCP_CE_CS_PARTITION_INDEX', + 'mmCP_CE_CS_PARTITION_INDEX_BASE_IDX', 'mmCP_CE_DB_BASE_HI', + 'mmCP_CE_DB_BASE_HI_BASE_IDX', 'mmCP_CE_DB_BASE_LO', + 'mmCP_CE_DB_BASE_LO_BASE_IDX', 'mmCP_CE_DB_BUFSZ', + 'mmCP_CE_DB_BUFSZ_BASE_IDX', 'mmCP_CE_DB_CMD_BUFSZ', + 'mmCP_CE_DB_CMD_BUFSZ_BASE_IDX', 'mmCP_CE_DE_COUNT', + 'mmCP_CE_DE_COUNT_BASE_IDX', 'mmCP_CE_DOORBELL_CONTROL', + 'mmCP_CE_DOORBELL_CONTROL_BASE_IDX', 'mmCP_CE_F32_INTERRUPT', + 'mmCP_CE_F32_INTERRUPT_BASE_IDX', 'mmCP_CE_GDS_ATOMIC0_PREOP_HI', + 'mmCP_CE_GDS_ATOMIC0_PREOP_HI_BASE_IDX', + 'mmCP_CE_GDS_ATOMIC0_PREOP_LO', + 'mmCP_CE_GDS_ATOMIC0_PREOP_LO_BASE_IDX', + 'mmCP_CE_GDS_ATOMIC1_PREOP_HI', + 'mmCP_CE_GDS_ATOMIC1_PREOP_HI_BASE_IDX', + 'mmCP_CE_GDS_ATOMIC1_PREOP_LO', + 'mmCP_CE_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'mmCP_CE_HEADER_DUMP', + 'mmCP_CE_HEADER_DUMP_BASE_IDX', 'mmCP_CE_IB1_BASE_HI', + 'mmCP_CE_IB1_BASE_HI_BASE_IDX', 'mmCP_CE_IB1_BASE_LO', + 'mmCP_CE_IB1_BASE_LO_BASE_IDX', 'mmCP_CE_IB1_BUFSZ', + 'mmCP_CE_IB1_BUFSZ_BASE_IDX', 'mmCP_CE_IB1_CMD_BUFSZ', + 'mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX', 'mmCP_CE_IB1_OFFSET', + 'mmCP_CE_IB1_OFFSET_BASE_IDX', 'mmCP_CE_IB2_BASE_HI', + 'mmCP_CE_IB2_BASE_HI_BASE_IDX', 'mmCP_CE_IB2_BASE_LO', + 'mmCP_CE_IB2_BASE_LO_BASE_IDX', 'mmCP_CE_IB2_BUFSZ', + 'mmCP_CE_IB2_BUFSZ_BASE_IDX', 'mmCP_CE_IB2_CMD_BUFSZ', + 'mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX', 'mmCP_CE_IB2_OFFSET', + 'mmCP_CE_IB2_OFFSET_BASE_IDX', 'mmCP_CE_IC_BASE_CNTL', + 'mmCP_CE_IC_BASE_CNTL_BASE_IDX', 'mmCP_CE_IC_BASE_HI', + 'mmCP_CE_IC_BASE_HI_BASE_IDX', 'mmCP_CE_IC_BASE_LO', + 'mmCP_CE_IC_BASE_LO_BASE_IDX', 'mmCP_CE_IC_OP_CNTL', + 'mmCP_CE_IC_OP_CNTL_BASE_IDX', 'mmCP_CE_INIT_BASE_HI', + 'mmCP_CE_INIT_BASE_HI_BASE_IDX', 'mmCP_CE_INIT_BASE_LO', + 'mmCP_CE_INIT_BASE_LO_BASE_IDX', 'mmCP_CE_INIT_BUFSZ', + 'mmCP_CE_INIT_BUFSZ_BASE_IDX', 'mmCP_CE_INIT_CMD_BUFSZ', + 'mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX', 'mmCP_CE_INSTR_PNTR', + 'mmCP_CE_INSTR_PNTR_BASE_IDX', 'mmCP_CE_INTR_ROUTINE_START', + 'mmCP_CE_INTR_ROUTINE_START_BASE_IDX', 'mmCP_CE_JT_STAT', + 'mmCP_CE_JT_STAT_BASE_IDX', 'mmCP_CE_METADATA_BASE_ADDR', + 'mmCP_CE_METADATA_BASE_ADDR_BASE_IDX', + 'mmCP_CE_METADATA_BASE_ADDR_HI', + 'mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX', + 'mmCP_CE_PRGRM_CNTR_START', 'mmCP_CE_PRGRM_CNTR_START_BASE_IDX', + 'mmCP_CE_ROQ_DB_STAT', 'mmCP_CE_ROQ_DB_STAT_BASE_IDX', + 'mmCP_CE_ROQ_IB1_STAT', 'mmCP_CE_ROQ_IB1_STAT_BASE_IDX', + 'mmCP_CE_ROQ_IB2_STAT', 'mmCP_CE_ROQ_IB2_STAT_BASE_IDX', + 'mmCP_CE_ROQ_RB_STAT', 'mmCP_CE_ROQ_RB_STAT_BASE_IDX', + 'mmCP_CE_UCODE_ADDR', 'mmCP_CE_UCODE_ADDR_BASE_IDX', + 'mmCP_CE_UCODE_DATA', 'mmCP_CE_UCODE_DATA_BASE_IDX', + 'mmCP_CMD_DATA', 'mmCP_CMD_DATA_BASE_IDX', 'mmCP_CMD_INDEX', + 'mmCP_CMD_INDEX_BASE_IDX', 'mmCP_CNTX_STAT', + 'mmCP_CNTX_STAT_BASE_IDX', 'mmCP_COHER_BASE', + 'mmCP_COHER_BASE_BASE_IDX', 'mmCP_COHER_BASE_HI', + 'mmCP_COHER_BASE_HI_BASE_IDX', 'mmCP_COHER_CNTL', + 'mmCP_COHER_CNTL_BASE_IDX', 'mmCP_COHER_SIZE', + 'mmCP_COHER_SIZE_BASE_IDX', 'mmCP_COHER_SIZE_HI', + 'mmCP_COHER_SIZE_HI_BASE_IDX', 'mmCP_COHER_START_DELAY', + 'mmCP_COHER_START_DELAY_BASE_IDX', 'mmCP_COHER_STATUS', + 'mmCP_COHER_STATUS_BASE_IDX', 'mmCP_CONTEXT_CNTL', + 'mmCP_CONTEXT_CNTL_BASE_IDX', 'mmCP_CPC_BUSY_STAT', + 'mmCP_CPC_BUSY_STAT2', 'mmCP_CPC_BUSY_STAT2_BASE_IDX', + 'mmCP_CPC_BUSY_STAT_BASE_IDX', 'mmCP_CPC_GFX_CNTL', + 'mmCP_CPC_GFX_CNTL_BASE_IDX', 'mmCP_CPC_GRBM_FREE_COUNT', + 'mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX', 'mmCP_CPC_HALT_HYST_COUNT', + 'mmCP_CPC_HALT_HYST_COUNT_BASE_IDX', 'mmCP_CPC_IC_BASE_CNTL', + 'mmCP_CPC_IC_BASE_CNTL_BASE_IDX', 'mmCP_CPC_IC_BASE_HI', + 'mmCP_CPC_IC_BASE_HI_BASE_IDX', 'mmCP_CPC_IC_BASE_LO', + 'mmCP_CPC_IC_BASE_LO_BASE_IDX', 'mmCP_CPC_IC_OP_CNTL', + 'mmCP_CPC_IC_OP_CNTL_BASE_IDX', 'mmCP_CPC_MGCG_SYNC_CNTL', + 'mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX', + 'mmCP_CPC_PRIV_VIOLATION_ADDR', + 'mmCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX', 'mmCP_CPC_SCRATCH_DATA', + 'mmCP_CPC_SCRATCH_DATA_BASE_IDX', 'mmCP_CPC_SCRATCH_INDEX', + 'mmCP_CPC_SCRATCH_INDEX_BASE_IDX', 'mmCP_CPC_STALLED_STAT1', + 'mmCP_CPC_STALLED_STAT1_BASE_IDX', 'mmCP_CPC_STATUS', + 'mmCP_CPC_STATUS_BASE_IDX', 'mmCP_CPF_BUSY_STAT', + 'mmCP_CPF_BUSY_STAT2', 'mmCP_CPF_BUSY_STAT2_BASE_IDX', + 'mmCP_CPF_BUSY_STAT_BASE_IDX', 'mmCP_CPF_GRBM_FREE_COUNT', + 'mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX', 'mmCP_CPF_STALLED_STAT1', + 'mmCP_CPF_STALLED_STAT1_BASE_IDX', 'mmCP_CPF_STATUS', + 'mmCP_CPF_STATUS_BASE_IDX', 'mmCP_CSF_STAT', + 'mmCP_CSF_STAT_BASE_IDX', 'mmCP_DB_BASE_HI', + 'mmCP_DB_BASE_HI_BASE_IDX', 'mmCP_DB_BASE_LO', + 'mmCP_DB_BASE_LO_BASE_IDX', 'mmCP_DB_BUFSZ', + 'mmCP_DB_BUFSZ_BASE_IDX', 'mmCP_DB_CMD_BUFSZ', + 'mmCP_DB_CMD_BUFSZ_BASE_IDX', 'mmCP_DDID_BASE_ADDR_HI', + 'mmCP_DDID_BASE_ADDR_HI_BASE_IDX', 'mmCP_DDID_BASE_ADDR_LO', + 'mmCP_DDID_BASE_ADDR_LO_BASE_IDX', 'mmCP_DDID_CNTL', + 'mmCP_DDID_CNTL_BASE_IDX', 'mmCP_DEVICE_ID', + 'mmCP_DEVICE_ID_BASE_IDX', 'mmCP_DE_CE_COUNT', + 'mmCP_DE_CE_COUNT_BASE_IDX', 'mmCP_DE_DE_COUNT', + 'mmCP_DE_DE_COUNT_BASE_IDX', 'mmCP_DE_LAST_INVAL_COUNT', + 'mmCP_DE_LAST_INVAL_COUNT_BASE_IDX', 'mmCP_DISPATCH_INDR_ADDR', + 'mmCP_DISPATCH_INDR_ADDR_BASE_IDX', 'mmCP_DISPATCH_INDR_ADDR_HI', + 'mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX', 'mmCP_DMA_CNTL', + 'mmCP_DMA_CNTL_BASE_IDX', 'mmCP_DMA_ME_CMD_ADDR_HI', + 'mmCP_DMA_ME_CMD_ADDR_HI_BASE_IDX', 'mmCP_DMA_ME_CMD_ADDR_LO', + 'mmCP_DMA_ME_CMD_ADDR_LO_BASE_IDX', 'mmCP_DMA_ME_COMMAND', + 'mmCP_DMA_ME_COMMAND_BASE_IDX', 'mmCP_DMA_ME_CONTROL', + 'mmCP_DMA_ME_CONTROL_BASE_IDX', 'mmCP_DMA_ME_DST_ADDR', + 'mmCP_DMA_ME_DST_ADDR_BASE_IDX', 'mmCP_DMA_ME_DST_ADDR_HI', + 'mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX', 'mmCP_DMA_ME_SRC_ADDR', + 'mmCP_DMA_ME_SRC_ADDR_BASE_IDX', 'mmCP_DMA_ME_SRC_ADDR_HI', + 'mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX', 'mmCP_DMA_PFP_CMD_ADDR_HI', + 'mmCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX', 'mmCP_DMA_PFP_CMD_ADDR_LO', + 'mmCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX', 'mmCP_DMA_PFP_COMMAND', + 'mmCP_DMA_PFP_COMMAND_BASE_IDX', 'mmCP_DMA_PFP_CONTROL', + 'mmCP_DMA_PFP_CONTROL_BASE_IDX', 'mmCP_DMA_PFP_DST_ADDR', + 'mmCP_DMA_PFP_DST_ADDR_BASE_IDX', 'mmCP_DMA_PFP_DST_ADDR_HI', + 'mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX', 'mmCP_DMA_PFP_SRC_ADDR', + 'mmCP_DMA_PFP_SRC_ADDR_BASE_IDX', 'mmCP_DMA_PFP_SRC_ADDR_HI', + 'mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX', 'mmCP_DMA_READ_TAGS', + 'mmCP_DMA_READ_TAGS_BASE_IDX', 'mmCP_DMA_WATCH0_ADDR_HI', + 'mmCP_DMA_WATCH0_ADDR_HI_BASE_IDX', 'mmCP_DMA_WATCH0_ADDR_LO', + 'mmCP_DMA_WATCH0_ADDR_LO_BASE_IDX', 'mmCP_DMA_WATCH0_CNTL', + 'mmCP_DMA_WATCH0_CNTL_BASE_IDX', 'mmCP_DMA_WATCH0_MASK', + 'mmCP_DMA_WATCH0_MASK_BASE_IDX', 'mmCP_DMA_WATCH1_ADDR_HI', + 'mmCP_DMA_WATCH1_ADDR_HI_BASE_IDX', 'mmCP_DMA_WATCH1_ADDR_LO', + 'mmCP_DMA_WATCH1_ADDR_LO_BASE_IDX', 'mmCP_DMA_WATCH1_CNTL', + 'mmCP_DMA_WATCH1_CNTL_BASE_IDX', 'mmCP_DMA_WATCH1_MASK', + 'mmCP_DMA_WATCH1_MASK_BASE_IDX', 'mmCP_DMA_WATCH2_ADDR_HI', + 'mmCP_DMA_WATCH2_ADDR_HI_BASE_IDX', 'mmCP_DMA_WATCH2_ADDR_LO', + 'mmCP_DMA_WATCH2_ADDR_LO_BASE_IDX', 'mmCP_DMA_WATCH2_CNTL', + 'mmCP_DMA_WATCH2_CNTL_BASE_IDX', 'mmCP_DMA_WATCH2_MASK', + 'mmCP_DMA_WATCH2_MASK_BASE_IDX', 'mmCP_DMA_WATCH3_ADDR_HI', + 'mmCP_DMA_WATCH3_ADDR_HI_BASE_IDX', 'mmCP_DMA_WATCH3_ADDR_LO', + 'mmCP_DMA_WATCH3_ADDR_LO_BASE_IDX', 'mmCP_DMA_WATCH3_CNTL', + 'mmCP_DMA_WATCH3_CNTL_BASE_IDX', 'mmCP_DMA_WATCH3_MASK', + 'mmCP_DMA_WATCH3_MASK_BASE_IDX', 'mmCP_DMA_WATCH_STAT', + 'mmCP_DMA_WATCH_STAT_ADDR_HI', + 'mmCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX', + 'mmCP_DMA_WATCH_STAT_ADDR_LO', + 'mmCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX', + 'mmCP_DMA_WATCH_STAT_BASE_IDX', 'mmCP_DRAW_INDX_INDR_ADDR', + 'mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX', + 'mmCP_DRAW_INDX_INDR_ADDR_HI', + 'mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX', 'mmCP_DRAW_OBJECT', + 'mmCP_DRAW_OBJECT_BASE_IDX', 'mmCP_DRAW_OBJECT_COUNTER', + 'mmCP_DRAW_OBJECT_COUNTER_BASE_IDX', 'mmCP_DRAW_WINDOW_CNTL', + 'mmCP_DRAW_WINDOW_CNTL_BASE_IDX', 'mmCP_DRAW_WINDOW_HI', + 'mmCP_DRAW_WINDOW_HI_BASE_IDX', 'mmCP_DRAW_WINDOW_LO', + 'mmCP_DRAW_WINDOW_LO_BASE_IDX', 'mmCP_DRAW_WINDOW_MASK_HI', + 'mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX', 'mmCP_ECC_FIRSTOCCURRENCE', + 'mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX', + 'mmCP_ECC_FIRSTOCCURRENCE_RING0', + 'mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX', + 'mmCP_ECC_FIRSTOCCURRENCE_RING1', + 'mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX', + 'mmCP_ECC_FIRSTOCCURRENCE_RING2', + 'mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX', 'mmCP_EOPQ_WAIT_TIME', + 'mmCP_EOPQ_WAIT_TIME_BASE_IDX', 'mmCP_EOP_DONE_ADDR_HI', + 'mmCP_EOP_DONE_ADDR_HI_BASE_IDX', 'mmCP_EOP_DONE_ADDR_LO', + 'mmCP_EOP_DONE_ADDR_LO_BASE_IDX', 'mmCP_EOP_DONE_CNTX_ID', + 'mmCP_EOP_DONE_CNTX_ID_BASE_IDX', 'mmCP_EOP_DONE_DATA_CNTL', + 'mmCP_EOP_DONE_DATA_CNTL_BASE_IDX', 'mmCP_EOP_DONE_DATA_HI', + 'mmCP_EOP_DONE_DATA_HI_BASE_IDX', 'mmCP_EOP_DONE_DATA_LO', + 'mmCP_EOP_DONE_DATA_LO_BASE_IDX', 'mmCP_EOP_DONE_EVENT_CNTL', + 'mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX', 'mmCP_EOP_LAST_FENCE_HI', + 'mmCP_EOP_LAST_FENCE_HI_BASE_IDX', 'mmCP_EOP_LAST_FENCE_LO', + 'mmCP_EOP_LAST_FENCE_LO_BASE_IDX', 'mmCP_FATAL_ERROR', + 'mmCP_FATAL_ERROR_BASE_IDX', 'mmCP_FETCHER_SOURCE', + 'mmCP_FETCHER_SOURCE_BASE_IDX', 'mmCP_GDS_ATOMIC0_PREOP_HI', + 'mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', 'mmCP_GDS_ATOMIC0_PREOP_LO', + 'mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', 'mmCP_GDS_ATOMIC1_PREOP_HI', + 'mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', 'mmCP_GDS_ATOMIC1_PREOP_LO', + 'mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'mmCP_GDS_BKUP_ADDR', + 'mmCP_GDS_BKUP_ADDR_BASE_IDX', 'mmCP_GDS_BKUP_ADDR_HI', + 'mmCP_GDS_BKUP_ADDR_HI_BASE_IDX', 'mmCP_GFX_DDID_DELTA_RPT_COUNT', + 'mmCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX', + 'mmCP_GFX_DDID_INFLIGHT_COUNT', + 'mmCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX', 'mmCP_GFX_DDID_RPTR', + 'mmCP_GFX_DDID_RPTR_BASE_IDX', 'mmCP_GFX_DDID_WPTR', + 'mmCP_GFX_DDID_WPTR_BASE_IDX', 'mmCP_GFX_ERROR', + 'mmCP_GFX_ERROR_BASE_IDX', 'mmCP_GFX_HPD_CONTROL0', + 'mmCP_GFX_HPD_CONTROL0_BASE_IDX', + 'mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI', + 'mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX', + 'mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO', + 'mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX', + 'mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI', + 'mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX', + 'mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO', + 'mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX', + 'mmCP_GFX_HPD_STATUS0', 'mmCP_GFX_HPD_STATUS0_BASE_IDX', + 'mmCP_GFX_HQD_ACTIVE', 'mmCP_GFX_HQD_ACTIVE_BASE_IDX', + 'mmCP_GFX_HQD_BASE', 'mmCP_GFX_HQD_BASE_BASE_IDX', + 'mmCP_GFX_HQD_BASE_HI', 'mmCP_GFX_HQD_BASE_HI_BASE_IDX', + 'mmCP_GFX_HQD_CE_BASE', 'mmCP_GFX_HQD_CE_BASE_BASE_IDX', + 'mmCP_GFX_HQD_CE_BASE_HI', 'mmCP_GFX_HQD_CE_BASE_HI_BASE_IDX', + 'mmCP_GFX_HQD_CE_CNTL', 'mmCP_GFX_HQD_CE_CNTL_BASE_IDX', + 'mmCP_GFX_HQD_CE_CSMD_RPTR', 'mmCP_GFX_HQD_CE_CSMD_RPTR_BASE_IDX', + 'mmCP_GFX_HQD_CE_OFFSET', 'mmCP_GFX_HQD_CE_OFFSET_BASE_IDX', + 'mmCP_GFX_HQD_CE_RPTR', 'mmCP_GFX_HQD_CE_RPTR_ADDR', + 'mmCP_GFX_HQD_CE_RPTR_ADDR_BASE_IDX', + 'mmCP_GFX_HQD_CE_RPTR_ADDR_HI', + 'mmCP_GFX_HQD_CE_RPTR_ADDR_HI_BASE_IDX', + 'mmCP_GFX_HQD_CE_RPTR_BASE_IDX', 'mmCP_GFX_HQD_CE_RPTR_WR', + 'mmCP_GFX_HQD_CE_RPTR_WR_BASE_IDX', 'mmCP_GFX_HQD_CE_WPTR', + 'mmCP_GFX_HQD_CE_WPTR_BASE_IDX', 'mmCP_GFX_HQD_CE_WPTR_HI', + 'mmCP_GFX_HQD_CE_WPTR_HI_BASE_IDX', + 'mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI', + 'mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO', + 'mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO_BASE_IDX', 'mmCP_GFX_HQD_CNTL', + 'mmCP_GFX_HQD_CNTL_BASE_IDX', 'mmCP_GFX_HQD_CSMD_RPTR', + 'mmCP_GFX_HQD_CSMD_RPTR_BASE_IDX', 'mmCP_GFX_HQD_DEQUEUE_REQUEST', + 'mmCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX', + 'mmCP_GFX_HQD_HQ_CONTROL0', 'mmCP_GFX_HQD_HQ_CONTROL0_BASE_IDX', + 'mmCP_GFX_HQD_HQ_STATUS0', 'mmCP_GFX_HQD_HQ_STATUS0_BASE_IDX', + 'mmCP_GFX_HQD_MAPPED', 'mmCP_GFX_HQD_MAPPED_BASE_IDX', + 'mmCP_GFX_HQD_OFFSET', 'mmCP_GFX_HQD_OFFSET_BASE_IDX', + 'mmCP_GFX_HQD_QUANTUM', 'mmCP_GFX_HQD_QUANTUM_BASE_IDX', + 'mmCP_GFX_HQD_QUEUE_PRIORITY', + 'mmCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX', + 'mmCP_GFX_HQD_QUE_MGR_CONTROL', + 'mmCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX', 'mmCP_GFX_HQD_RPTR', + 'mmCP_GFX_HQD_RPTR_ADDR', 'mmCP_GFX_HQD_RPTR_ADDR_BASE_IDX', + 'mmCP_GFX_HQD_RPTR_ADDR_HI', 'mmCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX', + 'mmCP_GFX_HQD_RPTR_BASE_IDX', 'mmCP_GFX_HQD_VMID', + 'mmCP_GFX_HQD_VMID_BASE_IDX', 'mmCP_GFX_HQD_WPTR', + 'mmCP_GFX_HQD_WPTR_BASE_IDX', 'mmCP_GFX_HQD_WPTR_HI', + 'mmCP_GFX_HQD_WPTR_HI_BASE_IDX', 'mmCP_GFX_INDEX_MUTEX', + 'mmCP_GFX_INDEX_MUTEX_BASE_IDX', 'mmCP_GFX_MQD_BASE_ADDR', + 'mmCP_GFX_MQD_BASE_ADDR_BASE_IDX', 'mmCP_GFX_MQD_BASE_ADDR_HI', + 'mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX', 'mmCP_GFX_MQD_CONTROL', + 'mmCP_GFX_MQD_CONTROL_BASE_IDX', 'mmCP_GFX_QUEUE_INDEX', + 'mmCP_GFX_QUEUE_INDEX_BASE_IDX', 'mmCP_GPU_TIMESTAMP_OFFSET_HI', + 'mmCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX', + 'mmCP_GPU_TIMESTAMP_OFFSET_LO', + 'mmCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX', 'mmCP_GRBM_FREE_COUNT', + 'mmCP_GRBM_FREE_COUNT_BASE_IDX', 'mmCP_HPD_MES_ROQ_OFFSETS', + 'mmCP_HPD_MES_ROQ_OFFSETS_BASE_IDX', 'mmCP_HPD_ROQ_OFFSETS', + 'mmCP_HPD_ROQ_OFFSETS_BASE_IDX', 'mmCP_HPD_STATUS0', + 'mmCP_HPD_STATUS0_BASE_IDX', 'mmCP_HPD_UTCL1_CNTL', + 'mmCP_HPD_UTCL1_CNTL_BASE_IDX', 'mmCP_HPD_UTCL1_ERROR', + 'mmCP_HPD_UTCL1_ERROR_ADDR', 'mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX', + 'mmCP_HPD_UTCL1_ERROR_BASE_IDX', 'mmCP_HQD_ACTIVE', + 'mmCP_HQD_ACTIVE_BASE_IDX', 'mmCP_HQD_AQL_CONTROL', + 'mmCP_HQD_AQL_CONTROL_BASE_IDX', 'mmCP_HQD_ATOMIC0_PREOP_HI', + 'mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX', 'mmCP_HQD_ATOMIC0_PREOP_LO', + 'mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX', 'mmCP_HQD_ATOMIC1_PREOP_HI', + 'mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX', 'mmCP_HQD_ATOMIC1_PREOP_LO', + 'mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX', + 'mmCP_HQD_CNTL_STACK_OFFSET', + 'mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX', 'mmCP_HQD_CNTL_STACK_SIZE', + 'mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX', + 'mmCP_HQD_CTX_SAVE_BASE_ADDR_HI', + 'mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX', + 'mmCP_HQD_CTX_SAVE_BASE_ADDR_LO', + 'mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX', + 'mmCP_HQD_CTX_SAVE_CONTROL', 'mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX', + 'mmCP_HQD_CTX_SAVE_SIZE', 'mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX', + 'mmCP_HQD_DDID_DELTA_RPT_COUNT', + 'mmCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX', + 'mmCP_HQD_DDID_INFLIGHT_COUNT', + 'mmCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX', 'mmCP_HQD_DDID_RPTR', + 'mmCP_HQD_DDID_RPTR_BASE_IDX', 'mmCP_HQD_DDID_WPTR', + 'mmCP_HQD_DDID_WPTR_BASE_IDX', 'mmCP_HQD_DEQUEUE_REQUEST', + 'mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX', 'mmCP_HQD_DEQUEUE_STATUS', + 'mmCP_HQD_DEQUEUE_STATUS_BASE_IDX', 'mmCP_HQD_DMA_OFFLOAD', + 'mmCP_HQD_DMA_OFFLOAD_BASE_IDX', 'mmCP_HQD_EOP_BASE_ADDR', + 'mmCP_HQD_EOP_BASE_ADDR_BASE_IDX', 'mmCP_HQD_EOP_BASE_ADDR_HI', + 'mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX', 'mmCP_HQD_EOP_CONTROL', + 'mmCP_HQD_EOP_CONTROL_BASE_IDX', 'mmCP_HQD_EOP_EVENTS', + 'mmCP_HQD_EOP_EVENTS_BASE_IDX', 'mmCP_HQD_EOP_RPTR', + 'mmCP_HQD_EOP_RPTR_BASE_IDX', 'mmCP_HQD_EOP_WPTR', + 'mmCP_HQD_EOP_WPTR_BASE_IDX', 'mmCP_HQD_EOP_WPTR_MEM', + 'mmCP_HQD_EOP_WPTR_MEM_BASE_IDX', 'mmCP_HQD_ERROR', + 'mmCP_HQD_ERROR_BASE_IDX', 'mmCP_HQD_GDS_RESOURCE_STATE', + 'mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX', 'mmCP_HQD_GFX_CONTROL', + 'mmCP_HQD_GFX_CONTROL_BASE_IDX', 'mmCP_HQD_GFX_STATUS', + 'mmCP_HQD_GFX_STATUS_BASE_IDX', 'mmCP_HQD_HQ_CONTROL0', + 'mmCP_HQD_HQ_CONTROL0_BASE_IDX', 'mmCP_HQD_HQ_CONTROL1', + 'mmCP_HQD_HQ_CONTROL1_BASE_IDX', 'mmCP_HQD_HQ_SCHEDULER0', + 'mmCP_HQD_HQ_SCHEDULER0_BASE_IDX', 'mmCP_HQD_HQ_SCHEDULER1', + 'mmCP_HQD_HQ_SCHEDULER1_BASE_IDX', 'mmCP_HQD_HQ_STATUS0', + 'mmCP_HQD_HQ_STATUS0_BASE_IDX', 'mmCP_HQD_HQ_STATUS1', + 'mmCP_HQD_HQ_STATUS1_BASE_IDX', 'mmCP_HQD_IB_BASE_ADDR', + 'mmCP_HQD_IB_BASE_ADDR_BASE_IDX', 'mmCP_HQD_IB_BASE_ADDR_HI', + 'mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX', 'mmCP_HQD_IB_CONTROL', + 'mmCP_HQD_IB_CONTROL_BASE_IDX', 'mmCP_HQD_IB_RPTR', + 'mmCP_HQD_IB_RPTR_BASE_IDX', 'mmCP_HQD_IQ_RPTR', + 'mmCP_HQD_IQ_RPTR_BASE_IDX', 'mmCP_HQD_IQ_TIMER', + 'mmCP_HQD_IQ_TIMER_BASE_IDX', 'mmCP_HQD_MSG_TYPE', + 'mmCP_HQD_MSG_TYPE_BASE_IDX', 'mmCP_HQD_OFFLOAD', + 'mmCP_HQD_OFFLOAD_BASE_IDX', 'mmCP_HQD_PERSISTENT_STATE', + 'mmCP_HQD_PERSISTENT_STATE_BASE_IDX', 'mmCP_HQD_PIPE_PRIORITY', + 'mmCP_HQD_PIPE_PRIORITY_BASE_IDX', 'mmCP_HQD_PQ_BASE', + 'mmCP_HQD_PQ_BASE_BASE_IDX', 'mmCP_HQD_PQ_BASE_HI', + 'mmCP_HQD_PQ_BASE_HI_BASE_IDX', 'mmCP_HQD_PQ_CONTROL', + 'mmCP_HQD_PQ_CONTROL_BASE_IDX', 'mmCP_HQD_PQ_DOORBELL_CONTROL', + 'mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX', 'mmCP_HQD_PQ_RPTR', + 'mmCP_HQD_PQ_RPTR_BASE_IDX', 'mmCP_HQD_PQ_RPTR_REPORT_ADDR', + 'mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX', + 'mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI', + 'mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX', 'mmCP_HQD_PQ_WPTR_HI', + 'mmCP_HQD_PQ_WPTR_HI_BASE_IDX', 'mmCP_HQD_PQ_WPTR_LO', + 'mmCP_HQD_PQ_WPTR_LO_BASE_IDX', 'mmCP_HQD_PQ_WPTR_POLL_ADDR', + 'mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX', + 'mmCP_HQD_PQ_WPTR_POLL_ADDR_HI', + 'mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX', 'mmCP_HQD_QUANTUM', + 'mmCP_HQD_QUANTUM_BASE_IDX', 'mmCP_HQD_QUEUE_PRIORITY', + 'mmCP_HQD_QUEUE_PRIORITY_BASE_IDX', 'mmCP_HQD_SEMA_CMD', + 'mmCP_HQD_SEMA_CMD_BASE_IDX', + 'mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT', + 'mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX', + 'mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET', + 'mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX', + 'mmCP_HQD_SUSPEND_WG_STATE_OFFSET', + 'mmCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX', 'mmCP_HQD_VMID', + 'mmCP_HQD_VMID_BASE_IDX', 'mmCP_HQD_WG_STATE_OFFSET', + 'mmCP_HQD_WG_STATE_OFFSET_BASE_IDX', 'mmCP_HYP_CE_UCODE_ADDR', + 'mmCP_HYP_CE_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_CE_UCODE_DATA', + 'mmCP_HYP_CE_UCODE_DATA_BASE_IDX', 'mmCP_HYP_MEC1_UCODE_ADDR', + 'mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_MEC1_UCODE_DATA', + 'mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX', 'mmCP_HYP_MEC2_UCODE_ADDR', + 'mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_MEC2_UCODE_DATA', + 'mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX', 'mmCP_HYP_ME_UCODE_ADDR', + 'mmCP_HYP_ME_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_ME_UCODE_DATA', + 'mmCP_HYP_ME_UCODE_DATA_BASE_IDX', 'mmCP_HYP_PFP_UCODE_ADDR', + 'mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX', 'mmCP_HYP_PFP_UCODE_DATA', + 'mmCP_HYP_PFP_UCODE_DATA_BASE_IDX', 'mmCP_IB1_BASE_HI', + 'mmCP_IB1_BASE_HI_BASE_IDX', 'mmCP_IB1_BASE_LO', + 'mmCP_IB1_BASE_LO_BASE_IDX', 'mmCP_IB1_BUFSZ', + 'mmCP_IB1_BUFSZ_BASE_IDX', 'mmCP_IB2_BASE_HI', + 'mmCP_IB2_BASE_HI_BASE_IDX', 'mmCP_IB2_BASE_LO', + 'mmCP_IB2_BASE_LO_BASE_IDX', 'mmCP_IB2_BUFSZ', + 'mmCP_IB2_BUFSZ_BASE_IDX', 'mmCP_IB2_CMD_BUFSZ', + 'mmCP_IB2_CMD_BUFSZ_BASE_IDX', 'mmCP_IB2_OFFSET', + 'mmCP_IB2_OFFSET_BASE_IDX', 'mmCP_IB2_PREAMBLE_BEGIN', + 'mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX', 'mmCP_IB2_PREAMBLE_END', + 'mmCP_IB2_PREAMBLE_END_BASE_IDX', 'mmCP_INDEX_BASE_ADDR', + 'mmCP_INDEX_BASE_ADDR_BASE_IDX', 'mmCP_INDEX_BASE_ADDR_HI', + 'mmCP_INDEX_BASE_ADDR_HI_BASE_IDX', 'mmCP_INDEX_TYPE', + 'mmCP_INDEX_TYPE_BASE_IDX', 'mmCP_INT_CNTL', + 'mmCP_INT_CNTL_BASE_IDX', 'mmCP_INT_CNTL_RING0', + 'mmCP_INT_CNTL_RING0_BASE_IDX', 'mmCP_INT_CNTL_RING1', + 'mmCP_INT_CNTL_RING1_BASE_IDX', 'mmCP_INT_CNTL_RING2', + 'mmCP_INT_CNTL_RING2_BASE_IDX', 'mmCP_INT_STATUS', + 'mmCP_INT_STATUS_BASE_IDX', 'mmCP_INT_STATUS_RING0', + 'mmCP_INT_STATUS_RING0_BASE_IDX', 'mmCP_INT_STATUS_RING1', + 'mmCP_INT_STATUS_RING1_BASE_IDX', 'mmCP_INT_STATUS_RING2', + 'mmCP_INT_STATUS_RING2_BASE_IDX', 'mmCP_IQ_WAIT_TIME1', + 'mmCP_IQ_WAIT_TIME1_BASE_IDX', 'mmCP_IQ_WAIT_TIME2', + 'mmCP_IQ_WAIT_TIME2_BASE_IDX', 'mmCP_IQ_WAIT_TIME3', + 'mmCP_IQ_WAIT_TIME3_BASE_IDX', 'mmCP_MAX_CONTEXT', + 'mmCP_MAX_CONTEXT_BASE_IDX', 'mmCP_ME0_PIPE0_PRIORITY', + 'mmCP_ME0_PIPE0_PRIORITY_BASE_IDX', 'mmCP_ME0_PIPE0_VMID', + 'mmCP_ME0_PIPE0_VMID_BASE_IDX', 'mmCP_ME0_PIPE1_PRIORITY', + 'mmCP_ME0_PIPE1_PRIORITY_BASE_IDX', 'mmCP_ME0_PIPE1_VMID', + 'mmCP_ME0_PIPE1_VMID_BASE_IDX', 'mmCP_ME0_PIPE2_PRIORITY', + 'mmCP_ME0_PIPE2_PRIORITY_BASE_IDX', 'mmCP_ME0_PIPE_PRIORITY_CNTS', + 'mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX', 'mmCP_ME1_INT_STAT_DEBUG', + 'mmCP_ME1_INT_STAT_DEBUG_BASE_IDX', 'mmCP_ME1_PIPE0_INT_CNTL', + 'mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX', 'mmCP_ME1_PIPE0_INT_STATUS', + 'mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX', 'mmCP_ME1_PIPE0_PRIORITY', + 'mmCP_ME1_PIPE0_PRIORITY_BASE_IDX', 'mmCP_ME1_PIPE1_INT_CNTL', + 'mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX', 'mmCP_ME1_PIPE1_INT_STATUS', + 'mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX', 'mmCP_ME1_PIPE1_PRIORITY', + 'mmCP_ME1_PIPE1_PRIORITY_BASE_IDX', 'mmCP_ME1_PIPE2_INT_CNTL', + 'mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX', 'mmCP_ME1_PIPE2_INT_STATUS', + 'mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX', 'mmCP_ME1_PIPE2_PRIORITY', + 'mmCP_ME1_PIPE2_PRIORITY_BASE_IDX', 'mmCP_ME1_PIPE3_INT_CNTL', + 'mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX', 'mmCP_ME1_PIPE3_INT_STATUS', + 'mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX', 'mmCP_ME1_PIPE3_PRIORITY', + 'mmCP_ME1_PIPE3_PRIORITY_BASE_IDX', 'mmCP_ME1_PIPE_PRIORITY_CNTS', + 'mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX', 'mmCP_ME2_INT_STAT_DEBUG', + 'mmCP_ME2_INT_STAT_DEBUG_BASE_IDX', 'mmCP_ME2_PIPE0_INT_CNTL', + 'mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX', 'mmCP_ME2_PIPE0_INT_STATUS', + 'mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX', 'mmCP_ME2_PIPE0_PRIORITY', + 'mmCP_ME2_PIPE0_PRIORITY_BASE_IDX', 'mmCP_ME2_PIPE1_INT_CNTL', + 'mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX', 'mmCP_ME2_PIPE1_INT_STATUS', + 'mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX', 'mmCP_ME2_PIPE1_PRIORITY', + 'mmCP_ME2_PIPE1_PRIORITY_BASE_IDX', 'mmCP_ME2_PIPE2_INT_CNTL', + 'mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX', 'mmCP_ME2_PIPE2_INT_STATUS', + 'mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX', 'mmCP_ME2_PIPE2_PRIORITY', + 'mmCP_ME2_PIPE2_PRIORITY_BASE_IDX', 'mmCP_ME2_PIPE3_INT_CNTL', + 'mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX', 'mmCP_ME2_PIPE3_INT_STATUS', + 'mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX', 'mmCP_ME2_PIPE3_PRIORITY', + 'mmCP_ME2_PIPE3_PRIORITY_BASE_IDX', 'mmCP_ME2_PIPE_PRIORITY_CNTS', + 'mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX', 'mmCP_MEC1_F32_INTERRUPT', + 'mmCP_MEC1_F32_INTERRUPT_BASE_IDX', 'mmCP_MEC1_F32_INT_DIS', + 'mmCP_MEC1_F32_INT_DIS_BASE_IDX', 'mmCP_MEC1_INSTR_PNTR', + 'mmCP_MEC1_INSTR_PNTR_BASE_IDX', 'mmCP_MEC1_INTR_ROUTINE_START', + 'mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX', + 'mmCP_MEC1_PRGRM_CNTR_START', + 'mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX', 'mmCP_MEC2_F32_INTERRUPT', + 'mmCP_MEC2_F32_INTERRUPT_BASE_IDX', 'mmCP_MEC2_F32_INT_DIS', + 'mmCP_MEC2_F32_INT_DIS_BASE_IDX', 'mmCP_MEC2_INSTR_PNTR', + 'mmCP_MEC2_INSTR_PNTR_BASE_IDX', 'mmCP_MEC2_INTR_ROUTINE_START', + 'mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX', + 'mmCP_MEC2_PRGRM_CNTR_START', + 'mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX', 'mmCP_MEC_CNTL', + 'mmCP_MEC_CNTL_BASE_IDX', 'mmCP_MEC_DOORBELL_RANGE_LOWER', + 'mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX', + 'mmCP_MEC_DOORBELL_RANGE_UPPER', + 'mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX', 'mmCP_MEC_JT_STAT', + 'mmCP_MEC_JT_STAT_BASE_IDX', 'mmCP_MEC_ME1_HEADER_DUMP', + 'mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX', 'mmCP_MEC_ME1_UCODE_ADDR', + 'mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX', 'mmCP_MEC_ME1_UCODE_DATA', + 'mmCP_MEC_ME1_UCODE_DATA_BASE_IDX', 'mmCP_MEC_ME2_HEADER_DUMP', + 'mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX', 'mmCP_MEC_ME2_UCODE_ADDR', + 'mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX', 'mmCP_MEC_ME2_UCODE_DATA', + 'mmCP_MEC_ME2_UCODE_DATA_BASE_IDX', 'mmCP_MEM_SLP_CNTL', + 'mmCP_MEM_SLP_CNTL_BASE_IDX', 'mmCP_MEQ_AVAIL', + 'mmCP_MEQ_AVAIL_BASE_IDX', 'mmCP_MEQ_STAT', + 'mmCP_MEQ_STAT_BASE_IDX', 'mmCP_MEQ_STQ_THRESHOLD', + 'mmCP_MEQ_STQ_THRESHOLD_BASE_IDX', 'mmCP_MEQ_THRESHOLDS', + 'mmCP_MEQ_THRESHOLDS_BASE_IDX', 'mmCP_MES_CNTL', + 'mmCP_MES_CNTL_BASE_IDX', 'mmCP_MES_DC_BASE_CNTL', + 'mmCP_MES_DC_BASE_CNTL_BASE_IDX', 'mmCP_MES_DC_BASE_HI', + 'mmCP_MES_DC_BASE_HI_BASE_IDX', 'mmCP_MES_DC_BASE_LO', + 'mmCP_MES_DC_BASE_LO_BASE_IDX', 'mmCP_MES_DC_OP_CNTL', + 'mmCP_MES_DC_OP_CNTL_BASE_IDX', 'mmCP_MES_DM_INDEX_ADDR', + 'mmCP_MES_DM_INDEX_ADDR_BASE_IDX', 'mmCP_MES_DM_INDEX_DATA', + 'mmCP_MES_DM_INDEX_DATA_BASE_IDX', 'mmCP_MES_DOORBELL_CONTROL1', + 'mmCP_MES_DOORBELL_CONTROL1_BASE_IDX', + 'mmCP_MES_DOORBELL_CONTROL2', + 'mmCP_MES_DOORBELL_CONTROL2_BASE_IDX', + 'mmCP_MES_DOORBELL_CONTROL3', + 'mmCP_MES_DOORBELL_CONTROL3_BASE_IDX', + 'mmCP_MES_DOORBELL_CONTROL4', + 'mmCP_MES_DOORBELL_CONTROL4_BASE_IDX', + 'mmCP_MES_DOORBELL_CONTROL5', + 'mmCP_MES_DOORBELL_CONTROL5_BASE_IDX', + 'mmCP_MES_DOORBELL_CONTROL6', + 'mmCP_MES_DOORBELL_CONTROL6_BASE_IDX', 'mmCP_MES_GP0_HI', + 'mmCP_MES_GP0_HI_BASE_IDX', 'mmCP_MES_GP0_LO', + 'mmCP_MES_GP0_LO_BASE_IDX', 'mmCP_MES_GP1_HI', + 'mmCP_MES_GP1_HI_BASE_IDX', 'mmCP_MES_GP1_LO', + 'mmCP_MES_GP1_LO_BASE_IDX', 'mmCP_MES_GP2_HI', + 'mmCP_MES_GP2_HI_BASE_IDX', 'mmCP_MES_GP2_LO', + 'mmCP_MES_GP2_LO_BASE_IDX', 'mmCP_MES_GP3_HI', + 'mmCP_MES_GP3_HI_BASE_IDX', 'mmCP_MES_GP3_LO', + 'mmCP_MES_GP3_LO_BASE_IDX', 'mmCP_MES_GP4_HI', + 'mmCP_MES_GP4_HI_BASE_IDX', 'mmCP_MES_GP4_LO', + 'mmCP_MES_GP4_LO_BASE_IDX', 'mmCP_MES_GP5_HI', + 'mmCP_MES_GP5_HI_BASE_IDX', 'mmCP_MES_GP5_LO', + 'mmCP_MES_GP5_LO_BASE_IDX', 'mmCP_MES_GP6_HI', + 'mmCP_MES_GP6_HI_BASE_IDX', 'mmCP_MES_GP6_LO', + 'mmCP_MES_GP6_LO_BASE_IDX', 'mmCP_MES_GP7_HI', + 'mmCP_MES_GP7_HI_BASE_IDX', 'mmCP_MES_GP7_LO', + 'mmCP_MES_GP7_LO_BASE_IDX', 'mmCP_MES_GP8_HI', + 'mmCP_MES_GP8_HI_BASE_IDX', 'mmCP_MES_GP8_LO', + 'mmCP_MES_GP8_LO_BASE_IDX', 'mmCP_MES_GP9_HI', + 'mmCP_MES_GP9_HI_BASE_IDX', 'mmCP_MES_GP9_LO', + 'mmCP_MES_GP9_LO_BASE_IDX', 'mmCP_MES_HEADER_DUMP', + 'mmCP_MES_HEADER_DUMP_BASE_IDX', 'mmCP_MES_IC_BASE_CNTL', + 'mmCP_MES_IC_BASE_CNTL_BASE_IDX', 'mmCP_MES_IC_BASE_HI', + 'mmCP_MES_IC_BASE_HI_BASE_IDX', 'mmCP_MES_IC_BASE_LO', + 'mmCP_MES_IC_BASE_LO_BASE_IDX', 'mmCP_MES_IC_OP_CNTL', + 'mmCP_MES_IC_OP_CNTL_BASE_IDX', 'mmCP_MES_INSTR_PNTR', + 'mmCP_MES_INSTR_PNTR_BASE_IDX', 'mmCP_MES_INTERRUPT', + 'mmCP_MES_INTERRUPT_BASE_IDX', 'mmCP_MES_INTR_ROUTINE_START', + 'mmCP_MES_INTR_ROUTINE_START_BASE_IDX', 'mmCP_MES_LOCAL_APERTURE', + 'mmCP_MES_LOCAL_APERTURE_BASE_IDX', 'mmCP_MES_LOCAL_BASE0_HI', + 'mmCP_MES_LOCAL_BASE0_HI_BASE_IDX', 'mmCP_MES_LOCAL_BASE0_LO', + 'mmCP_MES_LOCAL_BASE0_LO_BASE_IDX', 'mmCP_MES_LOCAL_MASK0_HI', + 'mmCP_MES_LOCAL_MASK0_HI_BASE_IDX', 'mmCP_MES_LOCAL_MASK0_LO', + 'mmCP_MES_LOCAL_MASK0_LO_BASE_IDX', 'mmCP_MES_MARCHID_HI', + 'mmCP_MES_MARCHID_HI_BASE_IDX', 'mmCP_MES_MARCHID_LO', + 'mmCP_MES_MARCHID_LO_BASE_IDX', 'mmCP_MES_MBADADDR_HI', + 'mmCP_MES_MBADADDR_HI_BASE_IDX', 'mmCP_MES_MBADADDR_LO', + 'mmCP_MES_MBADADDR_LO_BASE_IDX', 'mmCP_MES_MCAUSE_HI', + 'mmCP_MES_MCAUSE_HI_BASE_IDX', 'mmCP_MES_MCAUSE_LO', + 'mmCP_MES_MCAUSE_LO_BASE_IDX', 'mmCP_MES_MCYCLE_HI', + 'mmCP_MES_MCYCLE_HI_BASE_IDX', 'mmCP_MES_MCYCLE_LO', + 'mmCP_MES_MCYCLE_LO_BASE_IDX', 'mmCP_MES_MDBASE_HI', + 'mmCP_MES_MDBASE_HI_BASE_IDX', 'mmCP_MES_MDBASE_LO', + 'mmCP_MES_MDBASE_LO_BASE_IDX', 'mmCP_MES_MDBOUND_HI', + 'mmCP_MES_MDBOUND_HI_BASE_IDX', 'mmCP_MES_MDBOUND_LO', + 'mmCP_MES_MDBOUND_LO_BASE_IDX', 'mmCP_MES_MEPC_HI', + 'mmCP_MES_MEPC_HI_BASE_IDX', 'mmCP_MES_MEPC_LO', + 'mmCP_MES_MEPC_LO_BASE_IDX', 'mmCP_MES_MHARTID_HI', + 'mmCP_MES_MHARTID_HI_BASE_IDX', 'mmCP_MES_MHARTID_LO', + 'mmCP_MES_MHARTID_LO_BASE_IDX', 'mmCP_MES_MIBASE_HI', + 'mmCP_MES_MIBASE_HI_BASE_IDX', 'mmCP_MES_MIBASE_LO', + 'mmCP_MES_MIBASE_LO_BASE_IDX', 'mmCP_MES_MIBOUND_HI', + 'mmCP_MES_MIBOUND_HI_BASE_IDX', 'mmCP_MES_MIBOUND_LO', + 'mmCP_MES_MIBOUND_LO_BASE_IDX', 'mmCP_MES_MIE_HI', + 'mmCP_MES_MIE_HI_BASE_IDX', 'mmCP_MES_MIE_LO', + 'mmCP_MES_MIE_LO_BASE_IDX', 'mmCP_MES_MIMPID_HI', + 'mmCP_MES_MIMPID_HI_BASE_IDX', 'mmCP_MES_MIMPID_LO', + 'mmCP_MES_MIMPID_LO_BASE_IDX', 'mmCP_MES_MINSTRET_HI', + 'mmCP_MES_MINSTRET_HI_BASE_IDX', 'mmCP_MES_MINSTRET_LO', + 'mmCP_MES_MINSTRET_LO_BASE_IDX', 'mmCP_MES_MIP_HI', + 'mmCP_MES_MIP_HI_BASE_IDX', 'mmCP_MES_MIP_LO', + 'mmCP_MES_MIP_LO_BASE_IDX', 'mmCP_MES_MISA_HI', + 'mmCP_MES_MISA_HI_BASE_IDX', 'mmCP_MES_MISA_LO', + 'mmCP_MES_MISA_LO_BASE_IDX', 'mmCP_MES_MSCRATCH_HI', + 'mmCP_MES_MSCRATCH_HI_BASE_IDX', 'mmCP_MES_MSCRATCH_LO', + 'mmCP_MES_MSCRATCH_LO_BASE_IDX', 'mmCP_MES_MSTATUS_HI', + 'mmCP_MES_MSTATUS_HI_BASE_IDX', 'mmCP_MES_MSTATUS_LO', + 'mmCP_MES_MSTATUS_LO_BASE_IDX', 'mmCP_MES_MTIMECMP_HI', + 'mmCP_MES_MTIMECMP_HI_BASE_IDX', 'mmCP_MES_MTIMECMP_LO', + 'mmCP_MES_MTIMECMP_LO_BASE_IDX', 'mmCP_MES_MTIME_HI', + 'mmCP_MES_MTIME_HI_BASE_IDX', 'mmCP_MES_MTIME_LO', + 'mmCP_MES_MTIME_LO_BASE_IDX', 'mmCP_MES_MTVEC_HI', + 'mmCP_MES_MTVEC_HI_BASE_IDX', 'mmCP_MES_MTVEC_LO', + 'mmCP_MES_MTVEC_LO_BASE_IDX', 'mmCP_MES_MVENDORID_HI', + 'mmCP_MES_MVENDORID_HI_BASE_IDX', 'mmCP_MES_MVENDORID_LO', + 'mmCP_MES_MVENDORID_LO_BASE_IDX', 'mmCP_MES_PENDING_INTERRUPT', + 'mmCP_MES_PENDING_INTERRUPT_BASE_IDX', 'mmCP_MES_PERFCOUNT_CNTL', + 'mmCP_MES_PERFCOUNT_CNTL_BASE_IDX', 'mmCP_MES_PIPE0_PRIORITY', + 'mmCP_MES_PIPE0_PRIORITY_BASE_IDX', 'mmCP_MES_PIPE1_PRIORITY', + 'mmCP_MES_PIPE1_PRIORITY_BASE_IDX', 'mmCP_MES_PIPE2_PRIORITY', + 'mmCP_MES_PIPE2_PRIORITY_BASE_IDX', 'mmCP_MES_PIPE3_PRIORITY', + 'mmCP_MES_PIPE3_PRIORITY_BASE_IDX', 'mmCP_MES_PIPE_PRIORITY_CNTS', + 'mmCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX', + 'mmCP_MES_PRGRM_CNTR_START', 'mmCP_MES_PRGRM_CNTR_START_BASE_IDX', + 'mmCP_MES_PROCESS_QUANTUM_PIPE0', + 'mmCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX', + 'mmCP_MES_PROCESS_QUANTUM_PIPE1', + 'mmCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX', + 'mmCP_MES_SCRATCH_DATA', 'mmCP_MES_SCRATCH_DATA_BASE_IDX', + 'mmCP_MES_SCRATCH_INDEX', 'mmCP_MES_SCRATCH_INDEX_BASE_IDX', + 'mmCP_ME_ATOMIC_PREOP_HI', 'mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX', + 'mmCP_ME_ATOMIC_PREOP_LO', 'mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX', + 'mmCP_ME_CNTL', 'mmCP_ME_CNTL_BASE_IDX', 'mmCP_ME_COHER_BASE', + 'mmCP_ME_COHER_BASE_BASE_IDX', 'mmCP_ME_COHER_BASE_HI', + 'mmCP_ME_COHER_BASE_HI_BASE_IDX', 'mmCP_ME_COHER_CNTL', + 'mmCP_ME_COHER_CNTL_BASE_IDX', 'mmCP_ME_COHER_SIZE', + 'mmCP_ME_COHER_SIZE_BASE_IDX', 'mmCP_ME_COHER_SIZE_HI', + 'mmCP_ME_COHER_SIZE_HI_BASE_IDX', 'mmCP_ME_COHER_STATUS', + 'mmCP_ME_COHER_STATUS_BASE_IDX', 'mmCP_ME_F32_INTERRUPT', + 'mmCP_ME_F32_INTERRUPT_BASE_IDX', 'mmCP_ME_GDS_ATOMIC0_PREOP_HI', + 'mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX', + 'mmCP_ME_GDS_ATOMIC0_PREOP_LO', + 'mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX', + 'mmCP_ME_GDS_ATOMIC1_PREOP_HI', + 'mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX', + 'mmCP_ME_GDS_ATOMIC1_PREOP_LO', + 'mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'mmCP_ME_HEADER_DUMP', + 'mmCP_ME_HEADER_DUMP_BASE_IDX', 'mmCP_ME_IC_BASE_CNTL', + 'mmCP_ME_IC_BASE_CNTL_BASE_IDX', 'mmCP_ME_IC_BASE_HI', + 'mmCP_ME_IC_BASE_HI_BASE_IDX', 'mmCP_ME_IC_BASE_LO', + 'mmCP_ME_IC_BASE_LO_BASE_IDX', 'mmCP_ME_IC_OP_CNTL', + 'mmCP_ME_IC_OP_CNTL_BASE_IDX', 'mmCP_ME_INSTR_PNTR', + 'mmCP_ME_INSTR_PNTR_BASE_IDX', 'mmCP_ME_INTR_ROUTINE_START', + 'mmCP_ME_INTR_ROUTINE_START_BASE_IDX', 'mmCP_ME_MC_RADDR_HI', + 'mmCP_ME_MC_RADDR_HI_BASE_IDX', 'mmCP_ME_MC_RADDR_LO', + 'mmCP_ME_MC_RADDR_LO_BASE_IDX', 'mmCP_ME_MC_WADDR_HI', + 'mmCP_ME_MC_WADDR_HI_BASE_IDX', 'mmCP_ME_MC_WADDR_LO', + 'mmCP_ME_MC_WADDR_LO_BASE_IDX', 'mmCP_ME_MC_WDATA_HI', + 'mmCP_ME_MC_WDATA_HI_BASE_IDX', 'mmCP_ME_MC_WDATA_LO', + 'mmCP_ME_MC_WDATA_LO_BASE_IDX', 'mmCP_ME_PREEMPTION', + 'mmCP_ME_PREEMPTION_BASE_IDX', 'mmCP_ME_PRGRM_CNTR_START', + 'mmCP_ME_PRGRM_CNTR_START_BASE_IDX', 'mmCP_ME_RAM_DATA', + 'mmCP_ME_RAM_DATA_BASE_IDX', 'mmCP_ME_RAM_RADDR', + 'mmCP_ME_RAM_RADDR_BASE_IDX', 'mmCP_ME_RAM_WADDR', + 'mmCP_ME_RAM_WADDR_BASE_IDX', 'mmCP_MQD_BASE_ADDR', + 'mmCP_MQD_BASE_ADDR_BASE_IDX', 'mmCP_MQD_BASE_ADDR_HI', + 'mmCP_MQD_BASE_ADDR_HI_BASE_IDX', 'mmCP_MQD_CONTROL', + 'mmCP_MQD_CONTROL_BASE_IDX', 'mmCP_NUM_PRIM_NEEDED_COUNT0_HI', + 'mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX', + 'mmCP_NUM_PRIM_NEEDED_COUNT0_LO', + 'mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX', + 'mmCP_NUM_PRIM_NEEDED_COUNT1_HI', + 'mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX', + 'mmCP_NUM_PRIM_NEEDED_COUNT1_LO', + 'mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX', + 'mmCP_NUM_PRIM_NEEDED_COUNT2_HI', + 'mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX', + 'mmCP_NUM_PRIM_NEEDED_COUNT2_LO', + 'mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX', + 'mmCP_NUM_PRIM_NEEDED_COUNT3_HI', + 'mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX', + 'mmCP_NUM_PRIM_NEEDED_COUNT3_LO', + 'mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX', + 'mmCP_NUM_PRIM_WRITTEN_COUNT0_HI', + 'mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX', + 'mmCP_NUM_PRIM_WRITTEN_COUNT0_LO', + 'mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX', + 'mmCP_NUM_PRIM_WRITTEN_COUNT1_HI', + 'mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX', + 'mmCP_NUM_PRIM_WRITTEN_COUNT1_LO', + 'mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX', + 'mmCP_NUM_PRIM_WRITTEN_COUNT2_HI', + 'mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX', + 'mmCP_NUM_PRIM_WRITTEN_COUNT2_LO', + 'mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX', + 'mmCP_NUM_PRIM_WRITTEN_COUNT3_HI', + 'mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX', + 'mmCP_NUM_PRIM_WRITTEN_COUNT3_LO', + 'mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX', + 'mmCP_PA_CINVOC_COUNT_HI', 'mmCP_PA_CINVOC_COUNT_HI_BASE_IDX', + 'mmCP_PA_CINVOC_COUNT_LO', 'mmCP_PA_CINVOC_COUNT_LO_BASE_IDX', + 'mmCP_PA_CPRIM_COUNT_HI', 'mmCP_PA_CPRIM_COUNT_HI_BASE_IDX', + 'mmCP_PA_CPRIM_COUNT_LO', 'mmCP_PA_CPRIM_COUNT_LO_BASE_IDX', + 'mmCP_PERFMON_CNTL', 'mmCP_PERFMON_CNTL_BASE_IDX', + 'mmCP_PERFMON_CNTX_CNTL', 'mmCP_PERFMON_CNTX_CNTL_BASE_IDX', + 'mmCP_PFP_ATOMIC_PREOP_HI', 'mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX', + 'mmCP_PFP_ATOMIC_PREOP_LO', 'mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX', + 'mmCP_PFP_COMPLETION_STATUS', + 'mmCP_PFP_COMPLETION_STATUS_BASE_IDX', 'mmCP_PFP_F32_INTERRUPT', + 'mmCP_PFP_F32_INTERRUPT_BASE_IDX', + 'mmCP_PFP_GDS_ATOMIC0_PREOP_HI', + 'mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX', + 'mmCP_PFP_GDS_ATOMIC0_PREOP_LO', + 'mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX', + 'mmCP_PFP_GDS_ATOMIC1_PREOP_HI', + 'mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX', + 'mmCP_PFP_GDS_ATOMIC1_PREOP_LO', + 'mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX', 'mmCP_PFP_HEADER_DUMP', + 'mmCP_PFP_HEADER_DUMP_BASE_IDX', 'mmCP_PFP_IB_CONTROL', + 'mmCP_PFP_IB_CONTROL_BASE_IDX', 'mmCP_PFP_IC_BASE_CNTL', + 'mmCP_PFP_IC_BASE_CNTL_BASE_IDX', 'mmCP_PFP_IC_BASE_HI', + 'mmCP_PFP_IC_BASE_HI_BASE_IDX', 'mmCP_PFP_IC_BASE_LO', + 'mmCP_PFP_IC_BASE_LO_BASE_IDX', 'mmCP_PFP_IC_OP_CNTL', + 'mmCP_PFP_IC_OP_CNTL_BASE_IDX', 'mmCP_PFP_INSTR_PNTR', + 'mmCP_PFP_INSTR_PNTR_BASE_IDX', 'mmCP_PFP_INTR_ROUTINE_START', + 'mmCP_PFP_INTR_ROUTINE_START_BASE_IDX', 'mmCP_PFP_JT_STAT', + 'mmCP_PFP_JT_STAT_BASE_IDX', 'mmCP_PFP_LOAD_CONTROL', + 'mmCP_PFP_LOAD_CONTROL_BASE_IDX', 'mmCP_PFP_METADATA_BASE_ADDR', + 'mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX', + 'mmCP_PFP_METADATA_BASE_ADDR_HI', + 'mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX', + 'mmCP_PFP_PRGRM_CNTR_START', 'mmCP_PFP_PRGRM_CNTR_START_BASE_IDX', + 'mmCP_PFP_UCODE_ADDR', 'mmCP_PFP_UCODE_ADDR_BASE_IDX', + 'mmCP_PFP_UCODE_DATA', 'mmCP_PFP_UCODE_DATA_BASE_IDX', + 'mmCP_PIPEID', 'mmCP_PIPEID_BASE_IDX', 'mmCP_PIPE_STATS_ADDR_HI', + 'mmCP_PIPE_STATS_ADDR_HI_BASE_IDX', 'mmCP_PIPE_STATS_ADDR_LO', + 'mmCP_PIPE_STATS_ADDR_LO_BASE_IDX', 'mmCP_PIPE_STATS_CONTROL', + 'mmCP_PIPE_STATS_CONTROL_BASE_IDX', 'mmCP_PQ_STATUS', + 'mmCP_PQ_STATUS_BASE_IDX', 'mmCP_PQ_WPTR_POLL_CNTL', + 'mmCP_PQ_WPTR_POLL_CNTL1', 'mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX', + 'mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX', 'mmCP_PRED_NOT_VISIBLE', + 'mmCP_PRED_NOT_VISIBLE_BASE_IDX', 'mmCP_PRIV_VIOLATION_ADDR', + 'mmCP_PRIV_VIOLATION_ADDR_BASE_IDX', 'mmCP_PROCESS_QUANTUM', + 'mmCP_PROCESS_QUANTUM_BASE_IDX', 'mmCP_PWR_CNTL', + 'mmCP_PWR_CNTL_BASE_IDX', 'mmCP_QUEUE_THRESHOLDS', + 'mmCP_QUEUE_THRESHOLDS_BASE_IDX', 'mmCP_RB0_ACTIVE', + 'mmCP_RB0_ACTIVE_BASE_IDX', 'mmCP_RB0_BASE', + 'mmCP_RB0_BASE_BASE_IDX', 'mmCP_RB0_BASE_HI', + 'mmCP_RB0_BASE_HI_BASE_IDX', 'mmCP_RB0_BUFSZ_MASK', + 'mmCP_RB0_BUFSZ_MASK_BASE_IDX', 'mmCP_RB0_CNTL', + 'mmCP_RB0_CNTL_BASE_IDX', 'mmCP_RB0_RPTR', 'mmCP_RB0_RPTR_ADDR', + 'mmCP_RB0_RPTR_ADDR_BASE_IDX', 'mmCP_RB0_RPTR_ADDR_HI', + 'mmCP_RB0_RPTR_ADDR_HI_BASE_IDX', 'mmCP_RB0_RPTR_BASE_IDX', + 'mmCP_RB0_WPTR', 'mmCP_RB0_WPTR_BASE_IDX', 'mmCP_RB0_WPTR_HI', + 'mmCP_RB0_WPTR_HI_BASE_IDX', 'mmCP_RB1_ACTIVE', + 'mmCP_RB1_ACTIVE_BASE_IDX', 'mmCP_RB1_BASE', + 'mmCP_RB1_BASE_BASE_IDX', 'mmCP_RB1_BASE_HI', + 'mmCP_RB1_BASE_HI_BASE_IDX', 'mmCP_RB1_BUFSZ_MASK', + 'mmCP_RB1_BUFSZ_MASK_BASE_IDX', 'mmCP_RB1_CNTL', + 'mmCP_RB1_CNTL_BASE_IDX', 'mmCP_RB1_RPTR', 'mmCP_RB1_RPTR_ADDR', + 'mmCP_RB1_RPTR_ADDR_BASE_IDX', 'mmCP_RB1_RPTR_ADDR_HI', + 'mmCP_RB1_RPTR_ADDR_HI_BASE_IDX', 'mmCP_RB1_RPTR_BASE_IDX', + 'mmCP_RB1_WPTR', 'mmCP_RB1_WPTR_BASE_IDX', 'mmCP_RB1_WPTR_HI', + 'mmCP_RB1_WPTR_HI_BASE_IDX', 'mmCP_RB2_BASE', + 'mmCP_RB2_BASE_BASE_IDX', 'mmCP_RB2_CNTL', + 'mmCP_RB2_CNTL_BASE_IDX', 'mmCP_RB2_RPTR', 'mmCP_RB2_RPTR_ADDR', + 'mmCP_RB2_RPTR_ADDR_BASE_IDX', 'mmCP_RB2_RPTR_ADDR_HI', + 'mmCP_RB2_RPTR_ADDR_HI_BASE_IDX', 'mmCP_RB2_RPTR_BASE_IDX', + 'mmCP_RB2_WPTR', 'mmCP_RB2_WPTR_BASE_IDX', 'mmCP_RB_ACTIVE', + 'mmCP_RB_ACTIVE_BASE_IDX', 'mmCP_RB_BASE', + 'mmCP_RB_BASE_BASE_IDX', 'mmCP_RB_BUFSZ_MASK', + 'mmCP_RB_BUFSZ_MASK_BASE_IDX', 'mmCP_RB_CNTL', + 'mmCP_RB_CNTL_BASE_IDX', 'mmCP_RB_DOORBELL_CLEAR', + 'mmCP_RB_DOORBELL_CLEAR_BASE_IDX', 'mmCP_RB_DOORBELL_CONTROL', + 'mmCP_RB_DOORBELL_CONTROL_BASE_IDX', + 'mmCP_RB_DOORBELL_RANGE_LOWER', + 'mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX', + 'mmCP_RB_DOORBELL_RANGE_UPPER', + 'mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX', 'mmCP_RB_OFFSET', + 'mmCP_RB_OFFSET_BASE_IDX', 'mmCP_RB_RPTR', 'mmCP_RB_RPTR_ADDR', + 'mmCP_RB_RPTR_ADDR_BASE_IDX', 'mmCP_RB_RPTR_ADDR_HI', + 'mmCP_RB_RPTR_ADDR_HI_BASE_IDX', 'mmCP_RB_RPTR_BASE_IDX', + 'mmCP_RB_RPTR_WR', 'mmCP_RB_RPTR_WR_BASE_IDX', 'mmCP_RB_STATUS', + 'mmCP_RB_STATUS_BASE_IDX', 'mmCP_RB_VMID', + 'mmCP_RB_VMID_BASE_IDX', 'mmCP_RB_WPTR', 'mmCP_RB_WPTR_BASE_IDX', + 'mmCP_RB_WPTR_DELAY', 'mmCP_RB_WPTR_DELAY_BASE_IDX', + 'mmCP_RB_WPTR_HI', 'mmCP_RB_WPTR_HI_BASE_IDX', + 'mmCP_RB_WPTR_POLL_ADDR_HI', 'mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmCP_RB_WPTR_POLL_ADDR_LO', 'mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmCP_RB_WPTR_POLL_CNTL', 'mmCP_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmCP_RING0_PRIORITY', 'mmCP_RING0_PRIORITY_BASE_IDX', + 'mmCP_RING1_PRIORITY', 'mmCP_RING1_PRIORITY_BASE_IDX', + 'mmCP_RING2_PRIORITY', 'mmCP_RING2_PRIORITY_BASE_IDX', + 'mmCP_RINGID', 'mmCP_RINGID_BASE_IDX', 'mmCP_RING_PRIORITY_CNTS', + 'mmCP_RING_PRIORITY_CNTS_BASE_IDX', 'mmCP_ROQ1_THRESHOLDS', + 'mmCP_ROQ1_THRESHOLDS_BASE_IDX', 'mmCP_ROQ2_AVAIL', + 'mmCP_ROQ2_AVAIL_BASE_IDX', 'mmCP_ROQ2_THRESHOLDS', + 'mmCP_ROQ2_THRESHOLDS_BASE_IDX', 'mmCP_ROQ3_THRESHOLDS', + 'mmCP_ROQ3_THRESHOLDS_BASE_IDX', 'mmCP_ROQ_AVAIL', + 'mmCP_ROQ_AVAIL_BASE_IDX', 'mmCP_ROQ_DB_STAT', + 'mmCP_ROQ_DB_STAT_BASE_IDX', 'mmCP_ROQ_IB1_STAT', + 'mmCP_ROQ_IB1_STAT_BASE_IDX', 'mmCP_ROQ_IB2_STAT', + 'mmCP_ROQ_IB2_STAT_BASE_IDX', 'mmCP_ROQ_RB_STAT', + 'mmCP_ROQ_RB_STAT_BASE_IDX', 'mmCP_ROQ_THRESHOLDS', + 'mmCP_ROQ_THRESHOLDS_BASE_IDX', 'mmCP_SAMPLE_STATUS', + 'mmCP_SAMPLE_STATUS_BASE_IDX', 'mmCP_SCRATCH_DATA', + 'mmCP_SCRATCH_DATA_BASE_IDX', 'mmCP_SCRATCH_INDEX', + 'mmCP_SCRATCH_INDEX_BASE_IDX', 'mmCP_SC_PSINVOC_COUNT0_HI', + 'mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX', 'mmCP_SC_PSINVOC_COUNT0_LO', + 'mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX', 'mmCP_SC_PSINVOC_COUNT1_HI', + 'mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX', 'mmCP_SC_PSINVOC_COUNT1_LO', + 'mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX', 'mmCP_SD_CNTL', + 'mmCP_SD_CNTL_BASE_IDX', 'mmCP_SEM_WAIT_TIMER', + 'mmCP_SEM_WAIT_TIMER_BASE_IDX', 'mmCP_SIG_SEM_ADDR_HI', + 'mmCP_SIG_SEM_ADDR_HI_BASE_IDX', 'mmCP_SIG_SEM_ADDR_LO', + 'mmCP_SIG_SEM_ADDR_LO_BASE_IDX', 'mmCP_SOFT_RESET_CNTL', + 'mmCP_SOFT_RESET_CNTL_BASE_IDX', 'mmCP_STALLED_STAT1', + 'mmCP_STALLED_STAT1_BASE_IDX', 'mmCP_STALLED_STAT2', + 'mmCP_STALLED_STAT2_BASE_IDX', 'mmCP_STALLED_STAT3', + 'mmCP_STALLED_STAT3_BASE_IDX', 'mmCP_STAT', 'mmCP_STAT_BASE_IDX', + 'mmCP_STQ_AVAIL', 'mmCP_STQ_AVAIL_BASE_IDX', 'mmCP_STQ_STAT', + 'mmCP_STQ_STAT_BASE_IDX', 'mmCP_STQ_THRESHOLDS', + 'mmCP_STQ_THRESHOLDS_BASE_IDX', 'mmCP_STQ_WR_STAT', + 'mmCP_STQ_WR_STAT_BASE_IDX', 'mmCP_STREAM_OUT_ADDR_HI', + 'mmCP_STREAM_OUT_ADDR_HI_BASE_IDX', 'mmCP_STREAM_OUT_ADDR_LO', + 'mmCP_STREAM_OUT_ADDR_LO_BASE_IDX', 'mmCP_STREAM_OUT_CONTROL', + 'mmCP_STREAM_OUT_CONTROL_BASE_IDX', 'mmCP_STRMOUT_CNTL', + 'mmCP_STRMOUT_CNTL_BASE_IDX', 'mmCP_ST_BASE_HI', + 'mmCP_ST_BASE_HI_BASE_IDX', 'mmCP_ST_BASE_LO', + 'mmCP_ST_BASE_LO_BASE_IDX', 'mmCP_ST_BUFSZ', + 'mmCP_ST_BUFSZ_BASE_IDX', 'mmCP_ST_CMD_BUFSZ', + 'mmCP_ST_CMD_BUFSZ_BASE_IDX', 'mmCP_SUSPEND_CNTL', + 'mmCP_SUSPEND_CNTL_BASE_IDX', 'mmCP_SUSPEND_RESUME_REQ', + 'mmCP_SUSPEND_RESUME_REQ_BASE_IDX', 'mmCP_VGT_CSINVOC_COUNT_HI', + 'mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_CSINVOC_COUNT_LO', + 'mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VGT_DSINVOC_COUNT_HI', + 'mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_DSINVOC_COUNT_LO', + 'mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VGT_GSINVOC_COUNT_HI', + 'mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_GSINVOC_COUNT_LO', + 'mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VGT_GSPRIM_COUNT_HI', + 'mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX', 'mmCP_VGT_GSPRIM_COUNT_LO', + 'mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX', 'mmCP_VGT_HSINVOC_COUNT_HI', + 'mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_HSINVOC_COUNT_LO', + 'mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VGT_IAPRIM_COUNT_HI', + 'mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX', 'mmCP_VGT_IAPRIM_COUNT_LO', + 'mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX', 'mmCP_VGT_IAVERT_COUNT_HI', + 'mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX', 'mmCP_VGT_IAVERT_COUNT_LO', + 'mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX', 'mmCP_VGT_VSINVOC_COUNT_HI', + 'mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX', 'mmCP_VGT_VSINVOC_COUNT_LO', + 'mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX', 'mmCP_VIRT_STATUS', + 'mmCP_VIRT_STATUS_BASE_IDX', 'mmCP_VMID', 'mmCP_VMID_BASE_IDX', + 'mmCP_VMID_PREEMPT', 'mmCP_VMID_PREEMPT_BASE_IDX', + 'mmCP_VMID_RESET', 'mmCP_VMID_RESET_BASE_IDX', 'mmCP_VMID_STATUS', + 'mmCP_VMID_STATUS_BASE_IDX', 'mmCP_WAIT_REG_MEM_TIMEOUT', + 'mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX', 'mmCP_WAIT_SEM_ADDR_HI', + 'mmCP_WAIT_SEM_ADDR_HI_BASE_IDX', 'mmCP_WAIT_SEM_ADDR_LO', + 'mmCP_WAIT_SEM_ADDR_LO_BASE_IDX', 'mmCS_COPY_STATE', + 'mmCS_COPY_STATE_BASE_IDX', 'mmDB_ALPHA_TO_MASK', + 'mmDB_ALPHA_TO_MASK_BASE_IDX', 'mmDB_CGTT_CLK_CTRL_0', + 'mmDB_CGTT_CLK_CTRL_0_BASE_IDX', 'mmDB_COUNT_CONTROL', + 'mmDB_COUNT_CONTROL_BASE_IDX', 'mmDB_CREDIT_LIMIT', + 'mmDB_CREDIT_LIMIT_BASE_IDX', 'mmDB_DEBUG', 'mmDB_DEBUG2', + 'mmDB_DEBUG2_BASE_IDX', 'mmDB_DEBUG3', 'mmDB_DEBUG3_BASE_IDX', + 'mmDB_DEBUG4', 'mmDB_DEBUG4_BASE_IDX', 'mmDB_DEBUG5', + 'mmDB_DEBUG5_BASE_IDX', 'mmDB_DEBUG_BASE_IDX', + 'mmDB_DEPTH_BOUNDS_MAX', 'mmDB_DEPTH_BOUNDS_MAX_BASE_IDX', + 'mmDB_DEPTH_BOUNDS_MIN', 'mmDB_DEPTH_BOUNDS_MIN_BASE_IDX', + 'mmDB_DEPTH_CLEAR', 'mmDB_DEPTH_CLEAR_BASE_IDX', + 'mmDB_DEPTH_CONTROL', 'mmDB_DEPTH_CONTROL_BASE_IDX', + 'mmDB_DEPTH_SIZE_XY', 'mmDB_DEPTH_SIZE_XY_BASE_IDX', + 'mmDB_DEPTH_VIEW', 'mmDB_DEPTH_VIEW_BASE_IDX', 'mmDB_DFSM_CONFIG', + 'mmDB_DFSM_CONFIG_BASE_IDX', 'mmDB_DFSM_CONTROL', + 'mmDB_DFSM_CONTROL_BASE_IDX', 'mmDB_DFSM_FLUSH_AUX_EVENT', + 'mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX', 'mmDB_DFSM_FLUSH_ENABLE', + 'mmDB_DFSM_FLUSH_ENABLE_BASE_IDX', 'mmDB_DFSM_PRIMS_IN_FLIGHT', + 'mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX', 'mmDB_DFSM_TILES_IN_FLIGHT', + 'mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX', 'mmDB_DFSM_WATCHDOG', + 'mmDB_DFSM_WATCHDOG_BASE_IDX', 'mmDB_EQAA', 'mmDB_EQAA_BASE_IDX', + 'mmDB_EQUAD_STUTTER_CONTROL', + 'mmDB_EQUAD_STUTTER_CONTROL_BASE_IDX', + 'mmDB_ETILE_STUTTER_CONTROL', + 'mmDB_ETILE_STUTTER_CONTROL_BASE_IDX', 'mmDB_EXCEPTION_CONTROL', + 'mmDB_EXCEPTION_CONTROL_BASE_IDX', + 'mmDB_FGCG_INTERFACES_CLK_CTRL', + 'mmDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX', + 'mmDB_FGCG_SRAMS_CLK_CTRL', 'mmDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX', + 'mmDB_FIFO_DEPTH1', 'mmDB_FIFO_DEPTH1_BASE_IDX', + 'mmDB_FIFO_DEPTH2', 'mmDB_FIFO_DEPTH2_BASE_IDX', + 'mmDB_FIFO_DEPTH3', 'mmDB_FIFO_DEPTH3_BASE_IDX', + 'mmDB_FREE_CACHELINES', 'mmDB_FREE_CACHELINES_BASE_IDX', + 'mmDB_HTILE_DATA_BASE', 'mmDB_HTILE_DATA_BASE_BASE_IDX', + 'mmDB_HTILE_DATA_BASE_HI', 'mmDB_HTILE_DATA_BASE_HI_BASE_IDX', + 'mmDB_HTILE_SURFACE', 'mmDB_HTILE_SURFACE_BASE_IDX', + 'mmDB_LAST_OF_BURST_CONFIG', 'mmDB_LAST_OF_BURST_CONFIG_BASE_IDX', + 'mmDB_LQUAD_STUTTER_CONTROL', + 'mmDB_LQUAD_STUTTER_CONTROL_BASE_IDX', + 'mmDB_LTILE_STUTTER_CONTROL', + 'mmDB_LTILE_STUTTER_CONTROL_BASE_IDX', 'mmDB_MEM_ARB_WATERMARKS', + 'mmDB_MEM_ARB_WATERMARKS_BASE_IDX', 'mmDB_OCCLUSION_COUNT0_HI', + 'mmDB_OCCLUSION_COUNT0_HI_BASE_IDX', 'mmDB_OCCLUSION_COUNT0_LOW', + 'mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX', 'mmDB_OCCLUSION_COUNT1_HI', + 'mmDB_OCCLUSION_COUNT1_HI_BASE_IDX', 'mmDB_OCCLUSION_COUNT1_LOW', + 'mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX', 'mmDB_OCCLUSION_COUNT2_HI', + 'mmDB_OCCLUSION_COUNT2_HI_BASE_IDX', 'mmDB_OCCLUSION_COUNT2_LOW', + 'mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX', 'mmDB_OCCLUSION_COUNT3_HI', + 'mmDB_OCCLUSION_COUNT3_HI_BASE_IDX', 'mmDB_OCCLUSION_COUNT3_LOW', + 'mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX', 'mmDB_PERFCOUNTER0_HI', + 'mmDB_PERFCOUNTER0_HI_BASE_IDX', 'mmDB_PERFCOUNTER0_LO', + 'mmDB_PERFCOUNTER0_LO_BASE_IDX', 'mmDB_PERFCOUNTER0_SELECT', + 'mmDB_PERFCOUNTER0_SELECT1', 'mmDB_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmDB_PERFCOUNTER0_SELECT_BASE_IDX', 'mmDB_PERFCOUNTER1_HI', + 'mmDB_PERFCOUNTER1_HI_BASE_IDX', 'mmDB_PERFCOUNTER1_LO', + 'mmDB_PERFCOUNTER1_LO_BASE_IDX', 'mmDB_PERFCOUNTER1_SELECT', + 'mmDB_PERFCOUNTER1_SELECT1', 'mmDB_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmDB_PERFCOUNTER1_SELECT_BASE_IDX', 'mmDB_PERFCOUNTER2_HI', + 'mmDB_PERFCOUNTER2_HI_BASE_IDX', 'mmDB_PERFCOUNTER2_LO', + 'mmDB_PERFCOUNTER2_LO_BASE_IDX', 'mmDB_PERFCOUNTER2_SELECT', + 'mmDB_PERFCOUNTER2_SELECT_BASE_IDX', 'mmDB_PERFCOUNTER3_HI', + 'mmDB_PERFCOUNTER3_HI_BASE_IDX', 'mmDB_PERFCOUNTER3_LO', + 'mmDB_PERFCOUNTER3_LO_BASE_IDX', 'mmDB_PERFCOUNTER3_SELECT', + 'mmDB_PERFCOUNTER3_SELECT_BASE_IDX', 'mmDB_PRELOAD_CONTROL', + 'mmDB_PRELOAD_CONTROL_BASE_IDX', 'mmDB_RENDER_CONTROL', + 'mmDB_RENDER_CONTROL_BASE_IDX', 'mmDB_RENDER_OVERRIDE', + 'mmDB_RENDER_OVERRIDE2', 'mmDB_RENDER_OVERRIDE2_BASE_IDX', + 'mmDB_RENDER_OVERRIDE_BASE_IDX', 'mmDB_RESERVED_REG_1', + 'mmDB_RESERVED_REG_1_BASE_IDX', 'mmDB_RESERVED_REG_2', + 'mmDB_RESERVED_REG_2_BASE_IDX', 'mmDB_RESERVED_REG_3', + 'mmDB_RESERVED_REG_3_BASE_IDX', 'mmDB_RING_CONTROL', + 'mmDB_RING_CONTROL_BASE_IDX', 'mmDB_RMI_BC_GL2_CACHE_CONTROL', + 'mmDB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX', + 'mmDB_RMI_L2_CACHE_CONTROL', 'mmDB_RMI_L2_CACHE_CONTROL_BASE_IDX', + 'mmDB_SHADER_CONTROL', 'mmDB_SHADER_CONTROL_BASE_IDX', + 'mmDB_SRESULTS_COMPARE_STATE0', + 'mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX', + 'mmDB_SRESULTS_COMPARE_STATE1', + 'mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX', 'mmDB_STENCILREFMASK', + 'mmDB_STENCILREFMASK_BASE_IDX', 'mmDB_STENCILREFMASK_BF', + 'mmDB_STENCILREFMASK_BF_BASE_IDX', 'mmDB_STENCIL_CLEAR', + 'mmDB_STENCIL_CLEAR_BASE_IDX', 'mmDB_STENCIL_CONTROL', + 'mmDB_STENCIL_CONTROL_BASE_IDX', 'mmDB_STENCIL_INFO', + 'mmDB_STENCIL_INFO_BASE_IDX', 'mmDB_STENCIL_READ_BASE', + 'mmDB_STENCIL_READ_BASE_BASE_IDX', 'mmDB_STENCIL_READ_BASE_HI', + 'mmDB_STENCIL_READ_BASE_HI_BASE_IDX', 'mmDB_STENCIL_WRITE_BASE', + 'mmDB_STENCIL_WRITE_BASE_BASE_IDX', 'mmDB_STENCIL_WRITE_BASE_HI', + 'mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX', 'mmDB_SUBTILE_CONTROL', + 'mmDB_SUBTILE_CONTROL_BASE_IDX', 'mmDB_VRS_OVERRIDE_CNTL', + 'mmDB_VRS_OVERRIDE_CNTL_BASE_IDX', 'mmDB_WATERMARKS', + 'mmDB_WATERMARKS_BASE_IDX', 'mmDB_ZPASS_COUNT_HI', + 'mmDB_ZPASS_COUNT_HI_BASE_IDX', 'mmDB_ZPASS_COUNT_LOW', + 'mmDB_ZPASS_COUNT_LOW_BASE_IDX', 'mmDB_Z_INFO', + 'mmDB_Z_INFO_BASE_IDX', 'mmDB_Z_READ_BASE', + 'mmDB_Z_READ_BASE_BASE_IDX', 'mmDB_Z_READ_BASE_HI', + 'mmDB_Z_READ_BASE_HI_BASE_IDX', 'mmDB_Z_WRITE_BASE', + 'mmDB_Z_WRITE_BASE_BASE_IDX', 'mmDB_Z_WRITE_BASE_HI', + 'mmDB_Z_WRITE_BASE_HI_BASE_IDX', 'mmDIDT_INDEX_AUTO_INCR_EN', + 'mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX', 'mmDIDT_IND_DATA', + 'mmDIDT_IND_DATA_BASE_IDX', 'mmDIDT_IND_INDEX', + 'mmDIDT_IND_INDEX_BASE_IDX', 'mmEDC_HYSTERESIS_CNTL', + 'mmEDC_HYSTERESIS_CNTL_BASE_IDX', 'mmEDC_HYSTERESIS_STAT', + 'mmEDC_HYSTERESIS_STAT_BASE_IDX', 'mmEDC_PERF_COUNTER', + 'mmEDC_PERF_COUNTER_BASE_IDX', 'mmGB_ADDR_CONFIG', + 'mmGB_ADDR_CONFIG_BASE_IDX', 'mmGB_ADDR_CONFIG_READ', + 'mmGB_ADDR_CONFIG_READ_BASE_IDX', 'mmGB_BACKEND_MAP', + 'mmGB_BACKEND_MAP_BASE_IDX', 'mmGB_EDC_MODE', + 'mmGB_EDC_MODE_BASE_IDX', 'mmGB_GPU_ID', 'mmGB_GPU_ID_BASE_IDX', + 'mmGCEA_CGTT_CLK_CTRL', 'mmGCEA_CGTT_CLK_CTRL_BASE_IDX', + 'mmGCEA_DRAM_PAGE_BURST', 'mmGCEA_DRAM_PAGE_BURST_BASE_IDX', + 'mmGCEA_DRAM_RD_CAM_CNTL', 'mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX', + 'mmGCEA_DRAM_RD_CLI2GRP_MAP0', + 'mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX', + 'mmGCEA_DRAM_RD_CLI2GRP_MAP1', + 'mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX', + 'mmGCEA_DRAM_RD_GRP2VC_MAP', 'mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX', + 'mmGCEA_DRAM_RD_LAZY', 'mmGCEA_DRAM_RD_LAZY_BASE_IDX', + 'mmGCEA_DRAM_RD_PRI_AGE', 'mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX', + 'mmGCEA_DRAM_RD_PRI_FIXED', 'mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX', + 'mmGCEA_DRAM_RD_PRI_QUANT_PRI1', + 'mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX', + 'mmGCEA_DRAM_RD_PRI_QUANT_PRI2', + 'mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX', + 'mmGCEA_DRAM_RD_PRI_QUANT_PRI3', + 'mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX', + 'mmGCEA_DRAM_RD_PRI_QUEUING', + 'mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX', + 'mmGCEA_DRAM_RD_PRI_URGENCY', + 'mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX', 'mmGCEA_DRAM_WR_CAM_CNTL', + 'mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX', 'mmGCEA_DRAM_WR_CLI2GRP_MAP0', + 'mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX', + 'mmGCEA_DRAM_WR_CLI2GRP_MAP1', + 'mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX', + 'mmGCEA_DRAM_WR_GRP2VC_MAP', 'mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX', + 'mmGCEA_DRAM_WR_LAZY', 'mmGCEA_DRAM_WR_LAZY_BASE_IDX', + 'mmGCEA_DRAM_WR_PRI_AGE', 'mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX', + 'mmGCEA_DRAM_WR_PRI_FIXED', 'mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX', + 'mmGCEA_DRAM_WR_PRI_QUANT_PRI1', + 'mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX', + 'mmGCEA_DRAM_WR_PRI_QUANT_PRI2', + 'mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX', + 'mmGCEA_DRAM_WR_PRI_QUANT_PRI3', + 'mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX', + 'mmGCEA_DRAM_WR_PRI_QUEUING', + 'mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX', + 'mmGCEA_DRAM_WR_PRI_URGENCY', + 'mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX', 'mmGCEA_DSM_CNTL', + 'mmGCEA_DSM_CNTL2', 'mmGCEA_DSM_CNTL2A', + 'mmGCEA_DSM_CNTL2A_BASE_IDX', 'mmGCEA_DSM_CNTL2B', + 'mmGCEA_DSM_CNTL2B_BASE_IDX', 'mmGCEA_DSM_CNTL2_BASE_IDX', + 'mmGCEA_DSM_CNTLA', 'mmGCEA_DSM_CNTLA_BASE_IDX', + 'mmGCEA_DSM_CNTLB', 'mmGCEA_DSM_CNTLB_BASE_IDX', + 'mmGCEA_DSM_CNTL_BASE_IDX', 'mmGCEA_ERR_STATUS', + 'mmGCEA_ERR_STATUS_BASE_IDX', 'mmGCEA_GL2C_XBR_CREDITS', + 'mmGCEA_GL2C_XBR_CREDITS_BASE_IDX', 'mmGCEA_GL2C_XBR_MAXBURST', + 'mmGCEA_GL2C_XBR_MAXBURST_BASE_IDX', 'mmGCEA_IO_GROUP_BURST', + 'mmGCEA_IO_GROUP_BURST_BASE_IDX', 'mmGCEA_IO_RD_CLI2GRP_MAP0', + 'mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX', 'mmGCEA_IO_RD_CLI2GRP_MAP1', + 'mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX', + 'mmGCEA_IO_RD_COMBINE_FLUSH', + 'mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX', 'mmGCEA_IO_RD_PRI_AGE', + 'mmGCEA_IO_RD_PRI_AGE_BASE_IDX', 'mmGCEA_IO_RD_PRI_FIXED', + 'mmGCEA_IO_RD_PRI_FIXED_BASE_IDX', 'mmGCEA_IO_RD_PRI_QUANT_PRI1', + 'mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX', + 'mmGCEA_IO_RD_PRI_QUANT_PRI2', + 'mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX', + 'mmGCEA_IO_RD_PRI_QUANT_PRI3', + 'mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX', + 'mmGCEA_IO_RD_PRI_QUEUING', 'mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX', + 'mmGCEA_IO_RD_PRI_URGENCY', 'mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX', + 'mmGCEA_IO_RD_PRI_URGENCY_MASKING', + 'mmGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX', + 'mmGCEA_IO_WR_CLI2GRP_MAP0', 'mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX', + 'mmGCEA_IO_WR_CLI2GRP_MAP1', 'mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX', + 'mmGCEA_IO_WR_COMBINE_FLUSH', + 'mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX', 'mmGCEA_IO_WR_PRI_AGE', + 'mmGCEA_IO_WR_PRI_AGE_BASE_IDX', 'mmGCEA_IO_WR_PRI_FIXED', + 'mmGCEA_IO_WR_PRI_FIXED_BASE_IDX', 'mmGCEA_IO_WR_PRI_QUANT_PRI1', + 'mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX', + 'mmGCEA_IO_WR_PRI_QUANT_PRI2', + 'mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX', + 'mmGCEA_IO_WR_PRI_QUANT_PRI3', + 'mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX', + 'mmGCEA_IO_WR_PRI_QUEUING', 'mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX', + 'mmGCEA_IO_WR_PRI_URGENCY', 'mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX', + 'mmGCEA_IO_WR_PRI_URGENCY_MASKING', + 'mmGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX', + 'mmGCEA_LATENCY_SAMPLING', 'mmGCEA_LATENCY_SAMPLING_BASE_IDX', + 'mmGCEA_MISC', 'mmGCEA_MISC2', 'mmGCEA_MISC2_BASE_IDX', + 'mmGCEA_MISC_BASE_IDX', 'mmGCEA_PERFCOUNTER0_CFG', + 'mmGCEA_PERFCOUNTER0_CFG_BASE_IDX', 'mmGCEA_PERFCOUNTER1_CFG', + 'mmGCEA_PERFCOUNTER1_CFG_BASE_IDX', 'mmGCEA_PERFCOUNTER2_HI', + 'mmGCEA_PERFCOUNTER2_HI_BASE_IDX', 'mmGCEA_PERFCOUNTER2_LO', + 'mmGCEA_PERFCOUNTER2_LO_BASE_IDX', 'mmGCEA_PERFCOUNTER2_MODE', + 'mmGCEA_PERFCOUNTER2_MODE_BASE_IDX', 'mmGCEA_PERFCOUNTER2_SELECT', + 'mmGCEA_PERFCOUNTER2_SELECT1', + 'mmGCEA_PERFCOUNTER2_SELECT1_BASE_IDX', + 'mmGCEA_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGCEA_PERFCOUNTER_HI', + 'mmGCEA_PERFCOUNTER_HI_BASE_IDX', 'mmGCEA_PERFCOUNTER_LO', + 'mmGCEA_PERFCOUNTER_LO_BASE_IDX', 'mmGCEA_PERFCOUNTER_RSLT_CNTL', + 'mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'mmGCEA_PROBE_CNTL', + 'mmGCEA_PROBE_CNTL_BASE_IDX', 'mmGCEA_PROBE_MAP', + 'mmGCEA_PROBE_MAP_BASE_IDX', 'mmGCEA_RRET_MEM_RESERVE', + 'mmGCEA_RRET_MEM_RESERVE_BASE_IDX', 'mmGCMC_MEM_POWER_LS', + 'mmGCMC_MEM_POWER_LS_BASE_IDX', 'mmGCMC_SHARED_ACTIVE_FCN_ID', + 'mmGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX', + 'mmGCMC_SHARED_VIRT_RESET_REQ', 'mmGCMC_SHARED_VIRT_RESET_REQ2', + 'mmGCMC_SHARED_VIRT_RESET_REQ2_BASE_IDX', + 'mmGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX', 'mmGCMC_VM_AGP_BASE', + 'mmGCMC_VM_AGP_BASE_BASE_IDX', 'mmGCMC_VM_AGP_BOT', + 'mmGCMC_VM_AGP_BOT_BASE_IDX', 'mmGCMC_VM_AGP_TOP', + 'mmGCMC_VM_AGP_TOP_BASE_IDX', 'mmGCMC_VM_APT_CNTL', + 'mmGCMC_VM_APT_CNTL_BASE_IDX', + 'mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END', + 'mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX', + 'mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START', + 'mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX', + 'mmGCMC_VM_FB_LOCATION_BASE', + 'mmGCMC_VM_FB_LOCATION_BASE_BASE_IDX', + 'mmGCMC_VM_FB_LOCATION_TOP', 'mmGCMC_VM_FB_LOCATION_TOP_BASE_IDX', + 'mmGCMC_VM_FB_NOALLOC_CNTL', 'mmGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX', + 'mmGCMC_VM_FB_OFFSET', 'mmGCMC_VM_FB_OFFSET_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF0', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF1', 'mmGCMC_VM_FB_SIZE_OFFSET_VF10', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF11', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF12', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF13', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF14', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF15', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF16', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF17', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF18', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF19', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF2', 'mmGCMC_VM_FB_SIZE_OFFSET_VF20', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF21', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF22', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF23', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF24', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF25', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF26', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF27', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF28', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF29', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF3', 'mmGCMC_VM_FB_SIZE_OFFSET_VF30', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF31', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF4', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF5', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF6', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF7', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF8', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF9', + 'mmGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX', + 'mmGCMC_VM_L2_PERFCOUNTER0_CFG', + 'mmGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX', + 'mmGCMC_VM_L2_PERFCOUNTER1_CFG', + 'mmGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX', + 'mmGCMC_VM_L2_PERFCOUNTER2_CFG', + 'mmGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX', + 'mmGCMC_VM_L2_PERFCOUNTER3_CFG', + 'mmGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX', + 'mmGCMC_VM_L2_PERFCOUNTER4_CFG', + 'mmGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX', + 'mmGCMC_VM_L2_PERFCOUNTER5_CFG', + 'mmGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX', + 'mmGCMC_VM_L2_PERFCOUNTER6_CFG', + 'mmGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX', + 'mmGCMC_VM_L2_PERFCOUNTER7_CFG', + 'mmGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX', + 'mmGCMC_VM_L2_PERFCOUNTER_HI', + 'mmGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX', + 'mmGCMC_VM_L2_PERFCOUNTER_LO', + 'mmGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX', + 'mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL', + 'mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'mmGCMC_VM_LOCAL_HBM_ADDRESS_END', + 'mmGCMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX', + 'mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL', + 'mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX', + 'mmGCMC_VM_LOCAL_HBM_ADDRESS_START', + 'mmGCMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX', + 'mmGCMC_VM_MARC_BASE_HI_0', 'mmGCMC_VM_MARC_BASE_HI_0_BASE_IDX', + 'mmGCMC_VM_MARC_BASE_HI_1', 'mmGCMC_VM_MARC_BASE_HI_1_BASE_IDX', + 'mmGCMC_VM_MARC_BASE_HI_2', 'mmGCMC_VM_MARC_BASE_HI_2_BASE_IDX', + 'mmGCMC_VM_MARC_BASE_HI_3', 'mmGCMC_VM_MARC_BASE_HI_3_BASE_IDX', + 'mmGCMC_VM_MARC_BASE_LO_0', 'mmGCMC_VM_MARC_BASE_LO_0_BASE_IDX', + 'mmGCMC_VM_MARC_BASE_LO_1', 'mmGCMC_VM_MARC_BASE_LO_1_BASE_IDX', + 'mmGCMC_VM_MARC_BASE_LO_2', 'mmGCMC_VM_MARC_BASE_LO_2_BASE_IDX', + 'mmGCMC_VM_MARC_BASE_LO_3', 'mmGCMC_VM_MARC_BASE_LO_3_BASE_IDX', + 'mmGCMC_VM_MARC_LEN_HI_0', 'mmGCMC_VM_MARC_LEN_HI_0_BASE_IDX', + 'mmGCMC_VM_MARC_LEN_HI_1', 'mmGCMC_VM_MARC_LEN_HI_1_BASE_IDX', + 'mmGCMC_VM_MARC_LEN_HI_2', 'mmGCMC_VM_MARC_LEN_HI_2_BASE_IDX', + 'mmGCMC_VM_MARC_LEN_HI_3', 'mmGCMC_VM_MARC_LEN_HI_3_BASE_IDX', + 'mmGCMC_VM_MARC_LEN_LO_0', 'mmGCMC_VM_MARC_LEN_LO_0_BASE_IDX', + 'mmGCMC_VM_MARC_LEN_LO_1', 'mmGCMC_VM_MARC_LEN_LO_1_BASE_IDX', + 'mmGCMC_VM_MARC_LEN_LO_2', 'mmGCMC_VM_MARC_LEN_LO_2_BASE_IDX', + 'mmGCMC_VM_MARC_LEN_LO_3', 'mmGCMC_VM_MARC_LEN_LO_3_BASE_IDX', + 'mmGCMC_VM_MARC_RELOC_HI_0', 'mmGCMC_VM_MARC_RELOC_HI_0_BASE_IDX', + 'mmGCMC_VM_MARC_RELOC_HI_1', 'mmGCMC_VM_MARC_RELOC_HI_1_BASE_IDX', + 'mmGCMC_VM_MARC_RELOC_HI_2', 'mmGCMC_VM_MARC_RELOC_HI_2_BASE_IDX', + 'mmGCMC_VM_MARC_RELOC_HI_3', 'mmGCMC_VM_MARC_RELOC_HI_3_BASE_IDX', + 'mmGCMC_VM_MARC_RELOC_LO_0', 'mmGCMC_VM_MARC_RELOC_LO_0_BASE_IDX', + 'mmGCMC_VM_MARC_RELOC_LO_1', 'mmGCMC_VM_MARC_RELOC_LO_1_BASE_IDX', + 'mmGCMC_VM_MARC_RELOC_LO_2', 'mmGCMC_VM_MARC_RELOC_LO_2_BASE_IDX', + 'mmGCMC_VM_MARC_RELOC_LO_3', 'mmGCMC_VM_MARC_RELOC_LO_3_BASE_IDX', + 'mmGCMC_VM_MX_L1_TLB_CNTL', 'mmGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX', + 'mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2', + 'mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX', + 'mmGCMC_VM_NB_MMIOBASE', 'mmGCMC_VM_NB_MMIOBASE_BASE_IDX', + 'mmGCMC_VM_NB_MMIOLIMIT', 'mmGCMC_VM_NB_MMIOLIMIT_BASE_IDX', + 'mmGCMC_VM_NB_PCI_ARB', 'mmGCMC_VM_NB_PCI_ARB_BASE_IDX', + 'mmGCMC_VM_NB_PCI_CTRL', 'mmGCMC_VM_NB_PCI_CTRL_BASE_IDX', + 'mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1', + 'mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX', + 'mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2', + 'mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX', 'mmGCMC_VM_STEERING', + 'mmGCMC_VM_STEERING_BASE_IDX', + 'mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB', + 'mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX', + 'mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB', + 'mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX', + 'mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR', + 'mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX', + 'mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR', + 'mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX', + 'mmGCMC_VM_XGMI_GPUIOV_ENABLE', + 'mmGCMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX', + 'mmGCMC_VM_XGMI_LFB_CNTL', 'mmGCMC_VM_XGMI_LFB_CNTL_BASE_IDX', + 'mmGCMC_VM_XGMI_LFB_SIZE', 'mmGCMC_VM_XGMI_LFB_SIZE_BASE_IDX', + 'mmGCRD_SA_TARGETS_DISABLE', 'mmGCRD_SA_TARGETS_DISABLE_BASE_IDX', + 'mmGCR_CGTT_SCLK_CTRL', 'mmGCR_CGTT_SCLK_CTRL_BASE_IDX', + 'mmGCR_CMD_STATUS', 'mmGCR_CMD_STATUS_BASE_IDX', + 'mmGCR_GENERAL_CNTL', 'mmGCR_GENERAL_CNTL_BASE_IDX', + 'mmGCR_PERFCOUNTER0_HI', 'mmGCR_PERFCOUNTER0_HI_BASE_IDX', + 'mmGCR_PERFCOUNTER0_LO', 'mmGCR_PERFCOUNTER0_LO_BASE_IDX', + 'mmGCR_PERFCOUNTER0_SELECT', 'mmGCR_PERFCOUNTER0_SELECT1', + 'mmGCR_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmGCR_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGCR_PERFCOUNTER1_HI', + 'mmGCR_PERFCOUNTER1_HI_BASE_IDX', 'mmGCR_PERFCOUNTER1_LO', + 'mmGCR_PERFCOUNTER1_LO_BASE_IDX', 'mmGCR_PERFCOUNTER1_SELECT', + 'mmGCR_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGCR_PIO_CNTL', + 'mmGCR_PIO_CNTL_BASE_IDX', 'mmGCR_PIO_DATA', + 'mmGCR_PIO_DATA_BASE_IDX', 'mmGCR_SPARE', 'mmGCR_SPARE_BASE_IDX', + 'mmGCUTCL2_HARVEST_BYPASS_GROUPS', + 'mmGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX', + 'mmGCUTCL2_PERFCOUNTER0_CFG', + 'mmGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX', + 'mmGCUTCL2_PERFCOUNTER1_CFG', + 'mmGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX', + 'mmGCUTCL2_PERFCOUNTER2_CFG', + 'mmGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX', + 'mmGCUTCL2_PERFCOUNTER3_CFG', + 'mmGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX', 'mmGCUTCL2_PERFCOUNTER_HI', + 'mmGCUTCL2_PERFCOUNTER_HI_BASE_IDX', 'mmGCUTCL2_PERFCOUNTER_LO', + 'mmGCUTCL2_PERFCOUNTER_LO_BASE_IDX', + 'mmGCUTCL2_PERFCOUNTER_RSLT_CNTL', + 'mmGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID', + 'mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX', + 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI', + 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX', + 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO', + 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX', + 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI', + 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX', + 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO', + 'mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX', + 'mmGCVML2_PERFCOUNTER2_0_HI', + 'mmGCVML2_PERFCOUNTER2_0_HI_BASE_IDX', + 'mmGCVML2_PERFCOUNTER2_0_LO', + 'mmGCVML2_PERFCOUNTER2_0_LO_BASE_IDX', + 'mmGCVML2_PERFCOUNTER2_0_MODE', + 'mmGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX', + 'mmGCVML2_PERFCOUNTER2_0_SELECT', + 'mmGCVML2_PERFCOUNTER2_0_SELECT1', + 'mmGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX', + 'mmGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX', + 'mmGCVML2_PERFCOUNTER2_1_HI', + 'mmGCVML2_PERFCOUNTER2_1_HI_BASE_IDX', + 'mmGCVML2_PERFCOUNTER2_1_LO', + 'mmGCVML2_PERFCOUNTER2_1_LO_BASE_IDX', + 'mmGCVML2_PERFCOUNTER2_1_MODE', + 'mmGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX', + 'mmGCVML2_PERFCOUNTER2_1_SELECT', + 'mmGCVML2_PERFCOUNTER2_1_SELECT1', + 'mmGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX', + 'mmGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX', + 'mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT', + 'mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX', + 'mmGCVML2_WALKER_MACRO_THROTTLE_TIME', + 'mmGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX', + 'mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT', + 'mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX', + 'mmGCVML2_WALKER_MICRO_THROTTLE_TIME', + 'mmGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX', + 'mmGCVM_CONTEXT0_CNTL', 'mmGCVM_CONTEXT0_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT10_CNTL', 'mmGCVM_CONTEXT10_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT11_CNTL', 'mmGCVM_CONTEXT11_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT12_CNTL', 'mmGCVM_CONTEXT12_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT13_CNTL', 'mmGCVM_CONTEXT13_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT14_CNTL', 'mmGCVM_CONTEXT14_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT15_CNTL', 'mmGCVM_CONTEXT15_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT1_CNTL', 'mmGCVM_CONTEXT1_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT2_CNTL', 'mmGCVM_CONTEXT2_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT3_CNTL', 'mmGCVM_CONTEXT3_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT4_CNTL', 'mmGCVM_CONTEXT4_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT5_CNTL', 'mmGCVM_CONTEXT5_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT6_CNTL', 'mmGCVM_CONTEXT6_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT7_CNTL', 'mmGCVM_CONTEXT7_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT8_CNTL', 'mmGCVM_CONTEXT8_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT9_CNTL', 'mmGCVM_CONTEXT9_CNTL_BASE_IDX', + 'mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32', + 'mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32', + 'mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32', + 'mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32', + 'mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32', + 'mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX', + 'mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32', + 'mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX', + 'mmGCVM_CONTEXTS_DISABLE', 'mmGCVM_CONTEXTS_DISABLE_BASE_IDX', + 'mmGCVM_DEBUG', 'mmGCVM_DEBUG_BASE_IDX', + 'mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32', + 'mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX', + 'mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32', + 'mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX', + 'mmGCVM_DUMMY_PAGE_FAULT_CNTL', + 'mmGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX', 'mmGCVM_INVALIDATE_CNTL', + 'mmGCVM_INVALIDATE_CNTL_BASE_IDX', 'mmGCVM_INVALIDATE_ENG0_ACK', + 'mmGCVM_INVALIDATE_ENG0_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG0_REQ', + 'mmGCVM_INVALIDATE_ENG0_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG0_SEM', + 'mmGCVM_INVALIDATE_ENG0_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG10_ACK', + 'mmGCVM_INVALIDATE_ENG10_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG10_REQ', + 'mmGCVM_INVALIDATE_ENG10_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG10_SEM', + 'mmGCVM_INVALIDATE_ENG10_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG11_ACK', + 'mmGCVM_INVALIDATE_ENG11_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG11_REQ', + 'mmGCVM_INVALIDATE_ENG11_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG11_SEM', + 'mmGCVM_INVALIDATE_ENG11_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG12_ACK', + 'mmGCVM_INVALIDATE_ENG12_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG12_REQ', + 'mmGCVM_INVALIDATE_ENG12_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG12_SEM', + 'mmGCVM_INVALIDATE_ENG12_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG13_ACK', + 'mmGCVM_INVALIDATE_ENG13_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG13_REQ', + 'mmGCVM_INVALIDATE_ENG13_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG13_SEM', + 'mmGCVM_INVALIDATE_ENG13_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG14_ACK', + 'mmGCVM_INVALIDATE_ENG14_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG14_REQ', + 'mmGCVM_INVALIDATE_ENG14_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG14_SEM', + 'mmGCVM_INVALIDATE_ENG14_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG15_ACK', + 'mmGCVM_INVALIDATE_ENG15_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG15_REQ', + 'mmGCVM_INVALIDATE_ENG15_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG15_SEM', + 'mmGCVM_INVALIDATE_ENG15_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG16_ACK', + 'mmGCVM_INVALIDATE_ENG16_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG16_REQ', + 'mmGCVM_INVALIDATE_ENG16_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG16_SEM', + 'mmGCVM_INVALIDATE_ENG16_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG17_ACK', + 'mmGCVM_INVALIDATE_ENG17_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG17_REQ', + 'mmGCVM_INVALIDATE_ENG17_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG17_SEM', + 'mmGCVM_INVALIDATE_ENG17_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG1_ACK', + 'mmGCVM_INVALIDATE_ENG1_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG1_REQ', + 'mmGCVM_INVALIDATE_ENG1_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG1_SEM', + 'mmGCVM_INVALIDATE_ENG1_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG2_ACK', + 'mmGCVM_INVALIDATE_ENG2_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG2_REQ', + 'mmGCVM_INVALIDATE_ENG2_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG2_SEM', + 'mmGCVM_INVALIDATE_ENG2_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG3_ACK', + 'mmGCVM_INVALIDATE_ENG3_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG3_REQ', + 'mmGCVM_INVALIDATE_ENG3_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG3_SEM', + 'mmGCVM_INVALIDATE_ENG3_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG4_ACK', + 'mmGCVM_INVALIDATE_ENG4_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG4_REQ', + 'mmGCVM_INVALIDATE_ENG4_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG4_SEM', + 'mmGCVM_INVALIDATE_ENG4_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG5_ACK', + 'mmGCVM_INVALIDATE_ENG5_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG5_REQ', + 'mmGCVM_INVALIDATE_ENG5_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG5_SEM', + 'mmGCVM_INVALIDATE_ENG5_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG6_ACK', + 'mmGCVM_INVALIDATE_ENG6_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG6_REQ', + 'mmGCVM_INVALIDATE_ENG6_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG6_SEM', + 'mmGCVM_INVALIDATE_ENG6_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG7_ACK', + 'mmGCVM_INVALIDATE_ENG7_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG7_REQ', + 'mmGCVM_INVALIDATE_ENG7_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG7_SEM', + 'mmGCVM_INVALIDATE_ENG7_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG8_ACK', + 'mmGCVM_INVALIDATE_ENG8_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG8_REQ', + 'mmGCVM_INVALIDATE_ENG8_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG8_SEM', + 'mmGCVM_INVALIDATE_ENG8_SEM_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG9_ACK', + 'mmGCVM_INVALIDATE_ENG9_ACK_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32', + 'mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32', + 'mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG9_REQ', + 'mmGCVM_INVALIDATE_ENG9_REQ_BASE_IDX', + 'mmGCVM_INVALIDATE_ENG9_SEM', + 'mmGCVM_INVALIDATE_ENG9_SEM_BASE_IDX', + 'mmGCVM_IOMMU_CONTROL_REGISTER', + 'mmGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX', + 'mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE', + 'mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX', + 'mmGCVM_IOMMU_MMIO_CNTRL_1', 'mmGCVM_IOMMU_MMIO_CNTRL_1_BASE_IDX', + 'mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER', + 'mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX', + 'mmGCVM_L2_BANK_SELECT_RESERVED_CID', + 'mmGCVM_L2_BANK_SELECT_RESERVED_CID2', + 'mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX', + 'mmGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX', + 'mmGCVM_L2_CACHE_PARITY_CNTL', + 'mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX', 'mmGCVM_L2_CNTL', + 'mmGCVM_L2_CNTL2', 'mmGCVM_L2_CNTL2_BASE_IDX', 'mmGCVM_L2_CNTL3', + 'mmGCVM_L2_CNTL3_BASE_IDX', 'mmGCVM_L2_CNTL4', + 'mmGCVM_L2_CNTL4_BASE_IDX', 'mmGCVM_L2_CNTL5', + 'mmGCVM_L2_CNTL5_BASE_IDX', 'mmGCVM_L2_CNTL_BASE_IDX', + 'mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32', + 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX', + 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32', + 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX', + 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32', + 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX', + 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32', + 'mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX', + 'mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32', + 'mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX', + 'mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32', + 'mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX', + 'mmGCVM_L2_GCR_CNTL', 'mmGCVM_L2_GCR_CNTL_BASE_IDX', + 'mmGCVM_L2_ID_CTRL0', 'mmGCVM_L2_ID_CTRL0_BASE_IDX', + 'mmGCVM_L2_ID_CTRL1', 'mmGCVM_L2_ID_CTRL1_BASE_IDX', + 'mmGCVM_L2_ID_CTRL2', 'mmGCVM_L2_ID_CTRL2_BASE_IDX', + 'mmGCVM_L2_ID_CTRL3', 'mmGCVM_L2_ID_CTRL3_BASE_IDX', + 'mmGCVM_L2_ID_CTRL4', 'mmGCVM_L2_ID_CTRL4_BASE_IDX', + 'mmGCVM_L2_ID_CTRL5', 'mmGCVM_L2_ID_CTRL5_BASE_IDX', + 'mmGCVM_L2_ID_CTRL6', 'mmGCVM_L2_ID_CTRL6_BASE_IDX', + 'mmGCVM_L2_ID_CTRL7', 'mmGCVM_L2_ID_CTRL7_BASE_IDX', + 'mmGCVM_L2_ID_CTRL_HI', 'mmGCVM_L2_ID_CTRL_HI_BASE_IDX', + 'mmGCVM_L2_ID_STATUS', 'mmGCVM_L2_ID_STATUS_BASE_IDX', + 'mmGCVM_L2_IH_LOG_CNTL', 'mmGCVM_L2_IH_LOG_CNTL_BASE_IDX', + 'mmGCVM_L2_MM_GROUP_RT_CLASSES', + 'mmGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX', + 'mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES', + 'mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX', + 'mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32', + 'mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX', + 'mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32', + 'mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX', + 'mmGCVM_L2_PROTECTION_FAULT_CNTL', + 'mmGCVM_L2_PROTECTION_FAULT_CNTL2', + 'mmGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX', + 'mmGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX', + 'mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32', + 'mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX', + 'mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32', + 'mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX', + 'mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3', + 'mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX', + 'mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4', + 'mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX', + 'mmGCVM_L2_PROTECTION_FAULT_STATUS', + 'mmGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX', + 'mmGCVM_L2_PTE_CACHE_DUMP_CNTL', + 'mmGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX', + 'mmGCVM_L2_PTE_CACHE_DUMP_READ', + 'mmGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX', 'mmGCVM_L2_STATUS', + 'mmGCVM_L2_STATUS_BASE_IDX', 'mmGC_CAC_AGGR_LOWER', + 'mmGC_CAC_AGGR_LOWER_BASE_IDX', 'mmGC_CAC_AGGR_UPPER', + 'mmGC_CAC_AGGR_UPPER_BASE_IDX', 'mmGC_CAC_CGTT_CLK_CTRL', + 'mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX', 'mmGC_CAC_CTRL_1', + 'mmGC_CAC_CTRL_1_BASE_IDX', 'mmGC_CAC_CTRL_2', + 'mmGC_CAC_CTRL_2_BASE_IDX', 'mmGC_CAC_IND_DATA', + 'mmGC_CAC_IND_DATA_BASE_IDX', 'mmGC_CAC_IND_INDEX', + 'mmGC_CAC_IND_INDEX_BASE_IDX', 'mmGC_CAC_SOFT_CTRL', + 'mmGC_CAC_SOFT_CTRL_BASE_IDX', 'mmGC_EDC_CTRL', + 'mmGC_EDC_CTRL_BASE_IDX', 'mmGC_EDC_OVERFLOW', + 'mmGC_EDC_OVERFLOW_BASE_IDX', 'mmGC_EDC_ROLLING_POWER_DELTA', + 'mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX', 'mmGC_EDC_STATUS', + 'mmGC_EDC_STATUS_BASE_IDX', 'mmGC_EDC_STRETCH_CTRL', + 'mmGC_EDC_STRETCH_CTRL_BASE_IDX', 'mmGC_EDC_STRETCH_THRESHOLD', + 'mmGC_EDC_STRETCH_THRESHOLD_BASE_IDX', 'mmGC_EDC_THRESHOLD', + 'mmGC_EDC_THRESHOLD_BASE_IDX', 'mmGC_IH_COOKIE_0_PTR', + 'mmGC_IH_COOKIE_0_PTR_BASE_IDX', 'mmGC_THROTTLE_CTRL', + 'mmGC_THROTTLE_CTRL1', 'mmGC_THROTTLE_CTRL1_BASE_IDX', + 'mmGC_THROTTLE_CTRL_BASE_IDX', 'mmGC_THROTTLE_STATUS', + 'mmGC_THROTTLE_STATUS_BASE_IDX', 'mmGC_USER_PRIM_CONFIG', + 'mmGC_USER_PRIM_CONFIG_BASE_IDX', 'mmGC_USER_RB_BACKEND_DISABLE', + 'mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX', + 'mmGC_USER_RB_REDUNDANCY', 'mmGC_USER_RB_REDUNDANCY_BASE_IDX', + 'mmGC_USER_RMI_REDUNDANCY', 'mmGC_USER_RMI_REDUNDANCY_BASE_IDX', + 'mmGC_USER_SA_UNIT_DISABLE', 'mmGC_USER_SA_UNIT_DISABLE_BASE_IDX', + 'mmGC_USER_SHADER_ARRAY_CONFIG', + 'mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX', + 'mmGC_USER_SHADER_RATE_CONFIG', + 'mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX', 'mmGDS_ATOM_BASE', + 'mmGDS_ATOM_BASE_BASE_IDX', 'mmGDS_ATOM_CNTL', + 'mmGDS_ATOM_CNTL_BASE_IDX', 'mmGDS_ATOM_COMPLETE', + 'mmGDS_ATOM_COMPLETE_BASE_IDX', 'mmGDS_ATOM_DST', + 'mmGDS_ATOM_DST_BASE_IDX', 'mmGDS_ATOM_OFFSET0', + 'mmGDS_ATOM_OFFSET0_BASE_IDX', 'mmGDS_ATOM_OFFSET1', + 'mmGDS_ATOM_OFFSET1_BASE_IDX', 'mmGDS_ATOM_OP', + 'mmGDS_ATOM_OP_BASE_IDX', 'mmGDS_ATOM_READ0', + 'mmGDS_ATOM_READ0_BASE_IDX', 'mmGDS_ATOM_READ0_U', + 'mmGDS_ATOM_READ0_U_BASE_IDX', 'mmGDS_ATOM_READ1', + 'mmGDS_ATOM_READ1_BASE_IDX', 'mmGDS_ATOM_READ1_U', + 'mmGDS_ATOM_READ1_U_BASE_IDX', 'mmGDS_ATOM_SIZE', + 'mmGDS_ATOM_SIZE_BASE_IDX', 'mmGDS_ATOM_SRC0', + 'mmGDS_ATOM_SRC0_BASE_IDX', 'mmGDS_ATOM_SRC0_U', + 'mmGDS_ATOM_SRC0_U_BASE_IDX', 'mmGDS_ATOM_SRC1', + 'mmGDS_ATOM_SRC1_BASE_IDX', 'mmGDS_ATOM_SRC1_U', + 'mmGDS_ATOM_SRC1_U_BASE_IDX', 'mmGDS_CNTL_STATUS', + 'mmGDS_CNTL_STATUS_BASE_IDX', 'mmGDS_COMPUTE_MAX_WAVE_ID', + 'mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX', 'mmGDS_CONFIG', + 'mmGDS_CONFIG_BASE_IDX', 'mmGDS_CS_CTXSW_CNT0', + 'mmGDS_CS_CTXSW_CNT0_BASE_IDX', 'mmGDS_CS_CTXSW_CNT1', + 'mmGDS_CS_CTXSW_CNT1_BASE_IDX', 'mmGDS_CS_CTXSW_CNT2', + 'mmGDS_CS_CTXSW_CNT2_BASE_IDX', 'mmGDS_CS_CTXSW_CNT3', + 'mmGDS_CS_CTXSW_CNT3_BASE_IDX', 'mmGDS_CS_CTXSW_STATUS', + 'mmGDS_CS_CTXSW_STATUS_BASE_IDX', 'mmGDS_DSM_CNTL', + 'mmGDS_DSM_CNTL2', 'mmGDS_DSM_CNTL2_BASE_IDX', + 'mmGDS_DSM_CNTL_BASE_IDX', 'mmGDS_EDC_CNT', + 'mmGDS_EDC_CNT_BASE_IDX', 'mmGDS_EDC_GRBM_CNT', + 'mmGDS_EDC_GRBM_CNT_BASE_IDX', 'mmGDS_EDC_OA_DED', + 'mmGDS_EDC_OA_DED_BASE_IDX', 'mmGDS_EDC_OA_PHY_CNT', + 'mmGDS_EDC_OA_PHY_CNT_BASE_IDX', 'mmGDS_EDC_OA_PIPE_CNT', + 'mmGDS_EDC_OA_PIPE_CNT_BASE_IDX', 'mmGDS_ENHANCE', + 'mmGDS_ENHANCE2', 'mmGDS_ENHANCE2_BASE_IDX', + 'mmGDS_ENHANCE_BASE_IDX', 'mmGDS_GFX_CTXSW_STATUS', + 'mmGDS_GFX_CTXSW_STATUS_BASE_IDX', 'mmGDS_GS_CTXSW_CNT0', + 'mmGDS_GS_CTXSW_CNT0_BASE_IDX', 'mmGDS_GS_CTXSW_CNT1', + 'mmGDS_GS_CTXSW_CNT1_BASE_IDX', 'mmGDS_GS_CTXSW_CNT2', + 'mmGDS_GS_CTXSW_CNT2_BASE_IDX', 'mmGDS_GS_CTXSW_CNT3', + 'mmGDS_GS_CTXSW_CNT3_BASE_IDX', 'mmGDS_GWS_RESET0', + 'mmGDS_GWS_RESET0_BASE_IDX', 'mmGDS_GWS_RESET1', + 'mmGDS_GWS_RESET1_BASE_IDX', 'mmGDS_GWS_RESOURCE', + 'mmGDS_GWS_RESOURCE_BASE_IDX', 'mmGDS_GWS_RESOURCE_CNT', + 'mmGDS_GWS_RESOURCE_CNTL', 'mmGDS_GWS_RESOURCE_CNTL_BASE_IDX', + 'mmGDS_GWS_RESOURCE_CNT_BASE_IDX', 'mmGDS_GWS_RESOURCE_RESET', + 'mmGDS_GWS_RESOURCE_RESET_BASE_IDX', 'mmGDS_GWS_VMID0', + 'mmGDS_GWS_VMID0_BASE_IDX', 'mmGDS_GWS_VMID1', 'mmGDS_GWS_VMID10', + 'mmGDS_GWS_VMID10_BASE_IDX', 'mmGDS_GWS_VMID11', + 'mmGDS_GWS_VMID11_BASE_IDX', 'mmGDS_GWS_VMID12', + 'mmGDS_GWS_VMID12_BASE_IDX', 'mmGDS_GWS_VMID13', + 'mmGDS_GWS_VMID13_BASE_IDX', 'mmGDS_GWS_VMID14', + 'mmGDS_GWS_VMID14_BASE_IDX', 'mmGDS_GWS_VMID15', + 'mmGDS_GWS_VMID15_BASE_IDX', 'mmGDS_GWS_VMID1_BASE_IDX', + 'mmGDS_GWS_VMID2', 'mmGDS_GWS_VMID2_BASE_IDX', 'mmGDS_GWS_VMID3', + 'mmGDS_GWS_VMID3_BASE_IDX', 'mmGDS_GWS_VMID4', + 'mmGDS_GWS_VMID4_BASE_IDX', 'mmGDS_GWS_VMID5', + 'mmGDS_GWS_VMID5_BASE_IDX', 'mmGDS_GWS_VMID6', + 'mmGDS_GWS_VMID6_BASE_IDX', 'mmGDS_GWS_VMID7', + 'mmGDS_GWS_VMID7_BASE_IDX', 'mmGDS_GWS_VMID8', + 'mmGDS_GWS_VMID8_BASE_IDX', 'mmGDS_GWS_VMID9', + 'mmGDS_GWS_VMID9_BASE_IDX', 'mmGDS_MEMORY_CLEAN', + 'mmGDS_MEMORY_CLEAN_BASE_IDX', 'mmGDS_OA_ADDRESS', + 'mmGDS_OA_ADDRESS_BASE_IDX', 'mmGDS_OA_CGPG_RESTORE', + 'mmGDS_OA_CGPG_RESTORE_BASE_IDX', 'mmGDS_OA_CNTL', + 'mmGDS_OA_CNTL_BASE_IDX', 'mmGDS_OA_COUNTER', + 'mmGDS_OA_COUNTER_BASE_IDX', 'mmGDS_OA_INCDEC', + 'mmGDS_OA_INCDEC_BASE_IDX', 'mmGDS_OA_RESET', + 'mmGDS_OA_RESET_BASE_IDX', 'mmGDS_OA_RESET_MASK', + 'mmGDS_OA_RESET_MASK_BASE_IDX', 'mmGDS_OA_RING_SIZE', + 'mmGDS_OA_RING_SIZE_BASE_IDX', 'mmGDS_OA_VMID0', + 'mmGDS_OA_VMID0_BASE_IDX', 'mmGDS_OA_VMID1', 'mmGDS_OA_VMID10', + 'mmGDS_OA_VMID10_BASE_IDX', 'mmGDS_OA_VMID11', + 'mmGDS_OA_VMID11_BASE_IDX', 'mmGDS_OA_VMID12', + 'mmGDS_OA_VMID12_BASE_IDX', 'mmGDS_OA_VMID13', + 'mmGDS_OA_VMID13_BASE_IDX', 'mmGDS_OA_VMID14', + 'mmGDS_OA_VMID14_BASE_IDX', 'mmGDS_OA_VMID15', + 'mmGDS_OA_VMID15_BASE_IDX', 'mmGDS_OA_VMID1_BASE_IDX', + 'mmGDS_OA_VMID2', 'mmGDS_OA_VMID2_BASE_IDX', 'mmGDS_OA_VMID3', + 'mmGDS_OA_VMID3_BASE_IDX', 'mmGDS_OA_VMID4', + 'mmGDS_OA_VMID4_BASE_IDX', 'mmGDS_OA_VMID5', + 'mmGDS_OA_VMID5_BASE_IDX', 'mmGDS_OA_VMID6', + 'mmGDS_OA_VMID6_BASE_IDX', 'mmGDS_OA_VMID7', + 'mmGDS_OA_VMID7_BASE_IDX', 'mmGDS_OA_VMID8', + 'mmGDS_OA_VMID8_BASE_IDX', 'mmGDS_OA_VMID9', + 'mmGDS_OA_VMID9_BASE_IDX', 'mmGDS_PERFCOUNTER0_HI', + 'mmGDS_PERFCOUNTER0_HI_BASE_IDX', 'mmGDS_PERFCOUNTER0_LO', + 'mmGDS_PERFCOUNTER0_LO_BASE_IDX', 'mmGDS_PERFCOUNTER0_SELECT', + 'mmGDS_PERFCOUNTER0_SELECT1', + 'mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmGDS_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGDS_PERFCOUNTER1_HI', + 'mmGDS_PERFCOUNTER1_HI_BASE_IDX', 'mmGDS_PERFCOUNTER1_LO', + 'mmGDS_PERFCOUNTER1_LO_BASE_IDX', 'mmGDS_PERFCOUNTER1_SELECT', + 'mmGDS_PERFCOUNTER1_SELECT1', + 'mmGDS_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmGDS_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGDS_PERFCOUNTER2_HI', + 'mmGDS_PERFCOUNTER2_HI_BASE_IDX', 'mmGDS_PERFCOUNTER2_LO', + 'mmGDS_PERFCOUNTER2_LO_BASE_IDX', 'mmGDS_PERFCOUNTER2_SELECT', + 'mmGDS_PERFCOUNTER2_SELECT1', + 'mmGDS_PERFCOUNTER2_SELECT1_BASE_IDX', + 'mmGDS_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGDS_PERFCOUNTER3_HI', + 'mmGDS_PERFCOUNTER3_HI_BASE_IDX', 'mmGDS_PERFCOUNTER3_LO', + 'mmGDS_PERFCOUNTER3_LO_BASE_IDX', 'mmGDS_PERFCOUNTER3_SELECT', + 'mmGDS_PERFCOUNTER3_SELECT1', + 'mmGDS_PERFCOUNTER3_SELECT1_BASE_IDX', + 'mmGDS_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGDS_PROTECTION_FAULT', + 'mmGDS_PROTECTION_FAULT_BASE_IDX', 'mmGDS_PS_CTXSW_CNT0', + 'mmGDS_PS_CTXSW_CNT0_BASE_IDX', 'mmGDS_PS_CTXSW_CNT1', + 'mmGDS_PS_CTXSW_CNT1_BASE_IDX', 'mmGDS_PS_CTXSW_CNT2', + 'mmGDS_PS_CTXSW_CNT2_BASE_IDX', 'mmGDS_PS_CTXSW_CNT3', + 'mmGDS_PS_CTXSW_CNT3_BASE_IDX', 'mmGDS_PS_CTXSW_IDX', + 'mmGDS_PS_CTXSW_IDX_BASE_IDX', 'mmGDS_RD_ADDR', + 'mmGDS_RD_ADDR_BASE_IDX', 'mmGDS_RD_BURST_ADDR', + 'mmGDS_RD_BURST_ADDR_BASE_IDX', 'mmGDS_RD_BURST_COUNT', + 'mmGDS_RD_BURST_COUNT_BASE_IDX', 'mmGDS_RD_BURST_DATA', + 'mmGDS_RD_BURST_DATA_BASE_IDX', 'mmGDS_RD_DATA', + 'mmGDS_RD_DATA_BASE_IDX', 'mmGDS_VMID0_BASE', + 'mmGDS_VMID0_BASE_BASE_IDX', 'mmGDS_VMID0_SIZE', + 'mmGDS_VMID0_SIZE_BASE_IDX', 'mmGDS_VMID10_BASE', + 'mmGDS_VMID10_BASE_BASE_IDX', 'mmGDS_VMID10_SIZE', + 'mmGDS_VMID10_SIZE_BASE_IDX', 'mmGDS_VMID11_BASE', + 'mmGDS_VMID11_BASE_BASE_IDX', 'mmGDS_VMID11_SIZE', + 'mmGDS_VMID11_SIZE_BASE_IDX', 'mmGDS_VMID12_BASE', + 'mmGDS_VMID12_BASE_BASE_IDX', 'mmGDS_VMID12_SIZE', + 'mmGDS_VMID12_SIZE_BASE_IDX', 'mmGDS_VMID13_BASE', + 'mmGDS_VMID13_BASE_BASE_IDX', 'mmGDS_VMID13_SIZE', + 'mmGDS_VMID13_SIZE_BASE_IDX', 'mmGDS_VMID14_BASE', + 'mmGDS_VMID14_BASE_BASE_IDX', 'mmGDS_VMID14_SIZE', + 'mmGDS_VMID14_SIZE_BASE_IDX', 'mmGDS_VMID15_BASE', + 'mmGDS_VMID15_BASE_BASE_IDX', 'mmGDS_VMID15_SIZE', + 'mmGDS_VMID15_SIZE_BASE_IDX', 'mmGDS_VMID1_BASE', + 'mmGDS_VMID1_BASE_BASE_IDX', 'mmGDS_VMID1_SIZE', + 'mmGDS_VMID1_SIZE_BASE_IDX', 'mmGDS_VMID2_BASE', + 'mmGDS_VMID2_BASE_BASE_IDX', 'mmGDS_VMID2_SIZE', + 'mmGDS_VMID2_SIZE_BASE_IDX', 'mmGDS_VMID3_BASE', + 'mmGDS_VMID3_BASE_BASE_IDX', 'mmGDS_VMID3_SIZE', + 'mmGDS_VMID3_SIZE_BASE_IDX', 'mmGDS_VMID4_BASE', + 'mmGDS_VMID4_BASE_BASE_IDX', 'mmGDS_VMID4_SIZE', + 'mmGDS_VMID4_SIZE_BASE_IDX', 'mmGDS_VMID5_BASE', + 'mmGDS_VMID5_BASE_BASE_IDX', 'mmGDS_VMID5_SIZE', + 'mmGDS_VMID5_SIZE_BASE_IDX', 'mmGDS_VMID6_BASE', + 'mmGDS_VMID6_BASE_BASE_IDX', 'mmGDS_VMID6_SIZE', + 'mmGDS_VMID6_SIZE_BASE_IDX', 'mmGDS_VMID7_BASE', + 'mmGDS_VMID7_BASE_BASE_IDX', 'mmGDS_VMID7_SIZE', + 'mmGDS_VMID7_SIZE_BASE_IDX', 'mmGDS_VMID8_BASE', + 'mmGDS_VMID8_BASE_BASE_IDX', 'mmGDS_VMID8_SIZE', + 'mmGDS_VMID8_SIZE_BASE_IDX', 'mmGDS_VMID9_BASE', + 'mmGDS_VMID9_BASE_BASE_IDX', 'mmGDS_VMID9_SIZE', + 'mmGDS_VMID9_SIZE_BASE_IDX', 'mmGDS_VM_PROTECTION_FAULT', + 'mmGDS_VM_PROTECTION_FAULT_BASE_IDX', 'mmGDS_VS_CTXSW_CNT0', + 'mmGDS_VS_CTXSW_CNT0_BASE_IDX', 'mmGDS_VS_CTXSW_CNT1', + 'mmGDS_VS_CTXSW_CNT1_BASE_IDX', 'mmGDS_VS_CTXSW_CNT2', + 'mmGDS_VS_CTXSW_CNT2_BASE_IDX', 'mmGDS_VS_CTXSW_CNT3', + 'mmGDS_VS_CTXSW_CNT3_BASE_IDX', 'mmGDS_WD_GDS_CSB', + 'mmGDS_WD_GDS_CSB_BASE_IDX', 'mmGDS_WRITE_COMPLETE', + 'mmGDS_WRITE_COMPLETE_BASE_IDX', 'mmGDS_WR_ADDR', + 'mmGDS_WR_ADDR_BASE_IDX', 'mmGDS_WR_BURST_ADDR', + 'mmGDS_WR_BURST_ADDR_BASE_IDX', 'mmGDS_WR_BURST_DATA', + 'mmGDS_WR_BURST_DATA_BASE_IDX', 'mmGDS_WR_DATA', + 'mmGDS_WR_DATA_BASE_IDX', 'mmGE1_PERFCOUNTER0_HI', + 'mmGE1_PERFCOUNTER0_HI_BASE_IDX', 'mmGE1_PERFCOUNTER0_LO', + 'mmGE1_PERFCOUNTER0_LO_BASE_IDX', 'mmGE1_PERFCOUNTER0_SELECT', + 'mmGE1_PERFCOUNTER0_SELECT1', + 'mmGE1_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmGE1_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGE1_PERFCOUNTER1_HI', + 'mmGE1_PERFCOUNTER1_HI_BASE_IDX', 'mmGE1_PERFCOUNTER1_LO', + 'mmGE1_PERFCOUNTER1_LO_BASE_IDX', 'mmGE1_PERFCOUNTER1_SELECT', + 'mmGE1_PERFCOUNTER1_SELECT1', + 'mmGE1_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmGE1_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGE1_PERFCOUNTER2_HI', + 'mmGE1_PERFCOUNTER2_HI_BASE_IDX', 'mmGE1_PERFCOUNTER2_LO', + 'mmGE1_PERFCOUNTER2_LO_BASE_IDX', 'mmGE1_PERFCOUNTER2_SELECT', + 'mmGE1_PERFCOUNTER2_SELECT1', + 'mmGE1_PERFCOUNTER2_SELECT1_BASE_IDX', + 'mmGE1_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGE1_PERFCOUNTER3_HI', + 'mmGE1_PERFCOUNTER3_HI_BASE_IDX', 'mmGE1_PERFCOUNTER3_LO', + 'mmGE1_PERFCOUNTER3_LO_BASE_IDX', 'mmGE1_PERFCOUNTER3_SELECT', + 'mmGE1_PERFCOUNTER3_SELECT1', + 'mmGE1_PERFCOUNTER3_SELECT1_BASE_IDX', + 'mmGE1_PERFCOUNTER3_SELECT_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER0_HI', + 'mmGE2_DIST_PERFCOUNTER0_HI_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER0_LO', + 'mmGE2_DIST_PERFCOUNTER0_LO_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER0_SELECT', + 'mmGE2_DIST_PERFCOUNTER0_SELECT1', + 'mmGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER1_HI', + 'mmGE2_DIST_PERFCOUNTER1_HI_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER1_LO', + 'mmGE2_DIST_PERFCOUNTER1_LO_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER1_SELECT', + 'mmGE2_DIST_PERFCOUNTER1_SELECT1', + 'mmGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER2_HI', + 'mmGE2_DIST_PERFCOUNTER2_HI_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER2_LO', + 'mmGE2_DIST_PERFCOUNTER2_LO_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER2_SELECT', + 'mmGE2_DIST_PERFCOUNTER2_SELECT1', + 'mmGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER3_HI', + 'mmGE2_DIST_PERFCOUNTER3_HI_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER3_LO', + 'mmGE2_DIST_PERFCOUNTER3_LO_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER3_SELECT', + 'mmGE2_DIST_PERFCOUNTER3_SELECT1', + 'mmGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX', + 'mmGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER0_HI', 'mmGE2_SE_PERFCOUNTER0_HI_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER0_LO', 'mmGE2_SE_PERFCOUNTER0_LO_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER0_SELECT', 'mmGE2_SE_PERFCOUNTER0_SELECT1', + 'mmGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER1_HI', 'mmGE2_SE_PERFCOUNTER1_HI_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER1_LO', 'mmGE2_SE_PERFCOUNTER1_LO_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER1_SELECT', 'mmGE2_SE_PERFCOUNTER1_SELECT1', + 'mmGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER2_HI', 'mmGE2_SE_PERFCOUNTER2_HI_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER2_LO', 'mmGE2_SE_PERFCOUNTER2_LO_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER2_SELECT', 'mmGE2_SE_PERFCOUNTER2_SELECT1', + 'mmGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER3_HI', 'mmGE2_SE_PERFCOUNTER3_HI_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER3_LO', 'mmGE2_SE_PERFCOUNTER3_LO_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER3_SELECT', 'mmGE2_SE_PERFCOUNTER3_SELECT1', + 'mmGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX', + 'mmGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGE_CNTL', + 'mmGE_CNTL_BASE_IDX', 'mmGE_DMA_FIRST_INDEX', + 'mmGE_DMA_FIRST_INDEX_BASE_IDX', 'mmGE_INDX_OFFSET', + 'mmGE_INDX_OFFSET_BASE_IDX', 'mmGE_MAX_OUTPUT_PER_SUBGROUP', + 'mmGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX', 'mmGE_MAX_VTX_INDX', + 'mmGE_MAX_VTX_INDX_BASE_IDX', 'mmGE_MIN_VTX_INDX', + 'mmGE_MIN_VTX_INDX_BASE_IDX', 'mmGE_MULTI_PRIM_IB_RESET_EN', + 'mmGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX', 'mmGE_NGG_SUBGRP_CNTL', + 'mmGE_NGG_SUBGRP_CNTL_BASE_IDX', 'mmGE_PC_ALLOC', + 'mmGE_PC_ALLOC_BASE_IDX', 'mmGE_PC_CNTL', 'mmGE_PC_CNTL_BASE_IDX', + 'mmGE_PRIV_CONTROL', 'mmGE_PRIV_CONTROL_BASE_IDX', 'mmGE_STATUS', + 'mmGE_STATUS_BASE_IDX', 'mmGE_STEREO_CNTL', + 'mmGE_STEREO_CNTL_BASE_IDX', 'mmGE_USER_VGPR1', + 'mmGE_USER_VGPR1_BASE_IDX', 'mmGE_USER_VGPR2', + 'mmGE_USER_VGPR2_BASE_IDX', 'mmGE_USER_VGPR3', + 'mmGE_USER_VGPR3_BASE_IDX', 'mmGE_USER_VGPR_EN', + 'mmGE_USER_VGPR_EN_BASE_IDX', 'mmGFX_COPY_STATE', + 'mmGFX_COPY_STATE_BASE_IDX', 'mmGFX_PIPE_CONTROL', + 'mmGFX_PIPE_CONTROL_BASE_IDX', 'mmGFX_PIPE_PRIORITY', + 'mmGFX_PIPE_PRIORITY_BASE_IDX', 'mmGL1A_PERFCOUNTER0_HI', + 'mmGL1A_PERFCOUNTER0_HI_BASE_IDX', 'mmGL1A_PERFCOUNTER0_LO', + 'mmGL1A_PERFCOUNTER0_LO_BASE_IDX', 'mmGL1A_PERFCOUNTER0_SELECT', + 'mmGL1A_PERFCOUNTER0_SELECT1', + 'mmGL1A_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmGL1A_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGL1A_PERFCOUNTER1_HI', + 'mmGL1A_PERFCOUNTER1_HI_BASE_IDX', 'mmGL1A_PERFCOUNTER1_LO', + 'mmGL1A_PERFCOUNTER1_LO_BASE_IDX', 'mmGL1A_PERFCOUNTER1_SELECT', + 'mmGL1A_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGL1A_PERFCOUNTER2_HI', + 'mmGL1A_PERFCOUNTER2_HI_BASE_IDX', 'mmGL1A_PERFCOUNTER2_LO', + 'mmGL1A_PERFCOUNTER2_LO_BASE_IDX', 'mmGL1A_PERFCOUNTER2_SELECT', + 'mmGL1A_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGL1A_PERFCOUNTER3_HI', + 'mmGL1A_PERFCOUNTER3_HI_BASE_IDX', 'mmGL1A_PERFCOUNTER3_LO', + 'mmGL1A_PERFCOUNTER3_LO_BASE_IDX', 'mmGL1A_PERFCOUNTER3_SELECT', + 'mmGL1A_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGL1C_PERFCOUNTER0_HI', + 'mmGL1C_PERFCOUNTER0_HI_BASE_IDX', 'mmGL1C_PERFCOUNTER0_LO', + 'mmGL1C_PERFCOUNTER0_LO_BASE_IDX', 'mmGL1C_PERFCOUNTER0_SELECT', + 'mmGL1C_PERFCOUNTER0_SELECT1', + 'mmGL1C_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmGL1C_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGL1C_PERFCOUNTER1_HI', + 'mmGL1C_PERFCOUNTER1_HI_BASE_IDX', 'mmGL1C_PERFCOUNTER1_LO', + 'mmGL1C_PERFCOUNTER1_LO_BASE_IDX', 'mmGL1C_PERFCOUNTER1_SELECT', + 'mmGL1C_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGL1C_PERFCOUNTER2_HI', + 'mmGL1C_PERFCOUNTER2_HI_BASE_IDX', 'mmGL1C_PERFCOUNTER2_LO', + 'mmGL1C_PERFCOUNTER2_LO_BASE_IDX', 'mmGL1C_PERFCOUNTER2_SELECT', + 'mmGL1C_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGL1C_PERFCOUNTER3_HI', + 'mmGL1C_PERFCOUNTER3_HI_BASE_IDX', 'mmGL1C_PERFCOUNTER3_LO', + 'mmGL1C_PERFCOUNTER3_LO_BASE_IDX', 'mmGL1C_PERFCOUNTER3_SELECT', + 'mmGL1C_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGL1C_STATUS', + 'mmGL1C_STATUS_BASE_IDX', 'mmGL1C_UTCL0_CNTL2', + 'mmGL1C_UTCL0_CNTL2_BASE_IDX', 'mmGL1C_UTCL0_RETRY', + 'mmGL1C_UTCL0_RETRY_BASE_IDX', 'mmGL1C_UTCL0_STATUS', + 'mmGL1C_UTCL0_STATUS_BASE_IDX', 'mmGL1_ARB_STATUS', + 'mmGL1_ARB_STATUS_BASE_IDX', 'mmGL1_DRAM_BURST_MASK', + 'mmGL1_DRAM_BURST_MASK_BASE_IDX', 'mmGL1_PIPE_STEER', + 'mmGL1_PIPE_STEER_BASE_IDX', 'mmGL2A_ADDR_MATCH_CTRL', + 'mmGL2A_ADDR_MATCH_CTRL_BASE_IDX', 'mmGL2A_ADDR_MATCH_MASK', + 'mmGL2A_ADDR_MATCH_MASK_BASE_IDX', 'mmGL2A_ADDR_MATCH_SIZE', + 'mmGL2A_ADDR_MATCH_SIZE_BASE_IDX', 'mmGL2A_CGTT_SCLK_CTRL', + 'mmGL2A_CGTT_SCLK_CTRL_1', 'mmGL2A_CGTT_SCLK_CTRL_1_BASE_IDX', + 'mmGL2A_CGTT_SCLK_CTRL_BASE_IDX', 'mmGL2A_PERFCOUNTER0_HI', + 'mmGL2A_PERFCOUNTER0_HI_BASE_IDX', 'mmGL2A_PERFCOUNTER0_LO', + 'mmGL2A_PERFCOUNTER0_LO_BASE_IDX', 'mmGL2A_PERFCOUNTER0_SELECT', + 'mmGL2A_PERFCOUNTER0_SELECT1', + 'mmGL2A_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmGL2A_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGL2A_PERFCOUNTER1_HI', + 'mmGL2A_PERFCOUNTER1_HI_BASE_IDX', 'mmGL2A_PERFCOUNTER1_LO', + 'mmGL2A_PERFCOUNTER1_LO_BASE_IDX', 'mmGL2A_PERFCOUNTER1_SELECT', + 'mmGL2A_PERFCOUNTER1_SELECT1', + 'mmGL2A_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmGL2A_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGL2A_PERFCOUNTER2_HI', + 'mmGL2A_PERFCOUNTER2_HI_BASE_IDX', 'mmGL2A_PERFCOUNTER2_LO', + 'mmGL2A_PERFCOUNTER2_LO_BASE_IDX', 'mmGL2A_PERFCOUNTER2_SELECT', + 'mmGL2A_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGL2A_PERFCOUNTER3_HI', + 'mmGL2A_PERFCOUNTER3_HI_BASE_IDX', 'mmGL2A_PERFCOUNTER3_LO', + 'mmGL2A_PERFCOUNTER3_LO_BASE_IDX', 'mmGL2A_PERFCOUNTER3_SELECT', + 'mmGL2A_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGL2A_PRIORITY_CTRL', + 'mmGL2A_PRIORITY_CTRL_BASE_IDX', 'mmGL2C_ADDR_MATCH_MASK', + 'mmGL2C_ADDR_MATCH_MASK_BASE_IDX', 'mmGL2C_ADDR_MATCH_SIZE', + 'mmGL2C_ADDR_MATCH_SIZE_BASE_IDX', 'mmGL2C_CGTT_SCLK_CTRL', + 'mmGL2C_CGTT_SCLK_CTRL_BASE_IDX', 'mmGL2C_CM_CTRL0', + 'mmGL2C_CM_CTRL0_BASE_IDX', 'mmGL2C_CM_CTRL1', + 'mmGL2C_CM_CTRL1_BASE_IDX', 'mmGL2C_CM_STALL', + 'mmGL2C_CM_STALL_BASE_IDX', 'mmGL2C_CTRL', 'mmGL2C_CTRL2', + 'mmGL2C_CTRL2_BASE_IDX', 'mmGL2C_CTRL_BASE_IDX', + 'mmGL2C_LB_CTR_CTRL', 'mmGL2C_LB_CTR_CTRL_BASE_IDX', + 'mmGL2C_LB_CTR_SEL0', 'mmGL2C_LB_CTR_SEL0_BASE_IDX', + 'mmGL2C_LB_CTR_SEL1', 'mmGL2C_LB_CTR_SEL1_BASE_IDX', + 'mmGL2C_LB_DATA0', 'mmGL2C_LB_DATA0_BASE_IDX', 'mmGL2C_LB_DATA1', + 'mmGL2C_LB_DATA1_BASE_IDX', 'mmGL2C_LB_DATA2', + 'mmGL2C_LB_DATA2_BASE_IDX', 'mmGL2C_LB_DATA3', + 'mmGL2C_LB_DATA3_BASE_IDX', 'mmGL2C_MDC_PF_FLAG_CTRL', + 'mmGL2C_MDC_PF_FLAG_CTRL_BASE_IDX', 'mmGL2C_PERFCOUNTER0_HI', + 'mmGL2C_PERFCOUNTER0_HI_BASE_IDX', 'mmGL2C_PERFCOUNTER0_LO', + 'mmGL2C_PERFCOUNTER0_LO_BASE_IDX', 'mmGL2C_PERFCOUNTER0_SELECT', + 'mmGL2C_PERFCOUNTER0_SELECT1', + 'mmGL2C_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmGL2C_PERFCOUNTER0_SELECT_BASE_IDX', 'mmGL2C_PERFCOUNTER1_HI', + 'mmGL2C_PERFCOUNTER1_HI_BASE_IDX', 'mmGL2C_PERFCOUNTER1_LO', + 'mmGL2C_PERFCOUNTER1_LO_BASE_IDX', 'mmGL2C_PERFCOUNTER1_SELECT', + 'mmGL2C_PERFCOUNTER1_SELECT1', + 'mmGL2C_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmGL2C_PERFCOUNTER1_SELECT_BASE_IDX', 'mmGL2C_PERFCOUNTER2_HI', + 'mmGL2C_PERFCOUNTER2_HI_BASE_IDX', 'mmGL2C_PERFCOUNTER2_LO', + 'mmGL2C_PERFCOUNTER2_LO_BASE_IDX', 'mmGL2C_PERFCOUNTER2_SELECT', + 'mmGL2C_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGL2C_PERFCOUNTER3_HI', + 'mmGL2C_PERFCOUNTER3_HI_BASE_IDX', 'mmGL2C_PERFCOUNTER3_LO', + 'mmGL2C_PERFCOUNTER3_LO_BASE_IDX', 'mmGL2C_PERFCOUNTER3_SELECT', + 'mmGL2C_PERFCOUNTER3_SELECT_BASE_IDX', 'mmGL2C_SOFT_RESET', + 'mmGL2C_SOFT_RESET_BASE_IDX', 'mmGL2C_WBINVL2', + 'mmGL2C_WBINVL2_BASE_IDX', 'mmGL2_PIPE_STEER_0', + 'mmGL2_PIPE_STEER_0_BASE_IDX', 'mmGL2_PIPE_STEER_1', + 'mmGL2_PIPE_STEER_1_BASE_IDX', 'mmGRBM_CAM_DATA', + 'mmGRBM_CAM_DATA_BASE_IDX', 'mmGRBM_CAM_DATA_UPPER', + 'mmGRBM_CAM_DATA_UPPER_BASE_IDX', 'mmGRBM_CAM_INDEX', + 'mmGRBM_CAM_INDEX_BASE_IDX', 'mmGRBM_CGTT_CLK_CNTL', + 'mmGRBM_CGTT_CLK_CNTL_BASE_IDX', 'mmGRBM_CHIP_REVISION', + 'mmGRBM_CHIP_REVISION_BASE_IDX', 'mmGRBM_CNTL', + 'mmGRBM_CNTL_BASE_IDX', 'mmGRBM_DSM_BYPASS', + 'mmGRBM_DSM_BYPASS_BASE_IDX', 'mmGRBM_FENCE_RANGE0', + 'mmGRBM_FENCE_RANGE0_BASE_IDX', 'mmGRBM_FENCE_RANGE1', + 'mmGRBM_FENCE_RANGE1_BASE_IDX', 'mmGRBM_GFX_CLKEN_CNTL', + 'mmGRBM_GFX_CLKEN_CNTL_BASE_IDX', 'mmGRBM_GFX_CNTL', + 'mmGRBM_GFX_CNTL_BASE_IDX', 'mmGRBM_GFX_CNTL_SR_DATA', + 'mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX', 'mmGRBM_GFX_CNTL_SR_SELECT', + 'mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX', 'mmGRBM_GFX_INDEX', + 'mmGRBM_GFX_INDEX_BASE_IDX', 'mmGRBM_GFX_INDEX_SR_DATA', + 'mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX', 'mmGRBM_GFX_INDEX_SR_SELECT', + 'mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX', 'mmGRBM_HYP_CAM_DATA', + 'mmGRBM_HYP_CAM_DATA_BASE_IDX', 'mmGRBM_HYP_CAM_DATA_UPPER', + 'mmGRBM_HYP_CAM_DATA_UPPER_BASE_IDX', 'mmGRBM_HYP_CAM_INDEX', + 'mmGRBM_HYP_CAM_INDEX_BASE_IDX', 'mmGRBM_IH_CREDIT', + 'mmGRBM_IH_CREDIT_BASE_IDX', 'mmGRBM_INT_CNTL', + 'mmGRBM_INT_CNTL_BASE_IDX', 'mmGRBM_NOWHERE', + 'mmGRBM_NOWHERE_BASE_IDX', 'mmGRBM_PERFCOUNTER0_HI', + 'mmGRBM_PERFCOUNTER0_HI_BASE_IDX', 'mmGRBM_PERFCOUNTER0_LO', + 'mmGRBM_PERFCOUNTER0_LO_BASE_IDX', 'mmGRBM_PERFCOUNTER0_SELECT', + 'mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX', + 'mmGRBM_PERFCOUNTER0_SELECT_HI', + 'mmGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX', + 'mmGRBM_PERFCOUNTER1_HI', 'mmGRBM_PERFCOUNTER1_HI_BASE_IDX', + 'mmGRBM_PERFCOUNTER1_LO', 'mmGRBM_PERFCOUNTER1_LO_BASE_IDX', + 'mmGRBM_PERFCOUNTER1_SELECT', + 'mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX', + 'mmGRBM_PERFCOUNTER1_SELECT_HI', + 'mmGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX', 'mmGRBM_PWR_CNTL', + 'mmGRBM_PWR_CNTL2', 'mmGRBM_PWR_CNTL2_BASE_IDX', + 'mmGRBM_PWR_CNTL_BASE_IDX', 'mmGRBM_READ_ERROR', + 'mmGRBM_READ_ERROR2', 'mmGRBM_READ_ERROR2_BASE_IDX', + 'mmGRBM_READ_ERROR_BASE_IDX', 'mmGRBM_SCRATCH_REG0', + 'mmGRBM_SCRATCH_REG0_BASE_IDX', 'mmGRBM_SCRATCH_REG1', + 'mmGRBM_SCRATCH_REG1_BASE_IDX', 'mmGRBM_SCRATCH_REG2', + 'mmGRBM_SCRATCH_REG2_BASE_IDX', 'mmGRBM_SCRATCH_REG3', + 'mmGRBM_SCRATCH_REG3_BASE_IDX', 'mmGRBM_SCRATCH_REG4', + 'mmGRBM_SCRATCH_REG4_BASE_IDX', 'mmGRBM_SCRATCH_REG5', + 'mmGRBM_SCRATCH_REG5_BASE_IDX', 'mmGRBM_SCRATCH_REG6', + 'mmGRBM_SCRATCH_REG6_BASE_IDX', 'mmGRBM_SCRATCH_REG7', + 'mmGRBM_SCRATCH_REG7_BASE_IDX', 'mmGRBM_SE0_PERFCOUNTER_HI', + 'mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX', 'mmGRBM_SE0_PERFCOUNTER_LO', + 'mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX', + 'mmGRBM_SE0_PERFCOUNTER_SELECT', + 'mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX', + 'mmGRBM_SE1_PERFCOUNTER_HI', 'mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX', + 'mmGRBM_SE1_PERFCOUNTER_LO', 'mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX', + 'mmGRBM_SE1_PERFCOUNTER_SELECT', + 'mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX', + 'mmGRBM_SE2_PERFCOUNTER_HI', 'mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX', + 'mmGRBM_SE2_PERFCOUNTER_LO', 'mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX', + 'mmGRBM_SE2_PERFCOUNTER_SELECT', + 'mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX', + 'mmGRBM_SE3_PERFCOUNTER_HI', 'mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX', + 'mmGRBM_SE3_PERFCOUNTER_LO', 'mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX', + 'mmGRBM_SE3_PERFCOUNTER_SELECT', + 'mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX', 'mmGRBM_SEC_CNTL', + 'mmGRBM_SEC_CNTL_BASE_IDX', 'mmGRBM_SE_REMAP_CNTL', + 'mmGRBM_SE_REMAP_CNTL_BASE_IDX', 'mmGRBM_SKEW_CNTL', + 'mmGRBM_SKEW_CNTL_BASE_IDX', 'mmGRBM_SOFT_RESET', + 'mmGRBM_SOFT_RESET_BASE_IDX', 'mmGRBM_STATUS', 'mmGRBM_STATUS2', + 'mmGRBM_STATUS2_BASE_IDX', 'mmGRBM_STATUS3', + 'mmGRBM_STATUS3_BASE_IDX', 'mmGRBM_STATUS_BASE_IDX', + 'mmGRBM_STATUS_SE0', 'mmGRBM_STATUS_SE0_BASE_IDX', + 'mmGRBM_STATUS_SE1', 'mmGRBM_STATUS_SE1_BASE_IDX', + 'mmGRBM_STATUS_SE2', 'mmGRBM_STATUS_SE2_BASE_IDX', + 'mmGRBM_STATUS_SE3', 'mmGRBM_STATUS_SE3_BASE_IDX', + 'mmGRBM_TRAP_ADDR', 'mmGRBM_TRAP_ADDR_BASE_IDX', + 'mmGRBM_TRAP_ADDR_MSK', 'mmGRBM_TRAP_ADDR_MSK_BASE_IDX', + 'mmGRBM_TRAP_OP', 'mmGRBM_TRAP_OP_BASE_IDX', 'mmGRBM_TRAP_WD', + 'mmGRBM_TRAP_WD_BASE_IDX', 'mmGRBM_TRAP_WD_MSK', + 'mmGRBM_TRAP_WD_MSK_BASE_IDX', 'mmGRBM_UTCL2_INVAL_RANGE_END', + 'mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX', + 'mmGRBM_UTCL2_INVAL_RANGE_START', + 'mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX', + 'mmGRBM_WAIT_IDLE_CLOCKS', 'mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX', + 'mmGRBM_WRITE_ERROR', 'mmGRBM_WRITE_ERROR_BASE_IDX', + 'mmGRTAVFS_CLK_CNTL', 'mmGRTAVFS_CLK_CNTL_BASE_IDX', + 'mmGRTAVFS_GENERAL_0', 'mmGRTAVFS_GENERAL_0_BASE_IDX', + 'mmGRTAVFS_PSM_CNTL', 'mmGRTAVFS_PSM_CNTL_BASE_IDX', + 'mmGRTAVFS_RTAVFS_RD_DATA', 'mmGRTAVFS_RTAVFS_RD_DATA_BASE_IDX', + 'mmGRTAVFS_RTAVFS_REG_ADDR', 'mmGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', + 'mmGRTAVFS_RTAVFS_REG_CTRL', 'mmGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX', + 'mmGRTAVFS_RTAVFS_REG_STATUS', + 'mmGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX', + 'mmGRTAVFS_RTAVFS_WR_DATA', 'mmGRTAVFS_RTAVFS_WR_DATA_BASE_IDX', + 'mmGRTAVFS_SOFT_RESET', 'mmGRTAVFS_SOFT_RESET_BASE_IDX', + 'mmGRTAVFS_TARG_FREQ', 'mmGRTAVFS_TARG_FREQ_BASE_IDX', + 'mmGRTAVFS_TARG_VOLT', 'mmGRTAVFS_TARG_VOLT_BASE_IDX', + 'mmGUS_CGTT_CLK_CTRL', 'mmGUS_CGTT_CLK_CTRL_BASE_IDX', + 'mmGUS_DRAM_COMBINE_FLUSH', 'mmGUS_DRAM_COMBINE_FLUSH_BASE_IDX', + 'mmGUS_DRAM_COMBINE_RD_WR_EN', + 'mmGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX', 'mmGUS_DRAM_GROUP_BURST', + 'mmGUS_DRAM_GROUP_BURST_BASE_IDX', 'mmGUS_DRAM_PRI_AGE_COEFF', + 'mmGUS_DRAM_PRI_AGE_COEFF_BASE_IDX', 'mmGUS_DRAM_PRI_AGE_RATE', + 'mmGUS_DRAM_PRI_AGE_RATE_BASE_IDX', 'mmGUS_DRAM_PRI_FIXED', + 'mmGUS_DRAM_PRI_FIXED_BASE_IDX', 'mmGUS_DRAM_PRI_QUANT1_PRI1', + 'mmGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX', + 'mmGUS_DRAM_PRI_QUANT1_PRI2', + 'mmGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX', + 'mmGUS_DRAM_PRI_QUANT1_PRI3', + 'mmGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX', + 'mmGUS_DRAM_PRI_QUANT1_PRI4', + 'mmGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX', + 'mmGUS_DRAM_PRI_QUANT1_PRI5', + 'mmGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX', + 'mmGUS_DRAM_PRI_QUANT_PRI1', 'mmGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX', + 'mmGUS_DRAM_PRI_QUANT_PRI2', 'mmGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX', + 'mmGUS_DRAM_PRI_QUANT_PRI3', 'mmGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX', + 'mmGUS_DRAM_PRI_QUANT_PRI4', 'mmGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX', + 'mmGUS_DRAM_PRI_QUANT_PRI5', 'mmGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX', + 'mmGUS_DRAM_PRI_QUEUING', 'mmGUS_DRAM_PRI_QUEUING_BASE_IDX', + 'mmGUS_DRAM_PRI_URGENCY_COEFF', + 'mmGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX', + 'mmGUS_DRAM_PRI_URGENCY_MODE', + 'mmGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX', 'mmGUS_ERR_STATUS', + 'mmGUS_ERR_STATUS_BASE_IDX', 'mmGUS_IO_GROUP_BURST', + 'mmGUS_IO_GROUP_BURST_BASE_IDX', 'mmGUS_IO_RD_COMBINE_FLUSH', + 'mmGUS_IO_RD_COMBINE_FLUSH_BASE_IDX', 'mmGUS_IO_RD_PRI_AGE_COEFF', + 'mmGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX', 'mmGUS_IO_RD_PRI_AGE_RATE', + 'mmGUS_IO_RD_PRI_AGE_RATE_BASE_IDX', 'mmGUS_IO_RD_PRI_FIXED', + 'mmGUS_IO_RD_PRI_FIXED_BASE_IDX', 'mmGUS_IO_RD_PRI_QUANT1_PRI1', + 'mmGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX', + 'mmGUS_IO_RD_PRI_QUANT1_PRI2', + 'mmGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX', + 'mmGUS_IO_RD_PRI_QUANT1_PRI3', + 'mmGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX', + 'mmGUS_IO_RD_PRI_QUANT1_PRI4', + 'mmGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX', + 'mmGUS_IO_RD_PRI_QUANT_PRI1', + 'mmGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX', + 'mmGUS_IO_RD_PRI_QUANT_PRI2', + 'mmGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX', + 'mmGUS_IO_RD_PRI_QUANT_PRI3', + 'mmGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX', + 'mmGUS_IO_RD_PRI_QUANT_PRI4', + 'mmGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX', 'mmGUS_IO_RD_PRI_QUEUING', + 'mmGUS_IO_RD_PRI_QUEUING_BASE_IDX', + 'mmGUS_IO_RD_PRI_URGENCY_COEFF', + 'mmGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX', + 'mmGUS_IO_RD_PRI_URGENCY_MODE', + 'mmGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX', + 'mmGUS_IO_WR_COMBINE_FLUSH', 'mmGUS_IO_WR_COMBINE_FLUSH_BASE_IDX', + 'mmGUS_IO_WR_PRI_AGE_COEFF', 'mmGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX', + 'mmGUS_IO_WR_PRI_AGE_RATE', 'mmGUS_IO_WR_PRI_AGE_RATE_BASE_IDX', + 'mmGUS_IO_WR_PRI_FIXED', 'mmGUS_IO_WR_PRI_FIXED_BASE_IDX', + 'mmGUS_IO_WR_PRI_QUANT1_PRI1', + 'mmGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX', + 'mmGUS_IO_WR_PRI_QUANT1_PRI2', + 'mmGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX', + 'mmGUS_IO_WR_PRI_QUANT1_PRI3', + 'mmGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX', + 'mmGUS_IO_WR_PRI_QUANT1_PRI4', + 'mmGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX', + 'mmGUS_IO_WR_PRI_QUANT_PRI1', + 'mmGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX', + 'mmGUS_IO_WR_PRI_QUANT_PRI2', + 'mmGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX', + 'mmGUS_IO_WR_PRI_QUANT_PRI3', + 'mmGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX', + 'mmGUS_IO_WR_PRI_QUANT_PRI4', + 'mmGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX', 'mmGUS_IO_WR_PRI_QUEUING', + 'mmGUS_IO_WR_PRI_QUEUING_BASE_IDX', + 'mmGUS_IO_WR_PRI_URGENCY_COEFF', + 'mmGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX', + 'mmGUS_IO_WR_PRI_URGENCY_MODE', + 'mmGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX', 'mmGUS_L1_CH0_CMD_IN', + 'mmGUS_L1_CH0_CMD_IN_BASE_IDX', 'mmGUS_L1_CH0_CMD_OUT', + 'mmGUS_L1_CH0_CMD_OUT_BASE_IDX', 'mmGUS_L1_CH0_DATA_IN', + 'mmGUS_L1_CH0_DATA_IN_BASE_IDX', 'mmGUS_L1_CH0_DATA_OUT', + 'mmGUS_L1_CH0_DATA_OUT_BASE_IDX', 'mmGUS_L1_CH0_DATA_U_IN', + 'mmGUS_L1_CH0_DATA_U_IN_BASE_IDX', 'mmGUS_L1_CH0_DATA_U_OUT', + 'mmGUS_L1_CH0_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_CH1_CMD_IN', + 'mmGUS_L1_CH1_CMD_IN_BASE_IDX', 'mmGUS_L1_CH1_CMD_OUT', + 'mmGUS_L1_CH1_CMD_OUT_BASE_IDX', 'mmGUS_L1_CH1_DATA_IN', + 'mmGUS_L1_CH1_DATA_IN_BASE_IDX', 'mmGUS_L1_CH1_DATA_OUT', + 'mmGUS_L1_CH1_DATA_OUT_BASE_IDX', 'mmGUS_L1_CH1_DATA_U_IN', + 'mmGUS_L1_CH1_DATA_U_IN_BASE_IDX', 'mmGUS_L1_CH1_DATA_U_OUT', + 'mmGUS_L1_CH1_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_SA0_CMD_IN', + 'mmGUS_L1_SA0_CMD_IN_BASE_IDX', 'mmGUS_L1_SA0_CMD_OUT', + 'mmGUS_L1_SA0_CMD_OUT_BASE_IDX', 'mmGUS_L1_SA0_DATA_IN', + 'mmGUS_L1_SA0_DATA_IN_BASE_IDX', 'mmGUS_L1_SA0_DATA_OUT', + 'mmGUS_L1_SA0_DATA_OUT_BASE_IDX', 'mmGUS_L1_SA0_DATA_U_IN', + 'mmGUS_L1_SA0_DATA_U_IN_BASE_IDX', 'mmGUS_L1_SA0_DATA_U_OUT', + 'mmGUS_L1_SA0_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_SA1_CMD_IN', + 'mmGUS_L1_SA1_CMD_IN_BASE_IDX', 'mmGUS_L1_SA1_CMD_OUT', + 'mmGUS_L1_SA1_CMD_OUT_BASE_IDX', 'mmGUS_L1_SA1_DATA_IN', + 'mmGUS_L1_SA1_DATA_IN_BASE_IDX', 'mmGUS_L1_SA1_DATA_OUT', + 'mmGUS_L1_SA1_DATA_OUT_BASE_IDX', 'mmGUS_L1_SA1_DATA_U_IN', + 'mmGUS_L1_SA1_DATA_U_IN_BASE_IDX', 'mmGUS_L1_SA1_DATA_U_OUT', + 'mmGUS_L1_SA1_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_SA2_CMD_IN', + 'mmGUS_L1_SA2_CMD_IN_BASE_IDX', 'mmGUS_L1_SA2_CMD_OUT', + 'mmGUS_L1_SA2_CMD_OUT_BASE_IDX', 'mmGUS_L1_SA2_DATA_IN', + 'mmGUS_L1_SA2_DATA_IN_BASE_IDX', 'mmGUS_L1_SA2_DATA_OUT', + 'mmGUS_L1_SA2_DATA_OUT_BASE_IDX', 'mmGUS_L1_SA2_DATA_U_IN', + 'mmGUS_L1_SA2_DATA_U_IN_BASE_IDX', 'mmGUS_L1_SA2_DATA_U_OUT', + 'mmGUS_L1_SA2_DATA_U_OUT_BASE_IDX', 'mmGUS_L1_SA3_CMD_IN', + 'mmGUS_L1_SA3_CMD_IN_BASE_IDX', 'mmGUS_L1_SA3_CMD_OUT', + 'mmGUS_L1_SA3_CMD_OUT_BASE_IDX', 'mmGUS_L1_SA3_DATA_IN', + 'mmGUS_L1_SA3_DATA_IN_BASE_IDX', 'mmGUS_L1_SA3_DATA_OUT', + 'mmGUS_L1_SA3_DATA_OUT_BASE_IDX', 'mmGUS_L1_SA3_DATA_U_IN', + 'mmGUS_L1_SA3_DATA_U_IN_BASE_IDX', 'mmGUS_L1_SA3_DATA_U_OUT', + 'mmGUS_L1_SA3_DATA_U_OUT_BASE_IDX', 'mmGUS_LATENCY_SAMPLING', + 'mmGUS_LATENCY_SAMPLING_BASE_IDX', 'mmGUS_MISC', 'mmGUS_MISC2', + 'mmGUS_MISC2_BASE_IDX', 'mmGUS_MISC3', 'mmGUS_MISC3_BASE_IDX', + 'mmGUS_MISC_BASE_IDX', 'mmGUS_PERFCOUNTER0_CFG', + 'mmGUS_PERFCOUNTER0_CFG_BASE_IDX', 'mmGUS_PERFCOUNTER1_CFG', + 'mmGUS_PERFCOUNTER1_CFG_BASE_IDX', 'mmGUS_PERFCOUNTER2_HI', + 'mmGUS_PERFCOUNTER2_HI_BASE_IDX', 'mmGUS_PERFCOUNTER2_LO', + 'mmGUS_PERFCOUNTER2_LO_BASE_IDX', 'mmGUS_PERFCOUNTER2_MODE', + 'mmGUS_PERFCOUNTER2_MODE_BASE_IDX', 'mmGUS_PERFCOUNTER2_SELECT', + 'mmGUS_PERFCOUNTER2_SELECT1', + 'mmGUS_PERFCOUNTER2_SELECT1_BASE_IDX', + 'mmGUS_PERFCOUNTER2_SELECT_BASE_IDX', 'mmGUS_PERFCOUNTER_HI', + 'mmGUS_PERFCOUNTER_HI_BASE_IDX', 'mmGUS_PERFCOUNTER_LO', + 'mmGUS_PERFCOUNTER_LO_BASE_IDX', 'mmGUS_PERFCOUNTER_RSLT_CNTL', + 'mmGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX', 'mmGUS_SDP_ARB_FINAL', + 'mmGUS_SDP_ARB_FINAL_BASE_IDX', 'mmGUS_SDP_CREDITS', + 'mmGUS_SDP_CREDITS_BASE_IDX', 'mmGUS_SDP_ENABLE', + 'mmGUS_SDP_ENABLE_BASE_IDX', 'mmGUS_SDP_QOS_VC_PRIORITY', + 'mmGUS_SDP_QOS_VC_PRIORITY_BASE_IDX', 'mmGUS_SDP_REQ_CNTL', + 'mmGUS_SDP_REQ_CNTL_BASE_IDX', 'mmGUS_SDP_TAG_RESERVE0', + 'mmGUS_SDP_TAG_RESERVE0_BASE_IDX', 'mmGUS_SDP_TAG_RESERVE1', + 'mmGUS_SDP_TAG_RESERVE1_BASE_IDX', 'mmGUS_SDP_VCC_RESERVE0', + 'mmGUS_SDP_VCC_RESERVE0_BASE_IDX', 'mmGUS_SDP_VCC_RESERVE1', + 'mmGUS_SDP_VCC_RESERVE1_BASE_IDX', 'mmGUS_SDP_VCD_RESERVE0', + 'mmGUS_SDP_VCD_RESERVE0_BASE_IDX', 'mmGUS_SDP_VCD_RESERVE1', + 'mmGUS_SDP_VCD_RESERVE1_BASE_IDX', 'mmGUS_WRRSP_FIFO_CNTL', + 'mmGUS_WRRSP_FIFO_CNTL_BASE_IDX', 'mmIA_ENHANCE', + 'mmIA_ENHANCE_BASE_IDX', 'mmIA_MULTI_VGT_PARAM', + 'mmIA_MULTI_VGT_PARAM_BASE_IDX', 'mmIA_MULTI_VGT_PARAM_PIPED', + 'mmIA_MULTI_VGT_PARAM_PIPED_BASE_IDX', 'mmIA_UTCL1_CNTL', + 'mmIA_UTCL1_CNTL_BASE_IDX', 'mmIA_UTCL1_STATUS', + 'mmIA_UTCL1_STATUS_2', 'mmIA_UTCL1_STATUS_2_BASE_IDX', + 'mmIA_UTCL1_STATUS_BASE_IDX', 'mmLDS_CONFIG', + 'mmLDS_CONFIG_BASE_IDX', 'mmPA_CL_CLIP_CNTL', + 'mmPA_CL_CLIP_CNTL_BASE_IDX', 'mmPA_CL_CNTL_STATUS', + 'mmPA_CL_CNTL_STATUS_BASE_IDX', 'mmPA_CL_ENHANCE', + 'mmPA_CL_ENHANCE_BASE_IDX', 'mmPA_CL_GB_HORZ_CLIP_ADJ', + 'mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX', 'mmPA_CL_GB_HORZ_DISC_ADJ', + 'mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX', 'mmPA_CL_GB_VERT_CLIP_ADJ', + 'mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX', 'mmPA_CL_GB_VERT_DISC_ADJ', + 'mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX', 'mmPA_CL_NANINF_CNTL', + 'mmPA_CL_NANINF_CNTL_BASE_IDX', 'mmPA_CL_NGG_CNTL', + 'mmPA_CL_NGG_CNTL_BASE_IDX', 'mmPA_CL_POINT_CULL_RAD', + 'mmPA_CL_POINT_CULL_RAD_BASE_IDX', 'mmPA_CL_POINT_SIZE', + 'mmPA_CL_POINT_SIZE_BASE_IDX', 'mmPA_CL_POINT_X_RAD', + 'mmPA_CL_POINT_X_RAD_BASE_IDX', 'mmPA_CL_POINT_Y_RAD', + 'mmPA_CL_POINT_Y_RAD_BASE_IDX', 'mmPA_CL_PROG_NEAR_CLIP_Z', + 'mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX', 'mmPA_CL_UCP_0_W', + 'mmPA_CL_UCP_0_W_BASE_IDX', 'mmPA_CL_UCP_0_X', + 'mmPA_CL_UCP_0_X_BASE_IDX', 'mmPA_CL_UCP_0_Y', + 'mmPA_CL_UCP_0_Y_BASE_IDX', 'mmPA_CL_UCP_0_Z', + 'mmPA_CL_UCP_0_Z_BASE_IDX', 'mmPA_CL_UCP_1_W', + 'mmPA_CL_UCP_1_W_BASE_IDX', 'mmPA_CL_UCP_1_X', + 'mmPA_CL_UCP_1_X_BASE_IDX', 'mmPA_CL_UCP_1_Y', + 'mmPA_CL_UCP_1_Y_BASE_IDX', 'mmPA_CL_UCP_1_Z', + 'mmPA_CL_UCP_1_Z_BASE_IDX', 'mmPA_CL_UCP_2_W', + 'mmPA_CL_UCP_2_W_BASE_IDX', 'mmPA_CL_UCP_2_X', + 'mmPA_CL_UCP_2_X_BASE_IDX', 'mmPA_CL_UCP_2_Y', + 'mmPA_CL_UCP_2_Y_BASE_IDX', 'mmPA_CL_UCP_2_Z', + 'mmPA_CL_UCP_2_Z_BASE_IDX', 'mmPA_CL_UCP_3_W', + 'mmPA_CL_UCP_3_W_BASE_IDX', 'mmPA_CL_UCP_3_X', + 'mmPA_CL_UCP_3_X_BASE_IDX', 'mmPA_CL_UCP_3_Y', + 'mmPA_CL_UCP_3_Y_BASE_IDX', 'mmPA_CL_UCP_3_Z', + 'mmPA_CL_UCP_3_Z_BASE_IDX', 'mmPA_CL_UCP_4_W', + 'mmPA_CL_UCP_4_W_BASE_IDX', 'mmPA_CL_UCP_4_X', + 'mmPA_CL_UCP_4_X_BASE_IDX', 'mmPA_CL_UCP_4_Y', + 'mmPA_CL_UCP_4_Y_BASE_IDX', 'mmPA_CL_UCP_4_Z', + 'mmPA_CL_UCP_4_Z_BASE_IDX', 'mmPA_CL_UCP_5_W', + 'mmPA_CL_UCP_5_W_BASE_IDX', 'mmPA_CL_UCP_5_X', + 'mmPA_CL_UCP_5_X_BASE_IDX', 'mmPA_CL_UCP_5_Y', + 'mmPA_CL_UCP_5_Y_BASE_IDX', 'mmPA_CL_UCP_5_Z', + 'mmPA_CL_UCP_5_Z_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET', + 'mmPA_CL_VPORT_XOFFSET_1', 'mmPA_CL_VPORT_XOFFSET_10', + 'mmPA_CL_VPORT_XOFFSET_10_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_11', + 'mmPA_CL_VPORT_XOFFSET_11_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_12', + 'mmPA_CL_VPORT_XOFFSET_12_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_13', + 'mmPA_CL_VPORT_XOFFSET_13_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_14', + 'mmPA_CL_VPORT_XOFFSET_14_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_15', + 'mmPA_CL_VPORT_XOFFSET_15_BASE_IDX', + 'mmPA_CL_VPORT_XOFFSET_1_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_2', + 'mmPA_CL_VPORT_XOFFSET_2_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_3', + 'mmPA_CL_VPORT_XOFFSET_3_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_4', + 'mmPA_CL_VPORT_XOFFSET_4_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_5', + 'mmPA_CL_VPORT_XOFFSET_5_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_6', + 'mmPA_CL_VPORT_XOFFSET_6_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_7', + 'mmPA_CL_VPORT_XOFFSET_7_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_8', + 'mmPA_CL_VPORT_XOFFSET_8_BASE_IDX', 'mmPA_CL_VPORT_XOFFSET_9', + 'mmPA_CL_VPORT_XOFFSET_9_BASE_IDX', + 'mmPA_CL_VPORT_XOFFSET_BASE_IDX', 'mmPA_CL_VPORT_XSCALE', + 'mmPA_CL_VPORT_XSCALE_1', 'mmPA_CL_VPORT_XSCALE_10', + 'mmPA_CL_VPORT_XSCALE_10_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_11', + 'mmPA_CL_VPORT_XSCALE_11_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_12', + 'mmPA_CL_VPORT_XSCALE_12_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_13', + 'mmPA_CL_VPORT_XSCALE_13_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_14', + 'mmPA_CL_VPORT_XSCALE_14_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_15', + 'mmPA_CL_VPORT_XSCALE_15_BASE_IDX', + 'mmPA_CL_VPORT_XSCALE_1_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_2', + 'mmPA_CL_VPORT_XSCALE_2_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_3', + 'mmPA_CL_VPORT_XSCALE_3_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_4', + 'mmPA_CL_VPORT_XSCALE_4_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_5', + 'mmPA_CL_VPORT_XSCALE_5_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_6', + 'mmPA_CL_VPORT_XSCALE_6_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_7', + 'mmPA_CL_VPORT_XSCALE_7_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_8', + 'mmPA_CL_VPORT_XSCALE_8_BASE_IDX', 'mmPA_CL_VPORT_XSCALE_9', + 'mmPA_CL_VPORT_XSCALE_9_BASE_IDX', + 'mmPA_CL_VPORT_XSCALE_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET', + 'mmPA_CL_VPORT_YOFFSET_1', 'mmPA_CL_VPORT_YOFFSET_10', + 'mmPA_CL_VPORT_YOFFSET_10_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_11', + 'mmPA_CL_VPORT_YOFFSET_11_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_12', + 'mmPA_CL_VPORT_YOFFSET_12_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_13', + 'mmPA_CL_VPORT_YOFFSET_13_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_14', + 'mmPA_CL_VPORT_YOFFSET_14_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_15', + 'mmPA_CL_VPORT_YOFFSET_15_BASE_IDX', + 'mmPA_CL_VPORT_YOFFSET_1_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_2', + 'mmPA_CL_VPORT_YOFFSET_2_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_3', + 'mmPA_CL_VPORT_YOFFSET_3_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_4', + 'mmPA_CL_VPORT_YOFFSET_4_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_5', + 'mmPA_CL_VPORT_YOFFSET_5_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_6', + 'mmPA_CL_VPORT_YOFFSET_6_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_7', + 'mmPA_CL_VPORT_YOFFSET_7_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_8', + 'mmPA_CL_VPORT_YOFFSET_8_BASE_IDX', 'mmPA_CL_VPORT_YOFFSET_9', + 'mmPA_CL_VPORT_YOFFSET_9_BASE_IDX', + 'mmPA_CL_VPORT_YOFFSET_BASE_IDX', 'mmPA_CL_VPORT_YSCALE', + 'mmPA_CL_VPORT_YSCALE_1', 'mmPA_CL_VPORT_YSCALE_10', + 'mmPA_CL_VPORT_YSCALE_10_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_11', + 'mmPA_CL_VPORT_YSCALE_11_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_12', + 'mmPA_CL_VPORT_YSCALE_12_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_13', + 'mmPA_CL_VPORT_YSCALE_13_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_14', + 'mmPA_CL_VPORT_YSCALE_14_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_15', + 'mmPA_CL_VPORT_YSCALE_15_BASE_IDX', + 'mmPA_CL_VPORT_YSCALE_1_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_2', + 'mmPA_CL_VPORT_YSCALE_2_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_3', + 'mmPA_CL_VPORT_YSCALE_3_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_4', + 'mmPA_CL_VPORT_YSCALE_4_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_5', + 'mmPA_CL_VPORT_YSCALE_5_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_6', + 'mmPA_CL_VPORT_YSCALE_6_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_7', + 'mmPA_CL_VPORT_YSCALE_7_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_8', + 'mmPA_CL_VPORT_YSCALE_8_BASE_IDX', 'mmPA_CL_VPORT_YSCALE_9', + 'mmPA_CL_VPORT_YSCALE_9_BASE_IDX', + 'mmPA_CL_VPORT_YSCALE_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET', + 'mmPA_CL_VPORT_ZOFFSET_1', 'mmPA_CL_VPORT_ZOFFSET_10', + 'mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_11', + 'mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_12', + 'mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_13', + 'mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_14', + 'mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_15', + 'mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX', + 'mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_2', + 'mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_3', + 'mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_4', + 'mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_5', + 'mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_6', + 'mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_7', + 'mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_8', + 'mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX', 'mmPA_CL_VPORT_ZOFFSET_9', + 'mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX', + 'mmPA_CL_VPORT_ZOFFSET_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE', + 'mmPA_CL_VPORT_ZSCALE_1', 'mmPA_CL_VPORT_ZSCALE_10', + 'mmPA_CL_VPORT_ZSCALE_10_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_11', + 'mmPA_CL_VPORT_ZSCALE_11_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_12', + 'mmPA_CL_VPORT_ZSCALE_12_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_13', + 'mmPA_CL_VPORT_ZSCALE_13_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_14', + 'mmPA_CL_VPORT_ZSCALE_14_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_15', + 'mmPA_CL_VPORT_ZSCALE_15_BASE_IDX', + 'mmPA_CL_VPORT_ZSCALE_1_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_2', + 'mmPA_CL_VPORT_ZSCALE_2_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_3', + 'mmPA_CL_VPORT_ZSCALE_3_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_4', + 'mmPA_CL_VPORT_ZSCALE_4_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_5', + 'mmPA_CL_VPORT_ZSCALE_5_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_6', + 'mmPA_CL_VPORT_ZSCALE_6_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_7', + 'mmPA_CL_VPORT_ZSCALE_7_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_8', + 'mmPA_CL_VPORT_ZSCALE_8_BASE_IDX', 'mmPA_CL_VPORT_ZSCALE_9', + 'mmPA_CL_VPORT_ZSCALE_9_BASE_IDX', + 'mmPA_CL_VPORT_ZSCALE_BASE_IDX', 'mmPA_CL_VRS_CNTL', + 'mmPA_CL_VRS_CNTL_BASE_IDX', 'mmPA_CL_VS_OUT_CNTL', + 'mmPA_CL_VS_OUT_CNTL_BASE_IDX', 'mmPA_CL_VTE_CNTL', + 'mmPA_CL_VTE_CNTL_BASE_IDX', 'mmPA_PH_ENHANCE', + 'mmPA_PH_ENHANCE_BASE_IDX', 'mmPA_PH_INTERFACE_FIFO_SIZE', + 'mmPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX', 'mmPA_PH_PERFCOUNTER0_HI', + 'mmPA_PH_PERFCOUNTER0_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER0_LO', + 'mmPA_PH_PERFCOUNTER0_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER0_SELECT', + 'mmPA_PH_PERFCOUNTER0_SELECT1', + 'mmPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmPA_PH_PERFCOUNTER0_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER1_HI', + 'mmPA_PH_PERFCOUNTER1_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER1_LO', + 'mmPA_PH_PERFCOUNTER1_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER1_SELECT', + 'mmPA_PH_PERFCOUNTER1_SELECT1', + 'mmPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmPA_PH_PERFCOUNTER1_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER2_HI', + 'mmPA_PH_PERFCOUNTER2_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER2_LO', + 'mmPA_PH_PERFCOUNTER2_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER2_SELECT', + 'mmPA_PH_PERFCOUNTER2_SELECT1', + 'mmPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX', + 'mmPA_PH_PERFCOUNTER2_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER3_HI', + 'mmPA_PH_PERFCOUNTER3_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER3_LO', + 'mmPA_PH_PERFCOUNTER3_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER3_SELECT', + 'mmPA_PH_PERFCOUNTER3_SELECT1', + 'mmPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX', + 'mmPA_PH_PERFCOUNTER3_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER4_HI', + 'mmPA_PH_PERFCOUNTER4_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER4_LO', + 'mmPA_PH_PERFCOUNTER4_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER4_SELECT', + 'mmPA_PH_PERFCOUNTER4_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER5_HI', + 'mmPA_PH_PERFCOUNTER5_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER5_LO', + 'mmPA_PH_PERFCOUNTER5_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER5_SELECT', + 'mmPA_PH_PERFCOUNTER5_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER6_HI', + 'mmPA_PH_PERFCOUNTER6_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER6_LO', + 'mmPA_PH_PERFCOUNTER6_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER6_SELECT', + 'mmPA_PH_PERFCOUNTER6_SELECT_BASE_IDX', 'mmPA_PH_PERFCOUNTER7_HI', + 'mmPA_PH_PERFCOUNTER7_HI_BASE_IDX', 'mmPA_PH_PERFCOUNTER7_LO', + 'mmPA_PH_PERFCOUNTER7_LO_BASE_IDX', 'mmPA_PH_PERFCOUNTER7_SELECT', + 'mmPA_PH_PERFCOUNTER7_SELECT_BASE_IDX', 'mmPA_SC_AA_CONFIG', + 'mmPA_SC_AA_CONFIG_BASE_IDX', 'mmPA_SC_AA_MASK_X0Y0_X1Y0', + 'mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX', 'mmPA_SC_AA_MASK_X0Y1_X1Y1', + 'mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3', + 'mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX', + 'mmPA_SC_BC_WAVE_BREAK', 'mmPA_SC_BC_WAVE_BREAK_BASE_IDX', + 'mmPA_SC_BINNER_CNTL_0', 'mmPA_SC_BINNER_CNTL_0_BASE_IDX', + 'mmPA_SC_BINNER_CNTL_1', 'mmPA_SC_BINNER_CNTL_1_BASE_IDX', + 'mmPA_SC_BINNER_CNTL_OVERRIDE', + 'mmPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX', + 'mmPA_SC_BINNER_EVENT_CNTL_0', + 'mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX', + 'mmPA_SC_BINNER_EVENT_CNTL_1', + 'mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX', + 'mmPA_SC_BINNER_EVENT_CNTL_2', + 'mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX', + 'mmPA_SC_BINNER_EVENT_CNTL_3', + 'mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX', + 'mmPA_SC_BINNER_PERF_CNTL_0', + 'mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX', + 'mmPA_SC_BINNER_PERF_CNTL_1', + 'mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX', + 'mmPA_SC_BINNER_PERF_CNTL_2', + 'mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX', + 'mmPA_SC_BINNER_PERF_CNTL_3', + 'mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX', + 'mmPA_SC_BINNER_TIMEOUT_COUNTER', + 'mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX', + 'mmPA_SC_CENTROID_PRIORITY_0', + 'mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX', + 'mmPA_SC_CENTROID_PRIORITY_1', + 'mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX', 'mmPA_SC_CLIPRECT_0_BR', + 'mmPA_SC_CLIPRECT_0_BR_BASE_IDX', 'mmPA_SC_CLIPRECT_0_TL', + 'mmPA_SC_CLIPRECT_0_TL_BASE_IDX', 'mmPA_SC_CLIPRECT_1_BR', + 'mmPA_SC_CLIPRECT_1_BR_BASE_IDX', 'mmPA_SC_CLIPRECT_1_TL', + 'mmPA_SC_CLIPRECT_1_TL_BASE_IDX', 'mmPA_SC_CLIPRECT_2_BR', + 'mmPA_SC_CLIPRECT_2_BR_BASE_IDX', 'mmPA_SC_CLIPRECT_2_TL', + 'mmPA_SC_CLIPRECT_2_TL_BASE_IDX', 'mmPA_SC_CLIPRECT_3_BR', + 'mmPA_SC_CLIPRECT_3_BR_BASE_IDX', 'mmPA_SC_CLIPRECT_3_TL', + 'mmPA_SC_CLIPRECT_3_TL_BASE_IDX', 'mmPA_SC_CLIPRECT_RULE', + 'mmPA_SC_CLIPRECT_RULE_BASE_IDX', + 'mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL', + 'mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX', + 'mmPA_SC_DSM_CNTL', 'mmPA_SC_DSM_CNTL_BASE_IDX', + 'mmPA_SC_EDGERULE', 'mmPA_SC_EDGERULE_BASE_IDX', + 'mmPA_SC_ENHANCE', 'mmPA_SC_ENHANCE_1', + 'mmPA_SC_ENHANCE_1_BASE_IDX', 'mmPA_SC_ENHANCE_2', + 'mmPA_SC_ENHANCE_2_BASE_IDX', 'mmPA_SC_ENHANCE_3', + 'mmPA_SC_ENHANCE_3_BASE_IDX', 'mmPA_SC_ENHANCE_BASE_IDX', + 'mmPA_SC_ENHANCE_INTERNAL', 'mmPA_SC_ENHANCE_INTERNAL_BASE_IDX', + 'mmPA_SC_FIFO_DEPTH_CNTL', 'mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX', + 'mmPA_SC_FIFO_SIZE', 'mmPA_SC_FIFO_SIZE_BASE_IDX', + 'mmPA_SC_FORCE_EOV_MAX_CNTS', + 'mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX', + 'mmPA_SC_GENERIC_SCISSOR_BR', + 'mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX', + 'mmPA_SC_GENERIC_SCISSOR_TL', + 'mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX', + 'mmPA_SC_HP3D_TRAP_SCREEN_COUNT', + 'mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX', + 'mmPA_SC_HP3D_TRAP_SCREEN_H', 'mmPA_SC_HP3D_TRAP_SCREEN_HV_EN', + 'mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX', + 'mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK', + 'mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX', + 'mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX', + 'mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE', + 'mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX', + 'mmPA_SC_HP3D_TRAP_SCREEN_V', + 'mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX', 'mmPA_SC_IF_FIFO_SIZE', + 'mmPA_SC_IF_FIFO_SIZE_BASE_IDX', 'mmPA_SC_LINE_CNTL', + 'mmPA_SC_LINE_CNTL_BASE_IDX', 'mmPA_SC_LINE_STIPPLE', + 'mmPA_SC_LINE_STIPPLE_BASE_IDX', 'mmPA_SC_LINE_STIPPLE_STATE', + 'mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX', 'mmPA_SC_MODE_CNTL_0', + 'mmPA_SC_MODE_CNTL_0_BASE_IDX', 'mmPA_SC_MODE_CNTL_1', + 'mmPA_SC_MODE_CNTL_1_BASE_IDX', 'mmPA_SC_NGG_MODE_CNTL', + 'mmPA_SC_NGG_MODE_CNTL_BASE_IDX', 'mmPA_SC_P3D_TRAP_SCREEN_COUNT', + 'mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX', + 'mmPA_SC_P3D_TRAP_SCREEN_H', 'mmPA_SC_P3D_TRAP_SCREEN_HV_EN', + 'mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX', + 'mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK', + 'mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX', + 'mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX', + 'mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE', + 'mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX', + 'mmPA_SC_P3D_TRAP_SCREEN_V', 'mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX', + 'mmPA_SC_PBB_OVERRIDE_FLAG', 'mmPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX', + 'mmPA_SC_PERFCOUNTER0_HI', 'mmPA_SC_PERFCOUNTER0_HI_BASE_IDX', + 'mmPA_SC_PERFCOUNTER0_LO', 'mmPA_SC_PERFCOUNTER0_LO_BASE_IDX', + 'mmPA_SC_PERFCOUNTER0_SELECT', 'mmPA_SC_PERFCOUNTER0_SELECT1', + 'mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER1_HI', + 'mmPA_SC_PERFCOUNTER1_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER1_LO', + 'mmPA_SC_PERFCOUNTER1_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER1_SELECT', + 'mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER2_HI', + 'mmPA_SC_PERFCOUNTER2_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER2_LO', + 'mmPA_SC_PERFCOUNTER2_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER2_SELECT', + 'mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER3_HI', + 'mmPA_SC_PERFCOUNTER3_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER3_LO', + 'mmPA_SC_PERFCOUNTER3_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER3_SELECT', + 'mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER4_HI', + 'mmPA_SC_PERFCOUNTER4_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER4_LO', + 'mmPA_SC_PERFCOUNTER4_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER4_SELECT', + 'mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER5_HI', + 'mmPA_SC_PERFCOUNTER5_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER5_LO', + 'mmPA_SC_PERFCOUNTER5_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER5_SELECT', + 'mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER6_HI', + 'mmPA_SC_PERFCOUNTER6_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER6_LO', + 'mmPA_SC_PERFCOUNTER6_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER6_SELECT', + 'mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX', 'mmPA_SC_PERFCOUNTER7_HI', + 'mmPA_SC_PERFCOUNTER7_HI_BASE_IDX', 'mmPA_SC_PERFCOUNTER7_LO', + 'mmPA_SC_PERFCOUNTER7_LO_BASE_IDX', 'mmPA_SC_PERFCOUNTER7_SELECT', + 'mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX', + 'mmPA_SC_PKR_WAVE_TABLE_CNTL', + 'mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX', 'mmPA_SC_RASTER_CONFIG', + 'mmPA_SC_RASTER_CONFIG_1', 'mmPA_SC_RASTER_CONFIG_1_BASE_IDX', + 'mmPA_SC_RASTER_CONFIG_BASE_IDX', 'mmPA_SC_SCREEN_EXTENT_CONTROL', + 'mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX', + 'mmPA_SC_SCREEN_EXTENT_MAX_0', + 'mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX', + 'mmPA_SC_SCREEN_EXTENT_MAX_1', + 'mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX', + 'mmPA_SC_SCREEN_EXTENT_MIN_0', + 'mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX', + 'mmPA_SC_SCREEN_EXTENT_MIN_1', + 'mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX', + 'mmPA_SC_SCREEN_SCISSOR_BR', 'mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX', + 'mmPA_SC_SCREEN_SCISSOR_TL', 'mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX', + 'mmPA_SC_SHADER_CONTROL', 'mmPA_SC_SHADER_CONTROL_BASE_IDX', + 'mmPA_SC_TILE_STEERING_CREST_OVERRIDE', + 'mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX', + 'mmPA_SC_TILE_STEERING_OVERRIDE', + 'mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX', + 'mmPA_SC_TRAP_SCREEN_COUNT', 'mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX', + 'mmPA_SC_TRAP_SCREEN_H', 'mmPA_SC_TRAP_SCREEN_HV_EN', + 'mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX', + 'mmPA_SC_TRAP_SCREEN_HV_LOCK', + 'mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX', + 'mmPA_SC_TRAP_SCREEN_H_BASE_IDX', + 'mmPA_SC_TRAP_SCREEN_OCCURRENCE', + 'mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX', + 'mmPA_SC_TRAP_SCREEN_V', 'mmPA_SC_TRAP_SCREEN_V_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_0_BR', + 'mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_0_TL', + 'mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_10_BR', + 'mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_10_TL', + 'mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_11_BR', + 'mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_11_TL', + 'mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_12_BR', + 'mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_12_TL', + 'mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_13_BR', + 'mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_13_TL', + 'mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_14_BR', + 'mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_14_TL', + 'mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_15_BR', + 'mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_15_TL', + 'mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_1_BR', + 'mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_1_TL', + 'mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_2_BR', + 'mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_2_TL', + 'mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_3_BR', + 'mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_3_TL', + 'mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_4_BR', + 'mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_4_TL', + 'mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_5_BR', + 'mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_5_TL', + 'mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_6_BR', + 'mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_6_TL', + 'mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_7_BR', + 'mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_7_TL', + 'mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_8_BR', + 'mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_8_TL', + 'mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_9_BR', + 'mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX', + 'mmPA_SC_VPORT_SCISSOR_9_TL', + 'mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_0', + 'mmPA_SC_VPORT_ZMAX_0_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_1', + 'mmPA_SC_VPORT_ZMAX_10', 'mmPA_SC_VPORT_ZMAX_10_BASE_IDX', + 'mmPA_SC_VPORT_ZMAX_11', 'mmPA_SC_VPORT_ZMAX_11_BASE_IDX', + 'mmPA_SC_VPORT_ZMAX_12', 'mmPA_SC_VPORT_ZMAX_12_BASE_IDX', + 'mmPA_SC_VPORT_ZMAX_13', 'mmPA_SC_VPORT_ZMAX_13_BASE_IDX', + 'mmPA_SC_VPORT_ZMAX_14', 'mmPA_SC_VPORT_ZMAX_14_BASE_IDX', + 'mmPA_SC_VPORT_ZMAX_15', 'mmPA_SC_VPORT_ZMAX_15_BASE_IDX', + 'mmPA_SC_VPORT_ZMAX_1_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_2', + 'mmPA_SC_VPORT_ZMAX_2_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_3', + 'mmPA_SC_VPORT_ZMAX_3_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_4', + 'mmPA_SC_VPORT_ZMAX_4_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_5', + 'mmPA_SC_VPORT_ZMAX_5_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_6', + 'mmPA_SC_VPORT_ZMAX_6_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_7', + 'mmPA_SC_VPORT_ZMAX_7_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_8', + 'mmPA_SC_VPORT_ZMAX_8_BASE_IDX', 'mmPA_SC_VPORT_ZMAX_9', + 'mmPA_SC_VPORT_ZMAX_9_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_0', + 'mmPA_SC_VPORT_ZMIN_0_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_1', + 'mmPA_SC_VPORT_ZMIN_10', 'mmPA_SC_VPORT_ZMIN_10_BASE_IDX', + 'mmPA_SC_VPORT_ZMIN_11', 'mmPA_SC_VPORT_ZMIN_11_BASE_IDX', + 'mmPA_SC_VPORT_ZMIN_12', 'mmPA_SC_VPORT_ZMIN_12_BASE_IDX', + 'mmPA_SC_VPORT_ZMIN_13', 'mmPA_SC_VPORT_ZMIN_13_BASE_IDX', + 'mmPA_SC_VPORT_ZMIN_14', 'mmPA_SC_VPORT_ZMIN_14_BASE_IDX', + 'mmPA_SC_VPORT_ZMIN_15', 'mmPA_SC_VPORT_ZMIN_15_BASE_IDX', + 'mmPA_SC_VPORT_ZMIN_1_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_2', + 'mmPA_SC_VPORT_ZMIN_2_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_3', + 'mmPA_SC_VPORT_ZMIN_3_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_4', + 'mmPA_SC_VPORT_ZMIN_4_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_5', + 'mmPA_SC_VPORT_ZMIN_5_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_6', + 'mmPA_SC_VPORT_ZMIN_6_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_7', + 'mmPA_SC_VPORT_ZMIN_7_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_8', + 'mmPA_SC_VPORT_ZMIN_8_BASE_IDX', 'mmPA_SC_VPORT_ZMIN_9', + 'mmPA_SC_VPORT_ZMIN_9_BASE_IDX', 'mmPA_SC_WINDOW_OFFSET', + 'mmPA_SC_WINDOW_OFFSET_BASE_IDX', 'mmPA_SC_WINDOW_SCISSOR_BR', + 'mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX', 'mmPA_SC_WINDOW_SCISSOR_TL', + 'mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX', + 'mmPA_SIDEBAND_REQUEST_DELAYS', + 'mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX', 'mmPA_STATE_STEREO_X', + 'mmPA_STATE_STEREO_X_BASE_IDX', 'mmPA_STEREO_CNTL', + 'mmPA_STEREO_CNTL_BASE_IDX', 'mmPA_SU_CNTL_STATUS', + 'mmPA_SU_CNTL_STATUS_BASE_IDX', 'mmPA_SU_HARDWARE_SCREEN_OFFSET', + 'mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX', 'mmPA_SU_LINE_CNTL', + 'mmPA_SU_LINE_CNTL_BASE_IDX', 'mmPA_SU_LINE_STIPPLE_CNTL', + 'mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX', + 'mmPA_SU_LINE_STIPPLE_SCALE', + 'mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX', + 'mmPA_SU_LINE_STIPPLE_VALUE', + 'mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX', + 'mmPA_SU_OVER_RASTERIZATION_CNTL', + 'mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX', + 'mmPA_SU_PERFCOUNTER0_HI', 'mmPA_SU_PERFCOUNTER0_HI_BASE_IDX', + 'mmPA_SU_PERFCOUNTER0_LO', 'mmPA_SU_PERFCOUNTER0_LO_BASE_IDX', + 'mmPA_SU_PERFCOUNTER0_SELECT', 'mmPA_SU_PERFCOUNTER0_SELECT1', + 'mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX', 'mmPA_SU_PERFCOUNTER1_HI', + 'mmPA_SU_PERFCOUNTER1_HI_BASE_IDX', 'mmPA_SU_PERFCOUNTER1_LO', + 'mmPA_SU_PERFCOUNTER1_LO_BASE_IDX', 'mmPA_SU_PERFCOUNTER1_SELECT', + 'mmPA_SU_PERFCOUNTER1_SELECT1', + 'mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX', 'mmPA_SU_PERFCOUNTER2_HI', + 'mmPA_SU_PERFCOUNTER2_HI_BASE_IDX', 'mmPA_SU_PERFCOUNTER2_LO', + 'mmPA_SU_PERFCOUNTER2_LO_BASE_IDX', 'mmPA_SU_PERFCOUNTER2_SELECT', + 'mmPA_SU_PERFCOUNTER2_SELECT1', + 'mmPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX', + 'mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX', 'mmPA_SU_PERFCOUNTER3_HI', + 'mmPA_SU_PERFCOUNTER3_HI_BASE_IDX', 'mmPA_SU_PERFCOUNTER3_LO', + 'mmPA_SU_PERFCOUNTER3_LO_BASE_IDX', 'mmPA_SU_PERFCOUNTER3_SELECT', + 'mmPA_SU_PERFCOUNTER3_SELECT1', + 'mmPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX', + 'mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX', 'mmPA_SU_POINT_MINMAX', + 'mmPA_SU_POINT_MINMAX_BASE_IDX', 'mmPA_SU_POINT_SIZE', + 'mmPA_SU_POINT_SIZE_BASE_IDX', 'mmPA_SU_POLY_OFFSET_BACK_OFFSET', + 'mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX', + 'mmPA_SU_POLY_OFFSET_BACK_SCALE', + 'mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX', + 'mmPA_SU_POLY_OFFSET_CLAMP', 'mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX', + 'mmPA_SU_POLY_OFFSET_DB_FMT_CNTL', + 'mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX', + 'mmPA_SU_POLY_OFFSET_FRONT_OFFSET', + 'mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX', + 'mmPA_SU_POLY_OFFSET_FRONT_SCALE', + 'mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX', + 'mmPA_SU_PRIM_FILTER_CNTL', 'mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX', + 'mmPA_SU_SC_MODE_CNTL', 'mmPA_SU_SC_MODE_CNTL_BASE_IDX', + 'mmPA_SU_SMALL_PRIM_FILTER_CNTL', + 'mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX', 'mmPA_SU_VTX_CNTL', + 'mmPA_SU_VTX_CNTL_BASE_IDX', 'mmPCC_PERF_COUNTER', + 'mmPCC_PERF_COUNTER_BASE_IDX', 'mmPMM_GENERAL_CNTL', + 'mmPMM_GENERAL_CNTL_BASE_IDX', 'mmPWRBRK_PERF_COUNTER', + 'mmPWRBRK_PERF_COUNTER_BASE_IDX', 'mmRLC_AUTO_PG_CTRL', + 'mmRLC_AUTO_PG_CTRL_BASE_IDX', 'mmRLC_BUSY_CLK_CNTL', + 'mmRLC_BUSY_CLK_CNTL_BASE_IDX', 'mmRLC_CAC_MASK_CNTL', + 'mmRLC_CAC_MASK_CNTL_BASE_IDX', 'mmRLC_CAPTURE_GPU_CLOCK_COUNT', + 'mmRLC_CAPTURE_GPU_CLOCK_COUNT_1', + 'mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX', + 'mmRLC_CAPTURE_GPU_CLOCK_COUNT_2', + 'mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX', + 'mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX', 'mmRLC_CGCG_CGLS_CTRL', + 'mmRLC_CGCG_CGLS_CTRL_3D', 'mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX', + 'mmRLC_CGCG_CGLS_CTRL_BASE_IDX', 'mmRLC_CGCG_RAMP_CTRL', + 'mmRLC_CGCG_RAMP_CTRL_3D', 'mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX', + 'mmRLC_CGCG_RAMP_CTRL_BASE_IDX', 'mmRLC_CGTT_MGCG_OVERRIDE', + 'mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX', 'mmRLC_CLK_CNTL', + 'mmRLC_CLK_CNTL_BASE_IDX', 'mmRLC_CLK_COUNT_CTRL', + 'mmRLC_CLK_COUNT_CTRL_BASE_IDX', 'mmRLC_CLK_COUNT_GFXCLK_LSB', + 'mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX', + 'mmRLC_CLK_COUNT_GFXCLK_MSB', + 'mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX', + 'mmRLC_CLK_COUNT_REFCLK_LSB', + 'mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX', + 'mmRLC_CLK_COUNT_REFCLK_MSB', + 'mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX', 'mmRLC_CLK_COUNT_STAT', + 'mmRLC_CLK_COUNT_STAT_BASE_IDX', 'mmRLC_CLK_STATUS', + 'mmRLC_CLK_STATUS_BASE_IDX', 'mmRLC_CNTL', 'mmRLC_CNTL_BASE_IDX', + 'mmRLC_CPAXI_DOORBELL_MON_CTRL', + 'mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX', + 'mmRLC_CPAXI_DOORBELL_MON_DATA_LSB', + 'mmRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX', + 'mmRLC_CPAXI_DOORBELL_MON_DATA_MSB', + 'mmRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX', + 'mmRLC_CPAXI_DOORBELL_MON_STAT', + 'mmRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX', 'mmRLC_CP_EOF_INT', + 'mmRLC_CP_EOF_INT_BASE_IDX', 'mmRLC_CP_EOF_INT_CNT', + 'mmRLC_CP_EOF_INT_CNT_BASE_IDX', 'mmRLC_CP_SCHEDULERS', + 'mmRLC_CP_SCHEDULERS_BASE_IDX', 'mmRLC_CP_STAT_INVAL_CTRL', + 'mmRLC_CP_STAT_INVAL_CTRL_BASE_IDX', 'mmRLC_CP_STAT_INVAL_STAT', + 'mmRLC_CP_STAT_INVAL_STAT_BASE_IDX', 'mmRLC_CSIB_ADDR_HI', + 'mmRLC_CSIB_ADDR_HI_BASE_IDX', 'mmRLC_CSIB_ADDR_LO', + 'mmRLC_CSIB_ADDR_LO_BASE_IDX', 'mmRLC_CSIB_LENGTH', + 'mmRLC_CSIB_LENGTH_BASE_IDX', 'mmRLC_DYN_PG_REQUEST', + 'mmRLC_DYN_PG_REQUEST_BASE_IDX', 'mmRLC_DYN_PG_STATUS', + 'mmRLC_DYN_PG_STATUS_BASE_IDX', 'mmRLC_F32_UCODE_VERSION', + 'mmRLC_F32_UCODE_VERSION_BASE_IDX', 'mmRLC_FWL_FIRST_VIOL_ADDR', + 'mmRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX', 'mmRLC_GFX_RM_CNTL', + 'mmRLC_GFX_RM_CNTL_BASE_IDX', 'mmRLC_GPM_CP_DMA_COMPLETE_T0', + 'mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX', + 'mmRLC_GPM_CP_DMA_COMPLETE_T1', + 'mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX', 'mmRLC_GPM_GENERAL_0', + 'mmRLC_GPM_GENERAL_0_BASE_IDX', 'mmRLC_GPM_GENERAL_1', + 'mmRLC_GPM_GENERAL_10', 'mmRLC_GPM_GENERAL_10_BASE_IDX', + 'mmRLC_GPM_GENERAL_11', 'mmRLC_GPM_GENERAL_11_BASE_IDX', + 'mmRLC_GPM_GENERAL_12', 'mmRLC_GPM_GENERAL_12_BASE_IDX', + 'mmRLC_GPM_GENERAL_13', 'mmRLC_GPM_GENERAL_13_BASE_IDX', + 'mmRLC_GPM_GENERAL_14', 'mmRLC_GPM_GENERAL_14_BASE_IDX', + 'mmRLC_GPM_GENERAL_15', 'mmRLC_GPM_GENERAL_15_BASE_IDX', + 'mmRLC_GPM_GENERAL_16', 'mmRLC_GPM_GENERAL_16_BASE_IDX', + 'mmRLC_GPM_GENERAL_1_BASE_IDX', 'mmRLC_GPM_GENERAL_2', + 'mmRLC_GPM_GENERAL_2_BASE_IDX', 'mmRLC_GPM_GENERAL_3', + 'mmRLC_GPM_GENERAL_3_BASE_IDX', 'mmRLC_GPM_GENERAL_4', + 'mmRLC_GPM_GENERAL_4_BASE_IDX', 'mmRLC_GPM_GENERAL_5', + 'mmRLC_GPM_GENERAL_5_BASE_IDX', 'mmRLC_GPM_GENERAL_6', + 'mmRLC_GPM_GENERAL_6_BASE_IDX', 'mmRLC_GPM_GENERAL_7', + 'mmRLC_GPM_GENERAL_7_BASE_IDX', 'mmRLC_GPM_GENERAL_8', + 'mmRLC_GPM_GENERAL_8_BASE_IDX', 'mmRLC_GPM_GENERAL_9', + 'mmRLC_GPM_GENERAL_9_BASE_IDX', 'mmRLC_GPM_INT_DISABLE_TH0', + 'mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX', 'mmRLC_GPM_INT_FORCE_TH0', + 'mmRLC_GPM_INT_FORCE_TH0_BASE_IDX', 'mmRLC_GPM_INT_STAT_TH0', + 'mmRLC_GPM_INT_STAT_TH0_BASE_IDX', 'mmRLC_GPM_IRAM_ADDR', + 'mmRLC_GPM_IRAM_ADDR_BASE_IDX', 'mmRLC_GPM_IRAM_DATA', + 'mmRLC_GPM_IRAM_DATA_BASE_IDX', 'mmRLC_GPM_LEGACY_INT_CLEAR', + 'mmRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX', + 'mmRLC_GPM_LEGACY_INT_DISABLE', + 'mmRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX', + 'mmRLC_GPM_LEGACY_INT_STAT', 'mmRLC_GPM_LEGACY_INT_STAT_BASE_IDX', + 'mmRLC_GPM_LOG_CONT', 'mmRLC_GPM_LOG_CONT_BASE_IDX', + 'mmRLC_GPM_LOG_SIZE', 'mmRLC_GPM_LOG_SIZE_BASE_IDX', + 'mmRLC_GPM_PERF_COUNT_0', 'mmRLC_GPM_PERF_COUNT_0_BASE_IDX', + 'mmRLC_GPM_PERF_COUNT_1', 'mmRLC_GPM_PERF_COUNT_1_BASE_IDX', + 'mmRLC_GPM_SCRATCH_ADDR', 'mmRLC_GPM_SCRATCH_ADDR_BASE_IDX', + 'mmRLC_GPM_SCRATCH_DATA', 'mmRLC_GPM_SCRATCH_DATA_BASE_IDX', + 'mmRLC_GPM_STAT', 'mmRLC_GPM_STAT_BASE_IDX', + 'mmRLC_GPM_THREAD_ENABLE', 'mmRLC_GPM_THREAD_ENABLE_BASE_IDX', + 'mmRLC_GPM_THREAD_PRIORITY', 'mmRLC_GPM_THREAD_PRIORITY_BASE_IDX', + 'mmRLC_GPM_THREAD_RESET', 'mmRLC_GPM_THREAD_RESET_BASE_IDX', + 'mmRLC_GPM_TIMER_CTRL', 'mmRLC_GPM_TIMER_CTRL_BASE_IDX', + 'mmRLC_GPM_TIMER_INT_0', 'mmRLC_GPM_TIMER_INT_0_BASE_IDX', + 'mmRLC_GPM_TIMER_INT_1', 'mmRLC_GPM_TIMER_INT_1_BASE_IDX', + 'mmRLC_GPM_TIMER_INT_2', 'mmRLC_GPM_TIMER_INT_2_BASE_IDX', + 'mmRLC_GPM_TIMER_INT_3', 'mmRLC_GPM_TIMER_INT_3_BASE_IDX', + 'mmRLC_GPM_TIMER_INT_4', 'mmRLC_GPM_TIMER_INT_4_BASE_IDX', + 'mmRLC_GPM_TIMER_STAT', 'mmRLC_GPM_TIMER_STAT_BASE_IDX', + 'mmRLC_GPM_UCODE_ADDR', 'mmRLC_GPM_UCODE_ADDR_BASE_IDX', + 'mmRLC_GPM_UCODE_DATA', 'mmRLC_GPM_UCODE_DATA_BASE_IDX', + 'mmRLC_GPM_UTCL1_CNTL_0', 'mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX', + 'mmRLC_GPM_UTCL1_CNTL_1', 'mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX', + 'mmRLC_GPM_UTCL1_CNTL_2', 'mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX', + 'mmRLC_GPM_UTCL1_TH0_ERROR_1', + 'mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX', + 'mmRLC_GPM_UTCL1_TH0_ERROR_2', + 'mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX', + 'mmRLC_GPM_UTCL1_TH1_ERROR_1', + 'mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX', + 'mmRLC_GPM_UTCL1_TH1_ERROR_2', + 'mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX', + 'mmRLC_GPM_UTCL1_TH2_ERROR_1', + 'mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX', + 'mmRLC_GPM_UTCL1_TH2_ERROR_2', + 'mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX', 'mmRLC_GPR_REG1', + 'mmRLC_GPR_REG1_BASE_IDX', 'mmRLC_GPR_REG2', + 'mmRLC_GPR_REG2_BASE_IDX', 'mmRLC_GPU_CLOCK_32', + 'mmRLC_GPU_CLOCK_32_BASE_IDX', 'mmRLC_GPU_CLOCK_32_RES_SEL', + 'mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX', + 'mmRLC_GPU_CLOCK_COUNT_LSB', 'mmRLC_GPU_CLOCK_COUNT_LSB_1', + 'mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX', + 'mmRLC_GPU_CLOCK_COUNT_LSB_2', + 'mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX', + 'mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX', 'mmRLC_GPU_CLOCK_COUNT_MSB', + 'mmRLC_GPU_CLOCK_COUNT_MSB_1', + 'mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX', + 'mmRLC_GPU_CLOCK_COUNT_MSB_2', + 'mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX', + 'mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX', + 'mmRLC_GPU_CLOCK_COUNT_SPM_LSB', + 'mmRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX', + 'mmRLC_GPU_CLOCK_COUNT_SPM_MSB', + 'mmRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX', + 'mmRLC_GPU_IOV_ACTIVE_FCN_ID', + 'mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX', 'mmRLC_GPU_IOV_CFG_REG1', + 'mmRLC_GPU_IOV_CFG_REG1_BASE_IDX', 'mmRLC_GPU_IOV_CFG_REG2', + 'mmRLC_GPU_IOV_CFG_REG2_BASE_IDX', 'mmRLC_GPU_IOV_CFG_REG6', + 'mmRLC_GPU_IOV_CFG_REG6_BASE_IDX', 'mmRLC_GPU_IOV_CFG_REG8', + 'mmRLC_GPU_IOV_CFG_REG8_BASE_IDX', 'mmRLC_GPU_IOV_F32_CNTL', + 'mmRLC_GPU_IOV_F32_CNTL_BASE_IDX', 'mmRLC_GPU_IOV_F32_RESET', + 'mmRLC_GPU_IOV_F32_RESET_BASE_IDX', 'mmRLC_GPU_IOV_INT_DISABLE', + 'mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX', 'mmRLC_GPU_IOV_INT_FORCE', + 'mmRLC_GPU_IOV_INT_FORCE_BASE_IDX', 'mmRLC_GPU_IOV_INT_STAT', + 'mmRLC_GPU_IOV_INT_STAT_BASE_IDX', 'mmRLC_GPU_IOV_PERF_CNT_CNTL', + 'mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX', + 'mmRLC_GPU_IOV_PERF_CNT_RD_ADDR', + 'mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX', + 'mmRLC_GPU_IOV_PERF_CNT_RD_DATA', + 'mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX', + 'mmRLC_GPU_IOV_PERF_CNT_WR_ADDR', + 'mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX', + 'mmRLC_GPU_IOV_PERF_CNT_WR_DATA', + 'mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX', + 'mmRLC_GPU_IOV_RLC_RESPONSE', + 'mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX', 'mmRLC_GPU_IOV_SCH_0', + 'mmRLC_GPU_IOV_SCH_0_BASE_IDX', 'mmRLC_GPU_IOV_SCH_1', + 'mmRLC_GPU_IOV_SCH_1_BASE_IDX', 'mmRLC_GPU_IOV_SCH_2', + 'mmRLC_GPU_IOV_SCH_2_BASE_IDX', 'mmRLC_GPU_IOV_SCH_3', + 'mmRLC_GPU_IOV_SCH_3_BASE_IDX', 'mmRLC_GPU_IOV_SCH_BLOCK', + 'mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX', 'mmRLC_GPU_IOV_SCRATCH_ADDR', + 'mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX', + 'mmRLC_GPU_IOV_SCRATCH_DATA', + 'mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA0_BUSY_STATUS', + 'mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA0_STATUS', + 'mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA1_BUSY_STATUS', + 'mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA1_STATUS', + 'mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA2_BUSY_STATUS', + 'mmRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA2_STATUS', + 'mmRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA3_BUSY_STATUS', + 'mmRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA3_STATUS', + 'mmRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA4_BUSY_STATUS', + 'mmRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA4_STATUS', + 'mmRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA5_BUSY_STATUS', + 'mmRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA5_STATUS', + 'mmRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA6_BUSY_STATUS', + 'mmRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA6_STATUS', + 'mmRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA7_BUSY_STATUS', + 'mmRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SDMA7_STATUS', + 'mmRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_SMU_RESPONSE', + 'mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX', 'mmRLC_GPU_IOV_UCODE_ADDR', + 'mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX', 'mmRLC_GPU_IOV_UCODE_DATA', + 'mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX', + 'mmRLC_GPU_IOV_VF_DOORBELL_STATUS', + 'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX', + 'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR', + 'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX', + 'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET', + 'mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX', + 'mmRLC_GPU_IOV_VF_ENABLE', 'mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX', + 'mmRLC_GPU_IOV_VF_MASK', 'mmRLC_GPU_IOV_VF_MASK_BASE_IDX', + 'mmRLC_GPU_IOV_VIRT_RESET_REQ', + 'mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX', + 'mmRLC_GPU_IOV_VM_BUSY_STATUS', + 'mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX', 'mmRLC_GTS_OFFSET_LSB', + 'mmRLC_GTS_OFFSET_LSB_BASE_IDX', 'mmRLC_GTS_OFFSET_MSB', + 'mmRLC_GTS_OFFSET_MSB_BASE_IDX', 'mmRLC_HYP_BOOTLOAD_ADDR_HI', + 'mmRLC_HYP_BOOTLOAD_ADDR_HI_BASE_IDX', + 'mmRLC_HYP_BOOTLOAD_ADDR_LO', + 'mmRLC_HYP_BOOTLOAD_ADDR_LO_BASE_IDX', 'mmRLC_HYP_BOOTLOAD_SIZE', + 'mmRLC_HYP_BOOTLOAD_SIZE_BASE_IDX', 'mmRLC_HYP_RESET_VECTOR', + 'mmRLC_HYP_RESET_VECTOR_BASE_IDX', 'mmRLC_HYP_RLCG_UCODE_CHKSUM', + 'mmRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX', + 'mmRLC_HYP_RLCP_UCODE_CHKSUM', + 'mmRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX', + 'mmRLC_HYP_RLCV_UCODE_CHKSUM', + 'mmRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX', 'mmRLC_HYP_SEMAPHORE_0', + 'mmRLC_HYP_SEMAPHORE_0_BASE_IDX', 'mmRLC_HYP_SEMAPHORE_1', + 'mmRLC_HYP_SEMAPHORE_1_BASE_IDX', 'mmRLC_HYP_SEMAPHORE_2', + 'mmRLC_HYP_SEMAPHORE_2_BASE_IDX', 'mmRLC_HYP_SEMAPHORE_3', + 'mmRLC_HYP_SEMAPHORE_3_BASE_IDX', 'mmRLC_IH_COOKIE', + 'mmRLC_IH_COOKIE_BASE_IDX', 'mmRLC_IH_COOKIE_CNTL', + 'mmRLC_IH_COOKIE_CNTL_BASE_IDX', 'mmRLC_INT_STAT', + 'mmRLC_INT_STAT_BASE_IDX', 'mmRLC_JUMP_TABLE_RESTORE', + 'mmRLC_JUMP_TABLE_RESTORE_BASE_IDX', + 'mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK', + 'mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK_BASE_IDX', 'mmRLC_LB_CNTL', + 'mmRLC_LB_CNTL_BASE_IDX', 'mmRLC_LB_CNTR_1', + 'mmRLC_LB_CNTR_1_BASE_IDX', 'mmRLC_LB_CNTR_2', + 'mmRLC_LB_CNTR_2_BASE_IDX', 'mmRLC_LB_CNTR_INIT_1', + 'mmRLC_LB_CNTR_INIT_1_BASE_IDX', 'mmRLC_LB_CNTR_INIT_2', + 'mmRLC_LB_CNTR_INIT_2_BASE_IDX', 'mmRLC_LB_CNTR_MAX_1', + 'mmRLC_LB_CNTR_MAX_1_BASE_IDX', 'mmRLC_LB_CNTR_MAX_2', + 'mmRLC_LB_CNTR_MAX_2_BASE_IDX', 'mmRLC_LB_CONFIG_1', + 'mmRLC_LB_CONFIG_1_BASE_IDX', 'mmRLC_LB_CONFIG_2', + 'mmRLC_LB_CONFIG_2_BASE_IDX', 'mmRLC_LB_CONFIG_3', + 'mmRLC_LB_CONFIG_3_BASE_IDX', 'mmRLC_LB_CONFIG_4', + 'mmRLC_LB_CONFIG_4_BASE_IDX', 'mmRLC_LB_CONFIG_5', + 'mmRLC_LB_CONFIG_5_BASE_IDX', 'mmRLC_LB_DELAY', + 'mmRLC_LB_DELAY_BASE_IDX', 'mmRLC_LB_INIT_WGP_MASK', + 'mmRLC_LB_INIT_WGP_MASK_BASE_IDX', 'mmRLC_LB_PARAMS', + 'mmRLC_LB_PARAMS_BASE_IDX', 'mmRLC_LB_WGP_STAT', + 'mmRLC_LB_WGP_STAT_BASE_IDX', 'mmRLC_MAX_PG_WGP', + 'mmRLC_MAX_PG_WGP_BASE_IDX', 'mmRLC_MEM_SLP_CNTL', + 'mmRLC_MEM_SLP_CNTL_BASE_IDX', 'mmRLC_MGCG_CTRL', + 'mmRLC_MGCG_CTRL_BASE_IDX', 'mmRLC_PACE_INT_CLEAR', + 'mmRLC_PACE_INT_CLEAR_BASE_IDX', 'mmRLC_PACE_INT_DISABLE', + 'mmRLC_PACE_INT_DISABLE_BASE_IDX', 'mmRLC_PACE_INT_FORCE', + 'mmRLC_PACE_INT_FORCE_BASE_IDX', 'mmRLC_PACE_INT_STAT', + 'mmRLC_PACE_INT_STAT_BASE_IDX', 'mmRLC_PACE_SCRATCH_ADDR', + 'mmRLC_PACE_SCRATCH_ADDR_BASE_IDX', 'mmRLC_PACE_SCRATCH_DATA', + 'mmRLC_PACE_SCRATCH_DATA_BASE_IDX', 'mmRLC_PACE_SPARE_INT', + 'mmRLC_PACE_SPARE_INT_1', 'mmRLC_PACE_SPARE_INT_1_BASE_IDX', + 'mmRLC_PACE_SPARE_INT_BASE_IDX', 'mmRLC_PACE_TIMER_CTRL', + 'mmRLC_PACE_TIMER_CTRL_BASE_IDX', 'mmRLC_PACE_TIMER_INT_0', + 'mmRLC_PACE_TIMER_INT_0_BASE_IDX', 'mmRLC_PACE_TIMER_INT_1', + 'mmRLC_PACE_TIMER_INT_1_BASE_IDX', 'mmRLC_PACE_TIMER_STAT', + 'mmRLC_PACE_TIMER_STAT_BASE_IDX', 'mmRLC_PACE_UCODE_ADDR', + 'mmRLC_PACE_UCODE_ADDR_BASE_IDX', 'mmRLC_PACE_UCODE_DATA', + 'mmRLC_PACE_UCODE_DATA_BASE_IDX', + 'mmRLC_PCC_STRETCH_HYSTERESIS_CNTL', + 'mmRLC_PCC_STRETCH_HYSTERESIS_CNTL_BASE_IDX', + 'mmRLC_PERFCOUNTER0_HI', 'mmRLC_PERFCOUNTER0_HI_BASE_IDX', + 'mmRLC_PERFCOUNTER0_LO', 'mmRLC_PERFCOUNTER0_LO_BASE_IDX', + 'mmRLC_PERFCOUNTER0_SELECT', 'mmRLC_PERFCOUNTER0_SELECT_BASE_IDX', + 'mmRLC_PERFCOUNTER1_HI', 'mmRLC_PERFCOUNTER1_HI_BASE_IDX', + 'mmRLC_PERFCOUNTER1_LO', 'mmRLC_PERFCOUNTER1_LO_BASE_IDX', + 'mmRLC_PERFCOUNTER1_SELECT', 'mmRLC_PERFCOUNTER1_SELECT_BASE_IDX', + 'mmRLC_PERFMON_CLK_CNTL', 'mmRLC_PERFMON_CLK_CNTL_BASE_IDX', + 'mmRLC_PERFMON_CNTL', 'mmRLC_PERFMON_CNTL_BASE_IDX', + 'mmRLC_PG_ALWAYS_ON_WGP_MASK', + 'mmRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX', 'mmRLC_PG_CNTL', + 'mmRLC_PG_CNTL_BASE_IDX', 'mmRLC_PG_DELAY', 'mmRLC_PG_DELAY_2', + 'mmRLC_PG_DELAY_2_BASE_IDX', 'mmRLC_PG_DELAY_3', + 'mmRLC_PG_DELAY_3_BASE_IDX', 'mmRLC_PG_DELAY_BASE_IDX', + 'mmRLC_PREWALKER_UTCL1_ADDR_LSB', + 'mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX', + 'mmRLC_PREWALKER_UTCL1_ADDR_MSB', + 'mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX', + 'mmRLC_PREWALKER_UTCL1_CNTL', + 'mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX', + 'mmRLC_PREWALKER_UTCL1_SIZE_LSB', + 'mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX', + 'mmRLC_PREWALKER_UTCL1_SIZE_MSB', + 'mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX', + 'mmRLC_PREWALKER_UTCL1_TRIG', + 'mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX', 'mmRLC_R2I_CNTL_0', + 'mmRLC_R2I_CNTL_0_BASE_IDX', 'mmRLC_R2I_CNTL_1', + 'mmRLC_R2I_CNTL_1_BASE_IDX', 'mmRLC_R2I_CNTL_2', + 'mmRLC_R2I_CNTL_2_BASE_IDX', 'mmRLC_R2I_CNTL_3', + 'mmRLC_R2I_CNTL_3_BASE_IDX', 'mmRLC_REFCLOCK_TIMESTAMP_LSB', + 'mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX', + 'mmRLC_REFCLOCK_TIMESTAMP_MSB', + 'mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX', + 'mmRLC_RLCG_DOORBELL_0_DATA_HI', + 'mmRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX', + 'mmRLC_RLCG_DOORBELL_0_DATA_LO', + 'mmRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX', + 'mmRLC_RLCG_DOORBELL_1_DATA_HI', + 'mmRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX', + 'mmRLC_RLCG_DOORBELL_1_DATA_LO', + 'mmRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX', + 'mmRLC_RLCG_DOORBELL_2_DATA_HI', + 'mmRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX', + 'mmRLC_RLCG_DOORBELL_2_DATA_LO', + 'mmRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX', + 'mmRLC_RLCG_DOORBELL_3_DATA_HI', + 'mmRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX', + 'mmRLC_RLCG_DOORBELL_3_DATA_LO', + 'mmRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX', + 'mmRLC_RLCG_DOORBELL_CNTL', 'mmRLC_RLCG_DOORBELL_CNTL_BASE_IDX', + 'mmRLC_RLCG_DOORBELL_RANGE', 'mmRLC_RLCG_DOORBELL_RANGE_BASE_IDX', + 'mmRLC_RLCG_DOORBELL_STAT', 'mmRLC_RLCG_DOORBELL_STAT_BASE_IDX', + 'mmRLC_RLCP_DOORBELL_0_DATA_HI', + 'mmRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX', + 'mmRLC_RLCP_DOORBELL_0_DATA_LO', + 'mmRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX', + 'mmRLC_RLCP_DOORBELL_1_DATA_HI', + 'mmRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX', + 'mmRLC_RLCP_DOORBELL_1_DATA_LO', + 'mmRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX', + 'mmRLC_RLCP_DOORBELL_2_DATA_HI', + 'mmRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX', + 'mmRLC_RLCP_DOORBELL_2_DATA_LO', + 'mmRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX', + 'mmRLC_RLCP_DOORBELL_3_DATA_HI', + 'mmRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX', + 'mmRLC_RLCP_DOORBELL_3_DATA_LO', + 'mmRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX', + 'mmRLC_RLCP_DOORBELL_CNTL', 'mmRLC_RLCP_DOORBELL_CNTL_BASE_IDX', + 'mmRLC_RLCP_DOORBELL_RANGE', 'mmRLC_RLCP_DOORBELL_RANGE_BASE_IDX', + 'mmRLC_RLCP_DOORBELL_STAT', 'mmRLC_RLCP_DOORBELL_STAT_BASE_IDX', + 'mmRLC_RLCP_IRAM_ADDR', 'mmRLC_RLCP_IRAM_ADDR_BASE_IDX', + 'mmRLC_RLCP_IRAM_DATA', 'mmRLC_RLCP_IRAM_DATA_BASE_IDX', + 'mmRLC_RLCS_ABORTED_PD_SEQUENCE', + 'mmRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX', + 'mmRLC_RLCS_AUXILIARY_REG_1', + 'mmRLC_RLCS_AUXILIARY_REG_1_BASE_IDX', + 'mmRLC_RLCS_AUXILIARY_REG_2', + 'mmRLC_RLCS_AUXILIARY_REG_2_BASE_IDX', + 'mmRLC_RLCS_AUXILIARY_REG_3', + 'mmRLC_RLCS_AUXILIARY_REG_3_BASE_IDX', + 'mmRLC_RLCS_AUXILIARY_REG_4', + 'mmRLC_RLCS_AUXILIARY_REG_4_BASE_IDX', + 'mmRLC_RLCS_BOOTLOAD_ID_STATUS1', + 'mmRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX', + 'mmRLC_RLCS_BOOTLOAD_ID_STATUS2', + 'mmRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX', + 'mmRLC_RLCS_BOOTLOAD_STATUS', + 'mmRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX', 'mmRLC_RLCS_CGCG_REQUEST', + 'mmRLC_RLCS_CGCG_REQUEST_BASE_IDX', 'mmRLC_RLCS_CGCG_STATUS', + 'mmRLC_RLCS_CGCG_STATUS_BASE_IDX', 'mmRLC_RLCS_CMP_IDLE_CNTL', + 'mmRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX', + 'mmRLC_RLCS_CP_DMA_SRCID_OVER', + 'mmRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX', + 'mmRLC_RLCS_CP_INT_CTRL_1', 'mmRLC_RLCS_CP_INT_CTRL_1_BASE_IDX', + 'mmRLC_RLCS_CP_INT_CTRL_2', 'mmRLC_RLCS_CP_INT_CTRL_2_BASE_IDX', + 'mmRLC_RLCS_CP_INT_INFO_1', 'mmRLC_RLCS_CP_INT_INFO_1_BASE_IDX', + 'mmRLC_RLCS_CP_INT_INFO_2', 'mmRLC_RLCS_CP_INT_INFO_2_BASE_IDX', + 'mmRLC_RLCS_DEC_DUMP_ADDR', 'mmRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX', + 'mmRLC_RLCS_DEC_END', 'mmRLC_RLCS_DEC_END_BASE_IDX', + 'mmRLC_RLCS_DEC_START', 'mmRLC_RLCS_DEC_START_BASE_IDX', + 'mmRLC_RLCS_DIDT_FORCE_STALL', + 'mmRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX', 'mmRLC_RLCS_DSM_TRIG', + 'mmRLC_RLCS_DSM_TRIG_BASE_IDX', 'mmRLC_RLCS_EDC_INT_CNTL', + 'mmRLC_RLCS_EDC_INT_CNTL_BASE_IDX', 'mmRLC_RLCS_EXCEPTION_REG_1', + 'mmRLC_RLCS_EXCEPTION_REG_1_BASE_IDX', + 'mmRLC_RLCS_EXCEPTION_REG_2', + 'mmRLC_RLCS_EXCEPTION_REG_2_BASE_IDX', + 'mmRLC_RLCS_EXCEPTION_REG_3', + 'mmRLC_RLCS_EXCEPTION_REG_3_BASE_IDX', + 'mmRLC_RLCS_EXCEPTION_REG_4', + 'mmRLC_RLCS_EXCEPTION_REG_4_BASE_IDX', 'mmRLC_RLCS_GENERAL_0', + 'mmRLC_RLCS_GENERAL_0_BASE_IDX', 'mmRLC_RLCS_GENERAL_1', + 'mmRLC_RLCS_GENERAL_1_BASE_IDX', 'mmRLC_RLCS_GENERAL_2', + 'mmRLC_RLCS_GENERAL_2_BASE_IDX', 'mmRLC_RLCS_GENERAL_3', + 'mmRLC_RLCS_GENERAL_3_BASE_IDX', 'mmRLC_RLCS_GENERAL_4', + 'mmRLC_RLCS_GENERAL_4_BASE_IDX', 'mmRLC_RLCS_GENERAL_5', + 'mmRLC_RLCS_GENERAL_5_BASE_IDX', 'mmRLC_RLCS_GENERAL_6', + 'mmRLC_RLCS_GENERAL_6_BASE_IDX', 'mmRLC_RLCS_GENERAL_7', + 'mmRLC_RLCS_GENERAL_7_BASE_IDX', 'mmRLC_RLCS_GFX_DS_CNTL', + 'mmRLC_RLCS_GFX_DS_CNTL_BASE_IDX', + 'mmRLC_RLCS_GPM_LEGACY_INT_DISABLE', + 'mmRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX', + 'mmRLC_RLCS_GPM_LEGACY_INT_STAT', + 'mmRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX', 'mmRLC_RLCS_GPM_STAT', + 'mmRLC_RLCS_GPM_STAT_2', 'mmRLC_RLCS_GPM_STAT_2_BASE_IDX', + 'mmRLC_RLCS_GPM_STAT_BASE_IDX', + 'mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL', + 'mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX', + 'mmRLC_RLCS_GRBM_IDLE_BUSY_STAT', + 'mmRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX', + 'mmRLC_RLCS_GRBM_SOFT_RESET', + 'mmRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX', + 'mmRLC_RLCS_IH_COOKIE_SEMAPHORE', + 'mmRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX', 'mmRLC_RLCS_IH_CTRL_1', + 'mmRLC_RLCS_IH_CTRL_1_BASE_IDX', 'mmRLC_RLCS_IH_CTRL_2', + 'mmRLC_RLCS_IH_CTRL_2_BASE_IDX', 'mmRLC_RLCS_IH_CTRL_3', + 'mmRLC_RLCS_IH_CTRL_3_BASE_IDX', 'mmRLC_RLCS_IH_SEMAPHORE', + 'mmRLC_RLCS_IH_SEMAPHORE_BASE_IDX', 'mmRLC_RLCS_IH_STATUS', + 'mmRLC_RLCS_IH_STATUS_BASE_IDX', 'mmRLC_RLCS_IOV_CMD_STATUS', + 'mmRLC_RLCS_IOV_CMD_STATUS_BASE_IDX', + 'mmRLC_RLCS_IOV_CNTX_LOC_SIZE', + 'mmRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX', + 'mmRLC_RLCS_IOV_SCH_BLOCK', 'mmRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX', + 'mmRLC_RLCS_IOV_VM_BUSY_STATUS', + 'mmRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX', + 'mmRLC_RLCS_KMD_LOG_CNTL1', 'mmRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX', + 'mmRLC_RLCS_KMD_LOG_CNTL2', 'mmRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX', + 'mmRLC_RLCS_LB_CONTROL', 'mmRLC_RLCS_LB_CONTROL_BASE_IDX', + 'mmRLC_RLCS_LB_READ', 'mmRLC_RLCS_LB_READ_BASE_IDX', + 'mmRLC_RLCS_LB_STATUS', 'mmRLC_RLCS_LB_STATUS_BASE_IDX', + 'mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL', + 'mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL_BASE_IDX', + 'mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE', + 'mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX', + 'mmRLC_RLCS_PG_CHANGE_READ', 'mmRLC_RLCS_PG_CHANGE_READ_BASE_IDX', + 'mmRLC_RLCS_PG_CHANGE_STATUS', + 'mmRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX', + 'mmRLC_RLCS_POWER_BRAKE_CNTL', + 'mmRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX', + 'mmRLC_RLCS_POWER_BRAKE_CNTL_TH1', + 'mmRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX', + 'mmRLC_RLCS_SMUIO_VIDCHG_CTRL', + 'mmRLC_RLCS_SMUIO_VIDCHG_CTRL_BASE_IDX', + 'mmRLC_RLCS_SMU_GFXCLK_CONTROL', + 'mmRLC_RLCS_SMU_GFXCLK_CONTROL_BASE_IDX', + 'mmRLC_RLCS_SMU_GFXCLK_STATUS', + 'mmRLC_RLCS_SMU_GFXCLK_STATUS_BASE_IDX', 'mmRLC_RLCS_SOC_DS_CNTL', + 'mmRLC_RLCS_SOC_DS_CNTL_BASE_IDX', 'mmRLC_RLCS_SPM_INT_CTRL', + 'mmRLC_RLCS_SPM_INT_CTRL_BASE_IDX', 'mmRLC_RLCS_SPM_INT_INFO_1', + 'mmRLC_RLCS_SPM_INT_INFO_1_BASE_IDX', 'mmRLC_RLCS_SPM_INT_INFO_2', + 'mmRLC_RLCS_SPM_INT_INFO_2_BASE_IDX', 'mmRLC_RLCS_SPM_SQTT_MODE', + 'mmRLC_RLCS_SPM_SQTT_MODE_BASE_IDX', 'mmRLC_RLCS_SRM_SRCID_CNTL', + 'mmRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX', 'mmRLC_RLCS_UTCL2_CNTL', + 'mmRLC_RLCS_UTCL2_CNTL_BASE_IDX', 'mmRLC_RLCS_WGP_READ', + 'mmRLC_RLCS_WGP_READ_BASE_IDX', 'mmRLC_RLCS_WGP_STATUS', + 'mmRLC_RLCS_WGP_STATUS_BASE_IDX', 'mmRLC_RLCV_COMMAND', + 'mmRLC_RLCV_COMMAND_BASE_IDX', 'mmRLC_RLCV_DOORBELL_0_DATA_HI', + 'mmRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX', + 'mmRLC_RLCV_DOORBELL_0_DATA_LO', + 'mmRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX', + 'mmRLC_RLCV_DOORBELL_1_DATA_HI', + 'mmRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX', + 'mmRLC_RLCV_DOORBELL_1_DATA_LO', + 'mmRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX', + 'mmRLC_RLCV_DOORBELL_2_DATA_HI', + 'mmRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX', + 'mmRLC_RLCV_DOORBELL_2_DATA_LO', + 'mmRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX', + 'mmRLC_RLCV_DOORBELL_3_DATA_HI', + 'mmRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX', + 'mmRLC_RLCV_DOORBELL_3_DATA_LO', + 'mmRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX', + 'mmRLC_RLCV_DOORBELL_CNTL', 'mmRLC_RLCV_DOORBELL_CNTL_BASE_IDX', + 'mmRLC_RLCV_DOORBELL_RANGE', 'mmRLC_RLCV_DOORBELL_RANGE_BASE_IDX', + 'mmRLC_RLCV_DOORBELL_STAT', 'mmRLC_RLCV_DOORBELL_STAT_BASE_IDX', + 'mmRLC_RLCV_IRAM_ADDR', 'mmRLC_RLCV_IRAM_ADDR_BASE_IDX', + 'mmRLC_RLCV_IRAM_DATA', 'mmRLC_RLCV_IRAM_DATA_BASE_IDX', + 'mmRLC_RLCV_SAFE_MODE', 'mmRLC_RLCV_SAFE_MODE_BASE_IDX', + 'mmRLC_RLCV_SPARE_INT', 'mmRLC_RLCV_SPARE_INT_1', + 'mmRLC_RLCV_SPARE_INT_1_BASE_IDX', + 'mmRLC_RLCV_SPARE_INT_BASE_IDX', 'mmRLC_RLCV_TIMER_CTRL', + 'mmRLC_RLCV_TIMER_CTRL_BASE_IDX', 'mmRLC_RLCV_TIMER_INT_0', + 'mmRLC_RLCV_TIMER_INT_0_BASE_IDX', 'mmRLC_RLCV_TIMER_INT_1', + 'mmRLC_RLCV_TIMER_INT_1_BASE_IDX', 'mmRLC_RLCV_TIMER_STAT', + 'mmRLC_RLCV_TIMER_STAT_BASE_IDX', 'mmRLC_SAFE_MODE', + 'mmRLC_SAFE_MODE_BASE_IDX', 'mmRLC_SDMA0_BUSY_STATUS', + 'mmRLC_SDMA0_BUSY_STATUS_BASE_IDX', 'mmRLC_SDMA0_STATUS', + 'mmRLC_SDMA0_STATUS_BASE_IDX', 'mmRLC_SDMA1_BUSY_STATUS', + 'mmRLC_SDMA1_BUSY_STATUS_BASE_IDX', 'mmRLC_SDMA1_STATUS', + 'mmRLC_SDMA1_STATUS_BASE_IDX', 'mmRLC_SDMA2_BUSY_STATUS', + 'mmRLC_SDMA2_BUSY_STATUS_BASE_IDX', 'mmRLC_SDMA2_STATUS', + 'mmRLC_SDMA2_STATUS_BASE_IDX', 'mmRLC_SDMA3_BUSY_STATUS', + 'mmRLC_SDMA3_BUSY_STATUS_BASE_IDX', 'mmRLC_SDMA3_STATUS', + 'mmRLC_SDMA3_STATUS_BASE_IDX', 'mmRLC_SEMAPHORE_0', + 'mmRLC_SEMAPHORE_0_BASE_IDX', 'mmRLC_SEMAPHORE_1', + 'mmRLC_SEMAPHORE_1_BASE_IDX', 'mmRLC_SEMAPHORE_2', + 'mmRLC_SEMAPHORE_2_BASE_IDX', 'mmRLC_SEMAPHORE_3', + 'mmRLC_SEMAPHORE_3_BASE_IDX', 'mmRLC_SERDES_BUSY', + 'mmRLC_SERDES_BUSY_BASE_IDX', 'mmRLC_SERDES_CTRL', + 'mmRLC_SERDES_CTRL_BASE_IDX', 'mmRLC_SERDES_DATA', + 'mmRLC_SERDES_DATA_BASE_IDX', 'mmRLC_SERDES_MASK', + 'mmRLC_SERDES_MASK_BASE_IDX', 'mmRLC_SERDES_RD_DATA_0', + 'mmRLC_SERDES_RD_DATA_0_BASE_IDX', 'mmRLC_SERDES_RD_DATA_1', + 'mmRLC_SERDES_RD_DATA_1_BASE_IDX', 'mmRLC_SERDES_RD_DATA_2', + 'mmRLC_SERDES_RD_DATA_2_BASE_IDX', 'mmRLC_SERDES_RD_DATA_3', + 'mmRLC_SERDES_RD_DATA_3_BASE_IDX', 'mmRLC_SERDES_RD_INDEX', + 'mmRLC_SERDES_RD_INDEX_BASE_IDX', 'mmRLC_SMU_ARGUMENT_1', + 'mmRLC_SMU_ARGUMENT_1_BASE_IDX', 'mmRLC_SMU_ARGUMENT_2', + 'mmRLC_SMU_ARGUMENT_2_BASE_IDX', 'mmRLC_SMU_ARGUMENT_3', + 'mmRLC_SMU_ARGUMENT_3_BASE_IDX', 'mmRLC_SMU_ARGUMENT_4', + 'mmRLC_SMU_ARGUMENT_4_BASE_IDX', 'mmRLC_SMU_CLK_REQ', + 'mmRLC_SMU_CLK_REQ_BASE_IDX', 'mmRLC_SMU_COMMAND', + 'mmRLC_SMU_COMMAND_BASE_IDX', 'mmRLC_SMU_GRBM_REG_SAVE_CTRL', + 'mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX', 'mmRLC_SMU_MESSAGE', + 'mmRLC_SMU_MESSAGE_BASE_IDX', 'mmRLC_SMU_SAFE_MODE', + 'mmRLC_SMU_SAFE_MODE_BASE_IDX', 'mmRLC_SPARE_INT_0', + 'mmRLC_SPARE_INT_0_BASE_IDX', 'mmRLC_SPARE_INT_1', + 'mmRLC_SPARE_INT_1_BASE_IDX', 'mmRLC_SPARE_INT_2', + 'mmRLC_SPARE_INT_2_BASE_IDX', 'mmRLC_SPM_ACCUM_CTRL', + 'mmRLC_SPM_ACCUM_CTRLRAM_ADDR', + 'mmRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX', + 'mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET', + 'mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX', + 'mmRLC_SPM_ACCUM_CTRLRAM_DATA', + 'mmRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX', + 'mmRLC_SPM_ACCUM_CTRL_BASE_IDX', + 'mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS', + 'mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX', + 'mmRLC_SPM_ACCUM_DATARAM_ADDR', + 'mmRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX', + 'mmRLC_SPM_ACCUM_DATARAM_DATA', + 'mmRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX', + 'mmRLC_SPM_ACCUM_DATARAM_WRCOUNT', + 'mmRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX', + 'mmRLC_SPM_ACCUM_MODE', 'mmRLC_SPM_ACCUM_MODE_BASE_IDX', + 'mmRLC_SPM_ACCUM_SAMPLES_REQUESTED', + 'mmRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX', + 'mmRLC_SPM_ACCUM_STATUS', 'mmRLC_SPM_ACCUM_STATUS_BASE_IDX', + 'mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR', + 'mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX', + 'mmRLC_SPM_ACCUM_SWA_DATARAM_DATA', + 'mmRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX', + 'mmRLC_SPM_ACCUM_THRESHOLD', 'mmRLC_SPM_ACCUM_THRESHOLD_BASE_IDX', + 'mmRLC_SPM_DESER_START_SKEW', + 'mmRLC_SPM_DESER_START_SKEW_BASE_IDX', + 'mmRLC_SPM_GFXCLOCK_HIGHCOUNT', + 'mmRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX', + 'mmRLC_SPM_GFXCLOCK_LOWCOUNT', + 'mmRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX', + 'mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR', + 'mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR_BASE_IDX', + 'mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA', + 'mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA_BASE_IDX', + 'mmRLC_SPM_GLOBALS_MUXSEL_SKEW', + 'mmRLC_SPM_GLOBALS_MUXSEL_SKEW_BASE_IDX', + 'mmRLC_SPM_GLOBALS_SAMPLE_SKEW', + 'mmRLC_SPM_GLOBALS_SAMPLE_SKEW_BASE_IDX', + 'mmRLC_SPM_GLOBAL_MUXSEL_ADDR', + 'mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX', + 'mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET', + 'mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET_BASE_IDX', + 'mmRLC_SPM_GLOBAL_MUXSEL_DATA', + 'mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX', 'mmRLC_SPM_INT_CNTL', + 'mmRLC_SPM_INT_CNTL_BASE_IDX', 'mmRLC_SPM_INT_INFO_1', + 'mmRLC_SPM_INT_INFO_1_BASE_IDX', 'mmRLC_SPM_INT_INFO_2', + 'mmRLC_SPM_INT_INFO_2_BASE_IDX', 'mmRLC_SPM_INT_STATUS', + 'mmRLC_SPM_INT_STATUS_BASE_IDX', 'mmRLC_SPM_MC_CNTL', + 'mmRLC_SPM_MC_CNTL_BASE_IDX', 'mmRLC_SPM_PERFMON_CNTL', + 'mmRLC_SPM_PERFMON_CNTL_BASE_IDX', + 'mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE', + 'mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE_BASE_IDX', + 'mmRLC_SPM_PERFMON_RING_BASE_HI', + 'mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX', + 'mmRLC_SPM_PERFMON_RING_BASE_LO', + 'mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX', + 'mmRLC_SPM_PERFMON_RING_SIZE', + 'mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX', + 'mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE', + 'mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE_BASE_IDX', + 'mmRLC_SPM_PERFMON_SEGMENT_SIZE', + 'mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX', + 'mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE', + 'mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE_BASE_IDX', + 'mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE', + 'mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE_BASE_IDX', + 'mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE', + 'mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE_BASE_IDX', + 'mmRLC_SPM_RING_RDPTR', 'mmRLC_SPM_RING_RDPTR_BASE_IDX', + 'mmRLC_SPM_RING_WRPTR', 'mmRLC_SPM_RING_WRPTR_BASE_IDX', + 'mmRLC_SPM_SAMPLE_CNT', 'mmRLC_SPM_SAMPLE_CNT_BASE_IDX', + 'mmRLC_SPM_SEGMENT_THRESHOLD', + 'mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX', + 'mmRLC_SPM_SE_MUXSEL_ADDR', 'mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX', + 'mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET', + 'mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET_BASE_IDX', + 'mmRLC_SPM_SE_MUXSEL_DATA', 'mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX', + 'mmRLC_SPM_SE_MUXSEL_SKEW', 'mmRLC_SPM_SE_MUXSEL_SKEW_BASE_IDX', + 'mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR', + 'mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR_BASE_IDX', + 'mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA', + 'mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA_BASE_IDX', + 'mmRLC_SPM_SE_SAMPLE_SKEW', 'mmRLC_SPM_SE_SAMPLE_SKEW_BASE_IDX', + 'mmRLC_SPM_THREAD_TRACE_CTRL', + 'mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX', 'mmRLC_SPM_UTCL1_CNTL', + 'mmRLC_SPM_UTCL1_CNTL_BASE_IDX', 'mmRLC_SPM_UTCL1_ERROR_1', + 'mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX', 'mmRLC_SPM_UTCL1_ERROR_2', + 'mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX', 'mmRLC_SPM_VIRT_CTRL', + 'mmRLC_SPM_VIRT_CTRL_BASE_IDX', 'mmRLC_SPM_VIRT_STATUS', + 'mmRLC_SPM_VIRT_STATUS_BASE_IDX', 'mmRLC_SPP_CAM_ADDR', + 'mmRLC_SPP_CAM_ADDR_BASE_IDX', 'mmRLC_SPP_CAM_DATA', + 'mmRLC_SPP_CAM_DATA_BASE_IDX', 'mmRLC_SPP_CAM_EXT_ADDR', + 'mmRLC_SPP_CAM_EXT_ADDR_BASE_IDX', 'mmRLC_SPP_CAM_EXT_DATA', + 'mmRLC_SPP_CAM_EXT_DATA_BASE_IDX', 'mmRLC_SPP_CTRL', + 'mmRLC_SPP_CTRL_BASE_IDX', 'mmRLC_SPP_GLOBAL_SH_ID', + 'mmRLC_SPP_GLOBAL_SH_ID_BASE_IDX', 'mmRLC_SPP_GLOBAL_SH_ID_VALID', + 'mmRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX', + 'mmRLC_SPP_INFLIGHT_RD_ADDR', + 'mmRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX', + 'mmRLC_SPP_INFLIGHT_RD_DATA', + 'mmRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX', 'mmRLC_SPP_PBB_INFO', + 'mmRLC_SPP_PBB_INFO_BASE_IDX', 'mmRLC_SPP_PROF_INFO_1', + 'mmRLC_SPP_PROF_INFO_1_BASE_IDX', 'mmRLC_SPP_PROF_INFO_2', + 'mmRLC_SPP_PROF_INFO_2_BASE_IDX', 'mmRLC_SPP_PVT_LEVEL_MAX', + 'mmRLC_SPP_PVT_LEVEL_MAX_BASE_IDX', 'mmRLC_SPP_PVT_STAT_0', + 'mmRLC_SPP_PVT_STAT_0_BASE_IDX', 'mmRLC_SPP_PVT_STAT_1', + 'mmRLC_SPP_PVT_STAT_1_BASE_IDX', 'mmRLC_SPP_PVT_STAT_2', + 'mmRLC_SPP_PVT_STAT_2_BASE_IDX', 'mmRLC_SPP_PVT_STAT_3', + 'mmRLC_SPP_PVT_STAT_3_BASE_IDX', 'mmRLC_SPP_RESET', + 'mmRLC_SPP_RESET_BASE_IDX', 'mmRLC_SPP_SHADER_PROFILE_EN', + 'mmRLC_SPP_SHADER_PROFILE_EN_BASE_IDX', + 'mmRLC_SPP_SSF_CAPTURE_EN', 'mmRLC_SPP_SSF_CAPTURE_EN_BASE_IDX', + 'mmRLC_SPP_SSF_THRESHOLD_0', 'mmRLC_SPP_SSF_THRESHOLD_0_BASE_IDX', + 'mmRLC_SPP_SSF_THRESHOLD_1', 'mmRLC_SPP_SSF_THRESHOLD_1_BASE_IDX', + 'mmRLC_SPP_SSF_THRESHOLD_2', 'mmRLC_SPP_SSF_THRESHOLD_2_BASE_IDX', + 'mmRLC_SPP_STALL_STATE_UPDATE', + 'mmRLC_SPP_STALL_STATE_UPDATE_BASE_IDX', 'mmRLC_SPP_STATUS', + 'mmRLC_SPP_STATUS_BASE_IDX', 'mmRLC_SRM_ARAM_ADDR', + 'mmRLC_SRM_ARAM_ADDR_BASE_IDX', 'mmRLC_SRM_ARAM_DATA', + 'mmRLC_SRM_ARAM_DATA_BASE_IDX', 'mmRLC_SRM_CNTL', + 'mmRLC_SRM_CNTL_BASE_IDX', 'mmRLC_SRM_DRAM_ADDR', + 'mmRLC_SRM_DRAM_ADDR_BASE_IDX', 'mmRLC_SRM_DRAM_DATA', + 'mmRLC_SRM_DRAM_DATA_BASE_IDX', 'mmRLC_SRM_FWL_FIRST_VIOL_ADDR', + 'mmRLC_SRM_FWL_FIRST_VIOL_ADDR_BASE_IDX', 'mmRLC_SRM_GPM_ABORT', + 'mmRLC_SRM_GPM_ABORT_BASE_IDX', 'mmRLC_SRM_GPM_COMMAND', + 'mmRLC_SRM_GPM_COMMAND_BASE_IDX', 'mmRLC_SRM_GPM_COMMAND_STATUS', + 'mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_ADDR_0', + 'mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_ADDR_1', + 'mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_ADDR_2', + 'mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_ADDR_3', + 'mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_ADDR_4', + 'mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_ADDR_5', + 'mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_ADDR_6', + 'mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_ADDR_7', + 'mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_DATA_0', + 'mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_DATA_1', + 'mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_DATA_2', + 'mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_DATA_3', + 'mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_DATA_4', + 'mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_DATA_5', + 'mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_DATA_6', + 'mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX', + 'mmRLC_SRM_INDEX_CNTL_DATA_7', + 'mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX', 'mmRLC_SRM_RLCV_COMMAND', + 'mmRLC_SRM_RLCV_COMMAND_BASE_IDX', + 'mmRLC_SRM_RLCV_COMMAND_STATUS', + 'mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX', 'mmRLC_SRM_STAT', + 'mmRLC_SRM_STAT_BASE_IDX', 'mmRLC_STAT', 'mmRLC_STATIC_PG_STATUS', + 'mmRLC_STATIC_PG_STATUS_BASE_IDX', 'mmRLC_STAT_BASE_IDX', + 'mmRLC_UCODE_CNTL', 'mmRLC_UCODE_CNTL_BASE_IDX', + 'mmRLC_UTCL1_STATUS', 'mmRLC_UTCL1_STATUS_2', + 'mmRLC_UTCL1_STATUS_2_BASE_IDX', 'mmRLC_UTCL1_STATUS_BASE_IDX', + 'mmRLC_WGP_STATUS', 'mmRLC_WGP_STATUS_BASE_IDX', + 'mmRLC_XT_DOORBELL_0_DATA_HI', + 'mmRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX', + 'mmRLC_XT_DOORBELL_0_DATA_LO', + 'mmRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX', + 'mmRLC_XT_DOORBELL_1_DATA_HI', + 'mmRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX', + 'mmRLC_XT_DOORBELL_1_DATA_LO', + 'mmRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX', + 'mmRLC_XT_DOORBELL_2_DATA_HI', + 'mmRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX', + 'mmRLC_XT_DOORBELL_2_DATA_LO', + 'mmRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX', + 'mmRLC_XT_DOORBELL_3_DATA_HI', + 'mmRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX', + 'mmRLC_XT_DOORBELL_3_DATA_LO', + 'mmRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX', 'mmRLC_XT_DOORBELL_CNTL', + 'mmRLC_XT_DOORBELL_CNTL_BASE_IDX', 'mmRLC_XT_DOORBELL_RANGE', + 'mmRLC_XT_DOORBELL_RANGE_BASE_IDX', 'mmRLC_XT_DOORBELL_STAT', + 'mmRLC_XT_DOORBELL_STAT_BASE_IDX', 'mmRMI_CGTT_SCLK_CTRL', + 'mmRMI_CGTT_SCLK_CTRL_BASE_IDX', 'mmRMI_CLOCK_CNTRL', + 'mmRMI_CLOCK_CNTRL_BASE_IDX', 'mmRMI_DEMUX_CNTL', + 'mmRMI_DEMUX_CNTL_BASE_IDX', 'mmRMI_GENERAL_CNTL', + 'mmRMI_GENERAL_CNTL1', 'mmRMI_GENERAL_CNTL1_BASE_IDX', + 'mmRMI_GENERAL_CNTL_BASE_IDX', 'mmRMI_GENERAL_STATUS', + 'mmRMI_GENERAL_STATUS_BASE_IDX', 'mmRMI_PERFCOUNTER0_HI', + 'mmRMI_PERFCOUNTER0_HI_BASE_IDX', 'mmRMI_PERFCOUNTER0_LO', + 'mmRMI_PERFCOUNTER0_LO_BASE_IDX', 'mmRMI_PERFCOUNTER0_SELECT', + 'mmRMI_PERFCOUNTER0_SELECT1', + 'mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmRMI_PERFCOUNTER0_SELECT_BASE_IDX', 'mmRMI_PERFCOUNTER1_HI', + 'mmRMI_PERFCOUNTER1_HI_BASE_IDX', 'mmRMI_PERFCOUNTER1_LO', + 'mmRMI_PERFCOUNTER1_LO_BASE_IDX', 'mmRMI_PERFCOUNTER1_SELECT', + 'mmRMI_PERFCOUNTER1_SELECT_BASE_IDX', 'mmRMI_PERFCOUNTER2_HI', + 'mmRMI_PERFCOUNTER2_HI_BASE_IDX', 'mmRMI_PERFCOUNTER2_LO', + 'mmRMI_PERFCOUNTER2_LO_BASE_IDX', 'mmRMI_PERFCOUNTER2_SELECT', + 'mmRMI_PERFCOUNTER2_SELECT1', + 'mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX', + 'mmRMI_PERFCOUNTER2_SELECT_BASE_IDX', 'mmRMI_PERFCOUNTER3_HI', + 'mmRMI_PERFCOUNTER3_HI_BASE_IDX', 'mmRMI_PERFCOUNTER3_LO', + 'mmRMI_PERFCOUNTER3_LO_BASE_IDX', 'mmRMI_PERFCOUNTER3_SELECT', + 'mmRMI_PERFCOUNTER3_SELECT_BASE_IDX', 'mmRMI_PERF_COUNTER_CNTL', + 'mmRMI_PERF_COUNTER_CNTL_BASE_IDX', 'mmRMI_PROBE_POP_LOGIC_CNTL', + 'mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX', 'mmRMI_RB_GLX_CID_MAP', + 'mmRMI_RB_GLX_CID_MAP_BASE_IDX', 'mmRMI_SCOREBOARD_CNTL', + 'mmRMI_SCOREBOARD_CNTL_BASE_IDX', 'mmRMI_SCOREBOARD_STATUS0', + 'mmRMI_SCOREBOARD_STATUS0_BASE_IDX', 'mmRMI_SCOREBOARD_STATUS1', + 'mmRMI_SCOREBOARD_STATUS1_BASE_IDX', 'mmRMI_SCOREBOARD_STATUS2', + 'mmRMI_SCOREBOARD_STATUS2_BASE_IDX', 'mmRMI_SPARE', + 'mmRMI_SPARE_1', 'mmRMI_SPARE_1_BASE_IDX', 'mmRMI_SPARE_2', + 'mmRMI_SPARE_2_BASE_IDX', 'mmRMI_SPARE_BASE_IDX', + 'mmRMI_SUBBLOCK_STATUS0', 'mmRMI_SUBBLOCK_STATUS0_BASE_IDX', + 'mmRMI_SUBBLOCK_STATUS1', 'mmRMI_SUBBLOCK_STATUS1_BASE_IDX', + 'mmRMI_SUBBLOCK_STATUS2', 'mmRMI_SUBBLOCK_STATUS2_BASE_IDX', + 'mmRMI_SUBBLOCK_STATUS3', 'mmRMI_SUBBLOCK_STATUS3_BASE_IDX', + 'mmRMI_TCIW_FORMATTER0_CNTL', + 'mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX', + 'mmRMI_TCIW_FORMATTER1_CNTL', + 'mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX', 'mmRMI_UTCL1_CNTL1', + 'mmRMI_UTCL1_CNTL1_BASE_IDX', 'mmRMI_UTCL1_CNTL2', + 'mmRMI_UTCL1_CNTL2_BASE_IDX', 'mmRMI_UTCL1_STATUS', + 'mmRMI_UTCL1_STATUS_BASE_IDX', 'mmRMI_UTC_UNIT_CONFIG', + 'mmRMI_UTC_UNIT_CONFIG_BASE_IDX', 'mmRMI_UTC_XNACK_N_MISC_CNTL', + 'mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX', + 'mmRMI_XBAR_ARBITER_CONFIG', 'mmRMI_XBAR_ARBITER_CONFIG_1', + 'mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX', + 'mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX', 'mmRMI_XBAR_CONFIG', + 'mmRMI_XBAR_CONFIG_BASE_IDX', 'mmRTAVFS_RTAVFS_REG_ADDR', + 'mmRTAVFS_RTAVFS_REG_ADDR_BASE_IDX', 'mmRTAVFS_RTAVFS_WR_DATA', + 'mmRTAVFS_RTAVFS_WR_DATA_BASE_IDX', 'mmSCRATCH_ADDR', + 'mmSCRATCH_ADDR_BASE_IDX', 'mmSCRATCH_REG0', + 'mmSCRATCH_REG0_BASE_IDX', 'mmSCRATCH_REG1', + 'mmSCRATCH_REG1_BASE_IDX', 'mmSCRATCH_REG2', + 'mmSCRATCH_REG2_BASE_IDX', 'mmSCRATCH_REG3', + 'mmSCRATCH_REG3_BASE_IDX', 'mmSCRATCH_REG4', + 'mmSCRATCH_REG4_BASE_IDX', 'mmSCRATCH_REG5', + 'mmSCRATCH_REG5_BASE_IDX', 'mmSCRATCH_REG6', + 'mmSCRATCH_REG6_BASE_IDX', 'mmSCRATCH_REG7', + 'mmSCRATCH_REG7_BASE_IDX', 'mmSCRATCH_REG_ATOMIC', + 'mmSCRATCH_REG_ATOMIC_BASE_IDX', 'mmSCRATCH_REG_CMPSWAP_ATOMIC', + 'mmSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX', 'mmSCRATCH_UMSK', + 'mmSCRATCH_UMSK_BASE_IDX', 'mmSDMA0_ACTIVE_FCN_ID', + 'mmSDMA0_ACTIVE_FCN_ID_BASE_IDX', 'mmSDMA0_AQL_STATUS', + 'mmSDMA0_AQL_STATUS_BASE_IDX', 'mmSDMA0_ATOMIC_CNTL', + 'mmSDMA0_ATOMIC_CNTL_BASE_IDX', 'mmSDMA0_ATOMIC_PREOP_HI', + 'mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX', 'mmSDMA0_ATOMIC_PREOP_LO', + 'mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX', 'mmSDMA0_BA_THRESHOLD', + 'mmSDMA0_BA_THRESHOLD_BASE_IDX', 'mmSDMA0_BROADCAST_UCODE_ADDR', + 'mmSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX', + 'mmSDMA0_BROADCAST_UCODE_DATA', + 'mmSDMA0_BROADCAST_UCODE_DATA_BASE_IDX', 'mmSDMA0_CHICKEN_BITS', + 'mmSDMA0_CHICKEN_BITS_2', 'mmSDMA0_CHICKEN_BITS_2_BASE_IDX', + 'mmSDMA0_CHICKEN_BITS_BASE_IDX', 'mmSDMA0_CLK_CTRL', + 'mmSDMA0_CLK_CTRL_BASE_IDX', 'mmSDMA0_CLOCK_GATING_REG', + 'mmSDMA0_CLOCK_GATING_REG_BASE_IDX', 'mmSDMA0_CNTL', + 'mmSDMA0_CNTL_BASE_IDX', 'mmSDMA0_CONTEXT_REG_TYPE0', + 'mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX', 'mmSDMA0_CONTEXT_REG_TYPE1', + 'mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX', 'mmSDMA0_CONTEXT_REG_TYPE2', + 'mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX', 'mmSDMA0_CONTEXT_REG_TYPE3', + 'mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX', 'mmSDMA0_CRD_CNTL', + 'mmSDMA0_CRD_CNTL_BASE_IDX', 'mmSDMA0_DEC_START', + 'mmSDMA0_DEC_START_BASE_IDX', 'mmSDMA0_EA_DBIT_ADDR_DATA', + 'mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX', + 'mmSDMA0_EA_DBIT_ADDR_INDEX', + 'mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX', 'mmSDMA0_EDC_CONFIG', + 'mmSDMA0_EDC_CONFIG_BASE_IDX', 'mmSDMA0_EDC_COUNTER', + 'mmSDMA0_EDC_COUNTER_BASE_IDX', 'mmSDMA0_EDC_COUNTER_CLEAR', + 'mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX', 'mmSDMA0_ERROR_LOG', + 'mmSDMA0_ERROR_LOG_BASE_IDX', 'mmSDMA0_F32_CNTL', + 'mmSDMA0_F32_CNTL_BASE_IDX', 'mmSDMA0_F32_COUNTER', + 'mmSDMA0_F32_COUNTER_BASE_IDX', 'mmSDMA0_FREEZE', + 'mmSDMA0_FREEZE_BASE_IDX', 'mmSDMA0_GB_ADDR_CONFIG', + 'mmSDMA0_GB_ADDR_CONFIG_BASE_IDX', 'mmSDMA0_GB_ADDR_CONFIG_READ', + 'mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX', + 'mmSDMA0_GFX_CONTEXT_CNTL', 'mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX', + 'mmSDMA0_GFX_CONTEXT_STATUS', + 'mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX', 'mmSDMA0_GFX_CSA_ADDR_HI', + 'mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX', 'mmSDMA0_GFX_CSA_ADDR_LO', + 'mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX', 'mmSDMA0_GFX_DOORBELL', + 'mmSDMA0_GFX_DOORBELL_BASE_IDX', 'mmSDMA0_GFX_DOORBELL_LOG', + 'mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX', + 'mmSDMA0_GFX_DOORBELL_OFFSET', + 'mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_GFX_DUMMY_REG', + 'mmSDMA0_GFX_DUMMY_REG_BASE_IDX', 'mmSDMA0_GFX_IB_BASE_HI', + 'mmSDMA0_GFX_IB_BASE_HI_BASE_IDX', 'mmSDMA0_GFX_IB_BASE_LO', + 'mmSDMA0_GFX_IB_BASE_LO_BASE_IDX', 'mmSDMA0_GFX_IB_CNTL', + 'mmSDMA0_GFX_IB_CNTL_BASE_IDX', 'mmSDMA0_GFX_IB_OFFSET', + 'mmSDMA0_GFX_IB_OFFSET_BASE_IDX', 'mmSDMA0_GFX_IB_RPTR', + 'mmSDMA0_GFX_IB_RPTR_BASE_IDX', 'mmSDMA0_GFX_IB_SIZE', + 'mmSDMA0_GFX_IB_SIZE_BASE_IDX', 'mmSDMA0_GFX_IB_SUB_REMAIN', + 'mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_CNTL', + 'mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA0', + 'mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA1', + 'mmSDMA0_GFX_MIDCMD_DATA10', 'mmSDMA0_GFX_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA2', + 'mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA3', + 'mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA4', + 'mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA5', + 'mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA6', + 'mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA7', + 'mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA8', + 'mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_GFX_MIDCMD_DATA9', + 'mmSDMA0_GFX_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA0_GFX_MINOR_PTR_UPDATE', + 'mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_GFX_PREEMPT', + 'mmSDMA0_GFX_PREEMPT_BASE_IDX', 'mmSDMA0_GFX_RB_AQL_CNTL', + 'mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_GFX_RB_BASE', + 'mmSDMA0_GFX_RB_BASE_BASE_IDX', 'mmSDMA0_GFX_RB_BASE_HI', + 'mmSDMA0_GFX_RB_BASE_HI_BASE_IDX', 'mmSDMA0_GFX_RB_CNTL', + 'mmSDMA0_GFX_RB_CNTL_BASE_IDX', 'mmSDMA0_GFX_RB_RPTR', + 'mmSDMA0_GFX_RB_RPTR_ADDR_HI', + 'mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA0_GFX_RB_RPTR_ADDR_LO', + 'mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA0_GFX_RB_RPTR_BASE_IDX', 'mmSDMA0_GFX_RB_RPTR_HI', + 'mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_GFX_RB_WPTR', + 'mmSDMA0_GFX_RB_WPTR_BASE_IDX', 'mmSDMA0_GFX_RB_WPTR_HI', + 'mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX', + 'mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA0_GFX_RB_WPTR_POLL_CNTL', + 'mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX', 'mmSDMA0_GFX_SKIP_CNTL', + 'mmSDMA0_GFX_SKIP_CNTL_BASE_IDX', 'mmSDMA0_GFX_STATUS', + 'mmSDMA0_GFX_STATUS_BASE_IDX', 'mmSDMA0_GFX_WATERMARK', + 'mmSDMA0_GFX_WATERMARK_BASE_IDX', 'mmSDMA0_GLOBAL_TIMESTAMP_HI', + 'mmSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX', + 'mmSDMA0_GLOBAL_TIMESTAMP_LO', + 'mmSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX', 'mmSDMA0_HBM_PAGE_CONFIG', + 'mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX', 'mmSDMA0_HOLE_ADDR_HI', + 'mmSDMA0_HOLE_ADDR_HI_BASE_IDX', 'mmSDMA0_HOLE_ADDR_LO', + 'mmSDMA0_HOLE_ADDR_LO_BASE_IDX', 'mmSDMA0_IB_OFFSET_FETCH', + 'mmSDMA0_IB_OFFSET_FETCH_BASE_IDX', 'mmSDMA0_ID', + 'mmSDMA0_ID_BASE_IDX', 'mmSDMA0_INT_STATUS', + 'mmSDMA0_INT_STATUS_BASE_IDX', 'mmSDMA0_PAGE_CONTEXT_STATUS', + 'mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA0_PAGE_CSA_ADDR_HI', 'mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA0_PAGE_CSA_ADDR_LO', 'mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA0_PAGE_DOORBELL', 'mmSDMA0_PAGE_DOORBELL_BASE_IDX', + 'mmSDMA0_PAGE_DOORBELL_LOG', 'mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX', + 'mmSDMA0_PAGE_DOORBELL_OFFSET', + 'mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_PAGE_DUMMY_REG', + 'mmSDMA0_PAGE_DUMMY_REG_BASE_IDX', 'mmSDMA0_PAGE_IB_BASE_HI', + 'mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX', 'mmSDMA0_PAGE_IB_BASE_LO', + 'mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX', 'mmSDMA0_PAGE_IB_CNTL', + 'mmSDMA0_PAGE_IB_CNTL_BASE_IDX', 'mmSDMA0_PAGE_IB_OFFSET', + 'mmSDMA0_PAGE_IB_OFFSET_BASE_IDX', 'mmSDMA0_PAGE_IB_RPTR', + 'mmSDMA0_PAGE_IB_RPTR_BASE_IDX', 'mmSDMA0_PAGE_IB_SIZE', + 'mmSDMA0_PAGE_IB_SIZE_BASE_IDX', 'mmSDMA0_PAGE_IB_SUB_REMAIN', + 'mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_CNTL', + 'mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA0', + 'mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA1', + 'mmSDMA0_PAGE_MIDCMD_DATA10', + 'mmSDMA0_PAGE_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA2', + 'mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA3', + 'mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA4', + 'mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA5', + 'mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA6', + 'mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA7', + 'mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA8', + 'mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_PAGE_MIDCMD_DATA9', + 'mmSDMA0_PAGE_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA0_PAGE_MINOR_PTR_UPDATE', + 'mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_PAGE_PREEMPT', + 'mmSDMA0_PAGE_PREEMPT_BASE_IDX', 'mmSDMA0_PAGE_RB_AQL_CNTL', + 'mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_PAGE_RB_BASE', + 'mmSDMA0_PAGE_RB_BASE_BASE_IDX', 'mmSDMA0_PAGE_RB_BASE_HI', + 'mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX', 'mmSDMA0_PAGE_RB_CNTL', + 'mmSDMA0_PAGE_RB_CNTL_BASE_IDX', 'mmSDMA0_PAGE_RB_RPTR', + 'mmSDMA0_PAGE_RB_RPTR_ADDR_HI', + 'mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA0_PAGE_RB_RPTR_ADDR_LO', + 'mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA0_PAGE_RB_RPTR_BASE_IDX', 'mmSDMA0_PAGE_RB_RPTR_HI', + 'mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_PAGE_RB_WPTR', + 'mmSDMA0_PAGE_RB_WPTR_BASE_IDX', 'mmSDMA0_PAGE_RB_WPTR_HI', + 'mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX', + 'mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA0_PAGE_RB_WPTR_POLL_CNTL', + 'mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA0_PAGE_SKIP_CNTL', 'mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX', + 'mmSDMA0_PAGE_STATUS', 'mmSDMA0_PAGE_STATUS_BASE_IDX', + 'mmSDMA0_PAGE_WATERMARK', 'mmSDMA0_PAGE_WATERMARK_BASE_IDX', + 'mmSDMA0_PERFCNT_MISC_CNTL', 'mmSDMA0_PERFCNT_MISC_CNTL_BASE_IDX', + 'mmSDMA0_PERFCNT_PERFCOUNTER0_CFG', + 'mmSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', + 'mmSDMA0_PERFCNT_PERFCOUNTER1_CFG', + 'mmSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', + 'mmSDMA0_PERFCNT_PERFCOUNTER_HI', + 'mmSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX', + 'mmSDMA0_PERFCNT_PERFCOUNTER_LO', + 'mmSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX', + 'mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL', + 'mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'mmSDMA0_PERFCOUNTER0_HI', 'mmSDMA0_PERFCOUNTER0_HI_BASE_IDX', + 'mmSDMA0_PERFCOUNTER0_LO', 'mmSDMA0_PERFCOUNTER0_LO_BASE_IDX', + 'mmSDMA0_PERFCOUNTER0_SELECT', 'mmSDMA0_PERFCOUNTER0_SELECT1', + 'mmSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmSDMA0_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSDMA0_PERFCOUNTER1_HI', + 'mmSDMA0_PERFCOUNTER1_HI_BASE_IDX', 'mmSDMA0_PERFCOUNTER1_LO', + 'mmSDMA0_PERFCOUNTER1_LO_BASE_IDX', 'mmSDMA0_PERFCOUNTER1_SELECT', + 'mmSDMA0_PERFCOUNTER1_SELECT1', + 'mmSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmSDMA0_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSDMA0_PG_CNTL', + 'mmSDMA0_PG_CNTL_BASE_IDX', 'mmSDMA0_PG_CTX_CNTL', + 'mmSDMA0_PG_CTX_CNTL_BASE_IDX', 'mmSDMA0_PG_CTX_HI', + 'mmSDMA0_PG_CTX_HI_BASE_IDX', 'mmSDMA0_PG_CTX_LO', + 'mmSDMA0_PG_CTX_LO_BASE_IDX', 'mmSDMA0_PHASE0_QUANTUM', + 'mmSDMA0_PHASE0_QUANTUM_BASE_IDX', 'mmSDMA0_PHASE1_QUANTUM', + 'mmSDMA0_PHASE1_QUANTUM_BASE_IDX', 'mmSDMA0_PHASE2_QUANTUM', + 'mmSDMA0_PHASE2_QUANTUM_BASE_IDX', 'mmSDMA0_PHYSICAL_ADDR_HI', + 'mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX', 'mmSDMA0_PHYSICAL_ADDR_LO', + 'mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX', 'mmSDMA0_POWER_CNTL', + 'mmSDMA0_POWER_CNTL_BASE_IDX', 'mmSDMA0_PROGRAM', + 'mmSDMA0_PROGRAM_BASE_IDX', 'mmSDMA0_PUB_DUMMY_REG0', + 'mmSDMA0_PUB_DUMMY_REG0_BASE_IDX', 'mmSDMA0_PUB_DUMMY_REG1', + 'mmSDMA0_PUB_DUMMY_REG1_BASE_IDX', 'mmSDMA0_PUB_DUMMY_REG2', + 'mmSDMA0_PUB_DUMMY_REG2_BASE_IDX', 'mmSDMA0_PUB_DUMMY_REG3', + 'mmSDMA0_PUB_DUMMY_REG3_BASE_IDX', 'mmSDMA0_PUB_REG_TYPE0', + 'mmSDMA0_PUB_REG_TYPE0_BASE_IDX', 'mmSDMA0_PUB_REG_TYPE1', + 'mmSDMA0_PUB_REG_TYPE1_BASE_IDX', 'mmSDMA0_PUB_REG_TYPE2', + 'mmSDMA0_PUB_REG_TYPE2_BASE_IDX', 'mmSDMA0_PUB_REG_TYPE3', + 'mmSDMA0_PUB_REG_TYPE3_BASE_IDX', 'mmSDMA0_QUEUE_RESET_REQ', + 'mmSDMA0_QUEUE_RESET_REQ_BASE_IDX', 'mmSDMA0_RB_RPTR_FETCH', + 'mmSDMA0_RB_RPTR_FETCH_BASE_IDX', 'mmSDMA0_RB_RPTR_FETCH_HI', + 'mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX', 'mmSDMA0_RD_BURST_CNTL', + 'mmSDMA0_RD_BURST_CNTL_BASE_IDX', 'mmSDMA0_RELAX_ORDERING_LUT', + 'mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX', + 'mmSDMA0_RLC0_CONTEXT_STATUS', + 'mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA0_RLC0_CSA_ADDR_HI', 'mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC0_CSA_ADDR_LO', 'mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC0_DOORBELL', 'mmSDMA0_RLC0_DOORBELL_BASE_IDX', + 'mmSDMA0_RLC0_DOORBELL_LOG', 'mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX', + 'mmSDMA0_RLC0_DOORBELL_OFFSET', + 'mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC0_DUMMY_REG', + 'mmSDMA0_RLC0_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC0_IB_BASE_HI', + 'mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC0_IB_BASE_LO', + 'mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC0_IB_CNTL', + 'mmSDMA0_RLC0_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC0_IB_OFFSET', + 'mmSDMA0_RLC0_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC0_IB_RPTR', + 'mmSDMA0_RLC0_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC0_IB_SIZE', + 'mmSDMA0_RLC0_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC0_IB_SUB_REMAIN', + 'mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_CNTL', + 'mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA0', + 'mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA1', + 'mmSDMA0_RLC0_MIDCMD_DATA10', + 'mmSDMA0_RLC0_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA2', + 'mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA3', + 'mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA4', + 'mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA5', + 'mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA6', + 'mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA7', + 'mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA8', + 'mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC0_MIDCMD_DATA9', + 'mmSDMA0_RLC0_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA0_RLC0_MINOR_PTR_UPDATE', + 'mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC0_PREEMPT', + 'mmSDMA0_RLC0_PREEMPT_BASE_IDX', 'mmSDMA0_RLC0_RB_AQL_CNTL', + 'mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC0_RB_BASE', + 'mmSDMA0_RLC0_RB_BASE_BASE_IDX', 'mmSDMA0_RLC0_RB_BASE_HI', + 'mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC0_RB_CNTL', + 'mmSDMA0_RLC0_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC0_RB_RPTR', + 'mmSDMA0_RLC0_RB_RPTR_ADDR_HI', + 'mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC0_RB_RPTR_ADDR_LO', + 'mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC0_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC0_RB_RPTR_HI', + 'mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC0_RB_WPTR', + 'mmSDMA0_RLC0_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC0_RB_WPTR_HI', + 'mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX', + 'mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC0_RB_WPTR_POLL_CNTL', + 'mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA0_RLC0_SKIP_CNTL', 'mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX', + 'mmSDMA0_RLC0_STATUS', 'mmSDMA0_RLC0_STATUS_BASE_IDX', + 'mmSDMA0_RLC0_WATERMARK', 'mmSDMA0_RLC0_WATERMARK_BASE_IDX', + 'mmSDMA0_RLC1_CONTEXT_STATUS', + 'mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA0_RLC1_CSA_ADDR_HI', 'mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC1_CSA_ADDR_LO', 'mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC1_DOORBELL', 'mmSDMA0_RLC1_DOORBELL_BASE_IDX', + 'mmSDMA0_RLC1_DOORBELL_LOG', 'mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX', + 'mmSDMA0_RLC1_DOORBELL_OFFSET', + 'mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC1_DUMMY_REG', + 'mmSDMA0_RLC1_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC1_IB_BASE_HI', + 'mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC1_IB_BASE_LO', + 'mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC1_IB_CNTL', + 'mmSDMA0_RLC1_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC1_IB_OFFSET', + 'mmSDMA0_RLC1_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC1_IB_RPTR', + 'mmSDMA0_RLC1_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC1_IB_SIZE', + 'mmSDMA0_RLC1_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC1_IB_SUB_REMAIN', + 'mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_CNTL', + 'mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA0', + 'mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA1', + 'mmSDMA0_RLC1_MIDCMD_DATA10', + 'mmSDMA0_RLC1_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA2', + 'mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA3', + 'mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA4', + 'mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA5', + 'mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA6', + 'mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA7', + 'mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA8', + 'mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC1_MIDCMD_DATA9', + 'mmSDMA0_RLC1_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA0_RLC1_MINOR_PTR_UPDATE', + 'mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC1_PREEMPT', + 'mmSDMA0_RLC1_PREEMPT_BASE_IDX', 'mmSDMA0_RLC1_RB_AQL_CNTL', + 'mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC1_RB_BASE', + 'mmSDMA0_RLC1_RB_BASE_BASE_IDX', 'mmSDMA0_RLC1_RB_BASE_HI', + 'mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC1_RB_CNTL', + 'mmSDMA0_RLC1_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC1_RB_RPTR', + 'mmSDMA0_RLC1_RB_RPTR_ADDR_HI', + 'mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC1_RB_RPTR_ADDR_LO', + 'mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC1_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC1_RB_RPTR_HI', + 'mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC1_RB_WPTR', + 'mmSDMA0_RLC1_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC1_RB_WPTR_HI', + 'mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX', + 'mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC1_RB_WPTR_POLL_CNTL', + 'mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA0_RLC1_SKIP_CNTL', 'mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX', + 'mmSDMA0_RLC1_STATUS', 'mmSDMA0_RLC1_STATUS_BASE_IDX', + 'mmSDMA0_RLC1_WATERMARK', 'mmSDMA0_RLC1_WATERMARK_BASE_IDX', + 'mmSDMA0_RLC2_CONTEXT_STATUS', + 'mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA0_RLC2_CSA_ADDR_HI', 'mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC2_CSA_ADDR_LO', 'mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC2_DOORBELL', 'mmSDMA0_RLC2_DOORBELL_BASE_IDX', + 'mmSDMA0_RLC2_DOORBELL_LOG', 'mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX', + 'mmSDMA0_RLC2_DOORBELL_OFFSET', + 'mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC2_DUMMY_REG', + 'mmSDMA0_RLC2_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC2_IB_BASE_HI', + 'mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC2_IB_BASE_LO', + 'mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC2_IB_CNTL', + 'mmSDMA0_RLC2_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC2_IB_OFFSET', + 'mmSDMA0_RLC2_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC2_IB_RPTR', + 'mmSDMA0_RLC2_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC2_IB_SIZE', + 'mmSDMA0_RLC2_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC2_IB_SUB_REMAIN', + 'mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_CNTL', + 'mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA0', + 'mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA1', + 'mmSDMA0_RLC2_MIDCMD_DATA10', + 'mmSDMA0_RLC2_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA2', + 'mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA3', + 'mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA4', + 'mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA5', + 'mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA6', + 'mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA7', + 'mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA8', + 'mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC2_MIDCMD_DATA9', + 'mmSDMA0_RLC2_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA0_RLC2_MINOR_PTR_UPDATE', + 'mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC2_PREEMPT', + 'mmSDMA0_RLC2_PREEMPT_BASE_IDX', 'mmSDMA0_RLC2_RB_AQL_CNTL', + 'mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC2_RB_BASE', + 'mmSDMA0_RLC2_RB_BASE_BASE_IDX', 'mmSDMA0_RLC2_RB_BASE_HI', + 'mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC2_RB_CNTL', + 'mmSDMA0_RLC2_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC2_RB_RPTR', + 'mmSDMA0_RLC2_RB_RPTR_ADDR_HI', + 'mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC2_RB_RPTR_ADDR_LO', + 'mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC2_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC2_RB_RPTR_HI', + 'mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC2_RB_WPTR', + 'mmSDMA0_RLC2_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC2_RB_WPTR_HI', + 'mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX', + 'mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC2_RB_WPTR_POLL_CNTL', + 'mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA0_RLC2_SKIP_CNTL', 'mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX', + 'mmSDMA0_RLC2_STATUS', 'mmSDMA0_RLC2_STATUS_BASE_IDX', + 'mmSDMA0_RLC2_WATERMARK', 'mmSDMA0_RLC2_WATERMARK_BASE_IDX', + 'mmSDMA0_RLC3_CONTEXT_STATUS', + 'mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA0_RLC3_CSA_ADDR_HI', 'mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC3_CSA_ADDR_LO', 'mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC3_DOORBELL', 'mmSDMA0_RLC3_DOORBELL_BASE_IDX', + 'mmSDMA0_RLC3_DOORBELL_LOG', 'mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX', + 'mmSDMA0_RLC3_DOORBELL_OFFSET', + 'mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC3_DUMMY_REG', + 'mmSDMA0_RLC3_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC3_IB_BASE_HI', + 'mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC3_IB_BASE_LO', + 'mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC3_IB_CNTL', + 'mmSDMA0_RLC3_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC3_IB_OFFSET', + 'mmSDMA0_RLC3_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC3_IB_RPTR', + 'mmSDMA0_RLC3_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC3_IB_SIZE', + 'mmSDMA0_RLC3_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC3_IB_SUB_REMAIN', + 'mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_CNTL', + 'mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA0', + 'mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA1', + 'mmSDMA0_RLC3_MIDCMD_DATA10', + 'mmSDMA0_RLC3_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA2', + 'mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA3', + 'mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA4', + 'mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA5', + 'mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA6', + 'mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA7', + 'mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA8', + 'mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC3_MIDCMD_DATA9', + 'mmSDMA0_RLC3_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA0_RLC3_MINOR_PTR_UPDATE', + 'mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC3_PREEMPT', + 'mmSDMA0_RLC3_PREEMPT_BASE_IDX', 'mmSDMA0_RLC3_RB_AQL_CNTL', + 'mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC3_RB_BASE', + 'mmSDMA0_RLC3_RB_BASE_BASE_IDX', 'mmSDMA0_RLC3_RB_BASE_HI', + 'mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC3_RB_CNTL', + 'mmSDMA0_RLC3_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC3_RB_RPTR', + 'mmSDMA0_RLC3_RB_RPTR_ADDR_HI', + 'mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC3_RB_RPTR_ADDR_LO', + 'mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC3_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC3_RB_RPTR_HI', + 'mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC3_RB_WPTR', + 'mmSDMA0_RLC3_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC3_RB_WPTR_HI', + 'mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX', + 'mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC3_RB_WPTR_POLL_CNTL', + 'mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA0_RLC3_SKIP_CNTL', 'mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX', + 'mmSDMA0_RLC3_STATUS', 'mmSDMA0_RLC3_STATUS_BASE_IDX', + 'mmSDMA0_RLC3_WATERMARK', 'mmSDMA0_RLC3_WATERMARK_BASE_IDX', + 'mmSDMA0_RLC4_CONTEXT_STATUS', + 'mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA0_RLC4_CSA_ADDR_HI', 'mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC4_CSA_ADDR_LO', 'mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC4_DOORBELL', 'mmSDMA0_RLC4_DOORBELL_BASE_IDX', + 'mmSDMA0_RLC4_DOORBELL_LOG', 'mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX', + 'mmSDMA0_RLC4_DOORBELL_OFFSET', + 'mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC4_DUMMY_REG', + 'mmSDMA0_RLC4_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC4_IB_BASE_HI', + 'mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC4_IB_BASE_LO', + 'mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC4_IB_CNTL', + 'mmSDMA0_RLC4_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC4_IB_OFFSET', + 'mmSDMA0_RLC4_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC4_IB_RPTR', + 'mmSDMA0_RLC4_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC4_IB_SIZE', + 'mmSDMA0_RLC4_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC4_IB_SUB_REMAIN', + 'mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_CNTL', + 'mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA0', + 'mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA1', + 'mmSDMA0_RLC4_MIDCMD_DATA10', + 'mmSDMA0_RLC4_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA2', + 'mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA3', + 'mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA4', + 'mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA5', + 'mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA6', + 'mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA7', + 'mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA8', + 'mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC4_MIDCMD_DATA9', + 'mmSDMA0_RLC4_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA0_RLC4_MINOR_PTR_UPDATE', + 'mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC4_PREEMPT', + 'mmSDMA0_RLC4_PREEMPT_BASE_IDX', 'mmSDMA0_RLC4_RB_AQL_CNTL', + 'mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC4_RB_BASE', + 'mmSDMA0_RLC4_RB_BASE_BASE_IDX', 'mmSDMA0_RLC4_RB_BASE_HI', + 'mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC4_RB_CNTL', + 'mmSDMA0_RLC4_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC4_RB_RPTR', + 'mmSDMA0_RLC4_RB_RPTR_ADDR_HI', + 'mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC4_RB_RPTR_ADDR_LO', + 'mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC4_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC4_RB_RPTR_HI', + 'mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC4_RB_WPTR', + 'mmSDMA0_RLC4_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC4_RB_WPTR_HI', + 'mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX', + 'mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC4_RB_WPTR_POLL_CNTL', + 'mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA0_RLC4_SKIP_CNTL', 'mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX', + 'mmSDMA0_RLC4_STATUS', 'mmSDMA0_RLC4_STATUS_BASE_IDX', + 'mmSDMA0_RLC4_WATERMARK', 'mmSDMA0_RLC4_WATERMARK_BASE_IDX', + 'mmSDMA0_RLC5_CONTEXT_STATUS', + 'mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA0_RLC5_CSA_ADDR_HI', 'mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC5_CSA_ADDR_LO', 'mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC5_DOORBELL', 'mmSDMA0_RLC5_DOORBELL_BASE_IDX', + 'mmSDMA0_RLC5_DOORBELL_LOG', 'mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX', + 'mmSDMA0_RLC5_DOORBELL_OFFSET', + 'mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC5_DUMMY_REG', + 'mmSDMA0_RLC5_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC5_IB_BASE_HI', + 'mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC5_IB_BASE_LO', + 'mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC5_IB_CNTL', + 'mmSDMA0_RLC5_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC5_IB_OFFSET', + 'mmSDMA0_RLC5_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC5_IB_RPTR', + 'mmSDMA0_RLC5_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC5_IB_SIZE', + 'mmSDMA0_RLC5_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC5_IB_SUB_REMAIN', + 'mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_CNTL', + 'mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA0', + 'mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA1', + 'mmSDMA0_RLC5_MIDCMD_DATA10', + 'mmSDMA0_RLC5_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA2', + 'mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA3', + 'mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA4', + 'mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA5', + 'mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA6', + 'mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA7', + 'mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA8', + 'mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC5_MIDCMD_DATA9', + 'mmSDMA0_RLC5_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA0_RLC5_MINOR_PTR_UPDATE', + 'mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC5_PREEMPT', + 'mmSDMA0_RLC5_PREEMPT_BASE_IDX', 'mmSDMA0_RLC5_RB_AQL_CNTL', + 'mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC5_RB_BASE', + 'mmSDMA0_RLC5_RB_BASE_BASE_IDX', 'mmSDMA0_RLC5_RB_BASE_HI', + 'mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC5_RB_CNTL', + 'mmSDMA0_RLC5_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC5_RB_RPTR', + 'mmSDMA0_RLC5_RB_RPTR_ADDR_HI', + 'mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC5_RB_RPTR_ADDR_LO', + 'mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC5_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC5_RB_RPTR_HI', + 'mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC5_RB_WPTR', + 'mmSDMA0_RLC5_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC5_RB_WPTR_HI', + 'mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX', + 'mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC5_RB_WPTR_POLL_CNTL', + 'mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA0_RLC5_SKIP_CNTL', 'mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX', + 'mmSDMA0_RLC5_STATUS', 'mmSDMA0_RLC5_STATUS_BASE_IDX', + 'mmSDMA0_RLC5_WATERMARK', 'mmSDMA0_RLC5_WATERMARK_BASE_IDX', + 'mmSDMA0_RLC6_CONTEXT_STATUS', + 'mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA0_RLC6_CSA_ADDR_HI', 'mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC6_CSA_ADDR_LO', 'mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC6_DOORBELL', 'mmSDMA0_RLC6_DOORBELL_BASE_IDX', + 'mmSDMA0_RLC6_DOORBELL_LOG', 'mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX', + 'mmSDMA0_RLC6_DOORBELL_OFFSET', + 'mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC6_DUMMY_REG', + 'mmSDMA0_RLC6_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC6_IB_BASE_HI', + 'mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC6_IB_BASE_LO', + 'mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC6_IB_CNTL', + 'mmSDMA0_RLC6_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC6_IB_OFFSET', + 'mmSDMA0_RLC6_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC6_IB_RPTR', + 'mmSDMA0_RLC6_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC6_IB_SIZE', + 'mmSDMA0_RLC6_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC6_IB_SUB_REMAIN', + 'mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_CNTL', + 'mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA0', + 'mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA1', + 'mmSDMA0_RLC6_MIDCMD_DATA10', + 'mmSDMA0_RLC6_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA2', + 'mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA3', + 'mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA4', + 'mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA5', + 'mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA6', + 'mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA7', + 'mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA8', + 'mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC6_MIDCMD_DATA9', + 'mmSDMA0_RLC6_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA0_RLC6_MINOR_PTR_UPDATE', + 'mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC6_PREEMPT', + 'mmSDMA0_RLC6_PREEMPT_BASE_IDX', 'mmSDMA0_RLC6_RB_AQL_CNTL', + 'mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC6_RB_BASE', + 'mmSDMA0_RLC6_RB_BASE_BASE_IDX', 'mmSDMA0_RLC6_RB_BASE_HI', + 'mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC6_RB_CNTL', + 'mmSDMA0_RLC6_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC6_RB_RPTR', + 'mmSDMA0_RLC6_RB_RPTR_ADDR_HI', + 'mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC6_RB_RPTR_ADDR_LO', + 'mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC6_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC6_RB_RPTR_HI', + 'mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC6_RB_WPTR', + 'mmSDMA0_RLC6_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC6_RB_WPTR_HI', + 'mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX', + 'mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC6_RB_WPTR_POLL_CNTL', + 'mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA0_RLC6_SKIP_CNTL', 'mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX', + 'mmSDMA0_RLC6_STATUS', 'mmSDMA0_RLC6_STATUS_BASE_IDX', + 'mmSDMA0_RLC6_WATERMARK', 'mmSDMA0_RLC6_WATERMARK_BASE_IDX', + 'mmSDMA0_RLC7_CONTEXT_STATUS', + 'mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA0_RLC7_CSA_ADDR_HI', 'mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC7_CSA_ADDR_LO', 'mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC7_DOORBELL', 'mmSDMA0_RLC7_DOORBELL_BASE_IDX', + 'mmSDMA0_RLC7_DOORBELL_LOG', 'mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX', + 'mmSDMA0_RLC7_DOORBELL_OFFSET', + 'mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA0_RLC7_DUMMY_REG', + 'mmSDMA0_RLC7_DUMMY_REG_BASE_IDX', 'mmSDMA0_RLC7_IB_BASE_HI', + 'mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC7_IB_BASE_LO', + 'mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX', 'mmSDMA0_RLC7_IB_CNTL', + 'mmSDMA0_RLC7_IB_CNTL_BASE_IDX', 'mmSDMA0_RLC7_IB_OFFSET', + 'mmSDMA0_RLC7_IB_OFFSET_BASE_IDX', 'mmSDMA0_RLC7_IB_RPTR', + 'mmSDMA0_RLC7_IB_RPTR_BASE_IDX', 'mmSDMA0_RLC7_IB_SIZE', + 'mmSDMA0_RLC7_IB_SIZE_BASE_IDX', 'mmSDMA0_RLC7_IB_SUB_REMAIN', + 'mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_CNTL', + 'mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA0', + 'mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA1', + 'mmSDMA0_RLC7_MIDCMD_DATA10', + 'mmSDMA0_RLC7_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA2', + 'mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA3', + 'mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA4', + 'mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA5', + 'mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA6', + 'mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA7', + 'mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA8', + 'mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX', 'mmSDMA0_RLC7_MIDCMD_DATA9', + 'mmSDMA0_RLC7_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA0_RLC7_MINOR_PTR_UPDATE', + 'mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA0_RLC7_PREEMPT', + 'mmSDMA0_RLC7_PREEMPT_BASE_IDX', 'mmSDMA0_RLC7_RB_AQL_CNTL', + 'mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX', 'mmSDMA0_RLC7_RB_BASE', + 'mmSDMA0_RLC7_RB_BASE_BASE_IDX', 'mmSDMA0_RLC7_RB_BASE_HI', + 'mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX', 'mmSDMA0_RLC7_RB_CNTL', + 'mmSDMA0_RLC7_RB_CNTL_BASE_IDX', 'mmSDMA0_RLC7_RB_RPTR', + 'mmSDMA0_RLC7_RB_RPTR_ADDR_HI', + 'mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC7_RB_RPTR_ADDR_LO', + 'mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC7_RB_RPTR_BASE_IDX', 'mmSDMA0_RLC7_RB_RPTR_HI', + 'mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX', 'mmSDMA0_RLC7_RB_WPTR', + 'mmSDMA0_RLC7_RB_WPTR_BASE_IDX', 'mmSDMA0_RLC7_RB_WPTR_HI', + 'mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX', + 'mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA0_RLC7_RB_WPTR_POLL_CNTL', + 'mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA0_RLC7_SKIP_CNTL', 'mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX', + 'mmSDMA0_RLC7_STATUS', 'mmSDMA0_RLC7_STATUS_BASE_IDX', + 'mmSDMA0_RLC7_WATERMARK', 'mmSDMA0_RLC7_WATERMARK_BASE_IDX', + 'mmSDMA0_SCRATCH_RAM_ADDR', 'mmSDMA0_SCRATCH_RAM_ADDR_BASE_IDX', + 'mmSDMA0_SCRATCH_RAM_DATA', 'mmSDMA0_SCRATCH_RAM_DATA_BASE_IDX', + 'mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL', + 'mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', + 'mmSDMA0_STATUS1_REG', 'mmSDMA0_STATUS1_REG_BASE_IDX', + 'mmSDMA0_STATUS2_REG', 'mmSDMA0_STATUS2_REG_BASE_IDX', + 'mmSDMA0_STATUS3_REG', 'mmSDMA0_STATUS3_REG_BASE_IDX', + 'mmSDMA0_STATUS4_REG', 'mmSDMA0_STATUS4_REG_BASE_IDX', + 'mmSDMA0_STATUS5_REG', 'mmSDMA0_STATUS5_REG_BASE_IDX', + 'mmSDMA0_STATUS_REG', 'mmSDMA0_STATUS_REG_BASE_IDX', + 'mmSDMA0_TILING_CONFIG', 'mmSDMA0_TILING_CONFIG_BASE_IDX', + 'mmSDMA0_TIMESTAMP_CNTL', 'mmSDMA0_TIMESTAMP_CNTL_BASE_IDX', + 'mmSDMA0_TLBI_GCR_CNTL', 'mmSDMA0_TLBI_GCR_CNTL_BASE_IDX', + 'mmSDMA0_UCODE_ADDR', 'mmSDMA0_UCODE_ADDR_BASE_IDX', + 'mmSDMA0_UCODE_CHECKSUM', 'mmSDMA0_UCODE_CHECKSUM_BASE_IDX', + 'mmSDMA0_UCODE_DATA', 'mmSDMA0_UCODE_DATA_BASE_IDX', + 'mmSDMA0_UTCL1_CNTL', 'mmSDMA0_UTCL1_CNTL_BASE_IDX', + 'mmSDMA0_UTCL1_INV0', 'mmSDMA0_UTCL1_INV0_BASE_IDX', + 'mmSDMA0_UTCL1_INV1', 'mmSDMA0_UTCL1_INV1_BASE_IDX', + 'mmSDMA0_UTCL1_INV2', 'mmSDMA0_UTCL1_INV2_BASE_IDX', + 'mmSDMA0_UTCL1_PAGE', 'mmSDMA0_UTCL1_PAGE_BASE_IDX', + 'mmSDMA0_UTCL1_RD_STATUS', 'mmSDMA0_UTCL1_RD_STATUS_BASE_IDX', + 'mmSDMA0_UTCL1_RD_XNACK0', 'mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX', + 'mmSDMA0_UTCL1_RD_XNACK1', 'mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX', + 'mmSDMA0_UTCL1_TIMEOUT', 'mmSDMA0_UTCL1_TIMEOUT_BASE_IDX', + 'mmSDMA0_UTCL1_WATERMK', 'mmSDMA0_UTCL1_WATERMK_BASE_IDX', + 'mmSDMA0_UTCL1_WR_STATUS', 'mmSDMA0_UTCL1_WR_STATUS_BASE_IDX', + 'mmSDMA0_UTCL1_WR_XNACK0', 'mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX', + 'mmSDMA0_UTCL1_WR_XNACK1', 'mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX', + 'mmSDMA0_VERSION', 'mmSDMA0_VERSION_BASE_IDX', + 'mmSDMA0_VF_ENABLE', 'mmSDMA0_VF_ENABLE_BASE_IDX', + 'mmSDMA0_VIRT_RESET_REQ', 'mmSDMA0_VIRT_RESET_REQ_BASE_IDX', + 'mmSDMA0_VM_CNTL', 'mmSDMA0_VM_CNTL_BASE_IDX', + 'mmSDMA0_VM_CTX_CNTL', 'mmSDMA0_VM_CTX_CNTL_BASE_IDX', + 'mmSDMA0_VM_CTX_HI', 'mmSDMA0_VM_CTX_HI_BASE_IDX', + 'mmSDMA0_VM_CTX_LO', 'mmSDMA0_VM_CTX_LO_BASE_IDX', + 'mmSDMA1_ACTIVE_FCN_ID', 'mmSDMA1_ACTIVE_FCN_ID_BASE_IDX', + 'mmSDMA1_AQL_STATUS', 'mmSDMA1_AQL_STATUS_BASE_IDX', + 'mmSDMA1_ATOMIC_CNTL', 'mmSDMA1_ATOMIC_CNTL_BASE_IDX', + 'mmSDMA1_ATOMIC_PREOP_HI', 'mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX', + 'mmSDMA1_ATOMIC_PREOP_LO', 'mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX', + 'mmSDMA1_BA_THRESHOLD', 'mmSDMA1_BA_THRESHOLD_BASE_IDX', + 'mmSDMA1_CHICKEN_BITS', 'mmSDMA1_CHICKEN_BITS_2', + 'mmSDMA1_CHICKEN_BITS_2_BASE_IDX', + 'mmSDMA1_CHICKEN_BITS_BASE_IDX', 'mmSDMA1_CLK_CTRL', + 'mmSDMA1_CLK_CTRL_BASE_IDX', 'mmSDMA1_CLOCK_GATING_REG', + 'mmSDMA1_CLOCK_GATING_REG_BASE_IDX', 'mmSDMA1_CNTL', + 'mmSDMA1_CNTL_BASE_IDX', 'mmSDMA1_CONTEXT_REG_TYPE0', + 'mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX', 'mmSDMA1_CONTEXT_REG_TYPE1', + 'mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX', 'mmSDMA1_CONTEXT_REG_TYPE2', + 'mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX', 'mmSDMA1_CONTEXT_REG_TYPE3', + 'mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX', 'mmSDMA1_CRD_CNTL', + 'mmSDMA1_CRD_CNTL_BASE_IDX', 'mmSDMA1_DEC_START', + 'mmSDMA1_DEC_START_BASE_IDX', 'mmSDMA1_EA_DBIT_ADDR_DATA', + 'mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX', + 'mmSDMA1_EA_DBIT_ADDR_INDEX', + 'mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX', 'mmSDMA1_EDC_CONFIG', + 'mmSDMA1_EDC_CONFIG_BASE_IDX', 'mmSDMA1_EDC_COUNTER', + 'mmSDMA1_EDC_COUNTER_BASE_IDX', 'mmSDMA1_EDC_COUNTER_CLEAR', + 'mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX', 'mmSDMA1_ERROR_LOG', + 'mmSDMA1_ERROR_LOG_BASE_IDX', 'mmSDMA1_F32_CNTL', + 'mmSDMA1_F32_CNTL_BASE_IDX', 'mmSDMA1_F32_COUNTER', + 'mmSDMA1_F32_COUNTER_BASE_IDX', 'mmSDMA1_FREEZE', + 'mmSDMA1_FREEZE_BASE_IDX', 'mmSDMA1_GB_ADDR_CONFIG', + 'mmSDMA1_GB_ADDR_CONFIG_BASE_IDX', 'mmSDMA1_GB_ADDR_CONFIG_READ', + 'mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX', + 'mmSDMA1_GFX_CONTEXT_CNTL', 'mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX', + 'mmSDMA1_GFX_CONTEXT_STATUS', + 'mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX', 'mmSDMA1_GFX_CSA_ADDR_HI', + 'mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX', 'mmSDMA1_GFX_CSA_ADDR_LO', + 'mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX', 'mmSDMA1_GFX_DOORBELL', + 'mmSDMA1_GFX_DOORBELL_BASE_IDX', 'mmSDMA1_GFX_DOORBELL_LOG', + 'mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX', + 'mmSDMA1_GFX_DOORBELL_OFFSET', + 'mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_GFX_DUMMY_REG', + 'mmSDMA1_GFX_DUMMY_REG_BASE_IDX', 'mmSDMA1_GFX_IB_BASE_HI', + 'mmSDMA1_GFX_IB_BASE_HI_BASE_IDX', 'mmSDMA1_GFX_IB_BASE_LO', + 'mmSDMA1_GFX_IB_BASE_LO_BASE_IDX', 'mmSDMA1_GFX_IB_CNTL', + 'mmSDMA1_GFX_IB_CNTL_BASE_IDX', 'mmSDMA1_GFX_IB_OFFSET', + 'mmSDMA1_GFX_IB_OFFSET_BASE_IDX', 'mmSDMA1_GFX_IB_RPTR', + 'mmSDMA1_GFX_IB_RPTR_BASE_IDX', 'mmSDMA1_GFX_IB_SIZE', + 'mmSDMA1_GFX_IB_SIZE_BASE_IDX', 'mmSDMA1_GFX_IB_SUB_REMAIN', + 'mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_CNTL', + 'mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA0', + 'mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA1', + 'mmSDMA1_GFX_MIDCMD_DATA10', 'mmSDMA1_GFX_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA2', + 'mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA3', + 'mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA4', + 'mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA5', + 'mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA6', + 'mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA7', + 'mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA8', + 'mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_GFX_MIDCMD_DATA9', + 'mmSDMA1_GFX_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA1_GFX_MINOR_PTR_UPDATE', + 'mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_GFX_PREEMPT', + 'mmSDMA1_GFX_PREEMPT_BASE_IDX', 'mmSDMA1_GFX_RB_AQL_CNTL', + 'mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_GFX_RB_BASE', + 'mmSDMA1_GFX_RB_BASE_BASE_IDX', 'mmSDMA1_GFX_RB_BASE_HI', + 'mmSDMA1_GFX_RB_BASE_HI_BASE_IDX', 'mmSDMA1_GFX_RB_CNTL', + 'mmSDMA1_GFX_RB_CNTL_BASE_IDX', 'mmSDMA1_GFX_RB_RPTR', + 'mmSDMA1_GFX_RB_RPTR_ADDR_HI', + 'mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA1_GFX_RB_RPTR_ADDR_LO', + 'mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA1_GFX_RB_RPTR_BASE_IDX', 'mmSDMA1_GFX_RB_RPTR_HI', + 'mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_GFX_RB_WPTR', + 'mmSDMA1_GFX_RB_WPTR_BASE_IDX', 'mmSDMA1_GFX_RB_WPTR_HI', + 'mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX', + 'mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA1_GFX_RB_WPTR_POLL_CNTL', + 'mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX', 'mmSDMA1_GFX_SKIP_CNTL', + 'mmSDMA1_GFX_SKIP_CNTL_BASE_IDX', 'mmSDMA1_GFX_STATUS', + 'mmSDMA1_GFX_STATUS_BASE_IDX', 'mmSDMA1_GFX_WATERMARK', + 'mmSDMA1_GFX_WATERMARK_BASE_IDX', 'mmSDMA1_GLOBAL_TIMESTAMP_HI', + 'mmSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX', + 'mmSDMA1_GLOBAL_TIMESTAMP_LO', + 'mmSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX', 'mmSDMA1_HBM_PAGE_CONFIG', + 'mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX', 'mmSDMA1_HOLE_ADDR_HI', + 'mmSDMA1_HOLE_ADDR_HI_BASE_IDX', 'mmSDMA1_HOLE_ADDR_LO', + 'mmSDMA1_HOLE_ADDR_LO_BASE_IDX', 'mmSDMA1_IB_OFFSET_FETCH', + 'mmSDMA1_IB_OFFSET_FETCH_BASE_IDX', 'mmSDMA1_ID', + 'mmSDMA1_ID_BASE_IDX', 'mmSDMA1_INT_STATUS', + 'mmSDMA1_INT_STATUS_BASE_IDX', 'mmSDMA1_PAGE_CONTEXT_STATUS', + 'mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA1_PAGE_CSA_ADDR_HI', 'mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA1_PAGE_CSA_ADDR_LO', 'mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA1_PAGE_DOORBELL', 'mmSDMA1_PAGE_DOORBELL_BASE_IDX', + 'mmSDMA1_PAGE_DOORBELL_LOG', 'mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX', + 'mmSDMA1_PAGE_DOORBELL_OFFSET', + 'mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_PAGE_DUMMY_REG', + 'mmSDMA1_PAGE_DUMMY_REG_BASE_IDX', 'mmSDMA1_PAGE_IB_BASE_HI', + 'mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX', 'mmSDMA1_PAGE_IB_BASE_LO', + 'mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX', 'mmSDMA1_PAGE_IB_CNTL', + 'mmSDMA1_PAGE_IB_CNTL_BASE_IDX', 'mmSDMA1_PAGE_IB_OFFSET', + 'mmSDMA1_PAGE_IB_OFFSET_BASE_IDX', 'mmSDMA1_PAGE_IB_RPTR', + 'mmSDMA1_PAGE_IB_RPTR_BASE_IDX', 'mmSDMA1_PAGE_IB_SIZE', + 'mmSDMA1_PAGE_IB_SIZE_BASE_IDX', 'mmSDMA1_PAGE_IB_SUB_REMAIN', + 'mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_CNTL', + 'mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA0', + 'mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA1', + 'mmSDMA1_PAGE_MIDCMD_DATA10', + 'mmSDMA1_PAGE_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA2', + 'mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA3', + 'mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA4', + 'mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA5', + 'mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA6', + 'mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA7', + 'mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA8', + 'mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_PAGE_MIDCMD_DATA9', + 'mmSDMA1_PAGE_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA1_PAGE_MINOR_PTR_UPDATE', + 'mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_PAGE_PREEMPT', + 'mmSDMA1_PAGE_PREEMPT_BASE_IDX', 'mmSDMA1_PAGE_RB_AQL_CNTL', + 'mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_PAGE_RB_BASE', + 'mmSDMA1_PAGE_RB_BASE_BASE_IDX', 'mmSDMA1_PAGE_RB_BASE_HI', + 'mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX', 'mmSDMA1_PAGE_RB_CNTL', + 'mmSDMA1_PAGE_RB_CNTL_BASE_IDX', 'mmSDMA1_PAGE_RB_RPTR', + 'mmSDMA1_PAGE_RB_RPTR_ADDR_HI', + 'mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA1_PAGE_RB_RPTR_ADDR_LO', + 'mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA1_PAGE_RB_RPTR_BASE_IDX', 'mmSDMA1_PAGE_RB_RPTR_HI', + 'mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_PAGE_RB_WPTR', + 'mmSDMA1_PAGE_RB_WPTR_BASE_IDX', 'mmSDMA1_PAGE_RB_WPTR_HI', + 'mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX', + 'mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA1_PAGE_RB_WPTR_POLL_CNTL', + 'mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA1_PAGE_SKIP_CNTL', 'mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX', + 'mmSDMA1_PAGE_STATUS', 'mmSDMA1_PAGE_STATUS_BASE_IDX', + 'mmSDMA1_PAGE_WATERMARK', 'mmSDMA1_PAGE_WATERMARK_BASE_IDX', + 'mmSDMA1_PERFCNT_MISC_CNTL', 'mmSDMA1_PERFCNT_MISC_CNTL_BASE_IDX', + 'mmSDMA1_PERFCNT_PERFCOUNTER0_CFG', + 'mmSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', + 'mmSDMA1_PERFCNT_PERFCOUNTER1_CFG', + 'mmSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', + 'mmSDMA1_PERFCNT_PERFCOUNTER_HI', + 'mmSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX', + 'mmSDMA1_PERFCNT_PERFCOUNTER_LO', + 'mmSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX', + 'mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL', + 'mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'mmSDMA1_PERFCOUNTER0_HI', 'mmSDMA1_PERFCOUNTER0_HI_BASE_IDX', + 'mmSDMA1_PERFCOUNTER0_LO', 'mmSDMA1_PERFCOUNTER0_LO_BASE_IDX', + 'mmSDMA1_PERFCOUNTER0_SELECT', 'mmSDMA1_PERFCOUNTER0_SELECT1', + 'mmSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmSDMA1_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSDMA1_PERFCOUNTER1_HI', + 'mmSDMA1_PERFCOUNTER1_HI_BASE_IDX', 'mmSDMA1_PERFCOUNTER1_LO', + 'mmSDMA1_PERFCOUNTER1_LO_BASE_IDX', 'mmSDMA1_PERFCOUNTER1_SELECT', + 'mmSDMA1_PERFCOUNTER1_SELECT1', + 'mmSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmSDMA1_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSDMA1_PG_CNTL', + 'mmSDMA1_PG_CNTL_BASE_IDX', 'mmSDMA1_PG_CTX_CNTL', + 'mmSDMA1_PG_CTX_CNTL_BASE_IDX', 'mmSDMA1_PG_CTX_HI', + 'mmSDMA1_PG_CTX_HI_BASE_IDX', 'mmSDMA1_PG_CTX_LO', + 'mmSDMA1_PG_CTX_LO_BASE_IDX', 'mmSDMA1_PHASE0_QUANTUM', + 'mmSDMA1_PHASE0_QUANTUM_BASE_IDX', 'mmSDMA1_PHASE1_QUANTUM', + 'mmSDMA1_PHASE1_QUANTUM_BASE_IDX', 'mmSDMA1_PHASE2_QUANTUM', + 'mmSDMA1_PHASE2_QUANTUM_BASE_IDX', 'mmSDMA1_PHYSICAL_ADDR_HI', + 'mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX', 'mmSDMA1_PHYSICAL_ADDR_LO', + 'mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX', 'mmSDMA1_POWER_CNTL', + 'mmSDMA1_POWER_CNTL_BASE_IDX', 'mmSDMA1_PROGRAM', + 'mmSDMA1_PROGRAM_BASE_IDX', 'mmSDMA1_PUB_DUMMY_REG0', + 'mmSDMA1_PUB_DUMMY_REG0_BASE_IDX', 'mmSDMA1_PUB_DUMMY_REG1', + 'mmSDMA1_PUB_DUMMY_REG1_BASE_IDX', 'mmSDMA1_PUB_DUMMY_REG2', + 'mmSDMA1_PUB_DUMMY_REG2_BASE_IDX', 'mmSDMA1_PUB_DUMMY_REG3', + 'mmSDMA1_PUB_DUMMY_REG3_BASE_IDX', 'mmSDMA1_PUB_REG_TYPE0', + 'mmSDMA1_PUB_REG_TYPE0_BASE_IDX', 'mmSDMA1_PUB_REG_TYPE1', + 'mmSDMA1_PUB_REG_TYPE1_BASE_IDX', 'mmSDMA1_PUB_REG_TYPE2', + 'mmSDMA1_PUB_REG_TYPE2_BASE_IDX', 'mmSDMA1_PUB_REG_TYPE3', + 'mmSDMA1_PUB_REG_TYPE3_BASE_IDX', 'mmSDMA1_QUEUE_RESET_REQ', + 'mmSDMA1_QUEUE_RESET_REQ_BASE_IDX', 'mmSDMA1_RB_RPTR_FETCH', + 'mmSDMA1_RB_RPTR_FETCH_BASE_IDX', 'mmSDMA1_RB_RPTR_FETCH_HI', + 'mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX', 'mmSDMA1_RD_BURST_CNTL', + 'mmSDMA1_RD_BURST_CNTL_BASE_IDX', 'mmSDMA1_RELAX_ORDERING_LUT', + 'mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX', + 'mmSDMA1_RLC0_CONTEXT_STATUS', + 'mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA1_RLC0_CSA_ADDR_HI', 'mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC0_CSA_ADDR_LO', 'mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC0_DOORBELL', 'mmSDMA1_RLC0_DOORBELL_BASE_IDX', + 'mmSDMA1_RLC0_DOORBELL_LOG', 'mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX', + 'mmSDMA1_RLC0_DOORBELL_OFFSET', + 'mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC0_DUMMY_REG', + 'mmSDMA1_RLC0_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC0_IB_BASE_HI', + 'mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC0_IB_BASE_LO', + 'mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC0_IB_CNTL', + 'mmSDMA1_RLC0_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC0_IB_OFFSET', + 'mmSDMA1_RLC0_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC0_IB_RPTR', + 'mmSDMA1_RLC0_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC0_IB_SIZE', + 'mmSDMA1_RLC0_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC0_IB_SUB_REMAIN', + 'mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_CNTL', + 'mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA0', + 'mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA1', + 'mmSDMA1_RLC0_MIDCMD_DATA10', + 'mmSDMA1_RLC0_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA2', + 'mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA3', + 'mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA4', + 'mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA5', + 'mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA6', + 'mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA7', + 'mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA8', + 'mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC0_MIDCMD_DATA9', + 'mmSDMA1_RLC0_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA1_RLC0_MINOR_PTR_UPDATE', + 'mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC0_PREEMPT', + 'mmSDMA1_RLC0_PREEMPT_BASE_IDX', 'mmSDMA1_RLC0_RB_AQL_CNTL', + 'mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC0_RB_BASE', + 'mmSDMA1_RLC0_RB_BASE_BASE_IDX', 'mmSDMA1_RLC0_RB_BASE_HI', + 'mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC0_RB_CNTL', + 'mmSDMA1_RLC0_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC0_RB_RPTR', + 'mmSDMA1_RLC0_RB_RPTR_ADDR_HI', + 'mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC0_RB_RPTR_ADDR_LO', + 'mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC0_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC0_RB_RPTR_HI', + 'mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC0_RB_WPTR', + 'mmSDMA1_RLC0_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC0_RB_WPTR_HI', + 'mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX', + 'mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC0_RB_WPTR_POLL_CNTL', + 'mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA1_RLC0_SKIP_CNTL', 'mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX', + 'mmSDMA1_RLC0_STATUS', 'mmSDMA1_RLC0_STATUS_BASE_IDX', + 'mmSDMA1_RLC0_WATERMARK', 'mmSDMA1_RLC0_WATERMARK_BASE_IDX', + 'mmSDMA1_RLC1_CONTEXT_STATUS', + 'mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA1_RLC1_CSA_ADDR_HI', 'mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC1_CSA_ADDR_LO', 'mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC1_DOORBELL', 'mmSDMA1_RLC1_DOORBELL_BASE_IDX', + 'mmSDMA1_RLC1_DOORBELL_LOG', 'mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX', + 'mmSDMA1_RLC1_DOORBELL_OFFSET', + 'mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC1_DUMMY_REG', + 'mmSDMA1_RLC1_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC1_IB_BASE_HI', + 'mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC1_IB_BASE_LO', + 'mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC1_IB_CNTL', + 'mmSDMA1_RLC1_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC1_IB_OFFSET', + 'mmSDMA1_RLC1_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC1_IB_RPTR', + 'mmSDMA1_RLC1_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC1_IB_SIZE', + 'mmSDMA1_RLC1_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC1_IB_SUB_REMAIN', + 'mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_CNTL', + 'mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA0', + 'mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA1', + 'mmSDMA1_RLC1_MIDCMD_DATA10', + 'mmSDMA1_RLC1_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA2', + 'mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA3', + 'mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA4', + 'mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA5', + 'mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA6', + 'mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA7', + 'mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA8', + 'mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC1_MIDCMD_DATA9', + 'mmSDMA1_RLC1_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA1_RLC1_MINOR_PTR_UPDATE', + 'mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC1_PREEMPT', + 'mmSDMA1_RLC1_PREEMPT_BASE_IDX', 'mmSDMA1_RLC1_RB_AQL_CNTL', + 'mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC1_RB_BASE', + 'mmSDMA1_RLC1_RB_BASE_BASE_IDX', 'mmSDMA1_RLC1_RB_BASE_HI', + 'mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC1_RB_CNTL', + 'mmSDMA1_RLC1_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC1_RB_RPTR', + 'mmSDMA1_RLC1_RB_RPTR_ADDR_HI', + 'mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC1_RB_RPTR_ADDR_LO', + 'mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC1_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC1_RB_RPTR_HI', + 'mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC1_RB_WPTR', + 'mmSDMA1_RLC1_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC1_RB_WPTR_HI', + 'mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX', + 'mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC1_RB_WPTR_POLL_CNTL', + 'mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA1_RLC1_SKIP_CNTL', 'mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX', + 'mmSDMA1_RLC1_STATUS', 'mmSDMA1_RLC1_STATUS_BASE_IDX', + 'mmSDMA1_RLC1_WATERMARK', 'mmSDMA1_RLC1_WATERMARK_BASE_IDX', + 'mmSDMA1_RLC2_CONTEXT_STATUS', + 'mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA1_RLC2_CSA_ADDR_HI', 'mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC2_CSA_ADDR_LO', 'mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC2_DOORBELL', 'mmSDMA1_RLC2_DOORBELL_BASE_IDX', + 'mmSDMA1_RLC2_DOORBELL_LOG', 'mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX', + 'mmSDMA1_RLC2_DOORBELL_OFFSET', + 'mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC2_DUMMY_REG', + 'mmSDMA1_RLC2_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC2_IB_BASE_HI', + 'mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC2_IB_BASE_LO', + 'mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC2_IB_CNTL', + 'mmSDMA1_RLC2_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC2_IB_OFFSET', + 'mmSDMA1_RLC2_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC2_IB_RPTR', + 'mmSDMA1_RLC2_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC2_IB_SIZE', + 'mmSDMA1_RLC2_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC2_IB_SUB_REMAIN', + 'mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_CNTL', + 'mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA0', + 'mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA1', + 'mmSDMA1_RLC2_MIDCMD_DATA10', + 'mmSDMA1_RLC2_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA2', + 'mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA3', + 'mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA4', + 'mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA5', + 'mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA6', + 'mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA7', + 'mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA8', + 'mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC2_MIDCMD_DATA9', + 'mmSDMA1_RLC2_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA1_RLC2_MINOR_PTR_UPDATE', + 'mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC2_PREEMPT', + 'mmSDMA1_RLC2_PREEMPT_BASE_IDX', 'mmSDMA1_RLC2_RB_AQL_CNTL', + 'mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC2_RB_BASE', + 'mmSDMA1_RLC2_RB_BASE_BASE_IDX', 'mmSDMA1_RLC2_RB_BASE_HI', + 'mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC2_RB_CNTL', + 'mmSDMA1_RLC2_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC2_RB_RPTR', + 'mmSDMA1_RLC2_RB_RPTR_ADDR_HI', + 'mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC2_RB_RPTR_ADDR_LO', + 'mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC2_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC2_RB_RPTR_HI', + 'mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC2_RB_WPTR', + 'mmSDMA1_RLC2_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC2_RB_WPTR_HI', + 'mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX', + 'mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC2_RB_WPTR_POLL_CNTL', + 'mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA1_RLC2_SKIP_CNTL', 'mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX', + 'mmSDMA1_RLC2_STATUS', 'mmSDMA1_RLC2_STATUS_BASE_IDX', + 'mmSDMA1_RLC2_WATERMARK', 'mmSDMA1_RLC2_WATERMARK_BASE_IDX', + 'mmSDMA1_RLC3_CONTEXT_STATUS', + 'mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA1_RLC3_CSA_ADDR_HI', 'mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC3_CSA_ADDR_LO', 'mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC3_DOORBELL', 'mmSDMA1_RLC3_DOORBELL_BASE_IDX', + 'mmSDMA1_RLC3_DOORBELL_LOG', 'mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX', + 'mmSDMA1_RLC3_DOORBELL_OFFSET', + 'mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC3_DUMMY_REG', + 'mmSDMA1_RLC3_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC3_IB_BASE_HI', + 'mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC3_IB_BASE_LO', + 'mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC3_IB_CNTL', + 'mmSDMA1_RLC3_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC3_IB_OFFSET', + 'mmSDMA1_RLC3_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC3_IB_RPTR', + 'mmSDMA1_RLC3_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC3_IB_SIZE', + 'mmSDMA1_RLC3_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC3_IB_SUB_REMAIN', + 'mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_CNTL', + 'mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA0', + 'mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA1', + 'mmSDMA1_RLC3_MIDCMD_DATA10', + 'mmSDMA1_RLC3_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA2', + 'mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA3', + 'mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA4', + 'mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA5', + 'mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA6', + 'mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA7', + 'mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA8', + 'mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC3_MIDCMD_DATA9', + 'mmSDMA1_RLC3_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA1_RLC3_MINOR_PTR_UPDATE', + 'mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC3_PREEMPT', + 'mmSDMA1_RLC3_PREEMPT_BASE_IDX', 'mmSDMA1_RLC3_RB_AQL_CNTL', + 'mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC3_RB_BASE', + 'mmSDMA1_RLC3_RB_BASE_BASE_IDX', 'mmSDMA1_RLC3_RB_BASE_HI', + 'mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC3_RB_CNTL', + 'mmSDMA1_RLC3_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC3_RB_RPTR', + 'mmSDMA1_RLC3_RB_RPTR_ADDR_HI', + 'mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC3_RB_RPTR_ADDR_LO', + 'mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC3_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC3_RB_RPTR_HI', + 'mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC3_RB_WPTR', + 'mmSDMA1_RLC3_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC3_RB_WPTR_HI', + 'mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX', + 'mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC3_RB_WPTR_POLL_CNTL', + 'mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA1_RLC3_SKIP_CNTL', 'mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX', + 'mmSDMA1_RLC3_STATUS', 'mmSDMA1_RLC3_STATUS_BASE_IDX', + 'mmSDMA1_RLC3_WATERMARK', 'mmSDMA1_RLC3_WATERMARK_BASE_IDX', + 'mmSDMA1_RLC4_CONTEXT_STATUS', + 'mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA1_RLC4_CSA_ADDR_HI', 'mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC4_CSA_ADDR_LO', 'mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC4_DOORBELL', 'mmSDMA1_RLC4_DOORBELL_BASE_IDX', + 'mmSDMA1_RLC4_DOORBELL_LOG', 'mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX', + 'mmSDMA1_RLC4_DOORBELL_OFFSET', + 'mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC4_DUMMY_REG', + 'mmSDMA1_RLC4_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC4_IB_BASE_HI', + 'mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC4_IB_BASE_LO', + 'mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC4_IB_CNTL', + 'mmSDMA1_RLC4_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC4_IB_OFFSET', + 'mmSDMA1_RLC4_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC4_IB_RPTR', + 'mmSDMA1_RLC4_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC4_IB_SIZE', + 'mmSDMA1_RLC4_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC4_IB_SUB_REMAIN', + 'mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_CNTL', + 'mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA0', + 'mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA1', + 'mmSDMA1_RLC4_MIDCMD_DATA10', + 'mmSDMA1_RLC4_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA2', + 'mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA3', + 'mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA4', + 'mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA5', + 'mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA6', + 'mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA7', + 'mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA8', + 'mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC4_MIDCMD_DATA9', + 'mmSDMA1_RLC4_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA1_RLC4_MINOR_PTR_UPDATE', + 'mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC4_PREEMPT', + 'mmSDMA1_RLC4_PREEMPT_BASE_IDX', 'mmSDMA1_RLC4_RB_AQL_CNTL', + 'mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC4_RB_BASE', + 'mmSDMA1_RLC4_RB_BASE_BASE_IDX', 'mmSDMA1_RLC4_RB_BASE_HI', + 'mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC4_RB_CNTL', + 'mmSDMA1_RLC4_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC4_RB_RPTR', + 'mmSDMA1_RLC4_RB_RPTR_ADDR_HI', + 'mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC4_RB_RPTR_ADDR_LO', + 'mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC4_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC4_RB_RPTR_HI', + 'mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC4_RB_WPTR', + 'mmSDMA1_RLC4_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC4_RB_WPTR_HI', + 'mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX', + 'mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC4_RB_WPTR_POLL_CNTL', + 'mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA1_RLC4_SKIP_CNTL', 'mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX', + 'mmSDMA1_RLC4_STATUS', 'mmSDMA1_RLC4_STATUS_BASE_IDX', + 'mmSDMA1_RLC4_WATERMARK', 'mmSDMA1_RLC4_WATERMARK_BASE_IDX', + 'mmSDMA1_RLC5_CONTEXT_STATUS', + 'mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA1_RLC5_CSA_ADDR_HI', 'mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC5_CSA_ADDR_LO', 'mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC5_DOORBELL', 'mmSDMA1_RLC5_DOORBELL_BASE_IDX', + 'mmSDMA1_RLC5_DOORBELL_LOG', 'mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX', + 'mmSDMA1_RLC5_DOORBELL_OFFSET', + 'mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC5_DUMMY_REG', + 'mmSDMA1_RLC5_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC5_IB_BASE_HI', + 'mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC5_IB_BASE_LO', + 'mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC5_IB_CNTL', + 'mmSDMA1_RLC5_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC5_IB_OFFSET', + 'mmSDMA1_RLC5_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC5_IB_RPTR', + 'mmSDMA1_RLC5_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC5_IB_SIZE', + 'mmSDMA1_RLC5_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC5_IB_SUB_REMAIN', + 'mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_CNTL', + 'mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA0', + 'mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA1', + 'mmSDMA1_RLC5_MIDCMD_DATA10', + 'mmSDMA1_RLC5_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA2', + 'mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA3', + 'mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA4', + 'mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA5', + 'mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA6', + 'mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA7', + 'mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA8', + 'mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC5_MIDCMD_DATA9', + 'mmSDMA1_RLC5_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA1_RLC5_MINOR_PTR_UPDATE', + 'mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC5_PREEMPT', + 'mmSDMA1_RLC5_PREEMPT_BASE_IDX', 'mmSDMA1_RLC5_RB_AQL_CNTL', + 'mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC5_RB_BASE', + 'mmSDMA1_RLC5_RB_BASE_BASE_IDX', 'mmSDMA1_RLC5_RB_BASE_HI', + 'mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC5_RB_CNTL', + 'mmSDMA1_RLC5_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC5_RB_RPTR', + 'mmSDMA1_RLC5_RB_RPTR_ADDR_HI', + 'mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC5_RB_RPTR_ADDR_LO', + 'mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC5_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC5_RB_RPTR_HI', + 'mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC5_RB_WPTR', + 'mmSDMA1_RLC5_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC5_RB_WPTR_HI', + 'mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX', + 'mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC5_RB_WPTR_POLL_CNTL', + 'mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA1_RLC5_SKIP_CNTL', 'mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX', + 'mmSDMA1_RLC5_STATUS', 'mmSDMA1_RLC5_STATUS_BASE_IDX', + 'mmSDMA1_RLC5_WATERMARK', 'mmSDMA1_RLC5_WATERMARK_BASE_IDX', + 'mmSDMA1_RLC6_CONTEXT_STATUS', + 'mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA1_RLC6_CSA_ADDR_HI', 'mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC6_CSA_ADDR_LO', 'mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC6_DOORBELL', 'mmSDMA1_RLC6_DOORBELL_BASE_IDX', + 'mmSDMA1_RLC6_DOORBELL_LOG', 'mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX', + 'mmSDMA1_RLC6_DOORBELL_OFFSET', + 'mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC6_DUMMY_REG', + 'mmSDMA1_RLC6_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC6_IB_BASE_HI', + 'mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC6_IB_BASE_LO', + 'mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC6_IB_CNTL', + 'mmSDMA1_RLC6_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC6_IB_OFFSET', + 'mmSDMA1_RLC6_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC6_IB_RPTR', + 'mmSDMA1_RLC6_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC6_IB_SIZE', + 'mmSDMA1_RLC6_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC6_IB_SUB_REMAIN', + 'mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_CNTL', + 'mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA0', + 'mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA1', + 'mmSDMA1_RLC6_MIDCMD_DATA10', + 'mmSDMA1_RLC6_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA2', + 'mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA3', + 'mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA4', + 'mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA5', + 'mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA6', + 'mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA7', + 'mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA8', + 'mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC6_MIDCMD_DATA9', + 'mmSDMA1_RLC6_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA1_RLC6_MINOR_PTR_UPDATE', + 'mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC6_PREEMPT', + 'mmSDMA1_RLC6_PREEMPT_BASE_IDX', 'mmSDMA1_RLC6_RB_AQL_CNTL', + 'mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC6_RB_BASE', + 'mmSDMA1_RLC6_RB_BASE_BASE_IDX', 'mmSDMA1_RLC6_RB_BASE_HI', + 'mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC6_RB_CNTL', + 'mmSDMA1_RLC6_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC6_RB_RPTR', + 'mmSDMA1_RLC6_RB_RPTR_ADDR_HI', + 'mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC6_RB_RPTR_ADDR_LO', + 'mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC6_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC6_RB_RPTR_HI', + 'mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC6_RB_WPTR', + 'mmSDMA1_RLC6_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC6_RB_WPTR_HI', + 'mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX', + 'mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC6_RB_WPTR_POLL_CNTL', + 'mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA1_RLC6_SKIP_CNTL', 'mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX', + 'mmSDMA1_RLC6_STATUS', 'mmSDMA1_RLC6_STATUS_BASE_IDX', + 'mmSDMA1_RLC6_WATERMARK', 'mmSDMA1_RLC6_WATERMARK_BASE_IDX', + 'mmSDMA1_RLC7_CONTEXT_STATUS', + 'mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA1_RLC7_CSA_ADDR_HI', 'mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC7_CSA_ADDR_LO', 'mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC7_DOORBELL', 'mmSDMA1_RLC7_DOORBELL_BASE_IDX', + 'mmSDMA1_RLC7_DOORBELL_LOG', 'mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX', + 'mmSDMA1_RLC7_DOORBELL_OFFSET', + 'mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA1_RLC7_DUMMY_REG', + 'mmSDMA1_RLC7_DUMMY_REG_BASE_IDX', 'mmSDMA1_RLC7_IB_BASE_HI', + 'mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC7_IB_BASE_LO', + 'mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX', 'mmSDMA1_RLC7_IB_CNTL', + 'mmSDMA1_RLC7_IB_CNTL_BASE_IDX', 'mmSDMA1_RLC7_IB_OFFSET', + 'mmSDMA1_RLC7_IB_OFFSET_BASE_IDX', 'mmSDMA1_RLC7_IB_RPTR', + 'mmSDMA1_RLC7_IB_RPTR_BASE_IDX', 'mmSDMA1_RLC7_IB_SIZE', + 'mmSDMA1_RLC7_IB_SIZE_BASE_IDX', 'mmSDMA1_RLC7_IB_SUB_REMAIN', + 'mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_CNTL', + 'mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA0', + 'mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA1', + 'mmSDMA1_RLC7_MIDCMD_DATA10', + 'mmSDMA1_RLC7_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA2', + 'mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA3', + 'mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA4', + 'mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA5', + 'mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA6', + 'mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA7', + 'mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA8', + 'mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX', 'mmSDMA1_RLC7_MIDCMD_DATA9', + 'mmSDMA1_RLC7_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA1_RLC7_MINOR_PTR_UPDATE', + 'mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA1_RLC7_PREEMPT', + 'mmSDMA1_RLC7_PREEMPT_BASE_IDX', 'mmSDMA1_RLC7_RB_AQL_CNTL', + 'mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX', 'mmSDMA1_RLC7_RB_BASE', + 'mmSDMA1_RLC7_RB_BASE_BASE_IDX', 'mmSDMA1_RLC7_RB_BASE_HI', + 'mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX', 'mmSDMA1_RLC7_RB_CNTL', + 'mmSDMA1_RLC7_RB_CNTL_BASE_IDX', 'mmSDMA1_RLC7_RB_RPTR', + 'mmSDMA1_RLC7_RB_RPTR_ADDR_HI', + 'mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC7_RB_RPTR_ADDR_LO', + 'mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC7_RB_RPTR_BASE_IDX', 'mmSDMA1_RLC7_RB_RPTR_HI', + 'mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX', 'mmSDMA1_RLC7_RB_WPTR', + 'mmSDMA1_RLC7_RB_WPTR_BASE_IDX', 'mmSDMA1_RLC7_RB_WPTR_HI', + 'mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX', + 'mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA1_RLC7_RB_WPTR_POLL_CNTL', + 'mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA1_RLC7_SKIP_CNTL', 'mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX', + 'mmSDMA1_RLC7_STATUS', 'mmSDMA1_RLC7_STATUS_BASE_IDX', + 'mmSDMA1_RLC7_WATERMARK', 'mmSDMA1_RLC7_WATERMARK_BASE_IDX', + 'mmSDMA1_SCRATCH_RAM_ADDR', 'mmSDMA1_SCRATCH_RAM_ADDR_BASE_IDX', + 'mmSDMA1_SCRATCH_RAM_DATA', 'mmSDMA1_SCRATCH_RAM_DATA_BASE_IDX', + 'mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL', + 'mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', + 'mmSDMA1_STATUS1_REG', 'mmSDMA1_STATUS1_REG_BASE_IDX', + 'mmSDMA1_STATUS2_REG', 'mmSDMA1_STATUS2_REG_BASE_IDX', + 'mmSDMA1_STATUS3_REG', 'mmSDMA1_STATUS3_REG_BASE_IDX', + 'mmSDMA1_STATUS4_REG', 'mmSDMA1_STATUS4_REG_BASE_IDX', + 'mmSDMA1_STATUS5_REG', 'mmSDMA1_STATUS5_REG_BASE_IDX', + 'mmSDMA1_STATUS_REG', 'mmSDMA1_STATUS_REG_BASE_IDX', + 'mmSDMA1_TILING_CONFIG', 'mmSDMA1_TILING_CONFIG_BASE_IDX', + 'mmSDMA1_TIMESTAMP_CNTL', 'mmSDMA1_TIMESTAMP_CNTL_BASE_IDX', + 'mmSDMA1_TLBI_GCR_CNTL', 'mmSDMA1_TLBI_GCR_CNTL_BASE_IDX', + 'mmSDMA1_UCODE_ADDR', 'mmSDMA1_UCODE_ADDR_BASE_IDX', + 'mmSDMA1_UCODE_CHECKSUM', 'mmSDMA1_UCODE_CHECKSUM_BASE_IDX', + 'mmSDMA1_UCODE_DATA', 'mmSDMA1_UCODE_DATA_BASE_IDX', + 'mmSDMA1_UTCL1_CNTL', 'mmSDMA1_UTCL1_CNTL_BASE_IDX', + 'mmSDMA1_UTCL1_INV0', 'mmSDMA1_UTCL1_INV0_BASE_IDX', + 'mmSDMA1_UTCL1_INV1', 'mmSDMA1_UTCL1_INV1_BASE_IDX', + 'mmSDMA1_UTCL1_INV2', 'mmSDMA1_UTCL1_INV2_BASE_IDX', + 'mmSDMA1_UTCL1_PAGE', 'mmSDMA1_UTCL1_PAGE_BASE_IDX', + 'mmSDMA1_UTCL1_RD_STATUS', 'mmSDMA1_UTCL1_RD_STATUS_BASE_IDX', + 'mmSDMA1_UTCL1_RD_XNACK0', 'mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX', + 'mmSDMA1_UTCL1_RD_XNACK1', 'mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX', + 'mmSDMA1_UTCL1_TIMEOUT', 'mmSDMA1_UTCL1_TIMEOUT_BASE_IDX', + 'mmSDMA1_UTCL1_WATERMK', 'mmSDMA1_UTCL1_WATERMK_BASE_IDX', + 'mmSDMA1_UTCL1_WR_STATUS', 'mmSDMA1_UTCL1_WR_STATUS_BASE_IDX', + 'mmSDMA1_UTCL1_WR_XNACK0', 'mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX', + 'mmSDMA1_UTCL1_WR_XNACK1', 'mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX', + 'mmSDMA1_VERSION', 'mmSDMA1_VERSION_BASE_IDX', + 'mmSDMA1_VF_ENABLE', 'mmSDMA1_VF_ENABLE_BASE_IDX', + 'mmSDMA1_VIRT_RESET_REQ', 'mmSDMA1_VIRT_RESET_REQ_BASE_IDX', + 'mmSDMA1_VM_CNTL', 'mmSDMA1_VM_CNTL_BASE_IDX', + 'mmSDMA1_VM_CTX_CNTL', 'mmSDMA1_VM_CTX_CNTL_BASE_IDX', + 'mmSDMA1_VM_CTX_HI', 'mmSDMA1_VM_CTX_HI_BASE_IDX', + 'mmSDMA1_VM_CTX_LO', 'mmSDMA1_VM_CTX_LO_BASE_IDX', + 'mmSDMA2_ACTIVE_FCN_ID', 'mmSDMA2_ACTIVE_FCN_ID_BASE_IDX', + 'mmSDMA2_AQL_STATUS', 'mmSDMA2_AQL_STATUS_BASE_IDX', + 'mmSDMA2_ATOMIC_CNTL', 'mmSDMA2_ATOMIC_CNTL_BASE_IDX', + 'mmSDMA2_ATOMIC_PREOP_HI', 'mmSDMA2_ATOMIC_PREOP_HI_BASE_IDX', + 'mmSDMA2_ATOMIC_PREOP_LO', 'mmSDMA2_ATOMIC_PREOP_LO_BASE_IDX', + 'mmSDMA2_BA_THRESHOLD', 'mmSDMA2_BA_THRESHOLD_BASE_IDX', + 'mmSDMA2_CHICKEN_BITS', 'mmSDMA2_CHICKEN_BITS_2', + 'mmSDMA2_CHICKEN_BITS_2_BASE_IDX', + 'mmSDMA2_CHICKEN_BITS_BASE_IDX', 'mmSDMA2_CLK_CTRL', + 'mmSDMA2_CLK_CTRL_BASE_IDX', 'mmSDMA2_CLOCK_GATING_REG', + 'mmSDMA2_CLOCK_GATING_REG_BASE_IDX', 'mmSDMA2_CNTL', + 'mmSDMA2_CNTL_BASE_IDX', 'mmSDMA2_CONTEXT_REG_TYPE0', + 'mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX', 'mmSDMA2_CONTEXT_REG_TYPE1', + 'mmSDMA2_CONTEXT_REG_TYPE1_BASE_IDX', 'mmSDMA2_CONTEXT_REG_TYPE2', + 'mmSDMA2_CONTEXT_REG_TYPE2_BASE_IDX', 'mmSDMA2_CONTEXT_REG_TYPE3', + 'mmSDMA2_CONTEXT_REG_TYPE3_BASE_IDX', 'mmSDMA2_CRD_CNTL', + 'mmSDMA2_CRD_CNTL_BASE_IDX', 'mmSDMA2_DEC_START', + 'mmSDMA2_DEC_START_BASE_IDX', 'mmSDMA2_EA_DBIT_ADDR_DATA', + 'mmSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX', + 'mmSDMA2_EA_DBIT_ADDR_INDEX', + 'mmSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX', 'mmSDMA2_EDC_CONFIG', + 'mmSDMA2_EDC_CONFIG_BASE_IDX', 'mmSDMA2_EDC_COUNTER', + 'mmSDMA2_EDC_COUNTER_BASE_IDX', 'mmSDMA2_EDC_COUNTER_CLEAR', + 'mmSDMA2_EDC_COUNTER_CLEAR_BASE_IDX', 'mmSDMA2_ERROR_LOG', + 'mmSDMA2_ERROR_LOG_BASE_IDX', 'mmSDMA2_F32_CNTL', + 'mmSDMA2_F32_CNTL_BASE_IDX', 'mmSDMA2_F32_COUNTER', + 'mmSDMA2_F32_COUNTER_BASE_IDX', 'mmSDMA2_FREEZE', + 'mmSDMA2_FREEZE_BASE_IDX', 'mmSDMA2_GB_ADDR_CONFIG', + 'mmSDMA2_GB_ADDR_CONFIG_BASE_IDX', 'mmSDMA2_GB_ADDR_CONFIG_READ', + 'mmSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX', + 'mmSDMA2_GFX_CONTEXT_CNTL', 'mmSDMA2_GFX_CONTEXT_CNTL_BASE_IDX', + 'mmSDMA2_GFX_CONTEXT_STATUS', + 'mmSDMA2_GFX_CONTEXT_STATUS_BASE_IDX', 'mmSDMA2_GFX_CSA_ADDR_HI', + 'mmSDMA2_GFX_CSA_ADDR_HI_BASE_IDX', 'mmSDMA2_GFX_CSA_ADDR_LO', + 'mmSDMA2_GFX_CSA_ADDR_LO_BASE_IDX', 'mmSDMA2_GFX_DOORBELL', + 'mmSDMA2_GFX_DOORBELL_BASE_IDX', 'mmSDMA2_GFX_DOORBELL_LOG', + 'mmSDMA2_GFX_DOORBELL_LOG_BASE_IDX', + 'mmSDMA2_GFX_DOORBELL_OFFSET', + 'mmSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_GFX_DUMMY_REG', + 'mmSDMA2_GFX_DUMMY_REG_BASE_IDX', 'mmSDMA2_GFX_IB_BASE_HI', + 'mmSDMA2_GFX_IB_BASE_HI_BASE_IDX', 'mmSDMA2_GFX_IB_BASE_LO', + 'mmSDMA2_GFX_IB_BASE_LO_BASE_IDX', 'mmSDMA2_GFX_IB_CNTL', + 'mmSDMA2_GFX_IB_CNTL_BASE_IDX', 'mmSDMA2_GFX_IB_OFFSET', + 'mmSDMA2_GFX_IB_OFFSET_BASE_IDX', 'mmSDMA2_GFX_IB_RPTR', + 'mmSDMA2_GFX_IB_RPTR_BASE_IDX', 'mmSDMA2_GFX_IB_SIZE', + 'mmSDMA2_GFX_IB_SIZE_BASE_IDX', 'mmSDMA2_GFX_IB_SUB_REMAIN', + 'mmSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_CNTL', + 'mmSDMA2_GFX_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA0', + 'mmSDMA2_GFX_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA1', + 'mmSDMA2_GFX_MIDCMD_DATA10', 'mmSDMA2_GFX_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA2_GFX_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA2', + 'mmSDMA2_GFX_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA3', + 'mmSDMA2_GFX_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA4', + 'mmSDMA2_GFX_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA5', + 'mmSDMA2_GFX_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA6', + 'mmSDMA2_GFX_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA7', + 'mmSDMA2_GFX_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA8', + 'mmSDMA2_GFX_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_GFX_MIDCMD_DATA9', + 'mmSDMA2_GFX_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA2_GFX_MINOR_PTR_UPDATE', + 'mmSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_GFX_PREEMPT', + 'mmSDMA2_GFX_PREEMPT_BASE_IDX', 'mmSDMA2_GFX_RB_AQL_CNTL', + 'mmSDMA2_GFX_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_GFX_RB_BASE', + 'mmSDMA2_GFX_RB_BASE_BASE_IDX', 'mmSDMA2_GFX_RB_BASE_HI', + 'mmSDMA2_GFX_RB_BASE_HI_BASE_IDX', 'mmSDMA2_GFX_RB_CNTL', + 'mmSDMA2_GFX_RB_CNTL_BASE_IDX', 'mmSDMA2_GFX_RB_RPTR', + 'mmSDMA2_GFX_RB_RPTR_ADDR_HI', + 'mmSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA2_GFX_RB_RPTR_ADDR_LO', + 'mmSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA2_GFX_RB_RPTR_BASE_IDX', 'mmSDMA2_GFX_RB_RPTR_HI', + 'mmSDMA2_GFX_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_GFX_RB_WPTR', + 'mmSDMA2_GFX_RB_WPTR_BASE_IDX', 'mmSDMA2_GFX_RB_WPTR_HI', + 'mmSDMA2_GFX_RB_WPTR_HI_BASE_IDX', + 'mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA2_GFX_RB_WPTR_POLL_CNTL', + 'mmSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX', 'mmSDMA2_GFX_SKIP_CNTL', + 'mmSDMA2_GFX_SKIP_CNTL_BASE_IDX', 'mmSDMA2_GFX_STATUS', + 'mmSDMA2_GFX_STATUS_BASE_IDX', 'mmSDMA2_GFX_WATERMARK', + 'mmSDMA2_GFX_WATERMARK_BASE_IDX', 'mmSDMA2_GLOBAL_TIMESTAMP_HI', + 'mmSDMA2_GLOBAL_TIMESTAMP_HI_BASE_IDX', + 'mmSDMA2_GLOBAL_TIMESTAMP_LO', + 'mmSDMA2_GLOBAL_TIMESTAMP_LO_BASE_IDX', 'mmSDMA2_HBM_PAGE_CONFIG', + 'mmSDMA2_HBM_PAGE_CONFIG_BASE_IDX', 'mmSDMA2_HOLE_ADDR_HI', + 'mmSDMA2_HOLE_ADDR_HI_BASE_IDX', 'mmSDMA2_HOLE_ADDR_LO', + 'mmSDMA2_HOLE_ADDR_LO_BASE_IDX', 'mmSDMA2_IB_OFFSET_FETCH', + 'mmSDMA2_IB_OFFSET_FETCH_BASE_IDX', 'mmSDMA2_ID', + 'mmSDMA2_ID_BASE_IDX', 'mmSDMA2_INT_STATUS', + 'mmSDMA2_INT_STATUS_BASE_IDX', 'mmSDMA2_PAGE_CONTEXT_STATUS', + 'mmSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA2_PAGE_CSA_ADDR_HI', 'mmSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA2_PAGE_CSA_ADDR_LO', 'mmSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA2_PAGE_DOORBELL', 'mmSDMA2_PAGE_DOORBELL_BASE_IDX', + 'mmSDMA2_PAGE_DOORBELL_LOG', 'mmSDMA2_PAGE_DOORBELL_LOG_BASE_IDX', + 'mmSDMA2_PAGE_DOORBELL_OFFSET', + 'mmSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_PAGE_DUMMY_REG', + 'mmSDMA2_PAGE_DUMMY_REG_BASE_IDX', 'mmSDMA2_PAGE_IB_BASE_HI', + 'mmSDMA2_PAGE_IB_BASE_HI_BASE_IDX', 'mmSDMA2_PAGE_IB_BASE_LO', + 'mmSDMA2_PAGE_IB_BASE_LO_BASE_IDX', 'mmSDMA2_PAGE_IB_CNTL', + 'mmSDMA2_PAGE_IB_CNTL_BASE_IDX', 'mmSDMA2_PAGE_IB_OFFSET', + 'mmSDMA2_PAGE_IB_OFFSET_BASE_IDX', 'mmSDMA2_PAGE_IB_RPTR', + 'mmSDMA2_PAGE_IB_RPTR_BASE_IDX', 'mmSDMA2_PAGE_IB_SIZE', + 'mmSDMA2_PAGE_IB_SIZE_BASE_IDX', 'mmSDMA2_PAGE_IB_SUB_REMAIN', + 'mmSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_CNTL', + 'mmSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA0', + 'mmSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA1', + 'mmSDMA2_PAGE_MIDCMD_DATA10', + 'mmSDMA2_PAGE_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA2', + 'mmSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA3', + 'mmSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA4', + 'mmSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA5', + 'mmSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA6', + 'mmSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA7', + 'mmSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA8', + 'mmSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_PAGE_MIDCMD_DATA9', + 'mmSDMA2_PAGE_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA2_PAGE_MINOR_PTR_UPDATE', + 'mmSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_PAGE_PREEMPT', + 'mmSDMA2_PAGE_PREEMPT_BASE_IDX', 'mmSDMA2_PAGE_RB_AQL_CNTL', + 'mmSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_PAGE_RB_BASE', + 'mmSDMA2_PAGE_RB_BASE_BASE_IDX', 'mmSDMA2_PAGE_RB_BASE_HI', + 'mmSDMA2_PAGE_RB_BASE_HI_BASE_IDX', 'mmSDMA2_PAGE_RB_CNTL', + 'mmSDMA2_PAGE_RB_CNTL_BASE_IDX', 'mmSDMA2_PAGE_RB_RPTR', + 'mmSDMA2_PAGE_RB_RPTR_ADDR_HI', + 'mmSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA2_PAGE_RB_RPTR_ADDR_LO', + 'mmSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA2_PAGE_RB_RPTR_BASE_IDX', 'mmSDMA2_PAGE_RB_RPTR_HI', + 'mmSDMA2_PAGE_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_PAGE_RB_WPTR', + 'mmSDMA2_PAGE_RB_WPTR_BASE_IDX', 'mmSDMA2_PAGE_RB_WPTR_HI', + 'mmSDMA2_PAGE_RB_WPTR_HI_BASE_IDX', + 'mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA2_PAGE_RB_WPTR_POLL_CNTL', + 'mmSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA2_PAGE_SKIP_CNTL', 'mmSDMA2_PAGE_SKIP_CNTL_BASE_IDX', + 'mmSDMA2_PAGE_STATUS', 'mmSDMA2_PAGE_STATUS_BASE_IDX', + 'mmSDMA2_PAGE_WATERMARK', 'mmSDMA2_PAGE_WATERMARK_BASE_IDX', + 'mmSDMA2_PERFCNT_MISC_CNTL', 'mmSDMA2_PERFCNT_MISC_CNTL_BASE_IDX', + 'mmSDMA2_PERFCNT_PERFCOUNTER0_CFG', + 'mmSDMA2_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', + 'mmSDMA2_PERFCNT_PERFCOUNTER1_CFG', + 'mmSDMA2_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', + 'mmSDMA2_PERFCNT_PERFCOUNTER_HI', + 'mmSDMA2_PERFCNT_PERFCOUNTER_HI_BASE_IDX', + 'mmSDMA2_PERFCNT_PERFCOUNTER_LO', + 'mmSDMA2_PERFCNT_PERFCOUNTER_LO_BASE_IDX', + 'mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL', + 'mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'mmSDMA2_PERFCOUNTER0_HI', 'mmSDMA2_PERFCOUNTER0_HI_BASE_IDX', + 'mmSDMA2_PERFCOUNTER0_LO', 'mmSDMA2_PERFCOUNTER0_LO_BASE_IDX', + 'mmSDMA2_PERFCOUNTER0_SELECT', 'mmSDMA2_PERFCOUNTER0_SELECT1', + 'mmSDMA2_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmSDMA2_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSDMA2_PERFCOUNTER1_HI', + 'mmSDMA2_PERFCOUNTER1_HI_BASE_IDX', 'mmSDMA2_PERFCOUNTER1_LO', + 'mmSDMA2_PERFCOUNTER1_LO_BASE_IDX', 'mmSDMA2_PERFCOUNTER1_SELECT', + 'mmSDMA2_PERFCOUNTER1_SELECT1', + 'mmSDMA2_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmSDMA2_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSDMA2_PG_CNTL', + 'mmSDMA2_PG_CNTL_BASE_IDX', 'mmSDMA2_PG_CTX_CNTL', + 'mmSDMA2_PG_CTX_CNTL_BASE_IDX', 'mmSDMA2_PG_CTX_HI', + 'mmSDMA2_PG_CTX_HI_BASE_IDX', 'mmSDMA2_PG_CTX_LO', + 'mmSDMA2_PG_CTX_LO_BASE_IDX', 'mmSDMA2_PHASE0_QUANTUM', + 'mmSDMA2_PHASE0_QUANTUM_BASE_IDX', 'mmSDMA2_PHASE1_QUANTUM', + 'mmSDMA2_PHASE1_QUANTUM_BASE_IDX', 'mmSDMA2_PHASE2_QUANTUM', + 'mmSDMA2_PHASE2_QUANTUM_BASE_IDX', 'mmSDMA2_PHYSICAL_ADDR_HI', + 'mmSDMA2_PHYSICAL_ADDR_HI_BASE_IDX', 'mmSDMA2_PHYSICAL_ADDR_LO', + 'mmSDMA2_PHYSICAL_ADDR_LO_BASE_IDX', 'mmSDMA2_POWER_CNTL', + 'mmSDMA2_POWER_CNTL_BASE_IDX', 'mmSDMA2_PROGRAM', + 'mmSDMA2_PROGRAM_BASE_IDX', 'mmSDMA2_PUB_DUMMY_REG0', + 'mmSDMA2_PUB_DUMMY_REG0_BASE_IDX', 'mmSDMA2_PUB_DUMMY_REG1', + 'mmSDMA2_PUB_DUMMY_REG1_BASE_IDX', 'mmSDMA2_PUB_DUMMY_REG2', + 'mmSDMA2_PUB_DUMMY_REG2_BASE_IDX', 'mmSDMA2_PUB_DUMMY_REG3', + 'mmSDMA2_PUB_DUMMY_REG3_BASE_IDX', 'mmSDMA2_PUB_REG_TYPE0', + 'mmSDMA2_PUB_REG_TYPE0_BASE_IDX', 'mmSDMA2_PUB_REG_TYPE1', + 'mmSDMA2_PUB_REG_TYPE1_BASE_IDX', 'mmSDMA2_PUB_REG_TYPE2', + 'mmSDMA2_PUB_REG_TYPE2_BASE_IDX', 'mmSDMA2_PUB_REG_TYPE3', + 'mmSDMA2_PUB_REG_TYPE3_BASE_IDX', 'mmSDMA2_QUEUE_RESET_REQ', + 'mmSDMA2_QUEUE_RESET_REQ_BASE_IDX', 'mmSDMA2_RB_RPTR_FETCH', + 'mmSDMA2_RB_RPTR_FETCH_BASE_IDX', 'mmSDMA2_RB_RPTR_FETCH_HI', + 'mmSDMA2_RB_RPTR_FETCH_HI_BASE_IDX', 'mmSDMA2_RD_BURST_CNTL', + 'mmSDMA2_RD_BURST_CNTL_BASE_IDX', 'mmSDMA2_RELAX_ORDERING_LUT', + 'mmSDMA2_RELAX_ORDERING_LUT_BASE_IDX', + 'mmSDMA2_RLC0_CONTEXT_STATUS', + 'mmSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA2_RLC0_CSA_ADDR_HI', 'mmSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC0_CSA_ADDR_LO', 'mmSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC0_DOORBELL', 'mmSDMA2_RLC0_DOORBELL_BASE_IDX', + 'mmSDMA2_RLC0_DOORBELL_LOG', 'mmSDMA2_RLC0_DOORBELL_LOG_BASE_IDX', + 'mmSDMA2_RLC0_DOORBELL_OFFSET', + 'mmSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC0_DUMMY_REG', + 'mmSDMA2_RLC0_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC0_IB_BASE_HI', + 'mmSDMA2_RLC0_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC0_IB_BASE_LO', + 'mmSDMA2_RLC0_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC0_IB_CNTL', + 'mmSDMA2_RLC0_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC0_IB_OFFSET', + 'mmSDMA2_RLC0_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC0_IB_RPTR', + 'mmSDMA2_RLC0_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC0_IB_SIZE', + 'mmSDMA2_RLC0_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC0_IB_SUB_REMAIN', + 'mmSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_CNTL', + 'mmSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA0', + 'mmSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA1', + 'mmSDMA2_RLC0_MIDCMD_DATA10', + 'mmSDMA2_RLC0_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA2', + 'mmSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA3', + 'mmSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA4', + 'mmSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA5', + 'mmSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA6', + 'mmSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA7', + 'mmSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA8', + 'mmSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC0_MIDCMD_DATA9', + 'mmSDMA2_RLC0_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA2_RLC0_MINOR_PTR_UPDATE', + 'mmSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC0_PREEMPT', + 'mmSDMA2_RLC0_PREEMPT_BASE_IDX', 'mmSDMA2_RLC0_RB_AQL_CNTL', + 'mmSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC0_RB_BASE', + 'mmSDMA2_RLC0_RB_BASE_BASE_IDX', 'mmSDMA2_RLC0_RB_BASE_HI', + 'mmSDMA2_RLC0_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC0_RB_CNTL', + 'mmSDMA2_RLC0_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC0_RB_RPTR', + 'mmSDMA2_RLC0_RB_RPTR_ADDR_HI', + 'mmSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC0_RB_RPTR_ADDR_LO', + 'mmSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC0_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC0_RB_RPTR_HI', + 'mmSDMA2_RLC0_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC0_RB_WPTR', + 'mmSDMA2_RLC0_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC0_RB_WPTR_HI', + 'mmSDMA2_RLC0_RB_WPTR_HI_BASE_IDX', + 'mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC0_RB_WPTR_POLL_CNTL', + 'mmSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA2_RLC0_SKIP_CNTL', 'mmSDMA2_RLC0_SKIP_CNTL_BASE_IDX', + 'mmSDMA2_RLC0_STATUS', 'mmSDMA2_RLC0_STATUS_BASE_IDX', + 'mmSDMA2_RLC0_WATERMARK', 'mmSDMA2_RLC0_WATERMARK_BASE_IDX', + 'mmSDMA2_RLC1_CONTEXT_STATUS', + 'mmSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA2_RLC1_CSA_ADDR_HI', 'mmSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC1_CSA_ADDR_LO', 'mmSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC1_DOORBELL', 'mmSDMA2_RLC1_DOORBELL_BASE_IDX', + 'mmSDMA2_RLC1_DOORBELL_LOG', 'mmSDMA2_RLC1_DOORBELL_LOG_BASE_IDX', + 'mmSDMA2_RLC1_DOORBELL_OFFSET', + 'mmSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC1_DUMMY_REG', + 'mmSDMA2_RLC1_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC1_IB_BASE_HI', + 'mmSDMA2_RLC1_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC1_IB_BASE_LO', + 'mmSDMA2_RLC1_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC1_IB_CNTL', + 'mmSDMA2_RLC1_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC1_IB_OFFSET', + 'mmSDMA2_RLC1_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC1_IB_RPTR', + 'mmSDMA2_RLC1_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC1_IB_SIZE', + 'mmSDMA2_RLC1_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC1_IB_SUB_REMAIN', + 'mmSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_CNTL', + 'mmSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA0', + 'mmSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA1', + 'mmSDMA2_RLC1_MIDCMD_DATA10', + 'mmSDMA2_RLC1_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA2', + 'mmSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA3', + 'mmSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA4', + 'mmSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA5', + 'mmSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA6', + 'mmSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA7', + 'mmSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA8', + 'mmSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC1_MIDCMD_DATA9', + 'mmSDMA2_RLC1_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA2_RLC1_MINOR_PTR_UPDATE', + 'mmSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC1_PREEMPT', + 'mmSDMA2_RLC1_PREEMPT_BASE_IDX', 'mmSDMA2_RLC1_RB_AQL_CNTL', + 'mmSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC1_RB_BASE', + 'mmSDMA2_RLC1_RB_BASE_BASE_IDX', 'mmSDMA2_RLC1_RB_BASE_HI', + 'mmSDMA2_RLC1_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC1_RB_CNTL', + 'mmSDMA2_RLC1_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC1_RB_RPTR', + 'mmSDMA2_RLC1_RB_RPTR_ADDR_HI', + 'mmSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC1_RB_RPTR_ADDR_LO', + 'mmSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC1_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC1_RB_RPTR_HI', + 'mmSDMA2_RLC1_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC1_RB_WPTR', + 'mmSDMA2_RLC1_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC1_RB_WPTR_HI', + 'mmSDMA2_RLC1_RB_WPTR_HI_BASE_IDX', + 'mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC1_RB_WPTR_POLL_CNTL', + 'mmSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA2_RLC1_SKIP_CNTL', 'mmSDMA2_RLC1_SKIP_CNTL_BASE_IDX', + 'mmSDMA2_RLC1_STATUS', 'mmSDMA2_RLC1_STATUS_BASE_IDX', + 'mmSDMA2_RLC1_WATERMARK', 'mmSDMA2_RLC1_WATERMARK_BASE_IDX', + 'mmSDMA2_RLC2_CONTEXT_STATUS', + 'mmSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA2_RLC2_CSA_ADDR_HI', 'mmSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC2_CSA_ADDR_LO', 'mmSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC2_DOORBELL', 'mmSDMA2_RLC2_DOORBELL_BASE_IDX', + 'mmSDMA2_RLC2_DOORBELL_LOG', 'mmSDMA2_RLC2_DOORBELL_LOG_BASE_IDX', + 'mmSDMA2_RLC2_DOORBELL_OFFSET', + 'mmSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC2_DUMMY_REG', + 'mmSDMA2_RLC2_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC2_IB_BASE_HI', + 'mmSDMA2_RLC2_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC2_IB_BASE_LO', + 'mmSDMA2_RLC2_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC2_IB_CNTL', + 'mmSDMA2_RLC2_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC2_IB_OFFSET', + 'mmSDMA2_RLC2_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC2_IB_RPTR', + 'mmSDMA2_RLC2_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC2_IB_SIZE', + 'mmSDMA2_RLC2_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC2_IB_SUB_REMAIN', + 'mmSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_CNTL', + 'mmSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA0', + 'mmSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA1', + 'mmSDMA2_RLC2_MIDCMD_DATA10', + 'mmSDMA2_RLC2_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA2', + 'mmSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA3', + 'mmSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA4', + 'mmSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA5', + 'mmSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA6', + 'mmSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA7', + 'mmSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA8', + 'mmSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC2_MIDCMD_DATA9', + 'mmSDMA2_RLC2_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA2_RLC2_MINOR_PTR_UPDATE', + 'mmSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC2_PREEMPT', + 'mmSDMA2_RLC2_PREEMPT_BASE_IDX', 'mmSDMA2_RLC2_RB_AQL_CNTL', + 'mmSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC2_RB_BASE', + 'mmSDMA2_RLC2_RB_BASE_BASE_IDX', 'mmSDMA2_RLC2_RB_BASE_HI', + 'mmSDMA2_RLC2_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC2_RB_CNTL', + 'mmSDMA2_RLC2_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC2_RB_RPTR', + 'mmSDMA2_RLC2_RB_RPTR_ADDR_HI', + 'mmSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC2_RB_RPTR_ADDR_LO', + 'mmSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC2_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC2_RB_RPTR_HI', + 'mmSDMA2_RLC2_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC2_RB_WPTR', + 'mmSDMA2_RLC2_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC2_RB_WPTR_HI', + 'mmSDMA2_RLC2_RB_WPTR_HI_BASE_IDX', + 'mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC2_RB_WPTR_POLL_CNTL', + 'mmSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA2_RLC2_SKIP_CNTL', 'mmSDMA2_RLC2_SKIP_CNTL_BASE_IDX', + 'mmSDMA2_RLC2_STATUS', 'mmSDMA2_RLC2_STATUS_BASE_IDX', + 'mmSDMA2_RLC2_WATERMARK', 'mmSDMA2_RLC2_WATERMARK_BASE_IDX', + 'mmSDMA2_RLC3_CONTEXT_STATUS', + 'mmSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA2_RLC3_CSA_ADDR_HI', 'mmSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC3_CSA_ADDR_LO', 'mmSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC3_DOORBELL', 'mmSDMA2_RLC3_DOORBELL_BASE_IDX', + 'mmSDMA2_RLC3_DOORBELL_LOG', 'mmSDMA2_RLC3_DOORBELL_LOG_BASE_IDX', + 'mmSDMA2_RLC3_DOORBELL_OFFSET', + 'mmSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC3_DUMMY_REG', + 'mmSDMA2_RLC3_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC3_IB_BASE_HI', + 'mmSDMA2_RLC3_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC3_IB_BASE_LO', + 'mmSDMA2_RLC3_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC3_IB_CNTL', + 'mmSDMA2_RLC3_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC3_IB_OFFSET', + 'mmSDMA2_RLC3_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC3_IB_RPTR', + 'mmSDMA2_RLC3_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC3_IB_SIZE', + 'mmSDMA2_RLC3_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC3_IB_SUB_REMAIN', + 'mmSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_CNTL', + 'mmSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA0', + 'mmSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA1', + 'mmSDMA2_RLC3_MIDCMD_DATA10', + 'mmSDMA2_RLC3_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA2', + 'mmSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA3', + 'mmSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA4', + 'mmSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA5', + 'mmSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA6', + 'mmSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA7', + 'mmSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA8', + 'mmSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC3_MIDCMD_DATA9', + 'mmSDMA2_RLC3_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA2_RLC3_MINOR_PTR_UPDATE', + 'mmSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC3_PREEMPT', + 'mmSDMA2_RLC3_PREEMPT_BASE_IDX', 'mmSDMA2_RLC3_RB_AQL_CNTL', + 'mmSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC3_RB_BASE', + 'mmSDMA2_RLC3_RB_BASE_BASE_IDX', 'mmSDMA2_RLC3_RB_BASE_HI', + 'mmSDMA2_RLC3_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC3_RB_CNTL', + 'mmSDMA2_RLC3_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC3_RB_RPTR', + 'mmSDMA2_RLC3_RB_RPTR_ADDR_HI', + 'mmSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC3_RB_RPTR_ADDR_LO', + 'mmSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC3_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC3_RB_RPTR_HI', + 'mmSDMA2_RLC3_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC3_RB_WPTR', + 'mmSDMA2_RLC3_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC3_RB_WPTR_HI', + 'mmSDMA2_RLC3_RB_WPTR_HI_BASE_IDX', + 'mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC3_RB_WPTR_POLL_CNTL', + 'mmSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA2_RLC3_SKIP_CNTL', 'mmSDMA2_RLC3_SKIP_CNTL_BASE_IDX', + 'mmSDMA2_RLC3_STATUS', 'mmSDMA2_RLC3_STATUS_BASE_IDX', + 'mmSDMA2_RLC3_WATERMARK', 'mmSDMA2_RLC3_WATERMARK_BASE_IDX', + 'mmSDMA2_RLC4_CONTEXT_STATUS', + 'mmSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA2_RLC4_CSA_ADDR_HI', 'mmSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC4_CSA_ADDR_LO', 'mmSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC4_DOORBELL', 'mmSDMA2_RLC4_DOORBELL_BASE_IDX', + 'mmSDMA2_RLC4_DOORBELL_LOG', 'mmSDMA2_RLC4_DOORBELL_LOG_BASE_IDX', + 'mmSDMA2_RLC4_DOORBELL_OFFSET', + 'mmSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC4_DUMMY_REG', + 'mmSDMA2_RLC4_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC4_IB_BASE_HI', + 'mmSDMA2_RLC4_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC4_IB_BASE_LO', + 'mmSDMA2_RLC4_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC4_IB_CNTL', + 'mmSDMA2_RLC4_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC4_IB_OFFSET', + 'mmSDMA2_RLC4_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC4_IB_RPTR', + 'mmSDMA2_RLC4_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC4_IB_SIZE', + 'mmSDMA2_RLC4_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC4_IB_SUB_REMAIN', + 'mmSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_CNTL', + 'mmSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA0', + 'mmSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA1', + 'mmSDMA2_RLC4_MIDCMD_DATA10', + 'mmSDMA2_RLC4_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA2', + 'mmSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA3', + 'mmSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA4', + 'mmSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA5', + 'mmSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA6', + 'mmSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA7', + 'mmSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA8', + 'mmSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC4_MIDCMD_DATA9', + 'mmSDMA2_RLC4_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA2_RLC4_MINOR_PTR_UPDATE', + 'mmSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC4_PREEMPT', + 'mmSDMA2_RLC4_PREEMPT_BASE_IDX', 'mmSDMA2_RLC4_RB_AQL_CNTL', + 'mmSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC4_RB_BASE', + 'mmSDMA2_RLC4_RB_BASE_BASE_IDX', 'mmSDMA2_RLC4_RB_BASE_HI', + 'mmSDMA2_RLC4_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC4_RB_CNTL', + 'mmSDMA2_RLC4_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC4_RB_RPTR', + 'mmSDMA2_RLC4_RB_RPTR_ADDR_HI', + 'mmSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC4_RB_RPTR_ADDR_LO', + 'mmSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC4_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC4_RB_RPTR_HI', + 'mmSDMA2_RLC4_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC4_RB_WPTR', + 'mmSDMA2_RLC4_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC4_RB_WPTR_HI', + 'mmSDMA2_RLC4_RB_WPTR_HI_BASE_IDX', + 'mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC4_RB_WPTR_POLL_CNTL', + 'mmSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA2_RLC4_SKIP_CNTL', 'mmSDMA2_RLC4_SKIP_CNTL_BASE_IDX', + 'mmSDMA2_RLC4_STATUS', 'mmSDMA2_RLC4_STATUS_BASE_IDX', + 'mmSDMA2_RLC4_WATERMARK', 'mmSDMA2_RLC4_WATERMARK_BASE_IDX', + 'mmSDMA2_RLC5_CONTEXT_STATUS', + 'mmSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA2_RLC5_CSA_ADDR_HI', 'mmSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC5_CSA_ADDR_LO', 'mmSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC5_DOORBELL', 'mmSDMA2_RLC5_DOORBELL_BASE_IDX', + 'mmSDMA2_RLC5_DOORBELL_LOG', 'mmSDMA2_RLC5_DOORBELL_LOG_BASE_IDX', + 'mmSDMA2_RLC5_DOORBELL_OFFSET', + 'mmSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC5_DUMMY_REG', + 'mmSDMA2_RLC5_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC5_IB_BASE_HI', + 'mmSDMA2_RLC5_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC5_IB_BASE_LO', + 'mmSDMA2_RLC5_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC5_IB_CNTL', + 'mmSDMA2_RLC5_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC5_IB_OFFSET', + 'mmSDMA2_RLC5_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC5_IB_RPTR', + 'mmSDMA2_RLC5_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC5_IB_SIZE', + 'mmSDMA2_RLC5_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC5_IB_SUB_REMAIN', + 'mmSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_CNTL', + 'mmSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA0', + 'mmSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA1', + 'mmSDMA2_RLC5_MIDCMD_DATA10', + 'mmSDMA2_RLC5_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA2', + 'mmSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA3', + 'mmSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA4', + 'mmSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA5', + 'mmSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA6', + 'mmSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA7', + 'mmSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA8', + 'mmSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC5_MIDCMD_DATA9', + 'mmSDMA2_RLC5_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA2_RLC5_MINOR_PTR_UPDATE', + 'mmSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC5_PREEMPT', + 'mmSDMA2_RLC5_PREEMPT_BASE_IDX', 'mmSDMA2_RLC5_RB_AQL_CNTL', + 'mmSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC5_RB_BASE', + 'mmSDMA2_RLC5_RB_BASE_BASE_IDX', 'mmSDMA2_RLC5_RB_BASE_HI', + 'mmSDMA2_RLC5_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC5_RB_CNTL', + 'mmSDMA2_RLC5_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC5_RB_RPTR', + 'mmSDMA2_RLC5_RB_RPTR_ADDR_HI', + 'mmSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC5_RB_RPTR_ADDR_LO', + 'mmSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC5_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC5_RB_RPTR_HI', + 'mmSDMA2_RLC5_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC5_RB_WPTR', + 'mmSDMA2_RLC5_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC5_RB_WPTR_HI', + 'mmSDMA2_RLC5_RB_WPTR_HI_BASE_IDX', + 'mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC5_RB_WPTR_POLL_CNTL', + 'mmSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA2_RLC5_SKIP_CNTL', 'mmSDMA2_RLC5_SKIP_CNTL_BASE_IDX', + 'mmSDMA2_RLC5_STATUS', 'mmSDMA2_RLC5_STATUS_BASE_IDX', + 'mmSDMA2_RLC5_WATERMARK', 'mmSDMA2_RLC5_WATERMARK_BASE_IDX', + 'mmSDMA2_RLC6_CONTEXT_STATUS', + 'mmSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA2_RLC6_CSA_ADDR_HI', 'mmSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC6_CSA_ADDR_LO', 'mmSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC6_DOORBELL', 'mmSDMA2_RLC6_DOORBELL_BASE_IDX', + 'mmSDMA2_RLC6_DOORBELL_LOG', 'mmSDMA2_RLC6_DOORBELL_LOG_BASE_IDX', + 'mmSDMA2_RLC6_DOORBELL_OFFSET', + 'mmSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC6_DUMMY_REG', + 'mmSDMA2_RLC6_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC6_IB_BASE_HI', + 'mmSDMA2_RLC6_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC6_IB_BASE_LO', + 'mmSDMA2_RLC6_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC6_IB_CNTL', + 'mmSDMA2_RLC6_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC6_IB_OFFSET', + 'mmSDMA2_RLC6_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC6_IB_RPTR', + 'mmSDMA2_RLC6_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC6_IB_SIZE', + 'mmSDMA2_RLC6_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC6_IB_SUB_REMAIN', + 'mmSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_CNTL', + 'mmSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA0', + 'mmSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA1', + 'mmSDMA2_RLC6_MIDCMD_DATA10', + 'mmSDMA2_RLC6_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA2', + 'mmSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA3', + 'mmSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA4', + 'mmSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA5', + 'mmSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA6', + 'mmSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA7', + 'mmSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA8', + 'mmSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC6_MIDCMD_DATA9', + 'mmSDMA2_RLC6_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA2_RLC6_MINOR_PTR_UPDATE', + 'mmSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC6_PREEMPT', + 'mmSDMA2_RLC6_PREEMPT_BASE_IDX', 'mmSDMA2_RLC6_RB_AQL_CNTL', + 'mmSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC6_RB_BASE', + 'mmSDMA2_RLC6_RB_BASE_BASE_IDX', 'mmSDMA2_RLC6_RB_BASE_HI', + 'mmSDMA2_RLC6_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC6_RB_CNTL', + 'mmSDMA2_RLC6_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC6_RB_RPTR', + 'mmSDMA2_RLC6_RB_RPTR_ADDR_HI', + 'mmSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC6_RB_RPTR_ADDR_LO', + 'mmSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC6_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC6_RB_RPTR_HI', + 'mmSDMA2_RLC6_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC6_RB_WPTR', + 'mmSDMA2_RLC6_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC6_RB_WPTR_HI', + 'mmSDMA2_RLC6_RB_WPTR_HI_BASE_IDX', + 'mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC6_RB_WPTR_POLL_CNTL', + 'mmSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA2_RLC6_SKIP_CNTL', 'mmSDMA2_RLC6_SKIP_CNTL_BASE_IDX', + 'mmSDMA2_RLC6_STATUS', 'mmSDMA2_RLC6_STATUS_BASE_IDX', + 'mmSDMA2_RLC6_WATERMARK', 'mmSDMA2_RLC6_WATERMARK_BASE_IDX', + 'mmSDMA2_RLC7_CONTEXT_STATUS', + 'mmSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA2_RLC7_CSA_ADDR_HI', 'mmSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC7_CSA_ADDR_LO', 'mmSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC7_DOORBELL', 'mmSDMA2_RLC7_DOORBELL_BASE_IDX', + 'mmSDMA2_RLC7_DOORBELL_LOG', 'mmSDMA2_RLC7_DOORBELL_LOG_BASE_IDX', + 'mmSDMA2_RLC7_DOORBELL_OFFSET', + 'mmSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA2_RLC7_DUMMY_REG', + 'mmSDMA2_RLC7_DUMMY_REG_BASE_IDX', 'mmSDMA2_RLC7_IB_BASE_HI', + 'mmSDMA2_RLC7_IB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC7_IB_BASE_LO', + 'mmSDMA2_RLC7_IB_BASE_LO_BASE_IDX', 'mmSDMA2_RLC7_IB_CNTL', + 'mmSDMA2_RLC7_IB_CNTL_BASE_IDX', 'mmSDMA2_RLC7_IB_OFFSET', + 'mmSDMA2_RLC7_IB_OFFSET_BASE_IDX', 'mmSDMA2_RLC7_IB_RPTR', + 'mmSDMA2_RLC7_IB_RPTR_BASE_IDX', 'mmSDMA2_RLC7_IB_SIZE', + 'mmSDMA2_RLC7_IB_SIZE_BASE_IDX', 'mmSDMA2_RLC7_IB_SUB_REMAIN', + 'mmSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_CNTL', + 'mmSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA0', + 'mmSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA1', + 'mmSDMA2_RLC7_MIDCMD_DATA10', + 'mmSDMA2_RLC7_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA2', + 'mmSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA3', + 'mmSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA4', + 'mmSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA5', + 'mmSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA6', + 'mmSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA7', + 'mmSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA8', + 'mmSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX', 'mmSDMA2_RLC7_MIDCMD_DATA9', + 'mmSDMA2_RLC7_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA2_RLC7_MINOR_PTR_UPDATE', + 'mmSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA2_RLC7_PREEMPT', + 'mmSDMA2_RLC7_PREEMPT_BASE_IDX', 'mmSDMA2_RLC7_RB_AQL_CNTL', + 'mmSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX', 'mmSDMA2_RLC7_RB_BASE', + 'mmSDMA2_RLC7_RB_BASE_BASE_IDX', 'mmSDMA2_RLC7_RB_BASE_HI', + 'mmSDMA2_RLC7_RB_BASE_HI_BASE_IDX', 'mmSDMA2_RLC7_RB_CNTL', + 'mmSDMA2_RLC7_RB_CNTL_BASE_IDX', 'mmSDMA2_RLC7_RB_RPTR', + 'mmSDMA2_RLC7_RB_RPTR_ADDR_HI', + 'mmSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC7_RB_RPTR_ADDR_LO', + 'mmSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC7_RB_RPTR_BASE_IDX', 'mmSDMA2_RLC7_RB_RPTR_HI', + 'mmSDMA2_RLC7_RB_RPTR_HI_BASE_IDX', 'mmSDMA2_RLC7_RB_WPTR', + 'mmSDMA2_RLC7_RB_WPTR_BASE_IDX', 'mmSDMA2_RLC7_RB_WPTR_HI', + 'mmSDMA2_RLC7_RB_WPTR_HI_BASE_IDX', + 'mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA2_RLC7_RB_WPTR_POLL_CNTL', + 'mmSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA2_RLC7_SKIP_CNTL', 'mmSDMA2_RLC7_SKIP_CNTL_BASE_IDX', + 'mmSDMA2_RLC7_STATUS', 'mmSDMA2_RLC7_STATUS_BASE_IDX', + 'mmSDMA2_RLC7_WATERMARK', 'mmSDMA2_RLC7_WATERMARK_BASE_IDX', + 'mmSDMA2_SCRATCH_RAM_ADDR', 'mmSDMA2_SCRATCH_RAM_ADDR_BASE_IDX', + 'mmSDMA2_SCRATCH_RAM_DATA', 'mmSDMA2_SCRATCH_RAM_DATA_BASE_IDX', + 'mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL', + 'mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', + 'mmSDMA2_STATUS1_REG', 'mmSDMA2_STATUS1_REG_BASE_IDX', + 'mmSDMA2_STATUS2_REG', 'mmSDMA2_STATUS2_REG_BASE_IDX', + 'mmSDMA2_STATUS3_REG', 'mmSDMA2_STATUS3_REG_BASE_IDX', + 'mmSDMA2_STATUS4_REG', 'mmSDMA2_STATUS4_REG_BASE_IDX', + 'mmSDMA2_STATUS5_REG', 'mmSDMA2_STATUS5_REG_BASE_IDX', + 'mmSDMA2_STATUS_REG', 'mmSDMA2_STATUS_REG_BASE_IDX', + 'mmSDMA2_TILING_CONFIG', 'mmSDMA2_TILING_CONFIG_BASE_IDX', + 'mmSDMA2_TIMESTAMP_CNTL', 'mmSDMA2_TIMESTAMP_CNTL_BASE_IDX', + 'mmSDMA2_TLBI_GCR_CNTL', 'mmSDMA2_TLBI_GCR_CNTL_BASE_IDX', + 'mmSDMA2_UCODE_ADDR', 'mmSDMA2_UCODE_ADDR_BASE_IDX', + 'mmSDMA2_UCODE_CHECKSUM', 'mmSDMA2_UCODE_CHECKSUM_BASE_IDX', + 'mmSDMA2_UCODE_DATA', 'mmSDMA2_UCODE_DATA_BASE_IDX', + 'mmSDMA2_UTCL1_CNTL', 'mmSDMA2_UTCL1_CNTL_BASE_IDX', + 'mmSDMA2_UTCL1_INV0', 'mmSDMA2_UTCL1_INV0_BASE_IDX', + 'mmSDMA2_UTCL1_INV1', 'mmSDMA2_UTCL1_INV1_BASE_IDX', + 'mmSDMA2_UTCL1_INV2', 'mmSDMA2_UTCL1_INV2_BASE_IDX', + 'mmSDMA2_UTCL1_PAGE', 'mmSDMA2_UTCL1_PAGE_BASE_IDX', + 'mmSDMA2_UTCL1_RD_STATUS', 'mmSDMA2_UTCL1_RD_STATUS_BASE_IDX', + 'mmSDMA2_UTCL1_RD_XNACK0', 'mmSDMA2_UTCL1_RD_XNACK0_BASE_IDX', + 'mmSDMA2_UTCL1_RD_XNACK1', 'mmSDMA2_UTCL1_RD_XNACK1_BASE_IDX', + 'mmSDMA2_UTCL1_TIMEOUT', 'mmSDMA2_UTCL1_TIMEOUT_BASE_IDX', + 'mmSDMA2_UTCL1_WATERMK', 'mmSDMA2_UTCL1_WATERMK_BASE_IDX', + 'mmSDMA2_UTCL1_WR_STATUS', 'mmSDMA2_UTCL1_WR_STATUS_BASE_IDX', + 'mmSDMA2_UTCL1_WR_XNACK0', 'mmSDMA2_UTCL1_WR_XNACK0_BASE_IDX', + 'mmSDMA2_UTCL1_WR_XNACK1', 'mmSDMA2_UTCL1_WR_XNACK1_BASE_IDX', + 'mmSDMA2_VERSION', 'mmSDMA2_VERSION_BASE_IDX', + 'mmSDMA2_VF_ENABLE', 'mmSDMA2_VF_ENABLE_BASE_IDX', + 'mmSDMA2_VIRT_RESET_REQ', 'mmSDMA2_VIRT_RESET_REQ_BASE_IDX', + 'mmSDMA2_VM_CNTL', 'mmSDMA2_VM_CNTL_BASE_IDX', + 'mmSDMA2_VM_CTX_CNTL', 'mmSDMA2_VM_CTX_CNTL_BASE_IDX', + 'mmSDMA2_VM_CTX_HI', 'mmSDMA2_VM_CTX_HI_BASE_IDX', + 'mmSDMA2_VM_CTX_LO', 'mmSDMA2_VM_CTX_LO_BASE_IDX', + 'mmSDMA3_ACTIVE_FCN_ID', 'mmSDMA3_ACTIVE_FCN_ID_BASE_IDX', + 'mmSDMA3_AQL_STATUS', 'mmSDMA3_AQL_STATUS_BASE_IDX', + 'mmSDMA3_ATOMIC_CNTL', 'mmSDMA3_ATOMIC_CNTL_BASE_IDX', + 'mmSDMA3_ATOMIC_PREOP_HI', 'mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX', + 'mmSDMA3_ATOMIC_PREOP_LO', 'mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX', + 'mmSDMA3_BA_THRESHOLD', 'mmSDMA3_BA_THRESHOLD_BASE_IDX', + 'mmSDMA3_CHICKEN_BITS', 'mmSDMA3_CHICKEN_BITS_2', + 'mmSDMA3_CHICKEN_BITS_2_BASE_IDX', + 'mmSDMA3_CHICKEN_BITS_BASE_IDX', 'mmSDMA3_CLK_CTRL', + 'mmSDMA3_CLK_CTRL_BASE_IDX', 'mmSDMA3_CLOCK_GATING_REG', + 'mmSDMA3_CLOCK_GATING_REG_BASE_IDX', 'mmSDMA3_CNTL', + 'mmSDMA3_CNTL_BASE_IDX', 'mmSDMA3_CONTEXT_REG_TYPE0', + 'mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX', 'mmSDMA3_CONTEXT_REG_TYPE1', + 'mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX', 'mmSDMA3_CONTEXT_REG_TYPE2', + 'mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX', 'mmSDMA3_CONTEXT_REG_TYPE3', + 'mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX', 'mmSDMA3_CRD_CNTL', + 'mmSDMA3_CRD_CNTL_BASE_IDX', 'mmSDMA3_DEC_START', + 'mmSDMA3_DEC_START_BASE_IDX', 'mmSDMA3_EA_DBIT_ADDR_DATA', + 'mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX', + 'mmSDMA3_EA_DBIT_ADDR_INDEX', + 'mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX', 'mmSDMA3_EDC_CONFIG', + 'mmSDMA3_EDC_CONFIG_BASE_IDX', 'mmSDMA3_EDC_COUNTER', + 'mmSDMA3_EDC_COUNTER_BASE_IDX', 'mmSDMA3_EDC_COUNTER_CLEAR', + 'mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX', 'mmSDMA3_ERROR_LOG', + 'mmSDMA3_ERROR_LOG_BASE_IDX', 'mmSDMA3_F32_CNTL', + 'mmSDMA3_F32_CNTL_BASE_IDX', 'mmSDMA3_F32_COUNTER', + 'mmSDMA3_F32_COUNTER_BASE_IDX', 'mmSDMA3_FREEZE', + 'mmSDMA3_FREEZE_BASE_IDX', 'mmSDMA3_GB_ADDR_CONFIG', + 'mmSDMA3_GB_ADDR_CONFIG_BASE_IDX', 'mmSDMA3_GB_ADDR_CONFIG_READ', + 'mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX', + 'mmSDMA3_GFX_CONTEXT_CNTL', 'mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX', + 'mmSDMA3_GFX_CONTEXT_STATUS', + 'mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX', 'mmSDMA3_GFX_CSA_ADDR_HI', + 'mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX', 'mmSDMA3_GFX_CSA_ADDR_LO', + 'mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX', 'mmSDMA3_GFX_DOORBELL', + 'mmSDMA3_GFX_DOORBELL_BASE_IDX', 'mmSDMA3_GFX_DOORBELL_LOG', + 'mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX', + 'mmSDMA3_GFX_DOORBELL_OFFSET', + 'mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_GFX_DUMMY_REG', + 'mmSDMA3_GFX_DUMMY_REG_BASE_IDX', 'mmSDMA3_GFX_IB_BASE_HI', + 'mmSDMA3_GFX_IB_BASE_HI_BASE_IDX', 'mmSDMA3_GFX_IB_BASE_LO', + 'mmSDMA3_GFX_IB_BASE_LO_BASE_IDX', 'mmSDMA3_GFX_IB_CNTL', + 'mmSDMA3_GFX_IB_CNTL_BASE_IDX', 'mmSDMA3_GFX_IB_OFFSET', + 'mmSDMA3_GFX_IB_OFFSET_BASE_IDX', 'mmSDMA3_GFX_IB_RPTR', + 'mmSDMA3_GFX_IB_RPTR_BASE_IDX', 'mmSDMA3_GFX_IB_SIZE', + 'mmSDMA3_GFX_IB_SIZE_BASE_IDX', 'mmSDMA3_GFX_IB_SUB_REMAIN', + 'mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_CNTL', + 'mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA0', + 'mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA1', + 'mmSDMA3_GFX_MIDCMD_DATA10', 'mmSDMA3_GFX_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA2', + 'mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA3', + 'mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA4', + 'mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA5', + 'mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA6', + 'mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA7', + 'mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA8', + 'mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_GFX_MIDCMD_DATA9', + 'mmSDMA3_GFX_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA3_GFX_MINOR_PTR_UPDATE', + 'mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_GFX_PREEMPT', + 'mmSDMA3_GFX_PREEMPT_BASE_IDX', 'mmSDMA3_GFX_RB_AQL_CNTL', + 'mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_GFX_RB_BASE', + 'mmSDMA3_GFX_RB_BASE_BASE_IDX', 'mmSDMA3_GFX_RB_BASE_HI', + 'mmSDMA3_GFX_RB_BASE_HI_BASE_IDX', 'mmSDMA3_GFX_RB_CNTL', + 'mmSDMA3_GFX_RB_CNTL_BASE_IDX', 'mmSDMA3_GFX_RB_RPTR', + 'mmSDMA3_GFX_RB_RPTR_ADDR_HI', + 'mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA3_GFX_RB_RPTR_ADDR_LO', + 'mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA3_GFX_RB_RPTR_BASE_IDX', 'mmSDMA3_GFX_RB_RPTR_HI', + 'mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_GFX_RB_WPTR', + 'mmSDMA3_GFX_RB_WPTR_BASE_IDX', 'mmSDMA3_GFX_RB_WPTR_HI', + 'mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX', + 'mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA3_GFX_RB_WPTR_POLL_CNTL', + 'mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX', 'mmSDMA3_GFX_SKIP_CNTL', + 'mmSDMA3_GFX_SKIP_CNTL_BASE_IDX', 'mmSDMA3_GFX_STATUS', + 'mmSDMA3_GFX_STATUS_BASE_IDX', 'mmSDMA3_GFX_WATERMARK', + 'mmSDMA3_GFX_WATERMARK_BASE_IDX', 'mmSDMA3_GLOBAL_TIMESTAMP_HI', + 'mmSDMA3_GLOBAL_TIMESTAMP_HI_BASE_IDX', + 'mmSDMA3_GLOBAL_TIMESTAMP_LO', + 'mmSDMA3_GLOBAL_TIMESTAMP_LO_BASE_IDX', 'mmSDMA3_HBM_PAGE_CONFIG', + 'mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX', 'mmSDMA3_HOLE_ADDR_HI', + 'mmSDMA3_HOLE_ADDR_HI_BASE_IDX', 'mmSDMA3_HOLE_ADDR_LO', + 'mmSDMA3_HOLE_ADDR_LO_BASE_IDX', 'mmSDMA3_IB_OFFSET_FETCH', + 'mmSDMA3_IB_OFFSET_FETCH_BASE_IDX', 'mmSDMA3_ID', + 'mmSDMA3_ID_BASE_IDX', 'mmSDMA3_INT_STATUS', + 'mmSDMA3_INT_STATUS_BASE_IDX', 'mmSDMA3_PAGE_CONTEXT_STATUS', + 'mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA3_PAGE_CSA_ADDR_HI', 'mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA3_PAGE_CSA_ADDR_LO', 'mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA3_PAGE_DOORBELL', 'mmSDMA3_PAGE_DOORBELL_BASE_IDX', + 'mmSDMA3_PAGE_DOORBELL_LOG', 'mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX', + 'mmSDMA3_PAGE_DOORBELL_OFFSET', + 'mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_PAGE_DUMMY_REG', + 'mmSDMA3_PAGE_DUMMY_REG_BASE_IDX', 'mmSDMA3_PAGE_IB_BASE_HI', + 'mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX', 'mmSDMA3_PAGE_IB_BASE_LO', + 'mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX', 'mmSDMA3_PAGE_IB_CNTL', + 'mmSDMA3_PAGE_IB_CNTL_BASE_IDX', 'mmSDMA3_PAGE_IB_OFFSET', + 'mmSDMA3_PAGE_IB_OFFSET_BASE_IDX', 'mmSDMA3_PAGE_IB_RPTR', + 'mmSDMA3_PAGE_IB_RPTR_BASE_IDX', 'mmSDMA3_PAGE_IB_SIZE', + 'mmSDMA3_PAGE_IB_SIZE_BASE_IDX', 'mmSDMA3_PAGE_IB_SUB_REMAIN', + 'mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_CNTL', + 'mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA0', + 'mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA1', + 'mmSDMA3_PAGE_MIDCMD_DATA10', + 'mmSDMA3_PAGE_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA2', + 'mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA3', + 'mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA4', + 'mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA5', + 'mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA6', + 'mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA7', + 'mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA8', + 'mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_PAGE_MIDCMD_DATA9', + 'mmSDMA3_PAGE_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA3_PAGE_MINOR_PTR_UPDATE', + 'mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_PAGE_PREEMPT', + 'mmSDMA3_PAGE_PREEMPT_BASE_IDX', 'mmSDMA3_PAGE_RB_AQL_CNTL', + 'mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_PAGE_RB_BASE', + 'mmSDMA3_PAGE_RB_BASE_BASE_IDX', 'mmSDMA3_PAGE_RB_BASE_HI', + 'mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX', 'mmSDMA3_PAGE_RB_CNTL', + 'mmSDMA3_PAGE_RB_CNTL_BASE_IDX', 'mmSDMA3_PAGE_RB_RPTR', + 'mmSDMA3_PAGE_RB_RPTR_ADDR_HI', + 'mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA3_PAGE_RB_RPTR_ADDR_LO', + 'mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA3_PAGE_RB_RPTR_BASE_IDX', 'mmSDMA3_PAGE_RB_RPTR_HI', + 'mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_PAGE_RB_WPTR', + 'mmSDMA3_PAGE_RB_WPTR_BASE_IDX', 'mmSDMA3_PAGE_RB_WPTR_HI', + 'mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX', + 'mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA3_PAGE_RB_WPTR_POLL_CNTL', + 'mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA3_PAGE_SKIP_CNTL', 'mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX', + 'mmSDMA3_PAGE_STATUS', 'mmSDMA3_PAGE_STATUS_BASE_IDX', + 'mmSDMA3_PAGE_WATERMARK', 'mmSDMA3_PAGE_WATERMARK_BASE_IDX', + 'mmSDMA3_PERFCNT_MISC_CNTL', 'mmSDMA3_PERFCNT_MISC_CNTL_BASE_IDX', + 'mmSDMA3_PERFCNT_PERFCOUNTER0_CFG', + 'mmSDMA3_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX', + 'mmSDMA3_PERFCNT_PERFCOUNTER1_CFG', + 'mmSDMA3_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX', + 'mmSDMA3_PERFCNT_PERFCOUNTER_HI', + 'mmSDMA3_PERFCNT_PERFCOUNTER_HI_BASE_IDX', + 'mmSDMA3_PERFCNT_PERFCOUNTER_LO', + 'mmSDMA3_PERFCNT_PERFCOUNTER_LO_BASE_IDX', + 'mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL', + 'mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX', + 'mmSDMA3_PERFCOUNTER0_HI', 'mmSDMA3_PERFCOUNTER0_HI_BASE_IDX', + 'mmSDMA3_PERFCOUNTER0_LO', 'mmSDMA3_PERFCOUNTER0_LO_BASE_IDX', + 'mmSDMA3_PERFCOUNTER0_SELECT', 'mmSDMA3_PERFCOUNTER0_SELECT1', + 'mmSDMA3_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmSDMA3_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSDMA3_PERFCOUNTER1_HI', + 'mmSDMA3_PERFCOUNTER1_HI_BASE_IDX', 'mmSDMA3_PERFCOUNTER1_LO', + 'mmSDMA3_PERFCOUNTER1_LO_BASE_IDX', 'mmSDMA3_PERFCOUNTER1_SELECT', + 'mmSDMA3_PERFCOUNTER1_SELECT1', + 'mmSDMA3_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmSDMA3_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSDMA3_PG_CNTL', + 'mmSDMA3_PG_CNTL_BASE_IDX', 'mmSDMA3_PG_CTX_CNTL', + 'mmSDMA3_PG_CTX_CNTL_BASE_IDX', 'mmSDMA3_PG_CTX_HI', + 'mmSDMA3_PG_CTX_HI_BASE_IDX', 'mmSDMA3_PG_CTX_LO', + 'mmSDMA3_PG_CTX_LO_BASE_IDX', 'mmSDMA3_PHASE0_QUANTUM', + 'mmSDMA3_PHASE0_QUANTUM_BASE_IDX', 'mmSDMA3_PHASE1_QUANTUM', + 'mmSDMA3_PHASE1_QUANTUM_BASE_IDX', 'mmSDMA3_PHASE2_QUANTUM', + 'mmSDMA3_PHASE2_QUANTUM_BASE_IDX', 'mmSDMA3_PHYSICAL_ADDR_HI', + 'mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX', 'mmSDMA3_PHYSICAL_ADDR_LO', + 'mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX', 'mmSDMA3_POWER_CNTL', + 'mmSDMA3_POWER_CNTL_BASE_IDX', 'mmSDMA3_PROGRAM', + 'mmSDMA3_PROGRAM_BASE_IDX', 'mmSDMA3_PUB_DUMMY_REG0', + 'mmSDMA3_PUB_DUMMY_REG0_BASE_IDX', 'mmSDMA3_PUB_DUMMY_REG1', + 'mmSDMA3_PUB_DUMMY_REG1_BASE_IDX', 'mmSDMA3_PUB_DUMMY_REG2', + 'mmSDMA3_PUB_DUMMY_REG2_BASE_IDX', 'mmSDMA3_PUB_DUMMY_REG3', + 'mmSDMA3_PUB_DUMMY_REG3_BASE_IDX', 'mmSDMA3_PUB_REG_TYPE0', + 'mmSDMA3_PUB_REG_TYPE0_BASE_IDX', 'mmSDMA3_PUB_REG_TYPE1', + 'mmSDMA3_PUB_REG_TYPE1_BASE_IDX', 'mmSDMA3_PUB_REG_TYPE2', + 'mmSDMA3_PUB_REG_TYPE2_BASE_IDX', 'mmSDMA3_PUB_REG_TYPE3', + 'mmSDMA3_PUB_REG_TYPE3_BASE_IDX', 'mmSDMA3_QUEUE_RESET_REQ', + 'mmSDMA3_QUEUE_RESET_REQ_BASE_IDX', 'mmSDMA3_RB_RPTR_FETCH', + 'mmSDMA3_RB_RPTR_FETCH_BASE_IDX', 'mmSDMA3_RB_RPTR_FETCH_HI', + 'mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX', 'mmSDMA3_RD_BURST_CNTL', + 'mmSDMA3_RD_BURST_CNTL_BASE_IDX', 'mmSDMA3_RELAX_ORDERING_LUT', + 'mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX', + 'mmSDMA3_RLC0_CONTEXT_STATUS', + 'mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA3_RLC0_CSA_ADDR_HI', 'mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC0_CSA_ADDR_LO', 'mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC0_DOORBELL', 'mmSDMA3_RLC0_DOORBELL_BASE_IDX', + 'mmSDMA3_RLC0_DOORBELL_LOG', 'mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX', + 'mmSDMA3_RLC0_DOORBELL_OFFSET', + 'mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC0_DUMMY_REG', + 'mmSDMA3_RLC0_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC0_IB_BASE_HI', + 'mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC0_IB_BASE_LO', + 'mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC0_IB_CNTL', + 'mmSDMA3_RLC0_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC0_IB_OFFSET', + 'mmSDMA3_RLC0_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC0_IB_RPTR', + 'mmSDMA3_RLC0_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC0_IB_SIZE', + 'mmSDMA3_RLC0_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC0_IB_SUB_REMAIN', + 'mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_CNTL', + 'mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA0', + 'mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA1', + 'mmSDMA3_RLC0_MIDCMD_DATA10', + 'mmSDMA3_RLC0_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA2', + 'mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA3', + 'mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA4', + 'mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA5', + 'mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA6', + 'mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA7', + 'mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA8', + 'mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC0_MIDCMD_DATA9', + 'mmSDMA3_RLC0_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA3_RLC0_MINOR_PTR_UPDATE', + 'mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC0_PREEMPT', + 'mmSDMA3_RLC0_PREEMPT_BASE_IDX', 'mmSDMA3_RLC0_RB_AQL_CNTL', + 'mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC0_RB_BASE', + 'mmSDMA3_RLC0_RB_BASE_BASE_IDX', 'mmSDMA3_RLC0_RB_BASE_HI', + 'mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC0_RB_CNTL', + 'mmSDMA3_RLC0_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC0_RB_RPTR', + 'mmSDMA3_RLC0_RB_RPTR_ADDR_HI', + 'mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC0_RB_RPTR_ADDR_LO', + 'mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC0_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC0_RB_RPTR_HI', + 'mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC0_RB_WPTR', + 'mmSDMA3_RLC0_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC0_RB_WPTR_HI', + 'mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX', + 'mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC0_RB_WPTR_POLL_CNTL', + 'mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA3_RLC0_SKIP_CNTL', 'mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX', + 'mmSDMA3_RLC0_STATUS', 'mmSDMA3_RLC0_STATUS_BASE_IDX', + 'mmSDMA3_RLC0_WATERMARK', 'mmSDMA3_RLC0_WATERMARK_BASE_IDX', + 'mmSDMA3_RLC1_CONTEXT_STATUS', + 'mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA3_RLC1_CSA_ADDR_HI', 'mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC1_CSA_ADDR_LO', 'mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC1_DOORBELL', 'mmSDMA3_RLC1_DOORBELL_BASE_IDX', + 'mmSDMA3_RLC1_DOORBELL_LOG', 'mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX', + 'mmSDMA3_RLC1_DOORBELL_OFFSET', + 'mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC1_DUMMY_REG', + 'mmSDMA3_RLC1_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC1_IB_BASE_HI', + 'mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC1_IB_BASE_LO', + 'mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC1_IB_CNTL', + 'mmSDMA3_RLC1_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC1_IB_OFFSET', + 'mmSDMA3_RLC1_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC1_IB_RPTR', + 'mmSDMA3_RLC1_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC1_IB_SIZE', + 'mmSDMA3_RLC1_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC1_IB_SUB_REMAIN', + 'mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_CNTL', + 'mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA0', + 'mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA1', + 'mmSDMA3_RLC1_MIDCMD_DATA10', + 'mmSDMA3_RLC1_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA2', + 'mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA3', + 'mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA4', + 'mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA5', + 'mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA6', + 'mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA7', + 'mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA8', + 'mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC1_MIDCMD_DATA9', + 'mmSDMA3_RLC1_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA3_RLC1_MINOR_PTR_UPDATE', + 'mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC1_PREEMPT', + 'mmSDMA3_RLC1_PREEMPT_BASE_IDX', 'mmSDMA3_RLC1_RB_AQL_CNTL', + 'mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC1_RB_BASE', + 'mmSDMA3_RLC1_RB_BASE_BASE_IDX', 'mmSDMA3_RLC1_RB_BASE_HI', + 'mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC1_RB_CNTL', + 'mmSDMA3_RLC1_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC1_RB_RPTR', + 'mmSDMA3_RLC1_RB_RPTR_ADDR_HI', + 'mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC1_RB_RPTR_ADDR_LO', + 'mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC1_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC1_RB_RPTR_HI', + 'mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC1_RB_WPTR', + 'mmSDMA3_RLC1_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC1_RB_WPTR_HI', + 'mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX', + 'mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC1_RB_WPTR_POLL_CNTL', + 'mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA3_RLC1_SKIP_CNTL', 'mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX', + 'mmSDMA3_RLC1_STATUS', 'mmSDMA3_RLC1_STATUS_BASE_IDX', + 'mmSDMA3_RLC1_WATERMARK', 'mmSDMA3_RLC1_WATERMARK_BASE_IDX', + 'mmSDMA3_RLC2_CONTEXT_STATUS', + 'mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA3_RLC2_CSA_ADDR_HI', 'mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC2_CSA_ADDR_LO', 'mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC2_DOORBELL', 'mmSDMA3_RLC2_DOORBELL_BASE_IDX', + 'mmSDMA3_RLC2_DOORBELL_LOG', 'mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX', + 'mmSDMA3_RLC2_DOORBELL_OFFSET', + 'mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC2_DUMMY_REG', + 'mmSDMA3_RLC2_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC2_IB_BASE_HI', + 'mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC2_IB_BASE_LO', + 'mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC2_IB_CNTL', + 'mmSDMA3_RLC2_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC2_IB_OFFSET', + 'mmSDMA3_RLC2_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC2_IB_RPTR', + 'mmSDMA3_RLC2_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC2_IB_SIZE', + 'mmSDMA3_RLC2_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC2_IB_SUB_REMAIN', + 'mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_CNTL', + 'mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA0', + 'mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA1', + 'mmSDMA3_RLC2_MIDCMD_DATA10', + 'mmSDMA3_RLC2_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA2', + 'mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA3', + 'mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA4', + 'mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA5', + 'mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA6', + 'mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA7', + 'mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA8', + 'mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC2_MIDCMD_DATA9', + 'mmSDMA3_RLC2_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA3_RLC2_MINOR_PTR_UPDATE', + 'mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC2_PREEMPT', + 'mmSDMA3_RLC2_PREEMPT_BASE_IDX', 'mmSDMA3_RLC2_RB_AQL_CNTL', + 'mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC2_RB_BASE', + 'mmSDMA3_RLC2_RB_BASE_BASE_IDX', 'mmSDMA3_RLC2_RB_BASE_HI', + 'mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC2_RB_CNTL', + 'mmSDMA3_RLC2_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC2_RB_RPTR', + 'mmSDMA3_RLC2_RB_RPTR_ADDR_HI', + 'mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC2_RB_RPTR_ADDR_LO', + 'mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC2_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC2_RB_RPTR_HI', + 'mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC2_RB_WPTR', + 'mmSDMA3_RLC2_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC2_RB_WPTR_HI', + 'mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX', + 'mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC2_RB_WPTR_POLL_CNTL', + 'mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA3_RLC2_SKIP_CNTL', 'mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX', + 'mmSDMA3_RLC2_STATUS', 'mmSDMA3_RLC2_STATUS_BASE_IDX', + 'mmSDMA3_RLC2_WATERMARK', 'mmSDMA3_RLC2_WATERMARK_BASE_IDX', + 'mmSDMA3_RLC3_CONTEXT_STATUS', + 'mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA3_RLC3_CSA_ADDR_HI', 'mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC3_CSA_ADDR_LO', 'mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC3_DOORBELL', 'mmSDMA3_RLC3_DOORBELL_BASE_IDX', + 'mmSDMA3_RLC3_DOORBELL_LOG', 'mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX', + 'mmSDMA3_RLC3_DOORBELL_OFFSET', + 'mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC3_DUMMY_REG', + 'mmSDMA3_RLC3_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC3_IB_BASE_HI', + 'mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC3_IB_BASE_LO', + 'mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC3_IB_CNTL', + 'mmSDMA3_RLC3_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC3_IB_OFFSET', + 'mmSDMA3_RLC3_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC3_IB_RPTR', + 'mmSDMA3_RLC3_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC3_IB_SIZE', + 'mmSDMA3_RLC3_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC3_IB_SUB_REMAIN', + 'mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_CNTL', + 'mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA0', + 'mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA1', + 'mmSDMA3_RLC3_MIDCMD_DATA10', + 'mmSDMA3_RLC3_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA2', + 'mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA3', + 'mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA4', + 'mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA5', + 'mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA6', + 'mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA7', + 'mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA8', + 'mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC3_MIDCMD_DATA9', + 'mmSDMA3_RLC3_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA3_RLC3_MINOR_PTR_UPDATE', + 'mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC3_PREEMPT', + 'mmSDMA3_RLC3_PREEMPT_BASE_IDX', 'mmSDMA3_RLC3_RB_AQL_CNTL', + 'mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC3_RB_BASE', + 'mmSDMA3_RLC3_RB_BASE_BASE_IDX', 'mmSDMA3_RLC3_RB_BASE_HI', + 'mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC3_RB_CNTL', + 'mmSDMA3_RLC3_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC3_RB_RPTR', + 'mmSDMA3_RLC3_RB_RPTR_ADDR_HI', + 'mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC3_RB_RPTR_ADDR_LO', + 'mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC3_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC3_RB_RPTR_HI', + 'mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC3_RB_WPTR', + 'mmSDMA3_RLC3_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC3_RB_WPTR_HI', + 'mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX', + 'mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC3_RB_WPTR_POLL_CNTL', + 'mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA3_RLC3_SKIP_CNTL', 'mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX', + 'mmSDMA3_RLC3_STATUS', 'mmSDMA3_RLC3_STATUS_BASE_IDX', + 'mmSDMA3_RLC3_WATERMARK', 'mmSDMA3_RLC3_WATERMARK_BASE_IDX', + 'mmSDMA3_RLC4_CONTEXT_STATUS', + 'mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA3_RLC4_CSA_ADDR_HI', 'mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC4_CSA_ADDR_LO', 'mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC4_DOORBELL', 'mmSDMA3_RLC4_DOORBELL_BASE_IDX', + 'mmSDMA3_RLC4_DOORBELL_LOG', 'mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX', + 'mmSDMA3_RLC4_DOORBELL_OFFSET', + 'mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC4_DUMMY_REG', + 'mmSDMA3_RLC4_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC4_IB_BASE_HI', + 'mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC4_IB_BASE_LO', + 'mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC4_IB_CNTL', + 'mmSDMA3_RLC4_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC4_IB_OFFSET', + 'mmSDMA3_RLC4_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC4_IB_RPTR', + 'mmSDMA3_RLC4_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC4_IB_SIZE', + 'mmSDMA3_RLC4_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC4_IB_SUB_REMAIN', + 'mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_CNTL', + 'mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA0', + 'mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA1', + 'mmSDMA3_RLC4_MIDCMD_DATA10', + 'mmSDMA3_RLC4_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA2', + 'mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA3', + 'mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA4', + 'mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA5', + 'mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA6', + 'mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA7', + 'mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA8', + 'mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC4_MIDCMD_DATA9', + 'mmSDMA3_RLC4_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA3_RLC4_MINOR_PTR_UPDATE', + 'mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC4_PREEMPT', + 'mmSDMA3_RLC4_PREEMPT_BASE_IDX', 'mmSDMA3_RLC4_RB_AQL_CNTL', + 'mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC4_RB_BASE', + 'mmSDMA3_RLC4_RB_BASE_BASE_IDX', 'mmSDMA3_RLC4_RB_BASE_HI', + 'mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC4_RB_CNTL', + 'mmSDMA3_RLC4_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC4_RB_RPTR', + 'mmSDMA3_RLC4_RB_RPTR_ADDR_HI', + 'mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC4_RB_RPTR_ADDR_LO', + 'mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC4_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC4_RB_RPTR_HI', + 'mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC4_RB_WPTR', + 'mmSDMA3_RLC4_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC4_RB_WPTR_HI', + 'mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX', + 'mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC4_RB_WPTR_POLL_CNTL', + 'mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA3_RLC4_SKIP_CNTL', 'mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX', + 'mmSDMA3_RLC4_STATUS', 'mmSDMA3_RLC4_STATUS_BASE_IDX', + 'mmSDMA3_RLC4_WATERMARK', 'mmSDMA3_RLC4_WATERMARK_BASE_IDX', + 'mmSDMA3_RLC5_CONTEXT_STATUS', + 'mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA3_RLC5_CSA_ADDR_HI', 'mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC5_CSA_ADDR_LO', 'mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC5_DOORBELL', 'mmSDMA3_RLC5_DOORBELL_BASE_IDX', + 'mmSDMA3_RLC5_DOORBELL_LOG', 'mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX', + 'mmSDMA3_RLC5_DOORBELL_OFFSET', + 'mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC5_DUMMY_REG', + 'mmSDMA3_RLC5_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC5_IB_BASE_HI', + 'mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC5_IB_BASE_LO', + 'mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC5_IB_CNTL', + 'mmSDMA3_RLC5_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC5_IB_OFFSET', + 'mmSDMA3_RLC5_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC5_IB_RPTR', + 'mmSDMA3_RLC5_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC5_IB_SIZE', + 'mmSDMA3_RLC5_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC5_IB_SUB_REMAIN', + 'mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_CNTL', + 'mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA0', + 'mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA1', + 'mmSDMA3_RLC5_MIDCMD_DATA10', + 'mmSDMA3_RLC5_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA2', + 'mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA3', + 'mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA4', + 'mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA5', + 'mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA6', + 'mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA7', + 'mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA8', + 'mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC5_MIDCMD_DATA9', + 'mmSDMA3_RLC5_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA3_RLC5_MINOR_PTR_UPDATE', + 'mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC5_PREEMPT', + 'mmSDMA3_RLC5_PREEMPT_BASE_IDX', 'mmSDMA3_RLC5_RB_AQL_CNTL', + 'mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC5_RB_BASE', + 'mmSDMA3_RLC5_RB_BASE_BASE_IDX', 'mmSDMA3_RLC5_RB_BASE_HI', + 'mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC5_RB_CNTL', + 'mmSDMA3_RLC5_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC5_RB_RPTR', + 'mmSDMA3_RLC5_RB_RPTR_ADDR_HI', + 'mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC5_RB_RPTR_ADDR_LO', + 'mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC5_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC5_RB_RPTR_HI', + 'mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC5_RB_WPTR', + 'mmSDMA3_RLC5_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC5_RB_WPTR_HI', + 'mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX', + 'mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC5_RB_WPTR_POLL_CNTL', + 'mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA3_RLC5_SKIP_CNTL', 'mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX', + 'mmSDMA3_RLC5_STATUS', 'mmSDMA3_RLC5_STATUS_BASE_IDX', + 'mmSDMA3_RLC5_WATERMARK', 'mmSDMA3_RLC5_WATERMARK_BASE_IDX', + 'mmSDMA3_RLC6_CONTEXT_STATUS', + 'mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA3_RLC6_CSA_ADDR_HI', 'mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC6_CSA_ADDR_LO', 'mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC6_DOORBELL', 'mmSDMA3_RLC6_DOORBELL_BASE_IDX', + 'mmSDMA3_RLC6_DOORBELL_LOG', 'mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX', + 'mmSDMA3_RLC6_DOORBELL_OFFSET', + 'mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC6_DUMMY_REG', + 'mmSDMA3_RLC6_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC6_IB_BASE_HI', + 'mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC6_IB_BASE_LO', + 'mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC6_IB_CNTL', + 'mmSDMA3_RLC6_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC6_IB_OFFSET', + 'mmSDMA3_RLC6_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC6_IB_RPTR', + 'mmSDMA3_RLC6_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC6_IB_SIZE', + 'mmSDMA3_RLC6_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC6_IB_SUB_REMAIN', + 'mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_CNTL', + 'mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA0', + 'mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA1', + 'mmSDMA3_RLC6_MIDCMD_DATA10', + 'mmSDMA3_RLC6_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA2', + 'mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA3', + 'mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA4', + 'mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA5', + 'mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA6', + 'mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA7', + 'mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA8', + 'mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC6_MIDCMD_DATA9', + 'mmSDMA3_RLC6_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA3_RLC6_MINOR_PTR_UPDATE', + 'mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC6_PREEMPT', + 'mmSDMA3_RLC6_PREEMPT_BASE_IDX', 'mmSDMA3_RLC6_RB_AQL_CNTL', + 'mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC6_RB_BASE', + 'mmSDMA3_RLC6_RB_BASE_BASE_IDX', 'mmSDMA3_RLC6_RB_BASE_HI', + 'mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC6_RB_CNTL', + 'mmSDMA3_RLC6_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC6_RB_RPTR', + 'mmSDMA3_RLC6_RB_RPTR_ADDR_HI', + 'mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC6_RB_RPTR_ADDR_LO', + 'mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC6_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC6_RB_RPTR_HI', + 'mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC6_RB_WPTR', + 'mmSDMA3_RLC6_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC6_RB_WPTR_HI', + 'mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX', + 'mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC6_RB_WPTR_POLL_CNTL', + 'mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA3_RLC6_SKIP_CNTL', 'mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX', + 'mmSDMA3_RLC6_STATUS', 'mmSDMA3_RLC6_STATUS_BASE_IDX', + 'mmSDMA3_RLC6_WATERMARK', 'mmSDMA3_RLC6_WATERMARK_BASE_IDX', + 'mmSDMA3_RLC7_CONTEXT_STATUS', + 'mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX', + 'mmSDMA3_RLC7_CSA_ADDR_HI', 'mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC7_CSA_ADDR_LO', 'mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC7_DOORBELL', 'mmSDMA3_RLC7_DOORBELL_BASE_IDX', + 'mmSDMA3_RLC7_DOORBELL_LOG', 'mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX', + 'mmSDMA3_RLC7_DOORBELL_OFFSET', + 'mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX', 'mmSDMA3_RLC7_DUMMY_REG', + 'mmSDMA3_RLC7_DUMMY_REG_BASE_IDX', 'mmSDMA3_RLC7_IB_BASE_HI', + 'mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC7_IB_BASE_LO', + 'mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX', 'mmSDMA3_RLC7_IB_CNTL', + 'mmSDMA3_RLC7_IB_CNTL_BASE_IDX', 'mmSDMA3_RLC7_IB_OFFSET', + 'mmSDMA3_RLC7_IB_OFFSET_BASE_IDX', 'mmSDMA3_RLC7_IB_RPTR', + 'mmSDMA3_RLC7_IB_RPTR_BASE_IDX', 'mmSDMA3_RLC7_IB_SIZE', + 'mmSDMA3_RLC7_IB_SIZE_BASE_IDX', 'mmSDMA3_RLC7_IB_SUB_REMAIN', + 'mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_CNTL', + 'mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA0', + 'mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA1', + 'mmSDMA3_RLC7_MIDCMD_DATA10', + 'mmSDMA3_RLC7_MIDCMD_DATA10_BASE_IDX', + 'mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA2', + 'mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA3', + 'mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA4', + 'mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA5', + 'mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA6', + 'mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA7', + 'mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA8', + 'mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX', 'mmSDMA3_RLC7_MIDCMD_DATA9', + 'mmSDMA3_RLC7_MIDCMD_DATA9_BASE_IDX', + 'mmSDMA3_RLC7_MINOR_PTR_UPDATE', + 'mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX', 'mmSDMA3_RLC7_PREEMPT', + 'mmSDMA3_RLC7_PREEMPT_BASE_IDX', 'mmSDMA3_RLC7_RB_AQL_CNTL', + 'mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX', 'mmSDMA3_RLC7_RB_BASE', + 'mmSDMA3_RLC7_RB_BASE_BASE_IDX', 'mmSDMA3_RLC7_RB_BASE_HI', + 'mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX', 'mmSDMA3_RLC7_RB_CNTL', + 'mmSDMA3_RLC7_RB_CNTL_BASE_IDX', 'mmSDMA3_RLC7_RB_RPTR', + 'mmSDMA3_RLC7_RB_RPTR_ADDR_HI', + 'mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC7_RB_RPTR_ADDR_LO', + 'mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC7_RB_RPTR_BASE_IDX', 'mmSDMA3_RLC7_RB_RPTR_HI', + 'mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX', 'mmSDMA3_RLC7_RB_WPTR', + 'mmSDMA3_RLC7_RB_WPTR_BASE_IDX', 'mmSDMA3_RLC7_RB_WPTR_HI', + 'mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX', + 'mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI', + 'mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX', + 'mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO', + 'mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX', + 'mmSDMA3_RLC7_RB_WPTR_POLL_CNTL', + 'mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX', + 'mmSDMA3_RLC7_SKIP_CNTL', 'mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX', + 'mmSDMA3_RLC7_STATUS', 'mmSDMA3_RLC7_STATUS_BASE_IDX', + 'mmSDMA3_RLC7_WATERMARK', 'mmSDMA3_RLC7_WATERMARK_BASE_IDX', + 'mmSDMA3_SCRATCH_RAM_ADDR', 'mmSDMA3_SCRATCH_RAM_ADDR_BASE_IDX', + 'mmSDMA3_SCRATCH_RAM_DATA', 'mmSDMA3_SCRATCH_RAM_DATA_BASE_IDX', + 'mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL', + 'mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX', + 'mmSDMA3_STATUS1_REG', 'mmSDMA3_STATUS1_REG_BASE_IDX', + 'mmSDMA3_STATUS2_REG', 'mmSDMA3_STATUS2_REG_BASE_IDX', + 'mmSDMA3_STATUS3_REG', 'mmSDMA3_STATUS3_REG_BASE_IDX', + 'mmSDMA3_STATUS4_REG', 'mmSDMA3_STATUS4_REG_BASE_IDX', + 'mmSDMA3_STATUS5_REG', 'mmSDMA3_STATUS5_REG_BASE_IDX', + 'mmSDMA3_STATUS_REG', 'mmSDMA3_STATUS_REG_BASE_IDX', + 'mmSDMA3_TILING_CONFIG', 'mmSDMA3_TILING_CONFIG_BASE_IDX', + 'mmSDMA3_TIMESTAMP_CNTL', 'mmSDMA3_TIMESTAMP_CNTL_BASE_IDX', + 'mmSDMA3_TLBI_GCR_CNTL', 'mmSDMA3_TLBI_GCR_CNTL_BASE_IDX', + 'mmSDMA3_UCODE_ADDR', 'mmSDMA3_UCODE_ADDR_BASE_IDX', + 'mmSDMA3_UCODE_CHECKSUM', 'mmSDMA3_UCODE_CHECKSUM_BASE_IDX', + 'mmSDMA3_UCODE_DATA', 'mmSDMA3_UCODE_DATA_BASE_IDX', + 'mmSDMA3_UTCL1_CNTL', 'mmSDMA3_UTCL1_CNTL_BASE_IDX', + 'mmSDMA3_UTCL1_INV0', 'mmSDMA3_UTCL1_INV0_BASE_IDX', + 'mmSDMA3_UTCL1_INV1', 'mmSDMA3_UTCL1_INV1_BASE_IDX', + 'mmSDMA3_UTCL1_INV2', 'mmSDMA3_UTCL1_INV2_BASE_IDX', + 'mmSDMA3_UTCL1_PAGE', 'mmSDMA3_UTCL1_PAGE_BASE_IDX', + 'mmSDMA3_UTCL1_RD_STATUS', 'mmSDMA3_UTCL1_RD_STATUS_BASE_IDX', + 'mmSDMA3_UTCL1_RD_XNACK0', 'mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX', + 'mmSDMA3_UTCL1_RD_XNACK1', 'mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX', + 'mmSDMA3_UTCL1_TIMEOUT', 'mmSDMA3_UTCL1_TIMEOUT_BASE_IDX', + 'mmSDMA3_UTCL1_WATERMK', 'mmSDMA3_UTCL1_WATERMK_BASE_IDX', + 'mmSDMA3_UTCL1_WR_STATUS', 'mmSDMA3_UTCL1_WR_STATUS_BASE_IDX', + 'mmSDMA3_UTCL1_WR_XNACK0', 'mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX', + 'mmSDMA3_UTCL1_WR_XNACK1', 'mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX', + 'mmSDMA3_VERSION', 'mmSDMA3_VERSION_BASE_IDX', + 'mmSDMA3_VF_ENABLE', 'mmSDMA3_VF_ENABLE_BASE_IDX', + 'mmSDMA3_VIRT_RESET_REQ', 'mmSDMA3_VIRT_RESET_REQ_BASE_IDX', + 'mmSDMA3_VM_CNTL', 'mmSDMA3_VM_CNTL_BASE_IDX', + 'mmSDMA3_VM_CTX_CNTL', 'mmSDMA3_VM_CTX_CNTL_BASE_IDX', + 'mmSDMA3_VM_CTX_HI', 'mmSDMA3_VM_CTX_HI_BASE_IDX', + 'mmSDMA3_VM_CTX_LO', 'mmSDMA3_VM_CTX_LO_BASE_IDX', + 'mmSE_CAC_CGTT_CLK_CTRL', 'mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX', + 'mmSE_CAC_IND_DATA', 'mmSE_CAC_IND_DATA_BASE_IDX', + 'mmSE_CAC_IND_INDEX', 'mmSE_CAC_IND_INDEX_BASE_IDX', + 'mmSH_MEM_BASES', 'mmSH_MEM_BASES_BASE_IDX', 'mmSH_MEM_CONFIG', + 'mmSH_MEM_CONFIG_BASE_IDX', 'mmSH_RESERVED_REG0', + 'mmSH_RESERVED_REG0_BASE_IDX', 'mmSH_RESERVED_REG1', + 'mmSH_RESERVED_REG1_BASE_IDX', 'mmSMU_RLC_RESPONSE', + 'mmSMU_RLC_RESPONSE_BASE_IDX', 'mmSPI_ARB_CNTL_0', + 'mmSPI_ARB_CNTL_0_BASE_IDX', 'mmSPI_ARB_CYCLES_0', + 'mmSPI_ARB_CYCLES_0_BASE_IDX', 'mmSPI_ARB_CYCLES_1', + 'mmSPI_ARB_CYCLES_1_BASE_IDX', 'mmSPI_ARB_PRIORITY', + 'mmSPI_ARB_PRIORITY_BASE_IDX', 'mmSPI_BARYC_CNTL', + 'mmSPI_BARYC_CNTL_BASE_IDX', 'mmSPI_COMPUTE_QUEUE_RESET', + 'mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX', 'mmSPI_COMPUTE_WF_CTX_SAVE', + 'mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX', 'mmSPI_CONFIG_CNTL', + 'mmSPI_CONFIG_CNTL_1', 'mmSPI_CONFIG_CNTL_1_BASE_IDX', + 'mmSPI_CONFIG_CNTL_1_REMAP', 'mmSPI_CONFIG_CNTL_1_REMAP_BASE_IDX', + 'mmSPI_CONFIG_CNTL_2', 'mmSPI_CONFIG_CNTL_2_BASE_IDX', + 'mmSPI_CONFIG_CNTL_2_REMAP', 'mmSPI_CONFIG_CNTL_2_REMAP_BASE_IDX', + 'mmSPI_CONFIG_CNTL_BASE_IDX', 'mmSPI_CONFIG_CNTL_REMAP', + 'mmSPI_CONFIG_CNTL_REMAP_BASE_IDX', 'mmSPI_CONFIG_PS_CU_EN', + 'mmSPI_CONFIG_PS_CU_EN_BASE_IDX', 'mmSPI_CSQ_WF_ACTIVE_COUNT_0', + 'mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX', + 'mmSPI_CSQ_WF_ACTIVE_COUNT_1', + 'mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX', + 'mmSPI_CSQ_WF_ACTIVE_COUNT_2', + 'mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX', + 'mmSPI_CSQ_WF_ACTIVE_COUNT_3', + 'mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX', + 'mmSPI_CSQ_WF_ACTIVE_STATUS', + 'mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX', 'mmSPI_DSM_CNTL', + 'mmSPI_DSM_CNTL2', 'mmSPI_DSM_CNTL2_BASE_IDX', + 'mmSPI_DSM_CNTL_BASE_IDX', 'mmSPI_EDC_CNT', + 'mmSPI_EDC_CNT_BASE_IDX', 'mmSPI_EXP_THROTTLE_CTRL', + 'mmSPI_EXP_THROTTLE_CTRL_BASE_IDX', 'mmSPI_FEATURE_CTRL', + 'mmSPI_FEATURE_CTRL_BASE_IDX', 'mmSPI_GDBG_TRAP_CONFIG', + 'mmSPI_GDBG_TRAP_CONFIG_BASE_IDX', 'mmSPI_GDBG_TRAP_DATA0', + 'mmSPI_GDBG_TRAP_DATA0_BASE_IDX', 'mmSPI_GDBG_TRAP_DATA1', + 'mmSPI_GDBG_TRAP_DATA1_BASE_IDX', 'mmSPI_GDBG_TRAP_MASK', + 'mmSPI_GDBG_TRAP_MASK_BASE_IDX', 'mmSPI_GDBG_WAVE_CNTL', + 'mmSPI_GDBG_WAVE_CNTL2', 'mmSPI_GDBG_WAVE_CNTL2_BASE_IDX', + 'mmSPI_GDBG_WAVE_CNTL3', 'mmSPI_GDBG_WAVE_CNTL3_BASE_IDX', + 'mmSPI_GDBG_WAVE_CNTL_BASE_IDX', 'mmSPI_GDS_CREDITS', + 'mmSPI_GDS_CREDITS_BASE_IDX', 'mmSPI_GFX_CNTL', + 'mmSPI_GFX_CNTL_BASE_IDX', 'mmSPI_INTERP_CONTROL_0', + 'mmSPI_INTERP_CONTROL_0_BASE_IDX', 'mmSPI_LB_CTR_CTRL', + 'mmSPI_LB_CTR_CTRL_BASE_IDX', 'mmSPI_LB_DATA_PERWGP_WAVE_CS', + 'mmSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX', + 'mmSPI_LB_DATA_PERWGP_WAVE_HSGS', + 'mmSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX', + 'mmSPI_LB_DATA_PERWGP_WAVE_VSPS', + 'mmSPI_LB_DATA_PERWGP_WAVE_VSPS_BASE_IDX', 'mmSPI_LB_DATA_REG', + 'mmSPI_LB_DATA_REG_BASE_IDX', 'mmSPI_LB_DATA_WAVES', + 'mmSPI_LB_DATA_WAVES_BASE_IDX', 'mmSPI_LB_WGP_MASK', + 'mmSPI_LB_WGP_MASK_BASE_IDX', 'mmSPI_P0_TRAP_SCREEN_GPR_MIN', + 'mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX', + 'mmSPI_P0_TRAP_SCREEN_PSBA_HI', + 'mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX', + 'mmSPI_P0_TRAP_SCREEN_PSBA_LO', + 'mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX', + 'mmSPI_P0_TRAP_SCREEN_PSMA_HI', + 'mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX', + 'mmSPI_P0_TRAP_SCREEN_PSMA_LO', + 'mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX', + 'mmSPI_P1_TRAP_SCREEN_GPR_MIN', + 'mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX', + 'mmSPI_P1_TRAP_SCREEN_PSBA_HI', + 'mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX', + 'mmSPI_P1_TRAP_SCREEN_PSBA_LO', + 'mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX', + 'mmSPI_P1_TRAP_SCREEN_PSMA_HI', + 'mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX', + 'mmSPI_P1_TRAP_SCREEN_PSMA_LO', + 'mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX', 'mmSPI_PERFCOUNTER0_HI', + 'mmSPI_PERFCOUNTER0_HI_BASE_IDX', 'mmSPI_PERFCOUNTER0_LO', + 'mmSPI_PERFCOUNTER0_LO_BASE_IDX', 'mmSPI_PERFCOUNTER0_SELECT', + 'mmSPI_PERFCOUNTER0_SELECT1', + 'mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmSPI_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER1_HI', + 'mmSPI_PERFCOUNTER1_HI_BASE_IDX', 'mmSPI_PERFCOUNTER1_LO', + 'mmSPI_PERFCOUNTER1_LO_BASE_IDX', 'mmSPI_PERFCOUNTER1_SELECT', + 'mmSPI_PERFCOUNTER1_SELECT1', + 'mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmSPI_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER2_HI', + 'mmSPI_PERFCOUNTER2_HI_BASE_IDX', 'mmSPI_PERFCOUNTER2_LO', + 'mmSPI_PERFCOUNTER2_LO_BASE_IDX', 'mmSPI_PERFCOUNTER2_SELECT', + 'mmSPI_PERFCOUNTER2_SELECT1', + 'mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX', + 'mmSPI_PERFCOUNTER2_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER3_HI', + 'mmSPI_PERFCOUNTER3_HI_BASE_IDX', 'mmSPI_PERFCOUNTER3_LO', + 'mmSPI_PERFCOUNTER3_LO_BASE_IDX', 'mmSPI_PERFCOUNTER3_SELECT', + 'mmSPI_PERFCOUNTER3_SELECT1', + 'mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX', + 'mmSPI_PERFCOUNTER3_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER4_HI', + 'mmSPI_PERFCOUNTER4_HI_BASE_IDX', 'mmSPI_PERFCOUNTER4_LO', + 'mmSPI_PERFCOUNTER4_LO_BASE_IDX', 'mmSPI_PERFCOUNTER4_SELECT', + 'mmSPI_PERFCOUNTER4_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER5_HI', + 'mmSPI_PERFCOUNTER5_HI_BASE_IDX', 'mmSPI_PERFCOUNTER5_LO', + 'mmSPI_PERFCOUNTER5_LO_BASE_IDX', 'mmSPI_PERFCOUNTER5_SELECT', + 'mmSPI_PERFCOUNTER5_SELECT_BASE_IDX', 'mmSPI_PERFCOUNTER_BINS', + 'mmSPI_PERFCOUNTER_BINS_BASE_IDX', + 'mmSPI_PG_ENABLE_STATIC_WGP_MASK', + 'mmSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX', 'mmSPI_PQEV_CTRL', + 'mmSPI_PQEV_CTRL_BASE_IDX', 'mmSPI_PS_INPUT_ADDR', + 'mmSPI_PS_INPUT_ADDR_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_0', + 'mmSPI_PS_INPUT_CNTL_0_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_1', + 'mmSPI_PS_INPUT_CNTL_10', 'mmSPI_PS_INPUT_CNTL_10_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_11', 'mmSPI_PS_INPUT_CNTL_11_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_12', 'mmSPI_PS_INPUT_CNTL_12_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_13', 'mmSPI_PS_INPUT_CNTL_13_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_14', 'mmSPI_PS_INPUT_CNTL_14_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_15', 'mmSPI_PS_INPUT_CNTL_15_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_16', 'mmSPI_PS_INPUT_CNTL_16_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_17', 'mmSPI_PS_INPUT_CNTL_17_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_18', 'mmSPI_PS_INPUT_CNTL_18_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_19', 'mmSPI_PS_INPUT_CNTL_19_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_1_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_2', + 'mmSPI_PS_INPUT_CNTL_20', 'mmSPI_PS_INPUT_CNTL_20_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_21', 'mmSPI_PS_INPUT_CNTL_21_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_22', 'mmSPI_PS_INPUT_CNTL_22_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_23', 'mmSPI_PS_INPUT_CNTL_23_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_24', 'mmSPI_PS_INPUT_CNTL_24_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_25', 'mmSPI_PS_INPUT_CNTL_25_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_26', 'mmSPI_PS_INPUT_CNTL_26_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_27', 'mmSPI_PS_INPUT_CNTL_27_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_28', 'mmSPI_PS_INPUT_CNTL_28_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_29', 'mmSPI_PS_INPUT_CNTL_29_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_2_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_3', + 'mmSPI_PS_INPUT_CNTL_30', 'mmSPI_PS_INPUT_CNTL_30_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_31', 'mmSPI_PS_INPUT_CNTL_31_BASE_IDX', + 'mmSPI_PS_INPUT_CNTL_3_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_4', + 'mmSPI_PS_INPUT_CNTL_4_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_5', + 'mmSPI_PS_INPUT_CNTL_5_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_6', + 'mmSPI_PS_INPUT_CNTL_6_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_7', + 'mmSPI_PS_INPUT_CNTL_7_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_8', + 'mmSPI_PS_INPUT_CNTL_8_BASE_IDX', 'mmSPI_PS_INPUT_CNTL_9', + 'mmSPI_PS_INPUT_CNTL_9_BASE_IDX', 'mmSPI_PS_INPUT_ENA', + 'mmSPI_PS_INPUT_ENA_BASE_IDX', 'mmSPI_PS_IN_CONTROL', + 'mmSPI_PS_IN_CONTROL_BASE_IDX', 'mmSPI_PS_MAX_WAVE_ID', + 'mmSPI_PS_MAX_WAVE_ID_BASE_IDX', 'mmSPI_RESOURCE_RESERVE_CU_0', + 'mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_CU_1', + 'mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_CU_2', + 'mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_CU_3', + 'mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_CU_4', + 'mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_CU_5', + 'mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_CU_6', + 'mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_CU_7', + 'mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_CU_8', + 'mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_CU_9', + 'mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_EN_CU_0', + 'mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_EN_CU_1', + 'mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_EN_CU_2', + 'mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_EN_CU_3', + 'mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_EN_CU_4', + 'mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_EN_CU_5', + 'mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_EN_CU_6', + 'mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_EN_CU_7', + 'mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_EN_CU_8', + 'mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX', + 'mmSPI_RESOURCE_RESERVE_EN_CU_9', + 'mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX', + 'mmSPI_SHADER_COL_FORMAT', 'mmSPI_SHADER_COL_FORMAT_BASE_IDX', + 'mmSPI_SHADER_IDX_FORMAT', 'mmSPI_SHADER_IDX_FORMAT_BASE_IDX', + 'mmSPI_SHADER_LATE_ALLOC_VS', + 'mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX', + 'mmSPI_SHADER_PGM_CHKSUM_GS', + 'mmSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX', + 'mmSPI_SHADER_PGM_CHKSUM_HS', + 'mmSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX', + 'mmSPI_SHADER_PGM_CHKSUM_PS', + 'mmSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX', + 'mmSPI_SHADER_PGM_CHKSUM_VS', + 'mmSPI_SHADER_PGM_CHKSUM_VS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_ES', + 'mmSPI_SHADER_PGM_HI_ES_BASE_IDX', 'mmSPI_SHADER_PGM_HI_ES_GS', + 'mmSPI_SHADER_PGM_HI_ES_GS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_GS', + 'mmSPI_SHADER_PGM_HI_GS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_HS', + 'mmSPI_SHADER_PGM_HI_HS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_LS', + 'mmSPI_SHADER_PGM_HI_LS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_LS_HS', + 'mmSPI_SHADER_PGM_HI_LS_HS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_PS', + 'mmSPI_SHADER_PGM_HI_PS_BASE_IDX', 'mmSPI_SHADER_PGM_HI_VS', + 'mmSPI_SHADER_PGM_HI_VS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_ES', + 'mmSPI_SHADER_PGM_LO_ES_BASE_IDX', 'mmSPI_SHADER_PGM_LO_ES_GS', + 'mmSPI_SHADER_PGM_LO_ES_GS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_GS', + 'mmSPI_SHADER_PGM_LO_GS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_HS', + 'mmSPI_SHADER_PGM_LO_HS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_LS', + 'mmSPI_SHADER_PGM_LO_LS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_LS_HS', + 'mmSPI_SHADER_PGM_LO_LS_HS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_PS', + 'mmSPI_SHADER_PGM_LO_PS_BASE_IDX', 'mmSPI_SHADER_PGM_LO_VS', + 'mmSPI_SHADER_PGM_LO_VS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC1_GS', + 'mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC1_HS', + 'mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC1_PS', + 'mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC1_VS', + 'mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX', 'mmSPI_SHADER_PGM_RSRC2_GS', + 'mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX', + 'mmSPI_SHADER_PGM_RSRC2_GS_VS', + 'mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX', + 'mmSPI_SHADER_PGM_RSRC2_HS', 'mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX', + 'mmSPI_SHADER_PGM_RSRC2_PS', 'mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX', + 'mmSPI_SHADER_PGM_RSRC2_VS', 'mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX', + 'mmSPI_SHADER_PGM_RSRC3_GS', 'mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX', + 'mmSPI_SHADER_PGM_RSRC3_HS', 'mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX', + 'mmSPI_SHADER_PGM_RSRC3_PS', 'mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX', + 'mmSPI_SHADER_PGM_RSRC3_VS', 'mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX', + 'mmSPI_SHADER_PGM_RSRC4_GS', 'mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX', + 'mmSPI_SHADER_PGM_RSRC4_HS', 'mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX', + 'mmSPI_SHADER_PGM_RSRC4_PS', 'mmSPI_SHADER_PGM_RSRC4_PS_BASE_IDX', + 'mmSPI_SHADER_PGM_RSRC4_VS', 'mmSPI_SHADER_PGM_RSRC4_VS_BASE_IDX', + 'mmSPI_SHADER_POS_FORMAT', 'mmSPI_SHADER_POS_FORMAT_BASE_IDX', + 'mmSPI_SHADER_REQ_CTRL_ESGS', + 'mmSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX', + 'mmSPI_SHADER_REQ_CTRL_LSHS', + 'mmSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX', 'mmSPI_SHADER_REQ_CTRL_PS', + 'mmSPI_SHADER_REQ_CTRL_PS_BASE_IDX', 'mmSPI_SHADER_REQ_CTRL_VS', + 'mmSPI_SHADER_REQ_CTRL_VS_BASE_IDX', + 'mmSPI_SHADER_RSRC_LIMIT_CTRL', + 'mmSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_ESGS_0', + 'mmSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_ESGS_1', + 'mmSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_ESGS_2', + 'mmSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_ESGS_3', + 'mmSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_LSHS_0', + 'mmSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_LSHS_1', + 'mmSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_LSHS_2', + 'mmSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_LSHS_3', + 'mmSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_PS_0', + 'mmSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_PS_1', + 'mmSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_PS_2', + 'mmSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_PS_3', + 'mmSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_VS_0', + 'mmSPI_SHADER_USER_ACCUM_VS_0_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_VS_1', + 'mmSPI_SHADER_USER_ACCUM_VS_1_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_VS_2', + 'mmSPI_SHADER_USER_ACCUM_VS_2_BASE_IDX', + 'mmSPI_SHADER_USER_ACCUM_VS_3', + 'mmSPI_SHADER_USER_ACCUM_VS_3_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_ADDR_HI_GS', + 'mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_ADDR_HI_HS', + 'mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_ADDR_LO_GS', + 'mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_ADDR_LO_HS', + 'mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_0', + 'mmSPI_SHADER_USER_DATA_GS_0_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_1', 'mmSPI_SHADER_USER_DATA_GS_10', + 'mmSPI_SHADER_USER_DATA_GS_10_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_11', + 'mmSPI_SHADER_USER_DATA_GS_11_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_12', + 'mmSPI_SHADER_USER_DATA_GS_12_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_13', + 'mmSPI_SHADER_USER_DATA_GS_13_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_14', + 'mmSPI_SHADER_USER_DATA_GS_14_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_15', + 'mmSPI_SHADER_USER_DATA_GS_15_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_16', + 'mmSPI_SHADER_USER_DATA_GS_16_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_17', + 'mmSPI_SHADER_USER_DATA_GS_17_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_18', + 'mmSPI_SHADER_USER_DATA_GS_18_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_19', + 'mmSPI_SHADER_USER_DATA_GS_19_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_1_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_2', 'mmSPI_SHADER_USER_DATA_GS_20', + 'mmSPI_SHADER_USER_DATA_GS_20_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_21', + 'mmSPI_SHADER_USER_DATA_GS_21_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_22', + 'mmSPI_SHADER_USER_DATA_GS_22_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_23', + 'mmSPI_SHADER_USER_DATA_GS_23_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_24', + 'mmSPI_SHADER_USER_DATA_GS_24_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_25', + 'mmSPI_SHADER_USER_DATA_GS_25_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_26', + 'mmSPI_SHADER_USER_DATA_GS_26_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_27', + 'mmSPI_SHADER_USER_DATA_GS_27_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_28', + 'mmSPI_SHADER_USER_DATA_GS_28_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_29', + 'mmSPI_SHADER_USER_DATA_GS_29_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_2_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_3', 'mmSPI_SHADER_USER_DATA_GS_30', + 'mmSPI_SHADER_USER_DATA_GS_30_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_31', + 'mmSPI_SHADER_USER_DATA_GS_31_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_3_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_4', + 'mmSPI_SHADER_USER_DATA_GS_4_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_5', + 'mmSPI_SHADER_USER_DATA_GS_5_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_6', + 'mmSPI_SHADER_USER_DATA_GS_6_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_7', + 'mmSPI_SHADER_USER_DATA_GS_7_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_8', + 'mmSPI_SHADER_USER_DATA_GS_8_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_GS_9', + 'mmSPI_SHADER_USER_DATA_GS_9_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_0', + 'mmSPI_SHADER_USER_DATA_HS_0_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_1', 'mmSPI_SHADER_USER_DATA_HS_10', + 'mmSPI_SHADER_USER_DATA_HS_10_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_11', + 'mmSPI_SHADER_USER_DATA_HS_11_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_12', + 'mmSPI_SHADER_USER_DATA_HS_12_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_13', + 'mmSPI_SHADER_USER_DATA_HS_13_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_14', + 'mmSPI_SHADER_USER_DATA_HS_14_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_15', + 'mmSPI_SHADER_USER_DATA_HS_15_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_16', + 'mmSPI_SHADER_USER_DATA_HS_16_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_17', + 'mmSPI_SHADER_USER_DATA_HS_17_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_18', + 'mmSPI_SHADER_USER_DATA_HS_18_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_19', + 'mmSPI_SHADER_USER_DATA_HS_19_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_1_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_2', 'mmSPI_SHADER_USER_DATA_HS_20', + 'mmSPI_SHADER_USER_DATA_HS_20_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_21', + 'mmSPI_SHADER_USER_DATA_HS_21_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_22', + 'mmSPI_SHADER_USER_DATA_HS_22_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_23', + 'mmSPI_SHADER_USER_DATA_HS_23_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_24', + 'mmSPI_SHADER_USER_DATA_HS_24_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_25', + 'mmSPI_SHADER_USER_DATA_HS_25_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_26', + 'mmSPI_SHADER_USER_DATA_HS_26_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_27', + 'mmSPI_SHADER_USER_DATA_HS_27_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_28', + 'mmSPI_SHADER_USER_DATA_HS_28_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_29', + 'mmSPI_SHADER_USER_DATA_HS_29_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_2_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_3', 'mmSPI_SHADER_USER_DATA_HS_30', + 'mmSPI_SHADER_USER_DATA_HS_30_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_31', + 'mmSPI_SHADER_USER_DATA_HS_31_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_3_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_4', + 'mmSPI_SHADER_USER_DATA_HS_4_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_5', + 'mmSPI_SHADER_USER_DATA_HS_5_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_6', + 'mmSPI_SHADER_USER_DATA_HS_6_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_7', + 'mmSPI_SHADER_USER_DATA_HS_7_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_8', + 'mmSPI_SHADER_USER_DATA_HS_8_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_HS_9', + 'mmSPI_SHADER_USER_DATA_HS_9_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_0', + 'mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_1', 'mmSPI_SHADER_USER_DATA_PS_10', + 'mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_11', + 'mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_12', + 'mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_13', + 'mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_14', + 'mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_15', + 'mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_16', + 'mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_17', + 'mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_18', + 'mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_19', + 'mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_2', 'mmSPI_SHADER_USER_DATA_PS_20', + 'mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_21', + 'mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_22', + 'mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_23', + 'mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_24', + 'mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_25', + 'mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_26', + 'mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_27', + 'mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_28', + 'mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_29', + 'mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_3', 'mmSPI_SHADER_USER_DATA_PS_30', + 'mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_31', + 'mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_4', + 'mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_5', + 'mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_6', + 'mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_7', + 'mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_8', + 'mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_PS_9', + 'mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_0', + 'mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_1', 'mmSPI_SHADER_USER_DATA_VS_10', + 'mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_11', + 'mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_12', + 'mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_13', + 'mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_14', + 'mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_15', + 'mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_16', + 'mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_17', + 'mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_18', + 'mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_19', + 'mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_2', 'mmSPI_SHADER_USER_DATA_VS_20', + 'mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_21', + 'mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_22', + 'mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_23', + 'mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_24', + 'mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_25', + 'mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_26', + 'mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_27', + 'mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_28', + 'mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_29', + 'mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_3', 'mmSPI_SHADER_USER_DATA_VS_30', + 'mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_31', + 'mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_4', + 'mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_5', + 'mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_6', + 'mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_7', + 'mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_8', + 'mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX', + 'mmSPI_SHADER_USER_DATA_VS_9', + 'mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX', 'mmSPI_SHADER_Z_FORMAT', + 'mmSPI_SHADER_Z_FORMAT_BASE_IDX', 'mmSPI_START_PHASE', + 'mmSPI_START_PHASE_BASE_IDX', 'mmSPI_SX_EXPORT_BUFFER_SIZES', + 'mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX', + 'mmSPI_SX_SCOREBOARD_BUFFER_SIZES', + 'mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX', 'mmSPI_TMPRING_SIZE', + 'mmSPI_TMPRING_SIZE_BASE_IDX', 'mmSPI_USER_ACCUM_VMID_CNTL', + 'mmSPI_USER_ACCUM_VMID_CNTL_BASE_IDX', 'mmSPI_VS_OUT_CONFIG', + 'mmSPI_VS_OUT_CONFIG_BASE_IDX', 'mmSPI_WAVE_LIMIT_CNTL', + 'mmSPI_WAVE_LIMIT_CNTL_BASE_IDX', 'mmSPI_WAVE_LIMIT_CNTL_REMAP', + 'mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX', + 'mmSPI_WCL_PIPE_PERCENT_CS0', + 'mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX', + 'mmSPI_WCL_PIPE_PERCENT_CS1', + 'mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX', + 'mmSPI_WCL_PIPE_PERCENT_CS2', + 'mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX', + 'mmSPI_WCL_PIPE_PERCENT_CS3', + 'mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX', + 'mmSPI_WCL_PIPE_PERCENT_GFX', + 'mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX', + 'mmSPI_WCL_PIPE_PERCENT_HP3D', + 'mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX', 'mmSPI_WF_LIFETIME_CNTL', + 'mmSPI_WF_LIFETIME_CNTL_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_0', + 'mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_1', + 'mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_2', + 'mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_3', + 'mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_4', + 'mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX', 'mmSPI_WF_LIFETIME_LIMIT_5', + 'mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_0', + 'mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_1', 'mmSPI_WF_LIFETIME_STATUS_11', + 'mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_13', + 'mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_14', + 'mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_15', + 'mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_16', + 'mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_17', + 'mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_18', + 'mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_19', + 'mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_2', 'mmSPI_WF_LIFETIME_STATUS_20', + 'mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_21', + 'mmSPI_WF_LIFETIME_STATUS_21_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_4', + 'mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_6', + 'mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_7', + 'mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_8', + 'mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX', + 'mmSPI_WF_LIFETIME_STATUS_9', + 'mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX', 'mmSP_CONFIG', + 'mmSP_CONFIG_BASE_IDX', 'mmSQC_CACHES', 'mmSQC_CACHES_BASE_IDX', + 'mmSQC_CONFIG', 'mmSQC_CONFIG_BASE_IDX', + 'mmSQC_DCACHE_UTCL0_CNTL1', 'mmSQC_DCACHE_UTCL0_CNTL1_BASE_IDX', + 'mmSQC_DCACHE_UTCL0_CNTL2', 'mmSQC_DCACHE_UTCL0_CNTL2_BASE_IDX', + 'mmSQC_DCACHE_UTCL0_STATUS', 'mmSQC_DCACHE_UTCL0_STATUS_BASE_IDX', + 'mmSQC_ICACHE_UTCL0_CNTL1', 'mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX', + 'mmSQC_ICACHE_UTCL0_CNTL2', 'mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX', + 'mmSQC_ICACHE_UTCL0_STATUS', 'mmSQC_ICACHE_UTCL0_STATUS_BASE_IDX', + 'mmSQG_CONFIG', 'mmSQG_CONFIG_BASE_IDX', 'mmSQG_STATUS', + 'mmSQG_STATUS_BASE_IDX', 'mmSQG_UTCL0_CNTL1', + 'mmSQG_UTCL0_CNTL1_BASE_IDX', 'mmSQG_UTCL0_CNTL2', + 'mmSQG_UTCL0_CNTL2_BASE_IDX', 'mmSQG_UTCL0_STATUS', + 'mmSQG_UTCL0_STATUS_BASE_IDX', 'mmSQ_ALU_CLK_CTRL', + 'mmSQ_ALU_CLK_CTRL_BASE_IDX', 'mmSQ_ARB_CONFIG', + 'mmSQ_ARB_CONFIG_BASE_IDX', 'mmSQ_CMD', 'mmSQ_CMD_BASE_IDX', + 'mmSQ_CONFIG', 'mmSQ_CONFIG_BASE_IDX', 'mmSQ_DEBUG', + 'mmSQ_DEBUG_BASE_IDX', 'mmSQ_DEBUG_STS_GLOBAL', + 'mmSQ_DEBUG_STS_GLOBAL2', 'mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX', + 'mmSQ_DEBUG_STS_GLOBAL_BASE_IDX', 'mmSQ_DSM_CNTL', + 'mmSQ_DSM_CNTL2', 'mmSQ_DSM_CNTL2_BASE_IDX', + 'mmSQ_DSM_CNTL_BASE_IDX', 'mmSQ_EDC_CNT', 'mmSQ_EDC_CNT_BASE_IDX', + 'mmSQ_EDC_FUE_CNTL', 'mmSQ_EDC_FUE_CNTL_BASE_IDX', + 'mmSQ_FIFO_SIZES', 'mmSQ_FIFO_SIZES_BASE_IDX', 'mmSQ_IND_DATA', + 'mmSQ_IND_DATA_BASE_IDX', 'mmSQ_IND_INDEX', + 'mmSQ_IND_INDEX_BASE_IDX', 'mmSQ_INTERRUPT_AUTO_MASK', + 'mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX', 'mmSQ_INTERRUPT_MSG_CTRL', + 'mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX', 'mmSQ_LB_CTR_CTRL', + 'mmSQ_LB_CTR_CTRL_BASE_IDX', 'mmSQ_LB_CTR_SEL0', + 'mmSQ_LB_CTR_SEL0_BASE_IDX', 'mmSQ_LB_CTR_SEL1', + 'mmSQ_LB_CTR_SEL1_BASE_IDX', 'mmSQ_LB_DATA0', + 'mmSQ_LB_DATA0_BASE_IDX', 'mmSQ_LB_DATA1', + 'mmSQ_LB_DATA1_BASE_IDX', 'mmSQ_LB_DATA2', + 'mmSQ_LB_DATA2_BASE_IDX', 'mmSQ_LB_DATA3', + 'mmSQ_LB_DATA3_BASE_IDX', 'mmSQ_LDS_CLK_CTRL', + 'mmSQ_LDS_CLK_CTRL_BASE_IDX', 'mmSQ_PERFCOUNTER0_HI', + 'mmSQ_PERFCOUNTER0_HI_BASE_IDX', 'mmSQ_PERFCOUNTER0_LO', + 'mmSQ_PERFCOUNTER0_LO_BASE_IDX', 'mmSQ_PERFCOUNTER0_SELECT', + 'mmSQ_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER10_HI', + 'mmSQ_PERFCOUNTER10_HI_BASE_IDX', 'mmSQ_PERFCOUNTER10_LO', + 'mmSQ_PERFCOUNTER10_LO_BASE_IDX', 'mmSQ_PERFCOUNTER10_SELECT', + 'mmSQ_PERFCOUNTER10_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER11_HI', + 'mmSQ_PERFCOUNTER11_HI_BASE_IDX', 'mmSQ_PERFCOUNTER11_LO', + 'mmSQ_PERFCOUNTER11_LO_BASE_IDX', 'mmSQ_PERFCOUNTER11_SELECT', + 'mmSQ_PERFCOUNTER11_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER12_HI', + 'mmSQ_PERFCOUNTER12_HI_BASE_IDX', 'mmSQ_PERFCOUNTER12_LO', + 'mmSQ_PERFCOUNTER12_LO_BASE_IDX', 'mmSQ_PERFCOUNTER12_SELECT', + 'mmSQ_PERFCOUNTER12_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER13_HI', + 'mmSQ_PERFCOUNTER13_HI_BASE_IDX', 'mmSQ_PERFCOUNTER13_LO', + 'mmSQ_PERFCOUNTER13_LO_BASE_IDX', 'mmSQ_PERFCOUNTER13_SELECT', + 'mmSQ_PERFCOUNTER13_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER14_HI', + 'mmSQ_PERFCOUNTER14_HI_BASE_IDX', 'mmSQ_PERFCOUNTER14_LO', + 'mmSQ_PERFCOUNTER14_LO_BASE_IDX', 'mmSQ_PERFCOUNTER14_SELECT', + 'mmSQ_PERFCOUNTER14_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER15_HI', + 'mmSQ_PERFCOUNTER15_HI_BASE_IDX', 'mmSQ_PERFCOUNTER15_LO', + 'mmSQ_PERFCOUNTER15_LO_BASE_IDX', 'mmSQ_PERFCOUNTER15_SELECT', + 'mmSQ_PERFCOUNTER15_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER1_HI', + 'mmSQ_PERFCOUNTER1_HI_BASE_IDX', 'mmSQ_PERFCOUNTER1_LO', + 'mmSQ_PERFCOUNTER1_LO_BASE_IDX', 'mmSQ_PERFCOUNTER1_SELECT', + 'mmSQ_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER2_HI', + 'mmSQ_PERFCOUNTER2_HI_BASE_IDX', 'mmSQ_PERFCOUNTER2_LO', + 'mmSQ_PERFCOUNTER2_LO_BASE_IDX', 'mmSQ_PERFCOUNTER2_SELECT', + 'mmSQ_PERFCOUNTER2_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER3_HI', + 'mmSQ_PERFCOUNTER3_HI_BASE_IDX', 'mmSQ_PERFCOUNTER3_LO', + 'mmSQ_PERFCOUNTER3_LO_BASE_IDX', 'mmSQ_PERFCOUNTER3_SELECT', + 'mmSQ_PERFCOUNTER3_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER4_HI', + 'mmSQ_PERFCOUNTER4_HI_BASE_IDX', 'mmSQ_PERFCOUNTER4_LO', + 'mmSQ_PERFCOUNTER4_LO_BASE_IDX', 'mmSQ_PERFCOUNTER4_SELECT', + 'mmSQ_PERFCOUNTER4_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER5_HI', + 'mmSQ_PERFCOUNTER5_HI_BASE_IDX', 'mmSQ_PERFCOUNTER5_LO', + 'mmSQ_PERFCOUNTER5_LO_BASE_IDX', 'mmSQ_PERFCOUNTER5_SELECT', + 'mmSQ_PERFCOUNTER5_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER6_HI', + 'mmSQ_PERFCOUNTER6_HI_BASE_IDX', 'mmSQ_PERFCOUNTER6_LO', + 'mmSQ_PERFCOUNTER6_LO_BASE_IDX', 'mmSQ_PERFCOUNTER6_SELECT', + 'mmSQ_PERFCOUNTER6_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER7_HI', + 'mmSQ_PERFCOUNTER7_HI_BASE_IDX', 'mmSQ_PERFCOUNTER7_LO', + 'mmSQ_PERFCOUNTER7_LO_BASE_IDX', 'mmSQ_PERFCOUNTER7_SELECT', + 'mmSQ_PERFCOUNTER7_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER8_HI', + 'mmSQ_PERFCOUNTER8_HI_BASE_IDX', 'mmSQ_PERFCOUNTER8_LO', + 'mmSQ_PERFCOUNTER8_LO_BASE_IDX', 'mmSQ_PERFCOUNTER8_SELECT', + 'mmSQ_PERFCOUNTER8_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER9_HI', + 'mmSQ_PERFCOUNTER9_HI_BASE_IDX', 'mmSQ_PERFCOUNTER9_LO', + 'mmSQ_PERFCOUNTER9_LO_BASE_IDX', 'mmSQ_PERFCOUNTER9_SELECT', + 'mmSQ_PERFCOUNTER9_SELECT_BASE_IDX', 'mmSQ_PERFCOUNTER_CTRL', + 'mmSQ_PERFCOUNTER_CTRL2', 'mmSQ_PERFCOUNTER_CTRL2_BASE_IDX', + 'mmSQ_PERFCOUNTER_CTRL_BASE_IDX', 'mmSQ_RANDOM_WAVE_PRI', + 'mmSQ_RANDOM_WAVE_PRI_BASE_IDX', 'mmSQ_RUNTIME_CONFIG', + 'mmSQ_RUNTIME_CONFIG_BASE_IDX', 'mmSQ_SHADER_TBA_HI', + 'mmSQ_SHADER_TBA_HI_BASE_IDX', 'mmSQ_SHADER_TBA_LO', + 'mmSQ_SHADER_TBA_LO_BASE_IDX', 'mmSQ_SHADER_TMA_HI', + 'mmSQ_SHADER_TMA_HI_BASE_IDX', 'mmSQ_SHADER_TMA_LO', + 'mmSQ_SHADER_TMA_LO_BASE_IDX', 'mmSQ_TEX_CLK_CTRL', + 'mmSQ_TEX_CLK_CTRL_BASE_IDX', 'mmSQ_THREAD_TRACE_BUF0_BASE', + 'mmSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX', + 'mmSQ_THREAD_TRACE_BUF0_SIZE', + 'mmSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX', + 'mmSQ_THREAD_TRACE_BUF1_BASE', + 'mmSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX', + 'mmSQ_THREAD_TRACE_BUF1_SIZE', + 'mmSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX', 'mmSQ_THREAD_TRACE_CTRL', + 'mmSQ_THREAD_TRACE_CTRL_BASE_IDX', + 'mmSQ_THREAD_TRACE_DROPPED_CNTR', + 'mmSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX', + 'mmSQ_THREAD_TRACE_GFX_DRAW_CNTR', + 'mmSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX', + 'mmSQ_THREAD_TRACE_GFX_MARKER_CNTR', + 'mmSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX', + 'mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR', + 'mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX', + 'mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR', + 'mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX', + 'mmSQ_THREAD_TRACE_MASK', 'mmSQ_THREAD_TRACE_MASK_BASE_IDX', + 'mmSQ_THREAD_TRACE_STATUS', 'mmSQ_THREAD_TRACE_STATUS2', + 'mmSQ_THREAD_TRACE_STATUS2_BASE_IDX', + 'mmSQ_THREAD_TRACE_STATUS_BASE_IDX', + 'mmSQ_THREAD_TRACE_TOKEN_MASK', + 'mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX', + 'mmSQ_THREAD_TRACE_USERDATA_0', + 'mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX', + 'mmSQ_THREAD_TRACE_USERDATA_1', + 'mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX', + 'mmSQ_THREAD_TRACE_USERDATA_2', + 'mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX', + 'mmSQ_THREAD_TRACE_USERDATA_3', + 'mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX', + 'mmSQ_THREAD_TRACE_USERDATA_4', + 'mmSQ_THREAD_TRACE_USERDATA_4_BASE_IDX', + 'mmSQ_THREAD_TRACE_USERDATA_5', + 'mmSQ_THREAD_TRACE_USERDATA_5_BASE_IDX', + 'mmSQ_THREAD_TRACE_USERDATA_6', + 'mmSQ_THREAD_TRACE_USERDATA_6_BASE_IDX', + 'mmSQ_THREAD_TRACE_USERDATA_7', + 'mmSQ_THREAD_TRACE_USERDATA_7_BASE_IDX', 'mmSQ_THREAD_TRACE_WPTR', + 'mmSQ_THREAD_TRACE_WPTR_BASE_IDX', 'mmSQ_TIME_HI', + 'mmSQ_TIME_HI_BASE_IDX', 'mmSQ_TIME_LO', 'mmSQ_TIME_LO_BASE_IDX', + 'mmSQ_WATCH0_ADDR_H', 'mmSQ_WATCH0_ADDR_H_BASE_IDX', + 'mmSQ_WATCH0_ADDR_L', 'mmSQ_WATCH0_ADDR_L_BASE_IDX', + 'mmSQ_WATCH0_CNTL', 'mmSQ_WATCH0_CNTL_BASE_IDX', + 'mmSQ_WATCH1_ADDR_H', 'mmSQ_WATCH1_ADDR_H_BASE_IDX', + 'mmSQ_WATCH1_ADDR_L', 'mmSQ_WATCH1_ADDR_L_BASE_IDX', + 'mmSQ_WATCH1_CNTL', 'mmSQ_WATCH1_CNTL_BASE_IDX', + 'mmSQ_WATCH2_ADDR_H', 'mmSQ_WATCH2_ADDR_H_BASE_IDX', + 'mmSQ_WATCH2_ADDR_L', 'mmSQ_WATCH2_ADDR_L_BASE_IDX', + 'mmSQ_WATCH2_CNTL', 'mmSQ_WATCH2_CNTL_BASE_IDX', + 'mmSQ_WATCH3_ADDR_H', 'mmSQ_WATCH3_ADDR_H_BASE_IDX', + 'mmSQ_WATCH3_ADDR_L', 'mmSQ_WATCH3_ADDR_L_BASE_IDX', + 'mmSQ_WATCH3_CNTL', 'mmSQ_WATCH3_CNTL_BASE_IDX', + 'mmSQ_WREXEC_EXEC_HI', 'mmSQ_WREXEC_EXEC_HI_BASE_IDX', + 'mmSQ_WREXEC_EXEC_LO', 'mmSQ_WREXEC_EXEC_LO_BASE_IDX', + 'mmSX_BLEND_OPT_CONTROL', 'mmSX_BLEND_OPT_CONTROL_BASE_IDX', + 'mmSX_BLEND_OPT_EPSILON', 'mmSX_BLEND_OPT_EPSILON_BASE_IDX', + 'mmSX_DEBUG_1', 'mmSX_DEBUG_1_BASE_IDX', 'mmSX_MRT0_BLEND_OPT', + 'mmSX_MRT0_BLEND_OPT_BASE_IDX', 'mmSX_MRT1_BLEND_OPT', + 'mmSX_MRT1_BLEND_OPT_BASE_IDX', 'mmSX_MRT2_BLEND_OPT', + 'mmSX_MRT2_BLEND_OPT_BASE_IDX', 'mmSX_MRT3_BLEND_OPT', + 'mmSX_MRT3_BLEND_OPT_BASE_IDX', 'mmSX_MRT4_BLEND_OPT', + 'mmSX_MRT4_BLEND_OPT_BASE_IDX', 'mmSX_MRT5_BLEND_OPT', + 'mmSX_MRT5_BLEND_OPT_BASE_IDX', 'mmSX_MRT6_BLEND_OPT', + 'mmSX_MRT6_BLEND_OPT_BASE_IDX', 'mmSX_MRT7_BLEND_OPT', + 'mmSX_MRT7_BLEND_OPT_BASE_IDX', 'mmSX_PERFCOUNTER0_HI', + 'mmSX_PERFCOUNTER0_HI_BASE_IDX', 'mmSX_PERFCOUNTER0_LO', + 'mmSX_PERFCOUNTER0_LO_BASE_IDX', 'mmSX_PERFCOUNTER0_SELECT', + 'mmSX_PERFCOUNTER0_SELECT1', 'mmSX_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmSX_PERFCOUNTER0_SELECT_BASE_IDX', 'mmSX_PERFCOUNTER1_HI', + 'mmSX_PERFCOUNTER1_HI_BASE_IDX', 'mmSX_PERFCOUNTER1_LO', + 'mmSX_PERFCOUNTER1_LO_BASE_IDX', 'mmSX_PERFCOUNTER1_SELECT', + 'mmSX_PERFCOUNTER1_SELECT1', 'mmSX_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmSX_PERFCOUNTER1_SELECT_BASE_IDX', 'mmSX_PERFCOUNTER2_HI', + 'mmSX_PERFCOUNTER2_HI_BASE_IDX', 'mmSX_PERFCOUNTER2_LO', + 'mmSX_PERFCOUNTER2_LO_BASE_IDX', 'mmSX_PERFCOUNTER2_SELECT', + 'mmSX_PERFCOUNTER2_SELECT_BASE_IDX', 'mmSX_PERFCOUNTER3_HI', + 'mmSX_PERFCOUNTER3_HI_BASE_IDX', 'mmSX_PERFCOUNTER3_LO', + 'mmSX_PERFCOUNTER3_LO_BASE_IDX', 'mmSX_PERFCOUNTER3_SELECT', + 'mmSX_PERFCOUNTER3_SELECT_BASE_IDX', 'mmSX_PS_DOWNCONVERT', + 'mmSX_PS_DOWNCONVERT_BASE_IDX', 'mmSX_PS_DOWNCONVERT_CONTROL', + 'mmSX_PS_DOWNCONVERT_CONTROL_BASE_IDX', 'mmTA_BC_BASE_ADDR', + 'mmTA_BC_BASE_ADDR_BASE_IDX', 'mmTA_BC_BASE_ADDR_HI', + 'mmTA_BC_BASE_ADDR_HI_BASE_IDX', 'mmTA_CGTT_CTRL', + 'mmTA_CGTT_CTRL_BASE_IDX', 'mmTA_CNTL', 'mmTA_CNTL_BASE_IDX', + 'mmTA_CS_BC_BASE_ADDR', 'mmTA_CS_BC_BASE_ADDR_BASE_IDX', + 'mmTA_CS_BC_BASE_ADDR_HI', 'mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX', + 'mmTA_PERFCOUNTER0_HI', 'mmTA_PERFCOUNTER0_HI_BASE_IDX', + 'mmTA_PERFCOUNTER0_LO', 'mmTA_PERFCOUNTER0_LO_BASE_IDX', + 'mmTA_PERFCOUNTER0_SELECT', 'mmTA_PERFCOUNTER0_SELECT1', + 'mmTA_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmTA_PERFCOUNTER0_SELECT_BASE_IDX', 'mmTA_PERFCOUNTER1_HI', + 'mmTA_PERFCOUNTER1_HI_BASE_IDX', 'mmTA_PERFCOUNTER1_LO', + 'mmTA_PERFCOUNTER1_LO_BASE_IDX', 'mmTA_PERFCOUNTER1_SELECT', + 'mmTA_PERFCOUNTER1_SELECT_BASE_IDX', 'mmTA_RESERVED_010C', + 'mmTA_RESERVED_010C_BASE_IDX', 'mmTA_SCRATCH', + 'mmTA_SCRATCH_BASE_IDX', 'mmTA_STATUS', 'mmTA_STATUS_BASE_IDX', + 'mmTCI_CNTL_1', 'mmTCI_CNTL_1_BASE_IDX', 'mmTCI_CNTL_2', + 'mmTCI_CNTL_2_BASE_IDX', 'mmTCI_STATUS', 'mmTCI_STATUS_BASE_IDX', + 'mmTCP_EDC_CNT', 'mmTCP_EDC_CNT_BASE_IDX', 'mmTCP_INVALIDATE', + 'mmTCP_INVALIDATE_BASE_IDX', 'mmTCP_PERFCOUNTER0_HI', + 'mmTCP_PERFCOUNTER0_HI_BASE_IDX', 'mmTCP_PERFCOUNTER0_LO', + 'mmTCP_PERFCOUNTER0_LO_BASE_IDX', 'mmTCP_PERFCOUNTER0_SELECT', + 'mmTCP_PERFCOUNTER0_SELECT1', + 'mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmTCP_PERFCOUNTER0_SELECT_BASE_IDX', 'mmTCP_PERFCOUNTER1_HI', + 'mmTCP_PERFCOUNTER1_HI_BASE_IDX', 'mmTCP_PERFCOUNTER1_LO', + 'mmTCP_PERFCOUNTER1_LO_BASE_IDX', 'mmTCP_PERFCOUNTER1_SELECT', + 'mmTCP_PERFCOUNTER1_SELECT1', + 'mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX', + 'mmTCP_PERFCOUNTER1_SELECT_BASE_IDX', 'mmTCP_PERFCOUNTER2_HI', + 'mmTCP_PERFCOUNTER2_HI_BASE_IDX', 'mmTCP_PERFCOUNTER2_LO', + 'mmTCP_PERFCOUNTER2_LO_BASE_IDX', 'mmTCP_PERFCOUNTER2_SELECT', + 'mmTCP_PERFCOUNTER2_SELECT_BASE_IDX', 'mmTCP_PERFCOUNTER3_HI', + 'mmTCP_PERFCOUNTER3_HI_BASE_IDX', 'mmTCP_PERFCOUNTER3_LO', + 'mmTCP_PERFCOUNTER3_LO_BASE_IDX', 'mmTCP_PERFCOUNTER3_SELECT', + 'mmTCP_PERFCOUNTER3_SELECT_BASE_IDX', 'mmTCP_PERFCOUNTER_FILTER', + 'mmTCP_PERFCOUNTER_FILTER2', 'mmTCP_PERFCOUNTER_FILTER2_BASE_IDX', + 'mmTCP_PERFCOUNTER_FILTER_BASE_IDX', + 'mmTCP_PERFCOUNTER_FILTER_EN', + 'mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX', 'mmTCP_STATUS', + 'mmTCP_STATUS_BASE_IDX', 'mmTCP_WATCH0_ADDR_H', + 'mmTCP_WATCH0_ADDR_H_BASE_IDX', 'mmTCP_WATCH0_ADDR_L', + 'mmTCP_WATCH0_ADDR_L_BASE_IDX', 'mmTCP_WATCH0_CNTL', + 'mmTCP_WATCH0_CNTL_BASE_IDX', 'mmTCP_WATCH1_ADDR_H', + 'mmTCP_WATCH1_ADDR_H_BASE_IDX', 'mmTCP_WATCH1_ADDR_L', + 'mmTCP_WATCH1_ADDR_L_BASE_IDX', 'mmTCP_WATCH1_CNTL', + 'mmTCP_WATCH1_CNTL_BASE_IDX', 'mmTCP_WATCH2_ADDR_H', + 'mmTCP_WATCH2_ADDR_H_BASE_IDX', 'mmTCP_WATCH2_ADDR_L', + 'mmTCP_WATCH2_ADDR_L_BASE_IDX', 'mmTCP_WATCH2_CNTL', + 'mmTCP_WATCH2_CNTL_BASE_IDX', 'mmTCP_WATCH3_ADDR_H', + 'mmTCP_WATCH3_ADDR_H_BASE_IDX', 'mmTCP_WATCH3_ADDR_L', + 'mmTCP_WATCH3_ADDR_L_BASE_IDX', 'mmTCP_WATCH3_CNTL', + 'mmTCP_WATCH3_CNTL_BASE_IDX', 'mmTD_CGTT_CTRL', + 'mmTD_CGTT_CTRL_BASE_IDX', 'mmTD_DSM_CNTL', 'mmTD_DSM_CNTL2', + 'mmTD_DSM_CNTL2_BASE_IDX', 'mmTD_DSM_CNTL_BASE_IDX', + 'mmTD_PERFCOUNTER0_HI', 'mmTD_PERFCOUNTER0_HI_BASE_IDX', + 'mmTD_PERFCOUNTER0_LO', 'mmTD_PERFCOUNTER0_LO_BASE_IDX', + 'mmTD_PERFCOUNTER0_SELECT', 'mmTD_PERFCOUNTER0_SELECT1', + 'mmTD_PERFCOUNTER0_SELECT1_BASE_IDX', + 'mmTD_PERFCOUNTER0_SELECT_BASE_IDX', 'mmTD_PERFCOUNTER1_HI', + 'mmTD_PERFCOUNTER1_HI_BASE_IDX', 'mmTD_PERFCOUNTER1_LO', + 'mmTD_PERFCOUNTER1_LO_BASE_IDX', 'mmTD_PERFCOUNTER1_SELECT', + 'mmTD_PERFCOUNTER1_SELECT_BASE_IDX', 'mmTD_SCRATCH', + 'mmTD_SCRATCH_BASE_IDX', 'mmTD_STATUS', 'mmTD_STATUS_BASE_IDX', + 'mmUCONFIG_RESERVED_REG0', 'mmUCONFIG_RESERVED_REG0_BASE_IDX', + 'mmUCONFIG_RESERVED_REG1', 'mmUCONFIG_RESERVED_REG1_BASE_IDX', + 'mmUTCL1_ALOG', 'mmUTCL1_ALOG_BASE_IDX', 'mmUTCL1_CGTT_CLK_CTRL', + 'mmUTCL1_CGTT_CLK_CTRL_BASE_IDX', 'mmUTCL1_CTRL', + 'mmUTCL1_CTRL_BASE_IDX', 'mmUTCL1_PERFCOUNTER0_HI', + 'mmUTCL1_PERFCOUNTER0_HI_BASE_IDX', 'mmUTCL1_PERFCOUNTER0_LO', + 'mmUTCL1_PERFCOUNTER0_LO_BASE_IDX', 'mmUTCL1_PERFCOUNTER0_SELECT', + 'mmUTCL1_PERFCOUNTER0_SELECT_BASE_IDX', 'mmUTCL1_PERFCOUNTER1_HI', + 'mmUTCL1_PERFCOUNTER1_HI_BASE_IDX', 'mmUTCL1_PERFCOUNTER1_LO', + 'mmUTCL1_PERFCOUNTER1_LO_BASE_IDX', 'mmUTCL1_PERFCOUNTER1_SELECT', + 'mmUTCL1_PERFCOUNTER1_SELECT_BASE_IDX', 'mmUTCL1_STATUS', + 'mmUTCL1_STATUS_BASE_IDX', 'mmUTCL1_UTCL0_INVREQ_DISABLE', + 'mmUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX', + 'mmVGT_CACHE_INVALIDATION', 'mmVGT_CACHE_INVALIDATION_BASE_IDX', + 'mmVGT_DISPATCH_DRAW_INDEX', 'mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX', + 'mmVGT_DMA_BASE', 'mmVGT_DMA_BASE_BASE_IDX', 'mmVGT_DMA_BASE_HI', + 'mmVGT_DMA_BASE_HI_BASE_IDX', 'mmVGT_DMA_CONTROL', + 'mmVGT_DMA_CONTROL_BASE_IDX', 'mmVGT_DMA_DATA_FIFO_DEPTH', + 'mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX', 'mmVGT_DMA_EVENT_INITIATOR', + 'mmVGT_DMA_EVENT_INITIATOR_BASE_IDX', 'mmVGT_DMA_INDEX_TYPE', + 'mmVGT_DMA_INDEX_TYPE_BASE_IDX', 'mmVGT_DMA_LS_HS_CONFIG', + 'mmVGT_DMA_LS_HS_CONFIG_BASE_IDX', 'mmVGT_DMA_MAX_SIZE', + 'mmVGT_DMA_MAX_SIZE_BASE_IDX', 'mmVGT_DMA_NUM_INSTANCES', + 'mmVGT_DMA_NUM_INSTANCES_BASE_IDX', 'mmVGT_DMA_PRIMITIVE_TYPE', + 'mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX', 'mmVGT_DMA_REQ_FIFO_DEPTH', + 'mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX', 'mmVGT_DMA_SIZE', + 'mmVGT_DMA_SIZE_BASE_IDX', 'mmVGT_DRAW_INITIATOR', + 'mmVGT_DRAW_INITIATOR_BASE_IDX', 'mmVGT_DRAW_INIT_FIFO_DEPTH', + 'mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX', 'mmVGT_DRAW_PAYLOAD_CNTL', + 'mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX', 'mmVGT_ENHANCE', + 'mmVGT_ENHANCE_BASE_IDX', 'mmVGT_ESGS_RING_ITEMSIZE', + 'mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX', 'mmVGT_ESGS_RING_SIZE', + 'mmVGT_ESGS_RING_SIZE_BASE_IDX', 'mmVGT_ESGS_RING_SIZE_UMD', + 'mmVGT_ESGS_RING_SIZE_UMD_BASE_IDX', 'mmVGT_ES_PER_GS', + 'mmVGT_ES_PER_GS_BASE_IDX', 'mmVGT_EVENT_ADDRESS_REG', + 'mmVGT_EVENT_ADDRESS_REG_BASE_IDX', 'mmVGT_EVENT_INITIATOR', + 'mmVGT_EVENT_INITIATOR_BASE_IDX', 'mmVGT_FIFO_DEPTHS', + 'mmVGT_FIFO_DEPTHS_BASE_IDX', 'mmVGT_GROUP_DECR', + 'mmVGT_GROUP_DECR_BASE_IDX', 'mmVGT_GROUP_FIRST_DECR', + 'mmVGT_GROUP_FIRST_DECR_BASE_IDX', 'mmVGT_GROUP_PRIM_TYPE', + 'mmVGT_GROUP_PRIM_TYPE_BASE_IDX', 'mmVGT_GROUP_VECT_0_CNTL', + 'mmVGT_GROUP_VECT_0_CNTL_BASE_IDX', 'mmVGT_GROUP_VECT_0_FMT_CNTL', + 'mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX', 'mmVGT_GROUP_VECT_1_CNTL', + 'mmVGT_GROUP_VECT_1_CNTL_BASE_IDX', 'mmVGT_GROUP_VECT_1_FMT_CNTL', + 'mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX', + 'mmVGT_GSVS_RING_ITEMSIZE', 'mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX', + 'mmVGT_GSVS_RING_OFFSET_1', 'mmVGT_GSVS_RING_OFFSET_1_BASE_IDX', + 'mmVGT_GSVS_RING_OFFSET_2', 'mmVGT_GSVS_RING_OFFSET_2_BASE_IDX', + 'mmVGT_GSVS_RING_OFFSET_3', 'mmVGT_GSVS_RING_OFFSET_3_BASE_IDX', + 'mmVGT_GSVS_RING_SIZE', 'mmVGT_GSVS_RING_SIZE_BASE_IDX', + 'mmVGT_GSVS_RING_SIZE_UMD', 'mmVGT_GSVS_RING_SIZE_UMD_BASE_IDX', + 'mmVGT_GS_INSTANCE_CNT', 'mmVGT_GS_INSTANCE_CNT_BASE_IDX', + 'mmVGT_GS_MAX_VERT_OUT', 'mmVGT_GS_MAX_VERT_OUT_BASE_IDX', + 'mmVGT_GS_MAX_WAVE_ID', 'mmVGT_GS_MAX_WAVE_ID_BASE_IDX', + 'mmVGT_GS_MODE', 'mmVGT_GS_MODE_BASE_IDX', 'mmVGT_GS_ONCHIP_CNTL', + 'mmVGT_GS_ONCHIP_CNTL_BASE_IDX', 'mmVGT_GS_OUT_PRIM_TYPE', + 'mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX', 'mmVGT_GS_PER_ES', + 'mmVGT_GS_PER_ES_BASE_IDX', 'mmVGT_GS_PER_VS', + 'mmVGT_GS_PER_VS_BASE_IDX', 'mmVGT_GS_VERTEX_REUSE', + 'mmVGT_GS_VERTEX_REUSE_BASE_IDX', 'mmVGT_GS_VERT_ITEMSIZE', + 'mmVGT_GS_VERT_ITEMSIZE_1', 'mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX', + 'mmVGT_GS_VERT_ITEMSIZE_2', 'mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX', + 'mmVGT_GS_VERT_ITEMSIZE_3', 'mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX', + 'mmVGT_GS_VERT_ITEMSIZE_BASE_IDX', 'mmVGT_HOS_CNTL', + 'mmVGT_HOS_CNTL_BASE_IDX', 'mmVGT_HOS_MAX_TESS_LEVEL', + 'mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX', 'mmVGT_HOS_MIN_TESS_LEVEL', + 'mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX', 'mmVGT_HOS_REUSE_DEPTH', + 'mmVGT_HOS_REUSE_DEPTH_BASE_IDX', 'mmVGT_HS_OFFCHIP_PARAM', + 'mmVGT_HS_OFFCHIP_PARAM_BASE_IDX', 'mmVGT_HS_OFFCHIP_PARAM_UMD', + 'mmVGT_HS_OFFCHIP_PARAM_UMD_BASE_IDX', 'mmVGT_IMMED_DATA', + 'mmVGT_IMMED_DATA_BASE_IDX', 'mmVGT_INDEX_TYPE', + 'mmVGT_INDEX_TYPE_BASE_IDX', 'mmVGT_INDX_OFFSET', + 'mmVGT_INDX_OFFSET_BASE_IDX', 'mmVGT_INSTANCE_BASE_ID', + 'mmVGT_INSTANCE_BASE_ID_BASE_IDX', 'mmVGT_INSTANCE_STEP_RATE_0', + 'mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX', + 'mmVGT_INSTANCE_STEP_RATE_1', + 'mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX', 'mmVGT_LAST_COPY_STATE', + 'mmVGT_LAST_COPY_STATE_BASE_IDX', 'mmVGT_LS_HS_CONFIG', + 'mmVGT_LS_HS_CONFIG_BASE_IDX', 'mmVGT_MAX_VTX_INDX', + 'mmVGT_MAX_VTX_INDX_BASE_IDX', 'mmVGT_MC_LAT_CNTL', + 'mmVGT_MC_LAT_CNTL_BASE_IDX', 'mmVGT_MIN_VTX_INDX', + 'mmVGT_MIN_VTX_INDX_BASE_IDX', 'mmVGT_MULTI_PRIM_IB_RESET_EN', + 'mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX', + 'mmVGT_MULTI_PRIM_IB_RESET_INDX', + 'mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX', 'mmVGT_NUM_INDICES', + 'mmVGT_NUM_INDICES_BASE_IDX', 'mmVGT_NUM_INSTANCES', + 'mmVGT_NUM_INSTANCES_BASE_IDX', 'mmVGT_OUTPUT_PATH_CNTL', + 'mmVGT_OUTPUT_PATH_CNTL_BASE_IDX', 'mmVGT_OUT_DEALLOC_CNTL', + 'mmVGT_OUT_DEALLOC_CNTL_BASE_IDX', 'mmVGT_PRIMITIVEID_EN', + 'mmVGT_PRIMITIVEID_EN_BASE_IDX', 'mmVGT_PRIMITIVEID_RESET', + 'mmVGT_PRIMITIVEID_RESET_BASE_IDX', 'mmVGT_PRIMITIVE_TYPE', + 'mmVGT_PRIMITIVE_TYPE_BASE_IDX', 'mmVGT_REUSE_OFF', + 'mmVGT_REUSE_OFF_BASE_IDX', 'mmVGT_SHADER_STAGES_EN', + 'mmVGT_SHADER_STAGES_EN_BASE_IDX', 'mmVGT_STRMOUT_BUFFER_CONFIG', + 'mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX', + 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0', + 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX', + 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1', + 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX', + 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2', + 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX', + 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3', + 'mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX', + 'mmVGT_STRMOUT_BUFFER_OFFSET_0', + 'mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX', + 'mmVGT_STRMOUT_BUFFER_OFFSET_1', + 'mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX', + 'mmVGT_STRMOUT_BUFFER_OFFSET_2', + 'mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX', + 'mmVGT_STRMOUT_BUFFER_OFFSET_3', + 'mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX', + 'mmVGT_STRMOUT_BUFFER_SIZE_0', + 'mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX', + 'mmVGT_STRMOUT_BUFFER_SIZE_1', + 'mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX', + 'mmVGT_STRMOUT_BUFFER_SIZE_2', + 'mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX', + 'mmVGT_STRMOUT_BUFFER_SIZE_3', + 'mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX', 'mmVGT_STRMOUT_CONFIG', + 'mmVGT_STRMOUT_CONFIG_BASE_IDX', 'mmVGT_STRMOUT_DELAY', + 'mmVGT_STRMOUT_DELAY_BASE_IDX', + 'mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE', + 'mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX', + 'mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET', + 'mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX', + 'mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE', + 'mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX', + 'mmVGT_STRMOUT_VTX_STRIDE_0', + 'mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX', + 'mmVGT_STRMOUT_VTX_STRIDE_1', + 'mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX', + 'mmVGT_STRMOUT_VTX_STRIDE_2', + 'mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX', + 'mmVGT_STRMOUT_VTX_STRIDE_3', + 'mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX', 'mmVGT_SYS_CONFIG', + 'mmVGT_SYS_CONFIG_BASE_IDX', 'mmVGT_TESS_DISTRIBUTION', + 'mmVGT_TESS_DISTRIBUTION_BASE_IDX', 'mmVGT_TF_MEMORY_BASE', + 'mmVGT_TF_MEMORY_BASE_BASE_IDX', 'mmVGT_TF_MEMORY_BASE_HI', + 'mmVGT_TF_MEMORY_BASE_HI_BASE_IDX', 'mmVGT_TF_MEMORY_BASE_HI_UMD', + 'mmVGT_TF_MEMORY_BASE_HI_UMD_BASE_IDX', + 'mmVGT_TF_MEMORY_BASE_UMD', 'mmVGT_TF_MEMORY_BASE_UMD_BASE_IDX', + 'mmVGT_TF_PARAM', 'mmVGT_TF_PARAM_BASE_IDX', 'mmVGT_TF_RING_SIZE', + 'mmVGT_TF_RING_SIZE_BASE_IDX', 'mmVGT_TF_RING_SIZE_UMD', + 'mmVGT_TF_RING_SIZE_UMD_BASE_IDX', + 'mmVGT_VERTEX_REUSE_BLOCK_CNTL', + 'mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX', 'mmVGT_VS_MAX_WAVE_ID', + 'mmVGT_VS_MAX_WAVE_ID_BASE_IDX', 'mmVGT_VTX_CNT_EN', + 'mmVGT_VTX_CNT_EN_BASE_IDX', 'mmVGT_VTX_VECT_EJECT_REG', + 'mmVGT_VTX_VECT_EJECT_REG_BASE_IDX', + 'mmVIOLATION_DATA_ASYNC_VF_PROG', + 'mmVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX', 'mmWD_BUF_RESOURCE_1', + 'mmWD_BUF_RESOURCE_1_BASE_IDX', 'mmWD_BUF_RESOURCE_2', + 'mmWD_BUF_RESOURCE_2_BASE_IDX', 'mmWD_CNTL_SB_BUF_BASE', + 'mmWD_CNTL_SB_BUF_BASE_BASE_IDX', 'mmWD_CNTL_SB_BUF_BASE_HI', + 'mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX', 'mmWD_CNTL_STATUS', + 'mmWD_CNTL_STATUS_BASE_IDX', 'mmWD_ENHANCE', + 'mmWD_ENHANCE_BASE_IDX', 'mmWD_INDEX_BUF_BASE', + 'mmWD_INDEX_BUF_BASE_BASE_IDX', 'mmWD_INDEX_BUF_BASE_HI', + 'mmWD_INDEX_BUF_BASE_HI_BASE_IDX', 'mmWD_POS_BUF_BASE', + 'mmWD_POS_BUF_BASE_BASE_IDX', 'mmWD_POS_BUF_BASE_HI', + 'mmWD_POS_BUF_BASE_HI_BASE_IDX', 'mmWD_QOS', 'mmWD_QOS_BASE_IDX', + 'mmWD_UTCL1_CNTL', 'mmWD_UTCL1_CNTL_BASE_IDX', + 'mmWD_UTCL1_STATUS', 'mmWD_UTCL1_STATUS_BASE_IDX', + 'pq_exe_status__mec_release_mem__default', + 'pq_exe_status__mec_release_mem__phase_update', 'regCB_BLEND0_CONTROL', 'regCB_BLEND0_CONTROL_BASE_IDX', 'regCB_BLEND1_CONTROL', 'regCB_BLEND1_CONTROL_BASE_IDX', 'regCB_BLEND2_CONTROL', 'regCB_BLEND2_CONTROL_BASE_IDX', @@ -22006,7 +89003,8 @@ __all__ = \ 'regWD_UTCL1_CNTL', 'regWD_UTCL1_CNTL_BASE_IDX', 'regWD_UTCL1_STATUS', 'regWD_UTCL1_STATUS_BASE_IDX', 'struct_IP_BASE', 'struct_IP_BASE_INSTANCE', - 'struct_SDMA_PKT_ATOMIC_TAG', 'struct_SDMA_PKT_ATOMIC_TAG_0_0', + 'struct_PM4_MES_TYPE_3_HEADER_0', 'struct_SDMA_PKT_ATOMIC_TAG', + 'struct_SDMA_PKT_ATOMIC_TAG_0_0', 'struct_SDMA_PKT_ATOMIC_TAG_1_0', 'struct_SDMA_PKT_ATOMIC_TAG_2_0', 'struct_SDMA_PKT_ATOMIC_TAG_3_0', @@ -22060,6 +89058,16 @@ __all__ = \ 'struct_SDMA_PKT_TIMESTAMP_TAG_1_0', 'struct_SDMA_PKT_TIMESTAMP_TAG_2_0', 'struct_SDMA_PKT_TRAP_TAG', 'struct_SDMA_PKT_TRAP_TAG_0_0', 'struct_SDMA_PKT_TRAP_TAG_1_0', + 'struct_pm4_mec_release_mem', + 'struct_pm4_mec_release_mem_1_bitfields2', + 'struct_pm4_mec_release_mem_2_bitfields3', + 'struct_pm4_mec_release_mem_3_bitfields4', + 'struct_pm4_mec_release_mem_3_bitfields4b', + 'struct_pm4_mec_release_mem_5_bitfields6c', + 'struct_pm4_mec_write_data_mmio', + 'struct_pm4_mec_write_data_mmio_1_bitfields2', + 'struct_pm4_mec_write_data_mmio_2_bitfields3', 'uint32_t', + 'union_PM4_MES_TYPE_3_HEADER', 'union_SDMA_PKT_ATOMIC_TAG_ADDR_HI_UNION', 'union_SDMA_PKT_ATOMIC_TAG_ADDR_LO_UNION', 'union_SDMA_PKT_ATOMIC_TAG_CMP_DATA_HI_UNION', @@ -22112,4 +89120,12 @@ __all__ = \ 'union_SDMA_PKT_TIMESTAMP_TAG_ADDR_LO_UNION', 'union_SDMA_PKT_TIMESTAMP_TAG_HEADER_UNION', 'union_SDMA_PKT_TRAP_TAG_HEADER_UNION', - 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION'] + 'union_SDMA_PKT_TRAP_TAG_INT_CONTEXT_UNION', + 'union_pm4_mec_release_mem_0', 'union_pm4_mec_release_mem_1', + 'union_pm4_mec_release_mem_2', 'union_pm4_mec_release_mem_3', + 'union_pm4_mec_release_mem_4', 'union_pm4_mec_release_mem_5', + 'union_pm4_mec_release_mem_6', 'union_pm4_mec_write_data_mmio_0', + 'union_pm4_mec_write_data_mmio_1', + 'union_pm4_mec_write_data_mmio_2', + 'wr_confirm___write_data__do_not_wait_for_write_confirmation', + 'wr_confirm___write_data__wait_for_write_confirmation'] diff --git a/tinygrad_repo/tinygrad/runtime/autogen/comgr_3.py b/tinygrad_repo/tinygrad/runtime/autogen/comgr_3.py deleted file mode 100644 index 0fb7c920e..000000000 --- a/tinygrad_repo/tinygrad/runtime/autogen/comgr_3.py +++ /dev/null @@ -1,906 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: ['-D__HIP_PLATFORM_AMD__', '-I/opt/rocm/include', '-x', 'c++'] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util, os -PATHS_TO_TRY = [ - '/opt/rocm/lib/libamd_comgr.so', - os.getenv('ROCM_PATH', '')+'/lib/libamd_comgr.so', - '/usr/local/lib/libamd_comgr.dylib', - '/opt/homebrew/lib/libamd_comgr.dylib', -] -def _try_dlopen_amd_comgr(): - library = ctypes.util.find_library("amd_comgr") - if library: return ctypes.CDLL(library) - for candidate in PATHS_TO_TRY: - try: return ctypes.CDLL(candidate) - except OSError: pass - return None - - -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - -_libraries = {} -_libraries['libamd_comgr.so'] = _try_dlopen_amd_comgr() -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - - - - -# values for enumeration 'amd_comgr_status_s' -amd_comgr_status_s__enumvalues = { - 0: 'AMD_COMGR_STATUS_SUCCESS', - 1: 'AMD_COMGR_STATUS_ERROR', - 2: 'AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT', - 3: 'AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES', -} -AMD_COMGR_STATUS_SUCCESS = 0 -AMD_COMGR_STATUS_ERROR = 1 -AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT = 2 -AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES = 3 -amd_comgr_status_s = ctypes.c_uint32 # enum -amd_comgr_status_t = amd_comgr_status_s -amd_comgr_status_t__enumvalues = amd_comgr_status_s__enumvalues - -# values for enumeration 'amd_comgr_language_s' -amd_comgr_language_s__enumvalues = { - 0: 'AMD_COMGR_LANGUAGE_NONE', - 1: 'AMD_COMGR_LANGUAGE_OPENCL_1_2', - 2: 'AMD_COMGR_LANGUAGE_OPENCL_2_0', - 3: 'AMD_COMGR_LANGUAGE_HIP', - 4: 'AMD_COMGR_LANGUAGE_LLVM_IR', - 4: 'AMD_COMGR_LANGUAGE_LAST', -} -AMD_COMGR_LANGUAGE_NONE = 0 -AMD_COMGR_LANGUAGE_OPENCL_1_2 = 1 -AMD_COMGR_LANGUAGE_OPENCL_2_0 = 2 -AMD_COMGR_LANGUAGE_HIP = 3 -AMD_COMGR_LANGUAGE_LLVM_IR = 4 -AMD_COMGR_LANGUAGE_LAST = 4 -amd_comgr_language_s = ctypes.c_uint32 # enum -amd_comgr_language_t = amd_comgr_language_s -amd_comgr_language_t__enumvalues = amd_comgr_language_s__enumvalues -try: - amd_comgr_status_string = _libraries['libamd_comgr.so'].amd_comgr_status_string - amd_comgr_status_string.restype = amd_comgr_status_t - amd_comgr_status_string.argtypes = [amd_comgr_status_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - amd_comgr_get_version = _libraries['libamd_comgr.so'].amd_comgr_get_version - amd_comgr_get_version.restype = None - amd_comgr_get_version.argtypes = [ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_data_kind_s' -amd_comgr_data_kind_s__enumvalues = { - 0: 'AMD_COMGR_DATA_KIND_UNDEF', - 1: 'AMD_COMGR_DATA_KIND_SOURCE', - 2: 'AMD_COMGR_DATA_KIND_INCLUDE', - 3: 'AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER', - 4: 'AMD_COMGR_DATA_KIND_DIAGNOSTIC', - 5: 'AMD_COMGR_DATA_KIND_LOG', - 6: 'AMD_COMGR_DATA_KIND_BC', - 7: 'AMD_COMGR_DATA_KIND_RELOCATABLE', - 8: 'AMD_COMGR_DATA_KIND_EXECUTABLE', - 9: 'AMD_COMGR_DATA_KIND_BYTES', - 16: 'AMD_COMGR_DATA_KIND_FATBIN', - 17: 'AMD_COMGR_DATA_KIND_AR', - 18: 'AMD_COMGR_DATA_KIND_BC_BUNDLE', - 19: 'AMD_COMGR_DATA_KIND_AR_BUNDLE', - 20: 'AMD_COMGR_DATA_KIND_OBJ_BUNDLE', - 21: 'AMD_COMGR_DATA_KIND_SPIRV', - 21: 'AMD_COMGR_DATA_KIND_LAST', -} -AMD_COMGR_DATA_KIND_UNDEF = 0 -AMD_COMGR_DATA_KIND_SOURCE = 1 -AMD_COMGR_DATA_KIND_INCLUDE = 2 -AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER = 3 -AMD_COMGR_DATA_KIND_DIAGNOSTIC = 4 -AMD_COMGR_DATA_KIND_LOG = 5 -AMD_COMGR_DATA_KIND_BC = 6 -AMD_COMGR_DATA_KIND_RELOCATABLE = 7 -AMD_COMGR_DATA_KIND_EXECUTABLE = 8 -AMD_COMGR_DATA_KIND_BYTES = 9 -AMD_COMGR_DATA_KIND_FATBIN = 16 -AMD_COMGR_DATA_KIND_AR = 17 -AMD_COMGR_DATA_KIND_BC_BUNDLE = 18 -AMD_COMGR_DATA_KIND_AR_BUNDLE = 19 -AMD_COMGR_DATA_KIND_OBJ_BUNDLE = 20 -AMD_COMGR_DATA_KIND_SPIRV = 21 -AMD_COMGR_DATA_KIND_LAST = 21 -amd_comgr_data_kind_s = ctypes.c_uint32 # enum -amd_comgr_data_kind_t = amd_comgr_data_kind_s -amd_comgr_data_kind_t__enumvalues = amd_comgr_data_kind_s__enumvalues -class struct_amd_comgr_data_s(Structure): - pass - -struct_amd_comgr_data_s._pack_ = 1 # source:False -struct_amd_comgr_data_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_data_t = struct_amd_comgr_data_s -class struct_amd_comgr_data_set_s(Structure): - pass - -struct_amd_comgr_data_set_s._pack_ = 1 # source:False -struct_amd_comgr_data_set_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_data_set_t = struct_amd_comgr_data_set_s -class struct_amd_comgr_action_info_s(Structure): - pass - -struct_amd_comgr_action_info_s._pack_ = 1 # source:False -struct_amd_comgr_action_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_action_info_t = struct_amd_comgr_action_info_s -class struct_amd_comgr_metadata_node_s(Structure): - pass - -struct_amd_comgr_metadata_node_s._pack_ = 1 # source:False -struct_amd_comgr_metadata_node_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_metadata_node_t = struct_amd_comgr_metadata_node_s -class struct_amd_comgr_symbol_s(Structure): - pass - -struct_amd_comgr_symbol_s._pack_ = 1 # source:False -struct_amd_comgr_symbol_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_symbol_t = struct_amd_comgr_symbol_s -class struct_amd_comgr_disassembly_info_s(Structure): - pass - -struct_amd_comgr_disassembly_info_s._pack_ = 1 # source:False -struct_amd_comgr_disassembly_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_disassembly_info_t = struct_amd_comgr_disassembly_info_s -class struct_amd_comgr_symbolizer_info_s(Structure): - pass - -struct_amd_comgr_symbolizer_info_s._pack_ = 1 # source:False -struct_amd_comgr_symbolizer_info_s._fields_ = [ - ('handle', ctypes.c_uint64), -] - -amd_comgr_symbolizer_info_t = struct_amd_comgr_symbolizer_info_s -try: - amd_comgr_get_isa_count = _libraries['libamd_comgr.so'].amd_comgr_get_isa_count - amd_comgr_get_isa_count.restype = amd_comgr_status_t - amd_comgr_get_isa_count.argtypes = [ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -size_t = ctypes.c_uint64 -try: - amd_comgr_get_isa_name = _libraries['libamd_comgr.so'].amd_comgr_get_isa_name - amd_comgr_get_isa_name.restype = amd_comgr_status_t - amd_comgr_get_isa_name.argtypes = [size_t, ctypes.POINTER(ctypes.POINTER(ctypes.c_char))] -except AttributeError: - pass -try: - amd_comgr_get_isa_metadata = _libraries['libamd_comgr.so'].amd_comgr_get_isa_metadata - amd_comgr_get_isa_metadata.restype = amd_comgr_status_t - amd_comgr_get_isa_metadata.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_create_data = _libraries['libamd_comgr.so'].amd_comgr_create_data - amd_comgr_create_data.restype = amd_comgr_status_t - amd_comgr_create_data.argtypes = [amd_comgr_data_kind_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_release_data = _libraries['libamd_comgr.so'].amd_comgr_release_data - amd_comgr_release_data.restype = amd_comgr_status_t - amd_comgr_release_data.argtypes = [amd_comgr_data_t] -except AttributeError: - pass -try: - amd_comgr_get_data_kind = _libraries['libamd_comgr.so'].amd_comgr_get_data_kind - amd_comgr_get_data_kind.restype = amd_comgr_status_t - amd_comgr_get_data_kind.argtypes = [amd_comgr_data_t, ctypes.POINTER(amd_comgr_data_kind_s)] -except AttributeError: - pass -try: - amd_comgr_set_data = _libraries['libamd_comgr.so'].amd_comgr_set_data - amd_comgr_set_data.restype = amd_comgr_status_t - amd_comgr_set_data.argtypes = [amd_comgr_data_t, size_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -uint64_t = ctypes.c_uint64 -try: - amd_comgr_set_data_from_file_slice = _libraries['libamd_comgr.so'].amd_comgr_set_data_from_file_slice - amd_comgr_set_data_from_file_slice.restype = amd_comgr_status_t - amd_comgr_set_data_from_file_slice.argtypes = [amd_comgr_data_t, ctypes.c_int32, uint64_t, uint64_t] -except AttributeError: - pass -try: - amd_comgr_set_data_name = _libraries['libamd_comgr.so'].amd_comgr_set_data_name - amd_comgr_set_data_name.restype = amd_comgr_status_t - amd_comgr_set_data_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data = _libraries['libamd_comgr.so'].amd_comgr_get_data - amd_comgr_get_data.restype = amd_comgr_status_t - amd_comgr_get_data.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data_name = _libraries['libamd_comgr.so'].amd_comgr_get_data_name - amd_comgr_get_data_name.restype = amd_comgr_status_t - amd_comgr_get_data_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_data_isa_name = _libraries['libamd_comgr.so'].amd_comgr_get_data_isa_name - amd_comgr_get_data_isa_name.restype = amd_comgr_status_t - amd_comgr_get_data_isa_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_create_symbolizer_info = _libraries['libamd_comgr.so'].amd_comgr_create_symbolizer_info - amd_comgr_create_symbolizer_info.restype = amd_comgr_status_t - amd_comgr_create_symbolizer_info.argtypes = [amd_comgr_data_t, ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)), ctypes.POINTER(struct_amd_comgr_symbolizer_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_symbolizer_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_symbolizer_info - amd_comgr_destroy_symbolizer_info.restype = amd_comgr_status_t - amd_comgr_destroy_symbolizer_info.argtypes = [amd_comgr_symbolizer_info_t] -except AttributeError: - pass -try: - amd_comgr_symbolize = _libraries['libamd_comgr.so'].amd_comgr_symbolize - amd_comgr_symbolize.restype = amd_comgr_status_t - amd_comgr_symbolize.argtypes = [amd_comgr_symbolizer_info_t, uint64_t, ctypes.c_bool, ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_get_data_metadata = _libraries['libamd_comgr.so'].amd_comgr_get_data_metadata - amd_comgr_get_data_metadata.restype = amd_comgr_status_t - amd_comgr_get_data_metadata.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_metadata = _libraries['libamd_comgr.so'].amd_comgr_destroy_metadata - amd_comgr_destroy_metadata.restype = amd_comgr_status_t - amd_comgr_destroy_metadata.argtypes = [amd_comgr_metadata_node_t] -except AttributeError: - pass -try: - amd_comgr_create_data_set = _libraries['libamd_comgr.so'].amd_comgr_create_data_set - amd_comgr_create_data_set.restype = amd_comgr_status_t - amd_comgr_create_data_set.argtypes = [ctypes.POINTER(struct_amd_comgr_data_set_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_data_set = _libraries['libamd_comgr.so'].amd_comgr_destroy_data_set - amd_comgr_destroy_data_set.restype = amd_comgr_status_t - amd_comgr_destroy_data_set.argtypes = [amd_comgr_data_set_t] -except AttributeError: - pass -try: - amd_comgr_data_set_add = _libraries['libamd_comgr.so'].amd_comgr_data_set_add - amd_comgr_data_set_add.restype = amd_comgr_status_t - amd_comgr_data_set_add.argtypes = [amd_comgr_data_set_t, amd_comgr_data_t] -except AttributeError: - pass -try: - amd_comgr_data_set_remove = _libraries['libamd_comgr.so'].amd_comgr_data_set_remove - amd_comgr_data_set_remove.restype = amd_comgr_status_t - amd_comgr_data_set_remove.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t] -except AttributeError: - pass -try: - amd_comgr_action_data_count = _libraries['libamd_comgr.so'].amd_comgr_action_data_count - amd_comgr_action_data_count.restype = amd_comgr_status_t - amd_comgr_action_data_count.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_data_get_data = _libraries['libamd_comgr.so'].amd_comgr_action_data_get_data - amd_comgr_action_data_get_data.restype = amd_comgr_status_t - amd_comgr_action_data_get_data.argtypes = [amd_comgr_data_set_t, amd_comgr_data_kind_t, size_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_create_action_info = _libraries['libamd_comgr.so'].amd_comgr_create_action_info - amd_comgr_create_action_info.restype = amd_comgr_status_t - amd_comgr_create_action_info.argtypes = [ctypes.POINTER(struct_amd_comgr_action_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_action_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_action_info - amd_comgr_destroy_action_info.restype = amd_comgr_status_t - amd_comgr_destroy_action_info.argtypes = [amd_comgr_action_info_t] -except AttributeError: - pass -try: - amd_comgr_action_info_set_isa_name = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_isa_name - amd_comgr_action_info_set_isa_name.restype = amd_comgr_status_t - amd_comgr_action_info_set_isa_name.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_isa_name = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_isa_name - amd_comgr_action_info_get_isa_name.restype = amd_comgr_status_t - amd_comgr_action_info_get_isa_name.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_language = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_language - amd_comgr_action_info_set_language.restype = amd_comgr_status_t - amd_comgr_action_info_set_language.argtypes = [amd_comgr_action_info_t, amd_comgr_language_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_language = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_language - amd_comgr_action_info_get_language.restype = amd_comgr_status_t - amd_comgr_action_info_get_language.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(amd_comgr_language_s)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_option_list = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_option_list - amd_comgr_action_info_set_option_list.restype = amd_comgr_status_t - amd_comgr_action_info_set_option_list.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char) * 0, size_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_option_list_count = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_option_list_count - amd_comgr_action_info_get_option_list_count.restype = amd_comgr_status_t - amd_comgr_action_info_get_option_list_count.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_option_list_item = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_option_list_item - amd_comgr_action_info_get_option_list_item.restype = amd_comgr_status_t - amd_comgr_action_info_get_option_list_item.argtypes = [amd_comgr_action_info_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_bundle_entry_ids = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_bundle_entry_ids - amd_comgr_action_info_set_bundle_entry_ids.restype = amd_comgr_status_t - amd_comgr_action_info_set_bundle_entry_ids.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char) * 0, size_t] -except AttributeError: - pass -try: - amd_comgr_action_info_get_bundle_entry_id_count = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_bundle_entry_id_count - amd_comgr_action_info_get_bundle_entry_id_count.restype = amd_comgr_status_t - amd_comgr_action_info_get_bundle_entry_id_count.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_bundle_entry_id = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_bundle_entry_id - amd_comgr_action_info_get_bundle_entry_id.restype = amd_comgr_status_t - amd_comgr_action_info_get_bundle_entry_id.argtypes = [amd_comgr_action_info_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_device_lib_linking = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_device_lib_linking - amd_comgr_action_info_set_device_lib_linking.restype = amd_comgr_status_t - amd_comgr_action_info_set_device_lib_linking.argtypes = [amd_comgr_action_info_t, ctypes.c_bool] -except AttributeError: - pass -try: - amd_comgr_action_info_set_working_directory_path = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_working_directory_path - amd_comgr_action_info_set_working_directory_path.restype = amd_comgr_status_t - amd_comgr_action_info_set_working_directory_path.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_get_working_directory_path = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_working_directory_path - amd_comgr_action_info_get_working_directory_path.restype = amd_comgr_status_t - amd_comgr_action_info_get_working_directory_path.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_action_info_set_logging = _libraries['libamd_comgr.so'].amd_comgr_action_info_set_logging - amd_comgr_action_info_set_logging.restype = amd_comgr_status_t - amd_comgr_action_info_set_logging.argtypes = [amd_comgr_action_info_t, ctypes.c_bool] -except AttributeError: - pass -try: - amd_comgr_action_info_get_logging = _libraries['libamd_comgr.so'].amd_comgr_action_info_get_logging - amd_comgr_action_info_get_logging.restype = amd_comgr_status_t - amd_comgr_action_info_get_logging.argtypes = [amd_comgr_action_info_t, ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_action_kind_s' -amd_comgr_action_kind_s__enumvalues = { - 0: 'AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR', - 1: 'AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS', - 2: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC', - 3: 'AMD_COMGR_ACTION_LINK_BC_TO_BC', - 4: 'AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE', - 5: 'AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY', - 6: 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE', - 7: 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE', - 8: 'AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE', - 9: 'AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE', - 10: 'AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE', - 11: 'AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE', - 12: 'AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC', - 13: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE', - 14: 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE', - 15: 'AMD_COMGR_ACTION_UNBUNDLE', - 19: 'AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC', - 19: 'AMD_COMGR_ACTION_LAST', -} -AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR = 0 -AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS = 1 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC = 2 -AMD_COMGR_ACTION_LINK_BC_TO_BC = 3 -AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE = 4 -AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY = 5 -AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE = 6 -AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE = 7 -AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE = 8 -AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE = 9 -AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE = 10 -AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE = 11 -AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC = 12 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE = 13 -AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE = 14 -AMD_COMGR_ACTION_UNBUNDLE = 15 -AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC = 19 -AMD_COMGR_ACTION_LAST = 19 -amd_comgr_action_kind_s = ctypes.c_uint32 # enum -amd_comgr_action_kind_t = amd_comgr_action_kind_s -amd_comgr_action_kind_t__enumvalues = amd_comgr_action_kind_s__enumvalues -try: - amd_comgr_do_action = _libraries['libamd_comgr.so'].amd_comgr_do_action - amd_comgr_do_action.restype = amd_comgr_status_t - amd_comgr_do_action.argtypes = [amd_comgr_action_kind_t, amd_comgr_action_info_t, amd_comgr_data_set_t, amd_comgr_data_set_t] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_metadata_kind_s' -amd_comgr_metadata_kind_s__enumvalues = { - 0: 'AMD_COMGR_METADATA_KIND_NULL', - 1: 'AMD_COMGR_METADATA_KIND_STRING', - 2: 'AMD_COMGR_METADATA_KIND_MAP', - 3: 'AMD_COMGR_METADATA_KIND_LIST', - 3: 'AMD_COMGR_METADATA_KIND_LAST', -} -AMD_COMGR_METADATA_KIND_NULL = 0 -AMD_COMGR_METADATA_KIND_STRING = 1 -AMD_COMGR_METADATA_KIND_MAP = 2 -AMD_COMGR_METADATA_KIND_LIST = 3 -AMD_COMGR_METADATA_KIND_LAST = 3 -amd_comgr_metadata_kind_s = ctypes.c_uint32 # enum -amd_comgr_metadata_kind_t = amd_comgr_metadata_kind_s -amd_comgr_metadata_kind_t__enumvalues = amd_comgr_metadata_kind_s__enumvalues -try: - amd_comgr_get_metadata_kind = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_kind - amd_comgr_get_metadata_kind.restype = amd_comgr_status_t - amd_comgr_get_metadata_kind.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(amd_comgr_metadata_kind_s)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_string = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_string - amd_comgr_get_metadata_string.restype = amd_comgr_status_t - amd_comgr_get_metadata_string.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_map_size = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_map_size - amd_comgr_get_metadata_map_size.restype = amd_comgr_status_t - amd_comgr_get_metadata_map_size.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_iterate_map_metadata = _libraries['libamd_comgr.so'].amd_comgr_iterate_map_metadata - amd_comgr_iterate_map_metadata.restype = amd_comgr_status_t - amd_comgr_iterate_map_metadata.argtypes = [amd_comgr_metadata_node_t, ctypes.CFUNCTYPE(amd_comgr_status_s, struct_amd_comgr_metadata_node_s, struct_amd_comgr_metadata_node_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_metadata_lookup = _libraries['libamd_comgr.so'].amd_comgr_metadata_lookup - amd_comgr_metadata_lookup.restype = amd_comgr_status_t - amd_comgr_metadata_lookup.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_get_metadata_list_size = _libraries['libamd_comgr.so'].amd_comgr_get_metadata_list_size - amd_comgr_get_metadata_list_size.restype = amd_comgr_status_t - amd_comgr_get_metadata_list_size.argtypes = [amd_comgr_metadata_node_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_index_list_metadata = _libraries['libamd_comgr.so'].amd_comgr_index_list_metadata - amd_comgr_index_list_metadata.restype = amd_comgr_status_t - amd_comgr_index_list_metadata.argtypes = [amd_comgr_metadata_node_t, size_t, ctypes.POINTER(struct_amd_comgr_metadata_node_s)] -except AttributeError: - pass -try: - amd_comgr_iterate_symbols = _libraries['libamd_comgr.so'].amd_comgr_iterate_symbols - amd_comgr_iterate_symbols.restype = amd_comgr_status_t - amd_comgr_iterate_symbols.argtypes = [amd_comgr_data_t, ctypes.CFUNCTYPE(amd_comgr_status_s, struct_amd_comgr_symbol_s, ctypes.POINTER(None)), ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_symbol_lookup = _libraries['libamd_comgr.so'].amd_comgr_symbol_lookup - amd_comgr_symbol_lookup.restype = amd_comgr_status_t - amd_comgr_symbol_lookup.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(struct_amd_comgr_symbol_s)] -except AttributeError: - pass - -# values for enumeration 'amd_comgr_symbol_type_s' -amd_comgr_symbol_type_s__enumvalues = { - -1: 'AMD_COMGR_SYMBOL_TYPE_UNKNOWN', - 0: 'AMD_COMGR_SYMBOL_TYPE_NOTYPE', - 1: 'AMD_COMGR_SYMBOL_TYPE_OBJECT', - 2: 'AMD_COMGR_SYMBOL_TYPE_FUNC', - 3: 'AMD_COMGR_SYMBOL_TYPE_SECTION', - 4: 'AMD_COMGR_SYMBOL_TYPE_FILE', - 5: 'AMD_COMGR_SYMBOL_TYPE_COMMON', - 10: 'AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL', -} -AMD_COMGR_SYMBOL_TYPE_UNKNOWN = -1 -AMD_COMGR_SYMBOL_TYPE_NOTYPE = 0 -AMD_COMGR_SYMBOL_TYPE_OBJECT = 1 -AMD_COMGR_SYMBOL_TYPE_FUNC = 2 -AMD_COMGR_SYMBOL_TYPE_SECTION = 3 -AMD_COMGR_SYMBOL_TYPE_FILE = 4 -AMD_COMGR_SYMBOL_TYPE_COMMON = 5 -AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL = 10 -amd_comgr_symbol_type_s = ctypes.c_int32 # enum -amd_comgr_symbol_type_t = amd_comgr_symbol_type_s -amd_comgr_symbol_type_t__enumvalues = amd_comgr_symbol_type_s__enumvalues - -# values for enumeration 'amd_comgr_symbol_info_s' -amd_comgr_symbol_info_s__enumvalues = { - 0: 'AMD_COMGR_SYMBOL_INFO_NAME_LENGTH', - 1: 'AMD_COMGR_SYMBOL_INFO_NAME', - 2: 'AMD_COMGR_SYMBOL_INFO_TYPE', - 3: 'AMD_COMGR_SYMBOL_INFO_SIZE', - 4: 'AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED', - 5: 'AMD_COMGR_SYMBOL_INFO_VALUE', - 5: 'AMD_COMGR_SYMBOL_INFO_LAST', -} -AMD_COMGR_SYMBOL_INFO_NAME_LENGTH = 0 -AMD_COMGR_SYMBOL_INFO_NAME = 1 -AMD_COMGR_SYMBOL_INFO_TYPE = 2 -AMD_COMGR_SYMBOL_INFO_SIZE = 3 -AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED = 4 -AMD_COMGR_SYMBOL_INFO_VALUE = 5 -AMD_COMGR_SYMBOL_INFO_LAST = 5 -amd_comgr_symbol_info_s = ctypes.c_uint32 # enum -amd_comgr_symbol_info_t = amd_comgr_symbol_info_s -amd_comgr_symbol_info_t__enumvalues = amd_comgr_symbol_info_s__enumvalues -try: - amd_comgr_symbol_get_info = _libraries['libamd_comgr.so'].amd_comgr_symbol_get_info - amd_comgr_symbol_get_info.restype = amd_comgr_status_t - amd_comgr_symbol_get_info.argtypes = [amd_comgr_symbol_t, amd_comgr_symbol_info_t, ctypes.POINTER(None)] -except AttributeError: - pass -try: - amd_comgr_create_disassembly_info = _libraries['libamd_comgr.so'].amd_comgr_create_disassembly_info - amd_comgr_create_disassembly_info.restype = amd_comgr_status_t - amd_comgr_create_disassembly_info.argtypes = [ctypes.POINTER(ctypes.c_char), ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.c_uint64, ctypes.POINTER(ctypes.c_char), ctypes.c_uint64, ctypes.POINTER(None)), ctypes.CFUNCTYPE(None, ctypes.POINTER(ctypes.c_char), ctypes.POINTER(None)), ctypes.CFUNCTYPE(None, ctypes.c_uint64, ctypes.POINTER(None)), ctypes.POINTER(struct_amd_comgr_disassembly_info_s)] -except AttributeError: - pass -try: - amd_comgr_destroy_disassembly_info = _libraries['libamd_comgr.so'].amd_comgr_destroy_disassembly_info - amd_comgr_destroy_disassembly_info.restype = amd_comgr_status_t - amd_comgr_destroy_disassembly_info.argtypes = [amd_comgr_disassembly_info_t] -except AttributeError: - pass -try: - amd_comgr_disassemble_instruction = _libraries['libamd_comgr.so'].amd_comgr_disassemble_instruction - amd_comgr_disassemble_instruction.restype = amd_comgr_status_t - amd_comgr_disassemble_instruction.argtypes = [amd_comgr_disassembly_info_t, uint64_t, ctypes.POINTER(None), ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_demangle_symbol_name = _libraries['libamd_comgr.so'].amd_comgr_demangle_symbol_name - amd_comgr_demangle_symbol_name.restype = amd_comgr_status_t - amd_comgr_demangle_symbol_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_amd_comgr_data_s)] -except AttributeError: - pass -try: - amd_comgr_populate_mangled_names = _libraries['libamd_comgr.so'].amd_comgr_populate_mangled_names - amd_comgr_populate_mangled_names.restype = amd_comgr_status_t - amd_comgr_populate_mangled_names.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_get_mangled_name = _libraries['libamd_comgr.so'].amd_comgr_get_mangled_name - amd_comgr_get_mangled_name.restype = amd_comgr_status_t - amd_comgr_get_mangled_name.argtypes = [amd_comgr_data_t, size_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -try: - amd_comgr_populate_name_expression_map = _libraries['libamd_comgr.so'].amd_comgr_populate_name_expression_map - amd_comgr_populate_name_expression_map.restype = amd_comgr_status_t - amd_comgr_populate_name_expression_map.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64)] -except AttributeError: - pass -try: - amd_comgr_map_name_expression_to_symbol_name = _libraries['libamd_comgr.so'].amd_comgr_map_name_expression_to_symbol_name - amd_comgr_map_name_expression_to_symbol_name.restype = amd_comgr_status_t - amd_comgr_map_name_expression_to_symbol_name.argtypes = [amd_comgr_data_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_char), ctypes.POINTER(ctypes.c_char)] -except AttributeError: - pass -class struct_code_object_info_s(Structure): - pass - -struct_code_object_info_s._pack_ = 1 # source:False -struct_code_object_info_s._fields_ = [ - ('isa', ctypes.POINTER(ctypes.c_char)), - ('size', ctypes.c_uint64), - ('offset', ctypes.c_uint64), -] - -amd_comgr_code_object_info_t = struct_code_object_info_s -try: - amd_comgr_lookup_code_object = _libraries['libamd_comgr.so'].amd_comgr_lookup_code_object - amd_comgr_lookup_code_object.restype = amd_comgr_status_t - amd_comgr_lookup_code_object.argtypes = [amd_comgr_data_t, ctypes.POINTER(struct_code_object_info_s), size_t] -except AttributeError: - pass -try: - amd_comgr_map_elf_virtual_address_to_code_object_offset = _libraries['libamd_comgr.so'].amd_comgr_map_elf_virtual_address_to_code_object_offset - amd_comgr_map_elf_virtual_address_to_code_object_offset.restype = amd_comgr_status_t - amd_comgr_map_elf_virtual_address_to_code_object_offset.argtypes = [amd_comgr_data_t, uint64_t, ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_uint64), ctypes.POINTER(ctypes.c_bool)] -except AttributeError: - pass -__all__ = \ - ['AMD_COMGR_ACTION_ADD_PRECOMPILED_HEADERS', - 'AMD_COMGR_ACTION_ASSEMBLE_SOURCE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_CODEGEN_BC_TO_ASSEMBLY', - 'AMD_COMGR_ACTION_CODEGEN_BC_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_BC', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_EXECUTABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_COMPILE_SOURCE_WITH_DEVICE_LIBS_TO_BC', - 'AMD_COMGR_ACTION_DISASSEMBLE_BYTES_TO_SOURCE', - 'AMD_COMGR_ACTION_DISASSEMBLE_EXECUTABLE_TO_SOURCE', - 'AMD_COMGR_ACTION_DISASSEMBLE_RELOCATABLE_TO_SOURCE', - 'AMD_COMGR_ACTION_LAST', 'AMD_COMGR_ACTION_LINK_BC_TO_BC', - 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_EXECUTABLE', - 'AMD_COMGR_ACTION_LINK_RELOCATABLE_TO_RELOCATABLE', - 'AMD_COMGR_ACTION_SOURCE_TO_PREPROCESSOR', - 'AMD_COMGR_ACTION_TRANSLATE_SPIRV_TO_BC', - 'AMD_COMGR_ACTION_UNBUNDLE', 'AMD_COMGR_DATA_KIND_AR', - 'AMD_COMGR_DATA_KIND_AR_BUNDLE', 'AMD_COMGR_DATA_KIND_BC', - 'AMD_COMGR_DATA_KIND_BC_BUNDLE', 'AMD_COMGR_DATA_KIND_BYTES', - 'AMD_COMGR_DATA_KIND_DIAGNOSTIC', - 'AMD_COMGR_DATA_KIND_EXECUTABLE', 'AMD_COMGR_DATA_KIND_FATBIN', - 'AMD_COMGR_DATA_KIND_INCLUDE', 'AMD_COMGR_DATA_KIND_LAST', - 'AMD_COMGR_DATA_KIND_LOG', 'AMD_COMGR_DATA_KIND_OBJ_BUNDLE', - 'AMD_COMGR_DATA_KIND_PRECOMPILED_HEADER', - 'AMD_COMGR_DATA_KIND_RELOCATABLE', 'AMD_COMGR_DATA_KIND_SOURCE', - 'AMD_COMGR_DATA_KIND_SPIRV', 'AMD_COMGR_DATA_KIND_UNDEF', - 'AMD_COMGR_LANGUAGE_HIP', 'AMD_COMGR_LANGUAGE_LAST', - 'AMD_COMGR_LANGUAGE_LLVM_IR', 'AMD_COMGR_LANGUAGE_NONE', - 'AMD_COMGR_LANGUAGE_OPENCL_1_2', 'AMD_COMGR_LANGUAGE_OPENCL_2_0', - 'AMD_COMGR_METADATA_KIND_LAST', 'AMD_COMGR_METADATA_KIND_LIST', - 'AMD_COMGR_METADATA_KIND_MAP', 'AMD_COMGR_METADATA_KIND_NULL', - 'AMD_COMGR_METADATA_KIND_STRING', 'AMD_COMGR_STATUS_ERROR', - 'AMD_COMGR_STATUS_ERROR_INVALID_ARGUMENT', - 'AMD_COMGR_STATUS_ERROR_OUT_OF_RESOURCES', - 'AMD_COMGR_STATUS_SUCCESS', 'AMD_COMGR_SYMBOL_INFO_IS_UNDEFINED', - 'AMD_COMGR_SYMBOL_INFO_LAST', 'AMD_COMGR_SYMBOL_INFO_NAME', - 'AMD_COMGR_SYMBOL_INFO_NAME_LENGTH', 'AMD_COMGR_SYMBOL_INFO_SIZE', - 'AMD_COMGR_SYMBOL_INFO_TYPE', 'AMD_COMGR_SYMBOL_INFO_VALUE', - 'AMD_COMGR_SYMBOL_TYPE_AMDGPU_HSA_KERNEL', - 'AMD_COMGR_SYMBOL_TYPE_COMMON', 'AMD_COMGR_SYMBOL_TYPE_FILE', - 'AMD_COMGR_SYMBOL_TYPE_FUNC', 'AMD_COMGR_SYMBOL_TYPE_NOTYPE', - 'AMD_COMGR_SYMBOL_TYPE_OBJECT', 'AMD_COMGR_SYMBOL_TYPE_SECTION', - 'AMD_COMGR_SYMBOL_TYPE_UNKNOWN', 'amd_comgr_action_data_count', - 'amd_comgr_action_data_get_data', - 'amd_comgr_action_info_get_bundle_entry_id', - 'amd_comgr_action_info_get_bundle_entry_id_count', - 'amd_comgr_action_info_get_isa_name', - 'amd_comgr_action_info_get_language', - 'amd_comgr_action_info_get_logging', - 'amd_comgr_action_info_get_option_list_count', - 'amd_comgr_action_info_get_option_list_item', - 'amd_comgr_action_info_get_working_directory_path', - 'amd_comgr_action_info_set_bundle_entry_ids', - 'amd_comgr_action_info_set_device_lib_linking', - 'amd_comgr_action_info_set_isa_name', - 'amd_comgr_action_info_set_language', - 'amd_comgr_action_info_set_logging', - 'amd_comgr_action_info_set_option_list', - 'amd_comgr_action_info_set_working_directory_path', - 'amd_comgr_action_info_t', 'amd_comgr_action_kind_s', - 'amd_comgr_action_kind_t', 'amd_comgr_action_kind_t__enumvalues', - 'amd_comgr_code_object_info_t', 'amd_comgr_create_action_info', - 'amd_comgr_create_data', 'amd_comgr_create_data_set', - 'amd_comgr_create_disassembly_info', - 'amd_comgr_create_symbolizer_info', 'amd_comgr_data_kind_s', - 'amd_comgr_data_kind_t', 'amd_comgr_data_kind_t__enumvalues', - 'amd_comgr_data_set_add', 'amd_comgr_data_set_remove', - 'amd_comgr_data_set_t', 'amd_comgr_data_t', - 'amd_comgr_demangle_symbol_name', 'amd_comgr_destroy_action_info', - 'amd_comgr_destroy_data_set', - 'amd_comgr_destroy_disassembly_info', - 'amd_comgr_destroy_metadata', 'amd_comgr_destroy_symbolizer_info', - 'amd_comgr_disassemble_instruction', - 'amd_comgr_disassembly_info_t', 'amd_comgr_do_action', - 'amd_comgr_get_data', 'amd_comgr_get_data_isa_name', - 'amd_comgr_get_data_kind', 'amd_comgr_get_data_metadata', - 'amd_comgr_get_data_name', 'amd_comgr_get_isa_count', - 'amd_comgr_get_isa_metadata', 'amd_comgr_get_isa_name', - 'amd_comgr_get_mangled_name', 'amd_comgr_get_metadata_kind', - 'amd_comgr_get_metadata_list_size', - 'amd_comgr_get_metadata_map_size', - 'amd_comgr_get_metadata_string', 'amd_comgr_get_version', - 'amd_comgr_index_list_metadata', 'amd_comgr_iterate_map_metadata', - 'amd_comgr_iterate_symbols', 'amd_comgr_language_s', - 'amd_comgr_language_t', 'amd_comgr_language_t__enumvalues', - 'amd_comgr_lookup_code_object', - 'amd_comgr_map_elf_virtual_address_to_code_object_offset', - 'amd_comgr_map_name_expression_to_symbol_name', - 'amd_comgr_metadata_kind_s', 'amd_comgr_metadata_kind_t', - 'amd_comgr_metadata_kind_t__enumvalues', - 'amd_comgr_metadata_lookup', 'amd_comgr_metadata_node_t', - 'amd_comgr_populate_mangled_names', - 'amd_comgr_populate_name_expression_map', - 'amd_comgr_release_data', 'amd_comgr_set_data', - 'amd_comgr_set_data_from_file_slice', 'amd_comgr_set_data_name', - 'amd_comgr_status_s', 'amd_comgr_status_string', - 'amd_comgr_status_t', 'amd_comgr_status_t__enumvalues', - 'amd_comgr_symbol_get_info', 'amd_comgr_symbol_info_s', - 'amd_comgr_symbol_info_t', 'amd_comgr_symbol_info_t__enumvalues', - 'amd_comgr_symbol_lookup', 'amd_comgr_symbol_t', - 'amd_comgr_symbol_type_s', 'amd_comgr_symbol_type_t', - 'amd_comgr_symbol_type_t__enumvalues', 'amd_comgr_symbolize', - 'amd_comgr_symbolizer_info_t', 'size_t', - 'struct_amd_comgr_action_info_s', 'struct_amd_comgr_data_s', - 'struct_amd_comgr_data_set_s', - 'struct_amd_comgr_disassembly_info_s', - 'struct_amd_comgr_metadata_node_s', 'struct_amd_comgr_symbol_s', - 'struct_amd_comgr_symbolizer_info_s', 'struct_code_object_info_s', - 'uint64_t'] diff --git a/tinygrad_repo/tinygrad/runtime/autogen/ib.py b/tinygrad_repo/tinygrad/runtime/autogen/ib.py deleted file mode 100644 index 8ea06c22f..000000000 --- a/tinygrad_repo/tinygrad/runtime/autogen/ib.py +++ /dev/null @@ -1,7171 +0,0 @@ -# mypy: ignore-errors -# -*- coding: utf-8 -*- -# -# TARGET arch is: [] -# WORD_SIZE is: 8 -# POINTER_SIZE is: 8 -# LONGDOUBLE_SIZE is: 16 -# -import ctypes, ctypes.util - - -class AsDictMixin: - @classmethod - def as_dict(cls, self): - result = {} - if not isinstance(self, AsDictMixin): - # not a structure, assume it's already a python object - return self - if not hasattr(cls, "_fields_"): - return result - # sys.version_info >= (3, 5) - # for (field, *_) in cls._fields_: # noqa - for field_tuple in cls._fields_: # noqa - field = field_tuple[0] - if field.startswith('PADDING_'): - continue - value = getattr(self, field) - type_ = type(value) - if hasattr(value, "_length_") and hasattr(value, "_type_"): - # array - if not hasattr(type_, "as_dict"): - value = [v for v in value] - else: - type_ = type_._type_ - value = [type_.as_dict(v) for v in value] - elif hasattr(value, "contents") and hasattr(value, "_type_"): - # pointer - try: - if not hasattr(type_, "as_dict"): - value = value.contents - else: - type_ = type_._type_ - value = type_.as_dict(value.contents) - except ValueError: - # nullptr - value = None - elif isinstance(value, AsDictMixin): - # other structure - value = type_.as_dict(value) - result[field] = value - return result - - -class Structure(ctypes.Structure, AsDictMixin): - - def __init__(self, *args, **kwds): - # We don't want to use positional arguments fill PADDING_* fields - - args = dict(zip(self.__class__._field_names_(), args)) - args.update(kwds) - super(Structure, self).__init__(**args) - - @classmethod - def _field_names_(cls): - if hasattr(cls, '_fields_'): - return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) - else: - return () - - @classmethod - def get_type(cls, field): - for f in cls._fields_: - if f[0] == field: - return f[1] - return None - - @classmethod - def bind(cls, bound_fields): - fields = {} - for name, type_ in cls._fields_: - if hasattr(type_, "restype"): - if name in bound_fields: - if bound_fields[name] is None: - fields[name] = type_() - else: - # use a closure to capture the callback from the loop scope - fields[name] = ( - type_((lambda callback: lambda *args: callback(*args))( - bound_fields[name])) - ) - del bound_fields[name] - else: - # default callback implementation (does nothing) - try: - default_ = type_(0).restype().value - except TypeError: - default_ = None - fields[name] = type_(( - lambda default_: lambda *args: default_)(default_)) - else: - # not a callback function, use default initialization - if name in bound_fields: - fields[name] = bound_fields[name] - del bound_fields[name] - else: - fields[name] = type_() - if len(bound_fields) != 0: - raise ValueError( - "Cannot bind the following unknown callback(s) {}.{}".format( - cls.__name__, bound_fields.keys() - )) - return cls(**fields) - - -class Union(ctypes.Union, AsDictMixin): - pass - - - -c_int128 = ctypes.c_ubyte*16 -c_uint128 = c_int128 -void = None -if ctypes.sizeof(ctypes.c_longdouble) == 16: - c_long_double_t = ctypes.c_longdouble -else: - c_long_double_t = ctypes.c_ubyte*16 - -class FunctionFactoryStub: - def __getattr__(self, _): - return ctypes.CFUNCTYPE(lambda y:y) - -# libraries['libibverbs'] explanation -# As you did not list (-l libraryname.so) a library that exports this function -# This is a non-working stub instead. -# You can either re-run clan2py with -l /path/to/library.so -# Or manually fix this by comment the ctypes.CDLL loading -_libraries = {} -_libraries['libibverbs'] = ctypes.CDLL(ctypes.util.find_library('ibverbs'), use_errno=True) # ctypes.CDLL('libibverbs') -def string_cast(char_pointer, encoding='utf-8', errors='strict'): - value = ctypes.cast(char_pointer, ctypes.c_char_p).value - if value is not None and encoding is not None: - value = value.decode(encoding, errors=errors) - return value - - -def char_pointer_cast(string, encoding='utf-8'): - if encoding is not None: - try: - string = string.encode(encoding) - except AttributeError: - # In Python3, bytes has no encode attribute - pass - string = ctypes.c_char_p(string) - return ctypes.cast(string, ctypes.POINTER(ctypes.c_char)) - - - - - -INFINIBAND_VERBS_H = True # macro -VERBS_API_H = True # macro -# def RDMA_UAPI_PTR(_type, _name): # macro -# return {_type_name;__aligned_u64_name##_data_u64;} -IB_USER_IOCTL_VERBS_H = True # macro -IB_USER_VERBS_H = True # macro -IB_USER_VERBS_ABI_VERSION = 6 # macro -IB_USER_VERBS_CMD_THRESHOLD = 50 # macro -IB_USER_VERBS_CMD_COMMAND_MASK = 0xff # macro -IB_USER_VERBS_CMD_FLAG_EXTENDED = 0x80000000 # macro -IB_USER_VERBS_MAX_LOG_IND_TBL_SIZE = 0x0d # macro -IB_DEVICE_NAME_MAX = 64 # macro -IB_UVERBS_ACCESS_OPTIONAL_FIRST = (1<<20) # macro -IB_UVERBS_ACCESS_OPTIONAL_LAST = (1<<29) # macro -# ibv_flow_action_esp_keymat_aes_gcm = ib_uverbs_flow_action_esp_keymat_aes_gcm # macro -# ibv_flow_action_esp_replay_bmp = ib_uverbs_flow_action_esp_replay_bmp # macro -# ibv_flow_action_esp_encap = ib_uverbs_flow_action_esp_encap # macro -# ibv_flow_action_esp = ib_uverbs_flow_action_esp # macro -IBV_ACCESS_OPTIONAL_FIRST = (1<<20) # macro -__attribute_const = True # macro -# def vext_field_avail(type, fld, sz): # macro -# return (offsetof(type,fld)<(sz)) -# __VERBS_ABI_IS_EXTENDED = ((void*)UINTPTR_MAX) # macro -IBV_DEVICE_RAW_SCATTER_FCS = (1<<34) # macro -IBV_DEVICE_PCI_WRITE_END_PADDING = (1<<36) # macro -# IBV_ALLOCATOR_USE_DEFAULT = ((void*)-1) # macro -ETHERNET_LL_SIZE = 6 # macro -IB_ROCE_UDP_ENCAP_VALID_PORT_MIN = (0xC000) # macro -IB_ROCE_UDP_ENCAP_VALID_PORT_MAX = (0xFFFF) # macro -IB_GRH_FLOWLABEL_MASK = (0x000FFFFF) # macro - -# values for enumeration 'ib_uverbs_write_cmds' -ib_uverbs_write_cmds__enumvalues = { - 0: 'IB_USER_VERBS_CMD_GET_CONTEXT', - 1: 'IB_USER_VERBS_CMD_QUERY_DEVICE', - 2: 'IB_USER_VERBS_CMD_QUERY_PORT', - 3: 'IB_USER_VERBS_CMD_ALLOC_PD', - 4: 'IB_USER_VERBS_CMD_DEALLOC_PD', - 5: 'IB_USER_VERBS_CMD_CREATE_AH', - 6: 'IB_USER_VERBS_CMD_MODIFY_AH', - 7: 'IB_USER_VERBS_CMD_QUERY_AH', - 8: 'IB_USER_VERBS_CMD_DESTROY_AH', - 9: 'IB_USER_VERBS_CMD_REG_MR', - 10: 'IB_USER_VERBS_CMD_REG_SMR', - 11: 'IB_USER_VERBS_CMD_REREG_MR', - 12: 'IB_USER_VERBS_CMD_QUERY_MR', - 13: 'IB_USER_VERBS_CMD_DEREG_MR', - 14: 'IB_USER_VERBS_CMD_ALLOC_MW', - 15: 'IB_USER_VERBS_CMD_BIND_MW', - 16: 'IB_USER_VERBS_CMD_DEALLOC_MW', - 17: 'IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL', - 18: 'IB_USER_VERBS_CMD_CREATE_CQ', - 19: 'IB_USER_VERBS_CMD_RESIZE_CQ', - 20: 'IB_USER_VERBS_CMD_DESTROY_CQ', - 21: 'IB_USER_VERBS_CMD_POLL_CQ', - 22: 'IB_USER_VERBS_CMD_PEEK_CQ', - 23: 'IB_USER_VERBS_CMD_REQ_NOTIFY_CQ', - 24: 'IB_USER_VERBS_CMD_CREATE_QP', - 25: 'IB_USER_VERBS_CMD_QUERY_QP', - 26: 'IB_USER_VERBS_CMD_MODIFY_QP', - 27: 'IB_USER_VERBS_CMD_DESTROY_QP', - 28: 'IB_USER_VERBS_CMD_POST_SEND', - 29: 'IB_USER_VERBS_CMD_POST_RECV', - 30: 'IB_USER_VERBS_CMD_ATTACH_MCAST', - 31: 'IB_USER_VERBS_CMD_DETACH_MCAST', - 32: 'IB_USER_VERBS_CMD_CREATE_SRQ', - 33: 'IB_USER_VERBS_CMD_MODIFY_SRQ', - 34: 'IB_USER_VERBS_CMD_QUERY_SRQ', - 35: 'IB_USER_VERBS_CMD_DESTROY_SRQ', - 36: 'IB_USER_VERBS_CMD_POST_SRQ_RECV', - 37: 'IB_USER_VERBS_CMD_OPEN_XRCD', - 38: 'IB_USER_VERBS_CMD_CLOSE_XRCD', - 39: 'IB_USER_VERBS_CMD_CREATE_XSRQ', - 40: 'IB_USER_VERBS_CMD_OPEN_QP', -} -IB_USER_VERBS_CMD_GET_CONTEXT = 0 -IB_USER_VERBS_CMD_QUERY_DEVICE = 1 -IB_USER_VERBS_CMD_QUERY_PORT = 2 -IB_USER_VERBS_CMD_ALLOC_PD = 3 -IB_USER_VERBS_CMD_DEALLOC_PD = 4 -IB_USER_VERBS_CMD_CREATE_AH = 5 -IB_USER_VERBS_CMD_MODIFY_AH = 6 -IB_USER_VERBS_CMD_QUERY_AH = 7 -IB_USER_VERBS_CMD_DESTROY_AH = 8 -IB_USER_VERBS_CMD_REG_MR = 9 -IB_USER_VERBS_CMD_REG_SMR = 10 -IB_USER_VERBS_CMD_REREG_MR = 11 -IB_USER_VERBS_CMD_QUERY_MR = 12 -IB_USER_VERBS_CMD_DEREG_MR = 13 -IB_USER_VERBS_CMD_ALLOC_MW = 14 -IB_USER_VERBS_CMD_BIND_MW = 15 -IB_USER_VERBS_CMD_DEALLOC_MW = 16 -IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL = 17 -IB_USER_VERBS_CMD_CREATE_CQ = 18 -IB_USER_VERBS_CMD_RESIZE_CQ = 19 -IB_USER_VERBS_CMD_DESTROY_CQ = 20 -IB_USER_VERBS_CMD_POLL_CQ = 21 -IB_USER_VERBS_CMD_PEEK_CQ = 22 -IB_USER_VERBS_CMD_REQ_NOTIFY_CQ = 23 -IB_USER_VERBS_CMD_CREATE_QP = 24 -IB_USER_VERBS_CMD_QUERY_QP = 25 -IB_USER_VERBS_CMD_MODIFY_QP = 26 -IB_USER_VERBS_CMD_DESTROY_QP = 27 -IB_USER_VERBS_CMD_POST_SEND = 28 -IB_USER_VERBS_CMD_POST_RECV = 29 -IB_USER_VERBS_CMD_ATTACH_MCAST = 30 -IB_USER_VERBS_CMD_DETACH_MCAST = 31 -IB_USER_VERBS_CMD_CREATE_SRQ = 32 -IB_USER_VERBS_CMD_MODIFY_SRQ = 33 -IB_USER_VERBS_CMD_QUERY_SRQ = 34 -IB_USER_VERBS_CMD_DESTROY_SRQ = 35 -IB_USER_VERBS_CMD_POST_SRQ_RECV = 36 -IB_USER_VERBS_CMD_OPEN_XRCD = 37 -IB_USER_VERBS_CMD_CLOSE_XRCD = 38 -IB_USER_VERBS_CMD_CREATE_XSRQ = 39 -IB_USER_VERBS_CMD_OPEN_QP = 40 -ib_uverbs_write_cmds = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_IB_USER_VERBS_EX_CMD_QUERY_DEVICE' -c__Ea_IB_USER_VERBS_EX_CMD_QUERY_DEVICE__enumvalues = { - 1: 'IB_USER_VERBS_EX_CMD_QUERY_DEVICE', - 18: 'IB_USER_VERBS_EX_CMD_CREATE_CQ', - 24: 'IB_USER_VERBS_EX_CMD_CREATE_QP', - 26: 'IB_USER_VERBS_EX_CMD_MODIFY_QP', - 50: 'IB_USER_VERBS_EX_CMD_CREATE_FLOW', - 51: 'IB_USER_VERBS_EX_CMD_DESTROY_FLOW', - 52: 'IB_USER_VERBS_EX_CMD_CREATE_WQ', - 53: 'IB_USER_VERBS_EX_CMD_MODIFY_WQ', - 54: 'IB_USER_VERBS_EX_CMD_DESTROY_WQ', - 55: 'IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL', - 56: 'IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL', - 57: 'IB_USER_VERBS_EX_CMD_MODIFY_CQ', -} -IB_USER_VERBS_EX_CMD_QUERY_DEVICE = 1 -IB_USER_VERBS_EX_CMD_CREATE_CQ = 18 -IB_USER_VERBS_EX_CMD_CREATE_QP = 24 -IB_USER_VERBS_EX_CMD_MODIFY_QP = 26 -IB_USER_VERBS_EX_CMD_CREATE_FLOW = 50 -IB_USER_VERBS_EX_CMD_DESTROY_FLOW = 51 -IB_USER_VERBS_EX_CMD_CREATE_WQ = 52 -IB_USER_VERBS_EX_CMD_MODIFY_WQ = 53 -IB_USER_VERBS_EX_CMD_DESTROY_WQ = 54 -IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL = 55 -IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL = 56 -IB_USER_VERBS_EX_CMD_MODIFY_CQ = 57 -c__Ea_IB_USER_VERBS_EX_CMD_QUERY_DEVICE = ctypes.c_uint32 # enum - -# values for enumeration 'ib_placement_type' -ib_placement_type__enumvalues = { - 1: 'IB_FLUSH_GLOBAL', - 2: 'IB_FLUSH_PERSISTENT', -} -IB_FLUSH_GLOBAL = 1 -IB_FLUSH_PERSISTENT = 2 -ib_placement_type = ctypes.c_uint32 # enum - -# values for enumeration 'ib_selectivity_level' -ib_selectivity_level__enumvalues = { - 0: 'IB_FLUSH_RANGE', - 1: 'IB_FLUSH_MR', -} -IB_FLUSH_RANGE = 0 -IB_FLUSH_MR = 1 -ib_selectivity_level = ctypes.c_uint32 # enum -class struct_ib_uverbs_async_event_desc(Structure): - pass - -struct_ib_uverbs_async_event_desc._pack_ = 1 # source:False -struct_ib_uverbs_async_event_desc._fields_ = [ - ('element', ctypes.c_uint64), - ('event_type', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_comp_event_desc(Structure): - pass - -struct_ib_uverbs_comp_event_desc._pack_ = 1 # source:False -struct_ib_uverbs_comp_event_desc._fields_ = [ - ('cq_handle', ctypes.c_uint64), -] - -class struct_ib_uverbs_cq_moderation_caps(Structure): - pass - -struct_ib_uverbs_cq_moderation_caps._pack_ = 1 # source:False -struct_ib_uverbs_cq_moderation_caps._fields_ = [ - ('max_cq_moderation_count', ctypes.c_uint16), - ('max_cq_moderation_period', ctypes.c_uint16), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_cmd_hdr(Structure): - pass - -struct_ib_uverbs_cmd_hdr._pack_ = 1 # source:False -struct_ib_uverbs_cmd_hdr._fields_ = [ - ('command', ctypes.c_uint32), - ('in_words', ctypes.c_uint16), - ('out_words', ctypes.c_uint16), -] - -class struct_ib_uverbs_ex_cmd_hdr(Structure): - pass - -struct_ib_uverbs_ex_cmd_hdr._pack_ = 1 # source:False -struct_ib_uverbs_ex_cmd_hdr._fields_ = [ - ('response', ctypes.c_uint64), - ('provider_in_words', ctypes.c_uint16), - ('provider_out_words', ctypes.c_uint16), - ('cmd_hdr_reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_get_context(Structure): - pass - -struct_ib_uverbs_get_context._pack_ = 1 # source:False -struct_ib_uverbs_get_context._fields_ = [ - ('response', ctypes.c_uint64), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_get_context_resp(Structure): - pass - -struct_ib_uverbs_get_context_resp._pack_ = 1 # source:False -struct_ib_uverbs_get_context_resp._fields_ = [ - ('async_fd', ctypes.c_uint32), - ('num_comp_vectors', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_query_device(Structure): - pass - -struct_ib_uverbs_query_device._pack_ = 1 # source:False -struct_ib_uverbs_query_device._fields_ = [ - ('response', ctypes.c_uint64), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_query_device_resp(Structure): - pass - -struct_ib_uverbs_query_device_resp._pack_ = 1 # source:False -struct_ib_uverbs_query_device_resp._fields_ = [ - ('fw_ver', ctypes.c_uint64), - ('node_guid', ctypes.c_uint64), - ('sys_image_guid', ctypes.c_uint64), - ('max_mr_size', ctypes.c_uint64), - ('page_size_cap', ctypes.c_uint64), - ('vendor_id', ctypes.c_uint32), - ('vendor_part_id', ctypes.c_uint32), - ('hw_ver', ctypes.c_uint32), - ('max_qp', ctypes.c_uint32), - ('max_qp_wr', ctypes.c_uint32), - ('device_cap_flags', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('max_sge_rd', ctypes.c_uint32), - ('max_cq', ctypes.c_uint32), - ('max_cqe', ctypes.c_uint32), - ('max_mr', ctypes.c_uint32), - ('max_pd', ctypes.c_uint32), - ('max_qp_rd_atom', ctypes.c_uint32), - ('max_ee_rd_atom', ctypes.c_uint32), - ('max_res_rd_atom', ctypes.c_uint32), - ('max_qp_init_rd_atom', ctypes.c_uint32), - ('max_ee_init_rd_atom', ctypes.c_uint32), - ('atomic_cap', ctypes.c_uint32), - ('max_ee', ctypes.c_uint32), - ('max_rdd', ctypes.c_uint32), - ('max_mw', ctypes.c_uint32), - ('max_raw_ipv6_qp', ctypes.c_uint32), - ('max_raw_ethy_qp', ctypes.c_uint32), - ('max_mcast_grp', ctypes.c_uint32), - ('max_mcast_qp_attach', ctypes.c_uint32), - ('max_total_mcast_qp_attach', ctypes.c_uint32), - ('max_ah', ctypes.c_uint32), - ('max_fmr', ctypes.c_uint32), - ('max_map_per_fmr', ctypes.c_uint32), - ('max_srq', ctypes.c_uint32), - ('max_srq_wr', ctypes.c_uint32), - ('max_srq_sge', ctypes.c_uint32), - ('max_pkeys', ctypes.c_uint16), - ('local_ca_ack_delay', ctypes.c_ubyte), - ('phys_port_cnt', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 4), -] - -class struct_ib_uverbs_ex_query_device(Structure): - pass - -struct_ib_uverbs_ex_query_device._pack_ = 1 # source:False -struct_ib_uverbs_ex_query_device._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_odp_caps(Structure): - pass - -class struct_ib_uverbs_odp_caps_per_transport_caps(Structure): - pass - -struct_ib_uverbs_odp_caps_per_transport_caps._pack_ = 1 # source:False -struct_ib_uverbs_odp_caps_per_transport_caps._fields_ = [ - ('rc_odp_caps', ctypes.c_uint32), - ('uc_odp_caps', ctypes.c_uint32), - ('ud_odp_caps', ctypes.c_uint32), -] - -struct_ib_uverbs_odp_caps._pack_ = 1 # source:False -struct_ib_uverbs_odp_caps._fields_ = [ - ('general_caps', ctypes.c_uint64), - ('per_transport_caps', struct_ib_uverbs_odp_caps_per_transport_caps), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_rss_caps(Structure): - pass - -struct_ib_uverbs_rss_caps._pack_ = 1 # source:False -struct_ib_uverbs_rss_caps._fields_ = [ - ('supported_qpts', ctypes.c_uint32), - ('max_rwq_indirection_tables', ctypes.c_uint32), - ('max_rwq_indirection_table_size', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_tm_caps(Structure): - pass - -struct_ib_uverbs_tm_caps._pack_ = 1 # source:False -struct_ib_uverbs_tm_caps._fields_ = [ - ('max_rndv_hdr_size', ctypes.c_uint32), - ('max_num_tags', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('max_ops', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_query_device_resp(Structure): - pass - -struct_ib_uverbs_ex_query_device_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_query_device_resp._fields_ = [ - ('base', struct_ib_uverbs_query_device_resp), - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), - ('odp_caps', struct_ib_uverbs_odp_caps), - ('timestamp_mask', ctypes.c_uint64), - ('hca_core_clock', ctypes.c_uint64), - ('device_cap_flags_ex', ctypes.c_uint64), - ('rss_caps', struct_ib_uverbs_rss_caps), - ('max_wq_type_rq', ctypes.c_uint32), - ('raw_packet_caps', ctypes.c_uint32), - ('tm_caps', struct_ib_uverbs_tm_caps), - ('cq_moderation_caps', struct_ib_uverbs_cq_moderation_caps), - ('max_dm_size', ctypes.c_uint64), - ('xrc_odp_caps', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_query_port(Structure): - pass - -struct_ib_uverbs_query_port._pack_ = 1 # source:False -struct_ib_uverbs_query_port._fields_ = [ - ('response', ctypes.c_uint64), - ('port_num', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 7), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_query_port_resp(Structure): - pass - -struct_ib_uverbs_query_port_resp._pack_ = 1 # source:False -struct_ib_uverbs_query_port_resp._fields_ = [ - ('port_cap_flags', ctypes.c_uint32), - ('max_msg_sz', ctypes.c_uint32), - ('bad_pkey_cntr', ctypes.c_uint32), - ('qkey_viol_cntr', ctypes.c_uint32), - ('gid_tbl_len', ctypes.c_uint32), - ('pkey_tbl_len', ctypes.c_uint16), - ('lid', ctypes.c_uint16), - ('sm_lid', ctypes.c_uint16), - ('state', ctypes.c_ubyte), - ('max_mtu', ctypes.c_ubyte), - ('active_mtu', ctypes.c_ubyte), - ('lmc', ctypes.c_ubyte), - ('max_vl_num', ctypes.c_ubyte), - ('sm_sl', ctypes.c_ubyte), - ('subnet_timeout', ctypes.c_ubyte), - ('init_type_reply', ctypes.c_ubyte), - ('active_width', ctypes.c_ubyte), - ('active_speed', ctypes.c_ubyte), - ('phys_state', ctypes.c_ubyte), - ('link_layer', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), -] - -class struct_ib_uverbs_alloc_pd(Structure): - pass - -struct_ib_uverbs_alloc_pd._pack_ = 1 # source:False -struct_ib_uverbs_alloc_pd._fields_ = [ - ('response', ctypes.c_uint64), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_alloc_pd_resp(Structure): - pass - -struct_ib_uverbs_alloc_pd_resp._pack_ = 1 # source:False -struct_ib_uverbs_alloc_pd_resp._fields_ = [ - ('pd_handle', ctypes.c_uint32), - ('driver_data', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_dealloc_pd(Structure): - pass - -struct_ib_uverbs_dealloc_pd._pack_ = 1 # source:False -struct_ib_uverbs_dealloc_pd._fields_ = [ - ('pd_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_open_xrcd(Structure): - pass - -struct_ib_uverbs_open_xrcd._pack_ = 1 # source:False -struct_ib_uverbs_open_xrcd._fields_ = [ - ('response', ctypes.c_uint64), - ('fd', ctypes.c_uint32), - ('oflags', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_open_xrcd_resp(Structure): - pass - -struct_ib_uverbs_open_xrcd_resp._pack_ = 1 # source:False -struct_ib_uverbs_open_xrcd_resp._fields_ = [ - ('xrcd_handle', ctypes.c_uint32), - ('driver_data', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_close_xrcd(Structure): - pass - -struct_ib_uverbs_close_xrcd._pack_ = 1 # source:False -struct_ib_uverbs_close_xrcd._fields_ = [ - ('xrcd_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_reg_mr(Structure): - pass - -struct_ib_uverbs_reg_mr._pack_ = 1 # source:False -struct_ib_uverbs_reg_mr._fields_ = [ - ('response', ctypes.c_uint64), - ('start', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('hca_va', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('access_flags', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_reg_mr_resp(Structure): - pass - -struct_ib_uverbs_reg_mr_resp._pack_ = 1 # source:False -struct_ib_uverbs_reg_mr_resp._fields_ = [ - ('mr_handle', ctypes.c_uint32), - ('lkey', ctypes.c_uint32), - ('rkey', ctypes.c_uint32), - ('driver_data', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_rereg_mr(Structure): - pass - -struct_ib_uverbs_rereg_mr._pack_ = 1 # source:False -struct_ib_uverbs_rereg_mr._fields_ = [ - ('response', ctypes.c_uint64), - ('mr_handle', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('start', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('hca_va', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('access_flags', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_rereg_mr_resp(Structure): - pass - -struct_ib_uverbs_rereg_mr_resp._pack_ = 1 # source:False -struct_ib_uverbs_rereg_mr_resp._fields_ = [ - ('lkey', ctypes.c_uint32), - ('rkey', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_dereg_mr(Structure): - pass - -struct_ib_uverbs_dereg_mr._pack_ = 1 # source:False -struct_ib_uverbs_dereg_mr._fields_ = [ - ('mr_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_alloc_mw(Structure): - pass - -struct_ib_uverbs_alloc_mw._pack_ = 1 # source:False -struct_ib_uverbs_alloc_mw._fields_ = [ - ('response', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('mw_type', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 3), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_alloc_mw_resp(Structure): - pass - -struct_ib_uverbs_alloc_mw_resp._pack_ = 1 # source:False -struct_ib_uverbs_alloc_mw_resp._fields_ = [ - ('mw_handle', ctypes.c_uint32), - ('rkey', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_dealloc_mw(Structure): - pass - -struct_ib_uverbs_dealloc_mw._pack_ = 1 # source:False -struct_ib_uverbs_dealloc_mw._fields_ = [ - ('mw_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_create_comp_channel(Structure): - pass - -struct_ib_uverbs_create_comp_channel._pack_ = 1 # source:False -struct_ib_uverbs_create_comp_channel._fields_ = [ - ('response', ctypes.c_uint64), -] - -class struct_ib_uverbs_create_comp_channel_resp(Structure): - pass - -struct_ib_uverbs_create_comp_channel_resp._pack_ = 1 # source:False -struct_ib_uverbs_create_comp_channel_resp._fields_ = [ - ('fd', ctypes.c_uint32), -] - -class struct_ib_uverbs_create_cq(Structure): - pass - -struct_ib_uverbs_create_cq._pack_ = 1 # source:False -struct_ib_uverbs_create_cq._fields_ = [ - ('response', ctypes.c_uint64), - ('user_handle', ctypes.c_uint64), - ('cqe', ctypes.c_uint32), - ('comp_vector', ctypes.c_uint32), - ('comp_channel', ctypes.c_int32), - ('reserved', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - - -# values for enumeration 'ib_uverbs_ex_create_cq_flags' -ib_uverbs_ex_create_cq_flags__enumvalues = { - 1: 'IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION', - 2: 'IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN', -} -IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION = 1 -IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN = 2 -ib_uverbs_ex_create_cq_flags = ctypes.c_uint32 # enum -class struct_ib_uverbs_ex_create_cq(Structure): - pass - -struct_ib_uverbs_ex_create_cq._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_cq._fields_ = [ - ('user_handle', ctypes.c_uint64), - ('cqe', ctypes.c_uint32), - ('comp_vector', ctypes.c_uint32), - ('comp_channel', ctypes.c_int32), - ('comp_mask', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_create_cq_resp(Structure): - pass - -struct_ib_uverbs_create_cq_resp._pack_ = 1 # source:False -struct_ib_uverbs_create_cq_resp._fields_ = [ - ('cq_handle', ctypes.c_uint32), - ('cqe', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_ex_create_cq_resp(Structure): - pass - -struct_ib_uverbs_ex_create_cq_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_cq_resp._fields_ = [ - ('base', struct_ib_uverbs_create_cq_resp), - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), -] - -class struct_ib_uverbs_resize_cq(Structure): - pass - -struct_ib_uverbs_resize_cq._pack_ = 1 # source:False -struct_ib_uverbs_resize_cq._fields_ = [ - ('response', ctypes.c_uint64), - ('cq_handle', ctypes.c_uint32), - ('cqe', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_resize_cq_resp(Structure): - pass - -struct_ib_uverbs_resize_cq_resp._pack_ = 1 # source:False -struct_ib_uverbs_resize_cq_resp._fields_ = [ - ('cqe', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_poll_cq(Structure): - pass - -struct_ib_uverbs_poll_cq._pack_ = 1 # source:False -struct_ib_uverbs_poll_cq._fields_ = [ - ('response', ctypes.c_uint64), - ('cq_handle', ctypes.c_uint32), - ('ne', ctypes.c_uint32), -] - - -# values for enumeration 'ib_uverbs_wc_opcode' -ib_uverbs_wc_opcode__enumvalues = { - 0: 'IB_UVERBS_WC_SEND', - 1: 'IB_UVERBS_WC_RDMA_WRITE', - 2: 'IB_UVERBS_WC_RDMA_READ', - 3: 'IB_UVERBS_WC_COMP_SWAP', - 4: 'IB_UVERBS_WC_FETCH_ADD', - 5: 'IB_UVERBS_WC_BIND_MW', - 6: 'IB_UVERBS_WC_LOCAL_INV', - 7: 'IB_UVERBS_WC_TSO', - 8: 'IB_UVERBS_WC_FLUSH', - 9: 'IB_UVERBS_WC_ATOMIC_WRITE', -} -IB_UVERBS_WC_SEND = 0 -IB_UVERBS_WC_RDMA_WRITE = 1 -IB_UVERBS_WC_RDMA_READ = 2 -IB_UVERBS_WC_COMP_SWAP = 3 -IB_UVERBS_WC_FETCH_ADD = 4 -IB_UVERBS_WC_BIND_MW = 5 -IB_UVERBS_WC_LOCAL_INV = 6 -IB_UVERBS_WC_TSO = 7 -IB_UVERBS_WC_FLUSH = 8 -IB_UVERBS_WC_ATOMIC_WRITE = 9 -ib_uverbs_wc_opcode = ctypes.c_uint32 # enum -class struct_ib_uverbs_wc(Structure): - pass - -class union_ib_uverbs_wc_ex(Union): - pass - -union_ib_uverbs_wc_ex._pack_ = 1 # source:False -union_ib_uverbs_wc_ex._fields_ = [ - ('imm_data', ctypes.c_uint32), - ('invalidate_rkey', ctypes.c_uint32), -] - -struct_ib_uverbs_wc._pack_ = 1 # source:False -struct_ib_uverbs_wc._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('status', ctypes.c_uint32), - ('opcode', ctypes.c_uint32), - ('vendor_err', ctypes.c_uint32), - ('byte_len', ctypes.c_uint32), - ('ex', union_ib_uverbs_wc_ex), - ('qp_num', ctypes.c_uint32), - ('src_qp', ctypes.c_uint32), - ('wc_flags', ctypes.c_uint32), - ('pkey_index', ctypes.c_uint16), - ('slid', ctypes.c_uint16), - ('sl', ctypes.c_ubyte), - ('dlid_path_bits', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), -] - -class struct_ib_uverbs_poll_cq_resp(Structure): - pass - -struct_ib_uverbs_poll_cq_resp._pack_ = 1 # source:False -struct_ib_uverbs_poll_cq_resp._fields_ = [ - ('count', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('wc', struct_ib_uverbs_wc * 0), -] - -class struct_ib_uverbs_req_notify_cq(Structure): - pass - -struct_ib_uverbs_req_notify_cq._pack_ = 1 # source:False -struct_ib_uverbs_req_notify_cq._fields_ = [ - ('cq_handle', ctypes.c_uint32), - ('solicited_only', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_cq(Structure): - pass - -struct_ib_uverbs_destroy_cq._pack_ = 1 # source:False -struct_ib_uverbs_destroy_cq._fields_ = [ - ('response', ctypes.c_uint64), - ('cq_handle', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_cq_resp(Structure): - pass - -struct_ib_uverbs_destroy_cq_resp._pack_ = 1 # source:False -struct_ib_uverbs_destroy_cq_resp._fields_ = [ - ('comp_events_reported', ctypes.c_uint32), - ('async_events_reported', ctypes.c_uint32), -] - -class struct_ib_uverbs_global_route(Structure): - pass - -struct_ib_uverbs_global_route._pack_ = 1 # source:False -struct_ib_uverbs_global_route._fields_ = [ - ('dgid', ctypes.c_ubyte * 16), - ('flow_label', ctypes.c_uint32), - ('sgid_index', ctypes.c_ubyte), - ('hop_limit', ctypes.c_ubyte), - ('traffic_class', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), -] - -class struct_ib_uverbs_ah_attr(Structure): - pass - -struct_ib_uverbs_ah_attr._pack_ = 1 # source:False -struct_ib_uverbs_ah_attr._fields_ = [ - ('grh', struct_ib_uverbs_global_route), - ('dlid', ctypes.c_uint16), - ('sl', ctypes.c_ubyte), - ('src_path_bits', ctypes.c_ubyte), - ('static_rate', ctypes.c_ubyte), - ('is_global', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), -] - -class struct_ib_uverbs_qp_attr(Structure): - pass - -struct_ib_uverbs_qp_attr._pack_ = 1 # source:False -struct_ib_uverbs_qp_attr._fields_ = [ - ('qp_attr_mask', ctypes.c_uint32), - ('qp_state', ctypes.c_uint32), - ('cur_qp_state', ctypes.c_uint32), - ('path_mtu', ctypes.c_uint32), - ('path_mig_state', ctypes.c_uint32), - ('qkey', ctypes.c_uint32), - ('rq_psn', ctypes.c_uint32), - ('sq_psn', ctypes.c_uint32), - ('dest_qp_num', ctypes.c_uint32), - ('qp_access_flags', ctypes.c_uint32), - ('ah_attr', struct_ib_uverbs_ah_attr), - ('alt_ah_attr', struct_ib_uverbs_ah_attr), - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), - ('pkey_index', ctypes.c_uint16), - ('alt_pkey_index', ctypes.c_uint16), - ('en_sqd_async_notify', ctypes.c_ubyte), - ('sq_draining', ctypes.c_ubyte), - ('max_rd_atomic', ctypes.c_ubyte), - ('max_dest_rd_atomic', ctypes.c_ubyte), - ('min_rnr_timer', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('timeout', ctypes.c_ubyte), - ('retry_cnt', ctypes.c_ubyte), - ('rnr_retry', ctypes.c_ubyte), - ('alt_port_num', ctypes.c_ubyte), - ('alt_timeout', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 5), -] - -class struct_ib_uverbs_create_qp(Structure): - pass - -struct_ib_uverbs_create_qp._pack_ = 1 # source:False -struct_ib_uverbs_create_qp._fields_ = [ - ('response', ctypes.c_uint64), - ('user_handle', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('send_cq_handle', ctypes.c_uint32), - ('recv_cq_handle', ctypes.c_uint32), - ('srq_handle', ctypes.c_uint32), - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), - ('sq_sig_all', ctypes.c_ubyte), - ('qp_type', ctypes.c_ubyte), - ('is_srq', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), - ('driver_data', ctypes.c_uint64 * 0), -] - - -# values for enumeration 'ib_uverbs_create_qp_mask' -ib_uverbs_create_qp_mask__enumvalues = { - 1: 'IB_UVERBS_CREATE_QP_MASK_IND_TABLE', -} -IB_UVERBS_CREATE_QP_MASK_IND_TABLE = 1 -ib_uverbs_create_qp_mask = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_IB_UVERBS_CREATE_QP_SUP_COMP_MASK' -c__Ea_IB_UVERBS_CREATE_QP_SUP_COMP_MASK__enumvalues = { - 1: 'IB_UVERBS_CREATE_QP_SUP_COMP_MASK', -} -IB_UVERBS_CREATE_QP_SUP_COMP_MASK = 1 -c__Ea_IB_UVERBS_CREATE_QP_SUP_COMP_MASK = ctypes.c_uint32 # enum -class struct_ib_uverbs_ex_create_qp(Structure): - pass - -struct_ib_uverbs_ex_create_qp._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_qp._fields_ = [ - ('user_handle', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('send_cq_handle', ctypes.c_uint32), - ('recv_cq_handle', ctypes.c_uint32), - ('srq_handle', ctypes.c_uint32), - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), - ('sq_sig_all', ctypes.c_ubyte), - ('qp_type', ctypes.c_ubyte), - ('is_srq', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), - ('comp_mask', ctypes.c_uint32), - ('create_flags', ctypes.c_uint32), - ('rwq_ind_tbl_handle', ctypes.c_uint32), - ('source_qpn', ctypes.c_uint32), -] - -class struct_ib_uverbs_open_qp(Structure): - pass - -struct_ib_uverbs_open_qp._pack_ = 1 # source:False -struct_ib_uverbs_open_qp._fields_ = [ - ('response', ctypes.c_uint64), - ('user_handle', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('qpn', ctypes.c_uint32), - ('qp_type', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 7), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_create_qp_resp(Structure): - pass - -struct_ib_uverbs_create_qp_resp._pack_ = 1 # source:False -struct_ib_uverbs_create_qp_resp._fields_ = [ - ('qp_handle', ctypes.c_uint32), - ('qpn', ctypes.c_uint32), - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('driver_data', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_ex_create_qp_resp(Structure): - pass - -struct_ib_uverbs_ex_create_qp_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_qp_resp._fields_ = [ - ('base', struct_ib_uverbs_create_qp_resp), - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), -] - -class struct_ib_uverbs_qp_dest(Structure): - pass - -struct_ib_uverbs_qp_dest._pack_ = 1 # source:False -struct_ib_uverbs_qp_dest._fields_ = [ - ('dgid', ctypes.c_ubyte * 16), - ('flow_label', ctypes.c_uint32), - ('dlid', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), - ('sgid_index', ctypes.c_ubyte), - ('hop_limit', ctypes.c_ubyte), - ('traffic_class', ctypes.c_ubyte), - ('sl', ctypes.c_ubyte), - ('src_path_bits', ctypes.c_ubyte), - ('static_rate', ctypes.c_ubyte), - ('is_global', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), -] - -class struct_ib_uverbs_query_qp(Structure): - pass - -struct_ib_uverbs_query_qp._pack_ = 1 # source:False -struct_ib_uverbs_query_qp._fields_ = [ - ('response', ctypes.c_uint64), - ('qp_handle', ctypes.c_uint32), - ('attr_mask', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_query_qp_resp(Structure): - pass - -struct_ib_uverbs_query_qp_resp._pack_ = 1 # source:False -struct_ib_uverbs_query_qp_resp._fields_ = [ - ('dest', struct_ib_uverbs_qp_dest), - ('alt_dest', struct_ib_uverbs_qp_dest), - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), - ('qkey', ctypes.c_uint32), - ('rq_psn', ctypes.c_uint32), - ('sq_psn', ctypes.c_uint32), - ('dest_qp_num', ctypes.c_uint32), - ('qp_access_flags', ctypes.c_uint32), - ('pkey_index', ctypes.c_uint16), - ('alt_pkey_index', ctypes.c_uint16), - ('qp_state', ctypes.c_ubyte), - ('cur_qp_state', ctypes.c_ubyte), - ('path_mtu', ctypes.c_ubyte), - ('path_mig_state', ctypes.c_ubyte), - ('sq_draining', ctypes.c_ubyte), - ('max_rd_atomic', ctypes.c_ubyte), - ('max_dest_rd_atomic', ctypes.c_ubyte), - ('min_rnr_timer', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('timeout', ctypes.c_ubyte), - ('retry_cnt', ctypes.c_ubyte), - ('rnr_retry', ctypes.c_ubyte), - ('alt_port_num', ctypes.c_ubyte), - ('alt_timeout', ctypes.c_ubyte), - ('sq_sig_all', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 5), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_modify_qp(Structure): - pass - -struct_ib_uverbs_modify_qp._pack_ = 1 # source:False -struct_ib_uverbs_modify_qp._fields_ = [ - ('dest', struct_ib_uverbs_qp_dest), - ('alt_dest', struct_ib_uverbs_qp_dest), - ('qp_handle', ctypes.c_uint32), - ('attr_mask', ctypes.c_uint32), - ('qkey', ctypes.c_uint32), - ('rq_psn', ctypes.c_uint32), - ('sq_psn', ctypes.c_uint32), - ('dest_qp_num', ctypes.c_uint32), - ('qp_access_flags', ctypes.c_uint32), - ('pkey_index', ctypes.c_uint16), - ('alt_pkey_index', ctypes.c_uint16), - ('qp_state', ctypes.c_ubyte), - ('cur_qp_state', ctypes.c_ubyte), - ('path_mtu', ctypes.c_ubyte), - ('path_mig_state', ctypes.c_ubyte), - ('en_sqd_async_notify', ctypes.c_ubyte), - ('max_rd_atomic', ctypes.c_ubyte), - ('max_dest_rd_atomic', ctypes.c_ubyte), - ('min_rnr_timer', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('timeout', ctypes.c_ubyte), - ('retry_cnt', ctypes.c_ubyte), - ('rnr_retry', ctypes.c_ubyte), - ('alt_port_num', ctypes.c_ubyte), - ('alt_timeout', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 2), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_ex_modify_qp(Structure): - pass - -struct_ib_uverbs_ex_modify_qp._pack_ = 1 # source:False -struct_ib_uverbs_ex_modify_qp._fields_ = [ - ('base', struct_ib_uverbs_modify_qp), - ('rate_limit', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_modify_qp_resp(Structure): - pass - -struct_ib_uverbs_ex_modify_qp_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_modify_qp_resp._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_qp(Structure): - pass - -struct_ib_uverbs_destroy_qp._pack_ = 1 # source:False -struct_ib_uverbs_destroy_qp._fields_ = [ - ('response', ctypes.c_uint64), - ('qp_handle', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_qp_resp(Structure): - pass - -struct_ib_uverbs_destroy_qp_resp._pack_ = 1 # source:False -struct_ib_uverbs_destroy_qp_resp._fields_ = [ - ('events_reported', ctypes.c_uint32), -] - -class struct_ib_uverbs_sge(Structure): - pass - -struct_ib_uverbs_sge._pack_ = 1 # source:False -struct_ib_uverbs_sge._fields_ = [ - ('addr', ctypes.c_uint64), - ('length', ctypes.c_uint32), - ('lkey', ctypes.c_uint32), -] - - -# values for enumeration 'ib_uverbs_wr_opcode' -ib_uverbs_wr_opcode__enumvalues = { - 0: 'IB_UVERBS_WR_RDMA_WRITE', - 1: 'IB_UVERBS_WR_RDMA_WRITE_WITH_IMM', - 2: 'IB_UVERBS_WR_SEND', - 3: 'IB_UVERBS_WR_SEND_WITH_IMM', - 4: 'IB_UVERBS_WR_RDMA_READ', - 5: 'IB_UVERBS_WR_ATOMIC_CMP_AND_SWP', - 6: 'IB_UVERBS_WR_ATOMIC_FETCH_AND_ADD', - 7: 'IB_UVERBS_WR_LOCAL_INV', - 8: 'IB_UVERBS_WR_BIND_MW', - 9: 'IB_UVERBS_WR_SEND_WITH_INV', - 10: 'IB_UVERBS_WR_TSO', - 11: 'IB_UVERBS_WR_RDMA_READ_WITH_INV', - 12: 'IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP', - 13: 'IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD', - 14: 'IB_UVERBS_WR_FLUSH', - 15: 'IB_UVERBS_WR_ATOMIC_WRITE', -} -IB_UVERBS_WR_RDMA_WRITE = 0 -IB_UVERBS_WR_RDMA_WRITE_WITH_IMM = 1 -IB_UVERBS_WR_SEND = 2 -IB_UVERBS_WR_SEND_WITH_IMM = 3 -IB_UVERBS_WR_RDMA_READ = 4 -IB_UVERBS_WR_ATOMIC_CMP_AND_SWP = 5 -IB_UVERBS_WR_ATOMIC_FETCH_AND_ADD = 6 -IB_UVERBS_WR_LOCAL_INV = 7 -IB_UVERBS_WR_BIND_MW = 8 -IB_UVERBS_WR_SEND_WITH_INV = 9 -IB_UVERBS_WR_TSO = 10 -IB_UVERBS_WR_RDMA_READ_WITH_INV = 11 -IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP = 12 -IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD = 13 -IB_UVERBS_WR_FLUSH = 14 -IB_UVERBS_WR_ATOMIC_WRITE = 15 -ib_uverbs_wr_opcode = ctypes.c_uint32 # enum -class struct_ib_uverbs_send_wr(Structure): - pass - -class union_ib_uverbs_send_wr_ex(Union): - pass - -union_ib_uverbs_send_wr_ex._pack_ = 1 # source:False -union_ib_uverbs_send_wr_ex._fields_ = [ - ('imm_data', ctypes.c_uint32), - ('invalidate_rkey', ctypes.c_uint32), -] - -class union_ib_uverbs_send_wr_wr(Union): - pass - -class struct_ib_uverbs_send_wr_1_rdma(Structure): - pass - -struct_ib_uverbs_send_wr_1_rdma._pack_ = 1 # source:False -struct_ib_uverbs_send_wr_1_rdma._fields_ = [ - ('remote_addr', ctypes.c_uint64), - ('rkey', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_send_wr_1_atomic(Structure): - pass - -struct_ib_uverbs_send_wr_1_atomic._pack_ = 1 # source:False -struct_ib_uverbs_send_wr_1_atomic._fields_ = [ - ('remote_addr', ctypes.c_uint64), - ('compare_add', ctypes.c_uint64), - ('swap', ctypes.c_uint64), - ('rkey', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_send_wr_1_ud(Structure): - pass - -struct_ib_uverbs_send_wr_1_ud._pack_ = 1 # source:False -struct_ib_uverbs_send_wr_1_ud._fields_ = [ - ('ah', ctypes.c_uint32), - ('remote_qpn', ctypes.c_uint32), - ('remote_qkey', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -union_ib_uverbs_send_wr_wr._pack_ = 1 # source:False -union_ib_uverbs_send_wr_wr._fields_ = [ - ('rdma', struct_ib_uverbs_send_wr_1_rdma), - ('atomic', struct_ib_uverbs_send_wr_1_atomic), - ('ud', struct_ib_uverbs_send_wr_1_ud), - ('PADDING_0', ctypes.c_ubyte * 16), -] - -struct_ib_uverbs_send_wr._pack_ = 1 # source:False -struct_ib_uverbs_send_wr._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('num_sge', ctypes.c_uint32), - ('opcode', ctypes.c_uint32), - ('send_flags', ctypes.c_uint32), - ('ex', union_ib_uverbs_send_wr_ex), - ('wr', union_ib_uverbs_send_wr_wr), -] - -class struct_ib_uverbs_post_send(Structure): - pass - -struct_ib_uverbs_post_send._pack_ = 1 # source:False -struct_ib_uverbs_post_send._fields_ = [ - ('response', ctypes.c_uint64), - ('qp_handle', ctypes.c_uint32), - ('wr_count', ctypes.c_uint32), - ('sge_count', ctypes.c_uint32), - ('wqe_size', ctypes.c_uint32), - ('send_wr', struct_ib_uverbs_send_wr * 0), -] - -class struct_ib_uverbs_post_send_resp(Structure): - pass - -struct_ib_uverbs_post_send_resp._pack_ = 1 # source:False -struct_ib_uverbs_post_send_resp._fields_ = [ - ('bad_wr', ctypes.c_uint32), -] - -class struct_ib_uverbs_recv_wr(Structure): - pass - -struct_ib_uverbs_recv_wr._pack_ = 1 # source:False -struct_ib_uverbs_recv_wr._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('num_sge', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_post_recv(Structure): - pass - -struct_ib_uverbs_post_recv._pack_ = 1 # source:False -struct_ib_uverbs_post_recv._fields_ = [ - ('response', ctypes.c_uint64), - ('qp_handle', ctypes.c_uint32), - ('wr_count', ctypes.c_uint32), - ('sge_count', ctypes.c_uint32), - ('wqe_size', ctypes.c_uint32), - ('recv_wr', struct_ib_uverbs_recv_wr * 0), -] - -class struct_ib_uverbs_post_recv_resp(Structure): - pass - -struct_ib_uverbs_post_recv_resp._pack_ = 1 # source:False -struct_ib_uverbs_post_recv_resp._fields_ = [ - ('bad_wr', ctypes.c_uint32), -] - -class struct_ib_uverbs_post_srq_recv(Structure): - pass - -struct_ib_uverbs_post_srq_recv._pack_ = 1 # source:False -struct_ib_uverbs_post_srq_recv._fields_ = [ - ('response', ctypes.c_uint64), - ('srq_handle', ctypes.c_uint32), - ('wr_count', ctypes.c_uint32), - ('sge_count', ctypes.c_uint32), - ('wqe_size', ctypes.c_uint32), - ('recv', struct_ib_uverbs_recv_wr * 0), -] - -class struct_ib_uverbs_post_srq_recv_resp(Structure): - pass - -struct_ib_uverbs_post_srq_recv_resp._pack_ = 1 # source:False -struct_ib_uverbs_post_srq_recv_resp._fields_ = [ - ('bad_wr', ctypes.c_uint32), -] - -class struct_ib_uverbs_create_ah(Structure): - pass - -struct_ib_uverbs_create_ah._pack_ = 1 # source:False -struct_ib_uverbs_create_ah._fields_ = [ - ('response', ctypes.c_uint64), - ('user_handle', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('attr', struct_ib_uverbs_ah_attr), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_create_ah_resp(Structure): - pass - -struct_ib_uverbs_create_ah_resp._pack_ = 1 # source:False -struct_ib_uverbs_create_ah_resp._fields_ = [ - ('ah_handle', ctypes.c_uint32), - ('driver_data', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_destroy_ah(Structure): - pass - -struct_ib_uverbs_destroy_ah._pack_ = 1 # source:False -struct_ib_uverbs_destroy_ah._fields_ = [ - ('ah_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_attach_mcast(Structure): - pass - -struct_ib_uverbs_attach_mcast._pack_ = 1 # source:False -struct_ib_uverbs_attach_mcast._fields_ = [ - ('gid', ctypes.c_ubyte * 16), - ('qp_handle', ctypes.c_uint32), - ('mlid', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_detach_mcast(Structure): - pass - -struct_ib_uverbs_detach_mcast._pack_ = 1 # source:False -struct_ib_uverbs_detach_mcast._fields_ = [ - ('gid', ctypes.c_ubyte * 16), - ('qp_handle', ctypes.c_uint32), - ('mlid', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_flow_spec_hdr(Structure): - pass - -struct_ib_uverbs_flow_spec_hdr._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_hdr._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), - ('flow_spec_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_flow_eth_filter(Structure): - pass - -struct_ib_uverbs_flow_eth_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_eth_filter._fields_ = [ - ('dst_mac', ctypes.c_ubyte * 6), - ('src_mac', ctypes.c_ubyte * 6), - ('ether_type', ctypes.c_uint16), - ('vlan_tag', ctypes.c_uint16), -] - -class struct_ib_uverbs_flow_spec_eth(Structure): - pass - -class union_ib_uverbs_flow_spec_eth_0(Union): - pass - -class struct_ib_uverbs_flow_spec_eth_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_eth_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_eth_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_eth_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_eth_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_eth_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_eth_0_0), -] - -struct_ib_uverbs_flow_spec_eth._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_eth._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_eth._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_eth_0), - ('val', struct_ib_uverbs_flow_eth_filter), - ('mask', struct_ib_uverbs_flow_eth_filter), -] - -class struct_ib_uverbs_flow_ipv4_filter(Structure): - pass - -struct_ib_uverbs_flow_ipv4_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_ipv4_filter._fields_ = [ - ('src_ip', ctypes.c_uint32), - ('dst_ip', ctypes.c_uint32), - ('proto', ctypes.c_ubyte), - ('tos', ctypes.c_ubyte), - ('ttl', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), -] - -class struct_ib_uverbs_flow_spec_ipv4(Structure): - pass - -class union_ib_uverbs_flow_spec_ipv4_0(Union): - pass - -class struct_ib_uverbs_flow_spec_ipv4_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_ipv4_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_ipv4_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_ipv4_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_ipv4_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_ipv4_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_ipv4_0_0), -] - -struct_ib_uverbs_flow_spec_ipv4._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_ipv4._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_ipv4._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_ipv4_0), - ('val', struct_ib_uverbs_flow_ipv4_filter), - ('mask', struct_ib_uverbs_flow_ipv4_filter), -] - -class struct_ib_uverbs_flow_tcp_udp_filter(Structure): - pass - -struct_ib_uverbs_flow_tcp_udp_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_tcp_udp_filter._fields_ = [ - ('dst_port', ctypes.c_uint16), - ('src_port', ctypes.c_uint16), -] - -class struct_ib_uverbs_flow_spec_tcp_udp(Structure): - pass - -class union_ib_uverbs_flow_spec_tcp_udp_0(Union): - pass - -class struct_ib_uverbs_flow_spec_tcp_udp_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_tcp_udp_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_tcp_udp_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_tcp_udp_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_tcp_udp_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_tcp_udp_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_tcp_udp_0_0), -] - -struct_ib_uverbs_flow_spec_tcp_udp._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_tcp_udp._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_tcp_udp._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_tcp_udp_0), - ('val', struct_ib_uverbs_flow_tcp_udp_filter), - ('mask', struct_ib_uverbs_flow_tcp_udp_filter), -] - -class struct_ib_uverbs_flow_ipv6_filter(Structure): - pass - -struct_ib_uverbs_flow_ipv6_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_ipv6_filter._fields_ = [ - ('src_ip', ctypes.c_ubyte * 16), - ('dst_ip', ctypes.c_ubyte * 16), - ('flow_label', ctypes.c_uint32), - ('next_hdr', ctypes.c_ubyte), - ('traffic_class', ctypes.c_ubyte), - ('hop_limit', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte), -] - -class struct_ib_uverbs_flow_spec_ipv6(Structure): - pass - -class union_ib_uverbs_flow_spec_ipv6_0(Union): - pass - -class struct_ib_uverbs_flow_spec_ipv6_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_ipv6_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_ipv6_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_ipv6_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_ipv6_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_ipv6_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_ipv6_0_0), -] - -struct_ib_uverbs_flow_spec_ipv6._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_ipv6._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_ipv6._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_ipv6_0), - ('val', struct_ib_uverbs_flow_ipv6_filter), - ('mask', struct_ib_uverbs_flow_ipv6_filter), -] - -class struct_ib_uverbs_flow_spec_action_tag(Structure): - pass - -class union_ib_uverbs_flow_spec_action_tag_0(Union): - pass - -class struct_ib_uverbs_flow_spec_action_tag_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_action_tag_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_tag_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_action_tag_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_action_tag_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_action_tag_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_action_tag_0_0), -] - -struct_ib_uverbs_flow_spec_action_tag._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_tag._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_action_tag._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_action_tag_0), - ('tag_id', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_spec_action_drop(Structure): - pass - -class union_ib_uverbs_flow_spec_action_drop_0(Union): - pass - -class struct_ib_uverbs_flow_spec_action_drop_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_action_drop_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_drop_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_action_drop_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_action_drop_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_action_drop_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_action_drop_0_0), -] - -struct_ib_uverbs_flow_spec_action_drop._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_drop._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_action_drop._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_action_drop_0), -] - -class struct_ib_uverbs_flow_spec_action_handle(Structure): - pass - -class union_ib_uverbs_flow_spec_action_handle_0(Union): - pass - -class struct_ib_uverbs_flow_spec_action_handle_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_action_handle_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_handle_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_action_handle_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_action_handle_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_action_handle_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_action_handle_0_0), -] - -struct_ib_uverbs_flow_spec_action_handle._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_handle._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_action_handle._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_action_handle_0), - ('handle', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_spec_action_count(Structure): - pass - -class union_ib_uverbs_flow_spec_action_count_0(Union): - pass - -class struct_ib_uverbs_flow_spec_action_count_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_action_count_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_count_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_action_count_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_action_count_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_action_count_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_action_count_0_0), -] - -struct_ib_uverbs_flow_spec_action_count._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_action_count._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_action_count._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_action_count_0), - ('handle', ctypes.c_uint32), - ('reserved1', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_tunnel_filter(Structure): - pass - -struct_ib_uverbs_flow_tunnel_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_tunnel_filter._fields_ = [ - ('tunnel_id', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_spec_tunnel(Structure): - pass - -class union_ib_uverbs_flow_spec_tunnel_0(Union): - pass - -class struct_ib_uverbs_flow_spec_tunnel_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_tunnel_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_tunnel_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_tunnel_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_tunnel_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_tunnel_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_tunnel_0_0), -] - -struct_ib_uverbs_flow_spec_tunnel._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_tunnel._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_tunnel._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_tunnel_0), - ('val', struct_ib_uverbs_flow_tunnel_filter), - ('mask', struct_ib_uverbs_flow_tunnel_filter), -] - -class struct_ib_uverbs_flow_spec_esp_filter(Structure): - pass - -struct_ib_uverbs_flow_spec_esp_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_esp_filter._fields_ = [ - ('spi', ctypes.c_uint32), - ('seq', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_spec_esp(Structure): - pass - -class union_ib_uverbs_flow_spec_esp_0(Union): - pass - -class struct_ib_uverbs_flow_spec_esp_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_esp_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_esp_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_esp_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_esp_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_esp_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_esp_0_0), -] - -struct_ib_uverbs_flow_spec_esp._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_esp._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_esp._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_esp_0), - ('val', struct_ib_uverbs_flow_spec_esp_filter), - ('mask', struct_ib_uverbs_flow_spec_esp_filter), -] - -class struct_ib_uverbs_flow_gre_filter(Structure): - pass - -struct_ib_uverbs_flow_gre_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_gre_filter._fields_ = [ - ('c_ks_res0_ver', ctypes.c_uint16), - ('protocol', ctypes.c_uint16), - ('key', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_spec_gre(Structure): - pass - -class union_ib_uverbs_flow_spec_gre_0(Union): - pass - -class struct_ib_uverbs_flow_spec_gre_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_gre_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_gre_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_gre_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_gre_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_gre_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_gre_0_0), -] - -struct_ib_uverbs_flow_spec_gre._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_gre._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_gre._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_gre_0), - ('val', struct_ib_uverbs_flow_gre_filter), - ('mask', struct_ib_uverbs_flow_gre_filter), -] - -class struct_ib_uverbs_flow_mpls_filter(Structure): - pass - -struct_ib_uverbs_flow_mpls_filter._pack_ = 1 # source:False -struct_ib_uverbs_flow_mpls_filter._fields_ = [ - ('label', ctypes.c_uint32), -] - -class struct_ib_uverbs_flow_spec_mpls(Structure): - pass - -class union_ib_uverbs_flow_spec_mpls_0(Union): - pass - -class struct_ib_uverbs_flow_spec_mpls_0_0(Structure): - pass - -struct_ib_uverbs_flow_spec_mpls_0_0._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_mpls_0_0._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('reserved', ctypes.c_uint16), -] - -union_ib_uverbs_flow_spec_mpls_0._pack_ = 1 # source:False -union_ib_uverbs_flow_spec_mpls_0._anonymous_ = ('_0',) -union_ib_uverbs_flow_spec_mpls_0._fields_ = [ - ('hdr', struct_ib_uverbs_flow_spec_hdr), - ('_0', struct_ib_uverbs_flow_spec_mpls_0_0), -] - -struct_ib_uverbs_flow_spec_mpls._pack_ = 1 # source:False -struct_ib_uverbs_flow_spec_mpls._anonymous_ = ('_0',) -struct_ib_uverbs_flow_spec_mpls._fields_ = [ - ('_0', union_ib_uverbs_flow_spec_mpls_0), - ('val', struct_ib_uverbs_flow_mpls_filter), - ('mask', struct_ib_uverbs_flow_mpls_filter), -] - -class struct_ib_uverbs_flow_attr(Structure): - pass - -struct_ib_uverbs_flow_attr._pack_ = 1 # source:False -struct_ib_uverbs_flow_attr._fields_ = [ - ('type', ctypes.c_uint32), - ('size', ctypes.c_uint16), - ('priority', ctypes.c_uint16), - ('num_of_specs', ctypes.c_ubyte), - ('reserved', ctypes.c_ubyte * 2), - ('port', ctypes.c_ubyte), - ('flags', ctypes.c_uint32), - ('flow_specs', struct_ib_uverbs_flow_spec_hdr * 0), -] - -class struct_ib_uverbs_create_flow(Structure): - pass - -struct_ib_uverbs_create_flow._pack_ = 1 # source:False -struct_ib_uverbs_create_flow._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('qp_handle', ctypes.c_uint32), - ('flow_attr', struct_ib_uverbs_flow_attr), -] - -class struct_ib_uverbs_create_flow_resp(Structure): - pass - -struct_ib_uverbs_create_flow_resp._pack_ = 1 # source:False -struct_ib_uverbs_create_flow_resp._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('flow_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_flow(Structure): - pass - -struct_ib_uverbs_destroy_flow._pack_ = 1 # source:False -struct_ib_uverbs_destroy_flow._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('flow_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_create_srq(Structure): - pass - -struct_ib_uverbs_create_srq._pack_ = 1 # source:False -struct_ib_uverbs_create_srq._fields_ = [ - ('response', ctypes.c_uint64), - ('user_handle', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('srq_limit', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_create_xsrq(Structure): - pass - -struct_ib_uverbs_create_xsrq._pack_ = 1 # source:False -struct_ib_uverbs_create_xsrq._fields_ = [ - ('response', ctypes.c_uint64), - ('user_handle', ctypes.c_uint64), - ('srq_type', ctypes.c_uint32), - ('pd_handle', ctypes.c_uint32), - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('srq_limit', ctypes.c_uint32), - ('max_num_tags', ctypes.c_uint32), - ('xrcd_handle', ctypes.c_uint32), - ('cq_handle', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_create_srq_resp(Structure): - pass - -struct_ib_uverbs_create_srq_resp._pack_ = 1 # source:False -struct_ib_uverbs_create_srq_resp._fields_ = [ - ('srq_handle', ctypes.c_uint32), - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('srqn', ctypes.c_uint32), - ('driver_data', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_modify_srq(Structure): - pass - -struct_ib_uverbs_modify_srq._pack_ = 1 # source:False -struct_ib_uverbs_modify_srq._fields_ = [ - ('srq_handle', ctypes.c_uint32), - ('attr_mask', ctypes.c_uint32), - ('max_wr', ctypes.c_uint32), - ('srq_limit', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_query_srq(Structure): - pass - -struct_ib_uverbs_query_srq._pack_ = 1 # source:False -struct_ib_uverbs_query_srq._fields_ = [ - ('response', ctypes.c_uint64), - ('srq_handle', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), - ('driver_data', ctypes.c_uint64 * 0), -] - -class struct_ib_uverbs_query_srq_resp(Structure): - pass - -struct_ib_uverbs_query_srq_resp._pack_ = 1 # source:False -struct_ib_uverbs_query_srq_resp._fields_ = [ - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('srq_limit', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_srq(Structure): - pass - -struct_ib_uverbs_destroy_srq._pack_ = 1 # source:False -struct_ib_uverbs_destroy_srq._fields_ = [ - ('response', ctypes.c_uint64), - ('srq_handle', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_destroy_srq_resp(Structure): - pass - -struct_ib_uverbs_destroy_srq_resp._pack_ = 1 # source:False -struct_ib_uverbs_destroy_srq_resp._fields_ = [ - ('events_reported', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_create_wq(Structure): - pass - -struct_ib_uverbs_ex_create_wq._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_wq._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('wq_type', ctypes.c_uint32), - ('user_handle', ctypes.c_uint64), - ('pd_handle', ctypes.c_uint32), - ('cq_handle', ctypes.c_uint32), - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('create_flags', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_create_wq_resp(Structure): - pass - -struct_ib_uverbs_ex_create_wq_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_wq_resp._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), - ('wq_handle', ctypes.c_uint32), - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('wqn', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_destroy_wq(Structure): - pass - -struct_ib_uverbs_ex_destroy_wq._pack_ = 1 # source:False -struct_ib_uverbs_ex_destroy_wq._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('wq_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_destroy_wq_resp(Structure): - pass - -struct_ib_uverbs_ex_destroy_wq_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_destroy_wq_resp._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), - ('events_reported', ctypes.c_uint32), - ('reserved', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_modify_wq(Structure): - pass - -struct_ib_uverbs_ex_modify_wq._pack_ = 1 # source:False -struct_ib_uverbs_ex_modify_wq._fields_ = [ - ('attr_mask', ctypes.c_uint32), - ('wq_handle', ctypes.c_uint32), - ('wq_state', ctypes.c_uint32), - ('curr_wq_state', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('flags_mask', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_create_rwq_ind_table(Structure): - pass - -struct_ib_uverbs_ex_create_rwq_ind_table._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_rwq_ind_table._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('log_ind_tbl_size', ctypes.c_uint32), - ('wq_handles', ctypes.c_uint32 * 0), -] - -class struct_ib_uverbs_ex_create_rwq_ind_table_resp(Structure): - pass - -struct_ib_uverbs_ex_create_rwq_ind_table_resp._pack_ = 1 # source:False -struct_ib_uverbs_ex_create_rwq_ind_table_resp._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('response_length', ctypes.c_uint32), - ('ind_tbl_handle', ctypes.c_uint32), - ('ind_tbl_num', ctypes.c_uint32), -] - -class struct_ib_uverbs_ex_destroy_rwq_ind_table(Structure): - pass - -struct_ib_uverbs_ex_destroy_rwq_ind_table._pack_ = 1 # source:False -struct_ib_uverbs_ex_destroy_rwq_ind_table._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('ind_tbl_handle', ctypes.c_uint32), -] - -class struct_ib_uverbs_cq_moderation(Structure): - pass - -struct_ib_uverbs_cq_moderation._pack_ = 1 # source:False -struct_ib_uverbs_cq_moderation._fields_ = [ - ('cq_count', ctypes.c_uint16), - ('cq_period', ctypes.c_uint16), -] - -class struct_ib_uverbs_ex_modify_cq(Structure): - pass - -struct_ib_uverbs_ex_modify_cq._pack_ = 1 # source:False -struct_ib_uverbs_ex_modify_cq._fields_ = [ - ('cq_handle', ctypes.c_uint32), - ('attr_mask', ctypes.c_uint32), - ('attr', struct_ib_uverbs_cq_moderation), - ('reserved', ctypes.c_uint32), -] - - -# values for enumeration 'ib_uverbs_device_cap_flags' -ib_uverbs_device_cap_flags__enumvalues = { - 1: 'IB_UVERBS_DEVICE_RESIZE_MAX_WR', - 2: 'IB_UVERBS_DEVICE_BAD_PKEY_CNTR', - 4: 'IB_UVERBS_DEVICE_BAD_QKEY_CNTR', - 8: 'IB_UVERBS_DEVICE_RAW_MULTI', - 16: 'IB_UVERBS_DEVICE_AUTO_PATH_MIG', - 32: 'IB_UVERBS_DEVICE_CHANGE_PHY_PORT', - 64: 'IB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE', - 128: 'IB_UVERBS_DEVICE_CURR_QP_STATE_MOD', - 256: 'IB_UVERBS_DEVICE_SHUTDOWN_PORT', - 1024: 'IB_UVERBS_DEVICE_PORT_ACTIVE_EVENT', - 2048: 'IB_UVERBS_DEVICE_SYS_IMAGE_GUID', - 4096: 'IB_UVERBS_DEVICE_RC_RNR_NAK_GEN', - 8192: 'IB_UVERBS_DEVICE_SRQ_RESIZE', - 16384: 'IB_UVERBS_DEVICE_N_NOTIFY_CQ', - 131072: 'IB_UVERBS_DEVICE_MEM_WINDOW', - 262144: 'IB_UVERBS_DEVICE_UD_IP_CSUM', - 1048576: 'IB_UVERBS_DEVICE_XRC', - 2097152: 'IB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS', - 8388608: 'IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A', - 16777216: 'IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B', - 33554432: 'IB_UVERBS_DEVICE_RC_IP_CSUM', - 67108864: 'IB_UVERBS_DEVICE_RAW_IP_CSUM', - 536870912: 'IB_UVERBS_DEVICE_MANAGED_FLOW_STEERING', - 17179869184: 'IB_UVERBS_DEVICE_RAW_SCATTER_FCS', - 68719476736: 'IB_UVERBS_DEVICE_PCI_WRITE_END_PADDING', - 274877906944: 'IB_UVERBS_DEVICE_FLUSH_GLOBAL', - 549755813888: 'IB_UVERBS_DEVICE_FLUSH_PERSISTENT', - 1099511627776: 'IB_UVERBS_DEVICE_ATOMIC_WRITE', -} -IB_UVERBS_DEVICE_RESIZE_MAX_WR = 1 -IB_UVERBS_DEVICE_BAD_PKEY_CNTR = 2 -IB_UVERBS_DEVICE_BAD_QKEY_CNTR = 4 -IB_UVERBS_DEVICE_RAW_MULTI = 8 -IB_UVERBS_DEVICE_AUTO_PATH_MIG = 16 -IB_UVERBS_DEVICE_CHANGE_PHY_PORT = 32 -IB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE = 64 -IB_UVERBS_DEVICE_CURR_QP_STATE_MOD = 128 -IB_UVERBS_DEVICE_SHUTDOWN_PORT = 256 -IB_UVERBS_DEVICE_PORT_ACTIVE_EVENT = 1024 -IB_UVERBS_DEVICE_SYS_IMAGE_GUID = 2048 -IB_UVERBS_DEVICE_RC_RNR_NAK_GEN = 4096 -IB_UVERBS_DEVICE_SRQ_RESIZE = 8192 -IB_UVERBS_DEVICE_N_NOTIFY_CQ = 16384 -IB_UVERBS_DEVICE_MEM_WINDOW = 131072 -IB_UVERBS_DEVICE_UD_IP_CSUM = 262144 -IB_UVERBS_DEVICE_XRC = 1048576 -IB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS = 2097152 -IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A = 8388608 -IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B = 16777216 -IB_UVERBS_DEVICE_RC_IP_CSUM = 33554432 -IB_UVERBS_DEVICE_RAW_IP_CSUM = 67108864 -IB_UVERBS_DEVICE_MANAGED_FLOW_STEERING = 536870912 -IB_UVERBS_DEVICE_RAW_SCATTER_FCS = 17179869184 -IB_UVERBS_DEVICE_PCI_WRITE_END_PADDING = 68719476736 -IB_UVERBS_DEVICE_FLUSH_GLOBAL = 274877906944 -IB_UVERBS_DEVICE_FLUSH_PERSISTENT = 549755813888 -IB_UVERBS_DEVICE_ATOMIC_WRITE = 1099511627776 -ib_uverbs_device_cap_flags = ctypes.c_uint64 # enum - -# values for enumeration 'ib_uverbs_raw_packet_caps' -ib_uverbs_raw_packet_caps__enumvalues = { - 1: 'IB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING', - 2: 'IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS', - 4: 'IB_UVERBS_RAW_PACKET_CAP_IP_CSUM', - 8: 'IB_UVERBS_RAW_PACKET_CAP_DELAY_DROP', -} -IB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING = 1 -IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS = 2 -IB_UVERBS_RAW_PACKET_CAP_IP_CSUM = 4 -IB_UVERBS_RAW_PACKET_CAP_DELAY_DROP = 8 -ib_uverbs_raw_packet_caps = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_core_support' -ib_uverbs_core_support__enumvalues = { - 1: 'IB_UVERBS_CORE_SUPPORT_OPTIONAL_MR_ACCESS', -} -IB_UVERBS_CORE_SUPPORT_OPTIONAL_MR_ACCESS = 1 -ib_uverbs_core_support = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_access_flags' -ib_uverbs_access_flags__enumvalues = { - 1: 'IB_UVERBS_ACCESS_LOCAL_WRITE', - 2: 'IB_UVERBS_ACCESS_REMOTE_WRITE', - 4: 'IB_UVERBS_ACCESS_REMOTE_READ', - 8: 'IB_UVERBS_ACCESS_REMOTE_ATOMIC', - 16: 'IB_UVERBS_ACCESS_MW_BIND', - 32: 'IB_UVERBS_ACCESS_ZERO_BASED', - 64: 'IB_UVERBS_ACCESS_ON_DEMAND', - 128: 'IB_UVERBS_ACCESS_HUGETLB', - 256: 'IB_UVERBS_ACCESS_FLUSH_GLOBAL', - 512: 'IB_UVERBS_ACCESS_FLUSH_PERSISTENT', - 1048576: 'IB_UVERBS_ACCESS_RELAXED_ORDERING', - 1072693248: 'IB_UVERBS_ACCESS_OPTIONAL_RANGE', -} -IB_UVERBS_ACCESS_LOCAL_WRITE = 1 -IB_UVERBS_ACCESS_REMOTE_WRITE = 2 -IB_UVERBS_ACCESS_REMOTE_READ = 4 -IB_UVERBS_ACCESS_REMOTE_ATOMIC = 8 -IB_UVERBS_ACCESS_MW_BIND = 16 -IB_UVERBS_ACCESS_ZERO_BASED = 32 -IB_UVERBS_ACCESS_ON_DEMAND = 64 -IB_UVERBS_ACCESS_HUGETLB = 128 -IB_UVERBS_ACCESS_FLUSH_GLOBAL = 256 -IB_UVERBS_ACCESS_FLUSH_PERSISTENT = 512 -IB_UVERBS_ACCESS_RELAXED_ORDERING = 1048576 -IB_UVERBS_ACCESS_OPTIONAL_RANGE = 1072693248 -ib_uverbs_access_flags = ctypes.c_uint32 # enum -IBV_ACCESS_OPTIONAL_RANGE = IB_UVERBS_ACCESS_OPTIONAL_RANGE # macro - -# values for enumeration 'ib_uverbs_srq_type' -ib_uverbs_srq_type__enumvalues = { - 0: 'IB_UVERBS_SRQT_BASIC', - 1: 'IB_UVERBS_SRQT_XRC', - 2: 'IB_UVERBS_SRQT_TM', -} -IB_UVERBS_SRQT_BASIC = 0 -IB_UVERBS_SRQT_XRC = 1 -IB_UVERBS_SRQT_TM = 2 -ib_uverbs_srq_type = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_wq_type' -ib_uverbs_wq_type__enumvalues = { - 0: 'IB_UVERBS_WQT_RQ', -} -IB_UVERBS_WQT_RQ = 0 -ib_uverbs_wq_type = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_wq_flags' -ib_uverbs_wq_flags__enumvalues = { - 1: 'IB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING', - 2: 'IB_UVERBS_WQ_FLAGS_SCATTER_FCS', - 4: 'IB_UVERBS_WQ_FLAGS_DELAY_DROP', - 8: 'IB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING', -} -IB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING = 1 -IB_UVERBS_WQ_FLAGS_SCATTER_FCS = 2 -IB_UVERBS_WQ_FLAGS_DELAY_DROP = 4 -IB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING = 8 -ib_uverbs_wq_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_qp_type' -ib_uverbs_qp_type__enumvalues = { - 2: 'IB_UVERBS_QPT_RC', - 3: 'IB_UVERBS_QPT_UC', - 4: 'IB_UVERBS_QPT_UD', - 8: 'IB_UVERBS_QPT_RAW_PACKET', - 9: 'IB_UVERBS_QPT_XRC_INI', - 10: 'IB_UVERBS_QPT_XRC_TGT', - 255: 'IB_UVERBS_QPT_DRIVER', -} -IB_UVERBS_QPT_RC = 2 -IB_UVERBS_QPT_UC = 3 -IB_UVERBS_QPT_UD = 4 -IB_UVERBS_QPT_RAW_PACKET = 8 -IB_UVERBS_QPT_XRC_INI = 9 -IB_UVERBS_QPT_XRC_TGT = 10 -IB_UVERBS_QPT_DRIVER = 255 -ib_uverbs_qp_type = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_qp_create_flags' -ib_uverbs_qp_create_flags__enumvalues = { - 2: 'IB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK', - 256: 'IB_UVERBS_QP_CREATE_SCATTER_FCS', - 512: 'IB_UVERBS_QP_CREATE_CVLAN_STRIPPING', - 2048: 'IB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING', - 4096: 'IB_UVERBS_QP_CREATE_SQ_SIG_ALL', -} -IB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 2 -IB_UVERBS_QP_CREATE_SCATTER_FCS = 256 -IB_UVERBS_QP_CREATE_CVLAN_STRIPPING = 512 -IB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING = 2048 -IB_UVERBS_QP_CREATE_SQ_SIG_ALL = 4096 -ib_uverbs_qp_create_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_query_port_cap_flags' -ib_uverbs_query_port_cap_flags__enumvalues = { - 2: 'IB_UVERBS_PCF_SM', - 4: 'IB_UVERBS_PCF_NOTICE_SUP', - 8: 'IB_UVERBS_PCF_TRAP_SUP', - 16: 'IB_UVERBS_PCF_OPT_IPD_SUP', - 32: 'IB_UVERBS_PCF_AUTO_MIGR_SUP', - 64: 'IB_UVERBS_PCF_SL_MAP_SUP', - 128: 'IB_UVERBS_PCF_MKEY_NVRAM', - 256: 'IB_UVERBS_PCF_PKEY_NVRAM', - 512: 'IB_UVERBS_PCF_LED_INFO_SUP', - 1024: 'IB_UVERBS_PCF_SM_DISABLED', - 2048: 'IB_UVERBS_PCF_SYS_IMAGE_GUID_SUP', - 4096: 'IB_UVERBS_PCF_PKEY_SW_EXT_PORT_TRAP_SUP', - 16384: 'IB_UVERBS_PCF_EXTENDED_SPEEDS_SUP', - 65536: 'IB_UVERBS_PCF_CM_SUP', - 131072: 'IB_UVERBS_PCF_SNMP_TUNNEL_SUP', - 262144: 'IB_UVERBS_PCF_REINIT_SUP', - 524288: 'IB_UVERBS_PCF_DEVICE_MGMT_SUP', - 1048576: 'IB_UVERBS_PCF_VENDOR_CLASS_SUP', - 2097152: 'IB_UVERBS_PCF_DR_NOTICE_SUP', - 4194304: 'IB_UVERBS_PCF_CAP_MASK_NOTICE_SUP', - 8388608: 'IB_UVERBS_PCF_BOOT_MGMT_SUP', - 16777216: 'IB_UVERBS_PCF_LINK_LATENCY_SUP', - 33554432: 'IB_UVERBS_PCF_CLIENT_REG_SUP', - 134217728: 'IB_UVERBS_PCF_LINK_SPEED_WIDTH_TABLE_SUP', - 268435456: 'IB_UVERBS_PCF_VENDOR_SPECIFIC_MADS_TABLE_SUP', - 536870912: 'IB_UVERBS_PCF_MCAST_PKEY_TRAP_SUPPRESSION_SUP', - 1073741824: 'IB_UVERBS_PCF_MCAST_FDB_TOP_SUP', - 2147483648: 'IB_UVERBS_PCF_HIERARCHY_INFO_SUP', - 67108864: 'IB_UVERBS_PCF_IP_BASED_GIDS', -} -IB_UVERBS_PCF_SM = 2 -IB_UVERBS_PCF_NOTICE_SUP = 4 -IB_UVERBS_PCF_TRAP_SUP = 8 -IB_UVERBS_PCF_OPT_IPD_SUP = 16 -IB_UVERBS_PCF_AUTO_MIGR_SUP = 32 -IB_UVERBS_PCF_SL_MAP_SUP = 64 -IB_UVERBS_PCF_MKEY_NVRAM = 128 -IB_UVERBS_PCF_PKEY_NVRAM = 256 -IB_UVERBS_PCF_LED_INFO_SUP = 512 -IB_UVERBS_PCF_SM_DISABLED = 1024 -IB_UVERBS_PCF_SYS_IMAGE_GUID_SUP = 2048 -IB_UVERBS_PCF_PKEY_SW_EXT_PORT_TRAP_SUP = 4096 -IB_UVERBS_PCF_EXTENDED_SPEEDS_SUP = 16384 -IB_UVERBS_PCF_CM_SUP = 65536 -IB_UVERBS_PCF_SNMP_TUNNEL_SUP = 131072 -IB_UVERBS_PCF_REINIT_SUP = 262144 -IB_UVERBS_PCF_DEVICE_MGMT_SUP = 524288 -IB_UVERBS_PCF_VENDOR_CLASS_SUP = 1048576 -IB_UVERBS_PCF_DR_NOTICE_SUP = 2097152 -IB_UVERBS_PCF_CAP_MASK_NOTICE_SUP = 4194304 -IB_UVERBS_PCF_BOOT_MGMT_SUP = 8388608 -IB_UVERBS_PCF_LINK_LATENCY_SUP = 16777216 -IB_UVERBS_PCF_CLIENT_REG_SUP = 33554432 -IB_UVERBS_PCF_LINK_SPEED_WIDTH_TABLE_SUP = 134217728 -IB_UVERBS_PCF_VENDOR_SPECIFIC_MADS_TABLE_SUP = 268435456 -IB_UVERBS_PCF_MCAST_PKEY_TRAP_SUPPRESSION_SUP = 536870912 -IB_UVERBS_PCF_MCAST_FDB_TOP_SUP = 1073741824 -IB_UVERBS_PCF_HIERARCHY_INFO_SUP = 2147483648 -IB_UVERBS_PCF_IP_BASED_GIDS = 67108864 -ib_uverbs_query_port_cap_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_query_port_flags' -ib_uverbs_query_port_flags__enumvalues = { - 1: 'IB_UVERBS_QPF_GRH_REQUIRED', -} -IB_UVERBS_QPF_GRH_REQUIRED = 1 -ib_uverbs_query_port_flags = ctypes.c_uint32 # enum -IBV_QPF_GRH_REQUIRED = IB_UVERBS_QPF_GRH_REQUIRED # macro - -# values for enumeration 'ib_uverbs_flow_action_esp_keymat' -ib_uverbs_flow_action_esp_keymat__enumvalues = { - 0: 'IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM', -} -IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM = 0 -ib_uverbs_flow_action_esp_keymat = ctypes.c_uint32 # enum -ibv_flow_action_esp_keymat = ib_uverbs_flow_action_esp_keymat # macro -IBV_FLOW_ACTION_ESP_KEYMAT_AES_GCM = IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM # macro - -# values for enumeration 'ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo' -ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo__enumvalues = { - 0: 'IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ', -} -IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ = 0 -ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo = ctypes.c_uint32 # enum -ibv_flow_action_esp_keymat_aes_gcm_iv_algo = ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo # macro -IBV_FLOW_ACTION_IV_ALGO_SEQ = IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ # macro -class struct_ib_uverbs_flow_action_esp_keymat_aes_gcm(Structure): - pass - -struct_ib_uverbs_flow_action_esp_keymat_aes_gcm._pack_ = 1 # source:False -struct_ib_uverbs_flow_action_esp_keymat_aes_gcm._fields_ = [ - ('iv', ctypes.c_uint64), - ('iv_algo', ctypes.c_uint32), - ('salt', ctypes.c_uint32), - ('icv_len', ctypes.c_uint32), - ('key_len', ctypes.c_uint32), - ('aes_key', ctypes.c_uint32 * 8), -] - - -# values for enumeration 'ib_uverbs_flow_action_esp_replay' -ib_uverbs_flow_action_esp_replay__enumvalues = { - 0: 'IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE', - 1: 'IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP', -} -IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE = 0 -IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP = 1 -ib_uverbs_flow_action_esp_replay = ctypes.c_uint32 # enum -ibv_flow_action_esp_replay = ib_uverbs_flow_action_esp_replay # macro -IBV_FLOW_ACTION_ESP_REPLAY_NONE = IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE # macro -IBV_FLOW_ACTION_ESP_REPLAY_BMP = IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP # macro -class struct_ib_uverbs_flow_action_esp_replay_bmp(Structure): - pass - -struct_ib_uverbs_flow_action_esp_replay_bmp._pack_ = 1 # source:False -struct_ib_uverbs_flow_action_esp_replay_bmp._fields_ = [ - ('size', ctypes.c_uint32), -] - - -# values for enumeration 'ib_uverbs_flow_action_esp_flags' -ib_uverbs_flow_action_esp_flags__enumvalues = { - 0: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO', - 1: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD', - 0: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL', - 2: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT', - 0: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT', - 4: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT', - 8: 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW', -} -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO = 0 -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD = 1 -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL = 0 -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT = 2 -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT = 0 -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT = 4 -IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW = 8 -ib_uverbs_flow_action_esp_flags = ctypes.c_uint32 # enum -ibv_flow_action_esp_flags = ib_uverbs_flow_action_esp_flags # macro -IBV_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO # macro -IBV_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD # macro -IBV_FLOW_ACTION_ESP_FLAGS_TUNNEL = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL # macro -IBV_FLOW_ACTION_ESP_FLAGS_TRANSPORT = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT # macro -IBV_FLOW_ACTION_ESP_FLAGS_DECRYPT = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT # macro -IBV_FLOW_ACTION_ESP_FLAGS_ENCRYPT = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT # macro -IBV_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW = IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW # macro -class struct_ib_uverbs_flow_action_esp_encap(Structure): - pass - -class union_ib_uverbs_flow_action_esp_encap_0(Union): - pass - -union_ib_uverbs_flow_action_esp_encap_0._pack_ = 1 # source:False -union_ib_uverbs_flow_action_esp_encap_0._fields_ = [ - ('val_ptr', ctypes.POINTER(None)), - ('val_ptr_data_u64', ctypes.c_uint64), -] - -class union_ib_uverbs_flow_action_esp_encap_1(Union): - pass - -union_ib_uverbs_flow_action_esp_encap_1._pack_ = 1 # source:False -union_ib_uverbs_flow_action_esp_encap_1._fields_ = [ - ('next_ptr', ctypes.POINTER(struct_ib_uverbs_flow_action_esp_encap)), - ('next_ptr_data_u64', ctypes.c_uint64), -] - -struct_ib_uverbs_flow_action_esp_encap._pack_ = 1 # source:False -struct_ib_uverbs_flow_action_esp_encap._anonymous_ = ('_0', '_1',) -struct_ib_uverbs_flow_action_esp_encap._fields_ = [ - ('_0', union_ib_uverbs_flow_action_esp_encap_0), - ('_1', union_ib_uverbs_flow_action_esp_encap_1), - ('len', ctypes.c_uint16), - ('type', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_ib_uverbs_flow_action_esp(Structure): - pass - -struct_ib_uverbs_flow_action_esp._pack_ = 1 # source:False -struct_ib_uverbs_flow_action_esp._fields_ = [ - ('spi', ctypes.c_uint32), - ('seq', ctypes.c_uint32), - ('tfc_pad', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('hard_limit_pkts', ctypes.c_uint64), -] - - -# values for enumeration 'ib_uverbs_read_counters_flags' -ib_uverbs_read_counters_flags__enumvalues = { - 1: 'IB_UVERBS_READ_COUNTERS_PREFER_CACHED', -} -IB_UVERBS_READ_COUNTERS_PREFER_CACHED = 1 -ib_uverbs_read_counters_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_advise_mr_advice' -ib_uverbs_advise_mr_advice__enumvalues = { - 0: 'IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH', - 1: 'IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE', - 2: 'IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT', -} -IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH = 0 -IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE = 1 -IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = 2 -ib_uverbs_advise_mr_advice = ctypes.c_uint32 # enum -ibv_advise_mr_advice = ib_uverbs_advise_mr_advice # macro -IBV_ADVISE_MR_ADVICE_PREFETCH = IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH # macro -IBV_ADVISE_MR_ADVICE_PREFETCH_WRITE = IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE # macro -IBV_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT = IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT # macro - -# values for enumeration 'ib_uverbs_advise_mr_flag' -ib_uverbs_advise_mr_flag__enumvalues = { - 1: 'IB_UVERBS_ADVISE_MR_FLAG_FLUSH', -} -IB_UVERBS_ADVISE_MR_FLAG_FLUSH = 1 -ib_uverbs_advise_mr_flag = ctypes.c_uint32 # enum -IBV_ADVISE_MR_FLAG_FLUSH = IB_UVERBS_ADVISE_MR_FLAG_FLUSH # macro -class struct_ib_uverbs_query_port_resp_ex(Structure): - pass - -struct_ib_uverbs_query_port_resp_ex._pack_ = 1 # source:False -struct_ib_uverbs_query_port_resp_ex._fields_ = [ - ('legacy_resp', struct_ib_uverbs_query_port_resp), - ('port_cap_flags2', ctypes.c_uint16), - ('reserved', ctypes.c_ubyte * 2), - ('active_speed_ex', ctypes.c_uint32), -] - -class struct_ib_uverbs_qp_cap(Structure): - pass - -struct_ib_uverbs_qp_cap._pack_ = 1 # source:False -struct_ib_uverbs_qp_cap._fields_ = [ - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), -] - - -# values for enumeration 'rdma_driver_id' -rdma_driver_id__enumvalues = { - 0: 'RDMA_DRIVER_UNKNOWN', - 1: 'RDMA_DRIVER_MLX5', - 2: 'RDMA_DRIVER_MLX4', - 3: 'RDMA_DRIVER_CXGB3', - 4: 'RDMA_DRIVER_CXGB4', - 5: 'RDMA_DRIVER_MTHCA', - 6: 'RDMA_DRIVER_BNXT_RE', - 7: 'RDMA_DRIVER_OCRDMA', - 8: 'RDMA_DRIVER_NES', - 9: 'RDMA_DRIVER_I40IW', - 9: 'RDMA_DRIVER_IRDMA', - 10: 'RDMA_DRIVER_VMW_PVRDMA', - 11: 'RDMA_DRIVER_QEDR', - 12: 'RDMA_DRIVER_HNS', - 13: 'RDMA_DRIVER_USNIC', - 14: 'RDMA_DRIVER_RXE', - 15: 'RDMA_DRIVER_HFI1', - 16: 'RDMA_DRIVER_QIB', - 17: 'RDMA_DRIVER_EFA', - 18: 'RDMA_DRIVER_SIW', - 19: 'RDMA_DRIVER_ERDMA', - 20: 'RDMA_DRIVER_MANA', -} -RDMA_DRIVER_UNKNOWN = 0 -RDMA_DRIVER_MLX5 = 1 -RDMA_DRIVER_MLX4 = 2 -RDMA_DRIVER_CXGB3 = 3 -RDMA_DRIVER_CXGB4 = 4 -RDMA_DRIVER_MTHCA = 5 -RDMA_DRIVER_BNXT_RE = 6 -RDMA_DRIVER_OCRDMA = 7 -RDMA_DRIVER_NES = 8 -RDMA_DRIVER_I40IW = 9 -RDMA_DRIVER_IRDMA = 9 -RDMA_DRIVER_VMW_PVRDMA = 10 -RDMA_DRIVER_QEDR = 11 -RDMA_DRIVER_HNS = 12 -RDMA_DRIVER_USNIC = 13 -RDMA_DRIVER_RXE = 14 -RDMA_DRIVER_HFI1 = 15 -RDMA_DRIVER_QIB = 16 -RDMA_DRIVER_EFA = 17 -RDMA_DRIVER_SIW = 18 -RDMA_DRIVER_ERDMA = 19 -RDMA_DRIVER_MANA = 20 -rdma_driver_id = ctypes.c_uint32 # enum - -# values for enumeration 'ib_uverbs_gid_type' -ib_uverbs_gid_type__enumvalues = { - 0: 'IB_UVERBS_GID_TYPE_IB', - 1: 'IB_UVERBS_GID_TYPE_ROCE_V1', - 2: 'IB_UVERBS_GID_TYPE_ROCE_V2', -} -IB_UVERBS_GID_TYPE_IB = 0 -IB_UVERBS_GID_TYPE_ROCE_V1 = 1 -IB_UVERBS_GID_TYPE_ROCE_V2 = 2 -ib_uverbs_gid_type = ctypes.c_uint32 # enum -class struct_ib_uverbs_gid_entry(Structure): - pass - -struct_ib_uverbs_gid_entry._pack_ = 1 # source:False -struct_ib_uverbs_gid_entry._fields_ = [ - ('gid', ctypes.c_uint64 * 2), - ('gid_index', ctypes.c_uint32), - ('port_num', ctypes.c_uint32), - ('gid_type', ctypes.c_uint32), - ('netdev_ifindex', ctypes.c_uint32), -] - -class union_ibv_gid(Union): - pass - -class struct_ibv_gid_global(Structure): - pass - -struct_ibv_gid_global._pack_ = 1 # source:False -struct_ibv_gid_global._fields_ = [ - ('subnet_prefix', ctypes.c_uint64), - ('interface_id', ctypes.c_uint64), -] - -union_ibv_gid._pack_ = 1 # source:False -union_ibv_gid._fields_ = [ - ('raw', ctypes.c_ubyte * 16), - ('global', struct_ibv_gid_global), -] - - -# values for enumeration 'ibv_gid_type' -ibv_gid_type__enumvalues = { - 0: 'IBV_GID_TYPE_IB', - 1: 'IBV_GID_TYPE_ROCE_V1', - 2: 'IBV_GID_TYPE_ROCE_V2', -} -IBV_GID_TYPE_IB = 0 -IBV_GID_TYPE_ROCE_V1 = 1 -IBV_GID_TYPE_ROCE_V2 = 2 -ibv_gid_type = ctypes.c_uint32 # enum -class struct_ibv_gid_entry(Structure): - pass - -struct_ibv_gid_entry._pack_ = 1 # source:False -struct_ibv_gid_entry._fields_ = [ - ('gid', union_ibv_gid), - ('gid_index', ctypes.c_uint32), - ('port_num', ctypes.c_uint32), - ('gid_type', ctypes.c_uint32), - ('ndev_ifindex', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_node_type' -ibv_node_type__enumvalues = { - -1: 'IBV_NODE_UNKNOWN', - 1: 'IBV_NODE_CA', - 2: 'IBV_NODE_SWITCH', - 3: 'IBV_NODE_ROUTER', - 4: 'IBV_NODE_RNIC', - 5: 'IBV_NODE_USNIC', - 6: 'IBV_NODE_USNIC_UDP', - 7: 'IBV_NODE_UNSPECIFIED', -} -IBV_NODE_UNKNOWN = -1 -IBV_NODE_CA = 1 -IBV_NODE_SWITCH = 2 -IBV_NODE_ROUTER = 3 -IBV_NODE_RNIC = 4 -IBV_NODE_USNIC = 5 -IBV_NODE_USNIC_UDP = 6 -IBV_NODE_UNSPECIFIED = 7 -ibv_node_type = ctypes.c_int32 # enum - -# values for enumeration 'ibv_transport_type' -ibv_transport_type__enumvalues = { - -1: 'IBV_TRANSPORT_UNKNOWN', - 0: 'IBV_TRANSPORT_IB', - 1: 'IBV_TRANSPORT_IWARP', - 2: 'IBV_TRANSPORT_USNIC', - 3: 'IBV_TRANSPORT_USNIC_UDP', - 4: 'IBV_TRANSPORT_UNSPECIFIED', -} -IBV_TRANSPORT_UNKNOWN = -1 -IBV_TRANSPORT_IB = 0 -IBV_TRANSPORT_IWARP = 1 -IBV_TRANSPORT_USNIC = 2 -IBV_TRANSPORT_USNIC_UDP = 3 -IBV_TRANSPORT_UNSPECIFIED = 4 -ibv_transport_type = ctypes.c_int32 # enum - -# values for enumeration 'ibv_device_cap_flags' -ibv_device_cap_flags__enumvalues = { - 1: 'IBV_DEVICE_RESIZE_MAX_WR', - 2: 'IBV_DEVICE_BAD_PKEY_CNTR', - 4: 'IBV_DEVICE_BAD_QKEY_CNTR', - 8: 'IBV_DEVICE_RAW_MULTI', - 16: 'IBV_DEVICE_AUTO_PATH_MIG', - 32: 'IBV_DEVICE_CHANGE_PHY_PORT', - 64: 'IBV_DEVICE_UD_AV_PORT_ENFORCE', - 128: 'IBV_DEVICE_CURR_QP_STATE_MOD', - 256: 'IBV_DEVICE_SHUTDOWN_PORT', - 512: 'IBV_DEVICE_INIT_TYPE', - 1024: 'IBV_DEVICE_PORT_ACTIVE_EVENT', - 2048: 'IBV_DEVICE_SYS_IMAGE_GUID', - 4096: 'IBV_DEVICE_RC_RNR_NAK_GEN', - 8192: 'IBV_DEVICE_SRQ_RESIZE', - 16384: 'IBV_DEVICE_N_NOTIFY_CQ', - 131072: 'IBV_DEVICE_MEM_WINDOW', - 262144: 'IBV_DEVICE_UD_IP_CSUM', - 1048576: 'IBV_DEVICE_XRC', - 2097152: 'IBV_DEVICE_MEM_MGT_EXTENSIONS', - 8388608: 'IBV_DEVICE_MEM_WINDOW_TYPE_2A', - 16777216: 'IBV_DEVICE_MEM_WINDOW_TYPE_2B', - 33554432: 'IBV_DEVICE_RC_IP_CSUM', - 67108864: 'IBV_DEVICE_RAW_IP_CSUM', - 536870912: 'IBV_DEVICE_MANAGED_FLOW_STEERING', -} -IBV_DEVICE_RESIZE_MAX_WR = 1 -IBV_DEVICE_BAD_PKEY_CNTR = 2 -IBV_DEVICE_BAD_QKEY_CNTR = 4 -IBV_DEVICE_RAW_MULTI = 8 -IBV_DEVICE_AUTO_PATH_MIG = 16 -IBV_DEVICE_CHANGE_PHY_PORT = 32 -IBV_DEVICE_UD_AV_PORT_ENFORCE = 64 -IBV_DEVICE_CURR_QP_STATE_MOD = 128 -IBV_DEVICE_SHUTDOWN_PORT = 256 -IBV_DEVICE_INIT_TYPE = 512 -IBV_DEVICE_PORT_ACTIVE_EVENT = 1024 -IBV_DEVICE_SYS_IMAGE_GUID = 2048 -IBV_DEVICE_RC_RNR_NAK_GEN = 4096 -IBV_DEVICE_SRQ_RESIZE = 8192 -IBV_DEVICE_N_NOTIFY_CQ = 16384 -IBV_DEVICE_MEM_WINDOW = 131072 -IBV_DEVICE_UD_IP_CSUM = 262144 -IBV_DEVICE_XRC = 1048576 -IBV_DEVICE_MEM_MGT_EXTENSIONS = 2097152 -IBV_DEVICE_MEM_WINDOW_TYPE_2A = 8388608 -IBV_DEVICE_MEM_WINDOW_TYPE_2B = 16777216 -IBV_DEVICE_RC_IP_CSUM = 33554432 -IBV_DEVICE_RAW_IP_CSUM = 67108864 -IBV_DEVICE_MANAGED_FLOW_STEERING = 536870912 -ibv_device_cap_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_fork_status' -ibv_fork_status__enumvalues = { - 0: 'IBV_FORK_DISABLED', - 1: 'IBV_FORK_ENABLED', - 2: 'IBV_FORK_UNNEEDED', -} -IBV_FORK_DISABLED = 0 -IBV_FORK_ENABLED = 1 -IBV_FORK_UNNEEDED = 2 -ibv_fork_status = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_atomic_cap' -ibv_atomic_cap__enumvalues = { - 0: 'IBV_ATOMIC_NONE', - 1: 'IBV_ATOMIC_HCA', - 2: 'IBV_ATOMIC_GLOB', -} -IBV_ATOMIC_NONE = 0 -IBV_ATOMIC_HCA = 1 -IBV_ATOMIC_GLOB = 2 -ibv_atomic_cap = ctypes.c_uint32 # enum -class struct_ibv_alloc_dm_attr(Structure): - pass - -struct_ibv_alloc_dm_attr._pack_ = 1 # source:False -struct_ibv_alloc_dm_attr._fields_ = [ - ('length', ctypes.c_uint64), - ('log_align_req', ctypes.c_uint32), - ('comp_mask', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_dm_mask' -ibv_dm_mask__enumvalues = { - 1: 'IBV_DM_MASK_HANDLE', -} -IBV_DM_MASK_HANDLE = 1 -ibv_dm_mask = ctypes.c_uint32 # enum -class struct_ibv_dm(Structure): - pass - -class struct_ibv_context(Structure): - pass - -struct_ibv_dm._pack_ = 1 # source:False -struct_ibv_dm._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('memcpy_to_dm', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_dm), ctypes.c_uint64, ctypes.POINTER(None), ctypes.c_uint64)), - ('memcpy_from_dm', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(None), ctypes.POINTER(struct_ibv_dm), ctypes.c_uint64, ctypes.c_uint64)), - ('comp_mask', ctypes.c_uint32), - ('handle', ctypes.c_uint32), -] - -class struct_ibv_device(Structure): - pass - -class struct_ibv_context_ops(Structure): - pass - -class struct_ibv_device_attr(Structure): - pass - -class struct__compat_ibv_port_attr(Structure): - pass - -class struct_ibv_mw(Structure): - pass - -class struct_ibv_pd(Structure): - pass - - -# values for enumeration 'ibv_mw_type' -ibv_mw_type__enumvalues = { - 1: 'IBV_MW_TYPE_1', - 2: 'IBV_MW_TYPE_2', -} -IBV_MW_TYPE_1 = 1 -IBV_MW_TYPE_2 = 2 -ibv_mw_type = ctypes.c_uint32 # enum -class struct_ibv_qp(Structure): - pass - -class struct_ibv_mw_bind(Structure): - pass - -class struct_ibv_cq(Structure): - pass - -class struct_ibv_wc(Structure): - pass - -class struct_ibv_srq(Structure): - pass - -class struct_ibv_recv_wr(Structure): - pass - -class struct_ibv_send_wr(Structure): - pass - -struct_ibv_context_ops._pack_ = 1 # source:False -struct_ibv_context_ops._fields_ = [ - ('_compat_query_device', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_device_attr))), - ('_compat_query_port', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.c_ubyte, ctypes.POINTER(struct__compat_ibv_port_attr))), - ('_compat_alloc_pd', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_dealloc_pd', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_reg_mr', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_rereg_mr', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_dereg_mr', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('alloc_mw', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_mw), ctypes.POINTER(struct_ibv_pd), ibv_mw_type)), - ('bind_mw', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_mw), ctypes.POINTER(struct_ibv_mw_bind))), - ('dealloc_mw', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_mw))), - ('_compat_create_cq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('poll_cq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq), ctypes.c_int32, ctypes.POINTER(struct_ibv_wc))), - ('req_notify_cq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq), ctypes.c_int32)), - ('_compat_cq_event', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_resize_cq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_destroy_cq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_create_srq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_modify_srq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_query_srq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_destroy_srq', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('post_srq_recv', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr)))), - ('_compat_create_qp', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_query_qp', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_modify_qp', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_destroy_qp', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('post_send', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_send_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_send_wr)))), - ('post_recv', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr)))), - ('_compat_create_ah', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_destroy_ah', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_attach_mcast', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_detach_mcast', ctypes.CFUNCTYPE(ctypes.POINTER(None))), - ('_compat_async_event', ctypes.CFUNCTYPE(ctypes.POINTER(None))), -] - -class union_c__UA_pthread_mutex_t(Union): - pass - -class struct___pthread_mutex_s(Structure): - pass - -class struct___pthread_internal_list(Structure): - pass - -struct___pthread_internal_list._pack_ = 1 # source:False -struct___pthread_internal_list._fields_ = [ - ('__prev', ctypes.POINTER(struct___pthread_internal_list)), - ('__next', ctypes.POINTER(struct___pthread_internal_list)), -] - -struct___pthread_mutex_s._pack_ = 1 # source:False -struct___pthread_mutex_s._fields_ = [ - ('__lock', ctypes.c_int32), - ('__count', ctypes.c_uint32), - ('__owner', ctypes.c_int32), - ('__nusers', ctypes.c_uint32), - ('__kind', ctypes.c_int32), - ('__spins', ctypes.c_int16), - ('__elision', ctypes.c_int16), - ('__list', struct___pthread_internal_list), -] - -union_c__UA_pthread_mutex_t._pack_ = 1 # source:False -union_c__UA_pthread_mutex_t._fields_ = [ - ('__data', struct___pthread_mutex_s), - ('__size', ctypes.c_char * 40), - ('__align', ctypes.c_int64), - ('PADDING_0', ctypes.c_ubyte * 32), -] - -struct_ibv_context._pack_ = 1 # source:False -struct_ibv_context._fields_ = [ - ('device', ctypes.POINTER(struct_ibv_device)), - ('ops', struct_ibv_context_ops), - ('cmd_fd', ctypes.c_int32), - ('async_fd', ctypes.c_int32), - ('num_comp_vectors', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('mutex', union_c__UA_pthread_mutex_t), - ('abi_compat', ctypes.POINTER(None)), -] - -class struct__ibv_device_ops(Structure): - pass - -struct__ibv_device_ops._pack_ = 1 # source:False -struct__ibv_device_ops._fields_ = [ - ('_dummy1', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_device), ctypes.c_int32)), - ('_dummy2', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_context))), -] - -struct_ibv_device._pack_ = 1 # source:False -struct_ibv_device._fields_ = [ - ('_ops', struct__ibv_device_ops), - ('node_type', ibv_node_type), - ('transport_type', ibv_transport_type), - ('name', ctypes.c_char * 64), - ('dev_name', ctypes.c_char * 64), - ('dev_path', ctypes.c_char * 256), - ('ibdev_path', ctypes.c_char * 256), -] - -struct_ibv_device_attr._pack_ = 1 # source:False -struct_ibv_device_attr._fields_ = [ - ('fw_ver', ctypes.c_char * 64), - ('node_guid', ctypes.c_uint64), - ('sys_image_guid', ctypes.c_uint64), - ('max_mr_size', ctypes.c_uint64), - ('page_size_cap', ctypes.c_uint64), - ('vendor_id', ctypes.c_uint32), - ('vendor_part_id', ctypes.c_uint32), - ('hw_ver', ctypes.c_uint32), - ('max_qp', ctypes.c_int32), - ('max_qp_wr', ctypes.c_int32), - ('device_cap_flags', ctypes.c_uint32), - ('max_sge', ctypes.c_int32), - ('max_sge_rd', ctypes.c_int32), - ('max_cq', ctypes.c_int32), - ('max_cqe', ctypes.c_int32), - ('max_mr', ctypes.c_int32), - ('max_pd', ctypes.c_int32), - ('max_qp_rd_atom', ctypes.c_int32), - ('max_ee_rd_atom', ctypes.c_int32), - ('max_res_rd_atom', ctypes.c_int32), - ('max_qp_init_rd_atom', ctypes.c_int32), - ('max_ee_init_rd_atom', ctypes.c_int32), - ('atomic_cap', ibv_atomic_cap), - ('max_ee', ctypes.c_int32), - ('max_rdd', ctypes.c_int32), - ('max_mw', ctypes.c_int32), - ('max_raw_ipv6_qp', ctypes.c_int32), - ('max_raw_ethy_qp', ctypes.c_int32), - ('max_mcast_grp', ctypes.c_int32), - ('max_mcast_qp_attach', ctypes.c_int32), - ('max_total_mcast_qp_attach', ctypes.c_int32), - ('max_ah', ctypes.c_int32), - ('max_fmr', ctypes.c_int32), - ('max_map_per_fmr', ctypes.c_int32), - ('max_srq', ctypes.c_int32), - ('max_srq_wr', ctypes.c_int32), - ('max_srq_sge', ctypes.c_int32), - ('max_pkeys', ctypes.c_uint16), - ('local_ca_ack_delay', ctypes.c_ubyte), - ('phys_port_cnt', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_ibv_mw._pack_ = 1 # source:False -struct_ibv_mw._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('rkey', ctypes.c_uint32), - ('handle', ctypes.c_uint32), - ('type', ibv_mw_type), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_ibv_pd._pack_ = 1 # source:False -struct_ibv_pd._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('handle', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_qp_state' -ibv_qp_state__enumvalues = { - 0: 'IBV_QPS_RESET', - 1: 'IBV_QPS_INIT', - 2: 'IBV_QPS_RTR', - 3: 'IBV_QPS_RTS', - 4: 'IBV_QPS_SQD', - 5: 'IBV_QPS_SQE', - 6: 'IBV_QPS_ERR', - 7: 'IBV_QPS_UNKNOWN', -} -IBV_QPS_RESET = 0 -IBV_QPS_INIT = 1 -IBV_QPS_RTR = 2 -IBV_QPS_RTS = 3 -IBV_QPS_SQD = 4 -IBV_QPS_SQE = 5 -IBV_QPS_ERR = 6 -IBV_QPS_UNKNOWN = 7 -ibv_qp_state = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_qp_type' -ibv_qp_type__enumvalues = { - 2: 'IBV_QPT_RC', - 3: 'IBV_QPT_UC', - 4: 'IBV_QPT_UD', - 8: 'IBV_QPT_RAW_PACKET', - 9: 'IBV_QPT_XRC_SEND', - 10: 'IBV_QPT_XRC_RECV', - 255: 'IBV_QPT_DRIVER', -} -IBV_QPT_RC = 2 -IBV_QPT_UC = 3 -IBV_QPT_UD = 4 -IBV_QPT_RAW_PACKET = 8 -IBV_QPT_XRC_SEND = 9 -IBV_QPT_XRC_RECV = 10 -IBV_QPT_DRIVER = 255 -ibv_qp_type = ctypes.c_uint32 # enum -class union_c__UA_pthread_cond_t(Union): - pass - -class struct___pthread_cond_s(Structure): - pass - -class union_c__UA___atomic_wide_counter(Union): - pass - -class struct_c__UA___atomic_wide_counter___value32(Structure): - pass - -struct_c__UA___atomic_wide_counter___value32._pack_ = 1 # source:False -struct_c__UA___atomic_wide_counter___value32._fields_ = [ - ('__low', ctypes.c_uint32), - ('__high', ctypes.c_uint32), -] - -union_c__UA___atomic_wide_counter._pack_ = 1 # source:False -union_c__UA___atomic_wide_counter._fields_ = [ - ('__value64', ctypes.c_uint64), - ('__value32', struct_c__UA___atomic_wide_counter___value32), -] - -struct___pthread_cond_s._pack_ = 1 # source:False -struct___pthread_cond_s._fields_ = [ - ('__wseq', union_c__UA___atomic_wide_counter), - ('__g1_start', union_c__UA___atomic_wide_counter), - ('__g_refs', ctypes.c_uint32 * 2), - ('__g_size', ctypes.c_uint32 * 2), - ('__g1_orig_size', ctypes.c_uint32), - ('__wrefs', ctypes.c_uint32), - ('__g_signals', ctypes.c_uint32 * 2), -] - -union_c__UA_pthread_cond_t._pack_ = 1 # source:False -union_c__UA_pthread_cond_t._fields_ = [ - ('__data', struct___pthread_cond_s), - ('__size', ctypes.c_char * 48), - ('__align', ctypes.c_int64), - ('PADDING_0', ctypes.c_ubyte * 40), -] - -struct_ibv_qp._pack_ = 1 # source:False -struct_ibv_qp._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('qp_context', ctypes.POINTER(None)), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('send_cq', ctypes.POINTER(struct_ibv_cq)), - ('recv_cq', ctypes.POINTER(struct_ibv_cq)), - ('srq', ctypes.POINTER(struct_ibv_srq)), - ('handle', ctypes.c_uint32), - ('qp_num', ctypes.c_uint32), - ('state', ibv_qp_state), - ('qp_type', ibv_qp_type), - ('mutex', union_c__UA_pthread_mutex_t), - ('cond', union_c__UA_pthread_cond_t), - ('events_completed', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_ibv_comp_channel(Structure): - pass - -struct_ibv_cq._pack_ = 1 # source:False -struct_ibv_cq._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('channel', ctypes.POINTER(struct_ibv_comp_channel)), - ('cq_context', ctypes.POINTER(None)), - ('handle', ctypes.c_uint32), - ('cqe', ctypes.c_int32), - ('mutex', union_c__UA_pthread_mutex_t), - ('cond', union_c__UA_pthread_cond_t), - ('comp_events_completed', ctypes.c_uint32), - ('async_events_completed', ctypes.c_uint32), -] - -struct_ibv_comp_channel._pack_ = 1 # source:False -struct_ibv_comp_channel._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('fd', ctypes.c_int32), - ('refcnt', ctypes.c_int32), -] - -struct_ibv_srq._pack_ = 1 # source:False -struct_ibv_srq._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('srq_context', ctypes.POINTER(None)), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('handle', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('mutex', union_c__UA_pthread_mutex_t), - ('cond', union_c__UA_pthread_cond_t), - ('events_completed', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_ibv_mw_bind_info(Structure): - pass - -class struct_ibv_mr(Structure): - pass - -struct_ibv_mw_bind_info._pack_ = 1 # source:False -struct_ibv_mw_bind_info._fields_ = [ - ('mr', ctypes.POINTER(struct_ibv_mr)), - ('addr', ctypes.c_uint64), - ('length', ctypes.c_uint64), - ('mw_access_flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_ibv_mw_bind._pack_ = 1 # source:False -struct_ibv_mw_bind._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('send_flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('bind_info', struct_ibv_mw_bind_info), -] - -struct_ibv_mr._pack_ = 1 # source:False -struct_ibv_mr._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('addr', ctypes.POINTER(None)), - ('length', ctypes.c_uint64), - ('handle', ctypes.c_uint32), - ('lkey', ctypes.c_uint32), - ('rkey', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_wc_status' -ibv_wc_status__enumvalues = { - 0: 'IBV_WC_SUCCESS', - 1: 'IBV_WC_LOC_LEN_ERR', - 2: 'IBV_WC_LOC_QP_OP_ERR', - 3: 'IBV_WC_LOC_EEC_OP_ERR', - 4: 'IBV_WC_LOC_PROT_ERR', - 5: 'IBV_WC_WR_FLUSH_ERR', - 6: 'IBV_WC_MW_BIND_ERR', - 7: 'IBV_WC_BAD_RESP_ERR', - 8: 'IBV_WC_LOC_ACCESS_ERR', - 9: 'IBV_WC_REM_INV_REQ_ERR', - 10: 'IBV_WC_REM_ACCESS_ERR', - 11: 'IBV_WC_REM_OP_ERR', - 12: 'IBV_WC_RETRY_EXC_ERR', - 13: 'IBV_WC_RNR_RETRY_EXC_ERR', - 14: 'IBV_WC_LOC_RDD_VIOL_ERR', - 15: 'IBV_WC_REM_INV_RD_REQ_ERR', - 16: 'IBV_WC_REM_ABORT_ERR', - 17: 'IBV_WC_INV_EECN_ERR', - 18: 'IBV_WC_INV_EEC_STATE_ERR', - 19: 'IBV_WC_FATAL_ERR', - 20: 'IBV_WC_RESP_TIMEOUT_ERR', - 21: 'IBV_WC_GENERAL_ERR', - 22: 'IBV_WC_TM_ERR', - 23: 'IBV_WC_TM_RNDV_INCOMPLETE', -} -IBV_WC_SUCCESS = 0 -IBV_WC_LOC_LEN_ERR = 1 -IBV_WC_LOC_QP_OP_ERR = 2 -IBV_WC_LOC_EEC_OP_ERR = 3 -IBV_WC_LOC_PROT_ERR = 4 -IBV_WC_WR_FLUSH_ERR = 5 -IBV_WC_MW_BIND_ERR = 6 -IBV_WC_BAD_RESP_ERR = 7 -IBV_WC_LOC_ACCESS_ERR = 8 -IBV_WC_REM_INV_REQ_ERR = 9 -IBV_WC_REM_ACCESS_ERR = 10 -IBV_WC_REM_OP_ERR = 11 -IBV_WC_RETRY_EXC_ERR = 12 -IBV_WC_RNR_RETRY_EXC_ERR = 13 -IBV_WC_LOC_RDD_VIOL_ERR = 14 -IBV_WC_REM_INV_RD_REQ_ERR = 15 -IBV_WC_REM_ABORT_ERR = 16 -IBV_WC_INV_EECN_ERR = 17 -IBV_WC_INV_EEC_STATE_ERR = 18 -IBV_WC_FATAL_ERR = 19 -IBV_WC_RESP_TIMEOUT_ERR = 20 -IBV_WC_GENERAL_ERR = 21 -IBV_WC_TM_ERR = 22 -IBV_WC_TM_RNDV_INCOMPLETE = 23 -ibv_wc_status = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_wc_opcode' -ibv_wc_opcode__enumvalues = { - 0: 'IBV_WC_SEND', - 1: 'IBV_WC_RDMA_WRITE', - 2: 'IBV_WC_RDMA_READ', - 3: 'IBV_WC_COMP_SWAP', - 4: 'IBV_WC_FETCH_ADD', - 5: 'IBV_WC_BIND_MW', - 6: 'IBV_WC_LOCAL_INV', - 7: 'IBV_WC_TSO', - 8: 'IBV_WC_FLUSH', - 9: 'IBV_WC_ATOMIC_WRITE', - 128: 'IBV_WC_RECV', - 129: 'IBV_WC_RECV_RDMA_WITH_IMM', - 130: 'IBV_WC_TM_ADD', - 131: 'IBV_WC_TM_DEL', - 132: 'IBV_WC_TM_SYNC', - 133: 'IBV_WC_TM_RECV', - 134: 'IBV_WC_TM_NO_TAG', - 135: 'IBV_WC_DRIVER1', - 136: 'IBV_WC_DRIVER2', - 137: 'IBV_WC_DRIVER3', -} -IBV_WC_SEND = 0 -IBV_WC_RDMA_WRITE = 1 -IBV_WC_RDMA_READ = 2 -IBV_WC_COMP_SWAP = 3 -IBV_WC_FETCH_ADD = 4 -IBV_WC_BIND_MW = 5 -IBV_WC_LOCAL_INV = 6 -IBV_WC_TSO = 7 -IBV_WC_FLUSH = 8 -IBV_WC_ATOMIC_WRITE = 9 -IBV_WC_RECV = 128 -IBV_WC_RECV_RDMA_WITH_IMM = 129 -IBV_WC_TM_ADD = 130 -IBV_WC_TM_DEL = 131 -IBV_WC_TM_SYNC = 132 -IBV_WC_TM_RECV = 133 -IBV_WC_TM_NO_TAG = 134 -IBV_WC_DRIVER1 = 135 -IBV_WC_DRIVER2 = 136 -IBV_WC_DRIVER3 = 137 -ibv_wc_opcode = ctypes.c_uint32 # enum -class union_ibv_wc_0(Union): - pass - -union_ibv_wc_0._pack_ = 1 # source:False -union_ibv_wc_0._fields_ = [ - ('imm_data', ctypes.c_uint32), - ('invalidated_rkey', ctypes.c_uint32), -] - -struct_ibv_wc._pack_ = 1 # source:False -struct_ibv_wc._anonymous_ = ('_0',) -struct_ibv_wc._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('status', ibv_wc_status), - ('opcode', ibv_wc_opcode), - ('vendor_err', ctypes.c_uint32), - ('byte_len', ctypes.c_uint32), - ('_0', union_ibv_wc_0), - ('qp_num', ctypes.c_uint32), - ('src_qp', ctypes.c_uint32), - ('wc_flags', ctypes.c_uint32), - ('pkey_index', ctypes.c_uint16), - ('slid', ctypes.c_uint16), - ('sl', ctypes.c_ubyte), - ('dlid_path_bits', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -class struct_ibv_sge(Structure): - pass - -struct_ibv_recv_wr._pack_ = 1 # source:False -struct_ibv_recv_wr._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('next', ctypes.POINTER(struct_ibv_recv_wr)), - ('sg_list', ctypes.POINTER(struct_ibv_sge)), - ('num_sge', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_ibv_sge._pack_ = 1 # source:False -struct_ibv_sge._fields_ = [ - ('addr', ctypes.c_uint64), - ('length', ctypes.c_uint32), - ('lkey', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_wr_opcode' -ibv_wr_opcode__enumvalues = { - 0: 'IBV_WR_RDMA_WRITE', - 1: 'IBV_WR_RDMA_WRITE_WITH_IMM', - 2: 'IBV_WR_SEND', - 3: 'IBV_WR_SEND_WITH_IMM', - 4: 'IBV_WR_RDMA_READ', - 5: 'IBV_WR_ATOMIC_CMP_AND_SWP', - 6: 'IBV_WR_ATOMIC_FETCH_AND_ADD', - 7: 'IBV_WR_LOCAL_INV', - 8: 'IBV_WR_BIND_MW', - 9: 'IBV_WR_SEND_WITH_INV', - 10: 'IBV_WR_TSO', - 11: 'IBV_WR_DRIVER1', - 14: 'IBV_WR_FLUSH', - 15: 'IBV_WR_ATOMIC_WRITE', -} -IBV_WR_RDMA_WRITE = 0 -IBV_WR_RDMA_WRITE_WITH_IMM = 1 -IBV_WR_SEND = 2 -IBV_WR_SEND_WITH_IMM = 3 -IBV_WR_RDMA_READ = 4 -IBV_WR_ATOMIC_CMP_AND_SWP = 5 -IBV_WR_ATOMIC_FETCH_AND_ADD = 6 -IBV_WR_LOCAL_INV = 7 -IBV_WR_BIND_MW = 8 -IBV_WR_SEND_WITH_INV = 9 -IBV_WR_TSO = 10 -IBV_WR_DRIVER1 = 11 -IBV_WR_FLUSH = 14 -IBV_WR_ATOMIC_WRITE = 15 -ibv_wr_opcode = ctypes.c_uint32 # enum -class union_ibv_send_wr_0(Union): - pass - -union_ibv_send_wr_0._pack_ = 1 # source:False -union_ibv_send_wr_0._fields_ = [ - ('imm_data', ctypes.c_uint32), - ('invalidate_rkey', ctypes.c_uint32), -] - -class union_ibv_send_wr_wr(Union): - pass - -class struct_ibv_send_wr_1_rdma(Structure): - pass - -struct_ibv_send_wr_1_rdma._pack_ = 1 # source:False -struct_ibv_send_wr_1_rdma._fields_ = [ - ('remote_addr', ctypes.c_uint64), - ('rkey', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_ibv_send_wr_1_atomic(Structure): - pass - -struct_ibv_send_wr_1_atomic._pack_ = 1 # source:False -struct_ibv_send_wr_1_atomic._fields_ = [ - ('remote_addr', ctypes.c_uint64), - ('compare_add', ctypes.c_uint64), - ('swap', ctypes.c_uint64), - ('rkey', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_ibv_send_wr_1_ud(Structure): - pass - -class struct_ibv_ah(Structure): - pass - -struct_ibv_send_wr_1_ud._pack_ = 1 # source:False -struct_ibv_send_wr_1_ud._fields_ = [ - ('ah', ctypes.POINTER(struct_ibv_ah)), - ('remote_qpn', ctypes.c_uint32), - ('remote_qkey', ctypes.c_uint32), -] - -union_ibv_send_wr_wr._pack_ = 1 # source:False -union_ibv_send_wr_wr._fields_ = [ - ('rdma', struct_ibv_send_wr_1_rdma), - ('atomic', struct_ibv_send_wr_1_atomic), - ('ud', struct_ibv_send_wr_1_ud), - ('PADDING_0', ctypes.c_ubyte * 16), -] - -class union_ibv_send_wr_qp_type(Union): - pass - -class struct_ibv_send_wr_2_xrc(Structure): - pass - -struct_ibv_send_wr_2_xrc._pack_ = 1 # source:False -struct_ibv_send_wr_2_xrc._fields_ = [ - ('remote_srqn', ctypes.c_uint32), -] - -union_ibv_send_wr_qp_type._pack_ = 1 # source:False -union_ibv_send_wr_qp_type._fields_ = [ - ('xrc', struct_ibv_send_wr_2_xrc), -] - -class union_ibv_send_wr_3(Union): - pass - -class struct_ibv_send_wr_3_bind_mw(Structure): - pass - -struct_ibv_send_wr_3_bind_mw._pack_ = 1 # source:False -struct_ibv_send_wr_3_bind_mw._fields_ = [ - ('mw', ctypes.POINTER(struct_ibv_mw)), - ('rkey', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('bind_info', struct_ibv_mw_bind_info), -] - -class struct_ibv_send_wr_3_tso(Structure): - pass - -struct_ibv_send_wr_3_tso._pack_ = 1 # source:False -struct_ibv_send_wr_3_tso._fields_ = [ - ('hdr', ctypes.POINTER(None)), - ('hdr_sz', ctypes.c_uint16), - ('mss', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -union_ibv_send_wr_3._pack_ = 1 # source:False -union_ibv_send_wr_3._fields_ = [ - ('bind_mw', struct_ibv_send_wr_3_bind_mw), - ('tso', struct_ibv_send_wr_3_tso), - ('PADDING_0', ctypes.c_ubyte * 32), -] - -struct_ibv_send_wr._pack_ = 1 # source:False -struct_ibv_send_wr._anonymous_ = ('_0', '_1',) -struct_ibv_send_wr._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('next', ctypes.POINTER(struct_ibv_send_wr)), - ('sg_list', ctypes.POINTER(struct_ibv_sge)), - ('num_sge', ctypes.c_int32), - ('opcode', ibv_wr_opcode), - ('send_flags', ctypes.c_uint32), - ('_0', union_ibv_send_wr_0), - ('wr', union_ibv_send_wr_wr), - ('qp_type', union_ibv_send_wr_qp_type), - ('PADDING_0', ctypes.c_ubyte * 4), - ('_1', union_ibv_send_wr_3), -] - -struct_ibv_ah._pack_ = 1 # source:False -struct_ibv_ah._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('handle', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_ibv_query_device_ex_input(Structure): - pass - -struct_ibv_query_device_ex_input._pack_ = 1 # source:False -struct_ibv_query_device_ex_input._fields_ = [ - ('comp_mask', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_odp_transport_cap_bits' -ibv_odp_transport_cap_bits__enumvalues = { - 1: 'IBV_ODP_SUPPORT_SEND', - 2: 'IBV_ODP_SUPPORT_RECV', - 4: 'IBV_ODP_SUPPORT_WRITE', - 8: 'IBV_ODP_SUPPORT_READ', - 16: 'IBV_ODP_SUPPORT_ATOMIC', - 32: 'IBV_ODP_SUPPORT_SRQ_RECV', -} -IBV_ODP_SUPPORT_SEND = 1 -IBV_ODP_SUPPORT_RECV = 2 -IBV_ODP_SUPPORT_WRITE = 4 -IBV_ODP_SUPPORT_READ = 8 -IBV_ODP_SUPPORT_ATOMIC = 16 -IBV_ODP_SUPPORT_SRQ_RECV = 32 -ibv_odp_transport_cap_bits = ctypes.c_uint32 # enum -class struct_ibv_odp_caps(Structure): - pass - -class struct_ibv_odp_caps_per_transport_caps(Structure): - pass - -struct_ibv_odp_caps_per_transport_caps._pack_ = 1 # source:False -struct_ibv_odp_caps_per_transport_caps._fields_ = [ - ('rc_odp_caps', ctypes.c_uint32), - ('uc_odp_caps', ctypes.c_uint32), - ('ud_odp_caps', ctypes.c_uint32), -] - -struct_ibv_odp_caps._pack_ = 1 # source:False -struct_ibv_odp_caps._fields_ = [ - ('general_caps', ctypes.c_uint64), - ('per_transport_caps', struct_ibv_odp_caps_per_transport_caps), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_odp_general_caps' -ibv_odp_general_caps__enumvalues = { - 1: 'IBV_ODP_SUPPORT', - 2: 'IBV_ODP_SUPPORT_IMPLICIT', -} -IBV_ODP_SUPPORT = 1 -IBV_ODP_SUPPORT_IMPLICIT = 2 -ibv_odp_general_caps = ctypes.c_uint32 # enum -class struct_ibv_tso_caps(Structure): - pass - -struct_ibv_tso_caps._pack_ = 1 # source:False -struct_ibv_tso_caps._fields_ = [ - ('max_tso', ctypes.c_uint32), - ('supported_qpts', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_rx_hash_function_flags' -ibv_rx_hash_function_flags__enumvalues = { - 1: 'IBV_RX_HASH_FUNC_TOEPLITZ', -} -IBV_RX_HASH_FUNC_TOEPLITZ = 1 -ibv_rx_hash_function_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_rx_hash_fields' -ibv_rx_hash_fields__enumvalues = { - 1: 'IBV_RX_HASH_SRC_IPV4', - 2: 'IBV_RX_HASH_DST_IPV4', - 4: 'IBV_RX_HASH_SRC_IPV6', - 8: 'IBV_RX_HASH_DST_IPV6', - 16: 'IBV_RX_HASH_SRC_PORT_TCP', - 32: 'IBV_RX_HASH_DST_PORT_TCP', - 64: 'IBV_RX_HASH_SRC_PORT_UDP', - 128: 'IBV_RX_HASH_DST_PORT_UDP', - 256: 'IBV_RX_HASH_IPSEC_SPI', - 2147483648: 'IBV_RX_HASH_INNER', -} -IBV_RX_HASH_SRC_IPV4 = 1 -IBV_RX_HASH_DST_IPV4 = 2 -IBV_RX_HASH_SRC_IPV6 = 4 -IBV_RX_HASH_DST_IPV6 = 8 -IBV_RX_HASH_SRC_PORT_TCP = 16 -IBV_RX_HASH_DST_PORT_TCP = 32 -IBV_RX_HASH_SRC_PORT_UDP = 64 -IBV_RX_HASH_DST_PORT_UDP = 128 -IBV_RX_HASH_IPSEC_SPI = 256 -IBV_RX_HASH_INNER = 2147483648 -ibv_rx_hash_fields = ctypes.c_uint32 # enum -class struct_ibv_rss_caps(Structure): - pass - -struct_ibv_rss_caps._pack_ = 1 # source:False -struct_ibv_rss_caps._fields_ = [ - ('supported_qpts', ctypes.c_uint32), - ('max_rwq_indirection_tables', ctypes.c_uint32), - ('max_rwq_indirection_table_size', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('rx_hash_fields_mask', ctypes.c_uint64), - ('rx_hash_function', ctypes.c_ubyte), - ('PADDING_1', ctypes.c_ubyte * 7), -] - -class struct_ibv_packet_pacing_caps(Structure): - pass - -struct_ibv_packet_pacing_caps._pack_ = 1 # source:False -struct_ibv_packet_pacing_caps._fields_ = [ - ('qp_rate_limit_min', ctypes.c_uint32), - ('qp_rate_limit_max', ctypes.c_uint32), - ('supported_qpts', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_raw_packet_caps' -ibv_raw_packet_caps__enumvalues = { - 1: 'IBV_RAW_PACKET_CAP_CVLAN_STRIPPING', - 2: 'IBV_RAW_PACKET_CAP_SCATTER_FCS', - 4: 'IBV_RAW_PACKET_CAP_IP_CSUM', - 8: 'IBV_RAW_PACKET_CAP_DELAY_DROP', -} -IBV_RAW_PACKET_CAP_CVLAN_STRIPPING = 1 -IBV_RAW_PACKET_CAP_SCATTER_FCS = 2 -IBV_RAW_PACKET_CAP_IP_CSUM = 4 -IBV_RAW_PACKET_CAP_DELAY_DROP = 8 -ibv_raw_packet_caps = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_tm_cap_flags' -ibv_tm_cap_flags__enumvalues = { - 1: 'IBV_TM_CAP_RC', -} -IBV_TM_CAP_RC = 1 -ibv_tm_cap_flags = ctypes.c_uint32 # enum -class struct_ibv_tm_caps(Structure): - pass - -struct_ibv_tm_caps._pack_ = 1 # source:False -struct_ibv_tm_caps._fields_ = [ - ('max_rndv_hdr_size', ctypes.c_uint32), - ('max_num_tags', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('max_ops', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), -] - -class struct_ibv_cq_moderation_caps(Structure): - pass - -struct_ibv_cq_moderation_caps._pack_ = 1 # source:False -struct_ibv_cq_moderation_caps._fields_ = [ - ('max_cq_count', ctypes.c_uint16), - ('max_cq_period', ctypes.c_uint16), -] - - -# values for enumeration 'ibv_pci_atomic_op_size' -ibv_pci_atomic_op_size__enumvalues = { - 1: 'IBV_PCI_ATOMIC_OPERATION_4_BYTE_SIZE_SUP', - 2: 'IBV_PCI_ATOMIC_OPERATION_8_BYTE_SIZE_SUP', - 4: 'IBV_PCI_ATOMIC_OPERATION_16_BYTE_SIZE_SUP', -} -IBV_PCI_ATOMIC_OPERATION_4_BYTE_SIZE_SUP = 1 -IBV_PCI_ATOMIC_OPERATION_8_BYTE_SIZE_SUP = 2 -IBV_PCI_ATOMIC_OPERATION_16_BYTE_SIZE_SUP = 4 -ibv_pci_atomic_op_size = ctypes.c_uint32 # enum -class struct_ibv_pci_atomic_caps(Structure): - pass - -struct_ibv_pci_atomic_caps._pack_ = 1 # source:False -struct_ibv_pci_atomic_caps._fields_ = [ - ('fetch_add', ctypes.c_uint16), - ('swap', ctypes.c_uint16), - ('compare_swap', ctypes.c_uint16), -] - -class struct_ibv_device_attr_ex(Structure): - pass - -struct_ibv_device_attr_ex._pack_ = 1 # source:False -struct_ibv_device_attr_ex._fields_ = [ - ('orig_attr', struct_ibv_device_attr), - ('comp_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('odp_caps', struct_ibv_odp_caps), - ('completion_timestamp_mask', ctypes.c_uint64), - ('hca_core_clock', ctypes.c_uint64), - ('device_cap_flags_ex', ctypes.c_uint64), - ('tso_caps', struct_ibv_tso_caps), - ('rss_caps', struct_ibv_rss_caps), - ('max_wq_type_rq', ctypes.c_uint32), - ('packet_pacing_caps', struct_ibv_packet_pacing_caps), - ('raw_packet_caps', ctypes.c_uint32), - ('tm_caps', struct_ibv_tm_caps), - ('cq_mod_caps', struct_ibv_cq_moderation_caps), - ('PADDING_1', ctypes.c_ubyte * 4), - ('max_dm_size', ctypes.c_uint64), - ('pci_atomic_caps', struct_ibv_pci_atomic_caps), - ('PADDING_2', ctypes.c_ubyte * 2), - ('xrc_odp_caps', ctypes.c_uint32), - ('phys_port_cnt_ex', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_mtu' -ibv_mtu__enumvalues = { - 1: 'IBV_MTU_256', - 2: 'IBV_MTU_512', - 3: 'IBV_MTU_1024', - 4: 'IBV_MTU_2048', - 5: 'IBV_MTU_4096', -} -IBV_MTU_256 = 1 -IBV_MTU_512 = 2 -IBV_MTU_1024 = 3 -IBV_MTU_2048 = 4 -IBV_MTU_4096 = 5 -ibv_mtu = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_port_state' -ibv_port_state__enumvalues = { - 0: 'IBV_PORT_NOP', - 1: 'IBV_PORT_DOWN', - 2: 'IBV_PORT_INIT', - 3: 'IBV_PORT_ARMED', - 4: 'IBV_PORT_ACTIVE', - 5: 'IBV_PORT_ACTIVE_DEFER', -} -IBV_PORT_NOP = 0 -IBV_PORT_DOWN = 1 -IBV_PORT_INIT = 2 -IBV_PORT_ARMED = 3 -IBV_PORT_ACTIVE = 4 -IBV_PORT_ACTIVE_DEFER = 5 -ibv_port_state = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_IBV_LINK_LAYER_UNSPECIFIED' -c__Ea_IBV_LINK_LAYER_UNSPECIFIED__enumvalues = { - 0: 'IBV_LINK_LAYER_UNSPECIFIED', - 1: 'IBV_LINK_LAYER_INFINIBAND', - 2: 'IBV_LINK_LAYER_ETHERNET', -} -IBV_LINK_LAYER_UNSPECIFIED = 0 -IBV_LINK_LAYER_INFINIBAND = 1 -IBV_LINK_LAYER_ETHERNET = 2 -c__Ea_IBV_LINK_LAYER_UNSPECIFIED = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_port_cap_flags' -ibv_port_cap_flags__enumvalues = { - 2: 'IBV_PORT_SM', - 4: 'IBV_PORT_NOTICE_SUP', - 8: 'IBV_PORT_TRAP_SUP', - 16: 'IBV_PORT_OPT_IPD_SUP', - 32: 'IBV_PORT_AUTO_MIGR_SUP', - 64: 'IBV_PORT_SL_MAP_SUP', - 128: 'IBV_PORT_MKEY_NVRAM', - 256: 'IBV_PORT_PKEY_NVRAM', - 512: 'IBV_PORT_LED_INFO_SUP', - 2048: 'IBV_PORT_SYS_IMAGE_GUID_SUP', - 4096: 'IBV_PORT_PKEY_SW_EXT_PORT_TRAP_SUP', - 16384: 'IBV_PORT_EXTENDED_SPEEDS_SUP', - 32768: 'IBV_PORT_CAP_MASK2_SUP', - 65536: 'IBV_PORT_CM_SUP', - 131072: 'IBV_PORT_SNMP_TUNNEL_SUP', - 262144: 'IBV_PORT_REINIT_SUP', - 524288: 'IBV_PORT_DEVICE_MGMT_SUP', - 1048576: 'IBV_PORT_VENDOR_CLASS_SUP', - 2097152: 'IBV_PORT_DR_NOTICE_SUP', - 4194304: 'IBV_PORT_CAP_MASK_NOTICE_SUP', - 8388608: 'IBV_PORT_BOOT_MGMT_SUP', - 16777216: 'IBV_PORT_LINK_LATENCY_SUP', - 33554432: 'IBV_PORT_CLIENT_REG_SUP', - 67108864: 'IBV_PORT_IP_BASED_GIDS', -} -IBV_PORT_SM = 2 -IBV_PORT_NOTICE_SUP = 4 -IBV_PORT_TRAP_SUP = 8 -IBV_PORT_OPT_IPD_SUP = 16 -IBV_PORT_AUTO_MIGR_SUP = 32 -IBV_PORT_SL_MAP_SUP = 64 -IBV_PORT_MKEY_NVRAM = 128 -IBV_PORT_PKEY_NVRAM = 256 -IBV_PORT_LED_INFO_SUP = 512 -IBV_PORT_SYS_IMAGE_GUID_SUP = 2048 -IBV_PORT_PKEY_SW_EXT_PORT_TRAP_SUP = 4096 -IBV_PORT_EXTENDED_SPEEDS_SUP = 16384 -IBV_PORT_CAP_MASK2_SUP = 32768 -IBV_PORT_CM_SUP = 65536 -IBV_PORT_SNMP_TUNNEL_SUP = 131072 -IBV_PORT_REINIT_SUP = 262144 -IBV_PORT_DEVICE_MGMT_SUP = 524288 -IBV_PORT_VENDOR_CLASS_SUP = 1048576 -IBV_PORT_DR_NOTICE_SUP = 2097152 -IBV_PORT_CAP_MASK_NOTICE_SUP = 4194304 -IBV_PORT_BOOT_MGMT_SUP = 8388608 -IBV_PORT_LINK_LATENCY_SUP = 16777216 -IBV_PORT_CLIENT_REG_SUP = 33554432 -IBV_PORT_IP_BASED_GIDS = 67108864 -ibv_port_cap_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_port_cap_flags2' -ibv_port_cap_flags2__enumvalues = { - 1: 'IBV_PORT_SET_NODE_DESC_SUP', - 2: 'IBV_PORT_INFO_EXT_SUP', - 4: 'IBV_PORT_VIRT_SUP', - 8: 'IBV_PORT_SWITCH_PORT_STATE_TABLE_SUP', - 16: 'IBV_PORT_LINK_WIDTH_2X_SUP', - 32: 'IBV_PORT_LINK_SPEED_HDR_SUP', - 1024: 'IBV_PORT_LINK_SPEED_NDR_SUP', - 4096: 'IBV_PORT_LINK_SPEED_XDR_SUP', -} -IBV_PORT_SET_NODE_DESC_SUP = 1 -IBV_PORT_INFO_EXT_SUP = 2 -IBV_PORT_VIRT_SUP = 4 -IBV_PORT_SWITCH_PORT_STATE_TABLE_SUP = 8 -IBV_PORT_LINK_WIDTH_2X_SUP = 16 -IBV_PORT_LINK_SPEED_HDR_SUP = 32 -IBV_PORT_LINK_SPEED_NDR_SUP = 1024 -IBV_PORT_LINK_SPEED_XDR_SUP = 4096 -ibv_port_cap_flags2 = ctypes.c_uint32 # enum -class struct_ibv_port_attr(Structure): - pass - -struct_ibv_port_attr._pack_ = 1 # source:False -struct_ibv_port_attr._fields_ = [ - ('state', ibv_port_state), - ('max_mtu', ibv_mtu), - ('active_mtu', ibv_mtu), - ('gid_tbl_len', ctypes.c_int32), - ('port_cap_flags', ctypes.c_uint32), - ('max_msg_sz', ctypes.c_uint32), - ('bad_pkey_cntr', ctypes.c_uint32), - ('qkey_viol_cntr', ctypes.c_uint32), - ('pkey_tbl_len', ctypes.c_uint16), - ('lid', ctypes.c_uint16), - ('sm_lid', ctypes.c_uint16), - ('lmc', ctypes.c_ubyte), - ('max_vl_num', ctypes.c_ubyte), - ('sm_sl', ctypes.c_ubyte), - ('subnet_timeout', ctypes.c_ubyte), - ('init_type_reply', ctypes.c_ubyte), - ('active_width', ctypes.c_ubyte), - ('active_speed', ctypes.c_ubyte), - ('phys_state', ctypes.c_ubyte), - ('link_layer', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), - ('port_cap_flags2', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('active_speed_ex', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_event_type' -ibv_event_type__enumvalues = { - 0: 'IBV_EVENT_CQ_ERR', - 1: 'IBV_EVENT_QP_FATAL', - 2: 'IBV_EVENT_QP_REQ_ERR', - 3: 'IBV_EVENT_QP_ACCESS_ERR', - 4: 'IBV_EVENT_COMM_EST', - 5: 'IBV_EVENT_SQ_DRAINED', - 6: 'IBV_EVENT_PATH_MIG', - 7: 'IBV_EVENT_PATH_MIG_ERR', - 8: 'IBV_EVENT_DEVICE_FATAL', - 9: 'IBV_EVENT_PORT_ACTIVE', - 10: 'IBV_EVENT_PORT_ERR', - 11: 'IBV_EVENT_LID_CHANGE', - 12: 'IBV_EVENT_PKEY_CHANGE', - 13: 'IBV_EVENT_SM_CHANGE', - 14: 'IBV_EVENT_SRQ_ERR', - 15: 'IBV_EVENT_SRQ_LIMIT_REACHED', - 16: 'IBV_EVENT_QP_LAST_WQE_REACHED', - 17: 'IBV_EVENT_CLIENT_REREGISTER', - 18: 'IBV_EVENT_GID_CHANGE', - 19: 'IBV_EVENT_WQ_FATAL', -} -IBV_EVENT_CQ_ERR = 0 -IBV_EVENT_QP_FATAL = 1 -IBV_EVENT_QP_REQ_ERR = 2 -IBV_EVENT_QP_ACCESS_ERR = 3 -IBV_EVENT_COMM_EST = 4 -IBV_EVENT_SQ_DRAINED = 5 -IBV_EVENT_PATH_MIG = 6 -IBV_EVENT_PATH_MIG_ERR = 7 -IBV_EVENT_DEVICE_FATAL = 8 -IBV_EVENT_PORT_ACTIVE = 9 -IBV_EVENT_PORT_ERR = 10 -IBV_EVENT_LID_CHANGE = 11 -IBV_EVENT_PKEY_CHANGE = 12 -IBV_EVENT_SM_CHANGE = 13 -IBV_EVENT_SRQ_ERR = 14 -IBV_EVENT_SRQ_LIMIT_REACHED = 15 -IBV_EVENT_QP_LAST_WQE_REACHED = 16 -IBV_EVENT_CLIENT_REREGISTER = 17 -IBV_EVENT_GID_CHANGE = 18 -IBV_EVENT_WQ_FATAL = 19 -ibv_event_type = ctypes.c_uint32 # enum -class struct_ibv_async_event(Structure): - pass - -class union_ibv_async_event_element(Union): - pass - -class struct_ibv_wq(Structure): - pass - -union_ibv_async_event_element._pack_ = 1 # source:False -union_ibv_async_event_element._fields_ = [ - ('cq', ctypes.POINTER(struct_ibv_cq)), - ('qp', ctypes.POINTER(struct_ibv_qp)), - ('srq', ctypes.POINTER(struct_ibv_srq)), - ('wq', ctypes.POINTER(struct_ibv_wq)), - ('port_num', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -struct_ibv_async_event._pack_ = 1 # source:False -struct_ibv_async_event._fields_ = [ - ('element', union_ibv_async_event_element), - ('event_type', ibv_event_type), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_wq_state' -ibv_wq_state__enumvalues = { - 0: 'IBV_WQS_RESET', - 1: 'IBV_WQS_RDY', - 2: 'IBV_WQS_ERR', - 3: 'IBV_WQS_UNKNOWN', -} -IBV_WQS_RESET = 0 -IBV_WQS_RDY = 1 -IBV_WQS_ERR = 2 -IBV_WQS_UNKNOWN = 3 -ibv_wq_state = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_wq_type' -ibv_wq_type__enumvalues = { - 0: 'IBV_WQT_RQ', -} -IBV_WQT_RQ = 0 -ibv_wq_type = ctypes.c_uint32 # enum -struct_ibv_wq._pack_ = 1 # source:False -struct_ibv_wq._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('wq_context', ctypes.POINTER(None)), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('cq', ctypes.POINTER(struct_ibv_cq)), - ('wq_num', ctypes.c_uint32), - ('handle', ctypes.c_uint32), - ('state', ibv_wq_state), - ('wq_type', ibv_wq_type), - ('post_recv', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr)))), - ('mutex', union_c__UA_pthread_mutex_t), - ('cond', union_c__UA_pthread_cond_t), - ('events_completed', ctypes.c_uint32), - ('comp_mask', ctypes.c_uint32), -] - -try: - ibv_wc_status_str = _libraries['libibverbs'].ibv_wc_status_str - ibv_wc_status_str.restype = ctypes.POINTER(ctypes.c_char) - ibv_wc_status_str.argtypes = [ibv_wc_status] -except AttributeError: - pass - -# values for enumeration 'c__Ea_IBV_WC_IP_CSUM_OK_SHIFT' -c__Ea_IBV_WC_IP_CSUM_OK_SHIFT__enumvalues = { - 2: 'IBV_WC_IP_CSUM_OK_SHIFT', -} -IBV_WC_IP_CSUM_OK_SHIFT = 2 -c__Ea_IBV_WC_IP_CSUM_OK_SHIFT = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_create_cq_wc_flags' -ibv_create_cq_wc_flags__enumvalues = { - 1: 'IBV_WC_EX_WITH_BYTE_LEN', - 2: 'IBV_WC_EX_WITH_IMM', - 4: 'IBV_WC_EX_WITH_QP_NUM', - 8: 'IBV_WC_EX_WITH_SRC_QP', - 16: 'IBV_WC_EX_WITH_SLID', - 32: 'IBV_WC_EX_WITH_SL', - 64: 'IBV_WC_EX_WITH_DLID_PATH_BITS', - 128: 'IBV_WC_EX_WITH_COMPLETION_TIMESTAMP', - 256: 'IBV_WC_EX_WITH_CVLAN', - 512: 'IBV_WC_EX_WITH_FLOW_TAG', - 1024: 'IBV_WC_EX_WITH_TM_INFO', - 2048: 'IBV_WC_EX_WITH_COMPLETION_TIMESTAMP_WALLCLOCK', -} -IBV_WC_EX_WITH_BYTE_LEN = 1 -IBV_WC_EX_WITH_IMM = 2 -IBV_WC_EX_WITH_QP_NUM = 4 -IBV_WC_EX_WITH_SRC_QP = 8 -IBV_WC_EX_WITH_SLID = 16 -IBV_WC_EX_WITH_SL = 32 -IBV_WC_EX_WITH_DLID_PATH_BITS = 64 -IBV_WC_EX_WITH_COMPLETION_TIMESTAMP = 128 -IBV_WC_EX_WITH_CVLAN = 256 -IBV_WC_EX_WITH_FLOW_TAG = 512 -IBV_WC_EX_WITH_TM_INFO = 1024 -IBV_WC_EX_WITH_COMPLETION_TIMESTAMP_WALLCLOCK = 2048 -ibv_create_cq_wc_flags = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_IBV_WC_STANDARD_FLAGS' -c__Ea_IBV_WC_STANDARD_FLAGS__enumvalues = { - 127: 'IBV_WC_STANDARD_FLAGS', -} -IBV_WC_STANDARD_FLAGS = 127 -c__Ea_IBV_WC_STANDARD_FLAGS = ctypes.c_uint32 # enum - -# values for enumeration 'c__Ea_IBV_CREATE_CQ_SUP_WC_FLAGS' -c__Ea_IBV_CREATE_CQ_SUP_WC_FLAGS__enumvalues = { - 4095: 'IBV_CREATE_CQ_SUP_WC_FLAGS', -} -IBV_CREATE_CQ_SUP_WC_FLAGS = 4095 -c__Ea_IBV_CREATE_CQ_SUP_WC_FLAGS = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_wc_flags' -ibv_wc_flags__enumvalues = { - 1: 'IBV_WC_GRH', - 2: 'IBV_WC_WITH_IMM', - 4: 'IBV_WC_IP_CSUM_OK', - 8: 'IBV_WC_WITH_INV', - 16: 'IBV_WC_TM_SYNC_REQ', - 32: 'IBV_WC_TM_MATCH', - 64: 'IBV_WC_TM_DATA_VALID', -} -IBV_WC_GRH = 1 -IBV_WC_WITH_IMM = 2 -IBV_WC_IP_CSUM_OK = 4 -IBV_WC_WITH_INV = 8 -IBV_WC_TM_SYNC_REQ = 16 -IBV_WC_TM_MATCH = 32 -IBV_WC_TM_DATA_VALID = 64 -ibv_wc_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_access_flags' -ibv_access_flags__enumvalues = { - 1: 'IBV_ACCESS_LOCAL_WRITE', - 2: 'IBV_ACCESS_REMOTE_WRITE', - 4: 'IBV_ACCESS_REMOTE_READ', - 8: 'IBV_ACCESS_REMOTE_ATOMIC', - 16: 'IBV_ACCESS_MW_BIND', - 32: 'IBV_ACCESS_ZERO_BASED', - 64: 'IBV_ACCESS_ON_DEMAND', - 128: 'IBV_ACCESS_HUGETLB', - 256: 'IBV_ACCESS_FLUSH_GLOBAL', - 512: 'IBV_ACCESS_FLUSH_PERSISTENT', - 1048576: 'IBV_ACCESS_RELAXED_ORDERING', -} -IBV_ACCESS_LOCAL_WRITE = 1 -IBV_ACCESS_REMOTE_WRITE = 2 -IBV_ACCESS_REMOTE_READ = 4 -IBV_ACCESS_REMOTE_ATOMIC = 8 -IBV_ACCESS_MW_BIND = 16 -IBV_ACCESS_ZERO_BASED = 32 -IBV_ACCESS_ON_DEMAND = 64 -IBV_ACCESS_HUGETLB = 128 -IBV_ACCESS_FLUSH_GLOBAL = 256 -IBV_ACCESS_FLUSH_PERSISTENT = 512 -IBV_ACCESS_RELAXED_ORDERING = 1048576 -ibv_access_flags = ctypes.c_uint32 # enum -class struct_ibv_td_init_attr(Structure): - pass - -struct_ibv_td_init_attr._pack_ = 1 # source:False -struct_ibv_td_init_attr._fields_ = [ - ('comp_mask', ctypes.c_uint32), -] - -class struct_ibv_td(Structure): - pass - -struct_ibv_td._pack_ = 1 # source:False -struct_ibv_td._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), -] - - -# values for enumeration 'ibv_xrcd_init_attr_mask' -ibv_xrcd_init_attr_mask__enumvalues = { - 1: 'IBV_XRCD_INIT_ATTR_FD', - 2: 'IBV_XRCD_INIT_ATTR_OFLAGS', - 4: 'IBV_XRCD_INIT_ATTR_RESERVED', -} -IBV_XRCD_INIT_ATTR_FD = 1 -IBV_XRCD_INIT_ATTR_OFLAGS = 2 -IBV_XRCD_INIT_ATTR_RESERVED = 4 -ibv_xrcd_init_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_xrcd_init_attr(Structure): - pass - -struct_ibv_xrcd_init_attr._pack_ = 1 # source:False -struct_ibv_xrcd_init_attr._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('fd', ctypes.c_int32), - ('oflags', ctypes.c_int32), -] - -class struct_ibv_xrcd(Structure): - pass - -struct_ibv_xrcd._pack_ = 1 # source:False -struct_ibv_xrcd._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), -] - - -# values for enumeration 'ibv_rereg_mr_flags' -ibv_rereg_mr_flags__enumvalues = { - 1: 'IBV_REREG_MR_CHANGE_TRANSLATION', - 2: 'IBV_REREG_MR_CHANGE_PD', - 4: 'IBV_REREG_MR_CHANGE_ACCESS', - 7: 'IBV_REREG_MR_FLAGS_SUPPORTED', -} -IBV_REREG_MR_CHANGE_TRANSLATION = 1 -IBV_REREG_MR_CHANGE_PD = 2 -IBV_REREG_MR_CHANGE_ACCESS = 4 -IBV_REREG_MR_FLAGS_SUPPORTED = 7 -ibv_rereg_mr_flags = ctypes.c_uint32 # enum -class struct_ibv_global_route(Structure): - pass - -struct_ibv_global_route._pack_ = 1 # source:False -struct_ibv_global_route._fields_ = [ - ('dgid', union_ibv_gid), - ('flow_label', ctypes.c_uint32), - ('sgid_index', ctypes.c_ubyte), - ('hop_limit', ctypes.c_ubyte), - ('traffic_class', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -class struct_ibv_grh(Structure): - pass - -struct_ibv_grh._pack_ = 1 # source:False -struct_ibv_grh._fields_ = [ - ('version_tclass_flow', ctypes.c_uint32), - ('paylen', ctypes.c_uint16), - ('next_hdr', ctypes.c_ubyte), - ('hop_limit', ctypes.c_ubyte), - ('sgid', union_ibv_gid), - ('dgid', union_ibv_gid), -] - - -# values for enumeration 'ibv_rate' -ibv_rate__enumvalues = { - 0: 'IBV_RATE_MAX', - 2: 'IBV_RATE_2_5_GBPS', - 5: 'IBV_RATE_5_GBPS', - 3: 'IBV_RATE_10_GBPS', - 6: 'IBV_RATE_20_GBPS', - 4: 'IBV_RATE_30_GBPS', - 7: 'IBV_RATE_40_GBPS', - 8: 'IBV_RATE_60_GBPS', - 9: 'IBV_RATE_80_GBPS', - 10: 'IBV_RATE_120_GBPS', - 11: 'IBV_RATE_14_GBPS', - 12: 'IBV_RATE_56_GBPS', - 13: 'IBV_RATE_112_GBPS', - 14: 'IBV_RATE_168_GBPS', - 15: 'IBV_RATE_25_GBPS', - 16: 'IBV_RATE_100_GBPS', - 17: 'IBV_RATE_200_GBPS', - 18: 'IBV_RATE_300_GBPS', - 19: 'IBV_RATE_28_GBPS', - 20: 'IBV_RATE_50_GBPS', - 21: 'IBV_RATE_400_GBPS', - 22: 'IBV_RATE_600_GBPS', - 23: 'IBV_RATE_800_GBPS', - 24: 'IBV_RATE_1200_GBPS', -} -IBV_RATE_MAX = 0 -IBV_RATE_2_5_GBPS = 2 -IBV_RATE_5_GBPS = 5 -IBV_RATE_10_GBPS = 3 -IBV_RATE_20_GBPS = 6 -IBV_RATE_30_GBPS = 4 -IBV_RATE_40_GBPS = 7 -IBV_RATE_60_GBPS = 8 -IBV_RATE_80_GBPS = 9 -IBV_RATE_120_GBPS = 10 -IBV_RATE_14_GBPS = 11 -IBV_RATE_56_GBPS = 12 -IBV_RATE_112_GBPS = 13 -IBV_RATE_168_GBPS = 14 -IBV_RATE_25_GBPS = 15 -IBV_RATE_100_GBPS = 16 -IBV_RATE_200_GBPS = 17 -IBV_RATE_300_GBPS = 18 -IBV_RATE_28_GBPS = 19 -IBV_RATE_50_GBPS = 20 -IBV_RATE_400_GBPS = 21 -IBV_RATE_600_GBPS = 22 -IBV_RATE_800_GBPS = 23 -IBV_RATE_1200_GBPS = 24 -ibv_rate = ctypes.c_uint32 # enum -try: - ibv_rate_to_mult = _libraries['libibverbs'].ibv_rate_to_mult - ibv_rate_to_mult.restype = ctypes.c_int32 - ibv_rate_to_mult.argtypes = [ibv_rate] -except AttributeError: - pass -try: - mult_to_ibv_rate = _libraries['libibverbs'].mult_to_ibv_rate - mult_to_ibv_rate.restype = ibv_rate - mult_to_ibv_rate.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - ibv_rate_to_mbps = _libraries['libibverbs'].ibv_rate_to_mbps - ibv_rate_to_mbps.restype = ctypes.c_int32 - ibv_rate_to_mbps.argtypes = [ibv_rate] -except AttributeError: - pass -try: - mbps_to_ibv_rate = _libraries['libibverbs'].mbps_to_ibv_rate - mbps_to_ibv_rate.restype = ibv_rate - mbps_to_ibv_rate.argtypes = [ctypes.c_int32] -except AttributeError: - pass -class struct_ibv_ah_attr(Structure): - pass - -struct_ibv_ah_attr._pack_ = 1 # source:False -struct_ibv_ah_attr._fields_ = [ - ('grh', struct_ibv_global_route), - ('dlid', ctypes.c_uint16), - ('sl', ctypes.c_ubyte), - ('src_path_bits', ctypes.c_ubyte), - ('static_rate', ctypes.c_ubyte), - ('is_global', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - - -# values for enumeration 'ibv_srq_attr_mask' -ibv_srq_attr_mask__enumvalues = { - 1: 'IBV_SRQ_MAX_WR', - 2: 'IBV_SRQ_LIMIT', -} -IBV_SRQ_MAX_WR = 1 -IBV_SRQ_LIMIT = 2 -ibv_srq_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_srq_attr(Structure): - pass - -struct_ibv_srq_attr._pack_ = 1 # source:False -struct_ibv_srq_attr._fields_ = [ - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('srq_limit', ctypes.c_uint32), -] - -class struct_ibv_srq_init_attr(Structure): - pass - -struct_ibv_srq_init_attr._pack_ = 1 # source:False -struct_ibv_srq_init_attr._fields_ = [ - ('srq_context', ctypes.POINTER(None)), - ('attr', struct_ibv_srq_attr), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_srq_type' -ibv_srq_type__enumvalues = { - 0: 'IBV_SRQT_BASIC', - 1: 'IBV_SRQT_XRC', - 2: 'IBV_SRQT_TM', -} -IBV_SRQT_BASIC = 0 -IBV_SRQT_XRC = 1 -IBV_SRQT_TM = 2 -ibv_srq_type = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_srq_init_attr_mask' -ibv_srq_init_attr_mask__enumvalues = { - 1: 'IBV_SRQ_INIT_ATTR_TYPE', - 2: 'IBV_SRQ_INIT_ATTR_PD', - 4: 'IBV_SRQ_INIT_ATTR_XRCD', - 8: 'IBV_SRQ_INIT_ATTR_CQ', - 16: 'IBV_SRQ_INIT_ATTR_TM', - 32: 'IBV_SRQ_INIT_ATTR_RESERVED', -} -IBV_SRQ_INIT_ATTR_TYPE = 1 -IBV_SRQ_INIT_ATTR_PD = 2 -IBV_SRQ_INIT_ATTR_XRCD = 4 -IBV_SRQ_INIT_ATTR_CQ = 8 -IBV_SRQ_INIT_ATTR_TM = 16 -IBV_SRQ_INIT_ATTR_RESERVED = 32 -ibv_srq_init_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_tm_cap(Structure): - pass - -struct_ibv_tm_cap._pack_ = 1 # source:False -struct_ibv_tm_cap._fields_ = [ - ('max_num_tags', ctypes.c_uint32), - ('max_ops', ctypes.c_uint32), -] - -class struct_ibv_srq_init_attr_ex(Structure): - pass - -struct_ibv_srq_init_attr_ex._pack_ = 1 # source:False -struct_ibv_srq_init_attr_ex._fields_ = [ - ('srq_context', ctypes.POINTER(None)), - ('attr', struct_ibv_srq_attr), - ('comp_mask', ctypes.c_uint32), - ('srq_type', ibv_srq_type), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('xrcd', ctypes.POINTER(struct_ibv_xrcd)), - ('cq', ctypes.POINTER(struct_ibv_cq)), - ('tm_cap', struct_ibv_tm_cap), -] - - -# values for enumeration 'ibv_wq_init_attr_mask' -ibv_wq_init_attr_mask__enumvalues = { - 1: 'IBV_WQ_INIT_ATTR_FLAGS', - 2: 'IBV_WQ_INIT_ATTR_RESERVED', -} -IBV_WQ_INIT_ATTR_FLAGS = 1 -IBV_WQ_INIT_ATTR_RESERVED = 2 -ibv_wq_init_attr_mask = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_wq_flags' -ibv_wq_flags__enumvalues = { - 1: 'IBV_WQ_FLAGS_CVLAN_STRIPPING', - 2: 'IBV_WQ_FLAGS_SCATTER_FCS', - 4: 'IBV_WQ_FLAGS_DELAY_DROP', - 8: 'IBV_WQ_FLAGS_PCI_WRITE_END_PADDING', - 16: 'IBV_WQ_FLAGS_RESERVED', -} -IBV_WQ_FLAGS_CVLAN_STRIPPING = 1 -IBV_WQ_FLAGS_SCATTER_FCS = 2 -IBV_WQ_FLAGS_DELAY_DROP = 4 -IBV_WQ_FLAGS_PCI_WRITE_END_PADDING = 8 -IBV_WQ_FLAGS_RESERVED = 16 -ibv_wq_flags = ctypes.c_uint32 # enum -class struct_ibv_wq_init_attr(Structure): - pass - -struct_ibv_wq_init_attr._pack_ = 1 # source:False -struct_ibv_wq_init_attr._fields_ = [ - ('wq_context', ctypes.POINTER(None)), - ('wq_type', ibv_wq_type), - ('max_wr', ctypes.c_uint32), - ('max_sge', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('cq', ctypes.POINTER(struct_ibv_cq)), - ('comp_mask', ctypes.c_uint32), - ('create_flags', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_wq_attr_mask' -ibv_wq_attr_mask__enumvalues = { - 1: 'IBV_WQ_ATTR_STATE', - 2: 'IBV_WQ_ATTR_CURR_STATE', - 4: 'IBV_WQ_ATTR_FLAGS', - 8: 'IBV_WQ_ATTR_RESERVED', -} -IBV_WQ_ATTR_STATE = 1 -IBV_WQ_ATTR_CURR_STATE = 2 -IBV_WQ_ATTR_FLAGS = 4 -IBV_WQ_ATTR_RESERVED = 8 -ibv_wq_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_wq_attr(Structure): - pass - -struct_ibv_wq_attr._pack_ = 1 # source:False -struct_ibv_wq_attr._fields_ = [ - ('attr_mask', ctypes.c_uint32), - ('wq_state', ibv_wq_state), - ('curr_wq_state', ibv_wq_state), - ('flags', ctypes.c_uint32), - ('flags_mask', ctypes.c_uint32), -] - -class struct_ibv_rwq_ind_table(Structure): - pass - -struct_ibv_rwq_ind_table._pack_ = 1 # source:False -struct_ibv_rwq_ind_table._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('ind_tbl_handle', ctypes.c_int32), - ('ind_tbl_num', ctypes.c_int32), - ('comp_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_ind_table_init_attr_mask' -ibv_ind_table_init_attr_mask__enumvalues = { - 1: 'IBV_CREATE_IND_TABLE_RESERVED', -} -IBV_CREATE_IND_TABLE_RESERVED = 1 -ibv_ind_table_init_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_rwq_ind_table_init_attr(Structure): - pass - -struct_ibv_rwq_ind_table_init_attr._pack_ = 1 # source:False -struct_ibv_rwq_ind_table_init_attr._fields_ = [ - ('log_ind_tbl_size', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('ind_tbl', ctypes.POINTER(ctypes.POINTER(struct_ibv_wq))), - ('comp_mask', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_ibv_qp_cap(Structure): - pass - -struct_ibv_qp_cap._pack_ = 1 # source:False -struct_ibv_qp_cap._fields_ = [ - ('max_send_wr', ctypes.c_uint32), - ('max_recv_wr', ctypes.c_uint32), - ('max_send_sge', ctypes.c_uint32), - ('max_recv_sge', ctypes.c_uint32), - ('max_inline_data', ctypes.c_uint32), -] - -class struct_ibv_qp_init_attr(Structure): - pass - -struct_ibv_qp_init_attr._pack_ = 1 # source:False -struct_ibv_qp_init_attr._fields_ = [ - ('qp_context', ctypes.POINTER(None)), - ('send_cq', ctypes.POINTER(struct_ibv_cq)), - ('recv_cq', ctypes.POINTER(struct_ibv_cq)), - ('srq', ctypes.POINTER(struct_ibv_srq)), - ('cap', struct_ibv_qp_cap), - ('qp_type', ibv_qp_type), - ('sq_sig_all', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_qp_init_attr_mask' -ibv_qp_init_attr_mask__enumvalues = { - 1: 'IBV_QP_INIT_ATTR_PD', - 2: 'IBV_QP_INIT_ATTR_XRCD', - 4: 'IBV_QP_INIT_ATTR_CREATE_FLAGS', - 8: 'IBV_QP_INIT_ATTR_MAX_TSO_HEADER', - 16: 'IBV_QP_INIT_ATTR_IND_TABLE', - 32: 'IBV_QP_INIT_ATTR_RX_HASH', - 64: 'IBV_QP_INIT_ATTR_SEND_OPS_FLAGS', -} -IBV_QP_INIT_ATTR_PD = 1 -IBV_QP_INIT_ATTR_XRCD = 2 -IBV_QP_INIT_ATTR_CREATE_FLAGS = 4 -IBV_QP_INIT_ATTR_MAX_TSO_HEADER = 8 -IBV_QP_INIT_ATTR_IND_TABLE = 16 -IBV_QP_INIT_ATTR_RX_HASH = 32 -IBV_QP_INIT_ATTR_SEND_OPS_FLAGS = 64 -ibv_qp_init_attr_mask = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_qp_create_flags' -ibv_qp_create_flags__enumvalues = { - 2: 'IBV_QP_CREATE_BLOCK_SELF_MCAST_LB', - 256: 'IBV_QP_CREATE_SCATTER_FCS', - 512: 'IBV_QP_CREATE_CVLAN_STRIPPING', - 1024: 'IBV_QP_CREATE_SOURCE_QPN', - 2048: 'IBV_QP_CREATE_PCI_WRITE_END_PADDING', -} -IBV_QP_CREATE_BLOCK_SELF_MCAST_LB = 2 -IBV_QP_CREATE_SCATTER_FCS = 256 -IBV_QP_CREATE_CVLAN_STRIPPING = 512 -IBV_QP_CREATE_SOURCE_QPN = 1024 -IBV_QP_CREATE_PCI_WRITE_END_PADDING = 2048 -ibv_qp_create_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_qp_create_send_ops_flags' -ibv_qp_create_send_ops_flags__enumvalues = { - 1: 'IBV_QP_EX_WITH_RDMA_WRITE', - 2: 'IBV_QP_EX_WITH_RDMA_WRITE_WITH_IMM', - 4: 'IBV_QP_EX_WITH_SEND', - 8: 'IBV_QP_EX_WITH_SEND_WITH_IMM', - 16: 'IBV_QP_EX_WITH_RDMA_READ', - 32: 'IBV_QP_EX_WITH_ATOMIC_CMP_AND_SWP', - 64: 'IBV_QP_EX_WITH_ATOMIC_FETCH_AND_ADD', - 128: 'IBV_QP_EX_WITH_LOCAL_INV', - 256: 'IBV_QP_EX_WITH_BIND_MW', - 512: 'IBV_QP_EX_WITH_SEND_WITH_INV', - 1024: 'IBV_QP_EX_WITH_TSO', - 2048: 'IBV_QP_EX_WITH_FLUSH', - 4096: 'IBV_QP_EX_WITH_ATOMIC_WRITE', -} -IBV_QP_EX_WITH_RDMA_WRITE = 1 -IBV_QP_EX_WITH_RDMA_WRITE_WITH_IMM = 2 -IBV_QP_EX_WITH_SEND = 4 -IBV_QP_EX_WITH_SEND_WITH_IMM = 8 -IBV_QP_EX_WITH_RDMA_READ = 16 -IBV_QP_EX_WITH_ATOMIC_CMP_AND_SWP = 32 -IBV_QP_EX_WITH_ATOMIC_FETCH_AND_ADD = 64 -IBV_QP_EX_WITH_LOCAL_INV = 128 -IBV_QP_EX_WITH_BIND_MW = 256 -IBV_QP_EX_WITH_SEND_WITH_INV = 512 -IBV_QP_EX_WITH_TSO = 1024 -IBV_QP_EX_WITH_FLUSH = 2048 -IBV_QP_EX_WITH_ATOMIC_WRITE = 4096 -ibv_qp_create_send_ops_flags = ctypes.c_uint32 # enum -class struct_ibv_rx_hash_conf(Structure): - pass - -struct_ibv_rx_hash_conf._pack_ = 1 # source:False -struct_ibv_rx_hash_conf._fields_ = [ - ('rx_hash_function', ctypes.c_ubyte), - ('rx_hash_key_len', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 6), - ('rx_hash_key', ctypes.POINTER(ctypes.c_ubyte)), - ('rx_hash_fields_mask', ctypes.c_uint64), -] - -class struct_ibv_qp_init_attr_ex(Structure): - pass - -struct_ibv_qp_init_attr_ex._pack_ = 1 # source:False -struct_ibv_qp_init_attr_ex._fields_ = [ - ('qp_context', ctypes.POINTER(None)), - ('send_cq', ctypes.POINTER(struct_ibv_cq)), - ('recv_cq', ctypes.POINTER(struct_ibv_cq)), - ('srq', ctypes.POINTER(struct_ibv_srq)), - ('cap', struct_ibv_qp_cap), - ('qp_type', ibv_qp_type), - ('sq_sig_all', ctypes.c_int32), - ('comp_mask', ctypes.c_uint32), - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('xrcd', ctypes.POINTER(struct_ibv_xrcd)), - ('create_flags', ctypes.c_uint32), - ('max_tso_header', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('rwq_ind_tbl', ctypes.POINTER(struct_ibv_rwq_ind_table)), - ('rx_hash_conf', struct_ibv_rx_hash_conf), - ('source_qpn', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('send_ops_flags', ctypes.c_uint64), -] - - -# values for enumeration 'ibv_qp_open_attr_mask' -ibv_qp_open_attr_mask__enumvalues = { - 1: 'IBV_QP_OPEN_ATTR_NUM', - 2: 'IBV_QP_OPEN_ATTR_XRCD', - 4: 'IBV_QP_OPEN_ATTR_CONTEXT', - 8: 'IBV_QP_OPEN_ATTR_TYPE', - 16: 'IBV_QP_OPEN_ATTR_RESERVED', -} -IBV_QP_OPEN_ATTR_NUM = 1 -IBV_QP_OPEN_ATTR_XRCD = 2 -IBV_QP_OPEN_ATTR_CONTEXT = 4 -IBV_QP_OPEN_ATTR_TYPE = 8 -IBV_QP_OPEN_ATTR_RESERVED = 16 -ibv_qp_open_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_qp_open_attr(Structure): - pass - -struct_ibv_qp_open_attr._pack_ = 1 # source:False -struct_ibv_qp_open_attr._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('qp_num', ctypes.c_uint32), - ('xrcd', ctypes.POINTER(struct_ibv_xrcd)), - ('qp_context', ctypes.POINTER(None)), - ('qp_type', ibv_qp_type), - ('PADDING_0', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_qp_attr_mask' -ibv_qp_attr_mask__enumvalues = { - 1: 'IBV_QP_STATE', - 2: 'IBV_QP_CUR_STATE', - 4: 'IBV_QP_EN_SQD_ASYNC_NOTIFY', - 8: 'IBV_QP_ACCESS_FLAGS', - 16: 'IBV_QP_PKEY_INDEX', - 32: 'IBV_QP_PORT', - 64: 'IBV_QP_QKEY', - 128: 'IBV_QP_AV', - 256: 'IBV_QP_PATH_MTU', - 512: 'IBV_QP_TIMEOUT', - 1024: 'IBV_QP_RETRY_CNT', - 2048: 'IBV_QP_RNR_RETRY', - 4096: 'IBV_QP_RQ_PSN', - 8192: 'IBV_QP_MAX_QP_RD_ATOMIC', - 16384: 'IBV_QP_ALT_PATH', - 32768: 'IBV_QP_MIN_RNR_TIMER', - 65536: 'IBV_QP_SQ_PSN', - 131072: 'IBV_QP_MAX_DEST_RD_ATOMIC', - 262144: 'IBV_QP_PATH_MIG_STATE', - 524288: 'IBV_QP_CAP', - 1048576: 'IBV_QP_DEST_QPN', - 33554432: 'IBV_QP_RATE_LIMIT', -} -IBV_QP_STATE = 1 -IBV_QP_CUR_STATE = 2 -IBV_QP_EN_SQD_ASYNC_NOTIFY = 4 -IBV_QP_ACCESS_FLAGS = 8 -IBV_QP_PKEY_INDEX = 16 -IBV_QP_PORT = 32 -IBV_QP_QKEY = 64 -IBV_QP_AV = 128 -IBV_QP_PATH_MTU = 256 -IBV_QP_TIMEOUT = 512 -IBV_QP_RETRY_CNT = 1024 -IBV_QP_RNR_RETRY = 2048 -IBV_QP_RQ_PSN = 4096 -IBV_QP_MAX_QP_RD_ATOMIC = 8192 -IBV_QP_ALT_PATH = 16384 -IBV_QP_MIN_RNR_TIMER = 32768 -IBV_QP_SQ_PSN = 65536 -IBV_QP_MAX_DEST_RD_ATOMIC = 131072 -IBV_QP_PATH_MIG_STATE = 262144 -IBV_QP_CAP = 524288 -IBV_QP_DEST_QPN = 1048576 -IBV_QP_RATE_LIMIT = 33554432 -ibv_qp_attr_mask = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_query_qp_data_in_order_flags' -ibv_query_qp_data_in_order_flags__enumvalues = { - 1: 'IBV_QUERY_QP_DATA_IN_ORDER_RETURN_CAPS', -} -IBV_QUERY_QP_DATA_IN_ORDER_RETURN_CAPS = 1 -ibv_query_qp_data_in_order_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_query_qp_data_in_order_caps' -ibv_query_qp_data_in_order_caps__enumvalues = { - 1: 'IBV_QUERY_QP_DATA_IN_ORDER_WHOLE_MSG', - 2: 'IBV_QUERY_QP_DATA_IN_ORDER_ALIGNED_128_BYTES', -} -IBV_QUERY_QP_DATA_IN_ORDER_WHOLE_MSG = 1 -IBV_QUERY_QP_DATA_IN_ORDER_ALIGNED_128_BYTES = 2 -ibv_query_qp_data_in_order_caps = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_mig_state' -ibv_mig_state__enumvalues = { - 0: 'IBV_MIG_MIGRATED', - 1: 'IBV_MIG_REARM', - 2: 'IBV_MIG_ARMED', -} -IBV_MIG_MIGRATED = 0 -IBV_MIG_REARM = 1 -IBV_MIG_ARMED = 2 -ibv_mig_state = ctypes.c_uint32 # enum -class struct_ibv_qp_attr(Structure): - pass - -struct_ibv_qp_attr._pack_ = 1 # source:False -struct_ibv_qp_attr._fields_ = [ - ('qp_state', ibv_qp_state), - ('cur_qp_state', ibv_qp_state), - ('path_mtu', ibv_mtu), - ('path_mig_state', ibv_mig_state), - ('qkey', ctypes.c_uint32), - ('rq_psn', ctypes.c_uint32), - ('sq_psn', ctypes.c_uint32), - ('dest_qp_num', ctypes.c_uint32), - ('qp_access_flags', ctypes.c_uint32), - ('cap', struct_ibv_qp_cap), - ('ah_attr', struct_ibv_ah_attr), - ('alt_ah_attr', struct_ibv_ah_attr), - ('pkey_index', ctypes.c_uint16), - ('alt_pkey_index', ctypes.c_uint16), - ('en_sqd_async_notify', ctypes.c_ubyte), - ('sq_draining', ctypes.c_ubyte), - ('max_rd_atomic', ctypes.c_ubyte), - ('max_dest_rd_atomic', ctypes.c_ubyte), - ('min_rnr_timer', ctypes.c_ubyte), - ('port_num', ctypes.c_ubyte), - ('timeout', ctypes.c_ubyte), - ('retry_cnt', ctypes.c_ubyte), - ('rnr_retry', ctypes.c_ubyte), - ('alt_port_num', ctypes.c_ubyte), - ('alt_timeout', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), - ('rate_limit', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -class struct_ibv_qp_rate_limit_attr(Structure): - pass - -struct_ibv_qp_rate_limit_attr._pack_ = 1 # source:False -struct_ibv_qp_rate_limit_attr._fields_ = [ - ('rate_limit', ctypes.c_uint32), - ('max_burst_sz', ctypes.c_uint32), - ('typical_pkt_sz', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('comp_mask', ctypes.c_uint32), -] - -try: - ibv_wr_opcode_str = _libraries['libibverbs'].ibv_wr_opcode_str - ibv_wr_opcode_str.restype = ctypes.POINTER(ctypes.c_char) - ibv_wr_opcode_str.argtypes = [ibv_wr_opcode] -except AttributeError: - pass - -# values for enumeration 'ibv_send_flags' -ibv_send_flags__enumvalues = { - 1: 'IBV_SEND_FENCE', - 2: 'IBV_SEND_SIGNALED', - 4: 'IBV_SEND_SOLICITED', - 8: 'IBV_SEND_INLINE', - 16: 'IBV_SEND_IP_CSUM', -} -IBV_SEND_FENCE = 1 -IBV_SEND_SIGNALED = 2 -IBV_SEND_SOLICITED = 4 -IBV_SEND_INLINE = 8 -IBV_SEND_IP_CSUM = 16 -ibv_send_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_placement_type' -ibv_placement_type__enumvalues = { - 1: 'IBV_FLUSH_GLOBAL', - 2: 'IBV_FLUSH_PERSISTENT', -} -IBV_FLUSH_GLOBAL = 1 -IBV_FLUSH_PERSISTENT = 2 -ibv_placement_type = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_selectivity_level' -ibv_selectivity_level__enumvalues = { - 0: 'IBV_FLUSH_RANGE', - 1: 'IBV_FLUSH_MR', -} -IBV_FLUSH_RANGE = 0 -IBV_FLUSH_MR = 1 -ibv_selectivity_level = ctypes.c_uint32 # enum -class struct_ibv_data_buf(Structure): - pass - -struct_ibv_data_buf._pack_ = 1 # source:False -struct_ibv_data_buf._fields_ = [ - ('addr', ctypes.POINTER(None)), - ('length', ctypes.c_uint64), -] - - -# values for enumeration 'ibv_ops_wr_opcode' -ibv_ops_wr_opcode__enumvalues = { - 0: 'IBV_WR_TAG_ADD', - 1: 'IBV_WR_TAG_DEL', - 2: 'IBV_WR_TAG_SYNC', -} -IBV_WR_TAG_ADD = 0 -IBV_WR_TAG_DEL = 1 -IBV_WR_TAG_SYNC = 2 -ibv_ops_wr_opcode = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_ops_flags' -ibv_ops_flags__enumvalues = { - 1: 'IBV_OPS_SIGNALED', - 2: 'IBV_OPS_TM_SYNC', -} -IBV_OPS_SIGNALED = 1 -IBV_OPS_TM_SYNC = 2 -ibv_ops_flags = ctypes.c_uint32 # enum -class struct_ibv_ops_wr(Structure): - pass - -class struct_ibv_ops_wr_tm(Structure): - pass - -class struct_ibv_ops_wr_0_add(Structure): - pass - -struct_ibv_ops_wr_0_add._pack_ = 1 # source:False -struct_ibv_ops_wr_0_add._fields_ = [ - ('recv_wr_id', ctypes.c_uint64), - ('sg_list', ctypes.POINTER(struct_ibv_sge)), - ('num_sge', ctypes.c_int32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('tag', ctypes.c_uint64), - ('mask', ctypes.c_uint64), -] - -struct_ibv_ops_wr_tm._pack_ = 1 # source:False -struct_ibv_ops_wr_tm._fields_ = [ - ('unexpected_cnt', ctypes.c_uint32), - ('handle', ctypes.c_uint32), - ('add', struct_ibv_ops_wr_0_add), -] - -struct_ibv_ops_wr._pack_ = 1 # source:False -struct_ibv_ops_wr._fields_ = [ - ('wr_id', ctypes.c_uint64), - ('next', ctypes.POINTER(struct_ibv_ops_wr)), - ('opcode', ibv_ops_wr_opcode), - ('flags', ctypes.c_int32), - ('tm', struct_ibv_ops_wr_tm), -] - -class struct_ibv_qp_ex(Structure): - pass - -struct_ibv_qp_ex._pack_ = 1 # source:False -struct_ibv_qp_ex._fields_ = [ - ('qp_base', struct_ibv_qp), - ('comp_mask', ctypes.c_uint64), - ('wr_id', ctypes.c_uint64), - ('wr_flags', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('wr_atomic_cmp_swp', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64)), - ('wr_atomic_fetch_add', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64, ctypes.c_uint64)), - ('wr_bind_mw', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(struct_ibv_mw), ctypes.c_uint32, ctypes.POINTER(struct_ibv_mw_bind_info))), - ('wr_local_inv', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32)), - ('wr_rdma_read', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64)), - ('wr_rdma_write', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64)), - ('wr_rdma_write_imm', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64, ctypes.c_uint32)), - ('wr_send', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex))), - ('wr_send_imm', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32)), - ('wr_send_inv', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32)), - ('wr_send_tso', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(None), ctypes.c_uint16, ctypes.c_uint16)), - ('wr_set_ud_addr', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(struct_ibv_ah), ctypes.c_uint32, ctypes.c_uint32)), - ('wr_set_xrc_srqn', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32)), - ('wr_set_inline_data', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(None), ctypes.c_uint64)), - ('wr_set_inline_data_list', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint64, ctypes.POINTER(struct_ibv_data_buf))), - ('wr_set_sge', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64, ctypes.c_uint32)), - ('wr_set_sge_list', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint64, ctypes.POINTER(struct_ibv_sge))), - ('wr_start', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex))), - ('wr_complete', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp_ex))), - ('wr_abort', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex))), - ('wr_atomic_write', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64, ctypes.POINTER(None))), - ('wr_flush', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_qp_ex), ctypes.c_uint32, ctypes.c_uint64, ctypes.c_uint64, ctypes.c_ubyte, ctypes.c_ubyte)), -] - -try: - ibv_qp_to_qp_ex = _libraries['libibverbs'].ibv_qp_to_qp_ex - ibv_qp_to_qp_ex.restype = ctypes.POINTER(struct_ibv_qp_ex) - ibv_qp_to_qp_ex.argtypes = [ctypes.POINTER(struct_ibv_qp)] -except AttributeError: - pass -uint32_t = ctypes.c_uint32 -uint64_t = ctypes.c_uint64 -try: - ibv_wr_atomic_cmp_swp = _libraries['libibverbs'].ibv_wr_atomic_cmp_swp - ibv_wr_atomic_cmp_swp.restype = None - ibv_wr_atomic_cmp_swp.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, uint64_t, uint64_t] -except AttributeError: - pass -try: - ibv_wr_atomic_fetch_add = _libraries['libibverbs'].ibv_wr_atomic_fetch_add - ibv_wr_atomic_fetch_add.restype = None - ibv_wr_atomic_fetch_add.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, uint64_t] -except AttributeError: - pass -try: - ibv_wr_bind_mw = _libraries['libibverbs'].ibv_wr_bind_mw - ibv_wr_bind_mw.restype = None - ibv_wr_bind_mw.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(struct_ibv_mw), uint32_t, ctypes.POINTER(struct_ibv_mw_bind_info)] -except AttributeError: - pass -try: - ibv_wr_local_inv = _libraries['libibverbs'].ibv_wr_local_inv - ibv_wr_local_inv.restype = None - ibv_wr_local_inv.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t] -except AttributeError: - pass -try: - ibv_wr_rdma_read = _libraries['libibverbs'].ibv_wr_rdma_read - ibv_wr_rdma_read.restype = None - ibv_wr_rdma_read.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t] -except AttributeError: - pass -try: - ibv_wr_rdma_write = _libraries['libibverbs'].ibv_wr_rdma_write - ibv_wr_rdma_write.restype = None - ibv_wr_rdma_write.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t] -except AttributeError: - pass -size_t = ctypes.c_uint64 -uint8_t = ctypes.c_uint8 -try: - ibv_wr_flush = _libraries['libibverbs'].ibv_wr_flush - ibv_wr_flush.restype = None - ibv_wr_flush.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, size_t, uint8_t, uint8_t] -except AttributeError: - pass -__be32 = ctypes.c_uint32 -try: - ibv_wr_rdma_write_imm = _libraries['libibverbs'].ibv_wr_rdma_write_imm - ibv_wr_rdma_write_imm.restype = None - ibv_wr_rdma_write_imm.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, __be32] -except AttributeError: - pass -try: - ibv_wr_send = _libraries['libibverbs'].ibv_wr_send - ibv_wr_send.restype = None - ibv_wr_send.argtypes = [ctypes.POINTER(struct_ibv_qp_ex)] -except AttributeError: - pass -try: - ibv_wr_send_imm = _libraries['libibverbs'].ibv_wr_send_imm - ibv_wr_send_imm.restype = None - ibv_wr_send_imm.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), __be32] -except AttributeError: - pass -try: - ibv_wr_send_inv = _libraries['libibverbs'].ibv_wr_send_inv - ibv_wr_send_inv.restype = None - ibv_wr_send_inv.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t] -except AttributeError: - pass -uint16_t = ctypes.c_uint16 -try: - ibv_wr_send_tso = _libraries['libibverbs'].ibv_wr_send_tso - ibv_wr_send_tso.restype = None - ibv_wr_send_tso.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(None), uint16_t, uint16_t] -except AttributeError: - pass -try: - ibv_wr_set_ud_addr = _libraries['libibverbs'].ibv_wr_set_ud_addr - ibv_wr_set_ud_addr.restype = None - ibv_wr_set_ud_addr.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(struct_ibv_ah), uint32_t, uint32_t] -except AttributeError: - pass -try: - ibv_wr_set_xrc_srqn = _libraries['libibverbs'].ibv_wr_set_xrc_srqn - ibv_wr_set_xrc_srqn.restype = None - ibv_wr_set_xrc_srqn.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t] -except AttributeError: - pass -try: - ibv_wr_set_inline_data = _libraries['libibverbs'].ibv_wr_set_inline_data - ibv_wr_set_inline_data.restype = None - ibv_wr_set_inline_data.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - ibv_wr_set_inline_data_list = _libraries['libibverbs'].ibv_wr_set_inline_data_list - ibv_wr_set_inline_data_list.restype = None - ibv_wr_set_inline_data_list.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), size_t, ctypes.POINTER(struct_ibv_data_buf)] -except AttributeError: - pass -try: - ibv_wr_set_sge = _libraries['libibverbs'].ibv_wr_set_sge - ibv_wr_set_sge.restype = None - ibv_wr_set_sge.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, uint32_t] -except AttributeError: - pass -try: - ibv_wr_set_sge_list = _libraries['libibverbs'].ibv_wr_set_sge_list - ibv_wr_set_sge_list.restype = None - ibv_wr_set_sge_list.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), size_t, ctypes.POINTER(struct_ibv_sge)] -except AttributeError: - pass -try: - ibv_wr_start = _libraries['libibverbs'].ibv_wr_start - ibv_wr_start.restype = None - ibv_wr_start.argtypes = [ctypes.POINTER(struct_ibv_qp_ex)] -except AttributeError: - pass -try: - ibv_wr_complete = _libraries['libibverbs'].ibv_wr_complete - ibv_wr_complete.restype = ctypes.c_int32 - ibv_wr_complete.argtypes = [ctypes.POINTER(struct_ibv_qp_ex)] -except AttributeError: - pass -try: - ibv_wr_abort = _libraries['libibverbs'].ibv_wr_abort - ibv_wr_abort.restype = None - ibv_wr_abort.argtypes = [ctypes.POINTER(struct_ibv_qp_ex)] -except AttributeError: - pass -try: - ibv_wr_atomic_write = _libraries['libibverbs'].ibv_wr_atomic_write - ibv_wr_atomic_write.restype = None - ibv_wr_atomic_write.argtypes = [ctypes.POINTER(struct_ibv_qp_ex), uint32_t, uint64_t, ctypes.POINTER(None)] -except AttributeError: - pass -class struct_ibv_ece(Structure): - pass - -struct_ibv_ece._pack_ = 1 # source:False -struct_ibv_ece._fields_ = [ - ('vendor_id', ctypes.c_uint32), - ('options', ctypes.c_uint32), - ('comp_mask', ctypes.c_uint32), -] - -class struct_ibv_poll_cq_attr(Structure): - pass - -struct_ibv_poll_cq_attr._pack_ = 1 # source:False -struct_ibv_poll_cq_attr._fields_ = [ - ('comp_mask', ctypes.c_uint32), -] - -class struct_ibv_wc_tm_info(Structure): - pass - -struct_ibv_wc_tm_info._pack_ = 1 # source:False -struct_ibv_wc_tm_info._fields_ = [ - ('tag', ctypes.c_uint64), - ('priv', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -class struct_ibv_cq_ex(Structure): - pass - -struct_ibv_cq_ex._pack_ = 1 # source:False -struct_ibv_cq_ex._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), - ('channel', ctypes.POINTER(struct_ibv_comp_channel)), - ('cq_context', ctypes.POINTER(None)), - ('handle', ctypes.c_uint32), - ('cqe', ctypes.c_int32), - ('mutex', union_c__UA_pthread_mutex_t), - ('cond', union_c__UA_pthread_cond_t), - ('comp_events_completed', ctypes.c_uint32), - ('async_events_completed', ctypes.c_uint32), - ('comp_mask', ctypes.c_uint32), - ('status', ibv_wc_status), - ('wr_id', ctypes.c_uint64), - ('start_poll', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_poll_cq_attr))), - ('next_poll', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq_ex))), - ('end_poll', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_opcode', ctypes.CFUNCTYPE(ibv_wc_opcode, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_vendor_err', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_byte_len', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_imm_data', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_qp_num', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_src_qp', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_wc_flags', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_slid', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_sl', ctypes.CFUNCTYPE(ctypes.c_ubyte, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_dlid_path_bits', ctypes.CFUNCTYPE(ctypes.c_ubyte, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_completion_ts', ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_cvlan', ctypes.CFUNCTYPE(ctypes.c_uint16, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_flow_tag', ctypes.CFUNCTYPE(ctypes.c_uint32, ctypes.POINTER(struct_ibv_cq_ex))), - ('read_tm_info', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_wc_tm_info))), - ('read_completion_wallclock_ns', ctypes.CFUNCTYPE(ctypes.c_uint64, ctypes.POINTER(struct_ibv_cq_ex))), -] - -try: - ibv_cq_ex_to_cq = _libraries['libibverbs'].ibv_cq_ex_to_cq - ibv_cq_ex_to_cq.restype = ctypes.POINTER(struct_ibv_cq) - ibv_cq_ex_to_cq.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass - -# values for enumeration 'ibv_cq_attr_mask' -ibv_cq_attr_mask__enumvalues = { - 1: 'IBV_CQ_ATTR_MODERATE', - 2: 'IBV_CQ_ATTR_RESERVED', -} -IBV_CQ_ATTR_MODERATE = 1 -IBV_CQ_ATTR_RESERVED = 2 -ibv_cq_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_moderate_cq(Structure): - pass - -struct_ibv_moderate_cq._pack_ = 1 # source:False -struct_ibv_moderate_cq._fields_ = [ - ('cq_count', ctypes.c_uint16), - ('cq_period', ctypes.c_uint16), -] - -class struct_ibv_modify_cq_attr(Structure): - pass - -struct_ibv_modify_cq_attr._pack_ = 1 # source:False -struct_ibv_modify_cq_attr._fields_ = [ - ('attr_mask', ctypes.c_uint32), - ('moderate', struct_ibv_moderate_cq), -] - -try: - ibv_start_poll = _libraries['libibverbs'].ibv_start_poll - ibv_start_poll.restype = ctypes.c_int32 - ibv_start_poll.argtypes = [ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_poll_cq_attr)] -except AttributeError: - pass -try: - ibv_next_poll = _libraries['libibverbs'].ibv_next_poll - ibv_next_poll.restype = ctypes.c_int32 - ibv_next_poll.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_end_poll = _libraries['libibverbs'].ibv_end_poll - ibv_end_poll.restype = None - ibv_end_poll.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_opcode = _libraries['libibverbs'].ibv_wc_read_opcode - ibv_wc_read_opcode.restype = ibv_wc_opcode - ibv_wc_read_opcode.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_vendor_err = _libraries['libibverbs'].ibv_wc_read_vendor_err - ibv_wc_read_vendor_err.restype = uint32_t - ibv_wc_read_vendor_err.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_byte_len = _libraries['libibverbs'].ibv_wc_read_byte_len - ibv_wc_read_byte_len.restype = uint32_t - ibv_wc_read_byte_len.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_imm_data = _libraries['libibverbs'].ibv_wc_read_imm_data - ibv_wc_read_imm_data.restype = __be32 - ibv_wc_read_imm_data.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_invalidated_rkey = _libraries['libibverbs'].ibv_wc_read_invalidated_rkey - ibv_wc_read_invalidated_rkey.restype = uint32_t - ibv_wc_read_invalidated_rkey.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_qp_num = _libraries['libibverbs'].ibv_wc_read_qp_num - ibv_wc_read_qp_num.restype = uint32_t - ibv_wc_read_qp_num.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_src_qp = _libraries['libibverbs'].ibv_wc_read_src_qp - ibv_wc_read_src_qp.restype = uint32_t - ibv_wc_read_src_qp.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_wc_flags = _libraries['libibverbs'].ibv_wc_read_wc_flags - ibv_wc_read_wc_flags.restype = ctypes.c_uint32 - ibv_wc_read_wc_flags.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_slid = _libraries['libibverbs'].ibv_wc_read_slid - ibv_wc_read_slid.restype = uint32_t - ibv_wc_read_slid.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_sl = _libraries['libibverbs'].ibv_wc_read_sl - ibv_wc_read_sl.restype = uint8_t - ibv_wc_read_sl.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_dlid_path_bits = _libraries['libibverbs'].ibv_wc_read_dlid_path_bits - ibv_wc_read_dlid_path_bits.restype = uint8_t - ibv_wc_read_dlid_path_bits.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_completion_ts = _libraries['libibverbs'].ibv_wc_read_completion_ts - ibv_wc_read_completion_ts.restype = uint64_t - ibv_wc_read_completion_ts.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_completion_wallclock_ns = _libraries['libibverbs'].ibv_wc_read_completion_wallclock_ns - ibv_wc_read_completion_wallclock_ns.restype = uint64_t - ibv_wc_read_completion_wallclock_ns.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_cvlan = _libraries['libibverbs'].ibv_wc_read_cvlan - ibv_wc_read_cvlan.restype = uint16_t - ibv_wc_read_cvlan.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_flow_tag = _libraries['libibverbs'].ibv_wc_read_flow_tag - ibv_wc_read_flow_tag.restype = uint32_t - ibv_wc_read_flow_tag.argtypes = [ctypes.POINTER(struct_ibv_cq_ex)] -except AttributeError: - pass -try: - ibv_wc_read_tm_info = _libraries['libibverbs'].ibv_wc_read_tm_info - ibv_wc_read_tm_info.restype = None - ibv_wc_read_tm_info.argtypes = [ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_wc_tm_info)] -except AttributeError: - pass -try: - ibv_post_wq_recv = _libraries['libibverbs'].ibv_post_wq_recv - ibv_post_wq_recv.restype = ctypes.c_int32 - ibv_post_wq_recv.argtypes = [ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr))] -except AttributeError: - pass - -# values for enumeration 'ibv_flow_flags' -ibv_flow_flags__enumvalues = { - 2: 'IBV_FLOW_ATTR_FLAGS_DONT_TRAP', - 4: 'IBV_FLOW_ATTR_FLAGS_EGRESS', -} -IBV_FLOW_ATTR_FLAGS_DONT_TRAP = 2 -IBV_FLOW_ATTR_FLAGS_EGRESS = 4 -ibv_flow_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_flow_attr_type' -ibv_flow_attr_type__enumvalues = { - 0: 'IBV_FLOW_ATTR_NORMAL', - 1: 'IBV_FLOW_ATTR_ALL_DEFAULT', - 2: 'IBV_FLOW_ATTR_MC_DEFAULT', - 3: 'IBV_FLOW_ATTR_SNIFFER', -} -IBV_FLOW_ATTR_NORMAL = 0 -IBV_FLOW_ATTR_ALL_DEFAULT = 1 -IBV_FLOW_ATTR_MC_DEFAULT = 2 -IBV_FLOW_ATTR_SNIFFER = 3 -ibv_flow_attr_type = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_flow_spec_type' -ibv_flow_spec_type__enumvalues = { - 32: 'IBV_FLOW_SPEC_ETH', - 48: 'IBV_FLOW_SPEC_IPV4', - 49: 'IBV_FLOW_SPEC_IPV6', - 50: 'IBV_FLOW_SPEC_IPV4_EXT', - 52: 'IBV_FLOW_SPEC_ESP', - 64: 'IBV_FLOW_SPEC_TCP', - 65: 'IBV_FLOW_SPEC_UDP', - 80: 'IBV_FLOW_SPEC_VXLAN_TUNNEL', - 81: 'IBV_FLOW_SPEC_GRE', - 96: 'IBV_FLOW_SPEC_MPLS', - 256: 'IBV_FLOW_SPEC_INNER', - 4096: 'IBV_FLOW_SPEC_ACTION_TAG', - 4097: 'IBV_FLOW_SPEC_ACTION_DROP', - 4098: 'IBV_FLOW_SPEC_ACTION_HANDLE', - 4099: 'IBV_FLOW_SPEC_ACTION_COUNT', -} -IBV_FLOW_SPEC_ETH = 32 -IBV_FLOW_SPEC_IPV4 = 48 -IBV_FLOW_SPEC_IPV6 = 49 -IBV_FLOW_SPEC_IPV4_EXT = 50 -IBV_FLOW_SPEC_ESP = 52 -IBV_FLOW_SPEC_TCP = 64 -IBV_FLOW_SPEC_UDP = 65 -IBV_FLOW_SPEC_VXLAN_TUNNEL = 80 -IBV_FLOW_SPEC_GRE = 81 -IBV_FLOW_SPEC_MPLS = 96 -IBV_FLOW_SPEC_INNER = 256 -IBV_FLOW_SPEC_ACTION_TAG = 4096 -IBV_FLOW_SPEC_ACTION_DROP = 4097 -IBV_FLOW_SPEC_ACTION_HANDLE = 4098 -IBV_FLOW_SPEC_ACTION_COUNT = 4099 -ibv_flow_spec_type = ctypes.c_uint32 # enum -class struct_ibv_flow_eth_filter(Structure): - pass - -struct_ibv_flow_eth_filter._pack_ = 1 # source:False -struct_ibv_flow_eth_filter._fields_ = [ - ('dst_mac', ctypes.c_ubyte * 6), - ('src_mac', ctypes.c_ubyte * 6), - ('ether_type', ctypes.c_uint16), - ('vlan_tag', ctypes.c_uint16), -] - -class struct_ibv_flow_spec_eth(Structure): - pass - -struct_ibv_flow_spec_eth._pack_ = 1 # source:False -struct_ibv_flow_spec_eth._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('val', struct_ibv_flow_eth_filter), - ('mask', struct_ibv_flow_eth_filter), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -class struct_ibv_flow_ipv4_filter(Structure): - pass - -struct_ibv_flow_ipv4_filter._pack_ = 1 # source:False -struct_ibv_flow_ipv4_filter._fields_ = [ - ('src_ip', ctypes.c_uint32), - ('dst_ip', ctypes.c_uint32), -] - -class struct_ibv_flow_spec_ipv4(Structure): - pass - -struct_ibv_flow_spec_ipv4._pack_ = 1 # source:False -struct_ibv_flow_spec_ipv4._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_ipv4_filter), - ('mask', struct_ibv_flow_ipv4_filter), -] - -class struct_ibv_flow_ipv4_ext_filter(Structure): - pass - -struct_ibv_flow_ipv4_ext_filter._pack_ = 1 # source:False -struct_ibv_flow_ipv4_ext_filter._fields_ = [ - ('src_ip', ctypes.c_uint32), - ('dst_ip', ctypes.c_uint32), - ('proto', ctypes.c_ubyte), - ('tos', ctypes.c_ubyte), - ('ttl', ctypes.c_ubyte), - ('flags', ctypes.c_ubyte), -] - -class struct_ibv_flow_spec_ipv4_ext(Structure): - pass - -struct_ibv_flow_spec_ipv4_ext._pack_ = 1 # source:False -struct_ibv_flow_spec_ipv4_ext._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_ipv4_ext_filter), - ('mask', struct_ibv_flow_ipv4_ext_filter), -] - -class struct_ibv_flow_ipv6_filter(Structure): - pass - -struct_ibv_flow_ipv6_filter._pack_ = 1 # source:False -struct_ibv_flow_ipv6_filter._fields_ = [ - ('src_ip', ctypes.c_ubyte * 16), - ('dst_ip', ctypes.c_ubyte * 16), - ('flow_label', ctypes.c_uint32), - ('next_hdr', ctypes.c_ubyte), - ('traffic_class', ctypes.c_ubyte), - ('hop_limit', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte), -] - -class struct_ibv_flow_spec_ipv6(Structure): - pass - -struct_ibv_flow_spec_ipv6._pack_ = 1 # source:False -struct_ibv_flow_spec_ipv6._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_ipv6_filter), - ('mask', struct_ibv_flow_ipv6_filter), -] - -class struct_ibv_flow_esp_filter(Structure): - pass - -struct_ibv_flow_esp_filter._pack_ = 1 # source:False -struct_ibv_flow_esp_filter._fields_ = [ - ('spi', ctypes.c_uint32), - ('seq', ctypes.c_uint32), -] - -class struct_ibv_flow_spec_esp(Structure): - pass - -struct_ibv_flow_spec_esp._pack_ = 1 # source:False -struct_ibv_flow_spec_esp._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_esp_filter), - ('mask', struct_ibv_flow_esp_filter), -] - -class struct_ibv_flow_tcp_udp_filter(Structure): - pass - -struct_ibv_flow_tcp_udp_filter._pack_ = 1 # source:False -struct_ibv_flow_tcp_udp_filter._fields_ = [ - ('dst_port', ctypes.c_uint16), - ('src_port', ctypes.c_uint16), -] - -class struct_ibv_flow_spec_tcp_udp(Structure): - pass - -struct_ibv_flow_spec_tcp_udp._pack_ = 1 # source:False -struct_ibv_flow_spec_tcp_udp._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('val', struct_ibv_flow_tcp_udp_filter), - ('mask', struct_ibv_flow_tcp_udp_filter), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -class struct_ibv_flow_gre_filter(Structure): - pass - -struct_ibv_flow_gre_filter._pack_ = 1 # source:False -struct_ibv_flow_gre_filter._fields_ = [ - ('c_ks_res0_ver', ctypes.c_uint16), - ('protocol', ctypes.c_uint16), - ('key', ctypes.c_uint32), -] - -class struct_ibv_flow_spec_gre(Structure): - pass - -struct_ibv_flow_spec_gre._pack_ = 1 # source:False -struct_ibv_flow_spec_gre._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_gre_filter), - ('mask', struct_ibv_flow_gre_filter), -] - -class struct_ibv_flow_mpls_filter(Structure): - pass - -struct_ibv_flow_mpls_filter._pack_ = 1 # source:False -struct_ibv_flow_mpls_filter._fields_ = [ - ('label', ctypes.c_uint32), -] - -class struct_ibv_flow_spec_mpls(Structure): - pass - -struct_ibv_flow_spec_mpls._pack_ = 1 # source:False -struct_ibv_flow_spec_mpls._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_mpls_filter), - ('mask', struct_ibv_flow_mpls_filter), -] - -class struct_ibv_flow_tunnel_filter(Structure): - pass - -struct_ibv_flow_tunnel_filter._pack_ = 1 # source:False -struct_ibv_flow_tunnel_filter._fields_ = [ - ('tunnel_id', ctypes.c_uint32), -] - -class struct_ibv_flow_spec_tunnel(Structure): - pass - -struct_ibv_flow_spec_tunnel._pack_ = 1 # source:False -struct_ibv_flow_spec_tunnel._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('val', struct_ibv_flow_tunnel_filter), - ('mask', struct_ibv_flow_tunnel_filter), -] - -class struct_ibv_flow_spec_action_tag(Structure): - pass - -struct_ibv_flow_spec_action_tag._pack_ = 1 # source:False -struct_ibv_flow_spec_action_tag._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('tag_id', ctypes.c_uint32), -] - -class struct_ibv_flow_spec_action_drop(Structure): - pass - -struct_ibv_flow_spec_action_drop._pack_ = 1 # source:False -struct_ibv_flow_spec_action_drop._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -class struct_ibv_flow_spec_action_handle(Structure): - pass - -class struct_ibv_flow_action(Structure): - pass - -struct_ibv_flow_spec_action_handle._pack_ = 1 # source:False -struct_ibv_flow_spec_action_handle._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('action', ctypes.POINTER(struct_ibv_flow_action)), -] - -struct_ibv_flow_action._pack_ = 1 # source:False -struct_ibv_flow_action._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), -] - -class struct_ibv_flow_spec_counter_action(Structure): - pass - -class struct_ibv_counters(Structure): - pass - -struct_ibv_flow_spec_counter_action._pack_ = 1 # source:False -struct_ibv_flow_spec_counter_action._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('counters', ctypes.POINTER(struct_ibv_counters)), -] - -struct_ibv_counters._pack_ = 1 # source:False -struct_ibv_counters._fields_ = [ - ('context', ctypes.POINTER(struct_ibv_context)), -] - -class struct_ibv_flow_spec(Structure): - pass - -class union_ibv_flow_spec_0(Union): - pass - -class struct_ibv_flow_spec_0_hdr(Structure): - pass - -struct_ibv_flow_spec_0_hdr._pack_ = 1 # source:False -struct_ibv_flow_spec_0_hdr._fields_ = [ - ('type', ibv_flow_spec_type), - ('size', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), -] - -union_ibv_flow_spec_0._pack_ = 1 # source:False -union_ibv_flow_spec_0._fields_ = [ - ('hdr', struct_ibv_flow_spec_0_hdr), - ('eth', struct_ibv_flow_spec_eth), - ('ipv4', struct_ibv_flow_spec_ipv4), - ('tcp_udp', struct_ibv_flow_spec_tcp_udp), - ('ipv4_ext', struct_ibv_flow_spec_ipv4_ext), - ('ipv6', struct_ibv_flow_spec_ipv6), - ('esp', struct_ibv_flow_spec_esp), - ('tunnel', struct_ibv_flow_spec_tunnel), - ('gre', struct_ibv_flow_spec_gre), - ('mpls', struct_ibv_flow_spec_mpls), - ('flow_tag', struct_ibv_flow_spec_action_tag), - ('drop', struct_ibv_flow_spec_action_drop), - ('handle', struct_ibv_flow_spec_action_handle), - ('flow_count', struct_ibv_flow_spec_counter_action), - ('PADDING_0', ctypes.c_ubyte * 72), -] - -struct_ibv_flow_spec._pack_ = 1 # source:False -struct_ibv_flow_spec._anonymous_ = ('_0',) -struct_ibv_flow_spec._fields_ = [ - ('_0', union_ibv_flow_spec_0), -] - -class struct_ibv_flow_attr(Structure): - pass - -struct_ibv_flow_attr._pack_ = 1 # source:False -struct_ibv_flow_attr._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('type', ibv_flow_attr_type), - ('size', ctypes.c_uint16), - ('priority', ctypes.c_uint16), - ('num_of_specs', ctypes.c_ubyte), - ('port', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 2), - ('flags', ctypes.c_uint32), -] - -class struct_ibv_flow(Structure): - pass - -struct_ibv_flow._pack_ = 1 # source:False -struct_ibv_flow._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('context', ctypes.POINTER(struct_ibv_context)), - ('handle', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - - -# values for enumeration 'ibv_flow_action_esp_mask' -ibv_flow_action_esp_mask__enumvalues = { - 1: 'IBV_FLOW_ACTION_ESP_MASK_ESN', -} -IBV_FLOW_ACTION_ESP_MASK_ESN = 1 -ibv_flow_action_esp_mask = ctypes.c_uint32 # enum -class struct_ibv_flow_action_esp_attr(Structure): - pass - -struct_ibv_flow_action_esp_attr._pack_ = 1 # source:False -struct_ibv_flow_action_esp_attr._fields_ = [ - ('esp_attr', ctypes.POINTER(struct_ib_uverbs_flow_action_esp)), - ('keymat_proto', ib_uverbs_flow_action_esp_keymat), - ('keymat_len', ctypes.c_uint16), - ('PADDING_0', ctypes.c_ubyte * 2), - ('keymat_ptr', ctypes.POINTER(None)), - ('replay_proto', ib_uverbs_flow_action_esp_replay), - ('replay_len', ctypes.c_uint16), - ('PADDING_1', ctypes.c_ubyte * 2), - ('replay_ptr', ctypes.POINTER(None)), - ('esp_encap', ctypes.POINTER(struct_ib_uverbs_flow_action_esp_encap)), - ('comp_mask', ctypes.c_uint32), - ('esn', ctypes.c_uint32), -] - - -# values for enumeration 'c__Ea_IBV_SYSFS_NAME_MAX' -c__Ea_IBV_SYSFS_NAME_MAX__enumvalues = { - 64: 'IBV_SYSFS_NAME_MAX', - 256: 'IBV_SYSFS_PATH_MAX', -} -IBV_SYSFS_NAME_MAX = 64 -IBV_SYSFS_PATH_MAX = 256 -c__Ea_IBV_SYSFS_NAME_MAX = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_cq_init_attr_mask' -ibv_cq_init_attr_mask__enumvalues = { - 1: 'IBV_CQ_INIT_ATTR_MASK_FLAGS', - 2: 'IBV_CQ_INIT_ATTR_MASK_PD', -} -IBV_CQ_INIT_ATTR_MASK_FLAGS = 1 -IBV_CQ_INIT_ATTR_MASK_PD = 2 -ibv_cq_init_attr_mask = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_create_cq_attr_flags' -ibv_create_cq_attr_flags__enumvalues = { - 1: 'IBV_CREATE_CQ_ATTR_SINGLE_THREADED', - 2: 'IBV_CREATE_CQ_ATTR_IGNORE_OVERRUN', -} -IBV_CREATE_CQ_ATTR_SINGLE_THREADED = 1 -IBV_CREATE_CQ_ATTR_IGNORE_OVERRUN = 2 -ibv_create_cq_attr_flags = ctypes.c_uint32 # enum -class struct_ibv_cq_init_attr_ex(Structure): - pass - -struct_ibv_cq_init_attr_ex._pack_ = 1 # source:False -struct_ibv_cq_init_attr_ex._fields_ = [ - ('cqe', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('cq_context', ctypes.POINTER(None)), - ('channel', ctypes.POINTER(struct_ibv_comp_channel)), - ('comp_vector', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('wc_flags', ctypes.c_uint64), - ('comp_mask', ctypes.c_uint32), - ('flags', ctypes.c_uint32), - ('parent_domain', ctypes.POINTER(struct_ibv_pd)), -] - - -# values for enumeration 'ibv_parent_domain_init_attr_mask' -ibv_parent_domain_init_attr_mask__enumvalues = { - 1: 'IBV_PARENT_DOMAIN_INIT_ATTR_ALLOCATORS', - 2: 'IBV_PARENT_DOMAIN_INIT_ATTR_PD_CONTEXT', -} -IBV_PARENT_DOMAIN_INIT_ATTR_ALLOCATORS = 1 -IBV_PARENT_DOMAIN_INIT_ATTR_PD_CONTEXT = 2 -ibv_parent_domain_init_attr_mask = ctypes.c_uint32 # enum -class struct_ibv_parent_domain_init_attr(Structure): - pass - -struct_ibv_parent_domain_init_attr._pack_ = 1 # source:False -struct_ibv_parent_domain_init_attr._fields_ = [ - ('pd', ctypes.POINTER(struct_ibv_pd)), - ('td', ctypes.POINTER(struct_ibv_td)), - ('comp_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('alloc', ctypes.CFUNCTYPE(ctypes.POINTER(None), ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(None), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint64)), - ('free', ctypes.CFUNCTYPE(None, ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(None), ctypes.POINTER(None), ctypes.c_uint64)), - ('pd_context', ctypes.POINTER(None)), -] - -class struct_ibv_counters_init_attr(Structure): - pass - -struct_ibv_counters_init_attr._pack_ = 1 # source:False -struct_ibv_counters_init_attr._fields_ = [ - ('comp_mask', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_counter_description' -ibv_counter_description__enumvalues = { - 0: 'IBV_COUNTER_PACKETS', - 1: 'IBV_COUNTER_BYTES', -} -IBV_COUNTER_PACKETS = 0 -IBV_COUNTER_BYTES = 1 -ibv_counter_description = ctypes.c_uint32 # enum -class struct_ibv_counter_attach_attr(Structure): - pass - -struct_ibv_counter_attach_attr._pack_ = 1 # source:False -struct_ibv_counter_attach_attr._fields_ = [ - ('counter_desc', ibv_counter_description), - ('index', ctypes.c_uint32), - ('comp_mask', ctypes.c_uint32), -] - - -# values for enumeration 'ibv_read_counters_flags' -ibv_read_counters_flags__enumvalues = { - 1: 'IBV_READ_COUNTERS_ATTR_PREFER_CACHED', -} -IBV_READ_COUNTERS_ATTR_PREFER_CACHED = 1 -ibv_read_counters_flags = ctypes.c_uint32 # enum - -# values for enumeration 'ibv_values_mask' -ibv_values_mask__enumvalues = { - 1: 'IBV_VALUES_MASK_RAW_CLOCK', - 2: 'IBV_VALUES_MASK_RESERVED', -} -IBV_VALUES_MASK_RAW_CLOCK = 1 -IBV_VALUES_MASK_RESERVED = 2 -ibv_values_mask = ctypes.c_uint32 # enum -class struct_ibv_values_ex(Structure): - pass - -class struct_timespec(Structure): - pass - -struct_timespec._pack_ = 1 # source:False -struct_timespec._fields_ = [ - ('tv_sec', ctypes.c_int64), - ('tv_nsec', ctypes.c_int64), -] - -struct_ibv_values_ex._pack_ = 1 # source:False -struct_ibv_values_ex._fields_ = [ - ('comp_mask', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('raw_clock', struct_timespec), -] - -class struct_verbs_context(Structure): - pass - -class struct_verbs_ex_private(Structure): - pass - -struct_verbs_context._pack_ = 1 # source:False -struct_verbs_context._fields_ = [ - ('query_port', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.c_ubyte, ctypes.POINTER(struct_ibv_port_attr), ctypes.c_uint64)), - ('advise_mr', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_pd), ib_uverbs_advise_mr_advice, ctypes.c_uint32, ctypes.POINTER(struct_ibv_sge), ctypes.c_uint32)), - ('alloc_null_mr', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_mr), ctypes.POINTER(struct_ibv_pd))), - ('read_counters', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(ctypes.c_uint64), ctypes.c_uint32, ctypes.c_uint32)), - ('attach_counters_point_flow', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(struct_ibv_counter_attach_attr), ctypes.POINTER(struct_ibv_flow))), - ('create_counters', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_counters_init_attr))), - ('destroy_counters', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_counters))), - ('reg_dm_mr', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_mr), ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_dm), ctypes.c_uint64, ctypes.c_uint64, ctypes.c_uint32)), - ('alloc_dm', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_dm), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_alloc_dm_attr))), - ('free_dm', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_dm))), - ('modify_flow_action_esp', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_flow_action), ctypes.POINTER(struct_ibv_flow_action_esp_attr))), - ('destroy_flow_action', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_flow_action))), - ('create_flow_action_esp', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_flow_action), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_flow_action_esp_attr))), - ('modify_qp_rate_limit', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_qp_rate_limit_attr))), - ('alloc_parent_domain', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_parent_domain_init_attr))), - ('dealloc_td', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_td))), - ('alloc_td', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_td), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_td_init_attr))), - ('modify_cq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_cq), ctypes.POINTER(struct_ibv_modify_cq_attr))), - ('post_srq_ops', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_ops_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_ops_wr)))), - ('destroy_rwq_ind_table', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_rwq_ind_table))), - ('create_rwq_ind_table', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_rwq_ind_table), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_rwq_ind_table_init_attr))), - ('destroy_wq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_wq))), - ('modify_wq', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_wq_attr))), - ('create_wq', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_wq_init_attr))), - ('query_rt_values', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_values_ex))), - ('create_cq_ex', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_cq_ex), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_cq_init_attr_ex))), - ('priv', ctypes.POINTER(struct_verbs_ex_private)), - ('query_device_ex', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_query_device_ex_input), ctypes.POINTER(struct_ibv_device_attr_ex), ctypes.c_uint64)), - ('ibv_destroy_flow', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_flow))), - ('ABI_placeholder2', ctypes.CFUNCTYPE(None)), - ('ibv_create_flow', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_flow), ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_flow_attr))), - ('ABI_placeholder1', ctypes.CFUNCTYPE(None)), - ('open_qp', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_qp_open_attr))), - ('create_qp_ex', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_qp_init_attr_ex))), - ('get_srq_num', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(ctypes.c_uint32))), - ('create_srq_ex', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_srq_init_attr_ex))), - ('open_xrcd', ctypes.CFUNCTYPE(ctypes.POINTER(struct_ibv_xrcd), ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_xrcd_init_attr))), - ('close_xrcd', ctypes.CFUNCTYPE(ctypes.c_int32, ctypes.POINTER(struct_ibv_xrcd))), - ('_ABI_placeholder3', ctypes.c_uint64), - ('sz', ctypes.c_uint64), - ('context', struct_ibv_context), -] - -try: - verbs_get_ctx = _libraries['libibverbs'].verbs_get_ctx - verbs_get_ctx.restype = ctypes.POINTER(struct_verbs_context) - verbs_get_ctx.argtypes = [ctypes.POINTER(struct_ibv_context)] -except AttributeError: - pass -# def verbs_get_ctx_op(ctx, op): # macro -# return ({struct_verbs_context*__vctx=verbs_get_ctx(ctx);(!__vctx or (__vctx->szop)?NULL:__vctx;}) -try: - ibv_get_device_list = _libraries['libibverbs'].ibv_get_device_list - ibv_get_device_list.restype = ctypes.POINTER(ctypes.POINTER(struct_ibv_device)) - ibv_get_device_list.argtypes = [ctypes.POINTER(ctypes.c_int32)] -except AttributeError: - pass -try: - ibv_free_device_list = _libraries['libibverbs'].ibv_free_device_list - ibv_free_device_list.restype = None - ibv_free_device_list.argtypes = [ctypes.POINTER(ctypes.POINTER(struct_ibv_device))] -except AttributeError: - pass -try: - ibv_get_device_name = _libraries['libibverbs'].ibv_get_device_name - ibv_get_device_name.restype = ctypes.POINTER(ctypes.c_char) - ibv_get_device_name.argtypes = [ctypes.POINTER(struct_ibv_device)] -except AttributeError: - pass -try: - ibv_get_device_index = _libraries['libibverbs'].ibv_get_device_index - ibv_get_device_index.restype = ctypes.c_int32 - ibv_get_device_index.argtypes = [ctypes.POINTER(struct_ibv_device)] -except AttributeError: - pass -__be64 = ctypes.c_uint64 -try: - ibv_get_device_guid = _libraries['libibverbs'].ibv_get_device_guid - ibv_get_device_guid.restype = __be64 - ibv_get_device_guid.argtypes = [ctypes.POINTER(struct_ibv_device)] -except AttributeError: - pass -try: - ibv_open_device = _libraries['libibverbs'].ibv_open_device - ibv_open_device.restype = ctypes.POINTER(struct_ibv_context) - ibv_open_device.argtypes = [ctypes.POINTER(struct_ibv_device)] -except AttributeError: - pass -try: - ibv_close_device = _libraries['libibverbs'].ibv_close_device - ibv_close_device.restype = ctypes.c_int32 - ibv_close_device.argtypes = [ctypes.POINTER(struct_ibv_context)] -except AttributeError: - pass -try: - ibv_import_device = _libraries['libibverbs'].ibv_import_device - ibv_import_device.restype = ctypes.POINTER(struct_ibv_context) - ibv_import_device.argtypes = [ctypes.c_int32] -except AttributeError: - pass -try: - ibv_import_pd = _libraries['libibverbs'].ibv_import_pd - ibv_import_pd.restype = ctypes.POINTER(struct_ibv_pd) - ibv_import_pd.argtypes = [ctypes.POINTER(struct_ibv_context), uint32_t] -except AttributeError: - pass -try: - ibv_unimport_pd = _libraries['libibverbs'].ibv_unimport_pd - ibv_unimport_pd.restype = None - ibv_unimport_pd.argtypes = [ctypes.POINTER(struct_ibv_pd)] -except AttributeError: - pass -try: - ibv_import_mr = _libraries['libibverbs'].ibv_import_mr - ibv_import_mr.restype = ctypes.POINTER(struct_ibv_mr) - ibv_import_mr.argtypes = [ctypes.POINTER(struct_ibv_pd), uint32_t] -except AttributeError: - pass -try: - ibv_unimport_mr = _libraries['libibverbs'].ibv_unimport_mr - ibv_unimport_mr.restype = None - ibv_unimport_mr.argtypes = [ctypes.POINTER(struct_ibv_mr)] -except AttributeError: - pass -try: - ibv_import_dm = _libraries['libibverbs'].ibv_import_dm - ibv_import_dm.restype = ctypes.POINTER(struct_ibv_dm) - ibv_import_dm.argtypes = [ctypes.POINTER(struct_ibv_context), uint32_t] -except AttributeError: - pass -try: - ibv_unimport_dm = _libraries['libibverbs'].ibv_unimport_dm - ibv_unimport_dm.restype = None - ibv_unimport_dm.argtypes = [ctypes.POINTER(struct_ibv_dm)] -except AttributeError: - pass -try: - ibv_get_async_event = _libraries['libibverbs'].ibv_get_async_event - ibv_get_async_event.restype = ctypes.c_int32 - ibv_get_async_event.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_async_event)] -except AttributeError: - pass -try: - ibv_ack_async_event = _libraries['libibverbs'].ibv_ack_async_event - ibv_ack_async_event.restype = None - ibv_ack_async_event.argtypes = [ctypes.POINTER(struct_ibv_async_event)] -except AttributeError: - pass -try: - ibv_query_device = _libraries['libibverbs'].ibv_query_device - ibv_query_device.restype = ctypes.c_int32 - ibv_query_device.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_device_attr)] -except AttributeError: - pass -try: - ___ibv_query_port = _libraries['libibverbs'].___ibv_query_port - ___ibv_query_port.restype = ctypes.c_int32 - ___ibv_query_port.argtypes = [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.POINTER(struct_ibv_port_attr)] -except AttributeError: - pass -def ibv_query_port(context, port_num, port_attr): # macro - return ___ibv_query_port(context,port_num,port_attr) -try: - ibv_query_gid = _libraries['libibverbs'].ibv_query_gid - ibv_query_gid.restype = ctypes.c_int32 - ibv_query_gid.argtypes = [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.c_int32, ctypes.POINTER(union_ibv_gid)] -except AttributeError: - pass -try: - _ibv_query_gid_ex = _libraries['libibverbs']._ibv_query_gid_ex - _ibv_query_gid_ex.restype = ctypes.c_int32 - _ibv_query_gid_ex.argtypes = [ctypes.POINTER(struct_ibv_context), uint32_t, uint32_t, ctypes.POINTER(struct_ibv_gid_entry), uint32_t, size_t] -except AttributeError: - pass -try: - ibv_query_gid_ex = _libraries['libibverbs'].ibv_query_gid_ex - ibv_query_gid_ex.restype = ctypes.c_int32 - ibv_query_gid_ex.argtypes = [ctypes.POINTER(struct_ibv_context), uint32_t, uint32_t, ctypes.POINTER(struct_ibv_gid_entry), uint32_t] -except AttributeError: - pass -ssize_t = ctypes.c_int64 -try: - _ibv_query_gid_table = _libraries['libibverbs']._ibv_query_gid_table - _ibv_query_gid_table.restype = ssize_t - _ibv_query_gid_table.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_gid_entry), size_t, uint32_t, size_t] -except AttributeError: - pass -try: - ibv_query_gid_table = _libraries['libibverbs'].ibv_query_gid_table - ibv_query_gid_table.restype = ssize_t - ibv_query_gid_table.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_gid_entry), size_t, uint32_t] -except AttributeError: - pass -try: - ibv_query_pkey = _libraries['libibverbs'].ibv_query_pkey - ibv_query_pkey.restype = ctypes.c_int32 - ibv_query_pkey.argtypes = [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.c_int32, ctypes.POINTER(ctypes.c_uint16)] -except AttributeError: - pass -__be16 = ctypes.c_uint16 -try: - ibv_get_pkey_index = _libraries['libibverbs'].ibv_get_pkey_index - ibv_get_pkey_index.restype = ctypes.c_int32 - ibv_get_pkey_index.argtypes = [ctypes.POINTER(struct_ibv_context), uint8_t, __be16] -except AttributeError: - pass -try: - ibv_alloc_pd = _libraries['libibverbs'].ibv_alloc_pd - ibv_alloc_pd.restype = ctypes.POINTER(struct_ibv_pd) - ibv_alloc_pd.argtypes = [ctypes.POINTER(struct_ibv_context)] -except AttributeError: - pass -try: - ibv_dealloc_pd = _libraries['libibverbs'].ibv_dealloc_pd - ibv_dealloc_pd.restype = ctypes.c_int32 - ibv_dealloc_pd.argtypes = [ctypes.POINTER(struct_ibv_pd)] -except AttributeError: - pass -try: - ibv_create_flow = _libraries['libibverbs'].ibv_create_flow - ibv_create_flow.restype = ctypes.POINTER(struct_ibv_flow) - ibv_create_flow.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_flow_attr)] -except AttributeError: - pass -try: - ibv_destroy_flow = _libraries['libibverbs'].ibv_destroy_flow - ibv_destroy_flow.restype = ctypes.c_int32 - ibv_destroy_flow.argtypes = [ctypes.POINTER(struct_ibv_flow)] -except AttributeError: - pass -try: - ibv_create_flow_action_esp = _libraries['libibverbs'].ibv_create_flow_action_esp - ibv_create_flow_action_esp.restype = ctypes.POINTER(struct_ibv_flow_action) - ibv_create_flow_action_esp.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_flow_action_esp_attr)] -except AttributeError: - pass -try: - ibv_modify_flow_action_esp = _libraries['libibverbs'].ibv_modify_flow_action_esp - ibv_modify_flow_action_esp.restype = ctypes.c_int32 - ibv_modify_flow_action_esp.argtypes = [ctypes.POINTER(struct_ibv_flow_action), ctypes.POINTER(struct_ibv_flow_action_esp_attr)] -except AttributeError: - pass -try: - ibv_destroy_flow_action = _libraries['libibverbs'].ibv_destroy_flow_action - ibv_destroy_flow_action.restype = ctypes.c_int32 - ibv_destroy_flow_action.argtypes = [ctypes.POINTER(struct_ibv_flow_action)] -except AttributeError: - pass -try: - ibv_open_xrcd = _libraries['libibverbs'].ibv_open_xrcd - ibv_open_xrcd.restype = ctypes.POINTER(struct_ibv_xrcd) - ibv_open_xrcd.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_xrcd_init_attr)] -except AttributeError: - pass -try: - ibv_close_xrcd = _libraries['libibverbs'].ibv_close_xrcd - ibv_close_xrcd.restype = ctypes.c_int32 - ibv_close_xrcd.argtypes = [ctypes.POINTER(struct_ibv_xrcd)] -except AttributeError: - pass -try: - ibv_reg_mr_iova2 = _libraries['libibverbs'].ibv_reg_mr_iova2 - ibv_reg_mr_iova2.restype = ctypes.POINTER(struct_ibv_mr) - ibv_reg_mr_iova2.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(None), size_t, uint64_t, ctypes.c_uint32] -except AttributeError: - pass -try: - __ibv_reg_mr = _libraries['libibverbs'].__ibv_reg_mr - __ibv_reg_mr.restype = ctypes.POINTER(struct_ibv_mr) - __ibv_reg_mr.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(None), size_t, ctypes.c_uint32, ctypes.c_int32] -except AttributeError: - pass -# def ibv_reg_mr(pd, addr, length, access): # macro -# return __ibv_reg_mr(pd,addr,length,access,__builtin_constant_p(((access)&IB_UVERBS_ACCESS_OPTIONAL_RANGE)==0)) -try: - __ibv_reg_mr_iova = _libraries['libibverbs'].__ibv_reg_mr_iova - __ibv_reg_mr_iova.restype = ctypes.POINTER(struct_ibv_mr) - __ibv_reg_mr_iova.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(None), size_t, uint64_t, ctypes.c_uint32, ctypes.c_int32] -except AttributeError: - pass -# def ibv_reg_mr_iova(pd, addr, length, iova, access): # macro -# return __ibv_reg_mr_iova(pd,addr,length,iova,access,__builtin_constant_p(((access)&IB_UVERBS_ACCESS_OPTIONAL_RANGE)==0)) -try: - ibv_reg_dmabuf_mr = _libraries['libibverbs'].ibv_reg_dmabuf_mr - ibv_reg_dmabuf_mr.restype = ctypes.POINTER(struct_ibv_mr) - ibv_reg_dmabuf_mr.argtypes = [ctypes.POINTER(struct_ibv_pd), uint64_t, size_t, uint64_t, ctypes.c_int32, ctypes.c_int32] -except AttributeError: - pass - -# values for enumeration 'ibv_rereg_mr_err_code' -ibv_rereg_mr_err_code__enumvalues = { - -1: 'IBV_REREG_MR_ERR_INPUT', - -2: 'IBV_REREG_MR_ERR_DONT_FORK_NEW', - -3: 'IBV_REREG_MR_ERR_DO_FORK_OLD', - -4: 'IBV_REREG_MR_ERR_CMD', - -5: 'IBV_REREG_MR_ERR_CMD_AND_DO_FORK_NEW', -} -IBV_REREG_MR_ERR_INPUT = -1 -IBV_REREG_MR_ERR_DONT_FORK_NEW = -2 -IBV_REREG_MR_ERR_DO_FORK_OLD = -3 -IBV_REREG_MR_ERR_CMD = -4 -IBV_REREG_MR_ERR_CMD_AND_DO_FORK_NEW = -5 -ibv_rereg_mr_err_code = ctypes.c_int32 # enum -try: - ibv_rereg_mr = _libraries['libibverbs'].ibv_rereg_mr - ibv_rereg_mr.restype = ctypes.c_int32 - ibv_rereg_mr.argtypes = [ctypes.POINTER(struct_ibv_mr), ctypes.c_int32, ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(None), size_t, ctypes.c_int32] -except AttributeError: - pass -try: - ibv_dereg_mr = _libraries['libibverbs'].ibv_dereg_mr - ibv_dereg_mr.restype = ctypes.c_int32 - ibv_dereg_mr.argtypes = [ctypes.POINTER(struct_ibv_mr)] -except AttributeError: - pass -try: - ibv_alloc_mw = _libraries['libibverbs'].ibv_alloc_mw - ibv_alloc_mw.restype = ctypes.POINTER(struct_ibv_mw) - ibv_alloc_mw.argtypes = [ctypes.POINTER(struct_ibv_pd), ibv_mw_type] -except AttributeError: - pass -try: - ibv_dealloc_mw = _libraries['libibverbs'].ibv_dealloc_mw - ibv_dealloc_mw.restype = ctypes.c_int32 - ibv_dealloc_mw.argtypes = [ctypes.POINTER(struct_ibv_mw)] -except AttributeError: - pass -try: - ibv_inc_rkey = _libraries['libibverbs'].ibv_inc_rkey - ibv_inc_rkey.restype = uint32_t - ibv_inc_rkey.argtypes = [uint32_t] -except AttributeError: - pass -try: - ibv_bind_mw = _libraries['libibverbs'].ibv_bind_mw - ibv_bind_mw.restype = ctypes.c_int32 - ibv_bind_mw.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_mw), ctypes.POINTER(struct_ibv_mw_bind)] -except AttributeError: - pass -try: - ibv_create_comp_channel = _libraries['libibverbs'].ibv_create_comp_channel - ibv_create_comp_channel.restype = ctypes.POINTER(struct_ibv_comp_channel) - ibv_create_comp_channel.argtypes = [ctypes.POINTER(struct_ibv_context)] -except AttributeError: - pass -try: - ibv_destroy_comp_channel = _libraries['libibverbs'].ibv_destroy_comp_channel - ibv_destroy_comp_channel.restype = ctypes.c_int32 - ibv_destroy_comp_channel.argtypes = [ctypes.POINTER(struct_ibv_comp_channel)] -except AttributeError: - pass -try: - ibv_advise_mr = _libraries['libibverbs'].ibv_advise_mr - ibv_advise_mr.restype = ctypes.c_int32 - ibv_advise_mr.argtypes = [ctypes.POINTER(struct_ibv_pd), ib_uverbs_advise_mr_advice, uint32_t, ctypes.POINTER(struct_ibv_sge), uint32_t] -except AttributeError: - pass -try: - ibv_alloc_dm = _libraries['libibverbs'].ibv_alloc_dm - ibv_alloc_dm.restype = ctypes.POINTER(struct_ibv_dm) - ibv_alloc_dm.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_alloc_dm_attr)] -except AttributeError: - pass -try: - ibv_free_dm = _libraries['libibverbs'].ibv_free_dm - ibv_free_dm.restype = ctypes.c_int32 - ibv_free_dm.argtypes = [ctypes.POINTER(struct_ibv_dm)] -except AttributeError: - pass -try: - ibv_memcpy_to_dm = _libraries['libibverbs'].ibv_memcpy_to_dm - ibv_memcpy_to_dm.restype = ctypes.c_int32 - ibv_memcpy_to_dm.argtypes = [ctypes.POINTER(struct_ibv_dm), uint64_t, ctypes.POINTER(None), size_t] -except AttributeError: - pass -try: - ibv_memcpy_from_dm = _libraries['libibverbs'].ibv_memcpy_from_dm - ibv_memcpy_from_dm.restype = ctypes.c_int32 - ibv_memcpy_from_dm.argtypes = [ctypes.POINTER(None), ctypes.POINTER(struct_ibv_dm), uint64_t, size_t] -except AttributeError: - pass -try: - ibv_alloc_null_mr = _libraries['libibverbs'].ibv_alloc_null_mr - ibv_alloc_null_mr.restype = ctypes.POINTER(struct_ibv_mr) - ibv_alloc_null_mr.argtypes = [ctypes.POINTER(struct_ibv_pd)] -except AttributeError: - pass -try: - ibv_reg_dm_mr = _libraries['libibverbs'].ibv_reg_dm_mr - ibv_reg_dm_mr.restype = ctypes.POINTER(struct_ibv_mr) - ibv_reg_dm_mr.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_dm), uint64_t, size_t, ctypes.c_uint32] -except AttributeError: - pass -try: - ibv_create_cq = _libraries['libibverbs'].ibv_create_cq - ibv_create_cq.restype = ctypes.POINTER(struct_ibv_cq) - ibv_create_cq.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.c_int32, ctypes.POINTER(None), ctypes.POINTER(struct_ibv_comp_channel), ctypes.c_int32] -except AttributeError: - pass -try: - ibv_create_cq_ex = _libraries['libibverbs'].ibv_create_cq_ex - ibv_create_cq_ex.restype = ctypes.POINTER(struct_ibv_cq_ex) - ibv_create_cq_ex.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_cq_init_attr_ex)] -except AttributeError: - pass -try: - ibv_resize_cq = _libraries['libibverbs'].ibv_resize_cq - ibv_resize_cq.restype = ctypes.c_int32 - ibv_resize_cq.argtypes = [ctypes.POINTER(struct_ibv_cq), ctypes.c_int32] -except AttributeError: - pass -try: - ibv_destroy_cq = _libraries['libibverbs'].ibv_destroy_cq - ibv_destroy_cq.restype = ctypes.c_int32 - ibv_destroy_cq.argtypes = [ctypes.POINTER(struct_ibv_cq)] -except AttributeError: - pass -try: - ibv_get_cq_event = _libraries['libibverbs'].ibv_get_cq_event - ibv_get_cq_event.restype = ctypes.c_int32 - ibv_get_cq_event.argtypes = [ctypes.POINTER(struct_ibv_comp_channel), ctypes.POINTER(ctypes.POINTER(struct_ibv_cq)), ctypes.POINTER(ctypes.POINTER(None))] -except AttributeError: - pass -try: - ibv_ack_cq_events = _libraries['libibverbs'].ibv_ack_cq_events - ibv_ack_cq_events.restype = None - ibv_ack_cq_events.argtypes = [ctypes.POINTER(struct_ibv_cq), ctypes.c_uint32] -except AttributeError: - pass -try: - ibv_poll_cq = _libraries['libibverbs'].ibv_poll_cq - ibv_poll_cq.restype = ctypes.c_int32 - ibv_poll_cq.argtypes = [ctypes.POINTER(struct_ibv_cq), ctypes.c_int32, ctypes.POINTER(struct_ibv_wc)] -except AttributeError: - pass -try: - ibv_req_notify_cq = _libraries['libibverbs'].ibv_req_notify_cq - ibv_req_notify_cq.restype = ctypes.c_int32 - ibv_req_notify_cq.argtypes = [ctypes.POINTER(struct_ibv_cq), ctypes.c_int32] -except AttributeError: - pass -try: - ibv_modify_cq = _libraries['libibverbs'].ibv_modify_cq - ibv_modify_cq.restype = ctypes.c_int32 - ibv_modify_cq.argtypes = [ctypes.POINTER(struct_ibv_cq), ctypes.POINTER(struct_ibv_modify_cq_attr)] -except AttributeError: - pass -try: - ibv_create_srq = _libraries['libibverbs'].ibv_create_srq - ibv_create_srq.restype = ctypes.POINTER(struct_ibv_srq) - ibv_create_srq.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_srq_init_attr)] -except AttributeError: - pass -try: - ibv_create_srq_ex = _libraries['libibverbs'].ibv_create_srq_ex - ibv_create_srq_ex.restype = ctypes.POINTER(struct_ibv_srq) - ibv_create_srq_ex.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_srq_init_attr_ex)] -except AttributeError: - pass -try: - ibv_modify_srq = _libraries['libibverbs'].ibv_modify_srq - ibv_modify_srq.restype = ctypes.c_int32 - ibv_modify_srq.argtypes = [ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_srq_attr), ctypes.c_int32] -except AttributeError: - pass -try: - ibv_query_srq = _libraries['libibverbs'].ibv_query_srq - ibv_query_srq.restype = ctypes.c_int32 - ibv_query_srq.argtypes = [ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_srq_attr)] -except AttributeError: - pass -try: - ibv_get_srq_num = _libraries['libibverbs'].ibv_get_srq_num - ibv_get_srq_num.restype = ctypes.c_int32 - ibv_get_srq_num.argtypes = [ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(ctypes.c_uint32)] -except AttributeError: - pass -try: - ibv_destroy_srq = _libraries['libibverbs'].ibv_destroy_srq - ibv_destroy_srq.restype = ctypes.c_int32 - ibv_destroy_srq.argtypes = [ctypes.POINTER(struct_ibv_srq)] -except AttributeError: - pass -try: - ibv_post_srq_recv = _libraries['libibverbs'].ibv_post_srq_recv - ibv_post_srq_recv.restype = ctypes.c_int32 - ibv_post_srq_recv.argtypes = [ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr))] -except AttributeError: - pass -try: - ibv_post_srq_ops = _libraries['libibverbs'].ibv_post_srq_ops - ibv_post_srq_ops.restype = ctypes.c_int32 - ibv_post_srq_ops.argtypes = [ctypes.POINTER(struct_ibv_srq), ctypes.POINTER(struct_ibv_ops_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_ops_wr))] -except AttributeError: - pass -try: - ibv_create_qp = _libraries['libibverbs'].ibv_create_qp - ibv_create_qp.restype = ctypes.POINTER(struct_ibv_qp) - ibv_create_qp.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_qp_init_attr)] -except AttributeError: - pass -try: - ibv_create_qp_ex = _libraries['libibverbs'].ibv_create_qp_ex - ibv_create_qp_ex.restype = ctypes.POINTER(struct_ibv_qp) - ibv_create_qp_ex.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_qp_init_attr_ex)] -except AttributeError: - pass -try: - ibv_alloc_td = _libraries['libibverbs'].ibv_alloc_td - ibv_alloc_td.restype = ctypes.POINTER(struct_ibv_td) - ibv_alloc_td.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_td_init_attr)] -except AttributeError: - pass -try: - ibv_dealloc_td = _libraries['libibverbs'].ibv_dealloc_td - ibv_dealloc_td.restype = ctypes.c_int32 - ibv_dealloc_td.argtypes = [ctypes.POINTER(struct_ibv_td)] -except AttributeError: - pass -try: - ibv_alloc_parent_domain = _libraries['libibverbs'].ibv_alloc_parent_domain - ibv_alloc_parent_domain.restype = ctypes.POINTER(struct_ibv_pd) - ibv_alloc_parent_domain.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_parent_domain_init_attr)] -except AttributeError: - pass -try: - ibv_query_rt_values_ex = _libraries['libibverbs'].ibv_query_rt_values_ex - ibv_query_rt_values_ex.restype = ctypes.c_int32 - ibv_query_rt_values_ex.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_values_ex)] -except AttributeError: - pass -try: - ibv_query_device_ex = _libraries['libibverbs'].ibv_query_device_ex - ibv_query_device_ex.restype = ctypes.c_int32 - ibv_query_device_ex.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_query_device_ex_input), ctypes.POINTER(struct_ibv_device_attr_ex)] -except AttributeError: - pass -try: - ibv_open_qp = _libraries['libibverbs'].ibv_open_qp - ibv_open_qp.restype = ctypes.POINTER(struct_ibv_qp) - ibv_open_qp.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_qp_open_attr)] -except AttributeError: - pass -try: - ibv_modify_qp = _libraries['libibverbs'].ibv_modify_qp - ibv_modify_qp.restype = ctypes.c_int32 - ibv_modify_qp.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_qp_attr), ctypes.c_int32] -except AttributeError: - pass -try: - ibv_modify_qp_rate_limit = _libraries['libibverbs'].ibv_modify_qp_rate_limit - ibv_modify_qp_rate_limit.restype = ctypes.c_int32 - ibv_modify_qp_rate_limit.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_qp_rate_limit_attr)] -except AttributeError: - pass -try: - ibv_query_qp_data_in_order = _libraries['libibverbs'].ibv_query_qp_data_in_order - ibv_query_qp_data_in_order.restype = ctypes.c_int32 - ibv_query_qp_data_in_order.argtypes = [ctypes.POINTER(struct_ibv_qp), ibv_wr_opcode, uint32_t] -except AttributeError: - pass -try: - ibv_query_qp = _libraries['libibverbs'].ibv_query_qp - ibv_query_qp.restype = ctypes.c_int32 - ibv_query_qp.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_qp_attr), ctypes.c_int32, ctypes.POINTER(struct_ibv_qp_init_attr)] -except AttributeError: - pass -try: - ibv_destroy_qp = _libraries['libibverbs'].ibv_destroy_qp - ibv_destroy_qp.restype = ctypes.c_int32 - ibv_destroy_qp.argtypes = [ctypes.POINTER(struct_ibv_qp)] -except AttributeError: - pass -try: - ibv_create_wq = _libraries['libibverbs'].ibv_create_wq - ibv_create_wq.restype = ctypes.POINTER(struct_ibv_wq) - ibv_create_wq.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_wq_init_attr)] -except AttributeError: - pass -try: - ibv_modify_wq = _libraries['libibverbs'].ibv_modify_wq - ibv_modify_wq.restype = ctypes.c_int32 - ibv_modify_wq.argtypes = [ctypes.POINTER(struct_ibv_wq), ctypes.POINTER(struct_ibv_wq_attr)] -except AttributeError: - pass -try: - ibv_destroy_wq = _libraries['libibverbs'].ibv_destroy_wq - ibv_destroy_wq.restype = ctypes.c_int32 - ibv_destroy_wq.argtypes = [ctypes.POINTER(struct_ibv_wq)] -except AttributeError: - pass -try: - ibv_create_rwq_ind_table = _libraries['libibverbs'].ibv_create_rwq_ind_table - ibv_create_rwq_ind_table.restype = ctypes.POINTER(struct_ibv_rwq_ind_table) - ibv_create_rwq_ind_table.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_rwq_ind_table_init_attr)] -except AttributeError: - pass -try: - ibv_destroy_rwq_ind_table = _libraries['libibverbs'].ibv_destroy_rwq_ind_table - ibv_destroy_rwq_ind_table.restype = ctypes.c_int32 - ibv_destroy_rwq_ind_table.argtypes = [ctypes.POINTER(struct_ibv_rwq_ind_table)] -except AttributeError: - pass -try: - ibv_post_send = _libraries['libibverbs'].ibv_post_send - ibv_post_send.restype = ctypes.c_int32 - ibv_post_send.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_send_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_send_wr))] -except AttributeError: - pass -try: - ibv_post_recv = _libraries['libibverbs'].ibv_post_recv - ibv_post_recv.restype = ctypes.c_int32 - ibv_post_recv.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_recv_wr), ctypes.POINTER(ctypes.POINTER(struct_ibv_recv_wr))] -except AttributeError: - pass -try: - ibv_create_ah = _libraries['libibverbs'].ibv_create_ah - ibv_create_ah.restype = ctypes.POINTER(struct_ibv_ah) - ibv_create_ah.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_ah_attr)] -except AttributeError: - pass -try: - ibv_init_ah_from_wc = _libraries['libibverbs'].ibv_init_ah_from_wc - ibv_init_ah_from_wc.restype = ctypes.c_int32 - ibv_init_ah_from_wc.argtypes = [ctypes.POINTER(struct_ibv_context), uint8_t, ctypes.POINTER(struct_ibv_wc), ctypes.POINTER(struct_ibv_grh), ctypes.POINTER(struct_ibv_ah_attr)] -except AttributeError: - pass -try: - ibv_create_ah_from_wc = _libraries['libibverbs'].ibv_create_ah_from_wc - ibv_create_ah_from_wc.restype = ctypes.POINTER(struct_ibv_ah) - ibv_create_ah_from_wc.argtypes = [ctypes.POINTER(struct_ibv_pd), ctypes.POINTER(struct_ibv_wc), ctypes.POINTER(struct_ibv_grh), uint8_t] -except AttributeError: - pass -try: - ibv_destroy_ah = _libraries['libibverbs'].ibv_destroy_ah - ibv_destroy_ah.restype = ctypes.c_int32 - ibv_destroy_ah.argtypes = [ctypes.POINTER(struct_ibv_ah)] -except AttributeError: - pass -try: - ibv_attach_mcast = _libraries['libibverbs'].ibv_attach_mcast - ibv_attach_mcast.restype = ctypes.c_int32 - ibv_attach_mcast.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(union_ibv_gid), uint16_t] -except AttributeError: - pass -try: - ibv_detach_mcast = _libraries['libibverbs'].ibv_detach_mcast - ibv_detach_mcast.restype = ctypes.c_int32 - ibv_detach_mcast.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(union_ibv_gid), uint16_t] -except AttributeError: - pass -try: - ibv_fork_init = _libraries['libibverbs'].ibv_fork_init - ibv_fork_init.restype = ctypes.c_int32 - ibv_fork_init.argtypes = [] -except AttributeError: - pass -try: - ibv_is_fork_initialized = _libraries['libibverbs'].ibv_is_fork_initialized - ibv_is_fork_initialized.restype = ibv_fork_status - ibv_is_fork_initialized.argtypes = [] -except AttributeError: - pass -try: - ibv_node_type_str = _libraries['libibverbs'].ibv_node_type_str - ibv_node_type_str.restype = ctypes.POINTER(ctypes.c_char) - ibv_node_type_str.argtypes = [ibv_node_type] -except AttributeError: - pass -try: - ibv_port_state_str = _libraries['libibverbs'].ibv_port_state_str - ibv_port_state_str.restype = ctypes.POINTER(ctypes.c_char) - ibv_port_state_str.argtypes = [ibv_port_state] -except AttributeError: - pass -try: - ibv_event_type_str = _libraries['libibverbs'].ibv_event_type_str - ibv_event_type_str.restype = ctypes.POINTER(ctypes.c_char) - ibv_event_type_str.argtypes = [ibv_event_type] -except AttributeError: - pass -try: - ibv_resolve_eth_l2_from_gid = _libraries['libibverbs'].ibv_resolve_eth_l2_from_gid - ibv_resolve_eth_l2_from_gid.restype = ctypes.c_int32 - ibv_resolve_eth_l2_from_gid.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_ah_attr), ctypes.c_ubyte * 6, ctypes.POINTER(ctypes.c_uint16)] -except AttributeError: - pass -try: - ibv_is_qpt_supported = _libraries['libibverbs'].ibv_is_qpt_supported - ibv_is_qpt_supported.restype = ctypes.c_int32 - ibv_is_qpt_supported.argtypes = [uint32_t, ibv_qp_type] -except AttributeError: - pass -try: - ibv_create_counters = _libraries['libibverbs'].ibv_create_counters - ibv_create_counters.restype = ctypes.POINTER(struct_ibv_counters) - ibv_create_counters.argtypes = [ctypes.POINTER(struct_ibv_context), ctypes.POINTER(struct_ibv_counters_init_attr)] -except AttributeError: - pass -try: - ibv_destroy_counters = _libraries['libibverbs'].ibv_destroy_counters - ibv_destroy_counters.restype = ctypes.c_int32 - ibv_destroy_counters.argtypes = [ctypes.POINTER(struct_ibv_counters)] -except AttributeError: - pass -try: - ibv_attach_counters_point_flow = _libraries['libibverbs'].ibv_attach_counters_point_flow - ibv_attach_counters_point_flow.restype = ctypes.c_int32 - ibv_attach_counters_point_flow.argtypes = [ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(struct_ibv_counter_attach_attr), ctypes.POINTER(struct_ibv_flow)] -except AttributeError: - pass -try: - ibv_read_counters = _libraries['libibverbs'].ibv_read_counters - ibv_read_counters.restype = ctypes.c_int32 - ibv_read_counters.argtypes = [ctypes.POINTER(struct_ibv_counters), ctypes.POINTER(ctypes.c_uint64), uint32_t, uint32_t] -except AttributeError: - pass -try: - ibv_flow_label_to_udp_sport = _libraries['libibverbs'].ibv_flow_label_to_udp_sport - ibv_flow_label_to_udp_sport.restype = uint16_t - ibv_flow_label_to_udp_sport.argtypes = [uint32_t] -except AttributeError: - pass -try: - ibv_set_ece = _libraries['libibverbs'].ibv_set_ece - ibv_set_ece.restype = ctypes.c_int32 - ibv_set_ece.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_ece)] -except AttributeError: - pass -try: - ibv_query_ece = _libraries['libibverbs'].ibv_query_ece - ibv_query_ece.restype = ctypes.c_int32 - ibv_query_ece.argtypes = [ctypes.POINTER(struct_ibv_qp), ctypes.POINTER(struct_ibv_ece)] -except AttributeError: - pass -__all__ = \ - ['ETHERNET_LL_SIZE', 'IBV_ACCESS_FLUSH_GLOBAL', - 'IBV_ACCESS_FLUSH_PERSISTENT', 'IBV_ACCESS_HUGETLB', - 'IBV_ACCESS_LOCAL_WRITE', 'IBV_ACCESS_MW_BIND', - 'IBV_ACCESS_ON_DEMAND', 'IBV_ACCESS_OPTIONAL_FIRST', - 'IBV_ACCESS_OPTIONAL_RANGE', 'IBV_ACCESS_RELAXED_ORDERING', - 'IBV_ACCESS_REMOTE_ATOMIC', 'IBV_ACCESS_REMOTE_READ', - 'IBV_ACCESS_REMOTE_WRITE', 'IBV_ACCESS_ZERO_BASED', - 'IBV_ADVISE_MR_ADVICE_PREFETCH', - 'IBV_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT', - 'IBV_ADVISE_MR_ADVICE_PREFETCH_WRITE', 'IBV_ADVISE_MR_FLAG_FLUSH', - 'IBV_ATOMIC_GLOB', 'IBV_ATOMIC_HCA', 'IBV_ATOMIC_NONE', - 'IBV_COUNTER_BYTES', 'IBV_COUNTER_PACKETS', - 'IBV_CQ_ATTR_MODERATE', 'IBV_CQ_ATTR_RESERVED', - 'IBV_CQ_INIT_ATTR_MASK_FLAGS', 'IBV_CQ_INIT_ATTR_MASK_PD', - 'IBV_CREATE_CQ_ATTR_IGNORE_OVERRUN', - 'IBV_CREATE_CQ_ATTR_SINGLE_THREADED', - 'IBV_CREATE_CQ_SUP_WC_FLAGS', 'IBV_CREATE_IND_TABLE_RESERVED', - 'IBV_DEVICE_AUTO_PATH_MIG', 'IBV_DEVICE_BAD_PKEY_CNTR', - 'IBV_DEVICE_BAD_QKEY_CNTR', 'IBV_DEVICE_CHANGE_PHY_PORT', - 'IBV_DEVICE_CURR_QP_STATE_MOD', 'IBV_DEVICE_INIT_TYPE', - 'IBV_DEVICE_MANAGED_FLOW_STEERING', - 'IBV_DEVICE_MEM_MGT_EXTENSIONS', 'IBV_DEVICE_MEM_WINDOW', - 'IBV_DEVICE_MEM_WINDOW_TYPE_2A', 'IBV_DEVICE_MEM_WINDOW_TYPE_2B', - 'IBV_DEVICE_N_NOTIFY_CQ', 'IBV_DEVICE_PCI_WRITE_END_PADDING', - 'IBV_DEVICE_PORT_ACTIVE_EVENT', 'IBV_DEVICE_RAW_IP_CSUM', - 'IBV_DEVICE_RAW_MULTI', 'IBV_DEVICE_RAW_SCATTER_FCS', - 'IBV_DEVICE_RC_IP_CSUM', 'IBV_DEVICE_RC_RNR_NAK_GEN', - 'IBV_DEVICE_RESIZE_MAX_WR', 'IBV_DEVICE_SHUTDOWN_PORT', - 'IBV_DEVICE_SRQ_RESIZE', 'IBV_DEVICE_SYS_IMAGE_GUID', - 'IBV_DEVICE_UD_AV_PORT_ENFORCE', 'IBV_DEVICE_UD_IP_CSUM', - 'IBV_DEVICE_XRC', 'IBV_DM_MASK_HANDLE', - 'IBV_EVENT_CLIENT_REREGISTER', 'IBV_EVENT_COMM_EST', - 'IBV_EVENT_CQ_ERR', 'IBV_EVENT_DEVICE_FATAL', - 'IBV_EVENT_GID_CHANGE', 'IBV_EVENT_LID_CHANGE', - 'IBV_EVENT_PATH_MIG', 'IBV_EVENT_PATH_MIG_ERR', - 'IBV_EVENT_PKEY_CHANGE', 'IBV_EVENT_PORT_ACTIVE', - 'IBV_EVENT_PORT_ERR', 'IBV_EVENT_QP_ACCESS_ERR', - 'IBV_EVENT_QP_FATAL', 'IBV_EVENT_QP_LAST_WQE_REACHED', - 'IBV_EVENT_QP_REQ_ERR', 'IBV_EVENT_SM_CHANGE', - 'IBV_EVENT_SQ_DRAINED', 'IBV_EVENT_SRQ_ERR', - 'IBV_EVENT_SRQ_LIMIT_REACHED', 'IBV_EVENT_WQ_FATAL', - 'IBV_FLOW_ACTION_ESP_FLAGS_DECRYPT', - 'IBV_FLOW_ACTION_ESP_FLAGS_ENCRYPT', - 'IBV_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW', - 'IBV_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD', - 'IBV_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO', - 'IBV_FLOW_ACTION_ESP_FLAGS_TRANSPORT', - 'IBV_FLOW_ACTION_ESP_FLAGS_TUNNEL', - 'IBV_FLOW_ACTION_ESP_KEYMAT_AES_GCM', - 'IBV_FLOW_ACTION_ESP_MASK_ESN', 'IBV_FLOW_ACTION_ESP_REPLAY_BMP', - 'IBV_FLOW_ACTION_ESP_REPLAY_NONE', 'IBV_FLOW_ACTION_IV_ALGO_SEQ', - 'IBV_FLOW_ATTR_ALL_DEFAULT', 'IBV_FLOW_ATTR_FLAGS_DONT_TRAP', - 'IBV_FLOW_ATTR_FLAGS_EGRESS', 'IBV_FLOW_ATTR_MC_DEFAULT', - 'IBV_FLOW_ATTR_NORMAL', 'IBV_FLOW_ATTR_SNIFFER', - 'IBV_FLOW_SPEC_ACTION_COUNT', 'IBV_FLOW_SPEC_ACTION_DROP', - 'IBV_FLOW_SPEC_ACTION_HANDLE', 'IBV_FLOW_SPEC_ACTION_TAG', - 'IBV_FLOW_SPEC_ESP', 'IBV_FLOW_SPEC_ETH', 'IBV_FLOW_SPEC_GRE', - 'IBV_FLOW_SPEC_INNER', 'IBV_FLOW_SPEC_IPV4', - 'IBV_FLOW_SPEC_IPV4_EXT', 'IBV_FLOW_SPEC_IPV6', - 'IBV_FLOW_SPEC_MPLS', 'IBV_FLOW_SPEC_TCP', 'IBV_FLOW_SPEC_UDP', - 'IBV_FLOW_SPEC_VXLAN_TUNNEL', 'IBV_FLUSH_GLOBAL', 'IBV_FLUSH_MR', - 'IBV_FLUSH_PERSISTENT', 'IBV_FLUSH_RANGE', 'IBV_FORK_DISABLED', - 'IBV_FORK_ENABLED', 'IBV_FORK_UNNEEDED', 'IBV_GID_TYPE_IB', - 'IBV_GID_TYPE_ROCE_V1', 'IBV_GID_TYPE_ROCE_V2', - 'IBV_LINK_LAYER_ETHERNET', 'IBV_LINK_LAYER_INFINIBAND', - 'IBV_LINK_LAYER_UNSPECIFIED', 'IBV_MIG_ARMED', 'IBV_MIG_MIGRATED', - 'IBV_MIG_REARM', 'IBV_MTU_1024', 'IBV_MTU_2048', 'IBV_MTU_256', - 'IBV_MTU_4096', 'IBV_MTU_512', 'IBV_MW_TYPE_1', 'IBV_MW_TYPE_2', - 'IBV_NODE_CA', 'IBV_NODE_RNIC', 'IBV_NODE_ROUTER', - 'IBV_NODE_SWITCH', 'IBV_NODE_UNKNOWN', 'IBV_NODE_UNSPECIFIED', - 'IBV_NODE_USNIC', 'IBV_NODE_USNIC_UDP', 'IBV_ODP_SUPPORT', - 'IBV_ODP_SUPPORT_ATOMIC', 'IBV_ODP_SUPPORT_IMPLICIT', - 'IBV_ODP_SUPPORT_READ', 'IBV_ODP_SUPPORT_RECV', - 'IBV_ODP_SUPPORT_SEND', 'IBV_ODP_SUPPORT_SRQ_RECV', - 'IBV_ODP_SUPPORT_WRITE', 'IBV_OPS_SIGNALED', 'IBV_OPS_TM_SYNC', - 'IBV_PARENT_DOMAIN_INIT_ATTR_ALLOCATORS', - 'IBV_PARENT_DOMAIN_INIT_ATTR_PD_CONTEXT', - 'IBV_PCI_ATOMIC_OPERATION_16_BYTE_SIZE_SUP', - 'IBV_PCI_ATOMIC_OPERATION_4_BYTE_SIZE_SUP', - 'IBV_PCI_ATOMIC_OPERATION_8_BYTE_SIZE_SUP', 'IBV_PORT_ACTIVE', - 'IBV_PORT_ACTIVE_DEFER', 'IBV_PORT_ARMED', - 'IBV_PORT_AUTO_MIGR_SUP', 'IBV_PORT_BOOT_MGMT_SUP', - 'IBV_PORT_CAP_MASK2_SUP', 'IBV_PORT_CAP_MASK_NOTICE_SUP', - 'IBV_PORT_CLIENT_REG_SUP', 'IBV_PORT_CM_SUP', - 'IBV_PORT_DEVICE_MGMT_SUP', 'IBV_PORT_DOWN', - 'IBV_PORT_DR_NOTICE_SUP', 'IBV_PORT_EXTENDED_SPEEDS_SUP', - 'IBV_PORT_INFO_EXT_SUP', 'IBV_PORT_INIT', - 'IBV_PORT_IP_BASED_GIDS', 'IBV_PORT_LED_INFO_SUP', - 'IBV_PORT_LINK_LATENCY_SUP', 'IBV_PORT_LINK_SPEED_HDR_SUP', - 'IBV_PORT_LINK_SPEED_NDR_SUP', 'IBV_PORT_LINK_SPEED_XDR_SUP', - 'IBV_PORT_LINK_WIDTH_2X_SUP', 'IBV_PORT_MKEY_NVRAM', - 'IBV_PORT_NOP', 'IBV_PORT_NOTICE_SUP', 'IBV_PORT_OPT_IPD_SUP', - 'IBV_PORT_PKEY_NVRAM', 'IBV_PORT_PKEY_SW_EXT_PORT_TRAP_SUP', - 'IBV_PORT_REINIT_SUP', 'IBV_PORT_SET_NODE_DESC_SUP', - 'IBV_PORT_SL_MAP_SUP', 'IBV_PORT_SM', 'IBV_PORT_SNMP_TUNNEL_SUP', - 'IBV_PORT_SWITCH_PORT_STATE_TABLE_SUP', - 'IBV_PORT_SYS_IMAGE_GUID_SUP', 'IBV_PORT_TRAP_SUP', - 'IBV_PORT_VENDOR_CLASS_SUP', 'IBV_PORT_VIRT_SUP', - 'IBV_QPF_GRH_REQUIRED', 'IBV_QPS_ERR', 'IBV_QPS_INIT', - 'IBV_QPS_RESET', 'IBV_QPS_RTR', 'IBV_QPS_RTS', 'IBV_QPS_SQD', - 'IBV_QPS_SQE', 'IBV_QPS_UNKNOWN', 'IBV_QPT_DRIVER', - 'IBV_QPT_RAW_PACKET', 'IBV_QPT_RC', 'IBV_QPT_UC', 'IBV_QPT_UD', - 'IBV_QPT_XRC_RECV', 'IBV_QPT_XRC_SEND', 'IBV_QP_ACCESS_FLAGS', - 'IBV_QP_ALT_PATH', 'IBV_QP_AV', 'IBV_QP_CAP', - 'IBV_QP_CREATE_BLOCK_SELF_MCAST_LB', - 'IBV_QP_CREATE_CVLAN_STRIPPING', - 'IBV_QP_CREATE_PCI_WRITE_END_PADDING', - 'IBV_QP_CREATE_SCATTER_FCS', 'IBV_QP_CREATE_SOURCE_QPN', - 'IBV_QP_CUR_STATE', 'IBV_QP_DEST_QPN', - 'IBV_QP_EN_SQD_ASYNC_NOTIFY', 'IBV_QP_EX_WITH_ATOMIC_CMP_AND_SWP', - 'IBV_QP_EX_WITH_ATOMIC_FETCH_AND_ADD', - 'IBV_QP_EX_WITH_ATOMIC_WRITE', 'IBV_QP_EX_WITH_BIND_MW', - 'IBV_QP_EX_WITH_FLUSH', 'IBV_QP_EX_WITH_LOCAL_INV', - 'IBV_QP_EX_WITH_RDMA_READ', 'IBV_QP_EX_WITH_RDMA_WRITE', - 'IBV_QP_EX_WITH_RDMA_WRITE_WITH_IMM', 'IBV_QP_EX_WITH_SEND', - 'IBV_QP_EX_WITH_SEND_WITH_IMM', 'IBV_QP_EX_WITH_SEND_WITH_INV', - 'IBV_QP_EX_WITH_TSO', 'IBV_QP_INIT_ATTR_CREATE_FLAGS', - 'IBV_QP_INIT_ATTR_IND_TABLE', 'IBV_QP_INIT_ATTR_MAX_TSO_HEADER', - 'IBV_QP_INIT_ATTR_PD', 'IBV_QP_INIT_ATTR_RX_HASH', - 'IBV_QP_INIT_ATTR_SEND_OPS_FLAGS', 'IBV_QP_INIT_ATTR_XRCD', - 'IBV_QP_MAX_DEST_RD_ATOMIC', 'IBV_QP_MAX_QP_RD_ATOMIC', - 'IBV_QP_MIN_RNR_TIMER', 'IBV_QP_OPEN_ATTR_CONTEXT', - 'IBV_QP_OPEN_ATTR_NUM', 'IBV_QP_OPEN_ATTR_RESERVED', - 'IBV_QP_OPEN_ATTR_TYPE', 'IBV_QP_OPEN_ATTR_XRCD', - 'IBV_QP_PATH_MIG_STATE', 'IBV_QP_PATH_MTU', 'IBV_QP_PKEY_INDEX', - 'IBV_QP_PORT', 'IBV_QP_QKEY', 'IBV_QP_RATE_LIMIT', - 'IBV_QP_RETRY_CNT', 'IBV_QP_RNR_RETRY', 'IBV_QP_RQ_PSN', - 'IBV_QP_SQ_PSN', 'IBV_QP_STATE', 'IBV_QP_TIMEOUT', - 'IBV_QUERY_QP_DATA_IN_ORDER_ALIGNED_128_BYTES', - 'IBV_QUERY_QP_DATA_IN_ORDER_RETURN_CAPS', - 'IBV_QUERY_QP_DATA_IN_ORDER_WHOLE_MSG', 'IBV_RATE_100_GBPS', - 'IBV_RATE_10_GBPS', 'IBV_RATE_112_GBPS', 'IBV_RATE_1200_GBPS', - 'IBV_RATE_120_GBPS', 'IBV_RATE_14_GBPS', 'IBV_RATE_168_GBPS', - 'IBV_RATE_200_GBPS', 'IBV_RATE_20_GBPS', 'IBV_RATE_25_GBPS', - 'IBV_RATE_28_GBPS', 'IBV_RATE_2_5_GBPS', 'IBV_RATE_300_GBPS', - 'IBV_RATE_30_GBPS', 'IBV_RATE_400_GBPS', 'IBV_RATE_40_GBPS', - 'IBV_RATE_50_GBPS', 'IBV_RATE_56_GBPS', 'IBV_RATE_5_GBPS', - 'IBV_RATE_600_GBPS', 'IBV_RATE_60_GBPS', 'IBV_RATE_800_GBPS', - 'IBV_RATE_80_GBPS', 'IBV_RATE_MAX', - 'IBV_RAW_PACKET_CAP_CVLAN_STRIPPING', - 'IBV_RAW_PACKET_CAP_DELAY_DROP', 'IBV_RAW_PACKET_CAP_IP_CSUM', - 'IBV_RAW_PACKET_CAP_SCATTER_FCS', - 'IBV_READ_COUNTERS_ATTR_PREFER_CACHED', - 'IBV_REREG_MR_CHANGE_ACCESS', 'IBV_REREG_MR_CHANGE_PD', - 'IBV_REREG_MR_CHANGE_TRANSLATION', 'IBV_REREG_MR_ERR_CMD', - 'IBV_REREG_MR_ERR_CMD_AND_DO_FORK_NEW', - 'IBV_REREG_MR_ERR_DONT_FORK_NEW', 'IBV_REREG_MR_ERR_DO_FORK_OLD', - 'IBV_REREG_MR_ERR_INPUT', 'IBV_REREG_MR_FLAGS_SUPPORTED', - 'IBV_RX_HASH_DST_IPV4', 'IBV_RX_HASH_DST_IPV6', - 'IBV_RX_HASH_DST_PORT_TCP', 'IBV_RX_HASH_DST_PORT_UDP', - 'IBV_RX_HASH_FUNC_TOEPLITZ', 'IBV_RX_HASH_INNER', - 'IBV_RX_HASH_IPSEC_SPI', 'IBV_RX_HASH_SRC_IPV4', - 'IBV_RX_HASH_SRC_IPV6', 'IBV_RX_HASH_SRC_PORT_TCP', - 'IBV_RX_HASH_SRC_PORT_UDP', 'IBV_SEND_FENCE', 'IBV_SEND_INLINE', - 'IBV_SEND_IP_CSUM', 'IBV_SEND_SIGNALED', 'IBV_SEND_SOLICITED', - 'IBV_SRQT_BASIC', 'IBV_SRQT_TM', 'IBV_SRQT_XRC', - 'IBV_SRQ_INIT_ATTR_CQ', 'IBV_SRQ_INIT_ATTR_PD', - 'IBV_SRQ_INIT_ATTR_RESERVED', 'IBV_SRQ_INIT_ATTR_TM', - 'IBV_SRQ_INIT_ATTR_TYPE', 'IBV_SRQ_INIT_ATTR_XRCD', - 'IBV_SRQ_LIMIT', 'IBV_SRQ_MAX_WR', 'IBV_SYSFS_NAME_MAX', - 'IBV_SYSFS_PATH_MAX', 'IBV_TM_CAP_RC', 'IBV_TRANSPORT_IB', - 'IBV_TRANSPORT_IWARP', 'IBV_TRANSPORT_UNKNOWN', - 'IBV_TRANSPORT_UNSPECIFIED', 'IBV_TRANSPORT_USNIC', - 'IBV_TRANSPORT_USNIC_UDP', 'IBV_VALUES_MASK_RAW_CLOCK', - 'IBV_VALUES_MASK_RESERVED', 'IBV_WC_ATOMIC_WRITE', - 'IBV_WC_BAD_RESP_ERR', 'IBV_WC_BIND_MW', 'IBV_WC_COMP_SWAP', - 'IBV_WC_DRIVER1', 'IBV_WC_DRIVER2', 'IBV_WC_DRIVER3', - 'IBV_WC_EX_WITH_BYTE_LEN', 'IBV_WC_EX_WITH_COMPLETION_TIMESTAMP', - 'IBV_WC_EX_WITH_COMPLETION_TIMESTAMP_WALLCLOCK', - 'IBV_WC_EX_WITH_CVLAN', 'IBV_WC_EX_WITH_DLID_PATH_BITS', - 'IBV_WC_EX_WITH_FLOW_TAG', 'IBV_WC_EX_WITH_IMM', - 'IBV_WC_EX_WITH_QP_NUM', 'IBV_WC_EX_WITH_SL', - 'IBV_WC_EX_WITH_SLID', 'IBV_WC_EX_WITH_SRC_QP', - 'IBV_WC_EX_WITH_TM_INFO', 'IBV_WC_FATAL_ERR', 'IBV_WC_FETCH_ADD', - 'IBV_WC_FLUSH', 'IBV_WC_GENERAL_ERR', 'IBV_WC_GRH', - 'IBV_WC_INV_EECN_ERR', 'IBV_WC_INV_EEC_STATE_ERR', - 'IBV_WC_IP_CSUM_OK', 'IBV_WC_IP_CSUM_OK_SHIFT', - 'IBV_WC_LOCAL_INV', 'IBV_WC_LOC_ACCESS_ERR', - 'IBV_WC_LOC_EEC_OP_ERR', 'IBV_WC_LOC_LEN_ERR', - 'IBV_WC_LOC_PROT_ERR', 'IBV_WC_LOC_QP_OP_ERR', - 'IBV_WC_LOC_RDD_VIOL_ERR', 'IBV_WC_MW_BIND_ERR', - 'IBV_WC_RDMA_READ', 'IBV_WC_RDMA_WRITE', 'IBV_WC_RECV', - 'IBV_WC_RECV_RDMA_WITH_IMM', 'IBV_WC_REM_ABORT_ERR', - 'IBV_WC_REM_ACCESS_ERR', 'IBV_WC_REM_INV_RD_REQ_ERR', - 'IBV_WC_REM_INV_REQ_ERR', 'IBV_WC_REM_OP_ERR', - 'IBV_WC_RESP_TIMEOUT_ERR', 'IBV_WC_RETRY_EXC_ERR', - 'IBV_WC_RNR_RETRY_EXC_ERR', 'IBV_WC_SEND', - 'IBV_WC_STANDARD_FLAGS', 'IBV_WC_SUCCESS', 'IBV_WC_TM_ADD', - 'IBV_WC_TM_DATA_VALID', 'IBV_WC_TM_DEL', 'IBV_WC_TM_ERR', - 'IBV_WC_TM_MATCH', 'IBV_WC_TM_NO_TAG', 'IBV_WC_TM_RECV', - 'IBV_WC_TM_RNDV_INCOMPLETE', 'IBV_WC_TM_SYNC', - 'IBV_WC_TM_SYNC_REQ', 'IBV_WC_TSO', 'IBV_WC_WITH_IMM', - 'IBV_WC_WITH_INV', 'IBV_WC_WR_FLUSH_ERR', 'IBV_WQS_ERR', - 'IBV_WQS_RDY', 'IBV_WQS_RESET', 'IBV_WQS_UNKNOWN', 'IBV_WQT_RQ', - 'IBV_WQ_ATTR_CURR_STATE', 'IBV_WQ_ATTR_FLAGS', - 'IBV_WQ_ATTR_RESERVED', 'IBV_WQ_ATTR_STATE', - 'IBV_WQ_FLAGS_CVLAN_STRIPPING', 'IBV_WQ_FLAGS_DELAY_DROP', - 'IBV_WQ_FLAGS_PCI_WRITE_END_PADDING', 'IBV_WQ_FLAGS_RESERVED', - 'IBV_WQ_FLAGS_SCATTER_FCS', 'IBV_WQ_INIT_ATTR_FLAGS', - 'IBV_WQ_INIT_ATTR_RESERVED', 'IBV_WR_ATOMIC_CMP_AND_SWP', - 'IBV_WR_ATOMIC_FETCH_AND_ADD', 'IBV_WR_ATOMIC_WRITE', - 'IBV_WR_BIND_MW', 'IBV_WR_DRIVER1', 'IBV_WR_FLUSH', - 'IBV_WR_LOCAL_INV', 'IBV_WR_RDMA_READ', 'IBV_WR_RDMA_WRITE', - 'IBV_WR_RDMA_WRITE_WITH_IMM', 'IBV_WR_SEND', - 'IBV_WR_SEND_WITH_IMM', 'IBV_WR_SEND_WITH_INV', 'IBV_WR_TAG_ADD', - 'IBV_WR_TAG_DEL', 'IBV_WR_TAG_SYNC', 'IBV_WR_TSO', - 'IBV_XRCD_INIT_ATTR_FD', 'IBV_XRCD_INIT_ATTR_OFLAGS', - 'IBV_XRCD_INIT_ATTR_RESERVED', 'IB_DEVICE_NAME_MAX', - 'IB_FLUSH_GLOBAL', 'IB_FLUSH_MR', 'IB_FLUSH_PERSISTENT', - 'IB_FLUSH_RANGE', 'IB_GRH_FLOWLABEL_MASK', - 'IB_ROCE_UDP_ENCAP_VALID_PORT_MAX', - 'IB_ROCE_UDP_ENCAP_VALID_PORT_MIN', 'IB_USER_IOCTL_VERBS_H', - 'IB_USER_VERBS_ABI_VERSION', 'IB_USER_VERBS_CMD_ALLOC_MW', - 'IB_USER_VERBS_CMD_ALLOC_PD', 'IB_USER_VERBS_CMD_ATTACH_MCAST', - 'IB_USER_VERBS_CMD_BIND_MW', 'IB_USER_VERBS_CMD_CLOSE_XRCD', - 'IB_USER_VERBS_CMD_COMMAND_MASK', 'IB_USER_VERBS_CMD_CREATE_AH', - 'IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL', - 'IB_USER_VERBS_CMD_CREATE_CQ', 'IB_USER_VERBS_CMD_CREATE_QP', - 'IB_USER_VERBS_CMD_CREATE_SRQ', 'IB_USER_VERBS_CMD_CREATE_XSRQ', - 'IB_USER_VERBS_CMD_DEALLOC_MW', 'IB_USER_VERBS_CMD_DEALLOC_PD', - 'IB_USER_VERBS_CMD_DEREG_MR', 'IB_USER_VERBS_CMD_DESTROY_AH', - 'IB_USER_VERBS_CMD_DESTROY_CQ', 'IB_USER_VERBS_CMD_DESTROY_QP', - 'IB_USER_VERBS_CMD_DESTROY_SRQ', 'IB_USER_VERBS_CMD_DETACH_MCAST', - 'IB_USER_VERBS_CMD_FLAG_EXTENDED', - 'IB_USER_VERBS_CMD_GET_CONTEXT', 'IB_USER_VERBS_CMD_MODIFY_AH', - 'IB_USER_VERBS_CMD_MODIFY_QP', 'IB_USER_VERBS_CMD_MODIFY_SRQ', - 'IB_USER_VERBS_CMD_OPEN_QP', 'IB_USER_VERBS_CMD_OPEN_XRCD', - 'IB_USER_VERBS_CMD_PEEK_CQ', 'IB_USER_VERBS_CMD_POLL_CQ', - 'IB_USER_VERBS_CMD_POST_RECV', 'IB_USER_VERBS_CMD_POST_SEND', - 'IB_USER_VERBS_CMD_POST_SRQ_RECV', 'IB_USER_VERBS_CMD_QUERY_AH', - 'IB_USER_VERBS_CMD_QUERY_DEVICE', 'IB_USER_VERBS_CMD_QUERY_MR', - 'IB_USER_VERBS_CMD_QUERY_PORT', 'IB_USER_VERBS_CMD_QUERY_QP', - 'IB_USER_VERBS_CMD_QUERY_SRQ', 'IB_USER_VERBS_CMD_REG_MR', - 'IB_USER_VERBS_CMD_REG_SMR', 'IB_USER_VERBS_CMD_REQ_NOTIFY_CQ', - 'IB_USER_VERBS_CMD_REREG_MR', 'IB_USER_VERBS_CMD_RESIZE_CQ', - 'IB_USER_VERBS_CMD_THRESHOLD', 'IB_USER_VERBS_EX_CMD_CREATE_CQ', - 'IB_USER_VERBS_EX_CMD_CREATE_FLOW', - 'IB_USER_VERBS_EX_CMD_CREATE_QP', - 'IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL', - 'IB_USER_VERBS_EX_CMD_CREATE_WQ', - 'IB_USER_VERBS_EX_CMD_DESTROY_FLOW', - 'IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL', - 'IB_USER_VERBS_EX_CMD_DESTROY_WQ', - 'IB_USER_VERBS_EX_CMD_MODIFY_CQ', - 'IB_USER_VERBS_EX_CMD_MODIFY_QP', - 'IB_USER_VERBS_EX_CMD_MODIFY_WQ', - 'IB_USER_VERBS_EX_CMD_QUERY_DEVICE', 'IB_USER_VERBS_H', - 'IB_USER_VERBS_MAX_LOG_IND_TBL_SIZE', - 'IB_UVERBS_ACCESS_FLUSH_GLOBAL', - 'IB_UVERBS_ACCESS_FLUSH_PERSISTENT', 'IB_UVERBS_ACCESS_HUGETLB', - 'IB_UVERBS_ACCESS_LOCAL_WRITE', 'IB_UVERBS_ACCESS_MW_BIND', - 'IB_UVERBS_ACCESS_ON_DEMAND', 'IB_UVERBS_ACCESS_OPTIONAL_FIRST', - 'IB_UVERBS_ACCESS_OPTIONAL_LAST', - 'IB_UVERBS_ACCESS_OPTIONAL_RANGE', - 'IB_UVERBS_ACCESS_RELAXED_ORDERING', - 'IB_UVERBS_ACCESS_REMOTE_ATOMIC', 'IB_UVERBS_ACCESS_REMOTE_READ', - 'IB_UVERBS_ACCESS_REMOTE_WRITE', 'IB_UVERBS_ACCESS_ZERO_BASED', - 'IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH', - 'IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_NO_FAULT', - 'IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE', - 'IB_UVERBS_ADVISE_MR_FLAG_FLUSH', - 'IB_UVERBS_CORE_SUPPORT_OPTIONAL_MR_ACCESS', - 'IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN', - 'IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION', - 'IB_UVERBS_CREATE_QP_MASK_IND_TABLE', - 'IB_UVERBS_CREATE_QP_SUP_COMP_MASK', - 'IB_UVERBS_DEVICE_ATOMIC_WRITE', 'IB_UVERBS_DEVICE_AUTO_PATH_MIG', - 'IB_UVERBS_DEVICE_BAD_PKEY_CNTR', - 'IB_UVERBS_DEVICE_BAD_QKEY_CNTR', - 'IB_UVERBS_DEVICE_CHANGE_PHY_PORT', - 'IB_UVERBS_DEVICE_CURR_QP_STATE_MOD', - 'IB_UVERBS_DEVICE_FLUSH_GLOBAL', - 'IB_UVERBS_DEVICE_FLUSH_PERSISTENT', - 'IB_UVERBS_DEVICE_MANAGED_FLOW_STEERING', - 'IB_UVERBS_DEVICE_MEM_MGT_EXTENSIONS', - 'IB_UVERBS_DEVICE_MEM_WINDOW', - 'IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2A', - 'IB_UVERBS_DEVICE_MEM_WINDOW_TYPE_2B', - 'IB_UVERBS_DEVICE_N_NOTIFY_CQ', - 'IB_UVERBS_DEVICE_PCI_WRITE_END_PADDING', - 'IB_UVERBS_DEVICE_PORT_ACTIVE_EVENT', - 'IB_UVERBS_DEVICE_RAW_IP_CSUM', 'IB_UVERBS_DEVICE_RAW_MULTI', - 'IB_UVERBS_DEVICE_RAW_SCATTER_FCS', 'IB_UVERBS_DEVICE_RC_IP_CSUM', - 'IB_UVERBS_DEVICE_RC_RNR_NAK_GEN', - 'IB_UVERBS_DEVICE_RESIZE_MAX_WR', - 'IB_UVERBS_DEVICE_SHUTDOWN_PORT', 'IB_UVERBS_DEVICE_SRQ_RESIZE', - 'IB_UVERBS_DEVICE_SYS_IMAGE_GUID', - 'IB_UVERBS_DEVICE_UD_AV_PORT_ENFORCE', - 'IB_UVERBS_DEVICE_UD_IP_CSUM', 'IB_UVERBS_DEVICE_XRC', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT', - 'IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL', - 'IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM', - 'IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP', - 'IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE', - 'IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ', 'IB_UVERBS_GID_TYPE_IB', - 'IB_UVERBS_GID_TYPE_ROCE_V1', 'IB_UVERBS_GID_TYPE_ROCE_V2', - 'IB_UVERBS_PCF_AUTO_MIGR_SUP', 'IB_UVERBS_PCF_BOOT_MGMT_SUP', - 'IB_UVERBS_PCF_CAP_MASK_NOTICE_SUP', - 'IB_UVERBS_PCF_CLIENT_REG_SUP', 'IB_UVERBS_PCF_CM_SUP', - 'IB_UVERBS_PCF_DEVICE_MGMT_SUP', 'IB_UVERBS_PCF_DR_NOTICE_SUP', - 'IB_UVERBS_PCF_EXTENDED_SPEEDS_SUP', - 'IB_UVERBS_PCF_HIERARCHY_INFO_SUP', 'IB_UVERBS_PCF_IP_BASED_GIDS', - 'IB_UVERBS_PCF_LED_INFO_SUP', 'IB_UVERBS_PCF_LINK_LATENCY_SUP', - 'IB_UVERBS_PCF_LINK_SPEED_WIDTH_TABLE_SUP', - 'IB_UVERBS_PCF_MCAST_FDB_TOP_SUP', - 'IB_UVERBS_PCF_MCAST_PKEY_TRAP_SUPPRESSION_SUP', - 'IB_UVERBS_PCF_MKEY_NVRAM', 'IB_UVERBS_PCF_NOTICE_SUP', - 'IB_UVERBS_PCF_OPT_IPD_SUP', 'IB_UVERBS_PCF_PKEY_NVRAM', - 'IB_UVERBS_PCF_PKEY_SW_EXT_PORT_TRAP_SUP', - 'IB_UVERBS_PCF_REINIT_SUP', 'IB_UVERBS_PCF_SL_MAP_SUP', - 'IB_UVERBS_PCF_SM', 'IB_UVERBS_PCF_SM_DISABLED', - 'IB_UVERBS_PCF_SNMP_TUNNEL_SUP', - 'IB_UVERBS_PCF_SYS_IMAGE_GUID_SUP', 'IB_UVERBS_PCF_TRAP_SUP', - 'IB_UVERBS_PCF_VENDOR_CLASS_SUP', - 'IB_UVERBS_PCF_VENDOR_SPECIFIC_MADS_TABLE_SUP', - 'IB_UVERBS_QPF_GRH_REQUIRED', 'IB_UVERBS_QPT_DRIVER', - 'IB_UVERBS_QPT_RAW_PACKET', 'IB_UVERBS_QPT_RC', - 'IB_UVERBS_QPT_UC', 'IB_UVERBS_QPT_UD', 'IB_UVERBS_QPT_XRC_INI', - 'IB_UVERBS_QPT_XRC_TGT', - 'IB_UVERBS_QP_CREATE_BLOCK_MULTICAST_LOOPBACK', - 'IB_UVERBS_QP_CREATE_CVLAN_STRIPPING', - 'IB_UVERBS_QP_CREATE_PCI_WRITE_END_PADDING', - 'IB_UVERBS_QP_CREATE_SCATTER_FCS', - 'IB_UVERBS_QP_CREATE_SQ_SIG_ALL', - 'IB_UVERBS_RAW_PACKET_CAP_CVLAN_STRIPPING', - 'IB_UVERBS_RAW_PACKET_CAP_DELAY_DROP', - 'IB_UVERBS_RAW_PACKET_CAP_IP_CSUM', - 'IB_UVERBS_RAW_PACKET_CAP_SCATTER_FCS', - 'IB_UVERBS_READ_COUNTERS_PREFER_CACHED', 'IB_UVERBS_SRQT_BASIC', - 'IB_UVERBS_SRQT_TM', 'IB_UVERBS_SRQT_XRC', - 'IB_UVERBS_WC_ATOMIC_WRITE', 'IB_UVERBS_WC_BIND_MW', - 'IB_UVERBS_WC_COMP_SWAP', 'IB_UVERBS_WC_FETCH_ADD', - 'IB_UVERBS_WC_FLUSH', 'IB_UVERBS_WC_LOCAL_INV', - 'IB_UVERBS_WC_RDMA_READ', 'IB_UVERBS_WC_RDMA_WRITE', - 'IB_UVERBS_WC_SEND', 'IB_UVERBS_WC_TSO', 'IB_UVERBS_WQT_RQ', - 'IB_UVERBS_WQ_FLAGS_CVLAN_STRIPPING', - 'IB_UVERBS_WQ_FLAGS_DELAY_DROP', - 'IB_UVERBS_WQ_FLAGS_PCI_WRITE_END_PADDING', - 'IB_UVERBS_WQ_FLAGS_SCATTER_FCS', - 'IB_UVERBS_WR_ATOMIC_CMP_AND_SWP', - 'IB_UVERBS_WR_ATOMIC_FETCH_AND_ADD', 'IB_UVERBS_WR_ATOMIC_WRITE', - 'IB_UVERBS_WR_BIND_MW', 'IB_UVERBS_WR_FLUSH', - 'IB_UVERBS_WR_LOCAL_INV', - 'IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP', - 'IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD', - 'IB_UVERBS_WR_RDMA_READ', 'IB_UVERBS_WR_RDMA_READ_WITH_INV', - 'IB_UVERBS_WR_RDMA_WRITE', 'IB_UVERBS_WR_RDMA_WRITE_WITH_IMM', - 'IB_UVERBS_WR_SEND', 'IB_UVERBS_WR_SEND_WITH_IMM', - 'IB_UVERBS_WR_SEND_WITH_INV', 'IB_UVERBS_WR_TSO', - 'INFINIBAND_VERBS_H', 'RDMA_DRIVER_BNXT_RE', 'RDMA_DRIVER_CXGB3', - 'RDMA_DRIVER_CXGB4', 'RDMA_DRIVER_EFA', 'RDMA_DRIVER_ERDMA', - 'RDMA_DRIVER_HFI1', 'RDMA_DRIVER_HNS', 'RDMA_DRIVER_I40IW', - 'RDMA_DRIVER_IRDMA', 'RDMA_DRIVER_MANA', 'RDMA_DRIVER_MLX4', - 'RDMA_DRIVER_MLX5', 'RDMA_DRIVER_MTHCA', 'RDMA_DRIVER_NES', - 'RDMA_DRIVER_OCRDMA', 'RDMA_DRIVER_QEDR', 'RDMA_DRIVER_QIB', - 'RDMA_DRIVER_RXE', 'RDMA_DRIVER_SIW', 'RDMA_DRIVER_UNKNOWN', - 'RDMA_DRIVER_USNIC', 'RDMA_DRIVER_VMW_PVRDMA', 'VERBS_API_H', - '___ibv_query_port', '__attribute_const', '__be16', '__be32', - '__be64', '__ibv_reg_mr', '__ibv_reg_mr_iova', - '_ibv_query_gid_ex', '_ibv_query_gid_table', - 'c__Ea_IBV_CREATE_CQ_SUP_WC_FLAGS', - 'c__Ea_IBV_LINK_LAYER_UNSPECIFIED', 'c__Ea_IBV_SYSFS_NAME_MAX', - 'c__Ea_IBV_WC_IP_CSUM_OK_SHIFT', 'c__Ea_IBV_WC_STANDARD_FLAGS', - 'c__Ea_IB_USER_VERBS_EX_CMD_QUERY_DEVICE', - 'c__Ea_IB_UVERBS_CREATE_QP_SUP_COMP_MASK', 'ib_placement_type', - 'ib_selectivity_level', 'ib_uverbs_access_flags', - 'ib_uverbs_advise_mr_advice', 'ib_uverbs_advise_mr_flag', - 'ib_uverbs_core_support', 'ib_uverbs_create_qp_mask', - 'ib_uverbs_device_cap_flags', 'ib_uverbs_ex_create_cq_flags', - 'ib_uverbs_flow_action_esp_flags', - 'ib_uverbs_flow_action_esp_keymat', - 'ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo', - 'ib_uverbs_flow_action_esp_replay', 'ib_uverbs_gid_type', - 'ib_uverbs_qp_create_flags', 'ib_uverbs_qp_type', - 'ib_uverbs_query_port_cap_flags', 'ib_uverbs_query_port_flags', - 'ib_uverbs_raw_packet_caps', 'ib_uverbs_read_counters_flags', - 'ib_uverbs_srq_type', 'ib_uverbs_wc_opcode', 'ib_uverbs_wq_flags', - 'ib_uverbs_wq_type', 'ib_uverbs_wr_opcode', - 'ib_uverbs_write_cmds', 'ibv_access_flags', 'ibv_ack_async_event', - 'ibv_ack_cq_events', 'ibv_advise_mr', 'ibv_advise_mr_advice', - 'ibv_alloc_dm', 'ibv_alloc_mw', 'ibv_alloc_null_mr', - 'ibv_alloc_parent_domain', 'ibv_alloc_pd', 'ibv_alloc_td', - 'ibv_atomic_cap', 'ibv_attach_counters_point_flow', - 'ibv_attach_mcast', 'ibv_bind_mw', 'ibv_close_device', - 'ibv_close_xrcd', 'ibv_counter_description', 'ibv_cq_attr_mask', - 'ibv_cq_ex_to_cq', 'ibv_cq_init_attr_mask', 'ibv_create_ah', - 'ibv_create_ah_from_wc', 'ibv_create_comp_channel', - 'ibv_create_counters', 'ibv_create_cq', - 'ibv_create_cq_attr_flags', 'ibv_create_cq_ex', - 'ibv_create_cq_wc_flags', 'ibv_create_flow', - 'ibv_create_flow_action_esp', 'ibv_create_qp', 'ibv_create_qp_ex', - 'ibv_create_rwq_ind_table', 'ibv_create_srq', 'ibv_create_srq_ex', - 'ibv_create_wq', 'ibv_dealloc_mw', 'ibv_dealloc_pd', - 'ibv_dealloc_td', 'ibv_dereg_mr', 'ibv_destroy_ah', - 'ibv_destroy_comp_channel', 'ibv_destroy_counters', - 'ibv_destroy_cq', 'ibv_destroy_flow', 'ibv_destroy_flow_action', - 'ibv_destroy_qp', 'ibv_destroy_rwq_ind_table', 'ibv_destroy_srq', - 'ibv_destroy_wq', 'ibv_detach_mcast', 'ibv_device_cap_flags', - 'ibv_dm_mask', 'ibv_end_poll', 'ibv_event_type', - 'ibv_event_type_str', 'ibv_flow_action_esp_flags', - 'ibv_flow_action_esp_keymat', - 'ibv_flow_action_esp_keymat_aes_gcm_iv_algo', - 'ibv_flow_action_esp_mask', 'ibv_flow_action_esp_replay', - 'ibv_flow_attr_type', 'ibv_flow_flags', - 'ibv_flow_label_to_udp_sport', 'ibv_flow_spec_type', - 'ibv_fork_init', 'ibv_fork_status', 'ibv_free_device_list', - 'ibv_free_dm', 'ibv_get_async_event', 'ibv_get_cq_event', - 'ibv_get_device_guid', 'ibv_get_device_index', - 'ibv_get_device_list', 'ibv_get_device_name', - 'ibv_get_pkey_index', 'ibv_get_srq_num', 'ibv_gid_type', - 'ibv_import_device', 'ibv_import_dm', 'ibv_import_mr', - 'ibv_import_pd', 'ibv_inc_rkey', 'ibv_ind_table_init_attr_mask', - 'ibv_init_ah_from_wc', 'ibv_is_fork_initialized', - 'ibv_is_qpt_supported', 'ibv_memcpy_from_dm', 'ibv_memcpy_to_dm', - 'ibv_mig_state', 'ibv_modify_cq', 'ibv_modify_flow_action_esp', - 'ibv_modify_qp', 'ibv_modify_qp_rate_limit', 'ibv_modify_srq', - 'ibv_modify_wq', 'ibv_mtu', 'ibv_mw_type', 'ibv_next_poll', - 'ibv_node_type', 'ibv_node_type_str', 'ibv_odp_general_caps', - 'ibv_odp_transport_cap_bits', 'ibv_open_device', 'ibv_open_qp', - 'ibv_open_xrcd', 'ibv_ops_flags', 'ibv_ops_wr_opcode', - 'ibv_parent_domain_init_attr_mask', 'ibv_pci_atomic_op_size', - 'ibv_placement_type', 'ibv_poll_cq', 'ibv_port_cap_flags', - 'ibv_port_cap_flags2', 'ibv_port_state', 'ibv_port_state_str', - 'ibv_post_recv', 'ibv_post_send', 'ibv_post_srq_ops', - 'ibv_post_srq_recv', 'ibv_post_wq_recv', 'ibv_qp_attr_mask', - 'ibv_qp_create_flags', 'ibv_qp_create_send_ops_flags', - 'ibv_qp_init_attr_mask', 'ibv_qp_open_attr_mask', 'ibv_qp_state', - 'ibv_qp_to_qp_ex', 'ibv_qp_type', 'ibv_query_device', - 'ibv_query_device_ex', 'ibv_query_ece', 'ibv_query_gid', - 'ibv_query_gid_ex', 'ibv_query_gid_table', 'ibv_query_pkey', - 'ibv_query_qp', 'ibv_query_qp_data_in_order', - 'ibv_query_qp_data_in_order_caps', - 'ibv_query_qp_data_in_order_flags', 'ibv_query_rt_values_ex', - 'ibv_query_srq', 'ibv_rate', 'ibv_rate_to_mbps', - 'ibv_rate_to_mult', 'ibv_raw_packet_caps', 'ibv_read_counters', - 'ibv_read_counters_flags', 'ibv_reg_dm_mr', 'ibv_reg_dmabuf_mr', - 'ibv_reg_mr_iova2', 'ibv_req_notify_cq', 'ibv_rereg_mr', - 'ibv_rereg_mr_err_code', 'ibv_rereg_mr_flags', 'ibv_resize_cq', - 'ibv_resolve_eth_l2_from_gid', 'ibv_rx_hash_fields', - 'ibv_rx_hash_function_flags', 'ibv_selectivity_level', - 'ibv_send_flags', 'ibv_set_ece', 'ibv_srq_attr_mask', - 'ibv_srq_init_attr_mask', 'ibv_srq_type', 'ibv_start_poll', - 'ibv_tm_cap_flags', 'ibv_transport_type', 'ibv_unimport_dm', - 'ibv_unimport_mr', 'ibv_unimport_pd', 'ibv_values_mask', - 'ibv_wc_flags', 'ibv_wc_opcode', 'ibv_wc_read_byte_len', - 'ibv_wc_read_completion_ts', - 'ibv_wc_read_completion_wallclock_ns', 'ibv_wc_read_cvlan', - 'ibv_wc_read_dlid_path_bits', 'ibv_wc_read_flow_tag', - 'ibv_wc_read_imm_data', 'ibv_wc_read_invalidated_rkey', - 'ibv_wc_read_opcode', 'ibv_wc_read_qp_num', 'ibv_wc_read_sl', - 'ibv_wc_read_slid', 'ibv_wc_read_src_qp', 'ibv_wc_read_tm_info', - 'ibv_wc_read_vendor_err', 'ibv_wc_read_wc_flags', 'ibv_wc_status', - 'ibv_wc_status_str', 'ibv_wq_attr_mask', 'ibv_wq_flags', - 'ibv_wq_init_attr_mask', 'ibv_wq_state', 'ibv_wq_type', - 'ibv_wr_abort', 'ibv_wr_atomic_cmp_swp', - 'ibv_wr_atomic_fetch_add', 'ibv_wr_atomic_write', - 'ibv_wr_bind_mw', 'ibv_wr_complete', 'ibv_wr_flush', - 'ibv_wr_local_inv', 'ibv_wr_opcode', 'ibv_wr_opcode_str', - 'ibv_wr_rdma_read', 'ibv_wr_rdma_write', 'ibv_wr_rdma_write_imm', - 'ibv_wr_send', 'ibv_wr_send_imm', 'ibv_wr_send_inv', - 'ibv_wr_send_tso', 'ibv_wr_set_inline_data', - 'ibv_wr_set_inline_data_list', 'ibv_wr_set_sge', - 'ibv_wr_set_sge_list', 'ibv_wr_set_ud_addr', - 'ibv_wr_set_xrc_srqn', 'ibv_wr_start', 'ibv_xrcd_init_attr_mask', - 'mbps_to_ibv_rate', 'mult_to_ibv_rate', 'rdma_driver_id', - 'size_t', 'ssize_t', 'struct___pthread_cond_s', - 'struct___pthread_internal_list', 'struct___pthread_mutex_s', - 'struct__compat_ibv_port_attr', 'struct__ibv_device_ops', - 'struct_c__UA___atomic_wide_counter___value32', - 'struct_ib_uverbs_ah_attr', 'struct_ib_uverbs_alloc_mw', - 'struct_ib_uverbs_alloc_mw_resp', 'struct_ib_uverbs_alloc_pd', - 'struct_ib_uverbs_alloc_pd_resp', - 'struct_ib_uverbs_async_event_desc', - 'struct_ib_uverbs_attach_mcast', 'struct_ib_uverbs_close_xrcd', - 'struct_ib_uverbs_cmd_hdr', 'struct_ib_uverbs_comp_event_desc', - 'struct_ib_uverbs_cq_moderation', - 'struct_ib_uverbs_cq_moderation_caps', - 'struct_ib_uverbs_create_ah', 'struct_ib_uverbs_create_ah_resp', - 'struct_ib_uverbs_create_comp_channel', - 'struct_ib_uverbs_create_comp_channel_resp', - 'struct_ib_uverbs_create_cq', 'struct_ib_uverbs_create_cq_resp', - 'struct_ib_uverbs_create_flow', - 'struct_ib_uverbs_create_flow_resp', 'struct_ib_uverbs_create_qp', - 'struct_ib_uverbs_create_qp_resp', 'struct_ib_uverbs_create_srq', - 'struct_ib_uverbs_create_srq_resp', - 'struct_ib_uverbs_create_xsrq', 'struct_ib_uverbs_dealloc_mw', - 'struct_ib_uverbs_dealloc_pd', 'struct_ib_uverbs_dereg_mr', - 'struct_ib_uverbs_destroy_ah', 'struct_ib_uverbs_destroy_cq', - 'struct_ib_uverbs_destroy_cq_resp', - 'struct_ib_uverbs_destroy_flow', 'struct_ib_uverbs_destroy_qp', - 'struct_ib_uverbs_destroy_qp_resp', - 'struct_ib_uverbs_destroy_srq', - 'struct_ib_uverbs_destroy_srq_resp', - 'struct_ib_uverbs_detach_mcast', 'struct_ib_uverbs_ex_cmd_hdr', - 'struct_ib_uverbs_ex_create_cq', - 'struct_ib_uverbs_ex_create_cq_resp', - 'struct_ib_uverbs_ex_create_qp', - 'struct_ib_uverbs_ex_create_qp_resp', - 'struct_ib_uverbs_ex_create_rwq_ind_table', - 'struct_ib_uverbs_ex_create_rwq_ind_table_resp', - 'struct_ib_uverbs_ex_create_wq', - 'struct_ib_uverbs_ex_create_wq_resp', - 'struct_ib_uverbs_ex_destroy_rwq_ind_table', - 'struct_ib_uverbs_ex_destroy_wq', - 'struct_ib_uverbs_ex_destroy_wq_resp', - 'struct_ib_uverbs_ex_modify_cq', 'struct_ib_uverbs_ex_modify_qp', - 'struct_ib_uverbs_ex_modify_qp_resp', - 'struct_ib_uverbs_ex_modify_wq', - 'struct_ib_uverbs_ex_query_device', - 'struct_ib_uverbs_ex_query_device_resp', - 'struct_ib_uverbs_flow_action_esp', - 'struct_ib_uverbs_flow_action_esp_encap', - 'struct_ib_uverbs_flow_action_esp_keymat_aes_gcm', - 'struct_ib_uverbs_flow_action_esp_replay_bmp', - 'struct_ib_uverbs_flow_attr', 'struct_ib_uverbs_flow_eth_filter', - 'struct_ib_uverbs_flow_gre_filter', - 'struct_ib_uverbs_flow_ipv4_filter', - 'struct_ib_uverbs_flow_ipv6_filter', - 'struct_ib_uverbs_flow_mpls_filter', - 'struct_ib_uverbs_flow_spec_action_count', - 'struct_ib_uverbs_flow_spec_action_count_0_0', - 'struct_ib_uverbs_flow_spec_action_drop', - 'struct_ib_uverbs_flow_spec_action_drop_0_0', - 'struct_ib_uverbs_flow_spec_action_handle', - 'struct_ib_uverbs_flow_spec_action_handle_0_0', - 'struct_ib_uverbs_flow_spec_action_tag', - 'struct_ib_uverbs_flow_spec_action_tag_0_0', - 'struct_ib_uverbs_flow_spec_esp', - 'struct_ib_uverbs_flow_spec_esp_0_0', - 'struct_ib_uverbs_flow_spec_esp_filter', - 'struct_ib_uverbs_flow_spec_eth', - 'struct_ib_uverbs_flow_spec_eth_0_0', - 'struct_ib_uverbs_flow_spec_gre', - 'struct_ib_uverbs_flow_spec_gre_0_0', - 'struct_ib_uverbs_flow_spec_hdr', - 'struct_ib_uverbs_flow_spec_ipv4', - 'struct_ib_uverbs_flow_spec_ipv4_0_0', - 'struct_ib_uverbs_flow_spec_ipv6', - 'struct_ib_uverbs_flow_spec_ipv6_0_0', - 'struct_ib_uverbs_flow_spec_mpls', - 'struct_ib_uverbs_flow_spec_mpls_0_0', - 'struct_ib_uverbs_flow_spec_tcp_udp', - 'struct_ib_uverbs_flow_spec_tcp_udp_0_0', - 'struct_ib_uverbs_flow_spec_tunnel', - 'struct_ib_uverbs_flow_spec_tunnel_0_0', - 'struct_ib_uverbs_flow_tcp_udp_filter', - 'struct_ib_uverbs_flow_tunnel_filter', - 'struct_ib_uverbs_get_context', - 'struct_ib_uverbs_get_context_resp', 'struct_ib_uverbs_gid_entry', - 'struct_ib_uverbs_global_route', 'struct_ib_uverbs_modify_qp', - 'struct_ib_uverbs_modify_srq', 'struct_ib_uverbs_odp_caps', - 'struct_ib_uverbs_odp_caps_per_transport_caps', - 'struct_ib_uverbs_open_qp', 'struct_ib_uverbs_open_xrcd', - 'struct_ib_uverbs_open_xrcd_resp', 'struct_ib_uverbs_poll_cq', - 'struct_ib_uverbs_poll_cq_resp', 'struct_ib_uverbs_post_recv', - 'struct_ib_uverbs_post_recv_resp', 'struct_ib_uverbs_post_send', - 'struct_ib_uverbs_post_send_resp', - 'struct_ib_uverbs_post_srq_recv', - 'struct_ib_uverbs_post_srq_recv_resp', 'struct_ib_uverbs_qp_attr', - 'struct_ib_uverbs_qp_cap', 'struct_ib_uverbs_qp_dest', - 'struct_ib_uverbs_query_device', - 'struct_ib_uverbs_query_device_resp', - 'struct_ib_uverbs_query_port', 'struct_ib_uverbs_query_port_resp', - 'struct_ib_uverbs_query_port_resp_ex', - 'struct_ib_uverbs_query_qp', 'struct_ib_uverbs_query_qp_resp', - 'struct_ib_uverbs_query_srq', 'struct_ib_uverbs_query_srq_resp', - 'struct_ib_uverbs_recv_wr', 'struct_ib_uverbs_reg_mr', - 'struct_ib_uverbs_reg_mr_resp', 'struct_ib_uverbs_req_notify_cq', - 'struct_ib_uverbs_rereg_mr', 'struct_ib_uverbs_rereg_mr_resp', - 'struct_ib_uverbs_resize_cq', 'struct_ib_uverbs_resize_cq_resp', - 'struct_ib_uverbs_rss_caps', 'struct_ib_uverbs_send_wr', - 'struct_ib_uverbs_send_wr_1_atomic', - 'struct_ib_uverbs_send_wr_1_rdma', - 'struct_ib_uverbs_send_wr_1_ud', 'struct_ib_uverbs_sge', - 'struct_ib_uverbs_tm_caps', 'struct_ib_uverbs_wc', - 'struct_ibv_ah', 'struct_ibv_ah_attr', 'struct_ibv_alloc_dm_attr', - 'struct_ibv_async_event', 'struct_ibv_comp_channel', - 'struct_ibv_context', 'struct_ibv_context_ops', - 'struct_ibv_counter_attach_attr', 'struct_ibv_counters', - 'struct_ibv_counters_init_attr', 'struct_ibv_cq', - 'struct_ibv_cq_ex', 'struct_ibv_cq_init_attr_ex', - 'struct_ibv_cq_moderation_caps', 'struct_ibv_data_buf', - 'struct_ibv_device', 'struct_ibv_device_attr', - 'struct_ibv_device_attr_ex', 'struct_ibv_dm', 'struct_ibv_ece', - 'struct_ibv_flow', 'struct_ibv_flow_action', - 'struct_ibv_flow_action_esp_attr', 'struct_ibv_flow_attr', - 'struct_ibv_flow_esp_filter', 'struct_ibv_flow_eth_filter', - 'struct_ibv_flow_gre_filter', 'struct_ibv_flow_ipv4_ext_filter', - 'struct_ibv_flow_ipv4_filter', 'struct_ibv_flow_ipv6_filter', - 'struct_ibv_flow_mpls_filter', 'struct_ibv_flow_spec', - 'struct_ibv_flow_spec_0_hdr', 'struct_ibv_flow_spec_action_drop', - 'struct_ibv_flow_spec_action_handle', - 'struct_ibv_flow_spec_action_tag', - 'struct_ibv_flow_spec_counter_action', 'struct_ibv_flow_spec_esp', - 'struct_ibv_flow_spec_eth', 'struct_ibv_flow_spec_gre', - 'struct_ibv_flow_spec_ipv4', 'struct_ibv_flow_spec_ipv4_ext', - 'struct_ibv_flow_spec_ipv6', 'struct_ibv_flow_spec_mpls', - 'struct_ibv_flow_spec_tcp_udp', 'struct_ibv_flow_spec_tunnel', - 'struct_ibv_flow_tcp_udp_filter', 'struct_ibv_flow_tunnel_filter', - 'struct_ibv_gid_entry', 'struct_ibv_gid_global', - 'struct_ibv_global_route', 'struct_ibv_grh', - 'struct_ibv_moderate_cq', 'struct_ibv_modify_cq_attr', - 'struct_ibv_mr', 'struct_ibv_mw', 'struct_ibv_mw_bind', - 'struct_ibv_mw_bind_info', 'struct_ibv_odp_caps', - 'struct_ibv_odp_caps_per_transport_caps', 'struct_ibv_ops_wr', - 'struct_ibv_ops_wr_0_add', 'struct_ibv_ops_wr_tm', - 'struct_ibv_packet_pacing_caps', - 'struct_ibv_parent_domain_init_attr', - 'struct_ibv_pci_atomic_caps', 'struct_ibv_pd', - 'struct_ibv_poll_cq_attr', 'struct_ibv_port_attr', - 'struct_ibv_qp', 'struct_ibv_qp_attr', 'struct_ibv_qp_cap', - 'struct_ibv_qp_ex', 'struct_ibv_qp_init_attr', - 'struct_ibv_qp_init_attr_ex', 'struct_ibv_qp_open_attr', - 'struct_ibv_qp_rate_limit_attr', - 'struct_ibv_query_device_ex_input', 'struct_ibv_recv_wr', - 'struct_ibv_rss_caps', 'struct_ibv_rwq_ind_table', - 'struct_ibv_rwq_ind_table_init_attr', 'struct_ibv_rx_hash_conf', - 'struct_ibv_send_wr', 'struct_ibv_send_wr_1_atomic', - 'struct_ibv_send_wr_1_rdma', 'struct_ibv_send_wr_1_ud', - 'struct_ibv_send_wr_2_xrc', 'struct_ibv_send_wr_3_bind_mw', - 'struct_ibv_send_wr_3_tso', 'struct_ibv_sge', 'struct_ibv_srq', - 'struct_ibv_srq_attr', 'struct_ibv_srq_init_attr', - 'struct_ibv_srq_init_attr_ex', 'struct_ibv_td', - 'struct_ibv_td_init_attr', 'struct_ibv_tm_cap', - 'struct_ibv_tm_caps', 'struct_ibv_tso_caps', - 'struct_ibv_values_ex', 'struct_ibv_wc', 'struct_ibv_wc_tm_info', - 'struct_ibv_wq', 'struct_ibv_wq_attr', 'struct_ibv_wq_init_attr', - 'struct_ibv_xrcd', 'struct_ibv_xrcd_init_attr', 'struct_timespec', - 'struct_verbs_context', 'struct_verbs_ex_private', 'uint16_t', - 'uint32_t', 'uint64_t', 'uint8_t', - 'union_c__UA___atomic_wide_counter', 'union_c__UA_pthread_cond_t', - 'union_c__UA_pthread_mutex_t', - 'union_ib_uverbs_flow_action_esp_encap_0', - 'union_ib_uverbs_flow_action_esp_encap_1', - 'union_ib_uverbs_flow_spec_action_count_0', - 'union_ib_uverbs_flow_spec_action_drop_0', - 'union_ib_uverbs_flow_spec_action_handle_0', - 'union_ib_uverbs_flow_spec_action_tag_0', - 'union_ib_uverbs_flow_spec_esp_0', - 'union_ib_uverbs_flow_spec_eth_0', - 'union_ib_uverbs_flow_spec_gre_0', - 'union_ib_uverbs_flow_spec_ipv4_0', - 'union_ib_uverbs_flow_spec_ipv6_0', - 'union_ib_uverbs_flow_spec_mpls_0', - 'union_ib_uverbs_flow_spec_tcp_udp_0', - 'union_ib_uverbs_flow_spec_tunnel_0', - 'union_ib_uverbs_send_wr_ex', 'union_ib_uverbs_send_wr_wr', - 'union_ib_uverbs_wc_ex', 'union_ibv_async_event_element', - 'union_ibv_flow_spec_0', 'union_ibv_gid', 'union_ibv_send_wr_0', - 'union_ibv_send_wr_3', 'union_ibv_send_wr_qp_type', - 'union_ibv_send_wr_wr', 'union_ibv_wc_0', 'verbs_get_ctx'] diff --git a/tinygrad_repo/tinygrad/runtime/autogen/libusb.py b/tinygrad_repo/tinygrad/runtime/autogen/libusb.py index aa81cee87..c516ef6de 100644 --- a/tinygrad_repo/tinygrad/runtime/autogen/libusb.py +++ b/tinygrad_repo/tinygrad/runtime/autogen/libusb.py @@ -6,7 +6,7 @@ # POINTER_SIZE is: 8 # LONGDOUBLE_SIZE is: 16 # -import ctypes, ctypes.util, os +import ctypes, os class FunctionFactoryStub: diff --git a/tinygrad_repo/tinygrad/runtime/autogen/nv/nv.py b/tinygrad_repo/tinygrad/runtime/autogen/nv/nv.py index fa4485ad6..d7695c758 100644 --- a/tinygrad_repo/tinygrad/runtime/autogen/nv/nv.py +++ b/tinygrad_repo/tinygrad/runtime/autogen/nv/nv.py @@ -6419,21 +6419,6 @@ struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02._fields_ = [ rpc_ctrl_subdevice_get_libos_heap_stats_v29_02 = struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02 rpc_ctrl_subdevice_get_libos_heap_stats_v = struct_rpc_ctrl_subdevice_get_libos_heap_stats_v29_02 -FSP_NVDM_FORMAT_H = True # macro -NVDM_TYPE_HULK = 0x11 # macro -NVDM_TYPE_FIRMWARE_UPDATE = 0x12 # macro -NVDM_TYPE_PRC = 0x13 # macro -NVDM_TYPE_COT = 0x14 # macro -NVDM_TYPE_FSP_RESPONSE = 0x15 # macro -NVDM_TYPE_CAPS_QUERY = 0x16 # macro -NVDM_TYPE_INFOROM = 0x17 # macro -NVDM_TYPE_SMBPBI = 0x18 # macro -NVDM_TYPE_ROMREAD = 0x1A # macro -NVDM_TYPE_UEFI_RM = 0x1C # macro -NVDM_TYPE_UEFI_XTL_DEBUG_INTR = 0x1D # macro -NVDM_TYPE_TNVL = 0x1F # macro -NVDM_TYPE_CLOCK_BOOST = 0x20 # macro -NVDM_TYPE_FSP_GSP_COMM = 0x21 # macro class struct_GSP_MSG_QUEUE_ELEMENT(Structure): pass @@ -7172,28 +7157,6 @@ BCRT30_RSA3K_SIG_SIZE = 384 # macro FWSECLIC_READ_VBIOS_STRUCT_FLAGS = (2) # macro FWSECLIC_FRTS_REGION_MEDIA_FB = (2) # macro FWSECLIC_FRTS_REGION_SIZE_1MB_IN_4K = (0x100) # macro -class struct_c__SA_FALCON_APPLICATION_INTERFACE_HEADER_V1(Structure): - pass - -struct_c__SA_FALCON_APPLICATION_INTERFACE_HEADER_V1._pack_ = 1 # source:True -struct_c__SA_FALCON_APPLICATION_INTERFACE_HEADER_V1._fields_ = [ - ('version', ctypes.c_ubyte), - ('headerSize', ctypes.c_ubyte), - ('entrySize', ctypes.c_ubyte), - ('entryCount', ctypes.c_ubyte), -] - -FALCON_APPLICATION_INTERFACE_HEADER_V1 = struct_c__SA_FALCON_APPLICATION_INTERFACE_HEADER_V1 -class struct_c__SA_FALCON_APPLICATION_INTERFACE_ENTRY_V1(Structure): - pass - -struct_c__SA_FALCON_APPLICATION_INTERFACE_ENTRY_V1._pack_ = 1 # source:True -struct_c__SA_FALCON_APPLICATION_INTERFACE_ENTRY_V1._fields_ = [ - ('id', ctypes.c_uint32), - ('dmemOffset', ctypes.c_uint32), -] - -FALCON_APPLICATION_INTERFACE_ENTRY_V1 = struct_c__SA_FALCON_APPLICATION_INTERFACE_ENTRY_V1 class struct_c__SA_FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3(Structure): pass @@ -7382,8 +7345,6 @@ __all__ = \ 'FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS', 'FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB', 'FALCON_APPLICATION_INTERFACE_ENTRY_ID_DMEMMAPPER', - 'FALCON_APPLICATION_INTERFACE_ENTRY_V1', - 'FALCON_APPLICATION_INTERFACE_HEADER_V1', 'FALCON_UCODE_DESC_HEADER', 'FALCON_UCODE_DESC_HEADER_FORMAT', 'FALCON_UCODE_DESC_V3', 'FALCON_UCODE_DESC_V3_44_FMT', 'FALCON_UCODE_DESC_V3_SIZE_44', @@ -7400,9 +7361,8 @@ __all__ = \ 'FECS_ERROR_EVENT_TYPE_BUFFER_FULL', 'FECS_ERROR_EVENT_TYPE_BUFFER_RESET_REQUIRED', 'FECS_ERROR_EVENT_TYPE_MAX', 'FECS_ERROR_EVENT_TYPE_NONE', - 'FECS_ERROR_EVENT_TYPE__enumvalues', 'FSP_NVDM_FORMAT_H', - 'FWSECLIC_FRTS_CMD', 'FWSECLIC_FRTS_REGION_DESC', - 'FWSECLIC_FRTS_REGION_MEDIA_FB', + 'FECS_ERROR_EVENT_TYPE__enumvalues', 'FWSECLIC_FRTS_CMD', + 'FWSECLIC_FRTS_REGION_DESC', 'FWSECLIC_FRTS_REGION_MEDIA_FB', 'FWSECLIC_FRTS_REGION_SIZE_1MB_IN_4K', 'FWSECLIC_READ_VBIOS_DESC', 'FWSECLIC_READ_VBIOS_STRUCT_FLAGS', 'FW_WPR_LAYOUT_OFFSET', 'GPU_RECOVERY_EVENT_TYPE', @@ -7470,12 +7430,6 @@ __all__ = \ 'NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_STENCIL', 'NVB0CC_REGOPS_MODE', 'NVB0CC_REGOPS_MODE_ALL_OR_NONE', 'NVB0CC_REGOPS_MODE_CONTINUE_ON_ERROR', 'NVDM_PAYLOAD_COT', - 'NVDM_TYPE_CAPS_QUERY', 'NVDM_TYPE_CLOCK_BOOST', 'NVDM_TYPE_COT', - 'NVDM_TYPE_FIRMWARE_UPDATE', 'NVDM_TYPE_FSP_GSP_COMM', - 'NVDM_TYPE_FSP_RESPONSE', 'NVDM_TYPE_HULK', 'NVDM_TYPE_INFOROM', - 'NVDM_TYPE_PRC', 'NVDM_TYPE_ROMREAD', 'NVDM_TYPE_SMBPBI', - 'NVDM_TYPE_TNVL', 'NVDM_TYPE_UEFI_RM', - 'NVDM_TYPE_UEFI_XTL_DEBUG_INTR', 'NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX', 'NVGPU_ENGINE_CAPS_MASK_BITS', 'NV_ACPI_GENERIC_FUNC_COUNT', 'NV_BIT_FALCON_UCODE_DESC_HEADER_VDESC_FLAGS_VERSION_AVAILABLE', @@ -8372,8 +8326,6 @@ __all__ = \ 'struct_c__SA_BIT_DATA_FALCON_DATA_V2', 'struct_c__SA_BUSINFO', 'struct_c__SA_EcidManufacturingInfo', 'struct_c__SA_FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3', - 'struct_c__SA_FALCON_APPLICATION_INTERFACE_ENTRY_V1', - 'struct_c__SA_FALCON_APPLICATION_INTERFACE_HEADER_V1', 'struct_c__SA_FALCON_UCODE_DESC_HEADER', 'struct_c__SA_FALCON_UCODE_DESC_V3', 'struct_c__SA_FALCON_UCODE_TABLE_ENTRY_V1', diff --git a/tinygrad_repo/tinygrad/runtime/autogen/nv_gpu.py b/tinygrad_repo/tinygrad/runtime/autogen/nv_gpu.py index e3962d938..791af98ff 100644 --- a/tinygrad_repo/tinygrad/runtime/autogen/nv_gpu.py +++ b/tinygrad_repo/tinygrad/runtime/autogen/nv_gpu.py @@ -19609,30 +19609,6 @@ struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS._fields_ = [ ] NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS = struct_NV2080_CTRL_I2C_ENABLE_MONITOR_3D_MODE_PARAMS -GMMU_FMT_MAX_LEVELS = 6 # macro -# def NV90F1_CTRL_CMD(cat, idx): # macro -# return NVXXXX_CTRL_CMD(0x90F1,NV90F1_CTRL_##cat,idx) -NV90F1_CTRL_RESERVED = (0x00) # macro -NV90F1_CTRL_VASPACE = (0x01) # macro -NV90F1_CTRL_CMD_NULL = (0x90f10000) # macro -NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT = (0x90f10101) # macro -NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID = (0x1) # macro -NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO = (0x90f10102) # macro -NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID = (0x2) # macro -NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE = 0x0 # macro -# NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_BAR1 = NVBIT64 ( 0 ) # macro -NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES = (0x90f10103) # macro -NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID = (0x3) # macro -NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES = (0x90f10104) # macro -NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID = (0x4) # macro -NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF = (0x90f10105) # macro -NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID = (0x5) # macro -NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES = (0x90f10106) # macro -NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID = (0x6) # macro -NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE = (0x90f10107) # macro -NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID = (0x7) # macro -NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO = (0x90f10108) # macro -NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID = (0x8) # macro NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO = (0x20800a01) # macro NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID = (0x1) # macro NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_MESSAGE_ID = (0x1C) # macro @@ -20193,149 +20169,6 @@ NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID = (0x97) NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS = (0x20800a97) # macro NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID = (0xAB) # macro NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK = (0x20800aab) # macro -class struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pFmt', ctypes.POINTER(None)), -] - -NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS -class struct_NV_CTRL_VASPACE_PAGE_LEVEL(Structure): - pass - -class struct_MMU_FMT_LEVEL(Structure): - pass - -struct_MMU_FMT_LEVEL._pack_ = 1 # source:False -struct_MMU_FMT_LEVEL._fields_ = [ - ('virtAddrBitLo', ctypes.c_ubyte), - ('virtAddrBitHi', ctypes.c_ubyte), - ('entrySize', ctypes.c_ubyte), - ('bPageTable', ctypes.c_ubyte), - ('numSubLevels', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), - ('pageLevelIdTag', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), - ('subLevels', ctypes.POINTER(struct_MMU_FMT_LEVEL)), -] - -struct_NV_CTRL_VASPACE_PAGE_LEVEL._pack_ = 1 # source:False -struct_NV_CTRL_VASPACE_PAGE_LEVEL._fields_ = [ - ('pFmt', ctypes.POINTER(struct_MMU_FMT_LEVEL)), - ('levelFmt', struct_MMU_FMT_LEVEL), - ('sublevelFmt', struct_MMU_FMT_LEVEL * 2), - ('physAddress', ctypes.c_uint64), - ('aperture', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('size', ctypes.c_uint64), - ('entryIndex', ctypes.c_uint32), - ('PADDING_1', ctypes.c_ubyte * 4), -] - -NV_CTRL_VASPACE_PAGE_LEVEL = struct_NV_CTRL_VASPACE_PAGE_LEVEL -class struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('virtAddress', ctypes.c_uint64), - ('pageSize', ctypes.c_uint64), - ('flags', ctypes.c_uint64), - ('numLevels', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('levels', struct_NV_CTRL_VASPACE_PAGE_LEVEL * 6), -] - -NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS -class struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pageSize', ctypes.c_uint64), - ('virtAddrLo', ctypes.c_uint64), - ('virtAddrHi', ctypes.c_uint64), -] - -NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS = struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS -class struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pageSize', ctypes.c_uint64), - ('virtAddrLo', ctypes.c_uint64), - ('virtAddrHi', ctypes.c_uint64), -] - -NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS = struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS -NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS -class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS(Structure): - pass - -class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0._fields_ = [ - ('physAddress', ctypes.c_uint64), - ('size', ctypes.c_uint64), - ('aperture', ctypes.c_uint32), - ('pageShift', ctypes.c_ubyte), - ('PADDING_0', ctypes.c_ubyte * 3), -] - -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('pageSize', ctypes.c_uint64), - ('virtAddrLo', ctypes.c_uint64), - ('virtAddrHi', ctypes.c_uint64), - ('numLevelsToCopy', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), - ('levels', struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0 * 6), -] - -NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS = struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS -class struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('requiredVaRange', ctypes.c_uint64), -] - -NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS -class struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS(Structure): - pass - -struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS._pack_ = 1 # source:False -struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS._fields_ = [ - ('hSubDevice', ctypes.c_uint32), - ('subDeviceId', ctypes.c_uint32), - ('bytesFree', ctypes.c_uint64), - ('bytesTotal', ctypes.c_uint64), - ('largestFreeOffset', ctypes.c_uint64), - ('largestFreeSize', ctypes.c_uint64), - ('usableBytesFree', ctypes.c_uint64), - ('numFreeBlocks', ctypes.c_uint32), - ('PADDING_0', ctypes.c_ubyte * 4), -] - -NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS = struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS class struct_NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS(Structure): pass @@ -21348,10 +21181,39 @@ struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS._f NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS class struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS(Structure): - _pack_ = 1 # source:False - _fields_ = [ - ('PdeCopyParams', NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS), - ] + pass + +class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS(Structure): + pass + +class struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0(Structure): + pass + +struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0._pack_ = 1 # source:False +struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0._fields_ = [ + ('physAddress', ctypes.c_uint64), + ('size', ctypes.c_uint64), + ('aperture', ctypes.c_uint32), + ('pageShift', ctypes.c_ubyte), + ('PADDING_0', ctypes.c_ubyte * 3), +] + +struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS._pack_ = 1 # source:False +struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS._fields_ = [ + ('hSubDevice', ctypes.c_uint32), + ('subDeviceId', ctypes.c_uint32), + ('pageSize', ctypes.c_uint64), + ('virtAddrLo', ctypes.c_uint64), + ('virtAddrHi', ctypes.c_uint64), + ('numLevelsToCopy', ctypes.c_uint32), + ('PADDING_0', ctypes.c_ubyte * 4), + ('levels', struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0 * 6), +] + +struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS._pack_ = 1 # source:False +struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS._fields_ = [ + ('PdeCopyParams', struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS), +] NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS = struct_NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS class struct_NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X(Structure): @@ -27901,7 +27763,7 @@ __all__ = \ 'GF100_SUBDEVICE_INFOROM', 'GF100_SUBDEVICE_MASTER', 'GF100_TIMED_SEMAPHORE_SW', 'GF100_ZBC_CLEAR', 'GLOB_TYPE_APITEST', 'GLOB_TYPE_GET_NBSI_ACPI_RAW', - 'GLOB_TYPE_GET_NBSI_DIR', 'GMMU_FMT_MAX_LEVELS', 'GP100_UVM_SW', + 'GLOB_TYPE_GET_NBSI_DIR', 'GP100_UVM_SW', 'GPS_MAX_ACPI_OUTPUT_BUFFER_SIZE', 'GPS_MAX_COUNTERS_PER_BLOCK', 'GPU_PART_NUMBER_FMT', 'GT200_DEBUGGER', 'GUEST_VM_INFO_STATE', 'GUEST_VM_INFO_STATE_INITIALIZED', @@ -34493,35 +34355,9 @@ __all__ = \ 'NV83DE_CTRL_FIFO', 'NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS', 'NV83DE_CTRL_GR', 'NV83DE_CTRL_INTERNAL', 'NV83DE_CTRL_RESERVED', 'NV83DE_MMU_FAULT_INFO', 'NV83DE_SM_ERROR_STATE_REGISTERS', - 'NV9010_VBLANK_CALLBACK', 'NV90F1_CTRL_CMD_NULL', - 'NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES', - 'NV90F1_CTRL_CMD_VASPACE_GET_GMMU_FORMAT', - 'NV90F1_CTRL_CMD_VASPACE_GET_HOST_RM_MANAGED_SIZE', - 'NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO', - 'NV90F1_CTRL_CMD_VASPACE_GET_PAGE_LEVEL_INFO_VERIF', - 'NV90F1_CTRL_CMD_VASPACE_GET_VAS_HEAP_INFO', - 'NV90F1_CTRL_CMD_VASPACE_RELEASE_ENTRIES', - 'NV90F1_CTRL_CMD_VASPACE_RESERVE_ENTRIES', 'NV90F1_CTRL_RESERVED', - 'NV90F1_CTRL_VASPACE', - 'NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS', - 'NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS', - 'NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS', - 'NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_FLAG_NONE', - 'NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS', - 'NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS', - 'NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_VERIF_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS', - 'NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS', - 'NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_MESSAGE_ID', - 'NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS', - 'NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_BIND_PARAMS', 'NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID', - 'NVA06C_CTRL_CMD_BIND', 'NVA06C_CTRL_CMD_GET_INFO', + 'NV9010_VBLANK_CALLBACK', 'NVA06C_CTRL_BIND_PARAMS', + 'NVA06C_CTRL_BIND_PARAMS_MESSAGE_ID', 'NVA06C_CTRL_CMD_BIND', + 'NVA06C_CTRL_CMD_GET_INFO', 'NVA06C_CTRL_CMD_GET_INTERLEAVE_LEVEL', 'NVA06C_CTRL_CMD_GET_TIMESLICE', 'NVA06C_CTRL_CMD_GPFIFO_SCHEDULE', @@ -36589,7 +36425,6 @@ __all__ = \ 'NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE', 'NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE', 'NV_CONTEXT_DMA_ALLOCATION_PARAMS', 'NV_COUNTER_COLLECTION_UNIT', - 'NV_CTRL_VASPACE_PAGE_LEVEL', 'NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC', 'NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER', 'NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SPECIFIED', @@ -37168,8 +37003,7 @@ __all__ = \ 'struct_ACR_REGION_ID_PROP', 'struct_ACR_REQUEST_PARAMS', 'struct_ACR_STATUS_PARAMS', 'struct_CC_AES_CRYPTOBUNDLE', 'struct_CC_HMAC_CRYPTOBUNDLE', 'struct_CC_KMB', - 'struct_DRAM_CLK_INSTANCE', 'struct_MMU_FMT_LEVEL', - 'struct_NV0000_ALLOC_PARAMETERS', + 'struct_DRAM_CLK_INSTANCE', 'struct_NV0000_ALLOC_PARAMETERS', 'struct_NV0000_CTRL_CLIENT_GET_ACCESS_RIGHTS_PARAMS', 'struct_NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS', 'struct_NV0000_CTRL_CLIENT_GET_HANDLE_INFO_PARAMS', @@ -38235,12 +38069,6 @@ __all__ = \ 'struct_NV83DE_SM_ERROR_STATE_REGISTERS', 'struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS', 'struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0', - 'struct_NV90F1_CTRL_VASPACE_GET_GMMU_FORMAT_PARAMS', - 'struct_NV90F1_CTRL_VASPACE_GET_HOST_RM_MANAGED_SIZE_PARAMS', - 'struct_NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS', - 'struct_NV90F1_CTRL_VASPACE_GET_VAS_HEAP_INFO_PARAMS', - 'struct_NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS', - 'struct_NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS', 'struct_NVA06C_CTRL_GET_INFO_PARAMS', 'struct_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS', 'struct_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS', @@ -38266,7 +38094,6 @@ __all__ = \ 'struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS', 'struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS', 'struct_NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS', - 'struct_NV_CTRL_VASPACE_PAGE_LEVEL', 'struct_NV_MEMORY_DESC_PARAMS', 'struct_Nv2080ACPIEvent', 'struct_Nv2080AudioHdcpRequestRec', 'struct_Nv2080ClocksChangeNotificationRec', diff --git a/tinygrad_repo/tinygrad/runtime/graph/hcq.py b/tinygrad_repo/tinygrad/runtime/graph/hcq.py index d41c56fe9..4bcf17dba 100644 --- a/tinygrad_repo/tinygrad/runtime/graph/hcq.py +++ b/tinygrad_repo/tinygrad/runtime/graph/hcq.py @@ -1,11 +1,11 @@ import collections, time from typing import Any, cast -from tinygrad.helpers import round_up, PROFILE, merge_dicts, getenv, dedup -from tinygrad.runtime.support.hcq import HCQCompiled, HCQAllocator, HCQSignal, HCQBuffer, HWQueue, HCQArgsState, BumpAllocator, MMIOInterface +from tinygrad.helpers import round_up, PROFILE, merge_dicts +from tinygrad.runtime.support.hcq import HCQCompiled, HCQAllocator, HCQSignal, HCQBuffer, HWQueue, HCQArgsState, BumpAllocator from tinygrad.device import Buffer, BufferSpec, Compiled, Device, ProfileGraphEntry, ProfileGraphEvent from tinygrad.dtype import dtypes from tinygrad.uop.ops import UOp, Variable -from tinygrad.engine.realize import ExecItem, BufferXfer, CompiledRunner, BufferCopy +from tinygrad.engine.realize import ExecItem, BufferXfer, CompiledRunner from tinygrad.engine.jit import MultiGraphRunner class HCQGraph(MultiGraphRunner): @@ -13,9 +13,6 @@ class HCQGraph(MultiGraphRunner): super().__init__(jit_cache, input_rawbuffers, var_vals) self.devices = list(set(cast(HCQCompiled, d) for ji in jit_cache for d in [Device[cast(Buffer, x).device] for x in ji.bufs])) - # CPU Device is always last - self.devices = sorted(self.devices, key=lambda x: 1 if x._is_cpu() else 0) - # Replace input buffers with variables. self.hcq_bufs = [[cast(Buffer, x)._buf for x in ji.bufs] for ji in jit_cache] self.input_replace_to_var: dict[tuple[int, int], Variable] = {} @@ -29,7 +26,7 @@ class HCQGraph(MultiGraphRunner): for ji in jit_cache: if not isinstance(ji.prg, CompiledRunner): continue kernargs_size[ji.prg.dev] += round_up(ji.prg._prg.kernargs_alloc_size, 16) - self.kernargs_bufs: dict[Compiled, HCQBuffer] = {d:d.allocator._alloc(max(sz, 1), BufferSpec(cpu_access=True)) for d,sz in kernargs_size.items()} + self.kernargs_bufs: dict[Compiled, HCQBuffer] = {dev:dev.allocator._alloc(sz, BufferSpec(cpu_access=True)) for dev,sz in kernargs_size.items()} # Fill initial arguments. self.ji_args: dict[int, HCQArgsState] = {} @@ -51,15 +48,14 @@ class HCQGraph(MultiGraphRunner): self.comp_queues: dict[HCQCompiled, HWQueue] = {dev: dev.hw_compute_queue_t() for dev in self.devices} self.copy_queues: dict[HCQCompiled, HWQueue] = {} # lazy allocation - self.signals: dict[Any, HCQSignal] = {**{dev: dev.new_signal(value=0) for dev in self.devices if not dev._is_cpu()}, - **{"KICK": self.devices[0].new_signal(value=0)}, **{dev: self.devices[0].new_signal(value=0) for dev in self.devices if dev._is_cpu()}} + self.signals: dict[Any, HCQSignal] = {**{dev: dev.signal_t(value=0) for dev in self.devices}, **{"CPU": self.devices[0].signal_t(value=0)}} self.kickoff_value: int = 0 self.kickoff_var = UOp.variable("kickoff_var", 0, 0xffffffff, dtype=dtypes.uint32) # When profiling allocate 2 signals for each jit item to measure speed. The jth jit item have signals at 2*j and 2*j+1. # TODO: This logic might allocate a few extra signals... - self.prof_signals: list[HCQSignal] = [] - self.prof_graph_deps: list[list[int]] = [] + self.prof_signals: list[HCQSignal] = [self.devices[0].signal_t() for i in range(len(jit_cache) * 2)] if PROFILE else [] + self.prog_graph_deps: list[list[int]] = [] self.prof_graph_entries: list[ProfileGraphEntry] = [] last_j: dict[HWQueue, int|None] = collections.defaultdict(lambda: None) @@ -68,15 +64,10 @@ class HCQGraph(MultiGraphRunner): for dev, queue in self.comp_queues.items(): dev_access[queue].add(dev) - self.input_replace_map: dict[HCQCompiled, set[int]] = collections.defaultdict(set) self.fixedvars: dict[HCQCompiled, dict[Variable, int]] = {} for j,ji in enumerate(jit_cache): - if is_exec_prg:=isinstance(ji.prg, CompiledRunner): enqueue_dev: HCQCompiled = ji.prg.dev - else: - # For copy ops prioritize enqeueuing on the dest device, so reverse the buffers. - for b in cast(list[Buffer], ji.bufs[::-1]): - if (enqueue_dev:=cast(HCQCompiled, Device[b.device])).hw_copy_queue_t is not None: break + enqueue_dev: HCQCompiled = ji.prg.dev if (is_exec_prg:=isinstance(ji.prg, CompiledRunner)) else Device[ji.bufs[1].device] #type:ignore # set any fixedvars on the device self.fixedvars[enqueue_dev] = merge_dicts([self.fixedvars.get(enqueue_dev, {}), ji.fixedvars]) @@ -87,7 +78,7 @@ class HCQGraph(MultiGraphRunner): assert (enqueue_dev.hw_copy_queue_t is not None), "device must implement a copy queue" enqueue_queue = self.copy_queues.setdefault(enqueue_dev, enqueue_dev.hw_copy_queue_t()) - out_signal = self.signals.setdefault(enqueue_queue, self.devices[0].new_signal(value=0)) + out_signal = self.signals.setdefault(enqueue_queue, enqueue_dev.signal_t(value=0)) # Get dependencies based on input and output buffers. rdeps = self._access_resources(ji.bufs, ji.prg.p.outs if is_exec_prg else [0], (enqueue_queue, j + 1)) #type:ignore @@ -101,9 +92,9 @@ class HCQGraph(MultiGraphRunner): if (qa:=queue_access[enqueue_queue][dep_queue]) is None or qa < dep_val: opt_deps.append((self.signals[dep_queue], dep_val)) queue_access[enqueue_queue][dep_queue] = dep_val - dev_access[enqueue_queue].update(dev_access[dep_queue]) # Ensure device is ready for use in current context: the graph has initialized the device and it's safe to operate on it within this graph. + for dep_queue, _ in opt_deps: dev_access[enqueue_queue].update(dev_access[dep_queue]) sync_signals = [(self.signals[d], self.kickoff_var) for b in ji.bufs if (d:=Device[cast(Buffer, b).device]) not in dev_access[enqueue_queue]] dev_access[enqueue_queue].update(cast(HCQCompiled, Device[cast(Buffer, b).device]) for b in ji.bufs) @@ -127,31 +118,28 @@ class HCQGraph(MultiGraphRunner): prof_ji_desc = ji.prg._prg.name if is_exec_prg else f"{ji.bufs[1].device} -> {ji.bufs[0].device}" # type: ignore self.prof_graph_entries.append(ProfileGraphEntry(enqueue_dev.device, prof_ji_desc, sig_st, j * 2 + 1, is_copy=not is_exec_prg)) - self.prof_graph_deps.append([d - 1 for _, d in rdeps]) + self.prog_graph_deps.append([d - 1 for _, d in rdeps]) last_j[enqueue_queue] = j # Check which signals are used in the profile graph. - self.prof_signal_is_used = [any(ent.st_id == j or ent.en_id == j for ent in self.prof_graph_entries) for j in range(len(jit_cache) * 2)] + self.prof_signal_is_used = [any(ent.st_id == j or ent.en_id == j for ent in self.prof_graph_entries) for j in range(len(self.prof_signals))] # Build hardware queues. self.copy_to_devs: dict[HCQCompiled, set[HCQCompiled]] = {dev: set() for dev in self.devices} # Create variable timeline signals for each device. - timeline_sigaddrs = {dev: UOp.variable(f"timeline_sig_{self.dev_name(dev)}", 0, 0xffffffffffffffff, dtype=dtypes.uint64) for dev in self.devices} - self.virt_timeline_vals = {dev: UOp.variable(f"timeline_var_{self.dev_name(dev)}", 0, 0xffffffff, dtype=dtypes.uint32) for dev in self.devices} - self.virt_timeline_signals = {dev: dev.signal_t(HCQBuffer(timeline_sigaddrs[dev], 16), owner=dev, is_timeline=True) for dev in self.devices} + timeline_sigaddrs = {dev: UOp.variable(f"timeline_sig_{dev.device_id}", 0, 0xffffffffffffffff, dtype=dtypes.uint64) for dev in self.devices} + self.virt_timeline_vals = {dev: UOp.variable(f"timeline_var_{dev.device_id}", 0, 0xffffffff, dtype=dtypes.uint32) for dev in self.devices} + self.virt_timeline_signals = {dev: dev.signal_t(base_buf=HCQBuffer(timeline_sigaddrs[dev], 16), timeline_for_device=dev) for dev in self.devices} for dev in self.devices: self.comp_queues[dev].memory_barrier().wait(self.virt_timeline_signals[dev], self.virt_timeline_vals[dev]) \ - .wait(self.signals['KICK'], self.kickoff_var).signal(self.signals[dev], self.kickoff_var) + .wait(self.signals['CPU'], self.kickoff_var).signal(self.signals[dev], self.kickoff_var) for j,ji in enumerate(jit_cache): enqueue_dev, enqueue_queue, sync_signals, deps, signal, signal_val = self.ji_schedule[j] - # Lazy allocate signals - if PROFILE: self.prof_signals += [enqueue_dev.new_signal(value=0) for _ in range(2)] - for sig, val in sync_signals + deps: enqueue_queue.wait(sig, val) # Encode waits and start profile timestamp (if needed). @@ -160,11 +148,10 @@ class HCQGraph(MultiGraphRunner): # Encode main commands based on ji type. if isinstance(ji.prg, CompiledRunner): enqueue_queue.exec(ji.prg._prg, self.ji_args[j], tuple(ji.prg.p.global_size or (1,1,1)), tuple(ji.prg.p.local_size or (1,1,1))) - elif isinstance(ji.prg, (BufferXfer, BufferCopy)): + elif isinstance(ji.prg, BufferXfer): dest, src = [cast(Buffer, x) for x in ji.bufs[0:2]] - for bufid, src in enumerate(cast(list[Buffer], ji.bufs)): - if (inprep_idx:=self.input_replace.get((j, bufid))) is not None: self.input_replace_map[enqueue_dev].add(inprep_idx) - else: cast(HCQAllocator, enqueue_dev.allocator).map(self.hcq_bufs[j][bufid]) + cast(HCQAllocator, Device[src.device].allocator).map(dest._buf) + enqueue_queue.copy(self.hcq_bufs[j][0].va_addr, self.hcq_bufs[j][1].va_addr, dest.nbytes) self.copy_to_devs[cast(HCQCompiled, Device[dest.device])].add(cast(HCQCompiled, Device[src.device])) @@ -188,10 +175,7 @@ class HCQGraph(MultiGraphRunner): self.kickoff_value += 1 for dev in self.devices: self.last_timeline[dev][0].wait(self.last_timeline[dev][1]) for sig in self.queue_signals_to_reset: sig.value = 0 - self.signals['KICK'].value = self.kickoff_value - - for dev in self.devices: - for idx_to_map in self.input_replace_map[dev]: cast(HCQAllocator, dev.allocator).map(input_rawbuffers[idx_to_map]._buf) + self.signals['CPU'].value = self.kickoff_value if PROFILE and self.kickoff_value > 1: self.collect_timestamps() @@ -216,9 +200,7 @@ class HCQGraph(MultiGraphRunner): def collect_timestamps(self): # NOTE: Append to any device is fine... - self.devices[0].profile_events += [ProfileGraphEvent(self.prof_graph_entries, self.prof_graph_deps, [s.timestamp for s in self.prof_signals])] - - def dev_name(self, dev) -> str: return dev.device.replace(":", "_") + self.devices[0].profile_events += [ProfileGraphEvent(self.prof_graph_entries, self.prog_graph_deps, [s.timestamp for s in self.prof_signals])] def __del__(self): for dev in self.devices: self.last_timeline[dev][0].wait(self.last_timeline[dev][1]) @@ -226,19 +208,3 @@ class HCQGraph(MultiGraphRunner): if PROFILE and self.kickoff_value >= 1: self.collect_timestamps() for fdev, buf in self.kernargs_bufs.items(): fdev.allocator._free(buf, BufferSpec(cpu_access=True)) - - @staticmethod - def supports_exec_item(devs:list[Compiled], ei:ExecItem) -> bool: - # Check if all devices are HCQ - all_devs = cast(list[HCQCompiled], dedup(devs + [Device[b.device] for b in ei.bufs if b])) - if not all(issubclass(type(d), HCQCompiled) for d in all_devs): return False - - # If all of devices are mapped into CPU address space, can use CPU inside the peer group. - cpu_support = all(isinstance(d.timeline_signal.base_buf.view, MMIOInterface) for d in all_devs) - - # Check if all devices are within the same peer group. If CPU is supported, don't count it as a separate peer group. - if len(set(d.peer_group for d in all_devs if cpu_support and not d._is_cpu())) > 1: return False - - # MOCKGPU is not supported, since it can't execute commands in parallel - copy = (isinstance(ei.prg, BufferCopy) and cast(HCQCompiled, devs[0]).hw_copy_queue_t is not None) and not getenv("MOCKGPU") - return isinstance(ei.prg, (CompiledRunner, BufferXfer)) or copy diff --git a/tinygrad_repo/tinygrad/runtime/graph/metal.py b/tinygrad_repo/tinygrad/runtime/graph/metal.py index 112f70050..d8fd14abe 100644 --- a/tinygrad_repo/tinygrad/runtime/graph/metal.py +++ b/tinygrad_repo/tinygrad/runtime/graph/metal.py @@ -1,8 +1,8 @@ from typing import Any, cast -import ctypes, re, decimal +import ctypes, re from tinygrad.dtype import dtypes -from tinygrad.helpers import dedup, getenv, merge_dicts, PROFILE -from tinygrad.device import Buffer, ProfileGraphEntry, ProfileGraphEvent +from tinygrad.helpers import dedup, getenv, merge_dicts +from tinygrad.device import Buffer from tinygrad.engine.realize import ExecItem, CompiledRunner from tinygrad.engine.jit import GraphRunner, GraphException from tinygrad.uop.ops import Variable @@ -63,8 +63,6 @@ class MetalGraph(GraphRunner): def __call__(self, input_rawbuffers: list[Buffer], var_vals: dict[Variable, int], wait=False) -> float|None: if self.command_buffer is not None and self.command_buffer in self.dev.mtl_buffers_in_flight: wait_check(self.command_buffer) - # NOTE: old command buffer may not be inflight anymore - if self.command_buffer is not None and PROFILE: self.collect_timestamps() all_resources = dedup(self.all_resources + [input_rawbuffers[input_idx]._buf.buf for input_idx in self.input_replace.values()]) for (j,i),input_idx in self.input_replace.items(): @@ -102,15 +100,3 @@ class MetalGraph(GraphRunner): wait_check(command_buffer) return cmdbuf_en_time(command_buffer) - cmdbuf_st_time(command_buffer) return None - - def collect_timestamps(self): - # create a graph event and evenly space each program - st, en = decimal.Decimal(cmdbuf_st_time(self.command_buffer)) * 1000000, decimal.Decimal(cmdbuf_en_time(self.command_buffer)) * 1000000 - ents = [ProfileGraphEntry(self.device, cast(CompiledRunner, ji.prg)._prg.name, i, i+1, is_copy=False) for i,ji in enumerate(self.jit_cache)] - step = (en-st)/len(ents) - self.dev.profile_events += [ProfileGraphEvent(ents, [], [st+step*i for i in range(len(ents)+1)])] - - def __del__(self): - if PROFILE and self.command_buffer is not None: - wait_check(self.command_buffer) - self.collect_timestamps() diff --git a/tinygrad_repo/tinygrad/runtime/graph/remote.py b/tinygrad_repo/tinygrad/runtime/graph/remote.py index a0d9e20ed..a18bb0bbe 100644 --- a/tinygrad_repo/tinygrad/runtime/graph/remote.py +++ b/tinygrad_repo/tinygrad/runtime/graph/remote.py @@ -1,114 +1,41 @@ -import time, itertools from tinygrad.uop.ops import Variable -from tinygrad.engine.jit import MultiGraphRunner +from tinygrad.engine.jit import GraphRunner, MultiGraphRunner, GraphException from tinygrad.engine.realize import CompiledRunner, BufferXfer, ExecItem -from tinygrad.device import Device, Compiled, Buffer -from tinygrad.runtime.ops_remote import RemoteDevice, RemoteConnection, RemoteRequest, GraphComputeItem, Transfer, GraphAlloc, GraphFree, GraphExec -from tinygrad.runtime.ops_remote import BatchTransfer, Event, Wait -from tinygrad.helpers import unwrap, flatten, dedup -from enum import Enum, auto -from dataclasses import replace -from collections import defaultdict +from tinygrad.device import Device, Buffer +from tinygrad.runtime.ops_remote import RemoteDevice, GraphComputeItem, Transfer, GraphAlloc, GraphFree, GraphExec +from tinygrad.helpers import unwrap, flatten, dedup, all_same from typing import cast -class StagingType(Enum): NONE = auto(); GRAPH = auto(); TRANSFER = auto() # noqa: E702 - -def rd(dev:Compiled) -> RemoteDevice: return cast(RemoteDevice, dev) -def dev_key(dev:RemoteDevice): return dev.conn if dev.properties.graph_supports_multi else dev -def map_rawbuf(rawbuf:Buffer): return (cast(RemoteDevice, Device[rawbuf.device]).session, rawbuf._buf) - -class RemoteGraph(MultiGraphRunner): +class RemoteGraph(GraphRunner): def __init__(self, jit_cache: list[ExecItem], rawbufs: list[Buffer], var_vals: dict[Variable, int]): super().__init__(jit_cache, rawbufs, var_vals) - devices = dedup(flatten([[Device[unwrap(buf).device] for buf in ji.bufs] for ji in jit_cache])) - c2d = {device.conn: device for device in devices} - self.handle_indexes = {map_rawbuf(rawbufs[i]): i for i in sorted(dedup(self.input_replace.values()))} - - self.template: list[RemoteRequest] = [] - - stagings: dict[RemoteDevice|RemoteConnection, list[GraphComputeItem|Transfer]] = defaultdict(list) - clobbered_buffers: set[Buffer] = set() - cur_staging_type: StagingType = StagingType.NONE - - def _flush(new_staging_type:StagingType, force_break:bool=False): - nonlocal cur_staging_type - if cur_staging_type == new_staging_type and not force_break: return - # Pre-sync - if cur_staging_type == StagingType.TRANSFER: - for sdev,ddev in itertools.permutations(c2d.values(), 2): - self.template.append(Event(ddev.session, event:=next(ddev.event_num), session=sdev.session)) - self.template.append(Wait(event, session=ddev.session)) - # Flush - for dev in devices: - dk = dev_key(dev) - staging = stagings[dk] - if not staging: continue - match cur_staging_type: - case StagingType.GRAPH: - bufs = tuple(map_rawbuf(rawbufs[i]) for i in sorted(dedup(self.input_replace.values())) if dev_key(rd(Device[rawbufs[i].device])) == dk) - dev.q(GraphAlloc(graph_num:=next(dev.graph_num), tuple(staging), tuple(bufs), var_vals)) - self.template.append(GraphExec(graph_num, bufs, var_vals, wait=False, session=dev.session)) - case StagingType.TRANSFER: - st = cast(list[Transfer], staging) - for host in dedup(t.dsession.host for t in st): - sbuffer_nums = [(unwrap(t.session), t.buffer_num) for t in st if t.dsession.host == host] - dbuffer_nums = [(t.dsession, t.dbuffer_num) for t in st if t.dsession.host == host] - self.template.append(BatchTransfer(sbuffer_nums, dbuffer_nums, session=dev.session)) - staging.clear() - # Post-sync - if cur_staging_type == StagingType.TRANSFER: - for sdev,ddev in itertools.permutations(c2d.values(), 2): - self.template.append(Event(ddev.session, event:=next(ddev.event_num), session=sdev.session)) - self.template.append(Wait(event, session=ddev.session)) - cur_staging_type = new_staging_type - clobbered_buffers.clear() - - for ji in jit_cache: + self.devices = dedup(flatten([[Device[unwrap(buf).device] for buf in ji.bufs] for ji in jit_cache])) + if not all_same([d.conn for d in self.devices]): raise GraphException(f"Cross-host remote graph is not supported ({self.devices})") + self.iids = sorted(self.input_replace.values()) + def _process_ji(ji: ExecItem): match ji.prg: case CompiledRunner(): - _flush(StagingType.GRAPH) - gi = GraphComputeItem(ji.prg.dev.session, ji.prg._prg.name, ji.prg._prg.datahash, tuple(unwrap(buf)._buf for buf in ji.bufs), - tuple(ji.prg.p.vars), ji.fixedvars, tuple(ji.prg.p.ins), tuple(ji.prg.p.outs), - tuple(ji.prg.p.global_size) if ji.prg.p.global_size is not None else None, - tuple(ji.prg.p.local_size) if ji.prg.p.local_size is not None else None) - stagings[dev_key(ji.prg.dev)].append(gi) + return GraphComputeItem(ji.prg.dev.session, ji.prg._prg.name, ji.prg._prg.datahash, tuple(unwrap(buf)._buf for buf in ji.bufs), + tuple(ji.prg.p.vars), ji.fixedvars, tuple(ji.prg.p.ins), tuple(ji.prg.p.outs), + tuple(ji.prg.p.global_size) if ji.prg.p.global_size is not None else None, + tuple(ji.prg.p.local_size) if ji.prg.p.local_size is not None else None) case BufferXfer(): dest, src = ji.bufs[0:2] - dest_dev, src_dev = cast(RemoteDevice, Device[unwrap(dest).device]), cast(RemoteDevice, Device[unwrap(src).device]) assert dest is not None and src is not None, ji - ti = Transfer(session=src_dev.session, buffer_num=src._buf, dsession=dest_dev.session, dbuffer_num=dest._buf) - if dev_key(dest_dev) == dev_key(src_dev): - _flush(StagingType.GRAPH) - stagings[dev_key(src_dev)].append(ti) - elif dest_dev.conn == src_dev.conn: - _flush(StagingType.NONE) - self.template.append(ti) - else: - _flush(StagingType.TRANSFER, force_break=src in clobbered_buffers) - clobbered_buffers.add(dest) - stagings[dev_key(src_dev)].append(ti) - case _: raise NotImplementedError(ji.prg) - _flush(StagingType.NONE) + return Transfer(session=cast(RemoteDevice, Device[src.device]).session, buffer_num=src._buf, + dsession=cast(RemoteDevice, Device[dest.device]).session, dbuffer_num=dest._buf) + self.graph_num = next(self.devices[0].graph_num) + self.devices[0].q(GraphAlloc(self.graph_num, tuple(_process_ji(ji) for ji in jit_cache), self.map_rawbufs(rawbufs), var_vals)) + def __del__(self): - for req in self.template: - match req: - case GraphExec(): RemoteConnection(unwrap(req.session).host).q(GraphFree(req.graph_num, session=req.session)) + # This can happen if `GraphException` is thrown at the very start + if hasattr(self, "graph_num"): self.devices[0].q(GraphFree(self.graph_num)) + + def map_rawbufs(self, rawbufs:list[Buffer]): + return tuple((cast(RemoteDevice, Device[rawbufs[i].device]).session, rawbufs[i]._buf) for i in self.iids) + def __call__(self, rawbufs: list[Buffer], var_vals: dict[Variable, int], wait=False): - if wait: st = time.perf_counter() - rmap = {orig: map_rawbuf(rawbufs[replace_idx]) for orig,replace_idx in self.handle_indexes.items()} - for req in self.template: - match req: - case GraphExec(): - req = replace(req, bufs=tuple(rmap[buf] for buf in req.bufs), var_vals=var_vals, wait=wait) - case Transfer(): - if (req.session, req.buffer_num) in rmap: req = replace(req, buffer_num=rmap[(req.session, req.buffer_num)][1]) - if (req.dsession, req.dbuffer_num) in rmap: req = replace(req, dbuffer_num=rmap[(req.dsession, req.dbuffer_num)][1]) - case BatchTransfer(): - req = replace(req, sbuffer_nums=[rmap.get(b, b) for b in req.sbuffer_nums], dbuffer_nums=[rmap.get(b, b) for b in req.dbuffer_nums]) - case Event()|Wait(): - pass # event number can be reused - case _: raise NotImplementedError(req) - RemoteConnection(unwrap(req.session).host).q(req) - if wait: - RemoteConnection(unwrap(req.session).host).batch_submit() - return time.perf_counter() - st + self.devices[0].q(GraphExec(self.graph_num, self.map_rawbufs(rawbufs), var_vals, wait)) + if wait: return float(self.devices[0].conn.batch_submit()) + +class RemoteMultiGraph(RemoteGraph, MultiGraphRunner): pass diff --git a/tinygrad_repo/tinygrad/runtime/ops_amd.py b/tinygrad_repo/tinygrad/runtime/ops_amd.py index c0c27cc71..a286a2d57 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_amd.py +++ b/tinygrad_repo/tinygrad/runtime/ops_amd.py @@ -1,13 +1,13 @@ from __future__ import annotations from typing import cast, ClassVar -import os, ctypes, ctypes.util, struct, hashlib, functools, importlib, mmap, errno, array, contextlib, sys, weakref +import os, ctypes, ctypes.util, struct, hashlib, functools, importlib, mmap, errno, array, contextlib, sys, weakref, traceback assert sys.platform != 'win32' from dataclasses import dataclass from tinygrad.runtime.support.hcq import HCQCompiled, HCQAllocator, HCQBuffer, HWQueue, CLikeArgsState, HCQSignal, HCQProgram, FileIOInterface -from tinygrad.runtime.support.hcq import MMIOInterface, BumpAllocator +from tinygrad.runtime.support.hcq import MMIOInterface from tinygrad.uop.ops import sint -from tinygrad.device import Compiled, DMAFdRef, BufferSpec -from tinygrad.helpers import getenv, to_mv, round_up, data64_le, DEBUG, AMD_LLVM, PROFILE, ProfileEvent, suppress_finalizing, lo32, hi32 +from tinygrad.device import Compiled, ProfileEvent, BufferSpec, PROFILE +from tinygrad.helpers import getenv, to_mv, round_up, data64_le, all_same, flatten, DEBUG from tinygrad.renderer.cstyle import AMDRenderer from tinygrad.renderer.llvmir import AMDLLVMRenderer from tinygrad.runtime.autogen import kfd, hsa, pci, sqtt @@ -15,7 +15,7 @@ from tinygrad.runtime.autogen.am import am from tinygrad.runtime.support.compiler_amd import HIPCompiler, AMDLLVMCompiler from tinygrad.runtime.support.elf import elf_loader from tinygrad.runtime.support.am.amdev import AMDev, AMMemoryManager -from tinygrad.runtime.support.amd import AMDReg, AMDIP, import_module, import_soc, setup_pci_bars +from tinygrad.runtime.support.amd import AMDReg, AMDIP, import_module, setup_pci_bars from tinygrad.runtime.support.system import System, PCIIfaceBase, PCIAllocationMeta, MAP_FIXED, MAP_NORESERVE from tinygrad.runtime.support.usb import ASM24Controller, USBMMIOInterface if getenv("IOCTL"): import extra.hip_gpu_driver.hip_ioctl # noqa: F401 # pylint: disable=unused-import @@ -24,15 +24,14 @@ EVENT_INDEX_PARTIAL_FLUSH = 4 # based on a comment in nvd.h WAIT_REG_MEM_FUNCTION_EQ = 3 # == WAIT_REG_MEM_FUNCTION_NEQ = 4 # != WAIT_REG_MEM_FUNCTION_GEQ = 5 # >= -AQL_HDR = (1 << hsa.HSA_PACKET_HEADER_BARRIER) | (hsa.HSA_FENCE_SCOPE_SYSTEM << hsa.HSA_PACKET_HEADER_SCACQUIRE_FENCE_SCOPE) \ - | (hsa.HSA_FENCE_SCOPE_SYSTEM << hsa.HSA_PACKET_HEADER_SCRELEASE_FENCE_SCOPE) class AMDSignal(HCQSignal): - def __init__(self, *args, **kwargs): super().__init__(*args, **{**kwargs, 'timestamp_divider': 100}) + def __init__(self, base_buf:HCQBuffer|None=None, **kwargs): + super().__init__(base_buf, **kwargs, timestamp_divider=100, dev_t=AMDDevice) def _sleep(self, time_spent_waiting_ms:int): # Resonable to sleep for long workloads (which take more than 2s) and only timeline signals. - if time_spent_waiting_ms > 2000 and self.is_timeline and self.owner is not None: self.owner.iface.sleep(200) + if time_spent_waiting_ms > 2000 and self.timeline_for_device is not None: self.timeline_for_device.iface.sleep(200) class AMDComputeQueue(HWQueue): def __init__(self, dev:AMDDevice): @@ -47,12 +46,12 @@ class AMDComputeQueue(HWQueue): def wreg(self, reg:AMDReg, *args:sint, **kwargs:int): if bool(args) == bool(kwargs): raise RuntimeError('One (and only one) of *args or **kwargs must be specified') - if self.pm4.PACKET3_SET_SH_REG_START <= reg.addr[0] < self.pm4.PACKET3_SET_SH_REG_END: + if self.pm4.PACKET3_SET_SH_REG_START <= reg.addr < self.pm4.PACKET3_SET_SH_REG_END: set_packet, set_packet_start = self.pm4.PACKET3_SET_SH_REG, self.pm4.PACKET3_SET_SH_REG_START - elif self.pm4.PACKET3_SET_UCONFIG_REG_START <= reg.addr[0] < self.pm4.PACKET3_SET_UCONFIG_REG_START + 2**16-1: + elif self.pm4.PACKET3_SET_UCONFIG_REG_START <= reg.addr < self.pm4.PACKET3_SET_UCONFIG_REG_START + 2**16-1: set_packet, set_packet_start = self.pm4.PACKET3_SET_UCONFIG_REG, self.pm4.PACKET3_SET_UCONFIG_REG_START - else: raise RuntimeError(f'Cannot set {reg.name} ({reg.addr[0]}) via pm4 packet') - self.pkt3(set_packet, reg.addr[0] - set_packet_start, *(args or (reg.encode(**kwargs),))) + else: raise RuntimeError(f'Cannot set {reg.name} ({reg.addr}) via pm4 packet') + self.pkt3(set_packet, reg.addr - set_packet_start, *(args or (reg.encode(**kwargs),))) @contextlib.contextmanager def pred_exec(self, xcc_mask:int): @@ -108,13 +107,31 @@ class AMDComputeQueue(HWQueue): self.pkt3(self.pm4.PACKET3_RELEASE_MEM, event_dw | cache_flags_dw, memsel_dw, *data64_le(address), *data64_le(value), ctxid) + def xcc_barrier(self): + if self.dev.xcc_sync is None: return self + assert self.dev.xccs == 8, 'only 8 XCCs supported' + a, b = self.dev.xcc_sync + mem_eq = self.pm4.WAIT_REG_MEM_FUNCTION(WAIT_REG_MEM_FUNCTION_EQ) | self.pm4.WAIT_REG_MEM_MEM_SPACE(1) + self.pkt3(self.pm4.PACKET3_ATOMIC_MEM, self.soc.TC_OP_ATOMIC_ADD_RTN_32, *data64_le(a.value_addr), *data64_le(1), *data64_le(0), 0x10) # a += 1 + self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, mem_eq, *data64_le(a.value_addr), 0, 0b111, 0x80) # a == 0 (mod 8) via bitmask + self.pkt3(self.pm4.PACKET3_ATOMIC_MEM, self.soc.TC_OP_ATOMIC_ADD_RTN_32, *data64_le(b.value_addr), *data64_le(1), *data64_le(0), 0x10) # b += 1 + self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, mem_eq, *data64_le(b.value_addr), 0, 0b111, 0x80) # b == 0 (mod 8) via bitmask + return self + def memory_barrier(self): pf = '' if self.nbio.version[0] == 2 else '0' if self.nbio.version[:2] != (7, 11) else '1' - self.wait_reg_mem(reg_req=getattr(self.nbio, f'regBIF_BX_PF{pf}_GPU_HDP_FLUSH_REQ').addr[0], - reg_done=getattr(self.nbio, f'regBIF_BX_PF{pf}_GPU_HDP_FLUSH_DONE').addr[0], value=0xffffffff) + self.wait_reg_mem(reg_req=getattr(self.nbio, f'regBIF_BX_PF{pf}_GPU_HDP_FLUSH_REQ').addr, + reg_done=getattr(self.nbio, f'regBIF_BX_PF{pf}_GPU_HDP_FLUSH_DONE').addr, value=0xffffffff) self.acquire_mem() return self + def xcc_config(self): + self.wreg(self.gc.regCOMPUTE_TG_CHUNK_SIZE, 1) + for xcc_id in range(self.dev.xccs): + with self.pred_exec(xcc_mask=1 << xcc_id): + self.wreg(self.dev.regCOMPUTE_CURRENT_LOGIC_XCC_ID, xcc_id) + return self + def spi_config(self, tracing:bool): self.wreg(self.gc.regSPI_CONFIG_CNTL, ps_pkr_priority_cntl=3, exp_priority_order=3, gpr_write_priority=0x2c688, enable_sqg_bop_events=int(tracing), enable_sqg_top_events=int(tracing)) @@ -174,17 +191,17 @@ class AMDComputeQueue(HWQueue): self.wreg(self.gc.regGRBM_GFX_INDEX, se_index=se, instance_broadcast_writes=1) # Wait for FINISH_PENDING==0 self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, self.pm4.WAIT_REG_MEM_FUNCTION(WAIT_REG_MEM_FUNCTION_EQ), - self.gc.regSQ_THREAD_TRACE_STATUS.addr[0], 0, 0, self.gc.regSQ_THREAD_TRACE_STATUS.fields_mask('finish_pending'), 4) + self.gc.regSQ_THREAD_TRACE_STATUS.addr, 0, 0, self.gc.regSQ_THREAD_TRACE_STATUS.fields_mask('finish_pending'), 4) # Wait for FINISH_DONE!=0 self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, self.pm4.WAIT_REG_MEM_FUNCTION(WAIT_REG_MEM_FUNCTION_NEQ), - self.gc.regSQ_THREAD_TRACE_STATUS.addr[0], 0, 0, self.gc.regSQ_THREAD_TRACE_STATUS.fields_mask('finish_done'), 4) + self.gc.regSQ_THREAD_TRACE_STATUS.addr, 0, 0, self.gc.regSQ_THREAD_TRACE_STATUS.fields_mask('finish_done'), 4) # Disable SQTT self.sqtt_config(tracing=False) # Wait for BUSY==0 self.pkt3(self.pm4.PACKET3_WAIT_REG_MEM, self.pm4.WAIT_REG_MEM_FUNCTION(WAIT_REG_MEM_FUNCTION_EQ), - self.gc.regSQ_THREAD_TRACE_STATUS.addr[0], 0, 0, self.gc.regSQ_THREAD_TRACE_STATUS.fields_mask('busy'), 4) + self.gc.regSQ_THREAD_TRACE_STATUS.addr, 0, 0, self.gc.regSQ_THREAD_TRACE_STATUS.fields_mask('busy'), 4) # Copy WPTR to memory (src_sel = perf, dst_sel = tc_l2, wr_confirm = True) - self.pkt3(self.pm4.PACKET3_COPY_DATA, 1 << 20 | 2 << 8 | 4, self.gc.regSQ_THREAD_TRACE_WPTR.addr[0], 0, *data64_le(wptrs.va_addr+(se*4))) + self.pkt3(self.pm4.PACKET3_COPY_DATA, 1 << 20 | 2 << 8 | 4, self.gc.regSQ_THREAD_TRACE_WPTR.addr, 0, *data64_le(wptrs.va_addr+(se*4))) # Restore global broadcasting self.wreg(self.gc.regGRBM_GFX_INDEX, se_broadcast_writes=1, sa_broadcast_writes=1, instance_broadcast_writes=1) self.spi_config(tracing=False) @@ -259,10 +276,16 @@ class AMDComputeQueue(HWQueue): if prg.dev.sqtt_enabled: self.pkt3(self.pm4.PACKET3_EVENT_WRITE, self.pm4.EVENT_TYPE(self.soc.THREAD_TRACE_MARKER) | self.pm4.EVENT_INDEX(0)) self.pkt3(self.pm4.PACKET3_EVENT_WRITE, self.pm4.EVENT_TYPE(self.soc.CS_PARTIAL_FLUSH) | self.pm4.EVENT_INDEX(EVENT_INDEX_PARTIAL_FLUSH)) + + if self.dev.xccs > 1: + self.release_mem(cache_flush=True) + self.acquire_mem(gli=0) + self.xcc_barrier() return self def wait(self, signal:AMDSignal, value:sint=0): self.wait_reg_mem(mem=signal.value_addr, value=value, mask=0xffffffff) + if self.dev.xccs > 1: self.xcc_barrier() return self def timestamp(self, signal:AMDSignal): @@ -276,7 +299,7 @@ class AMDComputeQueue(HWQueue): self.release_mem(signal.value_addr, value, self.pm4.data_sel__mec_release_mem__send_32_bit_low, self.pm4.int_sel__mec_release_mem__send_interrupt_after_write_confirm, cache_flush=True) - if (dev:=signal.owner) is not None and signal.is_timeline and not dev.is_am(): + if (dev:=signal.timeline_for_device) is not None and not dev.is_am(): self.release_mem(dev.queue_event_mailbox_ptr, dev.queue_event.event_id, self.pm4.data_sel__mec_release_mem__send_32_bit_low, self.pm4.int_sel__mec_release_mem__send_interrupt_after_write_confirm, ctxid=dev.queue_event.event_id) return self @@ -307,41 +330,6 @@ class AMDComputeQueue(HWQueue): dev.compute_queue.put_value += len(cmds) dev.compute_queue.signal_doorbell(dev) -class AMDComputeAQLQueue(AMDComputeQueue): - def exec(self, prg:AMDProgram, args_state:CLikeArgsState, global_size:tuple[sint, ...], local_size:tuple[sint, ...]): - self.bind_args_state(args_state) - self._q.append(pkt:=hsa.hsa_kernel_dispatch_packet_t(header=AQL_HDR | (hsa.HSA_PACKET_TYPE_KERNEL_DISPATCH << hsa.HSA_PACKET_HEADER_TYPE), - setup=3< 0: dev.compute_queue.ring.view(offset=0, fmt='B')[:tail_bytes] = aql_bytes[cp_bytes:] - dev.compute_queue.put_value += len(aql_bytes) // 64 - dev.compute_queue.signal_doorbell(dev, doorbell_value=dev.compute_queue.put_value-1) - class AMDCopyQueue(HWQueue): def __init__(self, dev, max_copy_size=0x40000000): self.dev, self.sdma, self.internal_cmd_sizes, self.max_copy_size = dev, dev.sdma, [], max_copy_size @@ -367,7 +355,7 @@ class AMDCopyQueue(HWQueue): fence_flags = self.sdma.SDMA_PKT_FENCE_HEADER_MTYPE(3) if self.dev.target >= (10,0,0) else 0 self.q(self.sdma.SDMA_OP_FENCE | fence_flags, *data64_le(signal.value_addr), value) - if (dev:=signal.owner) is not None and signal.is_timeline and not dev.is_am(): + if (dev:=signal.timeline_for_device) is not None and not dev.is_am(): self.q(self.sdma.SDMA_OP_FENCE | fence_flags, *data64_le(dev.queue_event_mailbox_ptr), dev.queue_event.event_id) self.q(self.sdma.SDMA_OP_TRAP, self.sdma.SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(dev.queue_event.event_id)) elif dev is not None and dev.is_am(): self.q(self.sdma.SDMA_OP_TRAP, self.sdma.SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)) @@ -398,6 +386,9 @@ class AMDCopyQueue(HWQueue): self._q, self.cmd_sizes = hw_view, [len(self.indirect_cmd)] def _submit(self, dev:AMDDevice): + # usb devices run in single-step mode, so they can't overrun the queue. + if not dev.is_usb() and dev.sdma_queue.put_value - dev.sdma_queue.read_ptr > dev.sdma_queue.ring.nbytes: raise RuntimeError("SDMA queue overrun") + if self.binded_device == dev: # An IB packet must end on a 8 DW boundary. add = (8 - (((dev.sdma_queue.put_value % 32) // 4) + len(self.indirect_cmd) % 8)) % 8 @@ -413,12 +404,7 @@ class AMDCopyQueue(HWQueue): tail_blit_dword += cmdsz # Force align of submits to hit our usb layer write cache. - if (rem_packet_cnt := len(cmds) - tail_blit_dword) > 0 and dev.is_usb(): tail_blit_dword = 0 - - # USB devices run in single-step mode, so they can't overrun the queue. - total_bytes = (tail_blit_dword * 4 if rem_packet_cnt == 0 else -dev.sdma_queue.put_value % dev.sdma_queue.ring.nbytes) + rem_packet_cnt * 4 - assert total_bytes < dev.sdma_queue.ring.nbytes, "SDMA queue overrun" - while not dev.is_usb() and dev.sdma_queue.put_value + total_bytes - dev.sdma_queue.read_ptr > dev.sdma_queue.ring.nbytes: pass + if dev.is_usb() and (rem_packet_cnt := len(cmds) - tail_blit_dword) > 0: tail_blit_dword = 0 start_idx = (dev.sdma_queue.put_value % dev.sdma_queue.ring.nbytes) // 4 dev.sdma_queue.ring[start_idx : start_idx + tail_blit_dword] = array.array('I', cmds[:tail_blit_dword]) @@ -439,19 +425,14 @@ class AMDProgram(HCQProgram): # TODO; this API needs the type signature of the function and global_size/local_size self.dev, self.name, self.lib = dev, name, lib - image, sections, relocs = elf_loader(self.lib) - - rodata_entry = next((sh.header.sh_addr for sh in sections if sh.name == ".rodata"), -1) - assert rodata_entry >= 0, ".rodata section not found" - - for apply_image_offset, rel_sym_offset, typ, addent in relocs: - if typ == 5: image[apply_image_offset:apply_image_offset+8] = struct.pack('= 0 and text_entry >= 0, ".text or .rodata section not found" self.group_segment_size = image[rodata_entry:rodata_entry+4].cast("I")[0] self.private_segment_size = image[rodata_entry+4:rodata_entry+8].cast("I")[0] self.kernargs_segment_size = image[rodata_entry+8:rodata_entry+12].cast("I")[0] @@ -469,8 +450,8 @@ class AMDProgram(HCQProgram): self.rsrc1: int = code.compute_pgm_rsrc1 | ((1 << 20) if (11,0,0) <= self.dev.target < (12,0,0) else 0) self.rsrc2: int = code.compute_pgm_rsrc2 | (lds_size << 15) self.rsrc3: int = image[rodata_entry+44:rodata_entry+48].cast("I")[0] # NOTE: kernel descriptor, not in amd_kernel_code_t struct - self.aql_prog_addr: int = self.lib_gpu.va_addr + rodata_entry self.prog_addr: int = self.lib_gpu.va_addr + rodata_entry + code.kernel_code_entry_byte_offset + if code.kernel_code_entry_byte_offset == 0: self.prog_addr = self.lib_gpu.va_addr + text_entry # Some programs use hsa_kernel_dispatch_packet_t to read workgroup sizes during execution. # The packet is represented as a pointer and set up in SGPRs. Space for the packet is allocated as part of the kernel arguments. self.enable_dispatch_ptr: int = code.kernel_code_properties & hsa.AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_DISPATCH_PTR @@ -486,18 +467,17 @@ class AMDProgram(HCQProgram): class AMDAllocator(HCQAllocator['AMDDevice']): def __init__(self, dev:AMDDevice): super().__init__(dev, copy_bufs=getattr(dev.iface, 'copy_bufs', None), max_copyout_size=0x1000 if dev.is_usb() else None) - if hasattr(dev.iface, "as_dmaref"): self._as_dmaref = dev.iface.as_dmaref - self.supports_copy_from_disk = not dev.is_usb() def _alloc(self, size:int, options:BufferSpec) -> HCQBuffer: return self.dev.iface.alloc(size, host=options.host, uncached=options.uncached, cpu_access=options.cpu_access) - @suppress_finalizing def _free(self, opaque, options:BufferSpec): - self.dev.synchronize() - self.dev.iface.free(opaque) + try: + self.dev.synchronize() + self.dev.iface.free(opaque) + except AttributeError: pass - def _map(self, buf:HCQBuffer): return self.dev.iface.map(buf._base if buf._base is not None else buf) + def map(self, buf:HCQBuffer): self.dev.iface.map(buf._base if buf._base is not None else buf) @dataclass(frozen=True) class ProfileSQTTEvent(ProfileEvent): device:str; se:int; blob:bytes; itrace:bool # noqa: E702 @@ -513,7 +493,13 @@ class AMDQueueDesc: @property def read_ptr(self): return min(p[0] for p in self.read_ptrs) - def signal_doorbell(self, dev, doorbell_value:int|None=None): + @classmethod + def multi(cls, *queues: AMDQueueDesc): + assert all_same([(q.ring.addr, q.put_value) for q in queues]), f"All queues must have the same ring and put_value: {queues}" + return cls(ring=queues[0].ring, put_value=queues[0].put_value, doorbells=flatten(q.doorbells for q in queues), + read_ptrs=flatten(q.read_ptrs for q in queues), write_ptrs=flatten(q.write_ptrs for q in queues)) + + def signal_doorbell(self, dev): for write_ptr in self.write_ptrs: write_ptr[0] = self.put_value # Ensure all prior writes are visible to the GPU. @@ -521,7 +507,7 @@ class AMDQueueDesc: # Flush hdp if queue is in dev mem. if dev.is_am() and not dev.is_usb(): dev.iface.dev_impl.gmc.flush_hdp() - for doorbell in self.doorbells: doorbell[0] = self.put_value if doorbell_value is None else doorbell_value + for doorbell in self.doorbells: doorbell[0] = self.put_value class KFDIface: kfd:FileIOInterface|None = None @@ -551,10 +537,10 @@ class KFDIface: self.props = {(p:=l.split())[0]: int(p[1]) for l in FileIOInterface(f"{kfd_topo_path}/{KFDIface.gpus[device_id]}/properties").read().splitlines()} ip_base = f"/sys/class/drm/renderD{self.props['drm_render_minor']}/device/ip_discovery/die/0" id2ip = {am.GC_HWID: am.GC_HWIP, am.SDMA0_HWID: am.SDMA0_HWIP, am.NBIF_HWID: am.NBIF_HWIP} - ip_hw = [(id2ip[int(hwid)], int(hwid)) for hwid in FileIOInterface(ip_base).listdir() if hwid.isnumeric() and int(hwid) in id2ip] - self.ip_versions = {ip:tuple(int(FileIOInterface(f'{ip_base}/{hw}/0/{part}').read()) for part in ['major','minor','revision']) for ip,hw in ip_hw} - self.ip_offsets = {ip:{int(i):tuple(int(x, 16) for x in FileIOInterface(f'{ip_base}/{hw}/{i}/base_addr').read().splitlines()) - for i in FileIOInterface(f'{ip_base}/{hw}').listdir()} for ip,hw in ip_hw } + self.ip_versions = {id2ip[int(hwid)]:tuple(int(FileIOInterface(f'{ip_base}/{hwid}/0/{part}').read()) for part in ['major', 'minor', 'revision']) + for hwid in FileIOInterface(ip_base).listdir() if hwid.isnumeric() and int(hwid) in id2ip} + self.ip_offsets = {id2ip[int(hwid)]:tuple(int(x, 16) for x in FileIOInterface(f'{ip_base}/{hwid}/0/base_addr').read().splitlines()) + for hwid in FileIOInterface(ip_base).listdir() if hwid.isnumeric() and int(hwid) in id2ip} self.drm_fd = FileIOInterface(f"/dev/dri/renderD{self.props['drm_render_minor']}", os.O_RDWR) kfd.AMDKFD_IOC_ACQUIRE_VM(KFDIface.kfd, drm_fd=self.drm_fd.fd, gpu_id=self.gpu_id) @@ -575,7 +561,7 @@ class KFDIface: self.mem_fault_event = kfd.AMDKFD_IOC_CREATE_EVENT(KFDIface.kfd, event_type=kfd.KFD_IOC_EVENT_MEMORY) self.hw_fault_event = kfd.AMDKFD_IOC_CREATE_EVENT(KFDIface.kfd, event_type=kfd.KFD_IOC_EVENT_HW_EXCEPTION) - def alloc(self, size:int, host=False, uncached=False, cpu_access=False, contiguous=False, cpu_addr=None) -> HCQBuffer: + def alloc(self, size:int, host=False, uncached=False, cpu_access=False, contiguous=False) -> HCQBuffer: flags = kfd.KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | kfd.KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE | kfd.KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE if uncached: flags |= kfd.KFD_IOC_ALLOC_MEM_FLAGS_COHERENT | kfd.KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED | kfd.KFD_IOC_ALLOC_MEM_FLAGS_GTT @@ -584,7 +570,7 @@ class KFDIface: if cpu_access or host: flags |= kfd.KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC if flags & kfd.KFD_IOC_ALLOC_MEM_FLAGS_USERPTR: - buf = addr = cpu_addr or FileIOInterface.anon_mmap(0, size, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | mmap.MAP_ANONYMOUS, 0) + buf = addr = FileIOInterface.anon_mmap(0, size, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | mmap.MAP_ANONYMOUS, 0) else: buf, addr = 0, FileIOInterface.anon_mmap(0, size, 0, mmap.MAP_PRIVATE | mmap.MAP_ANONYMOUS | MAP_NORESERVE, 0) try: mem = kfd.AMDKFD_IOC_ALLOC_MEMORY_OF_GPU(self.kfd, va_addr=addr, size=size, base=addr, length=size, gpu_id=self.gpu_id, @@ -599,37 +585,31 @@ class KFDIface: buf = self.drm_fd.mmap(mem.va_addr, mem.size, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED | MAP_FIXED, mem.mmap_offset) assert addr == buf == mem.va_addr - view = MMIOInterface(mem.va_addr, mem.size, fmt='B') if cpu_access or host else None - self.map(hcqbuf:=HCQBuffer(mem.va_addr, mem.size, meta=mem, view=view, owner=self.dev)) + self.map(hcqbuf:=HCQBuffer(mem.va_addr, mem.size, meta=mem, view=MMIOInterface(mem.va_addr, mem.size, fmt='B') if cpu_access or host else None)) return hcqbuf def free(self, mem): - if len(mem.mapped_devs) > 0: - gpus = (ctypes.c_int32 * len(mem.mapped_devs))(*[x.iface.gpu_id for x in mem.mapped_devs]) - stm = kfd.AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU(self.kfd, handle=mem.meta.handle, device_ids_array_ptr=ctypes.addressof(gpus), n_devices=len(gpus)) + if len(gpus:=getattr(mem.meta, "mapped_gpu_ids", [])): + c_gpus = (ctypes.c_int32 * len(gpus))(*gpus) + stm = kfd.AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU(self.kfd, handle=mem.meta.handle, device_ids_array_ptr=ctypes.addressof(c_gpus), n_devices=len(gpus)) assert stm.n_success == len(gpus) if mem.va_addr: FileIOInterface.munmap(mem.va_addr, mem.size) kfd.AMDKFD_IOC_FREE_MEMORY_OF_GPU(self.kfd, handle=mem.meta.handle) - def as_dmaref(self, mem:HCQBuffer) -> DMAFdRef: - base = mem._base if mem._base is not None else mem - dmaref = DMAFdRef(kfd.AMDKFD_IOC_EXPORT_DMABUF(KFDIface.kfd, handle=base.meta.handle, flags=0).dmabuf_fd, mem.va_addr-base.va_addr, mem.size) - weakref.finalize(dmaref, os.close, dmaref.fd) - return dmaref - def map(self, mem): - if mem.owner is not None and mem.owner._is_cpu(): return self.alloc(mem.size, host=True, cpu_addr=mem.va_addr) + if self.gpu_id in getattr(mem.meta, "mapped_gpu_ids", []): return + mem.meta.__setattr__("mapped_gpu_ids", getattr(mem.meta, "mapped_gpu_ids", []) + [self.gpu_id]) + c_gpus = (ctypes.c_int32 * len(mem.meta.mapped_gpu_ids))(*mem.meta.mapped_gpu_ids) + stm = kfd.AMDKFD_IOC_MAP_MEMORY_TO_GPU(self.kfd, handle=mem.meta.handle, device_ids_array_ptr=ctypes.addressof(c_gpus), + n_devices=len(mem.meta.mapped_gpu_ids)) + assert stm.n_success == len(mem.meta.mapped_gpu_ids) - c_gpus = (ctypes.c_int32 * 1)(self.gpu_id) - stm = kfd.AMDKFD_IOC_MAP_MEMORY_TO_GPU(self.kfd, handle=mem.meta.handle, device_ids_array_ptr=ctypes.addressof(c_gpus), n_devices=1) - assert stm.n_success == 1 - - def create_queue(self, queue_type, ring, gart, rptr, wptr, eop_buffer=None, cwsr_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, xcc_id=0): + def create_queue(self, queue_type, ring, gart, eop_buffer=None, cwsr_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, xcc_id=0): queue = kfd.AMDKFD_IOC_CREATE_QUEUE(KFDIface.kfd, ring_base_address=ring.va_addr, ring_size=ring.size, gpu_id=self.gpu_id, queue_type=queue_type, queue_percentage=kfd.KFD_MAX_QUEUE_PERCENTAGE|(xcc_id<<8), queue_priority=kfd.KFD_MAX_QUEUE_PRIORITY, eop_buffer_address=eop_buffer.va_addr if eop_buffer else 0, eop_buffer_size=eop_buffer.size if eop_buffer else 0, ctl_stack_size=ctl_stack_size, ctx_save_restore_address=cwsr_buffer.va_addr if cwsr_buffer else 0, ctx_save_restore_size=ctx_save_restore_size, - write_pointer_address=gart.va_addr+wptr, read_pointer_address=gart.va_addr+rptr+8*xcc_id) + write_pointer_address=gart.va_addr, read_pointer_address=gart.va_addr + 8 * (xcc_id + 1)) if not hasattr(self, 'doorbells'): self.doorbells_base = queue.doorbell_offset & (~0x1fff) # doorbell is two pages @@ -655,17 +635,17 @@ class KFDIface: raise RuntimeError("\n".join(report)) class PCIIface(PCIIfaceBase): - gpus:ClassVar[list[str]] = [] - def __init__(self, dev, dev_id): super().__init__(dev, dev_id, vendor=0x1002, devices=[0x744c, 0x7480, 0x7550], bars=[0, 2, 5], vram_bar=0, va_start=AMMemoryManager.va_allocator.base, va_size=AMMemoryManager.va_allocator.size) - self._setup_adev(self.pci_dev.pcibus, self.pci_dev.map_bar(0), self.pci_dev.map_bar(2, fmt='Q'), self.pci_dev.map_bar(5, fmt='I')) + self._setup_adev(self.pci_dev.pcibus, self.pci_dev.map_bar(0), dbell:=self.pci_dev.map_bar(2, fmt='Q'), self.pci_dev.map_bar(5, fmt='I')) + self.doorbell_cpu_addr = dbell.addr self.pci_dev.write_config(pci.PCI_COMMAND, self.pci_dev.read_config(pci.PCI_COMMAND, 2) | pci.PCI_COMMAND_MASTER, 2) def _setup_adev(self, name, vram:MMIOInterface, doorbell:MMIOInterface, mmio:MMIOInterface, dma_regions:list[tuple[int, MMIOInterface]]|None=None): self.dev_impl:AMDev = AMDev(name, vram, doorbell, mmio, dma_regions) - self.ip_offsets, self.ip_versions = self.dev_impl.regs_offset, self.dev_impl.ip_ver + self.ip_versions = self.dev_impl.ip_ver + self.ip_offsets = {hwip: tuple(instances[0]) for hwip,instances in self.dev_impl.regs_offset.items()} gfxver = int(f"{self.dev_impl.ip_ver[am.GC_HWIP][0]:02d}{self.dev_impl.ip_ver[am.GC_HWIP][1]:02d}{self.dev_impl.ip_ver[am.GC_HWIP][2]:02d}") array_count = self.dev_impl.gc_info.gc_num_sa_per_se * self.dev_impl.gc_info.gc_num_se @@ -674,19 +654,18 @@ class PCIIface(PCIIfaceBase): 'max_slots_scratch_cu': self.dev_impl.gc_info.gc_max_scratch_slots_per_cu, 'max_waves_per_simd': self.dev_impl.gc_info.gc_max_waves_per_simd, 'simd_arrays_per_engine': self.dev_impl.gc_info.gc_num_sa_per_se, 'lds_size_in_kb': self.dev_impl.gc_info.gc_lds_size} - def create_queue(self, queue_type, ring, gart, rptr, wptr, eop_buffer=None, cwsr_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, xcc_id=0): + def create_queue(self, queue_type, ring, gart, eop_buffer=None, cwsr_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, xcc_id=0): assert cwsr_buffer is None, "no cwsr buffer for am" if queue_type == kfd.KFD_IOC_QUEUE_TYPE_SDMA: - self.dev_impl.sdma.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr+rptr, wptr_addr=gart.va_addr+wptr, + self.dev_impl.sdma.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10, doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0), pipe=0, queue=0) else: - self.dev_impl.gfx.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr+rptr, wptr_addr=gart.va_addr+wptr, - eop_addr=eop_buffer.va_addr, eop_size=eop_buffer.size, doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_MEC_RING0), pipe=0, queue=0, - aql=(queue_type==kfd.KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)) + self.dev_impl.gfx.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10, + eop_addr=eop_buffer.va_addr, eop_size=eop_buffer.size, doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_MEC_RING0), pipe=0, queue=0) - return AMDQueueDesc(ring=ring.cpu_view().view(fmt='I'), doorbells=[self.dev_impl.doorbell64.view(doorbell_index * 8, 8, fmt='Q')], - read_ptrs=[gart.cpu_view().view(offset=rptr, size=8, fmt='Q')], write_ptrs=[gart.cpu_view().view(offset=wptr, size=8, fmt='Q')]) + return AMDQueueDesc(ring=MMIOInterface(ring.va_addr, ring.size, fmt='I'), read_ptrs=[MMIOInterface(gart.va_addr, 8, fmt='Q')], + write_ptrs=[MMIOInterface(gart.va_addr+0x10, 8, fmt='Q')], doorbells=[MMIOInterface(self.doorbell_cpu_addr + doorbell_index * 8, 8, fmt='Q')]) def sleep(self, timeout): if self.pci_dev.irq_poller is not None and (events_cnt:=len(self.pci_dev.irq_poller.poll(timeout))): @@ -694,8 +673,7 @@ class PCIIface(PCIIfaceBase): self.dev_impl.ih.interrupt_handler() def on_device_hang(self): - devs:list[AMDDevice] = [d for pg in HCQCompiled.peer_groups.values() for d in pg if isinstance(d, AMDDevice) and d.is_am()] - for d in devs: d.iface.dev_impl.gmc.on_interrupt() + for d in self.dev.devices: d.iface.dev_impl.gmc.on_interrupt() raise RuntimeError("Device hang detected") def device_fini(self): self.dev_impl.fini() @@ -717,7 +695,7 @@ class USBIface(PCIIface): def _dma_view(self, ctrl_addr, size): return USBMMIOInterface(self.usb, ctrl_addr, size, fmt='B', pcimem=False) def _dma_region(self, ctrl_addr, sys_addr, size): region = self.dev_impl.mm.map_range(vaddr:=self.dev_impl.mm.alloc_vaddr(size=size), size, [(sys_addr, size)], system=True, uncached=True) - return HCQBuffer(vaddr, size, meta=PCIAllocationMeta(region, has_cpu_mapping=False), view=self._dma_view(ctrl_addr, size), owner=self.dev) + return HCQBuffer(vaddr, size, meta=PCIAllocationMeta(self.dev, [self.dev], region, has_cpu_mapping=False), view=self._dma_view(ctrl_addr, size)) def alloc(self, size:int, host=False, uncached=False, cpu_access=False, contiguous=False, **kwargs) -> HCQBuffer: if (host or (uncached and cpu_access)) and self.sys_next_off + size < self.sys_buf.size: @@ -725,22 +703,41 @@ class USBIface(PCIIface): return self.sys_buf.offset(self.sys_next_off - size, size) am_mapping = self.dev_impl.mm.valloc(size:=round_up(size, 4 << 10), uncached=uncached, contiguous=cpu_access) - return HCQBuffer(am_mapping.va_addr, size, meta=PCIAllocationMeta(am_mapping, has_cpu_mapping=False), - view=USBMMIOInterface(self.usb, self.bars[0][0] + am_mapping.paddrs[0][0], size, fmt='B') if cpu_access else None, owner=self.dev) + return HCQBuffer(am_mapping.va_addr, size, meta=PCIAllocationMeta(self.dev, [self.dev], am_mapping, has_cpu_mapping=False), + view=USBMMIOInterface(self.usb, self.bars[0][0] + am_mapping.paddrs[0][0], size, fmt='B') if cpu_access else None) - def create_queue(self, queue_type, ring, gart, rptr, wptr, eop_buffer=None, cwsr_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, xcc_id=0): - if queue_type == kfd.KFD_IOC_QUEUE_TYPE_COMPUTE: self.usb._pci_cacheable += [(ring.cpu_view().addr, ring.size)] - return super().create_queue(queue_type, ring, gart, rptr, wptr, eop_buffer, cwsr_buffer, ctl_stack_size, ctx_save_restore_size, xcc_id) + def create_queue(self, queue_type, ring, gart, eop_buffer=None, cwsr_buffer=None, ctl_stack_size=0, ctx_save_restore_size=0, xcc_id=0): + if queue_type == kfd.KFD_IOC_QUEUE_TYPE_SDMA: + self.dev_impl.sdma.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10, + doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0), pipe=0, queue=0) + else: + self.dev_impl.gfx.setup_ring(ring_addr=ring.va_addr, ring_size=ring.size, rptr_addr=gart.va_addr, wptr_addr=gart.va_addr+0x10, + eop_addr=eop_buffer.va_addr, eop_size=eop_buffer.size, doorbell=(doorbell_index:=am.AMDGPU_NAVI10_DOORBELL_MEC_RING0), pipe=0, queue=0) + self.usb._pci_cacheable += [(ring.cpu_view().addr, ring.size)] - def sleep(self, timeout): pass + return AMDQueueDesc(ring=ring.cpu_view().view(fmt='I'), doorbells=[self.dev_impl.doorbell64.view(doorbell_index * 8, 8, fmt='Q')], + read_ptrs=[gart.cpu_view().view(size=8, fmt='Q')], write_ptrs=[gart.cpu_view().view(offset=0x10, size=8, fmt='Q')]) class AMDDevice(HCQCompiled): + devices: ClassVar[list[HCQCompiled]] = [] + signal_pages: ClassVar[list[HCQBuffer]] = [] + signal_pool: ClassVar[list[HCQBuffer]] = [] + def is_am(self) -> bool: return isinstance(self.iface, (PCIIface, USBIface)) def is_usb(self) -> bool: return isinstance(self.iface, USBIface) + def _select_iface(self): + if len(nm:=getenv("AMD_IFACE", "")) > 0: return getattr(sys.modules[__name__], f"{nm.upper()}Iface")(self, self.device_id) + + errs:str = "" + for iface_t in (KFDIface, PCIIface, USBIface): + try: return iface_t(self, self.device_id) + except Exception: errs += f"\n{iface_t.__name__}: {traceback.format_exc()}" + raise RuntimeError(f"Cannot find a usable interface for AMD:{self.device_id}:\n{errs}") + def __init__(self, device:str=""): self.device_id = int(device.split(":")[1]) if ":" in device else 0 - self.iface = self._select_iface(KFDIface, PCIIface, USBIface) + self.iface = self._select_iface() self.target:tuple[int, ...] = ((trgt:=self.iface.props['gfx_target_version']) // 10000, (trgt // 100) % 100, trgt % 100) self.arch = "gfx%d%x%x" % self.target if self.target < (9,4,2) or self.target >= (13,0,0): raise RuntimeError(f"Unsupported arch: {self.arch}") @@ -750,51 +747,52 @@ class AMDDevice(HCQCompiled): self.max_wave_id = (self.iface.props['max_waves_per_simd'] * self.iface.props['simd_per_cu'] - 1) if self.target >= (10,1,0) else \ (min((self.max_cu_id+1)*40, self.iface.props['array_count'] // self.iface.props['simd_arrays_per_engine'] * 512) - 1) self.xccs = self.iface.props.get('num_xcc', 1) if getenv("XCCS", 1) else 1 - # this is what llvm refers to as "architected flat scratch" - self.has_scratch_base_registers = self.target >= (11,0,0) or self.target in {(9,4,2), (9,5,0)} + self.has_scratch_base_registers = self.target >= (11,0,0) or self.target == (9,4,2) # this is what llvm refers to as "architected flat scratch" # https://gitlab.freedesktop.org/agd5f/linux/-/blob/a1fc9f584c4aaf8bc1ebfa459fc57a3f26a290d8/drivers/gpu/drm/amd/amdkfd/kfd_queue.c#L391 sgrp_size_per_cu, lds_size_per_cu, hwreg_size_per_cu = 0x4000, 0x10000, 0x1000 - if self.target[:2] == (9,5): lds_size_per_cu = self.iface.props["lds_size_in_kb"] << 10 vgpr_size_per_cu = 0x60000 if self.target in {(11,0,0), (11,0,1), (12,0,0), (12,0,1)} else \ - 0x80000 if (self.target[:2]) in {(9,4), (9,5)} or self.target in {(9,0,8), (9,0,10)} else 0x40000 + 0x80000 if (self.target[:2]) == (9,4) or self.target in {(9,0,8), (9,0,10)} else 0x40000 wg_data_size = round_up((vgpr_size_per_cu + sgrp_size_per_cu + lds_size_per_cu + hwreg_size_per_cu) * (self.max_cu_id + 1), mmap.PAGESIZE) ctl_stack_size = round_up(12 * (self.max_cu_id + 1) * (self.max_wave_id + 1) + 8 + 40, mmap.PAGESIZE) if self.target >= (10,1,0) else \ round_up((self.max_wave_id + 1) * 8 + 8 + 40, mmap.PAGESIZE) debug_memory_size = round_up((self.max_cu_id + 1 if self.target >= (10,1,0) else 1) * (self.max_wave_id + 1) * 32, 64) if self.target[0] == 10: ctl_stack_size = min(ctl_stack_size, 0x7000) - self.soc = import_soc(self.target) + self.soc = importlib.import_module(f"tinygrad.runtime.autogen.am.{({9: 'vega10', 10: 'navi10', 11: 'soc21', 12: 'soc24'}[self.target[0]])}") self.pm4 = importlib.import_module(f"tinygrad.runtime.autogen.am.pm4_{'nv' if self.target[0] >= 10 else 'soc15'}") self.sdma = import_module('sdma', min(self.iface.ip_versions[am.SDMA0_HWIP], (6, 0, 0))) self.gc = AMDIP('gc', self.iface.ip_versions[am.GC_HWIP], self.iface.ip_offsets[am.GC_HWIP]) + # Define the regCOMPUTE_CURRENT_LOGIC_XCC_ID register, which is missing from the asic_regs files. + if self.target[:2] == (9,4): self.regCOMPUTE_CURRENT_LOGIC_XCC_ID = AMDReg("regCOMPUTE_CURRENT_LOGIC_XCC_ID", 0xe25, 0, {}, self.gc.bases) + nbio_name = 'nbio' if self.target[0] < 12 else 'nbif' nbio_pad = (0,) if self.target[0] == 9 else () - self.nbio = AMDIP(nbio_name, self.iface.ip_versions[am.NBIF_HWIP], {i:nbio_pad+x for i,x in self.iface.ip_offsets[am.NBIF_HWIP].items()}) + self.nbio = AMDIP(nbio_name, self.iface.ip_versions[am.NBIF_HWIP], nbio_pad+self.iface.ip_offsets[am.NBIF_HWIP]) - self.is_aql = getenv("AMD_AQL", int(self.xccs > 1)) - if self.is_aql: - self.pm4_ibs = self.iface.alloc(0x2000 if self.is_usb() else (16 << 20), uncached=True, cpu_access=True) - self.pm4_ib_alloc = BumpAllocator(self.pm4_ibs.size, wrap=True) - - self.compute_queue = self.create_queue(kfd.KFD_IOC_QUEUE_TYPE_COMPUTE_AQL if self.is_aql else kfd.KFD_IOC_QUEUE_TYPE_COMPUTE, - 0x2000 if self.is_usb() else (16 << 20), eop_buffer_size=0x1000, + self.compute_queue = self.create_queue(kfd.KFD_IOC_QUEUE_TYPE_COMPUTE, 0x2000 if self.is_usb() else 0x800000, eop_buffer_size=0x1000, ctx_save_restore_size=0 if self.is_am() else wg_data_size + ctl_stack_size, ctl_stack_size=ctl_stack_size, debug_memory_size=debug_memory_size) max_copy_size = 0x40000000 if self.iface.ip_versions[am.SDMA0_HWIP][0] >= 5 else 0x400000 - self.sdma_queue = self.create_queue(kfd.KFD_IOC_QUEUE_TYPE_SDMA, 0x200 if self.is_usb() else (16 << 20)) + self.sdma_queue = self.create_queue(kfd.KFD_IOC_QUEUE_TYPE_SDMA, 0x200 if self.is_usb() else 0x800000) - super().__init__(device, AMDAllocator(self), AMDLLVMRenderer(self.arch) if AMD_LLVM else AMDRenderer(self.arch), - AMDLLVMCompiler(self.arch) if AMD_LLVM else HIPCompiler(self.arch), functools.partial(AMDProgram, self), - AMDSignal, functools.partial(AMDComputeAQLQueue if self.is_aql else AMDComputeQueue, self), - functools.partial(AMDCopyQueue, self, max_copy_size=max_copy_size), + super().__init__(device, AMDAllocator(self), AMDLLVMRenderer(self.arch) if getenv("AMD_LLVM", 1) else AMDRenderer(self.arch), + AMDLLVMCompiler(self.arch) if getenv("AMD_LLVM", 1) else HIPCompiler(self.arch), functools.partial(AMDProgram, self), + AMDSignal, functools.partial(AMDComputeQueue, self), functools.partial(AMDCopyQueue, self, max_copy_size=max_copy_size), kernargs_size=(8 << 10) if self.is_usb() else (16 << 20), sigalloc_size=0x100 if self.is_usb() else 0x1000) # Scratch setup self.max_private_segment_size = 0 self._ensure_has_local_memory(128) # set default scratch size to 128 bytes per thread + # XCC setup + self.xcc_sync: tuple[AMDSignal, AMDSignal]|None = None + if self.xccs > 1: + self.xcc_sync_area = self.allocator.alloc(0x1000, BufferSpec(nolru=True, cpu_access=True)) + self.xcc_sync = (AMDSignal(base_buf=self.xcc_sync_area), AMDSignal(base_buf=self.xcc_sync_area.offset(256))) + AMDComputeQueue(self).xcc_config().submit(self) + # SQTT is disabled by default because of runtime overhead and big file sizes (~200mb to Tensor.full() two 4096x4096 tensors and matmul them) self.sqtt_enabled = PROFILE and bool(getenv("SQTT", 0)) if self.sqtt_enabled: @@ -808,26 +806,19 @@ class AMDDevice(HCQCompiled): self.sqtt_buffers = [self.allocator.alloc(SQTT_BUFFER_SIZE*1024*1024, BufferSpec(cpu_access=True, nolru=True)) for _ in range(SQTT_NUM)] self.sqtt_itrace_se_mask = getenv("SQTT_ITRACE_SE_MASK", 2) # -1 enable all, 0 disable all, >0 bitmask for where to enable instruction tracing self.cmd_id = 0 - cast(AMDComputeQueue, self.hw_compute_queue_t()).sqtt_start(self.sqtt_buffers, self.sqtt_itrace_se_mask).submit(self) + AMDComputeQueue(self).sqtt_start(self.sqtt_buffers, self.sqtt_itrace_se_mask).submit(self) def create_queue(self, queue_type, ring_size, ctx_save_restore_size=0, eop_buffer_size=0, ctl_stack_size=0, debug_memory_size=0): ring = self.iface.alloc(ring_size, uncached=True, cpu_access=True) gart = self.iface.alloc(0x100, uncached=True, cpu_access=True) - if queue_type == kfd.KFD_IOC_QUEUE_TYPE_COMPUTE_AQL: - aql_desc = hsa.amd_queue_t(queue_properties=hsa.AMD_QUEUE_PROPERTIES_IS_PTR64 | hsa.AMD_QUEUE_PROPERTIES_ENABLE_PROFILING, - read_dispatch_id_field_base_byte_offset=getattr(hsa.amd_queue_t, 'read_dispatch_id').offset, - max_cu_id=self.max_cu_id, max_wave_id=self.max_wave_id) - gart.cpu_view().view(fmt='B')[:ctypes.sizeof(aql_desc)] = bytes(aql_desc) - self.aql_desc = hsa.amd_queue_t.from_address(gart.va_addr) - cwsr_buffer_size = round_up((ctx_save_restore_size + debug_memory_size) * self.iface.props.get('num_xcc', 1), mmap.PAGESIZE) cwsr_buffer = self.iface.alloc(cwsr_buffer_size) if ctx_save_restore_size else None eop_buffer = self.iface.alloc(eop_buffer_size) if eop_buffer_size else None - return (self.iface.create_queue(queue_type, ring, gart, rptr=getattr(hsa.amd_queue_t, 'read_dispatch_id').offset, - wptr=getattr(hsa.amd_queue_t, 'write_dispatch_id').offset, eop_buffer=eop_buffer, cwsr_buffer=cwsr_buffer, - ctx_save_restore_size=ctx_save_restore_size, ctl_stack_size=ctl_stack_size)) + return AMDQueueDesc.multi(*(self.iface.create_queue(queue_type, ring, gart, eop_buffer=eop_buffer, cwsr_buffer=cwsr_buffer, xcc_id=xcc_id, + ctx_save_restore_size=ctx_save_restore_size, ctl_stack_size=ctl_stack_size) + for xcc_id in range(self.xccs if queue_type == kfd.KFD_IOC_QUEUE_TYPE_COMPUTE else 1))) def _ensure_has_local_memory(self, required): if self.max_private_segment_size >= required: return @@ -845,16 +836,8 @@ class AMDDevice(HCQCompiled): self.tmpring_size = waves << 12 | wavesize self.max_private_segment_size = required - if hasattr(self, 'aql_desc'): - self.aql_desc.scratch_backing_memory_location = self.scratch.va_addr - self.aql_desc.scratch_backing_memory_byte_size = self.scratch.size - self.aql_desc.scratch_wave64_lane_byte_size = self.max_private_segment_size * (self.aql_desc.max_wave_id + 1) // 64 - self.aql_desc.scratch_resource_descriptor[:] = [lo32(self.scratch.va_addr), hi32(self.scratch.va_addr) | (1 << 30), lo32(self.scratch.size), - 0x20814fac] # FORMAT=BUF_FORMAT_32_UINT,OOB_SELECT=2,ADD_TID_ENABLE=1,TYPE=SQ_RSRC_BUF,SQ_SELs - self.aql_desc.compute_tmpring_size = self.tmpring_size - def invalidate_caches(self): - self.hw_compute_queue_t().memory_barrier().signal(self.timeline_signal, self.next_timeline()).submit(self) + AMDComputeQueue(self).memory_barrier().signal(self.timeline_signal, self.next_timeline()).submit(self) self.synchronize() def on_device_hang(self): self.iface.on_device_hang() @@ -863,8 +846,7 @@ class AMDDevice(HCQCompiled): if self.sqtt_enabled: wptrs_buf = self.allocator.alloc(round_up(len(self.sqtt_buffers), 0x1000), BufferSpec(cpu_access=True, nolru=True)) wptrs = to_mv(wptrs_buf.va_addr, wptrs_buf.size) - cast(AMDComputeQueue, self.hw_compute_queue_t()).sqtt_stop(len(self.sqtt_buffers), wptrs_buf) \ - .signal(self.timeline_signal, self.next_timeline()).submit(self) + AMDComputeQueue(self).sqtt_stop(len(self.sqtt_buffers), wptrs_buf).signal(self.timeline_signal, self.next_timeline()).submit(self) self.synchronize() if DEBUG>=2: print('Saving SQTT in profile...') for i,buf0 in enumerate(self.sqtt_buffers): @@ -876,3 +858,8 @@ class AMDDevice(HCQCompiled): self.allocator._copyout(sqtt_buf:=memoryview(bytearray(wptr)), buf0) Compiled.profile_events += [ProfileSQTTEvent(self.device, i, bytes(sqtt_buf), bool((self.sqtt_itrace_se_mask >> i) & 0b1))] super()._at_profile_finalize() + + def finalize(self): + try: self.synchronize() # Try to finalize device in any case. + except RuntimeError as e: print(f"{self.device} synchronization failed before finalizing: {e}") + if hasattr(self.iface, 'device_fini'): self.iface.device_fini() diff --git a/tinygrad_repo/tinygrad/runtime/ops_cpu.py b/tinygrad_repo/tinygrad/runtime/ops_cpu.py index 5ebf1f8c3..c5a15afb5 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_cpu.py +++ b/tinygrad_repo/tinygrad/runtime/ops_cpu.py @@ -1,15 +1,8 @@ -from __future__ import annotations -import platform, subprocess, sys, ctypes, functools, time, mmap, threading, queue -from tinygrad.helpers import capstone_flatdump, getenv, from_mv, to_mv, OSX, mv_address, wait_cond, cpu_profile -from tinygrad.device import Compiler, BufferSpec, DMACPURef -from tinygrad.runtime.support.hcq import HCQCompiled, HCQAllocatorBase, HCQBuffer, HWQueue, HCQArgsState, HCQSignal, HCQProgram, MMIOInterface +import platform, subprocess, sys +from tinygrad.helpers import capstone_flatdump, getenv +from tinygrad.device import Compiled, Compiler, MallocAllocator, CPUProgram from tinygrad.runtime.support.elf import jit_loader from tinygrad.renderer.cstyle import ClangRenderer -from tinygrad.uop.ops import sint - -class CPUSignal(HCQSignal): - def _sleep(self, time_spent_waiting_ms:int): - if self.is_timeline and self.owner is not None: self.owner.tasks.join() class ClangJITCompiler(Compiler): def __init__(self, cachekey="compile_clang_jit"): super().__init__(cachekey) @@ -18,108 +11,12 @@ class ClangJITCompiler(Compiler): # -fno-math-errno is required for __builtin_sqrt to become an instruction instead of a function call # x18 is a reserved platform register. It is clobbered on context switch in macos and is used to store TEB pointer in windows on arm, don't use it target = 'x86_64' if sys.platform == 'win32' else platform.machine() - # on arm march means "runs on this arch and superset" instead of "optimize for this arch". x86 march == arm mcpu - arch = '-march=native' if platform.machine() in ('x86_64', 'AMD64') else '-mcpu=native' - args = [arch, f'--target={target}-none-unknown-elf', '-O2', '-fPIC', '-ffreestanding', '-fno-math-errno', '-nostdlib', '-fno-ident'] + args = ['-march=native', f'--target={target}-none-unknown-elf', '-O2', '-fPIC', '-ffreestanding', '-fno-math-errno', '-nostdlib', '-fno-ident'] arch_args = ['-ffixed-x18'] if target == 'arm64' else [] obj = subprocess.check_output([getenv("CC", 'clang'), '-c', '-x', 'c', *args, *arch_args, '-', '-o', '-'], input=src.encode('utf-8')) return jit_loader(obj) def disassemble(self, lib:bytes): return capstone_flatdump(lib) -class CPUWorker(threading.Thread): - def __init__(self, dev): - super().__init__() - self.dev, self.tasks, self.daemon = dev, dev.tasks, True - - def run(self): - while True: - cmd_iter = iter(self.tasks.get()) - for cmd in cmd_iter: - args_cnt = next(cmd_iter) - cmd(*[next(cmd_iter) for _ in range(args_cnt)]) - self.tasks.task_done() - -class CPUComputeQueue(HWQueue): - def _exec(self, prg, bufs, *args): - prg.fxn(*map(ctypes.c_uint64, args[:bufs]), *map(ctypes.c_int64 if platform.machine() == "arm64" else ctypes.c_int32, args[bufs:])) - def _signal(self, signal_addr, value): to_mv(signal_addr, 4).cast('I')[0] = value - def _wait(self, signal_addr, value): wait_cond(lambda: to_mv(signal_addr, 4).cast('I')[0] >= value, timeout_ms=60000) - def _timestamp(self, timestamp_addr): to_mv(timestamp_addr, 8).cast('Q')[0] = time.perf_counter_ns() - def cmd(self, cmd, *args): - self.q(cmd, len(args), *args) - return self - - def memory_barrier(self): return self - def exec(self, prg:CPUProgram, args_state:HCQArgsState, global_size, local_size): - return self.cmd(self._exec, prg, len(args_state.bufs), *[x.va_addr for x in args_state.bufs], *args_state.vals) - def wait(self, signal, value=0): return self.cmd(self._wait, signal.value_addr, value) - def timestamp(self, signal): return self.cmd(self._timestamp, signal.timestamp_addr) - def signal(self, signal, value:sint=0): return self.cmd(self._signal, signal.value_addr, value) - def _submit(self, dev): dev.tasks.put(self._q[:]) - -# NOTE: MAP_JIT is added to mmap module in python 3.13 -MAP_JIT = 0x0800 - -class CPUProgram(HCQProgram): - rt_lib = ctypes.CDLL(ctypes.util.find_library('System' if OSX else 'kernel32') if OSX or sys.platform == "win32" else 'libgcc_s.so.1') - - def __init__(self, dev, name:str, lib:bytes): - if sys.platform == "win32": - PAGE_EXECUTE_READWRITE, MEM_COMMIT, MEM_RESERVE = 0x40, 0x1000, 0x2000 - ctypes.windll.kernel32.VirtualAlloc.restype = ctypes.c_void_p - self.mem = ctypes.windll.kernel32.VirtualAlloc(ctypes.c_void_p(0), ctypes.c_size_t(len(lib)), MEM_COMMIT | MEM_RESERVE, PAGE_EXECUTE_READWRITE) - ctypes.memmove(self.mem, lib, len(lib)) - ctypes.windll.kernel32.GetCurrentProcess.restype = ctypes.c_void_p - proc = ctypes.windll.kernel32.GetCurrentProcess() - ctypes.windll.kernel32.FlushInstructionCache(ctypes.c_void_p(proc), ctypes.c_void_p(self.mem), ctypes.c_size_t(len(lib))) - self.fxn = ctypes.CFUNCTYPE(None)(self.mem) - else: - # On apple silicon with SPRR enabled (it always is in macos) RWX pages are unrepresentable: https://blog.svenpeter.dev/posts/m1_sprr_gxf/ - # MAP_JIT allows us to easily flip pages from RW- to R-X and vice versa. It is a noop on intel cpus. (man pthread_jit_write_protect_np) - self.mem = mmap.mmap(-1, len(lib), mmap.MAP_ANON|mmap.MAP_PRIVATE|(MAP_JIT if OSX else 0), mmap.PROT_READ|mmap.PROT_WRITE|mmap.PROT_EXEC) - - if OSX: CPUProgram.rt_lib.pthread_jit_write_protect_np(False) - self.mem.write(lib) - if OSX: CPUProgram.rt_lib.pthread_jit_write_protect_np(True) - - # __clear_cache isn't a normal libc function, but a compiler support routine found in libgcc_s for gcc and compiler-rt for clang. - # libgcc_s comes as shared library but compiler-rt is only a bunch of static library archives which we can't directly load, but fortunately - # it somehow found its way into libSystem on macos (likely because it used __builtin_clear_cache) and libgcc_s is ~always present on linux - # Using ["name"] instead of .name because otherwise name is getting mangled: https://docs.python.org/3.12/reference/expressions.html#index-5 - CPUProgram.rt_lib["__clear_cache"](ctypes.c_void_p(mv_address(self.mem)), ctypes.c_void_p(mv_address(self.mem) + len(lib))) - - self.fxn = ctypes.CFUNCTYPE(None)(mv_address(self.mem)) - - super().__init__(HCQArgsState, dev, name, kernargs_alloc_size=0) - - def __del__(self): - if getattr(sys, 'is_finalizing', lambda: True)(): return - if sys.platform == 'win32': ctypes.windll.kernel32.VirtualFree(ctypes.c_void_p(self.mem), ctypes.c_size_t(0), 0x8000) #0x8000 - MEM_RELEASE - -class CPUAllocator(HCQAllocatorBase): - def _alloc(self, size:int, options:BufferSpec) -> HCQBuffer: - if options.external_ptr: addr, buf = options.external_ptr, None - elif sys.platform == "win32": addr = mv_address(buf:=mmap.mmap(-1, size, access=mmap.ACCESS_WRITE)) - else: addr = mv_address(buf:=mmap.mmap(-1, size, mmap.MAP_ANON | mmap.MAP_PRIVATE, mmap.PROT_READ | mmap.PROT_WRITE)) - return HCQBuffer(va:=addr, sz:=size, meta=buf, view=MMIOInterface(va, sz, fmt='B'), owner=self.dev) - def _as_buffer(self, src) -> memoryview: - self.dev.synchronize() - return to_mv(src.va_addr, src.size) - def _as_dmaref(self, buf): - self.dev.synchronize() - return DMACPURef(buf.va_addr, buf.size) - def _copyin(self, dest, src:memoryview): - self.dev.synchronize() - with cpu_profile('TINY -> CPU', self.dev.device, is_copy=True): ctypes.memmove(dest.va_addr, from_mv(src), len(src)) - def _copyout(self, dest:memoryview, src): - self.dev.synchronize() - with cpu_profile('CPU -> TINY', self.dev.device, is_copy=True): ctypes.memmove(from_mv(dest), src.va_addr, len(dest)) - def _map(self, buf:HCQBuffer): - if buf.view is None or not isinstance(buf.view, MMIOInterface): raise RuntimeError("Cannot map buffer without view to cpu") - -class CPUDevice(HCQCompiled): - def __init__(self, device:str=""): - self.tasks:queue.Queue = queue.Queue() - CPUWorker(self).start() - super().__init__(device, CPUAllocator(self), ClangRenderer(), ClangJITCompiler(), functools.partial(CPUProgram, self), CPUSignal, CPUComputeQueue) +class CPUDevice(Compiled): + def __init__(self, device:str): super().__init__(device, MallocAllocator, ClangRenderer(), ClangJITCompiler(), CPUProgram) diff --git a/tinygrad_repo/tinygrad/runtime/ops_cuda.py b/tinygrad_repo/tinygrad/runtime/ops_cuda.py index 326ae84f0..f62577b24 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_cuda.py +++ b/tinygrad_repo/tinygrad/runtime/ops_cuda.py @@ -1,6 +1,6 @@ from __future__ import annotations import ctypes, ctypes.util, functools -from tinygrad.helpers import DEBUG, getenv, mv_address, init_c_var, init_c_struct_t, suppress_finalizing +from tinygrad.helpers import DEBUG, getenv, from_mv, init_c_var, init_c_struct_t from tinygrad.device import Compiled, BufferSpec, LRUAllocator from tinygrad.renderer.cstyle import CUDARenderer from tinygrad.renderer.ptx import PTXRenderer @@ -45,8 +45,9 @@ class CUDAProgram: self.prg = prg if self.smem > 0: check(cuda.cuFuncSetAttribute(self.prg, cuda.CU_FUNC_ATTRIBUTE_MAX_DYNAMIC_SHARED_SIZE_BYTES, self.smem)) - @suppress_finalizing - def __del__(self): check(cuda.cuModuleUnload(self.module)) + def __del__(self): + try: check(cuda.cuModuleUnload(self.module)) + except AttributeError: pass def __call__(self, *args, global_size:tuple[int,int,int]=(1,1,1), local_size:tuple[int,int,int]=(1,1,1), vals:tuple[int, ...]=(), wait=False): check(cuda.cuCtxSetCurrent(self.dev.context)) @@ -75,12 +76,12 @@ class CUDAAllocator(LRUAllocator['CUDADevice']): check(cuda.cuCtxSetCurrent(self.dev.context)) host_mem = self.alloc(len(src), BufferSpec(host=True)) self.dev.pending_copyin.append((host_mem, len(src), BufferSpec(host=True))) - ctypes.memmove(host_mem, mv_address(src), len(src)) + ctypes.memmove(host_mem, from_mv(src), len(src)) check(cuda.cuMemcpyHtoDAsync_v2(dest, host_mem, len(src), None)) def _copyout(self, dest:memoryview, src): CUDADevice.synchronize_system() check(cuda.cuCtxSetCurrent(self.dev.context)) - check(cuda.cuMemcpyDtoH_v2(mv_address(dest), src, len(dest))) + check(cuda.cuMemcpyDtoH_v2(from_mv(dest), src, len(dest))) def _transfer(self, dest, src, sz:int, src_dev, dest_dev): check(cuda.cuCtxSetCurrent(src_dev.context)) check(cuda.cuEventCreate(ctypes.byref(sync_event := cuda.CUevent()), 0)) diff --git a/tinygrad_repo/tinygrad/runtime/ops_disk.py b/tinygrad_repo/tinygrad/runtime/ops_disk.py index 1f810ec98..34d499966 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_disk.py +++ b/tinygrad_repo/tinygrad/runtime/ops_disk.py @@ -1,5 +1,5 @@ -import os, sys, mmap, io, ctypes, contextlib, pathlib -from typing import Generator, Callable +import os, sys, mmap, io, ctypes, ctypes.util, contextlib +from typing import Optional, Generator, Callable from tinygrad.helpers import OSX, round_up from tinygrad.device import Compiled, Allocator with contextlib.suppress(ImportError): @@ -12,15 +12,14 @@ class DiskDevice(Compiled): def __init__(self, device:str): if not DiskDevice._tried_io_uring_init: self._iouring_setup() - self.size: int|None = None - self.fd: int|None = None + self.size: Optional[int] = None + self.fd: Optional[int] = None self.count = 0 super().__init__(device, DiskAllocator(self), None, None, None) - def _might_open(self, size:int): + def _might_open(self, size): + self.count += 1 assert self.size is None or size <= self.size, f"can't reopen Disk tensor with larger size, opened with {self.size}, tried to open with {size}" - if self.size is not None and hasattr(self.device, "mem"): - self.count += 1 - return + if self.size is not None: return filename = self.device[len("disk:"):] self.size = size @@ -31,11 +30,10 @@ class DiskDevice(Compiled): else: try: self.fd = os.open(filename, os.O_RDWR|os.O_CREAT|getattr(os, "O_DIRECT", 0)) except OSError: self.fd = os.open(filename, os.O_RDWR|os.O_CREAT) - if not pathlib.Path(filename).is_block_device() and os.fstat(self.fd).st_size < self.size: os.ftruncate(self.fd, self.size) + if os.fstat(self.fd).st_size < self.size: os.ftruncate(self.fd, self.size) self.mem = mmap.mmap(self.fd, self.size) if hasattr(self.mem, 'madvise') and (hp := getattr(mmap, "MADV_HUGEPAGE", None)) is not None: with contextlib.suppress(OSError): self.mem.madvise(hp) # some systems have transparent_hugepage disabled - self.count += 1 def _might_close(self): self.count -= 1 if self.count == 0: diff --git a/tinygrad_repo/tinygrad/runtime/ops_dsp.py b/tinygrad_repo/tinygrad/runtime/ops_dsp.py index 640d992ec..c62fba07b 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_dsp.py +++ b/tinygrad_repo/tinygrad/runtime/ops_dsp.py @@ -1,11 +1,10 @@ from __future__ import annotations import ctypes, os, mmap, tempfile, pathlib, array, functools, threading, contextlib, sys, subprocess, struct assert sys.platform != 'win32' -from tinygrad.device import BufferSpec, Compiled, Allocator, Compiler -from tinygrad.runtime.ops_cpu import CPUAllocator +from tinygrad.device import BufferSpec, Compiled, Allocator, Compiler, MallocAllocator from tinygrad.dtype import dtypes, DType, PtrDType from tinygrad.uop.ops import Ops, UOp -from tinygrad.helpers import getenv, round_up, mv_address, to_mv, cpu_objdump, DEBUG +from tinygrad.helpers import from_mv, getenv, round_up, mv_address, to_mv, cpu_objdump, DEBUG from tinygrad.renderer.cstyle import ClangRenderer from tinygrad.runtime.autogen import libc, qcom_dsp if getenv("IOCTL"): import extra.dsp.run # noqa: F401 # pylint: disable=unused-import @@ -24,7 +23,7 @@ dsp_pm_late = PatternMatcher([ (UPat.var("x")+UPat(Ops.VECTORIZE,src=UPat.var("y")), lambda x,y: x+UOp(Ops.CUSTOMI,x.dtype,(y,),arg="{0}") if x.op is not Ops.CUSTOMI else None), (UPat.var("x")*UPat(Ops.VECTORIZE,src=UPat.var("y")), lambda x,y: x*UOp(Ops.CUSTOMI,x.dtype,(y,),arg="{0}") if x.op is not Ops.CUSTOMI else None), (UPat.var("x")//UPat(Ops.VECTORIZE,src=UPat.var("y")), lambda x,y: x//UOp(Ops.CUSTOMI,x.dtype,(y,),arg="{0}") if x.op is not Ops.CUSTOMI else None), - (UPat(Ops.DEFINE_REG, src=(UPat(Ops.VECTORIZE, src=UPat(Ops.CONST, arg=0)),), dtype=dtypes.uchar.vec(128), name="d", allow_any_len=True), + (UPat(Ops.DEFINE_ACC, src=(UPat(Ops.VECTORIZE, src=UPat(Ops.CONST, arg=0)),), dtype=dtypes.uchar.vec(128), name="d", allow_any_len=True), lambda d: d.replace(src=(UOp(Ops.CUSTOMI, d.dtype, arg="__builtin_HEXAGON_V6_vd0_128B()"),)+d.src[1:])), ]) @@ -109,8 +108,8 @@ class DSPAllocator(Allocator['DSPDevice']): qcom_dsp.ION_IOC_FREE(self.dev.ion_fd, handle=opaque.share_info.handle) def _as_buffer(self, src:DSPBuffer) -> memoryview: return to_mv(src.va_addr, src.size) - def _copyin(self, dest:DSPBuffer, src:memoryview): ctypes.memmove(dest.va_addr, mv_address(src), src.nbytes) - def _copyout(self, dest:memoryview, src:DSPBuffer): ctypes.memmove(mv_address(dest), src.va_addr, dest.nbytes) + def _copyin(self, dest:DSPBuffer, src:memoryview): ctypes.memmove(dest.va_addr, from_mv(src), src.nbytes) + def _copyout(self, dest:memoryview, src:DSPBuffer): ctypes.memmove(from_mv(dest), src.va_addr, dest.nbytes) def _offset(self, buf, size:int, offset:int): return DSPBuffer(buf.va_addr+offset, size, buf.share_info, buf.offset+offset) class ClangCompiler(Compiler): @@ -132,8 +131,7 @@ class DSPDevice(Compiled): def __init__(self, device:str=""): compiler_args = ["--target=hexagon", "-mcpu=hexagonv65", "-fuse-ld=lld", "-nostdlib", "-mhvx=v65", "-mhvx-length=128b"] if getenv("MOCKDSP"): - super().__init__(device, CPUAllocator(self), MockDSPRenderer(), - ClangCompiler(None, ["-static"] + compiler_args, 'llvm-objdump'), MockDSPProgram) + super().__init__(device, MallocAllocator, MockDSPRenderer(), ClangCompiler(None, ["-static"] + compiler_args, 'llvm-objdump'), MockDSPProgram) else: self.ion_fd = os.open('/dev/ion', os.O_RDONLY) # Generate link script to pass into clang. Aligning all used sections to 4k fixes invoke problem. @@ -295,11 +293,11 @@ class MockDSPProgram: os.chmod(dsp_lib.name, 0o0777) # NOTE: this timing includes a docker launch proc = subprocess.run(["docker", "run", "--rm", "-i", "-v", f"{os.path.abspath(os.path.dirname(dsp_lib.name))}:/work", "-w", "/work", - "qemu-hexagon", "-c", f"qemu-hexagon {'-strace' if DEBUG >= 5 else ''} /work/"+os.path.basename(dsp_lib.name)], - input=b''.join([bytes(to_mv(x.va_addr, x.size)) for x in bufs] + [struct.pack("I", x) for x in vals]), stdout=subprocess.PIPE, check=True) + "qemu-hexagon", "-c", f"qemu-hexagon {'-strace' if DEBUG >= 5 else ''} /work/"+os.path.basename(dsp_lib.name)], + input=b''.join([bytes(x) for x in bufs] + [struct.pack("I", x) for x in vals]), stdout=subprocess.PIPE, check=True) offset = 4 for x in bufs: - x.cpu_view()[:] = proc.stdout[offset:offset+x.size] - offset += x.size + x[:] = proc.stdout[offset:offset+len(x)] + offset += len(x) assert offset == len(proc.stdout) return struct.unpack("I", proc.stdout[0:4])[0] / 1e9 # pretend it's 1 Ghz, but this is an inscount, not a time diff --git a/tinygrad_repo/tinygrad/runtime/ops_gpu.py b/tinygrad_repo/tinygrad/runtime/ops_gpu.py index c9ebb338c..0a8304d89 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_gpu.py +++ b/tinygrad_repo/tinygrad/runtime/ops_gpu.py @@ -1,8 +1,8 @@ from __future__ import annotations -from typing import cast +from typing import Optional, cast import ctypes, functools, hashlib from tinygrad.runtime.autogen import opencl as cl -from tinygrad.helpers import init_c_var, to_char_p_p, from_mv, OSX, DEBUG, getenv, mv_address, suppress_finalizing +from tinygrad.helpers import init_c_var, to_char_p_p, from_mv, OSX, DEBUG, getenv, mv_address from tinygrad.renderer.cstyle import OpenCLRenderer, IntelRenderer from tinygrad.device import BufferSpec, LRUAllocator, Compiled, Compiler, CompileError @@ -46,14 +46,12 @@ class CLProgram: try: check(cl.clReleaseProgram(self.program)) except (TypeError, AttributeError): pass - def __call__(self, *bufs:tuple[ctypes._CData, BufferSpec], global_size:tuple[int,int,int]=(1,1,1), local_size:tuple[int,int,int]|None=None, - vals:tuple[int, ...]=(), wait=False) -> float|None: + def __call__(self, *bufs:tuple[ctypes._CData, BufferSpec], global_size:tuple[int,int,int]=(1,1,1), local_size:Optional[tuple[int,int,int]]=None, vals:tuple[int, ...]=(), wait=False) -> Optional[float]: # noqa: E501 for i,(b,_) in enumerate(bufs): cl.clSetKernelArg(self.kernel, i, ctypes.sizeof(b), ctypes.byref(b)) for i,v in enumerate(vals,start=len(bufs)): cl.clSetKernelArg(self.kernel, i, 4, ctypes.byref(ctypes.c_int32(v))) if local_size is not None: global_size = cast(tuple[int,int,int], tuple(int(g*l) for g,l in zip(global_size, local_size))) event = cl.cl_event() if wait else None - check(cl.clEnqueueNDRangeKernel(self.dev.queue, self.kernel, len(global_size), None, (ctypes.c_size_t * len(global_size))(*global_size), - (ctypes.c_size_t * len(local_size))(*local_size) if local_size else None, 0, None, event)) + check(cl.clEnqueueNDRangeKernel(self.dev.queue, self.kernel, len(global_size), None, (ctypes.c_size_t * len(global_size))(*global_size), (ctypes.c_size_t * len(local_size))(*local_size) if local_size else None, 0, None, event)) # noqa: E501 if wait: assert event is not None check(cl.clWaitForEvents(1, event)) @@ -69,8 +67,9 @@ class CLAllocator(LRUAllocator['CLDevice']): cl.cl_image_format(cl.CL_RGBA, {2: cl.CL_HALF_FLOAT, 4: cl.CL_FLOAT}[options.image.itemsize]), options.image.shape[1], options.image.shape[0], 0, None, status := ctypes.c_int32()), status), options) return (checked(cl.clCreateBuffer(self.dev.context, cl.CL_MEM_READ_WRITE, size, None, status := ctypes.c_int32()), status), options) - @suppress_finalizing - def _free(self, opaque:tuple[ctypes._CData, BufferSpec], options:BufferSpec): check(cl.clReleaseMemObject(opaque[0])) + def _free(self, opaque:tuple[ctypes._CData, BufferSpec], options:BufferSpec): + try: check(cl.clReleaseMemObject(opaque[0])) + except AttributeError: pass def _copyin(self, dest:tuple[ctypes._CData, BufferSpec], src:memoryview): if dest[1].image is not None: check(cl.clEnqueueWriteImage(self.dev.queue, dest[0], False, (ctypes.c_size_t * 3)(0,0,0), diff --git a/tinygrad_repo/tinygrad/runtime/ops_hip.py b/tinygrad_repo/tinygrad/runtime/ops_hip.py index a15e36685..d26a91d20 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_hip.py +++ b/tinygrad_repo/tinygrad/runtime/ops_hip.py @@ -1,5 +1,5 @@ import ctypes, functools -from tinygrad.helpers import init_c_var, mv_address, init_c_struct_t, getenv +from tinygrad.helpers import init_c_var, from_mv, init_c_struct_t, getenv from tinygrad.device import Compiled, LRUAllocator, BufferSpec from tinygrad.runtime.autogen import hip from tinygrad.runtime.support.compiler_amd import HIPCompiler @@ -57,7 +57,7 @@ class HIPAllocator(LRUAllocator[HIPDevice]): def _free(self, opaque, options:BufferSpec): check(hip.hipFree(opaque)) def _copyin(self, dest, src: memoryview): check(hip.hipSetDevice(self.dev.device_id)) - check(hip.hipMemcpy(dest, mv_address(src), len(src), hip.hipMemcpyHostToDevice)) + check(hip.hipMemcpy(dest, from_mv(src), len(src), hip.hipMemcpyHostToDevice)) def _copyout(self, dest:memoryview, src): self.dev.synchronize() - check(hip.hipMemcpy(mv_address(dest), src, len(dest), hip.hipMemcpyDeviceToHost)) + check(hip.hipMemcpy(from_mv(dest), src, len(dest), hip.hipMemcpyDeviceToHost)) diff --git a/tinygrad_repo/tinygrad/runtime/ops_llvm.py b/tinygrad_repo/tinygrad/runtime/ops_llvm.py index e5fabb84f..c628ad138 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_llvm.py +++ b/tinygrad_repo/tinygrad/runtime/ops_llvm.py @@ -1,7 +1,5 @@ -import ctypes, platform, functools, queue -from tinygrad.device import Compiler -from tinygrad.runtime.support.hcq import HCQCompiled, HCQSignal -from tinygrad.runtime.ops_cpu import CPUAllocator, CPUProgram, CPUComputeQueue, CPUWorker +import ctypes, platform +from tinygrad.device import Compiled, Compiler, MallocAllocator, CPUProgram from tinygrad.helpers import OSX, getenv, capstone_flatdump, DEBUG from tinygrad.renderer.llvmir import LLVMRenderer import tinygrad.runtime.autogen.llvm as llvm @@ -71,8 +69,5 @@ class HostLLVMCompiler(LLVMCompiler): cpu, feats = ctypes.string_at(llvm.LLVMGetHostCPUName()), (b'+reserve-x18,' if OSX else b'') + ctypes.string_at(llvm.LLVMGetHostCPUFeatures()) super().__init__(cpu.decode(), feats.decode()) -class LLVMDevice(HCQCompiled): - def __init__(self, device:str=""): - self.tasks:queue.Queue = queue.Queue() - CPUWorker(self).start() - super().__init__(device, CPUAllocator(self), LLVMRenderer(), HostLLVMCompiler(), functools.partial(CPUProgram, self), HCQSignal, CPUComputeQueue) +class LLVMDevice(Compiled): + def __init__(self, device:str): super().__init__(device, MallocAllocator, LLVMRenderer(), HostLLVMCompiler(), CPUProgram) diff --git a/tinygrad_repo/tinygrad/runtime/ops_metal.py b/tinygrad_repo/tinygrad/runtime/ops_metal.py index 9e453eb72..2dd030ae4 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_metal.py +++ b/tinygrad_repo/tinygrad/runtime/ops_metal.py @@ -1,7 +1,7 @@ -import subprocess, pathlib, struct, ctypes, tempfile, functools, contextlib, decimal, platform -from typing import Any, cast -from tinygrad.helpers import prod, to_mv, getenv, round_up, cache_dir, T, init_c_struct_t, PROFILE, ProfileRangeEvent, cpu_profile, unwrap -from tinygrad.device import Compiled, Compiler, CompileError, LRUAllocator, ProfileDeviceEvent +import os, pathlib, struct, ctypes, tempfile, functools, contextlib, decimal, platform +from typing import Any, Union, cast +from tinygrad.helpers import prod, to_mv, getenv, round_up, cache_dir, T, init_c_struct_t, PROFILE +from tinygrad.device import Compiled, Compiler, CompileError, LRUAllocator, cpu_profile, ProfileDeviceEvent, ProfileRangeEvent from tinygrad.renderer.cstyle import MetalRenderer class objc_id(ctypes.c_void_p): # This prevents ctypes from converting response to plain int, and dict.fromkeys() can use it to dedup @@ -83,8 +83,7 @@ class MetalDevice(Compiled): for cbuf in self.mtl_buffers_in_flight: wait_check(cbuf) st, en = decimal.Decimal(cmdbuf_st_time(cbuf)) * 1000000, decimal.Decimal(cmdbuf_en_time(cbuf)) * 1000000 - # NOTE: command buffers from MetalGraph are not profiled here - if PROFILE and (lb:=cmdbuf_label(cbuf)) is not None and not lb.startswith("batched"): + if PROFILE and (lb:=cmdbuf_label(cbuf)) is not None: Compiled.profile_events += [ProfileRangeEvent(self.device, lb, st, en, is_copy=lb.startswith("COPY"))] self.mtl_buffers_in_flight.clear() @@ -111,7 +110,7 @@ class MetalCompiler(Compiler): super().__init__("compile_metal_direct") def __reduce__(self): return (MetalCompiler,()) # force pickle to create new instance for each multiprocessing fork def compile(self, src:str) -> bytes: - ret: Exception|bytes = CompileError("MTLCodeGenServiceBuildRequest returned without calling the callback") + ret: Union[Exception, bytes] = CompileError("MTLCodeGenServiceBuildRequest returned without calling the callback") @ctypes.CFUNCTYPE(None, ctypes.c_void_p, ctypes.c_int32, ctypes.c_void_p, ctypes.c_size_t, ctypes.c_char_p) def callback(blockptr, error, dataPtr, dataLen, errorMessage): nonlocal ret @@ -144,10 +143,7 @@ class MetalCompiler(Compiler): with tempfile.NamedTemporaryFile(delete=True) as shader: shader.write(lib) shader.flush() - proc = subprocess.Popen(f"cd {pathlib.Path(__file__).parents[2]}/extra/disassemblers/applegpu && python3 compiler_explorer.py {shader.name}", - stdout=subprocess.PIPE, shell=True, text=True, bufsize=1) - for line in unwrap(proc.stdout): print(line, end="") - ret = proc.wait() + ret = os.system(f"cd {pathlib.Path(__file__).parents[2]}/extra/disassemblers/applegpu && python3 compiler_explorer.py {shader.name}") if ret: print("Disassembler Error: Make sure you have https://github.com/dougallj/applegpu cloned to tinygrad/extra/disassemblers/applegpu") class MetalProgram: @@ -202,8 +198,7 @@ class MetalAllocator(LRUAllocator[MetalDevice]): ret = msg("newBufferWithLength:options:", objc_id)(self.dev.sysdevice, ctypes.c_ulong(size), MTLResourceOptions.MTLResourceStorageModeShared) if ret.value is None: raise MemoryError(f"Metal OOM while allocating {size=}") return MetalBuffer(ret, size) - def _free(self, opaque:MetalBuffer, options): - if msg is not None and libobjc is not None: msg("release")(opaque.buf) + def _free(self, opaque:MetalBuffer, options): msg("release")(opaque.buf) def _transfer(self, dest:MetalBuffer, src:MetalBuffer, sz:int, src_dev:MetalDevice, dest_dev:MetalDevice): dest_dev.synchronize() src_command_buffer = msg("commandBuffer", objc_instance)(src_dev.mtl_queue) @@ -221,14 +216,11 @@ class MetalAllocator(LRUAllocator[MetalDevice]): msg("setLabel:")(src_command_buffer, to_ns_str(f"COPY {src_dev.device} -> {dest_dev.device}")) msg("commit")(src_command_buffer) src_dev.mtl_buffers_in_flight.append(src_command_buffer) - # Transfers currently synchronize the completion. Otherwise, copies can sometimes lead to incorrect values. - # There is no real metal multidevice support for now, so transfer is used only for tests. - src_dev.synchronize() def _cp_mv(self, dst, src, prof_desc): with cpu_profile(prof_desc, self.dev.device, is_copy=True): dst[:] = src def _as_buffer(self, src:MetalBuffer) -> memoryview: self.dev.synchronize() return to_mv(cast(int, msg("contents", objc_id)(src.buf).value), src.size + src.offset)[src.offset:] - def _copyin(self, dest:MetalBuffer, src:memoryview): self._cp_mv(self._as_buffer(dest), src, "TINY -> METAL") - def _copyout(self, dest:memoryview, src:MetalBuffer): self._cp_mv(dest, self._as_buffer(src), "METAL -> TINY") + def _copyin(self, dest:MetalBuffer, src:memoryview): self._cp_mv(self._as_buffer(dest), src, "CPU -> METAL") + def _copyout(self, dest:memoryview, src:MetalBuffer): self._cp_mv(dest, self._as_buffer(src), "METAL -> CPU") def _offset(self, buf:MetalBuffer, size:int, offset:int): return MetalBuffer(buf.buf, size, offset) diff --git a/tinygrad_repo/tinygrad/runtime/ops_null.py b/tinygrad_repo/tinygrad/runtime/ops_null.py index cd293f998..569888d8c 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_null.py +++ b/tinygrad_repo/tinygrad/runtime/ops_null.py @@ -1,33 +1,26 @@ -import functools -from tinygrad.device import Compiled, Compiler, Allocator -from tinygrad.engine.jit import MultiGraphRunner -from tinygrad.renderer.cstyle import CStyleLanguage +from tinygrad.device import Compiled, Compiler, Renderer, Allocator from tinygrad.uop.ops import Ops -from tinygrad.helpers import cpu_profile +from tinygrad.engine.jit import MultiGraphRunner -class NullRenderer(CStyleLanguage): +class NullRenderer(Renderer): device = "NULL" + code_for_op = {k:lambda:None for k in [Ops.EXP2, Ops.LOG2, Ops.SIN, Ops.SQRT]} has_local = False - float4 = "float4" - barrier = "// BARRIER" - code_for_op = {**CStyleLanguage.code_for_op, Ops.THREEFRY: lambda a,b,dtype: f"threefry({a},{b})", Ops.MAX: lambda a,b,dtype: f"max({a},{b})"} + def render(self, uops:list) -> str: return "" class NullProgram: - def __init__(self, device:str, name:str, lib:bytes): self.device, self.name = device, name + def __init__(self, name:str, lib:bytes): pass def __call__(self, *bufs, global_size:tuple[int,int,int]=(1,1,1), local_size:tuple[int,int,int]=(1,1,1), vals:tuple[int, ...]=(), wait=False): - with cpu_profile(self.name, self.device): return 1e-4 + return 1e-4 class NullAllocator(Allocator['NullDevice']): def _alloc(self, size, options): pass def _copyin(self, dest, src:memoryview): pass def _copyout(self, dest:memoryview, src): pass - def _transfer(self, dest, src, sz:int, src_dev, dest_dev): - with cpu_profile(f"{src_dev.device} -> {dest_dev.device}", self.dev.device): pass - def _offset(self, buf, offset:int, size:int): pass + def _transfer(self, dest, src, sz:int, src_dev, dest_dev): pass class NullGraph(MultiGraphRunner): def __call__(self, input_rawbuffers, var_vals, wait=False) -> float|None: return 1e-3 class NullDevice(Compiled): - def __init__(self, device:str): super().__init__(device, NullAllocator(self), NullRenderer(), Compiler(), functools.partial(NullProgram, device), - NullGraph) + def __init__(self, device:str): super().__init__(device, NullAllocator(self), NullRenderer(), Compiler(), NullProgram, NullGraph) diff --git a/tinygrad_repo/tinygrad/runtime/ops_nv.py b/tinygrad_repo/tinygrad/runtime/ops_nv.py index 81dbbd371..26f018c87 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_nv.py +++ b/tinygrad_repo/tinygrad/runtime/ops_nv.py @@ -1,20 +1,20 @@ from __future__ import annotations -import os, ctypes, contextlib, re, functools, mmap, struct, array, sys, weakref +import os, ctypes, contextlib, re, functools, mmap, struct, array, sys, weakref, traceback assert sys.platform != 'win32' -from typing import cast, ClassVar +from typing import cast, Union, ClassVar from dataclasses import dataclass from tinygrad.runtime.support.hcq import HCQCompiled, HCQAllocator, HCQBuffer, HWQueue, CLikeArgsState, HCQProgram, HCQSignal, BumpAllocator from tinygrad.runtime.support.hcq import MMIOInterface, FileIOInterface, MOCKGPU from tinygrad.uop.ops import sint from tinygrad.device import BufferSpec -from tinygrad.helpers import getenv, mv_address, round_up, data64, data64_le, prod, OSX, to_mv, hi32, lo32, suppress_finalizing +from tinygrad.helpers import getenv, mv_address, round_up, data64, data64_le, prod, OSX, to_mv, hi32, lo32 from tinygrad.renderer.ptx import PTXRenderer from tinygrad.renderer.cstyle import NVRenderer from tinygrad.runtime.support.compiler_cuda import CUDACompiler, PTXCompiler, PTX, NVPTXCompiler, NVCompiler from tinygrad.runtime.autogen import nv_gpu, pci from tinygrad.runtime.support.elf import elf_loader from tinygrad.runtime.support.nv.nvdev import NVDev, NVMemoryManager -from tinygrad.runtime.support.system import System, PCIIfaceBase, MAP_FIXED +from tinygrad.runtime.support.system import System, PCIIfaceBase if getenv("IOCTL"): import extra.nv_gpu_driver.nv_ioctl # noqa: F401 # pylint: disable=unused-import def get_error_str(status): return f"{status}: {nv_gpu.nv_status_codes.get(status, 'Unknown error')}" @@ -71,7 +71,11 @@ class QMD: if self.ver < 4: self.write(**{f'constant_buffer_addr_upper_{i}':hi32(addr), f'constant_buffer_addr_lower_{i}':lo32(addr)}) else: self.write(**{f'constant_buffer_addr_upper_shifted6_{i}':hi32(addr >> 6), f'constant_buffer_addr_lower_shifted6_{i}':lo32(addr >> 6)}) -class NVCommandQueue(HWQueue[HCQSignal, 'NVDevice', 'NVProgram', 'NVArgsState']): +class NVSignal(HCQSignal): + def __init__(self, base_buf:HCQBuffer|None=None, **kwargs): + super().__init__(base_buf, **kwargs, timestamp_divider=1000, dev_t=NVDevice) + +class NVCommandQueue(HWQueue[NVSignal, 'NVDevice', 'NVProgram', 'NVArgsState']): def __init__(self): self.active_qmd = None super().__init__() @@ -90,12 +94,12 @@ class NVCommandQueue(HWQueue[HCQSignal, 'NVDevice', 'NVProgram', 'NVArgsState']) if local_mem_tpc_bytes: self.nvm(1, nv_gpu.NVC6C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A, *data64(local_mem_tpc_bytes), 0xff) return self - def wait(self, signal:HCQSignal, value:sint=0): + def wait(self, signal:NVSignal, value:sint=0): self.nvm(0, nv_gpu.NVC56F_SEM_ADDR_LO, *data64_le(signal.value_addr), *data64_le(value), (3 << 0) | (1 << 24)) # ACQUIRE | PAYLOAD_SIZE_64BIT self.active_qmd = None return self - def timestamp(self, signal:HCQSignal): return self.signal(signal, 0) + def timestamp(self, signal:NVSignal): return self.signal(signal, 0) def bind(self, dev:NVDevice): self.binded_device = dev @@ -149,7 +153,7 @@ class NVComputeQueue(NVCommandQueue): self.active_qmd, self.active_qmd_buf = qmd, qmd_buf return self - def signal(self, signal:HCQSignal, value:sint=0): + def signal(self, signal:NVSignal, value:sint=0): if self.active_qmd is not None: for i in range(2): if self.active_qmd.read(f'release{i}_enable') == 0: @@ -176,7 +180,7 @@ class NVCopyQueue(NVCommandQueue): self.nvm(4, nv_gpu.NVC6B5_LAUNCH_DMA, 0x182) # TRANSFER_TYPE_NON_PIPELINED | DST_MEMORY_LAYOUT_PITCH | SRC_MEMORY_LAYOUT_PITCH return self - def signal(self, signal:HCQSignal, value:sint=0): + def signal(self, signal:NVSignal, value:sint=0): self.nvm(4, nv_gpu.NVC6B5_SET_SEMAPHORE_A, *data64(signal.value_addr), value) self.nvm(4, nv_gpu.NVC6B5_LAUNCH_DMA, 0x14) return self @@ -276,12 +280,13 @@ class NVAllocator(HCQAllocator['NVDevice']): def _alloc(self, size:int, options:BufferSpec) -> HCQBuffer: return self.dev.iface.alloc(size, cpu_access=options.cpu_access, host=options.host) - @suppress_finalizing def _free(self, opaque:HCQBuffer, options:BufferSpec): - self.dev.synchronize() - self.dev.iface.free(opaque) + try: + self.dev.synchronize() + self.dev.iface.free(opaque) + except AttributeError: pass - def _map(self, buf:HCQBuffer): return self.dev.iface.map(buf._base if buf._base is not None else buf) + def map(self, buf:HCQBuffer): self.dev.iface.map(buf._base if buf._base is not None else buf) @dataclass class GPFifo: @@ -291,11 +296,12 @@ class GPFifo: token: int put_value: int = 0 +MAP_FIXED, MAP_NORESERVE = 0x10, 0x400 class NVKIface: root = None fd_ctl: FileIOInterface fd_uvm: FileIOInterface - gpus_info: list|ctypes.Array = [] + gpus_info: Union[list, ctypes.Array] = [] # TODO: Need a proper allocator for va addresses # 0x1000000000 - 0x2000000000, reserved for system/cpu mappings @@ -360,7 +366,7 @@ class NVKIface: uvm.register_gpu(self.fd_uvm, rmCtrlFd=-1, gpu_uuid=self.gpu_uuid) uvm.register_gpu_vaspace(self.fd_uvm, gpuUuid=self.gpu_uuid, rmCtrlFd=self.fd_ctl.fd, hClient=self.root, hVaSpace=vaspace) - for dev in cast(list[NVDevice], [d for pg in HCQCompiled.peer_groups.values() for d in pg if isinstance(d, NVDevice) and not d.is_nvd()]): + for dev in cast(list[NVDevice], self.dev.devices): try: uvm.enable_peer_access(self.fd_uvm, gpuUuidA=self.gpu_uuid, gpuUuidB=dev.iface.gpu_uuid) except RuntimeError as e: raise RuntimeError(f"{e}. Make sure GPUs #{self.gpu_minor} & #{dev.iface.gpu_minor} have P2P enabled.") from e @@ -381,14 +387,14 @@ class NVKIface: if made.params.status != 0: raise RuntimeError(f"_gpu_map_to_cpu returned {get_error_str(made.params.status)}") return fd_dev.mmap(target, size, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED | (MAP_FIXED if target is not None else 0), 0) - def alloc(self, size:int, host=False, uncached=False, cpu_access=False, contiguous=False, map_flags=0, cpu_addr=None) -> HCQBuffer: + def alloc(self, size:int, host=False, uncached=False, cpu_access=False, contiguous=False, map_flags=0) -> HCQBuffer: # Uncached memory is "system". Use huge pages only for gpu memory. page_size = (4 << (12 if OSX else 10)) if uncached or host else ((2 << 20) if size >= (8 << 20) else (4 << (12 if OSX else 10))) size = round_up(size, page_size) va_addr = self._alloc_gpu_vaddr(size, alignment=page_size, force_low=cpu_access) if host: - va_addr = cpu_addr or FileIOInterface.anon_mmap(va_addr, size, mmap.PROT_READ|mmap.PROT_WRITE, MAP_FIXED|mmap.MAP_SHARED|mmap.MAP_ANONYMOUS, 0) + va_addr = FileIOInterface.anon_mmap(va_addr, size, mmap.PROT_READ | mmap.PROT_WRITE, MAP_FIXED | mmap.MAP_SHARED | mmap.MAP_ANONYMOUS, 0) flags = (nv_gpu.NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS << 4) | (nv_gpu.NVOS02_FLAGS_COHERENCY_CACHED << 12) \ | (nv_gpu.NVOS02_FLAGS_MAPPING_NO_MAP << 30) @@ -434,23 +440,21 @@ class NVKIface: # NOTE: va_addr is set to make rawbufs compatible with HCQBuffer protocol. return HCQBuffer(va_base, size, meta=uvm.map_external_allocation(self.fd_uvm, base=va_base, length=size, rmCtrlFd=self.fd_ctl.fd, - hClient=self.root, hMemory=mem_handle, gpuAttributesCount=1, perGpuAttributes=attrs, mapped_gpu_ids=[self.gpu_uuid], - has_cpu_mapping=has_cpu_mapping), view=MMIOInterface(va_base, size, fmt='B') if has_cpu_mapping else None, owner=self.dev) + hClient=self.root, hMemory=mem_handle, gpuAttributesCount=1, perGpuAttributes=attrs, + mapped_gpu_ids=[self.gpu_uuid], has_cpu_mapping=has_cpu_mapping), + view=MMIOInterface(va_base, size, fmt='B') if has_cpu_mapping else None) def map(self, mem:HCQBuffer): - if mem.owner is not None and mem.owner._is_cpu(): - if not any(x.device.startswith("NV") for x in mem.mapped_devs): return self.alloc(mem.size, host=True, cpu_addr=mem.va_addr) - mem = mem.mappings[next(x for x in mem.mapped_devs if x.device.startswith("NV"))] + if self.gpu_uuid in mem.meta.mapped_gpu_ids: return + mem.meta.mapped_gpu_ids.append(self.gpu_uuid) self._gpu_uvm_map(mem.va_addr, mem.size, mem.meta.hMemory, create_range=False) def _alloc_gpu_vaddr(self, size, alignment=(4 << 10), force_low=False): return NVKIface.low_uvm_vaddr_allocator.alloc(size, alignment) if force_low else NVKIface.uvm_vaddr_allocator.alloc(size, alignment) class PCIIface(PCIIfaceBase): - gpus:ClassVar[list[str]] = [] - def __init__(self, dev, dev_id): - super().__init__(dev, dev_id, vendor=0x10de, devices=[0x2204, 0x2684, 0x2b85], bars=[0, 1], vram_bar=1, + super().__init__(dev, dev_id, vendor=0x10de, devices=[0x2684], bars=[0, 1], vram_bar=1, va_start=NVMemoryManager.va_allocator.base, va_size=NVMemoryManager.va_allocator.size) System.reserve_hugepages(64) @@ -462,29 +466,36 @@ class PCIIface(PCIIfaceBase): self.rm_alloc(0, nv_gpu.NV01_ROOT, nv_gpu.NV0000_ALLOC_PARAMETERS()) # Setup classes for the GPU - self.gpfifo_class, self.compute_class, self.dma_class = (gsp:=self.dev_impl.gsp).gpfifo_class, gsp.compute_class, gsp.dma_class - - def alloc(self, size:int, host=False, uncached=False, cpu_access=False, contiguous=False, **kwargs) -> HCQBuffer: - # Force use of huge pages for large allocations. NVDev will attempt to use huge pages in any case, - # but if the size is not aligned, the tail will be allocated with 4KB pages, increasing TLB pressure. - page_size = (2 << 20) if size >= (8 << 20) and not uncached and not host else (4 << 10) - return super().alloc(round_up(size, page_size), host=host, uncached=uncached, cpu_access=cpu_access, contiguous=contiguous, **kwargs) + self.gpfifo_class, self.compute_class, self.dma_class = nv_gpu.AMPERE_CHANNEL_GPFIFO_A, nv_gpu.ADA_COMPUTE_A, nv_gpu.AMPERE_DMA_COPY_B def setup_usermode(self): return 0xce000000, self.pci_dev.map_bar(bar=0, fmt='I', off=0xbb0000, size=0x10000) def setup_vm(self, vaspace): pass def setup_gpfifo_vm(self, gpfifo): pass def rm_alloc(self, parent, clss, params=None, root=None) -> int: return self.dev_impl.gsp.rpc_rm_alloc(parent, clss, params, self.root) - def rm_control(self, obj, cmd, params=None): return self.dev_impl.gsp.rpc_rm_control(obj, cmd, params, self.root) + def rm_control(self, obj, cmd, params=None): + res = self.dev_impl.gsp.rpc_rm_control(obj, cmd, params, self.root) + return type(params).from_buffer_copy(res) if params is not None else None - def device_fini(self): self.dev_impl.fini() +class NVDevice(HCQCompiled[NVSignal]): + devices: ClassVar[list[HCQCompiled]] = [] + signal_pages: ClassVar[list[HCQBuffer]] = [] + signal_pool: ClassVar[list[HCQBuffer]] = [] -class NVDevice(HCQCompiled[HCQSignal]): def is_nvd(self) -> bool: return isinstance(self.iface, PCIIface) + def _select_iface(self): + if len(nm:=getenv("NV_IFACE", "")) > 0: return getattr(sys.modules[__name__], f"{nm.upper()}Iface")(self, self.device_id) + + errs:str = "" + for iface_t in (NVKIface, PCIIface): + try: return iface_t(self, self.device_id) + except Exception: errs += f"\n{iface_t.__name__}: {traceback.format_exc()}" + raise RuntimeError(f"Cannot find a usable interface for NV:{self.device_id}:\n{errs}") + def __init__(self, device:str=""): self.device_id = int(device.split(":")[1]) if ":" in device else 0 - self.iface = self._select_iface(NVKIface, PCIIface) + self.iface = self._select_iface() device_params = nv_gpu.NV0080_ALLOC_PARAMETERS(deviceId=self.iface.gpu_instance, hClientShare=self.iface.root, vaMode=nv_gpu.NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES) @@ -527,7 +538,7 @@ class NVDevice(HCQCompiled[HCQSignal]): compiler_t = (PTXCompiler if PTX else CUDACompiler) if MOCKGPU else (NVPTXCompiler if PTX else NVCompiler) super().__init__(device, NVAllocator(self), PTXRenderer(self.arch, device="NV") if PTX else NVRenderer(self.arch), compiler_t(self.arch), - functools.partial(NVProgram, self), HCQSignal, NVComputeQueue, NVCopyQueue) + functools.partial(NVProgram, self), NVSignal, NVComputeQueue, NVCopyQueue) self._setup_gpfifos() @@ -571,13 +582,13 @@ class NVDevice(HCQCompiled[HCQSignal]): self.shared_mem_window, self.local_mem_window = 0x729400000000, 0x729300000000 NVComputeQueue().setup(compute_class=self.iface.compute_class, local_mem_window=self.local_mem_window, shared_mem_window=self.shared_mem_window) \ - .signal(self.timeline_signal, self.next_timeline()).submit(self) + .signal(self.timeline_signal, self.timeline_value).submit(self) - NVCopyQueue().wait(self.timeline_signal, self.timeline_value - 1) \ - .setup(copy_class=self.iface.dma_class) \ - .signal(self.timeline_signal, self.next_timeline()).submit(self) + cast(NVCopyQueue, NVCopyQueue().wait(self.timeline_signal, self.timeline_value)) \ + .setup(copy_class=self.iface.dma_class) \ + .signal(self.timeline_signal, self.timeline_value + 1).submit(self) - self.synchronize() + self.timeline_value += 2 def _ensure_has_local_memory(self, required): if self.slm_per_thread >= required or ((maxlm:=getenv("NV_MAX_LOCAL_MEMORY_PER_THREAD")) > 0 and required >= maxlm): return diff --git a/tinygrad_repo/tinygrad/runtime/ops_python.py b/tinygrad_repo/tinygrad/runtime/ops_python.py index f5550abd7..0cdc59850 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_python.py +++ b/tinygrad_repo/tinygrad/runtime/ops_python.py @@ -2,41 +2,31 @@ # a python uops emulator # works to test the tensor cores, and all the uops in general # this is the (living) definition of uops -from typing import Any, TYPE_CHECKING +from typing import Optional, Any, TYPE_CHECKING import pickle, base64, itertools, time, struct, sys -from tinygrad.dtype import DType, dtypes, ImageDType, PtrDType, truncate, float_to_bf16 +from tinygrad.dtype import DType, dtypes, ImageDType, PtrDType, truncate from tinygrad.helpers import all_same, getenv, flatten, get_single_element from tinygrad.device import Compiled, Compiler, Allocator -from tinygrad.codegen.opt import tc -from tinygrad.uop.ops import exec_alu, python_alu, Ops, UOp, GroupOp +from tinygrad.uop.ops import exec_alu, Ops, UOp, GroupOp from tinygrad.renderer import Renderer +from tinygrad.renderer.cstyle import CUDARenderer, MetalRenderer, AMDRenderer, IntelRenderer, ClangRenderer -def storage_fmt_for_dtype(dtype: DType): return 'H' if dtype == dtypes.bfloat16 else dtype.fmt - -def to_storage_scalar(x, dtype: DType): - if dtype == dtypes.bfloat16: return (struct.unpack('I', struct.pack('f', float_to_bf16(x)))[0] >> 16) & 0xFFFF - return x - -def from_storage_scalar(x, dtype: DType): - if dtype == dtypes.bfloat16: return struct.unpack('f', struct.pack('I', (x & 0xFFFF) << 16))[0] - return x - -def _load(m, i, dtype: DType): +def _load(m, i): if i is None: return 0.0 if i < 0 or i >= len(m): raise IndexError(f"load out of bounds, size is {len(m)} and access is {i}") - return from_storage_scalar(m[i], dtype) + return m[i] -def load(inp, j, dtype: DType): - if len(inp) == 2: return [_load(m, x+j if x is not None else None, dtype) if gate else default for (m,x,gate),default in zip(*inp)] - return [_load(m, x+j if x is not None else None, dtype) for m,x,_ in inp[0]] +def load(inp, j=0): + if len(inp) == 2: return [_load(m, x+j if x is not None else None) if gate else default for (m,x,gate),default in zip(*inp)] + return [_load(m, x+j if x is not None else None) for m,x,_ in inp[0]] -def _store(m, i, v, dtype: DType): +def _store(m, i, v): if i < 0 or i >= len(m): raise IndexError(f"store out of bounds, size is {len(m)}, access is {i}, value is {v}") - m[i] = to_storage_scalar(v, dtype) + m[i] = v class PythonProgram: def __init__(self, name:str, lib:bytes): - self.uops: list[tuple[Ops, DType|None, list[int], Any]] = pickle.loads(lib) + self.uops: list[tuple[Ops, Optional[DType], list[int], Any]] = pickle.loads(lib) def __call__(self, *bufs, global_size:tuple[int,int,int]=(1,1,1), local_size:tuple[int,int,int]=(1,1,1), vals:tuple[int, ...]=(), wait=False): st = time.perf_counter() warp = list(itertools.product(*[range(x) for x in local_size[::-1]])) @@ -50,43 +40,45 @@ class PythonProgram: loop_ends: dict[int, int] = {} while i < len(self.uops): uop, dtype, idp, arg = self.uops[i] - void_ops = {Ops.ENDRANGE, Ops.BARRIER, Ops.IF, Ops.ENDIF, Ops.SINK, Ops.NOOP, Ops.STORE} + void_ops = {Ops.STORE, Ops.ENDRANGE, Ops.BARRIER, Ops.IF, Ops.ENDIF, Ops.SINK} + if uop is Ops.DEFINE_ACC: idp = [idp[0]] inp = [ul[v] for v in idp if self.uops[v][0] not in void_ops] dtp = [dl[v] for v in idp if self.uops[v][0] not in void_ops] if getenv("TRACE"): print(i, uop, dtype, arg, inp, dtp) + if uop is Ops.STORE: + assert len(inp) == 2, "expected store is ([(memory, offset, gate)], [value])" + if dtp[1].count > 1: + for j,val in enumerate(inp[1]): + for (m,o,g),v in zip(inp[0], val): + if g: _store(m, o+j, v) + else: + for (m,o,g),v in zip(*inp): + if g: _store(m, o, v) + i += 1 + continue if uop is Ops.ENDRANGE: loop_ends[idp[0]] = i i = idp[0] continue - if uop in (Ops.BARRIER, Ops.IF, Ops.ENDIF, Ops.SINK, Ops.NOOP): + if uop in (Ops.BARRIER, Ops.IF, Ops.ENDIF, Ops.SINK): # in the python emulator, the warp is always in sync i += 1 continue assert dtype is not None, f"{uop} is missing a dtype" dl[i] = dtype - if uop is Ops.STORE: - for j,val in enumerate(inp[1] if dtp[1].count > 1 else [inp[1]]): - for (m,o,g),v in zip(inp[0], val): - if g: _store(m, o+j, v, dtp[1].scalar()) - i += 1 - continue - if uop in {Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL, Ops.DEFINE_REG}: - assert isinstance(dtype, PtrDType), dtype - storage_fmt = storage_fmt_for_dtype(dtype.base.scalar()) - if storage_fmt is None: raise RuntimeError(f"{dtype=} is not supported") - if TYPE_CHECKING or sys.version_info < (3, 12): assert storage_fmt != "e" - if uop is Ops.DEFINE_REG: - # REGs are per thread - ul[i] = [memoryview(bytearray(dtype.size*dtype.itemsize)).cast(storage_fmt) for _ in range(warp_size)] - else: - buf = memoryview(bytearray(dtype.size*dtype.itemsize)) if uop is not Ops.DEFINE_GLOBAL else pbufs.pop(0) - ul[i] = [buf.cast(storage_fmt)] * warp_size + if uop in {Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL}: + assert dtype.fmt is not None and isinstance(dtype, PtrDType) + if TYPE_CHECKING or sys.version_info < (3, 12): assert dtype.fmt != "e" + buf = memoryview(bytearray(dtype.size*dtype.itemsize)) if uop is Ops.DEFINE_LOCAL else pbufs.pop(0) + ul[i] = [buf.cast(dtype.fmt)] * warp_size elif uop is Ops.DEFINE_VAR: ul[i] = [pvals.pop(0)] * warp_size elif uop is Ops.SPECIAL: if arg[0][0] == 'g': ul[i] = [idxs[2-int(arg[0][-1])]] * warp_size elif arg[0][0] == 'l': ul[i] = [x[2-int(arg[0][-1])] for x in warp] elif uop is Ops.CONST: ul[i] = [arg] * warp_size + elif uop is Ops.DEFINE_ACC: + ul[i] = [[inp[0][0][0]] * warp_size for _ in range(dtype.count)] if dtype.count > 1 else [inp[0][0]] * warp_size elif uop is Ops.INDEX: ret:list = [] if isinstance(dtp[0], ImageDType): @@ -109,17 +101,19 @@ class PythonProgram: continue elif uop is Ops.VECTORIZE: ul[i] = inp elif uop is Ops.BITCAST: - packed = struct.pack(str(warp_size) + storage_fmt_for_dtype(dtp[0].scalar()), *[to_storage_scalar(x, dtp[0].scalar()) for x in inp[0]]) - ul[i] = list(struct.unpack(str(warp_size) + storage_fmt_for_dtype(dtype.scalar()), packed)) - ul[i] = [from_storage_scalar(x, dtype.scalar()) for x in ul[i]] + assert dtp[0].fmt and dtype.fmt + pack_format, unpack_format = str(warp_size) + dtp[0].fmt, str(warp_size) + dtype.fmt + ul[i] = list(struct.unpack(unpack_format, struct.pack(pack_format, *inp[0]))) elif uop is Ops.CAST: ul[i] = [truncate.get(dtype, lambda dt: dt)(dtypes.as_const(x, dtype)) for x in inp[0]] elif uop is Ops.LOAD: if dtype.count > 1: - ul[i] = [load([inp[i][j] if i != 0 and dtp[i].count > 1 else inp[i] for i in range(len(inp))], j, dtype.scalar()) \ - for j in range(dtype.count)] + ul[i] = [load([inp[i][j] if i != 0 and dtp[i].count > 1 else inp[i] for i in range(len(inp))], j) for j in range(dtype.count)] else: - ul[i] = load(inp, 0, dtype) + ul[i] = load(inp) + elif uop is Ops.ASSIGN: + for j in range(len(inp[0])): inp[0][j] = inp[1][j] + ul[i] = inp[0] elif uop is Ops.GEP: ul[i] = inp[0][get_single_element(arg)] elif uop is Ops.WMMA: # here are the models for the WMMA instruction on the different hardware @@ -136,27 +130,24 @@ class PythonProgram: out[elem_idx][goff+lane_id] += sum(a_elem(inp[0], _k, c_j, goff) * b_elem(inp[1], c_i, _k, goff) for _k in range(K)) return out - first_src_dtype = self.uops[idp[0]][1] - assert isinstance(first_src_dtype, DType) # mypy - dims, dtype_in, device, threads = arg[1], first_src_dtype.scalar(), arg[4], arg[5] # TODO: refactor these to a shared TensorCoreLayout in kernel.py - if device == "METAL": + if arg[4] == "METAL": # A (2 elements on 32 threads): row major def a_b_elem(x, i, j, goff): return x[(i%2)][goff+(i//2)%2+(j%4)*2+(i//4)*8+(j//4)*16] # (i, j), C, D (2 elements on 32 threads): row major same as A/B def c_map(lane, elem): return (elem + ((lane%2)*2) + ((lane//8)%2)*4, ((lane//2)%4) + (lane//16)*4) ul[i] = wmma_helper(32, 8, 2, 2, 2, a_b_elem, a_b_elem, c_map) - elif device == "AMD" and threads == 64: + elif arg[4] == "AMD" and arg[5] == 64: def a_elem(x, k, row, goff): return x[k%4][goff + (k//4)*16 + row] def b_elem(x, col, k, goff): return a_elem(x, k, col, goff) # pylint: disable=arguments-out-of-order def c_map(lane, elem): return (lane%16, (lane//16)*4 + elem) ul[i] = wmma_helper(64, 16, 4, 4, 4, a_elem, b_elem, c_map) - elif device == "AMD" and len(inp[0]) == 8: # RDNA4 + elif arg[4] == "AMD" and len(inp[0]) == 8: # RDNA4 def a_elem(x, k, row, goff): return x[k - [0, 4, 4, 8][k//4]][goff + row + [0, 16, 0, 16][k//4]] def b_elem(x, col, k, goff): return a_elem(x, k, col, goff) def c_map(lane, elem): return (lane%16, (lane//16)*8 + elem) ul[i] = wmma_helper(32, 16, 8, 8, 8, a_elem, b_elem, c_map) - elif device == "AMD": + elif arg[4] == "AMD": # A (16 elements on 32 threads): col major, lane 16-32 == lane 0-15 def a_elem(x, k, row, goff): assert x[k][goff+row] == x[k][goff+row+16], "warp elements not duplicated properly across lanes" @@ -165,27 +156,27 @@ class PythonProgram: def b_elem(x, col, k, goff): return a_elem(x, k, col, goff) # pylint: disable=arguments-out-of-order def c_map(lane, elem): return (lane%16, lane//16+elem*2) # (i, j), C, D (8 elements on 32 threads): row major ul[i] = wmma_helper(32, 16, 16, 16, 8, a_elem, b_elem, c_map) - elif device == "CUDA": + elif arg[4] == "CUDA": # (col, row) given (lane, elem) for C & D (4 elements on 32 threads); shared by all tc shapes with M=16 N=8 def c_map(lane, elem): return (elem%2 + (lane%4)*2, lane//4 + (elem//2)*8) - if dims == (8,16,16): + if arg[1] == (8,16,16): def a_elem(x, k, row, goff): return x[k%2 + (row//8)*2 + (k//8)*4][goff + (k//2)%4 + (row%8)*4] def b_elem(x, col, k, goff): return x[k%2 + (k//8)*2][goff + (k//2)%4 + col*4] ul[i] = wmma_helper(32, 16, 8, 4, 4, a_elem, b_elem, c_map) - elif dims == (8,16,8) and dtype_in == dtypes.half: + elif arg[1] == (8,16,8) and arg[2] == dtypes.half: def a_elem(x, k, row, goff): return x[k%2 + (row//8)*2][goff + k//2 + (row%8)*4] def b_elem(x, col, k, goff): return x[k%2][goff + k//2 + col*4] ul[i] = wmma_helper(32, 8, 4, 2, 4, a_elem, b_elem, c_map) - elif dims == (8,16,8) and dtype_in == dtypes.float: + elif arg[1] == (8,16,8) and arg[2] == dtypes.float: def a_elem(x, k, row, goff): return x[(k//4)*2 + row//8][goff + k%4 + (row%8)*4] def b_elem(x, col, k, goff): return x[k//4][goff + k%4 + col*4] ul[i] = wmma_helper(32, 8, 4, 2, 4, a_elem, b_elem, c_map) else: raise NotImplementedError(f"unimplemented tensor core {arg}") - elif device == "INTEL": + elif arg[4] == "INTEL": # A (16 elements on 8 threads) def a_elem(x, k, row, goff): return x[k%2+row*2][goff+k//2] # B (16 elements on 8 threads) @@ -193,14 +184,14 @@ class PythonProgram: # C, D (8 elements on 8 threads) def c_map(lane, elem): return (lane, elem) ul[i] = wmma_helper(8, 16, 16, 16, 8, a_elem, b_elem, c_map) - elif device == "CPU": + elif arg[4] == "CPU": def elem(x, col, row, _): return x[col+row][0] # k is always 0 def c_map(_, elem): return (elem%16, elem//16) ul[i] = wmma_helper(1, 1, 16, 16, 256, elem, elem, c_map) else: raise NotImplementedError(f"unimplemented tensor core {arg}") elif uop in GroupOp.ALU: assert all_same([len(x) for x in inp]), f"{[len(x) for x in inp]} doesn't match on {uop}" - assert all_same([dtype] + dtp) or uop in {*GroupOp.Comparison, Ops.WHERE}, f"dtype mismatch on {uop}" + assert all_same([dtype] + dtp) or uop in {Ops.CMPNE, Ops.CMPLT, Ops.WHERE}, f"dtype mismatch on {uop}" ul[i] = [exec_alu(uop, dtype, p) for p in zip(*inp)] assert i in ul, (uop, dtype, idp, arg) i += 1 @@ -208,16 +199,15 @@ class PythonProgram: class PythonRenderer(Renderer): device = "PYTHON" - code_for_op = python_alu def __init__(self): - if getenv("EMULATE_METAL"): self.device, self.tensor_cores = "METAL", tc.metal - if getenv("EMULATE_AMD"): self.device, self.tensor_cores = "AMD", tc.amd_rdna3 - if getenv("EMULATE_AMD_MFMA"): self.device, self.tensor_cores = "AMD", tc.amd_cdna - if getenv("EMULATE_AMD_RDNA4"): self.device, self.tensor_cores = "AMD", tc.amd_rdna4 - if getenv("EMULATE_CUDA"): self.device, self.tensor_cores = "CUDA", tc.cuda_sm80 - if getenv("EMULATE_CUDA_SM75"): self.device, self.tensor_cores = "CUDA", tc.cuda_sm75 - if getenv("EMULATE_INTEL"): self.device, self.suffix, self.tensor_cores = "INTEL", "INTEL", tc.intel - if getenv("EMULATE_AMX"): self.device, self.tensor_cores = "CPU", tc.amx + if getenv("EMULATE_METAL"): self.device, self.tensor_cores = "METAL", MetalRenderer.tensor_cores + if getenv("EMULATE_AMD"): self.device, self.tensor_cores = "AMD", AMDRenderer.tensor_cores + if getenv("EMULATE_AMD_MFMA"): self.device, self.tensor_cores = "AMD", AMDRenderer.tensor_cores_mfma + if getenv("EMULATE_AMD_RDNA4"): self.device, self.tensor_cores = "AMD", AMDRenderer.tensor_cores_rdna4 + if getenv("EMULATE_CUDA"): self.device, self.tensor_cores = "CUDA", CUDARenderer.tc_sm80 + if getenv("EMULATE_CUDA_SM75"): self.device, self.tensor_cores = "CUDA", CUDARenderer.tc_sm75 + if getenv("EMULATE_INTEL"): self.device, self.suffix, self.tensor_cores = "INTEL", "INTEL", IntelRenderer.tensor_cores + if getenv("EMULATE_AMX"): self.device, self.tensor_cores = "CPU", ClangRenderer.tensor_cores def render(self, uops:list[UOp]) -> str: lops = [(u.op, u.dtype, [uops.index(v) for v in u.src], u.arg) for u in uops] diff --git a/tinygrad_repo/tinygrad/runtime/ops_qcom.py b/tinygrad_repo/tinygrad/runtime/ops_qcom.py index bc0857a67..08501812d 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_qcom.py +++ b/tinygrad_repo/tinygrad/runtime/ops_qcom.py @@ -2,7 +2,7 @@ from __future__ import annotations import os, ctypes, functools, mmap, struct, array, math, sys, weakref assert sys.platform != 'win32' from types import SimpleNamespace -from typing import Any, cast +from typing import Any, cast, ClassVar from tinygrad.device import BufferSpec from tinygrad.runtime.support.hcq import HCQBuffer, HWQueue, HCQProgram, HCQCompiled, HCQAllocatorBase, HCQSignal, HCQArgsState, BumpAllocator from tinygrad.runtime.support.hcq import FileIOInterface, MMIOInterface @@ -37,12 +37,14 @@ class QCOMCompiler(CLCompiler): def disassemble(self, lib:bytes): fromimport('extra.disassemblers.adreno', 'disasm')(lib) class QCOMSignal(HCQSignal): - def __init__(self, *args, **kwargs): super().__init__(*args, **{**kwargs, 'timestamp_divider': 19.2}) + def __init__(self, base_buf:HCQBuffer|None=None, **kwargs): + super().__init__(base_buf, **kwargs, timestamp_divider=19.2, dev_t=QCOMDevice) def _sleep(self, time_spent_waiting_ms:int): - # Sleep only for timeline signals. Do it immediately to free cpu. - if self.is_timeline and self.owner is not None: - kgsl.IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID(self.owner.fd, context_id=self.owner.ctx, timestamp=self.owner.last_cmd, timeout=0xffffffff) + # Sleep only for only timeline signals. Do it immediately to free cpu. + if self.timeline_for_device is not None: + kgsl.IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID(self.timeline_for_device.fd, context_id=self.timeline_for_device.ctx, + timestamp=self.timeline_for_device.last_cmd, timeout=0xffffffff) class QCOMComputeQueue(HWQueue): def __del__(self): @@ -278,7 +280,7 @@ class QCOMAllocator(HCQAllocatorBase): pitch = round_up((real_stride:=imgw * 4 * options.image.itemsize), 1 << pitchalign) + pitch_add size = pitch * imgh - buf = HCQBuffer(options.external_ptr, size, owner=self.dev) if options.external_ptr else self.dev._gpu_alloc(size) + buf = HCQBuffer(options.external_ptr, size) if options.external_ptr else self.dev._gpu_alloc(size) if options.image is not None: tex_fmt = adreno.FMT6_32_32_32_32_FLOAT if options.image.itemsize == 4 else adreno.FMT6_16_16_16_16_FLOAT @@ -313,6 +315,10 @@ class QCOMAllocator(HCQAllocatorBase): self.dev._gpu_free(opaque) class QCOMDevice(HCQCompiled): + devices: ClassVar[list[HCQCompiled]] = [] + signal_pages: ClassVar[list[HCQBuffer]] = [] + signal_pool: ClassVar[list[HCQBuffer]] = [] + gpu_id: int = 0 dummy_addr: int = 0 @@ -352,7 +358,7 @@ class QCOMDevice(HCQCompiled): va_addr = self.fd.mmap(0, bosz, mmap.PROT_READ | mmap.PROT_WRITE, mmap.MAP_SHARED, alloc.id * 0x1000) if fill_zeroes: ctypes.memset(va_addr, 0, size) - return HCQBuffer(va_addr=va_addr, size=size, meta=alloc, view=MMIOInterface(va_addr, size, fmt='B'), owner=self) + return HCQBuffer(va_addr=va_addr, size=size, meta=alloc, view=MMIOInterface(va_addr, size, fmt='B')) def _gpu_free(self, mem:HCQBuffer): kgsl.IOCTL_KGSL_GPUOBJ_FREE(self.fd, id=mem.meta.id) diff --git a/tinygrad_repo/tinygrad/runtime/ops_remote.py b/tinygrad_repo/tinygrad/runtime/ops_remote.py index 27ca50d9c..531bbb253 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_remote.py +++ b/tinygrad_repo/tinygrad/runtime/ops_remote.py @@ -5,11 +5,10 @@ # it should be a secure (example: no use of pickle) boundary. HTTP is used for RPC from __future__ import annotations -from typing import Callable, Iterator, Any, cast +from typing import Callable, Iterator, Optional, Any, cast from collections import defaultdict from dataclasses import dataclass, field, replace -import multiprocessing, threading, functools, itertools, asyncio, http, http.client, hashlib, time, os, binascii, struct, ast, contextlib, weakref -import traceback, builtins +import multiprocessing, functools, itertools, asyncio, http, http.client, hashlib, time, os, binascii, struct, ast, contextlib, weakref from tinygrad.renderer import Renderer, ProgramSpec from tinygrad.dtype import DTYPES_DICT, dtypes from tinygrad.uop.ops import UOp, Ops, Variable, sint @@ -17,7 +16,6 @@ from tinygrad.helpers import getenv, DEBUG, fromimport, unwrap, LazySeq, Timing from tinygrad.engine.jit import GraphRunner, MultiGraphRunner, ExecItem, graph_class from tinygrad.engine.realize import CompiledRunner, BufferXfer from tinygrad.device import Compiled, Buffer, Allocator, Compiler, Device, BufferSpec -from tinygrad.runtime.support.ib import IBCtx, IBConn, SGE # ***** API ***** @@ -37,12 +35,6 @@ class RemoteProperties: offset_supported: bool graph_supported: bool graph_supports_multi: bool - ib_gid: bytes|None - -@dataclass(frozen=True) -class RemoteException: - exc: Exception - trace: str = "" @dataclass(frozen=True) class GetProperties(RemoteRequest): pass @@ -53,18 +45,12 @@ class Event(RemoteRequest): event_session: SessionKey; event: int # noqa: E702 @dataclass(frozen=True) class Wait(RemoteRequest): event: int -@dataclass(frozen=True) -class IBConnect(RemoteRequest): host: str; gid: bytes; qp_num: int # noqa: E702 - @dataclass(frozen=True) class BufferAlloc(RemoteRequest): buffer_num: int; size: int; options: BufferSpec # noqa: E702 @dataclass(frozen=True) class BufferOffset(RemoteRequest): buffer_num: int; size: int; offset: int; sbuffer_num: int # noqa: E702 -@dataclass(frozen=True) -class BufferIOVAS(RemoteRequest): buffer_nums: list[tuple[SessionKey, int]] # noqa: E702 - @dataclass(frozen=True) class BufferFree(RemoteRequest): buffer_num: int # noqa: E702 @@ -77,11 +63,6 @@ class CopyOut(RemoteRequest): buffer_num: int @dataclass(frozen=True) class Transfer(RemoteRequest): buffer_num: int; dsession: SessionKey; dbuffer_num: int # noqa: E702 -@dataclass(frozen=True) -class BatchTransfer(RemoteRequest): - sbuffer_nums: list[tuple[SessionKey, int]] - dbuffer_nums: list[tuple[SessionKey, int]] - @dataclass(frozen=True) class ProgramAlloc(RemoteRequest): name: str; datahash: str # noqa: E702 @@ -91,7 +72,7 @@ class ProgramFree(RemoteRequest): name: str; datahash: str # noqa: E702 @dataclass(frozen=True) class ProgramExec(RemoteRequest): name: str; datahash: str; bufs: tuple[int, ...]; vals: tuple[int, ...] # noqa: E702 - global_size: tuple[int, ...]|None; local_size: tuple[int, ...]|None; wait: bool # noqa: E702 + global_size: Optional[tuple[int, ...]]; local_size: Optional[tuple[int, ...]]; wait: bool # noqa: E702 @dataclass(frozen=True) class GraphComputeItem: @@ -125,10 +106,9 @@ class GraphExec(RemoteRequest): wait: bool # for safe deserialization -eval_excs = [v for k,v in builtins.__dict__.items() if isinstance(v, type) and issubclass(v, Exception) and not k.endswith("Warning")] -eval_globals = {x.__name__:x for x in [SessionKey, SessionFree, RemoteProperties, GetProperties, Event, Wait, BufferAlloc, BufferOffset, BufferIOVAS, - BufferFree, CopyIn, CopyOut, Transfer, BatchTransfer, IBConnect, ProgramAlloc, ProgramFree, ProgramExec, - GraphComputeItem, GraphAlloc, GraphFree, GraphExec, BufferSpec, UOp, Ops, dtypes, RemoteException] + eval_excs} +eval_globals = {x.__name__:x for x in [SessionKey, SessionFree, RemoteProperties, GetProperties, Event, Wait, BufferAlloc, BufferOffset, BufferFree, + CopyIn, CopyOut, Transfer, ProgramAlloc, ProgramFree, ProgramExec, GraphComputeItem, GraphAlloc, GraphFree, + GraphExec, BufferSpec, UOp, Ops, dtypes]} attribute_whitelist: dict[Any, set[str]] = {dtypes: {*DTYPES_DICT.keys(), 'imagef', 'imageh'}, Ops: {x.name for x in Ops}} eval_fxns = {ast.Constant: lambda x: x.value, ast.Tuple: lambda x: tuple(map(safe_eval, x.elts)), ast.List: lambda x: list(map(safe_eval, x.elts)), ast.Dict: lambda x: {safe_eval(k):safe_eval(v) for k,v in zip(x.keys, x.values)}, @@ -175,12 +155,6 @@ class RemoteHandler: self.base_device = base_device self.sessions: defaultdict[SessionKey, RemoteSession] = defaultdict(RemoteSession) - try: self.ib_ctx: IBCtx|None = IBCtx(getenv("IB_DEV", 0)) - except (IndexError, AttributeError): self.ib_ctx = None - self.ib_lock = asyncio.Lock() - self.ib_conns: dict[str, IBConn|None] = {} - self.iova_cache: dict[tuple[SessionKey, int], tuple[int, int, int]] = {} - async def __call__(self, reader:asyncio.StreamReader, writer:asyncio.StreamWriter): while (req_hdr:=(await reader.readline()).decode().strip()): req_method, req_path, _ = req_hdr.split(' ') @@ -189,36 +163,9 @@ class RemoteHandler: key, value = hdr.split(':', 1) req_headers[key.lower()] = value.strip() req_body = await reader.readexactly(int(req_headers.get("content-length", "0"))) - try: res_status, res_body = await self.handle(req_method, req_path, req_body) - except Exception as e: - res_status, res_body = http.HTTPStatus.INTERNAL_SERVER_ERROR, repr(RemoteException(e, traceback.format_exc())).encode() - print(f"{traceback.format_exc()}", flush=True) + res_status, res_body = await self.handle(req_method, req_path, req_body) writer.write(f"HTTP/1.1 {res_status.value} {res_status.phrase}\r\nContent-Length: {len(res_body)}\r\n\r\n".encode() + res_body) - async def ib_connect(self, ssession:SessionKey, dsession:SessionKey) -> IBConn|None: - if self.ib_ctx is None: return None - await self.ib_lock.acquire() - conn = RemoteConnection(dsession.host) - if dsession.host not in self.ib_conns: - props = safe_eval(ast.parse(conn.q(GetProperties(session=dsession), wait=True), mode="eval").body) - if props.ib_gid is not None: - self.ib_conns[dsession.host] = ib_conn = IBConn(self.ib_ctx) - ibxc_ret = conn.q(IBConnect(ssession.host, ib_conn.gid, ib_conn.qp_num, session=dsession), wait=True) - ib_conn.connect(*struct.unpack('<16sQ', ibxc_ret)) - else: - self.ib_conns[dsession.host] = None - self.ib_lock.release() - return self.ib_conns[dsession.host] - - async def get_iovas(self, bufs:list[tuple[SessionKey, int]]) -> list[tuple[int, int, int]]: - await self.ib_lock.acquire() - if (rbufs:=[buf for buf in bufs if buf not in self.iova_cache]): - conn = RemoteConnection(rbufs[0][0].host) - resp = await conn.aq(BufferIOVAS(rbufs, session=rbufs[0][0]), wait=True) - self.iova_cache.update({rbuf: struct.unpack(' tuple[http.HTTPStatus, bytes]: status, ret = http.HTTPStatus.OK, b"" if path == "/batch" and method == "POST": @@ -235,34 +182,22 @@ class RemoteHandler: graph_cls = graph_class(Device[self.base_device]) rp = RemoteProperties( real_device=dev.device, renderer=(cls.__module__, cls.__name__, args), offset_supported=hasattr(dev.allocator, '_offset'), - graph_supported=graph_cls is not None, - graph_supports_multi=graph_cls is not None and issubclass(graph_cls, MultiGraphRunner) and hasattr(dev.allocator, '_transfer'), - ib_gid=bytes(self.ib_ctx.gid_attr.raw) if self.ib_ctx is not None else None, + graph_supported=graph_cls is not None, graph_supports_multi=graph_cls is not None and issubclass(graph_cls, MultiGraphRunner), ) ret = repr(rp).encode() case Event(): if c.session == c.event_session: session.events[c.event].set() else: - for d in Device._opened_devices: Device[d].synchronize() # wait for device*s* to finish executing previous stuff + dev.synchronize() # wait for device to finish executing previous stuff # TODO: don't wait, just send - await RemoteConnection(c.event_session.host).aq(Event(c.event_session, c.event, session=c.event_session), wait=True) + RemoteConnection(c.event_session.host).q(Event(c.event_session, c.event, session=c.event_session), wait=True) case Wait(): assert await session.events[c.event].wait() del session.events[c.event] # do not leak memory - case IBConnect(): - self.ib_conns[c.host] = ibc = IBConn(unwrap(self.ib_ctx)) - ibc.connect(c.gid, c.qp_num) - ret = struct.pack('<16sQ', ibc.gid, ibc.qp_num) case BufferAlloc(): assert c.buffer_num not in session.buffers, f"buffer {c.buffer_num} already allocated" session.buffers[c.buffer_num] = Buffer(dev.device, c.size, dtypes.uint8, options=c.options, preallocate=True) - case BufferIOVAS(): - rets = [] - for buffer_session,buffer_num in c.buffer_nums: - iova, mr = unwrap(self.ib_ctx).reg(buf:=self.sessions[buffer_session].buffers[buffer_num]) - rets.append(struct.pack("=3): for conn,data in datas.items(): conn.conn.request("POST", "/batch", data) for conn in datas.keys(): - resp = conn.conn.getresponse() - body = resp.read() - resps.append((conn, resp, body)) + response = conn.conn.getresponse() + assert response.status == 200, f"POST /batch failed: {response}" + resp = response.read() + if conn == self: ret = resp conn.req = BatchRequest() - if take_q: RemoteConnection.q_lock.release() - for conn,resp,body in resps: - match resp.status: - case http.HTTPStatus.OK: pass - case http.HTTPStatus.INTERNAL_SERVER_ERROR: - exc_wrapper = safe_eval(ast.parse(body.decode(), mode="eval").body) - exc_wrapper.exc.add_note(exc_wrapper.trace) - raise exc_wrapper.exc - case code: raise RuntimeError(f"POST /batch failed with {code}: {body.decode()}") - if conn == self: ret = body return ret def parse_hosts(hs:str) -> list[tuple[str, int]]|LazySeq[tuple[str, int]]: @@ -473,8 +371,9 @@ class RemoteDevice(Compiled): if not issubclass(renderer_class, Renderer): raise RuntimeError(f"renderer isn't a Renderer {renderer}") renderer_instance = renderer_class(*renderer[2]) renderer_instance.device = device - graph = fromimport('tinygrad.runtime.graph.remote', "RemoteGraph") if self.properties.graph_supported else None - super().__init__(device, RemoteAllocator(self), renderer_instance, Compiler(), functools.partial(RemoteProgram, self), graph, id(self.conn)) + graph_supported, graph_multi = self.properties.graph_supported, self.properties.graph_supports_multi + graph = fromimport('tinygrad.runtime.graph.remote', f"Remote{'Multi' if graph_multi else ''}Graph") if graph_supported else None + super().__init__(device, RemoteAllocator(self), renderer_instance, Compiler(), functools.partial(RemoteProgram, self), graph) def finalize(self): with contextlib.suppress(ConnectionError, http.client.HTTPException): self.q(SessionFree(), wait=True) diff --git a/tinygrad_repo/tinygrad/runtime/ops_webgpu.py b/tinygrad_repo/tinygrad/runtime/ops_webgpu.py index eef0a5cc3..1386c963c 100644 --- a/tinygrad_repo/tinygrad/runtime/ops_webgpu.py +++ b/tinygrad_repo/tinygrad/runtime/ops_webgpu.py @@ -1,7 +1,7 @@ import functools, struct from tinygrad.device import Compiled, Allocator, Compiler, BufferSpec from tinygrad.renderer.wgsl import WGSLRenderer -from tinygrad.helpers import round_up, suppress_finalizing +from tinygrad.helpers import round_up from tinygrad.runtime.autogen import webgpu from typing import List, Any, TypeAlias import ctypes @@ -188,8 +188,9 @@ class WebGpuAllocator(Allocator['WGPUDevPtr']): def _copyout(self, dest:memoryview, src:WGPUBufPtr): buffer_data = read_buffer(self.dev, src) dest[:] = buffer_data[:dest.nbytes] if webgpu.wgpuBufferGetSize(src) > dest.nbytes else buffer_data - @suppress_finalizing - def _free(self, opaque:WGPUBufPtr, options:BufferSpec): webgpu.wgpuBufferDestroy(opaque) + def _free(self, opaque:WGPUBufPtr, options:BufferSpec): + try: webgpu.wgpuBufferDestroy(opaque) + except AttributeError: pass class WebGpuDevice(Compiled): def __init__(self, device:str): diff --git a/tinygrad_repo/tinygrad/runtime/support/am/amdev.py b/tinygrad_repo/tinygrad/runtime/support/am/amdev.py index fa9ba7932..72ffca523 100644 --- a/tinygrad_repo/tinygrad/runtime/support/am/amdev.py +++ b/tinygrad_repo/tinygrad/runtime/support/am/amdev.py @@ -1,5 +1,5 @@ from __future__ import annotations -import ctypes, collections, dataclasses, functools, os, hashlib +import ctypes, collections, time, dataclasses, functools, os, hashlib from tinygrad.helpers import mv_address, getenv, DEBUG, fetch from tinygrad.runtime.autogen.am import am from tinygrad.runtime.support.hcq import MMIOInterface @@ -10,16 +10,16 @@ from tinygrad.runtime.support.am.ip import AM_SOC, AM_GMC, AM_IH, AM_PSP, AM_SMU AM_DEBUG = getenv("AM_DEBUG", 0) -@dataclasses.dataclass +@dataclasses.dataclass(frozen=True) class AMRegister(AMDReg): adev:AMDev - def read(self, inst=0): return self.adev.rreg(self.addr[inst]) - def read_bitfields(self, inst=0) -> dict[str, int]: return self.decode(self.read(inst=inst)) + def read(self): return self.adev.rreg(self.addr) + def read_bitfields(self) -> dict[str, int]: return self.decode(self.read()) - def write(self, _am_val:int=0, inst=0, **kwargs): self.adev.wreg(self.addr[inst], _am_val | self.encode(**kwargs)) + def write(self, _am_val:int=0, **kwargs): self.adev.wreg(self.addr, _am_val | self.encode(**kwargs)) - def update(self, inst=0, **kwargs): self.write(self.read(inst=inst) & ~self.fields_mask(*kwargs.keys()), inst=inst, **kwargs) + def update(self, **kwargs): self.write(self.read() & ~self.fields_mask(*kwargs.keys()), **kwargs) class AMFirmware: def __init__(self, adev): @@ -29,7 +29,7 @@ class AMFirmware: # Load SOS firmware self.sos_fw = {} - blob, sos_hdr = self.load_fw(f"psp_{fmt_ver(am.MP0_HWIP)}_sos.bin", versioned_header='struct_psp_firmware_header') + blob, sos_hdr = self.load_fw(f"psp_{fmt_ver(am.MP0_HWIP)}_sos.bin", am.struct_psp_firmware_header_v2_0) fw_bin = sos_hdr.psp_fw_bin for fw_i in range(sos_hdr.psp_fw_bin_count): @@ -45,11 +45,11 @@ class AMFirmware: self.smu_psp_desc = self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.header.ucode_size_bytes, am.GFX_FW_TYPE_SMU) # SDMA firmware - blob, hdr = self.load_fw(f"sdma_{fmt_ver(am.SDMA0_HWIP)}.bin", versioned_header='struct_sdma_firmware_header') + blob, hdr, hdr_v3 = self.load_fw(f"sdma_{fmt_ver(am.SDMA0_HWIP)}.bin", am.struct_sdma_firmware_header_v2_0, am.struct_sdma_firmware_header_v3_0) if hdr.header.header_version_major < 3: self.descs += [self.desc(blob, hdr.ctl_ucode_offset, hdr.ctl_ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH1)] self.descs += [self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.ctx_ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH0)] - else: self.descs += [self.desc(blob, hdr.header.ucode_array_offset_bytes, hdr.ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH0)] + else: self.descs += [self.desc(blob, hdr_v3.header.ucode_array_offset_bytes, hdr_v3.ucode_size_bytes, am.GFX_FW_TYPE_SDMA_UCODE_TH0)] # PFP, ME, MEC firmware for (fw_name, fw_cnt) in ([('PFP', 1), ('ME', 1)] if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) else []) + [('MEC', 1)]: @@ -83,13 +83,10 @@ class AMFirmware: self.descs += [self.desc(blob, hdr0.header.ucode_array_offset_bytes, hdr0.header.ucode_size_bytes, am.GFX_FW_TYPE_RLC_G)] - def load_fw(self, fname:str, *headers, versioned_header:str|None=None): + def load_fw(self, fname:str, *headers): fpath = fetch(f"https://gitlab.com/kernel-firmware/linux-firmware/-/raw/45f59212aebd226c7630aff4b58598967c0c8c91/amdgpu/{fname}", subdir="fw") blob = memoryview(bytearray(fpath.read_bytes())) if AM_DEBUG >= 1: print(f"am {self.adev.devfmt}: loading firmware {fname}: {hashlib.sha256(blob).hexdigest()}") - if versioned_header: - chdr = am.struct_common_firmware_header.from_address(mv_address(blob)) - headers += (getattr(am, versioned_header + f"_v{chdr.header_version_major}_{chdr.header_version_minor}"),) return tuple([blob] + [hdr.from_address(mv_address(blob)) for hdr in headers]) def desc(self, blob:memoryview, offset:int, size:int, *types:int) -> tuple[list[int], memoryview]: return (list(types), blob[offset:offset+size]) @@ -104,8 +101,7 @@ class AMPageTableEntry: def entry(self, entry_id:int) -> int: return self.entries[entry_id] def valid(self, entry_id:int) -> bool: return (self.entries[entry_id] & am.AMDGPU_PTE_VALID) != 0 def address(self, entry_id:int) -> int: return self.entries[entry_id] & 0x0000FFFFFFFFF000 - def is_page(self, entry_id:int) -> bool: return self.lv == am.AMDGPU_VM_PTB or self.adev.gmc.is_pte_huge_page(self.entries[entry_id]) - def supports_huge_page(self, paddr:int): return self.lv >= am.AMDGPU_VM_PDB2 + def is_pte(self, entry_id:int) -> bool: return self.lv == am.AMDGPU_VM_PTB or self.adev.gmc.is_pte_huge_page(self.entries[entry_id]) class AMMemoryManager(MemoryManager): va_allocator = TLSFAllocator(512 * (1 << 30), base=0x200000000000) # global for all devices. @@ -116,8 +112,6 @@ class AMMemoryManager(MemoryManager): self.dev.gmc.flush_tlb(ip='MM', vmid=0) class AMDev(PCIDevImplBase): - Version = 0xA0000006 - def __init__(self, devfmt, vram:MMIOInterface, doorbell:MMIOInterface, mmio:MMIOInterface, dma_regions:list[tuple[int, MMIOInterface]]|None=None): self.devfmt, self.vram, self.doorbell64, self.mmio, self.dma_regions = devfmt, vram, doorbell, mmio, dma_regions self.lock_fd = System.flock_acquire(f"am_{self.devfmt}.lock") @@ -134,10 +128,27 @@ class AMDev(PCIDevImplBase): # To enable this, AM uses a separate boot memory that is guaranteed not to be overwritten. This physical memory is utilized for # all blocks that are initialized only during the initial AM boot. # To determine if the GPU is in the third state, AM uses regSCRATCH_REG7 as a flag. - self.is_booting = True - self.init_sw(smi_dev=False) + self.is_booting, self.smi_dev = True, False # During boot only boot memory can be allocated. This flag is to validate this. + self.partial_boot = (self.reg("regSCRATCH_REG7").read() == (am_version:=0xA0000005)) and (getenv("AM_RESET", 0) != 1) + + # Memory manager & firmware + self.mm = AMMemoryManager(self, self.vram_size, boot_size=(32 << 20), pt_t=AMPageTableEntry, pte_cnt=[512, 512, 512, 512], + pte_covers=[(1 << ((9 * (3-lv)) + 12)) for lv in range(4)], first_lv=am.AMDGPU_VM_PDB1, first_page_lv=am.AMDGPU_VM_PDB2, + va_base=AMMemoryManager.va_allocator.base) + self.fw = AMFirmware(self) + + # Initialize IP blocks + self.soc:AM_SOC = AM_SOC(self) + self.gmc:AM_GMC = AM_GMC(self) + self.ih:AM_IH = AM_IH(self) + self.psp:AM_PSP = AM_PSP(self) + self.smu:AM_SMU = AM_SMU(self) + self.gfx:AM_GFX = AM_GFX(self) + self.sdma:AM_SDMA = AM_SDMA(self) + + # Init sw for all IP blocks + for ip in [self.soc, self.gmc, self.ih, self.psp, self.smu, self.gfx, self.sdma]: ip.init_sw() - self.partial_boot = (self.reg("regSCRATCH_REG7").read() == AMDev.Version) and (getenv("AM_RESET", 0) != 1) if self.partial_boot and (self.reg("regGCVM_CONTEXT0_CNTL").read() != 0 or self.reg(self.gmc.pf_status_reg("GC")).read() != 0): if DEBUG >= 2: print(f"am {self.devfmt}: Malformed state. Issuing a full reset.") self.partial_boot = False @@ -159,30 +170,9 @@ class AMDev(PCIDevImplBase): self.smu.set_clocks(level=-1) # last level, max perf. for ip in [self.soc, self.gfx]: ip.set_clockgating_state() - self.reg("regSCRATCH_REG7").write(AMDev.Version) + self.reg("regSCRATCH_REG7").write(am_version) if DEBUG >= 2: print(f"am {self.devfmt}: boot done") - def init_sw(self, smi_dev=False): - self.smi_dev = smi_dev # During boot only boot memory can be allocated. This flag is to validate this. - - # Memory manager & firmware - self.mm = AMMemoryManager(self, self.vram_size, boot_size=(32 << 20), pt_t=AMPageTableEntry, va_shifts=[12, 21, 30, 39], va_bits=48, - first_lv=am.AMDGPU_VM_PDB2, va_base=AMMemoryManager.va_allocator.base, - palloc_ranges=[(1 << (i + 12), 0x1000) for i in range(9 * (3 - am.AMDGPU_VM_PDB2), -1, -1)]) - self.fw = AMFirmware(self) - - # Initialize IP blocks - self.soc:AM_SOC = AM_SOC(self) - self.gmc:AM_GMC = AM_GMC(self) - self.ih:AM_IH = AM_IH(self) - self.psp:AM_PSP = AM_PSP(self) - self.smu:AM_SMU = AM_SMU(self) - self.gfx:AM_GFX = AM_GFX(self) - self.sdma:AM_SDMA = AM_SDMA(self) - - # Init sw for all IP blocks - for ip in [self.soc, self.gmc, self.ih, self.psp, self.smu, self.gfx, self.sdma]: ip.init_sw() - def fini(self): if DEBUG >= 2: print(f"am {self.devfmt}: Finalizing") for ip in [self.sdma, self.gfx]: ip.fini_hw() @@ -217,6 +207,12 @@ class AMDev(PCIDevImplBase): self.reg("regBIF_BX_PF0_RSMU_INDEX").write(reg) self.reg("regBIF_BX_PF0_RSMU_DATA").write(val) + def wait_reg(self, reg:AMRegister, value:int, mask=0xffffffff, timeout=10000) -> int: + start_time = int(time.perf_counter() * 1000) + while int(time.perf_counter() * 1000) - start_time < timeout: + if ((rval:=reg.read()) & mask) == value: return rval + raise RuntimeError(f'wait_reg timeout reg=0x{reg.addr:X} mask=0x{mask:X} value=0x{value:X} last_val=0x{rval}') + def _run_discovery(self): # NOTE: Fixed register to query memory size without known ip bases to find the discovery table. # The table is located at the end of VRAM - 64KB and is 10KB in size. @@ -226,7 +222,7 @@ class AMDev(PCIDevImplBase): self.bhdr = am.struct_binary_header.from_buffer(bytearray(self.vram.view(tmr_offset, tmr_size)[:])) ihdr = am.struct_ip_discovery_header.from_address(ctypes.addressof(self.bhdr) + self.bhdr.table_list[am.IP_DISCOVERY].offset) - assert self.bhdr.binary_signature == am.BINARY_SIGNATURE and ihdr.signature == am.DISCOVERY_TABLE_SIGNATURE, "discovery signatures mismatch" + assert ihdr.signature == am.DISCOVERY_TABLE_SIGNATURE and not ihdr.base_addr_64_bit, f"0x{ihdr.signature:X} != 0x{am.DISCOVERY_TABLE_SIGNATURE:X}" # Mapping of HW IP to Discovery HW IP hw_id_map = {am.__dict__[x]: int(y) for x,y in am.hw_id_map} @@ -239,7 +235,7 @@ class AMDev(PCIDevImplBase): ip_offset = ctypes.addressof(self.bhdr) + ctypes.sizeof(dhdr) + ihdr.die_info[num_die].die_offset for _ in range(dhdr.num_ips): ip = am.struct_ip_v4.from_address(ip_offset) - ba = ((ctypes.c_uint64 if ihdr.base_addr_64_bit else ctypes.c_uint32) * ip.num_base_address).from_address(ip_offset + 8) + ba = (ctypes.c_uint32 * ip.num_base_address).from_address(ip_offset + 8) for hw_ip in range(1, am.MAX_HWIP): if hw_ip in hw_id_map and hw_id_map[hw_ip] == ip.hw_id: self.regs_offset[hw_ip][ip.instance_number] = tuple(list(ba)) @@ -257,5 +253,6 @@ class AMDev(PCIDevImplBase): ("nbio" if self.ip_ver[am.GC_HWIP] < (12,0,0) else "nbif", am.NBIO_HWIP)] for prefix, hwip in mods: - self.__dict__.update(import_asic_regs(prefix, self.ip_ver[hwip], cls=functools.partial(AMRegister, adev=self, bases=self.regs_offset[hwip]))) - self.__dict__.update(import_asic_regs('mp', (11, 0), cls=functools.partial(AMRegister, adev=self, bases=self.regs_offset[am.MP1_HWIP]))) + self.__dict__.update(import_asic_regs(prefix, self.ip_ver[hwip], cls=functools.partial(AMRegister, adev=self, bases=self.regs_offset[hwip][0]))) + self.__dict__.update(import_asic_regs('mp', (11, 0), cls=functools.partial(AMRegister, adev=self, bases=self.regs_offset[am.MP1_HWIP][0]))) + diff --git a/tinygrad_repo/tinygrad/runtime/support/am/ip.py b/tinygrad_repo/tinygrad/runtime/support/am/ip.py index e6ff7a24e..d4e1c4637 100644 --- a/tinygrad_repo/tinygrad/runtime/support/am/ip.py +++ b/tinygrad_repo/tinygrad/runtime/support/am/ip.py @@ -1,8 +1,7 @@ -import ctypes, time, contextlib, functools +import ctypes, time, contextlib, importlib, functools from typing import Literal -from tinygrad.helpers import to_mv, data64, lo32, hi32, DEBUG, wait_cond from tinygrad.runtime.autogen.am import am -from tinygrad.runtime.support.amd import import_soc +from tinygrad.helpers import to_mv, data64, lo32, hi32, DEBUG class AM_IP: def __init__(self, adev): self.adev = adev @@ -12,7 +11,9 @@ class AM_IP: def set_clockgating_state(self): pass # Set clockgating state for this IP class AM_SOC(AM_IP): - def init_sw(self): self.module = import_soc(self.adev.ip_ver[am.GC_HWIP]) + def init_sw(self): + self.soc_ver = 24 if self.adev.ip_ver[am.GC_HWIP] >= (12,0,0) else 21 + self.module = importlib.import_module(f"tinygrad.runtime.autogen.am.soc{self.soc_ver}") def init_hw(self): self.adev.regRCC_DEV0_EPF2_STRAP2.update(strap_no_soft_reset_dev0_f2=0x0) @@ -32,7 +33,7 @@ class AM_GMC(AM_IP): # VM aperture self.vm_base = self.adev.mm.va_allocator.base - self.vm_end = min(self.vm_base + (1 << self.adev.mm.va_bits) - 1, 0x7fffffffffff) + self.vm_end = self.vm_base + self.adev.mm.va_allocator.size - 1 # GFX11/GFX12 has 44-bit address space self.address_space_mask = (1 << 44) - 1 @@ -52,12 +53,12 @@ class AM_GMC(AM_IP): # Can't issue TLB invalidation if the hub isn't initialized. if not self.hub_initted[ip]: return - if ip == "MM": wait_cond(lambda: self.adev.regMMVM_INVALIDATE_ENG17_SEM.read() & 0x1, value=1, msg="mm flush_tlb timeout") + if ip == "MM": self.adev.wait_reg(self.adev.regMMVM_INVALIDATE_ENG17_SEM, mask=0x1, value=0x1) self.adev.reg(f"reg{ip}VM_INVALIDATE_ENG17_REQ").write(flush_type=flush_type, per_vmid_invalidate_req=(1 << vmid), invalidate_l2_ptes=1, invalidate_l2_pde0=1, invalidate_l2_pde1=1, invalidate_l2_pde2=1, invalidate_l1_ptes=1, clear_protection_fault_status_addr=0) - wait_cond(lambda: self.adev.reg(f"reg{ip}VM_INVALIDATE_ENG17_ACK").read() & (1 << vmid), value=(1 << vmid), msg="flush_tlb timeout") + self.adev.wait_reg(self.adev.reg(f"reg{ip}VM_INVALIDATE_ENG17_ACK"), mask=(1 << vmid), value=(1 << vmid)) if ip == "MM": self.adev.regMMVM_INVALIDATE_ENG17_SEM.write(0x0) @@ -168,15 +169,14 @@ class AM_SMU(AM_IP): self._send_msg(self.smu_mod.PPSMC_MSG_SetSoftMinByFreq, clck << 16 | (vals[level])) self._send_msg(self.smu_mod.PPSMC_MSG_SetSoftMaxByFreq, clck << 16 | (vals[level])) - def _smu_cmn_send_msg(self, msg:int, param=0, debug=False): + def _smu_cmn_send_msg(self, msg, param=0, debug=False): (self.adev.mmMP1_SMN_C2PMSG_90 if not debug else self.adev.mmMP1_SMN_C2PMSG_54).write(0) # resp reg (self.adev.mmMP1_SMN_C2PMSG_82 if not debug else self.adev.mmMP1_SMN_C2PMSG_53).write(param) (self.adev.mmMP1_SMN_C2PMSG_66 if not debug else self.adev.mmMP1_SMN_C2PMSG_75).write(msg) - def _send_msg(self, msg:int, param:int, read_back_arg=False, timeout=10000, debug=False): # default timeout is 10 seconds + def _send_msg(self, msg, param, read_back_arg=False, timeout=10000, debug=False): # 10s self._smu_cmn_send_msg(msg, param, debug=debug) - wait_cond(lambda: (self.adev.mmMP1_SMN_C2PMSG_90 if not debug else self.adev.mmMP1_SMN_C2PMSG_54).read(), value=1, timeout_ms=timeout, - msg=f"SMU msg {msg:#x} timeout") + self.adev.wait_reg(self.adev.mmMP1_SMN_C2PMSG_90 if not debug else self.adev.mmMP1_SMN_C2PMSG_54, mask=0xFFFFFFFF, value=1, timeout=timeout) return (self.adev.mmMP1_SMN_C2PMSG_82 if not debug else self.adev.mmMP1_SMN_C2PMSG_53).read() if read_back_arg else None class AM_GFX(AM_IP): @@ -224,8 +224,7 @@ class AM_GFX(AM_IP): self._grbm_select() self.adev.regGCVM_CONTEXT0_CNTL.write(0) - def setup_ring(self, ring_addr:int, ring_size:int, rptr_addr:int, wptr_addr:int, eop_addr:int, eop_size:int, doorbell:int, pipe:int, queue:int, - aql:bool): + def setup_ring(self, ring_addr:int, ring_size:int, rptr_addr:int, wptr_addr:int, eop_addr:int, eop_size:int, doorbell:int, pipe:int, queue:int): mqd = self.adev.mm.valloc(0x1000, uncached=True, contiguous=True) struct_t = getattr(am, f"struct_v{self.adev.ip_ver[am.GC_HWIP][0]}_compute_mqd") @@ -236,10 +235,9 @@ class AM_GFX(AM_IP): cp_hqd_pq_rptr_report_addr_lo=lo32(rptr_addr), cp_hqd_pq_rptr_report_addr_hi=hi32(rptr_addr), cp_hqd_pq_wptr_poll_addr_lo=lo32(wptr_addr), cp_hqd_pq_wptr_poll_addr_hi=hi32(wptr_addr), cp_hqd_pq_doorbell_control=self.adev.regCP_HQD_PQ_DOORBELL_CONTROL.encode(doorbell_offset=doorbell*2, doorbell_en=1), - cp_hqd_pq_control=self.adev.regCP_HQD_PQ_CONTROL.encode(rptr_block_size=5, unord_dispatch=0, queue_size=(ring_size//4).bit_length()-2, - **({'queue_full_en':1, 'slot_based_wptr':2, 'no_update_rptr':1} if aql else {})), + cp_hqd_pq_control=self.adev.regCP_HQD_PQ_CONTROL.encode(rptr_block_size=5, unord_dispatch=0, queue_size=(ring_size//4).bit_length()-2), cp_hqd_ib_control=self.adev.regCP_HQD_IB_CONTROL.encode(min_ib_avail_size=0x3), cp_hqd_hq_status0=0x20004000, - cp_mqd_control=self.adev.regCP_MQD_CONTROL.encode(priv_state=1), cp_hqd_vmid=0, cp_hqd_aql_control=int(aql), + cp_mqd_control=self.adev.regCP_MQD_CONTROL.encode(priv_state=1), cp_hqd_vmid=0, cp_hqd_eop_base_addr_lo=lo32(eop_addr>>8), cp_hqd_eop_base_addr_hi=hi32(eop_addr>>8), cp_hqd_eop_control=self.adev.regCP_HQD_EOP_CONTROL.encode(eop_size=(eop_size//4).bit_length()-2)) @@ -250,7 +248,7 @@ class AM_GFX(AM_IP): self._grbm_select(me=1, pipe=pipe, queue=queue) mqd_st_mv = to_mv(ctypes.addressof(mqd_struct), ctypes.sizeof(mqd_struct)).cast('I') - for i, reg in enumerate(range(self.adev.regCP_MQD_BASE_ADDR.addr[0], self.adev.regCP_HQD_PQ_WPTR_HI.addr[0] + 1)): + for i, reg in enumerate(range(self.adev.regCP_MQD_BASE_ADDR.addr, self.adev.regCP_HQD_PQ_WPTR_HI.addr + 1)): self.adev.wreg(reg, mqd_st_mv[0x80 + i]) self.adev.regCP_HQD_ACTIVE.write(0x1) @@ -262,7 +260,7 @@ class AM_GFX(AM_IP): if hasattr(self.adev, 'regMM_ATC_L2_MISC_CG'): self.adev.regMM_ATC_L2_MISC_CG.write(enable=1, mem_ls_enable=1) self.adev.regRLC_SAFE_MODE.write(message=1, cmd=1) - wait_cond(lambda: self.adev.regRLC_SAFE_MODE.read() & 0x1, value=0, msg="RLC safe mode timeout") + self.adev.wait_reg(self.adev.regRLC_SAFE_MODE, mask=0x1, value=0x0) self.adev.regRLC_CGCG_CGLS_CTRL.update(cgcg_gfx_idle_threshold=0x36, cgcg_en=1, cgls_rep_compansat_delay=0xf, cgls_en=1) @@ -413,14 +411,14 @@ class AM_PSP(AM_IP): def is_sos_alive(self): return self.adev.reg(f"{self.reg_pref}_81").read() != 0x0 - def _wait_for_bootloader(self): wait_cond(lambda: self.adev.reg(f"{self.reg_pref}_35").read() & 0x80000000, value=0x80000000, msg="BL not ready") + def _wait_for_bootloader(self): self.adev.wait_reg(self.adev.reg(f"{self.reg_pref}_35"), mask=0x80000000, value=0x80000000) - def _prep_msg1(self, data:memoryview): + def _prep_msg1(self, data): assert len(data) <= self.msg1_view.nbytes, f"msg1 buffer is too small {len(data):#x} > {self.msg1_view.nbytes:#x}" self.msg1_view[:len(data)+4] = bytes(data) + b'\x00' * 4 self.adev.gmc.flush_hdp() - def _bootloader_load_component(self, fw:int, compid:int): + def _bootloader_load_component(self, fw, compid): if fw not in self.adev.fw.sos_fw: return 0 self._wait_for_bootloader() @@ -448,7 +446,7 @@ class AM_PSP(AM_IP): time.sleep(0.02) # Wait until the sOS is ready - wait_cond(lambda: self.adev.reg(f"{self.reg_pref}_64").read() & 0x80000000, value=0x80000000, msg="sOS not ready") + self.adev.wait_reg(self.adev.reg(f"{self.reg_pref}_64"), mask=0x80000000, value=0x80000000) self.adev.wreg_pair(self.reg_pref, "_69", "_70", self.adev.paddr2mc(self.ring_paddr)) self.adev.reg(f"{self.reg_pref}_71").write(self.ring_size) @@ -457,10 +455,10 @@ class AM_PSP(AM_IP): # There might be handshake issue with hardware which needs delay time.sleep(0.02) - wait_cond(lambda: self.adev.reg(f"{self.reg_pref}_64").read() & 0x8000FFFF, value=0x80000000, msg="sOS ring not created") + self.adev.wait_reg(self.adev.reg(f"{self.reg_pref}_64"), mask=0x8000FFFF, value=0x80000000) - def _ring_submit(self, cmd:am.struct_psp_gfx_cmd_resp) -> am.struct_psp_gfx_cmd_resp: - msg = am.struct_psp_gfx_rb_frame(fence_value=(prev_wptr:=self.adev.reg(f"{self.reg_pref}_67").read()) + 1, + def _ring_submit(self, cmd): + msg = am.struct_psp_gfx_rb_frame(fence_value=(prev_wptr:=self.adev.reg(f"{self.reg_pref}_67").read()), cmd_buf_addr_lo=lo32(self.adev.paddr2mc(self.cmd_paddr)), cmd_buf_addr_hi=hi32(self.adev.paddr2mc(self.cmd_paddr)), fence_addr_lo=lo32(self.adev.paddr2mc(self.fence_paddr)), fence_addr_hi=hi32(self.adev.paddr2mc(self.fence_paddr))) @@ -470,14 +468,15 @@ class AM_PSP(AM_IP): # Move the wptr self.adev.reg(f"{self.reg_pref}_67").write(prev_wptr + ctypes.sizeof(am.struct_psp_gfx_rb_frame) // 4) - wait_cond(lambda: self.adev.vram.view(self.fence_paddr, 4, 'I')[0], value=msg.fence_value, msg="sOS ring not responding") + while self.adev.vram.view(self.fence_paddr, 4, 'I')[0] != prev_wptr: pass + time.sleep(0.005) resp = type(cmd).from_buffer(bytearray(self.adev.vram.view(self.cmd_paddr, ctypes.sizeof(cmd))[:])) if resp.resp.status != 0: raise RuntimeError(f"PSP command failed {resp.cmd_id} {resp.resp.status}") return resp - def _load_ip_fw_cmd(self, fw_types:list[int], fw_bytes:memoryview): + def _load_ip_fw_cmd(self, fw_types, fw_bytes): self._prep_msg1(fw_bytes) for fw_type in fw_types: if DEBUG >= 2: print(f"am {self.adev.devfmt}: loading fw: {am.psp_gfx_fw_type__enumvalues[fw_type]}") @@ -487,7 +486,7 @@ class AM_PSP(AM_IP): cmd.cmd.cmd_load_ip_fw.fw_type = fw_type self._ring_submit(cmd) - def _tmr_load_cmd(self) -> am.struct_psp_gfx_cmd_resp: + def _tmr_load_cmd(self): cmd = am.struct_psp_gfx_cmd_resp(cmd_id=am.GFX_CMD_ID_SETUP_TMR) cmd.cmd.cmd_setup_tmr.buf_phy_addr_hi, cmd.cmd.cmd_setup_tmr.buf_phy_addr_lo = data64(self.adev.paddr2mc(self.tmr_paddr)) cmd.cmd.cmd_setup_tmr.system_phy_addr_hi, cmd.cmd.cmd_setup_tmr.system_phy_addr_lo = data64(self.tmr_paddr) @@ -495,7 +494,7 @@ class AM_PSP(AM_IP): cmd.cmd.cmd_setup_tmr.buf_size = self.tmr_size return self._ring_submit(cmd) - def _load_toc_cmd(self, toc_size:int) -> am.struct_psp_gfx_cmd_resp: + def _load_toc_cmd(self, toc_size): cmd = am.struct_psp_gfx_cmd_resp(cmd_id=am.GFX_CMD_ID_LOAD_TOC) cmd.cmd.cmd_load_toc.toc_phy_addr_hi, cmd.cmd.cmd_load_toc.toc_phy_addr_lo = data64(self.msg1_addr) cmd.cmd.cmd_load_toc.toc_size = toc_size diff --git a/tinygrad_repo/tinygrad/runtime/support/amd.py b/tinygrad_repo/tinygrad/runtime/support/amd.py index bc87ddae8..b29e618b1 100644 --- a/tinygrad_repo/tinygrad/runtime/support/amd.py +++ b/tinygrad_repo/tinygrad/runtime/support/amd.py @@ -5,10 +5,9 @@ from tinygrad.helpers import getbits, round_up, fetch from tinygrad.runtime.autogen import pci from tinygrad.runtime.support.usb import ASM24Controller -@dataclass +@dataclass(frozen=True) class AMDReg: - name:str; offset:int; segment:int; fields:dict[str, tuple[int, int]]; bases:dict[int, tuple[int, ...]] # noqa: E702 - def __post_init__(self): self.addr:dict[int, int] = { inst: bases[self.segment] + self.offset for inst, bases in self.bases.items() } + name:str; offset:int; segment:int; fields:dict[str, tuple[int, int]]; bases:tuple[int, ...] # noqa: E702 def encode(self, **kwargs) -> int: return functools.reduce(int.__or__, (value << self.fields[name][0] for name,value in kwargs.items()), 0) def decode(self, val: int) -> dict: return {name:getbits(val, start, end) for name,(start,end) in self.fields.items()} @@ -16,9 +15,12 @@ class AMDReg: def fields_mask(self, *names) -> int: return functools.reduce(int.__or__, ((((1 << (self.fields[nm][1]-self.fields[nm][0]+1)) - 1) << self.fields[nm][0]) for nm in names), 0) + @property + def addr(self): return self.bases[self.segment] + self.offset + @dataclass class AMDIP: - name:str; version:tuple[int, ...]; bases:dict[int, tuple[int, ...]] # noqa: E702 + name:str; version:tuple[int, ...]; bases:tuple[int, ...] # noqa: E702 def __post_init__(self): self.version = fixup_ip_version(self.name, self.version)[0] @functools.cached_property @@ -39,26 +41,15 @@ def fixup_ip_version(ip:str, version:tuple[int, ...]) -> list[tuple[int, ...]]: if ip in ['nbio', 'nbif']: version = _apply_ovrd({(3,3): (2,3,0)}) elif ip in ['mp', 'smu']: version = _apply_ovrd({(14,0,3): (14,0,2)}) - elif ip in ['gc']: version = _apply_ovrd({(9,5,0): (9,4,3)}) return [version, version[:2], version[:2]+(0,), version[:1]+(0, 0)] -def header_download(file, name=None, subdir="defines") -> str: - url = "https://gitlab.com/linux-kernel/linux-next/-/raw/cf6d949a409e09539477d32dbe7c954e4852e744/drivers/gpu/drm/amd" - return fetch(f"{url}/{file}", name=name, subdir=subdir).read_text() - -def import_header(path:str): - t = re.sub(r'//.*|/\*.*?\*/','', header_download(path, subdir="defines"), flags=re.S) - return {k:int(v,0) for k,v in re.findall(r'\b([A-Za-z_]\w*)\s*=\s*(0x[0-9A-Fa-f]+|\d+)', t)} - def import_module(name:str, version:tuple[int, ...], version_prefix:str=""): for ver in fixup_ip_version(name, version): try: return importlib.import_module(f"tinygrad.runtime.autogen.am.{name}_{version_prefix}{'_'.join(map(str, ver))}") except ImportError: pass raise ImportError(f"Failed to load autogen module for {name.upper()} {'.'.join(map(str, version))}") -def import_soc(ip): return type("SOC", (object,), import_header(f"include/{({9: 'vega10', 10: 'navi10', 11: 'soc21', 12: 'soc24'}[ip[0]])}_enum.h")) - def import_asic_regs(prefix:str, version:tuple[int, ...], cls=AMDReg) -> dict[str, AMDReg]: def _split_name(name): return name[:(pos:=next((i for i,c in enumerate(name) if c.isupper()), len(name)))], name[pos:] def _extract_regs(txt): @@ -66,7 +57,8 @@ def import_asic_regs(prefix:str, version:tuple[int, ...], cls=AMDReg) -> dict[st def _download_file(ver, suff) -> str: dir_prefix = {"osssys": "oss"}.get(prefix, prefix) fetch_name, file_name = f"{prefix}_{'_'.join(map(str, ver))}_{suff}.h", f"{prefix}_{'_'.join(map(str, version))}_{suff}.h" - return header_download(f"include/asic_reg/{dir_prefix}/{fetch_name}", name=file_name, subdir="asic_regs") + url = "https://gitlab.com/linux-kernel/linux-next/-/raw/cf6d949a409e09539477d32dbe7c954e4852e744/drivers/gpu/drm/amd/include/asic_reg" + return fetch(f"{url}/{dir_prefix}/{fetch_name}", name=file_name, subdir="asic_regs").read_text() for ver in fixup_ip_version(prefix, version): try: offs, sh_masks = _extract_regs(_download_file(ver, "offset")), _extract_regs(_download_file(ver, "sh_mask")) diff --git a/tinygrad_repo/tinygrad/runtime/support/hcq.py b/tinygrad_repo/tinygrad/runtime/support/hcq.py index 47962a960..8dcf1548b 100644 --- a/tinygrad_repo/tinygrad/runtime/support/hcq.py +++ b/tinygrad_repo/tinygrad/runtime/support/hcq.py @@ -1,11 +1,9 @@ from __future__ import annotations -from typing import cast, Callable, Type, TypeVar, Generic, Any -import contextlib, decimal, statistics, time, ctypes, array, os, struct, traceback, collections -try: import fcntl # windows misses that -except ImportError: fcntl = None #type:ignore[assignment] -from tinygrad.helpers import PROFILE, getenv, to_mv, round_up, ProfileRangeEvent +from typing import cast, Callable, Type, TypeVar, Generic, Any, ClassVar +import contextlib, decimal, statistics, time, ctypes, array, os, fcntl, struct +from tinygrad.helpers import PROFILE, getenv, to_mv, round_up from tinygrad.renderer import Renderer -from tinygrad.device import BufferSpec, Compiler, Compiled, LRUAllocator, ProfileDeviceEvent, ProfileProgramEvent +from tinygrad.device import BufferSpec, Compiler, Compiled, LRUAllocator, ProfileRangeEvent, ProfileDeviceEvent, ProfileProgramEvent from tinygrad.uop.ops import sym_infer, sint, Variable, UOp from tinygrad.runtime.autogen import libc @@ -219,17 +217,19 @@ class HWQueue(Generic[SignalType, HCQDeviceType, ProgramType, ArgsStateType]): def _submit(self, dev:HCQDeviceType): raise NotImplementedError("need _submit") class HCQSignal(Generic[HCQDeviceType]): - def __init__(self, base_buf:HCQBuffer, value:int=0, owner:HCQDeviceType|None=None, is_timeline:bool=False, timestamp_divider=1000): - self.base_buf, self.value_addr, self.timestamp_addr, self.owner = base_buf, base_buf.va_addr+0, base_buf.va_addr+8, owner - self.is_timeline = is_timeline + def __init__(self, base_buf:HCQBuffer|None=None, value:int=0, dev_t:Type[HCQDeviceType]|None=None, timeline_for_device:HCQDeviceType|None=None, + timestamp_divider=1, value_off=0, timestamp_off=8): + self.base_buf = cast(HCQBuffer, dev_t._alloc_signal() if dev_t is not None and base_buf is None else base_buf) + self.value_addr, self.timestamp_addr, self.dev_t = self.base_buf.va_addr+value_off, self.base_buf.va_addr+timestamp_off, dev_t self.timestamp_divider:decimal.Decimal = decimal.Decimal(timestamp_divider) + self.timeline_for_device:HCQDeviceType|None = timeline_for_device if isinstance(self.base_buf.va_addr, int): - self.value_mv, self.timestamp_mv = self.base_buf.cpu_view().view(0, 8, 'Q'), self.base_buf.cpu_view().view(8, 8, 'Q') + self.value_mv, self.timestamp_mv = self.base_buf.cpu_view().view(value_off, 8, 'Q'), self.base_buf.cpu_view().view(timestamp_off, 8, 'Q') self.value_mv[0] = value def __del__(self): - if isinstance(self.base_buf.va_addr, int) and self.owner is not None: HCQCompiled.signal_pool[self.owner.peer_group].append(self.base_buf) + if isinstance(self.base_buf.va_addr, int) and self.dev_t is not None: self.dev_t.signal_pool.append(self.base_buf) @property def value(self) -> int: return self.value_mv[0] @@ -270,7 +270,7 @@ class HCQSignal(Generic[HCQDeviceType]): @contextlib.contextmanager def hcq_profile(dev:HCQCompiled, enabled, desc, queue_type:Callable[[], HWQueue]|None=None, queue:HWQueue|None=None): - st, en = (dev.new_signal(), dev.new_signal()) if enabled else (None, None) + st, en = (dev.signal_t(), dev.signal_t()) if enabled else (None, None) if enabled and queue is not None: queue.timestamp(st) elif enabled: @@ -288,7 +288,7 @@ def hcq_profile(dev:HCQCompiled, enabled, desc, queue_type:Callable[[], HWQueue] class HCQArgsState(Generic[ProgramType]): def __init__(self, buf:HCQBuffer, prg:ProgramType, bufs:tuple[HCQBuffer, ...], vals:tuple[sint, ...]=()): - self.buf, self.prg, self.bufs, self.vals = buf, prg, bufs, vals + self.buf, self.prg = buf, prg self.bind_data:list[tuple[tuple[sint, ...], MMIOInterface, str]] = [] def bind_sints_to_buf(self, *vals:sint, buf:HCQBuffer, fmt, offset=0): self.bind_data.append((vals, buf.cpu_view().view(offset=offset), fmt)) @@ -320,8 +320,7 @@ class HCQProgram(Generic[HCQDeviceType]): Returns: Arguments state with the given buffers and values set for the program. """ - argsbuf = kernargs or self.dev.kernargs_buf.offset(offset=self.dev.kernargs_offset_allocator.alloc(self.kernargs_alloc_size), - size=self.kernargs_alloc_size) + argsbuf = kernargs or self.dev.kernargs_buf.offset(offset=self.dev.kernargs_offset_allocator.alloc(self.kernargs_alloc_size)) return self.args_state_t(argsbuf, self, bufs, vals=vals) def __call__(self, *bufs:HCQBuffer, global_size:tuple[int,int,int]=(1,1,1), local_size:tuple[int,int,int]=(1,1,1), @@ -355,48 +354,34 @@ class HCQCompiled(Compiled, Generic[SignalType]): """ A base class for devices compatible with the HCQ (Hardware Command Queue) API. """ - peer_groups: dict[str, list[HCQCompiled]] = collections.defaultdict(list) - signal_pages: dict[str, list[HCQBuffer]] = collections.defaultdict(list) # per peer group - signal_pool: dict[str, list[HCQBuffer]] = collections.defaultdict(list) # per peer group - cpu_devices: list[HCQCompiled] = [] + devices: ClassVar[list[HCQCompiled]] = [] + signal_pages: ClassVar[list[HCQBuffer]] = [] + signal_pool: ClassVar[list[HCQBuffer]] = [] def __init__(self, device:str, allocator:HCQAllocatorBase, renderer:Renderer, compiler:Compiler, runtime, signal_t:Type[SignalType], - comp_queue_t:Callable[[], HWQueue], copy_queue_t:Callable[[], HWQueue]|None=None, kernargs_size=(16 << 20), sigalloc_size=0x1000): + comp_queue_t:Callable[[], HWQueue], copy_queue_t:Callable[[], HWQueue]|None, kernargs_size=(16 << 20), sigalloc_size=0x1000): self.device_id:int = int(device.split(":")[1]) if ":" in device else 0 from tinygrad.runtime.graph.hcq import HCQGraph super().__init__(device, allocator, renderer, compiler, runtime, HCQGraph) - # TODO: peer logic is determined based on device name. - self.peer_group = device.split(":")[0] - HCQCompiled.peer_groups[self.peer_group].append(self) - # Map signals if any - for sig_page in HCQCompiled.signal_pages[self.peer_group]: cast(HCQAllocator, self.allocator).map(sig_page) + for sig_page in self.signal_pages: cast(HCQAllocator, self.allocator).map(sig_page) + self.devices.append(self) self.sigalloc_size = sigalloc_size self.signal_t, self.hw_compute_queue_t, self.hw_copy_queue_t = signal_t, comp_queue_t, copy_queue_t self.timeline_value:int = 1 - self.timeline_signal, self._shadow_timeline_signal = self.new_signal(value=0, is_timeline=True), self.new_signal(value=0, is_timeline=True) + self.timeline_signal:SignalType = self.signal_t(value=0, timeline_for_device=self) + self._shadow_timeline_signal:SignalType = self.signal_t(value=0, timeline_for_device=self) self.sig_prof_records:list[tuple[HCQSignal, HCQSignal, str, bool]] = [] self.kernargs_buf:HCQBuffer = self.allocator.alloc(kernargs_size, BufferSpec(cpu_access=True)) self.kernargs_offset_allocator:BumpAllocator = BumpAllocator(self.kernargs_buf.size, wrap=True) - self.error_state:Exception|None = None # Exception if error is unrecoverable and sync will always fail - - if self._is_cpu(): HCQCompiled.cpu_devices.append(self) - def synchronize(self): - if self.error_state is not None: raise self.error_state - - # If we have any work on CPU devices, need to synchronize them. This is just an optimization to release GIL allowing to finish faster. - if not self._is_cpu(): - for dev in HCQCompiled.cpu_devices: dev.synchronize() - try: self.timeline_signal.wait(self.timeline_value - 1) except RuntimeError as e: - self.error_state = e if hasattr(self, 'on_device_hang'): self.on_device_hang() else: raise e @@ -409,16 +394,15 @@ class HCQCompiled(Compiled, Generic[SignalType]): self.timeline_value += 1 return self.timeline_value - 1 - def new_signal(self, **kwargs) -> SignalType: - if not HCQCompiled.signal_pool[pg:=self.peer_group]: - HCQCompiled.signal_pages[pg].append(alc:=self.allocator.alloc(self.sigalloc_size, BufferSpec(host=True, uncached=True, cpu_access=True))) - HCQCompiled.signal_pool[pg] += [alc.offset(offset=off, size=16) for off in range(0, alc.size, 16)] - for dev in HCQCompiled.peer_groups[pg]: cast(HCQAllocator, dev.allocator).map(alc) - return self.signal_t(base_buf=HCQCompiled.signal_pool[pg].pop(), owner=self, **kwargs) + @classmethod + def _alloc_signal(cls) -> HCQBuffer: + if not cls.signal_pool: + cls.signal_pages.append(alc:=cls.devices[0].allocator.alloc(cls.devices[0].sigalloc_size, BufferSpec(host=True,uncached=True,cpu_access=True))) + cls.signal_pool += [alc.offset(offset=off, size=16) for off in range(0, alc.size, 16)] + for dev in cls.devices: cast(HCQAllocator, dev.allocator).map(alc) + return cls.signal_pool.pop() def _at_profile_finalize(self): - self.synchronize() # Expect device to be synchronizes - def _sync(d:HCQCompiled, q_t:Callable[[], HWQueue]): q_t().timestamp(d.timeline_signal).signal(d.timeline_signal, d.next_timeline()).submit(d) st = time.perf_counter_ns() @@ -442,45 +426,18 @@ class HCQCompiled(Compiled, Generic[SignalType]): except MemoryError: buf, realloced = self.allocator.alloc(oldbuf.size if oldbuf is not None else new_size, options=options), False return buf, realloced - def _select_iface(self, *ifaces:Type): - errs, err_short = "", "" - if val:=getenv(f'{type(self).__name__[:-6].upper()}_IFACE', ""): ifaces = tuple(x for x in ifaces if x.__name__.startswith(val.upper())) - for iface_t in ifaces: - try: return iface_t(self, self.device_id) - except Exception as e: errs, err_short = errs + f"\n{iface_t.__name__}: {traceback.format_exc()}", err_short + f"\n{iface_t.__name__}: {e}" - raise RuntimeError(f"{errs}\nNo interface for {type(self).__name__[:-6]}:{self.device_id} is available:{err_short}\n" \ - f"\nForce an interface with {type(self).__name__[:-6].upper()}_IFACE={('|'.join(x.__name__[:-5] for x in ifaces))}.") - - def _is_cpu(self) -> bool: return hasattr(self, 'device') and self.device.split(":")[0] in ("CPU", "LLVM") - - def finalize(self): - try: self.synchronize() # Try to finalize device in any case. - except RuntimeError as e: print(f"{self.device} synchronization failed before finalizing: {e}") - - # If the device has an interface, call its device_fini method to clean up resources. - if hasattr(self, 'iface') and hasattr(self.iface, 'device_fini'): self.iface.device_fini() - class HCQBuffer: - def __init__(self, va_addr:sint, size:int, texture_info:Any=None, meta:Any=None, _base:HCQBuffer|None=None, view:MMIOInterface|None=None, - owner:HCQCompiled|None=None): + def __init__(self, va_addr:sint, size:int, texture_info:Any=None, meta:Any=None, _base:HCQBuffer|None=None, view:MMIOInterface|None=None): self.va_addr, self.size, self.texture_info, self.meta, self._base, self.view = va_addr, size, texture_info, meta, _base, view - self._devs, self.owner = ([owner] if owner is not None else []), owner - self._mappings:dict[HCQCompiled, HCQBuffer] = {} # mapping to the other devices def offset(self, offset:int=0, size:int|None=None) -> HCQBuffer: - return HCQBuffer(self.va_addr+offset, size or (self.size - offset), owner=self.owner, texture_info=self.texture_info, meta=self.meta, - _base=self._base or self, view=(self.view.view(offset=offset, size=size) if self.view is not None else None)) + return HCQBuffer(self.va_addr+offset, size or (self.size - offset), texture_info=self.texture_info, meta=self.meta, _base=self._base or self, + view=(self.view.view(offset=offset, size=size) if self.view is not None else None)) def cpu_view(self) -> MMIOInterface: assert self.view is not None, "buffer has no cpu_view" return self.view - @property - def mappings(self): return self._mappings if self._base is None else self._base._mappings - - @property - def mapped_devs(self): return self._devs if self._base is None else self._base._devs - class HCQAllocatorBase(LRUAllocator[HCQDeviceType], Generic[HCQDeviceType]): """ A base allocator class compatible with the HCQ (Hardware Command Queue) API. @@ -493,22 +450,13 @@ class HCQAllocatorBase(LRUAllocator[HCQDeviceType], Generic[HCQDeviceType]): self.b = copy_bufs or [self._alloc(batch_size, BufferSpec(host=True)) for _ in range(batch_cnt)] self.b_timeline, self.b_next, self.max_copyout_size = [0] * len(self.b), 0, max_copyout_size - def map(self, buf:HCQBuffer): - if self.dev in buf.mapped_devs: return - if buf.owner is None: raise RuntimeError(f"map failed: buffer {buf.va_addr} has no owner, it's a virtual buffer") - if not hasattr(self, '_map'): raise NotImplementedError("map failed: no method implemented") - - # Since it's unified memory space, any buffer mapping is valid for all devices after successful map. - # Devices can save mappings and internal metadata as a new buffer. - if (mb:=self._map(buf)) is not None: buf.mappings[self.dev] = mb - buf.mapped_devs.append(self.dev) - + def map(self, buf:HCQBuffer): pass def _offset(self, buf, size:int, offset:int) -> HCQBuffer: return buf.offset(offset=offset, size=size) class HCQAllocator(HCQAllocatorBase, Generic[HCQDeviceType]): def _copyin(self, dest:HCQBuffer, src:memoryview): assert self.dev.hw_copy_queue_t is not None - with hcq_profile(self.dev, queue_type=self.dev.hw_copy_queue_t, desc=f"TINY -> {self.dev.device}", enabled=PROFILE): + with hcq_profile(self.dev, queue_type=self.dev.hw_copy_queue_t, desc=f"CPU -> {self.dev.device}", enabled=PROFILE): for i in range(0, src.nbytes, self.b[0].size): self.b_next = (self.b_next + 1) % len(self.b) self.dev.timeline_signal.wait(self.b_timeline[self.b_next]) @@ -540,7 +488,7 @@ class HCQAllocator(HCQAllocatorBase, Generic[HCQDeviceType]): self.dev.synchronize() assert self.dev.hw_copy_queue_t is not None - with hcq_profile(self.dev, queue_type=self.dev.hw_copy_queue_t, desc=f"{self.dev.device} -> TINY", enabled=PROFILE): + with hcq_profile(self.dev, queue_type=self.dev.hw_copy_queue_t, desc=f"{self.dev.device} -> CPU", enabled=PROFILE): for i in range(0, dest.nbytes, cp_size:=(self.max_copyout_size or self.b[0].size)): self.dev.hw_copy_queue_t().wait(self.dev.timeline_signal, self.dev.timeline_value - 1) \ .copy(self.b[0].va_addr, src.va_addr+i, lsize:=min(cp_size, dest.nbytes-i)) \ diff --git a/tinygrad_repo/tinygrad/runtime/support/ib.py b/tinygrad_repo/tinygrad/runtime/support/ib.py deleted file mode 100644 index 06c1220e4..000000000 --- a/tinygrad_repo/tinygrad/runtime/support/ib.py +++ /dev/null @@ -1,172 +0,0 @@ -from __future__ import annotations -import resource, ctypes, weakref, functools, itertools, tinygrad.runtime.autogen.ib as ib -from typing import Iterator -from dataclasses import dataclass -from weakref import WeakKeyDictionary -from tinygrad.device import Buffer, DMACPURef, DMAFdRef -from tinygrad.helpers import getenv, round_up, DEBUG - -DEFAULT_PORT, DEFAULT_GID = getenv("DEFAULT_PORT", 1), getenv("DEFAULT_GID", 3) # DEFAULT_GID=0 for RXE -IOVA_ALIGN = resource.getpagesize() - -def checkz(x, ret=None): - assert x == 0, f'{x} != 0 (errno {ctypes.get_errno()})' - return ret - -@dataclass(frozen=True) -class SGE: - dst_iova: int - dst_key: int - src_iova: int - src_key: int - size: int - -class IBCtx: - def __init__(self, idx:int): - # Open the device (aka Host Channel Adapter in ib-speak) - devs = ib.ibv_get_device_list(ctypes.byref(ndevs:=ctypes.c_int32())) - if idx >= ndevs.value: raise IndexError(f"{idx} > {ndevs.value}") - self.ctx = ib.ibv_open_device(devs[idx]) - ib.ibv_free_device_list(devs) - - # HACK: remove this (and all usage of `ctx.contents.ops`) when clang2py can deal with `static inline` wrapper-functions - self.vctx = ctypes.cast(ctypes.addressof(self.ctx.contents) - ib.struct_verbs_context.context.offset, ctypes.POINTER(ib.struct_verbs_context)) - - # Get attributes. Something like port_attr.max_msg_sz sound like it might requre taking the min of host's and remote's attributes if they differ - self.device_attr = checkz(ib.ibv_query_device(self.ctx, ctypes.byref(da:=ib.struct_ibv_device_attr())), da) - self.port_attr = checkz(self.vctx.contents.query_port(self.ctx, DEFAULT_PORT, ctypes.byref(pa:=ib.struct_ibv_port_attr()), ctypes.sizeof(pa)), pa) - self.gid_attr = checkz(ib.ibv_query_gid(self.ctx, DEFAULT_PORT, DEFAULT_GID, ctypes.byref(ga:=ib.union_ibv_gid())), ga) - - # Allocate protection domain - self.pd = ib.ibv_alloc_pd(self.ctx) - self.next_iova: int = IOVA_ALIGN # don't start at zero (nullptr) - - # weakref(buf) => (iova, mr, mr_dealloc). mr_dealloc is kept here to avoid double freeing mrs that are deallocated in __del__ - self.mrs: WeakKeyDictionary[Buffer, tuple[int, ctypes._Pointer[ib.struct_ibv_mr], weakref.finalize]] = WeakKeyDictionary() - - # Default soft fd limit is 1024, which is not enough, set soft to hard (maximum allowed by the os) - IBCtx.rlimit_fix() - - def __del__(self): - # must deallocate all mrs in protection domain before deallocating the protection domain - if hasattr(self, "mrs"): [fin() for _,_,fin in self.mrs.values()] - if hasattr(self, "pd"): ib.ibv_dealloc_pd(self.pd) - if hasattr(self, "ctx"): ib.ibv_close_device(self.ctx) - - @functools.cache # run once - @staticmethod - def rlimit_fix(): - soft, hard = resource.getrlimit(resource.RLIMIT_NOFILE) - resource.setrlimit(resource.RLIMIT_NOFILE, (hard, hard)) - if DEBUG>=2: print(f"IB: Increased fd limit from {soft} to {hard}") - - def alloc_iova(self, size:int, required_offset:int): - iova = round_up(self.next_iova - required_offset, IOVA_ALIGN) + required_offset - self.next_iova = iova + size - return iova - - def reg(self, buf:Buffer) -> tuple[int, ctypes._Pointer[ib.struct_ibv_mr]]: - buf = buf.base - if buf not in self.mrs: - if buf.nbytes > self.device_attr.max_mr_size: raise RuntimeError(f"Buffer too big: {buf.nbytes:#x} > {self.device_attr.max_mr_size:#x}") - if len(self.mrs) >= self.device_attr.max_mr: raise RuntimeError(f"Out of memory region cap: {len(self.mrs)} >= {self.device_attr.max_mr}") - # Local read is implied (but still have to create the memory region, except for short sends/writes with IBV_SEND_INLINE that are inlined by cpu) - mr_flags = ib.IBV_ACCESS_LOCAL_WRITE | ib.IBV_ACCESS_REMOTE_READ | ib.IBV_ACCESS_REMOTE_WRITE - match (dmaref:=buf.as_dmaref()): - case DMACPURef(): - iova = self.alloc_iova(dmaref.size, dmaref.addr % IOVA_ALIGN) - mr = ib.ibv_reg_mr_iova2(self.pd, ctypes.c_void_p(dmaref.addr), dmaref.size, iova, mr_flags) - case DMAFdRef(): - iova = self.alloc_iova(dmaref.size, dmaref.offset % IOVA_ALIGN) - mr = ib.ibv_reg_dmabuf_mr(self.pd, dmaref.offset, dmaref.size, iova, dmaref.fd, mr_flags) - case _: raise RuntimeError(f"Unknown type of dma ref: {dmaref}") - if not mr: raise RuntimeError(f"Couldn't register memory region for {buf} {dmaref} (errno={ctypes.get_errno()})") - self.mrs[buf] = (iova, mr, weakref.finalize(buf, ib.ibv_dereg_mr, mr)) - return self.mrs[buf][0:2] - -class IBConn: - def __init__(self, ctx:IBCtx): - self.ctx = ctx - - # Create Completion Channel. It is a file descriptor that kernel sends notifications through, not a thing in infiniband spec, just linux-ism - self.comp_channel = ib.ibv_create_comp_channel(self.ctx.ctx) - # Create Completion Queue. When a Work Request with signaled flag is completed a Completion Queue Entry is pushed onto this queue - self.cq = ib.ibv_create_cq(self.ctx.ctx, _capacity:=256, _cq_context:=None, self.comp_channel, _comp_vector:=0) - self.pending_wrids: set[int] = set() - self.wrid_num: Iterator[int] = itertools.count(0) # wc_id is uint64, this will never overflow - - # Create Queue Pair. It's the closest thing to a socket in infiniband with QP num being the closest thing to a port, except it's allocated by hca - qp_init_attrs_cap = ib.struct_ibv_qp_cap(max_send_wr=1024, max_recv_wr=64, max_send_sge=8, max_recv_sge=8, max_inline_data=64) - qp_init_attrs = ib.struct_ibv_qp_init_attr(send_cq=self.cq, recv_cq=self.cq, cap=qp_init_attrs_cap, qp_type=ib.IBV_QPT_RC) # Reliable Connection - self.qp = ib.ibv_create_qp(self.ctx.pd, ctypes.byref(qp_init_attrs)) - self.qp_cap = qp_init_attrs.cap - - # The most important thing about QPs is their state, when a new QP is created it's in the RESET state, before it can be properly used it has to go - # through Init, Ready To Receive, Ready To Send. A good docs on QP state machine: https://www.rdmamojo.com/2012/05/05/qp-state-machine/ - - # INIT - qp_access_flags = ib.IBV_ACCESS_REMOTE_WRITE | ib.IBV_ACCESS_REMOTE_READ - qpa = ib.struct_ibv_qp_attr(qp_state=ib.IBV_QPS_INIT, port_num=DEFAULT_PORT, qp_access_flags=qp_access_flags) - checkz(ib.ibv_modify_qp(self.qp, qpa, ib.IBV_QP_STATE | ib.IBV_QP_PORT | ib.IBV_QP_ACCESS_FLAGS | ib.IBV_QP_PKEY_INDEX)) - - self.gid, self.qp_num = bytes(self.ctx.gid_attr.raw), self.qp.contents.qp_num - - # Exchange GID and QP num with remote. At least in RoCEv2 gid can be guessed from remote's ip, QP num can't. - - def connect(self, remote_gid:bytes, remote_qp_num:int): - # RTR - qp_ah_attr_grh = ib.struct_ibv_global_route(hop_limit=1, dgid=ib.union_ibv_gid(raw=(ctypes.c_ubyte * 16)(*remote_gid)), sgid_index=DEFAULT_GID) - qp_ah_attr = ib.struct_ibv_ah_attr(is_global=1, port_num=DEFAULT_PORT, grh=qp_ah_attr_grh) - qpa = ib.struct_ibv_qp_attr(qp_state=ib.IBV_QPS_RTR, path_mtu=ib.IBV_MTU_4096, dest_qp_num=remote_qp_num, rq_psn=0, max_dest_rd_atomic=1, - min_rnr_timer=12, ah_attr=qp_ah_attr) - checkz(ib.ibv_modify_qp(self.qp, qpa, ib.IBV_QP_STATE | ib.IBV_QP_PATH_MTU | ib.IBV_QP_DEST_QPN | ib.IBV_QP_RQ_PSN | \ - ib.IBV_QP_MAX_DEST_RD_ATOMIC | ib.IBV_QP_MIN_RNR_TIMER | ib.IBV_QP_AV)) - - # RTS - qpa = ib.struct_ibv_qp_attr(qp_state=ib.IBV_QPS_RTS, timeout=14, retry_cnt=7, rnr_retry=7, sq_psn=0, max_rd_atomic=1) - checkz(ib.ibv_modify_qp(self.qp, qpa, ib.IBV_QP_STATE | ib.IBV_QP_TIMEOUT | ib.IBV_QP_RETRY_CNT | ib.IBV_QP_RNR_RETRY | ib.IBV_QP_SQ_PSN | \ - ib.IBV_QP_MAX_QP_RD_ATOMIC)) - - def __del__(self): - self.wait_cq() # need to wait for **everything** to complete before it's safe to dealloc queues and stuff - ib.ibv_destroy_qp(self.qp) - ib.ibv_destroy_cq(self.cq) - ib.ibv_destroy_comp_channel(self.comp_channel) - - def next_wrid(self): - self.pending_wrids.add(wrid:=next(self.wrid_num)) - return wrid - - def wait_cq(self, wr_id: int|None=None): - while (wr_id in self.pending_wrids) if wr_id is not None else self.pending_wrids: - if self.ctx.ctx.contents.ops.poll_cq(self.cq, _num_entries:=1, ctypes.byref(wc:=ib.struct_ibv_wc())): - if wc.status != ib.IBV_WC_SUCCESS: - raise RuntimeError(f'Work Request completed with error: wr_id={wc.wr_id} status={ib.ibv_wc_status__enumvalues.get(wc.status, wc.status)}') - self.pending_wrids.remove(wc.wr_id) - - def rdma_write(self, sgl:list[SGE]): - swr: ctypes._Pointer[ib.struct_ibv_send_wr]|None = None - swr_cnt, wr_id = 0, self.next_wrid() - def _post(): - nonlocal swr, swr_cnt, wr_id - if swr is not None: - # The swr can be freed when this returns, the memory that sge points to can be unmapped after work completion is retrieved from cq - checkz(self.ctx.ctx.contents.ops.post_send(self.qp, swr, ctypes.byref(_bad_wr:=ctypes.POINTER(ib.struct_ibv_send_wr)()))) - # TODO: async - self.wait_cq(wr_id) - swr, swr_cnt, wr_id = None, 0, self.next_wrid() - # Everything is in reverse for elegant chaining - for sg in reversed(sgl): - # Message size limit (max 2GB per ib spec, 1GB on tinybox mellanoxes) applies to both scatter-gather entries and entire wrs - for off in reversed(range(0, sg.size, self.ctx.port_attr.max_msg_sz)): - # Scatter-Gather Entry for local memory - sge = ctypes.pointer(ib.struct_ibv_sge(addr=sg.src_iova+off, length=min(sg.size-off, self.ctx.port_attr.max_msg_sz), lkey=sg.src_key)) - # RDMA struct for remote memory - wr = ib.union_ibv_send_wr_wr(rdma=ib.struct_ibv_send_wr_1_rdma(remote_addr=sg.dst_iova+off, rkey=sg.dst_key)) - # Signal (with chosen work request id) if it's the last wr (first in the loop since it's reversed) - wid, flags = (wr_id, ib.IBV_SEND_SIGNALED) if swr is None else (0, 0) - # Create Send Request - swr = ctypes.pointer(ib.struct_ibv_send_wr(opcode=ib.IBV_WR_RDMA_WRITE, sg_list=sge, num_sge=1, wr=wr, wr_id=wid, send_flags=flags, next=swr)) - # Flush if queue is being overrun - if (swr_cnt:=swr_cnt + 1) >= self.qp_cap.max_send_wr: _post() - _post() diff --git a/tinygrad_repo/tinygrad/runtime/support/memory.py b/tinygrad_repo/tinygrad/runtime/support/memory.py index 0c74ea412..35fe4f339 100644 --- a/tinygrad_repo/tinygrad/runtime/support/memory.py +++ b/tinygrad_repo/tinygrad/runtime/support/memory.py @@ -77,10 +77,11 @@ class TLSFAllocator: if self.lv1_entries[l1] == 0: continue for l2 in range(self.lv2(size) if l1 == size.bit_length() else 0, (1 << self.l2_cnt)): if len(self.storage[l1][l2]) > 0: + nsize = self.blocks[self.storage[l1][l2][0]][0] + assert nsize >= size, "block must be larger" + # Block start address. start = self.storage[l1][l2][0] - nsize = self.blocks[start][0] - assert nsize >= size, "block must be larger" # If request contains alignment, split the block into two parts. if (new_start:=round_up(start, align)) != start: @@ -117,7 +118,7 @@ class PageTableTraverseContext: assert self.create_pts, "Not allowed to create new page table" pt.set_entry(pte_idx, self.dev.mm.palloc(0x1000, zero=True, boot=self.boot), table=True, valid=True) - assert not pt.is_page(pte_idx), f"Must be table pt={pt.paddr:#x}, {pt.lv=} {pte_idx=} {pt.read_fields(pte_idx)}" + assert not pt.is_pte(pte_idx), f"Must be table pt={pt.paddr:#x}, {pt.lv=} {pte_idx=} {pt.read_fields(pte_idx)}" child_page_table = self.dev.mm.pt_t(self.dev, pt.address(pte_idx), lv=pt.lv+1) self.pt_stack.append((child_page_table, self._pt_pte_idx(child_page_table, self.vaddr), self._pt_pte_size(child_page_table))) @@ -137,14 +138,13 @@ class PageTableTraverseContext: pt, pt_cnt, _ = self.pt_stack.pop() if pt_cnt == self._pt_pte_cnt(pt.lv): self.pt_stack[-1] = (self.pt_stack[-1][0], self.pt_stack[-1][1] + 1, self.pt_stack[-1][2]) - def next(self, size:int, paddr:int|None=None, off:int=0): + def next(self, size:int, off=0): while size > 0: pt, pte_idx, pte_covers = self.pt_stack[-1] if self.create_pts: - assert paddr is not None, "paddr must be provided when allocating new page tables" - while pte_covers > size or not pt.supports_huge_page(paddr+off) or self.vaddr&(pte_covers-1) != 0: pt, pte_idx, pte_covers = self.level_down() + while pt.lv < self.dev.mm.first_page_lv or pte_covers > size or self.vaddr & (pte_covers-1) != 0: pt, pte_idx, pte_covers = self.level_down() else: - while not pt.is_page(pte_idx): pt, pte_idx, pte_covers = self.level_down() + while not pt.is_pte(pte_idx): pt, pte_idx, pte_covers = self.level_down() entries = min(size // pte_covers, self._pt_pte_cnt(pt.lv) - pte_idx) assert entries > 0, f"Invalid entries {size=:#x}, {pte_covers=:#x}" @@ -157,11 +157,9 @@ class PageTableTraverseContext: class MemoryManager: va_allocator: ClassVar[TLSFAllocator|None] = None - def __init__(self, dev, vram_size:int, boot_size:int, pt_t, va_bits:int, va_shifts:list[int], va_base:int, - palloc_ranges:list[tuple[int, int]], first_lv:int=0): - self.dev, self.vram_size, self.va_shifts, self.va_base, lvl_msb = dev, vram_size, va_shifts, va_base, va_shifts + [va_bits + 1] - self.pte_covers, self.pte_cnt = [1 << x for x in va_shifts][::-1], [1 << (lvl_msb[i+1] - lvl_msb[i]) for i in range(len(lvl_msb) - 1)][::-1] - self.pt_t, self.palloc_ranges, self.level_cnt, self.va_bits = pt_t, palloc_ranges, len(va_shifts), va_bits + def __init__(self, dev, vram_size:int, boot_size:int, pt_t, pte_cnt:list[int], pte_covers:list[int], first_lv:int, first_page_lv:int, va_base:int): + self.dev, self.vram_size, self.va_base = dev, vram_size, va_base + self.pt_t, self.pte_cnt, self.pte_covers, self.first_page_lv = pt_t, pte_cnt, pte_covers, first_page_lv self.boot_allocator = TLSFAllocator(boot_size, base=0) # per device self.pa_allocator = TLSFAllocator(vram_size - (64 << 20), base=self.boot_allocator.size) # per device @@ -178,7 +176,7 @@ class MemoryManager: def page_tables(self, vaddr:int, size:int): ctx = PageTableTraverseContext(self.dev, self.root_page_table, vaddr, create_pts=True) - for _ in ctx.next(size, paddr=0): return [pt for pt, _, _ in ctx.pt_stack] + for _ in ctx.next(size): return [pt for pt, _, _ in ctx.pt_stack] def map_range(self, vaddr:int, size:int, paddrs:list[tuple[int, int]], uncached=False, system=False, snooped=False, boot=False) -> VirtMapping: if getenv("MM_DEBUG", 0): print(f"mm {self.dev.devfmt}: mapping {vaddr=:#x} ({size=:#x})") @@ -187,7 +185,7 @@ class MemoryManager: ctx = PageTableTraverseContext(self.dev, self.root_page_table, vaddr, create_pts=True, boot=boot) for paddr, psize in paddrs: - for off, pt, pte_idx, pte_cnt, pte_covers in ctx.next(psize, paddr=paddr): + for off, pt, pte_idx, pte_cnt, pte_covers in ctx.next(psize): for pte_off in range(pte_cnt): assert not pt.valid(pte_idx + pte_off), f"PTE already mapped: {pt.entry(pte_idx + pte_off):#x}" pt.set_entry(pte_idx + pte_off, paddr + off + pte_off * pte_covers, uncached=uncached, system=system, snooped=snooped, @@ -219,19 +217,23 @@ class MemoryManager: if contiguous: paddrs = [(self.palloc(size, zero=True), size)] else: # Traverse the PT to find the largest contiguous sizes we need to allocate. Try to allocate the longest segment to reduce TLB pressure. - nxt_range, rem_size, paddrs = 0, size, [] - while rem_size > 0: - while self.palloc_ranges[nxt_range][0] > rem_size: nxt_range += 1 + paddrs = [] + ctx = PageTableTraverseContext(self.dev, self.root_page_table, va, create_pts=True) + for off, _, _, seg_cnt, seg_size in ctx.next(size): + rem_len = seg_cnt * seg_size + while rem_len > 0: + # Try to allocate as long segment (power of 2) as possible + cont_seg_sz, paddr = 1 << (self._frag_size(ctx.vaddr+off, rem_len) + 12), None + while cont_seg_sz >= 0x1000: + try: paddr = self.palloc(cont_seg_sz, zero=False) + except MemoryError: cont_seg_sz //= 2 + else: break - try: paddrs += [(self.palloc(try_sz:=self.palloc_ranges[nxt_range][0], self.palloc_ranges[nxt_range][1], zero=False), try_sz)] - except MemoryError: - # Move to a smaller size and try again. - nxt_range += 1 - if nxt_range == len(self.palloc_ranges): + if paddr is not None: paddrs += [(paddr, cont_seg_sz)] + else: for paddr, _ in paddrs: self.pa_allocator.free(paddr) - raise MemoryError(f"Failed to allocate memory. (total allocation size={size:#x}, current try={self.palloc_ranges[nxt_range-1]})") - continue - rem_size -= self.palloc_ranges[nxt_range][0] + raise MemoryError(f"Failed to allocate a contiguous page. (allocation size={size:#x})") + rem_len, off = rem_len - cont_seg_sz, off + cont_seg_sz return self.map_range(va, size, paddrs, uncached=uncached) diff --git a/tinygrad_repo/tinygrad/runtime/support/nv/ip.py b/tinygrad_repo/tinygrad/runtime/support/nv/ip.py index 203796021..3bd35a184 100644 --- a/tinygrad_repo/tinygrad/runtime/support/nv/ip.py +++ b/tinygrad_repo/tinygrad/runtime/support/nv/ip.py @@ -1,38 +1,36 @@ from __future__ import annotations import ctypes, time, array, struct, itertools, dataclasses -from typing import cast, Any from tinygrad.runtime.autogen.nv import nv -from tinygrad.helpers import to_mv, lo32, hi32, DEBUG, round_up, round_down, mv_address, fetch, wait_cond +from tinygrad.helpers import to_mv, lo32, hi32, DEBUG, round_up, round_down, mv_address, fetch from tinygrad.runtime.support.system import System from tinygrad.runtime.support.elf import elf_loader from tinygrad.runtime.autogen import nv_gpu @dataclasses.dataclass(frozen=True) -class GRBufDesc: size:int; virt:bool; phys:bool; local:bool=False # noqa: E702 +class GRBufDesc: size:int; v:int; p:int; lc:int=0 # noqa: E702 class NV_IP: def __init__(self, nvdev): self.nvdev = nvdev def init_sw(self): pass # Prepare sw/allocations for this IP def init_hw(self): pass # Initialize hw for this IP - def fini_hw(self): pass # Finalize hw for this IP class NVRpcQueue: def __init__(self, gsp:NV_GSP, va:int, completion_q_va:int|None=None): self.tx = nv.msgqTxHeader.from_address(va) - wait_cond(lambda: self.tx.entryOff, value=0x1000, msg="RPC queue not initialized") + while self.tx.entryOff != 0x1000: pass # wait for the tx header to be initialized if completion_q_va is not None: self.rx = nv.msgqRxHeader.from_address(completion_q_va + nv.msgqTxHeader.from_address(completion_q_va).rxHdrOff) self.gsp, self.va, self.queue_va, self.seq = gsp, va, va + self.tx.entryOff, 0 self.queue_mv = to_mv(self.queue_va, self.tx.msgSize * self.tx.msgCount) - def _checksum(self, data:bytes): + def _checksum(self, data): if (pad_len:=(-len(data)) % 8): data += b'\x00' * pad_len checksum = 0 for offset in range(0, len(data), 8): checksum ^= struct.unpack_from('Q', data, offset)[0] - return hi32(checksum) ^ lo32(checksum) + return ((checksum >> 32) & 0xFFFFFFFF) ^ (checksum & 0xFFFFFFFF) - def send_rpc(self, func:int, msg:bytes, wait=False): + def send_rpc(self, func, msg, wait=False): header = nv.rpc_message_header_v(signature=nv.NV_VGPU_MSG_SIGNATURE_VALID, rpc_result=nv.NV_VGPU_MSG_RESULT_RPC_PENDING, rpc_result_private=nv.NV_VGPU_MSG_RESULT_RPC_PENDING, header_version=(3<<24), function=func, length=len(msg) + 0x20) @@ -49,7 +47,7 @@ class NVRpcQueue: self.seq += 1 self.gsp.nvdev.NV_PGSP_QUEUE_HEAD[0].write(0x0) - def wait_resp(self, cmd:int) -> memoryview: + def wait_resp(self, cmd) -> memoryview: while True: System.memory_barrier() if self.rx.readPtr == self.tx.writePtr: continue @@ -60,14 +58,13 @@ class NVRpcQueue: # Handling special functions if hdr.function == nv.NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER: self.gsp.run_cpu_seq(msg) - elif hdr.function == nv.NV_VGPU_MSG_EVENT_OS_ERROR_LOG: - print(f"nv {self.gsp.nvdev.devfmt}: GSP LOG: {msg[12:].tobytes().rstrip(bytes([0])).decode('utf-8')}") + elif hdr.function == nv.NV_VGPU_MSG_EVENT_OS_ERROR_LOG: print(f"GSP LOG: {msg[12:].tobytes().rstrip(bytes([0])).decode('utf-8')}") # Update the read pointer self.rx.readPtr = (self.rx.readPtr + round_up(hdr.length, self.tx.msgSize) // self.tx.msgSize) % self.tx.msgCount System.memory_barrier() - if DEBUG >= 3: + if DEBUG >= 2: rpc_names = {**nv.c__Ea_NV_VGPU_MSG_FUNCTION_NOP__enumvalues, **nv.c__Ea_NV_VGPU_MSG_EVENT_FIRST_EVENT__enumvalues} print(f"nv {self.gsp.nvdev.devfmt}: in RPC: {rpc_names.get(hdr.function, f'ev:{hdr.function:x}')}, res:{hdr.rpc_result:#x}") @@ -89,7 +86,7 @@ class NV_FLCN(NV_IP): self.prep_booter() def prep_ucode(self): - expansion_rom_off, bit_addr = {"GA": 0x16600, "AD": 0x14e00}[self.nvdev.chip_name[:2]], 0x1b0 + expansion_rom_off, bit_addr = 0x14e00, 0x1b0 vbios_bytes = bytes(array.array('I', self.nvdev.mmio[0x00300000//4:(0x00300000+0x98e00)//4])) bit_header = nv.BIT_HEADER_V1_00.from_buffer_copy(vbios_bytes[bit_addr:bit_addr + ctypes.sizeof(nv.BIT_HEADER_V1_00)]) @@ -124,17 +121,12 @@ class NV_FLCN(NV_IP): def __patch(cmd_id, cmd): patched_image = bytearray(image) - hdr = nv.FALCON_APPLICATION_INTERFACE_HEADER_V1.from_buffer_copy(image[(app_hdr_off:=self.desc_v3.IMEMLoadSize+self.desc_v3.InterfaceOffset):]) - ents = (nv.FALCON_APPLICATION_INTERFACE_ENTRY_V1 * hdr.entryCount).from_buffer_copy(image[app_hdr_off + ctypes.sizeof(hdr):]) - for i in range(hdr.entryCount): - if ents[i].id == nv.FALCON_APPLICATION_INTERFACE_ENTRY_ID_DMEMMAPPER: dmem_offset = ents[i].dmemOffset - # Patch image - dmem = nv.FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3.from_buffer_copy(image[(dmem_mapper_offset:=self.desc_v3.IMEMLoadSize+dmem_offset):]) + dmem = nv.FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3.from_buffer_copy(image[(dmem_mapper_offset:=self.desc_v3.IMEMLoadSize+0xae0):]) dmem.init_cmd = cmd_id patched_image[dmem_mapper_offset : dmem_mapper_offset+len(bytes(dmem))] = bytes(dmem) patched_image[(cmd_off:=self.desc_v3.IMEMLoadSize+dmem.cmd_in_buffer_offset) : cmd_off+len(cmd)] = cmd - patched_image[(sig_off:=self.desc_v3.IMEMLoadSize+self.desc_v3.PKCDataOffset) : sig_off+0x180] = signature[-0x180:] + patched_image[(sig_off:=self.desc_v3.IMEMLoadSize+self.desc_v3.PKCDataOffset) : sig_off+0x180] = signature[0x180:] return System.alloc_sysmem(len(patched_image), contiguous=True, data=patched_image) @@ -160,7 +152,6 @@ class NV_FLCN(NV_IP): imemPa=self.desc_v3.IMEMPhysBase, imemVa=self.desc_v3.IMEMVirtBase, imemSz=self.desc_v3.IMEMLoadSize, dmemPa=self.desc_v3.DMEMPhysBase, dmemVa=0x0, dmemSz=self.desc_v3.DMEMLoadSize, pkc_off=self.desc_v3.PKCDataOffset, engid=self.desc_v3.EngineIdMask, ucodeid=self.desc_v3.UcodeId) - assert self.nvdev.NV_PFB_PRI_MMU_WPR2_ADDR_HI.read() != 0, "WPR2 is not initialized" self.reset(self.falcon, riscv=True) @@ -173,34 +164,35 @@ class NV_FLCN(NV_IP): mbx = self.execute_hs(self.sec2, self.booter_image_sysmem[0], code_off=self.booter_code_off, data_off=self.booter_data_off, imemPa=0x0, imemVa=self.booter_code_off, imemSz=self.booter_code_sz, dmemPa=0x0, dmemVa=0x0, dmemSz=self.booter_data_sz, pkc_off=0x10, engid=1, ucodeid=3, mailbox=self.nvdev.gsp.wpr_meta_sysmem) - assert mbx[0] == 0x0, f"Booter failed to execute, mailbox is {mbx[0]:08x}, {mbx[1]:08x}" + assert mbx[0] == 0x0, f"Booster failed to execute, mailbox is {mbx[0]:08x}, {mbx[1]:08x}" self.nvdev.NV_PFALCON_FALCON_OS.with_base(self.falcon).write(0x0) assert self.nvdev.NV_PRISCV_RISCV_CPUCTL.with_base(self.falcon).read_bitfields()['active_stat'] == 1, "GSP Core is not active" - def execute_dma(self, base:int, cmd:int, dest:int, mem_off:int, sysmem:int, size:int): - wait_cond(lambda: self.nvdev.NV_PFALCON_FALCON_DMATRFCMD.with_base(base).read_bitfields()['full'], value=0, msg="DMA does not progress") + def execute_dma(self, base, cmd, dest, mem_off, sysmem, size): + while self.nvdev.NV_PFALCON_FALCON_DMATRFCMD.with_base(base).read_bitfields()['full'] != 0: pass self.nvdev.NV_PFALCON_FALCON_DMATRFBASE.with_base(base).write(lo32(sysmem >> 8)) self.nvdev.NV_PFALCON_FALCON_DMATRFBASE1.with_base(base).write(hi32(sysmem >> 8) & 0x1ff) xfered = 0 while xfered < size: - wait_cond(lambda: self.nvdev.NV_PFALCON_FALCON_DMATRFCMD.with_base(base).read_bitfields()['full'], value=0, msg="DMA does not progress") + while self.nvdev.NV_PFALCON_FALCON_DMATRFCMD.with_base(base).read_bitfields()['full'] != 0: pass self.nvdev.NV_PFALCON_FALCON_DMATRFMOFFS.with_base(base).write(dest + xfered) self.nvdev.NV_PFALCON_FALCON_DMATRFFBOFFS.with_base(base).write(mem_off + xfered) self.nvdev.NV_PFALCON_FALCON_DMATRFCMD.with_base(base).write(cmd) xfered += 256 - wait_cond(lambda: self.nvdev.NV_PFALCON_FALCON_DMATRFCMD.with_base(base).read_bitfields()['idle'], msg="DMA does not complete") + while self.nvdev.NV_PFALCON_FALCON_DMATRFCMD.with_base(base).read_bitfields()['idle'] != 1: pass - def start_cpu(self, base:int): + def start_cpu(self, base): if self.nvdev.NV_PFALCON_FALCON_CPUCTL.with_base(base).read_bitfields()['alias_en'] == 1: self.nvdev.wreg(base + self.nvdev.NV_PFALCON_FALCON_CPUCTL_ALIAS, 0x2) else: self.nvdev.NV_PFALCON_FALCON_CPUCTL.with_base(base).write(startcpu=1) - def wait_cpu_halted(self, base): wait_cond(lambda: self.nvdev.NV_PFALCON_FALCON_CPUCTL.with_base(base).read_bitfields()['halted'], msg="not halted") + def wait_cpu_halted(self, base): + while self.nvdev.NV_PFALCON_FALCON_CPUCTL.with_base(base).read_bitfields()['halted'] == 0: pass def execute_hs(self, base, img_sysmem, code_off, data_off, imemPa, imemVa, imemSz, dmemPa, dmemVa, dmemSz, pkc_off, engid, ucodeid, mailbox=None): self.disable_ctx_req(base) @@ -233,78 +225,24 @@ class NV_FLCN(NV_IP): if mailbox is not None: return self.nvdev.NV_PFALCON_FALCON_MAILBOX0.with_base(base).read(), self.nvdev.NV_PFALCON_FALCON_MAILBOX1.with_base(base).read() - def disable_ctx_req(self, base:int): + def disable_ctx_req(self, base): self.nvdev.NV_PFALCON_FBIF_CTL.with_base(base).update(allow_phys_no_ctx=1) self.nvdev.NV_PFALCON_FALCON_DMACTL.with_base(base).write(0x0) - def reset(self, base:int, riscv=False): + def reset(self, base, riscv=False): engine_reg = self.nvdev.NV_PGSP_FALCON_ENGINE if base == self.falcon else self.nvdev.NV_PSEC_FALCON_ENGINE engine_reg.write(reset=1) time.sleep(0.1) engine_reg.write(reset=0) - wait_cond(lambda: self.nvdev.NV_PFALCON_FALCON_HWCFG2.with_base(base).read_bitfields()['mem_scrubbing'], value=0, msg="Scrubbing not completed") + while self.nvdev.NV_PFALCON_FALCON_HWCFG2.with_base(base).read_bitfields()['mem_scrubbing'] != 0: time.sleep(0.1) if riscv: self.nvdev.NV_PRISCV_RISCV_BCR_CTRL.with_base(base).write(core_select=1, valid=0, brfetch=1) elif self.nvdev.NV_PFALCON_FALCON_HWCFG2.with_base(base).read_bitfields()['riscv'] == 1: self.nvdev.NV_PRISCV_RISCV_BCR_CTRL.with_base(base).write(core_select=0) - wait_cond(lambda: self.nvdev.NV_PRISCV_RISCV_BCR_CTRL.with_base(base).read_bitfields()['valid'], msg="RISCV core not booted") + while self.nvdev.NV_PRISCV_RISCV_BCR_CTRL.with_base(base).read_bitfields()['valid'] != 1: pass self.nvdev.NV_PFALCON_FALCON_RM.with_base(base).write(self.nvdev.chip_id) -class NV_FLCN_COT(NV_IP): - def init_sw(self): - self.nvdev.include("src/common/inc/swref/published/ampere/ga102/dev_gsp.h") - self.nvdev.include("src/common/inc/swref/published/hopper/gh100/dev_falcon_v4.h") - self.nvdev.include("src/common/inc/swref/published/hopper/gh100/dev_vm.h") - self.nvdev.include("src/common/inc/swref/published/hopper/gh100/dev_fsp_pri.h") - self.nvdev.include("src/common/inc/swref/published/turing/tu102/dev_bus.h") - self.nvdev.include("src/nvidia/arch/nvalloc/common/inc/fsp/fsp_mctp_format.h") - self.nvdev.include("src/nvidia/arch/nvalloc/common/inc/fsp/fsp_emem_channels.h") - - self.fmc_boot_args, self.fmc_boot_args_sysmem = self.nvdev._alloc_boot_struct(nv.GSP_FMC_BOOT_PARAMS()) - self.init_fmc_image() - - def init_fmc_image(self): - self.fmc_booter_image = self.nvdev.extract_fw("kgspBinArchiveGspRmFmcGfwProdSigned", "ucode_image_data") - self.fmc_booter_hash = memoryview(self.nvdev.extract_fw("kgspBinArchiveGspRmFmcGfwProdSigned", "ucode_hash_data")).cast('I') - self.fmc_booter_sig = memoryview(self.nvdev.extract_fw("kgspBinArchiveGspRmFmcGfwProdSigned", "ucode_sig_data")).cast('I') - self.fmc_booter_pkey = memoryview(self.nvdev.extract_fw("kgspBinArchiveGspRmFmcGfwProdSigned", "ucode_pkey_data") + b'\x00\x00\x00').cast('I') - _, self.fmc_booter_sysmem = System.alloc_sysmem(len(self.fmc_booter_image), contiguous=True, data=self.fmc_booter_image) - - def init_hw(self): - self.falcon = 0x00110000 - - self.fmc_boot_args.bootGspRmParams = nv.GSP_ACR_BOOT_GSP_RM_PARAMS(gspRmDescOffset=self.nvdev.gsp.wpr_meta_sysmem, - gspRmDescSize=ctypes.sizeof(nv.GspFwWprMeta), target=nv.GSP_DMA_TARGET_COHERENT_SYSTEM, bIsGspRmBoot=True) - self.fmc_boot_args.gspRmParams = nv.GSP_RM_PARAMS(bootArgsOffset=self.nvdev.gsp.libos_args_sysmem[0], target=nv.GSP_DMA_TARGET_COHERENT_SYSTEM) - - cot_payload = nv.NVDM_PAYLOAD_COT(version=0x2, size=ctypes.sizeof(nv.NVDM_PAYLOAD_COT), frtsVidmemOffset=0x1c00000, frtsVidmemSize=0x100000, - gspBootArgsSysmemOffset=self.fmc_boot_args_sysmem, gspFmcSysmemOffset=self.fmc_booter_sysmem[0]) - for i,x in enumerate(self.fmc_booter_hash): cot_payload.hash384[i] = x - for i,x in enumerate(self.fmc_booter_sig): cot_payload.signature[i] = x - for i,x in enumerate(self.fmc_booter_pkey): cot_payload.publicKey[i] = x - - self.kfsp_send_msg(nv.NVDM_TYPE_COT, bytes(cot_payload)) - wait_cond(lambda: self.nvdev.NV_PFALCON_FALCON_HWCFG2.with_base(self.falcon).read_bitfields()['riscv_br_priv_lockdown'], value=0) - - def kfsp_send_msg(self, nvmd:int, buf:bytes): - # All single-packets go to seid 0 - headers = int.to_bytes((1 << 31) | (1 << 30), 4, 'little') + int.to_bytes((0x7e << 0) | (0x10de << 8) | (nvmd << 24), 4, 'little') - buf = headers + buf + (4 - (len(buf) % 4)) * b'\x00' - assert len(buf) < 0x400, f"FSP message too long: {len(buf)} bytes, max 1024 bytes" - - self.nvdev.NV_PFSP_EMEMC[0].write(offs=0, blk=0, aincw=1, aincr=0) - for i in range(0, len(buf), 4): self.nvdev.NV_PFSP_EMEMD[0].write(int.from_bytes(buf[i:i+4], 'little')) - - self.nvdev.NV_PFSP_QUEUE_TAIL[0].write(len(buf) - 4) - self.nvdev.NV_PFSP_QUEUE_HEAD[0].write(0) - - # Waiting for a response - wait_cond(lambda: self.nvdev.NV_PFSP_MSGQ_HEAD[0].read() != self.nvdev.NV_PFSP_MSGQ_TAIL[0].read(), msg="FSP didn't respond to message") - - self.nvdev.NV_PFSP_EMEMC[0].write(offs=0, blk=0, aincw=0, aincr=1) - self.nvdev.NV_PFSP_MSGQ_TAIL[0].write(self.nvdev.NV_PFSP_MSGQ_HEAD[0].read()) - class NV_GSP(NV_IP): def init_sw(self): self.handle_gen = itertools.count(0xcf000000) @@ -316,12 +254,6 @@ class NV_GSP(NV_IP): self.rpc_set_gsp_system_info() self.rpc_set_registry_table() - self.gpfifo_class, self.compute_class, self.dma_class = nv_gpu.AMPERE_CHANNEL_GPFIFO_A, nv_gpu.AMPERE_COMPUTE_B, nv_gpu.AMPERE_DMA_COPY_B - match self.nvdev.chip_name[:2]: - case "AD": self.compute_class = nv_gpu.ADA_COMPUTE_A - case "GB": - self.gpfifo_class,self.compute_class,self.dma_class=nv_gpu.BLACKWELL_CHANNEL_GPFIFO_A,nv_gpu.BLACKWELL_COMPUTE_B,nv_gpu.BLACKWELL_DMA_COPY_B - def init_rm_args(self, queue_size=0x40000): # Alloc queues pte_cnt = ((queue_pte_cnt:=(queue_size * 2) // 0x1000)) + round_up(queue_pte_cnt * 8, 0x1000) // 0x1000 @@ -391,28 +323,23 @@ class NV_GSP(NV_IP): self.init_gsp_image() self.init_boot_binary_image() - common = {'sizeOfBootloader':(boot_sz:=len(self.booter_image)), 'sysmemAddrOfBootloader':self.booter_sysmem[0], - 'sizeOfRadix3Elf':(radix3_sz:=len(self.gsp_image)), 'sysmemAddrOfRadix3Elf': self.gsp_radix3_sysmem[0], - 'sizeOfSignature': 0x1000, 'sysmemAddrOfSignature': self.gsp_signature_sysmem[0], - 'bootloaderCodeOffset': self.booter_desc.monitorCodeOffset, 'bootloaderDataOffset': self.booter_desc.monitorDataOffset, - 'bootloaderManifestOffset': self.booter_desc.manifestOffset, 'revision':nv.GSP_FW_WPR_META_REVISION, 'magic':nv.GSP_FW_WPR_META_MAGIC} - - if self.nvdev.fmc_boot: - m = nv.GspFwWprMeta(**common, vgaWorkspaceSize=0x20000, pmuReservedSize=0x1820000, nonWprHeapSize=0x220000, gspFwHeapSize=0x8700000, - frtsSize=0x100000) - else: - m = nv.GspFwWprMeta(**common, vgaWorkspaceSize=(vga_sz:=0x100000), vgaWorkspaceOffset=(vga_off:=self.nvdev.vram_size-vga_sz), - gspFwWprEnd=vga_off, frtsSize=(frts_sz:=0x100000), frtsOffset=(frts_off:=vga_off-frts_sz), bootBinOffset=(boot_off:=frts_off-boot_sz), - gspFwOffset=(gsp_off:=round_down(boot_off-radix3_sz, 0x10000)), gspFwHeapSize=(gsp_heap_sz:=0x8100000), fbSize=self.nvdev.vram_size, - gspFwHeapOffset=(gsp_heap_off:=round_down(gsp_off-gsp_heap_sz, 0x100000)), gspFwWprStart=(wpr_st:=round_down(gsp_heap_off-0x1000, 0x100000)), - nonWprHeapSize=(non_wpr_sz:=0x100000), nonWprHeapOffset=(non_wpr_off:=round_down(wpr_st-non_wpr_sz, 0x100000)), gspFwRsvdStart=non_wpr_off) - assert self.nvdev.flcn.frts_offset == m.frtsOffset, f"FRTS mismatch: {self.nvdev.flcn.frts_offset} != {m.frtsOffset}" + m = nv.GspFwWprMeta(revision=nv.GSP_FW_WPR_META_REVISION, magic=nv.GSP_FW_WPR_META_MAGIC, + fbSize=self.nvdev.vram_size, vgaWorkspaceSize=(vga_sz:=0x100000), vgaWorkspaceOffset=(vga_off:=self.nvdev.vram_size-vga_sz), + sizeOfRadix3Elf=(radix3_sz:=len(self.gsp_image)), gspFwWprEnd=vga_off, frtsSize=(frts_sz:=0x100000), frtsOffset=(frts_off:=vga_off-frts_sz), + sizeOfBootloader=(boot_sz:=len(self.booter_image)), bootBinOffset=(boot_off:=frts_off-boot_sz), + gspFwOffset=(gsp_off:=round_down(boot_off-radix3_sz, 0x10000)), gspFwHeapSize=(gsp_heap_sz:=0x8100000), + gspFwHeapOffset=(gsp_heap_off:=round_down(gsp_off-gsp_heap_sz, 0x100000)), gspFwWprStart=(wpr_start:=round_down(gsp_heap_off-0x1000, 0x100000)), + nonWprHeapSize=(non_wpr_sz:=0x100000), nonWprHeapOffset=(non_wpr_off:=round_down(wpr_start-non_wpr_sz, 0x100000)), gspFwRsvdStart=non_wpr_off, + sysmemAddrOfRadix3Elf=self.gsp_radix3_sysmem[0],sysmemAddrOfBootloader=self.booter_sysmem[0],sysmemAddrOfSignature=self.gsp_signature_sysmem[0], + bootloaderCodeOffset=self.booter_desc.monitorCodeOffset, bootloaderDataOffset=self.booter_desc.monitorDataOffset, + bootloaderManifestOffset=self.booter_desc.manifestOffset, sizeOfSignature=0x1000) self.wpr_meta, self.wpr_meta_sysmem = self.nvdev._alloc_boot_struct(m) + assert self.nvdev.flcn.frts_offset == self.wpr_meta.frtsOffset, f"FRTS mismatch: {self.nvdev.flcn.frts_offset} != {self.wpr_meta.frtsOffset}" - def promote_ctx(self, client:int, subdevice:int, obj:int, ctxbufs:dict[int, GRBufDesc], bufs=None, virt=None, phys=None): + def promote_ctx(self, client, subdevice, obj, ctxbufs, bufs=None, virt=None, phys=None): res, prom = {}, nv_gpu.NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS(entryCount=len(ctxbufs), engineType=0x1, hChanClient=client, hObject=obj) for i,(buf,desc) in enumerate(ctxbufs.items()): - use_v, use_p = (desc.virt if virt is None else virt), (desc.phys if phys is None else phys) + use_v, use_p = (desc.v if virt is None else virt), (desc.p if phys is None else phys) x = (bufs or {}).get(buf, self.nvdev.mm.valloc(desc.size, contiguous=True)) # allocate buffers prom.promoteEntry[i] = nv_gpu.NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY(bufferId=buf, gpuVirtAddr=x.va_addr if use_v else 0, bInitialize=use_p, gpuPhysAddr=x.paddrs[0][0] if use_p else 0, size=desc.size if use_p else 0, physAttr=0x4 if use_p else 0, bNonmapped=(use_p and not use_v)) @@ -427,37 +354,29 @@ class NV_GSP(NV_IP): vaspace = self.rpc_rm_alloc(hParent=dev, hClass=nv_gpu.FERMI_VASPACE_A, params=nv_gpu.NV_VASPACE_ALLOCATION_PARAMETERS()) # reserve 512MB for the reserved PDES - res_va = self.nvdev.mm.alloc_vaddr(res_sz:=(512 << 20)) + res_va = self.nvdev.mm.alloc_vaddr(512 << 20) - bufs_p = nv_gpu.struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS(pageSize=res_sz, numLevelsToCopy=3, - virtAddrLo=res_va, virtAddrHi=res_va + res_sz - 1) - for i,pt in enumerate(self.nvdev.mm.page_tables(res_va, size=res_sz)): - bufs_p.levels[i] = nv_gpu.struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0(physAddress=pt.paddr, - size=self.nvdev.mm.pte_cnt[0] * 8 if i == 0 else 0x1000, pageShift=self.nvdev.mm.pte_covers[i].bit_length() - 1, aperture=1) - self.rpc_rm_control(hObject=vaspace, cmd=nv_gpu.NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES, params=bufs_p) + bufs_p = nv_gpu.struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS(pageSize=(512<<20), numLevelsToCopy=3, + virtAddrLo=res_va, virtAddrHi=res_va+(512<<20)-1) + for i,pt in enumerate(self.nvdev.mm.page_tables(res_va, size=512<<20)[:3]): + bufs_p.levels[i] = nv_gpu.struct_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_0(physAddress=pt.paddr, size=0x20 if i == 0 else 0x1000, + pageShift=47 - (9 * i), aperture=1) + self.rpc_rm_control(hObject=vaspace, cmd=0x90f10106, params=bufs_p) - gpfifo_area = self.nvdev.mm.valloc(4 << 10, contiguous=True) - userd = nv_gpu.NV_MEMORY_DESC_PARAMS(base=gpfifo_area.paddrs[0][0] + 0x20 * 8, size=0x20, addressSpace=2, cacheAttrib=0) + gpfifo_area = self.nvdev.mm.valloc(2<<20, contiguous=True) + userd = nv_gpu.NV_MEMORY_DESC_PARAMS(base=gpfifo_area.paddrs[0][0] + 0x400 * 8, size=0x400, addressSpace=2, cacheAttrib=0) gg_params = nv_gpu.NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS(gpFifoOffset=gpfifo_area.va_addr, gpFifoEntries=32, engineType=0x1, cid=3, - hVASpace=vaspace, userdOffset=(ctypes.c_uint64*8)(0x20 * 8), userdMem=userd, internalFlags=0x1a, flags=0x200320) - ch_gpfifo = self.rpc_rm_alloc(hParent=dev, hClass=self.gpfifo_class, params=gg_params) + hVASpace=vaspace, userdOffset=(ctypes.c_uint64*8)(0x400 * 8), userdMem=userd, internalFlags=0x1a, flags=0x200320) + ch_gpfifo = self.rpc_rm_alloc(hParent=dev, hClass=nv_gpu.AMPERE_CHANNEL_GPFIFO_A, params=gg_params) - gr_ctx_bufs_info = self.rpc_rm_control(hObject=subdev, cmd=nv_gpu.NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO, - params=nv_gpu.NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS()).engineContextBuffersInfo[0] - def _ctx_info(idx, add=0, align=None): return round_up(gr_ctx_bufs_info.engine[idx].size + add, align or gr_ctx_bufs_info.engine[idx].alignment) + self.grctx_bufs = {0: GRBufDesc(0x237000, p=1, v=1), 1: GRBufDesc(0x6000, p=1, v=1, lc=1), 2: GRBufDesc(0x6000, p=1, v=1), + 3: GRBufDesc(0x3000, p=0, v=1), 4: GRBufDesc(0x20000, p=0, v=1), 5: GRBufDesc(0x2600000, p=0, v=1), 6: GRBufDesc(0x80000, p=0, v=1), + 9: GRBufDesc(0x10000, p=1, v=1), 10: GRBufDesc(0x80000, p=1, v=0), 11: GRBufDesc(0x80000, p=1, v=1)} - # Setup graphics context - gr_size = _ctx_info(nv_gpu.NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS, add=0x40000) - patch_size = _ctx_info(nv_gpu.NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH) - cfgs_sizes = {x: _ctx_info(x + 14, align=(2 << 20) if x == 5 else None) for x in range(3, 11)} # indices 3–10 are mapped to 17–24 - self.grctx_bufs = {0: GRBufDesc(gr_size, phys=True, virt=True), 1: GRBufDesc(patch_size, phys=True, virt=True, local=True), - 2: GRBufDesc(patch_size, phys=True, virt=True), **{x: GRBufDesc(cfgs_sizes[x], phys=False, virt=True) for x in range(3, 7)}, - 9: GRBufDesc(cfgs_sizes[9], phys=True, virt=True), 10: GRBufDesc(cfgs_sizes[10], phys=True, virt=False), - 11: GRBufDesc(cfgs_sizes[10], phys=True, virt=True)} # NOTE: 11 reuses cfgs_sizes[10] - self.promote_ctx(self.priv_root, subdev, ch_gpfifo, {k:v for k, v in self.grctx_bufs.items() if not v.local}) + self.promote_ctx(self.priv_root, subdev, ch_gpfifo, {k:v for k, v in self.grctx_bufs.items() if v.lc == 0}) - self.rpc_rm_alloc(hParent=ch_gpfifo, hClass=self.compute_class, params=None) - self.rpc_rm_alloc(hParent=ch_gpfifo, hClass=self.dma_class, params=None) + self.rpc_rm_alloc(hParent=ch_gpfifo, hClass=nv_gpu.ADA_COMPUTE_A, params=None) + self.rpc_rm_alloc(hParent=ch_gpfifo, hClass=nv_gpu.AMPERE_DMA_COPY_B, params=None) def init_hw(self): self.stat_q = NVRpcQueue(self, self.stat_q_va, self.cmd_q_va) @@ -466,17 +385,13 @@ class NV_GSP(NV_IP): self.stat_q.wait_resp(nv.NV_VGPU_MSG_EVENT_GSP_INIT_DONE) self.nvdev.NV_PBUS_BAR1_BLOCK.write(mode=0, target=0, ptr=0) - if self.nvdev.fmc_boot: self.nvdev.NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR.write(mode=0, target=0, ptr=0) - self.priv_root = 0xc1e00004 self.init_golden_image() - def fini_hw(self): self.rpc_unloading_guest_driver() - ### RPCs - def rpc_rm_alloc(self, hParent:int, hClass:int, params:Any, client=None) -> int: - if hClass == self.gpfifo_class: + def rpc_rm_alloc(self, hParent, hClass, params, client=None) -> int: + if hClass == nv_gpu.AMPERE_CHANNEL_GPFIFO_A: ramfc_alloc = self.nvdev.mm.valloc(0x1000, contiguous=True) params.ramfcMem = nv_gpu.NV_MEMORY_DESC_PARAMS(base=ramfc_alloc.paddrs[0][0], size=0x200, addressSpace=2, cacheAttrib=0) params.instanceMem = nv_gpu.NV_MEMORY_DESC_PARAMS(base=ramfc_alloc.paddrs[0][0], size=0x1000, addressSpace=2, cacheAttrib=0) @@ -496,27 +411,21 @@ class NV_GSP(NV_IP): if hClass == nv_gpu.FERMI_VASPACE_A and client != self.priv_root: self.rpc_set_page_directory(device=hParent, hVASpace=obj, pdir_paddr=self.nvdev.mm.root_page_table.paddr, client=client) if hClass == nv_gpu.NV20_SUBDEVICE_0: self.subdevice = obj # save subdevice handle - if hClass == self.compute_class and client != self.priv_root: + if hClass == nv_gpu.ADA_COMPUTE_A and client != self.priv_root: phys_gr_ctx = self.promote_ctx(client, self.subdevice, hParent, {k:v for k,v in self.grctx_bufs.items() if k in [0, 1, 2]}, virt=False) self.promote_ctx(client, self.subdevice, hParent, {k:v for k,v in self.grctx_bufs.items() if k in [0, 1, 2]}, phys_gr_ctx, phys=False) return obj if hClass != nv_gpu.NV1_ROOT else client - def rpc_rm_control(self, hObject:int, cmd:int, params:Any, client=None): + def rpc_rm_control(self, hObject, cmd, params, client=None): control_args = nv.rpc_gsp_rm_control_v(hClient=(client:=client or self.priv_root), hObject=hObject, cmd=cmd, flags=0x0, paramsSize=ctypes.sizeof(params) if params is not None else 0x0) self.cmd_q.send_rpc(nv.NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL, bytes(control_args) + (bytes(params) if params is not None else b'')) - res = self.stat_q.wait_resp(nv.NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL) - st = type(params).from_buffer_copy(res[len(bytes(control_args)):]) if params is not None else None + return self.stat_q.wait_resp(nv.NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL)[len(bytes(control_args)):] - # NOTE: gb20x requires the enable bit for token submission. Patch workSubmitToken here to maintain userspace compatibility. - if self.nvdev.chip_name.startswith("GB2") and cmd == nv_gpu.NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN: - cast(nv_gpu.NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS, st).workSubmitToken |= (1 << 30) - return st - - def rpc_set_page_directory(self, device:int, hVASpace:int, pdir_paddr:int, client=None, pasid=0xffffffff): + def rpc_set_page_directory(self, device, hVASpace, pdir_paddr, client=None): params = nv.struct_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05(physAddress=pdir_paddr, - numEntries=self.nvdev.mm.pte_cnt[0], flags=0x8, hVASpace=hVASpace, pasid=pasid, subDeviceId=1, chId=0) # flags field is all channels. - alloc_args = nv.rpc_set_page_directory_v(hClient=client or self.priv_root, hDevice=device, pasid=pasid, params=params) + numEntries=self.nvdev.mm.pte_cnt[0], flags=0x8, hVASpace=hVASpace, pasid=0xffffffff, subDeviceId=1, chId=0) # flags field is all channels. + alloc_args = nv.rpc_set_page_directory_v(hClient=client or self.priv_root, hDevice=device, pasid=0xffffffff, params=params) self.cmd_q.send_rpc(nv.NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY, bytes(alloc_args)) self.stat_q.wait_resp(nv.NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY) @@ -524,15 +433,10 @@ class NV_GSP(NV_IP): def bdf_as_int(s): return (int(s[5:7],16)<<8) | (int(s[8:10],16)<<3) | int(s[-1],16) data = nv.GspSystemInfo(gpuPhysAddr=self.nvdev.bars[0][0], gpuPhysFbAddr=self.nvdev.bars[1][0], gpuPhysInstAddr=self.nvdev.bars[3][0], - pciConfigMirrorBase=[0x88000, 0x92000][self.nvdev.fmc_boot], pciConfigMirrorSize=0x1000, nvDomainBusDeviceFunc=bdf_as_int(self.nvdev.devfmt), - bIsPassthru=1, PCIDeviceID=self.nvdev.venid, PCISubDeviceID=self.nvdev.subvenid, PCIRevisionID=self.nvdev.rev, maxUserVa=0x7ffffffff000) + pciConfigMirrorBase=0x88000, pciConfigMirrorSize=0x1000, nvDomainBusDeviceFunc=bdf_as_int(self.nvdev.devfmt), bIsPassthru=1, + PCIDeviceID=self.nvdev.venid, PCISubDeviceID=self.nvdev.subvenid, PCIRevisionID=self.nvdev.rev, maxUserVa=0x7ffffffff000) self.cmd_q.send_rpc(nv.NV_VGPU_MSG_FUNCTION_GSP_SET_SYSTEM_INFO, bytes(data)) - def rpc_unloading_guest_driver(self): - data = nv.rpc_unloading_guest_driver_v(bInPMTransition=0, bGc6Entering=0, newLevel=(__GPU_STATE_FLAGS_FAST_UNLOAD:=1 << 6)) - self.cmd_q.send_rpc(nv.NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER, bytes(data)) - self.stat_q.wait_resp(nv.NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER) - def rpc_set_registry_table(self): table = {'RMForcePcieConfigSave': 0x1, 'RMSecBusResetEnable': 0x1} entries_bytes, data_bytes = bytes(), bytes() @@ -546,7 +450,7 @@ class NV_GSP(NV_IP): header = nv.PACKED_REGISTRY_TABLE(size=hdr_size + len(entries_bytes) + len(data_bytes), numEntries=len(table)) self.cmd_q.send_rpc(nv.NV_VGPU_MSG_FUNCTION_SET_REGISTRY, bytes(header) + entries_bytes + data_bytes) - def run_cpu_seq(self, seq_buf:memoryview): + def run_cpu_seq(self, seq_buf): hdr = nv.rpc_run_cpu_sequencer_v17_00.from_address(mv_address(seq_buf)) cmd_iter = iter(seq_buf[ctypes.sizeof(nv.rpc_run_cpu_sequencer_v17_00):].cast('I')[:hdr.cmdIndex]) @@ -557,7 +461,7 @@ class NV_GSP(NV_IP): self.nvdev.wreg(addr, (self.nvdev.rreg(addr) & ~mask) | (val & mask)) elif op == 0x2: # reg poll addr, mask, val, _, _ = next(cmd_iter), next(cmd_iter), next(cmd_iter), next(cmd_iter), next(cmd_iter) - wait_cond(lambda: (self.nvdev.rreg(addr) & mask), value=val, msg=f"Register {addr:#x} not equal to {val:#x} after polling") + while (self.nvdev.rreg(addr) & mask) != val: pass elif op == 0x3: time.sleep(next(cmd_iter) / 1e6) # delay us elif op == 0x4: # save reg addr, index = next(cmd_iter), next(cmd_iter) @@ -574,7 +478,7 @@ class NV_GSP(NV_IP): self.nvdev.NV_PGSP_FALCON_MAILBOX1.write(hi32(self.libos_args_sysmem[0])) self.nvdev.flcn.start_cpu(self.nvdev.flcn.sec2) - wait_cond(lambda: self.nvdev.NV_PGC6_BSI_SECURE_SCRATCH_14.read_bitfields()['boot_stage_3_handoff'], msg="SEC2 didn't hand off") + while self.nvdev.NV_PGC6_BSI_SECURE_SCRATCH_14.read_bitfields()['boot_stage_3_handoff'] == 0: pass mailbox = self.nvdev.NV_PFALCON_FALCON_MAILBOX0.with_base(self.nvdev.flcn.sec2).read() assert mailbox == 0x0, f"Falcon SEC2 failed to execute, mailbox is {mailbox:08x}" diff --git a/tinygrad_repo/tinygrad/runtime/support/nv/nvdev.py b/tinygrad_repo/tinygrad/runtime/support/nv/nvdev.py index 6831b5e8b..bb7adc05f 100644 --- a/tinygrad_repo/tinygrad/runtime/support/nv/nvdev.py +++ b/tinygrad_repo/tinygrad/runtime/support/nv/nvdev.py @@ -3,7 +3,7 @@ import ctypes, time, functools, re, gzip, struct from tinygrad.helpers import getenv, DEBUG, fetch, getbits, to_mv from tinygrad.runtime.support.hcq import MMIOInterface from tinygrad.runtime.support.memory import TLSFAllocator, MemoryManager -from tinygrad.runtime.support.nv.ip import NV_FLCN, NV_FLCN_COT, NV_GSP +from tinygrad.runtime.support.nv.ip import NV_FLCN, NV_GSP from tinygrad.runtime.support.system import System, PCIDevImplBase NV_DEBUG = getenv("NV_DEBUG", 0) @@ -32,46 +32,40 @@ class NVReg: class NVPageTableEntry: def __init__(self, nvdev, paddr, lv): self.nvdev, self.paddr, self.lv, self.entries = nvdev, paddr, lv, nvdev.vram.view(paddr, 0x1000, fmt='Q') - def _is_dual_pde(self) -> bool: return self.lv == self.nvdev.mm.level_cnt - 2 - def set_entry(self, entry_id:int, paddr:int, table=False, uncached=False, system=False, snooped=False, frag=0, valid=True): if not table: - x = self.nvdev.pte_t.encode(valid=valid, address_sys=paddr >> 12, aperture=2 if system else 0, kind=6, - **({'pcf': int(uncached)} if self.nvdev.mmu_ver == 3 else {'vol': uncached})) + x = self.nvdev.NV_MMU_VER2_PTE.encode(valid=valid, address_sys=paddr >> 12, aperture=2 if system else 0, vol=uncached, kind=6) + elif self.lv == 3: + x = self.nvdev.NV_MMU_VER2_DUAL_PDE.encode(is_pte=False, address_small_sys=paddr >> 12, aperture_small=1 if valid else 0, vol_small=0, no_ats=1) else: - pde = self.nvdev.dual_pde_t if self._is_dual_pde() else self.nvdev.pde_t - small, sys = ("_small" if self._is_dual_pde() else ""), "" if self.nvdev.mmu_ver == 3 else "_sys" - x = pde.encode(is_pte=False, **{f'aperture{small}': 1 if valid else 0, f'address{small}{sys}': paddr >> 12}, - **({f'pcf{small}': 0b10} if self.nvdev.mmu_ver == 3 else {'no_ats': 1})) + x = self.nvdev.NV_MMU_VER2_PDE.encode(is_pte=False, address_sys=paddr >> 12, aperture=1 if valid else 0, vol=0, no_ats=1) - if self._is_dual_pde(): self.entries[2*entry_id], self.entries[2*entry_id+1] = x & 0xffffffffffffffff, x >> 64 - else: self.entries[entry_id] = x + if self.lv != 3: self.entries[entry_id] = x + else: + self.entries[2*entry_id] = x & 0xffffffffffffffff + self.entries[2*entry_id+1] = x >> 64 - def entry(self, entry_id:int) -> int: - return (self.entries[2*entry_id+1]<<64) | self.entries[2*entry_id] if self._is_dual_pde() else self.entries[entry_id] + def entry(self, entry_id:int) -> int: return (self.entries[2*entry_id+1]<<64) | self.entries[2*entry_id] if self.lv == 3 else self.entries[entry_id] def read_fields(self, entry_id:int) -> dict: - if self.is_page(entry_id): return self.nvdev.pte_t.decode(self.entry(entry_id)) - return (self.nvdev.dual_pde_t if self._is_dual_pde() else self.nvdev.pde_t).decode(self.entry(entry_id)) + if self.is_pte(entry_id): return self.nvdev.NV_MMU_VER2_PTE.decode(self.entry(entry_id)) + return (self.nvdev.NV_MMU_VER2_DUAL_PDE if self.lv == 3 else self.nvdev.NV_MMU_VER2_PDE).decode(self.entry(entry_id)) - def is_page(self, entry_id) -> bool: return (self.entry(entry_id) & 1 == 1) if self.lv < self.nvdev.mm.level_cnt - 1 else True - def supports_huge_page(self, paddr:int): return self.lv >= self.nvdev.mm.level_cnt - 3 and paddr % self.nvdev.mm.pte_covers[self.lv] == 0 + def is_pte(self, entry_id) -> bool: return (self.entry(entry_id) & 1 == 1) if self.lv <= 3 else True def valid(self, entry_id): - if self.is_page(entry_id): return self.read_fields(entry_id)['valid'] - return self.read_fields(entry_id)['aperture_small' if self._is_dual_pde() else 'aperture'] != 0 + if self.is_pte(entry_id): return self.read_fields(entry_id)['valid'] + return self.read_fields(entry_id)['aperture_small' if self.lv == 3 else 'aperture'] != 0 - def address(self, entry_id:int) -> int: - small, sys = ("_small" if self._is_dual_pde() else ""), "_sys" if self.nvdev.mmu_ver == 2 or self.lv == self.nvdev.mm.level_cnt - 1 else "" - return self.read_fields(entry_id)[f'address{small}{sys}'] << 12 + def address(self, entry_id:int) -> int: return self.read_fields(entry_id)['address_small_sys' if self.lv == 3 else 'address_sys'] << 12 class NVMemoryManager(MemoryManager): - va_allocator = TLSFAllocator((1 << 44), base=0x1000000000) # global for all devices. + va_allocator = TLSFAllocator((1 << 44), base=1 << 30) # global for all devices. def on_range_mapped(self): self.dev.NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE.write((1 << 0) | (1 << 1) | (1 << 6) | (1 << 31)) class NVDev(PCIDevImplBase): - def __init__(self, devfmt:str, mmio:MMIOInterface, vram:MMIOInterface, venid:int, subvenid:int, rev:int, bars:dict): + def __init__(self, devfmt, mmio:MMIOInterface, vram:MMIOInterface, venid:int, subvenid:int, rev:int, bars:dict): self.devfmt, self.mmio, self.vram, self.venid, self.subvenid, self.rev, self.bars = devfmt, mmio, vram, venid, subvenid, rev, bars self.lock_fd = System.flock_acquire(f"nv_{self.devfmt}.lock") @@ -79,16 +73,14 @@ class NVDev(PCIDevImplBase): self._early_init() # UVM depth HW level VA bits - # 0 PDE4 56:56 (hopper+) - # 1 PDE3 55:47 - # 2 PDE2 46:38 - # 3 PDE1 (or 512M PTE) 37:29 - # 4 PDE0 (dual 64k/4k PDE, or 2M PTE) 28:21 - # 5 PTE_64K / PTE_4K 20:16 / 20:12 - bits, shifts = (56, [12, 21, 29, 38, 47, 56]) if self.mmu_ver == 3 else (48, [12, 21, 29, 38, 47]) - self.mm = NVMemoryManager(self, self.vram_size, boot_size=(2 << 20), pt_t=NVPageTableEntry, va_bits=bits, va_shifts=shifts, va_base=0, - palloc_ranges=[(x, x) for x in [512 << 20, 2 << 20, 4 << 10]]) - self.flcn:NV_FLCN|NV_FLCN_COT = NV_FLCN_COT(self) if self.fmc_boot else NV_FLCN(self) + # 0 PDE3 48:47 + # 1 PDE2 46:38 + # 2 PDE1 (or 512M PTE) 37:29 + # 3 PDE0 (dual 64k/4k PDE, or 2M PTE) 28:21 + # 4 PTE_64K / PTE_4K 20:16 / 20:12 + self.mm = NVMemoryManager(self, self.vram_size, boot_size=(2 << 20), pt_t=NVPageTableEntry, pte_cnt=[4, 512, 512, 256, 512], + pte_covers=[0x800000000000, 0x4000000000, 0x20000000, 0x200000, 0x1000], first_lv=0, first_page_lv=4, va_base=0) + self.flcn:NV_FLCN = NV_FLCN(self) self.gsp:NV_GSP = NV_GSP(self) # Turn the booting early, gsp client is loaded from the clean. @@ -97,14 +89,11 @@ class NVDev(PCIDevImplBase): for ip in [self.flcn, self.gsp]: ip.init_sw() for ip in [self.flcn, self.gsp]: ip.init_hw() - def fini(self): - for ip in [self.gsp, self.flcn]: ip.fini_hw() - def reg(self, reg:str) -> NVReg: return self.__dict__[reg] - def wreg(self, addr:int, value:int): + def wreg(self, addr, value): self.mmio[addr // 4] = value if NV_DEBUG >= 4: print(f"wreg: {hex(addr)} = {hex(value)}") - def rreg(self, addr:int) -> int: return self.mmio[addr // 4] + def rreg(self, addr): return self.mmio[addr // 4] def _early_init(self): self.reg_names:set[str] = set() @@ -113,12 +102,11 @@ class NVDev(PCIDevImplBase): self.include("src/common/inc/swref/published/nv_ref.h") self.chip_id = self.reg("NV_PMC_BOOT_0").read() self.chip_details = self.reg("NV_PMC_BOOT_42").read_bitfields() - self.chip_name = {0x17: "GA1", 0x19: "AD1", 0x1b: "GB2"}[self.chip_details['architecture']] + f"{self.chip_details['implementation']:02d}" - self.mmu_ver, self.fmc_boot = (3, True) if self.chip_details['architecture'] >= 0x1a else (2, False) + self.chip_name = {0x17: "GA", 0x19: "AD"}[self.chip_details['architecture']] + str(100+self.chip_details['implementation']) self.include("src/common/inc/swref/published/turing/tu102/dev_fb.h") if self.reg("NV_PFB_PRI_MMU_WPR2_ADDR_HI").read() != 0: - if DEBUG >= 2: print(f"nv {self.devfmt}: WPR2 is up. Issuing a full reset.", flush=True) + if DEBUG >= 2: print(f"nv {self.devfmt}: WPR2 is up. Issuing a full reset.") System.pci_reset(self.devfmt) time.sleep(0.5) @@ -127,20 +115,19 @@ class NVDev(PCIDevImplBase): self.include("src/common/inc/swref/published/ampere/ga102/dev_gc6_island_addendum.h") # MMU Init - self.reg_names.update(mmu_pd_names:=[f'NV_MMU_VER{self.mmu_ver}_PTE', f'NV_MMU_VER{self.mmu_ver}_PDE', f'NV_MMU_VER{self.mmu_ver}_DUAL_PDE']) - for name in mmu_pd_names: self.__dict__[name] = NVReg(self, None, None, fields={}) - self.include(f"kernel-open/nvidia-uvm/hwref/{'hopper/gh100' if self.mmu_ver == 3 else 'turing/tu102'}/dev_mmu.h") - self.pte_t, self.pde_t, self.dual_pde_t = tuple([self.__dict__[name] for name in mmu_pd_names]) + self.reg_names.update(['NV_MMU_VER2_PTE', 'NV_MMU_VER2_PDE', 'NV_MMU_VER2_DUAL_PDE']) + for name in ['NV_MMU_VER2_PTE', 'NV_MMU_VER2_PDE', 'NV_MMU_VER2_DUAL_PDE']: self.__dict__[name] = NVReg(self, None, None, fields={}) + self.include("kernel-open/nvidia-uvm/hwref/turing/tu102/dev_mmu.h") self.vram_size = self.reg("NV_PGC6_AON_SECURE_SCRATCH_GROUP_42").read() << 20 - def _alloc_boot_struct(self, struct:ctypes.Structure) -> tuple[ctypes.Structure, int]: + def _alloc_boot_struct(self, struct): va, paddrs = System.alloc_sysmem(sz:=ctypes.sizeof(type(struct)), contiguous=True) to_mv(va, sz)[:] = bytes(struct) - return type(struct).from_address(va), paddrs[0] + return struct, paddrs[0] - def _download(self, file:str) -> str: - url = f"https://raw.githubusercontent.com/NVIDIA/open-gpu-kernel-modules/8ec351aeb96a93a4bb69ccc12a542bf8a8df2b6f/{file}" + def _download(self, file) -> str: + url = f"https://raw.githubusercontent.com/NVIDIA/open-gpu-kernel-modules/e8113f665d936d9f30a6d508f3bacd1e148539be/{file}" return fetch(url, subdir="defines").read_text() def extract_fw(self, file:str, dname:str) -> bytes: @@ -152,7 +139,7 @@ class NVDev(PCIDevImplBase): return gzip.decompress(struct.pack("<4BL2B", 0x1f, 0x8b, 8, 0, 0, 0, 3) + image) if "COMPRESSION: YES" in info else image def include(self, file:str): - regs_off = {'NV_PFALCON_FALCON': 0x0, 'NV_PGSP_FALCON': 0x0, 'NV_PSEC_FALCON': 0x0, 'NV_PRISCV_RISCV': 0x1000, 'NV_PGC6_AON': 0x0, 'NV_PFSP': 0x0, + regs_off = {'NV_PFALCON_FALCON': 0x0, 'NV_PGSP_FALCON': 0x0, 'NV_PSEC_FALCON': 0x0, 'NV_PRISCV_RISCV': 0x1000, 'NV_PGC6_AON': 0x0, 'NV_PGC6_BSI': 0x0, 'NV_PFALCON_FBIF': 0x600, 'NV_PFALCON2_FALCON': 0x1000, 'NV_PBUS': 0x0, 'NV_PFB': 0x0, 'NV_PMC': 0x0, 'NV_PGSP_QUEUE': 0x0, 'NV_VIRTUAL_FUNCTION':0xb80000} diff --git a/tinygrad_repo/tinygrad/runtime/support/system.py b/tinygrad_repo/tinygrad/runtime/support/system.py index 623886615..48d829a2e 100644 --- a/tinygrad_repo/tinygrad/runtime/support/system.py +++ b/tinygrad_repo/tinygrad/runtime/support/system.py @@ -1,8 +1,8 @@ -import os, mmap, array, functools, ctypes, select, contextlib, dataclasses, sys, errno -from typing import cast, ClassVar +import os, mmap, array, functools, ctypes, select, contextlib, dataclasses, sys, fcntl +from typing import cast from tinygrad.helpers import round_up, to_mv, getenv, OSX, temp from tinygrad.runtime.autogen import libc, vfio -from tinygrad.runtime.support.hcq import FileIOInterface, MMIOInterface, HCQBuffer +from tinygrad.runtime.support.hcq import FileIOInterface, MMIOInterface, HCQCompiled, HCQBuffer from tinygrad.runtime.support.memory import MemoryManager, VirtMapping MAP_FIXED, MAP_LOCKED, MAP_POPULATE, MAP_NORESERVE = 0x10, 0 if OSX else 0x2000, getattr(mmap, "MAP_POPULATE", 0 if OSX else 0x008000), 0x400 @@ -12,20 +12,16 @@ class _System: def memory_barrier(self): lib.atomic_thread_fence(__ATOMIC_SEQ_CST:=5) if (lib:=self.atomic_lib()) is not None else None - def lock_memory(self, addr:int, size:int): - if libc.mlock(ctypes.c_void_p(addr), size): raise RuntimeError(f"Failed to lock memory at {addr:#x} with size {size:#x}") - - def system_paddrs(self, vaddr:int, size:int) -> list[int]: - self.pagemap().seek(vaddr // mmap.PAGESIZE * 8) - return [(x & ((1<<55) - 1)) * mmap.PAGESIZE for x in array.array('Q', self.pagemap().read(size//mmap.PAGESIZE*8, binary=True))] - def alloc_sysmem(self, size:int, vaddr:int=0, contiguous:bool=False, data:bytes|None=None) -> tuple[int, list[int]]: assert not contiguous or size <= (2 << 20), "Contiguous allocation is only supported for sizes up to 2MB" flags = (libc.MAP_HUGETLB if contiguous and (size:=round_up(size, mmap.PAGESIZE)) > 0x1000 else 0) | (MAP_FIXED if vaddr else 0) va = FileIOInterface.anon_mmap(vaddr, size, mmap.PROT_READ|mmap.PROT_WRITE, mmap.MAP_SHARED|mmap.MAP_ANONYMOUS|MAP_POPULATE|MAP_LOCKED|flags, 0) if data is not None: to_mv(va, len(data))[:] = data - return va, self.system_paddrs(va, size) + + # Read pagemap to get the physical address of each page. The pages are locked. + self.pagemap().seek(va // mmap.PAGESIZE * 8) + return va, [(x & ((1<<55) - 1)) * mmap.PAGESIZE for x in array.array('Q', self.pagemap().read(size//mmap.PAGESIZE*8, binary=True))] def pci_reset(self, gpu): os.system(f"sudo sh -c 'echo 1 > /sys/bus/pci/devices/{gpu}/reset'") def pci_scan_bus(self, target_vendor:int, target_devices:list[int]) -> list[str]: @@ -59,8 +55,6 @@ class _System: except OSError: return None def flock_acquire(self, name:str) -> int: - import fcntl # to support windows - os.umask(0) # Set umask to 0 to allow creating files with 0666 permissions # Avoid O_CREAT because we don’t want to re-create/replace an existing file (triggers extra perms checks) when opening as non-owner. @@ -82,13 +76,9 @@ class PCIDevice: FileIOInterface(f"/sys/bus/pci/devices/{self.pcibus}/driver/unbind", os.O_WRONLY).write(self.pcibus) for i in resize_bars or []: - if FileIOInterface.exists(rpath:=f"/sys/bus/pci/devices/{self.pcibus}/resource{i}_resize"): - try: FileIOInterface(rpath, os.O_RDWR).write(str(int(FileIOInterface(rpath, os.O_RDONLY).read(), 16).bit_length() - 1)) - except OSError as e: - if e.errno in {errno.EPERM, errno.EACCES}: - raise RuntimeError(f"Cannot resize BAR {i}: {e}. Permission error: run `extra/amdpci/setup_python_cap.sh`" - " to allow python accessing device or run with sudo") from e - raise RuntimeError(f"Cannot resize BAR {i}: {e}. Ensure the resizable BAR option is enabled on your system.") from e + supported_sizes = int(FileIOInterface(f"/sys/bus/pci/devices/{self.pcibus}/resource{i}_resize", os.O_RDONLY).read(), 16) + try: FileIOInterface(f"/sys/bus/pci/devices/{self.pcibus}/resource{i}_resize", os.O_RDWR).write(str(supported_sizes.bit_length() - 1)) + except OSError as e: raise RuntimeError(f"Cannot resize BAR {i}: {e}. Ensure the resizable BAR option is enabled on your system.") from e if getenv("VFIO", 0) and (vfio_fd:=System.vfio()) is not None: FileIOInterface(f"/sys/bus/pci/devices/{self.pcibus}/driver_override", os.O_WRONLY).write("vfio-pci") @@ -127,21 +117,21 @@ class PCIDevImplBase: mm: MemoryManager @dataclasses.dataclass -class PCIAllocationMeta: mapping:VirtMapping; has_cpu_mapping:bool; hMemory:int=0 # noqa: E702 +class PCIAllocationMeta: owner:HCQCompiled; mapped_devs:list; mapping:VirtMapping; has_cpu_mapping:bool; hMemory:int=0 # noqa: E702 class PCIIfaceBase: dev_impl:PCIDevImplBase - gpus:ClassVar[list[str]] = [] + gpus:list[str] = [] def __init__(self, dev, dev_id, vendor, devices, bars, vram_bar, va_start, va_size): - if len((cls:=type(self)).gpus) == 0: - cls.gpus = System.pci_scan_bus(vendor, devices) + if len(PCIIfaceBase.gpus) == 0: + PCIIfaceBase.gpus = System.pci_scan_bus(vendor, devices) visible_devices = [int(x) for x in (getenv('VISIBLE_DEVICES', '')).split(',') if x.strip()] - cls.gpus = [cls.gpus[x] for x in visible_devices] if visible_devices else cls.gpus + PCIIfaceBase.gpus = [PCIIfaceBase.gpus[x] for x in visible_devices] if visible_devices else PCIIfaceBase.gpus # Acquire va range to avoid collisions. FileIOInterface.anon_mmap(va_start, va_size, 0, mmap.MAP_PRIVATE | mmap.MAP_ANONYMOUS | MAP_NORESERVE | MAP_FIXED, 0) - self.pci_dev, self.dev, self.vram_bar = PCIDevice(cls.gpus[dev_id], bars=bars, resize_bars=[vram_bar]), dev, vram_bar + self.pci_dev, self.dev, self.vram_bar = PCIDevice(PCIIfaceBase.gpus[dev_id], bars=bars, resize_bars=[vram_bar]), dev, vram_bar self.p2p_base_addr = self.pci_dev.bar_info[vram_bar][0] def alloc(self, size:int, host=False, uncached=False, cpu_access=False, contiguous=False, **kwargs) -> HCQBuffer: @@ -149,26 +139,23 @@ class PCIIfaceBase: vaddr = self.dev_impl.mm.alloc_vaddr(size:=round_up(size, mmap.PAGESIZE), align=mmap.PAGESIZE) paddrs = [(paddr, mmap.PAGESIZE) for paddr in System.alloc_sysmem(size, vaddr=vaddr, contiguous=contiguous)[1]] mapping = self.dev_impl.mm.map_range(vaddr, size, paddrs, system=True, snooped=True, uncached=True) - return HCQBuffer(vaddr, size, meta=PCIAllocationMeta(mapping, has_cpu_mapping=True, hMemory=paddrs[0][0]), - view=MMIOInterface(mapping.va_addr, size, fmt='B'), owner=self.dev) + return HCQBuffer(vaddr, size, meta=PCIAllocationMeta(self.dev, [self.dev], mapping, has_cpu_mapping=True, hMemory=paddrs[0][0]), + view=MMIOInterface(mapping.va_addr, size, fmt='B')) mapping = self.dev_impl.mm.valloc(size:=round_up(size, 4 << 10), uncached=uncached, contiguous=cpu_access) if cpu_access: self.pci_dev.map_bar(bar=self.vram_bar, off=mapping.paddrs[0][0], addr=mapping.va_addr, size=mapping.size) return HCQBuffer(mapping.va_addr, size, view=MMIOInterface(mapping.va_addr, size, fmt='B') if cpu_access else None, - meta=PCIAllocationMeta(mapping, has_cpu_mapping=cpu_access, hMemory=mapping.paddrs[0][0]), owner=self.dev) + meta=PCIAllocationMeta(self.dev, [self.dev], mapping, has_cpu_mapping=cpu_access, hMemory=mapping.paddrs[0][0])) def free(self, b:HCQBuffer): - for dev in b.mapped_devs[1:]: dev.iface.dev_impl.mm.unmap_range(b.va_addr, b.size) + for dev in b.meta.mapped_devs[1:]: dev.iface.dev_impl.mm.unmap_range(b.va_addr, b.size) if not b.meta.mapping.system: self.dev_impl.mm.vfree(b.meta.mapping) - if b.owner == self.dev and b.meta.has_cpu_mapping: FileIOInterface.munmap(b.va_addr, b.size) + if b.meta.owner == self.dev and b.meta.has_cpu_mapping: FileIOInterface.munmap(b.va_addr, b.size) def map(self, b:HCQBuffer): - if b.owner is not None and b.owner._is_cpu(): - System.lock_memory(cast(int, b.va_addr), b.size) - paddrs, snooped, uncached = [(x, 0x1000) for x in System.system_paddrs(cast(int, b.va_addr), round_up(b.size, 0x1000))], True, False - elif (ifa:=getattr(b.owner, "iface", None)) is not None and isinstance(ifa, PCIIfaceBase): - paddrs = [(paddr if b.meta.mapping.system else (paddr + ifa.p2p_base_addr), size) for paddr,size in b.meta.mapping.paddrs] - snooped, uncached = b.meta.mapping.snooped, b.meta.mapping.uncached - else: raise RuntimeError(f"map failed: {b.owner} -> {self.dev}") + # Check if the memory is already mapped on this device + if self.dev in b.meta.mapped_devs: return + b.meta.mapped_devs.append(self.dev) - self.dev_impl.mm.map_range(cast(int, b.va_addr), round_up(b.size, 0x1000), paddrs, system=True, snooped=snooped, uncached=uncached) + paddrs = [(paddr if b.meta.mapping.system else (paddr+b.meta.owner.iface.p2p_base_addr), size) for paddr,size in b.meta.mapping.paddrs] + self.dev_impl.mm.map_range(cast(int, b.va_addr), b.size, paddrs, system=True, snooped=b.meta.mapping.snooped, uncached=b.meta.mapping.uncached) diff --git a/tinygrad_repo/tinygrad/runtime/support/usb.py b/tinygrad_repo/tinygrad/runtime/support/usb.py index 285e3cf28..09b49204c 100644 --- a/tinygrad_repo/tinygrad/runtime/support/usb.py +++ b/tinygrad_repo/tinygrad/runtime/support/usb.py @@ -171,7 +171,7 @@ class ASM24Controller: if fmt_type == 0x60 and size == 4 and self._is_pci_cacheable(address) and self._pci_cache.get(address) == value: return [] assert fmt_type >> 8 == 0 and size > 0 and size <= 4, f"Invalid fmt_type {fmt_type} or size {size}" - if DEBUG >= 5: print("pcie_request", hex(fmt_type), hex(address), value, size) + if DEBUG >= 3: print("pcie_request", hex(fmt_type), hex(address), value, size) masked_address, offset = address & 0xFFFFFFFC, address & 0x3 assert size + offset <= 4 and (value is None or value >> (8 * size) == 0) diff --git a/tinygrad_repo/tinygrad/runtime/support/webgpu.py b/tinygrad_repo/tinygrad/runtime/support/webgpu.py index 11c6e1038..9b5362ee8 100644 --- a/tinygrad_repo/tinygrad/runtime/support/webgpu.py +++ b/tinygrad_repo/tinygrad/runtime/support/webgpu.py @@ -1,16 +1,10 @@ -import ctypes, ctypes.util, os, subprocess, platform, sysconfig +import ctypes, ctypes.util, os, subprocess, platform from tinygrad.helpers import OSX -WEBGPU_PATH: str | None - if OSX: if not os.path.exists(brew_prefix:=subprocess.check_output(['brew', '--prefix', 'dawn']).decode().strip()): raise FileNotFoundError('dawn library not found. Install it with `brew tap wpmed92/dawn && brew install dawn`') - WEBGPU_PATH = os.path.join(brew_prefix, 'lib', 'libwebgpu_dawn.dylib') -elif platform.system() == "Windows": - if not os.path.exists(pydawn_path:=os.path.join(sysconfig.get_paths()["purelib"], "pydawn")): - raise FileNotFoundError("dawn library not found. Install it with `pip install dawn-python`") - WEBGPU_PATH = os.path.join(pydawn_path, "lib", "libwebgpu_dawn.dll") + WEBGPU_PATH: str|None = os.path.join(brew_prefix, 'lib', 'libwebgpu_dawn.dylib') else: if (WEBGPU_PATH:=ctypes.util.find_library('webgpu_dawn')) is None: raise FileNotFoundError("dawn library not found. " + diff --git a/tinygrad_repo/tinygrad/schedule/rangeify.py b/tinygrad_repo/tinygrad/schedule/rangeify.py deleted file mode 100644 index 4a527edd5..000000000 --- a/tinygrad_repo/tinygrad/schedule/rangeify.py +++ /dev/null @@ -1,461 +0,0 @@ -from typing import Any -from dataclasses import dataclass, field -from tinygrad.dtype import dtypes, PtrDType, ImageDType, AddrSpace -from tinygrad.uop.ops import PatternMatcher, UPat, Ops, UOp, resolve, GroupOp, RewriteNotReady, _substitute -from tinygrad.helpers import argsort, prod, all_same, pluralize, getenv, RANGEIFY -from tinygrad.schedule.multi import multi_pm - -from tinygrad.schedule.kernelize import Kernel -from tinygrad.uop.ops import track_rewrites, graph_rewrite_map, graph_rewrite, identity_element, sint, AxisType - -# 0. do some cleanup rewrites, mostly copied from the old stuff - -double_reshape = PatternMatcher([ - # RESHAPE on RESHAPE is the second reshape - (UPat(Ops.RESHAPE, src=(UPat(Ops.RESHAPE),), name="x"), lambda x: x.replace(src=(x.src[0].src[0],))), -]) - -earliest_rewrites = double_reshape+PatternMatcher([ - # UOp with size 0 is zero - (UPat(GroupOp.All-{Ops.SINK}, name="root"), lambda root: root.const_like(0) if root.base.st is not None and root.size == 0 else None), - # DETACH and CONTIGUOUS_BACKWARD are NOOPs here, so is FUSE - (UPat((Ops.DETACH, Ops.CONTIGUOUS_BACKWARD, Ops.FUSE), name="x"), lambda x: x.src[0]), - # reduce of size 0 is the identity element - (UPat(Ops.REDUCE_AXIS, name="reduce", src=(UPat.var("x"),)), - lambda reduce,x: reduce.const_like(identity_element(reduce.arg[0], reduce.dtype)) if x.size == 0 and reduce.size != 0 else None), - # non shape changing RESHAPE is NOOP - (UPat(Ops.RESHAPE, name="x"), lambda x: x.src[0] if x.src[0].shape == x.arg else None), - # RESHAPE after COPY - (UPat(Ops.COPY, src=(UPat(Ops.RESHAPE, name="r"),UPat(name="d")), name="c"), lambda c,r,d: c.replace(src=(r.src[0],d)).reshape(r.arg)), - # TODO: this should be BUFFER_VIEW - (UPat(Ops.COPY, src=(UPat(Ops.SHRINK, name="r"),UPat(name="d")), name="c"), lambda c,r,d: c.replace(src=(r.src[0],d)).shrink(r.arg)), - # const hacks - (UPat(Ops.CONST, name="x"), lambda x: - x.replace(src=(x.src[0].src[0],)).reshape((1,)*len(x.shape)).expand(x.shape) if \ - len(x.src) and x.src[0].op is Ops.VIEW and not any(s == 0 for s in x.shape) else None), - # assign only to buffer - (UPat(Ops.ASSIGN, src=(UPat(GroupOp.All-{Ops.BUFFER}, name="target"), UPat(name="x"))), - lambda x,target: x if target.base.op is not Ops.BUFFER else None), - # contiguous/buffer/copy/assign is already contiguous - (UPat(Ops.CONTIGUOUS, name="root", src=(UPat((Ops.CONTIGUOUS, Ops.BUFFER, Ops.COPY, Ops.ASSIGN)),)), lambda root: root.src[0]), -]) - -# 1. add contiguous where we have to - -ALWAYS_CONTIGUOUS: set[Ops] = {Ops.CONTIGUOUS, Ops.ASSIGN, Ops.COPY, Ops.BUFFER, Ops.BUFFER_VIEW, - Ops.CONST, Ops.BIND, Ops.DEVICE, Ops.MSELECT, Ops.MSTACK, Ops.DEFINE_GLOBAL, - Ops.DEFINE_LOCAL, Ops.DEFINE_REG, Ops.LOAD} - -def realize(ctx:dict[UOp, None], tr:UOp) -> None: ctx[tr] = None - -def realize_parents(ctx:dict[UOp, None], rb:UOp) -> None: - for s in rb.src: - if s.op not in ALWAYS_CONTIGUOUS: ctx[s] = None - -def realize_assign(ctx:dict[UOp, None], a:UOp) -> None: - if a.src[1].op not in ALWAYS_CONTIGUOUS: ctx[a.src[1]] = None - -do_realize = PatternMatcher([ - # always realize SINK parents - (UPat(Ops.SINK, name="s"), lambda ctx,s: ctx.update((x.base, None) for x in s.src if x.base.op not in ALWAYS_CONTIGUOUS)), - # always realize ASSIGN/COPY/BUFFER_VIEW - (UPat({Ops.ASSIGN, Ops.COPY, Ops.BUFFER_VIEW}, name="tr"), realize), - # realize parents of COPY, MSELECT, MSTACK - (UPat((Ops.COPY, Ops.MSELECT, Ops.MSTACK), name="rb"), realize_parents), - # realize input to assign (might be optimized out) - (UPat(Ops.ASSIGN, name="a"), realize_assign), -]) - -add_contiguous = PatternMatcher([ - (UPat(GroupOp.All-{Ops.CONTIGUOUS}, name="x"), lambda ctx,x: x.replace(tag=1).contiguous() if x in ctx and x.tag is None else None), -]) -remove_tags = PatternMatcher([(UPat(GroupOp.All, name="x"), lambda x: x.replace(tag=None) if x.tag is not None else None)]) - -# 2. mark all children - -@dataclass -class ChildrenContext: children: dict[UOp, list[UOp]]|None = None -def extract_children(ctx:ChildrenContext, x:UOp): - if ctx.children is not None: return - children_map = x.get_children_map() - ctx.children = {} - for k,v in children_map.items(): - non_sink_children = [u for u in v if u.op is not Ops.SINK] - if len(non_sink_children) <= 1: continue - # NOTE: this gate shouldn't be here - if any(x.op is Ops.REDUCE_AXIS for x in k.toposort()) and any(x.op in {Ops.BUFFER, Ops.CONTIGUOUS} for x in k.toposort()): - ctx.children[k] = non_sink_children - -def mark_children(ctx:ChildrenContext, x:UOp): - assert ctx.children is not None - new_srcs = [(UOp(Ops.CHILD, s.dtype, src=(UOp(Ops.CHILDREN, s.dtype, (s,), arg=len(ctx.children[s])),), - arg=(ctx.children[s].index(x), len(ctx.children[s]))) if s in ctx.children else s) for s in x.src] - return x.replace(src=tuple(new_srcs)) - -pm_children = PatternMatcher([ - (UPat(Ops.SINK, name="x"), extract_children), - (UPat(GroupOp.All-{Ops.CHILD, Ops.CHILDREN}, name="x"), mark_children), -]) - -# 3. rangeify - -@dataclass -class RangeifyContext: - # block on parent until all children have been seen - seen_children: dict[UOp, dict[int, UOp]] = field(default_factory=dict) - seen_child: dict[UOp, Any] = field(default_factory=dict) - progress: int = 0 - - # create ranges - range_idx: int = 0 - def new_range(self, s:sint, axistype:AxisType=AxisType.LOOP): - ret = UOp.range(s, self.range_idx, axistype) - self.range_idx += 1 - return ret - -def map_reshape(idx:UOp, r:UOp): - acc = 1 - to_sum = [] - for s,src in list(zip(idx.shape, idx.src[1:]))[::-1]: - to_sum.append(acc*src) - acc *= s - mish = sum(to_sum, start=UOp.const(dtypes.int, 0)) - ret:list[UOp] = [] - for s in r.src[0].shape[::-1]: - ret.append(mish % s) # NOTE: simplify will turn this to CONST - mish //= s - tret = ret[0].sink(*ret[1:]).simplify().src[::-1] if len(ret) else () - return r.src[0].index(*tret, dtype=idx.dtype, arg=idx.arg) - -def map_pad(idx:UOp, r:UOp): - ret = list(idx.src[1:]) - bigwhere = UOp.const(dtypes.bool, True) - for i,(sh,(s,e)) in enumerate(zip(r.shape, r.arg)): - if s == 0 and e == 0: continue - where = UOp.const(dtypes.bool, True) - if resolve(e > 0): where = where & (ret[i] < (sh-e)) - if resolve(s > 0): where = where & (ret[i] >= s) - bigwhere = bigwhere & where - # this is safe but dumb - # TODO (S-Lykles): switch to mixed index/valid - ret[i] = (ret[i] - s).maximum(0).minimum(r.src[0].shape[i]-1) - # PAD is with 0 - return bigwhere.simplify().where(r.src[0].index(*ret, dtype=idx.dtype, arg=idx.arg), UOp.const(r.dtype, 0)) - -def map_expand(r:UOp, idx:UOp): - new_rngs = [] - ending_ranges = [] - non_ending_ranges = [] - for a,x,y in zip(idx.src[1:], r.src[0].shape, r.shape): - axis_to_range = [u for u in a.toposort() if u.op is Ops.RANGE] - if resolve(x!=y, False): - ending_ranges.extend(axis_to_range) - new_rngs.append(a.const_like(0)) - else: - non_ending_ranges.extend(axis_to_range) - new_rngs.append(a) - ending_ranges = [x.arg for x in ending_ranges if x not in non_ending_ranges] - if idx.arg is not None: ending_ranges.append(idx.arg) - return r.src[0].index(*new_rngs, arg=min(ending_ranges) if ending_ranges else None) - -pm_mops = PatternMatcher([ - # this is like the definitions of these - (UPat(Ops.SHRINK, name="r").f(Ops.INDEX, allow_any_len=True, name="idx"), - lambda r,idx: r.src[0].index(*[a+ss if resolve(ss != 0) else a for a,(ss,_) in zip(idx.src[1:], r.arg)], dtype=idx.dtype, arg=idx.arg)), - (UPat(Ops.PERMUTE, name="r").f(Ops.INDEX, allow_any_len=True, name="idx"), - lambda r,idx: r.src[0].index(*[idx.src[1+p] for p in argsort(idx.src[0].arg)], dtype=idx.dtype, arg=idx.arg)), - (UPat(Ops.FLIP, name="r").f(Ops.INDEX, allow_any_len=True, name="idx"), - lambda r,idx: r.src[0].index(*[((s-1)-a) if f else a for a,s,f in zip(idx.src[1:], r.shape, r.arg)], dtype=idx.dtype, arg=idx.arg)), - # expand needs to end ranges - (UPat(Ops.EXPAND, name="r").f(Ops.INDEX, allow_any_len=True, name="idx"), map_expand), - # reshape does a lot of symbolic stuff - (UPat(Ops.RESHAPE, name="r").f(Ops.INDEX, allow_any_len=True, name="idx"), map_reshape), - # pad adds min and max - (UPat(Ops.PAD, name="r").f(Ops.INDEX, allow_any_len=True, name="idx"), map_pad), -]) - -def map_partial_contiguous(ctx:RangeifyContext, x:UOp, idx:UOp): - if x.arg is None: return None # map_contiguous can handle this - # NOTE: all partial contiguous can safely be replaced by full contiguous. we should be able to match old functionality like this - if not (RANGEIFY > 1): return idx.replace(src=(x.replace(arg=None),)+idx.src[1:]) - ranges = [] - new_ranges = [] - passthrough_idx = [] - for i,s in enumerate(x.shape): - if i not in x.arg: - ranges.append(idx.src[1+i]) - continue - passthrough_idx.append(idx.src[1+i]) - ranges.append(ctx.new_range(s) if resolve(s!=1) else UOp.const(dtypes.int, 0)) - new_ranges.append(ranges[-1]) - ret = x.src[0].index(*ranges).bufferize(*[x for x in new_ranges if x.op is not Ops.CONST], arg=x.device) - return ret.index(*passthrough_idx) - -def map_contiguous(ctx:RangeifyContext, x:UOp): - if x.arg is not None: return None - ranges = [] - for s in x.shape[len(x.src)-1:]: - ranges.append(ctx.new_range(s) if resolve(s!=1) else UOp.const(dtypes.int, 0)) - ret = x.src[0].index(*ranges).bufferize(*x.src[1:], *[x for x in ranges if x.op is not Ops.CONST], arg=x.device) - return ret.shrink(((0, prod(x.shape)),)).forced_reshape(x.shape) - -def map_reduce(ctx:RangeifyContext, idx:UOp, red:UOp): - rngs = list(idx.src[1:]) - new_ranges = [] - for i,s in enumerate(red.src[0].shape): - if i in red.arg[1]: - rngs[i] = ctx.new_range(s, axistype=AxisType.REDUCE) - new_ranges.append(rngs[i]) - return UOp(Ops.REDUCE, red.dtype, src=(red.src[0].index(*rngs),)+tuple(new_ranges), arg=red.arg[0]) - -def index_child(ctx:RangeifyContext, c:UOp, x:UOp, idx:UOp): - if c not in ctx.seen_children: ctx.seen_children[c] = {} - # wait here until we have seen all the children - if len(ctx.seen_children[c]) != x.arg[1]: - ctx.progress += 1 - if ctx.progress > 10000: raise RuntimeError("children not making progress") - # NOTE: we mark this here - ctx.seen_children[c][x.arg[0]] = idx - raise RewriteNotReady - ctx.progress = 0 - - if c not in ctx.seen_child: - all_rngs = zip(*[ch.src[1:] for ch in ctx.seen_children[c].values()]) - out_rngs = [] - end_ranges = [] - idx_ranges = [] - for i,r in enumerate(all_rngs): - if all_same(r): - out_rngs.append(r[0]) - else: - out_rngs.append(ctx.new_range(c.shape[i])) - end_ranges.append(out_rngs[-1]) - idx_ranges.append(i) - ctx.seen_child[c] = (idx_ranges, end_ranges) - else: - out_rngs = list(idx.src[1:]) - idx_ranges, end_ranges = ctx.seen_child[c] - for i,nr in zip(idx_ranges, end_ranges): out_rngs[i] = nr - # index based on the shared ranges - ret = c.index(*out_rngs) - # if all ranges aren't the same between children, we have to bufferize - if len(idx_ranges) > 0: ret = ret.bufferize(*end_ranges, arg=x.device).index(*[idx.src[1+i] for i in idx_ranges]) - return ret - -def children_gate(ctx:RangeifyContext, idx:UOp, c:UOp): - if len(ctx.seen_children[c]) != c.arg: raise RuntimeError("all children should have been seen by now") - return idx.replace(src=(idx.src[0].src[0],)+idx.src[1:]) - -def might_end_axis(idx:UOp): - if idx.arg is None: return None - # TODO: write a proper cost function here - if all(x.op not in {Ops.BUFFER, Ops.CONTIGUOUS, Ops.BUFFERIZE} for x in idx.toposort()): return None - if all(x.op not in {Ops.REDUCE_AXIS} for x in idx.toposort()): return None - to_end_axis = [] - for i,a in enumerate(idx.src[1:]): - if any(x.arg > idx.arg for x in a.toposort() if x.op is Ops.RANGE): - to_end_axis.append(i) - if to_end_axis: return idx.replace(src=(idx.src[0].contiguous(arg=tuple(to_end_axis)),)+idx.src[1:], arg=None) - return idx.replace(arg=None) - -pm_rangeify = pm_mops+PatternMatcher([ - # sink contigs to kick it off - (UPat(Ops.CONTIGUOUS, src=(UPat(),), name="x", allow_any_len=True), map_contiguous), - # if there's an INDEX it can support partial contig - (UPat(Ops.INDEX, src=(UPat(Ops.CONTIGUOUS, src=(UPat(),), name="x"),), allow_any_len=True, name="idx"), map_partial_contiguous), - - # if there are new ended children, tag the SINK - (UPat(Ops.INDEX, src=(UPat(Ops.CHILD, src=(UPat(name="c"), ), name="x"),), allow_any_len=True, name="idx"), index_child), - (UPat(Ops.INDEX, src=(UPat(Ops.CHILDREN, name="c"),), allow_any_len=True, name="idx"), children_gate), - - # if we come across this, remove it. it was a CHILD unused in an INDEX - (UPat(Ops.CHILD, src=(UPat(Ops.CHILDREN, src=(UPat.var("x"),)),)), lambda x: x), - - # CONST (or DEFINE_VAR) can't have axes. remove srcs when we INDEX it - (UPat(Ops.INDEX, src=(UPat((Ops.CONST, Ops.DEFINE_VAR), name="c"),)), lambda c: c.replace(src=())), - - # handle arg on any op with weight. old endrange stuff - (UPat(Ops.INDEX, src=(UPat(GroupOp.Elementwise.union({Ops.REDUCE_AXIS})),), allow_any_len=True, name="idx"), might_end_axis), - - # move MAP through elementwise ALU / reduce. these are the items with cost - (UPat(Ops.INDEX, src=(UPat(GroupOp.Elementwise.union({Ops.STORE, Ops.ASSIGN, Ops.COPY, Ops.DEVICE, Ops.BIND})),), allow_any_len=True, name="x"), - lambda x: x.src[0].replace(src=tuple([s.index(*x.src[1:]) for s in x.src[0].src]))), - (UPat(Ops.INDEX, src=(UPat(Ops.REDUCE_AXIS, name="red"),), allow_any_len=True, name="idx"), map_reduce), -]) - -# 3.5 cleanups - -# you don't know in the first pass if axes are going to die, this happens if there's an EXPAND to the left -# TODO: figure out how to reenable this -def cleanup_dead_axes(b:UOp): - parents = b.src[0].toposort() - new_rng = [] - hit = False - reshape: list[sint] = [] - for s,rng in zip(b.shape, b.src[1:]): - if rng not in parents and rng.op is Ops.RANGE: - reshape.append(1) - hit = True - else: - reshape.append(s) - new_rng.append(rng) - if hit: - return b.replace(src=b.src[0:1]+tuple(new_rng)).reshape(tuple(reshape)).expand(b.shape) - -# if a buffer is being stored just for permutes or something, remove it -# we want to reexpress the indexes of idx2 in terms of the implied b1 -def remove_bufferize(b2:UOp, idx2:UOp): - # HACK - if len(b2.src) != len(idx2.src): return None - assert len(b2.src) == len(idx2.src) - assert all(x.op is Ops.RANGE for x in b2.src[1:]) - return b2.src[0].substitute(dict(zip(b2.src[1:], idx2.src[1:]))) - -pm_cleanups = double_reshape+pm_mops+PatternMatcher([ - #(UPat(Ops.BUFFERIZE, name="b"), cleanup_dead_axes), - # remove noop buffers. if we look at the next index we can remove even more of these - # NOTE: this is mostly the same case as below, but if there's no INDEX this gets more - #(UPat(Ops.INDEX, name="idx").f(Ops.BUFFERIZE, allow_any_len=True, name="b2"), - # lambda idx,b2: idx.src[0] if idx.src[1:] == b2.src[1:] else None), - # remove reindexing - (UPat(Ops.INDEX).f(Ops.BUFFERIZE, allow_any_len=True, name="b2").f(Ops.INDEX, allow_any_len=True, name="idx2"), remove_bufferize), - # no buffers for const - #(UPat(Ops.CONST, name='c').f(Ops.BUFFERIZE, allow_any_len=True, name="b"), lambda c,b: c.reshape((1,)*len(b.shape)).expand(b.shape)), -]) - -# 4. put in buffers for bufferize -# TODO: should BUFFERIZE look a lot more like STORE -# BUFFERIZE has device in arg -# BUFFERIZE doesn't have indexing, that's implied by the ranges it closes -# BUFFERIZE returns the BUFFER ready for INDEXing (doing this will make splitting a lot easier) -# NOTE: this has been fixed up a bit - -def bufferize_to_store(x:UOp, locals_allowed=False): - rngs = x.src[1:] - shape = tuple([int(r.vmax+1) for r in rngs]) - size = prod(shape) - assert size > 0, f"no zero sized buffers {shape}" - sdtype = x.dtype.ptr(size=size, addrspace=AddrSpace.GLOBAL if not isinstance(x.arg, tuple) else x.arg[0]) - if x.src[0].op is Ops.ASSIGN: - assign_target, assign_src = x.src[0].src - assert assign_target.op is Ops.INDEX - return assign_target.replace(dtype=sdtype).store(assign_src, *rngs, dtype=sdtype) - # NOTE: the DEFINE_LOCAL needs to be disambiguated here - if sdtype.addrspace == AddrSpace.GLOBAL: - buf = UOp.new_buffer(x.arg, size, x.dtype) - else: - if not locals_allowed: return None - buf = UOp(Ops.DEFINE_LOCAL, sdtype, arg=x.arg[1]) - return buf.reshape(shape).index(*rngs, dtype=sdtype).store(x.src[0], *rngs, dtype=sdtype).forced_reshape(shape, dtype=x.dtype) - -pm_add_buffers_local = pm_mops+PatternMatcher([ - (UPat(Ops.BUFFERIZE, name="x"), lambda x: bufferize_to_store(x, True)), -]) - -pm_add_buffers = pm_mops+PatternMatcher([ - (UPat(Ops.BUFFERIZE, name="x"), bufferize_to_store), - - # move RESHAPEs through MSELECT/MSTACK - (UPat((Ops.MSELECT, Ops.MSTACK), src=UPat(Ops.RESHAPE), name="m"), - lambda m: m.replace(src=tuple([x.src[0] for x in m.src])).reshape(m.src[0].arg)), -]) - -# 5. split into kernels - -@dataclass -class LocalAddBufferContext: - dg:int = 0 - map:dict = field(default_factory=dict) - vars:dict = field(default_factory=dict) - -def debuf(ctx:LocalAddBufferContext, buf:UOp): - ret = UOp(Ops.DEFINE_GLOBAL, buf.dtype.ptr(buf.arg), arg=ctx.dg) - if buf not in ctx.map: ctx.map[buf] = buf - ctx.dg += 1 - return ret - -def unbind_kernel(ctx:LocalAddBufferContext, b:UOp): - ctx.vars[b] = None - return b.src[0] - -def handle_assign(ctx:LocalAddBufferContext, assign:UOp): - buf = assign.as_buf() - # HACK to put the buffer in the MAP instead of MSTACK/MSELECT - if buf.op in {Ops.MSTACK, Ops.MSELECT}: buf = buf.src[0] - assert buf not in ctx.map - ctx.map[buf] = assign - return buf - -to_define_global = PatternMatcher([ - (UPat(Ops.BUFFER, name="buf"), debuf), - (UPat(Ops.BIND, name="b"), unbind_kernel), - (UPat((Ops.ASSIGN, Ops.MSTACK, Ops.MSELECT), name="assign"), handle_assign), - - # HACK in case any CONSTs were replaced - # this is only needed if you are using symbolic - #(UPat(Ops.CONST, name="c"), lambda c: c.replace(src=()) if len(c.src) else None), -]) - -rangeify_codegen = PatternMatcher([ - # add loads to non ptr indexes - # TODO: this can be moved into codegen? - (UPat((Ops.DEFINE_GLOBAL, Ops.STORE), name="dg").f(Ops.INDEX, name="idx", allow_any_len=True), - lambda dg,idx: None if isinstance(idx.dtype, (PtrDType, ImageDType)) else idx.replace(dtype=dg.dtype, arg=None).load()), - - # TODO: this can be moved into codegen - (UPat(Ops.STORE, name="store").f(Ops.INDEX, allow_any_len=True, name="idx").f(Ops.LOAD), - lambda store,idx: idx.replace(src=(store.as_buf(),)+idx.src[1:]).load(store if idx.dtype.addrspace != AddrSpace.LOCAL else store.barrier())), - - # TODO: hack for group for reduce - (UPat(Ops.IF, src=(UPat.var("gate"), UPat(Ops.LOAD, src=(UPat.var("src"), UPat.var("barrier"))),)), - lambda src, barrier, gate: src.load(UOp(Ops.IF, src=(gate, barrier)))), -]) - -def split_store(x:UOp): - if len(x.ranges): return None - ctx = LocalAddBufferContext() - ret = graph_rewrite(x, to_define_global+rangeify_codegen, ctx=ctx, name="kernel split", bottom_up=True) - - # NOTE: the hack for COPY is here - ret = ret.sink() if ret.src[1].op is not Ops.COPY else ret.src[1] - kernel = UOp(Ops.KERNEL, src=tuple(ctx.map.values())+tuple(ctx.vars.keys()), arg=Kernel(ret,())) - return x.as_buf().assign(kernel) - -split_kernels = PatternMatcher([ - (UPat(Ops.STORE, name="x"), split_store), -]) - -@track_rewrites(name=lambda sink,ret: f"Schedule {pluralize('Kernel',len([u for u in ret[sink].toposort() if u.op is Ops.KERNEL]))}", replay=True) -def get_rangeify_map(sink:UOp) -> dict[UOp, UOp]: - tensor_map = graph_rewrite_map(sink, multi_pm+earliest_rewrites, name="earliest") - realize_map: dict[UOp, UOp] = {} - graph_rewrite(tensor_map[sink], do_realize, ctx=realize_map, name="Input Graph") - tensor_map = graph_rewrite_map(tensor_map[sink], add_contiguous, ctx=realize_map, bottom_up=True, input_map=tensor_map, name="add contiguous") - tensor_map = graph_rewrite_map(tensor_map[sink], remove_tags, input_map=tensor_map, name="cleanup") - tensor_map = graph_rewrite_map(tensor_map[sink], pm_children, ctx=ChildrenContext(), bottom_up=True, input_map=tensor_map, name="children") - tensor_map = graph_rewrite_map(tensor_map[sink], pm_rangeify, ctx=RangeifyContext(), bottom_up=True, input_map=tensor_map, name="rangeify") - # NOTE: running symbolic can break the graph, leaving RANGE/INDEX/BUFFERIZE in the final graph - #tensor_map = graph_rewrite_map(tensor_map[sink], symbolic_simple, input_map=tensor_map, name="symbolic") - tensor_map = graph_rewrite_map(tensor_map[sink], pm_cleanups, bottom_up=True, input_map=tensor_map, name="cleanups") - if getenv("VIZ"): graph_rewrite(tensor_map[sink], PatternMatcher([]), name="View Rangeify Graph") - - tensor_map = graph_rewrite_map(tensor_map[sink], pm_add_buffers, bottom_up=True, input_map=tensor_map, name="add buffers") - tensor_map = graph_rewrite_map(tensor_map[sink], split_kernels, input_map=tensor_map, name="split kernels") - - # if a kernel depends on a buffer, and that buffer is later assigned to, make the assign depend on the kernel's assign - kernel_assign: dict[UOp, UOp] = {} - assign_rep: dict[UOp, UOp] = {} - for u in tensor_map[sink].toposort(): - if u.op is not Ops.ASSIGN: continue - kernel_assign[u.buf_uop] = u - for s in u.src[1].src: - # TODO: this is probably broken for MSELECT/MSTACK - if s.op is not Ops.BUFFER or s is u.buf_uop or (a:=kernel_assign.get(s)) is None: continue - if any(x.op is Ops.ASSIGN and x.buf_uop is s for x in u.toposort()): - raise RuntimeError(f"cycle detected in graph, kernel for {u.buf_uop} must either depend on ASSIGN or BUFFER") - assign_rep[a] = kernel_assign[s] = a.replace(src=a.src+(u,)) - if assign_rep: - tensor_map = graph_rewrite_map(tensor_map[sink], _substitute, ctx=assign_rep, bottom_up=True, input_map=tensor_map, name="fix_assign") - - if getenv("VIZ"): graph_rewrite(tensor_map[sink], PatternMatcher([]), name="View Kernel Graph") - return tensor_map diff --git a/tinygrad_repo/tinygrad/shape/shapetracker.py b/tinygrad_repo/tinygrad/shape/shapetracker.py index 3abddc69c..5b5ca7a96 100644 --- a/tinygrad_repo/tinygrad/shape/shapetracker.py +++ b/tinygrad_repo/tinygrad/shape/shapetracker.py @@ -2,9 +2,9 @@ from __future__ import annotations from dataclasses import dataclass import functools -from typing import Callable +from typing import Optional, Callable from tinygrad.helpers import merge_dicts, getenv -from tinygrad.shape.view import View, unravel +from tinygrad.shape.view import View, strides_for_shape, unravel from tinygrad.dtype import dtypes from tinygrad.uop.ops import UOp, Ops, graph_rewrite, Variable, sint, sint_to_uop, Context, PatternMatcher, UPat, GroupOp from tinygrad.uop.symbolic import split_uop, symbolic_flat, uop_given_valid, simplify_valid @@ -23,7 +23,7 @@ def handle_upcast(u: UOp) -> UOp|None: pm_upcast = PatternMatcher([(UPat(GroupOp.ALU, dtype=dtypes.int, name="u"), handle_upcast),]) @functools.cache -def views_to_indexed_uops(views: tuple[View, ...], _idxs:tuple[UOp, ...]|None=None) -> tuple[UOp, UOp]: +def views_to_indexed_uops(views: tuple[View, ...], _idxs:Optional[tuple[UOp, ...]]=None) -> tuple[UOp, UOp]: idx, valid = views[-1].to_indexed_uops(_idxs) for view in reversed(views[0:-1]): view = view.minify() @@ -38,19 +38,19 @@ def views_to_indexed_uops(views: tuple[View, ...], _idxs:tuple[UOp, ...]|None=No return graph_rewrite(UOp.sink(idx, valid), symbolic_flat+pm_upcast, name="indexing sym @ 2").src @functools.cache -def views_to_real_strides(views: tuple[View, ...], ignore_valid=False) -> tuple[sint|None, ...]: +def views_to_real_strides(views: tuple[View, ...], ignore_valid=False) -> tuple[Optional[sint], ...]: # NOTE: if a stride is not always valid, it will be None if len(views) == 1 and views[-1].mask is None: return views[-1].strides - ret: list[sint|None] = [None] * len(views[-1].shape) + ret: list[Optional[sint]] = [None] * len(views[-1].shape) idx, valid = views_to_indexed_uops(views) for c in split_uop(idx, Ops.ADD): - if c.op is Ops.RANGE: ret[c.arg[0]] = 1 - if c.op is Ops.MUL and c.src[0].op is Ops.RANGE and c.src[1].op is Ops.CONST: ret[c.src[0].arg[0]] = c.src[1].arg - if c.op is Ops.MUL and c.src[1].op is Ops.RANGE and c.src[0].op is Ops.CONST: ret[c.src[1].arg[0]] = c.src[0].arg - used_ranges = [x.arg[0] for x in idx.toposort() if x.op is Ops.RANGE] + if c.op is Ops.RANGE: ret[c.arg] = 1 + if c.op is Ops.MUL and c.src[0].op is Ops.RANGE and c.src[1].op is Ops.CONST: ret[c.src[0].arg] = c.src[1].arg + if c.op is Ops.MUL and c.src[1].op is Ops.RANGE and c.src[0].op is Ops.CONST: ret[c.src[1].arg] = c.src[0].arg + used_ranges = [x.arg for x in idx.toposort() if x.op is Ops.RANGE] ret = [x if i in used_ranges else 0 for i,x in enumerate(ret)] if not ignore_valid: - for masked_axis in [x.arg[0] for x in valid.toposort() if x.op is Ops.RANGE]: ret[masked_axis] = None + for masked_axis in [x.arg for x in valid.toposort() if x.op is Ops.RANGE]: ret[masked_axis] = None return tuple(ret) @dataclass(frozen=True, order=True) @@ -62,7 +62,7 @@ class ShapeTracker: for v in st.views: ret = ShapeTracker(ret.views + (v,)).simplify() # one view at a time = better simplification return ret - def invert(self, out_shape:tuple[sint, ...]) -> ShapeTracker|None: + def invert(self, out_shape:tuple[sint, ...]) -> Optional[ShapeTracker]: inverted_views:list[View] = [] for v,s in zip(self.views[::-1], [x.shape for x in self.views[::-1][1:]]+[out_shape]): if (inverted:= v.invert(s)) is None: return None @@ -75,6 +75,9 @@ class ShapeTracker: @property def contiguous(self) -> bool: return len(self.views) == 1 and self.views[0].contiguous + @property + def consecutive(self) -> bool: return len(self.views) == 1 and (v:=self.views[0]).mask is None and v.strides == strides_for_shape(v.shape) + @property def shape(self) -> tuple[sint, ...]: return self.views[-1].shape @@ -83,7 +86,8 @@ class ShapeTracker: def reduce(self, axis:tuple[int, ...]) -> tuple[sint, ...]: return tuple(1 if i in axis else s for i,s in enumerate(self.shape)) - def to_indexed_uops(self, _idxs:list[UOp]|tuple[UOp, ...]|None=None) -> tuple[UOp, UOp]: + def to_uop(self) -> UOp: return UOp(Ops.VIEW, dtypes.void, (), self) + def to_indexed_uops(self, _idxs:Optional[list[UOp]|tuple[UOp, ...]]=None) -> tuple[UOp, UOp]: return views_to_indexed_uops(self.views, tuple(_idxs) if _idxs is not None else None) # upper bound on buffer size required to fit this shapetracker @@ -105,14 +109,14 @@ class ShapeTracker: return ShapeTracker(tuple(unbound_views)), merge_dicts(var_vals) def substitute(self, dvars:dict[UOp, UOp]): return ShapeTracker(tuple(x.substitute(dvars) for x in self.views)) - def real_strides(self, ignore_valid=False) -> tuple[sint|None, ...]: + def real_strides(self, ignore_valid=False) -> tuple[Optional[sint], ...]: with Context(TRACK_MATCH_STATS=0): return views_to_real_strides(self.views, ignore_valid) def unit_stride_axes(self, ignore_valid=False) -> list[int]: return [i for i,st in enumerate(self.real_strides(ignore_valid)) if st == 1] def axis_is_masked(self, axis:int) -> bool: with Context(TRACK_MATCH_STATS=0): _, valid = self.to_indexed_uops() - return axis in [x.arg[0] for x in graph_rewrite(valid, symbolic_flat).toposort() if x.op is Ops.RANGE] + return axis in [x.arg for x in graph_rewrite(valid, symbolic_flat).toposort() if x.op is Ops.RANGE] def simplify(self) -> ShapeTracker: if len(self.views) >= 2 and (new_view := self.views[-2] + self.views[-1]) is not None: diff --git a/tinygrad_repo/tinygrad/shape/view.py b/tinygrad_repo/tinygrad/shape/view.py index 6b4cd22bb..85a781690 100644 --- a/tinygrad_repo/tinygrad/shape/view.py +++ b/tinygrad_repo/tinygrad/shape/view.py @@ -1,9 +1,9 @@ from __future__ import annotations import functools, operator, itertools from dataclasses import dataclass -from typing import cast, Sequence +from typing import Optional, cast, Sequence from tinygrad.dtype import dtypes -from tinygrad.uop.ops import resolve, UOp, Variable, sint, smax, smin, sint_to_uop, Ops, ssimplify +from tinygrad.uop.ops import resolve, UOp, Variable, sint, sym_infer, smax, smin, sint_to_uop, Ops, ssimplify from tinygrad.helpers import prod, all_int, argsort, flatten, ceildiv # returns the axes to create new_shape if new_shape can be created by combining axis from old_shape @@ -42,7 +42,7 @@ def strides_for_shape(shape:tuple[sint, ...]) -> tuple[sint, ...]: return canonicalize_strides(shape, strides) @functools.cache -def merge_dims(shape:tuple[int, ...], strides:tuple[int, ...], mask:tuple[tuple[int, int], ...]|None=None) -> tuple[tuple[int, int, int], ...]: +def merge_dims(shape:tuple[int, ...], strides:tuple[int, ...], mask:Optional[tuple[tuple[int, int], ...]]=None) -> tuple[tuple[int, int, int], ...]: # merge contiguous sub-parts or zero strided dims # any stride 0, masked from dim=1, or contiguous part is merged into next dim. # stride != 0 to stride == 0 starts a new merging block @@ -64,8 +64,8 @@ def merge_dims(shape:tuple[int, ...], strides:tuple[int, ...], mask:tuple[tuple[ return tuple(ret) @functools.cache -def _reshape_mask(_mask:tuple[tuple[sint, sint], ...]|None, old_shape:tuple[sint, ...], new_shape:tuple[sint, ...]) \ - -> tuple[tuple[sint, sint], ...]|None: +def _reshape_mask(_mask:Optional[tuple[tuple[sint, sint], ...]], old_shape:tuple[sint, ...], new_shape:tuple[sint, ...]) \ + -> Optional[tuple[tuple[sint, sint], ...]]: """Returns the new mask if reshape is possible, and None if not possible.""" if _mask is None: return tuple((0, s) for s in new_shape) if not all_int(flatten(_mask)): return None @@ -109,12 +109,12 @@ class View: shape:tuple[sint, ...] strides:tuple[sint, ...] offset:sint - mask:tuple[tuple[sint, sint], ...]|None + mask:Optional[tuple[tuple[sint, sint], ...]] contiguous:bool - def to_indexed_uops(self:View, idxs:Sequence[UOp]|None=None, vexpr:UOp=UOp.const(dtypes.bool, True)) -> tuple[UOp, UOp]: + def to_indexed_uops(self:View, idxs:Optional[Sequence[UOp]]=None, vexpr:UOp=UOp.const(dtypes.bool, True)) -> tuple[UOp, UOp]: """(idx, valid)""" - if idxs is None: idxs = [UOp.range(s, i) for i,s in enumerate(self.shape)] + if idxs is None: idxs = [UOp.range(dtypes.int, s, i) for i,s in enumerate(self.shape)] iexpr = sint_to_uop(self.offset) for idx,sh,st,m in zip(idxs, self.shape, self.strides, self.mask if self.mask is not None else itertools.repeat(None)): if resolve(sh != 1) and resolve(st != 0): iexpr = iexpr + idx*st @@ -131,7 +131,7 @@ class View: @staticmethod @functools.cache - def create(shape:tuple[sint, ...], strides:tuple[sint, ...]|None=None, offset:sint=0, mask:tuple[tuple[sint, sint], ...]|None=None): + def create(shape:tuple[sint, ...], strides:Optional[tuple[sint, ...]]=None, offset:sint=0, mask:Optional[tuple[tuple[sint, sint], ...]]=None): # TODO: resolve shouldn't be needed here if not all(resolve(s >= 0) for s in shape): raise ValueError(f"Trying to create View with negative dimension: {shape=}") strides = canonicalize_strides(shape, strides) if strides else strides_for_shape(shape) @@ -177,7 +177,7 @@ class View: return View.create(new_shape, new_strides, new_offset, new_mask) @functools.cache # pylint: disable=method-cache-max-size-none - def __add__(self, vm1:View) -> View|None: + def __add__(self, vm1:View) -> Optional[View]: vm2 = self if vm2.contiguous or vm1.size() == 0: return vm1 if vm1.contiguous and vm1.shape == vm2.shape: return vm2 @@ -192,15 +192,15 @@ class View: return None # Project vm1's offset and strides on to vm2. - origin = [ssimplify(o) for o in unravel(vm2.shape, vm1.offset)] + origin = unravel(vm2.shape, vm1.offset) terms: list[list[tuple[int, sint]]] = [[] for _ in vm2.shape] strides: list[sint] = [0] * len(vm1.shape) for d1, st in enumerate(vm1.strides): if st == 0: continue for d2, (o, s1) in enumerate(zip(origin, unravel(vm2.shape, vm1.offset + st))): - if not resolve((s1 := s1 - o)!=0): continue # if s1 can possibly be 0 + if (s1 := s1 - o) == 0: continue terms[d2].append((d1, s1)) - strides[d1] += ssimplify(s1 * vm2.strides[d2]) + strides[d1] += s1 * vm2.strides[d2] # Merge dimensions in vm2 if required. # NB: Merging too many dimensions can make it difficult to project vm2's mask, hence only combining when required. @@ -223,12 +223,9 @@ class View: # Try to project vm2's mask on to vm1. newb, newe, bad = [0] * len(vm1.shape), list(vm1.shape), False for (b, e), o, term, (_, t) in zip(vm2.mask, origin, terms, reversed(extents)): - if resolve(b <= (t := t.simplify()).vmin and t.vmax < e, False): continue + if resolve(b <= t.vmin and t.vmax < e, False): continue if len(term) != 1: - if not term and newe: - # t should be a constant if no terms contribute to this dimension, but it might not be simplified - if t.vmin != t.vmax: return None - newe[0] = 0 + if not term and newe: newe[0] = 0 else: bad = True continue d1, s1 = term[0] @@ -241,10 +238,10 @@ class View: # Otherwise if vm2's mask was violated, then cannot merge. if bad: return None - return View.create(vm1.shape, tuple(strides), ssimplify(sum(o * s for o, s in zip(origin, vm2.strides)) + vm2.offset)) + return View.create(vm1.shape, tuple(strides), sum(o * s for o, s in zip(origin, vm2.strides)) + vm2.offset) @functools.cache # pylint: disable=method-cache-max-size-none - def invert(self, out_shape:tuple[sint, ...]) -> View|None: + def invert(self, out_shape:tuple[sint, ...]) -> Optional[View]: ret = View.create(self.shape) if self.mask: ret = ret.shrink(self.mask) ret = ret.flip(tuple(x < 0 for x in self.strides)).permute(argsort(tuple(-x if x > 0 else x for x in self.strides))) @@ -306,15 +303,14 @@ class View: return View.create(self.shape, tuple(-z if f else z for z,f in zip(self.strides, arg)), self.offset+offset, mask) @functools.cache # pylint: disable=method-cache-max-size-none - def reshape(self, new_shape: tuple[sint, ...]) -> View|None: + def reshape(self, new_shape: tuple[sint, ...]) -> Optional[View]: if self.shape == new_shape: return self if not all(x >= 0 for x in new_shape): raise ValueError(f"shape can't contain negative numbers {new_shape}") # check for the same size - if all_int(self.shape): - # reshapes cannot introduce symbolic shape - assert all_int(new_shape), f"{self.shape=} -> {new_shape=} contains non int dims" - if prod(self.shape) != prod(new_shape): raise ValueError(f"size mismatched, can't reshape {self.shape=} -> {new_shape=}") + if (self_all_int := all_int(self.shape)): + assert all(isinstance(s, (int, UOp)) for s in new_shape), f"{self.shape=} -> {new_shape=} contains non (int, Variable) dim" + if resolve(prod(self.shape) != prod(new_shape), False): raise ValueError(f"size mismatched, can't reshape {self.shape=} -> {new_shape=}") if 0 in self.shape: return View.create(new_shape) if new_shape == () and self.mask and any(mx==my for (mx,my) in self.mask): return None @@ -322,6 +318,15 @@ class View: # after the asserts, it's okay to check contiguous if self.contiguous: return View.create(new_shape) + # if it's not contiguous and new shape is symbolic, check if it's directly replaceable + if self_all_int and not all_int(new_shape): + if len(self.shape) != len(new_shape): raise ValueError(f"cannot symbolic reshape non-contiguous {self} -> {new_shape}") + for si, so in zip(self.shape, new_shape): + if not isinstance(so, int): so = sym_infer(so, dict([v.unbind() for v in so.vars()])) + if si != so: raise ValueError(f"cannot symbolic reshape non-contiguous {self} -> {new_shape}") + # all dimensions matched, return the new view directly + return View(new_shape, self.strides, self.offset, self.mask, self.contiguous) + r_strides, r_new_shape = [], reversed(new_shape) for merged_size, new_stride, real_size in reversed(merge_dims(self.shape, self.strides, self.mask)): # TODO: write with get_contraction diff --git a/tinygrad_repo/tinygrad/tensor.py b/tinygrad_repo/tinygrad/tensor.py index bdfd18ea5..f6d446850 100644 --- a/tinygrad_repo/tinygrad/tensor.py +++ b/tinygrad_repo/tinygrad/tensor.py @@ -1,12 +1,12 @@ # inspired by https://github.com/karpathy/micrograd/blob/master/micrograd/engine.py from __future__ import annotations -import time, math, itertools, functools, struct, sys, inspect, pathlib, string, hashlib, weakref +import time, math, itertools, functools, struct, sys, inspect, pathlib, string, hashlib, weakref, contextvars from contextlib import ContextDecorator -from typing import Callable, ClassVar, Sequence, cast, get_args, Literal, SupportsIndex, ParamSpec, TypeVar, Generic +from typing import Callable, ClassVar, Sequence, cast, get_args, Literal, SupportsIndex, ParamSpec, TypeVar, Optional from tinygrad.dtype import DType, DTypeLike, dtypes, ImageDType, ConstType, least_upper_float, least_upper_dtype, sum_acc_dtype, to_dtype, truncate from tinygrad.dtype import _from_np_dtype, _to_np_dtype from tinygrad.helpers import argfix, make_tuple, flatten, prod, all_int, round_up, merge_dicts, argsort, getenv, all_same, fully_flatten, dedup -from tinygrad.helpers import IMAGE, WINO, Metadata, TRACEMETA, ceildiv, fetch, polyN, unwrap, DEBUG, is_numpy_ndarray, RANGEIFY, FUSE_ATTENTION +from tinygrad.helpers import IMAGE, WINO, Metadata, TRACEMETA, ceildiv, fetch, polyN, unwrap, DEBUG from tinygrad.gradient import compute_gradient from tinygrad.uop.ops import smax, smin, resolve, UOp, Ops, sint, Variable, MathTrait, identity_element, all_metadata from tinygrad.uop.spec import tensor_uop_spec, type_verify @@ -14,12 +14,11 @@ from tinygrad.device import Device, Buffer from tinygrad.engine.realize import run_schedule from tinygrad.engine.memory import memory_planner from tinygrad.engine.schedule import ScheduleItem, create_schedule_with_vars -from tinygrad.schedule.rangeify import get_rangeify_map -from tinygrad.schedule.kernelize import get_kernelize_map +from tinygrad.kernelize.kernelize import get_kernelize_map # *** all in scope Tensors are here. this gets relevant UOps *** -all_tensors: dict[weakref.ref[Tensor], None] = {} +all_tensors: set[weakref.ref[Tensor]] = set() def _find_all_tensors_for_uops(all_uops: set[UOp]) -> list[Tensor]: return [t for tref in all_tensors if (t:=tref()) is not None and t.uop in all_uops] @@ -40,9 +39,6 @@ def _apply_map_to_tensors(applied_map:dict[UOp, UOp], name:str|None=None) -> Non sink = UOp.sink(*[t.uop for t in fixed_tensors]) new_sink = sink.substitute(applied_map, name=name) - # NOTE: you can check the Tensor graph early here - #if __debug__: type_verify(list(new_sink.toposort()), tensor_uop_spec) - # set the relevant uop to the realized UOps for t,s,ns in zip(fixed_tensors, sink.src, new_sink.src): if s is ns: continue @@ -50,6 +46,9 @@ def _apply_map_to_tensors(applied_map:dict[UOp, UOp], name:str|None=None) -> Non # **** Tensor helper functions **** +# this tracks the tensor.py METADATA +_METADATA: contextvars.ContextVar[Optional[Metadata]] = contextvars.ContextVar("_METADATA", default=None) + def _fromnp(x: 'np.ndarray') -> UOp: # type: ignore [name-defined] # noqa: F821 ret = UOp.new_buffer("NPY", x.size, _from_np_dtype(x.dtype)) # fake realize @@ -68,7 +67,7 @@ def _frompy(x:list|tuple|bytes, dtype:DType) -> UOp: ret = UOp.new_buffer("PYTHON", prod(shape:=get_shape(x)), dtype).reshape(shape) assert dtype.fmt is not None, f"{dtype=} has None fmt" truncate_function = truncate[dtype] - data = struct.pack(f"{ret.size}{dtype.fmt}", *[truncate_function(dtypes.as_const(xi, dtype)) for xi in fully_flatten(x)]) + data = struct.pack(f"@{ret.size}{dtype.fmt}", *[truncate_function(xi) for xi in fully_flatten(x)]) # fake realize ret.buffer.allocate(memoryview(data if Device.DEFAULT != "PYTHON" else bytearray(data))) return ret @@ -153,7 +152,7 @@ class Tensor(MathTrait): else: dtype = dtypes.default_int if d and all_int(d) else dtypes.default_float # NOTE: this works because all_int([True, False]) is True if dtype in [dtypes.bfloat16, *dtypes.fp8s]: data = Tensor(_frompy(data, dtypes.float32), device=device).cast(dtype).uop else: data = _frompy(data, dtype) - elif is_numpy_ndarray(data): + elif str(type(data)) == "": import numpy as np assert isinstance(data, np.ndarray), f"expected np.ndarray, got {data}" if data.shape == (): data = UOp.const(dtype or _from_np_dtype(data.dtype), data.item(), device, ()) @@ -174,11 +173,11 @@ class Tensor(MathTrait): self.uop = data # add to all_tensors after construction succeeds - all_tensors[weakref.ref(self)] = None - def __del__(self): all_tensors.pop(weakref.ref(self), None) + all_tensors.add(weakref.ref(self)) + def __del__(self): all_tensors.discard(weakref.ref(self)) - def _apply_uop(self, fxn:Callable, *x:Tensor, extra_args=(), **kwargs) -> Tensor: - new_uop: UOp = fxn(*[t.uop for t in (self,)+x], *extra_args, **kwargs) + def _apply_uop(self, fxn:Callable, *x:Tensor, **kwargs) -> Tensor: + new_uop: UOp = fxn(*[t.uop for t in (self,)+x], **kwargs) if (metadata:=_METADATA.get()) is not None: all_metadata[new_uop] = (metadata,) needs_input_grad = [t.requires_grad for t in (self,)+x] return Tensor(new_uop, device=new_uop.device, requires_grad=True if any(needs_input_grad) else None if None in needs_input_grad else False) @@ -235,7 +234,7 @@ class Tensor(MathTrait): # verify Tensors match the spec if __debug__: type_verify(list(big_sink.toposort()), tensor_uop_spec) - becomes_map = get_rangeify_map(big_sink) if RANGEIFY else get_kernelize_map(big_sink) + becomes_map = get_kernelize_map(big_sink) _apply_map_to_tensors(becomes_map, name="Apply Kernelize Map") return self @@ -256,7 +255,7 @@ class Tensor(MathTrait): # create the schedule schedule, var_vals = create_schedule_with_vars(sink) schedule = memory_planner(schedule) - if DEBUG >= 1 and len(schedule) > 1: print(f"scheduled {len(schedule)} kernels in {(time.perf_counter()-st)*1000:.2f} ms") + if DEBUG >= 1 and len(schedule) >= 10: print(f"scheduled {len(schedule)} kernels in {(time.perf_counter()-st)*1000:.2f} ms") return schedule, var_vals def schedule(self, *lst:Tensor) -> list[ScheduleItem]: @@ -283,13 +282,11 @@ class Tensor(MathTrait): # TODO: this is a hack for writing to DISK. remove with working assign if isinstance(self.device, str) and self.device.startswith("DISK"): if x.__class__ is not Tensor: x = Tensor(x, device="CPU", dtype=self.dtype) - self._buffer().copyin(x._data()) + cast(Buffer, self.contiguous().realize().uop.base.buffer).ensure_allocated().copyin(x._data()) return self if x.__class__ is not Tensor: x = Tensor(x, device=self.device, dtype=self.dtype) if self.uop is x.uop: return self # a self assign is a NOOP # NOTE: we allow cross device assign - # broadcast x - if least_upper_dtype(self.dtype, x.dtype) == self.dtype: x = x._broadcast_to(self.shape).cast(self.dtype) assert self.shape == x.shape, f"assign shape mismatch {self.shape} != {x.shape}" assert self.device == x.device, f"assign device mismatch {self.device} != {x.device}" assert self.dtype == x.dtype, f"assign dtype mismatch {self.dtype} != {x.dtype}" @@ -302,10 +299,7 @@ class Tensor(MathTrait): """ return Tensor(self.uop.detach(), device=self.device, requires_grad=False) - def _buffer(self) -> Buffer: - x = self.cast(self.dtype.base).contiguous() - if isinstance(self.device, tuple): x = x.to("CPU") - return cast(Buffer, x.realize().uop.base.buffer).ensure_allocated() + def _buffer(self) -> Buffer: return cast(Buffer, self.cast(self.dtype.base).contiguous().to("CPU").realize().uop.base.buffer) def _data(self) -> memoryview: return self._buffer().as_buffer() def data(self) -> memoryview: @@ -349,8 +343,6 @@ class Tensor(MathTrait): print(t.tolist()) ``` """ - # TODO: remove half once minimum python supports it - if self.dtype in (dtypes.half, dtypes.bfloat16, *dtypes.fp8s): return self.cast(dtypes.float32).tolist() return self.data().tolist() def numpy(self) -> 'np.ndarray': # type: ignore [name-defined] # noqa: F821 @@ -442,7 +434,7 @@ class Tensor(MathTrait): if not isinstance(size:=prod([x.vmax if isinstance(x, UOp) else x for x in shape]), int): raise ValueError(f"size must be int {size}") # TODO: add test for multidevice tensor device = tuple(Device.canonicalize(d) for d in device) if isinstance(device, tuple) else Device.canonicalize(device) - return Tensor(UOp.new_buffer(device, size, dtype), device, dtype, **kwargs).shrink(((0,prod(shape)),)).reshape(shape) + return Tensor(UOp.new_buffer(device, size, dtype), device, dtype, **kwargs).reshape(shape) @staticmethod def from_blob(ptr:int, shape:tuple[int, ...], **kwargs) -> Tensor: @@ -669,7 +661,7 @@ class Tensor(MathTrait): ``` """ if n < 0 or (m is not None and m < 0): raise ValueError(f"cannot have negative {n=}, {m=}") - x = Tensor.ones(n, **kwargs).diag() + x = Tensor.ones((n,1),**kwargs).pad((None,(0,n))).flatten().shrink(((0,n*n),)).reshape(n,n) return x if m is None else x.pad((None, (0, m-n))) if m > n else x.shrink((None, (0, m))) def full_like(self, fill_value:ConstType, **kwargs) -> Tensor: @@ -770,7 +762,7 @@ class Tensor(MathTrait): print(Tensor.randn(2, 3).numpy()) ``` """ - return Tensor.empty(*shape, **kwargs).randn_like(dtype=dtype, requires_grad=requires_grad) + return Tensor.empty(*shape).randn_like(dtype=dtype, requires_grad=requires_grad) @staticmethod def randint(*shape, low=0, high=10, dtype=dtypes.int32, **kwargs) -> Tensor: @@ -897,7 +889,9 @@ class Tensor(MathTrait): print(Tensor.randperm(6).numpy()) ``` """ - return Tensor.rand(n, device=device, **kwargs).argsort().cast(dtype) + r = Tensor.rand(n, device=device, **kwargs) + _, indices = r.sort() + return indices.cast(dtype) def multinomial(self:Tensor, num_samples:int = 1, replacement:bool = False) -> Tensor: """ @@ -1133,12 +1127,11 @@ class Tensor(MathTrait): if (isinstance(indices, list) and all_int(indices)) or not isinstance(indices, (tuple, list)): indices = [indices] x, indices = self, list(indices) - # fill ellipsis or rest of indices with slice(None) + # filter ellipsis and fill with slice(None) or fill rest of indices with slice(None) if len(ellipsis_idx := [dim for dim, i in enumerate(indices) if i is Ellipsis]) > 1: raise IndexError("indices can only have a single ellipsis") - # NOTE: None adds a dim later + fill_idx = ellipsis_idx[0] if ellipsis_idx else len(indices) num_indices = len(indices) - len(ellipsis_idx) - sum(1 for i in indices if i is None) if num_indices > self.ndim: raise IndexError(f"too many {num_indices=} for {self.ndim=}") - fill_idx = ellipsis_idx[0] if ellipsis_idx else len(indices) indices[fill_idx:fill_idx+1] = [slice(None)] * (self.ndim - num_indices) indices_parsed, dim = [], 0 @@ -1146,15 +1139,12 @@ class Tensor(MathTrait): size = 1 if index is None else self.shape[dim] boundary, stride = [0, size], 1 # defaults match index: - case Tensor(): + case list() | tuple() | Tensor(): + if not isinstance(index, Tensor): index = Tensor(index, self.device, requires_grad=False) if not dtypes.is_int(index.dtype): raise IndexError(f"index dtype {index.dtype} is not supported") - index = (index < 0).where(index+size, index).to(self.device) # treat negative index values - case list() | tuple(): - if not dtypes.is_int((ti:=Tensor(index)).dtype): raise IndexError(f"{index=} contains non-int element") - index = Tensor([i+size if i<0 else i for i in fully_flatten(index)], self.device, requires_grad=False).reshape(ti.shape) + index = (index.to(self.device) < 0).where(index+size, index) # treat negative index values case int() | UOp(): # sint if index >= size or index < -size: raise IndexError(f"{index=} is out of bounds with {size=}") - # TODO: is this right for (negative) symbolic? boundary = [index, index+1] if index >= 0 else [index+size, index+size+1] case slice(): if index.step == 0: raise ValueError(f"{index=} cannot have 0 as step") @@ -1168,9 +1158,9 @@ class Tensor(MathTrait): elif stride < 0: boundary = [boundary[1] + 1, boundary[0] + 1] # update size for slice size = ceildiv((boundary[1] - boundary[0]), abs(stride)) - elif resolve(step == 1, False) and all(isinstance(s,sint) for s in (start, stop)) and resolve((stop-start) > 0, False): + elif (step == 1) and isinstance(step, int) and all(isinstance(s,(int,UOp)) for s in (start, stop)) and resolve((stop-start) > 0, False): # simple symbolic slice - size = cast(sint, cast(UOp, (stop - start)).ssimplify()) + size = cast(UOp|int, cast(UOp, (stop - start)).ssimplify()) else: raise TypeError(f"slice {index=} is not supported") case None: pass # do nothing case _: raise IndexError(f"{type(index).__name__} indexing is not supported") @@ -1182,9 +1172,9 @@ class Tensor(MathTrait): # flip negative strides shrinks, strides = zip(*((i['boundary'], i['stride']) for i in mops)) x = x.shrink(shrinks).flip(tuple(i for i,st in enumerate(strides) if st < 0)) - strides = tuple(map(abs, strides)) - # apply stride - if any(st != 1 for st in strides): + # handle stride != 1 or -1 + if any(abs(st) != 1 for st in strides): + strides = tuple(abs(s) for s in strides) # pad shape to multiple of stride if not all_int(x.shape): raise RuntimeError("symbolic shape not supported") x = x.pad(tuple((0, round_up(s, st) - s) for s, st in zip(x.shape, strides))) @@ -1192,7 +1182,7 @@ class Tensor(MathTrait): x = x.shrink(tuple(flatten(((0, s), (0, 1)) for s in x.shape[::2]))).reshape(x.shape[::2]) # dim injection from None by including None dim size (which is 1) and dim collapse by skipping int dim size - x = x.reshape(tuple(index['size'] for index in indices_parsed if not isinstance(index['index'], sint))) + x = x.reshape(tuple(index['size'] for index in indices_parsed if not isinstance(index['index'], (int, UOp)))) # tensor indexing if tops := [(d,i) for d,i in enumerate(i_ for i_ in indices_parsed if not isinstance(i_['index'], int)) if isinstance(i['index'], Tensor)]: @@ -1212,7 +1202,7 @@ class Tensor(MathTrait): # inject 1's for the extra dims added in create masks reshape_arg = x.shape[:dims[0]] + (1,) * len(big_shape) + x.shape[dims[0]:] # sum reduce the extra dims introduced in create masks - x = (mask.where(x.reshape(reshape_arg), 0)).sum(sum_axis:=tuple(d + len(big_shape) for d in dims), dtype=x.dtype) + x = (x.reshape(reshape_arg) * mask).sum(sum_axis:=tuple(d + len(big_shape) for d in dims), dtype=x.dtype) # special permute case if dims[0] != 0 and len(dims) != 1 and tuple(dims) != tuple(range(dims[0], dims[-1]+1)): @@ -1303,7 +1293,7 @@ class Tensor(MathTrait): assert all(s >= i for d,(s,i) in enumerate(zip(self.shape, index.shape)) if d != dim), "requires self.shape[d] >= index.shape[d] for all d != dim" index = index.to(self.device) x = self.shrink(tuple((0, i) if d != dim else None for d,i in enumerate(index.shape))).unsqueeze(-1).transpose(-1, dim) - return (index.unsqueeze(-1)._one_hot_along_dim(self.shape[dim]).where(x, 0)).sum(-1, dtype=self.dtype) + return (x * index.unsqueeze(-1)._one_hot_along_dim(self.shape[dim])).sum(-1, dtype=self.dtype) def cat(self:Tensor, *args:Tensor, dim:int=0) -> Tensor: """ @@ -1338,7 +1328,7 @@ class Tensor(MathTrait): ``` """ # checks for shapes and number of dimensions delegated to cat - return Tensor.cat(*[t.unsqueeze(dim) for t in argfix(self, *args)], dim=dim) + return Tensor.cat(*[t.unsqueeze(dim) for t in [self, *args]], dim=dim) def repeat_interleave(self, repeats:int, dim:int|None=None) -> Tensor: """ @@ -1568,33 +1558,7 @@ class Tensor(MathTrait): dim = self._resolve_dim(dim) return self.reshape(self.shape[:dim] + sizes + self.shape[dim+1:]) - def diag(self) -> Tensor: - """ - Returns a 2-D square tensor with the elements of input as the main diagonal. - - ```python exec="true" source="above" session="tensor" result="python" - print(Tensor([1, 2, 3]).diag().numpy()) - ``` - """ - if self.ndim != 1: raise ValueError(f"expect input to be 1-D, getting {self.ndim}-D") - return self.unsqueeze(-1).pad((None,(0,n:=self.shape[0]))).flatten().shrink(((0,n*n),)).reshape(n,n) - - def diagonal(self) -> Tensor: - """ - Returns a view of input tensor with its main diagonal elements. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.arange(9).reshape(3, 3) - print(t.numpy()) - ``` - ```python exec="true" source="above" session="tensor" result="python" - print(t.diagonal().numpy()) - ``` - """ - if self.ndim != 2 or (n:=self.shape[0]) != self.shape[1]: raise ValueError(f"only 2-D square tensor is supported, getting {self.shape=}") - return self.flatten().pad(((0, n))).reshape(n, n+1)[:, 0] - - def roll(self, shifts:int|tuple[int, ...], dims:int|tuple[int, ...]|None=None) -> Tensor: + def roll(self, shifts:int|tuple[int, ...], dims:int|tuple[int, ...]) -> Tensor: """ Rolls the tensor along specified dimension(s). The rolling operation is circular, meaning that elements that go beyond the edge are wrapped around to the beginning of the dimension. @@ -1607,11 +1571,12 @@ class Tensor(MathTrait): print(t.roll(shifts=-1, dims=0).numpy()) ``` """ - if dims is None: return self.flatten().roll(shifts, 0).reshape(self.shape) - dims, shifts, slices = tuple(self._resolve_dim(d) for d in make_tuple(dims, 1)), make_tuple(shifts, 1), [slice(None)] * self.ndim - if len(dims) != len(shifts): raise RuntimeError(f"{len(dims)=} != {len(shifts)=}") - for dim, shift in zip(dims, shifts): slices[dim] = slice(delta:=self.shape[dim]-shift%self.shape[dim], delta+self.shape[dim]) - return self.repeat(*tuple(2 if i in dims else 1 for i in range(self.ndim)))[slices] + dims, rolled = tuple(self._resolve_dim(d) for d in make_tuple(dims, 1)), self + for dim, shift in zip(dims, make_tuple(shifts, 1)): + shift = shift % self.shape[dim] + rolled = Tensor.cat(rolled[tuple(slice(None) if i != dim else slice(-shift, None) for i in range(rolled.ndim))], + rolled[tuple(slice(None) if i != dim else slice(None, -shift) for i in range(rolled.ndim))], dim=dim) + return rolled def rearrange(self, formula:str, **sizes) -> Tensor: """ @@ -1976,7 +1941,7 @@ class Tensor(MathTrait): """ return self.std(axis, keepdim, correction), self.mean(axis, keepdim) - def keccak(self, cfg:str|tuple[int, int]="sha3_256"): + def keccak(self, cfg:str|tuple[int, int] = "sha3_256"): """ Calculates a Keccak hash over the last dimension. Uses "sha3_256" by default. @@ -1988,80 +1953,43 @@ class Tensor(MathTrait): # https://keccak.team/keccak_specs_summary.html - def ctensor(l: Sequence[ConstType], dtype: DType = dtypes.uint64): - # TODO: contiguous is here for compile speed - return Tensor.stack(*(Tensor(v, dtype=dtype, device=self.device) for v in l)).contiguous() + def ctensor(l: Sequence[ConstType], dtype: DType = dtypes.uint64): return Tensor.stack(*(Tensor(v, dtype=dtype, device=self.device) for v in l)) rot_offsets = [44, 43, 21, 14, 28, 20, 3, 45, 61, 1, 6, 25, 8, 18, 27, 36, 10, 15, 56, 62, 55, 39, 41, 2] rot_offsets_v0, rot_offsets_v1 = ctensor([0] + [1 << v for v in rot_offsets]), ctensor([1] + [1 << (64 - v) for v in rot_offsets]) # calculated from π step - reorder_indexes = ctensor([0,6,12,18,24,3,9,10,16,22,1,7,13,19,20,4,5,11,17,23,2,8,14,15,21], dtype=dtypes.int32) + reorder_indexes = [0,6,12,18,24,3,9,10,16,22,1,7,13,19,20,4,5,11,17,23,2,8,14,15,21] rnd_const_masks = [ctensor([v]).pad((0, 24)) for v in (1, 0x8082, 0x800000000000808a, 0x8000000080008000, 0x808b, 0x80000001, 0x8000000080008081, 0x8000000000008009, 0x8a, 0x88, 0x80008009, 0x8000000a, 0x8000808b, 0x800000000000008b, 0x8000000000008089, 0x8000000000008003, 0x8000000000008002, 0x8000000000000080, 0x800a, 0x800000008000000a, 0x8000000080008081, 0x8000000000008080, 0x80000001, 0x8000000080008008)] - rate, dsbyte = {"sha3_224": (144, 6), "sha3_256": (136, 6), "shake_128": (168, 31)}[cfg] if isinstance(cfg, str) else cfg - data, data_pad = self.bitcast(dtypes.uint8).reshape(prod(self.shape[:-1]), self.shape[-1]), rate - (self.shape[-1] * self.dtype.itemsize % rate) + rate, dsbyte = { "sha3_224": (144, 6), "sha3_256": (136, 6), "shake_128": (168, 31) }[cfg] if isinstance(cfg, str) else cfg + data, data_pad = self.bitcast(dtypes.uint8).reshape(prod(self.shape[:-1]), -1), rate - (self.shape[-1] * self.dtype.itemsize % rate) # pad batches then pad blocks - data = data.pad((None, (0, data_pad))).reshape(bs := data.shape[0], -1, rate).pad((None, None, (0, 200 - rate))) + data = data.pad((None, (0, data_pad))).reshape(data.shape[0], -1, rate).pad((None, None, (0, 200 - rate))).flatten(1) # create pad mask - lbe = prod(data.shape[1:]) + rate - data_pad - 200 - if data_pad == 1: mb = [(lbe, 0), (1, dsbyte ^ 0x80), (200 - rate, 0)] - else: mb = [(lbe, 0), (1, dsbyte), (data_pad - 2, 0), (1, 0x80), (200 - rate, 0)] - pad_mask = Tensor.cat(*(Tensor(v, dtype=dtypes.uint8, device=data.device).expand(l) for l, v in mb if l > 0)).unsqueeze(0) + lbe = data.shape[1] + rate - data_pad - 200 + if data_pad == 1: mb = [(lbe, 0), (1, dsbyte ^ 0x80), (data.shape[-1] - lbe - 1, 0)] + else: mb = [(lbe, 0), (1, dsbyte), (data.shape[-1] + rate - lbe - 202, 0), (1, 0x80), (200 - rate, 0)] + pad_mask = Tensor.cat(*(Tensor(v, dtype=dtypes.uint8, device=data.device).expand(l) for l, v in mb if l > 0)) - data = (data.flatten(1) ^ pad_mask).reshape(*data.shape[:2], 200).bitcast(dtypes.uint64) + data = (data ^ pad_mask).reshape(data.shape[0], -1, 200).bitcast(dtypes.uint64) - state = Tensor.zeros(bs, 25, device=self.device, dtype=dtypes.uint64) + state = Tensor.zeros((data.shape[0], 25), device=self.device, dtype=dtypes.uint64) for k in range(int(data.shape[1])): - state = state.bitwise_xor(data[:,k].reshape(bs, 25)) + state = state.bitwise_xor(data[:,k].reshape(-1, 25)) for i in range(24): # f1600 # θ step - p = state.reshape(bs, 5, 5).transpose(2, 1) + p = state.reshape((-1, 5, 5)).transpose(2, 1) t1 = (p[:,:,0] ^ p[:,:,1] ^ p[:,:,2] ^ p[:,:,3] ^ p[:,:,4]).roll(-1, 1) # xor reduce - state = state ^ (t1.roll(2, 1).bitwise_xor((t1 << 1) ^ (t1 >> 63)).unsqueeze(2).expand(bs, 5, 5).transpose(2, 1).flatten(1)) + state = state ^ (t1.roll(2, 1).bitwise_xor((t1 << 1) ^ (t1 >> 63)).unsqueeze(2).expand((-1, -1, 5)).transpose(2, 1).flatten(1)) # ρ and π steps - state = state[:, reorder_indexes] - state = (state * rot_offsets_v0).bitwise_or(state // rot_offsets_v1).reshape(bs, 5, 5) + state = state[:,reorder_indexes] + state = (state * rot_offsets_v0).bitwise_or(state // rot_offsets_v1).reshape((-1, 5, 5)) # χ and ι step - state = state.bitwise_xor(~state.roll(shifts=-1, dims=2) & state.roll(shifts=-2, dims=2)) - state = state.flatten(1) ^ rnd_const_masks[i] - # NOTE: kernelize here to prevent internal stack from growing propotional to data size - state = state.kernelize() - return state.bitcast(dtypes.uint8)[:,:(obytes:=(200 - rate) // 2)].reshape(*self.shape[:-1], obytes) - - def _hash_1mb(self) -> Tensor: - assert self.dtype == dtypes.uint8, "only support uint8 tensors for hashing" - assert self.ndim == 2, "only support batched 1d tensors" - assert self.shape[1] == 1024 * 1024, "only support messages of 1mb" - - blocks = self.shape[0] * self.shape[1] // 4096 - data = self.reshape(blocks, 4096) - block_hashes = data.keccak("shake_128").reshape(self.shape[0], 4096) - return block_hashes.keccak("shake_128").reshape(self.shape[0], 16) - - def hash(self) -> Tensor: - """ - Calculates a 16-byte hash of the tensor. - ```python exec="false source="above" session="tensor" result="python" - t = Tensor(b"Hello World!").hash() - print(t.data().hex()) - ``` - """ - - data = self.flatten().bitcast(dtypes.uint8) - if (tsize := data.shape[0]) % 2**20 != 0: data = data.pad((0, 2**20 - tsize % 2**20)) - base_chunks = ceildiv(data.shape[0], 2**20) - tree_depth = math.ceil(math.log(base_chunks, 65536)) if base_chunks > 1 else 0 - - level_chunks = base_chunks - for _ in range(tree_depth + 1): - data = data.reshape(level_chunks, 2**20)._hash_1mb().flatten() - if (tsize := data.shape[0]) % 2**20 != 0: data = data.pad((0, 2**20 - tsize % 2**20)) - level_chunks = ceildiv(data.shape[0], 2**20) - - return data[:16] + state = state.bitwise_xor((state.roll(shifts=-1, dims=2) ^ -1) & state.roll(shifts=-2, dims=2)).flatten(1) ^ rnd_const_masks[i] + return state.bitcast(dtypes.uint8)[:,:(200 - rate) // 2].reshape(*self.shape[:-1], -1) def _softmax(self, axis, dtype:DTypeLike|None=None) -> tuple[Tensor, Tensor, Tensor]: m = self - self.max(axis=axis, keepdim=True).detach() @@ -2243,7 +2171,7 @@ class Tensor(MathTrait): """ def parse_formula(formula:str, *operands:Tensor): if "..." in (formula := formula.replace(" ", "")): - ell_chars, ell_longest = "".join(c for c in string.ascii_letters if c not in formula), 0 + ell_chars, ell_longest = "".join(set(string.ascii_letters) - set(formula)), 0 for i, inp in enumerate(filter(lambda x: "..." in x, inputs := formula.split("->")[0].split(","))): if (ell_count := max(operands[i].ndim, 1) - (len(inp) - len("..."))) > ell_longest: ell_longest = ell_count inputs[i] = inp.replace("...", ell_chars[-ell_count:]) @@ -2341,6 +2269,8 @@ class Tensor(MathTrait): NOTE: unlike PyTorch, this implementation is not limited to only 2d pooling and instead works for any number of dimensions. + See: https://paperswithcode.com/method/average-pooling + ```python exec="true" source="above" session="tensor" result="python" t = Tensor.arange(25).reshape(1, 1, 5, 5) print(t.avg_pool2d().numpy()) @@ -2387,6 +2317,8 @@ class Tensor(MathTrait): NOTE: unlike PyTorch, this implementation is not limited to only 2d pooling and instead works for any number of dimensions. + See: https://paperswithcode.com/method/max-pooling + ```python exec="true" source="above" session="tensor" result="python" t = Tensor.arange(25).reshape(1, 1, 5, 5) print(t.max_pool2d().numpy()) @@ -2437,7 +2369,7 @@ class Tensor(MathTrait): # https://arxiv.org/pdf/1603.07285 inverse of relationship 15 in section 5.1. output_size = tuple((i-1)*s - (pB+pA) + (d*(k-1)+1) for i,k,d,s,(pA,pB) in zip(spatial_shape,k_,d_,s_,p_)) else: output_size = output_size[-len(spatial_shape):] - ret = (indices.reshape(bs,c,1,-1)._one_hot_along_dim(prod(output_size), 2).where(self.reshape(bs,c,1,-1), 0)).sum(3) + ret = (indices.reshape(bs,c,1,-1)._one_hot_along_dim(prod(output_size), 2) * self.reshape(bs,c,1,-1)).sum(3) return ret.reshape(bs,c,*output_size) def conv2d(self, weight:Tensor, bias:Tensor|None=None, groups=1, stride=1, dilation=1, padding:int|tuple[int, ...]=0, @@ -2688,7 +2620,7 @@ class Tensor(MathTrait): print(t.triu(diagonal=-1).numpy()) ``` """ - return Tensor._tri(self.shape[-2], self.shape[-1], diagonal=diagonal, device=self.device, dtype=dtypes.bool).where(self, self.zeros_like()) + return Tensor._tri(self.shape[-2], self.shape[-1], diagonal=diagonal, device=self.device, dtype=dtypes.bool).where(self, 0).cast(self.dtype) def tril(self, diagonal:int=0) -> Tensor: """ @@ -2711,7 +2643,7 @@ class Tensor(MathTrait): print(t.tril(diagonal=-1).numpy()) ``` """ - return Tensor._tri(self.shape[-2], self.shape[-1], diagonal=diagonal+1, device=self.device, dtype=dtypes.bool).where(self.zeros_like(), self) + return Tensor._tri(self.shape[-2], self.shape[-1], diagonal=diagonal+1, device=self.device, dtype=dtypes.bool).where(0, self).cast(self.dtype) def interpolate(self, size:tuple[int, ...], mode:str="linear", align_corners:bool=False) -> Tensor: """ @@ -2854,11 +2786,12 @@ class Tensor(MathTrait): ``` """ x, dim = self, self._resolve_dim(dim) - if (orig_len:= x.shape[dim]) <= 1: return x, x.zeros_like(dtype=dtypes.default_int) # pad to power of 2 - n_stages = (orig_len-1).bit_length() + orig_len = x.shape[dim] + n_stages = math.ceil(math.log2(orig_len)) + fill_value = dtypes.min(x.dtype) if descending else dtypes.max(x.dtype) pads = tuple((0, 2**n_stages - orig_len) if i == dim else None for i in range(x.ndim)) - x = x.pad(pads, value=dtypes.min(x.dtype) if descending else dtypes.max(x.dtype)).unflatten(dim, (2,)*n_stages) + x = x.pad(pads, value=fill_value).unflatten(dim, (2,)*n_stages) # https://en.wikipedia.org/wiki/Bitonic_sorter#/media/File:BitonicSort1.svg for stage in range(1, n_stages+1): if stage != n_stages: @@ -2876,27 +2809,16 @@ class Tensor(MathTrait): # flip wires back to undo the crossover blue_box, flipped_green_box = x.split(1, crossover_dim) x = blue_box.cat(flipped_green_box.flip(flip_dims), dim=crossover_dim) - x = x.flatten(dim, dim+n_stages-1).shrink(tuple((0, s) for s in self.shape)) + x = x.flatten(dim, dim+n_stages-1).shrink(tuple((0, orig_len) if i == dim else None for i in range(x.ndim))) # compute indices for sorted values - mask = Tensor.ones(orig_len, orig_len, dtype=dtypes.bool, device=self.device).tril().reshape((None, None) + (1,)*(self.ndim-dim-1)) - def compute_counts(t:Tensor): return (mask & (t.unsqueeze(dim) == t.unsqueeze(dim+1))).sum(dim+1) + idx = Tensor.arange(orig_len, requires_grad=False, device=self.device).reshape(tuple(orig_len if i == dim else 1 for i in range(x.ndim))) + idx = idx.expand(x.shape) + def compute_counts(t:Tensor): return ((idx.unsqueeze(dim) <= idx.unsqueeze(dim+1)) & (t.unsqueeze(dim) == t.unsqueeze(dim+1))).sum(dim+1) count_orig, count_sorted = compute_counts(self), compute_counts(x) cond = (self.unsqueeze(dim+1) == x.unsqueeze(dim)) & (count_orig.unsqueeze(dim+1) == count_sorted.unsqueeze(dim)) - idx = Tensor.arange(orig_len, device=self.device).reshape(tuple(orig_len if i == dim else 1 for i in range(x.ndim))) idx = (cond * idx.unsqueeze(dim+1)).sum(dim) return x, idx - def argsort(self, dim:int=-1, descending:bool=False) -> Tensor: - """ - Returns the indices that sort input tensor along given `dimension` in given `descending` order by value. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor([[2, 3, 4, 1], [1, 4, 3, 2]]) - print(t.argsort().numpy()) - ``` - """ - return self.sort(dim, descending)[1] - def topk(self, k:int, dim:int=-1, largest:bool=True, sorted_:bool=True) -> tuple[Tensor, Tensor]: """ Computes the top-k elements of the tensor along the specified `dim`. @@ -2941,11 +2863,11 @@ class Tensor(MathTrait): """ return self*-1 if self.dtype != dtypes.bool else self.logical_not() - def contiguous(self, *args, **kwargs) -> Tensor: + def contiguous(self) -> Tensor: """ Returns a contiguous tensor. """ - return self._apply_uop(UOp.contiguous, extra_args=args, **kwargs) + return self._apply_uop(UOp.contiguous) def fuse(self) -> Tensor: """ @@ -2996,9 +2918,6 @@ class Tensor(MathTrait): print(Tensor([0., 1., 2., 3.]).exp().numpy()) ``` """ - # TODO: make it generic, and same thing to log and cos - if self.is_floating_point(): return self.cast(least_upper_dtype(self.dtype, dtypes.float32)).mul(1/math.log(2)).exp2().cast(self.dtype) - # TODO: behavior when DEFAULT_FLOAT is bfloat16 and input is int32? return self.mul(1/math.log(2)).exp2() def exp2(self) -> Tensor: @@ -3017,6 +2936,8 @@ class Tensor(MathTrait): """ Applies the Rectified Linear Unit (ReLU) function element-wise. + - Described: https://paperswithcode.com/method/relu + ```python exec="true" source="above" session="tensor" result="python" print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).relu().numpy()) ``` @@ -3053,6 +2974,7 @@ class Tensor(MathTrait): Applies the Hardsigmoid function element-wise. NOTE: default `alpha` and `beta` values are taken from torch + - Described: https://paperswithcode.com/method/hard-sigmoid - See: https://pytorch.org/docs/stable/generated/torch.nn.functional.hardsigmoid.html ```python exec="true" source="above" session="tensor" result="python" @@ -3099,7 +3021,6 @@ class Tensor(MathTrait): print(Tensor([0., math.pi/2, math.pi, 3*math.pi/2, 2*math.pi]).cos().numpy()) ``` """ - if self.is_floating_point(): return ((math.pi/2)-self.cast(least_upper_dtype(self.dtype, dtypes.float32))).sin().cast(self.dtype) return ((math.pi/2)-self).sin() def tan(self) -> Tensor: @@ -3155,7 +3076,7 @@ class Tensor(MathTrait): print(Tensor([-3.5, -2.5, -1.5, -0.5, 0.5, 1.5, 2.5, 3.5]).trunc().numpy()) ``` """ - return self._apply_uop(UOp.trunc) + return self.cast(dtypes.int32).cast(self.dtype) def ceil(self: Tensor) -> Tensor: """ @@ -3185,7 +3106,7 @@ class Tensor(MathTrait): print(Tensor([-3.5, -2.5, -1.5, -0.5, 0.5, 1.5, 2.5, 3.5]).round().numpy()) ``` """ - return ((self > 0) == ((b := self.trunc() / 2.0).trunc() == b)).where((self - 0.5).ceil(), (self + 0.5).floor()) + return ((self > 0) == ((b := self.cast(dtypes.int32) / 2.0).cast(dtypes.int32) == b)).where((self - 0.5).ceil(), (self + 0.5).floor()) def isinf(self:Tensor, detect_positive:bool=True, detect_negative:bool=True) -> Tensor: """ @@ -3296,6 +3217,7 @@ class Tensor(MathTrait): """ Applies the Exponential Linear Unit (ELU) function element-wise. + - Described: https://paperswithcode.com/method/elu - Paper: https://arxiv.org/abs/1511.07289v5 ```python exec="true" source="above" session="tensor" result="python" @@ -3308,6 +3230,7 @@ class Tensor(MathTrait): """ Applies the Continuously differentiable Exponential Linear Unit (CELU) function element-wise. + - Described: https://paperswithcode.com/method/celu - Paper: https://arxiv.org/abs/1704.07483 ```python exec="true" source="above" session="tensor" result="python" @@ -3320,6 +3243,7 @@ class Tensor(MathTrait): """ Applies the Scaled Exponential Linear Unit (SELU) function element-wise. + - Described: https://paperswithcode.com/method/selu - Paper: https://arxiv.org/abs/1706.02515v5 ```python exec="true" source="above" session="tensor" result="python" @@ -3344,6 +3268,7 @@ class Tensor(MathTrait): """ Applies the Sigmoid Linear Unit (SiLU) function element-wise. + - Described: https://paperswithcode.com/method/silu - Paper: https://arxiv.org/abs/1606.08415 ```python exec="true" source="above" session="tensor" result="python" @@ -3356,6 +3281,7 @@ class Tensor(MathTrait): """ Applies the ReLU6 function element-wise. + - Described: https://paperswithcode.com/method/relu6 - Paper: https://arxiv.org/abs/1704.04861v1 ```python exec="true" source="above" session="tensor" result="python" @@ -3368,6 +3294,7 @@ class Tensor(MathTrait): """ Applies the Hardswish function element-wise. + - Described: https://paperswithcode.com/method/hard-swish - Paper: https://arxiv.org/abs/1905.02244v5 ```python exec="true" source="above" session="tensor" result="python" @@ -3452,6 +3379,8 @@ class Tensor(MathTrait): """ Applies the Hardtanh function element-wise. + - Described: https://paperswithcode.com/method/hardtanh-activation + ```python exec="true" source="above" session="tensor" result="python" print(Tensor([-1.5, -1.0, -0.5, 0., 0.5, 1.0, 1.5]).hardtanh().numpy()) ``` @@ -3476,6 +3405,7 @@ class Tensor(MathTrait): """ Applies the Gaussian Error Linear Unit (GELU) function element-wise. + - Described: https://paperswithcode.com/method/gelu - Paper: https://arxiv.org/abs/1606.08415v5 ```python exec="true" source="above" session="tensor" result="python" @@ -3488,6 +3418,8 @@ class Tensor(MathTrait): """ Applies the Sigmoid GELU approximation element-wise. + - Described: https://paperswithcode.com/method/gelu + ```python exec="true" source="above" session="tensor" result="python" print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).quick_gelu().numpy()) ``` @@ -3498,6 +3430,8 @@ class Tensor(MathTrait): """ Applies the Leaky ReLU function element-wise. + - Described: https://paperswithcode.com/method/leaky-relu + ```python exec="true" source="above" session="tensor" result="python" print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).leaky_relu().numpy()) ``` @@ -3511,6 +3445,7 @@ class Tensor(MathTrait): """ Applies the Mish function element-wise. + - Described: https://paperswithcode.com/method/mish - Paper: https://arxiv.org/abs/1908.08681v3 ```python exec="true" source="above" session="tensor" result="python" @@ -3519,20 +3454,24 @@ class Tensor(MathTrait): """ return self * self.softplus().tanh() - def softplus(self, beta=1.0) -> Tensor: + def softplus(self, beta=1) -> Tensor: """ Applies the Softplus function element-wise. + - Described: https://paperswithcode.com/method/softplus + ```python exec="true" source="above" session="tensor" result="python" print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).softplus().numpy()) ``` """ - return (1/beta) * (self*beta).logaddexp(0.0) + return (1/beta) * (1 + (self*beta).exp()).log() def softsign(self) -> Tensor: """ Applies the Softsign function element-wise. + - Described: https://paperswithcode.com/method/softsign + ```python exec="true" source="above" session="tensor" result="python" print(Tensor([-3., -2., -1., 0., 1., 2., 3.]).softsign().numpy()) ``` @@ -3548,8 +3487,7 @@ class Tensor(MathTrait): # for each dimension, check either dim is 1, or it does not change if not all(resolve(s == ns) or resolve(s == 1) for s,ns in zip(shape, new_shape)): raise ValueError(f"cannot broadcast {self.shape} to {new_shape=}") - # NOTE: this cast is no-op in forward and uses sum_acc_dtype in the backward sum - return self.reshape(shape).cast(sum_acc_dtype(self.dtype))._apply_uop(UOp.expand, arg=new_shape).cast(self.dtype) + return self.reshape(shape)._apply_uop(UOp.expand, arg=new_shape) def _broadcasted(self, y:Tensor|ConstType|UOp, reverse:bool=False, match_dtype:bool=True) -> tuple[Tensor, Tensor]: x: Tensor = self @@ -3693,11 +3631,11 @@ class Tensor(MathTrait): """ base, exponent = self._broadcasted(x, reverse=reverse) # TODO: int pow - if not base.is_floating_point() and not (isinstance(x, int) and x >= 0): raise RuntimeError("base needs to be float") + if not base.is_floating_point(): raise RuntimeError("base needs to be float") ret = base._apply_uop(UOp.pow, exponent) # NOTE: pow(int, float) -> int - return ret.round().cast(self.dtype) if not reverse and not dtypes.is_float(self.dtype) and dtypes.is_float(exponent.dtype) else ret + return ret.round().cast(self.dtype) if not reverse and not dtypes.is_float(self.dtype) else ret def maximum(self, x:Tensor|ConstType) -> Tensor: """ @@ -3759,13 +3697,6 @@ class Tensor(MathTrait): # TODO: remove other*0? return (other < 0).where(-self.abs(), self.abs()) + other*0 - def logaddexp(self, other) -> Tensor: - """ - Calculates (self.exp()+other.exp()).log(), elementwise. - """ - m = self.maximum(other) - return ((self-m).exp() + (self._broadcasted(other)[1]-m).exp()).log() + m - # ***** op wrappers ***** def __invert__(self) -> Tensor: return self.bitwise_not() @@ -3833,6 +3764,7 @@ class Tensor(MathTrait): """ Applies Layer Normalization over a mini-batch of inputs. + - Described: https://paperswithcode.com/method/layer-normalization - Paper: https://arxiv.org/abs/1607.06450v1 ```python exec="true" source="above" session="tensor" result="python" @@ -3851,6 +3783,7 @@ class Tensor(MathTrait): """ Applies Batch Normalization over a mini-batch of inputs. + - Described: https://paperswithcode.com/method/batch-normalization - Paper: https://arxiv.org/abs/1502.03167 ```python exec="true" source="above" session="tensor" result="python" @@ -3875,6 +3808,7 @@ class Tensor(MathTrait): NOTE: dropout is only applied when `Tensor.training` is `True`. + - Described: https://paperswithcode.com/method/dropout - Paper: https://jmlr.org/papers/v15/srivastava14a.html ```python exec="true" source="above" session="tensor" result="python" @@ -3884,9 +3818,7 @@ class Tensor(MathTrait): print(t.dropout().numpy()) ``` """ - if not 0 <= p <= 1: raise ValueError(f"{p=} is out of range [0, 1]") if not Tensor.training or p == 0: return self - if p == 1: return self.zeros_like() return (Tensor.rand_like(self, requires_grad=False, dtype=dtypes.default_float, contiguous=False) >= p).contiguous().where(self, 0) / (1.0 - p) # helper function commonly used for indexing @@ -3910,12 +3842,12 @@ class Tensor(MathTrait): if num_classes == -1: num_classes = (self.max()+1).item() return self[..., None]._one_hot_along_dim(num_classes).where(1, 0) - def scaled_dot_product_attention(self, key:Tensor, value:Tensor, attn_mask:Tensor|None=None, dropout_p:float=0.0, - is_causal:bool=False, enable_gqa:bool=False) -> Tensor: + def scaled_dot_product_attention(self, key:Tensor, value:Tensor, attn_mask:Tensor|None=None, dropout_p:float=0.0, is_causal:bool=False) -> Tensor: """ Computes scaled dot-product attention. `self` is the query tensor, `key` is the key tensor, and `value` is the value tensor. + - Described: https://paperswithcode.com/method/scaled - Paper: https://arxiv.org/abs/1706.03762v7 ```python exec="true" source="above" session="tensor" result="python" @@ -3927,15 +3859,7 @@ class Tensor(MathTrait): """ # NOTE: it also works when `key` and `value` have symbolic shape. assert all_int(self.shape), f"does not support symbolic shape {self.shape}" - # GQA: https://docs.pytorch.org/docs/stable/generated/torch.nn.functional.scaled_dot_product_attention.html - if enable_gqa: - key = key.repeat_interleave(self.shape[-3] // key.shape[-3], dim=-3) - value = value.repeat_interleave(self.shape[-3] // value.shape[-3], dim=-3) - - if FUSE_ATTENTION: q, key, value = self.contiguous(), key.contiguous(), value.contiguous() - else: q = self - - qk = q.matmul(key.transpose(-2,-1), dtype=least_upper_dtype(q.dtype, key.dtype, dtypes.float32)) / math.sqrt(q.shape[-1]) + qk = self.matmul(key.transpose(-2,-1), dtype=least_upper_dtype(self.dtype, key.dtype, dtypes.float32)) / math.sqrt(self.shape[-1]) # handle attention mask if is_causal: if attn_mask is not None: raise RuntimeError("cannot set attn_mask when is_causal=True") @@ -3943,8 +3867,7 @@ class Tensor(MathTrait): if attn_mask is not None: if attn_mask.dtype == dtypes.bool: attn_mask = attn_mask.where(0, -float("inf")) qk = qk + attn_mask - attn = qk.cast(self.dtype).softmax(-1).dropout(dropout_p) @ value - return attn.fuse() if FUSE_ATTENTION else attn + return qk.cast(self.dtype).softmax(-1).dropout(dropout_p) @ value def _do_reduction(self, reduction:ReductionStr="mean") -> Tensor: if reduction not in get_args(ReductionStr): raise ValueError(f"{reduction=} must be one of {get_args(ReductionStr)}") @@ -3996,10 +3919,10 @@ class Tensor(MathTrait): ``` """ assert 0.0 <= label_smoothing <= 1.0, "label_smoothing must be in [0.0, 1.0]" - assert reduction in get_args(ReductionStr), f"reduction must be one of {get_args(ReductionStr)}" - log_probs = self.log_softmax() - loss_mask = (Y != ignore_index) if ignore_index != -1 else Y.ones_like(dtype=dtypes.bool) - y = Y.to(self.device).unsqueeze(-1)._one_hot_along_dim(self.shape[-1], dim=-1) * loss_mask.unsqueeze(-1) + assert reduction in ("mean", "sum", "none"), "reduction must be one of ['mean', 'sum', 'none']" + log_probs, loss_mask = self.log_softmax(), (Y != ignore_index) if ignore_index != -1 else Y.ones_like(dtype=dtypes.bool) + y_counted = Y.to(self.device).flatten().reshape(-1, 1)._one_hot_along_dim(self.shape[-1]) + y = (y_counted * loss_mask.reshape(-1, 1)).reshape(*Y.shape, self.shape[-1]) smoothing = label_smoothing * (log_probs.mean(-1) * loss_mask) unreduced = ((1 - label_smoothing) * (log_probs * y).sum(-1) + smoothing) # NOTE: because of ignore_index, we can't use Tensor.mean (so can't use `_do_reduction` here) @@ -4056,87 +3979,6 @@ class Tensor(MathTrait): nll = -self.gather(1, Y.unsqueeze(1)).squeeze(1) * masked_weight return nll.sum() / masked_weight.sum() if reduction == "mean" else nll._do_reduction(reduction) - def newton_schulz(self, steps:int, params:tuple[int, ...], eps:float=1.0e-7) -> Tensor: - """ - Performs the newton-schulz algorithm for odd polynomials. The degree of the odd polynomial depends on the number of params. - - ```python exec="true" source="above" session="tensor" result="python" - t = Tensor.randn(4, 4) - print(t.newton_schulz(steps=5, params=(2,-1.5,0.5)).numpy()) - ``` - """ - assert self.ndim > 1, "NS only works for two or more dims" - G = self / (self.square().sum(axis=(-2, -1), keepdim=True).sqrt() + eps) - G = G.transpose(-2, -1) if self.shape[-2] > self.shape[-1] else G - for _ in range(steps): G = sum(p * functools.reduce(lambda x, y: (y @ y.transpose(-2, -1)) @ x, [G]*i, G) for i,p in enumerate(params)) - return G.transpose(-2, -1) if self.shape[-2] > self.shape[-1] else G - - def qr(self) -> tuple[Tensor, Tensor]: - assert self.ndim > 1, f"expected two or more dimensions, got {self.ndim}" - R = self.clone() - b_shape, m, n = self.shape[0:self.ndim - 2], int(R.shape[-2]), int(R.shape[-1]) - Q = Tensor.eye(m, dtype = self.dtype).reshape((1,) * (len(self.shape) - 2) + 2 * (m,)).expand(b_shape + 2 * (m,)).contiguous() - for i in range(int(min(m, n))): - x = R[..., i:m, i] - s = -x[..., 0].sign() - u1 = x[..., 0] - s * x.square().sum(-1).sqrt() - w = x.unsqueeze(-1) / u1.reshape(b_shape + 2 * (1,)) - w[..., 0, 0] = 1 - tau = (-s * u1 / x.square().sum(-1).sqrt()).reshape(b_shape + 2 * (1,)).expand(w.shape) - R[..., i:m, :] = R[..., i:m, :] - (w * tau) @ (w.transpose(-2, -1) @ R[..., i:m, :]) - Q[..., :, i:m] = Q[..., :, i:m] - (Q[..., :, i:m] @ w) @ (tau.transpose(-2, -1) * w.transpose(-2, -1)) - return Q,R - - def svd(self, full_matrices = True) -> tuple[Tensor, Tensor, Tensor]: - #partial implementation of https://www.netlib.org/lapack/lawnspdf/lawn169.pdf , pg 26 - assert self.ndim > 1, f"expected two or more dimensions, got {self.ndim}" - b_shape, m, n = self.shape[:-2], int(self.shape[-2]), int(self.shape[-1]) - #preprocess the matrix - Q, R = (Tensor.qr(self) if m >= n else Tensor.qr(self.transpose(-2, -1))) - num, q_num = int(min(m, n)), int(max(m, n)) - U = R.shrink(tuple([(0, self.shape[i]) for i in range(self.ndim - 2)] + [(0, num), (0, num)])).contiguous() - V = Tensor.eye(num, dtype = self.dtype).reshape((1,) * (self.ndim - 2) + (num, num)).expand(b_shape + 2 * (num,)).contiguous() - #prepare round robin pairing - permute, inverse_permute = Tensor.arange(0, num, dtype = dtypes.int), Tensor.zeros(num, dtype = dtypes.int).contiguous() - permute[num//2:num] = permute[num//2:num].flip(0) - inverse_permute[permute] = Tensor.arange(num, dtype = dtypes.int) - def one_round_jacobi(U, V,permute,inverse_permute): - #pair all the columns - V_permuted, runoff_V = (V[..., permute].split(num - 1, -1)) if num % 2 == 1 else (V[..., permute], None) - V_left, V_right = V_permuted.split(num//2, -1) - U_permuted, runoff_U = (U[..., permute].split(num - 1, -1)) if num % 2 == 1 else (U[..., permute], None) - U_left, U_right = U_permuted.split(num//2, -1) - #compute the jacobi rotations for each pairing - gamma = (U_left * U_right).sum(-2).reshape(b_shape + (1, num//2)) - alpha, beta = U_permuted.square().sum(-2).unsqueeze(-2).split(num//2, -1) - tau = (beta - alpha) / (2 * gamma) - t = tau.sign() / (tau.abs() + (1 + tau.square()).sqrt()) - c = 1 / (1 + t.square()).sqrt() - s = c * t - #apply the rotations - U_left, U_right = c * U_left - s * U_right, s * U_left + c * U_right - U = U_left.cat(U_right.cat(runoff_U, dim = -1) if num % 2 == 1 else U_right, dim = -1)[..., inverse_permute] - V_left, V_right = c * V_left - s * V_right, s * V_left + c * V_right - V = V_left.cat(V_right.cat(runoff_V, dim = -1) if num % 2 == 1 else V_right, dim = -1)[..., inverse_permute] - #prepare the next round robin pairings - if num % 2 == 1: permute = ((permute - 1) % num) - else: permute = permute[0].reshape(1).cat(((permute[1:num] - 2) % (num - 1)) + 1) - inverse_permute = inverse_permute.scatter(0,permute,Tensor.arange(num,dtype=dtypes.int32)) - return U, V, permute, inverse_permute - max_iterations, iterations_per_round = 1, int((num) * math.log2(num) * 2 + 2)#sorta heuristic, most use num*log2(num) - for _ in range(max_iterations * iterations_per_round): U, V, permute, inverse_permute = one_round_jacobi(U, V, permute, inverse_permute) - #extract singular values and sort. construct U from Q - S, indices = U.square().sum(-2).sqrt().sort(dim = -1, descending=True) - new_indices = Tensor.arange(num).reshape((1,) * (self.ndim - 1) + (num,)).expand(b_shape + 2 * (num,)).contiguous() - new_indices[..., :num] = indices.reshape(b_shape + (1,) + (num,)).expand(b_shape + 2 * (num,)) - U,V = U.gather(-1, new_indices[...,0:num,0:num]) / S.unsqueeze(-2), V.gather(-1, new_indices[..., 0:num, 0:num]).realize() - - padded_u = Tensor.eye(q_num, dtype = U.dtype).reshape((1,) * (self.ndim - 2) + 2 * (q_num,)).expand(b_shape + 2 * (q_num,)).contiguous() - padded_u[..., 0:num, 0:num] = U - U = Q @ padded_u - if not full_matrices: U, V = U[..., 0:num], V[..., 0:num] - return (U, S, V.transpose(-2,-1)) if m >= n else (V, S, U.transpose(-2, -1)) - # ***** Tensor Properties ***** @property @@ -4327,11 +4169,6 @@ class Tensor(MathTrait): """ return self.cast(dtypes.bool) - def bfloat16(self) -> Tensor: return self.cast(dtypes.bfloat16) - def double(self) -> Tensor: return self.cast(dtypes.double) - def long(self) -> Tensor: return self.cast(dtypes.long) - def short(self) -> Tensor: return self.cast(dtypes.short) - # *** image Tensor function replacements *** def image_dot(self, w:Tensor, dtype:DTypeLike|None=None) -> Tensor: @@ -4412,16 +4249,6 @@ class Tensor(MathTrait): P = ParamSpec("P") T = TypeVar("T") - -# this tracks the tensor.py METADATA, contextvars.ContextVar was switched to this due to thread safety issues -class _ContextVar(Generic[T]): - def __init__(self, default:T): self.state:T = default - def get(self) -> T: return self.state - def set(self, x:T) -> T: - ret, self.state = self.state, x - return ret -_METADATA: _ContextVar[Metadata|None] = _ContextVar(default=None) - def _metadata_wrapper(fn: Callable[P, T]) -> Callable[P, T]: def _wrapper(*args: P.args, **kwargs: P.kwargs) -> T: if _METADATA.get() is not None: return fn(*args, **kwargs) @@ -4450,7 +4277,7 @@ def _metadata_wrapper(fn: Callable[P, T]) -> Callable[P, T]: token = _METADATA.set(Metadata(name=fn.__name__, caller=caller)) ret = fn(*args, **kwargs) - _METADATA.set(token) + _METADATA.reset(token) return ret return _wrapper diff --git a/tinygrad_repo/tinygrad/uop/__init__.py b/tinygrad_repo/tinygrad/uop/__init__.py index 2a453a7f6..a0ad51007 100644 --- a/tinygrad_repo/tinygrad/uop/__init__.py +++ b/tinygrad_repo/tinygrad/uop/__init__.py @@ -9,91 +9,73 @@ class FastEnum(IntEnum): # the order of these Ops controls the order of the toposort class Ops(FastEnum): # uops that aren't rendered - NOOP = auto(); SINK = auto(); UNIQUE = auto(); DEVICE = auto(); KERNEL = auto(); PRECAST = auto(); REWRITE_ERROR = auto() # noqa: E702 + SINK = auto(); CONTIGUOUS = auto(); CONTIGUOUS_BACKWARD = auto(); DETACH = auto(); KERNEL = auto(); UNIQUE = auto() # noqa: E702 - # track children - CHILD = auto(); CHILDREN = auto() # noqa: E702 + # MetaOps + COPY = auto(); BUFFER_VIEW = auto(); MSELECT = auto(); MSTACK = auto() # noqa: E702 - # buffer ops - COPY = auto(); BUFFER = auto(); BUFFER_VIEW = auto(); MSELECT = auto(); MSTACK = auto() # noqa: E702 - - # create buffer - BUFFERIZE = auto() - - # ops that adjust the behavior of the scheduler - CONTIGUOUS = auto(); CONTIGUOUS_BACKWARD = auto(); DETACH = auto(); FUSE = auto() # noqa: E702 - - # blocks in linearizer (only used there) + # blocks in linearizer BLOCK = auto(); BLOCKSTART = auto(); BLOCKEND = auto(); BLOCKFINAL = auto() # noqa: E702 - # movement ops! these only exist in the tensor graph + # movement ops! RESHAPE = auto(); PERMUTE = auto(); EXPAND = auto(); PAD = auto(); SHRINK = auto(); FLIP = auto() # noqa: E702 - MULTI = auto() # MULTI is really a movement op - # view is what all movement ops become - VIEW = auto() - - # TODO: remove VALID with the VIEW(CONST(DEVICE)) refactor - VALID = auto() - - # TODO: unify these ops into the levels of the memory hierarchy. depends on ASSIGN is STORE - DEFINE_GLOBAL = auto(); DEFINE_LOCAL = auto(); DEFINE_REG = auto() # noqa: E702 - - # this is for symbolic shapes - DEFINE_VAR = auto(); BIND = auto() # noqa: E702 - - # this is a RANGE for GPU dimensions, similar to symbolic shapes but not exactly - SPECIAL = auto() + # misc ops + UNROLL = auto(); CONTRACT = auto() # noqa: E702 + VIEW = auto(); DEFINE_GLOBAL = auto(); BUFFER = auto() # noqa: E702 + DEFINE_VAR = auto(); DEFINE_LOCAL = auto(); DEFINE_ACC = auto() # noqa: E702 + VALID = auto(); SPECIAL = auto(); NOOP = auto() # noqa: E702 # reduce REDUCE_AXIS = auto(); REDUCE = auto(); ALLREDUCE = auto() # noqa: E702 - # optimization helper ops - UNROLL = auto(); CONTRACT = auto(); GEP = auto(); VECTORIZE = auto(); CAT = auto(); PTRCAT = auto() # noqa: E702 + # helper ops + GEP = auto(); VECTORIZE = auto(); CAT = auto(); PTRCAT = auto() # noqa: E702 # UnaryOps - CAST = auto(); BITCAST = auto(); EXP2 = auto(); LOG2 = auto(); SIN = auto(); SQRT = auto(); RECIP = auto(); NEG = auto(); TRUNC = auto() # noqa: E702 + CAST = auto(); BITCAST = auto(); EXP2 = auto(); LOG2 = auto(); SIN = auto(); SQRT = auto(); RECIP = auto(); NEG = auto() # noqa: E702 # load/store before math LOAD = auto(); STORE = auto() # noqa: E702 - ASSIGN = auto() # TODO: ASSIGN is STORE, remove ASSIGN - # tensor core math op, not elementwise - WMMA = auto() - - # INDEX is a BinaryOp similar to ADD, but it operates on pointers + # early INDEX INDEX = auto() + # math ops + WMMA = auto() + # BinaryOps - ADD = auto(); MUL = auto(); SHL = auto(); SHR = auto(); IDIV = auto(); MAX = auto(); MOD = auto() # noqa: E702 - CMPLT = auto(); CMPNE = auto(); CMPEQ = auto() # noqa: E702 - XOR = auto(); OR = auto(); AND = auto() # noqa: E702 - THREEFRY = auto(); SUB = auto(); FDIV = auto(); POW = auto() # noqa: E702 + ADD = auto(); MUL = auto(); SHL = auto(); SHR = auto(); IDIV = auto(); MAX = auto(); MOD = auto(); CMPLT = auto(); CMPNE = auto() # noqa: E702 + EQ = auto(); XOR = auto(); OR = auto(); AND = auto(); THREEFRY = auto(); SUB = auto(); FDIV = auto(); POW = auto() # noqa: E702 # TernaryOps WHERE = auto(); MULACC = auto() # noqa: E702 - # control flow ops - BARRIER = auto(); RANGE = auto(); IF = auto(); ENDRANGE = auto(); ENDIF = auto() # noqa: E702 + # assignment ops + ASSIGN = auto() + BIND = auto() - # consts. VCONST is a vectorized const + # control flow ops + BARRIER = auto(); RANGE = auto(); IF = auto(); ENDRANGE = auto(); ENDIF = auto(); GBARRIER = auto() # noqa: E702 + + # consts last! VCONST = auto(); CONST = auto() # noqa: E702 - # CUSTOM/CUSTOMI are used to output strings into codegen. the I makes the string inline + # device + DEVICE = auto() + MULTI = auto() + + # CUSTOMI is inline CUSTOM = auto(); CUSTOMI = auto() # noqa: E702 + FUSE = auto() class GroupOp: - Unary = {Ops.EXP2, Ops.LOG2, Ops.SIN, Ops.SQRT, Ops.RECIP, Ops.NEG, Ops.TRUNC} - Binary = {Ops.ADD, Ops.MUL, Ops.IDIV, Ops.MAX, Ops.MOD, Ops.CMPLT, Ops.CMPNE, Ops.CMPEQ, - Ops.XOR, Ops.SHL, Ops.SHR, Ops.OR, Ops.AND, Ops.THREEFRY, Ops.SUB, Ops.FDIV, Ops.POW} + Unary = {Ops.EXP2, Ops.LOG2, Ops.SIN, Ops.SQRT, Ops.RECIP, Ops.NEG} + Binary = {Ops.ADD, Ops.MUL, Ops.IDIV, Ops.MAX, Ops.MOD, Ops.CMPLT, Ops.CMPNE, Ops.XOR, Ops.SHL, Ops.SHR, Ops.OR, Ops.AND, Ops.THREEFRY, + Ops.SUB, Ops.FDIV, Ops.POW} Ternary = {Ops.WHERE, Ops.MULACC} ALU = set.union(Unary, Binary, Ternary) - # TODO: is BITCAST always Elementwise if it's shape changing? - Elementwise = set.union(ALU, {Ops.CAST, Ops.BITCAST}) - - Defines = {Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL, Ops.DEFINE_REG} - Irreducible = {Ops.CONST, Ops.DEFINE_VAR, Ops.SPECIAL, Ops.RANGE} Movement = {Ops.RESHAPE, Ops.EXPAND, Ops.PERMUTE, Ops.PAD, Ops.SHRINK, Ops.FLIP} @@ -101,7 +83,7 @@ class GroupOp: Block = {Ops.BLOCK, Ops.BLOCKEND, Ops.BLOCKSTART} # BinaryOps that can be flipped - Commutative = {Ops.ADD, Ops.MUL, Ops.MAX, Ops.CMPNE, Ops.CMPEQ, Ops.XOR, Ops.AND, Ops.OR} + Commutative = {Ops.ADD, Ops.MUL, Ops.MAX, Ops.CMPNE, Ops.XOR, Ops.AND, Ops.OR} # BinaryOps where f(f(a,b),c) = f(a,f(b,c)) Associative = {Ops.ADD, Ops.MUL, Ops.AND, Ops.OR, Ops.MAX} @@ -109,9 +91,6 @@ class GroupOp: # BinaryOps that satisfy f(x,x)=x see https://en.wikipedia.org/wiki/Idempotence Idempotent = {Ops.OR, Ops.AND, Ops.MAX} - # These can change the dtype to bool - Comparison = {Ops.CMPLT, Ops.CMPNE, Ops.CMPEQ} - # do not preserve f(0) = 0 UnsafePad = {Ops.RECIP, Ops.LOG2, Ops.EXP2, Ops.IDIV, Ops.POW} diff --git a/tinygrad_repo/tinygrad/uop/mathtraits.py b/tinygrad_repo/tinygrad/uop/mathtraits.py index 05bf89d8b..b90fa37be 100644 --- a/tinygrad_repo/tinygrad/uop/mathtraits.py +++ b/tinygrad_repo/tinygrad/uop/mathtraits.py @@ -4,7 +4,7 @@ from tinygrad.dtype import dtypes class MathTrait: # required to implement - def alu(self:T, op:Ops, *src) -> T: raise NotImplementedError + def alu(self:T, arg:Ops, *src) -> T: raise NotImplementedError def const_like(self:T, b) -> T: raise NotImplementedError # great functions you get! @@ -161,7 +161,6 @@ class MathTrait: raise RuntimeError("where needs at least one UOp arg") def threefry(self, seed): return self.alu(Ops.THREEFRY, seed) def reciprocal(self): return self.alu(Ops.RECIP) - def trunc(self): return self.alu(Ops.TRUNC) def sqrt(self): return self.alu(Ops.SQRT) def sin(self): return self.alu(Ops.SIN) def log2(self): return self.alu(Ops.LOG2) diff --git a/tinygrad_repo/tinygrad/uop/ops.py b/tinygrad_repo/tinygrad/uop/ops.py index ac5f56c4f..21d15b61e 100644 --- a/tinygrad_repo/tinygrad/uop/ops.py +++ b/tinygrad_repo/tinygrad/uop/ops.py @@ -1,20 +1,16 @@ from __future__ import annotations -from typing import Any, Callable, cast, TYPE_CHECKING, Type, Sequence +from typing import Any, Optional, Union, Callable, cast, TYPE_CHECKING, Type, Sequence import sys, time, functools, itertools, math, operator, hashlib, os, types, pickle, pathlib, inspect, weakref from dataclasses import dataclass, field -from enum import Enum, auto from tinygrad.uop import Ops, GroupOp from tinygrad.uop.mathtraits import MathTrait -from tinygrad.dtype import ConstType, ImageDType, dtypes, DType, truncate, PtrDType -from tinygrad.helpers import ContextVar, all_int, prod, getenv, all_same, Context, partition, temp, unwrap, T, argfix, Metadata, flatten, TRACEMETA -from tinygrad.helpers import PICKLE_BUFFERS, PROFILE, dedup, cdiv, cmod, diskcache_put, to_function_name, cpu_profile, TracingKey +from tinygrad.dtype import ConstType, ImageDType, dtypes, DType, truncate +from tinygrad.helpers import ContextVar, all_int, prod, getenv, all_same, Context, partition, temp, unwrap, T, argfix, Metadata, flatten +from tinygrad.helpers import PICKLE_BUFFERS, PROFILE, dedup, cdiv, cmod, diskcache_put, to_function_name if TYPE_CHECKING: from tinygrad.shape.shapetracker import ShapeTracker from tinygrad.device import Buffer, MultiBuffer -class AxisType(Enum): - GLOBAL = auto(); LOCAL = auto(); LOOP = auto(); GROUP_REDUCE = auto(); REDUCE = auto(); UPCAST = auto(); UNROLL = auto() # noqa: E702 - # https://en.wikipedia.org/wiki/Identity_element def identity_element(op:Ops, dt:DType) -> ConstType: return dtypes.as_const({Ops.ADD:0, Ops.MUL:1, Ops.MAX:dtypes.min(dt)}[op], dt) @@ -37,7 +33,7 @@ def smin(*lst): return _suop(argfix(*lst), UOp.minimum, min) def srender(x) -> str: return x.render() if isinstance(x, UOp) else str(x) def ssimplify(uop): return uop.ssimplify() if isinstance(uop, UOp) else uop -def sym_infer(uop: UOp|int, var_vals: dict[UOp, int]) -> int: return uop.sym_infer(var_vals) if isinstance(uop, UOp) else uop +def sym_infer(uop: Union[UOp, int], var_vals: dict[UOp, int]) -> int: return uop.sym_infer(var_vals) if isinstance(uop, UOp) else uop # used for UOp and UPat def pretty_print(x:Any, rep:Callable, srcfn=lambda x: x.src, cache=None, d=0)->str: @@ -139,40 +135,19 @@ class UOp(MathTrait, metaclass=UOpMetaClass): @functools.cached_property def st(self) -> ShapeTracker|None: - if self.op is Ops.INDEX and self.src[0].op in {Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL, Ops.DEFINE_REG, - Ops.BUFFER, Ops.BUFFERIZE, Ops.VECTORIZE, Ops.STORE}: - return None - if self.op is Ops.BARRIER: return None - if self.op in GroupOp.Block: return None from tinygrad.shape.shapetracker import ShapeTracker # VIEW and MovementOps define a new ShapeTracker from the arg if self.op is Ops.VIEW: return self.arg - if self.op is Ops.BUFFERIZE: return ShapeTracker.from_shape((prod(tuple([int(r.vmax+1) for r in self.src[1:]])),)) - #if self.op is Ops.BUFFERIZE: return ShapeTracker.from_shape(tuple([r.vmax+1 for r in self.src[1:]])) - # allow reshape from nothing - if self.op is Ops.RESHAPE and self.src[0].st is None: return ShapeTracker.from_shape(self.arg) if self.op in GroupOp.Movement: return unwrap(self.src[0].st).mop(self.op, self.arg) # CONST with a DEVICE has a shape of () if self.op is Ops.CONST and len(self.src) and self.src[0].op is Ops.DEVICE: return ShapeTracker.from_shape(()) - if self.op is Ops.STORE and isinstance(self.dtype, PtrDType): return ShapeTracker.from_shape((self.dtype.size,)) # BufferOps and ASSIGN flow ShapeTracker from a direct edge - if self.op in {Ops.STORE, Ops.ASSIGN, Ops.LOAD}: return self.src[0].st if self.op in GroupOp.Buffer: return views[0] if (views:=[x.st for x in self.src if x.op is Ops.VIEW]) else None + if self.op is Ops.ASSIGN: return self.src[0].st # BUFFER/BUFFER_VIEW and KERNEL only have a size if self.op in {Ops.BUFFER, Ops.BUFFER_VIEW}: return ShapeTracker.from_shape((self.size,)) if self.op is Ops.KERNEL: return ShapeTracker.from_shape((self.arg.ast.size,)) - if self.op in {Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL, Ops.DEFINE_REG}: - sz = cast(PtrDType, self.dtype).size - return ShapeTracker.from_shape((sz,)) if sz > 0 else None - - # CONTIGUOUS with RANGE - # TODO: how are these not RANGE? - if self.op is Ops.CONTIGUOUS and len(self.src) > 1 and all(x.op is Ops.RANGE for x in self.src[1:]): - return ShapeTracker.from_shape((tuple([int(x.vmax+1) for x in self.src[1:]])+self.src[0].shape)) - - # hack for PTX, CASTing the ptr loses the shape - if self.op is Ops.CAST and self.src[0].op is Ops.DEFINE_GLOBAL: return None # otherwise we get the shape from sources if not (src_sts := [x.st for x in self.src if x.st is not None]): return None @@ -191,36 +166,20 @@ class UOp(MathTrait, metaclass=UOpMetaClass): if self.op is Ops.VIEW: return self.shape # NOTE: if a parent doesn't have st its full_shape is empty parent_shapes = [x.full_shape for x in self.src] - return tuple(smax(x) for x in itertools.zip_longest(*parent_shapes, fillvalue=1)) + return tuple(smax(x) for x in zip(*[x for x in parent_shapes if x != ()])) @property - def shape(self) -> tuple[sint, ...]: - assert self.st is not None, f"{self.op} doesn't have a shape" - return unwrap(self.st).shape + def shape(self) -> tuple[sint, ...]: return unwrap(self.st).shape @property def size(self) -> int: return self.arg[0] if self.op is Ops.BUFFER_VIEW else self.arg if self.op is Ops.BUFFER else unwrap(self.st).size - # determine what ranges this is in - @functools.cached_property - def ranges(self) -> dict[UOp, None]: - if self.op is Ops.RANGE: return {self:None} - range_start = {Ops.BUFFERIZE: 1, Ops.REDUCE: 1, Ops.STORE: 2, Ops.WMMA: 3} - ret: dict[UOp, None] = {} - if self.op in range_start.keys(): - for s in self.src[:range_start[self.op]]: ret.update(s.ranges) - for s in UOp.sink(*self.src[range_start[self.op]:]).ranges: - if s in ret: del ret[s] - else: - for s in self.src: ret.update(s.ranges) - return ret - # *** uop evaluation *** - def simplify(self, tracked=False): + def simplify(self): # late import! from tinygrad.uop.symbolic import symbolic - with Context(TRACK_MATCH_STATS=0 if not tracked else TRACK_MATCH_STATS.value): - return graph_rewrite(self, symbolic, name="simplify") - def ssimplify(self) -> UOp|ConstType: return ret.arg if (ret:=self.simplify()).op is Ops.CONST else ret + with Context(TRACK_MATCH_STATS=0): + return graph_rewrite(self, symbolic) + def ssimplify(self) -> Union[UOp, ConstType]: return ret.arg if (ret:=self.simplify()).op is Ops.CONST else ret def _eval(self, dtype, expected_type:Type[T]) -> T: assert self.dtype in dtype, f"eval with wrong dtype {self}" vmin, vmax = (simple_self:=self.simplify())._min_max @@ -248,12 +207,9 @@ class UOp(MathTrait, metaclass=UOpMetaClass): ret = self.arg[1] if self.op is Ops.REDUCE_AXIS else self.arg[7] assert isinstance(ret, tuple) and all(isinstance(x, int) for x in ret), f"axis_arg trying to return {ret}" return ret - def sink(*srcs:UOp|None, **kwargs): # pylint: disable=no-self-argument - return UOp(Ops.SINK, dtypes.void, tuple([x for x in srcs if x is not None]), **kwargs) + def sink(self, *srcs:UOp|None, **kwargs): return UOp(Ops.SINK, dtypes.void, (self,)+tuple([x for x in srcs if x is not None]), **kwargs) def detach(self): return UOp(Ops.DETACH, self.dtype, (self,)) - def index(self, *srcs:UOp|None, **kwargs): - return UOp(Ops.INDEX, kwargs.pop("dtype", self.dtype), (self,)+tuple([x for x in srcs if x is not None]), **kwargs) - def __getitem__(self, idx): return self.index(idx) + def index(self, idx:UOp, valid:UOp|None=None): return UOp(Ops.INDEX, self.dtype, (self,idx,valid) if valid is not None else (self,idx)) def const_like(self, b:ConstLike): # constants can optionally have a DEVICE source return UOp.const(self.dtype, b, device=self._device, shape=self.shape if self.st is not None else None) @@ -262,12 +218,11 @@ class UOp(MathTrait, metaclass=UOpMetaClass): if count == 1: return self return UOp(Ops.VECTORIZE, self.dtype.vec(count), (self,)*count) def cast(self, dtype:DType): - # TODO: we shouldn't have to check for dtype.count == 1 here, but CAST is misused in AMD LLVM - if dtype.count == 1 and dtype.count != self.dtype.count: dtype = dtype.vec(self.dtype.count) if self.dtype == dtype: return self return UOp(Ops.CAST, dtype, (self,)) + def cast_vec(self, dtype:DType): return UOp(Ops.CAST, dtype.vec(self.dtype.count), (self,)) def bitcast(self, dtype:DType): return UOp(Ops.BITCAST, dtype, (self,)) - def gep(self, i:tuple[int, ...]|int): + def gep(self, i:Union[tuple[int, ...], int]): if isinstance(i, tuple) and len(i) == 1: return self.gep(i[0]) if isinstance(i, int): # NOTE: these are just shortcuts to not have to create and fold later @@ -276,14 +231,14 @@ class UOp(MathTrait, metaclass=UOpMetaClass): if self.op is Ops.CONST: return UOp.const(self.dtype.scalar(), self.arg) i = (i,) return UOp(Ops.GEP, self.dtype.scalar().vec(len(i)) if len(i) > 1 else self.dtype.scalar(), (self,), i) - def load(self, *src:UOp, **kwargs): return UOp(Ops.LOAD, dtype=kwargs.pop("dtype", self.dtype.base), src=(self,)+src, **kwargs) - def store(self, *src:UOp, **kwargs): return UOp(Ops.STORE, kwargs.pop("dtype", dtypes.void), (self,)+src, **kwargs) - def assign(self, x:UOp): return UOp(Ops.ASSIGN, self.dtype, (self, x)) - def barrier(self, *src:UOp): return UOp(Ops.BARRIER, src=(self,)+src) - def alu(self, op, *src:UOp, **kwargs): + def load(self, *src:UOp, **kwargs): + if 'dtype' not in kwargs: kwargs['dtype'] = self.dtype.base + return UOp(Ops.LOAD, src=(self,)+src, **kwargs) + def store(self, *src:UOp, **kwargs): return UOp(Ops.STORE, dtypes.void, (self,)+src, **kwargs) + def alu(self, arg, *src:UOp): out_dtype = (self, *src)[-1].dtype - if op in {Ops.CMPLT, Ops.CMPNE, Ops.CMPEQ}: out_dtype = dtypes.bool.vec(out_dtype.count) if out_dtype.count > 1 else dtypes.bool - return UOp(op, out_dtype, (self,)+src, **kwargs) + if arg in {Ops.CMPLT, Ops.CMPNE}: out_dtype = dtypes.bool.vec(out_dtype.count) if out_dtype.count > 1 else dtypes.bool + return UOp(arg, out_dtype, (self,)+src) @staticmethod def const(dtype:DType, b:ConstLike, device:str|tuple[str, ...]|None=None, shape:tuple[sint, ...]|None=None): if isinstance(b, UOp): return b.unbind()[0] if b.op is Ops.BIND else b @@ -291,32 +246,33 @@ class UOp(MathTrait, metaclass=UOpMetaClass): ret = UOp(Ops.VCONST if isinstance(b, tuple) else Ops.CONST, dtype, arg=dtypes.as_const(b, dtype)) if shape is not None: from tinygrad.shape.shapetracker import ShapeTracker - ret = ret.replace(src=(UOp(Ops.VIEW, dtypes.void, (), ShapeTracker.from_shape(shape, (0,)*len(shape))),)) + ret = ret.replace(src=(ShapeTracker.from_shape(()).reshape((1,)*len(shape)).expand(shape).to_uop(),)) if device is not None: - if shape is not None: ret = ret.replace(src=(UOp(Ops.DEVICE, arg=device).view(unwrap(ret.st)),)) - else: ret = ret.replace(src=(UOp(Ops.DEVICE, arg=device),)) + ret = ret.replace(src=(UOp(Ops.DEVICE, arg=device).view(unwrap(ret.st)),)) return ret + def valid(self): return UOp.where(UOp(Ops.VALID, dtypes.bool, (UOp(Ops.VIEW, arg=self.st),)), self.const_like(self.base.arg), 0) @staticmethod - def range(end:sint, *arg): - if len(arg) == 0: raise RuntimeError("range needs an arg") - if len(arg) == 1: arg = arg+(AxisType.LOOP,) - return UOp(Ops.RANGE, dtype=dtypes.int, src=(sint_to_uop(end),), arg=arg) + def range(dtype:DType, end:sint, idx:int): return UOp(Ops.RANGE, dtype=dtype, src=(sint_to_uop(end),), arg=idx) def r(self, op:Ops, axis:tuple[int, ...]): axis = tuple(sorted([x for x in axis if resolve(self.shape[x] != 1)])) if len(axis) == 0: return self # move any non reduce axis before the first reduce axis - move_early, rest = partition(range(axis[0], len(self.shape)), lambda i: i not in axis and resolve(self.shape[i] != 1)) - permaxis = tuple(range(axis[0])) + tuple(move_early) + tuple(rest) - ret = self.permute(permaxis) - new_axis = tuple([x for x in range(axis[0]+len(move_early), len(self.shape)) if resolve(ret.shape[x] != 1)]) - assert len(axis) == len(new_axis) + move_early = [i for i in range(axis[0], len(self.shape)) if i not in axis and resolve(self.shape[i] != 1)] + if move_early: + permute = tuple(range(axis[0])) + tuple(move_early) + tuple([i for i in range(axis[0], len(self.shape)) if i not in move_early]) + ret = self.permute(permute) + new_axis = tuple([x for x in range(axis[0]+len(move_early), len(self.shape)) if resolve(ret.shape[x] != 1)]) + assert len(axis) == len(new_axis) + else: + ret, new_axis = self, axis ret = UOp(Ops.REDUCE_AXIS, self.dtype, (ret,), (op, new_axis)) return ret.reshape(tuple([x if i not in axis else 1 for i,x in enumerate(self.shape)])) + def assign(self, x:UOp): return UOp(Ops.ASSIGN, self.dtype, (self,x)) def reduce(self, *src:UOp, **kwargs): return UOp(Ops.REDUCE, kwargs.pop('dtype', self.dtype), src=(self,)+src, **kwargs) - def contiguous(self, *args, **kwargs): return UOp(Ops.CONTIGUOUS, dtype=self.dtype, src=(self,)+args, **kwargs) + def contiguous(self): return self.alu(Ops.CONTIGUOUS) def contiguous_backward(self): return self.alu(Ops.CONTIGUOUS_BACKWARD) - def bufferize(self, *args, **kwargs): return UOp(Ops.BUFFERIZE, dtype=self.dtype, src=(self,)+args, **kwargs) def fuse(self): return self.alu(Ops.FUSE) + def gbarrier(self): return self.alu(Ops.GBARRIER) def allreduce(self, op, device:str|tuple[str, ...]|UOp): assert isinstance(self.device, tuple), f"allreduce must be on tuple {self.device} isn't" return UOp(Ops.ALLREDUCE, self.dtype, (self, UOp(Ops.DEVICE, arg=device) if not isinstance(device, UOp) else device), op) @@ -334,7 +290,7 @@ class UOp(MathTrait, metaclass=UOpMetaClass): return tuple(itertools.pairwise(itertools.accumulate([self.src[0].shape[self.axis] for _ in self.device], initial=0))) @functools.cached_property - def axis(self) -> int|None: + def axis(self) -> Optional[int]: if self.op is Ops.MULTI: return self.arg # NOTE: they all have to share an axis, we always choose [-1] if self.op in GroupOp.ALU: return axes[-1] if (axes := dedup([x.axis for x in self.src if x.axis is not None])) else None @@ -382,18 +338,16 @@ class UOp(MathTrait, metaclass=UOpMetaClass): return self def view(self, new_st:ShapeTracker) -> UOp: return UOp(Ops.VIEW, self.dtype, (self,), new_st) - def _mop(self, op:Ops, arg) -> UOp: + def _mop(self, op:Ops, arg): ret = UOp(op, self.dtype, (self,), arg) if self.st == ret.st: return self # ignore NOOPs, also check ret.st return ret - def forced_reshape(self, arg:tuple[sint, ...], **kwargs): return UOp(Ops.RESHAPE, kwargs.pop("dtype", self.dtype), src=(self,), arg=arg) - def reshape(self, arg:tuple[sint, ...]): return self._mop(Ops.RESHAPE, arg) - def expand(self, arg:tuple[sint, ...]): return self._mop(Ops.EXPAND, arg) - def shrink(self, arg:tuple[tuple[sint, sint], ...]): return self._mop(Ops.SHRINK, arg) def pad(self, arg:tuple[tuple[sint, sint], ...]): return self._mop(Ops.PAD, arg) - def permute(self, arg:tuple[int, ...]): return self._mop(Ops.PERMUTE, arg) + def expand(self, arg:tuple[sint, ...]): return self._mop(Ops.EXPAND, arg) + def permute(self, arg:tuple[sint, ...]): return self._mop(Ops.PERMUTE, arg) + def shrink(self, arg:tuple[tuple[sint, sint], ...]): return self._mop(Ops.SHRINK, arg) def flip(self, arg:tuple[bool, ...]): return self._mop(Ops.FLIP, arg) # *** uop UNIQUE *** @@ -410,14 +364,14 @@ class UOp(MathTrait, metaclass=UOpMetaClass): @property def device(self) -> str|tuple[str, ...]: return cast(str|tuple[str, ...], unwrap(self._device)) @functools.cached_property - def _device(self) -> str|tuple[str, ...]|None: + def _device(self) -> Optional[str|tuple[str, ...]]: if self.op is Ops.DEVICE: return self.arg if self.op is Ops.MSELECT: assert isinstance(self.src[0].device, tuple), "mselect must be on tuple device" return self.src[0].device[self.arg] if self.op is Ops.MSTACK: return tuple(cast(str, x.device) for x in self.src) if self.op in {Ops.COPY, Ops.BUFFER, Ops.ALLREDUCE}: return self.src[1].device - return next((x._device for x in self.src if x._device is not None), None) + return dsrcs[0]._device if len(dsrcs:=[x for x in self.src if x._device is not None]) != 0 else None @property def buf_uop(self) -> UOp: if self.op is Ops.BUFFER: return self @@ -425,15 +379,6 @@ class UOp(MathTrait, metaclass=UOpMetaClass): if self.op is Ops.MSTACK: return UOp(Ops.MSTACK, self.dtype, src=tuple(x.buf_uop for x in self.src)) assert self.op is Ops.ASSIGN, f"must be ASSIGN {self.op}" return self.src[0].base - - def as_buf(self) -> UOp: - if self.op is Ops.MSELECT: return self.src[0].as_buf().mselect(self.arg) - if self.op is Ops.MSTACK: return UOp(Ops.MSTACK, self.dtype, src=tuple(x.as_buf() for x in self.src)) - # TODO: this should be the only one of these. this is the one RANGEIFY uses - s = self - while len(s.src) and s.op is not Ops.BUFFER: s = s.src[0] - return s - @property def buffer(self) -> Buffer|MultiBuffer: from tinygrad.device import Buffer, MultiBuffer @@ -457,7 +402,7 @@ class UOp(MathTrait, metaclass=UOpMetaClass): buffers[self] = ret return ret @property - def realized(self) -> Buffer|MultiBuffer|None: + def realized(self) -> Optional[Buffer|MultiBuffer]: # NOTE: this is used by the JIT to determine which inputs we capture return self.buffer if self.op in {Ops.BUFFER, Ops.MSTACK} and self.buffer.is_allocated() else None @property @@ -467,18 +412,17 @@ class UOp(MathTrait, metaclass=UOpMetaClass): # *** uop Variable stuff *** @staticmethod - def variable(name:str, min_val:ConstType, max_val:ConstType, dtype:DType=dtypes.int) -> UOp: + def variable(name:str, min_val:ConstType, max_val:ConstType, dtype:DType=dtypes.int): assert not isinstance(min_val, UOp) and not isinstance(max_val, UOp), f"can't create Variable {name} with {min_val}/{max_val}" return UOp(Ops.DEFINE_VAR, dtype, arg=(name, min_val, max_val)) @property def expr(self): assert self.op is Ops.DEFINE_VAR, f"op is {self.op}, need DEFINE_VAR" return self.arg[0] - def bind(self, val:int|UOp): + def bind(self, val:int): assert self.op is Ops.DEFINE_VAR, f"op is {self.op}, need DEFINE_VAR" - uval = self.const_like(val) if isinstance(val, int) else val - assert self.arg[1] <= uval.vmin and uval.vmax <= self.arg[2], f"bind {val} not in range [{self.arg[1]}, {self.arg[2]}]" - return UOp(Ops.BIND, self.dtype, (self, uval)) + assert self.arg[1] <= val and val <= self.arg[2], f"bind {val} not in range [{self.arg[1]}, {self.arg[2]}]" + return UOp(Ops.BIND, self.dtype, (self, self.const_like(val))) def unbind(self) -> tuple[Variable, int]: assert self.op is Ops.BIND and self.src[0].op is Ops.DEFINE_VAR and self.src[1].op is Ops.CONST, f"can't unbind {self}" return self.src[0], self.src[1].arg @@ -490,7 +434,7 @@ class UOp(MathTrait, metaclass=UOpMetaClass): all_vars = set([x for x in self.toposort() if x.op is Ops.DEFINE_VAR]) return bound_vars.union(set([x for x in all_vars if x not in bound_var_base])) def variables(self) -> list[Variable]: - st_vars: list[set[Variable]] = [x.arg.vars() for x in self.toposort() if x.op is Ops.VIEW] + st_vars: list[set[Variable]] = [x.st_arg.vars() for x in self.toposort() if x.op in GroupOp.Buffer] return sorted(set.union(*st_vars, set([x.unbind()[0] if x.op is not Ops.DEFINE_VAR else x for x in self.vars()])), key=lambda v: v.arg) # *** uop symbolic stuff *** @@ -518,7 +462,6 @@ class UOp(MathTrait, metaclass=UOpMetaClass): if (d0:=self.src[0].divides(v)) is not None: return d0 * self.src[1] if (d1:=self.src[1].divides(v)) is not None: return self.src[0] * d1 return None # generic None if we aren't sure - def pop_const(self) -> tuple[UOp, int]: return (self.src[0], self.src[1].arg) if self.op is Ops.ADD and self.src[1].op is Ops.CONST else (self, 0) @property def vmin(self) -> ConstType: return self._min_max[0] @property @@ -539,8 +482,13 @@ class UOp(MathTrait, metaclass=UOpMetaClass): if s1_vmax < 0: return (0, -s1_vmin-1) if s0_vmin >= 0 else (-(-s1_vmin-1), 0) if s0_vmax <= 0 else (-(-s1_vmin-1), -s1_vmin-1) if self.op is Ops.IDIV: assert isinstance(s0_vmin, int) and isinstance(s0_vmax, int) and isinstance(s1_vmin, int) and isinstance(s1_vmax, int) - if s1_vmin*s1_vmax>0: - return min(vals:=(cdiv(s0_vmin, s1_vmin), cdiv(s0_vmin, s1_vmax), cdiv(s0_vmax, s1_vmin), cdiv(s0_vmax, s1_vmax))), max(vals) + if (c:=s1_vmin) == s1_vmax: # s1 is a const + if c > 0: return cdiv(s0_vmin, c), cdiv(s0_vmax, c) + if c < 0: return cdiv(s0_vmax, c), cdiv(s0_vmin, c) + if (s0_vmax <= 0 and s1_vmax < 0): return cdiv(s0_vmax, s1_vmin), cdiv(s0_vmin, s1_vmax) + if (s0_vmin >= 0 and s1_vmin > 0): return cdiv(s0_vmin, s1_vmax), cdiv(s0_vmax, s1_vmin) + if (s0_vmax <= 0 and s1_vmin > 0): return cdiv(s0_vmin, s1_vmin), cdiv(s0_vmax, s1_vmax) + if (s0_vmin >= 0 and s1_vmax < 0): return cdiv(s0_vmax, s1_vmax), cdiv(s0_vmin, s1_vmin) if self.op is Ops.MAX: return max(s0_vmin, s1_vmin), max(s0_vmax, s1_vmax) if self.op is Ops.CMPLT: return (s0_vmax str: - with Context(TRACK_MATCH_STATS=0): - ret = graph_rewrite(self.simplify() if simplify else self, renderer if pm is None else pm) + def render(self, simplify=True, pm:Optional[PatternMatcher]=None) -> str: + ret = graph_rewrite(self.simplify() if simplify else self, renderer if pm is None else pm) return ret.arg if ret.op is Ops.NOOP else str(ret) @dataclass(frozen=True) class KernelInfo: name: str = "test" # name of the kernel - axis_types: tuple[AxisType, ...] = tuple() + local_dims: int = 0 # number of local dimensions (this is remapping RANGE to SPECIAL) + upcasted: int = 0 # count that are upcasted (this is remapping RANGE to UNROLL) dont_use_locals: bool = False # don't use local indexing applied_opts: tuple = tuple() opts_to_apply: tuple|None = None @@ -603,10 +550,10 @@ def safe_pow(x, y): python_alu: dict[Ops, Callable] = { Ops.LOG2: lambda x: math.log2(x) if x > 0 else -math.inf if x == 0 else math.nan, Ops.EXP2: safe_exp2, Ops.SQRT: lambda x: math.sqrt(x) if x >= 0 else math.nan, Ops.RECIP: lambda x: 1/x if x != 0 else math.copysign(math.inf, x), - Ops.SIN: lambda x: math.sin(x) if not math.isinf(x) else math.nan, Ops.POW: safe_pow, Ops.TRUNC: math.trunc, + Ops.SIN: lambda x: math.sin(x) if not math.isinf(x) else math.nan, Ops.POW: safe_pow, Ops.NEG: operator.neg, Ops.ADD: operator.add, Ops.SUB: operator.sub, Ops.MUL: operator.mul, Ops.CMPNE: operator.ne, Ops.CMPLT: operator.lt, Ops.XOR: operator.xor, Ops.OR: operator.or_, Ops.AND: operator.and_, Ops.SHR: operator.rshift, Ops.SHL: operator.lshift, Ops.MAX: max, - Ops.MOD: cmod, Ops.IDIV: cdiv, Ops.MULACC: lambda x,y,z: (x*y)+z, Ops.WHERE: lambda x,y,z: y if x else z, Ops.CMPEQ: operator.eq} + Ops.MOD: cmod, Ops.IDIV: cdiv, Ops.MULACC: lambda x,y,z: (x*y)+z, Ops.WHERE: lambda x,y,z: y if x else z} def exec_alu(op:Ops, dtype:DType, operands, truncate_output=True): if dtype.count > 1: @@ -635,18 +582,14 @@ def get_location() -> tuple[str, int]: def lines(fn) -> list[str]: with open(fn) as f: return f.readlines() -def printable(loc:tuple[str, int]) -> str: - try: return lines(loc[0])[loc[1]-1].strip() - except FileNotFoundError: return "" - class UPat(MathTrait): __slots__ = ("op", "dtype", "arg", "name", "src") - def __init__(self, op:Ops|tuple[Ops, ...]|set[Ops]|None=None, dtype:DType|tuple[DType, ...]|None=None, - src:tuple[UPat, ...]|list[UPat]|UPat|None=None, arg:Any=None, - name:str|None=None, allow_any_len:bool=False, custom_early_reject:set[Ops]|None=None, location=None): + def __init__(self, op:Optional[Union[Ops, tuple[Ops, ...], set[Ops]]]=None, dtype:Optional[Union[DType, tuple[DType, ...]]]=None, + src:Optional[Union[tuple[UPat, ...], list[UPat], UPat]]=None, arg:Any=None, + name:Optional[str]=None, allow_any_len:bool=False, custom_early_reject:Optional[set[Ops]]=None, location=None): assert op is None or isinstance(op, (Ops, tuple, set)), "op must be Ops or tuple of Ops" - self.op: tuple[Ops, ...]|None = (op,) if isinstance(op, Ops) else (tuple(op) if isinstance(op, set) else op) - self.dtype: tuple[DType, ...]|None = (dtype,) if isinstance(dtype, DType) else dtype + self.op: Optional[tuple[Ops, ...]] = (op,) if isinstance(op, Ops) else (tuple(op) if isinstance(op, set) else op) + self.dtype: Optional[tuple[DType, ...]] = (dtype,) if isinstance(dtype, DType) else dtype self.arg, self.name, self._in_src, self.custom_early_reject = arg, name, src, custom_early_reject self.src: Any = None assert self.name != "ctx", "UPat can't be named ctx" @@ -678,37 +621,35 @@ class UPat(MathTrait): @staticmethod @functools.cache - def var(name:str|None=None, dtype:DType|tuple[DType, ...]|None=None): return UPat(dtype=dtype, name=name) + def var(name:Optional[str]=None, dtype:Optional[Union[DType, tuple[DType, ...]]]=None): return UPat(dtype=dtype, name=name) @staticmethod @functools.cache - def cvar(name:str|None=None, dtype:DType|tuple[DType, ...]|None=None, vec=True): - return UPat((Ops.CONST,Ops.VCONST) if vec else Ops.CONST, dtype, name=name) + def cvar(name:Optional[str]=None, dtype:Optional[DType]=None, vec=True): return UPat((Ops.CONST,Ops.VCONST) if vec else Ops.CONST, dtype, name=name) @staticmethod - def const(dtype:DType|tuple[DType, ...]|None, b:ConstType): return UPat(Ops.CONST, dtype=dtype, arg=b) - - # lil helper - def f(self, op, **kwargs): return UPat(op, src=(self,), **kwargs) + def const(dtype:Optional[Union[DType, tuple[DType, ...]]], b:ConstType): return UPat(Ops.CONST, dtype=dtype, arg=b) # copied from UOp - def sink(self, *srcs:UPat|None, **kwargs): return UPat(Ops.SINK, dtypes.void, (self,)+tuple([x for x in srcs if x is not None]), **kwargs) - def index(self, idx:UPat, valid:UPat|None=None): return UPat(Ops.INDEX, self.dtype, (self,idx,valid) if valid is not None else (self,idx)) + def index(self, idx:UPat, valid:Optional[UPat]=None): return UPat(Ops.INDEX, self.dtype, (self,idx,valid) if valid is not None else (self,idx)) def view(self, st=None, **kwargs): return UPat(Ops.VIEW, self.dtype, (self,), st, **kwargs) def cast(self, dtype=None, **kwargs): return UPat(Ops.CAST, dtype, (self,), **kwargs) def bitcast(self, dtype=None): return UPat(Ops.BITCAST, dtype, (self,)) def gep(self, i:int|None=None, **kwargs): return UPat(Ops.GEP, None, (self,), (i,) if i is not None else None, **kwargs) def load(self, *src:UPat, **kwargs): return UPat(Ops.LOAD, src=(self,)+src, **kwargs) - def store(self, *src:UPat, **kwargs): return UPat(Ops.STORE, self.dtype, (self,)+src, **kwargs) + def store(self, *src:UPat, **kwargs): return UPat(Ops.STORE, dtypes.void, (self,)+src, **kwargs) def assign(self, x:UPat, **kwargs): return UPat(Ops.ASSIGN, self.dtype, (self,x), **kwargs) def reduce(self, *src:UPat, **kwargs): return UPat(Ops.REDUCE, self.dtype, src=(self,)+src, **kwargs) def fuse(self): return self.alu(Ops.FUSE) def or_broadcasted(self, **kwargs): return UPat.any(self, UPat(Ops.VECTORIZE, self.dtype, src=self, **kwargs)) - def contiguous(self, *args, **kwargs): return UPat(Ops.CONTIGUOUS, dtype=self.dtype, src=(self,)+args, **kwargs) def const_like(self, b:ConstLike): return UPat.const(self.dtype, cast(ConstType, b)) def alu(self, op:Ops, *src:UPat): asrc = (self,)+src return UPat(op, dtypes.bool if op in {Ops.CMPLT, Ops.CMPNE} else asrc[-1].dtype, list(asrc) if op in GroupOp.Commutative else asrc) + def printable(self:UPat) -> str: + try: return lines(self.location[0])[self.location[1]-1].strip() + except FileNotFoundError: return "" + def __repr__(self): def rep(x): form = "UPat(%s, %s, name=%s, dtype=%s, allow_any_len=%s, src=%s)" @@ -779,7 +720,7 @@ class PatternMatcher: def __reduce__(self): return PatternMatcher, ([(x,deconstruct_function(fxn) if fxn.__name__ == "" else fxn) for x,fxn in self.patterns],) @functools.cache # pylint: disable=method-cache-max-size-none - def __add__(self, more:PatternMatcher) -> PatternMatcher: return PatternMatcher(self.patterns+more.patterns) + def __add__(self, more:PatternMatcher): return PatternMatcher(self.patterns+more.patterns) def rewrite(self, uop:UOp, ctx=None) -> UOp|None: ler = {u.op for u in uop.src} @@ -788,6 +729,12 @@ class PatternMatcher: if (ret:=match(uop, ctx)) is not None and ret is not uop: return ret return None + def fixed_point_rewrite(self, uop:UOp, ctx=None) -> UOp: + # apply rewrite rules until a fixed point is reached. may return `uop` itself if PatternMatcher doesn't match + new_n: UOp|None = uop + while new_n is not None: last_n, new_n = new_n, self.rewrite(new_n, ctx) + return last_n + # *** non-blocking UOp tracker *** ucount = itertools.count() @@ -798,25 +745,23 @@ def track_uop(u:UOp): uop_number[u] = num = next(ucount) # KERNEL also has a UOp in the arg arg = type(u.arg)(track_uop(u.arg.ast), u.arg.metadata) if u.op is Ops.KERNEL else u.arg - uop_fields[num] = (u.op, u.dtype, tuple(track_uop(s) for s in u.src), arg, u.tag)+((u.metadata,) if TRACEMETA>=2 else ()) + uop_fields[num] = (u.op, u.dtype, tuple(track_uop(s) for s in u.src), arg, u.tag) return num # *** tracking pattern matcher *** VIZ = ContextVar("VIZ", 0) TRACK_MATCH_STATS = ContextVar("TRACK_MATCH_STATS", 2 if VIZ else 0) -match_stats:dict[UPat, list[int|float]] = dict() - +match_stats:dict[UPat, list[Union[int, float]]] = dict() @dataclass(frozen=True) class TrackedGraphRewrite: - loc:tuple[str, int] # location that called graph_rewrite - sink:int # the sink input to graph_rewrite - matches:list[tuple[int, int, tuple]] # before/after UOp, UPat location - name:str|None # optional name of the rewrite - depth:int # depth if it's a subrewrite - bottom_up:bool - -tracked_keys:list[TracingKey] = [] + loc: tuple[str, int] # location that called graph_rewrite + sink: int # the sink input to graph_rewrite + matches: list[tuple[int, int, UPat]] # before+after of all the matches + name: str|None # optional name of the rewrite + depth: int # depth if it's a subrewrite + bottom_up: bool +tracked_keys:list[Any] = [] tracked_ctxs:list[list[TrackedGraphRewrite]] = [] _name_cnt:dict[str, itertools.count] = {} @@ -827,28 +772,24 @@ if getenv("CAPTURE_PROCESS_REPLAY"): def save_to_diskcache(): for k,v in replay_capture.items(): diskcache_put("process_replay", k, v, prepickled=True) -def track_rewrites(name:Callable[..., str|TracingKey]|bool=True, replay:bool=False): +def track_rewrites(name:Callable|bool|None=None): def _decorator(func): def __wrapper(*args, **kwargs): - fn = key = func.__name__ if TRACK_MATCH_STATS >= 2: - tracked_keys.append(key:=TracingKey(n:=f"{fn} n{next(_name_cnt.setdefault(fn, itertools.count(1)))}", (n,))) + tracked_keys.append(args[0] if args and name is None else (fn:=func.__name__)+f" n{next(_name_cnt.setdefault(fn, itertools.count(1)))}") tracked_ctxs.append([]) - with cpu_profile(key, "TINY") as e: - ret = func(*args, **kwargs) + ret = func(*args, **kwargs) if TRACK_MATCH_STATS >= 2 and callable(name): name_ret = name(*args, **kwargs, ret=ret) - assert isinstance(name_ret, (TracingKey, str)), f"name function returned {type(name_ret)}" - tracked_keys[-1] = k = TracingKey(n:=tracked_keys[-1].display_name.replace(fn, name_ret), (n,)) if isinstance(name_ret, str) else name_ret - e.name = TracingKey(k.display_name if isinstance(name_ret, str) else f"{fn} for {k.display_name}", k.keys) - if getenv("CAPTURE_PROCESS_REPLAY") and replay: + tracked_keys[-1] = tracked_keys[-1].replace(fn, name_ret) if isinstance(name_ret, str) else name_ret + if getenv("CAPTURE_PROCESS_REPLAY"): # find the unittest frame we're capturing in frm = sys._getframe(1) while (f_back:=frm.f_back) is not None and "unittest" not in f_back.f_code.co_filename: frm = f_back loc = f"{frm.f_code.co_filename.split('/')[-1]}:{frm.f_lineno} {frm.f_code.co_name}" # capture global context vars and all the args passed in with Context(PICKLE_BUFFERS=0): - inputs = (fn, args, kwargs, ContextVar._cache) + inputs = (func.__name__, args, kwargs, ContextVar._cache) replay_capture[hashlib.sha256(pickle.dumps(inputs)).hexdigest()] = pickle.dumps(inputs+(loc, ret)) return ret return __wrapper @@ -862,8 +803,7 @@ def track_matches(func): depth = len(active_rewrites) tracked_ctxs[-1].append(ctx:=TrackedGraphRewrite(loc, track_uop(args[0]), [], kwargs.get("name", None), depth, kwargs.get("bottom_up", False))) active_rewrites.append(ctx) - with cpu_profile(kwargs.get("name", ""), "TINY", display=tracking): - ret = func(*args, **kwargs) + ret = func(*args, **kwargs) if tracking: active_rewrites.pop() return ret return _track_func @@ -879,17 +819,11 @@ class TrackedPatternMatcher(PatternMatcher): match_stats[p][2] += time.perf_counter()-st continue match_stats[p][1] += 1 - try: ret = match(uop, ctx) - except Exception as e: - if TRACK_MATCH_STATS >= 2 and active_rewrites and not isinstance(e, RewriteNotReady): - active_rewrites[-1].matches.append((track_uop(uop), track_uop(UOp(Ops.REWRITE_ERROR, src=uop.src, arg=str(sys.exc_info()[1]))), p.location)) - raise - if ret is not None and ret is not uop: + if (ret:=match(uop, ctx)) is not None: match_stats[p][0] += 1 match_stats[p][3] += (et:=time.perf_counter()-st) - if TRACK_MATCH_STATS >= 3: print(f"{et*1e6:7.2f} us -- ", printable(p.location)) - if TRACK_MATCH_STATS >= 2 and isinstance(ret, UOp) and active_rewrites: - active_rewrites[-1].matches.append((track_uop(uop), track_uop(ret), p.location)) + if TRACK_MATCH_STATS >= 3: print(f"{et*1e6:7.2f} us -- ", p.printable()) + if TRACK_MATCH_STATS >= 2 and isinstance(ret, UOp) and active_rewrites: active_rewrites[-1].matches.append((track_uop(uop),track_uop(ret), p)) return ret match_stats[p][2] += time.perf_counter()-st return None @@ -902,21 +836,20 @@ if TRACK_MATCH_STATS or PROFILE: if TRACK_MATCH_STATS >= 2: with open(fn:=temp("rewrites.pkl", append_user=True), "wb") as f: print(f"rewrote {len(tracked_ctxs)} graphs and matched {sum(len(r.matches) for x in tracked_ctxs for r in x)} times, saved to {fn}") - pickle.dump([(tracked_keys, tracked_ctxs, uop_fields)], f) - if VIZ: launch_viz(VIZ, temp("rewrites.pkl", append_user=True)) - if getenv("PRINT_MATCH_STATS", TRACK_MATCH_STATS.value): + with Context(PICKLE_BUFFERS=0): pickle.dump((tracked_keys, tracked_ctxs, uop_fields), f) + if VIZ: launch_viz("VIZ", temp("rewrites.pkl", append_user=True)) + if getenv("PRINT_MATCH_STATS", 1): ret = [0,0,0.0,0.0] for k,v in sorted(list(match_stats.items()), key=lambda x: x[1][2]+x[1][3]): loc_str = f"{k.location[0].split('/')[-1]}:{k.location[1]}" - if v[1] != 0: print(f"{v[0]:6d} / {v[1]:7d} -- {v[3]*1000.:9.2f} / {(v[2]+v[3])*1000.:9.2f} ms -- {loc_str:20s}", printable(k.location)) + if v[1] != 0: print(f"{v[0]:6d} / {v[1]:7d} -- {v[3]*1000.:9.2f} / {(v[2]+v[3])*1000.:9.2f} ms -- {loc_str:20s}", k.printable()) ret = [x+y for x,y in zip(ret, v)] print(f"{ret[0]:6d} / {ret[1]:7d} -- {ret[3]*1000.:9.2f} / {(ret[2]+ret[3])*1000.:9.2f} ms -- TOTAL") print(f"{len(match_stats)} rules, {sum(v[0] > 0 for v in match_stats.values())} matched once") - def launch_viz(var:ContextVar, data:str): - os.environ[(env_str:=var.key)] = "0" + def launch_viz(env_str:str, data:str): + os.environ[env_str] = "0" os.environ[f"{env_str}_DATA"] = data - os.environ[f"{env_str}_VALUE"] = str(var.value) if not int(os.getenv("VIZ", "0")) and not int(os.getenv("PROFILE", "0")): args = ['--kernels', getenv("VIZ_DATA", "")] if getenv("VIZ_DATA", "") else [] args += ['--profile', getenv("PROFILE_DATA", "")] if getenv("PROFILE_DATA", "") else [] @@ -924,80 +857,50 @@ if TRACK_MATCH_STATS or PROFILE: # *** simple graph rewrite engine *** -class RewriteNotReady(Exception): pass class RewriteContext: - def __init__(self, pm, bpm, ctx=None): - self.pm: PatternMatcher|None = pm - self.pm_cache: dict[UOp, UOp|None] = {} - self.bpm: PatternMatcher|None = bpm - self.bpm_cache: dict[UOp, UOp|None] = {} + def __init__(self, pm, ctx=None): + self.pm: PatternMatcher = pm self.ctx = ctx self.replace: dict[UOp, UOp] = {} - def cached_pm_rewrite(self, x:UOp): - if (ret:=self.pm_cache.get(x,False)) is not False: return ret - ret = self.pm_cache[x] = cast(PatternMatcher, self.pm).rewrite(x, self.ctx) - return ret - - def cached_bpm_rewrite(self, x:UOp): - if (ret:=self.bpm_cache.get(x,False)) is not False: return ret - ret = self.bpm_cache[x] = cast(PatternMatcher, self.bpm).rewrite(x, self.ctx) - return ret - - def unified_rewrite(self, root:UOp) -> UOp: + def unified_rewrite(self, root:UOp, bottom_up=False) -> UOp: stack: list[tuple[UOp, int, UOp]] = [(root, 0, root)] while stack: - if len(stack) >= 200000: raise RuntimeError("infinite loop in graph_rewrite (stack too big)") n, stage, new_n = stack.pop() if n in self.replace: continue # skip any nodes we have seen - try: - if stage == 0: - # if bottom up, we rewrite this node early. in both cases, we add its parents to the stack - if self.bpm is not None: - # apply rewrite rules until a fixed point is reached. may return `uop` itself if PatternMatcher doesn't match - test_n: UOp|None = n - seen = set() - while test_n is not None: - if test_n in seen: raise RuntimeError("infinite loop in fixed_point_rewrite") - seen.add(test_n) - new_n, test_n = test_n, self.cached_bpm_rewrite(test_n) - stack.append((n, 1, new_n)) - for x in reversed(new_n.src): stack.append((x, 0, x)) - elif stage == 1: - try: new_src = tuple([self.replace[x] for x in new_n.src]) - except KeyError: raise RewriteNotReady # pylint: disable=raise-missing-from - if new_src == new_n.src: - # if top down, do the rewrite. if no rewrite or bottom up, we are done rewriting this node so we add it to the dict - if self.pm is None or (new_src_n:=self.cached_pm_rewrite(new_n)) is None: - self.replace[n] = new_n - continue - else: - # if srcs changed from rewrites, construct a new UOp with the new srcs - new_src_n = UOp(new_n.op, new_n.dtype, new_src, new_n.arg, new_n.tag) - # trigger a rewrite of new_src_n, then after that rewrite is done, link it back to n - stack.append((n, 2, new_src_n)) - stack.append((new_src_n, 0, new_src_n)) + if stage == 0: + # if bottom up, we rewrite this node early. in both cases, we add its parents to the stack + if bottom_up: new_n = self.pm.fixed_point_rewrite(new_n, self.ctx) + stack.append((n, 1, new_n)) + for x in reversed(new_n.src): stack.append((x, 0, x)) + elif stage == 1: + if (new_src:=tuple([self.replace[x] for x in new_n.src])) == new_n.src: + # if top down, do the rewrite. if no rewrite or bottom up, we are done rewriting this node so we add it to the dict + if bottom_up or (new_src_n:=self.pm.rewrite(new_n, self.ctx)) is None: + self.replace[n] = new_n + continue else: - # in stage 2, we link the result of new_n to the result of n - try: self.replace[n] = self.replace[new_n] - except KeyError: raise RewriteNotReady # pylint: disable=raise-missing-from - except RewriteNotReady: - # retry this later - stack.insert(0, (n, stage, new_n)) + # if srcs changed from rewrites, construct a new UOp with the new srcs + new_src_n = UOp(new_n.op, new_n.dtype, new_src, new_n.arg, new_n.tag) + # trigger a rewrite of new_src_n, then after that rewrite is done, link it back to n + stack.append((n, 2, new_src_n)) + stack.append((new_src_n, 0, new_src_n)) + else: + # in stage 2, we link the result of new_n to the result of n + self.replace[n] = self.replace[new_n] return self.replace[root] @track_matches -def graph_rewrite(sink:UOp, pm:PatternMatcher, ctx=None, bottom_up=False, name=None, bpm=None) -> UOp: - rewrite_ctx = RewriteContext(pm if not bottom_up else None, pm if bottom_up else bpm, ctx) - return rewrite_ctx.unified_rewrite(sink) +def graph_rewrite(sink:UOp, pm:PatternMatcher, ctx=None, bottom_up=False, name=None) -> UOp: + rewrite_ctx = RewriteContext(pm, ctx) + return rewrite_ctx.unified_rewrite(sink, bottom_up) @track_matches -def graph_rewrite_map(sink:UOp, pm:PatternMatcher, ctx=None, bottom_up=False, name=None, bpm=None, - input_map:dict[UOp, UOp]|None=None, ) -> dict[UOp, UOp]: - rewrite_ctx = RewriteContext(pm if not bottom_up else None, pm if bottom_up else bpm, ctx) +def graph_rewrite_map(sink:UOp, pm:PatternMatcher, ctx=None, bottom_up=False, name=None, input_map:dict[UOp, UOp]|None=None) -> dict[UOp, UOp]: + rewrite_ctx = RewriteContext(pm, ctx) new_map: dict[UOp, UOp] = {} - for k in (list(sink.toposort())[::-1] if bottom_up else sink.toposort()): - new_map[k] = v = rewrite_ctx.unified_rewrite(k) + for k in sink.toposort(): + new_map[k] = v = rewrite_ctx.unified_rewrite(k, bottom_up) if k is not v and k.metadata is not None: all_metadata[v] = tuple(dedup(all_metadata.get(v, ())))+k.metadata if input_map is not None: for k,v in input_map.items(): new_map[k] = new_map.get(v,v) @@ -1012,7 +915,7 @@ syms = { Ops.ADD: "+", Ops.SUB: "-", Ops.IDIV: "//", Ops.MOD: "%", Ops.SHL: "<<" Ops.MUL: "*", Ops.CMPLT: "<", Ops.CMPNE: "!=", Ops.AND: "&", Ops.OR: "|", Ops.XOR: "^"} renderer = PatternMatcher([ (UPat((Ops.DEFINE_VAR, Ops.SPECIAL), name="x"), lambda x: UOp(Ops.NOOP, arg=x.arg[0])), - (UPat(Ops.RANGE, name="x"), lambda x: UOp(Ops.NOOP, arg=f"ridx{x.arg[0]}" if x.arg[0] >= 0 else f"ridxm{-x.arg[0]}")), + (UPat(Ops.RANGE, name="x"), lambda x: UOp(Ops.NOOP, arg=f"ridx{x.arg}")), (UPat((Ops.CONST, Ops.VCONST), name="x"), lambda x: UOp(Ops.NOOP, arg=str(x.arg))), (UPat(Ops.UNROLL, name="x"), lambda x: UOp(Ops.NOOP, arg=f"UNROLL({x.src[0].arg}, {x.arg})")), (UPat(Ops.CAST, name="x"), lambda x: UOp(Ops.NOOP, arg=f"({str(x.dtype)[7:]})({x.src[0].arg})")), @@ -1020,7 +923,6 @@ renderer = PatternMatcher([ (UPat(Ops.BIND, src=UPat(Ops.NOOP), name="x"), lambda x: x.src[0]), #(UPat(Ops.BIND, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"{x.src[0].arg}[={x.src[1].arg}]")), (UPat(Ops.NEG, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"(-{x.src[0].arg})")), - (UPat(Ops.RECIP, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"(1/{x.src[0].arg})")), (UPat(Ops.MAX, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"max({x.src[0].arg}, {x.src[1].arg})")), (UPat(Ops.MULACC, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"({x.src[0].arg}*{x.src[1].arg}+{x.src[2].arg})")), (UPat(Ops.WHERE, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=f"({x.src[1].arg} if {x.src[0].arg} else {x.src[2].arg})")), @@ -1034,7 +936,7 @@ renderer_infer = PatternMatcher([ # *** what was symbolic.py *** -sint = int|UOp +sint = Union[int, UOp] Variable = UOp -ConstLike = ConstType|Variable|tuple[ConstType, ...] +ConstLike = Union[ConstType, Variable, tuple[ConstType, ...]] diff --git a/tinygrad_repo/tinygrad/uop/spec.py b/tinygrad_repo/tinygrad/uop/spec.py index 0d9e21061..7252a76c3 100644 --- a/tinygrad_repo/tinygrad/uop/spec.py +++ b/tinygrad_repo/tinygrad/uop/spec.py @@ -1,8 +1,7 @@ from typing import cast, Callable -from tinygrad.uop.ops import PatternMatcher, UPat, GroupOp, Ops, UOp, print_uops, python_alu, graph_rewrite -from tinygrad.dtype import DType, ImageDType, dtypes, PtrDType, AddrSpace +from tinygrad.uop.ops import PatternMatcher, UPat, GroupOp, Ops, UOp, print_uops, python_alu, graph_rewrite, resolve +from tinygrad.dtype import DType, ImageDType, dtypes, PtrDType from tinygrad.helpers import all_same, prod, DEBUG, ContextVar, Context -from tinygrad.shape.shapetracker import ShapeTracker try: import z3 @@ -10,46 +9,27 @@ try: def z3_cdiv(a, b):return z3.If((a<0), z3.If(0= 0, z3.ToInt(a), -z3.ToInt(-a)))} + Ops.MAX: lambda a,b: z3.If(a z3.ArithRef: s = z3.Int(name, ctx=solver.ctx) solver.add(vmin <= s, s <= vmax) return s # ctx is (solver, load_number_dict) - # each uop gets rewritten to NOOP(arg=(solver, z3_object)), the arg has the solver first due to UOpMetaClass caching. z3 objects from different - # contexts can have the same hash but error on comparison z3_renderer = PatternMatcher([ # Ops.SPECIAL can have symbolic arg but it wont be in the toposort beacuse its not a src, we need to add it manually (UPat(Ops.SPECIAL, src=(), name="x"), lambda x: UOp(Ops.SPECIAL, arg=x.arg[0], src=(x.ufix(x.arg[1]),))), - (UPat(Ops.SPECIAL, src=UPat(Ops.NOOP), name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=(ctx[0],create_bounded(x.arg, 0, x.src[0].arg[1]-1, ctx[0])))), - (UPat(Ops.DEFINE_VAR, name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=(ctx[0],create_bounded(x.arg[0], x.arg[1], x.arg[2], ctx[0])))), - (UPat(Ops.RANGE, name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=(ctx[0],create_bounded(f"ridx{x.arg}", 0, x.src[0].arg[1]-1, ctx[0])))), - # float loads only become a variable when they get cast to int/bool - (UPat(Ops.LOAD, dtypes.ints, name="x"), - lambda x,ctx: UOp(Ops.NOOP, arg=(ctx[0],create_bounded(f"load{ctx[1].setdefault(x, len(ctx[1]))}", x.dtype.min, x.dtype.max, ctx[0])))), - (UPat(Ops.CONST, dtype=dtypes.ints+(dtypes.bool,), name="x"), - lambda x,ctx: UOp(Ops.NOOP, arg=(ctx[0],(z3.BoolVal if dtypes.is_bool(x.dtype) else z3.IntVal)(x.arg, ctx=ctx[0].ctx)))), - # z3 can cast from bool to int automatically - (UPat(Ops.CAST, dtype=dtypes.ints, src=UPat(Ops.NOOP), name="x"), lambda x: x.src[0]), - (UPat(Ops.CAST, dtype=dtypes.bool, src=UPat(Ops.NOOP), name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=(ctx[0], x.src[0].arg[1]!=0))), - # if the source of the cast is not a noop it means that it is a float and so we create a new variable - (UPat(Ops.CAST, dtype=dtypes.ints, name="x"), lambda x,ctx: - UOp(Ops.NOOP, arg=(ctx[0], create_bounded(f"cast{ctx[1].setdefault(x, len(ctx[1]))}", x.dtype.min, x.dtype.max, ctx[0])))), - (UPat(Ops.CAST, dtype=dtypes.bool, name="x"), lambda x,ctx: - UOp(Ops.NOOP, arg=(ctx[0], z3.Bool(f"cast{ctx[1].setdefault(x, len(ctx[1]))}",ctx=ctx[0].ctx)))), + (UPat(Ops.SPECIAL, src=UPat(Ops.NOOP), name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=create_bounded(x.arg, 0, x.src[0].arg-1, ctx[0]))), + (UPat(Ops.DEFINE_VAR, name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=create_bounded(x.arg[0], x.arg[1], x.arg[2], ctx[0]))), + (UPat(Ops.RANGE, name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=create_bounded(f"ridx{x.arg}", 0, x.src[0].arg-1, ctx[0]))), + (UPat(Ops.LOAD, name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=create_bounded(f"load{ctx[1].setdefault(x, len(ctx[1]))}", x.vmin, x.vmax, ctx[0]))), + (UPat(Ops.CONST, name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=(z3.BoolVal if dtypes.is_bool(x.dtype) else z3.IntVal)(x.arg, ctx=ctx[0].ctx))), + (UPat(Ops.CAST, name="x"), lambda x: x.src[0]), (UPat(Ops.XOR, src=UPat(Ops.NOOP), name="x"), - lambda x,ctx: UOp(Ops.NOOP, arg=(ctx[0], z3.BV2Int(z3_alu[x.op](*(z3.Int2BV(s.arg[1], x.dtype.itemsize*8) for s in x.src)))))), - (UPat(GroupOp.ALU, src=UPat(Ops.NOOP), name="x"), lambda x,ctx: UOp(Ops.NOOP, arg=(ctx[0], z3_alu[x.op](*(s.arg[1] for s in x.src))))), - # A comparison between floats introduces a new bool variable - (UPat(GroupOp.Comparison, src=UPat(dtype=dtypes.floats), name="x"), lambda x,ctx: - UOp(Ops.NOOP, arg=(ctx[0], z3.Bool(f"float_cmp{ctx[1].setdefault(x, len(ctx[1]))}",ctx=ctx[0].ctx)))), + lambda x: UOp(Ops.NOOP, arg=z3.BV2Int(z3_alu[x.op](*(z3.Int2BV(s.arg, x.dtype.itemsize*8) for s in x.src))))), + (UPat(GroupOp.ALU, src=UPat(Ops.NOOP), name="x"), lambda x: UOp(Ops.NOOP, arg=z3_alu[x.op](*(s.arg for s in x.src)))), ]) - def uops_to_z3(solver, *uops: UOp) -> 'list[z3.ExprRef]': - with Context(TRACK_MATCH_STATS=0): # cant pickle z3 objects - return [s.arg[1] for s in graph_rewrite(uops[0].sink(*uops[1:]), z3_renderer, ctx=(solver, {})).src] - z3_imported = True except (ImportError, AttributeError): z3_imported = False @@ -71,7 +51,7 @@ buffer_spec = PatternMatcher([ assign_spec = PatternMatcher([ # KERNEL can attach to an ASSIGN to describe the compute required to realize a BUFFER - (UPat(Ops.KERNEL, src=UPat((Ops.BUFFER, Ops.BUFFER_VIEW, Ops.ASSIGN, Ops.MSELECT, Ops.MSTACK, Ops.BIND))), lambda: True), + (UPat(Ops.KERNEL, src=UPat((Ops.BUFFER, Ops.BUFFER_VIEW, Ops.ASSIGN, Ops.MSELECT, Ops.MSTACK))), lambda: True), # ASSIGN has a target and a value. It can also optionally depend on other assigns (UPat(Ops.ASSIGN, name="x"), lambda x: len(x.src) >= 2 and all(s.op is Ops.ASSIGN for s in x.src[2:])), @@ -107,10 +87,6 @@ tensor_uop_spec = buffer_spec+assign_spec+PatternMatcher([ (UPat((Ops.DETACH, Ops.CONTIGUOUS, Ops.CONTIGUOUS_BACKWARD, Ops.FUSE), name="root", src=(UPat.var("x"),), arg=None), lambda root,x: root.dtype == x.dtype), - # CONTIGUOUS with a range - (UPat(Ops.CONTIGUOUS, name="root", src=(UPat.var("x"),), allow_any_len=True, arg=None), - lambda root,x: root.dtype == x.dtype and all(u.op is Ops.RANGE for u in root.src[1:])), - # COPY/ALLREDUCE/MULTI (UPat(Ops.COPY, name="copy", src=(UPat.var("x"), UPat(Ops.DEVICE)), arg=None), lambda copy,x: copy.dtype == x.dtype), (UPat(Ops.ALLREDUCE, name="red", src=(UPat.var("x"), UPat(Ops.DEVICE))), lambda red,x: red.dtype == x.dtype and isinstance(red.arg, Ops)), @@ -130,8 +106,9 @@ def validate_index(idx:UOp, gate:UOp=UOp.const(dtypes.bool, True)): if not z3_imported: raise ImportError("z3 is required for bounds checking, try IGNORE_OOB=0 or \"pip install z3-solver\"") solver = z3.Solver(ctx=z3.Context()) - z3_idx, z3_mask = uops_to_z3(solver, idx.src[1], mask) - solver.add(z3_mask) + z3_sink = graph_rewrite(idx.src[1].sink(mask), z3_renderer, ctx=(solver, {})) + z3_idx = z3_sink.src[0].arg + solver.add(z3_sink.src[1].arg) if solver.check((z3_idx<0)|(sz<=z3_idx)) == z3.sat: print(f"idx={idx.src[1].render(simplify=False)}") print(f"mask & gate={mask.render(simplify=False)}") @@ -151,54 +128,56 @@ index_pat = UPat(Ops.INDEX, name="idx").or_casted() # this is the matcher for the final rendered UOps # matcher functions returns True or False (or None to not match) spec = PatternMatcher([ - (UPat(Ops.DEFINE_GLOBAL, name="x"), lambda x: isinstance(x.dtype, (PtrDType, ImageDType)) and x.dtype.addrspace == AddrSpace.GLOBAL), - (UPat(Ops.DEFINE_LOCAL, name="x"), lambda x: isinstance(x.dtype, PtrDType) and x.dtype.addrspace == AddrSpace.LOCAL), - (UPat(Ops.DEFINE_REG, src=()), lambda: True), + (UPat(Ops.DEFINE_GLOBAL, name="x"), lambda x: isinstance(x.dtype, (PtrDType, ImageDType)) and not x.dtype.local), + (UPat(Ops.DEFINE_LOCAL, name="x"), lambda x: isinstance(x.dtype, PtrDType) and x.dtype.local), + (UPat(Ops.DEFINE_ACC, src=(UPat.var("c"),), name="x", allow_any_len=True), + lambda x,c: all(y.op is Ops.RANGE for y in x.src[1:]) and c.dtype == x.dtype), (UPat(Ops.DEFINE_VAR, name="x"), lambda x: isinstance(x.arg[1], int) and isinstance(x.arg[2], int)), - (UPat(Ops.RANGE, src=(UPat.var("x"),), name="rng"), lambda rng,x: rng.dtype == x.dtype and isinstance(rng.arg, tuple)), + (UPat(Ops.RANGE, src=(UPat.var("x"),), name="rng"), lambda rng,x: rng.dtype == x.dtype and isinstance(rng.arg, int)), (UPat(Ops.SPECIAL, src=()), lambda: True), - (UPat(Ops.VIEW, dtypes.void, src=(), name="x"), lambda x: isinstance(x.arg, ShapeTracker)), - (UPat(Ops.VIEW, src=(UPat.var("src"),), name="x"), - lambda x,src: isinstance(x.arg, ShapeTracker) and src.op is not Ops.STORE and x.dtype.base == src.dtype.base), + # TODO: confirm the args of both of these are shapetrackers + (UPat(Ops.VIEW, dtypes.void, src=()), lambda: True), + (UPat(Ops.VIEW, src=(UPat.var("src"),), name="x"), lambda x,src: src.op is not Ops.STORE and x.dtype.base == src.dtype.base), (UPat(Ops.VALID, dtypes.bool, (UPat(Ops.VIEW),)), lambda: True), (UPat(Ops.CONST, name="x"), lambda x: type(x.arg) is type(dtypes.as_const(x.arg, x.dtype))), # early LOAD has a - (UPat(Ops.LOAD, src=(UPat(Ops.VIEW, src=(UPat(GroupOp.Defines),)),)), lambda: True), - (UPat(Ops.LOAD, src=(UPat(Ops.VIEW, src=(UPat(GroupOp.Defines),)), UPat(Ops.STORE))), lambda: True), + (UPat(Ops.LOAD, src=(UPat(Ops.VIEW, src=(UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL)),)),)), lambda: True), + (UPat(Ops.LOAD, src=(UPat(Ops.VIEW, src=(UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL)),)), UPat(Ops.STORE))), lambda: True), # early STORE has a - (UPat(Ops.STORE, src=(UPat(Ops.VIEW, src=(UPat(GroupOp.Defines),)), UPat())), lambda: True), + (UPat(Ops.STORE, src=(UPat(Ops.VIEW, src=(UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL)),)), UPat())), lambda: True), # **** new style load/store **** # INDEX is used in new style load/store # INDEX takes a - (UPat(Ops.INDEX, src=(UPat(GroupOp.Defines), UPat())), lambda: True), - (UPat(Ops.INDEX, src=(UPat(GroupOp.Defines), UPat(), UPat(dtype=dtypes.bool))), lambda: True), - - # LOAD on STORE - (UPat(Ops.LOAD, src=(UPat(Ops.STORE),), allow_any_len=True), lambda: True), + (UPat(Ops.INDEX, src=(UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL)), UPat())), lambda: True), + (UPat(Ops.INDEX, src=(UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL)), UPat(), UPat(dtype=dtypes.bool))), lambda: True), # LOAD takes a - (UPat(Ops.LOAD, src=(index_pat, UPat(Ops.IF, name="cond")), allow_any_len=True), lambda idx,cond: validate_index(idx,cond.src[0])), - (UPat(Ops.LOAD, src=(index_pat,), allow_any_len=True), validate_index), + (UPat(Ops.LOAD, src=(index_pat,)), validate_index), + (UPat(Ops.LOAD, src=(index_pat, UPat(Ops.BARRIER))), validate_index), + (UPat(Ops.LOAD, src=(index_pat, UPat(Ops.IF, name="cond"))), lambda idx,cond: validate_index(idx,cond.src[0])), + (UPat(Ops.LOAD, src=(index_pat, UPat.var("alt")), name="ld"), lambda ld,alt,idx: ld.dtype == alt.dtype and validate_index(idx)), # STORE takes a - (UPat(Ops.STORE, src=(index_pat, UPat(name="val"), UPat(Ops.IF, name="gate")), allow_any_len=True), validate_store), - (UPat(Ops.STORE, src=(index_pat, UPat(name="val")), allow_any_len=True), validate_store), + (UPat(Ops.STORE, dtype=dtypes.void, src=(index_pat, UPat(name="val"))), validate_store), + (UPat(Ops.STORE, dtype=dtypes.void, src=(index_pat, UPat(name="val"), UPat(dtype=dtypes.bool, name="gate"))), validate_store), + (UPat(Ops.STORE, dtype=dtypes.void, src=(index_pat, UPat(name="val"), UPat(Ops.IF, name="gate"))), validate_store), # most ALUs have all matching dtypes, except CMPLT, CMPNE, and WHERE (UPat(Ops.WHERE, name="w", src=(UPat(dtype=dtypes.bool), UPat.var("x"), UPat.var("y"))), lambda w,x,y: w.dtype == x.dtype == y.dtype), - (UPat((Ops.CMPLT, Ops.CMPNE, Ops.CMPEQ), dtype=dtypes.bool, src=(UPat.var("x"), UPat.var("y"))), lambda x,y: x.dtype.base == y.dtype.base), + (UPat((Ops.CMPLT, Ops.CMPNE), dtype=dtypes.bool, src=(UPat.var("x"), UPat.var("y"))), lambda x,y: x.dtype.base == y.dtype.base), # and SHL/SHR, the shift distance can be an int (UPat((Ops.SHL, Ops.SHR), src=(UPat.var("x"), UPat.var("y")), name="a"), lambda a,x,y: a.dtype == x.dtype and y.dtype in (x.dtype, dtypes.uint)), (UPat((Ops.IDIV, Ops.MOD), name="x"), lambda x: None if dtypes.is_int(x.dtype) else False), (UPat(GroupOp.ALU, name="x"), lambda x: all(x.dtype.base == y.dtype.base for y in x.src)), + (UPat(Ops.ASSIGN, src=(UPat((Ops.DEFINE_ACC, Ops.DEFINE_GLOBAL)), UPat())), lambda: True), (UPat(Ops.ENDRANGE, dtype=dtypes.void, src=(UPat(Ops.RANGE),)), lambda: True), # WMMA has a @@ -221,7 +200,7 @@ spec = PatternMatcher([ # NOTE: for testing, we let sinks be anything #(UPat(Ops.SINK, src=UPat(Ops.STORE)), lambda: True), (UPat(Ops.SINK, dtypes.void), lambda: True), - (UPat((Ops.NOOP, Ops.CUSTOMI, Ops.CUSTOM, Ops.PRECAST)), lambda: True), + (UPat((Ops.NOOP, Ops.CUSTOMI, Ops.CUSTOM)), lambda: True), # PTX LOAD/STORE (UPat((Ops.LOAD, Ops.STORE), src=(UPat(dtype=dtypes.int64),), allow_any_len=True), lambda: True), @@ -229,7 +208,16 @@ spec = PatternMatcher([ # *** this is the UOp AST spec *** +def verify_sink_dims(sink:UOp): + if not all_same([s.shape for s in sink.src]): return False + for dims in zip(*[x.shape for x in sink.toposort() if x.st is not None]): + if len(n_dims:={s for s in dims if resolve(s!=1)}) > 1: + print(f"# INVALID KERNEL DIMS: can only have 1 or n in each dimension: {n_dims}") + return False + ast_spec = PatternMatcher([ + # shapes must have either 1 or n in each dimension + (UPat(Ops.SINK, src=UPat(Ops.STORE), name="sink"), verify_sink_dims), # VIEW can only exist in the edges (UPat(Ops.VIEW, src=(UPat((Ops.DEFINE_GLOBAL, Ops.DEFINE_LOCAL),))), lambda: True), (UPat(Ops.VIEW, name="view"), lambda view: len(view.src) == 0), @@ -245,4 +233,4 @@ def type_verify(uops:list[UOp], extra_spec:PatternMatcher|None=None): with Context(TRACK_MATCH_STATS=0): ret = check_spec.rewrite(u) if cast(bool|None, ret) is not True: if DEBUG >= 3: print_uops(uops) - raise RuntimeError(f"UOp verification failed at {i} on {u.op} {u.dtype} {len(u.src)} {[(x.op, x.dtype, x.arg) for x in u.src]} {u.arg}") + raise RuntimeError(f"UOp verification failed at {i} on {u.op} {u.dtype} {len(u.src)} {[x.op for x in u.src]} {u.arg}") diff --git a/tinygrad_repo/tinygrad/uop/symbolic.py b/tinygrad_repo/tinygrad/uop/symbolic.py index 4d3506704..91e0c56e8 100644 --- a/tinygrad_repo/tinygrad/uop/symbolic.py +++ b/tinygrad_repo/tinygrad/uop/symbolic.py @@ -1,11 +1,11 @@ # all of symbolic lives here now -from typing import cast +from typing import Any, Literal, cast import math, operator, struct, functools from collections import defaultdict from tinygrad.uop.ops import Ops, PatternMatcher, UPat, UOp, GroupOp, exec_alu -from tinygrad.dtype import ConstType, dtypes, PtrDType, AddrSpace, can_safe_cast +from tinygrad.dtype import ConstType, dtypes, PtrDType from tinygrad.helpers import partition, all_same, prod, flatten, get_single_element, cdiv, cmod, CORRECT_DIVMOD_FOLDING -from tinygrad.uop.decompositions import xpow +from tinygrad.uop.transcendental import xpow # ******** phase 1 of symbolic used to live in ops, it's the most generic folding rules ******** @@ -18,8 +18,7 @@ def simplify_pow(x:UOp, c:UOp) -> UOp|None: def fold_bitcast(root:UOp, c:UOp) -> UOp|None: if (from_fmt:=c.dtype.scalar().fmt) is None or (to_fmt:=root.dtype.scalar().fmt) is None: return None - if c.dtype.itemsize != root.dtype.itemsize: return None - def convert(v:ConstType): return struct.unpack(to_fmt, struct.pack(from_fmt, v))[0] + def convert(v:Any): return struct.unpack(to_fmt, struct.pack(from_fmt, v))[0] return root.const_like(convert(c.arg) if root.dtype.count == 1 else tuple(map(convert, c.arg))) symbolic_simple = PatternMatcher([ @@ -41,8 +40,6 @@ symbolic_simple = PatternMatcher([ (UPat(GroupOp.Idempotent, src=(UPat.var("x"), UPat.var("x"))), lambda x: x), (UPat.var("x", dtype=dtypes.bool).logical_not().logical_not(), lambda x: x), (UPat.var("x", dtype=dtypes.bool).where(UPat.const(dtypes.bool, True), UPat.const(dtypes.bool, False)), lambda x: x), - (UPat.var("x", dtype=dtypes.bool).where(UPat.const(dtypes.bool, False), UPat.const(dtypes.bool, True)), lambda x: x.logical_not()), - (UPat.var("x", dtype=dtypes.ints+(dtypes.bool,)).trunc(), lambda x: x), # ** zero folding ** (UPat.var("x") < UPat.var("x"), lambda x: x.const_like(False).cast(dtypes.bool.vec(x.dtype.count))), # x < x -> False (UPat.var("x") % UPat.var("x"), lambda x: x.const_like(0)), # x%x -> 0 @@ -67,28 +64,10 @@ symbolic_simple = PatternMatcher([ (UPat(Ops.CAST, name="root", src=(UPat.cvar("c"),)), lambda root, c: root.const_like(c.arg)), (UPat((Ops.CAST, Ops.BITCAST), name="root"), lambda root: root.src[0] if root.dtype == root.src[0].dtype else None), (UPat(Ops.BITCAST, name="root", src=(UPat.cvar("c"),)), fold_bitcast), - # b.cast(a).cast(b) -> b if a preserves all values in b - (UPat.var('x').cast(name="a").cast(name="b"), lambda x,a,b: x if x.dtype == b.dtype and can_safe_cast(b.dtype, a.dtype) else None), - # if the intermediate cast doesnt narrow we can do it in one cast, we have to be carefull with bfloat16 - (UPat.var('x').cast(name="a").cast(name="b"), lambda x,a,b: x.cast(b.dtype) if can_safe_cast(x.dtype, a.dtype) and - not (a.dtype==dtypes.float and (b.dtype==dtypes.bfloat16 or x.dtype==dtypes.bfloat16)) else None), # ** pow ** (UPat.var("x").alu(Ops.POW, UPat.cvar("c", vec=False)), simplify_pow), # positive const ** x (UPat.cvar("c", vec=False).alu(Ops.POW, UPat.var("x")), lambda c,x: c if c.arg == 1 else (x*math.log2(c.arg)).exp2() if c.arg > 0 else None), - # rules for threefry - ((UPat.var('x', dtypes.uint64)&0xFFFFFFFF).cast(dtypes.uint32), lambda x: x.cast(dtypes.uint32)&0xFFFFFFFF), # TODO: why is the and needed? - (((UPat.var(None, dtypes.uint64)*(1<<32)) | UPat.var('y', dtypes.uint32).cast(dtypes.uint64)).cast(dtypes.uint32), lambda y: y), - (((UPat.var('x', dtypes.uint64)*(1<<32)) | UPat.var(None, dtypes.uint32).cast(dtypes.uint64))//(1<<32), lambda x: x), - # hacks for threefry long removal when padded (TODO: genericize) - (UPat.var('x', dtypes.uint32).cast(dtypes.uint64) * UPat.var('y').where(UPat.const(dtypes.uint64, 1<<32), UPat.const(dtypes.uint64, 0)), - lambda x,y: y.where(x, 0).cast(dtypes.uint64) * (1<<32)), - ((UPat.var('x', dtypes.uint64)&(UPat.var('y').where(UPat.const(dtypes.uint64, 0xFFFFFFFF), UPat.const(dtypes.uint64, 0)))).cast(dtypes.uint32), - lambda x,y: y.where(x.cast(dtypes.uint32), 0)), - # new decomp rules for threefry - (((UPat.var(None, dtypes.uint64)<<32) | UPat.var('y', dtypes.uint32).cast(dtypes.uint64)).cast(dtypes.uint32), lambda y: y), - (((UPat.var('x', dtypes.uint64)<<32) | UPat.var(None, dtypes.uint32).cast(dtypes.uint64))>>32, lambda x: x), - (UPat.var('b').where(UPat.var('x', dtypes.uint32).cast(dtypes.uint64), UPat.const(dtypes.uint64, 0)).cast(dtypes.uint32), lambda b,x: b.where(x,0)) ]) # ******** phase 2 builds on phase 1, it includes the old "symbolic", rules that match deeper ******** @@ -143,91 +122,64 @@ def canonicalize_simplex(X:UOp) -> UOp|None: ret.append(u) return functools.reduce(operator.add, ret) if changed else None -def cancel_divmod(d: UOp, x: UOp, y: UOp) -> UOp|None: - # simple cancel div/mod case when the range of the numerator lies within a single denominator interval +def div_and_mod_folding(x: UOp, y: UOp, which: Literal[Ops.MOD, Ops.IDIV], split_rem: bool=False) -> UOp|None: + # simplify x // y or x % y, None means no change + # simple cancel div/mod case x_min, x_max, y_min, y_max = x.vmin, x.vmax, y.vmin, y.vmax assert isinstance(x_min, int) and isinstance(x_max, int) and isinstance(y_min, int) and isinstance(y_max, int) - if y_min==y_max==0: raise ZeroDivisionError(f"{'Division' if d.op is Ops.IDIV else 'Mod'} by zero trying to rewrite {x.alu(d.op, y)}") + if y_min*y_max > 0 and (q:=cdiv(x_min,y_min)) == cdiv(x_min,y_max) == cdiv(x_max,y_min) == cdiv(x_max,y_max): - return x - q*y if d.op is Ops.MOD else d.const_like(q) - return None + return x - q*y if which is Ops.MOD else x.const_like(q) -def remove_nested_mod(m: UOp, x: UOp, y: UOp) -> UOp|None: - # remove nested mod in case the inner mod is a multiple of the outer mod - # example: (a%4 + b)%2 -> (a+b)%2 - if ((c := y.arg) < 0) or x.vmin<0: return None - new_xs = [] - something_changed = False + if (y.op is not Ops.CONST) or ((c := y.arg) <= 0) or (x.dtype.count > 1): return None + + svars, factors, quotients, remainders, gcd, div, const, something_changed = [], [], [], [], c, 1, 0, False for u in split_uop(x, Ops.ADD): - if u.op is Ops.MOD: - if u.src[1].divides(c) is not None: - something_changed = True - u = u.src[0] - new_xs.append(u) - new_x: UOp = functools.reduce(operator.add, new_xs) - if something_changed and new_x.vmin>=0: return new_x % y - return None + if u.op is Ops.MOD and which is Ops.MOD and u.src[1].op is Ops.CONST and u.src[1].arg%c == 0: + u = u.src[0] + something_changed = True + v: UOp = u.divides(f:=u.const_factor()) + q, r = divmod(f, c) + if r==0 or ((which is Ops.MOD or split_rem or u.op is Ops.CONST) and r!=f): something_changed = True + if u.op is Ops.CONST: const += f + else: # div is the smallest common divisor of all terms + if f > 1 and c % f == 0 and (div == 1 or div > f): div = f + gcd = math.gcd(r, gcd) + factors.append(f); svars.append(v); quotients.append(q); remainders.append(r) # noqa: E702 -def fold_binary_numerator(d: UOp, x: UOp, y: UOp) -> UOp|None: # we can fold if the expression has only one non-constant term and this term can only take on two values - if ((c := y.arg) < 0) or (x.dtype.count > 1): return None - x,const = x.pop_const() - terms, factors = zip(*[(u.divides(f:=u.const_factor()),f) for u in split_uop(x, Ops.ADD)]) - if len(terms)==1 and (v:=terms[0]).vmax-v.vmin == 1: - y1 = cmod(factors[0]*v.vmin+const, c) if d.op is Ops.MOD else cdiv(factors[0]*v.vmin+const, c) # type: ignore - y2 = cmod(factors[0]*v.vmax+const, c) if d.op is Ops.MOD else cdiv(factors[0]*v.vmax+const, c) # type: ignore + if len(svars)==1 and (v:=svars[0]).vmax-v.vmin == 1: + y1 = cmod(factors[0]*v.vmin+const, c) if which is Ops.MOD else cdiv(factors[0]*v.vmin+const, c) + y2 = cmod(factors[0]*v.vmax+const, c) if which is Ops.MOD else cdiv(factors[0]*v.vmax+const, c) return (y2-y1)*(v-v.vmin) + y1 - return None -def fold_divmod_congruence(d: UOp, x: UOp, y: UOp) -> UOp|None: - # within a mod we can freely subtract multiples of c, we use this to see if a is congruent to an expression whose vmin/vmax are between 0 and c - if (x.vmin<0 and CORRECT_DIVMOD_FOLDING) or ((c := y.arg) < 0) or (x.dtype.count > 1): return None - x,const = x.pop_const() - terms, factors = zip(*[(u.divides(f:=u.const_factor()),f) for u in split_uop(x, Ops.ADD)]) - # a//c = (a-a%c)/c, if we can fold a%c, we can fold a//c - rems = [min((r:=f%c), r-c, key=abs) for f in factors] - if (rem:=sum(r*v for r,v in zip(rems,terms))+const%c).vmin//c!=rem.vmax//c: return None - if d.op is Ops.MOD: return rem - rem.vmin//c*c - return sum((f-r)//c * v for f,r,v in zip(factors,rems,terms)) + (const-const%c+rem.vmin//c*c)//c + if not CORRECT_DIVMOD_FOLDING or x_min>=0: + # a//c = (a-a%c)/c, if we can fold a%c, we can fold a//c + # within a mod we can freely subtract multiples of c, we use this to see if a is congruent to an expression whose vmin/vmax are between 0 and c + rems = [min(r, r-c, key=abs) for r in remainders] + if (rem:=sum(r*v for r,v in zip(rems,svars))+const%c).vmin//c==rem.vmax//c and all(f > 0 for f in factors): + if which is Ops.MOD: return rem - rem.vmin//c*c + return sum((f-r)//c * v for f,r,v in zip(factors,rems,svars)) + (const-const%c+rem.vmin//c*c)//c -def divide_by_gcd(d: UOp, x: UOp, y: UOp) -> UOp|None: - # x//y -> (x//gcd)//(y//gcd) or x%y -> gcd*(x//gcd)%(y//gcd) - terms, factors = zip(*[(u.divides(f:=u.const_factor()),f) for u in split_uop(x, Ops.ADD)]) - if (gcd := math.gcd(y.arg, *factors)) == 1: return None - ret = sum(f//gcd * v for f,v in zip(factors, terms)).alu(d.op, y.const_like(y.arg//gcd)) - return ret*gcd if d.op is Ops.MOD else ret - -def nest_div_by_smallest_factor(d: UOp, x: UOp, y: UOp) -> UOp|None: - # we try and nest the div and see if it allows the numerator to be simplified - if ((c := y.arg) < 0) or (x.dtype.count > 1): return None - factors = [u.const_factor() for u in split_uop(x.pop_const()[0], Ops.ADD)] - # div is the smallest factor of the denominator (greater than 1) out of all "factors" - # TODO: there are better ways to pick `div`, this sometimes adds extra divisions - # TODO: add same optimization for mod - div = min([y.arg]+[abs(f) for f in factors if abs(f) > 1 and (c%f)==0]) - if (1 < div < c) and (newxs:=(newx:=(x//div)).simplify()) is not newx and x.vmin>=0 and newx.vmin>=0: return newxs//(c//div) - return None - -def simplify_remainder(d: UOp, x: UOp, y: UOp) -> UOp|None: - # we try and take out the quotient and see if it allows the numerator to be simplified - if ((c := y.arg) < 0) or (x.dtype.count > 1): return None - x_no_const,const = x.pop_const() - terms, factors = zip(*[(u.divides(f:=u.const_factor()),f) for u in split_uop(x_no_const, Ops.ADD)]) - quotients, remainders = zip(*[divmod(f, c) for f in factors]) - gcd = math.gcd(c, *remainders) # gcd without const! - if const%c==const and gcd==1 and not any(r==0 or (r!=f and d.op is Ops.MOD) for r,f in zip(remainders, factors)): return None + if (g:=math.gcd(gcd, const))!=1: + ret = UOp(which, x.dtype, src=(sum(f//g * v for f,v in zip(factors, svars)) + const//g, x.const_like(c//g))) + return ret*g if which is Ops.MOD else ret + if gcd != 1: something_changed = True + if not something_changed: + if which is Ops.IDIV and (1 < div < c) and (newx:=div_and_mod_folding(x, x.const_like(div), Ops.IDIV)) is not None: return newx//(c//div) + return None quo, rem = x.const_like(const//c), x.const_like((const%c)//gcd) - for q,r,f,v in zip(quotients, remainders, factors, terms): - if d.op is Ops.IDIV and r!=0: + for q,r,f,v in zip(quotients, remainders, factors, svars): + if which is Ops.IDIV and (not split_rem) and r!=0: rem += f//gcd * v else: rem += r//gcd * v quo += q * v # if numerator before/after is negative, and it has remainder, don't simplify because C divmod is different from python divmod. - if (x.vmin < 0 or rem.vmin < 0) and remainders: return None - if d.op is Ops.MOD: return gcd*(rem % (c//gcd)) + const%gcd + if (x_min < 0 or rem.vmin < 0) and remainders: return None + if which is Ops.MOD: return gcd*(rem % (c//gcd)) + const%gcd return rem//(c//gcd)+quo def gep_through_wmma(gep:UOp, wmma:UOp): @@ -245,18 +197,18 @@ def gep_through_wmma(gep:UOp, wmma:UOp): gep_pushing = PatternMatcher([ # GEP/VECTORIZE, GEP/GEP, GEP/CONST, GEP/VCONST - (UPat(Ops.GEP, name='g2').f(Ops.GEP, name='g1'), + (UPat(Ops.GEP, src=(UPat(Ops.GEP, name='g2'),), name='g1'), lambda g1, g2: g2.src[0].gep(tuple(g2.arg[g1.arg[i]] for i in range(len(g1.arg))))), - (UPat(Ops.VECTORIZE, name='vec').f(Ops.GEP, name='gep'), + (UPat(Ops.GEP, src=(UPat(Ops.VECTORIZE, name="vec"),), name="gep"), lambda gep, vec: UOp(Ops.VECTORIZE, gep.dtype, tuple(vec.src[i] for i in gep.arg)) if len(gep.arg) > 1 else vec.src[gep.arg[0]]), - (UPat.cvar("c", vec=False).f(Ops.GEP, name="gep"), lambda gep, c: gep.const_like(c.arg)), - (UPat(Ops.VCONST, name="c").f(Ops.GEP, name="gep"), lambda gep, c: gep.const_like(tuple(c.arg[x] for x in gep.arg))), + (UPat(Ops.GEP, src=(UPat.cvar("c", vec=False),), name="gep"), lambda gep, c: gep.const_like(c.arg)), + (UPat(Ops.GEP, src=(UPat(Ops.VCONST, name="c"),), name="gep"), lambda gep, c: gep.const_like(tuple(c.arg[x] for x in gep.arg))), # GEP on void is skipped (UPat(Ops.GEP, src=(UPat(dtype=dtypes.void, name="x"),)), lambda x: x), # GEP in order is removed (UPat(Ops.GEP, name="g"), lambda g: g.src[0] if not isinstance(g.dtype, PtrDType) and g.arg == tuple(range(g.src[0].dtype.count)) else None), # push all GEPs through ALUs (fix arange stuff) - (UPat((*GroupOp.ALU, Ops.CAST, Ops.BITCAST), name='alu').f(Ops.GEP, name='gep'), + (UPat(Ops.GEP, src=(UPat((*GroupOp.ALU, Ops.CAST, Ops.BITCAST), name='alu'),), name='gep'), lambda gep,alu: UOp(alu.op, alu.dtype.scalar().vec(gep.dtype.count), tuple(x.gep(gep.arg) for x in alu.src), alu.arg) \ if not isinstance(gep.dtype, PtrDType) else None), # CAT can't be rendered. it's a VECTORIZE on vectors, we expand to a single VECTORIZEs with GEPs (TODO: move this later) @@ -265,7 +217,7 @@ gep_pushing = PatternMatcher([ # VECTORIZE on same GEP (UPat(Ops.VECTORIZE, name="v", src=UPat(Ops.GEP, src=(UPat.var("x"),))), lambda v,x: x.gep(tuple(get_single_element(i.arg) for i in v.src))), # push some GEPs through WMMAs - (UPat(Ops.WMMA, name="wmma").f(Ops.GEP, name="gep"), gep_through_wmma), + (UPat(Ops.GEP, src=(UPat(Ops.WMMA, name="wmma"),), name="gep"), gep_through_wmma), ]) commutative = PatternMatcher([ @@ -282,13 +234,10 @@ symbolic = symbolic_simple+commutative+PatternMatcher([ ((UPat.var("y") + UPat.var("x") * UPat.cvar("c0")) + UPat.var("x") * UPat.cvar("c1"), lambda x,y,c0,c1: y+x*(c0+c1)), (UPat.var("x") + UPat.var("x") * UPat.cvar("c"), lambda x,c: x*(c+1)), # (x+x*c)-> x*(c+1) ((UPat.var("y") + UPat.var("x")) + UPat.var("x") * UPat.cvar("c"), lambda x,y,c: y+x*(c+1)), - ((UPat.var("y") + UPat.var("x") * UPat.cvar("c")) + UPat.var("x"), lambda x,y,c: y+x*(c+1)), (UPat.var("x") + UPat.var("x"), lambda x: x*2), # (x+x)-> x*2 ((UPat.var("y") + UPat.var("x")) + UPat.var("x"), lambda y,x: y+x*2), ((UPat.var("x") / UPat.var("x2")) / UPat.var("x3"), lambda x,x2,x3: x/(x2*x3) if x2 is not x3 else None), # (x/x2)/x3 -> x/(x2*x3) (-1 * (UPat.var("x") + UPat.cvar("c")), lambda x,c: (-x)+(-c)), # -(x+c) -> -x + -c - (UPat.var('x', dtypes.ints).cast(dtypes.ints, name="a").cast(dtypes.ints, name="b"), - lambda x,a,b: x.cast(b.dtype) if a.dtype.min<=x.vmin and x.vmax<=a.dtype.max else None), # a conditional with the same results either way is a noop, also fold const conditionals (UPat.var().where(UPat.var("val"), UPat.var("val")), lambda val: val), (UPat.cvar("gate", vec=False).where(UPat.var("c0"), UPat.var("c1")), lambda gate, c0, c1: c0 if gate.arg else c1), @@ -296,9 +245,6 @@ symbolic = symbolic_simple+commutative+PatternMatcher([ # alu of two where with same conds can combine, only do if true branch or false branch is const (UPat(GroupOp.Binary, name="alu", src=(UPat.var("c").where(UPat.var("t"), UPat.var("f")), UPat.var("c").where(UPat.var("tt"), UPat.var("ff")))), \ lambda alu,c,t,tt,f,ff: c.where(t.alu(alu.op, tt), f.alu(alu.op, ff)) if t.op == tt.op == Ops.CONST or f.op == ff.op == Ops.CONST else None), - # if its a plus we add the associative variation too - ((UPat.var("y")+UPat.var("c").where(UPat.var("t"), UPat.var("f"))) + UPat.var("c").where(UPat.var("tt"), UPat.var("ff")), \ - lambda y,c,t,tt,f,ff: y+c.where(t+tt, f+ff) if t.op == tt.op == Ops.CONST or f.op == ff.op == Ops.CONST else None), # ALU/variable min==max -> CONST (slow!) (UPat(GroupOp.ALU|{Ops.DEFINE_VAR, Ops.SPECIAL, Ops.RANGE}, name="x"), lambda x: x.const_like(x.vmin) if x.vmin == x.vmax else None), # max folding @@ -338,24 +284,15 @@ symbolic = symbolic_simple+commutative+PatternMatcher([ # div folding ((UPat.var("x")//UPat.cvar("c") + UPat.cvar("a"))//UPat.cvar("d"), lambda x,c,a,d: (x+a*c)//(c*d) if c.vmin>0 and d.vmin>0 and ((x.vmin>=0 and a.vmin>=0) or (x.vmax<=0 and a.vmax<=0)) else None), # (x//c+a)//d -> (x+a*c)//(c*d) - # a range mod its own upper bound is just the range - (UPat(Ops.RANGE, src=UPat.var("end"), name="r")%UPat.var("end"), lambda r,end: r), - (UPat(Ops.RANGE, src=UPat.var("end"), name="r")//UPat.var("end"), lambda r,end: r.const_like(0)), - (UPat((Ops.IDIV, Ops.MOD), dtypes.sints, name="d", src=(UPat.var("x"), UPat.var("y"))), cancel_divmod), - (UPat((Ops.IDIV, Ops.MOD), dtypes.sints, name="d", src=(UPat.var("x"), UPat.cvar("y", vec=False))), fold_binary_numerator), - (UPat((Ops.IDIV, Ops.MOD), dtypes.sints, name="d", src=(UPat.var("x"), UPat.cvar("y", vec=False))), fold_divmod_congruence), - (UPat((Ops.IDIV, Ops.MOD), dtypes.sints, name="d", src=(UPat.var("x"), UPat.cvar("y", vec=False))), divide_by_gcd), - (UPat(Ops.MOD, dtypes.sints, name="m", src=(UPat.var("x"), UPat.cvar("y", vec=False))), remove_nested_mod), - (UPat((Ops.IDIV), dtypes.sints, name="d", src=(UPat.var("x"), UPat.cvar("y", vec=False))), nest_div_by_smallest_factor), - (UPat((Ops.IDIV, Ops.MOD), dtypes.sints, name="d", src=(UPat.var("x"), UPat.cvar("y", vec=False))), simplify_remainder), - (UPat.var("x") // UPat.var("d"), lambda x,d: -(x//(-d)) if d.vmax < 0 else None), + (UPat.var("x", dtypes.sints) // UPat.var("y"), lambda x,y: div_and_mod_folding(x,y,Ops.IDIV)), + (UPat.var("x") // UPat.var("d"), lambda x,d: -(x//(-d)) if d.vmax <=0 else None), (UPat.var("x") // UPat.var("d"), lambda x,d: -((-x)//d) if x.vmax <=0 else None), ((UPat.var("x", dtypes.sints)+UPat.cvar("c", vec=False)).named("n")//UPat.cvar("d", vec=False), lambda x,c,n,d: (-(-(c.arg%d.arg + x - (d.arg-1))//d) + c.arg//d.arg) if x.vmax<=0 and n.vmin>=0 and d.arg>0 else None), # ** mod ** # mod folding - (UPat.var("x") % UPat.var("d"), lambda x,d: -((-x)%d) if x.vmax <= 0 else None), - (UPat.var("x") % UPat.var("d"), lambda x,d: (x%(-d)) if d.vmax < 0 else None), + (UPat.var("x") % UPat.var("y"), lambda x,y: div_and_mod_folding(x,y,Ops.MOD)), + (UPat.var("x") % UPat.var("d"), lambda x,d: -((-x)%d) if x.vmax <=0 else None), ])+gep_pushing symbolic_flat = symbolic+PatternMatcher([ @@ -436,6 +373,22 @@ def simplify_valid(valid:UOp) -> UOp|None: if ret[-1] is not stmt: something_changed = True return functools.reduce(operator.and_, ret) if something_changed else None +# ***** threefry ***** + +def threefry2x32(x: UOp, key: UOp): + # split x and key from uint64 to two uint32 + x0, x1 = (x & 0xffffffff).cast(dtypes.uint32), ((x // 2**32) & 0xffffffff).cast(dtypes.uint32) + key0, key1 = (key & 0xffffffff).cast(dtypes.uint32), ((key // 2**32) & 0xffffffff).cast(dtypes.uint32) + + rotations = [[13, 15, 26, 6], [17, 29, 16, 24]] + ks = [key1, key0 ^ key1 ^ 0x1BD11BDA, key0] + xr = [x0 + ks[-1], x1 + ks[0]] + for i in range(5): + for r in rotations[i % 2]: xr[0], xr[1] = (x0 := xr[0] + xr[1]), x0 ^ ((xr[1] * 2**r) + (xr[1] // 2**(32 - r))) + xr = [(xr[0] + ks[i % 3]), (xr[1] + ks[(i + 1) % 3] + i + 1)] + + return xr[1].cast(dtypes.uint64) * 2**32 | xr[0].cast(dtypes.uint64) + # ******** phase 3 is the complete symbolic, and deals with very complex things like loop rewriting and threefry transform ******** def reduce_mul_chain(r:UOp): @@ -450,12 +403,9 @@ def reduce_mul_chain(r:UOp): return r.replace(src=(prod(inside) if len(inside) else r.src[0].const_like(1),)+r.src[1:])*prod(outside) # this is symbolic 2.0 -REMOVE_FROM_SINK = {Ops.SINK, Ops.UNROLL, Ops.PTRCAT, Ops.CAT, Ops.NOOP} -REMOVE_FROM_BARRIER = {Ops.VECTORIZE, Ops.SINK, Ops.CAT, Ops.PTRCAT, Ops.NOOP} sym = symbolic_flat+PatternMatcher([ - # LOAD/STORE -> NOOP - (UPat.var('x').store(UPat.var('x').load(), allow_any_len=True), lambda x: None if x.dtype.addrspace != AddrSpace.REG else x.src[0].src[0]), - (UPat(Ops.LOAD, src=(UPat.cvar('c'))), lambda c: c), + # self ASSIGN is just self + (UPat(Ops.ASSIGN, src=(UPat.var('x'), UPat.var('x'))), lambda x: x), # VECTORIZE/CONST, VECTORIZE/GEP (UPat(Ops.VECTORIZE, src=UPat(Ops.CONST), name="vec"), lambda vec: UOp.const(vec.dtype, tuple(x.arg for x in vec.src))), (UPat(Ops.VECTORIZE, src=UPat(Ops.GEP, src=(UPat.var("x"),)), name="vec"), lambda vec,x: x.gep(tuple(y.arg[0] for y in vec.src))), @@ -470,7 +420,20 @@ sym = symbolic_flat+PatternMatcher([ # tensor core with a 0 input is acc (UPat(Ops.WMMA, src=(UPat.const(None, 0.0), UPat.var(), UPat.var("acc"))), lambda acc: acc), (UPat(Ops.WMMA, src=(UPat.var(), UPat.const(None, 0.0), UPat.var("acc"))), lambda acc: acc), + # threefry + remove longs + (UPat(Ops.THREEFRY, dtype=dtypes.uint64, src=(UPat.var("x"), UPat.var("key"))), threefry2x32), + (UPat.var('x', dtypes.uint32).cast(dtypes.uint64).cast(dtypes.uint32), lambda x: x), # cast there and back is noop (TODO: genericize) + ((UPat.var('x', dtypes.uint64)&0xFFFFFFFF).cast(dtypes.uint32), lambda x: x.cast(dtypes.uint32)), # cast does truncation + (((UPat.var(None, dtypes.uint64)*(1<<32)) | UPat.var('y', dtypes.uint32).cast(dtypes.uint64)).cast(dtypes.uint32), lambda y: y), + (((UPat.var('x', dtypes.uint64)*(1<<32)) | UPat.var(None, dtypes.uint32).cast(dtypes.uint64))//(1<<32), lambda x: x), + # hacks for threefry long removal when padded (TODO: genericize) + (UPat.var('x', dtypes.uint32).cast(dtypes.uint64) * UPat.var('y').where(UPat.const(dtypes.uint64, 1<<32), UPat.const(dtypes.uint64, 0)), + lambda x,y: y.where(x, UOp.const(dtypes.uint32, 0)).cast(dtypes.uint64) * (1<<32)), + ((UPat.var('x', dtypes.uint64)&(UPat.var('y').where(UPat.const(dtypes.uint64, 0xFFFFFFFF), UPat.const(dtypes.uint64, 0)))).cast(dtypes.uint32), + lambda x,y: y.where(x.cast(dtypes.uint32), UOp.const(dtypes.uint32, 0))), # ** self folding ** + (UPat(Ops.DEFINE_ACC, src=(UPat.var("x"),)), lambda x: x), # a DEFINE_ACC without ranges is a CONST + (UPat(Ops.ASSIGN, src=(UPat.cvar(),UPat.var("x"))), lambda x: x), # an ASSIGN to a const is a NOOP # x!=0 -> (bool)x (UPat.var("x")!=0, lambda x: x.cast(dtypes.bool.vec(x.dtype.count))), # ** where ** @@ -480,27 +443,25 @@ sym = symbolic_flat+PatternMatcher([ (UPat.var("a").where(UPat.var("b").where(UPat.var("c"), UPat.var("d")), UPat.var("d")), lambda a,b,c,d: (a&b).where(c,d)), # ** pow ** ((UPat(Ops.POW, name="p"), lambda p: xpow(*p.src))), - # index true is index without op - (UPat(Ops.INDEX, src=(UPat.var("b"), UPat.var("idx"), UPat.const(dtypes.bool, True))), lambda b, idx: b.index(idx)), # ** load/store folding ** (UPat.store(UPat(Ops.INDEX, name="index"), UPat.load(UPat(Ops.INDEX, name="index"))), lambda index: UOp(Ops.NOOP)), - (UPat.store(UPat(Ops.INDEX, name="index"), UPat.var("gate").where(UPat.var("alt"), - UPat.load(UPat(Ops.INDEX, name="index"))), allow_any_len=True, name="store"), - lambda index, gate, alt, store: UOp.store(index.src[0].index(index.src[1], gate), alt, *store.src[2:])), + (UPat.store(UPat(Ops.INDEX, name="index"), UPat.var("gate").where(UPat.var("alt"), UPat.load(UPat(Ops.INDEX, name="index")))), + lambda index, gate, alt: UOp.store(index.src[0].index(index.src[1], gate), alt)), # fold gated LOAD/STORE (UPat().index(UPat(), UPat.const(dtypes.bool, True)).named("idx"), lambda idx: idx.replace(src=idx.src[0:2])), # remove True - (UPat((Ops.LOAD, Ops.STORE), src=(UPat().index(UPat(), UPat.const(dtypes.bool, False)).or_casted(),), allow_any_len=True, name="x"), - lambda x: UOp(Ops.NOOP) if x.op is Ops.STORE else x.const_like(0)), # NULL pointer store does nothing. NULL pointer load produces 0 - # remove VECTORIZE from SINK/BARRIER. TODO: SINK/BARRIER are really the same thing at GLOBAL/LOCAL levels - (UPat(Ops.BARRIER, name="root"), - lambda root: UOp(Ops.BARRIER, root.dtype, tuple(flatten(x.src if x.op in REMOVE_FROM_BARRIER else (x,) for x in root.src)), root.arg) - if any(x.op in REMOVE_FROM_BARRIER for x in root.src) else None), + (UPat().index(UPat(), UPat.const(dtypes.bool, False)).named("idx"), lambda idx: idx.const_like(0)), # False -> NULL pointer + (UPat(Ops.LOAD, src=(UPat.const(None, 0),), allow_any_len=True, name="x"), lambda x: x.const_like(0)), # NULL pointer load loads 0 + (UPat(Ops.STORE, src=(UPat.const(None, 0),), allow_any_len=True), lambda: UOp(Ops.NOOP)), # NULL pointer store does nothing + # remove NOOPs from SINK (UPat(Ops.SINK, name="root"), - lambda root: UOp(Ops.SINK, root.dtype, tuple(flatten(x.src if x.op in REMOVE_FROM_SINK else (x,) for x in root.src)), root.arg) - if any(x.op in REMOVE_FROM_SINK for x in root.src) else None), + lambda root: UOp(Ops.SINK, root.dtype, a, root.arg) if len(a:=tuple(x for x in root.src if x.op is not Ops.NOOP)) != len(root.src) else None), + # remove VECTORIZE from SINK/BARRIER + (UPat(Ops.BARRIER, src=(UPat((Ops.VECTORIZE, Ops.SINK), name='sink'),)), lambda sink: UOp(Ops.BARRIER, dtypes.void, sink.src)), + (UPat(Ops.SINK, name="root"), + lambda root: UOp(Ops.SINK, root.dtype, tuple(flatten(x.src if x.op in {Ops.SINK, Ops.UNROLL} else (x,) for x in root.src)), root.arg) + if any(x.op in {Ops.SINK, Ops.UNROLL} for x in root.src) else None), ((UPat.var("x") * UPat.var("x")).reciprocal(), lambda x: x.reciprocal()*x.reciprocal()), # 1/(x^c) -> (1/x)^c ((UPat.var("x") * UPat.var("x") * UPat.var("x")).reciprocal(), lambda x: x.reciprocal()*x.reciprocal()*x.reciprocal()), - ((UPat.var("x") * UPat.cvar("c")).reciprocal(), lambda x,c: x.reciprocal()*c.reciprocal()), # 1/(x*c) -> (1/c)*(1/x) (UPat.var("x") * ((1+UPat.var("x")).reciprocal().named("d")), lambda x,d: 1-d), # x*/(1+x) -> 1-1/(1+x) (UPat.var("x") * ((1+UPat.var("x")).reciprocal().named("d")*UPat.var("y")), lambda x,y,d: y*(1-d)), (UPat.var("x") * ((1+UPat.var("x")).reciprocal().named("d")+UPat.var("y")), lambda x,y,d: (1-d)+x*y), diff --git a/tinygrad_repo/tinygrad/uop/decompositions.py b/tinygrad_repo/tinygrad/uop/transcendental.py similarity index 59% rename from tinygrad_repo/tinygrad/uop/decompositions.py rename to tinygrad_repo/tinygrad/uop/transcendental.py index 57ce30342..3fff6e09b 100644 --- a/tinygrad_repo/tinygrad/uop/decompositions.py +++ b/tinygrad_repo/tinygrad/uop/transcendental.py @@ -1,11 +1,9 @@ -from typing import Callable -import math, functools -from tinygrad.dtype import dtypes, DType, promo_lattice -from tinygrad.device import is_dtype_supported -from tinygrad.helpers import polyN, DISABLE_FAST_IDIV -from tinygrad.uop.ops import UOp, UPat, Ops, PatternMatcher +import math +from tinygrad.dtype import dtypes, DType +from tinygrad.helpers import polyN +from tinygrad.uop.ops import UOp -TRANSCENDENTAL_DTYPES = (dtypes.float16, dtypes.float32, dtypes.float64) +TRANSCENDENTAL_SUPPORTED_DTYPES = (dtypes.float16, dtypes.float32, dtypes.float64) def _lazy_map_numbers(x:UOp, inf:UOp, _inf:UOp, nan:UOp, ratio:UOp): """replace inf -> inf, -inf -> _inf, nan -> nan, otherwise -> ratio""" @@ -32,14 +30,14 @@ def pow2if(q:UOp, float_dtype:DType): def ilogb2k(d:UOp) -> UOp: """calculate the integer part of log2(d), where d is normalized fp value in the range of [0, +inf).""" - assert d.dtype.scalar() in TRANSCENDENTAL_DTYPES + assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES dint = d.bitcast({dtypes.float64: dtypes.int64, dtypes.float32: dtypes.int32, dtypes.float16: dtypes.int16}[d.dtype.scalar()].vec(d.dtype.vcount)) # -1 <= ilog2bk(d) <= 128 return (shr(dint, mantissa_bits(d.dtype)) & exponent_mask(d.dtype)) - exponent_bias(d.dtype) def ldexp3k(d:UOp, e:UOp) -> UOp: """d*2^e. e is a number obtained by casting an integer in the range [-127, 127] to a float. d is any float number.""" - assert d.dtype.scalar() in TRANSCENDENTAL_DTYPES and e.dtype.scalar() in TRANSCENDENTAL_DTYPES + assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES and e.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES dtype = {dtypes.float64: dtypes.int64, dtypes.float32: dtypes.int32, dtypes.float16: dtypes.int16}[d.dtype.scalar()].vec(d.dtype.count) m1 = d.bitcast(dtype) m2 = shl(e.cast(dtype), mantissa_bits(d.dtype)) @@ -47,12 +45,12 @@ def ldexp3k(d:UOp, e:UOp) -> UOp: def ldexp2k(d:UOp, e:UOp) -> UOp: """d*2^e. much faster than ldexp3k but risky. d > 0 and d is not denormal.""" - assert d.dtype.scalar() in TRANSCENDENTAL_DTYPES and e.dtype.scalar() in (dtypes.int16, dtypes.int32, dtypes.int64) + assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES and e.dtype.scalar() in (dtypes.int16, dtypes.int32, dtypes.int64) return (d * pow2if(shr(e, 1), d.dtype)) * pow2if(e - shr(e, 1), d.dtype) def frexp(v:UOp) -> tuple[UOp, UOp]: """frexp(v) -> (mantissa, exponent) assuming v != 0""" - assert v.dtype.scalar() in TRANSCENDENTAL_DTYPES + assert v.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES # m1 = masks for mantissa, m2 = masks to normalize the mantissa. m1 = {dtypes.float64: 0x000FFFFFFFFFFFFF, dtypes.float32: 0x807FFFFF, dtypes.float16: 0x83FF}[v.dtype.scalar()] m2 = {dtypes.float64: 0x3FE0000000000000, dtypes.float32: 0x3F000000, dtypes.float16: 0x3800}[v.dtype.scalar()] @@ -72,7 +70,7 @@ def payne_hanek_reduction(d:UOp) -> tuple[UOp, UOp]: - `r`[d.dtype] is the reminder value corresponding to `round_to_nearest(x % pi/2)`. - `q`[int32] is an integer, and q % 4 is corresponding to the quadrant of the original angle `d`. """ - assert d.dtype.scalar() in TRANSCENDENTAL_DTYPES + assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES # https://stackoverflow.com/questions/30463616/payne-hanek-algorithm-implementation-in-c/30465751#30465751 # 190 bits of 2/pi for Payne-Hanek style argument reduction two_over_pi_f = [0x00000000, 0x28be60db, 0x9391054a, 0x7f09d5f4, 0x7d4d3770, 0x36d8a566, 0x4f10e410] @@ -80,10 +78,10 @@ def payne_hanek_reduction(d:UOp) -> tuple[UOp, UOp]: intermediate_dtype = dtypes.float32.vec(d.dtype.count) if d.dtype.base.scalar() == dtypes.float16 else d.dtype f, e = frexp(d) - ia = (f.cast(intermediate_dtype) * 4.294967296e9).cast(dtypes.uint64) + ia = (f.cast(intermediate_dtype) * 4.294967296e9).cast_vec(dtypes.uint64) # extract 96 relevant bits of 2/pi based on magnitude of argument - i = shr(e.cast(dtypes.uint64), 5) - e = e.cast(dtypes.int32) & 31 + i = shr(e.cast_vec(dtypes.uint64), 5) + e = e.cast_vec(dtypes.int32) & 31 offset = 32 - e def _take(an:UOp, offset:int, count:int=0) -> UOp: @@ -91,8 +89,8 @@ def payne_hanek_reduction(d:UOp) -> tuple[UOp, UOp]: if count+offset < len(two_over_pi_f) - 1: an = i.ne(count).where(_take(an, offset, count=count+1), an.const_like(two_over_pi_f[count+offset])) return an - def _shl_lazy(x:UOp, y:UOp): return (x.cast(dtypes.uint64) * pow2if(y, d.dtype).cast(dtypes.uint64)).cast(dtypes.uint32) - def _shr_lazy(x:UOp, y:UOp): return (x.cast(dtypes.uint64) // pow2if(y, d.dtype).cast(dtypes.uint64)).cast(dtypes.uint32) + def _shl_lazy(x, y): return (x.cast_vec(dtypes.uint64) * pow2if(y, d.dtype).cast_vec(dtypes.uint64)).cast_vec(dtypes.uint32) + def _shr_lazy(x, y): return (x.cast_vec(dtypes.uint64) // pow2if(y, d.dtype).cast_vec(dtypes.uint64)).cast_vec(dtypes.uint32) a = [_take(UOp.const(dtypes.uint32.vec(d.dtype.count), 0), i) for i in range(4)] # (two_over_pi_f[Int(i) + n] << e) | (two_over_pi_f[Int(i) + n+1] >> (nbits - e)) @@ -101,12 +99,12 @@ def payne_hanek_reduction(d:UOp) -> tuple[UOp, UOp]: mi = _shl_lazy(a[1], e) | _shr_lazy(a[2], offset) lo = _shl_lazy(a[2], e) | _shr_lazy(a[3], offset) - def _hp_mul(x:UOp, y:UOp) -> UOp: return x.cast(dtypes.uint64) * y.cast(dtypes.uint64) + def _hp_mul(x:UOp, y:UOp) -> UOp: return x.cast_vec(dtypes.uint64) * y.cast_vec(dtypes.uint64) # compute x * 2/pi p = shl(_hp_mul(ia, hi), 32) + _hp_mul(ia, mi) + shr(_hp_mul(ia, lo), 32) # round quotient to nearest - q = shr(p, 62).cast(dtypes.int32) + q = shr(p, 62).cast_vec(dtypes.int32) p = p & 0x3fffffffffffffff r = (p.cast(intermediate_dtype) * (3.4061215800865545e-19)).cast(d.dtype) @@ -133,7 +131,7 @@ def cody_waite_reduction(d:UOp) -> tuple[UOp, UOp]: d = (qdh + q) * -PI_D + d elif x.dtype.scalar() == dtypes.float16: # [FIXME] when reducing `d`, FP16 needs FP32 precision to achieve 1.0 ULP precision. - d = _reduce_d(x.cast(dtypes.float32), q.cast(dtypes.float32)).cast(dtypes.float16) + d = _reduce_d(x.cast_vec(dtypes.float32), q.cast_vec(dtypes.float32)).cast_vec(dtypes.float16) else: # https://github.com/shibatch/sleef/blob/4e08851f59fc2b545f9c393c6a23dfd311a26308/src/libm/sleefsp.c#L464-L503 d = q * -3.1414794921875 + x @@ -143,9 +141,9 @@ def cody_waite_reduction(d:UOp) -> tuple[UOp, UOp]: return d m_1_pi = 0.318309886183790671537767526745028724 - qdh = (d * (m_1_pi / 2.0**24)).cast(dtypes.int64).cast(d.dtype) * (2.0**24) + qdh = (d * (m_1_pi / 2.0**24)).cast_vec(dtypes.int64).cast(d.dtype) * (2.0**24) quadrant = rintk(d * m_1_pi -qdh) if d.dtype.base.scalar() == dtypes.float64 else rintk(d * m_1_pi) - return _reduce_d(d, quadrant.cast(d.dtype)), quadrant.cast(dtypes.int32) + return _reduce_d(d, quadrant.cast(d.dtype)), quadrant.cast_vec(dtypes.int32) # *** approximate sine on small angle. *** def trig_poly(d:UOp, coeff32, coeff64): return d * (polyN(d*d, coeff64) if d.dtype.scalar() == dtypes.float64 else polyN(d*d, coeff32)) @@ -174,7 +172,7 @@ def xsin(d:UOp, fast:bool=False, switch_over:float=30.0) -> UOp: - fast=True assumes x <= switch_over. - switch_over is the threshold for switching to payne_hanek_reduction. """ - assert d.dtype.scalar() in TRANSCENDENTAL_DTYPES + assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES # mask +-inf/nan as zero x = _lazy_map_numbers(d, d.const_like(0.0), d.const_like(0.0), d.const_like(0.0), d) # x_sign = sign(x) @@ -196,7 +194,7 @@ def xexp2(d:UOp) -> UOp: Implements a 1.0 ULP approximation for Ops.EXP2 - Paper: https://arxiv.org/pdf/2001.09258 """ - assert d.dtype.scalar() in TRANSCENDENTAL_DTYPES + assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES # mask +=inf/nan as zero. x = _lazy_map_numbers(d, d.const_like(0.0), d.const_like(0.0), d.const_like(0.0), d) q = rintk(x) @@ -222,9 +220,9 @@ def xlog2(d:UOp) -> UOp: Implements a 1.0 ULP approximation for Ops.LOG2 Paper: https://arxiv.org/pdf/2001.09258 5.5 """ - assert d.dtype.scalar() in TRANSCENDENTAL_DTYPES + assert d.dtype.scalar() in TRANSCENDENTAL_SUPPORTED_DTYPES # TODO: float16 denormal need float32 to achieve precision - if d.dtype.scalar() == dtypes.float16: return xlog2(d.cast(dtypes.float32)).cast(dtypes.float16) + if d.dtype.scalar() == dtypes.float16: return xlog2(d.cast_vec(dtypes.float32)).cast_vec(dtypes.float16) FLT_MIN = d.const_like(1e-6 if d.dtype.scalar() == dtypes.float16 else 1e-4) is_denormal = d UOp: # start with b ** e = exp2(e * log2(b)) ret = (base < 0).where(-base, base).log2().mul(exponent).exp2() # negative base adjustment: nan for non-integer exponent and -1 for odd exponent - non_int = exponent != exponent.cast(dtypes.int32).cast(exponent.dtype) + non_int = exponent != exponent.cast_vec(dtypes.int32).cast(exponent.dtype) adj = non_int.where(ret.const_like(math.nan), - (exponent < 0).where(-exponent, exponent).cast(dtypes.int32).mod(2).cast(dtypes.bool).where(ret.const_like(-1), ret.const_like(1))) + (exponent < 0).where(-exponent, exponent).cast_vec(dtypes.int32).mod(2).cast_vec(dtypes.bool).where(ret.const_like(-1), ret.const_like(1))) # fix 0 ** 0 = 1 return (base.eq(0) & exponent.eq(0)).where(ret.const_like(1), ret * (base < 0).where(adj, ret.const_like(1))) - -# *** integer division *** - -@functools.lru_cache(None) -def magicgu(vmax:int, d:int) -> tuple[int,int]: - # calculate m,s such that x//d == (x*m) >> s for all 0 <= x <= vmax, d>0; adapted from Hacker's Delight, Chapter 10 - nc = (vmax+1)//(d) * d - 1 - nbits = vmax.bit_length() - for s in range(0, 2*nbits + 1): - if 2**s > nc*(d - 1 - (2**s - 1) % d): - m = (2**s + d - 1 - (2**s - 1) % d)//d - return m, s - assert False - -def fast_idiv(device: str, x: UOp, d: int, dont_cast=False) -> UOp|None: - # If d is a power of two this is not valid for signed ints! - is_unsigned = True if x.vmin>=0 or x.dtype in dtypes.uints else False - assert d>0, "Sign should have been taken out of divisor" - vmin,vmax = max(x.vmin, x.dtype.min), min(x.vmax, x.dtype.max) - m,s = magicgu(max(vmax, abs(vmin)), d) - if m*vmin >= dtypes.min(x.dtype) and m*vmax <= dtypes.max(x.dtype): - return ((x*m) >> s) if is_unsigned else ((x*m) >> s) + (x<0).where(x.ufix(1), 0) - # before we try casting to a larger dtype (slow), we see if there are powers of two in d we can shift to make x smaller - if (largest_factor_of_two_in_d := (d & -d)) > 1: - if (ret:=fast_idiv(device, x//largest_factor_of_two_in_d, d//largest_factor_of_two_in_d, dont_cast=True)) is not None: return ret - if dont_cast: return None - # promo_lattice needs to return an unsigned type if the type is unsigned - if dtypes.is_int(next_dtype := promo_lattice[x.dtype][-1]) and is_dtype_supported(next_dtype, None if device=='' else device): - if m*vmin >= dtypes.min(next_dtype) and m*vmax <= dtypes.max(next_dtype): - return ((x.cast(next_dtype)*m) >> s).cast(x.dtype) if is_unsigned else ((x.cast(next_dtype)*m) >> s).cast(x.dtype) + (x<0).where(x.ufix(1), 0) - return None - -# ***** threefry ***** - -def threefry2x32(x: UOp, key: UOp): - # split x and key from uint64 to two uint32 - x0, x1 = (x & 0xffffffff).cast(dtypes.uint32), ((x // 2**32) & 0xffffffff).cast(dtypes.uint32) - key0, key1 = (key & 0xffffffff).cast(dtypes.uint32), ((key // 2**32) & 0xffffffff).cast(dtypes.uint32) - - rotations = [[13, 15, 26, 6], [17, 29, 16, 24]] - ks = [key1, key0 ^ key1 ^ 0x1BD11BDA, key0] - xr:list[UOp] = [x0 + ks[-1], x1 + ks[0]] - for i in range(5): - for r in rotations[i % 2]: xr[0], xr[1] = (x0 := xr[0] + xr[1]), x0 ^ ((xr[1] * 2**r) + (xr[1] // 2**(32 - r))) - xr = [(xr[0] + ks[i % 3]), (xr[1] + ks[(i + 1) % 3] + i + 1)] - - return xr[1].cast(dtypes.uint64) * 2**32 | xr[0].cast(dtypes.uint64) - -# ***** decomposition patterns ***** - -powers_of_two = {2**i:i for i in range(64)} -@functools.cache -def get_late_rewrite_patterns(ops:tuple[Ops, ...], force_transcendental=False): - pat: list[tuple[UPat, Callable]] = [] - for op,f in ((Ops.EXP2, xexp2), (Ops.LOG2, xlog2), (Ops.SIN, xsin)): - if op not in ops or force_transcendental: - pat += [(UPat(op, dtype=TRANSCENDENTAL_DTYPES, src=(UPat.var("d"),)), f), - (UPat(op, dtype=tuple(dt for dt in dtypes.floats if dt not in TRANSCENDENTAL_DTYPES), src=(UPat.var("d"),), name="x"), - lambda x,d: d.cast(dtypes.float32).alu(x.op).cast(x.dtype))] - # no real hardware supports THREEFRY, but NullRenderer does - if Ops.THREEFRY not in ops: pat.append((UPat(Ops.THREEFRY, dtype=dtypes.uint64, src=(UPat.var("x"), UPat.var("key"))), threefry2x32)) - # MAX can be rewritten as CMPLT + WHERE (max function is annoying on many cstyle backends) - if Ops.MAX not in ops and Ops.CMPLT in ops: pat.append((UPat(Ops.MAX, name="m"), lambda m: (m.src[0] < m.src[1]).where(m.src[1], m.src[0]))) - # rewrite SQRT to xpow 0.5 - if Ops.SQRT not in ops: pat.append((UPat(Ops.SQRT, src=UPat.var("d")), lambda d: xpow(d, d.const_like(0.5)))) - # rewrite MOD to AND (which should always be supported, but not for generic in tests): x % (2**y) -> x & (2**y-1) - if Ops.AND in ops: pat += [(UPat.var("x", dtypes.ints)%UPat.cvar("c"), lambda x,c: x & (c.arg-1) if c.arg in powers_of_two else None)] - if Ops.OR in ops: pat += [(UPat.var("x", dtypes.bool).logical_not()&UPat.var("y", dtypes.bool).logical_not(), - lambda x,y: (x | y).logical_not())] - # rewrite MUL/IDIV to SHL+SHR: x*(2**y) -> shl(x,y) and x//(2**y) -> shr(x,y) - if Ops.SHL in ops: pat += [(UPat.var("x", dtypes.ints)*UPat.cvar("c"), lambda c,x: x << v if (v:=powers_of_two.get(c.arg, 0)) else None)] - if Ops.SHR in ops: - # no reason to check x<0 for uints - pat += [(UPat.var("x", dtypes.uints)//UPat.cvar("c"), lambda x,c: x >> v if (v:=powers_of_two.get(c.arg, 0)) else None)] - pat += [(UPat.var("x", dtypes.ints)//UPat.cvar("c"), lambda x,c: (x+(l.const_like(l.vmin) if (l:=(x<0)).vmin==l.vmax else l).where( - c-1, 0)) >> v if (v:=powers_of_two.get(c.arg, 0)) else None)] # (x+(x<0).where(c-1, 0)) >> v - if not DISABLE_FAST_IDIV: - pat += [(UPat.var("x", dtypes.ints)//UPat.cvar("d"), lambda ctx, x, d: fast_idiv(ctx, x, d.arg))] - pat += [(UPat.var("x", dtypes.ints)%UPat.var("d"), lambda x, d: x-d*(x//d))] - if Ops.NEG in ops: - pat += [(UPat.var('x')*-1, lambda x: x.alu(Ops.NEG))] - if Ops.SUB in ops: pat += [(UPat.var('x')+UPat.var('y').alu(Ops.NEG), lambda x,y: x.alu(Ops.SUB, y))] - if Ops.CMPLT in ops: - # These are late rewrites because simplex expects equalities to be a certain format - pat += [ - ((UPat.var("x", dtypes.sints) < UPat.cvar("c", dtypes.sints)).logical_not(), lambda x,c: c-1 x==c - ] - if Ops.CMPEQ in ops: pat += [(UPat.var('x').ne(UPat.var('y')).logical_not(), lambda x,y: x.alu(Ops.CMPEQ, y))] - if Ops.MULACC in ops: pat += [(UPat.var('a')*UPat.var('b')+UPat.var('c'), lambda a,b,c: a.alu(Ops.MULACC, b, c))] - # some backends emit FDIV for RECIP, in that case: a*(1/b) -> a/b - if Ops.FDIV in ops: - pat += [(UPat.var("x").reciprocal(), lambda x: x.const_like(1).alu(Ops.FDIV, x))] - pat += [(UPat.var("a", dtypes.floats) * UPat.const(dtypes.floats, 1).alu(Ops.FDIV, UPat.var("b")), lambda a,b: a.alu(Ops.FDIV, b))] - return PatternMatcher(pat) diff --git a/tinygrad_repo/tinygrad/uop/upat.py b/tinygrad_repo/tinygrad/uop/upat.py index 5c5f221d3..090de2135 100644 --- a/tinygrad_repo/tinygrad/uop/upat.py +++ b/tinygrad_repo/tinygrad/uop/upat.py @@ -21,7 +21,7 @@ def _get_clause(self:UPat, base:UOp, depth=0) -> UOp: else: and_clause.append(UOp(Ops.CUSTOM, src=(base, UOp(Ops.BIND, arg=self.arg)), arg="{0}.arg == {1}")) if self.strict_length or self.required_len > 0: and_clause.append(UOp(Ops.CUSTOM, src=(base,), arg=("len({0}.src)"+(" == " if self.strict_length else " >= ")+str(self.required_len)))) - if self.name is not None: and_clause.append(UOp(Ops.STORE, src=(UOp(Ops.DEFINE_VAR, arg=self.name), base))) + if self.name is not None: and_clause.append(UOp(Ops.ASSIGN, src=(UOp(Ops.DEFINE_VAR, arg=self.name), base))) if self.dtype is not None: if len(self.dtype) > 1: and_clause.append(UOp(Ops.CUSTOM, src=(base, UOp(Ops.BIND, arg=tuple(self.dtype))), arg="({0}.dtype in {1} or {0}.dtype._scalar in {1})")) @@ -66,26 +66,26 @@ def do_process_and(a:UOp) -> UOp|None: or_clause = [UOp(Ops.OR, src=tuple([UOp(Ops.AND, src=x) for x in itertools.product(*[x.src for x in or_clause])]))] found = True - # handle stores - stores, new_src = partition(new_src, lambda x: x.op is Ops.STORE) - if len(stores): + # handle assigns + assigns, new_src = partition(new_src, lambda x: x.op is Ops.ASSIGN) + if len(assigns): if len(or_clause): - # push stores to the top if we have an or_clause + # push assigns to the top if we have an or_clause assert len(or_clause) == 1 and all(x.op is Ops.AND for x in or_clause[0].src) - or_clause = [UOp(Ops.OR, src=tuple([x.replace(src=x.src+tuple(stores)) for x in or_clause[0].src]))] + or_clause = [UOp(Ops.OR, src=tuple([x.replace(src=x.src+tuple(assigns)) for x in or_clause[0].src]))] found = True else: - # check for duplicate stores - dict_stores: dict[UOp, UOp] = {} - for a in stores: - if a.src[0] in dict_stores: - # duplicate store is a compare - new_src.append(UOp(Ops.CMPNE, src=(dict_stores[a.src[0]], a.src[1]))) + # check for duplicate assigns + dict_assigns: dict[UOp, UOp] = {} + for a in assigns: + if a.src[0] in dict_assigns: + # duplicate assign is a compare + new_src.append(UOp(Ops.CMPNE, src=(dict_assigns[a.src[0]], a.src[1]))) found = True else: - dict_stores[a.src[0]] = a.src[1] - # put the stores back - for k,v in dict_stores.items(): new_src.append(UOp(Ops.STORE, src=(k,v))) + dict_assigns[a.src[0]] = a.src[1] + # put the assigns back + for k,v in dict_assigns.items(): new_src.append(UOp(Ops.ASSIGN, src=(k,v))) # reassemble, if there's any deduping to do, do it if len(dretand:=dedup(new_src+or_clause)) != len(new_src)+len(or_clause): found = True @@ -115,25 +115,25 @@ pm_renderer = PatternMatcher([ def _final_render(x:UOp, has_ctx:bool, depth=1) -> list[str]: assert x.op is Ops.AND - and_pieces, store_pieces = [], [] + and_pieces, assign_pieces = [], [] or_pieces: list[str] = [] for s in x.src: if s.op is Ops.OR: assert len(or_pieces) == 0 and len(s.src) >= 1 for ss in s.src: or_pieces.extend(_final_render(ss, has_ctx, depth+1)) - elif s.op is Ops.STORE: + elif s.op is Ops.ASSIGN: assert s.src[0].op is Ops.DEFINE_VAR and s.src[1].op is Ops.NOOP - store_pieces.append(f"{s.src[0].arg}={s.src[1].arg}") + assign_pieces.append(f"{s.src[0].arg}={s.src[1].arg}") elif s.op is Ops.NOOP: and_pieces.append(s.arg) else: raise UPatCompileError(f"can't compile this {s}") # if we have an or, render it if len(or_pieces): - assert len(store_pieces) == 0 + assert len(assign_pieces) == 0 and_clause = ' and '.join(and_pieces) return [f"{' '*depth}if {and_clause if len(and_clause) else 'True'}:"] + or_pieces # if we don't, this is a final return - store_clause = ', '.join((["ctx=ctx"] if has_ctx else [])+store_pieces) - and_clause = ' and '.join(and_pieces + [f"(_ret:=_fxn({store_clause})) is not None"]) + assign_clause = ', '.join((["ctx=ctx"] if has_ctx else [])+assign_pieces) + and_clause = ' and '.join(and_pieces + [f"(_ret:=_fxn({assign_clause})) is not None"]) return [f"{' '*depth}if {and_clause}: return _ret"] def _get_code(self:UPat, has_ctx:bool): diff --git a/tinygrad_repo/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/x86asm.min.js b/tinygrad_repo/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/x86asm.min.js deleted file mode 100644 index 03f594459..000000000 --- a/tinygrad_repo/tinygrad/viz/assets/cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/x86asm.min.js +++ /dev/null @@ -1,19 +0,0 @@ -/*! `x86asm` grammar compiled for Highlight.js 11.10.0 */ -(()=>{var s=(()=>{"use strict";return s=>({name:"Intel x86 Assembly", -case_insensitive:!0,keywords:{$pattern:"[.%]?"+s.IDENT_RE, -keyword:"lock rep repe repz repne repnz xaquire xrelease bnd nobnd aaa aad aam aas adc add and arpl bb0_reset bb1_reset bound bsf bsr bswap bt btc btr bts call cbw cdq cdqe clc cld cli clts cmc cmp cmpsb cmpsd cmpsq cmpsw cmpxchg cmpxchg486 cmpxchg8b cmpxchg16b cpuid cpu_read cpu_write cqo cwd cwde daa das dec div dmint emms enter equ f2xm1 fabs fadd faddp fbld fbstp fchs fclex fcmovb fcmovbe fcmove fcmovnb fcmovnbe fcmovne fcmovnu fcmovu fcom fcomi fcomip fcomp fcompp fcos fdecstp fdisi fdiv fdivp fdivr fdivrp femms feni ffree ffreep fiadd ficom ficomp fidiv fidivr fild fimul fincstp finit fist fistp fisttp fisub fisubr fld fld1 fldcw fldenv fldl2e fldl2t fldlg2 fldln2 fldpi fldz fmul fmulp fnclex fndisi fneni fninit fnop fnsave fnstcw fnstenv fnstsw fpatan fprem fprem1 fptan frndint frstor fsave fscale fsetpm fsin fsincos fsqrt fst fstcw fstenv fstp fstsw fsub fsubp fsubr fsubrp ftst fucom fucomi fucomip fucomp fucompp fxam fxch fxtract fyl2x fyl2xp1 hlt ibts icebp idiv imul in inc incbin insb insd insw int int01 int1 int03 int3 into invd invpcid invlpg invlpga iret iretd iretq iretw jcxz jecxz jrcxz jmp jmpe lahf lar lds lea leave les lfence lfs lgdt lgs lidt lldt lmsw loadall loadall286 lodsb lodsd lodsq lodsw loop loope loopne loopnz loopz lsl lss ltr mfence monitor mov movd movq movsb movsd movsq movsw movsx movsxd movzx mul mwait neg nop not or out outsb outsd outsw packssdw packsswb packuswb paddb paddd paddsb paddsiw paddsw paddusb paddusw paddw pand pandn pause paveb pavgusb pcmpeqb pcmpeqd pcmpeqw pcmpgtb pcmpgtd pcmpgtw pdistib pf2id pfacc pfadd pfcmpeq pfcmpge pfcmpgt pfmax pfmin pfmul pfrcp pfrcpit1 pfrcpit2 pfrsqit1 pfrsqrt pfsub pfsubr pi2fd pmachriw pmaddwd pmagw pmulhriw pmulhrwa pmulhrwc pmulhw pmullw pmvgezb pmvlzb pmvnzb pmvzb pop popa popad popaw popf popfd popfq popfw por prefetch prefetchw pslld psllq psllw psrad psraw psrld psrlq psrlw psubb psubd psubsb psubsiw psubsw psubusb psubusw psubw punpckhbw punpckhdq punpckhwd punpcklbw punpckldq punpcklwd push pusha pushad pushaw pushf pushfd pushfq pushfw pxor rcl rcr rdshr rdmsr rdpmc rdtsc rdtscp ret retf retn rol ror rdm rsdc rsldt rsm rsts sahf sal salc sar sbb scasb scasd scasq scasw sfence sgdt shl shld shr shrd sidt sldt skinit smi smint smintold smsw stc std sti stosb stosd stosq stosw str sub svdc svldt svts swapgs syscall sysenter sysexit sysret test ud0 ud1 ud2b ud2 ud2a umov verr verw fwait wbinvd wrshr wrmsr xadd xbts xchg xlatb xlat xor cmove cmovz cmovne cmovnz cmova cmovnbe cmovae cmovnb cmovb cmovnae cmovbe cmovna cmovg cmovnle cmovge cmovnl cmovl cmovnge cmovle cmovng cmovc cmovnc cmovo cmovno cmovs cmovns cmovp cmovpe cmovnp cmovpo je jz jne jnz ja jnbe jae jnb jb jnae jbe jna jg jnle jge jnl jl jnge jle jng jc jnc jo jno js jns jpo jnp jpe jp sete setz setne setnz seta setnbe setae setnb setnc setb setnae setcset setbe setna setg setnle setge setnl setl setnge setle setng sets setns seto setno setpe setp setpo setnp addps addss andnps andps cmpeqps cmpeqss cmpleps cmpless cmpltps cmpltss cmpneqps cmpneqss cmpnleps cmpnless cmpnltps cmpnltss cmpordps cmpordss cmpunordps cmpunordss cmpps cmpss comiss cvtpi2ps cvtps2pi cvtsi2ss cvtss2si cvttps2pi cvttss2si divps divss ldmxcsr maxps maxss minps minss movaps movhps movlhps movlps movhlps movmskps movntps movss movups mulps mulss orps rcpps rcpss rsqrtps rsqrtss shufps sqrtps sqrtss stmxcsr subps subss ucomiss unpckhps unpcklps xorps fxrstor fxrstor64 fxsave fxsave64 xgetbv xsetbv xsave xsave64 xsaveopt xsaveopt64 xrstor xrstor64 prefetchnta prefetcht0 prefetcht1 prefetcht2 maskmovq movntq pavgb pavgw pextrw pinsrw pmaxsw pmaxub pminsw pminub pmovmskb pmulhuw psadbw pshufw pf2iw pfnacc pfpnacc pi2fw pswapd maskmovdqu clflush movntdq movnti movntpd movdqa movdqu movdq2q movq2dq paddq pmuludq pshufd pshufhw pshuflw pslldq psrldq psubq punpckhqdq punpcklqdq addpd addsd andnpd andpd cmpeqpd cmpeqsd cmplepd cmplesd cmpltpd cmpltsd cmpneqpd cmpneqsd cmpnlepd cmpnlesd cmpnltpd cmpnltsd cmpordpd cmpordsd cmpunordpd cmpunordsd cmppd comisd cvtdq2pd cvtdq2ps cvtpd2dq cvtpd2pi cvtpd2ps cvtpi2pd cvtps2dq cvtps2pd cvtsd2si cvtsd2ss cvtsi2sd cvtss2sd cvttpd2pi cvttpd2dq cvttps2dq cvttsd2si divpd divsd maxpd maxsd minpd minsd movapd movhpd movlpd movmskpd movupd mulpd mulsd orpd shufpd sqrtpd sqrtsd subpd subsd ucomisd unpckhpd unpcklpd xorpd addsubpd addsubps haddpd haddps hsubpd hsubps lddqu movddup movshdup movsldup clgi stgi vmcall vmclear vmfunc vmlaunch vmload vmmcall vmptrld vmptrst vmread vmresume vmrun vmsave vmwrite vmxoff vmxon invept invvpid pabsb pabsw pabsd palignr phaddw phaddd phaddsw phsubw phsubd phsubsw pmaddubsw pmulhrsw pshufb psignb psignw psignd extrq insertq movntsd movntss lzcnt blendpd blendps blendvpd blendvps dppd dpps extractps insertps movntdqa mpsadbw packusdw pblendvb pblendw pcmpeqq pextrb pextrd pextrq phminposuw pinsrb pinsrd pinsrq pmaxsb pmaxsd pmaxud pmaxuw pminsb pminsd pminud pminuw pmovsxbw pmovsxbd pmovsxbq pmovsxwd pmovsxwq pmovsxdq pmovzxbw pmovzxbd pmovzxbq pmovzxwd pmovzxwq pmovzxdq pmuldq pmulld ptest roundpd roundps roundsd roundss crc32 pcmpestri pcmpestrm pcmpistri pcmpistrm pcmpgtq popcnt getsec pfrcpv pfrsqrtv movbe aesenc aesenclast aesdec aesdeclast aesimc aeskeygenassist vaesenc vaesenclast vaesdec vaesdeclast vaesimc vaeskeygenassist vaddpd vaddps vaddsd vaddss vaddsubpd vaddsubps vandpd vandps vandnpd vandnps vblendpd vblendps vblendvpd vblendvps vbroadcastss vbroadcastsd vbroadcastf128 vcmpeq_ospd vcmpeqpd vcmplt_ospd vcmpltpd vcmple_ospd vcmplepd vcmpunord_qpd vcmpunordpd vcmpneq_uqpd vcmpneqpd vcmpnlt_uspd vcmpnltpd vcmpnle_uspd vcmpnlepd vcmpord_qpd vcmpordpd vcmpeq_uqpd vcmpnge_uspd vcmpngepd vcmpngt_uspd vcmpngtpd vcmpfalse_oqpd vcmpfalsepd vcmpneq_oqpd vcmpge_ospd vcmpgepd vcmpgt_ospd vcmpgtpd vcmptrue_uqpd vcmptruepd vcmplt_oqpd vcmple_oqpd vcmpunord_spd vcmpneq_uspd vcmpnlt_uqpd vcmpnle_uqpd vcmpord_spd vcmpeq_uspd vcmpnge_uqpd vcmpngt_uqpd vcmpfalse_ospd vcmpneq_ospd vcmpge_oqpd vcmpgt_oqpd vcmptrue_uspd vcmppd vcmpeq_osps vcmpeqps vcmplt_osps vcmpltps vcmple_osps vcmpleps vcmpunord_qps vcmpunordps vcmpneq_uqps vcmpneqps vcmpnlt_usps vcmpnltps vcmpnle_usps vcmpnleps vcmpord_qps vcmpordps vcmpeq_uqps vcmpnge_usps vcmpngeps vcmpngt_usps vcmpngtps vcmpfalse_oqps vcmpfalseps vcmpneq_oqps vcmpge_osps vcmpgeps vcmpgt_osps vcmpgtps vcmptrue_uqps vcmptrueps vcmplt_oqps vcmple_oqps vcmpunord_sps vcmpneq_usps vcmpnlt_uqps vcmpnle_uqps vcmpord_sps vcmpeq_usps vcmpnge_uqps vcmpngt_uqps vcmpfalse_osps vcmpneq_osps vcmpge_oqps vcmpgt_oqps vcmptrue_usps vcmpps vcmpeq_ossd vcmpeqsd vcmplt_ossd vcmpltsd vcmple_ossd vcmplesd vcmpunord_qsd vcmpunordsd vcmpneq_uqsd vcmpneqsd vcmpnlt_ussd vcmpnltsd vcmpnle_ussd vcmpnlesd vcmpord_qsd vcmpordsd vcmpeq_uqsd vcmpnge_ussd vcmpngesd vcmpngt_ussd vcmpngtsd vcmpfalse_oqsd vcmpfalsesd vcmpneq_oqsd vcmpge_ossd vcmpgesd vcmpgt_ossd vcmpgtsd vcmptrue_uqsd vcmptruesd vcmplt_oqsd vcmple_oqsd vcmpunord_ssd vcmpneq_ussd vcmpnlt_uqsd vcmpnle_uqsd vcmpord_ssd vcmpeq_ussd vcmpnge_uqsd vcmpngt_uqsd vcmpfalse_ossd vcmpneq_ossd vcmpge_oqsd vcmpgt_oqsd vcmptrue_ussd vcmpsd vcmpeq_osss vcmpeqss vcmplt_osss vcmpltss vcmple_osss vcmpless vcmpunord_qss vcmpunordss vcmpneq_uqss vcmpneqss vcmpnlt_usss vcmpnltss vcmpnle_usss vcmpnless vcmpord_qss vcmpordss vcmpeq_uqss vcmpnge_usss vcmpngess vcmpngt_usss vcmpngtss vcmpfalse_oqss vcmpfalsess vcmpneq_oqss vcmpge_osss vcmpgess vcmpgt_osss vcmpgtss vcmptrue_uqss vcmptruess vcmplt_oqss vcmple_oqss vcmpunord_sss vcmpneq_usss vcmpnlt_uqss vcmpnle_uqss vcmpord_sss vcmpeq_usss vcmpnge_uqss vcmpngt_uqss vcmpfalse_osss vcmpneq_osss vcmpge_oqss vcmpgt_oqss vcmptrue_usss vcmpss vcomisd vcomiss vcvtdq2pd vcvtdq2ps vcvtpd2dq vcvtpd2ps vcvtps2dq vcvtps2pd vcvtsd2si vcvtsd2ss vcvtsi2sd vcvtsi2ss vcvtss2sd vcvtss2si vcvttpd2dq vcvttps2dq vcvttsd2si vcvttss2si vdivpd vdivps vdivsd vdivss vdppd vdpps vextractf128 vextractps vhaddpd vhaddps vhsubpd vhsubps vinsertf128 vinsertps vlddqu vldqqu vldmxcsr vmaskmovdqu vmaskmovps vmaskmovpd vmaxpd vmaxps vmaxsd vmaxss vminpd vminps vminsd vminss vmovapd vmovaps vmovd vmovq vmovddup vmovdqa vmovqqa vmovdqu vmovqqu vmovhlps vmovhpd vmovhps vmovlhps vmovlpd vmovlps vmovmskpd vmovmskps vmovntdq vmovntqq vmovntdqa vmovntpd vmovntps vmovsd vmovshdup vmovsldup vmovss vmovupd vmovups vmpsadbw vmulpd vmulps vmulsd vmulss vorpd vorps vpabsb vpabsw vpabsd vpacksswb vpackssdw vpackuswb vpackusdw vpaddb vpaddw vpaddd vpaddq vpaddsb vpaddsw vpaddusb vpaddusw vpalignr vpand vpandn vpavgb vpavgw vpblendvb vpblendw vpcmpestri vpcmpestrm vpcmpistri vpcmpistrm vpcmpeqb vpcmpeqw vpcmpeqd vpcmpeqq vpcmpgtb vpcmpgtw vpcmpgtd vpcmpgtq vpermilpd vpermilps vperm2f128 vpextrb vpextrw vpextrd vpextrq vphaddw vphaddd vphaddsw vphminposuw vphsubw vphsubd vphsubsw vpinsrb vpinsrw vpinsrd vpinsrq vpmaddwd vpmaddubsw vpmaxsb vpmaxsw vpmaxsd vpmaxub vpmaxuw vpmaxud vpminsb vpminsw vpminsd vpminub vpminuw vpminud vpmovmskb vpmovsxbw vpmovsxbd vpmovsxbq vpmovsxwd vpmovsxwq vpmovsxdq vpmovzxbw vpmovzxbd vpmovzxbq vpmovzxwd vpmovzxwq vpmovzxdq vpmulhuw vpmulhrsw vpmulhw vpmullw vpmulld vpmuludq vpmuldq vpor vpsadbw vpshufb vpshufd vpshufhw vpshuflw vpsignb vpsignw vpsignd vpslldq vpsrldq vpsllw vpslld vpsllq vpsraw vpsrad vpsrlw vpsrld vpsrlq vptest vpsubb vpsubw vpsubd vpsubq vpsubsb vpsubsw vpsubusb vpsubusw vpunpckhbw vpunpckhwd vpunpckhdq vpunpckhqdq vpunpcklbw vpunpcklwd vpunpckldq vpunpcklqdq vpxor vrcpps vrcpss vrsqrtps vrsqrtss vroundpd vroundps vroundsd vroundss vshufpd vshufps vsqrtpd vsqrtps vsqrtsd vsqrtss vstmxcsr vsubpd vsubps vsubsd vsubss vtestps vtestpd vucomisd vucomiss vunpckhpd vunpckhps vunpcklpd vunpcklps vxorpd vxorps vzeroall vzeroupper pclmullqlqdq pclmulhqlqdq pclmullqhqdq pclmulhqhqdq pclmulqdq vpclmullqlqdq vpclmulhqlqdq vpclmullqhqdq vpclmulhqhqdq vpclmulqdq vfmadd132ps vfmadd132pd vfmadd312ps vfmadd312pd vfmadd213ps vfmadd213pd vfmadd123ps vfmadd123pd vfmadd231ps vfmadd231pd vfmadd321ps vfmadd321pd vfmaddsub132ps vfmaddsub132pd vfmaddsub312ps vfmaddsub312pd vfmaddsub213ps vfmaddsub213pd vfmaddsub123ps vfmaddsub123pd vfmaddsub231ps vfmaddsub231pd vfmaddsub321ps vfmaddsub321pd vfmsub132ps vfmsub132pd vfmsub312ps vfmsub312pd vfmsub213ps vfmsub213pd vfmsub123ps vfmsub123pd vfmsub231ps vfmsub231pd vfmsub321ps vfmsub321pd vfmsubadd132ps vfmsubadd132pd vfmsubadd312ps vfmsubadd312pd vfmsubadd213ps vfmsubadd213pd vfmsubadd123ps vfmsubadd123pd vfmsubadd231ps vfmsubadd231pd vfmsubadd321ps vfmsubadd321pd vfnmadd132ps vfnmadd132pd vfnmadd312ps vfnmadd312pd vfnmadd213ps vfnmadd213pd vfnmadd123ps vfnmadd123pd vfnmadd231ps vfnmadd231pd vfnmadd321ps vfnmadd321pd vfnmsub132ps vfnmsub132pd vfnmsub312ps vfnmsub312pd vfnmsub213ps vfnmsub213pd vfnmsub123ps vfnmsub123pd vfnmsub231ps vfnmsub231pd vfnmsub321ps vfnmsub321pd vfmadd132ss vfmadd132sd vfmadd312ss vfmadd312sd vfmadd213ss vfmadd213sd vfmadd123ss vfmadd123sd vfmadd231ss vfmadd231sd vfmadd321ss vfmadd321sd vfmsub132ss vfmsub132sd vfmsub312ss vfmsub312sd vfmsub213ss vfmsub213sd vfmsub123ss vfmsub123sd vfmsub231ss vfmsub231sd vfmsub321ss vfmsub321sd vfnmadd132ss vfnmadd132sd vfnmadd312ss vfnmadd312sd vfnmadd213ss vfnmadd213sd vfnmadd123ss vfnmadd123sd vfnmadd231ss vfnmadd231sd vfnmadd321ss vfnmadd321sd vfnmsub132ss vfnmsub132sd vfnmsub312ss vfnmsub312sd vfnmsub213ss vfnmsub213sd vfnmsub123ss vfnmsub123sd vfnmsub231ss vfnmsub231sd vfnmsub321ss vfnmsub321sd rdfsbase rdgsbase rdrand wrfsbase wrgsbase vcvtph2ps vcvtps2ph adcx adox rdseed clac stac xstore xcryptecb xcryptcbc xcryptctr xcryptcfb xcryptofb montmul xsha1 xsha256 llwpcb slwpcb lwpval lwpins vfmaddpd vfmaddps vfmaddsd vfmaddss vfmaddsubpd vfmaddsubps vfmsubaddpd vfmsubaddps vfmsubpd vfmsubps vfmsubsd vfmsubss vfnmaddpd vfnmaddps vfnmaddsd vfnmaddss vfnmsubpd vfnmsubps vfnmsubsd vfnmsubss vfrczpd vfrczps vfrczsd vfrczss vpcmov vpcomb vpcomd vpcomq vpcomub vpcomud vpcomuq vpcomuw vpcomw vphaddbd vphaddbq vphaddbw vphadddq vphaddubd vphaddubq vphaddubw vphaddudq vphadduwd vphadduwq vphaddwd vphaddwq vphsubbw vphsubdq vphsubwd vpmacsdd vpmacsdqh vpmacsdql vpmacssdd vpmacssdqh vpmacssdql vpmacsswd vpmacssww vpmacswd vpmacsww vpmadcsswd vpmadcswd vpperm vprotb vprotd vprotq vprotw vpshab vpshad vpshaq vpshaw vpshlb vpshld vpshlq vpshlw vbroadcasti128 vpblendd vpbroadcastb vpbroadcastw vpbroadcastd vpbroadcastq vpermd vpermpd vpermps vpermq vperm2i128 vextracti128 vinserti128 vpmaskmovd vpmaskmovq vpsllvd vpsllvq vpsravd vpsrlvd vpsrlvq vgatherdpd vgatherqpd vgatherdps vgatherqps vpgatherdd vpgatherqd vpgatherdq vpgatherqq xabort xbegin xend xtest andn bextr blci blcic blsi blsic blcfill blsfill blcmsk blsmsk blsr blcs bzhi mulx pdep pext rorx sarx shlx shrx tzcnt tzmsk t1mskc valignd valignq vblendmpd vblendmps vbroadcastf32x4 vbroadcastf64x4 vbroadcasti32x4 vbroadcasti64x4 vcompresspd vcompressps vcvtpd2udq vcvtps2udq vcvtsd2usi vcvtss2usi vcvttpd2udq vcvttps2udq vcvttsd2usi vcvttss2usi vcvtudq2pd vcvtudq2ps vcvtusi2sd vcvtusi2ss vexpandpd vexpandps vextractf32x4 vextractf64x4 vextracti32x4 vextracti64x4 vfixupimmpd vfixupimmps vfixupimmsd vfixupimmss vgetexppd vgetexpps vgetexpsd vgetexpss vgetmantpd vgetmantps vgetmantsd vgetmantss vinsertf32x4 vinsertf64x4 vinserti32x4 vinserti64x4 vmovdqa32 vmovdqa64 vmovdqu32 vmovdqu64 vpabsq vpandd vpandnd vpandnq vpandq vpblendmd vpblendmq vpcmpltd vpcmpled vpcmpneqd vpcmpnltd vpcmpnled vpcmpd vpcmpltq vpcmpleq vpcmpneqq vpcmpnltq vpcmpnleq vpcmpq vpcmpequd vpcmpltud vpcmpleud vpcmpnequd vpcmpnltud vpcmpnleud vpcmpud vpcmpequq vpcmpltuq vpcmpleuq vpcmpnequq vpcmpnltuq vpcmpnleuq vpcmpuq vpcompressd vpcompressq vpermi2d vpermi2pd vpermi2ps vpermi2q vpermt2d vpermt2pd vpermt2ps vpermt2q vpexpandd vpexpandq vpmaxsq vpmaxuq vpminsq vpminuq vpmovdb vpmovdw vpmovqb vpmovqd vpmovqw vpmovsdb vpmovsdw vpmovsqb vpmovsqd vpmovsqw vpmovusdb vpmovusdw vpmovusqb vpmovusqd vpmovusqw vpord vporq vprold vprolq vprolvd vprolvq vprord vprorq vprorvd vprorvq vpscatterdd vpscatterdq vpscatterqd vpscatterqq vpsraq vpsravq vpternlogd vpternlogq vptestmd vptestmq vptestnmd vptestnmq vpxord vpxorq vrcp14pd vrcp14ps vrcp14sd vrcp14ss vrndscalepd vrndscaleps vrndscalesd vrndscaless vrsqrt14pd vrsqrt14ps vrsqrt14sd vrsqrt14ss vscalefpd vscalefps vscalefsd vscalefss vscatterdpd vscatterdps vscatterqpd vscatterqps vshuff32x4 vshuff64x2 vshufi32x4 vshufi64x2 kandnw kandw kmovw knotw kortestw korw kshiftlw kshiftrw kunpckbw kxnorw kxorw vpbroadcastmb2q vpbroadcastmw2d vpconflictd vpconflictq vplzcntd vplzcntq vexp2pd vexp2ps vrcp28pd vrcp28ps vrcp28sd vrcp28ss vrsqrt28pd vrsqrt28ps vrsqrt28sd vrsqrt28ss vgatherpf0dpd vgatherpf0dps vgatherpf0qpd vgatherpf0qps vgatherpf1dpd vgatherpf1dps vgatherpf1qpd vgatherpf1qps vscatterpf0dpd vscatterpf0dps vscatterpf0qpd vscatterpf0qps vscatterpf1dpd vscatterpf1dps vscatterpf1qpd vscatterpf1qps prefetchwt1 bndmk bndcl bndcu bndcn bndmov bndldx bndstx sha1rnds4 sha1nexte sha1msg1 sha1msg2 sha256rnds2 sha256msg1 sha256msg2 hint_nop0 hint_nop1 hint_nop2 hint_nop3 hint_nop4 hint_nop5 hint_nop6 hint_nop7 hint_nop8 hint_nop9 hint_nop10 hint_nop11 hint_nop12 hint_nop13 hint_nop14 hint_nop15 hint_nop16 hint_nop17 hint_nop18 hint_nop19 hint_nop20 hint_nop21 hint_nop22 hint_nop23 hint_nop24 hint_nop25 hint_nop26 hint_nop27 hint_nop28 hint_nop29 hint_nop30 hint_nop31 hint_nop32 hint_nop33 hint_nop34 hint_nop35 hint_nop36 hint_nop37 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-begin:"\\b(?:[0-9A-Fa-f][0-9A-Fa-f_]*[Hh]|[0-9][0-9_]*[DdTt]?|[0-7][0-7_]*[QqOo]|[0-1][0-1_]*[BbYy])\\b" -},{ -begin:"\\b(?:0[Xx][0-9A-Fa-f_]+|0[DdTt][0-9_]+|0[QqOo][0-7_]+|0[BbYy][0-1_]+)\\b" -}]},s.QUOTE_STRING_MODE,{className:"string",variants:[{begin:"'",end:"[^\\\\]'" -},{begin:"`",end:"[^\\\\]`"}],relevance:0},{className:"symbol",variants:[{ -begin:"^\\s*[A-Za-z._?][A-Za-z0-9_$#@~.?]*(:|\\s+label)"},{ -begin:"^\\s*%%[A-Za-z0-9_$#@~.?]*:"}],relevance:0},{className:"subst", -begin:"%[0-9]+",relevance:0},{className:"subst",begin:"%!S+",relevance:0},{ -className:"meta",begin:/^\s*\.[\w_-]+/}]})})();hljs.registerLanguage("x86asm",s) -})(); \ No newline at end of file diff --git a/tinygrad_repo/tinygrad/viz/fetch_assets.sh b/tinygrad_repo/tinygrad/viz/fetch_assets.sh old mode 100644 new mode 100755 index 8bb6a3cd5..ae4720ce8 --- a/tinygrad_repo/tinygrad/viz/fetch_assets.sh +++ b/tinygrad_repo/tinygrad/viz/fetch_assets.sh @@ -10,6 +10,5 @@ fetch "dagrejs.github.io/project/dagre/latest/dagre.min.js" fetch "cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/styles/default.min.css" fetch "cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/highlight.min.js" fetch "cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/python.min.js" -fetch "cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/x86asm.min.js" fetch "cdnjs.cloudflare.com/ajax/libs/highlight.js/11.10.0/languages/cpp.min.js" fetch "unpkg.com/@highlightjs/cdn-assets@11.10.0/styles/tokyo-night-dark.min.css" diff --git a/tinygrad_repo/tinygrad/viz/index.html b/tinygrad_repo/tinygrad/viz/index.html index 23e61798a..e756199cc 100644 --- a/tinygrad_repo/tinygrad/viz/index.html +++ b/tinygrad_repo/tinygrad/viz/index.html @@ -10,7 +10,6 @@ - @@ -343,27 +226,29 @@ -

-
-
+
+
+ +
+
Rendering new layout...
+ - +
-
diff --git a/tinygrad_repo/tinygrad/viz/js/index.js b/tinygrad_repo/tinygrad/viz/js/index.js index 1ff74def4..4d05d9932 100644 --- a/tinygrad_repo/tinygrad/viz/js/index.js +++ b/tinygrad_repo/tinygrad/viz/js/index.js @@ -1,34 +1,9 @@ -// ** graph helpers +// **** graph renderers const displayGraph = (cls) => { for (const e of document.getElementsByClassName("view")) e.style.display = e.classList.contains(cls) ? "flex" : "none"; } -const darkenHex = (h, p = 0) => - `#${( - c = parseInt(h.slice(1), 16), - f = 1 - p / 100, - ((c >> 16 & 255) * f | 0) << 16 | - ((c >> 8 & 255) * f | 0) << 8 | - ((c & 255) * f | 0) - ).toString(16).padStart(6, '0')}`; - -const ANSI_COLORS = ["#b3b3b3", "#ff6666", "#66b366", "#ffff66", "#6666ff", "#ff66ff", "#66ffff", "#ffffff"]; -const parseColors = (name, defaultColor="#ffffff") => Array.from(name.matchAll(/(?:\u001b\[(\d+)m([\s\S]*?)\u001b\[0m)|([^\u001b]+)/g), - ([_, code, colored_st, st]) => ({ st: colored_st ?? st, color: code != null ? ANSI_COLORS[(parseInt(code)-30+60)%60] : defaultColor })); - -const rect = (s) => (typeof s === "string" ? document.querySelector(s) : s).getBoundingClientRect(); - -let timeout = null; -const updateProgress = ({ show=true }) => { - clearTimeout(timeout); - const msg = document.getElementById("progress-message"); - if (show) { - msg.innerText = "Rendering new graph..."; - timeout = setTimeout(() => { msg.style.display = "block"; }, 2000); - } else msg.style.display = "none"; -} - // ** UOp graph function intersectRect(r1, r2) { @@ -41,15 +16,11 @@ function intersectRect(r1, r2) { return {x:r1.x+dx*scale, y:r1.y+dy*scale}; } -function addTags(root) { - root.selectAll("circle").data(d => [d]).join("circle").attr("r", 5); - root.selectAll("text").data(d => [d]).join("text").text(d => d).attr("dy", "0.35em"); -} +const rect = (s) => (typeof s === "string" ? document.querySelector(s) : s).getBoundingClientRect(); -let [workerUrl, worker] = [null, null]; +let [workerUrl, worker, timeout] = [null, null, null]; async function renderDag(graph, additions, recenter=false) { // start calculating the new layout (non-blocking) - updateProgress({ show:true }); if (worker == null) { const resp = await Promise.all(["/assets/dagrejs.github.io/project/dagre/latest/dagre.min.js","/js/worker.js"].map(u => fetch(u))); workerUrl = URL.createObjectURL(new Blob([(await Promise.all(resp.map((r) => r.text()))).join("\n")], { type: "application/javascript" })); @@ -58,57 +29,43 @@ async function renderDag(graph, additions, recenter=false) { worker.terminate(); worker = new Worker(workerUrl); } + if (timeout != null) clearTimeout(timeout); + const progressMessage = document.querySelector(".progress-message"); + timeout = setTimeout(() => {progressMessage.style.display = "block"}, 2000); worker.postMessage({graph, additions, ctxs}); worker.onmessage = (e) => { displayGraph("graph"); - updateProgress({ show:false }); + progressMessage.style.display = "none"; + clearTimeout(timeout); + d3.select("#bars").html(""); const g = dagre.graphlib.json.read(e.data); // draw nodes const STROKE_WIDTH = 1.4; - d3.select("#graph-svg").on("click", () => d3.selectAll(".highlight").classed("highlight", false)); const nodes = d3.select("#nodes").selectAll("g").data(g.nodes().map(id => g.node(id)), d => d).join("g") - .attr("transform", d => `translate(${d.x},${d.y})`).classed("clickable", d => d.ref != null).on("click", (e,d) => { - if (d.ref != null) return setCtxWithHistory(d.ref); - const parents = g.predecessors(d.id); - if (parents == null) return; - const src = [...parents, d.id]; - nodes.classed("highlight", n => src.includes(n.id)); - d3.select("#edges").selectAll("path.edgePath").classed("highlight", e => src.includes(e.v) && e.w===d.id); - d3.select("#edge-labels").selectAll("g.port").classed("highlight", (_, i, nodes) => { - const [v, w] = nodes[i].id.split("-"); - return src.includes(v) && w===d.id; - }); - e.stopPropagation(); - }); + .attr("transform", d => `translate(${d.x},${d.y})`).classed("clickable", d => d.ref != null) + .on("click", (_,d) => setCtxWithHistory(d.ref)); nodes.selectAll("rect").data(d => [d]).join("rect").attr("width", d => d.width).attr("height", d => d.height).attr("fill", d => d.color) - .attr("x", d => -d.width/2).attr("y", d => -d.height/2).attr("class", d => d.className ?? "node"); + .attr("x", d => -d.width/2).attr("y", d => -d.height/2).attr("style", d => d.style ?? `stroke:#4a4b57; stroke-width:${STROKE_WIDTH}px;`); nodes.selectAll("g.label").data(d => [d]).join("g").attr("class", "label").attr("transform", d => { const x = (d.width-d.padding*2)/2; const y = (d.height-d.padding*2)/2+STROKE_WIDTH; return `translate(-${x}, -${y})`; - }).selectAll("text").data(d => { - const ret = [[]]; - for (const { st, color } of parseColors(d.label, defaultColor="initial")) { - for (const [i, l] of st.split("\n").entries()) { - if (i > 0) ret.push([]); - ret.at(-1).push({ st:l, color }); - } - } - return [ret]; - }).join("text").selectAll("tspan").data(d => d).join("tspan").attr("x", "0").attr("dy", 14).selectAll("tspan").data(d => d).join("tspan") - .attr("fill", d => darkenHex(d.color, 25)).text(d => d.st).attr("xml:space", "preserve"); - addTags(nodes.selectAll("g.tag").data(d => d.tag != null ? [d] : []).join("g").attr("class", "tag") - .attr("transform", d => `translate(${-d.width/2+8}, ${-d.height/2+8})`).datum(e => e.tag)); + }).selectAll("text").data(d => [d.label.split("\n")]).join("text").selectAll("tspan").data(d => d).join("tspan").text(d => d).attr("x", "0") + .attr("dy", 14).attr("xml:space", "preserve"); + const tags = nodes.selectAll("g.tag").data(d => d.tag != null ? [d] : []).join("g").attr("class", "tag") + .attr("transform", d => `translate(${-d.width/2+8}, ${-d.height/2+8})`); + tags.selectAll("circle").data(d => [d]).join("circle"); + tags.selectAll("text").data(d => [d.tag]).join("text").text(d => d).attr("dy", "0.35em"); // draw edges - const line = d3.line().x(d => d.x).y(d => d.y).curve(d3.curveBasis), edges = g.edges(); - d3.select("#edges").selectAll("path.edgePath").data(edges).join("path").attr("class", "edgePath").attr("d", (e) => { + const line = d3.line().x(d => d.x).y(d => d.y).curve(d3.curveBasis); + d3.select("#edges").selectAll("path.edgePath").data(g.edges()).join("path").attr("class", "edgePath").attr("d", (e) => { const edge = g.edge(e); const points = edge.points.slice(1, edge.points.length-1); points.unshift(intersectRect(g.node(e.v), points[0])); points.push(intersectRect(g.node(e.w), points[points.length-1])); return line(points); }).attr("marker-end", "url(#arrowhead)"); - addTags(d3.select("#edge-labels").selectAll("g").data(edges).join("g").attr("transform", (e) => { + const edgeLabels = d3.select("#edge-labels").selectAll("g").data(g.edges().filter(e => g.edge(e).label != null)).join("g").attr("transform", (e) => { // get a point near the end const [p1, p2] = g.edge(e).points.slice(-2); const dx = p2.x-p1.x; @@ -122,12 +79,148 @@ async function renderDag(graph, additions, recenter=false) { const x = p2.x - ux * offset; const y = p2.y - uy * offset; return `translate(${x}, ${y})` - }).attr("class", e => g.edge(e).label.type).attr("id", e => `${e.v}-${e.w}`).datum(e => g.edge(e).label.text)); + }).attr("class", "tag"); + edgeLabels.selectAll("circle").data(e => [g.edge(e).label]).join("circle"); + edgeLabels.selectAll("text").data(e => [g.edge(e).label]).join("text").text(d => d).attr("dy", "0.35em"); if (recenter) document.getElementById("zoom-to-fit-btn").click(); }; } +// ** Memory graph (WIP) + +DTYPE_SIZE = {"bool": 1, "char": 1, "uchar": 1, "short": 2, "ushort": 2, "int": 4, "uint": 4, + "long": 8, "ulong": 8, "half": 2, "bfloat": 2, "float": 4, "double": 8} +function getBuffer(e) { + const [_, size, dtype, num, device] = e.label.split("\n"); + return {nbytes:size*DTYPE_SIZE[dtype.split("dtypes.")[1]], dtype, device:device.split(" ")[1], num:parseInt(num.split(" ")[1])}; +} + +function pluralize(num, name, alt=null) { + return num === 1 ? `${num} ${name}` : `${num} ${alt ?? name+'s'}` +} + +function renderMemoryGraph(graph) { + displayGraph("graph"); + // ** construct alloc/free traces + // we can map reads/writes from the kernel graph + const actions = []; + const children = new Map(); // {buffer: [...assign]} + for (const [k,v] of Object.entries(graph)) { + if (!v.label.startsWith("ASSIGN")) continue; + actions.push({ op: "write", buffer: v.src[0] }); + for (const ks of graph[v.src[1]].src) { + const node = graph[ks]; + const s = node.label.startsWith("ASSIGN") ? node.src[0] : ks; + if (!children.has(s)) children.set(s, []); + children.get(s).push(v); + if (s !== v.src[0]) actions.push({ op: "read", buffer: s }); + } + } + const prealloc = new Set(); + const traces = []; + for (const a of actions) { + // a buffer is allocated immediately before the first write + // TODO: we don't know the buffer is preallocated if there's only an assign in the graph + if (a.op === "write") { + traces.push({ type: "alloc", buffer: a.buffer }); + } + else { + if (traces.find(t => t.buffer === a.buffer && t.type === "alloc") == null) { + prealloc.add(a.buffer); + } + else if (a === actions.findLast(({ buffer }) => buffer === a.buffer)) { + traces.push({type: "free", buffer: a.buffer }); + } + } + } + // ** get coordinates and layout for each buffer + const ret = {}; + let timestep = 0; // x + let memUsed = 0; // y + for (const id of prealloc) { + const buf = getBuffer(graph[id]); + ret[id] = { x: [timestep], y: [memUsed], buf, id }; + memUsed += buf.nbytes; + } + let peak = memUsed; + const liveBufs = [...prealloc]; + for (const t of traces) { + const buf = getBuffer(graph[t.buffer]); + const idx = liveBufs.findLastIndex(b => t.buffer === b); + // alloc + if (idx === -1) { + liveBufs.push(t.buffer); + ret[t.buffer] = { x: [timestep], y: [memUsed], buf, id: t.buffer }; + memUsed += buf.nbytes; + peak = Math.max(memUsed, peak); + timestep += 1; + } // free + else { + memUsed -= buf.nbytes; + timestep += 1; + const removed = ret[liveBufs.splice(idx, 1)[0]]; + removed.x.push(timestep); + removed.y.push(removed.y.at(-1)); + if (idx < liveBufs.length) { + for (let j=idx; j d3.format(".3~s")(d)+"B"; + axesGroup.append("g").call(d3.axisLeft(yscale).tickFormat(nbytes_format)); + axesGroup.append("g").attr("transform", `translate(0, ${yscale.range()[0]})`).call(d3.axisBottom(xscale).tickFormat(() => "")); + const polygonGroup = render.append("g").attr("id", "polygons"); + const colors = ["7aa2f7", "ff9e64", "f7768e", "2ac3de", "7dcfff", "1abc9c", "9ece6a", "e0af68", "bb9af7", "9d7cd8", "ff007c"]; + const polygons = polygonGroup.selectAll("polygon").data(Object.values(ret)).join("polygon").attr("points", (d) => { + const xs = d.x.map(t => xscale(t)); + const y1 = d.y.map(t => yscale(t)); + const y2 = d.y.map(t => yscale(t+d.buf.nbytes)); + const p0 = xs.map((x, i) => `${x},${y1[i]}`); + const p1 = xs.map((x, i) => `${x},${y2[i]}`).reverse(); + return `${p0.join(' ')} ${p1.join(' ')}`; + }).attr("fill", d => `#${colors[d.buf.num % colors.length]}`).on("mouseover", (e, { id, buf, x }) => { + d3.select(e.currentTarget).attr("stroke", "rgba(26, 27, 38, 0.8)").attr("stroke-width", 0.8); + const metadata = document.querySelector(".metadata"); + document.getElementById("current-buf")?.remove(); + const { num, dtype, nbytes, ...rest } = buf; + let label = `\nalive for ${pluralize(x[x.length-1]-x[0], 'timestep')}`; + label += '\n'+Object.entries(rest).map(([k, v]) => `${k}=${v}`).join('\n'); + const buf_children = children.get(id); + if (buf_children) { + label += `\n${pluralize(buf_children.length, 'child', 'children')}\n`; + label += buf_children.map((c,i) => `[${i+1}] `+graph[c.src[1]].label.split("\n")[1]).join("\n"); + } + metadata.appendChild(Object.assign(document.createElement("pre"), { innerText: label, id: "current-buf", className: "wrap" })); + }).on("mouseout", (e, _) => { + d3.select(e.currentTarget).attr("stroke", null).attr("stroke-width", null); + document.getElementById("current-buf")?.remove() + }); + // TODO: add the kernel line here + document.getElementById("zoom-to-fit-btn").click(); +} + +const ANSI_COLORS = ["#b3b3b3", "#ff6666", "#66b366", "#ffff66", "#6666ff", "#ff66ff", "#66ffff", "#ffffff"]; +const parseColors = (name) => [...name.matchAll(/(?:\u001b\[(\d+)m([\s\S]*?)\u001b\[0m)|([^\u001b]+)/g)].map(([_, code, colored_st, st]) => + ({ st: colored_st ?? st, color: code != null ? ANSI_COLORS[(parseInt(code)-30+60)%60] : "#ffffff" })); + // ** profiler graph function formatTime(ts, dur=ts) { @@ -135,306 +228,188 @@ function formatTime(ts, dur=ts) { if (dur<=1e6) return `${(ts*1e-3).toFixed(2)}ms`; return `${(ts*1e-6).toFixed(2)}s`; } -const formatUnit = (d, unit="") => d3.format(".3~s")(d)+unit; -const colorScheme = {TINY:["#1b5745", "#354f52", "#354f52", "#1d2e62", "#63b0cd"], - DEFAULT:["#2b2e39", "#2c2f3a", "#31343f", "#323544", "#2d303a", "#2e313c", "#343746", "#353847", "#3c4050", "#404459", "#444862", "#4a4e65"], - BUFFER:["#3A57B7","#5066C1","#6277CD","#7488D8","#8A9BE3","#A3B4F2"], - CATEGORICAL:["#ff8080", "#F4A261", "#C8F9D4", "#8D99AE", "#F4A261", "#ffffa2", "#ffffc0", "#87CEEB"],} -const cycleColors = (lst, i) => lst[i%lst.length]; +const colors = ["#1D1F2A", "#2A2D3D", "#373B4F", "#444862", "#12131A", "#2F3244", "#3B3F54", "#4A4E65", "#181A23", "#232532", "#313548", "#404459"]; -const rescaleTrack = (source, tid, k) => { - for (const e of source.shapes) { - for (let i=0; i { - ctx.beginPath(); - ctx.moveTo(x[0], y[0]); - ctx.lineTo(x[1], y[1]); - ctx.fillStyle = ctx.strokeStyle = "#f0f0f5"; - ctx.stroke(); -} - -var data, focusedDevice, canvasZoom, zoomLevel = d3.zoomIdentity; +var data, canvasZoom, zoomLevel = d3.zoomIdentity; async function renderProfiler() { displayGraph("profiler"); d3.select(".metadata").html(""); - // layout once! if (data != null) return; - const profiler = d3.select(".profiler").html(""); - const buf = await (await fetch("/get_profile")).arrayBuffer(); - const view = new DataView(buf); - let offset = 0; - const u8 = () => { const ret = view.getUint8(offset); offset += 1; return ret; } - const u32 = () => { const ret = view.getUint32(offset, true); offset += 4; return ret; } - const u64 = () => { const ret = new Number(view.getBigUint64(offset, true)); offset += 8; return ret; } - const f32 = () => { const ret = view.getFloat32(offset, true); offset += 4; return ret; } - const optional = (i) => i === 0 ? null : i-1; - const dur = u32(), peak = u64(), indexLen = u32(), layoutsLen = u32(); - const textDecoder = new TextDecoder("utf-8"); - const { strings, dtypeSize } = JSON.parse(textDecoder.decode(new Uint8Array(buf, offset, indexLen))); offset += indexLen; - // place devices on the y axis and set vertical positions - const [tickSize, padding] = [10, 8]; - const deviceList = profiler.append("div").attr("id", "device-list").style("padding-top", tickSize+padding+"px"); - const canvas = profiler.append("canvas").attr("id", "timeline").node(); - // NOTE: scrolling via mouse can only zoom the graph - canvas.addEventListener("wheel", e => (e.stopPropagation(), e.preventDefault()), { passive:false }); - const ctx = canvas.getContext("2d"); - const canvasTop = rect(canvas).top; - // color by key (name/device) - const colorMap = new Map(); - data = {tracks:new Map(), axes:{}}; - const heightScale = d3.scaleLinear().domain([0, peak]).range([4,maxheight=100]); - for (let i=0; i e.st >= levelEt); - const et = e.st+Math.trunc(e.dur); - if (depth === -1) { - depth = levels.length; - levels.push(et); - } else levels[depth] = et; - if (depth === 0) colorKey = e.name.split(" ")[0]; - if (!colorMap.has(colorKey)) colorMap.set(colorKey, cycleColors(colorScheme[k.split(":")[0]] ?? colorScheme.DEFAULT, colorMap.size)); - const fillColor = d3.color(colorMap.get(colorKey)).brighter(depth).toString(); - const label = parseColors(e.name).map(({ color, st }) => ({ color, st, width:ctx.measureText(st).width })); - if (e.ref != null) ref = {ctx:e.ref, step:0}; - else if (ref != null) { - const start = ref.step>0 ? ref.step+1 : 0; - const stepIdx = ctxs[ref.ctx+1].steps.findIndex((s, i) => i >= start && s.name == e.name); - ref = stepIdx === -1 ? null : {ctx:ref.ctx, step:stepIdx}; - } - const arg = { tooltipText:formatTime(e.dur)+(e.info != null ? "\n"+e.info : ""), ...ref }; - // offset y by depth - shapes.push({x:e.st, y:levelHeight*depth, width:e.dur, height:levelHeight, arg, label, fillColor }); + // fetch and process data + const { traceEvents } = await (await fetch("/get_profile")).json(); + let st, et; + const events = new Map(); + for (const e of traceEvents) { + if (e.name === "process_name") events.set(e.pid, { name:e.args.name, events:[] }); + if (e.ph === "X") { + if (st == null) [st, et] = [e.ts, e.ts+e.dur]; + else { + st = Math.min(st, e.ts); + et = Math.max(et, e.ts+e.dur); } - div.style("height", levelHeight*levels.length+padding+"px").style("pointerEvents", "none"); - } else { - const peak = u64(); - const height = heightScale(peak); - const yscale = d3.scaleLinear().domain([0, peak]).range([height, 0]); - let x = 0, y = 0; - const buf_shapes = new Map(), temp = new Map(); - const timestamps = []; - for (let j=0; j timestamps[s]); - const arg = {tooltipText:`${dtype} len:${formatUnit(sz)}\n${formatUnit(nbytes, "B")}`}; - shapes.push({ x, y0:y.map(yscale), y1:y.map(y0 => yscale(y0+nbytes)), arg, fillColor:cycleColors(colorScheme.BUFFER, shapes.length) }); - } - data.tracks.set(k, { shapes, offsetY, height, peak, scaleFactor:maxheight*4/height }); - div.style("height", height+padding+"px").style("cursor", "pointer").on("click", (e) => { - const newFocus = e.currentTarget.id === focusedDevice ? null : e.currentTarget.id; - let offset = 0; - for (const [tid, track] of data.tracks) { - track.offsetY += offset; - if (tid === newFocus) offset += rescaleTrack(track, tid, track.scaleFactor); - else if (tid === focusedDevice) offset += rescaleTrack(track, tid, 1/track.scaleFactor); - } - data.axes.y = newFocus != null ? { domain:[0, (t=data.tracks.get(newFocus)).peak], range:[t.offsetY+t.height, t.offsetY], fmt:"B" } : null; - focusedDevice = newFocus; - return resize(); - }); + events.get(e.pid).events.push(e); } } - updateProgress({ "show":false }); + const kernelMap = new Map(); + for (const [i, c] of ctxs.entries()) kernelMap.set(c.function_name, { name:c.name, i }); + // place devices on the y axis and set vertical positions + const [tickSize, padding] = [10, 8]; + const deviceList = document.getElementById("device-list"); + deviceList.style.paddingTop = `${tickSize+padding}px`; + const canvas = document.getElementById("timeline"); + const ctx = canvas.getContext("2d"); + const canvasTop = rect(canvas).top; + // color by name + const nameMap = new Map(); + data = []; + for (const [k, v] of events) { + if (v.events.length === 0) continue; + const div = deviceList.appendChild(document.createElement("div")); + div.id = `pid-${k}`; + div.innerText = v.name; + div.style.padding = `${padding}px`; + const { y:baseY, height:baseHeight } = rect(`#pid-${k}`); + // position events on the y axis, stack ones that overlap + const levels = []; + v.events.sort((a,b) => (a.ts-st) - (b.ts-st)); + const levelHeight = baseHeight-padding; + const offsetY = baseY-canvasTop+padding/2; + for (const [i,e] of v.events.entries()) { + // assign to the first free depth + const start = e.ts-st; + const end = start+e.dur; + let depth = levels.findIndex(l => start >= l); + if (depth === -1) { + depth = levels.length; + levels.push(end); + } else levels[depth] = end; + const kernel = kernelMap.get(e.name); + if (!nameMap.has(e.name)) { + const label = parseColors(kernel?.name ?? e.name).map(({ color, st }) => ({ color, st, width:ctx.measureText(st).width })); + nameMap.set(e.name, { fillColor:colors[i%colors.length], label }); + } + // offset y by depth + data.push({ x:start, dur:e.dur, name:e.name, height:levelHeight, y:offsetY+levelHeight*depth, kernel, ...nameMap.get(e.name) }); + } + // lastly, adjust device rect by number of levels + div.style.height = `${levelHeight*levels.length+padding}px`; + } // draw events on a timeline const dpr = window.devicePixelRatio || 1; const ellipsisWidth = ctx.measureText("...").width; const rectLst = []; - function render(transform) { - zoomLevel = transform; + function render(transform=null) { + if (transform != null) zoomLevel = transform; rectLst.length = 0; ctx.save(); ctx.clearRect(0, 0, canvas.clientWidth, canvas.clientHeight); - // rescale to match current zoom - const xscale = d3.scaleLinear().domain([0, dur]).range([0, canvas.clientWidth]); - xscale.domain(xscale.range().map(zoomLevel.invertX, zoomLevel).map(xscale.invert, xscale)); - const zoomDomain = transform != null ? xscale.domain() : null; - let yscale = null; - if (data.axes.y != null) { - yscale = d3.scaleLinear().domain(data.axes.y.domain).range(data.axes.y.range); - } - // draw shapes - for (const [_, { offsetY, shapes }] of data.tracks) { - for (const e of shapes) { - const [start, end] = e.width != null ? [e.x, e.x+e.width] : [e.x[0], e.x[e.x.length-1]]; - if (zoomDomain != null && (start>zoomDomain[1]|| end=0; i--) p.lineTo(x[i], offsetY+e.y1[i]); - p.closePath(); - ctx.fill(p); - // NOTE: y coordinates are in reverse order - for (let i = 0; i < x.length - 1; i++) { - let tooltipText = e.arg.tooltipText; - if (yscale != null && ((yaxisVal=yscale.invert(offsetY+e.y1[i]))>0)) { - tooltipText += `\nTotal: ${formatUnit(yaxisVal, data.axes.y.fmt)}`; - } - rectLst.push({ x0:x[i], x1:x[i+1], y0:offsetY+e.y1[i], y1:offsetY+e.y0[i], arg:{...e.arg, tooltipText} }); - } - continue; - } - // contiguous rect - const x = xscale(start); - const width = xscale(end)-x; - ctx.fillRect(x, offsetY+e.y, width, e.height); - rectLst.push({ y0:offsetY+e.y, y1:offsetY+e.y+e.height, x0:x, x1:x+width, arg:e.arg }); - // add label - if (e.label == null) continue; - ctx.textAlign = "left"; - ctx.textBaseline = "middle"; - let [labelX, labelWidth] = [x+2, 0]; - const labelY = offsetY+e.y+e.height/2; - for (const [i,l] of e.label.entries()) { - if (labelWidth+l.width+(i===e.label.length-1 ? 0 : ellipsisWidth)+2 > width) { - if (labelWidth !== 0) ctx.fillText("...", labelX, labelY); - break; - } - ctx.fillStyle = l.color; - ctx.fillText(l.st, labelX, labelY); - labelWidth += l.width; - labelX += l.width; - } - } - } - // draw axes - drawLine(ctx, xscale.range(), [0, 0]); - for (const tick of xscale.ticks()) { - // tick line - const x = xscale(tick); - drawLine(ctx, [x, x], [0, tickSize]) - // tick label + // time axis + ctx.beginPath(); + ctx.moveTo(0, 0); + ctx.lineTo(canvas.clientWidth, 0); + ctx.fillStyle = ctx.strokeStyle = "#f0f0f5"; + ctx.lineWidth = 1; + ctx.stroke(); + // xticks + const scale = d3.scaleLinear().domain([0, et-st]).range([0, canvas.clientWidth]); + scale.domain(scale.range().map(zoomLevel.invertX, zoomLevel).map(scale.invert, scale)); + const ticks = scale.ticks(); + for (const [i, tick] of ticks.entries()) { + ctx.beginPath(); + const x = (i/(ticks.length-1))*canvas.clientWidth; + ctx.moveTo(x, ctx.lineWidth); + ctx.lineTo(x, tickSize+ctx.lineWidth); + ctx.stroke(); + ctx.fontSize = "10px"; ctx.textBaseline = "top"; - ctx.textAlign = "left"; - ctx.fillText(formatTime(tick, dur), x+ctx.lineWidth+2, tickSize); + ctx.textAlign = i === ticks.length-1 ? "right" : "left"; + const padding = i === ticks.length-1 ? -1 : 1; + ctx.fillText(formatTime(tick, et-st), x+(ctx.lineWidth+2)*padding, tickSize); } - if (yscale != null) { - drawLine(ctx, [0, 0], yscale.range()); - for (const tick of yscale.ticks()) { - const y = yscale(tick); - drawLine(ctx, [0, tickSize], [y, y]); - ctx.textAlign = "left"; - ctx.textBaseline = "middle"; - ctx.fillText(formatUnit(tick, data.axes.y.fmt), tickSize+2, y); + // programs + for (const e of data) { + // zoom only changes x and width + const x = scale(e.x); + const width = scale(e.x+e.dur)-x; + ctx.fillStyle = e.fillColor; + ctx.fillRect(x, e.y, width, e.height); + rectLst.push({ y0:e.y, y1:e.y+e.height, x0:x, x1:x+width, ref:e.kernel?.i, tooltipText:formatTime(e.dur) }); + // add label + ctx.textAlign = "left"; + ctx.textBaseline = "middle"; + let [labelX, labelWidth] = [x+2, 0]; + const labelY = e.y+e.height/2; + for (const [i,l] of e.label.entries()) { + if (labelWidth+l.width+(i===e.label.length-1 ? 0 : ellipsisWidth)+2 > width) { + if (labelWidth !== 0) ctx.fillText("...", labelX, labelY); + break; + } + ctx.fillStyle = l.color; + ctx.fillText(l.st, labelX, labelY); + labelWidth += l.width; + labelX += l.width; } } ctx.restore(); } function resize() { - const profiler = document.querySelector(".profiler"); - // NOTE: use clientWidth to account for the scrollbar - let [width, height] = [profiler.clientWidth, profiler.scrollHeight]; + let { width, height } = rect(".profiler"); width -= rect("#device-list").width+padding; canvas.width = width*dpr; canvas.height = height*dpr; canvas.style.height = `${height}px`; canvas.style.width = `${width}px`; ctx.scale(dpr, dpr); - d3.select(canvas).call(canvasZoom.transform, zoomLevel); + render(); } - canvasZoom = d3.zoom().filter(vizZoomFilter).scaleExtent([1, Infinity]).translateExtent([[0,0], [Infinity,0]]).on("zoom", e => render(e.transform)); - d3.select(canvas).call(canvasZoom); - document.addEventListener("contextmenu", e => e.ctrlKey && e.preventDefault()); - resize(); window.addEventListener("resize", resize); + canvasZoom = d3.zoom().filter(e => (!e.ctrlKey || e.type === 'wheel' || e.type === 'mousedown') && !e.button) + .scaleExtent([1, Infinity]).translateExtent([[0,0], [Infinity,0]]).on("zoom", e => render(e.transform)); + d3.select(canvas).call(canvasZoom); + document.addEventListener("contextmenu", e => e.ctrlKey && e.preventDefault()); function findRectAtPosition(x, y) { const { top, left, width, height } = rect(canvas); const X = ((x-left) * (canvas.width/width))/dpr; const Y = ((y-top) * (canvas.height/height))/dpr; for (const r of rectLst) { - if (Y>=r.y0 && Y<=r.y1 && X>=r.x0 && X<=r.x1) return r.arg; + if (Y>=r.y0 && Y<=r.y1 && X>=r.x0 && X<=r.x1) return r; } } canvas.addEventListener("click", e => { e.preventDefault(); const foundRect = findRectAtPosition(e.clientX, e.clientY); - if (foundRect?.step != null) return setCtxWithHistory(foundRect.ctx, foundRect.step); + if (foundRect?.ref != null) return setCtxWithHistory(foundRect.ref); }); + const tooltip = document.body.appendChild(document.createElement("div")); + tooltip.id = "tooltip"; canvas.addEventListener("mousemove", e => { const foundRect = findRectAtPosition(e.clientX, e.clientY); if (foundRect?.tooltipText != null) { - const tooltip = document.getElementById("tooltip"); tooltip.style.display = "block"; tooltip.style.left = (e.pageX+10)+"px"; tooltip.style.top = (e.pageY)+"px"; - tooltip.innerText = foundRect.tooltipText; + tooltip.textContent = foundRect.tooltipText; } else tooltip.style.display = "none"; }); - canvas.addEventListener("mouseleave", () => document.getElementById("tooltip").style.display = "none"); + canvas.addEventListener("mouseleave", () => tooltip.style.display = "none"); } // ** zoom and recentering -const vizZoomFilter = e => (!e.ctrlKey || e.type === 'wheel' || e.type === 'mousedown') && !e.button && e.type !== 'dblclick'; -const svgZoom = d3.zoom().filter(vizZoomFilter).on("zoom", (e) => d3.select("#render").attr("transform", e.transform)); +const svgZoom = d3.zoom().on("zoom", (e) => d3.select("#render").attr("transform", e.transform)); d3.select("#graph-svg").call(svgZoom); // zoom to fit into view document.getElementById("zoom-to-fit-btn").addEventListener("click", () => { const canvas = d3.select("#timeline"); - if (!canvas.empty() && rect(canvas.node()).width !== 0) { + if (rect(canvas.node()).width !== 0) { return canvas.call(canvasZoom.transform, d3.zoomIdentity); } const svg = d3.select("#graph-svg"); @@ -453,7 +428,7 @@ document.getElementById("zoom-to-fit-btn").addEventListener("click", () => { // **** main VIZ interfacae -function codeBlock(st, language, { loc, wrap }={}) { +function codeBlock(st, language, { loc, wrap }) { const code = document.createElement("code"); code.innerHTML = hljs.highlight(st, { language }).value; code.className = "hljs"; @@ -468,19 +443,6 @@ function codeBlock(st, language, { loc, wrap }={}) { return ret; } -function appendTd(tr, value, unit=null) { - const fmt = (typeof value === "number" && !Number.isInteger(value)) ? value.toFixed(2) : value; - tr.appendChild(document.createElement("td")).innerText = unit == "us" ? formatTime(value) : fmt+(unit ?? ""); -} - -function appendRow(table, name, value, unit=null, cls="main-row") { - const tr = table.appendChild(document.createElement("tr")); - tr.className = cls; - tr.appendChild(document.createElement("td")).innerText = name; - appendTd(tr, value, unit); - return tr; -} - function setActive(e) { if (e == null) return; e.classList.add("active"); @@ -531,11 +493,12 @@ function setState(ns) { } // set a new context and keep the old one in browser history -function setCtxWithHistory(newCtx, step=0) { +function setCtxWithHistory(newCtx) { + if (newCtx == null) return; // NOTE: browser does a structured clone, passing a mutable object is safe. history.replaceState(state, ""); history.pushState(state, ""); - setState({ expandSteps:true, currentCtx:newCtx+1, currentStep:step, currentRewrite:0 }); + setState({ expandSteps:true, currentCtx:newCtx, currentStep:0, currentRewrite:0 }); } window.addEventListener("popstate", (e) => { @@ -559,7 +522,7 @@ async function main() { for (const [j,u] of steps.entries()) { const inner = ul.appendChild(document.createElement("ul")); inner.id = `step-${i}-${j}`; - inner.innerText = `${u.name ?? u.loc[0].replaceAll("\\", "/").split("/").pop()+':'+u.loc[1]}`+(u.match_count ? ` - ${u.match_count}` : ''); + inner.innerText = `${u.name ?? u.loc[0].replaceAll("\\", "/").split("/").pop()+':'+u.loc[1]} - ${u.match_count}`; inner.style.marginLeft = `${8*u.depth}px`; inner.onclick = (e) => { e.stopPropagation(); @@ -573,72 +536,23 @@ async function main() { const { currentCtx, currentStep, currentRewrite, expandSteps } = state; if (currentCtx == -1) return; const ctx = ctxs[currentCtx]; + if (ctx.name === "Profiler") return renderProfiler(); const step = ctx.steps[currentStep]; - const ckey = step?.query; + const ckey = `ctx=${currentCtx-1}&idx=${currentStep}`; // close any pending event sources let activeSrc = null; for (const e of evtSources) { - const url = new URL(e.url); - if (url.pathname+url.search !== ckey) e.close(); + if (e.url.split("?")[1] !== ckey) e.close(); else if (e.readyState === EventSource.OPEN) activeSrc = e; } - if (ctx.name === "Profiler") return renderProfiler(); if (ckey in cache) { ret = cache[ckey]; } - // ** Disassembly view - if (ckey.startsWith("/disasm")) { - if (!(ckey in cache)) cache[ckey] = ret = await (await fetch(ckey)).json(); - displayGraph("disasm"); - const root = document.createElement("div"); - root.className = "raw-text"; - const metadata = document.querySelector(".metadata"); - metadata.innerHTML = ""; - // detailed assembly view - if (ret.cols != null) { - const asm = root.appendChild(document.createElement("table")); - const thead = asm.appendChild(document.createElement("thead")); - for (const c of ret.cols) thead.appendChild(document.createElement("th")).innerText = c.title ?? c; - for (const r of ret.rows) { - const tr = asm.appendChild(document.createElement("tr")); - tr.className = "main-row code-row"; - for (const [i,value] of r.entries()) { - // string format scalar values - if (!Array.isArray(value)) appendTd(tr, value); - // display arrays in a bar graph - else { - const segmentsTd = tr.appendChild(document.createElement("td")); - segmentsTd.className = "pct-row"; - const usageBar = segmentsTd.appendChild(document.createElement("div")); - for (const [k, v, width] of value) { - const seg = usageBar.appendChild(document.createElement("div")); - seg.style.width = width+"%"; - seg.title = `${ret.cols[i].labels[k]} ${v}`; - seg.style.background = cycleColors(colorScheme.CATEGORICAL, parseInt(k)); - } - } - } - } - const summary = metadata.appendChild(document.createElement("table")); - for (const s of ret.summary) { - const tr = summary.appendChild(document.createElement("tr")); - tr.className = "main-row"; - const td = tr.appendChild(document.createElement("td")); - const div = td.appendChild(document.createElement("div")); - div.className = "legend"; - div.appendChild(document.createElement("div")).style.background = cycleColors(colorScheme.CATEGORICAL, s.idx); - div.appendChild(document.createElement("p")).textContent = s.label; - appendTd(tr, s.value); - } - } else root.appendChild(codeBlock(ret.src, "x86asm")); - return document.querySelector(".disasm").replaceChildren(root); - } - // ** UOp view (default) // if we don't have a complete cache yet we start streaming rewrites in this step if (!(ckey in cache) || (cache[ckey].length !== step.match_count+1 && activeSrc == null)) { ret = []; cache[ckey] = ret; - const eventSource = new EventSource(ckey); + const eventSource = new EventSource(`/ctxs?${ckey}`); evtSources.push(eventSource); eventSource.onmessage = (e) => { if (e.data === "END") return eventSource.close(); @@ -652,33 +566,15 @@ async function main() { }; } if (ret.length === 0) return; - renderDag(ret[currentRewrite].graph, ret[currentRewrite].changed_nodes || [], recenter=currentRewrite === 0); + if (step.name == "View Memory Graph") { + renderMemoryGraph(ret[currentRewrite].graph); + } else { + renderDag(ret[currentRewrite].graph, ret[currentRewrite].changed_nodes || [], recenter=currentRewrite === 0); + } // ** right sidebar code blocks const metadata = document.querySelector(".metadata"); - const [code, lang] = ctx.fmt != null ? [ctx.fmt, "cpp"] : [ret[currentRewrite].uop, "python"]; + const [code, lang] = ctx.kernel_code != null ? [ctx.kernel_code, "cpp"] : [ret[currentRewrite].uop, "python"]; metadata.replaceChildren(codeBlock(step.code_line, "python", { loc:step.loc, wrap:true }), codeBlock(code, lang, { wrap:false })); - if (ctx.runtime_stats != null) { - const div = metadata.appendChild(document.createElement("div")); - div.className = "stats-list"; - for (const [i, s] of ctx.runtime_stats.entries()) { - const p = div.appendChild(document.createElement("p")); - if (ctx.runtime_stats.length > 1) p.innerText = `Run ${i+1}/${ctx.runtime_stats.length}`; - const table = div.appendChild(document.createElement("table")); - const tbody = table.appendChild(document.createElement("tbody")); - for (const { name, value, unit, subunits } of s.data) { - const mainRow = appendRow(tbody, name, value, unit, "main-row"); - if (!subunits?.length) continue; - const subunitRow = tbody.appendChild(document.createElement("tr")); - subunitRow.style.display = "none"; - mainRow.onclick = () => subunitRow.style.display = subunitRow.style.display === "none" ? "table-row" : "none"; - mainRow.style.cursor = "pointer"; - const td = subunitRow.appendChild(document.createElement("td")); - td.colSpan = 2; - const table = td.appendChild(document.createElement("table")); - for (const u of subunits) appendRow(table, u.name, u.value, unit, "sub-row"); - } - } - } // ** rewrite steps if (step.match_count >= 1) { const rewriteList = metadata.appendChild(document.createElement("div")); diff --git a/tinygrad_repo/tinygrad/viz/js/worker.js b/tinygrad_repo/tinygrad/viz/js/worker.js index 5625ac7c5..94fdbb8f8 100644 --- a/tinygrad_repo/tinygrad/viz/js/worker.js +++ b/tinygrad_repo/tinygrad/viz/js/worker.js @@ -8,19 +8,22 @@ onmessage = (e) => { const { graph, additions, ctxs } = e.data; const g = new dagre.graphlib.Graph({ compound: true }); g.setGraph({ rankdir: "LR" }).setDefaultEdgeLabel(function() { return {}; }); - if (additions.length !== 0) g.setNode("addition", {label:"", className:"overlay", padding:0}); + if (additions.length !== 0) g.setNode("addition", {label:"", style:"fill: rgba(26, 27, 38, 0.5);", padding:0}); for (let [k, {label, src, ref, ...rest }] of Object.entries(graph)) { - // adjust node dims by label size (excluding escape codes) + add padding + const idx = ref ? ctxs.findIndex(k => k.ref === ref) : -1; + // replace colors in label + if (idx != -1) label += `\ncodegen@${ctxs[idx].function_name}`; + // adjust node dims by label size + add padding let [width, height] = [0, 0]; - for (line of label.replace(/\u001B\[(?:K|.*?m)/g, "").split("\n")) { + for (line of label.split("\n")) { width = Math.max(width, ctx.measureText(line).width); height += LINE_HEIGHT; } - g.setNode(k, {width:width+NODE_PADDING*2, height:height+NODE_PADDING*2, padding:NODE_PADDING, label, ref, id:k, ...rest}); + g.setNode(k, {width:width+NODE_PADDING*2, height:height+NODE_PADDING*2, padding:NODE_PADDING, label, ref:idx==-1 ? null : idx, ...rest}); // add edges const edgeCounts = {} - for (const [_, s] of src) edgeCounts[s] = (edgeCounts[s] || 0)+1; - for (const [port, s] of src) g.setEdge(s, k, { label: edgeCounts[s] > 1 ? {type:"tag", text:edgeCounts[s]} : {type:"port", text:port}}); + for (const s of src) edgeCounts[s] = (edgeCounts[s] || 0)+1; + for (const s of src) g.setEdge(s, k, { label: edgeCounts[s] > 1 ? edgeCounts[s] : null }); if (additions.includes(parseInt(k))) g.setParent(k, "addition"); } dagre.layout(g); diff --git a/tinygrad_repo/extra/perfetto/perfetto.html b/tinygrad_repo/tinygrad/viz/perfetto.html similarity index 100% rename from tinygrad_repo/extra/perfetto/perfetto.html rename to tinygrad_repo/tinygrad/viz/perfetto.html diff --git a/tinygrad_repo/tinygrad/viz/serve.py b/tinygrad_repo/tinygrad/viz/serve.py old mode 100644 new mode 100755 index 0354f6c73..46674b969 --- a/tinygrad_repo/tinygrad/viz/serve.py +++ b/tinygrad_repo/tinygrad/viz/serve.py @@ -1,48 +1,32 @@ #!/usr/bin/env python3 -import multiprocessing, pickle, difflib, os, threading, json, time, sys, webbrowser, socket, argparse, socketserver, functools, codecs, io, struct -import subprocess, ctypes, pathlib -from contextlib import redirect_stdout -from decimal import Decimal +import multiprocessing, pickle, difflib, os, threading, json, time, sys, webbrowser, socket, argparse, decimal, socketserver, functools from http.server import BaseHTTPRequestHandler from urllib.parse import parse_qs, urlparse from typing import Any, TypedDict, Generator -from tinygrad.helpers import colored, getenv, tqdm, unwrap, word_wrap, TRACEMETA, ProfileEvent, ProfileRangeEvent, TracingKey, ProfilePointEvent -from tinygrad.uop.ops import TrackedGraphRewrite, UOp, Ops, printable, GroupOp, srender, sint, sym_infer -from tinygrad.device import ProfileDeviceEvent, ProfileGraphEvent, ProfileGraphEntry, Device +from tinygrad.helpers import colored, getenv, tqdm, unwrap, word_wrap, TRACEMETA +from tinygrad.uop.ops import TrackedGraphRewrite, UOp, Ops, lines, GroupOp, srender, sint from tinygrad.renderer import ProgramSpec +from tinygrad.device import ProfileEvent, ProfileDeviceEvent, ProfileRangeEvent, ProfileGraphEvent from tinygrad.dtype import dtypes -from tinygrad.codegen.opt.kernel import axis_colors uops_colors = {Ops.LOAD: "#ffc0c0", Ops.STORE: "#87CEEB", Ops.CONST: "#e0e0e0", Ops.VCONST: "#e0e0e0", Ops.REDUCE: "#FF5B5B", - Ops.DEFINE_GLOBAL: "#ffe0b0", Ops.DEFINE_LOCAL: "#ffe0d0", Ops.DEFINE_REG: "#f0ffe0", Ops.REDUCE_AXIS: "#FF6B6B", + Ops.DEFINE_GLOBAL: "#ffe0b0", Ops.DEFINE_LOCAL: "#ffe0d0", Ops.DEFINE_ACC: "#f0ffe0", Ops.REDUCE_AXIS: "#FF6B6B", Ops.RANGE: "#c8a0e0", Ops.ASSIGN: "#909090", Ops.BARRIER: "#ff8080", Ops.IF: "#c8b0c0", Ops.SPECIAL: "#c0c0ff", Ops.INDEX: "#e8ffa0", Ops.WMMA: "#efefc0", Ops.VIEW: "#C8F9D4", Ops.MULTI: "#f6ccff", Ops.KERNEL: "#3e7f55", **{x:"#D8F9E4" for x in GroupOp.Movement}, **{x:"#ffffc0" for x in GroupOp.ALU}, Ops.THREEFRY:"#ffff80", Ops.BUFFER_VIEW: "#E5EAFF", Ops.BLOCK: "#C4A484", Ops.BLOCKEND: "#C4A4A4", Ops.BUFFER: "#B0BDFF", Ops.COPY: "#a040a0", Ops.FUSE: "#FFa500", - Ops.ALLREDUCE: "#ff40a0", Ops.MSELECT: "#d040a0", Ops.MSTACK: "#d040a0", Ops.CONTIGUOUS: "#FFC14D", - Ops.CHILDREN: "#80ffc0", Ops.CHILD: "#80fff0", Ops.BUFFERIZE: "#FF991C", Ops.REWRITE_ERROR: "#ff2e2e"} + Ops.ALLREDUCE: "#ff40a0", Ops.GBARRIER: "#FFC14D", Ops.MSELECT: "#d040a0", Ops.MSTACK: "#d040a0"} # VIZ API # ** Metadata for a track_rewrites scope -ref_map:dict[Any, int] = {} -traces:dict[int, tuple] = {} -def get_metadata(trace_bufs:list[tuple]) -> list[dict]: +def get_metadata(keys:list[Any], contexts:list[list[TrackedGraphRewrite]]) -> list[dict]: ret = [] - for keys,contexts,uop_fields in trace_bufs: - for k,v in zip(keys, contexts): - traces[i:=len(traces)] = (k, v, uop_fields) - steps = [{"name":s.name, "loc":s.loc, "depth":s.depth, "match_count":len(s.matches), "code_line":printable(s.loc), - "query":f"/ctxs?ctx={i}&idx={j}"} for j,s in enumerate(v)] - ret.append(r:={"name":k.display_name, "steps":steps}) - # use the first key to get runtime profiling data about this context - if getenv("PROFILE_VALUE") >= 2 and k.keys: r["runtime_stats"] = get_runtime_stats(k.keys[0]) - # program spec metadata - if isinstance(k.ret, ProgramSpec): - steps.append({"name":"View Disassembly", "query":f"/disasm?ctx={i}"}) - r["fmt"] = k.ret.src - for key in k.keys: ref_map[key] = i + for k,v in zip(keys, contexts): + steps = [{"name":s.name, "loc":s.loc, "depth":s.depth, "match_count":len(s.matches), "code_line":lines(s.loc[0])[s.loc[1]-1].strip()} for s in v] + if isinstance(k, ProgramSpec): ret.append({"name":k.name, "kernel_code":k.src, "ref":id(k.ast), "function_name":k.function_name, "steps":steps}) + else: ret.append({"name":str(k), "steps":steps}) return ret # ** Complete rewrite details for a graph_rewrite call @@ -63,13 +47,13 @@ def uop_to_json(x:UOp) -> dict[int, dict]: excluded: set[UOp] = set() for u in (toposort:=x.toposort()): # always exclude DEVICE/CONST/UNIQUE - if u.op in {Ops.DEVICE, Ops.CONST, Ops.UNIQUE} and u is not x: excluded.add(u) + if u.op in {Ops.DEVICE, Ops.CONST, Ops.UNIQUE}: excluded.add(u) # only exclude CONST VIEW source if it has no other children in the graph if u.op is Ops.CONST and len(u.src) != 0 and all(cr.op is Ops.CONST for c in u.src[0].children if (cr:=c()) is not None and cr in toposort): excluded.update(u.src) for u in toposort: if u in excluded: continue - argst = codecs.decode(str(u.arg), "unicode_escape") + argst = str(u.arg) if u.op is Ops.VIEW: argst = ("\n".join([f"{shape_to_str(v.shape)} / {shape_to_str(v.strides)}"+("" if v.offset == 0 else f" / {srender(v.offset)}")+ (f"\nMASK {mask_to_str(v.mask)}" if v.mask is not None else "") for v in unwrap(u.st).views])) @@ -77,169 +61,64 @@ def uop_to_json(x:UOp) -> dict[int, dict]: if u.dtype != dtypes.void: label += f"\n{u.dtype}" for idx,x in enumerate(u.src): if x in excluded: - arg = f"{x.arg:g}" if x.op is Ops.CONST and dtypes.is_float(u.dtype) else f"{x.arg}" - label += f"\n{x.op.name}{idx} {arg}" + (f" {x.src[0].op}" if len(x.src) else "") + if x.op is Ops.CONST and dtypes.is_float(u.dtype): label += f"\nCONST{idx} {x.arg:g}" + else: label += f"\n{x.op.name}{idx} {x.arg}" try: if u.op not in {Ops.VIEW, Ops.BUFFER, Ops.KERNEL, Ops.ASSIGN, Ops.COPY, Ops.SINK, *GroupOp.Buffer} and u.st is not None: label += f"\n{shape_to_str(u.shape)}" - elif len(rngs:=u.ranges): - label += f"\n({','.join([colored(str(x.arg[0]), axis_colors[x.arg[-1]]) for x in sorted(rngs, key=lambda x: x.arg[0:-1])])})" except Exception: - label += "\n" - if (ref:=ref_map.get(u.arg.ast) if u.op is Ops.KERNEL else None) is not None: label += f"\ncodegen@{ctxs[ref]['name']}" + label += "\n" # NOTE: kernel already has metadata in arg if TRACEMETA >= 2 and u.metadata is not None and u.op is not Ops.KERNEL: label += "\n"+repr(u.metadata) - graph[id(u)] = {"label":label, "src":[(i,id(x)) for i,x in enumerate(u.src) if x not in excluded], "color":uops_colors.get(u.op, "#ffffff"), - "ref":ref, "tag":u.tag} + graph[id(u)] = {"label":label, "src":[id(x) for x in u.src if x not in excluded], "color":uops_colors.get(u.op, "#ffffff"), + "ref":id(u.arg.ast) if u.op is Ops.KERNEL else None, "tag":u.tag} return graph @functools.cache -def _reconstruct(a:int, i:int): - op, dtype, src, arg, *rest = traces[i][2][a] - arg = type(arg)(_reconstruct(arg.ast, i), arg.metadata) if op is Ops.KERNEL else arg - return UOp(op, dtype, tuple(_reconstruct(s, i) for s in src), arg, *rest) +def _reconstruct(a:int): + op, dtype, src, arg, tag = contexts[2][a] + arg = type(arg)(_reconstruct(arg.ast), arg.metadata) if op is Ops.KERNEL else arg + return UOp(op, dtype, tuple(_reconstruct(s) for s in src), arg, tag) -def get_details(ctx:TrackedGraphRewrite, i:int=0) -> Generator[GraphRewriteDetails, None, None]: - yield {"graph":uop_to_json(next_sink:=_reconstruct(ctx.sink, i)), "uop":str(next_sink), "changed_nodes":None, "diff":None, "upat":None} +def get_details(ctx:TrackedGraphRewrite) -> Generator[GraphRewriteDetails, None, None]: + yield {"graph":uop_to_json(next_sink:=_reconstruct(ctx.sink)), "uop":str(next_sink), "changed_nodes":None, "diff":None, "upat":None} replaces: dict[UOp, UOp] = {} - for u0_num,u1_num,upat_loc in tqdm(ctx.matches): - replaces[u0:=_reconstruct(u0_num, i)] = u1 = _reconstruct(u1_num, i) + for u0_num,u1_num,upat in tqdm(ctx.matches): + replaces[u0:=_reconstruct(u0_num)] = u1 = _reconstruct(u1_num) try: new_sink = next_sink.substitute(replaces) - except RuntimeError as e: new_sink = UOp(Ops.NOOP, arg=str(e)) + except RecursionError as e: new_sink = UOp(Ops.NOOP, arg=str(e)) yield {"graph":(sink_json:=uop_to_json(new_sink)), "uop":str(new_sink), "changed_nodes":[id(x) for x in u1.toposort() if id(x) in sink_json], - "diff":list(difflib.unified_diff(str(u0).splitlines(), str(u1).splitlines())), "upat":(upat_loc, printable(upat_loc))} + "diff":list(difflib.unified_diff(str(u0).splitlines(), str(u1).splitlines())), "upat":(upat.location, upat.printable())} if not ctx.bottom_up: next_sink = new_sink -# encoder helpers - -def enum_str(s, cache:dict[str, int]) -> int: - if (cret:=cache.get(s)) is not None: return cret - cache[s] = ret = len(cache) - return ret - -def option(s:int|None) -> int: return 0 if s is None else s+1 - # Profiler API - -device_ts_diffs:dict[str, tuple[Decimal, Decimal]] = {} -def cpu_ts_diff(device:str, thread=0) -> Decimal: return device_ts_diffs.get(device, (Decimal(0),))[thread] - -DevEvent = ProfileRangeEvent|ProfileGraphEntry|ProfilePointEvent -def flatten_events(profile:list[ProfileEvent]) -> Generator[tuple[Decimal, Decimal, DevEvent], None, None]: - for e in profile: - if isinstance(e, ProfileRangeEvent): yield (e.st+(diff:=cpu_ts_diff(e.device, e.is_copy)), (e.en if e.en is not None else e.st)+diff, e) - elif isinstance(e, ProfilePointEvent): yield (e.ts, e.ts, e) - elif isinstance(e, ProfileGraphEvent): - cpu_ts = [] - for ent in e.ents: cpu_ts += [e.sigs[ent.st_id]+(diff:=cpu_ts_diff(ent.device, ent.is_copy)), e.sigs[ent.en_id]+diff] - yield (st:=min(cpu_ts)), (et:=max(cpu_ts)), ProfileRangeEvent(f"{e.ents[0].device.split(':')[0]} Graph", f"batched {len(e.ents)}", st, et) - for i,ent in enumerate(e.ents): yield (cpu_ts[i*2], cpu_ts[i*2+1], ent) - -# normalize event timestamps and attach kernel metadata -def timeline_layout(dev_events:list[tuple[int, int, float, DevEvent]], start_ts:int, scache:dict[str, int]) -> bytes|None: - events:list[bytes] = [] - exec_points:dict[str, dict] = {} - for st,et,dur,e in dev_events: - if isinstance(e, ProfilePointEvent) and e.name == "exec": exec_points[e.key] = e.arg - if dur == 0: continue - name, info = e.name, None - if (ref:=ref_map.get(name)) is not None: - name = ctxs[ref]["name"] - if isinstance(p:=traces[ref][0].ret, ProgramSpec) and (ei:=exec_points.get(p.name)) is not None: - info = f"{sym_infer(p.estimates.ops, ei['var_vals'])/(t:=dur*1e3):.2f} GFLOPS {sym_infer(p.estimates.mem, ei['var_vals'])/t:4.1f}"+ \ - f"|{sym_infer(p.estimates.lds,ei['var_vals'])/t:.1f} GB/s\n{ei['metadata']}" - elif isinstance(e.name, TracingKey): - name = e.name.display_name - ref = next((v for k in e.name.keys if (v:=ref_map.get(k)) is not None), None) - events.append(struct.pack(" bytes|None: - peak, mem = 0, 0 - temp:dict[int, int] = {} - events:list[bytes] = [] - for st,_,_,e in dev_events: - if not isinstance(e, ProfilePointEvent): continue - if e.name == "alloc": - events.append(struct.pack(" peak: peak = mem - if e.name == "free": - events.append(struct.pack(" bytes|None: - # start by getting the time diffs - for ev in profile: - if isinstance(ev,ProfileDeviceEvent): device_ts_diffs[ev.device] = (ev.comp_tdiff, ev.copy_tdiff if ev.copy_tdiff is not None else ev.comp_tdiff) - # map events per device - dev_events:dict[str, list[tuple[int, int, float, DevEvent]]] = {} - start_ts:int|None = None - end_ts:int|None = None - for ts,en,e in flatten_events(profile): - dev_events.setdefault(e.device,[]).append((st:=int(ts), et:=int(en), float(en-ts), e)) - if start_ts is None or st < start_ts: start_ts = st - if end_ts is None or et > end_ts: end_ts = et - if start_ts is None: return None - # return layout of per device events - layout:dict[str, bytes|None] = {} - scache:dict[str, int] = {} - peaks:list[int] = [] - dtype_size:dict[str, int] = {} - for k,v in dev_events.items(): - v.sort(key=lambda e:e[0]) - layout[k] = timeline_layout(v, start_ts, scache) - layout[f"{k} Memory"] = mem_layout(v, start_ts, unwrap(end_ts), peaks, dtype_size, scache) - ret = [b"".join([struct.pack(" list[dict]: - ret:list[dict] = [] - for e in profile: - if isinstance(e, ProfileRangeEvent) and e.en is not None and e.name == key: - ret.append({"device":e.device, "data":[{"name":"Duration", "value":float(e.en-e.st), "unit":"us"}]}) +devices:dict[str, tuple[decimal.Decimal, decimal.Decimal, int]] = {} +def prep_ts(device:str, ts:decimal.Decimal, is_copy): return int(decimal.Decimal(ts) + devices[device][is_copy]) +def dev_to_pid(device:str, is_copy=False): return {"pid": devices[device][2], "tid": int(is_copy)} +def dev_ev_to_perfetto_json(ev:ProfileDeviceEvent): + devices[ev.device] = (ev.comp_tdiff, ev.copy_tdiff if ev.copy_tdiff is not None else ev.comp_tdiff, len(devices)) + return [{"name": "process_name", "ph": "M", "pid": dev_to_pid(ev.device)['pid'], "args": {"name": ev.device}}, + {"name": "thread_name", "ph": "M", "pid": dev_to_pid(ev.device)['pid'], "tid": 0, "args": {"name": "COMPUTE"}}, + {"name": "thread_name", "ph": "M", "pid": dev_to_pid(ev.device)['pid'], "tid": 1, "args": {"name": "COPY"}}] +def range_ev_to_perfetto_json(ev:ProfileRangeEvent): + return [{"name": ev.name, "ph": "X", "ts": prep_ts(ev.device, ev.st, ev.is_copy), "dur": float(ev.en-ev.st), **dev_to_pid(ev.device, ev.is_copy)}] +def graph_ev_to_perfetto_json(ev:ProfileGraphEvent, reccnt): + ret = [] + for i,e in enumerate(ev.ents): + st, en = ev.sigs[e.st_id], ev.sigs[e.en_id] + ret += [{"name": e.name, "ph": "X", "ts": prep_ts(e.device, st, e.is_copy), "dur": float(en-st), **dev_to_pid(e.device, e.is_copy)}] + for dep in ev.deps[i]: + d = ev.ents[dep] + ret += [{"ph": "s", **dev_to_pid(d.device, d.is_copy), "id": reccnt+len(ret), "ts": prep_ts(d.device, ev.sigs[d.en_id], d.is_copy), "bp": "e"}] + ret += [{"ph": "f", **dev_to_pid(e.device, e.is_copy), "id": reccnt+len(ret)-1, "ts": prep_ts(e.device, st, e.is_copy), "bp": "e"}] return ret - -# ** Assembly analyzers - -def get_llvm_mca(asm:str, mtriple:str, mcpu:str) -> dict: - target_args = [f"-mtriple={mtriple}", f"-mcpu={mcpu}"] - # disassembly output can include headers / metadata, skip if llvm-mca can't parse those lines - data = json.loads(subprocess.check_output(["llvm-mca","-skip-unsupported-instructions=parse-failure","--json","-"]+target_args, input=asm.encode())) - cr = data["CodeRegions"][0] - resource_labels = data["TargetInfo"]["Resources"] - rows:list = [[instr] for instr in cr["Instructions"]] - # add scheduler estimates - for info in cr["InstructionInfoView"]["InstructionList"]: rows[info["Instruction"]].append(info["Latency"]) - # map per instruction resource usage - instr_usage:dict[int, dict[int, int]] = {} - for d in cr["ResourcePressureView"]["ResourcePressureInfo"]: - instr_usage.setdefault(i:=d["InstructionIndex"], {}).setdefault(r:=d["ResourceIndex"], 0) - instr_usage[i][r] += d["ResourceUsage"] - # last row is the usage summary - summary = [{"idx":k, "label":resource_labels[k], "value":v} for k,v in instr_usage.pop(len(rows), {}).items()] - max_usage = max([sum(v.values()) for i,v in instr_usage.items() if i 0 else None # ** HTTP server @@ -247,19 +126,32 @@ class Handler(BaseHTTPRequestHandler): def do_GET(self): ret, status_code, content_type = b"", 200, "text/html" - if (url:=urlparse(self.path)).path == "/": - with open(os.path.join(os.path.dirname(__file__), "index.html"), "rb") as f: ret = f.read() + if (fn:={"/":"index", "/profiler":"perfetto"}.get((url:=urlparse(self.path)).path)): + with open(os.path.join(os.path.dirname(__file__), f"{fn}.html"), "rb") as f: ret = f.read() elif self.path.startswith(("/assets/", "/js/")) and '/..' not in self.path: try: with open(os.path.join(os.path.dirname(__file__), self.path.strip('/')), "rb") as f: ret = f.read() if url.path.endswith(".js"): content_type = "application/javascript" if url.path.endswith(".css"): content_type = "text/css" except FileNotFoundError: status_code = 404 - elif (query:=parse_qs(url.query)): - if url.path == "/disasm": ret, content_type = get_disassembly(**query), "application/json" - else: return self.stream_json(get_details(traces[i:=int(query["ctx"][0])][1][int(query["idx"][0])], i)) - elif url.path == "/ctxs": ret, content_type = json.dumps(ctxs).encode(), "application/json" - elif url.path == "/get_profile" and profile_ret: ret, content_type = profile_ret, "application/octet-stream" + elif url.path == "/ctxs": + if "ctx" in (query:=parse_qs(url.query)): + kidx, ridx = int(query["ctx"][0]), int(query["idx"][0]) + try: + # stream details + self.send_response(200) + self.send_header("Content-Type", "text/event-stream") + self.send_header("Cache-Control", "no-cache") + self.end_headers() + for r in get_details(contexts[1][kidx][ridx]): + self.wfile.write(f"data: {json.dumps(r)}\n\n".encode("utf-8")) + self.wfile.flush() + self.wfile.write("data: END\n\n".encode("utf-8")) + return self.wfile.flush() + # pass if client closed connection + except (BrokenPipeError, ConnectionResetError): return + ret, content_type = json.dumps(ctxs).encode(), "application/json" + elif url.path == "/get_profile" and perfetto_profile is not None: ret, content_type = perfetto_profile, "application/json" else: status_code = 404 # send response @@ -269,19 +161,6 @@ class Handler(BaseHTTPRequestHandler): self.end_headers() return self.wfile.write(ret) - def stream_json(self, source:Generator): - try: - self.send_response(200) - self.send_header("Content-Type", "text/event-stream") - self.send_header("Cache-Control", "no-cache") - self.end_headers() - for r in source: - self.wfile.write(f"data: {json.dumps(r)}\n\n".encode("utf-8")) - self.wfile.flush() - self.wfile.write("data: END\n\n".encode("utf-8")) - # pass if client closed connection - except (BrokenPipeError, ConnectionResetError): return - # ** main loop def reloader(): @@ -292,17 +171,17 @@ def reloader(): os.execv(sys.executable, [sys.executable] + sys.argv) time.sleep(0.1) -def load_pickle(path:pathlib.Path|None) -> list: - if path is None or not path.exists(): return [] - with path.open("rb") as f: return pickle.load(f) +def load_pickle(path:str): + if path is None or not os.path.exists(path): return None + with open(path, "rb") as f: return pickle.load(f) # NOTE: using HTTPServer forces a potentially slow socket.getfqdn class TCPServerWithReuse(socketserver.TCPServer): allow_reuse_address = True if __name__ == "__main__": parser = argparse.ArgumentParser() - parser.add_argument('--kernels', type=pathlib.Path, help='Path to kernels', default=None) - parser.add_argument('--profile', type=pathlib.Path, help='Path profile', default=None) + parser.add_argument('--kernels', type=str, help='Path to kernels', default=None) + parser.add_argument('--profile', type=str, help='Path profile', default=None) args = parser.parse_args() with socket.socket(socket.AF_INET, socket.SOCK_STREAM) as s: @@ -313,16 +192,19 @@ if __name__ == "__main__": st = time.perf_counter() print("*** viz is starting") - ctxs = get_metadata(load_pickle(args.kernels)) + contexts, profile = load_pickle(args.kernels), load_pickle(args.profile) - profile_ret = get_profile(profile:=load_pickle(args.profile)) + # NOTE: this context is a tuple of list[keys] and list[values] + ctxs = get_metadata(*contexts[:2]) if contexts is not None else [] + + perfetto_profile = to_perfetto(profile) if profile is not None else None server = TCPServerWithReuse(('', PORT), Handler) reloader_thread = threading.Thread(target=reloader) reloader_thread.start() print(f"*** started viz on {HOST}:{PORT}") print(colored(f"*** ready in {(time.perf_counter()-st)*1e3:4.2f}ms", "green"), flush=True) - if len(getenv("BROWSER", "")) > 0: webbrowser.open(f"{HOST}:{PORT}") + if len(getenv("BROWSER", "")) > 0: webbrowser.open(f"{HOST}:{PORT}{'/profiler' if contexts is None else ''}") try: server.serve_forever() except KeyboardInterrupt: print("*** viz is shutting down...")

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